From d65bf6c15a506c2ab4b723a292714f5abdccb343 Mon Sep 17 00:00:00 2001 From: nobody <> Date: Sat, 13 Dec 2003 20:12:33 +0000 Subject: This commit was manufactured by cvs2svn to create branch 'drow-cplus- branch'. Cherrypick from master 2003-12-13 20:12:31 UTC Jim Blandy '* gdb.base/freebpcmd.exp, gdb.base/freebpcmd.c: New test.': COPYING.LIBGLOSS bfd/bfdio.c bfd/bfdwin.c bfd/cpu-iq2000.c bfd/cpu-msp430.c bfd/cpu-xtensa.c bfd/doc/fdl.texi bfd/elf32-am33lin.c bfd/elf32-iq2000.c bfd/elf32-m68hc1x.c bfd/elf32-m68hc1x.h bfd/elf32-msp430.c bfd/elf32-ppc.h bfd/elf32-sh64.h bfd/elf32-xtensa.c bfd/mach-o-target.c bfd/mach-o.c bfd/mach-o.h bfd/pef-traceback.h bfd/pef.c bfd/pef.h bfd/po/ro.po bfd/po/zh_CN.po bfd/xsym.c bfd/xsym.h bfd/xtensa-isa.c bfd/xtensa-modules.c config/accross.m4 config/acx.m4 config/gettext.m4 config/no-executables.m4 config/progtest.m4 cpu/ChangeLog cpu/frv.cpu cpu/frv.opc cpu/iq10.cpu cpu/iq2000.cpu cpu/iq2000.opc cpu/iq2000m.cpu cpu/simplify.inc gdb/ChangeLog-2002 gdb/alpha-mdebug-tdep.c gdb/amd64-nat.c gdb/amd64-nat.h gdb/amd64bsd-nat.c gdb/amd64fbsd-nat.c gdb/amd64fbsd-tdep.c gdb/amd64nbsd-nat.c gdb/amd64nbsd-tdep.c gdb/bfd-target.c gdb/bfd-target.h gdb/block.c gdb/block.h gdb/cli/cli-interp.c gdb/cli/cli-logging.c gdb/coff-pe-read.c gdb/coff-pe-read.h gdb/config/arm/tm-nbsd.h gdb/config/i386/fbsd64.mh gdb/config/i386/fbsd64.mt gdb/config/i386/interix.mh gdb/config/i386/interix.mt gdb/config/i386/nbsd64.mh gdb/config/i386/nbsd64.mt gdb/config/i386/nm-fbsd64.h gdb/config/i386/nm-interix.h gdb/config/i386/nm-nto.h gdb/config/i386/nto.mh gdb/config/i386/nto.mt gdb/config/i386/tm-nto.h gdb/config/powerpc/nm-ppc64-linux.h gdb/config/powerpc/ppc64-linux.mh gdb/config/tm-nto.h gdb/cp-namespace.c gdb/dictionary.c gdb/dictionary.h gdb/doc/annotate.texinfo gdb/doc/observer.texi gdb/dummy-frame.c gdb/dummy-frame.h gdb/dwarf2-frame.c gdb/dwarf2-frame.h gdb/dwarf2expr.c gdb/dwarf2expr.h gdb/dwarf2loc.c gdb/dwarf2loc.h gdb/exec.h gdb/frame-base.c gdb/frame-base.h gdb/frame-unwind.c gdb/frame-unwind.h gdb/gdb_gcore.sh gdb/glibc-tdep.c gdb/glibc-tdep.h gdb/hppa-hpux-tdep.c gdb/hppa-tdep.h gdb/i386-cygwin-tdep.c gdb/i386-interix-nat.c gdb/i386-interix-tdep.c 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The name of the +University may not be used to endorse or promote products derived +from this software without specific prior written permission. +THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR +IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. + +[1b] + +Copyright (c) 1991, 2000 The Regents of the University of California. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. +3. All advertising materials mentioning features or use of this software + must display the following acknowledgement: + This product includes software developed by the University of + California, Berkeley and its contributors. +4. Neither the name of the University nor the names of its contributors + may be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +[1c] + +Copyright (c) 1991, 1998, 2001 The Regents of the University of California. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. +3. [rescinded 22 July 1999] +4. Neither the name of the University nor the names of its contributors + may be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +------------------------------------------------------------- + Please note that in some of the above alternate licenses, there is a + statement regarding that acknowledgement must be made in any + advertising materials for products using the code. This restriction + no longer applies due to the following license change: + + ftp://ftp.cs.berkeley.edu/pub/4bsd/README.Impt.License.Change + + In some cases the defunct clause has been removed in modified newlib code and + in some cases, the clause has been left as-is. +------------------------------------------------------------- + +(2) DJ Delorie + +Copyright (C) 1993 DJ Delorie +All rights reserved. + +Redistribution and use in source and binary forms is permitted +provided that the above copyright notice and following paragraph are +duplicated in all such forms. + +This file is distributed WITHOUT ANY WARRANTY; without even the implied +warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + +(3) GPL (fr30 directory only) + +Copyright (C) 1998 Free Software Foundation, Inc. +Contributed by Cygnus Solutions. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. + +(4) Advanced Micro Devices + +Copyright 1989, 1990 Advanced Micro Devices, Inc. + +This software is the property of Advanced Micro Devices, Inc (AMD) which +specifically grants the user the right to modify, use and distribute this +software provided this notice is not removed or altered. All other rights +are reserved by AMD. + +AMD MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS +SOFTWARE. IN NO EVENT SHALL AMD BE LIABLE FOR INCIDENTAL OR CONSEQUENTIAL +DAMAGES IN CONNECTION WITH OR ARISING FROM THE FURNISHING, PERFORMANCE, OR +USE OF THIS SOFTWARE. + +So that all may benefit from your experience, please report any problems +or suggestions about this software to the 29K Technical Support Center at +800-29-29-AMD (800-292-9263) in the USA, or 0800-89-1131 in the UK, or +0031-11-1129 in Japan, toll free. The direct dial number is 512-462-4118. + +Advanced Micro Devices, Inc. +29K Support Products +Mail Stop 573 +5900 E. Ben White Blvd. +Austin, TX 78741 +800-292-9263 + +(5) Array Technology Corporation and MIPS (mips/lsi33k-stub.h) + +COPYRIGHT (C) 1991, 1992 ARRAY TECHNOLOGY CORPORATION + All Rights Reserved + +This software is confidential information which is proprietary to and +a trade secret of ARRAY Technology Corporation. Use, duplication, or +disclosure is subject to the terms of a separate license agreement. + +Copyright 1985 by MIPS Computer Systems, Inc. + +(6) University of Utah and the Computer Systems Laboratory (CSL) + [applies only to hppa*-*-pro* targets] + +Copyright (c) 1990,1994 The University of Utah and +the Computer Systems Laboratory (CSL). All rights reserved. + +Permission to use, copy, modify and distribute this software is hereby +granted provided that (1) source code retains these copyright, permission, +and disclaimer notices, and (2) redistributions including binaries +reproduce the notices in supporting documentation, and (3) all advertising +materials mentioning features or use of this software display the following +acknowledgement: ``This product includes software developed by the +Computer Systems Laboratory at the University of Utah.'' + +THE UNIVERSITY OF UTAH AND CSL ALLOW FREE USE OF THIS SOFTWARE IN ITS "AS +IS" CONDITION. THE UNIVERSITY OF UTAH AND CSL DISCLAIM ANY LIABILITY OF +ANY KIND FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. + +CSL requests users of this software to return to csl-dist@cs.utah.edu any +improvements that they make and grant CSL redistribution rights. + +(7) Sun Microsystems + +Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved. + +Developed at SunPro, a Sun Microsystems, Inc. business. +Permission to use, copy, modify, and distribute this +software is freely granted, provided that this notice +is preserved. + +(8) Hewlett Packard + +(c) Copyright 1986 HEWLETT-PACKARD COMPANY + +To anyone who acknowledges that this file is provided "AS IS" +without any express or implied warranty: + permission to use, copy, modify, and distribute this file +for any purpose is hereby granted without fee, provided that +the above copyright notice and this notice appears in all +copies, and that the name of Hewlett-Packard Company not be +used in advertising or publicity pertaining to distribution +of the software without specific, written prior permission. +Hewlett-Packard Company makes no representations about the +suitability of this software for any purpose. + +(9) Hans-Peter Nilsson + +Copyright (C) 2001 Hans-Peter Nilsson + +Permission to use, copy, modify, and distribute this software is +freely granted, provided that the above copyright notice, this notice +and the following disclaimer are preserved with no changes. + +THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR +IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +PURPOSE. + +(10) No Copyright + +THIS SOFTWARE IS NOT COPYRIGHTED + +(11) Cygnus Support / Cygnus Solutions + +Copyright (c) 1995, 1996, 1997, 1998, 1999 Cygnus Support + +The authors hereby grant permission to use, copy, modify, distribute, +and license this software and its documentation for any purpose, provided +that existing copyright notices are retained in all copies and that this +notice is included verbatim in any distributions. No written agreement, +license, or royalty fee is required for any of the authorized uses. +Modifications to this software may be copyrighted by their authors +and need not follow the licensing terms described here, provided that +the new terms are clearly indicated on the first page of each file where +they apply. + +--------------------------------------------------------------- + Please note that the copyright above may be used with the name + Cygnus Solutions instead of Cygnus Support. Both names should + be considered interchangeable. These copyrights are now owned + by Red Hat Incorporated. +--------------------------------------------------------------- + +(12) Red Hat Incorporated + +Copyright (c) 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. + +The authors hereby grant permission to use, copy, modify, distribute, +and license this software and its documentation for any purpose, provided +that existing copyright notices are retained in all copies and that this +notice is included verbatim in any distributions. No written agreement, +license, or royalty fee is required for any of the authorized uses. +Modifications to this software may be copyrighted by their authors +and need not follow the licensing terms described here, provided that +the new terms are clearly indicated on the first page of each file where +they apply. + +(13) Default copyright + +Unless otherwise stated in each remaining libgloss file, the remaining +files in the libgloss subdirectory are governed by the following copyright. + +Copyright (c) 1994, 1997, 2001, 2002 Red Hat Incorporated. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + The name of Red Hat Incorporated may not be used to endorse + or promote products derived from this software without specific + prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. diff --git a/bfd/bfdio.c b/bfd/bfdio.c new file mode 100644 index 0000000..b196a52 --- /dev/null +++ b/bfd/bfdio.c @@ -0,0 +1,416 @@ +/* Low-level I/O routines for BFDs. + Copyright 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, + 2000, 2001, 2002, 2003 Free Software Foundation, Inc. + Written by Cygnus Support. + +This file is part of BFD, the Binary File Descriptor library. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include "sysdep.h" + +#include "bfd.h" +#include "libbfd.h" + +#include + +#ifndef S_IXUSR +#define S_IXUSR 0100 /* Execute by owner. */ +#endif +#ifndef S_IXGRP +#define S_IXGRP 0010 /* Execute by group. */ +#endif +#ifndef S_IXOTH +#define S_IXOTH 0001 /* Execute by others. */ +#endif + +/* Note that archive entries don't have streams; they share their parent's. + This allows someone to play with the iostream behind BFD's back. + + Also, note that the origin pointer points to the beginning of a file's + contents (0 for non-archive elements). For archive entries this is the + first octet in the file, NOT the beginning of the archive header. */ + +static size_t +real_read (void *where, size_t a, size_t b, FILE *file) +{ + /* FIXME - this looks like an optimization, but it's really to cover + up for a feature of some OSs (not solaris - sigh) that + ld/pe-dll.c takes advantage of (apparently) when it creates BFDs + internally and tries to link against them. BFD seems to be smart + enough to realize there are no symbol records in the "file" that + doesn't exist but attempts to read them anyway. On Solaris, + attempting to read zero bytes from a NULL file results in a core + dump, but on other platforms it just returns zero bytes read. + This makes it to something reasonable. - DJ */ + if (a == 0 || b == 0) + return 0; + + +#if defined (__VAX) && defined (VMS) + /* Apparently fread on Vax VMS does not keep the record length + information. */ + return read (fileno (file), where, a * b); +#else + return fread (where, a, b, file); +#endif +} + +/* Return value is amount read. */ + +bfd_size_type +bfd_bread (void *ptr, bfd_size_type size, bfd *abfd) +{ + size_t nread; + + if ((abfd->flags & BFD_IN_MEMORY) != 0) + { + struct bfd_in_memory *bim; + bfd_size_type get; + + bim = abfd->iostream; + get = size; + if (abfd->where + get > bim->size) + { + if (bim->size < (bfd_size_type) abfd->where) + get = 0; + else + get = bim->size - abfd->where; + bfd_set_error (bfd_error_file_truncated); + } + memcpy (ptr, bim->buffer + abfd->where, (size_t) get); + abfd->where += get; + return get; + } + + nread = real_read (ptr, 1, (size_t) size, bfd_cache_lookup (abfd)); + if (nread != (size_t) -1) + abfd->where += nread; + + /* Set bfd_error if we did not read as much data as we expected. + + If the read failed due to an error set the bfd_error_system_call, + else set bfd_error_file_truncated. + + A BFD backend may wish to override bfd_error_file_truncated to + provide something more useful (eg. no_symbols or wrong_format). */ + if (nread != size) + { + if (ferror (bfd_cache_lookup (abfd))) + bfd_set_error (bfd_error_system_call); + else + bfd_set_error (bfd_error_file_truncated); + } + + return nread; +} + +bfd_size_type +bfd_bwrite (const void *ptr, bfd_size_type size, bfd *abfd) +{ + size_t nwrote; + + if ((abfd->flags & BFD_IN_MEMORY) != 0) + { + struct bfd_in_memory *bim = abfd->iostream; + size = (size_t) size; + if (abfd->where + size > bim->size) + { + bfd_size_type newsize, oldsize; + + oldsize = (bim->size + 127) & ~(bfd_size_type) 127; + bim->size = abfd->where + size; + /* Round up to cut down on memory fragmentation */ + newsize = (bim->size + 127) & ~(bfd_size_type) 127; + if (newsize > oldsize) + { + bim->buffer = bfd_realloc (bim->buffer, newsize); + if (bim->buffer == 0) + { + bim->size = 0; + return 0; + } + } + } + memcpy (bim->buffer + abfd->where, ptr, (size_t) size); + abfd->where += size; + return size; + } + + nwrote = fwrite (ptr, 1, (size_t) size, bfd_cache_lookup (abfd)); + if (nwrote != (size_t) -1) + abfd->where += nwrote; + if (nwrote != size) + { +#ifdef ENOSPC + errno = ENOSPC; +#endif + bfd_set_error (bfd_error_system_call); + } + return nwrote; +} + +bfd_vma +bfd_tell (bfd *abfd) +{ + file_ptr ptr; + + if ((abfd->flags & BFD_IN_MEMORY) != 0) + return abfd->where; + + ptr = ftell (bfd_cache_lookup (abfd)); + + if (abfd->my_archive) + ptr -= abfd->origin; + abfd->where = ptr; + return ptr; +} + +int +bfd_flush (bfd *abfd) +{ + if ((abfd->flags & BFD_IN_MEMORY) != 0) + return 0; + return fflush (bfd_cache_lookup(abfd)); +} + +/* Returns 0 for success, negative value for failure (in which case + bfd_get_error can retrieve the error code). */ +int +bfd_stat (bfd *abfd, struct stat *statbuf) +{ + FILE *f; + int result; + + if ((abfd->flags & BFD_IN_MEMORY) != 0) + abort (); + + f = bfd_cache_lookup (abfd); + if (f == NULL) + { + bfd_set_error (bfd_error_system_call); + return -1; + } + result = fstat (fileno (f), statbuf); + if (result < 0) + bfd_set_error (bfd_error_system_call); + return result; +} + +/* Returns 0 for success, nonzero for failure (in which case bfd_get_error + can retrieve the error code). */ + +int +bfd_seek (bfd *abfd, file_ptr position, int direction) +{ + int result; + FILE *f; + long file_position; + /* For the time being, a BFD may not seek to it's end. The problem + is that we don't easily have a way to recognize the end of an + element in an archive. */ + + BFD_ASSERT (direction == SEEK_SET || direction == SEEK_CUR); + + if (direction == SEEK_CUR && position == 0) + return 0; + + if ((abfd->flags & BFD_IN_MEMORY) != 0) + { + struct bfd_in_memory *bim; + + bim = abfd->iostream; + + if (direction == SEEK_SET) + abfd->where = position; + else + abfd->where += position; + + if (abfd->where > bim->size) + { + if ((abfd->direction == write_direction) || + (abfd->direction == both_direction)) + { + bfd_size_type newsize, oldsize; + oldsize = (bim->size + 127) & ~(bfd_size_type) 127; + bim->size = abfd->where; + /* Round up to cut down on memory fragmentation */ + newsize = (bim->size + 127) & ~(bfd_size_type) 127; + if (newsize > oldsize) + { + bim->buffer = bfd_realloc (bim->buffer, newsize); + if (bim->buffer == 0) + { + bim->size = 0; + return -1; + } + } + } + else + { + abfd->where = bim->size; + bfd_set_error (bfd_error_file_truncated); + return -1; + } + } + return 0; + } + + if (abfd->format != bfd_archive && abfd->my_archive == 0) + { +#if 0 + /* Explanation for this code: I'm only about 95+% sure that the above + conditions are sufficient and that all i/o calls are properly + adjusting the `where' field. So this is sort of an `assert' + that the `where' field is correct. If we can go a while without + tripping the abort, we can probably safely disable this code, + so that the real optimizations happen. */ + file_ptr where_am_i_now; + where_am_i_now = ftell (bfd_cache_lookup (abfd)); + if (abfd->my_archive) + where_am_i_now -= abfd->origin; + if (where_am_i_now != abfd->where) + abort (); +#endif + if (direction == SEEK_SET && (bfd_vma) position == abfd->where) + return 0; + } + else + { + /* We need something smarter to optimize access to archives. + Currently, anything inside an archive is read via the file + handle for the archive. Which means that a bfd_seek on one + component affects the `current position' in the archive, as + well as in any other component. + + It might be sufficient to put a spike through the cache + abstraction, and look to the archive for the file position, + but I think we should try for something cleaner. + + In the meantime, no optimization for archives. */ + } + + f = bfd_cache_lookup (abfd); + file_position = position; + if (direction == SEEK_SET && abfd->my_archive != NULL) + file_position += abfd->origin; + + result = fseek (f, file_position, direction); + if (result != 0) + { + int hold_errno = errno; + + /* Force redetermination of `where' field. */ + bfd_tell (abfd); + + /* An EINVAL error probably means that the file offset was + absurd. */ + if (hold_errno == EINVAL) + bfd_set_error (bfd_error_file_truncated); + else + { + bfd_set_error (bfd_error_system_call); + errno = hold_errno; + } + } + else + { + /* Adjust `where' field. */ + if (direction == SEEK_SET) + abfd->where = position; + else + abfd->where += position; + } + return result; +} + +/* +FUNCTION + bfd_get_mtime + +SYNOPSIS + long bfd_get_mtime (bfd *abfd); + +DESCRIPTION + Return the file modification time (as read from the file system, or + from the archive header for archive members). + +*/ + +long +bfd_get_mtime (bfd *abfd) +{ + FILE *fp; + struct stat buf; + + if (abfd->mtime_set) + return abfd->mtime; + + fp = bfd_cache_lookup (abfd); + if (0 != fstat (fileno (fp), &buf)) + return 0; + + abfd->mtime = buf.st_mtime; /* Save value in case anyone wants it */ + return buf.st_mtime; +} + +/* +FUNCTION + bfd_get_size + +SYNOPSIS + long bfd_get_size (bfd *abfd); + +DESCRIPTION + Return the file size (as read from file system) for the file + associated with BFD @var{abfd}. + + The initial motivation for, and use of, this routine is not + so we can get the exact size of the object the BFD applies to, since + that might not be generally possible (archive members for example). + It would be ideal if someone could eventually modify + it so that such results were guaranteed. + + Instead, we want to ask questions like "is this NNN byte sized + object I'm about to try read from file offset YYY reasonable?" + As as example of where we might do this, some object formats + use string tables for which the first <> bytes of the + table contain the size of the table itself, including the size bytes. + If an application tries to read what it thinks is one of these + string tables, without some way to validate the size, and for + some reason the size is wrong (byte swapping error, wrong location + for the string table, etc.), the only clue is likely to be a read + error when it tries to read the table, or a "virtual memory + exhausted" error when it tries to allocate 15 bazillon bytes + of space for the 15 bazillon byte table it is about to read. + This function at least allows us to answer the question, "is the + size reasonable?". +*/ + +long +bfd_get_size (bfd *abfd) +{ + FILE *fp; + struct stat buf; + + if ((abfd->flags & BFD_IN_MEMORY) != 0) + return ((struct bfd_in_memory *) abfd->iostream)->size; + + fp = bfd_cache_lookup (abfd); + if (0 != fstat (fileno (fp), & buf)) + return 0; + + return buf.st_size; +} diff --git a/bfd/bfdwin.c b/bfd/bfdwin.c new file mode 100644 index 0000000..fb7c967 --- /dev/null +++ b/bfd/bfdwin.c @@ -0,0 +1,251 @@ +/* Support for memory-mapped windows into a BFD. + Copyright 1995, 1996, 2001, 2002, 2003 Free Software Foundation, Inc. + Written by Cygnus Support. + +This file is part of BFD, the Binary File Descriptor library. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include "sysdep.h" + +#include "bfd.h" +#include "libbfd.h" + +/* Currently, if USE_MMAP is undefined, none if the window stuff is + used. Okay, so it's mis-named. At least the command-line option + "--without-mmap" is more obvious than "--without-windows" or some + such. */ + +#ifdef USE_MMAP + +#undef HAVE_MPROTECT /* code's not tested yet */ + +#if HAVE_MMAP || HAVE_MPROTECT || HAVE_MADVISE +#include +#endif + +#ifndef MAP_FILE +#define MAP_FILE 0 +#endif + +static int debug_windows; + +/* The idea behind the next and refcount fields is that one mapped + region can suffice for multiple read-only windows or multiple + non-overlapping read-write windows. It's not implemented yet + though. */ + +/* +INTERNAL_DEFINITION + +.struct _bfd_window_internal { +. struct _bfd_window_internal *next; +. void *data; +. bfd_size_type size; +. int refcount : 31; {* should be enough... *} +. unsigned mapped : 1; {* 1 = mmap, 0 = malloc *} +.}; +*/ + +void +bfd_init_window (bfd_window *windowp) +{ + windowp->data = 0; + windowp->i = 0; + windowp->size = 0; +} + +void +bfd_free_window (bfd_window *windowp) +{ + bfd_window_internal *i = windowp->i; + windowp->i = 0; + windowp->data = 0; + if (i == 0) + return; + i->refcount--; + if (debug_windows) + fprintf (stderr, "freeing window @%p<%p,%lx,%p>\n", + windowp, windowp->data, windowp->size, windowp->i); + if (i->refcount != 0) + return; + + if (i->mapped) + { +#ifdef HAVE_MMAP + munmap (i->data, i->size); + goto no_free; +#else + abort (); +#endif + } +#ifdef HAVE_MPROTECT + mprotect (i->data, i->size, PROT_READ | PROT_WRITE); +#endif + free (i->data); +#ifdef HAVE_MMAP + no_free: +#endif + i->data = 0; + /* There should be no more references to i at this point. */ + free (i); +} + +static int ok_to_map = 1; + +bfd_boolean +bfd_get_file_window (bfd *abfd, + file_ptr offset, + bfd_size_type size, + bfd_window *windowp, + bfd_boolean writable) +{ + static size_t pagesize; + bfd_window_internal *i = windowp->i; + bfd_size_type size_to_alloc = size; + + if (debug_windows) + fprintf (stderr, "bfd_get_file_window (%p, %6ld, %6ld, %p<%p,%lx,%p>, %d)", + abfd, (long) offset, (long) size, + windowp, windowp->data, (unsigned long) windowp->size, + windowp->i, writable); + + /* Make sure we know the page size, so we can be friendly to mmap. */ + if (pagesize == 0) + pagesize = getpagesize (); + if (pagesize == 0) + abort (); + + if (i == 0) + { + i = bfd_zmalloc (sizeof (bfd_window_internal)); + windowp->i = i; + if (i == 0) + return FALSE; + i->data = 0; + } +#ifdef HAVE_MMAP + if (ok_to_map + && (i->data == 0 || i->mapped == 1) + && (abfd->flags & BFD_IN_MEMORY) == 0) + { + file_ptr file_offset, offset2; + size_t real_size; + int fd; + FILE *f; + + /* Find the real file and the real offset into it. */ + while (abfd->my_archive != NULL) + { + offset += abfd->origin; + abfd = abfd->my_archive; + } + f = bfd_cache_lookup (abfd); + fd = fileno (f); + + /* Compute offsets and size for mmap and for the user's data. */ + offset2 = offset % pagesize; + if (offset2 < 0) + abort (); + file_offset = offset - offset2; + real_size = offset + size - file_offset; + real_size = real_size + pagesize - 1; + real_size -= real_size % pagesize; + + /* If we're re-using a memory region, make sure it's big enough. */ + if (i->data && i->size < size) + { + munmap (i->data, i->size); + i->data = 0; + } + i->data = mmap (i->data, real_size, + writable ? PROT_WRITE | PROT_READ : PROT_READ, + (writable + ? MAP_FILE | MAP_PRIVATE + : MAP_FILE | MAP_SHARED), + fd, file_offset); + if (i->data == (void *) -1) + { + /* An error happened. Report it, or try using malloc, or + something. */ + bfd_set_error (bfd_error_system_call); + i->data = 0; + windowp->data = 0; + if (debug_windows) + fprintf (stderr, "\t\tmmap failed!\n"); + return FALSE; + } + if (debug_windows) + fprintf (stderr, "\n\tmapped %ld at %p, offset is %ld\n", + (long) real_size, i->data, (long) offset2); + i->size = real_size; + windowp->data = (bfd_byte *) i->data + offset2; + windowp->size = size; + i->mapped = 1; + return TRUE; + } + else if (debug_windows) + { + if (ok_to_map) + fprintf (stderr, _("not mapping: data=%lx mapped=%d\n"), + (unsigned long) i->data, (int) i->mapped); + else + fprintf (stderr, _("not mapping: env var not set\n")); + } +#else + ok_to_map = 0; +#endif + +#ifdef HAVE_MPROTECT + if (!writable) + { + size_to_alloc += pagesize - 1; + size_to_alloc -= size_to_alloc % pagesize; + } +#endif + if (debug_windows) + fprintf (stderr, "\n\t%s(%6ld)", + i->data ? "realloc" : " malloc", (long) size_to_alloc); + i->data = bfd_realloc (i->data, size_to_alloc); + if (debug_windows) + fprintf (stderr, "\t-> %p\n", i->data); + i->refcount = 1; + if (i->data == NULL) + { + if (size_to_alloc == 0) + return TRUE; + return FALSE; + } + if (bfd_seek (abfd, offset, SEEK_SET) != 0) + return FALSE; + i->size = bfd_bread (i->data, size, abfd); + if (i->size != size) + return FALSE; + i->mapped = 0; +#ifdef HAVE_MPROTECT + if (!writable) + { + if (debug_windows) + fprintf (stderr, "\tmprotect (%p, %ld, PROT_READ)\n", i->data, + (long) i->size); + mprotect (i->data, i->size, PROT_READ); + } +#endif + windowp->data = i->data; + windowp->size = i->size; + return TRUE; +} + +#endif /* USE_MMAP */ diff --git a/bfd/cpu-iq2000.c b/bfd/cpu-iq2000.c new file mode 100644 index 0000000..4545f30 --- /dev/null +++ b/bfd/cpu-iq2000.c @@ -0,0 +1,56 @@ +/* BFD support for the Vitesse IQ2000 processor. + Copyright (C) 2003 Free Software Foundation, Inc. + +This file is part of BFD, the Binary File Descriptor library. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include "bfd.h" +#include "sysdep.h" +#include "libbfd.h" + +static const bfd_arch_info_type arch_info_struct[] = +{ + { + 32, /* bits per word */ + 32, /* bits per address */ + 8, /* bits per byte */ + bfd_arch_iq2000, /* architecture */ + bfd_mach_iq10, /* machine */ + "iq2000", /* architecture name */ + "iq10", /* printable name */ + 3, /* section align power */ + FALSE, /* the default ? */ + bfd_default_compatible, /* architecture comparison fn */ + bfd_default_scan, /* string to architecture convert fn */ + NULL /* next in list */ + } +}; + +const bfd_arch_info_type bfd_iq2000_arch = +{ + 32, /* bits per word */ + 32, /* bits per address */ + 8, /* bits per byte */ + bfd_arch_iq2000, /* architecture */ + bfd_mach_iq2000, /* machine */ + "iq2000", /* architecture name */ + "iq2000", /* printable name */ + 3, /* section align power */ + TRUE, /* the default ? */ + bfd_default_compatible, /* architecture comparison fn */ + bfd_default_scan, /* string to architecture convert fn */ + &arch_info_struct[0], /* next in list */ +}; diff --git a/bfd/cpu-msp430.c b/bfd/cpu-msp430.c new file mode 100644 index 0000000..519131c --- /dev/null +++ b/bfd/cpu-msp430.c @@ -0,0 +1,109 @@ +/* BFD library support routines for the MSP architecture. + Copyright (C) 2002, 2003 Free Software Foundation, Inc. + Contributed by Dmitry Diky + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include "bfd.h" +#include "sysdep.h" +#include "libbfd.h" + +static const bfd_arch_info_type *compatible + PARAMS ((const bfd_arch_info_type *, const bfd_arch_info_type *)); + +#define N(addr_bits, machine, print, default, next) \ +{ \ + 16, /* 16 bits in a word. */ \ + addr_bits, /* Bits in an address. */ \ + 8, /* 8 bits in a byte. */ \ + bfd_arch_msp430, \ + machine, /* Machine number. */ \ + "msp430", /* Architecture name. */ \ + print, /* Printable name. */ \ + 1, /* Section align power. */ \ + default, /* The default machine. */ \ + compatible, \ + bfd_default_scan, \ + next \ +} + +static const bfd_arch_info_type arch_info_struct[] = +{ + /* msp430x11x. */ + N (16, bfd_mach_msp11, "msp:11", FALSE, & arch_info_struct[1]), + + /* msp430x11x1. */ + N (16, bfd_mach_msp110, "msp:110", FALSE, & arch_info_struct[2]), + + /* msp430x12x. */ + N (16, bfd_mach_msp12, "msp:12", FALSE, & arch_info_struct[3]), + + /* msp430x13x. */ + N (16, bfd_mach_msp13, "msp:13", FALSE, & arch_info_struct[4]), + + /* msp430x14x. */ + N (16, bfd_mach_msp14, "msp:14", FALSE, & arch_info_struct[5]), + + /* msp430x15x. */ + N (16, bfd_mach_msp15, "msp:15", FALSE, & arch_info_struct[6]), + + /* msp430x16x. */ + N (16, bfd_mach_msp16, "msp:16", FALSE, & arch_info_struct[7]), + + /* msp430x31x. */ + N (16, bfd_mach_msp31, "msp:31", FALSE, & arch_info_struct[8]), + + /* msp430x32x. */ + N (16, bfd_mach_msp32, "msp:32", FALSE, & arch_info_struct[9]), + + /* msp430x33x. */ + N (16, bfd_mach_msp33, "msp:33", FALSE, & arch_info_struct[10]), + + /* msp430x41x. */ + N (16, bfd_mach_msp41, "msp:41", FALSE, & arch_info_struct[11]), + + /* msp430x42x. */ + N (16, bfd_mach_msp42, "msp:42", FALSE, & arch_info_struct[12]), + + /* msp430x43x. */ + N (16, bfd_mach_msp43, "msp:43", FALSE, & arch_info_struct[13]), + + /* msp430x44x. */ + N (16, bfd_mach_msp43, "msp:44", FALSE, NULL) +}; + +const bfd_arch_info_type bfd_msp430_arch = + N (16, bfd_mach_msp14, "msp:14", TRUE, & arch_info_struct[0]); + +/* This routine is provided two arch_infos and works out which MSP + machine which would be compatible with both and returns a pointer + to its info structure. */ + +static const bfd_arch_info_type * +compatible (a,b) + const bfd_arch_info_type * a; + const bfd_arch_info_type * b; +{ + /* If a & b are for different architectures we can do nothing. */ + if (a->arch != b->arch) + return NULL; + + if (a->mach <= b->mach) + return b; + + return a; +} diff --git a/bfd/cpu-xtensa.c b/bfd/cpu-xtensa.c new file mode 100644 index 0000000..fbfff64 --- /dev/null +++ b/bfd/cpu-xtensa.c @@ -0,0 +1,38 @@ +/* BFD support for the Xtensa processor. + Copyright 2003 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include "bfd.h" +#include "sysdep.h" +#include "libbfd.h" + +const bfd_arch_info_type bfd_xtensa_arch = +{ + 32, /* Bits per word. */ + 32, /* Bits per address. */ + 8, /* Bits per byte. */ + bfd_arch_xtensa, /* Architecture. */ + bfd_mach_xtensa, /* Machine. */ + "xtensa", /* Architecture name. */ + "xtensa", /* Printable name. */ + 4, /* Section align power. */ + TRUE, /* The default? */ + bfd_default_compatible, /* Architecture comparison fn. */ + bfd_default_scan, /* String to architecture convert fn. */ + NULL /* Next in list. */ +}; diff --git a/bfd/doc/fdl.texi b/bfd/doc/fdl.texi new file mode 100644 index 0000000..176233c --- /dev/null +++ b/bfd/doc/fdl.texi @@ -0,0 +1,366 @@ +@c -*-texinfo-*- +@appendix GNU Free Documentation License +@center Version 1.1, March 2000 + +@display +Copyright (C) 2000, Free Software Foundation, Inc. +59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +Everyone is permitted to copy and distribute verbatim copies +of this license document, but changing it is not allowed. +@end display +@sp 1 +@enumerate 0 +@item +PREAMBLE + +The purpose of this License is to make a manual, textbook, or other +written document ``free'' in the sense of freedom: to assure everyone +the effective freedom to copy and redistribute it, with or without +modifying it, either commercially or noncommercially. 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You may include a +translation of this License provided that you also include the +original English version of this License. In case of a disagreement +between the translation and the original English version of this +License, the original English version will prevail. +@sp 1 +@item +TERMINATION + +You may not copy, modify, sublicense, or distribute the Document except +as expressly provided for under this License. Any other attempt to +copy, modify, sublicense or distribute the Document is void, and will +automatically terminate your rights under this License. However, +parties who have received copies, or rights, from you under this +License will not have their licenses terminated so long as such +parties remain in full compliance. +@sp 1 +@item +FUTURE REVISIONS OF THIS LICENSE + +The Free Software Foundation may publish new, revised versions +of the GNU Free Documentation License from time to time. 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If the Document does not specify a version +number of this License, you may choose any version ever published (not +as a draft) by the Free Software Foundation. + +@end enumerate + +@unnumberedsec ADDENDUM: How to use this License for your documents + +To use this License in a document you have written, include a copy of +the License in the document and put the following copyright and +license notices just after the title page: + +@smallexample +@group +Copyright (C) @var{year} @var{your name}. +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License, Version 1.1 +or any later version published by the Free Software Foundation; +with the Invariant Sections being @var{list their titles}, with the +Front-Cover Texts being @var{list}, and with the Back-Cover Texts being @var{list}. +A copy of the license is included in the section entitled "GNU +Free Documentation License." +@end group +@end smallexample + +If you have no Invariant Sections, write ``with no Invariant Sections'' +instead of saying which ones are invariant. If you have no +Front-Cover Texts, write ``no Front-Cover Texts'' instead of +``Front-Cover Texts being @var{list}''; likewise for Back-Cover Texts. + +If your document contains nontrivial examples of program code, we +recommend releasing these examples in parallel under your choice of +free software license, such as the GNU General Public License, +to permit their use in free software. diff --git a/bfd/elf32-am33lin.c b/bfd/elf32-am33lin.c new file mode 100644 index 0000000..32e5663 --- /dev/null +++ b/bfd/elf32-am33lin.c @@ -0,0 +1,35 @@ +/* Matsushita AM33/2.0 support for 32-bit GNU/Linux ELF + Copyright 2003 + Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#define elf_symbol_leading_char 0 + +#define TARGET_LITTLE_SYM bfd_elf32_am33lin_vec +#define TARGET_LITTLE_NAME "elf32-am33lin" +#define ELF_ARCH bfd_arch_mn10300 +#define ELF_MACHINE_CODE EM_MN10300 +#define ELF_MACHINE_ALT1 EM_CYGNUS_MN10300 +#define ELF_MAXPAGESIZE 0x1000 + +/* Rename global functions. */ +#define _bfd_mn10300_elf_merge_private_bfd_data _bfd_am33_elf_merge_private_bfd_data +#define _bfd_mn10300_elf_object_p _bfd_am33_elf_object_p +#define _bfd_mn10300_elf_final_write_processing _bfd_am33_elf_final_write_processing + +#include "elf-m10300.c" diff --git a/bfd/elf32-iq2000.c b/bfd/elf32-iq2000.c new file mode 100644 index 0000000..f85ffac --- /dev/null +++ b/bfd/elf32-iq2000.c @@ -0,0 +1,952 @@ +/* IQ2000-specific support for 32-bit ELF. + Copyright (C) 2003 Free Software Foundation, Inc. + +This file is part of BFD, the Binary File Descriptor library. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include "bfd.h" +#include "sysdep.h" +#include "libbfd.h" +#include "elf-bfd.h" +#include "elf/iq2000.h" + +/* Forward declarations. */ + +/* Private relocation functions. */ +static bfd_reloc_status_type iq2000_elf_relocate_hi16 PARAMS ((bfd *, Elf_Internal_Rela *, bfd_byte *, bfd_vma)); +static reloc_howto_type * iq2000_reloc_type_lookup PARAMS ((bfd *, bfd_reloc_code_real_type)); +static void iq2000_info_to_howto_rela PARAMS ((bfd *, arelent *, Elf_Internal_Rela *)); +static bfd_boolean iq2000_elf_relocate_section PARAMS ((bfd *, struct bfd_link_info *, bfd *, asection *, bfd_byte *, Elf_Internal_Rela *, Elf_Internal_Sym *, asection **)); +static bfd_reloc_status_type iq2000_final_link_relocate PARAMS ((reloc_howto_type *, bfd *, asection *, bfd_byte *, Elf_Internal_Rela *, bfd_vma)); +static bfd_boolean iq2000_elf_gc_sweep_hook PARAMS ((bfd *, struct bfd_link_info *, asection *, const Elf_Internal_Rela *)); +static asection * iq2000_elf_gc_mark_hook PARAMS ((asection *sec, struct bfd_link_info *, Elf_Internal_Rela *, struct elf_link_hash_entry *, Elf_Internal_Sym *)); +static reloc_howto_type * iq2000_reloc_type_lookup PARAMS ((bfd *, bfd_reloc_code_real_type)); +static int elf32_iq2000_machine PARAMS ((bfd *)); +static bfd_boolean iq2000_elf_object_p PARAMS ((bfd *)); +static bfd_boolean iq2000_elf_set_private_flags PARAMS ((bfd *, flagword)); +static bfd_boolean iq2000_elf_copy_private_bfd_data PARAMS ((bfd *, bfd *)); +static bfd_boolean iq2000_elf_merge_private_bfd_data PARAMS ((bfd *, bfd *)); +static bfd_boolean iq2000_elf_print_private_bfd_data PARAMS ((bfd *, PTR)); +static bfd_boolean iq2000_elf_check_relocs PARAMS ((bfd *, struct bfd_link_info *, asection *, const Elf_Internal_Rela *)); +static bfd_reloc_status_type iq2000_elf_howto_hi16_reloc PARAMS ((bfd *, arelent *, asymbol *, PTR, asection *, bfd *, char **)); + + +static reloc_howto_type iq2000_elf_howto_table [] = +{ + /* This reloc does nothing. */ + + HOWTO (R_IQ2000_NONE, /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 32, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_bitfield, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_IQ2000_NONE", /* name */ + FALSE, /* partial_inplace */ + 0, /* src_mask */ + 0, /* dst_mask */ + FALSE), /* pcrel_offset */ + + /* A 16 bit absolute relocation. */ + HOWTO (R_IQ2000_16, /* type */ + 0, /* rightshift */ + 1, /* size (0 = byte, 1 = short, 2 = long) */ + 16, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_bitfield, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_IQ2000_16", /* name */ + FALSE, /* partial_inplace */ + 0x0000, /* src_mask */ + 0xffff, /* dst_mask */ + FALSE), /* pcrel_offset */ + + /* A 32 bit absolute relocation. */ + HOWTO (R_IQ2000_32, /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 31, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_bitfield, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_IQ2000_32", /* name */ + FALSE, /* partial_inplace */ + 0x00000000, /* src_mask */ + 0x7fffffff, /* dst_mask */ + FALSE), /* pcrel_offset */ + + /* 26 bit branch address. */ + HOWTO (R_IQ2000_26, /* type */ + 2, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 26, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + /* This needs complex overflow + detection, because the upper four + bits must match the PC. */ + bfd_elf_generic_reloc, /* special_function */ + "R_IQ2000_26", /* name */ + FALSE, /* partial_inplace */ + 0x00000000, /* src_mask */ + 0x03ffffff, /* dst_mask */ + FALSE), /* pcrel_offset */ + + /* 16 bit PC relative reference. */ + HOWTO (R_IQ2000_PC16, /* type */ + 2, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 16, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_signed, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_IQ2000_PC16", /* name */ + FALSE, /* partial_inplace */ + 0x0000, /* src_mask */ + 0xffff, /* dst_mask */ + TRUE), /* pcrel_offset */ + + /* high 16 bits of symbol value. */ + HOWTO (R_IQ2000_HI16, /* type */ + 16, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 15, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + iq2000_elf_howto_hi16_reloc, /* special_function */ + "R_IQ2000_HI16", /* name */ + FALSE, /* partial_inplace */ + 0x0000, /* src_mask */ + 0x7fff, /* dst_mask */ + FALSE), /* pcrel_offset */ + + /* Low 16 bits of symbol value. */ + HOWTO (R_IQ2000_LO16, /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 16, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_IQ2000_LO16", /* name */ + FALSE, /* partial_inplace */ + 0x0000, /* src_mask */ + 0xffff, /* dst_mask */ + FALSE), /* pcrel_offset */ + + /* 16-bit jump offset. */ + HOWTO (R_IQ2000_OFFSET_16, /* type */ + 2, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 16, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_IQ2000_OFFSET_16", /* name */ + FALSE, /* partial_inplace */ + 0x0000, /* src_mask */ + 0xffff, /* dst_mask */ + FALSE), /* pcrel_offset */ + + /* 21-bit jump offset. */ + HOWTO (R_IQ2000_OFFSET_21, /* type */ + 2, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 21, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_IQ2000_OFFSET_21", /* name */ + FALSE, /* partial_inplace */ + 0x000000, /* src_mask */ + 0x1fffff, /* dst_mask */ + FALSE), /* pcrel_offset */ + + /* unsigned high 16 bits of value. */ + HOWTO (R_IQ2000_OFFSET_21, /* type */ + 16, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 16, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_IQ2000_UHI16", /* name */ + FALSE, /* partial_inplace */ + 0x0000, /* src_mask */ + 0x7fff, /* dst_mask */ + FALSE), /* pcrel_offset */ + + /* A 32 bit absolute debug relocation. */ + HOWTO (R_IQ2000_32_DEBUG, /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 32, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_bitfield, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_IQ2000_32", /* name */ + FALSE, /* partial_inplace */ + 0x00000000, /* src_mask */ + 0xffffffff, /* dst_mask */ + FALSE), /* pcrel_offset */ + +}; + +/* GNU extension to record C++ vtable hierarchy. */ +static reloc_howto_type iq2000_elf_vtinherit_howto = + HOWTO (R_IQ2000_GNU_VTINHERIT, /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 0, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + NULL, /* special_function */ + "R_IQ2000_GNU_VTINHERIT", /* name */ + FALSE, /* partial_inplace */ + 0, /* src_mask */ + 0, /* dst_mask */ + FALSE); /* pcrel_offset */ + +/* GNU extension to record C++ vtable member usage. */ +static reloc_howto_type iq2000_elf_vtentry_howto = + HOWTO (R_IQ2000_GNU_VTENTRY, /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 0, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + NULL, /* special_function */ + "R_IQ2000_GNU_VTENTRY", /* name */ + FALSE, /* partial_inplace */ + 0, /* src_mask */ + 0, /* dst_mask */ + FALSE); /* pcrel_offset */ + + +/* Map BFD reloc types to IQ2000 ELF reloc types. */ + +struct iq2000_reloc_map +{ + bfd_reloc_code_real_type bfd_reloc_val; + unsigned int iq2000_reloc_val; +}; + +static const struct iq2000_reloc_map iq2000_reloc_map [] = +{ + { BFD_RELOC_NONE, R_IQ2000_NONE }, + { BFD_RELOC_16, R_IQ2000_16 }, + { BFD_RELOC_32, R_IQ2000_32 }, + { BFD_RELOC_MIPS_JMP, R_IQ2000_26 }, + { BFD_RELOC_16_PCREL_S2, R_IQ2000_PC16 }, + { BFD_RELOC_HI16, R_IQ2000_HI16 }, + { BFD_RELOC_LO16, R_IQ2000_LO16 }, + { BFD_RELOC_IQ2000_OFFSET_16,R_IQ2000_OFFSET_16 }, + { BFD_RELOC_IQ2000_OFFSET_21,R_IQ2000_OFFSET_21 }, + { BFD_RELOC_IQ2000_UHI16, R_IQ2000_UHI16 }, + { BFD_RELOC_VTABLE_INHERIT, R_IQ2000_GNU_VTINHERIT }, + { BFD_RELOC_VTABLE_ENTRY, R_IQ2000_GNU_VTENTRY }, +}; + +static bfd_reloc_status_type +iq2000_elf_howto_hi16_reloc (abfd, + reloc_entry, + symbol, + data, + input_section, + output_bfd, + error_message) + bfd *abfd ATTRIBUTE_UNUSED; + arelent *reloc_entry; + asymbol *symbol; + PTR data; + asection *input_section; + bfd *output_bfd; + char **error_message ATTRIBUTE_UNUSED; +{ + bfd_reloc_status_type ret; + bfd_vma relocation; + + /* If we're relocating, and this an external symbol, we don't want + to change anything. */ + if (output_bfd != (bfd *) NULL + && (symbol->flags & BSF_SECTION_SYM) == 0 + && reloc_entry->addend == 0) + { + reloc_entry->address += input_section->output_offset; + return bfd_reloc_ok; + } + + if (bfd_is_com_section (symbol->section)) + relocation = 0; + else + relocation = symbol->value; + + relocation += symbol->section->output_section->vma; + relocation += symbol->section->output_offset; + relocation += reloc_entry->addend; + + /* if %lo will have sign-extension, compensate by add 0x10000 to hi portion */ + if (relocation & 0x8000) + reloc_entry->addend += 0x10000; + + /* Now do the reloc in the usual way. */ + ret = bfd_elf_generic_reloc (abfd, reloc_entry, symbol, data, + input_section, output_bfd, error_message); + + /* put it back the way it was */ + if (relocation & 0x8000) + reloc_entry->addend -= 0x10000; + + return ret; +} + +static bfd_reloc_status_type +iq2000_elf_relocate_hi16 (input_bfd, relhi, contents, value) + bfd *input_bfd; + Elf_Internal_Rela *relhi; + bfd_byte *contents; + bfd_vma value; +{ + bfd_vma insn; + + insn = bfd_get_32 (input_bfd, contents + relhi->r_offset); + + value += relhi->r_addend; + value &= 0x7fffffff; /* mask off top-bit which is Harvard mask bit */ + + /* if top-bit of %lo value is on, this means that %lo will + sign-propagate and so we compensate by adding 1 to %hi value */ + if (value & 0x8000) + value += 0x10000; + + value >>= 16; + insn = ((insn & ~0xFFFF) | value); + + bfd_put_32 (input_bfd, insn, contents + relhi->r_offset); + return bfd_reloc_ok; +} + +static reloc_howto_type * +iq2000_reloc_type_lookup (abfd, code) + bfd * abfd ATTRIBUTE_UNUSED; + bfd_reloc_code_real_type code; +{ + /* Note that the iq2000_elf_howto_table is indxed by the R_ + constants. Thus, the order that the howto records appear in the + table *must* match the order of the relocation types defined in + include/elf/iq2000.h. */ + + switch (code) + { + case BFD_RELOC_NONE: + return &iq2000_elf_howto_table[ (int) R_IQ2000_NONE]; + case BFD_RELOC_16: + return &iq2000_elf_howto_table[ (int) R_IQ2000_16]; + case BFD_RELOC_32: + return &iq2000_elf_howto_table[ (int) R_IQ2000_32]; + case BFD_RELOC_MIPS_JMP: + return &iq2000_elf_howto_table[ (int) R_IQ2000_26]; + case BFD_RELOC_IQ2000_OFFSET_16: + return &iq2000_elf_howto_table[ (int) R_IQ2000_OFFSET_16]; + case BFD_RELOC_IQ2000_OFFSET_21: + return &iq2000_elf_howto_table[ (int) R_IQ2000_OFFSET_21]; + case BFD_RELOC_16_PCREL_S2: + return &iq2000_elf_howto_table[ (int) R_IQ2000_PC16]; + case BFD_RELOC_HI16: + return &iq2000_elf_howto_table[ (int) R_IQ2000_HI16]; + case BFD_RELOC_IQ2000_UHI16: + return &iq2000_elf_howto_table[ (int) R_IQ2000_UHI16]; + case BFD_RELOC_LO16: + return &iq2000_elf_howto_table[ (int) R_IQ2000_LO16]; + case BFD_RELOC_VTABLE_INHERIT: + return &iq2000_elf_vtinherit_howto; + case BFD_RELOC_VTABLE_ENTRY: + return &iq2000_elf_vtentry_howto; + default: + /* Pacify gcc -Wall. */ + return NULL; + } + return NULL; +} + + +/* Perform a single relocation. By default we use the standard BFD + routines. */ + +static bfd_reloc_status_type +iq2000_final_link_relocate (howto, input_bfd, input_section, contents, rel, relocation) + reloc_howto_type * howto; + bfd * input_bfd; + asection * input_section; + bfd_byte * contents; + Elf_Internal_Rela * rel; + bfd_vma relocation; +{ + return _bfd_final_link_relocate (howto, input_bfd, input_section, + contents, rel->r_offset, + relocation, rel->r_addend); +} + +/* Set the howto pointer for a IQ2000 ELF reloc. */ + +static void +iq2000_info_to_howto_rela (abfd, cache_ptr, dst) + bfd * abfd ATTRIBUTE_UNUSED; + arelent * cache_ptr; + Elf_Internal_Rela * dst; +{ + unsigned int r_type; + + r_type = ELF32_R_TYPE (dst->r_info); + switch (r_type) + { + case R_IQ2000_GNU_VTINHERIT: + cache_ptr->howto = & iq2000_elf_vtinherit_howto; + break; + + case R_IQ2000_GNU_VTENTRY: + cache_ptr->howto = & iq2000_elf_vtentry_howto; + break; + + default: + cache_ptr->howto = & iq2000_elf_howto_table [r_type]; + break; + } +} + +/* Look through the relocs for a section during the first phase. + Since we don't do .gots or .plts, we just need to consider the + virtual table relocs for gc. */ + +static bfd_boolean +iq2000_elf_check_relocs (abfd, info, sec, relocs) + bfd *abfd; + struct bfd_link_info *info; + asection *sec; + const Elf_Internal_Rela *relocs; +{ + Elf_Internal_Shdr *symtab_hdr; + struct elf_link_hash_entry **sym_hashes, **sym_hashes_end; + const Elf_Internal_Rela *rel; + const Elf_Internal_Rela *rel_end; + bfd_boolean changed = FALSE; + + if (info->relocatable) + return TRUE; + + symtab_hdr = &elf_tdata (abfd)->symtab_hdr; + sym_hashes = elf_sym_hashes (abfd); + sym_hashes_end = sym_hashes + symtab_hdr->sh_size/sizeof(Elf32_External_Sym); + if (!elf_bad_symtab (abfd)) + sym_hashes_end -= symtab_hdr->sh_info; + + rel_end = relocs + sec->reloc_count; + for (rel = relocs; rel < rel_end; rel++) + { + struct elf_link_hash_entry *h; + unsigned long r_symndx; + + r_symndx = ELF32_R_SYM (rel->r_info); + if (r_symndx < symtab_hdr->sh_info) + h = NULL; + else + h = sym_hashes[r_symndx - symtab_hdr->sh_info]; + + switch (ELF32_R_TYPE (rel->r_info)) + { + /* This relocation describes the C++ object vtable hierarchy. + Reconstruct it for later use during GC. */ + case R_IQ2000_GNU_VTINHERIT: + if (!_bfd_elf32_gc_record_vtinherit (abfd, sec, h, rel->r_offset)) + return FALSE; + break; + + /* This relocation describes which C++ vtable entries are actually + used. Record for later use during GC. */ + case R_IQ2000_GNU_VTENTRY: + if (!_bfd_elf32_gc_record_vtentry (abfd, sec, h, rel->r_addend)) + return FALSE; + break; + + case R_IQ2000_32: + /* For debug section, change to special harvard-aware relocations */ + if (memcmp (sec->name, ".debug", 6) == 0 + || memcmp (sec->name, ".stab", 5) == 0 + || memcmp (sec->name, ".eh_frame", 9) == 0) + { + ((Elf_Internal_Rela *) rel)->r_info + = ELF32_R_INFO (ELF32_R_SYM (rel->r_info), R_IQ2000_32_DEBUG); + changed = TRUE; + } + break; + } + } + + if (changed) + /* Note that we've changed relocs, otherwise if !info->keep_memory + we'll free the relocs and lose our changes. */ + (const Elf_Internal_Rela *) (elf_section_data (sec)->relocs) = relocs; + + return TRUE; +} + + +/* Relocate a IQ2000 ELF section. + There is some attempt to make this function usable for many architectures, + both USE_REL and USE_RELA ['twould be nice if such a critter existed], + if only to serve as a learning tool. + + The RELOCATE_SECTION function is called by the new ELF backend linker + to handle the relocations for a section. + + The relocs are always passed as Rela structures; if the section + actually uses Rel structures, the r_addend field will always be + zero. + + This function is responsible for adjusting the section contents as + necessary, and (if using Rela relocs and generating a relocatable + output file) adjusting the reloc addend as necessary. + + This function does not have to worry about setting the reloc + address or the reloc symbol index. + + LOCAL_SYMS is a pointer to the swapped in local symbols. + + LOCAL_SECTIONS is an array giving the section in the input file + corresponding to the st_shndx field of each local symbol. + + The global hash table entry for the global symbols can be found + via elf_sym_hashes (input_bfd). + + When generating relocatable output, this function must handle + STB_LOCAL/STT_SECTION symbols specially. The output symbol is + going to be the section symbol corresponding to the output + section, which means that the addend must be adjusted + accordingly. */ + +static bfd_boolean +iq2000_elf_relocate_section (output_bfd, info, input_bfd, input_section, + contents, relocs, local_syms, local_sections) + bfd * output_bfd ATTRIBUTE_UNUSED; + struct bfd_link_info * info; + bfd * input_bfd; + asection * input_section; + bfd_byte * contents; + Elf_Internal_Rela * relocs; + Elf_Internal_Sym * local_syms; + asection ** local_sections; +{ + Elf_Internal_Shdr * symtab_hdr; + struct elf_link_hash_entry ** sym_hashes; + Elf_Internal_Rela * rel; + Elf_Internal_Rela * relend; + + symtab_hdr = & elf_tdata (input_bfd)->symtab_hdr; + sym_hashes = elf_sym_hashes (input_bfd); + relend = relocs + input_section->reloc_count; + + for (rel = relocs; rel < relend; rel ++) + { + reloc_howto_type * howto; + unsigned long r_symndx; + Elf_Internal_Sym * sym; + asection * sec; + struct elf_link_hash_entry * h; + bfd_vma relocation; + bfd_reloc_status_type r; + const char * name = NULL; + int r_type; + + r_type = ELF32_R_TYPE (rel->r_info); + + if ( r_type == R_IQ2000_GNU_VTINHERIT + || r_type == R_IQ2000_GNU_VTENTRY) + continue; + + r_symndx = ELF32_R_SYM (rel->r_info); + + /* This is a final link. */ + howto = iq2000_elf_howto_table + ELF32_R_TYPE (rel->r_info); + h = NULL; + sym = NULL; + sec = NULL; + + if (r_symndx < symtab_hdr->sh_info) + { + sym = local_syms + r_symndx; + sec = local_sections [r_symndx]; + relocation = (sec->output_section->vma + + sec->output_offset + + sym->st_value); + + name = bfd_elf_string_from_elf_section + (input_bfd, symtab_hdr->sh_link, sym->st_name); + name = (name == NULL) ? bfd_section_name (input_bfd, sec) : name; +#ifdef DEBUG + fprintf (stderr, "local: sec: %s, sym: %s (%d), value: %x + %x + %x addend %x\n", + sec->name, name, sym->st_name, + sec->output_section->vma, sec->output_offset, + sym->st_value, rel->r_addend); +#endif + } + else + { + bfd_boolean unresolved_reloc; + bfd_boolean warned; + + RELOC_FOR_GLOBAL_SYMBOL (h, sym_hashes, r_symndx, + symtab_hdr, relocation, + sec, unresolved_reloc, info, warned); + + name = h->root.root.string; + } + + switch (r_type) + { + case R_IQ2000_HI16: + r = iq2000_elf_relocate_hi16 (input_bfd, rel, contents, relocation); + break; + + case R_IQ2000_PC16: + rel->r_addend -= 4; + /* Fall through. */ + + default: + r = iq2000_final_link_relocate (howto, input_bfd, input_section, + contents, rel, relocation); + break; + } + + if (r != bfd_reloc_ok) + { + const char * msg = (const char *) NULL; + + switch (r) + { + case bfd_reloc_overflow: + r = info->callbacks->reloc_overflow + (info, name, howto->name, (bfd_vma) 0, + input_bfd, input_section, rel->r_offset); + break; + + case bfd_reloc_undefined: + r = info->callbacks->undefined_symbol + (info, name, input_bfd, input_section, rel->r_offset, TRUE); + break; + + case bfd_reloc_outofrange: + msg = _("internal error: out of range error"); + break; + + case bfd_reloc_notsupported: + msg = _("internal error: unsupported relocation error"); + break; + + case bfd_reloc_dangerous: + msg = _("internal error: dangerous relocation"); + break; + + default: + msg = _("internal error: unknown error"); + break; + } + + if (msg) + r = info->callbacks->warning + (info, msg, name, input_bfd, input_section, rel->r_offset); + + if (! r) + return FALSE; + } + } + + return TRUE; +} + + +/* Update the got entry reference counts for the section being + removed. */ + +static bfd_boolean +iq2000_elf_gc_sweep_hook (abfd, info, sec, relocs) + bfd * abfd ATTRIBUTE_UNUSED; + struct bfd_link_info * info ATTRIBUTE_UNUSED; + asection * sec ATTRIBUTE_UNUSED; + const Elf_Internal_Rela * relocs ATTRIBUTE_UNUSED; +{ + return TRUE; +} + +/* Return the section that should be marked against GC for a given + relocation. */ + +static asection * +iq2000_elf_gc_mark_hook (sec, info, rel, h, sym) + asection * sec; + struct bfd_link_info * info ATTRIBUTE_UNUSED; + Elf_Internal_Rela * rel; + struct elf_link_hash_entry * h; + Elf_Internal_Sym * sym; +{ + if (h != NULL) + { + switch (ELF32_R_TYPE (rel->r_info)) + { + case R_IQ2000_GNU_VTINHERIT: + case R_IQ2000_GNU_VTENTRY: + break; + + default: + switch (h->root.type) + { + case bfd_link_hash_defined: + case bfd_link_hash_defweak: + return h->root.u.def.section; + + case bfd_link_hash_common: + return h->root.u.c.p->section; + + default: + break; + } + } + } + else + return bfd_section_from_elf_index (sec->owner, sym->st_shndx); + + return NULL; +} + + +/* Return the MACH for an e_flags value. */ + +static int +elf32_iq2000_machine (abfd) + bfd *abfd; +{ + switch (elf_elfheader (abfd)->e_flags & EF_IQ2000_CPU_MASK) + { + case EF_IQ2000_CPU_IQ2000: return bfd_mach_iq2000; + case EF_IQ2000_CPU_IQ10: return bfd_mach_iq10; + } + + return bfd_mach_iq2000; +} + + +/* Function to set the ELF flag bits. */ + +static bfd_boolean +iq2000_elf_set_private_flags (abfd, flags) + bfd *abfd; + flagword flags; +{ + elf_elfheader (abfd)->e_flags = flags; + elf_flags_init (abfd) = TRUE; + return TRUE; +} + +/* Copy backend specific data from one object module to another. */ + +static bfd_boolean +iq2000_elf_copy_private_bfd_data (ibfd, obfd) + bfd *ibfd; + bfd *obfd; +{ + if (bfd_get_flavour (ibfd) != bfd_target_elf_flavour + || bfd_get_flavour (obfd) != bfd_target_elf_flavour) + return TRUE; + + BFD_ASSERT (!elf_flags_init (obfd) + || elf_elfheader (obfd)->e_flags == elf_elfheader (ibfd)->e_flags); + + elf_elfheader (obfd)->e_flags = elf_elfheader (ibfd)->e_flags; + elf_flags_init (obfd) = TRUE; + return TRUE; +} + +/* Merge backend specific data from an object file to the output + object file when linking. */ + +static bfd_boolean +iq2000_elf_merge_private_bfd_data (ibfd, obfd) + bfd *ibfd; + bfd *obfd; +{ + flagword old_flags, old_partial; + flagword new_flags, new_partial; + bfd_boolean error = FALSE; + char new_opt[80]; + char old_opt[80]; + + new_opt[0] = old_opt[0] = '\0'; + new_flags = elf_elfheader (ibfd)->e_flags; + old_flags = elf_elfheader (obfd)->e_flags; + +#ifdef DEBUG + (*_bfd_error_handler) ("old_flags = 0x%.8lx, new_flags = 0x%.8lx, init = %s, filename = %s", + old_flags, new_flags, elf_flags_init (obfd) ? "yes" : "no", + bfd_get_filename (ibfd)); +#endif + + if (!elf_flags_init (obfd)) + { + /* First call, no flags set. */ + elf_flags_init (obfd) = TRUE; + elf_elfheader (obfd)->e_flags = new_flags; + } + + else if (new_flags == old_flags) + /* Compatible flags are ok. */ + ; + + else /* Possibly incompatible flags. */ + { + /* Warn if different cpu is used (allow a specific cpu to override + the generic cpu). */ + new_partial = (new_flags & EF_IQ2000_CPU_MASK); + old_partial = (old_flags & EF_IQ2000_CPU_MASK); + if (new_partial == old_partial) + ; + + else + { + switch (new_partial) + { + default: strcat (new_opt, " -m2000"); break; + case EF_IQ2000_CPU_IQ2000: strcat (new_opt, " -m2000"); break; + case EF_IQ2000_CPU_IQ10: strcat (new_opt, " -m10"); break; + } + + switch (old_partial) + { + default: strcat (old_opt, " -m2000"); break; + case EF_IQ2000_CPU_IQ2000: strcat (old_opt, " -m2000"); break; + case EF_IQ2000_CPU_IQ10: strcat (old_opt, " -m10"); break; + } + } + + /* Print out any mismatches from above. */ + if (new_opt[0]) + { + error = TRUE; + (*_bfd_error_handler) + (_("%s: compiled with %s and linked with modules compiled with %s"), + bfd_get_filename (ibfd), new_opt, old_opt); + } + + new_flags &= ~ EF_IQ2000_ALL_FLAGS; + old_flags &= ~ EF_IQ2000_ALL_FLAGS; + + /* Warn about any other mismatches. */ + if (new_flags != old_flags) + { + error = TRUE; + (*_bfd_error_handler) + (_("%s: uses different e_flags (0x%lx) fields than previous modules (0x%lx)"), + bfd_get_filename (ibfd), (long)new_flags, (long)old_flags); + } + } + + if (error) + bfd_set_error (bfd_error_bad_value); + + return !error; +} + + +static bfd_boolean +iq2000_elf_print_private_bfd_data (abfd, ptr) + bfd *abfd; + PTR ptr; +{ + FILE *file = (FILE *) ptr; + flagword flags; + + BFD_ASSERT (abfd != NULL && ptr != NULL); + + /* Print normal ELF private data. */ + _bfd_elf_print_private_bfd_data (abfd, ptr); + + flags = elf_elfheader (abfd)->e_flags; + fprintf (file, _("private flags = 0x%lx:"), (long)flags); + + switch (flags & EF_IQ2000_CPU_MASK) + { + default: break; + case EF_IQ2000_CPU_IQ2000: fprintf (file, " -m2000"); break; + case EF_IQ2000_CPU_IQ10: fprintf (file, " -m10"); break; + } + + fputc ('\n', file); + return TRUE; +} + +static +bfd_boolean +iq2000_elf_object_p (abfd) + bfd *abfd; +{ + /* Irix 5 and 6 is broken. Object file symbol tables are not always + sorted correctly such that local symbols precede global symbols, + and the sh_info field in the symbol table is not always right. */ + elf_bad_symtab (abfd) = TRUE; + + bfd_default_set_arch_mach (abfd, bfd_arch_iq2000, + elf32_iq2000_machine (abfd)); + return TRUE; +} + + +#define ELF_ARCH bfd_arch_iq2000 +#define ELF_MACHINE_CODE EM_IQ2000 +#define ELF_MAXPAGESIZE 0x1000 + +#define TARGET_BIG_SYM bfd_elf32_iq2000_vec +#define TARGET_BIG_NAME "elf32-iq2000" + +#define elf_info_to_howto_rel NULL +#define elf_info_to_howto iq2000_info_to_howto_rela +#define elf_backend_relocate_section iq2000_elf_relocate_section +#define elf_backend_gc_mark_hook iq2000_elf_gc_mark_hook +#define elf_backend_gc_sweep_hook iq2000_elf_gc_sweep_hook +#define elf_backend_check_relocs iq2000_elf_check_relocs +#define elf_backend_object_p iq2000_elf_object_p +#define elf_backend_rela_normal 1 + +#define elf_backend_can_gc_sections 1 + +#define bfd_elf32_bfd_reloc_type_lookup iq2000_reloc_type_lookup +#define bfd_elf32_bfd_set_private_flags iq2000_elf_set_private_flags +#define bfd_elf32_bfd_copy_private_bfd_data iq2000_elf_copy_private_bfd_data +#define bfd_elf32_bfd_merge_private_bfd_data iq2000_elf_merge_private_bfd_data +#define bfd_elf32_bfd_print_private_bfd_data iq2000_elf_print_private_bfd_data + +#include "elf32-target.h" diff --git a/bfd/elf32-m68hc1x.c b/bfd/elf32-m68hc1x.c new file mode 100644 index 0000000..709b8f4 --- /dev/null +++ b/bfd/elf32-m68hc1x.c @@ -0,0 +1,1423 @@ +/* Motorola 68HC11/HC12-specific support for 32-bit ELF + Copyright 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. + Contributed by Stephane Carrez (stcarrez@nerim.fr) + +This file is part of BFD, the Binary File Descriptor library. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include "bfd.h" +#include "sysdep.h" +#include "bfdlink.h" +#include "libbfd.h" +#include "elf-bfd.h" +#include "elf32-m68hc1x.h" +#include "elf/m68hc11.h" +#include "opcode/m68hc11.h" + + +#define m68hc12_stub_hash_lookup(table, string, create, copy) \ + ((struct elf32_m68hc11_stub_hash_entry *) \ + bfd_hash_lookup ((table), (string), (create), (copy))) + +static struct elf32_m68hc11_stub_hash_entry* m68hc12_add_stub + (const char *stub_name, + asection *section, + struct m68hc11_elf_link_hash_table *htab); + +static struct bfd_hash_entry *stub_hash_newfunc + (struct bfd_hash_entry *, struct bfd_hash_table *, const char *); + +static void m68hc11_elf_set_symbol (bfd* abfd, struct bfd_link_info *info, + const char* name, bfd_vma value, + asection* sec); + +static bfd_boolean m68hc11_elf_export_one_stub + (struct bfd_hash_entry *gen_entry, void *in_arg); + +static bfd_boolean m68hc11_get_relocation_value + (bfd* abfd, + struct bfd_link_info* info, + asection **local_sections, + Elf_Internal_Sym* local_syms, + Elf_Internal_Rela* rel, + const char** name, + bfd_vma* relocation, + bfd_boolean* is_far); + +static void scan_sections_for_abi (bfd*, asection*, PTR); + +struct m68hc11_scan_param +{ + struct m68hc11_page_info* pinfo; + bfd_boolean use_memory_banks; +}; + + +/* Create a 68HC11/68HC12 ELF linker hash table. */ + +struct m68hc11_elf_link_hash_table* +m68hc11_elf_hash_table_create (bfd *abfd) +{ + struct m68hc11_elf_link_hash_table *ret; + bfd_size_type amt = sizeof (struct m68hc11_elf_link_hash_table); + + ret = (struct m68hc11_elf_link_hash_table *) bfd_malloc (amt); + if (ret == (struct m68hc11_elf_link_hash_table *) NULL) + return NULL; + + memset (ret, 0, amt); + if (! _bfd_elf_link_hash_table_init (&ret->root, abfd, + _bfd_elf_link_hash_newfunc)) + { + free (ret); + return NULL; + } + + /* Init the stub hash table too. */ + amt = sizeof (struct bfd_hash_table); + ret->stub_hash_table = (struct bfd_hash_table*) bfd_malloc (amt); + if (ret->stub_hash_table == NULL) + { + free (ret); + return NULL; + } + if (!bfd_hash_table_init (ret->stub_hash_table, stub_hash_newfunc)) + return NULL; + + ret->stub_bfd = NULL; + ret->stub_section = 0; + ret->add_stub_section = NULL; + ret->sym_sec.abfd = NULL; + + return ret; +} + +/* Free the derived linker hash table. */ + +void +m68hc11_elf_bfd_link_hash_table_free (struct bfd_link_hash_table *hash) +{ + struct m68hc11_elf_link_hash_table *ret + = (struct m68hc11_elf_link_hash_table *) hash; + + bfd_hash_table_free (ret->stub_hash_table); + free (ret->stub_hash_table); + _bfd_generic_link_hash_table_free (hash); +} + +/* Assorted hash table functions. */ + +/* Initialize an entry in the stub hash table. */ + +static struct bfd_hash_entry * +stub_hash_newfunc (struct bfd_hash_entry *entry, struct bfd_hash_table *table, + const char *string) +{ + /* Allocate the structure if it has not already been allocated by a + subclass. */ + if (entry == NULL) + { + entry = bfd_hash_allocate (table, + sizeof (struct elf32_m68hc11_stub_hash_entry)); + if (entry == NULL) + return entry; + } + + /* Call the allocation method of the superclass. */ + entry = bfd_hash_newfunc (entry, table, string); + if (entry != NULL) + { + struct elf32_m68hc11_stub_hash_entry *eh; + + /* Initialize the local fields. */ + eh = (struct elf32_m68hc11_stub_hash_entry *) entry; + eh->stub_sec = NULL; + eh->stub_offset = 0; + eh->target_value = 0; + eh->target_section = NULL; + } + + return entry; +} + +/* Add a new stub entry to the stub hash. Not all fields of the new + stub entry are initialised. */ + +static struct elf32_m68hc11_stub_hash_entry * +m68hc12_add_stub (const char *stub_name, asection *section, + struct m68hc11_elf_link_hash_table *htab) +{ + struct elf32_m68hc11_stub_hash_entry *stub_entry; + + /* Enter this entry into the linker stub hash table. */ + stub_entry = m68hc12_stub_hash_lookup (htab->stub_hash_table, stub_name, + TRUE, FALSE); + if (stub_entry == NULL) + { + (*_bfd_error_handler) (_("%s: cannot create stub entry %s"), + bfd_archive_filename (section->owner), + stub_name); + return NULL; + } + + if (htab->stub_section == 0) + { + htab->stub_section = (*htab->add_stub_section) (".tramp", + htab->tramp_section); + } + + stub_entry->stub_sec = htab->stub_section; + stub_entry->stub_offset = 0; + return stub_entry; +} + +/* Hook called by the linker routine which adds symbols from an object + file. We use it for identify far symbols and force a loading of + the trampoline handler. */ + +bfd_boolean +elf32_m68hc11_add_symbol_hook (bfd *abfd, struct bfd_link_info *info, + const Elf_Internal_Sym *sym, + const char **namep ATTRIBUTE_UNUSED, + flagword *flagsp ATTRIBUTE_UNUSED, + asection **secp ATTRIBUTE_UNUSED, + bfd_vma *valp ATTRIBUTE_UNUSED) +{ + if (sym->st_other & STO_M68HC12_FAR) + { + struct elf_link_hash_entry *h; + + h = (struct elf_link_hash_entry *) + bfd_link_hash_lookup (info->hash, "__far_trampoline", + FALSE, FALSE, FALSE); + if (h == NULL) + { + struct bfd_link_hash_entry* entry = NULL; + + _bfd_generic_link_add_one_symbol (info, abfd, + "__far_trampoline", + BSF_GLOBAL, + bfd_und_section_ptr, + (bfd_vma) 0, (const char*) NULL, + FALSE, FALSE, &entry); + } + + } + return TRUE; +} + +/* External entry points for sizing and building linker stubs. */ + +/* Set up various things so that we can make a list of input sections + for each output section included in the link. Returns -1 on error, + 0 when no stubs will be needed, and 1 on success. */ + +int +elf32_m68hc11_setup_section_lists (bfd *output_bfd, struct bfd_link_info *info) +{ + bfd *input_bfd; + unsigned int bfd_count; + int top_id, top_index; + asection *section; + asection **input_list, **list; + bfd_size_type amt; + asection *text_section; + struct m68hc11_elf_link_hash_table *htab; + + htab = m68hc11_elf_hash_table (info); + + if (htab->root.root.creator->flavour != bfd_target_elf_flavour) + return 0; + + /* Count the number of input BFDs and find the top input section id. + Also search for an existing ".tramp" section so that we know + where generated trampolines must go. Default to ".text" if we + can't find it. */ + htab->tramp_section = 0; + text_section = 0; + for (input_bfd = info->input_bfds, bfd_count = 0, top_id = 0; + input_bfd != NULL; + input_bfd = input_bfd->link_next) + { + bfd_count += 1; + for (section = input_bfd->sections; + section != NULL; + section = section->next) + { + const char* name = bfd_get_section_name (input_bfd, section); + + if (!strcmp (name, ".tramp")) + htab->tramp_section = section; + + if (!strcmp (name, ".text")) + text_section = section; + + if (top_id < section->id) + top_id = section->id; + } + } + htab->bfd_count = bfd_count; + if (htab->tramp_section == 0) + htab->tramp_section = text_section; + + /* We can't use output_bfd->section_count here to find the top output + section index as some sections may have been removed, and + _bfd_strip_section_from_output doesn't renumber the indices. */ + for (section = output_bfd->sections, top_index = 0; + section != NULL; + section = section->next) + { + if (top_index < section->index) + top_index = section->index; + } + + htab->top_index = top_index; + amt = sizeof (asection *) * (top_index + 1); + input_list = (asection **) bfd_malloc (amt); + htab->input_list = input_list; + if (input_list == NULL) + return -1; + + /* For sections we aren't interested in, mark their entries with a + value we can check later. */ + list = input_list + top_index; + do + *list = bfd_abs_section_ptr; + while (list-- != input_list); + + for (section = output_bfd->sections; + section != NULL; + section = section->next) + { + if ((section->flags & SEC_CODE) != 0) + input_list[section->index] = NULL; + } + + return 1; +} + +/* Determine and set the size of the stub section for a final link. + + The basic idea here is to examine all the relocations looking for + PC-relative calls to a target that is unreachable with a "bl" + instruction. */ + +bfd_boolean +elf32_m68hc11_size_stubs (bfd *output_bfd, bfd *stub_bfd, + struct bfd_link_info *info, + asection * (*add_stub_section) (const char*, asection*)) +{ + bfd *input_bfd; + asection *section; + Elf_Internal_Sym *local_syms, **all_local_syms; + unsigned int bfd_indx, bfd_count; + bfd_size_type amt; + asection *stub_sec; + + struct m68hc11_elf_link_hash_table *htab = m68hc11_elf_hash_table (info); + + /* Stash our params away. */ + htab->stub_bfd = stub_bfd; + htab->add_stub_section = add_stub_section; + + /* Count the number of input BFDs and find the top input section id. */ + for (input_bfd = info->input_bfds, bfd_count = 0; + input_bfd != NULL; + input_bfd = input_bfd->link_next) + { + bfd_count += 1; + } + + /* We want to read in symbol extension records only once. To do this + we need to read in the local symbols in parallel and save them for + later use; so hold pointers to the local symbols in an array. */ + amt = sizeof (Elf_Internal_Sym *) * bfd_count; + all_local_syms = (Elf_Internal_Sym **) bfd_zmalloc (amt); + if (all_local_syms == NULL) + return FALSE; + + /* Walk over all the input BFDs, swapping in local symbols. */ + for (input_bfd = info->input_bfds, bfd_indx = 0; + input_bfd != NULL; + input_bfd = input_bfd->link_next, bfd_indx++) + { + Elf_Internal_Shdr *symtab_hdr; + + /* We'll need the symbol table in a second. */ + symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr; + if (symtab_hdr->sh_info == 0) + continue; + + /* We need an array of the local symbols attached to the input bfd. */ + local_syms = (Elf_Internal_Sym *) symtab_hdr->contents; + if (local_syms == NULL) + { + local_syms = bfd_elf_get_elf_syms (input_bfd, symtab_hdr, + symtab_hdr->sh_info, 0, + NULL, NULL, NULL); + /* Cache them for elf_link_input_bfd. */ + symtab_hdr->contents = (unsigned char *) local_syms; + } + if (local_syms == NULL) + { + free (all_local_syms); + return FALSE; + } + + all_local_syms[bfd_indx] = local_syms; + } + + for (input_bfd = info->input_bfds, bfd_indx = 0; + input_bfd != NULL; + input_bfd = input_bfd->link_next, bfd_indx++) + { + Elf_Internal_Shdr *symtab_hdr; + Elf_Internal_Sym *local_syms; + struct elf_link_hash_entry ** sym_hashes; + + sym_hashes = elf_sym_hashes (input_bfd); + + /* We'll need the symbol table in a second. */ + symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr; + if (symtab_hdr->sh_info == 0) + continue; + + local_syms = all_local_syms[bfd_indx]; + + /* Walk over each section attached to the input bfd. */ + for (section = input_bfd->sections; + section != NULL; + section = section->next) + { + Elf_Internal_Rela *internal_relocs, *irelaend, *irela; + + /* If there aren't any relocs, then there's nothing more + to do. */ + if ((section->flags & SEC_RELOC) == 0 + || section->reloc_count == 0) + continue; + + /* If this section is a link-once section that will be + discarded, then don't create any stubs. */ + if (section->output_section == NULL + || section->output_section->owner != output_bfd) + continue; + + /* Get the relocs. */ + internal_relocs + = _bfd_elf_link_read_relocs (input_bfd, section, NULL, + (Elf_Internal_Rela *) NULL, + info->keep_memory); + if (internal_relocs == NULL) + goto error_ret_free_local; + + /* Now examine each relocation. */ + irela = internal_relocs; + irelaend = irela + section->reloc_count; + for (; irela < irelaend; irela++) + { + unsigned int r_type, r_indx; + struct elf32_m68hc11_stub_hash_entry *stub_entry; + asection *sym_sec; + bfd_vma sym_value; + struct elf_link_hash_entry *hash; + const char *stub_name; + Elf_Internal_Sym *sym; + + r_type = ELF32_R_TYPE (irela->r_info); + + /* Only look at 16-bit relocs. */ + if (r_type != (unsigned int) R_M68HC11_16) + continue; + + /* Now determine the call target, its name, value, + section. */ + r_indx = ELF32_R_SYM (irela->r_info); + if (r_indx < symtab_hdr->sh_info) + { + /* It's a local symbol. */ + Elf_Internal_Shdr *hdr; + bfd_boolean is_far; + + sym = local_syms + r_indx; + is_far = (sym && (sym->st_other & STO_M68HC12_FAR)); + if (!is_far) + continue; + + hdr = elf_elfsections (input_bfd)[sym->st_shndx]; + sym_sec = hdr->bfd_section; + stub_name = (bfd_elf_string_from_elf_section + (input_bfd, symtab_hdr->sh_link, + sym->st_name)); + sym_value = sym->st_value; + hash = NULL; + } + else + { + /* It's an external symbol. */ + int e_indx; + + e_indx = r_indx - symtab_hdr->sh_info; + hash = (struct elf_link_hash_entry *) + (sym_hashes[e_indx]); + + while (hash->root.type == bfd_link_hash_indirect + || hash->root.type == bfd_link_hash_warning) + hash = ((struct elf_link_hash_entry *) + hash->root.u.i.link); + + if (hash->root.type == bfd_link_hash_defined + || hash->root.type == bfd_link_hash_defweak) + { + if (!(hash->other & STO_M68HC12_FAR)) + continue; + } + else if (hash->root.type == bfd_link_hash_undefweak) + { + continue; + } + else if (hash->root.type == bfd_link_hash_undefined) + { + continue; + } + else + { + bfd_set_error (bfd_error_bad_value); + goto error_ret_free_internal; + } + sym_sec = hash->root.u.def.section; + sym_value = hash->root.u.def.value; + stub_name = hash->root.root.string; + } + + if (!stub_name) + goto error_ret_free_internal; + + stub_entry = m68hc12_stub_hash_lookup + (htab->stub_hash_table, + stub_name, + FALSE, FALSE); + if (stub_entry == NULL) + { + if (add_stub_section == 0) + continue; + + stub_entry = m68hc12_add_stub (stub_name, section, htab); + if (stub_entry == NULL) + { + error_ret_free_internal: + if (elf_section_data (section)->relocs == NULL) + free (internal_relocs); + goto error_ret_free_local; + } + } + + stub_entry->target_value = sym_value; + stub_entry->target_section = sym_sec; + } + + /* We're done with the internal relocs, free them. */ + if (elf_section_data (section)->relocs == NULL) + free (internal_relocs); + } + } + + if (add_stub_section) + { + /* OK, we've added some stubs. Find out the new size of the + stub sections. */ + for (stub_sec = htab->stub_bfd->sections; + stub_sec != NULL; + stub_sec = stub_sec->next) + { + stub_sec->_raw_size = 0; + stub_sec->_cooked_size = 0; + } + + bfd_hash_traverse (htab->stub_hash_table, htab->size_one_stub, htab); + } + free (all_local_syms); + return TRUE; + + error_ret_free_local: + free (all_local_syms); + return FALSE; +} + +/* Export the trampoline addresses in the symbol table. */ +static bfd_boolean +m68hc11_elf_export_one_stub (struct bfd_hash_entry *gen_entry, void *in_arg) +{ + struct bfd_link_info *info; + struct m68hc11_elf_link_hash_table *htab; + struct elf32_m68hc11_stub_hash_entry *stub_entry; + char* name; + bfd_boolean result; + + info = (struct bfd_link_info *) in_arg; + htab = m68hc11_elf_hash_table (info); + + /* Massage our args to the form they really have. */ + stub_entry = (struct elf32_m68hc11_stub_hash_entry *) gen_entry; + + /* Generate the trampoline according to HC11 or HC12. */ + result = (* htab->build_one_stub) (gen_entry, in_arg); + + /* Make a printable name that does not conflict with the real function. */ + name = alloca (strlen (stub_entry->root.string) + 16); + sprintf (name, "tramp.%s", stub_entry->root.string); + + /* Export the symbol for debugging/disassembling. */ + m68hc11_elf_set_symbol (htab->stub_bfd, info, name, + stub_entry->stub_offset, + stub_entry->stub_sec); + return result; +} + +/* Export a symbol or set its value and section. */ +static void +m68hc11_elf_set_symbol (bfd *abfd, struct bfd_link_info *info, + const char *name, bfd_vma value, asection *sec) +{ + struct elf_link_hash_entry *h; + + h = (struct elf_link_hash_entry *) + bfd_link_hash_lookup (info->hash, name, FALSE, FALSE, FALSE); + if (h == NULL) + { + _bfd_generic_link_add_one_symbol (info, abfd, + name, + BSF_GLOBAL, + sec, + value, + (const char*) NULL, + TRUE, FALSE, NULL); + } + else + { + h->root.type = bfd_link_hash_defined; + h->root.u.def.value = value; + h->root.u.def.section = sec; + } +} + + +/* Build all the stubs associated with the current output file. The + stubs are kept in a hash table attached to the main linker hash + table. This function is called via m68hc12elf_finish in the + linker. */ + +bfd_boolean +elf32_m68hc11_build_stubs (bfd *abfd, struct bfd_link_info *info) +{ + asection *stub_sec; + struct bfd_hash_table *table; + struct m68hc11_elf_link_hash_table *htab; + struct m68hc11_scan_param param; + + m68hc11_elf_get_bank_parameters (info); + htab = m68hc11_elf_hash_table (info); + + for (stub_sec = htab->stub_bfd->sections; + stub_sec != NULL; + stub_sec = stub_sec->next) + { + bfd_size_type size; + + /* Allocate memory to hold the linker stubs. */ + size = stub_sec->_raw_size; + stub_sec->contents = (unsigned char *) bfd_zalloc (htab->stub_bfd, size); + if (stub_sec->contents == NULL && size != 0) + return FALSE; + stub_sec->_raw_size = 0; + } + + /* Build the stubs as directed by the stub hash table. */ + table = htab->stub_hash_table; + bfd_hash_traverse (table, m68hc11_elf_export_one_stub, info); + + /* Scan the output sections to see if we use the memory banks. + If so, export the symbols that define how the memory banks + are mapped. This is used by gdb and the simulator to obtain + the information. It can be used by programs to burn the eprom + at the good addresses. */ + param.use_memory_banks = FALSE; + param.pinfo = &htab->pinfo; + bfd_map_over_sections (abfd, scan_sections_for_abi, ¶m); + if (param.use_memory_banks) + { + m68hc11_elf_set_symbol (abfd, info, BFD_M68HC11_BANK_START_NAME, + htab->pinfo.bank_physical, + bfd_abs_section_ptr); + m68hc11_elf_set_symbol (abfd, info, BFD_M68HC11_BANK_VIRTUAL_NAME, + htab->pinfo.bank_virtual, + bfd_abs_section_ptr); + m68hc11_elf_set_symbol (abfd, info, BFD_M68HC11_BANK_SIZE_NAME, + htab->pinfo.bank_size, + bfd_abs_section_ptr); + } + + return TRUE; +} + +void +m68hc11_elf_get_bank_parameters (struct bfd_link_info *info) +{ + unsigned i; + struct m68hc11_page_info *pinfo; + struct bfd_link_hash_entry *h; + + pinfo = &m68hc11_elf_hash_table (info)->pinfo; + if (pinfo->bank_param_initialized) + return; + + pinfo->bank_virtual = M68HC12_BANK_VIRT; + pinfo->bank_mask = M68HC12_BANK_MASK; + pinfo->bank_physical = M68HC12_BANK_BASE; + pinfo->bank_shift = M68HC12_BANK_SHIFT; + pinfo->bank_size = 1 << M68HC12_BANK_SHIFT; + + h = bfd_link_hash_lookup (info->hash, BFD_M68HC11_BANK_START_NAME, + FALSE, FALSE, TRUE); + if (h != (struct bfd_link_hash_entry*) NULL + && h->type == bfd_link_hash_defined) + pinfo->bank_physical = (h->u.def.value + + h->u.def.section->output_section->vma + + h->u.def.section->output_offset); + + h = bfd_link_hash_lookup (info->hash, BFD_M68HC11_BANK_VIRTUAL_NAME, + FALSE, FALSE, TRUE); + if (h != (struct bfd_link_hash_entry*) NULL + && h->type == bfd_link_hash_defined) + pinfo->bank_virtual = (h->u.def.value + + h->u.def.section->output_section->vma + + h->u.def.section->output_offset); + + h = bfd_link_hash_lookup (info->hash, BFD_M68HC11_BANK_SIZE_NAME, + FALSE, FALSE, TRUE); + if (h != (struct bfd_link_hash_entry*) NULL + && h->type == bfd_link_hash_defined) + pinfo->bank_size = (h->u.def.value + + h->u.def.section->output_section->vma + + h->u.def.section->output_offset); + + pinfo->bank_shift = 0; + for (i = pinfo->bank_size; i != 0; i >>= 1) + pinfo->bank_shift++; + pinfo->bank_shift--; + pinfo->bank_mask = (1 << pinfo->bank_shift) - 1; + pinfo->bank_physical_end = pinfo->bank_physical + pinfo->bank_size; + pinfo->bank_param_initialized = 1; + + h = bfd_link_hash_lookup (info->hash, "__far_trampoline", FALSE, + FALSE, TRUE); + if (h != (struct bfd_link_hash_entry*) NULL + && h->type == bfd_link_hash_defined) + pinfo->trampoline_addr = (h->u.def.value + + h->u.def.section->output_section->vma + + h->u.def.section->output_offset); +} + +/* Return 1 if the address is in banked memory. + This can be applied to a virtual address and to a physical address. */ +int +m68hc11_addr_is_banked (struct m68hc11_page_info *pinfo, bfd_vma addr) +{ + if (addr >= pinfo->bank_virtual) + return 1; + + if (addr >= pinfo->bank_physical && addr <= pinfo->bank_physical_end) + return 1; + + return 0; +} + +/* Return the physical address seen by the processor, taking + into account banked memory. */ +bfd_vma +m68hc11_phys_addr (struct m68hc11_page_info *pinfo, bfd_vma addr) +{ + if (addr < pinfo->bank_virtual) + return addr; + + /* Map the address to the memory bank. */ + addr -= pinfo->bank_virtual; + addr &= pinfo->bank_mask; + addr += pinfo->bank_physical; + return addr; +} + +/* Return the page number corresponding to an address in banked memory. */ +bfd_vma +m68hc11_phys_page (struct m68hc11_page_info *pinfo, bfd_vma addr) +{ + if (addr < pinfo->bank_virtual) + return 0; + + /* Map the address to the memory bank. */ + addr -= pinfo->bank_virtual; + addr >>= pinfo->bank_shift; + addr &= 0x0ff; + return addr; +} + +/* This function is used for relocs which are only used for relaxing, + which the linker should otherwise ignore. */ + +bfd_reloc_status_type +m68hc11_elf_ignore_reloc (bfd *abfd ATTRIBUTE_UNUSED, + arelent *reloc_entry, + asymbol *symbol ATTRIBUTE_UNUSED, + void *data ATTRIBUTE_UNUSED, + asection *input_section, + bfd *output_bfd, + char **error_message ATTRIBUTE_UNUSED) +{ + if (output_bfd != NULL) + reloc_entry->address += input_section->output_offset; + return bfd_reloc_ok; +} + +bfd_reloc_status_type +m68hc11_elf_special_reloc (bfd *abfd ATTRIBUTE_UNUSED, + arelent *reloc_entry, + asymbol *symbol, + void *data ATTRIBUTE_UNUSED, + asection *input_section, + bfd *output_bfd, + char **error_message ATTRIBUTE_UNUSED) +{ + if (output_bfd != (bfd *) NULL + && (symbol->flags & BSF_SECTION_SYM) == 0 + && (! reloc_entry->howto->partial_inplace + || reloc_entry->addend == 0)) + { + reloc_entry->address += input_section->output_offset; + return bfd_reloc_ok; + } + + if (output_bfd != NULL) + return bfd_reloc_continue; + + if (reloc_entry->address > input_section->_cooked_size) + return bfd_reloc_outofrange; + + abort(); +} + +asection * +elf32_m68hc11_gc_mark_hook (asection *sec, + struct bfd_link_info *info ATTRIBUTE_UNUSED, + Elf_Internal_Rela *rel, + struct elf_link_hash_entry *h, + Elf_Internal_Sym *sym) +{ + if (h != NULL) + { + switch (ELF32_R_TYPE (rel->r_info)) + { + default: + switch (h->root.type) + { + case bfd_link_hash_defined: + case bfd_link_hash_defweak: + return h->root.u.def.section; + + case bfd_link_hash_common: + return h->root.u.c.p->section; + + default: + break; + } + } + } + else + return bfd_section_from_elf_index (sec->owner, sym->st_shndx); + + return NULL; +} + +bfd_boolean +elf32_m68hc11_gc_sweep_hook (bfd *abfd ATTRIBUTE_UNUSED, + struct bfd_link_info *info ATTRIBUTE_UNUSED, + asection *sec ATTRIBUTE_UNUSED, + const Elf_Internal_Rela *relocs ATTRIBUTE_UNUSED) +{ + /* We don't use got and plt entries for 68hc11/68hc12. */ + return TRUE; +} + +/* Look through the relocs for a section during the first phase. + Since we don't do .gots or .plts, we just need to consider the + virtual table relocs for gc. */ + +bfd_boolean +elf32_m68hc11_check_relocs (bfd *abfd, struct bfd_link_info *info, + asection *sec, const Elf_Internal_Rela *relocs) +{ + Elf_Internal_Shdr * symtab_hdr; + struct elf_link_hash_entry ** sym_hashes; + struct elf_link_hash_entry ** sym_hashes_end; + const Elf_Internal_Rela * rel; + const Elf_Internal_Rela * rel_end; + + if (info->relocatable) + return TRUE; + + symtab_hdr = & elf_tdata (abfd)->symtab_hdr; + sym_hashes = elf_sym_hashes (abfd); + sym_hashes_end = sym_hashes + symtab_hdr->sh_size / sizeof (Elf32_External_Sym); + if (!elf_bad_symtab (abfd)) + sym_hashes_end -= symtab_hdr->sh_info; + + rel_end = relocs + sec->reloc_count; + + for (rel = relocs; rel < rel_end; rel++) + { + struct elf_link_hash_entry * h; + unsigned long r_symndx; + + r_symndx = ELF32_R_SYM (rel->r_info); + + if (r_symndx < symtab_hdr->sh_info) + h = NULL; + else + h = sym_hashes [r_symndx - symtab_hdr->sh_info]; + + switch (ELF32_R_TYPE (rel->r_info)) + { + /* This relocation describes the C++ object vtable hierarchy. + Reconstruct it for later use during GC. */ + case R_M68HC11_GNU_VTINHERIT: + if (!_bfd_elf32_gc_record_vtinherit (abfd, sec, h, rel->r_offset)) + return FALSE; + break; + + /* This relocation describes which C++ vtable entries are actually + used. Record for later use during GC. */ + case R_M68HC11_GNU_VTENTRY: + if (!_bfd_elf32_gc_record_vtentry (abfd, sec, h, rel->r_addend)) + return FALSE; + break; + } + } + + return TRUE; +} + +static bfd_boolean +m68hc11_get_relocation_value (bfd *abfd, struct bfd_link_info *info, + asection **local_sections, + Elf_Internal_Sym *local_syms, + Elf_Internal_Rela *rel, + const char **name, + bfd_vma *relocation, bfd_boolean *is_far) +{ + Elf_Internal_Shdr *symtab_hdr; + struct elf_link_hash_entry **sym_hashes; + unsigned long r_symndx; + asection *sec; + struct elf_link_hash_entry *h; + Elf_Internal_Sym *sym; + const char* stub_name = 0; + + symtab_hdr = &elf_tdata (abfd)->symtab_hdr; + sym_hashes = elf_sym_hashes (abfd); + + r_symndx = ELF32_R_SYM (rel->r_info); + + /* This is a final link. */ + h = NULL; + sym = NULL; + sec = NULL; + if (r_symndx < symtab_hdr->sh_info) + { + sym = local_syms + r_symndx; + sec = local_sections[r_symndx]; + *relocation = (sec->output_section->vma + + sec->output_offset + + sym->st_value); + *is_far = (sym && (sym->st_other & STO_M68HC12_FAR)); + if (*is_far) + stub_name = (bfd_elf_string_from_elf_section + (abfd, symtab_hdr->sh_link, + sym->st_name)); + } + else + { + h = sym_hashes[r_symndx - symtab_hdr->sh_info]; + while (h->root.type == bfd_link_hash_indirect + || h->root.type == bfd_link_hash_warning) + h = (struct elf_link_hash_entry *) h->root.u.i.link; + if (h->root.type == bfd_link_hash_defined + || h->root.type == bfd_link_hash_defweak) + { + sec = h->root.u.def.section; + *relocation = (h->root.u.def.value + + sec->output_section->vma + + sec->output_offset); + } + else if (h->root.type == bfd_link_hash_undefweak) + *relocation = 0; + else + { + if (!((*info->callbacks->undefined_symbol) + (info, h->root.root.string, abfd, + sec, rel->r_offset, TRUE))) + return FALSE; + *relocation = 0; + } + *is_far = (h && (h->other & STO_M68HC12_FAR)); + stub_name = h->root.root.string; + } + + if (h != NULL) + *name = h->root.root.string; + else + { + *name = (bfd_elf_string_from_elf_section + (abfd, symtab_hdr->sh_link, sym->st_name)); + if (*name == NULL || **name == '\0') + *name = bfd_section_name (input_bfd, sec); + } + + if (*is_far && ELF32_R_TYPE (rel->r_info) == R_M68HC11_16) + { + struct elf32_m68hc11_stub_hash_entry* stub; + struct m68hc11_elf_link_hash_table *htab; + + htab = m68hc11_elf_hash_table (info); + stub = m68hc12_stub_hash_lookup (htab->stub_hash_table, + *name, FALSE, FALSE); + if (stub) + { + *relocation = stub->stub_offset + + stub->stub_sec->output_section->vma + + stub->stub_sec->output_offset; + *is_far = FALSE; + } + } + return TRUE; +} + +/* Relocate a 68hc11/68hc12 ELF section. */ +bfd_boolean +elf32_m68hc11_relocate_section (bfd *output_bfd ATTRIBUTE_UNUSED, + struct bfd_link_info *info, + bfd *input_bfd, asection *input_section, + bfd_byte *contents, Elf_Internal_Rela *relocs, + Elf_Internal_Sym *local_syms, + asection **local_sections) +{ + Elf_Internal_Shdr *symtab_hdr; + struct elf_link_hash_entry **sym_hashes; + Elf_Internal_Rela *rel, *relend; + const char *name; + struct m68hc11_page_info *pinfo; + const struct elf_backend_data * const ebd = get_elf_backend_data (input_bfd); + + symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr; + sym_hashes = elf_sym_hashes (input_bfd); + + /* Get memory bank parameters. */ + m68hc11_elf_get_bank_parameters (info); + pinfo = &m68hc11_elf_hash_table (info)->pinfo; + + rel = relocs; + relend = relocs + input_section->reloc_count; + for (; rel < relend; rel++) + { + int r_type; + arelent arel; + reloc_howto_type *howto; + unsigned long r_symndx; + Elf_Internal_Sym *sym; + asection *sec; + bfd_vma relocation; + bfd_reloc_status_type r = bfd_reloc_undefined; + bfd_vma phys_page; + bfd_vma phys_addr; + bfd_vma insn_addr; + bfd_vma insn_page; + bfd_boolean is_far; + + r_symndx = ELF32_R_SYM (rel->r_info); + r_type = ELF32_R_TYPE (rel->r_info); + + if (r_type == R_M68HC11_GNU_VTENTRY + || r_type == R_M68HC11_GNU_VTINHERIT ) + continue; + + if (info->relocatable) + { + /* This is a relocatable link. We don't have to change + anything, unless the reloc is against a section symbol, + in which case we have to adjust according to where the + section symbol winds up in the output section. */ + if (r_symndx < symtab_hdr->sh_info) + { + sym = local_syms + r_symndx; + if (ELF_ST_TYPE (sym->st_info) == STT_SECTION) + { + sec = local_sections[r_symndx]; + rel->r_addend += sec->output_offset + sym->st_value; + } + } + + continue; + } + (*ebd->elf_info_to_howto_rel) (input_bfd, &arel, rel); + howto = arel.howto; + + m68hc11_get_relocation_value (input_bfd, info, + local_sections, local_syms, + rel, &name, &relocation, &is_far); + + /* Do the memory bank mapping. */ + phys_addr = m68hc11_phys_addr (pinfo, relocation + rel->r_addend); + phys_page = m68hc11_phys_page (pinfo, relocation + rel->r_addend); + switch (r_type) + { + case R_M68HC11_24: + /* Reloc used by 68HC12 call instruction. */ + bfd_put_16 (input_bfd, phys_addr, + (bfd_byte*) contents + rel->r_offset); + bfd_put_8 (input_bfd, phys_page, + (bfd_byte*) contents + rel->r_offset + 2); + r = bfd_reloc_ok; + r_type = R_M68HC11_NONE; + break; + + case R_M68HC11_NONE: + r = bfd_reloc_ok; + break; + + case R_M68HC11_LO16: + /* Reloc generated by %addr(expr) gas to obtain the + address as mapped in the memory bank window. */ + relocation = phys_addr; + break; + + case R_M68HC11_PAGE: + /* Reloc generated by %page(expr) gas to obtain the + page number associated with the address. */ + relocation = phys_page; + break; + + case R_M68HC11_16: + /* Get virtual address of instruction having the relocation. */ + if (is_far) + { + const char* msg; + char* buf; + msg = _("Reference to the far symbol `%s' using a wrong " + "relocation may result in incorrect execution"); + buf = alloca (strlen (msg) + strlen (name) + 10); + sprintf (buf, msg, name); + + (* info->callbacks->warning) + (info, buf, name, input_bfd, NULL, rel->r_offset); + } + + /* Get virtual address of instruction having the relocation. */ + insn_addr = input_section->output_section->vma + + input_section->output_offset + + rel->r_offset; + + insn_page = m68hc11_phys_page (pinfo, insn_addr); + + if (m68hc11_addr_is_banked (pinfo, relocation + rel->r_addend) + && m68hc11_addr_is_banked (pinfo, insn_addr) + && phys_page != insn_page) + { + const char* msg; + char* buf; + + msg = _("banked address [%lx:%04lx] (%lx) is not in the same bank " + "as current banked address [%lx:%04lx] (%lx)"); + + buf = alloca (strlen (msg) + 128); + sprintf (buf, msg, phys_page, phys_addr, + (long) (relocation + rel->r_addend), + insn_page, m68hc11_phys_addr (pinfo, insn_addr), + (long) (insn_addr)); + if (!((*info->callbacks->warning) + (info, buf, name, input_bfd, input_section, + rel->r_offset))) + return FALSE; + break; + } + if (phys_page != 0 && insn_page == 0) + { + const char* msg; + char* buf; + + msg = _("reference to a banked address [%lx:%04lx] in the " + "normal address space at %04lx"); + + buf = alloca (strlen (msg) + 128); + sprintf (buf, msg, phys_page, phys_addr, insn_addr); + if (!((*info->callbacks->warning) + (info, buf, name, input_bfd, input_section, + insn_addr))) + return FALSE; + + relocation = phys_addr; + break; + } + + /* If this is a banked address use the phys_addr so that + we stay in the banked window. */ + if (m68hc11_addr_is_banked (pinfo, relocation + rel->r_addend)) + relocation = phys_addr; + break; + } + if (r_type != R_M68HC11_NONE) + r = _bfd_final_link_relocate (howto, input_bfd, input_section, + contents, rel->r_offset, + relocation, rel->r_addend); + + if (r != bfd_reloc_ok) + { + const char * msg = (const char *) 0; + + switch (r) + { + case bfd_reloc_overflow: + if (!((*info->callbacks->reloc_overflow) + (info, name, howto->name, (bfd_vma) 0, + input_bfd, input_section, rel->r_offset))) + return FALSE; + break; + + case bfd_reloc_undefined: + if (!((*info->callbacks->undefined_symbol) + (info, name, input_bfd, input_section, + rel->r_offset, TRUE))) + return FALSE; + break; + + case bfd_reloc_outofrange: + msg = _ ("internal error: out of range error"); + goto common_error; + + case bfd_reloc_notsupported: + msg = _ ("internal error: unsupported relocation error"); + goto common_error; + + case bfd_reloc_dangerous: + msg = _ ("internal error: dangerous error"); + goto common_error; + + default: + msg = _ ("internal error: unknown error"); + /* fall through */ + + common_error: + if (!((*info->callbacks->warning) + (info, msg, name, input_bfd, input_section, + rel->r_offset))) + return FALSE; + break; + } + } + } + + return TRUE; +} + + + +/* Set and control ELF flags in ELF header. */ + +bfd_boolean +_bfd_m68hc11_elf_set_private_flags (bfd *abfd, flagword flags) +{ + BFD_ASSERT (!elf_flags_init (abfd) + || elf_elfheader (abfd)->e_flags == flags); + + elf_elfheader (abfd)->e_flags = flags; + elf_flags_init (abfd) = TRUE; + return TRUE; +} + +/* Merge backend specific data from an object file to the output + object file when linking. */ + +bfd_boolean +_bfd_m68hc11_elf_merge_private_bfd_data (bfd *ibfd, bfd *obfd) +{ + flagword old_flags; + flagword new_flags; + bfd_boolean ok = TRUE; + + /* Check if we have the same endianess */ + if (!_bfd_generic_verify_endian_match (ibfd, obfd)) + return FALSE; + + if (bfd_get_flavour (ibfd) != bfd_target_elf_flavour + || bfd_get_flavour (obfd) != bfd_target_elf_flavour) + return TRUE; + + new_flags = elf_elfheader (ibfd)->e_flags; + elf_elfheader (obfd)->e_flags |= new_flags & EF_M68HC11_ABI; + old_flags = elf_elfheader (obfd)->e_flags; + + if (! elf_flags_init (obfd)) + { + elf_flags_init (obfd) = TRUE; + elf_elfheader (obfd)->e_flags = new_flags; + elf_elfheader (obfd)->e_ident[EI_CLASS] + = elf_elfheader (ibfd)->e_ident[EI_CLASS]; + + if (bfd_get_arch (obfd) == bfd_get_arch (ibfd) + && bfd_get_arch_info (obfd)->the_default) + { + if (! bfd_set_arch_mach (obfd, bfd_get_arch (ibfd), + bfd_get_mach (ibfd))) + return FALSE; + } + + return TRUE; + } + + /* Check ABI compatibility. */ + if ((new_flags & E_M68HC11_I32) != (old_flags & E_M68HC11_I32)) + { + (*_bfd_error_handler) + (_("%s: linking files compiled for 16-bit integers (-mshort) " + "and others for 32-bit integers"), + bfd_archive_filename (ibfd)); + ok = FALSE; + } + if ((new_flags & E_M68HC11_F64) != (old_flags & E_M68HC11_F64)) + { + (*_bfd_error_handler) + (_("%s: linking files compiled for 32-bit double (-fshort-double) " + "and others for 64-bit double"), + bfd_archive_filename (ibfd)); + ok = FALSE; + } + + /* Processor compatibility. */ + if (!EF_M68HC11_CAN_MERGE_MACH (new_flags, old_flags)) + { + (*_bfd_error_handler) + (_("%s: linking files compiled for HCS12 with " + "others compiled for HC12"), + bfd_archive_filename (ibfd)); + ok = FALSE; + } + new_flags = ((new_flags & ~EF_M68HC11_MACH_MASK) + | (EF_M68HC11_MERGE_MACH (new_flags, old_flags))); + + elf_elfheader (obfd)->e_flags = new_flags; + + new_flags &= ~(EF_M68HC11_ABI | EF_M68HC11_MACH_MASK); + old_flags &= ~(EF_M68HC11_ABI | EF_M68HC11_MACH_MASK); + + /* Warn about any other mismatches */ + if (new_flags != old_flags) + { + (*_bfd_error_handler) + (_("%s: uses different e_flags (0x%lx) fields than previous modules (0x%lx)"), + bfd_archive_filename (ibfd), (unsigned long) new_flags, + (unsigned long) old_flags); + ok = FALSE; + } + + if (! ok) + { + bfd_set_error (bfd_error_bad_value); + return FALSE; + } + + return TRUE; +} + +bfd_boolean +_bfd_m68hc11_elf_print_private_bfd_data (bfd *abfd, void *ptr) +{ + FILE *file = (FILE *) ptr; + + BFD_ASSERT (abfd != NULL && ptr != NULL); + + /* Print normal ELF private data. */ + _bfd_elf_print_private_bfd_data (abfd, ptr); + + /* xgettext:c-format */ + fprintf (file, _("private flags = %lx:"), elf_elfheader (abfd)->e_flags); + + if (elf_elfheader (abfd)->e_flags & E_M68HC11_I32) + fprintf (file, _("[abi=32-bit int, ")); + else + fprintf (file, _("[abi=16-bit int, ")); + + if (elf_elfheader (abfd)->e_flags & E_M68HC11_F64) + fprintf (file, _("64-bit double, ")); + else + fprintf (file, _("32-bit double, ")); + + if (strcmp (bfd_get_target (abfd), "elf32-m68hc11") == 0) + fprintf (file, _("cpu=HC11]")); + else if (elf_elfheader (abfd)->e_flags & EF_M68HCS12_MACH) + fprintf (file, _("cpu=HCS12]")); + else + fprintf (file, _("cpu=HC12]")); + + if (elf_elfheader (abfd)->e_flags & E_M68HC12_BANKS) + fprintf (file, _(" [memory=bank-model]")); + else + fprintf (file, _(" [memory=flat]")); + + fputc ('\n', file); + + return TRUE; +} + +static void scan_sections_for_abi (bfd *abfd ATTRIBUTE_UNUSED, + asection *asect, void *arg) +{ + struct m68hc11_scan_param* p = (struct m68hc11_scan_param*) arg; + + if (asect->vma >= p->pinfo->bank_virtual) + p->use_memory_banks = TRUE; +} + +/* Tweak the OSABI field of the elf header. */ + +void +elf32_m68hc11_post_process_headers (bfd *abfd, struct bfd_link_info *link_info) +{ + struct m68hc11_scan_param param; + + if (link_info == 0) + return; + + m68hc11_elf_get_bank_parameters (link_info); + + param.use_memory_banks = FALSE; + param.pinfo = &m68hc11_elf_hash_table (link_info)->pinfo; + bfd_map_over_sections (abfd, scan_sections_for_abi, ¶m); + if (param.use_memory_banks) + { + Elf_Internal_Ehdr * i_ehdrp; + + i_ehdrp = elf_elfheader (abfd); + i_ehdrp->e_flags |= E_M68HC12_BANKS; + } +} + diff --git a/bfd/elf32-m68hc1x.h b/bfd/elf32-m68hc1x.h new file mode 100644 index 0000000..5964023 --- /dev/null +++ b/bfd/elf32-m68hc1x.h @@ -0,0 +1,196 @@ +/* Motorola 68HC11/68HC12-specific support for 32-bit ELF + Copyright 2003 Free Software Foundation, Inc. + Contributed by Stephane Carrez (stcarrez@nerim.fr) + +This file is part of BFD, the Binary File Descriptor library. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef _ELF32_M68HC1X_H +#define _ELF32_M68HC1X_H + +#include "elf-bfd.h" +#include "bfdlink.h" +#include "elf/m68hc11.h" + +/* Name of symbols exported by HC11/HC12 linker when there is a memory + bank window. */ +#define BFD_M68HC11_BANK_START_NAME "__bank_start" +#define BFD_M68HC11_BANK_SIZE_NAME "__bank_size" +#define BFD_M68HC11_BANK_VIRTUAL_NAME "__bank_virtual" + +/* Set and control ELF flags in ELF header. */ +extern bfd_boolean _bfd_m68hc11_elf_merge_private_bfd_data (bfd*,bfd*); +extern bfd_boolean _bfd_m68hc11_elf_set_private_flags (bfd*,flagword); +extern bfd_boolean _bfd_m68hc11_elf_print_private_bfd_data (bfd*, void*); + +/* This hash entry is used to record a trampoline that must be generated + to call a far function using a normal calling convention ('jsr'). + The trampoline is used when a pointer to a far function is used. + It takes care of installing the proper memory bank as well as creating + the 'call/rtc' calling convention. */ +struct elf32_m68hc11_stub_hash_entry { + + /* Base hash table entry structure. */ + struct bfd_hash_entry root; + + /* The stub section. */ + asection *stub_sec; + + /* Offset within stub_sec of the beginning of this stub. */ + bfd_vma stub_offset; + + /* Given the symbol's value and its section we can determine its final + value when building the stubs (so the stub knows where to jump. */ + bfd_vma target_value; + asection *target_section; +}; + +/* Placeholder for the parameters to compute memory page and physical address. + The following formulas are used: + + sym > bank_virtual => + %addr(sym) = (((sym - bank_virtual) & bank_mask) + bank_physical + %page(sym) = (((sym - bank_virtual) >> bank_shift) % 256 + + sym < bank_virtual => + %addr(sym) = sym + %page(sym) = 0 + + + These parameters are obtained from the symbol table by looking + at the following: + + __bank_start Symbol marking the start of memory bank window + (bank_physical) + __bank_virtual Logical address of symbols for which the transformation + must be computed + __bank_page_size Size in bytes of page size (this is *NOT* the memory + bank window size and the window size is always + less or equal to the page size) + + For 68HC12, the window is at 0x8000 and the page size is 16K (full window). + For 68HC11 this is board specific (implemented by external hardware). + +*/ +struct m68hc11_page_info +{ + bfd_vma bank_virtual; + bfd_vma bank_physical; + bfd_vma bank_physical_end; + bfd_vma bank_mask; + bfd_vma bank_size; + int bank_shift; + int bank_param_initialized; + bfd_vma trampoline_addr; +}; + +struct m68hc11_elf_link_hash_table +{ + struct elf_link_hash_table root; + struct m68hc11_page_info pinfo; + + /* The stub hash table. */ + struct bfd_hash_table* stub_hash_table; + + /* Linker stub bfd. */ + bfd *stub_bfd; + + asection* stub_section; + asection* tramp_section; + + /* Linker call-backs. */ + asection * (*add_stub_section) PARAMS ((const char *, asection *)); + + /* Assorted information used by elf32_hppa_size_stubs. */ + unsigned int bfd_count; + int top_index; + asection **input_list; + + /* Small local sym to section mapping cache. */ + struct sym_sec_cache sym_sec; + + bfd_boolean (* size_one_stub) PARAMS((struct bfd_hash_entry*, void*)); + bfd_boolean (* build_one_stub) PARAMS((struct bfd_hash_entry*, void*)); +}; + +/* Get the Sparc64 ELF linker hash table from a link_info structure. */ + +#define m68hc11_elf_hash_table(p) \ + ((struct m68hc11_elf_link_hash_table *) ((p)->hash)) + +/* Create a 68HC11/68HC12 ELF linker hash table. */ + +extern struct m68hc11_elf_link_hash_table* m68hc11_elf_hash_table_create + (bfd*); +extern void m68hc11_elf_bfd_link_hash_table_free (struct bfd_link_hash_table*); + +extern void m68hc11_elf_get_bank_parameters (struct bfd_link_info*); + +/* Return 1 if the address is in banked memory. + This can be applied to a virtual address and to a physical address. */ +extern int m68hc11_addr_is_banked (struct m68hc11_page_info*, bfd_vma); + +/* Return the physical address seen by the processor, taking + into account banked memory. */ +extern bfd_vma m68hc11_phys_addr (struct m68hc11_page_info*, bfd_vma); + +/* Return the page number corresponding to an address in banked memory. */ +extern bfd_vma m68hc11_phys_page (struct m68hc11_page_info*, bfd_vma); + +bfd_reloc_status_type m68hc11_elf_ignore_reloc + (bfd *abfd, arelent *reloc_entry, + asymbol *symbol, void *data, asection *input_section, + bfd *output_bfd, char **error_message); +bfd_reloc_status_type m68hc11_elf_special_reloc + (bfd *abfd, arelent *reloc_entry, + asymbol *symbol, void *data, asection *input_section, + bfd *output_bfd, char **error_message); + +/* GC mark and sweep. */ +asection *elf32_m68hc11_gc_mark_hook + (asection *sec, struct bfd_link_info *info, + Elf_Internal_Rela *rel, struct elf_link_hash_entry *h, + Elf_Internal_Sym *sym); +bfd_boolean elf32_m68hc11_gc_sweep_hook + (bfd *abfd, struct bfd_link_info *info, + asection *sec, const Elf_Internal_Rela *relocs); +bfd_boolean elf32_m68hc11_check_relocs + (bfd * abfd, struct bfd_link_info * info, + asection * sec, const Elf_Internal_Rela * relocs); +bfd_boolean elf32_m68hc11_relocate_section + (bfd *output_bfd, struct bfd_link_info *info, + bfd *input_bfd, asection *input_section, + bfd_byte *contents, Elf_Internal_Rela *relocs, + Elf_Internal_Sym *local_syms, asection **local_sections); + +bfd_boolean elf32_m68hc11_add_symbol_hook + (bfd *abfd, struct bfd_link_info *info, + const Elf_Internal_Sym *sym, const char **namep, + flagword *flagsp, asection **secp, + bfd_vma *valp); + +/* Tweak the OSABI field of the elf header. */ + +extern void elf32_m68hc11_post_process_headers (bfd*, struct bfd_link_info*); + +int elf32_m68hc11_setup_section_lists (bfd *, struct bfd_link_info *); + +bfd_boolean elf32_m68hc11_size_stubs + (bfd *, bfd *, struct bfd_link_info *, + asection * (*) (const char *, asection *)); + +bfd_boolean elf32_m68hc11_build_stubs (bfd* abfd, struct bfd_link_info *); +#endif diff --git a/bfd/elf32-msp430.c b/bfd/elf32-msp430.c new file mode 100644 index 0000000..306a798 --- /dev/null +++ b/bfd/elf32-msp430.c @@ -0,0 +1,728 @@ +/* MSP430-specific support for 32-bit ELF + Copyright (C) 2002, 2003 Free Software Foundation, Inc. + Contributed by Dmitry Diky + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include "bfd.h" +#include "sysdep.h" +#include "libiberty.h" +#include "libbfd.h" +#include "elf-bfd.h" +#include "elf/msp430.h" + +static reloc_howto_type *bfd_elf32_bfd_reloc_type_lookup + PARAMS ((bfd *, bfd_reloc_code_real_type)); + +static void msp430_info_to_howto_rela + PARAMS ((bfd *, arelent *, Elf_Internal_Rela *)); + +static asection *elf32_msp430_gc_mark_hook + PARAMS ((asection *, struct bfd_link_info *, Elf_Internal_Rela *, + struct elf_link_hash_entry *, Elf_Internal_Sym *)); + +static bfd_boolean elf32_msp430_gc_sweep_hook + PARAMS ((bfd *, struct bfd_link_info *, asection *, + const Elf_Internal_Rela *)); + +static bfd_boolean elf32_msp430_check_relocs + PARAMS ((bfd *, struct bfd_link_info *, asection *, + const Elf_Internal_Rela *)); + +static bfd_reloc_status_type msp430_final_link_relocate + PARAMS ((reloc_howto_type *, bfd *, asection *, bfd_byte *, + Elf_Internal_Rela *, bfd_vma)); + +static bfd_boolean elf32_msp430_relocate_section + PARAMS ((bfd *, struct bfd_link_info *, bfd *, asection *, bfd_byte *, + Elf_Internal_Rela *, Elf_Internal_Sym *, asection **)); + +static void bfd_elf_msp430_final_write_processing + PARAMS ((bfd *, bfd_boolean)); + +static bfd_boolean elf32_msp430_object_p + PARAMS ((bfd *)); + +static void elf32_msp430_post_process_headers + PARAMS ((bfd *, struct bfd_link_info *)); + +/* Use RELA instead of REL. */ +#undef USE_REL + +static reloc_howto_type elf_msp430_howto_table[] = +{ + HOWTO (R_MSP430_NONE, /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 32, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_bitfield, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_MSP430_NONE", /* name */ + FALSE, /* partial_inplace */ + 0, /* src_mask */ + 0, /* dst_mask */ + FALSE), /* pcrel_offset */ + + HOWTO (R_MSP430_32, /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 32, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_bitfield, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_MSP430_32", /* name */ + FALSE, /* partial_inplace */ + 0xffffffff, /* src_mask */ + 0xffffffff, /* dst_mask */ + FALSE), /* pcrel_offset */ + + /* A 13 bit PC relative relocation. */ + HOWTO (R_MSP430_10_PCREL, /* type */ + 1, /* rightshift */ + 1, /* size (0 = byte, 1 = short, 2 = long) */ + 10, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_bitfield, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_MSP430_13_PCREL", /* name */ + FALSE, /* partial_inplace */ + 0xfff, /* src_mask */ + 0xfff, /* dst_mask */ + TRUE), /* pcrel_offset */ + + /* A 16 bit absolute relocation. */ + HOWTO (R_MSP430_16, /* type */ + 0, /* rightshift */ + 1, /* size (0 = byte, 1 = short, 2 = long) */ + 16, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont,/* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_MSP430_16", /* name */ + FALSE, /* partial_inplace */ + 0xffff, /* src_mask */ + 0xffff, /* dst_mask */ + FALSE), /* pcrel_offset */ + + /* A 16 bit absolute relocation for command address. */ + HOWTO (R_MSP430_16_PCREL, /* type */ + 1, /* rightshift */ + 1, /* size (0 = byte, 1 = short, 2 = long) */ + 16, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont,/* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_MSP430_16_PCREL", /* name */ + FALSE, /* partial_inplace */ + 0xffff, /* src_mask */ + 0xffff, /* dst_mask */ + TRUE), /* pcrel_offset */ + + /* A 16 bit absolute relocation, byte operations. */ + HOWTO (R_MSP430_16_BYTE, /* type */ + 0, /* rightshift */ + 1, /* size (0 = byte, 1 = short, 2 = long) */ + 16, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont,/* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_MSP430_16_BYTE", /* name */ + FALSE, /* partial_inplace */ + 0xffff, /* src_mask */ + 0xffff, /* dst_mask */ + FALSE), /* pcrel_offset */ + + /* A 16 bit absolute relocation for command address. */ + HOWTO (R_MSP430_16_PCREL_BYTE,/* type */ + 1, /* rightshift */ + 1, /* size (0 = byte, 1 = short, 2 = long) */ + 16, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont,/* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_MSP430_16_PCREL_BYTE", /* name */ + FALSE, /* partial_inplace */ + 0xffff, /* src_mask */ + 0xffff, /* dst_mask */ + TRUE) /* pcrel_offset */ +}; + +/* Map BFD reloc types to MSP430 ELF reloc types. */ + +struct msp430_reloc_map +{ + bfd_reloc_code_real_type bfd_reloc_val; + unsigned int elf_reloc_val; +}; + +static const struct msp430_reloc_map msp430_reloc_map[] = + { + {BFD_RELOC_NONE, R_MSP430_NONE}, + {BFD_RELOC_32, R_MSP430_32}, + {BFD_RELOC_MSP430_10_PCREL, R_MSP430_10_PCREL}, + {BFD_RELOC_16, R_MSP430_16_BYTE}, + {BFD_RELOC_MSP430_16_PCREL, R_MSP430_16_PCREL}, + {BFD_RELOC_MSP430_16, R_MSP430_16}, + {BFD_RELOC_MSP430_16_PCREL_BYTE, R_MSP430_16_PCREL_BYTE}, + {BFD_RELOC_MSP430_16_BYTE, R_MSP430_16_BYTE} + }; + +static reloc_howto_type * +bfd_elf32_bfd_reloc_type_lookup (abfd, code) + bfd *abfd ATTRIBUTE_UNUSED; + bfd_reloc_code_real_type code; +{ + unsigned int i; + + for (i = 0; i < ARRAY_SIZE (msp430_reloc_map); i++) + if (msp430_reloc_map[i].bfd_reloc_val == code) + return &elf_msp430_howto_table[msp430_reloc_map[i].elf_reloc_val]; + + return NULL; +} + +/* Set the howto pointer for an MSP430 ELF reloc. */ + +static void +msp430_info_to_howto_rela (abfd, cache_ptr, dst) + bfd *abfd ATTRIBUTE_UNUSED; + arelent *cache_ptr; + Elf_Internal_Rela *dst; +{ + unsigned int r_type; + + r_type = ELF32_R_TYPE (dst->r_info); + BFD_ASSERT (r_type < (unsigned int) R_MSP430_max); + cache_ptr->howto = &elf_msp430_howto_table[r_type]; +} + +static asection * +elf32_msp430_gc_mark_hook (sec, info, rel, h, sym) + asection *sec; + struct bfd_link_info *info ATTRIBUTE_UNUSED; + Elf_Internal_Rela *rel; + struct elf_link_hash_entry *h; + Elf_Internal_Sym *sym; +{ + if (h != NULL) + { + switch (ELF32_R_TYPE (rel->r_info)) + { + default: + switch (h->root.type) + { + case bfd_link_hash_defined: + case bfd_link_hash_defweak: + return h->root.u.def.section; + + case bfd_link_hash_common: + return h->root.u.c.p->section; + + default: + break; + } + } + } + else + return bfd_section_from_elf_index (sec->owner, sym->st_shndx); + + return NULL; +} + +static bfd_boolean +elf32_msp430_gc_sweep_hook (abfd, info, sec, relocs) + bfd *abfd ATTRIBUTE_UNUSED; + struct bfd_link_info *info ATTRIBUTE_UNUSED; + asection *sec ATTRIBUTE_UNUSED; + const Elf_Internal_Rela *relocs ATTRIBUTE_UNUSED; +{ + /* We don't use got and plt entries for msp430. */ + return TRUE; +} + +/* Look through the relocs for a section during the first phase. + Since we don't do .gots or .plts, we just need to consider the + virtual table relocs for gc. */ + +static bfd_boolean +elf32_msp430_check_relocs (abfd, info, sec, relocs) + bfd *abfd; + struct bfd_link_info *info; + asection *sec; + const Elf_Internal_Rela *relocs; +{ + Elf_Internal_Shdr *symtab_hdr; + struct elf_link_hash_entry **sym_hashes, **sym_hashes_end; + const Elf_Internal_Rela *rel; + const Elf_Internal_Rela *rel_end; + + if (info->relocatable) + return TRUE; + + symtab_hdr = &elf_tdata (abfd)->symtab_hdr; + sym_hashes = elf_sym_hashes (abfd); + sym_hashes_end = + sym_hashes + symtab_hdr->sh_size / sizeof (Elf32_External_Sym); + if (!elf_bad_symtab (abfd)) + sym_hashes_end -= symtab_hdr->sh_info; + + rel_end = relocs + sec->reloc_count; + for (rel = relocs; rel < rel_end; rel++) + { + struct elf_link_hash_entry *h; + unsigned long r_symndx; + + r_symndx = ELF32_R_SYM (rel->r_info); + if (r_symndx < symtab_hdr->sh_info) + h = NULL; + else + h = sym_hashes[r_symndx - symtab_hdr->sh_info]; + } + + return TRUE; +} + +/* Perform a single relocation. By default we use the standard BFD + routines, but a few relocs, we have to do them ourselves. */ + +static bfd_reloc_status_type +msp430_final_link_relocate (howto, input_bfd, input_section, + contents, rel, relocation) + reloc_howto_type *howto; + bfd *input_bfd; + asection *input_section; + bfd_byte *contents; + Elf_Internal_Rela *rel; + bfd_vma relocation; +{ + bfd_reloc_status_type r = bfd_reloc_ok; + bfd_vma x; + bfd_signed_vma srel; + + switch (howto->type) + { + case R_MSP430_10_PCREL: + contents += rel->r_offset; + srel = (bfd_signed_vma) relocation; + srel += rel->r_addend; + srel -= rel->r_offset; + srel -= 2; /* Branch instructions add 2 to the PC... */ + srel -= (input_section->output_section->vma + + input_section->output_offset); + + if (srel & 1) + return bfd_reloc_outofrange; + + /* MSP430 addresses commands as words. */ + srel >>= 1; + + /* Check for an overflow. */ + if (srel < -512 || srel > 511) + return bfd_reloc_overflow; + + x = bfd_get_16 (input_bfd, contents); + x = (x & 0xfc00) | (srel & 0x3ff); + bfd_put_16 (input_bfd, x, contents); + break; + + case R_MSP430_16_PCREL: + contents += rel->r_offset; + srel = (bfd_signed_vma) relocation; + srel += rel->r_addend; + srel -= rel->r_offset; + /* Only branch instructions add 2 to the PC... */ + srel -= (input_section->output_section->vma + + input_section->output_offset); + + if (srel & 1) + return bfd_reloc_outofrange; + + bfd_put_16 (input_bfd, srel & 0xffff, contents); + break; + + case R_MSP430_16_PCREL_BYTE: + contents += rel->r_offset; + srel = (bfd_signed_vma) relocation; + srel += rel->r_addend; + srel -= rel->r_offset; + /* Only branch instructions add 2 to the PC... */ + srel -= (input_section->output_section->vma + + input_section->output_offset); + + bfd_put_16 (input_bfd, srel & 0xffff, contents); + break; + + case R_MSP430_16_BYTE: + contents += rel->r_offset; + srel = (bfd_signed_vma) relocation; + srel += rel->r_addend; + bfd_put_16 (input_bfd, srel & 0xffff, contents); + break; + + case R_MSP430_16: + contents += rel->r_offset; + srel = (bfd_signed_vma) relocation; + srel += rel->r_addend; + + if (srel & 1) + return bfd_reloc_notsupported; + + bfd_put_16 (input_bfd, srel & 0xffff, contents); + break; + + default: + r = _bfd_final_link_relocate (howto, input_bfd, input_section, + contents, rel->r_offset, + relocation, rel->r_addend); + } + + return r; +} + +/* Relocate an MSP430 ELF section. */ + +static bfd_boolean +elf32_msp430_relocate_section (output_bfd, info, input_bfd, input_section, + contents, relocs, local_syms, local_sections) + bfd *output_bfd ATTRIBUTE_UNUSED; + struct bfd_link_info *info; + bfd *input_bfd; + asection *input_section; + bfd_byte *contents; + Elf_Internal_Rela *relocs; + Elf_Internal_Sym *local_syms; + asection **local_sections; +{ + Elf_Internal_Shdr *symtab_hdr; + struct elf_link_hash_entry **sym_hashes; + Elf_Internal_Rela *rel; + Elf_Internal_Rela *relend; + + symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr; + sym_hashes = elf_sym_hashes (input_bfd); + relend = relocs + input_section->reloc_count; + + for (rel = relocs; rel < relend; rel++) + { + reloc_howto_type *howto; + unsigned long r_symndx; + Elf_Internal_Sym *sym; + asection *sec; + struct elf_link_hash_entry *h; + bfd_vma relocation; + bfd_reloc_status_type r; + const char *name = NULL; + int r_type; + + /* This is a final link. */ + + r_type = ELF32_R_TYPE (rel->r_info); + r_symndx = ELF32_R_SYM (rel->r_info); + howto = elf_msp430_howto_table + ELF32_R_TYPE (rel->r_info); + h = NULL; + sym = NULL; + sec = NULL; + + if (r_symndx < symtab_hdr->sh_info) + { + sym = local_syms + r_symndx; + sec = local_sections[r_symndx]; + relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel); + + name = bfd_elf_string_from_elf_section + (input_bfd, symtab_hdr->sh_link, sym->st_name); + name = (name == NULL) ? bfd_section_name (input_bfd, sec) : name; + } + else + { + h = sym_hashes[r_symndx - symtab_hdr->sh_info]; + + while (h->root.type == bfd_link_hash_indirect + || h->root.type == bfd_link_hash_warning) + h = (struct elf_link_hash_entry *) h->root.u.i.link; + + name = h->root.root.string; + + if (h->root.type == bfd_link_hash_defined + || h->root.type == bfd_link_hash_defweak) + { + sec = h->root.u.def.section; + relocation = (h->root.u.def.value + + sec->output_section->vma + sec->output_offset); + } + else if (h->root.type == bfd_link_hash_undefweak) + { + relocation = 0; + } + else + { + if (!((*info->callbacks->undefined_symbol) + (info, h->root.root.string, input_bfd, + input_section, rel->r_offset, TRUE))) + return FALSE; + relocation = 0; + } + } + + r = msp430_final_link_relocate (howto, input_bfd, input_section, + contents, rel, relocation); + + if (r != bfd_reloc_ok) + { + const char *msg = (const char *) NULL; + + switch (r) + { + case bfd_reloc_overflow: + r = info->callbacks->reloc_overflow + (info, name, howto->name, (bfd_vma) 0, + input_bfd, input_section, rel->r_offset); + break; + + case bfd_reloc_undefined: + r = info->callbacks->undefined_symbol + (info, name, input_bfd, input_section, rel->r_offset, TRUE); + break; + + case bfd_reloc_outofrange: + msg = _("internal error: out of range error"); + break; + + case bfd_reloc_notsupported: + msg = _("internal error: unsupported relocation error"); + break; + + case bfd_reloc_dangerous: + msg = _("internal error: dangerous relocation"); + break; + + default: + msg = _("internal error: unknown error"); + break; + } + + if (msg) + r = info->callbacks->warning + (info, msg, name, input_bfd, input_section, rel->r_offset); + + if (!r) + return FALSE; + } + + } + + return TRUE; +} + +/* The final processing done just before writing out a MSP430 ELF object + file. This gets the MSP430 architecture right based on the machine + number. */ + +static void +bfd_elf_msp430_final_write_processing (abfd, linker) + bfd *abfd; + bfd_boolean linker ATTRIBUTE_UNUSED; +{ + unsigned long val; + + switch (bfd_get_mach (abfd)) + { + default: + case bfd_mach_msp110: + val = E_MSP430_MACH_MSP430x11x1; + break; + + case bfd_mach_msp11: + val = E_MSP430_MACH_MSP430x11; + break; + + case bfd_mach_msp12: + val = E_MSP430_MACH_MSP430x12; + break; + + case bfd_mach_msp13: + val = E_MSP430_MACH_MSP430x13; + break; + + case bfd_mach_msp14: + val = E_MSP430_MACH_MSP430x14; + break; + + case bfd_mach_msp15: + val = E_MSP430_MACH_MSP430x15; + break; + + case bfd_mach_msp16: + val = E_MSP430_MACH_MSP430x16; + break; + + case bfd_mach_msp31: + val = E_MSP430_MACH_MSP430x31; + break; + + case bfd_mach_msp32: + val = E_MSP430_MACH_MSP430x32; + break; + + case bfd_mach_msp33: + val = E_MSP430_MACH_MSP430x33; + break; + + case bfd_mach_msp41: + val = E_MSP430_MACH_MSP430x41; + break; + + case bfd_mach_msp42: + val = E_MSP430_MACH_MSP430x42; + break; + + case bfd_mach_msp43: + val = E_MSP430_MACH_MSP430x43; + break; + + case bfd_mach_msp44: + val = E_MSP430_MACH_MSP430x44; + break; + } + + elf_elfheader (abfd)->e_machine = EM_MSP430; + elf_elfheader (abfd)->e_flags &= ~EF_MSP430_MACH; + elf_elfheader (abfd)->e_flags |= val; +} + +/* Set the right machine number. */ + +static bfd_boolean +elf32_msp430_object_p (abfd) + bfd *abfd; +{ + int e_set = bfd_mach_msp14; + + if (elf_elfheader (abfd)->e_machine == EM_MSP430 + || elf_elfheader (abfd)->e_machine == EM_MSP430_OLD) + { + int e_mach = elf_elfheader (abfd)->e_flags & EF_MSP430_MACH; + + switch (e_mach) + { + default: + case E_MSP430_MACH_MSP430x11: + e_set = bfd_mach_msp11; + break; + + case E_MSP430_MACH_MSP430x11x1: + e_set = bfd_mach_msp110; + break; + + case E_MSP430_MACH_MSP430x12: + e_set = bfd_mach_msp12; + break; + + case E_MSP430_MACH_MSP430x13: + e_set = bfd_mach_msp13; + break; + + case E_MSP430_MACH_MSP430x14: + e_set = bfd_mach_msp14; + break; + + case E_MSP430_MACH_MSP430x15: + e_set = bfd_mach_msp15; + break; + + case E_MSP430_MACH_MSP430x16: + e_set = bfd_mach_msp16; + break; + + case E_MSP430_MACH_MSP430x31: + e_set = bfd_mach_msp31; + break; + + case E_MSP430_MACH_MSP430x32: + e_set = bfd_mach_msp32; + break; + + case E_MSP430_MACH_MSP430x33: + e_set = bfd_mach_msp33; + break; + + case E_MSP430_MACH_MSP430x41: + e_set = bfd_mach_msp41; + break; + + case E_MSP430_MACH_MSP430x42: + e_set = bfd_mach_msp42; + break; + + case E_MSP430_MACH_MSP430x43: + e_set = bfd_mach_msp43; + break; + + case E_MSP430_MACH_MSP430x44: + e_set = bfd_mach_msp44; + break; + } + } + + return bfd_default_set_arch_mach (abfd, bfd_arch_msp430, e_set); +} + +static void +elf32_msp430_post_process_headers (abfd, link_info) + bfd *abfd; + struct bfd_link_info *link_info ATTRIBUTE_UNUSED; +{ + Elf_Internal_Ehdr *i_ehdrp; /* ELF file header, internal form. */ + + i_ehdrp = elf_elfheader (abfd); + +#ifndef ELFOSABI_STANDALONE +#define ELFOSABI_STANDALONE 255 +#endif + + i_ehdrp->e_ident[EI_OSABI] = ELFOSABI_STANDALONE; +} + + +#define ELF_ARCH bfd_arch_msp430 +#define ELF_MACHINE_CODE EM_MSP430 +#define ELF_MACHINE_ALT1 EM_MSP430_OLD +#define ELF_MAXPAGESIZE 1 + +#define TARGET_LITTLE_SYM bfd_elf32_msp430_vec +#define TARGET_LITTLE_NAME "elf32-msp430" + +#define elf_info_to_howto msp430_info_to_howto_rela +#define elf_info_to_howto_rel NULL +#define elf_backend_relocate_section elf32_msp430_relocate_section +#define elf_backend_gc_mark_hook elf32_msp430_gc_mark_hook +#define elf_backend_gc_sweep_hook elf32_msp430_gc_sweep_hook +#define elf_backend_check_relocs elf32_msp430_check_relocs +#define elf_backend_can_gc_sections 1 +#define elf_backend_final_write_processing bfd_elf_msp430_final_write_processing +#define elf_backend_object_p elf32_msp430_object_p +#define elf_backend_post_process_headers elf32_msp430_post_process_headers + +#include "elf32-target.h" diff --git a/bfd/elf32-ppc.h b/bfd/elf32-ppc.h new file mode 100644 index 0000000..fa2c585 --- /dev/null +++ b/bfd/elf32-ppc.h @@ -0,0 +1,21 @@ +/* PowerPC-specific support for 64-bit ELF. + Copyright 2003 Free Software Foundation, Inc. + +This file is part of BFD, the Binary File Descriptor library. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +asection *ppc_elf_tls_setup (bfd *, struct bfd_link_info *); +bfd_boolean ppc_elf_tls_optimize (bfd *, struct bfd_link_info *); diff --git a/bfd/elf32-sh64.h b/bfd/elf32-sh64.h new file mode 100644 index 0000000..5916aec --- /dev/null +++ b/bfd/elf32-sh64.h @@ -0,0 +1,88 @@ +/* SH ELF support for BFD. + Copyright 2003 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef ELF32_SH64_H +#define ELF32_SH64_H + +#define SH64_CRANGES_SECTION_NAME ".cranges" +enum sh64_elf_cr_type { + CRT_NONE = 0, + CRT_DATA = 1, + CRT_SH5_ISA16 = 2, + CRT_SH5_ISA32 = 3 +}; + +/* The official definition is this: + + typedef struct { + Elf32_Addr cr_addr; + Elf32_Word cr_size; + Elf32_Half cr_type; + } Elf32_CRange; + + but we have no use for that exact type. Instead we use this struct for + the internal representation. */ +typedef struct { + bfd_vma cr_addr; + bfd_size_type cr_size; + enum sh64_elf_cr_type cr_type; +} sh64_elf_crange; + +#define SH64_CRANGE_SIZE (4 + 4 + 2) +#define SH64_CRANGE_CR_ADDR_OFFSET 0 +#define SH64_CRANGE_CR_SIZE_OFFSET 4 +#define SH64_CRANGE_CR_TYPE_OFFSET (4 + 4) + +/* Get the contents type of an arbitrary address, or return CRT_NONE. */ +extern enum sh64_elf_cr_type sh64_get_contents_type + (asection *, bfd_vma, sh64_elf_crange *); + +/* Simpler interface. + FIXME: This seems redundant now that we export the interface above. */ +extern bfd_boolean sh64_address_is_shmedia + (asection *, bfd_vma); + +extern int _bfd_sh64_crange_qsort_cmpb + (const void *, const void *); +extern int _bfd_sh64_crange_qsort_cmpl + (const void *, const void *); +extern int _bfd_sh64_crange_bsearch_cmpb + (const void *, const void *); +extern int _bfd_sh64_crange_bsearch_cmpl + (const void *, const void *); + +struct sh64_section_data +{ + flagword contents_flags; + + /* Only used in the cranges section, but we don't have an official + backend-specific bfd field. */ + bfd_size_type cranges_growth; +}; + +struct _sh64_elf_section_data +{ + struct bfd_elf_section_data elf; + struct sh64_section_data *sh64_info; +}; + +#define sh64_elf_section_data(sec) \ + ((struct _sh64_elf_section_data *) elf_section_data (sec)) + +#endif /* ELF32_SH64_H */ diff --git a/bfd/elf32-xtensa.c b/bfd/elf32-xtensa.c new file mode 100644 index 0000000..44450c5 --- /dev/null +++ b/bfd/elf32-xtensa.c @@ -0,0 +1,5856 @@ +/* Xtensa-specific support for 32-bit ELF. + Copyright 2003 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA + 02111-1307, USA. */ + +#include "bfd.h" +#include "sysdep.h" + +#ifdef ANSI_PROTOTYPES +#include +#else +#include +#endif +#include + +#include "bfdlink.h" +#include "libbfd.h" +#include "elf-bfd.h" +#include "elf/xtensa.h" +#include "xtensa-isa.h" +#include "xtensa-config.h" + +/* Main interface functions. */ +static void elf_xtensa_info_to_howto_rela + PARAMS ((bfd *, arelent *, Elf_Internal_Rela *)); +static reloc_howto_type *elf_xtensa_reloc_type_lookup + PARAMS ((bfd *abfd, bfd_reloc_code_real_type code)); +extern int xtensa_read_table_entries + PARAMS ((bfd *, asection *, property_table_entry **, const char *)); +static bfd_boolean elf_xtensa_check_relocs + PARAMS ((bfd *, struct bfd_link_info *, asection *, + const Elf_Internal_Rela *)); +static void elf_xtensa_hide_symbol + PARAMS ((struct bfd_link_info *, struct elf_link_hash_entry *, bfd_boolean)); +static asection *elf_xtensa_gc_mark_hook + PARAMS ((asection *, struct bfd_link_info *, Elf_Internal_Rela *, + struct elf_link_hash_entry *, Elf_Internal_Sym *)); +static bfd_boolean elf_xtensa_gc_sweep_hook + PARAMS ((bfd *, struct bfd_link_info *, asection *, + const Elf_Internal_Rela *)); +static bfd_boolean elf_xtensa_create_dynamic_sections + PARAMS ((bfd *, struct bfd_link_info *)); +static bfd_boolean elf_xtensa_adjust_dynamic_symbol + PARAMS ((struct bfd_link_info *, struct elf_link_hash_entry *)); +static bfd_boolean elf_xtensa_size_dynamic_sections + PARAMS ((bfd *, struct bfd_link_info *)); +static bfd_boolean elf_xtensa_modify_segment_map + PARAMS ((bfd *, struct bfd_link_info *)); +static bfd_boolean elf_xtensa_relocate_section + PARAMS ((bfd *, struct bfd_link_info *, bfd *, asection *, bfd_byte *, + Elf_Internal_Rela *, Elf_Internal_Sym *, asection **)); +static bfd_boolean elf_xtensa_relax_section + PARAMS ((bfd *, asection *, struct bfd_link_info *, bfd_boolean *again)); +static bfd_boolean elf_xtensa_finish_dynamic_symbol + PARAMS ((bfd *, struct bfd_link_info *, struct elf_link_hash_entry *, + Elf_Internal_Sym *)); +static bfd_boolean elf_xtensa_finish_dynamic_sections + PARAMS ((bfd *, struct bfd_link_info *)); +static bfd_boolean elf_xtensa_merge_private_bfd_data + PARAMS ((bfd *, bfd *)); +static bfd_boolean elf_xtensa_set_private_flags + PARAMS ((bfd *, flagword)); +extern flagword elf_xtensa_get_private_bfd_flags + PARAMS ((bfd *)); +static bfd_boolean elf_xtensa_print_private_bfd_data + PARAMS ((bfd *, PTR)); +static bfd_boolean elf_xtensa_object_p + PARAMS ((bfd *)); +static void elf_xtensa_final_write_processing + PARAMS ((bfd *, bfd_boolean)); +static enum elf_reloc_type_class elf_xtensa_reloc_type_class + PARAMS ((const Elf_Internal_Rela *)); +static bfd_boolean elf_xtensa_discard_info + PARAMS ((bfd *, struct elf_reloc_cookie *, struct bfd_link_info *)); +static bfd_boolean elf_xtensa_ignore_discarded_relocs + PARAMS ((asection *)); +static bfd_boolean elf_xtensa_grok_prstatus + PARAMS ((bfd *, Elf_Internal_Note *)); +static bfd_boolean elf_xtensa_grok_psinfo + PARAMS ((bfd *, Elf_Internal_Note *)); +static bfd_boolean elf_xtensa_new_section_hook + PARAMS ((bfd *, asection *)); + + +/* Local helper functions. */ + +static bfd_boolean xtensa_elf_dynamic_symbol_p + PARAMS ((struct elf_link_hash_entry *, struct bfd_link_info *)); +static int property_table_compare + PARAMS ((const PTR, const PTR)); +static bfd_boolean elf_xtensa_in_literal_pool + PARAMS ((property_table_entry *, int, bfd_vma)); +static void elf_xtensa_make_sym_local + PARAMS ((struct bfd_link_info *, struct elf_link_hash_entry *)); +static bfd_boolean add_extra_plt_sections + PARAMS ((bfd *, int)); +static bfd_boolean elf_xtensa_fix_refcounts + PARAMS ((struct elf_link_hash_entry *, PTR)); +static bfd_boolean elf_xtensa_allocate_plt_size + PARAMS ((struct elf_link_hash_entry *, PTR)); +static bfd_boolean elf_xtensa_allocate_got_size + PARAMS ((struct elf_link_hash_entry *, PTR)); +static void elf_xtensa_allocate_local_got_size + PARAMS ((struct bfd_link_info *, asection *)); +static bfd_reloc_status_type elf_xtensa_do_reloc + PARAMS ((reloc_howto_type *, bfd *, asection *, bfd_vma, bfd_byte *, + bfd_vma, bfd_boolean, char **)); +static char * vsprint_msg + VPARAMS ((const char *, const char *, int, ...)); +static char *build_encoding_error_message + PARAMS ((xtensa_opcode, xtensa_encode_result)); +static bfd_reloc_status_type bfd_elf_xtensa_reloc + PARAMS ((bfd *, arelent *, asymbol *, PTR, asection *, bfd *, char **)); +static void do_fix_for_relocatable_link + PARAMS ((Elf_Internal_Rela *, bfd *, asection *)); +static void do_fix_for_final_link + PARAMS ((Elf_Internal_Rela *, asection *, bfd_vma *)); +static bfd_vma elf_xtensa_create_plt_entry + PARAMS ((bfd *, bfd *, unsigned)); +static int elf_xtensa_combine_prop_entries + PARAMS ((bfd *, asection *, asection *)); +static bfd_boolean elf_xtensa_discard_info_for_section + PARAMS ((bfd *, struct elf_reloc_cookie *, struct bfd_link_info *, + asection *)); + +/* Local functions to handle Xtensa configurability. */ + +static void init_call_opcodes + PARAMS ((void)); +static bfd_boolean is_indirect_call_opcode + PARAMS ((xtensa_opcode)); +static bfd_boolean is_direct_call_opcode + PARAMS ((xtensa_opcode)); +static bfd_boolean is_windowed_call_opcode + PARAMS ((xtensa_opcode)); +static xtensa_opcode get_l32r_opcode + PARAMS ((void)); +static bfd_vma l32r_offset + PARAMS ((bfd_vma, bfd_vma)); +static int get_relocation_opnd + PARAMS ((Elf_Internal_Rela *)); +static xtensa_opcode get_relocation_opcode + PARAMS ((asection *, bfd_byte *, Elf_Internal_Rela *)); +static bfd_boolean is_l32r_relocation + PARAMS ((asection *, bfd_byte *, Elf_Internal_Rela *)); + +/* Functions for link-time code simplifications. */ + +static bfd_reloc_status_type elf_xtensa_do_asm_simplify + PARAMS ((bfd_byte *, bfd_vma, bfd_vma)); +static bfd_reloc_status_type contract_asm_expansion + PARAMS ((bfd_byte *, bfd_vma, Elf_Internal_Rela *)); +static xtensa_opcode swap_callx_for_call_opcode + PARAMS ((xtensa_opcode)); +static xtensa_opcode get_expanded_call_opcode + PARAMS ((bfd_byte *, int)); + +/* Access to internal relocations, section contents and symbols. */ + +static Elf_Internal_Rela *retrieve_internal_relocs + PARAMS ((bfd *, asection *, bfd_boolean)); +static void pin_internal_relocs + PARAMS ((asection *, Elf_Internal_Rela *)); +static void release_internal_relocs + PARAMS ((asection *, Elf_Internal_Rela *)); +static bfd_byte *retrieve_contents + PARAMS ((bfd *, asection *, bfd_boolean)); +static void pin_contents + PARAMS ((asection *, bfd_byte *)); +static void release_contents + PARAMS ((asection *, bfd_byte *)); +static Elf_Internal_Sym *retrieve_local_syms + PARAMS ((bfd *)); + +/* Miscellaneous utility functions. */ + +static asection *elf_xtensa_get_plt_section + PARAMS ((bfd *, int)); +static asection *elf_xtensa_get_gotplt_section + PARAMS ((bfd *, int)); +static asection *get_elf_r_symndx_section + PARAMS ((bfd *, unsigned long)); +static struct elf_link_hash_entry *get_elf_r_symndx_hash_entry + PARAMS ((bfd *, unsigned long)); +static bfd_vma get_elf_r_symndx_offset + PARAMS ((bfd *, unsigned long)); +static bfd_boolean pcrel_reloc_fits + PARAMS ((xtensa_operand, bfd_vma, bfd_vma)); +static bfd_boolean xtensa_is_property_section + PARAMS ((asection *)); +static bfd_boolean xtensa_is_littable_section + PARAMS ((asection *)); +static bfd_boolean is_literal_section + PARAMS ((asection *)); +static int internal_reloc_compare + PARAMS ((const PTR, const PTR)); +extern char *xtensa_get_property_section_name + PARAMS ((asection *, const char *)); + +/* Other functions called directly by the linker. */ + +typedef void (*deps_callback_t) + PARAMS ((asection *, bfd_vma, asection *, bfd_vma, PTR)); +extern bfd_boolean xtensa_callback_required_dependence + PARAMS ((bfd *, asection *, struct bfd_link_info *, + deps_callback_t, PTR)); + + +typedef struct xtensa_relax_info_struct xtensa_relax_info; + + +/* Total count of PLT relocations seen during check_relocs. + The actual PLT code must be split into multiple sections and all + the sections have to be created before size_dynamic_sections, + where we figure out the exact number of PLT entries that will be + needed. It is OK if this count is an overestimate, e.g., some + relocations may be removed by GC. */ + +static int plt_reloc_count = 0; + + +/* When this is true, relocations may have been modified to refer to + symbols from other input files. The per-section list of "fix" + records needs to be checked when resolving relocations. */ + +static bfd_boolean relaxing_section = FALSE; + + +static reloc_howto_type elf_howto_table[] = +{ + HOWTO (R_XTENSA_NONE, 0, 0, 0, FALSE, 0, complain_overflow_dont, + bfd_elf_xtensa_reloc, "R_XTENSA_NONE", + FALSE, 0x00000000, 0x00000000, FALSE), + HOWTO (R_XTENSA_32, 0, 2, 32, FALSE, 0, complain_overflow_bitfield, + bfd_elf_xtensa_reloc, "R_XTENSA_32", + TRUE, 0xffffffff, 0xffffffff, FALSE), + /* Replace a 32-bit value with a value from the runtime linker (only + used by linker-generated stub functions). The r_addend value is + special: 1 means to substitute a pointer to the runtime linker's + dynamic resolver function; 2 means to substitute the link map for + the shared object. */ + HOWTO (R_XTENSA_RTLD, 0, 2, 32, FALSE, 0, complain_overflow_dont, + NULL, "R_XTENSA_RTLD", + FALSE, 0x00000000, 0x00000000, FALSE), + HOWTO (R_XTENSA_GLOB_DAT, 0, 2, 32, FALSE, 0, complain_overflow_bitfield, + bfd_elf_generic_reloc, "R_XTENSA_GLOB_DAT", + FALSE, 0xffffffff, 0xffffffff, FALSE), + HOWTO (R_XTENSA_JMP_SLOT, 0, 2, 32, FALSE, 0, complain_overflow_bitfield, + bfd_elf_generic_reloc, "R_XTENSA_JMP_SLOT", + FALSE, 0xffffffff, 0xffffffff, FALSE), + HOWTO (R_XTENSA_RELATIVE, 0, 2, 32, FALSE, 0, complain_overflow_bitfield, + bfd_elf_generic_reloc, "R_XTENSA_RELATIVE", + FALSE, 0xffffffff, 0xffffffff, FALSE), + HOWTO (R_XTENSA_PLT, 0, 2, 32, FALSE, 0, complain_overflow_bitfield, + bfd_elf_xtensa_reloc, "R_XTENSA_PLT", + FALSE, 0xffffffff, 0xffffffff, FALSE), + EMPTY_HOWTO (7), + HOWTO (R_XTENSA_OP0, 0, 0, 0, TRUE, 0, complain_overflow_dont, + bfd_elf_xtensa_reloc, "R_XTENSA_OP0", + FALSE, 0x00000000, 0x00000000, TRUE), + HOWTO (R_XTENSA_OP1, 0, 0, 0, TRUE, 0, complain_overflow_dont, + bfd_elf_xtensa_reloc, "R_XTENSA_OP1", + FALSE, 0x00000000, 0x00000000, TRUE), + HOWTO (R_XTENSA_OP2, 0, 0, 0, TRUE, 0, complain_overflow_dont, + bfd_elf_xtensa_reloc, "R_XTENSA_OP2", + FALSE, 0x00000000, 0x00000000, TRUE), + /* Assembly auto-expansion. */ + HOWTO (R_XTENSA_ASM_EXPAND, 0, 0, 0, TRUE, 0, complain_overflow_dont, + bfd_elf_xtensa_reloc, "R_XTENSA_ASM_EXPAND", + FALSE, 0x00000000, 0x00000000, FALSE), + /* Relax assembly auto-expansion. */ + HOWTO (R_XTENSA_ASM_SIMPLIFY, 0, 0, 0, TRUE, 0, complain_overflow_dont, + bfd_elf_xtensa_reloc, "R_XTENSA_ASM_SIMPLIFY", + FALSE, 0x00000000, 0x00000000, TRUE), + EMPTY_HOWTO (13), + EMPTY_HOWTO (14), + /* GNU extension to record C++ vtable hierarchy. */ + HOWTO (R_XTENSA_GNU_VTINHERIT, 0, 2, 0, FALSE, 0, complain_overflow_dont, + NULL, "R_XTENSA_GNU_VTINHERIT", + FALSE, 0x00000000, 0x00000000, FALSE), + /* GNU extension to record C++ vtable member usage. */ + HOWTO (R_XTENSA_GNU_VTENTRY, 0, 2, 0, FALSE, 0, complain_overflow_dont, + _bfd_elf_rel_vtable_reloc_fn, "R_XTENSA_GNU_VTENTRY", + FALSE, 0x00000000, 0x00000000, FALSE) +}; + +#ifdef DEBUG_GEN_RELOC +#define TRACE(str) \ + fprintf (stderr, "Xtensa bfd reloc lookup %d (%s)\n", code, str) +#else +#define TRACE(str) +#endif + +static reloc_howto_type * +elf_xtensa_reloc_type_lookup (abfd, code) + bfd *abfd ATTRIBUTE_UNUSED; + bfd_reloc_code_real_type code; +{ + switch (code) + { + case BFD_RELOC_NONE: + TRACE ("BFD_RELOC_NONE"); + return &elf_howto_table[(unsigned) R_XTENSA_NONE ]; + + case BFD_RELOC_32: + TRACE ("BFD_RELOC_32"); + return &elf_howto_table[(unsigned) R_XTENSA_32 ]; + + case BFD_RELOC_XTENSA_RTLD: + TRACE ("BFD_RELOC_XTENSA_RTLD"); + return &elf_howto_table[(unsigned) R_XTENSA_RTLD ]; + + case BFD_RELOC_XTENSA_GLOB_DAT: + TRACE ("BFD_RELOC_XTENSA_GLOB_DAT"); + return &elf_howto_table[(unsigned) R_XTENSA_GLOB_DAT ]; + + case BFD_RELOC_XTENSA_JMP_SLOT: + TRACE ("BFD_RELOC_XTENSA_JMP_SLOT"); + return &elf_howto_table[(unsigned) R_XTENSA_JMP_SLOT ]; + + case BFD_RELOC_XTENSA_RELATIVE: + TRACE ("BFD_RELOC_XTENSA_RELATIVE"); + return &elf_howto_table[(unsigned) R_XTENSA_RELATIVE ]; + + case BFD_RELOC_XTENSA_PLT: + TRACE ("BFD_RELOC_XTENSA_PLT"); + return &elf_howto_table[(unsigned) R_XTENSA_PLT ]; + + case BFD_RELOC_XTENSA_OP0: + TRACE ("BFD_RELOC_XTENSA_OP0"); + return &elf_howto_table[(unsigned) R_XTENSA_OP0 ]; + + case BFD_RELOC_XTENSA_OP1: + TRACE ("BFD_RELOC_XTENSA_OP1"); + return &elf_howto_table[(unsigned) R_XTENSA_OP1 ]; + + case BFD_RELOC_XTENSA_OP2: + TRACE ("BFD_RELOC_XTENSA_OP2"); + return &elf_howto_table[(unsigned) R_XTENSA_OP2 ]; + + case BFD_RELOC_XTENSA_ASM_EXPAND: + TRACE ("BFD_RELOC_XTENSA_ASM_EXPAND"); + return &elf_howto_table[(unsigned) R_XTENSA_ASM_EXPAND ]; + + case BFD_RELOC_XTENSA_ASM_SIMPLIFY: + TRACE ("BFD_RELOC_XTENSA_ASM_SIMPLIFY"); + return &elf_howto_table[(unsigned) R_XTENSA_ASM_SIMPLIFY ]; + + case BFD_RELOC_VTABLE_INHERIT: + TRACE ("BFD_RELOC_VTABLE_INHERIT"); + return &elf_howto_table[(unsigned) R_XTENSA_GNU_VTINHERIT ]; + + case BFD_RELOC_VTABLE_ENTRY: + TRACE ("BFD_RELOC_VTABLE_ENTRY"); + return &elf_howto_table[(unsigned) R_XTENSA_GNU_VTENTRY ]; + + default: + break; + } + + TRACE ("Unknown"); + return NULL; +} + + +/* Given an ELF "rela" relocation, find the corresponding howto and record + it in the BFD internal arelent representation of the relocation. */ + +static void +elf_xtensa_info_to_howto_rela (abfd, cache_ptr, dst) + bfd *abfd ATTRIBUTE_UNUSED; + arelent *cache_ptr; + Elf_Internal_Rela *dst; +{ + unsigned int r_type = ELF32_R_TYPE (dst->r_info); + + BFD_ASSERT (r_type < (unsigned int) R_XTENSA_max); + cache_ptr->howto = &elf_howto_table[r_type]; +} + + +/* Functions for the Xtensa ELF linker. */ + +/* The name of the dynamic interpreter. This is put in the .interp + section. */ + +#define ELF_DYNAMIC_INTERPRETER "/lib/ld.so" + +/* The size in bytes of an entry in the procedure linkage table. + (This does _not_ include the space for the literals associated with + the PLT entry.) */ + +#define PLT_ENTRY_SIZE 16 + +/* For _really_ large PLTs, we may need to alternate between literals + and code to keep the literals within the 256K range of the L32R + instructions in the code. It's unlikely that anyone would ever need + such a big PLT, but an arbitrary limit on the PLT size would be bad. + Thus, we split the PLT into chunks. Since there's very little + overhead (2 extra literals) for each chunk, the chunk size is kept + small so that the code for handling multiple chunks get used and + tested regularly. With 254 entries, there are 1K of literals for + each chunk, and that seems like a nice round number. */ + +#define PLT_ENTRIES_PER_CHUNK 254 + +/* PLT entries are actually used as stub functions for lazy symbol + resolution. Once the symbol is resolved, the stub function is never + invoked. Note: the 32-byte frame size used here cannot be changed + without a corresponding change in the runtime linker. */ + +static const bfd_byte elf_xtensa_be_plt_entry[PLT_ENTRY_SIZE] = +{ + 0x6c, 0x10, 0x04, /* entry sp, 32 */ + 0x18, 0x00, 0x00, /* l32r a8, [got entry for rtld's resolver] */ + 0x1a, 0x00, 0x00, /* l32r a10, [got entry for rtld's link map] */ + 0x1b, 0x00, 0x00, /* l32r a11, [literal for reloc index] */ + 0x0a, 0x80, 0x00, /* jx a8 */ + 0 /* unused */ +}; + +static const bfd_byte elf_xtensa_le_plt_entry[PLT_ENTRY_SIZE] = +{ + 0x36, 0x41, 0x00, /* entry sp, 32 */ + 0x81, 0x00, 0x00, /* l32r a8, [got entry for rtld's resolver] */ + 0xa1, 0x00, 0x00, /* l32r a10, [got entry for rtld's link map] */ + 0xb1, 0x00, 0x00, /* l32r a11, [literal for reloc index] */ + 0xa0, 0x08, 0x00, /* jx a8 */ + 0 /* unused */ +}; + + +static inline bfd_boolean +xtensa_elf_dynamic_symbol_p (h, info) + struct elf_link_hash_entry *h; + struct bfd_link_info *info; +{ + /* Check if we should do dynamic things to this symbol. The + "ignore_protected" argument need not be set, because Xtensa code + does not require special handling of STV_PROTECTED to make function + pointer comparisons work properly. The PLT addresses are never + used for function pointers. */ + + return _bfd_elf_dynamic_symbol_p (h, info, 0); +} + + +static int +property_table_compare (ap, bp) + const PTR ap; + const PTR bp; +{ + const property_table_entry *a = (const property_table_entry *) ap; + const property_table_entry *b = (const property_table_entry *) bp; + + /* Check if one entry overlaps with the other; this shouldn't happen + except when searching for a match. */ + if ((b->address >= a->address && b->address < (a->address + a->size)) + || (a->address >= b->address && a->address < (b->address + b->size))) + return 0; + + return (a->address - b->address); +} + + +/* Get the literal table or instruction table entries for the given + section. Sets TABLE_P and returns the number of entries. On error, + returns a negative value. */ + +int +xtensa_read_table_entries (abfd, section, table_p, sec_name) + bfd *abfd; + asection *section; + property_table_entry **table_p; + const char *sec_name; +{ + asection *table_section; + char *table_section_name; + bfd_size_type table_size = 0; + bfd_byte *table_data; + property_table_entry *blocks; + int block_count; + bfd_size_type num_records; + Elf_Internal_Rela *internal_relocs; + + table_section_name = + xtensa_get_property_section_name (section, sec_name); + table_section = bfd_get_section_by_name (abfd, table_section_name); + free (table_section_name); + if (table_section != NULL) + table_size = bfd_get_section_size_before_reloc (table_section); + + if (table_size == 0) + { + *table_p = NULL; + return 0; + } + + num_records = table_size / 8; + table_data = retrieve_contents (abfd, table_section, TRUE); + blocks = (property_table_entry *) + bfd_malloc (num_records * sizeof (property_table_entry)); + block_count = 0; + + /* If the file has not yet been relocated, process the relocations + and sort out the table entries that apply to the specified section. */ + internal_relocs = retrieve_internal_relocs (abfd, table_section, TRUE); + if (internal_relocs) + { + unsigned i; + + for (i = 0; i < table_section->reloc_count; i++) + { + Elf_Internal_Rela *rel = &internal_relocs[i]; + unsigned long r_symndx; + + if (ELF32_R_TYPE (rel->r_info) == R_XTENSA_NONE) + continue; + + BFD_ASSERT (ELF32_R_TYPE (rel->r_info) == R_XTENSA_32); + r_symndx = ELF32_R_SYM (rel->r_info); + + if (get_elf_r_symndx_section (abfd, r_symndx) == section) + { + bfd_vma sym_off = get_elf_r_symndx_offset (abfd, r_symndx); + blocks[block_count].address = + (section->vma + sym_off + rel->r_addend + + bfd_get_32 (abfd, table_data + rel->r_offset)); + blocks[block_count].size = + bfd_get_32 (abfd, table_data + rel->r_offset + 4); + block_count++; + } + } + } + else + { + /* No relocations. Presumably the file has been relocated + and the addresses are already in the table. */ + bfd_vma off; + + for (off = 0; off < table_size; off += 8) + { + bfd_vma address = bfd_get_32 (abfd, table_data + off); + + if (address >= section->vma + && address < ( section->vma + section->_raw_size)) + { + blocks[block_count].address = address; + blocks[block_count].size = + bfd_get_32 (abfd, table_data + off + 4); + block_count++; + } + } + } + + release_contents (table_section, table_data); + release_internal_relocs (table_section, internal_relocs); + + if (block_count > 0) + { + /* Now sort them into address order for easy reference. */ + qsort (blocks, block_count, sizeof (property_table_entry), + property_table_compare); + } + + *table_p = blocks; + return block_count; +} + + +static bfd_boolean +elf_xtensa_in_literal_pool (lit_table, lit_table_size, addr) + property_table_entry *lit_table; + int lit_table_size; + bfd_vma addr; +{ + property_table_entry entry; + + if (lit_table_size == 0) + return FALSE; + + entry.address = addr; + entry.size = 1; + + if (bsearch (&entry, lit_table, lit_table_size, + sizeof (property_table_entry), property_table_compare)) + return TRUE; + + return FALSE; +} + + +/* Look through the relocs for a section during the first phase, and + calculate needed space in the dynamic reloc sections. */ + +static bfd_boolean +elf_xtensa_check_relocs (abfd, info, sec, relocs) + bfd *abfd; + struct bfd_link_info *info; + asection *sec; + const Elf_Internal_Rela *relocs; +{ + Elf_Internal_Shdr *symtab_hdr; + struct elf_link_hash_entry **sym_hashes; + const Elf_Internal_Rela *rel; + const Elf_Internal_Rela *rel_end; + property_table_entry *lit_table; + int ltblsize; + + if (info->relocatable) + return TRUE; + + symtab_hdr = &elf_tdata (abfd)->symtab_hdr; + sym_hashes = elf_sym_hashes (abfd); + + ltblsize = xtensa_read_table_entries (abfd, sec, &lit_table, + XTENSA_LIT_SEC_NAME); + if (ltblsize < 0) + return FALSE; + + rel_end = relocs + sec->reloc_count; + for (rel = relocs; rel < rel_end; rel++) + { + unsigned int r_type; + unsigned long r_symndx; + struct elf_link_hash_entry *h; + + r_symndx = ELF32_R_SYM (rel->r_info); + r_type = ELF32_R_TYPE (rel->r_info); + + if (r_symndx >= NUM_SHDR_ENTRIES (symtab_hdr)) + { + (*_bfd_error_handler) (_("%s: bad symbol index: %d"), + bfd_archive_filename (abfd), + r_symndx); + return FALSE; + } + + if (r_symndx < symtab_hdr->sh_info) + h = NULL; + else + { + h = sym_hashes[r_symndx - symtab_hdr->sh_info]; + while (h->root.type == bfd_link_hash_indirect + || h->root.type == bfd_link_hash_warning) + h = (struct elf_link_hash_entry *) h->root.u.i.link; + } + + switch (r_type) + { + case R_XTENSA_32: + if (h == NULL) + goto local_literal; + + if ((sec->flags & SEC_ALLOC) != 0) + { + if ((sec->flags & SEC_READONLY) != 0 + && !elf_xtensa_in_literal_pool (lit_table, ltblsize, + sec->vma + rel->r_offset)) + h->elf_link_hash_flags |= ELF_LINK_NON_GOT_REF; + + if (h->got.refcount <= 0) + h->got.refcount = 1; + else + h->got.refcount += 1; + } + break; + + case R_XTENSA_PLT: + /* If this relocation is against a local symbol, then it's + exactly the same as a normal local GOT entry. */ + if (h == NULL) + goto local_literal; + + if ((sec->flags & SEC_ALLOC) != 0) + { + if ((sec->flags & SEC_READONLY) != 0 + && !elf_xtensa_in_literal_pool (lit_table, ltblsize, + sec->vma + rel->r_offset)) + h->elf_link_hash_flags |= ELF_LINK_NON_GOT_REF; + + if (h->plt.refcount <= 0) + { + h->elf_link_hash_flags |= ELF_LINK_HASH_NEEDS_PLT; + h->plt.refcount = 1; + } + else + h->plt.refcount += 1; + + /* Keep track of the total PLT relocation count even if we + don't yet know whether the dynamic sections will be + created. */ + plt_reloc_count += 1; + + if (elf_hash_table (info)->dynamic_sections_created) + { + if (!add_extra_plt_sections (elf_hash_table (info)->dynobj, + plt_reloc_count)) + return FALSE; + } + } + break; + + local_literal: + if ((sec->flags & SEC_ALLOC) != 0) + { + bfd_signed_vma *local_got_refcounts; + + /* This is a global offset table entry for a local symbol. */ + local_got_refcounts = elf_local_got_refcounts (abfd); + if (local_got_refcounts == NULL) + { + bfd_size_type size; + + size = symtab_hdr->sh_info; + size *= sizeof (bfd_signed_vma); + local_got_refcounts = ((bfd_signed_vma *) + bfd_zalloc (abfd, size)); + if (local_got_refcounts == NULL) + return FALSE; + elf_local_got_refcounts (abfd) = local_got_refcounts; + } + local_got_refcounts[r_symndx] += 1; + + /* If the relocation is not inside the GOT, the DF_TEXTREL + flag needs to be set. */ + if (info->shared + && (sec->flags & SEC_READONLY) != 0 + && !elf_xtensa_in_literal_pool (lit_table, ltblsize, + sec->vma + rel->r_offset)) + info->flags |= DF_TEXTREL; + } + break; + + case R_XTENSA_OP0: + case R_XTENSA_OP1: + case R_XTENSA_OP2: + case R_XTENSA_ASM_EXPAND: + case R_XTENSA_ASM_SIMPLIFY: + /* Nothing to do for these. */ + break; + + case R_XTENSA_GNU_VTINHERIT: + /* This relocation describes the C++ object vtable hierarchy. + Reconstruct it for later use during GC. */ + if (!_bfd_elf32_gc_record_vtinherit (abfd, sec, h, rel->r_offset)) + return FALSE; + break; + + case R_XTENSA_GNU_VTENTRY: + /* This relocation describes which C++ vtable entries are actually + used. Record for later use during GC. */ + if (!_bfd_elf32_gc_record_vtentry (abfd, sec, h, rel->r_addend)) + return FALSE; + break; + + default: + break; + } + } + + free (lit_table); + return TRUE; +} + + +static void +elf_xtensa_hide_symbol (info, h, force_local) + struct bfd_link_info *info; + struct elf_link_hash_entry *h; + bfd_boolean force_local; +{ + /* For a shared link, move the plt refcount to the got refcount to leave + space for RELATIVE relocs. */ + elf_xtensa_make_sym_local (info, h); + + _bfd_elf_link_hash_hide_symbol (info, h, force_local); +} + + +/* Return the section that should be marked against GC for a given + relocation. */ + +static asection * +elf_xtensa_gc_mark_hook (sec, info, rel, h, sym) + asection *sec; + struct bfd_link_info *info ATTRIBUTE_UNUSED; + Elf_Internal_Rela *rel; + struct elf_link_hash_entry *h; + Elf_Internal_Sym *sym; +{ + if (h != NULL) + { + switch (ELF32_R_TYPE (rel->r_info)) + { + case R_XTENSA_GNU_VTINHERIT: + case R_XTENSA_GNU_VTENTRY: + break; + + default: + switch (h->root.type) + { + case bfd_link_hash_defined: + case bfd_link_hash_defweak: + return h->root.u.def.section; + + case bfd_link_hash_common: + return h->root.u.c.p->section; + + default: + break; + } + } + } + else + return bfd_section_from_elf_index (sec->owner, sym->st_shndx); + + return NULL; +} + +/* Update the GOT & PLT entry reference counts + for the section being removed. */ + +static bfd_boolean +elf_xtensa_gc_sweep_hook (abfd, info, sec, relocs) + bfd *abfd; + struct bfd_link_info *info ATTRIBUTE_UNUSED; + asection *sec; + const Elf_Internal_Rela *relocs; +{ + Elf_Internal_Shdr *symtab_hdr; + struct elf_link_hash_entry **sym_hashes; + bfd_signed_vma *local_got_refcounts; + const Elf_Internal_Rela *rel, *relend; + + if ((sec->flags & SEC_ALLOC) == 0) + return TRUE; + + symtab_hdr = &elf_tdata (abfd)->symtab_hdr; + sym_hashes = elf_sym_hashes (abfd); + local_got_refcounts = elf_local_got_refcounts (abfd); + + relend = relocs + sec->reloc_count; + for (rel = relocs; rel < relend; rel++) + { + unsigned long r_symndx; + unsigned int r_type; + struct elf_link_hash_entry *h = NULL; + + r_symndx = ELF32_R_SYM (rel->r_info); + if (r_symndx >= symtab_hdr->sh_info) + h = sym_hashes[r_symndx - symtab_hdr->sh_info]; + + r_type = ELF32_R_TYPE (rel->r_info); + switch (r_type) + { + case R_XTENSA_32: + if (h == NULL) + goto local_literal; + if (h->got.refcount > 0) + h->got.refcount--; + break; + + case R_XTENSA_PLT: + if (h == NULL) + goto local_literal; + if (h->plt.refcount > 0) + h->plt.refcount--; + break; + + local_literal: + if (local_got_refcounts[r_symndx] > 0) + local_got_refcounts[r_symndx] -= 1; + break; + + default: + break; + } + } + + return TRUE; +} + + +/* Create all the dynamic sections. */ + +static bfd_boolean +elf_xtensa_create_dynamic_sections (dynobj, info) + bfd *dynobj; + struct bfd_link_info *info; +{ + flagword flags, noalloc_flags; + asection *s; + + /* First do all the standard stuff. */ + if (! _bfd_elf_create_dynamic_sections (dynobj, info)) + return FALSE; + + /* Create any extra PLT sections in case check_relocs has already + been called on all the non-dynamic input files. */ + if (!add_extra_plt_sections (dynobj, plt_reloc_count)) + return FALSE; + + noalloc_flags = (SEC_HAS_CONTENTS | SEC_IN_MEMORY + | SEC_LINKER_CREATED | SEC_READONLY); + flags = noalloc_flags | SEC_ALLOC | SEC_LOAD; + + /* Mark the ".got.plt" section READONLY. */ + s = bfd_get_section_by_name (dynobj, ".got.plt"); + if (s == NULL + || ! bfd_set_section_flags (dynobj, s, flags)) + return FALSE; + + /* Create ".rela.got". */ + s = bfd_make_section (dynobj, ".rela.got"); + if (s == NULL + || ! bfd_set_section_flags (dynobj, s, flags) + || ! bfd_set_section_alignment (dynobj, s, 2)) + return FALSE; + + /* Create ".got.loc" (literal tables for use by dynamic linker). */ + s = bfd_make_section (dynobj, ".got.loc"); + if (s == NULL + || ! bfd_set_section_flags (dynobj, s, flags) + || ! bfd_set_section_alignment (dynobj, s, 2)) + return FALSE; + + /* Create ".xt.lit.plt" (literal table for ".got.plt*"). */ + s = bfd_make_section (dynobj, ".xt.lit.plt"); + if (s == NULL + || ! bfd_set_section_flags (dynobj, s, noalloc_flags) + || ! bfd_set_section_alignment (dynobj, s, 2)) + return FALSE; + + return TRUE; +} + + +static bfd_boolean +add_extra_plt_sections (dynobj, count) + bfd *dynobj; + int count; +{ + int chunk; + + /* Iterate over all chunks except 0 which uses the standard ".plt" and + ".got.plt" sections. */ + for (chunk = count / PLT_ENTRIES_PER_CHUNK; chunk > 0; chunk--) + { + char *sname; + flagword flags; + asection *s; + + /* Stop when we find a section has already been created. */ + if (elf_xtensa_get_plt_section (dynobj, chunk)) + break; + + flags = (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS | SEC_IN_MEMORY + | SEC_LINKER_CREATED | SEC_READONLY); + + sname = (char *) bfd_malloc (10); + sprintf (sname, ".plt.%u", chunk); + s = bfd_make_section (dynobj, sname); + if (s == NULL + || ! bfd_set_section_flags (dynobj, s, flags | SEC_CODE) + || ! bfd_set_section_alignment (dynobj, s, 2)) + return FALSE; + + sname = (char *) bfd_malloc (14); + sprintf (sname, ".got.plt.%u", chunk); + s = bfd_make_section (dynobj, sname); + if (s == NULL + || ! bfd_set_section_flags (dynobj, s, flags) + || ! bfd_set_section_alignment (dynobj, s, 2)) + return FALSE; + } + + return TRUE; +} + + +/* Adjust a symbol defined by a dynamic object and referenced by a + regular object. The current definition is in some section of the + dynamic object, but we're not including those sections. We have to + change the definition to something the rest of the link can + understand. */ + +static bfd_boolean +elf_xtensa_adjust_dynamic_symbol (info, h) + struct bfd_link_info *info ATTRIBUTE_UNUSED; + struct elf_link_hash_entry *h; +{ + /* If this is a weak symbol, and there is a real definition, the + processor independent code will have arranged for us to see the + real definition first, and we can just use the same value. */ + if (h->weakdef != NULL) + { + BFD_ASSERT (h->weakdef->root.type == bfd_link_hash_defined + || h->weakdef->root.type == bfd_link_hash_defweak); + h->root.u.def.section = h->weakdef->root.u.def.section; + h->root.u.def.value = h->weakdef->root.u.def.value; + return TRUE; + } + + /* This is a reference to a symbol defined by a dynamic object. The + reference must go through the GOT, so there's no need for COPY relocs, + .dynbss, etc. */ + + return TRUE; +} + + +static void +elf_xtensa_make_sym_local (info, h) + struct bfd_link_info *info; + struct elf_link_hash_entry *h; +{ + if (info->shared) + { + if (h->plt.refcount > 0) + { + /* Will use RELATIVE relocs instead of JMP_SLOT relocs. */ + if (h->got.refcount < 0) + h->got.refcount = 0; + h->got.refcount += h->plt.refcount; + h->plt.refcount = 0; + } + } + else + { + /* Don't need any dynamic relocations at all. */ + h->elf_link_hash_flags &= ~ELF_LINK_NON_GOT_REF; + h->plt.refcount = 0; + h->got.refcount = 0; + } +} + + +static bfd_boolean +elf_xtensa_fix_refcounts (h, arg) + struct elf_link_hash_entry *h; + PTR arg; +{ + struct bfd_link_info *info = (struct bfd_link_info *) arg; + + if (h->root.type == bfd_link_hash_warning) + h = (struct elf_link_hash_entry *) h->root.u.i.link; + + if (! xtensa_elf_dynamic_symbol_p (h, info)) + elf_xtensa_make_sym_local (info, h); + + /* If the symbol has a relocation outside the GOT, set the + DF_TEXTREL flag. */ + if ((h->elf_link_hash_flags & ELF_LINK_NON_GOT_REF) != 0) + info->flags |= DF_TEXTREL; + + return TRUE; +} + + +static bfd_boolean +elf_xtensa_allocate_plt_size (h, arg) + struct elf_link_hash_entry *h; + PTR arg; +{ + asection *srelplt = (asection *) arg; + + if (h->root.type == bfd_link_hash_warning) + h = (struct elf_link_hash_entry *) h->root.u.i.link; + + if (h->plt.refcount > 0) + srelplt->_raw_size += (h->plt.refcount * sizeof (Elf32_External_Rela)); + + return TRUE; +} + + +static bfd_boolean +elf_xtensa_allocate_got_size (h, arg) + struct elf_link_hash_entry *h; + PTR arg; +{ + asection *srelgot = (asection *) arg; + + if (h->root.type == bfd_link_hash_warning) + h = (struct elf_link_hash_entry *) h->root.u.i.link; + + if (h->got.refcount > 0) + srelgot->_raw_size += (h->got.refcount * sizeof (Elf32_External_Rela)); + + return TRUE; +} + + +static void +elf_xtensa_allocate_local_got_size (info, srelgot) + struct bfd_link_info *info; + asection *srelgot; +{ + bfd *i; + + for (i = info->input_bfds; i; i = i->link_next) + { + bfd_signed_vma *local_got_refcounts; + bfd_size_type j, cnt; + Elf_Internal_Shdr *symtab_hdr; + + local_got_refcounts = elf_local_got_refcounts (i); + if (!local_got_refcounts) + continue; + + symtab_hdr = &elf_tdata (i)->symtab_hdr; + cnt = symtab_hdr->sh_info; + + for (j = 0; j < cnt; ++j) + { + if (local_got_refcounts[j] > 0) + srelgot->_raw_size += (local_got_refcounts[j] + * sizeof (Elf32_External_Rela)); + } + } +} + + +/* Set the sizes of the dynamic sections. */ + +static bfd_boolean +elf_xtensa_size_dynamic_sections (output_bfd, info) + bfd *output_bfd ATTRIBUTE_UNUSED; + struct bfd_link_info *info; +{ + bfd *dynobj, *abfd; + asection *s, *srelplt, *splt, *sgotplt, *srelgot, *spltlittbl, *sgotloc; + bfd_boolean relplt, relgot; + int plt_entries, plt_chunks, chunk; + + plt_entries = 0; + plt_chunks = 0; + srelgot = 0; + + dynobj = elf_hash_table (info)->dynobj; + if (dynobj == NULL) + abort (); + + if (elf_hash_table (info)->dynamic_sections_created) + { + /* Set the contents of the .interp section to the interpreter. */ + if (info->executable) + { + s = bfd_get_section_by_name (dynobj, ".interp"); + if (s == NULL) + abort (); + s->_raw_size = sizeof ELF_DYNAMIC_INTERPRETER; + s->contents = (unsigned char *) ELF_DYNAMIC_INTERPRETER; + } + + /* Allocate room for one word in ".got". */ + s = bfd_get_section_by_name (dynobj, ".got"); + if (s == NULL) + abort (); + s->_raw_size = 4; + + /* Adjust refcounts for symbols that we now know are not "dynamic". */ + elf_link_hash_traverse (elf_hash_table (info), + elf_xtensa_fix_refcounts, + (PTR) info); + + /* Allocate space in ".rela.got" for literals that reference + global symbols. */ + srelgot = bfd_get_section_by_name (dynobj, ".rela.got"); + if (srelgot == NULL) + abort (); + elf_link_hash_traverse (elf_hash_table (info), + elf_xtensa_allocate_got_size, + (PTR) srelgot); + + /* If we are generating a shared object, we also need space in + ".rela.got" for R_XTENSA_RELATIVE relocs for literals that + reference local symbols. */ + if (info->shared) + elf_xtensa_allocate_local_got_size (info, srelgot); + + /* Allocate space in ".rela.plt" for literals that have PLT entries. */ + srelplt = bfd_get_section_by_name (dynobj, ".rela.plt"); + if (srelplt == NULL) + abort (); + elf_link_hash_traverse (elf_hash_table (info), + elf_xtensa_allocate_plt_size, + (PTR) srelplt); + + /* Allocate space in ".plt" to match the size of ".rela.plt". For + each PLT entry, we need the PLT code plus a 4-byte literal. + For each chunk of ".plt", we also need two more 4-byte + literals, two corresponding entries in ".rela.got", and an + 8-byte entry in ".xt.lit.plt". */ + spltlittbl = bfd_get_section_by_name (dynobj, ".xt.lit.plt"); + if (spltlittbl == NULL) + abort (); + + plt_entries = srelplt->_raw_size / sizeof (Elf32_External_Rela); + plt_chunks = + (plt_entries + PLT_ENTRIES_PER_CHUNK - 1) / PLT_ENTRIES_PER_CHUNK; + + /* Iterate over all the PLT chunks, including any extra sections + created earlier because the initial count of PLT relocations + was an overestimate. */ + for (chunk = 0; + (splt = elf_xtensa_get_plt_section (dynobj, chunk)) != NULL; + chunk++) + { + int chunk_entries; + + sgotplt = elf_xtensa_get_gotplt_section (dynobj, chunk); + if (sgotplt == NULL) + abort (); + + if (chunk < plt_chunks - 1) + chunk_entries = PLT_ENTRIES_PER_CHUNK; + else if (chunk == plt_chunks - 1) + chunk_entries = plt_entries - (chunk * PLT_ENTRIES_PER_CHUNK); + else + chunk_entries = 0; + + if (chunk_entries != 0) + { + sgotplt->_raw_size = 4 * (chunk_entries + 2); + splt->_raw_size = PLT_ENTRY_SIZE * chunk_entries; + srelgot->_raw_size += 2 * sizeof (Elf32_External_Rela); + spltlittbl->_raw_size += 8; + } + else + { + sgotplt->_raw_size = 0; + splt->_raw_size = 0; + } + } + + /* Allocate space in ".got.loc" to match the total size of all the + literal tables. */ + sgotloc = bfd_get_section_by_name (dynobj, ".got.loc"); + if (sgotloc == NULL) + abort (); + sgotloc->_raw_size = spltlittbl->_raw_size; + for (abfd = info->input_bfds; abfd != NULL; abfd = abfd->link_next) + { + if (abfd->flags & DYNAMIC) + continue; + for (s = abfd->sections; s != NULL; s = s->next) + { + if (! elf_discarded_section (s) + && xtensa_is_littable_section (s) + && s != spltlittbl) + sgotloc->_raw_size += s->_raw_size; + } + } + } + + /* Allocate memory for dynamic sections. */ + relplt = FALSE; + relgot = FALSE; + for (s = dynobj->sections; s != NULL; s = s->next) + { + const char *name; + bfd_boolean strip; + + if ((s->flags & SEC_LINKER_CREATED) == 0) + continue; + + /* It's OK to base decisions on the section name, because none + of the dynobj section names depend upon the input files. */ + name = bfd_get_section_name (dynobj, s); + + strip = FALSE; + + if (strncmp (name, ".rela", 5) == 0) + { + if (strcmp (name, ".rela.plt") == 0) + relplt = TRUE; + else if (strcmp (name, ".rela.got") == 0) + relgot = TRUE; + + /* We use the reloc_count field as a counter if we need + to copy relocs into the output file. */ + s->reloc_count = 0; + } + else if (strncmp (name, ".plt.", 5) == 0 + || strncmp (name, ".got.plt.", 9) == 0) + { + if (s->_raw_size == 0) + { + /* If we don't need this section, strip it from the output + file. We must create the ".plt*" and ".got.plt*" + sections in create_dynamic_sections and/or check_relocs + based on a conservative estimate of the PLT relocation + count, because the sections must be created before the + linker maps input sections to output sections. The + linker does that before size_dynamic_sections, where we + compute the exact size of the PLT, so there may be more + of these sections than are actually needed. */ + strip = TRUE; + } + } + else if (strcmp (name, ".got") != 0 + && strcmp (name, ".plt") != 0 + && strcmp (name, ".got.plt") != 0 + && strcmp (name, ".xt.lit.plt") != 0 + && strcmp (name, ".got.loc") != 0) + { + /* It's not one of our sections, so don't allocate space. */ + continue; + } + + if (strip) + _bfd_strip_section_from_output (info, s); + else + { + /* Allocate memory for the section contents. */ + s->contents = (bfd_byte *) bfd_zalloc (dynobj, s->_raw_size); + if (s->contents == NULL && s->_raw_size != 0) + return FALSE; + } + } + + if (elf_hash_table (info)->dynamic_sections_created) + { + /* Add the special XTENSA_RTLD relocations now. The offsets won't be + known until finish_dynamic_sections, but we need to get the relocs + in place before they are sorted. */ + if (srelgot == NULL) + abort (); + for (chunk = 0; chunk < plt_chunks; chunk++) + { + Elf_Internal_Rela irela; + bfd_byte *loc; + + irela.r_offset = 0; + irela.r_info = ELF32_R_INFO (0, R_XTENSA_RTLD); + irela.r_addend = 0; + + loc = (srelgot->contents + + srelgot->reloc_count * sizeof (Elf32_External_Rela)); + bfd_elf32_swap_reloca_out (output_bfd, &irela, loc); + bfd_elf32_swap_reloca_out (output_bfd, &irela, + loc + sizeof (Elf32_External_Rela)); + srelgot->reloc_count += 2; + } + + /* Add some entries to the .dynamic section. We fill in the + values later, in elf_xtensa_finish_dynamic_sections, but we + must add the entries now so that we get the correct size for + the .dynamic section. The DT_DEBUG entry is filled in by the + dynamic linker and used by the debugger. */ +#define add_dynamic_entry(TAG, VAL) \ + bfd_elf32_add_dynamic_entry (info, (bfd_vma) (TAG), (bfd_vma) (VAL)) + + if (! info->shared) + { + if (!add_dynamic_entry (DT_DEBUG, 0)) + return FALSE; + } + + if (relplt) + { + if (!add_dynamic_entry (DT_PLTGOT, 0) + || !add_dynamic_entry (DT_PLTRELSZ, 0) + || !add_dynamic_entry (DT_PLTREL, DT_RELA) + || !add_dynamic_entry (DT_JMPREL, 0)) + return FALSE; + } + + if (relgot) + { + if (!add_dynamic_entry (DT_RELA, 0) + || !add_dynamic_entry (DT_RELASZ, 0) + || !add_dynamic_entry (DT_RELAENT, sizeof (Elf32_External_Rela))) + return FALSE; + } + + if ((info->flags & DF_TEXTREL) != 0) + { + if (!add_dynamic_entry (DT_TEXTREL, 0)) + return FALSE; + } + + if (!add_dynamic_entry (DT_XTENSA_GOT_LOC_OFF, 0) + || !add_dynamic_entry (DT_XTENSA_GOT_LOC_SZ, 0)) + return FALSE; + } +#undef add_dynamic_entry + + return TRUE; +} + + +/* Remove any PT_LOAD segments with no allocated sections. Prior to + binutils 2.13, this function used to remove the non-SEC_ALLOC + sections from PT_LOAD segments, but that task has now been moved + into elf.c. We still need this function to remove any empty + segments that result, but there's nothing Xtensa-specific about + this and it probably ought to be moved into elf.c as well. */ + +static bfd_boolean +elf_xtensa_modify_segment_map (abfd, info) + bfd *abfd; + struct bfd_link_info *info ATTRIBUTE_UNUSED; +{ + struct elf_segment_map **m_p; + + m_p = &elf_tdata (abfd)->segment_map; + while (*m_p != NULL) + { + if ((*m_p)->p_type == PT_LOAD && (*m_p)->count == 0) + *m_p = (*m_p)->next; + else + m_p = &(*m_p)->next; + } + return TRUE; +} + + +/* Perform the specified relocation. The instruction at (contents + address) + is modified to set one operand to represent the value in "relocation". The + operand position is determined by the relocation type recorded in the + howto. */ + +#define CALL_SEGMENT_BITS (30) +#define CALL_SEGMENT_SIZE (1<type) + { + case R_XTENSA_NONE: + return bfd_reloc_ok; + + case R_XTENSA_ASM_EXPAND: + if (!is_weak_undef) + { + /* Check for windowed CALL across a 1GB boundary. */ + xtensa_opcode opcode = + get_expanded_call_opcode (contents + address, + input_section->_raw_size - address); + if (is_windowed_call_opcode (opcode)) + { + self_address = (input_section->output_section->vma + + input_section->output_offset + + address); + if ((self_address >> CALL_SEGMENT_BITS) != + (relocation >> CALL_SEGMENT_BITS)) + { + *error_message = "windowed longcall crosses 1GB boundary; " + "return may fail"; + return bfd_reloc_dangerous; + } + } + } + return bfd_reloc_ok; + + case R_XTENSA_ASM_SIMPLIFY: + { + /* Convert the L32R/CALLX to CALL. */ + bfd_reloc_status_type retval = + elf_xtensa_do_asm_simplify (contents, address, + input_section->_raw_size); + if (retval != bfd_reloc_ok) + return retval; + + /* The CALL needs to be relocated. Continue below for that part. */ + address += 3; + howto = &elf_howto_table[(unsigned) R_XTENSA_OP0 ]; + } + break; + + case R_XTENSA_32: + case R_XTENSA_PLT: + { + bfd_vma x; + x = bfd_get_32 (abfd, contents + address); + x = x + relocation; + bfd_put_32 (abfd, x, contents + address); + } + return bfd_reloc_ok; + } + + /* Read the instruction into a buffer and decode the opcode. */ + ibuff = xtensa_insnbuf_alloc (isa); + xtensa_insnbuf_from_chars (isa, ibuff, contents + address); + opcode = xtensa_decode_insn (isa, ibuff); + + /* Determine which operand is being relocated. */ + if (opcode == XTENSA_UNDEFINED) + { + *error_message = "cannot decode instruction"; + return bfd_reloc_dangerous; + } + + if (howto->type < R_XTENSA_OP0 || howto->type > R_XTENSA_OP2) + { + *error_message = "unexpected relocation"; + return bfd_reloc_dangerous; + } + + opnd = howto->type - R_XTENSA_OP0; + + /* Calculate the PC address for this instruction. */ + if (!howto->pc_relative) + { + *error_message = "expected PC-relative relocation"; + return bfd_reloc_dangerous; + } + + self_address = (input_section->output_section->vma + + input_section->output_offset + + address); + + /* Apply the relocation. */ + operand = xtensa_get_operand (isa, opcode, opnd); + newval = xtensa_operand_do_reloc (operand, relocation, self_address); + encode_result = xtensa_operand_encode (operand, &newval); + xtensa_operand_set_field (operand, ibuff, newval); + + /* Write the modified instruction back out of the buffer. */ + xtensa_insnbuf_to_chars (isa, ibuff, contents + address); + free (ibuff); + + if (encode_result != xtensa_encode_result_ok) + { + char *message = build_encoding_error_message (opcode, encode_result); + *error_message = message; + return bfd_reloc_dangerous; + } + + /* Final check for call. */ + if (is_direct_call_opcode (opcode) + && is_windowed_call_opcode (opcode)) + { + if ((self_address >> CALL_SEGMENT_BITS) != + (relocation >> CALL_SEGMENT_BITS)) + { + *error_message = "windowed call crosses 1GB boundary; " + "return may fail"; + return bfd_reloc_dangerous; + } + } + + return bfd_reloc_ok; +} + + +static char * +vsprint_msg VPARAMS ((const char *origmsg, const char *fmt, int arglen, ...)) +{ + /* To reduce the size of the memory leak, + we only use a single message buffer. */ + static bfd_size_type alloc_size = 0; + static char *message = NULL; + bfd_size_type orig_len, len = 0; + bfd_boolean is_append; + + VA_OPEN (ap, arglen); + VA_FIXEDARG (ap, const char *, origmsg); + + is_append = (origmsg == message); + + orig_len = strlen (origmsg); + len = orig_len + strlen (fmt) + arglen + 20; + if (len > alloc_size) + { + message = (char *) bfd_realloc (message, len); + alloc_size = len; + } + if (!is_append) + memcpy (message, origmsg, orig_len); + vsprintf (message + orig_len, fmt, ap); + VA_CLOSE (ap); + return message; +} + + +static char * +build_encoding_error_message (opcode, encode_result) + xtensa_opcode opcode; + xtensa_encode_result encode_result; +{ + const char *opname = xtensa_opcode_name (xtensa_default_isa, opcode); + const char *msg = NULL; + + switch (encode_result) + { + case xtensa_encode_result_ok: + msg = "unexpected valid encoding"; + break; + case xtensa_encode_result_align: + msg = "misaligned encoding"; + break; + case xtensa_encode_result_not_in_table: + msg = "encoding not in lookup table"; + break; + case xtensa_encode_result_too_low: + msg = "encoding out of range: too low"; + break; + case xtensa_encode_result_too_high: + msg = "encoding out of range: too high"; + break; + case xtensa_encode_result_not_ok: + default: + msg = "could not encode"; + break; + } + + if (is_direct_call_opcode (opcode) + && (encode_result == xtensa_encode_result_too_low + || encode_result == xtensa_encode_result_too_high)) + + msg = "direct call out of range"; + + else if (opcode == get_l32r_opcode ()) + { + /* L32Rs have the strange interaction with encoding in that they + have an unsigned immediate field, so libisa returns "too high" + when the absolute value is out of range and never returns "too + low", but I leave the "too low" message in case anything + changes. */ + if (encode_result == xtensa_encode_result_too_low) + msg = "literal out of range"; + else if (encode_result == xtensa_encode_result_too_high) + msg = "literal placed after use"; + } + + return vsprint_msg (opname, ": %s", strlen (msg) + 2, msg); +} + + +/* This function is registered as the "special_function" in the + Xtensa howto for handling simplify operations. + bfd_perform_relocation / bfd_install_relocation use it to + perform (install) the specified relocation. Since this replaces the code + in bfd_perform_relocation, it is basically an Xtensa-specific, + stripped-down version of bfd_perform_relocation. */ + +static bfd_reloc_status_type +bfd_elf_xtensa_reloc (abfd, reloc_entry, symbol, data, input_section, + output_bfd, error_message) + bfd *abfd; + arelent *reloc_entry; + asymbol *symbol; + PTR data; + asection *input_section; + bfd *output_bfd; + char **error_message; +{ + bfd_vma relocation; + bfd_reloc_status_type flag; + bfd_size_type octets = reloc_entry->address * bfd_octets_per_byte (abfd); + bfd_vma output_base = 0; + reloc_howto_type *howto = reloc_entry->howto; + asection *reloc_target_output_section; + bfd_boolean is_weak_undef; + + /* ELF relocs are against symbols. If we are producing relocatable + output, and the reloc is against an external symbol, the resulting + reloc will also be against the same symbol. In such a case, we + don't want to change anything about the way the reloc is handled, + since it will all be done at final link time. This test is similar + to what bfd_elf_generic_reloc does except that it lets relocs with + howto->partial_inplace go through even if the addend is non-zero. + (The real problem is that partial_inplace is set for XTENSA_32 + relocs to begin with, but that's a long story and there's little we + can do about it now....) */ + + if (output_bfd != (bfd *) NULL + && (symbol->flags & BSF_SECTION_SYM) == 0) + { + reloc_entry->address += input_section->output_offset; + return bfd_reloc_ok; + } + + /* Is the address of the relocation really within the section? */ + if (reloc_entry->address > (input_section->_cooked_size + / bfd_octets_per_byte (abfd))) + return bfd_reloc_outofrange; + + /* Work out which section the relocation is targeted at and the + initial relocation command value. */ + + /* Get symbol value. (Common symbols are special.) */ + if (bfd_is_com_section (symbol->section)) + relocation = 0; + else + relocation = symbol->value; + + reloc_target_output_section = symbol->section->output_section; + + /* Convert input-section-relative symbol value to absolute. */ + if ((output_bfd && !howto->partial_inplace) + || reloc_target_output_section == NULL) + output_base = 0; + else + output_base = reloc_target_output_section->vma; + + relocation += output_base + symbol->section->output_offset; + + /* Add in supplied addend. */ + relocation += reloc_entry->addend; + + /* Here the variable relocation holds the final address of the + symbol we are relocating against, plus any addend. */ + if (output_bfd) + { + if (!howto->partial_inplace) + { + /* This is a partial relocation, and we want to apply the relocation + to the reloc entry rather than the raw data. Everything except + relocations against section symbols has already been handled + above. */ + + BFD_ASSERT (symbol->flags & BSF_SECTION_SYM); + reloc_entry->addend = relocation; + reloc_entry->address += input_section->output_offset; + return bfd_reloc_ok; + } + else + { + reloc_entry->address += input_section->output_offset; + reloc_entry->addend = 0; + } + } + + is_weak_undef = (bfd_is_und_section (symbol->section) + && (symbol->flags & BSF_WEAK) != 0); + flag = elf_xtensa_do_reloc (howto, abfd, input_section, relocation, + (bfd_byte *) data, (bfd_vma) octets, + is_weak_undef, error_message); + + if (flag == bfd_reloc_dangerous) + { + /* Add the symbol name to the error message. */ + if (! *error_message) + *error_message = ""; + *error_message = vsprint_msg (*error_message, ": (%s + 0x%lx)", + strlen (symbol->name) + 17, + symbol->name, reloc_entry->addend); + } + + return flag; +} + + +/* Set up an entry in the procedure linkage table. */ + +static bfd_vma +elf_xtensa_create_plt_entry (dynobj, output_bfd, reloc_index) + bfd *dynobj; + bfd *output_bfd; + unsigned reloc_index; +{ + asection *splt, *sgotplt; + bfd_vma plt_base, got_base; + bfd_vma code_offset, lit_offset; + int chunk; + + chunk = reloc_index / PLT_ENTRIES_PER_CHUNK; + splt = elf_xtensa_get_plt_section (dynobj, chunk); + sgotplt = elf_xtensa_get_gotplt_section (dynobj, chunk); + BFD_ASSERT (splt != NULL && sgotplt != NULL); + + plt_base = splt->output_section->vma + splt->output_offset; + got_base = sgotplt->output_section->vma + sgotplt->output_offset; + + lit_offset = 8 + (reloc_index % PLT_ENTRIES_PER_CHUNK) * 4; + code_offset = (reloc_index % PLT_ENTRIES_PER_CHUNK) * PLT_ENTRY_SIZE; + + /* Fill in the literal entry. This is the offset of the dynamic + relocation entry. */ + bfd_put_32 (output_bfd, reloc_index * sizeof (Elf32_External_Rela), + sgotplt->contents + lit_offset); + + /* Fill in the entry in the procedure linkage table. */ + memcpy (splt->contents + code_offset, + (bfd_big_endian (output_bfd) + ? elf_xtensa_be_plt_entry + : elf_xtensa_le_plt_entry), + PLT_ENTRY_SIZE); + bfd_put_16 (output_bfd, l32r_offset (got_base + 0, + plt_base + code_offset + 3), + splt->contents + code_offset + 4); + bfd_put_16 (output_bfd, l32r_offset (got_base + 4, + plt_base + code_offset + 6), + splt->contents + code_offset + 7); + bfd_put_16 (output_bfd, l32r_offset (got_base + lit_offset, + plt_base + code_offset + 9), + splt->contents + code_offset + 10); + + return plt_base + code_offset; +} + + +/* Relocate an Xtensa ELF section. This is invoked by the linker for + both relocatable and final links. */ + +static bfd_boolean +elf_xtensa_relocate_section (output_bfd, info, input_bfd, + input_section, contents, relocs, + local_syms, local_sections) + bfd *output_bfd; + struct bfd_link_info *info; + bfd *input_bfd; + asection *input_section; + bfd_byte *contents; + Elf_Internal_Rela *relocs; + Elf_Internal_Sym *local_syms; + asection **local_sections; +{ + Elf_Internal_Shdr *symtab_hdr; + Elf_Internal_Rela *rel; + Elf_Internal_Rela *relend; + struct elf_link_hash_entry **sym_hashes; + asection *srelgot, *srelplt; + bfd *dynobj; + char *error_message = NULL; + + if (xtensa_default_isa == NULL) + xtensa_isa_init (); + + dynobj = elf_hash_table (info)->dynobj; + symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr; + sym_hashes = elf_sym_hashes (input_bfd); + + srelgot = NULL; + srelplt = NULL; + if (dynobj != NULL) + { + srelgot = bfd_get_section_by_name (dynobj, ".rela.got");; + srelplt = bfd_get_section_by_name (dynobj, ".rela.plt"); + } + + rel = relocs; + relend = relocs + input_section->reloc_count; + for (; rel < relend; rel++) + { + int r_type; + reloc_howto_type *howto; + unsigned long r_symndx; + struct elf_link_hash_entry *h; + Elf_Internal_Sym *sym; + asection *sec; + bfd_vma relocation; + bfd_reloc_status_type r; + bfd_boolean is_weak_undef; + bfd_boolean unresolved_reloc; + bfd_boolean warned; + + r_type = ELF32_R_TYPE (rel->r_info); + if (r_type == (int) R_XTENSA_GNU_VTINHERIT + || r_type == (int) R_XTENSA_GNU_VTENTRY) + continue; + + if (r_type < 0 || r_type >= (int) R_XTENSA_max) + { + bfd_set_error (bfd_error_bad_value); + return FALSE; + } + howto = &elf_howto_table[r_type]; + + r_symndx = ELF32_R_SYM (rel->r_info); + + if (info->relocatable) + { + /* This is a relocatable link. + 1) If the reloc is against a section symbol, adjust + according to the output section. + 2) If there is a new target for this relocation, + the new target will be in the same output section. + We adjust the relocation by the output section + difference. */ + + if (relaxing_section) + { + /* Check if this references a section in another input file. */ + do_fix_for_relocatable_link (rel, input_bfd, input_section); + r_type = ELF32_R_TYPE (rel->r_info); + } + + if (r_type == R_XTENSA_ASM_SIMPLIFY) + { + /* Convert ASM_SIMPLIFY into the simpler relocation + so that they never escape a relaxing link. */ + contract_asm_expansion (contents, input_section->_raw_size, rel); + r_type = ELF32_R_TYPE (rel->r_info); + } + + /* This is a relocatable link, so we don't have to change + anything unless the reloc is against a section symbol, + in which case we have to adjust according to where the + section symbol winds up in the output section. */ + if (r_symndx < symtab_hdr->sh_info) + { + sym = local_syms + r_symndx; + if (ELF_ST_TYPE (sym->st_info) == STT_SECTION) + { + sec = local_sections[r_symndx]; + rel->r_addend += sec->output_offset + sym->st_value; + } + } + + /* If there is an addend with a partial_inplace howto, + then move the addend to the contents. This is a hack + to work around problems with DWARF in relocatable links + with some previous version of BFD. Now we can't easily get + rid of the hack without breaking backward compatibility.... */ + if (rel->r_addend) + { + howto = &elf_howto_table[r_type]; + if (howto->partial_inplace) + { + r = elf_xtensa_do_reloc (howto, input_bfd, input_section, + rel->r_addend, contents, + rel->r_offset, FALSE, + &error_message); + if (r != bfd_reloc_ok) + { + if (!((*info->callbacks->reloc_dangerous) + (info, error_message, input_bfd, input_section, + rel->r_offset))) + return FALSE; + } + rel->r_addend = 0; + } + } + + /* Done with work for relocatable link; continue with next reloc. */ + continue; + } + + /* This is a final link. */ + + h = NULL; + sym = NULL; + sec = NULL; + is_weak_undef = FALSE; + unresolved_reloc = FALSE; + warned = FALSE; + + if (howto->partial_inplace) + { + /* Because R_XTENSA_32 was made partial_inplace to fix some + problems with DWARF info in partial links, there may be + an addend stored in the contents. Take it out of there + and move it back into the addend field of the reloc. */ + rel->r_addend += bfd_get_32 (input_bfd, contents + rel->r_offset); + bfd_put_32 (input_bfd, 0, contents + rel->r_offset); + } + + if (r_symndx < symtab_hdr->sh_info) + { + sym = local_syms + r_symndx; + sec = local_sections[r_symndx]; + relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel); + } + else + { + RELOC_FOR_GLOBAL_SYMBOL (h, sym_hashes, r_symndx, + symtab_hdr, relocation, sec, + unresolved_reloc, info, + warned); + + if (relocation == 0 + && !unresolved_reloc + && h->root.type == bfd_link_hash_undefweak) + is_weak_undef = TRUE; + } + + if (relaxing_section) + { + /* Check if this references a section in another input file. */ + do_fix_for_final_link (rel, input_section, &relocation); + + /* Update some already cached values. */ + r_type = ELF32_R_TYPE (rel->r_info); + howto = &elf_howto_table[r_type]; + } + + /* Sanity check the address. */ + if (rel->r_offset >= input_section->_raw_size + && ELF32_R_TYPE (rel->r_info) != R_XTENSA_NONE) + { + bfd_set_error (bfd_error_bad_value); + return FALSE; + } + + /* Generate dynamic relocations. */ + if (elf_hash_table (info)->dynamic_sections_created) + { + bfd_boolean dynamic_symbol = xtensa_elf_dynamic_symbol_p (h, info); + + if (dynamic_symbol && (r_type == R_XTENSA_OP0 + || r_type == R_XTENSA_OP1 + || r_type == R_XTENSA_OP2)) + { + /* This is an error. The symbol's real value won't be known + until runtime and it's likely to be out of range anyway. */ + const char *name = h->root.root.string; + error_message = vsprint_msg ("invalid relocation for dynamic " + "symbol", ": %s", + strlen (name) + 2, name); + if (!((*info->callbacks->reloc_dangerous) + (info, error_message, input_bfd, input_section, + rel->r_offset))) + return FALSE; + } + else if ((r_type == R_XTENSA_32 || r_type == R_XTENSA_PLT) + && (input_section->flags & SEC_ALLOC) != 0 + && (dynamic_symbol || info->shared)) + { + Elf_Internal_Rela outrel; + bfd_byte *loc; + asection *srel; + + if (dynamic_symbol && r_type == R_XTENSA_PLT) + srel = srelplt; + else + srel = srelgot; + + BFD_ASSERT (srel != NULL); + + outrel.r_offset = + _bfd_elf_section_offset (output_bfd, info, + input_section, rel->r_offset); + + if ((outrel.r_offset | 1) == (bfd_vma) -1) + memset (&outrel, 0, sizeof outrel); + else + { + outrel.r_offset += (input_section->output_section->vma + + input_section->output_offset); + + if (dynamic_symbol) + { + outrel.r_addend = rel->r_addend; + rel->r_addend = 0; + + if (r_type == R_XTENSA_32) + { + outrel.r_info = + ELF32_R_INFO (h->dynindx, R_XTENSA_GLOB_DAT); + relocation = 0; + } + else /* r_type == R_XTENSA_PLT */ + { + outrel.r_info = + ELF32_R_INFO (h->dynindx, R_XTENSA_JMP_SLOT); + + /* Create the PLT entry and set the initial + contents of the literal entry to the address of + the PLT entry. */ + relocation = + elf_xtensa_create_plt_entry (dynobj, output_bfd, + srel->reloc_count); + } + unresolved_reloc = FALSE; + } + else + { + /* Generate a RELATIVE relocation. */ + outrel.r_info = ELF32_R_INFO (0, R_XTENSA_RELATIVE); + outrel.r_addend = 0; + } + } + + loc = (srel->contents + + srel->reloc_count++ * sizeof (Elf32_External_Rela)); + bfd_elf32_swap_reloca_out (output_bfd, &outrel, loc); + BFD_ASSERT (sizeof (Elf32_External_Rela) * srel->reloc_count + <= srel->_cooked_size); + } + } + + /* Dynamic relocs are not propagated for SEC_DEBUGGING sections + because such sections are not SEC_ALLOC and thus ld.so will + not process them. */ + if (unresolved_reloc + && !((input_section->flags & SEC_DEBUGGING) != 0 + && (h->elf_link_hash_flags & ELF_LINK_HASH_DEF_DYNAMIC) != 0)) + (*_bfd_error_handler) + (_("%s(%s+0x%lx): unresolvable relocation against symbol `%s'"), + bfd_archive_filename (input_bfd), + bfd_get_section_name (input_bfd, input_section), + (long) rel->r_offset, + h->root.root.string); + + /* There's no point in calling bfd_perform_relocation here. + Just go directly to our "special function". */ + r = elf_xtensa_do_reloc (howto, input_bfd, input_section, + relocation + rel->r_addend, + contents, rel->r_offset, is_weak_undef, + &error_message); + + if (r != bfd_reloc_ok && !warned) + { + const char *name; + + BFD_ASSERT (r == bfd_reloc_dangerous); + BFD_ASSERT (error_message != (char *) NULL); + + if (h != NULL) + name = h->root.root.string; + else + { + name = bfd_elf_string_from_elf_section + (input_bfd, symtab_hdr->sh_link, sym->st_name); + if (name && *name == '\0') + name = bfd_section_name (input_bfd, sec); + } + if (name) + error_message = vsprint_msg (error_message, ": %s", + strlen (name), name); + if (!((*info->callbacks->reloc_dangerous) + (info, error_message, input_bfd, input_section, + rel->r_offset))) + return FALSE; + } + } + + return TRUE; +} + + +/* Finish up dynamic symbol handling. There's not much to do here since + the PLT and GOT entries are all set up by relocate_section. */ + +static bfd_boolean +elf_xtensa_finish_dynamic_symbol (output_bfd, info, h, sym) + bfd *output_bfd ATTRIBUTE_UNUSED; + struct bfd_link_info *info ATTRIBUTE_UNUSED; + struct elf_link_hash_entry *h; + Elf_Internal_Sym *sym; +{ + if ((h->elf_link_hash_flags & ELF_LINK_HASH_NEEDS_PLT) != 0 + && (h->elf_link_hash_flags & ELF_LINK_HASH_DEF_REGULAR) == 0) + { + /* Mark the symbol as undefined, rather than as defined in + the .plt section. Leave the value alone. */ + sym->st_shndx = SHN_UNDEF; + } + + /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute. */ + if (strcmp (h->root.root.string, "_DYNAMIC") == 0 + || strcmp (h->root.root.string, "_GLOBAL_OFFSET_TABLE_") == 0) + sym->st_shndx = SHN_ABS; + + return TRUE; +} + + +/* Combine adjacent literal table entries in the output. Adjacent + entries within each input section may have been removed during + relaxation, but we repeat the process here, even though it's too late + to shrink the output section, because it's important to minimize the + number of literal table entries to reduce the start-up work for the + runtime linker. Returns the number of remaining table entries or -1 + on error. */ + +static int +elf_xtensa_combine_prop_entries (output_bfd, sxtlit, sgotloc) + bfd *output_bfd; + asection *sxtlit; + asection *sgotloc; +{ + bfd_byte *contents; + property_table_entry *table; + bfd_size_type section_size, sgotloc_size; + bfd_vma offset; + int n, m, num; + + section_size = (sxtlit->_cooked_size != 0 + ? sxtlit->_cooked_size : sxtlit->_raw_size); + BFD_ASSERT (section_size % 8 == 0); + num = section_size / 8; + + sgotloc_size = (sgotloc->_cooked_size != 0 + ? sgotloc->_cooked_size : sgotloc->_raw_size); + if (sgotloc_size != section_size) + { + (*_bfd_error_handler) + ("internal inconsistency in size of .got.loc section"); + return -1; + } + + contents = (bfd_byte *) bfd_malloc (section_size); + table = (property_table_entry *) + bfd_malloc (num * sizeof (property_table_entry)); + if (contents == 0 || table == 0) + return -1; + + /* The ".xt.lit.plt" section has the SEC_IN_MEMORY flag set and this + propagates to the output section, where it doesn't really apply and + where it breaks the following call to bfd_get_section_contents. */ + sxtlit->flags &= ~SEC_IN_MEMORY; + + if (! bfd_get_section_contents (output_bfd, sxtlit, contents, 0, + section_size)) + return -1; + + /* There should never be any relocations left at this point, so this + is quite a bit easier than what is done during relaxation. */ + + /* Copy the raw contents into a property table array and sort it. */ + offset = 0; + for (n = 0; n < num; n++) + { + table[n].address = bfd_get_32 (output_bfd, &contents[offset]); + table[n].size = bfd_get_32 (output_bfd, &contents[offset + 4]); + offset += 8; + } + qsort (table, num, sizeof (property_table_entry), property_table_compare); + + for (n = 0; n < num; n++) + { + bfd_boolean remove = FALSE; + + if (table[n].size == 0) + remove = TRUE; + else if (n > 0 && + (table[n-1].address + table[n-1].size == table[n].address)) + { + table[n-1].size += table[n].size; + remove = TRUE; + } + + if (remove) + { + for (m = n; m < num - 1; m++) + { + table[m].address = table[m+1].address; + table[m].size = table[m+1].size; + } + + n--; + num--; + } + } + + /* Copy the data back to the raw contents. */ + offset = 0; + for (n = 0; n < num; n++) + { + bfd_put_32 (output_bfd, table[n].address, &contents[offset]); + bfd_put_32 (output_bfd, table[n].size, &contents[offset + 4]); + offset += 8; + } + + /* Clear the removed bytes. */ + if ((bfd_size_type) (num * 8) < section_size) + { + memset (&contents[num * 8], 0, section_size - num * 8); + sxtlit->_cooked_size = num * 8; + } + + if (! bfd_set_section_contents (output_bfd, sxtlit, contents, 0, + section_size)) + return -1; + + /* Copy the contents to ".got.loc". */ + memcpy (sgotloc->contents, contents, section_size); + + free (contents); + free (table); + return num; +} + + +/* Finish up the dynamic sections. */ + +static bfd_boolean +elf_xtensa_finish_dynamic_sections (output_bfd, info) + bfd *output_bfd; + struct bfd_link_info *info; +{ + bfd *dynobj; + asection *sdyn, *srelplt, *sgot, *sxtlit, *sgotloc; + Elf32_External_Dyn *dyncon, *dynconend; + int num_xtlit_entries; + + if (! elf_hash_table (info)->dynamic_sections_created) + return TRUE; + + dynobj = elf_hash_table (info)->dynobj; + sdyn = bfd_get_section_by_name (dynobj, ".dynamic"); + BFD_ASSERT (sdyn != NULL); + + /* Set the first entry in the global offset table to the address of + the dynamic section. */ + sgot = bfd_get_section_by_name (dynobj, ".got"); + if (sgot) + { + BFD_ASSERT (sgot->_raw_size == 4); + if (sdyn == NULL) + bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents); + else + bfd_put_32 (output_bfd, + sdyn->output_section->vma + sdyn->output_offset, + sgot->contents); + } + + srelplt = bfd_get_section_by_name (dynobj, ".rela.plt"); + if (srelplt != NULL && srelplt->_raw_size != 0) + { + asection *sgotplt, *srelgot, *spltlittbl; + int chunk, plt_chunks, plt_entries; + Elf_Internal_Rela irela; + bfd_byte *loc; + unsigned rtld_reloc; + + srelgot = bfd_get_section_by_name (dynobj, ".rela.got");; + BFD_ASSERT (srelgot != NULL); + + spltlittbl = bfd_get_section_by_name (dynobj, ".xt.lit.plt"); + BFD_ASSERT (spltlittbl != NULL); + + /* Find the first XTENSA_RTLD relocation. Presumably the rest + of them follow immediately after.... */ + for (rtld_reloc = 0; rtld_reloc < srelgot->reloc_count; rtld_reloc++) + { + loc = srelgot->contents + rtld_reloc * sizeof (Elf32_External_Rela); + bfd_elf32_swap_reloca_in (output_bfd, loc, &irela); + if (ELF32_R_TYPE (irela.r_info) == R_XTENSA_RTLD) + break; + } + BFD_ASSERT (rtld_reloc < srelgot->reloc_count); + + plt_entries = (srelplt->_raw_size / sizeof (Elf32_External_Rela)); + plt_chunks = + (plt_entries + PLT_ENTRIES_PER_CHUNK - 1) / PLT_ENTRIES_PER_CHUNK; + + for (chunk = 0; chunk < plt_chunks; chunk++) + { + int chunk_entries = 0; + + sgotplt = elf_xtensa_get_gotplt_section (dynobj, chunk); + BFD_ASSERT (sgotplt != NULL); + + /* Emit special RTLD relocations for the first two entries in + each chunk of the .got.plt section. */ + + loc = srelgot->contents + rtld_reloc * sizeof (Elf32_External_Rela); + bfd_elf32_swap_reloca_in (output_bfd, loc, &irela); + BFD_ASSERT (ELF32_R_TYPE (irela.r_info) == R_XTENSA_RTLD); + irela.r_offset = (sgotplt->output_section->vma + + sgotplt->output_offset); + irela.r_addend = 1; /* tell rtld to set value to resolver function */ + bfd_elf32_swap_reloca_out (output_bfd, &irela, loc); + rtld_reloc += 1; + BFD_ASSERT (rtld_reloc <= srelgot->reloc_count); + + /* Next literal immediately follows the first. */ + loc += sizeof (Elf32_External_Rela); + bfd_elf32_swap_reloca_in (output_bfd, loc, &irela); + BFD_ASSERT (ELF32_R_TYPE (irela.r_info) == R_XTENSA_RTLD); + irela.r_offset = (sgotplt->output_section->vma + + sgotplt->output_offset + 4); + /* Tell rtld to set value to object's link map. */ + irela.r_addend = 2; + bfd_elf32_swap_reloca_out (output_bfd, &irela, loc); + rtld_reloc += 1; + BFD_ASSERT (rtld_reloc <= srelgot->reloc_count); + + /* Fill in the literal table. */ + if (chunk < plt_chunks - 1) + chunk_entries = PLT_ENTRIES_PER_CHUNK; + else + chunk_entries = plt_entries - (chunk * PLT_ENTRIES_PER_CHUNK); + + BFD_ASSERT ((unsigned) (chunk + 1) * 8 <= spltlittbl->_cooked_size); + bfd_put_32 (output_bfd, + sgotplt->output_section->vma + sgotplt->output_offset, + spltlittbl->contents + (chunk * 8) + 0); + bfd_put_32 (output_bfd, + 8 + (chunk_entries * 4), + spltlittbl->contents + (chunk * 8) + 4); + } + + /* All the dynamic relocations have been emitted at this point. + Make sure the relocation sections are the correct size. */ + if (srelgot->_cooked_size != (sizeof (Elf32_External_Rela) + * srelgot->reloc_count) + || srelplt->_cooked_size != (sizeof (Elf32_External_Rela) + * srelplt->reloc_count)) + abort (); + + /* The .xt.lit.plt section has just been modified. This must + happen before the code below which combines adjacent literal + table entries, and the .xt.lit.plt contents have to be forced to + the output here. */ + if (! bfd_set_section_contents (output_bfd, + spltlittbl->output_section, + spltlittbl->contents, + spltlittbl->output_offset, + spltlittbl->_raw_size)) + return FALSE; + /* Clear SEC_HAS_CONTENTS so the contents won't be output again. */ + spltlittbl->flags &= ~SEC_HAS_CONTENTS; + } + + /* Combine adjacent literal table entries. */ + BFD_ASSERT (! info->relocatable); + sxtlit = bfd_get_section_by_name (output_bfd, ".xt.lit"); + sgotloc = bfd_get_section_by_name (dynobj, ".got.loc"); + BFD_ASSERT (sxtlit && sgotloc); + num_xtlit_entries = + elf_xtensa_combine_prop_entries (output_bfd, sxtlit, sgotloc); + if (num_xtlit_entries < 0) + return FALSE; + + dyncon = (Elf32_External_Dyn *) sdyn->contents; + dynconend = (Elf32_External_Dyn *) (sdyn->contents + sdyn->_raw_size); + for (; dyncon < dynconend; dyncon++) + { + Elf_Internal_Dyn dyn; + const char *name; + asection *s; + + bfd_elf32_swap_dyn_in (dynobj, dyncon, &dyn); + + switch (dyn.d_tag) + { + default: + break; + + case DT_XTENSA_GOT_LOC_SZ: + dyn.d_un.d_val = num_xtlit_entries; + break; + + case DT_XTENSA_GOT_LOC_OFF: + name = ".got.loc"; + goto get_vma; + case DT_PLTGOT: + name = ".got"; + goto get_vma; + case DT_JMPREL: + name = ".rela.plt"; + get_vma: + s = bfd_get_section_by_name (output_bfd, name); + BFD_ASSERT (s); + dyn.d_un.d_ptr = s->vma; + break; + + case DT_PLTRELSZ: + s = bfd_get_section_by_name (output_bfd, ".rela.plt"); + BFD_ASSERT (s); + dyn.d_un.d_val = (s->_cooked_size ? s->_cooked_size : s->_raw_size); + break; + + case DT_RELASZ: + /* Adjust RELASZ to not include JMPREL. This matches what + glibc expects and what is done for several other ELF + targets (e.g., i386, alpha), but the "correct" behavior + seems to be unresolved. Since the linker script arranges + for .rela.plt to follow all other relocation sections, we + don't have to worry about changing the DT_RELA entry. */ + s = bfd_get_section_by_name (output_bfd, ".rela.plt"); + if (s) + { + dyn.d_un.d_val -= + (s->_cooked_size ? s->_cooked_size : s->_raw_size); + } + break; + } + + bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon); + } + + return TRUE; +} + + +/* Functions for dealing with the e_flags field. */ + +/* Merge backend specific data from an object file to the output + object file when linking. */ + +static bfd_boolean +elf_xtensa_merge_private_bfd_data (ibfd, obfd) + bfd *ibfd; + bfd *obfd; +{ + unsigned out_mach, in_mach; + flagword out_flag, in_flag; + + /* Check if we have the same endianess. */ + if (!_bfd_generic_verify_endian_match (ibfd, obfd)) + return FALSE; + + /* Don't even pretend to support mixed-format linking. */ + if (bfd_get_flavour (ibfd) != bfd_target_elf_flavour + || bfd_get_flavour (obfd) != bfd_target_elf_flavour) + return FALSE; + + out_flag = elf_elfheader (obfd)->e_flags; + in_flag = elf_elfheader (ibfd)->e_flags; + + out_mach = out_flag & EF_XTENSA_MACH; + in_mach = in_flag & EF_XTENSA_MACH; + if (out_mach != in_mach) + { + (*_bfd_error_handler) + ("%s: incompatible machine type. Output is 0x%x. Input is 0x%x", + bfd_archive_filename (ibfd), out_mach, in_mach); + bfd_set_error (bfd_error_wrong_format); + return FALSE; + } + + if (! elf_flags_init (obfd)) + { + elf_flags_init (obfd) = TRUE; + elf_elfheader (obfd)->e_flags = in_flag; + + if (bfd_get_arch (obfd) == bfd_get_arch (ibfd) + && bfd_get_arch_info (obfd)->the_default) + return bfd_set_arch_mach (obfd, bfd_get_arch (ibfd), + bfd_get_mach (ibfd)); + + return TRUE; + } + + if ((out_flag & EF_XTENSA_XT_INSN) != + (in_flag & EF_XTENSA_XT_INSN)) + elf_elfheader(obfd)->e_flags &= (~ EF_XTENSA_XT_INSN); + + if ((out_flag & EF_XTENSA_XT_LIT) != + (in_flag & EF_XTENSA_XT_LIT)) + elf_elfheader(obfd)->e_flags &= (~ EF_XTENSA_XT_LIT); + + return TRUE; +} + + +static bfd_boolean +elf_xtensa_set_private_flags (abfd, flags) + bfd *abfd; + flagword flags; +{ + BFD_ASSERT (!elf_flags_init (abfd) + || elf_elfheader (abfd)->e_flags == flags); + + elf_elfheader (abfd)->e_flags |= flags; + elf_flags_init (abfd) = TRUE; + + return TRUE; +} + + +extern flagword +elf_xtensa_get_private_bfd_flags (abfd) + bfd *abfd; +{ + return elf_elfheader (abfd)->e_flags; +} + + +static bfd_boolean +elf_xtensa_print_private_bfd_data (abfd, farg) + bfd *abfd; + PTR farg; +{ + FILE *f = (FILE *) farg; + flagword e_flags = elf_elfheader (abfd)->e_flags; + + fprintf (f, "\nXtensa header:\n"); + if ((e_flags & EF_XTENSA_MACH) == E_XTENSA_MACH) + fprintf (f, "\nMachine = Base\n"); + else + fprintf (f, "\nMachine Id = 0x%x\n", e_flags & EF_XTENSA_MACH); + + fprintf (f, "Insn tables = %s\n", + (e_flags & EF_XTENSA_XT_INSN) ? "true" : "false"); + + fprintf (f, "Literal tables = %s\n", + (e_flags & EF_XTENSA_XT_LIT) ? "true" : "false"); + + return _bfd_elf_print_private_bfd_data (abfd, farg); +} + + +/* Set the right machine number for an Xtensa ELF file. */ + +static bfd_boolean +elf_xtensa_object_p (abfd) + bfd *abfd; +{ + int mach; + unsigned long arch = elf_elfheader (abfd)->e_flags & EF_XTENSA_MACH; + + switch (arch) + { + case E_XTENSA_MACH: + mach = bfd_mach_xtensa; + break; + default: + return FALSE; + } + + (void) bfd_default_set_arch_mach (abfd, bfd_arch_xtensa, mach); + return TRUE; +} + + +/* The final processing done just before writing out an Xtensa ELF object + file. This gets the Xtensa architecture right based on the machine + number. */ + +static void +elf_xtensa_final_write_processing (abfd, linker) + bfd *abfd; + bfd_boolean linker ATTRIBUTE_UNUSED; +{ + int mach; + unsigned long val; + + switch (mach = bfd_get_mach (abfd)) + { + case bfd_mach_xtensa: + val = E_XTENSA_MACH; + break; + default: + return; + } + + elf_elfheader (abfd)->e_flags &= (~ EF_XTENSA_MACH); + elf_elfheader (abfd)->e_flags |= val; +} + + +static enum elf_reloc_type_class +elf_xtensa_reloc_type_class (rela) + const Elf_Internal_Rela *rela; +{ + switch ((int) ELF32_R_TYPE (rela->r_info)) + { + case R_XTENSA_RELATIVE: + return reloc_class_relative; + case R_XTENSA_JMP_SLOT: + return reloc_class_plt; + default: + return reloc_class_normal; + } +} + + +static bfd_boolean +elf_xtensa_discard_info_for_section (abfd, cookie, info, sec) + bfd *abfd; + struct elf_reloc_cookie *cookie; + struct bfd_link_info *info; + asection *sec; +{ + bfd_byte *contents; + bfd_vma section_size; + bfd_vma offset, actual_offset; + size_t removed_bytes = 0; + + section_size = (sec->_cooked_size ? sec->_cooked_size : sec->_raw_size); + if (section_size == 0 || section_size % 8 != 0) + return FALSE; + + if (sec->output_section + && bfd_is_abs_section (sec->output_section)) + return FALSE; + + contents = retrieve_contents (abfd, sec, info->keep_memory); + if (!contents) + return FALSE; + + cookie->rels = retrieve_internal_relocs (abfd, sec, info->keep_memory); + if (!cookie->rels) + { + release_contents (sec, contents); + return FALSE; + } + + cookie->rel = cookie->rels; + cookie->relend = cookie->rels + sec->reloc_count; + + for (offset = 0; offset < section_size; offset += 8) + { + actual_offset = offset - removed_bytes; + + /* The ...symbol_deleted_p function will skip over relocs but it + won't adjust their offsets, so do that here. */ + while (cookie->rel < cookie->relend + && cookie->rel->r_offset < offset) + { + cookie->rel->r_offset -= removed_bytes; + cookie->rel++; + } + + while (cookie->rel < cookie->relend + && cookie->rel->r_offset == offset) + { + if (_bfd_elf32_reloc_symbol_deleted_p (offset, cookie)) + { + /* Remove the table entry. (If the reloc type is NONE, then + the entry has already been merged with another and deleted + during relaxation.) */ + if (ELF32_R_TYPE (cookie->rel->r_info) != R_XTENSA_NONE) + { + /* Shift the contents up. */ + if (offset + 8 < section_size) + memmove (&contents[actual_offset], + &contents[actual_offset+8], + section_size - offset - 8); + removed_bytes += 8; + } + + /* Remove this relocation. */ + cookie->rel->r_info = ELF32_R_INFO (0, R_XTENSA_NONE); + } + + /* Adjust the relocation offset for previous removals. This + should not be done before calling ...symbol_deleted_p + because it might mess up the offset comparisons there. + Make sure the offset doesn't underflow in the case where + the first entry is removed. */ + if (cookie->rel->r_offset >= removed_bytes) + cookie->rel->r_offset -= removed_bytes; + else + cookie->rel->r_offset = 0; + + cookie->rel++; + } + } + + if (removed_bytes != 0) + { + /* Adjust any remaining relocs (shouldn't be any). */ + for (; cookie->rel < cookie->relend; cookie->rel++) + { + if (cookie->rel->r_offset >= removed_bytes) + cookie->rel->r_offset -= removed_bytes; + else + cookie->rel->r_offset = 0; + } + + /* Clear the removed bytes. */ + memset (&contents[section_size - removed_bytes], 0, removed_bytes); + + pin_contents (sec, contents); + pin_internal_relocs (sec, cookie->rels); + + sec->_cooked_size = section_size - removed_bytes; + /* Also shrink _raw_size. See comments in relax_property_section. */ + sec->_raw_size = sec->_cooked_size; + + if (xtensa_is_littable_section (sec)) + { + bfd *dynobj = elf_hash_table (info)->dynobj; + if (dynobj) + { + asection *sgotloc = + bfd_get_section_by_name (dynobj, ".got.loc"); + if (sgotloc) + { + bfd_size_type sgotloc_size = + (sgotloc->_cooked_size ? sgotloc->_cooked_size + : sgotloc->_raw_size); + sgotloc->_cooked_size = sgotloc_size - removed_bytes; + sgotloc->_raw_size = sgotloc_size - removed_bytes; + } + } + } + } + else + { + release_contents (sec, contents); + release_internal_relocs (sec, cookie->rels); + } + + return (removed_bytes != 0); +} + + +static bfd_boolean +elf_xtensa_discard_info (abfd, cookie, info) + bfd *abfd; + struct elf_reloc_cookie *cookie; + struct bfd_link_info *info; +{ + asection *sec; + bfd_boolean changed = FALSE; + + for (sec = abfd->sections; sec != NULL; sec = sec->next) + { + if (xtensa_is_property_section (sec)) + { + if (elf_xtensa_discard_info_for_section (abfd, cookie, info, sec)) + changed = TRUE; + } + } + + return changed; +} + + +static bfd_boolean +elf_xtensa_ignore_discarded_relocs (sec) + asection *sec; +{ + return xtensa_is_property_section (sec); +} + + +/* Support for core dump NOTE sections. */ + +static bfd_boolean +elf_xtensa_grok_prstatus (abfd, note) + bfd *abfd; + Elf_Internal_Note *note; +{ + int offset; + unsigned int raw_size; + + /* The size for Xtensa is variable, so don't try to recognize the format + based on the size. Just assume this is GNU/Linux. */ + + /* pr_cursig */ + elf_tdata (abfd)->core_signal = bfd_get_16 (abfd, note->descdata + 12); + + /* pr_pid */ + elf_tdata (abfd)->core_pid = bfd_get_32 (abfd, note->descdata + 24); + + /* pr_reg */ + offset = 72; + raw_size = note->descsz - offset - 4; + + /* Make a ".reg/999" section. */ + return _bfd_elfcore_make_pseudosection (abfd, ".reg", + raw_size, note->descpos + offset); +} + + +static bfd_boolean +elf_xtensa_grok_psinfo (abfd, note) + bfd *abfd; + Elf_Internal_Note *note; +{ + switch (note->descsz) + { + default: + return FALSE; + + case 128: /* GNU/Linux elf_prpsinfo */ + elf_tdata (abfd)->core_program + = _bfd_elfcore_strndup (abfd, note->descdata + 32, 16); + elf_tdata (abfd)->core_command + = _bfd_elfcore_strndup (abfd, note->descdata + 48, 80); + } + + /* Note that for some reason, a spurious space is tacked + onto the end of the args in some (at least one anyway) + implementations, so strip it off if it exists. */ + + { + char *command = elf_tdata (abfd)->core_command; + int n = strlen (command); + + if (0 < n && command[n - 1] == ' ') + command[n - 1] = '\0'; + } + + return TRUE; +} + + +/* Generic Xtensa configurability stuff. */ + +static xtensa_opcode callx0_op = XTENSA_UNDEFINED; +static xtensa_opcode callx4_op = XTENSA_UNDEFINED; +static xtensa_opcode callx8_op = XTENSA_UNDEFINED; +static xtensa_opcode callx12_op = XTENSA_UNDEFINED; +static xtensa_opcode call0_op = XTENSA_UNDEFINED; +static xtensa_opcode call4_op = XTENSA_UNDEFINED; +static xtensa_opcode call8_op = XTENSA_UNDEFINED; +static xtensa_opcode call12_op = XTENSA_UNDEFINED; + +static void +init_call_opcodes () +{ + if (callx0_op == XTENSA_UNDEFINED) + { + callx0_op = xtensa_opcode_lookup (xtensa_default_isa, "callx0"); + callx4_op = xtensa_opcode_lookup (xtensa_default_isa, "callx4"); + callx8_op = xtensa_opcode_lookup (xtensa_default_isa, "callx8"); + callx12_op = xtensa_opcode_lookup (xtensa_default_isa, "callx12"); + call0_op = xtensa_opcode_lookup (xtensa_default_isa, "call0"); + call4_op = xtensa_opcode_lookup (xtensa_default_isa, "call4"); + call8_op = xtensa_opcode_lookup (xtensa_default_isa, "call8"); + call12_op = xtensa_opcode_lookup (xtensa_default_isa, "call12"); + } +} + + +static bfd_boolean +is_indirect_call_opcode (opcode) + xtensa_opcode opcode; +{ + init_call_opcodes (); + return (opcode == callx0_op + || opcode == callx4_op + || opcode == callx8_op + || opcode == callx12_op); +} + + +static bfd_boolean +is_direct_call_opcode (opcode) + xtensa_opcode opcode; +{ + init_call_opcodes (); + return (opcode == call0_op + || opcode == call4_op + || opcode == call8_op + || opcode == call12_op); +} + + +static bfd_boolean +is_windowed_call_opcode (opcode) + xtensa_opcode opcode; +{ + init_call_opcodes (); + return (opcode == call4_op + || opcode == call8_op + || opcode == call12_op + || opcode == callx4_op + || opcode == callx8_op + || opcode == callx12_op); +} + + +static xtensa_opcode +get_l32r_opcode (void) +{ + static xtensa_opcode l32r_opcode = XTENSA_UNDEFINED; + if (l32r_opcode == XTENSA_UNDEFINED) + { + l32r_opcode = xtensa_opcode_lookup (xtensa_default_isa, "l32r"); + BFD_ASSERT (l32r_opcode != XTENSA_UNDEFINED); + } + return l32r_opcode; +} + + +static bfd_vma +l32r_offset (addr, pc) + bfd_vma addr; + bfd_vma pc; +{ + bfd_vma offset; + + offset = addr - ((pc+3) & -4); + BFD_ASSERT ((offset & ((1 << 2) - 1)) == 0); + offset = (signed int) offset >> 2; + BFD_ASSERT ((signed int) offset >> 16 == -1); + return offset; +} + + +/* Get the operand number for a PC-relative relocation. + If the relocation is not a PC-relative one, return (-1). */ + +static int +get_relocation_opnd (irel) + Elf_Internal_Rela *irel; +{ + if (ELF32_R_TYPE (irel->r_info) < R_XTENSA_OP0 + || ELF32_R_TYPE (irel->r_info) >= R_XTENSA_max) + return -1; + return ELF32_R_TYPE (irel->r_info) - R_XTENSA_OP0; +} + + +/* Get the opcode for a relocation. */ + +static xtensa_opcode +get_relocation_opcode (sec, contents, irel) + asection *sec; + bfd_byte *contents; + Elf_Internal_Rela *irel; +{ + static xtensa_insnbuf ibuff = NULL; + xtensa_isa isa = xtensa_default_isa; + + if (get_relocation_opnd (irel) == -1) + return XTENSA_UNDEFINED; + + if (contents == NULL) + return XTENSA_UNDEFINED; + + if (sec->_raw_size <= irel->r_offset) + return XTENSA_UNDEFINED; + + if (ibuff == NULL) + ibuff = xtensa_insnbuf_alloc (isa); + + /* Decode the instruction. */ + xtensa_insnbuf_from_chars (isa, ibuff, &contents[irel->r_offset]); + return xtensa_decode_insn (isa, ibuff); +} + + +bfd_boolean +is_l32r_relocation (sec, contents, irel) + asection *sec; + bfd_byte *contents; + Elf_Internal_Rela *irel; +{ + xtensa_opcode opcode; + + if (ELF32_R_TYPE (irel->r_info) != R_XTENSA_OP1) + return FALSE; + + opcode = get_relocation_opcode (sec, contents, irel); + return (opcode == get_l32r_opcode ()); +} + + +/* Code for transforming CALLs at link-time. */ + +static bfd_reloc_status_type +elf_xtensa_do_asm_simplify (contents, address, content_length) + bfd_byte *contents; + bfd_vma address; + bfd_vma content_length; +{ + static xtensa_insnbuf insnbuf = NULL; + xtensa_opcode opcode; + xtensa_operand operand; + xtensa_opcode direct_call_opcode; + xtensa_isa isa = xtensa_default_isa; + bfd_byte *chbuf = contents + address; + int opn; + + if (insnbuf == NULL) + insnbuf = xtensa_insnbuf_alloc (isa); + + if (content_length < address) + { + (*_bfd_error_handler) + ("Attempt to convert L32R/CALLX to CALL failed"); + return bfd_reloc_other; + } + + opcode = get_expanded_call_opcode (chbuf, content_length - address); + direct_call_opcode = swap_callx_for_call_opcode (opcode); + if (direct_call_opcode == XTENSA_UNDEFINED) + { + (*_bfd_error_handler) + ("Attempt to convert L32R/CALLX to CALL failed"); + return bfd_reloc_other; + } + + /* Assemble a NOP ("or a1, a1, a1") into the 0 byte offset. */ + opcode = xtensa_opcode_lookup (isa, "or"); + xtensa_encode_insn (isa, opcode, insnbuf); + for (opn = 0; opn < 3; opn++) + { + operand = xtensa_get_operand (isa, opcode, opn); + xtensa_operand_set_field (operand, insnbuf, 1); + } + xtensa_insnbuf_to_chars (isa, insnbuf, chbuf); + + /* Assemble a CALL ("callN 0") into the 3 byte offset. */ + xtensa_encode_insn (isa, direct_call_opcode, insnbuf); + operand = xtensa_get_operand (isa, opcode, 0); + xtensa_operand_set_field (operand, insnbuf, 0); + xtensa_insnbuf_to_chars (isa, insnbuf, chbuf + 3); + + return bfd_reloc_ok; +} + + +static bfd_reloc_status_type +contract_asm_expansion (contents, content_length, irel) + bfd_byte *contents; + bfd_vma content_length; + Elf_Internal_Rela *irel; +{ + bfd_reloc_status_type retval = + elf_xtensa_do_asm_simplify (contents, irel->r_offset, content_length); + + if (retval != bfd_reloc_ok) + return retval; + + /* Update the irel->r_offset field so that the right immediate and + the right instruction are modified during the relocation. */ + irel->r_offset += 3; + irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info), R_XTENSA_OP0); + return bfd_reloc_ok; +} + + +static xtensa_opcode +swap_callx_for_call_opcode (opcode) + xtensa_opcode opcode; +{ + init_call_opcodes (); + + if (opcode == callx0_op) return call0_op; + if (opcode == callx4_op) return call4_op; + if (opcode == callx8_op) return call8_op; + if (opcode == callx12_op) return call12_op; + + /* Return XTENSA_UNDEFINED if the opcode is not an indirect call. */ + return XTENSA_UNDEFINED; +} + + +/* Check if "buf" is pointing to a "L32R aN; CALLX aN" sequence, and + if so, return the CALLX opcode. If not, return XTENSA_UNDEFINED. */ + +#define L32R_TARGET_REG_OPERAND 0 +#define CALLN_SOURCE_OPERAND 0 + +static xtensa_opcode +get_expanded_call_opcode (buf, bufsize) + bfd_byte *buf; + int bufsize; +{ + static xtensa_insnbuf insnbuf = NULL; + xtensa_opcode opcode; + xtensa_operand operand; + xtensa_isa isa = xtensa_default_isa; + uint32 regno, call_regno; + + /* Buffer must be at least 6 bytes. */ + if (bufsize < 6) + return XTENSA_UNDEFINED; + + if (insnbuf == NULL) + insnbuf = xtensa_insnbuf_alloc (isa); + + xtensa_insnbuf_from_chars (isa, insnbuf, buf); + opcode = xtensa_decode_insn (isa, insnbuf); + + if (opcode != get_l32r_opcode ()) + return XTENSA_UNDEFINED; + + operand = xtensa_get_operand (isa, opcode, L32R_TARGET_REG_OPERAND); + regno = xtensa_operand_decode + (operand, xtensa_operand_get_field (operand, insnbuf)); + + /* Next instruction should be an CALLXn with operand 0 == regno. */ + xtensa_insnbuf_from_chars (isa, insnbuf, + buf + xtensa_insn_length (isa, opcode)); + opcode = xtensa_decode_insn (isa, insnbuf); + + if (!is_indirect_call_opcode (opcode)) + return XTENSA_UNDEFINED; + + operand = xtensa_get_operand (isa, opcode, CALLN_SOURCE_OPERAND); + call_regno = xtensa_operand_decode + (operand, xtensa_operand_get_field (operand, insnbuf)); + if (call_regno != regno) + return XTENSA_UNDEFINED; + + return opcode; +} + + +/* Data structures used during relaxation. */ + +/* r_reloc: relocation values. */ + +/* Through the relaxation process, we need to keep track of the values + that will result from evaluating relocations. The standard ELF + relocation structure is not sufficient for this purpose because we're + operating on multiple input files at once, so we need to know which + input file a relocation refers to. The r_reloc structure thus + records both the input file (bfd) and ELF relocation. + + For efficiency, an r_reloc also contains a "target_offset" field to + cache the target-section-relative offset value that is represented by + the relocation. */ + +typedef struct r_reloc_struct r_reloc; + +struct r_reloc_struct +{ + bfd *abfd; + Elf_Internal_Rela rela; + bfd_vma target_offset; +}; + +static bfd_boolean r_reloc_is_const + PARAMS ((const r_reloc *)); +static void r_reloc_init + PARAMS ((r_reloc *, bfd *, Elf_Internal_Rela *)); +static bfd_vma r_reloc_get_target_offset + PARAMS ((const r_reloc *)); +static asection *r_reloc_get_section + PARAMS ((const r_reloc *)); +static bfd_boolean r_reloc_is_defined + PARAMS ((const r_reloc *)); +static struct elf_link_hash_entry *r_reloc_get_hash_entry + PARAMS ((const r_reloc *)); + + +/* The r_reloc structure is included by value in literal_value, but not + every literal_value has an associated relocation -- some are simple + constants. In such cases, we set all the fields in the r_reloc + struct to zero. The r_reloc_is_const function should be used to + detect this case. */ + +static bfd_boolean +r_reloc_is_const (r_rel) + const r_reloc *r_rel; +{ + return (r_rel->abfd == NULL); +} + + +static void +r_reloc_init (r_rel, abfd, irel) + r_reloc *r_rel; + bfd *abfd; + Elf_Internal_Rela *irel; +{ + if (irel != NULL) + { + r_rel->rela = *irel; + r_rel->abfd = abfd; + r_rel->target_offset = r_reloc_get_target_offset (r_rel); + } + else + memset (r_rel, 0, sizeof (r_reloc)); +} + + +static bfd_vma +r_reloc_get_target_offset (r_rel) + const r_reloc *r_rel; +{ + bfd_vma target_offset; + unsigned long r_symndx; + + BFD_ASSERT (!r_reloc_is_const (r_rel)); + r_symndx = ELF32_R_SYM (r_rel->rela.r_info); + target_offset = get_elf_r_symndx_offset (r_rel->abfd, r_symndx); + return (target_offset + r_rel->rela.r_addend); +} + + +static struct elf_link_hash_entry * +r_reloc_get_hash_entry (r_rel) + const r_reloc *r_rel; +{ + unsigned long r_symndx = ELF32_R_SYM (r_rel->rela.r_info); + return get_elf_r_symndx_hash_entry (r_rel->abfd, r_symndx); +} + + +static asection * +r_reloc_get_section (r_rel) + const r_reloc *r_rel; +{ + unsigned long r_symndx = ELF32_R_SYM (r_rel->rela.r_info); + return get_elf_r_symndx_section (r_rel->abfd, r_symndx); +} + + +static bfd_boolean +r_reloc_is_defined (r_rel) + const r_reloc *r_rel; +{ + asection *sec = r_reloc_get_section (r_rel); + if (sec == bfd_abs_section_ptr + || sec == bfd_com_section_ptr + || sec == bfd_und_section_ptr) + return FALSE; + return TRUE; +} + + +/* source_reloc: relocations that reference literal sections. */ + +/* To determine whether literals can be coalesced, we need to first + record all the relocations that reference the literals. The + source_reloc structure below is used for this purpose. The + source_reloc entries are kept in a per-literal-section array, sorted + by offset within the literal section (i.e., target offset). + + The source_sec and r_rel.rela.r_offset fields identify the source of + the relocation. The r_rel field records the relocation value, i.e., + the offset of the literal being referenced. The opnd field is needed + to determine the range of the immediate field to which the relocation + applies, so we can determine whether another literal with the same + value is within range. The is_null field is true when the relocation + is being removed (e.g., when an L32R is being removed due to a CALLX + that is converted to a direct CALL). */ + +typedef struct source_reloc_struct source_reloc; + +struct source_reloc_struct +{ + asection *source_sec; + r_reloc r_rel; + xtensa_operand opnd; + bfd_boolean is_null; +}; + + +static void init_source_reloc + PARAMS ((source_reloc *, asection *, const r_reloc *, xtensa_operand)); +static source_reloc *find_source_reloc + PARAMS ((source_reloc *, int, asection *, Elf_Internal_Rela *)); +static int source_reloc_compare + PARAMS ((const PTR, const PTR)); + + +static void +init_source_reloc (reloc, source_sec, r_rel, opnd) + source_reloc *reloc; + asection *source_sec; + const r_reloc *r_rel; + xtensa_operand opnd; +{ + reloc->source_sec = source_sec; + reloc->r_rel = *r_rel; + reloc->opnd = opnd; + reloc->is_null = FALSE; +} + + +/* Find the source_reloc for a particular source offset and relocation + type. Note that the array is sorted by _target_ offset, so this is + just a linear search. */ + +static source_reloc * +find_source_reloc (src_relocs, src_count, sec, irel) + source_reloc *src_relocs; + int src_count; + asection *sec; + Elf_Internal_Rela *irel; +{ + int i; + + for (i = 0; i < src_count; i++) + { + if (src_relocs[i].source_sec == sec + && src_relocs[i].r_rel.rela.r_offset == irel->r_offset + && (ELF32_R_TYPE (src_relocs[i].r_rel.rela.r_info) + == ELF32_R_TYPE (irel->r_info))) + return &src_relocs[i]; + } + + return NULL; +} + + +static int +source_reloc_compare (ap, bp) + const PTR ap; + const PTR bp; +{ + const source_reloc *a = (const source_reloc *) ap; + const source_reloc *b = (const source_reloc *) bp; + + return (a->r_rel.target_offset - b->r_rel.target_offset); +} + + +/* Literal values and value hash tables. */ + +/* Literals with the same value can be coalesced. The literal_value + structure records the value of a literal: the "r_rel" field holds the + information from the relocation on the literal (if there is one) and + the "value" field holds the contents of the literal word itself. + + The value_map structure records a literal value along with the + location of a literal holding that value. The value_map hash table + is indexed by the literal value, so that we can quickly check if a + particular literal value has been seen before and is thus a candidate + for coalescing. */ + +typedef struct literal_value_struct literal_value; +typedef struct value_map_struct value_map; +typedef struct value_map_hash_table_struct value_map_hash_table; + +struct literal_value_struct +{ + r_reloc r_rel; + unsigned long value; +}; + +struct value_map_struct +{ + literal_value val; /* The literal value. */ + r_reloc loc; /* Location of the literal. */ + value_map *next; +}; + +struct value_map_hash_table_struct +{ + unsigned bucket_count; + value_map **buckets; + unsigned count; +}; + + +static bfd_boolean is_same_value + PARAMS ((const literal_value *, const literal_value *)); +static value_map_hash_table *value_map_hash_table_init + PARAMS ((void)); +static unsigned hash_literal_value + PARAMS ((const literal_value *)); +static unsigned hash_bfd_vma + PARAMS ((bfd_vma)); +static value_map *get_cached_value + PARAMS ((value_map_hash_table *, const literal_value *)); +static value_map *add_value_map + PARAMS ((value_map_hash_table *, const literal_value *, const r_reloc *)); + + +static bfd_boolean +is_same_value (src1, src2) + const literal_value *src1; + const literal_value *src2; +{ + if (r_reloc_is_const (&src1->r_rel) != r_reloc_is_const (&src2->r_rel)) + return FALSE; + + if (r_reloc_is_const (&src1->r_rel)) + return (src1->value == src2->value); + + if (ELF32_R_TYPE (src1->r_rel.rela.r_info) + != ELF32_R_TYPE (src2->r_rel.rela.r_info)) + return FALSE; + + if (r_reloc_get_target_offset (&src1->r_rel) + != r_reloc_get_target_offset (&src2->r_rel)) + return FALSE; + + if (src1->value != src2->value) + return FALSE; + + /* Now check for the same section and the same elf_hash. */ + if (r_reloc_is_defined (&src1->r_rel)) + { + if (r_reloc_get_section (&src1->r_rel) + != r_reloc_get_section (&src2->r_rel)) + return FALSE; + } + else + { + if (r_reloc_get_hash_entry (&src1->r_rel) + != r_reloc_get_hash_entry (&src2->r_rel)) + return FALSE; + + if (r_reloc_get_hash_entry (&src1->r_rel) == 0) + return FALSE; + } + + return TRUE; +} + + +/* Must be power of 2. */ +#define INITIAL_HASH_RELOC_BUCKET_COUNT 1024 + +static value_map_hash_table * +value_map_hash_table_init () +{ + value_map_hash_table *values; + + values = (value_map_hash_table *) + bfd_malloc (sizeof (value_map_hash_table)); + + values->bucket_count = INITIAL_HASH_RELOC_BUCKET_COUNT; + values->count = 0; + values->buckets = (value_map **) + bfd_zmalloc (sizeof (value_map *) * values->bucket_count); + + return values; +} + + +static unsigned +hash_bfd_vma (val) + bfd_vma val; +{ + return (val >> 2) + (val >> 10); +} + + +static unsigned +hash_literal_value (src) + const literal_value *src; +{ + unsigned hash_val; + + if (r_reloc_is_const (&src->r_rel)) + return hash_bfd_vma (src->value); + + hash_val = (hash_bfd_vma (r_reloc_get_target_offset (&src->r_rel)) + + hash_bfd_vma (src->value)); + + /* Now check for the same section and the same elf_hash. */ + if (r_reloc_is_defined (&src->r_rel)) + hash_val += hash_bfd_vma ((bfd_vma) (unsigned) r_reloc_get_section (&src->r_rel)); + else + hash_val += hash_bfd_vma ((bfd_vma) (unsigned) r_reloc_get_hash_entry (&src->r_rel)); + + return hash_val; +} + + +/* Check if the specified literal_value has been seen before. */ + +static value_map * +get_cached_value (map, val) + value_map_hash_table *map; + const literal_value *val; +{ + value_map *map_e; + value_map *bucket; + unsigned idx; + + idx = hash_literal_value (val); + idx = idx & (map->bucket_count - 1); + bucket = map->buckets[idx]; + for (map_e = bucket; map_e; map_e = map_e->next) + { + if (is_same_value (&map_e->val, val)) + return map_e; + } + return NULL; +} + + +/* Record a new literal value. It is illegal to call this if VALUE + already has an entry here. */ + +static value_map * +add_value_map (map, val, loc) + value_map_hash_table *map; + const literal_value *val; + const r_reloc *loc; +{ + value_map **bucket_p; + unsigned idx; + + value_map *val_e = (value_map *) bfd_zmalloc (sizeof (value_map)); + + BFD_ASSERT (get_cached_value (map, val) == NULL); + val_e->val = *val; + val_e->loc = *loc; + + idx = hash_literal_value (val); + idx = idx & (map->bucket_count - 1); + bucket_p = &map->buckets[idx]; + + val_e->next = *bucket_p; + *bucket_p = val_e; + map->count++; + /* FIXME: consider resizing the hash table if we get too many entries */ + + return val_e; +} + + +/* Lists of literals being coalesced or removed. */ + +/* In the usual case, the literal identified by "from" is being + coalesced with another literal identified by "to". If the literal is + unused and is being removed altogether, "to.abfd" will be NULL. + The removed_literal entries are kept on a per-section list, sorted + by the "from" offset field. */ + +typedef struct removed_literal_struct removed_literal; +typedef struct removed_literal_list_struct removed_literal_list; + +struct removed_literal_struct +{ + r_reloc from; + r_reloc to; + removed_literal *next; +}; + +struct removed_literal_list_struct +{ + removed_literal *head; + removed_literal *tail; +}; + + +static void add_removed_literal + PARAMS ((removed_literal_list *, const r_reloc *, const r_reloc *)); +static removed_literal *find_removed_literal + PARAMS ((removed_literal_list *, bfd_vma)); +static bfd_vma offset_with_removed_literals + PARAMS ((removed_literal_list *, bfd_vma)); + + +/* Record that the literal at "from" is being removed. If "to" is not + NULL, the "from" literal is being coalesced with the "to" literal. */ + +static void +add_removed_literal (removed_list, from, to) + removed_literal_list *removed_list; + const r_reloc *from; + const r_reloc *to; +{ + removed_literal *r, *new_r, *next_r; + + new_r = (removed_literal *) bfd_zmalloc (sizeof (removed_literal)); + + new_r->from = *from; + if (to) + new_r->to = *to; + else + new_r->to.abfd = NULL; + new_r->next = NULL; + + r = removed_list->head; + if (r == NULL) + { + removed_list->head = new_r; + removed_list->tail = new_r; + } + /* Special check for common case of append. */ + else if (removed_list->tail->from.target_offset < from->target_offset) + { + removed_list->tail->next = new_r; + removed_list->tail = new_r; + } + else + { + while (r->from.target_offset < from->target_offset + && r->next != NULL) + { + r = r->next; + } + next_r = r->next; + r->next = new_r; + new_r->next = next_r; + if (next_r == NULL) + removed_list->tail = new_r; + } +} + + +/* Check if the list of removed literals contains an entry for the + given address. Return the entry if found. */ + +static removed_literal * +find_removed_literal (removed_list, addr) + removed_literal_list *removed_list; + bfd_vma addr; +{ + removed_literal *r = removed_list->head; + while (r && r->from.target_offset < addr) + r = r->next; + if (r && r->from.target_offset == addr) + return r; + return NULL; +} + + +/* Adjust an offset in a section to compensate for literals that are + being removed. Search the list of removed literals and subtract + 4 bytes for every removed literal prior to the given address. */ + +static bfd_vma +offset_with_removed_literals (removed_list, addr) + removed_literal_list *removed_list; + bfd_vma addr; +{ + removed_literal *r = removed_list->head; + unsigned num_bytes = 0; + + if (r == NULL) + return addr; + + while (r && r->from.target_offset <= addr) + { + num_bytes += 4; + r = r->next; + } + if (num_bytes > addr) + return 0; + return (addr - num_bytes); +} + + +/* Coalescing literals may require a relocation to refer to a section in + a different input file, but the standard relocation information + cannot express that. Instead, the reloc_bfd_fix structures are used + to "fix" the relocations that refer to sections in other input files. + These structures are kept on per-section lists. The "src_type" field + records the relocation type in case there are multiple relocations on + the same location. FIXME: This is ugly; an alternative might be to + add new symbols with the "owner" field to some other input file. */ + +typedef struct reloc_bfd_fix_struct reloc_bfd_fix; + +struct reloc_bfd_fix_struct +{ + asection *src_sec; + bfd_vma src_offset; + unsigned src_type; /* Relocation type. */ + + bfd *target_abfd; + asection *target_sec; + bfd_vma target_offset; + + reloc_bfd_fix *next; +}; + + +static reloc_bfd_fix *reloc_bfd_fix_init + PARAMS ((asection *, bfd_vma, unsigned, bfd *, asection *, bfd_vma)); +static reloc_bfd_fix *get_bfd_fix + PARAMS ((reloc_bfd_fix *, asection *, bfd_vma, unsigned)); + + +static reloc_bfd_fix * +reloc_bfd_fix_init (src_sec, src_offset, src_type, + target_abfd, target_sec, target_offset) + asection *src_sec; + bfd_vma src_offset; + unsigned src_type; + bfd *target_abfd; + asection *target_sec; + bfd_vma target_offset; +{ + reloc_bfd_fix *fix; + + fix = (reloc_bfd_fix *) bfd_malloc (sizeof (reloc_bfd_fix)); + fix->src_sec = src_sec; + fix->src_offset = src_offset; + fix->src_type = src_type; + fix->target_abfd = target_abfd; + fix->target_sec = target_sec; + fix->target_offset = target_offset; + + return fix; +} + + +static reloc_bfd_fix * +get_bfd_fix (fix_list, sec, offset, type) + reloc_bfd_fix *fix_list; + asection *sec; + bfd_vma offset; + unsigned type; +{ + reloc_bfd_fix *r; + + for (r = fix_list; r != NULL; r = r->next) + { + if (r->src_sec == sec + && r->src_offset == offset + && r->src_type == type) + return r; + } + return NULL; +} + + +/* Per-section data for relaxation. */ + +struct xtensa_relax_info_struct +{ + bfd_boolean is_relaxable_literal_section; + int visited; /* Number of times visited. */ + + source_reloc *src_relocs; /* Array[src_count]. */ + int src_count; + int src_next; /* Next src_relocs entry to assign. */ + + removed_literal_list removed_list; + + reloc_bfd_fix *fix_list; +}; + +struct elf_xtensa_section_data +{ + struct bfd_elf_section_data elf; + xtensa_relax_info relax_info; +}; + +static void init_xtensa_relax_info + PARAMS ((asection *)); +static xtensa_relax_info *get_xtensa_relax_info + PARAMS ((asection *)); +static void add_fix + PARAMS ((asection *, reloc_bfd_fix *)); + + +static bfd_boolean +elf_xtensa_new_section_hook (abfd, sec) + bfd *abfd; + asection *sec; +{ + struct elf_xtensa_section_data *sdata; + bfd_size_type amt = sizeof (*sdata); + + sdata = (struct elf_xtensa_section_data *) bfd_zalloc (abfd, amt); + if (sdata == NULL) + return FALSE; + sec->used_by_bfd = (PTR) sdata; + + return _bfd_elf_new_section_hook (abfd, sec); +} + + +static void +init_xtensa_relax_info (sec) + asection *sec; +{ + xtensa_relax_info *relax_info = get_xtensa_relax_info (sec); + + relax_info->is_relaxable_literal_section = FALSE; + relax_info->visited = 0; + + relax_info->src_relocs = NULL; + relax_info->src_count = 0; + relax_info->src_next = 0; + + relax_info->removed_list.head = NULL; + relax_info->removed_list.tail = NULL; + + relax_info->fix_list = NULL; +} + + +static xtensa_relax_info * +get_xtensa_relax_info (sec) + asection *sec; +{ + struct elf_xtensa_section_data *section_data; + + /* No info available if no section or if it is an output section. */ + if (!sec || sec == sec->output_section) + return NULL; + + section_data = (struct elf_xtensa_section_data *) elf_section_data (sec); + return §ion_data->relax_info; +} + + +static void +add_fix (src_sec, fix) + asection *src_sec; + reloc_bfd_fix *fix; +{ + xtensa_relax_info *relax_info; + + relax_info = get_xtensa_relax_info (src_sec); + fix->next = relax_info->fix_list; + relax_info->fix_list = fix; +} + + +/* Access to internal relocations, section contents and symbols. */ + +/* During relaxation, we need to modify relocations, section contents, + and symbol definitions, and we need to keep the original values from + being reloaded from the input files, i.e., we need to "pin" the + modified values in memory. We also want to continue to observe the + setting of the "keep-memory" flag. The following functions wrap the + standard BFD functions to take care of this for us. */ + +static Elf_Internal_Rela * +retrieve_internal_relocs (abfd, sec, keep_memory) + bfd *abfd; + asection *sec; + bfd_boolean keep_memory; +{ + Elf_Internal_Rela *internal_relocs; + + if ((sec->flags & SEC_LINKER_CREATED) != 0) + return NULL; + + internal_relocs = elf_section_data (sec)->relocs; + if (internal_relocs == NULL) + internal_relocs = (_bfd_elf_link_read_relocs + (abfd, sec, (PTR) NULL, (Elf_Internal_Rela *) NULL, + keep_memory)); + return internal_relocs; +} + + +static void +pin_internal_relocs (sec, internal_relocs) + asection *sec; + Elf_Internal_Rela *internal_relocs; +{ + elf_section_data (sec)->relocs = internal_relocs; +} + + +static void +release_internal_relocs (sec, internal_relocs) + asection *sec; + Elf_Internal_Rela *internal_relocs; +{ + if (internal_relocs + && elf_section_data (sec)->relocs != internal_relocs) + free (internal_relocs); +} + + +static bfd_byte * +retrieve_contents (abfd, sec, keep_memory) + bfd *abfd; + asection *sec; + bfd_boolean keep_memory; +{ + bfd_byte *contents; + + contents = elf_section_data (sec)->this_hdr.contents; + + if (contents == NULL && sec->_raw_size != 0) + { + contents = (bfd_byte *) bfd_malloc (sec->_raw_size); + if (contents != NULL) + { + if (! bfd_get_section_contents (abfd, sec, contents, + (file_ptr) 0, sec->_raw_size)) + { + free (contents); + return NULL; + } + if (keep_memory) + elf_section_data (sec)->this_hdr.contents = contents; + } + } + return contents; +} + + +static void +pin_contents (sec, contents) + asection *sec; + bfd_byte *contents; +{ + elf_section_data (sec)->this_hdr.contents = contents; +} + + +static void +release_contents (sec, contents) + asection *sec; + bfd_byte *contents; +{ + if (contents && + elf_section_data (sec)->this_hdr.contents != contents) + free (contents); +} + + +static Elf_Internal_Sym * +retrieve_local_syms (input_bfd) + bfd *input_bfd; +{ + Elf_Internal_Shdr *symtab_hdr; + Elf_Internal_Sym *isymbuf; + size_t locsymcount; + + symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr; + locsymcount = symtab_hdr->sh_info; + + isymbuf = (Elf_Internal_Sym *) symtab_hdr->contents; + if (isymbuf == NULL && locsymcount != 0) + isymbuf = bfd_elf_get_elf_syms (input_bfd, symtab_hdr, locsymcount, 0, + NULL, NULL, NULL); + + /* Save the symbols for this input file so they won't be read again. */ + if (isymbuf && isymbuf != (Elf_Internal_Sym *) symtab_hdr->contents) + symtab_hdr->contents = (unsigned char *) isymbuf; + + return isymbuf; +} + + +/* Code for link-time relaxation. */ + +/* Local helper functions. */ +static bfd_boolean analyze_relocations + PARAMS ((struct bfd_link_info *)); +static bfd_boolean find_relaxable_sections + PARAMS ((bfd *, asection *, struct bfd_link_info *, bfd_boolean *)); +static bfd_boolean collect_source_relocs + PARAMS ((bfd *, asection *, struct bfd_link_info *)); +static bfd_boolean is_resolvable_asm_expansion + PARAMS ((bfd *, asection *, bfd_byte *, Elf_Internal_Rela *, + struct bfd_link_info *, bfd_boolean *)); +static bfd_boolean remove_literals + PARAMS ((bfd *, asection *, struct bfd_link_info *, value_map_hash_table *)); +static bfd_boolean relax_section + PARAMS ((bfd *, asection *, struct bfd_link_info *)); +static bfd_boolean relax_property_section + PARAMS ((bfd *, asection *, struct bfd_link_info *)); +static bfd_boolean relax_section_symbols + PARAMS ((bfd *, asection *)); +static bfd_boolean relocations_reach + PARAMS ((source_reloc *, int, const r_reloc *)); +static void translate_reloc + PARAMS ((const r_reloc *, r_reloc *)); +static Elf_Internal_Rela *get_irel_at_offset + PARAMS ((asection *, Elf_Internal_Rela *, bfd_vma)); +static Elf_Internal_Rela *find_associated_l32r_irel + PARAMS ((asection *, bfd_byte *, Elf_Internal_Rela *, + Elf_Internal_Rela *)); +static void shrink_dynamic_reloc_sections + PARAMS ((struct bfd_link_info *, bfd *, asection *, Elf_Internal_Rela *)); + + +static bfd_boolean +elf_xtensa_relax_section (abfd, sec, link_info, again) + bfd *abfd; + asection *sec; + struct bfd_link_info *link_info; + bfd_boolean *again; +{ + static value_map_hash_table *values = NULL; + xtensa_relax_info *relax_info; + + if (!values) + { + /* Do some overall initialization for relaxation. */ + values = value_map_hash_table_init (); + relaxing_section = TRUE; + if (!analyze_relocations (link_info)) + return FALSE; + } + *again = FALSE; + + /* Don't mess with linker-created sections. */ + if ((sec->flags & SEC_LINKER_CREATED) != 0) + return TRUE; + + relax_info = get_xtensa_relax_info (sec); + BFD_ASSERT (relax_info != NULL); + + switch (relax_info->visited) + { + case 0: + /* Note: It would be nice to fold this pass into + analyze_relocations, but it is important for this step that the + sections be examined in link order. */ + if (!remove_literals (abfd, sec, link_info, values)) + return FALSE; + *again = TRUE; + break; + + case 1: + if (!relax_section (abfd, sec, link_info)) + return FALSE; + *again = TRUE; + break; + + case 2: + if (!relax_section_symbols (abfd, sec)) + return FALSE; + break; + } + + relax_info->visited++; + return TRUE; +} + +/* Initialization for relaxation. */ + +/* This function is called once at the start of relaxation. It scans + all the input sections and marks the ones that are relaxable (i.e., + literal sections with L32R relocations against them). It then + collect source_reloc information for all the relocations against + those relaxable sections. */ + +static bfd_boolean +analyze_relocations (link_info) + struct bfd_link_info *link_info; +{ + bfd *abfd; + asection *sec; + bfd_boolean is_relaxable = FALSE; + + /* Initialize the per-section relaxation info. */ + for (abfd = link_info->input_bfds; abfd != NULL; abfd = abfd->link_next) + for (sec = abfd->sections; sec != NULL; sec = sec->next) + { + init_xtensa_relax_info (sec); + } + + /* Mark relaxable sections (and count relocations against each one). */ + for (abfd = link_info->input_bfds; abfd != NULL; abfd = abfd->link_next) + for (sec = abfd->sections; sec != NULL; sec = sec->next) + { + if (!find_relaxable_sections (abfd, sec, link_info, &is_relaxable)) + return FALSE; + } + + /* Bail out if there are no relaxable sections. */ + if (!is_relaxable) + return TRUE; + + /* Allocate space for source_relocs. */ + for (abfd = link_info->input_bfds; abfd != NULL; abfd = abfd->link_next) + for (sec = abfd->sections; sec != NULL; sec = sec->next) + { + xtensa_relax_info *relax_info; + + relax_info = get_xtensa_relax_info (sec); + if (relax_info->is_relaxable_literal_section) + { + relax_info->src_relocs = (source_reloc *) + bfd_malloc (relax_info->src_count * sizeof (source_reloc)); + } + } + + /* Collect info on relocations against each relaxable section. */ + for (abfd = link_info->input_bfds; abfd != NULL; abfd = abfd->link_next) + for (sec = abfd->sections; sec != NULL; sec = sec->next) + { + if (!collect_source_relocs (abfd, sec, link_info)) + return FALSE; + } + + return TRUE; +} + + +/* Find all the literal sections that might be relaxed. The motivation + for this pass is that collect_source_relocs() needs to record _all_ + the relocations that target each relaxable section. That is + expensive and unnecessary unless the target section is actually going + to be relaxed. This pass identifies all such sections by checking if + they have L32Rs pointing to them. In the process, the total number + of relocations targeting each section is also counted so that we + know how much space to allocate for source_relocs against each + relaxable literal section. */ + +static bfd_boolean +find_relaxable_sections (abfd, sec, link_info, is_relaxable_p) + bfd *abfd; + asection *sec; + struct bfd_link_info *link_info; + bfd_boolean *is_relaxable_p; +{ + Elf_Internal_Rela *internal_relocs; + bfd_byte *contents; + bfd_boolean ok = TRUE; + unsigned i; + + internal_relocs = retrieve_internal_relocs (abfd, sec, + link_info->keep_memory); + if (internal_relocs == NULL) + return ok; + + contents = retrieve_contents (abfd, sec, link_info->keep_memory); + if (contents == NULL && sec->_raw_size != 0) + { + ok = FALSE; + goto error_return; + } + + for (i = 0; i < sec->reloc_count; i++) + { + Elf_Internal_Rela *irel = &internal_relocs[i]; + r_reloc r_rel; + asection *target_sec; + xtensa_relax_info *target_relax_info; + + r_reloc_init (&r_rel, abfd, irel); + + target_sec = r_reloc_get_section (&r_rel); + target_relax_info = get_xtensa_relax_info (target_sec); + if (!target_relax_info) + continue; + + /* Count relocations against the target section. */ + target_relax_info->src_count++; + + if (is_literal_section (target_sec) + && is_l32r_relocation (sec, contents, irel) + && r_reloc_is_defined (&r_rel)) + { + /* Mark the target section as relaxable. */ + target_relax_info->is_relaxable_literal_section = TRUE; + *is_relaxable_p = TRUE; + } + } + + error_return: + release_contents (sec, contents); + release_internal_relocs (sec, internal_relocs); + return ok; +} + + +/* Record _all_ the relocations that point to relaxable literal + sections, and get rid of ASM_EXPAND relocs by either converting them + to ASM_SIMPLIFY or by removing them. */ + +static bfd_boolean +collect_source_relocs (abfd, sec, link_info) + bfd *abfd; + asection *sec; + struct bfd_link_info *link_info; +{ + Elf_Internal_Rela *internal_relocs; + bfd_byte *contents; + bfd_boolean ok = TRUE; + unsigned i; + + internal_relocs = retrieve_internal_relocs (abfd, sec, + link_info->keep_memory); + if (internal_relocs == NULL) + return ok; + + contents = retrieve_contents (abfd, sec, link_info->keep_memory); + if (contents == NULL && sec->_raw_size != 0) + { + ok = FALSE; + goto error_return; + } + + /* Record relocations against relaxable literal sections. */ + for (i = 0; i < sec->reloc_count; i++) + { + Elf_Internal_Rela *irel = &internal_relocs[i]; + r_reloc r_rel; + asection *target_sec; + xtensa_relax_info *target_relax_info; + + r_reloc_init (&r_rel, abfd, irel); + + target_sec = r_reloc_get_section (&r_rel); + target_relax_info = get_xtensa_relax_info (target_sec); + + if (target_relax_info + && target_relax_info->is_relaxable_literal_section) + { + xtensa_opcode opcode; + xtensa_operand opnd; + source_reloc *s_reloc; + int src_next; + + src_next = target_relax_info->src_next++; + s_reloc = &target_relax_info->src_relocs[src_next]; + + opcode = get_relocation_opcode (sec, contents, irel); + if (opcode == XTENSA_UNDEFINED) + opnd = NULL; + else + opnd = xtensa_get_operand (xtensa_default_isa, opcode, + get_relocation_opnd (irel)); + + init_source_reloc (s_reloc, sec, &r_rel, opnd); + } + } + + /* Now get rid of ASM_EXPAND relocations. At this point, the + src_relocs array for the target literal section may still be + incomplete, but it must at least contain the entries for the L32R + relocations associated with ASM_EXPANDs because they were just + added in the preceding loop over the relocations. */ + + for (i = 0; i < sec->reloc_count; i++) + { + Elf_Internal_Rela *irel = &internal_relocs[i]; + bfd_boolean is_reachable; + + if (!is_resolvable_asm_expansion (abfd, sec, contents, irel, link_info, + &is_reachable)) + continue; + + if (is_reachable) + { + Elf_Internal_Rela *l32r_irel; + r_reloc r_rel; + asection *target_sec; + xtensa_relax_info *target_relax_info; + + /* Mark the source_reloc for the L32R so that it will be + removed in remove_literals(), along with the associated + literal. */ + l32r_irel = find_associated_l32r_irel (sec, contents, + irel, internal_relocs); + if (l32r_irel == NULL) + continue; + + r_reloc_init (&r_rel, abfd, l32r_irel); + + target_sec = r_reloc_get_section (&r_rel); + target_relax_info = get_xtensa_relax_info (target_sec); + + if (target_relax_info + && target_relax_info->is_relaxable_literal_section) + { + source_reloc *s_reloc; + + /* Search the source_relocs for the entry corresponding to + the l32r_irel. Note: The src_relocs array is not yet + sorted, but it wouldn't matter anyway because we're + searching by source offset instead of target offset. */ + s_reloc = find_source_reloc (target_relax_info->src_relocs, + target_relax_info->src_next, + sec, l32r_irel); + BFD_ASSERT (s_reloc); + s_reloc->is_null = TRUE; + } + + /* Convert this reloc to ASM_SIMPLIFY. */ + irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info), + R_XTENSA_ASM_SIMPLIFY); + l32r_irel->r_info = ELF32_R_INFO (0, R_XTENSA_NONE); + + pin_internal_relocs (sec, internal_relocs); + } + else + { + /* It is resolvable but doesn't reach. We resolve now + by eliminating the relocation -- the call will remain + expanded into L32R/CALLX. */ + irel->r_info = ELF32_R_INFO (0, R_XTENSA_NONE); + pin_internal_relocs (sec, internal_relocs); + } + } + + error_return: + release_contents (sec, contents); + release_internal_relocs (sec, internal_relocs); + return ok; +} + + +/* Return TRUE if the asm expansion can be resolved. Generally it can + be resolved on a final link or when a partial link locates it in the + same section as the target. Set "is_reachable" flag if the target of + the call is within the range of a direct call, given the current VMA + for this section and the target section. */ + +bfd_boolean +is_resolvable_asm_expansion (abfd, sec, contents, irel, link_info, + is_reachable_p) + bfd *abfd; + asection *sec; + bfd_byte *contents; + Elf_Internal_Rela *irel; + struct bfd_link_info *link_info; + bfd_boolean *is_reachable_p; +{ + asection *target_sec; + bfd_vma target_offset; + r_reloc r_rel; + xtensa_opcode opcode, direct_call_opcode; + bfd_vma self_address; + bfd_vma dest_address; + + *is_reachable_p = FALSE; + + if (contents == NULL) + return FALSE; + + if (ELF32_R_TYPE (irel->r_info) != R_XTENSA_ASM_EXPAND) + return FALSE; + + opcode = get_expanded_call_opcode (contents + irel->r_offset, + sec->_raw_size - irel->r_offset); + + direct_call_opcode = swap_callx_for_call_opcode (opcode); + if (direct_call_opcode == XTENSA_UNDEFINED) + return FALSE; + + /* Check and see that the target resolves. */ + r_reloc_init (&r_rel, abfd, irel); + if (!r_reloc_is_defined (&r_rel)) + return FALSE; + + target_sec = r_reloc_get_section (&r_rel); + target_offset = r_reloc_get_target_offset (&r_rel); + + /* If the target is in a shared library, then it doesn't reach. This + isn't supposed to come up because the compiler should never generate + non-PIC calls on systems that use shared libraries, but the linker + shouldn't crash regardless. */ + if (!target_sec->output_section) + return FALSE; + + /* For relocatable sections, we can only simplify when the output + section of the target is the same as the output section of the + source. */ + if (link_info->relocatable + && (target_sec->output_section != sec->output_section)) + return FALSE; + + self_address = (sec->output_section->vma + + sec->output_offset + irel->r_offset + 3); + dest_address = (target_sec->output_section->vma + + target_sec->output_offset + target_offset); + + *is_reachable_p = pcrel_reloc_fits + (xtensa_get_operand (xtensa_default_isa, direct_call_opcode, 0), + self_address, dest_address); + + if ((self_address >> CALL_SEGMENT_BITS) != + (dest_address >> CALL_SEGMENT_BITS)) + return FALSE; + + return TRUE; +} + + +static Elf_Internal_Rela * +find_associated_l32r_irel (sec, contents, other_irel, internal_relocs) + asection *sec; + bfd_byte *contents; + Elf_Internal_Rela *other_irel; + Elf_Internal_Rela *internal_relocs; +{ + unsigned i; + + for (i = 0; i < sec->reloc_count; i++) + { + Elf_Internal_Rela *irel = &internal_relocs[i]; + + if (irel == other_irel) + continue; + if (irel->r_offset != other_irel->r_offset) + continue; + if (is_l32r_relocation (sec, contents, irel)) + return irel; + } + + return NULL; +} + +/* First relaxation pass. */ + +/* If the section is relaxable (i.e., a literal section), check each + literal to see if it has the same value as another literal that has + already been seen, either in the current section or a previous one. + If so, add an entry to the per-section list of removed literals. The + actual changes are deferred until the next pass. */ + +static bfd_boolean +remove_literals (abfd, sec, link_info, values) + bfd *abfd; + asection *sec; + struct bfd_link_info *link_info; + value_map_hash_table *values; +{ + xtensa_relax_info *relax_info; + bfd_byte *contents; + Elf_Internal_Rela *internal_relocs; + source_reloc *src_relocs; + bfd_boolean ok = TRUE; + int i; + + /* Do nothing if it is not a relaxable literal section. */ + relax_info = get_xtensa_relax_info (sec); + BFD_ASSERT (relax_info); + + if (!relax_info->is_relaxable_literal_section) + return ok; + + internal_relocs = retrieve_internal_relocs (abfd, sec, + link_info->keep_memory); + + contents = retrieve_contents (abfd, sec, link_info->keep_memory); + if (contents == NULL && sec->_raw_size != 0) + { + ok = FALSE; + goto error_return; + } + + /* Sort the source_relocs by target offset. */ + src_relocs = relax_info->src_relocs; + qsort (src_relocs, relax_info->src_count, + sizeof (source_reloc), source_reloc_compare); + + for (i = 0; i < relax_info->src_count; i++) + { + source_reloc *rel; + Elf_Internal_Rela *irel = NULL; + literal_value val; + value_map *val_map; + + rel = &src_relocs[i]; + irel = get_irel_at_offset (sec, internal_relocs, + rel->r_rel.target_offset); + + /* If the target_offset for this relocation is the same as the + previous relocation, then we've already considered whether the + literal can be coalesced. Skip to the next one.... */ + if (i != 0 && (src_relocs[i-1].r_rel.target_offset + == rel->r_rel.target_offset)) + continue; + + /* Check if the relocation was from an L32R that is being removed + because a CALLX was converted to a direct CALL, and check if + there are no other relocations to the literal. */ + if (rel->is_null + && (i == relax_info->src_count - 1 + || (src_relocs[i+1].r_rel.target_offset + != rel->r_rel.target_offset))) + { + /* Mark the unused literal so that it will be removed. */ + add_removed_literal (&relax_info->removed_list, &rel->r_rel, NULL); + + /* Zero out the relocation on this literal location. */ + if (irel) + { + if (elf_hash_table (link_info)->dynamic_sections_created) + shrink_dynamic_reloc_sections (link_info, abfd, sec, irel); + + irel->r_info = ELF32_R_INFO (0, R_XTENSA_NONE); + } + + continue; + } + + /* Find the literal value. */ + r_reloc_init (&val.r_rel, abfd, irel); + BFD_ASSERT (rel->r_rel.target_offset < sec->_raw_size); + val.value = bfd_get_32 (abfd, contents + rel->r_rel.target_offset); + + /* Check if we've seen another literal with the same value. */ + val_map = get_cached_value (values, &val); + if (val_map != NULL) + { + /* First check that THIS and all the other relocs to this + literal will FIT if we move them to the new address. */ + + if (relocations_reach (rel, relax_info->src_count - i, + &val_map->loc)) + { + /* Mark that the literal will be coalesced. */ + add_removed_literal (&relax_info->removed_list, + &rel->r_rel, &val_map->loc); + } + else + { + /* Relocations do not reach -- do not remove this literal. */ + val_map->loc = rel->r_rel; + } + } + else + { + /* This is the first time we've seen this literal value. */ + BFD_ASSERT (sec == r_reloc_get_section (&rel->r_rel)); + add_value_map (values, &val, &rel->r_rel); + } + } + +error_return: + release_contents (sec, contents); + release_internal_relocs (sec, internal_relocs); + return ok; +} + + +/* Check if the original relocations (presumably on L32R instructions) + identified by reloc[0..N] can be changed to reference the literal + identified by r_rel. If r_rel is out of range for any of the + original relocations, then we don't want to coalesce the original + literal with the one at r_rel. We only check reloc[0..N], where the + offsets are all the same as for reloc[0] (i.e., they're all + referencing the same literal) and where N is also bounded by the + number of remaining entries in the "reloc" array. The "reloc" array + is sorted by target offset so we know all the entries for the same + literal will be contiguous. */ + +static bfd_boolean +relocations_reach (reloc, remaining_relocs, r_rel) + source_reloc *reloc; + int remaining_relocs; + const r_reloc *r_rel; +{ + bfd_vma from_offset, source_address, dest_address; + asection *sec; + int i; + + if (!r_reloc_is_defined (r_rel)) + return FALSE; + + sec = r_reloc_get_section (r_rel); + from_offset = reloc[0].r_rel.target_offset; + + for (i = 0; i < remaining_relocs; i++) + { + if (reloc[i].r_rel.target_offset != from_offset) + break; + + /* Ignore relocations that have been removed. */ + if (reloc[i].is_null) + continue; + + /* The original and new output section for these must be the same + in order to coalesce. */ + if (r_reloc_get_section (&reloc[i].r_rel)->output_section + != sec->output_section) + return FALSE; + + /* A NULL operand means it is not a PC-relative relocation, so + the literal can be moved anywhere. */ + if (reloc[i].opnd) + { + /* Otherwise, check to see that it fits. */ + source_address = (reloc[i].source_sec->output_section->vma + + reloc[i].source_sec->output_offset + + reloc[i].r_rel.rela.r_offset); + dest_address = (sec->output_section->vma + + sec->output_offset + + r_rel->target_offset); + + if (!pcrel_reloc_fits (reloc[i].opnd, source_address, dest_address)) + return FALSE; + } + } + + return TRUE; +} + + +/* WARNING: linear search here. If the relocation are in order by + address, we can use a faster binary search. ALSO, we assume that + there is only 1 non-NONE relocation per address. */ + +static Elf_Internal_Rela * +get_irel_at_offset (sec, internal_relocs, offset) + asection *sec; + Elf_Internal_Rela *internal_relocs; + bfd_vma offset; +{ + unsigned i; + if (!internal_relocs) + return NULL; + for (i = 0; i < sec->reloc_count; i++) + { + Elf_Internal_Rela *irel = &internal_relocs[i]; + if (irel->r_offset == offset + && ELF32_R_TYPE (irel->r_info) != R_XTENSA_NONE) + return irel; + } + return NULL; +} + + +/* Second relaxation pass. */ + +/* Modify all of the relocations to point to the right spot, and if this + is a relaxable section, delete the unwanted literals and fix the + cooked_size. */ + +bfd_boolean +relax_section (abfd, sec, link_info) + bfd *abfd; + asection *sec; + struct bfd_link_info *link_info; +{ + Elf_Internal_Rela *internal_relocs; + xtensa_relax_info *relax_info; + bfd_byte *contents; + bfd_boolean ok = TRUE; + unsigned i; + + relax_info = get_xtensa_relax_info (sec); + BFD_ASSERT (relax_info); + + /* Handle property sections (e.g., literal tables) specially. */ + if (xtensa_is_property_section (sec)) + { + BFD_ASSERT (!relax_info->is_relaxable_literal_section); + return relax_property_section (abfd, sec, link_info); + } + + internal_relocs = retrieve_internal_relocs (abfd, sec, + link_info->keep_memory); + contents = retrieve_contents (abfd, sec, link_info->keep_memory); + if (contents == NULL && sec->_raw_size != 0) + { + ok = FALSE; + goto error_return; + } + + if (internal_relocs) + { + for (i = 0; i < sec->reloc_count; i++) + { + Elf_Internal_Rela *irel; + xtensa_relax_info *target_relax_info; + bfd_vma source_offset; + r_reloc r_rel; + unsigned r_type; + asection *target_sec; + + /* Locally change the source address. + Translate the target to the new target address. + If it points to this section and has been removed, + NULLify it. + Write it back. */ + + irel = &internal_relocs[i]; + source_offset = irel->r_offset; + + r_type = ELF32_R_TYPE (irel->r_info); + r_reloc_init (&r_rel, abfd, irel); + + if (relax_info->is_relaxable_literal_section) + { + if (r_type != R_XTENSA_NONE + && find_removed_literal (&relax_info->removed_list, + irel->r_offset)) + { + /* Remove this relocation. */ + if (elf_hash_table (link_info)->dynamic_sections_created) + shrink_dynamic_reloc_sections (link_info, abfd, sec, irel); + irel->r_info = ELF32_R_INFO (0, R_XTENSA_NONE); + irel->r_offset = offset_with_removed_literals + (&relax_info->removed_list, irel->r_offset); + continue; + } + source_offset = + offset_with_removed_literals (&relax_info->removed_list, + irel->r_offset); + irel->r_offset = source_offset; + } + + target_sec = r_reloc_get_section (&r_rel); + target_relax_info = get_xtensa_relax_info (target_sec); + + if (target_relax_info + && target_relax_info->is_relaxable_literal_section) + { + r_reloc new_rel; + reloc_bfd_fix *fix; + + translate_reloc (&r_rel, &new_rel); + + /* FIXME: If the relocation still references a section in + the same input file, the relocation should be modified + directly instead of adding a "fix" record. */ + + fix = reloc_bfd_fix_init (sec, source_offset, r_type, 0, + r_reloc_get_section (&new_rel), + new_rel.target_offset); + add_fix (sec, fix); + } + + pin_internal_relocs (sec, internal_relocs); + } + } + + if (relax_info->is_relaxable_literal_section) + { + /* Walk through the contents and delete literals that are not needed + anymore. */ + + unsigned long size = sec->_cooked_size; + unsigned long removed = 0; + + removed_literal *reloc = relax_info->removed_list.head; + for (; reloc; reloc = reloc->next) + { + unsigned long upper = sec->_raw_size; + bfd_vma start = reloc->from.target_offset + 4; + if (reloc->next) + upper = reloc->next->from.target_offset; + if (upper - start != 0) + { + BFD_ASSERT (start <= upper); + memmove (contents + start - removed - 4, + contents + start, + upper - start ); + pin_contents (sec, contents); + } + removed += 4; + size -= 4; + } + + /* Change the section size. */ + sec->_cooked_size = size; + /* Also shrink _raw_size. (The code in relocate_section that + checks that relocations are within the section must use + _raw_size because of the way the stabs sections are relaxed; + shrinking _raw_size means that these checks will not be + unnecessarily lax.) */ + sec->_raw_size = size; + } + + error_return: + release_internal_relocs (sec, internal_relocs); + release_contents (sec, contents); + return ok; +} + + +/* Fix up a relocation to take account of removed literals. */ + +static void +translate_reloc (orig_rel, new_rel) + const r_reloc *orig_rel; + r_reloc *new_rel; +{ + asection *sec; + xtensa_relax_info *relax_info; + removed_literal *removed; + unsigned long new_offset; + + *new_rel = *orig_rel; + + if (!r_reloc_is_defined (orig_rel)) + return; + sec = r_reloc_get_section (orig_rel); + + relax_info = get_xtensa_relax_info (sec); + BFD_ASSERT (relax_info); + + if (!relax_info->is_relaxable_literal_section) + return; + + /* Check if the original relocation is against a literal being removed. */ + removed = find_removed_literal (&relax_info->removed_list, + orig_rel->target_offset); + if (removed) + { + asection *new_sec; + + /* The fact that there is still a relocation to this literal indicates + that the literal is being coalesced, not simply removed. */ + BFD_ASSERT (removed->to.abfd != NULL); + + /* This was moved to some other address (possibly in another section). */ + *new_rel = removed->to; + new_sec = r_reloc_get_section (new_rel); + if (new_sec != sec) + { + sec = new_sec; + relax_info = get_xtensa_relax_info (sec); + if (!relax_info || !relax_info->is_relaxable_literal_section) + return; + } + } + + /* ...and the target address may have been moved within its section. */ + new_offset = offset_with_removed_literals (&relax_info->removed_list, + new_rel->target_offset); + + /* Modify the offset and addend. */ + new_rel->target_offset = new_offset; + new_rel->rela.r_addend += (new_offset - new_rel->target_offset); +} + + +/* For dynamic links, there may be a dynamic relocation for each + literal. The number of dynamic relocations must be computed in + size_dynamic_sections, which occurs before relaxation. When a + literal is removed, this function checks if there is a corresponding + dynamic relocation and shrinks the size of the appropriate dynamic + relocation section accordingly. At this point, the contents of the + dynamic relocation sections have not yet been filled in, so there's + nothing else that needs to be done. */ + +static void +shrink_dynamic_reloc_sections (info, abfd, input_section, rel) + struct bfd_link_info *info; + bfd *abfd; + asection *input_section; + Elf_Internal_Rela *rel; +{ + Elf_Internal_Shdr *symtab_hdr; + struct elf_link_hash_entry **sym_hashes; + unsigned long r_symndx; + int r_type; + struct elf_link_hash_entry *h; + bfd_boolean dynamic_symbol; + + symtab_hdr = &elf_tdata (abfd)->symtab_hdr; + sym_hashes = elf_sym_hashes (abfd); + + r_type = ELF32_R_TYPE (rel->r_info); + r_symndx = ELF32_R_SYM (rel->r_info); + + if (r_symndx < symtab_hdr->sh_info) + h = NULL; + else + h = sym_hashes[r_symndx - symtab_hdr->sh_info]; + + dynamic_symbol = xtensa_elf_dynamic_symbol_p (h, info); + + if ((r_type == R_XTENSA_32 || r_type == R_XTENSA_PLT) + && (input_section->flags & SEC_ALLOC) != 0 + && (dynamic_symbol || info->shared)) + { + bfd *dynobj; + const char *srel_name; + asection *srel; + bfd_boolean is_plt = FALSE; + + dynobj = elf_hash_table (info)->dynobj; + BFD_ASSERT (dynobj != NULL); + + if (dynamic_symbol && r_type == R_XTENSA_PLT) + { + srel_name = ".rela.plt"; + is_plt = TRUE; + } + else + srel_name = ".rela.got"; + + /* Reduce size of the .rela.* section by one reloc. */ + srel = bfd_get_section_by_name (dynobj, srel_name); + BFD_ASSERT (srel != NULL); + BFD_ASSERT (srel->_cooked_size >= sizeof (Elf32_External_Rela)); + srel->_cooked_size -= sizeof (Elf32_External_Rela); + + /* Also shrink _raw_size. (This seems wrong but other bfd code seems + to assume that linker-created sections will never be relaxed and + hence _raw_size must always equal _cooked_size.) */ + srel->_raw_size = srel->_cooked_size; + + if (is_plt) + { + asection *splt, *sgotplt, *srelgot; + int reloc_index, chunk; + + /* Find the PLT reloc index of the entry being removed. This + is computed from the size of ".rela.plt". It is needed to + figure out which PLT chunk to resize. Usually "last index + = size - 1" since the index starts at zero, but in this + context, the size has just been decremented so there's no + need to subtract one. */ + reloc_index = srel->_cooked_size / sizeof (Elf32_External_Rela); + + chunk = reloc_index / PLT_ENTRIES_PER_CHUNK; + splt = elf_xtensa_get_plt_section (dynobj, chunk); + sgotplt = elf_xtensa_get_gotplt_section (dynobj, chunk); + BFD_ASSERT (splt != NULL && sgotplt != NULL); + + /* Check if an entire PLT chunk has just been eliminated. */ + if (reloc_index % PLT_ENTRIES_PER_CHUNK == 0) + { + /* The two magic GOT entries for that chunk can go away. */ + srelgot = bfd_get_section_by_name (dynobj, ".rela.got"); + BFD_ASSERT (srelgot != NULL); + srelgot->reloc_count -= 2; + srelgot->_cooked_size -= 2 * sizeof (Elf32_External_Rela); + /* Shrink _raw_size (see comment above). */ + srelgot->_raw_size = srelgot->_cooked_size; + + sgotplt->_cooked_size -= 8; + + /* There should be only one entry left (and it will be + removed below). */ + BFD_ASSERT (sgotplt->_cooked_size == 4); + BFD_ASSERT (splt->_cooked_size == PLT_ENTRY_SIZE); + } + + BFD_ASSERT (sgotplt->_cooked_size >= 4); + BFD_ASSERT (splt->_cooked_size >= PLT_ENTRY_SIZE); + + sgotplt->_cooked_size -= 4; + splt->_cooked_size -= PLT_ENTRY_SIZE; + + /* Shrink _raw_sizes (see comment above). */ + sgotplt->_raw_size = sgotplt->_cooked_size; + splt->_raw_size = splt->_cooked_size; + } + } +} + + +/* This is similar to relax_section except that when a target is moved, + we shift addresses up. We also need to modify the size. This + algorithm does NOT allow for relocations into the middle of the + property sections. */ + +static bfd_boolean +relax_property_section (abfd, sec, link_info) + bfd *abfd; + asection *sec; + struct bfd_link_info *link_info; +{ + Elf_Internal_Rela *internal_relocs; + bfd_byte *contents; + unsigned i, nexti; + bfd_boolean ok = TRUE; + + internal_relocs = retrieve_internal_relocs (abfd, sec, + link_info->keep_memory); + contents = retrieve_contents (abfd, sec, link_info->keep_memory); + if (contents == NULL && sec->_raw_size != 0) + { + ok = FALSE; + goto error_return; + } + + if (internal_relocs) + { + for (i = 0; i < sec->reloc_count; i++) + { + Elf_Internal_Rela *irel; + xtensa_relax_info *target_relax_info; + r_reloc r_rel; + unsigned r_type; + asection *target_sec; + + /* Locally change the source address. + Translate the target to the new target address. + If it points to this section and has been removed, MOVE IT. + Also, don't forget to modify the associated SIZE at + (offset + 4). */ + + irel = &internal_relocs[i]; + r_type = ELF32_R_TYPE (irel->r_info); + if (r_type == R_XTENSA_NONE) + continue; + + r_reloc_init (&r_rel, abfd, irel); + + target_sec = r_reloc_get_section (&r_rel); + target_relax_info = get_xtensa_relax_info (target_sec); + + if (target_relax_info + && target_relax_info->is_relaxable_literal_section) + { + /* Translate the relocation's destination. */ + bfd_vma new_offset; + bfd_vma new_end_offset; + bfd_byte *size_p; + long old_size, new_size; + + new_offset = + offset_with_removed_literals (&target_relax_info->removed_list, + r_rel.target_offset); + + /* Assert that we are not out of bounds. */ + size_p = &contents[irel->r_offset + 4]; + old_size = bfd_get_32 (abfd, &contents[irel->r_offset + 4]); + + new_end_offset = + offset_with_removed_literals (&target_relax_info->removed_list, + r_rel.target_offset + old_size); + + new_size = new_end_offset - new_offset; + if (new_size != old_size) + { + bfd_put_32 (abfd, new_size, size_p); + pin_contents (sec, contents); + } + + if (new_offset != r_rel.target_offset) + { + bfd_vma diff = new_offset - r_rel.target_offset; + irel->r_addend += diff; + pin_internal_relocs (sec, internal_relocs); + } + } + } + } + + /* Combine adjacent property table entries. This is also done in + finish_dynamic_sections() but at that point it's too late to + reclaim the space in the output section, so we do this twice. */ + + if (internal_relocs) + { + Elf_Internal_Rela *last_irel = NULL; + int removed_bytes = 0; + bfd_vma offset, last_irel_offset; + bfd_vma section_size; + + /* Walk over memory and irels at the same time. + This REQUIRES that the internal_relocs be sorted by offset. */ + qsort (internal_relocs, sec->reloc_count, sizeof (Elf_Internal_Rela), + internal_reloc_compare); + nexti = 0; /* Index into internal_relocs. */ + + pin_internal_relocs (sec, internal_relocs); + pin_contents (sec, contents); + + last_irel_offset = (bfd_vma) -1; + section_size = (sec->_cooked_size ? sec->_cooked_size : sec->_raw_size); + BFD_ASSERT (section_size % 8 == 0); + + for (offset = 0; offset < section_size; offset += 8) + { + Elf_Internal_Rela *irel, *next_irel; + bfd_vma bytes_to_remove, size, actual_offset; + bfd_boolean remove_this_irel; + + irel = NULL; + next_irel = NULL; + + /* Find the next two relocations (if there are that many left), + skipping over any R_XTENSA_NONE relocs. On entry, "nexti" is + the starting reloc index. After these two loops, "i" + is the index of the first non-NONE reloc past that starting + index, and "nexti" is the index for the next non-NONE reloc + after "i". */ + + for (i = nexti; i < sec->reloc_count; i++) + { + if (ELF32_R_TYPE (internal_relocs[i].r_info) != R_XTENSA_NONE) + { + irel = &internal_relocs[i]; + break; + } + internal_relocs[i].r_offset -= removed_bytes; + } + + for (nexti = i + 1; nexti < sec->reloc_count; nexti++) + { + if (ELF32_R_TYPE (internal_relocs[nexti].r_info) + != R_XTENSA_NONE) + { + next_irel = &internal_relocs[nexti]; + break; + } + internal_relocs[nexti].r_offset -= removed_bytes; + } + + remove_this_irel = FALSE; + bytes_to_remove = 0; + actual_offset = offset - removed_bytes; + size = bfd_get_32 (abfd, &contents[actual_offset + 4]); + + /* Check that the irels are sorted by offset, + with only one per address. */ + BFD_ASSERT (!irel || (int) irel->r_offset > (int) last_irel_offset); + BFD_ASSERT (!next_irel || next_irel->r_offset > irel->r_offset); + + /* Make sure there isn't a reloc on the size field. */ + if (irel && irel->r_offset == offset + 4) + { + irel->r_offset -= removed_bytes; + last_irel_offset = irel->r_offset; + } + else if (next_irel && next_irel->r_offset == offset + 4) + { + nexti += 1; + irel->r_offset -= removed_bytes; + next_irel->r_offset -= removed_bytes; + last_irel_offset = next_irel->r_offset; + } + else if (size == 0) + { + /* Always remove entries with zero size. */ + bytes_to_remove = 8; + if (irel && irel->r_offset == offset) + { + remove_this_irel = TRUE; + + irel->r_offset -= removed_bytes; + last_irel_offset = irel->r_offset; + } + } + else if (irel && irel->r_offset == offset) + { + if (ELF32_R_TYPE (irel->r_info) == R_XTENSA_32) + { + if (last_irel) + { + bfd_vma old_size = + bfd_get_32 (abfd, &contents[last_irel->r_offset + 4]); + bfd_vma old_address = + (last_irel->r_addend + + bfd_get_32 (abfd, &contents[last_irel->r_offset])); + bfd_vma new_address = + (irel->r_addend + + bfd_get_32 (abfd, &contents[actual_offset])); + + if ((ELF32_R_SYM (irel->r_info) == + ELF32_R_SYM (last_irel->r_info)) + && (old_address + old_size == new_address)) + { + /* fix the old size */ + bfd_put_32 (abfd, old_size + size, + &contents[last_irel->r_offset + 4]); + bytes_to_remove = 8; + remove_this_irel = TRUE; + } + else + last_irel = irel; + } + else + last_irel = irel; + } + + irel->r_offset -= removed_bytes; + last_irel_offset = irel->r_offset; + } + + if (remove_this_irel) + { + irel->r_info = ELF32_R_INFO (0, R_XTENSA_NONE); + irel->r_offset -= bytes_to_remove; + } + + if (bytes_to_remove != 0) + { + removed_bytes += bytes_to_remove; + if (offset + 8 < section_size) + memmove (&contents[actual_offset], + &contents[actual_offset+8], + section_size - offset - 8); + } + } + + if (removed_bytes) + { + /* Clear the removed bytes. */ + memset (&contents[section_size - removed_bytes], 0, removed_bytes); + + sec->_cooked_size = section_size - removed_bytes; + /* Also shrink _raw_size. (The code in relocate_section that + checks that relocations are within the section must use + _raw_size because of the way the stabs sections are + relaxed; shrinking _raw_size means that these checks will + not be unnecessarily lax.) */ + sec->_raw_size = sec->_cooked_size; + + if (xtensa_is_littable_section (sec)) + { + bfd *dynobj = elf_hash_table (link_info)->dynobj; + if (dynobj) + { + asection *sgotloc = + bfd_get_section_by_name (dynobj, ".got.loc"); + if (sgotloc) + { + bfd_size_type sgotloc_size = + (sgotloc->_cooked_size ? sgotloc->_cooked_size + : sgotloc->_raw_size); + sgotloc->_cooked_size = sgotloc_size - removed_bytes; + sgotloc->_raw_size = sgotloc_size - removed_bytes; + } + } + } + } + } + + error_return: + release_internal_relocs (sec, internal_relocs); + release_contents (sec, contents); + return ok; +} + + +/* Third relaxation pass. */ + +/* Change symbol values to account for removed literals. */ + +bfd_boolean +relax_section_symbols (abfd, sec) + bfd *abfd; + asection *sec; +{ + xtensa_relax_info *relax_info; + unsigned int sec_shndx; + Elf_Internal_Shdr *symtab_hdr; + Elf_Internal_Sym *isymbuf; + unsigned i, num_syms, num_locals; + + relax_info = get_xtensa_relax_info (sec); + BFD_ASSERT (relax_info); + + if (!relax_info->is_relaxable_literal_section) + return TRUE; + + sec_shndx = _bfd_elf_section_from_bfd_section (abfd, sec); + + symtab_hdr = &elf_tdata (abfd)->symtab_hdr; + isymbuf = retrieve_local_syms (abfd); + + num_syms = symtab_hdr->sh_size / sizeof (Elf32_External_Sym); + num_locals = symtab_hdr->sh_info; + + /* Adjust the local symbols defined in this section. */ + for (i = 0; i < num_locals; i++) + { + Elf_Internal_Sym *isym = &isymbuf[i]; + + if (isym->st_shndx == sec_shndx) + { + bfd_vma new_address = offset_with_removed_literals + (&relax_info->removed_list, isym->st_value); + if (new_address != isym->st_value) + isym->st_value = new_address; + } + } + + /* Now adjust the global symbols defined in this section. */ + for (i = 0; i < (num_syms - num_locals); i++) + { + struct elf_link_hash_entry *sym_hash; + + sym_hash = elf_sym_hashes (abfd)[i]; + + if (sym_hash->root.type == bfd_link_hash_warning) + sym_hash = (struct elf_link_hash_entry *) sym_hash->root.u.i.link; + + if ((sym_hash->root.type == bfd_link_hash_defined + || sym_hash->root.type == bfd_link_hash_defweak) + && sym_hash->root.u.def.section == sec) + { + bfd_vma new_address = offset_with_removed_literals + (&relax_info->removed_list, sym_hash->root.u.def.value); + if (new_address != sym_hash->root.u.def.value) + sym_hash->root.u.def.value = new_address; + } + } + + return TRUE; +} + + +/* "Fix" handling functions, called while performing relocations. */ + +static void +do_fix_for_relocatable_link (rel, input_bfd, input_section) + Elf_Internal_Rela *rel; + bfd *input_bfd; + asection *input_section; +{ + r_reloc r_rel; + asection *sec, *old_sec; + bfd_vma old_offset; + int r_type = ELF32_R_TYPE (rel->r_info); + reloc_bfd_fix *fix_list; + reloc_bfd_fix *fix; + + if (r_type == R_XTENSA_NONE) + return; + + fix_list = (get_xtensa_relax_info (input_section))->fix_list; + if (fix_list == NULL) + return; + + fix = get_bfd_fix (fix_list, input_section, rel->r_offset, r_type); + if (fix == NULL) + return; + + r_reloc_init (&r_rel, input_bfd, rel); + old_sec = r_reloc_get_section (&r_rel); + old_offset = r_reloc_get_target_offset (&r_rel); + + if (old_sec == NULL || !r_reloc_is_defined (&r_rel)) + { + BFD_ASSERT (r_type == R_XTENSA_ASM_EXPAND); + /* Leave it be. Resolution will happen in a later stage. */ + } + else + { + sec = fix->target_sec; + rel->r_addend += ((sec->output_offset + fix->target_offset) + - (old_sec->output_offset + old_offset)); + } +} + + +static void +do_fix_for_final_link (rel, input_section, relocationp) + Elf_Internal_Rela *rel; + asection *input_section; + bfd_vma *relocationp; +{ + asection *sec; + int r_type = ELF32_R_TYPE (rel->r_info); + reloc_bfd_fix *fix_list; + reloc_bfd_fix *fix; + + if (r_type == R_XTENSA_NONE) + return; + + fix_list = (get_xtensa_relax_info (input_section))->fix_list; + if (fix_list == NULL) + return; + + fix = get_bfd_fix (fix_list, input_section, rel->r_offset, r_type); + if (fix == NULL) + return; + + sec = fix->target_sec; + *relocationp = (sec->output_section->vma + + sec->output_offset + + fix->target_offset - rel->r_addend); +} + + +/* Miscellaneous utility functions.... */ + +static asection * +elf_xtensa_get_plt_section (dynobj, chunk) + bfd *dynobj; + int chunk; +{ + char plt_name[10]; + + if (chunk == 0) + return bfd_get_section_by_name (dynobj, ".plt"); + + sprintf (plt_name, ".plt.%u", chunk); + return bfd_get_section_by_name (dynobj, plt_name); +} + + +static asection * +elf_xtensa_get_gotplt_section (dynobj, chunk) + bfd *dynobj; + int chunk; +{ + char got_name[14]; + + if (chunk == 0) + return bfd_get_section_by_name (dynobj, ".got.plt"); + + sprintf (got_name, ".got.plt.%u", chunk); + return bfd_get_section_by_name (dynobj, got_name); +} + + +/* Get the input section for a given symbol index. + If the symbol is: + . a section symbol, return the section; + . a common symbol, return the common section; + . an undefined symbol, return the undefined section; + . an indirect symbol, follow the links; + . an absolute value, return the absolute section. */ + +static asection * +get_elf_r_symndx_section (abfd, r_symndx) + bfd *abfd; + unsigned long r_symndx; +{ + Elf_Internal_Shdr *symtab_hdr = &elf_tdata (abfd)->symtab_hdr; + asection *target_sec = NULL; + if (r_symndx < symtab_hdr->sh_info) + { + Elf_Internal_Sym *isymbuf; + unsigned int section_index; + + isymbuf = retrieve_local_syms (abfd); + section_index = isymbuf[r_symndx].st_shndx; + + if (section_index == SHN_UNDEF) + target_sec = bfd_und_section_ptr; + else if (section_index > 0 && section_index < SHN_LORESERVE) + target_sec = bfd_section_from_elf_index (abfd, section_index); + else if (section_index == SHN_ABS) + target_sec = bfd_abs_section_ptr; + else if (section_index == SHN_COMMON) + target_sec = bfd_com_section_ptr; + else + /* Who knows? */ + target_sec = NULL; + } + else + { + unsigned long indx = r_symndx - symtab_hdr->sh_info; + struct elf_link_hash_entry *h = elf_sym_hashes (abfd)[indx]; + + while (h->root.type == bfd_link_hash_indirect + || h->root.type == bfd_link_hash_warning) + h = (struct elf_link_hash_entry *) h->root.u.i.link; + + switch (h->root.type) + { + case bfd_link_hash_defined: + case bfd_link_hash_defweak: + target_sec = h->root.u.def.section; + break; + case bfd_link_hash_common: + target_sec = bfd_com_section_ptr; + break; + case bfd_link_hash_undefined: + case bfd_link_hash_undefweak: + target_sec = bfd_und_section_ptr; + break; + default: /* New indirect warning. */ + target_sec = bfd_und_section_ptr; + break; + } + } + return target_sec; +} + + +static struct elf_link_hash_entry * +get_elf_r_symndx_hash_entry (abfd, r_symndx) + bfd *abfd; + unsigned long r_symndx; +{ + unsigned long indx; + struct elf_link_hash_entry *h; + Elf_Internal_Shdr *symtab_hdr = &elf_tdata (abfd)->symtab_hdr; + + if (r_symndx < symtab_hdr->sh_info) + return NULL; + + indx = r_symndx - symtab_hdr->sh_info; + h = elf_sym_hashes (abfd)[indx]; + while (h->root.type == bfd_link_hash_indirect + || h->root.type == bfd_link_hash_warning) + h = (struct elf_link_hash_entry *) h->root.u.i.link; + return h; +} + + +/* Get the section-relative offset for a symbol number. */ + +static bfd_vma +get_elf_r_symndx_offset (abfd, r_symndx) + bfd *abfd; + unsigned long r_symndx; +{ + Elf_Internal_Shdr *symtab_hdr = &elf_tdata (abfd)->symtab_hdr; + bfd_vma offset = 0; + + if (r_symndx < symtab_hdr->sh_info) + { + Elf_Internal_Sym *isymbuf; + isymbuf = retrieve_local_syms (abfd); + offset = isymbuf[r_symndx].st_value; + } + else + { + unsigned long indx = r_symndx - symtab_hdr->sh_info; + struct elf_link_hash_entry *h = + elf_sym_hashes (abfd)[indx]; + + while (h->root.type == bfd_link_hash_indirect + || h->root.type == bfd_link_hash_warning) + h = (struct elf_link_hash_entry *) h->root.u.i.link; + if (h->root.type == bfd_link_hash_defined + || h->root.type == bfd_link_hash_defweak) + offset = h->root.u.def.value; + } + return offset; +} + + +static bfd_boolean +pcrel_reloc_fits (opnd, self_address, dest_address) + xtensa_operand opnd; + bfd_vma self_address; + bfd_vma dest_address; +{ + uint32 new_address = + xtensa_operand_do_reloc (opnd, dest_address, self_address); + return (xtensa_operand_encode (opnd, &new_address) + == xtensa_encode_result_ok); +} + + +static int linkonce_len = sizeof (".gnu.linkonce.") - 1; +static int insn_sec_len = sizeof (XTENSA_INSN_SEC_NAME) - 1; +static int lit_sec_len = sizeof (XTENSA_LIT_SEC_NAME) - 1; + + +static bfd_boolean +xtensa_is_property_section (sec) + asection *sec; +{ + if (strncmp (XTENSA_INSN_SEC_NAME, sec->name, insn_sec_len) == 0 + || strncmp (XTENSA_LIT_SEC_NAME, sec->name, lit_sec_len) == 0) + return TRUE; + + if (strncmp (".gnu.linkonce.", sec->name, linkonce_len) == 0 + && (sec->name[linkonce_len] == 'x' + || sec->name[linkonce_len] == 'p') + && sec->name[linkonce_len + 1] == '.') + return TRUE; + + return FALSE; +} + + +static bfd_boolean +xtensa_is_littable_section (sec) + asection *sec; +{ + if (strncmp (XTENSA_LIT_SEC_NAME, sec->name, lit_sec_len) == 0) + return TRUE; + + if (strncmp (".gnu.linkonce.", sec->name, linkonce_len) == 0 + && sec->name[linkonce_len] == 'p' + && sec->name[linkonce_len + 1] == '.') + return TRUE; + + return FALSE; +} + + +static bfd_boolean +is_literal_section (sec) + asection *sec; +{ + /* FIXME: the current definition of this leaves a lot to be desired.... */ + if (sec == NULL || sec->name == NULL) + return FALSE; + return (strstr (sec->name, "literal") != NULL); +} + + +static int +internal_reloc_compare (ap, bp) + const PTR ap; + const PTR bp; +{ + const Elf_Internal_Rela *a = (const Elf_Internal_Rela *) ap; + const Elf_Internal_Rela *b = (const Elf_Internal_Rela *) bp; + + return (a->r_offset - b->r_offset); +} + + +char * +xtensa_get_property_section_name (sec, base_name) + asection *sec; + const char *base_name; +{ + if (strncmp (sec->name, ".gnu.linkonce.", linkonce_len) == 0) + { + char *prop_sec_name; + const char *suffix; + char linkonce_kind = 0; + + if (strcmp (base_name, XTENSA_INSN_SEC_NAME) == 0) + linkonce_kind = 'x'; + else if (strcmp (base_name, XTENSA_LIT_SEC_NAME) == 0) + linkonce_kind = 'p'; + else + abort (); + + prop_sec_name = (char *) bfd_malloc (strlen (sec->name) + 1); + memcpy (prop_sec_name, ".gnu.linkonce.", linkonce_len); + prop_sec_name[linkonce_len] = linkonce_kind; + prop_sec_name[linkonce_len + 1] = '.'; + + suffix = sec->name + linkonce_len; + while (*suffix) + { + suffix += 1; + if (suffix[-1] == '.') + break; + } + strcpy (prop_sec_name + linkonce_len + 2, suffix); + + return prop_sec_name; + } + + return strdup (base_name); +} + + +/* Other functions called directly by the linker. */ + +bfd_boolean +xtensa_callback_required_dependence (abfd, sec, link_info, callback, closure) + bfd *abfd; + asection *sec; + struct bfd_link_info *link_info; + deps_callback_t callback; + PTR closure; +{ + Elf_Internal_Rela *internal_relocs; + bfd_byte *contents; + unsigned i; + bfd_boolean ok = TRUE; + + /* ".plt*" sections have no explicit relocations but they contain L32R + instructions that reference the corresponding ".got.plt*" sections. */ + if ((sec->flags & SEC_LINKER_CREATED) != 0 + && strncmp (sec->name, ".plt", 4) == 0) + { + asection *sgotplt; + + /* Find the corresponding ".got.plt*" section. */ + if (sec->name[4] == '\0') + sgotplt = bfd_get_section_by_name (sec->owner, ".got.plt"); + else + { + char got_name[14]; + int chunk = 0; + + BFD_ASSERT (sec->name[4] == '.'); + chunk = strtol (&sec->name[5], NULL, 10); + + sprintf (got_name, ".got.plt.%u", chunk); + sgotplt = bfd_get_section_by_name (sec->owner, got_name); + } + BFD_ASSERT (sgotplt); + + /* Assume worst-case offsets: L32R at the very end of the ".plt" + section referencing a literal at the very beginning of + ".got.plt". This is very close to the real dependence, anyway. */ + (*callback) (sec, sec->_raw_size, sgotplt, 0, closure); + } + + internal_relocs = retrieve_internal_relocs (abfd, sec, + link_info->keep_memory); + if (internal_relocs == NULL + || sec->reloc_count == 0) + return ok; + + /* Cache the contents for the duration of this scan. */ + contents = retrieve_contents (abfd, sec, link_info->keep_memory); + if (contents == NULL && sec->_raw_size != 0) + { + ok = FALSE; + goto error_return; + } + + if (xtensa_default_isa == NULL) + xtensa_isa_init (); + + for (i = 0; i < sec->reloc_count; i++) + { + Elf_Internal_Rela *irel = &internal_relocs[i]; + if (is_l32r_relocation (sec, contents, irel)) + { + r_reloc l32r_rel; + asection *target_sec; + bfd_vma target_offset; + + r_reloc_init (&l32r_rel, abfd, irel); + target_sec = NULL; + target_offset = 0; + /* L32Rs must be local to the input file. */ + if (r_reloc_is_defined (&l32r_rel)) + { + target_sec = r_reloc_get_section (&l32r_rel); + target_offset = r_reloc_get_target_offset (&l32r_rel); + } + (*callback) (sec, irel->r_offset, target_sec, target_offset, + closure); + } + } + + error_return: + release_internal_relocs (sec, internal_relocs); + release_contents (sec, contents); + return ok; +} + +/* The default literal sections should always be marked as "code" (i.e., + SHF_EXECINSTR). This is particularly important for the Linux kernel + module loader so that the literals are not placed after the text. */ +static struct bfd_elf_special_section const elf_xtensa_special_sections[]= +{ + { ".literal", 8, 0, SHT_PROGBITS, SHF_ALLOC + SHF_EXECINSTR }, + { ".init.literal", 13, 0, SHT_PROGBITS, SHF_ALLOC + SHF_EXECINSTR }, + { ".fini.literal", 13, 0, SHT_PROGBITS, SHF_ALLOC + SHF_EXECINSTR }, + { NULL, 0, 0, 0, 0 } +}; + + +#ifndef ELF_ARCH +#define TARGET_LITTLE_SYM bfd_elf32_xtensa_le_vec +#define TARGET_LITTLE_NAME "elf32-xtensa-le" +#define TARGET_BIG_SYM bfd_elf32_xtensa_be_vec +#define TARGET_BIG_NAME "elf32-xtensa-be" +#define ELF_ARCH bfd_arch_xtensa + +/* The new EM_XTENSA value will be recognized beginning in the Xtensa T1040 + release. However, we still have to generate files with the EM_XTENSA_OLD + value so that pre-T1040 tools can read the files. As soon as we stop + caring about pre-T1040 tools, the following two values should be + swapped. At the same time, any other code that uses EM_XTENSA_OLD + (e.g., prep_headers() in elf.c) should be changed to use EM_XTENSA. */ +#define ELF_MACHINE_CODE EM_XTENSA_OLD +#define ELF_MACHINE_ALT1 EM_XTENSA + +#if XCHAL_HAVE_MMU +#define ELF_MAXPAGESIZE (1 << XCHAL_MMU_MIN_PTE_PAGE_SIZE) +#else /* !XCHAL_HAVE_MMU */ +#define ELF_MAXPAGESIZE 1 +#endif /* !XCHAL_HAVE_MMU */ +#endif /* ELF_ARCH */ + +#define elf_backend_can_gc_sections 1 +#define elf_backend_can_refcount 1 +#define elf_backend_plt_readonly 1 +#define elf_backend_got_header_size 4 +#define elf_backend_want_dynbss 0 +#define elf_backend_want_got_plt 1 + +#define elf_info_to_howto elf_xtensa_info_to_howto_rela + +#define bfd_elf32_bfd_final_link bfd_elf32_bfd_final_link +#define bfd_elf32_bfd_merge_private_bfd_data elf_xtensa_merge_private_bfd_data +#define bfd_elf32_new_section_hook elf_xtensa_new_section_hook +#define bfd_elf32_bfd_print_private_bfd_data elf_xtensa_print_private_bfd_data +#define bfd_elf32_bfd_relax_section elf_xtensa_relax_section +#define bfd_elf32_bfd_reloc_type_lookup elf_xtensa_reloc_type_lookup +#define bfd_elf32_bfd_set_private_flags elf_xtensa_set_private_flags + +#define elf_backend_adjust_dynamic_symbol elf_xtensa_adjust_dynamic_symbol +#define elf_backend_check_relocs elf_xtensa_check_relocs +#define elf_backend_create_dynamic_sections elf_xtensa_create_dynamic_sections +#define elf_backend_discard_info elf_xtensa_discard_info +#define elf_backend_ignore_discarded_relocs elf_xtensa_ignore_discarded_relocs +#define elf_backend_final_write_processing elf_xtensa_final_write_processing +#define elf_backend_finish_dynamic_sections elf_xtensa_finish_dynamic_sections +#define elf_backend_finish_dynamic_symbol elf_xtensa_finish_dynamic_symbol +#define elf_backend_gc_mark_hook elf_xtensa_gc_mark_hook +#define elf_backend_gc_sweep_hook elf_xtensa_gc_sweep_hook +#define elf_backend_grok_prstatus elf_xtensa_grok_prstatus +#define elf_backend_grok_psinfo elf_xtensa_grok_psinfo +#define elf_backend_hide_symbol elf_xtensa_hide_symbol +#define elf_backend_modify_segment_map elf_xtensa_modify_segment_map +#define elf_backend_object_p elf_xtensa_object_p +#define elf_backend_reloc_type_class elf_xtensa_reloc_type_class +#define elf_backend_relocate_section elf_xtensa_relocate_section +#define elf_backend_size_dynamic_sections elf_xtensa_size_dynamic_sections +#define elf_backend_special_sections elf_xtensa_special_sections + +#include "elf32-target.h" diff --git a/bfd/mach-o-target.c b/bfd/mach-o-target.c new file mode 100644 index 0000000..b271bfc --- /dev/null +++ b/bfd/mach-o-target.c @@ -0,0 +1,117 @@ +/* Mach-O support for BFD. + Copyright 1999, 2000, 2001, 2002 + Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef TARGET_NAME +#error TARGET_NAME must be defined +#endif /* TARGET_NAME */ + +#ifndef TARGET_STRING +#error TARGET_STRING must be defined +#endif /* TARGET_STRING */ + +#ifndef TARGET_BIG_ENDIAN +#error TARGET_BIG_ENDIAN must be defined +#endif /* TARGET_BIG_ENDIAN */ + +#ifndef TARGET_ARCHIVE +#error TARGET_ARCHIVE must be defined +#endif /* TARGET_ARCHIVE */ + +#if ((TARGET_ARCHIVE) && (! TARGET_BIG_ENDIAN)) +#error Mach-O fat files must always be big-endian. +#endif /* ((TARGET_ARCHIVE) && (! TARGET_BIG_ENDIAN)) */ + +const bfd_target TARGET_NAME = +{ + TARGET_STRING, /* Name. */ + bfd_target_mach_o_flavour, +#if TARGET_BIG_ENDIAN + BFD_ENDIAN_BIG, /* Target byte order. */ + BFD_ENDIAN_BIG, /* Target headers byte order. */ +#else + BFD_ENDIAN_LITTLE, /* Target byte order. */ + BFD_ENDIAN_LITTLE, /* Target headers byte order. */ +#endif + (HAS_RELOC | EXEC_P | /* Object flags. */ + HAS_LINENO | HAS_DEBUG | + HAS_SYMS | HAS_LOCALS | DYNAMIC | WP_TEXT | D_PAGED), + (SEC_CODE | SEC_DATA | SEC_ROM | SEC_HAS_CONTENTS + | SEC_ALLOC | SEC_LOAD | SEC_RELOC), /* Section flags. */ + '_', /* symbol_leading_char. */ + ' ', /* ar_pad_char. */ + 16, /* ar_max_namelen. */ + +#if TARGET_BIG_ENDIAN + bfd_getb64, bfd_getb_signed_64, bfd_putb64, + bfd_getb32, bfd_getb_signed_32, bfd_putb32, + bfd_getb16, bfd_getb_signed_16, bfd_putb16, /* Data. */ + bfd_getb64, bfd_getb_signed_64, bfd_putb64, + bfd_getb32, bfd_getb_signed_32, bfd_putb32, + bfd_getb16, bfd_getb_signed_16, bfd_putb16, /* Hdrs. */ +#else + bfd_getl64, bfd_getl_signed_64, bfd_putl64, + bfd_getl32, bfd_getl_signed_32, bfd_putl32, + bfd_getl16, bfd_getl_signed_16, bfd_putl16, /* data */ + bfd_getl64, bfd_getl_signed_64, bfd_putl64, + bfd_getl32, bfd_getl_signed_32, bfd_putl32, + bfd_getl16, bfd_getl_signed_16, bfd_putl16, /* hdrs */ +#endif /* TARGET_BIG_ENDIAN */ + + { /* bfd_check_format. */ +#if TARGET_ARCHIVE + _bfd_dummy_target, + _bfd_dummy_target, + bfd_mach_o_archive_p, + _bfd_dummy_target, +#else + _bfd_dummy_target, + bfd_mach_o_object_p, + _bfd_dummy_target, + bfd_mach_o_core_p +#endif + }, + { /* bfd_set_format. */ + bfd_false, + bfd_mach_o_mkobject, + bfd_false, + bfd_mach_o_mkobject, + }, + { /* bfd_write_contents. */ + bfd_false, + bfd_mach_o_write_contents, + bfd_false, + bfd_mach_o_write_contents, + }, + + BFD_JUMP_TABLE_GENERIC (bfd_mach_o), + BFD_JUMP_TABLE_COPY (bfd_mach_o), + BFD_JUMP_TABLE_CORE (bfd_mach_o), + BFD_JUMP_TABLE_ARCHIVE (bfd_mach_o), + BFD_JUMP_TABLE_SYMBOLS (bfd_mach_o), + BFD_JUMP_TABLE_RELOCS (bfd_mach_o), + BFD_JUMP_TABLE_WRITE (bfd_mach_o), + BFD_JUMP_TABLE_LINK (bfd_mach_o), + BFD_JUMP_TABLE_DYNAMIC (_bfd_nodynamic), + + NULL, + + NULL +}; + diff --git a/bfd/mach-o.c b/bfd/mach-o.c new file mode 100644 index 0000000..2dc8073 --- /dev/null +++ b/bfd/mach-o.c @@ -0,0 +1,2227 @@ +/* Mach-O support for BFD. + Copyright 1999, 2000, 2001, 2002, 2003 + Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include "mach-o.h" +#include "bfd.h" +#include "sysdep.h" +#include "libbfd.h" +#include "libiberty.h" +#include + +#ifndef BFD_IO_FUNCS +#define BFD_IO_FUNCS 0 +#endif + +#define bfd_mach_o_mkarchive _bfd_noarchive_mkarchive +#define bfd_mach_o_read_ar_hdr _bfd_noarchive_read_ar_hdr +#define bfd_mach_o_slurp_armap _bfd_noarchive_slurp_armap +#define bfd_mach_o_slurp_extended_name_table _bfd_noarchive_slurp_extended_name_table +#define bfd_mach_o_construct_extended_name_table _bfd_noarchive_construct_extended_name_table +#define bfd_mach_o_truncate_arname _bfd_noarchive_truncate_arname +#define bfd_mach_o_write_armap _bfd_noarchive_write_armap +#define bfd_mach_o_get_elt_at_index _bfd_noarchive_get_elt_at_index +#define bfd_mach_o_generic_stat_arch_elt _bfd_noarchive_generic_stat_arch_elt +#define bfd_mach_o_update_armap_timestamp _bfd_noarchive_update_armap_timestamp +#define bfd_mach_o_close_and_cleanup _bfd_generic_close_and_cleanup +#define bfd_mach_o_bfd_free_cached_info _bfd_generic_bfd_free_cached_info +#define bfd_mach_o_new_section_hook _bfd_generic_new_section_hook +#define bfd_mach_o_get_section_contents_in_window _bfd_generic_get_section_contents_in_window +#define bfd_mach_o_bfd_is_local_label_name _bfd_nosymbols_bfd_is_local_label_name +#define bfd_mach_o_get_lineno _bfd_nosymbols_get_lineno +#define bfd_mach_o_find_nearest_line _bfd_nosymbols_find_nearest_line +#define bfd_mach_o_bfd_make_debug_symbol _bfd_nosymbols_bfd_make_debug_symbol +#define bfd_mach_o_read_minisymbols _bfd_generic_read_minisymbols +#define bfd_mach_o_minisymbol_to_symbol _bfd_generic_minisymbol_to_symbol +#define bfd_mach_o_get_reloc_upper_bound _bfd_norelocs_get_reloc_upper_bound +#define bfd_mach_o_canonicalize_reloc _bfd_norelocs_canonicalize_reloc +#define bfd_mach_o_bfd_reloc_type_lookup _bfd_norelocs_bfd_reloc_type_lookup +#define bfd_mach_o_bfd_get_relocated_section_contents bfd_generic_get_relocated_section_contents +#define bfd_mach_o_bfd_relax_section bfd_generic_relax_section +#define bfd_mach_o_bfd_link_hash_table_create _bfd_generic_link_hash_table_create +#define bfd_mach_o_bfd_link_hash_table_free _bfd_generic_link_hash_table_free +#define bfd_mach_o_bfd_link_add_symbols _bfd_generic_link_add_symbols +#define bfd_mach_o_bfd_link_just_syms _bfd_generic_link_just_syms +#define bfd_mach_o_bfd_final_link _bfd_generic_final_link +#define bfd_mach_o_bfd_link_split_section _bfd_generic_link_split_section +#define bfd_mach_o_set_arch_mach bfd_default_set_arch_mach +#define bfd_mach_o_bfd_merge_private_bfd_data _bfd_generic_bfd_merge_private_bfd_data +#define bfd_mach_o_bfd_set_private_flags _bfd_generic_bfd_set_private_flags +#define bfd_mach_o_bfd_print_private_bfd_data _bfd_generic_bfd_print_private_bfd_data +#define bfd_mach_o_get_section_contents _bfd_generic_get_section_contents +#define bfd_mach_o_set_section_contents _bfd_generic_set_section_contents +#define bfd_mach_o_bfd_gc_sections bfd_generic_gc_sections +#define bfd_mach_o_bfd_merge_sections bfd_generic_merge_sections +#define bfd_mach_o_bfd_discard_group bfd_generic_discard_group + +static bfd_boolean bfd_mach_o_bfd_copy_private_symbol_data + PARAMS ((bfd *, asymbol *, bfd *, asymbol *)); +static bfd_boolean bfd_mach_o_bfd_copy_private_section_data + PARAMS ((bfd *, asection *, bfd *, asection *)); +static bfd_boolean bfd_mach_o_bfd_copy_private_bfd_data + PARAMS ((bfd *, bfd *)); +static long bfd_mach_o_count_symbols + PARAMS ((bfd *)); +static long bfd_mach_o_get_symtab_upper_bound + PARAMS ((bfd *)); +static long bfd_mach_o_canonicalize_symtab + PARAMS ((bfd *, asymbol **)); +static void bfd_mach_o_get_symbol_info + PARAMS ((bfd *, asymbol *, symbol_info *)); +static void bfd_mach_o_print_symbol + PARAMS ((bfd *, PTR, asymbol *, bfd_print_symbol_type)); +static void bfd_mach_o_convert_architecture + PARAMS ((bfd_mach_o_cpu_type, bfd_mach_o_cpu_subtype, + enum bfd_architecture *, unsigned long *)); +static bfd_boolean bfd_mach_o_write_contents + PARAMS ((bfd *)); +static int bfd_mach_o_sizeof_headers + PARAMS ((bfd *, bfd_boolean)); +static asymbol * bfd_mach_o_make_empty_symbol + PARAMS ((bfd *)); +static int bfd_mach_o_write_header + PARAMS ((bfd *, bfd_mach_o_header *)); +static int bfd_mach_o_read_header + PARAMS ((bfd *, bfd_mach_o_header *)); +static asection * bfd_mach_o_make_bfd_section + PARAMS ((bfd *, bfd_mach_o_section *)); +static int bfd_mach_o_scan_read_section + PARAMS ((bfd *, bfd_mach_o_section *, bfd_vma)); +static int bfd_mach_o_scan_write_section + PARAMS ((bfd *, bfd_mach_o_section *, bfd_vma)); +static int bfd_mach_o_scan_write_symtab_symbols + PARAMS ((bfd *, bfd_mach_o_load_command *)); +static int bfd_mach_o_scan_write_thread + PARAMS ((bfd *, bfd_mach_o_load_command *)); +static int bfd_mach_o_scan_read_dylinker + PARAMS ((bfd *, bfd_mach_o_load_command *)); +static int bfd_mach_o_scan_read_dylib + PARAMS ((bfd *, bfd_mach_o_load_command *)); +static int bfd_mach_o_scan_read_prebound_dylib + PARAMS ((bfd *, bfd_mach_o_load_command *)); +static int bfd_mach_o_scan_read_thread + PARAMS ((bfd *, bfd_mach_o_load_command *)); +static int bfd_mach_o_scan_write_symtab + PARAMS ((bfd *, bfd_mach_o_load_command *)); +static int bfd_mach_o_scan_read_dysymtab + PARAMS ((bfd *, bfd_mach_o_load_command *)); +static int bfd_mach_o_scan_read_symtab + PARAMS ((bfd *, bfd_mach_o_load_command *)); +static int bfd_mach_o_scan_read_segment + PARAMS ((bfd *, bfd_mach_o_load_command *)); +static int bfd_mach_o_scan_write_segment + PARAMS ((bfd *, bfd_mach_o_load_command *)); +static int bfd_mach_o_scan_read_command + PARAMS ((bfd *, bfd_mach_o_load_command *)); +static void bfd_mach_o_flatten_sections + PARAMS ((bfd *)); +static const char * bfd_mach_o_i386_flavour_string + PARAMS ((unsigned int)); +static const char * bfd_mach_o_ppc_flavour_string + PARAMS ((unsigned int)); + +/* The flags field of a section structure is separated into two parts a section + type and section attributes. The section types are mutually exclusive (it + can only have one type) but the section attributes are not (it may have more + than one attribute). */ + +#define SECTION_TYPE 0x000000ff /* 256 section types. */ +#define SECTION_ATTRIBUTES 0xffffff00 /* 24 section attributes. */ + +/* Constants for the section attributes part of the flags field of a section + structure. */ + +#define SECTION_ATTRIBUTES_USR 0xff000000 /* User-settable attributes. */ +#define S_ATTR_PURE_INSTRUCTIONS 0x80000000 /* Section contains only true machine instructions. */ +#define SECTION_ATTRIBUTES_SYS 0x00ffff00 /* System setable attributes. */ +#define S_ATTR_SOME_INSTRUCTIONS 0x00000400 /* Section contains some machine instructions. */ +#define S_ATTR_EXT_RELOC 0x00000200 /* Section has external relocation entries. */ +#define S_ATTR_LOC_RELOC 0x00000100 /* Section has local relocation entries. */ + +#define N_STAB 0xe0 +#define N_TYPE 0x1e +#define N_EXT 0x01 +#define N_UNDF 0x0 +#define N_ABS 0x2 +#define N_SECT 0xe +#define N_INDR 0xa + +bfd_boolean +bfd_mach_o_valid (abfd) + bfd *abfd; +{ + if (abfd == NULL || abfd->xvec == NULL) + return 0; + + if (! ((abfd->xvec == &mach_o_be_vec) + || (abfd->xvec == &mach_o_le_vec) + || (abfd->xvec == &mach_o_fat_vec))) + return 0; + + if (abfd->tdata.mach_o_data == NULL) + return 0; + return 1; +} + +/* Copy any private info we understand from the input symbol + to the output symbol. */ + +static bfd_boolean +bfd_mach_o_bfd_copy_private_symbol_data (ibfd, isymbol, obfd, osymbol) + bfd *ibfd ATTRIBUTE_UNUSED; + asymbol *isymbol ATTRIBUTE_UNUSED; + bfd *obfd ATTRIBUTE_UNUSED; + asymbol *osymbol ATTRIBUTE_UNUSED; +{ + return TRUE; +} + +/* Copy any private info we understand from the input section + to the output section. */ + +static bfd_boolean +bfd_mach_o_bfd_copy_private_section_data (ibfd, isection, obfd, osection) + bfd *ibfd ATTRIBUTE_UNUSED; + asection *isection ATTRIBUTE_UNUSED; + bfd *obfd ATTRIBUTE_UNUSED; + asection *osection ATTRIBUTE_UNUSED; +{ + return TRUE; +} + +/* Copy any private info we understand from the input bfd + to the output bfd. */ + +static bfd_boolean +bfd_mach_o_bfd_copy_private_bfd_data (ibfd, obfd) + bfd *ibfd; + bfd *obfd; +{ + BFD_ASSERT (bfd_mach_o_valid (ibfd)); + BFD_ASSERT (bfd_mach_o_valid (obfd)); + + obfd->tdata.mach_o_data = ibfd->tdata.mach_o_data; + obfd->tdata.mach_o_data->ibfd = ibfd; + return TRUE; +} + +static long +bfd_mach_o_count_symbols (abfd) + bfd *abfd; +{ + bfd_mach_o_data_struct *mdata = NULL; + long nsyms = 0; + unsigned long i; + + BFD_ASSERT (bfd_mach_o_valid (abfd)); + mdata = abfd->tdata.mach_o_data; + + for (i = 0; i < mdata->header.ncmds; i++) + if (mdata->commands[i].type == BFD_MACH_O_LC_SYMTAB) + { + bfd_mach_o_symtab_command *sym = &mdata->commands[i].command.symtab; + nsyms += sym->nsyms; + } + + return nsyms; +} + +static long +bfd_mach_o_get_symtab_upper_bound (abfd) + bfd *abfd; +{ + long nsyms = bfd_mach_o_count_symbols (abfd); + + if (nsyms < 0) + return nsyms; + + return ((nsyms + 1) * sizeof (asymbol *)); +} + +static long +bfd_mach_o_canonicalize_symtab (abfd, alocation) + bfd *abfd; + asymbol **alocation; +{ + bfd_mach_o_data_struct *mdata = abfd->tdata.mach_o_data; + long nsyms = bfd_mach_o_count_symbols (abfd); + asymbol **csym = alocation; + unsigned long i, j; + + if (nsyms < 0) + return nsyms; + + for (i = 0; i < mdata->header.ncmds; i++) + { + if (mdata->commands[i].type == BFD_MACH_O_LC_SYMTAB) + { + bfd_mach_o_symtab_command *sym = &mdata->commands[i].command.symtab; + + if (bfd_mach_o_scan_read_symtab_symbols (abfd, &mdata->commands[i].command.symtab) != 0) + { + fprintf (stderr, "bfd_mach_o_canonicalize_symtab: unable to load symbols for section %lu\n", i); + return 0; + } + + BFD_ASSERT (sym->symbols != NULL); + + for (j = 0; j < sym->nsyms; j++) + { + BFD_ASSERT (csym < (alocation + nsyms)); + *csym++ = &sym->symbols[j]; + } + } + } + + *csym++ = NULL; + + return nsyms; +} + +static void +bfd_mach_o_get_symbol_info (abfd, symbol, ret) + bfd *abfd ATTRIBUTE_UNUSED; + asymbol *symbol; + symbol_info *ret; +{ + bfd_symbol_info (symbol, ret); +} + +static void +bfd_mach_o_print_symbol (abfd, afile, symbol, how) + bfd *abfd; + PTR afile; + asymbol *symbol; + bfd_print_symbol_type how; +{ + FILE *file = (FILE *) afile; + + switch (how) + { + case bfd_print_symbol_name: + fprintf (file, "%s", symbol->name); + break; + default: + bfd_print_symbol_vandf (abfd, (PTR) file, symbol); + fprintf (file, " %-5s %s", symbol->section->name, symbol->name); + } +} + +static void +bfd_mach_o_convert_architecture (mtype, msubtype, type, subtype) + bfd_mach_o_cpu_type mtype; + bfd_mach_o_cpu_subtype msubtype ATTRIBUTE_UNUSED; + enum bfd_architecture *type; + unsigned long *subtype; +{ + *subtype = bfd_arch_unknown; + + switch (mtype) + { + case BFD_MACH_O_CPU_TYPE_VAX: *type = bfd_arch_vax; break; + case BFD_MACH_O_CPU_TYPE_MC680x0: *type = bfd_arch_m68k; break; + case BFD_MACH_O_CPU_TYPE_I386: *type = bfd_arch_i386; break; + case BFD_MACH_O_CPU_TYPE_MIPS: *type = bfd_arch_mips; break; + case BFD_MACH_O_CPU_TYPE_MC98000: *type = bfd_arch_m98k; break; + case BFD_MACH_O_CPU_TYPE_HPPA: *type = bfd_arch_hppa; break; + case BFD_MACH_O_CPU_TYPE_ARM: *type = bfd_arch_arm; break; + case BFD_MACH_O_CPU_TYPE_MC88000: *type = bfd_arch_m88k; break; + case BFD_MACH_O_CPU_TYPE_SPARC: *type = bfd_arch_sparc; break; + case BFD_MACH_O_CPU_TYPE_I860: *type = bfd_arch_i860; break; + case BFD_MACH_O_CPU_TYPE_ALPHA: *type = bfd_arch_alpha; break; + case BFD_MACH_O_CPU_TYPE_POWERPC: *type = bfd_arch_powerpc; break; + default: *type = bfd_arch_unknown; break; + } + + switch (*type) + { + case bfd_arch_i386: *subtype = bfd_mach_i386_i386; break; + case bfd_arch_sparc: *subtype = bfd_mach_sparc; break; + default: + *subtype = bfd_arch_unknown; + } +} + +static bfd_boolean +bfd_mach_o_write_contents (abfd) + bfd *abfd; +{ + unsigned int i; + asection *s; + + bfd_mach_o_data_struct *mdata = abfd->tdata.mach_o_data; + + /* Write data sections first in case they overlap header data to be + written later. */ + + for (s = abfd->sections; s != (asection *) NULL; s = s->next) + ; + +#if 0 + for (i = 0; i < mdata->header.ncmds; i++) + { + bfd_mach_o_load_command *cur = &mdata->commands[i]; + if (cur->type != BFD_MACH_O_LC_SEGMENT) + break; + + { + bfd_mach_o_segment_command *seg = &cur->command.segment; + char buf[1024]; + bfd_vma nbytes = seg->filesize; + bfd_vma curoff = seg->fileoff; + + while (nbytes > 0) + { + bfd_vma thisread = nbytes; + + if (thisread > 1024) + thisread = 1024; + + bfd_seek (abfd, curoff, SEEK_SET); + if (bfd_bread ((PTR) buf, thisread, abfd) != thisread) + return FALSE; + + bfd_seek (abfd, curoff, SEEK_SET); + if (bfd_bwrite ((PTR) buf, thisread, abfd) != thisread) + return FALSE; + + nbytes -= thisread; + curoff += thisread; + } + } + } +#endif + + /* Now write header information. */ + if (bfd_mach_o_write_header (abfd, &mdata->header) != 0) + return FALSE; + + for (i = 0; i < mdata->header.ncmds; i++) + { + unsigned char buf[8]; + bfd_mach_o_load_command *cur = &mdata->commands[i]; + unsigned long typeflag; + + typeflag = cur->type_required ? cur->type & BFD_MACH_O_LC_REQ_DYLD : cur->type; + + bfd_h_put_32 (abfd, typeflag, buf); + bfd_h_put_32 (abfd, cur->len, buf + 4); + + bfd_seek (abfd, cur->offset, SEEK_SET); + if (bfd_bwrite ((PTR) buf, 8, abfd) != 8) + return FALSE; + + switch (cur->type) + { + case BFD_MACH_O_LC_SEGMENT: + if (bfd_mach_o_scan_write_segment (abfd, cur) != 0) + return FALSE; + break; + case BFD_MACH_O_LC_SYMTAB: + if (bfd_mach_o_scan_write_symtab (abfd, cur) != 0) + return FALSE; + break; + case BFD_MACH_O_LC_SYMSEG: + break; + case BFD_MACH_O_LC_THREAD: + case BFD_MACH_O_LC_UNIXTHREAD: + if (bfd_mach_o_scan_write_thread (abfd, cur) != 0) + return FALSE; + break; + case BFD_MACH_O_LC_LOADFVMLIB: + case BFD_MACH_O_LC_IDFVMLIB: + case BFD_MACH_O_LC_IDENT: + case BFD_MACH_O_LC_FVMFILE: + case BFD_MACH_O_LC_PREPAGE: + case BFD_MACH_O_LC_DYSYMTAB: + case BFD_MACH_O_LC_LOAD_DYLIB: + case BFD_MACH_O_LC_LOAD_WEAK_DYLIB: + case BFD_MACH_O_LC_ID_DYLIB: + case BFD_MACH_O_LC_LOAD_DYLINKER: + case BFD_MACH_O_LC_ID_DYLINKER: + case BFD_MACH_O_LC_PREBOUND_DYLIB: + case BFD_MACH_O_LC_ROUTINES: + case BFD_MACH_O_LC_SUB_FRAMEWORK: + break; + default: + fprintf (stderr, + "unable to write unknown load command 0x%lx\n", + (long) cur->type); + return FALSE; + } + } + + return TRUE; +} + +static int +bfd_mach_o_sizeof_headers (a, b) + bfd *a ATTRIBUTE_UNUSED; + bfd_boolean b ATTRIBUTE_UNUSED; +{ + return 0; +} + +/* Make an empty symbol. This is required only because + bfd_make_section_anyway wants to create a symbol for the section. */ + +static asymbol * +bfd_mach_o_make_empty_symbol (abfd) + bfd *abfd; +{ + asymbol *new; + + new = (asymbol *) bfd_zalloc (abfd, sizeof (asymbol)); + if (new == NULL) + return new; + new->the_bfd = abfd; + return new; +} + +static int +bfd_mach_o_write_header (abfd, header) + bfd *abfd; + bfd_mach_o_header *header; +{ + unsigned char buf[28]; + + bfd_h_put_32 (abfd, header->magic, buf + 0); + bfd_h_put_32 (abfd, header->cputype, buf + 4); + bfd_h_put_32 (abfd, header->cpusubtype, buf + 8); + bfd_h_put_32 (abfd, header->filetype, buf + 12); + bfd_h_put_32 (abfd, header->ncmds, buf + 16); + bfd_h_put_32 (abfd, header->sizeofcmds, buf + 20); + bfd_h_put_32 (abfd, header->flags, buf + 24); + + bfd_seek (abfd, 0, SEEK_SET); + if (bfd_bwrite ((PTR) buf, 28, abfd) != 28) + return -1; + + return 0; +} + +static int +bfd_mach_o_read_header (abfd, header) + bfd *abfd; + bfd_mach_o_header *header; +{ + unsigned char buf[28]; + bfd_vma (*get32) PARAMS ((const bfd_byte *)) = NULL; + + bfd_seek (abfd, 0, SEEK_SET); + + if (bfd_bread ((PTR) buf, 28, abfd) != 28) + return -1; + + if (bfd_getb32 (buf) == 0xfeedface) + { + header->byteorder = BFD_ENDIAN_BIG; + header->magic = 0xfeedface; + get32 = bfd_getb32; + } + else if (bfd_getl32 (buf) == 0xfeedface) + { + header->byteorder = BFD_ENDIAN_LITTLE; + header->magic = 0xfeedface; + get32 = bfd_getl32; + } + else + { + header->byteorder = BFD_ENDIAN_UNKNOWN; + return -1; + } + + header->cputype = (*get32) (buf + 4); + header->cpusubtype = (*get32) (buf + 8); + header->filetype = (*get32) (buf + 12); + header->ncmds = (*get32) (buf + 16); + header->sizeofcmds = (*get32) (buf + 20); + header->flags = (*get32) (buf + 24); + + return 0; +} + +static asection * +bfd_mach_o_make_bfd_section (abfd, section) + bfd *abfd; + bfd_mach_o_section *section; +{ + asection *bfdsec; + char *sname; + const char *prefix = "LC_SEGMENT"; + unsigned int snamelen; + + snamelen = strlen (prefix) + 1 + + strlen (section->segname) + 1 + + strlen (section->sectname) + 1; + + sname = (char *) bfd_alloc (abfd, snamelen); + if (sname == NULL) + return NULL; + sprintf (sname, "%s.%s.%s", prefix, section->segname, section->sectname); + + bfdsec = bfd_make_section_anyway (abfd, sname); + if (bfdsec == NULL) + return NULL; + + bfdsec->vma = section->addr; + bfdsec->lma = section->addr; + bfdsec->_raw_size = section->size; + bfdsec->filepos = section->offset; + bfdsec->alignment_power = section->align; + + if (section->flags & BFD_MACH_O_S_ZEROFILL) + bfdsec->flags = SEC_ALLOC; + else + bfdsec->flags = SEC_HAS_CONTENTS | SEC_LOAD | SEC_ALLOC | SEC_CODE; + + return bfdsec; +} + +static int +bfd_mach_o_scan_read_section (abfd, section, offset) + bfd *abfd; + bfd_mach_o_section *section; + bfd_vma offset; +{ + unsigned char buf[68]; + + bfd_seek (abfd, offset, SEEK_SET); + if (bfd_bread ((PTR) buf, 68, abfd) != 68) + return -1; + + memcpy (section->sectname, buf, 16); + section->sectname[16] = '\0'; + memcpy (section->segname, buf + 16, 16); + section->segname[16] = '\0'; + section->addr = bfd_h_get_32 (abfd, buf + 32); + section->size = bfd_h_get_32 (abfd, buf + 36); + section->offset = bfd_h_get_32 (abfd, buf + 40); + section->align = bfd_h_get_32 (abfd, buf + 44); + section->reloff = bfd_h_get_32 (abfd, buf + 48); + section->nreloc = bfd_h_get_32 (abfd, buf + 52); + section->flags = bfd_h_get_32 (abfd, buf + 56); + section->reserved1 = bfd_h_get_32 (abfd, buf + 60); + section->reserved2 = bfd_h_get_32 (abfd, buf + 64); + section->bfdsection = bfd_mach_o_make_bfd_section (abfd, section); + + if (section->bfdsection == NULL) + return -1; + + return 0; +} + +static int +bfd_mach_o_scan_write_section (abfd, section, offset) + bfd *abfd; + bfd_mach_o_section *section; + bfd_vma offset; +{ + unsigned char buf[68]; + + memcpy (buf, section->sectname, 16); + memcpy (buf + 16, section->segname, 16); + bfd_h_put_32 (abfd, section->addr, buf + 32); + bfd_h_put_32 (abfd, section->size, buf + 36); + bfd_h_put_32 (abfd, section->offset, buf + 40); + bfd_h_put_32 (abfd, section->align, buf + 44); + bfd_h_put_32 (abfd, section->reloff, buf + 48); + bfd_h_put_32 (abfd, section->nreloc, buf + 52); + bfd_h_put_32 (abfd, section->flags, buf + 56); + /* bfd_h_put_32 (abfd, section->reserved1, buf + 60); */ + /* bfd_h_put_32 (abfd, section->reserved2, buf + 64); */ + + bfd_seek (abfd, offset, SEEK_SET); + if (bfd_bwrite ((PTR) buf, 68, abfd) != 68) + return -1; + + return 0; +} + +static int +bfd_mach_o_scan_write_symtab_symbols (abfd, command) + bfd *abfd; + bfd_mach_o_load_command *command; +{ + bfd_mach_o_symtab_command *sym = &command->command.symtab; + asymbol *s = NULL; + unsigned long i; + + for (i = 0; i < sym->nsyms; i++) + { + unsigned char buf[12]; + bfd_vma symoff = sym->symoff + (i * 12); + unsigned char ntype = 0; + unsigned char nsect = 0; + short ndesc = 0; + + s = &sym->symbols[i]; + + /* Don't set this from the symbol information; use stored values. */ +#if 0 + if (s->flags & BSF_GLOBAL) + ntype |= N_EXT; + if (s->flags & BSF_DEBUGGING) + ntype |= N_STAB; + + if (s->section == bfd_und_section_ptr) + ntype |= N_UNDF; + else if (s->section == bfd_abs_section_ptr) + ntype |= N_ABS; + else + ntype |= N_SECT; +#endif + + /* Instead just set from the stored values. */ + ntype = (s->udata.i >> 24) & 0xff; + nsect = (s->udata.i >> 16) & 0xff; + ndesc = s->udata.i & 0xffff; + + bfd_h_put_32 (abfd, s->name - sym->strtab, buf); + bfd_h_put_8 (abfd, ntype, buf + 4); + bfd_h_put_8 (abfd, nsect, buf + 5); + bfd_h_put_16 (abfd, ndesc, buf + 6); + bfd_h_put_32 (abfd, s->section->vma + s->value, buf + 8); + + bfd_seek (abfd, symoff, SEEK_SET); + if (bfd_bwrite ((PTR) buf, 12, abfd) != 12) + { + fprintf (stderr, "bfd_mach_o_scan_write_symtab_symbols: unable to write %d bytes at %lu\n", + 12, (unsigned long) symoff); + return -1; + } + } + + return 0; +} + +int +bfd_mach_o_scan_read_symtab_symbol (abfd, sym, s, i) + bfd *abfd; + bfd_mach_o_symtab_command *sym; + asymbol *s; + unsigned long i; +{ + bfd_mach_o_data_struct *mdata = abfd->tdata.mach_o_data; + bfd_vma symoff = sym->symoff + (i * 12); + unsigned char buf[12]; + unsigned char type = -1; + unsigned char section = -1; + short desc = -1; + unsigned long value = -1; + unsigned long stroff = -1; + unsigned int symtype = -1; + + BFD_ASSERT (sym->strtab != NULL); + + bfd_seek (abfd, symoff, SEEK_SET); + if (bfd_bread ((PTR) buf, 12, abfd) != 12) + { + fprintf (stderr, "bfd_mach_o_scan_read_symtab_symbol: unable to read %d bytes at %lu\n", + 12, (unsigned long) symoff); + return -1; + } + + stroff = bfd_h_get_32 (abfd, buf); + type = bfd_h_get_8 (abfd, buf + 4); + symtype = (type & 0x0e); + section = bfd_h_get_8 (abfd, buf + 5) - 1; + desc = bfd_h_get_16 (abfd, buf + 6); + value = bfd_h_get_32 (abfd, buf + 8); + + if (stroff >= sym->strsize) + { + fprintf (stderr, "bfd_mach_o_scan_read_symtab_symbol: symbol name out of range (%lu >= %lu)\n", + (unsigned long) stroff, (unsigned long) sym->strsize); + return -1; + } + + s->the_bfd = abfd; + s->name = sym->strtab + stroff; + s->value = value; + s->udata.i = (type << 24) | (section << 16) | desc; + s->flags = 0x0; + + if (type & BFD_MACH_O_N_STAB) + { + s->flags |= BSF_DEBUGGING; + s->section = bfd_und_section_ptr; + } + else + { + if (type & BFD_MACH_O_N_PEXT) + { + type &= ~BFD_MACH_O_N_PEXT; + s->flags |= BSF_GLOBAL; + } + + if (type & BFD_MACH_O_N_EXT) + { + type &= ~BFD_MACH_O_N_EXT; + s->flags |= BSF_GLOBAL; + } + + switch (symtype) + { + case BFD_MACH_O_N_UNDF: + s->section = bfd_und_section_ptr; + break; + case BFD_MACH_O_N_PBUD: + s->section = bfd_und_section_ptr; + break; + case BFD_MACH_O_N_ABS: + s->section = bfd_abs_section_ptr; + break; + case BFD_MACH_O_N_SECT: + if ((section > 0) && (section <= mdata->nsects)) + { + s->section = mdata->sections[section - 1]->bfdsection; + s->value = s->value - mdata->sections[section - 1]->addr; + } + else + { + /* Mach-O uses 0 to mean "no section"; not an error. */ + if (section != 0) + { + fprintf (stderr, "bfd_mach_o_scan_read_symtab_symbol: " + "symbol \"%s\" specified invalid section %d (max %lu): setting to undefined\n", + s->name, section, mdata->nsects); + } + s->section = bfd_und_section_ptr; + } + break; + case BFD_MACH_O_N_INDR: + fprintf (stderr, "bfd_mach_o_scan_read_symtab_symbol: " + "symbol \"%s\" is unsupported 'indirect' reference: setting to undefined\n", + s->name); + s->section = bfd_und_section_ptr; + break; + default: + fprintf (stderr, "bfd_mach_o_scan_read_symtab_symbol: " + "symbol \"%s\" specified invalid type field 0x%x: setting to undefined\n", + s->name, symtype); + s->section = bfd_und_section_ptr; + break; + } + } + + return 0; +} + +int +bfd_mach_o_scan_read_symtab_strtab (abfd, sym) + bfd *abfd; + bfd_mach_o_symtab_command *sym; +{ + BFD_ASSERT (sym->strtab == NULL); + + if (abfd->flags & BFD_IN_MEMORY) + { + struct bfd_in_memory *b; + + b = (struct bfd_in_memory *) abfd->iostream; + + if ((sym->stroff + sym->strsize) > b->size) + { + bfd_set_error (bfd_error_file_truncated); + return -1; + } + sym->strtab = b->buffer + sym->stroff; + return 0; + } + + sym->strtab = bfd_alloc (abfd, sym->strsize); + if (sym->strtab == NULL) + return -1; + + bfd_seek (abfd, sym->stroff, SEEK_SET); + if (bfd_bread ((PTR) sym->strtab, sym->strsize, abfd) != sym->strsize) + { + fprintf (stderr, "bfd_mach_o_scan_read_symtab_strtab: unable to read %lu bytes at %lu\n", + sym->strsize, sym->stroff); + return -1; + } + + return 0; +} + +int +bfd_mach_o_scan_read_symtab_symbols (abfd, sym) + bfd *abfd; + bfd_mach_o_symtab_command *sym; +{ + unsigned long i; + int ret; + + BFD_ASSERT (sym->symbols == NULL); + sym->symbols = bfd_alloc (abfd, sym->nsyms * sizeof (asymbol)); + + if (sym->symbols == NULL) + { + fprintf (stderr, "bfd_mach_o_scan_read_symtab_symbols: unable to allocate memory for symbols\n"); + return -1; + } + + ret = bfd_mach_o_scan_read_symtab_strtab (abfd, sym); + if (ret != 0) + return ret; + + for (i = 0; i < sym->nsyms; i++) + { + ret = bfd_mach_o_scan_read_symtab_symbol (abfd, sym, &sym->symbols[i], i); + if (ret != 0) + return ret; + } + + return 0; +} + +int +bfd_mach_o_scan_read_dysymtab_symbol (abfd, dysym, sym, s, i) + bfd *abfd; + bfd_mach_o_dysymtab_command *dysym; + bfd_mach_o_symtab_command *sym; + asymbol *s; + unsigned long i; +{ + unsigned long isymoff = dysym->indirectsymoff + (i * 4); + unsigned long symindex; + unsigned char buf[4]; + + BFD_ASSERT (i < dysym->nindirectsyms); + + bfd_seek (abfd, isymoff, SEEK_SET); + if (bfd_bread ((PTR) buf, 4, abfd) != 4) + { + fprintf (stderr, "bfd_mach_o_scan_read_dysymtab_symbol: unable to read %lu bytes at %lu\n", + (unsigned long) 4, isymoff); + return -1; + } + symindex = bfd_h_get_32 (abfd, buf); + + return bfd_mach_o_scan_read_symtab_symbol (abfd, sym, s, symindex); +} + +static const char * +bfd_mach_o_i386_flavour_string (flavour) + unsigned int flavour; +{ + switch ((int) flavour) + { + case BFD_MACH_O_i386_NEW_THREAD_STATE: return "i386_NEW_THREAD_STATE"; + case BFD_MACH_O_i386_FLOAT_STATE: return "i386_FLOAT_STATE"; + case BFD_MACH_O_i386_ISA_PORT_MAP_STATE: return "i386_ISA_PORT_MAP_STATE"; + case BFD_MACH_O_i386_V86_ASSIST_STATE: return "i386_V86_ASSIST_STATE"; + case BFD_MACH_O_i386_REGS_SEGS_STATE: return "i386_REGS_SEGS_STATE"; + case BFD_MACH_O_i386_THREAD_SYSCALL_STATE: return "i386_THREAD_SYSCALL_STATE"; + case BFD_MACH_O_i386_THREAD_STATE_NONE: return "i386_THREAD_STATE_NONE"; + case BFD_MACH_O_i386_SAVED_STATE: return "i386_SAVED_STATE"; + case BFD_MACH_O_i386_THREAD_STATE: return "i386_THREAD_STATE"; + case BFD_MACH_O_i386_THREAD_FPSTATE: return "i386_THREAD_FPSTATE"; + case BFD_MACH_O_i386_THREAD_EXCEPTSTATE: return "i386_THREAD_EXCEPTSTATE"; + case BFD_MACH_O_i386_THREAD_CTHREADSTATE: return "i386_THREAD_CTHREADSTATE"; + default: return "UNKNOWN"; + } +} + +static const char * +bfd_mach_o_ppc_flavour_string (flavour) + unsigned int flavour; +{ + switch ((int) flavour) + { + case BFD_MACH_O_PPC_THREAD_STATE: return "PPC_THREAD_STATE"; + case BFD_MACH_O_PPC_FLOAT_STATE: return "PPC_FLOAT_STATE"; + case BFD_MACH_O_PPC_EXCEPTION_STATE: return "PPC_EXCEPTION_STATE"; + case BFD_MACH_O_PPC_VECTOR_STATE: return "PPC_VECTOR_STATE"; + default: return "UNKNOWN"; + } +} + +static int +bfd_mach_o_scan_write_thread (abfd, command) + bfd *abfd; + bfd_mach_o_load_command *command; +{ + bfd_mach_o_thread_command *cmd = &command->command.thread; + unsigned int i; + unsigned char buf[8]; + bfd_vma offset; + unsigned int nflavours; + + BFD_ASSERT ((command->type == BFD_MACH_O_LC_THREAD) + || (command->type == BFD_MACH_O_LC_UNIXTHREAD)); + + offset = 8; + nflavours = 0; + for (i = 0; i < cmd->nflavours; i++) + { + BFD_ASSERT ((cmd->flavours[i].size % 4) == 0); + BFD_ASSERT (cmd->flavours[i].offset == (command->offset + offset + 8)); + + bfd_h_put_32 (abfd, cmd->flavours[i].flavour, buf); + bfd_h_put_32 (abfd, (cmd->flavours[i].size / 4), buf + 4); + + bfd_seek (abfd, command->offset + offset, SEEK_SET); + if (bfd_bwrite ((PTR) buf, 8, abfd) != 8) + return -1; + + offset += cmd->flavours[i].size + 8; + } + + return 0; +} + +static int +bfd_mach_o_scan_read_dylinker (abfd, command) + bfd *abfd; + bfd_mach_o_load_command *command; +{ + bfd_mach_o_dylinker_command *cmd = &command->command.dylinker; + unsigned char buf[4]; + unsigned int nameoff; + asection *bfdsec; + char *sname; + const char *prefix; + + BFD_ASSERT ((command->type == BFD_MACH_O_LC_ID_DYLINKER) + || (command->type == BFD_MACH_O_LC_LOAD_DYLINKER)); + + bfd_seek (abfd, command->offset + 8, SEEK_SET); + if (bfd_bread ((PTR) buf, 4, abfd) != 4) + return -1; + + nameoff = bfd_h_get_32 (abfd, buf + 0); + + cmd->name_offset = command->offset + nameoff; + cmd->name_len = command->len - nameoff; + + if (command->type == BFD_MACH_O_LC_LOAD_DYLINKER) + prefix = "LC_LOAD_DYLINKER"; + else if (command->type == BFD_MACH_O_LC_ID_DYLINKER) + prefix = "LC_ID_DYLINKER"; + else + abort (); + + sname = (char *) bfd_alloc (abfd, strlen (prefix) + 1); + if (sname == NULL) + return -1; + strcpy (sname, prefix); + + bfdsec = bfd_make_section_anyway (abfd, sname); + if (bfdsec == NULL) + return -1; + + bfdsec->vma = 0; + bfdsec->lma = 0; + bfdsec->_raw_size = command->len - 8; + bfdsec->filepos = command->offset + 8; + bfdsec->alignment_power = 0; + bfdsec->flags = SEC_HAS_CONTENTS; + + cmd->section = bfdsec; + + return 0; +} + +static int +bfd_mach_o_scan_read_dylib (abfd, command) + bfd *abfd; + bfd_mach_o_load_command *command; +{ + bfd_mach_o_dylib_command *cmd = &command->command.dylib; + unsigned char buf[16]; + unsigned int nameoff; + asection *bfdsec; + char *sname; + const char *prefix; + + BFD_ASSERT ((command->type == BFD_MACH_O_LC_ID_DYLIB) + || (command->type == BFD_MACH_O_LC_LOAD_DYLIB) + || (command->type == BFD_MACH_O_LC_LOAD_WEAK_DYLIB)); + + bfd_seek (abfd, command->offset + 8, SEEK_SET); + if (bfd_bread ((PTR) buf, 16, abfd) != 16) + return -1; + + nameoff = bfd_h_get_32 (abfd, buf + 0); + cmd->timestamp = bfd_h_get_32 (abfd, buf + 4); + cmd->current_version = bfd_h_get_32 (abfd, buf + 8); + cmd->compatibility_version = bfd_h_get_32 (abfd, buf + 12); + + cmd->name_offset = command->offset + nameoff; + cmd->name_len = command->len - nameoff; + + if (command->type == BFD_MACH_O_LC_LOAD_DYLIB) + prefix = "LC_LOAD_DYLIB"; + else if (command->type == BFD_MACH_O_LC_LOAD_WEAK_DYLIB) + prefix = "LC_LOAD_WEAK_DYLIB"; + else if (command->type == BFD_MACH_O_LC_ID_DYLIB) + prefix = "LC_ID_DYLIB"; + else + abort (); + + sname = (char *) bfd_alloc (abfd, strlen (prefix) + 1); + if (sname == NULL) + return -1; + strcpy (sname, prefix); + + bfdsec = bfd_make_section_anyway (abfd, sname); + if (bfdsec == NULL) + return -1; + + bfdsec->vma = 0; + bfdsec->lma = 0; + bfdsec->_raw_size = command->len - 8; + bfdsec->filepos = command->offset + 8; + bfdsec->alignment_power = 0; + bfdsec->flags = SEC_HAS_CONTENTS; + + cmd->section = bfdsec; + + return 0; +} + +static int +bfd_mach_o_scan_read_prebound_dylib (abfd, command) + bfd *abfd ATTRIBUTE_UNUSED; + bfd_mach_o_load_command *command ATTRIBUTE_UNUSED; +{ + /* bfd_mach_o_prebound_dylib_command *cmd = &command->command.prebound_dylib; */ + + BFD_ASSERT (command->type == BFD_MACH_O_LC_PREBOUND_DYLIB); + return 0; +} + +static int +bfd_mach_o_scan_read_thread (abfd, command) + bfd *abfd; + bfd_mach_o_load_command *command; +{ + bfd_mach_o_data_struct *mdata = NULL; + bfd_mach_o_thread_command *cmd = &command->command.thread; + unsigned char buf[8]; + bfd_vma offset; + unsigned int nflavours; + unsigned int i; + + BFD_ASSERT ((command->type == BFD_MACH_O_LC_THREAD) + || (command->type == BFD_MACH_O_LC_UNIXTHREAD)); + + BFD_ASSERT (bfd_mach_o_valid (abfd)); + mdata = abfd->tdata.mach_o_data; + + offset = 8; + nflavours = 0; + while (offset != command->len) + { + if (offset >= command->len) + return -1; + + bfd_seek (abfd, command->offset + offset, SEEK_SET); + + if (bfd_bread ((PTR) buf, 8, abfd) != 8) + return -1; + + offset += 8 + bfd_h_get_32 (abfd, buf + 4) * 4; + nflavours++; + } + + cmd->flavours = + ((bfd_mach_o_thread_flavour *) + bfd_alloc (abfd, nflavours * sizeof (bfd_mach_o_thread_flavour))); + if (cmd->flavours == NULL) + return -1; + cmd->nflavours = nflavours; + + offset = 8; + nflavours = 0; + while (offset != command->len) + { + if (offset >= command->len) + return -1; + + if (nflavours >= cmd->nflavours) + return -1; + + bfd_seek (abfd, command->offset + offset, SEEK_SET); + + if (bfd_bread ((PTR) buf, 8, abfd) != 8) + return -1; + + cmd->flavours[nflavours].flavour = bfd_h_get_32 (abfd, buf); + cmd->flavours[nflavours].offset = command->offset + offset + 8; + cmd->flavours[nflavours].size = bfd_h_get_32 (abfd, buf + 4) * 4; + offset += cmd->flavours[nflavours].size + 8; + nflavours++; + } + + for (i = 0; i < nflavours; i++) + { + asection *bfdsec; + unsigned int snamelen; + char *sname; + const char *flavourstr; + const char *prefix = "LC_THREAD"; + unsigned int j = 0; + + switch (mdata->header.cputype) + { + case BFD_MACH_O_CPU_TYPE_POWERPC: + flavourstr = bfd_mach_o_ppc_flavour_string (cmd->flavours[i].flavour); + break; + case BFD_MACH_O_CPU_TYPE_I386: + flavourstr = bfd_mach_o_i386_flavour_string (cmd->flavours[i].flavour); + break; + default: + flavourstr = "UNKNOWN_ARCHITECTURE"; + break; + } + + snamelen = strlen (prefix) + 1 + 20 + 1 + strlen (flavourstr) + 1; + sname = (char *) bfd_alloc (abfd, snamelen); + if (sname == NULL) + return -1; + + for (;;) + { + sprintf (sname, "%s.%s.%u", prefix, flavourstr, j); + if (bfd_get_section_by_name (abfd, sname) == NULL) + break; + j++; + } + + bfdsec = bfd_make_section (abfd, sname); + + bfdsec->vma = 0; + bfdsec->lma = 0; + bfdsec->_raw_size = cmd->flavours[i].size; + bfdsec->filepos = cmd->flavours[i].offset; + bfdsec->alignment_power = 0x0; + bfdsec->flags = SEC_HAS_CONTENTS; + + cmd->section = bfdsec; + } + + return 0; +} + +static int +bfd_mach_o_scan_write_symtab (abfd, command) + bfd *abfd; + bfd_mach_o_load_command *command; +{ + bfd_mach_o_symtab_command *seg = &command->command.symtab; + unsigned char buf[16]; + + BFD_ASSERT (command->type == BFD_MACH_O_LC_SYMTAB); + + bfd_h_put_32 (abfd, seg->symoff, buf); + bfd_h_put_32 (abfd, seg->nsyms, buf + 4); + bfd_h_put_32 (abfd, seg->stroff, buf + 8); + bfd_h_put_32 (abfd, seg->strsize, buf + 12); + + bfd_seek (abfd, command->offset + 8, SEEK_SET); + if (bfd_bwrite ((PTR) buf, 16, abfd) != 16) + return -1; + + if (bfd_mach_o_scan_write_symtab_symbols (abfd, command) != 0) + return -1; + + return 0; +} + +static int +bfd_mach_o_scan_read_dysymtab (abfd, command) + bfd *abfd; + bfd_mach_o_load_command *command; +{ + bfd_mach_o_dysymtab_command *seg = &command->command.dysymtab; + unsigned char buf[72]; + + BFD_ASSERT (command->type == BFD_MACH_O_LC_DYSYMTAB); + + bfd_seek (abfd, command->offset + 8, SEEK_SET); + if (bfd_bread ((PTR) buf, 72, abfd) != 72) + return -1; + + seg->ilocalsym = bfd_h_get_32 (abfd, buf + 0); + seg->nlocalsym = bfd_h_get_32 (abfd, buf + 4); + seg->iextdefsym = bfd_h_get_32 (abfd, buf + 8); + seg->nextdefsym = bfd_h_get_32 (abfd, buf + 12); + seg->iundefsym = bfd_h_get_32 (abfd, buf + 16); + seg->nundefsym = bfd_h_get_32 (abfd, buf + 20); + seg->tocoff = bfd_h_get_32 (abfd, buf + 24); + seg->ntoc = bfd_h_get_32 (abfd, buf + 28); + seg->modtaboff = bfd_h_get_32 (abfd, buf + 32); + seg->nmodtab = bfd_h_get_32 (abfd, buf + 36); + seg->extrefsymoff = bfd_h_get_32 (abfd, buf + 40); + seg->nextrefsyms = bfd_h_get_32 (abfd, buf + 44); + seg->indirectsymoff = bfd_h_get_32 (abfd, buf + 48); + seg->nindirectsyms = bfd_h_get_32 (abfd, buf + 52); + seg->extreloff = bfd_h_get_32 (abfd, buf + 56); + seg->nextrel = bfd_h_get_32 (abfd, buf + 60); + seg->locreloff = bfd_h_get_32 (abfd, buf + 64); + seg->nlocrel = bfd_h_get_32 (abfd, buf + 68); + + return 0; +} + +static int +bfd_mach_o_scan_read_symtab (abfd, command) + bfd *abfd; + bfd_mach_o_load_command *command; +{ + bfd_mach_o_symtab_command *seg = &command->command.symtab; + unsigned char buf[16]; + asection *bfdsec; + char *sname; + const char *prefix = "LC_SYMTAB.stabs"; + + BFD_ASSERT (command->type == BFD_MACH_O_LC_SYMTAB); + + bfd_seek (abfd, command->offset + 8, SEEK_SET); + if (bfd_bread ((PTR) buf, 16, abfd) != 16) + return -1; + + seg->symoff = bfd_h_get_32 (abfd, buf); + seg->nsyms = bfd_h_get_32 (abfd, buf + 4); + seg->stroff = bfd_h_get_32 (abfd, buf + 8); + seg->strsize = bfd_h_get_32 (abfd, buf + 12); + seg->symbols = NULL; + seg->strtab = NULL; + + sname = (char *) bfd_alloc (abfd, strlen (prefix) + 1); + if (sname == NULL) + return -1; + strcpy (sname, prefix); + + bfdsec = bfd_make_section_anyway (abfd, sname); + if (bfdsec == NULL) + return -1; + + bfdsec->vma = 0; + bfdsec->lma = 0; + bfdsec->_raw_size = seg->nsyms * 12; + bfdsec->filepos = seg->symoff; + bfdsec->alignment_power = 0; + bfdsec->flags = SEC_HAS_CONTENTS; + + seg->stabs_segment = bfdsec; + + prefix = "LC_SYMTAB.stabstr"; + sname = (char *) bfd_alloc (abfd, strlen (prefix) + 1); + if (sname == NULL) + return -1; + strcpy (sname, prefix); + + bfdsec = bfd_make_section_anyway (abfd, sname); + if (bfdsec == NULL) + return -1; + + bfdsec->vma = 0; + bfdsec->lma = 0; + bfdsec->_raw_size = seg->strsize; + bfdsec->filepos = seg->stroff; + bfdsec->alignment_power = 0; + bfdsec->flags = SEC_HAS_CONTENTS; + + seg->stabstr_segment = bfdsec; + + return 0; +} + +static int +bfd_mach_o_scan_read_segment (abfd, command) + bfd *abfd; + bfd_mach_o_load_command *command; +{ + unsigned char buf[48]; + bfd_mach_o_segment_command *seg = &command->command.segment; + unsigned long i; + asection *bfdsec; + char *sname; + const char *prefix = "LC_SEGMENT"; + unsigned int snamelen; + + BFD_ASSERT (command->type == BFD_MACH_O_LC_SEGMENT); + + bfd_seek (abfd, command->offset + 8, SEEK_SET); + if (bfd_bread ((PTR) buf, 48, abfd) != 48) + return -1; + + memcpy (seg->segname, buf, 16); + seg->vmaddr = bfd_h_get_32 (abfd, buf + 16); + seg->vmsize = bfd_h_get_32 (abfd, buf + 20); + seg->fileoff = bfd_h_get_32 (abfd, buf + 24); + seg->filesize = bfd_h_get_32 (abfd, buf + 28); + /* seg->maxprot = bfd_h_get_32 (abfd, buf + 32); */ + /* seg->initprot = bfd_h_get_32 (abfd, buf + 36); */ + seg->nsects = bfd_h_get_32 (abfd, buf + 40); + seg->flags = bfd_h_get_32 (abfd, buf + 44); + + snamelen = strlen (prefix) + 1 + strlen (seg->segname) + 1; + sname = (char *) bfd_alloc (abfd, snamelen); + if (sname == NULL) + return -1; + sprintf (sname, "%s.%s", prefix, seg->segname); + + bfdsec = bfd_make_section_anyway (abfd, sname); + if (bfdsec == NULL) + return -1; + + bfdsec->vma = seg->vmaddr; + bfdsec->lma = seg->vmaddr; + bfdsec->_raw_size = seg->filesize; + bfdsec->filepos = seg->fileoff; + bfdsec->alignment_power = 0x0; + bfdsec->flags = SEC_HAS_CONTENTS | SEC_LOAD | SEC_ALLOC | SEC_CODE; + + seg->segment = bfdsec; + + if (seg->nsects != 0) + { + seg->sections = + ((bfd_mach_o_section *) + bfd_alloc (abfd, seg->nsects * sizeof (bfd_mach_o_section))); + if (seg->sections == NULL) + return -1; + + for (i = 0; i < seg->nsects; i++) + { + bfd_vma segoff = command->offset + 48 + 8 + (i * 68); + + if (bfd_mach_o_scan_read_section (abfd, &seg->sections[i], + segoff) != 0) + return -1; + } + } + + return 0; +} + +static int +bfd_mach_o_scan_write_segment (abfd, command) + bfd *abfd; + bfd_mach_o_load_command *command; +{ + unsigned char buf[48]; + bfd_mach_o_segment_command *seg = &command->command.segment; + unsigned long i; + + BFD_ASSERT (command->type == BFD_MACH_O_LC_SEGMENT); + + memcpy (buf, seg->segname, 16); + bfd_h_put_32 (abfd, seg->vmaddr, buf + 16); + bfd_h_put_32 (abfd, seg->vmsize, buf + 20); + bfd_h_put_32 (abfd, seg->fileoff, buf + 24); + bfd_h_put_32 (abfd, seg->filesize, buf + 28); + bfd_h_put_32 (abfd, 0 /* seg->maxprot */, buf + 32); + bfd_h_put_32 (abfd, 0 /* seg->initprot */, buf + 36); + bfd_h_put_32 (abfd, seg->nsects, buf + 40); + bfd_h_put_32 (abfd, seg->flags, buf + 44); + + bfd_seek (abfd, command->offset + 8, SEEK_SET); + if (bfd_bwrite ((PTR) buf, 48, abfd) != 48) + return -1; + + { + char buf[1024]; + bfd_vma nbytes = seg->filesize; + bfd_vma curoff = seg->fileoff; + + while (nbytes > 0) + { + bfd_vma thisread = nbytes; + + if (thisread > 1024) + thisread = 1024; + + bfd_seek (abfd, curoff, SEEK_SET); + if (bfd_bread ((PTR) buf, thisread, abfd) != thisread) + return -1; + + bfd_seek (abfd, curoff, SEEK_SET); + if (bfd_bwrite ((PTR) buf, thisread, abfd) != thisread) + return -1; + + nbytes -= thisread; + curoff += thisread; + } + } + + for (i = 0; i < seg->nsects; i++) + { + bfd_vma segoff = command->offset + 48 + 8 + (i * 68); + + if (bfd_mach_o_scan_write_section (abfd, &seg->sections[i], segoff) != 0) + return -1; + } + + return 0; +} + +static int +bfd_mach_o_scan_read_command (abfd, command) + bfd *abfd; + bfd_mach_o_load_command *command; +{ + unsigned char buf[8]; + + bfd_seek (abfd, command->offset, SEEK_SET); + if (bfd_bread ((PTR) buf, 8, abfd) != 8) + return -1; + + command->type = (bfd_h_get_32 (abfd, buf) & ~BFD_MACH_O_LC_REQ_DYLD); + command->type_required = (bfd_h_get_32 (abfd, buf) & BFD_MACH_O_LC_REQ_DYLD + ? 1 : 0); + command->len = bfd_h_get_32 (abfd, buf + 4); + + switch (command->type) + { + case BFD_MACH_O_LC_SEGMENT: + if (bfd_mach_o_scan_read_segment (abfd, command) != 0) + return -1; + break; + case BFD_MACH_O_LC_SYMTAB: + if (bfd_mach_o_scan_read_symtab (abfd, command) != 0) + return -1; + break; + case BFD_MACH_O_LC_SYMSEG: + break; + case BFD_MACH_O_LC_THREAD: + case BFD_MACH_O_LC_UNIXTHREAD: + if (bfd_mach_o_scan_read_thread (abfd, command) != 0) + return -1; + break; + case BFD_MACH_O_LC_LOAD_DYLINKER: + case BFD_MACH_O_LC_ID_DYLINKER: + if (bfd_mach_o_scan_read_dylinker (abfd, command) != 0) + return -1; + break; + case BFD_MACH_O_LC_LOAD_DYLIB: + case BFD_MACH_O_LC_ID_DYLIB: + case BFD_MACH_O_LC_LOAD_WEAK_DYLIB: + if (bfd_mach_o_scan_read_dylib (abfd, command) != 0) + return -1; + break; + case BFD_MACH_O_LC_PREBOUND_DYLIB: + if (bfd_mach_o_scan_read_prebound_dylib (abfd, command) != 0) + return -1; + break; + case BFD_MACH_O_LC_LOADFVMLIB: + case BFD_MACH_O_LC_IDFVMLIB: + case BFD_MACH_O_LC_IDENT: + case BFD_MACH_O_LC_FVMFILE: + case BFD_MACH_O_LC_PREPAGE: + case BFD_MACH_O_LC_ROUTINES: + case BFD_MACH_O_LC_SUB_FRAMEWORK: + break; + case BFD_MACH_O_LC_DYSYMTAB: + if (bfd_mach_o_scan_read_dysymtab (abfd, command) != 0) + return -1; + break; + case BFD_MACH_O_LC_SUB_UMBRELLA: + case BFD_MACH_O_LC_SUB_CLIENT: + case BFD_MACH_O_LC_SUB_LIBRARY: + case BFD_MACH_O_LC_TWOLEVEL_HINTS: + case BFD_MACH_O_LC_PREBIND_CKSUM: + break; + default: + fprintf (stderr, "unable to read unknown load command 0x%lx\n", + (unsigned long) command->type); + break; + } + + return 0; +} + +static void +bfd_mach_o_flatten_sections (abfd) + bfd *abfd; +{ + bfd_mach_o_data_struct *mdata = abfd->tdata.mach_o_data; + long csect = 0; + unsigned long i, j; + + mdata->nsects = 0; + + for (i = 0; i < mdata->header.ncmds; i++) + { + if (mdata->commands[i].type == BFD_MACH_O_LC_SEGMENT) + { + bfd_mach_o_segment_command *seg; + + seg = &mdata->commands[i].command.segment; + mdata->nsects += seg->nsects; + } + } + + mdata->sections = bfd_alloc (abfd, + mdata->nsects * sizeof (bfd_mach_o_section *)); + csect = 0; + + for (i = 0; i < mdata->header.ncmds; i++) + { + if (mdata->commands[i].type == BFD_MACH_O_LC_SEGMENT) + { + bfd_mach_o_segment_command *seg; + + seg = &mdata->commands[i].command.segment; + BFD_ASSERT (csect + seg->nsects <= mdata->nsects); + + for (j = 0; j < seg->nsects; j++) + mdata->sections[csect++] = &seg->sections[j]; + } + } +} + +int +bfd_mach_o_scan_start_address (abfd) + bfd *abfd; +{ + bfd_mach_o_data_struct *mdata = abfd->tdata.mach_o_data; + bfd_mach_o_thread_command *cmd = NULL; + unsigned long i; + + for (i = 0; i < mdata->header.ncmds; i++) + { + if ((mdata->commands[i].type == BFD_MACH_O_LC_THREAD) || + (mdata->commands[i].type == BFD_MACH_O_LC_UNIXTHREAD)) + { + if (cmd == NULL) + cmd = &mdata->commands[i].command.thread; + else + return 0; + } + } + + if (cmd == NULL) + return 0; + + for (i = 0; i < cmd->nflavours; i++) + { + if ((mdata->header.cputype == BFD_MACH_O_CPU_TYPE_I386) + && (cmd->flavours[i].flavour + == (unsigned long) BFD_MACH_O_i386_THREAD_STATE)) + { + unsigned char buf[4]; + + bfd_seek (abfd, cmd->flavours[i].offset + 40, SEEK_SET); + + if (bfd_bread (buf, 4, abfd) != 4) + return -1; + + abfd->start_address = bfd_h_get_32 (abfd, buf); + } + else if ((mdata->header.cputype == BFD_MACH_O_CPU_TYPE_POWERPC) + && (cmd->flavours[i].flavour == BFD_MACH_O_PPC_THREAD_STATE)) + { + unsigned char buf[4]; + + bfd_seek (abfd, cmd->flavours[i].offset + 0, SEEK_SET); + + if (bfd_bread (buf, 4, abfd) != 4) + return -1; + + abfd->start_address = bfd_h_get_32 (abfd, buf); + } + } + + return 0; +} + +int +bfd_mach_o_scan (abfd, header, mdata) + bfd *abfd; + bfd_mach_o_header *header; + bfd_mach_o_data_struct *mdata; +{ + unsigned int i; + enum bfd_architecture cputype; + unsigned long cpusubtype; + + mdata->header = *header; + mdata->symbols = NULL; + + abfd->flags = (abfd->xvec->object_flags + | (abfd->flags & (BFD_IN_MEMORY | BFD_IO_FUNCS))); + abfd->tdata.mach_o_data = mdata; + + bfd_mach_o_convert_architecture (header->cputype, header->cpusubtype, + &cputype, &cpusubtype); + if (cputype == bfd_arch_unknown) + { + fprintf (stderr, "bfd_mach_o_scan: unknown architecture 0x%lx/0x%lx\n", + header->cputype, header->cpusubtype); + return -1; + } + + bfd_set_arch_mach (abfd, cputype, cpusubtype); + + if (header->ncmds != 0) + { + mdata->commands = + ((bfd_mach_o_load_command *) + bfd_alloc (abfd, header->ncmds * sizeof (bfd_mach_o_load_command))); + if (mdata->commands == NULL) + return -1; + + for (i = 0; i < header->ncmds; i++) + { + bfd_mach_o_load_command *cur = &mdata->commands[i]; + + if (i == 0) + cur->offset = 28; + else + { + bfd_mach_o_load_command *prev = &mdata->commands[i - 1]; + cur->offset = prev->offset + prev->len; + } + + if (bfd_mach_o_scan_read_command (abfd, cur) < 0) + return -1; + } + } + + if (bfd_mach_o_scan_start_address (abfd) < 0) + { +#if 0 + fprintf (stderr, "bfd_mach_o_scan: unable to scan start address: %s\n", + bfd_errmsg (bfd_get_error ())); + abfd->tdata.mach_o_data = NULL; + return -1; +#endif + } + + bfd_mach_o_flatten_sections (abfd); + + return 0; +} + +bfd_boolean +bfd_mach_o_mkobject (abfd) + bfd *abfd; +{ + bfd_mach_o_data_struct *mdata = NULL; + + mdata = ((bfd_mach_o_data_struct *) + bfd_alloc (abfd, sizeof (bfd_mach_o_data_struct))); + if (mdata == NULL) + return FALSE; + abfd->tdata.mach_o_data = mdata; + + mdata->header.magic = 0; + mdata->header.cputype = 0; + mdata->header.cpusubtype = 0; + mdata->header.filetype = 0; + mdata->header.ncmds = 0; + mdata->header.sizeofcmds = 0; + mdata->header.flags = 0; + mdata->header.byteorder = BFD_ENDIAN_UNKNOWN; + mdata->commands = NULL; + mdata->nsymbols = 0; + mdata->symbols = NULL; + mdata->nsects = 0; + mdata->sections = NULL; + mdata->ibfd = NULL; + + return TRUE; +} + +const bfd_target * +bfd_mach_o_object_p (abfd) + bfd *abfd; +{ + struct bfd_preserve preserve; + bfd_mach_o_header header; + + preserve.marker = NULL; + if (bfd_mach_o_read_header (abfd, &header) != 0) + goto wrong; + + if (! (header.byteorder == BFD_ENDIAN_BIG + || header.byteorder == BFD_ENDIAN_LITTLE)) + { + fprintf (stderr, "unknown header byte-order value 0x%lx\n", + (long) header.byteorder); + goto wrong; + } + + if (! ((header.byteorder == BFD_ENDIAN_BIG + && abfd->xvec->byteorder == BFD_ENDIAN_BIG + && abfd->xvec->header_byteorder == BFD_ENDIAN_BIG) + || (header.byteorder == BFD_ENDIAN_LITTLE + && abfd->xvec->byteorder == BFD_ENDIAN_LITTLE + && abfd->xvec->header_byteorder == BFD_ENDIAN_LITTLE))) + goto wrong; + + preserve.marker = bfd_zalloc (abfd, sizeof (bfd_mach_o_data_struct)); + if (preserve.marker == NULL + || !bfd_preserve_save (abfd, &preserve)) + goto fail; + + if (bfd_mach_o_scan (abfd, &header, + (bfd_mach_o_data_struct *) preserve.marker) != 0) + goto wrong; + + bfd_preserve_finish (abfd, &preserve); + return abfd->xvec; + + wrong: + bfd_set_error (bfd_error_wrong_format); + + fail: + if (preserve.marker != NULL) + bfd_preserve_restore (abfd, &preserve); + return NULL; +} + +const bfd_target * +bfd_mach_o_core_p (abfd) + bfd *abfd; +{ + struct bfd_preserve preserve; + bfd_mach_o_header header; + + preserve.marker = NULL; + if (bfd_mach_o_read_header (abfd, &header) != 0) + goto wrong; + + if (! (header.byteorder == BFD_ENDIAN_BIG + || header.byteorder == BFD_ENDIAN_LITTLE)) + { + fprintf (stderr, "unknown header byte-order value 0x%lx\n", + (long) header.byteorder); + abort (); + } + + if (! ((header.byteorder == BFD_ENDIAN_BIG + && abfd->xvec->byteorder == BFD_ENDIAN_BIG + && abfd->xvec->header_byteorder == BFD_ENDIAN_BIG) + || (header.byteorder == BFD_ENDIAN_LITTLE + && abfd->xvec->byteorder == BFD_ENDIAN_LITTLE + && abfd->xvec->header_byteorder == BFD_ENDIAN_LITTLE))) + goto wrong; + + if (header.filetype != BFD_MACH_O_MH_CORE) + goto wrong; + + preserve.marker = bfd_zalloc (abfd, sizeof (bfd_mach_o_data_struct)); + if (preserve.marker == NULL + || !bfd_preserve_save (abfd, &preserve)) + goto fail; + + if (bfd_mach_o_scan (abfd, &header, + (bfd_mach_o_data_struct *) preserve.marker) != 0) + goto wrong; + + bfd_preserve_finish (abfd, &preserve); + return abfd->xvec; + + wrong: + bfd_set_error (bfd_error_wrong_format); + + fail: + if (preserve.marker != NULL) + bfd_preserve_restore (abfd, &preserve); + return NULL; +} + +typedef struct mach_o_fat_archentry +{ + unsigned long cputype; + unsigned long cpusubtype; + unsigned long offset; + unsigned long size; + unsigned long align; + bfd *abfd; +} mach_o_fat_archentry; + +typedef struct mach_o_fat_data_struct +{ + unsigned long magic; + unsigned long nfat_arch; + mach_o_fat_archentry *archentries; +} mach_o_fat_data_struct; + +const bfd_target * +bfd_mach_o_archive_p (abfd) + bfd *abfd; +{ + mach_o_fat_data_struct *adata = NULL; + unsigned char buf[20]; + unsigned long i; + + bfd_seek (abfd, 0, SEEK_SET); + if (bfd_bread ((PTR) buf, 8, abfd) != 8) + goto error; + + adata = (mach_o_fat_data_struct *) + bfd_alloc (abfd, sizeof (mach_o_fat_data_struct)); + if (adata == NULL) + goto error; + + adata->magic = bfd_getb32 (buf); + adata->nfat_arch = bfd_getb32 (buf + 4); + if (adata->magic != 0xcafebabe) + goto error; + + adata->archentries = (mach_o_fat_archentry *) + bfd_alloc (abfd, adata->nfat_arch * sizeof (mach_o_fat_archentry)); + if (adata->archentries == NULL) + goto error; + + for (i = 0; i < adata->nfat_arch; i++) + { + bfd_seek (abfd, 8 + 20 * i, SEEK_SET); + + if (bfd_bread ((PTR) buf, 20, abfd) != 20) + goto error; + adata->archentries[i].cputype = bfd_getb32 (buf); + adata->archentries[i].cpusubtype = bfd_getb32 (buf + 4); + adata->archentries[i].offset = bfd_getb32 (buf + 8); + adata->archentries[i].size = bfd_getb32 (buf + 12); + adata->archentries[i].align = bfd_getb32 (buf + 16); + adata->archentries[i].abfd = NULL; + } + + abfd->tdata.mach_o_fat_data = adata; + return abfd->xvec; + + error: + if (adata != NULL) + bfd_release (abfd, adata); + bfd_set_error (bfd_error_wrong_format); + return NULL; +} + +bfd * +bfd_mach_o_openr_next_archived_file (archive, prev) + bfd *archive; + bfd *prev; +{ + mach_o_fat_data_struct *adata; + mach_o_fat_archentry *entry = NULL; + unsigned long i; + + adata = (mach_o_fat_data_struct *) archive->tdata.mach_o_fat_data; + BFD_ASSERT (adata != NULL); + + /* Find index of previous entry. */ + if (prev == NULL) + i = 0; /* Start at first one. */ + else + { + for (i = 0; i < adata->nfat_arch; i++) + { + if (adata->archentries[i].abfd == prev) + break; + } + + if (i == adata->nfat_arch) + { + /* Not found. */ + bfd_set_error (bfd_error_bad_value); + return NULL; + } + i++; /* Get next entry. */ + } + + if (i >= adata->nfat_arch) + { + bfd_set_error (bfd_error_no_more_archived_files); + return NULL; + } + + entry = &adata->archentries[i]; + if (entry->abfd == NULL) + { + bfd *nbfd = _bfd_new_bfd_contained_in (archive); + char *s = NULL; + + if (nbfd == NULL) + return NULL; + + nbfd->origin = entry->offset; + s = bfd_malloc (strlen (archive->filename) + 1); + if (s == NULL) + return NULL; + strcpy (s, archive->filename); + nbfd->filename = s; + nbfd->iostream = NULL; + entry->abfd = nbfd; + } + + return entry->abfd; +} + +int +bfd_mach_o_lookup_section (abfd, section, mcommand, msection) + bfd *abfd; + asection *section; + bfd_mach_o_load_command **mcommand; + bfd_mach_o_section **msection; +{ + struct mach_o_data_struct *md = abfd->tdata.mach_o_data; + unsigned int i, j, num; + + bfd_mach_o_load_command *ncmd = NULL; + bfd_mach_o_section *nsect = NULL; + + BFD_ASSERT (mcommand != NULL); + BFD_ASSERT (msection != NULL); + + num = 0; + for (i = 0; i < md->header.ncmds; i++) + { + struct bfd_mach_o_load_command *cmd = &md->commands[i]; + struct bfd_mach_o_segment_command *seg = NULL; + + if (cmd->type != BFD_MACH_O_LC_SEGMENT) + continue; + seg = &cmd->command.segment; + + if (seg->segment == section) + { + if (num == 0) + ncmd = cmd; + num++; + } + + for (j = 0; j < seg->nsects; j++) + { + struct bfd_mach_o_section *sect = &seg->sections[j]; + + if (sect->bfdsection == section) + { + if (num == 0) + nsect = sect; + num++; + } + } + } + + *mcommand = ncmd; + *msection = nsect; + return num; +} + +int +bfd_mach_o_lookup_command (abfd, type, mcommand) + bfd *abfd; + bfd_mach_o_load_command_type type; + bfd_mach_o_load_command **mcommand; +{ + struct mach_o_data_struct *md = NULL; + bfd_mach_o_load_command *ncmd = NULL; + unsigned int i, num; + + md = abfd->tdata.mach_o_data; + + BFD_ASSERT (md != NULL); + BFD_ASSERT (mcommand != NULL); + + num = 0; + for (i = 0; i < md->header.ncmds; i++) + { + struct bfd_mach_o_load_command *cmd = &md->commands[i]; + + if (cmd->type != type) + continue; + + if (num == 0) + ncmd = cmd; + num++; + } + + *mcommand = ncmd; + return num; +} + +unsigned long +bfd_mach_o_stack_addr (type) + enum bfd_mach_o_cpu_type type; +{ + switch (type) + { + case BFD_MACH_O_CPU_TYPE_MC680x0: + return 0x04000000; + case BFD_MACH_O_CPU_TYPE_MC88000: + return 0xffffe000; + case BFD_MACH_O_CPU_TYPE_POWERPC: + return 0xc0000000; + case BFD_MACH_O_CPU_TYPE_I386: + return 0xc0000000; + case BFD_MACH_O_CPU_TYPE_SPARC: + return 0xf0000000; + case BFD_MACH_O_CPU_TYPE_I860: + return 0; + case BFD_MACH_O_CPU_TYPE_HPPA: + return 0xc0000000 - 0x04000000; + default: + return 0; + } +} + +int +bfd_mach_o_core_fetch_environment (abfd, rbuf, rlen) + bfd *abfd; + unsigned char **rbuf; + unsigned int *rlen; +{ + bfd_mach_o_data_struct *mdata = abfd->tdata.mach_o_data; + unsigned long stackaddr = bfd_mach_o_stack_addr (mdata->header.cputype); + unsigned int i = 0; + + for (i = 0; i < mdata->header.ncmds; i++) + { + bfd_mach_o_load_command *cur = &mdata->commands[i]; + bfd_mach_o_segment_command *seg = NULL; + + if (cur->type != BFD_MACH_O_LC_SEGMENT) + continue; + + seg = &cur->command.segment; + + if ((seg->vmaddr + seg->vmsize) == stackaddr) + { + unsigned long start = seg->fileoff; + unsigned long end = seg->fileoff + seg->filesize; + unsigned char *buf = bfd_malloc (1024); + unsigned long size = 1024; + + for (;;) + { + bfd_size_type nread = 0; + unsigned long offset; + int found_nonnull = 0; + + if (size > (end - start)) + size = (end - start); + + buf = bfd_realloc (buf, size); + + bfd_seek (abfd, end - size, SEEK_SET); + nread = bfd_bread (buf, size, abfd); + + if (nread != size) + return -1; + + for (offset = 4; offset <= size; offset += 4) + { + unsigned long val; + + val = *((unsigned long *) (buf + size - offset)); + if (! found_nonnull) + { + if (val != 0) + found_nonnull = 1; + } + else if (val == 0x0) + { + unsigned long bottom; + unsigned long top; + + bottom = seg->fileoff + seg->filesize - offset; + top = seg->fileoff + seg->filesize - 4; + *rbuf = bfd_malloc (top - bottom); + *rlen = top - bottom; + + memcpy (*rbuf, buf + size - *rlen, *rlen); + return 0; + } + } + + if (size == (end - start)) + break; + + size *= 2; + } + } + } + + return -1; +} + +char * +bfd_mach_o_core_file_failing_command (abfd) + bfd *abfd; +{ + unsigned char *buf = NULL; + unsigned int len = 0; + int ret = -1; + + ret = bfd_mach_o_core_fetch_environment (abfd, &buf, &len); + if (ret < 0) + return NULL; + + return buf; +} + +int +bfd_mach_o_core_file_failing_signal (abfd) + bfd *abfd ATTRIBUTE_UNUSED; +{ + return 0; +} + +bfd_boolean +bfd_mach_o_core_file_matches_executable_p (core_bfd, exec_bfd) + bfd *core_bfd ATTRIBUTE_UNUSED; + bfd *exec_bfd ATTRIBUTE_UNUSED; +{ + return TRUE; +} + +#define TARGET_NAME mach_o_be_vec +#define TARGET_STRING "mach-o-be" +#define TARGET_BIG_ENDIAN 1 +#define TARGET_ARCHIVE 0 + +#include "mach-o-target.c" + +#undef TARGET_NAME +#undef TARGET_STRING +#undef TARGET_BIG_ENDIAN +#undef TARGET_ARCHIVE + +#define TARGET_NAME mach_o_le_vec +#define TARGET_STRING "mach-o-le" +#define TARGET_BIG_ENDIAN 0 +#define TARGET_ARCHIVE 0 + +#include "mach-o-target.c" + +#undef TARGET_NAME +#undef TARGET_STRING +#undef TARGET_BIG_ENDIAN +#undef TARGET_ARCHIVE + +#define TARGET_NAME mach_o_fat_vec +#define TARGET_STRING "mach-o-fat" +#define TARGET_BIG_ENDIAN 1 +#define TARGET_ARCHIVE 1 + +#include "mach-o-target.c" + +#undef TARGET_NAME +#undef TARGET_STRING +#undef TARGET_BIG_ENDIAN +#undef TARGET_ARCHIVE diff --git a/bfd/mach-o.h b/bfd/mach-o.h new file mode 100644 index 0000000..1f7dd60 --- /dev/null +++ b/bfd/mach-o.h @@ -0,0 +1,511 @@ +/* Mach-O support for BFD. + Copyright 1999, 2000, 2001, 2002 + Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef _BFD_MACH_O_H_ +#define _BFD_MACH_O_H_ + +#include "bfd.h" + +#define BFD_MACH_O_N_STAB 0xe0 /* If any of these bits set, a symbolic debugging entry. */ +#define BFD_MACH_O_N_PEXT 0x10 /* Private external symbol bit. */ +#define BFD_MACH_O_N_TYPE 0x0e /* Mask for the type bits. */ +#define BFD_MACH_O_N_EXT 0x01 /* External symbol bit, set for external symbols. */ +#define BFD_MACH_O_N_UNDF 0x00 /* Undefined, n_sect == NO_SECT. */ +#define BFD_MACH_O_N_ABS 0x02 /* Absolute, n_sect == NO_SECT. */ +#define BFD_MACH_O_N_SECT 0x0e /* Defined in section number n_sect. */ +#define BFD_MACH_O_N_PBUD 0x0c /* Prebound undefined (defined in a dylib). */ +#define BFD_MACH_O_N_INDR 0x0a /* Indirect. */ + +typedef enum bfd_mach_o_ppc_thread_flavour + { + BFD_MACH_O_PPC_THREAD_STATE = 1, + BFD_MACH_O_PPC_FLOAT_STATE = 2, + BFD_MACH_O_PPC_EXCEPTION_STATE = 3, + BFD_MACH_O_PPC_VECTOR_STATE = 4 + } +bfd_mach_o_ppc_thread_flavour; + +typedef enum bfd_mach_o_i386_thread_flavour + { + BFD_MACH_O_i386_NEW_THREAD_STATE = 1, + BFD_MACH_O_i386_FLOAT_STATE = 2, + BFD_MACH_O_i386_ISA_PORT_MAP_STATE = 3, + BFD_MACH_O_i386_V86_ASSIST_STATE = 4, + BFD_MACH_O_i386_REGS_SEGS_STATE = 5, + BFD_MACH_O_i386_THREAD_SYSCALL_STATE = 6, + BFD_MACH_O_i386_THREAD_STATE_NONE = 7, + BFD_MACH_O_i386_SAVED_STATE = 8, + BFD_MACH_O_i386_THREAD_STATE = -1, + BFD_MACH_O_i386_THREAD_FPSTATE = -2, + BFD_MACH_O_i386_THREAD_EXCEPTSTATE = -3, + BFD_MACH_O_i386_THREAD_CTHREADSTATE = -4, + } +bfd_mach_o_i386_thread_flavour; + +#define BFD_MACH_O_LC_REQ_DYLD 0x80000000 + +typedef enum bfd_mach_o_load_command_type + { + BFD_MACH_O_LC_SEGMENT = 0x1, /* File segment to be mapped. */ + BFD_MACH_O_LC_SYMTAB = 0x2, /* Link-edit stab symbol table info (obsolete). */ + BFD_MACH_O_LC_SYMSEG = 0x3, /* Link-edit gdb symbol table info. */ + BFD_MACH_O_LC_THREAD = 0x4, /* Thread. */ + BFD_MACH_O_LC_UNIXTHREAD = 0x5, /* UNIX thread (includes a stack). */ + BFD_MACH_O_LC_LOADFVMLIB = 0x6, /* Load a fixed VM shared library. */ + BFD_MACH_O_LC_IDFVMLIB = 0x7, /* Fixed VM shared library id. */ + BFD_MACH_O_LC_IDENT = 0x8, /* Object identification information (obsolete). */ + BFD_MACH_O_LC_FVMFILE = 0x9, /* Fixed VM file inclusion. */ + BFD_MACH_O_LC_PREPAGE = 0xa, /* Prepage command (internal use). */ + BFD_MACH_O_LC_DYSYMTAB = 0xb, /* Dynamic link-edit symbol table info. */ + BFD_MACH_O_LC_LOAD_DYLIB = 0xc, /* Load a dynamically linked shared library. */ + BFD_MACH_O_LC_ID_DYLIB = 0xd, /* Dynamically linked shared lib identification. */ + BFD_MACH_O_LC_LOAD_DYLINKER = 0xe, /* Load a dynamic linker. */ + BFD_MACH_O_LC_ID_DYLINKER = 0xf, /* Dynamic linker identification. */ + BFD_MACH_O_LC_PREBOUND_DYLIB = 0x10,/* Modules prebound for a dynamically. */ + BFD_MACH_O_LC_ROUTINES = 0x11, /* Image routines. */ + BFD_MACH_O_LC_SUB_FRAMEWORK = 0x12, /* Sub framework. */ + BFD_MACH_O_LC_SUB_UMBRELLA = 0x13, /* Sub umbrella. */ + BFD_MACH_O_LC_SUB_CLIENT = 0x14, /* Sub client. */ + BFD_MACH_O_LC_SUB_LIBRARY = 0x15, /* Sub library. */ + BFD_MACH_O_LC_TWOLEVEL_HINTS = 0x16,/* Two-level namespace lookup hints. */ + BFD_MACH_O_LC_PREBIND_CKSUM = 0x17, /* Prebind checksum. */ + /* Load a dynamically linked shared library that is allowed to be + missing (weak). */ + BFD_MACH_O_LC_LOAD_WEAK_DYLIB = 0x18 + } +bfd_mach_o_load_command_type; + +typedef enum bfd_mach_o_cpu_type + { + BFD_MACH_O_CPU_TYPE_VAX = 1, + BFD_MACH_O_CPU_TYPE_MC680x0 = 6, + BFD_MACH_O_CPU_TYPE_I386 = 7, + BFD_MACH_O_CPU_TYPE_MIPS = 8, + BFD_MACH_O_CPU_TYPE_MC98000 = 10, + BFD_MACH_O_CPU_TYPE_HPPA = 11, + BFD_MACH_O_CPU_TYPE_ARM = 12, + BFD_MACH_O_CPU_TYPE_MC88000 = 13, + BFD_MACH_O_CPU_TYPE_SPARC = 14, + BFD_MACH_O_CPU_TYPE_I860 = 15, + BFD_MACH_O_CPU_TYPE_ALPHA = 16, + BFD_MACH_O_CPU_TYPE_POWERPC = 18 + } +bfd_mach_o_cpu_type; + +typedef enum bfd_mach_o_filetype + { + BFD_MACH_O_MH_OBJECT = 1, + BFD_MACH_O_MH_EXECUTE = 2, + BFD_MACH_O_MH_FVMLIB = 3, + BFD_MACH_O_MH_CORE = 4, + BFD_MACH_O_MH_PRELOAD = 5, + BFD_MACH_O_MH_DYLIB = 6, + BFD_MACH_O_MH_DYLINKER = 7, + BFD_MACH_O_MH_BUNDLE = 8 + } +bfd_mach_o_filetype; + +/* Constants for the type of a section. */ + +typedef enum bfd_mach_o_section_type + { + /* Regular section. */ + BFD_MACH_O_S_REGULAR = 0x0, + + /* Zero fill on demand section. */ + BFD_MACH_O_S_ZEROFILL = 0x1, + + /* Section with only literal C strings. */ + BFD_MACH_O_S_CSTRING_LITERALS = 0x2, + + /* Section with only 4 byte literals. */ + BFD_MACH_O_S_4BYTE_LITERALS = 0x3, + + /* Section with only 8 byte literals. */ + BFD_MACH_O_S_8BYTE_LITERALS = 0x4, + + /* Section with only pointers to literals. */ + BFD_MACH_O_S_LITERAL_POINTERS = 0x5, + + /* For the two types of symbol pointers sections and the symbol stubs + section they have indirect symbol table entries. For each of the + entries in the section the indirect symbol table entries, in + corresponding order in the indirect symbol table, start at the index + stored in the reserved1 field of the section structure. Since the + indirect symbol table entries correspond to the entries in the + section the number of indirect symbol table entries is inferred from + the size of the section divided by the size of the entries in the + section. For symbol pointers sections the size of the entries in + the section is 4 bytes and for symbol stubs sections the byte size + of the stubs is stored in the reserved2 field of the section + structure. */ + + /* Section with only non-lazy symbol pointers. */ + BFD_MACH_O_S_NON_LAZY_SYMBOL_POINTERS = 0x6, + + /* Section with only lazy symbol pointers. */ + BFD_MACH_O_S_LAZY_SYMBOL_POINTERS = 0x7, + + /* Section with only symbol stubs, byte size of stub in the reserved2 field. */ + BFD_MACH_O_S_SYMBOL_STUBS = 0x8, + + /* Section with only function pointers for initialization. */ + BFD_MACH_O_S_MOD_INIT_FUNC_POINTERS = 0x9 + } +bfd_mach_o_section_type; + +typedef unsigned long bfd_mach_o_cpu_subtype; + +typedef struct bfd_mach_o_header +{ + unsigned long magic; + unsigned long cputype; + unsigned long cpusubtype; + unsigned long filetype; + unsigned long ncmds; + unsigned long sizeofcmds; + unsigned long flags; + enum bfd_endian byteorder; +} +bfd_mach_o_header; + +typedef struct bfd_mach_o_section +{ + asection *bfdsection; + char sectname[16 + 1]; + char segname[16 + 1]; + bfd_vma addr; + bfd_vma size; + bfd_vma offset; + unsigned long align; + bfd_vma reloff; + unsigned long nreloc; + unsigned long flags; + unsigned long reserved1; + unsigned long reserved2; +} +bfd_mach_o_section; + +typedef struct bfd_mach_o_segment_command +{ + char segname[16]; + bfd_vma vmaddr; + bfd_vma vmsize; + bfd_vma fileoff; + unsigned long filesize; + unsigned long nsects; + unsigned long flags; + bfd_mach_o_section *sections; + asection *segment; +} +bfd_mach_o_segment_command; + +typedef struct bfd_mach_o_symtab_command +{ + unsigned long symoff; + unsigned long nsyms; + unsigned long stroff; + unsigned long strsize; + asymbol *symbols; + char *strtab; + asection *stabs_segment; + asection *stabstr_segment; +} +bfd_mach_o_symtab_command; + +/* This is the second set of the symbolic information which is used to support + the data structures for the dynamically link editor. + + The original set of symbolic information in the symtab_command which contains + the symbol and string tables must also be present when this load command is + present. When this load command is present the symbol table is organized + into three groups of symbols: + local symbols (static and debugging symbols) - grouped by module + defined external symbols - grouped by module (sorted by name if not lib) + undefined external symbols (sorted by name) + In this load command there are offsets and counts to each of the three groups + of symbols. + + This load command contains a the offsets and sizes of the following new + symbolic information tables: + table of contents + module table + reference symbol table + indirect symbol table + The first three tables above (the table of contents, module table and + reference symbol table) are only present if the file is a dynamically linked + shared library. For executable and object modules, which are files + containing only one module, the information that would be in these three + tables is determined as follows: + table of contents - the defined external symbols are sorted by name + module table - the file contains only one module so everything in the + file is part of the module. + reference symbol table - is the defined and undefined external symbols + + For dynamically linked shared library files this load command also contains + offsets and sizes to the pool of relocation entries for all sections + separated into two groups: + external relocation entries + local relocation entries + For executable and object modules the relocation entries continue to hang + off the section structures. */ + +typedef struct bfd_mach_o_dysymtab_command +{ + /* The symbols indicated by symoff and nsyms of the LC_SYMTAB load command + are grouped into the following three groups: + local symbols (further grouped by the module they are from) + defined external symbols (further grouped by the module they are from) + undefined symbols + + The local symbols are used only for debugging. The dynamic binding + process may have to use them to indicate to the debugger the local + symbols for a module that is being bound. + + The last two groups are used by the dynamic binding process to do the + binding (indirectly through the module table and the reference symbol + table when this is a dynamically linked shared library file). */ + + unsigned long ilocalsym; /* Index to local symbols. */ + unsigned long nlocalsym; /* Number of local symbols. */ + unsigned long iextdefsym; /* Index to externally defined symbols. */ + unsigned long nextdefsym; /* Number of externally defined symbols. */ + unsigned long iundefsym; /* Index to undefined symbols. */ + unsigned long nundefsym; /* Number of undefined symbols. */ + + /* For the for the dynamic binding process to find which module a symbol + is defined in the table of contents is used (analogous to the ranlib + structure in an archive) which maps defined external symbols to modules + they are defined in. This exists only in a dynamically linked shared + library file. For executable and object modules the defined external + symbols are sorted by name and is use as the table of contents. */ + + unsigned long tocoff; /* File offset to table of contents. */ + unsigned long ntoc; /* Number of entries in table of contents. */ + + /* To support dynamic binding of "modules" (whole object files) the symbol + table must reflect the modules that the file was created from. This is + done by having a module table that has indexes and counts into the merged + tables for each module. The module structure that these two entries + refer to is described below. This exists only in a dynamically linked + shared library file. For executable and object modules the file only + contains one module so everything in the file belongs to the module. */ + + unsigned long modtaboff; /* File offset to module table. */ + unsigned long nmodtab; /* Number of module table entries. */ + + /* To support dynamic module binding the module structure for each module + indicates the external references (defined and undefined) each module + makes. For each module there is an offset and a count into the + reference symbol table for the symbols that the module references. + This exists only in a dynamically linked shared library file. For + executable and object modules the defined external symbols and the + undefined external symbols indicates the external references. */ + + unsigned long extrefsymoff; /* Offset to referenced symbol table. */ + unsigned long nextrefsyms; /* Number of referenced symbol table entries. */ + + /* The sections that contain "symbol pointers" and "routine stubs" have + indexes and (implied counts based on the size of the section and fixed + size of the entry) into the "indirect symbol" table for each pointer + and stub. For every section of these two types the index into the + indirect symbol table is stored in the section header in the field + reserved1. An indirect symbol table entry is simply a 32bit index into + the symbol table to the symbol that the pointer or stub is referring to. + The indirect symbol table is ordered to match the entries in the section. */ + + unsigned long indirectsymoff; /* File offset to the indirect symbol table. */ + unsigned long nindirectsyms; /* Number of indirect symbol table entries. */ + + /* To support relocating an individual module in a library file quickly the + external relocation entries for each module in the library need to be + accessed efficiently. Since the relocation entries can't be accessed + through the section headers for a library file they are separated into + groups of local and external entries further grouped by module. In this + case the presents of this load command who's extreloff, nextrel, + locreloff and nlocrel fields are non-zero indicates that the relocation + entries of non-merged sections are not referenced through the section + structures (and the reloff and nreloc fields in the section headers are + set to zero). + + Since the relocation entries are not accessed through the section headers + this requires the r_address field to be something other than a section + offset to identify the item to be relocated. In this case r_address is + set to the offset from the vmaddr of the first LC_SEGMENT command. + + The relocation entries are grouped by module and the module table + entries have indexes and counts into them for the group of external + relocation entries for that the module. + + For sections that are merged across modules there must not be any + remaining external relocation entries for them (for merged sections + remaining relocation entries must be local). */ + + unsigned long extreloff; /* Offset to external relocation entries. */ + unsigned long nextrel; /* Number of external relocation entries. */ + + /* All the local relocation entries are grouped together (they are not + grouped by their module since they are only used if the object is moved + from it statically link edited address). */ + + unsigned long locreloff; /* Offset to local relocation entries. */ + unsigned long nlocrel; /* Number of local relocation entries. */ +} +bfd_mach_o_dysymtab_command; + +/* An indirect symbol table entry is simply a 32bit index into the symbol table + to the symbol that the pointer or stub is refering to. Unless it is for a + non-lazy symbol pointer section for a defined symbol which strip(1) as + removed. In which case it has the value INDIRECT_SYMBOL_LOCAL. If the + symbol was also absolute INDIRECT_SYMBOL_ABS is or'ed with that. */ + +#define INDIRECT_SYMBOL_LOCAL 0x80000000 +#define INDIRECT_SYMBOL_ABS 0x40000000 + +typedef struct bfd_mach_o_thread_flavour +{ + unsigned long flavour; + bfd_vma offset; + unsigned long size; +} +bfd_mach_o_thread_flavour; + +typedef struct bfd_mach_o_thread_command +{ + unsigned long nflavours; + bfd_mach_o_thread_flavour *flavours; + asection *section; +} +bfd_mach_o_thread_command; + +typedef struct bfd_mach_o_dylinker_command +{ + unsigned long cmd; /* LC_ID_DYLIB or LC_LOAD_DYLIB. */ + unsigned long cmdsize; /* Includes pathname string. */ + unsigned long name_offset; /* Offset to library's path name. */ + unsigned long name_len; /* Offset to library's path name. */ + asection *section; +} +bfd_mach_o_dylinker_command; + +typedef struct bfd_mach_o_dylib_command +{ + unsigned long cmd; /* LC_ID_DYLIB or LC_LOAD_DYLIB. */ + unsigned long cmdsize; /* Includes pathname string. */ + unsigned long name_offset; /* Offset to library's path name. */ + unsigned long name_len; /* Offset to library's path name. */ + unsigned long timestamp; /* Library's build time stamp. */ + unsigned long current_version; /* Library's current version number. */ + unsigned long compatibility_version; /* Library's compatibility vers number. */ + asection *section; +} +bfd_mach_o_dylib_command; + +typedef struct bfd_mach_o_prebound_dylib_command +{ + unsigned long cmd; /* LC_PREBOUND_DYLIB. */ + unsigned long cmdsize; /* Includes strings. */ + unsigned long name; /* Library's path name. */ + unsigned long nmodules; /* Number of modules in library. */ + unsigned long linked_modules; /* Bit vector of linked modules. */ + asection *section; +} +bfd_mach_o_prebound_dylib_command; + +typedef struct bfd_mach_o_load_command +{ + bfd_mach_o_load_command_type type; + unsigned int type_required; + bfd_vma offset; + bfd_vma len; + union + { + bfd_mach_o_segment_command segment; + bfd_mach_o_symtab_command symtab; + bfd_mach_o_dysymtab_command dysymtab; + bfd_mach_o_thread_command thread; + bfd_mach_o_dylib_command dylib; + bfd_mach_o_dylinker_command dylinker; + bfd_mach_o_prebound_dylib_command prebound_dylib; + } + command; +} +bfd_mach_o_load_command; + +typedef struct mach_o_data_struct +{ + bfd_mach_o_header header; + bfd_mach_o_load_command *commands; + unsigned long nsymbols; + asymbol *symbols; + unsigned long nsects; + bfd_mach_o_section **sections; + bfd *ibfd; +} +mach_o_data_struct; + +typedef struct mach_o_data_struct bfd_mach_o_data_struct; + +bfd_boolean bfd_mach_o_valid + PARAMS ((bfd *)); +int bfd_mach_o_scan_read_symtab_symbol + PARAMS ((bfd *, bfd_mach_o_symtab_command *, asymbol *, unsigned long)); +int bfd_mach_o_scan_read_symtab_strtab + PARAMS ((bfd *, bfd_mach_o_symtab_command *)); +int bfd_mach_o_scan_read_symtab_symbols + PARAMS ((bfd *, bfd_mach_o_symtab_command *)); +int bfd_mach_o_scan_read_dysymtab_symbol + PARAMS ((bfd *, bfd_mach_o_dysymtab_command *, bfd_mach_o_symtab_command *, + asymbol *, unsigned long)); +int bfd_mach_o_scan_start_address + PARAMS ((bfd *)); +int bfd_mach_o_scan + PARAMS ((bfd *, bfd_mach_o_header *, bfd_mach_o_data_struct *)); +bfd_boolean bfd_mach_o_mkobject + PARAMS ((bfd *)); +const bfd_target * bfd_mach_o_object_p + PARAMS ((bfd *)); +const bfd_target * bfd_mach_o_core_p + PARAMS ((bfd *)); +const bfd_target * bfd_mach_o_archive_p + PARAMS ((bfd *)); +bfd * bfd_mach_o_openr_next_archived_file + PARAMS ((bfd *, bfd *)); +int bfd_mach_o_lookup_section + PARAMS ((bfd *, asection *, bfd_mach_o_load_command **, + bfd_mach_o_section **)); +int bfd_mach_o_lookup_command + PARAMS ((bfd *, bfd_mach_o_load_command_type, bfd_mach_o_load_command **)); +unsigned long bfd_mach_o_stack_addr + PARAMS ((enum bfd_mach_o_cpu_type)); +int bfd_mach_o_core_fetch_environment + PARAMS ((bfd *, unsigned char **, unsigned int *)); +char * bfd_mach_o_core_file_failing_command + PARAMS ((bfd *)); +int bfd_mach_o_core_file_failing_signal + PARAMS ((bfd *)); +bfd_boolean bfd_mach_o_core_file_matches_executable_p + PARAMS ((bfd *, bfd *)); + +extern const bfd_target mach_o_be_vec; +extern const bfd_target mach_o_le_vec; +extern const bfd_target mach_o_fat_vec; + +#endif /* _BFD_MACH_O_H_ */ diff --git a/bfd/pef-traceback.h b/bfd/pef-traceback.h new file mode 100644 index 0000000..15f43b6 --- /dev/null +++ b/bfd/pef-traceback.h @@ -0,0 +1,215 @@ +/* PowerPC traceback table support for BFD. + Copyright 1993, 1998, 1999, 2000, 2001, 2002 + Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* Originally written by Ira Ruben, 06/28/93 */ + +/* This is a compiler independent representation of the AIX Version 3 traceback table (in + sys/debug.h), which occurs, usually, one per procedure (routine). The table is marked by + a multiple of 4 32-bit word of zeroes in the instruction space. The traceback table is + also referred to as "procedure-end table". + + The AIX traceback table representation on which this header is based is defined as a + series of bit field struct specifications. Bit fields are compiler dependent! Thus, + the definitions presented here follow the original header and the existing documentation + (such as it is), but define the fields as BIT MASKS and other macros. The mask names, + however, where chosen as the original field names to give some compatibility with the + original header and to agree with the documentation. */ + +#ifndef __TRACEBACK__ +#define __TRACEBACK__ + +#define TB_C 0U /* C */ +#define TB_FORTRAN 1U /* FORTRAN */ +#define TB_PASCAL 2U /* Pascal */ +#define TB_ADA 3U /* ADA */ +#define TB_PL1 4U /* PL1 */ +#define TB_BASIC 5U /* Basic */ +#define TB_LISP 6U /* Lisp */ +#define TB_COBOL 7U /* eCobol */ +#define TB_MODULA2 8U /* Modula2 */ +#define TB_CPLUSPLUS 9U /* C++ */ +#define TB_RPG 10U /* RPG */ +#define TB_PL8 11U /* PL8 */ +#define TB_ASM 12U /* Asm */ + +/* flags 1 */ + +#define TB_GLOBALLINK 0x80U /* Routine is Global Linkage. */ +#define TB_is_eprol 0x40U /* Out-of-line prolog or epilog routine. */ +#define TB_HAS_TBOFF 0x20U /* tb_offset set (extension field). */ +#define TB_INT_PROC 0x10U /* Internal leaf routine. */ +#define TB_HAS_CTL 0x08U /* Has controlled automatic storage. */ +#define TB_TOCLESS 0X04U /* Routine has no TOC. */ +#define TB_FP_PRESENT 0x02U /* Routine has floating point ops. */ +#define TB_LOG_ABORT 0x01U /* fp_present && log/abort compiler opt. */ + +/* flags 2 */ + +#define TB_INT_HNDL 0x80U /* Routine is an interrupt handler. */ +#define TB_NAME_PRESENT 0x40U /* Name_len/name set (extension field). */ +#define TB_USES_ALLOCA 0x20U /* Uses alloca() to allocate storage. */ +#define TB_CL_DIS_inv 0x1CU /* On-condition directives (see below). */ +#define TB_SAVES_CR 0x02U /* Routine saves the CR. */ +#define TB_SAVES_LR 0x01U /* Routine saves the LR. */ + +/* cl_dis_inv "on condition" settings: */ + +#define TB_CL_DIS_INV(x) (((x) & cl_dis_inv) >> 2U) + +#define TB_WALK_ONCOND 0U /* Walk stack without restoring state. */ +#define TB_DISCARD_ONCOND 1U /* Walk stack and discard. */ +#define TB_INVOKE_ONCOND 2U /* Invoke a specific system routine. */ + +/* flags 3 */ + +#define TB_STORES_BC 0x80U /* Routine saves frame ptr of caller. */ +#define TB_SPARE2 0X40U /* Spare bit. */ +#define TB_FPR_SAVED 0x3fU /* Number of FPRs saved (max of 32). */ + /* (Last reg saved is ALWAYS fpr31). */ + +#define TB_NUM_FPR_SAVED(x) ((x) & fpr_saved) + +/* flags 4 */ + +#define TB_HAS_VEC_INFO 0x80U /* Routine uses vectors. */ +#define TB_SPARE3 0X40U /* Spare bit. */ +#define TB_GPR_SAVED 0x3fU /* Number of GPRs saved (max of 32). */ + /* (Last reg saved is ALWAYS gpr31). */ + +#define TB_NUM_GPR_SAVED(x) ((x) & gpr_saved) + +/* flags 5 */ + +#define TB_FLOATPARAMS 0xfeU /* Number of floating point parameters. */ +#define TB_PARAMSONSTK 0X01U /* All parameters are on the stack. */ + +#define TB_NUM_FLOATPARAMS(X) (((x) & floatparams) >> 1U) + +/* traceback_table (fixed portion). */ + +struct traceback_table +{ + /* Traceback table layout (fixed portion): */ + + unsigned char version; /* Traceback format version. */ + unsigned char lang; /* Language indicators: */ + unsigned char flags1; /* Flag bits #1: */ + unsigned char flags2; /* Flag bits #2: */ + unsigned char flags3; /* Flag bits #3: */ + unsigned char flags4; /* Flag bits #4: */ + unsigned char fixedparams; /* Number of fixed point parameters. */ + unsigned char flags5; /* Flag bits #5: */ +}; + +/* traceback_table (optional) extensions. */ + +/* Optional portions exist independently in the order presented below, + not as a structure or a union. Whether or not portions exist is + determinable from bit-fields within the fixed portion above. */ + +/* The following is present only if fixedparams or floatparams are non + zero and it immediately follows the fixed portion of the traceback + table... */ + +/* Order and type encoding of parameters: */ +struct traceback_table_fixedparams +{ + unsigned long paraminfo; +}; + +/* Left-justified bit-encoding as follows: */ +#define FIXED_PARAM 0 /* '0' ==> fixed param (1 gpr or word). */ +#define SPFP_PARAM 2 /* '10' ==> single-precision float param. */ +#define DPFP_PARAM 3 /* '11' ==> double-precision float param. */ + +#define PARAM_ENCODING(x, bit) /* Yields xxx_PARAM as a function of "bit". */ \ + ((((x)&(1UL<<(31UL-(bit++))))==0UL) /* Values 0:31 (left-to-right). "bit" is */ \ + ? FIXED_PARAM /* an L-value that's left incremented to */ \ + : ((((x)&(1UL<<(31UL-(bit++))))==0)/* the next bit position for the next */ \ + ? SPFP_PARAM /* parameter. This will be 1 or 2 bit */ \ + : DPFP_PARAM)) /* positions later. */ + +/* The following is present only if has_tboff (in flags1) in fixed part is present... */ + +/* Offset from start of code to TracebackTbl. */ +struct traceback_table_tboff +{ + unsigned long tb_offset; +}; + +/* The following is present only if int_hndl (in flags2) in fixed part is present ... */ + +/* What interrupts are handled by the routine. */ +struct traceback_table_interrupts +{ + long hand_mask; +}; + +/* The following are present only if has_ctl (in flags1) in fixed part is present... */ + +/* Controlled automatic storage info: */ +struct traceback_table_anchors +{ + unsigned long ctl_info; /* Number of controlled automatic anchors. */ + long ctl_info_disp[1]; /* Array of stack displacements where each. */ +}; /* Anchor is located (array STARTS here). */ + +/* The following are present only if name_present (in flags2) in fixed + part is present... */ + +/* Routine name: */ +struct traceback_table_routine +{ + unsigned short name_len; /* Length of name that follows. */ + char name[1]; /* Name starts here (NOT null terminated). */ +}; + +/* The following are present only if uses_alloca (in flags2) in fixed + part is present... */ + +/* Register auto storage when alloca() is used. */ +struct traceback_table_alloca +{ + char alloca_reg; +}; + +/* The following are present only if has_vec_info (in flags4) in fixed + part is present... */ + +/* Vector info: */ +struct traceback_table_vector +{ + unsigned char vec_flags1; /* Vec info bits #1: */ + +#define TB_VR_SAVED 0xFCU /* Number of saved vector registers. */ +#define TB_SAVES_VRSAVE 0x02U /* Saves VRsave. */ +#define TB_HAS_VARARGS 0x01U /* Routine has a variable argument list. */ + +#define TB_NUM_VR_SAVED(x) (((x) & TB_VR_SAVED) >> 2U) + + unsigned char vec_flags2; /* Vec info bits #2: */ + +#define TB_VECTORPARAMS 0xfeU /* Number of vector parameters. */ +#define TB_VEC_PRESENT 0x01U /* Routine uses at least one vec instr. */ + +#define VECPARAMS(x) (((x) & TB_VECTORPARAMS) >> 1U) +}; + +#endif diff --git a/bfd/pef.c b/bfd/pef.c new file mode 100644 index 0000000..7d758cf --- /dev/null +++ b/bfd/pef.c @@ -0,0 +1,1292 @@ +/* PEF support for BFD. + Copyright 1999, 2000, 2001, 2002, 2003 + Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include "safe-ctype.h" + +#include "pef.h" +#include "pef-traceback.h" + +#include "bfd.h" +#include "sysdep.h" +#include "libbfd.h" + +#include "libiberty.h" + +#ifndef BFD_IO_FUNCS +#define BFD_IO_FUNCS 0 +#endif + +#define bfd_pef_close_and_cleanup _bfd_generic_close_and_cleanup +#define bfd_pef_bfd_free_cached_info _bfd_generic_bfd_free_cached_info +#define bfd_pef_new_section_hook _bfd_generic_new_section_hook +#define bfd_pef_bfd_is_local_label_name bfd_generic_is_local_label_name +#define bfd_pef_get_lineno _bfd_nosymbols_get_lineno +#define bfd_pef_find_nearest_line _bfd_nosymbols_find_nearest_line +#define bfd_pef_bfd_make_debug_symbol _bfd_nosymbols_bfd_make_debug_symbol +#define bfd_pef_read_minisymbols _bfd_generic_read_minisymbols +#define bfd_pef_minisymbol_to_symbol _bfd_generic_minisymbol_to_symbol +#define bfd_pef_get_reloc_upper_bound _bfd_norelocs_get_reloc_upper_bound +#define bfd_pef_canonicalize_reloc _bfd_norelocs_canonicalize_reloc +#define bfd_pef_bfd_reloc_type_lookup _bfd_norelocs_bfd_reloc_type_lookup +#define bfd_pef_set_arch_mach _bfd_generic_set_arch_mach +#define bfd_pef_get_section_contents _bfd_generic_get_section_contents +#define bfd_pef_set_section_contents _bfd_generic_set_section_contents +#define bfd_pef_bfd_get_relocated_section_contents bfd_generic_get_relocated_section_contents +#define bfd_pef_bfd_relax_section bfd_generic_relax_section +#define bfd_pef_bfd_gc_sections bfd_generic_gc_sections +#define bfd_pef_bfd_merge_sections bfd_generic_merge_sections +#define bfd_pef_bfd_discard_group bfd_generic_discard_group +#define bfd_pef_bfd_link_hash_table_create _bfd_generic_link_hash_table_create +#define bfd_pef_bfd_link_hash_table_free _bfd_generic_link_hash_table_free +#define bfd_pef_bfd_link_add_symbols _bfd_generic_link_add_symbols +#define bfd_pef_bfd_link_just_syms _bfd_generic_link_just_syms +#define bfd_pef_bfd_final_link _bfd_generic_final_link +#define bfd_pef_bfd_link_split_section _bfd_generic_link_split_section +#define bfd_pef_get_section_contents_in_window _bfd_generic_get_section_contents_in_window + +static void bfd_pef_print_symbol PARAMS ((bfd *, PTR, asymbol *, bfd_print_symbol_type)); +static void bfd_pef_convert_architecture PARAMS ((unsigned long, enum bfd_architecture *, unsigned long *)); +static bfd_boolean bfd_pef_mkobject PARAMS ((bfd *)); +static int bfd_pef_parse_traceback_table PARAMS ((bfd *, asection *, unsigned char *, size_t, size_t, asymbol *, FILE *)); +static const char *bfd_pef_section_name PARAMS ((bfd_pef_section *)); +static unsigned long bfd_pef_section_flags PARAMS ((bfd_pef_section *)); +static asection *bfd_pef_make_bfd_section PARAMS ((bfd *, bfd_pef_section *)); +static int bfd_pef_read_header PARAMS ((bfd *, bfd_pef_header *)); +static const bfd_target *bfd_pef_object_p PARAMS ((bfd *)); +static int bfd_pef_parse_traceback_tables PARAMS ((bfd *, asection *, unsigned char *, size_t, long *, asymbol **)); +static int bfd_pef_parse_function_stub PARAMS ((bfd *, unsigned char *, size_t, unsigned long *)); +static int bfd_pef_parse_function_stubs PARAMS ((bfd *, asection *, unsigned char *, size_t, unsigned char *, size_t, unsigned long *, asymbol **)); +static long bfd_pef_parse_symbols PARAMS ((bfd *, asymbol **)); +static long bfd_pef_count_symbols PARAMS ((bfd *)); +static long bfd_pef_get_symtab_upper_bound PARAMS ((bfd *)); +static long bfd_pef_canonicalize_symtab PARAMS ((bfd *, asymbol **)); +static asymbol *bfd_pef_make_empty_symbol PARAMS ((bfd *)); +static void bfd_pef_get_symbol_info PARAMS ((bfd *, asymbol *, symbol_info *)); +static int bfd_pef_sizeof_headers PARAMS ((bfd *, bfd_boolean)); +static int bfd_pef_xlib_read_header PARAMS ((bfd *, bfd_pef_xlib_header *)); +static int bfd_pef_xlib_scan PARAMS ((bfd *, bfd_pef_xlib_header *)); +static const bfd_target *bfd_pef_xlib_object_p PARAMS ((bfd *)); + +static void +bfd_pef_print_symbol (abfd, afile, symbol, how) + bfd *abfd; + PTR afile; + asymbol *symbol; + bfd_print_symbol_type how; +{ + FILE *file = (FILE *) afile; + + switch (how) + { + case bfd_print_symbol_name: + fprintf (file, "%s", symbol->name); + break; + default: + bfd_print_symbol_vandf (abfd, (PTR) file, symbol); + fprintf (file, " %-5s %s", symbol->section->name, symbol->name); + if (strncmp (symbol->name, "__traceback_", strlen ("__traceback_")) == 0) + { + char *buf = alloca (symbol->udata.i); + size_t offset = symbol->value + 4; + size_t len = symbol->udata.i; + int ret; + + bfd_get_section_contents (abfd, symbol->section, buf, offset, len); + ret = bfd_pef_parse_traceback_table (abfd, symbol->section, buf, + len, 0, NULL, file); + if (ret < 0) + fprintf (file, " [ERROR]"); + } + } +} + +static void +bfd_pef_convert_architecture (architecture, type, subtype) + unsigned long architecture; + enum bfd_architecture *type; + unsigned long *subtype; +{ + const unsigned long ARCH_POWERPC = 0x70777063; /* 'pwpc' */ + const unsigned long ARCH_M68K = 0x6d36386b; /* 'm68k' */ + + *subtype = bfd_arch_unknown; + *type = bfd_arch_unknown; + + if (architecture == ARCH_POWERPC) + *type = bfd_arch_powerpc; + else if (architecture == ARCH_M68K) + *type = bfd_arch_m68k; +} + +static bfd_boolean +bfd_pef_mkobject (abfd) + bfd *abfd ATTRIBUTE_UNUSED; +{ + return TRUE; +} + +static int +bfd_pef_parse_traceback_table (abfd, section, buf, len, pos, sym, file) + bfd *abfd; + asection *section; + unsigned char *buf; + size_t len; + size_t pos; + asymbol *sym; + FILE *file; +{ + struct traceback_table table; + size_t offset; + const char *s; + asymbol tmpsymbol; + + if (sym == NULL) + sym = &tmpsymbol; + + sym->name = NULL; + sym->value = 0; + sym->the_bfd = abfd; + sym->section = section; + sym->flags = 0; + sym->udata.i = 0; + + /* memcpy is fine since all fields are unsigned char. */ + + if ((pos + 8) > len) + return -1; + memcpy (&table, buf + pos, 8); + + /* Calling code relies on returned symbols having a name and + correct offset. */ + + if ((table.lang != TB_C) && (table.lang != TB_CPLUSPLUS)) + return -1; + + if (! (table.flags2 & TB_NAME_PRESENT)) + return -1; + + if (! table.flags1 & TB_HAS_TBOFF) + return -1; + + offset = 8; + + if ((table.flags5 & TB_FLOATPARAMS) || (table.fixedparams)) + offset += 4; + + if (table.flags1 & TB_HAS_TBOFF) + { + struct traceback_table_tboff off; + + if ((pos + offset + 4) > len) + return -1; + off.tb_offset = bfd_getb32 (buf + pos + offset); + offset += 4; + + /* Need to subtract 4 because the offset includes the 0x0L + preceding the table. */ + + if (file != NULL) + fprintf (file, " [offset = 0x%lx]", off.tb_offset); + + if ((file == NULL) && ((off.tb_offset + 4) > (pos + offset))) + return -1; + + sym->value = pos - off.tb_offset - 4; + } + + if (table.flags2 & TB_INT_HNDL) + offset += 4; + + if (table.flags1 & TB_HAS_CTL) + { + struct traceback_table_anchors anchors; + + if ((pos + offset + 4) > len) + return -1; + anchors.ctl_info = bfd_getb32 (buf + pos + offset); + offset += 4; + + if (anchors.ctl_info > 1024) + return -1; + + offset += anchors.ctl_info * 4; + } + + if (table.flags2 & TB_NAME_PRESENT) + { + struct traceback_table_routine name; + char *namebuf; + + if ((pos + offset + 2) > len) + return -1; + name.name_len = bfd_getb16 (buf + pos + offset); + offset += 2; + + if (name.name_len > 4096) + return -1; + + if ((pos + offset + name.name_len) > len) + return -1; + + namebuf = (char *) bfd_alloc (abfd, name.name_len + 1); + if (namebuf == NULL) + return -1; + + memcpy (namebuf, buf + pos + offset, name.name_len); + namebuf[name.name_len] = '\0'; + + /* Strip leading period inserted by compiler. */ + if (namebuf[0] == '.') + memmove (namebuf, namebuf + 1, name.name_len + 1); + + sym->name = namebuf; + + for (s = sym->name; (*s != '\0'); s++) + if (! ISPRINT (*s)) + return -1; + + offset += name.name_len; + } + + if (table.flags2 & TB_USES_ALLOCA) + offset += 4; + + if (table.flags4 & TB_HAS_VEC_INFO) + offset += 4; + + if (file != NULL) + fprintf (file, " [length = 0x%lx]", (long) offset); + + return offset; +} + +static const char *bfd_pef_section_name (section) + bfd_pef_section *section; +{ + switch (section->section_kind) + { + case BFD_PEF_SECTION_CODE: return "code"; + case BFD_PEF_SECTION_UNPACKED_DATA: return "unpacked-data"; + case BFD_PEF_SECTION_PACKED_DATA: return "packed-data"; + case BFD_PEF_SECTION_CONSTANT: return "constant"; + case BFD_PEF_SECTION_LOADER: return "loader"; + case BFD_PEF_SECTION_DEBUG: return "debug"; + case BFD_PEF_SECTION_EXEC_DATA: return "exec-data"; + case BFD_PEF_SECTION_EXCEPTION: return "exception"; + case BFD_PEF_SECTION_TRACEBACK: return "traceback"; + default: return "unknown"; + } +} + +static unsigned long bfd_pef_section_flags (section) + bfd_pef_section *section; +{ + switch (section->section_kind) + { + case BFD_PEF_SECTION_CODE: + return SEC_HAS_CONTENTS | SEC_LOAD | SEC_ALLOC | SEC_CODE; + case BFD_PEF_SECTION_UNPACKED_DATA: + case BFD_PEF_SECTION_PACKED_DATA: + case BFD_PEF_SECTION_CONSTANT: + case BFD_PEF_SECTION_LOADER: + case BFD_PEF_SECTION_DEBUG: + case BFD_PEF_SECTION_EXEC_DATA: + case BFD_PEF_SECTION_EXCEPTION: + case BFD_PEF_SECTION_TRACEBACK: + default: + return SEC_HAS_CONTENTS | SEC_LOAD | SEC_ALLOC; + } +} + +static asection * +bfd_pef_make_bfd_section (abfd, section) + bfd *abfd; + bfd_pef_section *section; +{ + asection *bfdsec; + const char *name = bfd_pef_section_name (section); + + bfdsec = bfd_make_section_anyway (abfd, name); + if (bfdsec == NULL) + return NULL; + + bfdsec->vma = section->default_address + section->container_offset; + bfdsec->lma = section->default_address + section->container_offset; + bfdsec->_raw_size = section->container_length; + bfdsec->filepos = section->container_offset; + bfdsec->alignment_power = section->alignment; + + bfdsec->flags = bfd_pef_section_flags (section); + + return bfdsec; +} + +int bfd_pef_parse_loader_header (abfd, buf, len, header) + bfd *abfd ATTRIBUTE_UNUSED; + unsigned char *buf; + size_t len; + bfd_pef_loader_header *header; +{ + BFD_ASSERT (len == 56); + + header->main_section = bfd_getb32 (buf); + header->main_offset = bfd_getb32 (buf + 4); + header->init_section = bfd_getb32 (buf + 8); + header->init_offset = bfd_getb32 (buf + 12); + header->term_section = bfd_getb32 (buf + 16); + header->term_offset = bfd_getb32 (buf + 20); + header->imported_library_count = bfd_getb32 (buf + 24); + header->total_imported_symbol_count = bfd_getb32 (buf + 28); + header->reloc_section_count = bfd_getb32 (buf + 32); + header->reloc_instr_offset = bfd_getb32 (buf + 36); + header->loader_strings_offset = bfd_getb32 (buf + 40); + header->export_hash_offset = bfd_getb32 (buf + 44); + header->export_hash_table_power = bfd_getb32 (buf + 48); + header->exported_symbol_count = bfd_getb32 (buf + 52); + + return 0; +} + +int bfd_pef_parse_imported_library (abfd, buf, len, header) + bfd *abfd ATTRIBUTE_UNUSED; + unsigned char *buf; + size_t len; + bfd_pef_imported_library *header; +{ + BFD_ASSERT (len == 24); + + header->name_offset = bfd_getb32 (buf); + header->old_implementation_version = bfd_getb32 (buf + 4); + header->current_version = bfd_getb32 (buf + 8); + header->imported_symbol_count = bfd_getb32 (buf + 12); + header->first_imported_symbol = bfd_getb32 (buf + 16); + header->options = buf[20]; + header->reserved_a = buf[21]; + header->reserved_b = bfd_getb16 (buf + 22); + + return 0; +} + +int bfd_pef_parse_imported_symbol (abfd, buf, len, symbol) + bfd *abfd ATTRIBUTE_UNUSED; + unsigned char *buf; + size_t len; + bfd_pef_imported_symbol *symbol; +{ + unsigned long value; + + BFD_ASSERT (len == 4); + + value = bfd_getb32 (buf); + symbol->class = value >> 24; + symbol->name = value & 0x00ffffff; + + return 0; +} + +int bfd_pef_scan_section (abfd, section) + bfd *abfd; + bfd_pef_section *section; +{ + unsigned char buf[28]; + + bfd_seek (abfd, section->header_offset, SEEK_SET); + if (bfd_bread ((PTR) buf, 28, abfd) != 28) + return -1; + + section->name_offset = bfd_h_get_32 (abfd, buf); + section->default_address = bfd_h_get_32 (abfd, buf + 4); + section->total_length = bfd_h_get_32 (abfd, buf + 8); + section->unpacked_length = bfd_h_get_32 (abfd, buf + 12); + section->container_length = bfd_h_get_32 (abfd, buf + 16); + section->container_offset = bfd_h_get_32 (abfd, buf + 20); + section->section_kind = buf[24]; + section->share_kind = buf[25]; + section->alignment = buf[26]; + section->reserved = buf[27]; + + section->bfd_section = bfd_pef_make_bfd_section (abfd, section); + if (section->bfd_section == NULL) + return -1; + + return 0; +} + +void +bfd_pef_print_loader_header (abfd, header, file) + bfd *abfd ATTRIBUTE_UNUSED; + bfd_pef_loader_header *header; + FILE *file; +{ + fprintf (file, "main_section: %ld\n", header->main_section); + fprintf (file, "main_offset: %lu\n", header->main_offset); + fprintf (file, "init_section: %ld\n", header->init_section); + fprintf (file, "init_offset: %lu\n", header->init_offset); + fprintf (file, "term_section: %ld\n", header->term_section); + fprintf (file, "term_offset: %lu\n", header->term_offset); + fprintf (file, "imported_library_count: %lu\n", + header->imported_library_count); + fprintf (file, "total_imported_symbol_count: %lu\n", + header->total_imported_symbol_count); + fprintf (file, "reloc_section_count: %lu\n", header->reloc_section_count); + fprintf (file, "reloc_instr_offset: %lu\n", header->reloc_instr_offset); + fprintf (file, "loader_strings_offset: %lu\n", + header->loader_strings_offset); + fprintf (file, "export_hash_offset: %lu\n", header->export_hash_offset); + fprintf (file, "export_hash_table_power: %lu\n", + header->export_hash_table_power); + fprintf (file, "exported_symbol_count: %lu\n", + header->exported_symbol_count); +} + +int +bfd_pef_print_loader_section (abfd, file) + bfd *abfd; + FILE *file; +{ + bfd_pef_loader_header header; + asection *loadersec = NULL; + unsigned char *loaderbuf = NULL; + size_t loaderlen = 0; + int ret; + + loadersec = bfd_get_section_by_name (abfd, "loader"); + if (loadersec == NULL) + return -1; + + loaderlen = bfd_section_size (abfd, loadersec); + loaderbuf = (unsigned char *) bfd_malloc (loaderlen); + if (bfd_seek (abfd, loadersec->filepos, SEEK_SET) < 0) + { + free (loaderbuf); + return -1; + } + if (bfd_bread ((PTR) loaderbuf, loaderlen, abfd) != loaderlen) + { + free (loaderbuf); + return -1; + } + + if (loaderlen < 56) + { + free (loaderbuf); + return -1; + } + ret = bfd_pef_parse_loader_header (abfd, loaderbuf, 56, &header); + if (ret < 0) + { + free (loaderbuf); + return -1; + } + + bfd_pef_print_loader_header (abfd, &header, file); + return 0; +} + +int +bfd_pef_scan_start_address (abfd) + bfd *abfd; +{ + bfd_pef_loader_header header; + asection *section; + + asection *loadersec = NULL; + unsigned char *loaderbuf = NULL; + size_t loaderlen = 0; + int ret; + + loadersec = bfd_get_section_by_name (abfd, "loader"); + if (loadersec == NULL) + goto end; + + loaderlen = bfd_section_size (abfd, loadersec); + loaderbuf = (unsigned char *) bfd_malloc (loaderlen); + if (bfd_seek (abfd, loadersec->filepos, SEEK_SET) < 0) + goto error; + if (bfd_bread ((PTR) loaderbuf, loaderlen, abfd) != loaderlen) + goto error; + + if (loaderlen < 56) + goto error; + ret = bfd_pef_parse_loader_header (abfd, loaderbuf, 56, &header); + if (ret < 0) + goto error; + + if (header.main_section < 0) + goto end; + + for (section = abfd->sections; section != NULL; section = section->next) + if ((section->index + 1) == header.main_section) + break; + + if (section == NULL) + goto error; + + abfd->start_address = section->vma + header.main_offset; + + end: + if (loaderbuf != NULL) + free (loaderbuf); + return 0; + + error: + if (loaderbuf != NULL) + free (loaderbuf); + return -1; +} + +int +bfd_pef_scan (abfd, header, mdata) + bfd *abfd; + bfd_pef_header *header; + bfd_pef_data_struct *mdata; +{ + unsigned int i; + enum bfd_architecture cputype; + unsigned long cpusubtype; + + mdata->header = *header; + + bfd_pef_convert_architecture (header->architecture, &cputype, &cpusubtype); + if (cputype == bfd_arch_unknown) + { + fprintf (stderr, "bfd_pef_scan: unknown architecture 0x%lx\n", + header->architecture); + return -1; + } + bfd_set_arch_mach (abfd, cputype, cpusubtype); + + mdata->header = *header; + + abfd->flags = (abfd->xvec->object_flags + | (abfd->flags & (BFD_IN_MEMORY | BFD_IO_FUNCS))); + + if (header->section_count != 0) + { + mdata->sections = + ((bfd_pef_section *) + bfd_alloc (abfd, header->section_count * sizeof (bfd_pef_section))); + + if (mdata->sections == NULL) + return -1; + + for (i = 0; i < header->section_count; i++) + { + bfd_pef_section *cur = &mdata->sections[i]; + cur->header_offset = 40 + (i * 28); + if (bfd_pef_scan_section (abfd, cur) < 0) + return -1; + } + } + + if (bfd_pef_scan_start_address (abfd) < 0) + { +#if 0 + fprintf (stderr, "bfd_pef_scan: unable to scan start address: %s\n", + bfd_errmsg (bfd_get_error ())); + return -1; +#endif + } + + abfd->tdata.pef_data = mdata; + + return 0; +} + +static int +bfd_pef_read_header (abfd, header) + bfd *abfd; + bfd_pef_header *header; +{ + unsigned char buf[40]; + + bfd_seek (abfd, 0, SEEK_SET); + + if (bfd_bread ((PTR) buf, 40, abfd) != 40) + return -1; + + header->tag1 = bfd_getb32 (buf); + header->tag2 = bfd_getb32 (buf + 4); + header->architecture = bfd_getb32 (buf + 8); + header->format_version = bfd_getb32 (buf + 12); + header->timestamp = bfd_getb32 (buf + 16); + header->old_definition_version = bfd_getb32 (buf + 20); + header->old_implementation_version = bfd_getb32 (buf + 24); + header->current_version = bfd_getb32 (buf + 28); + header->section_count = bfd_getb32 (buf + 32) + 1; + header->instantiated_section_count = bfd_getb32 (buf + 34); + header->reserved = bfd_getb32 (buf + 36); + + return 0; +} + +static const bfd_target * +bfd_pef_object_p (abfd) + bfd *abfd; +{ + struct bfd_preserve preserve; + bfd_pef_header header; + + preserve.marker = NULL; + if (bfd_pef_read_header (abfd, &header) != 0) + goto wrong; + + if (header.tag1 != BFD_PEF_TAG1 || header.tag2 != BFD_PEF_TAG2) + goto wrong; + + preserve.marker = bfd_zalloc (abfd, sizeof (bfd_pef_data_struct)); + if (preserve.marker == NULL + || !bfd_preserve_save (abfd, &preserve)) + goto fail; + + if (bfd_pef_scan (abfd, &header, + (bfd_pef_data_struct *) preserve.marker) != 0) + goto wrong; + + bfd_preserve_finish (abfd, &preserve); + return abfd->xvec; + + wrong: + bfd_set_error (bfd_error_wrong_format); + + fail: + if (preserve.marker != NULL) + bfd_preserve_restore (abfd, &preserve); + return NULL; +} + +static int bfd_pef_parse_traceback_tables (abfd, sec, buf, len, nsym, csym) + bfd *abfd; + asection *sec; + unsigned char *buf; + size_t len; + long *nsym; + asymbol **csym; +{ + char *name; + + asymbol function; + asymbol traceback; + + const char *const tbprefix = "__traceback_"; + size_t tbnamelen; + + size_t pos = 0; + unsigned long count = 0; + int ret; + + for (;;) + { + /* We're reading symbols two at a time. */ + if (csym && ((csym[count] == NULL) || (csym[count + 1] == NULL))) + break; + + pos += 3; + pos -= (pos % 4); + + while ((pos + 4) <= len) + { + if (bfd_getb32 (buf + pos) == 0) + break; + pos += 4; + } + + if ((pos + 4) > len) + break; + + ret = bfd_pef_parse_traceback_table (abfd, sec, buf, len, pos + 4, + &function, 0); + if (ret < 0) + { + /* Skip over 0x0L to advance to next possible traceback table. */ + pos += 4; + continue; + } + + BFD_ASSERT (function.name != NULL); + + /* Don't bother to compute the name if we are just + counting symbols. */ + + if (csym) + { + tbnamelen = strlen (tbprefix) + strlen (function.name); + name = bfd_alloc (abfd, tbnamelen + 1); + if (name == NULL) + { + bfd_release (abfd, (PTR) function.name); + function.name = NULL; + break; + } + snprintf (name, tbnamelen + 1, "%s%s", tbprefix, function.name); + traceback.name = name; + traceback.value = pos; + traceback.the_bfd = abfd; + traceback.section = sec; + traceback.flags = 0; + traceback.udata.i = ret; + + *(csym[count]) = function; + *(csym[count + 1]) = traceback; + } + + pos += ret; + count += 2; + } + + *nsym = count; + return 0; +} + +static int bfd_pef_parse_function_stub (abfd, buf, len, offset) + bfd *abfd ATTRIBUTE_UNUSED; + unsigned char *buf; + size_t len; + unsigned long *offset; +{ + BFD_ASSERT (len == 24); + + if ((bfd_getb32 (buf) & 0xffff0000) != 0x81820000) + return -1; + if (bfd_getb32 (buf + 4) != 0x90410014) + return -1; + if (bfd_getb32 (buf + 8) != 0x800c0000) + return -1; + if (bfd_getb32 (buf + 12) != 0x804c0004) + return -1; + if (bfd_getb32 (buf + 16) != 0x7c0903a6) + return -1; + if (bfd_getb32 (buf + 20) != 0x4e800420) + return -1; + + if (offset != NULL) + *offset = (bfd_getb32 (buf) & 0x0000ffff) / 4; + + return 0; +} + +static int bfd_pef_parse_function_stubs (abfd, codesec, codebuf, codelen, + loaderbuf, loaderlen, nsym, csym) + bfd *abfd; + asection *codesec; + unsigned char *codebuf; + size_t codelen; + unsigned char *loaderbuf; + size_t loaderlen; + unsigned long *nsym; + asymbol **csym; +{ + const char *const sprefix = "__stub_"; + + size_t codepos = 0; + unsigned long count = 0; + + bfd_pef_loader_header header; + bfd_pef_imported_library *libraries = NULL; + bfd_pef_imported_symbol *imports = NULL; + + unsigned long i; + int ret; + + if (loaderlen < 56) + goto error; + + ret = bfd_pef_parse_loader_header (abfd, loaderbuf, 56, &header); + if (ret < 0) + goto error; + + libraries = (bfd_pef_imported_library *) bfd_malloc + (header.imported_library_count * sizeof (bfd_pef_imported_library)); + imports = (bfd_pef_imported_symbol *) bfd_malloc + (header.total_imported_symbol_count * sizeof (bfd_pef_imported_symbol)); + + if (loaderlen < (56 + (header.imported_library_count * 24))) + goto error; + for (i = 0; i < header.imported_library_count; i++) + { + ret = bfd_pef_parse_imported_library + (abfd, loaderbuf + 56 + (i * 24), 24, &libraries[i]); + if (ret < 0) + goto error; + } + + if (loaderlen < (56 + (header.imported_library_count * 24) + + (header.total_imported_symbol_count * 4))) + goto error; + for (i = 0; i < header.total_imported_symbol_count; i++) + { + ret = (bfd_pef_parse_imported_symbol + (abfd, + loaderbuf + 56 + (header.imported_library_count * 24) + (i * 4), + 4, &imports[i])); + if (ret < 0) + goto error; + } + + codepos = 0; + + for (;;) + { + asymbol sym; + const char *symname; + char *name; + unsigned long index; + int ret; + + if (csym && (csym[count] == NULL)) + break; + + codepos += 3; + codepos -= (codepos % 4); + + while ((codepos + 4) <= codelen) + { + if ((bfd_getb32 (codebuf + codepos) & 0xffff0000) == 0x81820000) + break; + codepos += 4; + } + + if ((codepos + 4) > codelen) + break; + + ret = bfd_pef_parse_function_stub (abfd, codebuf + codepos, 24, &index); + if (ret < 0) + { + codepos += 24; + continue; + } + + if (index >= header.total_imported_symbol_count) + { + codepos += 24; + continue; + } + + { + size_t max, namelen; + const char *s; + + if (loaderlen < (header.loader_strings_offset + imports[index].name)) + goto error; + + max = loaderlen - (header.loader_strings_offset + imports[index].name); + symname = loaderbuf + header.loader_strings_offset + imports[index].name; + namelen = 0; + for (s = symname; s < (symname + max); s++) + { + if (*s == '\0') + break; + if (! ISPRINT (*s)) + goto error; + namelen++; + } + if (*s != '\0') + goto error; + + name = bfd_alloc (abfd, strlen (sprefix) + namelen + 1); + if (name == NULL) + break; + + snprintf (name, strlen (sprefix) + namelen + 1, "%s%s", + sprefix, symname); + sym.name = name; + } + + sym.value = codepos; + sym.the_bfd = abfd; + sym.section = codesec; + sym.flags = 0; + sym.udata.i = 0; + + codepos += 24; + + if (csym != NULL) + *(csym[count]) = sym; + + count++; + } + + goto end; + + end: + if (libraries != NULL) + free (libraries); + if (imports != NULL) + free (imports); + *nsym = count; + return 0; + + error: + if (libraries != NULL) + free (libraries); + if (imports != NULL) + free (imports); + *nsym = count; + return -1; +} + +static long bfd_pef_parse_symbols (abfd, csym) + bfd *abfd; + asymbol **csym; +{ + unsigned long count = 0; + + asection *codesec = NULL; + unsigned char *codebuf = NULL; + size_t codelen = 0; + + asection *loadersec = NULL; + unsigned char *loaderbuf = NULL; + size_t loaderlen = 0; + + codesec = bfd_get_section_by_name (abfd, "code"); + if (codesec != NULL) + { + codelen = bfd_section_size (abfd, codesec); + codebuf = (unsigned char *) bfd_malloc (codelen); + if (bfd_seek (abfd, codesec->filepos, SEEK_SET) < 0) + goto end; + if (bfd_bread ((PTR) codebuf, codelen, abfd) != codelen) + goto end; + } + + loadersec = bfd_get_section_by_name (abfd, "loader"); + if (loadersec != NULL) + { + loaderlen = bfd_section_size (abfd, loadersec); + loaderbuf = (unsigned char *) bfd_malloc (loaderlen); + if (bfd_seek (abfd, loadersec->filepos, SEEK_SET) < 0) + goto end; + if (bfd_bread ((PTR) loaderbuf, loaderlen, abfd) != loaderlen) + goto end; + } + + count = 0; + if (codesec != NULL) + { + unsigned long ncount = 0; + bfd_pef_parse_traceback_tables (abfd, codesec, codebuf, codelen, + &ncount, csym); + count += ncount; + } + + if ((codesec != NULL) && (loadersec != NULL)) + { + unsigned long ncount = 0; + bfd_pef_parse_function_stubs + (abfd, codesec, codebuf, codelen, loaderbuf, loaderlen, &ncount, + (csym != NULL) ? (csym + count) : NULL); + count += ncount; + } + + if (csym != NULL) + csym[count] = NULL; + + end: + if (codebuf != NULL) + free (codebuf); + + if (loaderbuf != NULL) + free (loaderbuf); + + return count; +} + +static long +bfd_pef_count_symbols (abfd) + bfd *abfd; +{ + return bfd_pef_parse_symbols (abfd, NULL); +} + +static long +bfd_pef_get_symtab_upper_bound (abfd) + bfd *abfd; +{ + long nsyms = bfd_pef_count_symbols (abfd); + if (nsyms < 0) + return nsyms; + return ((nsyms + 1) * sizeof (asymbol *)); +} + +static long +bfd_pef_canonicalize_symtab (abfd, alocation) + bfd *abfd; + asymbol **alocation; +{ + long i; + asymbol *syms; + long ret; + + long nsyms = bfd_pef_count_symbols (abfd); + if (nsyms < 0) + return nsyms; + + syms = bfd_alloc (abfd, nsyms * sizeof (asymbol)); + if (syms == NULL) + return -1; + + for (i = 0; i < nsyms; i++) + alocation[i] = &syms[i]; + + alocation[nsyms] = NULL; + + ret = bfd_pef_parse_symbols (abfd, alocation); + if (ret != nsyms) + return 0; + + return ret; +} + +static asymbol * +bfd_pef_make_empty_symbol (abfd) + bfd *abfd; +{ + return (asymbol *) bfd_alloc (abfd, sizeof (asymbol)); +} + +static void +bfd_pef_get_symbol_info (abfd, symbol, ret) + bfd *abfd ATTRIBUTE_UNUSED; + asymbol *symbol; + symbol_info *ret; +{ + bfd_symbol_info (symbol, ret); +} + +static int +bfd_pef_sizeof_headers (abfd, exec) + bfd *abfd ATTRIBUTE_UNUSED; + bfd_boolean exec ATTRIBUTE_UNUSED; +{ + return 0; +} + +const bfd_target pef_vec = +{ + "pef", /* name */ + bfd_target_pef_flavour, /* flavour */ + BFD_ENDIAN_BIG, /* byteorder */ + BFD_ENDIAN_BIG, /* header_byteorder */ + (HAS_RELOC | EXEC_P | /* object flags */ + HAS_LINENO | HAS_DEBUG | + HAS_SYMS | HAS_LOCALS | DYNAMIC | WP_TEXT | D_PAGED), + (SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_CODE | SEC_DATA + | SEC_ROM | SEC_HAS_CONTENTS), /* section_flags */ + 0, /* symbol_leading_char */ + ' ', /* ar_pad_char */ + 16, /* ar_max_namelen */ + bfd_getb64, bfd_getb_signed_64, bfd_putb64, + bfd_getb32, bfd_getb_signed_32, bfd_putb32, + bfd_getb16, bfd_getb_signed_16, bfd_putb16, /* data */ + bfd_getb64, bfd_getb_signed_64, bfd_putb64, + bfd_getb32, bfd_getb_signed_32, bfd_putb32, + bfd_getb16, bfd_getb_signed_16, bfd_putb16, /* hdrs */ + { /* bfd_check_format */ + _bfd_dummy_target, + bfd_pef_object_p, /* bfd_check_format */ + _bfd_dummy_target, + _bfd_dummy_target, + }, + { /* bfd_set_format */ + bfd_false, + bfd_pef_mkobject, + bfd_false, + bfd_false, + }, + { /* bfd_write_contents */ + bfd_false, + bfd_true, + bfd_false, + bfd_false, + }, + + BFD_JUMP_TABLE_GENERIC (bfd_pef), + BFD_JUMP_TABLE_COPY (_bfd_generic), + BFD_JUMP_TABLE_CORE (_bfd_nocore), + BFD_JUMP_TABLE_ARCHIVE (_bfd_noarchive), + BFD_JUMP_TABLE_SYMBOLS (bfd_pef), + BFD_JUMP_TABLE_RELOCS (bfd_pef), + BFD_JUMP_TABLE_WRITE (bfd_pef), + BFD_JUMP_TABLE_LINK (bfd_pef), + BFD_JUMP_TABLE_DYNAMIC (_bfd_nodynamic), + + NULL, + + NULL +}; + +#define bfd_pef_xlib_close_and_cleanup _bfd_generic_close_and_cleanup +#define bfd_pef_xlib_bfd_free_cached_info _bfd_generic_bfd_free_cached_info +#define bfd_pef_xlib_new_section_hook _bfd_generic_new_section_hook +#define bfd_pef_xlib_get_section_contents _bfd_generic_get_section_contents +#define bfd_pef_xlib_set_section_contents _bfd_generic_set_section_contents +#define bfd_pef_xlib_get_section_contents_in_window _bfd_generic_get_section_contents_in_window +#define bfd_pef_xlib_set_section_contents_in_window _bfd_generic_set_section_contents_in_window + +static int +bfd_pef_xlib_read_header (abfd, header) + bfd *abfd; + bfd_pef_xlib_header *header; +{ + unsigned char buf[76]; + + bfd_seek (abfd, 0, SEEK_SET); + + if (bfd_bread ((PTR) buf, 76, abfd) != 76) + return -1; + + header->tag1 = bfd_getb32 (buf); + header->tag2 = bfd_getb32 (buf + 4); + header->current_format = bfd_getb32 (buf + 8); + header->container_strings_offset = bfd_getb32 (buf + 12); + header->export_hash_offset = bfd_getb32 (buf + 16); + header->export_key_offset = bfd_getb32 (buf + 20); + header->export_symbol_offset = bfd_getb32 (buf + 24); + header->export_names_offset = bfd_getb32 (buf + 28); + header->export_hash_table_power = bfd_getb32 (buf + 32); + header->exported_symbol_count = bfd_getb32 (buf + 36); + header->frag_name_offset = bfd_getb32 (buf + 40); + header->frag_name_length = bfd_getb32 (buf + 44); + header->dylib_path_offset = bfd_getb32 (buf + 48); + header->dylib_path_length = bfd_getb32 (buf + 52); + header->cpu_family = bfd_getb32 (buf + 56); + header->cpu_model = bfd_getb32 (buf + 60); + header->date_time_stamp = bfd_getb32 (buf + 64); + header->current_version = bfd_getb32 (buf + 68); + header->old_definition_version = bfd_getb32 (buf + 72); + header->old_implementation_version = bfd_getb32 (buf + 76); + + return 0; +} + +int +bfd_pef_xlib_scan (abfd, header) + bfd *abfd; + bfd_pef_xlib_header *header; +{ + bfd_pef_xlib_data_struct *mdata = NULL; + + mdata = ((bfd_pef_xlib_data_struct *) + bfd_alloc (abfd, sizeof (bfd_pef_xlib_data_struct))); + if (mdata == NULL) + return -1; + + mdata->header = *header; + + abfd->flags = (abfd->xvec->object_flags + | (abfd->flags & (BFD_IN_MEMORY | BFD_IO_FUNCS))); + + abfd->tdata.pef_xlib_data = mdata; + + return 0; +} + +static const bfd_target * +bfd_pef_xlib_object_p (abfd) + bfd *abfd; +{ + struct bfd_preserve preserve; + bfd_pef_xlib_header header; + + if (bfd_pef_xlib_read_header (abfd, &header) != 0) + { + bfd_set_error (bfd_error_wrong_format); + return NULL; + } + + if ((header.tag1 != BFD_PEF_XLIB_TAG1) + || ((header.tag2 != BFD_PEF_VLIB_TAG2) + && (header.tag2 != BFD_PEF_BLIB_TAG2))) + { + bfd_set_error (bfd_error_wrong_format); + return NULL; + } + + if (! bfd_preserve_save (abfd, &preserve)) + { + bfd_set_error (bfd_error_wrong_format); + return NULL; + } + + if (bfd_pef_xlib_scan (abfd, &header) != 0) + { + bfd_preserve_restore (abfd, &preserve); + bfd_set_error (bfd_error_wrong_format); + return NULL; + } + + bfd_preserve_finish (abfd, &preserve); + return abfd->xvec; +} + +const bfd_target pef_xlib_vec = +{ + "pef-xlib", /* name */ + bfd_target_pef_xlib_flavour, /* flavour */ + BFD_ENDIAN_BIG, /* byteorder */ + BFD_ENDIAN_BIG, /* header_byteorder */ + (HAS_RELOC | EXEC_P | /* object flags */ + HAS_LINENO | HAS_DEBUG | + HAS_SYMS | HAS_LOCALS | DYNAMIC | WP_TEXT | D_PAGED), + (SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_CODE | SEC_DATA + | SEC_ROM | SEC_HAS_CONTENTS), /* section_flags */ + 0, /* symbol_leading_char */ + ' ', /* ar_pad_char */ + 16, /* ar_max_namelen */ + bfd_getb64, bfd_getb_signed_64, bfd_putb64, + bfd_getb32, bfd_getb_signed_32, bfd_putb32, + bfd_getb16, bfd_getb_signed_16, bfd_putb16, /* data */ + bfd_getb64, bfd_getb_signed_64, bfd_putb64, + bfd_getb32, bfd_getb_signed_32, bfd_putb32, + bfd_getb16, bfd_getb_signed_16, bfd_putb16, /* hdrs */ + { /* bfd_check_format */ + _bfd_dummy_target, + bfd_pef_xlib_object_p, /* bfd_check_format */ + _bfd_dummy_target, + _bfd_dummy_target, + }, + { /* bfd_set_format */ + bfd_false, + bfd_pef_mkobject, + bfd_false, + bfd_false, + }, + { /* bfd_write_contents */ + bfd_false, + bfd_true, + bfd_false, + bfd_false, + }, + + BFD_JUMP_TABLE_GENERIC (bfd_pef_xlib), + BFD_JUMP_TABLE_COPY (_bfd_generic), + BFD_JUMP_TABLE_CORE (_bfd_nocore), + BFD_JUMP_TABLE_ARCHIVE (_bfd_noarchive), + BFD_JUMP_TABLE_SYMBOLS (_bfd_nosymbols), + BFD_JUMP_TABLE_RELOCS (_bfd_norelocs), + BFD_JUMP_TABLE_WRITE (_bfd_nowrite), + BFD_JUMP_TABLE_LINK (_bfd_nolink), + BFD_JUMP_TABLE_DYNAMIC (_bfd_nodynamic), + + NULL, + + NULL +}; diff --git a/bfd/pef.h b/bfd/pef.h new file mode 100644 index 0000000..caeb710 --- /dev/null +++ b/bfd/pef.h @@ -0,0 +1,186 @@ +/* PEF support for BFD. + Copyright 1999, 2000, 2001, 2002 + Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include "bfd.h" + +#include + +struct bfd_pef_header +{ + unsigned long tag1; + unsigned long tag2; + unsigned long architecture; + unsigned long format_version; + unsigned long timestamp; + unsigned long old_definition_version; + unsigned long old_implementation_version; + unsigned long current_version; + unsigned short section_count; + unsigned short instantiated_section_count; + unsigned long reserved; +}; +typedef struct bfd_pef_header bfd_pef_header; + +struct bfd_pef_loader_header +{ + long main_section; + unsigned long main_offset; + long init_section; + unsigned long init_offset; + long term_section; + unsigned long term_offset; + unsigned long imported_library_count; + unsigned long total_imported_symbol_count; + unsigned long reloc_section_count; + unsigned long reloc_instr_offset; + unsigned long loader_strings_offset; + unsigned long export_hash_offset; + unsigned long export_hash_table_power; + unsigned long exported_symbol_count; +}; +typedef struct bfd_pef_loader_header bfd_pef_loader_header; + +struct bfd_pef_imported_library +{ + unsigned long name_offset; + unsigned long old_implementation_version; + unsigned long current_version; + unsigned long imported_symbol_count; + unsigned long first_imported_symbol; + unsigned char options; + unsigned char reserved_a; + unsigned short reserved_b; +}; +typedef struct bfd_pef_imported_library bfd_pef_imported_library; + +enum bfd_pef_imported_library_options + { + BFD_PEF_WEAK_IMPORT_LIB = 0x40, + BFD_PEF_INIT_LIB_BEFORE = 0x80 + }; + +struct bfd_pef_imported_symbol +{ + unsigned char class; + unsigned long name; +}; +typedef struct bfd_pef_imported_symbol bfd_pef_imported_symbol; + +enum bfd_pef_imported_symbol_class + { + BFD_PEF_CODE_SYMBOL = 0x00, + BFD_PEF_DATA_SYMBOL = 0x01, + BFD_PEF_TVECTOR_SYMBOL = 0x02, + BFD_PEF_TOC_SYMBOL = 0x03, + BFD_PEF_GLUE_SYMBOL = 0x04, + BFD_PEF_UNDEFINED_SYMBOL = 0x0F, + BFD_PEF_WEAK_IMPORT_SYMBOL_MASK = 0x80 + }; + +#define BFD_PEF_TAG1 0x4A6F7921 /* 'Joy!' */ +#define BFD_PEF_TAG2 0x70656666 /* 'peff' */ + +#define BFD_PEF_VERSION 0x00000001 + +struct bfd_pef_section +{ + long name_offset; + unsigned long header_offset; + unsigned long default_address; + unsigned long total_length; + unsigned long unpacked_length; + unsigned long container_length; + unsigned long container_offset; + unsigned char section_kind; + unsigned char share_kind; + unsigned char alignment; + unsigned char reserved; + asection *bfd_section; +}; +typedef struct bfd_pef_section bfd_pef_section; + +#define BFD_PEF_SECTION_CODE 0 +#define BFD_PEF_SECTION_UNPACKED_DATA 1 +#define BFD_PEF_SECTION_PACKED_DATA 2 +#define BFD_PEF_SECTION_CONSTANT 3 +#define BFD_PEF_SECTION_LOADER 4 +#define BFD_PEF_SECTION_DEBUG 5 +#define BFD_PEF_SECTION_EXEC_DATA 6 +#define BFD_PEF_SECTION_EXCEPTION 7 +#define BFD_PEF_SECTION_TRACEBACK 8 + +#define BFD_PEF_SHARE_PROCESS 1 +#define BFD_PEF_SHARE_GLOBAL 4 +#define BFD_PEF_SHARE_PROTECTED 5 + +struct bfd_pef_data_struct +{ + bfd_pef_header header; + bfd_pef_section *sections; + bfd *ibfd; +}; +typedef struct bfd_pef_data_struct bfd_pef_data_struct; + +#define BFD_PEF_XLIB_TAG1 0xF04D6163 /* '?Mac' */ +#define BFD_PEF_VLIB_TAG2 0x564C6962 /* 'VLib' */ +#define BFD_PEF_BLIB_TAG2 0x424C6962 /* 'BLib' */ + +#define BFD_PEF_XLIB_VERSION 0x00000001 + +struct bfd_pef_xlib_header +{ + unsigned long tag1; + unsigned long tag2; + unsigned long current_format; + unsigned long container_strings_offset; + unsigned long export_hash_offset; + unsigned long export_key_offset; + unsigned long export_symbol_offset; + unsigned long export_names_offset; + unsigned long export_hash_table_power; + unsigned long exported_symbol_count; + + unsigned long frag_name_offset; + unsigned long frag_name_length; + unsigned long dylib_path_offset; + unsigned long dylib_path_length; + unsigned long cpu_family; + unsigned long cpu_model; + unsigned long date_time_stamp; + unsigned long current_version; + unsigned long old_definition_version; + unsigned long old_implementation_version; +}; +typedef struct bfd_pef_xlib_header bfd_pef_xlib_header; + +struct bfd_pef_xlib_data_struct +{ + bfd_pef_xlib_header header; +}; +typedef struct bfd_pef_xlib_data_struct bfd_pef_xlib_data_struct; + +int bfd_pef_parse_loader_header PARAMS ((bfd *, unsigned char *, size_t, bfd_pef_loader_header *)); +int bfd_pef_print_loader_section PARAMS ((bfd *, FILE *)); +void bfd_pef_print_loader_header PARAMS ((bfd *, bfd_pef_loader_header *, FILE *)); +int bfd_pef_parse_imported_library PARAMS ((bfd *, unsigned char *, size_t, bfd_pef_imported_library *)); +int bfd_pef_parse_imported_symbol PARAMS ((bfd *, unsigned char *, size_t, bfd_pef_imported_symbol *)); +int bfd_pef_scan_section PARAMS ((bfd *, bfd_pef_section *)); +int bfd_pef_scan_start_address PARAMS ((bfd *)); +int bfd_pef_scan PARAMS ((bfd *, bfd_pef_header *, bfd_pef_data_struct *)); diff --git a/bfd/po/ro.po b/bfd/po/ro.po new file mode 100644 index 0000000..5706e4f --- /dev/null +++ b/bfd/po/ro.po @@ -0,0 +1,3026 @@ +# Mesajele în limba românã pentru pachetul bfd. +# Copyright (C) 2003 Free Software Foundation, Inc. +# Eugen Hoanca , 2003. +# +msgid "" +msgstr "" +"Project-Id-Version: bfd 2.14rel030712\n" +"POT-Creation-Date: 2003-07-11 13:53+0930\n" +"PO-Revision-Date: 2003-11-25 08:39+0200\n" +"Last-Translator: Eugen Hoanca \n" +"Language-Team: Romanian \n" +"MIME-Version: 1.0\n" +"Content-Type: text/plain; charset=ISO-8859-2\n" +"Content-Transfer-Encoding: 8bit\n" + +#: aout-adobe.c:204 +#, c-format +msgid "%s: Unknown section type in a.out.adobe file: %x\n" +msgstr "%s: Tip secþiune necunoscut în fiºier adobe a.out: %x\n" + +#: aout-cris.c:207 +#, c-format +msgid "%s: Invalid relocation type exported: %d" +msgstr "%s: Tip de relocare exportat invalid: %d" + +#: aout-cris.c:251 +#, c-format +msgid "%s: Invalid relocation type imported: %d" +msgstr "%s: Tip de relocare importat invalid: %d" + +#: aout-cris.c:262 +#, c-format +msgid "%s: Bad relocation record imported: %d" +msgstr "%s: Înregistrare de relocare greºitã importatã: %d" + +#: aoutx.h:1295 aoutx.h:1716 +#, c-format +msgid "%s: can not represent section `%s' in a.out object file format" +msgstr "%s: nu se poate reprezenta secþiunea `%s' în format de fiºier obiect a.out" + +#: aoutx.h:1682 +#, c-format +msgid "%s: can not represent section for symbol `%s' in a.out object file format" +msgstr "%s: nu se poate reprezenta secþiunea pentru simbolul `%s' în formatul de fiºier obiect a.out" + +#: aoutx.h:1684 +msgid "*unknown*" +msgstr "*necunoscut*" + +#: aoutx.h:3776 +#, c-format +msgid "%s: relocatable link from %s to %s not supported" +msgstr "%s: legãtura relocalizabilã din %s cãtre %s nesuportatã" + +#: archive.c:1751 +msgid "Warning: writing archive was slow: rewriting timestamp\n" +msgstr "Avertisment: scrierea arhivei a fost lentã: se rescrie marcajul de timp(timestamp)\n" + +#: archive.c:2014 +msgid "Reading archive file mod timestamp" +msgstr "Citirea fiºierului arhivã mod marcaj de timp" + +#: archive.c:2040 +msgid "Writing updated armap timestamp" +msgstr "Scriere marcaj de timp armap înnoit" + +#: bfd.c:280 +msgid "No error" +msgstr "Nici o eroare" + +#: bfd.c:281 +msgid "System call error" +msgstr "Eroare apel sistem" + +#: bfd.c:282 +msgid "Invalid bfd target" +msgstr "Þintã bfd invalidã" + +#: bfd.c:283 +msgid "File in wrong format" +msgstr "Fiºier în format eronat" + +#: bfd.c:284 +msgid "Archive object file in wrong format" +msgstr "Fiºier obiect arhivã în format eronat" + +#: bfd.c:285 +msgid "Invalid operation" +msgstr "Operaþie invalidã" + +#: bfd.c:286 +msgid "Memory exhausted" +msgstr "Memorie plinã" + +#: bfd.c:287 +msgid "No symbols" +msgstr "Nici un simbol" + +#: bfd.c:288 +msgid "Archive has no index; run ranlib to add one" +msgstr "Arhiva nu are nici un index.; rulaþi ranlib pentru a adãuga unul" + +#: bfd.c:289 +msgid "No more archived files" +msgstr "Nu mai existã fiºiere arhivate" + +#: bfd.c:290 +msgid "Malformed archive" +msgstr "Arhivã malformatã" + +#: bfd.c:291 +msgid "File format not recognized" +msgstr "Formatul de fiºier nu a fost recunoscut" + +#: bfd.c:292 +msgid "File format is ambiguous" +msgstr "Formatul de fiºier este ambiguu" + +#: bfd.c:293 +msgid "Section has no contents" +msgstr "Secþiunea nu are conþinut" + +#: bfd.c:294 +msgid "Nonrepresentable section on output" +msgstr "Secþiune de output nereprezentabilã" + +#: bfd.c:295 +msgid "Symbol needs debug section which does not exist" +msgstr "Simbolul necesitã secþiune de debug care nu existã" + +#: bfd.c:296 +msgid "Bad value" +msgstr "Valoare eronatã" + +#: bfd.c:297 +msgid "File truncated" +msgstr "Fiºier trunchiat" + +#: bfd.c:298 +msgid "File too big" +msgstr "Fiºier prea mare" + +#: bfd.c:299 +msgid "#" +msgstr "#" + +#: bfd.c:687 +#, c-format +msgid "BFD %s assertion fail %s:%d" +msgstr "Aserþiunea BFD %s a eºuat %s:%d" + +#: bfd.c:703 +#, c-format +msgid "BFD %s internal error, aborting at %s line %d in %s\n" +msgstr "Eroare interna BFD %s, se renunþã la %s linia %d în %s\n" + +#: bfd.c:707 +#, c-format +msgid "BFD %s internal error, aborting at %s line %d\n" +msgstr "Eroare internã BFD %s, se renunþã la %s linia %d\n" + +#: bfd.c:709 +msgid "Please report this bug.\n" +msgstr "Vã rugãm raportaþi acest bug.\n" + +#: bfdwin.c:202 +#, c-format +msgid "not mapping: data=%lx mapped=%d\n" +msgstr "nu se mapeazã: data=%lx mapat =%d\n" + +#: bfdwin.c:205 +msgid "not mapping: env var not set\n" +msgstr "nu se mapeazã: variabila env nu este setatã\n" + +#: binary.c:306 +#, c-format +msgid "Warning: Writing section `%s' to huge (ie negative) file offset 0x%lx." +msgstr "Avertisment: Scrierea secþiunii `%s' spre offset de fiºier imens (sau negativ) 0x%lx" + +#: coff-a29k.c:120 +msgid "Missing IHCONST" +msgstr "IHCONST lipsã" + +#: coff-a29k.c:181 +msgid "Missing IHIHALF" +msgstr "IHHALF lipsã" + +#: coff-a29k.c:213 coff-or32.c:236 +msgid "Unrecognized reloc" +msgstr "Reloc necunoscut" + +#: coff-a29k.c:409 +msgid "missing IHCONST reloc" +msgstr "IHCONST reloc lipsã" + +#: coff-a29k.c:499 +msgid "missing IHIHALF reloc" +msgstr "IHIHALF reloc lipsã" + +#: coff-alpha.c:884 coff-alpha.c:921 coff-alpha.c:1992 coff-mips.c:1397 +msgid "GP relative relocation used when GP not defined" +msgstr "Relocare relativã GP folositã când GP nu este definit" + +#: coff-alpha.c:1488 +msgid "using multiple gp values" +msgstr "folosire de valori multiple gp" + +#: coff-arm.c:1066 elf32-arm.h:294 +#, c-format +msgid "%s: unable to find THUMB glue '%s' for `%s'" +msgstr "%s: nu s-a putut gãsi legãtura(glue) THUMB `%s' pentru `%s'" + +#: coff-arm.c:1096 elf32-arm.h:329 +#, c-format +msgid "%s: unable to find ARM glue '%s' for `%s'" +msgstr "%s: nu s-a putut gãsi legãtura(glue) ARM `%s' pentru `%s'" + +#: coff-arm.c:1394 coff-arm.c:1489 elf32-arm.h:892 elf32-arm.h:999 +#, c-format +msgid "%s(%s): warning: interworking not enabled." +msgstr "%s(%s): avertisment: interlucrul(interworking) nu este activat" + +#: coff-arm.c:1398 elf32-arm.h:1002 +#, c-format +msgid " first occurrence: %s: arm call to thumb" +msgstr " prima gãsire: %s: apelare braþ(arm) cãtre deget(thumb)" + +#: coff-arm.c:1493 elf32-arm.h:895 +#, c-format +msgid " first occurrence: %s: thumb call to arm" +msgstr " prima gãsire: %s: apelare deget(thumb) cãtre braþ(arm)" + +#: coff-arm.c:1496 +msgid " consider relinking with --support-old-code enabled" +msgstr " luaþi în considerare relinkuirea cu --support-old-code activat" + +#: coff-arm.c:1788 coff-tic80.c:687 cofflink.c:3038 +#, c-format +msgid "%s: bad reloc address 0x%lx in section `%s'" +msgstr "%s: adresã eronatã de relocare 0x%lx în secþiunea `%s'" + +#: coff-arm.c:2132 +#, c-format +msgid "%s: illegal symbol index in reloc: %d" +msgstr "%s: index ilegal de simbol în reloc: %d" + +#: coff-arm.c:2265 +#, c-format +msgid "ERROR: %s is compiled for APCS-%d, whereas %s is compiled for APCS-%d" +msgstr "EROARE: %s este compilat pentru APCS-%d, pe când %s e compilat pentru APCS-%d" + +#: coff-arm.c:2280 elf32-arm.h:2328 +#, c-format +msgid "ERROR: %s passes floats in float registers, whereas %s passes them in integer registers" +msgstr "EROARE: %s trimite float în regiºtrii de float, pe când %s îi trimite în regiºtrii de integer" + +#: coff-arm.c:2283 elf32-arm.h:2333 +#, c-format +msgid "ERROR: %s passes floats in integer registers, whereas %s passes them in float registers" +msgstr "EROARE: %s trimite integer în regiºtrii de integer, pe când %s îi trimite în regiºtrii de float" + +#: coff-arm.c:2298 +#, c-format +msgid "ERROR: %s is compiled as position independent code, whereas target %s is absolute position" +msgstr "EROARE: %s este compilat ca ºi cod independent de poziþie,pe când þinta %seste poziþie absolutã" + +#: coff-arm.c:2301 +#, c-format +msgid "ERROR: %s is compiled as absolute position code, whereas target %s is position independent" +msgstr "EROARE: %s este compilat ca ºi cod poziþie absolutã,pe când þinta %seste independentã de poziþie" + +#: coff-arm.c:2330 elf32-arm.h:2405 +#, c-format +msgid "Warning: %s supports interworking, whereas %s does not" +msgstr "Avertisment: %s suportã interlucru(interworking), pe când %s nu suportã" + +#: coff-arm.c:2333 elf32-arm.h:2412 +#, c-format +msgid "Warning: %s does not support interworking, whereas %s does" +msgstr "Avertisment: %s nu suportã interlucru(interworking), pe când %s suportã" + +#: coff-arm.c:2360 +#, c-format +msgid "private flags = %x:" +msgstr "marcaje(flags) private = %x:" + +#: coff-arm.c:2368 elf32-arm.h:2467 +msgid " [floats passed in float registers]" +msgstr " [floats trecuþi în regiºtri de float]" + +#: coff-arm.c:2370 +msgid " [floats passed in integer registers]" +msgstr " [floats trecuþi în regiºtrii de integer]" + +#: coff-arm.c:2373 elf32-arm.h:2470 +msgid " [position independent]" +msgstr "[ independent de poziþie]" + +#: coff-arm.c:2375 +msgid " [absolute position]" +msgstr " [poziþie absolutã]" + +#: coff-arm.c:2379 +msgid " [interworking flag not initialised]" +msgstr " [marcajul(flag) de interlucru(interworking) nu este iniþializat]" + +#: coff-arm.c:2381 +msgid " [interworking supported]" +msgstr " [interlucru(interworking) suportat]" + +#: coff-arm.c:2383 +msgid " [interworking not supported]" +msgstr " [interlucru(interworking) nesuportat]" + +#: coff-arm.c:2431 elf32-arm.h:2150 +#, c-format +msgid "Warning: Not setting interworking flag of %s since it has already been specified as non-interworking" +msgstr "Avertisment: Nu se seteazã marcajul(flagu) de interlucru(interworking) al %s atâta timp cât a fost specificat ca non-interlucru(interworking)" + +#: coff-arm.c:2435 elf32-arm.h:2154 +#, c-format +msgid "Warning: Clearing the interworking flag of %s due to outside request" +msgstr "Avertisment: Se ºterge marcajul(flag) de interlucru(interworking) al %s datoritã unei cereri din afarã" + +#: coff-h8300.c:1096 +#, c-format +msgid "cannot handle R_MEM_INDIRECT reloc when using %s output" +msgstr "nu am putut mainpula(handle) relocarea R_MEM_INDIRECT în folosirea ieºirii(output) %s" + +#: coff-i960.c:137 coff-i960.c:486 +msgid "uncertain calling convention for non-COFF symbol" +msgstr "convenþie de apelare nesigurã pentru simbol non-COFF" + +#: coff-m68k.c:482 coff-mips.c:2394 elf32-m68k.c:2193 elf32-mips.c:1783 +msgid "unsupported reloc type" +msgstr "tip de relocare nesuportat" + +#: coff-mips.c:839 elf32-mips.c:1088 elf64-mips.c:1590 elfn32-mips.c:1554 +msgid "GP relative relocation when _gp not defined" +msgstr "Relocare relativã GP atâta timp cât _gp nu este definit" + +#. No other sections should appear in -membedded-pic +#. code. +#: coff-mips.c:2431 +msgid "reloc against unsupported section" +msgstr "relocare pe o secþiune nesuportatã" + +#: coff-mips.c:2439 +msgid "reloc not properly aligned" +msgstr "relocare incorect aliniatã" + +#: coff-rs6000.c:2790 +#, c-format +msgid "%s: unsupported relocation type 0x%02x" +msgstr "%s: tip de relocare nesuportat 0x%02x" + +#: coff-rs6000.c:2883 +#, c-format +msgid "%s: TOC reloc at 0x%x to symbol `%s' with no TOC entry" +msgstr "%s: relocare TOC la 0x%x cãtre simbolul `%s' fãrã nici o intrare TOC" + +#: coff-rs6000.c:3616 coff64-rs6000.c:2109 +#, c-format +msgid "%s: symbol `%s' has unrecognized smclas %d" +msgstr "%s: simbolul `%s' are un smclas necunoscut %d" + +#: coff-tic4x.c:170 coff-tic54x.c:288 coff-tic80.c:450 +#, c-format +msgid "Unrecognized reloc type 0x%x" +msgstr "Tip de relocare necunoscut 0x%x" + +#: coff-tic4x.c:218 coff-tic54x.c:373 coffcode.h:5045 +#, c-format +msgid "%s: warning: illegal symbol index %ld in relocs" +msgstr "%s: avertisment: index ilegal de simbol %ld în relocãri" + +#: coff-w65.c:364 +#, c-format +msgid "ignoring reloc %s\n" +msgstr "se ignorã reloc %s\n" + +#: coffcode.h:1108 +#, c-format +msgid "%s (%s): Section flag %s (0x%x) ignored" +msgstr "%s (%s): Marcajul(flag) de secþiune %s (0x%x) ignorat" + +#: coffcode.h:2214 +#, c-format +msgid "Unrecognized TI COFF target id '0x%x'" +msgstr "Id þintã TI COFF necunoscut `0x%x'" + +#: coffcode.h:4437 +#, c-format +msgid "%s: warning: illegal symbol index %ld in line numbers" +msgstr "%s: avertisment: index ilegal de simbol %ld în numãrul de linii" + +#: coffcode.h:4451 +#, c-format +msgid "%s: warning: duplicate line number information for `%s'" +msgstr "%s: avertisment: informaþie duplicat a numãrului de linii pentru `%s'" + +#: coffcode.h:4805 +#, c-format +msgid "%s: Unrecognized storage class %d for %s symbol `%s'" +msgstr "%s: Clasã de depozitare(storage) %d necunoscutã pentru %s simbolul `%s'" + +#: coffcode.h:4938 +#, c-format +msgid "warning: %s: local symbol `%s' has no section" +msgstr "avertisment: %s: simbolul local `%s' nu are secþiune" + +#: coffcode.h:5083 +#, c-format +msgid "%s: illegal relocation type %d at address 0x%lx" +msgstr "%s: tip ilegal de relocare %d la adresa 0x%lx" + +#: coffgen.c:1666 +#, c-format +msgid "%s: bad string table size %lu" +msgstr "%s: mãrime tabel ºiruri invalidã %lu" + +#: cofflink.c:538 elflink.h:1276 +#, c-format +msgid "Warning: type of symbol `%s' changed from %d to %d in %s" +msgstr "Avertisment: tipul de simbol `%s' schimbat de la %d la %d în %s" + +#: cofflink.c:2328 +#, c-format +msgid "%s: relocs in section `%s', but it has no contents" +msgstr "%s: relocãri în secþiunea `%s', dar fãrã conþinut" + +#: cofflink.c:2671 coffswap.h:890 +#, c-format +msgid "%s: %s: reloc overflow: 0x%lx > 0xffff" +msgstr "%s: %s: depãºire(overflow) de relocãri: 0x%lx > 0xffff" + +#: cofflink.c:2680 coffswap.h:876 +#, c-format +msgid "%s: warning: %s: line number overflow: 0x%lx > 0xffff" +msgstr "%s: avertisment: %s: depãºire(overflow) numãr de linii: 0x%lx > 0xffff" + +#: cpu-arm.c:196 cpu-arm.c:206 +#, c-format +msgid "ERROR: %s is compiled for the EP9312, whereas %s is compiled for XScale" +msgstr "EROARE: %s este compilat pentru EP9312, pe când %s e compilat pentru XScale" + +#: cpu-arm.c:344 +#, c-format +msgid "warning: unable to update contents of %s section in %s" +msgstr "avertisment: imposibil de adus la zi(update) conþinutul secþiunii %s în %s" + +#: dwarf2.c:380 +msgid "Dwarf Error: Can't find .debug_str section." +msgstr "Eroare Pitic(Dwarf): Nu pot gãsi secþiunea debug_str" + +#: dwarf2.c:397 +#, c-format +msgid "Dwarf Error: DW_FORM_strp offset (%lu) greater than or equal to .debug_str size (%lu)." +msgstr "Eroare Pitic(Dwarf): DW_FORM_strp offset (%lu) mai mare sau egalã cu mãrimea .debug_str (%lu)." + +#: dwarf2.c:541 +msgid "Dwarf Error: Can't find .debug_abbrev section." +msgstr "Eroare Pitic(Dwarf): Nu pot gãsi secþiunea debug_abbrev." + +#: dwarf2.c:556 +#, c-format +msgid "Dwarf Error: Abbrev offset (%lu) greater than or equal to .debug_abbrev size (%lu)." +msgstr "Eroare Pitic(Dwarf): Offset abbrev(%lu) mai mare sau egal cu mãrimea .debug_abbrev (%lu)." + +#: dwarf2.c:756 +#, c-format +msgid "Dwarf Error: Invalid or unhandled FORM value: %u." +msgstr "Eroare Pitic(Dwarf): Valoare FORM invalidã sau nemanipulabilã: %u." + +#: dwarf2.c:933 +msgid "Dwarf Error: mangled line number section (bad file number)." +msgstr "Eroare Pitic(Dwarf): secþiune numãr de linii trunchiatã (numãr fiºier eronat)" + +#: dwarf2.c:1032 +msgid "Dwarf Error: Can't find .debug_line section." +msgstr "Eroare Pitic(Dwarf): Nu pot gãsi secþiunea debug_line." + +#: dwarf2.c:1049 +#, c-format +msgid "Dwarf Error: Line offset (%lu) greater than or equal to .debug_line size (%lu)." +msgstr "Eroare Pitic(Dwarf): Offsetul de linie (%lu) mai mare sau egal cu mãrimea .debug_line (%lu)" + +#: dwarf2.c:1255 +msgid "Dwarf Error: mangled line number section." +msgstr "Eroare Pitic(Dwarf): secþiune trunchiatã numãr de linii" + +#: dwarf2.c:1470 dwarf2.c:1620 +#, c-format +msgid "Dwarf Error: Could not find abbrev number %u." +msgstr "Eroare Pitic(Dwarf): Nu am putut gãsi numãrul abbrev: %u." + +#: dwarf2.c:1581 +#, c-format +msgid "Dwarf Error: found dwarf version '%u', this reader only handles version 2 information." +msgstr "Eroare Pitic(Dwarf): S-a gãsit dwarf versiunea `%u', acest cititor manipuleazã doar informaþii ale versiunii 2." + +#: dwarf2.c:1588 +#, c-format +msgid "Dwarf Error: found address size '%u', this reader can not handle sizes greater than '%u'." +msgstr "Eroare Pitic(Dwarf): s-a gãsit adresa mãrimea `%u', acest cititor nu poate manipula mãrimi mai mari decât `%u'" + +#: dwarf2.c:1611 +#, c-format +msgid "Dwarf Error: Bad abbrev number: %u." +msgstr "Eroare Pitic(Dwarf): Numãr invalid de abbrev: %u" + +#: ecoff.c:1339 +#, c-format +msgid "Unknown basic type %d" +msgstr "Tip de bazã necunoscut %d" + +#: ecoff.c:1599 +#, c-format +msgid "" +"\n" +" End+1 symbol: %ld" +msgstr "" +"\n" +" Simbol Sfârºit+1: %ld" + +#: ecoff.c:1606 ecoff.c:1609 +#, c-format +msgid "" +"\n" +" First symbol: %ld" +msgstr "" +"\n" +" Primul simbol: %ld" + +#: ecoff.c:1621 +#, c-format +msgid "" +"\n" +" End+1 symbol: %-7ld Type: %s" +msgstr "" +"\n" +" Simbol Sfârºit+1: %-7ld Tip: %s" + +#: ecoff.c:1628 +#, c-format +msgid "" +"\n" +" Local symbol: %ld" +msgstr "" +"\n" +" Simbol local: %ld" + +#: ecoff.c:1636 +#, c-format +msgid "" +"\n" +" struct; End+1 symbol: %ld" +msgstr "" +"\n" +" struct; Simbol Sfârºit+1: %ld" + +#: ecoff.c:1641 +#, c-format +msgid "" +"\n" +" union; End+1 symbol: %ld" +msgstr "" +"\n" +" uniune; Simbol Sfârºit+1: %ld" + +#: ecoff.c:1646 +#, c-format +msgid "" +"\n" +" enum; End+1 symbol: %ld" +msgstr "" +"\n" +" enum; Simbol Sfârºit+1: %ld" + +#: ecoff.c:1652 +#, c-format +msgid "" +"\n" +" Type: %s" +msgstr "" +"\n" +" Tip: %s" + +#: elf-hppa.h:1458 elf-hppa.h:1491 elf-m10300.c:1628 elf64-sh64.c:1704 +#, c-format +msgid "%s: warning: unresolvable relocation against symbol `%s' from %s section" +msgstr "%s: avertisment: relocare nerezolvabilã pe simbolul `%s; din secþiunea `%s'" + +#: elf-m10200.c:442 elf-m10300.c:1695 elf32-arm.h:2088 elf32-avr.c:812 +#: elf32-cris.c:1390 elf32-d10v.c:570 elf32-fr30.c:634 elf32-frv.c:815 +#: elf32-h8300.c:528 elf32-i860.c:1028 elf32-ip2k.c:1586 elf32-iq2000.c:699 +#: elf32-m32r.c:1283 elf32-m68hc1x.c:1305 elf32-msp430.c:510 +#: elf32-openrisc.c:436 elf32-v850.c:1777 elf32-xstormy16.c:976 +#: elf64-mmix.c:1332 +msgid "internal error: out of range error" +msgstr "eroare internã: eroare depãºire de domeniu(out of range)" + +#: elf-m10200.c:446 elf-m10300.c:1699 elf32-arm.h:2092 elf32-avr.c:816 +#: elf32-cris.c:1394 elf32-d10v.c:574 elf32-fr30.c:638 elf32-frv.c:819 +#: elf32-h8300.c:532 elf32-i860.c:1032 elf32-iq2000.c:703 elf32-m32r.c:1287 +#: elf32-m68hc1x.c:1309 elf32-msp430.c:514 elf32-openrisc.c:440 +#: elf32-v850.c:1781 elf32-xstormy16.c:980 elf64-mmix.c:1336 elfxx-mips.c:6452 +msgid "internal error: unsupported relocation error" +msgstr "eroare internã: eroare de relocare nesuportatã" + +#: elf-m10200.c:450 elf-m10300.c:1703 elf32-arm.h:2096 elf32-d10v.c:578 +#: elf32-h8300.c:536 elf32-m32r.c:1291 elf32-m68hc1x.c:1313 +msgid "internal error: dangerous error" +msgstr "eroare internã: eroare periculoasã" + +#: elf-m10200.c:454 elf-m10300.c:1707 elf32-arm.h:2100 elf32-avr.c:824 +#: elf32-cris.c:1402 elf32-d10v.c:582 elf32-fr30.c:646 elf32-frv.c:827 +#: elf32-h8300.c:540 elf32-i860.c:1040 elf32-ip2k.c:1601 elf32-iq2000.c:711 +#: elf32-m32r.c:1295 elf32-m68hc1x.c:1317 elf32-msp430.c:522 +#: elf32-openrisc.c:448 elf32-v850.c:1801 elf32-xstormy16.c:988 +#: elf64-mmix.c:1344 +msgid "internal error: unknown error" +msgstr "eroare internã: eroare necunoscutã" + +#: elf.c:372 +#, c-format +msgid "%s: invalid string offset %u >= %lu for section `%s'" +msgstr "%s: offset de ºir invalid %u >= %lu pentru secþiunea `%s'" + +#: elf.c:624 +#, c-format +msgid "%s: invalid SHT_GROUP entry" +msgstr "%s: intrare SHT_GROUP invalidã" + +#: elf.c:695 +#, c-format +msgid "%s: no group info for section %s" +msgstr "%s nu existã informaþii de grup pentru secþiunea %s" + +#: elf.c:1055 +msgid "" +"\n" +"Program Header:\n" +msgstr "" +"\n" +"Header Program:\n" + +#: elf.c:1106 +msgid "" +"\n" +"Dynamic Section:\n" +msgstr "" +"\n" +"Secþiune Dinamicã:\n" + +#: elf.c:1235 +msgid "" +"\n" +"Version definitions:\n" +msgstr "" +"\n" +"Definiþii de versiune:\n" + +#: elf.c:1258 +msgid "" +"\n" +"Version References:\n" +msgstr "" +"\n" +"Referinþe Versiune:\n" + +#: elf.c:1263 +#, c-format +msgid " required from %s:\n" +msgstr " cerute de %s:\n" + +#: elf.c:1944 +#, c-format +msgid "%s: invalid link %lu for reloc section %s (index %u)" +msgstr "%s: link invalid %lu pentru secþiunea de relocare %s (index %u)" + +#: elf.c:3686 +#, c-format +msgid "%s: Not enough room for program headers (allocated %u, need %u)" +msgstr "%s: Memorie insuficientã pentru headerele programului (alocatã %u, necesarã %u)" + +#: elf.c:3791 +#, c-format +msgid "%s: Not enough room for program headers, try linking with -N" +msgstr "%s: Memorie insuficientã pentru headerele programului, încercaþi linkuirea cu -N" + +#: elf.c:3922 +#, c-format +msgid "Error: First section in segment (%s) starts at 0x%x whereas the segment starts at 0x%x" +msgstr "Eroare: prima secþiune în segment (%s) începe la 0x%x pe când segmentul începe la 0x%x" + +#: elf.c:4242 +#, c-format +msgid "%s: warning: allocated section `%s' not in segment" +msgstr "%s: avertisment: secþiunea alocatã `%s' nu este în segment" + +#: elf.c:4566 +#, c-format +msgid "%s: symbol `%s' required but not present" +msgstr "%s: simbolul `%s' necesar, dar nu este prezent" + +#: elf.c:4854 +#, c-format +msgid "%s: warning: Empty loadable segment detected, is this intentional ?\n" +msgstr "%s: avertisment: S-a detectat segment încãrcabil vid, este intenþionat ?\n" + +#: elf.c:5485 +#, c-format +msgid "Unable to find equivalent output section for symbol '%s' from section '%s'" +msgstr "Nnu am putut gãsi secþiunea de output echivalentã pentru simbolul '%s' din secþiunea '%s'" + +#: elf.c:6298 +#, c-format +msgid "%s: unsupported relocation type %s" +msgstr "%s: tip de relocare nesuportat: %s" + +#: elf32-arm.h:1228 +#, c-format +msgid "%s: Warning: Arm BLX instruction targets Arm function '%s'." +msgstr "%s: Avertisment: BLX Arm are ca þintã funcþia Arm `%s'." + +#: elf32-arm.h:1424 +#, c-format +msgid "%s: Warning: Thumb BLX instruction targets thumb function '%s'." +msgstr "%s: Avertisment: BLX Thumb are ca þintã funcþia thumb `%s'." + +#: elf32-arm.h:1918 elf32-sh.c:4706 elf64-sh64.c:1613 +#, c-format +msgid "%s(%s+0x%lx): %s relocation against SEC_MERGE section" +msgstr "%s(%s+0x%lx): %s relocare pe secþiunea SEC_MERGE" + +#: elf32-arm.h:2012 +#, c-format +msgid "%s: warning: unresolvable relocation %d against symbol `%s' from %s section" +msgstr "%s: avertisment: relocare nerezolvabilã %d pe simbolul `%s' din secþiunea %s" + +#: elf32-arm.h:2202 +#, c-format +msgid "Warning: Clearing the interworking flag of %s because non-interworking code in %s has been linked with it" +msgstr "Avertisment: Se ºterge marcajul(flag) de interlucru(interworking) al %s deoarece împreunã cu el a fost linkuit cod non-interlucru în %s" + +#: elf32-arm.h:2302 +#, c-format +msgid "ERROR: %s is compiled for EABI version %d, whereas %s is compiled for version %d" +msgstr "EROARE: %s este compilat pentru EABI versiunea %d, pe când %s este compilat pentru versiunea %d" + +#: elf32-arm.h:2316 +#, c-format +msgid "ERROR: %s is compiled for APCS-%d, whereas target %s uses APCS-%d" +msgstr "EROARE: %s este compilat pentru APCS-%d, pe când þinta %s foloseºte APCS-%d" + +#: elf32-arm.h:2344 +#, c-format +msgid "ERROR: %s uses VFP instructions, whereas %s does not" +msgstr "EROARE: %s foloseºte instrucþiuni VFP, pe când %s nu le foloseºte" + +#: elf32-arm.h:2349 +#, c-format +msgid "ERROR: %s uses FPA instructions, whereas %s does not" +msgstr "EROARE: %s foloseºte instrucþiuni FPA, pe când %s nu le foloseºte" + +#: elf32-arm.h:2360 elf32-arm.h:2365 +#, c-format +msgid "ERROR: %s uses Maverick instructions, whereas %s does not" +msgstr "EROARE: %s foloseºte instrucþiuni Maverick, pe când %s nu le foloseºte" + +#: elf32-arm.h:2385 +#, c-format +msgid "ERROR: %s uses software FP, whereas %s uses hardware FP" +msgstr "EROARE: %s foloseºte FP software, pe când %s foloseºte FP hardware" + +#: elf32-arm.h:2390 +#, c-format +msgid "ERROR: %s uses hardware FP, whereas %s uses software FP" +msgstr "EROARE: %s foloseºte FP hardware, pe când %s foloseºte FP software" + +#. Ignore init flag - it may not be set, despite the flags field +#. containing valid data. +#: elf32-arm.h:2443 elf32-cris.c:2975 elf32-m68hc1x.c:1459 elf32-m68k.c:397 +#: elf32-vax.c:546 elfxx-mips.c:9238 +#, c-format +msgid "private flags = %lx:" +msgstr "marcaje(flags) private = %lx:" + +#: elf32-arm.h:2452 +msgid " [interworking enabled]" +msgstr " [interlucru(interworking) activat]" + +#: elf32-arm.h:2460 +msgid " [VFP float format]" +msgstr " [format float VFP]" + +#: elf32-arm.h:2462 +msgid " [Maverick float format]" +msgstr " [format float Maverick]" + +#: elf32-arm.h:2464 +msgid " [FPA float format]" +msgstr " [format float FPA]" + +#: elf32-arm.h:2473 +msgid " [new ABI]" +msgstr " [ABI nou]" + +#: elf32-arm.h:2476 +msgid " [old ABI]" +msgstr " [ABI vechi]" + +#: elf32-arm.h:2479 +msgid " [software FP]" +msgstr " [FP software]" + +#: elf32-arm.h:2488 +msgid " [Version1 EABI]" +msgstr " [EABI Versiunea1]" + +#: elf32-arm.h:2491 elf32-arm.h:2502 +msgid " [sorted symbol table]" +msgstr " [tabelã sortatã de simboluri]" + +#: elf32-arm.h:2493 elf32-arm.h:2504 +msgid " [unsorted symbol table]" +msgstr " [tabelã de simboluri nesortatã]" + +#: elf32-arm.h:2499 +msgid " [Version2 EABI]" +msgstr " [EABI Versiunea2]" + +#: elf32-arm.h:2507 +msgid " [dynamic symbols use segment index]" +msgstr " [simbolurile dinamice folosesc index de segment]" + +#: elf32-arm.h:2510 +msgid " [mapping symbols precede others]" +msgstr " [simbolurile de mapare le precedeazã pe celelalte]" + +#: elf32-arm.h:2517 +msgid " " +msgstr " " + +#: elf32-arm.h:2524 +msgid " [relocatable executable]" +msgstr " [executabil relocabil]" + +#: elf32-arm.h:2527 +msgid " [has entry point]" +msgstr " [are punct de intrare]" + +#: elf32-arm.h:2532 +msgid "" +msgstr "" + +#: elf32-avr.c:820 elf32-cris.c:1398 elf32-fr30.c:642 elf32-frv.c:823 +#: elf32-i860.c:1036 elf32-ip2k.c:1597 elf32-iq2000.c:707 elf32-msp430.c:518 +#: elf32-openrisc.c:444 elf32-v850.c:1785 elf32-xstormy16.c:984 +#: elf64-mmix.c:1340 +msgid "internal error: dangerous relocation" +msgstr "eroare internã: relocare periculoasã" + +#: elf32-cris.c:931 +#, c-format +msgid "%s: unresolvable relocation %s against symbol `%s' from %s section" +msgstr "%s: relocare nerezolvabilã %s pe simbolul `%s' din secþiunea `%s'" + +#: elf32-cris.c:993 +#, c-format +msgid "%s: No PLT nor GOT for relocation %s against symbol `%s' from %s section" +msgstr "%s:Nu existã nici PLT nici GOR pentru relocarea %s pe simbolul `%s' din secþiunea %s" + +#: elf32-cris.c:996 elf32-cris.c:1122 +msgid "[whose name is lost]" +msgstr "[al cãrui nume s-a pierdut]" + +#: elf32-cris.c:1111 +#, c-format +msgid "%s: relocation %s with non-zero addend %d against local symbol from %s section" +msgstr "%s: relocarea %s cu adãugarea diferitã de zero %d pe simbolul local din secþiunea %s" + +#: elf32-cris.c:1118 +#, c-format +msgid "%s: relocation %s with non-zero addend %d against symbol `%s' from %s section" +msgstr "%s: relocarea %s cu adãugare non-zero %d pe simbolul `%s' din secþiunea %s" + +#: elf32-cris.c:1143 +#, c-format +msgid "%s: relocation %s is not allowed for global symbol: `%s' from %s section" +msgstr "%s: relocarea %s nu este permisã pentru simbolul global `%s' din secþiunea %s" + +#: elf32-cris.c:1158 +#, c-format +msgid "%s: relocation %s in section %s with no GOT created" +msgstr "%s: relocarea %s din secþiunea %s fãrã GOT creat" + +#: elf32-cris.c:1277 +#, c-format +msgid "%s: Internal inconsistency; no relocation section %s" +msgstr "%s: Inconsistenþã internã, nu existã secþiunea de relocare %s" + +#: elf32-cris.c:2500 +#, c-format +msgid "" +"%s, section %s:\n" +" relocation %s should not be used in a shared object; recompile with -fPIC" +msgstr "" +"%s, secþiunea %s:\n" +" relocarea %s n-ar trebui folositã într-un shared object; recompilaþi cu -fPIC" + +#: elf32-cris.c:2978 +msgid " [symbols have a _ prefix]" +msgstr " [simbolurile au un _prefix]" + +#: elf32-cris.c:3017 +#, c-format +msgid "%s: uses _-prefixed symbols, but writing file with non-prefixed symbols" +msgstr "%s: se folosesc simbolurile _-prefixate, dar se scrie fiºierul cu simboluri neprefixate" + +#: elf32-cris.c:3018 +#, c-format +msgid "%s: uses non-prefixed symbols, but writing file with _-prefixed symbols" +msgstr "%s: se folosesc simboluri neprefixate, dar se scrie fiºierul cu simboluri _-prefixate" + +#: elf32-frv.c:1223 +#, c-format +msgid "%s: compiled with %s and linked with modules that use non-pic relocations" +msgstr "%s: compilat cu %s ºi linkuit cu module care folosesc relocaþii non-pic" + +#: elf32-frv.c:1273 elf32-iq2000.c:895 +#, c-format +msgid "%s: compiled with %s and linked with modules compiled with %s" +msgstr "%s: compilat cu %s ºi linkuit cu module compilate cu %s" + +#: elf32-frv.c:1285 +#, c-format +msgid "%s: uses different unknown e_flags (0x%lx) fields than previous modules (0x%lx)" +msgstr "%s: foloseºte câmpuri marcaje e_flags (0x%lx) diferite de modulele anterioare (0x%lx)" + +#: elf32-frv.c:1321 elf32-iq2000.c:933 +#, c-format +msgid "private flags = 0x%lx:" +msgstr "marcaje(flags) private = 0x%lx" + +#: elf32-gen.c:83 elf64-gen.c:82 +#, c-format +msgid "%s: Relocations in generic ELF (EM: %d)" +msgstr "%s: Relocãri în ELF generic (EM: %d)" + +#: elf32-hppa.c:672 elf32-m68hc1x.c:176 elf64-ppc.c:3118 +#, c-format +msgid "%s: cannot create stub entry %s" +msgstr "%s: nu se poate crea intrarea trunchiatã %s" + +#: elf32-hppa.c:957 elf32-hppa.c:3538 +#, c-format +msgid "%s(%s+0x%lx): cannot reach %s, recompile with -ffunction-sections" +msgstr "%s(%s+0x%lx): nu se poate gãsi %s, recompilaþi cu -ffunction-sections" + +#: elf32-hppa.c:1340 elf64-x86-64.c:672 elf64-x86-64.c:797 +#, c-format +msgid "%s: relocation %s can not be used when making a shared object; recompile with -fPIC" +msgstr "%s: relocarea %s nu poate fi utilizatã când se face un shared object, recompilaþicu -fPIC" + +#: elf32-hppa.c:1360 +#, c-format +msgid "%s: relocation %s should not be used when making a shared object; recompile with -fPIC" +msgstr "%s: relocarea %s nu ar trebui utilizatã când se face un shared object, recompilaþicu -fPIC" + +#: elf32-hppa.c:1553 +#, c-format +msgid "Could not find relocation section for %s" +msgstr "Nu se poate gãsi secþiunea de relocare pentru %s" + +#: elf32-hppa.c:2828 +#, c-format +msgid "%s: duplicate export stub %s" +msgstr "%s: exportare de ciot(stub) duplicatã %s" + +#: elf32-hppa.c:3416 +#, c-format +msgid "%s(%s+0x%lx): fixing %s" +msgstr "%s(%s+0x%lx): se fixeazã %s" + +#: elf32-hppa.c:4039 +#, c-format +msgid "%s(%s+0x%lx): cannot handle %s for %s" +msgstr "%s(%s+0x%lx): nu pot manipula %s pentru %s" + +#: elf32-hppa.c:4357 +msgid ".got section not immediately after .plt section" +msgstr "secþiunea .got nu urmeazã imediat dupã secþiunea .plt" + +#: elf32-i386.c:326 +#, c-format +msgid "%s: invalid relocation type %d" +msgstr "%s: tip de relocare invalid %d" + +#: elf32-i386.c:841 elf32-s390.c:990 elf32-sparc.c:887 elf32-xtensa.c:637 +#: elf64-s390.c:943 elf64-x86-64.c:650 +#, c-format +msgid "%s: bad symbol index: %d" +msgstr "%s:index de simboluri invalid: %d" + +#: elf32-i386.c:949 elf32-s390.c:1168 elf32-sh.c:6426 elf32-sparc.c:1011 +#: elf64-s390.c:1129 +#, c-format +msgid "%s: `%s' accessed both as normal and thread local symbol" +msgstr "%s: `%s' accesate ºi ca simboluri locale normale ºi ca simboluri locale pe fire (thread)" + +#: elf32-i386.c:1064 elf32-s390.c:1279 elf64-ppc.c:3929 elf64-s390.c:1243 +#: elf64-x86-64.c:886 +#, c-format +msgid "%s: bad relocation section name `%s'" +msgstr "%s: nume secþiune relocare invalid `%s'" + +#: elf32-i386.c:2908 elf32-m68k.c:1757 elf32-s390.c:3022 elf32-sparc.c:2879 +#: elf32-xtensa.c:2193 elf64-s390.c:3018 elf64-sparc.c:2664 +#: elf64-x86-64.c:2452 +#, c-format +msgid "%s(%s+0x%lx): unresolvable relocation against symbol `%s'" +msgstr "%s(%s+0x%lx): relocare nerezolvabilã pe simbolul `%s'" + +#: elf32-i386.c:2947 elf32-m68k.c:1796 elf32-s390.c:3072 elf64-s390.c:3068 +#: elf64-x86-64.c:2490 +#, c-format +msgid "%s(%s+0x%lx): reloc against `%s': error %d" +msgstr "%s(%s+0x%lx): relocare pe `%s': eroare %d" + +#: elf32-ip2k.c:565 elf32-ip2k.c:571 elf32-ip2k.c:734 elf32-ip2k.c:740 +msgid "ip2k relaxer: switch table without complete matching relocation information." +msgstr "ip2k relaxer: schimbare de tabel fãrã potrivirea completã a informaþiei de relocare." + +#: elf32-ip2k.c:588 elf32-ip2k.c:767 +msgid "ip2k relaxer: switch table header corrupt." +msgstr "ip2k relaxer: headerul tablelului de schimbare este corupt." + +#: elf32-ip2k.c:1395 +#, c-format +msgid "ip2k linker: missing page instruction at 0x%08lx (dest = 0x%08lx)." +msgstr "ip2k linker: lipseºte instrucþiunea de paginã la 0x%08lx (dest = 0x%08lx)." + +#: elf32-ip2k.c:1409 +#, c-format +msgid "ip2k linker: redundant page instruction at 0x%08lx (dest = 0x%08lx)." +msgstr "ip2k linker: instrucþiune redundantã de paginã la 0x%08lx (dest = 0x%08lx)." + +#. Only if it's not an unresolved symbol. +#: elf32-ip2k.c:1593 +msgid "unsupported relocation between data/insn address spaces" +msgstr "relocare nesuportatã între datã/spaþiu adresã insn" + +#: elf32-iq2000.c:907 elf32-m68hc1x.c:1431 elf32-ppc.c:2175 elf64-sparc.c:3072 +#: elfxx-mips.c:9195 +#, c-format +msgid "%s: uses different e_flags (0x%lx) fields than previous modules (0x%lx)" +msgstr "%s: foloseºte câmpuri de marcaje e_flags (0x%lx) diferite de modulele anterioare (0x%lx)" + +#: elf32-m32r.c:930 +msgid "SDA relocation when _SDA_BASE_ not defined" +msgstr "Relocare SDA când _SDA_BASE_ nu este definit" + +#: elf32-m32r.c:1018 elf64-alpha.c:4279 elf64-alpha.c:4407 elf32-ia64.c:3958 +#: elf64-ia64.c:3958 +#, c-format +msgid "%s: unknown relocation type %d" +msgstr "%s: tip necunoscut de relocare %d" + +#: elf32-m32r.c:1226 +#, c-format +msgid "%s: The target (%s) of an %s relocation is in the wrong section (%s)" +msgstr "%s: Þinta (%s) unei relocãri %s este în secþiunea nepotrivitã (%s)" + +#: elf32-m32r.c:1952 +#, c-format +msgid "%s: Instruction set mismatch with previous modules" +msgstr "%s: Setul de instrucþiuni nu se potriveºte cu modulele anterioare" + +#: elf32-m32r.c:1975 +#, c-format +msgid "private flags = %lx" +msgstr "marcaje (flags) private = %lx" + +#: elf32-m32r.c:1980 +msgid ": m32r instructions" +msgstr ": instrucþiuni m32r" + +#: elf32-m32r.c:1981 +msgid ": m32rx instructions" +msgstr ": instrucþiuni m32rx" + +#: elf32-m68hc1x.c:1217 +#, c-format +msgid "Reference to the far symbol `%s' using a wrong relocation may result in incorrect execution" +msgstr "Referinþa la simbolul depãrtat `%s' folosind o relocare invalidã poate duce la execuþie incorectã" + +#: elf32-m68hc1x.c:1240 +#, c-format +msgid "banked address [%lx:%04lx] (%lx) is not in the same bank as current banked address [%lx:%04lx] (%lx)" +msgstr "adresa banked [%lx:%04lx] (%lx) nu este în acelaºi bank precum adresa banked curentã [%lx:%04lx] (%lx)" + +#: elf32-m68hc1x.c:1259 +#, c-format +msgid "reference to a banked address [%lx:%04lx] in the normal address space at %04lx" +msgstr "referinþã la adresa banked [%lx:%04lx] în spaþiul normal de adresã la %04lx" + +#: elf32-m68hc1x.c:1396 +#, c-format +msgid "%s: linking files compiled for 16-bit integers (-mshort) and others for 32-bit integers" +msgstr "%s: linkuire a fiºierelor compilate pentru întregi(integers) pe 16-biþi (-mshort) ºi a celorlalte pentru întregi(integers) pe 32-biþi" + +#: elf32-m68hc1x.c:1404 +#, c-format +msgid "%s: linking files compiled for 32-bit double (-fshort-double) and others for 64-bit double" +msgstr "%s: linkuire a fiºierelor compilate pentru double pe 32-biþi (-fshort-double) ºi a celorlalte pentru double pe 64-biþi" + +#: elf32-m68hc1x.c:1414 +#, c-format +msgid "%s: linking files compiled for HCS12 with others compiled for HC12" +msgstr "%s:linkuire a fiºierelor compilate pentru HCS12 cu celelalte compilate pentru HC12" + +#: elf32-m68hc1x.c:1462 +msgid "[abi=32-bit int, " +msgstr "[abi=32-bit int, " + +#: elf32-m68hc1x.c:1464 +msgid "[abi=16-bit int, " +msgstr "[abi=16-bit int, " + +#: elf32-m68hc1x.c:1467 +msgid "64-bit double, " +msgstr "double pe 64-biþi, " + +#: elf32-m68hc1x.c:1469 +msgid "32-bit double, " +msgstr "double pe 32-biþi, " + +#: elf32-m68hc1x.c:1472 +msgid "cpu=HC11]" +msgstr "cpu=HC11]" + +#: elf32-m68hc1x.c:1474 +msgid "cpu=HCS12]" +msgstr "cpu=HCS12]" + +#: elf32-m68hc1x.c:1476 +msgid "cpu=HC12]" +msgstr "cpu=HC12]" + +#: elf32-m68hc1x.c:1479 +msgid " [memory=bank-model]" +msgstr " [memorie=mod-bank]" + +#: elf32-m68hc1x.c:1481 +msgid " [memory=flat]" +msgstr " [memorie=întinsã(flat)]" + +#: elf32-m68k.c:400 +msgid " [cpu32]" +msgstr " [cpu32]" + +#: elf32-m68k.c:403 +msgid " [m68000]" +msgstr " [m68000]" + +#: elf32-mcore.c:353 elf32-mcore.c:456 +#, c-format +msgid "%s: Relocation %s (%d) is not currently supported.\n" +msgstr "%s: Relocarea %s (%d) nu este încã suportatã.\n" + +#: elf32-mcore.c:441 +#, c-format +msgid "%s: Unknown relocation type %d\n" +msgstr "%s: Tip necunoscut de relocare %d\n" + +#: elf32-mips.c:1170 elf64-mips.c:1717 elfn32-mips.c:1664 +msgid "32bits gp relative relocation occurs for an external symbol" +msgstr "relocarea relativã gp 32bits are loc pe un simbol extern" + +#: elf32-mips.c:1314 elf64-mips.c:1830 elfn32-mips.c:1783 +#, c-format +msgid "Linking mips16 objects into %s format is not supported" +msgstr "Linkuirea obiectelor mips16 în formatul %s nu este suportatã" + +#: elf32-ppc.c:2056 +#, c-format +msgid "generic linker can't handle %s" +msgstr "linkerul generic nu poate manipula(handle) %s" + +#: elf32-ppc.c:2138 +#, c-format +msgid "%s: compiled with -mrelocatable and linked with modules compiled normally" +msgstr "%s: compilat cu -mrelocatable ºi linkuit cu module compilate normal" + +#: elf32-ppc.c:2147 +#, c-format +msgid "%s: compiled normally and linked with modules compiled with -mrelocatable" +msgstr "%s: compilat normal ºi linkuite cu module compilate cu -mrelocatable" + +#: elf32-ppc.c:3413 +#, c-format +msgid "%s: relocation %s cannot be used when making a shared object" +msgstr "%s: relocarea %s nu poate fi folositã când se creazã un shared object" + +#. It does not make sense to have a procedure linkage +#. table entry for a local symbol. +#: elf32-ppc.c:3619 +#, c-format +msgid "%s(%s+0x%lx): %s reloc against local symbol" +msgstr "relocare %s(%s+0x%lx): %s pe simbol local" + +#: elf32-ppc.c:4862 elf64-ppc.c:7789 +#, c-format +msgid "%s: unknown relocation type %d for symbol %s" +msgstr "%s: tip de relocare %d necunoscut pentru simbolul %s" + +#: elf32-ppc.c:5113 +#, c-format +msgid "%s(%s+0x%lx): non-zero addend on %s reloc against `%s'" +msgstr "%s(%s+0x%lx): adãugare non-zero în relocarea %s pentru `%s'" + +#: elf32-ppc.c:5399 elf32-ppc.c:5425 elf32-ppc.c:5484 +#, c-format +msgid "%s: the target (%s) of a %s relocation is in the wrong output section (%s)" +msgstr "%s: þinta (%s) unei relocãri %s este într-o secþiune invalidã de output (%s)" + +#: elf32-ppc.c:5539 +#, c-format +msgid "%s: relocation %s is not yet supported for symbol %s." +msgstr "%s: relocarea %s nu este încã suportatã pentru simbolul %s." + +#: elf32-ppc.c:5594 elf64-ppc.c:8461 +#, c-format +msgid "%s(%s+0x%lx): unresolvable %s relocation against symbol `%s'" +msgstr "%s(%s+0x%lx): relocare nerezolvabilã %s pe simbolul `%s'" + +#: elf32-ppc.c:5644 elf64-ppc.c:8507 +#, c-format +msgid "%s(%s+0x%lx): %s reloc against `%s': error %d" +msgstr "%s(%s+0x%lx):relocarea %s pe `%s': eroare %d" + +#: elf32-ppc.c:5888 +#, c-format +msgid "corrupt or empty %s section in %s" +msgstr "secþiune %s coruptã sau vidã în %s" + +#: elf32-ppc.c:5895 +#, c-format +msgid "unable to read in %s section from %s" +msgstr "nu se poate citi în secþiunea %s din %s" + +#: elf32-ppc.c:5901 +#, c-format +msgid "corrupt %s section in %s" +msgstr "secþiune coruptã %s în %s" + +#: elf32-ppc.c:5944 +#, c-format +msgid "warning: unable to set size of %s section in %s" +msgstr "avertisment: nu se poate seta mãrimea secþiunii %s în %s" + +#: elf32-ppc.c:5994 +msgid "failed to allocate space for new APUinfo section." +msgstr "nu s-a putut aloca spaþiu pentru secþiunea nouã APUinfo." + +#: elf32-ppc.c:6013 +msgid "failed to compute new APUinfo section." +msgstr "nu s-a putut calcula(compute) secþiunea nouã APUinfo." + +#: elf32-ppc.c:6016 +msgid "failed to install new APUinfo section." +msgstr "nu s-a putut instala secþiunea APUinfo nouã." + +#: elf32-s390.c:2256 elf64-s390.c:2226 +#, c-format +msgid "%s(%s+0x%lx): invalid instruction for TLS relocation %s" +msgstr "%s(%s+0x%lx): instrucþiune invalidã pentur relocarea TLS %s" + +#: elf32-sh.c:2103 +#, c-format +msgid "%s: 0x%lx: warning: bad R_SH_USES offset" +msgstr "%s: 0x%lx: avertisment: offset R_SH_USES invalid" + +#: elf32-sh.c:2115 +#, c-format +msgid "%s: 0x%lx: warning: R_SH_USES points to unrecognized insn 0x%x" +msgstr "%s: 0x%lx: avertisment: R_SH_USES trimite cãtre insn necunoscut 0x%x" + +#: elf32-sh.c:2132 +#, c-format +msgid "%s: 0x%lx: warning: bad R_SH_USES load offset" +msgstr "%s: 0x%lx: avertisment:offset de încãrcare R_SH_USES invalid" + +#: elf32-sh.c:2147 +#, c-format +msgid "%s: 0x%lx: warning: could not find expected reloc" +msgstr "%s: 0x%lx: avertismetn: nu s-a putut gãsi relocarea aºteptatã" + +#: elf32-sh.c:2175 +#, c-format +msgid "%s: 0x%lx: warning: symbol in unexpected section" +msgstr "%s: 0x%lx: avertisment: simbol în secþiune neaºteptatã" + +#: elf32-sh.c:2300 +#, c-format +msgid "%s: 0x%lx: warning: could not find expected COUNT reloc" +msgstr "%s: 0x%lx: avertisment: nu s-a putut gãsi relocarea COUNT aºteptatã" + +#: elf32-sh.c:2309 +#, c-format +msgid "%s: 0x%lx: warning: bad count" +msgstr "%s: 0x%lx: avertisment: numãrãtoare(count) invalidã" + +#: elf32-sh.c:2712 elf32-sh.c:3088 +#, c-format +msgid "%s: 0x%lx: fatal: reloc overflow while relaxing" +msgstr "%s: 0x%lx: fatal: relocare depãºitã(overflow) în timpul relaxãrii" + +#: elf32-sh.c:4654 elf64-sh64.c:1585 +msgid "Unexpected STO_SH5_ISA32 on local symbol is not handled" +msgstr "STO_SH5_ISA32 neaºteptat pe simbol local ce nu poate fi manipulat" + +#: elf32-sh.c:4809 +#, c-format +msgid "%s: unresolvable relocation against symbol `%s' from %s section" +msgstr "%s: relocare nerezolvabilã pe simbolul '%s' din secþiunea `%s'" + +#: elf32-sh.c:4881 +#, c-format +msgid "%s: 0x%lx: fatal: unaligned branch target for relax-support relocation" +msgstr "%s: 0x%lx: fatal: ramurã þintã nealiniatã pentru relocare cu suport de relaxare" + +#: elf32-sh.c:6627 elf64-alpha.c:4848 +#, c-format +msgid "%s: TLS local exec code cannot be linked into shared objects" +msgstr "%s: codul local executabil TLS nu poate fi linkuit în shared objects" + +#: elf32-sh64.c:221 elf64-sh64.c:2407 +#, c-format +msgid "%s: compiled as 32-bit object and %s is 64-bit" +msgstr "%s: compilat ca obiect pe 32-biþi ºi %s este pe 64-biþi" + +#: elf32-sh64.c:224 elf64-sh64.c:2410 +#, c-format +msgid "%s: compiled as 64-bit object and %s is 32-bit" +msgstr "%s: compilat ca obiect pe 64-biþi ºi %s este pe 32-biþi" + +#: elf32-sh64.c:226 elf64-sh64.c:2412 +#, c-format +msgid "%s: object size does not match that of target %s" +msgstr "%s: mãrimea obiectului nu se potriveºte cu cea a þintei %s" + +#: elf32-sh64.c:461 elf64-sh64.c:2990 +#, c-format +msgid "%s: encountered datalabel symbol in input" +msgstr "%s: s-a întâlnit un simbol etichetãdate(datalabel) în intrare(input)" + +#: elf32-sh64.c:544 +msgid "PTB mismatch: a SHmedia address (bit 0 == 1)" +msgstr "nepotrivire PTB: o adresã SHmedia (bit 0 == 1)" + +#: elf32-sh64.c:547 +msgid "PTA mismatch: a SHcompact address (bit 0 == 0)" +msgstr "nepotrivire PTA: o adresã SHcompact (bit 0 == 0)" + +#: elf32-sh64.c:565 +#, c-format +msgid "%s: GAS error: unexpected PTB insn with R_SH_PT_16" +msgstr "%s: eroare GASr: PTB insn neaºteptat cu R_SH_PT_16" + +#: elf32-sh64.c:614 elf64-sh64.c:1748 +#, c-format +msgid "%s: error: unaligned relocation type %d at %08x reloc %08x\n" +msgstr "%s: eroare: tip de reloare nealiniat %d la %08x relocarea %08x\n" + +#: elf32-sh64.c:698 +#, c-format +msgid "%s: could not write out added .cranges entries" +msgstr "%s: nu am putut scrie intrãrile .cranges adãugate" + +#: elf32-sh64.c:760 +#, c-format +msgid "%s: could not write out sorted .cranges entries" +msgstr "%s: nu am putut scrie intrãrile .cranges sortate" + +#: elf32-sparc.c:2521 elf64-sparc.c:2314 +#, c-format +msgid "%s: probably compiled without -fPIC?" +msgstr "%s: probabil compilat fãrã -fPIC?" + +#: elf32-sparc.c:3348 +#, c-format +msgid "%s: compiled for a 64 bit system and target is 32 bit" +msgstr "%s: compilat pentru un sistem 64 biþi ºi þinta fiind pe 32 biþi" + +#: elf32-sparc.c:3362 +#, c-format +msgid "%s: linking little endian files with big endian files" +msgstr "%s: linkuire fiºiere little endian files cu fiºiere big endian" + +#: elf32-v850.c:753 +#, c-format +msgid "Variable `%s' cannot occupy in multiple small data regions" +msgstr "Variabila `%s' nu poate ocupa regiuni multiple de date mici" + +#: elf32-v850.c:756 +#, c-format +msgid "Variable `%s' can only be in one of the small, zero, and tiny data regions" +msgstr "Variabila `%s' nu poate sã fie în una din regiunile mici, zero sau micuþe" + +#: elf32-v850.c:759 +#, c-format +msgid "Variable `%s' cannot be in both small and zero data regions simultaneously" +msgstr "Variabila `%s' nu poate fi simultan ºi în regiuni de date mici ºi de date zero" + +#: elf32-v850.c:762 +#, c-format +msgid "Variable `%s' cannot be in both small and tiny data regions simultaneously" +msgstr "Variabila `%s' nu poate fi simultan ºi în regiuni de date mici ºi de date micuþe" + +#: elf32-v850.c:765 +#, c-format +msgid "Variable `%s' cannot be in both zero and tiny data regions simultaneously" +msgstr "Variabila `%s' nu poate fi simultan ºi în regiuni de date zero ºi de date micuþe" + +#: elf32-v850.c:1144 +msgid "FAILED to find previous HI16 reloc\n" +msgstr "EªUARE în gãsirea relocãrii anterioare HI16\n" + +#: elf32-v850.c:1789 +msgid "could not locate special linker symbol __gp" +msgstr "nu am putut localiza simbolul special de linker __gp" + +#: elf32-v850.c:1793 +msgid "could not locate special linker symbol __ep" +msgstr "nu am putut localiza simbolul special de linker __ep" + +#: elf32-v850.c:1797 +msgid "could not locate special linker symbol __ctbp" +msgstr "nu am putut localiza simbolul special de linker __ctbp" + +#: elf32-v850.c:1963 +#, c-format +msgid "%s: Architecture mismatch with previous modules" +msgstr "%s: Arhitectura nu se potriveºte cu modulele anterioare" + +#: elf32-v850.c:1983 +#, c-format +msgid "private flags = %lx: " +msgstr "marcaje(flags) private=- %lx: " + +#: elf32-v850.c:1988 +msgid "v850 architecture" +msgstr "arhitecturã v850" + +#: elf32-v850.c:1989 +msgid "v850e architecture" +msgstr "arhitecturã v850e" + +#: elf32-vax.c:549 +msgid " [nonpic]" +msgstr " [nonpic]" + +#: elf32-vax.c:552 +msgid " [d-float]" +msgstr " [d-float]" + +#: elf32-vax.c:555 +msgid " [g-float]" +msgstr " [g-float]" + +#: elf32-vax.c:663 +#, c-format +msgid "%s: warning: GOT addend of %ld to `%s' does not match previous GOT addend of %ld" +msgstr "%s: avertisment: adãugarea GOT a %ld în `%s' nu se potriveºte adãugãrii GOT anterioare a %ld" + +#: elf32-vax.c:1667 +#, c-format +msgid "%s: warning: PLT addend of %d to `%s' from %s section ignored" +msgstr "%s: avertisment: adãugarea PLT a %d în `%s' din secþiunea %s ignoratã" + +#: elf32-vax.c:1802 +#, c-format +msgid "%s: warning: %s relocation against symbol `%s' from %s section" +msgstr "%s: avertisment: relocare %s pentru simbolul `%s' din secþiunea %s" + +#: elf32-vax.c:1808 +#, c-format +msgid "%s: warning: %s relocation to 0x%x from %s section" +msgstr "%s: avertisment: relocare %s spre 0x%x din secþiunea %s" + +#: elf32-xstormy16.c:462 elf32-ia64.c:2450 elf64-ia64.c:2450 +msgid "non-zero addend in @fptr reloc" +msgstr "adãugare non-zero în relocare @fptr" + +#: elf64-alpha.c:1108 +msgid "GPDISP relocation did not find ldah and lda instructions" +msgstr "relocarea GPDISP nu a gãsit instrucþiuni ldah ºi lda" + +#: elf64-alpha.c:3731 +#, c-format +msgid "%s: .got subsegment exceeds 64K (size %d)" +msgstr "%s: .subsegmentul got depãseºte 64K (size %d)" + +#: elf64-alpha.c:4602 elf64-alpha.c:4614 +#, c-format +msgid "%s: gp-relative relocation against dynamic symbol %s" +msgstr "%s: relocare relativã-gp pentru simbolul %s" + +#: elf64-alpha.c:4640 elf64-alpha.c:4773 +#, c-format +msgid "%s: pc-relative relocation against dynamic symbol %s" +msgstr "%s: relocare relativã pc pentru simbolul dinamic %s" + +#: elf64-alpha.c:4668 +#, c-format +msgid "%s: change in gp: BRSGP %s" +msgstr "%s: schimbare în gp: BRSGP %s" + +#: elf64-alpha.c:4693 +msgid "" +msgstr "" + +#: elf64-alpha.c:4698 +#, c-format +msgid "%s: !samegp reloc against symbol without .prologue: %s" +msgstr "%s: !samegp reloc apentru simbol fãrã .prologue: %s" + +#: elf64-alpha.c:4749 +#, c-format +msgid "%s: unhandled dynamic relocation against %s" +msgstr "%s: relocare dinamicã nemanipulabilã pentru %s" + +#: elf64-alpha.c:4832 +#, c-format +msgid "%s: dtp-relative relocation against dynamic symbol %s" +msgstr "%s: relocare relativã-dtp pentru simbolul dinamic %s" + +#: elf64-alpha.c:4855 +#, c-format +msgid "%s: tp-relative relocation against dynamic symbol %s" +msgstr "%s: relocare relativã-tp pentru simbolul dinamic %s" + +#: elf64-hppa.c:2086 +#, c-format +msgid "stub entry for %s cannot load .plt, dp offset = %ld" +msgstr "intrarea trunchiatã pentru %s nu poate încãrca .plt, offset dp = %ld" + +#: elf64-mmix.c:1032 +#, c-format +msgid "" +"%s: Internal inconsistency error for value for\n" +" linker-allocated global register: linked: 0x%lx%08lx != relaxed: 0x%lx%08lx\n" +msgstr "" +"%s: eroare internã de inconsistenþã pentru valoarea\n" +"registrului global alocat de linker: linkuit: 0x%lx%08lx != relaxat: 0x%lx%08lx\n" + +#: elf64-mmix.c:1416 +#, c-format +msgid "%s: base-plus-offset relocation against register symbol: (unknown) in %s" +msgstr "%s:relocare-offset-bazã-plus pentru simbolul registru: (necunoscut) în %s" + +#: elf64-mmix.c:1421 +#, c-format +msgid "%s: base-plus-offset relocation against register symbol: %s in %s" +msgstr "%s:relocare-offset-bazã-plus pentru simbolul registru: %s în %s" + +#: elf64-mmix.c:1465 +#, c-format +msgid "%s: register relocation against non-register symbol: (unknown) in %s" +msgstr "%s:relocare registru pentru simbolul non-registru: (necunoscut) în %s" + +#: elf64-mmix.c:1470 +#, c-format +msgid "%s: register relocation against non-register symbol: %s in %s" +msgstr "%s:relocare registru pentru simbolul non-registru: %s în %s" + +#: elf64-mmix.c:1507 +#, c-format +msgid "%s: directive LOCAL valid only with a register or absolute value" +msgstr "%s: directiva LOCAL este validã doar cu un registru sau o valoare absolutã" + +#: elf64-mmix.c:1535 +#, c-format +msgid "%s: LOCAL directive: Register $%ld is not a local register. First global register is $%ld." +msgstr "%s: directivã LOCAL: Registrulr $%ld nu este un registru local. Primul registru global $%ld." + +#: elf64-mmix.c:1994 +#, c-format +msgid "%s: Error: multiple definition of `%s'; start of %s is set in a earlier linked file\n" +msgstr "%s: Eroare: definiþii multiple ale `%s'; începutul lui %s este setat într-un fiºierlinkuit anterior\n" + +#: elf64-mmix.c:2053 +msgid "Register section has contents\n" +msgstr "Secþiunea registru nu are conþinut\n" + +#: elf64-mmix.c:2216 +#, c-format +msgid "" +"Internal inconsistency: remaining %u != max %u.\n" +" Please report this bug." +msgstr "" +"Inconsistenþã internã: rãmâne %u ! = max %u\n" +" Vã rugãm raportaþi acest bug." + +#: elf64-ppc.c:2388 libbfd.c:831 +#, c-format +msgid "%s: compiled for a big endian system and target is little endian" +msgstr "%s: compilat pentru un sistem big endiat iar þinta este little endian" + +#: elf64-ppc.c:2391 libbfd.c:833 +#, c-format +msgid "%s: compiled for a little endian system and target is big endian" +msgstr "%s: compilat pentru un sistem little endiat iar þinta este big endian" + +#: elf64-ppc.c:4857 +#, c-format +msgid "%s: unexpected reloc type %u in .opd section" +msgstr "%s: tip de relocare neaºteptat %u în secþiune .opd" + +#: elf64-ppc.c:4877 +#, c-format +msgid "%s: .opd is not a regular array of opd entries" +msgstr "%s: .opd nu este un domeniu(array) de intrãri opd" + +#: elf64-ppc.c:4897 +#, c-format +msgid "%s: undefined sym `%s' in .opd section" +msgstr "%s: sym nedefinit `%s' în secþiune .opd" + +#: elf64-ppc.c:6136 +#, c-format +msgid "can't find branch stub `%s'" +msgstr "nu pot gãsi ramura trunchiatã `%s'" + +#: elf64-ppc.c:6175 elf64-ppc.c:6250 +#, c-format +msgid "linkage table error against `%s'" +msgstr "eroare tabel de linkuire pentru `%s'" + +#: elf64-ppc.c:6340 +#, c-format +msgid "can't build branch stub `%s'" +msgstr "nu se poate construi ramura trunchiatã `%s'" + +#: elf64-ppc.c:7047 +msgid ".glink and .plt too far apart" +msgstr ".glink ºi .plt prea departe unul de altul" + +#: elf64-ppc.c:7135 +msgid "stubs don't match calculated size" +msgstr "trunchierile(stubs) sunt în neconcordanþã cu mãrimea calculatã" + +#: elf64-ppc.c:7147 +#, c-format +msgid "" +"linker stubs in %u groups\n" +" branch %lu\n" +" toc adjust %lu\n" +" long branch %lu\n" +" long toc adj %lu\n" +" plt call %lu" +msgstr "" +"trunchieri(stubs) de linker în grupurile %u\n" +" ramurã %lu\n" +" ajustare toc %lu\n" +" ramurã lungã %lu\n" +" ajust. lungã toc %lu\n" +" apelare plt %lu" + +#: elf64-ppc.c:7723 +#, c-format +msgid "%s(%s+0x%lx): automatic multiple TOCs not supported using your crt files; recompile with -mminimal-toc or upgrade gcc" +msgstr "%s(%s+0x%lx): TOCuri multiple nu sunt suportateîn folosirea fiºierelor voastre crt; recompilaþi cu -mminimal-toc sau upgradaþi gcc" + +#: elf64-ppc.c:7731 +#, c-format +msgid "%s(%s+0x%lx): sibling call optimization to `%s' does not allow automatic multiple TOCs; recompile with -mminimal-toc or -fno-optimize-sibling-calls, or make `%s' extern" +msgstr "%s(%s+0 x%lx): optimizare apelare sibling pentru `%s' nu permite automatTOCuri multiple; recompilaþi cu -mminimal-toc sau -fno-optimize-sibling-calls, sau faceþi(make) `%s' extern" + +#: elf64-ppc.c:8329 +#, c-format +msgid "%s: relocation %s is not supported for symbol %s." +msgstr "%s: relocarea %s nu este suportatã pentru simbolul %s." + +#: elf64-ppc.c:8408 +#, c-format +msgid "%s: error: relocation %s not a multiple of %d" +msgstr "%s: eroare: relocarea %s nu este multiplu de %d" + +#: elf64-sparc.c:1370 +#, c-format +msgid "%s: check_relocs: unhandled reloc type %d" +msgstr "%s: check_relocs: tip de relocare nemanipulabil %d" + +#: elf64-sparc.c:1407 +#, c-format +msgid "%s: Only registers %%g[2367] can be declared using STT_REGISTER" +msgstr "%s: Doar regiºtrii %%g[2367] pot fi declaraþi folosind STT_REGISTER" + +#: elf64-sparc.c:1427 +#, c-format +msgid "Register %%g%d used incompatibly: %s in %s, previously %s in %s" +msgstr "Registrul %%g%d a folosit incompatibilitãþi: %s în %s, anterior %s în %s" + +#: elf64-sparc.c:1450 +#, c-format +msgid "Symbol `%s' has differing types: REGISTER in %s, previously %s in %s" +msgstr "Simbolul `%s' are tipuri diferenþiate: REGISTER în %s, anterior %s în %s" + +#: elf64-sparc.c:1496 +#, c-format +msgid "Symbol `%s' has differing types: %s in %s, previously REGISTER in %s" +msgstr "Simbolul `%s' are tipuri diferenþiate: %s în %s, anterior REGISTER în %s" + +#: elf64-sparc.c:3053 +#, c-format +msgid "%s: linking UltraSPARC specific with HAL specific code" +msgstr "%s: linkuire cod specific UltraSPARC cu cod specific HAL" + +#: elf64-x86-64.c:739 +#, c-format +msgid "%s: %s' accessed both as normal and thread local symbol" +msgstr "%s: `%s' accesate ºi ca simboluri locale normale ºi ca simboluri locale pe fire (thread)" + +#: elfcode.h:1113 +#, c-format +msgid "%s: version count (%ld) does not match symbol count (%ld)" +msgstr "%s: numãrul versiunii(%ld) nu se potriveºte cu numãrul simbolului (%ld)" + +#: elfcode.h:1342 +#, c-format +msgid "%s(%s): relocation %d has invalid symbol index %ld" +msgstr "%s(%s): relocarea %d are indexul de simbol invalid %ld" + +#: elflink.c:1456 +#, c-format +msgid "%s: warning: unexpected redefinition of indirect versioned symbol `%s'" +msgstr "%s: avertisment: redefinire neaºteptatã a simbolului indirect cu versiune(versioned) `%s'" + +#: elflink.c:1807 +#, c-format +msgid "%s: undefined versioned symbol name %s" +msgstr "%s: nume de simbol versiune %s nedefinit" + +#: elflink.c:2142 +#, c-format +msgid "%s: relocation size mismatch in %s section %s" +msgstr "%s: nepotrivire a mãrimii de relocare în %s secþiunea %s" + +#: elflink.c:2434 +#, c-format +msgid "warning: type and size of dynamic symbol `%s' are not defined" +msgstr "avertisment: tipul ºi mãrimea simbolului dinamic `%s' nu sunt definite" + +#: elflink.h:1022 +#, c-format +msgid "%s: %s: invalid version %u (max %d)" +msgstr "%s: %s: versiune invalidã %u (max %d)" + +#: elflink.h:1063 +#, c-format +msgid "%s: %s: invalid needed version %d" +msgstr "%s: %s: versiune necesarã %d invalidã" + +#: elflink.h:1238 +#, c-format +msgid "Warning: alignment %u of symbol `%s' in %s is smaller than %u in %s" +msgstr "Avertisment: alinierea %u al simbolului `%s' din %s este mai micã decât %u în %s" + +#: elflink.h:1252 +#, c-format +msgid "Warning: size of symbol `%s' changed from %lu in %s to %lu in %s" +msgstr "Avertisment: mãrimea simbolului `%s' a fost schimbatã din %lu din %s în %lu din %s" + +#: elflink.h:2160 +#, c-format +msgid "%s: undefined version: %s" +msgstr "%s:versiune %s nedefinitã" + +#: elflink.h:2226 +#, c-format +msgid "%s: .preinit_array section is not allowed in DSO" +msgstr "%s: secþiunea .preinit_array section nu este permisã în DSO" + +#: elflink.h:3078 +msgid "Not enough memory to sort relocations" +msgstr "Nu existã memorie suficientã pentru a sorta relocãrile" + +#: elflink.h:3958 elflink.h:4001 +#, c-format +msgid "%s: could not find output section %s" +msgstr "%s: nu s-a putut gãsi secþiunea de output %s" + +#: elflink.h:3964 +#, c-format +msgid "warning: %s section has zero size" +msgstr "avertisment: secþiunea %s are mãrime zero" + +#: elflink.h:4483 +#, c-format +msgid "%s: %s symbol `%s' in %s is referenced by DSO" +msgstr "%s: %s simbolul `%s' în %s este referit de DSO" + +#: elflink.h:4564 +#, c-format +msgid "%s: could not find output section %s for input section %s" +msgstr "%s: nu am putut gãsi secþiunea de output %s pentru secþiunea de input %s" + +#: elflink.h:4666 +#, c-format +msgid "%s: %s symbol `%s' isn't defined" +msgstr "%s: %s simbolul `%s' nu este definit" + +#: elflink.h:5053 elflink.h:5095 +msgid "%T: discarded in section `%s' from %s\n" +msgstr "%T: abandonat(discarded) în secþiunea `%s' din %s\n" + +#: elfxx-mips.c:887 +msgid "static procedure (no name)" +msgstr "procedurã staticã (fãrã nume)" + +#: elfxx-mips.c:1897 +msgid "not enough GOT space for local GOT entries" +msgstr "nu existã destul spaþiu GOT pentru intrãrile GOT locale" + +#: elfxx-mips.c:3691 +#, c-format +msgid "%s: %s+0x%lx: jump to stub routine which is not jal" +msgstr "%s: %s+0x%lx: salt la rutinã ciot(stub) ce nu este jal" + +#: elfxx-mips.c:5192 +#, c-format +msgid "%s: Malformed reloc detected for section %s" +msgstr "%s: Relocare malformatã detectatã pentru secþiunea %s" + +#: elfxx-mips.c:5266 +#, c-format +msgid "%s: CALL16 reloc at 0x%lx not against global symbol" +msgstr "%s: relocarea CALL16 la 0x%lx nu este pe simbolul global" + +#: elfxx-mips.c:8692 +#, c-format +msgid "%s: illegal section name `%s'" +msgstr "%s: nume ilegal de secþiune `%s'" + +#: elfxx-mips.c:9025 +#, c-format +msgid "%s: endianness incompatible with that of the selected emulation" +msgstr "%s: endianness incompatibilã cu aceea a emulaþiei selectate" + +#: elfxx-mips.c:9037 +#, c-format +msgid "%s: ABI is incompatible with that of the selected emulation" +msgstr "%s: ABI este incompatibil cu cel al emulaþiei selectate" + +#: elfxx-mips.c:9104 +#, c-format +msgid "%s: warning: linking PIC files with non-PIC files" +msgstr "%s: avertisment: linkuire de fiºiere PIC cu fiºiere non-PIC" + +#: elfxx-mips.c:9121 +#, c-format +msgid "%s: linking 32-bit code with 64-bit code" +msgstr "%s: linkuire cod 32-biþi cu cod 64-biþi" + +#: elfxx-mips.c:9149 +#, c-format +msgid "%s: linking %s module with previous %s modules" +msgstr "%s: linkuire a modulului %s cu modulele%s anterioare" + +#: elfxx-mips.c:9172 +#, c-format +msgid "%s: ABI mismatch: linking %s module with previous %s modules" +msgstr "%s: nepotrivire ABI: linkuire modul %s cu module %s anterioare" + +#: elfxx-mips.c:9241 +msgid " [abi=O32]" +msgstr " [abi=O32]" + +#: elfxx-mips.c:9243 +msgid " [abi=O64]" +msgstr " [abi=O64]" + +#: elfxx-mips.c:9245 +msgid " [abi=EABI32]" +msgstr " [abi=EABI32]" + +#: elfxx-mips.c:9247 +msgid " [abi=EABI64]" +msgstr " [abi=EABI64]" + +#: elfxx-mips.c:9249 +msgid " [abi unknown]" +msgstr " [abi necunoscut]" + +#: elfxx-mips.c:9251 +msgid " [abi=N32]" +msgstr " [abi=N32]" + +#: elfxx-mips.c:9253 +msgid " [abi=64]" +msgstr " [abi=64]" + +#: elfxx-mips.c:9255 +msgid " [no abi set]" +msgstr " [abi nesetat]" + +#: elfxx-mips.c:9258 +msgid " [mips1]" +msgstr " [mips1]" + +#: elfxx-mips.c:9260 +msgid " [mips2]" +msgstr " [mips2]" + +#: elfxx-mips.c:9262 +msgid " [mips3]" +msgstr " [mips3]" + +#: elfxx-mips.c:9264 +msgid " [mips4]" +msgstr " [mips4]" + +#: elfxx-mips.c:9266 +msgid " [mips5]" +msgstr " [mips5]" + +#: elfxx-mips.c:9268 +msgid " [mips32]" +msgstr " [mips32]" + +#: elfxx-mips.c:9270 +msgid " [mips64]" +msgstr " [mips64]" + +#: elfxx-mips.c:9272 +msgid " [mips32r2]" +msgstr " [mips32r2]" + +#: elfxx-mips.c:9274 +msgid " [unknown ISA]" +msgstr " [ISA necunoscut]" + +#: elfxx-mips.c:9277 +msgid " [mdmx]" +msgstr " [mdmx]" + +#: elfxx-mips.c:9280 +msgid " [mips16]" +msgstr " [mips16]" + +#: elfxx-mips.c:9283 +msgid " [32bitmode]" +msgstr " [mod32biþi]" + +#: elfxx-mips.c:9285 +msgid " [not 32bitmode]" +msgstr " [non-mod32biþi]" + +#: i386linux.c:457 m68klinux.c:461 sparclinux.c:458 +#, c-format +msgid "Output file requires shared library `%s'\n" +msgstr "Fiºierul de output necesitã biblioteca globalã(shared) `%s'\n" + +#: i386linux.c:465 m68klinux.c:469 sparclinux.c:466 +#, c-format +msgid "Output file requires shared library `%s.so.%s'\n" +msgstr "Fiºierul de output necesitã biblioteca globalã(shared) `%s'.so.`%s'\n" + +#: i386linux.c:654 i386linux.c:704 m68klinux.c:661 m68klinux.c:709 +#: sparclinux.c:656 sparclinux.c:706 +#, c-format +msgid "Symbol %s not defined for fixups\n" +msgstr "Simbolul %s nu este definit pentru acceptare(fixups)\n" + +#: i386linux.c:728 m68klinux.c:733 sparclinux.c:730 +msgid "Warning: fixup count mismatch\n" +msgstr "Avertisment: nepotrivire numãrãtori acceptare(fixup)\n" + +#: ieee.c:293 +#, c-format +msgid "%s: string too long (%d chars, max 65535)" +msgstr "%s: ºir prea lung (%d caractere, max 65535)" + +#: ieee.c:428 +#, c-format +msgid "%s: unrecognized symbol `%s' flags 0x%x" +msgstr "%s: simbol necunoscut `%s' marcaje(flags) 0x%x" + +#: ieee.c:938 +#, c-format +msgid "%s: unimplemented ATI record %u for symbol %u" +msgstr "%s: înregistrare ATI neimplementatã %u pe simbolul %u" + +#: ieee.c:963 +#, c-format +msgid "%s: unexpected ATN type %d in external part" +msgstr "%s: tip ATN neaºteptat %d în parte externã" + +#: ieee.c:985 +#, c-format +msgid "%s: unexpected type after ATN" +msgstr "%s: tip neaºteptat dupã ATN" + +#: ihex.c:264 +#, c-format +msgid "%s:%d: unexpected character `%s' in Intel Hex file\n" +msgstr "%s:%d: caracter neaºteptat `%s' în fiºier Intel Hex\n" + +#: ihex.c:372 +#, c-format +msgid "%s:%u: bad checksum in Intel Hex file (expected %u, found %u)" +msgstr "%s:%u: checksum invalid în fiºier Intel Hex (se aºtepta %u, s-a gãsit %u)" + +#: ihex.c:426 +#, c-format +msgid "%s:%u: bad extended address record length in Intel Hex file" +msgstr "%s: %u: mãrime înregistrare a adresei extinse invalidã în fiºier Intel Hex" + +#: ihex.c:443 +#, c-format +msgid "%s:%u: bad extended start address length in Intel Hex file" +msgstr "%s: %u: mãrime adresã de start extinsã invalidã în fiºier Intel Hex" + +#: ihex.c:460 +#, c-format +msgid "%s:%u: bad extended linear address record length in Intel Hex file" +msgstr "%s: %u: mãrime înregistrare a adresei lineare extinse invalidã în fiºier Intel Hex" + +#: ihex.c:477 +#, c-format +msgid "%s:%u: bad extended linear start address length in Intel Hex file" +msgstr "%s: %u: mãrime adresã linearã de start extinsã invalidã în fiºier Intel Hex" + +#: ihex.c:494 +#, c-format +msgid "%s:%u: unrecognized ihex type %u in Intel Hex file\n" +msgstr "%s: %u: tip ihex necunoscut %u în fiºier Intel Hex\n" + +#: ihex.c:619 +#, c-format +msgid "%s: internal error in ihex_read_section" +msgstr "%s: eroare internã în ihex_read_section" + +#: ihex.c:654 +#, c-format +msgid "%s: bad section length in ihex_read_section" +msgstr "%s: mãrime secþiune invalidã în ihex_read_section" + +#: ihex.c:872 +#, c-format +msgid "%s: address 0x%s out of range for Intel Hex file" +msgstr "%s: adresa 0x%s este în afara domeniului(range) pentru fiºierul Intel Hex" + +#: libbfd.c:861 +#, c-format +msgid "Deprecated %s called at %s line %d in %s\n" +msgstr "%s învechitã apelatã la %s linia %d în %s\n" + +#: libbfd.c:864 +#, c-format +msgid "Deprecated %s called\n" +msgstr "%s învechitã apelatã\n" + +#: linker.c:1829 +#, c-format +msgid "%s: indirect symbol `%s' to `%s' is a loop" +msgstr "%s: simbolul indirect `%s' pentru `%s' este o buclã" + +#: linker.c:2697 +#, c-format +msgid "Attempt to do relocatable link with %s input and %s output" +msgstr "Încercare de a crea un link relocabil cu input %s ºi output %s" + +#: merge.c:896 +#, c-format +msgid "%s: access beyond end of merged section (%ld + %ld)" +msgstr "%s: acces dincolo de sfârºitul secþiunii concatenate(merged) (%ld + %ld)" + +#: mmo.c:503 +#, c-format +msgid "%s: No core to allocate section name %s\n" +msgstr "%s:Nu existã nucleu(core) pentru a aloca numele de secþiune %s\n" + +#: mmo.c:579 +#, c-format +msgid "%s: No core to allocate a symbol %d bytes long\n" +msgstr "%s: Nu existã nucleu(core) pentru a aloca un simbol lung de %d octeþi\n" + +#: mmo.c:1287 +#, c-format +msgid "%s: invalid mmo file: initialization value for $255 is not `Main'\n" +msgstr "%s: fiºier mmo invalid: valoare de iniþializare pentru $255 nu este 'Main'\n" + +#: mmo.c:1433 +#, c-format +msgid "%s: unsupported wide character sequence 0x%02X 0x%02X after symbol name starting with `%s'\n" +msgstr "%s: secvenþã mare(wide) de caractere 0x%02X 0x%02X nesuportatã dupã numele de simbol care începe cu `%s'\n" + +#: mmo.c:1674 +#, c-format +msgid "%s: invalid mmo file: unsupported lopcode `%d'\n" +msgstr "%s: fiºier mmo invalid: lopcode `%d' nesuportat\n" + +#: mmo.c:1684 +#, c-format +msgid "%s: invalid mmo file: expected YZ = 1 got YZ = %d for lop_quote\n" +msgstr "%s: fiºier mmo invalid: pentru lop_quote se aºtepta YZ = 1 s-a primit YZ= %d\n" + +#: mmo.c:1720 +#, c-format +msgid "%s: invalid mmo file: expected z = 1 or z = 2, got z = %d for lop_loc\n" +msgstr "%s: fiºier mmo invalid: pentru lop_loc se aºtepta z =1 sau z = 2 s-a primit z = %d\n" + +#: mmo.c:1766 +#, c-format +msgid "%s: invalid mmo file: expected z = 1 or z = 2, got z = %d for lop_fixo\n" +msgstr "%s: fiºier mmo invalid: pentru lop_fixo se aºtepta z =1 sau z = 2 s-a primit z = %d\n" + +#: mmo.c:1805 +#, c-format +msgid "%s: invalid mmo file: expected y = 0, got y = %d for lop_fixrx\n" +msgstr "%s: fiºier mmo invalid: pentru lop_fixrx se aºtepta y =0 s-a primit y = %d\n" + +#: mmo.c:1814 +#, c-format +msgid "%s: invalid mmo file: expected z = 16 or z = 24, got z = %d for lop_fixrx\n" +msgstr "%s: fiºier mmo invalid: pentru lop_fixrx se aºtepta z =16 sau z = 24 s-a primit z = %d\n" + +#: mmo.c:1837 +#, c-format +msgid "%s: invalid mmo file: leading byte of operand word must be 0 or 1, got %d for lop_fixrx\n" +msgstr "%s: fiºier mmo invalid: pentru lop_fixrx octetul de înceout al operandului word trebuie sã fie 0 sau 1, s-a primit %d\n" + +#: mmo.c:1860 +#, c-format +msgid "%s: cannot allocate file name for file number %d, %d bytes\n" +msgstr "%s: nu se poate aloca nume fiºier pentru fiºierul numãrul %d, %d octeþi\n" + +#: mmo.c:1880 +#, c-format +msgid "%s: invalid mmo file: file number %d `%s', was already entered as `%s'\n" +msgstr "%s: fiºier mmo invalid: fiºierul numãrul %d `%s' a fost deja introdus ca `%s'\n" + +#: mmo.c:1893 +#, c-format +msgid "%s: invalid mmo file: file name for number %d was not specified before use\n" +msgstr "%s: fiºier mmo invalid: numele de fiºier pentru numãrul %d nu a fost specificat înainte de folosire\n" + +#: mmo.c:1999 +#, c-format +msgid "%s: invalid mmo file: fields y and z of lop_stab non-zero, y: %d, z: %d\n" +msgstr "%s: fiºier mmo invalid: câmpurile y ºi z ale lop_stab sunt non-zero: y: %d, z: %d\n" + +#: mmo.c:2035 +#, c-format +msgid "%s: invalid mmo file: lop_end not last item in file\n" +msgstr "%s: fiºier mmo invalid: lop_end nu este ultimul element în fiºier\n" + +#: mmo.c:2048 +#, c-format +msgid "%s: invalid mmo file: YZ of lop_end (%ld) not equal to the number of tetras to the preceding lop_stab (%ld)\n" +msgstr "%s: fiºier mmo invalid: YZ al lop_end (%ld) nu este egal cu numerele tetras ale lop_stab precedent (%ld)\n" + +#: mmo.c:2698 +#, c-format +msgid "%s: invalid symbol table: duplicate symbol `%s'\n" +msgstr "%s: tabelã de simboluri invalidã: simbol `%s' duplicat\n" + +#: mmo.c:2949 +#, c-format +msgid "%s: Bad symbol definition: `Main' set to %s rather than the start address %s\n" +msgstr "%s: Definire invalidã de simbol: `Main' setat la %s în loc de adresa de start %s\n" + +#: mmo.c:3039 +#, c-format +msgid "%s: warning: symbol table too large for mmo, larger than 65535 32-bit words: %d. Only `Main' will be emitted.\n" +msgstr "%s: avertisment: tabela de simboluri prea mare pentru mmo, mai mare decâd 65535 cuvinte pe 32 de biþi: %d. Doar 'Main' va fi emis.\n" + +#: mmo.c:3084 +#, c-format +msgid "%s: internal error, symbol table changed size from %d to %d words\n" +msgstr "%s: eroare internã, tabela de simboluri ºi-a schimbat mãrimea din %d în %d cuvinte\n" + +#: mmo.c:3139 +#, c-format +msgid "%s: internal error, internal register section %s had contents\n" +msgstr "%s: eroare internã, secþiunea de regiºtri internã %s nu are conþinut\n" + +#: mmo.c:3191 +#, c-format +msgid "%s: no initialized registers; section length 0\n" +msgstr "%s: nu existã regiºtri iniþializaþi; lungime secþiune 0\n" + +#: mmo.c:3197 +#, c-format +msgid "%s: too many initialized registers; section length %ld\n" +msgstr "%s: prea mulþi regiºtri iniþializaþi; lungime secþiune %ld\n" + +#: mmo.c:3202 +#, c-format +msgid "%s: invalid start address for initialized registers of length %ld: 0x%lx%08lx\n" +msgstr "%s: adresã de start invalidã pentru regiºtrii iniþializaþi de lungime %ld: 0x%lx%08lx\n" + +#: oasys.c:1052 +#, c-format +msgid "%s: can not represent section `%s' in oasys" +msgstr "%s: nu se poate reprezenta secþiune `%s' în oasys" + +#: osf-core.c:137 +#, c-format +msgid "Unhandled OSF/1 core file section type %d\n" +msgstr "Tip nemanipulabil %d de fiºier nucleu(core) OSF/1\n" + +#: pe-mips.c:659 +#, c-format +msgid "%s: `ld -r' not supported with PE MIPS objects\n" +msgstr "%s: `ld -r' nu este suportat cu obiecte PE MIPS\n" + +#. OK, at this point the following variables are set up: +#. src = VMA of the memory we're fixing up +#. mem = pointer to memory we're fixing up +#. val = VMA of what we need to refer to +#. +#: pe-mips.c:795 +#, c-format +msgid "%s: unimplemented %s\n" +msgstr "%s: %s neimplementat\n" + +#: pe-mips.c:821 +#, c-format +msgid "%s: jump too far away\n" +msgstr "%s: salt prea departe(far away)\n" + +#: pe-mips.c:848 +#, c-format +msgid "%s: bad pair/reflo after refhi\n" +msgstr "%s: pair/reflo invalid dupã refhi\n" + +#. XXX code yet to be written. +#: peicode.h:787 +#, c-format +msgid "%s: Unhandled import type; %x" +msgstr "%s: Tip import nemanipulabil; %x" + +#: peicode.h:792 +#, c-format +msgid "%s: Unrecognised import type; %x" +msgstr "%s: Tip import necunoscut; %x" + +#: peicode.h:806 +#, c-format +msgid "%s: Unrecognised import name type; %x" +msgstr "%s: Tip nume import necunoscut; %x" + +#: peicode.h:1164 +#, c-format +msgid "%s: Unrecognised machine type (0x%x) in Import Library Format archive" +msgstr "%s: Tip maºinã necunoscut (0x%x) în arhiva Import Library Format" + +#: peicode.h:1176 +#, c-format +msgid "%s: Recognised but unhandled machine type (0x%x) in Import Library Format archive" +msgstr "%s: Tip de maºinã recunoscut dar nemanipulabil (0x%x) în arhiva Import Library Format" + +#: peicode.h:1193 +#, c-format +msgid "%s: size field is zero in Import Library Format header" +msgstr "%s: mãrimea câmpului din headerul Import Library Format este zero" + +#: peicode.h:1224 +#, c-format +msgid "%s: string not null terminated in ILF object file." +msgstr "%s: ºirul nenul terminat în fiºier obiect ILF." + +#: ppcboot.c:416 +msgid "" +"\n" +"ppcboot header:\n" +msgstr "" +"\n" +"header ppcboot:\n" + +#: ppcboot.c:417 +#, c-format +msgid "Entry offset = 0x%.8lx (%ld)\n" +msgstr "Offset intrare = 0x%.8lx (%ld)\n" + +#: ppcboot.c:418 +#, c-format +msgid "Length = 0x%.8lx (%ld)\n" +msgstr "Lungime = 0x%.8lx (%ld)\n" + +#: ppcboot.c:421 +#, c-format +msgid "Flag field = 0x%.2x\n" +msgstr "Câmp Marcaj(Flag) = 0x%.2x\n" + +#: ppcboot.c:427 +#, c-format +msgid "Partition name = \"%s\"\n" +msgstr "Nume Partiþie = \"%s\"\n" + +#: ppcboot.c:446 +#, c-format +msgid "" +"\n" +"Partition[%d] start = { 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x }\n" +msgstr "" +"\n" +"Start Partiþie[%d] = { 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x }\n" + +#: ppcboot.c:452 +#, c-format +msgid "Partition[%d] end = { 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x }\n" +msgstr "Sfârºit Partiþie[%d] = { 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x }\n" + +#: ppcboot.c:458 +#, c-format +msgid "Partition[%d] sector = 0x%.8lx (%ld)\n" +msgstr "Sector Partiþie[%d] sector = 0x%.8lx (%ld)\n" + +#: ppcboot.c:459 +#, c-format +msgid "Partition[%d] length = 0x%.8lx (%ld)\n" +msgstr "Mãrime Partiþie[%d] = 0x%.8lx (%ld)\n" + +#: som.c:5422 +msgid "som_sizeof_headers unimplemented" +msgstr "som_sizeof_headers neimplementatã" + +#: srec.c:302 +#, c-format +msgid "%s:%d: Unexpected character `%s' in S-record file\n" +msgstr "%s:%d: Caracter neaºteptat `%s'în fiºier S-record\n" + +#: stabs.c:319 +#, c-format +msgid "%s(%s+0x%lx): Stabs entry has invalid string index." +msgstr "%s(%s+0x%lx): Intrarea bruscã(stab) are index ºir invalid." + +#: syms.c:1019 +msgid "Unsupported .stab relocation" +msgstr "Relocare .stab nesuportatã" + +#: vms-gsd.c:356 +#, c-format +msgid "bfd_make_section (%s) failed" +msgstr "bfd_make_section (%s) eºuatã" + +#: vms-gsd.c:371 +#, c-format +msgid "bfd_set_section_flags (%s, %x) failed" +msgstr "bfd_set_section_flags (%s, %x) eºuatã" + +#: vms-gsd.c:407 +#, c-format +msgid "Size mismatch section %s=%lx, %s=%lx" +msgstr "Mãrime nepotrivitã secþiune %s=%lx, %s=%lx" + +#: vms-gsd.c:704 +#, c-format +msgid "unknown gsd/egsd subtype %d" +msgstr "subtip %d gsd/egsd necunoscut" + +#: vms-hdr.c:408 +msgid "Object module NOT error-free !\n" +msgstr "Modul obiect CU erori !\n" + +#: vms-misc.c:541 +#, c-format +msgid "Stack overflow (%d) in _bfd_vms_push" +msgstr "Depãºire(overflow) de stivã(%d) în bfd_vms_push" + +#: vms-misc.c:559 +msgid "Stack underflow in _bfd_vms_pop" +msgstr "Subfolosire(underflow) a stivei _bfd_vms_pop" + +#: vms-misc.c:918 +msgid "_bfd_vms_output_counted called with zero bytes" +msgstr "_bfd_vms_output_counted apelat cu zero octeþi" + +#: vms-misc.c:923 +msgid "_bfd_vms_output_counted called with too many bytes" +msgstr "_bfd_vms_output_counted apelat cu prea mulþi octeþi" + +#: vms-misc.c:1054 +#, c-format +msgid "Symbol %s replaced by %s\n" +msgstr "Simbolul %s înlocuit de %s\n" + +#: vms-misc.c:1117 +#, c-format +msgid "failed to enter %s" +msgstr "Eºec în introducerea %s" + +#: vms-tir.c:102 +msgid "No Mem !" +msgstr "Nu mai existã Mem !" + +#: vms-tir.c:383 +#, c-format +msgid "bad section index in %s" +msgstr "index de secþiune invalid în %s" + +#: vms-tir.c:396 +#, c-format +msgid "unsupported STA cmd %s" +msgstr "cmd STA %s nesuportatã" + +#: vms-tir.c:401 vms-tir.c:1261 +#, c-format +msgid "reserved STA cmd %d" +msgstr "cmd STA %d rezervatã" + +#: vms-tir.c:512 vms-tir.c:535 +#, c-format +msgid "%s: no symbol \"%s\"" +msgstr "%s: nu existã simbolul \"%s\"" + +#. unsigned shift +#. rotate +#. Redefine symbol to current location. +#. Define a literal. +#: vms-tir.c:602 vms-tir.c:714 vms-tir.c:824 vms-tir.c:842 vms-tir.c:850 +#: vms-tir.c:859 vms-tir.c:1584 +#, c-format +msgid "%s: not supported" +msgstr "%s: nesuportat" + +#: vms-tir.c:607 vms-tir.c:1439 +#, c-format +msgid "%s: not implemented" +msgstr "%s: neimplementat" + +#: vms-tir.c:611 vms-tir.c:1443 +#, c-format +msgid "reserved STO cmd %d" +msgstr "cmd STO %d rezervatã" + +#: vms-tir.c:729 vms-tir.c:1589 +#, c-format +msgid "reserved OPR cmd %d" +msgstr "cmd OPR %d rezervatã" + +#: vms-tir.c:797 vms-tir.c:1653 +#, c-format +msgid "reserved CTL cmd %d" +msgstr "cmd CTL %d rezervatã" + +#. stack byte from image +#. arg: none. +#: vms-tir.c:1169 +msgid "stack-from-image not implemented" +msgstr "stack-from-image neimplementatã" + +#: vms-tir.c:1187 +msgid "stack-entry-mask not fully implemented" +msgstr "stack-entry-mask neimplementatã complet" + +#. compare procedure argument +#. arg: cs symbol name +#. by argument index +#. da argument descriptor +#. +#. compare argument descriptor with symbol argument (ARG$V_PASSMECH) +#. and stack TRUE (args match) or FALSE (args dont match) value. +#: vms-tir.c:1201 +msgid "PASSMECH not fully implemented" +msgstr "PASSMECH neimplementatã complet" + +#: vms-tir.c:1220 +msgid "stack-local-symbol not fully implemented" +msgstr "stack-local-symbol neimplementatã complet" + +#: vms-tir.c:1233 +msgid "stack-literal not fully implemented" +msgstr "stack-literal neimplementatã complet" + +#: vms-tir.c:1254 +msgid "stack-local-symbol-entry-point-mask not fully implemented" +msgstr "stack-local-symbol-entry-point-mask neimplementatã complet" + +#: vms-tir.c:1531 vms-tir.c:1543 vms-tir.c:1555 vms-tir.c:1567 vms-tir.c:1632 +#: vms-tir.c:1640 vms-tir.c:1648 +#, c-format +msgid "%s: not fully implemented" +msgstr "%s: neimplementatã complet" + +#: vms-tir.c:1705 +#, c-format +msgid "obj code %d not found" +msgstr "codul abj %d nu a fost gãsit" + +#: vms-tir.c:2043 +#, c-format +msgid "SEC_RELOC with no relocs in section %s" +msgstr "SEC_RELOC fãrã relocãri în secþiunea %s" + +#: vms-tir.c:2331 +#, c-format +msgid "Unhandled relocation %s" +msgstr "Relocare nemanipulabilã %s" + +#: xcofflink.c:1244 +#, c-format +msgid "%s: `%s' has line numbers but no enclosing section" +msgstr "%s: `%s' are numere de linii dar nici o secþiune de închidere" + +#: xcofflink.c:1297 +#, c-format +msgid "%s: class %d symbol `%s' has no aux entries" +msgstr "%s: clasa %d simbolul `%s' nu are intrãri aux" + +#: xcofflink.c:1320 +#, c-format +msgid "%s: symbol `%s' has unrecognized csect type %d" +msgstr "%s: simbolul `%s' are tip necunoscut csect %d" + +#: xcofflink.c:1332 +#, c-format +msgid "%s: bad XTY_ER symbol `%s': class %d scnum %d scnlen %d" +msgstr "%s: simbol XTY_ER invalid `%s': clasa %d scnum %d scnlen %d" + +#: xcofflink.c:1368 +#, c-format +msgid "%s: XMC_TC0 symbol `%s' is class %d scnlen %d" +msgstr "%s: simblul XMC_TC0 `%s' este clasa %d scnlen %d" + +#: xcofflink.c:1520 +#, c-format +msgid "%s: csect `%s' not in enclosing section" +msgstr "%s: csect `%s' nu este în secþiunea de închidere" + +#: xcofflink.c:1627 +#, c-format +msgid "%s: misplaced XTY_LD `%s'" +msgstr "%s:XTY_LD `%s' rãtãcit" + +#: xcofflink.c:1958 +#, c-format +msgid "%s: reloc %s:%d not in csect" +msgstr "%s: relocarea %s:%d nu este în csect" + +#: xcofflink.c:2095 +#, c-format +msgid "%s: XCOFF shared object when not producing XCOFF output" +msgstr "%s: XCOFF shared object neproducând output XCOFF" + +#: xcofflink.c:2116 +#, c-format +msgid "%s: dynamic object with no .loader section" +msgstr "%s: obiect dinamic fãrã secþiune .loader" + +#: xcofflink.c:2761 +#, c-format +msgid "%s: no such symbol" +msgstr "%s: nu existã acest simbol" + +#: xcofflink.c:2894 +msgid "error: undefined symbol __rtinit" +msgstr "eroare: simbol __rtinit nedefinit" + +#: xcofflink.c:3455 +#, c-format +msgid "warning: attempt to export undefined symbol `%s'" +msgstr "avertisment: încercare de exportare a simbolului nedefinit `%s'" + +#: xcofflink.c:4448 +#, c-format +msgid "TOC overflow: 0x%lx > 0x10000; try -mminimal-toc when compiling" +msgstr "suprasolicitare(overflow) TOC: 0x%lx > 0x10000; încercaþi -mminimal-toc la compilare" + +#: xcofflink.c:5288 xcofflink.c:5755 xcofflink.c:5817 xcofflink.c:6119 +#, c-format +msgid "%s: loader reloc in unrecognized section `%s'" +msgstr "%s: relocare loader în secþiune necunoscutã `%s'" + +#: xcofflink.c:5310 xcofflink.c:6130 +#, c-format +msgid "%s: `%s' in loader reloc but not loader sym" +msgstr "%s: `%s' în relocare loader dar nu în loader sym" + +#: xcofflink.c:5325 +#, c-format +msgid "%s: loader reloc in read-only section %s" +msgstr "%s: relocare loader în secþiunea doar-în-citire %s" + +#: elf32-ia64.c:2392 elf64-ia64.c:2392 +msgid "@pltoff reloc against local symbol" +msgstr "relocare @pltoff pe simbol local" + +#: elf32-ia64.c:3804 elf64-ia64.c:3804 +#, c-format +msgid "%s: short data segment overflowed (0x%lx >= 0x400000)" +msgstr "%s: segment de date scurt depãºit(overflowed) (0x%lx >= 0x400000)" + +#: elf32-ia64.c:3815 elf64-ia64.c:3815 +#, c-format +msgid "%s: __gp does not cover short data segment" +msgstr "%s: __gp nu acoperã segmentul de date scurte" + +#: elf32-ia64.c:4131 elf64-ia64.c:4131 +#, c-format +msgid "%s: linking non-pic code in a shared library" +msgstr "%s: linkuire cod non-pic într-o bibliotecã globalã(shared)" + +#: elf32-ia64.c:4164 elf64-ia64.c:4164 +#, c-format +msgid "%s: @gprel relocation against dynamic symbol %s" +msgstr "%s: relocare @gprel pe simbolul dinamic %s" + +#: elf32-ia64.c:4224 elf64-ia64.c:4224 +#, c-format +msgid "%s: linking non-pic code in a position independent executable" +msgstr "%s: linkuire cod non-pic într-un executabil independent de poziþie" + +#: elf32-ia64.c:4363 elf64-ia64.c:4363 +#, c-format +msgid "%s: @internal branch to dynamic symbol %s" +msgstr "%s: ramurã @internal cãtre simbolul dinamic %s" + +#: elf32-ia64.c:4365 elf64-ia64.c:4365 +#, c-format +msgid "%s: speculation fixup to dynamic symbol %s" +msgstr "%s: rezolvare de speculaþie cãtre simbolul dinamic %s" + +#: elf32-ia64.c:4367 elf64-ia64.c:4367 +#, c-format +msgid "%s: @pcrel relocation against dynamic symbol %s" +msgstr "%s: relocare @pcrell pe simbolul dinamic %s" + +#: elf32-ia64.c:4579 elf64-ia64.c:4579 +msgid "unsupported reloc" +msgstr "relocare nesuportatã" + +#: elf32-ia64.c:4858 elf64-ia64.c:4858 +#, c-format +msgid "%s: linking trap-on-NULL-dereference with non-trapping files" +msgstr "%s: linkuire trap-on-NULL-dereference cu fiºiere non-trapping" + +#: elf32-ia64.c:4867 elf64-ia64.c:4867 +#, c-format +msgid "%s: linking big-endian files with little-endian files" +msgstr "%s: linkuire fiºiere big-endiancu fiºiere little-endian" + +#: elf32-ia64.c:4876 elf64-ia64.c:4876 +#, c-format +msgid "%s: linking 64-bit files with 32-bit files" +msgstr "%s: linkuire fiºiere pe 64-biþi cu fiºiere pe 32-biþi" + +#: elf32-ia64.c:4885 elf64-ia64.c:4885 +#, c-format +msgid "%s: linking constant-gp files with non-constant-gp files" +msgstr "%s: linkuire fiºiere constant-gp cu fiºiere non-constant-gp" + +#: elf32-ia64.c:4895 elf64-ia64.c:4895 +#, c-format +msgid "%s: linking auto-pic files with non-auto-pic files" +msgstr "%s: linkuire fiºiere auto-pic cu fiºiere non-auto-pic" + +#: peigen.c:985 pepigen.c:985 +#, c-format +msgid "%s: line number overflow: 0x%lx > 0xffff" +msgstr "%s: depãºire(overflow) numãr linii: 0x%lx > 0xffff" + +#: peigen.c:1002 pepigen.c:1002 +#, c-format +msgid "%s: reloc overflow 1: 0x%lx > 0xffff" +msgstr "%s: depãºire(overflow) relocare 1: 0x%lx > 0xffff" + +#: peigen.c:1016 pepigen.c:1016 +msgid "Export Directory [.edata (or where ever we found it)]" +msgstr "Director Exportare [.edata (sau oriunde se gãseºte)]" + +#: peigen.c:1017 pepigen.c:1017 +msgid "Import Directory [parts of .idata]" +msgstr "Director Importare [ pãrþi ale .idata]" + +#: peigen.c:1018 pepigen.c:1018 +msgid "Resource Directory [.rsrc]" +msgstr "Director Resursã [.rsrc]" + +#: peigen.c:1019 pepigen.c:1019 +msgid "Exception Directory [.pdata]" +msgstr "Director Excepþie [.pdata]" + +#: peigen.c:1020 pepigen.c:1020 +msgid "Security Directory" +msgstr "Director Securitate" + +#: peigen.c:1021 pepigen.c:1021 +msgid "Base Relocation Directory [.reloc]" +msgstr "Director Relocare de Bazã [.reloc]" + +#: peigen.c:1022 pepigen.c:1022 +msgid "Debug Directory" +msgstr "Director Debug" + +#: peigen.c:1023 pepigen.c:1023 +msgid "Description Directory" +msgstr "Director Descriere" + +#: peigen.c:1024 pepigen.c:1024 +msgid "Special Directory" +msgstr "Director Special" + +#: peigen.c:1025 pepigen.c:1025 +msgid "Thread Storage Directory [.tls]" +msgstr "Director Depozitare Fire(Thread) [.tls]" + +#: peigen.c:1026 pepigen.c:1026 +msgid "Load Configuration Directory" +msgstr "Director Încãrcare Configuraþie" + +#: peigen.c:1027 pepigen.c:1027 +msgid "Bound Import Directory" +msgstr "Director Importare de Graniþã(Bound)" + +#: peigen.c:1028 pepigen.c:1028 +msgid "Import Address Table Directory" +msgstr "Director Importare Tabelã de Adrese" + +#: peigen.c:1029 pepigen.c:1029 +msgid "Delay Import Directory" +msgstr "Director Importare Întârziere" + +#: peigen.c:1030 peigen.c:1031 pepigen.c:1030 pepigen.c:1031 +msgid "Reserved" +msgstr "Rezervat" + +#: peigen.c:1094 pepigen.c:1094 +msgid "" +"\n" +"There is an import table, but the section containing it could not be found\n" +msgstr "" +"\n" +"Existã o tabelã de importare, dar secþiunea care o conþine n-a putut fi gãsitã\n" + +#: peigen.c:1099 pepigen.c:1099 +#, c-format +msgid "" +"\n" +"There is an import table in %s at 0x%lx\n" +msgstr "" +"\n" +"Existã o tabelã de importare în %s la 0x%lx\n" + +#: peigen.c:1136 pepigen.c:1136 +#, c-format +msgid "" +"\n" +"Function descriptor located at the start address: %04lx\n" +msgstr "" +"\n" +"Descriptorul de funcþie localizat la adresa de start: %04lx\n" + +#: peigen.c:1139 pepigen.c:1139 +#, c-format +msgid "\tcode-base %08lx toc (loadable/actual) %08lx/%08lx\n" +msgstr "\tcode-base %08lx toc (încãrcabil/actual) %08lx/%08lx\n" + +#: peigen.c:1145 pepigen.c:1145 +msgid "" +"\n" +"No reldata section! Function descriptor not decoded.\n" +msgstr "" +"\n" +"Nu existã secþiune reldata! Descriptorul de funcþie nu este decodat.\n" + +#: peigen.c:1150 pepigen.c:1150 +#, c-format +msgid "" +"\n" +"The Import Tables (interpreted %s section contents)\n" +msgstr "" +"\n" +"Tabelele de Importare (interpretat conþinutul secþiunii %s)\n" + +#: peigen.c:1153 pepigen.c:1153 +msgid "" +" vma: Hint Time Forward DLL First\n" +" Table Stamp Chain Name Thunk\n" +msgstr "" +" vma: Sugestie Timp Înaintare DLL Primul\n" +" Tabel Marcaj Lanþ Nume Thunk\n" + +#: peigen.c:1204 pepigen.c:1204 +#, c-format +msgid "" +"\n" +"\tDLL Name: %s\n" +msgstr "" +"\n" +"\tNume DLL: %s\n" + +#: peigen.c:1215 pepigen.c:1215 +msgid "\tvma: Hint/Ord Member-Name Bound-To\n" +msgstr "\tvma: Sugestie/Ord Membru-Nume Salt-La\n" + +#: peigen.c:1240 pepigen.c:1240 +msgid "" +"\n" +"There is a first thunk, but the section containing it could not be found\n" +msgstr "" +"\n" +"Existã un prim thunk, dar secþiunea care îl conþine nu poate fi gãsitã\n" + +#: peigen.c:1380 pepigen.c:1380 +msgid "" +"\n" +"There is an export table, but the section containing it could not be found\n" +msgstr "" +"\n" +"Existã o tabelã de export, dar secþiunea ce o conþine nu poate fi gãsitã\n" + +#: peigen.c:1385 pepigen.c:1385 +#, c-format +msgid "" +"\n" +"There is an export table in %s at 0x%lx\n" +msgstr "" +"\n" +"Existã o tabelã de exportare în %s la 0x%lx\n" + +#: peigen.c:1416 pepigen.c:1416 +#, c-format +msgid "" +"\n" +"The Export Tables (interpreted %s section contents)\n" +"\n" +msgstr "" +"\n" +"Tabelele de Exportare (interpretare conþinut secþiune %s)\n" +"\n" + +#: peigen.c:1420 pepigen.c:1420 +#, c-format +msgid "Export Flags \t\t\t%lx\n" +msgstr "Marcaje(Flags) Exportare \t\t\t%lx\n" + +#: peigen.c:1423 pepigen.c:1423 +#, c-format +msgid "Time/Date stamp \t\t%lx\n" +msgstr "Marcaj(stamp) Orã/Datã \t\t%lx\n" + +#: peigen.c:1426 pepigen.c:1426 +#, c-format +msgid "Major/Minor \t\t\t%d/%d\n" +msgstr "Major/Minor \t\t\t%d/%d\n" + +#: peigen.c:1429 pepigen.c:1429 +msgid "Name \t\t\t\t" +msgstr "Nume \t\t\t\t" + +#: peigen.c:1435 pepigen.c:1435 +#, c-format +msgid "Ordinal Base \t\t\t%ld\n" +msgstr "Bazã Ordinalã \t\t\t%ld\n" + +#: peigen.c:1438 pepigen.c:1438 +msgid "Number in:\n" +msgstr "Numãr în:\n" + +#: peigen.c:1441 pepigen.c:1441 +#, c-format +msgid "\tExport Address Table \t\t%08lx\n" +msgstr "\t Tabelã Exportare Adrese \t\t%08lx\n" + +#: peigen.c:1445 pepigen.c:1445 +#, c-format +msgid "\t[Name Pointer/Ordinal] Table\t%08lx\n" +msgstr "\tTabelã [Nume Pointer/Ordinal]\t%08lx\n" + +#: peigen.c:1448 pepigen.c:1448 +msgid "Table Addresses\n" +msgstr "Adrese Tabelã\n" + +#: peigen.c:1451 pepigen.c:1451 +msgid "\tExport Address Table \t\t" +msgstr "\tTabelã Exportare de Adrese \t\t" + +#: peigen.c:1456 pepigen.c:1456 +msgid "\tName Pointer Table \t\t" +msgstr "\tNume Pointer Tabelã \t\t" + +#: peigen.c:1461 pepigen.c:1461 +msgid "\tOrdinal Table \t\t\t" +msgstr "\tOrdinal Tabelã \t\t\t" + +#: peigen.c:1476 pepigen.c:1476 +#, c-format +msgid "" +"\n" +"Export Address Table -- Ordinal Base %ld\n" +msgstr "" +"\n" +"Tabelã Exportare de Adrese -- Bazã Ordinalã %ld\n" + +#: peigen.c:1495 pepigen.c:1495 +msgid "Forwarder RVA" +msgstr "Trimiþãtor(Forwarder) RVA" + +#: peigen.c:1506 pepigen.c:1506 +msgid "Export RVA" +msgstr "Exportare RVA" + +#: peigen.c:1513 pepigen.c:1513 +msgid "" +"\n" +"[Ordinal/Name Pointer] Table\n" +msgstr "" +"\n" +"[Ordinal/Nume Pointer] Tabelã\n" + +#: peigen.c:1568 pepigen.c:1568 +#, c-format +msgid "Warning, .pdata section size (%ld) is not a multiple of %d\n" +msgstr "Avertisment, mãrimea secþiunii .pdata (%ld) nu este multiplu de %d\n" + +#: peigen.c:1572 pepigen.c:1572 +msgid "" +"\n" +"The Function Table (interpreted .pdata section contents)\n" +msgstr "" +"\n" +"Tabela de Funcþii (interpretare conþinut secþiune .pdata)\n" + +#: peigen.c:1575 pepigen.c:1575 +msgid " vma:\t\t\tBegin Address End Address Unwind Info\n" +msgstr " vma:\t\t\tAdresã Început Adresã Sfârºit Info Unwind\n" + +#: peigen.c:1577 pepigen.c:1577 +msgid "" +" vma:\t\tBegin End EH EH PrologEnd Exception\n" +" \t\tAddress Address Handler Data Address Mask\n" +msgstr "" +" vma:\t\tÎnceput Sfârºit EH EH PrologSfârºit Excepþii\n" +" \t\tAdresã Adresã Manipulant Date Adresã Mascã\n" + +#: peigen.c:1647 pepigen.c:1647 +msgid " Register save millicode" +msgstr " Registrul salveazã millicode " + +#: peigen.c:1650 pepigen.c:1650 +msgid " Register restore millicode" +msgstr "Registrul reface millicode" + +#: peigen.c:1653 pepigen.c:1653 +msgid " Glue code sequence" +msgstr "Secvenþã de cod lipitã(glue)" + +#: peigen.c:1705 pepigen.c:1705 +msgid "" +"\n" +"\n" +"PE File Base Relocations (interpreted .reloc section contents)\n" +msgstr "" +"\n" +"\n" +"Relocãri Bazã Fiºier PE (interpretare conþinut secþiune .reloc)\n" + +#: peigen.c:1735 pepigen.c:1735 +#, c-format +msgid "" +"\n" +"Virtual Address: %08lx Chunk size %ld (0x%lx) Number of fixups %ld\n" +msgstr "" +"\n" +"Adresã Virtualã: %08lx Mãrime Trunchiere %ld (0x%lx) Numãr acceptãri %ld\n" + +#: peigen.c:1748 pepigen.c:1748 +#, c-format +msgid "\treloc %4d offset %4x [%4lx] %s" +msgstr "\trelocarea %4d offset %4x [%4lx] %s" + +#. The MS dumpbin program reportedly ands with 0xff0f before +#. printing the characteristics field. Not sure why. No reason to +#. emulate it here. +#: peigen.c:1788 pepigen.c:1788 +#, c-format +msgid "" +"\n" +"Characteristics 0x%x\n" +msgstr "" +"\n" +"Caracteristici 0x%x\n" + +#~ msgid "%s: Unknown special linker type %d" +#~ msgstr "%s: Tip special necunoscut de linker %d" + +#~ msgid "v850ea architecture" +#~ msgstr "arhitecturã v850ea" + +#~ msgid "%s: Section %s is too large to add hole of %ld bytes" +#~ msgstr "%s: Secþiunea %s este prea mare pentru a adãuga o gaurã de %ld octeþi" + +#~ msgid "Error: out of memory" +#~ msgstr "Eroare: memorie plinã" + +#~ msgid "warning: relocation against removed section; zeroing" +#~ msgstr "avertisment: relocare pe secþiune eliminatã; se umple cu zero(zeroing)" + +#~ msgid "warning: relocation against removed section" +#~ msgstr "avertisment: relocare pe secþiune eliminatã" + +#~ msgid "local symbols in discarded section %s" +#~ msgstr "simboluri locale în secþiunea îndepãrtatã(discarded) %s" + +#~ msgid "%s: linking abicalls files with non-abicalls files" +#~ msgstr "%s: linkuire fiºiere abicalls cu fiºiere non-abicalls" + +#~ msgid "%s: ISA mismatch (-mips%d) with previous modules (-mips%d)" +#~ msgstr "%s: nepotrivire ISA (-mips%d) cu modulele anterioare (-mips%d)" + +#~ msgid "%s: ISA mismatch (%d) with previous modules (%d)" +#~ msgstr "%s: nepotrivire ISA (%d) cu modulele anterioare (%d)" + +#~ msgid "%s: dynamic relocation against speculation fixup" +#~ msgstr "%s: relocare dinamicã pe acceptare(fixup) speculativã" + +#~ msgid "%s: speculation fixup against undefined weak symbol" +#~ msgstr "%s: speculaþie acceptare(fixup) pe simbol ambiguu(weak) nedefinit" diff --git a/bfd/po/zh_CN.po b/bfd/po/zh_CN.po new file mode 100644 index 0000000..a7ca6d7 --- /dev/null +++ b/bfd/po/zh_CN.po @@ -0,0 +1,2702 @@ +# SOME DESCRIPTIVE TITLE. +# Copyright (C) 2003 Free Software Foundation, Inc. +# Wang Li , 2003. +# +msgid "" +msgstr "" +"Project-Id-Version: bfd 2.12.91\n" +"POT-Creation-Date: 2002-07-23 15:55-0400\n" +"PO-Revision-Date: 2003-03-11 09:46+0800\n" +"Last-Translator: Wang Li \n" +"Language-Team: Chinese (simplified) \n" +"MIME-Version: 1.0\n" +"Content-Type: text/plain; charset=gb2312\n" +"Content-Transfer-Encoding: 8bit\n" + +#: aout-adobe.c:197 +#, c-format +msgid "%s: Unknown section type in a.out.adobe file: %x\n" +msgstr "%s£ºa.out.adobe ÎļþÖнڵÄÀàÐÍδ֪£º%x\n" + +#: aout-cris.c:208 +#, c-format +msgid "%s: Invalid relocation type exported: %d" +msgstr "%s£ºµ¼³öÎÞЧµÄÖض¨Î»ÀàÐÍ£º%d" + +#: aout-cris.c:252 +#, c-format +msgid "%s: Invalid relocation type imported: %d" +msgstr "%s£ºµ¼ÈëÎÞЧµÄÖض¨Î»ÀàÐÍ£º%d" + +#: aout-cris.c:263 +#, c-format +msgid "%s: Bad relocation record imported: %d" +msgstr "%s£ºµ¼Èë´íÎóµÄÖض¨Î»¼Ç¼£º%d" + +#: aoutx.h:1282 aoutx.h:1699 +#, c-format +msgid "%s: can not represent section `%s' in a.out object file format" +msgstr "%s£ºÎÞ·¨ÔÚ a.out ¶ÔÏóÎļþ¸ñʽÖбíʾ½Ú¡°%s¡±" + +#: aoutx.h:1669 +#, c-format +msgid "%s: can not represent section for symbol `%s' in a.out object file format" +msgstr "%s£ºÎÞ·¨ÔÚ a.out ¶ÔÏóÎļþ¸ñʽÖÐΪ·ûºÅ¡°%s¡±±íʾ½Ú" + +#: aoutx.h:1671 +msgid "*unknown*" +msgstr "*δ֪*" + +#: aoutx.h:3732 +#, c-format +msgid "%s: relocateable link from %s to %s not supported" +msgstr "%s£º²»Ö§³Ö´Ó %s µ½ %s µÄ¿ÉÖض¨Î»µÄÁ¬½Ó" + +#: archive.c:1826 +msgid "Warning: writing archive was slow: rewriting timestamp\n" +msgstr "¾¯¸æ£ºÐ´Èë¹éµµ¹ýÂý£ºÖØÐÂдÈëʱ¼ä´Á\n" + +#: archive.c:2093 +msgid "Reading archive file mod timestamp" +msgstr "ÕýÔÚ¶ÁÈëÎļþÐÞ¸Äʱ¼ä´Á" + +#. FIXME: bfd can't call perror. +#: archive.c:2120 +msgid "Writing updated armap timestamp" +msgstr "ÕýÔÚ¸üРarmap ʱ¼ä´Á" + +#: bfd.c:274 +msgid "No error" +msgstr "ÎÞ´íÎó" + +#: bfd.c:275 +msgid "System call error" +msgstr "ϵͳµ÷ÓôíÎó" + +#: bfd.c:276 +msgid "Invalid bfd target" +msgstr "ÎÞЧµÄ bfd Ä¿±ê" + +#: bfd.c:277 +msgid "File in wrong format" +msgstr "Îļþ¸ñʽ´íÎó" + +#: bfd.c:278 +msgid "Archive object file in wrong format" +msgstr "¹éµµÄ¿±êÎļþ¸ñʽ´íÎó" + +#: bfd.c:279 +msgid "Invalid operation" +msgstr "ÎÞЧµÄ²Ù×÷" + +#: bfd.c:280 +msgid "Memory exhausted" +msgstr "ÄÚ´æºÄ¾¡" + +#: bfd.c:281 +msgid "No symbols" +msgstr "ÎÞ·ûºÅ" + +#: bfd.c:282 +msgid "Archive has no index; run ranlib to add one" +msgstr "¹éµµÃ»ÓÐË÷Òý£»ÔËÐÐ ranlib ÒÔÌí¼ÓÒ»¸ö" + +#: bfd.c:283 +msgid "No more archived files" +msgstr "ûÓиü¶àµÄ¹éµµÎļþ" + +#: bfd.c:284 +msgid "Malformed archive" +msgstr "»ûÐεĹ鵵" + +#: bfd.c:285 +msgid "File format not recognized" +msgstr "²»¿Éʶ±ðµÄÎļþ¸ñʽ" + +#: bfd.c:286 +msgid "File format is ambiguous" +msgstr "¶þÒåÐÔµÄÎļþ¸ñʽ" + +#: bfd.c:287 +msgid "Section has no contents" +msgstr "½ÚûÓÐÄÚÈÝ" + +#: bfd.c:288 +msgid "Nonrepresentable section on output" +msgstr "Êä³ö²»¿É±íʾµÄ½Ú" + +#: bfd.c:289 +msgid "Symbol needs debug section which does not exist" +msgstr "·ûºÅÐèÒª²»´æÔڵĵ÷ÊÔ½Ú" + +#: bfd.c:290 +msgid "Bad value" +msgstr "´íÎóµÄÖµ" + +#: bfd.c:291 +msgid "File truncated" +msgstr "Îļþ±»½Ø¶Ï" + +#: bfd.c:292 +msgid "File too big" +msgstr "Îļþ¹ý´ó" + +#: bfd.c:293 +msgid "#" +msgstr "#<ÎÞЧµÄ´íÎóÂë>" + +#: bfd.c:700 +#, c-format +msgid "BFD %s assertion fail %s:%d" +msgstr "BFD %s ¶ÏÑÔʧ°Ü %s£º%d" + +#: bfd.c:719 +#, c-format +msgid "BFD %s internal error, aborting at %s line %d in %s\n" +msgstr "BFD %1$s ÄÚ²¿´íÎó£¬Òì³£ÖÐÖ¹ÓÚ %4$s µÄ %3$d ÐÐµÄ %2$s\n" + +#: bfd.c:723 +#, c-format +msgid "BFD %s internal error, aborting at %s line %d\n" +msgstr "BFD %1$s ÄÚ²¿´íÎó£¬Òì³£ÖÐÖ¹ÓÚ %3$d ÐÐµÄ %2$s\n" + +#: bfd.c:725 +msgid "Please report this bug.\n" +msgstr "Ç뱨¸æ¸Ã BUG¡£\n" + +#: binary.c:306 +#, c-format +msgid "Warning: Writing section `%s' to huge (ie negative) file offset 0x%lx." +msgstr "¾¯¸æ£º½«½Ú¡°%s¡±Ð´Èë¹ý´ó(ÀýÈ縺Êý)ÎļþÆ«ÒÆÁ¿µÄλÖà 0x%lx¡£" + +#: coff-a29k.c:119 +msgid "Missing IHCONST" +msgstr "ÒÅʧ IHCONST" + +#: coff-a29k.c:180 +msgid "Missing IHIHALF" +msgstr "ÒÅʧ IHIHALF" + +#: coff-a29k.c:212 coff-or32.c:229 +msgid "Unrecognized reloc" +msgstr "ÎÞ·¨Ê¶±ðµÄÖض¨Î»" + +#: coff-a29k.c:408 +msgid "missing IHCONST reloc" +msgstr "ÒÅʧ IHCONST Öض¨Î»" + +#: coff-a29k.c:498 +msgid "missing IHIHALF reloc" +msgstr "ÒÅʧ IHIHALF Öض¨Î»" + +#: coff-alpha.c:881 coff-alpha.c:918 coff-alpha.c:1989 coff-mips.c:1432 +msgid "GP relative relocation used when GP not defined" +msgstr "ÔÚ GP 䶨ÒåµÄÇé¿öÏÂʹÓÃÁË GP Ïà¶ÔÖض¨Î»" + +#: coff-alpha.c:1485 +msgid "using multiple gp values" +msgstr "ʹÓÃÁ˶à¸ö GP Öµ" + +#: coff-arm.c:1066 elf32-arm.h:285 +#, c-format +msgid "%s: unable to find THUMB glue '%s' for `%s'" +msgstr "" + +#: coff-arm.c:1096 elf32-arm.h:320 +#, c-format +msgid "%s: unable to find ARM glue '%s' for `%s'" +msgstr "" + +#: coff-arm.c:1391 coff-arm.c:1486 elf32-arm.h:887 elf32-arm.h:991 +#, c-format +msgid "%s(%s): warning: interworking not enabled." +msgstr "" + +#: coff-arm.c:1395 elf32-arm.h:994 +#, c-format +msgid " first occurrence: %s: arm call to thumb" +msgstr "" + +#: coff-arm.c:1490 elf32-arm.h:890 +#, c-format +msgid " first occurrence: %s: thumb call to arm" +msgstr "" + +#: coff-arm.c:1493 +msgid " consider relinking with --support-old-code enabled" +msgstr " ³¢ÊÔÆôÓà --support-old-code ÖØÐÂÁ¬½Ó" + +#: coff-arm.c:1785 coff-tic80.c:686 cofflink.c:3031 +#, c-format +msgid "%s: bad reloc address 0x%lx in section `%s'" +msgstr "" + +#: coff-arm.c:2127 +#, c-format +msgid "%s: illegal symbol index in reloc: %d" +msgstr "%s£ºÖض¨Î»ÖзǷ¨µÄ·ûºÅË÷Òý£º%d" + +#: coff-arm.c:2255 +#, c-format +msgid "ERROR: %s is compiled for APCS-%d, whereas %s is compiled for APCS-%d" +msgstr "´íÎó£º%s ÊÇΪ APCS-%d ±àÒëµÄ£¬¶ø %s ÊÇΪ APCS-%d ±àÒëµÄ" + +#: coff-arm.c:2270 elf32-arm.h:2297 +#, c-format +msgid "ERROR: %s passes floats in float registers, whereas %s passes them in integer registers" +msgstr "´íÎó£º%s ÔÚ¸¡µã¼Ä´æÆ÷Öд«µÝ¸¡µãÊý£¬¶ø %s ÔÚÕûÊý¼Ä´æÆ÷Öд«µÝËüÃÇ" + +#: coff-arm.c:2273 elf32-arm.h:2302 +#, c-format +msgid "ERROR: %s passes floats in integer registers, whereas %s passes them in float registers" +msgstr "´íÎó£º%s ÔÚÕûÊý¼Ä´æÆ÷Öд«µÝ¸¡µãÊý£¬¶ø %s ÔÚ¸¡µãÊý¼Ä´æÆ÷Öд«µÝËüÃÇ" + +#: coff-arm.c:2288 +#, c-format +msgid "ERROR: %s is compiled as position independent code, whereas target %s is absolute position" +msgstr "´íÎó£º%s ±»±àÒëΪλÖÃÎ޹شúÂ룬¶øÄ¿±ê %s ²ÉÓþø¶ÔλÖÃ" + +#: coff-arm.c:2291 +#, c-format +msgid "ERROR: %s is compiled as absolute position code, whereas target %s is position independent" +msgstr "´íÎó£º%s ±»±àÒëΪ¾ø¶ÔλÖôúÂ룬¶øÄ¿±ê %s ÊÇλÖÃÎ޹صÄ" + +#: coff-arm.c:2320 elf32-arm.h:2358 +#, c-format +msgid "Warning: %s supports interworking, whereas %s does not" +msgstr "¾¯¸æ£º%s Ö§³Ö»¥²Ù×÷£¬¶ø %s ²»Ö§³Ö" + +#: coff-arm.c:2323 elf32-arm.h:2365 +#, c-format +msgid "Warning: %s does not support interworking, whereas %s does" +msgstr "¾¯¸æ£º%s ²»Ö§³Ö»¥²Ù×÷£¬¶ø %s Ö§³Ö" + +#: coff-arm.c:2350 +#, c-format +msgid "private flags = %x:" +msgstr "˽ÓбêÖ¾ = %x£º" + +#: coff-arm.c:2358 elf32-arm.h:2418 +msgid " [floats passed in float registers]" +msgstr " [ÔÚ¸¡µã¼Ä´æÆ÷Öд«µÝ¸¡µãÊý]" + +#: coff-arm.c:2360 +msgid " [floats passed in integer registers]" +msgstr " [ÔÚÕûÊý¼Ä´æÆ÷Öд«µÝ¸¡µãÊý]" + +#: coff-arm.c:2363 elf32-arm.h:2421 +msgid " [position independent]" +msgstr " [λÖÃÎÞ¹Ø]" + +#: coff-arm.c:2365 +msgid " [absolute position]" +msgstr " [¾ø¶ÔλÖÃ]" + +#: coff-arm.c:2369 +msgid " [interworking flag not initialised]" +msgstr " [»¥²Ù×÷±ê־δ³õʼ»¯]" + +#: coff-arm.c:2371 +msgid " [interworking supported]" +msgstr " [Ö§³Ö»¥²Ù×÷]" + +#: coff-arm.c:2373 +msgid " [interworking not supported]" +msgstr " [²»Ö§³Ö»¥²Ù×÷]" + +#: coff-arm.c:2421 elf32-arm.h:2124 +#, c-format +msgid "Warning: Not setting interworking flag of %s since it has already been specified as non-interworking" +msgstr "¾¯¸æ£ºÓÉÓÚ %s ÒѾ­±»Ö¸¶¨Îª²»¿É»¥²Ù×÷µÄ£¬Òò¶øûÓÐÉ趨»¥²Ù×÷±êÖ¾" + +#: coff-arm.c:2425 elf32-arm.h:2128 +#, c-format +msgid "Warning: Clearing the interworking flag of %s due to outside request" +msgstr "¾¯¸æ£ºÕýÔÚ¸ù¾ÝÍâ½çÇëÇóÇå³ý %s µÄ»¥²Ù×÷±êÖ¾" + +#: coff-i960.c:136 coff-i960.c:485 +msgid "uncertain calling convention for non-COFF symbol" +msgstr "¹ØÓÚ·Ç-COFF ·ûºÅ²»È·¶¨µÄµ÷ÓÃÔ¼¶¨" + +#: coff-m68k.c:481 coff-mips.c:2429 elf32-m68k.c:2157 elf32-mips.c:1844 +msgid "unsupported reloc type" +msgstr "²»Ö§³ÖµÄÖض¨Î»ÀàÐÍ" + +#: coff-mips.c:874 elf32-mips.c:1062 elf64-mips.c:1609 +msgid "GP relative relocation when _gp not defined" +msgstr "" + +#. No other sections should appear in -membedded-pic +#. code. +#: coff-mips.c:2466 +msgid "reloc against unsupported section" +msgstr "¹ØÓÚ²»Ö§³Ö½ÚµÄÖض¨Î»" + +#: coff-mips.c:2474 +msgid "reloc not properly aligned" +msgstr "Öض¨Î»Ã»ÓÐÕýÈ·¶ÔÆë" + +#: coff-rs6000.c:2766 +#, c-format +msgid "%s: unsupported relocation type 0x%02x" +msgstr "%s£º²»Ö§³ÖµÄÖض¨Î»ÀàÐÍ 0x%02x" + +#: coff-rs6000.c:2859 +#, c-format +msgid "%s: TOC reloc at 0x%x to symbol `%s' with no TOC entry" +msgstr "" + +#: coff-rs6000.c:3590 coff64-rs6000.c:2091 +#, c-format +msgid "%s: symbol `%s' has unrecognized smclas %d" +msgstr "" + +#: coff-tic54x.c:279 coff-tic80.c:449 +#, c-format +msgid "Unrecognized reloc type 0x%x" +msgstr "ÎÞ·¨Ê¶±ðµÄÖض¨Î»ÀàÐÍ 0x%x" + +#: coff-tic54x.c:390 coffcode.h:4974 +#, c-format +msgid "%s: warning: illegal symbol index %ld in relocs" +msgstr "%s£º¾¯¸æ£ºÖض¨Î»ÖзǷ¨µÄ·ûºÅË÷Òý %ld" + +#: coff-w65.c:363 +#, c-format +msgid "ignoring reloc %s\n" +msgstr "ÕýÔÚºöÂÔÖض¨Î» %s\n" + +#: coffcode.h:1086 +#, c-format +msgid "%s (%s): Section flag %s (0x%x) ignored" +msgstr "%s (%s)£ººöÂÔ½Ú±êÖ¾ %s (0x%x)" + +#: coffcode.h:2143 +#, c-format +msgid "Unrecognized TI COFF target id '0x%x'" +msgstr "ÎÞ·¨Ê¶±ðµÄ TI COFF Ä¿±ê id ¡°0x%x¡±" + +#: coffcode.h:4365 +#, c-format +msgid "%s: warning: illegal symbol index %ld in line numbers" +msgstr "%s£º¾¯¸æ£ºÐкÅÖеķǷ¨·ûºÅË÷Òý %ld" + +#: coffcode.h:4379 +#, c-format +msgid "%s: warning: duplicate line number information for `%s'" +msgstr "%s£º¾¯¸æ£ºÎª¡°%s¡±¸´ÖÆÐкÅÐÅÏ¢" + +#: coffcode.h:4736 +#, c-format +msgid "%s: Unrecognized storage class %d for %s symbol `%s'" +msgstr "" + +#: coffcode.h:4867 +#, c-format +msgid "warning: %s: local symbol `%s' has no section" +msgstr "¾¯¸æ£º%s£º±¾µØ·ûºÅ¡°%s¡±Ã»ÓнÚ" + +#: coffcode.h:5012 +#, c-format +msgid "%s: illegal relocation type %d at address 0x%lx" +msgstr "%1$s£ºÎ»ÓÚµØÖ· 0x%3$lx ´¦µÄ·Ç·¨Öض¨Î»ÀàÐÍ %2$d" + +#: coffgen.c:1661 +#, c-format +msgid "%s: bad string table size %lu" +msgstr "%s£º×Ö·û´®±íµÄ´óС´íÎó %lu" + +#: cofflink.c:534 elflink.h:1912 +#, c-format +msgid "Warning: type of symbol `%s' changed from %d to %d in %s" +msgstr "¾¯¸æ£º%4$s ÖеķûºÅ¡°%1$s¡±µÄÀàÐÍÓÉ %2$d ±äΪ %3$d" + +#: cofflink.c:2321 +#, c-format +msgid "%s: relocs in section `%s', but it has no contents" +msgstr "" + +#: cofflink.c:2664 coffswap.h:877 +#, c-format +msgid "%s: %s: reloc overflow: 0x%lx > 0xffff" +msgstr "%s£º%s£ºÖض¨Î»Òç³ö£º0x%lx > 0xffff" + +#: cofflink.c:2673 coffswap.h:864 +#, c-format +msgid "%s: warning: %s: line number overflow: 0x%lx > 0xffff" +msgstr "%s£º¾¯¸æ£º%s£ºÐкÅÒç³ö£º0x%lx > 0xffff" + +#: dwarf2.c:382 +msgid "Dwarf Error: Can't find .debug_str section." +msgstr "С´íÎó£ºÎÞ·¨ÕÒµ½ .debug_str ½Ú¡£" + +#: dwarf2.c:399 +#, c-format +msgid "Dwarf Error: DW_FORM_strp offset (%lu) greater than or equal to .debug_str size (%lu)." +msgstr "" + +#: dwarf2.c:543 +msgid "Dwarf Error: Can't find .debug_abbrev section." +msgstr "С´íÎó£ºÎÞ·¨ÕÒµ½ .debug_abbrev ½Ú¡£" + +#: dwarf2.c:560 +#, c-format +msgid "Dwarf Error: Abbrev offset (%lu) greater than or equal to .debug_abbrev size (%lu)." +msgstr "" + +#: dwarf2.c:757 +#, c-format +msgid "Dwarf Error: Invalid or unhandled FORM value: %u." +msgstr "С´íÎó£ºÎÞЧ»òδ´¦ÀíµÄ±íµ¥Öµ£º%u¡£" + +#: dwarf2.c:852 +msgid "Dwarf Error: mangled line number section (bad file number)." +msgstr "" + +#: dwarf2.c:938 +msgid "Dwarf Error: Can't find .debug_line section." +msgstr "С´íÎó£ºÎÞ·¨ÕÒµ½ .debug_line ½Ú¡£" + +#: dwarf2.c:961 +#, c-format +msgid "Dwarf Error: Line offset (%lu) greater than or equal to .debug_line size (%lu)." +msgstr "" + +#: dwarf2.c:1159 +msgid "Dwarf Error: mangled line number section." +msgstr "" + +#: dwarf2.c:1355 dwarf2.c:1566 +#, c-format +msgid "Dwarf Error: Could not find abbrev number %u." +msgstr "" + +#: dwarf2.c:1527 +#, c-format +msgid "Dwarf Error: found dwarf version '%u', this reader only handles version 2 information." +msgstr "" + +#: dwarf2.c:1534 +#, c-format +msgid "Dwarf Error: found address size '%u', this reader can not handle sizes greater than '%u'." +msgstr "" + +#: dwarf2.c:1557 +#, c-format +msgid "Dwarf Error: Bad abbrev number: %u." +msgstr "С´íÎ󣺴íÎóµÄËõд±àºÅ£º%u¡£" + +#: ecoff.c:1318 +#, c-format +msgid "Unknown basic type %d" +msgstr "δ֪µÄ»ù±¾ÀàÐÍ %d" + +#: ecoff.c:1578 +#, c-format +msgid "" +"\n" +" End+1 symbol: %ld" +msgstr "" +"\n" +" End+1 ·ûºÅ£º%ld" + +#: ecoff.c:1585 ecoff.c:1588 +#, c-format +msgid "" +"\n" +" First symbol: %ld" +msgstr "" +"\n" +" µÚÒ»¸ö·ûºÅ£º%ld" + +#: ecoff.c:1600 +#, c-format +msgid "" +"\n" +" End+1 symbol: %-7ld Type: %s" +msgstr "" +"\n" +" End+1 ·ûºÅ£º%-7ld ÀàÐÍ£º%s" + +#: ecoff.c:1607 +#, c-format +msgid "" +"\n" +" Local symbol: %ld" +msgstr "" +"\n" +" ±¾µØ·ûºÅ£º%ld" + +#: ecoff.c:1615 +#, c-format +msgid "" +"\n" +" struct; End+1 symbol: %ld" +msgstr "" +"\n" +" ½á¹¹£»End+1 ·ûºÅ£º%ld" + +#: ecoff.c:1620 +#, c-format +msgid "" +"\n" +" union; End+1 symbol: %ld" +msgstr "" +"\n" +" ÁªºÏ£»End+1 ·ûºÅ£º%ld" + +#: ecoff.c:1625 +#, c-format +msgid "" +"\n" +" enum; End+1 symbol: %ld" +msgstr "" +"\n" +" ö¾Ù£»End+1 ·ûºÅ£º%ld" + +#: ecoff.c:1631 +#, c-format +msgid "" +"\n" +" Type: %s" +msgstr "" +"\n" +" ÀàÐÍ£º%s" + +#: elf-hppa.h:1476 elf-hppa.h:1509 elf32-ppc.c:3091 elf32-sh.c:4213 +#: elf64-sh64.c:1659 +#, c-format +msgid "%s: warning: unresolvable relocation against symbol `%s' from %s section" +msgstr "%1$s£º¾¯¸æ£ºÀ´×Ô %3$s ½ÚµÄ¹ØÓÚ·ûºÅ¡°%2$s¡±µÄ²»¿É½âÎöµÄÖض¨Î»" + +#: elf-m10200.c:446 elf-m10300.c:656 elf32-arm.h:2084 elf32-avr.c:833 +#: elf32-cris.c:1403 elf32-d10v.c:481 elf32-fr30.c:635 elf32-frv.c:809 +#: elf32-h8300.c:548 elf32-i860.c:1031 elf32-m32r.c:1278 elf32-openrisc.c:439 +#: elf32-v850.c:1691 elf32-xstormy16.c:933 elf64-mmix.c:1302 +msgid "internal error: out of range error" +msgstr "ÄÚ²¿´íÎ󣺳¬³ö·¶Î§´íÎó" + +#: elf-m10200.c:450 elf-m10300.c:660 elf32-arm.h:2088 elf32-avr.c:837 +#: elf32-cris.c:1407 elf32-d10v.c:485 elf32-fr30.c:639 elf32-frv.c:813 +#: elf32-h8300.c:552 elf32-i860.c:1035 elf32-m32r.c:1282 elf32-openrisc.c:443 +#: elf32-v850.c:1695 elf32-xstormy16.c:937 elf64-mmix.c:1306 elfxx-mips.c:5264 +msgid "internal error: unsupported relocation error" +msgstr "ÄÚ²¿´íÎ󣺲»Ö§³ÖµÄÖض¨Î»´íÎó" + +#: elf-m10200.c:454 elf-m10300.c:664 elf32-arm.h:2092 elf32-d10v.c:489 +#: elf32-h8300.c:556 elf32-m32r.c:1286 +msgid "internal error: dangerous error" +msgstr "ÄÚ²¿´íÎó£ºÎ£ÏյĴíÎó" + +#: elf-m10200.c:458 elf-m10300.c:668 elf32-arm.h:2096 elf32-avr.c:845 +#: elf32-cris.c:1415 elf32-d10v.c:493 elf32-fr30.c:647 elf32-frv.c:821 +#: elf32-h8300.c:560 elf32-i860.c:1043 elf32-m32r.c:1290 elf32-openrisc.c:451 +#: elf32-v850.c:1715 elf32-xstormy16.c:945 elf64-mmix.c:1314 +msgid "internal error: unknown error" +msgstr "ÄÚ²¿´íÎó£ºÎ´ÖªµÄ´íÎó" + +#: elf.c:343 +#, c-format +msgid "%s: invalid string offset %u >= %lu for section `%s'" +msgstr "" + +#: elf.c:589 +#, c-format +msgid "%s: invalid SHT_GROUP entry" +msgstr "%s£ºÎÞЧµÄ SHT_GROUP ÌõÄ¿" + +#: elf.c:660 +#, c-format +msgid "%s: no group info for section %s" +msgstr "%s£ºÃ»ÓйØÓÚ½Ú %s µÄ×éÐÅÏ¢" + +#: elf.c:1023 +msgid "" +"\n" +"Program Header:\n" +msgstr "" +"\n" +"³ÌÐòÍ·£º\n" + +#: elf.c:1073 +msgid "" +"\n" +"Dynamic Section:\n" +msgstr "" +"\n" +"¶¯Ì¬½Ú£º\n" + +#: elf.c:1202 +msgid "" +"\n" +"Version definitions:\n" +msgstr "" +"\n" +"°æ±¾¶¨Ò壺\n" + +#: elf.c:1225 +msgid "" +"\n" +"Version References:\n" +msgstr "" +"\n" +"°æ±¾ÒýÓãº\n" + +#: elf.c:1230 +#, c-format +msgid " required from %s:\n" +msgstr "" + +#: elf.c:1902 +#, c-format +msgid "%s: invalid link %lu for reloc section %s (index %u)" +msgstr "" + +#: elf.c:3603 +#, c-format +msgid "%s: Not enough room for program headers (allocated %u, need %u)" +msgstr "%s£ºÃ»ÓÐ×ã¹»µÄ¿Õ¼ä±£´æ³ÌÐòÍ·£¨·ÖÅä %u£¬ÐèÒª %u£©" + +#: elf.c:3708 +#, c-format +msgid "%s: Not enough room for program headers, try linking with -N" +msgstr "%s£ºÃ»ÓÐ×ã¹»µÄ¿Õ¼ä±£´æ³ÌÐòÍ·£¬ÊÔÓà -N ½øÐÐÁ¬½Ó" + +#: elf.c:3833 +#, c-format +msgid "Error: First section in segment (%s) starts at 0x%x whereas the segment starts at 0x%x" +msgstr "´íÎ󣺶Π(%s) ÖеĵÚÒ»¸ö½Ú¿ªÊ¼ÓÚ 0x%x£¬È»¶ø¶Î¿ªÊ¼ÓÚ 0x%x" + +#: elf.c:4148 +#, c-format +msgid "%s: warning: allocated section `%s' not in segment" +msgstr "%s£º¾¯¸æ£ºÒÑ·ÖÅäµÄ½Ú¡°%s¡±²»ÔÚ¶ÎÖÐ" + +#: elf.c:4472 +#, c-format +msgid "%s: symbol `%s' required but not present" +msgstr "%s£º±ØÐèµÄ·ûºÅ¡°%s¡±²»´æÔÚ" + +#: elf.c:4749 +#, c-format +msgid "%s: warning: Empty loadable segment detected, is this intentional ?\n" +msgstr "%s£º¾¯¸æ£º·¢ÏֿյĿÉ×°Èë¶Î£¬ËüÊÇÄÚ²¿µÄ£¿\n" + +#: elf.c:6193 +#, c-format +msgid "%s: unsupported relocation type %s" +msgstr "%s£º²»Ö§³ÖµÄÖض¨Î»µÄÀàÐÍ %s" + +#: elf32-arm.h:1221 +#, c-format +msgid "%s: Warning: Arm BLX instruction targets Arm function '%s'." +msgstr "" + +#: elf32-arm.h:1417 +#, c-format +msgid "%s: Warning: Thumb BLX instruction targets thumb function '%s'." +msgstr "" + +#: elf32-arm.h:1914 elf32-sh.c:4125 +#, c-format +msgid "%s(%s+0x%lx): %s relocation against SEC_MERGE section" +msgstr "%s(%s+0x%lx)£º¹ØÓÚ SEC_MERGE ½ÚµÄÖض¨Î» %s" + +#: elf32-arm.h:2008 +#, c-format +msgid "%s: warning: unresolvable relocation %d against symbol `%s' from %s section" +msgstr "" + +#: elf32-arm.h:2176 +#, c-format +msgid "Warning: Clearing the interworking flag of %s because non-interworking code in %s has been linked with it" +msgstr "" + +#: elf32-arm.h:2271 +#, c-format +msgid "ERROR: %s is compiled for EABI version %d, whereas %s is compiled for version %d" +msgstr "´íÎó£º%s ÊÇΪ EABI °æ±¾ %d ±àÒëµÄ£¬¶ø %s ÔòÊÇΪ°æ±¾ %d ±àÒëµÄ" + +#: elf32-arm.h:2285 +#, c-format +msgid "ERROR: %s is compiled for APCS-%d, whereas target %s uses APCS-%d" +msgstr "´íÎó£º%s ÊÇΪ APCS-%d ±àÒëµÄ£¬¶øÄ¿±ê %s ʹÓà APCS-%d" + +#: elf32-arm.h:2313 +#, c-format +msgid "ERROR: %s uses VFP instructions, whereas %s uses FPA instructions" +msgstr "´íÎó£º%s ʹÓà VFP Ö¸Á¶ø %s ʹÓà FPA Ö¸Áî" + +#: elf32-arm.h:2318 +#, c-format +msgid "ERROR: %s uses FPA instructions, whereas %s uses VFP instructions" +msgstr "´íÎó£º%s ʹÓà FPA Ö¸Á¶ø %s ʹÓà VFP Ö¸Áî" + +#: elf32-arm.h:2338 +#, c-format +msgid "ERROR: %s uses software FP, whereas %s uses hardware FP" +msgstr "´íÎó£º%s ʹÓÃÈí¼þ FP£¬¶ø %s ʹÓÃÓ²¼þ FP" + +#: elf32-arm.h:2343 +#, c-format +msgid "ERROR: %s uses hardware FP, whereas %s uses software FP" +msgstr "´íÎó£º%s ʹÓÃÓ²¼þ FP£¬¶ø %s ʹÓÃÈí¼þ FP" + +#. Ignore init flag - it may not be set, despite the flags field +#. containing valid data. +#: elf32-arm.h:2396 elf32-cris.c:2988 elf32-m68k.c:410 elf32-vax.c:543 +#: elfxx-mips.c:7756 +#, c-format +msgid "private flags = %lx:" +msgstr "˽ÓбêÖ¾ = %lx£º" + +#: elf32-arm.h:2405 +msgid " [interworking enabled]" +msgstr " [ÆôÓû¥²Ù×÷]" + +#: elf32-arm.h:2413 +msgid " [VFP float format]" +msgstr " [VFP ¸¡µã¸ñʽ]" + +#: elf32-arm.h:2415 +msgid " [FPA float format]" +msgstr " [FPA ¸¡µã¸ñʽ]" + +#: elf32-arm.h:2424 +msgid " [new ABI]" +msgstr " [РABI]" + +#: elf32-arm.h:2427 +msgid " [old ABI]" +msgstr " [¾É ABI]" + +#: elf32-arm.h:2430 +msgid " [software FP]" +msgstr " [Èí¼þ FP]" + +#: elf32-arm.h:2438 +msgid " [Version1 EABI]" +msgstr " [°æ±¾1 EABI]" + +#: elf32-arm.h:2441 elf32-arm.h:2452 +msgid " [sorted symbol table]" +msgstr " [ÅÅÐò¹ýµÄ·ûºÅ±í]" + +#: elf32-arm.h:2443 elf32-arm.h:2454 +msgid " [unsorted symbol table]" +msgstr " [δÅÅÐòµÄ·ûºÅ±í]" + +#: elf32-arm.h:2449 +msgid " [Version2 EABI]" +msgstr " [°æ±¾2 EABI]" + +#: elf32-arm.h:2457 +msgid " [dynamic symbols use segment index]" +msgstr " [¶¯Ì¬·ûºÅʹÓöÎË÷Òý]" + +#: elf32-arm.h:2460 +msgid " [mapping symbols precede others]" +msgstr "" + +#: elf32-arm.h:2467 +msgid " " +msgstr " <²»¿Éʶ±ðµÄ EABI °æ±¾>" + +#: elf32-arm.h:2474 +msgid " [relocatable executable]" +msgstr " [¿ÉÖØж¨Î»µÄ¿ÉÖ´ÐгÌÐò]" + +#: elf32-arm.h:2477 +msgid " [has entry point]" +msgstr " [º¬ÓÐÈë¿Úµã]" + +#: elf32-arm.h:2482 +msgid "" +msgstr "<ÎÞ·¨Ê¶±ðµÄ±ê־λ¼¯ºÏ>" + +#: elf32-avr.c:841 elf32-cris.c:1411 elf32-fr30.c:643 elf32-frv.c:817 +#: elf32-i860.c:1039 elf32-openrisc.c:447 elf32-v850.c:1699 +#: elf32-xstormy16.c:941 elf64-mmix.c:1310 +msgid "internal error: dangerous relocation" +msgstr "ÄÚ²¿´íÎó£ºÎ£ÏÕµÄÖض¨Î»" + +#: elf32-cris.c:949 +#, c-format +msgid "%s: unresolvable relocation %s against symbol `%s' from %s section" +msgstr "%1$s£ºÀ´×Ô %4$s ½ÚµÄ¹ØÓÚ·ûºÅ¡°%3$s¡±µÄÎÞ·¨½âÎöµÄÖض¨Î» %2$s" + +#: elf32-cris.c:1012 +#, c-format +msgid "%s: No PLT nor GOT for relocation %s against symbol `%s' from %s section" +msgstr "" + +#: elf32-cris.c:1015 elf32-cris.c:1141 +msgid "[whose name is lost]" +msgstr "" + +#: elf32-cris.c:1130 +#, c-format +msgid "%s: relocation %s with non-zero addend %d against local symbol from %s section" +msgstr "" + +#: elf32-cris.c:1137 +#, c-format +msgid "%s: relocation %s with non-zero addend %d against symbol `%s' from %s section" +msgstr "" + +#: elf32-cris.c:1155 +#, c-format +msgid "%s: relocation %s is not allowed for global symbol: `%s' from %s section" +msgstr "" + +#: elf32-cris.c:1170 +#, c-format +msgid "%s: relocation %s in section %s with no GOT created" +msgstr "" + +#: elf32-cris.c:1288 +#, c-format +msgid "%s: Internal inconsistency; no relocation section %s" +msgstr "%s£ºÄÚ²¿²»Ò»Ö£»Ã»ÓÐÖض¨Î»½Ú %s" + +#: elf32-cris.c:2514 +#, c-format +msgid "" +"%s, section %s:\n" +" relocation %s should not be used in a shared object; recompile with -fPIC" +msgstr "" + +#: elf32-cris.c:2991 +msgid " [symbols have a _ prefix]" +msgstr " [·ûºÅÓиö _ ǰ׺]" + +#: elf32-cris.c:3030 +#, c-format +msgid "%s: uses _-prefixed symbols, but writing file with non-prefixed symbols" +msgstr "%s£ºÊ¹Óôø _ ǰ׺µÄ·ûºÅ£¬µ«ÒÔÎÞǰ׺·ûºÅдÈëÎļþ" + +#: elf32-cris.c:3031 +#, c-format +msgid "%s: uses non-prefixed symbols, but writing file with _-prefixed symbols" +msgstr "%s£ºÊ¹ÓÃÎÞǰ׺·ûºÅ£¬µ«ÒÔ´ø _ ǰ׺µÄ·ûºÅдÈëÎļþ" + +#: elf32-frv.c:1217 +#, c-format +msgid "%s: compiled with %s and linked with modules that use non-pic relocations" +msgstr "" + +#: elf32-frv.c:1267 +#, c-format +msgid "%s: compiled with %s and linked with modules compiled with %s" +msgstr "%s£ºÒÔ %s ±àÒ벢ͬÒÔ %s ±àÒëµÄÄ£¿éÁ¬½Ó" + +#: elf32-frv.c:1279 +#, c-format +msgid "%s: uses different unknown e_flags (0x%lx) fields than previous modules (0x%lx)" +msgstr "" + +#: elf32-frv.c:1315 +#, c-format +msgid "private flags = 0x%lx:" +msgstr "˽ÓбêÖ¾ = 0x%lx£º" + +#: elf32-gen.c:82 elf64-gen.c:82 +#, c-format +msgid "%s: Relocations in generic ELF (EM: %d)" +msgstr "" + +#: elf32-hppa.c:671 elf64-ppc.c:2323 +#, c-format +msgid "%s: cannot create stub entry %s" +msgstr "" + +#: elf32-hppa.c:956 elf32-hppa.c:3555 +#, c-format +msgid "%s(%s+0x%lx): cannot reach %s, recompile with -ffunction-sections" +msgstr "" + +#: elf32-hppa.c:1338 elf64-x86-64.c:673 +#, c-format +msgid "%s: relocation %s can not be used when making a shared object; recompile with -fPIC" +msgstr "" + +#: elf32-hppa.c:1358 +#, c-format +msgid "%s: relocation %s should not be used when making a shared object; recompile with -fPIC" +msgstr "" + +#: elf32-hppa.c:1551 +#, c-format +msgid "Could not find relocation section for %s" +msgstr "ÎÞ·¨Îª %s ÕÒµ½Öض¨Î»½Ú" + +#: elf32-hppa.c:2855 +#, c-format +msgid "%s: duplicate export stub %s" +msgstr "" + +#: elf32-hppa.c:3433 +#, c-format +msgid "%s(%s+0x%lx): fixing %s" +msgstr "%s(%s+0x%lx)£ºÕýÔÚÐÞ¸´ %s" + +#: elf32-hppa.c:4080 +#, c-format +msgid "%s(%s+0x%lx): cannot handle %s for %s" +msgstr "" + +#: elf32-hppa.c:4393 +msgid ".got section not immediately after .plt section" +msgstr ".got ½Ú²»Äܽô½ÓÔÚ .plt ½ÚÖ®ºó" + +#: elf32-i386.c:379 +#, c-format +msgid "%s: invalid relocation type %d" +msgstr "%s£ºÎÞЧµÄÖض¨Î»ÀàÐÍ %d" + +#: elf32-i386.c:876 elf32-s390.c:649 elf64-s390.c:595 elf64-x86-64.c:591 +#, c-format +msgid "%s: bad symbol index: %d" +msgstr "%s£º´íÎóµÄ·ûºÅË÷Òý£º%d" + +#: elf32-i386.c:948 +#, c-format +msgid "%s: `%s' accessed both as normal and thread local symbol" +msgstr "" + +#: elf32-i386.c:1072 elf32-s390.c:808 elf64-ppc.c:2827 elf64-s390.c:759 +#: elf64-x86-64.c:761 +#, c-format +msgid "%s: bad relocation section name `%s'" +msgstr "%s£º´íÎóµÄÖض¨Î»½ÚÃû³Æ¡°%s¡±" + +#: elf32-i386.c:1159 elf64-alpha.c:4768 +#, c-format +msgid "%s: TLS local exec code cannot be linked into shared objects" +msgstr "" + +#: elf32-i386.c:2747 elf32-s390.c:1981 elf32-sparc.c:1571 elf64-ppc.c:5918 +#: elf64-s390.c:1945 elf64-sparc.c:2578 elf64-x86-64.c:1948 +#, c-format +msgid "%s(%s+0x%lx): unresolvable relocation against symbol `%s'" +msgstr "" + +#: elf32-i386.c:2784 elf32-s390.c:2019 elf64-ppc.c:5977 elf64-s390.c:1983 +#: elf64-x86-64.c:1986 +#, c-format +msgid "%s(%s+0x%lx): reloc against `%s': error %d" +msgstr "" + +#: elf32-m32r.c:924 +msgid "SDA relocation when _SDA_BASE_ not defined" +msgstr "ÔÚ _SDA_BASE_ 䶨Òåʱ³öÏÖ SDA Öض¨Î»" + +#: elf32-ia64.c:3687 elf32-m32r.c:1013 elf32-ppc.c:2987 elf64-alpha.c:4185 +#: elf64-alpha.c:4313 elf64-ia64.c:3687 +#, c-format +msgid "%s: unknown relocation type %d" +msgstr "%s£ºÎ´ÖªµÄÖض¨Î»ÀàÐÍ %d" + +#: elf32-m32r.c:1221 +#, c-format +msgid "%s: The target (%s) of an %s relocation is in the wrong section (%s)" +msgstr "" + +#: elf32-m32r.c:1947 +#, c-format +msgid "%s: Instruction set mismatch with previous modules" +msgstr "" + +#: elf32-m32r.c:1970 +#, c-format +msgid "private flags = %lx" +msgstr "˽ÓбêÖ¾ = %lx" + +#: elf32-m32r.c:1975 +msgid ": m32r instructions" +msgstr "£ºm32r Ö¸Áî" + +#: elf32-m32r.c:1976 +msgid ": m32rx instructions" +msgstr "£ºm32rx Ö¸Áî" + +#: elf32-m68k.c:413 +msgid " [cpu32]" +msgstr " [cpu32]" + +#: elf32-m68k.c:416 +msgid " [m68000]" +msgstr " [m68000]" + +#: elf32-mcore.c:354 elf32-mcore.c:457 +#, c-format +msgid "%s: Relocation %s (%d) is not currently supported.\n" +msgstr "" + +#: elf32-mcore.c:442 +#, c-format +msgid "%s: Unknown relocation type %d\n" +msgstr "%s£ºÎ´ÖªµÄÖض¨Î»ÀàÐÍ %d\n" + +#: elf32-mips.c:1152 elf64-mips.c:1783 +msgid "32bits gp relative relocation occurs for an external symbol" +msgstr "" + +#: elf32-mips.c:1301 +#, c-format +msgid "Linking mips16 objects into %s format is not supported" +msgstr "½« mips16 Ä¿±êÎļþÁ¬½Óµ½ %s ¸ñʽÊDz»Ö§³ÖµÄ" + +#: elf32-ppc.c:1460 +#, c-format +msgid "%s: compiled with -mrelocatable and linked with modules compiled normally" +msgstr "" + +#: elf32-ppc.c:1468 +#, c-format +msgid "%s: compiled normally and linked with modules compiled with -mrelocatable" +msgstr "" + +#: elf32-ppc.c:1494 elf64-sparc.c:2989 elfxx-mips.c:7713 +#, c-format +msgid "%s: uses different e_flags (0x%lx) fields than previous modules (0x%lx)" +msgstr "" + +#: elf32-ppc.c:1592 +#, c-format +msgid "%s: Unknown special linker type %d" +msgstr "%s£ºÎ´ÖªµÄÌض¨Á¬½ÓÆ÷ÀàÐÍ %d" + +#: elf32-ppc.c:2273 elf32-ppc.c:2307 elf32-ppc.c:2342 +#, c-format +msgid "%s: relocation %s cannot be used when making a shared object" +msgstr "%s£º´´½¨¹²ÏíÄ¿±êÎļþʱ²»ÄÜʹÓÃÖض¨Î» %s" + +#: elf32-ppc.c:3126 elf64-ppc.c:5473 +#, c-format +msgid "%s: unknown relocation type %d for symbol %s" +msgstr "%1$s£º¹ØÓÚ·ûºÅ %3$s µÄδ֪Öض¨Î»ÀàÐÍ %2$d" + +#: elf32-ppc.c:3482 elf32-ppc.c:3503 elf32-ppc.c:3553 +#, c-format +msgid "%s: The target (%s) of a %s relocation is in the wrong output section (%s)" +msgstr "" + +#: elf32-ppc.c:3619 +#, c-format +msgid "%s: Relocation %s is not yet supported for symbol %s." +msgstr "%s£ºÉв»Ö§³Ö¹ØÓÚ·ûºÅ %s µÄÖض¨Î» %s¡£" + +#: elf32-sh.c:1964 +#, c-format +msgid "%s: 0x%lx: warning: bad R_SH_USES offset" +msgstr "%s£º0x%lx£º¾¯¸æ£º´íÎóµÄ R_SH_USES Æ«ÒÆÁ¿" + +#: elf32-sh.c:1976 +#, c-format +msgid "%s: 0x%lx: warning: R_SH_USES points to unrecognized insn 0x%x" +msgstr "%s£º0x%lx£º¾¯¸æ£ºR_SH_USES Ö¸ÏòÎÞ·¨Ê¶±ðµÄÖ¸Áî 0x%x" + +#: elf32-sh.c:1993 +#, c-format +msgid "%s: 0x%lx: warning: bad R_SH_USES load offset" +msgstr "%s£º0x%lx£º¾¯¸æ£º´íÎóµÄ R_SH_USES ×°ÈëÆ«ÒÆÁ¿" + +#: elf32-sh.c:2008 +#, c-format +msgid "%s: 0x%lx: warning: could not find expected reloc" +msgstr "%s£º0x%lx£º¾¯¸æ£ºÎÞ·¨ÕÒµ½Ô¤ÆÚµÄÖض¨Î»" + +#: elf32-sh.c:2036 +#, c-format +msgid "%s: 0x%lx: warning: symbol in unexpected section" +msgstr "%s£º0x%lx£º¾¯¸æ£ºÒâÍâ½ÚÖгöÏÖ·ûºÅ" + +#: elf32-sh.c:2153 +#, c-format +msgid "%s: 0x%lx: warning: could not find expected COUNT reloc" +msgstr "%s£º0x%lx£º¾¯¸æ£ºÎÞ·¨ÕÒµ½Ô¤ÆÚµÄ COUNT Öض¨Î»" + +#: elf32-sh.c:2162 +#, c-format +msgid "%s: 0x%lx: warning: bad count" +msgstr "%s£º0x%lx£º¾¯¸æ£º´íÎó¼ÆÊý" + +#: elf32-sh.c:2550 elf32-sh.c:2926 +#, c-format +msgid "%s: 0x%lx: fatal: reloc overflow while relaxing" +msgstr "" + +#: elf32-sh.c:4073 elf64-sh64.c:1576 +msgid "Unexpected STO_SH5_ISA32 on local symbol is not handled" +msgstr "" + +#: elf32-sh.c:4284 +#, c-format +msgid "%s: 0x%lx: fatal: unaligned branch target for relax-support relocation" +msgstr "" + +#: elf32-sh64.c:203 elf64-sh64.c:2364 +#, c-format +msgid "%s: compiled as 32-bit object and %s is 64-bit" +msgstr "%s£º±àÒëΪ 32-λĿ±êÎļþµ« %s ÊÇ 64-λµÄ" + +#: elf32-sh64.c:206 elf64-sh64.c:2367 +#, c-format +msgid "%s: compiled as 64-bit object and %s is 32-bit" +msgstr "%s£º±àÒëΪ 64-λĿ±êÎļþµ« %s ÊÇ 32-λµÄ" + +#: elf32-sh64.c:208 elf64-sh64.c:2369 +#, c-format +msgid "%s: object size does not match that of target %s" +msgstr "%s£ºÄ¿±êÎļþ´óСºÍÄ¿±ê %s ²»Æ¥Åä" + +#: elf32-sh64.c:440 elf64-sh64.c:2941 +#, c-format +msgid "%s: encountered datalabel symbol in input" +msgstr "%s£ºÔÚÊäÈëÖÐÓöµ½Êý¾Ý±êÇ©·ûºÅ" + +#: elf32-sh64.c:523 +msgid "PTB mismatch: a SHmedia address (bit 0 == 1)" +msgstr "PTB ²»Æ¥Å䣺SHmedia µØÖ· (λ 0 == 1)" + +#: elf32-sh64.c:526 +msgid "PTA mismatch: a SHcompact address (bit 0 == 0)" +msgstr "PTA ²»Æ¥Å䣺SHcompact µØÖ· (λ 0 == 0)" + +#: elf32-sh64.c:544 +#, c-format +msgid "%s: GAS error: unexpected PTB insn with R_SH_PT_16" +msgstr "%s£ºGAS ´íÎó£ºÒâÍâµÄ´øÓÐ R_SH_PT_16 µÄ PTB Ö¸Áî" + +#: elf32-sh64.c:593 elf64-sh64.c:1703 +#, c-format +msgid "%s: error: unaligned relocation type %d at %08x reloc %08x\n" +msgstr "" + +#: elf32-sh64.c:677 +#, c-format +msgid "%s: could not write out added .cranges entries" +msgstr "%s£ºÎÞ·¨Ð´³ö .cranges ÌõÄ¿" + +#: elf32-sh64.c:739 +#, c-format +msgid "%s: could not write out sorted .cranges entries" +msgstr "%s£ºÎÞ·¨Ð´³ö¾­ÅÅÐòµÄ .cranges ÌõÄ¿" + +#: elf32-sparc.c:1535 elf64-sparc.c:2224 +#, c-format +msgid "%s: probably compiled without -fPIC?" +msgstr "" + +#: elf32-sparc.c:2002 +#, c-format +msgid "%s: compiled for a 64 bit system and target is 32 bit" +msgstr "%s£ºÎª 64 λϵͳ±àÒ뵫Ŀ±êƽ̨ÊÇ 32 λµÄ" + +#: elf32-sparc.c:2016 +#, c-format +msgid "%s: linking little endian files with big endian files" +msgstr "%s£ºÁ¬½ÓС¶ËÎļþºÍ´ó¶ËÎļþ" + +#: elf32-v850.c:682 +#, c-format +msgid "Variable `%s' cannot occupy in multiple small data regions" +msgstr "±äÁ¿¡°%s¡±²»ÄÜÕ¼¾Ý¶à¸öСÊý¾ÝÇø" + +#: elf32-v850.c:685 +#, c-format +msgid "Variable `%s' can only be in one of the small, zero, and tiny data regions" +msgstr "±äÁ¿¡°%s¡±Ö»ÄܳöÏÖÔÚСÊý¾ÝÇø¡¢ÁãÊý¾ÝÇø¡¢Î¢Êý¾ÝÇøÖ®Ò»" + +#: elf32-v850.c:688 +#, c-format +msgid "Variable `%s' cannot be in both small and zero data regions simultaneously" +msgstr "±äÁ¿¡°%s¡±²»ÄÜͬʱ³öÏÖÔÚСÊý¾ÝÇøºÍÁãÊý¾ÝÇø" + +#: elf32-v850.c:691 +#, c-format +msgid "Variable `%s' cannot be in both small and tiny data regions simultaneously" +msgstr "±äÁ¿¡°%s¡±²»ÄÜͬʱ³öÏÖÔÚСÊý¾ÝÇøºÍ΢Êý¾ÝÇø" + +#: elf32-v850.c:694 +#, c-format +msgid "Variable `%s' cannot be in both zero and tiny data regions simultaneously" +msgstr "±äÁ¿¡°%s¡±²»ÄÜͬʱ³öÏÖÔÚÁãÊý¾ÝÇøºÍ΢Êý¾ÝÇø" + +#: elf32-v850.c:1072 +msgid "FAILED to find previous HI16 reloc\n" +msgstr "Ñ°ÕÒÉÏÒ»¸ö HI16 Öض¨Î»Ê§°Ü\n" + +#: elf32-v850.c:1703 +msgid "could not locate special linker symbol __gp" +msgstr "ÎÞ·¨¶¨Î»ÌØÊâÁ¬½ÓÆ÷·ûºÅ __gp" + +#: elf32-v850.c:1707 +msgid "could not locate special linker symbol __ep" +msgstr "ÎÞ·¨¶¨Î»ÌØÊâÁ¬½ÓÆ÷·ûºÅ __ep" + +#: elf32-v850.c:1711 +msgid "could not locate special linker symbol __ctbp" +msgstr "ÎÞ·¨¶¨Î»ÌØÊâÁª»úÆ÷·ûºÅ __ctbp" + +#: elf32-v850.c:1875 +#, c-format +msgid "%s: Architecture mismatch with previous modules" +msgstr "%s£ºÌåϵ½á¹¹Í¬Ç°Ò»¸öÄ£¿é²»Æ¥Åä" + +#: elf32-v850.c:1895 +#, c-format +msgid "private flags = %lx: " +msgstr "˽ÓбêÖ¾ = %lx£º" + +#: elf32-v850.c:1900 +msgid "v850 architecture" +msgstr "v850 Ìåϵ½á¹¹" + +#: elf32-v850.c:1901 +msgid "v850e architecture" +msgstr "v850e Ìåϵ½á¹¹" + +#: elf32-v850.c:1902 +msgid "v850ea architecture" +msgstr "v850ea Ìåϵ½á¹¹" + +#: elf32-vax.c:546 +msgid " [nonpic]" +msgstr "" + +#: elf32-vax.c:549 +msgid " [d-float]" +msgstr "" + +#: elf32-vax.c:552 +msgid " [g-float]" +msgstr "" + +#: elf32-vax.c:674 +#, c-format +msgid "%s: warning: GOT addend of %ld to `%s' does not match previous GOT addend of %ld" +msgstr "" + +#: elf32-vax.c:1679 +#, c-format +msgid "%s: warning: PLT addend of %d to `%s' from %s section ignored" +msgstr "" + +#: elf32-vax.c:1814 +#, c-format +msgid "%s: warning: %s relocation against symbol `%s' from %s section" +msgstr "" + +#: elf32-vax.c:1820 +#, c-format +msgid "%s: warning: %s relocation to 0x%x from %s section" +msgstr "" + +#: elf32-ia64.c:2280 elf32-xstormy16.c:414 elf64-ia64.c:2280 +msgid "non-zero addend in @fptr reloc" +msgstr "" + +#: elf64-alpha.c:1097 +msgid "GPDISP relocation did not find ldah and lda instructions" +msgstr "GPDISP Öض¨Î»ÎÞ·¨ÕÒµ½ ldah ºÍ lda Ö¸Áî" + +#: elf64-alpha.c:3675 +#, c-format +msgid "%s: .got subsegment exceeds 64K (size %d)" +msgstr "%s£º.got ×Ó½Ú³¬¹ýÁË 64K (´óС %d)" + +#: elf64-alpha.c:4498 elf64-alpha.c:4510 +#, c-format +msgid "%s: gp-relative relocation against dynamic symbol %s" +msgstr "" + +#: elf64-alpha.c:4536 elf64-alpha.c:4676 +#, c-format +msgid "%s: pc-relative relocation against dynamic symbol %s" +msgstr "" + +#: elf64-alpha.c:4564 +#, c-format +msgid "%s: change in gp: BRSGP %s" +msgstr "" + +#: elf64-alpha.c:4589 +msgid "" +msgstr "<δ֪>" + +#: elf64-alpha.c:4594 +#, c-format +msgid "%s: !samegp reloc against symbol without .prologue: %s" +msgstr "" + +#: elf64-alpha.c:4639 +#, c-format +msgid "%s: unhandled dynamic relocation against %s" +msgstr "%s£ºÎ´´¦ÀíµÄ¹ØÓÚ %s µÄ¶¯Ì¬Öض¨Î»" + +#: elf64-alpha.c:4752 +#, c-format +msgid "%s: dtp-relative relocation against dynamic symbol %s" +msgstr "" + +#: elf64-alpha.c:4775 +#, c-format +msgid "%s: tp-relative relocation against dynamic symbol %s" +msgstr "" + +#: elf64-hppa.c:2080 +#, c-format +msgid "stub entry for %s cannot load .plt, dp offset = %ld" +msgstr "" + +#: elf64-mmix.c:1002 +#, c-format +msgid "" +"%s: Internal inconsistency error for value for\n" +" linker-allocated global register: linked: 0x%lx%08lx != relaxed: 0x%lx%08lx\n" +msgstr "" + +#: elf64-mmix.c:1386 +#, c-format +msgid "%s: base-plus-offset relocation against register symbol: (unknown) in %s" +msgstr "" + +#: elf64-mmix.c:1391 +#, c-format +msgid "%s: base-plus-offset relocation against register symbol: %s in %s" +msgstr "" + +#: elf64-mmix.c:1435 +#, c-format +msgid "%s: register relocation against non-register symbol: (unknown) in %s" +msgstr "" + +#: elf64-mmix.c:1440 +#, c-format +msgid "%s: register relocation against non-register symbol: %s in %s" +msgstr "" + +#: elf64-mmix.c:1477 +#, c-format +msgid "%s: directive LOCAL valid only with a register or absolute value" +msgstr "%s£ºÖ¸Áî LOCAL Ö»¶Ô¼Ä´æÆ÷»ò¾ø¶ÔÖµÓÐЧ" + +#: elf64-mmix.c:1505 +#, c-format +msgid "%s: LOCAL directive: Register $%ld is not a local register. First global register is $%ld." +msgstr "%s£ºLOCAL Ö¸Á¼Ä´æÆ÷ $%ld ²»ÊDZ¾µØ¼Ä´æÆ÷¡£ µÚÒ»¸öÈ«¾Ö¼Ä´æÆ÷ÊÇ $%ld¡£" + +#: elf64-mmix.c:1965 +#, c-format +msgid "%s: Error: multiple definition of `%s'; start of %s is set in a earlier linked file\n" +msgstr "%s£º´íÎó£ºÖظ´¶¨Òå¡°%s¡±£»%s µÄÆðµãÔÚ´ËÇ°Á¬½ÓµÄÎļþÖÐÒÑÉ趨\n" + +#: elf64-mmix.c:2024 +msgid "Register section has contents\n" +msgstr "¼Ä´æÆ÷½ÚÓÐÄÚÈÝ\n" + +#: elf64-mmix.c:2186 +#, c-format +msgid "" +"Internal inconsistency: remaining %u != max %u.\n" +" Please report this bug." +msgstr "" +"ÄÚ²¿²»Ò»Ö£ºÊ£Óà %u != ×î´ó %u¡£\n" +" Ç뱨¸æ¸Ã bug¡£" + +#: elf64-ppc.c:1669 libbfd.c:1435 +#, c-format +msgid "%s: compiled for a big endian system and target is little endian" +msgstr "%s£ºÎª´ó¶Ëϵͳ±àÒ뵫Ŀ±êƽ̨ÊÇС¶ËµÄ" + +#: elf64-ppc.c:1671 libbfd.c:1437 +#, c-format +msgid "%s: compiled for a little endian system and target is big endian" +msgstr "%s£ºÎªÐ¡¶Ëϵͳ±àÒ뵫Ŀ±êƽ̨ÊÇ´ó¶ËµÄ" + +#: elf64-ppc.c:3610 +#, c-format +msgid "%s: unexpected reloc type %u in .opd section" +msgstr "%s£º.opd ½ÚÖÐÒâÍâµÄÖض¨Î»ÀàÐÍ %u" + +#: elf64-ppc.c:3630 +#, c-format +msgid "%s: .opd is not a regular array of opd entries" +msgstr "%s£º.opd ²»ÊÇ opd ÌõÄ¿µÄÆÕͨÊý×é" + +#: elf64-ppc.c:3672 +#, c-format +msgid "%s: undefined sym `%s' in .opd section" +msgstr "%s£º.opd ½ÚÖÐ䶨ÒåµÄ¡°%s¡±" + +#: elf64-ppc.c:4397 +#, c-format +msgid "can't find branch stub `%s'" +msgstr "" + +#: elf64-ppc.c:4436 elf64-ppc.c:4501 +#, c-format +msgid "linkage table error against `%s'" +msgstr "" + +#: elf64-ppc.c:4573 +#, c-format +msgid "can't build branch stub `%s'" +msgstr "" + +#: elf64-ppc.c:5179 +msgid "stubs don't match calculated size" +msgstr "" + +#: elf64-ppc.c:5828 +#, c-format +msgid "%s: Relocation %s is not supported for symbol %s." +msgstr "%s£ºÖض¨Î» %s ²»Ö§³Ö·ûºÅ %s¡£" + +#: elf64-ppc.c:5872 +#, c-format +msgid "%s: error: relocation %s not a multiple of 4" +msgstr "%s£º´íÎó£ºÖض¨Î» %s ²»ÊÇ 4 µÄ±¶Êý" + +#: elf64-sparc.c:1280 +#, c-format +msgid "%s: check_relocs: unhandled reloc type %d" +msgstr "%s£ºcheck_relocs£ºÎ´´¦ÀíµÄÖض¨Î»ÀàÐÍ %d" + +#: elf64-sparc.c:1317 +#, c-format +msgid "%s: Only registers %%g[2367] can be declared using STT_REGISTER" +msgstr "%s£ºÖ»ÓмĴæÆ÷ %%g[2367] ¿ÉÒÔÓà STT_REGISTER À´ÉùÃ÷" + +#: elf64-sparc.c:1337 +#, c-format +msgid "Register %%g%d used incompatibly: %s in %s, previously %s in %s" +msgstr "²»¼æÈݵØʹÓüĴæÆ÷ %%g%1$d£ºÔÚ %3$s ÖÐΪ %2$s£¬ÔÚÇ°ÃæµÄ %5$s ÖÐΪ %4$s" + +#: elf64-sparc.c:1360 +#, c-format +msgid "Symbol `%s' has differing types: REGISTER in %s, previously %s in %s" +msgstr "·ûºÅ¡°%1$s¡±µÄÀàÐͲ»Í¬£º%2$s ÖÐΪ¼Ä´æÆ÷£¬ÔÚÇ°ÃæµÄ %4$s ÖÐΪ %3$s" + +#: elf64-sparc.c:1406 +#, c-format +msgid "Symbol `%s' has differing types: %s in %s, previously REGISTER in %s" +msgstr "" + +#: elf64-sparc.c:2970 +#, c-format +msgid "%s: linking UltraSPARC specific with HAL specific code" +msgstr "" + +#: elfcode.h:1198 +#, c-format +msgid "%s: version count (%ld) does not match symbol count (%ld)" +msgstr "%s£º°æ±¾¼ÆÊý (%ld) ÎÞ·¨Æ¥Åä·ûºÅ¼ÆÊý (%ld)" + +#: elflink.c:440 +#, c-format +msgid "%s: Section %s is too large to add hole of %ld bytes" +msgstr "" + +#: elflink.h:1090 +#, c-format +msgid "%s: warning: unexpected redefinition of `%s'" +msgstr "%s£º¾¯¸æ£ºÒâÍâµÄÖØж¨Òå¡°%s¡±" + +#: elflink.h:1727 +#, c-format +msgid "%s: %s: invalid version %u (max %d)" +msgstr "%s£º%s£ºÎÞЧµÄ°æ±¾ %u (×î´ó %d)" + +#: elflink.h:1768 +#, c-format +msgid "%s: %s: invalid needed version %d" +msgstr "%s£º%s£ºÎÞЧµÄ±Ø±¸°æ±¾ %d" + +#: elflink.h:1890 +#, c-format +msgid "Warning: size of symbol `%s' changed from %lu to %lu in %s" +msgstr "¾¯¸æ£º%4$s ÖеķûºÅ¡°%1$s¡±µÄ´óСÓÉ %2$lu ±äΪ %3$lu" + +#: elflink.h:3174 +#, c-format +msgid "%s: .preinit_array section is not allowed in DSO" +msgstr "%s£ºDSO Öв»ÔÊÐí³öÏÖ .preinit_array ½Ú" + +#: elflink.h:4030 +#, c-format +msgid "warning: type and size of dynamic symbol `%s' are not defined" +msgstr "¾¯¸æ£º¶¯Ì¬·ûºÅ¡°%s¡±µÄÀàÐͺʹóС䶨Òå" + +#: elflink.h:4345 +#, c-format +msgid "%s: undefined versioned symbol name %s" +msgstr "%s£ºÎ´¶¨ÒåµÄÓа汾·ûºÅÃû %s" + +#: elflink.h:4611 elflink.h:4619 elflink.h:6508 elflink.h:7600 +msgid "Error: out of memory" +msgstr "´íÎó£ºÃ»ÓÐÄÚ´æ" + +#: elflink.h:4781 +msgid "Not enough memory to sort relocations" +msgstr "ûÓÐ×ã¹»µÄÄÚ´æ½øÐÐÖض¨Î»ÅÅÐò" + +#: elflink.h:5682 elflink.h:5725 +#, c-format +msgid "%s: could not find output section %s" +msgstr "%s£ºÎÞ·¨ÕÒµ½Êä³ö½Ú %s" + +#: elflink.h:5688 +#, c-format +msgid "warning: %s section has zero size" +msgstr "¾¯¸æ£º%s ½ÚµÄ´óСΪÁã" + +#: elflink.h:6275 +#, c-format +msgid "%s: could not find output section %s for input section %s" +msgstr "%1$s£ºÎÞ·¨ÎªÊäÈë½Ú %3$s ÕÒµ½Êä³ö½Ú %2$s" + +#: elflink.h:6486 +#, c-format +msgid "%s: relocation size mismatch in %s section %s" +msgstr "" + +#: elflink.h:6849 +msgid "warning: relocation against removed section; zeroing" +msgstr "¾¯¸æ£º¹ØÓÚÒÑɾ³ýµÄ½ÚµÄÖض¨Î»£»ÕýÔÚÇåÁã" + +#: elflink.h:6879 +msgid "warning: relocation against removed section" +msgstr "¾¯¸æ£º¹ØÓÚÒÑɾ³ýµÄ½ÚµÄÖض¨Î»" + +#: elflink.h:6892 +#, c-format +msgid "local symbols in discarded section %s" +msgstr "ÒѽûÓÃµÄ½Ú %s Öеı¾µØ·ûºÅ" + +#: elfxx-mips.c:734 +msgid "static procedure (no name)" +msgstr "¾²Ì¬¹ý³Ì (ÎÞÃû³Æ)" + +#: elfxx-mips.c:1601 +msgid "not enough GOT space for local GOT entries" +msgstr "ûÓÐ×ã¹»µÄ GOT ¿Õ¼äÓÃÓÚ GOT ÌõÄ¿" + +#: elfxx-mips.c:2750 +#, c-format +msgid "%s: %s+0x%lx: jump to stub routine which is not jal" +msgstr "" + +#: elfxx-mips.c:4270 +#, c-format +msgid "%s: Malformed reloc detected for section %s" +msgstr "" + +#: elfxx-mips.c:4348 +#, c-format +msgid "%s: CALL16 reloc at 0x%lx not against global symbol" +msgstr "" + +#: elfxx-mips.c:7301 +#, c-format +msgid "%s: illegal section name `%s'" +msgstr "%s£º·Ç·¨µÄ½ÚÃû¡°%s¡±" + +#: elfxx-mips.c:7615 +#, c-format +msgid "%s: linking PIC files with non-PIC files" +msgstr "%s£º½« PIC Îļþͬ·Ç-PIC ÎļþÁ¬½Ó" + +#: elfxx-mips.c:7625 +#, c-format +msgid "%s: linking abicalls files with non-abicalls files" +msgstr "" + +#: elfxx-mips.c:7654 +#, c-format +msgid "%s: ISA mismatch (-mips%d) with previous modules (-mips%d)" +msgstr "%s£ºISA (-mips%d) ͬǰÃæµÄÄ£¿é(-mips%d)²»Æ¥Åä" + +#: elfxx-mips.c:7676 +#, c-format +msgid "%s: ISA mismatch (%d) with previous modules (%d)" +msgstr "%s£ºISA (%d) ͬǰÃæµÄÄ£¿é (%d) ²»Æ¥Åä" + +#: elfxx-mips.c:7699 +#, c-format +msgid "%s: ABI mismatch: linking %s module with previous %s modules" +msgstr "%s£ºABI ²»Æ¥Å䣺ÕýÔÚ½«Ä£¿é %s ͬǰһ¸öÄ£¿é %s ½øÐÐÁ¬½Ó" + +#: elfxx-mips.c:7759 +msgid " [abi=O32]" +msgstr " [abi=O32]" + +#: elfxx-mips.c:7761 +msgid " [abi=O64]" +msgstr " [abi=O64]" + +#: elfxx-mips.c:7763 +msgid " [abi=EABI32]" +msgstr " [abi=EABI32]" + +#: elfxx-mips.c:7765 +msgid " [abi=EABI64]" +msgstr " [abi=EABI64]" + +#: elfxx-mips.c:7767 +msgid " [abi unknown]" +msgstr " [abi δ֪]" + +#: elfxx-mips.c:7769 +msgid " [abi=N32]" +msgstr " [abi=N32]" + +#: elfxx-mips.c:7771 +msgid " [abi=64]" +msgstr " [abi=64]" + +#: elfxx-mips.c:7773 +msgid " [no abi set]" +msgstr "" + +#: elfxx-mips.c:7776 +msgid " [mips1]" +msgstr " [mips1]" + +#: elfxx-mips.c:7778 +msgid " [mips2]" +msgstr " [mips2]" + +#: elfxx-mips.c:7780 +msgid " [mips3]" +msgstr " [mips3]" + +#: elfxx-mips.c:7782 +msgid " [mips4]" +msgstr " [mips4]" + +#: elfxx-mips.c:7784 +msgid " [mips5]" +msgstr " [mips5]" + +#: elfxx-mips.c:7786 +msgid " [mips32]" +msgstr " [mips32]" + +#: elfxx-mips.c:7788 +msgid " [mips64]" +msgstr " [mips64]" + +#: elfxx-mips.c:7790 +msgid " [unknown ISA]" +msgstr " [δ֪µÄ ISA]" + +#: elfxx-mips.c:7793 +msgid " [mdmx]" +msgstr " [mdmx]" + +#: elfxx-mips.c:7796 +msgid " [mips16]" +msgstr " [mips16]" + +#: elfxx-mips.c:7799 +msgid " [32bitmode]" +msgstr " [32λģʽ]" + +#: elfxx-mips.c:7801 +msgid " [not 32bitmode]" +msgstr " [·Ç 32λģʽ]" + +#: i386linux.c:458 m68klinux.c:462 sparclinux.c:459 +#, c-format +msgid "Output file requires shared library `%s'\n" +msgstr "Êä³öÎļþÐèÒª¹²Ïí¿â¡°%s¡±\n" + +#: i386linux.c:466 m68klinux.c:470 sparclinux.c:467 +#, c-format +msgid "Output file requires shared library `%s.so.%s'\n" +msgstr "Êä³öÎļþÐèÒª¹²Ïí¿â¡°%s.so.%s¡±\n" + +#: i386linux.c:655 i386linux.c:705 m68klinux.c:662 m68klinux.c:710 +#: sparclinux.c:657 sparclinux.c:707 +#, c-format +msgid "Symbol %s not defined for fixups\n" +msgstr "" + +#: i386linux.c:729 m68klinux.c:734 sparclinux.c:731 +msgid "Warning: fixup count mismatch\n" +msgstr "" + +#: ieee.c:235 +#, c-format +msgid "%s: string too long (%d chars, max 65535)" +msgstr "%s£º×Ö·û´®¹ý³¤ (%d ×Ö·û£¬×î´ó 65535)" + +#: ieee.c:365 +#, c-format +msgid "%s: unrecognized symbol `%s' flags 0x%x" +msgstr "%s£ºÎÞ·¨Ê¶±ðµÄ¡°%s¡±±êÖ¾ 0x%x" + +#: ieee.c:877 +#, c-format +msgid "%s: unimplemented ATI record %u for symbol %u" +msgstr "" + +#: ieee.c:902 +#, c-format +msgid "%s: unexpected ATN type %d in external part" +msgstr "" + +#: ieee.c:924 +#, c-format +msgid "%s: unexpected type after ATN" +msgstr "%s£ºATN Ö®ºó³öÏÖÒâÍâµÄÀàÐÍ" + +#: ihex.c:258 +#, c-format +msgid "%s:%d: unexpected character `%s' in Intel Hex file\n" +msgstr "%s£º%d£ºIntel Ê®Áù½øÖÆÎļþÖеÄÒâÍâ×Ö·û¡°%s\n" + +#: ihex.c:366 +#, c-format +msgid "%s:%u: bad checksum in Intel Hex file (expected %u, found %u)" +msgstr "%s£º%u£ºIntel Ê®Áù½øÖÆÎļþÖеÄУÑéºÍ´íÎó (ӦΪ %u¡¢ÊµÎª %u)" + +#: ihex.c:420 +#, c-format +msgid "%s:%u: bad extended address record length in Intel Hex file" +msgstr "" + +#: ihex.c:437 +#, c-format +msgid "%s:%u: bad extended start address length in Intel Hex file" +msgstr "" + +#: ihex.c:454 +#, c-format +msgid "%s:%u: bad extended linear address record length in Intel Hex file" +msgstr "" + +#: ihex.c:471 +#, c-format +msgid "%s:%u: bad extended linear start address length in Intel Hex file" +msgstr "" + +#: ihex.c:488 +#, c-format +msgid "%s:%u: unrecognized ihex type %u in Intel Hex file\n" +msgstr "" + +#: ihex.c:607 +#, c-format +msgid "%s: internal error in ihex_read_section" +msgstr "" + +#: ihex.c:642 +#, c-format +msgid "%s: bad section length in ihex_read_section" +msgstr "" + +#: ihex.c:860 +#, c-format +msgid "%s: address 0x%s out of range for Intel Hex file" +msgstr "" + +#: libbfd.c:492 +#, c-format +msgid "not mapping: data=%lx mapped=%d\n" +msgstr "" + +#: libbfd.c:495 +msgid "not mapping: env var not set\n" +msgstr "" + +#: libbfd.c:1466 +#, c-format +msgid "Deprecated %s called at %s line %d in %s\n" +msgstr "" + +#: libbfd.c:1469 +#, c-format +msgid "Deprecated %s called\n" +msgstr "" + +#: linker.c:1873 +#, c-format +msgid "%s: indirect symbol `%s' to `%s' is a loop" +msgstr "" + +#: linker.c:2776 +#, c-format +msgid "Attempt to do relocateable link with %s input and %s output" +msgstr "" + +#: merge.c:892 +#, c-format +msgid "%s: access beyond end of merged section (%ld + %ld)" +msgstr "" + +#: mmo.c:460 +#, c-format +msgid "%s: No core to allocate section name %s\n" +msgstr "" + +#: mmo.c:536 +#, c-format +msgid "%s: No core to allocate a symbol %d bytes long\n" +msgstr "" + +#: mmo.c:1245 +#, c-format +msgid "%s: invalid mmo file: initialization value for $255 is not `Main'\n" +msgstr "" + +#: mmo.c:1391 +#, c-format +msgid "%s: unsupported wide character sequence 0x%02X 0x%02X after symbol name starting with `%s'\n" +msgstr "" + +#: mmo.c:1633 +#, c-format +msgid "%s: invalid mmo file: unsupported lopcode `%d'\n" +msgstr "" + +#: mmo.c:1643 +#, c-format +msgid "%s: invalid mmo file: expected YZ = 1 got YZ = %d for lop_quote\n" +msgstr "" + +#: mmo.c:1679 +#, c-format +msgid "%s: invalid mmo file: expected z = 1 or z = 2, got z = %d for lop_loc\n" +msgstr "" + +#: mmo.c:1725 +#, c-format +msgid "%s: invalid mmo file: expected z = 1 or z = 2, got z = %d for lop_fixo\n" +msgstr "" + +#: mmo.c:1764 +#, c-format +msgid "%s: invalid mmo file: expected y = 0, got y = %d for lop_fixrx\n" +msgstr "" + +#: mmo.c:1773 +#, c-format +msgid "%s: invalid mmo file: expected z = 16 or z = 24, got z = %d for lop_fixrx\n" +msgstr "" + +#: mmo.c:1796 +#, c-format +msgid "%s: invalid mmo file: leading byte of operand word must be 0 or 1, got %d for lop_fixrx\n" +msgstr "" + +#: mmo.c:1819 +#, c-format +msgid "%s: cannot allocate file name for file number %d, %d bytes\n" +msgstr "" + +#: mmo.c:1839 +#, c-format +msgid "%s: invalid mmo file: file number %d `%s', was already entered as `%s'\n" +msgstr "" + +#: mmo.c:1852 +#, c-format +msgid "%s: invalid mmo file: file name for number %d was not specified before use\n" +msgstr "" + +#: mmo.c:1958 +#, c-format +msgid "%s: invalid mmo file: fields y and z of lop_stab non-zero, y: %d, z: %d\n" +msgstr "" + +#: mmo.c:1994 +#, c-format +msgid "%s: invalid mmo file: lop_end not last item in file\n" +msgstr "" + +#: mmo.c:2007 +#, c-format +msgid "%s: invalid mmo file: YZ of lop_end (%ld) not equal to the number of tetras to the preceding lop_stab (%ld)\n" +msgstr "" + +#: mmo.c:2670 +#, c-format +msgid "%s: invalid symbol table: duplicate symbol `%s'\n" +msgstr "" + +#: mmo.c:2921 +#, c-format +msgid "%s: Bad symbol definition: `Main' set to %s rather than the start address %s\n" +msgstr "" + +#: mmo.c:3011 +#, c-format +msgid "%s: warning: symbol table too large for mmo, larger than 65535 32-bit words: %d. Only `Main' will be emitted.\n" +msgstr "" + +#: mmo.c:3056 +#, c-format +msgid "%s: internal error, symbol table changed size from %d to %d words\n" +msgstr "" + +#: mmo.c:3111 +#, c-format +msgid "%s: internal error, internal register section %s had contents\n" +msgstr "" + +#: mmo.c:3163 +#, c-format +msgid "%s: no initialized registers; section length 0\n" +msgstr "" + +#: mmo.c:3169 +#, c-format +msgid "%s: too many initialized registers; section length %ld\n" +msgstr "" + +#: mmo.c:3174 +#, c-format +msgid "%s: invalid start address for initialized registers of length %ld: 0x%lx%08lx\n" +msgstr "" + +#: oasys.c:1029 +#, c-format +msgid "%s: can not represent section `%s' in oasys" +msgstr "" + +#: osf-core.c:132 +#, c-format +msgid "Unhandled OSF/1 core file section type %d\n" +msgstr "" + +#: pe-mips.c:658 +#, c-format +msgid "%s: `ld -r' not supported with PE MIPS objects\n" +msgstr "" + +#. OK, at this point the following variables are set up: +#. src = VMA of the memory we're fixing up +#. mem = pointer to memory we're fixing up +#. val = VMA of what we need to refer to +#. +#: pe-mips.c:794 +#, c-format +msgid "%s: unimplemented %s\n" +msgstr "%s£ºÎ´ÊµÏÖµÄ %s\n" + +#: pe-mips.c:820 +#, c-format +msgid "%s: jump too far away\n" +msgstr "%s£ºÌøת¹ýÔ¶\n" + +#: pe-mips.c:847 +#, c-format +msgid "%s: bad pair/reflo after refhi\n" +msgstr "" + +#. XXX code yet to be written. +#: peicode.h:785 +#, c-format +msgid "%s: Unhandled import type; %x" +msgstr "%s£ºÎ´´¦ÀíµÄµ¼ÈëÀàÐÍ£»%x" + +#: peicode.h:790 +#, c-format +msgid "%s: Unrecognised import type; %x" +msgstr "%s£ºÎ´Ê¶±ðµÄµ¼ÈëÀàÐÍ£»%x" + +#: peicode.h:804 +#, c-format +msgid "%s: Unrecognised import name type; %x" +msgstr "%s£ºÎ´Ê¶±ðµÄµ¼ÈëÃû×ÖÀàÐÍ£»%x" + +#: peicode.h:1162 +#, c-format +msgid "%s: Unrecognised machine type (0x%x) in Import Library Format archive" +msgstr "" + +#: peicode.h:1174 +#, c-format +msgid "%s: Recognised but unhandled machine type (0x%x) in Import Library Format archive" +msgstr "" + +#: peicode.h:1191 +#, c-format +msgid "%s: size field is zero in Import Library Format header" +msgstr "" + +#: peicode.h:1219 +#, c-format +msgid "%s: string not null terminated in ILF object file." +msgstr "" + +#: ppcboot.c:416 +msgid "" +"\n" +"ppcboot header:\n" +msgstr "" + +#: ppcboot.c:417 +#, c-format +msgid "Entry offset = 0x%.8lx (%ld)\n" +msgstr "ÌõÄ¿Æ«ÒÆÁ¿ = 0x%.8lx (%ld)\n" + +#: ppcboot.c:418 +#, c-format +msgid "Length = 0x%.8lx (%ld)\n" +msgstr "³¤¶È = 0x%.8lx (%ld)\n" + +#: ppcboot.c:421 +#, c-format +msgid "Flag field = 0x%.2x\n" +msgstr "±êÖ¾Óò = 0x%.2x\n" + +#: ppcboot.c:427 +#, c-format +msgid "Partition name = \"%s\"\n" +msgstr "·ÖÇøÃû = \"%s\"\n" + +#: ppcboot.c:446 +#, c-format +msgid "" +"\n" +"Partition[%d] start = { 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x }\n" +msgstr "" +"\n" +"·ÖÇø[%d] Æðµã = { 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x }\n" + +#: ppcboot.c:452 +#, c-format +msgid "Partition[%d] end = { 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x }\n" +msgstr "·ÖÇø[%d] ÖÕµã = { 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x }\n" + +#: ppcboot.c:458 +#, c-format +msgid "Partition[%d] sector = 0x%.8lx (%ld)\n" +msgstr "·ÖÇø[%d] ÉÈÇø = 0x%.8lx (%ld)\n" + +#: ppcboot.c:459 +#, c-format +msgid "Partition[%d] length = 0x%.8lx (%ld)\n" +msgstr "·ÖÇø[%d] ³¤¶È = 0x%.8lx (%ld)\n" + +#: som.c:5398 +msgid "som_sizeof_headers unimplemented" +msgstr "" + +#: srec.c:301 +#, c-format +msgid "%s:%d: Unexpected character `%s' in S-record file\n" +msgstr "" + +#: stabs.c:319 +#, c-format +msgid "%s(%s+0x%lx): Stabs entry has invalid string index." +msgstr "" + +#: syms.c:1044 +msgid "Unsupported .stab relocation" +msgstr "²»Ö§³ÖµÄ .stab Öض¨Î»" + +#: vms-gsd.c:356 +#, c-format +msgid "bfd_make_section (%s) failed" +msgstr "" + +#: vms-gsd.c:371 +#, c-format +msgid "bfd_set_section_flags (%s, %x) failed" +msgstr "" + +#: vms-gsd.c:407 +#, c-format +msgid "Size mismatch section %s=%lx, %s=%lx" +msgstr "" + +#: vms-gsd.c:702 +#, c-format +msgid "unknown gsd/egsd subtype %d" +msgstr "" + +#: vms-hdr.c:406 +msgid "Object module NOT error-free !\n" +msgstr "" + +#: vms-misc.c:543 +#, c-format +msgid "Stack overflow (%d) in _bfd_vms_push" +msgstr "" + +#: vms-misc.c:561 +msgid "Stack underflow in _bfd_vms_pop" +msgstr "" + +#: vms-misc.c:919 +msgid "_bfd_vms_output_counted called with zero bytes" +msgstr "" + +#: vms-misc.c:924 +msgid "_bfd_vms_output_counted called with too many bytes" +msgstr "" + +#: vms-misc.c:1055 +#, c-format +msgid "Symbol %s replaced by %s\n" +msgstr "" + +#: vms-misc.c:1117 +#, c-format +msgid "failed to enter %s" +msgstr "" + +#: vms-tir.c:81 +msgid "No Mem !" +msgstr "" + +#: vms-tir.c:362 +#, c-format +msgid "bad section index in %s" +msgstr "%s ÖеĴíÎó½ÚË÷Òý" + +#: vms-tir.c:375 +#, c-format +msgid "unsupported STA cmd %s" +msgstr "²»Ö§³ÖµÄ STA ÃüÁî %s" + +#: vms-tir.c:380 vms-tir.c:1240 +#, c-format +msgid "reserved STA cmd %d" +msgstr "" + +#: vms-tir.c:491 vms-tir.c:514 +#, c-format +msgid "%s: no symbol \"%s\"" +msgstr "" + +#. unsigned shift +#. rotate +#. Redefine symbol to current location. +#. Define a literal. +#: vms-tir.c:581 vms-tir.c:693 vms-tir.c:803 vms-tir.c:821 vms-tir.c:829 +#: vms-tir.c:838 vms-tir.c:1563 +#, c-format +msgid "%s: not supported" +msgstr "%s£º²»Ö§³Ö" + +#: vms-tir.c:586 vms-tir.c:1418 +#, c-format +msgid "%s: not implemented" +msgstr "%s£ºÎ´ÊµÏÖ" + +#: vms-tir.c:590 vms-tir.c:1422 +#, c-format +msgid "reserved STO cmd %d" +msgstr "±£ÁôµÄ STO ÃüÁî %d" + +#: vms-tir.c:708 vms-tir.c:1568 +#, c-format +msgid "reserved OPR cmd %d" +msgstr "±£ÁôµÄ OPR ÃüÁî %d" + +#: vms-tir.c:776 vms-tir.c:1632 +#, c-format +msgid "reserved CTL cmd %d" +msgstr "±£ÁôµÄ CTL ÃüÁî %d" + +#. stack byte from image +#. arg: none. +#: vms-tir.c:1148 +msgid "stack-from-image not implemented" +msgstr "δʵÏÖ stack-from-image" + +#: vms-tir.c:1166 +msgid "stack-entry-mask not fully implemented" +msgstr "ÉÐδÍêȫʵÏÖ stack-entry-mask" + +#. compare procedure argument +#. arg: cs symbol name +#. by argument index +#. da argument descriptor +#. +#. compare argument descriptor with symbol argument (ARG$V_PASSMECH) +#. and stack TRUE (args match) or FALSE (args dont match) value. +#: vms-tir.c:1180 +msgid "PASSMECH not fully implemented" +msgstr "ÉÐδÍêȫʵÏÖ PASSMECH" + +#: vms-tir.c:1199 +msgid "stack-local-symbol not fully implemented" +msgstr "ÉÐδÍêȫʵÏÖ stack-local-symbol" + +#: vms-tir.c:1212 +msgid "stack-literal not fully implemented" +msgstr "ÉÐδÍêȫʵÏÖ stack-literal" + +#: vms-tir.c:1233 +msgid "stack-local-symbol-entry-point-mask not fully implemented" +msgstr "ÉÐδÍêȫʵÏÖ stack-local-symbol-entry-point-mask" + +#: vms-tir.c:1510 vms-tir.c:1522 vms-tir.c:1534 vms-tir.c:1546 vms-tir.c:1611 +#: vms-tir.c:1619 vms-tir.c:1627 +#, c-format +msgid "%s: not fully implemented" +msgstr "%s£ºÉÐδÍêȫʵÏÖ" + +#: vms-tir.c:1684 +#, c-format +msgid "obj code %d not found" +msgstr "" + +#: vms-tir.c:2019 +#, c-format +msgid "SEC_RELOC with no relocs in section %s" +msgstr "" + +#: vms-tir.c:2307 +#, c-format +msgid "Unhandled relocation %s" +msgstr "δ´¦ÀíµÄÖض¨Î» %s" + +#: xcofflink.c:1243 +#, c-format +msgid "%s: `%s' has line numbers but no enclosing section" +msgstr "" + +#: xcofflink.c:1296 +#, c-format +msgid "%s: class %d symbol `%s' has no aux entries" +msgstr "" + +#: xcofflink.c:1319 +#, c-format +msgid "%s: symbol `%s' has unrecognized csect type %d" +msgstr "" + +#: xcofflink.c:1331 +#, c-format +msgid "%s: bad XTY_ER symbol `%s': class %d scnum %d scnlen %d" +msgstr "" + +#: xcofflink.c:1367 +#, c-format +msgid "%s: XMC_TC0 symbol `%s' is class %d scnlen %d" +msgstr "" + +#: xcofflink.c:1519 +#, c-format +msgid "%s: csect `%s' not in enclosing section" +msgstr "" + +#: xcofflink.c:1626 +#, c-format +msgid "%s: misplaced XTY_LD `%s'" +msgstr "" + +#: xcofflink.c:1957 +#, c-format +msgid "%s: reloc %s:%d not in csect" +msgstr "" + +#: xcofflink.c:2092 +#, c-format +msgid "%s: XCOFF shared object when not producing XCOFF output" +msgstr "" + +#: xcofflink.c:2113 +#, c-format +msgid "%s: dynamic object with no .loader section" +msgstr "" + +#: xcofflink.c:2758 +#, c-format +msgid "%s: no such symbol" +msgstr "" + +#: xcofflink.c:2891 +msgid "error: undefined symbol __rtinit" +msgstr "´íÎó£ºÎ´¶¨ÒåµÄ·ûºÅ __rtinit" + +#: xcofflink.c:3453 +#, c-format +msgid "warning: attempt to export undefined symbol `%s'" +msgstr "¾¯¸æ£ºÊÔͼµ¼³ö䶨ÒåµÄ·ûºÅ¡°%s¡±" + +#: xcofflink.c:4447 +#, c-format +msgid "TOC overflow: 0x%lx > 0x10000; try -mminimal-toc when compiling" +msgstr "" + +#: xcofflink.c:5287 xcofflink.c:5756 xcofflink.c:5818 xcofflink.c:6119 +#, c-format +msgid "%s: loader reloc in unrecognized section `%s'" +msgstr "" + +#: xcofflink.c:5309 xcofflink.c:6130 +#, c-format +msgid "%s: `%s' in loader reloc but not loader sym" +msgstr "" + +#: xcofflink.c:5324 +#, c-format +msgid "%s: loader reloc in read-only section %s" +msgstr "" + +#: elf32-ia64.c:2222 elf64-ia64.c:2222 +msgid "@pltoff reloc against local symbol" +msgstr "" + +#: elf32-ia64.c:3562 elf64-ia64.c:3562 +#, c-format +msgid "%s: short data segment overflowed (0x%lx >= 0x400000)" +msgstr "" + +#: elf32-ia64.c:3573 elf64-ia64.c:3573 +#, c-format +msgid "%s: __gp does not cover short data segment" +msgstr "" + +#: elf32-ia64.c:3858 elf64-ia64.c:3858 +#, c-format +msgid "%s: linking non-pic code in a shared library" +msgstr "" + +#: elf32-ia64.c:3891 elf64-ia64.c:3891 +#, c-format +msgid "%s: @gprel relocation against dynamic symbol %s" +msgstr "" + +#: elf32-ia64.c:4030 elf64-ia64.c:4030 +#, c-format +msgid "%s: dynamic relocation against speculation fixup" +msgstr "" + +#: elf32-ia64.c:4038 elf64-ia64.c:4038 +#, c-format +msgid "%s: speculation fixup against undefined weak symbol" +msgstr "" + +#: elf32-ia64.c:4271 elf64-ia64.c:4271 +msgid "unsupported reloc" +msgstr "²»Ö§³ÖµÄÖض¨Î»" + +#: elf32-ia64.c:4551 elf64-ia64.c:4551 +#, c-format +msgid "%s: linking trap-on-NULL-dereference with non-trapping files" +msgstr "" + +#: elf32-ia64.c:4560 elf64-ia64.c:4560 +#, c-format +msgid "%s: linking big-endian files with little-endian files" +msgstr "%s£º½«´ó¶ËÎļþͬС¶ËÎļþ" + +#: elf32-ia64.c:4569 elf64-ia64.c:4569 +#, c-format +msgid "%s: linking 64-bit files with 32-bit files" +msgstr "%s£º½« 64-λÎļþͬ 32-λÎļþÁ¬½Ó" + +#: elf32-ia64.c:4578 elf64-ia64.c:4578 +#, c-format +msgid "%s: linking constant-gp files with non-constant-gp files" +msgstr "" + +#: elf32-ia64.c:4588 elf64-ia64.c:4588 +#, c-format +msgid "%s: linking auto-pic files with non-auto-pic files" +msgstr "" + +#: peigen.c:962 pepigen.c:962 +#, c-format +msgid "%s: line number overflow: 0x%lx > 0xffff" +msgstr "%s£ºÐкÅÒç³ö£º0x%lx > 0xffff" + +#: peigen.c:979 pepigen.c:979 +#, c-format +msgid "%s: reloc overflow 1: 0x%lx > 0xffff" +msgstr "" + +#: peigen.c:993 pepigen.c:993 +msgid "Export Directory [.edata (or where ever we found it)]" +msgstr "µ¼³öĿ¼ [.edata (»òÕßÆäËüÈκÎÄÜÕÒµ½ËüµÄµØ·½)]" + +#: peigen.c:994 pepigen.c:994 +msgid "Import Directory [parts of .idata]" +msgstr "µ¼ÈëĿ¼ [.idata µÄÒ»²¿·Ö]" + +#: peigen.c:995 pepigen.c:995 +msgid "Resource Directory [.rsrc]" +msgstr "×ÊԴĿ¼ [.rsrc]" + +#: peigen.c:996 pepigen.c:996 +msgid "Exception Directory [.pdata]" +msgstr "" + +#: peigen.c:997 pepigen.c:997 +msgid "Security Directory" +msgstr "°²È«Ä¿Â¼" + +#: peigen.c:998 pepigen.c:998 +msgid "Base Relocation Directory [.reloc]" +msgstr "" + +#: peigen.c:999 pepigen.c:999 +msgid "Debug Directory" +msgstr "µ÷ÊÔĿ¼" + +#: peigen.c:1000 pepigen.c:1000 +msgid "Description Directory" +msgstr "ÃèÊöĿ¼" + +#: peigen.c:1001 pepigen.c:1001 +msgid "Special Directory" +msgstr "ÌØÊâĿ¼" + +#: peigen.c:1002 pepigen.c:1002 +msgid "Thread Storage Directory [.tls]" +msgstr "Ï̴߳洢Ŀ¼ [.tls]" + +#: peigen.c:1003 pepigen.c:1003 +msgid "Load Configuration Directory" +msgstr "×°ÈëÅäÖÃĿ¼" + +#: peigen.c:1004 pepigen.c:1004 +msgid "Bound Import Directory" +msgstr "" + +#: peigen.c:1005 pepigen.c:1005 +msgid "Import Address Table Directory" +msgstr "µ¼ÈëµØÖ·±íĿ¼" + +#: peigen.c:1006 pepigen.c:1006 +msgid "Delay Import Directory" +msgstr "ÑÓ³Ùµ¼ÈëĿ¼" + +#: peigen.c:1007 peigen.c:1008 pepigen.c:1007 pepigen.c:1008 +msgid "Reserved" +msgstr "±£Áô" + +#: peigen.c:1071 pepigen.c:1071 +msgid "" +"\n" +"There is an import table, but the section containing it could not be found\n" +msgstr "" + +#: peigen.c:1076 pepigen.c:1076 +#, c-format +msgid "" +"\n" +"There is an import table in %s at 0x%lx\n" +msgstr "" + +#: peigen.c:1113 pepigen.c:1113 +#, c-format +msgid "" +"\n" +"Function descriptor located at the start address: %04lx\n" +msgstr "" + +#: peigen.c:1116 pepigen.c:1116 +#, c-format +msgid "\tcode-base %08lx toc (loadable/actual) %08lx/%08lx\n" +msgstr "" + +#: peigen.c:1122 pepigen.c:1122 +msgid "" +"\n" +"No reldata section! Function descriptor not decoded.\n" +msgstr "" + +#: peigen.c:1127 pepigen.c:1127 +#, c-format +msgid "" +"\n" +"The Import Tables (interpreted %s section contents)\n" +msgstr "" + +#: peigen.c:1130 pepigen.c:1130 +msgid "" +" vma: Hint Time Forward DLL First\n" +" Table Stamp Chain Name Thunk\n" +msgstr "" + +#: peigen.c:1181 pepigen.c:1181 +#, c-format +msgid "" +"\n" +"\tDLL Name: %s\n" +msgstr "" +"\n" +"\tDLL Ãû³Æ£º%s\n" + +#: peigen.c:1192 pepigen.c:1192 +msgid "\tvma: Hint/Ord Member-Name Bound-To\n" +msgstr "" + +#: peigen.c:1217 pepigen.c:1217 +msgid "" +"\n" +"There is a first thunk, but the section containing it could not be found\n" +msgstr "" + +#: peigen.c:1357 pepigen.c:1357 +msgid "" +"\n" +"There is an export table, but the section containing it could not be found\n" +msgstr "" + +#: peigen.c:1362 pepigen.c:1362 +#, c-format +msgid "" +"\n" +"There is an export table in %s at 0x%lx\n" +msgstr "" +"\n" +"%s Öеĵ¼³ö±íλÓÚ 0x%lx\n" + +#: peigen.c:1393 pepigen.c:1393 +#, c-format +msgid "" +"\n" +"The Export Tables (interpreted %s section contents)\n" +"\n" +msgstr "" + +#: peigen.c:1397 pepigen.c:1397 +#, c-format +msgid "Export Flags \t\t\t%lx\n" +msgstr "µ¼³ö±êÖ¾ \t\t\t%lx\n" + +#: peigen.c:1400 pepigen.c:1400 +#, c-format +msgid "Time/Date stamp \t\t%lx\n" +msgstr "ÈÕÆÚ/ʱ¼ä´Á \t\t%lx\n" + +#: peigen.c:1403 pepigen.c:1403 +#, c-format +msgid "Major/Minor \t\t\t%d/%d\n" +msgstr "" + +#: peigen.c:1406 pepigen.c:1406 +msgid "Name \t\t\t\t" +msgstr "Ãû³Æ \t\t\t\t" + +#: peigen.c:1412 pepigen.c:1412 +#, c-format +msgid "Ordinal Base \t\t\t%ld\n" +msgstr "" + +#: peigen.c:1415 pepigen.c:1415 +msgid "Number in:\n" +msgstr "" + +#: peigen.c:1418 pepigen.c:1418 +#, c-format +msgid "\tExport Address Table \t\t%08lx\n" +msgstr "" + +#: peigen.c:1422 pepigen.c:1422 +#, c-format +msgid "\t[Name Pointer/Ordinal] Table\t%08lx\n" +msgstr "" + +#: peigen.c:1425 pepigen.c:1425 +msgid "Table Addresses\n" +msgstr "±íµØÖ·\n" + +#: peigen.c:1428 pepigen.c:1428 +msgid "\tExport Address Table \t\t" +msgstr "\tµ¼³öµØÖ·±í \t\t" + +#: peigen.c:1433 pepigen.c:1433 +msgid "\tName Pointer Table \t\t" +msgstr "\tÃû³ÆÖ¸Õë±í \t\t" + +#: peigen.c:1438 pepigen.c:1438 +msgid "\tOrdinal Table \t\t\t" +msgstr "" + +#: peigen.c:1453 pepigen.c:1453 +#, c-format +msgid "" +"\n" +"Export Address Table -- Ordinal Base %ld\n" +msgstr "" + +#: peigen.c:1472 pepigen.c:1472 +msgid "Forwarder RVA" +msgstr "" + +#: peigen.c:1483 pepigen.c:1483 +msgid "Export RVA" +msgstr "µ¼³ö RVA" + +#: peigen.c:1490 pepigen.c:1490 +msgid "" +"\n" +"[Ordinal/Name Pointer] Table\n" +msgstr "" + +#: peigen.c:1545 pepigen.c:1545 +#, c-format +msgid "Warning, .pdata section size (%ld) is not a multiple of %d\n" +msgstr "" + +#: peigen.c:1549 pepigen.c:1549 +msgid "" +"\n" +"The Function Table (interpreted .pdata section contents)\n" +msgstr "" + +#: peigen.c:1552 pepigen.c:1552 +msgid " vma:\t\t\tBegin Address End Address Unwind Info\n" +msgstr "" + +#: peigen.c:1554 pepigen.c:1554 +msgid "" +" vma:\t\tBegin End EH EH PrologEnd Exception\n" +" \t\tAddress Address Handler Data Address Mask\n" +msgstr "" + +#: peigen.c:1624 pepigen.c:1624 +msgid " Register save millicode" +msgstr "" + +#: peigen.c:1627 pepigen.c:1627 +msgid " Register restore millicode" +msgstr "" + +#: peigen.c:1630 pepigen.c:1630 +msgid " Glue code sequence" +msgstr "" + +#: peigen.c:1682 pepigen.c:1682 +msgid "" +"\n" +"\n" +"PE File Base Relocations (interpreted .reloc section contents)\n" +msgstr "" + +#: peigen.c:1712 pepigen.c:1712 +#, c-format +msgid "" +"\n" +"Virtual Address: %08lx Chunk size %ld (0x%lx) Number of fixups %ld\n" +msgstr "" + +#: peigen.c:1725 pepigen.c:1725 +#, c-format +msgid "\treloc %4d offset %4x [%4lx] %s" +msgstr "" + +#. The MS dumpbin program reportedly ands with 0xff0f before +#. printing the characteristics field. Not sure why. No reason to +#. emulate it here. +#: peigen.c:1765 pepigen.c:1765 +#, c-format +msgid "" +"\n" +"Characteristics 0x%x\n" +msgstr "" diff --git a/bfd/xsym.c b/bfd/xsym.c new file mode 100644 index 0000000..a4058dd --- /dev/null +++ b/bfd/xsym.c @@ -0,0 +1,2484 @@ +/* xSYM symbol-file support for BFD. + Copyright 1999, 2000, 2001, 2002, 2003 + Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include "xsym.h" +#include "bfd.h" +#include "sysdep.h" +#include "libbfd.h" + +#define bfd_sym_close_and_cleanup _bfd_generic_close_and_cleanup +#define bfd_sym_bfd_free_cached_info _bfd_generic_bfd_free_cached_info +#define bfd_sym_new_section_hook _bfd_generic_new_section_hook +#define bfd_sym_bfd_is_local_label_name bfd_generic_is_local_label_name +#define bfd_sym_get_lineno _bfd_nosymbols_get_lineno +#define bfd_sym_find_nearest_line _bfd_nosymbols_find_nearest_line +#define bfd_sym_bfd_make_debug_symbol _bfd_nosymbols_bfd_make_debug_symbol +#define bfd_sym_read_minisymbols _bfd_generic_read_minisymbols +#define bfd_sym_minisymbol_to_symbol _bfd_generic_minisymbol_to_symbol +#define bfd_sym_get_reloc_upper_bound _bfd_norelocs_get_reloc_upper_bound +#define bfd_sym_canonicalize_reloc _bfd_norelocs_canonicalize_reloc +#define bfd_sym_bfd_reloc_type_lookup _bfd_norelocs_bfd_reloc_type_lookup +#define bfd_sym_set_arch_mach _bfd_generic_set_arch_mach +#define bfd_sym_get_section_contents _bfd_generic_get_section_contents +#define bfd_sym_set_section_contents _bfd_generic_set_section_contents +#define bfd_sym_bfd_get_relocated_section_contents bfd_generic_get_relocated_section_contents +#define bfd_sym_bfd_relax_section bfd_generic_relax_section +#define bfd_sym_bfd_gc_sections bfd_generic_gc_sections +#define bfd_sym_bfd_merge_sections bfd_generic_merge_sections +#define bfd_sym_bfd_discard_group bfd_generic_discard_group +#define bfd_sym_bfd_link_hash_table_create _bfd_generic_link_hash_table_create +#define bfd_sym_bfd_link_hash_table_free _bfd_generic_link_hash_table_free +#define bfd_sym_bfd_link_add_symbols _bfd_generic_link_add_symbols +#define bfd_sym_bfd_link_just_syms _bfd_generic_link_just_syms +#define bfd_sym_bfd_final_link _bfd_generic_final_link +#define bfd_sym_bfd_link_split_section _bfd_generic_link_split_section +#define bfd_sym_get_section_contents_in_window _bfd_generic_get_section_contents_in_window + +static int pstrcmp PARAMS ((unsigned char *, unsigned char *)); +static unsigned long compute_offset + PARAMS ((unsigned long, unsigned long, unsigned long, unsigned long)); + +extern const bfd_target sym_vec; + +static int +pstrcmp (a, b) + unsigned char *a; + unsigned char *b; +{ + unsigned char clen; + int ret; + + clen = (a[0] > b[0]) ? a[0] : b[0]; + ret = memcmp (a + 1, b + 1, clen); + if (ret != 0) + return ret; + + if (a[0] == b[0]) + return 0; + else if (a[0] < b[0]) + return -1; + else + return 0; +} + +static unsigned long +compute_offset (first_page, page_size, entry_size, index) + unsigned long first_page; + unsigned long page_size; + unsigned long entry_size; + unsigned long index; +{ + unsigned long entries_per_page = page_size / entry_size; + unsigned long page_number = first_page + (index / entries_per_page); + unsigned long page_offset = (index % entries_per_page) * entry_size; + + return (page_number * page_size) + page_offset; +} + +bfd_boolean +bfd_sym_mkobject (abfd) + bfd *abfd ATTRIBUTE_UNUSED; +{ + return 1; +} + +void +bfd_sym_print_symbol (abfd, afile, symbol, how) + bfd *abfd ATTRIBUTE_UNUSED; + PTR afile ATTRIBUTE_UNUSED; + asymbol *symbol ATTRIBUTE_UNUSED; + bfd_print_symbol_type how ATTRIBUTE_UNUSED; +{ + return; +} + +bfd_boolean +bfd_sym_valid (abfd) + bfd *abfd; +{ + if (abfd == NULL || abfd->xvec == NULL) + return 0; + + return abfd->xvec == &sym_vec; +} + +unsigned char * +bfd_sym_read_name_table (abfd, dshb) + bfd *abfd; + bfd_sym_header_block *dshb; +{ + unsigned char *rstr; + long ret; + size_t table_size = dshb->dshb_nte.dti_page_count * dshb->dshb_page_size; + size_t table_offset = dshb->dshb_nte.dti_first_page * dshb->dshb_page_size; + + rstr = (unsigned char *) bfd_alloc (abfd, table_size); + if (rstr == NULL) + return rstr; + + bfd_seek (abfd, table_offset, SEEK_SET); + ret = bfd_bread (rstr, table_size, abfd); + if (ret < 0 || (unsigned long) ret != table_size) + { + bfd_release (abfd, rstr); + return NULL; + } + + return rstr; +} + +void +bfd_sym_parse_file_reference_v32 (buf, len, entry) + unsigned char *buf; + size_t len; + bfd_sym_file_reference *entry; +{ + BFD_ASSERT (len == 6); + + entry->fref_frte_index = bfd_getb16 (buf); + entry->fref_offset = bfd_getb32 (buf + 2); +} + +void +bfd_sym_parse_disk_table_v32 (buf, len, table) + unsigned char *buf; + size_t len; + bfd_sym_table_info *table; +{ + BFD_ASSERT (len == 8); + + table->dti_first_page = bfd_getb16 (buf); + table->dti_page_count = bfd_getb16 (buf + 2); + table->dti_object_count = bfd_getb32 (buf + 4); +} + +void +bfd_sym_parse_header_v32 (buf, len, header) + unsigned char *buf; + size_t len; + bfd_sym_header_block *header; +{ + BFD_ASSERT (len == 154); + + memcpy (header->dshb_id, buf, 32); + header->dshb_page_size = bfd_getb16 (buf + 32); + header->dshb_hash_page = bfd_getb16 (buf + 34); + header->dshb_root_mte = bfd_getb16 (buf + 36); + header->dshb_mod_date = bfd_getb32 (buf + 38); + + bfd_sym_parse_disk_table_v32 (buf + 42, 8, &header->dshb_frte); + bfd_sym_parse_disk_table_v32 (buf + 50, 8, &header->dshb_rte); + bfd_sym_parse_disk_table_v32 (buf + 58, 8, &header->dshb_mte); + bfd_sym_parse_disk_table_v32 (buf + 66, 8, &header->dshb_cmte); + bfd_sym_parse_disk_table_v32 (buf + 74, 8, &header->dshb_cvte); + bfd_sym_parse_disk_table_v32 (buf + 82, 8, &header->dshb_csnte); + bfd_sym_parse_disk_table_v32 (buf + 90, 8, &header->dshb_clte); + bfd_sym_parse_disk_table_v32 (buf + 98, 8, &header->dshb_ctte); + bfd_sym_parse_disk_table_v32 (buf + 106, 8, &header->dshb_tte); + bfd_sym_parse_disk_table_v32 (buf + 114, 8, &header->dshb_nte); + bfd_sym_parse_disk_table_v32 (buf + 122, 8, &header->dshb_tinfo); + bfd_sym_parse_disk_table_v32 (buf + 130, 8, &header->dshb_fite); + bfd_sym_parse_disk_table_v32 (buf + 138, 8, &header->dshb_const); + + memcpy (&header->dshb_file_creator, buf + 146, 4); + memcpy (&header->dshb_file_type, buf + 150, 4); +} + +int +bfd_sym_read_header_v32 (abfd, header) + bfd *abfd; + bfd_sym_header_block *header; +{ + unsigned char buf[154]; + long ret; + + ret = bfd_bread (buf, 154, abfd); + if (ret != 154) + return -1; + + bfd_sym_parse_header_v32 (buf, 154, header); + + return 0; +} + +int +bfd_sym_read_header_v34 (abfd, header) + bfd *abfd ATTRIBUTE_UNUSED; + bfd_sym_header_block *header ATTRIBUTE_UNUSED; +{ + abort (); +} + +int +bfd_sym_read_header (abfd, header, version) + bfd *abfd; + bfd_sym_header_block *header; + bfd_sym_version version; +{ + switch (version) + { + case BFD_SYM_VERSION_3_5: + case BFD_SYM_VERSION_3_4: + return bfd_sym_read_header_v34 (abfd, header); + case BFD_SYM_VERSION_3_3: + case BFD_SYM_VERSION_3_2: + return bfd_sym_read_header_v32 (abfd, header); + case BFD_SYM_VERSION_3_1: + default: + return FALSE; + } +} + +int +bfd_sym_read_version (abfd, version) + bfd *abfd; + bfd_sym_version *version; +{ + unsigned char version_string[32]; + long ret; + + ret = bfd_bread (version_string, sizeof (version_string), abfd); + if (ret != sizeof (version_string)) + return -1; + + if (pstrcmp (version_string, BFD_SYM_VERSION_STR_3_1) == 0) + *version = BFD_SYM_VERSION_3_1; + else if (pstrcmp (version_string, BFD_SYM_VERSION_STR_3_2) == 0) + *version = BFD_SYM_VERSION_3_2; + else if (pstrcmp (version_string, BFD_SYM_VERSION_STR_3_3) == 0) + *version = BFD_SYM_VERSION_3_3; + else if (pstrcmp (version_string, BFD_SYM_VERSION_STR_3_4) == 0) + *version = BFD_SYM_VERSION_3_4; + else if (pstrcmp (version_string, BFD_SYM_VERSION_STR_3_5) == 0) + *version = BFD_SYM_VERSION_3_5; + else + return -1; + + return 0; +} + +void +bfd_sym_display_table_summary (f, dti, name) + FILE *f; + bfd_sym_table_info *dti; + const char *name; +{ + fprintf (f, "%-6s %13ld %13ld %13ld\n", + name, + dti->dti_first_page, + dti->dti_page_count, + dti->dti_object_count); +} + +void +bfd_sym_display_header (f, dshb) + FILE *f; + bfd_sym_header_block *dshb; +{ + fprintf (f, " Version: %.*s\n", dshb->dshb_id[0], dshb->dshb_id + 1); + fprintf (f, " Page Size: 0x%x\n", dshb->dshb_page_size); + fprintf (f, " Hash Page: %lu\n", dshb->dshb_hash_page); + fprintf (f, " Root MTE: %lu\n", dshb->dshb_root_mte); + fprintf (f, " Modification Date: "); + fprintf (f, "[unimplemented]"); + fprintf (f, " (0x%lx)\n", dshb->dshb_mod_date); + + fprintf (f, " File Creator: %.4s Type: %.4s\n\n", + dshb->dshb_file_creator, dshb->dshb_file_type); + + fprintf (f, "Table Name First Page Page Count Object Count\n"); + fprintf (f, "~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n"); + + bfd_sym_display_table_summary (f, &dshb->dshb_nte, "NTE"); + bfd_sym_display_table_summary (f, &dshb->dshb_rte, "RTE"); + bfd_sym_display_table_summary (f, &dshb->dshb_mte, "MTE"); + bfd_sym_display_table_summary (f, &dshb->dshb_frte, "FRTE"); + bfd_sym_display_table_summary (f, &dshb->dshb_cmte, "CMTE"); + bfd_sym_display_table_summary (f, &dshb->dshb_cvte, "CVTE"); + bfd_sym_display_table_summary (f, &dshb->dshb_csnte, "CSNTE"); + bfd_sym_display_table_summary (f, &dshb->dshb_clte, "CLTE"); + bfd_sym_display_table_summary (f, &dshb->dshb_ctte, "CTTE"); + bfd_sym_display_table_summary (f, &dshb->dshb_tte, "TTE"); + bfd_sym_display_table_summary (f, &dshb->dshb_tinfo, "TINFO"); + bfd_sym_display_table_summary (f, &dshb->dshb_fite, "FITE"); + bfd_sym_display_table_summary (f, &dshb->dshb_const, "CONST"); + + fprintf (f, "\n"); +} + +void +bfd_sym_parse_resources_table_entry_v32 (buf, len, entry) + unsigned char *buf; + size_t len; + bfd_sym_resources_table_entry *entry; +{ + BFD_ASSERT (len == 18); + + memcpy (&entry->rte_res_type, buf, 4); + entry->rte_res_number = bfd_getb16 (buf + 4); + entry->rte_nte_index = bfd_getb32 (buf + 6); + entry->rte_mte_first = bfd_getb16 (buf + 10); + entry->rte_mte_last = bfd_getb16 (buf + 12); + entry->rte_res_size = bfd_getb32 (buf + 14); +} + +void +bfd_sym_parse_modules_table_entry_v33 (buf, len, entry) + unsigned char *buf; + size_t len; + bfd_sym_modules_table_entry *entry; +{ + BFD_ASSERT (len == 46); + + entry->mte_rte_index = bfd_getb16 (buf); + entry->mte_res_offset = bfd_getb32 (buf + 2); + entry->mte_size = bfd_getb32 (buf + 6); + entry->mte_kind = buf[10]; + entry->mte_scope = buf[11]; + entry->mte_parent = bfd_getb16 (buf + 12); + bfd_sym_parse_file_reference_v32 (buf + 14, 6, &entry->mte_imp_fref); + entry->mte_imp_end = bfd_getb32 (buf + 20); + entry->mte_nte_index = bfd_getb32 (buf + 24); + entry->mte_cmte_index = bfd_getb16 (buf + 28); + entry->mte_cvte_index = bfd_getb32 (buf + 30); + entry->mte_clte_index = bfd_getb16 (buf + 34); + entry->mte_ctte_index = bfd_getb16 (buf + 36); + entry->mte_csnte_idx_1 = bfd_getb32 (buf + 38); + entry->mte_csnte_idx_2 = bfd_getb32 (buf + 42); +} + +void +bfd_sym_parse_file_references_table_entry_v32 (buf, len, entry) + unsigned char *buf; + size_t len; + bfd_sym_file_references_table_entry *entry; +{ + unsigned int type; + + BFD_ASSERT (len == 10); + + memset (entry, 0, sizeof (bfd_sym_file_references_table_entry)); + type = bfd_getb16 (buf); + + switch (type) + { + case BFD_SYM_END_OF_LIST_3_2: + entry->generic.type = BFD_SYM_END_OF_LIST; + break; + + case BFD_SYM_FILE_NAME_INDEX_3_2: + entry->filename.type = BFD_SYM_FILE_NAME_INDEX; + entry->filename.nte_index = bfd_getb32 (buf + 2); + entry->filename.mod_date = bfd_getb32 (buf + 6); + break; + + default: + entry->entry.mte_index = type; + entry->entry.file_offset = bfd_getb32 (buf + 2); + } +} + +void +bfd_sym_parse_contained_modules_table_entry_v32 (buf, len, entry) + unsigned char *buf; + size_t len; + bfd_sym_contained_modules_table_entry *entry; +{ + unsigned int type; + + BFD_ASSERT (len == 6); + + memset (entry, 0, sizeof (bfd_sym_contained_modules_table_entry)); + type = bfd_getb16 (buf); + + switch (type) + { + case BFD_SYM_END_OF_LIST_3_2: + entry->generic.type = BFD_SYM_END_OF_LIST; + break; + + default: + entry->entry.mte_index = type; + entry->entry.nte_index = bfd_getb32 (buf + 2); + break; + } +} + +void +bfd_sym_parse_contained_variables_table_entry_v32 (buf, len, entry) + unsigned char *buf; + size_t len; + bfd_sym_contained_variables_table_entry *entry; +{ + unsigned int type; + + BFD_ASSERT (len == 26); + + memset (entry, 0, sizeof (bfd_sym_contained_variables_table_entry)); + type = bfd_getb16 (buf); + + switch (type) + { + case BFD_SYM_END_OF_LIST_3_2: + entry->generic.type = BFD_SYM_END_OF_LIST; + break; + + case BFD_SYM_SOURCE_FILE_CHANGE_3_2: + entry->file.type = BFD_SYM_SOURCE_FILE_CHANGE; + bfd_sym_parse_file_reference_v32 (buf + 2, 6, &entry->file.fref); + break; + + default: + entry->entry.tte_index = type; + entry->entry.nte_index = bfd_getb32 (buf + 2); + entry->entry.file_delta = bfd_getb16 (buf + 6); + entry->entry.scope = buf[8]; + entry->entry.la_size = buf[9]; + + if (entry->entry.la_size == BFD_SYM_CVTE_SCA) + { + entry->entry.address.scstruct.sca_kind = buf[10]; + entry->entry.address.scstruct.sca_class = buf[11]; + entry->entry.address.scstruct.sca_offset = bfd_getb32 (buf + 12); + } + else if (entry->entry.la_size <= BFD_SYM_CVTE_SCA) + { + memcpy (&entry->entry.address.lastruct.la, buf + 10, BFD_SYM_CVTE_SCA); + entry->entry.address.lastruct.la_kind = buf[23]; + } + else if (entry->entry.la_size == BFD_SYM_CVTE_BIG_LA) + { + entry->entry.address.biglastruct.big_la = bfd_getb32 (buf + 10); + entry->entry.address.biglastruct.big_la_kind = buf[12]; + } + } +} + +void +bfd_sym_parse_contained_statements_table_entry_v32 (buf, len, entry) + unsigned char *buf; + size_t len; + bfd_sym_contained_statements_table_entry *entry; +{ + unsigned int type; + + BFD_ASSERT (len == 8); + + memset (entry, 0, sizeof (bfd_sym_contained_statements_table_entry)); + type = bfd_getb16 (buf); + + switch (type) + { + case BFD_SYM_END_OF_LIST_3_2: + entry->generic.type = BFD_SYM_END_OF_LIST; + break; + + case BFD_SYM_SOURCE_FILE_CHANGE_3_2: + entry->file.type = BFD_SYM_SOURCE_FILE_CHANGE; + bfd_sym_parse_file_reference_v32 (buf + 2, 6, &entry->file.fref); + break; + + default: + entry->entry.mte_index = type; + entry->entry.mte_offset = bfd_getb16 (buf + 2); + entry->entry.file_delta = bfd_getb32 (buf + 4); + break; + } +} + +void +bfd_sym_parse_contained_labels_table_entry_v32 (buf, len, entry) + unsigned char *buf; + size_t len; + bfd_sym_contained_labels_table_entry *entry; +{ + unsigned int type; + + BFD_ASSERT (len == 12); + + memset (entry, 0, sizeof (bfd_sym_contained_labels_table_entry)); + type = bfd_getb16 (buf); + + switch (type) + { + case BFD_SYM_END_OF_LIST_3_2: + entry->generic.type = BFD_SYM_END_OF_LIST; + break; + + case BFD_SYM_SOURCE_FILE_CHANGE_3_2: + entry->file.type = BFD_SYM_SOURCE_FILE_CHANGE; + bfd_sym_parse_file_reference_v32 (buf + 2, 6, &entry->file.fref); + break; + + default: + entry->entry.mte_index = type; + entry->entry.mte_offset = bfd_getb16 (buf + 2); + entry->entry.nte_index = bfd_getb32 (buf + 4); + entry->entry.file_delta = bfd_getb16 (buf + 8); + entry->entry.scope = bfd_getb16 (buf + 10); + break; + } +} + +void +bfd_sym_parse_type_table_entry_v32 (buf, len, entry) + unsigned char *buf; + size_t len; + bfd_sym_type_table_entry *entry; +{ + BFD_ASSERT (len == 4); + + *entry = bfd_getb32 (buf); +} + +int +bfd_sym_fetch_resources_table_entry (abfd, entry, index) + bfd *abfd; + bfd_sym_resources_table_entry *entry; + unsigned long index; +{ + void (*parser) PARAMS ((unsigned char *, size_t, + bfd_sym_resources_table_entry *)); + unsigned long offset; + unsigned long entry_size; + unsigned char buf[18]; + bfd_sym_data_struct *sdata = NULL; + + parser = NULL; + BFD_ASSERT (bfd_sym_valid (abfd)); + sdata = abfd->tdata.sym_data; + + if (index == 0) + return -1; + + switch (sdata->version) + { + case BFD_SYM_VERSION_3_5: + case BFD_SYM_VERSION_3_4: + return -1; + + case BFD_SYM_VERSION_3_3: + case BFD_SYM_VERSION_3_2: + entry_size = 18; + parser = bfd_sym_parse_resources_table_entry_v32; + break; + + case BFD_SYM_VERSION_3_1: + default: + return -1; + } + if (parser == NULL) + return -1; + + offset = compute_offset (sdata->header.dshb_rte.dti_first_page, + sdata->header.dshb_page_size, + entry_size, index); + + if (bfd_seek (abfd, offset, SEEK_SET) < 0) + return -1; + if (bfd_bread (buf, entry_size, abfd) != entry_size) + return -1; + + (*parser) (buf, entry_size, entry); + + return 0; +} + +int +bfd_sym_fetch_modules_table_entry (abfd, entry, index) + bfd *abfd; + bfd_sym_modules_table_entry *entry; + unsigned long index; +{ + void (*parser) PARAMS ((unsigned char *, size_t, + bfd_sym_modules_table_entry *)); + unsigned long offset; + unsigned long entry_size; + unsigned char buf[46]; + bfd_sym_data_struct *sdata = NULL; + + parser = NULL; + BFD_ASSERT (bfd_sym_valid (abfd)); + sdata = abfd->tdata.sym_data; + + if (index == 0) + return -1; + + switch (sdata->version) + { + case BFD_SYM_VERSION_3_5: + case BFD_SYM_VERSION_3_4: + return -1; + + case BFD_SYM_VERSION_3_3: + entry_size = 46; + parser = bfd_sym_parse_modules_table_entry_v33; + break; + + case BFD_SYM_VERSION_3_2: + case BFD_SYM_VERSION_3_1: + default: + return -1; + } + if (parser == NULL) + return -1; + + offset = compute_offset (sdata->header.dshb_mte.dti_first_page, + sdata->header.dshb_page_size, + entry_size, index); + + if (bfd_seek (abfd, offset, SEEK_SET) < 0) + return -1; + if (bfd_bread (buf, entry_size, abfd) != entry_size) + return -1; + + (*parser) (buf, entry_size, entry); + + return 0; +} + +int +bfd_sym_fetch_file_references_table_entry (abfd, entry, index) + bfd *abfd; + bfd_sym_file_references_table_entry *entry; + unsigned long index; +{ + void (*parser) PARAMS ((unsigned char *, size_t, + bfd_sym_file_references_table_entry *)); + unsigned long offset; + unsigned long entry_size = 0; + unsigned char buf[8]; + bfd_sym_data_struct *sdata = NULL; + + parser = NULL; + BFD_ASSERT (bfd_sym_valid (abfd)); + sdata = abfd->tdata.sym_data; + + if (index == 0) + return -1; + + switch (sdata->version) + { + case BFD_SYM_VERSION_3_3: + case BFD_SYM_VERSION_3_2: + entry_size = 10; + parser = bfd_sym_parse_file_references_table_entry_v32; + break; + + case BFD_SYM_VERSION_3_5: + case BFD_SYM_VERSION_3_4: + case BFD_SYM_VERSION_3_1: + default: + break; + } + + if (parser == NULL) + return -1; + + offset = compute_offset (sdata->header.dshb_frte.dti_first_page, + sdata->header.dshb_page_size, + entry_size, index); + + if (bfd_seek (abfd, offset, SEEK_SET) < 0) + return -1; + if (bfd_bread (buf, entry_size, abfd) != entry_size) + return -1; + + (*parser) (buf, entry_size, entry); + + return 0; +} + +int +bfd_sym_fetch_contained_modules_table_entry (abfd, entry, index) + bfd *abfd; + bfd_sym_contained_modules_table_entry *entry; + unsigned long index; +{ + void (*parser) PARAMS ((unsigned char *, size_t, + bfd_sym_contained_modules_table_entry *)); + unsigned long offset; + unsigned long entry_size = 0; + unsigned char buf[6]; + bfd_sym_data_struct *sdata = NULL; + + parser = NULL; + BFD_ASSERT (bfd_sym_valid (abfd)); + sdata = abfd->tdata.sym_data; + + if (index == 0) + return -1; + + switch (sdata->version) + { + case BFD_SYM_VERSION_3_3: + case BFD_SYM_VERSION_3_2: + entry_size = 6; + parser = bfd_sym_parse_contained_modules_table_entry_v32; + break; + + case BFD_SYM_VERSION_3_5: + case BFD_SYM_VERSION_3_4: + case BFD_SYM_VERSION_3_1: + default: + break; + } + + if (parser == NULL) + return -1; + + offset = compute_offset (sdata->header.dshb_cmte.dti_first_page, + sdata->header.dshb_page_size, + entry_size, index); + + if (bfd_seek (abfd, offset, SEEK_SET) < 0) + return -1; + if (bfd_bread (buf, entry_size, abfd) != entry_size) + return -1; + + (*parser) (buf, entry_size, entry); + + return 0; +} + +int +bfd_sym_fetch_contained_variables_table_entry (abfd, entry, index) + bfd *abfd; + bfd_sym_contained_variables_table_entry *entry; + unsigned long index; +{ + void (*parser) PARAMS ((unsigned char *, size_t, + bfd_sym_contained_variables_table_entry *)); + unsigned long offset; + unsigned long entry_size = 0; + unsigned char buf[26]; + bfd_sym_data_struct *sdata = NULL; + + parser = NULL; + BFD_ASSERT (bfd_sym_valid (abfd)); + sdata = abfd->tdata.sym_data; + + if (index == 0) + return -1; + + switch (sdata->version) + { + case BFD_SYM_VERSION_3_3: + case BFD_SYM_VERSION_3_2: + entry_size = 26; + parser = bfd_sym_parse_contained_variables_table_entry_v32; + break; + + case BFD_SYM_VERSION_3_5: + case BFD_SYM_VERSION_3_4: + case BFD_SYM_VERSION_3_1: + default: + break; + } + + if (parser == NULL) + return -1; + + offset = compute_offset (sdata->header.dshb_cvte.dti_first_page, + sdata->header.dshb_page_size, + entry_size, index); + + if (bfd_seek (abfd, offset, SEEK_SET) < 0) + return -1; + if (bfd_bread (buf, entry_size, abfd) != entry_size) + return -1; + + (*parser) (buf, entry_size, entry); + + return 0; +} + +int +bfd_sym_fetch_contained_statements_table_entry (abfd, entry, index) + bfd *abfd; + bfd_sym_contained_statements_table_entry *entry; + unsigned long index; +{ + void (*parser) PARAMS ((unsigned char *, size_t, + bfd_sym_contained_statements_table_entry *)); + unsigned long offset; + unsigned long entry_size = 0; + unsigned char buf[8]; + bfd_sym_data_struct *sdata = NULL; + + parser = NULL; + BFD_ASSERT (bfd_sym_valid (abfd)); + sdata = abfd->tdata.sym_data; + + if (index == 0) + return -1; + + switch (sdata->version) + { + case BFD_SYM_VERSION_3_3: + case BFD_SYM_VERSION_3_2: + entry_size = 8; + parser = bfd_sym_parse_contained_statements_table_entry_v32; + break; + + case BFD_SYM_VERSION_3_5: + case BFD_SYM_VERSION_3_4: + case BFD_SYM_VERSION_3_1: + default: + break; + } + + if (parser == NULL) + return -1; + + offset = compute_offset (sdata->header.dshb_csnte.dti_first_page, + sdata->header.dshb_page_size, + entry_size, index); + + if (bfd_seek (abfd, offset, SEEK_SET) < 0) + return -1; + if (bfd_bread (buf, entry_size, abfd) != entry_size) + return -1; + + (*parser) (buf, entry_size, entry); + + return 0; +} + +int +bfd_sym_fetch_contained_labels_table_entry (abfd, entry, index) + bfd *abfd; + bfd_sym_contained_labels_table_entry *entry; + unsigned long index; +{ + void (*parser) PARAMS ((unsigned char *, size_t, + bfd_sym_contained_labels_table_entry *)); + unsigned long offset; + unsigned long entry_size = 0; + unsigned char buf[12]; + bfd_sym_data_struct *sdata = NULL; + + parser = NULL; + BFD_ASSERT (bfd_sym_valid (abfd)); + sdata = abfd->tdata.sym_data; + + if (index == 0) + return -1; + + switch (sdata->version) + { + case BFD_SYM_VERSION_3_3: + case BFD_SYM_VERSION_3_2: + entry_size = 12; + parser = bfd_sym_parse_contained_labels_table_entry_v32; + break; + + case BFD_SYM_VERSION_3_5: + case BFD_SYM_VERSION_3_4: + case BFD_SYM_VERSION_3_1: + default: + break; + } + + if (parser == NULL) + return -1; + + offset = compute_offset (sdata->header.dshb_clte.dti_first_page, + sdata->header.dshb_page_size, + entry_size, index); + + if (bfd_seek (abfd, offset, SEEK_SET) < 0) + return -1; + if (bfd_bread (buf, entry_size, abfd) != entry_size) + return -1; + + (*parser) (buf, entry_size, entry); + + return 0; +} + +int +bfd_sym_fetch_contained_types_table_entry (abfd, entry, index) + bfd *abfd; + bfd_sym_contained_types_table_entry *entry; + unsigned long index; +{ + void (*parser) PARAMS ((unsigned char *, size_t, + bfd_sym_contained_types_table_entry *)); + unsigned long offset; + unsigned long entry_size = 0; + unsigned char buf[0]; + bfd_sym_data_struct *sdata = NULL; + + parser = NULL; + BFD_ASSERT (bfd_sym_valid (abfd)); + sdata = abfd->tdata.sym_data; + + if (index == 0) + return -1; + + switch (sdata->version) + { + case BFD_SYM_VERSION_3_3: + case BFD_SYM_VERSION_3_2: + entry_size = 0; + parser = NULL; + break; + + case BFD_SYM_VERSION_3_5: + case BFD_SYM_VERSION_3_4: + case BFD_SYM_VERSION_3_1: + default: + break; + } + + if (parser == NULL) + return -1; + + offset = compute_offset (sdata->header.dshb_ctte.dti_first_page, + sdata->header.dshb_page_size, + entry_size, index); + + if (bfd_seek (abfd, offset, SEEK_SET) < 0) + return -1; + if (bfd_bread (buf, entry_size, abfd) != entry_size) + return -1; + + (*parser) (buf, entry_size, entry); + + return 0; +} + +int +bfd_sym_fetch_file_references_index_table_entry (abfd, entry, index) + bfd *abfd; + bfd_sym_file_references_index_table_entry *entry; + unsigned long index; +{ + void (*parser) PARAMS ((unsigned char *, size_t, + bfd_sym_file_references_index_table_entry *)); + unsigned long offset; + unsigned long entry_size = 0; + unsigned char buf[0]; + bfd_sym_data_struct *sdata = NULL; + + parser = NULL; + BFD_ASSERT (bfd_sym_valid (abfd)); + sdata = abfd->tdata.sym_data; + + if (index == 0) + return -1; + + switch (sdata->version) + { + case BFD_SYM_VERSION_3_3: + case BFD_SYM_VERSION_3_2: + entry_size = 0; + parser = NULL; + break; + + case BFD_SYM_VERSION_3_5: + case BFD_SYM_VERSION_3_4: + case BFD_SYM_VERSION_3_1: + default: + break; + } + + if (parser == NULL) + return -1; + + offset = compute_offset (sdata->header.dshb_fite.dti_first_page, + sdata->header.dshb_page_size, + entry_size, index); + + if (bfd_seek (abfd, offset, SEEK_SET) < 0) + return -1; + if (bfd_bread (buf, entry_size, abfd) != entry_size) + return -1; + + (*parser) (buf, entry_size, entry); + + return 0; +} + +int +bfd_sym_fetch_constant_pool_entry (abfd, entry, index) + bfd *abfd; + bfd_sym_constant_pool_entry *entry; + unsigned long index; +{ + void (*parser) PARAMS ((unsigned char *, size_t, + bfd_sym_constant_pool_entry *)); + unsigned long offset; + unsigned long entry_size = 0; + unsigned char buf[0]; + bfd_sym_data_struct *sdata = NULL; + + parser = NULL; + BFD_ASSERT (bfd_sym_valid (abfd)); + sdata = abfd->tdata.sym_data; + + if (index == 0) + return -1; + + switch (sdata->version) + { + case BFD_SYM_VERSION_3_3: + case BFD_SYM_VERSION_3_2: + entry_size = 0; + parser = NULL; + break; + + case BFD_SYM_VERSION_3_5: + case BFD_SYM_VERSION_3_4: + case BFD_SYM_VERSION_3_1: + default: + break; + } + + if (parser == NULL) + return -1; + + offset = compute_offset (sdata->header.dshb_fite.dti_first_page, + sdata->header.dshb_page_size, + entry_size, index); + + if (bfd_seek (abfd, offset, SEEK_SET) < 0) + return -1; + if (bfd_bread (buf, entry_size, abfd) != entry_size) + return -1; + + (*parser) (buf, entry_size, entry); + + return 0; +} + +int +bfd_sym_fetch_type_table_entry (abfd, entry, index) + bfd *abfd; + bfd_sym_type_table_entry *entry; + unsigned long index; +{ + void (*parser) PARAMS ((unsigned char *, size_t, + bfd_sym_type_table_entry *)); + unsigned long offset; + unsigned long entry_size = 0; + unsigned char buf[4]; + bfd_sym_data_struct *sdata = NULL; + + parser = NULL; + BFD_ASSERT (bfd_sym_valid (abfd)); + sdata = abfd->tdata.sym_data; + + switch (sdata->version) + { + case BFD_SYM_VERSION_3_3: + case BFD_SYM_VERSION_3_2: + entry_size = 4; + parser = bfd_sym_parse_type_table_entry_v32; + break; + + case BFD_SYM_VERSION_3_5: + case BFD_SYM_VERSION_3_4: + case BFD_SYM_VERSION_3_1: + default: + break; + } + + if (parser == NULL) + return -1; + + offset = compute_offset (sdata->header.dshb_tte.dti_first_page, + sdata->header.dshb_page_size, + entry_size, index); + + if (bfd_seek (abfd, offset, SEEK_SET) < 0) + return -1; + if (bfd_bread (buf, entry_size, abfd) != entry_size) + return -1; + + (*parser) (buf, entry_size, entry); + + return 0; +} + +int +bfd_sym_fetch_type_information_table_entry (abfd, entry, offset) + bfd *abfd; + bfd_sym_type_information_table_entry *entry; + unsigned long offset; +{ + unsigned char buf[4]; + bfd_sym_data_struct *sdata = NULL; + + BFD_ASSERT (bfd_sym_valid (abfd)); + sdata = abfd->tdata.sym_data; + + if (offset == 0) + return -1; + + if (bfd_seek (abfd, offset, SEEK_SET) < 0) + return -1; + + if (bfd_bread (buf, 4, abfd) != 4) + return -1; + entry->nte_index = bfd_getb32 (buf); + + if (bfd_bread (buf, 2, abfd) != 2) + return -1; + entry->physical_size = bfd_getb16 (buf); + + if (entry->physical_size & 0x8000) + { + if (bfd_bread (buf, 4, abfd) != 4) + return -1; + entry->physical_size &= 0x7fff; + entry->logical_size = bfd_getb32 (buf); + entry->offset = offset + 10; + } + else + { + if (bfd_bread (buf, 2, abfd) != 2) + return -1; + entry->physical_size &= 0x7fff; + entry->logical_size = bfd_getb16 (buf); + entry->offset = offset + 8; + } + + return 0; +} + +int +bfd_sym_fetch_type_table_information (abfd, entry, index) + bfd *abfd; + bfd_sym_type_information_table_entry *entry; + unsigned long index; +{ + bfd_sym_type_table_entry tindex; + bfd_sym_data_struct *sdata = NULL; + + BFD_ASSERT (bfd_sym_valid (abfd)); + sdata = abfd->tdata.sym_data; + + if (sdata->header.dshb_tte.dti_object_count <= 99) + return -1; + if (index < 100) + return -1; + + if (bfd_sym_fetch_type_table_entry (abfd, &tindex, index - 100) < 0) + return -1; + if (bfd_sym_fetch_type_information_table_entry (abfd, entry, tindex) < 0) + return -1; + + return 0; +} + +const unsigned char * +bfd_sym_symbol_name (abfd, index) + bfd *abfd; + unsigned long index; +{ + bfd_sym_data_struct *sdata = NULL; + + BFD_ASSERT (bfd_sym_valid (abfd)); + sdata = abfd->tdata.sym_data; + + if (index == 0) + return ""; + + index *= 2; + if ((index / sdata->header.dshb_page_size) + > sdata->header.dshb_nte.dti_page_count) + return "\009[INVALID]"; + + return (const unsigned char *) sdata->name_table + index; +} + +const unsigned char * +bfd_sym_module_name (abfd, index) + bfd *abfd; + unsigned long index; +{ + bfd_sym_modules_table_entry entry; + + if (bfd_sym_fetch_modules_table_entry (abfd, &entry, index) < 0) + return "\011[INVALID]"; + + return bfd_sym_symbol_name (abfd, entry.mte_nte_index); +} + +const char * +bfd_sym_unparse_storage_kind (kind) + enum bfd_sym_storage_kind kind; +{ + switch (kind) + { + case BFD_SYM_STORAGE_KIND_LOCAL: return "LOCAL"; + case BFD_SYM_STORAGE_KIND_VALUE: return "VALUE"; + case BFD_SYM_STORAGE_KIND_REFERENCE: return "REFERENCE"; + case BFD_SYM_STORAGE_KIND_WITH: return "WITH"; + default: return "[UNKNOWN]"; + } +} + +const char * +bfd_sym_unparse_storage_class (kind) + enum bfd_sym_storage_class kind; +{ + switch (kind) + { + case BFD_SYM_STORAGE_CLASS_REGISTER: return "REGISTER"; + case BFD_SYM_STORAGE_CLASS_GLOBAL: return "GLOBAL"; + case BFD_SYM_STORAGE_CLASS_FRAME_RELATIVE: return "FRAME_RELATIVE"; + case BFD_SYM_STORAGE_CLASS_STACK_RELATIVE: return "STACK_RELATIVE"; + case BFD_SYM_STORAGE_CLASS_ABSOLUTE: return "ABSOLUTE"; + case BFD_SYM_STORAGE_CLASS_CONSTANT: return "CONSTANT"; + case BFD_SYM_STORAGE_CLASS_RESOURCE: return "RESOURCE"; + case BFD_SYM_STORAGE_CLASS_BIGCONSTANT: return "BIGCONSTANT"; + default: return "[UNKNOWN]"; + } +} + +const char * +bfd_sym_unparse_module_kind (kind) + enum bfd_sym_module_kind kind; +{ + switch (kind) + { + case BFD_SYM_MODULE_KIND_NONE: return "NONE"; + case BFD_SYM_MODULE_KIND_PROGRAM: return "PROGRAM"; + case BFD_SYM_MODULE_KIND_UNIT: return "UNIT"; + case BFD_SYM_MODULE_KIND_PROCEDURE: return "PROCEDURE"; + case BFD_SYM_MODULE_KIND_FUNCTION: return "FUNCTION"; + case BFD_SYM_MODULE_KIND_DATA: return "DATA"; + case BFD_SYM_MODULE_KIND_BLOCK: return "BLOCK"; + default: return "[UNKNOWN]"; + } +} + +const char * +bfd_sym_unparse_symbol_scope (scope) + enum bfd_sym_symbol_scope scope; +{ + switch (scope) + { + case BFD_SYM_SYMBOL_SCOPE_LOCAL: return "LOCAL"; + case BFD_SYM_SYMBOL_SCOPE_GLOBAL: return "GLOBAL"; + default: + return "[UNKNOWN]"; + } +} + +void +bfd_sym_print_file_reference (abfd, f, entry) + bfd *abfd; + FILE *f; + bfd_sym_file_reference *entry; +{ + bfd_sym_file_references_table_entry frtentry; + int ret; + + ret = bfd_sym_fetch_file_references_table_entry (abfd, &frtentry, + entry->fref_frte_index); + fprintf (f, "FILE "); + + if ((ret < 0) || (frtentry.generic.type != BFD_SYM_FILE_NAME_INDEX)) + fprintf (f, "[INVALID]"); + else + fprintf (f, "\"%.*s\"", + bfd_sym_symbol_name (abfd, frtentry.filename.nte_index)[0], + &bfd_sym_symbol_name (abfd, frtentry.filename.nte_index)[1]); + + fprintf (f, " (FRTE %lu)", entry->fref_frte_index); +} + +void +bfd_sym_print_resources_table_entry (abfd, f, entry) + bfd *abfd; + FILE *f; + bfd_sym_resources_table_entry *entry; +{ + fprintf (f, " \"%.*s\" (NTE %lu), type \"%.4s\", num %u, size %lu, MTE %lu -- %lu", + bfd_sym_symbol_name (abfd, entry->rte_nte_index)[0], + &bfd_sym_symbol_name (abfd, entry->rte_nte_index)[1], + entry->rte_nte_index, entry->rte_res_type, entry->rte_res_number, + entry->rte_res_size, entry->rte_mte_first, entry->rte_mte_last); +} + +void +bfd_sym_print_modules_table_entry (abfd, f, entry) + bfd *abfd; + FILE *f; + bfd_sym_modules_table_entry *entry; +{ + fprintf (f, "\"%.*s\" (NTE %lu)", + bfd_sym_symbol_name (abfd, entry->mte_nte_index)[0], + &bfd_sym_symbol_name (abfd, entry->mte_nte_index)[1], + entry->mte_nte_index); + + fprintf (f, "\n "); + + bfd_sym_print_file_reference (abfd, f, &entry->mte_imp_fref); + fprintf (f, " range %lu -- %lu", + entry->mte_imp_fref.fref_offset, entry->mte_imp_end); + + fprintf (f, "\n "); + + fprintf (f, "kind %s", bfd_sym_unparse_module_kind (entry->mte_kind)); + fprintf (f, ", scope %s", bfd_sym_unparse_symbol_scope (entry->mte_scope)); + + fprintf (f, ", RTE %lu, offset %lu, size %lu", + entry->mte_rte_index, entry->mte_res_offset, entry->mte_size); + + fprintf (f, "\n "); + + fprintf (f, "CMTE %lu, CVTE %lu, CLTE %lu, CTTE %lu, CSNTE1 %lu, CSNTE2 %lu", + entry->mte_cmte_index, entry->mte_cvte_index, + entry->mte_clte_index, entry->mte_ctte_index, + entry->mte_csnte_idx_1, entry->mte_csnte_idx_2); + + if (entry->mte_parent != 0) + fprintf (f, ", parent %lu", entry->mte_parent); + else + fprintf (f, ", no parent"); + + if (entry->mte_cmte_index != 0) + fprintf (f, ", child %lu", entry->mte_cmte_index); + else + fprintf (f, ", no child"); + +#if 0 + { + MTE bfd_sym_modules_table_entry pentry; + + ret = bfd_sym_fetch_modules_table_entry (abfd, &pentry, entry->mte_parent); + if (ret < 0) + fprintf (f, " parent MTE %lu [INVALID]\n", entry->mte_parent); + else + fprintf (f, " parent MTE %lu \"%.*s\"\n", + entry->mte_parent, + bfd_sym_symbol_name (abfd, pentry.mte_nte_index)[0], + &bfd_sym_symbol_name (abfd, pentry.mte_nte_index)[1]); + } +#endif +} + +void +bfd_sym_print_file_references_table_entry (abfd, f, entry) + bfd *abfd; + FILE *f; + bfd_sym_file_references_table_entry *entry; +{ + switch (entry->generic.type) + { + case BFD_SYM_FILE_NAME_INDEX: + fprintf (f, "FILE \"%.*s\" (NTE %lu), modtime ", + bfd_sym_symbol_name (abfd, entry->filename.nte_index)[0], + &bfd_sym_symbol_name (abfd, entry->filename.nte_index)[1], + entry->filename.nte_index); + + fprintf (f, "[UNIMPLEMENTED]"); + /* printModDate (entry->filename.mod_date); */ + fprintf (f, " (0x%lx)", entry->filename.mod_date); + break; + + case BFD_SYM_END_OF_LIST: + fprintf (f, "END"); + break; + + default: + fprintf (f, "\"%.*s\" (MTE %lu), offset %lu", + bfd_sym_module_name (abfd, entry->entry.mte_index)[0], + &bfd_sym_module_name (abfd, entry->entry.mte_index)[1], + entry->entry.mte_index, + entry->entry.file_offset); + break; + } +} + +void +bfd_sym_print_contained_modules_table_entry (abfd, f, entry) + bfd *abfd; + FILE *f; + bfd_sym_contained_modules_table_entry *entry; +{ + switch (entry->generic.type) + { + case BFD_SYM_END_OF_LIST: + fprintf (f, "END"); + break; + + default: + fprintf (f, "\"%.*s\" (MTE %lu, NTE %lu)", + bfd_sym_module_name (abfd, entry->entry.mte_index)[0], + &bfd_sym_module_name (abfd, entry->entry.mte_index)[1], + entry->entry.mte_index, + entry->entry.nte_index); + break; + } +} + +void +bfd_sym_print_contained_variables_table_entry (abfd, f, entry) + bfd *abfd; + FILE *f; + bfd_sym_contained_variables_table_entry *entry; +{ + if (entry->generic.type == BFD_SYM_END_OF_LIST) + { + fprintf (f, "END"); + return; + } + + if (entry->generic.type == BFD_SYM_SOURCE_FILE_CHANGE) + { + bfd_sym_print_file_reference (abfd, f, &entry->file.fref); + fprintf (f, " offset %lu", entry->file.fref.fref_offset); + return; + } + + fprintf (f, "\"%.*s\" (NTE %lu)", + bfd_sym_symbol_name (abfd, entry->entry.nte_index)[0], + &bfd_sym_symbol_name (abfd, entry->entry.nte_index)[1], + entry->entry.nte_index); + + fprintf (f, ", TTE %lu", entry->entry.tte_index); + fprintf (f, ", offset %lu", entry->entry.file_delta); + fprintf (f, ", scope %s", bfd_sym_unparse_symbol_scope (entry->entry.scope)); + + if (entry->entry.la_size == BFD_SYM_CVTE_SCA) + fprintf (f, ", latype %s, laclass %s, laoffset %lu", + bfd_sym_unparse_storage_kind (entry->entry.address.scstruct.sca_kind), + bfd_sym_unparse_storage_class (entry->entry.address.scstruct.sca_class), + entry->entry.address.scstruct.sca_offset); + else if (entry->entry.la_size <= BFD_SYM_CVTE_LA_MAX_SIZE) + { + unsigned long i; + + fprintf (f, ", la ["); + for (i = 0; i < entry->entry.la_size; i++) + fprintf (f, "0x%02x ", entry->entry.address.lastruct.la[i]); + fprintf (f, "]"); + } + else if (entry->entry.la_size == BFD_SYM_CVTE_BIG_LA) + fprintf (f, ", bigla %lu, biglakind %u", + entry->entry.address.biglastruct.big_la, + entry->entry.address.biglastruct.big_la_kind); + + else + fprintf (f, ", la [INVALID]"); +} + +void +bfd_sym_print_contained_statements_table_entry (abfd, f, entry) + bfd *abfd; + FILE *f; + bfd_sym_contained_statements_table_entry *entry; +{ + if (entry->generic.type == BFD_SYM_END_OF_LIST) + { + fprintf (f, "END"); + return; + } + + if (entry->generic.type == BFD_SYM_SOURCE_FILE_CHANGE) + { + bfd_sym_print_file_reference (abfd, f, &entry->file.fref); + fprintf (f, " offset %lu", entry->file.fref.fref_offset); + return; + } + + fprintf (f, "\"%.*s\" (MTE %lu), offset %lu, delta %lu", + bfd_sym_module_name (abfd, entry->entry.mte_index)[0], + &bfd_sym_module_name (abfd, entry->entry.mte_index)[1], + entry->entry.mte_index, + entry->entry.mte_offset, + entry->entry.file_delta); +} + +void +bfd_sym_print_contained_labels_table_entry (abfd, f, entry) + bfd *abfd; + FILE *f; + bfd_sym_contained_labels_table_entry *entry; +{ + if (entry->generic.type == BFD_SYM_END_OF_LIST) + { + fprintf (f, "END"); + return; + } + + if (entry->generic.type == BFD_SYM_SOURCE_FILE_CHANGE) + { + bfd_sym_print_file_reference (abfd, f, &entry->file.fref); + fprintf (f, " offset %lu", entry->file.fref.fref_offset); + return; + } + + fprintf (f, "\"%.*s\" (MTE %lu), offset %lu, delta %lu, scope %s", + bfd_sym_module_name (abfd, entry->entry.mte_index)[0], + &bfd_sym_module_name (abfd, entry->entry.mte_index)[1], + entry->entry.mte_index, + entry->entry.mte_offset, + entry->entry.file_delta, + bfd_sym_unparse_symbol_scope (entry->entry.scope)); +} + +void +bfd_sym_print_contained_types_table_entry (abfd, f, entry) + bfd *abfd ATTRIBUTE_UNUSED; + FILE *f; + bfd_sym_contained_types_table_entry *entry ATTRIBUTE_UNUSED; +{ + fprintf (f, "[UNIMPLEMENTED]"); +} + +const char * +bfd_sym_type_operator_name (num) + unsigned char num; +{ + switch (num) + { + case 1: return "TTE"; + case 2: return "PointerTo"; + case 3: return "ScalarOf"; + case 4: return "ConstantOf"; + case 5: return "EnumerationOf"; + case 6: return "VectorOf"; + case 7: return "RecordOf"; + case 8: return "UnionOf"; + case 9: return "SubRangeOf"; + case 10: return "SetOf"; + case 11: return "NamedTypeOf"; + case 12: return "ProcOf"; + case 13: return "ValueOf"; + case 14: return "ArrayOf"; + default: return "[UNKNOWN OPERATOR]"; + } +} + +const char * +bfd_sym_type_basic_name (num) + unsigned char num; +{ + switch (num) + { + case 0: return "void"; + case 1: return "pascal string"; + case 2: return "unsigned long"; + case 3: return "signed long"; + case 4: return "extended (10 bytes)"; + case 5: return "pascal boolean (1 byte)"; + case 6: return "unsigned byte"; + case 7: return "signed byte"; + case 8: return "character (1 byte)"; + case 9: return "wide character (2 bytes)"; + case 10: return "unsigned short"; + case 11: return "signed short"; + case 12: return "singled"; + case 13: return "double"; + case 14: return "extended (12 bytes)"; + case 15: return "computational (8 bytes)"; + case 16: return "c string"; + case 17: return "as-is string"; + default: return "[UNKNOWN BASIC TYPE]"; + } +} + +int +bfd_sym_fetch_long (buf, len, offset, offsetptr, value) + unsigned char *buf; + unsigned long len; + unsigned long offset; + unsigned long *offsetptr; + long *value; +{ + int ret; + + if (offset >= len) + { + *value = 0; + offset += 0; + ret = -1; + } + else if (! (buf[offset] & 0x80)) + { + *value = buf[offset]; + offset += 1; + ret = 0; + } + else if (buf[offset] == 0xc0) + { + if ((offset + 5) > len) + { + *value = 0; + offset = len; + ret = -1; + } + else + { + *value = bfd_getb32 (buf + offset + 1); + offset += 5; + ret = 0; + } + } + else if ((buf[offset] & 0xc0) == 0xc0) + { + *value = -(buf[offset] & 0x3f); + offset += 1; + ret = 0; + } + else if ((buf[offset] & 0xc0) == 0x80) + { + if ((offset + 2) > len) + { + *value = 0; + offset = len; + ret = -1; + } + else + { + *value = bfd_getb16 (buf + offset) & 0x3fff; + offset += 2; + ret = 0; + } + } + else + abort (); + + if (offsetptr != NULL) + *offsetptr = offset; + + return ret; +} + +void +bfd_sym_print_type_information (abfd, f, buf, len, offset, offsetptr) + bfd *abfd; + FILE *f; + unsigned char *buf; + unsigned long len; + unsigned long offset; + unsigned long *offsetptr; +{ + unsigned int type; + + if (offset >= len) + { + fprintf (f, "[NULL]"); + + if (offsetptr != NULL) + *offsetptr = offset; + return; + } + + type = buf[offset]; + offset++; + + if (! (type & 0x80)) + { + fprintf (f, "[%s] (0x%x)", bfd_sym_type_basic_name (type & 0x7f), type); + + if (offsetptr != NULL) + *offsetptr = offset; + return; + } + + if (type & 0x40) + fprintf (f, "[packed "); + else + fprintf (f, "["); + + switch (type & 0x3f) + { + case 1: + { + long value; + bfd_sym_type_information_table_entry tinfo; + + bfd_sym_fetch_long (buf, len, offset, &offset, &value); + if (value <= 0) + fprintf (f, "[INVALID]"); + else + { + if (bfd_sym_fetch_type_table_information (abfd, &tinfo, value) < 0) + fprintf (f, "[INVALID]"); + else + fprintf (f, "\"%.*s\"", + bfd_sym_symbol_name (abfd, tinfo.nte_index)[0], + &bfd_sym_symbol_name (abfd, tinfo.nte_index)[1]); + } + fprintf (f, " (TTE %lu)", value); + break; + } + + case 2: + fprintf (f, "pointer (0x%x) to ", type); + bfd_sym_print_type_information (abfd, f, buf, len, offset, &offset); + break; + + case 3: + { + unsigned long value; + + fprintf (f, "scalar (0x%x) of ", type); + bfd_sym_print_type_information (abfd, f, buf, len, offset, &offset); + bfd_sym_fetch_long (buf, len, offset, &offset, &value); + fprintf (f, " (%lu)", value); + break; + } + + case 5: + { + unsigned long lower, upper, nelem; + unsigned long i; + + fprintf (f, "enumeration (0x%x) of ", type); + bfd_sym_print_type_information (abfd, f, buf, len, offset, &offset); + bfd_sym_fetch_long (buf, len, offset, &offset, &lower); + bfd_sym_fetch_long (buf, len, offset, &offset, &upper); + bfd_sym_fetch_long (buf, len, offset, &offset, &nelem); + fprintf (f, " from %lu to %lu with %lu elements: ", lower, upper, nelem); + + for (i = 0; i < nelem; i++) + { + fprintf (f, "\n "); + bfd_sym_print_type_information (abfd, f, buf, len, offset, &offset); + } + break; + } + + case 6: + fprintf (f, "vector (0x%x)", type); + fprintf (f, "\n index "); + bfd_sym_print_type_information (abfd, f, buf, len, offset, &offset); + fprintf (f, "\n target "); + bfd_sym_print_type_information (abfd, f, buf, len, offset, &offset); + break; + + case 7: + case 8: + { + long nrec, eloff, i; + + if ((type & 0x3f) == 7) + fprintf (f, "record (0x%x) of ", type); + else + fprintf (f, "union (0x%x) of ", type); + + bfd_sym_fetch_long (buf, len, offset, &offset, &nrec); + fprintf (f, "%lu elements: ", nrec); + + for (i = 0; i < nrec; i++) + { + bfd_sym_fetch_long (buf, len, offset, &offset, &eloff); + fprintf (f, "\n "); + fprintf (f, "offset %lu: ", eloff); + bfd_sym_print_type_information (abfd, f, buf, len, offset, &offset); + } + break; + } + + case 9: + fprintf (f, "subrange (0x%x) of ", type); + bfd_sym_print_type_information (abfd, f, buf, len, offset, &offset); + fprintf (f, " lower "); + bfd_sym_print_type_information (abfd, f, buf, len, offset, &offset); + fprintf (f, " upper "); + bfd_sym_print_type_information (abfd, f, buf, len, offset, &offset); + break; + + case 11: + { + long value; + + fprintf (f, "named type (0x%x) ", type); + bfd_sym_fetch_long (buf, len, offset, &offset, &value); + if (value <= 0) + fprintf (f, "[INVALID]"); + else + fprintf (f, "\"%.*s\"", + bfd_sym_symbol_name (abfd, value)[0], + &bfd_sym_symbol_name (abfd, value)[1]); + + fprintf (f, " (NTE %lu) with type ", value); + bfd_sym_print_type_information (abfd, f, buf, len, offset, &offset); + break; + } + + default: + fprintf (f, "%s (0x%x)", bfd_sym_type_operator_name (type), type); + break; + } + + if (type == (0x40 | 0x6)) + { + /* Vector. */ + long n, width, m; + long l; + long i; + + bfd_sym_fetch_long (buf, len, offset, &offset, &n); + bfd_sym_fetch_long (buf, len, offset, &offset, &width); + bfd_sym_fetch_long (buf, len, offset, &offset, &m); + /* fprintf (f, "\n "); */ + fprintf (f, " N %ld, width %ld, M %ld, ", n, width, m); + for (i = 0; i < m; i++) + { + bfd_sym_fetch_long (buf, len, offset, &offset, &l); + if (i != 0) + fprintf (f, " "); + fprintf (f, "%ld", l); + } + } + else if (type & 0x40) + { + /* Other packed type. */ + long msb, lsb; + + bfd_sym_fetch_long (buf, len, offset, &offset, &msb); + bfd_sym_fetch_long (buf, len, offset, &offset, &lsb); + /* fprintf (f, "\n "); */ + fprintf (f, " msb %ld, lsb %ld", msb, lsb); + } + + fprintf (f, "]"); + + if (offsetptr != NULL) + *offsetptr = offset; +} + +void +bfd_sym_print_type_information_table_entry (abfd, f, entry) + bfd *abfd; + FILE *f; + bfd_sym_type_information_table_entry *entry; +{ + unsigned char *buf; + unsigned long offset; + unsigned int i; + + fprintf (f, "\"%.*s\" (NTE %lu), %lu bytes at %lu, logical size %lu", + bfd_sym_symbol_name (abfd, entry->nte_index)[0], + &bfd_sym_symbol_name (abfd, entry->nte_index)[1], + entry->nte_index, + entry->physical_size, entry->offset, entry->logical_size); + + fprintf (f, "\n "); + + buf = alloca (entry->physical_size); + if (buf == NULL) + { + fprintf (f, "[ERROR]\n"); + return; + } + if (bfd_seek (abfd, entry->offset, SEEK_SET) < 0) + { + fprintf (f, "[ERROR]\n"); + return; + } + if (bfd_bread (buf, entry->physical_size, abfd) != entry->physical_size) + { + fprintf (f, "[ERROR]\n"); + return; + } + + fprintf (f, "["); + for (i = 0; i < entry->physical_size; i++) + { + if (i == 0) + fprintf (f, "0x%02x", buf[i]); + else + fprintf (f, " 0x%02x", buf[i]); + } + + fprintf (f, "]"); + fprintf (f, "\n "); + + bfd_sym_print_type_information (abfd, f, buf, entry->physical_size, 0, &offset); + + if (offset != entry->physical_size) + fprintf (f, "\n [parser used %lu bytes instead of %lu]", offset, entry->physical_size); } + +void +bfd_sym_print_file_references_index_table_entry (abfd, f, entry) + bfd *abfd ATTRIBUTE_UNUSED; + FILE *f; + bfd_sym_file_references_index_table_entry *entry ATTRIBUTE_UNUSED; +{ + fprintf (f, "[UNIMPLEMENTED]"); +} + +void +bfd_sym_print_constant_pool_entry (abfd, f, entry) + bfd *abfd ATTRIBUTE_UNUSED; + FILE *f; + bfd_sym_constant_pool_entry *entry ATTRIBUTE_UNUSED; +{ + fprintf (f, "[UNIMPLEMENTED]"); +} + +unsigned char * +bfd_sym_display_name_table_entry (abfd, f, entry) + bfd *abfd; + FILE *f; + unsigned char *entry; +{ + unsigned long index; + unsigned long offset; + bfd_sym_data_struct *sdata = NULL; + + BFD_ASSERT (bfd_sym_valid (abfd)); + sdata = abfd->tdata.sym_data; + index = (entry - sdata->name_table) / 2; + + if (sdata->version >= BFD_SYM_VERSION_3_4 && entry[0] == 255 && entry[1] == 0) + { + unsigned short length = bfd_getb16 (entry + 2); + fprintf (f, "[%8lu] \"%.*s\"\n", index, length, entry + 4); + offset = 2 + length + 1; + } + else + { + if (! (entry[0] == 0 || (entry[0] == 1 && entry[1] == '\0'))) + fprintf (f, "[%8lu] \"%.*s\"\n", index, entry[0], entry + 1); + + if (sdata->version >= BFD_SYM_VERSION_3_4) + offset = entry[0] + 2; + else + offset = entry[0] + 1; + } + + return (entry + offset + (offset % 2)); +} + +void +bfd_sym_display_name_table (abfd, f) + bfd *abfd; + FILE *f; +{ + unsigned long name_table_len; + unsigned char *name_table, *name_table_end, *cur; + bfd_sym_data_struct *sdata = NULL; + + BFD_ASSERT (bfd_sym_valid (abfd)); + sdata = abfd->tdata.sym_data; + + name_table_len = sdata->header.dshb_nte.dti_page_count * sdata->header.dshb_page_size; + name_table = sdata->name_table; + name_table_end = name_table + name_table_len; + + fprintf (f, "name table (NTE) contains %lu bytes:\n\n", name_table_len); + + cur = name_table; + for (;;) + { + cur = bfd_sym_display_name_table_entry (abfd, f, cur); + if (cur >= name_table_end) + break; + } +} + +void +bfd_sym_display_resources_table (abfd, f) + bfd *abfd; + FILE *f; +{ + unsigned long i; + bfd_sym_resources_table_entry entry; + bfd_sym_data_struct *sdata = NULL; + + BFD_ASSERT (bfd_sym_valid (abfd)); + sdata = abfd->tdata.sym_data; + + fprintf (f, "resource table (RTE) contains %lu objects:\n\n", + sdata->header.dshb_rte.dti_object_count); + + for (i = 1; i <= sdata->header.dshb_rte.dti_object_count; i++) + { + if (bfd_sym_fetch_resources_table_entry (abfd, &entry, i) < 0) + fprintf (f, " [%8lu] [INVALID]\n", i); + else + { + fprintf (f, " [%8lu] ", i); + bfd_sym_print_resources_table_entry (abfd, f, &entry); + fprintf (f, "\n"); + } + } +} + +void +bfd_sym_display_modules_table (abfd, f) + bfd *abfd; + FILE *f; +{ + unsigned long i; + bfd_sym_modules_table_entry entry; + bfd_sym_data_struct *sdata = NULL; + + BFD_ASSERT (bfd_sym_valid (abfd)); + sdata = abfd->tdata.sym_data; + + fprintf (f, "module table (MTE) contains %lu objects:\n\n", + sdata->header.dshb_mte.dti_object_count); + + for (i = 1; i <= sdata->header.dshb_mte.dti_object_count; i++) + { + if (bfd_sym_fetch_modules_table_entry (abfd, &entry, i) < 0) + fprintf (f, " [%8lu] [INVALID]\n", i); + else + { + fprintf (f, " [%8lu] ", i); + bfd_sym_print_modules_table_entry (abfd, f, &entry); + fprintf (f, "\n"); + } + } +} + +void +bfd_sym_display_file_references_table (abfd, f) + bfd *abfd; + FILE *f; +{ + unsigned long i; + bfd_sym_file_references_table_entry entry; + bfd_sym_data_struct *sdata = NULL; + + BFD_ASSERT (bfd_sym_valid (abfd)); + sdata = abfd->tdata.sym_data; + + fprintf (f, "file reference table (FRTE) contains %lu objects:\n\n", + sdata->header.dshb_frte.dti_object_count); + + for (i = 1; i <= sdata->header.dshb_frte.dti_object_count; i++) + { + if (bfd_sym_fetch_file_references_table_entry (abfd, &entry, i) < 0) + fprintf (f, " [%8lu] [INVALID]\n", i); + else + { + fprintf (f, " [%8lu] ", i); + bfd_sym_print_file_references_table_entry (abfd, f, &entry); + fprintf (f, "\n"); + } + } +} + +void +bfd_sym_display_contained_modules_table (abfd, f) + bfd *abfd; + FILE *f; +{ + unsigned long i; + bfd_sym_contained_modules_table_entry entry; + bfd_sym_data_struct *sdata = NULL; + + BFD_ASSERT (bfd_sym_valid (abfd)); + sdata = abfd->tdata.sym_data; + + fprintf (f, "contained modules table (CMTE) contains %lu objects:\n\n", + sdata->header.dshb_cmte.dti_object_count); + + for (i = 1; i <= sdata->header.dshb_cmte.dti_object_count; i++) + { + if (bfd_sym_fetch_contained_modules_table_entry (abfd, &entry, i) < 0) + fprintf (f, " [%8lu] [INVALID]\n", i); + else + { + fprintf (f, " [%8lu] ", i); + bfd_sym_print_contained_modules_table_entry (abfd, f, &entry); + fprintf (f, "\n"); + } + } +} + +void +bfd_sym_display_contained_variables_table (abfd, f) + bfd *abfd; + FILE *f; +{ + unsigned long i; + bfd_sym_contained_variables_table_entry entry; + bfd_sym_data_struct *sdata = NULL; + + BFD_ASSERT (bfd_sym_valid (abfd)); + sdata = abfd->tdata.sym_data; + + fprintf (f, "contained variables table (CVTE) contains %lu objects:\n\n", + sdata->header.dshb_cvte.dti_object_count); + + for (i = 1; i <= sdata->header.dshb_cvte.dti_object_count; i++) + { + if (bfd_sym_fetch_contained_variables_table_entry (abfd, &entry, i) < 0) + fprintf (f, " [%8lu] [INVALID]\n", i); + else + { + fprintf (f, " [%8lu] ", i); + bfd_sym_print_contained_variables_table_entry (abfd, f, &entry); + fprintf (f, "\n"); + } + } + + fprintf (f, "\n"); +} + +void +bfd_sym_display_contained_statements_table (abfd, f) + bfd *abfd; + FILE *f; +{ + unsigned long i; + bfd_sym_contained_statements_table_entry entry; + bfd_sym_data_struct *sdata = NULL; + + BFD_ASSERT (bfd_sym_valid (abfd)); + sdata = abfd->tdata.sym_data; + + fprintf (f, "contained statements table (CSNTE) contains %lu objects:\n\n", + sdata->header.dshb_csnte.dti_object_count); + + for (i = 1; i <= sdata->header.dshb_csnte.dti_object_count; i++) + { + if (bfd_sym_fetch_contained_statements_table_entry (abfd, &entry, i) < 0) + fprintf (f, " [%8lu] [INVALID]\n", i); + else + { + fprintf (f, " [%8lu] ", i); + bfd_sym_print_contained_statements_table_entry (abfd, f, &entry); + fprintf (f, "\n"); + } + } +} + +void +bfd_sym_display_contained_labels_table (abfd, f) + bfd *abfd; + FILE *f; +{ + unsigned long i; + bfd_sym_contained_labels_table_entry entry; + bfd_sym_data_struct *sdata = NULL; + + BFD_ASSERT (bfd_sym_valid (abfd)); + sdata = abfd->tdata.sym_data; + + fprintf (f, "contained labels table (CLTE) contains %lu objects:\n\n", + sdata->header.dshb_clte.dti_object_count); + + for (i = 1; i <= sdata->header.dshb_clte.dti_object_count; i++) + { + if (bfd_sym_fetch_contained_labels_table_entry (abfd, &entry, i) < 0) + fprintf (f, " [%8lu] [INVALID]\n", i); + else + { + fprintf (f, " [%8lu] ", i); + bfd_sym_print_contained_labels_table_entry (abfd, f, &entry); + fprintf (f, "\n"); + } + } +} + +void +bfd_sym_display_contained_types_table (abfd, f) + bfd *abfd; + FILE *f; +{ + unsigned long i; + bfd_sym_contained_types_table_entry entry; + bfd_sym_data_struct *sdata = NULL; + + BFD_ASSERT (bfd_sym_valid (abfd)); + sdata = abfd->tdata.sym_data; + + fprintf (f, "contained types table (CTTE) contains %lu objects:\n\n", + sdata->header.dshb_ctte.dti_object_count); + + for (i = 1; i <= sdata->header.dshb_ctte.dti_object_count; i++) + { + if (bfd_sym_fetch_contained_types_table_entry (abfd, &entry, i) < 0) + fprintf (f, " [%8lu] [INVALID]\n", i); + else + { + fprintf (f, " [%8lu] ", i); + bfd_sym_print_contained_types_table_entry (abfd, f, &entry); + fprintf (f, "\n"); + } + } +} + +void +bfd_sym_display_file_references_index_table (abfd, f) + bfd *abfd; + FILE *f; +{ + unsigned long i; + bfd_sym_file_references_index_table_entry entry; + bfd_sym_data_struct *sdata = NULL; + + BFD_ASSERT (bfd_sym_valid (abfd)); + sdata = abfd->tdata.sym_data; + + fprintf (f, "file references index table (FITE) contains %lu objects:\n\n", + sdata->header.dshb_fite.dti_object_count); + + for (i = 1; i <= sdata->header.dshb_fite.dti_object_count; i++) + { + if (bfd_sym_fetch_file_references_index_table_entry (abfd, &entry, i) < 0) + fprintf (f, " [%8lu] [INVALID]\n", i); + else + { + fprintf (f, " [%8lu] ", i); + bfd_sym_print_file_references_index_table_entry (abfd, f, &entry); + fprintf (f, "\n"); + } + } +} + +void +bfd_sym_display_constant_pool (abfd, f) + bfd *abfd; + FILE *f; +{ + unsigned long i; + bfd_sym_constant_pool_entry entry; + bfd_sym_data_struct *sdata = NULL; + + BFD_ASSERT (bfd_sym_valid (abfd)); + sdata = abfd->tdata.sym_data; + + fprintf (f, "constant pool (CONST) contains %lu objects:\n\n", + sdata->header.dshb_const.dti_object_count); + + for (i = 1; i <= sdata->header.dshb_const.dti_object_count; i++) + { + if (bfd_sym_fetch_constant_pool_entry (abfd, &entry, i) < 0) + fprintf (f, " [%8lu] [INVALID]\n", i); + else + { + fprintf (f, " [%8lu] ", i); + bfd_sym_print_constant_pool_entry (abfd, f, &entry); + fprintf (f, "\n"); + } + } +} + +void +bfd_sym_display_type_information_table (abfd, f) + bfd *abfd; + FILE *f; +{ + unsigned long i; + bfd_sym_type_table_entry index; + bfd_sym_type_information_table_entry entry; + bfd_sym_data_struct *sdata = NULL; + + BFD_ASSERT (bfd_sym_valid (abfd)); + sdata = abfd->tdata.sym_data; + + if (sdata->header.dshb_tte.dti_object_count > 99) + fprintf (f, "type table (TINFO) contains %lu objects:\n\n", + sdata->header.dshb_tte.dti_object_count - 99); + else + { + fprintf (f, "type table (TINFO) contains [INVALID] objects:\n\n"); + return; + } + + for (i = 100; i <= sdata->header.dshb_tte.dti_object_count; i++) + { + if (bfd_sym_fetch_type_table_entry (abfd, &index, i - 100) < 0) + fprintf (f, " [%8lu] [INVALID]\n", i); + else + { + fprintf (f, " [%8lu] (TINFO %lu) ", i, index); + + if (bfd_sym_fetch_type_information_table_entry (abfd, &entry, index) < 0) + fprintf (f, "[INVALID]"); + else + bfd_sym_print_type_information_table_entry (abfd, f, &entry); + + fprintf (f, "\n"); + } + } +} + +int +bfd_sym_scan (abfd, version, mdata) + bfd *abfd; + bfd_sym_version version; + bfd_sym_data_struct *mdata; +{ + asection *bfdsec; + const char *name = "symbols"; + + mdata->name_table = 0; + mdata->sbfd = abfd; + mdata->version = version; + + bfd_seek (abfd, 0, SEEK_SET); + if (bfd_sym_read_header (abfd, &mdata->header, mdata->version) != 0) + return -1; + + mdata->name_table = bfd_sym_read_name_table (abfd, &mdata->header); + if (mdata->name_table == NULL) + return -1; + + bfdsec = bfd_make_section_anyway (abfd, name); + if (bfdsec == NULL) + return -1; + + bfdsec->vma = 0; + bfdsec->lma = 0; + bfdsec->_raw_size = 0; + bfdsec->filepos = 0; + bfdsec->alignment_power = 0; + + bfdsec->flags = SEC_HAS_CONTENTS; + + abfd->tdata.sym_data = mdata; + + return 0; +} + +const bfd_target * +bfd_sym_object_p (abfd) + bfd *abfd; +{ + struct bfd_preserve preserve; + bfd_sym_version version = -1; + + preserve.marker = NULL; + bfd_seek (abfd, 0, SEEK_SET); + if (bfd_sym_read_version (abfd, &version) != 0) + goto wrong; + + preserve.marker = bfd_alloc (abfd, sizeof (bfd_sym_data_struct)); + if (preserve.marker == NULL + || ! bfd_preserve_save (abfd, &preserve)) + goto fail; + + if (bfd_sym_scan (abfd, version, + (bfd_sym_data_struct *) preserve.marker) != 0) + goto wrong; + + bfd_preserve_finish (abfd, &preserve); + return abfd->xvec; + + wrong: + bfd_set_error (bfd_error_wrong_format); + + fail: + if (preserve.marker != NULL) + bfd_preserve_restore (abfd, &preserve); + return NULL; +} + +asymbol * +bfd_sym_make_empty_symbol (abfd) + bfd *abfd; +{ + return (asymbol *) bfd_alloc (abfd, sizeof (asymbol)); +} + +void +bfd_sym_get_symbol_info (abfd, symbol, ret) + bfd *abfd ATTRIBUTE_UNUSED; + asymbol *symbol; + symbol_info *ret; +{ + bfd_symbol_info (symbol, ret); +} + +long +bfd_sym_get_symtab_upper_bound (abfd) + bfd *abfd ATTRIBUTE_UNUSED; +{ + return 0; +} + +long +bfd_sym_canonicalize_symtab (abfd, sym) + bfd *abfd ATTRIBUTE_UNUSED; + asymbol **sym ATTRIBUTE_UNUSED; +{ + return 0; +} + +int +bfd_sym_sizeof_headers (abfd, exec) + bfd *abfd ATTRIBUTE_UNUSED; + bfd_boolean exec ATTRIBUTE_UNUSED; +{ + return 0; +} + +const bfd_target sym_vec = +{ + "sym", /* name */ + bfd_target_sym_flavour, /* flavour */ + BFD_ENDIAN_BIG, /* byteorder */ + BFD_ENDIAN_BIG, /* header_byteorder */ + (HAS_RELOC | EXEC_P | /* object flags */ + HAS_LINENO | HAS_DEBUG | + HAS_SYMS | HAS_LOCALS | DYNAMIC | WP_TEXT | D_PAGED), + (SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_CODE | SEC_DATA + | SEC_ROM | SEC_HAS_CONTENTS), /* section_flags */ + 0, /* symbol_leading_char */ + ' ', /* ar_pad_char */ + 16, /* ar_max_namelen */ + bfd_getb64, bfd_getb_signed_64, bfd_putb64, + bfd_getb32, bfd_getb_signed_32, bfd_putb32, + bfd_getb16, bfd_getb_signed_16, bfd_putb16, /* data */ + bfd_getb64, bfd_getb_signed_64, bfd_putb64, + bfd_getb32, bfd_getb_signed_32, bfd_putb32, + bfd_getb16, bfd_getb_signed_16, bfd_putb16, /* hdrs */ + { /* bfd_check_format */ + _bfd_dummy_target, + bfd_sym_object_p, /* bfd_check_format */ + _bfd_dummy_target, + _bfd_dummy_target, + }, + { /* bfd_set_format */ + bfd_false, + bfd_sym_mkobject, + bfd_false, + bfd_false, + }, + { /* bfd_write_contents */ + bfd_false, + bfd_true, + bfd_false, + bfd_false, + }, + + BFD_JUMP_TABLE_GENERIC (bfd_sym), + BFD_JUMP_TABLE_COPY (_bfd_generic), + BFD_JUMP_TABLE_CORE (_bfd_nocore), + BFD_JUMP_TABLE_ARCHIVE (_bfd_noarchive), + BFD_JUMP_TABLE_SYMBOLS (bfd_sym), + BFD_JUMP_TABLE_RELOCS (bfd_sym), + BFD_JUMP_TABLE_WRITE (bfd_sym), + BFD_JUMP_TABLE_LINK (bfd_sym), + BFD_JUMP_TABLE_DYNAMIC (_bfd_nodynamic), + + NULL, + + NULL +}; + diff --git a/bfd/xsym.h b/bfd/xsym.h new file mode 100644 index 0000000..7b36467 --- /dev/null +++ b/bfd/xsym.h @@ -0,0 +1,701 @@ +/* xSYM symbol-file support for BFD. + Copyright 1999, 2000, 2001, 2002, 2003 + Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include "bfd.h" +#include + +#ifndef __xSYM_H__ +#define __xSYM_H__ + +#define BFD_SYM_VERSION_STR_3_1 "\013Version 3.1" +#define BFD_SYM_VERSION_STR_3_2 "\013Version 3.2" +#define BFD_SYM_VERSION_STR_3_3 "\013Version 3.3" +#define BFD_SYM_VERSION_STR_3_4 "\013Version 3.4" +#define BFD_SYM_VERSION_STR_3_5 "\013Version 3.5" +#define BFD_SYM_END_OF_LIST_3_2 0xffff +#define BFD_SYM_END_OF_LIST_3_4 0xffffffff +#define BFD_SYM_END_OF_LIST BFD_SYM_END_OF_LIST_3_4 +#define BFD_SYM_FILE_NAME_INDEX_3_2 0xfffe +#define BFD_SYM_FILE_NAME_INDEX_3_4 0xfffffffe +#define BFD_SYM_FILE_NAME_INDEX BFD_SYM_FILE_NAME_INDEX_3_4 +#define BFD_SYM_SOURCE_FILE_CHANGE_3_2 0xfffe +#define BFD_SYM_SOURCE_FILE_CHANGE_3_4 0xfffffffe +#define BFD_SYM_SOURCE_FILE_CHANGE BFD_SYM_SOURCE_FILE_CHANGE_3_4 +#define BFD_SYM_MAXIMUM_LEGAL_INDEX_3_2 0xfffd +#define BFD_SYM_MAXIMUM_LEGAL_INDEX_3_4 0xfffffffd +#define BFD_SYM_MAXIMUM_LEGAL_INDEX BFD_SYM_MAXIMUM_LEGAL_INDEX_3_4 + +enum bfd_sym_storage_class +{ + BFD_SYM_STORAGE_CLASS_REGISTER = 0, + BFD_SYM_STORAGE_CLASS_GLOBAL = 1, + BFD_SYM_STORAGE_CLASS_FRAME_RELATIVE = 2, + BFD_SYM_STORAGE_CLASS_STACK_RELATIVE = 3, + BFD_SYM_STORAGE_CLASS_ABSOLUTE = 4, + BFD_SYM_STORAGE_CLASS_CONSTANT = 5, + BFD_SYM_STORAGE_CLASS_BIGCONSTANT = 6, + BFD_SYM_STORAGE_CLASS_RESOURCE = 99 +}; +typedef enum bfd_sym_storage_class bfd_sym_storage_class; + +enum bfd_sym_storage_kind +{ + BFD_SYM_STORAGE_KIND_LOCAL = 0, + BFD_SYM_STORAGE_KIND_VALUE = 1, + BFD_SYM_STORAGE_KIND_REFERENCE = 2, + BFD_SYM_STORAGE_KIND_WITH = 3 +}; +typedef enum bfd_sym_storage_kind bfd_sym_storage_kind; + +enum bfd_sym_version +{ + BFD_SYM_VERSION_3_1, + BFD_SYM_VERSION_3_2, + BFD_SYM_VERSION_3_3, + BFD_SYM_VERSION_3_4, + BFD_SYM_VERSION_3_5 +}; +typedef enum bfd_sym_version bfd_sym_version; + +enum bfd_sym_module_kind +{ + BFD_SYM_MODULE_KIND_NONE = 0, + BFD_SYM_MODULE_KIND_PROGRAM = 1, + BFD_SYM_MODULE_KIND_UNIT = 2, + BFD_SYM_MODULE_KIND_PROCEDURE = 3, + BFD_SYM_MODULE_KIND_FUNCTION = 4, + BFD_SYM_MODULE_KIND_DATA = 5, + BFD_SYM_MODULE_KIND_BLOCK = 6 +}; +typedef enum bfd_sym_module_kind bfd_sym_module_kind; + +enum bfd_sym_symbol_scope +{ + BFD_SYM_SYMBOL_SCOPE_LOCAL = 0, /* Object is seen only inside current scope. */ + BFD_SYM_SYMBOL_SCOPE_GLOBAL = 1 /* Object has global scope. */ +}; +typedef enum bfd_sym_symbol_scope bfd_sym_symbol_scope; + +struct bfd_sym_file_reference +{ + unsigned long fref_frte_index; /* File reference table index. */ + unsigned long fref_offset; /* Absolute offset into source file. */ +}; +typedef struct bfd_sym_file_reference bfd_sym_file_reference; + +/* NAME TABLE (NTE). */ + +/* RESOURCES TABLE (RTE) + + All code and data is *defined* to reside in a resource. Even A5 + relative data is defined to reside in a dummy resource of ResType + 'gbld'. Code always resides in a resource. Because a code/data + is built of many modules, when walking through a resource we must + point back to the modules in the order they were defined. This is + done by requiring the entries in the Modules Entry table to be + ordered by resource/resource-number and by the location in that + resource. Hence, the resource table entry points to the first + module making up that resource. All modules table entries following + that first one with the same restype/resnum are contiguous and offset + from that first entry. */ + +struct bfd_sym_resources_table_entry +{ + unsigned char rte_res_type[4]; /* Resource Type. */ + unsigned short rte_res_number; /* Resource Number. */ + unsigned long rte_nte_index; /* Name of the resource. */ + unsigned long rte_mte_first; /* Index of first module in the resource. */ + unsigned long rte_mte_last; /* Index of the last module in the resource. */ + unsigned long rte_res_size; /* Size of the resource. */ +}; +typedef struct bfd_sym_resources_table_entry bfd_sym_resources_table_entry; + +/* MODULES TABLE (MTE) + + Modules table entries are ordered by their appearance in a resource. + (Note that having a single module copied into two resources is not + possible). Modules map back to their resource via an index into the + resource table and an offset into the resource. Modules also point + to their source files, both the definition module and implementation + module. Because modules can be textually nested within other + modules, a link to the parent (containing) module is required. This + module can textually contain other modules. A link to the contiguous + list of child (contained) modules is required. Variables, statements, + and types defined in the module are pointed to by indexing the head of + the contiguous lists of contained variables, contained statements, + and contained types. */ + +struct bfd_sym_modules_table_entry +{ + unsigned long mte_rte_index; /* Which resource it is in. */ + unsigned long mte_res_offset; /* Offset into the resource. */ + unsigned long mte_size; /* Size of module. */ + char mte_kind; /* What kind of module this is. */ + char mte_scope; /* How visible is it? */ + unsigned long mte_parent; /* Containing module. */ + bfd_sym_file_reference mte_imp_fref; /* Implementation source. */ + unsigned long mte_imp_end; /* End of implementation source. */ + unsigned long mte_nte_index; /* The name of the module. */ + unsigned long mte_cmte_index; /* Modules contained in this. */ + unsigned long mte_cvte_index; /* Variables contained in this. */ + unsigned long mte_clte_index; /* Local labels defined here. */ + unsigned long mte_ctte_index; /* Types contained in this. */ + unsigned long mte_csnte_idx_1; /* CSNTE index of mte_snbr_first. */ + unsigned long mte_csnte_idx_2; /* CSNTE index of mte_snbr_last. */ +}; +typedef struct bfd_sym_modules_table_entry bfd_sym_modules_table_entry; + +/* FILE REFERENCES TABLE (FRTE) + + The FILE REFERENCES TABLE maps from source file to module & offset. + The table is ordered by increasing file offset. Each new offset + references a module. + + FRT = FILE_SOURCE_START + FILE_SOURCE_INCREMENT* + END_OF_LIST. + + *** THIS MECHANISM IS VERY SLOW FOR FILE+STATEMENT_NUMBER TO + *** MODULE/CODE ADDRESS OPERATIONS. ANOTHER MECHANISM IS + *** REQUIRED!! */ + +union bfd_sym_file_references_table_entry +{ + struct + { + /* END_OF_LIST, FILE_NAME_INDEX, or module table entry. */ + unsigned long type; + } + generic; + + struct + { + /* FILE_NAME_INDEX. */ + unsigned long type; + unsigned long nte_index; + unsigned long mod_date; + } + filename; + + struct + { + /* < FILE_NAME_INDEX. */ + unsigned long mte_index; + unsigned long file_offset; + } + entry; +}; +typedef union bfd_sym_file_references_table_entry bfd_sym_file_references_table_entry; + +/* CONTAINED MODULES TABLE (CMTE) + + Contained Modules are lists of indices into the modules table. The + lists are terminated by an END_OF_LIST index. All entries are of the + same size, hence mapping an index into a CMTE list is simple. + + CMT = MTE_INDEX* END_OF_LIST. */ + +union bfd_sym_contained_modules_table_entry +{ + struct + { + /* END_OF_LIST, index. */ + unsigned long type; + } + generic; + + struct + { + unsigned long mte_index; /* Index into the Modules Table. */ + unsigned long nte_index; /* The name of the module. */ + } + entry; +}; +typedef union bfd_sym_contained_modules_table_entry bfd_sym_contained_modules_table_entry; + +/* CONTAINED VARIABLES TABLE (CVTE) + + Contained Variables map into the module table, file table, name table, and type + table. Contained Variables are a contiguous list of source file change record, + giving the name of and offset into the source file corresponding to all variables + following. Variable definition records contain an index into the name table (giving + the text of the variable as it appears in the source code), an index into the type + table giving the type of the variable, an increment added to the source file + offset giving the start of the implementation of the variable, and a storage + class address, giving information on variable's runtime address. + + CVT = SOURCE_FILE_CHANGE SYMBOL_INFO* END_OF_LIST. + SYMBOL_INFO = SYMBOL_DEFINITION | SOURCE_FILE_CHANGE . + + All entries are of the same size, making the fetching of data simple. The + variable entries in the list are in ALPHABETICAL ORDER to simplify the display of + available variables for several of the debugger's windows. */ + +/* 'la_size' determines the variant used below: + + == BFD_SYM_CVTE_SCA + Traditional STORAGE_CLASS_ADDRESS; + + <= BFD_SYM_CVTE_LA_MAX_SIZE + That many logical address bytes ("in-situ"); + + == BFD_SYM_CVTE_BIG_LA + Logical address bytes in constant pool, at offset 'big_la'. */ + +#define BFD_SYM_CVTE_SCA 0 /* Indicate SCA variant of CVTE. */ +#define BFD_SYM_CVTE_LA_MAX_SIZE 13 /* Max# of logical address bytes in a CVTE. */ +#define BFD_SYM_CVTE_BIG_LA 127 /* Indicates LA redirection to constant pool. */ + +union bfd_sym_contained_variables_table_entry +{ + struct + { + /* END_OF_LIST, SOURCE_FILE_CHANGE, or type table entry. */ + unsigned long type; + } + generic; + + struct + { + /* SOURCE_FILE_CHANGE. */ + unsigned long type; + bfd_sym_file_reference fref; + } + file; + + struct + { + /* < SOURCE_FILE_CHANGE. */ + unsigned long tte_index; + unsigned long nte_index; + unsigned long file_delta; /* Increment from previous source. */ + unsigned char scope; + unsigned char la_size; /* #bytes of LAs below. */ + + union + { + /* la_size == BFD_SYM_CVTE_SCA. */ + struct + { + unsigned char sca_kind; /* Distinguish local from value/var formal. */ + unsigned char sca_class; /* The storage class itself. */ + unsigned long sca_offset; + } + scstruct; + + /* la_size <= BFD_SYM_CVTE_LA_MAX_SIZE. */ + struct { + unsigned char la[BFD_SYM_CVTE_LA_MAX_SIZE]; /* Logical address bytes. */ + unsigned char la_kind; /* Eqv. cvte_location.sca_kind. */ + } + lastruct; + + /* la_size == BFD_SYM_CVTE_BIG_LA 127. */ + struct + { + unsigned long big_la; /* Logical address bytes in constant pool. */ + unsigned char big_la_kind; /* Eqv. cvte_location.sca_kind. */ + } + biglastruct; + } + address; + } + entry; +}; +typedef union bfd_sym_contained_variables_table_entry bfd_sym_contained_variables_table_entry; + +/* CONTAINED STATEMENTS TABLE (CSNTE) + + Contained Statements table. This table is similar to the Contained + Variables table except that instead of VARIABLE_DEFINITION entries, this + module contains STATEMENT_NUMBER_DEFINITION entries. A statement number + definition points back to the containing module (via an index into + the module entry table) and contains the file and resource deltas + to add to the previous values to get to this statement. + All entries are of the same size, making the fetching of data simple. The + entries in the table are in order of increasing statement number within the + source file. + + The Contained Statements table is indexed from two places. An MTE contains + an index to the first statement number within the module. An FRTE contains + an index to the first statement in the table (Possibly. This is slow.) Or + a table of fast statement number to CSNTE entry mappings indexes into the + table. Choice not yet made. */ + +union bfd_sym_contained_statements_table_entry +{ + struct + { + /* END_OF_LIST, SOURCE_FILE_CHANGE, or statement table entry. */ + unsigned long type; + } + generic; + + struct + { + /* SOURCE_FILE_CHANGE. */ + unsigned long type; + bfd_sym_file_reference fref; /* File name table. */ + } + file; + + struct + { + unsigned long mte_index; /* Which module contains it. */ + unsigned long file_delta; /* Where it is defined. */ + unsigned long mte_offset; /* Where it is in the module. */ + } + entry; +}; +typedef union bfd_sym_contained_statements_table_entry bfd_sym_contained_statements_table_entry; + +/* CONTAINED LABELS TABLE (CLTE) + + Contained Labels table names those labels local to the module. It is similar + to the Contained Statements table. */ + +union bfd_sym_contained_labels_table_entry +{ + struct + { + /* END_OF_LIST, SOURCE_FILE_CHANGE, index. */ + unsigned long type; + } + generic; + + struct + { + /* SOURCE_FILE_CHANGE. */ + unsigned long type; + bfd_sym_file_reference fref; + } + file; + + struct + { + /* < SOURCE_FILE_CHANGE. */ + unsigned long mte_index; /* Which module contains us. */ + unsigned long mte_offset; /* Where it is in the module. */ + unsigned long nte_index; /* The name of the label. */ + unsigned long file_delta; /* Where it is defined. */ + unsigned short scope; /* How visible the label is. */ + } + entry; +}; +typedef union bfd_sym_contained_labels_table_entry bfd_sym_contained_labels_table_entry; + +/* CONTAINED TYPES TABLE (CTTE) + + Contained Types define the named types that are in the module. It is used to + map name indices into type indices. The type entries in the table are in + alphabetical order by type name. */ + +union bfd_sym_contained_types_table_entry +{ + struct + { + /* END_OF_LIST, SOURCE_FILE_CHANGE, or type table entry. */ + unsigned long type; + } + generic; + + struct + { + /* SOURCE_FILE_CHANGE. */ + unsigned long type; + bfd_sym_file_reference fref; + } + file; + + struct + { + /* < SOURCE_FILE_CHANGE. */ + unsigned long tte_index; + unsigned long nte_index; + unsigned long file_delta; /* From last file definition. */ + } + entry; +}; +typedef union bfd_sym_contained_types_table_entry bfd_sym_contained_types_table_entry; + +/* TYPE TABLE (TTE). */ + +typedef unsigned long bfd_sym_type_table_entry; + +/* TYPE INFORMATION TABLE (TINFO). */ + +struct bfd_sym_type_information_table_entry +{ + unsigned long nte_index; + unsigned long physical_size; + unsigned long logical_size; + unsigned long offset; +}; +typedef struct bfd_sym_type_information_table_entry bfd_sym_type_information_table_entry; + +/* FILE REFERENCES INDEX TABLE (FITE) + + The FRTE INDEX TABLE indexes into the FILE REFERENCE TABLE above. The FRTE + at that index is the FILE_SOURCE_START for a series of files. The FRTEs are + indexed from 1. The list is terminated with an END_OF_LIST. */ + +union bfd_sym_file_references_index_table_entry +{ + struct + { + unsigned long type; + } + generic; + + struct + { + unsigned long frte_index; /* Index into the FRTE table. */ + unsigned long nte_index; /* Name table index, gives filename. */ + } + entry; +}; +typedef union bfd_sym_file_references_index_table_entry bfd_sym_file_references_index_table_entry; + +/* CONSTANT POOL (CONST) + + The CONSTANT_POOL consists of entries that start on word boundaries. The entries + are referenced by byte index into the constant pool, not by record number. + + Each entry takes the form: + + <16-bit size> + + + Entries do not cross page boundaries. */ + +typedef short bfd_sym_constant_pool_entry; + +/* The DISK_SYMBOL_HEADER_BLOCK is the first record in a .SYM file, + defining the physical characteristics of the symbolic information. + The remainder of the * .SYM file is stored in fixed block + allocations. For the purposes of paging, the * file is considered + to be an array of dshb_page_size blocks, with block 0 (and * + possibly more) devoted to the DISK_SYMBOL_HEADER_BLOCK. + + The dti_object_count field means that the allowed indices for that + type of object are 0 .. dti_object_count. An index of 0, although + allowed, is never done. However, an 0th entry is created in the + table. That entry is filled with all zeroes. The reason for this + is to avoid off-by-one programming errors that would otherwise + occur: an index of k *MEANS* k, not k-1 when going to the disk + table. */ + +struct bfd_sym_table_info +{ + unsigned long dti_first_page; /* First page for this table. */ + unsigned long dti_page_count; /* Number of pages for the table. */ + unsigned long dti_object_count; /* Number of objects in the table. */ +}; +typedef struct bfd_sym_table_info bfd_sym_table_info; + +struct bfd_sym_header_block +{ + unsigned char dshb_id[32]; /* Version information. */ + unsigned short dshb_page_size; /* Size of the pages/blocks. */ + unsigned long dshb_hash_page; /* Disk page for the hash table. */ + unsigned long dshb_root_mte; /* MTE index of the program root. */ + unsigned long dshb_mod_date; /* modification date of executable. */ + bfd_sym_table_info dshb_frte; /* Per TABLE information. */ + bfd_sym_table_info dshb_rte; + bfd_sym_table_info dshb_mte; + bfd_sym_table_info dshb_cmte; + bfd_sym_table_info dshb_cvte; + bfd_sym_table_info dshb_csnte; + bfd_sym_table_info dshb_clte; + bfd_sym_table_info dshb_ctte; + bfd_sym_table_info dshb_tte; + bfd_sym_table_info dshb_nte; + bfd_sym_table_info dshb_tinfo; + bfd_sym_table_info dshb_fite; /* File information. */ + bfd_sym_table_info dshb_const; /* Constant pool. */ + + unsigned char dshb_file_creator[4]; /* Executable's creator. */ + unsigned char dshb_file_type[4]; /* Executable's file type. */ +}; +typedef struct bfd_sym_header_block bfd_sym_header_block; + +struct bfd_sym_data_struct +{ + unsigned char *name_table; + bfd_sym_header_block header; + bfd_sym_version version; + bfd *sbfd; +}; +typedef struct bfd_sym_data_struct bfd_sym_data_struct; + +extern bfd_boolean bfd_sym_mkobject + PARAMS ((bfd *)); +extern void bfd_sym_print_symbol + PARAMS ((bfd *, PTR, asymbol *, bfd_print_symbol_type)); +extern bfd_boolean bfd_sym_valid + PARAMS ((bfd *)); +extern unsigned char * bfd_sym_read_name_table + PARAMS ((bfd *, bfd_sym_header_block *)); +extern void bfd_sym_parse_file_reference_v32 + PARAMS ((unsigned char *, size_t, bfd_sym_file_reference *)); +extern void bfd_sym_parse_disk_table_v32 + PARAMS ((unsigned char *, size_t, bfd_sym_table_info *)); +extern void bfd_sym_parse_header_v32 + PARAMS ((unsigned char *, size_t, bfd_sym_header_block *)); +extern int bfd_sym_read_header_v32 + PARAMS ((bfd *, bfd_sym_header_block *)); +extern int bfd_sym_read_header_v34 + PARAMS ((bfd *, bfd_sym_header_block *)); +extern int bfd_sym_read_header + PARAMS ((bfd *, bfd_sym_header_block *, bfd_sym_version)); +extern int bfd_sym_read_version + PARAMS ((bfd *, bfd_sym_version *)); +extern void bfd_sym_display_table_summary + PARAMS ((FILE *, bfd_sym_table_info *, const char *)); +extern void bfd_sym_display_header + PARAMS ((FILE *, bfd_sym_header_block *)); +extern void bfd_sym_parse_resources_table_entry_v32 + PARAMS ((unsigned char *, size_t, bfd_sym_resources_table_entry *)); +extern void bfd_sym_parse_modules_table_entry_v33 + PARAMS ((unsigned char *, size_t, bfd_sym_modules_table_entry *)); +extern void bfd_sym_parse_file_references_table_entry_v32 + PARAMS ((unsigned char *, size_t, bfd_sym_file_references_table_entry *)); +extern void bfd_sym_parse_contained_modules_table_entry_v32 + PARAMS ((unsigned char *, size_t, bfd_sym_contained_modules_table_entry *)); +extern void bfd_sym_parse_contained_variables_table_entry_v32 + PARAMS ((unsigned char *, size_t, bfd_sym_contained_variables_table_entry *)); +extern void bfd_sym_parse_contained_statements_table_entry_v32 + PARAMS ((unsigned char *, size_t, bfd_sym_contained_statements_table_entry *)); +extern void bfd_sym_parse_contained_labels_table_entry_v32 + PARAMS ((unsigned char *, size_t, bfd_sym_contained_labels_table_entry *)); +extern void bfd_sym_parse_type_table_entry_v32 + PARAMS ((unsigned char *, size_t, bfd_sym_type_table_entry *)); +extern int bfd_sym_fetch_resources_table_entry + PARAMS ((bfd *, bfd_sym_resources_table_entry *, unsigned long)); +extern int bfd_sym_fetch_modules_table_entry + PARAMS ((bfd *, bfd_sym_modules_table_entry *, unsigned long)); +extern int bfd_sym_fetch_file_references_table_entry + PARAMS ((bfd *, bfd_sym_file_references_table_entry *, unsigned long)); +extern int bfd_sym_fetch_contained_modules_table_entry + PARAMS ((bfd *, bfd_sym_contained_modules_table_entry *, unsigned long)); +extern int bfd_sym_fetch_contained_variables_table_entry + PARAMS ((bfd *, bfd_sym_contained_variables_table_entry *, unsigned long)); +extern int bfd_sym_fetch_contained_statements_table_entry + PARAMS ((bfd *, bfd_sym_contained_statements_table_entry *, unsigned long)); +extern int bfd_sym_fetch_contained_labels_table_entry + PARAMS ((bfd *, bfd_sym_contained_labels_table_entry *, unsigned long)); +extern int bfd_sym_fetch_contained_types_table_entry + PARAMS ((bfd *, bfd_sym_contained_types_table_entry *, unsigned long)); +extern int bfd_sym_fetch_file_references_index_table_entry + PARAMS ((bfd *, bfd_sym_file_references_index_table_entry *, unsigned long)); +extern int bfd_sym_fetch_constant_pool_entry + PARAMS ((bfd *, bfd_sym_constant_pool_entry *, unsigned long)); +extern int bfd_sym_fetch_type_table_entry + PARAMS ((bfd *, bfd_sym_type_table_entry *, unsigned long)); +extern int bfd_sym_fetch_type_information_table_entry + PARAMS ((bfd *, bfd_sym_type_information_table_entry *, unsigned long)); +extern int bfd_sym_fetch_type_table_information + PARAMS ((bfd *, bfd_sym_type_information_table_entry *, unsigned long)); +extern const unsigned char * bfd_sym_symbol_name + PARAMS ((bfd *, unsigned long)); +extern const unsigned char * bfd_sym_module_name + PARAMS ((bfd *, unsigned long)); +extern const char * bfd_sym_unparse_storage_kind + PARAMS ((enum bfd_sym_storage_kind)); +extern const char * bfd_sym_unparse_storage_class + PARAMS ((enum bfd_sym_storage_class)); +extern const char * bfd_sym_unparse_module_kind + PARAMS ((enum bfd_sym_module_kind)); +extern const char * bfd_sym_unparse_symbol_scope + PARAMS ((enum bfd_sym_symbol_scope)); +extern void bfd_sym_print_file_reference + PARAMS ((bfd *, FILE *, bfd_sym_file_reference *)); +extern void bfd_sym_print_resources_table_entry + PARAMS ((bfd *, FILE *, bfd_sym_resources_table_entry *)); +extern void bfd_sym_print_modules_table_entry + PARAMS ((bfd *, FILE *, bfd_sym_modules_table_entry *)); +extern void bfd_sym_print_file_references_table_entry + PARAMS ((bfd *, FILE *, bfd_sym_file_references_table_entry *)); +extern void bfd_sym_print_contained_modules_table_entry + PARAMS ((bfd *, FILE *, bfd_sym_contained_modules_table_entry *)); +extern void bfd_sym_print_contained_variables_table_entry + PARAMS ((bfd *, FILE *f, bfd_sym_contained_variables_table_entry *)); +extern void bfd_sym_print_contained_statements_table_entry + PARAMS ((bfd *, FILE *, bfd_sym_contained_statements_table_entry *)); +extern void bfd_sym_print_contained_labels_table_entry + PARAMS ((bfd *, FILE *, bfd_sym_contained_labels_table_entry *)); +extern void bfd_sym_print_contained_types_table_entry + PARAMS ((bfd *, FILE *, bfd_sym_contained_types_table_entry *)); +extern const char * bfd_sym_type_operator_name + PARAMS ((unsigned char)); +extern const char * bfd_sym_type_basic_name + PARAMS ((unsigned char)); +extern int bfd_sym_fetch_long + PARAMS ((unsigned char *, unsigned long, unsigned long, unsigned long *, long *)); +extern void bfd_sym_print_type_information + PARAMS ((bfd *, FILE *, unsigned char *, unsigned long, unsigned long, unsigned long *)); +extern void bfd_sym_print_type_information_table_entry + PARAMS ((bfd *, FILE *, bfd_sym_type_information_table_entry *)); +extern void bfd_sym_print_file_references_index_table_entry + PARAMS ((bfd *, FILE *, bfd_sym_file_references_index_table_entry *)); +extern void bfd_sym_print_constant_pool_entry + PARAMS ((bfd *, FILE *, bfd_sym_constant_pool_entry *)); +extern unsigned char * bfd_sym_display_name_table_entry + PARAMS ((bfd *, FILE *, unsigned char *)); +extern void bfd_sym_display_name_table + PARAMS ((bfd *, FILE *)); +extern void bfd_sym_display_resources_table + PARAMS ((bfd *, FILE *)); +extern void bfd_sym_display_modules_table + PARAMS ((bfd *, FILE *)); +extern void bfd_sym_display_file_references_table + PARAMS ((bfd *, FILE *)); +extern void bfd_sym_display_contained_modules_table + PARAMS ((bfd *, FILE *)); +extern void bfd_sym_display_contained_variables_table + PARAMS ((bfd *, FILE *)); +extern void bfd_sym_display_contained_statements_table + PARAMS ((bfd *, FILE *)); +extern void bfd_sym_display_contained_labels_table + PARAMS ((bfd *, FILE *)); +extern void bfd_sym_display_contained_types_table + PARAMS ((bfd *, FILE *)); +extern void bfd_sym_display_file_references_index_table + PARAMS ((bfd *, FILE *)); +extern void bfd_sym_display_constant_pool + PARAMS ((bfd *, FILE *)); +extern void bfd_sym_display_type_information_table + PARAMS ((bfd *, FILE *)); +extern int bfd_sym_scan + PARAMS ((bfd *, bfd_sym_version, bfd_sym_data_struct *)); +extern const bfd_target * bfd_sym_object_p + PARAMS ((bfd *)); +extern asymbol * bfd_sym_make_empty_symbol + PARAMS ((bfd *)); +extern void bfd_sym_get_symbol_info + PARAMS ((bfd *, asymbol *, symbol_info *)); +extern long bfd_sym_get_symtab_upper_bound + PARAMS ((bfd *)); +extern long bfd_sym_canonicalize_symtab + PARAMS ((bfd *, asymbol **)); +extern int bfd_sym_sizeof_headers + PARAMS ((bfd *, bfd_boolean)); + +#endif /* __xSYM_H__ */ diff --git a/bfd/xtensa-isa.c b/bfd/xtensa-isa.c new file mode 100644 index 0000000..761e5c6 --- /dev/null +++ b/bfd/xtensa-isa.c @@ -0,0 +1,593 @@ +/* Configurable Xtensa ISA support. + Copyright 2003 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include +#include +#include +#include + +#include "xtensa-isa.h" +#include "xtensa-isa-internal.h" + +xtensa_isa xtensa_default_isa = NULL; + +static int +opname_lookup_compare (const void *v1, const void *v2) +{ + opname_lookup_entry *e1 = (opname_lookup_entry *)v1; + opname_lookup_entry *e2 = (opname_lookup_entry *)v2; + + return strcmp (e1->key, e2->key); +} + + +xtensa_isa +xtensa_isa_init (void) +{ + xtensa_isa isa; + int mod; + + isa = xtensa_load_isa (0); + if (isa == 0) + { + fprintf (stderr, "Failed to initialize Xtensa base ISA module\n"); + return NULL; + } + + for (mod = 1; xtensa_isa_modules[mod].get_num_opcodes_fn; mod++) + { + if (!xtensa_extend_isa (isa, mod)) + { + fprintf (stderr, "Failed to initialize Xtensa TIE ISA module\n"); + return NULL; + } + } + + return isa; +} + +/* ISA information. */ + +static int +xtensa_check_isa_config (xtensa_isa_internal *isa, + struct config_struct *config_table) +{ + int i, j; + + if (!config_table) + { + fprintf (stderr, "Error: Empty configuration table in ISA DLL\n"); + return 0; + } + + /* For the first module, save a pointer to the table and record the + specified endianness and availability of the density option. */ + + if (isa->num_modules == 0) + { + int found_memory_order = 0; + + isa->config = config_table; + isa->has_density = 1; /* Default to have density option. */ + + for (i = 0; config_table[i].param_name; i++) + { + if (!strcmp (config_table[i].param_name, "IsaMemoryOrder")) + { + isa->is_big_endian = + (strcmp (config_table[i].param_value, "BigEndian") == 0); + found_memory_order = 1; + } + if (!strcmp (config_table[i].param_name, "IsaUseDensityInstruction")) + { + isa->has_density = atoi (config_table[i].param_value); + } + } + if (!found_memory_order) + { + fprintf (stderr, "Error: \"IsaMemoryOrder\" missing from " + "configuration table in ISA DLL\n"); + return 0; + } + + return 1; + } + + /* For subsequent modules, check that the parameters match. Note: This + code is sufficient to handle the current model where there are never + more than 2 modules; we might at some point want to handle cases where + module N > 0 specifies some parameters not included in the base table, + and we would then add those to isa->config so that subsequent modules + would check against them. */ + + for (i = 0; config_table[i].param_name; i++) + { + for (j = 0; isa->config[j].param_name; j++) + { + if (!strcmp (config_table[i].param_name, isa->config[j].param_name)) + { + int mismatch; + if (!strcmp (config_table[i].param_name, "IsaCoprocessorCount")) + { + /* Only require the coprocessor count to be <= the base. */ + int tiecnt = atoi (config_table[i].param_value); + int basecnt = atoi (isa->config[j].param_value); + mismatch = (tiecnt > basecnt); + } + else + mismatch = strcmp (config_table[i].param_value, + isa->config[j].param_value); + if (mismatch) + { +#define MISMATCH_MESSAGE \ +"Error: Configuration mismatch in the \"%s\" parameter:\n\ +the configuration used when the TIE file was compiled had a value of\n\ +\"%s\", while the current configuration has a value of\n\ +\"%s\". Please rerun the TIE compiler with a matching\n\ +configuration.\n" + fprintf (stderr, MISMATCH_MESSAGE, + config_table[i].param_name, + config_table[i].param_value, + isa->config[j].param_value); + return 0; + } + break; + } + } + } + + return 1; +} + + +static int +xtensa_add_isa (xtensa_isa_internal *isa, libisa_module_specifier libisa) +{ + int (*get_num_opcodes_fn) (void); + struct config_struct *(*get_config_table_fn) (void); + xtensa_opcode_internal **(*get_opcodes_fn) (void); + int (*decode_insn_fn) (const xtensa_insnbuf); + xtensa_opcode_internal **opcodes; + int opc, insn_size, prev_num_opcodes, new_num_opcodes, this_module; + + get_num_opcodes_fn = xtensa_isa_modules[libisa].get_num_opcodes_fn; + get_opcodes_fn = xtensa_isa_modules[libisa].get_opcodes_fn; + decode_insn_fn = xtensa_isa_modules[libisa].decode_insn_fn; + get_config_table_fn = xtensa_isa_modules[libisa].get_config_table_fn; + + if (!get_num_opcodes_fn || !get_opcodes_fn || !decode_insn_fn + || (!get_config_table_fn && isa->num_modules == 0)) + return 0; + + if (get_config_table_fn + && !xtensa_check_isa_config (isa, get_config_table_fn ())) + return 0; + + prev_num_opcodes = isa->num_opcodes; + new_num_opcodes = (*get_num_opcodes_fn) (); + + isa->num_opcodes += new_num_opcodes; + isa->opcode_table = (xtensa_opcode_internal **) + realloc (isa->opcode_table, isa->num_opcodes * + sizeof (xtensa_opcode_internal *)); + isa->opname_lookup_table = (opname_lookup_entry *) + realloc (isa->opname_lookup_table, isa->num_opcodes * + sizeof (opname_lookup_entry)); + + opcodes = (*get_opcodes_fn) (); + + insn_size = isa->insn_size; + for (opc = 0; opc < new_num_opcodes; opc++) + { + xtensa_opcode_internal *intopc = opcodes[opc]; + int newopc = prev_num_opcodes + opc; + isa->opcode_table[newopc] = intopc; + isa->opname_lookup_table[newopc].key = intopc->name; + isa->opname_lookup_table[newopc].opcode = newopc; + if (intopc->length > insn_size) + insn_size = intopc->length; + } + + isa->insn_size = insn_size; + isa->insnbuf_size = ((isa->insn_size + sizeof (xtensa_insnbuf_word) - 1) / + sizeof (xtensa_insnbuf_word)); + + qsort (isa->opname_lookup_table, isa->num_opcodes, + sizeof (opname_lookup_entry), opname_lookup_compare); + + /* Check for duplicate opcode names. */ + for (opc = 1; opc < isa->num_opcodes; opc++) + { + if (!opname_lookup_compare (&isa->opname_lookup_table[opc-1], + &isa->opname_lookup_table[opc])) + { + fprintf (stderr, "Error: Duplicate TIE opcode \"%s\"\n", + isa->opname_lookup_table[opc].key); + return 0; + } + } + + this_module = isa->num_modules; + isa->num_modules += 1; + + isa->module_opcode_base = (int *) realloc (isa->module_opcode_base, + isa->num_modules * sizeof (int)); + isa->module_decode_fn = (xtensa_insn_decode_fn *) + realloc (isa->module_decode_fn, isa->num_modules * + sizeof (xtensa_insn_decode_fn)); + + isa->module_opcode_base[this_module] = prev_num_opcodes; + isa->module_decode_fn[this_module] = decode_insn_fn; + + xtensa_default_isa = isa; + + return 1; /* Library was successfully added. */ +} + + +xtensa_isa +xtensa_load_isa (libisa_module_specifier libisa) +{ + xtensa_isa_internal *isa; + + isa = (xtensa_isa_internal *) malloc (sizeof (xtensa_isa_internal)); + memset (isa, 0, sizeof (xtensa_isa_internal)); + if (!xtensa_add_isa (isa, libisa)) + { + xtensa_isa_free (isa); + return NULL; + } + return (xtensa_isa) isa; +} + + +int +xtensa_extend_isa (xtensa_isa isa, libisa_module_specifier libisa) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *) isa; + return xtensa_add_isa (intisa, libisa); +} + + +void +xtensa_isa_free (xtensa_isa isa) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *) isa; + if (intisa->opcode_table) + free (intisa->opcode_table); + if (intisa->opname_lookup_table) + free (intisa->opname_lookup_table); + if (intisa->module_opcode_base) + free (intisa->module_opcode_base); + if (intisa->module_decode_fn) + free (intisa->module_decode_fn); + free (intisa); +} + + +int +xtensa_insn_maxlength (xtensa_isa isa) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *) isa; + return intisa->insn_size; +} + + +int +xtensa_insnbuf_size (xtensa_isa isa) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + return intisa->insnbuf_size; +} + + +int +xtensa_num_opcodes (xtensa_isa isa) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *) isa; + return intisa->num_opcodes; +} + + +xtensa_opcode +xtensa_opcode_lookup (xtensa_isa isa, const char *opname) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *) isa; + opname_lookup_entry entry, *result; + + entry.key = opname; + result = bsearch (&entry, intisa->opname_lookup_table, intisa->num_opcodes, + sizeof (opname_lookup_entry), opname_lookup_compare); + if (!result) return XTENSA_UNDEFINED; + return result->opcode; +} + + +xtensa_opcode +xtensa_decode_insn (xtensa_isa isa, const xtensa_insnbuf insn) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *) isa; + int n, opc; + for (n = 0; n < intisa->num_modules; n++) { + opc = (intisa->module_decode_fn[n]) (insn); + if (opc != XTENSA_UNDEFINED) + return intisa->module_opcode_base[n] + opc; + } + return XTENSA_UNDEFINED; +} + + +/* Opcode information. */ + +void +xtensa_encode_insn (xtensa_isa isa, xtensa_opcode opc, xtensa_insnbuf insn) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *) isa; + xtensa_insnbuf template = intisa->opcode_table[opc]->template(); + int len = intisa->opcode_table[opc]->length; + int n; + + /* Convert length to 32-bit words. */ + len = (len + 3) / 4; + + /* Copy the template. */ + for (n = 0; n < len; n++) + insn[n] = template[n]; + + /* Fill any unused buffer space with zeros. */ + for ( ; n < intisa->insnbuf_size; n++) + insn[n] = 0; +} + + +const char * +xtensa_opcode_name (xtensa_isa isa, xtensa_opcode opc) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *) isa; + return intisa->opcode_table[opc]->name; +} + + +int +xtensa_insn_length (xtensa_isa isa, xtensa_opcode opc) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *) isa; + return intisa->opcode_table[opc]->length; +} + + +int +xtensa_insn_length_from_first_byte (xtensa_isa isa, char first_byte) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *) isa; + int is_density = (first_byte & (intisa->is_big_endian ? 0x80 : 0x08)) != 0; + return (intisa->has_density && is_density ? 2 : 3); +} + + +int +xtensa_num_operands (xtensa_isa isa, xtensa_opcode opc) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *) isa; + return intisa->opcode_table[opc]->iclass->num_operands; +} + + +xtensa_operand +xtensa_get_operand (xtensa_isa isa, xtensa_opcode opc, int opnd) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *) isa; + xtensa_iclass_internal *iclass = intisa->opcode_table[opc]->iclass; + if (opnd >= iclass->num_operands) + return NULL; + return (xtensa_operand) iclass->operands[opnd]; +} + + +/* Operand information. */ + +char * +xtensa_operand_kind (xtensa_operand opnd) +{ + xtensa_operand_internal *intop = (xtensa_operand_internal *) opnd; + return intop->operand_kind; +} + + +char +xtensa_operand_inout (xtensa_operand opnd) +{ + xtensa_operand_internal *intop = (xtensa_operand_internal *) opnd; + return intop->inout; +} + + +uint32 +xtensa_operand_get_field (xtensa_operand opnd, const xtensa_insnbuf insn) +{ + xtensa_operand_internal *intop = (xtensa_operand_internal *) opnd; + return (*intop->get_field) (insn); +} + + +void +xtensa_operand_set_field (xtensa_operand opnd, xtensa_insnbuf insn, uint32 val) +{ + xtensa_operand_internal *intop = (xtensa_operand_internal *) opnd; + return (*intop->set_field) (insn, val); +} + + +xtensa_encode_result +xtensa_operand_encode (xtensa_operand opnd, uint32 *valp) +{ + xtensa_operand_internal *intop = (xtensa_operand_internal *) opnd; + return (*intop->encode) (valp); +} + + +uint32 +xtensa_operand_decode (xtensa_operand opnd, uint32 val) +{ + xtensa_operand_internal *intop = (xtensa_operand_internal *) opnd; + return (*intop->decode) (val); +} + + +int +xtensa_operand_isPCRelative (xtensa_operand opnd) +{ + xtensa_operand_internal *intop = (xtensa_operand_internal *) opnd; + return intop->isPCRelative; +} + + +uint32 +xtensa_operand_do_reloc (xtensa_operand opnd, uint32 addr, uint32 pc) +{ + xtensa_operand_internal *intop = (xtensa_operand_internal *) opnd; + if (!intop->isPCRelative) + return addr; + return (*intop->do_reloc) (addr, pc); +} + + +uint32 +xtensa_operand_undo_reloc (xtensa_operand opnd, uint32 offset, uint32 pc) +{ + xtensa_operand_internal *intop = (xtensa_operand_internal *) opnd; + if (!intop->isPCRelative) + return offset; + return (*intop->undo_reloc) (offset, pc); +} + + +/* Instruction buffers. */ + +xtensa_insnbuf +xtensa_insnbuf_alloc (xtensa_isa isa) +{ + return (xtensa_insnbuf) malloc (xtensa_insnbuf_size (isa) * + sizeof (xtensa_insnbuf_word)); +} + + +void +xtensa_insnbuf_free (xtensa_insnbuf buf) +{ + free( buf ); +} + + +/* Given , the index of a byte in a xtensa_insnbuf, our + internal representation of a xtensa instruction word, return the index of + its word and the bit index of its low order byte in the xtensa_insnbuf. */ + +static inline int +byte_to_word_index (int byte_index) +{ + return byte_index / sizeof (xtensa_insnbuf_word); +} + + +static inline int +byte_to_bit_index (int byte_index) +{ + return (byte_index & 0x3) * 8; +} + + +/* Copy an instruction in the 32 bit words pointed at by to characters + pointed at by . This is more complicated than you might think because + we want 16 bit instructions in bytes 2,3 for big endian. This function + allows us to specify which byte in to start with and which way to + increment, allowing trivial implementation for both big and little endian. + And it seems to make pretty good code for both. */ + +void +xtensa_insnbuf_to_chars (xtensa_isa isa, const xtensa_insnbuf insn, char *cp) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *) isa; + int insn_size = xtensa_insn_maxlength (intisa); + int fence_post, start, increment, i, byte_count; + xtensa_opcode opc; + + if (intisa->is_big_endian) + { + start = insn_size - 1; + increment = -1; + } + else + { + start = 0; + increment = 1; + } + + /* Find the opcode; do nothing if the buffer does not contain a valid + instruction since we need to know how many bytes to copy. */ + opc = xtensa_decode_insn (isa, insn); + if (opc == XTENSA_UNDEFINED) + return; + + byte_count = xtensa_insn_length (isa, opc); + fence_post = start + (byte_count * increment); + + for (i = start; i != fence_post; i += increment, ++cp) + { + int word_inx = byte_to_word_index (i); + int bit_inx = byte_to_bit_index (i); + + *cp = (insn[word_inx] >> bit_inx) & 0xff; + } +} + +/* Inward conversion from byte stream to xtensa_insnbuf. See + xtensa_insnbuf_to_chars for a discussion of why this is + complicated by endianness. */ + +void +xtensa_insnbuf_from_chars (xtensa_isa isa, xtensa_insnbuf insn, const char* cp) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *) isa; + int insn_size = xtensa_insn_maxlength (intisa); + int fence_post, start, increment, i; + + if (intisa->is_big_endian) + { + start = insn_size - 1; + increment = -1; + } + else + { + start = 0; + increment = 1; + } + + fence_post = start + (insn_size * increment); + memset (insn, 0, xtensa_insnbuf_size (isa) * sizeof (xtensa_insnbuf_word)); + + for ( i = start; i != fence_post; i += increment, ++cp ) + { + int word_inx = byte_to_word_index (i); + int bit_inx = byte_to_bit_index (i); + + insn[word_inx] |= (*cp & 0xff) << bit_inx; + } +} + diff --git a/bfd/xtensa-modules.c b/bfd/xtensa-modules.c new file mode 100644 index 0000000..e5d7682 --- /dev/null +++ b/bfd/xtensa-modules.c @@ -0,0 +1,6088 @@ +/* Xtensa configuration-specific ISA information. + Copyright 2003 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include +#include "xtensa-isa-internal.h" +#include "ansidecl.h" + +#define BPW 32 +#define WINDEX(_n) ((_n) / BPW) +#define BINDEX(_n) ((_n) %% BPW) + +static uint32 tie_do_reloc_l (uint32, uint32) ATTRIBUTE_UNUSED; +static uint32 tie_undo_reloc_l (uint32, uint32) ATTRIBUTE_UNUSED; + +static uint32 +tie_do_reloc_l (uint32 addr, uint32 pc) +{ + return (addr - pc); +} + +static uint32 +tie_undo_reloc_l (uint32 offset, uint32 pc) +{ + return (pc + offset); +} + +xtensa_opcode_internal** get_opcodes (void); +int get_num_opcodes (void); +int decode_insn (const xtensa_insnbuf); +int interface_version (void); + +uint32 get_bbi_field (const xtensa_insnbuf); +void set_bbi_field (xtensa_insnbuf, uint32); +uint32 get_bbi4_field (const xtensa_insnbuf); +void set_bbi4_field (xtensa_insnbuf, uint32); +uint32 get_i_field (const xtensa_insnbuf); +void set_i_field (xtensa_insnbuf, uint32); +uint32 get_imm12_field (const xtensa_insnbuf); +void set_imm12_field (xtensa_insnbuf, uint32); +uint32 get_imm12b_field (const xtensa_insnbuf); +void set_imm12b_field (xtensa_insnbuf, uint32); +uint32 get_imm16_field (const xtensa_insnbuf); +void set_imm16_field (xtensa_insnbuf, uint32); +uint32 get_imm4_field (const xtensa_insnbuf); +void set_imm4_field (xtensa_insnbuf, uint32); +uint32 get_imm6_field (const xtensa_insnbuf); +void set_imm6_field (xtensa_insnbuf, uint32); +uint32 get_imm6hi_field (const xtensa_insnbuf); +void set_imm6hi_field (xtensa_insnbuf, uint32); +uint32 get_imm6lo_field (const xtensa_insnbuf); +void set_imm6lo_field (xtensa_insnbuf, uint32); +uint32 get_imm7_field (const xtensa_insnbuf); +void set_imm7_field (xtensa_insnbuf, uint32); +uint32 get_imm7hi_field (const xtensa_insnbuf); +void set_imm7hi_field (xtensa_insnbuf, uint32); +uint32 get_imm7lo_field (const xtensa_insnbuf); +void set_imm7lo_field (xtensa_insnbuf, uint32); +uint32 get_imm8_field (const xtensa_insnbuf); +void set_imm8_field (xtensa_insnbuf, uint32); +uint32 get_m_field (const xtensa_insnbuf); +void set_m_field (xtensa_insnbuf, uint32); +uint32 get_mn_field (const xtensa_insnbuf); +void set_mn_field (xtensa_insnbuf, uint32); +uint32 get_n_field (const xtensa_insnbuf); +void set_n_field (xtensa_insnbuf, uint32); +uint32 get_none_field (const xtensa_insnbuf); +void set_none_field (xtensa_insnbuf, uint32); +uint32 get_offset_field (const xtensa_insnbuf); +void set_offset_field (xtensa_insnbuf, uint32); +uint32 get_op0_field (const xtensa_insnbuf); +void set_op0_field (xtensa_insnbuf, uint32); +uint32 get_op1_field (const xtensa_insnbuf); +void set_op1_field (xtensa_insnbuf, uint32); +uint32 get_op2_field (const xtensa_insnbuf); +void set_op2_field (xtensa_insnbuf, uint32); +uint32 get_r_field (const xtensa_insnbuf); +void set_r_field (xtensa_insnbuf, uint32); +uint32 get_s_field (const xtensa_insnbuf); +void set_s_field (xtensa_insnbuf, uint32); +uint32 get_sa4_field (const xtensa_insnbuf); +void set_sa4_field (xtensa_insnbuf, uint32); +uint32 get_sae_field (const xtensa_insnbuf); +void set_sae_field (xtensa_insnbuf, uint32); +uint32 get_sae4_field (const xtensa_insnbuf); +void set_sae4_field (xtensa_insnbuf, uint32); +uint32 get_sal_field (const xtensa_insnbuf); +void set_sal_field (xtensa_insnbuf, uint32); +uint32 get_sar_field (const xtensa_insnbuf); +void set_sar_field (xtensa_insnbuf, uint32); +uint32 get_sas_field (const xtensa_insnbuf); +void set_sas_field (xtensa_insnbuf, uint32); +uint32 get_sas4_field (const xtensa_insnbuf); +void set_sas4_field (xtensa_insnbuf, uint32); +uint32 get_sr_field (const xtensa_insnbuf); +void set_sr_field (xtensa_insnbuf, uint32); +uint32 get_t_field (const xtensa_insnbuf); +void set_t_field (xtensa_insnbuf, uint32); +uint32 get_thi3_field (const xtensa_insnbuf); +void set_thi3_field (xtensa_insnbuf, uint32); +uint32 get_z_field (const xtensa_insnbuf); +void set_z_field (xtensa_insnbuf, uint32); + + +uint32 +get_bbi_field (const xtensa_insnbuf insn) +{ + return ((insn[0] & 0xf0000) >> 16) | + ((insn[0] & 0x100) >> 4); +} + +void +set_bbi_field (xtensa_insnbuf insn, uint32 val) +{ + insn[0] = (insn[0] & 0xfff0ffff) | ((val << 16) & 0xf0000); + insn[0] = (insn[0] & 0xfffffeff) | ((val << 4) & 0x100); +} + +uint32 +get_bbi4_field (const xtensa_insnbuf insn) +{ + return ((insn[0] & 0x100) >> 8); +} + +void +set_bbi4_field (xtensa_insnbuf insn, uint32 val) +{ + insn[0] = (insn[0] & 0xfffffeff) | ((val << 8) & 0x100); +} + +uint32 +get_i_field (const xtensa_insnbuf insn) +{ + return ((insn[0] & 0x80000) >> 19); +} + +void +set_i_field (xtensa_insnbuf insn, uint32 val) +{ + insn[0] = (insn[0] & 0xfff7ffff) | ((val << 19) & 0x80000); +} + +uint32 +get_imm12_field (const xtensa_insnbuf insn) +{ + return ((insn[0] & 0xfff)); +} + +void +set_imm12_field (xtensa_insnbuf insn, uint32 val) +{ + insn[0] = (insn[0] & 0xfffff000) | (val & 0xfff); +} + +uint32 +get_imm12b_field (const xtensa_insnbuf insn) +{ + return ((insn[0] & 0xff)) | + ((insn[0] & 0xf000) >> 4); +} + +void +set_imm12b_field (xtensa_insnbuf insn, uint32 val) +{ + insn[0] = (insn[0] & 0xffffff00) | (val & 0xff); + insn[0] = (insn[0] & 0xffff0fff) | ((val << 4) & 0xf000); +} + +uint32 +get_imm16_field (const xtensa_insnbuf insn) +{ + return ((insn[0] & 0xffff)); +} + +void +set_imm16_field (xtensa_insnbuf insn, uint32 val) +{ + insn[0] = (insn[0] & 0xffff0000) | (val & 0xffff); +} + +uint32 +get_imm4_field (const xtensa_insnbuf insn) +{ + return ((insn[0] & 0xf00) >> 8); +} + +void +set_imm4_field (xtensa_insnbuf insn, uint32 val) +{ + insn[0] = (insn[0] & 0xfffff0ff) | ((val << 8) & 0xf00); +} + +uint32 +get_imm6_field (const xtensa_insnbuf insn) +{ + return ((insn[0] & 0xf00) >> 8) | + ((insn[0] & 0x30000) >> 12); +} + +void +set_imm6_field (xtensa_insnbuf insn, uint32 val) +{ + insn[0] = (insn[0] & 0xfffff0ff) | ((val << 8) & 0xf00); + insn[0] = (insn[0] & 0xfffcffff) | ((val << 12) & 0x30000); +} + +uint32 +get_imm6hi_field (const xtensa_insnbuf insn) +{ + return ((insn[0] & 0x30000) >> 16); +} + +void +set_imm6hi_field (xtensa_insnbuf insn, uint32 val) +{ + insn[0] = (insn[0] & 0xfffcffff) | ((val << 16) & 0x30000); +} + +uint32 +get_imm6lo_field (const xtensa_insnbuf insn) +{ + return ((insn[0] & 0xf00) >> 8); +} + +void +set_imm6lo_field (xtensa_insnbuf insn, uint32 val) +{ + insn[0] = (insn[0] & 0xfffff0ff) | ((val << 8) & 0xf00); +} + +uint32 +get_imm7_field (const xtensa_insnbuf insn) +{ + return ((insn[0] & 0xf00) >> 8) | + ((insn[0] & 0x70000) >> 12); +} + +void +set_imm7_field (xtensa_insnbuf insn, uint32 val) +{ + insn[0] = (insn[0] & 0xfffff0ff) | ((val << 8) & 0xf00); + insn[0] = (insn[0] & 0xfff8ffff) | ((val << 12) & 0x70000); +} + +uint32 +get_imm7hi_field (const xtensa_insnbuf insn) +{ + return ((insn[0] & 0x70000) >> 16); +} + +void +set_imm7hi_field (xtensa_insnbuf insn, uint32 val) +{ + insn[0] = (insn[0] & 0xfff8ffff) | ((val << 16) & 0x70000); +} + +uint32 +get_imm7lo_field (const xtensa_insnbuf insn) +{ + return ((insn[0] & 0xf00) >> 8); +} + +void +set_imm7lo_field (xtensa_insnbuf insn, uint32 val) +{ + insn[0] = (insn[0] & 0xfffff0ff) | ((val << 8) & 0xf00); +} + +uint32 +get_imm8_field (const xtensa_insnbuf insn) +{ + return ((insn[0] & 0xff)); +} + +void +set_imm8_field (xtensa_insnbuf insn, uint32 val) +{ + insn[0] = (insn[0] & 0xffffff00) | (val & 0xff); +} + +uint32 +get_m_field (const xtensa_insnbuf insn) +{ + return ((insn[0] & 0x30000) >> 16); +} + +void +set_m_field (xtensa_insnbuf insn, uint32 val) +{ + insn[0] = (insn[0] & 0xfffcffff) | ((val << 16) & 0x30000); +} + +uint32 +get_mn_field (const xtensa_insnbuf insn) +{ + return ((insn[0] & 0x30000) >> 16) | + ((insn[0] & 0xc0000) >> 16); +} + +void +set_mn_field (xtensa_insnbuf insn, uint32 val) +{ + insn[0] = (insn[0] & 0xfffcffff) | ((val << 16) & 0x30000); + insn[0] = (insn[0] & 0xfff3ffff) | ((val << 16) & 0xc0000); +} + +uint32 +get_n_field (const xtensa_insnbuf insn) +{ + return ((insn[0] & 0xc0000) >> 18); +} + +void +set_n_field (xtensa_insnbuf insn, uint32 val) +{ + insn[0] = (insn[0] & 0xfff3ffff) | ((val << 18) & 0xc0000); +} + +uint32 +get_none_field (const xtensa_insnbuf insn) +{ + return ((insn[0] & 0x0)); +} + +void +set_none_field (xtensa_insnbuf insn, uint32 val) +{ + insn[0] = (insn[0] & 0xffffffff) | (val & 0x0); +} + +uint32 +get_offset_field (const xtensa_insnbuf insn) +{ + return ((insn[0] & 0x3ffff)); +} + +void +set_offset_field (xtensa_insnbuf insn, uint32 val) +{ + insn[0] = (insn[0] & 0xfffc0000) | (val & 0x3ffff); +} + +uint32 +get_op0_field (const xtensa_insnbuf insn) +{ + return ((insn[0] & 0xf00000) >> 20); +} + +void +set_op0_field (xtensa_insnbuf insn, uint32 val) +{ + insn[0] = (insn[0] & 0xff0fffff) | ((val << 20) & 0xf00000); +} + +uint32 +get_op1_field (const xtensa_insnbuf insn) +{ + return ((insn[0] & 0xf0) >> 4); +} + +void +set_op1_field (xtensa_insnbuf insn, uint32 val) +{ + insn[0] = (insn[0] & 0xffffff0f) | ((val << 4) & 0xf0); +} + +uint32 +get_op2_field (const xtensa_insnbuf insn) +{ + return ((insn[0] & 0xf)); +} + +void +set_op2_field (xtensa_insnbuf insn, uint32 val) +{ + insn[0] = (insn[0] & 0xfffffff0) | (val & 0xf); +} + +uint32 +get_r_field (const xtensa_insnbuf insn) +{ + return ((insn[0] & 0xf00) >> 8); +} + +void +set_r_field (xtensa_insnbuf insn, uint32 val) +{ + insn[0] = (insn[0] & 0xfffff0ff) | ((val << 8) & 0xf00); +} + +uint32 +get_s_field (const xtensa_insnbuf insn) +{ + return ((insn[0] & 0xf000) >> 12); +} + +void +set_s_field (xtensa_insnbuf insn, uint32 val) +{ + insn[0] = (insn[0] & 0xffff0fff) | ((val << 12) & 0xf000); +} + +uint32 +get_sa4_field (const xtensa_insnbuf insn) +{ + return ((insn[0] & 0x1)); +} + +void +set_sa4_field (xtensa_insnbuf insn, uint32 val) +{ + insn[0] = (insn[0] & 0xfffffffe) | (val & 0x1); +} + +uint32 +get_sae_field (const xtensa_insnbuf insn) +{ + return ((insn[0] & 0xf000) >> 12) | + ((insn[0] & 0x10)); +} + +void +set_sae_field (xtensa_insnbuf insn, uint32 val) +{ + insn[0] = (insn[0] & 0xffff0fff) | ((val << 12) & 0xf000); + insn[0] = (insn[0] & 0xffffffef) | (val & 0x10); +} + +uint32 +get_sae4_field (const xtensa_insnbuf insn) +{ + return ((insn[0] & 0x10) >> 4); +} + +void +set_sae4_field (xtensa_insnbuf insn, uint32 val) +{ + insn[0] = (insn[0] & 0xffffffef) | ((val << 4) & 0x10); +} + +uint32 +get_sal_field (const xtensa_insnbuf insn) +{ + return ((insn[0] & 0xf0000) >> 16) | + ((insn[0] & 0x1) << 4); +} + +void +set_sal_field (xtensa_insnbuf insn, uint32 val) +{ + insn[0] = (insn[0] & 0xfff0ffff) | ((val << 16) & 0xf0000); + insn[0] = (insn[0] & 0xfffffffe) | ((val >> 4) & 0x1); +} + +uint32 +get_sar_field (const xtensa_insnbuf insn) +{ + return ((insn[0] & 0xf000) >> 12) | + ((insn[0] & 0x1) << 4); +} + +void +set_sar_field (xtensa_insnbuf insn, uint32 val) +{ + insn[0] = (insn[0] & 0xffff0fff) | ((val << 12) & 0xf000); + insn[0] = (insn[0] & 0xfffffffe) | ((val >> 4) & 0x1); +} + +uint32 +get_sas_field (const xtensa_insnbuf insn) +{ + return ((insn[0] & 0xf000) >> 12) | + ((insn[0] & 0x10000) >> 12); +} + +void +set_sas_field (xtensa_insnbuf insn, uint32 val) +{ + insn[0] = (insn[0] & 0xffff0fff) | ((val << 12) & 0xf000); + insn[0] = (insn[0] & 0xfffeffff) | ((val << 12) & 0x10000); +} + +uint32 +get_sas4_field (const xtensa_insnbuf insn) +{ + return ((insn[0] & 0x10000) >> 16); +} + +void +set_sas4_field (xtensa_insnbuf insn, uint32 val) +{ + insn[0] = (insn[0] & 0xfffeffff) | ((val << 16) & 0x10000); +} + +uint32 +get_sr_field (const xtensa_insnbuf insn) +{ + return ((insn[0] & 0xf00) >> 8) | + ((insn[0] & 0xf000) >> 8); +} + +void +set_sr_field (xtensa_insnbuf insn, uint32 val) +{ + insn[0] = (insn[0] & 0xfffff0ff) | ((val << 8) & 0xf00); + insn[0] = (insn[0] & 0xffff0fff) | ((val << 8) & 0xf000); +} + +uint32 +get_t_field (const xtensa_insnbuf insn) +{ + return ((insn[0] & 0xf0000) >> 16); +} + +void +set_t_field (xtensa_insnbuf insn, uint32 val) +{ + insn[0] = (insn[0] & 0xfff0ffff) | ((val << 16) & 0xf0000); +} + +uint32 +get_thi3_field (const xtensa_insnbuf insn) +{ + return ((insn[0] & 0xe0000) >> 17); +} + +void +set_thi3_field (xtensa_insnbuf insn, uint32 val) +{ + insn[0] = (insn[0] & 0xfff1ffff) | ((val << 17) & 0xe0000); +} + +uint32 +get_z_field (const xtensa_insnbuf insn) +{ + return ((insn[0] & 0x40000) >> 18); +} + +void +set_z_field (xtensa_insnbuf insn, uint32 val) +{ + insn[0] = (insn[0] & 0xfffbffff) | ((val << 18) & 0x40000); +} + +uint32 decode_b4constu (uint32); +xtensa_encode_result encode_b4constu (uint32 *); +uint32 decode_simm8x256 (uint32); +xtensa_encode_result encode_simm8x256 (uint32 *); +uint32 decode_soffset (uint32); +xtensa_encode_result encode_soffset (uint32 *); +uint32 decode_imm4 (uint32); +xtensa_encode_result encode_imm4 (uint32 *); +uint32 decode_op0 (uint32); +xtensa_encode_result encode_op0 (uint32 *); +uint32 decode_op1 (uint32); +xtensa_encode_result encode_op1 (uint32 *); +uint32 decode_imm6 (uint32); +xtensa_encode_result encode_imm6 (uint32 *); +uint32 decode_op2 (uint32); +xtensa_encode_result encode_op2 (uint32 *); +uint32 decode_imm7 (uint32); +xtensa_encode_result encode_imm7 (uint32 *); +uint32 decode_simm4 (uint32); +xtensa_encode_result encode_simm4 (uint32 *); +uint32 decode_ai4const (uint32); +xtensa_encode_result encode_ai4const (uint32 *); +uint32 decode_imm8 (uint32); +xtensa_encode_result encode_imm8 (uint32 *); +uint32 decode_sae (uint32); +xtensa_encode_result encode_sae (uint32 *); +uint32 decode_imm7lo (uint32); +xtensa_encode_result encode_imm7lo (uint32 *); +uint32 decode_simm7 (uint32); +xtensa_encode_result encode_simm7 (uint32 *); +uint32 decode_simm8 (uint32); +xtensa_encode_result encode_simm8 (uint32 *); +uint32 decode_uimm12x8 (uint32); +xtensa_encode_result encode_uimm12x8 (uint32 *); +uint32 decode_sal (uint32); +xtensa_encode_result encode_sal (uint32 *); +uint32 decode_uimm6 (uint32); +xtensa_encode_result encode_uimm6 (uint32 *); +uint32 decode_sas4 (uint32); +xtensa_encode_result encode_sas4 (uint32 *); +uint32 decode_uimm8 (uint32); +xtensa_encode_result encode_uimm8 (uint32 *); +uint32 decode_uimm16x4 (uint32); +xtensa_encode_result encode_uimm16x4 (uint32 *); +uint32 decode_sar (uint32); +xtensa_encode_result encode_sar (uint32 *); +uint32 decode_sa4 (uint32); +xtensa_encode_result encode_sa4 (uint32 *); +uint32 decode_sas (uint32); +xtensa_encode_result encode_sas (uint32 *); +uint32 decode_imm6hi (uint32); +xtensa_encode_result encode_imm6hi (uint32 *); +uint32 decode_bbi (uint32); +xtensa_encode_result encode_bbi (uint32 *); +uint32 decode_uimm8x2 (uint32); +xtensa_encode_result encode_uimm8x2 (uint32 *); +uint32 decode_uimm8x4 (uint32); +xtensa_encode_result encode_uimm8x4 (uint32 *); +uint32 decode_msalp32 (uint32); +xtensa_encode_result encode_msalp32 (uint32 *); +uint32 decode_bbi4 (uint32); +xtensa_encode_result encode_bbi4 (uint32 *); +uint32 decode_op2p1 (uint32); +xtensa_encode_result encode_op2p1 (uint32 *); +uint32 decode_soffsetx4 (uint32); +xtensa_encode_result encode_soffsetx4 (uint32 *); +uint32 decode_imm6lo (uint32); +xtensa_encode_result encode_imm6lo (uint32 *); +uint32 decode_imm12 (uint32); +xtensa_encode_result encode_imm12 (uint32 *); +uint32 decode_b4const (uint32); +xtensa_encode_result encode_b4const (uint32 *); +uint32 decode_i (uint32); +xtensa_encode_result encode_i (uint32 *); +uint32 decode_imm16 (uint32); +xtensa_encode_result encode_imm16 (uint32 *); +uint32 decode_mn (uint32); +xtensa_encode_result encode_mn (uint32 *); +uint32 decode_m (uint32); +xtensa_encode_result encode_m (uint32 *); +uint32 decode_n (uint32); +xtensa_encode_result encode_n (uint32 *); +uint32 decode_none (uint32); +xtensa_encode_result encode_none (uint32 *); +uint32 decode_imm12b (uint32); +xtensa_encode_result encode_imm12b (uint32 *); +uint32 decode_r (uint32); +xtensa_encode_result encode_r (uint32 *); +uint32 decode_s (uint32); +xtensa_encode_result encode_s (uint32 *); +uint32 decode_t (uint32); +xtensa_encode_result encode_t (uint32 *); +uint32 decode_thi3 (uint32); +xtensa_encode_result encode_thi3 (uint32 *); +uint32 decode_sae4 (uint32); +xtensa_encode_result encode_sae4 (uint32 *); +uint32 decode_offset (uint32); +xtensa_encode_result encode_offset (uint32 *); +uint32 decode_imm7hi (uint32); +xtensa_encode_result encode_imm7hi (uint32 *); +uint32 decode_uimm4x16 (uint32); +xtensa_encode_result encode_uimm4x16 (uint32 *); +uint32 decode_simm12b (uint32); +xtensa_encode_result encode_simm12b (uint32 *); +uint32 decode_lsi4x4 (uint32); +xtensa_encode_result encode_lsi4x4 (uint32 *); +uint32 decode_z (uint32); +xtensa_encode_result encode_z (uint32 *); +uint32 decode_simm12 (uint32); +xtensa_encode_result encode_simm12 (uint32 *); +uint32 decode_sr (uint32); +xtensa_encode_result encode_sr (uint32 *); +uint32 decode_nimm4x2 (uint32); +xtensa_encode_result encode_nimm4x2 (uint32 *); + + +static const uint32 b4constu_table[] = { + 32768, + 65536, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 10, + 12, + 16, + 32, + 64, + 128, + 256 +}; + +uint32 +decode_b4constu (uint32 val) +{ + val = b4constu_table[val]; + return val; +} + +xtensa_encode_result +encode_b4constu (uint32 *valp) +{ + uint32 val = *valp; + unsigned i; + for (i = 0; i < (1 << 4); i += 1) + if (b4constu_table[i] == val) goto found; + return xtensa_encode_result_not_in_table; + found: + val = i; + *valp = val; + return xtensa_encode_result_ok; +} + +uint32 +decode_simm8x256 (uint32 val) +{ + val = (val ^ 0x80) - 0x80; + val <<= 8; + return val; +} + +xtensa_encode_result +encode_simm8x256 (uint32 *valp) +{ + uint32 val = *valp; + if ((val & ((1 << 8) - 1)) != 0) + return xtensa_encode_result_align; + val = (signed int) val >> 8; + if (((val + (1 << 7)) >> 8) != 0) + { + if ((signed int) val > 0) + return xtensa_encode_result_too_high; + else + return xtensa_encode_result_too_low; + } + *valp = val; + return xtensa_encode_result_ok; +} + +uint32 +decode_soffset (uint32 val) +{ + val = (val ^ 0x20000) - 0x20000; + return val; +} + +xtensa_encode_result +encode_soffset (uint32 *valp) +{ + uint32 val = *valp; + if (((val + (1 << 17)) >> 18) != 0) + { + if ((signed int) val > 0) + return xtensa_encode_result_too_high; + else + return xtensa_encode_result_too_low; + } + *valp = val; + return xtensa_encode_result_ok; +} + +uint32 +decode_imm4 (uint32 val) +{ + return val; +} + +xtensa_encode_result +encode_imm4 (uint32 *valp) +{ + uint32 val = *valp; + if ((val >> 4) != 0) + return xtensa_encode_result_too_high; + *valp = val; + return xtensa_encode_result_ok; +} + +uint32 +decode_op0 (uint32 val) +{ + return val; +} + +xtensa_encode_result +encode_op0 (uint32 *valp) +{ + uint32 val = *valp; + if ((val >> 4) != 0) + return xtensa_encode_result_too_high; + *valp = val; + return xtensa_encode_result_ok; +} + +uint32 +decode_op1 (uint32 val) +{ + return val; +} + +xtensa_encode_result +encode_op1 (uint32 *valp) +{ + uint32 val = *valp; + if ((val >> 4) != 0) + return xtensa_encode_result_too_high; + *valp = val; + return xtensa_encode_result_ok; +} + +uint32 +decode_imm6 (uint32 val) +{ + return val; +} + +xtensa_encode_result +encode_imm6 (uint32 *valp) +{ + uint32 val = *valp; + if ((val >> 6) != 0) + return xtensa_encode_result_too_high; + *valp = val; + return xtensa_encode_result_ok; +} + +uint32 +decode_op2 (uint32 val) +{ + return val; +} + +xtensa_encode_result +encode_op2 (uint32 *valp) +{ + uint32 val = *valp; + if ((val >> 4) != 0) + return xtensa_encode_result_too_high; + *valp = val; + return xtensa_encode_result_ok; +} + +uint32 +decode_imm7 (uint32 val) +{ + return val; +} + +xtensa_encode_result +encode_imm7 (uint32 *valp) +{ + uint32 val = *valp; + if ((val >> 7) != 0) + return xtensa_encode_result_too_high; + *valp = val; + return xtensa_encode_result_ok; +} + +uint32 +decode_simm4 (uint32 val) +{ + val = (val ^ 0x8) - 0x8; + return val; +} + +xtensa_encode_result +encode_simm4 (uint32 *valp) +{ + uint32 val = *valp; + if (((val + (1 << 3)) >> 4) != 0) + { + if ((signed int) val > 0) + return xtensa_encode_result_too_high; + else + return xtensa_encode_result_too_low; + } + *valp = val; + return xtensa_encode_result_ok; +} + +static const uint32 ai4const_table[] = { + -1, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 +}; + +uint32 +decode_ai4const (uint32 val) +{ + val = ai4const_table[val]; + return val; +} + +xtensa_encode_result +encode_ai4const (uint32 *valp) +{ + uint32 val = *valp; + unsigned i; + for (i = 0; i < (1 << 4); i += 1) + if (ai4const_table[i] == val) goto found; + return xtensa_encode_result_not_in_table; + found: + val = i; + *valp = val; + return xtensa_encode_result_ok; +} + +uint32 +decode_imm8 (uint32 val) +{ + return val; +} + +xtensa_encode_result +encode_imm8 (uint32 *valp) +{ + uint32 val = *valp; + if ((val >> 8) != 0) + return xtensa_encode_result_too_high; + *valp = val; + return xtensa_encode_result_ok; +} + +uint32 +decode_sae (uint32 val) +{ + return val; +} + +xtensa_encode_result +encode_sae (uint32 *valp) +{ + uint32 val = *valp; + if ((val >> 5) != 0) + return xtensa_encode_result_too_high; + *valp = val; + return xtensa_encode_result_ok; +} + +uint32 +decode_imm7lo (uint32 val) +{ + return val; +} + +xtensa_encode_result +encode_imm7lo (uint32 *valp) +{ + uint32 val = *valp; + if ((val >> 4) != 0) + return xtensa_encode_result_too_high; + *valp = val; + return xtensa_encode_result_ok; +} + +uint32 +decode_simm7 (uint32 val) +{ + if (val > 95) + val |= -32; + return val; +} + +xtensa_encode_result +encode_simm7 (uint32 *valp) +{ + uint32 val = *valp; + if ((signed int) val < -32) + return xtensa_encode_result_too_low; + if ((signed int) val > 95) + return xtensa_encode_result_too_high; + *valp = val; + return xtensa_encode_result_ok; +} + +uint32 +decode_simm8 (uint32 val) +{ + val = (val ^ 0x80) - 0x80; + return val; +} + +xtensa_encode_result +encode_simm8 (uint32 *valp) +{ + uint32 val = *valp; + if (((val + (1 << 7)) >> 8) != 0) + { + if ((signed int) val > 0) + return xtensa_encode_result_too_high; + else + return xtensa_encode_result_too_low; + } + *valp = val; + return xtensa_encode_result_ok; +} + +uint32 +decode_uimm12x8 (uint32 val) +{ + val <<= 3; + return val; +} + +xtensa_encode_result +encode_uimm12x8 (uint32 *valp) +{ + uint32 val = *valp; + if ((val & ((1 << 3) - 1)) != 0) + return xtensa_encode_result_align; + val = (signed int) val >> 3; + if ((val >> 12) != 0) + return xtensa_encode_result_too_high; + *valp = val; + return xtensa_encode_result_ok; +} + +uint32 +decode_sal (uint32 val) +{ + return val; +} + +xtensa_encode_result +encode_sal (uint32 *valp) +{ + uint32 val = *valp; + if ((val >> 5) != 0) + return xtensa_encode_result_too_high; + *valp = val; + return xtensa_encode_result_ok; +} + +uint32 +decode_uimm6 (uint32 val) +{ + return val; +} + +xtensa_encode_result +encode_uimm6 (uint32 *valp) +{ + uint32 val = *valp; + if ((val >> 6) != 0) + return xtensa_encode_result_too_high; + *valp = val; + return xtensa_encode_result_ok; +} + +uint32 +decode_sas4 (uint32 val) +{ + return val; +} + +xtensa_encode_result +encode_sas4 (uint32 *valp) +{ + uint32 val = *valp; + if ((val >> 1) != 0) + return xtensa_encode_result_too_high; + *valp = val; + return xtensa_encode_result_ok; +} + +uint32 +decode_uimm8 (uint32 val) +{ + return val; +} + +xtensa_encode_result +encode_uimm8 (uint32 *valp) +{ + uint32 val = *valp; + if ((val >> 8) != 0) + return xtensa_encode_result_too_high; + *valp = val; + return xtensa_encode_result_ok; +} + +uint32 +decode_uimm16x4 (uint32 val) +{ + val |= -1 << 16; + val <<= 2; + return val; +} + +xtensa_encode_result +encode_uimm16x4 (uint32 *valp) +{ + uint32 val = *valp; + if ((val & ((1 << 2) - 1)) != 0) + return xtensa_encode_result_align; + val = (signed int) val >> 2; + if ((signed int) val >> 16 != -1) + { + if ((signed int) val >= 0) + return xtensa_encode_result_too_high; + else + return xtensa_encode_result_too_low; + } + *valp = val; + return xtensa_encode_result_ok; +} + +uint32 +decode_sar (uint32 val) +{ + return val; +} + +xtensa_encode_result +encode_sar (uint32 *valp) +{ + uint32 val = *valp; + if ((val >> 5) != 0) + return xtensa_encode_result_too_high; + *valp = val; + return xtensa_encode_result_ok; +} + +uint32 +decode_sa4 (uint32 val) +{ + return val; +} + +xtensa_encode_result +encode_sa4 (uint32 *valp) +{ + uint32 val = *valp; + if ((val >> 1) != 0) + return xtensa_encode_result_too_high; + *valp = val; + return xtensa_encode_result_ok; +} + +uint32 +decode_sas (uint32 val) +{ + return val; +} + +xtensa_encode_result +encode_sas (uint32 *valp) +{ + uint32 val = *valp; + if ((val >> 5) != 0) + return xtensa_encode_result_too_high; + *valp = val; + return xtensa_encode_result_ok; +} + +uint32 +decode_imm6hi (uint32 val) +{ + return val; +} + +xtensa_encode_result +encode_imm6hi (uint32 *valp) +{ + uint32 val = *valp; + if ((val >> 2) != 0) + return xtensa_encode_result_too_high; + *valp = val; + return xtensa_encode_result_ok; +} + +uint32 +decode_bbi (uint32 val) +{ + return val; +} + +xtensa_encode_result +encode_bbi (uint32 *valp) +{ + uint32 val = *valp; + if ((val >> 5) != 0) + return xtensa_encode_result_too_high; + *valp = val; + return xtensa_encode_result_ok; +} + +uint32 +decode_uimm8x2 (uint32 val) +{ + val <<= 1; + return val; +} + +xtensa_encode_result +encode_uimm8x2 (uint32 *valp) +{ + uint32 val = *valp; + if ((val & ((1 << 1) - 1)) != 0) + return xtensa_encode_result_align; + val = (signed int) val >> 1; + if ((val >> 8) != 0) + return xtensa_encode_result_too_high; + *valp = val; + return xtensa_encode_result_ok; +} + +uint32 +decode_uimm8x4 (uint32 val) +{ + val <<= 2; + return val; +} + +xtensa_encode_result +encode_uimm8x4 (uint32 *valp) +{ + uint32 val = *valp; + if ((val & ((1 << 2) - 1)) != 0) + return xtensa_encode_result_align; + val = (signed int) val >> 2; + if ((val >> 8) != 0) + return xtensa_encode_result_too_high; + *valp = val; + return xtensa_encode_result_ok; +} + +static const uint32 mip32const_table[] = { + 32, + 31, + 30, + 29, + 28, + 27, + 26, + 25, + 24, + 23, + 22, + 21, + 20, + 19, + 18, + 17, + 16, + 15, + 14, + 13, + 12, + 11, + 10, + 9, + 8, + 7, + 6, + 5, + 4, + 3, + 2, + 1 +}; + +uint32 +decode_msalp32 (uint32 val) +{ + val = mip32const_table[val]; + return val; +} + +xtensa_encode_result +encode_msalp32 (uint32 *valp) +{ + uint32 val = *valp; + unsigned i; + for (i = 0; i < (1 << 5); i += 1) + if (mip32const_table[i] == val) goto found; + return xtensa_encode_result_not_in_table; + found: + val = i; + *valp = val; + return xtensa_encode_result_ok; +} + +uint32 +decode_bbi4 (uint32 val) +{ + return val; +} + +xtensa_encode_result +encode_bbi4 (uint32 *valp) +{ + uint32 val = *valp; + if ((val >> 1) != 0) + return xtensa_encode_result_too_high; + *valp = val; + return xtensa_encode_result_ok; +} + +static const uint32 i4p1const_table[] = { + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 16 +}; + +uint32 +decode_op2p1 (uint32 val) +{ + val = i4p1const_table[val]; + return val; +} + +xtensa_encode_result +encode_op2p1 (uint32 *valp) +{ + uint32 val = *valp; + unsigned i; + for (i = 0; i < (1 << 4); i += 1) + if (i4p1const_table[i] == val) goto found; + return xtensa_encode_result_not_in_table; + found: + val = i; + *valp = val; + return xtensa_encode_result_ok; +} + +uint32 +decode_soffsetx4 (uint32 val) +{ + val = (val ^ 0x20000) - 0x20000; + val <<= 2; + return val; +} + +xtensa_encode_result +encode_soffsetx4 (uint32 *valp) +{ + uint32 val = *valp; + if ((val & ((1 << 2) - 1)) != 0) + return xtensa_encode_result_align; + val = (signed int) val >> 2; + if (((val + (1 << 17)) >> 18) != 0) + { + if ((signed int) val > 0) + return xtensa_encode_result_too_high; + else + return xtensa_encode_result_too_low; + } + *valp = val; + return xtensa_encode_result_ok; +} + +uint32 +decode_imm6lo (uint32 val) +{ + return val; +} + +xtensa_encode_result +encode_imm6lo (uint32 *valp) +{ + uint32 val = *valp; + if ((val >> 4) != 0) + return xtensa_encode_result_too_high; + *valp = val; + return xtensa_encode_result_ok; +} + +uint32 +decode_imm12 (uint32 val) +{ + return val; +} + +xtensa_encode_result +encode_imm12 (uint32 *valp) +{ + uint32 val = *valp; + if ((val >> 12) != 0) + return xtensa_encode_result_too_high; + *valp = val; + return xtensa_encode_result_ok; +} + +static const uint32 b4const_table[] = { + -1, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 10, + 12, + 16, + 32, + 64, + 128, + 256 +}; + +uint32 +decode_b4const (uint32 val) +{ + val = b4const_table[val]; + return val; +} + +xtensa_encode_result +encode_b4const (uint32 *valp) +{ + uint32 val = *valp; + unsigned i; + for (i = 0; i < (1 << 4); i += 1) + if (b4const_table[i] == val) goto found; + return xtensa_encode_result_not_in_table; + found: + val = i; + *valp = val; + return xtensa_encode_result_ok; +} + +uint32 +decode_i (uint32 val) +{ + return val; +} + +xtensa_encode_result +encode_i (uint32 *valp) +{ + uint32 val = *valp; + if ((val >> 1) != 0) + return xtensa_encode_result_too_high; + *valp = val; + return xtensa_encode_result_ok; +} + +uint32 +decode_imm16 (uint32 val) +{ + return val; +} + +xtensa_encode_result +encode_imm16 (uint32 *valp) +{ + uint32 val = *valp; + if ((val >> 16) != 0) + return xtensa_encode_result_too_high; + *valp = val; + return xtensa_encode_result_ok; +} + +uint32 +decode_mn (uint32 val) +{ + return val; +} + +xtensa_encode_result +encode_mn (uint32 *valp) +{ + uint32 val = *valp; + if ((val >> 4) != 0) + return xtensa_encode_result_too_high; + *valp = val; + return xtensa_encode_result_ok; +} + +uint32 +decode_m (uint32 val) +{ + return val; +} + +xtensa_encode_result +encode_m (uint32 *valp) +{ + uint32 val = *valp; + if ((val >> 2) != 0) + return xtensa_encode_result_too_high; + *valp = val; + return xtensa_encode_result_ok; +} + +uint32 +decode_n (uint32 val) +{ + return val; +} + +xtensa_encode_result +encode_n (uint32 *valp) +{ + uint32 val = *valp; + if ((val >> 2) != 0) + return xtensa_encode_result_too_high; + *valp = val; + return xtensa_encode_result_ok; +} + +uint32 +decode_none (uint32 val) +{ + return val; +} + +xtensa_encode_result +encode_none (uint32 *valp) +{ + uint32 val = *valp; + if ((val >> 0) != 0) + return xtensa_encode_result_too_high; + *valp = val; + return xtensa_encode_result_ok; +} + +uint32 +decode_imm12b (uint32 val) +{ + return val; +} + +xtensa_encode_result +encode_imm12b (uint32 *valp) +{ + uint32 val = *valp; + if ((val >> 12) != 0) + return xtensa_encode_result_too_high; + *valp = val; + return xtensa_encode_result_ok; +} + +uint32 +decode_r (uint32 val) +{ + return val; +} + +xtensa_encode_result +encode_r (uint32 *valp) +{ + uint32 val = *valp; + if ((val >> 4) != 0) + return xtensa_encode_result_too_high; + *valp = val; + return xtensa_encode_result_ok; +} + +uint32 +decode_s (uint32 val) +{ + return val; +} + +xtensa_encode_result +encode_s (uint32 *valp) +{ + uint32 val = *valp; + if ((val >> 4) != 0) + return xtensa_encode_result_too_high; + *valp = val; + return xtensa_encode_result_ok; +} + +uint32 +decode_t (uint32 val) +{ + return val; +} + +xtensa_encode_result +encode_t (uint32 *valp) +{ + uint32 val = *valp; + if ((val >> 4) != 0) + return xtensa_encode_result_too_high; + *valp = val; + return xtensa_encode_result_ok; +} + +uint32 +decode_thi3 (uint32 val) +{ + return val; +} + +xtensa_encode_result +encode_thi3 (uint32 *valp) +{ + uint32 val = *valp; + if ((val >> 3) != 0) + return xtensa_encode_result_too_high; + *valp = val; + return xtensa_encode_result_ok; +} + +uint32 +decode_sae4 (uint32 val) +{ + return val; +} + +xtensa_encode_result +encode_sae4 (uint32 *valp) +{ + uint32 val = *valp; + if ((val >> 1) != 0) + return xtensa_encode_result_too_high; + *valp = val; + return xtensa_encode_result_ok; +} + +uint32 +decode_offset (uint32 val) +{ + return val; +} + +xtensa_encode_result +encode_offset (uint32 *valp) +{ + uint32 val = *valp; + if ((val >> 18) != 0) + return xtensa_encode_result_too_high; + *valp = val; + return xtensa_encode_result_ok; +} + +uint32 +decode_imm7hi (uint32 val) +{ + return val; +} + +xtensa_encode_result +encode_imm7hi (uint32 *valp) +{ + uint32 val = *valp; + if ((val >> 3) != 0) + return xtensa_encode_result_too_high; + *valp = val; + return xtensa_encode_result_ok; +} + +uint32 +decode_uimm4x16 (uint32 val) +{ + val <<= 4; + return val; +} + +xtensa_encode_result +encode_uimm4x16 (uint32 *valp) +{ + uint32 val = *valp; + if ((val & ((1 << 4) - 1)) != 0) + return xtensa_encode_result_align; + val = (signed int) val >> 4; + if ((val >> 4) != 0) + return xtensa_encode_result_too_high; + *valp = val; + return xtensa_encode_result_ok; +} + +uint32 +decode_simm12b (uint32 val) +{ + val = (val ^ 0x800) - 0x800; + return val; +} + +xtensa_encode_result +encode_simm12b (uint32 *valp) +{ + uint32 val = *valp; + if (((val + (1 << 11)) >> 12) != 0) + { + if ((signed int) val > 0) + return xtensa_encode_result_too_high; + else + return xtensa_encode_result_too_low; + } + *valp = val; + return xtensa_encode_result_ok; +} + +uint32 +decode_lsi4x4 (uint32 val) +{ + val <<= 2; + return val; +} + +xtensa_encode_result +encode_lsi4x4 (uint32 *valp) +{ + uint32 val = *valp; + if ((val & ((1 << 2) - 1)) != 0) + return xtensa_encode_result_align; + val = (signed int) val >> 2; + if ((val >> 4) != 0) + return xtensa_encode_result_too_high; + *valp = val; + return xtensa_encode_result_ok; +} + +uint32 +decode_z (uint32 val) +{ + return val; +} + +xtensa_encode_result +encode_z (uint32 *valp) +{ + uint32 val = *valp; + if ((val >> 1) != 0) + return xtensa_encode_result_too_high; + *valp = val; + return xtensa_encode_result_ok; +} + +uint32 +decode_simm12 (uint32 val) +{ + val = (val ^ 0x800) - 0x800; + return val; +} + +xtensa_encode_result +encode_simm12 (uint32 *valp) +{ + uint32 val = *valp; + if (((val + (1 << 11)) >> 12) != 0) + { + if ((signed int) val > 0) + return xtensa_encode_result_too_high; + else + return xtensa_encode_result_too_low; + } + *valp = val; + return xtensa_encode_result_ok; +} + +uint32 +decode_sr (uint32 val) +{ + return val; +} + +xtensa_encode_result +encode_sr (uint32 *valp) +{ + uint32 val = *valp; + if ((val >> 8) != 0) + return xtensa_encode_result_too_high; + *valp = val; + return xtensa_encode_result_ok; +} + +uint32 +decode_nimm4x2 (uint32 val) +{ + val |= -1 << 4; + val <<= 2; + return val; +} + +xtensa_encode_result +encode_nimm4x2 (uint32 *valp) +{ + uint32 val = *valp; + if ((val & ((1 << 2) - 1)) != 0) + return xtensa_encode_result_align; + val = (signed int) val >> 2; + if ((signed int) val >> 4 != -1) + { + if ((signed int) val >= 0) + return xtensa_encode_result_too_high; + else + return xtensa_encode_result_too_low; + } + *valp = val; + return xtensa_encode_result_ok; +} + + + +uint32 do_reloc_l (uint32, uint32); +uint32 undo_reloc_l (uint32, uint32); +uint32 do_reloc_L (uint32, uint32); +uint32 undo_reloc_L (uint32, uint32); +uint32 do_reloc_r (uint32, uint32); +uint32 undo_reloc_r (uint32, uint32); + + +uint32 +do_reloc_l (uint32 addr, uint32 pc) +{ + return addr - pc - 4; +} + +uint32 +undo_reloc_l (uint32 offset, uint32 pc) +{ + return pc + offset + 4; +} + +uint32 +do_reloc_L (uint32 addr, uint32 pc) +{ + return addr - (pc & -4) - 4; +} + +uint32 +undo_reloc_L (uint32 offset, uint32 pc) +{ + return (pc & -4) + offset + 4; +} + +uint32 +do_reloc_r (uint32 addr, uint32 pc) +{ + return addr - ((pc+3) & -4); +} + +uint32 +undo_reloc_r (uint32 offset, uint32 pc) +{ + return ((pc+3) & -4) + offset; +} + +static xtensa_operand_internal iib4const_operand = { + "i", + '<', + 0, + get_r_field, + set_r_field, + encode_b4const, + decode_b4const, + 0, + 0 +}; + +static xtensa_operand_internal iiuimm8_operand = { + "i", + '<', + 0, + get_imm8_field, + set_imm8_field, + encode_uimm8, + decode_uimm8, + 0, + 0 +}; + +static xtensa_operand_internal lisoffsetx4_operand = { + "L", + '<', + 1, + get_offset_field, + set_offset_field, + encode_soffsetx4, + decode_soffsetx4, + do_reloc_L, + undo_reloc_L, +}; + +static xtensa_operand_internal iisimm8x256_operand = { + "i", + '<', + 0, + get_imm8_field, + set_imm8_field, + encode_simm8x256, + decode_simm8x256, + 0, + 0 +}; + +static xtensa_operand_internal lisimm12_operand = { + "l", + '<', + 1, + get_imm12_field, + set_imm12_field, + encode_simm12, + decode_simm12, + do_reloc_l, + undo_reloc_l, +}; + +static xtensa_operand_internal iiop2p1_operand = { + "i", + '<', + 0, + get_op2_field, + set_op2_field, + encode_op2p1, + decode_op2p1, + 0, + 0 +}; + +static xtensa_operand_internal iisae_operand = { + "i", + '<', + 0, + get_sae_field, + set_sae_field, + encode_sae, + decode_sae, + 0, + 0 +}; + +static xtensa_operand_internal iis_operand = { + "i", + '<', + 0, + get_s_field, + set_s_field, + encode_s, + decode_s, + 0, + 0 +}; + +static xtensa_operand_internal iit_operand = { + "i", + '<', + 0, + get_t_field, + set_t_field, + encode_t, + decode_t, + 0, + 0 +}; + +static xtensa_operand_internal iisimm12b_operand = { + "i", + '<', + 0, + get_imm12b_field, + set_imm12b_field, + encode_simm12b, + decode_simm12b, + 0, + 0 +}; + +static xtensa_operand_internal iinimm4x2_operand = { + "i", + '<', + 0, + get_imm4_field, + set_imm4_field, + encode_nimm4x2, + decode_nimm4x2, + 0, + 0 +}; + +static xtensa_operand_internal iiuimm4x16_operand = { + "i", + '<', + 0, + get_op2_field, + set_op2_field, + encode_uimm4x16, + decode_uimm4x16, + 0, + 0 +}; + +static xtensa_operand_internal abs_operand = { + "a", + '=', + 0, + get_s_field, + set_s_field, + encode_s, + decode_s, + 0, + 0 +}; + +static xtensa_operand_internal iisar_operand = { + "i", + '<', + 0, + get_sar_field, + set_sar_field, + encode_sar, + decode_sar, + 0, + 0 +}; + +static xtensa_operand_internal abt_operand = { + "a", + '=', + 0, + get_t_field, + set_t_field, + encode_t, + decode_t, + 0, + 0 +}; + +static xtensa_operand_internal iisas_operand = { + "i", + '<', + 0, + get_sas_field, + set_sas_field, + encode_sas, + decode_sas, + 0, + 0 +}; + +static xtensa_operand_internal amr_operand = { + "a", + '=', + 0, + get_r_field, + set_r_field, + encode_r, + decode_r, + 0, + 0 +}; + +static xtensa_operand_internal iib4constu_operand = { + "i", + '<', + 0, + get_r_field, + set_r_field, + encode_b4constu, + decode_b4constu, + 0, + 0 +}; + +static xtensa_operand_internal iisr_operand = { + "i", + '<', + 0, + get_sr_field, + set_sr_field, + encode_sr, + decode_sr, + 0, + 0 +}; + +static xtensa_operand_internal iibbi_operand = { + "i", + '<', + 0, + get_bbi_field, + set_bbi_field, + encode_bbi, + decode_bbi, + 0, + 0 +}; + +static xtensa_operand_internal iiai4const_operand = { + "i", + '<', + 0, + get_t_field, + set_t_field, + encode_ai4const, + decode_ai4const, + 0, + 0 +}; + +static xtensa_operand_internal iiuimm12x8_operand = { + "i", + '<', + 0, + get_imm12_field, + set_imm12_field, + encode_uimm12x8, + decode_uimm12x8, + 0, + 0 +}; + +static xtensa_operand_internal riuimm16x4_operand = { + "r", + '<', + 1, + get_imm16_field, + set_imm16_field, + encode_uimm16x4, + decode_uimm16x4, + do_reloc_r, + undo_reloc_r, +}; + +static xtensa_operand_internal lisimm8_operand = { + "l", + '<', + 1, + get_imm8_field, + set_imm8_field, + encode_simm8, + decode_simm8, + do_reloc_l, + undo_reloc_l, +}; + +static xtensa_operand_internal iilsi4x4_operand = { + "i", + '<', + 0, + get_r_field, + set_r_field, + encode_lsi4x4, + decode_lsi4x4, + 0, + 0 +}; + +static xtensa_operand_internal iiuimm8x2_operand = { + "i", + '<', + 0, + get_imm8_field, + set_imm8_field, + encode_uimm8x2, + decode_uimm8x2, + 0, + 0 +}; + +static xtensa_operand_internal iisimm4_operand = { + "i", + '<', + 0, + get_mn_field, + set_mn_field, + encode_simm4, + decode_simm4, + 0, + 0 +}; + +static xtensa_operand_internal iimsalp32_operand = { + "i", + '<', + 0, + get_sal_field, + set_sal_field, + encode_msalp32, + decode_msalp32, + 0, + 0 +}; + +static xtensa_operand_internal liuimm6_operand = { + "l", + '<', + 1, + get_imm6_field, + set_imm6_field, + encode_uimm6, + decode_uimm6, + do_reloc_l, + undo_reloc_l, +}; + +static xtensa_operand_internal iiuimm8x4_operand = { + "i", + '<', + 0, + get_imm8_field, + set_imm8_field, + encode_uimm8x4, + decode_uimm8x4, + 0, + 0 +}; + +static xtensa_operand_internal lisoffset_operand = { + "l", + '<', + 1, + get_offset_field, + set_offset_field, + encode_soffset, + decode_soffset, + do_reloc_l, + undo_reloc_l, +}; + +static xtensa_operand_internal iisimm7_operand = { + "i", + '<', + 0, + get_imm7_field, + set_imm7_field, + encode_simm7, + decode_simm7, + 0, + 0 +}; + +static xtensa_operand_internal ais_operand = { + "a", + '<', + 0, + get_s_field, + set_s_field, + encode_s, + decode_s, + 0, + 0 +}; + +static xtensa_operand_internal liuimm8_operand = { + "l", + '<', + 1, + get_imm8_field, + set_imm8_field, + encode_uimm8, + decode_uimm8, + do_reloc_l, + undo_reloc_l, +}; + +static xtensa_operand_internal ait_operand = { + "a", + '<', + 0, + get_t_field, + set_t_field, + encode_t, + decode_t, + 0, + 0 +}; + +static xtensa_operand_internal iisimm8_operand = { + "i", + '<', + 0, + get_imm8_field, + set_imm8_field, + encode_simm8, + decode_simm8, + 0, + 0 +}; + +static xtensa_operand_internal aor_operand = { + "a", + '>', + 0, + get_r_field, + set_r_field, + encode_r, + decode_r, + 0, + 0 +}; + +static xtensa_operand_internal aos_operand = { + "a", + '>', + 0, + get_s_field, + set_s_field, + encode_s, + decode_s, + 0, + 0 +}; + +static xtensa_operand_internal aot_operand = { + "a", + '>', + 0, + get_t_field, + set_t_field, + encode_t, + decode_t, + 0, + 0 +}; + +static xtensa_iclass_internal nopn_iclass = { + 0, + 0 +}; + +static xtensa_operand_internal *movi_operand_list[] = { + &aot_operand, + &iisimm12b_operand +}; + +static xtensa_iclass_internal movi_iclass = { + 2, + &movi_operand_list[0] +}; + +static xtensa_operand_internal *bsi8u_operand_list[] = { + &ais_operand, + &iib4constu_operand, + &lisimm8_operand +}; + +static xtensa_iclass_internal bsi8u_iclass = { + 3, + &bsi8u_operand_list[0] +}; + +static xtensa_operand_internal *itlb_operand_list[] = { + &ais_operand +}; + +static xtensa_iclass_internal itlb_iclass = { + 1, + &itlb_operand_list[0] +}; + +static xtensa_operand_internal *shiftst_operand_list[] = { + &aor_operand, + &ais_operand, + &ait_operand +}; + +static xtensa_iclass_internal shiftst_iclass = { + 3, + &shiftst_operand_list[0] +}; + +static xtensa_operand_internal *l32r_operand_list[] = { + &aot_operand, + &riuimm16x4_operand +}; + +static xtensa_iclass_internal l32r_iclass = { + 2, + &l32r_operand_list[0] +}; + +static xtensa_iclass_internal rfe_iclass = { + 0, + 0 +}; + +static xtensa_operand_internal *wait_operand_list[] = { + &iis_operand +}; + +static xtensa_iclass_internal wait_iclass = { + 1, + &wait_operand_list[0] +}; + +static xtensa_operand_internal *rfi_operand_list[] = { + &iis_operand +}; + +static xtensa_iclass_internal rfi_iclass = { + 1, + &rfi_operand_list[0] +}; + +static xtensa_operand_internal *movz_operand_list[] = { + &amr_operand, + &ais_operand, + &ait_operand +}; + +static xtensa_iclass_internal movz_iclass = { + 3, + &movz_operand_list[0] +}; + +static xtensa_operand_internal *callx_operand_list[] = { + &ais_operand +}; + +static xtensa_iclass_internal callx_iclass = { + 1, + &callx_operand_list[0] +}; + +static xtensa_operand_internal *mov_n_operand_list[] = { + &aot_operand, + &ais_operand +}; + +static xtensa_iclass_internal mov_n_iclass = { + 2, + &mov_n_operand_list[0] +}; + +static xtensa_operand_internal *loadi4_operand_list[] = { + &aot_operand, + &ais_operand, + &iilsi4x4_operand +}; + +static xtensa_iclass_internal loadi4_iclass = { + 3, + &loadi4_operand_list[0] +}; + +static xtensa_operand_internal *exti_operand_list[] = { + &aor_operand, + &ait_operand, + &iisae_operand, + &iiop2p1_operand +}; + +static xtensa_iclass_internal exti_iclass = { + 4, + &exti_operand_list[0] +}; + +static xtensa_operand_internal *break_operand_list[] = { + &iis_operand, + &iit_operand +}; + +static xtensa_iclass_internal break_iclass = { + 2, + &break_operand_list[0] +}; + +static xtensa_operand_internal *slli_operand_list[] = { + &aor_operand, + &ais_operand, + &iimsalp32_operand +}; + +static xtensa_iclass_internal slli_iclass = { + 3, + &slli_operand_list[0] +}; + +static xtensa_operand_internal *s16i_operand_list[] = { + &ait_operand, + &ais_operand, + &iiuimm8x2_operand +}; + +static xtensa_iclass_internal s16i_iclass = { + 3, + &s16i_operand_list[0] +}; + +static xtensa_operand_internal *call_operand_list[] = { + &lisoffsetx4_operand +}; + +static xtensa_iclass_internal call_iclass = { + 1, + &call_operand_list[0] +}; + +static xtensa_operand_internal *shifts_operand_list[] = { + &aor_operand, + &ais_operand +}; + +static xtensa_iclass_internal shifts_iclass = { + 2, + &shifts_operand_list[0] +}; + +static xtensa_operand_internal *shiftt_operand_list[] = { + &aor_operand, + &ait_operand +}; + +static xtensa_iclass_internal shiftt_iclass = { + 2, + &shiftt_operand_list[0] +}; + +static xtensa_operand_internal *rotw_operand_list[] = { + &iisimm4_operand +}; + +static xtensa_iclass_internal rotw_iclass = { + 1, + &rotw_operand_list[0] +}; + +static xtensa_operand_internal *addsub_operand_list[] = { + &aor_operand, + &ais_operand, + &ait_operand +}; + +static xtensa_iclass_internal addsub_iclass = { + 3, + &addsub_operand_list[0] +}; + +static xtensa_operand_internal *l8i_operand_list[] = { + &aot_operand, + &ais_operand, + &iiuimm8_operand +}; + +static xtensa_iclass_internal l8i_iclass = { + 3, + &l8i_operand_list[0] +}; + +static xtensa_operand_internal *sari_operand_list[] = { + &iisas_operand +}; + +static xtensa_iclass_internal sari_iclass = { + 1, + &sari_operand_list[0] +}; + +static xtensa_operand_internal *xsr_operand_list[] = { + &abt_operand, + &iisr_operand +}; + +static xtensa_iclass_internal xsr_iclass = { + 2, + &xsr_operand_list[0] +}; + +static xtensa_operand_internal *rsil_operand_list[] = { + &aot_operand, + &iis_operand +}; + +static xtensa_iclass_internal rsil_iclass = { + 2, + &rsil_operand_list[0] +}; + +static xtensa_operand_internal *bst8_operand_list[] = { + &ais_operand, + &ait_operand, + &lisimm8_operand +}; + +static xtensa_iclass_internal bst8_iclass = { + 3, + &bst8_operand_list[0] +}; + +static xtensa_operand_internal *addi_operand_list[] = { + &aot_operand, + &ais_operand, + &iisimm8_operand +}; + +static xtensa_iclass_internal addi_iclass = { + 3, + &addi_operand_list[0] +}; + +static xtensa_operand_internal *callx12_operand_list[] = { + &ais_operand +}; + +static xtensa_iclass_internal callx12_iclass = { + 1, + &callx12_operand_list[0] +}; + +static xtensa_operand_internal *bsi8_operand_list[] = { + &ais_operand, + &iib4const_operand, + &lisimm8_operand +}; + +static xtensa_iclass_internal bsi8_iclass = { + 3, + &bsi8_operand_list[0] +}; + +static xtensa_operand_internal *jumpx_operand_list[] = { + &ais_operand +}; + +static xtensa_iclass_internal jumpx_iclass = { + 1, + &jumpx_operand_list[0] +}; + +static xtensa_iclass_internal retn_iclass = { + 0, + 0 +}; + +static xtensa_operand_internal *nsa_operand_list[] = { + &aot_operand, + &ais_operand +}; + +static xtensa_iclass_internal nsa_iclass = { + 2, + &nsa_operand_list[0] +}; + +static xtensa_operand_internal *storei4_operand_list[] = { + &ait_operand, + &ais_operand, + &iilsi4x4_operand +}; + +static xtensa_iclass_internal storei4_iclass = { + 3, + &storei4_operand_list[0] +}; + +static xtensa_operand_internal *wtlb_operand_list[] = { + &ait_operand, + &ais_operand +}; + +static xtensa_iclass_internal wtlb_iclass = { + 2, + &wtlb_operand_list[0] +}; + +static xtensa_operand_internal *dce_operand_list[] = { + &ais_operand, + &iiuimm4x16_operand +}; + +static xtensa_iclass_internal dce_iclass = { + 2, + &dce_operand_list[0] +}; + +static xtensa_operand_internal *l16i_operand_list[] = { + &aot_operand, + &ais_operand, + &iiuimm8x2_operand +}; + +static xtensa_iclass_internal l16i_iclass = { + 3, + &l16i_operand_list[0] +}; + +static xtensa_operand_internal *callx4_operand_list[] = { + &ais_operand +}; + +static xtensa_iclass_internal callx4_iclass = { + 1, + &callx4_operand_list[0] +}; + +static xtensa_operand_internal *callx8_operand_list[] = { + &ais_operand +}; + +static xtensa_iclass_internal callx8_iclass = { + 1, + &callx8_operand_list[0] +}; + +static xtensa_operand_internal *movsp_operand_list[] = { + &aot_operand, + &ais_operand +}; + +static xtensa_iclass_internal movsp_iclass = { + 2, + &movsp_operand_list[0] +}; + +static xtensa_operand_internal *wsr_operand_list[] = { + &ait_operand, + &iisr_operand +}; + +static xtensa_iclass_internal wsr_iclass = { + 2, + &wsr_operand_list[0] +}; + +static xtensa_operand_internal *call12_operand_list[] = { + &lisoffsetx4_operand +}; + +static xtensa_iclass_internal call12_iclass = { + 1, + &call12_operand_list[0] +}; + +static xtensa_operand_internal *call4_operand_list[] = { + &lisoffsetx4_operand +}; + +static xtensa_iclass_internal call4_iclass = { + 1, + &call4_operand_list[0] +}; + +static xtensa_operand_internal *addmi_operand_list[] = { + &aot_operand, + &ais_operand, + &iisimm8x256_operand +}; + +static xtensa_iclass_internal addmi_iclass = { + 3, + &addmi_operand_list[0] +}; + +static xtensa_operand_internal *bit_operand_list[] = { + &aor_operand, + &ais_operand, + &ait_operand +}; + +static xtensa_iclass_internal bit_iclass = { + 3, + &bit_operand_list[0] +}; + +static xtensa_operand_internal *call8_operand_list[] = { + &lisoffsetx4_operand +}; + +static xtensa_iclass_internal call8_iclass = { + 1, + &call8_operand_list[0] +}; + +static xtensa_iclass_internal itlba_iclass = { + 0, + 0 +}; + +static xtensa_operand_internal *break_n_operand_list[] = { + &iis_operand +}; + +static xtensa_iclass_internal break_n_iclass = { + 1, + &break_n_operand_list[0] +}; + +static xtensa_operand_internal *sar_operand_list[] = { + &ais_operand +}; + +static xtensa_iclass_internal sar_iclass = { + 1, + &sar_operand_list[0] +}; + +static xtensa_operand_internal *s32e_operand_list[] = { + &ait_operand, + &ais_operand, + &iinimm4x2_operand +}; + +static xtensa_iclass_internal s32e_iclass = { + 3, + &s32e_operand_list[0] +}; + +static xtensa_operand_internal *bz6_operand_list[] = { + &ais_operand, + &liuimm6_operand +}; + +static xtensa_iclass_internal bz6_iclass = { + 2, + &bz6_operand_list[0] +}; + +static xtensa_operand_internal *loop_operand_list[] = { + &ais_operand, + &liuimm8_operand +}; + +static xtensa_iclass_internal loop_iclass = { + 2, + &loop_operand_list[0] +}; + +static xtensa_operand_internal *rsr_operand_list[] = { + &aot_operand, + &iisr_operand +}; + +static xtensa_iclass_internal rsr_iclass = { + 2, + &rsr_operand_list[0] +}; + +static xtensa_operand_internal *icache_operand_list[] = { + &ais_operand, + &iiuimm8x4_operand +}; + +static xtensa_iclass_internal icache_iclass = { + 2, + &icache_operand_list[0] +}; + +static xtensa_operand_internal *s8i_operand_list[] = { + &ait_operand, + &ais_operand, + &iiuimm8_operand +}; + +static xtensa_iclass_internal s8i_iclass = { + 3, + &s8i_operand_list[0] +}; + +static xtensa_iclass_internal return_iclass = { + 0, + 0 +}; + +static xtensa_operand_internal *dcache_operand_list[] = { + &ais_operand, + &iiuimm8x4_operand +}; + +static xtensa_iclass_internal dcache_iclass = { + 2, + &dcache_operand_list[0] +}; + +static xtensa_operand_internal *s32i_operand_list[] = { + &ait_operand, + &ais_operand, + &iiuimm8x4_operand +}; + +static xtensa_iclass_internal s32i_iclass = { + 3, + &s32i_operand_list[0] +}; + +static xtensa_operand_internal *jump_operand_list[] = { + &lisoffset_operand +}; + +static xtensa_iclass_internal jump_iclass = { + 1, + &jump_operand_list[0] +}; + +static xtensa_operand_internal *addi_n_operand_list[] = { + &aor_operand, + &ais_operand, + &iiai4const_operand +}; + +static xtensa_iclass_internal addi_n_iclass = { + 3, + &addi_n_operand_list[0] +}; + +static xtensa_iclass_internal sync_iclass = { + 0, + 0 +}; + +static xtensa_operand_internal *neg_operand_list[] = { + &aor_operand, + &ait_operand +}; + +static xtensa_iclass_internal neg_iclass = { + 2, + &neg_operand_list[0] +}; + +static xtensa_iclass_internal syscall_iclass = { + 0, + 0 +}; + +static xtensa_operand_internal *bsz12_operand_list[] = { + &ais_operand, + &lisimm12_operand +}; + +static xtensa_iclass_internal bsz12_iclass = { + 2, + &bsz12_operand_list[0] +}; + +static xtensa_iclass_internal excw_iclass = { + 0, + 0 +}; + +static xtensa_operand_internal *movi_n_operand_list[] = { + &aos_operand, + &iisimm7_operand +}; + +static xtensa_iclass_internal movi_n_iclass = { + 2, + &movi_n_operand_list[0] +}; + +static xtensa_operand_internal *rtlb_operand_list[] = { + &aot_operand, + &ais_operand +}; + +static xtensa_iclass_internal rtlb_iclass = { + 2, + &rtlb_operand_list[0] +}; + +static xtensa_operand_internal *actl_operand_list[] = { + &aot_operand, + &ais_operand +}; + +static xtensa_iclass_internal actl_iclass = { + 2, + &actl_operand_list[0] +}; + +static xtensa_operand_internal *srli_operand_list[] = { + &aor_operand, + &ait_operand, + &iis_operand +}; + +static xtensa_iclass_internal srli_iclass = { + 3, + &srli_operand_list[0] +}; + +static xtensa_operand_internal *bsi8b_operand_list[] = { + &ais_operand, + &iibbi_operand, + &lisimm8_operand +}; + +static xtensa_iclass_internal bsi8b_iclass = { + 3, + &bsi8b_operand_list[0] +}; + +static xtensa_operand_internal *acts_operand_list[] = { + &ait_operand, + &ais_operand +}; + +static xtensa_iclass_internal acts_iclass = { + 2, + &acts_operand_list[0] +}; + +static xtensa_operand_internal *add_n_operand_list[] = { + &aor_operand, + &ais_operand, + &ait_operand +}; + +static xtensa_iclass_internal add_n_iclass = { + 3, + &add_n_operand_list[0] +}; + +static xtensa_operand_internal *srai_operand_list[] = { + &aor_operand, + &ait_operand, + &iisar_operand +}; + +static xtensa_iclass_internal srai_iclass = { + 3, + &srai_operand_list[0] +}; + +static xtensa_operand_internal *entry_operand_list[] = { + &abs_operand, + &iiuimm12x8_operand +}; + +static xtensa_iclass_internal entry_iclass = { + 2, + &entry_operand_list[0] +}; + +static xtensa_operand_internal *l32e_operand_list[] = { + &aot_operand, + &ais_operand, + &iinimm4x2_operand +}; + +static xtensa_iclass_internal l32e_iclass = { + 3, + &l32e_operand_list[0] +}; + +static xtensa_operand_internal *dpf_operand_list[] = { + &ais_operand, + &iiuimm8x4_operand +}; + +static xtensa_iclass_internal dpf_iclass = { + 2, + &dpf_operand_list[0] +}; + +static xtensa_operand_internal *l32i_operand_list[] = { + &aot_operand, + &ais_operand, + &iiuimm8x4_operand +}; + +static xtensa_iclass_internal l32i_iclass = { + 3, + &l32i_operand_list[0] +}; + +static xtensa_insnbuf abs_template (void); +static xtensa_insnbuf add_template (void); +static xtensa_insnbuf add_n_template (void); +static xtensa_insnbuf addi_template (void); +static xtensa_insnbuf addi_n_template (void); +static xtensa_insnbuf addmi_template (void); +static xtensa_insnbuf addx2_template (void); +static xtensa_insnbuf addx4_template (void); +static xtensa_insnbuf addx8_template (void); +static xtensa_insnbuf and_template (void); +static xtensa_insnbuf ball_template (void); +static xtensa_insnbuf bany_template (void); +static xtensa_insnbuf bbc_template (void); +static xtensa_insnbuf bbci_template (void); +static xtensa_insnbuf bbs_template (void); +static xtensa_insnbuf bbsi_template (void); +static xtensa_insnbuf beq_template (void); +static xtensa_insnbuf beqi_template (void); +static xtensa_insnbuf beqz_template (void); +static xtensa_insnbuf beqz_n_template (void); +static xtensa_insnbuf bge_template (void); +static xtensa_insnbuf bgei_template (void); +static xtensa_insnbuf bgeu_template (void); +static xtensa_insnbuf bgeui_template (void); +static xtensa_insnbuf bgez_template (void); +static xtensa_insnbuf blt_template (void); +static xtensa_insnbuf blti_template (void); +static xtensa_insnbuf bltu_template (void); +static xtensa_insnbuf bltui_template (void); +static xtensa_insnbuf bltz_template (void); +static xtensa_insnbuf bnall_template (void); +static xtensa_insnbuf bne_template (void); +static xtensa_insnbuf bnei_template (void); +static xtensa_insnbuf bnez_template (void); +static xtensa_insnbuf bnez_n_template (void); +static xtensa_insnbuf bnone_template (void); +static xtensa_insnbuf break_template (void); +static xtensa_insnbuf break_n_template (void); +static xtensa_insnbuf call0_template (void); +static xtensa_insnbuf call12_template (void); +static xtensa_insnbuf call4_template (void); +static xtensa_insnbuf call8_template (void); +static xtensa_insnbuf callx0_template (void); +static xtensa_insnbuf callx12_template (void); +static xtensa_insnbuf callx4_template (void); +static xtensa_insnbuf callx8_template (void); +static xtensa_insnbuf dhi_template (void); +static xtensa_insnbuf dhwb_template (void); +static xtensa_insnbuf dhwbi_template (void); +static xtensa_insnbuf dii_template (void); +static xtensa_insnbuf diwb_template (void); +static xtensa_insnbuf diwbi_template (void); +static xtensa_insnbuf dpfr_template (void); +static xtensa_insnbuf dpfro_template (void); +static xtensa_insnbuf dpfw_template (void); +static xtensa_insnbuf dpfwo_template (void); +static xtensa_insnbuf dsync_template (void); +static xtensa_insnbuf entry_template (void); +static xtensa_insnbuf esync_template (void); +static xtensa_insnbuf excw_template (void); +static xtensa_insnbuf extui_template (void); +static xtensa_insnbuf idtlb_template (void); +static xtensa_insnbuf idtlba_template (void); +static xtensa_insnbuf ihi_template (void); +static xtensa_insnbuf iii_template (void); +static xtensa_insnbuf iitlb_template (void); +static xtensa_insnbuf iitlba_template (void); +static xtensa_insnbuf ipf_template (void); +static xtensa_insnbuf isync_template (void); +static xtensa_insnbuf j_template (void); +static xtensa_insnbuf jx_template (void); +static xtensa_insnbuf l16si_template (void); +static xtensa_insnbuf l16ui_template (void); +static xtensa_insnbuf l32e_template (void); +static xtensa_insnbuf l32i_template (void); +static xtensa_insnbuf l32i_n_template (void); +static xtensa_insnbuf l32r_template (void); +static xtensa_insnbuf l8ui_template (void); +static xtensa_insnbuf ldct_template (void); +static xtensa_insnbuf lict_template (void); +static xtensa_insnbuf licw_template (void); +static xtensa_insnbuf loop_template (void); +static xtensa_insnbuf loopgtz_template (void); +static xtensa_insnbuf loopnez_template (void); +static xtensa_insnbuf memw_template (void); +static xtensa_insnbuf mov_n_template (void); +static xtensa_insnbuf moveqz_template (void); +static xtensa_insnbuf movgez_template (void); +static xtensa_insnbuf movi_template (void); +static xtensa_insnbuf movi_n_template (void); +static xtensa_insnbuf movltz_template (void); +static xtensa_insnbuf movnez_template (void); +static xtensa_insnbuf movsp_template (void); +static xtensa_insnbuf neg_template (void); +static xtensa_insnbuf nop_n_template (void); +static xtensa_insnbuf nsa_template (void); +static xtensa_insnbuf nsau_template (void); +static xtensa_insnbuf or_template (void); +static xtensa_insnbuf pdtlb_template (void); +static xtensa_insnbuf pitlb_template (void); +static xtensa_insnbuf rdtlb0_template (void); +static xtensa_insnbuf rdtlb1_template (void); +static xtensa_insnbuf ret_template (void); +static xtensa_insnbuf ret_n_template (void); +static xtensa_insnbuf retw_template (void); +static xtensa_insnbuf retw_n_template (void); +static xtensa_insnbuf rfde_template (void); +static xtensa_insnbuf rfe_template (void); +static xtensa_insnbuf rfi_template (void); +static xtensa_insnbuf rfwo_template (void); +static xtensa_insnbuf rfwu_template (void); +static xtensa_insnbuf ritlb0_template (void); +static xtensa_insnbuf ritlb1_template (void); +static xtensa_insnbuf rotw_template (void); +static xtensa_insnbuf rsil_template (void); +static xtensa_insnbuf rsr_template (void); +static xtensa_insnbuf rsync_template (void); +static xtensa_insnbuf s16i_template (void); +static xtensa_insnbuf s32e_template (void); +static xtensa_insnbuf s32i_template (void); +static xtensa_insnbuf s32i_n_template (void); +static xtensa_insnbuf s8i_template (void); +static xtensa_insnbuf sdct_template (void); +static xtensa_insnbuf sict_template (void); +static xtensa_insnbuf sicw_template (void); +static xtensa_insnbuf simcall_template (void); +static xtensa_insnbuf sll_template (void); +static xtensa_insnbuf slli_template (void); +static xtensa_insnbuf sra_template (void); +static xtensa_insnbuf srai_template (void); +static xtensa_insnbuf src_template (void); +static xtensa_insnbuf srl_template (void); +static xtensa_insnbuf srli_template (void); +static xtensa_insnbuf ssa8b_template (void); +static xtensa_insnbuf ssa8l_template (void); +static xtensa_insnbuf ssai_template (void); +static xtensa_insnbuf ssl_template (void); +static xtensa_insnbuf ssr_template (void); +static xtensa_insnbuf sub_template (void); +static xtensa_insnbuf subx2_template (void); +static xtensa_insnbuf subx4_template (void); +static xtensa_insnbuf subx8_template (void); +static xtensa_insnbuf syscall_template (void); +static xtensa_insnbuf waiti_template (void); +static xtensa_insnbuf wdtlb_template (void); +static xtensa_insnbuf witlb_template (void); +static xtensa_insnbuf wsr_template (void); +static xtensa_insnbuf xor_template (void); +static xtensa_insnbuf xsr_template (void); + +static xtensa_insnbuf +abs_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00001006 }; + return &template[0]; +} + +static xtensa_insnbuf +add_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00000008 }; + return &template[0]; +} + +static xtensa_insnbuf +add_n_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00a00000 }; + return &template[0]; +} + +static xtensa_insnbuf +addi_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00200c00 }; + return &template[0]; +} + +static xtensa_insnbuf +addi_n_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00b00000 }; + return &template[0]; +} + +static xtensa_insnbuf +addmi_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00200d00 }; + return &template[0]; +} + +static xtensa_insnbuf +addx2_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00000009 }; + return &template[0]; +} + +static xtensa_insnbuf +addx4_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x0000000a }; + return &template[0]; +} + +static xtensa_insnbuf +addx8_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x0000000b }; + return &template[0]; +} + +static xtensa_insnbuf +and_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00000001 }; + return &template[0]; +} + +static xtensa_insnbuf +ball_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00700400 }; + return &template[0]; +} + +static xtensa_insnbuf +bany_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00700800 }; + return &template[0]; +} + +static xtensa_insnbuf +bbc_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00700500 }; + return &template[0]; +} + +static xtensa_insnbuf +bbci_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00700600 }; + return &template[0]; +} + +static xtensa_insnbuf +bbs_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00700d00 }; + return &template[0]; +} + +static xtensa_insnbuf +bbsi_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00700e00 }; + return &template[0]; +} + +static xtensa_insnbuf +beq_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00700100 }; + return &template[0]; +} + +static xtensa_insnbuf +beqi_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00680000 }; + return &template[0]; +} + +static xtensa_insnbuf +beqz_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00640000 }; + return &template[0]; +} + +static xtensa_insnbuf +beqz_n_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00c80000 }; + return &template[0]; +} + +static xtensa_insnbuf +bge_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00700a00 }; + return &template[0]; +} + +static xtensa_insnbuf +bgei_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x006b0000 }; + return &template[0]; +} + +static xtensa_insnbuf +bgeu_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00700b00 }; + return &template[0]; +} + +static xtensa_insnbuf +bgeui_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x006f0000 }; + return &template[0]; +} + +static xtensa_insnbuf +bgez_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00670000 }; + return &template[0]; +} + +static xtensa_insnbuf +blt_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00700200 }; + return &template[0]; +} + +static xtensa_insnbuf +blti_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x006a0000 }; + return &template[0]; +} + +static xtensa_insnbuf +bltu_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00700300 }; + return &template[0]; +} + +static xtensa_insnbuf +bltui_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x006e0000 }; + return &template[0]; +} + +static xtensa_insnbuf +bltz_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00660000 }; + return &template[0]; +} + +static xtensa_insnbuf +bnall_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00700c00 }; + return &template[0]; +} + +static xtensa_insnbuf +bne_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00700900 }; + return &template[0]; +} + +static xtensa_insnbuf +bnei_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00690000 }; + return &template[0]; +} + +static xtensa_insnbuf +bnez_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00650000 }; + return &template[0]; +} + +static xtensa_insnbuf +bnez_n_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00cc0000 }; + return &template[0]; +} + +static xtensa_insnbuf +bnone_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00700000 }; + return &template[0]; +} + +static xtensa_insnbuf +break_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00000400 }; + return &template[0]; +} + +static xtensa_insnbuf +break_n_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00d20f00 }; + return &template[0]; +} + +static xtensa_insnbuf +call0_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00500000 }; + return &template[0]; +} + +static xtensa_insnbuf +call12_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x005c0000 }; + return &template[0]; +} + +static xtensa_insnbuf +call4_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00540000 }; + return &template[0]; +} + +static xtensa_insnbuf +call8_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00580000 }; + return &template[0]; +} + +static xtensa_insnbuf +callx0_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00030000 }; + return &template[0]; +} + +static xtensa_insnbuf +callx12_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x000f0000 }; + return &template[0]; +} + +static xtensa_insnbuf +callx4_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00070000 }; + return &template[0]; +} + +static xtensa_insnbuf +callx8_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x000b0000 }; + return &template[0]; +} + +static xtensa_insnbuf +dhi_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00260700 }; + return &template[0]; +} + +static xtensa_insnbuf +dhwb_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00240700 }; + return &template[0]; +} + +static xtensa_insnbuf +dhwbi_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00250700 }; + return &template[0]; +} + +static xtensa_insnbuf +dii_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00270700 }; + return &template[0]; +} + +static xtensa_insnbuf +diwb_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00280740 }; + return &template[0]; +} + +static xtensa_insnbuf +diwbi_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00280750 }; + return &template[0]; +} + +static xtensa_insnbuf +dpfr_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00200700 }; + return &template[0]; +} + +static xtensa_insnbuf +dpfro_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00220700 }; + return &template[0]; +} + +static xtensa_insnbuf +dpfw_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00210700 }; + return &template[0]; +} + +static xtensa_insnbuf +dpfwo_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00230700 }; + return &template[0]; +} + +static xtensa_insnbuf +dsync_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00030200 }; + return &template[0]; +} + +static xtensa_insnbuf +entry_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x006c0000 }; + return &template[0]; +} + +static xtensa_insnbuf +esync_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00020200 }; + return &template[0]; +} + +static xtensa_insnbuf +excw_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00080200 }; + return &template[0]; +} + +static xtensa_insnbuf +extui_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00000040 }; + return &template[0]; +} + +static xtensa_insnbuf +idtlb_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00000c05 }; + return &template[0]; +} + +static xtensa_insnbuf +idtlba_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00000805 }; + return &template[0]; +} + +static xtensa_insnbuf +ihi_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x002e0700 }; + return &template[0]; +} + +static xtensa_insnbuf +iii_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x002f0700 }; + return &template[0]; +} + +static xtensa_insnbuf +iitlb_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00000405 }; + return &template[0]; +} + +static xtensa_insnbuf +iitlba_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00000005 }; + return &template[0]; +} + +static xtensa_insnbuf +ipf_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x002c0700 }; + return &template[0]; +} + +static xtensa_insnbuf +isync_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00000200 }; + return &template[0]; +} + +static xtensa_insnbuf +j_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00600000 }; + return &template[0]; +} + +static xtensa_insnbuf +jx_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x000a0000 }; + return &template[0]; +} + +static xtensa_insnbuf +l16si_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00200900 }; + return &template[0]; +} + +static xtensa_insnbuf +l16ui_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00200100 }; + return &template[0]; +} + +static xtensa_insnbuf +l32e_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00000090 }; + return &template[0]; +} + +static xtensa_insnbuf +l32i_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00200200 }; + return &template[0]; +} + +static xtensa_insnbuf +l32i_n_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00800000 }; + return &template[0]; +} + +static xtensa_insnbuf +l32r_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00100000 }; + return &template[0]; +} + +static xtensa_insnbuf +l8ui_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00200000 }; + return &template[0]; +} + +static xtensa_insnbuf +ldct_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x0000081f }; + return &template[0]; +} + +static xtensa_insnbuf +lict_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x0000001f }; + return &template[0]; +} + +static xtensa_insnbuf +licw_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x0000021f }; + return &template[0]; +} + +static xtensa_insnbuf +loop_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x006d0800 }; + return &template[0]; +} + +static xtensa_insnbuf +loopgtz_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x006d0a00 }; + return &template[0]; +} + +static xtensa_insnbuf +loopnez_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x006d0900 }; + return &template[0]; +} + +static xtensa_insnbuf +memw_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x000c0200 }; + return &template[0]; +} + +static xtensa_insnbuf +mov_n_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00d00000 }; + return &template[0]; +} + +static xtensa_insnbuf +moveqz_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00000038 }; + return &template[0]; +} + +static xtensa_insnbuf +movgez_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x0000003b }; + return &template[0]; +} + +static xtensa_insnbuf +movi_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00200a00 }; + return &template[0]; +} + +static xtensa_insnbuf +movi_n_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00c00000 }; + return &template[0]; +} + +static xtensa_insnbuf +movltz_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x0000003a }; + return &template[0]; +} + +static xtensa_insnbuf +movnez_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00000039 }; + return &template[0]; +} + +static xtensa_insnbuf +movsp_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00000100 }; + return &template[0]; +} + +static xtensa_insnbuf +neg_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00000006 }; + return &template[0]; +} + +static xtensa_insnbuf +nop_n_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00d30f00 }; + return &template[0]; +} + +static xtensa_insnbuf +nsa_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00000e04 }; + return &template[0]; +} + +static xtensa_insnbuf +nsau_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00000f04 }; + return &template[0]; +} + +static xtensa_insnbuf +or_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00000002 }; + return &template[0]; +} + +static xtensa_insnbuf +pdtlb_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00000d05 }; + return &template[0]; +} + +static xtensa_insnbuf +pitlb_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00000505 }; + return &template[0]; +} + +static xtensa_insnbuf +rdtlb0_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00000b05 }; + return &template[0]; +} + +static xtensa_insnbuf +rdtlb1_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00000f05 }; + return &template[0]; +} + +static xtensa_insnbuf +ret_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00020000 }; + return &template[0]; +} + +static xtensa_insnbuf +ret_n_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00d00f00 }; + return &template[0]; +} + +static xtensa_insnbuf +retw_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00060000 }; + return &template[0]; +} + +static xtensa_insnbuf +retw_n_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00d10f00 }; + return &template[0]; +} + +static xtensa_insnbuf +rfde_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00002300 }; + return &template[0]; +} + +static xtensa_insnbuf +rfe_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00000300 }; + return &template[0]; +} + +static xtensa_insnbuf +rfi_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00010300 }; + return &template[0]; +} + +static xtensa_insnbuf +rfwo_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00004300 }; + return &template[0]; +} + +static xtensa_insnbuf +rfwu_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00005300 }; + return &template[0]; +} + +static xtensa_insnbuf +ritlb0_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00000305 }; + return &template[0]; +} + +static xtensa_insnbuf +ritlb1_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00000705 }; + return &template[0]; +} + +static xtensa_insnbuf +rotw_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00000804 }; + return &template[0]; +} + +static xtensa_insnbuf +rsil_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00000600 }; + return &template[0]; +} + +static xtensa_insnbuf +rsr_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00000030 }; + return &template[0]; +} + +static xtensa_insnbuf +rsync_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00010200 }; + return &template[0]; +} + +static xtensa_insnbuf +s16i_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00200500 }; + return &template[0]; +} + +static xtensa_insnbuf +s32e_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00000094 }; + return &template[0]; +} + +static xtensa_insnbuf +s32i_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00200600 }; + return &template[0]; +} + +static xtensa_insnbuf +s32i_n_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00900000 }; + return &template[0]; +} + +static xtensa_insnbuf +s8i_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00200400 }; + return &template[0]; +} + +static xtensa_insnbuf +sdct_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x0000091f }; + return &template[0]; +} + +static xtensa_insnbuf +sict_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x0000011f }; + return &template[0]; +} + +static xtensa_insnbuf +sicw_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x0000031f }; + return &template[0]; +} + +static xtensa_insnbuf +simcall_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00001500 }; + return &template[0]; +} + +static xtensa_insnbuf +sll_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x0000001a }; + return &template[0]; +} + +static xtensa_insnbuf +slli_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00000010 }; + return &template[0]; +} + +static xtensa_insnbuf +sra_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x0000001b }; + return &template[0]; +} + +static xtensa_insnbuf +srai_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00000012 }; + return &template[0]; +} + +static xtensa_insnbuf +src_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00000018 }; + return &template[0]; +} + +static xtensa_insnbuf +srl_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00000019 }; + return &template[0]; +} + +static xtensa_insnbuf +srli_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00000014 }; + return &template[0]; +} + +static xtensa_insnbuf +ssa8b_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00000304 }; + return &template[0]; +} + +static xtensa_insnbuf +ssa8l_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00000204 }; + return &template[0]; +} + +static xtensa_insnbuf +ssai_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00000404 }; + return &template[0]; +} + +static xtensa_insnbuf +ssl_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00000104 }; + return &template[0]; +} + +static xtensa_insnbuf +ssr_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00000004 }; + return &template[0]; +} + +static xtensa_insnbuf +sub_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x0000000c }; + return &template[0]; +} + +static xtensa_insnbuf +subx2_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x0000000d }; + return &template[0]; +} + +static xtensa_insnbuf +subx4_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x0000000e }; + return &template[0]; +} + +static xtensa_insnbuf +subx8_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x0000000f }; + return &template[0]; +} + +static xtensa_insnbuf +syscall_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00000500 }; + return &template[0]; +} + +static xtensa_insnbuf +waiti_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00000700 }; + return &template[0]; +} + +static xtensa_insnbuf +wdtlb_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00000e05 }; + return &template[0]; +} + +static xtensa_insnbuf +witlb_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00000605 }; + return &template[0]; +} + +static xtensa_insnbuf +wsr_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00000031 }; + return &template[0]; +} + +static xtensa_insnbuf +xor_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00000003 }; + return &template[0]; +} + +static xtensa_insnbuf +xsr_template (void) +{ + static xtensa_insnbuf_word template[] = { 0x00000016 }; + return &template[0]; +} + +static xtensa_opcode_internal abs_opcode = { + "abs", + 3, + abs_template, + &neg_iclass +}; + +static xtensa_opcode_internal add_opcode = { + "add", + 3, + add_template, + &addsub_iclass +}; + +static xtensa_opcode_internal add_n_opcode = { + "add.n", + 2, + add_n_template, + &add_n_iclass +}; + +static xtensa_opcode_internal addi_opcode = { + "addi", + 3, + addi_template, + &addi_iclass +}; + +static xtensa_opcode_internal addi_n_opcode = { + "addi.n", + 2, + addi_n_template, + &addi_n_iclass +}; + +static xtensa_opcode_internal addmi_opcode = { + "addmi", + 3, + addmi_template, + &addmi_iclass +}; + +static xtensa_opcode_internal addx2_opcode = { + "addx2", + 3, + addx2_template, + &addsub_iclass +}; + +static xtensa_opcode_internal addx4_opcode = { + "addx4", + 3, + addx4_template, + &addsub_iclass +}; + +static xtensa_opcode_internal addx8_opcode = { + "addx8", + 3, + addx8_template, + &addsub_iclass +}; + +static xtensa_opcode_internal and_opcode = { + "and", + 3, + and_template, + &bit_iclass +}; + +static xtensa_opcode_internal ball_opcode = { + "ball", + 3, + ball_template, + &bst8_iclass +}; + +static xtensa_opcode_internal bany_opcode = { + "bany", + 3, + bany_template, + &bst8_iclass +}; + +static xtensa_opcode_internal bbc_opcode = { + "bbc", + 3, + bbc_template, + &bst8_iclass +}; + +static xtensa_opcode_internal bbci_opcode = { + "bbci", + 3, + bbci_template, + &bsi8b_iclass +}; + +static xtensa_opcode_internal bbs_opcode = { + "bbs", + 3, + bbs_template, + &bst8_iclass +}; + +static xtensa_opcode_internal bbsi_opcode = { + "bbsi", + 3, + bbsi_template, + &bsi8b_iclass +}; + +static xtensa_opcode_internal beq_opcode = { + "beq", + 3, + beq_template, + &bst8_iclass +}; + +static xtensa_opcode_internal beqi_opcode = { + "beqi", + 3, + beqi_template, + &bsi8_iclass +}; + +static xtensa_opcode_internal beqz_opcode = { + "beqz", + 3, + beqz_template, + &bsz12_iclass +}; + +static xtensa_opcode_internal beqz_n_opcode = { + "beqz.n", + 2, + beqz_n_template, + &bz6_iclass +}; + +static xtensa_opcode_internal bge_opcode = { + "bge", + 3, + bge_template, + &bst8_iclass +}; + +static xtensa_opcode_internal bgei_opcode = { + "bgei", + 3, + bgei_template, + &bsi8_iclass +}; + +static xtensa_opcode_internal bgeu_opcode = { + "bgeu", + 3, + bgeu_template, + &bst8_iclass +}; + +static xtensa_opcode_internal bgeui_opcode = { + "bgeui", + 3, + bgeui_template, + &bsi8u_iclass +}; + +static xtensa_opcode_internal bgez_opcode = { + "bgez", + 3, + bgez_template, + &bsz12_iclass +}; + +static xtensa_opcode_internal blt_opcode = { + "blt", + 3, + blt_template, + &bst8_iclass +}; + +static xtensa_opcode_internal blti_opcode = { + "blti", + 3, + blti_template, + &bsi8_iclass +}; + +static xtensa_opcode_internal bltu_opcode = { + "bltu", + 3, + bltu_template, + &bst8_iclass +}; + +static xtensa_opcode_internal bltui_opcode = { + "bltui", + 3, + bltui_template, + &bsi8u_iclass +}; + +static xtensa_opcode_internal bltz_opcode = { + "bltz", + 3, + bltz_template, + &bsz12_iclass +}; + +static xtensa_opcode_internal bnall_opcode = { + "bnall", + 3, + bnall_template, + &bst8_iclass +}; + +static xtensa_opcode_internal bne_opcode = { + "bne", + 3, + bne_template, + &bst8_iclass +}; + +static xtensa_opcode_internal bnei_opcode = { + "bnei", + 3, + bnei_template, + &bsi8_iclass +}; + +static xtensa_opcode_internal bnez_opcode = { + "bnez", + 3, + bnez_template, + &bsz12_iclass +}; + +static xtensa_opcode_internal bnez_n_opcode = { + "bnez.n", + 2, + bnez_n_template, + &bz6_iclass +}; + +static xtensa_opcode_internal bnone_opcode = { + "bnone", + 3, + bnone_template, + &bst8_iclass +}; + +static xtensa_opcode_internal break_opcode = { + "break", + 3, + break_template, + &break_iclass +}; + +static xtensa_opcode_internal break_n_opcode = { + "break.n", + 2, + break_n_template, + &break_n_iclass +}; + +static xtensa_opcode_internal call0_opcode = { + "call0", + 3, + call0_template, + &call_iclass +}; + +static xtensa_opcode_internal call12_opcode = { + "call12", + 3, + call12_template, + &call12_iclass +}; + +static xtensa_opcode_internal call4_opcode = { + "call4", + 3, + call4_template, + &call4_iclass +}; + +static xtensa_opcode_internal call8_opcode = { + "call8", + 3, + call8_template, + &call8_iclass +}; + +static xtensa_opcode_internal callx0_opcode = { + "callx0", + 3, + callx0_template, + &callx_iclass +}; + +static xtensa_opcode_internal callx12_opcode = { + "callx12", + 3, + callx12_template, + &callx12_iclass +}; + +static xtensa_opcode_internal callx4_opcode = { + "callx4", + 3, + callx4_template, + &callx4_iclass +}; + +static xtensa_opcode_internal callx8_opcode = { + "callx8", + 3, + callx8_template, + &callx8_iclass +}; + +static xtensa_opcode_internal dhi_opcode = { + "dhi", + 3, + dhi_template, + &dcache_iclass +}; + +static xtensa_opcode_internal dhwb_opcode = { + "dhwb", + 3, + dhwb_template, + &dcache_iclass +}; + +static xtensa_opcode_internal dhwbi_opcode = { + "dhwbi", + 3, + dhwbi_template, + &dcache_iclass +}; + +static xtensa_opcode_internal dii_opcode = { + "dii", + 3, + dii_template, + &dcache_iclass +}; + +static xtensa_opcode_internal diwb_opcode = { + "diwb", + 3, + diwb_template, + &dce_iclass +}; + +static xtensa_opcode_internal diwbi_opcode = { + "diwbi", + 3, + diwbi_template, + &dce_iclass +}; + +static xtensa_opcode_internal dpfr_opcode = { + "dpfr", + 3, + dpfr_template, + &dpf_iclass +}; + +static xtensa_opcode_internal dpfro_opcode = { + "dpfro", + 3, + dpfro_template, + &dpf_iclass +}; + +static xtensa_opcode_internal dpfw_opcode = { + "dpfw", + 3, + dpfw_template, + &dpf_iclass +}; + +static xtensa_opcode_internal dpfwo_opcode = { + "dpfwo", + 3, + dpfwo_template, + &dpf_iclass +}; + +static xtensa_opcode_internal dsync_opcode = { + "dsync", + 3, + dsync_template, + &sync_iclass +}; + +static xtensa_opcode_internal entry_opcode = { + "entry", + 3, + entry_template, + &entry_iclass +}; + +static xtensa_opcode_internal esync_opcode = { + "esync", + 3, + esync_template, + &sync_iclass +}; + +static xtensa_opcode_internal excw_opcode = { + "excw", + 3, + excw_template, + &excw_iclass +}; + +static xtensa_opcode_internal extui_opcode = { + "extui", + 3, + extui_template, + &exti_iclass +}; + +static xtensa_opcode_internal idtlb_opcode = { + "idtlb", + 3, + idtlb_template, + &itlb_iclass +}; + +static xtensa_opcode_internal idtlba_opcode = { + "idtlba", + 3, + idtlba_template, + &itlba_iclass +}; + +static xtensa_opcode_internal ihi_opcode = { + "ihi", + 3, + ihi_template, + &icache_iclass +}; + +static xtensa_opcode_internal iii_opcode = { + "iii", + 3, + iii_template, + &icache_iclass +}; + +static xtensa_opcode_internal iitlb_opcode = { + "iitlb", + 3, + iitlb_template, + &itlb_iclass +}; + +static xtensa_opcode_internal iitlba_opcode = { + "iitlba", + 3, + iitlba_template, + &itlba_iclass +}; + +static xtensa_opcode_internal ipf_opcode = { + "ipf", + 3, + ipf_template, + &icache_iclass +}; + +static xtensa_opcode_internal isync_opcode = { + "isync", + 3, + isync_template, + &sync_iclass +}; + +static xtensa_opcode_internal j_opcode = { + "j", + 3, + j_template, + &jump_iclass +}; + +static xtensa_opcode_internal jx_opcode = { + "jx", + 3, + jx_template, + &jumpx_iclass +}; + +static xtensa_opcode_internal l16si_opcode = { + "l16si", + 3, + l16si_template, + &l16i_iclass +}; + +static xtensa_opcode_internal l16ui_opcode = { + "l16ui", + 3, + l16ui_template, + &l16i_iclass +}; + +static xtensa_opcode_internal l32e_opcode = { + "l32e", + 3, + l32e_template, + &l32e_iclass +}; + +static xtensa_opcode_internal l32i_opcode = { + "l32i", + 3, + l32i_template, + &l32i_iclass +}; + +static xtensa_opcode_internal l32i_n_opcode = { + "l32i.n", + 2, + l32i_n_template, + &loadi4_iclass +}; + +static xtensa_opcode_internal l32r_opcode = { + "l32r", + 3, + l32r_template, + &l32r_iclass +}; + +static xtensa_opcode_internal l8ui_opcode = { + "l8ui", + 3, + l8ui_template, + &l8i_iclass +}; + +static xtensa_opcode_internal ldct_opcode = { + "ldct", + 3, + ldct_template, + &actl_iclass +}; + +static xtensa_opcode_internal lict_opcode = { + "lict", + 3, + lict_template, + &actl_iclass +}; + +static xtensa_opcode_internal licw_opcode = { + "licw", + 3, + licw_template, + &actl_iclass +}; + +static xtensa_opcode_internal loop_opcode = { + "loop", + 3, + loop_template, + &loop_iclass +}; + +static xtensa_opcode_internal loopgtz_opcode = { + "loopgtz", + 3, + loopgtz_template, + &loop_iclass +}; + +static xtensa_opcode_internal loopnez_opcode = { + "loopnez", + 3, + loopnez_template, + &loop_iclass +}; + +static xtensa_opcode_internal memw_opcode = { + "memw", + 3, + memw_template, + &sync_iclass +}; + +static xtensa_opcode_internal mov_n_opcode = { + "mov.n", + 2, + mov_n_template, + &mov_n_iclass +}; + +static xtensa_opcode_internal moveqz_opcode = { + "moveqz", + 3, + moveqz_template, + &movz_iclass +}; + +static xtensa_opcode_internal movgez_opcode = { + "movgez", + 3, + movgez_template, + &movz_iclass +}; + +static xtensa_opcode_internal movi_opcode = { + "movi", + 3, + movi_template, + &movi_iclass +}; + +static xtensa_opcode_internal movi_n_opcode = { + "movi.n", + 2, + movi_n_template, + &movi_n_iclass +}; + +static xtensa_opcode_internal movltz_opcode = { + "movltz", + 3, + movltz_template, + &movz_iclass +}; + +static xtensa_opcode_internal movnez_opcode = { + "movnez", + 3, + movnez_template, + &movz_iclass +}; + +static xtensa_opcode_internal movsp_opcode = { + "movsp", + 3, + movsp_template, + &movsp_iclass +}; + +static xtensa_opcode_internal neg_opcode = { + "neg", + 3, + neg_template, + &neg_iclass +}; + +static xtensa_opcode_internal nop_n_opcode = { + "nop.n", + 2, + nop_n_template, + &nopn_iclass +}; + +static xtensa_opcode_internal nsa_opcode = { + "nsa", + 3, + nsa_template, + &nsa_iclass +}; + +static xtensa_opcode_internal nsau_opcode = { + "nsau", + 3, + nsau_template, + &nsa_iclass +}; + +static xtensa_opcode_internal or_opcode = { + "or", + 3, + or_template, + &bit_iclass +}; + +static xtensa_opcode_internal pdtlb_opcode = { + "pdtlb", + 3, + pdtlb_template, + &rtlb_iclass +}; + +static xtensa_opcode_internal pitlb_opcode = { + "pitlb", + 3, + pitlb_template, + &rtlb_iclass +}; + +static xtensa_opcode_internal rdtlb0_opcode = { + "rdtlb0", + 3, + rdtlb0_template, + &rtlb_iclass +}; + +static xtensa_opcode_internal rdtlb1_opcode = { + "rdtlb1", + 3, + rdtlb1_template, + &rtlb_iclass +}; + +static xtensa_opcode_internal ret_opcode = { + "ret", + 3, + ret_template, + &return_iclass +}; + +static xtensa_opcode_internal ret_n_opcode = { + "ret.n", + 2, + ret_n_template, + &retn_iclass +}; + +static xtensa_opcode_internal retw_opcode = { + "retw", + 3, + retw_template, + &return_iclass +}; + +static xtensa_opcode_internal retw_n_opcode = { + "retw.n", + 2, + retw_n_template, + &retn_iclass +}; + +static xtensa_opcode_internal rfde_opcode = { + "rfde", + 3, + rfde_template, + &rfe_iclass +}; + +static xtensa_opcode_internal rfe_opcode = { + "rfe", + 3, + rfe_template, + &rfe_iclass +}; + +static xtensa_opcode_internal rfi_opcode = { + "rfi", + 3, + rfi_template, + &rfi_iclass +}; + +static xtensa_opcode_internal rfwo_opcode = { + "rfwo", + 3, + rfwo_template, + &rfe_iclass +}; + +static xtensa_opcode_internal rfwu_opcode = { + "rfwu", + 3, + rfwu_template, + &rfe_iclass +}; + +static xtensa_opcode_internal ritlb0_opcode = { + "ritlb0", + 3, + ritlb0_template, + &rtlb_iclass +}; + +static xtensa_opcode_internal ritlb1_opcode = { + "ritlb1", + 3, + ritlb1_template, + &rtlb_iclass +}; + +static xtensa_opcode_internal rotw_opcode = { + "rotw", + 3, + rotw_template, + &rotw_iclass +}; + +static xtensa_opcode_internal rsil_opcode = { + "rsil", + 3, + rsil_template, + &rsil_iclass +}; + +static xtensa_opcode_internal rsr_opcode = { + "rsr", + 3, + rsr_template, + &rsr_iclass +}; + +static xtensa_opcode_internal rsync_opcode = { + "rsync", + 3, + rsync_template, + &sync_iclass +}; + +static xtensa_opcode_internal s16i_opcode = { + "s16i", + 3, + s16i_template, + &s16i_iclass +}; + +static xtensa_opcode_internal s32e_opcode = { + "s32e", + 3, + s32e_template, + &s32e_iclass +}; + +static xtensa_opcode_internal s32i_opcode = { + "s32i", + 3, + s32i_template, + &s32i_iclass +}; + +static xtensa_opcode_internal s32i_n_opcode = { + "s32i.n", + 2, + s32i_n_template, + &storei4_iclass +}; + +static xtensa_opcode_internal s8i_opcode = { + "s8i", + 3, + s8i_template, + &s8i_iclass +}; + +static xtensa_opcode_internal sdct_opcode = { + "sdct", + 3, + sdct_template, + &acts_iclass +}; + +static xtensa_opcode_internal sict_opcode = { + "sict", + 3, + sict_template, + &acts_iclass +}; + +static xtensa_opcode_internal sicw_opcode = { + "sicw", + 3, + sicw_template, + &acts_iclass +}; + +static xtensa_opcode_internal simcall_opcode = { + "simcall", + 3, + simcall_template, + &syscall_iclass +}; + +static xtensa_opcode_internal sll_opcode = { + "sll", + 3, + sll_template, + &shifts_iclass +}; + +static xtensa_opcode_internal slli_opcode = { + "slli", + 3, + slli_template, + &slli_iclass +}; + +static xtensa_opcode_internal sra_opcode = { + "sra", + 3, + sra_template, + &shiftt_iclass +}; + +static xtensa_opcode_internal srai_opcode = { + "srai", + 3, + srai_template, + &srai_iclass +}; + +static xtensa_opcode_internal src_opcode = { + "src", + 3, + src_template, + &shiftst_iclass +}; + +static xtensa_opcode_internal srl_opcode = { + "srl", + 3, + srl_template, + &shiftt_iclass +}; + +static xtensa_opcode_internal srli_opcode = { + "srli", + 3, + srli_template, + &srli_iclass +}; + +static xtensa_opcode_internal ssa8b_opcode = { + "ssa8b", + 3, + ssa8b_template, + &sar_iclass +}; + +static xtensa_opcode_internal ssa8l_opcode = { + "ssa8l", + 3, + ssa8l_template, + &sar_iclass +}; + +static xtensa_opcode_internal ssai_opcode = { + "ssai", + 3, + ssai_template, + &sari_iclass +}; + +static xtensa_opcode_internal ssl_opcode = { + "ssl", + 3, + ssl_template, + &sar_iclass +}; + +static xtensa_opcode_internal ssr_opcode = { + "ssr", + 3, + ssr_template, + &sar_iclass +}; + +static xtensa_opcode_internal sub_opcode = { + "sub", + 3, + sub_template, + &addsub_iclass +}; + +static xtensa_opcode_internal subx2_opcode = { + "subx2", + 3, + subx2_template, + &addsub_iclass +}; + +static xtensa_opcode_internal subx4_opcode = { + "subx4", + 3, + subx4_template, + &addsub_iclass +}; + +static xtensa_opcode_internal subx8_opcode = { + "subx8", + 3, + subx8_template, + &addsub_iclass +}; + +static xtensa_opcode_internal syscall_opcode = { + "syscall", + 3, + syscall_template, + &syscall_iclass +}; + +static xtensa_opcode_internal waiti_opcode = { + "waiti", + 3, + waiti_template, + &wait_iclass +}; + +static xtensa_opcode_internal wdtlb_opcode = { + "wdtlb", + 3, + wdtlb_template, + &wtlb_iclass +}; + +static xtensa_opcode_internal witlb_opcode = { + "witlb", + 3, + witlb_template, + &wtlb_iclass +}; + +static xtensa_opcode_internal wsr_opcode = { + "wsr", + 3, + wsr_template, + &wsr_iclass +}; + +static xtensa_opcode_internal xor_opcode = { + "xor", + 3, + xor_template, + &bit_iclass +}; + +static xtensa_opcode_internal xsr_opcode = { + "xsr", + 3, + xsr_template, + &xsr_iclass +}; + +static xtensa_opcode_internal * opcodes[149] = { + &abs_opcode, + &add_opcode, + &add_n_opcode, + &addi_opcode, + &addi_n_opcode, + &addmi_opcode, + &addx2_opcode, + &addx4_opcode, + &addx8_opcode, + &and_opcode, + &ball_opcode, + &bany_opcode, + &bbc_opcode, + &bbci_opcode, + &bbs_opcode, + &bbsi_opcode, + &beq_opcode, + &beqi_opcode, + &beqz_opcode, + &beqz_n_opcode, + &bge_opcode, + &bgei_opcode, + &bgeu_opcode, + &bgeui_opcode, + &bgez_opcode, + &blt_opcode, + &blti_opcode, + &bltu_opcode, + &bltui_opcode, + &bltz_opcode, + &bnall_opcode, + &bne_opcode, + &bnei_opcode, + &bnez_opcode, + &bnez_n_opcode, + &bnone_opcode, + &break_opcode, + &break_n_opcode, + &call0_opcode, + &call12_opcode, + &call4_opcode, + &call8_opcode, + &callx0_opcode, + &callx12_opcode, + &callx4_opcode, + &callx8_opcode, + &dhi_opcode, + &dhwb_opcode, + &dhwbi_opcode, + &dii_opcode, + &diwb_opcode, + &diwbi_opcode, + &dpfr_opcode, + &dpfro_opcode, + &dpfw_opcode, + &dpfwo_opcode, + &dsync_opcode, + &entry_opcode, + &esync_opcode, + &excw_opcode, + &extui_opcode, + &idtlb_opcode, + &idtlba_opcode, + &ihi_opcode, + &iii_opcode, + &iitlb_opcode, + &iitlba_opcode, + &ipf_opcode, + &isync_opcode, + &j_opcode, + &jx_opcode, + &l16si_opcode, + &l16ui_opcode, + &l32e_opcode, + &l32i_opcode, + &l32i_n_opcode, + &l32r_opcode, + &l8ui_opcode, + &ldct_opcode, + &lict_opcode, + &licw_opcode, + &loop_opcode, + &loopgtz_opcode, + &loopnez_opcode, + &memw_opcode, + &mov_n_opcode, + &moveqz_opcode, + &movgez_opcode, + &movi_opcode, + &movi_n_opcode, + &movltz_opcode, + &movnez_opcode, + &movsp_opcode, + &neg_opcode, + &nop_n_opcode, + &nsa_opcode, + &nsau_opcode, + &or_opcode, + &pdtlb_opcode, + &pitlb_opcode, + &rdtlb0_opcode, + &rdtlb1_opcode, + &ret_opcode, + &ret_n_opcode, + &retw_opcode, + &retw_n_opcode, + &rfde_opcode, + &rfe_opcode, + &rfi_opcode, + &rfwo_opcode, + &rfwu_opcode, + &ritlb0_opcode, + &ritlb1_opcode, + &rotw_opcode, + &rsil_opcode, + &rsr_opcode, + &rsync_opcode, + &s16i_opcode, + &s32e_opcode, + &s32i_opcode, + &s32i_n_opcode, + &s8i_opcode, + &sdct_opcode, + &sict_opcode, + &sicw_opcode, + &simcall_opcode, + &sll_opcode, + &slli_opcode, + &sra_opcode, + &srai_opcode, + &src_opcode, + &srl_opcode, + &srli_opcode, + &ssa8b_opcode, + &ssa8l_opcode, + &ssai_opcode, + &ssl_opcode, + &ssr_opcode, + &sub_opcode, + &subx2_opcode, + &subx4_opcode, + &subx8_opcode, + &syscall_opcode, + &waiti_opcode, + &wdtlb_opcode, + &witlb_opcode, + &wsr_opcode, + &xor_opcode, + &xsr_opcode +}; + +xtensa_opcode_internal ** +get_opcodes (void) +{ + return &opcodes[0]; +} + +int +get_num_opcodes (void) +{ + return 149; +} + +#define xtensa_abs_op 0 +#define xtensa_add_op 1 +#define xtensa_add_n_op 2 +#define xtensa_addi_op 3 +#define xtensa_addi_n_op 4 +#define xtensa_addmi_op 5 +#define xtensa_addx2_op 6 +#define xtensa_addx4_op 7 +#define xtensa_addx8_op 8 +#define xtensa_and_op 9 +#define xtensa_ball_op 10 +#define xtensa_bany_op 11 +#define xtensa_bbc_op 12 +#define xtensa_bbci_op 13 +#define xtensa_bbs_op 14 +#define xtensa_bbsi_op 15 +#define xtensa_beq_op 16 +#define xtensa_beqi_op 17 +#define xtensa_beqz_op 18 +#define xtensa_beqz_n_op 19 +#define xtensa_bge_op 20 +#define xtensa_bgei_op 21 +#define xtensa_bgeu_op 22 +#define xtensa_bgeui_op 23 +#define xtensa_bgez_op 24 +#define xtensa_blt_op 25 +#define xtensa_blti_op 26 +#define xtensa_bltu_op 27 +#define xtensa_bltui_op 28 +#define xtensa_bltz_op 29 +#define xtensa_bnall_op 30 +#define xtensa_bne_op 31 +#define xtensa_bnei_op 32 +#define xtensa_bnez_op 33 +#define xtensa_bnez_n_op 34 +#define xtensa_bnone_op 35 +#define xtensa_break_op 36 +#define xtensa_break_n_op 37 +#define xtensa_call0_op 38 +#define xtensa_call12_op 39 +#define xtensa_call4_op 40 +#define xtensa_call8_op 41 +#define xtensa_callx0_op 42 +#define xtensa_callx12_op 43 +#define xtensa_callx4_op 44 +#define xtensa_callx8_op 45 +#define xtensa_dhi_op 46 +#define xtensa_dhwb_op 47 +#define xtensa_dhwbi_op 48 +#define xtensa_dii_op 49 +#define xtensa_diwb_op 50 +#define xtensa_diwbi_op 51 +#define xtensa_dpfr_op 52 +#define xtensa_dpfro_op 53 +#define xtensa_dpfw_op 54 +#define xtensa_dpfwo_op 55 +#define xtensa_dsync_op 56 +#define xtensa_entry_op 57 +#define xtensa_esync_op 58 +#define xtensa_excw_op 59 +#define xtensa_extui_op 60 +#define xtensa_idtlb_op 61 +#define xtensa_idtlba_op 62 +#define xtensa_ihi_op 63 +#define xtensa_iii_op 64 +#define xtensa_iitlb_op 65 +#define xtensa_iitlba_op 66 +#define xtensa_ipf_op 67 +#define xtensa_isync_op 68 +#define xtensa_j_op 69 +#define xtensa_jx_op 70 +#define xtensa_l16si_op 71 +#define xtensa_l16ui_op 72 +#define xtensa_l32e_op 73 +#define xtensa_l32i_op 74 +#define xtensa_l32i_n_op 75 +#define xtensa_l32r_op 76 +#define xtensa_l8ui_op 77 +#define xtensa_ldct_op 78 +#define xtensa_lict_op 79 +#define xtensa_licw_op 80 +#define xtensa_loop_op 81 +#define xtensa_loopgtz_op 82 +#define xtensa_loopnez_op 83 +#define xtensa_memw_op 84 +#define xtensa_mov_n_op 85 +#define xtensa_moveqz_op 86 +#define xtensa_movgez_op 87 +#define xtensa_movi_op 88 +#define xtensa_movi_n_op 89 +#define xtensa_movltz_op 90 +#define xtensa_movnez_op 91 +#define xtensa_movsp_op 92 +#define xtensa_neg_op 93 +#define xtensa_nop_n_op 94 +#define xtensa_nsa_op 95 +#define xtensa_nsau_op 96 +#define xtensa_or_op 97 +#define xtensa_pdtlb_op 98 +#define xtensa_pitlb_op 99 +#define xtensa_rdtlb0_op 100 +#define xtensa_rdtlb1_op 101 +#define xtensa_ret_op 102 +#define xtensa_ret_n_op 103 +#define xtensa_retw_op 104 +#define xtensa_retw_n_op 105 +#define xtensa_rfde_op 106 +#define xtensa_rfe_op 107 +#define xtensa_rfi_op 108 +#define xtensa_rfwo_op 109 +#define xtensa_rfwu_op 110 +#define xtensa_ritlb0_op 111 +#define xtensa_ritlb1_op 112 +#define xtensa_rotw_op 113 +#define xtensa_rsil_op 114 +#define xtensa_rsr_op 115 +#define xtensa_rsync_op 116 +#define xtensa_s16i_op 117 +#define xtensa_s32e_op 118 +#define xtensa_s32i_op 119 +#define xtensa_s32i_n_op 120 +#define xtensa_s8i_op 121 +#define xtensa_sdct_op 122 +#define xtensa_sict_op 123 +#define xtensa_sicw_op 124 +#define xtensa_simcall_op 125 +#define xtensa_sll_op 126 +#define xtensa_slli_op 127 +#define xtensa_sra_op 128 +#define xtensa_srai_op 129 +#define xtensa_src_op 130 +#define xtensa_srl_op 131 +#define xtensa_srli_op 132 +#define xtensa_ssa8b_op 133 +#define xtensa_ssa8l_op 134 +#define xtensa_ssai_op 135 +#define xtensa_ssl_op 136 +#define xtensa_ssr_op 137 +#define xtensa_sub_op 138 +#define xtensa_subx2_op 139 +#define xtensa_subx4_op 140 +#define xtensa_subx8_op 141 +#define xtensa_syscall_op 142 +#define xtensa_waiti_op 143 +#define xtensa_wdtlb_op 144 +#define xtensa_witlb_op 145 +#define xtensa_wsr_op 146 +#define xtensa_xor_op 147 +#define xtensa_xsr_op 148 + +int +decode_insn (const xtensa_insnbuf insn) +{ + switch (get_op0_field (insn)) { + case 0: /* QRST: op0=0000 */ + switch (get_op1_field (insn)) { + case 3: /* RST3: op1=0011 */ + switch (get_op2_field (insn)) { + case 8: /* MOVEQZ: op2=1000 */ + return xtensa_moveqz_op; + case 9: /* MOVNEZ: op2=1001 */ + return xtensa_movnez_op; + case 10: /* MOVLTZ: op2=1010 */ + return xtensa_movltz_op; + case 11: /* MOVGEZ: op2=1011 */ + return xtensa_movgez_op; + case 0: /* RSR: op2=0000 */ + return xtensa_rsr_op; + case 1: /* WSR: op2=0001 */ + return xtensa_wsr_op; + } + break; + case 9: /* LSI4: op1=1001 */ + switch (get_op2_field (insn)) { + case 4: /* S32E: op2=0100 */ + return xtensa_s32e_op; + case 0: /* L32E: op2=0000 */ + return xtensa_l32e_op; + } + break; + case 4: /* EXTUI: op1=010x */ + case 5: /* EXTUI: op1=010x */ + return xtensa_extui_op; + case 0: /* RST0: op1=0000 */ + switch (get_op2_field (insn)) { + case 15: /* SUBX8: op2=1111 */ + return xtensa_subx8_op; + case 0: /* ST0: op2=0000 */ + switch (get_r_field (insn)) { + case 0: /* SNM0: r=0000 */ + switch (get_m_field (insn)) { + case 2: /* JR: m=10 */ + switch (get_n_field (insn)) { + case 0: /* RET: n=00 */ + return xtensa_ret_op; + case 1: /* RETW: n=01 */ + return xtensa_retw_op; + case 2: /* JX: n=10 */ + return xtensa_jx_op; + } + break; + case 3: /* CALLX: m=11 */ + switch (get_n_field (insn)) { + case 0: /* CALLX0: n=00 */ + return xtensa_callx0_op; + case 1: /* CALLX4: n=01 */ + return xtensa_callx4_op; + case 2: /* CALLX8: n=10 */ + return xtensa_callx8_op; + case 3: /* CALLX12: n=11 */ + return xtensa_callx12_op; + } + break; + } + break; + case 1: /* MOVSP: r=0001 */ + return xtensa_movsp_op; + case 2: /* SYNC: r=0010 */ + switch (get_s_field (insn)) { + case 0: /* SYNCT: s=0000 */ + switch (get_t_field (insn)) { + case 2: /* ESYNC: t=0010 */ + return xtensa_esync_op; + case 3: /* DSYNC: t=0011 */ + return xtensa_dsync_op; + case 8: /* EXCW: t=1000 */ + return xtensa_excw_op; + case 12: /* MEMW: t=1100 */ + return xtensa_memw_op; + case 0: /* ISYNC: t=0000 */ + return xtensa_isync_op; + case 1: /* RSYNC: t=0001 */ + return xtensa_rsync_op; + } + break; + } + break; + case 4: /* BREAK: r=0100 */ + return xtensa_break_op; + case 3: /* RFEI: r=0011 */ + switch (get_t_field (insn)) { + case 0: /* RFET: t=0000 */ + switch (get_s_field (insn)) { + case 2: /* RFDE: s=0010 */ + return xtensa_rfde_op; + case 4: /* RFWO: s=0100 */ + return xtensa_rfwo_op; + case 5: /* RFWU: s=0101 */ + return xtensa_rfwu_op; + case 0: /* RFE: s=0000 */ + return xtensa_rfe_op; + } + break; + case 1: /* RFI: t=0001 */ + return xtensa_rfi_op; + } + break; + case 5: /* SCALL: r=0101 */ + switch (get_s_field (insn)) { + case 0: /* SYSCALL: s=0000 */ + return xtensa_syscall_op; + case 1: /* SIMCALL: s=0001 */ + return xtensa_simcall_op; + } + break; + case 6: /* RSIL: r=0110 */ + return xtensa_rsil_op; + case 7: /* WAITI: r=0111 */ + return xtensa_waiti_op; + } + break; + case 1: /* AND: op2=0001 */ + return xtensa_and_op; + case 2: /* OR: op2=0010 */ + return xtensa_or_op; + case 3: /* XOR: op2=0011 */ + return xtensa_xor_op; + case 4: /* ST1: op2=0100 */ + switch (get_r_field (insn)) { + case 15: /* NSAU: r=1111 */ + return xtensa_nsau_op; + case 0: /* SSR: r=0000 */ + return xtensa_ssr_op; + case 1: /* SSL: r=0001 */ + return xtensa_ssl_op; + case 2: /* SSA8L: r=0010 */ + return xtensa_ssa8l_op; + case 3: /* SSA8B: r=0011 */ + return xtensa_ssa8b_op; + case 4: /* SSAI: r=0100 */ + return xtensa_ssai_op; + case 8: /* ROTW: r=1000 */ + return xtensa_rotw_op; + case 14: /* NSA: r=1110 */ + return xtensa_nsa_op; + } + break; + case 8: /* ADD: op2=1000 */ + return xtensa_add_op; + case 5: /* ST4: op2=0101 */ + switch (get_r_field (insn)) { + case 15: /* RDTLB1: r=1111 */ + return xtensa_rdtlb1_op; + case 0: /* IITLBA: r=0000 */ + return xtensa_iitlba_op; + case 3: /* RITLB0: r=0011 */ + return xtensa_ritlb0_op; + case 4: /* IITLB: r=0100 */ + return xtensa_iitlb_op; + case 8: /* IDTLBA: r=1000 */ + return xtensa_idtlba_op; + case 5: /* PITLB: r=0101 */ + return xtensa_pitlb_op; + case 6: /* WITLB: r=0110 */ + return xtensa_witlb_op; + case 7: /* RITLB1: r=0111 */ + return xtensa_ritlb1_op; + case 11: /* RDTLB0: r=1011 */ + return xtensa_rdtlb0_op; + case 12: /* IDTLB: r=1100 */ + return xtensa_idtlb_op; + case 13: /* PDTLB: r=1101 */ + return xtensa_pdtlb_op; + case 14: /* WDTLB: r=1110 */ + return xtensa_wdtlb_op; + } + break; + case 6: /* RT0: op2=0110 */ + switch (get_s_field (insn)) { + case 0: /* NEG: s=0000 */ + return xtensa_neg_op; + case 1: /* ABS: s=0001 */ + return xtensa_abs_op; + } + break; + case 9: /* ADDX2: op2=1001 */ + return xtensa_addx2_op; + case 10: /* ADDX4: op2=1010 */ + return xtensa_addx4_op; + case 11: /* ADDX8: op2=1011 */ + return xtensa_addx8_op; + case 12: /* SUB: op2=1100 */ + return xtensa_sub_op; + case 13: /* SUBX2: op2=1101 */ + return xtensa_subx2_op; + case 14: /* SUBX4: op2=1110 */ + return xtensa_subx4_op; + } + break; + case 1: /* RST1: op1=0001 */ + switch (get_op2_field (insn)) { + case 15: /* IMP: op2=1111 */ + switch (get_r_field (insn)) { + case 0: /* LICT: r=0000 */ + return xtensa_lict_op; + case 1: /* SICT: r=0001 */ + return xtensa_sict_op; + case 2: /* LICW: r=0010 */ + return xtensa_licw_op; + case 3: /* SICW: r=0011 */ + return xtensa_sicw_op; + case 8: /* LDCT: r=1000 */ + return xtensa_ldct_op; + case 9: /* SDCT: r=1001 */ + return xtensa_sdct_op; + } + break; + case 0: /* SLLI: op2=000x */ + case 1: /* SLLI: op2=000x */ + return xtensa_slli_op; + case 2: /* SRAI: op2=001x */ + case 3: /* SRAI: op2=001x */ + return xtensa_srai_op; + case 4: /* SRLI: op2=0100 */ + return xtensa_srli_op; + case 8: /* SRC: op2=1000 */ + return xtensa_src_op; + case 9: /* SRL: op2=1001 */ + return xtensa_srl_op; + case 6: /* XSR: op2=0110 */ + return xtensa_xsr_op; + case 10: /* SLL: op2=1010 */ + return xtensa_sll_op; + case 11: /* SRA: op2=1011 */ + return xtensa_sra_op; + } + break; + } + break; + case 1: /* L32R: op0=0001 */ + return xtensa_l32r_op; + case 2: /* LSAI: op0=0010 */ + switch (get_r_field (insn)) { + case 0: /* L8UI: r=0000 */ + return xtensa_l8ui_op; + case 1: /* L16UI: r=0001 */ + return xtensa_l16ui_op; + case 2: /* L32I: r=0010 */ + return xtensa_l32i_op; + case 4: /* S8I: r=0100 */ + return xtensa_s8i_op; + case 5: /* S16I: r=0101 */ + return xtensa_s16i_op; + case 9: /* L16SI: r=1001 */ + return xtensa_l16si_op; + case 6: /* S32I: r=0110 */ + return xtensa_s32i_op; + case 7: /* CACHE: r=0111 */ + switch (get_t_field (insn)) { + case 15: /* III: t=1111 */ + return xtensa_iii_op; + case 0: /* DPFR: t=0000 */ + return xtensa_dpfr_op; + case 1: /* DPFW: t=0001 */ + return xtensa_dpfw_op; + case 2: /* DPFRO: t=0010 */ + return xtensa_dpfro_op; + case 4: /* DHWB: t=0100 */ + return xtensa_dhwb_op; + case 3: /* DPFWO: t=0011 */ + return xtensa_dpfwo_op; + case 8: /* DCE: t=1000 */ + switch (get_op1_field (insn)) { + case 4: /* DIWB: op1=0100 */ + return xtensa_diwb_op; + case 5: /* DIWBI: op1=0101 */ + return xtensa_diwbi_op; + } + break; + case 5: /* DHWBI: t=0101 */ + return xtensa_dhwbi_op; + case 6: /* DHI: t=0110 */ + return xtensa_dhi_op; + case 7: /* DII: t=0111 */ + return xtensa_dii_op; + case 12: /* IPF: t=1100 */ + return xtensa_ipf_op; + case 14: /* IHI: t=1110 */ + return xtensa_ihi_op; + } + break; + case 10: /* MOVI: r=1010 */ + return xtensa_movi_op; + case 12: /* ADDI: r=1100 */ + return xtensa_addi_op; + case 13: /* ADDMI: r=1101 */ + return xtensa_addmi_op; + } + break; + case 8: /* L32I.N: op0=1000 */ + return xtensa_l32i_n_op; + case 5: /* CALL: op0=0101 */ + switch (get_n_field (insn)) { + case 0: /* CALL0: n=00 */ + return xtensa_call0_op; + case 1: /* CALL4: n=01 */ + return xtensa_call4_op; + case 2: /* CALL8: n=10 */ + return xtensa_call8_op; + case 3: /* CALL12: n=11 */ + return xtensa_call12_op; + } + break; + case 6: /* SI: op0=0110 */ + switch (get_n_field (insn)) { + case 0: /* J: n=00 */ + return xtensa_j_op; + case 1: /* BZ: n=01 */ + switch (get_m_field (insn)) { + case 0: /* BEQZ: m=00 */ + return xtensa_beqz_op; + case 1: /* BNEZ: m=01 */ + return xtensa_bnez_op; + case 2: /* BLTZ: m=10 */ + return xtensa_bltz_op; + case 3: /* BGEZ: m=11 */ + return xtensa_bgez_op; + } + break; + case 2: /* BI0: n=10 */ + switch (get_m_field (insn)) { + case 0: /* BEQI: m=00 */ + return xtensa_beqi_op; + case 1: /* BNEI: m=01 */ + return xtensa_bnei_op; + case 2: /* BLTI: m=10 */ + return xtensa_blti_op; + case 3: /* BGEI: m=11 */ + return xtensa_bgei_op; + } + break; + case 3: /* BI1: n=11 */ + switch (get_m_field (insn)) { + case 0: /* ENTRY: m=00 */ + return xtensa_entry_op; + case 1: /* B1: m=01 */ + switch (get_r_field (insn)) { + case 8: /* LOOP: r=1000 */ + return xtensa_loop_op; + case 9: /* LOOPNEZ: r=1001 */ + return xtensa_loopnez_op; + case 10: /* LOOPGTZ: r=1010 */ + return xtensa_loopgtz_op; + } + break; + case 2: /* BLTUI: m=10 */ + return xtensa_bltui_op; + case 3: /* BGEUI: m=11 */ + return xtensa_bgeui_op; + } + break; + } + break; + case 9: /* S32I.N: op0=1001 */ + return xtensa_s32i_n_op; + case 10: /* ADD.N: op0=1010 */ + return xtensa_add_n_op; + case 7: /* B: op0=0111 */ + switch (get_r_field (insn)) { + case 6: /* BBCI: r=011x */ + case 7: /* BBCI: r=011x */ + return xtensa_bbci_op; + case 0: /* BNONE: r=0000 */ + return xtensa_bnone_op; + case 1: /* BEQ: r=0001 */ + return xtensa_beq_op; + case 2: /* BLT: r=0010 */ + return xtensa_blt_op; + case 4: /* BALL: r=0100 */ + return xtensa_ball_op; + case 14: /* BBSI: r=111x */ + case 15: /* BBSI: r=111x */ + return xtensa_bbsi_op; + case 3: /* BLTU: r=0011 */ + return xtensa_bltu_op; + case 5: /* BBC: r=0101 */ + return xtensa_bbc_op; + case 8: /* BANY: r=1000 */ + return xtensa_bany_op; + case 9: /* BNE: r=1001 */ + return xtensa_bne_op; + case 10: /* BGE: r=1010 */ + return xtensa_bge_op; + case 11: /* BGEU: r=1011 */ + return xtensa_bgeu_op; + case 12: /* BNALL: r=1100 */ + return xtensa_bnall_op; + case 13: /* BBS: r=1101 */ + return xtensa_bbs_op; + } + break; + case 11: /* ADDI.N: op0=1011 */ + return xtensa_addi_n_op; + case 12: /* ST2: op0=1100 */ + switch (get_i_field (insn)) { + case 0: /* MOVI.N: i=0 */ + return xtensa_movi_n_op; + case 1: /* BZ6: i=1 */ + switch (get_z_field (insn)) { + case 0: /* BEQZ.N: z=0 */ + return xtensa_beqz_n_op; + case 1: /* BNEZ.N: z=1 */ + return xtensa_bnez_n_op; + } + break; + } + break; + case 13: /* ST3: op0=1101 */ + switch (get_r_field (insn)) { + case 15: /* S3: r=1111 */ + switch (get_t_field (insn)) { + case 0: /* RET.N: t=0000 */ + return xtensa_ret_n_op; + case 1: /* RETW.N: t=0001 */ + return xtensa_retw_n_op; + case 2: /* BREAK.N: t=0010 */ + return xtensa_break_n_op; + case 3: /* NOP.N: t=0011 */ + return xtensa_nop_n_op; + } + break; + case 0: /* MOV.N: r=0000 */ + return xtensa_mov_n_op; + } + break; + } + return XTENSA_UNDEFINED; +} + +int +interface_version (void) +{ + return 3; +} + +static struct config_struct config_table[] = { + {"IsaMemoryOrder", "BigEndian"}, + {"PIFReadDataBits", "128"}, + {"PIFWriteDataBits", "128"}, + {"IsaCoprocessorCount", "0"}, + {"IsaUseBooleans", "0"}, + {"IsaUseDensityInstruction", "1"}, + {0, 0} +}; + +struct config_struct * get_config_table (void); + +struct config_struct * +get_config_table (void) +{ + return config_table; +} + +xtensa_isa_module xtensa_isa_modules[] = { + { get_num_opcodes, get_opcodes, decode_insn, get_config_table }, + { 0, 0, 0, 0 } +}; diff --git a/config/accross.m4 b/config/accross.m4 new file mode 100644 index 0000000..a4cebf6 --- /dev/null +++ b/config/accross.m4 @@ -0,0 +1,98 @@ +AC_DEFUN([AC_COMPILE_CHECK_SIZEOF], +[changequote(<<, >>)dnl +dnl The name to #define. +define(<>, translit(sizeof_$1, [a-z *], [A-Z_P]))dnl +dnl The cache variable name. +define(<>, translit(ac_cv_sizeof_$1, [ *], [_p]))dnl +changequote([, ])dnl +AC_MSG_CHECKING(size of $1) +AC_CACHE_VAL(AC_CV_NAME, +[for ac_size in 4 8 1 2 16 12 $2 ; do # List sizes in rough order of prevalence. + AC_TRY_COMPILE([#include "confdefs.h" +#include +$2 +], [switch (0) case 0: case (sizeof ($1) == $ac_size):;], AC_CV_NAME=$ac_size) + if test x$AC_CV_NAME != x ; then break; fi +done +]) +if test x$AC_CV_NAME = x ; then + AC_MSG_ERROR([cannot determine a size for $1]) +fi +AC_MSG_RESULT($AC_CV_NAME) +AC_DEFINE_UNQUOTED(AC_TYPE_NAME, $AC_CV_NAME, [The number of bytes in type $1]) +undefine([AC_TYPE_NAME])dnl +undefine([AC_CV_NAME])dnl +]) + +AC_DEFUN([AC_C_BIGENDIAN_CROSS], +[AC_CACHE_CHECK(whether byte ordering is bigendian, ac_cv_c_bigendian, +[ac_cv_c_bigendian=unknown +# See if sys/param.h defines the BYTE_ORDER macro. +AC_TRY_COMPILE([#include +#include ], [ +#if !BYTE_ORDER || !BIG_ENDIAN || !LITTLE_ENDIAN + bogus endian macros +#endif], [# It does; now see whether it defined to BIG_ENDIAN or not. +AC_TRY_COMPILE([#include +#include ], [ +#if BYTE_ORDER != BIG_ENDIAN + not big endian +#endif], ac_cv_c_bigendian=yes, ac_cv_c_bigendian=no)]) +if test $ac_cv_c_bigendian = unknown; then +AC_TRY_RUN([main () { + /* Are we little or big endian? From Harbison&Steele. */ + union + { + long l; + char c[sizeof (long)]; + } u; + u.l = 1; + exit (u.c[sizeof (long) - 1] == 1); +}], ac_cv_c_bigendian=no, ac_cv_c_bigendian=yes, +[ echo $ac_n "cross-compiling... " 2>&AC_FD_MSG ]) +fi]) +if test $ac_cv_c_bigendian = unknown; then +AC_MSG_CHECKING(to probe for byte ordering) +[ +cat >conftest.c <&AC_FD_MSG + ac_cv_c_bigendian=yes + fi + if test `grep -l LiTTleEnDian conftest.o` ; then + echo $ac_n ' little endian probe OK, ' 1>&AC_FD_MSG + if test $ac_cv_c_bigendian = yes ; then + ac_cv_c_bigendian=unknown; + else + ac_cv_c_bigendian=no + fi + fi + echo $ac_n 'guessing bigendian ... ' >&AC_FD_MSG + fi + fi +AC_MSG_RESULT($ac_cv_c_bigendian) +fi +if test $ac_cv_c_bigendian = yes; then + AC_DEFINE(WORDS_BIGENDIAN, 1, [whether byteorder is bigendian]) + AC_DEFINE(HOST_WORDS_BIG_ENDIAN, 1, + [Define if the host machine stores words of multi-word integers in + big-endian order.]) + BYTEORDER=4321 +else + BYTEORDER=1234 +fi +AC_DEFINE_UNQUOTED(BYTEORDER, $BYTEORDER, [1234 = LIL_ENDIAN, 4321 = BIGENDIAN]) +if test $ac_cv_c_bigendian = unknown; then + AC_MSG_ERROR(unknown endianess - sorry, please pre-set ac_cv_c_bigendian) +fi +]) diff --git a/config/acx.m4 b/config/acx.m4 new file mode 100644 index 0000000..96b7c8a --- /dev/null +++ b/config/acx.m4 @@ -0,0 +1,157 @@ +# Autoconf M4 include file defining utility macros for complex Canadian +# cross builds. + +dnl #### +dnl # _GCC_TOPLEV_NONCANONICAL_BUILD +dnl # $build_alias or canonical $build if blank. +dnl # Used when we would use $build_alias, but empty is not OK. +AC_DEFUN([_GCC_TOPLEV_NONCANONICAL_BUILD], +[AC_REQUIRE([AC_CANONICAL_BUILD]) []dnl +case ${build_alias} in + "") build_noncanonical=${build} ;; + *) build_noncanonical=${build_alias} ;; +esac +]) []dnl # _GCC_TOPLEV_NONCANONICAL_BUILD + +dnl #### +dnl # _GCC_TOPLEV_NONCANONICAL_HOST +dnl # $host_alias, or $build_noncanonical if blank. +dnl # Used when we would use $host_alias, but empty is not OK. +AC_DEFUN([_GCC_TOPLEV_NONCANONICAL_HOST], +[AC_REQUIRE([_GCC_TOPLEV_NONCANONICAL_BUILD]) []dnl +case ${host_alias} in + "") host_noncanonical=${build_noncanonical} ;; + *) host_noncanonical=${host_alias} ;; +esac +]) []dnl # _GCC_TOPLEV_NONCANONICAL_HOST + +dnl #### +dnl # _GCC_TOPLEV_NONCANONICAL_TARGET +dnl # $target_alias or $host_noncanonical if blank. +dnl # Used when we would use $target_alias, but empty is not OK. +AC_DEFUN([_GCC_TOPLEV_NONCANONICAL_TARGET], +[AC_REQUIRE([_GCC_TOPLEV_NONCANONICAL_HOST]) []dnl +case ${target_alias} in + "") target_noncanonical=${host_noncanonical} ;; + *) target_noncanonical=${target_alias} ;; +esac +]) []dnl # _GCC_TOPLEV_NONCANONICAL_TARGET + +dnl #### +dnl # GCC_TOPLEV_SUBDIRS +dnl # GCC & friends build 'build', 'host', and 'target' tools. These must +dnl # be separated into three well-known subdirectories of the build directory: +dnl # build_subdir, host_subdir, and target_subdir. The values are determined +dnl # here so that they can (theoretically) be changed in the future. They +dnl # were previously reproduced across many different files. +dnl # +dnl # This logic really amounts to very little with autoconf 2.13; it will +dnl # amount to a lot more with autoconf 2.5x. +AC_DEFUN([GCC_TOPLEV_SUBDIRS], +[AC_REQUIRE([_GCC_TOPLEV_NONCANONICAL_TARGET]) []dnl +AC_REQUIRE([_GCC_TOPLEV_NONCANONICAL_BUILD]) []dnl +# Prefix 'build-' so this never conflicts with target_subdir. +build_subdir="build-${build_noncanonical}" +# Not really a subdirectory, but here for completeness. +host_subdir=. +# No prefix. +target_subdir=${target_noncanonical} +AC_SUBST([build_subdir]) []dnl +AC_SUBST([host_subdir]) []dnl +AC_SUBST([target_subdir]) []dnl +]) []dnl # GCC_TOPLEV_SUBDIRS + + +#### +# _NCN_TOOL_PREFIXES: Some stuff that oughtta be done in AC_CANONICAL_SYSTEM +# or AC_INIT. +# These demand that AC_CANONICAL_SYSTEM be called beforehand. +AC_DEFUN([_NCN_TOOL_PREFIXES], +[ncn_tool_prefix= +test -n "$host_alias" && ncn_tool_prefix=$host_alias- +ncn_target_tool_prefix= +test -n "$target_alias" && ncn_target_tool_prefix=$target_alias- +]) []dnl # _NCN_TOOL_PREFIXES + +#### +# NCN_CHECK_TARGET_TOOL(variable, prog-to-check-for,[value-if-not-found],[path]) +# Like AC_CHECK_TOOL, but tries a prefix of the target, not the host. +# Code is pretty much lifted from autoconf2.53. + +AC_DEFUN([NCN_CHECK_TARGET_TOOL], +[AC_REQUIRE([_NCN_TOOL_PREFIXES]) []dnl +if test -n "$ncn_target_tool_prefix"; then + AC_CHECK_PROG([$1], [${ncn_target_tool_prefix}$2], + [${ncn_target_tool_prefix}$2], , [$4]) +fi +if test -z "$ac_cv_prog_$1" ; then + ncn_cv_$1=$$1 + AC_CHECK_PROG([ncn_cv_$1], [$2], [$2], [$3], [$4]) + $1=$ncn_cv_$1 +else + $1="$ac_cv_prog_$1" +fi +]) []dnl # NCN_CHECK_TARGET_TOOL + + +#### +# NCN_STRICT_CHECK_TOOL(variable, prog-to-check-for,[value-if-not-found],[path]) +# Like AC_CHECK_TOOL, but requires the prefix if build!=host. + +AC_DEFUN([NCN_STRICT_CHECK_TOOL], +[AC_REQUIRE([_NCN_TOOL_PREFIXES]) []dnl +if test -n "$ncn_tool_prefix"; then + AC_CHECK_PROG([$1], [${ncn_tool_prefix}$2], + [${ncn_tool_prefix}$2], , [$4]) +fi +if test -z "$ac_cv_prog_$1" ; then + if test $build = $host ; then + ncn_cv_$1=$$1 + AC_CHECK_PROG([ncn_cv_$1], [$2], [$2], [ifelse([$3],[],[$2],[$3])], [$4]) + $1=$ncn_cv_$1 + else + $1="ifelse([$3],[],[${ncn_tool_prefix}$2],[$3])" + fi +else + $1="$ac_cv_prog_$1" +fi +]) []dnl # NCN_STRICT_CHECK_TOOL + + +#### +# NCN_STRICT_CHECK_TARGET_TOOL(variable, prog-to-check-for,[value-if-not-found],[path]) +# Like NCN_CHECK_TARGET_TOOL, but requires the prefix if build!=target. + +AC_DEFUN([NCN_STRICT_CHECK_TARGET_TOOL], +[AC_REQUIRE([_NCN_TOOL_PREFIXES]) []dnl +if test -n "$ncn_target_tool_prefix"; then + AC_CHECK_PROG([$1], [${ncn_target_tool_prefix}$2], + [${ncn_target_tool_prefix}$2], , [$4]) +fi +if test -z "$ac_cv_prog_$1" ; then + if test $build = $target ; then + ncn_cv_$1=$$1 + AC_CHECK_PROG([ncn_cv_$1], [$2], [$2], [ifelse([$3],[],[$2],[$3])], [$4]) + $1=$ncn_cv_$1 + else + $1="ifelse([$3],[],[${ncn_target_tool_prefix}$2],[$3])" + fi +else + $1="$ac_cv_prog_$1" +fi +]) []dnl # NCN_STRICT_CHECK_TARGET_TOOL + +### +# AC_PROG_CPP_WERROR +# Used for autoconf 2.5x to force AC_PREPROC_IFELSE to reject code which +# triggers warnings from the preprocessor. Will be in autoconf 2.58. +# For now, using this also overrides header checks to use only the +# preprocessor (matches 2.13 behavior; matching 2.58's behavior is a +# bit harder from here). +# Eventually autoconf will default to checking headers with the compiler +# instead, and we'll have to do this differently. + +AC_DEFUN([AC_PROG_CPP_WERROR], +[AC_REQUIRE([AC_PROG_CPP])dnl +m4_define([AC_CHECK_HEADER],m4_defn([_AC_CHECK_HEADER_OLD])) +ac_c_preproc_warn_flag=yes])# AC_PROG_CPP_WERROR diff --git a/config/gettext.m4 b/config/gettext.m4 new file mode 100644 index 0000000..d10aae8 --- /dev/null +++ b/config/gettext.m4 @@ -0,0 +1,66 @@ +# intl sister-directory configuration rules. +# + +# The idea behind this macro is that there's no need to repeat all the +# autoconf probes done by the intl directory - it's already done them +# for us. In fact, there's no need even to look at the cache for the +# answers. All we need to do is nab a few pieces of information. +# The intl directory is set up to make this easy, by generating a +# small file which can be sourced as a shell script; then we produce +# the necessary substitutions and definitions for this directory. + +AC_DEFUN([ZW_GNU_GETTEXT_SISTER_DIR], +[# If we haven't got the data from the intl directory, +# assume NLS is disabled. +USE_NLS=no AC_SUBST(USE_NLS) +LIBINTL= AC_SUBST(LIBINTL) +LIBINTL_DEP= AC_SUBST(LIBINTL_DEP) +INCINTL= AC_SUBST(INCINTL) +XGETTEXT= AC_SUBST(XGETTEXT) +GMSGFMT= AC_SUBST(GMSGFMT) +POSUB= AC_SUBST(POSUB) +if test -f ../intl/config.intl; then + . ../intl/config.intl +fi +AC_MSG_CHECKING([whether NLS is requested]) +if test x"$USE_NLS" != xyes; then + AC_MSG_RESULT(no) +else + AC_MSG_RESULT(yes) + AC_DEFINE(ENABLE_NLS, 1, + [Define to 1 if translation of program messages to the + user's native language is requested.]) + + AC_MSG_CHECKING(for catalogs to be installed) + # Look for .po and .gmo files in the source directory. + CATALOGS= AC_SUBST(CATALOGS) + XLINGUAS= + for cat in $srcdir/po/*.gmo $srcdir/po/*.po; do + # If there aren't any .gmo files the shell will give us the + # literal string "../path/to/srcdir/po/*.gmo" which has to be + # weeded out. + case "$cat" in *\**) + continue;; + esac + # The quadruple backslash is collapsed to a double backslash + # by the backticks, then collapsed again by the double quotes, + # leaving us with one backslash in the sed expression (right + # before the dot that mustn't act as a wildcard). + cat=`echo $cat | sed -e "s!$srcdir/!!" -e "s!\\\\.po!.gmo!"` + lang=`echo $cat | sed -e 's!po/!!' -e "s!\\\\.gmo!!"` + # The user is allowed to set LINGUAS to a list of languages to + # install catalogs for. If it's empty that means "all of them." + if test "x$LINGUAS" = x; then + CATALOGS="$CATALOGS $cat" + XLINGUAS="$XLINGUAS $lang" + else + case "$LINGUAS" in *$lang*) + CATALOGS="$CATALOGS $cat" + XLINGUAS="$XLINGUAS $lang" + ;; + esac + fi + done + LINGUAS="$XLINGUAS" + AC_MSG_RESULT($LINGUAS) +fi]) diff --git a/config/no-executables.m4 b/config/no-executables.m4 new file mode 100644 index 0000000..ca26b71 --- /dev/null +++ b/config/no-executables.m4 @@ -0,0 +1,61 @@ +# GCC_NO_EXECUTABLES +# ----------------- +# FIXME: The GCC team has specific needs which the current Autoconf +# framework cannot solve elegantly. This macro implements a dirty +# hack until Autoconf is able to provide the services its users +# need. +# +# Several of the support libraries that are often built with GCC can't +# assume the tool-chain is already capable of linking a program: the +# compiler often expects to be able to link with some of such +# libraries. +# +# In several of these libraries, workarounds have been introduced to +# avoid the AC_PROG_CC_WORKS test, that would just abort their +# configuration. The introduction of AC_EXEEXT, enabled either by +# libtool or by CVS autoconf, have just made matters worse. +# +# Unlike the previous AC_NO_EXECUTABLES, this test does not +# disable link tests at autoconf time, but at configure time. +# This allows AC_NO_EXECUTABLES to be invoked conditionally. +AC_DEFUN_ONCE([GCC_NO_EXECUTABLES], +[m4_divert_push([KILL]) + +AC_BEFORE([$0], [_AC_COMPILER_EXEEXT]) +AC_BEFORE([$0], [AC_LINK_IFELSE]) + +m4_define([_AC_COMPILER_EXEEXT], +AC_LANG_CONFTEST([AC_LANG_PROGRAM()]) +# FIXME: Cleanup? +AS_IF([AC_TRY_EVAL(ac_link)], [gcc_no_link=no], [gcc_no_link=yes]) +if test x$gcc_no_link = xyes; then + # Setting cross_compile will disable run tests; it will + # also disable AC_CHECK_FILE but that's generally + # correct if we can't link. + cross_compiling=yes + EXEEXT= +else + m4_defn([_AC_COMPILER_EXEEXT])dnl +fi +) + +m4_define([AC_LINK_IFELSE], +if test x$gcc_no_link = xyes; then + AC_MSG_ERROR([Link tests are not allowed after [[$0]].]) +fi +m4_defn([AC_LINK_IFELSE])) + +dnl This is a shame. We have to provide a default for some link tests, +dnl similar to the default for run tests. +m4_define([AC_FUNC_MMAP], +if test x$gcc_no_link = xyes; then + if test "x${ac_cv_func_mmap_fixed_mapped+set}" != xset; then + ac_cv_func_mmap_fixed_mapped=no + fi +fi +if test "x${ac_cv_func_mmap_fixed_mapped+set}" != xset; then + m4_defn([AC_FUNC_MMAP]) +fi) + +m4_divert_pop()dnl +])# GCC_NO_EXECUTABLES diff --git a/config/progtest.m4 b/config/progtest.m4 new file mode 100644 index 0000000..8fe527c --- /dev/null +++ b/config/progtest.m4 @@ -0,0 +1,91 @@ +# progtest.m4 serial 3 (gettext-0.12) +dnl Copyright (C) 1996-2003 Free Software Foundation, Inc. +dnl This file is free software, distributed under the terms of the GNU +dnl General Public License. As a special exception to the GNU General +dnl Public License, this file may be distributed as part of a program +dnl that contains a configuration script generated by Autoconf, under +dnl the same distribution terms as the rest of that program. +dnl +dnl This file can can be used in projects which are not available under +dnl the GNU General Public License or the GNU Library General Public +dnl License but which still want to provide support for the GNU gettext +dnl functionality. +dnl Please note that the actual code of the GNU gettext library is covered +dnl by the GNU Library General Public License, and the rest of the GNU +dnl gettext package package is covered by the GNU General Public License. +dnl They are *not* in the public domain. + +dnl Authors: +dnl Ulrich Drepper , 1996. + +# Search path for a program which passes the given test. + +dnl AM_PATH_PROG_WITH_TEST(VARIABLE, PROG-TO-CHECK-FOR, +dnl TEST-PERFORMED-ON-FOUND_PROGRAM [, VALUE-IF-NOT-FOUND [, PATH]]) +AC_DEFUN([AM_PATH_PROG_WITH_TEST], +[ +# Prepare PATH_SEPARATOR. +# The user is always right. +if test "${PATH_SEPARATOR+set}" != set; then + echo "#! /bin/sh" >conf$$.sh + echo "exit 0" >>conf$$.sh + chmod +x conf$$.sh + if (PATH="/nonexistent;."; conf$$.sh) >/dev/null 2>&1; then + PATH_SEPARATOR=';' + else + PATH_SEPARATOR=: + fi + rm -f conf$$.sh +fi + +# Find out how to test for executable files. Don't use a zero-byte file, +# as systems may use methods other than mode bits to determine executability. +cat >conf$$.file <<_ASEOF +#! /bin/sh +exit 0 +_ASEOF +chmod +x conf$$.file +if test -x conf$$.file >/dev/null 2>&1; then + ac_executable_p="test -x" +else + ac_executable_p="test -f" +fi +rm -f conf$$.file + +# Extract the first word of "$2", so it can be a program name with args. +set dummy $2; ac_word=[$]2 +AC_MSG_CHECKING([for $ac_word]) +AC_CACHE_VAL(ac_cv_path_$1, +[case "[$]$1" in + [[\\/]]* | ?:[[\\/]]*) + ac_cv_path_$1="[$]$1" # Let the user override the test with a path. + ;; + *) + ac_save_IFS="$IFS"; IFS=$PATH_SEPARATOR + for ac_dir in ifelse([$5], , $PATH, [$5]); do + IFS="$ac_save_IFS" + test -z "$ac_dir" && ac_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if $ac_executable_p "$ac_dir/$ac_word$ac_exec_ext"; then + if [$3]; then + ac_cv_path_$1="$ac_dir/$ac_word$ac_exec_ext" + break 2 + fi + fi + done + done + IFS="$ac_save_IFS" +dnl If no 4th arg is given, leave the cache variable unset, +dnl so AC_PATH_PROGS will keep looking. +ifelse([$4], , , [ test -z "[$]ac_cv_path_$1" && ac_cv_path_$1="$4" +])dnl + ;; +esac])dnl +$1="$ac_cv_path_$1" +if test ifelse([$4], , [-n "[$]$1"], ["[$]$1" != "$4"]); then + AC_MSG_RESULT([$]$1) +else + AC_MSG_RESULT(no) +fi +AC_SUBST($1)dnl +]) diff --git a/cpu/ChangeLog b/cpu/ChangeLog new file mode 100644 index 0000000..faeb5a6 --- /dev/null +++ b/cpu/ChangeLog @@ -0,0 +1,148 @@ +2003-10-10 Dave Brolley + + * frv.cpu (dnpmop): New p-macro. + (GRdoublek): Use dnpmop. + (CPRdoublek, FRdoublei, FRdoublej, FRdoublek): Ditto. + (store-double-r-r): Use (.sym regtype doublek). + (r-store-double): Ditto. + (store-double-r-r-u): Ditto. + (conditional-store-double): Ditto. + (conditional-store-double-u): Ditto. + (store-double-r-simm): Ditto. + (fmovs): Assign to UNIT FMALL. + +2003-10-06 Dave Brolley + + * frv.cpu, frv.opc: Add support for fr550. + +2003-09-24 Dave Brolley + + * frv.cpu (u-commit): New modelling unit for fr500. + (mwtaccg): Use frv_ref_SI to reference ACC40Sk as an input operand. + (commit-r): Use u-commit model for fr500. + (commit): Ditto. + (conditional-float-binary-op): Take profiling data as an argument. + Update callers. + (ne-float-binary-op): Ditto. + +2003-09-19 Michael Snyder + + * frv.cpu (nldqi): Delete unimplemented instruction. + +2003-09-12 Dave Brolley + + * frv.cpu (u-clrgr, u-clrfr): New units of model fr500. + (clear-ne-flag-r): Pass insn profiling in as an argument. Call + frv_ref_SI to get input register referenced for profiling. + (clear-ne-flag-all): Pass insn profiling in as an argument. + (clrgr,clrfr,clrga,clrfa): Add profiling information. + +2003-09-11 Michael Snyder + + * frv.cpu: Typographical corrections. + +2003-09-09 Dave Brolley + + * frv.cpu (media-dual-complex): Change UNIT to FMALL. + (conditional-media-dual-complex, media-quad-complex): Likewise. + +2003-09-04 Dave Brolley + + * frv.cpu (register-transfer): Pass in all attributes in on argument. + Update all callers. + (conditional-register-transfer): Ditto. + (cache-preload): Ditto. + (floating-point-conversion): Ditto. + (floating-point-neg): Ditto. + (float-abs): Ditto. + (float-binary-op-s): Ditto. + (conditional-float-binary-op): Ditto. + (ne-float-binary-op): Ditto. + (float-dual-arith): Ditto. + (ne-float-dual-arith): Ditto. + +2003-09-03 Dave Brolley + + * frv.opc (parse_A, parse_A0, parse_A1): New parse handlers. + * frv.cpu (UNIT): Add IALL, FMALL, FMLOW, STORE, SCAN, DCPL, MDUALACC, + MCLRACC-1. + (A): Removed operand. + (A0,A1): New operands replace operand A. + (mnop): Now a real insn + (mclracc): Removed insn. + (mclracc-0, mclracc-1): New insns replace mclracc. + (all insns): Use new UNIT attributes. + +2003-08-21 Nick Clifton + + * frv.cpu (mbtoh): Replace input parameter to u-media-dual-expand + and u-media-dual-btoh with output parameter. + (cmbtoh): Add profiling hack. + +2003-08-19 Michael Snyder + + * frv.cpu: Fix typo, Frintkeven -> FRintkeven + +2003-06-10 Doug Evans + + * frv.cpu: Add IDOC attribute. + +2003-06-06 Andrew Cagney + + Contributed by Red Hat. + * iq2000.cpu: New file. Written by Ben Elliston, Jeff Johnston, + Stan Cox, and Frank Ch. Eigler. + * iq2000.opc: New file. Written by Ben Elliston, Frank + Ch. Eigler, Chris Moller, Jeff Johnston, and Stan Cox. + * iq2000m.cpu: New file. Written by Jeff Johnston. + * iq10.cpu: New file. Written by Jeff Johnston. + +2003-06-05 Nick Clifton + + * frv.cpu (FRintieven): New operand. An even-numbered only + version of the FRinti operand. + (FRintjeven): Likewise for FRintj. + (FRintkeven): Likewise for FRintk. + (mdcutssi, media-dual-word-rotate-r-r, mqsaths, + media-quad-arith-sat-semantics, media-quad-arith-sat, + conditional-media-quad-arith-sat, mdunpackh, + media-quad-multiply-semantics, media-quad-multiply, + conditional-media-quad-multiply, media-quad-complex-i, + media-quad-multiply-acc-semantics, media-quad-multiply-acc, + conditional-media-quad-multiply-acc, munpackh, + media-quad-multiply-cross-acc-semantics, mdpackh, + media-quad-multiply-cross-acc, mbtoh-semantics, + media-quad-cross-multiply-cross-acc-semantics, + media-quad-cross-multiply-cross-acc, mbtoh, mhtob-semantics, + media-quad-cross-multiply-acc-semantics, cmbtoh, + media-quad-cross-multiply-acc, media-quad-complex, mhtob, + media-expand-halfword-to-double-semantics, mexpdhd, cmexpdhd, + cmhtob): Use new operands. + * frv.opc (CGEN_VERBOSE_ASSEMBLER_ERRORS): Define. + (parse_even_register): New function. + +2003-06-03 Nick Clifton + + * frv.cpu (media-dual-word-rotate-r-r): Use a signed 6-bit + immediate value not unsigned. + +2003-06-03 Andrew Cagney + + Contributed by Red Hat. + * frv.cpu: New file. Written by Dave Brolley, Catherine Moore, + and Eric Christopher. + * frv.opc: New file. Written by Catherine Moore, and Dave + Brolley. + * simplify.inc: New file. Written by Doug Evans. + +2003-05-02 Andrew Cagney + + * New file. + + +Local Variables: +mode: change-log +left-margin: 8 +fill-column: 74 +version-control: never +End: diff --git a/cpu/frv.cpu b/cpu/frv.cpu new file mode 100644 index 0000000..f7bb296 --- /dev/null +++ b/cpu/frv.cpu @@ -0,0 +1,8894 @@ +; Fujitsu FRV opcode support, for GNU Binutils. -*- Scheme -*- +; +; Copyright 2000, 2001, 2003 Free Software Foundation, Inc. +; +; Contributed by Red Hat Inc; developed under contract from Fujitsu. +; +; This file is part of the GNU Binutils. +; +; This program is free software; you can redistribute it and/or modify +; it under the terms of the GNU General Public License as published by +; the Free Software Foundation; either version 2 of the License, or +; (at your option) any later version. +; +; This program is distributed in the hope that it will be useful, +; but WITHOUT ANY WARRANTY; without even the implied warranty of +; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +; GNU General Public License for more details. +; +; You should have received a copy of the GNU General Public License +; along with this program; if not, write to the Free Software +; Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +(include "simplify.inc") + +; define-arch must appear first + +(define-arch + (name frv) ; name of cpu architecture + (comment "Fujitsu FRV") + (insn-lsb0? #t) + (machs frv fr550 fr500 fr400 tomcat simple) + (isas frv) +) + +(define-isa + (name frv) + (base-insn-bitsize 32) + ; Initial bitnumbers to decode insns by. + (decode-assist (24 23 22 21 20 19 18)) + (liw-insns 1) ; The frv fetches up to 1 insns at a time. + (parallel-insns 8) ; The frv executes up to 8 insns at a time. +) + +; Cpu family definitions. +; +(define-cpu + ; cpu names must be distinct from the architecture name and machine names. + ; The "b" suffix stands for "base" and is the convention. + ; The "f" suffix stands for "family" and is the convention. + (name frvbf) + (comment "Fujitsu FRV base family") + (endian big) + (word-bitsize 32) +) + +; Generic FR-V machine. Supports the entire architecture +(define-mach + (name frv) + (comment "Generic FRV cpu") + (cpu frvbf) +) +(define-model + (name frv) (comment "Generic FRV model") (attrs) + (mach frv) + + (pipeline all "" () ((fetch) (decode) (execute) (writeback))) + + ; `state' is a list of variables for recording model state + ; (state) + + (unit u-exec "Execution Unit" () + 1 1 ; issue done + () ; state + () ; inputs + () ; outputs + () ; profile action (default) + ) +) + +; FR550 machine +(define-mach + (name fr550) + (comment "FR550 cpu") + (cpu frvbf) +) +(define-model + (name fr550) (comment "FR550 model") (attrs) + (mach fr550) + + (pipeline all "" () ((fetch) (decode) (execute) (writeback))) + + ; `state' is a list of variables for recording model state + (state + ; State items + ; These are all masks with each bit representing one register. + (prev-fr-load DI) ; Previous use of FR register was target of a load + (prev-fr-complex-1 DI) ; Previous use of FR register has variable latency + (prev-fr-complex-2 DI) ; Previous use of FR register has variable latency + (prev-ccr-complex DI) ; Previous use of CCR register has variable latency + (prev-acc-mmac DI) ; Previous use of ACC register was a MMAC category + (cur-fr-load DI) ; Current use of FR register was target of a load + (cur-fr-complex-1 DI) ; Current use of FR register has variable latency + (cur-fr-complex-2 DI) ; Current use of FR register has variable latency + (cur-ccr-complex SI) ; Current use of CCR register has variable latency + (cur-acc-mmac DI) ; Current use of ACC register was a MMAC category + ) + ; Basic unit for instructions with no latency penalties + (unit u-exec "Execution Unit" () + 1 1 ; issue done + () ; state + () ; inputs + () ; outputs + () ; profile action (default) + ) + ; Basic integer insn unit + (unit u-integer "Integer Unit" () + 1 1 ; issue done + () ; state + ((GRi INT -1) (GRj INT -1)) ; inputs + ((GRk INT -1) (ICCi_1 INT -1)) ; outputs + () ; profile action (default) + ) + ; Integer multiplication unit + (unit u-imul "Integer Multiplication Unit" () + 1 1 ; issue done + () ; state + ((GRi INT -1) (GRj INT -1)) ; inputs + ((GRdoublek INT -1) (ICCi_1 INT -1)) ; outputs + () ; profile action (default) + ) + ; Integer division unit + (unit u-idiv "Integer Division Unit" () + 1 1 ; issue done + () ; state + ((GRi INT -1) (GRj INT -1)) ; inputs + ((GRk INT -1) (ICCi_1 INT -1)) ; outputs + () ; profile action (default) + ) + ; Branch unit + (unit u-branch "Branch Unit" () + 1 1 ; issue done + () ; state + ((GRi INT -1) (GRj INT -1) + (ICCi_2 INT -1) (FCCi_2 INT -1)) ; inputs + ((pc)) ; outputs + () ; profile action (default) + ) + ; Trap unit + (unit u-trap "Trap Unit" () + 1 1 ; issue done + () ; state + ((GRi INT -1) (GRj INT -1) + (ICCi_2 INT -1) (FCCi_2 INT -1)) ; inputs + () ; outputs + () ; profile action (default) + ) + ; Condition code check unit + (unit u-check "Check Unit" () + 1 1 ; issue done + () ; state + ((ICCi_3 INT -1) (FCCi_3 INT -1)) ; inputs + () ; outputs + () ; profile action (default) + ) + ; Float Arithmetic unit + (unit u-float-arith "Float Arithmetic unit" () + 1 1 ; issue done + () ; state + ((FRi INT -1) (FRj INT -1) ; inputs + (FRdoublei INT -1) (FRdoublej INT -1)) ; inputs + ((FRk INT -1) (FRdoublek INT -1)) ; outputs + () ; profile action (default) + ) + ; Float Dual Arithmetic unit + (unit u-float-dual-arith "Float Arithmetic unit" () + ; This unit has a 2 cycle penalty -- see table 14-14 in the fr550 LSI + 1 3 ; issue done + () ; state + ((FRi INT -1) (FRj INT -1) ; inputs + (FRdoublei INT -1) (FRdoublej INT -1)) ; inputs + ((FRk INT -1) (FRdoublek INT -1)) ; outputs + () ; profile action (default) + ) + ; Float Div unit + (unit u-float-div "Float Div unit" () + 1 1 ; issue done + () ; state + ((FRi INT -1) (FRj INT -1)) ; inputs + ((FRk INT -1)) ; outputs + () ; profile action (default) + ) + ; Float Square Root unit + (unit u-float-sqrt "Float Square Root unit" () + 1 1 ; issue done + () ; state + ((FRj INT -1) (FRdoublej INT -1)) ; inputs + ((FRk INT -1) (FRdoublek INT -1)) ; outputs + () ; profile action (default) + ) + ; Float Compare unit + (unit u-float-compare "Float Compare unit" () + 1 1 ; issue done + () ; state + ((FRi INT -1) (FRj INT -1) + (FRdoublei INT -1) (FRdoublej INT -1)) ; inputs + ((FCCi_2 INT -1)) ; outputs + () ; profile action (default) + ) + ; Dual Float Compare unit + (unit u-float-dual-compare "Float Dual Compare unit" () + ; This unit has a 2 cycle penalty -- see table 14-14 in the fr550 LSI + 1 3 ; issue done + () ; state + ((FRi INT -1) (FRj INT -1)) ; inputs + ((FCCi_2 INT -1)) ; outputs + () ; profile action (default) + ) + ; FR Move to GR unit + (unit u-fr2gr "FR Move to GR Unit" () + 1 1 ; issue done + () ; state + ((FRintk INT -1)) ; inputs + ((GRj INT -1)) ; outputs + () ; profile action (default) + ) + ; GR Move to FR unit + (unit u-gr2fr "GR Move to FR Unit" () + 1 1 ; issue done + () ; state + ((GRj INT -1)) ; inputs + ((FRintk INT -1)) ; outputs + () ; profile action (default) + ) + ; SPR Move to GR unit + (unit u-spr2gr "SPR Move to GR Unit" () + 1 1 ; issue done + () ; state + ((spr INT -1)) ; inputs + ((GRj INT -1)) ; outputs + () ; profile action (default) + ) + ; GR Move to SPR unit + (unit u-gr2spr "GR Move to SPR Unit" () + 1 1 ; issue done + () ; state + ((GRj INT -1)) ; inputs + ((spr INT -1)) ; outputs + () ; profile action (default) + ) + ; GR set half unit + (unit u-set-hilo "GR Set Half" () + 1 1 ; issue done + () ; state + () ; inputs + ((GRkhi INT -1) (GRklo INT -1)) ; outputs + () ; profile action (default) + ) + ; GR load unit + (unit u-gr-load "GR Load Unit" () + 1 1 ; issue done + () ; state + ((GRi INT -1) (GRj INT -1)) ; inputs + ((GRk INT -1) (GRdoublek INT -1)) ; outputs + () ; profile action (default) + ) + ; GR store unit + (unit u-gr-store "GR Store Unit" () + 1 1 ; issue done + () ; state + ((GRi INT -1) (GRj INT -1) (GRk INT -1) (GRdoublek INT -1)) ; inputs + () ; outputs + () ; profile action (default) + ) + ; FR load unit + (unit u-fr-load "FR Load Unit" () + 1 1 ; issue done + () ; state + ((GRi INT -1) (GRj INT -1)) ; inputs + ((FRintk INT -1) (FRdoublek INT -1)) ; outputs + () ; profile action (default) + ) + ; FR store unit + (unit u-fr-store "FR Store Unit" () + 1 1 ; issue done + () ; state + ((GRi INT -1) (GRj INT -1) (FRintk INT -1) (FRdoublek INT -1)) ; inputs + () ; outputs + () ; profile action (default) + ) + ; Swap unit + (unit u-swap "Swap Unit" () + 1 1 ; issue done + () ; state + ((GRi INT -1) (GRj INT -1)) ; inputs + ((GRk INT -1)) ; outputs + () ; profile action (default) + ) + ; FR Move to FR unit + (unit u-fr2fr "FR Move to FR Unit" () + 1 1 ; issue done + () ; state + ((FRi INT -1)) ; inputs + ((FRk INT -1)) ; outputs + () ; profile action (default) + ) + ; Clrgr unit + (unit u-clrgr "Clrgr Unit" () + 1 1 ; issue done + () ; state + ((GRk INT -1)) ; inputs + () ; outputs + () ; profile action (default) + ) + ; Clrfr unit + (unit u-clrfr "Clrfr Unit" () + 1 1 ; issue done + () ; state + ((FRk INT -1)) ; inputs + () ; outputs + () ; profile action (default) + ) + ; Insn cache invalidate unit + (unit u-ici "Insn cache invalidate unit" () + 1 1 ; issue done + () ; state + ((GRi INT -1) (GRj INT -1)) ; inputs + () ; outputs + () ; profile action (default) + ) + ; Data cache invalidate unit + (unit u-dci "Data cache invalidate unit" () + 1 1 ; issue done + () ; state + ((GRi INT -1) (GRj INT -1)) ; inputs + () ; outputs + () ; profile action (default) + ) + ; Data cache flush unit + (unit u-dcf "Data cache flush unit" () + 1 1 ; issue done + () ; state + ((GRi INT -1) (GRj INT -1)) ; inputs + () ; outputs + () ; profile action (default) + ) + ; Insn cache preload unit + (unit u-icpl "Insn cache preload unit" () + 1 1 ; issue done + () ; state + ((GRi INT -1) (GRj INT -1)) ; inputs + () ; outputs + () ; profile action (default) + ) + ; Data cache preload unit + (unit u-dcpl "Data cache preload unit" () + 1 1 ; issue done + () ; state + ((GRi INT -1) (GRj INT -1)) ; inputs + () ; outputs + () ; profile action (default) + ) + ; Insn cache unlock unit + (unit u-icul "Insn cache unlock unit" () + 1 1 ; issue done + () ; state + ((GRi INT -1) (GRj INT -1)) ; inputs + () ; outputs + () ; profile action (default) + ) + ; Data cache unlock unit + (unit u-dcul "Data cache unlock unit" () + 1 1 ; issue done + () ; state + ((GRi INT -1) (GRj INT -1)) ; inputs + () ; outputs + () ; profile action (default) + ) + ; commit unit + (unit u-commit "Commit Unit" () + 1 1 ; issue done + () ; state + ((GRk INT -1) (FRk INT -1)) ; inputs + () ; outputs + () ; profile action (default) + ) + ; Float Conversion unit + (unit u-float-convert "Float Conversion unit" () + 1 1 ; issue done + () ; state + ((FRj INT -1) (FRintj INT -1) (FRdoublej INT -1)) ; inputs + ((FRk INT -1) (FRintk INT -1) (FRdoublek INT -1)) ; outputs + () ; profile action (default) + ) + ; Media units + (unit u-media "Media unit" () + 1 1 ; issue done + () ; state + ((FRinti INT -1) (FRintj INT -1)) ; inputs + ((FRintk INT -1)) ; outputs + () ; profile action (default) + ) + (unit u-media-quad "Media-quad unit" () + 1 1 ; issue done + () ; state + ((FRintieven INT -1) (FRintjeven INT -1)) ; inputs + ((FRintkeven INT -1)) ; outputs + () ; profile action (default) + ) + (unit u-media-dual-expand "Media Dual Expand unit" () + 1 1 ; issue done + () ; state + ((FRinti INT -1)) ; inputs + ((FRintkeven INT -1)) ; outputs + () ; profile action (default) + ) + (unit u-media-3-dual "Media-3-dual unit" () + 1 1 ; issue done + () ; state + ((FRinti INT -1)) ; inputs + ((FRintk INT -1)) ; outputs + () ; profile action (default) + ) + (unit u-media-3-acc "Media unit for M-3 using ACC" () + 1 1 ; issue done + () ; state + ((FRintj INT -1) (ACC40Si INT -1)) ; inputs + ((FRintk INT -1)) ; outputs + () ; profile action (default) + ) + (unit u-media-3-acc-dual "Media-3-acc-dual unit" () + 1 1 ; issue done + () ; state + ((ACC40Si INT -1)) ; inputs + ((FRintkeven INT -1)) ; outputs + () ; profile action (default) + ) + (unit u-media-3-wtacc "Media-3-wtacc unit" () + 1 1 ; issue done + () ; state + ((FRinti INT -1) (ACC40Sk INT -1)) ; inputs + () ; outputs + () ; profile action (default) + ) + (unit u-media-3-mclracc "Media-3-mclracc unit" () + 1 1 ; issue done + () ; state + () ; inputs + () ; outputs + () ; profile action (default) + ) + (unit u-media-set "Media set" () + 1 1 ; issue done + () ; state + () ; inputs + ((FRintk INT -1)) ; outputs + () ; profile action (default) + ) + (unit u-media-4 "Media-4 unit" () + 1 1 ; issue done + () ; state + ((FRinti INT -1) (FRintj INT -1)) ; inputs + ((ACC40Sk INT -1) (ACC40Uk INT -1)) ; outputs + () ; profile action (default) + ) + (unit u-media-4-acc "Media-4-acc unit" () + 1 1 ; issue done + () ; state + ((ACC40Si INT -1)) ; inputs + ((ACC40Sk INT -1)) ; outputs + () ; profile action (default) + ) + (unit u-media-4-acc-dual "Media-4-acc-dual unit" () + 1 1 ; issue done + () ; state + ((ACC40Si INT -1)) ; inputs + ((ACC40Sk INT -1)) ; outputs + () ; profile action (default) + ) + (unit u-media-4-add-sub "Media-4-add-sub unit" () + 1 1 ; issue done + () ; state + ((ACC40Si INT -1)) ; inputs + ((ACC40Sk INT -1)) ; outputs + () ; profile action (default) + ) + (unit u-media-4-add-sub-dual "Media-4-add-sub-dual unit" () + 1 1 ; issue done + () ; state + ((ACC40Si INT -1)) ; inputs + ((ACC40Sk INT -1)) ; outputs + () ; profile action (default) + ) + (unit u-media-4-quad "Media-4-quad unit" () + 1 1 ; issue done + () ; state + ((FRintieven INT -1) (FRintjeven INT -1)) ; inputs + ((ACC40Sk INT -1) (ACC40Uk INT -1)) ; outputs + () ; profile action (default) + ) +) + +; FR500 machine. +(define-mach + (name fr500) + (comment "FR500 cpu") + (cpu frvbf) +) +(define-model + (name fr500) (comment "FR500 model") (attrs) + (mach fr500) + + (pipeline all "" () ((fetch) (decode) (execute) (writeback))) + + ; `state' is a list of variables for recording model state + (state + ; State items + ; These are all masks with each bit representing one register. + (prev-fpop DI) ; Previous use of FR register was floating point insn + (prev-media DI) ; Previous use of FR register was a media insn + (prev-cc-complex DI) ; Previous use of ICC register was not simple + (cur-fpop DI) ; Current use of FR register was floating point insn + (cur-media DI) ; Current use of FR register was a media insn + (cur-cc-complex DI) ; Current use of ICC register was not simple + ) + ; Basic unit for instructions with no latency penalties + (unit u-exec "Execution Unit" () + 1 1 ; issue done + () ; state + () ; inputs + () ; outputs + () ; profile action (default) + ) + ; Basic integer insn unit + (unit u-integer "Integer Unit" () + 1 1 ; issue done + () ; state + ((GRi INT -1) (GRj INT -1)) ; inputs + ((GRk INT -1) (ICCi_1 INT -1)) ; outputs + () ; profile action (default) + ) + ; Integer multiplication unit + (unit u-imul "Integer Multiplication Unit" () + 1 1 ; issue done + () ; state + ((GRi INT -1) (GRj INT -1)) ; inputs + ((GRdoublek INT -1) (ICCi_1 INT -1)) ; outputs + () ; profile action (default) + ) + ; Integer division unit + (unit u-idiv "Integer Division Unit" () + 1 1 ; issue done + () ; state + ((GRi INT -1) (GRj INT -1)) ; inputs + ((GRk INT -1) (ICCi_1 INT -1)) ; outputs + () ; profile action (default) + ) + ; Branch unit + (unit u-branch "Branch Unit" () + 1 1 ; issue done + () ; state + ((GRi INT -1) (GRj INT -1) + (ICCi_2 INT -1) (FCCi_2 INT -1)) ; inputs + ((pc)) ; outputs + () ; profile action (default) + ) + ; Trap unit + (unit u-trap "Trap Unit" () + 1 1 ; issue done + () ; state + ((GRi INT -1) (GRj INT -1) + (ICCi_2 INT -1) (FCCi_2 INT -1)) ; inputs + () ; outputs + () ; profile action (default) + ) + ; Condition code check unit + (unit u-check "Check Unit" () + 1 1 ; issue done + () ; state + ((ICCi_3 INT -1) (FCCi_3 INT -1)) ; inputs + () ; outputs + () ; profile action (default) + ) + ; Clrgr unit + (unit u-clrgr "Clrgr Unit" () + 1 1 ; issue done + () ; state + ((GRk INT -1)) ; inputs + () ; outputs + () ; profile action (default) + ) + ; Clrfr unit + (unit u-clrfr "Clrfr Unit" () + 1 1 ; issue done + () ; state + ((FRk INT -1)) ; inputs + () ; outputs + () ; profile action (default) + ) + ; GR set half unit + (unit u-set-hilo "GR Set Half" () + 1 1 ; issue done + () ; state + () ; inputs + ((GRkhi INT -1) (GRklo INT -1)) ; outputs + () ; profile action (default) + ) + ; GR load unit -- TODO doesn't handle quad + (unit u-gr-load "GR Load Unit" () + 1 1 ; issue done + () ; state + ((GRi INT -1) (GRj INT -1)) ; inputs + ((GRk INT -1) (GRdoublek INT -1)) ; outputs + () ; profile action (default) + ) + ; GR store unit -- TODO doesn't handle quad + (unit u-gr-store "GR Store Unit" () + 1 1 ; issue done + () ; state + ((GRi INT -1) (GRj INT -1) (GRk INT -1) (GRdoublek INT -1)) ; inputs + () ; outputs + () ; profile action (default) + ) + ; GR recovering store unit -- TODO doesn't handle quad + (unit u-gr-r-store "GR Recovering Store Unit" () + 1 1 ; issue done + () ; state + ((GRi INT -1) (GRj INT -1) (GRk INT -1) (GRdoublek INT -1)) ; inputs + () ; outputs + () ; profile action (default) + ) + ; FR load unit -- TODO doesn't handle quad + (unit u-fr-load "FR Load Unit" () + 1 1 ; issue done + () ; state + ((GRi INT -1) (GRj INT -1)) ; inputs + ((FRintk INT -1) (FRdoublek INT -1)) ; outputs + () ; profile action (default) + ) + ; FR store unit -- TODO doesn't handle quad + (unit u-fr-store "FR Store Unit" () + 1 1 ; issue done + () ; state + ((GRi INT -1) (GRj INT -1) (FRintk INT -1) (FRdoublek INT -1)) ; inputs + () ; outputs + () ; profile action (default) + ) + ; FR recovering store unit -- TODO doesn't handle quad + (unit u-fr-r-store "FR Recovering Store Unit" () + 1 1 ; issue done + () ; state + ((GRi INT -1) (GRj INT -1) (FRintk INT -1) (FRdoublek INT -1)) ; inputs + () ; outputs + () ; profile action (default) + ) + ; Swap unit + (unit u-swap "Swap Unit" () + 1 1 ; issue done + () ; state + ((GRi INT -1) (GRj INT -1)) ; inputs + ((GRk INT -1)) ; outputs + () ; profile action (default) + ) + ; FR Move to FR unit + (unit u-fr2fr "FR Move to FR Unit" () + 1 1 ; issue done + () ; state + ((FRi INT -1)) ; inputs + ((FRk INT -1)) ; outputs + () ; profile action (default) + ) + ; FR Move to GR unit + (unit u-fr2gr "FR Move to GR Unit" () + 1 1 ; issue done + () ; state + ((FRintk INT -1)) ; inputs + ((GRj INT -1)) ; outputs + () ; profile action (default) + ) + ; SPR Move to GR unit + (unit u-spr2gr "SPR Move to GR Unit" () + 1 1 ; issue done + () ; state + ((spr INT -1)) ; inputs + ((GRj INT -1)) ; outputs + () ; profile action (default) + ) + ; GR Move to FR unit + (unit u-gr2fr "GR Move to FR Unit" () + 1 1 ; issue done + () ; state + ((GRj INT -1)) ; inputs + ((FRintk INT -1)) ; outputs + () ; profile action (default) + ) + ; GR Move to SPR unit + (unit u-gr2spr "GR Move to SPR Unit" () + 1 1 ; issue done + () ; state + ((GRj INT -1)) ; inputs + ((spr INT -1)) ; outputs + () ; profile action (default) + ) + ; Float Arithmetic unit + (unit u-float-arith "Float Arithmetic unit" () + 1 1 ; issue done + () ; state + ((FRi INT -1) (FRj INT -1) ; inputs + (FRdoublei INT -1) (FRdoublej INT -1)) ; inputs + ((FRk INT -1) (FRdoublek INT -1)) ; outputs + () ; profile action (default) + ) + ; Float Dual Arithmetic unit + (unit u-float-dual-arith "Float Arithmetic unit" () + 1 1 ; issue done + () ; state + ((FRi INT -1) (FRj INT -1) ; inputs + (FRdoublei INT -1) (FRdoublej INT -1)) ; inputs + ((FRk INT -1) (FRdoublek INT -1)) ; outputs + () ; profile action (default) + ) + ; Float Div unit + (unit u-float-div "Float Div unit" () + 1 1 ; issue done + () ; state + ((FRi INT -1) (FRj INT -1)) ; inputs + ((FRk INT -1)) ; outputs + () ; profile action (default) + ) + ; Float Square Root unit + (unit u-float-sqrt "Float Square Root unit" () + 1 1 ; issue done + () ; state + ((FRj INT -1) (FRdoublej INT -1)) ; inputs + ((FRk INT -1) (FRdoublek INT -1)) ; outputs + () ; profile action (default) + ) + ; Float Dual Square Root unit + (unit u-float-dual-sqrt "Float Dual Square Root unit" () + 1 1 ; issue done + () ; state + ((FRj INT -1)) ; inputs + ((FRk INT -1)) ; outputs + () ; profile action (default) + ) + ; Float Compare unit + (unit u-float-compare "Float Compare unit" () + 1 1 ; issue done + () ; state + ((FRi INT -1) (FRj INT -1) + (FRdoublei INT -1) (FRdoublej INT -1)) ; inputs + ((FCCi_2 INT -1)) ; outputs + () ; profile action (default) + ) + ; Dual Float Compare unit + (unit u-float-dual-compare "Float Dual Compare unit" () + 1 1 ; issue done + () ; state + ((FRi INT -1) (FRj INT -1)) ; inputs + ((FCCi_2 INT -1)) ; outputs + () ; profile action (default) + ) + ; Float Conversion unit + (unit u-float-convert "Float Conversion unit" () + 1 1 ; issue done + () ; state + ((FRj INT -1) (FRintj INT -1) (FRdoublej INT -1)) ; inputs + ((FRk INT -1) (FRintk INT -1) (FRdoublek INT -1)) ; outputs + () ; profile action (default) + ) + ; Dual Float Conversion unit + (unit u-float-dual-convert "Float Dual Conversion unit" () + 1 1 ; issue done + () ; state + ((FRj INT -1) (FRintj INT -1)) ; inputs + ((FRk INT -1) (FRintk INT -1)) ; outputs + () ; profile action (default) + ) + ; Media unit + (unit u-media "Media unit" () + 1 1 ; issue done + () ; state + ((FRinti INT -1) (FRintj INT -1) (ACC40Si INT -1) (ACCGi INT -1)) ; inputs + ((FRintk INT -1) (ACC40Sk INT -1) (ACC40Uk INT -1) (ACCGk INT -1)) ; outputs + () ; profile action (default) + ) + ; Media Quad Arithmetic unit + (unit u-media-quad-arith "Media Quad Arithmetic unit" () + 1 1 ; issue done + () ; state + ((FRinti INT -1) (FRintj INT -1)) ; inputs + ((FRintk INT -1)) ; outputs + () ; profile action (default) + ) + ; Media Dual Multiplication unit + (unit u-media-dual-mul "Media Dual Multiplication unit" () + 1 1 ; issue done + () ; state + ((FRinti INT -1) (FRintj INT -1)) ; inputs + ((ACC40Sk INT -1) (ACC40Uk INT -1)) ; outputs + () ; profile action (default) + ) + ; Media Quad Multiplication unit + (unit u-media-quad-mul "Media Quad Multiplication unit" () + 1 1 ; issue done + () ; state + ((FRinti INT -1) (FRintj INT -1)) ; inputs + ((ACC40Sk INT -1) (ACC40Uk INT -1)) ; outputs + () ; profile action (default) + ) + ; Media Quad Complex unit + (unit u-media-quad-complex "Media Quad Complex unit" () + 1 1 ; issue done + () ; state + ((FRinti INT -1) (FRintj INT -1)) ; inputs + ((ACC40Sk INT -1)) ; outputs + () ; profile action (default) + ) + ; Media Dual Expand unit + (unit u-media-dual-expand "Media Dual Expand unit" () + 1 1 ; issue done + () ; state + ((FRinti INT -1)) ; inputs + ((FRintk INT -1)) ; outputs + () ; profile action (default) + ) + ; Media Dual Unpack unit + (unit u-media-dual-unpack "Media Dual Unpack unit" () + 1 1 ; issue done + () ; state + ((FRinti INT -1)) ; inputs + ((FRintk INT -1)) ; outputs + () ; profile action (default) + ) + ; Media Dual byte to half unit + (unit u-media-dual-btoh "Media Byte to byte" () + 1 1 ; issue done + () ; state + ((FRintj INT -1)) ; inputs + ((FRintk INT -1)) ; outputs + () ; profile action (default) + ) + ; Media Dual half to byte unit + (unit u-media-dual-htob "Media Half to byte" () + 1 1 ; issue done + () ; state + ((FRintj INT -1)) ; inputs + ((FRintk INT -1)) ; outputs + () ; profile action (default) + ) + ; Media Dual byte to half unit extended + (unit u-media-dual-btohe "Media Byte to byte extended" () + 1 1 ; issue done + () ; state + ((FRintj INT -1)) ; inputs + ((FRintk INT -1)) ; outputs + () ; profile action (default) + ) + ; Barrier unit + (unit u-barrier "Barrier unit" () + 1 1 ; issue done + () ; state + () ; inputs + () ; outputs + () ; profile action (default) + ) + ; Memory Barrier unit + (unit u-membar "Memory Barrier unit" () + 1 1 ; issue done + () ; state + () ; inputs + () ; outputs + () ; profile action (default) + ) + ; Insn cache invalidate unit + (unit u-ici "Insn cache invalidate unit" () + 1 1 ; issue done + () ; state + ((GRi INT -1) (GRj INT -1)) ; inputs + () ; outputs + () ; profile action (default) + ) + ; Data cache invalidate unit + (unit u-dci "Data cache invalidate unit" () + 1 1 ; issue done + () ; state + ((GRi INT -1) (GRj INT -1)) ; inputs + () ; outputs + () ; profile action (default) + ) + ; Data cache flush unit + (unit u-dcf "Data cache flush unit" () + 1 1 ; issue done + () ; state + ((GRi INT -1) (GRj INT -1)) ; inputs + () ; outputs + () ; profile action (default) + ) + ; Insn cache preload unit + (unit u-icpl "Insn cache preload unit" () + 1 1 ; issue done + () ; state + ((GRi INT -1) (GRj INT -1)) ; inputs + () ; outputs + () ; profile action (default) + ) + ; Data cache preload unit + (unit u-dcpl "Data cache preload unit" () + 1 1 ; issue done + () ; state + ((GRi INT -1) (GRj INT -1)) ; inputs + () ; outputs + () ; profile action (default) + ) + ; Insn cache unlock unit + (unit u-icul "Insn cache unlock unit" () + 1 1 ; issue done + () ; state + ((GRi INT -1) (GRj INT -1)) ; inputs + () ; outputs + () ; profile action (default) + ) + ; Data cache unlock unit + (unit u-dcul "Data cache unlock unit" () + 1 1 ; issue done + () ; state + ((GRi INT -1) (GRj INT -1)) ; inputs + () ; outputs + () ; profile action (default) + ) + ; commit unit + (unit u-commit "Commit Unit" () + 1 1 ; issue done + () ; state + ((GRk INT -1) (FRk INT -1)) ; inputs + () ; outputs + () ; profile action (default) + ) +) + +; Tomcat machine. Early version of fr500 machine +(define-mach + (name tomcat) + (comment "Tomcat -- early version of fr500") + (cpu frvbf) +) +(define-model + (name tomcat) (comment "Tomcat model") (attrs) + (mach tomcat) + + (pipeline all "" () ((fetch) (decode) (execute) (writeback))) + + ; `state' is a list of variables for recording model state + ; (state) + + (unit u-exec "Execution Unit" () + 1 1 ; issue done + () ; state + () ; inputs + () ; outputs + () ; profile action (default) + ) +) + +; FR400 machine +(define-mach + (name fr400) + (comment "FR400 cpu") + (cpu frvbf) +) +(define-model + (name fr400) (comment "FR400 model") (attrs) + (mach fr400) + (pipeline all "" () ((fetch) (decode) (execute) (writeback))) + ; `state' is a list of variables for recording model state + (state + ; State items + ; These are all masks with each bit representing one register. + (prev-fp-load DI) ; Previous use of FR register was floating point load + (prev-fr-p4 DI) ; Previous use of FR register was media unit 4 + (prev-fr-p6 DI) ; Previous use of FR register was media unit 6 + (prev-acc-p2 DI) ; Previous use of ACC register was media unit 2 + (prev-acc-p4 DI) ; Previous use of ACC register was media unit 4 + (cur-fp-load DI) ; Current use of FR register is floating point load + (cur-fr-p4 DI) ; Current use of FR register is media unit 4 + (cur-fr-p6 DI) ; Current use of FR register is media unit 6 + (cur-acc-p2 DI) ; Current use of ACC register is media unit 2 + (cur-acc-p4 DI) ; Current use of ACC register is media unit 4 + ) + (unit u-exec "Execution Unit" () + 1 1 ; issue done + () ; state + () ; inputs + () ; outputs + () ; profile action (default) + ) + ; Basic integer insn unit + (unit u-integer "Integer Unit" () + 1 1 ; issue done + () ; state + ((GRi INT -1) (GRj INT -1)) ; inputs + ((GRk INT -1) (ICCi_1 INT -1)) ; outputs + () ; profile action (default) + ) + ; Integer multiplication unit + (unit u-imul "Integer Multiplication Unit" () + 1 1 ; issue done + () ; state + ((GRi INT -1) (GRj INT -1)) ; inputs + ((GRdoublek INT -1) (ICCi_1 INT -1)) ; outputs + () ; profile action (default) + ) + ; Integer division unit + (unit u-idiv "Integer Division Unit" () + 1 1 ; issue done + () ; state + ((GRi INT -1) (GRj INT -1)) ; inputs + ((GRk INT -1) (ICCi_1 INT -1)) ; outputs + () ; profile action (default) + ) + ; Branch unit + (unit u-branch "Branch Unit" () + 1 1 ; issue done + () ; state + ((GRi INT -1) (GRj INT -1) + (ICCi_2 INT -1) (FCCi_2 INT -1)) ; inputs + ((pc)) ; outputs + () ; profile action (default) + ) + ; Trap unit + (unit u-trap "Trap Unit" () + 1 1 ; issue done + () ; state + ((GRi INT -1) (GRj INT -1) + (ICCi_2 INT -1) (FCCi_2 INT -1)) ; inputs + () ; outputs + () ; profile action (default) + ) + ; Condition code check unit + (unit u-check "Check Unit" () + 1 1 ; issue done + () ; state + ((ICCi_3 INT -1) (FCCi_3 INT -1)) ; inputs + () ; outputs + () ; profile action (default) + ) + ; GR set half unit + (unit u-set-hilo "GR Set Half" () + 1 1 ; issue done + () ; state + () ; inputs + ((GRkhi INT -1) (GRklo INT -1)) ; outputs + () ; profile action (default) + ) + ; GR load unit -- TODO doesn't handle quad + (unit u-gr-load "GR Load Unit" () + 1 1 ; issue done + () ; state + ((GRi INT -1) (GRj INT -1)) ; inputs + ((GRk INT -1) (GRdoublek INT -1)) ; outputs + () ; profile action (default) + ) + ; GR store unit -- TODO doesn't handle quad + (unit u-gr-store "GR Store Unit" () + 1 1 ; issue done + () ; state + ((GRi INT -1) (GRj INT -1) (GRk INT -1) (GRdoublek INT -1)) ; inputs + () ; outputs + () ; profile action (default) + ) + ; FR load unit -- TODO doesn't handle quad + (unit u-fr-load "FR Load Unit" () + 1 1 ; issue done + () ; state + ((GRi INT -1) (GRj INT -1)) ; inputs + ((FRintk INT -1) (FRdoublek INT -1)) ; outputs + () ; profile action (default) + ) + ; FR store unit -- TODO doesn't handle quad + (unit u-fr-store "FR Store Unit" () + 1 1 ; issue done + () ; state + ((GRi INT -1) (GRj INT -1) (FRintk INT -1) (FRdoublek INT -1)) ; inputs + () ; outputs + () ; profile action (default) + ) + ; Swap unit + (unit u-swap "Swap Unit" () + 1 1 ; issue done + () ; state + ((GRi INT -1) (GRj INT -1)) ; inputs + ((GRk INT -1)) ; outputs + () ; profile action (default) + ) + ; FR Move to GR unit + (unit u-fr2gr "FR Move to GR Unit" () + 1 1 ; issue done + () ; state + ((FRintk INT -1)) ; inputs + ((GRj INT -1)) ; outputs + () ; profile action (default) + ) + ; SPR Move to GR unit + (unit u-spr2gr "SPR Move to GR Unit" () + 1 1 ; issue done + () ; state + ((spr INT -1)) ; inputs + ((GRj INT -1)) ; outputs + () ; profile action (default) + ) + ; GR Move to FR unit + (unit u-gr2fr "GR Move to FR Unit" () + 1 1 ; issue done + () ; state + ((GRj INT -1)) ; inputs + ((FRintk INT -1)) ; outputs + () ; profile action (default) + ) + ; GR Move to SPR unit + (unit u-gr2spr "GR Move to SPR Unit" () + 1 1 ; issue done + () ; state + ((GRj INT -1)) ; inputs + ((spr INT -1)) ; outputs + () ; profile action (default) + ) + ; Media unit M1 -- see table 13-8 in the fr400 LSI + (unit u-media-1 "Media-1 unit" () + 1 1 ; issue done + () ; state + ((FRinti INT -1) (FRintj INT -1)) ; inputs + ((FRintk INT -1)) ; outputs + () ; profile action (default) + ) + (unit u-media-1-quad "Media-1-quad unit" () + 1 1 ; issue done + () ; state + ((FRinti INT -1) (FRintj INT -1)) ; inputs + ((FRintk INT -1)) ; outputs + () ; profile action (default) + ) + (unit u-media-hilo "Media-hilo unit -- a variation of the Media-1 unit" () + 1 1 ; issue done + () ; state + () ; inputs + ((FRkhi INT -1) (FRklo INT -1)) ; outputs + () ; profile action (default) + ) + ; Media unit M2 -- see table 13-8 in the fr400 LSI + (unit u-media-2 "Media-2 unit" () + 1 1 ; issue done + () ; state + ((FRinti INT -1) (FRintj INT -1)) ; inputs + ((ACC40Sk INT -1) (ACC40Uk INT -1)) ; outputs + () ; profile action (default) + ) + (unit u-media-2-quad "Media-2-quad unit" () + 1 1 ; issue done + () ; state + ((FRinti INT -1) (FRintj INT -1)) ; inputs + ((ACC40Sk INT -1) (ACC40Uk INT -1)) ; outputs + () ; profile action (default) + ) + (unit u-media-2-acc "Media-2-acc unit" () + 1 1 ; issue done + () ; state + ((ACC40Si INT -1)) ; inputs + ((ACC40Sk INT -1)) ; outputs + () ; profile action (default) + ) + (unit u-media-2-acc-dual "Media-2-acc-dual unit" () + 1 1 ; issue done + () ; state + ((ACC40Si INT -1)) ; inputs + ((ACC40Sk INT -1)) ; outputs + () ; profile action (default) + ) + (unit u-media-2-add-sub "Media-2-add-sub unit" () + 1 1 ; issue done + () ; state + ((ACC40Si INT -1)) ; inputs + ((ACC40Sk INT -1)) ; outputs + () ; profile action (default) + ) + (unit u-media-2-add-sub-dual "Media-2-add-sub-dual unit" () + 1 1 ; issue done + () ; state + ((ACC40Si INT -1)) ; inputs + ((ACC40Sk INT -1)) ; outputs + () ; profile action (default) + ) + ; Media unit M3 -- see table 13-8 in the fr400 LSI + (unit u-media-3 "Media-3 unit" () + 1 1 ; issue done + () ; state + ((FRinti INT -1) (FRintj INT -1)) ; inputs + ((FRintk INT -1)) ; outputs + () ; profile action (default) + ) + (unit u-media-3-dual "Media-3-dual unit" () + 1 1 ; issue done + () ; state + ((FRinti INT -1)) ; inputs + ((FRintk INT -1)) ; outputs + () ; profile action (default) + ) + (unit u-media-3-quad "Media-3-quad unit" () + 1 1 ; issue done + () ; state + ((FRinti INT -1) (FRintj INT -1)) ; inputs + ((FRintk INT -1)) ; outputs + () ; profile action (default) + ) + ; Media unit M4 -- see table 13-8 in the fr400 LSI + (unit u-media-4 "Media-4 unit" () + 1 1 ; issue done + () ; state + ((ACC40Si INT -1) (FRintj INT -1)) ; inputs + ((ACC40Sk INT -1) (FRintk INT -1)) ; outputs + () ; profile action (default) + ) + (unit u-media-4-accg "Media-4-accg unit" () + 1 1 ; issue done + () ; state + ((ACCGi INT -1) (FRinti INT -1)) ; inputs + ((ACCGk INT -1) (FRintk INT -1)) ; outputs + () ; profile action (default) + ) + (unit u-media-4-acc-dual "Media-4-acc-dual unit" () + 1 1 ; issue done + () ; state + ((ACC40Si INT -1)) ; inputs + ((FRintk INT -1)) ; outputs + () ; profile action (default) + ) + ; Media unit M6 -- see table 13-8 in the fr400 LSI + (unit u-media-6 "Media-6 unit" () + 1 1 ; issue done + () ; state + ((FRinti INT -1)) ; inputs + ((FRintk INT -1)) ; outputs + () ; profile action (default) + ) + ; Media unit M7 -- see table 13-8 in the fr400 LSI + (unit u-media-7 "Media-1 unit" () + 1 1 ; issue done + () ; state + ((FRinti INT -1) (FRintj INT -1)) ; inputs + ((FCCk INT -1)) ; outputs + () ; profile action (default) + ) + ; Media Dual Expand unit + (unit u-media-dual-expand "Media Dual Expand unit" () + 1 1 ; issue done + () ; state + ((FRinti INT -1)) ; inputs + ((FRintk INT -1)) ; outputs + () ; profile action (default) + ) + ; Media Dual half to byte unit + (unit u-media-dual-htob "Media Half to byte" () + 1 1 ; issue done + () ; state + ((FRintj INT -1)) ; inputs + ((FRintk INT -1)) ; outputs + () ; profile action (default) + ) + ; Barrier unit + (unit u-barrier "Barrier unit" () + 1 1 ; issue done + () ; state + () ; inputs + () ; outputs + () ; profile action (default) + ) + ; Memory Barrier unit + (unit u-membar "Memory Barrier unit" () + 1 1 ; issue done + () ; state + () ; inputs + () ; outputs + () ; profile action (default) + ) + ; Insn cache invalidate unit + (unit u-ici "Insn cache invalidate unit" () + 1 1 ; issue done + () ; state + ((GRi INT -1) (GRj INT -1)) ; inputs + () ; outputs + () ; profile action (default) + ) + ; Data cache invalidate unit + (unit u-dci "Data cache invalidate unit" () + 1 1 ; issue done + () ; state + ((GRi INT -1) (GRj INT -1)) ; inputs + () ; outputs + () ; profile action (default) + ) + ; Data cache flush unit + (unit u-dcf "Data cache flush unit" () + 1 1 ; issue done + () ; state + ((GRi INT -1) (GRj INT -1)) ; inputs + () ; outputs + () ; profile action (default) + ) + ; Insn cache preload unit + (unit u-icpl "Insn cache preload unit" () + 1 1 ; issue done + () ; state + ((GRi INT -1) (GRj INT -1)) ; inputs + () ; outputs + () ; profile action (default) + ) + ; Data cache preload unit + (unit u-dcpl "Data cache preload unit" () + 1 1 ; issue done + () ; state + ((GRi INT -1) (GRj INT -1)) ; inputs + () ; outputs + () ; profile action (default) + ) + ; Insn cache unlock unit + (unit u-icul "Insn cache unlock unit" () + 1 1 ; issue done + () ; state + ((GRi INT -1) (GRj INT -1)) ; inputs + () ; outputs + () ; profile action (default) + ) + ; Data cache unlock unit + (unit u-dcul "Data cache unlock unit" () + 1 1 ; issue done + () ; state + ((GRi INT -1) (GRj INT -1)) ; inputs + () ; outputs + () ; profile action (default) + ) +) + +; Simple machine - single issue integer machine +(define-mach + (name simple) + (comment "Simple single issue integer cpu") + (cpu frvbf) +) +(define-model + (name simple) (comment "Simple model") (attrs) + (mach simple) + (pipeline all "" () ((fetch) (decode) (execute) (writeback))) + ; `state' is a list of variables for recording model state + (state) + (unit u-exec "Execution Unit" () + 1 1 ; issue done + () ; state + () ; inputs + () ; outputs + () ; profile action (default) + ) +) + +; The instruction fetch/execute cycle. +; +; This is how to fetch and decode an instruction. +; Leave it out for now + +; (define-extract (const SI 0)) + +; This is how to execute a decoded instruction. +; Leave it out for now + +; (define-execute (const SI 0)) + +; An attribute to describe which unit an insn runs in. +(define-attr + (for insn) + (type enum) + (name UNIT) + (comment "parallel execution pipeline selection") + ; The order of declaration is significant. + ; See the *_unit_mapping tables in frv.opc + ; Keep variations on the same unit together. + ; Keep the '01' variant immediately after the '1' variant in each unit. + ; Keep the 'ALL' variations immediately after the last numbered variant in each unit. + (values NIL + I0 I1 I01 I2 I3 IALL + FM0 FM1 FM01 FM2 FM3 FMALL FMLOW + B0 B1 B01 + C + MULT-DIV ; multiply/division slotted differently on different machines + LOAD ; loads slotted differently on different machines + STORE ; store slotted differently on different machines + SCAN ; scan, scani slotted differently on different machines + DCPL ; dcpl slotted differently on different machines + MDUALACC ; media dual acc slotted differently on different machines + MCLRACC-1; mclracc A==1 slotted differently on different machines + NUM_UNITS + ) +) +; Attributes to describe major categories of insns +(define-attr + (for insn) + (type enum) + (name FR400-MAJOR) + (comment "fr400 major insn categories") + ; The order of declaration is significant. Keep variations on the same major + ; together. + (values NONE + I-1 I-2 I-3 I-4 I-5 + B-1 B-2 B-3 B-4 B-5 B-6 + C-1 C-2 + M-1 M-2 + ) +) +(define-attr + (for insn) + (type enum) + (name FR500-MAJOR) + (comment "fr500 major insn categories") + ; The order of declaration is significant. Keep variations on the same major + ; together. + (values NONE + I-1 I-2 I-3 I-4 I-5 I-6 + B-1 B-2 B-3 B-4 B-5 B-6 + C-1 C-2 + F-1 F-2 F-3 F-4 F-5 F-6 F-7 F-8 + M-1 M-2 M-3 M-4 M-5 M-6 M-7 M-8 + ) +) +(define-attr + (for insn) + (type enum) + (name FR550-MAJOR) + (comment "fr550 major insn categories") + ; The order of declaration is significant. Keep variations on the same major + ; together. + (values NONE + I-1 I-2 I-3 I-4 I-5 I-6 I-7 I-8 + B-1 B-2 B-3 B-4 B-5 B-6 + C-1 C-2 + F-1 F-2 F-3 F-4 + M-1 M-2 M-3 M-4 M-5 + ) +) +; Privileged insn +(define-attr + (for insn) + (type boolean) + (name PRIVILEGED) + (comment "insn only allowed in supervisor mode") +) +; Non-Excepting insn +(define-attr + (for insn) + (type boolean) + (name NON-EXCEPTING) + (comment "non-excepting insn") +) +; Conditional insn +(define-attr + (for insn) + (type boolean) + (name CONDITIONAL) + (comment "conditional insn") +) +; insn accesses FR registers +(define-attr + (for insn) + (type boolean) + (name FR-ACCESS) + (comment "insn accesses FR registers") +) +; insn preserves MSR.OVF +(define-attr + (for insn) + (type boolean) + (name PRESERVE-OVF) + (comment "Preserve value of MSR.OVF") +) +; null attribute -- used as a place holder for where an attribue is required. +(define-attr + (for insn) + (type boolean) + (name NA) + (comment "placeholder attribute") + (attrs META) ; do not define in any generated file for now +) + +; IDOC attribute for instruction documentation. + +(define-attr + (for insn) + (type enum) + (name IDOC) + (comment "insn kind for documentation") + (attrs META) + (values + (MEM - () "Memory") + (ALU - () "ALU") + (FPU - () "FPU") + (BR - () "Branch") + (PRIV - () "Priviledged") + (MISC - () "Miscellaneous") + ) +) + +; Instruction fields. +; +; Attributes: +; PCREL-ADDR: pc relative value (for reloc and disassembly purposes) +; ABS-ADDR: absolute address (for reloc and disassembly purposes?) +; RESERVED: bits are not used to decode insn, must be all 0 +(dnf f-pack "packing bit" () 31 1) +(dnf f-op "primary opcode" () 24 7) +(dnf f-ope1 "extended opcode" () 11 6) +(dnf f-ope2 "extended opcode" () 9 4) +(dnf f-ope3 "extended opcode" () 15 3) +(dnf f-ope4 "extended opcode" () 7 2) + +(dnf f-GRi "source register 1" () 17 6) +(dnf f-GRj "source register 2" () 5 6) +(dnf f-GRk "destination register" () 30 6) + +(dnf f-FRi "source register 1" () 17 6) +(dnf f-FRj "source register 2" () 5 6) +(dnf f-FRk "destination register" () 30 6) + +(dnf f-CPRi "source register 1" () 17 6) +(dnf f-CPRj "source register 2" () 5 6) +(dnf f-CPRk "destination register" () 30 6) + +(dnf f-ACCGi "source register" () 17 6) +(dnf f-ACCGk "destination register" () 30 6) + +(dnf f-ACC40Si "40 bit signed accumulator" () 17 6) +(dnf f-ACC40Ui "40 bit unsigned accumulator" () 17 6) +(dnf f-ACC40Sk "40 bit accumulator" () 30 6) +(dnf f-ACC40Uk "40 bit accumulator" () 30 6) + +(dnf f-CRi "source register" () 14 3) +(dnf f-CRj "source register" () 2 3) +(dnf f-CRk "destination register" () 27 3) +(dnf f-CCi "condition register" () 11 3) + +(df f-CRj_int "target cr for ck insns" () 26 2 UINT + ((value pc) (sub WI value 4)) + ((value pc) (add WI value 4)) +) +(dnf f-CRj_float "target cr for fck insns" () 26 2) + +(dnf f-ICCi_1 "condition register" () 11 2) +(dnf f-ICCi_2 "condition register" () 26 2) +(dnf f-ICCi_3 "condition register" () 1 2) +(dnf f-FCCi_1 "condition register" () 11 2) +(dnf f-FCCi_2 "condition register" () 26 2) +(dnf f-FCCi_3 "condition register" () 1 2) +(dnf f-FCCk "condition register" () 26 2) +(dnf f-eir "exception insn register" () 17 6) + +(df f-s10 "10 bit sign extended" () 9 10 INT #f #f) +(df f-s12 "12 bit sign extended" () 11 12 INT #f #f) +(df f-d12 "12 bit sign extended" () 11 12 INT #f #f) +(df f-u16 "16 bit unsigned" () 15 16 UINT #f #f) +(df f-s16 "16 bit sign extended" () 15 16 INT #f #f) +(df f-s6 "6 bit signed" () 5 6 INT #f #f) +(df f-s6_1 "6 bit signed" () 11 6 INT #f #f) +(df f-u6 "6 bit unsigned" () 5 6 UINT #f #f) +(df f-s5 "5 bit signed" () 4 5 INT #f #f) + +(df f-u12-h "upper 6 bits of u12" () 17 6 INT #f #f) +(df f-u12-l "lower 6 bits of u12" () 5 6 UINT #f #f) +(dnmf f-u12 "12 bit signed immediate" () INT + (f-u12-h f-u12-l) + (sequence () ; insert + (set (ifield f-u12-h) (sra SI (ifield f-u12) 6)) + (set (ifield f-u12-l) (and (ifield f-u12) #x3f)) + ) + (sequence () ; extract + (set (ifield f-u12) (or (sll (ifield f-u12-h) 6) + (ifield f-u12-l))) + ) +) + +(dnf f-int-cc "integer branch conditions" () 30 4) +(dnf f-flt-cc "floating branch conditions" () 30 4) +(df f-cond "conditional arithmetic" () 8 1 UINT #f #f) +(df f-ccond "lr branch condition" () 12 1 UINT #f #f) +(df f-hint "2 bit branch prediction hint" () 17 2 UINT #f #f) +(df f-LI "link indicator" () 25 1 UINT #f #f) +(df f-lock "cache lock indicator" () 25 1 UINT #f #f) +(df f-debug "debug mode indicator" () 25 1 UINT #f #f) +(df f-A "all accumulator bit" () 17 1 UINT #f #f) +(df f-ae "cache all entries indicator" () 25 1 UINT #f #f) + +(dnf f-spr-h "upper 6 bits of spr" () 30 6) +(dnf f-spr-l "lower 6 bits of spr" () 17 6) +(dnmf f-spr "special purpose register" () UINT + (f-spr-h f-spr-l) + (sequence () ; insert + (set (ifield f-spr-h) (srl (ifield f-spr) (const 6))) + (set (ifield f-spr-l) (and (ifield f-spr) (const #x3f))) + ) + (sequence () ; extract + (set (ifield f-spr) (or (sll (ifield f-spr-h) (const 6)) + (ifield f-spr-l))) + ) +) + +(df f-label16 "18 bit pc relative signed offset" (PCREL-ADDR) 15 16 INT + ((value pc) (sra WI (sub WI value pc) (const 2))) + ((value pc) (add WI (sll WI value (const 2)) pc)) +) + +(df f-labelH6 "upper 6 bits of label24" () 30 6 INT #f #f) +(dnf f-labelL18 "lower 18 bits of label24" () 17 18) +(dnmf f-label24 "26 bit signed offset" (PCREL-ADDR) INT + (f-labelH6 f-labelL18) + ; insert + (sequence () + (set (ifield f-labelH6) + (sra WI (sub (ifield f-label24) pc) (const 20))) + (set (ifield f-labelL18) + (and (srl (sub (ifield f-label24) pc) (const 2)) + (const #x3ffff))) + ) + ; extract + (sequence () + (set (ifield f-label24) + (add (sll (or (sll (ifield f-labelH6) (const 18)) + (ifield f-labelL18)) + (const 2)) + pc))) +) + +(dnf f-ICCi_1-null "null field" (RESERVED) 11 2) +(dnf f-ICCi_2-null "null field" (RESERVED) 26 2) +(dnf f-ICCi_3-null "null field" (RESERVED) 1 2) +(dnf f-FCCi_1-null "null field" (RESERVED) 11 2) +(dnf f-FCCi_2-null "null field" (RESERVED) 26 2) +(dnf f-FCCi_3-null "null field" (RESERVED) 1 2) +(dnf f-rs-null "null field" (RESERVED) 17 6) +(dnf f-GRi-null "null field" (RESERVED) 17 6) +(dnf f-GRj-null "null field" (RESERVED) 5 6) +(dnf f-GRk-null "null field" (RESERVED) 30 6) +(dnf f-FRi-null "null field" (RESERVED) 17 6) +(dnf f-FRj-null "null field" (RESERVED) 5 6) +(dnf f-ACCj-null "null field" (RESERVED) 5 6) +(dnf f-rd-null "null field" (RESERVED) 30 6) +(dnf f-cond-null "null field" (RESERVED) 30 4) +(dnf f-ccond-null "null field" (RESERVED) 12 1) +(dnf f-s12-null "null field" (RESERVED) 11 12) +(dnf f-label16-null "null field" (RESERVED) 15 16) +(dnf f-misc-null-1 "null field" (RESERVED) 30 5) +(dnf f-misc-null-2 "null field" (RESERVED) 11 6) +(dnf f-misc-null-3 "null field" (RESERVED) 11 4) +(dnf f-misc-null-4 "null field" (RESERVED) 17 2) +(dnf f-misc-null-5 "null field" (RESERVED) 17 16) +(dnf f-misc-null-6 "null field" (RESERVED) 30 3) +(dnf f-misc-null-7 "null field" (RESERVED) 17 3) +(dnf f-misc-null-8 "null field" (RESERVED) 5 3) +(dnf f-misc-null-9 "null field" (RESERVED) 5 4) +(dnf f-misc-null-10 "null field" (RESERVED) 16 5) +(dnf f-misc-null-11 "null field" (RESERVED) 5 1) + +(dnf f-LI-off "null field" (RESERVED) 25 1) +(dnf f-LI-on "null field" (RESERVED) 25 1) + +; Enums. + +; insn-op: +; FIXME: should use die macro or some such +(define-normal-insn-enum insn-op "insn op enums" () OP_ f-op + ( + "00" "01" "02" "03" "04" "05" "06" "07" "08" "09" "0A" "0B" "0C" "0D" "0E" "0F" + "10" "11" "12" "13" "14" "15" "16" "17" "18" "19" "1A" "1B" "1C" "1D" "1E" "1F" + "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "2A" "2B" "2C" "2D" "2E" "2F" + "30" "31" "32" "33" "34" "35" "36" "37" "38" "39" "3A" "3B" "3C" "3D" "3E" "3F" + "40" "41" "42" "43" "44" "45" "46" "47" "48" "49" "4A" "4B" "4C" "4D" "4E" "4F" + "50" "51" "52" "53" "54" "55" "56" "57" "58" "59" "5A" "5B" "5C" "5D" "5E" "5F" + "60" "61" "62" "63" "64" "65" "66" "67" "68" "69" "6A" "6B" "6C" "6D" "6E" "6F" + "70" "71" "72" "73" "74" "75" "76" "77" "78" "79" "7A" "7B" "7C" "7D" "7E" "7F" + ) +) + +(define-normal-insn-enum insn-ope1 "insn ope enums" () OPE1_ f-ope1 + ( + "00" "01" "02" "03" "04" "05" "06" "07" "08" "09" "0A" "0B" "0C" "0D" "0E" "0F" + "10" "11" "12" "13" "14" "15" "16" "17" "18" "19" "1A" "1B" "1C" "1D" "1E" "1F" + "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "2A" "2B" "2C" "2D" "2E" "2F" + "30" "31" "32" "33" "34" "35" "36" "37" "38" "39" "3A" "3B" "3C" "3D" "3E" "3F" + ) +) + +(define-normal-insn-enum insn-ope2 "insn ope enums" () OPE2_ f-ope2 + ( + "00" "01" "02" "03" "04" "05" "06" "07" "08" "09" "0A" "0B" "0C" "0D" "0E" "0F" + ) +) + +(define-normal-insn-enum insn-ope3 "insn ope enums" () OPE3_ f-ope3 + ( + "00" "01" "02" "03" "04" "05" "06" "07" + ) +) + +(define-normal-insn-enum insn-ope4 "insn ope enums" () OPE4_ f-ope4 + ( + "0" "1" "2" "3" + ) +) + +; int-cc: integer branch conditions +; FIXME: should use die macro or some such +(define-normal-insn-enum int-cc "integer branch cond enums" () ICC_ f-int-cc + ( + "nev" "c" "v" "lt" "eq" "ls" "n" "le" + "ra" "nc" "nv" "ge" "ne" "hi" "p" "gt" + ) +) + +; flt-cc: floating-point/media branch conditions +; FIXME: should use die macro or some such +(define-normal-insn-enum flt-cc "float branch cond enums" () FCC_ f-flt-cc + ("nev" "u" "gt" "ug" "lt" "ul" "lg" "ne" + "eq" "ue" "ge" "uge" "le" "ule" "o" "ra") +) + +; Hardware pieces. +; These entries list the elements of the raw hardware. +; They're also used to provide tables and other elements of the assembly +; language. +(dnh h-pc "program counter" (PC PROFILE) (pc) () () ()) + +; The PSR. The individual fields are referenced more than the entire +; register, so reference them directly. We can assemble the +; entire register contents when necessary. +; +(dsh h-psr_imple "PSR.IMPLE" () (register UQI)) +(dsh h-psr_ver "PSR.VER" () (register UQI)) +(dsh h-psr_ice "PSR.ICE bit" () (register BI)) +(dsh h-psr_nem "PSR.NEM bit" () (register BI)) +(dsh h-psr_cm "PSR.CM bit" () (register BI)) +(dsh h-psr_be "PSR.BE bit" () (register BI)) +(dsh h-psr_esr "PSR.ESR bit" () (register BI)) +(dsh h-psr_ef "PSR.EF bit" () (register BI)) +(dsh h-psr_em "PSR.EM bit" () (register BI)) +(dsh h-psr_pil "PSR.PIL " () (register UQI)) +(dsh h-psr_ps "PSR.PS bit" () (register BI)) +(dsh h-psr_et "PSR.ET bit" () (register BI)) + +; PSR.S requires special handling because the shadow registers (SR0-SR4) must +; be switched with GR4-GR7 when changing from user to supervisor mode or +; vice-versa. +(define-hardware + (name h-psr_s) + (comment "PSR.S bit") + (attrs) + (type register BI) + (get) + (set (newval) (c-call VOID "@cpu@_h_psr_s_set_handler" newval)) +) + +; The TBR. The individual bits are referenced more than the entire +; register, so reference them directly. We can assemble the +; entire register contents when necessary. +; +(dsh h-tbr_tba "TBR.TBA" () (register UWI)) +(dsh h-tbr_tt "TBR.TT" () (register UQI)) + +; The BPSR. The individual bits are referenced more than the entire +; register, so reference them directly. We can assemble the +; entire register contents when necessary. +; +(dsh h-bpsr_bs "PSR.S bit" () (register BI)) +(dsh h-bpsr_bet "PSR.ET bit" () (register BI)) + +; General registers +; +(define-keyword + (name gr-names) + (print-name h-gr) + (prefix "") + (values + (sp 1) (fp 2) + (gr0 0)(gr1 1)(gr2 2)(gr3 3)(gr4 4)(gr5 5)(gr6 6)(gr7 7) + (gr8 8)(gr9 9)(gr10 10)(gr11 11)(gr12 12)(gr13 13)(gr14 14)(gr15 15) + (gr16 16)(gr17 17)(gr18 18)(gr19 19)(gr20 20)(gr21 21)(gr22 22)(gr23 23) + (gr24 24)(gr25 25)(gr26 26)(gr27 27)(gr28 28)(gr29 29)(gr30 30)(gr31 31) + (gr32 32)(gr33 33)(gr34 34)(gr35 35)(gr36 36)(gr37 37)(gr38 38)(gr39 39) + (gr40 40)(gr41 41)(gr42 42)(gr43 43)(gr44 44)(gr45 45)(gr46 46)(gr47 47) + (gr48 48)(gr49 49)(gr50 50)(gr51 51)(gr52 52)(gr53 53)(gr54 54)(gr55 55) + (gr56 56)(gr57 57)(gr58 58)(gr59 59)(gr60 60)(gr61 61)(gr62 62)(gr63 63) + ) +) + +(define-hardware + (name h-gr) + (comment "general registers") + (attrs PROFILE) + (type register USI (64)) + (indices extern-keyword gr-names) + (get (index) (c-call WI "@cpu@_h_gr_get_handler" index)) + (set (index newval) (c-call VOID "@cpu@_h_gr_set_handler" index newval)) +) + +; General Registers as double words +; These registers are shadowed onto h-gr +(define-hardware + (name h-gr_double) + (comment "general registers as double words") + (attrs PROFILE VIRTUAL) + (type register DI (32)) + ; FIXME: Need constraint to prohibit odd numbers. + (indices extern-keyword gr-names) + (get (index) + (c-call DI "@cpu@_h_gr_double_get_handler" index)) + (set (index newval) + (c-call VOID "@cpu@_h_gr_double_set_handler" index newval)) +) + +; General Registers as high and low half words +; These registers are shadowed onto h-gr +(define-hardware + (name h-gr_hi) + (comment "general registers as high half word") + (attrs PROFILE VIRTUAL) + (type register UHI (64)) + (indices extern-keyword gr-names) + (get (index) (c-call UHI "@cpu@_h_gr_hi_get_handler" index)) + (set (index newval) (c-call VOID "@cpu@_h_gr_hi_set_handler" index newval)) +) +(define-hardware + (name h-gr_lo) + (comment "general registers as low half word") + (attrs PROFILE VIRTUAL) + (type register UHI (64)) + (indices extern-keyword gr-names) + (get (index) (c-call UHI "@cpu@_h_gr_lo_get_handler" index)) + (set (index newval) (c-call VOID "@cpu@_h_gr_lo_set_handler" index newval)) +) + +; Floating Point Registers +(define-keyword + (name fr-names) + (print-name h-fr) + (prefix "") + (values + (fr0 0)(fr1 1)(fr2 2)(fr3 3)(fr4 4)(fr5 5)(fr6 6)(fr7 7) + (fr8 8)(fr9 9)(fr10 10)(fr11 11)(fr12 12)(fr13 13)(fr14 14)(fr15 15) + (fr16 16)(fr17 17)(fr18 18)(fr19 19)(fr20 20)(fr21 21)(fr22 22)(fr23 23) + (fr24 24)(fr25 25)(fr26 26)(fr27 27)(fr28 28)(fr29 29)(fr30 30)(fr31 31) + (fr32 32)(fr33 33)(fr34 34)(fr35 35)(fr36 36)(fr37 37)(fr38 38)(fr39 39) + (fr40 40)(fr41 41)(fr42 42)(fr43 43)(fr44 44)(fr45 45)(fr46 46)(fr47 47) + (fr48 48)(fr49 49)(fr50 50)(fr51 51)(fr52 52)(fr53 53)(fr54 54)(fr55 55) + (fr56 56)(fr57 57)(fr58 58)(fr59 59)(fr60 60)(fr61 61)(fr62 62)(fr63 63) + ) +) + +(define-hardware + (name h-fr) + (comment "floating point registers") + (attrs PROFILE) + (type register SF (64)) + (indices extern-keyword fr-names) + (get (index) (c-call SF "@cpu@_h_fr_get_handler" index)) + (set (index newval) (c-call VOID "@cpu@_h_fr_set_handler" index newval)) +) + +; Floating Point Registers as double precision +; These registers are shadowed onto h-fr + +(define-hardware + (name h-fr_double) + (comment "floating point registers as double precision") + (attrs PROFILE VIRTUAL) + (type register DF (32)) + ; FIXME: Need constraint to prohibit odd numbers. + (indices extern-keyword fr-names) + (get (index) + (c-call DF "@cpu@_h_fr_double_get_handler" index)) + (set (index newval) + (c-call VOID "@cpu@_h_fr_double_set_handler" index newval)) +) + +; Floating Point Registers as integer words. +; These registers are shadowed onto h-fr + +(define-hardware + (name h-fr_int) + (comment "floating point registers as integers") + (attrs PROFILE VIRTUAL) + (type register USI (64)) + (indices extern-keyword fr-names) + (get (index) + (c-call USI "@cpu@_h_fr_int_get_handler" index)) + (set (index newval) + (c-call VOID "@cpu@_h_fr_int_set_handler" index newval)) +) + +; Floating Point Registers as high and low half words +; These registers are shadowed onto h-fr +(define-hardware + (name h-fr_hi) + (comment "floating point registers as unsigned high half word") + (attrs PROFILE VIRTUAL) + (type register UHI (64)) + (indices extern-keyword fr-names) + (get (regno) (srl (reg h-fr_int regno) 16)) + (set (regno newval) (set (reg h-fr_int regno) + (or (and (reg h-fr_int regno) #xffff) + (sll newval 16)))) +) +(define-hardware + (name h-fr_lo) + (comment "floating point registers as unsigned low half word") + (attrs PROFILE VIRTUAL) + (type register UHI (64)) + (indices extern-keyword fr-names) + (get (regno) (and (reg h-fr_int regno) #xffff)) + (set (regno newval) (set (reg h-fr_int regno) + (or (and (reg h-fr_int regno) #xffff0000) + (and newval #xffff)))) +) + +; Floating Point Registers as unsigned bytes +; These registers are shadowed onto h-fr +(define-hardware + (name h-fr_0) + (comment "floating point registers as unsigned byte 0") + (attrs PROFILE VIRTUAL) + (type register UHI (64)) + (indices extern-keyword fr-names) + (get (regno) (and (reg h-fr_int regno) #xff)) + (set (regno newval) + (sequence () + (if (gt USI newval #xff) + (set newval #xff)) + (set (reg h-fr_int regno) (or (and (reg h-fr_int regno) #xffffff00) + newval)))) +) +(define-hardware + (name h-fr_1) + (comment "floating point registers as unsigned byte 1") + (attrs PROFILE VIRTUAL) + (type register UHI (64)) + (indices extern-keyword fr-names) + (get (regno) (and (srl (reg h-fr_int regno) 8) #xff)) + (set (regno newval) + (sequence () + (if (gt USI newval #xff) + (set newval #xff)) + (set (reg h-fr_int regno) (or (and (reg h-fr_int regno) #xffff00ff) + (sll newval 8))))) +) +(define-hardware + (name h-fr_2) + (comment "floating point registers as unsigned byte 2") + (attrs PROFILE VIRTUAL) + (type register UHI (64)) + (indices extern-keyword fr-names) + (get (regno) (and (srl (reg h-fr_int regno) 16) #xff)) + (set (regno newval) + (sequence () + (if (gt USI newval #xff) + (set newval #xff)) + (set (reg h-fr_int regno) (or (and (reg h-fr_int regno) #xff00ffff) + (sll newval 16))))) +) +(define-hardware + (name h-fr_3) + (comment "floating point registers as unsigned byte 3") + (attrs PROFILE VIRTUAL) + (type register UHI (64)) + (indices extern-keyword fr-names) + (get (regno) (and (srl (reg h-fr_int regno) 24) #xff)) + (set (regno newval) + (sequence () + (if (gt USI newval #xff) + (set newval #xff)) + (set (reg h-fr_int regno) (or (and (reg h-fr_int regno) #x00ffffff) + (sll newval 24))))) +) +; Coprocessor Registers +; +(define-keyword + (name cpr-names) + (print-name h-cpr) + (prefix "") + (values +(cpr0 0)(cpr1 1)(cpr2 2)(cpr3 3)(cpr4 4)(cpr5 5)(cpr6 6)(cpr7 7) +(cpr8 8)(cpr9 9)(cpr10 10)(cpr11 11)(cpr12 12)(cpr13 13)(cpr14 14)(cpr15 15) +(cpr16 16)(cpr17 17)(cpr18 18)(cpr19 19)(cpr20 20)(cpr21 21)(cpr22 22)(cpr23 23) +(cpr24 24)(cpr25 25)(cpr26 26)(cpr27 27)(cpr28 28)(cpr29 29)(cpr30 30)(cpr31 31) +(cpr32 32)(cpr33 33)(cpr34 34)(cpr35 35)(cpr36 36)(cpr37 37)(cpr38 38)(cpr39 39) +(cpr40 40)(cpr41 41)(cpr42 42)(cpr43 43)(cpr44 44)(cpr45 45)(cpr46 46)(cpr47 47) +(cpr48 48)(cpr49 49)(cpr50 50)(cpr51 51)(cpr52 52)(cpr53 53)(cpr54 54)(cpr55 55) +(cpr56 56)(cpr57 57)(cpr58 58)(cpr59 59)(cpr60 60)(cpr61 61)(cpr62 62)(cpr63 63) + ) +) + +(define-hardware + (name h-cpr) + (comment "coprocessor registers") + (attrs PROFILE (MACH frv)) + (type register WI (64)) + (indices extern-keyword cpr-names) +) + +; Coprocessor Registers as double words +; These registers are shadowed onto h-cpr +(define-hardware + (name h-cpr_double) + (comment "coprocessor registers as double words") + (attrs PROFILE VIRTUAL (MACH frv)) + (type register DI (32)) + ; FIXME: Need constraint to prohibit odd numbers. + (indices extern-keyword cpr-names) + (get (index) + (c-call DI "@cpu@_h_cpr_double_get_handler" index)) + (set (index newval) + (c-call VOID "@cpu@_h_cpr_double_set_handler" index newval)) +) + +; Special Purpose Registers +; +(define-keyword + (name spr-names) + (print-name h-spr) + (prefix "") + (values + (psr 0) (pcsr 1) (bpcsr 2) (tbr 3) (bpsr 4) + + (hsr0 16) (hsr1 17) (hsr2 18) (hsr3 19) + (hsr4 20) (hsr5 21) (hsr6 22) (hsr7 23) + (hsr8 24) (hsr9 25) (hsr10 26) (hsr11 27) + (hsr12 28) (hsr13 29) (hsr14 30) (hsr15 31) + (hsr16 32) (hsr17 33) (hsr18 34) (hsr19 35) + (hsr20 36) (hsr21 37) (hsr22 38) (hsr23 39) + (hsr24 40) (hsr25 41) (hsr26 42) (hsr27 43) + (hsr28 44) (hsr29 45) (hsr30 46) (hsr31 47) + (hsr32 48) (hsr33 49) (hsr34 50) (hsr35 51) + (hsr36 52) (hsr37 53) (hsr38 54) (hsr39 55) + (hsr40 56) (hsr41 57) (hsr42 58) (hsr43 59) + (hsr44 60) (hsr45 61) (hsr46 62) (hsr47 63) + (hsr48 64) (hsr49 65) (hsr50 66) (hsr51 67) + (hsr52 68) (hsr53 69) (hsr54 70) (hsr55 71) + (hsr56 72) (hsr57 73) (hsr58 74) (hsr59 75) + (hsr60 76) (hsr61 77) (hsr62 78) (hsr63 79) + + (ccr 256) (cccr 263) (lr 272) (lcr 273) (iacc0h 280) (iacc0l 281) (isr 288) + + (neear0 352) (neear1 353) (neear2 354) (neear3 355) + (neear4 356) (neear5 357) (neear6 358) (neear7 359) + (neear8 360) (neear9 361) (neear10 362) (neear11 363) + (neear12 364) (neear13 365) (neear14 366) (neear15 367) + (neear16 368) (neear17 369) (neear18 370) (neear19 371) + (neear20 372) (neear21 373) (neear22 374) (neear23 375) + (neear24 376) (neear25 377) (neear26 378) (neear27 379) + (neear28 380) (neear29 381) (neear30 382) (neear31 383) + + (nesr0 384) (nesr1 385) (nesr2 386) (nesr3 387) + (nesr4 388) (nesr5 389) (nesr6 390) (nesr7 391) + (nesr8 392) (nesr9 393) (nesr10 394) (nesr11 395) + (nesr12 396) (nesr13 397) (nesr14 398) (nesr15 399) + (nesr16 400) (nesr17 401) (nesr18 402) (nesr19 403) + (nesr20 404) (nesr21 405) (nesr22 406) (nesr23 407) + (nesr24 408) (nesr25 409) (nesr26 410) (nesr27 411) + (nesr28 412) (nesr29 413) (nesr30 414) (nesr31 415) + + (necr 416) + + (gner0 432) (gner1 433) + + (fner0 434) (fner1 435) + + (epcr0 512) (epcr1 513) (epcr2 514) (epcr3 515) + (epcr4 516) (epcr5 517) (epcr6 518) (epcr7 519) + (epcr8 520) (epcr9 521) (epcr10 522) (epcr11 523) + (epcr12 524) (epcr13 525) (epcr14 526) (epcr15 527) + (epcr16 528) (epcr17 529) (epcr18 530) (epcr19 531) + (epcr20 532) (epcr21 533) (epcr22 534) (epcr23 535) + (epcr24 536) (epcr25 537) (epcr26 538) (epcr27 539) + (epcr28 540) (epcr29 541) (epcr30 542) (epcr31 543) + (epcr32 544) (epcr33 545) (epcr34 546) (epcr35 547) + (epcr36 548) (epcr37 549) (epcr38 550) (epcr39 551) + (epcr40 552) (epcr41 553) (epcr42 554) (epcr43 555) + (epcr44 556) (epcr45 557) (epcr46 558) (epcr47 559) + (epcr48 560) (epcr49 561) (epcr50 562) (epcr51 563) + (epcr52 564) (epcr53 565) (epcr54 566) (epcr55 567) + (epcr56 568) (epcr57 569) (epcr58 570) (epcr59 571) + (epcr60 572) (epcr61 573) (epcr62 574) (epcr63 575) + + (esr0 576) (esr1 577) (esr2 578) (esr3 579) + (esr4 580) (esr5 581) (esr6 582) (esr7 583) + (esr8 584) (esr9 585) (esr10 586) (esr11 587) + (esr12 588) (esr13 589) (esr14 590) (esr15 591) + (esr16 592) (esr17 593) (esr18 594) (esr19 595) + (esr20 596) (esr21 597) (esr22 598) (esr23 599) + (esr24 600) (esr25 601) (esr26 602) (esr27 603) + (esr28 604) (esr29 605) (esr30 606) (esr31 607) + (esr32 608) (esr33 609) (esr34 610) (esr35 611) + (esr36 612) (esr37 613) (esr38 614) (esr39 615) + (esr40 616) (esr41 617) (esr42 618) (esr43 619) + (esr44 620) (esr45 621) (esr46 622) (esr47 623) + (esr48 624) (esr49 625) (esr50 626) (esr51 627) + (esr52 628) (esr53 629) (esr54 630) (esr55 631) + (esr56 632) (esr57 633) (esr58 634) (esr59 635) + (esr60 636) (esr61 637) (esr62 638) (esr63 639) + + (eir0 640) (eir1 641) (eir2 642) (eir3 643) + (eir4 644) (eir5 645) (eir6 646) (eir7 647) + (eir8 648) (eir9 649) (eir10 650) (eir11 651) + (eir12 652) (eir13 653) (eir14 654) (eir15 655) + (eir16 656) (eir17 657) (eir18 658) (eir19 659) + (eir20 660) (eir21 661) (eir22 662) (eir23 663) + (eir24 664) (eir25 665) (eir26 666) (eir27 667) + (eir28 668) (eir29 669) (eir30 670) (eir31 671) + + (esfr0 672) (esfr1 673) + + (sr0 768) (sr1 769) (sr2 770) (sr3 771) + + (fsr0 1024) (fsr1 1025) (fsr2 1026) (fsr3 1027) + (fsr4 1028) (fsr5 1029) (fsr6 1030) (fsr7 1031) + (fsr8 1032) (fsr9 1033) (fsr10 1034) (fsr11 1035) + (fsr12 1036) (fsr13 1037) (fsr14 1038) (fsr15 1039) + (fsr16 1040) (fsr17 1041) (fsr18 1042) (fsr19 1043) + (fsr20 1044) (fsr21 1045) (fsr22 1046) (fsr23 1047) + (fsr24 1048) (fsr25 1049) (fsr26 1050) (fsr27 1051) + (fsr28 1052) (fsr29 1053) (fsr30 1054) (fsr31 1055) + (fsr32 1056) (fsr33 1057) (fsr34 1058) (fsr35 1059) + (fsr36 1060) (fsr37 1061) (fsr38 1062) (fsr39 1063) + (fsr40 1064) (fsr41 1065) (fsr42 1066) (fsr43 1067) + (fsr44 1068) (fsr45 1069) (fsr46 1070) (fsr47 1071) + (fsr48 1072) (fsr49 1073) (fsr50 1074) (fsr51 1075) + (fsr52 1076) (fsr53 1077) (fsr54 1078) (fsr55 1079) + (fsr56 1080) (fsr57 1081) (fsr58 1082) (fsr59 1083) + (fsr60 1084) (fsr61 1085) (fsr62 1086) (fsr63 1087) + + ; FQ0-FQ31 are 64 bit registers. + ; These names allow access to the upper 32 bits of the FQ registers. + (fqop0 1088) (fqop1 1090) (fqop2 1092) (fqop3 1094) + (fqop4 1096) (fqop5 1098) (fqop6 1100) (fqop7 1102) + (fqop8 1104) (fqop9 1106) (fqop10 1108) (fqop11 1110) + (fqop12 1112) (fqop13 1114) (fqop14 1116) (fqop15 1118) + (fqop16 1120) (fqop17 1122) (fqop18 1124) (fqop19 1126) + (fqop20 1128) (fqop21 1130) (fqop22 1132) (fqop23 1134) + (fqop24 1136) (fqop25 1138) (fqop26 1140) (fqop27 1142) + (fqop28 1144) (fqop29 1146) (fqop30 1148) (fqop31 1150) + ; These names allow access to the lower 32 bits of the FQ registers. + (fqst0 1089) (fqst1 1091) (fqst2 1093) (fqst3 1095) + (fqst4 1097) (fqst5 1099) (fqst6 1101) (fqst7 1103) + (fqst8 1105) (fqst9 1107) (fqst10 1109) (fqst11 1111) + (fqst12 1113) (fqst13 1115) (fqst14 1117) (fqst15 1119) + (fqst16 1121) (fqst17 1123) (fqst18 1125) (fqst19 1127) + (fqst20 1129) (fqst21 1131) (fqst22 1133) (fqst23 1135) + (fqst24 1137) (fqst25 1139) (fqst26 1141) (fqst27 1143) + (fqst28 1145) (fqst29 1147) (fqst30 1149) (fqst31 1151) + ; These also access the lower 32 bits of the FQ registers. + ; These are not accessible as spr registers (see LSI appendix - section 13.4) +; (fq0 1089) (fq1 1091) (fq2 1093) (fq3 1095) +; (fq4 1097) (fq5 1099) (fq6 1101) (fq7 1103) +; (fq8 1105) (fq9 1107) (fq10 1109) (fq11 1111) +; (fq12 1113) (fq13 1115) (fq14 1117) (fq15 1119) +; (fq16 1121) (fq17 1123) (fq18 1125) (fq19 1127) +; (fq20 1129) (fq21 1131) (fq22 1133) (fq23 1135) +; (fq24 1137) (fq25 1139) (fq26 1141) (fq27 1143) +; (fq28 1145) (fq29 1147) (fq30 1149) (fq31 1151) + + (mcilr0 1272) (mcilr1 1273) + + (msr0 1280) (msr1 1281) (msr2 1282) (msr3 1283) + (msr4 1284) (msr5 1285) (msr6 1286) (msr7 1287) + (msr8 1288) (msr9 1289) (msr10 1290) (msr11 1291) + (msr12 1292) (msr13 1293) (msr14 1294) (msr15 1295) + (msr16 1296) (msr17 1297) (msr18 1298) (msr19 1299) + (msr20 1300) (msr21 1301) (msr22 1302) (msr23 1303) + (msr24 1304) (msr25 1305) (msr26 1306) (msr27 1307) + (msr28 1308) (msr29 1309) (msr30 1310) (msr31 1311) + (msr32 1312) (msr33 1313) (msr34 1314) (msr35 1315) + (msr36 1316) (msr37 1317) (msr38 1318) (msr39 1319) + (msr40 1320) (msr41 1321) (msr42 1322) (msr43 1323) + (msr44 1324) (msr45 1325) (msr46 1326) (msr47 1327) + (msr48 1328) (msr49 1329) (msr50 1330) (msr51 1331) + (msr52 1332) (msr53 1333) (msr54 1334) (msr55 1335) + (msr56 1336) (msr57 1337) (msr58 1338) (msr59 1339) + (msr60 1340) (msr61 1341) (msr62 1342) (msr63 1343) + + ; MQ0-MQ31 are 64 bit registers. + ; These names allow access to the upper 32 bits of the MQ registers. + (mqop0 1344) (mqop1 1346) (mqop2 1348) (mqop3 1350) + (mqop4 1352) (mqop5 1354) (mqop6 1356) (mqop7 1358) + (mqop8 1360) (mqop9 1362) (mqop10 1364) (mqop11 1366) + (mqop12 1368) (mqop13 1370) (mqop14 1372) (mqop15 1374) + (mqop16 1376) (mqop17 1378) (mqop18 1380) (mqop19 1382) + (mqop20 1384) (mqop21 1386) (mqop22 1388) (mqop23 1390) + (mqop24 1392) (mqop25 1394) (mqop26 1396) (mqop27 1398) + (mqop28 1400) (mqop29 1402) (mqop30 1404) (mqop31 1406) + ; These names allow access to the lower 32 bits of the MQ registers. + (mqst0 1345) (mqst1 1347) (mqst2 1349) (mqst3 1351) + (mqst4 1353) (mqst5 1355) (mqst6 1357) (mqst7 1359) + (mqst8 1361) (mqst9 1363) (mqst10 1365) (mqst11 1367) + (mqst12 1369) (mqst13 1371) (mqst14 1373) (mqst15 1375) + (mqst16 1377) (mqst17 1379) (mqst18 1381) (mqst19 1383) + (mqst20 1385) (mqst21 1387) (mqst22 1389) (mqst23 1391) + (mqst24 1393) (mqst25 1395) (mqst26 1397) (mqst27 1399) + (mqst28 1401) (mqst29 1403) (mqst30 1405) (mqst31 1407) + ; These also access the lower 32 bits of the MQ registers. + ; These are not accessible as spr registers (see LSI appendix - section 13.4) +; (mq0 1345) (mq1 1347) (mq2 1349) (mq3 1351) +; (mq4 1353) (mq5 1355) (mq6 1357) (mq7 1359) +; (mq8 1361) (mq9 1363) (mq10 1365) (mq11 1367) +; (mq12 1369) (mq13 1371) (mq14 1373) (mq15 1375) +; (mq16 1377) (mq17 1379) (mq18 1381) (mq19 1383) +; (mq20 1385) (mq21 1387) (mq22 1389) (mq23 1391) +; (mq24 1393) (mq25 1395) (mq26 1397) (mq27 1399) +; (mq28 1401) (mq29 1403) (mq30 1405) (mq31 1407) + + ; These are not accessible as spr registers (see LSI appendix - section 13.4) +; (acc0 1408) (acc1 1409) (acc2 1410) (acc3 1411) +; (acc4 1412) (acc5 1413) (acc6 1414) (acc7 1415) +; (acc8 1416) (acc9 1417) (acc10 1418) (acc11 1419) +; (acc12 1420) (acc13 1421) (acc14 1422) (acc15 1423) +; (acc16 1424) (acc17 1425) (acc18 1426) (acc19 1427) +; (acc20 1428) (acc21 1429) (acc22 1430) (acc23 1431) +; (acc24 1432) (acc25 1433) (acc26 1434) (acc27 1435) +; (acc28 1436) (acc29 1437) (acc30 1438) (acc31 1439) +; (acc32 1440) (acc33 1441) (acc34 1442) (acc35 1443) +; (acc36 1444) (acc37 1445) (acc38 1446) (acc39 1447) +; (acc40 1448) (acc41 1449) (acc42 1450) (acc43 1451) +; (acc44 1452) (acc45 1453) (acc46 1454) (acc47 1455) +; (acc48 1456) (acc49 1457) (acc50 1458) (acc51 1459) +; (acc52 1460) (acc53 1461) (acc54 1462) (acc55 1463) +; (acc56 1464) (acc57 1465) (acc58 1466) (acc59 1467) +; (acc60 1468) (acc61 1469) (acc62 1470) (acc63 1471) + +; (accg0 1472) (accg1 1473) (accg2 1474) (accg3 1475) +; (accg4 1476) (accg5 1477) (accg6 1478) (accg7 1479) +; (accg8 1480) (accg9 1481) (accg10 1482) (accg11 1483) +; (accg12 1484) (accg13 1485) (accg14 1486) (accg15 1487) +; (accg16 1488) (accg17 1489) (accg18 1490) (accg19 1491) +; (accg20 1492) (accg21 1493) (accg22 1494) (accg23 1495) +; (accg24 1496) (accg25 1497) (accg26 1498) (accg27 1499) +; (accg28 1500) (accg29 1501) (accg30 1502) (accg31 1503) +; (accg32 1504) (accg33 1505) (accg34 1506) (accg35 1507) +; (accg36 1508) (accg37 1509) (accg38 1510) (accg39 1511) +; (accg40 1512) (accg41 1513) (accg42 1514) (accg43 1515) +; (accg44 1516) (accg45 1517) (accg46 1518) (accg47 1519) +; (accg48 1520) (accg49 1521) (accg50 1522) (accg51 1523) +; (accg52 1524) (accg53 1525) (accg54 1526) (accg55 1527) +; (accg56 1528) (accg57 1529) (accg58 1530) (accg59 1531) +; (accg60 1532) (accg61 1533) (accg62 1534) (accg63 1535) + + (ear0 1536) (ear1 1537) (ear2 1538) (ear3 1539) + (ear4 1540) (ear5 1541) (ear6 1542) (ear7 1543) + (ear8 1544) (ear9 1545) (ear10 1546) (ear11 1547) + (ear12 1548) (ear13 1549) (ear14 1550) (ear15 1551) + (ear16 1552) (ear17 1553) (ear18 1554) (ear19 1555) + (ear20 1556) (ear21 1557) (ear22 1558) (ear23 1559) + (ear24 1560) (ear25 1561) (ear26 1562) (ear27 1563) + (ear28 1564) (ear29 1565) (ear30 1566) (ear31 1567) + (ear32 1568) (ear33 1569) (ear34 1570) (ear35 1571) + (ear36 1572) (ear37 1573) (ear38 1574) (ear39 1575) + (ear40 1576) (ear41 1577) (ear42 1578) (ear43 1579) + (ear44 1580) (ear45 1581) (ear46 1582) (ear47 1583) + (ear48 1584) (ear49 1585) (ear50 1586) (ear51 1587) + (ear52 1588) (ear53 1589) (ear54 1590) (ear55 1591) + (ear56 1592) (ear57 1593) (ear58 1594) (ear59 1595) + (ear60 1596) (ear61 1597) (ear62 1598) (ear63 1599) + + (edr0 1600) (edr1 1601) (edr2 1602) (edr3 1603) + (edr4 1604) (edr5 1605) (edr6 1606) (edr7 1607) + (edr8 1608) (edr9 1609) (edr10 1610) (edr11 1611) + (edr12 1612) (edr13 1613) (edr14 1614) (edr15 1615) + (edr16 1616) (edr17 1617) (edr18 1618) (edr19 1619) + (edr20 1620) (edr21 1621) (edr22 1622) (edr23 1623) + (edr24 1624) (edr25 1625) (edr26 1626) (edr27 1627) + (edr28 1628) (edr29 1629) (edr30 1630) (edr31 1631) + (edr32 1632) (edr33 1636) (edr34 1634) (edr35 1635) + (edr36 1636) (edr37 1637) (edr38 1638) (edr39 1639) + (edr40 1640) (edr41 1641) (edr42 1642) (edr43 1643) + (edr44 1644) (edr45 1645) (edr46 1646) (edr47 1647) + (edr48 1648) (edr49 1649) (edr50 1650) (edr51 1651) + (edr52 1652) (edr53 1653) (edr54 1654) (edr55 1655) + (edr56 1656) (edr57 1657) (edr58 1658) (edr59 1659) + (edr60 1660) (edr61 1661) (edr62 1662) (edr63 1663) + + (iamlr0 1664) (iamlr1 1665) (iamlr2 1666) (iamlr3 1667) + (iamlr4 1668) (iamlr5 1669) (iamlr6 1670) (iamlr7 1671) + (iamlr8 1672) (iamlr9 1673) (iamlr10 1674) (iamlr11 1675) + (iamlr12 1676) (iamlr13 1677) (iamlr14 1678) (iamlr15 1679) + (iamlr16 1680) (iamlr17 1681) (iamlr18 1682) (iamlr19 1683) + (iamlr20 1684) (iamlr21 1685) (iamlr22 1686) (iamlr23 1687) + (iamlr24 1688) (iamlr25 1689) (iamlr26 1690) (iamlr27 1691) + (iamlr28 1692) (iamlr29 1693) (iamlr30 1694) (iamlr31 1695) + (iamlr32 1696) (iamlr33 1697) (iamlr34 1698) (iamlr35 1699) + (iamlr36 1700) (iamlr37 1701) (iamlr38 1702) (iamlr39 1703) + (iamlr40 1704) (iamlr41 1705) (iamlr42 1706) (iamlr43 1707) + (iamlr44 1708) (iamlr45 1709) (iamlr46 1710) (iamlr47 1711) + (iamlr48 1712) (iamlr49 1713) (iamlr50 1714) (iamlr51 1715) + (iamlr52 1716) (iamlr53 1717) (iamlr54 1718) (iamlr55 1719) + (iamlr56 1720) (iamlr57 1721) (iamlr58 1722) (iamlr59 1723) + (iamlr60 1724) (iamlr61 1725) (iamlr62 1726) (iamlr63 1727) + + (iampr0 1728) (iampr1 1729) (iampr2 1730) (iampr3 1731) + (iampr4 1732) (iampr5 1733) (iampr6 1734) (iampr7 1735) + (iampr8 1736) (iampr9 1737) (iampr10 1738) (iampr11 1739) + (iampr12 1740) (iampr13 1741) (iampr14 1742) (iampr15 1743) + (iampr16 1744) (iampr17 1745) (iampr18 1746) (iampr19 1747) + (iampr20 1748) (iampr21 1749) (iampr22 1750) (iampr23 1751) + (iampr24 1752) (iampr25 1753) (iampr26 1754) (iampr27 1755) + (iampr28 1756) (iampr29 1757) (iampr30 1758) (iampr31 1759) + (iampr32 1760) (iampr33 1761) (iampr34 1762) (iampr35 1763) + (iampr36 1764) (iampr37 1765) (iampr38 1766) (iampr39 1767) + (iampr40 1768) (iampr41 1769) (iampr42 1770) (iampr43 1771) + (iampr44 1772) (iampr45 1773) (iampr46 1774) (iampr47 1775) + (iampr48 1776) (iampr49 1777) (iampr50 1778) (iampr51 1779) + (iampr52 1780) (iampr53 1781) (iampr54 1782) (iampr55 1783) + (iampr56 1784) (iampr57 1785) (iampr58 1786) (iampr59 1787) + (iampr60 1788) (iampr61 1789) (iampr62 1790) (iampr63 1791) + + (damlr0 1792) (damlr1 1793) (damlr2 1794) (damlr3 1795) + (damlr4 1796) (damlr5 1797) (damlr6 1798) (damlr7 1799) + (damlr8 1800) (damlr9 1801) (damlr10 1802) (damlr11 1803) + (damlr12 1804) (damlr13 1805) (damlr14 1806) (damlr15 1807) + (damlr16 1808) (damlr17 1809) (damlr18 1810) (damlr19 1811) + (damlr20 1812) (damlr21 1813) (damlr22 1814) (damlr23 1815) + (damlr24 1816) (damlr25 1817) (damlr26 1818) (damlr27 1819) + (damlr28 1820) (damlr29 1821) (damlr30 1822) (damlr31 1823) + (damlr32 1824) (damlr33 1825) (damlr34 1826) (damlr35 1827) + (damlr36 1828) (damlr37 1829) (damlr38 1830) (damlr39 1831) + (damlr40 1832) (damlr41 1833) (damlr42 1834) (damlr43 1835) + (damlr44 1836) (damlr45 1837) (damlr46 1838) (damlr47 1839) + (damlr48 1840) (damlr49 1841) (damlr50 1842) (damlr51 1843) + (damlr52 1844) (damlr53 1845) (damlr54 1846) (damlr55 1847) + (damlr56 1848) (damlr57 1849) (damlr58 1850) (damlr59 1851) + (damlr60 1852) (damlr61 1853) (damlr62 1854) (damlr63 1855) + + (dampr0 1856) (dampr1 1857) (dampr2 1858) (dampr3 1859) + (dampr4 1860) (dampr5 1861) (dampr6 1862) (dampr7 1863) + (dampr8 1864) (dampr9 1865) (dampr10 1866) (dampr11 1867) + (dampr12 1868) (dampr13 1869) (dampr14 1870) (dampr15 1871) + (dampr16 1872) (dampr17 1873) (dampr18 1874) (dampr19 1875) + (dampr20 1876) (dampr21 1877) (dampr22 1878) (dampr23 1879) + (dampr24 1880) (dampr25 1881) (dampr26 1882) (dampr27 1883) + (dampr28 1884) (dampr29 1885) (dampr30 1886) (dampr31 1887) + (dampr32 1888) (dampr33 1889) (dampr34 1890) (dampr35 1891) + (dampr36 1892) (dampr37 1893) (dampr38 1894) (dampr39 1895) + (dampr40 1896) (dampr41 1897) (dampr42 1898) (dampr43 1899) + (dampr44 1900) (dampr45 1901) (dampr46 1902) (dampr47 1903) + (dampr48 1904) (dampr49 1905) (dampr50 1906) (dampr51 1907) + (dampr52 1908) (dampr53 1909) (dampr54 1910) (dampr55 1911) + (dampr56 1912) (dampr57 1913) (dampr58 1914) (dampr59 1915) + (dampr60 1916) (dampr61 1917) (dampr62 1918) (dampr63 1919) + + (amcr 1920) (stbar 1921) (mmcr 1922) + (dcr 2048) (brr 2049) (nmar 2050) + + (ibar0 2052) (ibar1 2053) (ibar2 2054) (ibar3 2055) + (dbar0 2056) (dbar1 2057) (dbar2 2058) (dbar3 2059) + + (dbdr00 2060) (dbdr01 2061) (dbdr02 2062) (dbdr03 2063) + (dbdr10 2064) (dbdr11 2065) (dbdr12 2066) (dbdr13 2067) + (dbdr20 2068) (dbdr21 2069) (dbdr22 2070) (dbdr23 2071) + (dbdr30 2072) (dbdr31 2073) (dbdr32 2074) (dbdr33 2075) + + (dbmr00 2076) (dbmr01 2077) (dbmr02 2078) (dbmr03 2079) + (dbmr10 2080) (dbmr11 2081) (dbmr12 2082) (dbmr13 2083) + (dbmr20 2084) (dbmr21 2085) (dbmr22 2086) (dbmr23 2087) + (dbmr30 2088) (dbmr31 2089) (dbmr32 2090) (dbmr33 2091) + + (cpcfr 2092) (cpcr 2093) (cpsr 2094) + + (cpesr0 2096) (cpesr1 2097) + (cpemr0 2098) (cpemr1 2099) + + (ihsr8 3848) + ) +) + +(define-hardware + (name h-spr) + (comment "special purpose registers") + (attrs PROFILE) + (type register UWI (4096)) + (indices extern-keyword spr-names) + (get (index) (c-call UWI "@cpu@_h_spr_get_handler" index)) + (set (index newval) (c-call VOID "@cpu@_h_spr_set_handler" index newval)) +) + +(define-pmacro (spr-pcsr) (reg h-spr 1)) +(define-pmacro (spr-bpcsr) (reg h-spr 2)) +(define-pmacro (spr-lr) (reg h-spr 272)) +(define-pmacro (spr-lcr) (reg h-spr 273)) +(define-pmacro (spr-iacc0h) (reg h-spr 280)) +(define-pmacro (spr-iacc0l) (reg h-spr 281)) +(define-pmacro (spr-sr0) (reg h-spr 768)) +(define-pmacro (spr-sr1) (reg h-spr 769)) +(define-pmacro (spr-sr2) (reg h-spr 770)) +(define-pmacro (spr-sr3) (reg h-spr 771)) + +; Accumulator guard. Actually a subset of the SPR registers, but those SPRs +; are read-only in most insns. This hardware element is used by those insns +; which have direct access (mwtaccg, mrdaccg). +(define-keyword + (name accg-names) + (print-name h-accg) + (prefix "") + (values + (accg0 0)(accg1 1)(accg2 2)(accg3 3) + (accg4 4)(accg5 5)(accg6 6)(accg7 7) + (accg8 8)(accg9 9)(accg10 10)(accg11 11) + (accg12 12)(accg13 13)(accg14 14)(accg15 15) + (accg16 16)(accg17 17)(accg18 18)(accg19 19) + (accg20 20)(accg21 21)(accg22 22)(accg23 23) + (accg24 24)(accg25 25)(accg26 26)(accg27 27) + (accg28 28)(accg29 29)(accg30 30)(accg31 31) + (accg32 32)(accg33 33)(accg34 34)(accg35 35) + (accg36 36)(accg37 37)(accg38 38)(accg39 39) + (accg40 40)(accg41 41)(accg42 42)(accg43 43) + (accg44 44)(accg45 45)(accg46 46)(accg47 47) + (accg48 48)(accg49 49)(accg50 50)(accg51 51) + (accg52 52)(accg53 53)(accg54 54)(accg55 55) + (accg56 56)(accg57 57)(accg58 58)(accg59 59) + (accg60 60)(accg61 61)(accg62 62)(accg63 63) + ) +) + +(define-hardware + (name h-accg) + (comment "accumulator guard") + (attrs PROFILE VIRTUAL) + (type register UWI (64)) + (indices extern-keyword accg-names) + (get (index) + (and (reg h-spr (add index 1472)) #xff)) + (set (index newval) + (set (raw-reg UWI h-spr (add index 1472)) (and newval #xff))) +) + +; 40 bit accumulator. Composed of ACCG and ACC registers concatenated, but +; referenced more often as the composed 40 bits. +(define-keyword + (name acc-names) + (print-name h-acc40) + (prefix "") + (values +(acc0 0)(acc1 1)(acc2 2)(acc3 3)(acc4 4)(acc5 5)(acc6 6)(acc7 7) +(acc8 8)(acc9 9)(acc10 10)(acc11 11)(acc12 12)(acc13 13)(acc14 14)(acc15 15) +(acc16 16)(acc17 17)(acc18 18)(acc19 19)(acc20 20)(acc21 21)(acc22 22)(acc23 23) +(acc24 24)(acc25 25)(acc26 26)(acc27 27)(acc28 28)(acc29 29)(acc30 30)(acc31 31) +(acc32 32)(acc33 33)(acc34 34)(acc35 35)(acc36 36)(acc37 37)(acc38 38)(acc39 39) +(acc40 40)(acc41 41)(acc42 42)(acc43 43)(acc44 44)(acc45 45)(acc46 46)(acc47 47) +(acc48 48)(acc49 49)(acc50 50)(acc51 51)(acc52 52)(acc53 53)(acc54 54)(acc55 55) +(acc56 56)(acc57 57)(acc58 58)(acc59 59)(acc60 60)(acc61 61)(acc62 62)(acc63 63) + ) +) + +(define-hardware + (name h-acc40S) + (comment "40 bit signed accumulator") + (attrs PROFILE VIRTUAL) + (type register DI (64)) + (indices extern-keyword acc-names) + ; The accumlator is made up of two 32 bit registers, accgi/acci. + ; We want to extract this as a combined 40 signed bits + (get (index) + (or DI + (sll DI (ext DI (trunc QI (reg h-spr (add index 1472)))) + 32) + (zext DI (reg h-spr (add index 1408))))) + ; Bits 40-63 are not written. raw-reg is used to bypass read-only restrictions + ; on ACC and ACCG registers + (set (index newval) + (sequence () + (c-call VOID "frv_check_spr_write_access" (add index 1408)) + (set (raw-reg UWI h-spr + (add index 1472)) (and (srl newval 32) #xff)) + (set (raw-reg UWI h-spr + (add index 1408)) (trunc USI newval)))) +) + +(define-hardware + (name h-acc40U) + (comment "40 bit unsigned accumulator") + (attrs PROFILE VIRTUAL) + (type register UDI (64)) + (indices extern-keyword acc-names) + ; The accumlator is made up of two 32 bit registers, accgi/acci. + ; We want to extract this as a combined 40 unsigned bits + (get (index) + (or DI + (sll DI (zext DI (reg h-spr (add index 1472))) 32) + (zext DI (reg h-spr (add index 1408))))) + ; Bits 40-63 are not written. raw-reg is used to bypass read-only restrictions + ; on ACC and ACCG registers + (set (index newval) + (sequence () + (c-call VOID "frv_check_spr_write_access" (add index 1408)) + (set (raw-reg UWI h-spr + (add index 1472)) (and (srl newval 32) #xff)) + (set (raw-reg UWI h-spr + (add index 1408)) (trunc USI newval)))) +) +; 64-bit signed accumulator. Composed of iacc0h and iacc0l registers +; concatenated, but referenced more often as the composed 64 bits. +(define-keyword + ; This is totally hokey -- I have to have an index! + (name iacc0-names) + (print-name h-iacc0) + (prefix "") + (values (iacc0 0)) +) + +(define-hardware + (name h-iacc0) + (comment "64 bit signed accumulator") + (attrs PROFILE VIRTUAL (MACH fr400)) + (type register DI (1)) + (indices extern-keyword iacc0-names) + ; The single 64-bit integer accumulator is made up of two 32 bit + ; registers, iacc0h and iacc0l. We want to extract this as a + ; combined 64 signed bits. + (get (idx) (or DI (sll DI (ext DI (spr-iacc0h)) 32) (zext DI (spr-iacc0l)))) + (set (idx newval) + (sequence () + (set (spr-iacc0h) (trunc SI (srl newval 32))) + (set (spr-iacc0l) (trunc SI newval)))) +) + +; Integer condition code registers (CCR) +; +; The individual sub registers bits of the CCR are referenced more often than +; the entire register so set them directly. We can assemble the +; entire register when necessary. +; +(define-keyword + (name iccr-names) + (print-name h-iccr) + (prefix "") + (values (icc0 0) (icc1 1) (icc2 2) (icc3 3)) +) + +(define-hardware + (name h-iccr) + (comment "Integer condition code registers") + (attrs PROFILE) + (type register UQI (4)) + (indices extern-keyword iccr-names) +) + +; Floating point condition code registers (CCR) +; +; The individual sub registers bits of the CCR are referenced more often than +; the entire register so set them directly. We can assemble the +; entire register when necessary. +; +(define-keyword + (name fccr-names) + (print-name h-fccr) + (prefix "") + (values (fcc0 0) (fcc1 1) (fcc2 2) (fcc3 3)) +) + +(define-hardware + (name h-fccr) + (comment "Floating point condition code registers") + (attrs PROFILE) + (type register UQI (4)) + (indices extern-keyword fccr-names) +) + +; C condition code registers (CCCR) +; +(define-keyword + (name cccr-names) + (print-name h-cccr) + (prefix "") + (values (cc0 0) (cc1 1) (cc2 2) (cc3 3) (cc4 4) (cc5 5) (cc6 6) (cc7 7)) +) + +(define-hardware + (name h-cccr) + (comment "Condition code registers") + (attrs PROFILE) + (type register UQI (8)) + (indices extern-keyword cccr-names) +) + +; Dummy hardware used to define packing bit on insns +; +(define-hardware + (name h-pack) + (comment "Packing bit dummy hardware") + (type immediate (UINT 1)) + (values keyword "" (("" 1) (".p" 0) (".P" 0))) +) +; Dummy hardware used to define hint field for branches always taken +; +(define-hardware + (name h-hint-taken) + (comment "Branch taken hint dummy hardware") + (type immediate (UINT 1)) + ; The order of these is important. We want '2' to get written by default, + ; but we also want the docoder/disassembler to allow the values '0', '1' and + ; '3'. + (values keyword "" (("" 2) ("" 0) ("" 1) ("" 3))) +) +; Dummy hardware used to define hint field for branches never taken +; +(define-hardware + (name h-hint-not-taken) + (comment "Branch not taken hint dummy hardware") + (type immediate (UINT 1)) + ; The order of these is important. We want '0' to get written by default, + ; but we also want the docoder/disassembler to allow the values '1', '2' and + ; '3'. + (values keyword "" (("" 0) ("" 1) ("" 2) ("" 3))) +) + +; Instruction Operands. +; These entries provide a layer between the assembler and the raw hardware +; description, and are used to refer to hardware elements in the semantic +; code. Usually there's a bit of over-specification, but in more complicated +; instruction sets there isn't. + +; FRV specific operand attributes: + +(define-attr + (for operand) + (type boolean) + (name HASH-PREFIX) + (comment "immediates have an optional '#' prefix") +) + +; ??? Convention says this should be o-sr, but then the insn definitions +; should refer to o-sr which is clumsy. The "o-" could be implicit, but +; then it should be implicit for all the symbols here, but then there would +; be confusion between (f-)simm8 and (h-)simm8. +; So for now the rule is exactly as it appears here. + +; dnmop: define-normal-mode-operand: temporary, pending potential removal +; of modes from h/w. +(define-pmacro (dnmop xname xcomment xattrs xtype xindex xmode) + (define-operand + (name xname) + (comment xcomment) + (.splice attrs (.unsplice xattrs)) + (type xtype) + (index xindex) + (mode xmode) + ) +) + +; dnpmop: define-normal-parsed-mode-operand: Normal mode operand with parse handler +(define-pmacro (dnpmop xname xcomment xattrs xtype xindex xmode xparse) + (define-operand + (name xname) + (comment xcomment) + (.splice attrs (.unsplice xattrs)) + (type xtype) + (index xindex) + (mode xmode) + (handlers (parse xparse)) + ) +) + +(dnop pack "packing bit" () h-pack f-pack) + +(dnmop GRi "source register 1" () h-gr f-GRi SI) +(dnmop GRj "source register 2" () h-gr f-GRj SI) +(dnmop GRk "destination register" () h-gr f-GRk SI) +(dnmop GRkhi "destination register" () h-gr_hi f-GRk UHI) +(dnmop GRklo "destination register" () h-gr_lo f-GRk UHI) +(dnpmop GRdoublek "destination register" () h-gr_double f-GRk DI "even_register") +(dnmop ACC40Si "signed accumulator" () h-acc40S f-ACC40Si DI) +(dnmop ACC40Ui "unsigned accumulator" () h-acc40U f-ACC40Ui UDI) +(dnmop ACC40Sk "target accumulator" () h-acc40S f-ACC40Sk DI) +(dnmop ACC40Uk "target accumulator" () h-acc40U f-ACC40Uk UDI) +(dnmop ACCGi "source register" () h-accg f-ACCGi UWI) +(dnmop ACCGk "target register" () h-accg f-ACCGk UWI) + +(dnmop CPRi "source register" ((MACH frv)) h-cpr f-CPRi SI) +(dnmop CPRj "source register" ((MACH frv)) h-cpr f-CPRj SI) +(dnmop CPRk "destination register" ((MACH frv)) h-cpr f-CPRk SI) +(dnpmop CPRdoublek "destination register" ((MACH frv)) h-cpr_double f-CPRk DI "even_register") + +; floating point operands +(dnmop FRinti "source register 1" () h-fr_int f-FRi SI) +(dnmop FRintj "source register 2" () h-fr_int f-FRj SI) +(dnmop FRintk "target register" () h-fr_int f-FRk SI) +(dnmop FRi "source register 1" () h-fr f-FRi SF) +(dnmop FRj "source register 2" () h-fr f-FRj SF) +(dnmop FRk "destination register" () h-fr f-FRk SF) +(dnmop FRkhi "destination register" () h-fr_hi f-FRk UHI) +(dnmop FRklo "destination register" () h-fr_lo f-FRk UHI) +(dnpmop FRdoublei "source register 1" () h-fr_double f-FRi DF "even_register") +(dnpmop FRdoublej "source register 2" () h-fr_double f-FRj DF "even_register") +(dnpmop FRdoublek "target register" () h-fr_double f-FRk DF "even_register") + +(dnop CRi "source register 1" () h-cccr f-CRi) +(dnop CRj "source register 2" () h-cccr f-CRj) +(dnop CRj_int "destination register" () h-cccr f-CRj_int) +(dnop CRj_float "destination register" () h-cccr f-CRj_float) +(dnop CRk "destination register" () h-cccr f-CRk) +(dnop CCi "condition register" () h-cccr f-CCi) + +(dnop ICCi_1 "condition register" () h-iccr f-ICCi_1) +(dnop ICCi_2 "condition register" () h-iccr f-ICCi_2) +(dnop ICCi_3 "condition register" () h-iccr f-ICCi_3) +(dnop FCCi_1 "condition register" () h-fccr f-FCCi_1) +(dnop FCCi_2 "condition register" () h-fccr f-FCCi_2) +(dnop FCCi_3 "condition register" () h-fccr f-FCCi_3) +(dnop FCCk "condition register" () h-fccr f-FCCk) + +(dnop eir "exception insn reg" () h-uint f-eir) +(dnop s10 "10 bit signed immediate" (HASH-PREFIX) h-sint f-s10) +(dnop u16 "16 bit unsigned immediate" (HASH-PREFIX) h-uint f-u16) +(dnop s16 "16 bit signed immediate" (HASH-PREFIX) h-sint f-s16) +(dnop s6 "6 bit signed immediate" (HASH-PREFIX) h-sint f-s6) +(dnop s6_1 "6 bit signed immediate" (HASH-PREFIX) h-sint f-s6_1) +(dnop u6 "6 bit unsigned immediate" (HASH-PREFIX) h-uint f-u6) +(dnop s5 "5 bit signed immediate" (HASH-PREFIX) h-sint f-s5) +(dnop cond "conditional arithmetic" (HASH-PREFIX) h-uint f-cond) +(dnop ccond "lr branch condition" (HASH-PREFIX) h-uint f-ccond) +(dnop hint "2 bit branch predictor" (HASH-PREFIX) h-uint f-hint) +(dnop hint_taken "2 bit branch predictor" () h-hint-taken f-hint) +(dnop hint_not_taken "2 bit branch predictor" () h-hint-not-taken f-hint) + +(dnop LI "link indicator" () h-uint f-LI) +(dnop lock "cache lock indicator" (HASH-PREFIX) h-uint f-lock) +(dnop debug "debug mode indicator" (HASH-PREFIX) h-uint f-debug) +(dnop ae "all entries indicator" (HASH-PREFIX) h-uint f-ae) + +(dnop label16 "18 bit pc relative address" () h-iaddr f-label16) +(dnop label24 "26 bit pc relative address" () h-iaddr f-label24) + +(define-operand + (name A0) + (comment "A==0 operand of mclracc") + (attrs) + (type h-uint) + (index f-A) + (mode USI) + (handlers (parse "A0")) +) + +(define-operand + (name A1) + (comment "A==1 operand of mclracc") + (attrs) + (type h-uint) + (index f-A) + (mode USI) + (handlers (parse "A1")) +) + +(define-operand + (name FRintieven) + (comment "(even) source register 1") + (attrs) + (type h-fr_int) + (index f-FRi) + (mode SI) + (handlers (parse "even_register")) +) + +(define-operand + (name FRintjeven) + (comment "(even) source register 2") + (attrs) + (type h-fr_int) + (index f-FRj) + (mode SI) + (handlers (parse "even_register")) +) + +(define-operand + (name FRintkeven) + (comment "(even) target register") + (attrs) + (type h-fr_int) + (index f-FRk) + (mode SI) + (handlers (parse "even_register")) +) + +(define-operand + (name d12) + (comment "12 bit signed immediate") + (attrs) + (type h-sint) + (index f-d12) + (handlers (parse "d12")) +) + +(define-operand + (name s12) + (comment "12 bit signed immediate") + (attrs HASH-PREFIX) + (type h-sint) + (index f-d12) + (handlers (parse "s12")) +) + +(define-operand + (name u12) + (comment "12 bit signed immediate") + (attrs HASH-PREFIX) + (type h-sint) + (index f-u12) + (handlers (parse "u12")) +) + +(define-operand + (name spr) + (comment "special purpose register") + (attrs) + (type h-spr) + (index f-spr) + (handlers (parse "spr") (print "spr")) +) + +(define-operand + (name ulo16) + (comment "16 bit unsigned immediate, for #lo()") + (attrs) + (type h-uint) + (index f-u16) + (handlers (parse "ulo16") (print "lo")) +) + +(define-operand + (name slo16) + (comment "16 bit unsigned immediate, for #lo()") + (attrs) + (type h-sint) + (index f-s16) + (handlers (parse "uslo16") (print "lo")) +) + +(define-operand + (name uhi16) + (comment "16 bit unsigned immediate, for #hi()") + (attrs) + (type h-uint) + (index f-u16) + (handlers (parse "uhi16") (print "hi")) +) + +; operands representing hardware +; +(dnop psr_esr "PSR.ESR bit" (SEM-ONLY) h-psr_esr f-nil) +(dnop psr_s "PSR.S bit" (SEM-ONLY) h-psr_s f-nil) +(dnop psr_ps "PSR.PS bit" (SEM-ONLY) h-psr_ps f-nil) +(dnop psr_et "PSR.ET bit" (SEM-ONLY) h-psr_et f-nil) + +(dnop bpsr_bs "BPSR.BS bit" (SEM-ONLY) h-bpsr_bs f-nil) +(dnop bpsr_bet "BPSR.BET bit" (SEM-ONLY) h-bpsr_bet f-nil) + +(dnop tbr_tba "TBR.TBA" (SEM-ONLY) h-tbr_tba f-nil) +(dnop tbr_tt "TBR.TT" (SEM-ONLY) h-tbr_tt f-nil) + +; Null operands +; +(define-pmacro (ICCi_1-null) (f-ICCi_1-null 0)) +(define-pmacro (ICCi_2-null) (f-ICCi_2-null 0)) +(define-pmacro (ICCi_3-null) (f-ICCi_3-null 0)) +(define-pmacro (FCCi_1-null) (f-FCCi_1-null 0)) +(define-pmacro (FCCi_2-null) (f-FCCi_2-null 0)) +(define-pmacro (FCCi_3-null) (f-FCCi_3-null 0)) +(define-pmacro (rs-null) (f-rs-null 0)) +(define-pmacro (GRi-null) (f-GRi-null 0)) +(define-pmacro (GRj-null) (f-GRj-null 0)) +(define-pmacro (GRk-null) (f-GRk-null 0)) +(define-pmacro (FRi-null) (f-FRi-null 0)) +(define-pmacro (FRj-null) (f-FRj-null 0)) +(define-pmacro (ACCj-null) (f-ACCj-null 0)) +(define-pmacro (rd-null) (f-rd-null 0)) +(define-pmacro (cond-null) (f-cond-null 0)) +(define-pmacro (ccond-null) (f-ccond-null 0)) +(define-pmacro (s12-null) (f-s12-null 0)) +(define-pmacro (label16-null) (f-label16-null 0)) +(define-pmacro (misc-null-1) (f-misc-null-1 0)) +(define-pmacro (misc-null-2) (f-misc-null-2 0)) +(define-pmacro (misc-null-3) (f-misc-null-3 0)) +(define-pmacro (misc-null-4) (f-misc-null-4 0)) +(define-pmacro (misc-null-5) (f-misc-null-5 0)) +(define-pmacro (misc-null-6) (f-misc-null-6 0)) +(define-pmacro (misc-null-7) (f-misc-null-7 0)) +(define-pmacro (misc-null-8) (f-misc-null-8 0)) +(define-pmacro (misc-null-9) (f-misc-null-9 0)) +(define-pmacro (misc-null-10) (f-misc-null-10 0)) +(define-pmacro (misc-null-11) (f-misc-null-11 0)) + +(define-pmacro (LI-on) (f-LI-on 1)) +(define-pmacro (LI-off) (f-LI-off 0)) + +; Instruction definitions. +; +; Notes: +; - dni is short for "define-normal-instruction" +; - Macros are used to represent each insn format. These should be used as much +; as possible unless an insn has exceptional behaviour +; + +; Commonly used Macros +; +; Specific registers +; + +; Integer condition code manipulation +; +(define-pmacro (set-z-and-n icc x) + (if (eq x 0) + (set icc (or (and icc #x7) #x4)) + (if (lt x 0) + (set icc (or (and icc #xb) #x8)) + (set icc (and icc #x3)))) +) + +(define-pmacro (set-n icc val) + (if (eq val 0) + (set icc (and icc #x7)) + (set icc (or icc #x8))) +) + +(define-pmacro (set-z icc val) + (if (eq val 0) + (set icc (and icc #xb)) + (set icc (or icc #x4))) +) + +(define-pmacro (set-v icc val) + (if (eq val 0) + (set icc (and icc #xd)) + (set icc (or icc #x2))) +) + +(define-pmacro (set-c icc val) + (if (eq val 0) + (set icc (and icc #xe)) + (set icc (or icc #x1))) +) + +(define-pmacro (nbit icc) + (trunc BI (srl (and icc #x8) 3)) +) + +(define-pmacro (zbit icc) + (trunc BI (srl (and icc #x4) 2)) +) + +(define-pmacro (vbit icc) + (trunc BI (srl (and icc #x2) 1)) +) + +(define-pmacro (cbit icc) + (trunc BI (and icc #x1)) +) + +(define-pmacro (ebit icc) + (trunc BI (srl (and icc #x8) 3)) +) + +(define-pmacro (lbit icc) + (trunc BI (srl (and icc #x4) 2)) +) + +(define-pmacro (gbit icc) + (trunc BI (srl (and icc #x2) 1)) +) + +(define-pmacro (ubit icc) + (trunc BI (and icc #x1)) +) + +; FRV insns +; +; +; Format: INT, Logic, Shift r-r +; +(define-pmacro (int-logic-r-r name operation op ope comment) + (dni name + (comment) + ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1)) + (.str name "$pack $GRi,$GRj,$GRk") + (+ pack GRk op GRi (ICCi_1-null) ope GRj) + (set GRk (operation GRi GRj)) + ((fr400 (unit u-integer)) + (fr500 (unit u-integer)) (fr550 (unit u-integer))) + ) +) + +(int-logic-r-r add add OP_00 OPE2_00 "add reg/reg") +(int-logic-r-r sub sub OP_00 OPE2_04 "sub reg/reg") +(int-logic-r-r and and OP_01 OPE2_00 "and reg/reg") +(int-logic-r-r or or OP_01 OPE2_02 "or reg/reg") +(int-logic-r-r xor xor OP_01 OPE2_04 "xor reg/reg") + +(dni not + ("not") + ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1)) + ("not$pack $GRj,$GRk") + (+ pack GRk OP_01 (rs-null) (ICCi_1-null) OPE2_06 GRj) + (set GRk (inv GRj)) + ((fr400 (unit u-integer)) + (fr500 (unit u-integer)) (fr550 (unit u-integer))) +) + +(dni sdiv + "signed division" + ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) (FR400-MAJOR I-1)) + "sdiv$pack $GRi,$GRj,$GRk" + (+ pack GRk OP_00 GRi (ICCi_1-null) OPE2_0E GRj) + (sequence () + (c-call VOID "@cpu@_signed_integer_divide" + GRi GRj (index-of GRk) 0) + (clobber GRk)) + ((fr400 (unit u-idiv)) + (fr500 (unit u-idiv)) (fr550 (unit u-idiv))) +) + +(dni nsdiv + "non excepting signed division" + ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) NON-EXCEPTING + (MACH simple,tomcat,fr500,fr550,frv)) + "nsdiv$pack $GRi,$GRj,$GRk" + (+ pack GRk OP_01 GRi (ICCi_1-null) OPE2_0E GRj) + (sequence () + (c-call VOID "@cpu@_signed_integer_divide" + GRi GRj (index-of GRk) 1) + (clobber GRk)) + ((fr400 (unit u-idiv)) + (fr500 (unit u-idiv)) (fr550 (unit u-idiv))) +) + +(dni udiv + "unsigned division reg/reg" + ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) (FR400-MAJOR I-1)) + "udiv$pack $GRi,$GRj,$GRk" + (+ pack GRk OP_00 GRi (ICCi_1-null) OPE2_0F GRj) + (sequence () + (c-call VOID "@cpu@_unsigned_integer_divide" + GRi GRj (index-of GRk) 0) + (clobber GRk)) + ((fr400 (unit u-idiv)) + (fr500 (unit u-idiv)) (fr550 (unit u-idiv))) +) + +(dni nudiv + "non excepting unsigned division" + ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) NON-EXCEPTING + (MACH simple,tomcat,fr500,fr550,frv)) + "nudiv$pack $GRi,$GRj,$GRk" + (+ pack GRk OP_01 GRi (ICCi_1-null) OPE2_0F GRj) + (sequence () + (c-call VOID "@cpu@_unsigned_integer_divide" + GRi GRj (index-of GRk) 1) + (clobber GRk)) + ((fr400 (unit u-idiv)) + (fr500 (unit u-idiv)) (fr550 (unit u-idiv))) +) + +; Multiplication +; +(define-pmacro (multiply-r-r name signop op ope comment) + (dni name + (comment) + ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) (FR400-MAJOR I-1)) + (.str name "$pack $GRi,$GRj,$GRdoublek") + (+ pack GRdoublek op GRi (ICCi_1-null) ope GRj) + (set GRdoublek (mul DI (signop DI GRi) (signop DI GRj))) + ((fr400 (unit u-imul)) + (fr500 (unit u-imul)) (fr550 (unit u-imul))) + ) +) + +(multiply-r-r smul ext OP_00 OPE2_08 "signed multiply reg/reg") +(multiply-r-r umul zext OP_00 OPE2_0A "unsigned multiply reg/reg") + +; Multiplication with integer accumulator IACC +; + +(define-pmacro (iacc-set value) + (set (reg h-iacc0 0) value)) + +(define-pmacro (iacc-add value) + (set (reg h-iacc0 0) + (cond DI + ((andif (andif (gt value 0) (gt (reg h-iacc0 0) 0)) + (lt (sub DI #x7fffffffffffffff value) (reg h-iacc0 0))) + ; Positive overflow + (const DI #x7fffffffffffffff)) + ((andif (andif (lt value 0) (lt (reg h-iacc0 0) 0)) + (gt (sub DI #x8000000000000000 value) (reg h-iacc0 0))) + ; Negative overflow + (const DI #x8000000000000000)) + (else + (add DI (reg h-iacc0 0) value)))) +) + +(define-pmacro (iacc-sub value) + (set (reg h-iacc0 0) + (cond DI + ((andif (andif (lt value 0) (gt (reg h-iacc0 0) 0)) + (lt (add DI #x7fffffffffffffff value) (reg h-iacc0 0))) + ; Positive overflow + (const DI #x7fffffffffffffff)) + ((andif (andif (gt value 0) (lt (reg h-iacc0 0) 0)) + (gt (add DI #x8000000000000000 value) (reg h-iacc0 0))) + ; Negative overflow + (const DI #x8000000000000000)) + (else + (sub DI (reg h-iacc0 0) value)))) +) + +(define-pmacro (iacc-multiply-r-r name operation op ope comment) + (dni name + (comment) + ((UNIT MULT-DIV) (FR400-MAJOR I-1) (MACH fr400)) + (.str name "$pack $GRi,$GRj") + (+ pack (rd-null) op GRi ope GRj) + ((.sym iacc- operation) (mul DI (ext DI GRi) (ext DI GRj))) + ((fr400 (unit u-integer))) + ) +) + +(iacc-multiply-r-r smu set OP_46 OPE1_05 "Signed multiply reg/reg/iacc") +(iacc-multiply-r-r smass add OP_46 OPE1_06 "Signed multiply/add reg/reg/iacc") +(iacc-multiply-r-r smsss sub OP_46 OPE1_07 "Signed multiply/sub reg/reg/iacc") + +(define-pmacro (int-shift-r-r name op ope comment) + (dni name + (comment) + ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1)) + (.str name "$pack $GRi,$GRj,$GRk") + (+ pack GRk op GRi (ICCi_1-null) ope GRj) + (set GRk (name GRi (and GRj #x1f))) + ((fr400 (unit u-integer)) + (fr500 (unit u-integer)) (fr550 (unit u-integer))) + ) +) + +(int-shift-r-r sll OP_01 OPE2_08 "shift left logical reg/reg") +(int-shift-r-r srl OP_01 OPE2_0A "shift right logical reg/reg") +(int-shift-r-r sra OP_01 OPE2_0C "shift right arith reg/reg") + +(dni slass + "shift left arith reg/reg with saturation" + ((UNIT IALL) (FR400-MAJOR I-1) (MACH fr400)) + "slass$pack $GRi,$GRj,$GRk" + (+ pack GRk OP_46 GRi OPE1_02 GRj) + (set GRk (c-call SI "@cpu@_shift_left_arith_saturate" GRi GRj)) + () +) + +(dni scutss + "Integer accumulator cut with saturation" + ((UNIT IALL) (FR400-MAJOR I-1) (MACH fr400)) + "scutss$pack $GRj,$GRk" + (+ pack GRk OP_46 (rs-null) OPE1_04 GRj) + (set GRk (c-call SI "@cpu@_iacc_cut" (reg h-iacc0 0) GRj)) + () +) + +(define-pmacro (scan-semantics arg1 arg2 targ) + (sequence ((WI tmp1) (WI tmp2)) + (set tmp1 arg1) + (set tmp2 (sra arg2 1)) + (set targ (c-call WI "@cpu@_scan_result" (xor tmp1 tmp2)))) +) + +(dni scan + "scan" + ((UNIT SCAN) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1)) + "scan$pack $GRi,$GRj,$GRk" + (+ pack GRk OP_0B GRi (ICCi_1-null) OPE2_00 GRj) + (scan-semantics GRi GRj GRk) + ((fr400 (unit u-integer)) + (fr500 (unit u-integer)) (fr550 (unit u-integer))) +) + +; Format: conditional INT, Logic, Shift r-r +; +(define-pmacro (conditional-int-logic name operation op ope comment) + (dni name + (comment) + ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1) CONDITIONAL) + (.str name "$pack $GRi,$GRj,$GRk,$CCi,$cond") + (+ pack GRk op GRi CCi cond ope GRj) + (if (eq CCi (or cond 2)) + (set GRk (operation GRi GRj))) + ((fr400 (unit u-integer)) + (fr500 (unit u-integer)) (fr550 (unit u-integer))) + ) +) + +(conditional-int-logic cadd add OP_58 OPE4_0 "conditional add") +(conditional-int-logic csub sub OP_58 OPE4_1 "conditional sub") +(conditional-int-logic cand and OP_5A OPE4_0 "conditional and") +(conditional-int-logic cor or OP_5A OPE4_1 "conditional or") +(conditional-int-logic cxor xor OP_5A OPE4_2 "conditional xor") + +(dni cnot + "conditional not" + ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1) CONDITIONAL) + "cnot$pack $GRj,$GRk,$CCi,$cond" + (+ pack GRk OP_5A (rs-null) CCi cond OPE4_3 GRj) + (if (eq CCi (or cond 2)) + (set GRk (inv GRj))) + ((fr400 (unit u-integer)) + (fr500 (unit u-integer)) (fr550 (unit u-integer))) +) + +(dni csmul + "conditional signed multiply" + ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) (FR400-MAJOR I-1) CONDITIONAL) + "csmul$pack $GRi,$GRj,$GRdoublek,$CCi,$cond" + (+ pack GRdoublek OP_58 GRi CCi cond OPE4_2 GRj) + (if (eq CCi (or cond 2)) + (set GRdoublek (mul DI (ext DI GRi) (ext DI GRj)))) + ((fr400 (unit u-imul)) + (fr500 (unit u-imul)) (fr550 (unit u-imul))) +) + +(dni csdiv + "conditional signed division" + ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) (FR400-MAJOR I-1) CONDITIONAL) + "csdiv$pack $GRi,$GRj,$GRk,$CCi,$cond" + (+ pack GRk OP_58 GRi CCi cond OPE4_3 GRj) + (if (eq CCi (or cond 2)) + (sequence () + (c-call VOID "@cpu@_signed_integer_divide" + GRi GRj (index-of GRk) 0) + (clobber GRk))) + ((fr400 (unit u-idiv)) + (fr500 (unit u-idiv)) (fr550 (unit u-idiv))) +) + +(dni cudiv + "conditional unsigned division" + ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) (FR400-MAJOR I-1) CONDITIONAL) + "cudiv$pack $GRi,$GRj,$GRk,$CCi,$cond" + (+ pack GRk OP_59 GRi CCi cond OPE4_3 GRj) + (if (eq CCi (or cond 2)) + (sequence () + (c-call VOID "@cpu@_unsigned_integer_divide" + GRi GRj (index-of GRk) 0) + (clobber GRk))) + ((fr400 (unit u-idiv)) + (fr500 (unit u-idiv)) (fr550 (unit u-idiv))) +) + +(define-pmacro (conditional-shift name operation op ope comment) + (dni name + (comment) + ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1) CONDITIONAL) + (.str name "$pack $GRi,$GRj,$GRk,$CCi,$cond") + (+ pack GRk op GRi CCi cond ope GRj) + (if (eq CCi (or cond 2)) + (set GRk (operation GRi (and GRj #x1f)))) + ((fr400 (unit u-integer)) + (fr500 (unit u-integer)) (fr550 (unit u-integer))) + ) +) + +(conditional-shift csll sll OP_5C OPE4_0 "conditional shift left logical") +(conditional-shift csrl srl OP_5C OPE4_1 "conditional shift right logical") +(conditional-shift csra sra OP_5C OPE4_2 "conditional shift right arith") + +(dni cscan + "conditional scan" + ((UNIT SCAN) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1) CONDITIONAL) + "cscan$pack $GRi,$GRj,$GRk,$CCi,$cond" + (+ pack GRk OP_65 GRi CCi cond OPE4_3 GRj) + (if (eq CCi (or cond 2)) + (scan-semantics GRi GRj GRk)) + ((fr400 (unit u-integer)) + (fr500 (unit u-integer)) (fr550 (unit u-integer))) +) + +; Format: INT, Logic, Shift, cc r-r +; +(define-pmacro (int-arith-cc-semantics operation icc) + (sequence ((BI tmp) (QI cc) (SI result)) + (set cc icc) + (set tmp ((.sym operation -oflag) GRi GRj (const 0))) + (set-v cc tmp) + (set tmp ((.sym operation -cflag) GRi GRj (const 0))) + (set-c cc tmp) + (set result (operation GRi GRj)) + (set-z-and-n cc result) + (set GRk result) + (set icc cc)) +) + +(define-pmacro (int-arith-cc-r-r name operation op ope comment) + (dni name + (comment) + ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1)) + (.str name "$pack $GRi,$GRj,$GRk,$ICCi_1") + (+ pack GRk op GRi ICCi_1 ope GRj) + (int-arith-cc-semantics operation ICCi_1) + ((fr400 (unit u-integer)) + (fr500 (unit u-integer)) (fr550 (unit u-integer))) + ) +) + +(int-arith-cc-r-r addcc add OP_00 OPE2_01 "add reg/reg, set icc") +(int-arith-cc-r-r subcc sub OP_00 OPE2_05 "sub reg/reg, set icc") + +(define-pmacro (int-logic-cc-semantics op icc) + (sequence ((SI tmp)) + (set tmp (op GRi GRj)) + (set GRk tmp) + (set-z-and-n icc tmp)) +) + +(define-pmacro (int-logic-cc-r-r name op ope comment) + (dni (.sym name cc) + (comment) + ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1)) + (.str (.sym name cc) "$pack $GRi,$GRj,$GRk,$ICCi_1") + (+ pack GRk op GRi ICCi_1 ope GRj) + (int-logic-cc-semantics name ICCi_1) + ((fr400 (unit u-integer)) + (fr500 (unit u-integer)) (fr550 (unit u-integer))) + ) +) + +(int-logic-cc-r-r and OP_01 OPE2_01 "and reg/reg, set icc") +(int-logic-cc-r-r or OP_01 OPE2_03 "or reg/reg, set icc") +(int-logic-cc-r-r xor OP_01 OPE2_05 "xor reg/reg, set icc") + +(define-pmacro (int-shift-cc-semantics op l-r icc) + (sequence ((WI shift) (SI tmp) (QI cc)) + (set shift (and GRj #x1f)) + (set cc (c-call QI (.str "@cpu@_set_icc_for_shift_" l-r) + GRi shift icc)) + (set tmp (op GRi shift)) + (set GRk tmp) + (set-z-and-n cc tmp) + (set icc cc)) +) + +(define-pmacro (int-shift-cc-r-r name l-r op ope comment) + (dni (.sym name cc) + (comment) + ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1)) + (.str (.sym name cc) "$pack $GRi,$GRj,$GRk,$ICCi_1") + (+ pack GRk op GRi ICCi_1 ope GRj) + (int-shift-cc-semantics name l-r ICCi_1) + ((fr400 (unit u-integer)) + (fr500 (unit u-integer)) (fr550 (unit u-integer))) + ) +) + +(int-shift-cc-r-r sll left OP_01 OPE2_09 "shift left logical reg/reg,set icc") +(int-shift-cc-r-r srl right OP_01 OPE2_0B "shift right logical reg/reg,set icc") +(int-shift-cc-r-r sra right OP_01 OPE2_0D "shift right arith reg/reg,set icc") + +(define-pmacro (multiply-cc-semantics signop arg1 arg2 targ icc) + (sequence ((DI tmp) (QI cc)) + (set cc icc) + (set tmp (mul DI (signop DI arg1) (signop DI arg2))) + (set-n cc (srl DI tmp 63)) + (set-z cc (eq tmp 0)) + (set targ tmp) + (set icc cc)) +) + +(define-pmacro (multiply-cc-r-r name signop op ope comment) + (dni name + (comment) + ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) (FR400-MAJOR I-1)) + (.str name "$pack $GRi,$GRj,$GRdoublek,$ICCi_1") + (+ pack GRdoublek op GRi ICCi_1 ope GRj) + (multiply-cc-semantics signop GRi GRj GRdoublek ICCi_1) + ((fr400 (unit u-imul)) + (fr500 (unit u-imul)) (fr550 (unit u-imul))) + ) +) + +(multiply-cc-r-r smulcc ext OP_00 OPE2_09 "signed multiply reg/reg") +(multiply-cc-r-r umulcc zext OP_00 OPE2_0B "unsigned multiply reg/reg") + + +; Format: conditional INT, Logic, Shift, cc r-r +; +(define-pmacro (conditional-int-arith-cc name operation op ope comment) + (dni name + (comment) + ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1) CONDITIONAL) + (.str name "$pack $GRi,$GRj,$GRk,$CCi,$cond") + (+ pack GRk op GRi CCi cond ope GRj) + (if (eq CCi (or cond 2)) + (int-arith-cc-semantics operation + (reg h-iccr (and (index-of CCi) 3)))) + ((fr400 (unit u-integer)) + (fr500 (unit u-integer)) (fr550 (unit u-integer))) + ) +) + +(conditional-int-arith-cc caddcc add OP_59 OPE4_0 "add, set icc") +(conditional-int-arith-cc csubcc sub OP_59 OPE4_1 "sub, set icc") + +(dni csmulcc + "conditional signed multiply and set condition code" + ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) (FR400-MAJOR I-1) CONDITIONAL) + "csmulcc$pack $GRi,$GRj,$GRdoublek,$CCi,$cond" + (+ pack GRdoublek OP_59 GRi CCi cond OPE4_2 GRj) + (if (eq CCi (or cond 2)) + (multiply-cc-semantics ext GRi GRj GRdoublek + (reg h-iccr (and (index-of CCi) 3)))) + ((fr400 (unit u-imul)) + (fr500 (unit u-imul)) (fr550 (unit u-imul))) +) + +(define-pmacro (conditional-int-logic-cc name operation op ope comment) + (dni name + (comment) + ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1) CONDITIONAL) + (.str name "$pack $GRi,$GRj,$GRk,$CCi,$cond") + (+ pack GRk op GRi CCi cond ope GRj) + (if (eq CCi (or cond 2)) + (int-logic-cc-semantics operation + (reg h-iccr (and (index-of CCi) 3)))) + ((fr400 (unit u-integer)) + (fr500 (unit u-integer)) (fr550 (unit u-integer))) + ) +) + +(conditional-int-logic-cc candcc and OP_5B OPE4_0 "conditional and, set icc") +(conditional-int-logic-cc corcc or OP_5B OPE4_1 "conditional or , set icc") +(conditional-int-logic-cc cxorcc xor OP_5B OPE4_2 "conditional xor, set icc") + +(define-pmacro (conditional-int-shift-cc name l-r op ope comment) + (dni (.sym c name cc) + (comment) + ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1) CONDITIONAL) + (.str (.sym c name cc) "$pack $GRi,$GRj,$GRk,$CCi,$cond") + (+ pack GRk op GRi CCi cond ope GRj) + (if (eq CCi (or cond 2)) + (int-shift-cc-semantics name l-r + (reg h-iccr (and (index-of CCi) 3)))) + ((fr400 (unit u-integer)) + (fr500 (unit u-integer)) (fr550 (unit u-integer))) + ) +) + +(conditional-int-shift-cc sll left OP_5D OPE4_0 "shift left logical, set icc") +(conditional-int-shift-cc srl right OP_5D OPE4_1 "shift right logical, set icc") +(conditional-int-shift-cc sra right OP_5D OPE4_2 "shift right arith , set icc") + +; Add and subtract with carry +; +(define-pmacro (int-arith-x-r-r name operation op ope comment) + (dni name + (comment) + ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1)) + (.str name "$pack $GRi,$GRj,$GRk,$ICCi_1") + (+ pack GRk op GRi ICCi_1 ope GRj) + (set GRk ((.sym operation c) GRi GRj (cbit ICCi_1))) + ((fr400 (unit u-integer)) + (fr500 (unit u-integer)) (fr550 (unit u-integer))) + ) +) + +(int-arith-x-r-r addx add OP_00 OPE2_02 "Add reg/reg, with carry") +(int-arith-x-r-r subx sub OP_00 OPE2_06 "Sub reg/reg, with carry") + +(define-pmacro (int-arith-x-cc-r-r name operation op ope comment) + (dni name + (comment) + ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1)) + (.str name "$pack $GRi,$GRj,$GRk,$ICCi_1") + (+ pack GRk op GRi ICCi_1 ope GRj) + (sequence ((WI tmp) (QI cc)) + (set cc ICCi_1) + (set tmp ((.sym operation c) GRi GRj (cbit cc))) + (set-v cc ((.sym operation -oflag) GRi GRj (cbit cc))) + (set-c cc ((.sym operation -cflag) GRi GRj (cbit cc))) + (set-z-and-n cc tmp) + (set GRk tmp) + (set ICCi_1 cc)) + ((fr400 (unit u-integer)) + (fr500 (unit u-integer)) (fr550 (unit u-integer))) + ) +) + +(int-arith-x-cc-r-r addxcc add OP_00 OPE2_03 "Add reg/reg, use/set carry") +(int-arith-x-cc-r-r subxcc sub OP_00 OPE2_07 "Sub reg/reg, use/set carry") +; Add and subtract with saturation +; +(define-pmacro (int-arith-ss-r-r name operation op ope comment) + (dni name + (comment) + ((UNIT IALL) (FR400-MAJOR I-1) (MACH fr400)) + (.str name "$pack $GRi,$GRj,$GRk") + (+ pack GRk op GRi ope GRj) + (sequence () + (set GRk (operation GRi GRj)) + (if ((.sym operation -oflag) GRi GRj (const 0)) + ; Overflow, saturate. + ; Sign of result will be + ; same as sign of first operand. + (set GRk + (cond SI + ((gt GRi 0) (const #x7fffffff)) + ((lt GRi 0) (const #x80000000)) + (else (const 0))))) + ) + ((fr400 (unit u-integer))) + ) +) + +(int-arith-ss-r-r addss add OP_46 OPE1_00 "add reg/reg, with saturation") +(int-arith-ss-r-r subss sub OP_46 OPE1_01 "sub reg/reg, with saturation") + +; Format: INT, Logic, Shift r-simm +; +(define-pmacro (int-logic-r-simm name operation op comment) + (dni name + (comment) + ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1)) + (.str name "$pack $GRi,$s12,$GRk") + (+ pack GRk op GRi s12) + (set GRk (operation GRi s12)) + ((fr400 (unit u-integer)) + (fr500 (unit u-integer)) (fr550 (unit u-integer))) + ) +) + +(int-logic-r-simm addi add OP_10 "add reg/immed") +(int-logic-r-simm subi sub OP_14 "sub reg/immed") +(int-logic-r-simm andi and OP_20 "and reg/immed") +(int-logic-r-simm ori or OP_22 "or reg/immed") +(int-logic-r-simm xori xor OP_24 "xor reg/immed") + +(dni sdivi + "signed division reg/immed" + ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) (FR400-MAJOR I-1)) + "sdivi$pack $GRi,$s12,$GRk" + (+ pack GRk OP_1E GRi s12) + (sequence () + (c-call VOID "@cpu@_signed_integer_divide" + GRi s12 (index-of GRk) 0) + (clobber GRk)) + ((fr400 (unit u-idiv)) + (fr500 (unit u-idiv)) (fr550 (unit u-idiv))) +) + +(dni nsdivi + "non excepting signed division reg/immed" + ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) NON-EXCEPTING + (MACH simple,tomcat,fr500,fr550,frv)) + "nsdivi$pack $GRi,$s12,$GRk" + (+ pack GRk OP_2E GRi s12) + (sequence () + (c-call VOID "@cpu@_signed_integer_divide" + GRi s12 (index-of GRk) 1) + (clobber GRk)) + ((fr400 (unit u-idiv)) + (fr500 (unit u-idiv)) (fr550 (unit u-idiv))) +) + +(dni udivi + "unsigned division reg/immed" + ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) (FR400-MAJOR I-1)) + "udivi$pack $GRi,$s12,$GRk" + (+ pack GRk OP_1F GRi s12) + (sequence () + (c-call VOID "@cpu@_unsigned_integer_divide" + GRi s12 (index-of GRk) 0) + (clobber GRk)) + ((fr400 (unit u-idiv)) + (fr500 (unit u-idiv)) (fr550 (unit u-idiv))) +) + +(dni nudivi + "non excepting unsigned division reg/immed" + ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) NON-EXCEPTING + (MACH simple,tomcat,fr500,fr550,frv)) + "nudivi$pack $GRi,$s12,$GRk" + (+ pack GRk OP_2F GRi s12) + (sequence () + (c-call VOID "@cpu@_unsigned_integer_divide" + GRi s12 (index-of GRk) 1) + (clobber GRk)) + ((fr400 (unit u-idiv)) + (fr500 (unit u-idiv)) (fr550 (unit u-idiv))) +) + +(define-pmacro (multiply-r-simm name signop op comment) + (dni name + (comment) + ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) (FR400-MAJOR I-1)) + (.str name "$pack $GRi,$s12,$GRdoublek") + (+ pack GRdoublek op GRi s12) + (set GRdoublek (mul DI (signop DI GRi) (signop DI s12))) + ((fr400 (unit u-imul)) + (fr500 (unit u-imul)) (fr550 (unit u-imul))) + ) +) + +(multiply-r-simm smuli ext OP_18 "signed multiply reg/immed") +(multiply-r-simm umuli zext OP_1A "unsigned multiply reg/immed") + +(define-pmacro (int-shift-r-simm name op comment) + (dni (.sym name i) + (comment) + ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1)) + (.str (.sym name i) "$pack $GRi,$s12,$GRk") + (+ pack GRk op GRi s12) + (set GRk (name GRi (and s12 #x1f))) + ((fr400 (unit u-integer)) + (fr500 (unit u-integer)) (fr550 (unit u-integer))) + ) +) + +(int-shift-r-simm sll OP_28 "shift left logical reg/immed") +(int-shift-r-simm srl OP_2A "shift right logical reg/immed") +(int-shift-r-simm sra OP_2C "shift right arith reg/immed") + +(dni scani + "scan immediate" + ((UNIT SCAN) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1)) + "scani$pack $GRi,$s12,$GRk" + (+ pack GRk OP_47 GRi s12) + (scan-semantics GRi s12 GRk) + ((fr400 (unit u-integer)) + (fr500 (unit u-integer)) (fr550 (unit u-integer))) +) + +; Format: INT, Logic, Shift cc r-simm +; +(define-pmacro (int-arith-cc-r-simm name operation op comment) + (dni name + (comment) + ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1)) + (.str name "$pack $GRi,$s10,$GRk,$ICCi_1") + (+ pack GRk op GRi ICCi_1 s10) + (sequence ((BI tmp) (QI cc) (SI result)) + (set cc ICCi_1) + (set tmp ((.sym operation -oflag) GRi s10 (const 0))) + (set-v cc tmp) + (set tmp ((.sym operation -cflag) GRi s10 (const 0))) + (set-c cc tmp) + (set result (operation GRi s10)) + (set-z-and-n cc result) + (set GRk result) + (set ICCi_1 cc)) + ((fr400 (unit u-integer)) + (fr500 (unit u-integer)) (fr550 (unit u-integer))) + ) +) + +(int-arith-cc-r-simm addicc add OP_11 "add reg/immed, set icc") +(int-arith-cc-r-simm subicc sub OP_15 "sub reg/immed, set icc") + +(define-pmacro (int-logic-cc-r-simm name op comment) + (dni (.sym name icc) + (comment) + ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1)) + (.str (.sym name icc) "$pack $GRi,$s10,$GRk,$ICCi_1") + (+ pack GRk op GRi ICCi_1 s10) + (sequence ((SI tmp)) + (set tmp (name GRi s10)) + (set GRk tmp) + (set-z-and-n ICCi_1 tmp)) + ((fr400 (unit u-integer)) + (fr500 (unit u-integer)) (fr550 (unit u-integer))) + ) +) + +(int-logic-cc-r-simm and OP_21 "and reg/immed, set icc") +(int-logic-cc-r-simm or OP_23 "or reg/immed, set icc") +(int-logic-cc-r-simm xor OP_25 "xor reg/immed, set icc") + +(define-pmacro (multiply-cc-r-simm name signop op comment) + (dni name + (comment) + ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) (FR400-MAJOR I-1)) + (.str name "$pack $GRi,$s10,$GRdoublek,$ICCi_1") + (+ pack GRdoublek op GRi ICCi_1 s10) + (multiply-cc-semantics signop GRi s10 GRdoublek ICCi_1) + ((fr400 (unit u-imul)) + (fr500 (unit u-imul)) (fr550 (unit u-imul))) + ) +) + +(multiply-cc-r-simm smulicc ext OP_19 "signed multiply reg/immed") +(multiply-cc-r-simm umulicc zext OP_1B "unsigned multiply reg/immed") + +(define-pmacro (int-shift-cc-r-simm name l-r op comment) + (dni (.sym name icc) + (comment) + ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1)) + (.str (.sym name icc) "$pack $GRi,$s10,$GRk,$ICCi_1") + (+ pack GRk op GRi ICCi_1 s10) + (sequence ((WI shift) (SI tmp) (QI cc)) + (set shift (and s10 #x1f)) + (set cc (c-call QI (.str "@cpu@_set_icc_for_shift_" l-r) + GRi shift ICCi_1)) + (set tmp (name GRi shift)) + (set GRk tmp) + (set-z-and-n cc tmp) + (set ICCi_1 cc)) + ((fr400 (unit u-integer)) + (fr500 (unit u-integer)) (fr550 (unit u-integer))) + ) +) + +(int-shift-cc-r-simm sll left OP_29 "shift left logical reg/immed, set icc") +(int-shift-cc-r-simm srl right OP_2B "shift right logical reg/immed, set icc") +(int-shift-cc-r-simm sra right OP_2D "shift right arith reg/immed, set icc") + +(define-pmacro (int-arith-x-r-simm name operation op comment) + (dni name + (comment) + ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1)) + (.str name "$pack $GRi,$s10,$GRk,$ICCi_1") + (+ pack GRk op GRi ICCi_1 s10) + (set GRk ((.sym operation c) GRi s10 (cbit ICCi_1))) + ((fr400 (unit u-integer)) + (fr500 (unit u-integer)) (fr550 (unit u-integer))) + ) +) + +(int-arith-x-r-simm addxi add OP_12 "Add reg/immed, with carry") +(int-arith-x-r-simm subxi sub OP_16 "Sub reg/immed, with carry") + +(define-pmacro (int-arith-x-cc-r-simm name operation op comment) + (dni name + (comment) + ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1)) + (.str name "$pack $GRi,$s10,$GRk,$ICCi_1") + (+ pack GRk op GRi ICCi_1 s10) + (sequence ((WI tmp) (QI cc)) + (set cc ICCi_1) + (set tmp ((.sym operation c) GRi s10 (cbit cc))) + (set-v cc ((.sym operation -oflag) GRi s10 (cbit cc))) + (set-c cc ((.sym operation -cflag) GRi s10 (cbit cc))) + (set-z-and-n cc tmp) + (set GRk tmp) + (set ICCi_1 cc)) + ((fr400 (unit u-integer)) + (fr500 (unit u-integer)) (fr550 (unit u-integer))) + ) +) + +(int-arith-x-cc-r-simm addxicc add OP_13 "Add reg/immed, with carry") +(int-arith-x-cc-r-simm subxicc sub OP_17 "Sub reg/immed, with carry") + +; Byte compare insns + +(dni cmpb + "Compare bytes" + ((UNIT IALL) (FR400-MAJOR I-1) (FR550-MAJOR I-1) (MACH fr400,fr550)) + "cmpb$pack $GRi,$GRj,$ICCi_1" + (+ pack (GRk-null) OP_00 GRi ICCi_1 OPE2_0C GRj) + (sequence ((QI cc)) + (set-n cc (eq (and GRi #xff000000) (and GRj #xff000000))) + (set-z cc (eq (and GRi #x00ff0000) (and GRj #x00ff0000))) + (set-v cc (eq (and GRi #x0000ff00) (and GRj #x0000ff00))) + (set-c cc (eq (and GRi #x000000ff) (and GRj #x000000ff))) + (set ICCi_1 cc)) + ((fr400 (unit u-integer)) (fr550 (unit u-integer))) +) + +(dni cmpba + "OR of Compare bytes" + ((UNIT IALL) (FR400-MAJOR I-1) (FR550-MAJOR I-1) (MACH fr400,fr550)) + "cmpba$pack $GRi,$GRj,$ICCi_1" + (+ pack (GRk-null) OP_00 GRi ICCi_1 OPE2_0D GRj) + (sequence ((QI cc)) + (set cc 0) + (set-c cc + (orif (eq (and GRi #xff000000) (and GRj #xff000000)) + (orif (eq (and GRi #x00ff0000) (and GRj #x00ff0000)) + (orif (eq (and GRi #x0000ff00) + (and GRj #x0000ff00)) + (eq (and GRi #x000000ff) + (and GRj #x000000ff)))))) + (set ICCi_1 cc)) + ((fr400 (unit u-integer)) (fr550 (unit u-integer))) +) + +; Format: Load immediate +; +(dni setlo + "set low order bits" + ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1)) + "setlo$pack $ulo16,$GRklo" + (+ pack GRk OP_3D (misc-null-4) u16) + (set GRklo u16) + ((fr400 (unit u-set-hilo)) + (fr500 (unit u-set-hilo)) (fr550 (unit u-set-hilo))) +) + +(dni sethi + "set high order bits" + ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1)) + "sethi$pack $uhi16,$GRkhi" + (+ pack GRkhi OP_3E (misc-null-4) u16) + (set GRkhi u16) + ((fr400 (unit u-set-hilo)) + (fr500 (unit u-set-hilo)) (fr550 (unit u-set-hilo))) +) + +(dni setlos + "set low order bits and extend sign" + ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1)) + "setlos$pack $slo16,$GRk" + (+ pack GRk OP_3F (misc-null-4) s16) + (set GRk s16) + ((fr400 (unit u-integer)) + (fr500 (unit u-integer)) (fr550 (unit u-integer))) +) + +(define-pmacro (load-gr-r name mode op ope comment) + (dni name + (comment) + ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) (FR400-MAJOR I-2)) + (.str name "$pack @($GRi,$GRj),$GRk") + (+ pack GRk op GRi ope GRj) + (set GRk (c-call mode (.str "@cpu@_read_mem_" mode) pc (add GRi GRj))) + ((fr400 (unit u-gr-load)) + (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) + ) +) + +(load-gr-r ldsb QI OP_02 OPE1_00 "Load signed byte") +(load-gr-r ldub UQI OP_02 OPE1_01 "Load unsigned byte") +(load-gr-r ldsh HI OP_02 OPE1_02 "Load signed half") +(load-gr-r lduh UHI OP_02 OPE1_03 "Load unsigned half") +(load-gr-r ld SI OP_02 OPE1_04 "Load word") + +(define-pmacro (load-fr-r name mode op ope comment) + (dni name + (comment) + ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) (FR400-MAJOR I-2) FR-ACCESS) + (.str name "$pack @($GRi,$GRj),$FRintk") + (+ pack FRintk op GRi ope GRj) + (set FRintk (c-call mode (.str "@cpu@_read_mem_" mode) pc (add GRi GRj))) + ((fr400 (unit u-fr-load)) + (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) + ) +) + +(load-fr-r ldbf UQI OP_02 OPE1_08 "Load byte float") +(load-fr-r ldhf UHI OP_02 OPE1_09 "Load half float") +(load-fr-r ldf SI OP_02 OPE1_0A "Load word float") + +(define-pmacro (load-cpr-r name mode op ope reg attr comment) + (dni name + (comment) + ((UNIT LOAD) (FR500-MAJOR I-2) attr) + (.str name "$pack @($GRi,$GRj),$" reg "k") + (+ pack (.sym reg k) op GRi ope GRj) + (set (.sym reg k) + (c-call mode (.str "@cpu@_read_mem_" mode) pc (add GRi GRj))) + () + ) +) + +(load-cpr-r ldc SI OP_02 OPE1_0D CPR (MACH frv) "Load coprocessor word") + +; These correspond to enumerators in frv-sim.h +(define-pmacro (ne-UQI-size) 0) +(define-pmacro (ne-QI-size) 1) +(define-pmacro (ne-UHI-size) 2) +(define-pmacro (ne-HI-size) 3) +(define-pmacro (ne-SI-size) 4) +(define-pmacro (ne-DI-size) 5) +(define-pmacro (ne-XI-size) 6) + +(define-pmacro (ne-load-semantics base dispix targ idisp size is_float action) + (sequence ((BI do_op)) + (set do_op + (c-call BI "@cpu@_check_non_excepting_load" + (index-of base) dispix (index-of targ) + idisp size is_float)) + (if do_op action)) +) + +(define-pmacro (ne-load-gr-r name mode op ope size comment) + (dni name + (comment) + ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) NON-EXCEPTING + (MACH simple,tomcat,fr500,fr550,frv)) + (.str name "$pack @($GRi,$GRj),$GRk") + (+ pack GRk op GRi ope GRj) + (ne-load-semantics GRi (index-of GRj) GRk 0 size 0 + (set GRk + (c-call mode (.str "@cpu@_read_mem_" mode) + pc (add GRi GRj)))) + ((fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) + ) +) + +(ne-load-gr-r nldsb QI OP_02 OPE1_20 (ne-QI-size) "Load signed byte") +(ne-load-gr-r nldub UQI OP_02 OPE1_21 (ne-UQI-size) "Load unsigned byte") +(ne-load-gr-r nldsh HI OP_02 OPE1_22 (ne-HI-size) "Load signed half") +(ne-load-gr-r nlduh UHI OP_02 OPE1_23 (ne-UHI-size) "Load unsigned half") +(ne-load-gr-r nld SI OP_02 OPE1_24 (ne-SI-size) "Load word") + +(define-pmacro (ne-load-fr-r name mode op ope size comment) + (dni name + (comment) + ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) NON-EXCEPTING FR-ACCESS + (MACH simple,tomcat,fr500,fr550,frv)) + (.str name "$pack @($GRi,$GRj),$FRintk") + (+ pack FRintk op GRi ope GRj) + (ne-load-semantics GRi (index-of GRj) FRintk 0 size 1 + (set FRintk + (c-call mode (.str "@cpu@_read_mem_" mode) + pc (add GRi GRj)))) + ((fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) + ) +) + +(ne-load-fr-r nldbf UQI OP_02 OPE1_28 (ne-UQI-size) "Load byte float") +(ne-load-fr-r nldhf UHI OP_02 OPE1_29 (ne-UHI-size) "Load half float") +(ne-load-fr-r nldf SI OP_02 OPE1_2A (ne-SI-size) "Load word float") + +; Semantics for a load-double insn +; +(define-pmacro (load-double-semantics not_gr mode regtype address arg) + (if (orif not_gr (ne (index-of (.sym regtype doublek)) 0)) + (sequence () + (set address (add GRi arg)) + (set (.sym regtype doublek) + (c-call mode (.str "@cpu@_read_mem_" mode) pc address)))) +) + +(define-pmacro (load-double-r-r + name not_gr mode op ope regtype attr profile comment) + (dni name + (comment) + ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) (FR400-MAJOR I-2) attr) + (.str name "$pack @($GRi,$GRj),$" regtype "doublek") + (+ pack (.sym regtype doublek) op GRi ope GRj) + (sequence ((WI address)) + (load-double-semantics not_gr mode regtype address GRj)) + profile + ) +) + +(load-double-r-r ldd 0 DI OP_02 OPE1_05 GR NA + ((fr400 (unit u-gr-load)) (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) + "Load double word") +(load-double-r-r lddf 1 DF OP_02 OPE1_0B FR FR-ACCESS + ((fr400 (unit u-fr-load)) (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) + "Load double float") +(load-double-r-r lddc 1 DI OP_02 OPE1_0E CPR (MACH frv) () + "Load coprocessor double") + +(define-pmacro (ne-load-double-r-r + name not_gr mode op ope regtype size is_float attr profile + comment) + (dni name + (comment) + ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) NON-EXCEPTING attr + (MACH simple,tomcat,fr500,fr550,frv)) + (.str name "$pack @($GRi,$GRj),$" regtype "doublek") + (+ pack (.sym regtype doublek) op GRi ope GRj) + (sequence ((WI address)) + (ne-load-semantics GRi (index-of GRj) (.sym regtype doublek) + 0 size is_float + (load-double-semantics not_gr mode + regtype + address GRj))) + profile + ) +) + +(ne-load-double-r-r nldd 0 DI OP_02 OPE1_25 GR (ne-DI-size) 0 NA + ((fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) "Load double word") +(ne-load-double-r-r nlddf 1 DF OP_02 OPE1_2B FR (ne-DI-size) 1 FR-ACCESS + ((fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) "Load double float") + +; Semantics for a load-quad insn +; +(define-pmacro (load-quad-semantics regtype address arg) + (sequence () + (set address (add GRi arg)) + (c-call VOID (.str "@cpu@_load_quad_" regtype) + pc address (index-of (.sym regtype k)))) +) + +(define-pmacro (load-quad-r-r name op ope regtype attr profile comment) + (dni name + (comment) + ((UNIT LOAD) (FR500-MAJOR I-2) (MACH frv) attr) + (.str name "$pack @($GRi,$GRj),$" regtype "k") + (+ pack (.sym regtype k) op GRi ope GRj) + (sequence ((WI address)) + (load-quad-semantics regtype address GRj)) + ; TODO regtype-k not referenced for profiling + profile + ) +) + +(load-quad-r-r ldq OP_02 OPE1_06 GR NA ((fr500 (unit u-gr-load))) + "Load quad word") +(load-quad-r-r ldqf OP_02 OPE1_0C FRint FR-ACCESS ((fr500 (unit u-fr-load))) + "Load quad float") +(load-quad-r-r ldqc OP_02 OPE1_0F CPR NA () "Load coprocessor quad") + +(define-pmacro (ne-load-quad-r-r + name op ope regtype size is_float attr profile comment) + (dni name + (comment) + ((UNIT LOAD) (FR500-MAJOR I-2) (MACH frv) NON-EXCEPTING attr) + (.str name "$pack @($GRi,$GRj),$" regtype "k") + (+ pack (.sym regtype k) op GRi ope GRj) + (sequence ((WI address)) + (ne-load-semantics GRi (index-of GRj) (.sym regtype k) + 0 size is_float + (load-quad-semantics regtype address GRj))) + ; TODO regtype-k not referenced for profiling + profile + ) +) + +(ne-load-quad-r-r nldq OP_02 OPE1_26 GR (ne-XI-size) 0 NA + ((fr500 (unit u-gr-load))) "Load quad word") +(ne-load-quad-r-r nldqf OP_02 OPE1_2C FRint (ne-XI-size) 1 FR-ACCESS + ((fr500 (unit u-fr-load))) "Load quad float") + +(define-pmacro (load-gr-u-semantics mode) + (sequence ((UWI address)) + (set address (add GRi GRj)) + (set GRk (c-call mode (.str "@cpu@_read_mem_" mode) pc address)) + (if (ne (index-of GRi) (index-of GRk)) + (sequence () + (set GRi address) + (c-call VOID "@cpu@_force_update")))) +) + +(define-pmacro (load-gr-u name mode op ope comment) + (dni name + (comment) + ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) (FR400-MAJOR I-2)) + (.str name "$pack @($GRi,$GRj),$GRk") + (+ pack GRk op GRi ope GRj) + (load-gr-u-semantics mode) + ((fr400 (unit u-gr-load)) + (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) + ) +) + +(load-gr-u ldsbu QI OP_02 OPE1_10 "Load signed byte, update index") +(load-gr-u ldubu UQI OP_02 OPE1_11 "Load unsigned byte, update index") +(load-gr-u ldshu HI OP_02 OPE1_12 "Load signed half, update index") +(load-gr-u lduhu UHI OP_02 OPE1_13 "Load unsigned half, update index") +(load-gr-u ldu SI OP_02 OPE1_14 "Load word, update index") + +(define-pmacro (ne-load-gr-u name mode op ope size comment) + (dni name + (comment) + ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) NON-EXCEPTING + (MACH simple,tomcat,fr500,fr550,frv)) + (.str name "$pack @($GRi,$GRj),$GRk") + (+ pack GRk op GRi ope GRj) + (ne-load-semantics GRi (index-of GRj) GRk 0 size 0 (load-gr-u-semantics mode)) + ((fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) + ) +) + +(ne-load-gr-u nldsbu QI OP_02 OPE1_30 (ne-QI-size) "Load signed byte, update index") +(ne-load-gr-u nldubu UQI OP_02 OPE1_31 (ne-UQI-size) "Load unsigned byte, update index") +(ne-load-gr-u nldshu HI OP_02 OPE1_32 (ne-HI-size) "Load signed half, update index") +(ne-load-gr-u nlduhu UHI OP_02 OPE1_33 (ne-UHI-size) "Load unsigned half, update index") +(ne-load-gr-u nldu SI OP_02 OPE1_34 (ne-SI-size) "Load word, update index") + +(define-pmacro (load-non-gr-u-semantics mode regtype) + (sequence ((UWI address)) + (set address (add GRi GRj)) + (set (.sym regtype k) + (c-call mode (.str "@cpu@_read_mem_" mode) pc address)) + (set GRi address) + (c-call VOID "@cpu@_force_update")) +) + +(define-pmacro (load-fr-u name mode op ope comment) + (dni name + (comment) + ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) (FR400-MAJOR I-2) FR-ACCESS) + (.str name "$pack @($GRi,$GRj),$FRintk") + (+ pack FRintk op GRi ope GRj) + (load-non-gr-u-semantics mode FRint) + ((fr400 (unit u-fr-load)) + (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) + ) +) + +(load-fr-u ldbfu UQI OP_02 OPE1_18 "Load byte float, update index") +(load-fr-u ldhfu UHI OP_02 OPE1_19 "Load half float, update index") +(load-fr-u ldfu SI OP_02 OPE1_1A "Load word float, update index") + +(define-pmacro (load-cpr-u name mode op ope comment) + (dni name + (comment) + ((UNIT LOAD) (FR500-MAJOR I-2) (MACH frv)) + (.str name "$pack @($GRi,$GRj),$CPRk") + (+ pack CPRk op GRi ope GRj) + (load-non-gr-u-semantics mode CPR) + () + ) +) + +(load-cpr-u ldcu SI OP_02 OPE1_1D "Load coprocessor word float,update index") + +(define-pmacro (ne-load-non-gr-u name mode op ope regtype size comment) + (dni name + (comment) + ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) NON-EXCEPTING FR-ACCESS + (MACH simple,tomcat,fr500,fr550,frv)) + (.str name "$pack @($GRi,$GRj),$" regtype "k") + (+ pack (.sym regtype k) op GRi ope GRj) + (ne-load-semantics GRi (index-of GRj) (.sym regtype k) 0 size 1 + (load-non-gr-u-semantics mode regtype)) + ((fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) + ) +) + +(ne-load-non-gr-u nldbfu UQI OP_02 OPE1_38 FRint (ne-UQI-size) "Load byte float, update index") +(ne-load-non-gr-u nldhfu UHI OP_02 OPE1_39 FRint (ne-UHI-size) "Load half float, update index") +(ne-load-non-gr-u nldfu SI OP_02 OPE1_3A FRint (ne-SI-size) "Load word float, update index") + +(define-pmacro (load-double-gr-u-semantics) + (sequence ((WI address)) + (load-double-semantics 0 DI GR address GRj) + (if (ne (index-of GRi) (index-of GRdoublek)) + (sequence () + (set GRi address) + (c-call VOID "@cpu@_force_update")))) +) + +(define-pmacro (load-double-gr-u name op ope comment) + (dni name + (comment) + ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) (FR400-MAJOR I-2)) + (.str name "$pack @($GRi,$GRj),$GRdoublek") + (+ pack GRdoublek op GRi ope GRj) + (load-double-gr-u-semantics) + ((fr400 (unit u-gr-load)) + (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) + ) +) + +(load-double-gr-u lddu OP_02 OPE1_15 "Load double word, update index") + +(define-pmacro (ne-load-double-gr-u name op ope size comment) + (dni name + (comment) + ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) NON-EXCEPTING + (MACH simple,tomcat,fr500,fr550,frv)) + (.str name "$pack @($GRi,$GRj),$GRdoublek") + (+ pack GRdoublek op GRi ope GRj) + (ne-load-semantics GRi (index-of GRj) GRdoublek 0 size 0 + (load-double-gr-u-semantics)) + ((fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) + + ) +) + +(ne-load-double-gr-u nlddu OP_02 OPE1_35 (ne-DI-size) "Load double word, update index") + +(define-pmacro (load-double-non-gr-u-semantics mode regtype) + (sequence ((WI address)) + (load-double-semantics 1 mode regtype address GRj) + (set GRi address) + (c-call VOID "@cpu@_force_update")) +) + +(define-pmacro (load-double-non-gr-u + name mode op ope regtype attr profile comment) + (dni name + (comment) + ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) (FR400-MAJOR I-2) attr) + (.str name "$pack @($GRi,$GRj),$" regtype "doublek") + (+ pack (.sym regtype doublek) op GRi ope GRj) + (load-double-non-gr-u-semantics mode regtype) + profile + ) +) + +(load-double-non-gr-u lddfu DF OP_02 OPE1_1B FR FR-ACCESS + ((fr400 (unit u-fr-load)) (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) + "Load double float, update index") +(load-double-non-gr-u lddcu DI OP_02 OPE1_1E CPR (MACH frv) + () "Load coprocessor double float, update index") + +(define-pmacro (ne-load-double-non-gr-u name mode op ope regtype size comment) + (dni name + (comment) + ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) NON-EXCEPTING FR-ACCESS + (MACH simple,tomcat,fr500,fr550,frv)) + (.str name "$pack @($GRi,$GRj),$" regtype "doublek") + (+ pack (.sym regtype doublek) op GRi ope GRj) + (ne-load-semantics GRi (index-of GRj) (.sym regtype doublek) 0 size 1 + (load-double-non-gr-u-semantics mode regtype)) + ((fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) + ) +) + +(ne-load-double-non-gr-u nlddfu DF OP_02 OPE1_3B FR (ne-DI-size) "Load double float, update index") + +(define-pmacro (load-quad-gr-u-semantics) + (sequence ((WI address)) + (load-quad-semantics GR address GRj) + (if (ne (index-of GRi) (index-of GRk)) + (sequence () + (set GRi address) + (c-call VOID "@cpu@_force_update")))) +) + +(define-pmacro (load-quad-gr-u name op ope comment) + (dni name + (comment) + ((UNIT LOAD) (FR500-MAJOR I-2) (MACH frv)) + (.str name "$pack @($GRi,$GRj),$GRk") + (+ pack GRk op GRi ope GRj) + (load-quad-gr-u-semantics) + ; TODO - GRk not referenced here for profiling + ((fr500 (unit u-gr-load))) + ) +) + +(load-quad-gr-u ldqu OP_02 OPE1_16 "Load quad word, update index") + +(define-pmacro (ne-load-quad-gr-u name op ope size comment) + (dni name + (comment) + ((UNIT LOAD) (FR500-MAJOR I-2) (MACH frv) NON-EXCEPTING) + (.str name "$pack @($GRi,$GRj),$GRk") + (+ pack GRk op GRi ope GRj) + (ne-load-semantics GRi (index-of GRj) GRk 0 size 0 + (load-quad-gr-u-semantics)) + ; TODO - GRk not referenced here for profiling + ((fr500 (unit u-gr-load))) + ) +) + +(ne-load-quad-gr-u nldqu OP_02 OPE1_36 (ne-XI-size) "Load quad word, update index") + +(define-pmacro (load-quad-non-gr-u-semantics regtype) + (sequence ((WI address)) + (load-quad-semantics regtype address GRj) + (set GRi address) + (c-call VOID "@cpu@_force_update")) +) + +(define-pmacro (load-quad-non-gr-u name op ope regtype attr profile comment) + (dni name + (comment) + ((UNIT LOAD) (FR500-MAJOR I-2) (MACH frv) attr) + (.str name "$pack @($GRi,$GRj),$" regtype "k") + (+ pack (.sym regtype k) op GRi ope GRj) + (load-quad-non-gr-u-semantics regtype) + profile + ) +) + +(load-quad-non-gr-u ldqfu OP_02 OPE1_1C FRint FR-ACCESS + ((fr500 (unit u-fr-load))) "Load quad float, update index") +(load-quad-non-gr-u ldqcu OP_02 OPE1_1F CPR NA + () "Load coprocessor quad word, update index") + +(define-pmacro (ne-load-quad-non-gr-u name op ope regtype size comment) + (dni name + (comment) + ((UNIT LOAD) (FR500-MAJOR I-2) (MACH frv) NON-EXCEPTING FR-ACCESS) + (.str name "$pack @($GRi,$GRj),$" regtype "k") + (+ pack (.sym regtype k) op GRi ope GRj) + (ne-load-semantics GRi (index-of GRj) (.sym regtype k) 0 size 1 + (load-quad-non-gr-u-semantics regtype)) + ((fr500 (unit u-fr-load))) + ) +) + +(ne-load-quad-non-gr-u nldqfu OP_02 OPE1_3C FRint (ne-XI-size) "Load quad float,update index") + +(define-pmacro (load-r-simm name mode op regtype attr profile comment) + (dni name + (comment) + ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) (FR400-MAJOR I-2) attr) + (.str name "$pack @($GRi,$d12),$" regtype "k") + (+ pack (.sym regtype k) op GRi d12) + (set (.sym regtype k) + (c-call mode (.str "@cpu@_read_mem_" mode) pc (add GRi d12))) + profile + ) +) + +(load-r-simm ldsbi QI OP_30 GR NA + ((fr400 (unit u-gr-load)) (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) + "Load signed byte") +(load-r-simm ldshi HI OP_31 GR NA + ((fr400 (unit u-gr-load)) (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) + "Load signed half") +(load-r-simm ldi SI OP_32 GR NA + ((fr400 (unit u-gr-load)) (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) + "Load word") +(load-r-simm ldubi UQI OP_35 GR NA + ((fr400 (unit u-gr-load)) (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) + "Load unsigned byte") +(load-r-simm lduhi UHI OP_36 GR NA + ((fr400 (unit u-gr-load)) (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) + "Load unsigned half") + +(load-r-simm ldbfi UQI OP_38 FRint FR-ACCESS + ((fr400 (unit u-fr-load)) (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) + "Load byte float") +(load-r-simm ldhfi UHI OP_39 FRint FR-ACCESS + ((fr400 (unit u-fr-load)) (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) + "Load half float") +(load-r-simm ldfi SI OP_3A FRint FR-ACCESS + ((fr400 (unit u-fr-load)) (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) + "Load word float") + +(define-pmacro (ne-load-r-simm + name mode op regtype size is_float attr profile comment) + (dni name + (comment) + ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) NON-EXCEPTING attr + (MACH simple,tomcat,fr500,fr550,frv)) + (.str name "$pack @($GRi,$d12),$" regtype "k") + (+ pack (.sym regtype k) op GRi d12) + (ne-load-semantics GRi -1 (.sym regtype k) d12 size is_float + (set (.sym regtype k) + (c-call mode (.str "@cpu@_read_mem_" mode) + pc (add GRi d12)))) + profile + ) +) + +(ne-load-r-simm nldsbi QI OP_40 GR (ne-QI-size) 0 NA + ((fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) "Load signed byte") +(ne-load-r-simm nldubi UQI OP_41 GR (ne-UQI-size) 0 NA + ((fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) "Load unsigned byte") +(ne-load-r-simm nldshi HI OP_42 GR (ne-HI-size) 0 NA + ((fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) "Load signed half") +(ne-load-r-simm nlduhi UHI OP_43 GR (ne-UHI-size) 0 NA + ((fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) "Load unsigned half") +(ne-load-r-simm nldi SI OP_44 GR (ne-SI-size) 0 NA + ((fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) "Load word") + +(ne-load-r-simm nldbfi UQI OP_48 FRint (ne-UQI-size) 1 FR-ACCESS + ((fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) "Load byte float") +(ne-load-r-simm nldhfi UHI OP_49 FRint (ne-UHI-size) 1 FR-ACCESS + ((fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) "Load half float") +(ne-load-r-simm nldfi SI OP_4A FRint (ne-SI-size) 1 FR-ACCESS + ((fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) "Load word float") + +(define-pmacro (load-double-r-simm + name not_gr mode op regtype attr profile comment) + (dni name + (comment) + ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) (FR400-MAJOR I-2) attr) + (.str name "$pack @($GRi,$d12),$" regtype "doublek") + (+ pack (.sym regtype doublek) op GRi d12) + (sequence ((WI address)) + (load-double-semantics not_gr mode regtype address d12)) + profile + ) +) + +(load-double-r-simm lddi 0 DI OP_33 GR NA + ((fr400 (unit u-gr-load)) (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) + "Load double word") +(load-double-r-simm lddfi 1 DF OP_3B FR FR-ACCESS + ((fr400 (unit u-fr-load)) (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) + "Load double float") + +(define-pmacro (ne-load-double-r-simm + name not_gr mode op regtype size is_float attr profile comment) + (dni name + (comment) + ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) NON-EXCEPTING attr + (MACH simple,tomcat,fr500,fr550,frv)) + (.str name "$pack @($GRi,$d12),$" regtype "doublek") + (+ pack (.sym regtype doublek) op GRi d12) + (sequence ((WI address)) + (ne-load-semantics GRi -1 (.sym regtype doublek) + d12 size is_float + (load-double-semantics not_gr mode + regtype + address d12))) + profile + ) +) + +(ne-load-double-r-simm nlddi 0 DI OP_45 GR (ne-DI-size) 0 NA + ((fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) "Load double word") +(ne-load-double-r-simm nlddfi 1 DF OP_4B FR (ne-DI-size) 1 FR-ACCESS + ((fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) "Load double float") + +(define-pmacro (load-quad-r-simm name op regtype attr profile comment) + (dni name + (comment) + ((UNIT LOAD) (FR500-MAJOR I-2) (MACH frv) attr) + (.str name "$pack @($GRi,$d12),$" regtype "k") + (+ pack (.sym regtype k) op GRi d12) + (sequence ((WI address)) + (load-quad-semantics regtype address d12)) + profile + ) +) + +(load-quad-r-simm ldqi OP_34 GR NA + ((fr500 (unit u-gr-load))) "Load quad word") +(load-quad-r-simm ldqfi OP_3C FRint FR-ACCESS + ((fr500 (unit u-fr-load))) "Load quad float") + +(define-pmacro (ne-load-quad-r-simm + name op regtype size is_float attr profile comment) + (dni name + (comment) + ((UNIT LOAD) (FR500-MAJOR I-2) (MACH frv) NON-EXCEPTING attr) + (.str name "$pack @($GRi,$d12),$" regtype "k") + (+ pack (.sym regtype k) op GRi d12) + (sequence ((WI address)) + (ne-load-semantics GRi -1 (.sym regtype k) d12 size is_float + (load-quad-semantics regtype address d12))) + profile + ) +) + +(ne-load-quad-r-simm nldqfi OP_4C FRint (ne-XI-size) 1 FR-ACCESS + ((fr500 (unit u-fr-load))) "Load quad float") + +(define-pmacro (store-r-r name mode op ope reg attr profile comment) + (dni name + (comment) + ((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3) (FR400-MAJOR I-3) attr) + (.str name "$pack $" reg "k,@($GRi,$GRj)") + (+ pack (.sym reg k) op GRi ope GRj) + (c-call VOID (.str "@cpu@_write_mem_" mode) + pc (add GRi GRj) (.sym reg k)) + profile + ) +) + +(store-r-r stb QI OP_03 OPE1_00 GR NA + ((fr400 (unit u-gr-store)) (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) + "Store unsigned byte") +(store-r-r sth HI OP_03 OPE1_01 GR NA + ((fr400 (unit u-gr-store)) (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) + "Store unsigned half") +(store-r-r st SI OP_03 OPE1_02 GR NA + ((fr400 (unit u-gr-store)) (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) + "Store word") + +(store-r-r stbf QI OP_03 OPE1_08 FRint FR-ACCESS + ((fr400 (unit u-fr-store)) (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) + "Store byte float") +(store-r-r sthf HI OP_03 OPE1_09 FRint FR-ACCESS + ((fr400 (unit u-fr-store)) (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) + "Store half float") +(store-r-r stf SI OP_03 OPE1_0A FRint FR-ACCESS + ((fr400 (unit u-fr-store)) (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) + "Store word float") + +(store-r-r stc SI OP_03 OPE1_25 CPR (MACH frv) () "Store coprocessor word") + +(define-pmacro (r-store name mode op ope reg size is_float profile comment) + (dni name + (comment) + ((UNIT STORE) (FR500-MAJOR I-3) (MACH frv)) + (.str name "$pack $" reg "k,@($GRi,$GRj)") + (+ pack (.sym reg k) op GRi ope GRj) + (sequence ((WI address)) + (set address (add GRi GRj)) + (c-call VOID (.str "@cpu@_write_mem_" mode) + pc address (.sym reg k)) + (c-call VOID "@cpu@_check_recovering_store" + address (index-of (.sym reg k)) size is_float)) + profile + ) +) + +(r-store rstb QI OP_03 OPE1_20 GR 1 0 + ((fr500 (unit u-gr-r-store))) "Store unsigned byte") +(r-store rsth HI OP_03 OPE1_21 GR 2 0 + ((fr500 (unit u-gr-r-store))) "Store unsigned half") +(r-store rst SI OP_03 OPE1_22 GR 4 0 + ((fr500 (unit u-gr-r-store))) "Store word") + +(r-store rstbf QI OP_03 OPE1_28 FRint 1 1 + ((fr500 (unit u-fr-r-store))) "Store byte float") +(r-store rsthf HI OP_03 OPE1_29 FRint 2 1 + ((fr500 (unit u-fr-r-store))) "Store half float") +(r-store rstf SI OP_03 OPE1_2A FRint 4 1 + ((fr500 (unit u-fr-r-store))) "Store word float") + +; Semantics for a store-double insn +; +(define-pmacro (store-double-semantics mode regtype address arg) + (sequence () + (set address (add GRi arg)) + (c-call VOID (.str "@cpu@_write_mem_" mode) + pc address (.sym regtype doublek))) +) + +(define-pmacro (store-double-r-r name mode op ope regtype attr profile comment) + (dni name + (comment) + ((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3) (FR400-MAJOR I-3) attr) + (.str name "$pack $" regtype "doublek,@($GRi,$GRj)") + (+ pack (.sym regtype doublek) op GRi ope GRj) + (sequence ((WI address)) + (store-double-semantics mode regtype address GRj)) + profile + ) +) + +(store-double-r-r std DI OP_03 OPE1_03 GR NA + ((fr400 (unit u-gr-store)) (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) + "Store double word") +(store-double-r-r stdf DF OP_03 OPE1_0B FR FR-ACCESS + ((fr400 (unit u-fr-store)) (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) + "Store double float") + +(store-double-r-r stdc DI OP_03 OPE1_26 CPR (MACH frv) + () "Store coprocessor double word") + +(define-pmacro (r-store-double + name mode op ope regtype is_float attr profile comment) + (dni name + (comment) + ((UNIT STORE) (FR500-MAJOR I-3) (MACH frv) attr) + (.str name "$pack $" regtype "doublek,@($GRi,$GRj)") + (+ pack (.sym regtype doublek) op GRi ope GRj) + (sequence ((WI address)) + (store-double-semantics mode regtype address GRj) + (c-call VOID "@cpu@_check_recovering_store" + address (index-of (.sym regtype doublek)) 8 is_float)) + profile + ) +) + +(r-store-double rstd DI OP_03 OPE1_23 GR 0 NA + ((fr500 (unit u-gr-r-store))) "Store double word") +(r-store-double rstdf DF OP_03 OPE1_2B FR 1 FR-ACCESS + ((fr500 (unit u-fr-r-store))) "Store double float") + +; Semantics for a store-quad insn +; +(define-pmacro (store-quad-semantics regtype address arg) + (sequence () + (set address (add GRi arg)) + (c-call VOID (.str "@cpu@_store_quad_" regtype) + pc address (index-of (.sym regtype k)))) +) + +(define-pmacro (store-quad-r-r name op ope regtype attr profile comment) + (dni name + (comment) + ((UNIT STORE) (FR500-MAJOR I-3) (MACH frv) attr) + (.str name "$pack $" regtype "k,@($GRi,$GRj)") + (+ pack (.sym regtype k) op GRi ope GRj) + (sequence ((WI address)) + (store-quad-semantics regtype address GRj)) + profile + ) +) + +(store-quad-r-r stq OP_03 OPE1_04 GR NA + ((fr500 (unit u-gr-store))) "Store quad word") +(store-quad-r-r stqf OP_03 OPE1_0C FRint FR-ACCESS + ((fr500 (unit u-fr-store))) + "Store quad float") +(store-quad-r-r stqc OP_03 OPE1_27 CPR NA + () "Store coprocessor quad word") + +(define-pmacro (r-store-quad name op ope regtype is_float attr profile comment) + (dni name + (comment) + ((UNIT STORE) (FR500-MAJOR I-3) (MACH frv) attr) + (.str name "$pack $" regtype "k,@($GRi,$GRj)") + (+ pack (.sym regtype k) op GRi ope GRj) + (sequence ((WI address)) + (store-quad-semantics regtype address GRj) + (c-call VOID "@cpu@_check_recovering_store" + address (index-of (.sym regtype k)) 16 is_float)) + profile + ) +) + +(r-store-quad rstq OP_03 OPE1_24 GR 0 NA + ((fr500 (unit u-gr-r-store))) "Store quad word") +(r-store-quad rstqf OP_03 OPE1_2C FRint 1 FR-ACCESS + ((fr500 (unit u-fr-r-store))) "Store quad float") + +(define-pmacro (store-r-r-u name mode op ope regtype attr profile comment) + (dni name + (comment) + ((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3) (FR400-MAJOR I-3) attr) + (.str name "$pack $" regtype "k,@($GRi,$GRj)") + (+ pack (.sym regtype k) op GRi ope GRj) + (sequence ((UWI address)) + (set address (add GRi GRj)) + (c-call VOID (.str "@cpu@_write_mem_" mode) + pc address (.sym regtype k)) + (set GRi address)) + profile + ) +) + +(store-r-r-u stbu QI OP_03 OPE1_10 GR NA + ((fr400 (unit u-gr-store)) (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) + "Store unsigned byte, update index") +(store-r-r-u sthu HI OP_03 OPE1_11 GR NA + ((fr400 (unit u-gr-store)) (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) + "Store unsigned half, update index") +(store-r-r-u stu WI OP_03 OPE1_12 GR NA + ((fr400 (unit u-gr-store)) (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) + "Store word, update index") + +(store-r-r-u stbfu QI OP_03 OPE1_18 FRint FR-ACCESS + ((fr400 (unit u-fr-store)) (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) + "Store byte float, update index") +(store-r-r-u sthfu HI OP_03 OPE1_19 FRint FR-ACCESS + ((fr400 (unit u-fr-store)) (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) + "Store half float, update index") +(store-r-r-u stfu SI OP_03 OPE1_1A FRint FR-ACCESS + ((fr400 (unit u-fr-store)) (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) + "Store word float, update index") + +(store-r-r-u stcu SI OP_03 OPE1_2D CPR (MACH frv) () + "Store coprocessor word, update index") + +(define-pmacro (store-double-r-r-u + name mode op ope regtype attr profile comment) + (dni name + (comment) + ((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3) (FR400-MAJOR I-3) attr) + (.str name "$pack $" regtype "doublek,@($GRi,$GRj)") + (+ pack (.sym regtype doublek) op GRi ope GRj) + (sequence ((WI address)) + (store-double-semantics mode regtype address GRj) + (set GRi address)) + profile + ) +) + +(store-double-r-r-u stdu DI OP_03 OPE1_13 GR NA + ((fr400 (unit u-gr-store)) (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) + "Store double word, update index") +(store-double-r-r-u stdfu DF OP_03 OPE1_1B FR FR-ACCESS + ((fr400 (unit u-fr-store)) (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) + "Store double float,update index") +(store-double-r-r-u stdcu DI OP_03 OPE1_2E CPR (MACH frv) () + "Store coprocessor double word, update index") + +(define-pmacro (store-quad-r-r-u name op ope regtype attr profile comment) + (dni name + (comment) + ((UNIT STORE) (FR500-MAJOR I-3) (MACH frv) attr) + (.str name "$pack $" regtype "k,@($GRi,$GRj)") + (+ pack (.sym regtype k) op GRi ope GRj) + (sequence ((WI address)) + (store-quad-semantics regtype address GRj) + (set GRi address)) + profile + ) +) + +(store-quad-r-r-u stqu OP_03 OPE1_14 GR NA + ((fr500 (unit u-gr-store))) + "Store quad word, update index") +(store-quad-r-r-u stqfu OP_03 OPE1_1C FRint FR-ACCESS + ((fr500 (unit u-fr-store))) + "Store quad float, update index") +(store-quad-r-r-u stqcu OP_03 OPE1_2F CPR NA () + "Store coprocessor quad word, update index") + +(define-pmacro (conditional-load name mode op ope regtype profile comment) + (dni name + (comment) + ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) (FR400-MAJOR I-2) CONDITIONAL) + (.str name "$pack @($GRi,$GRj),$" regtype "k,$CCi,$cond") + (+ pack (.sym regtype k) op GRi CCi cond ope GRj) + (if (eq CCi (or cond 2)) + (set (.sym regtype k) + (c-call mode (.str "@cpu@_read_mem_" mode) pc (add GRi GRj)))) + profile + ) +) + +(conditional-load cldsb QI OP_5E OPE4_0 GR + ((fr400 (unit u-gr-load)) (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) + "Load signed byte") +(conditional-load cldub UQI OP_5E OPE4_1 GR + ((fr400 (unit u-gr-load)) (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) + "Load unsigned byte") +(conditional-load cldsh HI OP_5E OPE4_2 GR + ((fr400 (unit u-gr-load)) (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) + "Load signed half") +(conditional-load clduh UHI OP_5E OPE4_3 GR + ((fr400 (unit u-gr-load)) (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) + "Load unsigned half") +(conditional-load cld SI OP_5F OPE4_0 GR + ((fr400 (unit u-gr-load)) (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) + "Load word") + +(conditional-load cldbf UQI OP_60 OPE4_0 FRint + ((fr400 (unit u-fr-load)) (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) + "Load byte float") +(conditional-load cldhf UHI OP_60 OPE4_1 FRint + ((fr400 (unit u-fr-load)) (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) + "Load half float") +(conditional-load cldf SI OP_60 OPE4_2 FRint + ((fr400 (unit u-fr-load)) (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) + "Load word float") + +(define-pmacro (conditional-load-double + name not_gr mode op ope regtype attr profile comment) + (dni name + (comment) + ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) (FR400-MAJOR I-2) CONDITIONAL attr) + (.str name "$pack @($GRi,$GRj),$" regtype "doublek,$CCi,$cond") + (+ pack (.sym regtype doublek) op GRi CCi cond ope GRj) + (if (eq CCi (or cond 2)) + (sequence ((WI address)) + (load-double-semantics not_gr mode regtype address GRj))) + profile + ) +) + +(conditional-load-double cldd 0 DI OP_5F OPE4_1 GR NA + ((fr400 (unit u-gr-load)) (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) + "Load double word") +(conditional-load-double clddf 1 DF OP_60 OPE4_3 FR FR-ACCESS + ((fr400 (unit u-gr-load)) (fr500 (unit u-gr-load)) (fr550 (unit u-fr-load))) + "Load double float") + +(dni cldq + "conditional load quad integer" + ((UNIT LOAD) (FR500-MAJOR I-2) (MACH frv) CONDITIONAL) + "cldq$pack @($GRi,$GRj),$GRk,$CCi,$cond" + (+ pack GRk OP_5F GRi CCi cond OPE4_2 GRj) + (if (eq CCi (or cond 2)) + (sequence ((WI address)) + (load-quad-semantics GR address GRj))) + ((fr500 (unit u-gr-load))) +) + +(define-pmacro (conditional-load-gr-u name mode op ope comment) + (dni name + (comment) + ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) (FR400-MAJOR I-2) CONDITIONAL) + (.str name "$pack @($GRi,$GRj),$GRk,$CCi,$cond") + (+ pack GRk op GRi CCi cond ope GRj) + (if (eq CCi (or cond 2)) + (sequence ((WI address)) + (set address (add GRi GRj)) + (set GRk + (c-call mode (.str "@cpu@_read_mem_" mode) + pc address)) + (if (ne (index-of GRi) (index-of GRk)) + (set GRi address)))) + ((fr400 (unit u-gr-load)) + (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) + ) +) + +(conditional-load-gr-u cldsbu QI OP_61 OPE4_0 "Load signed byte, update") +(conditional-load-gr-u cldubu UQI OP_61 OPE4_1 "Load unsigned byte, update") +(conditional-load-gr-u cldshu HI OP_61 OPE4_2 "Load signed half, update") +(conditional-load-gr-u clduhu UHI OP_61 OPE4_3 "Load unsigned half, update") +(conditional-load-gr-u cldu SI OP_62 OPE4_0 "Load word, update") + +(define-pmacro (conditional-load-non-gr-u name mode op ope regtype comment) + (dni name + (comment) + ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) (FR400-MAJOR I-2) CONDITIONAL FR-ACCESS) + (.str name "$pack @($GRi,$GRj),$" regtype "k,$CCi,$cond") + (+ pack (.sym regtype k) op GRi CCi cond ope GRj) + (if (eq CCi (or cond 2)) + (sequence ((WI address)) + (set address (add GRi GRj)) + (set (.sym regtype k) + (c-call mode (.str "@cpu@_read_mem_" mode) + pc address)) + (set GRi address))) + ((fr400 (unit u-fr-load)) + (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) + ) +) + +(conditional-load-non-gr-u cldbfu UQI OP_63 OPE4_0 FRint "Load byte float, update") +(conditional-load-non-gr-u cldhfu UHI OP_63 OPE4_1 FRint "Load half float, update") +(conditional-load-non-gr-u cldfu SI OP_63 OPE4_2 FRint "Load word float, update") + + +(dni clddu + "Load double word, update" + ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) (FR400-MAJOR I-2) CONDITIONAL) + "clddu$pack @($GRi,$GRj),$GRdoublek,$CCi,$cond" + (+ pack GRdoublek OP_62 GRi CCi cond OPE4_1 GRj) + (if (eq CCi (or cond 2)) + (sequence ((WI address)) + (load-double-semantics 0 DI GR address GRj) + (if (ne (index-of GRi) (index-of GRdoublek)) + (set GRi address)))) + ((fr400 (unit u-gr-load)) + (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) +) + +(dni clddfu + "Load double float, update" + ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) (FR400-MAJOR I-2) CONDITIONAL FR-ACCESS) + "clddfu$pack @($GRi,$GRj),$FRdoublek,$CCi,$cond" + (+ pack FRdoublek OP_63 GRi CCi cond OPE4_3 GRj) + (if (eq CCi (or cond 2)) + (sequence ((WI address)) + (load-double-semantics 1 DF FR address GRj) + (set GRi address))) + ((fr400 (unit u-fr-load)) + (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) +) + +(dni cldqu + "conditional load quad integer and update index" + ((UNIT LOAD) (FR500-MAJOR I-2) (MACH frv) CONDITIONAL) + "cldqu$pack @($GRi,$GRj),$GRk,$CCi,$cond" + (+ pack GRk OP_62 GRi CCi cond OPE4_2 GRj) + (if (eq CCi (or cond 2)) + (sequence ((WI address)) + (load-quad-semantics GR address GRj) + (if (ne (index-of GRi) (index-of GRk)) + (set GRi address)))) + ((fr500 (unit u-gr-load))) +) + +(define-pmacro (conditional-store name mode op ope regtype profile comment) + (dni name + (comment) + ((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3) (FR400-MAJOR I-3) CONDITIONAL) + (.str name "$pack $" regtype "k,@($GRi,$GRj),$CCi,$cond") + (+ pack (.sym regtype k) op GRi CCi cond ope GRj) + (if (eq CCi (or cond 2)) + (c-call VOID (.str "@cpu@_write_mem_" mode) + pc (add GRi GRj) (.sym regtype k))) + profile + ) +) + +(conditional-store cstb QI OP_64 OPE4_0 GR + ((fr400 (unit u-gr-store)) (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) + "Store unsigned byte") +(conditional-store csth HI OP_64 OPE4_1 GR + ((fr400 (unit u-gr-store)) (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) + "Store unsigned half") +(conditional-store cst SI OP_64 OPE4_2 GR + ((fr400 (unit u-gr-store)) (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) + "Store word") + +(conditional-store cstbf QI OP_66 OPE4_0 FRint + ((fr400 (unit u-fr-store)) (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) + "Store byte float") +(conditional-store csthf HI OP_66 OPE4_1 FRint + ((fr400 (unit u-fr-store)) (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) + "Store half float") +(conditional-store cstf SI OP_66 OPE4_2 FRint + ((fr400 (unit u-fr-store)) (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) + "Store word float") + +(define-pmacro (conditional-store-double + name mode op ope regtype attr profile comment) + (dni name + (comment) + ((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3) (FR400-MAJOR I-3) CONDITIONAL attr) + (.str name "$pack $" regtype "doublek,@($GRi,$GRj),$CCi,$cond") + (+ pack (.sym regtype doublek) op GRi CCi cond ope GRj) + (if (eq CCi (or cond 2)) + (sequence ((WI address)) + (store-double-semantics mode regtype address GRj))) + profile + ) +) + +(conditional-store-double cstd DI OP_64 OPE4_3 GR NA + ((fr400 (unit u-gr-store)) (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) + "Store double word") +(conditional-store-double cstdf DF OP_66 OPE4_3 FR FR-ACCESS + ((fr400 (unit u-fr-store)) (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) + "Store double float") + +(dni cstq + "conditionally store quad word" + ((UNIT STORE) (FR500-MAJOR I-3) (MACH frv) CONDITIONAL) + "cstq$pack $GRk,@($GRi,$GRj),$CCi,$cond" + (+ pack GRk OP_65 GRi CCi cond OPE4_0 GRj) + (if (eq CCi (or cond 2)) + (sequence ((WI address)) + (store-quad-semantics GR address GRj))) + ((fr500 (unit u-gr-store))) +) + +(define-pmacro (conditional-store-u + name mode op ope regtype attr profile comment) + (dni name + (comment) + ((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3) (FR400-MAJOR I-3) CONDITIONAL attr) + (.str name "$pack $" regtype "k,@($GRi,$GRj),$CCi,$cond") + (+ pack (.sym regtype k) op GRi CCi cond ope GRj) + (if (eq CCi (or cond 2)) + (sequence ((WI address)) + (set address (add GRi GRj)) + (c-call VOID (.str "@cpu@_write_mem_" mode) + pc address (.sym regtype k)) + (set GRi address))) + profile + ) +) + +(conditional-store-u cstbu QI OP_67 OPE4_0 GR NA + ((fr400 (unit u-gr-store)) (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) + "Store unsigned byte, update index") +(conditional-store-u csthu HI OP_67 OPE4_1 GR NA + ((fr400 (unit u-gr-store)) (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) + "Store unsigned half, update index") +(conditional-store-u cstu SI OP_67 OPE4_2 GR NA + ((fr400 (unit u-gr-store)) (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) + "Store word, update index") + +(conditional-store-u cstbfu QI OP_68 OPE4_0 FRint FR-ACCESS + ((fr400 (unit u-fr-store)) (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) + "Store byte float, update index") +(conditional-store-u csthfu HI OP_68 OPE4_1 FRint FR-ACCESS + ((fr400 (unit u-fr-store)) (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) + "Store half float, update index") +(conditional-store-u cstfu SI OP_68 OPE4_2 FRint FR-ACCESS + ((fr400 (unit u-fr-store)) (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) + "Store word float, update index") + +(define-pmacro (conditional-store-double-u + name mode op ope regtype attr profile comment) + (dni name + (comment) + ((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3) (FR400-MAJOR I-3) CONDITIONAL attr) + (.str name "$pack $" regtype "doublek,@($GRi,$GRj),$CCi,$cond") + (+ pack (.sym regtype doublek) op GRi CCi cond ope GRj) + (if (eq CCi (or cond 2)) + (sequence ((WI address)) + (store-double-semantics mode regtype address GRj) + (set GRi address))) + profile + ) +) + +(conditional-store-double-u cstdu DI OP_67 OPE4_3 GR NA + ((fr400 (unit u-gr-store)) + (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) + "Store double word, update index") +(conditional-store-double-u cstdfu DF OP_68 OPE4_3 FR FR-ACCESS + ((fr400 (unit u-fr-store)) + (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) + "Store double float, update index") + +(define-pmacro (store-r-simm name mode op regtype attr profile comment) + (dni name + (comment) + ((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3) (FR400-MAJOR I-3) attr) + (.str name "$pack $" regtype "k,@($GRi,$d12)") + (+ pack (.sym regtype k) op GRi d12) + (c-call VOID (.str "@cpu@_write_mem_" mode) + pc (add GRi d12) (.sym regtype k)) + profile + ) +) + +(store-r-simm stbi QI OP_50 GR NA + ((fr400 (unit u-gr-store)) (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) + "Store unsigned byte") +(store-r-simm sthi HI OP_51 GR NA + ((fr400 (unit u-gr-store)) (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) + "Store unsigned half") +(store-r-simm sti SI OP_52 GR NA + ((fr400 (unit u-gr-store)) (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) + "Store word") + +(store-r-simm stbfi QI OP_4E FRint FR-ACCESS + ((fr400 (unit u-fr-store)) (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) + "Store byte float") +(store-r-simm sthfi HI OP_4F FRint FR-ACCESS + ((fr400 (unit u-fr-store)) (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) + "Store half float") +(store-r-simm stfi SI OP_55 FRint FR-ACCESS + ((fr400 (unit u-fr-store)) (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) + "Store word float") + +(define-pmacro (store-double-r-simm name mode op regtype attr profile comment) + (dni name + (comment) + ((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3) (FR400-MAJOR I-3) attr) + (.str name "$pack $" regtype "doublek,@($GRi,$d12)") + (+ pack (.sym regtype doublek) op GRi d12) + (sequence ((WI address)) + (store-double-semantics mode regtype address d12)) + profile + ) +) + +(store-double-r-simm stdi DI OP_53 GR NA + ((fr400 (unit u-gr-store)) + (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) + "Store double word") +(store-double-r-simm stdfi DF OP_56 FR FR-ACCESS + ((fr400 (unit u-fr-store)) + (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) + "Store double float") + +(define-pmacro (store-quad-r-simm name op regtype attr profile comment) + (dni name + (comment) + ((UNIT STORE) (FR500-MAJOR I-3) (MACH frv) attr) + (.str name "$pack $" regtype "k,@($GRi,$d12)") + (+ pack (.sym regtype k) op GRi d12) + (sequence ((WI address)) + (store-quad-semantics regtype address d12)) + profile + ) +) + +(store-quad-r-simm stqi OP_54 GR NA ((fr500 (unit u-gr-store))) + "Store quad word") +(store-quad-r-simm stqfi OP_57 FRint FR-ACCESS () + "Store quad float") + +(define-pmacro (swap-semantics base offset arg) + (sequence ((WI tmp) (WI address)) + (set tmp arg) + (set address (add base offset)) + (c-call VOID "@cpu@_check_swap_address" address) + (set arg (c-call WI "@cpu@_read_mem_WI" pc address)) + (c-call VOID "@cpu@_write_mem_WI" pc address tmp)) +) + +(dni swap + "Swap contents of memory with GR" + ((UNIT C) (FR500-MAJOR C-2) (FR550-MAJOR C-2) (FR400-MAJOR C-2)) + "swap$pack @($GRi,$GRj),$GRk" + (+ pack GRk OP_03 GRi OPE1_05 GRj) + (swap-semantics GRi GRj GRk) + ((fr400 (unit u-swap)) + (fr500 (unit u-swap)) (fr550 (unit u-swap))) +) + +(dni "swapi" + "Swap contents of memory with GR" + ((UNIT C) (FR500-MAJOR C-2) (FR550-MAJOR C-2) (FR400-MAJOR C-2)) + ("swapi$pack @($GRi,$d12),$GRk") + (+ pack GRk OP_4D GRi d12) + (swap-semantics GRi d12 GRk) + ((fr400 (unit u-swap)) + (fr500 (unit u-swap)) (fr550 (unit u-swap))) +) + +(dni cswap + "Conditionally swap contents of memory with GR" + ((UNIT C) (FR500-MAJOR C-2) (FR550-MAJOR C-2) (FR400-MAJOR C-2) CONDITIONAL) + "cswap$pack @($GRi,$GRj),$GRk,$CCi,$cond" + (+ pack GRk OP_65 GRi CCi cond OPE4_2 GRj) + (if (eq CCi (or cond 2)) + (swap-semantics GRi GRj GRk)) + ((fr400 (unit u-swap)) + (fr500 (unit u-swap)) (fr550 (unit u-swap))) +) + +(define-pmacro (register-transfer + name op ope reg_src reg_targ pipe attrs profile comment) + (dni name + (comment) + (.splice (UNIT pipe) (.unsplice attrs)) + (.str name "$pack $" reg_src ",$" reg_targ) + (+ pack reg_targ op (rs-null) ope reg_src) + (set reg_targ reg_src) + profile + ) +) + +(register-transfer movgf OP_03 OPE1_15 + GRj FRintk I0 + ((FR500-MAJOR I-4) (FR550-MAJOR I-5) (FR400-MAJOR I-4) FR-ACCESS) + ((fr400 (unit u-gr2fr)) (fr500 (unit u-gr2fr)) (fr550 (unit u-gr2fr))) + "transfer gr to fr") +(register-transfer movfg OP_03 OPE1_0D + FRintk GRj I0 + ((FR500-MAJOR I-4) (FR550-MAJOR I-5) (FR400-MAJOR I-4) FR-ACCESS) + ((fr400 (unit u-fr2gr)) (fr500 (unit u-fr2gr)) (fr550 (unit u-fr2gr))) + "transfer fr to gr") + +(define-pmacro (nextreg hw r offset) (reg hw (add (index-of r) offset))) + +(define-pmacro (register-transfer-double-from-gr-semantics cond) + (if cond + (if (eq (index-of GRj) 0) + (sequence () + (set FRintk 0) + (set (nextreg h-fr_int FRintk 1) 0)) + (sequence () + (set FRintk GRj) + (set (nextreg h-fr_int FRintk 1) (nextreg h-gr GRj 1))))) +) + +(dni movgfd + "move GR for FR double" + ((UNIT I0) (FR500-MAJOR I-4) (FR550-MAJOR I-5) (FR400-MAJOR I-4) FR-ACCESS) + "movgfd$pack $GRj,$FRintk" + (+ pack FRintk OP_03 (rs-null) OPE1_16 GRj) + (register-transfer-double-from-gr-semantics 1) + ; TODO -- doesn't handle second register in the pair + ((fr400 (unit u-gr2fr)) + (fr500 (unit u-gr2fr)) (fr550 (unit u-gr2fr))) +) + +(define-pmacro (register-transfer-double-to-gr-semantics cond) + (if (andif (ne (index-of GRj) 0) cond) + (sequence () + (set GRj FRintk) + (set (nextreg h-gr GRj 1) (nextreg h-fr_int FRintk 1)))) +) + +(dni movfgd + "move FR for GR double" + ((UNIT I0) (FR500-MAJOR I-4) (FR550-MAJOR I-5) (FR400-MAJOR I-4) FR-ACCESS) + "movfgd$pack $FRintk,$GRj" + (+ pack FRintk OP_03 (rs-null) OPE1_0E GRj) + (register-transfer-double-to-gr-semantics 1) + ; TODO -- doesn't handle second register in the pair + ((fr400 (unit u-fr2gr)) + (fr500 (unit u-fr2gr)) (fr550 (unit u-fr2gr))) +) + +(dni movgfq + "move GR for FR quad" + ((UNIT I0) (FR500-MAJOR I-4) (MACH frv) FR-ACCESS) + "movgfq$pack $GRj,$FRintk" + (+ pack FRintk OP_03 (rs-null) OPE1_17 GRj) + (if (eq (index-of GRj) 0) + (sequence () + (set FRintk 0) + (set (reg h-fr_int (add (index-of FRintk) 1)) 0) + (set (reg h-fr_int (add (index-of FRintk) 2)) 0) + (set (reg h-fr_int (add (index-of FRintk) 3)) 0)) + (sequence () + (set FRintk GRj) + (set (reg h-fr_int (add (index-of FRintk) 1)) + (reg h-gr (add (index-of GRj) 1))) + (set (reg h-fr_int (add (index-of FRintk) 2)) + (reg h-gr (add (index-of GRj) 2))) + (set (reg h-fr_int (add (index-of FRintk) 3)) + (reg h-gr (add (index-of GRj) 3))))) + () +) + +(dni movfgq + "move FR for GR quad" + ((UNIT I0) (FR500-MAJOR I-4) (MACH frv) FR-ACCESS) + "movfgq$pack $FRintk,$GRj" + (+ pack FRintk OP_03 (rs-null) OPE1_0F GRj) + (if (ne (index-of GRj) 0) + (sequence () + (set GRj FRintk) + (set (reg h-gr (add (index-of GRj) 1)) + (reg h-fr_int (add (index-of FRintk) 1))) + (set (reg h-gr (add (index-of GRj) 2)) + (reg h-fr_int (add (index-of FRintk) 2))) + (set (reg h-gr (add (index-of GRj) 3)) + (reg h-fr_int (add (index-of FRintk) 3))))) + () +) + +(define-pmacro (conditional-register-transfer + name op ope reg_src reg_targ pipe attrs profile comment) + (dni name + (comment) + (.splice (UNIT pipe) CONDITIONAL FR-ACCESS (.unsplice attrs)) + (.str name "$pack $" reg_src ",$" reg_targ ",$CCi,$cond") + (+ pack reg_targ op (rs-null) CCi cond ope reg_src) + (if (eq CCi (or cond 2)) + (set reg_targ reg_src)) + profile + ) +) + +(conditional-register-transfer cmovgf OP_69 OPE4_0 GRj FRintk I0 + ((FR500-MAJOR I-4) (FR550-MAJOR I-5) (FR400-MAJOR I-4)) + ((fr400 (unit u-gr2fr)) (fr500 (unit u-gr2fr)) (fr550 (unit u-gr2fr))) + "transfer gr to fr") +(conditional-register-transfer cmovfg OP_69 OPE4_2 FRintk GRj I0 + ((FR500-MAJOR I-4) (FR550-MAJOR I-5) (FR400-MAJOR I-4)) + ((fr400 (unit u-fr2gr)) (fr500 (unit u-fr2gr)) (fr550 (unit u-fr2gr))) + "transfer fr to gr") + + +(dni cmovgfd + "Conditional move GR to FR double" + ((UNIT I0) (FR500-MAJOR I-4) (FR550-MAJOR I-5) (FR400-MAJOR I-4) CONDITIONAL FR-ACCESS) + "cmovgfd$pack $GRj,$FRintk,$CCi,$cond" + (+ pack FRintk OP_69 (rs-null) CCi cond OPE4_1 GRj) + (register-transfer-double-from-gr-semantics (eq CCi (or cond 2))) + ; TODO -- doesn't handle extra registers in double + ((fr400 (unit u-gr2fr)) + (fr500 (unit u-gr2fr)) (fr550 (unit u-gr2fr))) +) + +(dni cmovfgd + "Conditional move FR to GR double" + ((UNIT I0) (FR500-MAJOR I-4) (FR550-MAJOR I-5) (FR400-MAJOR I-4) CONDITIONAL FR-ACCESS) + "cmovfgd$pack $FRintk,$GRj,$CCi,$cond" + (+ pack FRintk OP_69 (rs-null) CCi cond OPE4_3 GRj) + (register-transfer-double-to-gr-semantics (eq CCi (or cond 2))) + ; TODO -- doesn't handle second register in the pair + ((fr400 (unit u-fr2gr)) + (fr500 (unit u-fr2gr)) (fr550 (unit u-fr2gr))) +) + +(define-pmacro (register-transfer-spr + name op ope reg_src reg_targ unitname comment) + (dni name + (comment) + ((UNIT C) (FR500-MAJOR C-2) (FR550-MAJOR C-2) (FR400-MAJOR C-2)) + (.str name "$pack $" reg_src ",$" reg_targ) + (+ pack reg_targ op ope reg_src) + (set reg_targ reg_src) + ((fr400 (unit unitname)) + (fr500 (unit unitname)) (fr550 (unit unitname))) + ) +) + +(register-transfer-spr movgs OP_03 OPE1_06 GRj spr u-gr2spr "transfer gr->spr") +(register-transfer-spr movsg OP_03 OPE1_07 spr GRj u-spr2gr "transfer spr->gr") + +; Integer Branch Conditions +(define-pmacro (Inev cc) (const BI 0)) +(define-pmacro (Ira cc) (const BI 1)) +(define-pmacro (Ieq cc) ( zbit cc)) +(define-pmacro (Ine cc) (not (zbit cc))) +(define-pmacro (Ile cc) ( orif (zbit cc) (xor (nbit cc) (vbit cc)))) +(define-pmacro (Igt cc) (not (orif (zbit cc) (xor (nbit cc) (vbit cc))))) +(define-pmacro (Ilt cc) ( xor (nbit cc) (vbit cc))) +(define-pmacro (Ige cc) (not (xor (nbit cc) (vbit cc)))) +(define-pmacro (Ils cc) ( orif (cbit cc) (zbit cc))) +(define-pmacro (Ihi cc) (not (orif (cbit cc) (zbit cc)))) +(define-pmacro (Ic cc) ( cbit cc)) +(define-pmacro (Inc cc) (not (cbit cc))) +(define-pmacro (In cc) ( nbit cc)) +(define-pmacro (Ip cc) (not (nbit cc))) +(define-pmacro (Iv cc) ( vbit cc)) +(define-pmacro (Inv cc) (not (vbit cc))) + +; Float Branch Conditions +(define-pmacro (Fnev cc) (const BI 0)) +(define-pmacro (Fra cc) (const BI 1)) +(define-pmacro (Fne cc) (orif (lbit cc) (orif (gbit cc) (ubit cc)))) +(define-pmacro (Feq cc) (ebit cc)) +(define-pmacro (Flg cc) (orif (lbit cc) (gbit cc))) +(define-pmacro (Fue cc) (orif (ebit cc) (ubit cc))) +(define-pmacro (Ful cc) (orif (lbit cc) (ubit cc))) +(define-pmacro (Fge cc) (orif (ebit cc) (gbit cc))) +(define-pmacro (Flt cc) (lbit cc)) +(define-pmacro (Fuge cc) (orif (ebit cc) (orif (gbit cc) (ubit cc)))) +(define-pmacro (Fug cc) (orif (gbit cc) (ubit cc))) +(define-pmacro (Fle cc) (orif (ebit cc) (lbit cc))) +(define-pmacro (Fgt cc) (gbit cc)) +(define-pmacro (Fule cc) (orif (ebit cc) (orif (lbit cc) (ubit cc)))) +(define-pmacro (Fu cc) (ubit cc)) +(define-pmacro (Fo cc) (orif (ebit cc) (orif (lbit cc) (gbit cc)))) + +(define-pmacro (conditional-branch-i prefix cc op cond comment) + (dni (.sym prefix cc) + (comment) + ((UNIT B01) (FR500-MAJOR B-1) (FR550-MAJOR B-1) (FR400-MAJOR B-1)) + (.str (.sym prefix cc) "$pack $ICCi_2,$hint,$label16") + (+ pack (.sym ICC_ cc) ICCi_2 op hint label16) + (sequence () + (c-call VOID "@cpu@_model_branch" label16 hint) + (if (cond ICCi_2) + (set pc label16))) + ((fr400 (unit u-branch)) + (fr500 (unit u-branch)) (fr550 (unit u-branch))) + ) +) + +(dni bra + "integer branch equal" + ((UNIT B01) (FR500-MAJOR B-1) (FR550-MAJOR B-1) (FR400-MAJOR B-1)) + "bra$pack $hint_taken$label16" + (+ pack ICC_ra (ICCi_2-null) OP_06 hint_taken label16) + (sequence () + (c-call VOID "@cpu@_model_branch" label16 hint_taken) + (set pc label16)) + ((fr400 (unit u-branch)) + (fr500 (unit u-branch)) (fr550 (unit u-branch))) +) + +(dni bno + "integer branch never" + ((UNIT B01) (FR500-MAJOR B-1) (FR550-MAJOR B-1) (FR400-MAJOR B-1)) + "bno$pack$hint_not_taken" + (+ pack ICC_nev (ICCi_2-null) OP_06 hint_not_taken (label16-null)) + (c-call VOID "@cpu@_model_branch" label16 hint_not_taken) + ((fr400 (unit u-branch)) + (fr500 (unit u-branch)) (fr550 (unit u-branch))) +) + +(conditional-branch-i b eq OP_06 Ieq "integer branch equal") +(conditional-branch-i b ne OP_06 Ine "integer branch not equal") +(conditional-branch-i b le OP_06 Ile "integer branch less or equal") +(conditional-branch-i b gt OP_06 Igt "integer branch greater") +(conditional-branch-i b lt OP_06 Ilt "integer branch less") +(conditional-branch-i b ge OP_06 Ige "integer branch greater or equal") +(conditional-branch-i b ls OP_06 Ils "integer branch less or equal unsigned") +(conditional-branch-i b hi OP_06 Ihi "integer branch greater unsigned") +(conditional-branch-i b c OP_06 Ic "integer branch carry set") +(conditional-branch-i b nc OP_06 Inc "integer branch carry clear") +(conditional-branch-i b n OP_06 In "integer branch negative") +(conditional-branch-i b p OP_06 Ip "integer branch positive") +(conditional-branch-i b v OP_06 Iv "integer branch overflow set") +(conditional-branch-i b nv OP_06 Inv "integer branch overflow clear") + +(define-pmacro (conditional-branch-f prefix cc op cond comment) + (dni (.sym prefix cc) + (comment) + ((UNIT B01) (FR500-MAJOR B-1) (FR550-MAJOR B-1) (FR400-MAJOR B-1) FR-ACCESS) + (.str (.sym prefix cc) "$pack $FCCi_2,$hint,$label16") + (+ pack (.sym FCC_ cc) FCCi_2 op hint label16) + (sequence () + (c-call VOID "@cpu@_model_branch" label16 hint) + (if (cond FCCi_2) (set pc label16))) + ((fr400 (unit u-branch)) + (fr500 (unit u-branch)) (fr550 (unit u-branch))) + ) +) + +(dni fbra + "float branch equal" + ((UNIT B01) (FR500-MAJOR B-1) (FR550-MAJOR B-1) (FR400-MAJOR B-1) FR-ACCESS) + "fbra$pack $hint_taken$label16" + (+ pack FCC_ra (FCCi_2-null) OP_07 hint_taken label16) + (sequence () + (c-call VOID "@cpu@_model_branch" label16 hint_taken) + (set pc label16)) + ((fr400 (unit u-branch)) + (fr500 (unit u-branch)) (fr550 (unit u-branch))) +) + +(dni fbno + "float branch never" + ((UNIT B01) (FR500-MAJOR B-1) (FR550-MAJOR B-1) (FR400-MAJOR B-1) FR-ACCESS) + "fbno$pack$hint_not_taken" + (+ pack FCC_nev (FCCi_2-null) OP_07 hint_not_taken (label16-null)) + (c-call VOID "@cpu@_model_branch" label16 hint_not_taken) + ((fr400 (unit u-branch)) + (fr500 (unit u-branch)) (fr550 (unit u-branch))) +) + +(conditional-branch-f fb ne OP_07 Fne "float branch not equal") +(conditional-branch-f fb eq OP_07 Feq "float branch equal") +(conditional-branch-f fb lg OP_07 Flg "float branch less or greater") +(conditional-branch-f fb ue OP_07 Fue "float branch unordered or equal") +(conditional-branch-f fb ul OP_07 Ful "float branch unordered or less") +(conditional-branch-f fb ge OP_07 Fge "float branch greater or equal") +(conditional-branch-f fb lt OP_07 Flt "float branch less") +(conditional-branch-f fb uge OP_07 Fuge "float branch unordered, greater,equal") +(conditional-branch-f fb ug OP_07 Fug "float branch unordered or greater") +(conditional-branch-f fb le OP_07 Fle "float branch less or equal") +(conditional-branch-f fb gt OP_07 Fgt "float branch greater") +(conditional-branch-f fb ule OP_07 Fule "float branch unordered, less or equal") +(conditional-branch-f fb u OP_07 Fu "float branch unordered") +(conditional-branch-f fb o OP_07 Fo "float branch ordered") + +(define-pmacro (ctrlr-branch-semantics cond ccond) + (sequence ((SI tmp)) + (set tmp (sub (spr-lcr) 1)) + (set (spr-lcr) tmp) + (if cond + (if (eq ccond 0) + (if (ne tmp 0) + (set pc (spr-lr))) + (if (eq tmp 0) + (set pc (spr-lr)))))) +) + +(dni bctrlr + "LCR conditional branch to lr" + ((UNIT B0) (FR500-MAJOR B-2) (FR550-MAJOR B-2) (FR400-MAJOR B-2)) + ("bctrlr$pack $ccond,$hint") + (+ pack (cond-null) (ICCi_2-null) OP_0E hint OPE3_01 ccond (s12-null)) + (sequence () + (c-call VOID "@cpu@_model_branch" (spr-lr) hint) + (ctrlr-branch-semantics (const BI 1) ccond)) + ((fr400 (unit u-branch)) + (fr500 (unit u-branch)) (fr550 (unit u-branch))) +) + +(define-pmacro (conditional-branch-cclr prefix cc i-f op ope cond attr comment) + (dni (.sym prefix cc lr) + (comment) + ((UNIT B01) (FR500-MAJOR B-3) (FR550-MAJOR B-3) (FR400-MAJOR B-3) attr) + (.str (.sym prefix cc lr) "$pack $" i-f "CCi_2,$hint") + (+ pack (.sym i-f CC_ cc) (.sym i-f CCi_2) op hint ope + (ccond-null) (s12-null)) + (sequence () + (c-call VOID "@cpu@_model_branch" (spr-lr) hint) + (if (cond (.sym i-f CCi_2)) (set pc (spr-lr)))) + ((fr400 (unit u-branch)) + (fr500 (unit u-branch)) (fr550 (unit u-branch))) + ) +) + +(dni bralr + "integer cclr branch always" + ((UNIT B01) (FR500-MAJOR B-3) (FR550-MAJOR B-3) (FR400-MAJOR B-3)) + "bralr$pack$hint_taken" + (+ pack ICC_ra (ICCi_2-null) OP_0E hint_taken OPE3_02 (ccond-null) (s12-null)) + (sequence () + (c-call VOID "@cpu@_model_branch" (spr-lr) hint_taken) + (set pc (spr-lr))) + ((fr400 (unit u-branch)) + (fr500 (unit u-branch)) (fr550 (unit u-branch))) +) + +(dni bnolr + "integer cclr branch never" + ((UNIT B01) (FR500-MAJOR B-3) (FR550-MAJOR B-3) (FR400-MAJOR B-3)) + "bnolr$pack$hint_not_taken" + (+ pack ICC_nev (ICCi_2-null) OP_0E hint_not_taken OPE3_02 (ccond-null) (s12-null)) + (c-call VOID "@cpu@_model_branch" (spr-lr) hint_not_taken) + ((fr400 (unit u-branch)) + (fr500 (unit u-branch)) (fr550 (unit u-branch))) +) + +(conditional-branch-cclr b eq I OP_0E OPE3_02 Ieq NA "integer cclr branch equal") +(conditional-branch-cclr b ne I OP_0E OPE3_02 Ine NA "integer cclr branch not equal") +(conditional-branch-cclr b le I OP_0E OPE3_02 Ile NA "integer cclr branch less or equal") +(conditional-branch-cclr b gt I OP_0E OPE3_02 Igt NA "integer cclr branch greater") +(conditional-branch-cclr b lt I OP_0E OPE3_02 Ilt NA "integer cclr branch less") +(conditional-branch-cclr b ge I OP_0E OPE3_02 Ige NA "integer cclr branch greater or equal") +(conditional-branch-cclr b ls I OP_0E OPE3_02 Ils NA "integer cclr branch less or equal unsigned") +(conditional-branch-cclr b hi I OP_0E OPE3_02 Ihi NA "integer cclr branch greater unsigned") +(conditional-branch-cclr b c I OP_0E OPE3_02 Ic NA "integer cclr branch carry set") +(conditional-branch-cclr b nc I OP_0E OPE3_02 Inc NA "integer cclr branch carry clear") +(conditional-branch-cclr b n I OP_0E OPE3_02 In NA "integer cclr branch negative") +(conditional-branch-cclr b p I OP_0E OPE3_02 Ip NA "integer cclr branch positive") +(conditional-branch-cclr b v I OP_0E OPE3_02 Iv NA "integer cclr branch overflow set") +(conditional-branch-cclr b nv I OP_0E OPE3_02 Inv NA "integer cclr branch overflow clear") + +(dni fbralr + "float cclr branch always" + ((UNIT B01) (FR500-MAJOR B-3) (FR550-MAJOR B-3) (FR400-MAJOR B-3) FR-ACCESS) + "fbralr$pack$hint_taken" + (+ pack FCC_ra (FCCi_2-null) OP_0E hint_taken OPE3_06 (ccond-null) (s12-null)) + (sequence () + (c-call VOID "@cpu@_model_branch" (spr-lr) hint_taken) + (set pc (spr-lr))) + ((fr400 (unit u-branch)) + (fr500 (unit u-branch)) (fr550 (unit u-branch))) +) + +(dni fbnolr + "float cclr branch never" + ((UNIT B01) (FR500-MAJOR B-3) (FR550-MAJOR B-3) (FR400-MAJOR B-3) FR-ACCESS) + "fbnolr$pack$hint_not_taken" + (+ pack FCC_nev (FCCi_2-null) OP_0E hint_not_taken OPE3_06 (ccond-null) (s12-null)) + (c-call VOID "@cpu@_model_branch" (spr-lr) hint_not_taken) + ((fr400 (unit u-branch)) + (fr500 (unit u-branch)) (fr550 (unit u-branch))) +) + +(conditional-branch-cclr fb eq F OP_0E OPE3_06 Feq FR-ACCESS "float cclr branch equal") +(conditional-branch-cclr fb ne F OP_0E OPE3_06 Fne FR-ACCESS "float cclr branch not equal") +(conditional-branch-cclr fb lg F OP_0E OPE3_06 Flg FR-ACCESS "float branch less or greater") +(conditional-branch-cclr fb ue F OP_0E OPE3_06 Fue FR-ACCESS "float branch unordered or equal") +(conditional-branch-cclr fb ul F OP_0E OPE3_06 Ful FR-ACCESS "float branch unordered or less") +(conditional-branch-cclr fb ge F OP_0E OPE3_06 Fge FR-ACCESS "float branch greater or equal") +(conditional-branch-cclr fb lt F OP_0E OPE3_06 Flt FR-ACCESS "float branch less") +(conditional-branch-cclr fb uge F OP_0E OPE3_06 Fuge FR-ACCESS "float branch unordered, greater, equal") +(conditional-branch-cclr fb ug F OP_0E OPE3_06 Fug FR-ACCESS "float branch unordered or greater") +(conditional-branch-cclr fb le F OP_0E OPE3_06 Fle FR-ACCESS "float branch less or equal") +(conditional-branch-cclr fb gt F OP_0E OPE3_06 Fgt FR-ACCESS "float branch greater") +(conditional-branch-cclr fb ule F OP_0E OPE3_06 Fule FR-ACCESS "float branch unordered, less or equal") +(conditional-branch-cclr fb u F OP_0E OPE3_06 Fu FR-ACCESS "float branch unordered") +(conditional-branch-cclr fb o F OP_0E OPE3_06 Fo FR-ACCESS "float branch ordered") + +(define-pmacro (conditional-branch-ctrlr prefix cc i-f op ope cond attr comment) + (dni (.sym prefix cc lr) + (comment) + ((UNIT B0) (FR500-MAJOR B-2) (FR550-MAJOR B-2) (FR400-MAJOR B-2) attr) + (.str (.sym prefix cc lr) "$pack $" i-f "CCi_2,$ccond,$hint") + (+ pack (.sym i-f CC_ cc) (.sym i-f CCi_2) op hint ope ccond (s12-null)) + (sequence () + (c-call VOID "@cpu@_model_branch" (spr-lr) hint) + (ctrlr-branch-semantics (cond (.sym i-f CCi_2)) ccond)) + ((fr400 (unit u-branch)) + (fr500 (unit u-branch)) (fr550 (unit u-branch))) + ) +) + +(dni bcralr + "integer ctrlr branch always" + ((UNIT B0) (FR500-MAJOR B-2) (FR550-MAJOR B-2) (FR400-MAJOR B-2)) + "bcralr$pack $ccond$hint_taken" + (+ pack ICC_ra (ICCi_2-null) OP_0E hint_taken OPE3_03 ccond (s12-null)) + (sequence () + (c-call VOID "@cpu@_model_branch" (spr-lr) hint_taken) + (ctrlr-branch-semantics (const BI 1) ccond)) + ((fr400 (unit u-branch)) + (fr500 (unit u-branch)) (fr550 (unit u-branch))) +) + +(dni bcnolr + "integer ctrlr branch never" + ((UNIT B0) (FR500-MAJOR B-2) (FR550-MAJOR B-2) (FR400-MAJOR B-2)) + "bcnolr$pack$hint_not_taken" + (+ pack ICC_nev (ICCi_2-null) OP_0E hint_not_taken OPE3_03 (ccond-null) (s12-null)) + (sequence () + (c-call VOID "@cpu@_model_branch" (spr-lr) hint_not_taken) + (ctrlr-branch-semantics (const BI 0) ccond)) + ((fr400 (unit u-branch)) + (fr500 (unit u-branch)) (fr550 (unit u-branch))) +) + +(conditional-branch-ctrlr bc eq I OP_0E OPE3_03 Ieq NA "integer ctrlr branch equal") +(conditional-branch-ctrlr bc ne I OP_0E OPE3_03 Ine NA "integer ctrlr branch not equal") +(conditional-branch-ctrlr bc le I OP_0E OPE3_03 Ile NA "integer ctrlr branch less equal") +(conditional-branch-ctrlr bc gt I OP_0E OPE3_03 Igt NA "integer ctrlr branch greater") +(conditional-branch-ctrlr bc lt I OP_0E OPE3_03 Ilt NA "integer ctrlr branch less") +(conditional-branch-ctrlr bc ge I OP_0E OPE3_03 Ige NA "integer ctrlr branch greater equal") +(conditional-branch-ctrlr bc ls I OP_0E OPE3_03 Ils NA "integer ctrlr branch less equal unsigned") +(conditional-branch-ctrlr bc hi I OP_0E OPE3_03 Ihi NA "integer ctrlr branch greater unsigned") +(conditional-branch-ctrlr bc c I OP_0E OPE3_03 Ic NA "integer ctrlr branch carry set") +(conditional-branch-ctrlr bc nc I OP_0E OPE3_03 Inc NA "integer ctrlr branch carry clear") +(conditional-branch-ctrlr bc n I OP_0E OPE3_03 In NA "integer ctrlr branch negative") +(conditional-branch-ctrlr bc p I OP_0E OPE3_03 Ip NA "integer ctrlr branch positive") +(conditional-branch-ctrlr bc v I OP_0E OPE3_03 Iv NA "integer ctrlr branch overflow set") +(conditional-branch-ctrlr bc nv I OP_0E OPE3_03 Inv NA "integer ctrlr branch overflow clear") + +(dni fcbralr + "float ctrlr branch always" + ((UNIT B0) (FR500-MAJOR B-2) (FR550-MAJOR B-2) (FR400-MAJOR B-2) FR-ACCESS) + "fcbralr$pack $ccond$hint_taken" + (+ pack FCC_ra (FCCi_2-null) OP_0E hint_taken OPE3_07 ccond (s12-null)) + (sequence () + (c-call VOID "@cpu@_model_branch" (spr-lr) hint_taken) + (ctrlr-branch-semantics (const BI 1) ccond)) + ((fr400 (unit u-branch)) + (fr500 (unit u-branch)) (fr550 (unit u-branch))) +) + +(dni fcbnolr + "float ctrlr branch never" + ((UNIT B0) (FR500-MAJOR B-2) (FR550-MAJOR B-2) (FR400-MAJOR B-2) FR-ACCESS) + "fcbnolr$pack$hint_not_taken" + (+ pack FCC_nev (FCCi_2-null) OP_0E hint_not_taken OPE3_07 (ccond-null) (s12-null)) + (sequence () + (c-call VOID "@cpu@_model_branch" (spr-lr) hint_not_taken) + (ctrlr-branch-semantics (const BI 0) ccond)) + ((fr400 (unit u-branch)) + (fr500 (unit u-branch)) (fr550 (unit u-branch))) +) + +(conditional-branch-ctrlr fcb eq F OP_0E OPE3_07 Feq FR-ACCESS "float cclr branch equal") +(conditional-branch-ctrlr fcb ne F OP_0E OPE3_07 Fne FR-ACCESS "float cclr branch not equal") +(conditional-branch-ctrlr fcb lg F OP_0E OPE3_07 Flg FR-ACCESS "float branch less or greater") +(conditional-branch-ctrlr fcb ue F OP_0E OPE3_07 Fue FR-ACCESS "float branch unordered or equal") +(conditional-branch-ctrlr fcb ul F OP_0E OPE3_07 Ful FR-ACCESS "float branch unordered or less") +(conditional-branch-ctrlr fcb ge F OP_0E OPE3_07 Fge FR-ACCESS "float branch greater or equal") +(conditional-branch-ctrlr fcb lt F OP_0E OPE3_07 Flt FR-ACCESS "float branch less") +(conditional-branch-ctrlr fcb uge F OP_0E OPE3_07 Fuge FR-ACCESS "float branch unordered, greater, equal") +(conditional-branch-ctrlr fcb ug F OP_0E OPE3_07 Fug FR-ACCESS "float branch unordered or greater") +(conditional-branch-ctrlr fcb le F OP_0E OPE3_07 Fle FR-ACCESS "float branch less or equal") +(conditional-branch-ctrlr fcb gt F OP_0E OPE3_07 Fgt FR-ACCESS "float branch greater") +(conditional-branch-ctrlr fcb ule F OP_0E OPE3_07 Fule FR-ACCESS "float branch unordered, less or equal") +(conditional-branch-ctrlr fcb u F OP_0E OPE3_07 Fu FR-ACCESS "float branch unordered") +(conditional-branch-ctrlr fcb o F OP_0E OPE3_07 Fo FR-ACCESS "float branch ordered") + +(define-pmacro (jump-and-link-semantics base offset LI) + (sequence () + (if (eq LI 1) + (c-call VOID "@cpu@_set_write_next_vliw_addr_to_LR" 1)) + ; Target address gets aligned here + (set pc (and (add base offset) #xfffffffc)) + (c-call VOID "@cpu@_model_branch" pc #x2)) ; hint branch taken +) + +(dni jmpl + "jump and link" + ((UNIT I0) (FR500-MAJOR I-5) (FR550-MAJOR I-6) (FR400-MAJOR I-5)) + "jmpl$pack @($GRi,$GRj)" + (+ pack (misc-null-1) (LI-off) OP_0C GRi (misc-null-2) GRj) + (jump-and-link-semantics GRi GRj LI) + ((fr400 (unit u-branch)) + (fr500 (unit u-branch)) (fr550 (unit u-branch))) +) + +(dni calll + "call and link" + ((UNIT I0) (FR500-MAJOR I-5) (FR400-MAJOR I-5)) + "calll$pack @($GRi,$GRj)" + (+ pack (misc-null-1) (LI-on) OP_0C GRi (misc-null-2) GRj) + (jump-and-link-semantics GRi GRj LI) + ((fr400 (unit u-branch)) + (fr500 (unit u-branch))) +) + +(dni jmpil + "jump immediate and link" + ((UNIT I0) (FR500-MAJOR I-5) (FR550-MAJOR I-6) (FR400-MAJOR I-5)) + "jmpil$pack @($GRi,$s12)" + (+ pack (misc-null-1) (LI-off) OP_0D GRi s12) + (jump-and-link-semantics GRi s12 LI) + ((fr400 (unit u-branch)) + (fr500 (unit u-branch)) (fr550 (unit u-branch))) +) + +(dni callil + "call immediate and link" + ((UNIT I0) (FR500-MAJOR I-5) (FR400-MAJOR I-5)) + "callil$pack @($GRi,$s12)" + (+ pack (misc-null-1) (LI-on) OP_0D GRi s12) + (jump-and-link-semantics GRi s12 LI) + ((fr400 (unit u-branch)) + (fr500 (unit u-branch))) +) + +(dni call + "call and link" + ((UNIT B0) (FR500-MAJOR B-4) (FR550-MAJOR B-4) (FR400-MAJOR B-4)) + "call$pack $label24" + (+ pack OP_0F label24) + (sequence () + (c-call VOID "@cpu@_set_write_next_vliw_addr_to_LR" 1) + (set pc label24) + (c-call VOID "@cpu@_model_branch" pc #x2)) ; hint branch taken + ((fr400 (unit u-branch)) + (fr500 (unit u-branch)) (fr550 (unit u-branch))) +) + +(dni rett + "return from trap" + ((UNIT C) (FR500-MAJOR C-2) (FR550-MAJOR C-2) (FR400-MAJOR C-2) PRIVILEGED) + "rett$pack $debug" + (+ pack (misc-null-1) debug OP_05 (rs-null) (s12-null)) + ; frv_rett handles operating vs user mode + (sequence () + (set pc (c-call UWI "frv_rett" pc debug)) + (c-call VOID "@cpu@_model_branch" pc #x2)) ; hint branch taken + () +) + +(dni rei + "run exception instruction" + ((UNIT C) (FR500-MAJOR C-1) (MACH frv) PRIVILEGED) + "rei$pack $eir" + (+ pack (rd-null) OP_37 eir (s12-null)) + (nop) ; for now + () +) + +(define-pmacro (trap-semantics cond base offset) + (if cond + (sequence () + ; This is defered to frv_itrap because for the breakpoint + ; case we want to change as little of the machine state as + ; possible. + ; + ; PCSR=PC + ; PSR.PS=PSR.S + ; PSR.ET=0 + ; if PSR.ESR==1 + ; SR0 through SR3=GR4 through GR7 + ; TBR.TT=0x80 + ((GRi + s12) & 0x7f) + ; PC=TBR + ; We still should indicate what is modified by this insn. + (clobber (spr-pcsr)) + (clobber psr_ps) + (clobber psr_et) + (clobber tbr_tt) + (if (ne psr_esr (const 0)) + (sequence () + (clobber (spr-sr0)) + (clobber (spr-sr1)) + (clobber (spr-sr2)) + (clobber (spr-sr3)))) + ; frv_itrap handles operating vs user mode + (c-call VOID "frv_itrap" pc base offset))) +) + +(define-pmacro (trap-r prefix cc i-f op ope cond attr comment) + (dni (.sym prefix cc) + (comment) + ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1) (FR400-MAJOR C-1) attr) + (.str (.sym prefix cc) "$pack $" i-f "CCi_2,$GRi,$GRj") + (+ pack (.sym i-f CC_ cc) (.sym i-f CCi_2) op GRi (misc-null-3) ope GRj) + (trap-semantics (cond (.sym i-f CCi_2)) GRi GRj) + ((fr400 (unit u-trap)) + (fr500 (unit u-trap)) (fr550 (unit u-trap))) + ) +) + +(dni tra + "integer trap always" + ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1) (FR400-MAJOR C-1)) + "tra$pack $GRi,$GRj" + (+ pack ICC_ra (ICCi_2-null) OP_04 GRi (misc-null-3) OPE4_0 GRj) + (trap-semantics (const BI 1) GRi GRj) + ((fr400 (unit u-trap)) + (fr500 (unit u-trap)) (fr550 (unit u-trap))) +) + +(dni tno + "integer trap never" + ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1) (FR400-MAJOR C-1)) + "tno$pack" + (+ pack ICC_nev (ICCi_2-null) OP_04 (GRi-null) (misc-null-3) OPE4_0 (GRj-null)) + (trap-semantics (const BI 0) GRi GRj) + ((fr400 (unit u-trap)) + (fr500 (unit u-trap)) (fr550 (unit u-trap))) +) + +(trap-r t eq I OP_04 OPE4_0 Ieq NA "integer trap equal") +(trap-r t ne I OP_04 OPE4_0 Ine NA "integer trap not equal") +(trap-r t le I OP_04 OPE4_0 Ile NA "integer trap less or equal") +(trap-r t gt I OP_04 OPE4_0 Igt NA "integer trap greater") +(trap-r t lt I OP_04 OPE4_0 Ilt NA "integer trap less") +(trap-r t ge I OP_04 OPE4_0 Ige NA "integer trap greater or equal") +(trap-r t ls I OP_04 OPE4_0 Ils NA "integer trap less or equal unsigned") +(trap-r t hi I OP_04 OPE4_0 Ihi NA "integer trap greater unsigned") +(trap-r t c I OP_04 OPE4_0 Ic NA "integer trap carry set") +(trap-r t nc I OP_04 OPE4_0 Inc NA "integer trap carry clear") +(trap-r t n I OP_04 OPE4_0 In NA "integer trap negative") +(trap-r t p I OP_04 OPE4_0 Ip NA "integer trap positive") +(trap-r t v I OP_04 OPE4_0 Iv NA "integer trap overflow set") +(trap-r t nv I OP_04 OPE4_0 Inv NA "integer trap overflow clear") + +(dni ftra + "float trap always" + ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1) (FR400-MAJOR C-1) FR-ACCESS) + "ftra$pack $GRi,$GRj" + (+ pack FCC_ra (FCCi_2-null) OP_04 GRi (misc-null-3) OPE4_1 GRj) + (trap-semantics (const BI 1) GRi GRj) + ((fr400 (unit u-trap)) + (fr500 (unit u-trap)) (fr550 (unit u-trap))) +) + +(dni ftno + "flost trap never" + ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1) (FR400-MAJOR C-1) FR-ACCESS) + "ftno$pack" + (+ pack FCC_nev (FCCi_2-null) OP_04 (GRi-null) (misc-null-3) OPE4_1 (GRj-null)) + (trap-semantics (const BI 0) GRi GRj) + ((fr400 (unit u-trap)) + (fr500 (unit u-trap)) (fr550 (unit u-trap))) +) + +(trap-r ft ne F OP_04 OPE4_1 Fne FR-ACCESS "float trap not equal") +(trap-r ft eq F OP_04 OPE4_1 Feq FR-ACCESS "float trap equal") +(trap-r ft lg F OP_04 OPE4_1 Flg FR-ACCESS "float trap greater or less") +(trap-r ft ue F OP_04 OPE4_1 Fue FR-ACCESS "float trap unordered or equal") +(trap-r ft ul F OP_04 OPE4_1 Ful FR-ACCESS "float trap unordered or less") +(trap-r ft ge F OP_04 OPE4_1 Fge FR-ACCESS "float trap greater or equal") +(trap-r ft lt F OP_04 OPE4_1 Flt FR-ACCESS "float trap less") +(trap-r ft uge F OP_04 OPE4_1 Fuge FR-ACCESS "float trap unordered greater or equal") +(trap-r ft ug F OP_04 OPE4_1 Fug FR-ACCESS "float trap unordered or greater") +(trap-r ft le F OP_04 OPE4_1 Fle FR-ACCESS "float trap less or equal") +(trap-r ft gt F OP_04 OPE4_1 Fgt FR-ACCESS "float trap greater") +(trap-r ft ule F OP_04 OPE4_1 Fule FR-ACCESS "float trap unordered less or equal") +(trap-r ft u F OP_04 OPE4_1 Fu FR-ACCESS "float trap unordered") +(trap-r ft o F OP_04 OPE4_1 Fo FR-ACCESS "float trap ordered") + +(define-pmacro (trap-immed prefix cc i-f op cond attr comment) + (dni (.sym prefix cc) + (comment) + ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1) (FR400-MAJOR C-1) attr) + (.str (.sym prefix cc) "$pack $" i-f "CCi_2,$GRi,$s12") + (+ pack (.sym i-f CC_ cc) (.sym i-f CCi_2) op GRi s12) + (trap-semantics (cond (.sym i-f CCi_2)) GRi s12) + ((fr400 (unit u-trap)) + (fr500 (unit u-trap)) (fr550 (unit u-trap))) + ) +) + +(dni tira + "integer trap always" + ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1) (FR400-MAJOR C-1)) + "tira$pack $GRi,$s12" + (+ pack ICC_ra (ICCi_2-null) OP_1C GRi s12) + (trap-semantics (const BI 1) GRi s12) + ((fr400 (unit u-trap)) + (fr500 (unit u-trap)) (fr550 (unit u-trap))) +) + +(dni tino + "integer trap never" + ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1) (FR400-MAJOR C-1)) + "tino$pack" + (+ pack ICC_nev (ICCi_2-null) OP_1C (GRi-null) (s12-null)) + (trap-semantics (const BI 0) GRi s12) + ((fr400 (unit u-trap)) + (fr500 (unit u-trap)) (fr550 (unit u-trap))) +) + +(trap-immed ti eq I OP_1C Ieq NA "integer trap equal") +(trap-immed ti ne I OP_1C Ine NA "integer trap not equal") +(trap-immed ti le I OP_1C Ile NA "integer trap less or equal") +(trap-immed ti gt I OP_1C Igt NA "integer trap greater") +(trap-immed ti lt I OP_1C Ilt NA "integer trap less") +(trap-immed ti ge I OP_1C Ige NA "integer trap greater or equal") +(trap-immed ti ls I OP_1C Ils NA "integer trap less or equal unsigned") +(trap-immed ti hi I OP_1C Ihi NA "integer trap greater unsigned") +(trap-immed ti c I OP_1C Ic NA "integer trap carry set") +(trap-immed ti nc I OP_1C Inc NA "integer trap carry clear") +(trap-immed ti n I OP_1C In NA "integer trap negative") +(trap-immed ti p I OP_1C Ip NA "integer trap positive") +(trap-immed ti v I OP_1C Iv NA "integer trap overflow set") +(trap-immed ti nv I OP_1C Inv NA "integer trap overflow clear") + +(dni ftira + "float trap always" + ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1) (FR400-MAJOR C-1) FR-ACCESS) + "ftira$pack $GRi,$s12" + (+ pack FCC_ra (ICCi_2-null) OP_1D GRi s12) + (trap-semantics (const BI 1) GRi s12) + ((fr400 (unit u-trap)) + (fr500 (unit u-trap)) (fr550 (unit u-trap))) +) + +(dni ftino + "float trap never" + ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1) (FR400-MAJOR C-1) FR-ACCESS) + "ftino$pack" + (+ pack FCC_nev (FCCi_2-null) OP_1D (GRi-null) (s12-null)) + (trap-semantics (const BI 0) GRi s12) + ((fr400 (unit u-trap)) + (fr500 (unit u-trap)) (fr550 (unit u-trap))) +) + +(trap-immed fti ne F OP_1D Fne FR-ACCESS "float trap not equal") +(trap-immed fti eq F OP_1D Feq FR-ACCESS "float trap equal") +(trap-immed fti lg F OP_1D Flg FR-ACCESS "float trap greater or less") +(trap-immed fti ue F OP_1D Fue FR-ACCESS "float trap unordered or equal") +(trap-immed fti ul F OP_1D Ful FR-ACCESS "float trap unordered or less") +(trap-immed fti ge F OP_1D Fge FR-ACCESS "float trap greater or equal") +(trap-immed fti lt F OP_1D Flt FR-ACCESS "float trap less") +(trap-immed fti uge F OP_1D Fuge FR-ACCESS "float trap unordered greater or equal") +(trap-immed fti ug F OP_1D Fug FR-ACCESS "float trap unordered or greater") +(trap-immed fti le F OP_1D Fle FR-ACCESS "float trap less or equal") +(trap-immed fti gt F OP_1D Fgt FR-ACCESS "float trap greater") +(trap-immed fti ule F OP_1D Fule FR-ACCESS "float trap unordered less or equal") +(trap-immed fti u F OP_1D Fu FR-ACCESS "float trap unordered") +(trap-immed fti o F OP_1D Fo FR-ACCESS "float trap ordered") + +(dni break + "break trap" + ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1) (FR400-MAJOR C-1)) + "break$pack" + (+ pack (rd-null) OP_04 (rs-null) (misc-null-3) OPE4_3 (GRj-null)) + (sequence () + ; This is defered to frv_break because for the breakpoint + ; case we want to change as little of the machine state as + ; possible. + ; + ; BPCSR=PC + ; BPSR.BS=PSR.S + ; BPSR.BET=PSR.ET + ; PSR.S=1 + ; PSR.ET=0 + ; TBR.TT=0xff + ; PC=TBR + ; We still should indicate what is modified by this insn. + (clobber (spr-bpcsr)) + (clobber bpsr_bs) + (clobber bpsr_bet) + (clobber psr_s) + (clobber psr_et) + (clobber tbr_tt) + (c-call VOID "frv_break")) + () +) + +(dni mtrap + "media trap" + ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1) (FR400-MAJOR C-1) FR-ACCESS) + "mtrap$pack" + (+ pack (rd-null) OP_04 (rs-null) (misc-null-3) OPE4_2 (GRj-null)) + (c-call VOID "frv_mtrap") + () +) + +(define-pmacro (condition-code-logic name operation ope comment) + (dni name + (comment) + ((UNIT B01) (FR500-MAJOR B-6) (FR550-MAJOR B-6) (FR400-MAJOR B-6)) + (.str name "$pack $CRi,$CRj,$CRk") + (+ pack (misc-null-6) CRk OP_0A (misc-null-7) CRi ope (misc-null-8) CRj) + (set CRk (c-call UQI "@cpu@_cr_logic" operation CRi CRj)) + () + ) +) +(define-pmacro (op-andcr) 0) +(define-pmacro (op-orcr) 1) +(define-pmacro (op-xorcr) 2) +(define-pmacro (op-nandcr) 3) +(define-pmacro (op-norcr) 4) +(define-pmacro (op-andncr) 5) +(define-pmacro (op-orncr) 6) +(define-pmacro (op-nandncr) 7) +(define-pmacro (op-norncr) 8) + +(define-pmacro (cr-true) 3) +(define-pmacro (cr-false) 2) +(define-pmacro (cr-undefined) 0) + +(condition-code-logic andcr (op-andcr) OPE1_08 "and condition code regs") +(condition-code-logic orcr (op-orcr) OPE1_09 "or condition code regs") +(condition-code-logic xorcr (op-xorcr) OPE1_0A "xor condition code regs") +(condition-code-logic nandcr (op-nandcr) OPE1_0C "nand condition code regs") +(condition-code-logic norcr (op-norcr) OPE1_0D "nor condition code regs") +(condition-code-logic andncr (op-andncr) OPE1_10 "andn condition code regs") +(condition-code-logic orncr (op-orncr) OPE1_11 "orn condition code regs") +(condition-code-logic nandncr (op-nandncr) OPE1_14 "nandn condition code regs") +(condition-code-logic norncr (op-norncr) OPE1_15 "norn condition code regs") + +(dni notcr + ("not cccr register") + ((UNIT B01) (FR500-MAJOR B-6) (FR550-MAJOR B-6) (FR400-MAJOR B-6)) + (.str notcr "$pack $CRj,$CRk") + (+ pack (misc-null-6) CRk OP_0A (rs-null) OPE1_0B (misc-null-8) CRj) + (set CRk (xor CRj 1)) + () +) + +(define-pmacro (check-semantics cond cr) + (if cond (set cr (cr-true)) (set cr (cr-false))) +) + +(define-pmacro (check-int-condition-code prefix cc op cond comment) + (dni (.sym prefix cc) + (comment) + ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5) (FR400-MAJOR B-5)) + (.str (.sym prefix cc) "$pack $ICCi_3,$CRj_int") + (+ pack (.sym ICC_ cc) CRj_int op (misc-null-5) ICCi_3) + (check-semantics (cond ICCi_3) CRj_int) + ((fr400 (unit u-check)) + (fr500 (unit u-check)) (fr550 (unit u-check))) + ) +) + +(dni ckra + "check integer cc always" + ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5) (FR400-MAJOR B-5)) + "ckra$pack $CRj_int" + (+ pack ICC_ra CRj_int OP_08 (misc-null-5) (ICCi_3-null)) + (check-semantics (const BI 1) CRj_int) + ((fr400 (unit u-check)) + (fr500 (unit u-check)) (fr550 (unit u-check))) +) + +(dni ckno + "check integer cc never" + ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5) (FR400-MAJOR B-5)) + "ckno$pack $CRj_int" + (+ pack ICC_nev CRj_int OP_08 (misc-null-5) (ICCi_3-null)) + (check-semantics (const BI 0) CRj_int) + ((fr400 (unit u-check)) + (fr500 (unit u-check)) (fr550 (unit u-check))) +) + +(check-int-condition-code ck eq OP_08 Ieq "check integer cc equal") +(check-int-condition-code ck ne OP_08 Ine "check integer cc not equal") +(check-int-condition-code ck le OP_08 Ile "check integer cc less or equal") +(check-int-condition-code ck gt OP_08 Igt "check integer cc greater") +(check-int-condition-code ck lt OP_08 Ilt "check integer cc less") +(check-int-condition-code ck ge OP_08 Ige "check integer cc greater or equal") +(check-int-condition-code ck ls OP_08 Ils "check integer cc less or equal unsigned") +(check-int-condition-code ck hi OP_08 Ihi "check integer cc greater unsigned") +(check-int-condition-code ck c OP_08 Ic "check integer cc carry set") +(check-int-condition-code ck nc OP_08 Inc "check integer cc carry clear") +(check-int-condition-code ck n OP_08 In "check integer cc negative") +(check-int-condition-code ck p OP_08 Ip "check integer cc positive") +(check-int-condition-code ck v OP_08 Iv "check integer cc overflow set") +(check-int-condition-code ck nv OP_08 Inv "check integer cc overflow clear") + +(define-pmacro (check-float-condition-code prefix cc op cond comment) + (dni (.sym prefix cc) + (comment) + ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5) (FR400-MAJOR B-5) FR-ACCESS) + (.str (.sym prefix cc) "$pack $FCCi_3,$CRj_float") + (+ pack (.sym FCC_ cc) CRj_float op (misc-null-5) FCCi_3) + (check-semantics (cond FCCi_3) CRj_float) + ((fr400 (unit u-check)) + (fr500 (unit u-check)) (fr550 (unit u-check))) + ) +) + +(dni fckra + "check float cc always" + ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5) (FR400-MAJOR B-5) FR-ACCESS) + "fckra$pack $CRj_float" + (+ pack FCC_ra CRj_float OP_09 (misc-null-5) FCCi_3) + (check-semantics (const BI 1) CRj_float) + ((fr400 (unit u-check)) + (fr500 (unit u-check)) (fr550 (unit u-check))) +) + +(dni fckno + "check float cc never" + ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5) (FR400-MAJOR B-5) FR-ACCESS) + "fckno$pack $CRj_float" + (+ pack FCC_nev CRj_float OP_09 (misc-null-5) FCCi_3) + (check-semantics (const BI 0) CRj_float) + ((fr400 (unit u-check)) + (fr500 (unit u-check)) (fr550 (unit u-check))) +) + +(check-float-condition-code fck ne OP_09 Fne "check float cc not equal") +(check-float-condition-code fck eq OP_09 Feq "check float cc equal") +(check-float-condition-code fck lg OP_09 Flg "check float cc greater or less") +(check-float-condition-code fck ue OP_09 Fue "check float cc unordered or equal") +(check-float-condition-code fck ul OP_09 Ful "check float cc unordered or less") +(check-float-condition-code fck ge OP_09 Fge "check float cc greater or equal") +(check-float-condition-code fck lt OP_09 Flt "check float cc less") +(check-float-condition-code fck uge OP_09 Fuge "check float cc unordered greater or equal") +(check-float-condition-code fck ug OP_09 Fug "check float cc unordered or greater") +(check-float-condition-code fck le OP_09 Fle "check float cc less or equal") +(check-float-condition-code fck gt OP_09 Fgt "check float cc greater") +(check-float-condition-code fck ule OP_09 Fule "check float cc unordered less or equal") +(check-float-condition-code fck u OP_09 Fu "check float cc unordered") +(check-float-condition-code fck o OP_09 Fo "check float cc ordered") + +(define-pmacro (conditional-check-int-condition-code prefix cc op ope test comment) + (dni (.sym prefix cc) + (comment) + ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5) (FR400-MAJOR B-5) CONDITIONAL) + (.str (.sym prefix cc) "$pack $ICCi_3,$CRj_int,$CCi,$cond") + (+ pack (.sym ICC_ cc) CRj_int op (rs-null) CCi cond ope + (misc-null-9) ICCi_3) + (if (eq CCi (or cond 2)) + (check-semantics (test ICCi_3) CRj_int) + (set CRj_int (cr-undefined))) + ((fr400 (unit u-check)) + (fr500 (unit u-check)) (fr550 (unit u-check))) + ) +) + +(dni cckra + "conditional check integer cc always" + ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5) (FR400-MAJOR B-5) CONDITIONAL) + "cckra$pack $CRj_int,$CCi,$cond" + (+ pack ICC_ra CRj_int OP_6A (rs-null) CCi cond OPE4_0 + (misc-null-9) (ICCi_3-null)) + (if (eq CCi (or cond 2)) + (check-semantics (const BI 1) CRj_int) + (set CRj_int (cr-undefined))) + ((fr400 (unit u-check)) + (fr500 (unit u-check)) (fr550 (unit u-check))) +) + +(dni cckno + "conditional check integer cc never" + ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5) (FR400-MAJOR B-5) CONDITIONAL) + "cckno$pack $CRj_int,$CCi,$cond" + (+ pack ICC_nev CRj_int OP_6A (rs-null) CCi cond OPE4_0 + (misc-null-9) (ICCi_3-null)) + (if (eq CCi (or cond 2)) + (check-semantics (const BI 0) CRj_int) + (set CRj_int (cr-undefined))) + ((fr400 (unit u-check)) + (fr500 (unit u-check)) (fr550 (unit u-check))) +) + +(conditional-check-int-condition-code cck eq OP_6A OPE4_0 Ieq "check integer cc equal") +(conditional-check-int-condition-code cck ne OP_6A OPE4_0 Ine "check integer cc not equal") +(conditional-check-int-condition-code cck le OP_6A OPE4_0 Ile "check integer cc less or equal") +(conditional-check-int-condition-code cck gt OP_6A OPE4_0 Igt "check integer cc greater") +(conditional-check-int-condition-code cck lt OP_6A OPE4_0 Ilt "check integer cc less") +(conditional-check-int-condition-code cck ge OP_6A OPE4_0 Ige "check integer cc greater or equal") +(conditional-check-int-condition-code cck ls OP_6A OPE4_0 Ils "check integer cc less or equal unsigned") +(conditional-check-int-condition-code cck hi OP_6A OPE4_0 Ihi "check integer cc greater unsigned") +(conditional-check-int-condition-code cck c OP_6A OPE4_0 Ic "check integer cc carry set") +(conditional-check-int-condition-code cck nc OP_6A OPE4_0 Inc "check integer cc carry clear") +(conditional-check-int-condition-code cck n OP_6A OPE4_0 In "check integer cc negative") +(conditional-check-int-condition-code cck p OP_6A OPE4_0 Ip "check integer cc positive") +(conditional-check-int-condition-code cck v OP_6A OPE4_0 Iv "check integer cc overflow set") +(conditional-check-int-condition-code cck nv OP_6A OPE4_0 Inv "check integer cc overflow clear") + +(define-pmacro (conditional-check-float-condition-code prefix cc op ope test comment) + (dni (.sym prefix cc) + (comment) + ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5) (FR400-MAJOR B-5) CONDITIONAL FR-ACCESS) + (.str (.sym prefix cc) "$pack $FCCi_3,$CRj_float,$CCi,$cond") + (+ pack (.sym FCC_ cc) CRj_float op (rs-null) CCi cond ope + (misc-null-9) FCCi_3) + (if (eq CCi (or cond 2)) + (check-semantics (test FCCi_3) CRj_float) + (set CRj_float (cr-undefined))) + ((fr400 (unit u-check)) + (fr500 (unit u-check)) (fr550 (unit u-check))) + ) +) + +(dni cfckra + "conditional check float cc always" + ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5) (FR400-MAJOR B-5) CONDITIONAL FR-ACCESS) + "cfckra$pack $CRj_float,$CCi,$cond" + (+ pack FCC_ra CRj_float OP_6A (rs-null) CCi cond OPE4_1 + (misc-null-9) (FCCi_3-null)) + (if (eq CCi (or cond 2)) + (check-semantics (const BI 1) CRj_float) + (set CRj_float (cr-undefined))) + ((fr400 (unit u-check)) + (fr500 (unit u-check)) (fr550 (unit u-check))) +) + +(dni cfckno + "conditional check float cc never" + ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5) (FR400-MAJOR B-5) CONDITIONAL FR-ACCESS) + "cfckno$pack $CRj_float,$CCi,$cond" + (+ pack FCC_nev CRj_float OP_6A (rs-null) CCi cond OPE4_1 + (misc-null-9) (FCCi_3-null)) + (if (eq CCi (or cond 2)) + (check-semantics (const BI 0) CRj_float) + (set CRj_float (cr-undefined))) + ((fr400 (unit u-check)) + (fr500 (unit u-check)) (fr550 (unit u-check))) +) + +(conditional-check-float-condition-code cfck ne OP_6A OPE4_1 Fne "check float cc not equal") +(conditional-check-float-condition-code cfck eq OP_6A OPE4_1 Feq "check float cc equal") +(conditional-check-float-condition-code cfck lg OP_6A OPE4_1 Flg "check float cc greater or less") +(conditional-check-float-condition-code cfck ue OP_6A OPE4_1 Fue "check float cc unordered or equal") +(conditional-check-float-condition-code cfck ul OP_6A OPE4_1 Ful "check float cc unordered or less") +(conditional-check-float-condition-code cfck ge OP_6A OPE4_1 Fge "check float cc greater or equal") +(conditional-check-float-condition-code cfck lt OP_6A OPE4_1 Flt "check float cc less") +(conditional-check-float-condition-code cfck uge OP_6A OPE4_1 Fuge "check float cc unordered greater or equal") +(conditional-check-float-condition-code cfck ug OP_6A OPE4_1 Fug "check float cc unordered or greater") +(conditional-check-float-condition-code cfck le OP_6A OPE4_1 Fle "check float cc less or equal") +(conditional-check-float-condition-code cfck gt OP_6A OPE4_1 Fgt "check float cc greater") +(conditional-check-float-condition-code cfck ule OP_6A OPE4_1 Fule "check float cc unordered less or equal") +(conditional-check-float-condition-code cfck u OP_6A OPE4_1 Fu "check float cc unordered") +(conditional-check-float-condition-code cfck o OP_6A OPE4_1 Fo "check float cc ordered") + +(dni cjmpl + "conditional jump and link" + ((UNIT I0) (FR500-MAJOR I-5) (FR550-MAJOR I-6) (FR400-MAJOR I-5) CONDITIONAL) + "cjmpl$pack @($GRi,$GRj),$CCi,$cond" + (+ pack (misc-null-1) (LI-off) OP_6A GRi CCi cond OPE4_2 GRj) + (if (eq CCi (or cond 2)) + (jump-and-link-semantics GRi GRj LI)) + ((fr400 (unit u-branch)) + (fr500 (unit u-branch)) (fr550 (unit u-branch))) +) + +(dni ccalll + "conditional call and link" + ((UNIT I0) (FR500-MAJOR I-5) (FR400-MAJOR I-5) CONDITIONAL) + "ccalll$pack @($GRi,$GRj),$CCi,$cond" + (+ pack (misc-null-1) (LI-on) OP_6A GRi CCi cond OPE4_2 GRj) + (if (eq CCi (or cond 2)) + (jump-and-link-semantics GRi GRj LI)) + ((fr400 (unit u-branch)) + (fr500 (unit u-branch))) +) + +(define-pmacro (cache-invalidate name cache all op ope profile comment) + (dni name + (comment) + ((UNIT C) (FR500-MAJOR C-2) (FR550-MAJOR C-2) (FR400-MAJOR C-2)) + (.str name "$pack @($GRi,$GRj)") + (+ pack (rd-null) op GRi ope GRj) + (c-call VOID (.str "@cpu@_" cache "_cache_invalidate") (add GRi GRj) all) + profile + ) +) + +(cache-invalidate ici insn 0 OP_03 OPE1_38 + ((fr400 (unit u-ici)) (fr500 (unit u-ici)) (fr550 (unit u-ici))) + "invalidate insn cache") +(cache-invalidate dci data 0 OP_03 OPE1_3C + ((fr400 (unit u-dci)) (fr500 (unit u-dci)) (fr550 (unit u-dci))) + "invalidate data cache") + +(define-pmacro (cache-invalidate-entry name cache op ope profile comment) + (dni name + (comment) + ((UNIT C) (FR400-MAJOR C-2) (FR550-MAJOR C-2) (MACH fr400,fr550)) + (.str name "$pack @($GRi,$GRj),$ae") + (+ pack (misc-null-1) ae op GRi ope GRj) + (if (eq ae 0) + (c-call VOID (.str "@cpu@_" cache "_cache_invalidate") (add GRi GRj) -1) ; Invalid ae setting for this insn + (c-call VOID (.str "@cpu@_" cache "_cache_invalidate") (add GRi GRj) ae)) + profile + ) +) + +(cache-invalidate-entry icei insn OP_03 OPE1_39 + ((fr400 (unit u-ici)) (fr550 (unit u-ici))) + "invalidate insn cache entry") +(cache-invalidate-entry dcei data OP_03 OPE1_3A + ((fr400 (unit u-dci)) (fr550 (unit u-dci))) + "invalidate data cache entry") + +(dni dcf + "Data cache flush" + ((UNIT C) (FR500-MAJOR C-2) (FR550-MAJOR C-2) (FR400-MAJOR C-2)) + "dcf$pack @($GRi,$GRj)" + (+ pack (rd-null) OP_03 GRi OPE1_3D GRj) + (c-call VOID "@cpu@_data_cache_flush" (add GRi GRj) 0) + ((fr400 (unit u-dcf)) + (fr500 (unit u-dcf)) (fr550 (unit u-dcf))) +) + +(dni dcef + "Data cache entry flush" + ((UNIT C) (FR400-MAJOR C-2) (FR550-MAJOR C-2) (MACH fr400,fr550)) + "dcef$pack @($GRi,$GRj),$ae" + (+ pack (misc-null-1) ae OP_03 GRi OPE1_3B GRj) + (if (eq ae 0) + (c-call VOID "@cpu@_data_cache_flush" (add GRi GRj) -1) + (c-call VOID "@cpu@_data_cache_flush" (add GRi GRj) ae)) + ((fr400 (unit u-dcf)) (fr550 (unit u-dcf))) +) + +(define-pmacro (write-TLB name insn op ope comment) + (dni name + (comment) + ((UNIT C) (FR500-MAJOR C-2) (MACH frv) PRIVILEGED) + (.str insn "$pack $GRk,@($GRi,$GRj)") + (+ pack GRk op GRi ope GRj) + (nop) ; for now + () + ) +) + +(write-TLB witlb witlb OP_03 OPE1_32 "write for insn TLB") +(write-TLB wdtlb wdtlb OP_03 OPE1_36 "write for data TLB") + +(define-pmacro (invalidate-TLB name insn op ope comment) + (dni name + (comment) + ((UNIT C) (FR500-MAJOR C-2) (MACH frv) PRIVILEGED) + (.str insn "$pack @($GRi,$GRj)") + (+ pack (rd-null) op GRi ope GRj) + (nop) ; for now + () + ) +) + +(invalidate-TLB itlbi itlbi OP_03 OPE1_33 "invalidate insn TLB") +(invalidate-TLB dtlbi dtlbi OP_03 OPE1_37 "invalidate data TLB") + +(define-pmacro (cache-preload name cache pipe attrs op ope profile comment) + (dni name + (comment) + (.splice (UNIT pipe) (FR500-MAJOR C-2) (FR400-MAJOR C-2) (.unsplice attrs)) + (.str name "$pack $GRi,$GRj,$lock") + (+ pack (misc-null-1) lock op GRi ope GRj) + (c-call VOID (.str "@cpu@_" cache "_cache_preload") GRi GRj lock) + profile + ) +) + +(cache-preload icpl insn C ((FR550-MAJOR C-2)) OP_03 OPE1_30 + ((fr400 (unit u-icpl)) (fr500 (unit u-icpl)) (fr550 (unit u-icpl))) + "preload insn cache") +(cache-preload dcpl data DCPL ((FR550-MAJOR I-8)) OP_03 OPE1_34 + ((fr400 (unit u-dcpl)) (fr500 (unit u-dcpl)) (fr550 (unit u-dcpl))) + "preload data cache") + +(define-pmacro (cache-unlock name cache op ope profile comment) + (dni name + (comment) + ((UNIT C) (FR500-MAJOR C-2) (FR550-MAJOR C-2) (FR400-MAJOR C-2)) + (.str name "$pack $GRi") + (+ pack (rd-null) op GRi ope (GRj-null)) + (c-call VOID (.str "@cpu@_" cache "_cache_unlock") GRi) + profile + ) +) + +(cache-unlock icul insn OP_03 OPE1_31 + ((fr400 (unit u-icul)) (fr500 (unit u-icul)) (fr550 (unit u-icul))) + "unlock insn cache") +(cache-unlock dcul data OP_03 OPE1_35 + ((fr400 (unit u-dcul)) (fr500 (unit u-dcul)) (fr550 (unit u-dcul))) + "unlock data cache") + +(define-pmacro (barrier name insn op ope profile comment) + (dni name + (comment) + ((UNIT C) (FR500-MAJOR C-2) (FR550-MAJOR C-2) (FR400-MAJOR C-2)) + (.str insn "$pack") + (+ pack (rd-null) op (rs-null) ope (GRj-null)) + (nop) ; sufficient implementation + profile + ) +) + +(barrier bar bar OP_03 OPE1_3E + ((fr400 (unit u-barrier)) (fr500 (unit u-barrier))) + "barrier") +(barrier membar membar OP_03 OPE1_3F + ((fr400 (unit u-membar)) (fr500 (unit u-membar))) + "memory barrier") + +; Coprocessor operations +(define-pmacro (cop-op num op) + (dni (.sym cop num) + "Coprocessor operation" + ((UNIT C) (FR500-MAJOR C-2) (MACH frv)) + (.str "cop" num "$pack $s6_1,$CPRi,$CPRj,$CPRk") + (+ pack CPRk op CPRi s6_1 CPRj) + (nop) ; sufficient implementation + () + ) +) + +(cop-op 1 OP_7E) +(cop-op 2 OP_7F) + +(define-pmacro (clear-ne-flag-semantics target_index is_float) + (c-call VOID "@cpu@_clear_ne_flags" target_index is_float) +) + +(define-pmacro (clear-ne-flag-r name op ope reg is_float attr profile comment) + (dni name + (comment) + ((UNIT I01) (FR500-MAJOR I-6) (FR550-MAJOR I-7) (MACH simple,tomcat,fr500,fr550,frv) attr) + (.str name "$pack $" reg "k") + (+ pack (.sym reg k) op (rs-null) ope (GRj-null)) + (sequence () + ; hack to get this referenced for profiling + (c-raw-call VOID "frv_ref_SI" (.sym reg k)) + (clear-ne-flag-semantics (index-of (.sym reg k)) is_float)) + profile + ) +) + +(clear-ne-flag-r clrgr OP_0A OPE1_00 GR 0 NA + ((fr500 (unit u-clrgr)) (fr550 (unit u-clrgr))) + "Clear GR NE flag") +(clear-ne-flag-r clrfr OP_0A OPE1_02 FR 1 FR-ACCESS + ((fr500 (unit u-clrfr)) (fr550 (unit u-clrfr))) + "Clear FR NE flag") + +(define-pmacro (clear-ne-flag-all name op ope is_float attr profile comment) + (dni name + (comment) + ((UNIT I01) (FR500-MAJOR I-6) (FR550-MAJOR I-7) (MACH simple,tomcat,fr500,fr550,frv) attr) + (.str name "$pack") + (+ pack (rd-null) op (rs-null) ope (GRj-null)) + (clear-ne-flag-semantics -1 is_float) + profile + ) +) + +(clear-ne-flag-all clrga OP_0A OPE1_01 0 NA + ((fr500 (unit u-clrgr)) (fr550 (unit u-clrgr))) + "Clear GR NE flag ALL") +(clear-ne-flag-all clrfa OP_0A OPE1_03 1 FR-ACCESS + ((fr500 (unit u-clrfr)) (fr550 (unit u-clrfr))) + "Clear FR NE flag ALL") + +(define-pmacro (commit-semantics target_index is_float) + (c-call VOID "@cpu@_commit" target_index is_float) +) + +(define-pmacro (commit-r name op ope reg is_float attr comment) + (dni name + (comment) + ((UNIT I01) (FR500-MAJOR I-6) (FR550-MAJOR I-7) (MACH frv,fr500,fr550) attr) + (.str name "$pack $" reg "k") + (+ pack (.sym reg k) op (rs-null) ope (GRj-null)) + (commit-semantics (index-of (.sym reg k)) is_float) + ((fr500 (unit u-commit)) (fr550 (unit u-commit))) + ) +) + +(commit-r commitgr OP_0A OPE1_04 GR 0 NA "commit exceptions, specific GR") +(commit-r commitfr OP_0A OPE1_06 FR 1 FR-ACCESS "commit exceptions, specific FR") + +(define-pmacro (commit name op ope is_float attr comment) + (dni name + (comment) + ((UNIT I01) (FR500-MAJOR I-6) (FR550-MAJOR I-7) (MACH frv,fr500,fr550) attr) + (.str name "$pack") + (+ pack (rd-null) op (rs-null) ope (GRj-null)) + (commit-semantics -1 is_float) + ((fr500 (unit u-commit)) (fr550 (unit u-commit))) + ) +) + +(commit commitga OP_0A OPE1_05 0 NA "commit exceptions, any GR") +(commit commitfa OP_0A OPE1_07 1 FR-ACCESS "commit exceptions, any FR") + +(define-pmacro (floating-point-conversion + name op ope conv mode src targ attr comment) + (dni name + (comment) + (.splice (UNIT FMALL) (FR500-MAJOR F-1) (.unsplice attr)) + (.str name "$pack $" src ",$" targ) + (+ pack targ op (rs-null) ope src) + (set targ (conv mode src)) + ((fr500 (unit u-float-convert)) (fr550 (unit u-float-convert))) + ) +) + +(floating-point-conversion fitos OP_79 OPE1_00 float SF FRintj FRk + ((FR550-MAJOR F-2) (MACH simple,tomcat,fr500,fr550,frv)) + "Convert Integer to Single") +(floating-point-conversion fstoi OP_79 OPE1_01 fix SI FRj FRintk + ((FR550-MAJOR F-2) (MACH simple,tomcat,fr500,fr550,frv)) + "Convert Single to Integer") +(floating-point-conversion fitod OP_7A OPE1_00 float DF FRintj FRdoublek + ((MACH frv)) + "Convert Integer to Double") +(floating-point-conversion fdtoi OP_7A OPE1_01 fix SI FRdoublej FRintk + ((MACH frv)) + "Convert Double to Integer") + +(define-pmacro (floating-point-dual-conversion + name op ope conv mode src src_hw targ targ_hw attr comment) + (dni name + (comment) + ((MACH frv) (UNIT FMALL) (FR500-MAJOR F-1) attr) + (.str name "$pack $" src ",$" targ) + (+ pack targ op (rs-null) ope src) + (sequence () + (set targ (conv mode src)) + (set (nextreg targ_hw targ 1) + (conv mode (nextreg src_hw src 1)))) + ((fr500 (unit u-float-dual-convert))) + ) +) + +(floating-point-dual-conversion fditos OP_79 OPE1_10 float SF FRintj h-fr_int FRk h-fr NA "Dual Convert Integer to Single") +(floating-point-dual-conversion fdstoi OP_79 OPE1_11 fix SI FRj h-fr FRintk h-fr_int NA "Dual Convert Single to Integer") + +(define-pmacro (ne-floating-point-dual-conversion + name op ope conv mode src src_hw targ targ_hw attr comment) + (dni name + (comment) + ((MACH frv) (UNIT FMALL) (FR500-MAJOR F-1) NON-EXCEPTING attr) + (.str name "$pack $" src ",$" targ) + (+ pack targ op (rs-null) ope src) + (sequence () + (c-call VOID "@cpu@_set_ne_index" (index-of targ)) + (set targ (conv mode src)) + (c-call VOID "@cpu@_set_ne_index" (add (index-of targ) 1)) + (set (nextreg targ_hw targ 1) + (conv mode (nextreg src_hw src 1)))) + ((fr500 (unit u-float-dual-convert))) + ) +) + +(ne-floating-point-dual-conversion nfditos OP_79 OPE1_30 float SF FRintj h-fr_int FRk h-fr NA "Non excepting dual Convert Integer to Single") +(ne-floating-point-dual-conversion nfdstoi OP_79 OPE1_31 fix SI FRj h-fr FRintk h-fr_int NA "Non excepting dual Convert Single to Integer") + +(define-pmacro (conditional-floating-point-conversion + name op ope conv mode src targ comment) + (dni name + (comment) + ((UNIT FMALL) (FR500-MAJOR F-1) (FR550-MAJOR F-2) (MACH simple,tomcat,fr500,fr550,frv)) + (.str name "$pack $" src ",$" targ ",$CCi,$cond") + (+ pack targ op (rs-null) CCi cond ope src) + (if (eq CCi (or cond 2)) + (set targ (conv mode src))) + ((fr500 (unit u-float-convert)) (fr550 (unit u-float-convert))) + ) +) + +(conditional-floating-point-conversion cfitos OP_6B OPE4_0 float SF FRintj FRk "Conditional convert Integer to Single") +(conditional-floating-point-conversion cfstoi OP_6B OPE4_1 fix SI FRj FRintk "Conditional convert Single to Integer") + +(define-pmacro (ne-floating-point-conversion + name op ope conv mode src targ comment) + (dni name + (comment) + ((UNIT FMALL) (FR500-MAJOR F-1) (FR550-MAJOR F-2) (MACH simple,tomcat,fr500,fr550,frv)) + (.str name "$pack $" src ",$" targ) + (+ pack targ op (rs-null) ope src) + (sequence () + (c-call VOID "@cpu@_set_ne_index" (index-of targ)) + (set targ (conv mode src))) + ((fr500 (unit u-float-convert)) (fr550 (unit u-float-convert))) + ) +) + +(ne-floating-point-conversion nfitos OP_79 OPE1_20 float SF FRintj FRk "NE convert Integer to Single") +(ne-floating-point-conversion nfstoi OP_79 OPE1_21 fix SI FRj FRintk "NE convert Single to Integer") + +(register-transfer fmovs OP_79 OPE1_02 + FRj FRk FMALL + ((FR500-MAJOR F-1) (FR550-MAJOR F-2) (MACH simple,tomcat,fr500,fr550,frv)) + ((fr500 (unit u-fr2fr))) + "Move Single Float") +(register-transfer fmovd OP_7A OPE1_02 + ; TODO -- unit doesn't handle extra register + FRdoublej FRdoublek FM01 + ((FR500-MAJOR F-1) (MACH frv)) + ((fr500 (unit u-fr2fr)) (fr550 (unit u-fr2fr))) + "Move Double Float") + +(dni fdmovs + "Dual move single float" + ((MACH frv) (UNIT FMALL) (FR500-MAJOR F-1)) + "fdmovs$pack $FRj,$FRk" + (+ pack FRk OP_79 (rs-null) OPE1_12 FRj) + (sequence () + (set FRk FRj) + (set (nextreg h-fr FRk 1) (nextreg h-fr FRj 1))) + ; TODO -- unit doesn't handle extra register + ((fr500 (unit u-fr2fr))) +) + +(conditional-register-transfer cfmovs OP_6C OPE4_0 FRj FRk FM01 + ((FR500-MAJOR F-1) (FR550-MAJOR F-2) + (MACH simple,tomcat,fr500,fr550,frv)) + ((fr500 (unit u-fr2fr)) (fr550 (unit u-fr2fr))) + "Conditional move Single Float") + +(define-pmacro (floating-point-neg name src targ op ope attr comment) + (dni name + (comment) + (.splice (UNIT FMALL) (FR500-MAJOR F-1) (.unsplice attr)) + (.str name "$pack $" src ",$" targ) + (+ pack src op (rs-null) ope targ) + (set targ (neg src)) + ((fr500 (unit u-float-arith)) (fr550 (unit u-float-arith))) + ) +) + +(floating-point-neg fnegs FRj FRk OP_79 OPE1_03 ((FR550-MAJOR F-2) (MACH simple,tomcat,fr500,fr550,frv)) "Floating point negate, single") +(floating-point-neg fnegd FRdoublej FRdoublek OP_7A OPE1_03 ((MACH frv)) "Floating point negate, double") + +(dni fdnegs + "Floating point dual negate, single" + ((MACH frv) (UNIT FMALL) (FR500-MAJOR F-1)) + "fdnegs$pack $FRj,$FRk" + (+ pack FRk OP_79 (rs-null) OPE1_13 FRj) + (sequence () + (set FRk (neg FRj)) + (set (nextreg h-fr FRk 1) (neg (nextreg h-fr FRj 1)))) + ((fr500 (unit u-float-dual-arith))) +) + +(dni cfnegs + "Conditional floating point negate, single" + ((UNIT FMALL) (FR500-MAJOR F-1) (FR550-MAJOR F-2) (MACH simple,tomcat,fr500,fr550,frv)) + "cfnegs$pack $FRj,$FRk,$CCi,$cond" + (+ pack FRj OP_6C (rs-null) CCi cond OPE4_1 FRk) + (if (eq CCi (or cond 2)) + (set FRk (neg FRj))) + ((fr500 (unit u-float-arith)) (fr550 (unit u-float-arith))) +) + +(define-pmacro (float-abs name src targ op ope attr comment) + (dni name + (comment) + (.splice (UNIT FMALL) (FR500-MAJOR F-1) (.unsplice attr)) + (.str name "$pack $" src ",$" targ ) + (+ pack targ op (rs-null) ope src) + (set targ (abs src)) + ((fr500 (unit u-float-arith)) (fr550 (unit u-float-arith))) + ) +) + +(float-abs fabss FRj FRk OP_79 OPE1_04 ((FR550-MAJOR F-2) (MACH simple,tomcat,fr500,fr550,frv)) "Float absolute value, single") +(float-abs fabsd FRdoublej FRdoublek OP_7A OPE1_04 ((MACH frv)) "Float absolute value, double") + +(dni fdabss + "Floating point dual absolute value, single" + ((MACH frv) (UNIT FMALL) (FR500-MAJOR F-1)) + "fdabss$pack $FRj,$FRk" + (+ pack FRk OP_79 (rs-null) OPE1_14 FRj) + (sequence () + (set FRk (abs FRj)) + (set (nextreg h-fr FRk 1) (abs (nextreg h-fr FRj 1)))) + ((fr500 (unit u-float-dual-arith))) +) + +(dni cfabss + "Conditional floating point absolute value, single" + ((UNIT FMALL) (FR500-MAJOR F-1) (FR550-MAJOR F-2) (MACH simple,tomcat,fr500,fr550,frv)) + "cfabss$pack $FRj,$FRk,$CCi,$cond" + (+ pack FRj OP_6C (rs-null) CCi cond OPE4_2 FRk) + (if (eq CCi (or cond 2)) + (set FRk (abs FRj))) + ((fr500 (unit u-float-arith)) (fr550 (unit u-float-arith))) +) + +(dni fsqrts + "Square root single" + ((UNIT FM01) (FR500-MAJOR F-4) (FR550-MAJOR F-3) (MACH simple,tomcat,fr500,fr550,frv)) + "fsqrts$pack $FRj,$FRk" + (+ pack FRk OP_79 (rs-null) OPE1_05 FRj) + (set FRk (sqrt SF FRj)) + ((fr500 (unit u-float-sqrt)) (fr550 (unit u-float-sqrt))) +) + +(dni fdsqrts + "Dual square root single" + ((MACH frv) (UNIT FM01) (FR500-MAJOR F-4)) + "fdsqrts$pack $FRj,$FRk" + (+ pack FRk OP_79 (rs-null) OPE1_15 FRj) + (sequence () + (set FRk (sqrt SF FRj)) + (set (nextreg h-fr FRk 1) (sqrt (nextreg h-fr FRj 1)))) + ((fr500 (unit u-float-dual-sqrt))) +) + +(dni nfdsqrts + "Non excepting Dual square root single" + ((MACH frv) (UNIT FM01) (FR500-MAJOR F-4) NON-EXCEPTING) + "nfdsqrts$pack $FRj,$FRk" + (+ pack FRk OP_79 (rs-null) OPE1_35 FRj) + (sequence () + (c-call VOID "@cpu@_set_ne_index" (index-of FRk)) + (set FRk (sqrt SF FRj)) + (c-call VOID "@cpu@_set_ne_index" (add (index-of FRk) 1)) + (set (nextreg h-fr FRk 1) (sqrt (nextreg h-fr FRj 1)))) + ((fr500 (unit u-float-dual-sqrt))) +) + +(dni fsqrtd + "Square root double" + ((UNIT FM01) (FR500-MAJOR F-4) (MACH frv)) + "fsqrtd$pack $FRdoublej,$FRdoublek" + (+ pack FRdoublek OP_7A (rs-null) OPE1_05 FRdoublej) + (set FRdoublek (sqrt DF FRdoublej)) + ((fr500 (unit u-float-sqrt))) +) + +(dni cfsqrts + "Conditional square root single" + ((UNIT FM01) (FR500-MAJOR F-4) (FR550-MAJOR F-3) (MACH simple,tomcat,fr500,fr550,frv)) + "cfsqrts$pack $FRj,$FRk,$CCi,$cond" + (+ pack FRk OP_6E (rs-null) CCi cond OPE4_2 FRj) + (if (eq CCi (or cond 2)) + (set FRk (sqrt SF FRj))) + ((fr500 (unit u-float-sqrt)) (fr550 (unit u-float-sqrt))) +) + +(dni nfsqrts + "Non exception square root, single" + ((UNIT FM01) (FR500-MAJOR F-4) (FR550-MAJOR F-3) (MACH simple,tomcat,fr500,fr550,frv)) + "nfsqrts$pack $FRj,$FRk" + (+ pack FRk OP_79 (rs-null) OPE1_25 FRj) + (sequence () + (c-call VOID "@cpu@_set_ne_index" (index-of FRk)) + (set FRk (sqrt SF FRj))) + ((fr500 (unit u-float-sqrt)) (fr550 (unit u-float-sqrt))) +) + +(define-pmacro (float-binary-op-s name pipe attr operation op ope comment) + (dni name + (comment) + (.splice (UNIT pipe) (MACH simple,tomcat,fr500,fr550,frv) (.unsplice attr)) + (.str name "$pack $FRi,$FRj,$FRk") + (+ pack FRk op FRi ope FRj) + (set FRk (operation FRi FRj)) + ((fr500 (unit u-float-arith)) (fr550 (unit u-float-arith))) + ) +) + +(float-binary-op-s fadds FMALL ((FR500-MAJOR F-2) (FR550-MAJOR F-2)) add OP_79 OPE1_06 "add single float") +(float-binary-op-s fsubs FMALL ((FR500-MAJOR F-2) (FR550-MAJOR F-2)) sub OP_79 OPE1_07 "sub single float") +(float-binary-op-s fmuls FM01 ((FR500-MAJOR F-3) (FR550-MAJOR F-3)) mul OP_79 OPE1_08 "mul single float") + +(dni fdivs + "div single float" + ((UNIT FM01) (FR500-MAJOR F-4) (FR550-MAJOR F-3) (MACH simple,tomcat,fr500,fr550,frv)) + "fdivs$pack $FRi,$FRj,$FRk" + (+ pack FRk OP_79 FRi OPE1_09 FRj) + (set FRk (div FRi FRj)) + ((fr500 (unit u-float-div)) + (fr550 (unit u-float-div))) +) + +(define-pmacro (float-binary-op-d name operation op ope major comment) + (dni name + (comment) + ((UNIT FMALL) (FR500-MAJOR major) (MACH frv)) + (.str name "$pack $FRdoublei,$FRdoublej,$FRdoublek") + (+ pack FRdoublek op FRdoublei ope FRdoublej) + (set FRdoublek (operation FRdoublei FRdoublej)) + ((fr500 (unit u-float-arith))) + ) +) + +(float-binary-op-d faddd add OP_7A OPE1_06 F-2 "add double float") +(float-binary-op-d fsubd sub OP_7A OPE1_07 F-2 "sub double float") +(float-binary-op-d fmuld mul OP_7A OPE1_08 F-3 "mul double float") +(float-binary-op-d fdivd div OP_7A OPE1_09 F-4 "div double float") + +(define-pmacro (conditional-float-binary-op name pipe attr operation op ope profile comment) + (dni name + (comment) + (.splice (UNIT pipe) (MACH simple,tomcat,fr500,fr550,frv) + (.unsplice attr)) + (.str name "$pack $FRi,$FRj,$FRk,$CCi,$cond") + (+ pack FRk op FRi CCi cond ope FRj) + (if (eq CCi (or cond 2)) + (set FRk (operation FRi FRj))) + profile + ) +) + +(conditional-float-binary-op cfadds FMALL ((FR500-MAJOR F-2) (FR550-MAJOR F-2)) add OP_6D OPE4_0 + ((fr500 (unit u-float-arith)) (fr550 (unit u-float-arith))) + "cond add single") +(conditional-float-binary-op cfsubs FMALL ((FR500-MAJOR F-2) (FR550-MAJOR F-2)) sub OP_6D OPE4_1 + ((fr500 (unit u-float-arith)) (fr550 (unit u-float-arith))) + "cond sub single") +(conditional-float-binary-op cfmuls FM01 ((FR500-MAJOR F-3) (FR550-MAJOR F-3)) mul OP_6E OPE4_0 + ((fr500 (unit u-float-arith)) (fr550 (unit u-float-arith))) + "cond mul single") +(conditional-float-binary-op cfdivs FM01 ((FR500-MAJOR F-4) (FR550-MAJOR F-3)) div OP_6E OPE4_1 + ((fr500 (unit u-float-div)) (fr550 (unit u-float-div))) + "cond div single") + +(define-pmacro (ne-float-binary-op name pipe attr operation op ope profile comment) + (dni name + (comment) + (.splice (UNIT pipe) (MACH simple,tomcat,fr500,fr550,frv) + (.unsplice attr)) + (.str name "$pack $FRi,$FRj,$FRk") + (+ pack FRk op FRi ope FRj) + (sequence () + (c-call VOID "@cpu@_set_ne_index" (index-of FRk)) + (set FRk (operation FRi FRj))) + profile + ) +) + +(ne-float-binary-op nfadds FMALL ((FR500-MAJOR F-2) (FR550-MAJOR F-2)) add OP_79 OPE1_26 + ((fr500 (unit u-float-arith)) (fr550 (unit u-float-arith))) + "ne add single") +(ne-float-binary-op nfsubs FMALL ((FR500-MAJOR F-2) (FR550-MAJOR F-2)) sub OP_79 OPE1_27 + ((fr500 (unit u-float-arith)) (fr550 (unit u-float-arith))) + "ne sub single") +(ne-float-binary-op nfmuls FM01 ((FR500-MAJOR F-3) (FR550-MAJOR F-3)) mul OP_79 OPE1_28 + ((fr500 (unit u-float-arith)) (fr550 (unit u-float-arith))) + "ne mul single") +(ne-float-binary-op nfdivs FM01 ((FR500-MAJOR F-4) (FR550-MAJOR F-3)) div OP_79 OPE1_29 + ((fr500 (unit u-float-div)) (fr550 (unit u-float-div))) + "ne div single") + +(define-pmacro (fcc-eq) 8) +(define-pmacro (fcc-lt) 4) +(define-pmacro (fcc-gt) 2) +(define-pmacro (fcc-uo) 1) + +(define-pmacro (compare-and-set-fcc arg1 arg2 fcc) + (if (gt arg1 arg2) + (set fcc (fcc-gt)) + (if (eq arg1 arg2) + (set fcc (fcc-eq)) + (if (lt arg1 arg2) + (set fcc (fcc-lt)) + (set fcc (fcc-uo))))) +) + +(dni fcmps + "compare single float" + ((UNIT FMALL) (FR500-MAJOR F-2) (FR550-MAJOR F-2) (MACH simple,tomcat,fr500,fr550,frv)) + "fcmps$pack $FRi,$FRj,$FCCi_2" + (+ pack (cond-null) FCCi_2 OP_79 FRi OPE1_0A FRj) + (compare-and-set-fcc FRi FRj FCCi_2) + ((fr500 (unit u-float-compare)) (fr550 (unit u-float-compare))) +) + +(dni fcmpd + "compare double float" + ((UNIT FMALL) (FR500-MAJOR F-2) (MACH frv)) + "fcmpd$pack $FRdoublei,$FRdoublej,$FCCi_2" + (+ pack (cond-null) FCCi_2 OP_7A FRdoublei OPE1_0A FRdoublej) + (compare-and-set-fcc FRdoublei FRdoublej FCCi_2) + ((fr500 (unit u-float-compare))) +) + +(dni cfcmps + "Conditional compare single, float" + ((UNIT FMALL) (FR500-MAJOR F-2) (FR550-MAJOR F-2) (MACH simple,tomcat,fr500,fr550,frv)) + "cfcmps$pack $FRi,$FRj,$FCCi_2,$CCi,$cond" + (+ pack (cond-null) FCCi_2 OP_6D FRi CCi cond OPE4_2 FRj) + (if (eq CCi (or cond 2)) + (compare-and-set-fcc FRi FRj FCCi_2)) + ((fr500 (unit u-float-compare)) (fr550 (unit u-float-compare))) +) + +(dni fdcmps + "float dual compare single" + ((UNIT FMALL) (FR500-MAJOR F-6) (FR550-MAJOR F-4) (MACH simple,tomcat,fr500,fr550,frv)) + "fdcmps$pack $FRi,$FRj,$FCCi_2" + (+ pack (cond-null) FCCi_2 OP_79 FRi OPE1_1A FRj) + (sequence () + (compare-and-set-fcc FRi FRj FCCi_2) + (compare-and-set-fcc (nextreg h-fr FRi 1) (nextreg h-fr FRj 1) + (nextreg h-fccr FCCi_2 1))) + ((fr500 (unit u-float-dual-compare)) (fr550 (unit u-float-dual-compare))) +) + +(define-pmacro (float-mul-with-add name add_sub arg1 arg2 targ op ope comment) + (dni name + (comment) + ((UNIT FMALL) (FR500-MAJOR F-5) (MACH frv)) + (.str name "$pack $" arg1 ",$" arg2 ",$" targ) + (+ pack targ op arg1 ope arg2) + (set targ (add_sub (mul arg1 arg2) targ)) + ((fr500 (unit u-float-dual-arith))) + ) +) + +(float-mul-with-add fmadds add FRi FRj FRk OP_79 OPE1_0B "mul with add, single") +(float-mul-with-add fmsubs sub FRi FRj FRk OP_79 OPE1_0C "mul with sub, single") + +(float-mul-with-add fmaddd add FRdoublei FRdoublej FRdoublek OP_7A OPE1_0B "mul with add, double") +(float-mul-with-add fmsubd sub FRdoublei FRdoublej FRdoublek OP_7A OPE1_0C "mul with sub, double") + +(dni fdmadds + "Float dual multiply with add" + ((UNIT FMALL) (FR500-MAJOR F-5) (MACH frv)) + "fdmadds$pack $FRi,$FRj,$FRk" + (+ pack FRk OP_79 FRi OPE1_1B FRj) + (sequence () + (set FRk (add (mul FRi FRj) FRk)) + (set (nextreg h-fr FRk 1) + (add (mul (nextreg h-fr FRi 1) (nextreg h-fr FRj 1)) + (nextreg h-fr FRk 1)))) + ; TODO dual registers not referenced for profiling + ((fr500 (unit u-float-dual-arith))) +) + +(dni nfdmadds + "Non excepting float dual multiply with add" + ((UNIT FMALL) (FR500-MAJOR F-5) (MACH frv)) + "nfdmadds$pack $FRi,$FRj,$FRk" + (+ pack FRk OP_79 FRi OPE1_3B FRj) + (sequence () + (c-call VOID "@cpu@_set_ne_index" (index-of FRk)) + (set FRk (add (mul FRi FRj) FRk)) + (c-call VOID "@cpu@_set_ne_index" (add (index-of FRk) 1)) + (set (nextreg h-fr FRk 1) + (add (mul (nextreg h-fr FRi 1) (nextreg h-fr FRj 1)) + (nextreg h-fr FRk 1)))) + ; TODO dual registers not referenced for profiling + ((fr500 (unit u-float-dual-arith))) +) + +(define-pmacro (conditional-float-mul-with-add + name add_sub arg1 arg2 targ op ope comment) + (dni name + (comment) + ((UNIT FMALL) (FR500-MAJOR F-5) (MACH frv) CONDITIONAL) + (.str name "$pack $FRi,$FRj,$FRk,$CCi,$cond") + (+ pack FRk op FRi CCi cond ope FRj) + (if (eq CCi (or cond 2)) + (set targ (add_sub (mul arg1 arg2) targ))) + ((fr500 (unit u-float-dual-arith))) + ) +) + +(conditional-float-mul-with-add cfmadds add FRi FRj FRk OP_6F OPE4_0 "conditional mul with add, single") +(conditional-float-mul-with-add cfmsubs sub FRi FRj FRk OP_6F OPE4_1 "conditional mul with sub, single") + +(define-pmacro (ne-float-mul-with-add name add_sub arg1 arg2 targ op ope comment) + (dni name + (comment) + ((UNIT FMALL) (FR500-MAJOR F-5) (MACH frv) NON-EXCEPTING) + (.str name "$pack $" arg1 ",$" arg2 ",$" targ) + (+ pack targ op arg1 ope arg2) + (sequence () + (c-call VOID "@cpu@_set_ne_index" (index-of targ)) + (set targ (add_sub (mul arg1 arg2) targ))) + ((fr500 (unit u-float-dual-arith))) + ) +) + +(ne-float-mul-with-add nfmadds add FRi FRj FRk OP_79 OPE1_2B "non excepting mul with add, single") +(ne-float-mul-with-add nfmsubs sub FRi FRj FRk OP_79 OPE1_2C "non excepting mul with sub, single") + +(define-pmacro (float-parallel-mul-add-semantics cond add_sub arg1 arg2 targ) + (if cond + (sequence () + (set targ (mul arg1 arg2)) + (set (nextreg h-fr targ 1) + (add_sub (nextreg h-fr arg1 1) (nextreg h-fr arg2 1))))) +) + +(define-pmacro (float-parallel-mul-add + name add_sub arg1 arg2 targ op ope comment) + (dni name + (comment) + ((UNIT FM01) (FR500-MAJOR F-5) (FR550-MAJOR F-4) (MACH simple,tomcat,fr500,fr550,frv)) + (.str name "$pack $" arg1 ",$" arg2 ",$" targ) + (+ pack targ op arg1 ope arg2) + (float-parallel-mul-add-semantics 1 add_sub arg1 arg2 targ) + ((fr500 (unit u-float-dual-arith)) (fr550 (unit u-float-dual-arith))) + ) +) + +(float-parallel-mul-add fmas add FRi FRj FRk OP_79 OPE1_0E "parallel mul/add, single") +(float-parallel-mul-add fmss sub FRi FRj FRk OP_79 OPE1_0F "parallel mul/sub, single") + +(define-pmacro (float-dual-parallel-mul-add-semantics add_sub arg1 arg2 targ) + (sequence () + (set targ (mul arg1 arg2)) + (set (nextreg h-fr targ 1) + (add_sub (nextreg h-fr arg1 1) (nextreg h-fr arg2 1))) + (set (nextreg h-fr targ 2) + (mul (nextreg h-fr arg1 2) (nextreg h-fr arg2 2))) + (set (nextreg h-fr targ 3) + (add_sub (nextreg h-fr arg1 3) (nextreg h-fr arg2 3)))) +) + +(define-pmacro (float-dual-parallel-mul-add + name add_sub arg1 arg2 targ op ope comment) + (dni name + (comment) + ((UNIT FM01) (FR500-MAJOR F-5) (MACH frv)) + (.str name "$pack $" arg1 ",$" arg2 ",$" targ) + (+ pack targ op arg1 ope arg2) + (float-dual-parallel-mul-add-semantics add_sub arg1 arg2 targ) + () + ) +) + +(float-dual-parallel-mul-add fdmas add FRi FRj FRk OP_79 OPE1_1C "dual parallel mul/add, single") +(float-dual-parallel-mul-add fdmss sub FRi FRj FRk OP_79 OPE1_1D "dual parallel mul/sub, single") + +(define-pmacro (ne-float-dual-parallel-mul-add-semantics add_sub arg1 arg2 targ) + (sequence () + (c-call VOID "@cpu@_set_ne_index" (index-of targ)) + (c-call VOID "@cpu@_set_ne_index" (add (index-of targ) 1)) + (c-call VOID "@cpu@_set_ne_index" (add (index-of targ) 2)) + (c-call VOID "@cpu@_set_ne_index" (add (index-of targ) 3)) + (set targ (mul arg1 arg2)) + (set (nextreg h-fr targ 1) + (add_sub (nextreg h-fr arg1 1) (nextreg h-fr arg2 1))) + (set (nextreg h-fr targ 2) + (mul (nextreg h-fr arg1 2) (nextreg h-fr arg2 2))) + (set (nextreg h-fr targ 3) + (add_sub (nextreg h-fr arg1 3) (nextreg h-fr arg2 3)))) +) + +(define-pmacro (ne-float-dual-parallel-mul-add + name add_sub arg1 arg2 targ op ope comment) + (dni name + (comment) + ((UNIT FM01) (FR500-MAJOR F-5) (MACH frv)) + (.str name "$pack $" arg1 ",$" arg2 ",$" targ) + (+ pack targ op arg1 ope arg2) + (ne-float-dual-parallel-mul-add-semantics add_sub arg1 arg2 targ) + () + ) +) + +(ne-float-dual-parallel-mul-add nfdmas add FRi FRj FRk OP_79 OPE1_3C "non excepting dual parallel mul/add, single") +(ne-float-dual-parallel-mul-add nfdmss sub FRi FRj FRk OP_79 OPE1_3D "non excepting dual parallel mul/sub, single") + +(define-pmacro (conditional-float-parallel-mul-add name add_sub op ope comment) + (dni name + (comment) + ((UNIT FM01) (FR500-MAJOR F-5) (FR550-MAJOR F-4) CONDITIONAL (MACH simple,tomcat,fr500,fr550,frv)) + (.str name "$pack $FRi,$FRj,$FRk,$CCi,$cond") + (+ pack FRk op FRi CCi cond ope FRj) + (float-parallel-mul-add-semantics (eq CCi (or cond 2)) + add_sub FRi FRj FRk) + ((fr500 (unit u-float-dual-arith)) (fr550 (unit u-float-dual-arith))) + ) +) + +(conditional-float-parallel-mul-add cfmas add OP_6F OPE4_2 "conditional parallel mul/add, single") +(conditional-float-parallel-mul-add cfmss sub OP_6F OPE4_3 "conditional parallel mul/sub, single") + +(define-pmacro (float-parallel-mul-add-double-semantics add_sub arg1 arg2 targ) + (sequence () + (set targ (ftrunc SF (mul DF (fext DF arg1) (fext DF arg2)))) + (set (nextreg h-fr targ 1) + (ftrunc SF (add_sub DF + (fext DF (nextreg h-fr arg1 1)) + (fext DF (nextreg h-fr arg2 1)))))) +) + +(define-pmacro (float-parallel-mul-add-double + name add_sub arg1 arg2 targ op ope comment) + (dni name + (comment) + ((UNIT FM01) (FR500-MAJOR F-5) (MACH frv)) + (.str name "$pack $" arg1 ",$" arg2 ",$" targ) + (+ pack targ op arg1 ope arg2) + (float-parallel-mul-add-double-semantics add_sub arg1 arg2 targ) + () + ) +) + +(float-parallel-mul-add-double fmad add FRi FRj FRk OP_7A OPE1_0E "parallel mul/add, double") +(float-parallel-mul-add-double fmsd sub FRi FRj FRk OP_7A OPE1_0F "parallel mul/sub, double") + +(define-pmacro (ne-float-parallel-mul-add name add_sub op ope comment) + (dni name + (comment) + ((UNIT FM01) (FR500-MAJOR F-5) (FR550-MAJOR F-4) (MACH simple,tomcat,fr500,fr550,frv)) + (.str name "$pack $FRi,$FRj,$FRk") + (+ pack FRk op FRi ope FRj) + (sequence () + (c-call VOID "@cpu@_set_ne_index" (index-of FRk)) + (set FRk (mul FRi FRj)) + (c-call VOID "@cpu@_set_ne_index" (add (index-of FRk) 1)) + (set (nextreg h-fr FRk 1) + (add_sub (nextreg h-fr FRi 1) (nextreg h-fr FRj 1)))) + ((fr500 (unit u-float-dual-arith)) (fr550 (unit u-float-dual-arith))) + ) +) + +(ne-float-parallel-mul-add nfmas add OP_79 OPE1_2E "ne parallel mul/add,single") +(ne-float-parallel-mul-add nfmss sub OP_79 OPE1_2F "ne parallel mul/sub,single") + +(define-pmacro (float-dual-arith name attr oper1 oper2 op ope comment) + (dni name + (comment) + (.splice (UNIT FM01) (.unsplice attr)) + (.str name "$pack $FRi,$FRj,$FRk") + (+ pack FRk op FRi ope FRj) + (sequence () + (set FRk (oper1 FRi FRj)) + (set (nextreg h-fr FRk 1) + (oper2 (nextreg h-fr FRi 1) (nextreg h-fr FRj 1)))) + ((fr500 (unit u-float-dual-arith)) (fr550 (unit u-float-dual-arith))) + ) +) + +(float-dual-arith fdadds ((FR500-MAJOR F-6) (FR550-MAJOR F-4) (MACH simple,tomcat,fr500,fr550,frv)) add add OP_79 OPE1_16 "dual add, single") +(float-dual-arith fdsubs ((FR500-MAJOR F-6) (FR550-MAJOR F-4) (MACH simple,tomcat,fr500,fr550,frv)) sub sub OP_79 OPE1_17 "dual sub, single") +(float-dual-arith fdmuls ((FR500-MAJOR F-7) (FR550-MAJOR F-4) (MACH simple,tomcat,fr500,fr550,frv)) mul mul OP_79 OPE1_18 "dual mul, single") +(float-dual-arith fddivs ((FR500-MAJOR F-7) (MACH frv)) div div OP_79 OPE1_19 "dual div,single") +(float-dual-arith fdsads ((FR500-MAJOR F-6) (FR550-MAJOR F-4) (MACH simple,tomcat,fr500,fr550,frv)) add sub OP_79 OPE1_1E "dual add/sub, single") + +(dni fdmulcs + "Float dual cross multiply single" + ((UNIT FM01) (FR500-MAJOR F-7) (FR550-MAJOR F-4) (MACH simple,tomcat,fr500,fr550,frv)) + "fdmulcs$pack $FRi,$FRj,$FRk" + (+ pack FRk OP_79 FRi OPE1_1F FRj) + (sequence () + (set FRk (mul FRi (nextreg h-fr FRj 1))) + (set (nextreg h-fr FRk 1) (mul (nextreg h-fr FRi 1) FRj))) + ((fr500 (unit u-float-dual-arith)) (fr550 (unit u-float-dual-arith))) +) + +(dni nfdmulcs + "NE float dual cross multiply single" + ((UNIT FM01) (FR500-MAJOR F-7) (FR550-MAJOR F-4) (MACH simple,tomcat,fr500,fr550,frv)) + "nfdmulcs$pack $FRi,$FRj,$FRk" + (+ pack FRk OP_79 FRi OPE1_3F FRj) + (sequence () + (c-call VOID "@cpu@_set_ne_index" (index-of FRk)) + (set FRk (mul FRi (nextreg h-fr FRj 1))) + (c-call VOID "@cpu@_set_ne_index" (add (index-of FRk) 1)) + (set (nextreg h-fr FRk 1) (mul (nextreg h-fr FRi 1) FRj))) + ((fr500 (unit u-float-dual-arith)) (fr550 (unit u-float-dual-arith))) +) + +(define-pmacro (ne-float-dual-arith name attr oper1 oper2 op ope comment) + (dni name + (comment) + (.splice (UNIT FM01) (.unsplice attr)) + (.str name "$pack $FRi,$FRj,$FRk") + (+ pack FRk op FRi ope FRj) + (sequence () + (c-call VOID "@cpu@_set_ne_index" (index-of FRk)) + (set FRk (oper1 FRi FRj)) + (c-call VOID "@cpu@_set_ne_index" (add (index-of FRk) 1)) + (set (nextreg h-fr FRk 1) + (oper2 (nextreg h-fr FRi 1) (nextreg h-fr FRj 1)))) + ((fr500 (unit u-float-dual-arith)) (fr550 (unit u-float-dual-arith))) + ) +) + +(ne-float-dual-arith nfdadds ((FR500-MAJOR F-6) (FR550-MAJOR F-4) (MACH simple,tomcat,fr500,fr550,frv)) add add OP_79 OPE1_36 "ne dual add, single") +(ne-float-dual-arith nfdsubs ((FR500-MAJOR F-6) (FR550-MAJOR F-4) (MACH simple,tomcat,fr500,fr550,frv)) sub sub OP_79 OPE1_37 "ne dual sub, single") +(ne-float-dual-arith nfdmuls ((FR500-MAJOR F-7) (FR550-MAJOR F-4) (MACH simple,tomcat,fr500,fr550,frv)) mul mul OP_79 OPE1_38 "ne dual mul, single") +(ne-float-dual-arith nfddivs ((FR500-MAJOR F-7) (MACH frv)) div div OP_79 OPE1_39 "ne dual div,single") +(ne-float-dual-arith nfdsads ((FR500-MAJOR F-6) (FR550-MAJOR F-4) (MACH simple,tomcat,fr500,fr550,frv)) add sub OP_79 OPE1_3E "ne dual add/sub, single") + +(dni nfdcmps + "non-excepting dual float compare" + ((UNIT FM01) (FR500-MAJOR F-6) (MACH simple,tomcat,frv)) + "nfdcmps$pack $FRi,$FRj,$FCCi_2" + (+ pack (cond-null) FCCi_2 OP_79 FRi OPE1_3A FRj) + (sequence () + (c-call VOID "@cpu@_set_ne_index" (index-of FRk)) + (compare-and-set-fcc FRi FRj FCCi_2) + (c-call VOID "@cpu@_set_ne_index" (add (index-of FRk) 1)) + (compare-and-set-fcc (nextreg h-fr FRi 1) (nextreg h-fr FRj 1) + (nextreg h-fccr FCCi_2 1))) + ((fr500 (unit u-float-dual-compare))) +) + +; Media Instructions +; +(define-pmacro (halfword hilo arg offset) + (reg (.sym h-fr_ hilo) (add (index-of arg) offset))) + +(dni mhsetlos + "Media set lower signed 12 bits" + ((UNIT FMALL) (MACH fr400,fr550) (FR550-MAJOR M-5) (FR400-MAJOR M-1)) + "mhsetlos$pack $u12,$FRklo" + (+ pack FRklo OP_78 OPE1_20 u12) + (set FRklo u12) + ((fr400 (unit u-media-hilo)) (fr550 (unit u-media-set (out FRintk FRklo)))) +) + +(dni mhsethis + "Media set upper signed 12 bits" + ((UNIT FMALL) (MACH fr400,fr550) (FR550-MAJOR M-5) (FR400-MAJOR M-1)) + "mhsethis$pack $u12,$FRkhi" + (+ pack FRkhi OP_78 OPE1_22 u12) + (set FRkhi u12) + ((fr400 (unit u-media-hilo)) (fr550 (unit u-media-set (out FRintk FRkhi)))) +) + +(dni mhdsets + "Media dual set halfword signed 12 bits" + ((UNIT FMALL) (MACH fr400,fr550) (FR550-MAJOR M-5) (FR400-MAJOR M-1)) + "mhdsets$pack $u12,$FRintk" + (+ pack FRintk OP_78 OPE1_24 u12) + (sequence () + ; hack to get FRintk passed to modelling functions + (set FRintk (c-raw-call SI "frv_ref_SI" FRintk)) + (set (halfword hi FRintk 0) u12) + (set (halfword lo FRintk 0) u12)) + ((fr400 (unit u-media-1)) (fr550 (unit u-media-set))) +) + +(define-pmacro (set-5-semantics target value) + (sequence ((HI tmp)) + (set tmp target) + (set tmp (and tmp #x07ff)) + (set tmp (or tmp (sll (and s5 #x1f) 11))) + (set target tmp)) +) + +(define-pmacro (media-set-5 name hilo op ope comment) + (dni name + (comment) + ((UNIT FMALL) (MACH fr400,fr550) (FR550-MAJOR M-5) (FR400-MAJOR M-1)) + (.str name "$pack $s5,$FRk" hilo) + (+ pack (.sym FRk hilo) op (FRi-null) ope (misc-null-11) s5) + (set-5-semantics (.sym FRk hilo) s5) + ((fr400 (unit u-media-hilo)) (fr550 (unit u-media-set (out FRintk (.sym FRk hilo))))) + ) +) + +(media-set-5 mhsetloh lo OP_78 OPE1_21 "Media set upper 5 bits lo") +(media-set-5 mhsethih hi OP_78 OPE1_23 "Media set upper 5 bits hi") + +(dni mhdseth + "Media dual set halfword upper 5 bits" + ((UNIT FMALL) (MACH fr400,fr550) (FR550-MAJOR M-5) (FR400-MAJOR M-1)) + "mhdseth$pack $s5,$FRintk" + (+ pack FRintk OP_78 (FRi-null) OPE1_25 (misc-null-11) s5) + (sequence () + ; hack to get FRintk passed to modelling functions + (set FRintk (c-raw-call SI "frv_ref_SI" FRintk)) + (set-5-semantics (halfword hi FRintk 0) s5) + (set-5-semantics (halfword lo FRintk 0) s5)) + ((fr400 (unit u-media-1)) (fr550 (unit u-media-set))) +) + +(define-pmacro (media-logic-r-r name operation op ope comment) + (dni name + (comment) + ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2) (FR400-MAJOR M-1)) + (.str name "$pack $FRinti,$FRintj,$FRintk") + (+ pack FRintk op FRinti ope FRintj) + (set FRintk (operation FRinti FRintj)) + ((fr400 (unit u-media-1)) + (fr500 (unit u-media)) (fr550 (unit u-media))) + ) +) + +(media-logic-r-r mand and OP_7B OPE1_00 "and reg/reg") +(media-logic-r-r mor or OP_7B OPE1_01 "or reg/reg") +(media-logic-r-r mxor xor OP_7B OPE1_02 "xor reg/reg") + +(define-pmacro (conditional-media-logic name operation op ope comment) + (dni name + (comment) + ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2) (FR400-MAJOR M-1) CONDITIONAL) + (.str name "$pack $FRinti,$FRintj,$FRintk,$CCi,$cond") + (+ pack FRintk op FRinti CCi cond ope FRintj) + (if (eq CCi (or cond 2)) + (set FRintk (operation FRinti FRintj))) + ((fr400 (unit u-media-1)) + (fr500 (unit u-media)) (fr550 (unit u-media))) + ) +) + +(conditional-media-logic cmand and OP_70 OPE4_0 "conditional and reg/reg") +(conditional-media-logic cmor or OP_70 OPE4_1 "conditional or reg/reg") +(conditional-media-logic cmxor xor OP_70 OPE4_2 "conditional xor reg/reg") + +(dni mnot + ("mnot") + ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2) (FR400-MAJOR M-1)) + ("mnot$pack $FRintj,$FRintk") + (+ pack FRintk OP_7B (rs-null) OPE1_03 FRintj) + (set FRintk (inv FRintj)) + ((fr400 (unit u-media-1)) + (fr500 (unit u-media)) (fr550 (unit u-media))) +) + +(dni cmnot + ("cmnot") + ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2) (FR400-MAJOR M-1) CONDITIONAL) + ("cmnot$pack $FRintj,$FRintk,$CCi,$cond") + (+ pack FRintk OP_70 (rs-null) CCi cond OPE4_3 FRintj) + (if (eq CCi (or cond 2)) + (set FRintk (inv FRintj))) + ((fr400 (unit u-media-1)) + (fr500 (unit u-media)) (fr550 (unit u-media))) +) + +(define-pmacro (media-rotate-r-r name operation op ope comment) + (dni name + (comment) + ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) (FR400-MAJOR M-1)) + (.str name "$pack $FRinti,$u6,$FRintk") + (+ pack FRintk op FRinti ope u6) + (set FRintk (operation FRinti (and u6 #x1f))) + ((fr400 (unit u-media-3)) + (fr500 (unit u-media)) (fr550 (unit u-media))) + ) +) + +(media-rotate-r-r mrotli rol OP_7B OPE1_04 "rotate left reg/reg") +(media-rotate-r-r mrotri ror OP_7B OPE1_05 "rotate right reg/reg") + +(define-pmacro (media-cut-r-r name arg op ope comment) + (dni name + (comment) + ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) (FR400-MAJOR M-2)) + (.str name "$pack $FRinti,$" arg ",$FRintk") + (+ pack FRintk op FRinti ope arg) + (set FRintk (c-call SI "@cpu@_cut" FRinti (nextreg h-fr_int FRinti 1) arg)) + ((fr400 (unit u-media-3)) + (fr500 (unit u-media)) (fr550 (unit u-media))) + ) +) + +(media-cut-r-r mwcut FRintj OP_7B OPE1_06 "media cut") +(media-cut-r-r mwcuti u6 OP_7B OPE1_07 "media cut") + +(define-pmacro (media-cut-acc name arg op ope comment) + (dni name + (comment) + ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) (FR400-MAJOR M-1)) + (.str name "$pack $ACC40Si,$" arg ",$FRintk") + (+ pack FRintk op ACC40Si ope arg) + (set FRintk (c-call SI "@cpu@_media_cut" ACC40Si arg)) + ((fr400 (unit u-media-4)) + (fr500 (unit u-media)) (fr550 (unit u-media-3-acc))) + ) +) + +(media-cut-acc mcut FRintj OP_7B OPE1_2C "media accumulator cut reg") +(media-cut-acc mcuti s6 OP_7B OPE1_2E "media accumulator cut immed") + +(define-pmacro (media-cut-acc-ss name arg op ope comment) + (dni name + (comment) + ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) (FR400-MAJOR M-1)) + (.str name "$pack $ACC40Si,$" arg ",$FRintk") + (+ pack FRintk op ACC40Si ope arg) + (set FRintk (c-call SI "@cpu@_media_cut_ss" ACC40Si arg)) + ((fr400 (unit u-media-4)) + (fr500 (unit u-media)) (fr550 (unit u-media-3-acc))) + ) +) + +(media-cut-acc-ss mcutss FRintj OP_7B OPE1_2D "media accumulator cut reg with saturation") +(media-cut-acc-ss mcutssi s6 OP_7B OPE1_2F "media accumulator cut immed with saturation") + +; Dual Media Instructions +; +(define-pmacro (register-unaligned register alignment) + (and (index-of register) (sub alignment 1)) +) + +(dni mdcutssi + "Media dual cut with signed saturation" + ((UNIT FMLOW) (MACH fr400,fr550) (FR550-MAJOR M-3) (FR400-MAJOR M-2)) + "mdcutssi$pack $ACC40Si,$s6,$FRintkeven" + (+ pack FRintkeven OP_78 ACC40Si OPE1_0E s6) + (if (register-unaligned ACC40Si 2) + (c-call VOID "@cpu@_media_acc_not_aligned") + (if (register-unaligned FRintkeven 2) + (c-call VOID "@cpu@_media_register_not_aligned") + (sequence () + (set FRintkeven (c-call SI "@cpu@_media_cut_ss" ACC40Si s6)) + (set (nextreg h-fr_int FRintkeven 1) + (c-call SI "@cpu@_media_cut_ss" + (nextreg h-acc40S ACC40Si 1) s6))))) + ((fr400 (unit u-media-4-acc-dual + (out FRintk FRintkeven))) (fr550 (unit u-media-3-acc-dual))) +) + +; The (add (xxxx) (mul arg 0)) is a hack to get a reference to arg generated +; so it will be passed to the unit modelers. YUCK!!!!! +(define-pmacro (extract-hilo reg1 off1 reg2 off2 arg1hi arg1lo arg2hi arg2lo) + (sequence () + (set arg1hi (add (halfword hi reg1 off1) (mul reg1 0))) + (set arg1lo (add (halfword lo reg1 off1) (mul reg1 0))) + (set arg2hi (add (halfword hi reg2 off2) (mul reg2 0))) + (set arg2lo (add (halfword lo reg2 off2) (mul reg2 0)))) +) + +(dni maveh + "Media dual average" + ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2) (FR400-MAJOR M-1)) + "maveh$pack $FRinti,$FRintj,$FRintk" + (+ pack FRintk OP_7B FRinti OPE1_08 FRintj) + (set FRintk (c-call SI "@cpu@_media_average" FRinti FRintj)) + ((fr400 (unit u-media-1)) + (fr500 (unit u-media)) (fr550 (unit u-media))) +) + +(define-pmacro (media-dual-shift name operation op ope profile comment) + (dni name + (comment) + ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) (FR400-MAJOR M-1)) + (.str name "$pack $FRinti,$u6,$FRintk") + (+ pack FRintk op FRinti ope u6) + (sequence () + ; hack to get these referenced for profiling + (set FRinti (c-raw-call SI "frv_ref_SI" FRinti)) + (set FRintk (c-raw-call SI "frv_ref_SI" FRintk)) + (set (halfword hi FRintk 0) + (operation (halfword hi FRinti 0) (and u6 #xf))) + (set (halfword lo FRintk 0) + (operation (halfword lo FRinti 0) (and u6 #xf)))) + profile + ) +) + +(media-dual-shift msllhi sll OP_7B OPE1_09 + ((fr400 (unit u-media-3)) (fr500 (unit u-media)) (fr550 (unit u-media))) + "Media dual shift left logical") +(media-dual-shift msrlhi srl OP_7B OPE1_0A + ((fr400 (unit u-media-3)) (fr500 (unit u-media)) (fr550 (unit u-media))) + "Media dual shift right logical") +(media-dual-shift msrahi sra OP_7B OPE1_0B + ((fr400 (unit u-media-6)) (fr500 (unit u-media)) (fr550 (unit u-media))) + "Media dual shift right arithmetic") + +(define-pmacro (media-dual-word-rotate-r-r name operation op ope comment) + (dni name + (comment) + ((UNIT FMLOW) (MACH fr400,fr550) (FR550-MAJOR M-3) (FR400-MAJOR M-2)) + (.str name "$pack $FRintieven,$s6,$FRintkeven") + (+ pack FRintkeven op FRintieven ope s6) + (if (orif (register-unaligned FRintieven 2) + (register-unaligned FRintkeven 2)) + (c-call VOID "@cpu@_media_register_not_aligned") + (sequence () + (set FRintkeven (operation FRintieven (and s6 #x1f))) + (set (nextreg h-fr_int FRintkeven 1) + (operation (nextreg h-fr_int FRintieven 1) + (and s6 #x1f))))) + ((fr400 (unit u-media-3-quad + (in FRinti FRintieven) + (out FRintk FRintkeven))) (fr550 (unit u-media-quad))) + ) +) + +(media-dual-word-rotate-r-r mdrotli rol OP_78 OPE1_0B "rotate left reg/reg") + +(dni mcplhi + "Media bit concatenate, halfword" + ((UNIT FMLOW) (MACH fr400,fr550) (FR550-MAJOR M-3) (FR400-MAJOR M-2)) + "mcplhi$pack $FRinti,$u6,$FRintk" + (+ pack FRintk OP_78 FRinti OPE1_0C u6) + (sequence ((HI arg1) (HI arg2) (HI shift)) + (set FRinti (c-raw-call SI "frv_ref_SI" FRinti)) + (set FRintk (c-raw-call SI "frv_ref_SI" FRintk)) + (set shift (and u6 #xf)) + (set arg1 (sll (halfword hi FRinti 0) shift)) + (if (ne shift 0) + (sequence () + (set arg2 (halfword hi FRinti 1)) + (set arg2 (srl HI (sll HI arg2 (sub 15 shift)) + (sub 15 shift))) + (set arg1 (or HI arg1 arg2)))) + (set (halfword hi FRintk 0) arg1)) + ((fr400 (unit u-media-3-dual)) (fr550 (unit u-media-3-dual))) +) + +(dni mcpli + "Media bit concatenate, word" + ((UNIT FMLOW) (MACH fr400,fr550) (FR550-MAJOR M-3) (FR400-MAJOR M-2)) + "mcpli$pack $FRinti,$u6,$FRintk" + (+ pack FRintk OP_78 FRinti OPE1_0D u6) + (sequence ((SI tmp) (SI shift)) + (set shift (and u6 #x1f)) + (set tmp (sll FRinti shift)) + (if (ne shift 0) + (sequence ((SI tmp1)) + (set tmp1 (srl (sll (nextreg h-fr_int FRinti 1) + (sub 31 shift)) + (sub 31 shift))) + (set tmp (or tmp tmp1)))) + (set FRintk tmp)) + ((fr400 (unit u-media-3-dual)) (fr550 (unit u-media-3-dual))) +) + +(define-pmacro (saturate arg max min result) + (if (gt arg max) + (set result max) + (if (lt arg min) + (set result min) + (set result arg))) +) + +(dni msaths + "Media dual saturation signed" + ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2) (FR400-MAJOR M-1)) + "msaths$pack $FRinti,$FRintj,$FRintk" + (+ pack FRintk OP_7B FRinti OPE1_0C FRintj) + (sequence ((HI argihi) (HI argilo) (HI argjhi) (HI argjlo)) + (extract-hilo FRinti 0 FRintj 0 argihi argilo argjhi argjlo) + (saturate argihi argjhi (inv argjhi) (halfword hi FRintk 0)) + (saturate argilo argjlo (inv argjlo) (halfword lo FRintk 0))) + ((fr400 (unit u-media-1)) + (fr500 (unit u-media)) (fr550 (unit u-media))) +) + +(dni mqsaths + "Media quad saturation signed" + ((UNIT FMALL) (MACH fr400,fr550) (FR550-MAJOR M-2) (FR400-MAJOR M-1)) + "mqsaths$pack $FRintieven,$FRintjeven,$FRintkeven" + (+ pack FRintkeven OP_78 FRintieven OPE1_0F FRintjeven) + (if (orif (register-unaligned FRintieven 2) + (orif (register-unaligned FRintjeven 2) + (register-unaligned FRintkeven 2))) + (c-call VOID "@cpu@_media_register_not_aligned") + (sequence ((HI argihi) (HI argilo) (HI argjhi) (HI argjlo)) + ; hack to get FRintkeven referenced as a target for profiling + (set FRintkeven (c-raw-call SI "frv_ref_SI" FRintkeven)) + (extract-hilo FRintieven 0 FRintjeven 0 argihi argilo argjhi argjlo) + (saturate argihi argjhi (inv argjhi) (halfword hi FRintkeven 0)) + (saturate argilo argjlo (inv argjlo) (halfword lo FRintkeven 0)) + (extract-hilo FRintieven 1 FRintjeven 1 argihi argilo argjhi argjlo) + (saturate argihi argjhi (inv argjhi) (halfword hi FRintkeven 1)) + (saturate argilo argjlo (inv argjlo) (halfword lo FRintkeven 1)))) + ((fr400 (unit u-media-1-quad + (in FRinti FRintieven) + (in FRintj FRintjeven) + (out FRintk FRintkeven))) (fr550 (unit u-media-quad))) +) + +(define-pmacro (saturate-unsigned arg max result) + (if (gt arg max) + (set result max) + (set result arg)) +) + +(dni msathu + "Media dual saturation unsigned" + ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2) (FR400-MAJOR M-1)) + "msathu$pack $FRinti,$FRintj,$FRintk" + (+ pack FRintk OP_7B FRinti OPE1_0D FRintj) + (sequence ((UHI argihi) (UHI argilo) (UHI argjhi) (UHI argjlo)) + (extract-hilo FRinti 0 FRintj 0 argihi argilo argjhi argjlo) + (saturate-unsigned argihi argjhi (halfword hi FRintk 0)) + (saturate-unsigned argilo argjlo (halfword lo FRintk 0))) + ((fr400 (unit u-media-1)) + (fr500 (unit u-media)) (fr550 (unit u-media))) +) + +(define-pmacro (media-dual-compare name mode op ope comment) + (dni name + (comment) + ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2) (FR400-MAJOR M-1)) + (.str name "$pack $FRinti,$FRintj,$FCCk") + (+ pack (cond-null) FCCk op FRinti ope FRintj) + (if (register-unaligned FCCk 2) + (c-call VOID "@cpu@_media_cr_not_aligned") + (sequence ((mode argihi) (mode argilo) (mode argjhi) (mode argjlo)) + (extract-hilo FRinti 0 FRintj 0 + argihi argilo argjhi argjlo) + (compare-and-set-fcc argihi argjhi FCCk) + (compare-and-set-fcc argilo argjlo (nextreg h-fccr FCCk 1)))) + ; TODO - doesn't handle second FCC + ((fr400 (unit u-media-7)) + (fr500 (unit u-media)) (fr550 (unit u-media))) + ) +) + +(media-dual-compare mcmpsh HI OP_7B OPE1_0E "Media dual compare signed") +(media-dual-compare mcmpuh UHI OP_7B OPE1_0F "Media dual compare unsigned") + +; Bits for the MSR.SIE field +(define-pmacro (msr-sie-nil) 0) +(define-pmacro (msr-sie-fri-hi) 8) +(define-pmacro (msr-sie-fri-lo) 4) +(define-pmacro (msr-sie-fri-1-hi) 2) +(define-pmacro (msr-sie-fri-1-lo) 1) +(define-pmacro (msr-sie-acci) 8) +(define-pmacro (msr-sie-acci-1) 4) +(define-pmacro (msr-sie-acci-2) 2) +(define-pmacro (msr-sie-acci-3) 1) + +(define-pmacro (saturate-v arg max min sie result) + (if (gt DI arg max) + (sequence () + (set result max) + (c-call VOID "@cpu@_media_overflow" sie)) + (if (lt DI arg min) + (sequence () + (set result min) + (c-call VOID "@cpu@_media_overflow" sie)) + (set result arg))) +) + +(dni mabshs + "Media dual absolute value, halfword" + ((UNIT FMALL) (MACH fr400,fr550) (FR550-MAJOR M-2) (FR400-MAJOR M-1)) + "mabshs$pack $FRintj,$FRintk" + (+ pack FRintk OP_78 (FRi-null) OPE1_0A FRintj) + (sequence ((HI arghi) (HI arglo)) + (set FRintj (c-raw-call SI "frv_ref_SI" FRintj)) + (set FRintk (c-raw-call SI "frv_ref_SI" FRintk)) + (set arghi (halfword hi FRintj 0)) + (set arglo (halfword lo FRintj 0)) + (saturate-v (abs arghi) 32767 -32768 (msr-sie-fri-hi) + (halfword hi FRintk 0)) + (saturate-v (abs arglo) 32767 -32768 (msr-sie-fri-lo) + (halfword lo FRintk 0))) + ((fr400 (unit u-media-1)) (fr550 (unit u-media))) +) + +(define-pmacro (media-arith-sat-semantics + operation arg1 arg2 res mode max min sie) + (sequence ((DI tmp)) + (set tmp (operation arg1 arg2)) + (saturate-v tmp max min sie res)) +) + +(define-pmacro (media-dual-arith-sat-semantics operation mode max min) + (sequence ((mode argihi) (mode argilo) (mode argjhi) (mode argjlo)) + (extract-hilo FRinti 0 FRintj 0 argihi argilo argjhi argjlo) + (media-arith-sat-semantics operation argihi argjhi + (halfword hi FRintk 0) mode max min + (msr-sie-fri-hi)) + (media-arith-sat-semantics operation argilo argjlo + (halfword lo FRintk 0) mode max min + (msr-sie-fri-lo))) +) + +(define-pmacro (media-dual-arith-sat name operation mode max min op ope comment) + (dni name + (comment) + ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2) (FR400-MAJOR M-1)) + (.str name "$pack $FRinti,$FRintj,$FRintk") + (+ pack FRintk op FRinti ope FRintj) + (media-dual-arith-sat-semantics operation mode max min) + ((fr400 (unit u-media-1)) + (fr500 (unit u-media)) (fr550 (unit u-media))) + ) +) + +(media-dual-arith-sat maddhss add HI 32767 -32768 OP_7B OPE1_10 "Media dual add signed with saturation") +(media-dual-arith-sat maddhus add UHI 65535 0 OP_7B OPE1_11 "Media dual add unsigned with saturation") + +(media-dual-arith-sat msubhss sub HI 32767 -32768 OP_7B OPE1_12 "Media dual sub signed with saturation") +(media-dual-arith-sat msubhus sub UHI 65535 0 OP_7B OPE1_13 "Media dual sub unsigned with saturation") + +(define-pmacro (conditional-media-dual-arith-sat + name operation mode max min op ope comment) + (dni name + (comment) + ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2) (FR400-MAJOR M-1) CONDITIONAL) + (.str name "$pack $FRinti,$FRintj,$FRintk,$CCi,$cond") + (+ pack FRintk op FRinti CCi cond ope FRintj) + (if (eq CCi (or cond 2)) + (media-dual-arith-sat-semantics operation mode max min)) + ((fr400 (unit u-media-1)) + (fr500 (unit u-media)) (fr550 (unit u-media))) + ) +) + +(conditional-media-dual-arith-sat cmaddhss add HI 32767 -32768 OP_71 OPE4_0 "Conditional Media dual add signed with saturation") +(conditional-media-dual-arith-sat cmaddhus add UHI 65535 0 OP_71 OPE4_1 "Conditional Media dual add unsigned with saturation") + +(conditional-media-dual-arith-sat cmsubhss sub HI 32767 -32768 OP_71 OPE4_2 "Conditional Media dual sub signed with saturation") +(conditional-media-dual-arith-sat cmsubhus sub UHI 65535 0 OP_71 OPE4_3 "Conditional Media dual sub unsigned with saturation") + +(define-pmacro (media-quad-arith-sat-semantics cond operation mode max min) + (if (orif (register-unaligned FRintieven 2) + (orif (register-unaligned FRintjeven 2) + (register-unaligned FRintkeven 2))) + (c-call VOID "@cpu@_media_register_not_aligned") + (if cond + (sequence ((mode argihi) (mode argilo) (mode argjhi) (mode argjlo)) + ; hack to get FRintkeven referenced as a target for profiling + (set FRintkeven (c-raw-call SI "frv_ref_SI" FRintkeven)) + (extract-hilo FRintieven 0 FRintjeven 0 + argihi argilo argjhi argjlo) + (media-arith-sat-semantics operation argihi argjhi + (halfword hi FRintkeven 0) mode + max min (msr-sie-fri-hi)) + (media-arith-sat-semantics operation argilo argjlo + (halfword lo FRintkeven 0) mode + max min (msr-sie-fri-lo)) + (extract-hilo FRintieven 1 FRintjeven 1 + argihi argilo argjhi argjlo) + (media-arith-sat-semantics operation argihi argjhi + (halfword hi FRintkeven 1) mode + max min (msr-sie-fri-1-hi)) + (media-arith-sat-semantics operation argilo argjlo + (halfword lo FRintkeven 1) mode + max min (msr-sie-fri-1-lo))))) +) + +(define-pmacro (media-quad-arith-sat name operation mode max min op ope comment) + (dni name + (comment) + ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2) (FR400-MAJOR M-2)) + (.str name "$pack $FRintieven,$FRintjeven,$FRintkeven") + (+ pack FRintkeven op FRintieven ope FRintjeven) + (media-quad-arith-sat-semantics 1 operation mode max min) + ((fr400 (unit u-media-1-quad + (in FRinti FRintieven) + (in FRintj FRintjeven) + (out FRintk FRintkeven))) + (fr500 (unit u-media-quad-arith + (in FRinti FRintieven) + (in FRintj FRintjeven) + (out FRintk FRintkeven))) (fr550 (unit u-media-quad))) + ) +) + +(media-quad-arith-sat mqaddhss add HI 32767 -32768 OP_7B OPE1_18 "Media quad add signed with saturation") +(media-quad-arith-sat mqaddhus add UHI 65535 0 OP_7B OPE1_19 "Media quad add unsigned with saturation") + +(media-quad-arith-sat mqsubhss sub HI 32767 -32768 OP_7B OPE1_1A "Media quad sub signed with saturation") +(media-quad-arith-sat mqsubhus sub UHI 65535 0 OP_7B OPE1_1B "Media quad sub unsigned with saturation") + +(define-pmacro (conditional-media-quad-arith-sat + name operation mode max min op ope comment) + (dni name + (comment) + ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2) (FR400-MAJOR M-2) CONDITIONAL) + (.str name "$pack $FRintieven,$FRintjeven,$FRintkeven,$CCi,$cond") + (+ pack FRintkeven op FRintieven CCi cond ope FRintjeven) + (media-quad-arith-sat-semantics (eq CCi (or cond 2)) + operation mode max min) + ((fr400 (unit u-media-1-quad + (in FRinti FRintieven) + (in FRintj FRintjeven) + (out FRintk FRintkeven))) + (fr500 (unit u-media-quad-arith + (in FRinti FRintieven) + (in FRintj FRintjeven) + (out FRintk FRintkeven))) (fr550 (unit u-media-quad))) + ) +) + +(conditional-media-quad-arith-sat cmqaddhss add HI 32767 -32768 OP_73 OPE4_0 "Conditional Media quad add signed with saturation") +(conditional-media-quad-arith-sat cmqaddhus add UHI 65535 0 OP_73 OPE4_1 "Conditional Media quad add unsigned with saturation") + +(conditional-media-quad-arith-sat cmqsubhss sub HI 32767 -32768 OP_73 OPE4_2 "Conditional Media quad sub signed with saturation") +(conditional-media-quad-arith-sat cmqsubhus sub UHI 65535 0 OP_73 OPE4_3 "Conditional Media quad sub unsigned with saturation") + +(define-pmacro (media-acc-arith-sat name operation mode max min op ope comment) + (dni name + (comment) + ((UNIT FMALL) (MACH fr400,fr550) (FR550-MAJOR M-4) (FR400-MAJOR M-1)) + (.str name "$pack $ACC40Si,$ACC40Sk") + (+ pack ACC40Sk op ACC40Si ope (ACCj-null)) + (if (c-call SI "@cpu@_check_acc_range" (index-of ACC40Si)) + (if (c-call SI "@cpu@_check_acc_range" (index-of ACC40Sk)) + (if (register-unaligned ACC40Si 2) + (c-call VOID "@cpu@_media_acc_not_aligned") + (media-arith-sat-semantics operation ACC40Si + (nextreg h-acc40S ACC40Si 1) + ACC40Sk mode max min (msr-sie-acci))))) + ((fr400 (unit u-media-2-acc)) (fr550 (unit u-media-4-acc))) + ) +) + +(media-acc-arith-sat maddaccs add DI #x7fffffffff (inv DI #x7fffffffff) + OP_78 OPE1_04 "Media accumulator addition") +(media-acc-arith-sat msubaccs sub DI #x7fffffffff (inv DI #x7fffffffff) + OP_78 OPE1_05 "Media accumulator subtraction") + +(define-pmacro (media-dual-acc-arith-sat name operation mode max min op ope + comment) + (dni name + (comment) + ((UNIT MDUALACC) (MACH fr400,fr550) (FR550-MAJOR M-4) (FR400-MAJOR M-2)) + (.str name "$pack $ACC40Si,$ACC40Sk") + (+ pack ACC40Sk op ACC40Si ope (ACCj-null)) + (if (c-call SI "@cpu@_check_acc_range" (index-of ACC40Si)) + (if (c-call SI "@cpu@_check_acc_range" (index-of ACC40Sk)) + (if (register-unaligned ACC40Si 4) + (c-call VOID "@cpu@_media_acc_not_aligned") + (if (register-unaligned ACC40Sk 2) + (c-call VOID "@cpu@_media_acc_not_aligned") + (sequence () + (media-arith-sat-semantics operation ACC40Si + (nextreg h-acc40S ACC40Si 1) + ACC40Sk mode max min + (msr-sie-acci)) + (media-arith-sat-semantics operation + (nextreg h-acc40S ACC40Si 2) + (nextreg h-acc40S ACC40Si 3) + (nextreg h-acc40S ACC40Sk 1) + mode max min + (msr-sie-acci-1))))))) + ((fr400 (unit u-media-2-acc-dual)) (fr550 (unit u-media-4-acc-dual))) + ) +) + +(media-dual-acc-arith-sat mdaddaccs add DI #x7fffffffff (inv DI #x7fffffffff) + OP_78 OPE1_06 "Media accumulator addition") +(media-dual-acc-arith-sat mdsubaccs sub DI #x7fffffffff (inv DI #x7fffffffff) + OP_78 OPE1_07 "Media accumulator subtraction") + +(dni masaccs + "Media add and subtract signed accumulator with saturation" + ((UNIT FMALL) (MACH fr400,fr550) (FR550-MAJOR M-4) (FR400-MAJOR M-1)) + "masaccs$pack $ACC40Si,$ACC40Sk" + (+ pack ACC40Sk OP_78 ACC40Si OPE1_08 (ACCj-null)) + (if (c-call SI "@cpu@_check_acc_range" (index-of ACC40Si)) + (if (c-call SI "@cpu@_check_acc_range" (index-of ACC40Sk)) + (if (register-unaligned ACC40Si 2) + (c-call VOID "@cpu@_media_acc_not_aligned") + (if (register-unaligned ACC40Sk 2) + (c-call VOID "@cpu@_media_acc_not_aligned") + (sequence () + (media-arith-sat-semantics add ACC40Si + (nextreg h-acc40S ACC40Si 1) + ACC40Sk DI + #x7fffffffff + (inv DI #x7fffffffff) + (msr-sie-acci)) + (media-arith-sat-semantics sub ACC40Si + (nextreg h-acc40S ACC40Si 1) + (nextreg h-acc40S ACC40Sk 1) + DI + #x7fffffffff + (inv DI #x7fffffffff) + (msr-sie-acci-1))))))) + ((fr400 (unit u-media-2-add-sub)) (fr550 (unit u-media-4-add-sub))) + ) + +(dni mdasaccs + "Media add and subtract signed accumulator with saturation" + ((UNIT MDUALACC) (MACH fr400,fr550) (FR550-MAJOR M-4) (FR400-MAJOR M-2)) + "mdasaccs$pack $ACC40Si,$ACC40Sk" + (+ pack ACC40Sk OP_78 ACC40Si OPE1_09 (ACCj-null)) + (if (c-call SI "@cpu@_check_acc_range" (index-of ACC40Si)) + (if (c-call SI "@cpu@_check_acc_range" (index-of ACC40Sk)) + (if (register-unaligned ACC40Si 4) + (c-call VOID "@cpu@_media_acc_not_aligned") + (if (register-unaligned ACC40Sk 4) + (c-call VOID "@cpu@_media_acc_not_aligned") + (sequence () + (media-arith-sat-semantics add ACC40Si + (nextreg h-acc40S ACC40Si 1) + ACC40Sk DI + #x7fffffffff + (inv DI #x7fffffffff) + (msr-sie-acci)) + (media-arith-sat-semantics sub ACC40Si + (nextreg h-acc40S ACC40Si 1) + (nextreg h-acc40S ACC40Sk 1) + DI + #x7fffffffff + (inv DI #x7fffffffff) + (msr-sie-acci-1)) + (media-arith-sat-semantics add + (nextreg h-acc40S ACC40Si 2) + (nextreg h-acc40S ACC40Si 3) + (nextreg h-acc40S ACC40Sk 2) + DI + #x7fffffffff + (inv DI #x7fffffffff) + (msr-sie-acci-2)) + (media-arith-sat-semantics sub + (nextreg h-acc40S ACC40Si 2) + (nextreg h-acc40S ACC40Si 3) + (nextreg h-acc40S ACC40Sk 3) + DI + #x7fffffffff + (inv DI #x7fffffffff) + (msr-sie-acci-3))))))) + ((fr400 (unit u-media-2-add-sub-dual)) (fr550 (unit u-media-4-add-sub-dual))) + ) + +(define-pmacro (media-multiply-semantics conv arg1 arg2 res) + (set res (mul DI (conv DI arg1) (conv DI arg2))) +) + +(define-pmacro (media-dual-multiply-semantics cond mode conv rhs1 rhs2) + (if (c-call SI "@cpu@_check_acc_range" (index-of ACC40Sk)) + (if (register-unaligned ACC40Sk 2) + (c-call VOID "@cpu@_media_acc_not_aligned") + (if cond + (sequence ((mode argihi) (mode argilo) (mode argjhi) (mode argjlo)) + (extract-hilo FRinti 0 FRintj 0 + argihi argilo argjhi argjlo) + (media-multiply-semantics conv argihi rhs1 ACC40Sk) + (media-multiply-semantics conv argilo rhs2 + (nextreg h-acc40S ACC40Sk 1)))))) +) + +(define-pmacro (media-dual-multiply name mode conv rhs1 rhs2 op ope comment) + (dni name + (comment) + ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) (FR400-MAJOR M-1) PRESERVE-OVF) + (.str name "$pack $FRinti,$FRintj,$ACC40Sk") + (+ pack ACC40Sk op FRinti ope FRintj) + (media-dual-multiply-semantics 1 mode conv rhs1 rhs2) + ((fr400 (unit u-media-2)) + (fr500 (unit u-media-dual-mul)) (fr550 (unit u-media-4))) + ) +) + +(media-dual-multiply mmulhs HI ext argjhi argjlo OP_7B OPE1_14 "Media dual multiply signed") +(media-dual-multiply mmulhu UHI zext argjhi argjlo OP_7B OPE1_15 "Media dual multiply unsigned") + +(media-dual-multiply mmulxhs HI ext argjlo argjhi OP_7B OPE1_28 "Media dual cross multiply signed") +(media-dual-multiply mmulxhu UHI zext argjlo argjhi OP_7B OPE1_29 "Media dual cross multiply unsigned") + +(define-pmacro (conditional-media-dual-multiply + name mode conv rhs1 rhs2 op ope comment) + (dni name + (comment) + ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) (FR400-MAJOR M-1) + PRESERVE-OVF CONDITIONAL) + (.str name "$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond") + (+ pack ACC40Sk op FRinti CCi cond ope FRintj) + (media-dual-multiply-semantics (eq CCi (or cond 2)) mode conv rhs1 rhs2) + ((fr400 (unit u-media-2)) + (fr500 (unit u-media-dual-mul)) (fr550 (unit u-media-4))) + ) +) + +(conditional-media-dual-multiply cmmulhs HI ext argjhi argjlo OP_72 OPE4_0 "Conditional Media dual multiply signed") +(conditional-media-dual-multiply cmmulhu UHI zext argjhi argjlo OP_72 OPE4_1 "Conditional Media dual multiply unsigned") + +(define-pmacro (media-quad-multiply-semantics cond mode conv rhs1 rhs2) + (if (c-call SI "@cpu@_check_acc_range" (index-of ACC40Sk)) + (if (register-unaligned ACC40Sk 4) + (c-call VOID "@cpu@_media_acc_not_aligned") + (if (orif (register-unaligned FRintieven 2) + (register-unaligned FRintjeven 2)) + (c-call VOID "@cpu@_media_register_not_aligned") + (if cond + (sequence ((mode argihi) (mode argilo) + (mode argjhi) (mode argjlo)) + (extract-hilo FRintieven 0 FRintjeven 0 + argihi argilo argjhi argjlo) + (media-multiply-semantics conv argihi rhs1 ACC40Sk) + (media-multiply-semantics conv argilo rhs2 + (nextreg h-acc40S ACC40Sk 1)) + (extract-hilo FRintieven 1 FRintjeven 1 + argihi argilo argjhi argjlo) + (media-multiply-semantics conv argihi rhs1 + (nextreg h-acc40S ACC40Sk 2)) + (media-multiply-semantics conv argilo rhs2 + (nextreg h-acc40S ACC40Sk 3))))))) +) + +(define-pmacro (media-quad-multiply name mode conv rhs1 rhs2 op ope comment) + (dni name + (comment) + ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) (FR400-MAJOR M-2) PRESERVE-OVF) + (.str name "$pack $FRintieven,$FRintjeven,$ACC40Sk") + (+ pack ACC40Sk op FRintieven ope FRintjeven) + (media-quad-multiply-semantics 1 mode conv rhs1 rhs2) + ((fr400 (unit u-media-2-quad + (in FRinti FRintieven) + (in FRintj FRintjeven))) + (fr500 (unit u-media-quad-mul + (in FRinti FRintieven) + (in FRintj FRintjeven))) (fr550 (unit u-media-4-quad))) + ) +) + +(media-quad-multiply mqmulhs HI ext argjhi argjlo OP_7B OPE1_1C "Media quad multiply signed") +(media-quad-multiply mqmulhu UHI zext argjhi argjlo OP_7B OPE1_1D "Media quad multiply unsigned") + +(media-quad-multiply mqmulxhs HI ext argjlo argjhi OP_7B OPE1_2A "Media quad cross multiply signed") +(media-quad-multiply mqmulxhu UHI zext argjlo argjhi OP_7B OPE1_2B "Media quad cross multiply unsigned") + +(define-pmacro (conditional-media-quad-multiply + name mode conv rhs1 rhs2 op ope comment) + (dni name + (comment) + ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) (FR400-MAJOR M-2) + PRESERVE-OVF CONDITIONAL) + (.str name "$pack $FRintieven,$FRintjeven,$ACC40Sk,$CCi,$cond") + (+ pack ACC40Sk op FRintieven CCi cond ope FRintjeven) + (media-quad-multiply-semantics (eq CCi (or cond 2)) mode conv rhs1 rhs2) + ((fr400 (unit u-media-2-quad + (in FRinti FRintieven) + (in FRintj FRintjeven))) + (fr500 (unit u-media-quad-mul + (in FRinti FRintieven) + (in FRintj FRintjeven))) (fr550 (unit u-media-4-quad))) + ) +) + +(conditional-media-quad-multiply cmqmulhs HI ext argjhi argjlo OP_74 OPE4_0 "Conditional Media quad multiply signed") +(conditional-media-quad-multiply cmqmulhu UHI zext argjhi argjlo OP_74 OPE4_1 "Conditional Media quad multiply unsigned") + +(define-pmacro (media-multiply-acc-semantics + conv arg1 addop arg2 res max min sie) + (sequence ((DI tmp)) + (set tmp (addop res (mul DI (conv DI arg1) (conv DI arg2)))) + (saturate-v tmp max min sie res)) +) + +(define-pmacro (media-dual-multiply-acc-semantics + cond mode conv addop rhw res max min) + (if (c-call SI "@cpu@_check_acc_range" (index-of res)) + (if (register-unaligned res 2) + (c-call VOID "@cpu@_media_acc_not_aligned") + (if cond + (sequence ((mode argihi) (mode argilo) (mode argjhi) (mode argjlo)) + (extract-hilo FRinti 0 FRintj 0 + argihi argilo argjhi argjlo) + (media-multiply-acc-semantics conv argihi addop argjhi + res + max min (msr-sie-acci)) + (media-multiply-acc-semantics conv argilo addop argjlo + (nextreg rhw res 1) + max min (msr-sie-acci-1)))))) +) + +(define-pmacro (media-dual-multiply-acc + name mode conv addop rhw res max min op ope comment) + (dni name + (comment) + ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) (FR400-MAJOR M-1)) + (.str name "$pack $FRinti,$FRintj,$" res) + (+ pack res op FRinti ope FRintj) + (media-dual-multiply-acc-semantics 1 mode conv addop rhw res max min) + ((fr400 (unit u-media-2)) + (fr500 (unit u-media-dual-mul)) (fr550 (unit u-media-4))) + ) +) + +(media-dual-multiply-acc mmachs HI ext add h-acc40S ACC40Sk + (const DI #x7fffffffff) (const DI #xffffff8000000000) + OP_7B OPE1_16 + "Media dual multiply and accumulate signed") + +(media-dual-multiply-acc mmachu UHI zext add h-acc40U ACC40Uk + (const DI #xffffffffff) (const DI 0) + OP_7B OPE1_17 + "Media dual multiply and accumulate unsigned") + +(media-dual-multiply-acc mmrdhs HI ext sub h-acc40S ACC40Sk + (const DI #x7fffffffff) (const DI #xffffff8000000000) + OP_7B OPE1_30 + "Media dual multiply and reduce signed") + +(media-dual-multiply-acc mmrdhu UHI zext sub h-acc40U ACC40Uk + (const DI #xffffffffff) (const DI 0) + OP_7B OPE1_31 + "Media dual multiply and reduce unsigned") + +(define-pmacro (conditional-media-dual-multiply-acc + name mode conv addop rhw res max min op ope comment) + (dni name + (comment) + ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) (FR400-MAJOR M-1) CONDITIONAL) + (.str name "$pack $FRinti,$FRintj,$" res ",$CCi,$cond") + (+ pack res op FRinti CCi cond ope FRintj) + (media-dual-multiply-acc-semantics (eq CCi (or cond 2)) + mode conv addop rhw res max min) + ((fr400 (unit u-media-2)) + (fr500 (unit u-media-dual-mul)) (fr550 (unit u-media-4))) + ) +) + +(conditional-media-dual-multiply-acc cmmachs HI ext add h-acc40S ACC40Sk + (const DI #x7fffffffff) (const DI #xffffff8000000000) + OP_72 OPE4_2 + "Conditional Media dual multiply and accumulate signed") + +(conditional-media-dual-multiply-acc cmmachu UHI zext add h-acc40U ACC40Uk + (const DI #xffffffffff) (const DI 0) + OP_72 OPE4_3 + "Conditional Media dual multiply and accumulate unsigned") + +(define-pmacro (media-quad-multiply-acc-semantics + cond mode conv addop rhw res max min) + (if (c-call SI "@cpu@_check_acc_range" (index-of res)) + (if (register-unaligned res 4) + (c-call VOID "@cpu@_media_acc_not_aligned") + (if (orif (register-unaligned FRintieven 2) + (register-unaligned FRintjeven 2)) + (c-call VOID "@cpu@_media_register_not_aligned") + (if cond + (sequence ((mode argihi) (mode argilo) + (mode argjhi) (mode argjlo)) + (extract-hilo FRintieven 0 FRintjeven 0 + argihi argilo argjhi argjlo) + (media-multiply-acc-semantics conv argihi addop argjhi + res + max min (msr-sie-acci)) + (media-multiply-acc-semantics conv argilo addop argjlo + (nextreg rhw res 1) + max min (msr-sie-acci-1)) + (extract-hilo FRintieven 1 FRintjeven 1 + argihi argilo argjhi argjlo) + (media-multiply-acc-semantics conv argihi addop argjhi + (nextreg rhw res 2) + max min (msr-sie-acci-2)) + (media-multiply-acc-semantics conv argilo addop argjlo + (nextreg rhw res 3) + max min + (msr-sie-acci-3))))))) +) + +(define-pmacro (media-quad-multiply-acc + name mode conv addop rhw res max min op ope comment) + (dni name + (comment) + ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) (FR400-MAJOR M-2)) + (.str name "$pack $FRintieven,$FRintjeven,$" res) + (+ pack res op FRintieven ope FRintjeven) + (media-quad-multiply-acc-semantics 1 mode conv addop rhw res max min) + ((fr400 (unit u-media-2-quad + (in FRinti FRintieven) + (in FRintj FRintjeven))) + (fr500 (unit u-media-quad-mul + (in FRinti FRintieven) + (in FRintj FRintjeven))) (fr550 (unit u-media-4-quad))) + ) +) + +(media-quad-multiply-acc mqmachs HI ext add h-acc40S ACC40Sk + (const DI #x7fffffffff) (const DI #xffffff8000000000) + OP_7B OPE1_1E + "Media quad multiply and accumulate signed") + +(media-quad-multiply-acc mqmachu UHI zext add h-acc40U ACC40Uk + (const DI #xffffffffff) (const DI 0) + OP_7B OPE1_1F + "Media quad multiply and accumulate unsigned") + +(define-pmacro (conditional-media-quad-multiply-acc + name mode conv addop rhw res max min op ope comment) + (dni name + (comment) + ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) (FR400-MAJOR M-2) CONDITIONAL) + (.str name "$pack $FRintieven,$FRintjeven,$" res ",$CCi,$cond") + (+ pack res op FRintieven CCi cond ope FRintjeven) + (media-quad-multiply-acc-semantics (eq CCi (or cond 2)) + mode conv addop rhw res max min) + ((fr400 (unit u-media-2-quad + (in FRinti FRintieven) + (in FRintj FRintjeven))) + (fr500 (unit u-media-quad-mul + (in FRinti FRintieven) + (in FRintj FRintjeven))) (fr550 (unit u-media-4-quad))) + ) +) + +(conditional-media-quad-multiply-acc cmqmachs HI ext add h-acc40S ACC40Sk + (const DI #x7fffffffff) (const DI #xffffff8000000000) + OP_74 OPE4_2 + "Conditional Media quad multiply and accumulate signed") + +(conditional-media-quad-multiply-acc cmqmachu UHI zext add h-acc40U ACC40Uk + (const DI #xffffffffff) (const DI 0) + OP_74 OPE4_3 + "Conditional media quad multiply and accumulate unsigned") + +(define-pmacro (media-quad-multiply-cross-acc-semantics + cond mode conv addop rhw res max min) + (if (c-call SI "@cpu@_check_acc_range" (index-of res)) + (if (register-unaligned res 4) + (c-call VOID "@cpu@_media_acc_not_aligned") + (if (orif (register-unaligned FRintieven 2) + (register-unaligned FRintjeven 2)) + (c-call VOID "@cpu@_media_register_not_aligned") + (if cond + (sequence ((mode argihi) (mode argilo) + (mode argjhi) (mode argjlo)) + (extract-hilo FRintieven 0 FRintjeven 0 + argihi argilo argjhi argjlo) + (media-multiply-acc-semantics conv argihi addop argjhi + (nextreg rhw res 2) + max min (msr-sie-acci-2)) + (media-multiply-acc-semantics conv argilo addop argjlo + (nextreg rhw res 3) + max min (msr-sie-acci-3)) + (extract-hilo FRintieven 1 FRintjeven 1 + argihi argilo argjhi argjlo) + (media-multiply-acc-semantics conv argihi addop argjhi + res + max min (msr-sie-acci)) + (media-multiply-acc-semantics conv argilo addop argjlo + (nextreg rhw res 1) + max min + (msr-sie-acci-1))))))) +) + +(define-pmacro (media-quad-multiply-cross-acc + name mode conv addop rhw res max min op ope comment) + (dni name + (comment) + ((UNIT MDUALACC) (MACH fr400,fr550) (FR550-MAJOR M-4) (FR400-MAJOR M-2)) + (.str name "$pack $FRintieven,$FRintjeven,$" res) + (+ pack res op FRintieven ope FRintjeven) + (media-quad-multiply-cross-acc-semantics 1 mode conv addop rhw res + max min) + ((fr400 (unit u-media-2-quad + (in FRinti FRintieven) + (in FRintj FRintjeven))) (fr550 (unit u-media-4-quad))) + ) +) + +(media-quad-multiply-cross-acc mqxmachs HI ext add h-acc40S ACC40Sk + (const DI #x7fffffffff) (const DI #xffffff8000000000) + OP_78 OPE1_00 + "Media quad multiply and cross accumulate signed") + +(define-pmacro (media-quad-cross-multiply-cross-acc-semantics + cond mode conv addop rhw res max min) + (if (c-call SI "@cpu@_check_acc_range" (index-of res)) + (if (register-unaligned res 4) + (c-call VOID "@cpu@_media_acc_not_aligned") + (if (orif (register-unaligned FRintieven 2) + (register-unaligned FRintjeven 2)) + (c-call VOID "@cpu@_media_register_not_aligned") + (if cond + (sequence ((mode argihi) (mode argilo) + (mode argjhi) (mode argjlo)) + (extract-hilo FRintieven 0 FRintjeven 0 + argihi argilo argjhi argjlo) + (media-multiply-acc-semantics conv argihi addop argjlo + (nextreg rhw res 2) + max min (msr-sie-acci-2)) + (media-multiply-acc-semantics conv argilo addop argjhi + (nextreg rhw res 3) + max min (msr-sie-acci-3)) + (extract-hilo FRintieven 1 FRintjeven 1 + argihi argilo argjhi argjlo) + (media-multiply-acc-semantics conv argihi addop argjlo + res + max min (msr-sie-acci)) + (media-multiply-acc-semantics conv argilo addop argjhi + (nextreg rhw res 1) + max min + (msr-sie-acci-1))))))) +) + +(define-pmacro (media-quad-cross-multiply-cross-acc + name mode conv addop rhw res max min op ope comment) + (dni name + (comment) + ((UNIT MDUALACC) (MACH fr400,fr550) (FR550-MAJOR M-4) (FR400-MAJOR M-2)) + (.str name "$pack $FRintieven,$FRintjeven,$" res) + (+ pack res op FRintieven ope FRintjeven) + (media-quad-cross-multiply-cross-acc-semantics 1 mode conv addop rhw res + max min) + ((fr400 (unit u-media-2-quad + (in FRinti FRintieven) + (in FRintj FRintjeven))) (fr550 (unit u-media-4-quad))) + ) +) + +(media-quad-cross-multiply-cross-acc mqxmacxhs HI ext add h-acc40S ACC40Sk + (const DI #x7fffffffff) (const DI #xffffff8000000000) + OP_78 OPE1_01 + "Media quad cross multiply and cross accumulate signed") + +(define-pmacro (media-quad-cross-multiply-acc-semantics + cond mode conv addop rhw res max min) + (if (c-call SI "@cpu@_check_acc_range" (index-of res)) + (if (register-unaligned res 4) + (c-call VOID "@cpu@_media_acc_not_aligned") + (if (orif (register-unaligned FRintieven 2) + (register-unaligned FRintjeven 2)) + (c-call VOID "@cpu@_media_register_not_aligned") + (if cond + (sequence ((mode argihi) (mode argilo) + (mode argjhi) (mode argjlo)) + (extract-hilo FRintieven 0 FRintjeven 0 + argihi argilo argjhi argjlo) + (media-multiply-acc-semantics conv argihi addop argjlo + res + max min (msr-sie-acci)) + (media-multiply-acc-semantics conv argilo addop argjhi + (nextreg rhw res 1) + max min (msr-sie-acci-1)) + (extract-hilo FRintieven 1 FRintjeven 1 + argihi argilo argjhi argjlo) + (media-multiply-acc-semantics conv argihi addop argjlo + (nextreg rhw res 2) + max min (msr-sie-acci-2)) + (media-multiply-acc-semantics conv argilo addop argjhi + (nextreg rhw res 3) + max min + (msr-sie-acci-3))))))) +) + +(define-pmacro (media-quad-cross-multiply-acc + name mode conv addop rhw res max min op ope comment) + (dni name + (comment) + ((UNIT MDUALACC) (MACH fr400,fr550) (FR550-MAJOR M-4) (FR400-MAJOR M-2)) + (.str name "$pack $FRintieven,$FRintjeven,$" res) + (+ pack res op FRintieven ope FRintjeven) + (media-quad-cross-multiply-acc-semantics 1 mode conv addop rhw res + max min) + ((fr400 (unit u-media-2-quad + (in FRinti FRintieven) + (in FRintj FRintjeven))) (fr550 (unit u-media-4-quad))) + ) +) + +(media-quad-cross-multiply-acc mqmacxhs HI ext add h-acc40S ACC40Sk + (const DI #x7fffffffff) (const DI #xffffff8000000000) + OP_78 OPE1_02 + "Media quad cross multiply and accumulate signed") + +(define-pmacro (media-complex-semantics + conv lhs1 rhs1 lhs2 rhs2 res max min sie) + (sequence ((DI tmp1) (DI tmp2)) + (media-multiply-semantics conv lhs1 rhs1 tmp1) + (media-multiply-semantics conv lhs2 rhs2 tmp2) + (set tmp1 (sub tmp1 tmp2)) + (saturate-v tmp1 max min sie res)) +) + +(define-pmacro (media-complex-semantics-i + conv lhs1 rhs1 lhs2 rhs2 res max min sie) + (sequence ((DI tmp1) (DI tmp2)) + (media-multiply-semantics conv lhs1 rhs1 tmp1) + (media-multiply-semantics conv lhs2 rhs2 tmp2) + (set tmp1 (add tmp1 tmp2)) + (saturate-v tmp1 max min sie res)) +) + +(define-pmacro (media-dual-complex-semantics mode conv rhs1 rhs2 max min) + (if (c-call SI "@cpu@_check_acc_range" (index-of ACC40Sk)) + (sequence ((mode argihi) (mode argilo) (mode argjhi) (mode argjlo)) + (extract-hilo FRinti 0 FRintj 0 argihi argilo argjhi argjlo) + (media-complex-semantics conv argihi rhs1 argilo rhs2 ACC40Sk + max min (msr-sie-acci)))) +) + +(define-pmacro (media-dual-complex-semantics-i mode conv rhs1 rhs2 max min) + (if (c-call SI "@cpu@_check_acc_range" (index-of ACC40Sk)) + (sequence ((mode argihi) (mode argilo) (mode argjhi) (mode argjlo)) + (extract-hilo FRinti 0 FRintj 0 argihi argilo argjhi argjlo) + (media-complex-semantics-i conv argihi rhs1 argilo rhs2 ACC40Sk + max min (msr-sie-acci)))) +) + +(define-pmacro (media-dual-complex + name mode conv rhs1 rhs2 max min op ope comment) + (dni name + (comment) + ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) (FR400-MAJOR M-1)) + (.str name "$pack $FRinti,$FRintj,$ACC40Sk") + (+ pack ACC40Sk op FRinti ope FRintj) + (media-dual-complex-semantics mode conv rhs1 rhs2 max min) + ((fr400 (unit u-media-2)) + (fr500 (unit u-media-dual-mul)) (fr550 (unit u-media-4))) + ) +) + +(define-pmacro (media-dual-complex-i + name mode conv rhs1 rhs2 max min op ope comment) + (dni name + (comment) + ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) (FR400-MAJOR M-1)) + (.str name "$pack $FRinti,$FRintj,$ACC40Sk") + (+ pack ACC40Sk op FRinti ope FRintj) + (media-dual-complex-semantics-i mode conv rhs1 rhs2 max min) + ((fr400 (unit u-media-2)) + (fr500 (unit u-media-dual-mul)) (fr550 (unit u-media-4))) + ) +) + +(media-dual-complex mcpxrs HI ext argjhi argjlo + (const DI #x7fffffffff) (const DI #xffffff8000000000) + OP_7B OPE1_20 + "Media dual complex real signed with saturation") + +(media-dual-complex mcpxru UHI zext argjhi argjlo + (const DI #xffffffffff) (const DI 0) + OP_7B OPE1_21 + "Media dual complex real unsigned with saturation") + +(media-dual-complex-i mcpxis HI ext argjlo argjhi + (const DI #x7fffffffff) (const DI #xffffff8000000000) + OP_7B OPE1_22 + "Media dual complex imaginary signed with saturation") + +(media-dual-complex-i mcpxiu UHI zext argjlo argjhi + (const DI #xffffffffff) (const DI 0) + OP_7B OPE1_23 + "Media dual complex imaginary unsigned with saturation") + +(define-pmacro (conditional-media-dual-complex + name mode conv rhs1 rhs2 max min op ope comment) + (dni name + (comment) + ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) (FR400-MAJOR M-1) CONDITIONAL) + (.str name "$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond") + (+ pack ACC40Sk op FRinti CCi cond ope FRintj) + (if (eq CCi (or cond 2)) + (media-dual-complex-semantics mode conv rhs1 rhs2 max min)) + ((fr400 (unit u-media-2)) + (fr500 (unit u-media-dual-mul)) (fr550 (unit u-media-4))) + ) +) + +(define-pmacro (conditional-media-dual-complex-i + name mode conv rhs1 rhs2 max min op ope comment) + (dni name + (comment) + ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) (FR400-MAJOR M-1) CONDITIONAL) + (.str name "$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond") + (+ pack ACC40Sk op FRinti CCi cond ope FRintj) + (if (eq CCi (or cond 2)) + (media-dual-complex-semantics-i mode conv rhs1 rhs2 max min)) + ((fr400 (unit u-media-2)) + (fr500 (unit u-media-dual-mul)) (fr550 (unit u-media-4))) + ) +) + +(conditional-media-dual-complex cmcpxrs HI ext argjhi argjlo + (const DI #x7fffffffff) (const DI #xffffff8000000000) + OP_75 OPE4_0 + "Conditional Media dual complex real signed with saturation") + +(conditional-media-dual-complex cmcpxru UHI zext argjhi argjlo + (const DI #xffffffffff) (const DI 0) + OP_75 OPE4_1 + "Conditional Media dual complex real unsigned with saturation") + +(conditional-media-dual-complex-i cmcpxis HI ext argjlo argjhi + (const DI #x7fffffffff) (const DI #xffffff8000000000) + OP_75 OPE4_2 + "Conditional Media dual complex imaginary signed with saturation") + +(conditional-media-dual-complex-i cmcpxiu UHI zext argjlo argjhi + (const DI #xffffffffff) (const DI 0) + OP_75 OPE4_3 + "Conditional Media dual complex imaginary unsigned with saturation") + +(define-pmacro (media-quad-complex + name mode conv rhs1 rhs2 max min op ope comment) + (dni name + (comment) + ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) (FR400-MAJOR M-2)) + (.str name "$pack $FRintieven,$FRintjeven,$ACC40Sk") + (+ pack ACC40Sk op FRintieven ope FRintjeven) + (if (c-call SI "@cpu@_check_acc_range" (index-of ACC40Sk)) + (if (register-unaligned ACC40Sk 2) + (c-call VOID "@cpu@_media_acc_not_aligned") + (if (orif (register-unaligned FRintieven 2) + (register-unaligned FRintjeven 2)) + (c-call VOID "@cpu@_media_register_not_aligned") + (sequence ((mode argihi) (mode argilo) + (mode argjhi) (mode argjlo)) + (extract-hilo FRintieven 0 FRintjeven 0 + argihi argilo argjhi argjlo) + (media-complex-semantics conv argihi rhs1 argilo rhs2 + ACC40Sk + max min (msr-sie-acci)) + (extract-hilo FRintieven 1 FRintjeven 1 + argihi argilo argjhi argjlo) + (media-complex-semantics conv argihi rhs1 argilo rhs2 + (nextreg h-acc40S ACC40Sk 1) + max min (msr-sie-acci-1)))))) + ((fr400 (unit u-media-2-quad + (in FRinti FRintieven) + (in FRintj FRintjeven))) + (fr500 (unit u-media-quad-complex + (in FRinti FRintieven) + (in FRintj FRintjeven))) (fr550 (unit u-media-4-quad))) + ) +) + +(define-pmacro (media-quad-complex-i + name mode conv rhs1 rhs2 max min op ope comment) + (dni name + (comment) + ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) (FR400-MAJOR M-2)) + (.str name "$pack $FRintieven,$FRintjeven,$ACC40Sk") + (+ pack ACC40Sk op FRintieven ope FRintjeven) + (if (c-call SI "@cpu@_check_acc_range" (index-of ACC40Sk)) + (if (register-unaligned ACC40Sk 2) + (c-call VOID "@cpu@_media_acc_not_aligned") + (if (orif (register-unaligned FRintieven 2) + (register-unaligned FRintjeven 2)) + (c-call VOID "@cpu@_media_register_not_aligned") + (sequence ((mode argihi) (mode argilo) + (mode argjhi) (mode argjlo)) + (extract-hilo FRintieven 0 FRintjeven 0 + argihi argilo argjhi argjlo) + (media-complex-semantics-i conv argihi rhs1 argilo rhs2 + ACC40Sk + max min (msr-sie-acci)) + (extract-hilo FRintieven 1 FRintjeven 1 + argihi argilo argjhi argjlo) + (media-complex-semantics-i conv argihi rhs1 argilo rhs2 + (nextreg h-acc40S ACC40Sk 1) + max min (msr-sie-acci-1)))))) + ((fr400 (unit u-media-2-quad + (in FRinti FRintieven) + (in FRintj FRintjeven))) + (fr500 (unit u-media-quad-complex + (in FRinti FRintieven) + (in FRintj FRintjeven))) (fr550 (unit u-media-4-quad))) + ) +) + +(media-quad-complex mqcpxrs HI ext argjhi argjlo + (const DI #x7fffffffff) (const DI #xffffff8000000000) + OP_7B OPE1_24 + "Media quad complex real signed with saturation") + +(media-quad-complex mqcpxru UHI zext argjhi argjlo + (const DI #xffffffffff) (const DI 0) + OP_7B OPE1_25 + "Media quad complex real unsigned with saturation") + +(media-quad-complex-i mqcpxis HI ext argjlo argjhi + (const DI #x7fffffffff) (const DI #xffffff8000000000) + OP_7B OPE1_26 + "Media quad complex imaginary signed with saturation") + +(media-quad-complex-i mqcpxiu UHI zext argjlo argjhi + (const DI #xffffffffff) (const DI 0) + OP_7B OPE1_27 + "Media quad complex imaginary unsigned with saturation") + +(define-pmacro (media-pack src1 src2 targ offset) + (sequence () + (set (halfword hi targ offset) (halfword lo src1 offset)) + (set (halfword lo targ offset) (halfword lo src2 offset))) +) + +(define-pmacro (media-expand-halfword-to-word-semantics cond) + (if cond + (sequence ((UHI tmp)) + (if (and u6 1) + (set tmp (halfword lo FRinti 0)) + (set tmp (halfword hi FRinti 0))) + (set (halfword hi FRintk 0) tmp) + (set (halfword lo FRintk 0) tmp))) +) + +(dni mexpdhw + "Media expand halfword to word" + ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) (FR400-MAJOR M-1)) + "mexpdhw$pack $FRinti,$u6,$FRintk" + (+ pack FRintk OP_7B FRinti OPE1_32 u6) + (media-expand-halfword-to-word-semantics 1) + ((fr400 (unit u-media-3)) + (fr500 (unit u-media)) (fr550 (unit u-media))) +) + +(dni cmexpdhw + "Conditional media expand halfword to word" + ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) (FR400-MAJOR M-1) CONDITIONAL) + "cmexpdhw$pack $FRinti,$u6,$FRintk,$CCi,$cond" + (+ pack FRintk OP_76 FRinti CCi cond OPE4_2 u6) + (media-expand-halfword-to-word-semantics (eq CCi (or cond 2))) + ((fr400 (unit u-media-3)) + (fr500 (unit u-media)) (fr550 (unit u-media))) +) + +(define-pmacro (media-expand-halfword-to-double-semantics cond) + (if (register-unaligned FRintkeven 2) + (c-call VOID "@cpu@_media_register_not_aligned") + (if cond + (sequence ((UHI tmp)) + ; a hack to get FRintkeven referenced for profiling + (set FRintkeven (c-raw-call SI "frv_ref_SI" FRintkeven)) + (if (and u6 1) + (set tmp (halfword lo FRinti 0)) + (set tmp (halfword hi FRinti 0))) + (set (halfword hi FRintkeven 0) tmp) + (set (halfword lo FRintkeven 0) tmp) + (set (halfword hi FRintkeven 1) tmp) + (set (halfword lo FRintkeven 1) tmp)))) +) + +(dni mexpdhd + "Media expand halfword to double" + ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) (FR400-MAJOR M-2)) + "mexpdhd$pack $FRinti,$u6,$FRintkeven" + (+ pack FRintkeven OP_7B FRinti OPE1_33 u6) + (media-expand-halfword-to-double-semantics 1) + ((fr400 (unit u-media-dual-expand + (out FRintk FRintkeven))) + (fr500 (unit u-media-dual-expand + (out FRintk FRintkeven))) (fr550 (unit u-media-dual-expand))) +) + +(dni cmexpdhd + "Conditional media expand halfword to double" + ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) (FR400-MAJOR M-2) CONDITIONAL) + "cmexpdhd$pack $FRinti,$u6,$FRintkeven,$CCi,$cond" + (+ pack FRintkeven OP_76 FRinti CCi cond OPE4_3 u6) + (media-expand-halfword-to-double-semantics (eq CCi (or cond 2))) + ((fr400 (unit u-media-dual-expand + (out FRintk FRintkeven))) + (fr500 (unit u-media-dual-expand + (out FRintk FRintkeven))) (fr550 (unit u-media-dual-expand))) +) + +(dni mpackh + "Media halfword pack" + ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) (FR400-MAJOR M-1)) + "mpackh$pack $FRinti,$FRintj,$FRintk" + (+ pack FRintk OP_7B FRinti OPE1_34 FRintj) + (media-pack FRinti FRintj FRintk 0) + ((fr400 (unit u-media-3)) + (fr500 (unit u-media)) (fr550 (unit u-media))) +) + +(dni mdpackh + "Media dual pack" + ((UNIT FM01) (FR500-MAJOR M-5) (FR550-MAJOR M-3) (FR400-MAJOR M-2)) + "mdpackh$pack $FRintieven,$FRintjeven,$FRintkeven" + (+ pack FRintkeven OP_7B FRintieven OPE1_36 FRintjeven) + (if (orif (register-unaligned FRintieven 2) + (orif (register-unaligned FRintjeven 2) + (register-unaligned FRintkeven 2))) + (c-call VOID "@cpu@_media_register_not_aligned") + (sequence () + ; hack to get these referenced for profiling + (set FRintieven (c-raw-call SI "frv_ref_SI" FRintieven)) + (set FRintjeven (c-raw-call SI "frv_ref_SI" FRintjeven)) + (set FRintkeven (c-raw-call SI "frv_ref_SI" FRintkeven)) + (media-pack FRintieven FRintjeven FRintkeven 0) + (media-pack FRintieven FRintjeven FRintkeven 1))) + ((fr400 (unit u-media-3-quad + (in FRinti FRintieven) + (in FRintj FRintjeven) + (out FRintk FRintkeven))) + (fr500 (unit u-media-quad-arith + (in FRinti FRintieven) + (in FRintj FRintjeven) + (out FRintk FRintkeven))) (fr550 (unit u-media-quad))) +) + +(define-pmacro (media-unpack src soff targ toff) + (sequence () + (set (halfword hi targ toff) (halfword hi src soff)) + (set (halfword lo targ toff) (halfword hi src soff)) + (set (halfword hi targ (add toff 1)) (halfword lo src soff)) + (set (halfword lo targ (add toff 1)) (halfword lo src soff))) +) + +(dni munpackh + "Media halfword unpack" + ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) (FR400-MAJOR M-2)) + "munpackh$pack $FRinti,$FRintkeven" + (+ pack FRintkeven OP_7B FRinti OPE1_35 (FRj-null)) + (if (register-unaligned FRintkeven 2) + (c-call VOID "@cpu@_media_register_not_aligned") + (sequence () + ; hack to get these referenced for profiling + (set FRinti (c-raw-call SI "frv_ref_SI" FRinti)) + (set FRintkeven (c-raw-call SI "frv_ref_SI" FRintkeven)) + (media-unpack FRinti 0 FRintkeven 0))) + ((fr400 (unit u-media-dual-expand + (out FRintk FRintkeven))) + (fr500 (unit u-media-dual-expand + (out FRintk FRintkeven))) (fr550 (unit u-media-dual-expand))) +) + +(dni mdunpackh + "Media dual unpack" + ((UNIT FM01) (FR500-MAJOR M-7) (MACH simple,tomcat,frv)) + "mdunpackh$pack $FRintieven,$FRintk" + (+ pack FRintk OP_7B FRintieven OPE1_37 (FRj-null)) + (if (orif (register-unaligned FRintieven 2) (register-unaligned FRintk 4)) + (c-call VOID "@cpu@_media_register_not_aligned") + (sequence () + ; hack to get these referenced for profiling + (set FRintieven (c-raw-call SI "frv_ref_SI" FRintieven)) + (set FRintk (c-raw-call SI "frv_ref_SI" FRintk)) + (media-unpack FRintieven 0 FRintk 0) + (media-unpack FRintieven 1 FRintk 2))) + ((fr500 (unit u-media-dual-unpack + (in FRinti FRintieven)))) +) + +(define-pmacro (ubyte num arg offset) + (reg (.sym h-fr_ num) (add (index-of arg) offset))) + +(define-pmacro (mbtoh-semantics cond) + (if (register-unaligned FRintkeven 2) + (c-call VOID "@cpu@_media_register_not_aligned") + (if cond + (sequence () + (set (halfword hi FRintkeven 0) (ubyte 3 FRintj 0)) + (set (halfword lo FRintkeven 0) (ubyte 2 FRintj 0)) + (set (halfword hi FRintkeven 1) (ubyte 1 FRintj 0)) + (set (halfword lo FRintkeven 1) (ubyte 0 FRintj 0))))) +) + +(dni mbtoh + "Media convert byte to halfword" + ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) (FR400-MAJOR M-2)) + "mbtoh$pack $FRintj,$FRintkeven" + (+ pack FRintkeven OP_7B (FRi-null) OPE1_38 FRintj) + (sequence () + ; hack to get these referenced for profiling + (set FRintj (c-raw-call SI "frv_ref_SI" FRintj)) + (set FRintkeven (c-raw-call SI "frv_ref_SI" FRintkeven)) + (mbtoh-semantics 1)) + ((fr400 (unit u-media-dual-expand + (out FRintk FRintkeven))) + (fr500 (unit u-media-dual-btoh + (out FRintk FRintkeven))) (fr550 (unit u-media-dual-expand))) +) + +(dni cmbtoh + "Conditional media convert byte to halfword" + ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) (FR400-MAJOR M-2) CONDITIONAL) + "cmbtoh$pack $FRintj,$FRintkeven,$CCi,$cond" + (+ pack FRintkeven OP_77 (FRi-null) CCi cond OPE4_0 FRintj) + (sequence () + ; hack to get these referenced for profiling + (set FRintj (c-raw-call SI "frv_ref_SI" FRintj)) + (set FRintkeven (c-raw-call SI "frv_ref_SI" FRintkeven)) + (mbtoh-semantics (eq CCi (or cond 2)))) + ((fr400 (unit u-media-dual-expand + (out FRintk FRintkeven))) + (fr500 (unit u-media-dual-btoh + (out FRintk FRintkeven))) (fr550 (unit u-media-dual-expand (in FRinti FRintj)))) +) + +(define-pmacro (mhtob-semantics cond) + (if (register-unaligned FRintjeven 2) + (c-call VOID "@cpu@_media_register_not_aligned") + (if cond + (sequence () + (set (ubyte 3 FRintk 0) (halfword hi FRintjeven 0)) + (set (ubyte 2 FRintk 0) (halfword lo FRintjeven 0)) + (set (ubyte 1 FRintk 0) (halfword hi FRintjeven 1)) + (set (ubyte 0 FRintk 0) (halfword lo FRintjeven 1))))) +) + +(dni mhtob + "Media convert halfword to byte" + ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) (FR400-MAJOR M-2)) + "mhtob$pack $FRintjeven,$FRintk" + (+ pack FRintk OP_7B (FRi-null) OPE1_39 FRintjeven) + (sequence () + ; hack to get these referenced for profiling + (set FRintjeven (c-raw-call SI "frv_ref_SI" FRintjeven)) + (set FRintk (c-raw-call SI "frv_ref_SI" FRintk)) + (mhtob-semantics 1)) + ((fr400 (unit u-media-dual-htob + (in FRintj FRintjeven))) + (fr500 (unit u-media-dual-htob + (in FRintj FRintjeven))) (fr550 (unit u-media-3-dual (in FRinti FRintjeven)))) +) + +(dni cmhtob + "Conditional media convert halfword to byte" + ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) (FR400-MAJOR M-2) CONDITIONAL) + "cmhtob$pack $FRintjeven,$FRintk,$CCi,$cond" + (+ pack FRintk OP_77 (FRi-null) CCi cond OPE4_1 FRintjeven) + (sequence () + ; hack to get these referenced for profiling + (set FRintjeven (c-raw-call SI "frv_ref_SI" FRintjeven)) + (set FRintk (c-raw-call SI "frv_ref_SI" FRintk)) + (mhtob-semantics (eq CCi (or cond 2)))) + ((fr400 (unit u-media-dual-htob + (in FRintj FRintjeven))) + (fr500 (unit u-media-dual-htob + (in FRintj FRintjeven))) (fr550 (unit u-media-3-dual (in FRinti FRintjeven)))) +) + +(define-pmacro (mbtohe-semantics cond) + (if (register-unaligned FRintk 4) + (c-call VOID "@cpu@_media_register_not_aligned") + (if cond + (sequence () + (set (halfword hi FRintk 0) (ubyte 3 FRintj 0)) + (set (halfword lo FRintk 0) (ubyte 3 FRintj 0)) + (set (halfword hi FRintk 1) (ubyte 2 FRintj 0)) + (set (halfword lo FRintk 1) (ubyte 2 FRintj 0)) + (set (halfword hi FRintk 2) (ubyte 1 FRintj 0)) + (set (halfword lo FRintk 2) (ubyte 1 FRintj 0)) + (set (halfword hi FRintk 3) (ubyte 0 FRintj 0)) + (set (halfword lo FRintk 3) (ubyte 0 FRintj 0))))) +) + +(dni mbtohe + "Media convert byte to halfword extended" + ((UNIT FM01) (FR500-MAJOR M-7) (MACH simple,tomcat,frv)) + "mbtohe$pack $FRintj,$FRintk" + (+ pack FRintk OP_7B (FRi-null) OPE1_3A FRintj) + (sequence () + ; hack to get these referenced for profiling + (set FRintj (c-raw-call SI "frv_ref_SI" FRintj)) + (set FRintk (c-raw-call SI "frv_ref_SI" FRintk)) + (mbtohe-semantics 1)) + ((fr500 (unit u-media-dual-btohe))) +) + +(dni cmbtohe + "Conditional media convert byte to halfword extended" + ((UNIT FM01) (FR500-MAJOR M-7) CONDITIONAL (MACH simple,tomcat,frv)) + "cmbtohe$pack $FRintj,$FRintk,$CCi,$cond" + (+ pack FRintk OP_77 (FRi-null) CCi cond OPE4_2 FRintj) + (sequence () + ; hack to get these referenced for profiling + (set FRintj (c-raw-call SI "frv_ref_SI" FRintj)) + (set FRintk (c-raw-call SI "frv_ref_SI" FRintk)) + (mbtohe-semantics (eq CCi (or cond 2)))) + ((fr500 (unit u-media-dual-btohe))) +) + +; Media NOP +; A special case of mclracc +(dni mnop "Media nop" + ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-1) (FR400-MAJOR M-1)) + "mnop$pack" + (+ pack (f-ACC40Sk 63) OP_7B (f-A 1) (misc-null-10) OPE1_3B (FRj-null)) + (nop) + () +) + +; mclracc with #A==0 +(dni mclracc-0 + "Media clear accumulator(s)" + ((UNIT FM01) (FR500-MAJOR M-3) (FR550-MAJOR M-3) (FR400-MAJOR M-1)) + "mclracc$pack $ACC40Sk,$A0" + (+ pack ACC40Sk OP_7B (f-A 0) (misc-null-10) OPE1_3B (FRj-null)) + (c-call VOID "@cpu@_clear_accumulators" (index-of ACC40Sk) 0) + ((fr400 (unit u-media-4)) + (fr500 (unit u-media)) (fr550 (unit u-media-3-mclracc))) +) + +; mclracc with #A==1 +(dni mclracc-1 + "Media clear accumulator(s)" + ((UNIT MCLRACC-1) (FR500-MAJOR M-6) (FR550-MAJOR M-3) (FR400-MAJOR M-2)) + "mclracc$pack $ACC40Sk,$A1" + (+ pack ACC40Sk OP_7B (f-A 1) (misc-null-10) OPE1_3B (FRj-null)) + (c-call VOID "@cpu@_clear_accumulators" (index-of ACC40Sk) 1) + ((fr400 (unit u-media-4)) + (fr500 (unit u-media)) (fr550 (unit u-media-3-mclracc))) +) + +(dni mrdacc + "Media read accumulator" + ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) (FR400-MAJOR M-1)) + "mrdacc$pack $ACC40Si,$FRintk" + (+ pack FRintk OP_7B ACC40Si OPE1_3C (FRj-null)) + (set FRintk ACC40Si) + ((fr400 (unit u-media-4)) + (fr500 (unit u-media)) (fr550 (unit u-media-3-acc))) +) + +(dni mrdaccg + "Media read accumulator guard" + ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) (FR400-MAJOR M-1)) + "mrdaccg$pack $ACCGi,$FRintk" + (+ pack FRintk OP_7B ACCGi OPE1_3E (FRj-null)) + (set FRintk ACCGi) + ((fr400 (unit u-media-4-accg)) + (fr500 (unit u-media)) (fr550 (unit u-media-3-acc (in ACC40Si ACCGi)))) +) + +(dni mwtacc + "Media write accumulator" + ((UNIT FM01) (FR500-MAJOR M-3) (FR550-MAJOR M-3) (FR400-MAJOR M-1)) + "mwtacc$pack $FRinti,$ACC40Sk" + (+ pack ACC40Sk OP_7B FRinti OPE1_3D (FRj-null)) + (set ACC40Sk (or (and ACC40Sk (const DI #xffffffff00000000)) + FRinti)) + ((fr400 (unit u-media-4)) + (fr500 (unit u-media)) (fr550 (unit u-media-3-wtacc))) +) + +(dni mwtaccg + "Media write accumulator guard" + ((UNIT FM01) (FR500-MAJOR M-3) (FR550-MAJOR M-3) (FR400-MAJOR M-1)) + "mwtaccg$pack $FRinti,$ACCGk" + (+ pack ACCGk OP_7B FRinti OPE1_3F (FRj-null)) + (sequence () + ; hack to get these referenced for profiling + (c-raw-call VOID "frv_ref_SI" ACCGk) + (set ACCGk FRinti)) + ((fr400 (unit u-media-4-accg)) + (fr500 (unit u-media)) (fr550 (unit u-media-3-wtacc (in ACC40Sk ACCGk)))) +) + +(define-pmacro (media-cop num op) + (dni (.sym mcop num) + "Media custom instruction" + ((UNIT FM01) (FR500-MAJOR M-1) (MACH frv)) + (.str "mcop" num "$pack $FRi,$FRj,$FRk") + (+ pack FRk op FRi OPE1_00 FRj) + (c-call VOID "@cpu@_media_cop" num) + () + ) +) + +(media-cop 1 OP_7C) +(media-cop 2 OP_7D) + +; nop +; A nop is defined to be a "ori gr0,0,gr0" +; This needn't be a macro-insn, but making it one greatly simplifies decode.c +; On the other hand spending a little time in the decoder is often worth it. +; +(dnmi nop "nop" + ((UNIT IALL) (FR500-MAJOR I-1) (FR400-MAJOR I-1)) + "nop$pack" + (emit ori pack (GRi 0) (s12 0) (GRk 0)) +) + +; Floating point NOP +(dni fnop + "Floating point nop" + ((UNIT FMALL) (FR500-MAJOR F-8) (FR550-MAJOR F-1) (MACH simple,tomcat,fr500,fr550,frv)) + "fnop$pack" + (+ pack (rd-null) OP_79 (FRi-null) OPE1_0D (FRj-null)) + (nop) + () +) + +; A return instruction +(dnmi ret "return" + (NO-DIS (UNIT B01) (FR500-MAJOR B-3) (FR400-MAJOR B-3)) + "ret$pack" + (emit bralr pack (hint_taken 2)) +) + +(dnmi cmp "compare" + (NO-DIS (UNIT IALL) (FR500-MAJOR I-1) (FR400-MAJOR I-1)) + "cmp$pack $GRi,$GRj,$ICCi_1" + (emit subcc pack GRi GRj (GRk 0) ICCi_1) +) + +(dnmi cmpi "compare immediate" + (NO-DIS (UNIT IALL) (FR500-MAJOR I-1) (FR400-MAJOR I-1)) + "cmpi$pack $GRi,$s10,$ICCi_1" + (emit subicc pack GRi s10 (GRk 0) ICCi_1) +) + +(dnmi ccmp "conditional compare" + (NO-DIS (UNIT IALL) (FR500-MAJOR I-1) (FR400-MAJOR I-1) CONDITIONAL) + "ccmp$pack $GRi,$GRj,$CCi,$cond" + (emit csubcc pack GRi GRj (GRk 0) CCi cond) +) + +(dnmi mov "move" + (NO-DIS (UNIT IALL) (FR500-MAJOR I-1) (FR400-MAJOR I-1)) + "mov$pack $GRi,$GRk" + (emit ori pack GRi (s12 0) GRk) +) + +(dnmi cmov "conditional move" + (NO-DIS (UNIT IALL) (FR500-MAJOR I-1) (FR400-MAJOR I-1) CONDITIONAL) + "cmov$pack $GRi,$GRk,$CCi,$cond" + (emit cor pack GRi (GRj 0) GRk CCi cond) +) diff --git a/cpu/frv.opc b/cpu/frv.opc new file mode 100644 index 0000000..e149508 --- /dev/null +++ b/cpu/frv.opc @@ -0,0 +1,1267 @@ +/* Fujitsu FRV opcode support, for GNU Binutils. -*- C -*- + + Copyright 2000, 2001, 2003 Free Software Foundation, Inc. + + Contributed by Red Hat Inc; developed under contract from Fujitsu. + + This file is part of the GNU Binutils. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +*/ + +/* This file is an addendum to frv.cpu. Heavy use of C code isn't + appropriate in .cpu files, so it resides here. This especially applies + to assembly/disassembly where parsing/printing can be quite involved. + Such things aren't really part of the specification of the cpu, per se, + so .cpu files provide the general framework and .opc files handle the + nitty-gritty details as necessary. + + Each section is delimited with start and end markers. + + -opc.h additions use: "-- opc.h" + -opc.c additions use: "-- opc.c" + -asm.c additions use: "-- asm.c" + -dis.c additions use: "-- dis.c" + -ibd.h additions use: "-- ibd.h" +*/ + +/* -- opc.h */ + +#undef CGEN_DIS_HASH_SIZE +#define CGEN_DIS_HASH_SIZE 128 +#undef CGEN_DIS_HASH +#define CGEN_DIS_HASH(buffer, value) (((value) >> 18) & 127) + +/* Allows reason codes to be output when assembler errors occur. */ +#define CGEN_VERBOSE_ASSEMBLER_ERRORS + +/* Vliw support. */ +#define FRV_VLIW_SIZE 8 /* fr550 has largest vliw size of 8. */ +#define PAD_VLIW_COMBO ,UNIT_NIL,UNIT_NIL,UNIT_NIL,UNIT_NIL +typedef CGEN_ATTR_VALUE_TYPE VLIW_COMBO[FRV_VLIW_SIZE]; + +typedef struct +{ + int next_slot; + int constraint_violation; + unsigned long mach; + unsigned long elf_flags; + CGEN_ATTR_VALUE_TYPE *unit_mapping; + VLIW_COMBO *current_vliw; + CGEN_ATTR_VALUE_TYPE major[FRV_VLIW_SIZE]; + const CGEN_INSN* insn[FRV_VLIW_SIZE]; +} FRV_VLIW; + +int frv_is_branch_major PARAMS ((CGEN_ATTR_VALUE_TYPE, unsigned long)); +int frv_is_float_major PARAMS ((CGEN_ATTR_VALUE_TYPE, unsigned long)); +int frv_is_media_major PARAMS ((CGEN_ATTR_VALUE_TYPE, unsigned long)); +int frv_is_branch_insn PARAMS ((const CGEN_INSN *)); +int frv_is_float_insn PARAMS ((const CGEN_INSN *)); +int frv_is_media_insn PARAMS ((const CGEN_INSN *)); +void frv_vliw_reset PARAMS ((FRV_VLIW *, unsigned long mach, unsigned long elf_flags)); +int frv_vliw_add_insn PARAMS ((FRV_VLIW *, const CGEN_INSN *)); +int spr_valid PARAMS ((long)); +/* -- */ + +/* -- opc.c */ +#include "elf/frv.h" +#include + +static int match_unit + PARAMS ((FRV_VLIW *, CGEN_ATTR_VALUE_TYPE, CGEN_ATTR_VALUE_TYPE)); +static int match_vliw + PARAMS ((VLIW_COMBO *, VLIW_COMBO *, int)); +static VLIW_COMBO * add_next_to_vliw + PARAMS ((FRV_VLIW *, CGEN_ATTR_VALUE_TYPE)); +static int find_major_in_vliw + PARAMS ((FRV_VLIW *, CGEN_ATTR_VALUE_TYPE)); +static int fr400_check_insn_major_constraints + PARAMS ((FRV_VLIW *, CGEN_ATTR_VALUE_TYPE)); +static int fr500_check_insn_major_constraints + PARAMS ((FRV_VLIW *, CGEN_ATTR_VALUE_TYPE)); +static int fr550_check_insn_major_constraints + PARAMS ((FRV_VLIW *, CGEN_ATTR_VALUE_TYPE, const CGEN_INSN *)); +static int check_insn_major_constraints + PARAMS ((FRV_VLIW *, CGEN_ATTR_VALUE_TYPE, const CGEN_INSN *)); + +int +frv_is_branch_major (CGEN_ATTR_VALUE_TYPE major, unsigned long mach) +{ + switch (mach) + { + case bfd_mach_fr400: + if (major >= FR400_MAJOR_B_1 && major <= FR400_MAJOR_B_6) + return 1; /* is a branch */ + break; + default: + if (major >= FR500_MAJOR_B_1 && major <= FR500_MAJOR_B_6) + return 1; /* is a branch */ + break; + } + + return 0; /* not a branch */ +} + +int +frv_is_float_major (CGEN_ATTR_VALUE_TYPE major, unsigned long mach) +{ + switch (mach) + { + case bfd_mach_fr400: + return 0; /* No float insns */ + default: + if (major >= FR500_MAJOR_F_1 && major <= FR500_MAJOR_F_8) + return 1; /* is a float insn */ + break; + } + + return 0; /* not a branch */ +} + +int +frv_is_media_major (CGEN_ATTR_VALUE_TYPE major, unsigned long mach) +{ + switch (mach) + { + case bfd_mach_fr400: + if (major >= FR400_MAJOR_M_1 && major <= FR400_MAJOR_M_2) + return 1; /* is a media insn */ + break; + default: + if (major >= FR500_MAJOR_M_1 && major <= FR500_MAJOR_M_8) + return 1; /* is a media insn */ + break; + } + + return 0; /* not a branch */ +} + +int +frv_is_branch_insn (const CGEN_INSN *insn) +{ + if (frv_is_branch_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR400_MAJOR), + bfd_mach_fr400)) + return 1; + if (frv_is_branch_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR500_MAJOR), + bfd_mach_fr500)) + return 1; + + return 0; +} + +int +frv_is_float_insn (const CGEN_INSN *insn) +{ + if (frv_is_float_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR400_MAJOR), + bfd_mach_fr400)) + return 1; + if (frv_is_float_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR500_MAJOR), + bfd_mach_fr500)) + return 1; + + return 0; +} + +int +frv_is_media_insn (const CGEN_INSN *insn) +{ + if (frv_is_media_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR400_MAJOR), + bfd_mach_fr400)) + return 1; + if (frv_is_media_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR500_MAJOR), + bfd_mach_fr500)) + return 1; + + return 0; +} + +/* This table represents the allowable packing for vliw insns for the fr400. + The fr400 has only 2 vliw slots. Represent this by not allowing any insns + in the extra slots. + Subsets of any given row are also allowed. */ +static VLIW_COMBO fr400_allowed_vliw[] = +{ + /* slot0 slot1 slot2 slot3 */ + { UNIT_I0, UNIT_I1, UNIT_NIL, UNIT_NIL PAD_VLIW_COMBO }, + { UNIT_I0, UNIT_FM0, UNIT_NIL, UNIT_NIL PAD_VLIW_COMBO }, + { UNIT_I0, UNIT_B0, UNIT_NIL, UNIT_NIL PAD_VLIW_COMBO }, + { UNIT_FM0, UNIT_FM1, UNIT_NIL, UNIT_NIL PAD_VLIW_COMBO }, + { UNIT_FM0, UNIT_B0, UNIT_NIL, UNIT_NIL PAD_VLIW_COMBO }, + { UNIT_B0, UNIT_NIL, UNIT_NIL, UNIT_NIL PAD_VLIW_COMBO }, + { UNIT_C, UNIT_NIL, UNIT_NIL, UNIT_NIL PAD_VLIW_COMBO }, + { UNIT_NIL, UNIT_NIL, UNIT_NIL, UNIT_NIL PAD_VLIW_COMBO } +}; + +/* This table represents the allowable packing for vliw insns for the fr500. + The fr500 has only 4 vliw slots. Represent this by not allowing any insns + in the extra slots. + Subsets of any given row are also allowed. */ +static VLIW_COMBO fr500_allowed_vliw[] = +{ + /* slot0 slot1 slot2 slot3 */ + { UNIT_I0, UNIT_FM0, UNIT_I1, UNIT_FM1 PAD_VLIW_COMBO }, + { UNIT_I0, UNIT_FM0, UNIT_I1, UNIT_B0 PAD_VLIW_COMBO }, + { UNIT_I0, UNIT_FM0, UNIT_FM1, UNIT_B0 PAD_VLIW_COMBO }, + { UNIT_I0, UNIT_FM0, UNIT_B0, UNIT_B1 PAD_VLIW_COMBO }, + { UNIT_I0, UNIT_I1, UNIT_B0, UNIT_B1 PAD_VLIW_COMBO }, + { UNIT_I0, UNIT_B0, UNIT_B1, UNIT_NIL PAD_VLIW_COMBO }, + { UNIT_FM0, UNIT_FM1, UNIT_B0, UNIT_B1 PAD_VLIW_COMBO }, + { UNIT_FM0, UNIT_B0, UNIT_B1, UNIT_NIL PAD_VLIW_COMBO }, + { UNIT_B0, UNIT_B1, UNIT_NIL, UNIT_NIL PAD_VLIW_COMBO }, + { UNIT_C, UNIT_NIL, UNIT_NIL, UNIT_NIL PAD_VLIW_COMBO }, + { UNIT_NIL, UNIT_NIL, UNIT_NIL, UNIT_NIL PAD_VLIW_COMBO } +}; + +/* This table represents the allowable packing for vliw insns for the fr550. + Subsets of any given row are also allowed. */ +static VLIW_COMBO fr550_allowed_vliw[] = +{ + /* slot0 slot1 slot2 slot3 slot4 slot5 slot6 slot7 */ + { UNIT_I0, UNIT_I1, UNIT_I2, UNIT_I3, UNIT_B0, UNIT_B1 , UNIT_NIL, UNIT_NIL }, + { UNIT_I0, UNIT_I1, UNIT_I2, UNIT_B0, UNIT_B1 , UNIT_NIL, UNIT_NIL, UNIT_NIL }, + { UNIT_I0, UNIT_I1, UNIT_B0, UNIT_B1 , UNIT_NIL, UNIT_NIL, UNIT_NIL, UNIT_NIL }, + { UNIT_I0, UNIT_B0, UNIT_B1 , UNIT_NIL, UNIT_NIL, UNIT_NIL, UNIT_NIL, UNIT_NIL }, + { UNIT_I0, UNIT_FM0, UNIT_I1, UNIT_FM1, UNIT_I2, UNIT_FM2, UNIT_I3, UNIT_FM3 }, + { UNIT_I0, UNIT_FM0, UNIT_I1, UNIT_FM1, UNIT_I2, UNIT_FM2, UNIT_I3, UNIT_B0 }, + { UNIT_I0, UNIT_FM0, UNIT_I1, UNIT_FM1, UNIT_I2, UNIT_FM2, UNIT_FM3, UNIT_B0 }, + { UNIT_I0, UNIT_FM0, UNIT_I1, UNIT_FM1, UNIT_I2, UNIT_FM2, UNIT_B0, UNIT_B1 }, + { UNIT_I0, UNIT_FM0, UNIT_I1, UNIT_FM1, UNIT_I2, UNIT_I3, UNIT_B0, UNIT_B1 }, + { UNIT_I0, UNIT_FM0, UNIT_I1, UNIT_FM1, UNIT_I2, UNIT_B0, UNIT_B1, UNIT_NIL }, + { UNIT_I0, UNIT_FM0, UNIT_I1, UNIT_FM1, UNIT_FM2, UNIT_FM3, UNIT_B0, UNIT_B1 }, + { UNIT_I0, UNIT_FM0, UNIT_I1, UNIT_FM1, UNIT_FM2, UNIT_FM3, UNIT_B0, UNIT_B1 }, + { UNIT_I0, UNIT_FM0, UNIT_I1, UNIT_FM1, UNIT_FM2, UNIT_B0, UNIT_B1, UNIT_NIL }, + { UNIT_I0, UNIT_FM0, UNIT_I1, UNIT_FM1, UNIT_B0, UNIT_B1, UNIT_NIL, UNIT_NIL }, + { UNIT_I0, UNIT_FM0, UNIT_I1, UNIT_I2, UNIT_I3, UNIT_B0, UNIT_B1, UNIT_NIL }, + { UNIT_I0, UNIT_FM0, UNIT_I1, UNIT_I2, UNIT_B0, UNIT_B1, UNIT_NIL, UNIT_NIL }, + { UNIT_I0, UNIT_FM0, UNIT_I1, UNIT_B0, UNIT_B1, UNIT_NIL, UNIT_NIL, UNIT_NIL }, + { UNIT_I0, UNIT_FM0, UNIT_FM1, UNIT_FM2, UNIT_FM3, UNIT_B0, UNIT_B1, UNIT_NIL }, + { UNIT_I0, UNIT_FM0, UNIT_FM1, UNIT_FM2, UNIT_B0, UNIT_B1, UNIT_NIL, UNIT_NIL }, + { UNIT_I0, UNIT_FM0, UNIT_FM1, UNIT_B0, UNIT_B1, UNIT_NIL, UNIT_NIL, UNIT_NIL }, + { UNIT_I0, UNIT_FM0, UNIT_B0, UNIT_B1, UNIT_NIL, UNIT_NIL, UNIT_NIL, UNIT_NIL }, + { UNIT_B0, UNIT_B1, UNIT_NIL, UNIT_NIL, UNIT_NIL, UNIT_NIL, UNIT_NIL, UNIT_NIL }, + { UNIT_C, UNIT_NIL, UNIT_NIL, UNIT_NIL, UNIT_NIL, UNIT_NIL, UNIT_NIL, UNIT_NIL }, + { UNIT_FM0, UNIT_FM1, UNIT_FM2, UNIT_FM3, UNIT_B0, UNIT_B1, UNIT_NIL, UNIT_NIL }, + { UNIT_FM0, UNIT_FM1, UNIT_FM2, UNIT_B0, UNIT_B1, UNIT_NIL, UNIT_NIL, UNIT_NIL }, + { UNIT_FM0, UNIT_FM1, UNIT_B0, UNIT_B1, UNIT_NIL, UNIT_NIL, UNIT_NIL, UNIT_NIL }, + { UNIT_FM0, UNIT_B0, UNIT_B1, UNIT_NIL, UNIT_NIL, UNIT_NIL, UNIT_NIL, UNIT_NIL }, + { UNIT_NIL, UNIT_NIL, UNIT_NIL, UNIT_NIL, UNIT_NIL, UNIT_NIL, UNIT_NIL, UNIT_NIL } +}; + +/* Some insns are assigned specialized implementation units which map to + different actual implementation units on different machines. These + tables perform that mapping. */ +static CGEN_ATTR_VALUE_TYPE fr400_unit_mapping[] = +{ +/* unit in insn actual unit */ +/* NIL */ UNIT_NIL, +/* I0 */ UNIT_I0, +/* I1 */ UNIT_I1, +/* I01 */ UNIT_I01, +/* I2 */ UNIT_NIL, /* no I2 or I3 unit */ +/* I3 */ UNIT_NIL, +/* IALL */ UNIT_I01, /* only I0 and I1 units */ +/* FM0 */ UNIT_FM0, +/* FM1 */ UNIT_FM1, +/* FM01 */ UNIT_FM01, +/* FM2 */ UNIT_NIL, /* no F2 or M2 units */ +/* FM3 */ UNIT_NIL, /* no F3 or M3 units */ +/* FMALL */ UNIT_FM01,/* Only F0,F1,M0,M1 units */ +/* FMLOW */ UNIT_FM0, /* Only F0,M0 units */ +/* B0 */ UNIT_B0, /* branches only in B0 unit. */ +/* B1 */ UNIT_B0, +/* B01 */ UNIT_B0, +/* C */ UNIT_C, +/* MULT-DIV */ UNIT_I0, /* multiply and divide only in I0 unit. */ +/* LOAD */ UNIT_I0, /* load only in I0 unit. */ +/* STORE */ UNIT_I0, /* store only in I0 unit. */ +/* SCAN */ UNIT_I0, /* scan only in I0 unit. */ +/* DCPL */ UNIT_C, /* dcpl only in C unit. */ +/* MDUALACC */ UNIT_FM0, /* media dual acc insn only in FM0 unit. */ +/* MCLRACC-1*/ UNIT_FM0 /* mclracc,A==1 insn only in FM0 unit. */ +}; + +static CGEN_ATTR_VALUE_TYPE fr500_unit_mapping[] = +{ +/* unit in insn actual unit */ +/* NIL */ UNIT_NIL, +/* I0 */ UNIT_I0, +/* I1 */ UNIT_I1, +/* I01 */ UNIT_I01, +/* I2 */ UNIT_NIL, /* no I2 or I3 unit */ +/* I3 */ UNIT_NIL, +/* IALL */ UNIT_I01, /* only I0 and I1 units */ +/* FM0 */ UNIT_FM0, +/* FM1 */ UNIT_FM1, +/* FM01 */ UNIT_FM01, +/* FM2 */ UNIT_NIL, /* no F2 or M2 units */ +/* FM3 */ UNIT_NIL, /* no F3 or M2 units */ +/* FMALL */ UNIT_FM01,/* Only F0,F1,M0,M1 units */ +/* FMLOW */ UNIT_FM0, /* Only F0,M0 units */ +/* B0 */ UNIT_B0, +/* B1 */ UNIT_B1, +/* B01 */ UNIT_B01, +/* C */ UNIT_C, +/* MULT-DIV */ UNIT_I01, /* multiply and divide in I0 or I1 unit. */ +/* LOAD */ UNIT_I01, /* load in I0 or I1 unit. */ +/* STORE */ UNIT_I0, /* store only in I0 unit. */ +/* SCAN */ UNIT_I01, /* scan in I0 or I1 unit. */ +/* DCPL */ UNIT_C, /* dcpl only in C unit. */ +/* MDUALACC */ UNIT_FM0, /* media dual acc insn only in FM0 unit. */ +/* MCLRACC-1*/ UNIT_FM01 /* mclracc,A==1 in FM0 or FM1 unit. */ +}; + +static CGEN_ATTR_VALUE_TYPE fr550_unit_mapping[] = +{ +/* unit in insn actual unit */ +/* NIL */ UNIT_NIL, +/* I0 */ UNIT_I0, +/* I1 */ UNIT_I1, +/* I01 */ UNIT_I01, +/* I2 */ UNIT_I2, +/* I3 */ UNIT_I3, +/* IALL */ UNIT_IALL, +/* FM0 */ UNIT_FM0, +/* FM1 */ UNIT_FM1, +/* FM01 */ UNIT_FM01, +/* FM2 */ UNIT_FM2, +/* FM3 */ UNIT_FM3, +/* FMALL */ UNIT_FMALL, +/* FMLOW */ UNIT_FM01, /* Only F0,F1,M0,M1 units */ +/* B0 */ UNIT_B0, +/* B1 */ UNIT_B1, +/* B01 */ UNIT_B01, +/* C */ UNIT_C, +/* MULT-DIV */ UNIT_I01, /* multiply and divide in I0 or I1 unit. */ +/* LOAD */ UNIT_I01, /* load in I0 or I1 unit. */ +/* STORE */ UNIT_I01, /* store in I0 or I1 unit. */ +/* SCAN */ UNIT_IALL, /* scan in any integer unit. */ +/* DCPL */ UNIT_I0, /* dcpl only in I0 unit. */ +/* MDUALACC */ UNIT_FMALL,/* media dual acc insn in all media units */ +/* MCLRACC-1*/ UNIT_FM01 /* mclracc,A==1 in FM0 or FM1 unit. */ +}; + +void +frv_vliw_reset (FRV_VLIW *vliw, unsigned long mach, unsigned long elf_flags) +{ + vliw->next_slot = 0; + vliw->constraint_violation = 0; + vliw->mach = mach; + vliw->elf_flags = elf_flags; + + switch (mach) + { + case bfd_mach_fr400: + vliw->current_vliw = fr400_allowed_vliw; + vliw->unit_mapping = fr400_unit_mapping; + break; + case bfd_mach_fr550: + vliw->current_vliw = fr550_allowed_vliw; + vliw->unit_mapping = fr550_unit_mapping; + break; + default: + vliw->current_vliw = fr500_allowed_vliw; + vliw->unit_mapping = fr500_unit_mapping; + break; + } +} + +/* Return 1 if unit1 is a match for unit2. + Unit1 comes from the insn's UNIT attribute. unit2 comes from one of the + *_allowed_vliw tables above. */ +static int +match_unit (FRV_VLIW *vliw, + CGEN_ATTR_VALUE_TYPE unit1, CGEN_ATTR_VALUE_TYPE unit2) +{ + /* Map any specialized implementation units to actual ones. */ + unit1 = vliw->unit_mapping[unit1]; + + if (unit1 == unit2) + return 1; + if (unit1 < unit2) + return 0; + + switch (unit1) + { + case UNIT_I01: + case UNIT_FM01: + case UNIT_B01: + /* The 01 versions of these units are within 2 enums of the 0 or 1 + versions. */ + if (unit1 - unit2 <= 2) + return 1; + break; + case UNIT_IALL: + case UNIT_FMALL: + /* The ALL versions of these units are within 5 enums of the 0, 1, 2 or 3 + versions. */ + if (unit1 - unit2 <= 5) + return 1; + break; + default: + break; + } + + return 0; +} + +/* Return 1 if the vliws match, 0 otherwise. */ + +static int +match_vliw (VLIW_COMBO *vliw1, VLIW_COMBO *vliw2, int vliw_size) +{ + int i; + + for (i = 0; i < vliw_size; ++i) + { + if ((*vliw1)[i] != (*vliw2)[i]) + return 0; + } + + return 1; +} + +/* Find the next vliw vliw in the table that can accomodate the new insn. + If one is found then return it. Otherwise return NULL. */ + +static VLIW_COMBO * +add_next_to_vliw (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE unit) +{ + int next = vliw->next_slot; + VLIW_COMBO *current = vliw->current_vliw; + VLIW_COMBO *potential; + + if (next <= 0) + { + fprintf (stderr, "frv-opc.c line %d: bad vliw->next_slot value.\n", + __LINE__); + abort (); /* Should never happen */ + } + + /* The table is sorted by units allowed within slots, so vliws with + identical starting sequences are together. */ + potential = current; + do + { + if (match_unit (vliw, unit, (*potential)[next])) + return potential; + ++potential; + } + while (match_vliw (potential, current, next)); + + return NULL; +} + +/* Look for the given major insn type in the given vliw. Return 1 if found, + return 0 otherwise. */ + +static int +find_major_in_vliw (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major) +{ + int i; + + for (i = 0; i < vliw->next_slot; ++i) + if (vliw->major[i] == major) + return 1; + + return 0; +} + +/* Check for constraints between the insns in the vliw due to major insn + types. */ + +static int +fr400_check_insn_major_constraints ( + FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major +) +{ + /* In the cpu file, all media insns are represented as being allowed in + both media units. This makes it easier since this is the case for fr500. + Catch the invalid combinations here. Insns of major class FR400_MAJOR_M_2 + cannot coexist with any other media insn in a vliw. */ + switch (major) + { + case FR400_MAJOR_M_2: + return ! find_major_in_vliw (vliw, FR400_MAJOR_M_1) + && ! find_major_in_vliw (vliw, FR400_MAJOR_M_2); + default: + break; + } + return 1; +} + +static int +find_unit_in_vliw ( + FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE unit +) +{ + int i; + for (i = 0; i < vliw->next_slot; ++i) + if (CGEN_INSN_ATTR_VALUE (vliw->insn[i], CGEN_INSN_UNIT) == unit) + return 1; + + return 0; /* not found */ +} + +static int +find_major_in_slot ( + FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major, CGEN_ATTR_VALUE_TYPE slot +) +{ + int i; + + for (i = 0; i < vliw->next_slot; ++i) + if (vliw->major[i] == major && (*vliw->current_vliw)[i] == slot) + return 1; + + return 0; +} + +static int +fr550_find_media_in_vliw (FRV_VLIW *vliw) +{ + int i; + + for (i = 0; i < vliw->next_slot; ++i) + { + if (vliw->major[i] < FR550_MAJOR_M_1 || vliw->major[i] > FR550_MAJOR_M_5) + continue; + + /* Found a media insn, however, MNOP and MCLRACC don't count. */ + if (CGEN_INSN_NUM (vliw->insn[i]) == FRV_INSN_MNOP + || CGEN_INSN_NUM (vliw->insn[i]) == FRV_INSN_MCLRACC_0 + || CGEN_INSN_NUM (vliw->insn[i]) == FRV_INSN_MCLRACC_1) + continue; + + return 1; /* found one */ + } + + return 0; +} + +static int +fr550_find_float_in_vliw (FRV_VLIW *vliw) +{ + int i; + + for (i = 0; i < vliw->next_slot; ++i) + { + if (vliw->major[i] < FR550_MAJOR_F_1 || vliw->major[i] > FR550_MAJOR_F_4) + continue; + + /* Found a floating point insn, however, FNOP doesn't count. */ + if (CGEN_INSN_NUM (vliw->insn[i]) == FRV_INSN_FNOP) + continue; + + return 1; /* found one */ + } + + return 0; +} + +static int +fr550_check_insn_major_constraints ( + FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major, const CGEN_INSN *insn +) +{ + CGEN_ATTR_VALUE_TYPE unit; + CGEN_ATTR_VALUE_TYPE slot = (*vliw->current_vliw)[vliw->next_slot]; + switch (slot) + { + case UNIT_I2: + /* If it's a store, then there must be another store in I1 */ + unit = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_UNIT); + if (unit == UNIT_STORE) + return find_unit_in_vliw (vliw, UNIT_STORE); + break; + case UNIT_FM2: + case UNIT_FM3: + /* Floating point insns other than FNOP in slot f2 or f3 cannot coexist with + media insns. */ + if (major >= FR550_MAJOR_F_1 && major <= FR550_MAJOR_F_4 + && CGEN_INSN_NUM (insn) != FRV_INSN_FNOP) + return ! fr550_find_media_in_vliw (vliw); + /* Media insns other than MNOP in slot m2 or m3 cannot coexist with + floating point insns. */ + if (major >= FR550_MAJOR_M_1 && major <= FR550_MAJOR_M_5 + && CGEN_INSN_NUM (insn) != FRV_INSN_MNOP) + return ! fr550_find_float_in_vliw (vliw); + /* F-2 in slot f2 or f3 cannot coexist with F-2 or F-4 in slot f1 or f2 + respectively. + */ + if (major == FR550_MAJOR_F_2) + return ! find_major_in_slot (vliw, FR550_MAJOR_F_2, slot - (UNIT_FM2 - UNIT_FM0)) + && ! find_major_in_slot (vliw, FR550_MAJOR_F_4, slot - (UNIT_FM2 - UNIT_FM0)); + /* M-2 or M-5 in slot m2 or m3 cannot coexist with M-2 in slot m1 or m2 + respectively. */ + if (major == FR550_MAJOR_M_2 || major == FR550_MAJOR_M_5) + return ! find_major_in_slot (vliw, FR550_MAJOR_M_2, slot - (UNIT_FM2 - UNIT_FM0)); + /* M-4 in slot m2 or m3 cannot coexist with M-4 in slot m1 or m2 + respectively. */ + if (major == FR550_MAJOR_M_4) + return ! find_major_in_slot (vliw, FR550_MAJOR_M_4, slot - (UNIT_FM2 - UNIT_FM0)); + break; + default: + break; + } + return 1; /* all ok */ +} + +static int +fr500_check_insn_major_constraints ( + FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major +) +{ + /* TODO: A table might be faster for some of the more complex instances + here. */ + switch (major) + { + case FR500_MAJOR_I_1: + case FR500_MAJOR_I_4: + case FR500_MAJOR_I_5: + case FR500_MAJOR_I_6: + case FR500_MAJOR_B_1: + case FR500_MAJOR_B_2: + case FR500_MAJOR_B_3: + case FR500_MAJOR_B_4: + case FR500_MAJOR_B_5: + case FR500_MAJOR_B_6: + case FR500_MAJOR_F_4: + case FR500_MAJOR_F_8: + case FR500_MAJOR_M_8: + return 1; /* OK */ + case FR500_MAJOR_I_2: + /* Cannot coexist with I-3 insn. */ + return ! find_major_in_vliw (vliw, FR500_MAJOR_I_3); + case FR500_MAJOR_I_3: + /* Cannot coexist with I-2 insn. */ + return ! find_major_in_vliw (vliw, FR500_MAJOR_I_2); + case FR500_MAJOR_F_1: + case FR500_MAJOR_F_2: + /* Cannot coexist with F-5, F-6, or M-7 insn. */ + return ! find_major_in_vliw (vliw, FR500_MAJOR_F_5) + && ! find_major_in_vliw (vliw, FR500_MAJOR_F_6) + && ! find_major_in_vliw (vliw, FR500_MAJOR_M_7); + case FR500_MAJOR_F_3: + /* Cannot coexist with F-7, or M-7 insn. */ + return ! find_major_in_vliw (vliw, FR500_MAJOR_F_7) + && ! find_major_in_vliw (vliw, FR500_MAJOR_M_7); + case FR500_MAJOR_F_5: + /* Cannot coexist with F-1, F-2, F-6, F-7, or M-7 insn. */ + return ! find_major_in_vliw (vliw, FR500_MAJOR_F_1) + && ! find_major_in_vliw (vliw, FR500_MAJOR_F_2) + && ! find_major_in_vliw (vliw, FR500_MAJOR_F_6) + && ! find_major_in_vliw (vliw, FR500_MAJOR_F_7) + && ! find_major_in_vliw (vliw, FR500_MAJOR_M_7); + case FR500_MAJOR_F_6: + /* Cannot coexist with F-1, F-2, F-5, F-6, or M-7 insn. */ + return ! find_major_in_vliw (vliw, FR500_MAJOR_F_1) + && ! find_major_in_vliw (vliw, FR500_MAJOR_F_2) + && ! find_major_in_vliw (vliw, FR500_MAJOR_F_5) + && ! find_major_in_vliw (vliw, FR500_MAJOR_F_6) + && ! find_major_in_vliw (vliw, FR500_MAJOR_M_7); + case FR500_MAJOR_F_7: + /* Cannot coexist with F-3, F-5, F-7, or M-7 insn. */ + return ! find_major_in_vliw (vliw, FR500_MAJOR_F_3) + && ! find_major_in_vliw (vliw, FR500_MAJOR_F_5) + && ! find_major_in_vliw (vliw, FR500_MAJOR_F_7) + && ! find_major_in_vliw (vliw, FR500_MAJOR_M_7); + case FR500_MAJOR_M_1: + /* Cannot coexist with M-7 insn. */ + return ! find_major_in_vliw (vliw, FR500_MAJOR_M_7); + case FR500_MAJOR_M_2: + case FR500_MAJOR_M_3: + /* Cannot coexist with M-5, M-6 or M-7 insn. */ + return ! find_major_in_vliw (vliw, FR500_MAJOR_M_5) + && ! find_major_in_vliw (vliw, FR500_MAJOR_M_6) + && ! find_major_in_vliw (vliw, FR500_MAJOR_M_7); + case FR500_MAJOR_M_4: + /* Cannot coexist with M-6 insn. */ + return ! find_major_in_vliw (vliw, FR500_MAJOR_M_6); + case FR500_MAJOR_M_5: + /* Cannot coexist with M-2, M-3, M-5, M-6 or M-7 insn. */ + return ! find_major_in_vliw (vliw, FR500_MAJOR_M_2) + && ! find_major_in_vliw (vliw, FR500_MAJOR_M_3) + && ! find_major_in_vliw (vliw, FR500_MAJOR_M_5) + && ! find_major_in_vliw (vliw, FR500_MAJOR_M_6) + && ! find_major_in_vliw (vliw, FR500_MAJOR_M_7); + case FR500_MAJOR_M_6: + /* Cannot coexist with M-2, M-3, M-4, M-5, M-6 or M-7 insn. */ + return ! find_major_in_vliw (vliw, FR500_MAJOR_M_2) + && ! find_major_in_vliw (vliw, FR500_MAJOR_M_3) + && ! find_major_in_vliw (vliw, FR500_MAJOR_M_4) + && ! find_major_in_vliw (vliw, FR500_MAJOR_M_5) + && ! find_major_in_vliw (vliw, FR500_MAJOR_M_6) + && ! find_major_in_vliw (vliw, FR500_MAJOR_M_7); + case FR500_MAJOR_M_7: + /* Cannot coexist with M-1, M-2, M-3, M-5, M-6 or M-7 insn. */ + return ! find_major_in_vliw (vliw, FR500_MAJOR_M_1) + && ! find_major_in_vliw (vliw, FR500_MAJOR_M_2) + && ! find_major_in_vliw (vliw, FR500_MAJOR_M_3) + && ! find_major_in_vliw (vliw, FR500_MAJOR_M_5) + && ! find_major_in_vliw (vliw, FR500_MAJOR_M_6) + && ! find_major_in_vliw (vliw, FR500_MAJOR_M_7) + && ! find_major_in_vliw (vliw, FR500_MAJOR_F_1) + && ! find_major_in_vliw (vliw, FR500_MAJOR_F_2) + && ! find_major_in_vliw (vliw, FR500_MAJOR_F_3) + && ! find_major_in_vliw (vliw, FR500_MAJOR_F_5) + && ! find_major_in_vliw (vliw, FR500_MAJOR_F_6) + && ! find_major_in_vliw (vliw, FR500_MAJOR_F_7); + default: + fprintf (stderr, "frv-opc.c, line %d: bad major code, aborting.\n", + __LINE__); + abort (); + break; + } + return 1; +} + +static int +check_insn_major_constraints ( + FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major, const CGEN_INSN *insn +) +{ + int rc; + switch (vliw->mach) + { + case bfd_mach_fr400: + rc = fr400_check_insn_major_constraints (vliw, major); + break; + case bfd_mach_fr550: + rc = fr550_check_insn_major_constraints (vliw, major, insn); + break; + default: + rc = fr500_check_insn_major_constraints (vliw, major); + break; + } + return rc; +} + +/* Add in insn to the VLIW vliw if possible. Return 0 if successful, + non-zero otherwise. */ +int +frv_vliw_add_insn (FRV_VLIW *vliw, const CGEN_INSN *insn) +{ + int index; + CGEN_ATTR_VALUE_TYPE major; + CGEN_ATTR_VALUE_TYPE unit; + VLIW_COMBO *new_vliw; + + if (vliw->constraint_violation || CGEN_INSN_INVALID_P (insn)) + return 1; + + index = vliw->next_slot; + if (index >= FRV_VLIW_SIZE) + return 1; + + unit = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_UNIT); + if (unit == UNIT_NIL) + { + fprintf (stderr, "frv-opc.c line %d: bad insn unit.\n", + __LINE__); + abort (); /* no UNIT specified for this insn in frv.cpu */ + } + + switch (vliw->mach) + { + case bfd_mach_fr400: + major = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR400_MAJOR); + break; + case bfd_mach_fr550: + major = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR550_MAJOR); + break; + default: + major = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR500_MAJOR); + break; + } + + if (index <= 0) + { + /* Any insn can be added to slot 0. */ + while (! match_unit (vliw, unit, (*vliw->current_vliw)[0])) + ++vliw->current_vliw; + vliw->major[0] = major; + vliw->insn[0] = insn; + vliw->next_slot = 1; + return 0; + } + + /* If there are already insns in the vliw(s) check to see that + this one can be added. Do this by finding an allowable vliw + combination that can accept the new insn. */ + if (! (vliw->elf_flags & EF_FRV_NOPACK)) + { + new_vliw = add_next_to_vliw (vliw, unit); + if (new_vliw && check_insn_major_constraints (vliw, major, insn)) + { + vliw->current_vliw = new_vliw; + vliw->major[index] = major; + vliw->insn[index] = insn; + vliw->next_slot++; + return 0; + } + + /* The frv machine supports all packing conbinations. If we fail, + to add the insn, then it could not be handled as if it was the fr500. + Just return as if it was handled ok. */ + if (vliw->mach == bfd_mach_frv) + return 0; + } + + vliw->constraint_violation = 1; + return 1; +} + +int +spr_valid (regno) + long regno; +{ + if (regno < 0) return 0; + if (regno <= 4095) return 1; + return 0; +} +/* -- */ + +/* -- asm.c */ +static const char * parse_ulo16 + PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *)); +static const char * parse_uslo16 + PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *)); +static const char * parse_uhi16 + PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *)); +static long parse_register_number + PARAMS ((const char **)); +static const char * parse_spr + PARAMS ((CGEN_CPU_DESC, const char **, CGEN_KEYWORD *, long *)); +static const char * parse_d12 + PARAMS ((CGEN_CPU_DESC, const char **, int, long *)); +static const char * parse_s12 + PARAMS ((CGEN_CPU_DESC, const char **, int, long *)); +static const char * parse_u12 + PARAMS ((CGEN_CPU_DESC, const char **, int, long *)); +static const char * parse_even_register + PARAMS ((CGEN_CPU_DESC, const char **, CGEN_KEYWORD *, long *)); +static const char * parse_A0 + PARAMS ((CGEN_CPU_DESC, const char **, int, long *)); +static const char * parse_A1 + PARAMS ((CGEN_CPU_DESC, const char **, int, long *)); +static const char * parse_A + PARAMS ((CGEN_CPU_DESC, const char **, int, long *, long)); + +static const char * +parse_ulo16 (cd, strp, opindex, valuep) + CGEN_CPU_DESC cd; + const char **strp; + int opindex; + unsigned long *valuep; +{ + const char *errmsg; + enum cgen_parse_operand_result result_type; + bfd_vma value; + + if (**strp == '#' || **strp == '%') + { + if (strncasecmp (*strp + 1, "lo(", 3) == 0) + { + *strp += 4; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_FRV_LO16, + &result_type, &value); + if (**strp != ')') + return "missing `)'"; + ++*strp; + if (errmsg == NULL + && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) + value &= 0xffff; + *valuep = value; + return errmsg; + } + if (strncasecmp (*strp + 1, "gprello(", 8) == 0) + { + *strp += 9; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_FRV_GPRELLO, + &result_type, &value); + if (**strp != ')') + return "missing ')'"; + ++*strp; + if (errmsg == NULL + && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) + value >>= 16; + *valuep = value; + return errmsg; + } + } + return cgen_parse_signed_integer (cd, strp, opindex, valuep); +} + +static const char * +parse_uslo16 (cd, strp, opindex, valuep) + CGEN_CPU_DESC cd; + const char **strp; + int opindex; + unsigned long *valuep; +{ + const char *errmsg; + enum cgen_parse_operand_result result_type; + bfd_vma value; + + if (**strp == '#' || **strp == '%') + { + if (strncasecmp (*strp + 1, "lo(", 3) == 0) + { + *strp += 4; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_FRV_LO16, + &result_type, &value); + if (**strp != ')') + return "missing `)'"; + ++*strp; + if (errmsg == NULL + && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) + value &= 0xffff; + *valuep = value; + return errmsg; + } + else if (strncasecmp (*strp + 1, "gprello(", 8) == 0) + { + *strp += 9; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_FRV_GPRELLO, + &result_type, &value); + if (**strp != ')') + return "missing ')'"; + ++*strp; + if (errmsg == NULL + && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) + value &= 0xffff; + *valuep = value; + return errmsg; + } + } + return cgen_parse_unsigned_integer (cd, strp, opindex, valuep); +} + +static const char * +parse_uhi16 (cd, strp, opindex, valuep) + CGEN_CPU_DESC cd; + const char **strp; + int opindex; + unsigned long *valuep; +{ + const char *errmsg; + enum cgen_parse_operand_result result_type; + bfd_vma value; + + if (**strp == '#' || **strp == '%') + { + if (strncasecmp (*strp + 1, "hi(", 3) == 0) + { + *strp += 4; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_FRV_HI16, + &result_type, &value); + if (**strp != ')') + return "missing `)'"; + ++*strp; + if (errmsg == NULL + && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) + value >>= 16; + *valuep = value; + return errmsg; + } + else if (strncasecmp (*strp + 1, "gprelhi(", 8) == 0) + { + *strp += 9; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_FRV_GPRELHI, + &result_type, &value); + if (**strp != ')') + return "missing ')'"; + ++*strp; + if (errmsg == NULL + && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) + value >>= 16; + *valuep = value; + return errmsg; + } + } + return cgen_parse_unsigned_integer (cd, strp, opindex, valuep); +} + +static long +parse_register_number (strp) + const char **strp; +{ + int regno; + if (**strp < '0' || **strp > '9') + return -1; /* error */ + + regno = **strp - '0'; + for (++*strp; **strp >= '0' && **strp <= '9'; ++*strp) + regno = regno * 10 + (**strp - '0'); + + return regno; +} + +static const char * +parse_spr (cd, strp, table, valuep) + CGEN_CPU_DESC cd; + const char **strp; + CGEN_KEYWORD * table; + long *valuep; +{ + const char *save_strp; + long regno; + + /* Check for spr index notation. */ + if (strncasecmp (*strp, "spr[", 4) == 0) + { + *strp += 4; + regno = parse_register_number (strp); + if (**strp != ']') + return "missing `]'"; + ++*strp; + if (! spr_valid (regno)) + return "Special purpose register number is out of range"; + *valuep = regno; + return NULL; + } + + save_strp = *strp; + regno = parse_register_number (strp); + if (regno != -1) + { + if (! spr_valid (regno)) + return "Special purpose register number is out of range"; + *valuep = regno; + return NULL; + } + + *strp = save_strp; + return cgen_parse_keyword (cd, strp, table, valuep); +} + +static const char * +parse_d12 (cd, strp, opindex, valuep) + CGEN_CPU_DESC cd; + const char **strp; + int opindex; + long *valuep; +{ + const char *errmsg; + enum cgen_parse_operand_result result_type; + bfd_vma value; + + /* Check for small data reference. */ + if (**strp == '#' || **strp == '%') + { + if (strncasecmp (*strp + 1, "gprel12(", 8) == 0) + { + *strp += 9; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_FRV_GPREL12, + &result_type, &value); + if (**strp != ')') + return "missing `)'"; + ++*strp; + *valuep = value; + return errmsg; + } + } + return cgen_parse_signed_integer (cd, strp, opindex, valuep); +} + +static const char * +parse_s12 (cd, strp, opindex, valuep) + CGEN_CPU_DESC cd; + const char **strp; + int opindex; + long *valuep; +{ + const char *errmsg; + enum cgen_parse_operand_result result_type; + bfd_vma value; + + /* Check for small data reference. */ + if ((**strp == '#' || **strp == '%') + && strncasecmp (*strp + 1, "gprel12(", 8) == 0) + { + *strp += 9; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_FRV_GPREL12, + &result_type, &value); + if (**strp != ')') + return "missing `)'"; + ++*strp; + *valuep = value; + return errmsg; + } + else + { + if (**strp == '#') + ++*strp; + return cgen_parse_signed_integer (cd, strp, opindex, valuep); + } +} + +static const char * +parse_u12 (cd, strp, opindex, valuep) + CGEN_CPU_DESC cd; + const char **strp; + int opindex; + long *valuep; +{ + const char *errmsg; + enum cgen_parse_operand_result result_type; + bfd_vma value; + + /* Check for small data reference. */ + if ((**strp == '#' || **strp == '%') + && strncasecmp (*strp + 1, "gprel12(", 8) == 0) + { + *strp += 9; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_FRV_GPRELU12, + &result_type, &value); + if (**strp != ')') + return "missing `)'"; + ++*strp; + *valuep = value; + return errmsg; + } + else + { + if (**strp == '#') + ++*strp; + return cgen_parse_signed_integer (cd, strp, opindex, valuep); + } +} + +static const char * +parse_A (cd, strp, opindex, valuep, A) + CGEN_CPU_DESC cd; + const char **strp; + int opindex; + long *valuep; + long A; +{ + const char *errmsg; + + if (**strp == '#') + ++*strp; + + errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, valuep); + if (errmsg) + return errmsg; + + if (*valuep != A) + return "Value of A operand must be 0 or 1"; + + return NULL; +} + +static const char * +parse_A0 (cd, strp, opindex, valuep) + CGEN_CPU_DESC cd; + const char **strp; + int opindex; + long *valuep; +{ + return parse_A (cd, strp, opindex, valuep, 0); +} + +static const char * +parse_A1 (cd, strp, opindex, valuep) + CGEN_CPU_DESC cd; + const char **strp; + int opindex; + long *valuep; +{ + return parse_A (cd, strp, opindex, valuep, 1); +} + +static const char * +parse_even_register (cd, strP, tableP, valueP) + CGEN_CPU_DESC cd; + const char ** strP; + CGEN_KEYWORD * tableP; + long * valueP; +{ + const char * errmsg; + const char * saved_star_strP = * strP; + + errmsg = cgen_parse_keyword (cd, strP, tableP, valueP); + + if (errmsg == NULL && ((* valueP) & 1)) + { + errmsg = _("register number must be even"); + * strP = saved_star_strP; + } + + return errmsg; +} +/* -- */ + +/* -- dis.c */ +static void print_spr + PARAMS ((CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned)); +static void print_hi + PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int)); +static void print_lo + PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int)); + +static void +print_spr (cd, dis_info, names, regno, attrs) + CGEN_CPU_DESC cd; + PTR dis_info; + CGEN_KEYWORD *names; + long regno; + unsigned int attrs; +{ + /* Use the register index format for any unnamed registers. */ + if (cgen_keyword_lookup_value (names, regno) == NULL) + { + disassemble_info *info = (disassemble_info *) dis_info; + (*info->fprintf_func) (info->stream, "spr[%ld]", regno); + } + else + print_keyword (cd, dis_info, names, regno, attrs); +} + +static void +print_hi (cd, dis_info, value, attrs, pc, length) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + PTR dis_info; + long value; + unsigned int attrs ATTRIBUTE_UNUSED; + bfd_vma pc ATTRIBUTE_UNUSED; + int length ATTRIBUTE_UNUSED; +{ + disassemble_info *info = (disassemble_info *) dis_info; + if (value) + (*info->fprintf_func) (info->stream, "0x%lx", value); + else + (*info->fprintf_func) (info->stream, "hi(0x%lx)", value); +} + +static void +print_lo (cd, dis_info, value, attrs, pc, length) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + PTR dis_info; + long value; + unsigned int attrs ATTRIBUTE_UNUSED; + bfd_vma pc ATTRIBUTE_UNUSED; + int length ATTRIBUTE_UNUSED; +{ + disassemble_info *info = (disassemble_info *) dis_info; + if (value) + (*info->fprintf_func) (info->stream, "0x%lx", value); + else + (*info->fprintf_func) (info->stream, "lo(0x%lx)", value); +} + +/* -- */ diff --git a/cpu/iq10.cpu b/cpu/iq10.cpu new file mode 100644 index 0000000..322f3cc --- /dev/null +++ b/cpu/iq10.cpu @@ -0,0 +1,1111 @@ +; IQ10-only CPU description. -*- Scheme -*- +; +; Copyright 2001, 2002 Free Software Foundation, Inc. +; +; Contributed by Red Hat Inc; developed under contract from Vitesse. +; +; This file is part of the GNU Binutils. +; +; This program is free software; you can redistribute it and/or modify +; it under the terms of the GNU General Public License as published by +; the Free Software Foundation; either version 2 of the License, or +; (at your option) any later version. +; +; This program is distributed in the hope that it will be useful, +; but WITHOUT ANY WARRANTY; without even the implied warranty of +; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +; GNU General Public License for more details. +; +; You should have received a copy of the GNU General Public License +; along with this program; if not, write to the Free Software +; Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + + +; Instructions. + +(dni andoui-q10 "iq10 and upper ones immediate" (MACH10 USES-RS USES-RT) + "andoui $rt,$rs,$hi16" + (+ OP10_ANDOUI rs rt hi16) + (set rt (and rs (or (sll hi16 16) #xFFFF))) + ()) + +(dni andoui2-q10 "iq10 and upper ones immediate" (ALIAS NO-DIS MACH10 USES-RS USES-RT) + "andoui ${rt-rs},$hi16" + (+ OP10_ANDOUI rt-rs hi16) + (set rt-rs (and rt-rs (or (sll hi16 16) #xFFFF))) + ()) + +(dni orui-q10 "or upper immediate" (MACH10 USES-RS USES-RT) + "orui $rt,$rs,$hi16" + (+ OP10_ORUI rs rt hi16) + (set rt (or rs (sll hi16 16))) + ()) + +(dni orui2-q10 "or upper immediate" (ALIAS NO-DIS MACH10 USES-RS USES-RT) + "orui ${rt-rs},$hi16" + (+ OP10_ORUI rt-rs hi16) + (set rt-rs (or rt-rs (sll hi16 16))) + ()) + +(dni mrgbq10 "merge bytes" (MACH10 USES-RD USES-RS USES-RT) + "mrgb $rd,$rs,$rt,$maskq10" + (+ OP_SPECIAL rs rt rd maskq10 FUNC_MRGB) + (sequence ((SI temp)) + (if (bitclear? mask 0) + (set temp (and rs #xFF)) + (set temp (and rt #xFF))) + (if (bitclear? mask 1) + (set temp (or temp (and rs #xFF00))) + (set temp (or temp (and rt #xFF00)))) + (if (bitclear? mask 2) + (set temp (or temp (and rs #xFF0000))) + (set temp (or temp (and rt #xFF0000)))) + (if (bitclear? mask 3) + (set temp (or temp (and rs #xFF000000))) + (set temp (or temp (and rt #xFF000000)))) + (set rd temp)) + ()) + +(dni mrgbq102 "merge bytes" (ALIAS NO-DIS MACH10 USES-RD USES-RS USES-RT) + "mrgb ${rd-rs},$rt,$maskq10" + (+ OP_SPECIAL rt rd-rs maskq10 FUNC_MRGB) + (sequence ((SI temp)) + (if (bitclear? mask 0) + (set temp (and rd-rs #xFF)) + (set temp (and rt #xFF))) + (if (bitclear? mask 1) + (set temp (or temp (and rd-rs #xFF00))) + (set temp (or temp (and rt #xFF00)))) + (if (bitclear? mask 2) + (set temp (or temp (and rd-rs #xFF0000))) + (set temp (or temp (and rt #xFF0000)))) + (if (bitclear? mask 3) + (set temp (or temp (and rd-rs #xFF000000))) + (set temp (or temp (and rt #xFF000000)))) + (set rd-rs temp)) + ()) + +; In the future, we'll want the j & jal to use the 21 bit target, with +; the upper five bits shifted up. For now, give 'em the 16 bit target. + +(dni jq10 "jump" (MACH10) + "j $jmptarg" + (+ OP_J (f-rs 0) (f-rt 0) jmptarg) +; "j $jmptargq10" +; (+ OP_J upper-5-jmptargq10 (f-rt 0) lower-16-jmptargq10) + (delay 1 (set pc jmptarg)) + ()) + +(dni jalq10 "jump and link" (MACH10 USES-RT) + "jal $rt,$jmptarg" + (+ OP_JAL (f-rs 0) rt jmptarg) +; "jal $rt,$jmptargq10" +; (+ OP_JAL upper-5-jmptargq10 rt lower-16-jmptargq10) + (delay 1 + (sequence () + (set rt (add pc 8)) + (set pc jmptarg))) + ()) + +(dni jalq10-2 "jump and link, implied r31" (MACH10 USES-RT) + "jal $jmptarg" + (+ OP_JAL (f-rs 0) (f-rt 31) jmptarg) + (delay 1 + (sequence () + (set rt (add pc 8)) + (set pc jmptarg))) + ()) + +; Branch instructions. + +(dni bbil "branch bit immediate likely" (MACH10 USES-RS) + "bbil $rs($bitnum),$offset" + (+ OP10_BBIL rs bitnum offset) + (if (bitset? rs bitnum) + (delay 1 (set pc offset)) + (skip 1)) + ()) + +(dni bbinl "branch bit immediate negated likely" (MACH10 USES-RS) + "bbinl $rs($bitnum),$offset" + (+ OP10_BBINL rs bitnum offset) + (if (bitclear? rs bitnum) + (delay 1 (set pc offset)) + (skip 1)) + ()) + +(dni bbvl "branch bit variable likely" (MACH10 USES-RS USES-RT) + "bbvl $rs,$rt,$offset" + (+ OP10_BBVL rs rt offset) + (if (bitset? rs (and rt #x1F)) + (delay 1 (set pc offset)) + (skip 1)) + ()) + +(dni bbvnl "branch bit variable negated likely" (MACH10 USES-RS USES-RT) + "bbvnl $rs,$rt,$offset" + (+ OP10_BBVNL rs rt offset) + (if (bitclear? rs (and rt #x1F)) + (delay 1 (set pc offset)) + (skip 1)) + ()) + +(dni bgtzal "branch if greater than zero and link" (MACH10 USES-RS USES-R31) + "bgtzal $rs,$offset" + (+ OP_REGIMM rs FUNC_BGTZAL offset) + (if (gt rs 0) + (sequence () + (set (reg h-gr 31) (add pc 8)) + (delay 1 (set pc offset)))) + ()) + +(dni bgtzall + "branch if greater than zero and link likely" (MACH10 USES-RS USES-R31) + "bgtzall $rs,$offset" + (+ OP_REGIMM rs FUNC_BGTZALL offset) + (if (gt rs 0) + (sequence () + (set (reg h-gr 31) (add pc 8)) + (delay 1 (set pc offset))) + (skip 1)) + ()) + +(dni blezal "branch if less than or equal to zero and link" (MACH10 USES-RS USES-R31) + "blezal $rs,$offset" + (+ OP_REGIMM rs FUNC_BLEZAL offset) + (if (le rs 0) + (sequence () + (set (reg h-gr 31) (add pc 8)) + (delay 1 (set pc offset)))) + ()) + +(dni blezall + "branch if less than or equal to zero and link likely" (MACH10 USES-RS USES-R31) + "blezall $rs,$offset" + (+ OP_REGIMM rs FUNC_BLEZALL offset) + (if (le rs 0) + (sequence () + (set (reg h-gr 31) (add pc 8)) + (delay 1 (set pc offset))) + (skip 1)) + ()) + +(dni bgtz-q10 "branch if greater than zero" (MACH10 USES-RS) + "bgtz $rs,$offset" + (+ OP_REGIMM rs FUNC_BGTZ offset) + (if (gt rs 0) + (delay 1 (set pc offset))) + ()) + +(dni bgtzl-q10 "branch if greater than zero likely" (MACH10 USES-RS) + "bgtzl $rs,$offset" + (+ OP_REGIMM rs FUNC_BGTZL offset) + (if (gt rs 0) + (delay 1 (set pc offset)) + (skip 1)) + ()) + + +(dni blez-q10 "branch if less than or equal to zero" (MACH10 USES-RS) + "blez $rs,$offset" + (+ OP_REGIMM rs FUNC_BLEZ offset) + (if (le rs 0) + (delay 1 (set pc offset))) + ()) + +(dni blezl-q10 "branch if less than or equal to zero likely" (MACH10 USES-RS) + "blezl $rs,$offset" + (+ OP_REGIMM rs FUNC_BLEZL offset) + (if (le rs 0) + (delay 1 (set pc offset)) + (skip 1)) + ()) + +(dni bmb-q10 "branch if matching byte-lane" (MACH10 USES-RS USES-RT) + "bmb $rs,$rt,$offset" + (+ OP10_BMB rs rt offset) + (sequence ((BI branch?)) + (set branch? 0) + (if (eq (and rs #xFF) (and rt #xFF)) + (set branch? 1)) + (if (eq (and rs #xFF00) (and rt #xFF00)) + (set branch? 1)) + (if (eq (and rs #xFF0000) (and rt #xFF0000)) + (set branch? 1)) + (if (eq (and rs #xFF000000) (and rt #xFF000000)) + (set branch? 1)) + (if branch? + (delay 1 (set pc offset)))) + ()) + +(dni bmbl "branch if matching byte-lane likely" (MACH10 USES-RS USES-RT) + "bmbl $rs,$rt,$offset" + (+ OP10_BMBL rs rt offset) + (sequence ((BI branch?)) + (set branch? 0) + (if (eq (and rs #xFF) (and rt #xFF)) + (set branch? 1)) + (if (eq (and rs #xFF00) (and rt #xFF00)) + (set branch? 1)) + (if (eq (and rs #xFF0000) (and rt #xFF0000)) + (set branch? 1)) + (if (eq (and rs #xFF000000) (and rt #xFF000000)) + (set branch? 1)) + (if branch? + (delay 1 (set pc offset)) + (skip 1))) + ()) + +(dni bri "branch if register invalid" (MACH10 USES-RS) + "bri $rs,$offset" + (+ OP_REGIMM rs FUNC_BRI offset) + (if (gt rs 0) + (delay 1 (set pc offset)) + (skip 1)) + ()) + +(dni brv "branch if register invalid" (MACH10 USES-RS) + "brv $rs,$offset" + (+ OP_REGIMM rs FUNC_BRV offset) + (if (gt rs 0) + (delay 1 (set pc offset)) + (skip 1)) + ()) + +; debug instructions + +(dni bctx "branch if the current context == instruction[21]" (MACH10 USES-RS) + "bctx $rs,$offset" + (+ OP_REGIMM rs FUNC_BCTX offset) + (delay 1 (set pc offset)) + ()) + +(dni yield "unconditional yield to the other context" (MACH10) + "yield" + (+ OP_SPECIAL (f-rs 0) (f-rt 0) (f-rd 0) (f-shamt 0) FUNC10_YIELD) + (unimp yield) + ()) + +; Special instructions. + +(dni crc32 "CRC, 32 bit input" (MACH10 USES-RD USES-RS USES-RT) + "crc32 $rd,$rs,$rt" + (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_CRC32) + (unimp crc32) + ()) + +(dni crc32b "CRC, 8 bit input" (MACH10 USES-RD USES-RS USES-RT) + "crc32b $rd,$rs,$rt" + (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_CRC32B) + (unimp crc32b) + ()) + +(dni cnt1s "Count ones" (MACH10 USES-RD USES-RS) + "cnt1s $rd,$rs" + (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC10_CNT1S) + (unimp crcp) + ()) + + +; Special Instructions + +(dni avail "Mark Header Buffer Available" (MACH10 USES-RD) + "avail $rd" + (+ OP_COP3 (f-rs 0) (f-rt 0) rd (f-shamt 0) FUNC10_AVAIL) + (unimp avail) + ()) + +(dni free "Mark Header Buffer Free" (MACH10 USES-RS USES-RD) + "free $rd,$rs" + (+ OP_COP3 rs (f-rt 0) rd (f-shamt 0) FUNC10_FREE) + (unimp free) + ()) + +(dni tstod "Test Header Buffer Order Dependency" (MACH10 USES-RS USES-RD) + "tstod $rd,$rs" + (+ OP_COP3 rs (f-rt 0) rd (f-shamt 0) FUNC10_TSTOD) + (unimp tstod) + ()) + +(dni cmphdr "Get a Complete Header" (MACH10 USES-RD) + "cmphdr $rd" + (+ OP_COP3 (f-rs 0) (f-rt 0) rd (f-shamt 0) FUNC10_CMPHDR) + (unimp cmphdr) + ()) + +(dni mcid "Allocate a Multicast ID" (MACH10 USES-RD USES-RT) + "mcid $rd,$rt" + (+ OP_COP3 (f-rs 0) rt rd (f-shamt 0) FUNC10_MCID) + (unimp mcid) + ()) + +(dni dba "Allocate a Data Buffer Pointer" (MACH10 USES-RD) + "dba $rd" + (+ OP_COP3 (f-rs 0) (f-rt 0) rd (f-shamt 0) FUNC10_DBA) + (unimp dba) + ()) + +(dni dbd "Deallocate a Data Buffer Pointer" (MACH10 USES-RS USES-RT USES-RD) + "dbd $rd,$rs,$rt" + (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_DBD) + (unimp dbd) + ()) + +(dni dpwt "DSTN_PORT Write" (MACH10 USES-RS USES-RD) + "dpwt $rd,$rs" + (+ OP_COP3 rs (f-rt 0) rd (f-shamt 0) FUNC10_DPWT) + (unimp dpwt) + ()) + +; Architectural and coprocessor instructions. + +(dni chkhdrq10 "" (MACH10 USES-RS USES-RD) + "chkhdr $rd,$rs" + (+ OP_COP3 rs (f-rt 0) rd (f-shamt 0) FUNC10_CHKHDR) + (unimp chkhdr) + ()) + +; Coprocessor DMA Instructions (IQ10) + +(dni rba "Read Bytes Absolute" (MACH10 USES-RS USES-RT USES-RD) + "rba $rd,$rs,$rt" + (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_RBA) + (unimp rba) + ()) + +(dni rbal "Read Bytes Absolute and Lock" (MACH10 USES-RS USES-RT USES-RD) + "rbal $rd,$rs,$rt" + (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_RBAL) + (unimp rbal) + ()) + +(dni rbar "Read Bytes Absolute and Release" (MACH10 USES-RS USES-RT USES-RD) + "rbar $rd,$rs,$rt" + (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_RBAR) + (unimp rbar) + ()) + +(dni wba "Write Bytes Absolute" (MACH10 USES-RS USES-RT USES-RD) + "wba $rd,$rs,$rt" + (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_WBA) + (unimp wba) + ()) + +(dni wbau "Write Bytes Absolute and Unlock" (MACH10 USES-RS USES-RT USES-RD) + "wbau $rd,$rs,$rt" + (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_WBAU) + (unimp wbau) + ()) + +(dni wbac "Write Bytes Absolute Cacheable" (MACH10 USES-RS USES-RT USES-RD) + "wbac $rd,$rs,$rt" + (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_WBAC) + (unimp wbac) + ()) + +(dni rbi "Read Bytes Immediate" (MACH10 USES-RD USES-RS USES-RT) + "rbi $rd,$rs,$rt,$bytecount" + (+ OP_COP3 rs rt rd FUNC10_RBI bytecount) + (unimp rbi) + ()) + +(dni rbil "Read Bytes Immediate and Lock" (MACH10 USES-RD USES-RS USES-RT) + "rbil $rd,$rs,$rt,$bytecount" + (+ OP_COP3 rs rt rd FUNC10_RBIL bytecount) + (unimp rbil) + ()) + +(dni rbir "Read Bytes Immediate and Release" (MACH10 USES-RD USES-RS USES-RT) + "rbir $rd,$rs,$rt,$bytecount" + (+ OP_COP3 rs rt rd FUNC10_RBIR bytecount) + (unimp rbir) + ()) + +(dni wbi "Write Bytes Immediate" (MACH10 USES-RD USES-RS USES-RT) + "wbi $rd,$rs,$rt,$bytecount" + (+ OP_COP3 rs rt rd FUNC10_WBI bytecount) + (unimp wbi) + ()) + +(dni wbic "Write Bytes Immediate Cacheable" (MACH10 USES-RD USES-RS USES-RT) + "wbic $rd,$rs,$rt,$bytecount" + (+ OP_COP3 rs rt rd FUNC10_WBIC bytecount) + (unimp wbic) + ()) + +(dni wbiu "Write Bytes Immediate" (MACH10 USES-RD USES-RS USES-RT) + "wbiu $rd,$rs,$rt,$bytecount" + (+ OP_COP3 rs rt rd FUNC10_WBIU bytecount) + (unimp wbiu) + ()) + +(dni pkrli "Packet Release Immediate" (MACH10 USES-RD USES-RS USES-RT) + "pkrli $rd,$rs,$rt,$bytecount" + (+ OP_COP2 rs rt rd FUNC10_PKRLI bytecount) + (unimp pkrli) + ()) + +(dni pkrlih "Packet Release Immediate and Hold" (MACH10 USES-RD USES-RS USES-RT) + "pkrlih $rd,$rs,$rt,$bytecount" + (+ OP_COP2 rs rt rd FUNC10_PKRLIH bytecount) + (unimp pkrlih) + ()) + +(dni pkrliu "Packet Release Immediate Unconditional" (MACH10 USES-RD USES-RS USES-RT) + "pkrliu $rd,$rs,$rt,$bytecount" + (+ OP_COP2 rs rt rd FUNC10_PKRLIU bytecount) + (unimp pkrliu) + ()) + +(dni pkrlic "Packet Release Immediate Continue" (MACH10 USES-RD USES-RS USES-RT) + "pkrlic $rd,$rs,$rt,$bytecount" + (+ OP_COP2 rs rt rd FUNC10_PKRLIC bytecount) + (unimp pkrlic) + ()) + +(dni pkrla "Packet Release Absolute" (MACH10 USES-RS USES-RT USES-RD) + "pkrla $rd,$rs,$rt" + (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_PKRLA) + (unimp pkrla) + ()) + +(dni pkrlau "Packet Release Absolute Unconditional" (MACH10 USES-RS USES-RT USES-RD) + "pkrlau $rd,$rs,$rt" + (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_PKRLAU) + (unimp pkrlau) + ()) + +(dni pkrlah "Packet Release Absolute and Hold" (MACH10 USES-RS USES-RT USES-RD) + "pkrlah $rd,$rs,$rt" + (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_PKRLAH) + (unimp pkrlah) + ()) + +(dni pkrlac "Packet Release Absolute Continue" (MACH10 USES-RS USES-RT USES-RD) + "pkrlac $rd,$rs,$rt" + (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_PKRLAC) + (unimp pkrlac) + ()) + +; Main Memory Access Instructions + +(dni lock "lock memory" (MACH10 USES-RD USES-RT) + "lock $rd,$rt" + (+ OP_COP3 (f-rs 0) rt rd (f-shamt 0) FUNC10_LOCK) + (unimp lock) + ()) + +(dni unlk "unlock memory" (MACH10 USES-RT USES-RD) + "unlk $rd,$rt" + (+ OP_COP3 (f-rs 0) rt rd (f-shamt 0) FUNC10_UNLK) + (unimp unlk) + ()) + +(dni swrd "Single Word Read" (MACH10 USES-RT USES-RD) + "swrd $rd,$rt" + (+ OP_COP3 (f-rs 0) rt rd (f-shamt 0) FUNC10_SWRD) + (unimp swrd) + ()) + +(dni swrdl "Single Word Read and Lock" (MACH10 USES-RT USES-RD) + "swrdl $rd,$rt" + (+ OP_COP3 (f-rs 0) rt rd (f-shamt 0) FUNC10_SWRDL) + (unimp swrdl) + ()) + +(dni swwr "Single Word Write" (MACH10 USES-RS USES-RT USES-RD) + "swwr $rd,$rs,$rt" + (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_SWWR) + (unimp swwr) + ()) + +(dni swwru "Single Word Write and Unlock" (MACH10 USES-RS USES-RT USES-RD) + "swwru $rd,$rs,$rt" + (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_SWWRU) + (unimp swwru) + ()) + +(dni dwrd "Double Word Read" (MACH10 EVEN-REG-NUM USES-RT USES-RD) + "dwrd $rd,$rt" + (+ OP_COP3 (f-rs 0) rt rd (f-shamt 0) FUNC10_DWRD) + (unimp dwrd) + ()) + +(dni dwrdl "Double Word Read and Lock" (MACH10 EVEN-REG-NUM USES-RT USES-RD) + "dwrdl $rd,$rt" + (+ OP_COP3 (f-rs 0) rt rd (f-shamt 0) FUNC10_DWRDL) + (unimp dwrdl) + ()) + +; CAM access instructions (IQ10) + +(dni cam36 "CAM Access in 36-bit Mode" (MACH10 USES-RT USES-RD) + "cam36 $rd,$rt,${cam-z},${cam-y}" + (+ OP_COP3 (f-rs 0) rt rd FUNC10_CAM36 cam-z cam-y) + (unimp cam36) + ()) + +(dni cam72 "CAM Access in 72-bit Mode" (MACH10 USES-RT USES-RD) + "cam72 $rd,$rt,${cam-y},${cam-z}" + (+ OP_COP3 (f-rs 0) rt rd FUNC10_CAM72 cam-z cam-y) + (unimp cam72) + ()) + +(dni cam144 "CAM Access in 144-bit Mode" (MACH10 USES-RT USES-RD) + "cam144 $rd,$rt,${cam-y},${cam-z}" + (+ OP_COP3 (f-rs 0) rt rd FUNC10_CAM144 cam-z cam-y) + (unimp cam144) + ()) + +(dni cam288 "CAM Access in 288-bit Mode" (MACH10 USES-RT USES-RD) + "cam288 $rd,$rt,${cam-y},${cam-z}" + (+ OP_COP3 (f-rs 0) rt rd FUNC10_CAM288 cam-z cam-y) + (unimp cam288) + ()) + +; Counter manager instructions (IQ10) + +(dni cm32and "Counter Manager And" (MACH10 USES-RS USES-RT USES-RD) + "cm32and $rd,$rs,$rt" + (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM32AND) + (unimp cm32and) + ()) + +(dni cm32andn "Counter Manager And With Inverse" (MACH10 USES-RS USES-RT USES-RD) + "cm32andn $rd,$rs,$rt" + (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM32ANDN) + (unimp cm32andn) + ()) + +(dni cm32or "Counter Manager Or" (MACH10 USES-RS USES-RT USES-RD) + "cm32or $rd,$rs,$rt" + (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM32OR) + (unimp cm32or) + ()) + +(dni cm32ra "Counter Manager 32-bit Rolling Add" (MACH10 USES-RS USES-RT USES-RD) + "cm32ra $rd,$rs,$rt" + (+ OP_COP3 rs rt rd (f-shamt 2) FUNC10_CM32RA) + (unimp cm32ra) + ()) + +(dni cm32rd "Counter Manager 32-bit Rolling Decrement" (MACH10 USES-RT USES-RD) + "cm32rd $rd,$rt" + (+ OP_COP3 (f-rs 0) rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM32RD) + (unimp cm32rd) + ()) + +(dni cm32ri "Counter Manager 32-bit Rolling Increment" (MACH10 USES-RT USES-RD) + "cm32ri $rd,$rt" + (+ OP_COP3 (f-rs 0) rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM32RI) + (unimp cm32ri) + ()) + +(dni cm32rs "Counter Manager 32-bit Rolling Subtract" (MACH10 USES-RS USES-RT USES-RD) + "cm32rs $rd,$rs,$rt" + (+ OP_COP3 rs rt rd (f-shamt 2) FUNC10_CM32RS) + (unimp cm32rs) + ()) + +(dni cm32sa "Counter Manager 32-bit Saturating Add" (MACH10 USES-RS USES-RT USES-RD) + "cm32sa $rd,$rs,$rt" + (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM32SA) + (unimp cm32sa) + ()) + +(dni cm32sd "Counter Manager 32-bit Saturating Decrement" (MACH10 USES-RT USES-RD) + "cm32sd $rd,$rt" + (+ OP_COP3 (f-rs 0) rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM32SD) + (unimp cm32sd) + ()) + +(dni cm32si "Counter Manager 32-bit Saturating Increment" (MACH10 USES-RT USES-RD) + "cm32si $rd,$rt" + (+ OP_COP3 (f-rs 0) rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM32SI) + (unimp cm32si) + ()) + +(dni cm32ss "Counter Manager 32-bit Saturating Subtract" (MACH10 USES-RS USES-RT USES-RD) + "cm32ss $rd,$rs,$rt" + (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM32SS) + (unimp cm32ss) + ()) + +(dni cm32xor "Counter Manager Xor" (MACH10 USES-RS USES-RT USES-RD) + "cm32xor $rd,$rs,$rt" + (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM32XOR) + (unimp cm32xor) + ()) + +(dni cm64clr "Counter Manager Clear" (MACH10 EVEN-REG-NUM USES-RT USES-RD) + "cm64clr $rd,$rt" + (+ OP_COP3 (f-rs 0) rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM64CLR) + (unimp cm64clr) + ()) + +(dni cm64ra "Counter Manager 64-bit Rolling Add" (MACH10 EVEN-REG-NUM USES-RS USES-RT USES-RD) + "cm64ra $rd,$rs,$rt" + (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM64RA) + (unimp cm64ra) + ()) + +(dni cm64rd "Counter Manager 64-bit Rolling Decrement" (MACH10 EVEN-REG-NUM USES-RT USES-RD) + "cm64rd $rd,$rt" + (+ OP_COP3 (f-rs 0) rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM64RD) + (unimp cm64rd) + ()) + +(dni cm64ri "Counter Manager 32-bit Rolling Increment" (MACH10 EVEN-REG-NUM USES-RT USES-RD) + "cm64ri $rd,$rt" + (+ OP_COP3 (f-rs 0) rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM64RI) + (unimp cm64ri) + ()) + +(dni cm64ria2 "Counter Manager 32/32 Rolling Increment/Add" (MACH10 EVEN-REG-NUM USES-RS USES-RT USES-RD) + "cm64ria2 $rd,$rs,$rt" + (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM64RIA2) + (unimp cm64ria2) + ()) + +(dni cm64rs "Counter Manager 64-bit Rolling Subtract" (MACH10 EVEN-REG-NUM USES-RS USES-RT USES-RD) + "cm64rs $rd,$rs,$rt" + (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM64RS) + (unimp cm64rs) + ()) + +(dni cm64sa "Counter Manager 64-bit Saturating Add" (MACH10 EVEN-REG-NUM USES-RS USES-RT USES-RD) + "cm64sa $rd,$rs,$rt" + (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM64SA) + (unimp cm64sa) + ()) + +(dni cm64sd "Counter Manager 64-bit Saturating Decrement" (MACH10 EVEN-REG-NUM USES-RT USES-RD) + "cm64sd $rd,$rt" + (+ OP_COP3 (f-rs 0) rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM64SD) + (unimp cm64sd) + ()) + +(dni cm64si "Counter Manager 64-bit Saturating Increment" (MACH10 EVEN-REG-NUM USES-RT USES-RD) + "cm64si $rd,$rt" + (+ OP_COP3 (f-rs 0) rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM64SI) + (unimp cm64si) + ()) + +(dni cm64sia2 "Counter Manager 32/32 Saturating Increment/Add" (MACH10 EVEN-REG-NUM USES-RS USES-RT USES-RD) + "cm64sia2 $rd,$rs,$rt" + (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM64SIA2) + (unimp cm64sia2) + ()) + +(dni cm64ss "Counter Manager 64-bit Saturating Subtract" (MACH10 EVEN-REG-NUM USES-RS USES-RT USES-RD) + "cm64ss $rd,$rs,$rt" + (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM64SS) + (unimp cm64ss) + ()) + +(dni cm128ria2 "Counter Manager 128-bit 64/64 Rolling Increment/Add" (MACH10 EVEN-REG-NUM USES-RS USES-RT USES-RD) + "cm128ria2 $rd,$rs,$rt" + (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM128RIA2) + (unimp cm128ria2) + ()) + +(dni cm128ria3 "Counter Manager 128-bit 32/32/64 Rolling Increment/Add" (MACH10 EVEN-REG-NUM USES-RS USES-RT USES-RD) + "cm128ria3 $rd,$rs,$rt,${cm-3z}" + (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM128RIA3 cm-3z) + (unimp cm128ria3) + ()) + +(dni cm128ria4 "Counter Manager 128-bit 32/32/32/32 Rolling Inc/Add" (MACH10 USES-RS USES-RT USES-RD) + "cm128ria4 $rd,$rs,$rt,${cm-4z}" + (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM128RIA4 cm-4z) + (unimp cm128ria4) + ()) + +(dni cm128sia2 "Counter Manager 128-bit 64/64 Saturating Inc/Add" (MACH10 EVEN-REG-NUM USES-RS USES-RT USES-RD) + "cm128sia2 $rd,$rs,$rt" + (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM128SIA2) + (unimp cm128sia2) + ()) + +(dni cm128sia3 "Counter Manager 128-bit 32/32/64 Saturating Inc/Add" (MACH10 EVEN-REG-NUM USES-RS USES-RT USES-RD) + "cm128sia3 $rd,$rs,$rt,${cm-3z}" + (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM128SIA3 cm-3z) + (unimp cm128sia3) + ()) + +(dni cm128sia4 "Counter Manager 128-bit 32/32/32/32 Saturating Inc/Add" (MACH10 USES-RS USES-RT USES-RD) + "cm128sia4 $rd,$rs,$rt,${cm-4z}" + (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM128SIA4 cm-4z) + (unimp cm128sia4) + ()) + +(dni cm128vsa "Counter Manager Continuous State Dual Leaky Token Bucket Policing" (MACH10 USES-RS USES-RT USES-RD) + "cm128vsa $rd,$rs,$rt" + (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM128VSA) + (unimp cm128vsa) + ()) + +; Coprocessor Data Movement Instructions + +; Note that we don't set the USES-RD or USES-RT attributes for many of the following +; instructions, as it's the COP register that's being specified. + +; ??? Is YIELD-INSN the right attribute for IQ10? The IQ2000 used the attribute to warn about +; yielding instructions in a delay slot, but that's not relevant in IQ10. What *is* relevant +; (and unique to IQ10) is instructions that yield if the destination register is accessed +; before the value is there, causing a yield. + +(dni cfc "copy from coprocessor control register" (MACH10 LOAD-DELAY USES-RD YIELD-INSN) + "cfc $rd,$rt" + (+ OP_COP3 (f-rs 0) rt rd (f-shamt 0) FUNC10_CFC) + (unimp cfc) + ()) + +(dni ctc "copy to coprocessor control register" (MACH10 USES-RS) + "ctc $rs,$rt" + (+ OP_COP3 rs rt (f-rd 0) (f-shamt 0) FUNC10_CTC) + (unimp ctc) + ()) + +; Macros + +(dnmi m-avail "Mark Header Buffer Available" (MACH10 NO-DIS) + "avail" + (emit avail (f-rd 0)) +) + +(dnmi m-cam36 "CAM Access in 36-bit Mode" (MACH10 USES-RT USES-RD NO-DIS) + "cam36 $rd,$rt,${cam-z}" + (emit cam36 rd rt cam-z (f-cam-y 0)) +) + +(dnmi m-cam72 "CAM Access in 72-bit Mode" (MACH10 USES-RT USES-RD NO-DIS) + "cam72 $rd,$rt,${cam-z}" + (emit cam72 rd rt cam-z (f-cam-y 0)) +) + +(dnmi m-cam144 "CAM Access in 144-bit Mode" (MACH10 USES-RT USES-RD NO-DIS) + "cam144 $rd,$rt,${cam-z}" + (emit cam144 rd rt cam-z (f-cam-y 0)) +) + +(dnmi m-cam288 "CAM Access in 288-bit Mode" (MACH10 USES-RT USES-RD NO-DIS) + "cam288 $rd,$rt,${cam-z}" + (emit cam288 rd rt cam-z (f-cam-y 0)) +) + +(dnmi m-cm32read "Counter Manager 32-bit Rolling Add R0" (MACH10 USES-RT USES-RD NO-DIS) + "cm32read $rd,$rt" + (emit cm32ra rd (f-rs 0) rt) +) + +(dnmi m-cm64read "Counter Manager 64-bit Rolling Add R0" (MACH10 USES-RT USES-RD NO-DIS) + "cm64read $rd,$rt" + (emit cm64ra rd (f-rs 0) rt) +) + +(dnmi m-cm32mlog "Counter Manager 32-bit or R0" (MACH10 USES-RS USES-RT NO-DIS) + "cm32mlog $rs,$rt" + (emit cm32or (f-rd 0) rs rt) +) + +(dnmi m-cm32and "Counter Manager And" (MACH10 USES-RS USES-RT USES-RD NO-DIS) + "cm32and $rs,$rt" + (emit cm32and (f-rd 0) rs rt) +) + +(dnmi m-cm32andn "Counter Manager And With Inverse" (MACH10 USES-RS USES-RT USES-RD NO-DIS) + "cm32andn $rs,$rt" + (emit cm32andn (f-rd 0) rs rt) +) + +(dnmi m-cm32or "Counter Manager Or" (MACH10 USES-RS USES-RT USES-RD NO-DIS) + "cm32or $rs,$rt" + (emit cm32or (f-rd 0) rs rt) +) + +(dnmi m-cm32ra "Counter Manager 32-bit Rolling Add" (MACH10 USES-RS USES-RT USES-RD NO-DIS) + "cm32ra $rs,$rt" + (emit cm32ra (f-rd 0) rs rt) +) + +(dnmi m-cm32rd "Counter Manager 32-bit Rolling Decrement" (MACH10 USES-RT USES-RD NO-DIS) + "cm32rd $rt" + (emit cm32rd (f-rd 0) rt) +) + +(dnmi m-cm32ri "Counter Manager 32-bit Rolling Increment" (MACH10 USES-RT USES-RD NO-DIS) + "cm32ri $rt" + (emit cm32ri (f-rd 0) rt) +) + +(dnmi m-cm32rs "Counter Manager 32-bit Rolling Subtract" (MACH10 USES-RS USES-RT USES-RD NO-DIS) + "cm32rs $rs,$rt" + (emit cm32rs (f-rd 0) rs rt) +) + +(dnmi m-cm32sa "Counter Manager 32-bit Saturating Add" (MACH10 USES-RS USES-RT USES-RD NO-DIS) + "cm32sa $rs,$rt" + (emit cm32sa (f-rd 0) rs rt) +) + +(dnmi m-cm32sd "Counter Manager 32-bit Saturating Decrement" (MACH10 USES-RT USES-RD NO-DIS) + "cm32sd $rt" + (emit cm32sd (f-rd 0) rt) +) + +(dnmi m-cm32si "Counter Manager 32-bit Saturating Increment" (MACH10 USES-RT USES-RD NO-DIS) + "cm32si $rt" + (emit cm32si (f-rd 0) rt) +) + +(dnmi m-cm32ss "Counter Manager 32-bit Saturating Subtract" (MACH10 USES-RS USES-RT USES-RD NO-DIS) + "cm32ss $rs,$rt" + (emit cm32ss (f-rd 0) rs rt) +) + +(dnmi m-cm32xor "Counter Manager Xor" (MACH10 USES-RS USES-RT USES-RD NO-DIS) + "cm32xor $rs,$rt" + (emit cm32xor (f-rd 0) rs rt) +) + +(dnmi m-cm64clr "Counter Manager Clear" (MACH10 USES-RT USES-RD NO-DIS) + "cm64clr $rt" + (emit cm64clr (f-rd 0) rt) +) + +(dnmi m-cm64ra "Counter Manager 64-bit Rolling Add" (MACH10 USES-RS USES-RT USES-RD NO-DIS) + "cm64ra $rs,$rt" + (emit cm64ra (f-rd 0) rs rt) +) + +(dnmi m-cm64rd "Counter Manager 64-bit Rolling Decrement" (MACH10 USES-RT USES-RD NO-DIS) + "cm64rd $rt" + (emit cm64rd (f-rd 0) rt) +) + +(dnmi m-cm64ri "Counter Manager 32-bit Rolling Increment" (MACH10 USES-RT USES-RD NO-DIS) + "cm64ri $rt" + (emit cm64ri (f-rd 0) rt) +) + +(dnmi m-cm64ria2 "Counter Manager 32/32 Rolling Increment/Add" (MACH10 USES-RS USES-RT USES-RD NO-DIS) + "cm64ria2 $rs,$rt" + (emit cm64ria2 (f-rd 0) rs rt) +) + +(dnmi m-cm64rs "Counter Manager 64-bit Rolling Subtract" (MACH10 USES-RS USES-RT USES-RD NO-DIS) + "cm64rs $rs,$rt" + (emit cm64rs (f-rd 0) rs rt) +) + +(dnmi m-cm64sa "Counter Manager 64-bit Saturating Add" (MACH10 USES-RS USES-RT USES-RD NO-DIS) + "cm64sa $rs,$rt" + (emit cm64sa (f-rd 0) rs rt) +) + +(dnmi m-cm64sd "Counter Manager 64-bit Saturating Decrement" (MACH10 USES-RT USES-RD NO-DIS) + "cm64sd $rt" + (emit cm64sd (f-rd 0) rt) +) + +(dnmi m-cm64si "Counter Manager 64-bit Saturating Increment" (MACH10 USES-RT USES-RD NO-DIS) + "cm64si $rt" + (emit cm64si (f-rd 0) rt) +) + +(dnmi m-cm64sia2 "Counter Manager 32/32 Saturating Increment/Add" (MACH10 USES-RS USES-RT USES-RD NO-DIS) + "cm64sia2 $rs,$rt" + (emit cm64sia2 (f-rd 0) rs rt) +) + +(dnmi m-cm64ss "Counter Manager 64-bit Saturating Subtract" (MACH10 USES-RS USES-RT USES-RD NO-DIS) + "cm64ss $rs,$rt" + (emit cm64ss (f-rd 0) rs rt) +) + +(dnmi m-cm128ria2 "Counter Manager 128-bit 64/64 Rolling Increment/Add" (MACH10 USES-RS USES-RT USES-RD NO-DIS) + "cm128ria2 $rs,$rt" + (emit cm128ria2 (f-rd 0) rs rt) +) + +(dnmi m-cm128ria3 "Counter Manager 128-bit 32/32/64 Rolling Increment/Add" (MACH10 USES-RS USES-RT USES-RD NO-DIS) + "cm128ria3 $rs,$rt,${cm-3z}" + (emit cm128ria3 (f-rd 0) rs rt cm-3z) +) + +(dnmi m-cm128ria4 "Counter Manager 128-bit 32/32/32/32 Rolling Inc/Add" (MACH10 USES-RS USES-RT USES-RD NO-DIS) + "cm128ria4 $rs,$rt,${cm-4z}" + (emit cm128ria4 (f-rd 0) rs rt cm-4z) +) + +(dnmi m-cm128sia2 "Counter Manager 128-bit 64/64 Saturating Inc/Add" (MACH10 USES-RS USES-RT USES-RD NO-DIS) + "cm128sia2 $rs,$rt" + (emit cm128sia2 (f-rd 0) rs rt) +) + +(dnmi m-cm128sia3 "Counter Manager 128-bit 32/32/64 Saturating Inc/Add" (MACH10 USES-RS USES-RT USES-RD NO-DIS) + "cm128sia3 $rs,$rt,${cm-3z}" + (emit cm128sia3 (f-rd 0) rs rt cm-3z) +) + +(dnmi m-cm128sia4 "Counter Manager 128-bit 32/32/32/32 Saturating Inc/Add" (MACH10 USES-RS USES-RT USES-RD NO-DIS) + "cm128sia4 $rs,$rt,${cm-4z}" + (emit cm128sia4 (f-rd 0) rs rt cm-4z) +) + +(dnmi m-cmphdr "Get a Complete Header" (MACH10 NO-DIS) + "cmphdr" + (emit cmphdr (f-rd 0)) +) + +(dnmi m-dbd "Deallocate a Data Buffer Pointer" (MACH10 USES-RD USES-RT NO-DIS) + "dbd $rd,$rt" + (emit dbd rd (f-rs 0) rt) +) + +(dnmi m2-dbd "Deallocate a Data Buffer Pointer" (MACH10 USES-RT NO-DIS) + "dbd $rt" + (emit dbd (f-rd 0) (f-rs 0) rt) +) + +(dnmi m-dpwt "DSTN_PORT Write" (MACH10 USES-RS NO-DIS) + "dpwt $rs" + (emit dpwt (f-rd 0) rs) +) + +(dnmi m-free "" (MACH10 USES-RS USES-RD NO-DIS) + "free $rs" + (emit free (f-rd 0) rs) +) + +;(dnmi m-jal "jump and link, implied r31" (MACH10 USES-RT NO-DIS) +; "jal $jmptarg" +; (emit jal (f-rt 31) jmptarg) +;) + +(dnmi m-lock "lock memory" (MACH10 USES-RT NO-DIS) + "lock $rt" + (emit lock (f-rd 0) rt) +) + +(dnmi m-pkrla "Packet Release Absolute" (MACH10 USES-RS USES-RT USES-RD NO-DIS) + "pkrla $rs,$rt" + (emit pkrla (f-rd 0) rs rt) +) + +(dnmi m-pkrlac "Packet Release Absolute Continue" (MACH10 USES-RS USES-RT USES-RD NO-DIS) + "pkrlac $rs,$rt" + (emit pkrlac (f-rd 0) rs rt) +) + +(dnmi m-pkrlah "Packet Release Absolute and Hold" (MACH10 USES-RS USES-RT USES-RD NO-DIS) + "pkrlah $rs,$rt" + (emit pkrlah (f-rd 0) rs rt) +) + +(dnmi m-pkrlau "Packet Release Absolute Unconditional" (MACH10 USES-RS USES-RT USES-RD NO-DIS) + "pkrlau $rs,$rt" + (emit pkrlau (f-rd 0) rs rt) +) + +(dnmi m-pkrli "Packet Release Immediate" (MACH10 USES-RD USES-RS USES-RT NO-DIS) + "pkrli $rs,$rt,$bytecount" + (emit pkrli (f-rd 0) rs rt bytecount) +) + +(dnmi m-pkrlic "Packet Release Immediate Continue" (MACH10 USES-RS USES-RT NO-DIS) + "pkrlic $rs,$rt,$bytecount" + (emit pkrlic (f-rd 0) rs rt bytecount) +) + +(dnmi m-pkrlih "Packet Release Immediate and Hold" (MACH10 USES-RD USES-RS USES-RT NO-DIS) + "pkrlih $rs,$rt,$bytecount" + (emit pkrlih (f-rd 0) rs rt bytecount) +) + +(dnmi m-pkrliu "Packet Release Immediate Unconditional" (MACH10 USES-RD USES-RS USES-RT NO-DIS) + "pkrliu $rs,$rt,$bytecount" + (emit pkrliu (f-rd 0) rs rt bytecount) +) + +(dnmi m-rba "Read Bytes Absolute" (MACH10 USES-RS USES-RT USES-RD NO-DIS) + "rba $rs,$rt" + (emit rba (f-rd 0) rs rt) +) + +(dnmi m-rbal "Read Bytes Absolute and Lock" (MACH10 USES-RS USES-RT USES-RD NO-DIS) + "rbal $rs,$rt" + (emit rbal (f-rd 0) rs rt) +) + +(dnmi m-rbar "Read Bytes Absolute and Release" (MACH10 USES-RS USES-RT USES-RD NO-DIS) + "rbar $rs,$rt" + (emit rbar (f-rd 0) rs rt) +) + +(dnmi m-rbi "Read Bytes Immediate" (MACH10 USES-RS USES-RT NO-DIS) + "rbi $rs,$rt,$bytecount" + (emit rbi (f-rd 0) rs rt bytecount) +) + +(dnmi m-rbil "Read Bytes Immediate and Lock" (MACH10 USES-RS USES-RT NO-DIS) + "rbil $rs,$rt,$bytecount" + (emit rbil (f-rd 0) rs rt bytecount) +) + +(dnmi m-rbir "Read Bytes Immediate and Release" (MACH10 USES-RS USES-RT NO-DIS) + "rbir $rs,$rt,$bytecount" + (emit rbir (f-rd 0) rs rt bytecount) +) + +(dnmi m-swwr "Single Word Write" (MACH10 USES-RS USES-RT USES-RD NO-DIS) + "swwr $rs,$rt" + (emit swwr (f-rd 0) rs rt) +) + +(dnmi m-swwru "Single Word Write and Unlock" (MACH10 USES-RS USES-RT USES-RD NO-DIS) + "swwru $rs,$rt" + (emit swwru (f-rd 0) rs rt) +) + +(dnmi m-tstod "Test Header Buffer Order Dependency" (MACH10 USES-RS USES-RD NO-DIS) + "tstod $rs" + (emit tstod (f-rd 0) rs) +) + +(dnmi m-unlk "" (MACH10 USES-RT USES-RD NO-DIS) + "unlk $rt" + (emit unlk (f-rd 0) rt) +) + +(dnmi m-wba "Write Bytes Absolute" (MACH10 USES-RS USES-RT USES-RD NO-DIS) + "wba $rs,$rt" + (emit wba (f-rd 0) rs rt) +) + +(dnmi m-wbac "Write Bytes Absolute Cacheable" (MACH10 USES-RS USES-RT USES-RD NO-DIS) + "wbac $rs,$rt" + (emit wbac (f-rd 0) rs rt) +) + +(dnmi m-wbau "Write Bytes Absolute and Unlock" (MACH10 USES-RS USES-RT USES-RD NO-DIS) + "wbau $rs,$rt" + (emit wbau (f-rd 0) rs rt) +) + +(dnmi m-wbi "Write Bytes Immediate" (MACH10 USES-RD USES-RS USES-RT NO-DIS) + "wbi $rs,$rt,$bytecount" + (emit wbi (f-rd 0) rs rt bytecount) +) + +(dnmi m-wbic "Write Bytes Immediate Cacheable" (MACH10 USES-RD USES-RS USES-RT NO-DIS) + "wbic $rs,$rt,$bytecount" + (emit wbic (f-rd 0) rs rt bytecount) +) + +(dnmi m-wbiu "Write Bytes Immediate" (MACH10 USES-RD USES-RS USES-RT NO-DIS) + "wbiu $rs,$rt,$bytecount" + (emit wbiu (f-rd 0) rs rt bytecount) +) + diff --git a/cpu/iq2000.cpu b/cpu/iq2000.cpu new file mode 100644 index 0000000..2a34859 --- /dev/null +++ b/cpu/iq2000.cpu @@ -0,0 +1,1199 @@ +; IQ2000/IQ10 Common CPU description. -*- Scheme -*- +; +; Copyright 2000, 2001, 2002 Free Software Foundation, Inc. +; +; Contributed by Red Hat Inc; developed under contract from Vitesse. +; +; This file is part of the GNU Binutils. +; +; This program is free software; you can redistribute it and/or modify +; it under the terms of the GNU General Public License as published by +; the Free Software Foundation; either version 2 of the License, or +; (at your option) any later version. +; +; This program is distributed in the hope that it will be useful, +; but WITHOUT ANY WARRANTY; without even the implied warranty of +; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +; GNU General Public License for more details. +; +; You should have received a copy of the GNU General Public License +; along with this program; if not, write to the Free Software +; Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +(include "simplify.inc") + +(define-arch + (name iq2000) + (comment "IQ2000 architecture") + (insn-lsb0? #t) + (machs iq2000 iq10) + (isas iq2000) +) + +(define-isa + (name iq2000) + (comment "Basic IQ2000 instruction set") + (default-insn-word-bitsize 32) + (default-insn-bitsize 32) + (base-insn-bitsize 32) + (decode-assist (31 30 29 28 27 26)) +) + +(define-cpu + (name iq2000bf) + (comment "IQ2000 family") + (endian big) + (word-bitsize 32) + (file-transform "") +) + +(define-cpu + (name iq10bf) + (comment "IQ10 coprocessor family") + (endian big) + (word-bitsize 32) + (file-transform "") + +) + +(define-mach + (name iq2000) + (comment "IQ2000 packet processing engine") + (cpu iq2000bf) + (isas iq2000) +) + +(define-mach + (name iq10) + (comment "IQ10 coprocessor") + (cpu iq10bf) + (isas iq2000) +) + +(define-model + (name iq2000) + (comment "IQ2000 microprocessor") + (mach iq2000) + (unit u-exec "Execution Unit" () + 1 1 ; issue done + () () () ()) +) + +(define-model + (name iq10) + (comment "IQ10 coprocessor") + (mach iq10) + (unit u-exec "Execution Unit" () + 1 1 ; issue done + () () () ()) +) + +; Macros to simplify MACH attribute specification. + +(define-pmacro MACH2000 (MACH iq2000)) +(define-pmacro MACH10 (MACH iq10)) + + +; Hardware elements. + +(define-hardware + (name h-pc) + (comment "program counter") + (attrs PC PROFILE (ISA iq2000)) + (type pc) + (get () (c-call USI "get_h_pc")) + (set (newval) (c-call VOID "set_h_pc" newval)) +) +; FIXME: it would be nice if the hardwired zero in R0 could be +; specified as a virtual hardware element, with one less register in +; the register file proper. + +(define-keyword + (name gr-names) + (print-name h-gr) + (values (r0 0) (%0 0) (r1 1) (%1 1) (r2 2) (%2 2) (r3 3) (%3 3) + (r4 4) (%4 4) (r5 5) (%5 5) (r6 6) (%6 6) (r7 7) (%7 7) + (r8 8) (%8 8) (r9 9) (%9 9) (r10 10) (%10 10) (r11 11) (%11 11) + (r12 12) (%12 12) (r13 13) (%13 13) (r14 14) (%14 14) (r15 15) (%15 15) + (r16 16) (%16 16) (r17 17) (%17 17) (r18 18) (%18 18) (r19 19) (%19 19) + (r20 20) (%20 20) (r21 21) (%21 21) (r22 22) (%22 22) (r23 23) (%23 23) + (r24 24) (%24 24) (r25 25) (%25 25) (r26 26) (%26 26) (r27 27) (%27 27) + (r28 28) (%28 28) (r29 29) (%29 29) (r30 30) (%30 30) (r31 31) (%31 31)) +) + +(define-hardware + (name h-gr) + (comment "General purpose registers") +; (attrs (ISA iq2000) CACHE-ADDR) + (type register SI (32)) + (indices extern-keyword gr-names) + (get (idx) + (cond SI + ((eq idx 0) (const 0)) + (else (raw-reg h-gr idx)))) + (set (idx newval) + (cond VOID + ((eq idx 0) (nop)) + (else (set (raw-reg h-gr idx) newval)))) +) + + +; Instruction fields. + +(dnf f-opcode "opcode field" () 31 6) +(dnf f-rs "register field Rs" () 25 5) +(dnf f-rt "register field Rt" () 20 5) +(dnf f-rd "register field Rd" () 15 5) +(dnf f-shamt "shift amount field" () 10 5) +(dnf f-cp-op "coprocessor op field" () 10 3) +(dnf f-cp-op-10 "coprocessor op field for CAM" () 10 5) +(dnf f-cp-grp "coprocessor group field" () 7 2) +(dnf f-func "function field" () 5 6) +(dnf f-imm "immediate field" () 15 16) + +(define-multi-ifield + (name f-rd-rs) + (comment "register Rd implied from Rs") + (attrs) + (mode UINT) + (subfields f-rd f-rs) + (insert (sequence () + (set (ifield f-rd) (ifield f-rd-rs)) + (set (ifield f-rs) (ifield f-rd-rs)) + )) + (extract (sequence () + (set (ifield f-rd-rs) (ifield f-rs)) + )) +) + +(define-multi-ifield + (name f-rd-rt) + (comment "register Rd implied from Rt") + (attrs) + (mode UINT) + (subfields f-rd f-rt) + (insert (sequence () + (set (ifield f-rd) (ifield f-rd-rt)) + (set (ifield f-rt) (ifield f-rd-rt)) + )) + (extract (sequence () + (set (ifield f-rd-rt) (ifield f-rt)) + )) +) + +(define-multi-ifield + (name f-rt-rs) + (comment "register Rt implied from Rs") + (attrs) + (mode UINT) + (subfields f-rt f-rs) + (insert (sequence () + (set (ifield f-rt) (ifield f-rt-rs)) + (set (ifield f-rs) (ifield f-rt-rs)) + )) + (extract (sequence () + (set (ifield f-rd-rs) (ifield f-rs)) + )) +) + +(df f-jtarg "jump target field" (ABS-ADDR) 15 16 UINT + ((value pc) (srl USI (and USI value #x03FFFF) 2)) + ((value pc) (or USI (and USI pc #xF0000000) (sll USI value 2)))) + +(df f-jtargq10 "iq10 jump target field" (ABS-ADDR) 20 21 UINT + ((value pc) (srl SI (and SI value #x7FFFFF) 2)) + ((value pc) (or SI (and SI pc #xF0000000) (sll SI value 2)))) + +(df f-offset "pc offset field" (PCREL-ADDR) 15 16 INT + ; Actually, this is relative to the address of the delay slot. + ((value pc) (sra SI (sub SI value pc) 2)) + ((value pc) (add SI (sll SI value 2) (add pc 4)))) + +; Instruction fields that scarcely appear in instructions. + +(dnf f-count "count field" () 15 7) +(dnf f-bytecount "byte count field" () 7 8) +(dnf f-index "index field" () 8 9) +(dnf f-mask "mask field" () 9 4) +(dnf f-maskq10 "iq10 mask field" () 10 5) +(dnf f-maskl "mask left field" () 4 5) +(dnf f-excode "execcode field" () 25 20) +(dnf f-rsrvd "reserved field" () 25 10) +(dnf f-10-11 "bits 10:0" () 10 11) +(dnf f-24-19 "bits 24:6" () 24 19) +(dnf f-5 "bit 5" () 5 1) +(dnf f-10 "bit 10" () 10 1) +(dnf f-25 "bit 25" () 25 1) +(dnf f-cam-z "cam global mask z" () 5 3) +(dnf f-cam-y "cam operation y" () 2 3) +(dnf f-cm-3func "CM 3 bit fn field" () 5 3) +(dnf f-cm-4func "CM 4 bit fn field" () 5 4) +(dnf f-cm-3z "CM 3Z field" () 1 2) +(dnf f-cm-4z "CM 4Z field" () 2 3) + + +; Enumerations. + +(define-normal-insn-enum + opcodes "primary opcodes" () OP_ f-opcode + (("SPECIAL" 0) ("REGIMM" 1) ("J" 2) ("JAL" 3) ("BEQ" 4) ("BNE" 5) ("BLEZ" 6) ("BGTZ" 7) + ("ADDI" 8) ("ADDIU" 9) ("SLTI" 10) ("SLTIU" 11) ("ANDI" 12) ("ORI" 13) ("XORI" 14) ("LUI" 15) + ("COP0" 16) ("COP1" 17) ("COP2" 18) ("COP3" 19) ("BEQL" 20) ("BNEL" 21) ("BLEZL" 22) ("BGTZL" 23) + ("BMB0" 24) ("BMB1" 25) ("BMB2" 26) ("BMB3" 27) ("BBI" 28) ("BBV" 29) ("BBIN" 30) ("BBVN" 31) + ("LB" 32) ("LH" 33) ("LW" 35) ("LBU" 36) ("LHU" 37) ("RAM" 39) + ("SB" 40) ("SH" 41) ("SW" 43) ("ANDOI" 44) ("BMB" 45) ("ORUI" 47) + ("LDW" 48) + ("SDW" 56) ("ANDOUI" 63)) +) + +(define-normal-insn-enum + q10_opcodes "iq10-only primary opcodes" () OP10_ f-opcode + (("BMB" 6) ("ORUI" 15) ("BMBL" 22) ("ANDOUI" 47) ("BBIL" 60) ("BBVL" 61) ("BBINL" 62) ("BBVNL" 63)) +) + +(define-normal-insn-enum + regimm-functions "branch sub-opcodes" () FUNC_ f-rt + (("BLTZ" 0) ("BGEZ" 1) ("BLTZL" 2) ("BGEZL" 3) ("BLEZ" 4) ("BGTZ" 5) ("BLEZL" 6) ("BGTZL" 7) + ("BRI" 8) ("BRV" 9) ("BCTX" 12) + ("BLTZAL" 16) ("BGEZAL" 17) ("BLTZALL" 18) ("BGEZALL" 19) ("BLEZAL" 20) ("BGTZAL" 21) ("BLEZALL" 22) ("BGTZALL" 23)) +) + +(define-normal-insn-enum + functions "function sub-opcodes" () FUNC_ f-func + (("SLL" 0) ("SLMV" 1) ("SRL" 2) ("SRA" 3) ("SLLV" 4) ("SRMV" 5) ("SRLV" 6) ("SRAV" 7) + ("JR" 8) ("JALR" 9) ("JCR" 10) ("SYSCALL" 12) ("BREAK" 13) ("SLEEP" 14) + ("ADD" 32) ("ADDU" 33) ("SUB" 34) ("SUBU" 35) ("AND" 36) ("OR" 37) ("XOR" 38) ("NOR" 39) + ("ADO16" 41) ("SLT" 42) ("SLTU" 43) ("MRGB" 45)) +) + +; iq10 special function sub-opcodes +(define-normal-insn-enum + q10s_functions "iq10-only special function sub-opcodes" () FUNC10_ f-func + (("YIELD" 14) ("CNT1S" 46)) +) + +; coprocessor opcodes in concert with f-cp-grp +(define-normal-insn-enum + cop_functions "iq10 function sub-opcodes" () FUNC10_ f-func + (("CFC" 0) ("LOCK" 1) ("CTC" 2) ("UNLK" 3) ("SWRD" 4) ("SWRDL" 5) ("SWWR" 6) ("SWWRU" 7) + ("RBA" 8) ("RBAL" 9) ("RBAR" 10) ("DWRD" 12) ("DWRDL" 13) + ("WBA" 16) ("WBAU" 17) ("WBAC" 18) ("CRC32" 20) ("CRC32B" 21) + ("MCID" 32) ("DBD" 33) ("DBA" 34) ("DPWT" 35) ("AVAIL" 36) ("FREE" 37) ("CHKHDR" 38) ("TSTOD" 39) + ("PKRLA" 40) ("PKRLAU" 41) ("PKRLAH" 42) ("PKRLAC" 43) ("CMPHDR" 44) + + ("CM64RS" 0) ("CM64RD" 1) ("CM64RI" 4) ("CM64CLR" 5) + ("CM64SS" 8) ("CM64SD" 9) ("CM64SI" 12) + ("CM64RA" 16) ("CM64RIA2" 20) ("CM128RIA2" 21) + ("CM64SA" 24) ("CM64SIA2" 28) ("CM128SIA2" 29) + ("CM32RS" 32) ("CM32RD" 33) ("CM32XOR" 34) ("CM32ANDN" 35) ("CM32RI" 36) ("CM128VSA" 38) + ("CM32SS" 40) ("CM32SD" 41) ("CM32OR" 42) ("CM32AND" 43) ("CM32SI" 44) + ("CM32RA" 48) + ("CM32SA" 56) ) +) + +; coprocessor opcodes in concert with f-cp-grp +(define-normal-insn-enum + cop_cm128_4functions "iq10 function sub-opcodes" () FUNC10_ f-cm-4func + (("CM128RIA3" 4) ("CM128SIA3" 6)) +) + +(define-normal-insn-enum + cop_cm128_3functions "iq10 function sub-opcodes" () FUNC10_ f-cm-3func + (("CM128RIA4" 6) ("CM128SIA4" 7)) +) + +(define-normal-insn-enum + cop2_functions "iq10 coprocessor sub-opcodes" () FUNC10_ f-cp-op + (("PKRLI" 0) ("PKRLIU" 1) ("PKRLIH" 2) ("PKRLIC" 3) ("RBIR" 1) ("RBI" 2) ("RBIL" 3) ("WBIC" 5) ("WBI" 6) ("WBIU" 7)) +) + +(define-normal-insn-enum + cop3_cam_functions "iq10 coprocessor cam sub-opcodes" () FUNC10_ f-cp-op-10 + (("CAM36" 16) ("CAM72" 17) ("CAM144" 18) ("CAM288" 19)) +) + + +; Attributes. + +(define-attr + (for insn) + (type boolean) + (name YIELD-INSN) + (comment "insn generates a context yield") +) + +(define-attr + (for insn) + (type boolean) + (name LOAD-DELAY) + (comment "insn has a load delay") +) + +(define-attr + (for insn) + (type boolean) + (name EVEN-REG-NUM) + (comment "insn requires an even numbered register in rt(2000) or rd(10)") +) + +(define-attr + (for insn) + (type boolean) + (name UNSUPPORTED) + (comment "insn is unsupported") +) + +(define-pmacro (define-reg-use-attr regfield) + (define-attr + (for insn) + (type boolean) + (name (.sym USES- (.upcase regfield))) + (comment ("insn accesses register operand " regfield)))) + +(define-reg-use-attr rd) +(define-reg-use-attr rs) +(define-reg-use-attr rt) +(define-reg-use-attr r31) + + +; Operands. + +(dnop rs "register Rs" () h-gr f-rs) +(dnop rt "register Rt" () h-gr f-rt) +(dnop rd "register Rd" () h-gr f-rd) +(dnop rd-rs "register Rd from Rs" () h-gr f-rd-rs) +(dnop rd-rt "register Rd from Rt" () h-gr f-rd-rt) +(dnop rt-rs "register Rt from Rs" () h-gr f-rt-rs) +(dnop shamt "shift amount" () h-uint f-shamt) +(define-operand (name imm) (comment "immediate") (attrs) + (type h-uint) (index f-imm) (handlers (parse "imm"))) +(dnop offset "pc-relative offset" () h-iaddr f-offset) +(dnop baseoff "base register offset" () h-iaddr f-imm) +(dnop jmptarg "jump target" () h-iaddr f-jtarg) +(dnop mask "mask" () h-uint f-mask) +(dnop maskq10 "iq10 mask" () h-uint f-maskq10) +(dnop maskl "mask left" () h-uint f-maskl) +(dnop count "count" () h-uint f-count) +(dnop index "index" () h-uint f-index) +(dnop execode "execcode" () h-uint f-excode) +(dnop bytecount "byte count" () h-uint f-bytecount) +(dnop cam-y "cam global opn y" () h-uint f-cam-y) +(dnop cam-z "cam global mask z" () h-uint f-cam-z) +(dnop cm-3func "CM 3 bit fn field" () h-uint f-cm-3func) +(dnop cm-4func "CM 4 bit fn field" () h-uint f-cm-4func) +(dnop cm-3z "CM 3 bit Z field" () h-uint f-cm-3z) +(dnop cm-4z "CM 4 bit Z field" () h-uint f-cm-4z) + +; Aliases for the rs and rt operands. This just makes the load/store +; insns easier to compare with the instruction set documentation. + +(dnop base "base register" () h-gr f-rs) +(dnop maskr "mask right" () h-uint f-rs) +(dnop bitnum "bit number" () h-uint f-rt) + +; For high(foo). +(define-operand + (name hi16) + (comment "high 16 bit immediate") + (attrs) + (type h-uint) + (index f-imm) + (handlers (parse "hi16")) +) + +; For low(foo). +(define-operand + (name lo16) + (comment "16 bit signed immediate, for low") + (attrs) + (type h-uint) + (index f-imm) + (handlers (parse "lo16")) +) + +; For negated imm. +(define-operand + (name mlo16) + (comment "negated 16 bit signed immediate") + (attrs) + (type h-uint) + (index f-imm) + (handlers (parse "mlo16")) +) + +; For iq10 jmps +; In the future, we'll want the j & jal to use the 21 bit target, with +; the upper five bits shifted up. For now, don't use this. +(define-operand + (name jmptargq10) + (comment "iq10 21-bit jump offset") + (attrs) + (type h-iaddr) + (index f-jtargq10) + (handlers (parse "jtargq10")) +) + + +; Instructions. + +; A pmacro for use in semantic bodies of unimplemented insns. +(define-pmacro (unimp mnemonic) (nop)) + +(define-pmacro (bitset? value bit-num) + (and value (sll 1 bit-num))) + +(define-pmacro (bitclear? value bit-num) + (not (bitset? value bit-num))) + +; Arithmetic/logic instructions. + +(dni add2 "add registers" (ALIAS NO-DIS USES-RD USES-RS USES-RT) + "add ${rd-rs},$rt" + (+ OP_SPECIAL rt rd-rs (f-shamt 0) FUNC_ADD) + (set rd-rs (add rt rd-rs)) + ()) + +(dni add "add registers" (USES-RD USES-RS USES-RT) + "add $rd,$rs,$rt" + (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_ADD) + (set rd (add rs rt)) + ()) + + +(dni addi2 "add immediate" (ALIAS NO-DIS USES-RS USES-RT) + "addi ${rt-rs},$lo16" + (+ OP_ADDI rt-rs lo16) + (set rt-rs (add rt-rs (ext SI (trunc HI lo16)))) + ()) + +(dni addi "add immediate" (USES-RS USES-RT) + "addi $rt,$rs,$lo16" + (+ OP_ADDI rs rt lo16) + (set rt (add rs (ext SI (trunc HI lo16)))) + ()) + +(dni addiu2 "add immediate unsigned" (ALIAS NO-DIS USES-RS USES-RT) + "addiu ${rt-rs},$lo16" + (+ OP_ADDIU rt-rs lo16) + (set rt-rs (add rt-rs (ext SI (trunc HI lo16)))) + ()) + +(dni addiu "add immediate unsigned" (USES-RS USES-RT) + "addiu $rt,$rs,$lo16" + (+ OP_ADDIU rs rt lo16) + (set rt (add rs (ext SI (trunc HI lo16)))) + ()) + +(dni addu2 "add unsigned" (ALIAS NO-DIS USES-RD USES-RS USES-RT) + "addu ${rd-rs},$rt" + (+ OP_SPECIAL rd-rs rt (f-shamt 0) FUNC_ADDU) + (set rd-rs (add rd-rs rt)) + ()) + +(dni addu "add unsigned" (USES-RD USES-RS USES-RT) + "addu $rd,$rs,$rt" + (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_ADDU) + (set rd (add rs rt)) + ()) + +(dni ado162 "add 16, ones complement" (ALIAS NO-DIS USES-RD USES-RS USES-RT) + "ado16 ${rd-rs},$rt" + (+ OP_SPECIAL rd-rs rt (f-shamt 0) FUNC_ADO16) + (sequence ((HI high) (HI low)) + (set low (add HI (and HI rd-rs #xFFFF) (and HI rt #xFFFF))) + (set high (add HI (srl rd-rs 16) (srl rt 16))) + (set rd-rs (or SI (sll SI high 16) low))) + ()) + +(dni ado16 "add 16, ones complement" (USES-RD USES-RS USES-RT) + "ado16 $rd,$rs,$rt" + (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_ADO16) + (sequence ((HI high) (HI low)) + (set low (add HI (and HI rs #xFFFF) (and HI rt #xFFFF))) + (set high (add HI (srl rs 16) (srl rt 16))) + (set rd (or SI (sll SI high 16) low))) + ()) + +(dni and2 "and register" (ALIAS NO-DIS USES-RD USES-RS USES-RT) + "and ${rd-rs},$rt" + (+ OP_SPECIAL rd-rs rt (f-shamt 0) FUNC_AND) + (set rd-rs (and rd-rs rt)) + ()) + +(dni and "and register" (USES-RD USES-RS USES-RT) + "and $rd,$rs,$rt" + (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_AND) + (set rd (and rs rt)) + ()) + +(dni andi2 "and immediate" (ALIAS NO-DIS USES-RS USES-RT) + "andi ${rt-rs},$lo16" + (+ OP_ANDI rt-rs lo16) + (set rt-rs (and rt-rs (zext SI lo16))) + ()) + +(dni andi "and immediate" (USES-RS USES-RT) + "andi $rt,$rs,$lo16" + (+ OP_ANDI rs rt lo16) + (set rt (and rs (zext SI lo16))) + ()) + +(dni andoi2 "and ones immediate" (ALIAS NO-DIS USES-RS USES-RT) + "andoi ${rt-rs},$lo16" + (+ OP_ANDOI rt-rs lo16) + (set rt-rs (and rt-rs (or #xFFFF0000 (ext SI (trunc HI lo16))))) + ()) + +(dni andoi "and ones immediate" (USES-RS USES-RT) + "andoi $rt,$rs,$lo16" + (+ OP_ANDOI rs rt lo16) + (set rt (and rs (or #xFFFF0000 (ext SI (trunc HI lo16))))) + ()) + +(dni nor2 "nor" (ALIAS NO-DIS USES-RD USES-RS USES-RT) + "nor ${rd-rs},$rt" + (+ OP_SPECIAL rd-rs rt (f-shamt 0) FUNC_NOR) + (set rd-rs (inv (or rd-rs rt))) + ()) + +(dni nor "nor" (USES-RD USES-RS USES-RT) + "nor $rd,$rs,$rt" + (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_NOR) + (set rd (inv (or rs rt))) + ()) + +(dni or2 "or" (ALIAS NO-DIS USES-RD USES-RS USES-RT) + "or ${rd-rs},$rt" + (+ OP_SPECIAL rd-rs rt (f-shamt 0) FUNC_OR) + (set rd-rs (or rd-rs rt)) + ()) + +(dni or "or" (USES-RD USES-RS USES-RT) + "or $rd,$rs,$rt" + (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_OR) + (set rd (or rs rt)) + ()) + +(dni ori2 "or immediate" (ALIAS NO-DIS USES-RS USES-RT) + "ori ${rt-rs},$lo16" + (+ OP_ORI rt-rs lo16) + (set rt-rs (or rt-rs (zext SI lo16))) + ()) + +(dni ori "or immediate" (USES-RS USES-RT) + "ori $rt,$rs,$lo16" + (+ OP_ORI rs rt lo16) + (set rt (or rs (zext SI lo16))) + ()) + +(dni ram "rotate and mask" (USES-RD USES-RT) + "ram $rd,$rt,$shamt,$maskl,$maskr" + (+ OP_RAM maskr rt rd shamt (f-5 0) maskl) + (sequence () + (set rd (ror rt shamt)) + (set rd (and rd (srl #xFFFFFFFF maskl))) + (set rd (and rd (sll #xFFFFFFFF maskr)))) + ()) + +(dni sll "shift left logical" (USES-RD USES-RT) + "sll $rd,$rt,$shamt" + (+ OP_SPECIAL (f-rs 0) rt rd shamt (f-func 0)) + (set rd (sll rt shamt)) + ()) + +(dni sllv2 "shift left logical variable" (ALIAS NO-DIS USES-RD USES-RS USES-RT) + "sllv ${rd-rt},$rs" + (+ OP_SPECIAL rs rd-rt (f-shamt 0) FUNC_SLLV) + (set rd-rt (sll rd-rt (and rs #x1F))) + ()) + +(dni sllv "shift left logical variable" (USES-RD USES-RS USES-RT) + "sllv $rd,$rt,$rs" + (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_SLLV) + (set rd (sll rt (and rs #x1F))) + ()) + +(dni slmv2 "shift left and mask variable" (ALIAS NO-DIS USES-RD USES-RS USES-RT) + "slmv ${rd-rt},$rs,$shamt" + (+ OP_SPECIAL rs rd-rt shamt FUNC_SLMV) + (set rd-rt (and (sll rd-rt shamt) (srl #xFFFFFFFF rs))) + ()) + +(dni slmv "shift left and mask variable" (USES-RD USES-RS USES-RT) + "slmv $rd,$rt,$rs,$shamt" + (+ OP_SPECIAL rs rt rd shamt FUNC_SLMV) + (set rd (and (sll rt shamt) (srl #xFFFFFFFF rs))) + ()) + +(dni slt2 "set if less than" (ALIAS NO-DIS USES-RD USES-RS USES-RT) + "slt ${rd-rs},$rt" + (+ OP_SPECIAL rt rd-rs (f-shamt 0) FUNC_SLT) + (if (lt rd-rs rt) + (set rd-rs 1) + (set rd-rs 0)) + ()) + +(dni slt "set if less than" (USES-RD USES-RS USES-RT) + "slt $rd,$rs,$rt" + (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_SLT) + (if (lt rs rt) + (set rd 1) + (set rd 0)) + ()) + +(dni slti2 "set if less than immediate" (ALIAS NO-DIS USES-RS USES-RT) + "slti ${rt-rs},$imm" + (+ OP_SLTI rt-rs imm) + (if (lt rt-rs (ext SI (trunc HI imm))) + (set rt-rs 1) + (set rt-rs 0)) + ()) + +(dni slti "set if less than immediate" (USES-RS USES-RT) + "slti $rt,$rs,$imm" + (+ OP_SLTI rs rt imm) + (if (lt rs (ext SI (trunc HI imm))) + (set rt 1) + (set rt 0)) + ()) + +(dni sltiu2 "set if less than immediate unsigned" (ALIAS NO-DIS USES-RS USES-RT) + "sltiu ${rt-rs},$imm" + (+ OP_SLTIU rt-rs imm) + (if (ltu rt-rs (ext SI (trunc HI imm))) + (set rt-rs 1) + (set rt-rs 0)) + ()) + +(dni sltiu "set if less than immediate unsigned" (USES-RS USES-RT) + "sltiu $rt,$rs,$imm" + (+ OP_SLTIU rs rt imm) + (if (ltu rs (ext SI (trunc HI imm))) + (set rt 1) + (set rt 0)) + ()) + +(dni sltu2 "set if less than unsigned" (ALIAS NO-DIS USES-RD USES-RS USES-RT) + "sltu ${rd-rs},$rt" + (+ OP_SPECIAL rd-rs rt (f-shamt 0) FUNC_SLTU) + (if (ltu rd-rs rt) + (set rd-rs 1) + (set rd-rs 0)) + ()) + +(dni sltu "set if less than unsigned" (USES-RD USES-RS USES-RT) + "sltu $rd,$rs,$rt" + (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_SLTU) + (if (ltu rs rt) + (set rd 1) + (set rd 0)) + ()) + +(dni sra2 "shift right arithmetic" (ALIAS NO-DIS USES-RD USES-RT) + "sra ${rd-rt},$shamt" + (+ OP_SPECIAL (f-rs 0) rd-rt shamt FUNC_SRA) + (set rd-rt (sra rd-rt shamt)) + ()) + +(dni sra "shift right arithmetic" (USES-RD USES-RT) + "sra $rd,$rt,$shamt" + (+ OP_SPECIAL (f-rs 0) rt rd shamt FUNC_SRA) + (set rd (sra rt shamt)) + ()) + +(dni srav2 "shift right arithmetic variable" (ALIAS NO-DIS USES-RD USES-RS USES-RT) + "srav ${rd-rt},$rs" + (+ OP_SPECIAL rs rd-rt (f-shamt 0) FUNC_SRAV) + (set rd-rt (sra rd-rt (and rs #x1F))) + ()) + +(dni srav "shift right arithmetic variable" (USES-RD USES-RS USES-RT) + "srav $rd,$rt,$rs" + (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_SRAV) + (set rd (sra rt (and rs #x1F))) + ()) + +(dni srl "shift right logical" (USES-RD USES-RT) + "srl $rd,$rt,$shamt" + (+ OP_SPECIAL (f-rs 0) rt rd shamt FUNC_SRL) + (set rd (srl rt shamt)) + ()) + +(dni srlv2 "shift right logical variable" (ALIAS NO-DIS USES-RD USES-RS USES-RT) + "srlv ${rd-rt},$rs" + (+ OP_SPECIAL rs rd-rt (f-shamt 0) FUNC_SRLV) + (set rd-rt (srl rd-rt (and rs #x1F))) + ()) + +(dni srlv "shift right logical variable" (USES-RD USES-RS USES-RT) + "srlv $rd,$rt,$rs" + (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_SRLV) + (set rd (srl rt (and rs #x1F))) + ()) + +(dni srmv2 "shift right and mask variable" (ALIAS NO-DIS USES-RD USES-RS USES-RT) + "srmv ${rd-rt},$rs,$shamt" + (+ OP_SPECIAL rs rd-rt shamt FUNC_SRMV) + (set rd-rt (and (srl rd-rt shamt) (sll #xFFFFFFFF rs))) + ()) + +(dni srmv "shift right and mask variable" (USES-RD USES-RS USES-RT) + "srmv $rd,$rt,$rs,$shamt" + (+ OP_SPECIAL rs rt rd shamt FUNC_SRMV) + (set rd (and (srl rt shamt) (sll #xFFFFFFFF rs))) + ()) + +(dni sub2 "subtract" (ALIAS NO-DIS USES-RD USES-RS USES-RT) + "sub ${rd-rs},$rt" + (+ OP_SPECIAL rt rd-rs (f-shamt 0) FUNC_SUB) + (set rd-rs (sub rd-rs rt)) + ()) + +(dni sub "subtract" (USES-RD USES-RS USES-RT) + "sub $rd,$rs,$rt" + (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_SUB) + (set rd (sub rs rt)) + ()) + +(dni subu2 "subtract unsigned" (ALIAS NO-DIS USES-RD USES-RS USES-RT) + "subu ${rd-rs},$rt" + (+ OP_SPECIAL rt rd-rs (f-shamt 0) FUNC_SUBU) + (set rd-rs (sub rd-rs rt)) + ()) + +(dni subu "subtract unsigned" (USES-RD USES-RS USES-RT) + "subu $rd,$rs,$rt" + (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_SUBU) + (set rd (sub rs rt)) + ()) + +(dni xor2 "exclusive or" (ALIAS NO-DIS USES-RD USES-RS USES-RT) + "xor ${rd-rs},$rt" + (+ OP_SPECIAL rt rd-rs (f-shamt 0) FUNC_XOR) + (set rd-rs (xor rd-rs rt)) + ()) + +(dni xor "exclusive or" (USES-RD USES-RS USES-RT) + "xor $rd,$rs,$rt" + (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_XOR) + (set rd (xor rs rt)) + ()) + +(dni xori2 "exclusive or immediate" (ALIAS NO-DIS USES-RS USES-RT) + "xori ${rt-rs},$lo16" + (+ OP_XORI rt-rs lo16) + (set rt-rs (xor rt-rs (zext SI lo16))) + ()) + +(dni xori "exclusive or immediate" (USES-RS USES-RT) + "xori $rt,$rs,$lo16" + (+ OP_XORI rs rt lo16) + (set rt (xor rs (zext SI lo16))) + ()) + + +; Branch instructions. + +(dni bbi "branch bit immediate" (USES-RS) + "bbi $rs($bitnum),$offset" + (+ OP_BBI rs bitnum offset) + (if (bitset? rs bitnum) + (delay 1 (set pc offset))) + ()) + +(dni bbin "branch bit immediate negated" (USES-RS) + "bbin $rs($bitnum),$offset" + (+ OP_BBIN rs bitnum offset) + (if (bitclear? rs bitnum) + (delay 1 (set pc offset))) + ()) + +(dni bbv "branch bit variable" (USES-RS USES-RT) + "bbv $rs,$rt,$offset" + (+ OP_BBV rs rt offset) + (if (bitset? rs (and rt #x1F)) + (delay 1 (set pc offset))) + ()) + +(dni bbvn "branch bit variable negated" (USES-RS USES-RT) + "bbvn $rs,$rt,$offset" + (+ OP_BBVN rs rt offset) + (if (bitclear? rs (and rt #x1F)) + (delay 1 (set pc offset))) + ()) + +(dni beq "branch if equal" (USES-RS USES-RT) + "beq $rs,$rt,$offset" + (+ OP_BEQ rs rt offset) + (if (eq rs rt) + (delay 1 (set pc offset))) + ()) + +(dni beql "branch if equal likely" (USES-RS USES-RT) + "beql $rs,$rt,$offset" + (+ OP_BEQL rs rt offset) + (if (eq rs rt) + (delay 1 (set pc offset)) + (skip 1)) + ()) + +(dni bgez "branch if greater than or equal to zero" (USES-RS) + "bgez $rs,$offset" + (+ OP_REGIMM rs FUNC_BGEZ offset) + (if (ge rs 0) + (delay 1 (set pc offset))) + ()) + +(dni bgezal "branch if greater than or equal to zero and link" (USES-RS USES-R31) + "bgezal $rs,$offset" + (+ OP_REGIMM rs FUNC_BGEZAL offset) + (if (ge rs 0) + (sequence () + (set (reg h-gr 31) (add pc 8)) + (delay 1 (set pc offset)))) + ()) + +(dni bgezall + "branch if greater than equal to zero and link likely" (USES-RS USES-R31) + "bgezall $rs,$offset" + (+ OP_REGIMM rs FUNC_BGEZALL offset) + (if (ge rs 0) + (sequence () + (set (reg h-gr 31) (add pc 8)) + (delay 1 (set pc offset))) + (skip 1)) + ()) + +(dni bgezl "branch if greater or equal to zero likely" (USES-RS) + "bgezl $rs,$offset" + (+ OP_REGIMM rs FUNC_BGEZL offset) + (if (ge rs 0) + (delay 1 (set pc offset)) + (skip 1)) + ()) + +(dni bltz "branch if less than zero" (USES-RS) + "bltz $rs,$offset" + (+ OP_REGIMM rs FUNC_BLTZ offset) + (if (lt rs 0) + (delay 1 (set pc offset))) + ()) + +(dni bltzl "branch if less than zero likely" (USES-RS) + "bltzl $rs,$offset" + (+ OP_REGIMM rs FUNC_BLTZL offset) + (if (lt rs 0) + (delay 1 (set pc offset)) + (skip 1)) + ()) + +(dni bltzal "branch if less than zero and link" (USES-RS USES-R31) + "bltzal $rs,$offset" + (+ OP_REGIMM rs FUNC_BLTZAL offset) + (if (lt rs 0) + (sequence () + (set (reg h-gr 31) (add pc 8)) + (delay 1 (set pc offset)))) + ()) + +(dni bltzall "branch if less than zero and link likely" (USES-RS USES-R31) + "bltzall $rs,$offset" + (+ OP_REGIMM rs FUNC_BLTZALL offset) + (if (lt rs 0) + (sequence () + (set (reg h-gr 31) (add pc 8)) + (delay 1 (set pc offset))) + (skip 1)) + ()) + +(dni bmb0 "branch if matching byte-lane 0" (USES-RS USES-RT) + "bmb0 $rs,$rt,$offset" + (+ OP_BMB0 rs rt offset) + (if (eq (and rs #xFF) (and rt #xFF)) + (delay 1 (set pc offset))) + ()) + +(dni bmb1 "branch if matching byte-lane 1" (USES-RS USES-RT) + "bmb1 $rs,$rt,$offset" + (+ OP_BMB1 rs rt offset) + (if (eq (and rs #xFF00) (and rt #xFF00)) + (delay 1 (set pc offset))) + ()) + +(dni bmb2 "branch if matching byte-lane 2" (USES-RS USES-RT) + "bmb2 $rs,$rt,$offset" + (+ OP_BMB2 rs rt offset) + (if (eq (and rs #xFF0000) (and rt #xFF0000)) + (delay 1 (set pc offset))) + ()) + +(dni bmb3 "branch if matching byte-lane 3" (USES-RS USES-RT) + "bmb3 $rs,$rt,$offset" + (+ OP_BMB3 rs rt offset) + (if (eq (and rs #xFF000000) (and rt #xFF000000)) + (delay 1 (set pc offset))) + ()) + +(dni bne "branch if not equal" (USES-RS USES-RT) + "bne $rs,$rt,$offset" + (+ OP_BNE rs rt offset) + (if (ne rs rt) + (delay 1 (set pc offset))) + ()) + +(dni bnel "branch if not equal likely" (USES-RS USES-RT) + "bnel $rs,$rt,$offset" + (+ OP_BNEL rs rt offset) + (if (ne rs rt) + (delay 1 (set pc offset)) + (skip 1)) + ()) + + + + +; Jump instructions. +; Might as well jump! + +(dni jalr "jump and link register" (USES-RD USES-RS) + "jalr $rd,$rs" + (+ OP_SPECIAL rs (f-rt 0) rd (f-shamt 0) FUNC_JALR) + (delay 1 + (sequence () + (set rd (add pc 8)) + (set pc rs))) + ()) + +(dni jr "jump register" (USES-RS) + "jr $rs" + (+ OP_SPECIAL rs (f-rt 0) (f-rd 0) (f-shamt 0) FUNC_JR) + (delay 1 (set pc rs)) + ()) + + +; Load instructions. + +(dni lb "load byte" (LOAD-DELAY USES-RS USES-RT) + "lb $rt,$lo16($base)" + (+ OP_LB base rt lo16) + (set rt (ext WI (mem QI (add base (ext SI (trunc HI lo16)))))) +; (sequence ((SI addr) (SI word)) +; (set addr (add base lo16)) +; (set word (mem SI (and addr (inv 3)))) +; (set word (srl word (sll (and addr 2) 3))) +; (set rt (ext SI word))) + ()) + +(dni lbu "load byte unsigned" (LOAD-DELAY USES-RS USES-RT) + "lbu $rt,$lo16($base)" + (+ OP_LBU base rt lo16) + (set rt (zext WI (mem QI (add base (ext SI (trunc HI lo16)))))) +; (sequence ((SI addr) (SI word)) +; (set addr (add base lo16)) +; (set word (mem SI (and addr (inv 3)))) +; (set rt (srl word (sll (and addr 2) 3)))) + ()) + +(dni lh "load half word" (LOAD-DELAY USES-RS USES-RT) + "lh $rt,$lo16($base)" + (+ OP_LH base rt lo16) + (set rt (ext WI (mem HI (add base (ext SI (trunc HI lo16)))))) +; (sequence ((SI addr) (HI word)) +; (set addr (add base lo16)) +; (set word (mem SI (and addr (inv 3)))) +; (set word (srl word (sll (and addr 1) 4))) +; (set rt (ext SI word))) + ()) + +(dni lhu "load half word unsigned" (LOAD-DELAY USES-RS USES-RT) + "lhu $rt,$lo16($base)" + (+ OP_LHU base rt lo16) + (set rt (zext WI (mem HI (add base (ext SI (trunc HI lo16)))))) +; (sequence ((SI addr) (SI word)) +; (set addr (add base lo16)) +; (set word (mem SI (and addr (inv 3)))) +; (set rt (srl word (sll (and addr 1) 4)))) + ()) + +(dni lui "load upper immediate" (USES-RT) + "lui $rt,$hi16" + (+ OP_LUI (f-rs 0) rt hi16) + (set rt (sll hi16 16)) + ()) + +(dni lw "load word" (LOAD-DELAY USES-RS USES-RT) + "lw $rt,$lo16($base)" + (+ OP_LW base rt lo16) + (set rt (mem SI (add base (ext SI (trunc HI lo16))))) + ()) + + +; Store instructions. + +(dni sb "store byte" (USES-RS USES-RT) + "sb $rt,$lo16($base)" + (+ OP_SB base rt lo16) + (set (mem QI (add base (ext SI (trunc HI lo16)))) (and QI rt #xFF)) + ()) + +(dni sh "store half word" (USES-RS USES-RT) + "sh $rt,$lo16($base)" + (+ OP_SH base rt lo16) + (set (mem HI (add base (ext SI (trunc HI lo16)))) (and HI rt #xFFFF)) + ()) + +(dni sw "store word" (USES-RS USES-RT) + "sw $rt,$lo16($base)" + (+ OP_SW base rt lo16) + (set (mem SI (add base (ext SI (trunc HI lo16)))) rt) + ()) + + +; Special instructions for simulation/debugging +(dni break "breakpoint" () + "break" + (+ OP_SPECIAL (f-rs 0) (f-rt 0) (f-rd 0) (f-shamt 0) FUNC_BREAK) + (c-call VOID "do_break" pc) + ()) + +(dni syscall "system call" (YIELD-INSN) + "syscall" + (+ OP_SPECIAL execode (f-func 12)) + (c-call VOID "do_syscall") + ()) + +; Macro instructions, common to iq10 & iq2000 + +(dnmi nop "nop" () + "nop" + (emit sll (rd 0) (rt 0) (shamt 0)) +) + +(dnmi li "load immediate" (USES-RS NO-DIS) + "li $rs,$imm" + (emit ori (rt 0) rs imm) +) + +(dnmi move "move" (USES-RD USES-RT NO-DIS) + "move $rd,$rt" + (emit or rd (rs 0) rt) +) + +(dnmi lb-base-0 "load byte - implied base 0" (USES-RT NO-DIS) + "lb $rt,$lo16" + (emit lb rt lo16 (base 0)) +) + +(dnmi lbu-base-0 "load byte unsigned - implied base 0" (USES-RT NO-DIS) + "lbu $rt,$lo16" + (emit lbu rt lo16 (base 0)) +) + +(dnmi lh-base-0 "load half - implied base 0" (USES-RT NO-DIS) + "lh $rt,$lo16" + (emit lh rt lo16 (base 0)) +) + +(dnmi lw-base-0 "load word - implied base 0" (USES-RT NO-DIS) + "lw $rt,$lo16" + (emit lw rt lo16 (base 0)) +) + +(dnmi m-add "add immediate" (USES-RS USES-RT NO-DIS) + "add $rt,$rs,$lo16" + (emit addi rt rs lo16)) + +(dnmi m-addu "add immediate unsigned" (USES-RS USES-RT NO-DIS) + "addu $rt,$rs,$lo16" + (emit addiu rt rs lo16) +) + +(dnmi m-and "and immediate" (USES-RS USES-RT NO-DIS) + "and $rt,$rs,$lo16" + (emit andi rt rs lo16) +) + +(dnmi m-j "jump register" (USES-RS NO-DIS) + "j $rs" + (emit jr rs) +) + +(dnmi m-or "or immediate" (USES-RS USES-RT NO-DIS) + "or $rt,$rs,$lo16" + (emit ori rt rs lo16) +) + +(dnmi m-sll "shift left logical" (USES-RD USES-RT USES-RS NO-DIS) + "sll $rd,$rt,$rs" + (emit sllv rd rt rs) +) + +(dnmi m-slt "slt immediate" (USES-RS USES-RT NO-DIS) + "slt $rt,$rs,$imm" + (emit slti rt rs imm) +) + +(dnmi m-sltu "sltu immediate" (USES-RS USES-RT NO-DIS) + "sltu $rt,$rs,$imm" + (emit sltiu rt rs imm) +) + +(dnmi m-sra "shift right arithmetic" (USES-RD USES-RT USES-RS NO-DIS) + "sra $rd,$rt,$rs" + (emit srav rd rt rs) +) + +(dnmi m-srl "shift right logical" (USES-RD USES-RT USES-RS NO-DIS) + "srl $rd,$rt,$rs" + (emit srlv rd rt rs) +) + +(dnmi not "not" (USES-RD USES-RT NO-DIS) + "not $rd,$rt" + (emit nor rd (rs 0) rt) +) + +(dnmi subi "sub immediate" (USES-RS USES-RT NO-DIS) + "subi $rt,$rs,$mlo16" + (emit addiu rt rs mlo16) +) + +(dnmi m-sub "subtract immediate" (USES-RS USES-RT NO-DIS) + "sub $rt,$rs,$mlo16" + (emit addiu rt rs mlo16) +) + +(dnmi m-subu "subtract unsigned" (USES-RS USES-RT NO-DIS) + "subu $rt,$rs,$mlo16" + (emit addiu rt rs mlo16) +) + +(dnmi sb-base-0 "store byte - implied base 0" (USES-RT NO-DIS) + "sb $rt,$lo16" + (emit sb rt lo16 (base 0)) +) + +(dnmi sh-base-0 "store half - implied base 0" (USES-RT NO-DIS) + "sh $rt,$lo16" + (emit sh rt lo16 (base 0)) +) + +(dnmi sw-base-0 "store word - implied base 0" (USES-RT NO-DIS) + "sw $rt,$lo16" + (emit sw rt lo16 (base 0)) +) + +(dnmi m-xor "xor immediate" (USES-RS USES-RT NO-DIS) + "xor $rt,$rs,$lo16" + (emit xori rt rs lo16) +) + + +(if (keep-mach? (iq2000)) +(include "iq2000m.cpu")) + +(if (keep-mach? (iq10)) +(include "iq10.cpu")) + + + diff --git a/cpu/iq2000.opc b/cpu/iq2000.opc new file mode 100644 index 0000000..06600ec --- /dev/null +++ b/cpu/iq2000.opc @@ -0,0 +1,324 @@ +/* IQ2000 opcode support. -*- C -*- + + Copyright 2000, 2001, 2002 Free Software Foundation, Inc. + + Contributed by Red Hat Inc; developed under contract from Fujitsu. + + This file is part of the GNU Binutils. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +*/ + +/* This file is an addendum to iq2000.cpu. Heavy use of C code isn't + appropriate in .cpu files, so it resides here. This especially applies + to assembly/disassembly where parsing/printing can be quite involved. + Such things aren't really part of the specification of the cpu, per se, + so .cpu files provide the general framework and .opc files handle the + nitty-gritty details as necessary. + + Each section is delimited with start and end markers. + + -opc.h additions use: "-- opc.h" + -opc.c additions use: "-- opc.c" + -asm.c additions use: "-- asm.c" + -dis.c additions use: "-- dis.c" + -ibd.h additions use: "-- ibd.h" +*/ + +/* -- opc.h */ + +/* Allows reason codes to be output when assembler errors occur. */ +#define CGEN_VERBOSE_ASSEMBLER_ERRORS + +/* Override disassembly hashing - there are variable bits in the top + byte of these instructions. */ +#define CGEN_DIS_HASH_SIZE 8 +#define CGEN_DIS_HASH(buf,value) (((* (unsigned char*) (buf)) >> 6) % CGEN_DIS_HASH_SIZE) + +/* following activates check beyond hashing since some iq2000 and iq10 + instructions have same mnemonics but different functionality. */ +#define CGEN_VALIDATE_INSN_SUPPORTED + +extern int iq2000_cgen_insn_supported (CGEN_CPU_DESC cd, CGEN_INSN *insn); + +/* -- asm.c */ +static const char * parse_mimm PARAMS ((CGEN_CPU_DESC, const char **, int, long *)); +static const char * parse_imm PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *)); +static const char * parse_hi16 PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *)); +static const char * parse_lo16 PARAMS ((CGEN_CPU_DESC, const char **, int, long *)); + +/* Special check to ensure that instruction exists for given machine */ +int +iq2000_cgen_insn_supported (cd, insn) + CGEN_CPU_DESC cd; + CGEN_INSN *insn; +{ + int machs = cd->machs; + + return ((CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_MACH) & machs) != 0); +} + +static int iq2000_cgen_isa_register (strp) + const char **strp; +{ + int len; + int ch1, ch2; + if (**strp == 'r' || **strp == 'R') + { + len = strlen (*strp); + if (len == 2) + { + ch1 = (*strp)[1]; + if ('0' <= ch1 && ch1 <= '9') + return 1; + } + else if (len == 3) + { + ch1 = (*strp)[1]; + ch2 = (*strp)[2]; + if (('1' <= ch1 && ch1 <= '2') && ('0' <= ch2 && ch2 <= '9')) + return 1; + if ('3' == ch1 && (ch2 == '0' || ch2 == '1')) + return 1; + } + } + if (**strp == '%' && tolower((*strp)[1]) != 'l' && tolower((*strp)[1]) != 'h') + return 1; + return 0; +} + +/* Handle negated literal. */ + +static const char * +parse_mimm (cd, strp, opindex, valuep) + CGEN_CPU_DESC cd; + const char **strp; + int opindex; + long *valuep; +{ + const char *errmsg; + long value; + + /* Verify this isn't a register */ + if (iq2000_cgen_isa_register (strp)) + errmsg = _("immediate value cannot be register"); + else + { + long value; + + errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value); + if (errmsg == NULL) + { + long x = (-value) & 0xFFFF0000; + if (x != 0 && x != 0xFFFF0000) + errmsg = _("immediate value out of range"); + else + *valuep = (-value & 0xFFFF); + } + } + return errmsg; +} + +/* Handle signed/unsigned literal. */ + +static const char * +parse_imm (cd, strp, opindex, valuep) + CGEN_CPU_DESC cd; + const char **strp; + int opindex; + unsigned long *valuep; +{ + const char *errmsg; + long value; + + if (iq2000_cgen_isa_register (strp)) + errmsg = _("immediate value cannot be register"); + else + { + long value; + + errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value); + if (errmsg == NULL) + { + long x = value & 0xFFFF0000; + if (x != 0 && x != 0xFFFF0000) + errmsg = _("immediate value out of range"); + else + *valuep = (value & 0xFFFF); + } + } + return errmsg; +} + +/* Handle iq10 21-bit jmp offset. */ + +static const char * +parse_jtargq10 (cd, strp, opindex, reloc, type_addr, valuep) + CGEN_CPU_DESC cd; + const char **strp; + int opindex; + int reloc; + enum cgen_parse_operand_result *type_addr; + unsigned long *valuep; +{ + const char *errmsg; + bfd_vma value; + enum cgen_parse_operand_result result_type = CGEN_PARSE_OPERAND_RESULT_NUMBER; + + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_IQ2000_OFFSET_21, + &result_type, &value); + if (errmsg == NULL && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) + { + /* check value is within 23-bits (remembering that 2-bit shift right will occur) */ + if (value > 0x7fffff) + return _("21-bit offset out of range"); + } + *valuep = (value & 0x7FFFFF); + return errmsg; +} + +/* Handle high(). */ + +static const char * +parse_hi16 (cd, strp, opindex, valuep) + CGEN_CPU_DESC cd; + const char **strp; + int opindex; + unsigned long *valuep; +{ + if (strncasecmp (*strp, "%hi(", 4) == 0) + { + enum cgen_parse_operand_result result_type; + bfd_vma value; + const char *errmsg; + + *strp += 4; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_HI16, + &result_type, &value); + if (**strp != ')') + return _("missing `)'"); + + ++*strp; + if (errmsg == NULL + && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) + { + /* if value has top-bit of %lo on, then it will + sign-propagate and so we compensate by adding + 1 to the resultant %hi value */ + if (value & 0x8000) + value += 0x10000; + value >>= 16; + } + *valuep = value; + + return errmsg; + } + + /* we add %uhi in case a user just wants the high 16-bits or is using + an insn like ori for %lo which does not sign-propagate */ + if (strncasecmp (*strp, "%uhi(", 5) == 0) + { + enum cgen_parse_operand_result result_type; + bfd_vma value; + const char *errmsg; + + *strp += 5; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_IQ2000_UHI16, + &result_type, &value); + if (**strp != ')') + return _("missing `)'"); + + ++*strp; + if (errmsg == NULL + && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) + { + value >>= 16; + } + *valuep = value; + + return errmsg; + } + + return parse_imm (cd, strp, opindex, valuep); +} + +/* Handle %lo in a signed context. + The signedness of the value doesn't matter to %lo(), but this also + handles the case where %lo() isn't present. */ + +static const char * +parse_lo16 (cd, strp, opindex, valuep) + CGEN_CPU_DESC cd; + const char **strp; + int opindex; + long *valuep; +{ + if (strncasecmp (*strp, "%lo(", 4) == 0) + { + const char *errmsg; + enum cgen_parse_operand_result result_type; + bfd_vma value; + + *strp += 4; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_LO16, + &result_type, &value); + if (**strp != ')') + return _("missing `)'"); + ++*strp; + if (errmsg == NULL + && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) + value &= 0xffff; + *valuep = value; + return errmsg; + } + + return parse_imm (cd, strp, opindex, valuep); +} + +/* Handle %lo in a negated signed context. + The signedness of the value doesn't matter to %lo(), but this also + handles the case where %lo() isn't present. */ + +static const char * +parse_mlo16 (cd, strp, opindex, valuep) + CGEN_CPU_DESC cd; + const char **strp; + int opindex; + long *valuep; +{ + if (strncasecmp (*strp, "%lo(", 4) == 0) + { + const char *errmsg; + enum cgen_parse_operand_result result_type; + bfd_vma value; + + *strp += 4; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_LO16, + &result_type, &value); + if (**strp != ')') + return _("missing `)'"); + ++*strp; + if (errmsg == NULL + && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) + value = (-value) & 0xffff; + *valuep = value; + return errmsg; + } + + return parse_mimm (cd, strp, opindex, valuep); +} + +/* -- */ diff --git a/cpu/iq2000m.cpu b/cpu/iq2000m.cpu new file mode 100644 index 0000000..a3a41d9 --- /dev/null +++ b/cpu/iq2000m.cpu @@ -0,0 +1,630 @@ +; IQ2000-only CPU description. -*- Scheme -*- +; +; Copyright 2000, 2001, 2002 Free Software Foundation, Inc. +; +; Contributed by Red Hat Inc; developed under contract from Vitesse. +; +; This file is part of the GNU Binutils. +; +; This program is free software; you can redistribute it and/or modify +; it under the terms of the GNU General Public License as published by +; the Free Software Foundation; either version 2 of the License, or +; (at your option) any later version. +; +; This program is distributed in the hope that it will be useful, +; but WITHOUT ANY WARRANTY; without even the implied warranty of +; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +; GNU General Public License for more details. +; +; You should have received a copy of the GNU General Public License +; along with this program; if not, write to the Free Software +; Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +(dni andoui "and upper ones immediate" (MACH2000 USES-RS USES-RT) + "andoui $rt,$rs,$hi16" + (+ OP_ANDOUI rs rt hi16) + (set rt (and rs (or (sll hi16 16) #xFFFF))) + ()) + +(dni andoui2 "and upper ones immediate" (ALIAS NO-DIS MACH2000 USES-RS USES-RT) + "andoui ${rt-rs},$hi16" + (+ OP_ANDOUI rt-rs hi16) + (set rt-rs (and rt-rs (or (sll hi16 16) #xFFFF))) + ()) + +(dni orui2 "or upper immediate" (ALIAS NO-DIS MACH2000 USES-RS USES-RT) + "orui ${rt-rs},$hi16" + (+ OP_ORUI rt-rs hi16) + (set rt-rs (or rt-rs (sll hi16 16))) + ()) + +(dni orui "or upper immediate" (MACH2000 USES-RS USES-RT) + "orui $rt,$rs,$hi16" + (+ OP_ORUI rs rt hi16) + (set rt (or rs (sll hi16 16))) + ()) + +(dni bgtz "branch if greater than zero" (MACH2000 USES-RS) + "bgtz $rs,$offset" + (+ OP_BGTZ rs (f-rt 0) offset) + (if (gt rs 0) + (delay 1 (set pc offset))) + ()) + + +(dni bgtzl "branch if greater than zero likely" (MACH2000 USES-RS) + "bgtzl $rs,$offset" + (+ OP_BGTZL rs (f-rt 0) offset) + (if (gt rs 0) + (delay 1 (set pc offset)) + (skip 1)) + ()) + +(dni blez "branch if less than or equal to zero" (MACH2000 USES-RS) + "blez $rs,$offset" + (+ OP_BLEZ rs (f-rt 0) offset) + (if (le rs 0) + (delay 1 (set pc offset))) + ()) + +(dni blezl "branch if less than or equal to zero likely" (MACH2000 USES-RS) + "blezl $rs,$offset" + (+ OP_BLEZL rs (f-rt 0) offset) + (if (le rs 0) + (delay 1 (set pc offset)) + (skip 1)) + ()) + + +(dni mrgb "merge bytes" (MACH2000 USES-RD USES-RS USES-RT) + "mrgb $rd,$rs,$rt,$mask" + (+ OP_SPECIAL rs rt rd (f-10 0) mask FUNC_MRGB) + (sequence ((SI temp)) + (if (bitclear? mask 0) + (set temp (and rs #xFF)) + (set temp (and rt #xFF))) + (if (bitclear? mask 1) + (set temp (or temp (and rs #xFF00))) + (set temp (or temp (and rt #xFF00)))) + (if (bitclear? mask 2) + (set temp (or temp (and rs #xFF0000))) + (set temp (or temp (and rt #xFF0000)))) + (if (bitclear? mask 3) + (set temp (or temp (and rs #xFF000000))) + (set temp (or temp (and rt #xFF000000)))) + (set rd temp)) + ()) + +(dni mrgb2 "merge bytes" (ALIAS NO-DIS MACH2000 USES-RD USES-RS USES-RT) + "mrgb ${rd-rs},$rt,$mask" + (+ OP_SPECIAL rt rd-rs (f-10 0) mask FUNC_MRGB) + (sequence ((SI temp)) + (if (bitclear? mask 0) + (set temp (and rd-rs #xFF)) + (set temp (and rt #xFF))) + (if (bitclear? mask 1) + (set temp (or temp (and rd-rs #xFF00))) + (set temp (or temp (and rt #xFF00)))) + (if (bitclear? mask 2) + (set temp (or temp (and rd-rs #xFF0000))) + (set temp (or temp (and rt #xFF0000)))) + (if (bitclear? mask 3) + (set temp (or temp (and rd-rs #xFF000000))) + (set temp (or temp (and rt #xFF000000)))) + (set rd-rs temp)) + ()) + +; NOTE: None of these instructions' semantics are specified, so they +; will not work in a simulator. +; +; Architectural and coprocessor instructions. +; BREAK and SYSCALL are implemented with escape hatches to the C +; code. These are used by the test suite to indicate pass/failures. + +(dni bctxt "branch and switch context" (MACH2000 DELAY-SLOT COND-CTI USES-RS) + "bctxt $rs,$offset" + (+ OP_REGIMM rs (f-rt 6) offset) + (unimp bctxt) + ()) + +(dni bc0f "branch if copro 0 condition false" (MACH2000 DELAY-SLOT COND-CTI) + "bc0f $offset" + (+ OP_COP0 (f-rs 8) (f-rt 0) offset) + (unimp bc0f) + ()) + +(dni bc0fl "branch if copro 0 condition false likely" (MACH2000 DELAY-SLOT COND-CTI SKIP-CTI) + "bc0fl $offset" + (+ OP_COP0 (f-rs 8) (f-rt 2) offset) + (unimp bc0fl) + ()) + +(dni bc3f "branch if copro 3 condition false" (MACH2000 DELAY-SLOT COND-CTI) + "bc3f $offset" + (+ OP_COP3 (f-rs 8) (f-rt 0) offset) + (unimp bc3f) + ()) + +(dni bc3fl "branch if copro 3 condition false likely" (MACH2000 DELAY-SLOT COND-CTI SKIP-CTI) + "bc3fl $offset" + (+ OP_COP3 (f-rs 8) (f-rt 2) offset) + (unimp bc3fl) + ()) + +(dni bc0t "branch if copro 0 condition true" (MACH2000 DELAY-SLOT COND-CTI) + "bc0t $offset" + (+ OP_COP0 (f-rs 8) (f-rt 1) offset) + (unimp bc0t) + ()) + +(dni bc0tl "branch if copro 0 condition true likely" (MACH2000 DELAY-SLOT COND-CTI SKIP-CTI) + "bc0tl $offset" + (+ OP_COP0 (f-rs 8) (f-rt 3) offset) + (unimp bc0tl) + ()) + +(dni bc3t "branch if copro 3 condition true" (MACH2000 DELAY-SLOT COND-CTI) + "bc3t $offset" + (+ OP_COP3 (f-rs 8) (f-rt 1) offset) + (unimp bc3t) + ()) + +(dni bc3tl "branch if copro 3 condition true likely" (MACH2000 DELAY-SLOT COND-CTI SKIP-CTI) + "bc3tl $offset" + (+ OP_COP3 (f-rs 8) (f-rt 3) offset) + (unimp bc3tl) + ()) + +; Note that we don't set the USES-RD or USES-RT attributes for many of the following +; instructions, as it's the COP register that's being specified. + +(dni cfc0 "control from coprocessor 0" (MACH2000 LOAD-DELAY USES-RT) + "cfc0 $rt,$rd" + (+ OP_COP0 (f-rs 2) rt rd (f-10-11 0)) + (unimp cfc0) + ()) + +(dni cfc1 "control from coprocessor 1" (MACH2000 LOAD-DELAY USES-RT) + "cfc1 $rt,$rd" + (+ OP_COP1 (f-rs 2) rt rd (f-10-11 0)) + (unimp cfc1) + ()) + +(dni cfc2 "control from coprocessor 2" (MACH2000 LOAD-DELAY USES-RT YIELD-INSN) + "cfc2 $rt,$rd" + (+ OP_COP2 (f-rs 2) rt rd (f-10-11 0)) + (unimp cfc2) + ()) + +(dni cfc3 "control from coprocessor 3" (MACH2000 LOAD-DELAY USES-RT YIELD-INSN) + "cfc3 $rt,$rd" + (+ OP_COP3 (f-rs 2) rt rd (f-10-11 0)) + (unimp cfc3) + ()) + +; COPz instructions are an instruction form, not real instructions +; with associated assembly mnemonics. Therefore, they are omitted +; from the ISA description. + +(dni chkhdr "check header" (MACH2000 LOAD-DELAY USES-RD YIELD-INSN) + "chkhdr $rd,$rt" + (+ OP_COP3 (f-rs 9) rt rd (f-shamt 0) (f-func 0)) + (unimp chkhdr) + ()) + +(dni ctc0 "control to coprocessor 0" (MACH2000 USES-RT) + "ctc0 $rt,$rd" + (+ OP_COP0 (f-rs 6) rt rd (f-10-11 0)) + (unimp ctc0) + ()) + +(dni ctc1 "control to coprocessor 1" (MACH2000 USES-RT) + "ctc1 $rt,$rd" + (+ OP_COP1 (f-rs 6) rt rd (f-10-11 0)) + (unimp ctc1) + ()) + +(dni ctc2 "control to coprocessor 2" (MACH2000 USES-RT) + "ctc2 $rt,$rd" + (+ OP_COP2 (f-rs 6) rt rd (f-10-11 0)) + (unimp ctc2) + ()) + +(dni ctc3 "control to coprocessor 3" (MACH2000 USES-RT) + "ctc3 $rt,$rd" + (+ OP_COP3 (f-rs 6) rt rd (f-10-11 0)) + (unimp ctc3) + ()) + +(dni jcr "jump context register" (MACH2000 DELAY-SLOT UNCOND-CTI USES-RS) + "jcr $rs" + (+ OP_SPECIAL rs (f-rt 0) (f-rd 0) (f-shamt 0) FUNC_JCR) + (unimp jcr) + ()) + +(dni luc32 "lookup chain 32 bits" (MACH2000 USES-RD USES-RT YIELD-INSN) + "luc32 $rt,$rd" + (+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 3)) + (unimp luc32) + ()) + +(dni luc32l "lookup chain 32 bits and lock" (MACH2000 USES-RD USES-RT YIELD-INSN) + "luc32l $rt,$rd" + (+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 7)) + (unimp luc32l) + ()) + +(dni luc64 "lookup chain 64 bits" (MACH2000 USES-RD USES-RT YIELD-INSN) + "luc64 $rt,$rd" + (+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 11)) + (unimp luc64) + ()) + +(dni luc64l "lookup chain 64 bits and lock" (MACH2000 USES-RD USES-RT YIELD-INSN) + "luc64l $rt,$rd" + (+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 15)) + (unimp luc64l) + ()) + +(dni luk "lookup key" (MACH2000 USES-RD USES-RT) + "luk $rt,$rd" + (+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 8)) + (unimp luk) + ()) + +(dni lulck "lookup lock" (MACH2000 USES-RT YIELD-INSN) + "lulck $rt" + (+ OP_COP2 (f-rs 1) rt (f-rd 0) (f-shamt 0) (f-func 4)) + (unimp lulck) + ()) + +(dni lum32 "lookup match 32 bits" (MACH2000 USES-RD USES-RT YIELD-INSN) + "lum32 $rt,$rd" + (+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 2)) + (unimp lum32) + ()) + +(dni lum32l "lookup match 32 bits and lock" (MACH2000 USES-RD USES-RT YIELD-INSN) + "lum32l $rt,$rd" + (+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 6)) + (unimp lum32l) + ()) + +(dni lum64 "lookup match 64 bits" (MACH2000 USES-RD USES-RT YIELD-INSN) + "lum64 $rt,$rd" + (+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 10)) + (unimp lum64) + ()) + +(dni lum64l "lookup match 64 bits and lock" (MACH2000 USES-RD USES-RT YIELD-INSN) + "lum64l $rt,$rd" + (+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 14)) + (unimp lum64l) + ()) + +(dni lur "lookup read" (MACH2000 USES-RD USES-RT YIELD-INSN) + "lur $rt,$rd" + (+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 1)) + (unimp lur) + ()) + +(dni lurl "lookup read and lock" (MACH2000 USES-RD USES-RT YIELD-INSN) + "lurl $rt,$rd" + (+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 5)) + (unimp lurl) + ()) + +(dni luulck "lookup unlock" (MACH2000 USES-RT YIELD-INSN) + "luulck $rt" + (+ OP_COP2 (f-rs 1) rt (f-rd 0) (f-shamt 0) (f-func 0)) + (unimp luulck) + ()) + +(dni mfc0 "move from coprocessor 0" (MACH2000 LOAD-DELAY USES-RT) + "mfc0 $rt,$rd" + (+ OP_COP0 (f-rs 0) rt rd (f-10-11 0)) + (unimp mfc0) + ()) + +(dni mfc1 "move from coprocessor 1" (MACH2000 LOAD-DELAY USES-RT) + "mfc1 $rt,$rd" + (+ OP_COP1 (f-rs 0) rt rd (f-10-11 0)) + (unimp mfc1) + ()) + +(dni mfc2 "move from coprocessor 2" (MACH2000 LOAD-DELAY USES-RT YIELD-INSN) + "mfc2 $rt,$rd" + (+ OP_COP2 (f-rs 0) rt rd (f-10-11 0)) + (unimp mfc2) + ()) + +(dni mfc3 "move from coprocessor 3" (MACH2000 LOAD-DELAY USES-RT YIELD-INSN) + "mfc3 $rt,$rd" + (+ OP_COP3 (f-rs 0) rt rd (f-10-11 0)) + (unimp mfc3) + ()) + +(dni mtc0 "move to coprocessor 0" (MACH2000 USES-RT) + "mtc0 $rt,$rd" + (+ OP_COP0 (f-rs 4) rt rd (f-10-11 0)) + (unimp mtc0) + ()) + +(dni mtc1 "move to coprocessor 1" (MACH2000 USES-RT) + "mtc1 $rt,$rd" + (+ OP_COP1 (f-rs 4) rt rd (f-10-11 0)) + (unimp mtc1) + ()) + +(dni mtc2 "move to coprocessor 2" (MACH2000 USES-RT) + "mtc2 $rt,$rd" + (+ OP_COP2 (f-rs 4) rt rd (f-10-11 0)) + (unimp mtc2) + ()) + +(dni mtc3 "move to coprocessor 3" (MACH2000 USES-RT) + "mtc3 $rt,$rd" + (+ OP_COP3 (f-rs 4) rt rd (f-10-11 0)) + (unimp mtc3) + ()) + +(dni pkrl "pkrl" (MACH2000 USES-RD USES-RT YIELD-INSN) + "pkrl $rd,$rt" + (+ OP_COP3 (f-rs 1) rt rd (f-shamt 0) (f-func 7)) + (unimp pkrl) + ()) + +(dni pkrlr1 "pkrlr1" (MACH2000 USES-RT YIELD-INSN) + "pkrlr1 $rt,$count" + (+ OP_COP3 (f-rs 29) rt count) + (unimp pkrlr1) + ()) + +(dni pkrlr30 "pkrlr30" (MACH2000 USES-RT YIELD-INSN) + "pkrlr30 $rt,$count" + (+ OP_COP3 (f-rs 31) rt count) + (unimp pkrlr30) + ()) + +(dni rb "dma read bytes" (MACH2000 USES-RD USES-RT YIELD-INSN) + "rb $rd,$rt" + (+ OP_COP3 (f-rs 1) rt rd (f-shamt 0) (f-func 4)) + (unimp rb) + ()) + +(dni rbr1 "dma read bytes using r1" (MACH2000 USES-RT YIELD-INSN) + "rbr1 $rt,$count" + (+ OP_COP3 (f-rs 24) rt count) + (unimp rbr1) + ()) + +(dni rbr30 "dma read bytes using r30" (MACH2000 USES-RT YIELD-INSN) + "rbr30 $rt,$count" + (+ OP_COP3 (f-rs 26) rt count) + (unimp rbr30) + ()) + +(dni rfe "restore from exception" (MACH2000) + "rfe" + (+ OP_COP0 (f-25 1) (f-24-19 0) (f-func 16)) + (unimp rfe) + ()) + +(dni rx "dma read word64s" (MACH2000 USES-RD USES-RT YIELD-INSN) + "rx $rd,$rt" + (+ OP_COP3 (f-rs 1) rt rd (f-shamt 0) (f-func 6)) + (unimp rx) + ()) + +(dni rxr1 "dma read word64s using r1" (MACH2000 USES-RT YIELD-INSN) + "rxr1 $rt,$count" + (+ OP_COP3 (f-rs 28) rt count) + (unimp rxr1) + ()) + +(dni rxr30 "dma read word 64s using r30" (MACH2000 USES-RT YIELD-INSN) + "rxr30 $rt,$count" + (+ OP_COP3 (f-rs 30) rt count) + (unimp rxr30) + ()) + +(dni sleep "sleep" (MACH2000 YIELD-INSN) + "sleep" + (+ OP_SPECIAL execode FUNC_SLEEP) + (unimp sleep) + ()) + +(dni srrd "sram read" (MACH2000 USES-RT YIELD-INSN) + "srrd $rt" + (+ OP_COP2 (f-rs 1) rt (f-rd 0) (f-shamt 0) (f-func 16)) + (unimp srrd) + ()) + +(dni srrdl "sram read and lock" (MACH2000 USES-RT YIELD-INSN) + "srrdl $rt" + (+ OP_COP2 (f-rs 1) rt (f-rd 0) (f-shamt 0) (f-func 20)) + (unimp srrdl) + ()) + +(dni srulck "sram unlock" (MACH2000 USES-RT YIELD-INSN) + "srulck $rt" + (+ OP_COP2 (f-rs 1) rt (f-rd 0) (f-shamt 0) (f-func 22)) + (unimp srulck) + ()) + +(dni srwr "sram write" (MACH2000 USES-RD USES-RT YIELD-INSN) + "srwr $rt,$rd" + (+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 17)) + (unimp srwr) + ()) + +(dni srwru "sram write and unlock" (MACH2000 USES-RD USES-RT YIELD-INSN) + "srwru $rt,$rd" + (+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 21)) + (unimp srwru) + ()) + +(dni trapqfl "yield if dma queue full" (MACH2000 YIELD-INSN) + "trapqfl" + (+ OP_COP3 (f-rs 1) (f-rt 0) (f-rd 0) (f-shamt 0) (f-func 8)) + (unimp trapqfl) + ()) + +(dni trapqne "yield if dma queue not empty" (MACH2000 YIELD-INSN) + "trapqne" + (+ OP_COP3 (f-rs 1) (f-rt 0) (f-rd 0) (f-shamt 0) (f-func 9)) + (unimp trapqne) + ()) + +(dni traprel "traprel" (MACH2000 USES-RT YIELD-INSN) + "traprel $rt" + (+ OP_COP3 (f-rs 1) rt (f-rd 0) (f-shamt 0) (f-func 10)) + (unimp traprel) + ()) + +(dni wb "dma write bytes" (MACH2000 USES-RD USES-RT YIELD-INSN) + "wb $rd,$rt" + (+ OP_COP3 (f-rs 1) rt rd (f-shamt 0) (f-func 0)) + (unimp wb) + ()) + +(dni wbu "dma write bytes and unlock" (MACH2000 USES-RD USES-RT YIELD-INSN) + "wbu $rd,$rt" + (+ OP_COP3 (f-rs 1) rt rd (f-shamt 0) (f-func 1)) + (unimp wbu) + ()) + +(dni wbr1 "dma write bytes using r1" (MACH2000 USES-RT YIELD-INSN) + "wbr1 $rt,$count" + (+ OP_COP3 (f-rs 16) rt count) + (unimp wbr1) + ()) + +(dni wbr1u "dma write bytes using r1 and unlock" (MACH2000 USES-RT YIELD-INSN) + "wbr1u $rt,$count" + (+ OP_COP3 (f-rs 17) rt count) + (unimp wbr1u) + ()) + +(dni wbr30 "dma write bytes using r30" (MACH2000 USES-RT YIELD-INSN) + "wbr30 $rt,$count" + (+ OP_COP3 (f-rs 18) rt count) + (unimp wbr30) + ()) + +(dni wbr30u "dma write bytes using r30 and unlock" (MACH2000 USES-RT YIELD-INSN) + "wbr30u $rt,$count" + (+ OP_COP3 (f-rs 19) rt count) + (unimp wbr30u) + ()) + +(dni wx "dma write word64s" (MACH2000 USES-RD USES-RT YIELD-INSN) + "wx $rd,$rt" + (+ OP_COP3 (f-rs 1) rt rd (f-shamt 0) (f-func 2)) + (unimp wx) + ()) + +(dni wxu "dma write word64s and unlock" (MACH2000 USES-RD USES-RT YIELD-INSN) + "wxu $rd,$rt" + (+ OP_COP3 (f-rs 1) rt rd (f-shamt 0) (f-func 3)) + (unimp wxu) + ()) + +(dni wxr1 "dma write word64s using r1" (MACH2000 USES-RT YIELD-INSN) + "wxr1 $rt,$count" + (+ OP_COP3 (f-rs 20) rt count) + (unimp wxr1) + ()) + +(dni wxr1u "dma write word64s using r1 and unlock" (MACH2000 USES-RT YIELD-INSN) + "wxr1u $rt,$count" + (+ OP_COP3 (f-rs 21) rt count) + (unimp wxr1u) + ()) + +(dni wxr30 "dma write word64s using r30" (MACH2000 USES-RT YIELD-INSN) + "wxr30 $rt,$count" + (+ OP_COP3 (f-rs 22) rt count) + (unimp wxr30) + ()) + +(dni wxr30u "dma write word64s using r30 and unlock" (MACH2000 USES-RT YIELD-INSN) + "wxr30u $rt,$count" + (+ OP_COP3 (f-rs 23) rt count) + (unimp wxr30u) + ()) + + +; Load/Store instructions. + +(dni ldw "load double word" (MACH2000 EVEN-REG-NUM LOAD-DELAY USES-RT) + "ldw $rt,$lo16($base)" + (+ OP_LDW base rt lo16) + (sequence ((SI addr)) + (set addr (and (add base lo16) (inv 3))) + (set (reg h-gr (add (ifield f-rt) 1)) (mem SI addr)) + (set rt (mem SI (add addr 4)))) + ()) + +(dni sdw "store double word" (MACH2000 EVEN-REG-NUM USES-RT) + "sdw $rt,$lo16($base)" + (+ OP_SDW base rt lo16) + (sequence ((SI addr)) + (set addr (and (add base lo16) (inv 3))) + (set (mem SI (add addr 4)) rt) + (set (mem SI addr) (reg h-gr (add (ifield f-rt) 1)))) + ()) + + +; Jump instructions + +(dni j "jump" (MACH2000) + "j $jmptarg" + (+ OP_J (f-rsrvd 0) jmptarg) + (delay 1 (set pc jmptarg)) + ()) + +(dni jal "jump and link" (MACH2000 USES-R31) + "jal $jmptarg" + (+ OP_JAL (f-rsrvd 0) jmptarg) + (delay 1 + (sequence () + (set (reg h-gr 31) (add pc 8)) + (set pc jmptarg))) + ()) + +(dni bmb "branch if matching byte-lane" (MACH2000 USES-RS USES-RT) + "bmb $rs,$rt,$offset" + (+ OP_BMB rs rt offset) + (sequence ((BI branch?)) + (set branch? 0) + (if (eq (and rs #xFF) (and rt #xFF)) + (set branch? 1)) + (if (eq (and rs #xFF00) (and rt #xFF00)) + (set branch? 1)) + (if (eq (and rs #xFF0000) (and rt #xFF0000)) + (set branch? 1)) + (if (eq (and rs #xFF000000) (and rt #xFF000000)) + (set branch? 1)) + (if branch? + (delay 1 (set pc offset)))) + ()) + + +; Macros + +(dnmi ldw-base-0 "load double word - implied base 0" (MACH2000 EVEN-REG-NUM LOAD-DELAY USES-RT USES-RS NO-DIS) + "ldw $rt,$lo16" + (emit ldw rt lo16 (base 0)) +) + +(dnmi sdw-base-0 "store double word - implied base 0" (MACH2000 EVEN-REG-NUM USES-RT NO-DIS) + "sdw $rt,$lo16" + (emit sdw rt lo16 (base 0)) +) + + + + + + diff --git a/cpu/simplify.inc b/cpu/simplify.inc new file mode 100644 index 0000000..12b05b7 --- /dev/null +++ b/cpu/simplify.inc @@ -0,0 +1,215 @@ +; Collection of macros, for GNU Binutils .cpu files. -*- Scheme -*- +; +; Copyright 2000 Free Software Foundation, Inc. +; +; Contributed by Red Hat Inc. +; +; This file is part of the GNU Binutils. +; +; This program is free software; you can redistribute it and/or modify +; it under the terms of the GNU General Public License as published by +; the Free Software Foundation; either version 2 of the License, or +; (at your option) any later version. +; +; This program is distributed in the hope that it will be useful, +; but WITHOUT ANY WARRANTY; without even the implied warranty of +; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +; GNU General Public License for more details. +; +; You should have received a copy of the GNU General Public License +; along with this program; if not, write to the Free Software +; Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +; Enums. + +; Define a normal enum without using name/value pairs. +; This is currently the same as define-full-enum but it needn't remain +; that way (it's define-full-enum that would change). + +(define-pmacro (define-normal-enum name comment attrs prefix vals) + "\ +Define a normal enum, fixed number of arguments. +" + (define-full-enum name comment attrs prefix vals) +) + +; Define a normal insn enum. + +(define-pmacro (define-normal-insn-enum name comment attrs prefix fld vals) + "\ +Define a normal instruction opcode enum. +" + (define-full-insn-enum name comment attrs prefix fld vals) +) + +; Instruction fields. + +; Normally, fields are unsigned have no encode/decode needs. + +(define-pmacro (define-normal-ifield name comment attrs start length) + "Define a normal instruction field.\n" + (define-full-ifield name comment attrs start length UINT #f #f) +) + +; For those who don't like typing. + +(define-pmacro df + "Shorthand form of define-full-ifield.\n" + define-full-ifield +) +(define-pmacro dnf + "Shorthand form of define-normal-ifield.\n" + define-normal-ifield +) + +; Define a normal multi-ifield. +; FIXME: The define-normal version for ifields doesn't include the mode. + +(define-pmacro (define-normal-multi-ifield name comment attrs + mode subflds insert extract) + "Define a normal multi-part instruction field.\n" + (define-full-multi-ifield name comment attrs mode subflds insert extract) +) + +; For those who don't like typing. + +(define-pmacro dnmf + "Shorthand form of define-normal-multi-ifield.\n" + define-normal-multi-ifield +) + +; Simple multi-ifields: mode is UINT, default insert/extract support. + +(define-pmacro (dsmf name comment attrs subflds) + "Define a simple multi-part instruction field.\n" + (define-full-multi-ifield name comment attrs UINT subflds #f #f) +) + +; Hardware. + +; Simpler version for most hardware elements. +; Allow special assembler support specification but no semantic-name or +; get/set specs. + +(define-pmacro (define-normal-hardware name comment attrs type + indices values handlers) + "\ +Define a normal hardware element. +" + (define-full-hardware name comment attrs name type + indices values handlers () () ()) +) + +; For those who don't like typing. + +(define-pmacro dnh + "Shorthand form of define-normal-hardware.\n" + define-normal-hardware +) + +; Simpler version of dnh that leaves out the indices, values, handlers, +; get, set, and layout specs. +; This is useful for 1 bit registers. +; ??? While dsh and dnh aren't that distinguishable when perusing a .cpu file, +; they both take a fixed number of positional arguments, and dsh is a proper +; subset of dnh with all arguments in the same positions, so methinks things +; are ok. + +(define-pmacro (define-simple-hardware name comment attrs type) + "\ +Define a simple hardware element (usually a scalar register). +" + (define-full-hardware name comment attrs name type () () () () () ()) +) + +(define-pmacro dsh + "Shorthand form of define-simple-hardware.\n" + define-simple-hardware +) + +; Operands. + +(define-pmacro (define-normal-operand name comment attrs type index) + "Define a normal operand.\n" + (define-full-operand name comment attrs type DFLT index () () ()) +) + +; For those who don't like typing. +; FIXME: dno? + +(define-pmacro dnop + "Shorthand form of define-normal-operand.\n" + define-normal-operand +) + +(define-pmacro (dndo x-name x-mode x-args + x-syntax x-base-ifield x-encoding x-ifield-assertion + x-getter x-setter) + "Define a normal derived operand." + (define-derived-operand + (name x-name) + (mode x-mode) + (args x-args) + (syntax x-syntax) + (base-ifield x-base-ifield) + (encoding x-encoding) + (ifield-assertion x-ifield-assertion) + (getter x-getter) + (setter x-setter) + ) +) + +; Instructions. + +; Define an instruction object, normal version. +; At present all fields must be specified. +; Fields ifield-assertion is absent. + +(define-pmacro (define-normal-insn name comment attrs syntax fmt semantics timing) + "Define a normal instruction.\n" + (define-full-insn name comment attrs syntax fmt () semantics timing) +) + +; To reduce the amount of typing. +; Note that this is the same name as the D'ni in MYST. Oooohhhh..... +; this must be the right way to go. :-) + +(define-pmacro dni + "Shorthand form of define-normal-insn.\n" + define-normal-insn +) + +; Macro instructions. + +; Define a macro-insn object, normal version. +; This only supports expanding to one real insn. + +(define-pmacro (define-normal-macro-insn name comment attrs syntax expansion) + "Define a normal macro instruction.\n" + (define-full-minsn name comment attrs syntax expansion) +) + +; To reduce the amount of typing. + +(define-pmacro dnmi + "Shorthand form of define-normal-macro-insn.\n" + define-normal-macro-insn +) + +; Modes. +; ??? Not currently available for use. +; +; Define Normal Mode +; +;(define-pmacro (define-normal-mode name comment attrs bits bytes +; non-mode-c-type printf-type sem-mode ptr-to host?) +; "Define a normal mode.\n" +; (define-full-mode name comment attrs bits bytes +; non-mode-c-type printf-type sem-mode ptr-to host?) +;) +; +; For those who don't like typing. +;(define-pmacro dnm +; "Shorthand form of define-normal-mode.\n" +; define-normal-mode +;) diff --git a/gdb/ChangeLog-2002 b/gdb/ChangeLog-2002 new file mode 100644 index 0000000..ad2cfda --- /dev/null +++ b/gdb/ChangeLog-2002 @@ -0,0 +1,15039 @@ +2002-12-31 Mark Kettenis + + * gdb_dirent.h: Cleanup and update code to match the example in + the Autoconf manual. + * configure.in: Call AC_HEADER_DIRENT. Remove dirent.h, + sys/ndir.h, sys/dir.h and ndir.h from call to AC_CHECK_HEADERS. + * configure: Regenerated. + +2002-12-30 Adam Fedor + + * objc-exp.y (parse_number): Cast sscanf arguments to proper type. + (yylex): Initialize c to avoid uninitialized warning. + +2002-12-29 Kazu Hirata + + * doc/fdl.texi: Revert the last change. + +2002-12-29 Mark Kettenis + + * tracepoint.c (ISATTY): Removed. + +2002-12-26 J. Brobecker + + Continuing work to convert the hppa targets to multiarch partil. + + * hppa-tdep.c: Add some missing forward declarations. + (frameless_function_invocation): Prefix the function name + by "hppa_" to avoid polluting the namespace. Update all calls + to use the new function name. + (saved_pc_after_call): Ditto. + (init_extra_frame_info): Ditto. + (frame_chain): Ditto. + (push_dummy_frame): Ditto. + (target_read_pc): Ditto. + (target_write_pc): Ditto. + (in_solib_call_trampoline): Ditto. + (in_solib_return_trampoline): Ditto. + (skip_trampoline_code): Ditto. + (hppa_read_fp): New function, renamed from target_read_fp. + (hppa_target_read_fp): New function, using hppa_read_fp. + This function conforms to the function profile for the + READ_FP gdbarch method. + (hppa_extract_struct_value_address): New function, extracted + from the definition of the DEPRECATED_EXTRACT_STRUCT_VALUE_ADDRESS + macro. + (hppa_frame_num_args): New function. + (hppa_gdbarch_init): Setup the gdbarch vector for the hppa target. + + * config/pa/tm-hppa.h: Wrap around all gdbarch-eligible macros + inside "#if !GDB_MULTI_ARCH ... #endif" conditional, in preparation + for the switch to multiarch partial. + Update some of the macros definitions to match some changes + described above in the name of the function they are calling. + (PUSH_DUMMY_FRAME): Add a FIXME explaining why this macro will + not be straightforward to convert. Do now wrap it inside + "#if !... #endif" to remember that this macro has still not + been taken care of. + (FIX_CALL_DUMMY): Likewise. + +2002-12-26 J. Brobecker + + Continuing work to convert the hppa targets to multiarch partial. + + * hppa-tdep.c (hppa_register_raw_size): New function replacing + the body of macro REGISTER_RAW_SIZE. + * hppa-hpux-tdep.c: Add new functions replacing macro bodies from + config/pa/tm-hppah.h. These functions will be used to initialize + the gdbarch structure. + (hppa_hpux_pc_in_sigtramp): New function. + (hppa_hpux_frame_saved_pc_in_sigtramp): New function. + (hppa_hpux_frame_base_before_sigtramp): New function. + (hppa_hpux_frame_find_saved_regs_in_sigtramp): New function. + Add gdbcore.h #include. + * config/pa/tm-hppa.h (REGISTER_RAW_SIZE): Change the definition + of this gdbarch-eligible macro to a call to the new associated + function. + * config/pa/tm-hppah.h (PC_IN_SIGTRAMP): Likewise. + (FRAME_SAVED_PC_IN_SIGTRAMP): Change the definition of this macro + into a call to the new associated function. + (FRAME_BASE_BEFORE_SIGTRAMP): Likewise. + (FRAME_FIND_SAVED_REGS_IN_SIGTRAMP): Likewise. + * Makefile.in (hppa-hpux-tdep.o): Add dependency on gdbcore.h. + +2002-12-24 David Carlton + + * config/sparc/tm-sparc.h: Delete duplicate definition of + DEPRECATED_PC_IN_CALL_DUMMY. + +2002-12-24 Kevin Buettner + + * Makefile.in (mips-linux-tdep.o): Add $(mips_tdep_h) and + $(gdb_assert_h). + * configure.tgt: Recognize mips64*-*-linux*. + * mips-linux-tdep.c (mips-tdep.h, gdb_assert.h): Include. + (supply_32_bit_reg): New function. + (supply_gregset): Call supply_32bit_reg() instead of supply_register(). + (fill_gregset): Use regcache_collect() instead of + deprecated_registers[]. + (register_addr): Change name to mips_linux_register_addr(). + (MIPS64_ELF_NGREG, MIPS64_ELF_NFPREG, MIPS64_FPR_BASE, MIPS64_PC) + (MIPS64_CAUSE, MIPS64_BADVADDR, MIPS64_MMHI, MIPS64_MMLO) + (MIPS64_FPC_CSR, MIPS64_FPC_EIR, MIPS64_EF_REG0, MIPS64_EF_REG31) + (MIPS64_EF_LO, MIPS64_EF_HI, MIPS64_EF_CP0_EPC, MIPS64_EF_CP0_BADVADDR) + (MIPS64_EF_CP0_STATUS, MIPS64_EF_CP0_CAUSE, MIPS64_EF_SIZE) + (MIPS64_LINUX_JB_PC): New defines. + (mips64_elf_greg_t, mips64_elf_gregset_t, mips64_elf_fpreg_t) + (mips64_elf_fpregset_t): New typedefs. + (mips64_linux_get_longhmp_target, mips64_supply_gregset) + (mips64_fill_gregset, mips64_supply_fpregset, mips64_fill_fpregset) + (mips64_linux_register_addr, set_mips_linux_register_addr) + (register_addr, mips64_linux_svr4_fetch_link_map_offsets): + (init_register_addr_data) + New functions. + (fetch_core_registers): Add support for core file formats with 64-bit + registers. + (mips_linux_init_abi): Distinguish o32, n32, and n64 ABIs. + (register_addr_data): New static global variable. + (_initialize_mips_linux_tdep): Initialize register_addr_data. Invoke + gdbarch_register_osabi() for each MIPS machine. + * config/mips/linux64.mt: New file. + * config/mips/tm-linux64.h: New file. + +2002-12-23 Adam Fedor + + * maint.c (maintenance_demangle): Add switch to demangle + ObjC language symbols as well. + +2002-12-23 Adam Fedor + + * objc-lang.c (lookup_objc_class, lookup_child_selector): Remove + last argument from complaint function call. + +2002-12-23 Kevin Buettner + + * exec.c (print_section_info): Add FIXME comments regarding format + string choices. + +2002-12-23 Daniel Jacobowitz + + * config/pa/nm-hppab.h: Delete duplicate CANNOT_STORE_REGISTER decl. + * config/pa/nm-hppao.h: Delete duplicate CANNOT_STORE_REGISTER decl. + +2002-12-23 Rodney Brown + + * config/pa/nm-hppah.h: Delete duplicate CANNOT_STORE_REGISTER decl. + +2002-12-23 David Carlton + + * symtab.c (lookup_symbol_aux): Delete 'force_return' variable. + (lookup_symbol_aux_minsyms): Delete 'force_return' argument. + (search_symbols): Call lookup_symbol_aux_minsyms to find debugging + information associated to a minsym, not lookup_symbol. + +2002-12-21 Mark Kettenis + + * x86-64-tdep.h (x86_64_init_abi): New prototype. + * x86-64-tdep.c (i386_fp_regnum_p): Remove function. + (x86_64_init_abi): Make non-static. Set number of pseudo + registers to 0. + (x86_64_gdbarch_init): Remove function. + (_initialize_x86_64_tdep): Renove register_gdbarch_init call. + Remove code dealing with dissambly. + * x86-64-linux-tdep.c (x86_64_linux_init_abi): New function. + (_initialize_x86_64_linux_tdep): New function. + * config/i386/x86-64linux.mt (TDEPFILES): Add i386-tdep.o and + i386-tdep.o. + +2002-12-14 Mark Kettenis + + * osabi.c: Include "gdb_assert.h" and "gdb_string.h". + (struct gdb_osabi_handler): Remove member `arch'. Add member + `arch_info'. + (gdbarch_register_osabi): Add new argument `machine'. Use ot to + construct a `struct bfd_arch_info' and store it in the `struct + gdb_osabi_handler' that is created. + (gdbarch_init_osabi): Check for compatibility based on machine + type and architecture. + * osabi.h (gdbarch_register_osabi): Adjust prototype and update + comment. + * alpha-linux-tdep.c (_initialize_alpha_linux_tdep): Add 0 as + second argument in call to gdbarch_register_osabi. + * alpha-osf1-tdep.c (_initialize_alpha_osf1_tdep): Likewise. + * alphafbsd-tdep.c (_initialize_alphafbsd_tdep): Likewise. + * alphanbsd-tdep.c (_initialize_alphanbsd_tdep): Likewise. + * arm-linux-tdep.c (_initialize_arm_linux_tdep): Likewise. + * arm-tdep.c (_initialize_arm_tdep): Likewise. + * armnbsd-tdep.c (_initialize_armnbsd_tdep): Likewise. + * hppa-hpux-tdep.c (_initialize_hppa_hpux_tdep): Likewise. + * i386-interix-tdep.c (_initialize_i386_interix_tdep): Likewise. + * i386-linux-tdep.c (_initialize_i386_linux_tdep): Likewise. + * i386-sol2-tdep.c (_initialize_i386_sol2_tdep): Likewise. + * i386-tdep.c (_initialize_i386_tdep): Likewise. + * i386bsd-tdep.c (_initialize_i386bsd_tdep): Likewise. + * i386gnu-tdep.c (_initialize_i386gnu_tdep): Likewise. + * i386ly-tdep.c (_initialize_i386lynx_tdep): Renamed from + _initialize_i386bsd_tdep and updated likewise. + * i386nbsd-tdep.c (_initialize_i386nbsd_tdep): Likewise. + * i386obsd-tdep.c (_initialize_i386obsd_tdep): Likewise. + * mips-irix-tdep.c (_initialize_mips_irix_tdep): Likewise. + * mips-linux-tdep.c (_initialize_mips_linux_tdep): Likewise. + * mipsnbsd-tdep.c (_initialize_mipsnbsd__tdep): Likewise. + * ns32knbsd-tdep.c (_initialize_ns32kmnsd_tdep): Likewise. + * ppc-linux-tdep.c (_initialize_ppc_linux_tdep): Likewise. + * ppcnbsd-tdep.c (_initialize_ppcnbsd_tdep): Likewise. + * shnbsd-tdep.c (_initialize_shnbsd_tdep): Likewise. + * sparcnbsd-tdep.c (_initialize_sparcnbsd_tdep): Likewise. + +2002-12-20 Kevin Buettner + + * solib-svr4.c (elf_locate_base): Fix sizeof() related bug. Add + DT_MIPS_RLD_MAP case for 64-bit targets. + +2002-12-20 Kevin Buettner + + * mips-tdep.c (heuristic_proc_desc): Clear memory associated with + ``temp_saved_regs'', not the pointer or other storage contiguous + to this pointer. + +2002-12-20 Kevin Buettner + + * Makefile.in (mips-linux-tdep.o): Add $(osabi_h) and $(gdb_string_h). + * config/mips/tm-linux.h (mips_linux_svr4_fetch_link_map_offsets) + (mips_linux_get_longjmp_target): Delete declarations. + (SVR4_FETCH_LINK_MAP_OFFSETS, GET_LONGJMP_TARGET) + (MIPS_LINUX_JB_ELEMENT_SIZE, MIPS_LINUX_JB_PC): Delete definitions. + * mips-linux-tdep.c (osabi.h, gdb_string.h): Include. + (MIPS_LINUX_JB_ELEMENT_SIZE, MIPS_LINUX_JB_PC): Define. + (mips_linux_get_longjmp_target) + (mips_linux_svr4_fetch_link_map_offsets): Make static. + (mips_linux_init_abi): New function. + (_initialize_mips_linux_tdep): Register mips_linux_init_abi(). + +2002-12-19 Keith Seitz + + patch committed by Elena Zannoni + * thread.c (do_captured_list_thread_ids): Call prune_threads and + target_find_new_threads. Fix for PR mi/669. + +2002-12-19 David Carlton + + * linespec.c (decode_line_1): Move code into decode_all_digits. + (decode_all_digits): New function. + +2002-12-19 Kevin Buettner + + * exec.c (print_section_info): Select a format string to use with + local_hex_string_custom() based upon the value of TARGET_ADDR_BIT. + +2002-12-18 Andrew Cagney + + * frame.c (deprecated_update_current_frame_pc_hack): Replace + deprecated_update_current_frame_pc_hack. + (deprecated_update_frame_base_hack): New function. + * frame.h (deprecated_update_frame_pc_hack): Replace + (deprecated_update_frame_base_hack): Declare. + * infrun.c (normal_stop): Update. + +2002-12-18 Andrew Cagney + + * rs6000-tdep.c (rs6000_init_extra_frame_info): Use + frame_extra_info_zalloc. + (rs6000_frame_args_address): Use get_frame_extra_info. + (frame_get_saved_regs): Use get_frame_saved_regs. + (frame_initial_stack_address): Use get_frame_saved_regs and + get_frame_extra_info. + (frame_initial_stack_address): Use get_frame_extra_info. + +2002-12-17 Kevin Buettner + + * dve3900-rom.c (r3900_regnames): Don't use NUM_REGS to determine + array size. + (fetch_bitmapped_register, store_bitmapped_register): Add bounds + checks for r3900_regnames[]. + +2002-12-17 Richard Earnshaw + + * armnbsd-tdep.c (ARM_NBSD_JB_PC): Renamed from JB_PC. + All uses changed + (ARM_NBSD_JB_ELELMENT_SIZE): Similarly. + +2002-12-17 David Carlton + + * symtab.c (lookup_partial_symbol): Don't search past the end of + the partial symbols. + +2002-12-17 Andrew Cagney + + * stack.c (frame_info): Use get_frame_saved_regs. + * breakpoint.c (until_break_command): Use get_frame_pc. + +2002-12-16 Kevin Buettner + + * buildsym.c (block_end_complaint, anon_block_end_complaint) + (innerblock_complaint, innerblock_anon_complaint) + (blockvector_complaint): Delete deprecated complaint structs. + (finish_block, make_blockvector, end_symtab): Replace calls + to complain() with calls to complaint(). + * coffread.c (ef_complaint, ef_stack_complaint, eb_stack_complaint) + (bf_no_aux_complaint, ef_no_aux_complaint, lineno_complaint) + (unexpected_type_complaint, bad_sclass_complaint) + (misordered_blocks_complaint, tagndx_bad_complaint, eb_complaint): + Delete deprecated complaint structs. + (coff_symtab_read, enter_linenos, decode_type, decode_base_type): + Replace calls to complain() with calls to complaint(). + * dbxread.c (lbrac_complaint, string_table_offset_complaint) + (unknown_symtype_complaint, unknown_symchar_complaint) + (lbrac_rbrac_complaint, lbrac_unmatched_complaint) + (lbrac_mismatch_complaint, repeated_header_complaint) + (unclaimed_bincl_complaint, discarding_local_symbols_complaint): + Delete deprecated complaint structs. + (unknown_symtype_complaint, lbrac_mismatch_complaint) + (repeated_header_complaint) + (function_outside_compiliation_unit_complaint): New functions. + (add_old_header_file, find_corresponding_bincl_psymtab) + (set_namestring, find_stab_function_addr, read_dbx_symtab) + (process_one_symbol): Replace calls to complain() with, possibly + indirect, calls to complaint(). + * dwarfread.c (no_bfd_get_N, malformed_die, bad_die_ref) + (unknown_attribute_form, unknown_attribute_length) + (unexpected_fund_type, unknown_type_modifier, volatile_ignored) + (const_ignored, botched_modified_type, op_deref2, op_deref4) + (basereg_not_handled, dup_user_type_allocation) + (dup_user_type_definition, missing_tag, bad_array_element_type) + (subscript_data_items, unhandled_array_subscript_format) + (unknown_array_subscript_format, not_row_major) + (missing_at_name): Delete deprecated complaint structs. + (bad_die_ref_complaint, unknown_attribute_form_complaint) + (dup_user_type_definition_complaint) + (bad_array_element_type_complaint): New functions. + (lookup_utype, alloc_utype, struct_type, decode_array_element_type) + (decode_subscript_data_item, dwarf_read_array_type) + (read_tag_string_type, read_subroutine_type, read_func_scope) + (locval, scan_partial_symbols, decode_modified_type) + (decode_func_type, basicdieinfo, completeddieinfo, target_to_host) + (attribute_size): Replace calls to complain() with, possibly + indirect, calls to complaint(). + * elfread.c (section_info_complaint, section_info_dup_complaint) + (stab_info_mismatch_complaint, stab_info_questionable_complaint): + Delete deprecated complaint structs. + (elf_symtab_read, elfstab_offset_sections): Replace calls to + complain() with calls to complaint(). + * gdbtypes.c (stub_noname_complaint): Delete deprecated complaint + struct. + (stub_noname_complaint): New function. + (check_typedef, add_mangled_type): Replace calls to complain() + with calls to complaint(). + * hpread.c (string_table_offset_complaint, lbrac_unmatched_complaint) + (lbrac_mismatch_complaint, hpread_unhandled_end_common_complaint) + (hpread_unhandled_type_complaint, hpread_struct_complaint) + (hpread_array_complaint, hpread_type_lookup_complaint) + (hpread_unexpected_end_complaint, hpread_tagdef_complaint) + (hpread_unhandled_common_complaint) + (hpread_unhandled_blockdata_complaint): Delete deprecated complaint + struct definitions and declarations. + (lbrac_unmatched_complaint, lbrac_mismatch_complaint): New functions. + (SET_NAMESTRING, hpread_type_lookup, hpread_process_one_debug_symbol): + Replace calls to complain() with, possibly indirect, calls to + complaint(). + * macrotab.c (macro_include, check_for_redefinition, macro_undef): + Likewise. + * mdebugread.c (bad_file_number_complaint, index_complaint) + (aux_index_complaint, block_index_complaint) + (unknown_ext_complaint, unknown_sym_complaint) + (unknown_st_complaint, block_overflow_complaint) + (basic_type_complaint, unknown_type_qual_complaint) + (array_index_type_complaint, bad_tag_guess_complaint) + (block_member_complaint, stEnd_complaint) + (unknown_mdebug_symtype_complaint, stab_unknown_complaint) + (pdr_for_nonsymbol_complaint, pdr_static_symbol_complaint) + (bad_setjmp_pdr_complaint, bad_fbitfield_complaint) + (bad_continued_complaint, bad_rfd_entry_complaint) + (unexpected_type_code_complaint, unable_to_cross_ref_complaint) + (bad_indirect_xref_complaint, illegal_forward_tq0_complaint) + (illegal_forward_bt_complaint, bad_linetable_guess_complaint) + (bad_ext_ifd_complaint, bad_ext_iss_complaint): Delete deprecated + complaint structs. + (index_complaint, unknown_ext_complaint, basic_type_complaint) + (bad_tag_guess_complaint, bad_rfd_entry_complaint) + (unexpected_type_code_complaint) + (function_outside_compilation_unit_complaint): New functions. + (parse_symbol, parse_type, upgrade_type, parse_procedure) + (parse_partial_symbols, psymtab_to_symtab_1, cross_ref, add_symbol): + Replace calls to complain() with, possibly indirect calls to + complaint(). + * objc-lang.c (noclass_lookup_complaint, nosel_lookup_complaint): + Delete deprecated complaint structs. + (lookup__objc_class, lookup_child_selector): Replace complain() + with complaint(). + * remote-vx.c (cant_contact_target): Delete deprecated complaint + struct. + (vx_lookup_symbol): Replace complain() with complaint(). + * stabsread.c (invalid_cpp_abbrev_complaint) + (invalid_cpp_type_complaint, member_fn_complaint) + (const_vol_complaint, error_type_complaint) + (invalid_member_complaint, range_type_base_complaint) + (reg_value_complaint, vtbl_notfound_complaint) + (unrecognized_cplus_name_complaint, rs6000_builtin_complaint) + (unresolved_sym_chain_complaint, stabs_general_complaint) + (lrs_general_complaint, multiply_defined_struct): Delete + deprecated complaint structs. + (invalid_cpp_abbrev_complaint, ref_value_complaint) + (stabs_general_complaint, lrs_general_complaint) + (msg_unknown_complaint): New functions. + (dbx_lookup_type, read_cfront_baseclasses) + (read_cfront_member_functions, resolve_symbol_reference) + (define_symbol, resolve_live_range, add_live_range, read_type) + (rs6000_builtin_type, read_member_functions, read_cpp_abbrev) + (read_one_struct_field, read_baseclasses, read_tilde_fields) + (read_cfront_static_fields, attach_fields_to_type) + (complain_about_struct_wipeout, read_range_type) + (common_block_start, common_block_end, cleanup_undefined_types) + (scan_file_globals): Replace complain() with complaint(). + * stabsread.h (unknown_symtype_complaint, unknown_symchar_complaint): + Delete deprecated complaint struct declarations. + * xcoffread.c (storclass_complaint, bf_notfound_complaint) + (ef_complaint, eb_complaint): Delete deprecated complaint structs. + (bf_not_found_complaint, ef_complaint, eb_complaint) + (function_outside_compilation_unit_complaint): New functions. + (record_include_begin, record_include_end, enter_line_range) + (xcoff_next_symbol_text, read_xcoff_symtab, process_xcoff_symbol) + (read_symbol, read_symbol_lineno, scan_xcoff_symtab) Replace + complain() with complaint(). + +2002-12-16 Andrew Cagney + + * config/arc/arc.mt, config/arc/tm-arc.h: Delete. + * config/d30v/d30v.mt, config/d30v/tm-d30v.h: Delete. + * config/fr30/fr30.mt, config/fr30/tm-fr30.h: Delete. + * config/i386/i386aix.mh, config/i386/i386aix.mt: Delete. + * config/i386/i386m3.mh, config/i386/i386m3.mt: Delete. + * config/i386/i386mach.mh, config/i386/i386os9k.mt: Delete. + * config/i386/nm-i386aix.h, config/i386/nm-i386mach.h: Delete. + * config/i386/nm-m3.h, config/i386/tm-i386aix.h: Delete. + * config/i386/tm-i386m3.h, config/i386/tm-i386mk.h: Delete. + * config/i386/xm-i386aix.h, config/i386/xm-i386m3.h: Delete. + * config/i386/xm-i386mach.h, config/i386/xm-i386mk.h: Delete. + * config/i960/mon960.mt, config/i960/nindy960.mt: Delete. + * config/i960/tm-i960.h, config/i960/tm-mon960.h: Delete. + * config/i960/tm-nindy960.h, config/i960/tm-vx960.h: Delete. + * config/i960/vxworks960.mt, config/m68k/apollo68b.mh: Delete. + * config/m68k/apollo68b.mt, config/m68k/apollo68v.mh: Delete. + * config/m68k/hp300bsd.mh, config/m68k/hp300bsd.mt: Delete. + * config/m68k/hp300hpux.mh, config/m68k/hp300hpux.mt: Delete. + * config/m88k/delta88.mh, config/m88k/delta88.mt: Delete. + * config/m88k/delta88v4.mh, config/m88k/delta88v4.mt: Delete. + * config/m88k/m88k.mh, config/m88k/m88k.mt: Delete. + * config/m88k/nm-delta88v4.h, config/m88k/nm-m88k.h: Delete. + * config/m88k/tm-delta88.h, config/m88k/tm-delta88v4.h: Delete. + * config/m88k/tm-m88k.h, config/m88k/xm-delta88.h: Delete. + * config/m88k/xm-dgux.h: Delete. + * fr30-tdep.c, i386aix-nat.c, i386m3-nat.c: Delete. + * i386mach-nat.c, i960-tdep.c, m88k-nat.c: Delete. + * os9kread.c, remote-bug.c, remote-nindy.c: Delete. + * remote-nrom.c, remote-os9k.c, remote-vx960.c: Delete. + * d30v-tdep.c, arc-tdep.c, cxux-nat.c, dst.h, dstread.c: Delete. + * ch-exp.c, ch-lang.c, ch-lang.h, ch-typeprint.c: Delete. + * ch-valprint.c: Delete. + +2002-12-15 Daniel Jacobowitz + + * infrun.c (handle_inferior_event): Rearrange code to resume if + no catchpoint triggers for an event. + +2002-12-15 Daniel Jacobowitz + + * infrun.c (handle_inferior_event): Merge TARGET_WAITKIND_FORKED + and TARGET_WAITKIND_VFORKED cases. + +2002-12-15 Daniel Jacobowitz + + * infrun.c (handle_inferior_event): Assume that catchpoints + are not affected by DECR_PC_AFTER_BREAK. + +2002-12-15 Daniel Jacobowitz + + * target.c (update_current_target): Don't inherit DONT_USE. + * target.h (struct target_ops): Remove DONT_USE. + (target_next): Remove macro. + +2002-12-15 Mark Kettenis + + * ui-out.c (MAX_UI_OUT_LEVELS): Raise to 6. Fixes PR cli/654. + +2002-12-14 Richard Earnshaw + + * arm-tdep.c (convert_from_extended): New argument to hold the + type of floating point result we want to convert to. Make input + argument const. Fix all callers. + (convert_to_extended): Similarly. + (arm_extract_return_value): Now takes a regcache argument. Change + code to use regcache accessor functions. Correctly extract + smaller-than-word results on big-endian machines. + (arm_store_return_value): Now takes a regcache argument. Change + code to use regcache accessor functions. Correctly zero/sign extend + smaller than word results before storing into r0. + (arm_gdbarch_init): Register new-style extract_return_value and + store_return_value functions. + +2002-12-13 Michael Snyder + + * thread-db.c (thread_from_lwp): Uniquify error msg. + (lwp_from_thread): Ditto. + (check_event): Ditto. + (find_new_threads_callback): Ditto. + (thread_db_pid_to_str): Ditto. + +2002-12-13 Andrew Cagney + + * frame.h (get_frame_saved_regs): Declare. + (frame_saved_regs_zalloc): Change return type to CORE_ADDR + pointer. + * frame.c (get_frame_saved_regs): New function. + (frame_saved_regs_zalloc): Return the allocated saved_regs. + +2002-12-13 Andrew Cagney + + * frame.c (deprecated_update_current_frame_pc_hack): New + function. + * frame.h (deprecated_update_current_frame_pc_hack): Declare. + * infrun.c (normal_stop): Use said function instead of directly + modifying the frame's PC. + +2002-12-13 Alexandre Oliva + + * frame.h (frame_id_unwind_ftype): Fix typo in return type. + +2002-12-13 Kevin Buettner + + * config/mips/tm-mips.h, config/mips/tm-irix3.h, + config/mips/tm-irix6.h (NUM_REGS): Delete. + * mips-tdep.c (mips_gdbarch_init): Call set_gdbarch_num_regs(). + (temp_saved_regs): Declare as a pointer rather than an array. + (mips32_heuristic_proc_desc, heuristic_proc_desc): Make sure + that ``temp_saved_regs'' has storage allocated to it and that + it's the correct size. + +2002-12-13 Jeff Johnston + + * defs.h (init_last_source_visited): New prototype. + (add_path): Ditto. + * source.c (add_path): New function that adds to a specified path. + (mod_path): Change to call add_path. + (init_last_source_visited): New function to allow interfaces to + initialize static variable: last_source_visited. Part of fix + for PR gdb/741. + * Makefile.in: Add support for mi/mi-cmd-env.c. + +2002-12-13 Andrew Cagney + + * frame.h (frame_id_unwind): Declare. + (struct frame_info): Add fields id_unwind, id_unwind_cache_p and + id_unwind_cache. + (frame_id_unwind_ftype): Declare. + * frame.c (frame_id_unwind): New function. + (set_unwind_by_pc): Add unwind_id parameter. Initialized. + (create_new_frame, get_prev_frame): Pass id_unwind to + set_unwind_by_pc. + (frame_saved_regs_id_unwind): New function. + (frame_saved_regs_id_unwind): New function. + * dummy-frame.c (dummy_frame_id_unwind): New function. + (struct dummy_frame): Add field id. + (generic_push_dummy_frame): Initialize `id'. + * dummy-frame.h (dummy_frame_id_unwind): Declare. + +2002-12-13 Andrew Cagney + + * infcmd.c (run_stack_dummy): Create a frame ID directly and then + pass that to set_momentary_breakpoint. Move comments to where they + belong. + * frame.h (set_current_frame): Delete declaration. + * frame.c (set_current_frame): Delete function. + +2002-12-13 Andrew Cagney + + * frame.c (frame_extra_info_zalloc): New function. + * frame.h (frame_extra_info_zalloc): Declare. + +2002-12-13 Joel Brobecker + + * hppa-tdep.c (hppa_pop_frame): Fix a compilation error introduced + in the previous prototype change to set_momentary_breakpoint. + +2002-12-12 Daniel Jacobowitz + + * infrun.c (pending_follow): Remove saw_parent_fork, saw_child_fork, + and saw_child_exec. + (follow_fork, init_wait_for_inferior, handle_inferior_event): Remove + references to saw_parent_fork, saw_child_fork, and saw_child_exec. + (stop_stepping): Remove outdated check for child vfork events. + +2002-12-12 Andrew Cagney + + * GDB 5.3 released from gdb_5_3-branch. + +2002-12-11 Daniel Jacobowitz + + * corelow.c (init_core_ops): Delete references to to_require_attach + and to_require_detach. + * exec.c (init_exec_ops): Likewise. + * hppah-nat.c (child_follow_fork): Call hppa_require_attach and + hppa_require_detach directly. + * inferior.h (REQUIRE_ATTACH, REQUIRE_DETACH): Delete. + * inftarg.c (child_detach): Remove. + (child_detach_from_process): Rename to child_detach, remove + after_fork argument. + (child_attach): Remove. + (child_attach_to_process): Rename to child_attach, remove after_fork + argument. + (init_child_ops): Delete references to to_require_attach + and to_require_detach. + * infttrace.c (hppa_require_attach): Update comment. + * target.c (cleanup_target, update_current_target) + (init_dummy_target, setup_target_debug): Delete references to + to_require_attach and to_require_detach. + (find_default_require_detach, find_default_require_attach) + (debug_to_require_attach, debug_to_require_detach): Remove + functions. + * target.h (struct target_ops): Remove to_require_attach + and to_require_detach. + (target_require_attach, target_require_detach): Delete macros. + (find_default_require_detach, find_default_require_attach): Delete + prototypes. + * config/pa/nm-hppah.h (REQUIRE_ATTACH, REQUIRE_DETACH): Delete. + +2002-12-11 Andrew Cagney + + * frame.c (get_frame_extra_info): New function. + * frame.h (get_frame_extra_info): Declare. + +2002-12-11 Andrew Cagney + + * breakpoint.h (struct breakpoint): Replace frame with frame_id. + (set_momentary_breaokpoint): Replace `struct frame_info' parameter + with `struct frame_id'. + (set_longjmp_resume_breakpoint): Ditto. + * infrun.c (handle_inferior_event): Update. + * breakpoint.c (watch_command_1, until_break_command): Update. + * infrun.c (handle_inferior_event, check_sigtramp2): Update. + (handle_inferior_event, step_over_function): Update. + * breakpoint.c (bpstat_stop_status, print_one_breakpoint): Update. + (set_raw_breakpoint, set_longjmp_resume_breakpoint): Update. + (set_momentary_breakpoint, deprecated_frame_in_dummy): Update. + * infcmd.c (finish_command, run_stack_dummy): Update. + +2002-12-11 Kevin Buettner + + * dwarf2read.c (dwarf2_const_ignored, dwarf2_volatile_ignored) + (dwarf2_non_const_array_bound_ignored) + (dwarf2_missing_line_number_section) + (dwarf2_statement_list_fits_in_line_number_section) + (dwarf2_mangled_line_number_section, dwarf2_unsupported_die_ref_attr) + (dwarf2_unsupported_stack_op, dwarf2_complex_location_expr) + (dwarf2_unsupported_tag, dwarf2_unsupported_at_encoding) + (dwarf2_unsupported_at_frame_base, dwarf2_unexpected_tag) + (dwarf2_missing_at_frame_base, dwarf2_bad_static_member_name) + (dwarf2_unsupported_accessibility, dwarf2_bad_member_name_complaint) + (dwarf2_missing_member_fn_type_complaint) + (dwarf2_vtbl_not_found_complaint, dwarf2_absolute_sibling_complaint) + (dwarf2_const_value_length_mismatch) + (dwarf2_unsupported_const_value_attr, dwarf2_misplaced_line_number) + (dwarf2_line_header_too_long, dwarf2_missing_macinfo_section) + (dwarf2_macros_too_long, dwarf2_macros_not_terminated) + (dwarf2_macro_outside_file, dwarf2_macro_unmatched_end_file) + (dwarf2_macro_malformed_definition, dwarf2_macro_spaces_in_definition) + (dwarf2_invalid_attrib_class, dwarf2_invalid_pointer_size): Delete + complaints using deprecated struct.. + (dwarf2_non_const_array_bound_ignored_complaint) + (dwarf2_complex_location_expr_complaint) + (dwarf2_unsupported_at_frame_base_complaint) + (dwarf2_const_value_length_mismatch_complaint) + (dwarf2_macros_too_long_complaint) + (dwarf2_macro_malformed_definition_complaint) + (dwarf2_invalid_attrib_class_complaint): New functions. + (read_func_scope, dwarf2_attach_fields_to_type, dwarf2_add_member_fn) + (read_structure_scope, read_array_type, read_common_block) + (read_tag_pointer_type, read_base_type, read_partial_die) + (dwarf_decode_line_header, check_cu_functions, dwarf_decode_lines) + (new_symbol, dwarf2_const_value, read_type_die) + (dwarf2_get_ref_die_offset, decode_locdesc, consume_improper_spaces) + (parse_macro_definition, dwarf_decode_macros): Replace calls to + complain() with, possibly indirect, calls to complaint(). + +2002-12-11 Andrew Cagney + + * frame.c (deprecated_get_frame_saved_regs): Rename + get_frame_saved_regs. + * frame.h (deprecated_get_frame_saved_regs): Update declaration. + * sparc-tdep.c: Update. + * hppa-tdep.c: Update. + * h8500-tdep.c: Update. + +2002-12-11 Kevin Buettner + + * gdbarch.sh (ADDRESS_CLASS_TYPE_FLAGS_TO_NAME) + (ADDRESS_CLASS_NAME_TO_TYPE_FLAGS): Use ``const char *'' instead of + ``char *'' for return and parameter types. + * gdbarch.h, gdbarch.c: Regenerate. + * gdbtypes.h, gdbtypes.c (address_space_int_to_name): Change + return type from ``char *'' to ``const char *''. + * c-typeprint.c (c_type_print_modifier): Make ``address_space_id'' + const. + +2002-12-11 Mark Kettenis + + * i386-tdep.c: Include "dummy-frame.h". + (i386_frame_chain, i386_frame_saved_pc): Replace + DEPRECATED_PC_IN_CALL_DUMMY with call to pc_in_dummy_frame. + (i386_gdbarch_init): Don't set deprecated_pc_in_call_dummy. + +2002-12-10 Andrew Cagney + + * gdbarch.sh (DEPRECATED_INIT_FRAME_PC): Rename INIT_FRAME_PC. + Change to a function with predicate. + * gdbarch.h, gdbarch.c: Re-generate. + * frame.c (get_prev_frame): Update. Test + DEPRECATED_INIT_FRAME_PC_P. + * config/sparc/tm-sparc.h (DEPRECATED_INIT_FRAME_PC): Update. + * config/rs6000/tm-rs6000.h (DEPRECATED_INIT_FRAME_PC): Update. + * config/mn10200/tm-mn10200.h (DEPRECATED_INIT_FRAME_PC): Update. + * alpha-tdep.c (alpha_gdbarch_init): Update. + * mn10300-tdep.c (mn10300_gdbarch_init): Update. + * mips-tdep.c (mips_gdbarch_init): Update. + * i386-interix-tdep.c (i386_interix_init_abi): Update. + * arm-tdep.c: Update comments. + * h8300-tdep.c (h8300_gdbarch_init): Explicitly set init_frame_pc. + * config/m32r/tm-m32r.h (DEPRECATED_INIT_FRAME_PC): Ditto. + * frv-tdep.c (frv_gdbarch_init): Ditto. + * x86-64-tdep.c (x86_64_init_abi): Ditto. + * ia64-tdep.c (ia64_gdbarch_init): Ditto. + * s390-tdep.c (s390_gdbarch_init): Ditto. + * v850-tdep.c (v850_gdbarch_init): Ditto. + * vax-tdep.c (vax_gdbarch_init): Ditto. + * sh-tdep.c (sh_gdbarch_init): Ditto. + * ns32k-tdep.c (ns32k_gdbarch_init): Ditto. + * m68hc11-tdep.c (m68hc11_gdbarch_init): Ditto. + * mcore-tdep.c (mcore_gdbarch_init): Ditto. + * xstormy16-tdep.c (xstormy16_gdbarch_init): Ditto. + * i386-tdep.c (i386_gdbarch_init): Ditto. + * d10v-tdep.c (d10v_gdbarch_init): Ditto. + * cris-tdep.c (cris_gdbarch_init): Ditto. + * avr-tdep.c (avr_gdbarch_init): Ditto. + * arm-tdep.c (arm_gdbarch_init): Ditto. + * config/z8k/tm-z8k.h (INIT_FRAME_PC_FIRST): Delete macro. + (DEPRECATED_INIT_FRAME_PC): Rename INIT_FRAME_PC. + +2002-12-10 Daniel Jacobowitz + + * config/pa/nm-hppah.h (CHILD_POST_FOLLOW_VFORK): Change to + CHILD_FOLLOW_FORK. + * hppah-nat.c (saved_vfork_pid): Add. + (child_post_follow_vfork): Remove. + (child_follow_fork): New function. + (child_wait): Call detach_breakpoints after receiving the child vfork. + Call child_resume directly instead of going through resume (). + Make sure we have the exec before reporting the vfork. + * inferior.h (follow_inferior_reset_breakpoints): Add prototype. + * infrun.c (follow_fork, follow_vfork, follow_inferior_fork): Remove. + (follow_fork): New function. Call target_follow_fork. + (follow_inferior_reset_breakpoints): New function broken out from + old follow_inferior_fork. + (resume): Remove hack to follow exec after vfork. + * inftarg.c (child_post_follow_vfork): Remove. + (child_follow_fork): New function. + (init_child_ops): Replace to_post_follow_vfork with to_follow_fork. + * target.c (cleanup_target): Replace to_post_follow_vfork with + to_follow_fork. + (update_current_target): Likewise. + (setup_target_debug): Likewise. + (debug_to_post_follow_vfork): Remove. + (debug_to_follow_fork): New function. + * target.h (struct target_ops): Replace to_post_folow_vfork with + to_follow_fork. + (child_post_follow_vfork): Remove prototype. + (child_follow_fork): Add prototype. + (target_post_follow_vfork): Remove macro. + (target_follow_fork): Add macro. + +2002-12-10 Daniel Jacobowitz + + * hppah-nat.c (saved_child_execd_pathname, saved_vfork_state): New. + (child_post_follow_vfork): Cancel pending exec event if we follow + the parent. + (child_wait): Only return TARGET_WAITKIND_VFORKED when all necessary + events have been processed. Return a fake TARGET_WAITKIND_EXECD + event at the following wait call if necessary. + * infrun.c (follow_vfork): Don't follow_exec here. + (handle_inferior_event): Add comment to TARGET_WAITKIND_EXECD + case about HP/UX 10.20. Remove code pushed down to + hppah-nat.c:child_wait. + * infttrace.c (child_resume): Use TT_PROC_CONTINUE if + vfork_in_flight is set. + +2002-12-10 Daniel Jacobowitz + + * hppah-nat.c (child_wait): Return TARGET_WAITKIND_IGNORE + for the parent's fork event. + * infrun.c (handle_inferior_event): Only expect one fork event. + Call prepare_to_wait for TARGET_WAITKIND_IGNORE. Update comment. + * target.h: Update comment for TARGET_WAITKIND_IGNORE. + +2002-12-10 Andrew Cagney + + * PROBLEMS: Delete reference to PR gdb/725. + + * MAINTAINERS (gdb.c++): Add David Carlton. + +2002-12-09 David Carlton + + * cli/cli-setshow.c: #include after defs.h. + * cli/cli-cmds.c: Ditto. + +2002-12-09 Andrew Cagney + + * gdbarch.sh (gdbarch_dump): Print NAME_OF_MALLOC using %s. Wrap + function address in <>. + * gdbarch.c: Re-generate. + +2002-12-09 David Carlton + + * p-exp.y: Rename TRUE and FALSE to TRUEKEYWORD and FALSEKEYWORD. + +2002-12-09 David Carlton + + * linespec.c (symtab_from_filename): New function. + (decode_line_1): Move code into symtab_from_filename. + +2002-12-09 Kevin Buettner + + * lin-lwp.c (strsignal): Make extern declaration match that of glibc. + +2002-12-07 Andrew Cagney + + * f-valprint.c (info_common_command): Use get_frame_pc. + * std-regs.c (value_of_builtin_frame_pc_reg): Ditto. + * ax-gdb.c (agent_command): Ditto. + * rs6000-tdep.c (rs6000_init_extra_frame_info): Ditto. + (rs6000_pop_frame): Ditto. + (rs6000_frameless_function_invocation): Ditto. + (rs6000_frame_saved_pc, frame_get_saved_regs): Ditto. + (frame_initial_stack_address, rs6000_frame_chain): Ditto. + * macroscope.c (default_macro_scope): Ditto. + * stack.c (print_frame_info_base): Ditto. + (print_frame, frame_info, print_frame_label_vars): Ditto. + (return_command, func_command, get_frame_language): Ditto. + * infcmd.c (finish_command): Ditto. + * dummy-frame.c (cached_find_dummy_frame): Ditto. + * breakpoint.c (deprecated_frame_in_dummy): Ditto. + (break_at_finish_at_depth_command_1): Ditto. + (break_at_finish_command_1): Ditto. + (until_break_command, get_catch_sals): Ditto. + * blockframe.c (func_frame_chain_valid): Ditto. + (frameless_look_for_prologue): Ditto. + (frame_address_in_block, generic_func_frame_chain_valid): Ditto. + +2002-12-08 Andrew Cagney + + * config/rs6000/tm-rs6000.h (init_frame_pc_noop): Add declaration. + * dwarf2cfi.c (cfi_init_frame_pc): Cast the PC to a pointer. + +2002-12-08 Andrew Cagney + + * gdbarch.sh (INIT_FRAME_PC_FIRST, INIT_FRAME_PC_DEFAULT): Convert + to pure functions. + * gdbarch.h, gdbarch.c: Re-generate. + * frame.c (get_prev_frame): Explictly assign prev's pc with value + returned by INIT_FRAME_PC_FIRST and INIT_EXTRA_FRAME_INFO. + + * arch-utils.h (init_frame_pc_default, init_frame_pc_noop): Change + declaration to a function returning a CORE_ADDR. + * x86-64-tdep.h (x86_64_init_frame_pc): Ditto. + * arch-utils.c (init_frame_pc_noop): Return the PC value. + (init_frame_pc_default): Ditto. + * x86-64-linux-tdep.c (x86_64_init_frame_pc): Ditto. + * s390-tdep.c (s390_init_frame_pc_first): Ditto. + * mips-tdep.c (mips_init_frame_pc_first): Ditto. + * dwarf2cfi.h (cfi_init_frame_pc): Ditto. + * dwarf2cfi.c (cfi_init_frame_pc): Ditto. + * alpha-tdep.c (alpha_init_frame_pc_first): Ditto. + + * i386-interix-tdep.c (i386_interix_init_abi): Set init_frame_pc + to init_frame_pc_noop. + (i386_interix_init_frame_pc): Delete function. + * z8k-tdep.c (init_frame_pc): Delete function. + * config/z8k/tm-z8k.h (INIT_FRAME_PC): Define as init_frame_pc_noop. + (INIT_FRAME_PC_FIRST): Ditto. + * config/mn10200/tm-mn10200.h (INIT_FRAME_PC): Ditto. + (INIT_FRAME_PC_FIRST): Ditto. + * config/sparc/tm-sparc.h (INIT_FRAME_PC): Ditto. + * config/rs6000/tm-rs6000.h (INIT_FRAME_PC): Redefine as + init_frame_pc_noop. + (INIT_FRAME_PC_FIRST): Convert to an expression. + * config/sparc/tm-sparc.h (INIT_FRAME_PC_FIRST): Ditto. + +2002-12-08 Andrew Cagney + + * blockframe.c: Use get_frame_base instead of directly accessing + the `struct frame_info' member frame. + * f-valprint.c, std-regs.c, rs6000-tdep.c: Ditto. + * stack.c, dummy-frame.c, breakpoint.c: Ditto. + +2002-12-08 Elena Zannoni + + * Makefile.in (readline_h): Define. + (completer.o): Depend on readline_h. + (corelow.o): Ditto. + (event-top.o): Ditto. + (exec.o): Ditto. + (solib.o): Ditto. + (source.o): Ditto. + (symfile.o): Ditto. + (symmisc.o): Ditto. + (top.o): Ditto. + (tracepoint.o): Ditto. + (utils.o): Ditto. + (cli-dump.o): Ditto. + (tui-hooks.o): Ditto. + (tuiWin.o): Ditto. + +2002-12-08 Elena Zannoni + + More cleanup from import of readline 4.3. + * completer.h (complete_line, readline_line_completion_function): + Update prototypes. + (line_completion_function): Removed, not used outside of completer.c. + * completer.c (readline_line_completion_function, + complete_function, line_completion_function): Use const for first + parameter. + (line_completion_function): Make static. + (filename_completer): filename_completion_function is now called + rl_filename_completion_function + * corelow.c: Include . + * exec.c: Ditto. + * solib.c: Ditto. + * source.c: Ditto. + * symfile.c: Ditto. + * symmisc.c: Ditto. + * top.c (init_main): No need to coerce + readline_line_completion_function anymore. + * cli/cli-dump.c: Include . + +2002-12-08 Andrew Cagney + + * stack.c (frame_info): Use get_prev_frame. + * blockframe.c (frame_address_in_block): Ditto. + * rs6000-tdep.c (rs6000_init_extra_frame_info): Ditto. + (rs6000_frameless_function_invocation): Ditto. + (rs6000_frame_saved_pc): Ditto. + (rs6000_frame_chain): Ditto. + * arch-utils.c (init_frame_pc_default): Ditto. + +2002-12-08 Andrew Cagney + + * config/mn10200/tm-mn10200.h (DEPRECATED_PC_IN_CALL_DUMMY): + Delete redundant definition. + +2002-12-08 Elena Zannoni + + Import of readline 4.3: + * cli/cli-cmds.c: Include readline/tilde.h. + * cli/cli-setshow.c: Ditto. + * defs.h: Don't declare tilde_expand anymore, since readline + exports it. + +2002-12-08 Elena Zannoni + + * Makefile.in (thread-db.o): Add explicit rule to ignore the use of + -Werror on this file. + +2002-12-07 Andrew Cagney + + * gdbarch.sh (TARGET_FLOAT_FORMAT): Use the macro when printing + the format name. + (TARGET_DOUBLE_FORMAT, TARGET_LONG_DOUBLE_FORMAT): Ditto. + * gdbarch.c: Regenerate. + +2002-12-06 Andrew Cagney + + * gdbarch.sh (DEPRECATED_INIT_FRAME_PC_FIRST): Rename + INIT_FRAME_PC_FIRST. Change to a function with predicate. Do not + provide a default value. + * gdbarch.h, gdbarch.c: Regenerate. + * frame.c (get_prev_frame): Update. Check + DEPRECATED_INIT_FRAME_PC_FIRST_P. + * s390-tdep.c (s390_gdbarch_init): Update. + * mips-tdep.c (mips_gdbarch_init): Update. + * config/sparc/tm-sparc.h (DEPRECATED_INIT_FRAME_PC_FIRST): Update. + * config/rs6000/tm-rs6000.h (DEPRECATED_INIT_FRAME_PC_FIRST): Update. + * alpha-tdep.c (alpha_gdbarch_init): Update. + +2002-12-06 Elena Zannoni + + * ia64-linux-nat.c: Include gdb_string.h. + * alpha-nat.c: Ditto. + * ppc-linux-nat.c: Ditto. + * Makefile.in (ia64-linux-nat.o, alpha-nat.o, ppc-linux-nat.o): + Update dependencies. + +2002-12-05 Andrew Cagney + + * gdbthread.h: Include "frame.h". + (struct thread_info): Replace step_frame_address with + step_frame_id. + * inferior.h: Include "frame.h". + (step_frame_id): Replace external variable step_frame_address. + * gdbthread.h (save_infrun_state): Replace step_frame_address + parameter with step_frame_id parameter. + (load_infrun_state): Ditto. + * Makefile.in (gdbthread_h, inferior_h): Add $(frame_h). + * infcmd.c (step_frame_id, step_1, step_once): Update. + * thread.c (load_infrun_state, save_infrun_state): Update. + * infrun.c (clear_proceed_status, save_inferior_status): Update. + (handle_inferior_event, step_over_function): Update. + (normal_stop, context_switch, restore_inferior_status): Update. + (struct inferior_status): Replace step_frame_address with + step_frame_id. + +2002-12-05 David Carlton + + * dwarf2read.c (dwarf2_add_field): Treat a field that is a + DW_TAG_member as well as a declaration as being a C++ static data + member. + (read_structure_scope): Combine tests for DW_TAG_member and + DW_TAG_variable. + +2002-12-05 David Carlton + + * linespec.c (decode_compound): New function. + (decode_line_1): Move code into decode_compound. + +2002-12-05 David Carlton + + * symtab.c (lookup_symbol_aux_local): Add 'static_block' + argument. + (lookup_symbol_aux): Do the 'field_of_this' check before checking + the static block. See PR gdb/804. + +2002-12-05 David Carlton + + * symtab.c (lookup_symbol_aux_block): New function. + (lookup_symbol_aux_local): Move code into lookup_symbol_aux_block. + +2002-12-05 Andrew Cagney + + * gdbarch.sh: Dump the predicate function and macro values. + (read): Print error on standard error. + * gdbarch.c: Regenerate. + +2002-12-04 Kevin Buettner + + * Makefile.in (mips_tdep_h): Define. + (mips-tdep.o): Add mips_tdep_h to dependency list. + * mips-tdep.h: New file. + * mips-tdep.c (mips-tdep.h): Include. + (enum mips_abi): Move to mips-tdep.h. + (mips_abi): New function. + +2002-12-04 David Carlton + + * Makefile.in (f-exp.tab.c): Don't depend on c-exp.tab.c. + +2002-12-04 David Carlton + + * symtab.c (lookup_symbol_aux): Move minsym code into a separate + function. + (lookup_symbol_aux_minsyms): New function. + +2002-12-04 J. Brobecker + + * pa64solib.c: s/boolean/int/. Fixes a build failure on hppa64-hpux. + +2002-12-04 J. Brobecker + + * config/pa/tm-hppah.h (PC_IN_SIGTRAMP): Renamed from IN_SIGTRAMP, + which is an obsolete macro name. + +2002-12-04 Daniel Jacobowitz + + * doublest.c (convert_floatformat_to_doublest): Cast exp_bias to int. + * config/alpha/alpha-linux.mh (MH_CFLAGS): Add -mieee. + +2002-12-03 H.J. Lu (hjl@gnu.org) + + * breakpoint.c (create_thread_event_breakpoint): Use xasprintf. + (create_breakpoints): Make sure the addr_string field is not + NULL. + +2002-12-03 Andrew Cagney + + * sparc-nat.c (fetch_inferior_registers) + (store_inferior_registers): Add comment on problem of LWP vs + threads. + + From 2002-11-21 Daniel Jacobowitz + * lin-lwp.c (lin_lwp_fetch_registers): Remove. + (lin_lwp_store_registers): Remove. + (init_lin_lwp_ops): Use fetch_inferior_registers + and store_inferior_registers directly. + * sparc-nat.c (fetch_inferior_registers): Honor LWP ID. + (store_inferior_registers): Likewise. + Fix PR gdb/725. + +2002-12-03 Andrew Cagney + + * frame.h (get_frame_id): Convert to a function. + (null_frame_id, frame_id_p): Declare. + (frame_id_eq, frame_id_inner): Declare. + (frame_id_build): New function. + * frame.c (get_frame_id): Update. Use null_frame_id. + (frame_find_by_id): Rewrite using frame_id_p, frame_id_eq and + frame_id_inner. + (null_frame_id, frame_id_p): Define. + (frame_id_eq, frame_id_inner): Define. + (frame_id_build): New function. + * varobj.c (varobj_create): Update. + (varobj_update): Update. + * valops.c (value_assign): Update. + (new_root_variable): Update. + * infrun.c (save_inferior_status): Update. + * breakpoint.c (watch_command_1): Update. + +2002-12-03 J. Brobecker + + * config/pa/tm-hppah.h (SNAP1): Remove unused macro. + (SNAP2): Likewise. + +2002-12-03 Andrew Cagney + + * NEWS: Mention Daniel Jacobowitz's multi-threaded shared library + patch. + + * PROBLEMS: Mention PR gdb/725. + +2002-12-03 Andreas Schwab + + * infcmd.c (construct_inferior_arguments): Handle empty arguments. + +2002-12-02 Adam Fedor + Klee Dienes + + * objc-lang.c (objc_printstr): Add width arg to match + printstr prototype. + (compare_selectors): Add 'const' to arg types. + (compare_classes): Likewise. + (find_imps): Cast msym pointer to avoid compiler warning. + (print_object_command): Validate the address before + passing it to the print routine. + (find_objc_msgcall_submethod): Change function argument to + return an int. + * objc-lang.h: Add 'extern' to all function declarations. + (value_nsstring): Add declaration. + +2002-12-02 J. Brobecker + + * somsolib.c (dld_cache): Replace boolean by int for field is_valid. + Fixes a build failure on HP/UX. + + * hpread.c (told_objfile): Replace boolean type by int. Fixes a build + failure on HP/UX. + (hpread_has_name): Advance declaration to avoid a compilation warning. + (pst_syms_count): Add missing variable type. By change, the compiler + was defaulting to int, which seems a good choice. Fixes a compilation + warning. + (pst_syms_size): Likewise. + +2002-12-02 J. Brobecker + + * hppa-tdep.c: Add #include "osabi.h" (for hppa_gdbarch_init). + (hppa_gdbarch_init): Detect osabi from objfile. Will be needed + later to set the proper gdbarch methods depending on the osabi. + * Makefile.in (hppa-tdep.o): Add dependency on osabi.h. + +2002-12-02 J. Brobecker + + * osabi.h (gdb_osabi): Add two new enum values for HPUX ELF and SOM. + * osabi.c (gdb_osabi_name): Add strings images for the two new + enum values. + (generic_elf_osabi_sniffer): Handle HPUX objfiles. + +2002-12-02 Andrew Cagney + + * MAINTAINERS (Java): Global maintainers are responible for Java. + (Past Maintainers): Mention both Anthony Green and Per Bothner as + part Java maintainers. + +2002-12-02 J. Brobecker + + * xcoffread.c (read_symbol_lineno): Replace boolean by int. + Fixes a compilation failure on AiX. + +2002-12-02 J. Brobecker + + * config/powerpc/aix432.mh (NATDEPFILES): Add a comment explaining + why aix-thread.o is not listed. + +2002-12-01 Andrew Cagney + + * gdbarch.sh (DEPRECATED_PC_IN_CALL_DUMMY): Rename + PC_IN_CALL_DUMMY. Change to predicate. Always allow call. + * gdbarch.h, gdbarch.c: Re-generate. + * config/sparc/tm-sparc.h, config/sparc/tm-sp64.h: Update. + * config/mn10200/tm-mn10200.h, config/h8500/tm-h8500.h: Update. + * config/pa/tm-hppa.h, frame.h: Update. + * x86-64-tdep.c, vax-tdep.c, sparc-tdep.c: Update. + * s390-tdep.c, ns32k-tdep.c, mn10300-tdep.c: Update. + * m68k-tdep.c, i386-tdep.c, frv-tdep.c: Update. + * cris-tdep.c, alpha-tdep.c: Update. + * frame.c (set_unwind_by_pc, create_new_frame): Use either + DEPRECATED_PC_IN_CALL_DUMMY or pc_in_dummy_frame. + (get_prev_frame): Ditto. + +2002-11-30 Andrew Cagney + + * exec.c (xfer_memory): Replace boolean with int. + * p-exp.y: Use 0 instead of false. + * corelow.c (gdb_check_format): Change return type to int from + boolean. + * utils.c: Don't include or first. + +2002-11-29 Stephane Carrez + + * m68hc11-tdep.c (m68hc11_register_raw_size): Remove. + (m68hc11_register_byte): Remove. + (m68hc11_gdbarch_init): Don't set the above. + +2002-11-29 Andrew Cagney + + * remote-mips.c (mips_initialize): Force a selected frame rebuild + by calling get_selected_frame. + * ocd.c (ocd_start_remote): Use get_selected frame instead of + set_current_frame, create_new_frame, select_frame and + get_current_frame. + * remote-e7000.c (e7000_start_remote): Ditto. + * remote-mips.c (common_open): Ditto + * remote-rdp.c (remote_rdp_open): Ditto. + +2002-11-29 Andreas Schwab + + * m68k-tdep.c (m68k_frame_chain, m68k_frame_saved_pc) + (altos_skip_prologue, delta68_frame_saved_pc, isi_frame_num_args) + (delta68_frame_num_args, news_frame_num_args, m68k_skip_prologue) + (m68k_frame_init_saved_regs, m68k_saved_pc_after_call): Use + read_memory_unsigned_integer instead of read_memory_integer when + dealing with addresses and instruction opcodes. + * m68klinux-tdep.c (m68k_linux_sigtramp_saved_pc) + (m68k_linux_frame_saved_pc): Likewise. + +2002-11-29 Andrew Cagney + + * stack.c (selected_frame, select_frame): Move from here ... + * frame.c (selected_frame, select_frame): ... to here. Include + "language.h". + * Makefile.in (frame.o): Update dependencies. + * frame.c (get_selected_frame): New function. + * frame.h (get_selected_frame): Declare. + (deprecated_selected_frame): Rename selected_frame. + * ada-lang.c, ada-tasks.c, breakpoint.c, corelow.c: Update. + * eval.c, f-valprint.c, findvar.c, frame.c, frame.h: Update. + * h8300-tdep.c, h8500-tdep.c, hppa-tdep.c, infcmd.c: Update. + * inflow.c, infrun.c, macroscope.c, mips-tdep.c: Update. + * mn10300-tdep.c, ocd.c, regcache.h, remote-e7000.c: Update. + * remote-mips.c, remote-rdp.c, sh-tdep.c, sparc-tdep.c: Update. + * stack.c, thread.c, tracepoint.c, valops.c, varobj.c: Update. + * z8k-tdep.c, cli/cli-cmds.c: Update. + +2002-11-29 Andrew Cagney + + * frame.h (get_selected_block): Add comments. + +2002-11-28 Andrew Cagney + + * frame.c (pc_notcurrent): New function. + (find_frame_sal): New function. + * frame.h (find_frame_sal): Declare. + (struct symtab_and_line): Add opaque declaration. + * stack.c (print_frame_info_base): Use find_frame_sal instead of + find_pc_line. + (frame_info): Ditto. + * ada-lang.c (find_printable_frame): Ditto. + +2002-11-28 J. Brobecker + + * configure.in: Check that the pthdebug library is recent enough + before enabling thread support on native AiX. + * configure: Regenerate. + + * config/powerpc/aix432.mh (NATDEPFILES): Remove aix-thread.o + from the list of object files as it is now appended by configure + if thread support is enabled. + (NAT_CLIBS): Removed as -lpthdebug is also appended by configure + if thread support is enabled. + +2002-11-28 Andrew Cagney + + * stack.c (get_selected_block): In-line get_current_block. + * frame.h (get_current_block): Delete declaration. + * blockframe.c (get_current_block): Delete function. + +2002-11-28 Andrew Cagney + + * gdbarch.sh (DEPRECATED_USE_GENERIC_DUMMY_FRAMES): Rename + USE_GENERIC_DUMMY_FRAMES. + * gdbarch.h, gdbarch.c: Regenerate. + * valops.c, frame.c: Update. + * config/z8k/tm-z8k.h, config/mn10200/tm-mn10200.h: Update. + * config/m32r/tm-m32r.h, config/h8500/tm-h8500.h: Update. + * config/pa/tm-hppa.h, blockframe.c: Update. + * vax-tdep.c, sparc-tdep.c, ns32k-tdep.c: Ditto. + * m68k-tdep.c, alpha-tdep.c: Ditto. + + * arm-tdep.c: Eliminate USE_GENERIC_DUMMY_FRAMES as always 1. + * mips-tdep.c: Ditto. + +2002-11-27 Andrew Cagney + + * gdbarch.sh (CALL_DUMMY_LOCATION): Default to AT_ENTRY_POINT. + (USE_GENERIC_DUMMY_FRAMES): Default to true. + (PC_IN_CALL_DUMMY): Default to generic_pc_in_call_dummy. + * gdbarch.c, gdbarch.h: Re-generate. + * inferior.h (USE_GENERIC_DUMMY_FRAMES): Delete macro definition. + (CALL_DUMMY_LOCATION): Delete macro definition. + (PC_IN_CALL_DUMMY): Delete macro definitions. + + * arm-tdep.c (arm_gdbarch_init): Do not set pc_in_call_dummy, + default is already generic_pc_in_call_dummy. + * xstormy16-tdep.c (xstormy16_gdbarch_init): Ditto. + * v850-tdep.c (v850_gdbarch_init): Ditto. + * sh-tdep.c (sh_gdbarch_init): Ditto. + * rs6000-tdep.c (rs6000_gdbarch_init): Ditto. + * mips-tdep.c (mips_gdbarch_init): Ditto. + * mcore-tdep.c (mcore_gdbarch_init): Ditto. + * m68hc11-tdep.c (m68hc11_gdbarch_init): Ditto. + * ia64-tdep.c (ia64_gdbarch_init): Ditto. + * h8300-tdep.c (h8300_gdbarch_init): Ditto. + * d10v-tdep.c (d10v_gdbarch_init): Ditto. + * avr-tdep.c (avr_gdbarch_init): Ditto. + + * arm-tdep.c (arm_gdbarch_init): Do not set + use_generic_dummy_frames, default is already 1. + * xstormy16-tdep.c (xstormy16_gdbarch_init): Ditto. + * x86-64-tdep.c (x86_64_gdbarch_init): Ditto. + * v850-tdep.c (v850_gdbarch_init): Ditto. + * sh-tdep.c (sh_gdbarch_init): Ditto. + * s390-tdep.c (s390_gdbarch_init): Ditto. + * rs6000-tdep.c (rs6000_gdbarch_init): Ditto. + * mn10300-tdep.c (mn10300_gdbarch_init): Ditto. + * mips-tdep.c (mips_gdbarch_init): Ditto. + * mcore-tdep.c (mcore_gdbarch_init): Ditto. + * m68hc11-tdep.c (m68hc11_gdbarch_init): Ditto. + * ia64-tdep.c (ia64_gdbarch_init): Ditto. + * i386-tdep.c (i386_gdbarch_init): Ditto. + * h8300-tdep.c (h8300_gdbarch_init): Ditto. + * frv-tdep.c (frv_gdbarch_init): Ditto. + * d10v-tdep.c (d10v_gdbarch_init): Ditto. + * cris-tdep.c (cris_gdbarch_init): Ditto. + * avr-tdep.c (avr_gdbarch_init): Ditto. + + * xstormy16-tdep.c (xstormy16_gdbarch_init): Do not set + call_dummy_location, default is already AT_ENTRY_POINT. + * x86-64-tdep.c (x86_64_gdbarch_init): Ditto. + * v850-tdep.c (v850_gdbarch_init): Ditto. + * sparc-tdep.c (sparc_gdbarch_init): Ditto. + * sh-tdep.c (sh_gdbarch_init): Ditto. + * s390-tdep.c (s390_gdbarch_init): Ditto. + * rs6000-tdep.c (rs6000_gdbarch_init): Ditto. + * mn10300-tdep.c (mn10300_gdbarch_init): Ditto. + * mips-tdep.c (mips_gdbarch_init): Ditto. + * mcore-tdep.c (mcore_gdbarch_init): Ditto. + * m68hc11-tdep.c (m68hc11_gdbarch_init): Ditto. + * ia64-tdep.c (ia64_gdbarch_init): Ditto. + * i386-tdep.c (i386_gdbarch_init): Ditto. + * h8300-tdep.c (h8300_gdbarch_init): Ditto. + * frv-tdep.c (frv_gdbarch_init): Ditto. + * d10v-tdep.c (d10v_gdbarch_init): Ditto. + * cris-tdep.c (cris_gdbarch_init): Ditto. + * avr-tdep.c (avr_gdbarch_init): Ditto. + * arm-tdep.c (arm_gdbarch_init): Ditto. + * alpha-tdep.c (alpha_gdbarch_init): Ditto. + +2002-11-28 Andrew Cagney + + * frame.h: Update comments on set_current_frame, create_new_frame, + flush_cached_frames, reinit_frame_cache, select_frame and + selected_frame. + +2002-11-27 Andrew Cagney + + * config/z8k/tm-z8k.h (PC_IN_CALL_DUMMY): Update definition to use + deprecated pc_in_call_dummy function. + * config/sparc/tm-sparc.h (PC_IN_CALL_DUMMY): Ditto. + * config/sparc/tm-sp64.h (PC_IN_CALL_DUMMY): Ditto. + * config/pa/tm-hppa.h (PC_IN_CALL_DUMMY): Ditto. + * config/mn10200/tm-mn10200.h (PC_IN_CALL_DUMMY): Ditto. + * config/h8500/tm-h8500.h (PC_IN_CALL_DUMMY): Ditto. + +2002-11-26 Martin M. Hunt + + * Makefile.in: Remove Tix dependencies. + * acinclude.m4: Ditto. + * aclocal.m4: Ditto. + * configure.in: Ditto. + * configure: Regenerated. + +2002-11-26 Andrew Cagney + + * gdbarch.sh (TARGET_FLOAT_FORMAT): Print the float format name. + (TARGET_DOUBLE_FORMAT, TARGET_LONG_DOUBLE_FORMAT): Ditto. + * gdbarch.c: Re-generate. + +2002-11-26 Andrew Cagney + + * config/h8500/tm-h8500.h (CALL_DUMMY_LOCATION): Define as ON_STACK. + (USE_GENERIC_DUMMY_FRAMES): Define as zero. + (PC_IN_CALL_DUMMY): Define as pc_in_call_dummy_on_stack. + * config/mn10200/tm-mn10200.h (PC_IN_CALL_DUMMY): Define as + pc_in_call_dummy_at_entry_point. + * config/pa/tm-hppa.h (CALL_DUMMY_LOCATION): Define as ON_STACK. + (USE_GENERIC_DUMMY_FRAMES): Define as zero. + (PC_IN_CALL_DUMMY): Define as pc_in_call_dummy_on_stack. + * config/pa/tm-hppa64.h (CALL_DUMMY_LOCATION): Delete undefine. + * config/sparc/tm-sparc.h (PC_IN_CALL_DUMMY): Define as + pc_in_call_dummy_on_stack. + * config/sparc/tm-sp64.h (PC_IN_CALL_DUMMY): Redefine as + pc_in_call_dummy_at_entry_point and pc_in_call_dummy_on_stack. + * config/z8k/tm-z8k.h (CALL_DUMMY_LOCATION): Define as ON_STACK. + (USE_GENERIC_DUMMY_FRAMES): Define as zero. + (PC_IN_CALL_DUMMY): Defile as pc_in_call_dummy_on_stack. + +2002-11-26 Andrew Cagney + + * inferior.h (deprecated_pc_in_call_dummy_before_text_end): Rename + pc_in_call_dummy_before_text_end + (deprecated_pc_in_call_dummy_after_text_end): Rename + pc_in_call_dummy_after_text_end. + (deprecated_pc_in_call_dummy_on_stack): Rename + pc_in_call_dummy_on_stack. + (deprecated_pc_in_call_dummy_at_entry_point): Rename + pc_in_call_dummy_at_entry_point. + * m68k-tdep.c (m68k_gdbarch_init): Update. + * s390-tdep.c (s390_gdbarch_init): Update. + * x86-64-tdep.c (x86_64_gdbarch_init): Update. + * vax-tdep.c (vax_gdbarch_init): Update. + * sparc-tdep.c (sparc_gdbarch_init): Update. + * ns32k-tdep.c (ns32k_gdbarch_init): Update. + * mn10300-tdep.c (mn10300_gdbarch_init): Update. + * i386-tdep.c (i386_gdbarch_init): Update. + * frv-tdep.c (frv_gdbarch_init): Update. + * cris-tdep.c (cris_gdbarch_init): Update. + * config/sparc/tm-sparc.h (PC_IN_CALL_DUMMY): Update. + * blockframe.c (deprecated_pc_in_call_dummy_before_text_end) + (deprecated_pc_in_call_dummy_after_text_end) + (deprecated_pc_in_call_dummy_on_stack) + (deprecated_pc_in_call_dummy_at_entry_point): Update. + * alpha-tdep.c (alpha_gdbarch_init): Update. + +2002-11-25 Daniel Jacobowitz + + * acconfig.h (HAVE_PREAD64): Add. + * configure.in: Check for pread64. + * config.in: Regenerated. + * configure: Regenerated. + * lin-lwp.c (lin_lwp_xfer_memory): Call linux_proc_xfer_memory. + * linux-proc.c (linux_proc_xfer_memory): New function. + * config/nm-linux.h (linux_proc_xfer_memory): Add prototype. + +2002-11-25 David Carlton + + * dwarf2read.c (scan_partial_symbols): Descend into namespace + pdi's with no name. + +2002-11-25 Andrew Cagney + + * MAINTAINERS: Mark h8500 as broken. Breakage occured Fri Nov 5 + 16:32:04 1999 Andrew Cagney . + +2002-11-25 Jim Blandy + + * symfile.c (init_objfile_sect_indices): New function. + (default_symfile_offsets): Move the section-index-initializing + stuff into init_objfile_sect_indices, and call that. + + * symtab.h (SIZEOF_N_SECTION_OFFSETS): New macro. + (SIZEOF_SECTION_OFFSETS): Use SIZEOF_N_SECTION_OFFSETS. + + * symfile.c (syms_from_objfile): Adjust indentation. + + * symfile.c (symbol_file_add): Flush gdb_stdout even if from_tty + || info_verbose isn't true. + +2002-11-24 Andrew Cagney + + * gdbarch.sh (FRAME_ARGS_ADDRESS, FRAME_LOCALS_ADDRESS): Change + default to get_frame_base. + * gdbarch.h, gdbarch.c: Regenerate. + * arch-utils.c (default_frame_address): Delete function. + * arch-utils.h (default_frame_address): Delete declaration + +2002-11-24 Pierre Muller + + * varobj.c (find_frame_addr_in_frame_chain): + Use get_frame_base instead of FRAME_FP, + obvious fix. + +2002-11-19 Andrew Cagney + + * frame.h (FRAME_FP): Delete macro. + (get_frame_base): New function declaration. + * frame.c (get_frame_base): New function. + (get_frame_id): Use ->frame. + (frame_find_by_id): Rewrite to use get_frame_id. + * blockframe.c: Use get_frame_base instead of FRAME_FP. + * cris-tdep.c, d10v-tdep.c, findvar.c, h8500-tdep.c: Ditto. + * hppa-tdep.c, i386-tdep.c, infcmd.c, infrun.c: Ditto. + * m68hc11-tdep.c, m68k-tdep.c, mcore-tdep.c, mips-tdep.c: Ditto. + * mn10200-tdep.c, mn10300-tdep.c, rs6000-tdep.c: Ditto. + * sh-tdep.c, sparc-tdep.c, stack.c, tracepoint.c: Ditto. + * v850-tdep.c, valops.c, z8k-tdep.c: Ditto. + +2002-11-24 Andrew Cagney + + * arm-tdep.c (arm_gdbarch_init): Do not set get_saved_register. + +2002-11-24 Andrew Cagney + + * frame.c (set_unwind_by_pc): Revert change below, use + PC_IN_CALL_DUMMY. + (get_prev_frame): Ditto. + +2002-11-24 Andrew Cagney + + * dummy-frame.c (pc_in_dummy_frame): New function. + (generic_pc_in_call_dummy): Call pc_in_dummy_frame. + (find_dummy_frame): Update comment. + (generic_pop_current_frame): Use get_frame_type. + * dummy-frame.h (pc_in_dummy_frame): Declare. + * frame.c (set_unwind_by_pc): Use pc_in_dummy_frame. + (create_new_frame): Use pc_in_dummy_frame. + (get_prev_frame): Use pc_in_dummy_frame. + (frame_saved_regs_register_unwind): Use get_prev_frame. + (deprecated_generic_get_saved_register): Use get_prev_frame. + +2002-11-23 Andrew Cagney + + * blockframe.c (find_frame_addr_in_frame_chain): Move function + from here ... + * varobj.c (find_frame_addr_in_frame_chain): ... to here. + (varobj_create): Note that frame ID should be used. + * frame.h (find_frame_addr_in_frame_chain): Delete declaration. + +2002-11-23 Andrew Cagney + + * breakpoint.c: Include "gdb_assert.h". + (deprecated_frame_in_dummy): Assert that generic dummy frames are + not being used. + * Makefile.in (breakpoint.o): Update dependencies. + * ada-lang.c (find_printable_frame): Use get_frame_type instead of + deprecated_frame_in_dummy. + * stack.c (print_frame_info_base): Ditto. + (frame_info): Ditto. + (print_frame_info_base): Ditto. Delete dead code. + +2002-11-23 Andreas Schwab + + * Makefile.in (m68k_tdep_h): Define. + (abug-rom.o, cpu32bug-rom.o, dbug-rom.o, m68k-tdep.o, m68klinux-nat.o) + (remote-est.o, rom68k-rom.o): Add $(m68k_tdep_h). + * m68k-tdep.c: Move register number enum ... + * m68k-tdep.h: ... to this new file and rename the constants from + E_* to M68K_*. All uses changed. + * config/m68k/tm-m68k.h (D0_REGNUM, A0_REGNUM): Remove definitions. + * abug-rom.c: Include "m68k-tdep.h". Use + M68K_D0_REGNUM/M68K_A0_REGNUM instead of D0_REGNUM/A0_REGNUM. + * cpu32bug-rom.c: Likewise. + * dbug-rom.c: Likewise. + * m68k-tdep.c: Likewise. + * m68klinux-nat.c: Likewise. + * remote-est.c: Likewise. + * rom68k-rom.c: Likewise. + * config/m68k/tm-linux.h: Likewise. + +2002-11-23 Andrew Cagney + + * arm-tdep.c (arm_gdbarch_init): Remove old style non-generic + dummy frame initialization code. + * mips-tdep.c (mips_gdbarch_init): Ditto. + +2002-11-22 Christopher Faylor + + * win32-nat.c (child_attach): Reset saw_create counter or subsequent + attach will hang. + +2002-11-22 Andrew Cagney + + * gdbarch.sh (FRAME_ARGS_ADDRESS, FRAME_LOCALS_ADDRESS): Default + to default_frame_address. + * gdbarch.h, gdbarch.c: Re-generate. + + * d10v-tdep.c (d10v_gdbarch_init): Do not set frame_args_address + or frame_locals_address to default_frame_address. + * m68k-tdep.c (m68k_gdbarch_init): Update. + * i386-tdep.c (i386_gdbarch_init): Update. + * frv-tdep.c (frv_gdbarch_init): Update. + * sh-tdep.c (sh_gdbarch_init): Update. + * v850-tdep.c (v850_gdbarch_init): Update. + * sparc-tdep.c (sparc_gdbarch_init): Update. + * mips-tdep.c (mips_gdbarch_init): Update. + * mn10300-tdep.c (mn10300_gdbarch_init): Update. + * x86-64-tdep.c (x86_64_gdbarch_init): Update. + * xstormy16-tdep.c (xstormy16_gdbarch_init): Update. + + * cris-tdep.c (cris_frame_args_address): Delete function. + (cris_frame_locals_address): Delete function. + (cris_gdbarch_init): Do not set frame_args_address or + frame_locals_address. + +2002-11-22 Michael Snyder + + * thread-db.c (thread_db_load): Tell the user what's going on + if dlopen fails on libthread_db. + +2002-11-23 Andreas Schwab + + * m68k-tdep.c (m68k_register_virtual_type): Use architecture + invariant return values. + +2002-11-22 Andreas Schwab + + * valops.c (value_slice): Move declaration of `offset' to avoid + warning. + +2002-11-22 Christopher Faylor + + * win32-nat.c (psapi_get_dll_name): Fix a compiler warning. + (struct so_stuff): Add end_addr field. + (register_loaded_dll): Calculate and store end address of loaded dll. + (solib_address): New function. + (child_solib_loaded_library_pathname): Pass carefully constructed + section info to safe_symbol_file_add rather than ignoring it. + (get_child_debug_event): Call re_enable_breakpoints_in_shlibs when a + DLL is loaded. + (do_initial_child_stuff): Call disable_breakpoints_in_shlibs. + (child_create_inferior): Fix a compiler warning. + * config/i386/tm-cygwin.h (PC_SOLIB): Define new macro. + (solib_address): Declare new function. + +2002-11-22 Andreas Schwab + + * m68k-tdep.c (m68k_register_virtual_type): Return int for SR, FPC + and FPS registers. + +2002-11-21 Daniel Jacobowitz + + * maint.c (_initialize_maint_cmds): Fix typo. From + Francesco Potorti` . + +2002-11-21 Andrew Cagney + + * mips-tdep.c (mips_dump_tdep): Delete references to + GDB_TARGET_UNMASK_DISAS_PC and GDB_TARGET_MASK_DISAS_PC. + * config/mips/tm-mips.h (GDB_TARGET_MASK_DISAS_PC): Delete macro. + (GDB_TARGET_UNMASK_DISAS_PC): Delete macro. + * printcmd.c (build_address_symbolic): Delete calls to + GDB_TARGET_UNMASK_DISAS_PC and GDB_TARGET_MASK_DISAS_PC. + (address_info): Ditto. + Fix PR gdb/773. + +2002-11-19 Klee Dienes + Adam Fedor + + * completer.c (skip_quoted_chars): Renamed from skip_chars. Add + the ability to explicitly specify the quote characters and word + break characters; if NULL is specified for either, use the old + behavior of using the characters used by the completer. + (skip_chars): New function. Convenience wrapper around + skip_quoted_chars to provide the original skip_chars behavior. + * completer.h (skip_quoted_chars): Add prototype. + +2002-11-19 Andrew Cagney + + Problems reported by Paul Eggert. + * gdbarch.sh: Use `sort -k 3`. Fix PR gdb/527. + +2002-11-19 Andreas Schwab + + * m68klinux-nat.c (IS_SIGTRAMP, IS_RT_SIGTRAMP) + (m68k_linux_in_sigtramp, SIGCONTEXT_PC_OFFSET) + (UCONTEXT_PC_OFFSET, m68k_linux_sigtramp_saved_pc) + (m68k_linux_frame_saved_pc): Move to ... + * m68klinux-tdep.c: ... here. New file. + * Makefile.in (m68klinux-tdep.o): Add dependencies. + * config/m68k/linux.mt (TDEPFILES): Add m68klinux-tdep.o. + +2002-11-19 Adam Fedor + + * objc-exp.y: Revert to old skip_quoted usage. + +2002-11-19 Adam Fedor + + * Makefile.in (SFILES): Add objc-exp.y objc-lang.c. + (objc_lang_h): Define. + (YYFILES): Add objc-exp.tab.c. + (local-maintainer-clean): Remove objc-exp.tab.c. + (objc-exp.tab.c, objc-exp.tab.o, objc-lang.o): New target. + +2002-11-19 Pierre Muller + + * p-exp.y (typecast rule): Add automatic dereference of + pascal classes if needed. + (THIS): Set current_type. + Automatically dereference pascal classes. + (typebase rule): Add ^typebase recognition. + +2002-11-18 Adam Fedor + + * expprint.c (print_subexp): Handle OP_OBJC_NSSTRING, + OP_OBJC_MSGCALL, and OP_OBJC_SELF. + (op_name): Handle OP_OBJC_SELF. + * Makefile.in (expprint.o): Add additional depends. + +2002-11-18 Adam Fedor + + * expression.h: Rename ObjC ops to OP_OBJC_MSGCALL, + OP_OBJC_SELECTOR, OP_OBJC_NSSTRING, and OP_OBJC_SELF. + * parse.c (length_of_subexp, prefixify_subexp): Likewise. + * objc-exp.y: Likewise. + +2002-11-18 Adam Fedor + + * gdb/parser-defs.h: (struct objc_class_str): New structure + for parsing ObjC classes. + +2002-11-18 Andrew Cagney + + * stack.c (frame_relative_level): Copy function from here ... + * frame.c (frame_relative_level): ...to here. + +2002-11-18 Andrew Cagney + + * frame.h (enum frame_type): Define. + (get_frame_type): Declare. + (struct frame_info): Add field `type'. Delete field + signal_handler_caller. + (deprecated_set_frame_signal_handler_caller): Declare. + * frame.c (get_frame_type): New function. + (deprecated_set_frame_type): New function. + (create_new_frame): Set the frame's type. + (get_prev_frame): Similar. + * sparc-tdep.c: Use get_frame_type instead of signal_handler_caller. + * s390-tdep.c: Ditto. + * m68klinux-nat.c: Ditto. + * ns32k-tdep.c: Ditto. + * x86-64-linux-tdep.c: Ditto. + * vax-tdep.c: Ditto. + * rs6000-tdep.c: Ditto. + * ppc-linux-tdep.c: Ditto. + * i386-interix-tdep.c: Ditto. + * mips-tdep.c: Ditto. + * m68k-tdep.c: Ditto. + * hppa-tdep.c: Ditto. + * ia64-tdep.c: Ditto. + * cris-tdep.c: Ditto. + * arm-tdep.c: Ditto. + * alpha-tdep.c: Ditto. + * i386-tdep.c: Ditto. + * stack.c: Ditto. + * ada-lang.c: Ditto. + * blockframe.c: Update. + * i386-interix-tdep.c (i386_interix_back_one_frame): Use + deprecated_set_frame_type instead of signal_handler_caller. + * ppc-linux-tdep.c (ppc_linux_init_extra_frame_info): Ditto. + * rs6000-tdep.c (rs6000_init_extra_frame_info): Ditto. + * breakpoint.h: Delete FIXME suggesting get_frame_type. + +2002-11-18 Klee Dienes + + * Makefile.in (buildsym.o): Add dependency for gdb_assert.h. + +2002-11-18 Klee Dienes + + * buildsym.c (pop_context): Add comment. + +2002-11-18 Klee Dienes + + * buildsym.h (pop_context): Convert to function, defined in + buildsym.c. + * buildsym.c: Include gdb_assert.h. + (pop_context): Implement as C function. Add check for stack + underflow. + * dbxread.c (process_one_symbol): Complain and stop processing + that symbol if we are already at the top of the context stack for + a function-end N_FUN (this would imply an umatched RBRAC). Ditto + when processing N_RBRAC. + +2002-11-16 Daniel Jacobowitz + + * config/pa/nm-hppah.h (CHILD_POST_FOLLOW_INFERIOR_BY_CLONE): Don't + define. + (struct target_waitstatus): Add opaque definition. + * corelow.c (init_core_ops): Don't set to_clone_and_follow_inferior. + * exec.c (init_exec_ops): Likewise. + * fork-child.c (clone_and_follow_inferior): Remove. + * hppah-nat.c (child_post_follow_inferior_by_clone): Remove. + * inferior.h (clone_and_follow_inferior): Remove prototype. + * infrun.c (follow_fork_mode_both): Remove. + (follow_fork_mode_kind_names): Remove commented out "both". + (follow_inferior_fork): Remove follow_fork_mode_both support. + * inftarg.c (child_clone_and_follow_inferior): Remove. + (child_post_follow_inferior_by_clone): Remove. + (init_child_ops): Don't set to_clone_and_follow_inferior + or to_post_follow_inferior_by_clone. + * target.c (default_clone_and_follow_inferior): Remove. + (cleanup_target): Don't set to_clone_and_follow_inferior + or to_post_follow_inferior_by_clone. + (find_default_clone_and_follow_inferior): Remove. + (init_dummy_target): Don't set to_clone_and_follow_inferior. + (debug_to_clone_and_follow_inferior): Remove. + (debug_to_post_follow_inferior_by_clone): Remove. + (setup_target_debug): Don't set to_clone_and_follow_inferior + or to_post_follow_inferior_by_clone. + * target.h (struct target_ops): Remove to_clone_and_follow_inferior + and to_post_follow_inferior_by_clone. + (child_clone_and_follow_inferior): Remove prototype. + (child_post_follow_inferior_by_clone): Remove prototype. + (target_clone_and_follow_inferior): Remove macro. + (target_post_follow_inferior_by_clone): Remove macro. + (find_default_clone_and_follow_inferior): Remove prototype. + +2002-11-16 Daniel Jacobowitz + + * breakpoint.c (bpstat_stop_status): Call inferior_has_forked, + inferior_has_vforked, and inferior_has_execd instead of + target_has_forked, target_has_vforked, and target_has_execd. + * config/pa/nm-hppah.h (CHILD_HAS_FORKED, CHILD_HAS_VFORKED) + (CHILD_HAS_EXECD, CHILD_HAS_SYSCALL_EVENT): Don't define. + (CHILD_WAIT): Define. + (child_wait): Add prototype. + * hppah-nat.c (hpux_has_forked): Rename from child_has_forked. + Add prototype. + (hpux_has_vforked): Likewise, from child_has_vforked. + (hpux_has_execd): Likewise, from child_has_execd. + (hpux_has_syscall_event): Likewise, from child_has_syscall_event. + (not_same_real_pid, child_wait): New, copied from inftarg.c. + Call hpux_has_forked, hpux_has_vforked, hpux_has_execd, + and hpux_has_syscall_event instead of the target hooks. + * infrun.c (inferior_has_forked, inferior_has_vforked) + (inferior_has_execd): New functions. + * inftarg.c (not_same_real_pid): Remove. + (child_wait): Remove references to not_same_real_pid, + target_has_forked, target_has_vforked, target_has_execd, + and target_has_syscall_event. + (child_has_forked, child_has_vforked, child_has_execd) + (child_has_syscall_event): Remove. + (init_child_ops): Remove references to child_has_forked, + child_has_vforked, child_has_execd, and child_has_syscall_event. + * infttrace.c (hpux_has_forked): Rename from child_has_forked. + (hpux_has_vforked): Likewise, from child_has_vforked. + (hpux_has_execd): Likewise, from child_has_execd. + (hpux_has_syscall_event): Likewise, from child_has_syscall_event. + * target.c (cleanup_target): Remove references to + to_has_forked, to_has_vforked, to_has_execd, and + to_has_syscall_event. + (update_current_target): Likewise. + (setup_target_debug): Likewise. + (debug_to_has_forked): Remove. + (debug_to_has_vforked): Remove. + (debug_to_has_execd): Remove. + (debug_to_has_syscall_event): Remove. + * target.h (struct target_ops): Remove to_has_forked. + to_has_vforked, to_has_execd, and to_has_syscall_event. + (child_has_forked, child_has_vforked, child_has_execd) + (child_has_syscall_event): Remove prototypes. + (inferior_has_forked, inferior_has_vforked, inferior_has_execd): Add + prototypes. + (target_has_forked, target_has_vforked, target_has_execd) + (target_has_syscall_event): Remove macros. + +2002-11-16 Daniel Jacobowitz + + * hppah-nat.c (child_can_follow_vfork_prior_to_exec): Remove. + * inftarg.c (child_can_follow_vfork_prior_to_exec): Remove. + (init_child_ops): Don't initialize to_can_follow_vfork_prior_to_exec. + * infttrace.c (child_can_follow_vfork_prior_to_exec): Remove. + * target.c (cleanup_target): Remove reference to + to_can_follow_vfork_prior_to_exec. + (update_current_target): Likewise. + (debug_to_can_follow_vfork_prior_to_exec): Remove. + (setup_target_debug): Remove reference to + to_can_follow_vfork_prior_to_exec. + * target.h (struct target_ops): Remove + to_can_follow_vfork_prior_to_exec. + (child_can_follow_vfork_prior_to_exec): Remove prototype. + (target_can_follow_vfork_prior_to_exec): Remove definition. + * config/pa/nm-hppah.h (CHILD_CAN_FOLLOW_VFORK_PRIOR_TO_EXEC): Don't + define. + * infrun.c (follow_vfork_when_exec): Remove. + (follow_inferior_fork): Remove references to follow_vfork_when_exec. + (follow_exec): Likewise. + (handle_inferior_event): Likewise. + (keep_going): Likewise. + +2002-11-15 Andrew Cagney + + * frame.c (generic_unwind_get_saved_register): Make static. + * frame.h (generic_unwind_get_saved_register): Delete declaration. + * avr-tdep.c (avr_gdbarch_init): Do not set get_saved_register, + defaults to generic_unwind_get_saved_register. + * mn10300-tdep.c (mn10300_gdbarch_init): Ditto. + * h8300-tdep.c (h8300_gdbarch_init): Ditto. + * frv-tdep.c (frv_gdbarch_init): Ditto. + * i386-tdep.c (i386_gdbarch_init): Ditto. + * s390-tdep.c (s390_gdbarch_init): Ditto. + * rs6000-tdep.c (rs6000_gdbarch_init): Ditto. + * v850-tdep.c (v850_gdbarch_init): Ditto. + * mcore-tdep.c (mcore_gdbarch_init): Ditto. + * d10v-tdep.c (d10v_gdbarch_init): Ditto. + * config/mn10200/tm-mn10200.h (GET_SAVED_REGISTER): Delete macro. + +2002-11-15 Andrew Cagney + + * x86-64-linux-nat.c (i386_sse_regnum_p): New function. Copy from + i386-tdep.c. + +2002-11-15 Andrew Cagney + + * frame.h (sigtramp_saved_pc): Delete declaration. + * blockframe.c (sigtramp_saved_pc): Delete function. + * ns32k-tdep.c (ns32k_sigtramp_saved_pc): New function. + (ns32k_frame_saved_pc): Call ns32k_sigtramp_saved_pc. + * vax-tdep.c (vax_sigtramp_saved_pc): New function. + (vax_frame_saved_pc): Call vax_sigtramp_saved_pc. + +2002-11-15 Andrew Cagney + + * frame.c (frame_pc_unwind): New function. + (frame_saved_regs_pc_unwind): New function. + (frame_register_unwind): Pass unwind_cache instead of + register_unwind_cache. + (set_unwind_by_pc): Add unwind_pc parameter, set. + (create_new_frame): Pass frame->pc_unwind to set_unwind_by_pc. + (get_prev_frame): Ditto. + * frame.h (frame_pc_unwind_ftype): Declare. + (struct frame_info): Add pc_unwind, pc_unwind_cache_p and + pc_unwind_cache. Rename register_unwind_cache to unwind_cache. + (frame_pc_unwind): Declare. + * dummy-frame.c (dummy_frame_pc_unwind): New function. + (struct dummy_frame): Add comment mentioning that values are for + previous frame. + * dummy-frame.h (dummy_frame_pc_unwind): Declare. + * blockframe.c (file_frame_chain_valid): Use frame_pc_unwind. + (generic_file_frame_chain_valid): Ditto. + * stack.c (frame_info): Ditto. + +2002-11-15 David Carlton + + * linespec.c (locate_first_half): New function. + (decode_line_1): Move code into locate_first_half. + +2002-11-15 Andrew Cagney + + * complaints.h: Add comment explaining how to eliminate a + deprecated_complain call. + * complaints.h: Fix spelling errors. + +2002-11-15 David Carlton + + * printcmd.c: Remove #include "disasm.h". + +2002-11-14 Andrew Cagney + + * frame.h: Move the most relevant interface functions to the start + of the file. + +2002-11-14 Andrew Cagney + + * regcache.h (deprecated_registers): Rename registers. + * a68v-nat.c, alpha-nat.c, arch-utils.c, core-sol2.c: Update. + * hp300ux-nat.c, hppab-nat.c, hppah-nat.c: Update. + * hppam3-nat.c, hpux-thread.c, i386gnu-nat.c: Update. + * ia64-aix-nat.c, ia64-linux-nat.c, ia64-tdep.c: Update. + * irix4-nat.c, irix5-nat.c, lynx-nat.c, m68k-tdep.c: Update. + * m68knbsd-nat.c, mips-linux-tdep.c, mipsm3-nat.c: Update. + * mipsv4-nat.c, ns32knbsd-nat.c, ppc-bdm.c: Update. + * ppc-sysv-tdep.c, ptx4-nat.c, regcache.c, remote-es.c: Update. + * remote-sds.c, remote-vx68.c, remote-vxmips.c: Update. + * remote-vxsparc.c, rs6000-tdep.c, sol-thread.c: Update. + * sparc-nat.c, sparc-tdep.c, sun3-nat.c, symm-nat.c: Update. + * v850ice.c: Update. + +Wed Nov 13 19:51:05 2002 Andrew Cagney + + * utils.c (gdb_realpath): Add comment mentioning realpath with a + NULL buffer. + +2002-11-13 Andrew Cagney + + * regcache.h (deprecated_read_register_bytes): Rename + read_register_bytes. + (deprecated_write_register_bytes): Rename write_register_bytes. + * alpha-tdep.c, arm-tdep.c, cris-tdep.c, d10v-tdep.c: Update. + * dwarf2cfi.c, frv-tdep.c, hppa-tdep.c, ia64-tdep.c: Update. + * m68k-tdep.c, mcore-tdep.c, mips-tdep.c, mn10300-tdep.c: Update. + * ns32k-tdep.c, regcache.c, remote-sds.c, remote-vx.c: Update. + * remote.c, rs6000-tdep.c, s390-tdep.c, sh-tdep.c: Update. + * sparc-tdep.c, v850-tdep.c, vax-tdep.c, x86-64-tdep.c: Update. + * xstormy16-tdep.c, z8k-tdep.c, config/nm-gnu.h: Update. + * config/nm-m3.h, config/h8500/tm-h8500.h: Update. + * config/i386/nm-ptx4.h, config/i386/nm-symmetry.h: Update. + * config/m32r/tm-m32r.h, config/m68k/nm-sun3.h: Update. + * config/m68k/tm-delta68.h, config/m68k/tm-linux.h: Update. + * config/mn10200/tm-mn10200.h, config/pa/tm-hppa64.h: Update. + * config/sparc/nm-nbsd.h, config/sparc/nm-sun4os4.h: Update. + * config/sparc/nm-sun4sol2.h, config/sparc/tm-sparclet.h: Update. + +2002-11-13 Jim Blandy + + * findvar.c (read_var_value): Doc fix. + +2002-11-13 Andrew Cagney + + * regcache.c (struct regcache): Replace passthough_p with + readonly_p. + (regcache_xmalloc): Initialize readonly_p. + (build_regcache): Initialize readonly_p. + (regcache_save): New function. + (regcache_restore): New function. + (regcache_cpy): Re-implement using regcache_save and + regcache_restore. + (regcache_raw_read): Update. + (regcache_cooked_read): When a read-only cache, checked for cached + pseudo register values. + (regcache_raw_write): Assert that the cache is not read-only. + Remove code handling a non-passthrough cache. + * regcache.h (regcache_save): Declare. + (regcache_restore): Declare. + +2002-11-13 Andrew Cagney + + * regcache.c (struct regcache_descr): Add fields + sizeof_cooked_registers and sizeof_cooked_register_valid_p. + (init_legacy_regcache_descr): Compute the size of a cooked + register cache and then assign that to sizeof_raw_registers. Set + sizeof_raw_register_valid_p to sizeof_cooked_register_valid_p + (init_legacy_regcache_descr): Ditto. + +2002-11-13 Andrew Cagney + + * regcache.c (register_buffer): Move to near start of file, update + description. + (regcache_raw_read): Use. + (regcache_raw_write): Use. + (struct regcache): Rename raw_registers to registers and + raw_register_valid_p to register_valid_p. + (regcache_xmalloc): Update. + (regcache_xfree): Update. + (register_buffer): Update. + (regcache_cpy): Update. + (regcache_cpy_no_passthrough): Update. + (regcache_valid_p): Update. + (deprecated_grub_regcache_for_registers): Update. + (deprecated_grub_regcache_for_register_valid): Update. + (set_register_cached): Update. + (regcache_raw_write): Update. + +2002-11-13 Pierre Muller + + * p-exp.y (name_not_typename): Use copy_name to + set current_type variable for fields of THIS. + +2002-11-12 Daniel Jacobowitz + + * gnu-nat.c (init_gnu_ops): Remove NULL initializations. + * monitor.c (init_base_monitor_ops): Likewise. + * ppc-bdm.c (init_bdm_ppc_ops): Likewise. + * remote-array.c (init_array_ops): Likewise. + * remote-e7000.c (init_e7000_ops): Likewise. + * remote-es.c (init_es1800_ops): Likewise. + (init_es1800_child_ops): Likewise. + * remote-rdp.c (init_remote_rdp_ops): Likewise. + * remote-sim.c (init_gdbsim_ops): Likewise. + * remote-st.c (init_st2000_ops): Likewise. + * sol-thread.c (init_sol_core_ops): Likewise. + (init_sol_thread_ops): Likewise. + * v850ice.c (init_850ice_ops): Likewise. + * win32-nat.c (init_child_ops): Likewise. + * wince.c (init_child_ops): Likewise. + +2002-11-12 Andrew Cagney + + * utils.c (gdb_realpath): Make rp a constant pointer. + +2002-11-12 Andrew Cagney + + * utils.c (gdb_realpath): Rewrite. Try, in order: realpath() with + a constant buffer; cannonicalize_file_name(); realpath() with a + pathconf() defined buffer, xstrdup(). + +2002-11-12 Andrew Cagney + + * config/djgpp/fnchange.lst: Fix typo, hang1.c to hang1.C; hang2.c + to hang2.C; hang3.c to hang3.C. + +2002-11-11 Elena Zannoni + + * findvar.c (read_var_value): Reenable TLS code. + +2002-11-11 Elena Zannoni + Jim Blandy + + * gdb_thread_db.h (enum): Add TD_NOTALLOC. + * target.c (update_current_target): Add + to_get_thread_local_address. + * target.h (to_get_thread_local_address): Export. + (target_get_thread_local_address): Define. + (target_get_thread_local_address_p): Define. + * thread-db.c: Include solib-svr4.h. + (td_thr_tls_get_addr_p): Define. + (thread_db_load): Get a pointer to td_thr_tls_get_addr. + (thread_db_get_thread_local_address): New function. + (init_thread_db_ops): Initialize to_get_thread_local_address. + * configure.in: Add test for TD_NOTALLOC in thread_db.h. + * configure: Regenerate. + * config.in: Regenerate. + +2002-11-11 David Carlton + + * linespec.c (set_flags): New function. + (decode_line_1): Move code into set_flags. + +2002-11-11 David Carlton + + * linespec.c (decode_line_1): Move chunks of code to separate + functions. + (initialize_defaults): New function. + (decode_indirect): New function. + +2002-11-11 Andrew Cagney + + * blockframe.c (sigtramp_saved_pc): Fix tipo. void_func_ptr + instead of void_code_ptr. + (sigtramp_saved_pc): Ditto. + + * x86-64-tdep.c (i386_fp_regnum_p): Copy i386-tdep.c's + i386_fp_regnum_p. + +2002-11-10 Daniel Jacobowitz + + * gdbtypes.h (struct main_type): Move artificial flag out of + loc. New member of ``struct field'' named static_kind. Reduce + overloaded meaning of bitsize. + (FIELD_ARTIFICIAL, SET_FIELD_PHYSNAME, SET_FIELD_PHYSADDR) + (TYPE_FIELD_STATIC, TYPE_FIELD_STATIC_HAS_ADDR): Likewise. + (FIELD_STATIC_KIND, TYPE_FIELD_STATIC_KIND): New macros. + + * ada-lang.c (fill_in_ada_prototype): Initialize static_kind for + new fields. + (template_to_fixed_record_type, template_to_static_fixed_type) + (to_record_with_fixed_variant_part): Likewise. + * coffread.c (coff_read_struct_type, coff_read_enum_type): Likewise. + * dwarf2read.c (dwarf2_add_field, read_enumeration): Likewise. + * dwarfread.c (struct_type, enum_type): Likewise. + * hpread.c (hpread_read_enum_type) + (hpread_read_function_type, hpread_read_doc_function_type) + (hpread_read_struct_type): Likewise. + * mdebugread.c (parse_symbol): Likewise. + +2002-11-10 Andrew Cagney + + * breakpoint.h (deprecated_frame_in_dummy): Rename frame_in_dummy. + * stack.c (print_frame_info_base): Update. + (print_frame_info_base, frame_info): Update. + * sparc-tdep.c (sparc_init_extra_frame_info): Update. + (sparc_frame_saved_pc): Update. + * ada-lang.c (find_printable_frame): Update. + * breakpoint.c (deprecated_frame_in_dummy): Update. + +2002-11-09 Mark Kettenis + + * i386-linux-nat.c (ORIG_EAX): Define to -1 if not already + defined. + (regmap): Extend to cover all registers. + (PT_READ_U, PT_WRITE_U, PTRACE_XFER_TYPE, + OLD_CANNOT_FETCH_REGISTERS, OLD_CANNOT_STORE_REGISTERS): Remove + definitions. + (fetch_register, sore_register): Simplify. + (old_fetch_inferior_registers, old_store_inferior_registers): + Remove functions. + (cannot_fetch_register, cannot_store_register): Change + implementation to use regmap array to decide which registers + cannot be fetched/stored. This removes $orig_eax from the + registers that cannot be fetched/stored. + (fetch_inferior_registers): Call fetch_register directly instead + of calling old_fetch_inferior_registers. + (store_inferior_registers): Call store_register directly instead + of calling old_store_inferior_registers. + (i386_linux_dr_get): Replace PT_READ_U with PTRACE_PEEKUSER. + (i386_linux_dr_set): Replace PT_WRITE_U with PTRACE_POKEUSER. + * config/i386/nm-linux.h (U_REGS_OFFSET): Remove definition. + +2002-11-09 Klee Dienes + + * i387-tdep.c (i387_supply_register): When called with NULL as a + buffer, mark the register as not provided (to mirror the behavior + of supply_register). + (i387_supply_fxsave): Ditto. + (i387_supply_fsave): Ditto (inherits the behavior from + i387_supply_register). + +2002-11-09 Klee Dienes + + * blockframe.c (sigtramp_saved_pc): Use + builtin_type_void_code_ptr, not builtin_type_void_data_ptr (we are + extracting the PC). Use TYPE_LENGTH (builtin_type_void_code_ptr) + instead of (TARGET_PTR_BIT / TARGET_CHAR_BIT). + +2002-11-09 Andrew Cagney + + * frame.c (get_prev_frame): Test prev_p to identify a previously + unwound frame. Initialize prev_p. + * frame.h (struct frame_info): Add field prev_p. Expand prev/next + comment. + +2002-11-09 Andrew Cagney + + * frame.c (get_prev_frame): Cleanups. Eliminate redundant tests + for a NULL NEXT_FRAME. Simplify fromleaf initialization. Add + more comments. Zap dead code. + +2002-11-09 Mark Kettenis + + * infcmd.c (print_vector_info, print_float_info): Move code that + checks whether the target has any registers and whether there is a + selected frame up, such that it is also used if a target provides + multi-arch definitions of these functions. + +2002-11-08 Andrew Cagney + + * Makefile.in (DESTDIR): Define. + (install-only, install-gdbtk, uninstall-gdbtk): Add $(DESTDIR) + prefix. + + * config/djgpp/fnchange.lst: 8.3 proof i386obsd-nat.c and + i386obsd-tdep.c. Rename to "gdb.cxx", paths containing "gdb.c++". + +2002-11-08 Andrew Cagney + + * i386-linux-tdep.c: Include "reggroups.h". + (i386_linux_register_reggroup_p): New function. + (i386_linux_init_abi): Set register_reggroup_p to + i386_linux_register_reggroup_p. + * i386-tdep.h (i386_register_reggroup_p): Declare. + * i386-tdep.c: Include "reggroups.h". + (i386_init_reggroups): New function. + (i386_add_reggroups): New function. + (i386_register_reggroup_p): New function. + (i386_sse_reggroup, i386_mmx_reggroup): New variables. + (_initialize_i386_tdep): Call i386_init_reggroups. + (i386_gdbarch_init): Set register_reggroup_p and add in the i386 + specific reggroups. + +2002-11-09 Mark Kettenis + + * infptrace.c (child_xfer_memory): Make use of the new PT_IO + request that's available in *BSD. + + * i386-tdep.h (IS_FPU_CTRL_REGNUM): Remove. + + * i387-tdep.c (i387_fill_fxsave): Use FOOFF_REGNUM instead of + FDOFF_REGNUM. + +2002-11-08 Andrew Cagney + + * frame.c (set_unwind_by_pc): Use dummy_frame_register_unwind. + * dummy-frame.c (find_dummy_frame): Rename + generic_find_dummy_frame, make static. Return the dummy frame + instead of the regcache. + (generic_find_dummy_frame): Re-implement using find_dummy_frame, + (cached_find_dummy_frame): New function. Use find_dummy_frame. + (dummy_frame_register_unwind): Rename + generic_call_dummy_register_unwind. Use cached_find_dummy_frame. + * dummy-frame.h (dummy_frame_register_unwind): Rename + generic_call_dummy_register_unwind. + +2002-11-08 Mark Kettenis + + * config/i386/tm-i386v42mp.h: Remove file. Move its contents, + except the inclusion of "i386/tm-i386.h", to... + * config/i386/nm-i386v42mp.h: ...here. + * config/i386/i386v42mp.mt (TM_FILE): Set to tm-i386.h. + +2002-11-08 Andrew Cagney + + * Makefile.in (frame.o): Update dependencies. + * blockframe.c (current_frame, frame_obstack_alloc) + (frame_saved_regs_zalloc, get_current_frame) + (set_current_frame, create_new_frame) + (set_unwind_by_pc, get_next_frame) + (flush_cached_frames, reinit_frame_cache) + (frame_saved_regs_register_unwind) + (deprecated_generic_get_saved_register) + (get_prev_frame, get_frame_pc, get_frame_saved_regs) + (_initialize_blockframe): Move frame code from here... + * frame.c: ...to here. Include "gdb_obstack.h", "gdbcore.h", + "annotate.h" and "dummy-frame.h". + (_initialize_frame): New function. + +2002-11-08 Jim Blandy + + * dwarf2read.c (read_func_scope): Restore list_in_scope properly + when we finish a function a context. + * buildsym.h (outermost_context_p): New macro. + (Bug analyzed by David Edelsohn.) + +2002-11-08 Andrew Cagney + + * blockframe.c: Include "dummy-frame.h". + (struct dummy_frame, dummy_frame_stack) + (generic_find_dummy_frame, deprecated_generic_find_dummy_frame) + (generic_pc_in_call_dummy, deprecated_read_register_dummy) + (generic_push_dummy_frame, generic_save_dummy_frame_tos) + (generic_save_call_dummy_addr, generic_pop_current_frame) + (generic_pop_dummy_frame, generic_fix_call_dummy) + (generic_fix_call_dummy, generic_call_dummy_register_unwind): Move + dummy frame code from here... + * dummy-frame.c: ...to here. New file. + * dummy-frame.h: New file. + (generic_call_dummy_register_unwind): Declare. + (generic_find_dummy_frame): Declare. + * Makefile.in (SFILES): Add dummy-frame.c. + (dummy-frame.o): Specify dependencies. + (dummy_frame_h): Define. + (COMMON_OBS): Add dummy-frame.o. + (blockframe.o): Update dependencies. + +2002-11-08 Jim Blandy + + * dwarf2read.c (read_func_scope): Restore local_symbols and + param_symbols after we finish the function context. (Based on a + patch from David Edelsohn.) + +2002-11-08 David Carlton + + * linespec.c (symbol_found): New function. + (minsym_found): New function. + (decode_line_1): Separate out some code into separate functions. + +2002-11-08 Joel Brobecker + + * i386-tdep.c (i386_frameless_signal_p): Make non static for + the benefit of the interix target. + * i386-tdep.h (i386_frameless_signal_p): Declare. + +2002-11-08 Andrew Cagney + + * i386-tdep.h (i386_linux_orig_eax_regnum_p): Delete stray + declaration that snuck in from change below. + +2002-11-06 Andrew Cagney + + * i386-tdep.c (i386_mmx_regnum_p): Rename mmx_regnum_p. Update + all callers. + (i386_fp_regnum_p): New function. Use instead of FP_REGNUM_P. + (i386_fpc_regnum_p): New function. Use instead of FPC_REGNUM_P. + (i386_sse_regnum_p): New function. Use instead of SSE_REGNUM_P. + (i386_mxcsr_regnum_p): new function. Use instead of + MXCSR_REGNUM_P. + * i386-tdep.h (SSE_REGNUM_P): Delete macro. + (i386_sse_regnum_p): Declare. + (i386_mxcsr_regnum_p): Declare. + (FP_REGNUM_P, FPC_REGNUM_P): Delete macros. + (i386_fp_regnum_p, i386_fpc_regnum_p): Declare. + (IS_FP_REGNUM): Update definition. + (IS_FPU_CTRL_REGNUM): Update definition.. + (IS_SSE_REGNUM): Update definition.. + * i386v-nat.c (register_u_addr): Update. + * go32-nat.c (fetch_register): Update. + (store_register): Update. + +2002-11-07 Joel Brobecker + + Preparation work to convert the hppa targets to multiarch partial. + + * hppa-tdep.c: Add new functions replacing macro bodies from + config/pa/tm-hppa.h. These function will be used to initialize + the gdbarch structure. Import some comments from tm-hppa.h, + and place them where appropriate, to avoid loosing them when + we cleanup this file. + (hppa_reg_struct_has_addr): New function. + (hppa_inner_than): New function. + (hppa_stack_align): New function. + (hppa_pc_requires_run_before_use): New function. + (hppa_instruction_nullified): New function. + (hppa_register_byte): New function. + (hppa_register_virtual_type): New function. + (hppa_store_struct_return): New function. + (hppa_cannot_store_register): New function. + (hppa_frame_args_address): New function. + (hppa_frame_locals_address): New function. + (hppa_smash_text_address): New function. + (hppa_coerce_float_to_double): New function. Requires the inclusion + of "language.h". + + * Makefile.in (hppa-tdep.o): Add dependency on language.h. + + * tm-hppa.h (REG_STRUCT_HAS_ADDR): Change the definition of this + gdbarch-eligible macro to a call to the new associated function + created in hppa-tdep.c. + (INNER_THAN): Likewise. + (STACK_ALIGN): Likewise. + (PC_REQUIRES_RUN_BEFORE_USE): Likewise. + (INSTRUCTION_NULLIFIED): Likewise. + (REGISTER_BYTE): Likewise. + (REGISTER_VIRTUAL_TYPE): Likewise. + (STORE_STRUCT_RETURN): Likewise. + (CANNOT_STORE_REGISTER): Likewise. + (FRAME_ARGS_ADDRESS): Likewise. + (FRAME_LOCALS_ADDRESS): Likewise. + (SMASH_TEXT_ADDRESS): Likewise. + (COERCE_FLOAT_TO_DOUBLE): Likewise. + (ABOUT_TO_RETURN): Delete, as no longer used. + +2002-11-07 Fernando Nasser + + * printcmd.c (disassemble_command): Remove obsolete function. + (_initialize_printcmd): Do not create disassemble command here. + * cli/cli-cmds.c (disassemble_command): New function. Implements + disassemble command. + (init_cli_cmds): Create disassemble command here instead. + +2002-11-07 Andrew Cagney + + * MAINTAINERS: Add Daniel Jacobowitz to global maintainers list. + +2002-11-07 Andrew Cagney + + * regcache.h (regcache_cooked_read_using_offset_hack) + (regcache_cooked_write_using_offset_hack): Delete declarations. + (register_changed): Delete declaration. + * regcache.c (regcache_cooked_read_using_offset_hack) + (regcache_cooked_write_using_offset_hack): Delete functions. + (cooked_xfer_using_offset_hack): Delete function. + (register_changed): Delete function. + +2002-11-07 Jim Blandy + + * macroscope.c: #include "complaints.h". + (sal_macro_scope): Cope with filenames that appear in the symtabs, + but not in the macro table. + * Makefile.in (macroscope.o): Record dependency. + +2002-11-07 Joel Brobecker + + * PROBLEMS: Document gdb/816 (unable to read core file on alpha-osf). + +2002-11-07 Andrew Cagney + + * regcache.c (deprecated_registers_fetched): Update. + * regcache.h (deprecated_registers_fetched): Rename + registers_fetched. + * remote-vxsparc.c (vx_read_register): Update. + * remote-vxmips.c (vx_read_register): Update. + * remote-vx68.c (vx_read_register): Update. + * irix5-nat.c (fetch_core_registers): Update. + * mipsm3-nat.c (fetch_inferior_registers): Update. + * sun3-nat.c (fetch_inferior_registers): Update. + * symm-nat.c (fetch_inferior_registers): Update. + * ns32knbsd-nat.c (fetch_inferior_registers): Update. + (fetch_core_registers): Update. + (fetch_kcore_registers): Update. + * mips-nat.c (fetch_inferior_registers): Update. + * corelow.c (get_core_registers): Update. + * a68v-nat.c (fetch_inferior_registers): Update. + +2002-11-06 Joel Brobecker + + Put in place the framework necessary for multiarching the hppa targets. + * hppa-tdep.c (hppa_gdbarch_init): New function. + (hppa_dump_tdep): New function. + (_initialize_hppa_tdep): Register the hppa gdbarch init function and + tdep structure dumper. + * config/pa/tm-hppa.h (GDB_MULTI_ARCH): New macro, defined to 0 + until the multi-arching conversion has partially been completed. + +2002-11-06 Andrew Cagney + + * valops.c (value_assign): Merge lval_register case into + lval_reg_frame_relative. Use frame_register and + regcache_cooked_write instead of get_saved_register and + write_register_bytes. After flushing the register cache, try to + re-select the selected frame. + +2002-11-06 Andrew Cagney + + * regcache.h (deprecated_register_valid): Rename register_valid. + * regcache.c: Update. + * ia64-aix-nat.c: Update. + * i386gnu-nat.c: Update. + * alpha-nat.c: Update. + * sparc-nat.c: Update. + * lynx-nat.c: Update. + * remote-mips.c: Update. + +2002-11-06 Joel Brobecker + + * hppa-tdep.c (_initialize_hppa_tdep): Move function body + to end of file, to be more consistent with the pratice followed + by other targets. + +2002-11-06 Andrew Cagney + + * infcmd.c: Include "reggroups.h" and . + (print_float_info): Print registers in float_reggroup. + (print_vector_info): Print registers in vector_reggroup. + (default_print_registers_info): When all, print registers in + all_reggroup. Otherwize, print registers in general_reggroup. + (registers_info): Rewrite. Add support for register groups. + Eliminate a goto. + +2002-11-06 Elena Zannoni + + * symtab.c (methods_info): Delete. It has been ifdeffed out for + ages. + (symtab_symbol_info): Remove eons old ifdeffed out code. + (_initialize_symtab): Remove prehistoric disabled 'info methods' + command. + +2002-11-06 Theodore A. Roth + + * c-exp.y: Add missing semi-colons. + * f-exp.y: Add missing semi-colons. + * m2-exp.y: Add missing semi-colons. + * p-exp.y: Add missing semi-colons. + Add empty action to start rule to avoid a type clash error when + building with bison >= 1.50. + +2002-11-06 Jim Blandy + + * macrotab.h (struct macro_source_file): Doc fix. + +2002-11-05 Jeff Johnston + + * varobj.c (child_exists, cplus_number_of_children): Change + STREQ macro references to strcmp. + (cplus_name_of_child): Change code to handle the fact that + fields are not necessarily contiguous with regards to their + access control. This is a fix for PR gdb/792. + +2002-11-05 Andrew Cagney + + * gdbarch.sh (GET_SAVED_REGISTER): Change to a predicate function. + * gdbarch.h, gdbarch.c: Regnerate. + * frame.h (frame_register): Declare. + * frame.c (frame_register): New function. + (get_saved_register): Test GET_SAVED_REGISTER_P before calling + GET_SAVED_REGISTER, otherwize call + generic_unwind_get_saved_register. + (frame_register_read): Use frame_register instead of + get_saved_register. + +2002-11-05 Elena Zannoni + + From Jim Ingham : + * event-top.c (gdb_disable_readline): New function. + (_initialize_event_loop): Move comment. + +2002-11-05 Elena Zannoni + + * event-loop.c (start_event_loop): Add comment. + Update copyright. + +2002-11-05 Andrew Cagney + + * infcmd.c (default_print_registers_info): Do not call + PRINT_REGISTER_HOOK. + +2002-11-05 Andrew Cagney + + * sparc-tdep.c (sparc_print_register_hook): Make static. + (sparc_print_registers_info): New function. + (sparc_do_registers_info): New function. + (sparclet_print_registers_info): New function. + (sparclet_do_registers_info): New function. + (do_sparc_print_registers_info): New function. + (sparc_print_registers): New static function, clone of infcmd.c's + default_print_registers_info. + * config/sparc/tm-sparclet.h (PRINT_REGISTER_HOOK): Delete macro. + (sparclet_do_registers_info): Declare. + (DEPRECATED_DO_REGISTERS_INFO): Re-define. + * config/sparc/tm-sparc.h (DEPRECATED_DO_REGISTERS_INFO): + Re-define. + (sparc_do_registers_info): Declare. + (PRINT_REGISTER_HOOK): Delete macro. + (sparc_print_register_hook): Delete declaration. + +2002-11-05 David Carlton + + * symtab.c (lookup_symbol_aux): Move chunks of code into separate + functions. + (lookup_symbol_aux_local): New function. + (lookup_symbol_aux_symtabs): New function. + (lookup_symbol_aux_psymtabs): New function. + +2002-11-05 David Carlton + + * symtab.c (lookup_symbol_aux): In minsym sections, don't use the + previous values of 'objfile' and 'block'. + +2002-11-05 Pierre Muller + + * values.c (value_change_enclosing_type): Set + enclosing_type field correctly also for the case where + more memory needs to be allocated. + +2002-11-03 Mark Kettenis + + * i387-tdep.c (i387_print_float_info): Call fputs_filtered instead + of puts_filtered. + + * i387-tdep.c (i387_print_float_info): Replace calls to + register_read and deprecated_read_register_gen with calls to + frame_register_read, and make the necessary adjustments to the + surrounding code. + +2002-11-02 Andrew Cagney + + * gdbarch.sh (register_reggroup_p): Allow default value. + * gdbarch.h, gdbarch.c: Regenerate. + +2002-11-02 Andrew Cagney + + * regcache.h: Add coment indicating replacements for deprecated + functions. + +2002-11-02 Andrew Cagney + + * reggroups.h, reggroups.c: New files. + * regcache.c: Include "reggroups.h". + (enum regcache_dump_what): Add `regcache_dump_groups'. + (regcache_dump): Contract size of the "Type" column. When + specified, dump the register's groups. + (maintenance_print_register_groups): New function. + (_initialize_regcache): Add command `maint print register-groups'. + * Makefile.in (COMMON_OBS): Add reggroups.o + (SFILES): Add reggroups.c. + (reggroups_h): Define. + (regcache.o, gdbarch.o): Update dependencies. + (reggroups.o): Specify dependencies. + * gdbarch.sh (register_reggroup_p): Add pure multi-arch method. + Add opaque declaration for `struct reggroup' in generated .h file. + Include "reggroups.h" in generated .c file. + gdbarch.h, gdbarch.c: Re-generate. + +2002-11-02 Andrew Cagney + + * regcache.h (deprecated_read_register_gen): Rename + read_register_gen. + (deprecated_write_register_gen): Rename write_register_gen. + * i387-tdep.c: Update. + * x86-64-linux-nat.c: Update + * wince.c: Update. + * thread-db.c: Update. + * win32-nat.c: Update. + * mips-tdep.c: Update. + * d10v-tdep.c: Update. + * cris-tdep.c: Update. + * remote-sim.c: Update. + * remote-rdi.c: Update. + * remote-rdp.c: Update. + * frame.c: Update. + * target.c: Update. + * blockframe.c: Update. + * x86-64-tdep.c: Update. + * xstormy16-tdep.c: Update. + * sh-tdep.c: Update. + * s390-tdep.c: Update. + * rs6000-tdep.c: Update. + * sparc-tdep.c: Update. + * i386-tdep.c: Update. + * dwarf2cfi.c: Update. + * regcache.c: Update. + +2002-11-01 Joel Brobecker + + New interix-specific files: + * config/i386/nm-interix.h: New file. + * config/i386/interix.mh: New file. + * config/i386/interix.mt: New file. + * i386-interix-nat.c: New file. + * i386-interix-tdep.c: New file. + +2002-11-01 Andrew Cagney + + * frame.h (deprecated_generic_get_saved_register): Rename + generic_get_saved_register. + * blockframe.c (deprecated_generic_get_saved_register): Update. + * xstormy16-tdep.c (xstormy16_get_saved_register): Update. + (xstormy16_frame_saved_register): Update. + * sh-tdep.c (sh_gdbarch_init): Update. + * m68hc11-tdep.c (m68hc11_gdbarch_init): Update. + * ia64-tdep.c (ia64_get_saved_register): Update. + * cris-tdep.c (cris_gdbarch_init): Update. + * config/m32r/tm-m32r.h (GET_SAVED_REGISTER): Update. + * arm-tdep.c (arm_gdbarch_init): Update. + +2002-10-31 Daniel Jacobowitz + + * lin-lwp.c (lin_lwp_resume): Remove resume_all test for !step. + +2002-10-31 Daniel Jacobowitz + + * i386-linux-tdep.c (i386_linux_pc_in_sigtramp): Check for + trampolines in sigaction. + +2002-10-31 Andrew Cagney + + * h8300-tdep.c: Include "gdb_assert.h". + (h8300_print_register): Add gdbarch, file and frame parameters. + Use frame_read_unsigned_register to read the register's value. + Use fprintf_filtered to display output. + (h8300_print_registers_info): Replace h8300_do_registers_info. + (h8300_gdbarch_init): Set print_registers_info. + +2002-10-31 Andrew Cagney + + * frame.c (frame_read_unsigned_register): New function. + (frame_read_signed_register): New function. + * frame.h (frame_read_unsigned_register): Declare. + (frame_read_signed_register): Declare. + +2002-10-31 Andrew Cagney + + * h8500-tdep.c (h8500_print_registers_info): New static function, + clone of infcmd.c's default_print_registers_info. + (h8500_do_registers_info): New funtion. + (h8500_print_register_hook): Rename print_register_hook, make + static. + + * config/h8500/tm-h8500.h: Update copyright. + (DEPRECATED_DO_REGISTERS_INFO): Define. + (h8500_do_registers_info: Declare. + (PRINT_REGISTER_HOOK): Delete macro. + (print_register_hook): Delete function. + +2002-10-31 Andrew Cagney + + * z8k-tdep.c (z8k_print_register_hook): Make static. + (z8k_print_registers_info): New static function, clone of + infcmd.c's default_print_registers_info. + (z8k_do_registers_info): New function. Wrap + z8k_print_registers_info. + * config/z8k/tm-z8k.h: Update copyright. + (PRINT_REGISTER_HOOK): Delete macro. + (z8k_print_register_hook): Delete declaration. + (DEPRECATED_DO_REGISTERS_INFO): Define. + (z8k_do_registers_info): Declare. + +2002-10-30 Joel Brobecker + + * hppa-tdep.c (find_function_in_inferior): Remove this extern, + as this is already provided by value.h, and was actually causing + a compilation error because of a conflict in parameter type + declaration due to a missing const keyword. + (low_text_segment_addres): Fix a compilation warning. + +2002-10-29 Daniel Jacobowitz + + * mips-linux-nat.c (mips_linux_cannot_fetch_register): Don't fetch + registers without a name. + (mips_linux_cannot_store_register): Don't store registers without + a name. + +2002-10-28 David Carlton + + * symtab.c (find_addr_symbol): Delete. (It was already commented + out.) + * symtab.h: Delete prototype for find_addr_symbol. + +2002-10-26 Andrew Cagney + + * gdbarch.sh (DEPRECATED_DO_REGISTERS_INFO): Rename + DO_REGISTERS_INFO. + gdbarch.h, gdbarch.c: Re-generate. + * infcmd.c (default_print_registers_info): Update reference. + * mips-tdep.c (mips_gdbarch_init): Set deprecated_do_registers_info. + (mips_dump_tdep): Do not print DO_REGISTERS_INFO. + * sh-tdep.c (sh_gdbarch_init): Ditto. + * mn10300-tdep.c (mn10300_gdbarch_init): Ditto. + * h8300-tdep.c (h8300_gdbarch_init): Ditto. + +2002-10-26 Mark Kettenis + + * x86-64-tdep.c (x86_64_init_abi): Set init_extra_frame_info to + cfi_init_extra_frame_info. + * x86-64-tdep.h (x86_64_init_extra_frame_info): Remove prototype. + * x86-64-linux-tdep.c (x86_64_init_extra_frame_info): Remove function. + + * x86-64-tdep.c (x86_64_init_abi): Add calls to override the i386 + target where necessary. Add more comments and remove the ones + that don't provide any useful information. + + * i386-tdep.c (i386_frame_saved_pc): Replace call to + deprecated_read_register_dummy with + frame_unwind_unsigned_register. + + * i386-tdep.c (i386_extract_struct_value_address): Use + regcache_raw_read_unsigned instead of + regcache_cooked_read_unsigned since we know that the register + we're reading isn't a pseudo register. Rename variable 'val' into + the more descriptive 'addr'. + + * x86-64-tdep.c: Fix some formatting problems, mostly in comments. + (x86_64_push_return_address): Add comment. + (x86_64_pop_frame): Make static. + (examine_argument): Clarify comment. + (x86_64_skip_prologue): Make prolog_expact variable static. + + * dwarf2cfi.c: Fix some formatting problems. + (context_cpy, read_encoded_pointer): Clarify comments. + + * x86-64-tdep.c (x86_64_breakpoint_from_pc): Constify. + (x86_64_init_abi): Move set_gdbarch_* calls that overlap with the + i386 target back into x86_64_gdbarch_init. Add some comments and + remove meaningless ones. + +2002-10-25 Andrew Cagney + + * complaints.h (struct deprecated_complaint): Rename `struct + complaint'. + * complaints.c (complain): Update. + * remote-vx68.c, remote-vxmips.c, remote-vxsparc.c: Delete + incorrect comment indicating that "symfile.h" was being included + for the `struct complaint' definition. + * remote-vx.c: Update. + * objc-lang.c: Update. + * xcoffread.c: Update. + * hpread.c: Update. + * mdebugread.c: Update. + * stabsread.c: Update. + * dwarf2read.c: Update. + * dwarfread.c: Update. + * elfread.c: Update. + * coffread.c: Update. + * stabsread.h: Update. + * dbxread.c: Update. + * buildsym.c: Update. + * gdbtypes.c: Update. + * macrotab.c: Update. + +2002-10-25 Mark Kettenis + + * x86-64-tdep.c (x86_64_gdbarch_init): Make a bit more similar to + the version in i386-tdep.c. Move set_gdbarch_* calls out into... + (x86_64_init_abi): ...new function. + + * Makefile.in (i386v-nat.o): Add $(i386_tdep_h). + * i386v-nat.c: Include "i386-tdep.h". + +2002-10-25 Andrew Cagney + + * gdbtypes.c (address_space_name_to_int): Update. + (address_space_int_to_name): Update. + * gdbarch.sh (address_class_type_flags_to_name): Change to a pure + multi-arch predicate. + (address_class_name_to_type_flags): Ditto. + * gdbarch.h, gdbarch.c: Re-generate. + + * MAINTAINERS: Check all warnings when h8300hms and alpha-elf. + +2002-10-24 Martin M. Hunt + + * utils.c (string_to_core_addr): Revert patch from 11 Oct. + +2002-10-24 Elena Zannoni + + * symtab.h (INIT_SAL): Delete macro. + (init_sal): Export. + * symtab.c (init_sal): New function. + + * ada-lang.c (ada_finish_decode_line_1): Change INIT_SAL macro + to init_sal function call. + (find_sal_from_funcs_and_line): Ditto. + (all_sals_for_line): Ditto. + * breakpoint.c (create_internal_breakpoint): Ditto. + (create_fork_vfork_event_catchpoint): Ditto. + (create_exec_event_catchpoint): Ditto. + (parse_breakpoint_sals): Ditto. + (watch_command_1): Ditto. + (handle_gnu_4_16_catch_command): Ditto. + (clear_command): Ditto. + * hppa-tdep.c (child_enable_exception_callback): Ditto. + * infcmd.c (run_stack_dummy): Ditto. + * infrun.c (process_event_stop_test): Ditto. + (check_sigtramp2): Ditto. + (step_over_function): Ditto. + * linespec.c (decode_line_2): Ditto. + (decode_line_1): Ditto. + * source.c (line_info): Ditto. + * symtab.c (find_pc_sect_line): Ditto. + +2002-10-24 Michal Ludvig + + * dwarf2cfi.c (struct context) + (struct context_reg): Moved to dwarf2cfi.h + (context_alloc, frame_state_alloc, context_cpy): + Made extern instead of static, removed prototypes. + * dwarf2cfi.h (struct context) + (struct context_reg): New, moved from dwarf2cfi.c + (context_alloc, frame_state_alloc, context_cpy): + New prototypes. + * x86-64-linux-tdep.c (x86_64_linux_sigtramp_saved_pc): + Changed from static to extern. + (LINUX_SIGINFO_SIZE, LINUX_SIGCONTEXT_PC_OFFSET) + (LINUX_SIGCONTEXT_FP_OFFSET) + (LINUX_UCONTEXT_SIGCONTEXT_OFFSET): Adjusted. + (x86_64_linux_in_sigtramp, x86_64_linux_frame_chain) + (x86_64_init_frame_pc, x86_64_init_extra_frame_info): New. + * x86-64-tdep.c (x86_64_gdbarch_init): Several + set_gdbarch_*() calls now use x86-64 specific functions + instead of DWARF2 CFI ones. + * x86-64-tdep.h (x86_64_linux_in_sigtramp) + (x86_64_linux_frame_chain, x86_64_init_frame_pc) + (x86_64_init_extra_frame_info): New prototypes. + +2002-10-23 David Carlton + + * linespec.c: #include "parser-defs.h". + Delete prototype for find_template_name_end. + * Makefile.in (linespec.o): Depend on $(parser_defs_h). + +2002-10-23 Jeff Johnston + + * NEWS: add recent mi fixes. + * varobj.c (struct varobj): Add new "updated" flag. + (new_variable): Default "updated" flag to 0. + (varobj_set_value): Set "updated" flag to 1 if value + changes. + (varobj_update): Check varobj "updated" flag before + comparing old and refreshed values. Fix for + PR gdb/702. + +2002-10-23 David Carlton + + * parse.c (parse_exp_1): Use BLOCK_START. + * x86-64-tdep.c (x86_64_skip_prologue): Use BLOCK_END, + SYMBOL_BLOCK_VALUE. + * objc-lang.c (find_methods): Use BLOCK_START, BLOCK_END. + +2002-10-23 David Carlton + + * symtab.c: Delete cplusplus_hint. + Delete prototype for find_template_name_end. + +2002-10-23 Elena Zannoni + + * symtab.h: Update comment. + +2002-10-23 Michael Snyder + + * printcmd.c (address_info): Restore quotes in output. + * valops.c (value_of_local): Restore quotes in error message. + +2002-10-23 Elena Zannoni + + * symtab.c (symbol_demangled_name): New function. + * symtab.h (SYMBOL_DEMANGLED_NAME): Simplify macro, by + turning most of it into a function. + (symbol_demangled_name): Export. + +2002-10-23 Michael Snyder + + * valops.c (value_of_local): Restore quotes in error message. + +2002-10-23 Elena Zannoni + + * symtab.c (symbol_init_language_specific): New function. + * symtab.h (SYMBOL_INIT_LANGUAGE_SPECIFIC): Simplify macro, by + turning most of it into a function. + (symbol_init_language_specific): Export. + +2002-10-23 David Carlton + + * dwarf2read.c (dwarf_tag_name): Add DWARF 3 names. + (dwarf_attr_name): Ditto. + (dwarf_type_encoding_name): Ditto. + (scan_partial_symbols): Descend into DW_TAG_namespace entries. + (process_die): Handle DW_TAG_namespace, + DW_TAG_imported_declaration, DW_TAG_imported_module. + (read_namespace): New function. + +2002-10-22 Joel Brobecker + + * configure.in: Define NEW_PROC_API on Interix too. + * configure: Regenerate. + +2002-10-21 Joel Brobecker + + * configure: Regenerate using the proper version of autoconf. + +2002-10-21 Elena Zannoni + + * findvar.c (read_var_value): Temporarily disable TLS code, until + complete TLS support is added. + +2002-10-21 Jim Blandy + Elena Zannoni + + * symtab.h (address_class): Re-add LOC_THREAD_LOCAL_STATIC + for thread local storage locations. + (struct symbol): Add objfile field. + (SYMBOL_OBJFILE): Define. + * dwarf2read.c (is_thread_local): New static variable. + (new_symbol): If variable is in thread local fill in address class + and objfile appropriately. + (decode_locdesc): Recognize and handle DW_OP_GNU_push_tls_address + stack operation. + * printcmd.c (address_info): Print the information for thread + local storage variable. + * findvar.c (read_var_value): In case of thread local variable, + defer to the target vector code to compute address. + +2002-10-21 Elena Zannoni + + * solib-svr4.c (svr4_fetch_objfile_link_map): New function. + * solib-svr4.h (svr4_fetch_objfile_link_map): Export. + +2002-10-21 Elena Zannoni + + * symtab.h (address_class): Rename + LOC_THREAD_LOCAL_STATIC to LOC_HP_THREAD_LOCAL_STATIC. + * hpread.c (hpread_process_one_debug_symbol): Ditto. + * printcmd.c (address_info): Ditto. + * findvar.c (symbol_read_needs_frame, read_var_value): Ditto. + +2002-10-20 Mark Kettenis + + * i386bsd-nat.c (i386bsd_dr_set, i386bsd_dr_get_status): Use + DBREG_DRX macro to acces debug registers. + + * Makefile.in (i386obsd-tdep.o): New target. + + * solib-sunos.c: Include "bcache.h" and "regcache.h". + * Makefile.in (solib-sunos.o): Add $(bcache_h) and $(regcache_h). + + * configure.tgt (i[3456]86-*-openbsd*): Set gdb_target to obds. + * config/i386/obsd.mt: New file. + * i386bsd-nat.c (_initialize_i386bsd_nat): Introduce + i386obsd_sc_pc_offset and i386obsd_sc_sp_offset; + * i386obsd-nat.c (_initialize_i386obsd_nat): Set + i386obsd_sigtramp_start and i386obsd_sigtramp_end instead of + i386nbsd_sigtramp_start and i386nbsd_sigtramp_end. + * i386obsd-tdep.c: New file. + +2002-10-19 Adam Fedor + + * objc-exp.y (name_not_typename): Fix invalid comment. + +2002-10-20 Mark Kettenis + + * solib-sunos.c (allocate_rt_common_objfile): Use bcache_xmalloc + to allocate partial syms and macro byte caches. + +2002-10-18 David Carlton + + * symtab.h: Delete 'struct source' and 'struct sourcevector'. + +2002-10-18 Adam Fedor + + * stabsread.c (find_name_end): New function. + (define_symbol): Use it. + +2002-10-18 Daniel Jacobowitz + + * config/alpha/nm-fbsd.h (CANNOT_STEP_BREAKPOINT): Define to 1. + * config/alpha/nm-linux.h (CANNOT_STEP_BREAKPOINT): Define to 1. + * config/alpha/nm-nbsd.h (CANNOT_STEP_BREAKPOINT): Define to 1. + * config/alpha/nm-osf.h (CANNOT_STEP_BREAKPOINT): Define to 1. + +2002-10-17 David Carlton + + * symfile.h: Add opaque declaration for struct obstack. + Declare obsavestring to take a const char *. + * symfile.c (obsavestring): Make first argument a const char *. + +2002-10-16 Adam Fedor + + * breakpoint.c (parse_breakpoint_sals): Ignore ObjC method + names when matching breakpoints in current file. + +2002-10-16 Kevin Buettner + + * dwarf2read.c (dwarf2_invalid_pointer_size): New complaint. + (read_tag_pointer_type): Add address class support. + * gdbarch.sh (ADDRESS_CLASS_TYPE_FLAGS) + (ADDRESS_CLASS_TYPE_FLAGS_TO_NAME, ADDRESS_CLASS_NAME_TO_TYPE_FLAGS): + New methods. + * gdbarch.h, gdbarch.c: Regenerate. + * gdbtypes.c (address_space_name_to_int, address_space_int_to_name) + (make_type_with_address_space, recursive_type_dump): Add address + class support. + * gdbtypes.h (TYPE_FLAG_ADDRESS_CLASS_1, TYPE_FLAG_ADDRESS_CLASS_2) + (TYPE_FLAG_ADDRESS_CLASS_ALL, TYPE_ADDRESS_CLASS_1) + (TYPE_ADDRESS_CLASS_2, TYPE_ADDRESS_CLASS_ALL): New defines + +2002-10-16 Klee Dienes + + * stabsread.c (read_tilde_fields): Use name[sizeof(vptr_name)-2] + to get the last character of a char[] buffer, not + name[sizeof(vptr_name)-1]. + +2002-10-14 Adam Fedor + + * symtab.h: New objc_specific struct. + (SYMBOL_INIT_LANGUAGE_SPECIFIC): Handle ObjC. + (SYMBOL_DEMANGLED_NAME): Likewise. + +2002-10-14 Adam Fedor + + * symfile.c (init_filename_language_table): Add ObjC file extension. + +2002-10-14 Adam Fedor + + * utils.c (puts_filtered_tabular): New function. + (fprintf_symbol_filtered): Get ObjC demangled name. + * defs.h (puts_filtered_tabular): Declared. + +2002-10-14 Kevin Buettner + + * c-lang.h (c_type_print_varspec_prefix): Delete. + * c-typeprint.c (c_type_print_varspec_prefix): Make static. Add + ``need_post_space'' parameter. Adjust all callers. + +2002-10-14 Daniel Jacobowitz + + * config/mips/nm-irix4.h (HAVE_NONSTEPPABLE_WATCHPOINT): Define to 1. + * config/mips/nm-irix5.h (HAVE_NONSTEPPABLE_WATCHPOINT): Likewise. + * config/mips/tm-embed.h (HAVE_NONSTEPPABLE_WATCHPOINT): Likewise. + * config/pa/nm-hppah.h (HAVE_NONSTEPPABLE_WATCHPOINT): Likewise. + +2002-10-13 Adam Fedor + + * source.c (print_source_lines): Update comments. + +2002-10-13 Adam Fedor + + * valops.c (value_of_local): New function. + (value_of_this): Use it. + * value.h (value_of_local): Declared. + +2002-10-13 Adam Fedor + + * parse.c: (length_of_subexp, prefixify_subexp): Handle + OP_MSGCALL, OP_SELECTOR, OP_NSSTRING, and OP_SELF. + +2002-10-12 Adam Fedor + + * language.c (binop_result_type): Add language_objc to case. + (integral_type): Likewise. + (character_type): Likewise. + (string_type): Likewise. + (boolean_type): Likewise. + (structured_type): Likewise. + (binop_type_check): Likewise. + +2002-10-11 Adam Fedor + + * printcmd.c (address_info): Print 'self' for ObjC. + +2002-10-11 Adam Fedor + + * expression.h: New ops OP_NSSTRING, OP_SELECTOR, OP_MSGCALL, and + OP_SELF. + +2002-10-11 Adam Fedor + + * language.h (CAST_IS_CONVERSION): Add language_objc. + +2002-10-11 Adam Fedor + + * defs.h (enum language): Add language_objc. + +2002-10-11 Klee Dienes + + * corefile.c (read_memory_typed_address): New function. + * gdbcore.h (read_memory_typed_address): Add prototype. + * blockframe.c (sigtramp_saved_pc): Use read_memory_typed_address + to read a value destined for a CORE_ADDR, not read_memory_integer. + * f-valprint.c (f77_get_dynamic_upperbound): Ditto. + (f77_get_dynamic_lowerbound): Ditto. + +2002-10-11 Martin M. Hunt + + * utils.c (string_to_core_addr): After turning string into + a number, convert to a CORE_ADDR using INTEGER_TO_ADDRESS + which will do necessary sign-extension, etc. + +2002-10-11 Daniel Jacobowitz + + * c-exp.y (THIS): Delete token and grammar rule. + (yylex): Don't return THIS. + * cp-valprint.c (vtbl_ptr_name_old): Delete. + (cp_is_vtbl_ptr_type): Don't check vtbl_ptr_name_old. + * demangle.c (cplus_markers): Update comment. Put '$' + first. Remove CPLUS_MARKER. + (_initialize_demangler): Don't call set_cplus_marker_for_demangling. + * jv-exp.y (THIS): Delete token and grammar rule. + (yylex): Don't return THIS. + * mips-tdep.c (mips_dump_tdep): Don't dump CPLUS_MARKER. + * objc-exp.y (THIS): Delete token and grammar rule. + (yylex): Don't return THIS. + * p-exp.y (yylex): Remove reference to CPLUS_MARKER. + * stabsread.c (vptr_name, vb_name): Replace CPLUS_MARKER with '$'. + (read_member_functions): Likewise for opname. + (read_tilde_fields): Use is_cplus_marker. + + * defs.h (CPLUS_MARKER): Don't define. + * config/tm-sysv4.h (CPLUS_MARKER): Likewise. + * config/i386/xm-i386sco.h (CPLUS_MARKER): Likewise. + * config/mips/tm-irix3.h (CPLUS_MARKER): Likewise. + * config/mips/tm-irix6.h (CPLUS_MARKER): Likewise. + * config/rs6000/tm-rs6000.h (CPLUS_MARKER): Likewise. + + * config/i386/tm-i386v4.h: Delete file. + * config/djgpp/fnchange.lst: Delete tm-i386v4.h. + * config/i386/tm-i386sol2.h: Include "i386/tm-i386.h" instead. + * config/i386/tm-i386v42mp.h: Include "i386/tm-i386.h" instead. + * config/i386/tm-ptx.h: Include "i386/tm-i386.h" instead. + * config/i386/i386gnu.mt (TM_FILE): Use tm-i386.h. + * config/i386/i386sco5.mt (TM_FILE): Likewise. + * config/i386/i386v4.mt (TM_FILE): Likewise. + * config/i386/ncr3000.mt (TM_FILE): Likewise. + +2002-10-10 Marko Mlinar + + * infrun.c (resume): Convert #ifdef HAVE_NONSTEPPABLE_WATCHPOINT into C, + accidentially not commited 2002-10-09 + * gdbarch.h, gdbarch.c: Re-generate. + +2002-10-09 Marko Mlinar + + * infrun.c (resume): Convert #ifdef HAVE_NONSTEPPABLE_WATCHPOINT into C. + * gdbarch.sh (HAVE_NONSTEPPABLE_WATCHPOINT): Add. + * gdbarch.h, gdbarch.c: Re-generate. + +2002-10-08 Petr Sorfa + + Revised and re-submitted by John Wolfe + + Move the Dwarf 2 abbrev table to a per-compilation-unit structure, + so we can work on more than one compilation unit at a time. This + helps prepare GDB to handle inter-CU die references. + * dwarf2read.c (ABBREV_HASH_SIZE): moved definition forward in + the code to be defined before struct comp_unit_head. + (comp_unit_head): Added new members - offset, cu_head, + begin_die, next and dwarf2_abbrevs. + (dwarf2_abbrevs): Removed single static var; now member of + struct comp_unit_head. + dwarf2_build_psymtabs_hard): Complete new struct comp_unit_head + members. + (psymtab_to_symtab_1): Changed to work with the new + struct comp_unit_head. + (dwarf2_read_abbrevs): Now accepts a cu_header parameter and + constructs the dwarf2_abbrevs[] inside the cu_header. + (dwarf2_empty_abbrev_table): Now expects a ptr to a + dwarf2_abbrev table to clean up. + (dwarf2_lookup_abbrev): Now accepts a cu_header parameter and + handling of dwarf2_abbrevs inside the cu_header. + (read_partial_die): Now supports the call to the new + dwarf2_lookup_abbrev. + (read_full_die): Now supports the call to the new + dwarf2_lookup_abbrev. + +2002-10-06 Christopher Faylor + + * Makefile.in (install-gdbtk): Add missing continuation backslash to + insure that shell variables, such as "transformed_name" are propagated + to later shell statements in rule. + +2002-10-06 Mark Kettenis + + * config/i386/nm-i386sco.h: Add protection against + multiple-inclusion. Include "i386/nm-i386v.h". + (REGISTER_U_ADDR): Remove define. + (i386_register_u_addr): Remove prototype. + +2002-10-04 Michael Snyder + + * m32r-stub.c (handle_exception): Make sure exception is "trap" + before treating it as a single-step event. + +2002-10-03 Adam Fedor + + * objc-lang.c: ARI fixes. Change string.h to gdb_string.h. + (objc_demangle): Remove assignment in if statements, Replace + free with xfree. + (add_msglist): Likewise. + (end_msglist): Likewise. + (complare_selectors): Likewise. + (selectors_info): Likewise. + (compare_classes): Likewise. + (classes_info): Likewise. + (print_object_command): Likewise. + (find_objc_msgcall_submethod): Replace PTR with void *. + * objc-lang.h: Remove check for __STDC__. + +2002-10-03 Jeff Johnston + + * ui-out.h (ui_out_field_fmt_int): New prototype. + * ui-out.c (ui_out_field_fmt_int): New function allowing specification + of field width and alignment. + * stack.c (print_frame_info_base): When printing frame level, use + ui_out_field_fmt_int with a width of 2 and left alignment. Fix for + PR gdb/192 + +2002-10-03 Jeff Johnston + + * MAINTAINERS: Add self to Write After Approval list. + +2002-10-02 Elena Zannoni + + * infcmd.c (interrupt_target_command_wrapper): Delete. + (interrupt_target_command): Make non static. + (nofp_registers_info): Make static. + * stack.c (return_command_wrapper): Delete. + (return_command): Make non static. + +2002-10-02 Elena Zannoni + + * event-top.c (gdb_setup_readline): New function. Code moved from + _initialize_event_loop(). + (_initialize_event_loop): Call gdb_setup_readline(). + +2002-10-02 Andrew Cagney + + * infrun.c (resume): Convert #ifdef CANNOT_STEP_BREAKPOINT into C. + * gdbarch.sh (CANNOT_STEP_BREAKPOINT): Add. + * gdbarch.h, gdbarch.c: Re-generate. + +2002-10-02 Daniel Jacobowitz + + Fix PR gdb/778 + * gdbtypes.c (fill_in_vptr_fieldno): Call check_typedef + before recursing. + * gnu-v3-abi.c (gnuv3_virtual_fn_field): Check return value + of fill_in_vptr_fieldno. + +2002-10-02 Elena Zannoni + + * inferior.h (registers_info, stepi_command, nexti_command, + continue_command, interrupt_target_command): Export from infcmd.c. + * frame.h (args_info, selected_frame_level_changed_hook, + return_command): Export from stack.c. + * v850ice.c (stepi_command, nexti_command, continue_command): use + prototypes from inferior.h. + * tracepoint.c (registers_info, args_info, locals_info): Use + prototypes from frame.h and inferior.h. + * Makefile.in (mi-main.o): Add dependency on frame.h. + +2002-10-02 Andrew Cagney + + * rs6000-tdep.c (rs6000_store_struct_return): Store struct_return + value in register 3 adjusted by ppc_gp0_regnum. + + * rs6000-tdep.c (skip_prologue): Bias alloca_reg by ppc_gp0_regnum. + +2002-10-02 Marko Mlinar + + * MAINTAINERS: Add myself to the Write After Approval list. + +2002-10-01 Alexandre Oliva + + * mips-tdep.c (mips_find_abi_section): .mdebug.abi64 is the name + of the section for the N64 ABI, fixed. + + * config/mips/tm-irix6.h: Include solib.h. + +2002-10-01 Elena Zannoni + + * dwarf2read.c (dwarf_stack_op_name): Recognize more dwarf3 and + GNU operators. + +2002-10-01 Andrew Cagney + + * NEWS: Mention that MI syntax, selected by "mi" changed to "mi2" + and that "mi0" syntax has been removed. + +2002-09-30 David Carlton + + * Makefile.in (ppc-sysv-tdep.o): Depend on gdb_string_h. + * ppc-sysv-tdep.c: #include "gdb_string.h". + * remote-sds.c (getmessage): Add semicolon after 'retry' label to + pacify GCC. + +2002-10-01 Andrew Cagney + + * rs6000-tdep.c (rs6000_gdbarch_init): For powerpc:7400, fix + "vrsave"'s register number. + +2002-09-30 Andrew Cagney + + * mips-tdep.c (mips_frame_saved_pc): When a generic dummy frame, + use frame_unwind_signed_register to obtain the PC. + (mips_frame_chain): Handle a generic dummy frame. + (mips_init_extra_frame_info): When a generic dummy frame, don't + re-compute the frame base. + (mips_pop_frame): Handle generic dummy frames. + (mips_gdbarch_init): When generic dummy frames, set + use_generic_dummy_frames, push_dummy_frame to + generic_push_dummy_frame, pc_in_call_dummy to + generic_pc_in_call_dummy, and save_dummy_frame_top_of_stack to + generic_save_dummy_frame_tos. + +2002-09-30 Andrew Cagney + + * blockframe.c (generic_find_dummy_frame): Rewrite. Only test + against TOP when TOP was explictly set. + (generic_push_dummy_frame): Set TOP to zero. + +2002-09-30 Elena Zannoni + + * event-loop.c (start_event_loop): Rename variable 'result' to + 'gdb_result', to avoid conflicts with upcoming intepreters changes. + +2002-09-30 Keith Seitz + + * gdb-events.sh (selected_thread_changed): New event. + * gdb-events.c: Regenerated. + * gdb-events.h: Regenerated. + +2002-09-30 Hans-Peter Nilsson + + * MAINTAINERS: Add self to Write After Approval list. + +2002-09-30 Fernando Nasser + + * disasm.c: New file. + * disasm.h: New file. + * mi/mi-cmd-disas.c (gdb_dis_asm_read_memory): Moved to disasm.c. + (compare_lines): Ditto. + (dump_insns): Ditto. + (do_mixed_source_and_assembly): Moved to disasm.c. Added uiout + argument. + (do_assembly_only): Ditto. + (do_disassembly): Renamed to gdb_disassembly and moved to + disasm.c. Sdded uiout argument. + * Makefile.in: Add new files. Reorder SFILES list. Update + dependencies. Include libgdb.a later in the insight executable. + +2002-09-29 Andrew Cagney + + * config/djgpp/fnchange.lst: Rename bfd/elf64-alpha.c and + bfd/elf64-alpha-fbsd.c. + +2002-09-29 Andrew Cagney + + * config/djgpp/fnchange.lst: Rename i386gnu-nat.c and + i386gnu-tdep.c. + +2002-09-29 Andrew Cagney + + * gnu-nat.h (debug): Use __FILE__ and __LINE__ instead of + __FUNCTION__. + * gnu-nat.c (do_mach_notify_no_senders): Replace __FUNCTION__ with + function name. + (do_mach_notify_port_deleted, do_mach_notify_msg_accepted): Ditto. + (do_mach_notify_port_destroyed, do_mach_notify_send_once): Ditto. + (S_proc_setmsgport_reply, S_proc_getmsgport_reply): Ditto. + (S_msg_sig_post_reply): Ditto. + +2002-09-28 Corinna Vinschen + + * sh-tdep.c (sh_use_struct_convention): Use definition according + to ABI. + (sh_push_arguments): Store in register with correct endianess. + (sh_default_store_return_value): Ditto. + (sh_gdbarch_init): Set sizeof long double to 8. + +2002-09-27 Mark Kettenis + + * defs.h: Move inclusion of "ansidecl.h" before "gdb_locale.h". + Fix some whitespace problems. + +2002-09-27 David Carlton + + * Makefile.in (cris-tdep.o): Depend on gdb_string_h. + (mcore-tdep.o): Ditto. + (ns32k-tdep.o): Ditto. + (ns32knbsd-tdep.o): Ditto. + (sh3-rom.o): Ditto. + (vax-tdep.o): Ditto. + * cris-tdep.c: #include "gdb_string.h" + * mcore-tdep.c: Ditto. + * ns32k-tdep.c: Ditto. + * ns32knbsd-tdep.c: Ditto. + * sh3-rom.c: Ditto. + * vax-tdep.c: Ditto. + +2002-09-27 David Carlton + + * config/djgpp/fnchange.lst: Add entries for + gdb/testsuite/gdb.c++/m-static files. + +2002-09-27 Jim Wilson + + * MAINTAINERS: Add myself to the Write After Approval list. + +2002-09-26 Martin M. Hunt + + * mips-tdep.c (find_proc_desc): Initialize startaddr. + + +2002-09-26 Andrew Cagney + + * rs6000-tdep.c (rs6000_frame_chain): Don't chain past the dummy + frame. + +2002-09-26 Andrew Cagney + + * rs6000-tdep.c (rs6000_extract_struct_value_address): Return 0. + (rs6000_struct_return_address): Delete variable. + (rs6000_store_struct_return): Update. + (rs6000_gdbarch_init): Set extract_struct_value_address instead of + deprecated_extract_struct_value_address. + (rs6000_frame_align): New function. + (rs6000_gdbarch_init): Set frame_align. + +2002-09-26 Andrew Cagney + + From Grace Sainsbury : + * Makefile.in (gdbtk-main.o): New target. + (gdb.o): New target. + (main_h): Define. + (main.o): Update dependencies. + (gdb$(EXEEXT)): Add gdb.o. + (SUBDIR_GDBTK_SRCS): Add gdbtk-main.c. + (SUBDIR_GDBTK_ALL, SUBDIR_GDBTK_UNINSTALL): Set. + (SUBDIR_GDBTK_CLEAN): Set. + (install-gdbtk): Install the insight binary. + (uninstall-gdbtk): New target. + (all-gdbtk, clean-gdbtk): New rule. + * top.c (use_windows): Default to zero. + * main.c: Include "main.h". + (main): Delete. + (struct captured_main_args): Delete. + (gdb_main): New function. + * main.h: New file. + * gdb.c: New File. + +2002-09-25 Andrew Cagney + + * frame.c: Include "gdb_string.h" and "builtin-regs.h". + (frame_map_regnum_to_name): New function. + (frame_map_name_to_regnum): New function. + * frame.h (frame_map_name_to_regnum): Declare. + (frame_map_regnum_to_name): Declare. + * builtin-regs.c (builtin_reg_map_regnum_to_name): New function. + * builtin-regs.h (builtin_reg_map_regnum_to_name): Declare. + * parse.c: Do not include "builtin-regs.h". + (target_map_name_to_register): Delete function. + (write_dollar_variable): Use frame_map_name_to_regnum. + * parser-defs.h (target_map_name_to_register): Delete declaration. + * expprint.c: Include "frame.h". + (print_subexp): Use frame_map_regnum_to_name. + * eval.c (evaluate_subexp_standard): Use frame_map_regnum_to_name. + * infcmd.c (registers_info): Use frame_map_name_to_regnum. + +2002-09-25 Andrew Cagney + + * rs6000-tdep.c (rs6000_frame_saved_pc): If the link register + wasn't saved, and the next innermost frame is a dummy, return the + dummy frame's link register. + +2002-09-24 Jim Blandy + + Fix from Paul Breed: + * main.c (captured_main): Add a `break' after the case for 'b'. + +2002-09-24 Keith Seitz + + * varobj.c (c_type_of_child): Use get_target_type instead + of TYPE_TARGET_TYPE. + +2002-09-22 Fernando Nasser + + * source.c (get_current_or_default_source_symtab_and_line): Remove + function. + (set_default_source_symtab_and_line): New function. Attempts to + determine a source file to list lines from if one is not currently + defined. + (get_current_source_symtab_and_line): Initialize sal.pc and + sal.end fields. + (set_current_source_symtab_and_line): Mark argument as const. + * source.h: Update declarations and comments. + * linespec.c (decode_line_1): Replace call to removed routine above. + * stack.c (print_frame_info_base): Ditto. + * cli/cli-cmds.c (edit_command): Ditto. + (list_command): Ditto. + +2002-09-22 Fernando Nasser + + * source.c (get_current_or_default_source_symtab_and_line): Initialize + sal.pc and sal.end fields. + (get_current_or_default_source_symtab_and_line): Ditto. + * breakpoint.c (parse_breakpoint_sals): Use correct accessor function + so we do not cause a new source symtab to be searched for (reverting an + unintentional change from the 2002-09-20 patch). + * scm-lang.c (scm_unpac): Ditto. + +2002-09-21 Andrew Cagney + + * complaints.c (symfile_explanations): Remove new-line from + ``isolated_message''. + (vcomplaint): When ISOLATED_MESSAGE, force a line break. + (clear_complaints): When a SUBSEQUENT_MESSAGE, force a line break. + +2002-09-20 Nick Clifton + + * NEWS: Announce that V850EA ISA is no longer supported. + * v850-tdep.c: Remove reference to bfd_mach_v850ea. + +2002-09-20 David Carlton + + * Makefile.in (c-lang.o): Correct dependencies. + (utils.o): Gather dependencies. + (charset.o): Move. + * c-lang.c: #include "gdb_string.h" + +2002-09-20 Fernando Nasser + + From 2002-07-02 George Helffrich + * cli/cli-cmds.c (list_command): New function. Implements the new + cli edit command. + (_init_cli_cmds): Add new command definition. + * gdb.1: Document edit command. + * doc/gdb.texinfo: Document edit command. + +2002-09-20 Fernando Nasser + + * source.c: Make global variables current_source_symtab and + current_source_line static. + (list_command): Moved to cli/cli-cmds.c. + (ambiguous_line_spec): Moved to cli/cli-cmds.c. + (get_first_line_listed): New accessor function. + (get_lines_to_list): New accessor function. + (get_current_source_symtab_and_line): New function. Retrieves the + position in the source code that we consider current. + (get_current_or_default_source_symtab_and_line): New function. + Like the above but attempts to determine a default position if one + is not currently defined. + (set_current_source_symtab_and_line): New function. Sets the source + code position considered current and returns the previously set one. + (clear_current_source_symtab_and_line): Reset stored information about + a current source line. + (_initialize_source): Remove registration for the "list" command and + its alias. + * source.h: Add declarations for the new functions above. + * symtab.h: Remove declarations for the global variables mentioned + above. + * breakpoint.c (parse_breakpoint_sals): Use accessor functions to + obtain current source line. + * linespec.c (decode_line_1): Ditto. + * macroscope.c (default_macro_scope): Ditto. + * scm-lang.c (scm_unpac): Ditto. + * stack.c (print_frame_info_base): Ditto. + * symfile.c (clear_symtab_users): Ditto. + * symtab.c (decode_line_spec): Ditto. + * cli/cli-cmds.c (list_command): Moved here from source.c. + (ambiguous_line_spec): Moved here from source.c. + (_init_cli_cmds): Add definition for "list" and its alias. + * Makefile.in: Update dependencies. + +2002-09-20 Corinna Vinschen + + * h8300-tdep.c (h8300_examine_prologue): Match saved regs location + with what gcc thinks is correct. + +2002-09-20 Corinna Vinschen + + * h8300-tdep.c (h8300_examine_prologue): Fix loop for saved regs in + multiple register push instruction. + +2002-09-19 Jim Blandy + + Add support for distinct host and target character sets. + * charset.c, charset.h: New files. + * c-exp.y: #include "charset.h". + (yylex): Convert character and string literals to the target + character set, before returning them as the semantic value of the + token. + * c-lang.c: #include "charset.h". + (c_emit_char): Use charset-specific methods to recognize + characters with backslash escape forms, to decide which characters + to print literally and which to print using numeric escape + sequences, and to convert target characters to host characters + before printing. + * utils.c: #include "charset.h". + (no_control_char_error): New function. + (parse_escape): Use charset-specific methods to recognize + backslash escapes, parse `control character' notation, and convert + characters from the host character set to the target character set. + * configure.in: Set the default host character set. + Check where to find iconv, and what its argument types might be. + * acinclude.m4 (AM_ICONV): New macro, borrowed from GCC. + * Makefile.in (SFILES): List charset.c. + (COMMON_OBS): List charset.o. + (charset.o): New rule. + (charset_h): New header dependency variable. + (c-lang.o, utils.o, c-exp.tab.o): Note dependency on $(charset_h). + (LIBICONV): New variable, set by configure. + (CLIBS): Include $(LIBICONV) here. + * aclocal.m4, config.in, configure: Regenerated. + +2002-09-19 Joel Brobecker + + * ada-exp.y: Add missing semicolons to end rules. Fixes a + bison 1.35 warning. + +2002-09-19 Richard Earnshaw + + * gdb_mbuild.sh: New file. + +2002-09-19 Andrew Cagney + + * objc-exp.y, objc-lang.h, objc-lang.c: Fix copyright notice. + +2002-09-18 Andrew Cagney + + * breakpoint.c, c-exp.y, defs.h, elfread.c, expression.h, + jv-exp.y, language.c, language.h, p-exp.y, parse.c, parser-defs.h, + printcmd.c, source.c, stabsread.c, symfile.c, symtab.h, utils.c, + valops.c, value.h: Revert previous change. + +2002-09-18 Michael Snyder + + Preliminary support for Objective-C: + * defs.h (language_objc): New enum value. + (puts_filtered_tabular): Declaration only, exported from utils.c. + (skip_quoted): Delete, declared in completer.h. + * c-exp.y: Include completer.h. + * p-exp.y: Ditto. + * jv-exp.y: Ditto. + * expression.h (OP_MSGCALL, OP_SELECTOR, OP_SELF, OP_NSSTRING): + New operator enum values. + * language.h (CAST_IS_CONVERSION): Test for language_objc. + * language.c (binop_result_type): Handle language_objc case. + (integral_type, character_type, string_type, boolean_type, + structured_type, binop_type_check): Ditto. + * symtab.h (SYMBOL_OBJC_DEMANGLED_NAME): Define. + (struct objc_specific): Add to general_symbol_info. + (SYMBOL_INIT_LANGUAGE_SPECIFIC): Add objc initialization. + (SYMBOL_DEMANGLED_NAME): Handle objc case. + * parser-defs.h (struct objc_class_str): New struct type. + (start_msglist, end_msglist, add_msglist): Declaration only, + exported from objc-lang.c. + * value.h (value_of_local, value_nsstring, + call_function_by_hand_expecting_type): Exported from valops.c. + * valops.c (find_function_addr): Export. + (call_function_by_hand_expecting_type): New function. + (value_of_local): New function. + * symfile.c (init_filename_language_table): Add ".m" extension + for Objective-C. + * utils.c (puts_filtered_tabular): New function. + (fprintf_symbol_filtered): Add objc demangling support (disabled). + (set/show demangle): Extend help-string to refer to ObjC. + * elfread.c (elf_symtab_read): Skip Objective-C special symbols. + * stabsread.c (symbol_reference_defined): Objective-C symbols + may contain colons: make allowances when scanning stabs strings + for colons. + (objc_find_colon): New function. + * printcmd.c (address_info): If language == objc then print + "self" instead of "this". + * parse.c (length_of_subexp): Handle new operators OP_MSGCALL, + OP_NSSTRING, and OP_SELF. + (prefixify_subexp): Ditto. + * source.c (print_source_lines): Mention objc in comment. + * breakpoint.c (parse_breakpoint_sals): Recognize Objective-C + method names. + +2002-09-18 Andrew Cagney + + * complaints.h: Update copyright. + (struct complaints): Declare. + (struct complaint): Make `message' constant. + (internal_complaint): Declare. + (complaint): Declare. + (complaint_root): Delete declaration. + (symfile_complaints): Delete declaration. + (struct complaints): Add opaque declaration. + (clear_complaints): Add a complaints parameter. + * complaints.c: Update copyright. + (enum complaint_series): Define. + (complaint_root): Delete. + (struct complaints): Define. + (complaint_sentinel, symfile_complaint_book): New variables. + (symfile_explanations, symfile_complaints): New variables. + New variables. + (get_complaints): New function. + (vcomplaint): New function. + (complaint): New function. + (internal_complaint): New function. + (complain): Call vcomplain with symfile_complaint. + (clear_complaints): Rewrite. + (_initialize_complaints): Use add_setshow_command. + * Makefile.in (complaints.o): Update dependencies. + * symfile.c (syms_from_objfile): Add symfile_complaints parameter + to call to clear_complaints. + (new_symfile_objfile, reread_symbols): Ditto. + (oldsyms_complaint): Delete. + (empty_symtab_complaint, unknown_option_complaint): Delete. + (free_named_symtabs): Use complaint instead of complain. + +2002-09-18 Michael Snyder + + Contributed by Apple Computer, Inc. Merged with current sources + by Adam Fedor [cagney]. + + * objc-lang.c: First clean-up round: comments, indentation. + * objc-lang.h: Ditto. + * objc-lang.y: Ditto. + +2002-09-18 Andrew Cagney + + * maint.c (maintenance_internal_error): Print the parameter as the + error message. + (maintenance_internal_warning): New function. + (_initialize_maint_cmds): Add command `maint internal-warning'. + + * defs.h (internal_warning, internal_vwarning): Declare. + * utils.c (struct internal_problem): Define. + (internal_vproblem): New function. + (internal_warning): New function. + (internal_vwarning): New function. + (internal_warning_problem, internal_error_problem): New variables. + (internal_verror): Just call internal_vproblem. + +2002-09-18 Michael Snyder + + * objc-lang.c: New file, support for Objective-C. + Preliminary check-in, not yet integrated into gdb. + * objc-lang.h: New file. + * objc-exp.y: New file. + +2002-09-18 Andrew Cagney + + * infrun.c (signal_stop_update): Convert definition to ISO C. + (signal_print_update): Ditto. + (signal_pass_update): Ditto. + * inflow.c (terminal_save_ours): Ditto. + + * h8300-tdep.c (h8300_gdbarch_init): Use C instead of C++ + comments. + + * config/djgpp/fnchange.lst: Handle name clashes between + bfd/coff-tic30.c, bfd/coff-tic4x.c, bfd/coff-tic54x.c and + bfd/coff-tic80.c. + + * i386-linux-tdep.h: Fix tipo. + +2002-09-18 Adam Fedor + + * MAINTAINERS: Add myself to the Write After Approval list. + +2002-09-18 Jim Blandy + + * dbxread.c, mdebugread.c: Revert my change of 2001-10-23. Moving + texthigh and textlow to reader-specific structs caused + objfile_relocate to miss them. This is fixable, but the work that + the change was supposed to prepare GDB for never got done anyway. + +2002-09-18 David Carlton + + * MAINTAINERS: Alphabetize Write After Approval list. + +2002-09-18 Daniel Jacobowitz + + Fix PR gdb/709 + * values.c (value_static_field): Call read_var_value. + +2002-09-18 Andrew Cagney + + * valops.c (hand_function_call): Align the initial stack pointer + and STRUCT_ADDR using frame_align. When STRUCT_RETURN and + FRAME_ALIGN_P, use STRUCT_ADDR to obtain the called function's + return value. + * mips-tdep.c (mips_frame_align): New function. + (mips_gdbarch_init): Set frame_align. + * gdbarch.sh (FRAME_ALIGN): New method. + * gdbarch.h, gdbarch.c: Re-generate. + +2002-09-18 Michal Ludvig + + * x86-64-linux-nat.c (x86_64_regmap): Added CS and SS + registers. + +2002-09-17 Andrew Cagney + + * NEWS: Mention that MIPS $fp behavior changed. + * mipsnbsd-tdep.c (mipsnbsd_cannot_fetch_register): Delete + reference to FP_REGNUM. + (mipsnbsd_cannot_store_register): Ditto. + * mips-linux-nat.c: Update copyright. + (mips_linux_cannot_fetch_register): Delete reference to FP_REGNUM. + (mips_linux_cannot_store_register): Ditto. + * mips-linux-tdep.c (supply_gregset): Ditto. Update copyright. + * config/mips/tm-mips.h: Update copyright. + (FP_REGNUM): Delete macro. + (MIPS_REGISTER_NAMES): Replace "fp" with "". + * config/mips/tm-irix6.h (FP_REGNUM): Delete macro. + * mips-tdep.c (mips_gdbarch_init): Set read_fp to mips_read_sp. + (mips_r3041_reg_names, mips_r3051_reg_names) + (mips_r3081_reg_names): Replace "fp" with "". + Fix PR gdb/480. + +2002-09-17 Theodore A. Roth + + * gdb/avr-tdep.c(avr_scan_prologue): Fix bad call to + generic_read_register_dummy() (PR gdb/703). + (avr_push_return_address): #if 0 out unused vars. + (avr_gdbarch_init): Enable use of avr_push_return_address(). + +2002-09-17 Michael Snyder + + * m32r-stub.c (restore_and_return): Postpone restoring of PSW. + RTE will take care of it. + +2002-09-17 Andrew Cagney + + * arch-utils.c (legacy_virtual_frame_pointer): If FP_REGNUM is + invalid, return SP_REGNUM. + +2002-09-17 Michael Snyder + + * mips-tdep.c (mips_pop_frame): Read saved values of floating + point registers without sign extension. + +2002-09-17 Andrew Cagney + + * blockframe.c (deprecated_read_register_dummy): Rename + generic_read_register_dummy. + * frame.c (frame_unwind_signed_register): New function. + (frame_unwind_unsigned_register): New function. + * frame.h (frame_unwind_signed_register): Declare. + (frame_unwind_unsigned_register): Declare. + (deprecated_read_register_dummy): Rename + generic_read_register_dummy. + + * h8300-tdep.c (h8300_frame_chain): Update. + (h8300_frame_saved_pc): Update. + * xstormy16-tdep.c (xstormy16_frame_saved_pc): Update. + * rs6000-tdep.c (rs6000_frame_saved_pc): Update. + * s390-tdep.c (s390_frame_saved_pc_nofix): Update. + (s390_frame_chain): Update. + * v850-tdep.c (v850_find_callers_reg): Update. + (v850_frame_saved_pc): Update. + * m32r-tdep.c (m32r_init_extra_frame_info): Update. + (m32r_find_callers_reg): Update. + (m32r_frame_saved_pc): Update. + * sh-tdep.c (sh_find_callers_reg): Update. + (sh64_get_saved_pr): Update. + (sh_init_extra_frame_info): Update. + (sh_init_extra_frame_info): Update. + (sh64_init_extra_frame_info): Update. + (sh64_init_extra_frame_info): Update. + * mcore-tdep.c (mcore_find_callers_reg): Update. + (mcore_frame_saved_pc): Update. + (mcore_init_extra_frame_info): Update. + * i386-tdep.c (i386_frame_saved_pc): Update. + * ia64-tdep.c (ia64_frame_saved_pc): Update. + (ia64_init_extra_frame_info): Update. + (ia64_init_extra_frame_info): Update. + * d10v-tdep.c (d10v_frame_saved_pc): Update. + * cris-tdep.c (cris_init_extra_frame_info): Update. + * avr-tdep.c (avr_frame_chain): Update. + (avr_init_extra_frame_info): Update. + (avr_frame_saved_pc): Update. + * arm-tdep.c (arm_find_callers_reg): Update. + (arm_init_extra_frame_info): Update. + (arm_frame_saved_pc): Update. + +2002-09-17 Tom Tromey + + * c-lang.c (c_emit_char): Don't treat \0 specially unless quoter + is "'". + +2002-09-17 Corinna Vinschen + + * MAINTAINERS: Remove "non multi-arched" text from h8300. + * h8300-tdep.c (h8300_next_prologue_insn) Renamed from + NEXT_PROLOGUE_INSN. + (h8300_examine_prologue): Call h8300_next_prologue_insn instead of + NEXT_PROLOGUE_INSN. + +2002-09-16 Joel Brobecker + + * osfsolib.c: Remove file, replaced by solib-osf.c. + * Makefile.in: Remove compilation rules for osfsolib.c. + +2002-09-16 David Carlton + + * cp-valprint.c (cp_print_class_method): Correct args to + check_stub_method_group. + +2002-09-16 Corinna Vinschen + + * h8300-tdep.c: Multiarch. Drop `set machine' command in favor of + `set architecture'. Unify naming convention of functions. + (h8300_skip_prologue): Improve prologue analysis. + (h8300_push_arguments): Rewritten to more closely match GCC's + bizarre argument-passing behavior, along with the comment describing + said behavior. + * remote-hms.c (hms_regnames): Don't use NUM_REGS in definition. + * config/h8300/tm-h8300.h: Multiarch. Just keep stuff needed by + sim, remote-e7000.c, remote-hms.c and remote.c + +2002-09-15 Mark Kettenis + + * i386-tdep.c (gdb_print_insn_i386): Removed. + (i386_print_insn): New function. + (i386_gdbarch_init): Set print_insn to i386_print_insns. + (_initialize_i386_tdep): Don't initialize tm_print_insn and + tm_print_insn_info. + +2002-09-14 Mark Kettenis + + * gdbtypes.c (check_stub_method_group): Initialize found_stub to + zero. + +2002-09-14 Corinna Vinschen + + * arch-utils.c (legacy_pc_in_sigtramp): Move preprocessor expression + for IN_SIGTRAMP to here. Use IN_SIGTRAMP only if it's defined. + Guard usage of SIGTRAMP_START() by using SIGTRAMP_START_P. + +2002-09-13 Christopher Faylor + + * win32-nat.c (child_create_inferior): Honor 'tty' command. + +2002-09-13 Daniel Jacobowitz + + * gdbtypes.c (check_stub_method): Make static. + (check_stub_method_group): New function. + * gdbtypes.h: Update prototypes. + * cp-support.c: New file. + * cp-support.h: New file. + + * stabsread.c: Include "cp-abi.h" and "cp-support.h". + (update_method_name_from_physname): New function. + (read_member_functions): Correct method names for operators + and v3 constructors/destructors. Separate v2 constructors and + destructors. + * Makefile.in (stabsread.o): Update dependencies. + (SFILES): Add cp-support.c. + (COMMON_OBS): Add cp-support.o. + (cp_support_h, cp-support.o): Add. + + * cp-valprint.c (cp_print_class_method): Call + check_stub_method_group instead of check_stub_method. Remove + extraneous QUITs. + * p-valprint.c (pascal_object_print_class_method): Likewise. + * valops.c (search_struct_method): Likewise. + (find_method_list, value_struct_elt_for_reference): Likewise. + +2002-09-13 Andrew Cagney + + * gdbarch.sh (SIGTRAMP_END): Change to a predicate function. + * gdbarch.h, gdbarch.c: Regenerate. + +2002-09-13 Andrew Cagney + + * frame.c (find_saved_register): Delete function. + * frame.h (find_saved_register): Delete declaration. + Fix PR gdb/631. + +Fri Sep 13 14:59:55 2002 Andrew Cagney + + * mips-tdep.c (read_next_frame_reg): Re-hack using + frame_register_unwind. + +Fri Sep 13 07:42:09 2002 Andrew Cagney + + * mips-tdep.c (mips_get_saved_register): Re-hack using + frame_register_unwind. + +2002-09-12 Joel Brobecker + + * gdbarch.sh (NAME_OF_MALLOC): New variable in the architecture + vector. Will be useful for Interix. + * gdbarch.h, gdbarch.c: Regenerate. + + * valops.c (value_allocate_space_in_inferior): Replace hard-coded + name of the malloc function by NAME_OF_MALLOC. + +2002-09-12 Joel Brobecker + + * value.h (find_function_in_inferior): Add const keyword to + one of the parameters. Allows us to invoke this function with + a const char *. + * valops.c (find_function_in_inferior): Likewise. + +2002-09-12 Joel Brobecker + + * exec.c (xfer_memory): Fix compilation warning with old versions + of GCC. + * tracepoint.c (trace_find_tracepoint_command): Likewise. + +2002-09-12 David Carlton + + * symtab.h: Run through gdb_indent.h. + Add 2002 to Copyright year list. + +2002-09-12 Alan Modra + + * x86-64-tdep.c (_initialize_x86_64_tdep): Don't use hard-coded + mach constants. + * MAINTAINERS: Add myself to write after approval list. + +2002-09-11 J. Brobecker + + * osabi.c (gdb_osabi_name): Add entry for GDB_OSABI_INTERIX. + +2002-09-11 J. Brobecker + + * osabi.h (gdb_osabi): Add new GDB_OSABI_INTERIX enum value for + Interix. + +2002-06-05 Paul N. Hilfinger + + * procfs.c (do_detach): Clear current signal, not just fault. + Corrects problem with breakpoint trap signal leaking to detached + process on Tru64. + +2002-09-10 Michael Snyder + + * buildsym.c (finish_block): Protect against null pointer. + +2002-09-10 Andrew Cagney + + * infcmd.c (default_print_registers_info): Send all output to + ``file'' instead of ``gdb_stdout''. + +2002-09-10 Michael Snyder + + * mips-tdep.c (mips_extract_struct_value_address): Make val a + LONGEST, and use signed register read (addresses are sign- + extended for mips). + +2002-09-10 Stephane Carrez + + * event-loop.c (gdb_do_one_event): Make public. + * event-loop.h (gdb_do_one_event): Declare. + +2002-09-10 Jeff Law + + * infttrace.c (child_resume): Simplify and rework to avoid + TT_PROC_CONTINUE. + +2002-09-09 Fred Fish + + * printcmd.c (print_scalar_formatted): "len" is the number of + target bytes, NOT the number of target bits. + +2002-09-09 Elena Zannoni + + From: Emmanuel Thome' + * top.c (init_main): Set rl_terminal_name. + +2002-09-08 Aidan Skinner + + * ada-lang.c (ada_array_bound, ada_type_match, + _initialize_ada_language): Fix K&R definitions. + * ada-tasks.c (get_current_task): Fix K&R definitions. + * ada-valprint.c (adjust_type_signedness): Fix K&R definitions. + +2002-09-07 Christopher Faylor + + * MAINTAINERS: Remove CE from list of maintainership responsibilities. + Add XP. + +2002-09-06 Mark Kettenis + + * i386-tdep.c (i386_register_virtual_type, + i386_register_convertible, i386_register_convert_to_virtual, + i386_register_comvert_to_raw): Use FP_REGNUM_P and SSE_REGNUM_P + instead of IS_FP_REGNUM and IS_SSE_REGNUM. + (i386_gdbarch_init): Fix comment. Add comments on calls that set + sp_regnum, fp_regnum, pc_regnum, ps_regnum and fp0_regnum. + Don't set push_arguments twice. + + * i386bsd-tdep.c (i386bsd_init_abi): Set sigtramp_start and + sigtramp_end to i386bsd_sigtramp_start and i386bsd_sigtramp_end. + * i386nbsd-tdep.c (i386nbsd_init_abi): Set sigtramp_start and + sigtramp_end to NULL. + * config/i386/tm-fbsd.h (SIGTRAMP_START, SIGTRAMP_END): Remove + defines. + (i386bsd_sigtramp_start, i386_sigtramp_end): Remove prototypes. + + * i386nbsd-tdep.c (i386nbsd_pc_in_sigtramp): Remove spurious + whitespace. + + * gdbarch.sh (SIGTRAMP_START, SIGTRAMP_END): New methods. + * gdbarch.h, gdbarch.c: Re-generate. + * blockframe.c (find_pc_sect_partial_function): Convert to use + SIGTRAMP_START_P predicate. + +2002-09-05 Michael Snyder + + * arm-tdep.c (arm_init_extra_frame_info): Distinguish between + generic_dummy_frame method and old method. Also distinguish + between ARM_FP_REGNUM and THUMB_FP_REGNUM. + (arm_extract_return_value): Use new regcache method. + + * mips-tdep.c (mips_n32n64_push_arguments): Remove alignment + adjustment that doesn't conform to the ABI. + (mips_extract_struct_value_address): Retrieve V0_REGNUM from + saved regcache, not from current regcache. + +2002-09-05 Andrew Cagney + + * NEWS: Update for 5.3. Add new section ``Changes since 5.3''. + * README: Update. + +2002-09-04 Jason Thorpe + + * arm-tdep.c (arm_addr_bits_remove): Don't check for Thumb mode + if arm_apcs_32 is false. + +2002-09-04 Andrew Cagney + + GDB 5.3 branch created. + +2002-09-03 Theodore A. Roth + + * gdb/avr-tdep.c (avr_gdbarch_init): Use + generic_unwind_get_saved_register. + +2002-09-03 David Carlton + + * dwarf2read.c (dwarf2_add_member_fn): Add the 'type' + argument (PR gdb/653). Update call to smash_to_method_type. + (read_structure_scope): Update call to dwarf2_add_member_fn. + +2002-09-03 Michal Ludvig + + * x86-64-linux-tdep.c: Include gdb_string.h + * x86-64-linux-nat.c: Ditto. + +2002-09-02 Jason Thorpe + + * ada-exp.y (yyname, yyrule): Remap global variables that appear + when YYDEBUG is set to 1. + * c-exp.y: Likewise. + * f-exp.y: Likewise. + * jv-exp.y: Likewise. + * m2-exp.y: Likewise. + * p-exp.y: Likewise. + +2002-09-02 Jason Thorpe + + * Makefile.in (i386nbsd-tdep.o): Add $(solib_svr4_h) to + dependency list. + * i386nbsd-tdep.c (i386nbsdelf_init_abi): Set + solib_svr4_fetch_link_map_offsets to + nbsd_ilp32_solib_svr4_fetch_link_map_offsets. + * config/i386/nbsd.mt (TDEPFILES): Add solib.o and solib-svr4.o. + * config/i386/nbsdaout.mh (NATDEPFILES): Remove solib.o. + * config/i386/nbsdelf.mh (NATDEPFILES): Remove solib.o, + solib-svr4.o, and solib-legacy.o. + * config/i386/tm-nbsd.h: Include solib.h. + +2002-09-02 Jason Thorpe + + * configure.tgt (i[3456]86-*-netbsdelf*): Merge with... + (i[3456]86-*-netbsd*): ...this. Set gdb_target to nbsd. + (i[3456]86-*-openbsd*): Make this a separate entry. Add a + comment noting that this needs its own target configuration. + * config/i386/nbsd.mt: New file. + * config/i386/nbsdaout.mt: Remove. + * config/i386/nbsdelf.mt: Ditto. + * config/i386/tm-nbsdaout.h: Ditto. + +2002-09-02 Jason Thorpe + + * i386nbsd-tdep.c (i386nbsd_sigtramp_offset): New function. + (i386nbsd_pc_in_sigtramp): Rewrite to use i386nbsd_sigtramp_offset. + (i386nbsd_init_abi): Don't initialize tdep->sigtramp_start or + tdep->sigtramp_end. + (i386nbsd_sigtramp_start, i386nbsd_sigtramp_end): Remove. + * config/i386/tm-nbsd.h (SIGTRAMP_START, SIGTRAMP_END) + (i386bsd_sigtramp_start, i386bsd_sigtramp_end): Remove. + +2002-09-02 Jason Thorpe + + * Makefile.in (i386nbsd-tdep.o): Add $(arch_utils_h), + $(i386_tdep_h), and $(nbsd_tdep_h) to dependency list. + * i386-tdep.h (i386bsd_init_abi): New prototype. + * i386bsd-tdep.c (i386bsd_init_abi): Remove "static" from + function declaration. + (_initialize_i386bsd_tdep): Don't register OS ABI handlers + for NetBSD-a.out or NetBSD-ELF. + (i386nbsd_sigtramp_start, i386nbsd_sigtramp_end) + (i386nbsd_sc_pc_offset, i386nbsd_sc_sp_offset) + (i386nbsd_init_abi, i386nbsdelf_init_abi): Move to... + * i386nbsd-tdep.c: ...here. Include arch-utils.h, i386-tdep.h, + and nbsd-tdep.h. + (i386nbsd_pc_in_sigtramp): New function. + (i386nbsd_init_abi): Set gdbarch_pc_in_sigtramp to + i386nbsd_pc_in_sigtramp. + (_initialize_i386nbsd_tdep): Register i386nbsd_init_abi + and i386nbsdelf_init_abi OS ABI handlers. + * config/i386/nbsdaout.mt (TDEPFILES): Add nbsd-tdep.o. + * config/i386/nbsdelf.mt (TDEPFILES): Likewise. + +2002-09-02 Mark Kettenis + + * i386-linux-nat.c (dummy_sse_values): Only try to fill in the SSE + registers if the target really has them. + +2002-08-31 Jason Thorpe + + * Makefile.in (mipsnbsd-tdep.o): Use $(nbsd_tdep_h) rather + than nbsd-tdep.h. + +2002-08-31 Jason Thorpe + + * Makefile.in (alphanbsd-tdep.o): Add $(frame_h) to dependency + list. + * alphanbsd-tdep.c (alphanbsd_sigcontext_addr) + (alphanbsd_skip_sigtramp_frame): New functions. + (alphanbsd_init_abi): Set tdep->skip_sigtramp_frame to + alphanbsd_skip_sigtramp_frame. Set tdep->sigcontext_addr + to alphanbsd_sigcontext_addr. + +2002-08-31 Jason Thorpe + + * Makefile.in (mipsnbsd-tdep.o): Add nbsd-tdep.h to dependency + list. + (nbsd-tdep.o): Add $(gdb_string_h) to dependency list. + * alphanbsd-tdep.c (alphanbsd_pc_in_sigtramp): Use + nbsd_pc_in_sigtramp. + * mipsnbsd-tdep.c: Include nbsd-tdep.h. + (mipsnbsd_pc_in_sigtramp): Use nbsd_pc_in_sigtramp. + * nbsd-tdep.c: Include gdb_string.h. + (nbsd_pc_in_sigtramp): New function. + * nbsd-tdep.h (nbsd_pc_in_sigtramp): New prototype. + * ppcnbsd-tdep.c (ppcnbsd_pc_in_sigtramp): New function. + (ppcnbsd_init_abi): Set gdbarch_pc_in_sigtramp to + ppcnbsd_pc_in_sigtramp. + * shnbsd-tdep.c (shnbsd_pc_in_sigtramp): New function. + (shnbsd_init_abi): Set gdbarch_pc_in_sigtramp to + shnbsd_pc_in_sigtramp. + * sparcnbsd-tdep.c (sparcnbsd_init_abi_elf): Set + gdbarch_pc_in_sigtramp to nbsd_pc_in_sigtramp. + * config/mips/nbsd.mt (TDEPFILES): Add nbsd-tdep.o. + +2002-08-30 Pierre Muller + + * breakpoint.c (breakpoint_init_inferior): Reset the val field of + watchpoints to NULL. + (insert_breakpoints): set val field of watchpoints if NULL. + + +2002-08-29 Jim Blandy + + * symtab.c (lookup_symbol_aux): In the cases where we find a + minimal symbol of an appropriate name and use its address to + select a symtab to read and search, use `name' (as passed to us) + as the demangled name when searching the symtab's global and + static blocks, not the minsym's name. + +2002-08-29 Keith Seitz + + * stack.c (print_frame_info_base): Always set current_source_symtab + and current_source_line. + +2002-08-29 Donn Terry + + * proc-api.c (rw_table): Fix typo in #ifdef PCSHOLD (missing S). + +2002-08-28 Keith Seitz + + * stack.c (select_frame): Add FIXME concerning selected-frame + events. + (select_frame_command): Send selected-frame-level-changed + event notification, but only if the level actually changed. + (up_silently_base): Add selected-frame-level-changed event + notification. + (down_silently_base): Likewise. + +2002-08-28 Andrew Cagney + + * Makefile.in: Update dependencies for all gdb/*.c files. + +2002-08-27 Tom Tromey + + * Makefile.in (osabi.o, i387-tdep.o, i386-linux-nat.o, lin-lwp.o, + ax-gdb.o, signals.o, jv-valprint.o, c-valprint.o, cp-abi.o): + Update dependencies. + * i387-tdep.c: Include gdb_string.h. + * osabi.c: Likewise. + * i386-linux-nat.c: Likewise. + * lin-lwp.c: Likewise. + * ax-gdb.c: Likewise. + * signals/signals.c: Likewise. + * jv-valprint.c: Likewise. + * p-lang.c: Likewise. + * c-valprint.c: Likewise. + * cp-abi.c: Likewise. + +2002-08-27 Elena Zannoni + + * cli/cli-script.h (copy_command_lines): Export. + * breakpoint.c: Include cli/cli-script.h. + * Makefile.in (breakpoint.o): Update dependencies. + +2002-08-26 Michael Snyder + + * breakpoint.c (insert_breakpoints): Protect all references + to 'process_warning'. Shorten long lines. + +2002-08-26 Joel Brobecker + + * cli/cli-script.c (copy_command_lines): New function. + * defs.h (copy_command_lines): Export. + * testsuite/gdb.base/commands.exp: New tests for commands + attached to a temporary breakpoint, and for commands that + delete the breakpoint they are attached to. + +2002-08-26 Michael Snyder + + * breakpoint.c (bpstat_stop_status): Instead of copying the + pointer to the breakpoint commands struct, make a new copy + of the struct and point to that. + (bpstat_clear): Free the commands struct. + (bpstat_clear_actions): Free the commands struct. + (bpstat_do_actions): Free the command actions. Also execute + the local cleanups, instead of deleting them. + (delete_breakpoint): Leave the commands field of the bpstat + chain alone -- it will be freed later. + +2002-08-26 Kevin Buettner + + * rs6000-tdep.c (altivec_register_p): Restore function inadvertently + deleted in 2002-08-20 commit. This function is still used by + ppc-linux-nat.c. + +2002-08-26 Keith Seitz + + * gdb-events.sh: Add selected-frame-level-changed event. + * gdb-events.c: Regenerated. + * gdb-events.h: Regenerated. + +2002-08-26 Stephane Carrez + + Fix PR gdb/393: + * inflow.c (terminal_save_ours): New function to save terminal + settings. + * inferior.h (terminal_save_ours): Declare. + * target.c (debug_to_terminal_save_ours): New function. + (cleanup_target): Defaults to_terminal_save_ours. + (update_current_target): Inherit to_terminal_save_ours. + (setup_target_debug): Set to_terminal_save_ours. + * target.h (target_terminal_save_ours): New to save terminal settings. + (target_ops): New member to_terminal_save_ours. + * gnu-nat.c (init_gnu_ops): Set to_terminal_save_ours. + * hpux-thread.c (init_hpux_thread_ops): Likewise. + * inftarg.c (init_child_ops): Likewise. + * m3-nat.c (init_m3_ops): Likewise. + * procfs.c (init_procfs_ops): Likewise. + * wince.c (init_child_ops): Likewise. + * win32-nat.c (init_child_ops): Likewise. + * sol-thread.c (init_sol_thread_ops): Likewise. + +2002-08-26 Mark Kettenis + + * i386-tdep.c (i386_store_return_value): Undeprecate. Convert to + use regcache_* functions. + (i386_gdbarch_init): Set store_return_value instead of + deprecated_store_return_value. + + * regcache.c (regcache_raw_write_signed, + regcache_raw_write_unsigned): New functions. + * regcache.h (regcache_raw_write_signed, + regcache_raw_write_unsigned): New prototypes. + +2002-08-25 Andrew Cagney + + * Makefile.in (c-exp.tab.o, jv-exp.tab.o, f-exp.tab.o) + (m2-exp.tab.o, p-exp.tab.o, ada-exp.tab.o): Move to before the + source file dependencies. Cleanup corresponding generator rules. + +2002-08-25 Andrew Cagney + + * regcache.h (register_offset_hack): Declare. + (regcache_cooked_read_using_offset_hack): Declare. + (regcache_cooked_write_using_offset_hack): Declare. + + * regcache.c (register_offset_hack): New function. + (regcache_cooked_read_using_offset_hack): New function. + (regcache_cooked_write_using_offset_hack): New function. + (regcache_dump): Check that the registers, according to their + offset, are packed hard against each other. + (cooked_xfer_using_offset_hack): New function. + +2002-08-25 Andrew Cagney + + * regcache.c (struct regcache_descr): Add field register_type. + (init_legacy_regcache_descr): Pass a pre-allocated regcache_descr + in as a parameter + (init_regcache_descr): Initialize register_type. Pass the descr + to init_legacy_regcache_descr. Use register_type instead of + REGISTER_VIRTUAL_TYPE. + (register_type): New function. + (regcache_dump): Replace REGISTER_VIRTUAL_TYPE with register_type. + * regcache.h (register_type): Declare. + +2002-08-25 Andrew Cagney + + * rs6000-tdep.c (rs6000_gdbarch_init): Set store_struct_return + instead of deprecated_store_return_value. Fix fallout from + 2002-08-23 Andrew Cagney . + +2002-08-25 Andrew Cagney + + * regcache.c (max_register_size): New function. + (init_legacy_regcache_descr): Ensure that max_register_size is + large enough for REGISTER_VIRTUAL_SIZE. + * regcache.h (max_register_size): Declare. + +2002-08-24 Andrew Cagney + + * rs6000-tdep.c (rs6000_gdbarch_init): Use deprecated version of + store_return_value. + (e500_extract_return_value): Change type of valbuf pointer to + void. + +2002-08-24 Mark Kettenis + + * PROBLEMS: Clarify problems with FreeBSD's compiler and suggest + workaround. + + * valprint.c (print_longest) [CC_HAS_LONG_LONG && + PRINTF_HAS_LONG_LONG]: Cast val_long to (long long) or (unsigned + long long) to prevent compiler warning on 64-bit systems. + +2002-08-23 Andrew Cagney + + * gdbarch.sh (STORE_RETURN_VALUE): Add regcache parameter. + (DEPRECATED_STORE_RETURN_VALUE): New method. + (EXTRACT_RETURN_VALUE): Make buffer parameter a void pointer. + * gdbarch.h, gdbarch.c: Re-generate. + + * values.c (set_return_value): Pass current_regcache to + STORE_RETURN_VALUE. + * arch-utils.h (legacy_store_return_value): Declare. + * arch-utils.c (legacy_store_return_value): New function. + (legacy_extract_return_value): Update parameters. + + * config/pa/tm-hppa.h (DEPRECATED_STORE_RETURN_VALUE): Rename + STORE_RETURN_VALUE. + * config/pa/tm-hppa64.h (DEPRECATED_STORE_RETURN_VALUE): Ditto. + * config/sparc/tm-sparc.h (DEPRECATED_STORE_RETURN_VALUE): Ditto. + * config/z8k/tm-z8k.h (DEPRECATED_STORE_RETURN_VALUE): Ditto. + * config/sparc/tm-sparclet.h (DEPRECATED_STORE_RETURN_VALUE): Ditto. + * config/mn10200/tm-mn10200.h (DEPRECATED_STORE_RETURN_VALUE): Ditto. + * config/m68k/tm-linux.h (DEPRECATED_STORE_RETURN_VALUE): Ditto. + * config/m68k/tm-delta68.h (DEPRECATED_STORE_RETURN_VALUE): Ditto. + * config/m32r/tm-m32r.h (DEPRECATED_STORE_RETURN_VALUE): Ditto. + * config/h8500/tm-h8500.h (DEPRECATED_STORE_RETURN_VALUE): Ditto. + * config/h8300/tm-h8300.h (DEPRECATED_STORE_RETURN_VALUE): Ditto. + + * m68hc11-tdep.c (m68hc11_gdbarch_init): Update. + * i386-tdep.c (i386_extract_return_value): Update. + * arch-utils.c (legacy_extract_return_value): Update. + * frv-tdep.c (frv_gdbarch_init): Update. + * cris-tdep.c (cris_gdbarch_init): Update. + * d10v-tdep.c (d10v_gdbarch_init): Update. + * rs6000-tdep.c (rs6000_gdbarch_init): Update. + * m68k-tdep.c (m68k_gdbarch_init): Update. + * mcore-tdep.c (mcore_gdbarch_init): Update. + * mn10300-tdep.c (mn10300_gdbarch_init): Update. + * s390-tdep.c (s390_gdbarch_init): Update. + * sparc-tdep.c (sparc_gdbarch_init): Update. + * sh-tdep.c (sh_gdbarch_init): Update. + * x86-64-tdep.c (x86_64_gdbarch_init): Update. + * v850-tdep.c (v850_gdbarch_init): Update. + * avr-tdep.c (avr_gdbarch_init): Update. + * ia64-tdep.c (ia64_gdbarch_init): Update. + * ns32k-tdep.c (ns32k_gdbarch_init): Update. + * vax-tdep.c (vax_gdbarch_init): Update. + * alpha-tdep.c (alpha_gdbarch_init): Update. + * arm-tdep.c (arm_gdbarch_init): Update. + * mips-tdep.c (mips_gdbarch_init): Update. + * i386-tdep.c (i386_gdbarch_init): Update. + +2002-08-23 Andrew Cagney + + * config/djgpp/fnchange.lst: Add entries for bfd/elf32-ppcqnx.c, + bfd/elf32-ppc.c, bfd/elf32-sh.c and bfd/elf32-shqnx.c. + +2002-08-24 Mark Kettenis + + * PROBLEMS: Refer to GDB 5.3 instead of 5.2. Mention FreeBSD + problems. + +2002-08-23 Joel Brobecker + + * infrun.c (handle_inferior_event): Move a comment outside of a + function call, in order to avoid indent reformatting this part + of the code in an unreadable way. + +2002-08-23 Grace Sainsbury + + * infrun.c (normal_stop, proceed): Remove call to print_sys_errmsg + when breakpoints fail. Move general breakpoint error messages to + insert_breakpoints. + * breakpoint.c (insert_breakpoints): Change warnings when + breakpoints are nto inserted to specify the type. Remove call to + memory_error when hardware breakpoints can't be inserted. Remove + multiple calls to warning so all messages are sent to the user at + once. + (delete_breakpoints): Make insert error messsages more explicit. + +2002-08-23 Daniel Jacobowitz + + * ChangeLog: Move gdbserver entries after GDB 5.2 to + gdbserver/ChangeLog. + +2002-08-23 Mark Kettenis + + * i386-tdep.c: Include "objfiles.h". + (i386_svr4_init_abi): Set in_solib_call_trampoline and + skip_trampoline_code. + * config/i386/tm-i386v4.h: Don't include "config/tm-sysv4.h". + (CPLUS_MARKER): Define to '.'. + + * linux-proc.c (struct linux_corefile_thread_data): Add num_notes + member. + (linux_corefile_thread_callback): Increase args->num_notes. + (linux_make_note_section): Initialize thread_args.num_notes, and + use it to determine whether notes for any threads were created. + +2002-08-23 Donn Terry + + * proc-api.c (rw_table): Do not include a row for PCDSTOP if the + corresponding macro is not defined. Likewise for PCNICE, PCSHOLD + and PCUNKILL. + (write_with_trace): Conditionalize out the switch branch handling + PCSHOLD if the corresponding macro is not defined. Likewise for + PRSABORT and PRSTOP. + This change will be needed by the Interix port. + +2002-08-22 Elena Zannoni + + * ppc-sysv-tdep.c (ppc_sysv_abi_push_arguments): use + write_register wherever possible instead of manipulating the + register bytes directly. + Assign VALUE_CONTENTS to a variable and use that. + The GPR numbers are now dependent on the architecture. + +2002-08-22 Elena Zannoni + + * rs6000-tdep.c (struct rs6000_framedata): Add saved_ev and + ev_offset fields. + (skip_prologue): Add support for BookE/e500 instructions. + (e500_extract_return_value): New function. + (frame_get_saved_regs): Add support for saving ev registers and + pseudo gpr's. + (e500_store_return_value): New function. + (rs6000_gdbarch_init): Move up default intializations of + deprecated_extract_return_value and store_return_value. Overwrite + init of store_return_value with e500 specific version. + Set extract_return_value for e500. + +2002-08-22 Elena Zannoni + + * blockframe.c (generic_call_dummy_register_unwind): Use + regcache_cooked_read to catch cases in which the variable is + stored in a pseudo register. + +2002-08-22 Andrew Cagney + + * NEWS: Mention that the i960 has been made obsolete. + * Makefile.in (SFILES): Delete remote-nrom.c, remote-nindy.c and + i960-tdep.c + (remote-nrom.o): Obsolete target. + (remote-nindy.o, i960-tdep.o): Ditto. + * remote-nrom.c: Make file obsolete. + * remote-nindy.c, remote-vx960.c: Ditto. + * config/i960/vxworks960.mt, config/i960/nindy960.mt: Ditto. + * config/i960/mon960.mt, config/i960/tm-i960.h: Ditto. + * config/i960/tm-vx960.h, config/i960/tm-nindy960.h: Ditto. + * config/i960/tm-mon960.h, i960-tdep.c: Ditto. + * configure.tgt: Make i960-*-bout*, i960-nindy-coff*, + i960-*-coff*, i960-nindy-elf*, i960-*-elf*, i960-*-nindy* and + i960-*-vxworks* obsolete. + * MAINTAINERS: Note that the i960 is obsolete. + +2002-08-21 Corinna Vinschen + + * MAINTAINERS: Change the s390 target to s390-linux-gnu (second + attempt). + +2002-08-22 Jim Blandy + + * coffread.c (coff_symfile_read): Don't try to read the line + number table from disk if the image file doesn't have a symbol + table; we'll never actually look at the info anyway, and Windows + ships DLL's with bogus file offsets for the line number data. + +2002-08-21 Elena Zannoni + + * rs6000-tdep.c (rs6000_gdbarch_init): Figure out whether we have + an e500 executable. + +2002-08-21 Michael Snyder + + * mips-tdep.c (MSYMBOL_IS_SPECIAL): Replace macro with function. + (MSYMBOL_SIZE): Replace macro with function. + (DEFAULT_MIPS_TYPE): Delete unused macro. + * config/mips/tm-mips.h (DEFAULT_MIPS_TYPE): Delete unused macro. + * config/mips/tm-embed.h (DEFAULT_MIPS_TYPE): Delete unused macro. + +2002-08-21 Jim Blandy + + * valops.c (value_cast): Simplify and correct logic for doing a + static cast from a pointer to a base class to a pointer to a + derived class. + +2002-08-21 Andrew Cagney + + * infcmd.c (default_print_registers_info): Replace + do_registers_info. + (registers_info): Use gdbarch_print_registers_info instead of + DO_REGISTERS_INFO. + * inferior.h (default_print_registers_info): Replace + do_registers_info. + * gdbarch.sh (PRINT_REGISTERS_INFO): New method. + (DO_REGISTERS_INFO): Change to a predicate function. + * gdbarch.h, gdbarch.c: Regenerate. + +2002-08-21 Keith Seitz + + * gdb-events.sh: Add target-changed event. + * gdb-events.c: Regenerated. + * gdb-events.c: Regenerated. + * valops.c (value_assign): Add target-changed event notification + to inlval_register, lval_memory, and lval_reg_frame_relative. + +2002-08-21 Joel Brobecker + + * NEWS: Add an entry regarding the improvement of the next/step + operation on Alpha Tru64 multi-processor machines. + +2002-08-21 Andrew Cagney + + * Makefile.in: Update dependencies for mi/ cli/ and tui/ + directores. + * Makefile.in: Update all _h macro definitions. + * Makefile.in (install-gdbtk): Move to install section. + (rdi-share/libangsd.a): Move to end of file. + +2002-08-19 Andrew Cagney + + * frame.c (frame_register_unwind): When a register, set addrp to + the register's byte. + +2002-08-20 Michael Snyder + + * mips-tdep.c (MSYMBOL_IS_SPECIAL, MSYMBOL_SIZE): These are only + used locally, so move them from the target machine header to here. + (mips_set_processor_type, mips_register_name, mips32_next_pc, + mips16_next_pc, cached_proc_desc, mips_set_processor_type): + Make static. + * config/mips/tm-mips.h (MSYMBOL_IS_SPECIAL, MSYMBOL_SIZE): Delete. + +2002-08-20 Andrew Cagney + + * NEWS: Mention that the Apollo line was made obsolete. + * configure.tgt: Make m68*-apollo*-bsd*, m68*-hp-bsd*, and + m68*-hp-hpux* obsolete. + * configure.host: Make m68*-apollo*-sysv*, m68*-apollo*-bsd*, + m68*-hp-bsd* and m68*-hp-hpux* obsolete. + * buildsym.c (make_blockvector): Make static. + * buildsym.h (make_blockvector): Make extern declaration obsolete. + * Makefile.in (HFILES_NO_SRCDIR): Remove dst.h + (ALLDEPFILES): Remove dstread.c. + (dstread.o): Obsolete make rule. + * dstread.c: Makefile obsolete. + * dst.h: Ditto. + * config/m68k/hp300hpux.mt: Ditto. + * config/m68k/hp300hpux.mh: Ditto. + * config/m68k/hp300bsd.mt: Ditto. + * config/m68k/hp300bsd.mh: Ditto. + * config/m68k/apollo68b.mt: Ditto. + * config/m68k/apollo68v.mh: Ditto. + * config/m68k/apollo68b.mh: Ditto. + +2002-08-20 Michael Snyder + + * mips-tdep.c (mips_in_return_stub): Make static. + (mips_gdbarch_init): Set in_solib_return_trampoline. + * config/mips/tm-mips.h (IN_SOLIB_RETURN_TRAMPOLINE): Delete. + +2002-08-20 Michael Snyder + + * gdbarch.sh (IN_SOLIB_RETURN_TRAMPOLINE): Add. + * gdbarch.c, gdbarch.h: Regenerate. + * arch-utils.c, arch-utils.h (generic_in_solib_return_trampoline): + Add. + * infrun.c (IN_SOLIB_RETURN_TRAMPOLINE): Delete default definition. + +2002-08-20 Michael Snyder + + * mips-tdep.c (mips_skip_stub, mips_in_call_stub): Make static. + (mips_gdbarch_init): Set skip_trampoline_code, + in_solib_call_trampoline. + * config/mips/tm-mips.h (REGISTER_NAME): Delete. + (IN_SOLIB_CALL_TRAMPOLINE, SKIP_TRAMPOLINE_CODE): Delete. + +2002-08-20 Elena Zannoni + + * ppc-tdep.h (struct gdbarch_tdep): Add ev registers. + + * rs6000-tdep.c (rs6000_register_virtual_type): Return 64 bit + vector type for ev registers. + (e500_pseudo_register_read): New function. + (e500_pseudo_register_write): New function. + (e500_dwarf2_reg_to_regnum): New function. + (PPC_UISA_NOFP_SPRS): New macro. + (PPC_EV_REGS): New macro. + (PPC_GPRS_PSEUDO_REGS): New macro. + (registers_e500): New register set for e500. + (variants): Add e500 variant. + (rs6000_gdbarch_init): Move setting of pc, sp, fp regnums to + before setting architectural dependent variations. Initialize ev + registers numbers. Add case for e500 architecture. Set the + number of pseudo registers. + +2002-08-20 Elena Zannoni + + * rs6000-tdep.c: Clean up comments. + +2002-08-20 Andrew Cagney + + * h8300-tdep.c: Re-indent file. + +2002-08-20 Jim Blandy + + * Makefile.in (LDFLAGS): Allow the configure script to establish a + default for this. + +2002-08-20 Keith Seitz + + * breakpoints.c (watch_command_1): Use internal breakpoint + when setting a watchpoint_scope breakpoint. + +2002-08-20 Elena Zannoni + + * gdbtypes.c (build_builtin_type_vec64): Add name to type. + (build_builtin_type_vec64i): Ditto. + (build_builtin_type_vec128): Ditto. + (build_builtin_type_vec128i): Ditto. + +2002-08-19 Michael Snyder + + * config/mips/tm-mips.h (ELF_MAKE_MSYMBOL_SPECIAL): Delete. + (MSYMBOL_IS_SPECIAL, MSYMBOL_SIZE): Change into functions. + (FIX_CALL_DUMMY, PUSH_RETURN_ADDRESS, PUSH_DUMMY_FRAME, + POP_FRAME, INIT_EXTRA_FRAME_INFO): Delete. + (CALL_DUMMY_START_OFFSET, CALL_DUMMY_BREAKPOINT_OFFSET, + CALL_DUMMY_ADDRESS): Delete. + * mips-tdep.c (mips_elf_make_msymbol_special, mips_msymbol_size, + mips_msymbol_is_special, mips_fix_call_dummy): New functions. + (mips_gdbarch_init): Set elf_make_msymbol_special, pop_frame, + push_dummy_frame, fix_call_dummy, init_extra_frame_info, + push_return_address. + (mips_register_raw_size, mips_eabi_use_struct_convention, + mips_n32n64_use_struct_convention, mips_o32_use_struct_convention, + mips_o32_reg_struct_has_addr, mips_frame_saved_pc, mips_frame_chain, + mips_init_extra_frame_info, mips_eabi_push_arguments, + mips_n32n64_push_arguments, mips_push_return_address, + mips_push_dummy_frame, mips_pop_frame, mips_skip_prologue, + mips_breakpoint_from_pc, mips_call_dummy_address): Make static. + +2002-08-19 Michael Snyder + + * mips-tdep.c (mips_frame_num_args): New function. + (mips_gdbarch_init): Set frame_chain, frameless_function_invocation, + frame_saved_pc, frame_args_address, frame_locals_address, + frame_num_args, and frame_args_skip. + * config/mips/tm-mips.h (FRAME_CHAIN, FRAMELESS_FUNCTION_INVOCATION, + FRAME_SAVED_PC, FRAME_ARGS_ADDRESS, FRAME_LOCALS_ADDRESS, + FRAME_NUM_ARGS, FRAME_ARGS_SKIP): Delete. + * config/mips/tm-mipsv4.h (FRAME_CHAIN_VALID): Delete. + +2002-08-20 Michael Snyder + + * config/mips/tm-mips.h (STORE_STRUCT_RETURN): Delete. + (EXTRACT_STRUCT_VALUE_ADDRESS): Delete. + * mips-tdep.c (mips_store_struct_return): New function. + (mips_extract_struct_value_address): New function. + (mips_gdbarch_init): Set store_struct_return and + extract_struct_value_address. + +2002-08-20 David Carlton + + * dwarf2read.c (dwarf2_build_psymtabs): Check that + dwarf_line_offset is nonzero before creating dwarf_line_buffer. + (read_file_scope): Check that line_header is nonzero before + decoding macro information. + +2002-08-20 Mark Kettenis + + * i386-tdep.h (FP_REGNUM_P): Change such that we don't incorrectly + flag the general-purpose registers as floating-point on targets + that don't support the floating-point registers. + +2002-08-20 Elena Zannoni + + * rs6000-tdep.c (altivec_register_p): Delete. + (rs6000_do_altivec_registers): Delete. + (rs6000_altivec_registers_info): Delete. + (rs6000_do_registers_info): Delete. + (_initialize_rs6000_tdep): Remove command 'info powerpc altivec'. + (rs6000_gdbarch_init): Remove setting of do_registers_info. + +2002-08-20 Elena Zannoni + + * infcmd.c (do_registers_info): Print vector registers in hex + format only. + (print_vector_info): Check that printing registers + makes sense. + (print_float_info): Ditto. + +2002-08-20 Andrew Cagney + + * mips-tdep.c (mips_gdbarch_init): Update. + (mips_o32_extract_return_value): Rewrite. + (mips_o32_store_return_value): Rewrite. + (mips_o32_xfer_return_value): New function. + (mips_xfer_register): Tweak debug print message. Allow for + buf_offset when dumping the value transfered. + +2002-08-20 Andrew Cagney + + * config/mips/tm-nbsd.h (MIPS_DEFAULT_ABI): Delete. + * config/mips/tm-linux.h (MIPS_DEFAULT_ABI): Delete. + * config/mips/tm-irix5.h (MIPS_DEFAULT_ABI): Delete. + * config/mips/tm-irix6.h (MIPS_DEFAULT_ABI): Delete. + * mips-tdep.c (mips_gdbarch_init) [MIPS_DEFAULT_ABI]: Delete code. + +2002-08-14 Michael Snyder + + * mips-tdep.c (mips_frame_chain): Check for call-dummy frames. + +2002-08-19 Elena Zannoni + + * rs6000-tdep.c (struct reg): Add field to indicate a pseudo + register. + (P): New macro to define a register as a pseudo register. + (R, R4, R8, R16, FR32, R64, R0): Updated. + (struct variant): Add new fields for number of pseudo registers + and number of total registers. + (tot_num_registers): New macro replacing.... + (num_registers): ...deleted macro. + (num_registers): New function. + (num_pseudo_registers): New function. + (variants): Update all variants to intialize new fields correctly. + Postpone initialization of number of pseudo regs and real regs. + (init_variants): New function. + (rs6000_gdbarch_init): Initialize variants. Update calculation of + registers offsets. + +2002-08-19 David Carlton + + * valops.c (search_struct_field): Change error message to treat + return value of 0 from value_static_field as meaning that field is + optimized out. + (value_struct_elt_for_reference): Ditto. + * values.c (value_static_field): Treat an unresolved location the + same as a nonexistent symbol. Fix PR gdb/635. + * gnu-v2-abi.c (gnuv2_value_rtti_type): Eliminate test for being + enclosed. Fix PR gdb/574. + * MAINTAINERS: Add self to Write After Approval list. + +2002-08-19 Andrew Cagney + + * mips-tdep.c (mips_xfer_register): New function. + (mips_n32n64_extract_return_value): Rewrite. + (mips_gdbarch_init): For N32 and N64, set extract_return_value + instead of deprecated_extract_return_value. + +2002-08-19 Elena Zannoni + + * rs6000-tdep.c (TDEP): Delete macro. + (branch_dest): Replace use of TDEP macro with its body. + (rs6000_pop_frame): Ditto. + (rs6000_push_arguments): Ditto. + (rs6000_skip_trampoline_code): Ditto. + (rs6000_frame_saved_pc): Ditto. + (rs6000_frame_chain): Ditto. + (rs6000_register_name): Ditto. + (rs6000_register_byte): Ditto. + (rs6000_register_raw_size): Ditto. + (rs6000_register_virtual_type): Ditto. + (rs6000_register_convertible): Ditto. + (rs6000_convert_from_func_ptr_addr): Ditto. + +2002-08-19 Daniel Jacobowitz + + * config/mips/tm-linux.h (REALTIME_LO, REALTIME_HI): Define + conditionally. + (JB_PC, JB_ELEMENT_SIZE): Rename to MIPS_LINUX_JB_PC and + MIPS_LINUX_JB_ELEMENT_SIZE. + * mips-linux-tdep.c (supply_gregset, fill_gregset): Use alloca + for MAX_REGISTER_RAW_SIZE arrays. + (mips_linux_get_longjmp_target): Use MIPS_LINUX_JB_PC and + MIPS_LINUX_JB_ELEMENT_SIZE. + +2002-08-19 Pierre Muller + + * i387-tdep.c (i387_print_float_info): Fix typo in comment. + +2002-08-19 Aidan Skinner + + * Makefile.in (SFILES): Add ada-exp.y ada-lang.c ada-typeprint.c + ada-valprint.c ada-tasks.c. + (YYFILES): Add ada-exp.y. + (ada-exp.tab.c ada-lex.c ada-lang.o): New target. + (ada-tasks.o ada-typeprint.o ada-valprint.o): New target. + (ada-exp.tab.o): New target. + +2002-08-18 Andrew Cagney + + * regcache.c (regcache_xfer_part): New function. + (regcache_raw_read_part): New function. + (regcache_raw_write_part): New function. + (regcache_cooked_read_part): New function. + (regcache_cooked_write_part): New function. + * regcache.h (regcache_raw_read_part): Declare. + (regcache_raw_write_part): Declare. + (regcache_cooked_read_part): Declare. + (regcache_cooked_write_part): Declare. + +2002-08-18 Daniel Jacobowitz + + * remote.c (remote_open_1): Add async_p. + (remote_async_open_1): Delete. + (open_remote_target): Delete. + (remote_open, extended_remote_open): Update calls to remote_open_1. + (remote_async_open, extended_remote_async_open): Call + remote_open_1 instead of remote_async_open_1. + +2002-08-19 Mark Kettenis + + * blockframe.c: Fix a few coding standard violations. + +2002-08-19 Mark Kettenis + + * config/i386/nm-i386sco5.h (START_INFERIOR_TRAPS_EXPECTED): Moved + here from ... + * config/i386/tm-i386sco5.h: ... here. File removed. + * config/i386/i386sco5.mt (TM_FILE): Set to tm-i386v4.h. + + * config/i386/nm-i386v.h (START_INFERIOR_TRAPS_EXPECTED): New define. + * config/i386/i386aout.mt (TDEPFILES): Add i387-tdep.o + (TM_FILE): Set to tm-i386.h. + * config/i386/i386v.mt (TM_FILE): Set to tm-i386.h. + * config/i386/tm-i386v.h: Remove file. + * config/i386/tm-ptx.h [!SEQUENT_PTX4]: Include "i386/tm-i386.h" + instead of "i386/tm-i386v.h". + (START_INFERIOR_TRAPS_EXPECTED): Remove define. + * config/i386/tm-symmetry: Include "i386/tm-i386.h" instead of + "i386/tm-i386v.h". + (START_INFERIOR_TRAPS_EXPECTED): Remove define. + * config/i386/tm-vxworks.h: Include "i386/tm-i386.h" instead of + "i386/tm-i386.h". + +2002-08-18 Mark Kettenis + + * config/i386/nm-i386v.h: Add protection against + multiple-inclusion. + (i386_register_u_addr): Remove prototype. + (register_u_addr): New prototype. + (REGISTER_U_ADDR): Redefine accordingly. + * i386v-nat.c: Improve several comments. + (i386_register_u_addr): Change signature and rename to + register_u_addr. Use FP_REGNUM_P. Rewrite slightly to get rid of + ubase variable. + +2002-08-18 Andrew Cagney + + * config/mips/tm-mips.h (STORE_RETURN_VALUE): Delete macro. + (DEPRECATED_EXTRACT_RETURN_VALUE): Delete macro. + * mips-tdep.c (mips_gdbarch_init): Set store_return_value and + deprecated_extract_return_value. + (mips_o32_push_arguments, mips_o64_push_arguments): Clone and + rename mips_o32o64_push_arguments. + (mips_gdbarch_init): Update. + (mips_extract_return_value): Delete. + (mips_o32_extract_return_value): Clone mips_extract_return_value. + (mips_o64_extract_return_value): Clone mips_extract_return_value. + (mips_eabi_extract_return_value): Clone mips_extract_return_value. + (mips_n32n64_extract_return_value): Clone + mips_extract_return_value. + (mips_store_return_value): Delete. + (mips_o32_store_return_value): Clone mips_store_return_value. + (mips_o64_store_return_value): Clone mips_store_return_value. + (mips_eabi_store_return_value): Clone mips_store_return_value. + (mips_n32n64_store_return_value): Clone mips_store_return_value. + +2002-08-18 Aidan Skinner + + * ada-lang.c: Use gdb_string.h instead of . + * ada-typeprint.c: Use gdb_string.h instead of . + +2002-08-18 Aidan Skinner + + * ada-lang.c: Run through gdb_indent.sh. + * ada-lang.h: Run through gdb_indent.sh. + * ada-tasks.c: Run through gdb_indent.sh. + * ada-typeprint.c: Run through gdb_indent.sh. + * ada-valprint.c: Run through gdb_indent.sh. + +2002-08-18 Andrew Cagney + + * osabi.c (gdbarch_init_osabi): Don't complain about an unknown + ABI. + +2002-08-18 Mark Kettenis + + * i386b-nat.c [FETCH_INFERIOR_REGISTERS]: Remove dead code. + + * config/i386/nm-i386bsd.h (FLOAT_INFO): Remove redundant #undef. + * i386b-nat.c [FLOAT_INFO]: Remove dead code. + + * i386-tdep.c (i386_do_pop_frame, i386_store_return_value): Call + write_register_gen instead of write_register_bytes. + + * NEWS: Mention that the i[3456]-*mach3*, i[3456]-*-mach* and + i[3456]-*-osf1mk* configurations have been made obsolete. + * configure.host: Make i[3456]86-*-mach3*, i[3456]86-*mach* and + i[3456]86-*-osf1mk* hosts obsolete. + * confighure.tgt: Make i[3456]86-*-mach3*, i[3456]86-*-osf1mk* + targets obsolete. + * config/i386/i386mach.mh, config/i386/nm-i386mach.h, + config/i386/xm-i386mach.h, config/i386/i386m3.mh, + config/i386/i386m3.mt, config/i386/nm-m3.h, + config/i386/tm-i386m3.h, config/i386/xm-i386m3.h, + config/i386/i386mk.mh, config/i386/i386mk.mt, + config/i386/tm-i386mk.h, config/i386/xm-i386mk.h: Make files + obsolete. + * i386mach-nat.c, i386m3-nat.c: Make files obsolete. + * Makefile.in (ALLDEPFILES): Remove i386mach.c i386m3-nat.c + (i386mach-nat.o, i386m3-nat.o):Make targets obsolete. + +2002-08-18 Andrew Cagney + + * config/pa/tm-hppa.h (hppa_store_return_value): Declare. + (hppa_value_returned_from_stack): Declare. + (hppa_extract_return_value): Declare. + * config/pa/hppa.mt: New file. + * configure.tgt: Recognize hppa*-*-*. + * MAINTAINERS: Change HPPA target to hppa-elf. Still broken. + +2002-08-18 Mark Kettenis + + * i386-sol2-tdep.c (_initialize_i386_sol2_tdep): Fix typo in + comment. + +2002-08-17 Mark Kettenis + + * top.c (gdb_rl_operate_and_get_next): Make sure + operate-and-get-next functions correctly even when the history + list is completely filled. + +2002-08-18 Andrew Cagney + + * MAINTAINERS (Target Instruction Set Architectures): Rename + Target/Architectures. Replace vax-dec-vms5.5 with vax-netbsd. + Replace s390-linux with s390-linux-gnu. Remove i386-aout, + mcore-pe, mips64-elf, sparc64-elf. Remove i586-pc-msdosdjgpp, + already listed under Host/Native. + + * configure.tgt: Combine i[3456]86-*-coff*, i[3456]86-*-elf*, + i[3456]86-*-pe*, and i[3456]86-*-aout* into i[3456]86-*-*. Add + mips*-*-*. + +2002-08-17 Andrew Cagney + + * config/ia64/ia64.mt: New file. + * config/alpha/alpha.mt: New file. + * MAINTAINERS: Change the alpha target to alpha-elf and IA-64 to + ia64-linux-gnu. Mention that ia64-elf is broken. + * configure.tgt: Add alpha*-*-* and ia64*-*-* patterns. + +2002-08-17 Mark Kettenis + + * i386-tdep.c (i386_svr4_init_abi, i386_nw_init_abi): Use + generic_func_frame_valid instead of func_frame_valid. + +2002-08-16 Joel Brobecker + + * alpha-osf1-tdep.c (alpha_osf1_init_abi): Unfortunately, + procfs appears to be broken when debugging on multi-processor + machines. So enable software single stepping in order to avoid + using the procfs interface to do next/step operations, using + internal breakpoints instead. + + * infrun.c (handle_inferior_event): Readjust the stop_pc by + DECR_PC_AFTER_BREAK when hitting a single step breakpoint, to + make this pc address equal to the value it would have if the + system stepping capability was used. Also set a new flag used + to ensure that we don't readjust the PC one more time later. + + * breakpoint.c (bpstat_stop_status): Do not adjust the PC + address by DECR_PC_AFTER_BREAK when software single step is + in use for this architecture, as this has already been taken + care of in handle_inferior_event(). + +2002-08-16 Joel Brobecker + + * infrun.c (handle_inferior_event): Minor reformatting, to make + a rather long condition expression easier to read. + +2002-08-16 Andrew Cagney + + * Makefile.in (gdbtk.o): Move to end of file. + (gdbtk-bp.o, gdbtk-cmds.o): Ditto. + (gdbtk-hooks.o, gdbtk-register.o): Ditto. + (gdbtk-stack.o, gdbtk-varobj.o): Ditto. + (gdbtk-wrapper.o, gdbres.o): Ditto. + +2002-08-16 Andrew Cagney + + * Makefile.in (copying.o): Separate out compile rule. + (hpux-thread.o, procfs.o, signals.o): Ditto. + (v850ice.o, z8k-tdep.o): Ditto. + (tui-file.o): Move to TUI section. + (xdr_ptrace.o, xdr_rdb.o, xdr_ld.o): Move to separate section. + (nindy.o, Onindy.o, ttyflush.o): Move to separate section. + +2002-08-16 Joel Brobecker + + * i386-tdep.c (i386_pe_skip_trampoline_code): renamed from + skip_trampoline_code, for better namespace-proofing. + + * i386-tdep.h (i386_pe_skip_trampoline_code): Add declaration. + +2002-08-16 Joel Brobecker + + * config/i386/tm-cygwin.h: Remove some "#if 0"'ed macros. + +2002-08-16 Joel Brobecker + + * infrun.c (handle_inferior_event): When receiving a SIGTRAP + signal, check whether we hit a breakpoint before checking for a + single step breakpoint. Otherwise, GDB fails to notice that a + breakpoint has been hit when stepping onto a breakpoint. + +2002-08-16 Keith Seitz + + * gdb-events.sh (clear_gdb_event_hooks): New function. + * gdb-events.c: Regenerate. + * gdb-events.h: Regenerate. + +2002-08-16 Andrew Cagney + + * breakpoint.c (bpstat_stop_status): Rename not_a_breakpoint to + not_a_sw_breakpoint. + * breakpoint.h (bpstat_stop_status): Add parameter names. + +2002-08-16 Grace Sainsbury + + * remote.c (remote_insert_hw_breakpoint) + (remote_remove_hw_breakpoint): Fix calculation of length field + for Z-packet. + +2002-08-15 Michael Snyder + + * irix5-nat.c (supply_gregset): Allocate plenty-big buffer + (32 bytes) instead of using MAX_REGISTER_RAW_SIZE. + (supply_fpregset): Ditto. + + * config/mips/tm-mips.h (REGISTER_CONVERT_TO_VIRTUAL, + REGISTER_CONVERT_TO_RAW, REGISTER_CONVERTIBLE, + MAX_REGISTER_RAW_SIZE, MAX_REGISTER_VIRTUAL_SIZE): Delete. + (TARGET_READ_SP): Delete. + (DO_REGISTERS_INFO): Delete. + (FUNCTION_START_OFFSET, IN_SIGTRAMP, REGISTER_VIRTUAL_SIZE): + Delete. + (REGISTER_CONVERT_FROM_TYPE, REGISTER_CONVERT_TO_TYPE): Convert + from macros to functions. + + * mips-tdep.c (mips_gdbarch_init): Set the above in the gdbarch. + (mips_register_convertible, mips_register_convert_to_virtual, + mips_register_convert_to_raw): Make static. + (mips_read_sp): New function. + (mips_gdbarch_init): Set gdbarch read_sp to mips_read_sp. + (mips_do_registers_info): Make static. + (mips_gdbarch_init): Insert mips_do_registers_info into gdbarch. + (in_sigtramp): Make static, rename to mips_pc_in_sigtramp. + (mips_register_convert_from_type, mips_register_convert_to_type): + New functions. + (mips_gdbarch_init): Set up function_start_offset, + register_virtual_size, pc_in_sigtramp. + +2002-08-15 Andrew Cagney + + * infcmd.c (vector_info): New function. + (_initialize_infcmd): Add command "info vector". + (print_vector_info): New function. + + * gdbarch.sh (PRINT_VECTOR_INFO): New method + * gdbarch.h, gdbarch.c: Regenerate. + +2002-08-15 Andrew Cagney + + * infcmd.c (do_registers_info): Rename parameter ``fpregs'' to + ``print_all''. Only print vector registers when ``print_all''. + +2002-08-15 Andrew Cagney + + * i387-tdep.h (i387_print_float_info): Add `args' parameter. + * i387-tdep.c (i387_print_float_info): Add `args' parameter. + + * gdbarch.sh (PRINT_FLOAT_INFO): Change to a predicate method. + Add `args' parameter. + * gdbarch.h, gdbarch.c: Regenerate. + + * arm-tdep.c (arm_print_float_info): Add the parameter `args'. + + * infcmd.c (float_info): Call print_float_info. + (print_float_info): New function. By default, print the + floating-point registers. + + * arch-utils.h (default_print_float_info): Delete declaration. + * arch-utils.c (default_print_float_info): Delete function. + +2002-08-16 Mark Kettenis + + * config/i386/nm-i386v.h (FLOAT_INFO): Remove already commented + out define. + + * i387-tdep.c (i387_print_float_info): Add comment about ignoring + FRAME. + + * NEWS: Mention that the i[3456]-*-aix target has been made obsolete. + * configure.host: Make i[3456]86-*-aix host obsolete. + * configure.tgt: Make i[3456]86-*-aix target obsolete. + * config/i386/i386aix.mh, config/i386/i386aix.mt, + config/i386/nm-i386aix.h, condig/i386/tm-i386aix.h, + config/i386/xm-i386aix.h: Make files obsolete. + * i386aix-nat.c: Make file obsolete. + * Makefile.in (ALLDEPFILES): Remove i386aix-nat.c. + (i386aix-nat.o): Make target obsolete. + + * config/i386/nm-gnu.h: Removed. + * config/i386/nm-i386gnu.h: New file. + (THREAD_STATE_FLAVOR, THREAD_STATE_SIZE, + THREAD_STATE_SET_TRACED, THREAD_STATE_CLEAR_STATE, ATTACH_DETACH): + Moved here from ... + * config/i386/tm-i386gnu.h: ... here. Removed. + * config/i386/xm-i386gnu.h: Removed. + * config/i386/i386gnu.mh (XM_FILE): Set to xm-i386.h. + (NAT_FILE): Set to nm-i386gnu.h. + * config/i386/i386gnu.mt (TDEPFILES): Add i386gnu-tdep.o. + * i386-tdep.c: New file. + * Makefile.in (ALLDEPFILES): Add i386gnu-nat.c and i386gnu-tdep.c. + (i386gnu-tdep.o): Specify dependencies. + +2002-08-15 Mark Kettenis + + * config/i386/tm-i386sco5.h: Include "i386/tm-i386v4.h" instead of + "i386/tm-i386.h", "i386/tm-i386v.h" and "config/tm-sysv.h". + Adjust a few comments to reflect reality a bit closer. + (KERNEL_U_SIZE, TARGET_HAS_HARDWARE_WATCHPOINTS, + TARGET_CAN_USE_HARDWARE_WATCHPOINT, HAVE_CONTINUEABLE_WATCHPOINT, + HAVE_STEPPABLE_WATCHPOINT, STOPPED_BY_WATCHPOINT, + target_insert_watchpoint, target_remove_watchpoint): + Move defines to ... + * config/i386/nm-i386sco5.h: ... here. + (kernel_u_size): Add prototype. Improve a few comments and add + protection against multiple inclusion. + + * config/i386/nm-i386sco.h (FLOAT_INFO): Remove already commented + out define. + + * uw-thread.c (SP_ARG0): Define if not already defined. + * config/i386/tm-i386.h (SO_ARG0): Remove define. + + * config/i386/tm-i386v4.h (HAVE_I387_REGS): Remove define. + + * config/i386/tm-i386.h: Don't include "regcache.h". + + * i387-tdep.h (i387_print_float_info): New prototype. + * i387-tdep.c (print_i387_value, print_i387_ext, + print_i387_status_word, print_i387_control_word): Add `struct + ui_file *' argument and use it for output. + (i387_print_float_info): Renamed from i387_float_info. Add + `struct gdbarch *' and `struct ui_file *' arguments and use the + latter for output. + * i386-tdep.c: Include "i387-tdep.h". + (i386_gdbarch_init): Set print_float_info. + * config/i386/tm-i386.h (i387_float_info): Remove prototype. + (FLOAT_INFO): Remove define. + +2002-08-13 Michael Snyder + + * mips-tdep.c (mips_push_arguments): Rename to + mips_eabi_push_arguments, and tune for EABI. + (MIPS_REGS_HAVE_HOME_P): Delete. + (struct gdbarch_tdep): Remove mips_regs_have_home_p field. + (mips_gdbarch_init): Set gdbarch push_arguments for eabi. + Delete references to mips_regs_have_home_p. + +2002-08-14 Keith Seitz + + * Makefile.in (install-gdbtk): Create insight plugin directory. + Install plugins.tcl file. + +2002-08-14 Keith Seitz + + * configure.in: Move SUBDIRS to near top of the file so that + --enable options may add things to it. + If gdbtk is enabled, add gdbtk directory to SUBDIRS and configdirs. + * configure: Regenerate. + +2002-08-13 Michael Snyder + + * mips-tdep.c (mips_o32o64_push_arguments): New function, + cloned from mips_push_arguments, tuned for o32/o64 ABI. + (mips_gdbarch_init): Set gdbarch_push_arguments to new func. + +2002-08-13 Andrew Cagney + + * vax-tdep.c (vax_get_saved_register): Delete function. + (vax_gdbarch_init): Update. + * ns32k-tdep.c (ns32k_get_saved_register): Delete function. + (ns32k_gdbarch_init): Update. + * alpha-tdep.c (alpha_get_saved_register): Delete function. + (alpha_gdbarch_init): Update. + +2002-08-13 Andrew Cagney + + * regcache.c (init_regcache_descr): Overallocate the + raw_register_valid_p array including space for NUM_PSEUDO_REGS. + (registers_changed): Replace NUM_REGS+NUM_PSEUDO_REGS with + nr_raw_registers. + (set_register_cached): Add range checking assertions. Use + current_regcache. + +2002-08-13 Mark Kettenis + + * i386-tdep.c (i386_stab_reg_to_regnum): Return correct register + numbers for MMX registers. + +2002-08-13 Andrew Cagney + + * i386-tdep.c (i386_gdbarch_init): Use + generic_unwind_get_saved_register. + +2002-08-13 Kevin Buettner + + * procfs.c (procfs_can_use_hw_breakpoint): New function. + (init_procfs_ops): Define ``to_can_use_hw_breakpoint'' for procfs + target vector. + * config/mips/nm-irix5.h (TARGET_CAN_USE_HARDWARE_WATCHPOINT): + Delete. Add comment regarding this now-deleted target method. + +2002-08-13 Stephane Carrez + + * m68hc11-tdep.c (M68HC12_NUM_PSEUDO_REGS): New define. + (M68HC12_HARD_PC_REGNUM): Define specific PC for 68HC12 (pseudo reg). + (m68hc11_pseudo_register_read): Compute the 68HC12 PC using the + real PC and the page number (if it's within the memory bank window). + (m68hc11_pseudo_register_write): Likewise when saving. + (m68hc11_register_name): Name the virtual pc 'pc' and the real one ppc. + (m68hc11_register_virtual_type): Return uint32 for virtual pc. + (m68hc11_register_raw_size): And use 32-bit for it. + (m68hc11_gdbarch_init): Use 32-bit address for 68HC12 if the + 16K memory bank is used by the prog; also use the virtual pc. + +2002-08-13 Stephane Carrez + + * m68hc11-tdep.c (m68hc11_elf_make_msymbol_special): New function. + (m68hc11_gdbarch_init): Install it in gdbarch. + (MSYMBOL_SET_RTC, MSYMBOL_SET_RTI): New to set symbol specific flags. + (MSYMBOL_IS_RTC, MSYMBOL_IS_RTI): New to test these flags. + (MSYMBOL_SIZE): New for documentation. + (insn_return_kind): Enum to specify how a function returns. + (frame_extra_info): Cleanup and record the return mode. + (gdbarch_tdep, USE_PAGE_REGISTER): New to control the use of page + register in address computation. + (m68hc11_get_return_insn): New to obtain the return instruction used + by the function. + (m68hc11_frame_init_saved_regs): Take into account the return + instruction used by the function for far and interrupt functions. + (m68hc11_init_extra_frame_info): Take into account page register. + (m68hc11_frame_args_address): Adjust according to the return mode. + (show_regs): Print page register only when it's used. + +2002-08-13 Stephane Carrez + + * m68hc11-tdep.c (HARD_PAGE_REGNUM): Define for 68HC12 page register. + (M68HC11_LAST_HARD_REG, m68hc11_register_names): Update. + (m68hc11_register_virtual_type): Return a 8-bit type for 8-bit + registers. + (m68hc11_register_raw_size): Likewise. + +2002-08-13 Andrew Cagney + + * i386-tdep.c (i386_register_name): Handle mmx registers. + (mmx_regnum_p): New function. + (i386_mmx_names): New array. + (mmx_num_regs): New variable. + (i386_pseudo_register_read): New function. + (i386_pseudo_register_write): New function. + (mmx_regnum_to_fp_regnum): New function. Code from Fernando Nasser. + + * regcache.c (regcache_raw_read_unsigned): New function. + (regcache_raw_read_signed): New function. + * regcache.h (regcache_raw_read_unsigned): Declare. + (regcache_raw_read_signed): Declare. + +2002-08-13 Andrew Cagney + + * regcache.c (regcache_raw_read_as_address): Delete function. + (regcache_cooked_read_signed): New function. + (regcache_cooked_read_unsigned): New function. + * regcache.h (regcache_cooked_read_signed): Declare. + (regcache_cooked_read_unsigned): Declare. + (regcache_raw_read_as_address): Delete declaration. + + * blockframe.c (generic_read_register_dummy): Use + regcache_cooked_read_unsigned. + * i386-tdep.c (i386_extract_struct_value_address): Use + regcache_cooked_read_unsigned. + +2002-08-13 Stephane Carrez + + * m68hc11-tdep.c (m68hc11_gdbarch_init): Set int, double and long + double sizes according to ELF ABI flags. + (gdbarch_tdep): Record elf_flags. + +2002-08-13 Stephane Carrez + + * m68hc11-tdep.c (M6812_OP_PSHX, M6812_OP_PSHY): New defines. + (m6812_prolog): They can appear in 68HC12 function prologue. + (m68hc11_frame_chain): Cleanup. + +2002-08-12 Andrew Cagney + + * i386-tdep.h (i386_register_byte, i386_register_raw_size): Delete + declarations. + * i386-linux-tdep.c (i386_linux_register_byte): Delete function. + (i386_linux_register_raw_size): Delete function. + (i386_linux_init_abi): Update. + * i386-tdep.c (i386_register_raw_size): Delete function. + (i386_register_byte): Delete function. + (i386_gdbarch_init): Update. + (i386_register_size): Delete array. + (i386_register_offset): Delete array. + + * config/i386/tm-symmetry.h (REGISTER_BYTE): Delete macro. + (REGISTER_RAW_SIZE): Delete macro. + * config/i386/tm-ptx.h (REGISTER_RAW_SIZE): Delete macro. + (REGISTER_BYTE): Delete macro. + +2002-08-11 Aidan Skinner + + * ada-lang.c (ada_lookup_partial_symbol) + (to_fixed_variant_branch_type) (find_line_in_linetable): Fix + prototype names so that grep ^func works properly. + + * ada-lang.c (ada_array_element_type) + (ada_lookup_partial_symbol): Fix typos in parameter list. + + * ada-valprint.c (val_print_packed_array_elements) (ada_val_print_1): + Fix prototype names so that grep ^func works properly. + +2002-08-10 Andrew Cagney + Elena Zannoni + Martin M. Hunt + + * gdbtypes.c (build_builtin_type_vec128): Set the vector bit. + (build_builtin_type_vec128i): Set the vector bit. + * gdbtypes.h (builtin_type_vec64, builtin_type_vec64i): Declare. + * gdbtypes.c (builtin_type_vec64, builtin_type_vec64i): Define. + (build_builtin_type_vec64): New function. + (build_builtin_type_vec64i): New function. + (build_gdbtypes): Initialize builtin_type_vec64 and + builtin_type_vec64i. + +2002-08-09 Andrew Cagney + + * regcache.c (regcache_dump): Compare the register offset + with REGISTER_BYTE. + * arch-utils.c (generic_register_byte): New function. + * arch-utils.h (generic_register_byte): Declare. + * gdbarch.sh (REGISTER_BYTE): Default to generic_register_byte. + * gdbarch.h, gdbarch.c: Regenerate. + +2002-08-09 Andrew Cagney + + * regcache.c: Include "gdbcmd.h" + (_initialize_regcache): Add commands "maintenance print + registers", "maintenance print raw-registers" and "maintenance + print cooked-registers". + (enum regcache_dump_what): Define. + (dump_endian_bytes): New function. + (regcache_dump): New function. + (regcache_print): New function. + (maintenance_print_registers): New function. + (maintenance_print_raw_registers): New function. + (maintenance_print_cooked_registers): New function. + * Makefile.in (regcache.o): Update dependencies. + +2002-08-09 Michael Snyder + + * mips-tdep.c (ROUND_DOWN, ROUND_UP): Move to global scope. + (mips_push_arguments): Correct some comments. Use paddr_nz + for printing addresses in debug output. Replace static + allocation using MAX_REGISTER_RAW_SIZE with alloca. + (mips_n32n64_push_arguments): New function, cloned from + mips_push_arguments and tuned for the n32/n64 ABI. + (mips_push_register): Buffer needs dynamic allocation. + (mips_print_register): Ditto. + (do_gp_register_row): Ditto. + (mips_store_return_value): Ditto. + (mips_gdbarch_init): Set gdbarch_push_arguments per ABI. + +2002-08-09 Don Howard + + * memattr.c (mem_info_command): Print special case of upper bound + as max CORE_ADDR + 1. + +2002-08-08 Michael Snyder + + * mips-tdep.c (mips_n32n64_use_struct_convention): N32 only + returns structs by ref if they're too big to fit in two registers. + +2002-08-09 Kevin Buettner + + * mips-tdep.c (mips_init_extra_frame_info): Initialize SP_REGNUM's + saved regs value. + (read_next_frame_reg): Call FRAME_INIT_SAVED_REGS instead of + mips_find_saved_regs(). + (mips_pop_frame): Likewise. + +2002-08-09 Kevin Buettner + + * blockframe.c (frame_saved_regs_register_unwind): Revise + PC_IN_CALL_DUMMY assertion to only apply when generic dummy + frames are in use. + +2002-08-09 Grace Sainsbury + + * remote.c: (remote_wait, remote_async_wait): Add check for awatch + T-packets; the 'a' is not taken as a register number. + (remote_check_watch_resources, remote_stopped_by_watchpoint) + (remote_stopped_data_address): New functions; add to target + vector. + (remote_insert_hw_breakpoint, remote_remove_hw_breakpoint): Change + prototypes to match other implementations of this + function. replace integer argument with pointer -- the length + field in the Z-packet is the length of what is pointed to or 1 if + pointer is null. Add to target vector. + (remote_insert_watchpoint, remote_remove_watchpoint): Add to + target vector. + + From Mark Salter: + * remote.c (remote_wait): Add support to extract optional + watchpoint information from T-packet. Ignore unrecognized + optional info in T-packet. + (remote_async_wait): Ditto. + +2002-08-09 Corinna Vinschen + + * cli/cli-dump.c: Change fopen modes to use binary open modes + as defined in include/fopen-bin.h throughout. + +2002-08-08 Michael Snyder + + * mips-tdep.c: Minor whitespace and indentation clean-ups. + +2002-08-08 Kevin Buettner + + * doublest.c (store_floating): Avoid floatformat_from_doublest() + assertion failure by returning early after a warning. + +2002-08-08 Kevin Buettner + + * mips-tdep.c (mips_find_saved_regs): Make static. + (mips_frame_init_saved_regs): New function. + (mips_gdbarch_init): Setup FRAME_INIT_SAVED_REGS method. + * config/mips/tm-mips.h (FRAME_INIT_SAVED_REGS): Delete macro. + (mips_find_saved_regs): Delete declaration. + +2002-08-08 Grace Sainsbury + + * remote.c (remote_wait, remote_async_wait): Change + thread_num from int to ULONGEST. + (unpack_varlen_hex): Change result parameter from + int * to ULONGEST *. + +2002-08-08 Andrew Cagney + + * configure.tgt: Replace powerpc-*-sysv*, powerpc-*-elf*, + powerpcle-*-eabi*, powerpcle-*-sysv* and powerpcle-*-elf* with + powerpc*-*-*. + * MAINTAINERS: Remove redundant rs6000-ibm-aix4.1 target. + +2002-08-08 Andrew Cagney + + * gcore.c (override_derive_stack_segment): Delete variable. + (preempt_derive_stack_segment): Delete function. + (derive_stack_segment): Delete function. + (default_derive_stack_segment): Renamed to derive_stack_segment. + (override_derive_heap_segment): Delete variable. + (preempt_derive_heap_segment): Delete function. + (derive_heap_segment): Delete function. + (default_derive_heap_segment): Rename to derive_heap_segment. + +2002-08-06 Michael Snyder + + * config/mips/tm-mips.h: Remove #define USE_STRUCT_CONVENTION. + * mips-tdep.c (mips_EABI_use_struct_convention, + mips_OABI_use_struct_convention, mips_NABI_use_struct_convention): + New functions. (mips_use_struct_convention): Delete. + (mips_gdbarch_init): set use_gdbarch_convention. + +2002-08-06 Michael Snyder + + * mips-tdep.c: gdbarch-ify reg_struct_has_addr. + (mips_eabi_reg_struct_has_addr, mips_n32n64_reg_struct_has_addr, + mips_o32_reg_struct_has_addr): New functions. + (mips_gdbarch_init): Set gdbarch reg_struct_has_addr. + +2002-08-07 Andrew Cagney + + * regcache.c (pseudo_register): Delete function. + (fetch_register): Delete function. + (store_register): Delete function. + (regcache_raw_read, legacy_read_register_gen): Use + target_fetch_registers instead of fetch_register. + (legacy_write_register_gen, regcache_raw_write): Use + target_store_register instead of store_register. + (write_register_bytes): Ditto. + + * gdbarch.sh (FETCH_PSEUDO_REGISTER): Delete. + (STORE_PSEUDO_REGISTER): Delete. + * gdbarch.h, gdbarch.c: Regenerate. + +2002-08-06 Corinna Vinschen + + * cli/cli-dump.c (add_dump_command): Explicitely use "b" flag to + write dump file binary. + +2002-08-05 Michael Snyder + + * mips-tdep.c (mips_find_saved_regs): Adjust stack according + to MIPS_SAVED_REGSIZE, not GDB_TARGET_IS_MIPS64. Enhance comment. + (mips_gdbarch_init): Set N32 target to be mips64. + +2002-08-06 Kevin Buettner + + * frame.c (find_saved_register): Break out of loop once saved + register address is found. Don't mention sparc in loop comment + anymore. + +2002-08-06 Kevin Buettner + + * mips-tdep.c (mips_gdbarch_init): For the N32 ABI, set + mips_default_saved_regsize to 8. + +2002-08-06 Andrew Cagney + + * gcore.c: Do not include . + * Makefile.in (gcore.o): Update dependencies. + +2002-08-06 Andrew Cagney + + * configure.tgt: Make arc-*-* obsolete. + * NEWS: Mention that arc-*-* has been identifed as obsolete. + * MAINTAINERS: Make arc-elf obsolete. + * arc-tdep.c: Make file obsolete. + * config/arc/arc.mt: Ditto. + * config/arc/tm-arc.h: Ditto. + +2002-08-05 Theodore A. Roth + + * avr-tdep.c (avr_skip_prologue): Fix to return the correct pc. + +2002-08-05 Andrew Cagney + + * mcore-tdep.c (mcore_gdbarch_init): Use + generic_unwind_get_saved_register instead of + generic_get_saved_register. + * v850-tdep.c (v850_gdbarch_init): Ditto. + * frv-tdep.c (frv_gdbarch_init): Ditto. + * mn10300-tdep.c (mn10300_gdbarch_init): Ditto. + * s390-tdep.c (s390_gdbarch_init): Ditto. + * d10v-tdep.c (d10v_gdbarch_init): Ditto. + * config/mn10200/tm-mn10200.h (GET_SAVED_REGISTER): Ditto. + * config/h8300/tm-h8300.h (GET_SAVED_REGISTER): Ditto. + +2002-08-05 Joel Brobecker + + * objfiles.h: Add missing #include "symfile.h" + + * Makefile.in (objfiles_h): Add dependency on symfile.h and dependents. + +2002-08-04 Andrew Cagney + + From 2002-08-01 david carlton : + * hpread.c (hpread_read_struct_type): Deleted superfluous setting + of FIELD_BITSIZE. + +2002-08-04 Daniel Jacobowitz + + * NEWS: Cleanup and nitpick. + +2002-08-03 Andrew Cagney + + * NEWS: Cleanup. Use *-linux*-gnu*. Only use `*' for headings. + +2002-08-03 Andrew Cagney + + * Makefile.in (gdbtk-bp.o): Update dependencies. + (gdbtk-register.o): Ditto. + (gdbtk-varobj.o): Ditto. + +2002-08-03 Andrew Cagney + + * m68hc11-tdep.c (m68hc11_pseudo_register_read): Replace + m68hc11_fetch_pseudo_register. + (m68hc11_pseudo_register_write): Replace + m68hc11_store_pseudo_register. + (m68hc11_gdbarch_init): Update. + +Fri Aug 2 15:53:50 2002 Andrew Cagney + + * gdbarch.sh: Include "gdb_string.h". + * gdbarch.c: Regenerate. + + * regcache.c: Include "gdb_string.h". + * ax-general.c: Ditto. + * varobj.c: Ditto. + * std-regs.c: Ditto. + * fbsd-proc.c: Ditto. + * thread.c: Ditto. + + * Makefile.in (regcache.o): Update dependencies. + (thread.o, gdbarch.o): Ditto. + (ax-general.o, gdbarch.o): Ditto. + (varobj.o, std-regs.o): Ditto. + (fbsd-proc.o): Specify dependencies. + +2002-08-02 Andrew Cagney + + * regcache.c (regcache_cooked_read): Rename rawnum parameter to + regnum. + (regcache_cooked_write): Ditto. + +2002-08-02 Andrew Cagney + + * regcache.c (regcache_cooked_read): New function. + (regcache_cooked_write): New function. + (read_register_gen): Rewrite using regcache_cooked_read. + (write_register_gen): Rewrite using regcache_cooked_write. + + * regcache.h (regcache_cooked_read, regcache_cooked_write): + Declare. + +2002-08-02 Andrew Cagney + + * gdbarch.sh (pseudo_register_read, pseudo_register_write): + Replace the architecture methods register_read and register_write. + * gdbarch.h, gdbarch.c: Regenerate. + * regcache.c (init_regcache_descr): Update. + (read_register_gen): Update. + (write_register_gen): Update. + (supply_register): Update comment. + + * sh-tdep.c (sh_gdbarch_init): Update. + (sh_pseudo_register_read, sh64_pseudo_register_read): Add + `regcache' and `gdbarch' parameters. Make `buffer' a void + pointer. Update code. + (sh_pseudo_register_write, sh64_pseudo_register_write): Add + `regcache' and `gdbarch' parameters. Make `buffer' a constant + void pointer. Update code. + (sh64_register_write): Delete. + (sh4_register_read): Delete. + (sh64_register_read): Delete. + (sh4_register_write): Delete. + (sh_sh4_register_convert_to_raw): Make `from' parameter a constant + void pointer, `to' parameter a void pointer. + (sh_sh64_register_convert_to_raw): Ditto. + +2002-08-01 Kevin Buettner + + * mips-tdep.c (mips_register_virtual_type): Use architecture + invariant return values. + +2002-08-01 Andrew Cagney + + * linux-proc.c: Include "gdb_string.h". + * Makefile.in (linux-proc.o): Update dependency list. + +2002-08-01 Kevin Buettner + + * mips-tdep.c (mips_gdbarch_init): Add comments. Fix typo in + comment. + +2002-08-01 Grace Sainsbury + + * target.h: Add to_insert_hw_breakpoint, to_remove_hw_breakpoint, + to_insert_watchpoint, to_remove_watchpoint, + to_stopped_by_watchpoint, to_stopped_data_address, + to_region_size_ok_for_hw_watchpoint, to_can_use_hw_breakpoint to + target vecctor. Define their corresponding macros so they call + them. + + * target.c: Add default and debug versions of for + to_insert_hw_breakpoint, to_remove_hw_breakpoint, + to_insert_watchpoint, to_remove_watchpoint, + to_stopped_by_watchpoint, to_stopped_data_address, + to_region_size_ok_for_hw_watchpoint, to_can_use_hw_breakpoint. + +2002-08-01 Kevin Buettner + + * mips-tdep.c (mips_register_virtual_type): New function. + (mips_gdbarch_init): Register mips_register_virtual_type() + with gdbarch machinery. + * config/mips/tm-irix6.h (mips/tm-bigmips64.h): Include + this file instead of tm-bigmips.h. + (MIPS_REGSIZE): Delete this macro. + (REGISTER_VIRTUAL_TYPE): Delete macro. Undef macro so that + multiarch version in mips-tdep.c will be found. + +2002-08-01 Andrew Cagney + + * NEWS: Menion that CHILL has been made obsolete. + + * gdbtypes.c (chill_varying_type): Make chill references obsolete. + * stabsread.c (read_range_type): Ditto. + * gdbtypes.h: Ditto. + * language.c (binop_type_check): Ditto. + (binop_result_type): Ditto. + (integral_type): Ditto. + (character_type): Ditto. + (string_type): Ditto. + (boolean_type): Ditto. + (structured_type): Ditto. + (lang_bool_type): Ditto. + (binop_type_check): Ditto. + * language.h (_LANG_chill): Ditto. + * dwarfread.c (set_cu_language): Ditto. + * dwarfread.c (CHILL_PRODUCER): Ditto. + * dwarfread.c (handle_producer): Ditto. + * expression.h (enum exp_opcode): Ditto. + * eval.c: Ditto for comments. + * typeprint.c (typedef_print) [_LANG_chill]: Ditto. + * expprint.c (print_subexp): Ditto. + (print_subexp): Ditto. + * valops.c (value_cast): Ditto. + (search_struct_field): Ditto. + * value.h (COERCE_VARYING_ARRAY): Ditto. + * symfile.c (init_filename_language_table): Ditto. + (add_psymbol_with_dem_name_to_list): Ditto. + * valarith.c (value_binop): Ditto. + (value_neg): Ditto. + * valops.c (value_slice): Ditto. + * symtab.h (union language_specific): Ditto. + (SYMBOL_INIT_LANGUAGE_SPECIFIC): Ditto. + (SYMBOL_DEMANGLED_NAME): Ditto. + (SYMBOL_CHILL_DEMANGLED_NAME): Ditto. + * defs.h (enum language): Ditto. + * symtab.c (got_symtab): Ditto. + * utils.c (fprintf_symbol_filtered): Ditto. + + * ch-typeprint.c: Make file obsolete. + * ch-valprint.c: Make file obsolete. + * ch-lang.h: Make file obsolete. + * ch-exp.c: Make file obsolete. + * ch-lang.c: Make file obsolete. + + * Makefile.in (FLAGS_TO_PASS): Do not pass CHILL or CHILLFLAGS or + CHILL_LIB. + (TARGET_FLAGS_TO_PASS): Ditto. + (CHILLFLAGS): Obsolete. + (CHILL): Obsolete. + (CHILL_FOR_TARGET): Obsolete. + (CHILL_LIB): Obsolete. + (SFILES): Remove ch-exp.c, ch-lang.c, ch-typeprint.c and + ch-valprint.c. + (HFILES_NO_SRCDIR): Remove ch-lang.h. + (COMMON_OBS): Remove ch-valprint.o, ch-typeprint.o, ch-exp.o and + ch-lang.o. + (ch-exp.o, ch-lang.o, ch-typeprint.o, ch-valprint.o): Delete + targets. + +2002-07-31 Joel Brobecker + + * dwarf2read.c (set_cu_language): Add handler for LANG_Ada95. + This does not change anything at the moment, but will be helpful + later when full Ada support is integrated. + +2002-07-31 Kevin Buettner + + * mips-tdep.c (_initialize_mips_tdep): Add "n64" to "set mips abi" + help message. + +2002-07-31 Kevin Buettner + + * mips-tdep.c (mips_push_arguments): Fetch gdbarch_tdep struct + and save it in a local variable. Use variable in later test. + +2002-07-31 Kevin Buettner + + * mips-tdep.c (mips_find_abi_section): Add N64 ABI recognition + test. (Thanks to Daniel Jacobowitz.) + +2002-07-31 Kevin Buettner + + * mips-tdep.c (enum mips_abi): Add MIPS_ABI_N64. + (mips_abi_strings): Add "n64". + (mips_gdbarch_init): Add test for n64 abi. Add MIPS_ABI_N64 case. + +2002-07-31 Kevin Buettner + + * config/mips/tm-irix6.h (MIPS_REGSIZE): Define to be 8. + (REGISTER_VIRTUAL_TYPE): Some registers are now 64 bits wide. + +2002-07-31 Kevin Buettner + + * utils.c (host_pointer_to_address, address_to_host_pointer): + Use gdb_assert() instead of explicit call to internal_error(). + +2002-07-30 Kevin Buettner + + * Makefile.in (rs6000-nat.o): Update dependencies. + + From Nicholas Duffek: + * Makefile.in (ALLDEPFILES): Add aix-thread.c. + (aix-thread.o): New rule. + * configure.host (gdb_host): Set to aix432 on AIX 4.3.2+. + * config/powerpc/aix432.mh: New file. + +2002-07-30 Daniel Jacobowitz + + * ppc-linux-tdep.c (ELF_NGREG, ELF_NFPREG, ELF_NVRREG) + (ELF_FPREGSET_SIZE, ELF_GREGSET_SIZE): New enums. + (fetch_core_registers, ppc_linux_supply_gregset) + (ppc_linux_supply_fpregset): New functions. + (ppc_linux_regset_core_fns): New. + (_initialize_ppc_linux_tdep): Call add_core_fns. + * ppc-tdep.h: Add prototypes for ppc_linux_supply_fpregset + and ppc_linux_supply_gregset. + * ppc-linux-nat.c (supply_gregset): Call ppc_linux_supply_gregset. + (supply_fpregset): Call ppc_linux_supply_fpregset. + * config/powerpc/linux.mh (NATDEPFILES): Remove core-regset.o and + corelow.o. + * config/powerpc/linux.mt (TDEPFILES): Add corelow.o. + +2002-07-30 Daniel Jacobowitz + + * symtab.c (lookup_symbol): Demangle before lowercasing. + +2002-07-30 Andrew Cagney + + * symtab.h: Replace #include "gdb_obstack.h" with opaque + declaration. + * cli/cli-cmds.c, cli/cli-script.c: Include "gdb_string.h". + * gnu-v3-abi.c, arc-tdep.c, cli/cli-decode.c: Ditto. + * avr-tdep.c, mon960-rom.c, i960-tdep.c: Ditto. + * arch-utils.c, cli/cli-setshow.c: Unconditionally include + "gdb_string.h". + * Makefile.in (cli-script.o, cli-cmds.o): Update dependencies. + (gnu-v3-abi.o, cli-setshow.o, i960-tdep.o): Ditto. + (cli-decode.o, mi-cmd-var.o, mi-cmd-disas.o): Ditto. + (avr-tdep.o, mon960-rom.o): Ditto. + (aout_stabs_gnu_h): Define. + (symtab_h): Remove $(gdb_obstack_h). + +2002-07-30 Jim Blandy + + Patch from David Carlton : + * gdbinit.in: Move the `dir' commands that add GDB's own source + directory to the search path to the end, so that the `gdb' source + directory will be searched first. + +2002-07-29 Andrew Cagney + + * gdb_obstack.h: New file. + * symtab.h: Include "gdb_obstack.h" instead of "obstack.h". + (obstack_chunk_alloc, obstack_chunk_free): Delete macros. + * objfiles.h: Include "gdb_obstack.h". + * Makefile.in (gdb_obstack_h): Define. + (symtab_h): Add $(gdb_obstack_h). + (objfiles_h): Add $(gdb_obstack_h). + + * objfiles.c: Include "gdb_obstack.h" instead of "obstack.h". + * macrotab.c, cp-valprint.c, dbxread.c: Ditto. + * ch-typeprint.c, ch-valprint.c, dstread.c: Ditto. + * macroexp.c, p-typeprint.c, stabsread.c: Ditto. + * symtab.c, f-typeprint.c, mdebugread.c: Ditto. + * p-valprint.c, symmisc.c, typeprint.c: Ditto. + * symfile.c, coffread.c, c-typeprint.c: Ditto. + * buildsym.c, bcache.c, ada-typeprint.c: Ditto. + + * Makefile.in (bcache.o): Update dependencies. + (buildsym.o, c-typeprint.o, ch-typeprint.o): Ditto. + (ch-valprint.o, coffread.o, cp-valprint.o): Ditto. + (dbxread.o, dstread.o, f-typeprint.o): Ditto. + (objfiles.o, p-typeprint.o, p-valprint.o): Ditto. + (stabsread.o, symfile.o, symmisc.o): Ditto. + (symtab.o, typeprint.o, macroexp.o): Ditto. + (macrotab.o, mdebugread.o): Ditto. + (f_lang_h, coff_sym_h, coff_symconst_h): Define. + (coff_ecoff_h, aout_aout64_h): Define. + (aout_stabs_gnu_h, libaout_h): Define. + +2002-07-29 Andrew Cagney + + * regcache.c (struct regcache_descr): Rename nr_registers to + nr_cooked_registers. Revise comments describing the structure + member fields. + (init_regcache_descr): Update. + (init_legacy_regcache_descr): Update. + (read_register_gen, write_register_gen): When a cooked register in + the raw register range, directly access the value from the raw + register cache. + +2002-07-29 Andrew Cagney + + * z8k-tdep.c: Do not include "obstack.h". + * h8300-tdep.c, h8500-tdep.c: Ditto. + * m68hc11-tdep.c, sh-tdep.c: Ditto. + * valprint.c, v850-tdep.c: Ditto. + * d10v-tdep.c, mn10300-tdep.c: Ditto. + * mn10200-tdep.c: Ditto. + + * Makefile.in (z8k-tdep.o): Update dependencies. + (m68hc11-tdep.o, valprint.o): Ditto. + (v850-tdep.o, d10v-tdep.o): Ditto. + (mn10300-tdep.o, sparc-tdep.o): Ditto. + (sh-tdep.o, h8500-tdep.o, h8300-tdep.o): Ditto. + (m32r-tdep.o, mn10200-tdep.o): Specify dependencies. + (sh_opc_h, gdb_sim_sh_h): Define. + (elf_sh_h, elf_bfd_h): Define. + (opcode_m68hc11_h): Define. + (OPCODES_SRC, OPCODES_DIR): define. + (OPCODES): Use $(OPCODES_DIR). + (gdb_sim_d10v_h): Rename sim_d10v_h. + (gdb_sim_arm_h): Rename sim_arm_h. + +2002-07-26 Kevin Buettner + + * utils.c (host_pointer_to_address, address_to_host_pointer): + Change internal_error() message to indicate function responsible + for the error. + +2002-07-26 Kevin Buettner + + * ui-out.c (ui_out_field_core_addr): Remove unnecessary cast in + calls to local_hex_string_custom(). + +2002-07-26 Kevin Buettner + + * irix5-nat.c: Move IRIX shared library support from here... + * solib-irix.c: ...to here. Revised substantially to work with + generic solib framework. + + * osabi.h (gdb_osabi): Add new enum constant GDB_OSABI_IRIX. + * osabi.c (gdb_osabi_names): Add corresponding string for Irix. + * mips-irix-tdep.c: New file. + + * Makefile.in (ALLDEPFILES): Add mips-irix-tdep.c and solib-irix.c. + (mips-irix-tdep.o, solib-irix.o): New rules. + * config/mips/irix5.mt (TDEPFILES): Add mips-irix-tdep.o, solib.o, + solib-irix.o. + * config/mips/irix6.mt (TDEPFILES): Likewise. + * config/mips/irix6.mh (NATDEPFILES): Remove solib.o. + +2002-07-26 Kevin Buettner + + * aix-thread.c (coff/internal.h, bfd/libcoff.h, pthread.h): Remove + disabled (via ``#if 0'') includes. + +2002-07-26 Kevin Buettner + + * aix-thread.c (special_register_p, supply_sprs64, supply_sprs32) + (fetch_regs_user_thread, fetch_regs_kernel_thread, fill_sprs64) + (fill_sprs32, store_regs_user_thread, store_regs_kernel_thread): + Add support for the fpscr register. + * rs6000-nat.c (regmap, fetch_inferior_registers) + (store_inferior_registers, fetch_core_registers): Likewise. + +2002-07-26 Kevin Buettner + + * rs6000-nat.c (language.h): Include. + (special_regs): Delete this array. + (regmap): New function. + (fetch_register, store_register): Use regmap() to map gdb + register numbers to ptrace register numbers. Also, use + outputs from regmap() to make decisions regarding type of + ptrace() call to make. In particular, don't compare against + FIRST_UISA_SP_REGNUM or LAST_UISA_SP_REGNUM. + (fetch_inferior_registers, store_inferior_registers): Where + possible, obtain register numbers from tdep struct. Don't + refer to FIRST_UISA_SP_REGNUM or LAST_UISA_SP_REGNUM. + * config/rs6000/tm-rs6000.h (FIRST_UISA_SP_REGNUM) + (LAST_UISA_SP_REGNUM): Delete. + +2002-07-25 Kevin Buettner + + * rs6000-nat.c (ppc-tdep.h): Include. + (fetch_registers, store_register, fetch_core_registers): Don't + access registers[] directly. Instead, use supply_register() or + regcache_collect() as appropriate. + (find_toc_address): Format hex address with local_hex_string(). + +2002-07-25 Andrew Cagney + + * config/djgpp/fnchange.lst: Rename bfd/elf32-fr30.c and + bfd/elf32-frv.c. + +2002-07-24 Tom Tromey + + * jv-exp.y: Marked all strings with _(). + (ClassInstanceCreationExpression, ArrayCreationExpression): Use + internal_error. + (MethodInvocation, CastExpression, parse_number, yyerror, + java_type_from_name, push_expression_name, yylex): Typo fixes. + +2002-07-24 Daniel Jacobowitz + + * ui-file.c (struct tee_file, tee_file_new, tee_file_delete) + (tee_file_flush, tee_file_write, tee_file_fputs) + (tee_file_isatty): New. + * ui-file.h (tee_file_new): Add prototype. + +2002-07-24 Aidan Skinner + + * ada-lang.c: Change k&r style function definitions to prototyped + form. + * ada-typeprint.c: Change k&r style function definitions to prototyped + form. + * ada-valprint.c: Change k&r style function definitions to prototyped + form. + +2002-07-24 Andrew Cagney + + * README: Remove reference to remote-bug. + * Makefile.in (ALLDEPFILES): Remove m88k-nat.c, m88k-tdep.c and + remote-bug.c. + (m88k-nat.o): Delete rule. + (m88k-tdep.o): Delete rule. + (remote-bug.o): Delete rule. + * MAINTAINERS: Mark as obsolete. + * elfread.c (elf_symtab_read): Mention that m88k is obsolete. + * m88k-tdep.c: Make file obsolete. + * config/m88k/m88k.mh: Ditto. + * config/m88k/delta88v4.mh: Ditto. + * config/m88k/delta88v4.mt: Ditto. + * config/m88k/delta88.mt: Ditto. + * config/m88k/delta88.mh: Ditto. + * remote-bug.c: Ditto. + * config/m88k/tm-delta88.h: Ditto. + * config/m88k/nm-delta88v4.h: Ditto. + * config/m88k/xm-delta88.h: Ditto. + * config/m88k/xm-dgux.h: Ditto. + * config/m88k/tm-m88k.h: Ditto. + * config/m88k/nm-m88k.h: Ditto. + * config/m88k/tm-delta88v4.h: Ditto. + * m88k-nat.c: Ditto. + * cxux-nat.c: Ditto. + * configure.host: Make m88*-motorola-sysv4*, m88*-motorola-sysv* + and m88*-*-* obsolete. + * configure.tgt: Make m88*-motorola-sysv4*, m88*-motorola-* and + m88*-*-* obsolete. + +2002-07-24 Andrew Cagney + + * findvar.c (extract_unsigned_integer): Make `addr' parameter + constant. Same for local pointer variables. + (extract_signed_integer): Ditto. + * defs.h (extract_unsigned_integer): Update. + (extract_signed_integer): Update. + +2002-07-24 Andrew Cagney + + * regcache.c (regcache_raw_write): Change buf parameter to a + constant void pointer. + (regcache_raw_read): Change buf parameter to a void pointer. + (legacy_write_register_gen): Change myaddr parameter a constant + void pointer. + (supply_register): Change val parameter to a const void pointer. + * regcache.h (regcache_raw_write): Update declaration. + (regcache_raw_read): Update declaration. + (supply_register): Update declaration. + +2002-07-24 Tom Tromey + + * defs.h (gdb_readline_wrapper): Declare. + * utils.c (prompt_for_continue): Use gdb_readline_wrapper. + * tracepoint.c (read_actions): Use gdb_readline_wrapper. + * top.c (gdb_readline_wrapper): New function. + (command_line_input): Use it. + +2002-07-24 Andrew Cagney + + * regcache.h (regcache_raw_read, regcache_raw_write): Replace + regcache_read and regcache_write. + (regcache_raw_read_as_address): Replace regcache_read_as_address. + * regcache.c: Update. + * sh-tdep.c (sh64_push_arguments): Update comment. + (sh_pseudo_register_read): Update. + (sh_pseudo_register_write): Update. + (sh4_register_read): Update. + (sh4_register_write): Update. + (sh64_pseudo_register_read): Update. + (sh64_pseudo_register_write): Update. + (sh64_register_read): Update. + (sh64_register_write): Update. + * i386-tdep.c (i386_extract_return_value): Update. + (i386_extract_struct_value_address): Update. + (i386_extract_return_value): Update. + * blockframe.c (generic_read_register_dummy): Update. + (generic_call_dummy_register_unwind): Update + * infrun.c (write_inferior_status_register): Update. + +2002-07-23 Jim Blandy + + * parser-defs.h (expression_context_pc): Make this extern. + (Thanks to Michael Snyder.) + +2002-07-23 Andrew Cagney + + GDB 5.2.1 released from 5.2 branch. + * NEWS: Mention changes in 5.2.1 including addition of AVR target. + * README: Update to mention 5.2.1. + +2002-07-23 Mark Salter + + * remote.c (remote_read_bytes): Fix check for error. + +2002-07-22 Kevin Buettner + + * aix-thread.c (language.h): Include. + (ptrace_check, pdc_symbol_addrs, pdc_read_regs, pdc_write_regs) + (pdc_read_data, pdc_write_data, pdc_alloc, pdc_realloc, pdc_dealloc): + Print newlines at end of debug messages. + (pdc_symbol_addrs, pdc_read_regs, pdc_write_regs, pdc_read_data) + (pdc_write_data): Use local_hex_string() instead of %llx formats. + +2002-07-22 Kevin Buettner + + * aix-thread.c (ppc-tdep.h): Include. + (special_register_p): New function. + (supply_sprs64, supply_sprs32, fill_sprs64, fill_sprs32) + (store_regs_user_thread): Use register number information from + gdbarch_tdep struct instead of hardcoded offsets relative to + FIRST_UISA_SP_REGNUM. + (fetch_regs_kernel_thread, store_regs_kernel_thread): Call + special_register_p() instead of using FPLAST_REGNUM and + LAST_UISA_SP_REGNUM as lower and upper bounds on the special + register numbers. Also, don't assume that LAST_UISA_SP_REGNUM + will be MQ's register number. + +2002-07-22 Michael Snyder + + * aix-thread.c (ops): Rename to aix_thread_ops. + (base_ops): Rename to base_target. + (ops_attach): Rename to aix_thread_attach. + (ops_detach): Rename to aix_thread_detach. + (ops_resume): Rename to aix_thread_detach. + (ops_wait): Rename to aix_thread_wait. + (ops_kill): Rename to aix_thread_kill. + (init_ops): Rename to init_aix_thread_ops. + (ops_fetch_register): Rename to aix_thread_fetch_register. + (ops_store_register): Rename to aix_thread_store_register. + (ops_mourn_inferior): Rename to aix_thread_mourn_inferior. + (ops_thread_alive): Rename to aix_thread_thread_alive. + (ops_extra_thread_info: Rename to aix_thread_extra_thread_info. + (ops_pid_to_str): Rename to aix_thread_pid_to_str. + (ops_xfer_memory): Rename to aix_thread_xfer_memory. + (fetch_regs_lib): Rename to fetch_regs_user_thread. + (fetch_regs_kern): Rename to fetch_regs_kernel_thread. + (store_regs_lib): Rename to store_regs_user_thread. + (store_regs_kern): Rename to store_regs_kernel_thread. + +2002-07-22 Michael Snyder + + * aix-thread.c (ops_prepare_to_store): Eliminate. + (init_ops): Don't initialize ops.prepare_to_store. + (store_regs_kern): Pre-fetch register buffers from child, + because some registers may not be in the cache. Copy + regs from register cache only if they are cached. + (store_regs_lib): Copy regs from register cache only + if they are cached. + (fill_sprs32, (fill_sprs64, fill_fprs, fill_gprs32, + fill_gprs64): Ditto. + +2002-07-22 Kevin Buettner + + * aix-thread.c (gdb_assert.h): Include. + (fill_sprs64, fill_sprs32): Add selected asserts to make sure that + register sizes (from register cache) match size of buffer holding + register data. + (fill_sprs32): Change parameter types to match those in the ptrace() + buffer. + (store_regs_lib): Likewise, but for 32-bit temporary variables. + (ops_prepare_to_store): Rename loop variable ``i'' to ``regno''. + +2002-07-22 Michael Snyder + + * aix-thread.c (supply_sprs64): Cosmetic change. + (supply_sprs32): Cosmetic change. + (fill_gprs64, fill_gprs32, fill_fprs, fill_sprs32): New funcs. + (fill_sprs64): Use regcache_collect instead of read_register. + (store_regs_lib): Use regcache_collect instead of + read_register. Use fill_sprs32 instead of fill_sprs64, + if debugging a 32-bit architecture. + (store_regs_kern): Use fill_gprs64 etc. to pull the values + out of the register cache, instead of passing a pointer into + the register cache directly to ptrace. Use regcache_collect + insteaad of read_register. + (ops_prepare_to_store): Use target_read_registers instead + of read_register_bytes. + +2002-07-20 Aidan Skinner + + * MAINTAINERS: Add self under write after approval. + +2002-07-20 Aidan Skinner + + * ada-tasks.c: Change k&r style function definitions to prototyped + form. + +2002-07-19 Andrew Cagney + + * Makefile.in (x86-64-tdep.o): Add $(objfiles_h). + * x86-64-tdep.c: Include "objfiles.h". + (x86_64_gdbarch_init): Set in_solib_call_trampoline to + in_plt_section. From 2002-07-18 Michal Ludvig . + +2002-07-17 Michal Ludvig + + * dwarf2cfi.c (execute_stack_op): Complain on unknown DW_OP_ value. + (update_context): Initialise cfa variable. + +2002-07-17 Michael Snyder + + * aix-thread.c: Shorten some long lines. + Bring comments into line with code spec. + +2002-07-18 Joel Brobecker + + * infrun.c: Re-indent using gdb_indent.sh. + +2002-07-18 Joel Brobecker + + * infrun.c (handle_inferior_event): Remove unneeded extra brace. + Leave the indentation temporarily untouched, to minimize the diffs. + +2002-07-18 Elena Zannoni + + * stabsread.c: Make os9k sections of the code obsolete, + for real this time. + * stabsread.h: Make os9k sections of the code obsolete. + +2002-07-18 Michal Ludvig + + * linux-low.c (regsets_store_inferior_registers): Add free() + at the end of a loop to prevent memory leak. + * linux-x86-64-low.c (x86_64_regmap): Add CS, SS registers. + (X86_64_NUM_GREGS): Count it from the size of x86_64_regmap. + * config/sparc/tm-sp64linux.h: Make the rest of #endif + line a comment. + * Makefile.in (x86-64-linux-nat.o): Remove dependency on i387-tdep.h + +2002-07-17 Jim Blandy + + * macrocmd.c (info_macro_command): Remove newline from error + message. + +2002-07-17 J"orn Rennecke + + * sh-tdep.c (sh_dsp_register_sim_regno): New function. + (sh_gdbarch_init): Use it for sh-dsp. + +2002-07-16 Kevin Buettner + + * dwarf2read.c (read_initial_length): Handle older, non-standard, + 64-bit DWARF2 format. + +2002-07-16 Joel Brobecker + + * proc-api.c: use HAVE_SYS_PROC_H macro to avoid including + when not available. + +2002-07-16 Andrew Cagney + + * NEWS: Mention that the i[34]86-*-os9k has been made obsolete. + * stabsread.c: Make os9k sections of the code obsolete. + * configure.tgt: Make i[3456]86-*-os9k target obsolete. + * config/i386/i386os9k.mt: Make file obsolete. + * Makefile.in (ALLDEPFILES): Remove remote-os9k.c. + (COMMON_OBS): Remove os9kread.o + (SFILES): Remove os9kread.c. + (os9kread.o, remote-os9k.o): Make target obsolete. + * remote-os9k.c: Make file obsolete. + * os9kread.c: Make file obsolete. + * Makefile.in + +2002-07-16 Andrew Cagney + + * NEWS: Mention that the FR30 has been made obsolete. + * fr30-tdep.c: Make file obsolete. + * config/fr30/tm-fr30.h: Ditto. + * config/fr30/fr30.mt: Ditto. + * configure.tgt: Make fr30-*-elf obsolete. + * MAINTAINERS: Make fr30-elf obsolete. + +2002-07-16 Pierre Muller + + * blockframe.c (get_pc_function_start): return 0 if the minimal symbol + found is not inside a section. + +2002-07-15 Kevin Buettner + + * aix-thread.c (ptrace_check): Use safe_strerror() instead of + strerror(). + (pdc_realloc): Use xrealloc() instead of realloc(). + +2002-07-15 Kevin Buettner + + * aix-thread.c (PD_ERROR, CALL_BASE): Delete. + (ops_resume, ops_wait, fetch_regs_lib, store_regs_lib) + (ops_xfer_memory, ops_kill): Don't use PD_ERROR or CALL_BASE + macros. + +2002-07-15 Kevin Buettner + + * aix-thread.c (ptrace_check): Eliminate goto. + (sync_threadlists): Eliminate gotos. Also, fix array overrun + problem. + +2002-07-15 Kevin Buettner + + * aix-thread.c (gdbcmd.h): Include. + (DEBUG, DBG, DBG2, dbg): Eliminate. + (debug_aix_thread): New static global. + (ptrace_check, pdc_symbol_addrs, pdc_read_regs, pdc_write_regs) + (pdc_read_data, pdc_write_data, pdc_alloc, pdc_realloc, pdc_dealloc) + (fetch_regs_lib, store_regs_lib, store_regs_kern): Rewrite + invocations to DBG and DBG2 macros to test against + ``debug_aix_thread'' and call fprintf_unfiltered(). + (_initialize_aix_thread): Add new command "set debug aix-thread". + +2002-07-15 Andrew Cagney + + From Gerhard Tonn : + * s390-nat.c (fill_fpregset, fill_gregset): Use regcache_collect + instead of supply_register. + +2002-07-15 Andrew Cagney + + * dwarf2cfi.c: Include "gdb_assert.h". + (frame_state_for): Use gdb_assert to check that fde->cie_ptr is + non-NULL. + (update_context): Do not use __func__. Add missing ``break''. + (update_context): Do not use __func__. + +2002-07-15 Elena Zannoni + + * rs6000-tdep.c (rs6000_gdbarch_init): Remove variable print_insn + and its setting. Set gdbarch instruction printing functions + directly. For non-rs6000 case use new function + gdb_print_insn_powerpc. + (gdb_print_insn_powerpc): New function. + +2002-07-13 Andrew Cagney + + * NEWS: Mention that the d30v has been marked obsolete. + * MAINTAINERS: Note that d30v / d30v-elf has been made obsolete. + * configure.tgt: Mark d30v-*-* as obsolete. + * d30v-tdep.c: Mark file as obsolete. + * config/d30v/d30v.mt: Ditto. + * config/d30v/tm-d30v.h: Ditto. + +2002-07-13 Aidan Skinner + + * ada-tasks.c (add_task_entry): replace calls to + malloc() with xmalloc + * ada-tasks.c (init_task_list): replace calls to free with xfree() + + * ada-lang.c (replace_operator_with_call, fill_in_ada_prototype, + ada_finish_decode_line_1, all_sals_for_line + ada_breakpoint_rewrite): replace calls to free() with xfree() + +2002-07-12 Kevin Buettner + + From Nicholas Duffek (with minor changes by Martin Hunt, + Louis Hamilton, and Kevin Buettner): + * aix-thread.c: New file. + +2002-07-12 Petr Sorfa + + * dwarf2read.c (dwarf2_invalid_attrib_class): New + complaint for invalid attribute class or form. + (read_func_scope): DW_AT_frame_base + better handling of DW_AT_block*. + (dwarf2_add_member_fn): DW_AT_vtable_elem_location + better handling of DW_AT_block*. + (read_common_block): DW_AT_location + better handling of DW_AT_block*. + (read_partial_die): DW_AT_location better handling + of DW_AT_block*. + (new_symbol): DW_AT_external better handling of + DW_AT_block*. Proper initialization of variable + "addr". + (attr_form_is_block): New function that returns true + if the attribute's form is of DW_FORM_block*. + +2002-07-12 Peter Schauer + + * valops.c (find_method_list): Remove comment about + removed STATIC_MEMFUNCP argument. + (value_find_oload_method_list): Likewise. + +2002-07-12 Kevin Buettner + + From Nicholas Duffek: + * rs6000-nat.c (vmap_ldinfo, xcoff_relocate_core): Call + target_new_objfile_hook. + +2002-07-12 Kevin Buettner + + From Nicholas Duffek: + * xcoffread.c (scan_xcoff_symtab): Recognize XMC_TD as a data storage + csect. + +2002-07-12 Andrew Cagney + + * MAINTAINERS: Mention --enable-sim-build-warnings. + (m68hc11-elf): Disable sim build warnings. + (m32r-elf): Mark as broken obsolete candidate. + (x86_64-linux-gnu): Mark as buildable with -Werror. + (arm-elf): Change -w to ``,'' which enables warnings but not + -Werror. + +2002-07-12 Andrew Cagney + + * bcache.h: Update copyright. + (struct bstring, struct bcache): Move definition to "bcache.c". + Replaced by opaque declaration. + (bcache_xfree): Replace free_bcache. + (bcache_xmalloc, bcache_memory_used): Declare. + + * bcache.c: Update copyright. + (struct bstring, struct bcache): Moved to here from "bcache.h". + Update comments. + (bcache_xmalloc, bcache_memory_used): New functions. + (bcache_xfree): Replace function free_bcache. + + * Makefile.in (objfiles.o): Add $(bcache_h). + (objfiles_h): Remove $(bcache_h). + (symfile.o): Add $(bcache_h). + + * symmisc.c: Update copyright. + (print_symbol_bcache_statistics): Pass psymbol_cache by value. + (print_objfile_statistics): Use bcache_memory_used. + + * symfile.c: Include "bcache.h". + (reread_symbols): Use bcache_xfree. + (reread_symbols): Use bcache_xmalloc and bcache_xfree. + (add_psymbol_to_list): Pass psymbol_cache by value. + (add_psymbol_with_dem_name_to_list): Ditto. + + * objfiles.h: Update copyright. + (struct bcache): Declare opaque. Do not include "bcache.h". + (struct objfile): Change psymbol_cache and macro_cache to ``struct + bcache'' pointers. + * dwarf2read.c (macro_start_file): Pass macro_cache by value. + + * objfiles.c: Include "bcache.h". Update copyright. + (allocate_objfile): Use bcache_xmalloc to create psymbol_cache and + macro_cache. + (free_objfile): Use bcache_xfree. + +2002-07-11 Grace Sainsbury + + * monitor.c (monitor_fetch_register): Make name a constant. + (monitor_store_register): Same. + +2002-07-11 Daniel Jacobowitz + + Based on patch from Daniel Berlin . + * buildsym.c: Include "demangle.h" for SYMBOL_INIT_DEMANGLED_NAME. + (finish_block) For non-function blocks, hash the symbol table. For + function blocks, mark the symbol table as unhashed. + * minsyms.c (msymbol_hash): Return hash value without taking modulus. + (msymbol_hash_iw): Likewise. + (add_minsym_to_hash_table): Take modulus of msymbol_hash's return + value. + (add_minsym_to_demangled_hash_table): Likewise for msymbol_hash_iw. + (lookup_minimal_symbol): Likewise for both. + * symtab.h (struct block): Add `hashtable' flag. Comment the + hashtable. + (BLOCK_HASHTABLE, BLOCK_BUCKETS, BLOCK_BUCKET): New macro. + (ALL_BLOCK_SYMBOLS): Update. + (BLOCK_SHOULD_SORT): Do not sort hashed blocks. + (struct symbol): Add `hash_next' pointer. + * symtab.c (lookup_block_symbol): Search using the hash table when + possible. + (find_pc_sect_symtab): Use ALL_BLOCK_SYMBOLS. + (search_symbols, find_addr_symbol): Likewise. + + * dstread.c (process_dst_block): Clear hashtable bit for new block. + (read_dst_symtab): Likewise. + * jv-lang.c (get_java_class_symtab): Likewise. + * mdebugread.c: Include "gdb_assert.h". + (shrink_block): Assert that the block being modified is not hashed. + * coffread.c (patch_opaque_types): Use ALL_BLOCK_SYMBOLS. + * symmisc.c (free_symtab_block): Walk the hash table when freeing + symbols. + (dump_symtab): Recognize hashed blocks. + * printcmd.c (print_frame_args): Assert that function blocks do not + have hashed symbol tables. + * ada-lang.c (symtab_for_sym): Use ALL_BLOCK_SYMBOLS. + (fill_in_ada_prototype, debug_print_block): Likewise. + (ada_add_block_symbols): Use ALL_BLOCK_SYMBOLS. Handle hash tables. + +2002-07-11 Corinna Vinschen + + * stack.c (print_frame): Use result of frame_address_in_block() + instead of fi->pc when evaluating symbols. + (backtrace_command_1): Ditto. + +2002-07-11 Andrew Cagney + + * cris-tdep.c (cris_saved_pc_after_call): Fix parameter type. + Make static. + + * arm-tdep.c (arm_register_name): Make return type constant. + +2002-07-10 Andrew Cagney + + * win32-nat.c (has_detach_ability): Convert to strict ISO C + prototype. + * top.c (gdb_rl_operate_and_get_next_completion): Ditto. + * s390-tdep.c (s390_fp_regnum): Ditto. + (s390_read_fp): Ditto. + (s390_pop_frame): Ditto. + (_initialize_s390_tdep): Ditto. + * remote.c (get_remote_state): Ditto. + * procfs.c (mappingflags): Ditto. + * memattr.c (_initialize_mem): Ditto. + * mcore-tdep.c (mcore_pop_frame): Ditto. + * m68klinux-nat.c (_initialize_m68k_linux_nat): Ditto. + * m68k-tdep.c (m68k_register_bytes_ok): Ditto. + * language.c (set_case_str): Ditto. + * gnu-v3-abi.c (vtable_address_point_offset): Ditto. + * frv-tdep.c (new_variant): Ditto. + (frv_stopped_data_address): Ditto. + * dwarf2cfi.c (fde_chunks_need_space): Ditto. + (context_alloc): Ditto. + (frame_state_alloc): Ditto. + (unwind_tmp_obstack_init): Ditto. + (unwind_tmp_obstack_free): Ditto. + (cfi_read_fp): Ditto. + * cris-tdep.c (cris_saved_pc_after_call): Ditto. + (cris_pop_frame): Ditto. + * c-lang.c (scanning_macro_expansion): Ditto. + (finished_macro_expansion): Ditto. + (c_preprocess_and_parse): Ditto. + * gdbarch.sh: Ditto. + * gdbarch.h, gdbarch.c: Regenerate. + * config/mn10200/tm-mn10200.h: Adjust indentation. + * target.c: Adjust indentation. + * symtab.h: Adjust indentation. + * stabsread.h: Adjust indentation. + * remote-es.c: Adjust indentation. + * os9kread.c: Adjust indentation. + +2002-07-10 Andrew Cagney + + * wince.c (_initialize_wince): Rename _initialize_inftarg. + * win32-nat.c (_initialize_win32_nat): Rename _initialize_inftarg. + +2002-07-10 Grace Sainsbury + + * NEWS: Mention m68k, mcore multi-arching. + * MAINTAINERS: Change status of m68k, mcore to reflect + multi-arching. + +2002-07-10 Daniel Jacobowitz + + * valops.c (find_overload_match): Free oload_syms. + +2002-07-09 Joel Brobecker + + Define HAVE_SYS_PROC_H if sys/proc.h exists + * configure.in: Add check for sys/proc.h + * config.in: Regenerate. + * configure: Regenerate. + +2002-07-09 Grace Sainsbury + + * config/m68k/tm-m68k.h: Remove macros wrapped in + #if !GDB_MULTI_ARCH. + +2002-07-08 Andrew Cagney + + * config.in, configure: Regenerate. + +2002-07-08 Mark Kettenis + + * dwarf2cfi.c: Include "gcore.h". + (execute_stack_op): Fix implementation of the + DW_OP_deref and DW_OP_deref_size operators by letting do their + lookup in the target. + +2002-07-07 Mark Kettenis + + From Peter Schauer : + * i386-sol2-tdep.c (i386_sol2_init_abi): Correct value for + tdep->sc_sp_offset. + +2002-07-05 Daniel Jacobowitz + + Fix PR gdb/595, gdb/602 + * gnu-v3-abi.c (gnuv3_baseclass_offset): Remove unused variables. + Don't call value_cast, just read the vtable pointer; update comments + to match. + +2002-07-05 Grace Sainsbury + + * config/mcore/tm-mcore.h: Remove file. + * config/mcore/mcore.mt: Remove definition of TM_FILE + * configure.tgt: Set gdb_multi_arch to yes for the mcore target. + +2002-07-05 Mark Kettenis + + * i386bsd-tdep.c: Include "gdb_string.h". + +2002-07-04 Grace Sainsbury + + * config/mcore/tm-mcore.h (GDB_MULTI_ARCH): Set to 2. + (PR_REGNUM, FIRST_ARGREG, LAST_ARGREG,RETVAL_REGNUM): Move to + mcore-tdep. + (REG_STRUCT_HAS_ADDR, USE_STRUCT_CONVENTION, GET_SAVED_REGISTER) + (TARGET_VIRTUAL_FRAME_POINTER, BELIEVE_PCC_PROMOTION): Remove. + * mcore-tdep.c (PR_REGNUM, FIRST_ARGREG, LAST_ARGREG) + (RETVAL_REGNUM): Move macros from tm-mcore.h + (mcore_reg_struct_has_addr): New function. + (mcore_gdbarch_init): Added initializations for the macros removed + from tm-mcore.h. + +2002-07-04 Mark Kettenis + + * osabi.c (generic_elf_osabi_sniffer): Add check for FreeBSD 3.x's + traditonal string branding within the ELF header. + +2002-07-04 Daniel Jacobowitz + + * symtab.c (remove_params): New function. + (make_symbol_overload_list): Use it instead of cplus_demangle. + (overload_list_add_symbol): Likewise. Reorder. Fix memory leak. + +2002-07-04 Mark Kettenis + + * i386obsd-nat.c (_initialize_i386obsd_nat): Fix typo in prototype. + + * i386bsd-tdep.c (i386nbsd_sigtramp_start, i386nbsd_sigtramp_end): + New variables. + (i386nbsd_init_abi): Use these to initialize tdep->sigtramp_start + and tdep->sigtramp_end. + * i386obsd-nat.c: New file. + * config/i386/obsd.mh (NATDEPFILES): Add i386obsd-nat.o. + + * dwarf2cfi.c (cfi_pop_frame): Use alloca() for regbuf. + Don't call get_current_frame(). + +2002-07-04 Pierre Muller + + * i386-nat.c (child_post_startup_inferior): New function + calling i386_cleanup_dregs if + I386_USE_GENERIC_WATCHPOINTS is defined. + * config/i386/nm-i386.h: define CHILD_POST_STARTUP_INFERIOR + conditional to acknowledge that i386-nat.c has its + own child_post_startup_inferior function. + +2002-07-04 Mark Kettenis + + * i386-tdep.h (I386_MAX_REGISTER_SIZE): New define. + * i386-tdep.c (i386_do_pop_frame): Use I386_MAX_REGISTER_SIZE + instead of MAX_REGISTER_RAW_SIZE. + (i386_extract_return_value, i386_extract_struct_value_address): + Convert to use regcache. + (i386_gdbarch_init): Set max_register_raw_size and + max_register_virtual_size to I386_MAX_REGISTER_SIZE. + Set extract_return_value and extract_struct_value_address instead + of their deprecated variants. + + Convert i386 target to generic dummy frames. + * i386-tdep.c: Include "symfile.h". + (i386_frameless_signal_p): Consider a function to be frameless if + the pc points at the first instruction of the function. + (i386_frame_chain): Handle (generic) call dummies. + (i386_frame_saved_pc): Likewise. + (i386_frame_init_saved_regs): Remove code dealing with call + dummies on the stack. + (i386_push_dummy_frame): Removed. + (i386_call_dummy_words): Removed. + (i386_fix_call_dummy): Removed. + (i386_push_return_address): New function. + (i386_do_pop_frame): Renamed from i386_pop_frame. Add FRAME + parameter, and don't call get_current_frame. + (i386_pop_frame): New function. + (i386_gdbarch_init): Set use_generic_dummy_frames to 1, set + call_dummy_location to AT_ENTRY_POINT, set call_dummy_address to + entry_point_address, set call_dummy_breakpoint_offset to 0, set + call_dummy_length to 0, set call_dummy_words to NULL, set + sizeof_call_dummy_words to 0, set fix_call_dummy to + generic_fix_call_dummy, set pc_in_call_dummy to + pc_in_call_dummy_at_entry_point, set push_dummy_frame to + generic_push_dummy_frame, set push_return_address to + i386_push_return_address and set frame_chain_valid to + generic_file_frame_chain_valid. + +2002-07-03 Andrew Cagney + + * gdbarch.sh (struct regcache): Add opaque declaration. + (EXTRACT_RETURN_VALUE): New architecture method. + (EXTRACT_STRUCT_VALUE_ADDRESS): Ditto. + * gdbarch.h, gdbarch.c: Regenerate. + * arch-utils.c (legacy_extract_return_value): New function. + * arch-utils.h (legacy_extract_return_value): Declare. + * values.c (value_being_returned): Re-enable code handling + EXTRACT_STRUCT_VALUE_ADDRESS. Move + deprecated_grub_regcache_for_registers call to block handling + DEPRECATED_EXTRACT_STRUCT_VALUE_ADDRESS. + (EXTRACT_RETURN_VALUE): Do not define. + +2002-07-03 Grace Sainsbury + + * config/mcore/tm-mcore.h (REGISTER_BYTES, NUM_REGS, PC_REGNUM) + (SP_REGNUM, FP_REGNUM, FUNCTION_START_OFFSET, DECR_PC_AFTER_BREAK) + (BREAKPOINT_FROM_PC, INNER_THAN, SAVED_PC_AFTER_CALL) + (INIT_EXTRA_FRAME_INFO, FRAME_INIT_SAVED_REGS, INIT_FRAME_PC) + (FRAME_CHAIN, FRAME_CHAIN_VALID, FRAME_SAVED_PC) + (STORE_RETURN_VALUE, DEPRECATED_EXTRACT_RETURN_VALUE) + (STORE_STRUCT_RETURN, DEPRECATED_EXTRACT_STRUCT_VALUE_ADDRESS) + (SKIP_PROLOGUE, FRAME_ARGS_SKIP, FRAME_ARGS_ADDRESS) + (FRAME_LOCALS_ADDRESS, FRAME_NUM_ARGS, POP_FRAME) + (PUSH_RETURN_ADDRESS, PUSH_DUMMY_FRAME, PUSH_ARGUMENTS): Remove. + * mcore-tdep.c (mcore_init_extra_frame_info): Add fromleaf + argument so the function fits the prototype in the architecture + vector. + (mcore_pop_frame): Remove argument so the function fits the + prototype. Use get_current_frame instead of the argument. + (mcore_push_arguments): Change type of struct_return so the + function can be used in the architecture vector. + (mcore_store_struct_return): Add. + (mcore_frame_init_saved_regs): Add. + (mcore_gdbarch_init): Add function calls to replace the macros + removed from tm-mcore.h + +2002-07-03 Andrew Cagney + + * infcmd.c (print_return_value): Remove compatibility code calling + deprecated_grub_regcache_for_registers. + + * values.c: Include "regcache.h". + (value_being_returned): Update. Use + deprecated_grub_regcache_for_registers to extract the register + buffer address. + * value.h (value_being_returned): Change ``retbuf'' parameter to a + ``struct regcache''. + * Makefile.in (values.o): Add dependency on $(regcache_h). + + * inferior.h (run_stack_dummy): Change type of second parameter to + a ``struct regcache''. + * valops.c (hand_function_call): Change type of retbuf to ``struct + regcache''. Allocate using regcache_xmalloc, clean using + make_cleanup_regcache_xfree. + * infcmd.c (run_stack_dummy): Update. Use + regcache_cpu_no_passthrough instead of memcpy to copy the buffer. + + * regcache.c (do_regcache_xfree): New function. + (make_cleanup_regcache_xfree): New function. + * regcache.h (make_cleanup_regcache_xfree): Declare. + +2002-07-03 Martin M. Hunt + + * event-top.c (command_line_handler): Don't read past + beginning of buffer. + +2002-07-03 Martin M. Hunt + + * varobj.c (struct varobj_root): Change frame from CORE_ADDR to + struct frame_id. + (varobj_create): Store frame_id for root. + (varobj_gen_name): Use xasprintf. + (varobj_update): Save and restore frame using get_frame_id() and + frame_find_by_id(). + (create_child): Use xasprintf. + (new_root_variable): Initialize frame_id. + (c_name_of_child): Use xasprintf. Call find_frame_by_id(). + (c_value_of_variable): Use xasprintf. Move mem_fileopen call + to prevent memory leak. + +2002-07-03 Andrew Cagney + + * valops.c (hand_function_call): Move declaration of retbuf to + start of function, allocate using malloc, add a cleanup but before + the inf_status cleanup, cleanup the buffer. Rename local variable + old_chain to inf_status_cleanup. + +2002-07-03 Martin M. Hunt + + * top.c (execute_command): Use cmd_func() and cmd_func_p(). + + * cli/cli-decode.c (cmd_func_p): New function. + (cmd_func): New function. + + * command.h: Add cmd_func() and cmd_func_p(). + +2002-07-03 Grace Sainsbury + + * config/mcore/tm-mcore.h (GDB_MULTI_ARCH): Add macro. Set to 0. + (REGISTER_SIZE): Remove. + (MAX_REGISTER_RAW_SIZE): Remove. + (REGISTER_VIRTUAL_TYPE): Remove. + (MAX_REGISTER_VIRTUAL_SIZE): Remove. + (REGISTER_NAME): Remove. + (USE_GENERIC_DUMMY_FRAMES): Remove. + (CALL_DUMMY): Remove. + (CALL_DUMMY_START_OFFSET): Remove. + (CALL_DUMMY_BREAKPOINT_OFFSET): Remove. + (CALL_DUMMY_LOCATION): Remove. + (FIX_CALL_DUMMY): Remove. + (CALL_DUMMY_ADDRESS): Remove. + (SIZEOF_CALL_DUMMY_WORDS): Remove. + (SAVE_DUMMY_FRAME_TOS): Remove. + * mcore-tdep.c (MCORE_REG_SIZE, MCORE_NUM_REGS): Add macros. + (mcore_register_virtual_type): New function. + (mcore_register_byte): New function. + (mcore_register_size): New function. + (mcore_register_name): New function. + (mcore_gdbarch_init): New function. Add set_gdbarch calls for + macros removed from tm-mcore.h. + (mcore_dump_tdep): Add. + (_initialize_mcore_tdep): Add gdbarch_register call. + +2002-07-03 Mark Kettenis + + * i386-tdep.c (i386_frameless_signal_p): Provide an argument in to + frameless_look_for_prologue, such that we actually call this + function. + +2002-07-02 Joel Brobecker + + * frame.h (frame_address_in_block): New function. + + * blockframe.c (frame_address_in_block): New function extracted + from get_frame_block(). + (get_frame_block): Use frame_address_in_block(). + (block_innermost_frame): Use frame_address_in_block() to match + the frame pc address against the block boundaries rather than + the frame pc directly. This prevents a failure when a frame pc + is actually a return-address pointing immediately after the end + of the given block. + +2002-07-02 Grace Sainsbury + + * MAINTAINERS: Add self under write after approval. + +2002-07-02 Grace Sainsbury + + * m68k-tdep.c (m68k_remote_breakpoint_from_pc): Add. Currently not + used in architecture vector. The default is + m68k_local_breakpoint_from_pc. + (m68k_local_breakpoint_from_pc): Add. + (enum): Add register numbers from tm-m68k.h. + (m68k_gdbarch_init): Add breakpoint_from_pc to architecture + vector. + * config/m68k/tm-m68k.h (GDB_MULTI_ARCH): Set to + GDB_MULTI_ARCH_PARTIAL. + (BPT_VECTOR, REGISTER_BYTES_FP, REGISTER_BYTES_NOFP) + (NUM_FREGS, SIG_PC_FP_OFFSET, SP_ARG0, REMOTE_BPT_VECTOR): Move to + m68k-tdep.c. + (BREAKPOINT, REMOTE_BREAKPOINT): Remove. + (A1_REGNUM, FP0_REGNUM, FPC_REGNUM, FPS_REGNUM, FPI_REGNUM): Move + to enum in m68k-tdep.c + +2002-07-02 Joel Brobecker + + * solib-osf.c (open_map): Compute the list of shared libraries + loaded by the inferior, rather than the list of libraries loaded + by GDB itself. Otherwise, GDB ends up reading the symbols from + the wrong shared libraries... + +2002-07-02 Mark Kettenis + + * i386-linux-tdep.c (i386_linux_sigcontext_addr): Make static. + (LINUX_SIGCONTEXT_PC_OFFSET, LINUX_SIGCONEXT_SP_OFFSET): Remove + macros. + (i386_linux_sigtramp_saved_pc, i386_linux_sigtramp_saved_sp): + Remove functions. + (FRAMELESS_SIGNAL): Remove function. + (i386_linux_frame_chain, i386_linux_frame_saved_pc, + i386_linux_saved_pc_after_call): Removed. + (i386_linux_init_abi): Initialize tdep->sigcontext_addr, + tdep->sc_pc_offset and tdep->sc_sp_offset. Don't override + frame_chain, frame_saved_pc and saved_pc_after_call any longer. + + * i386-tdep.c (i386_frameless_signal_p): New function. + (i386_frame_chain): Deal with frameless signals. + (i386_sigtramp_saved_sp): New function. + (i386_frame_saved_pc): Deal with frameless signals. + (i386_saved_pc_after_call): Make sure the correct value is + returned just after entry into a sigtramp. + * i386bsd-tdep.c (i386bsd_sc_sp_offset, i386nbsd_sc_sp_offset, + i386fbsd4_sc_sp_offset): New variables. + (i386bsd_init_abi, i386nbsd_init_abi, i386fbsd4_init_abi): Use + these variables to initialize tdep->sc_sp_offset. * i386bsd-nat.c + (_initialize_i386bsd_nat): Add sanity check for sc_sp_offset + similiar to what we already did for sc_pc_offset. + * i386-sol2-tdep.c (i386_sol2_init_abi): Initialize + tdep->sc_sp_offset. + + * i386nbsd-tdep.c (fetch_elfcore_registers): Wrap long line. + +2002-07-02 Michal Ludvig + + * config/i386/tm-x86-64linux.h: New. + * config/i386/x86-64linux.mt: Add GDB_MULTI_ARCH and TM_FILE + definitions. + * config/i386/nm-x86-64.h: Rename to ... + * config/i386/nm-x86-64linux.h: ... this one. + * config/i386/x86-64linux.mh: Reflect the above change. + +2002-07-01 Mark Kettenis + + * i386-tdep.h (struct gdbarch_tdep): Replace sigtramp_saved_pc + with sigcontext_addr. Add sc_sp_offset. + (i386bsd_sigtramp_saved_pc): Remove prototype. + (i386bsd_sicontext_addr): Add prototype. + * i386-tdep.c (i386_sigtramp_saved_pc): New function. + (i386_frame_saved_pc): Rewrite to call i386_sigtramp_saved_pc. + (i386_svr4_sigtramp_saved_pc): Removed. + (i386_svr4_sigcontext_addr): New function. + (i386_svr4_init_abi): Don't initialize tdep->sigtramp_saved_pc. + Initialize tdep->sigcontext_addr instead. Initialize + tdep->sc_pc_offset and tdep->sc_sp_offset. + (i386_gdbarch_init): Likewise. + * i386bsd-tdep.c (i386bsd_sigcontext_addr): Don't make it static + any more. + (i386bsd_sigtramp_saved_pc): Remove function. + (i386bsd_init_abi): Don't initialize tdep->sigtramp_saved_pc. + Initialize tdep->sigcontext_addr instead. Initialize + tdep->sc_pc_offset. + * i386-linux-tdep.c (i386_linux_init_abi): Remove initialization + of tdep->sigtramp_saved_pc. + * i386-sol2-tdep.c (i386_sol2_init_abi): Don't initialize + tdep->sigtramp_saved_pc. Initialize tdep->sigcontext_addr + instead. + + * i386-tdep.c (i386_frameless_function_invocation, + i386_frame_num_args, i386_frame_init_saved_regs, + i386_skip_prologue, i386_push_dummy_frame, i386_fix_call_dummy, + i386_pop_frame, i386_push_arguments, i386_store_struct_return, + i386_extract_return_value, i386_store_return_value, + i386_extract_struct_value_address, i386_register_virtual_type, + i386_register_convertible, i386_register_convert_to_virtual, + i386_register_convert_to_raw, i386_svr4_sigtramp_saved_pc, + i386_go32_init_abi, i386_nw_init_abi, i386_gdbarch_init): Make + static. + +2002-07-01 Mark Kettenis + + * i386bsd-tdep.c (i386bsd_frame_saved_pc): Removed. + + * config/i386/tm-i386sol2.h (COERCE_FLOAT_TO_DOUBLE): Removed. + * i386-sol2-tdep.c (i386_sol2_init_abi): Adjust for the removal of + this macro. Include "value.h". + +2002-06-30 Aidan Skinner + + * ada-exp.tab.c: remove as it's a generated file + * ada-lex.c: remove as it's a generated file + +2002-06-30 Mark Kettenis + + * config/i386/tm-i386.h (struct frame_info, struct + frame_saved_regs, struct value, struct type): Remove forward + declarations. + + * config/i386/tm-linux.h [HAVE_PTRACE_GETFPXREGS] + (FILL_FPXREGSET, HAVE_SSE_REGS): Remove define. + * config/i386/nm-linux.h [HAVE_PTRACE_GETFPXREGS] + (FILL_FPXREGSET): Define. + + * config/i386/tm-nbsd.h (HAVE_SSE_REGS): Remove define. + + * configure.tgt (i[3456]86-*-openbsd*): Fold into + i[3456]86-*-netbsd* case. + * config/i386/tm-obsd.h: Removed. + * config/i386/obsd.mt: Removed. + * config/i386/obsd.mh (NATDEPFILES): Remove corelow.o and + core-aout.o. + (MH_CFLAGS): Add -DYYDEBUG=0. + + * i386bsd-nat.c (_initialize_i386bsd_nat): Define SC_PC_OFFSET to + i386nbsd_sc_pc_offset on OpenBSD too. + + * config/i386/tm-fbsd.h [!SVR4_SHARED_LIBS] + (IN_SOLIB_CALL_TRAMPOLINE): Remove define. + * config/i386/tm-nbsdaout.h (IN_SOLIB_CALL_TRAMPOLINE): Remove + define. + * i386bsd-tdep.c: Include "arch-utils.h". + (i386bsd_aout_in_solib_call_trampoline): New function. + (i386bsd_init_abi): Set in_solib_call_trampoline to + i386bsd_aout_in_solib_call_trampoline. + (i386nbsdelf_init_abi, i386fbsd_init_abi): Set + in_solib_call_trampoline to generic_in_solib_call_trampoline. + +2002-06-28 Andrew Cagney + + * macrotab.h: Do not include "obstack.h" or "bcache.h". + (struct obstack, struct bcache): Add opaque declarations. + * Makefile.in (macrotab_h): Update + +2002-06-28 Andrew Cagney + + * blockframe.c (generic_find_dummy_frame): Change return type to + ``struct regcache''. + (struct dummy_frame): Replace field ``registers'' with regcache, a + struct regcache object. + (generic_find_dummy_frame): Update. + (generic_push_dummy_frame): Update. Use regcache_xfree, + regcache_xmalloc and regcache_cpy. + (generic_pop_dummy_frame): Update. Use regcache_cpy and + regcache_xfree. + (deprecated_generic_find_dummy_frame): Update. + (generic_read_register_dummy): Update. Use + regcache_read_as_address. + (generic_call_dummy_register_unwind): Update. Use regcache_read. + (generic_get_saved_register): Update. Use regcache_read. + +2002-06-28 Andrew Cagney + + * Makefile.in (objfiles_h): Add $(bcache_h). + * objfiles.h: Include "bcache.h". + + * Makefile.in (symtab_h): Remove $(bcache_h). + * symtab.h: Do not include "bcache.h". + +2002-06-28 Andrew Cagney + + * ppcnbsd-tdep.c (ppcnbsd_init_abi): Set frame_chain_valid to + generic_func_frame_chain_valid. + +2002-06-28 David O'Brien + + * config/i386/nm-fbsd.h: Include . + * config/i386/tm-fbsd.h: Likewise. + +2002-06-28 Andrew Cagney + + * rs6000-tdep.c (rs6000_gdbarch_init): Use + generic_unwind_get_saved_register. + +2002-06-27 Andrew Cagney + + From 2002-06-27 John David Anglin : + * regcache.c (supply_register): Add missing argument to + register_buffer call. + +2002-06-27 Andrew Cagney + + * Makefile.in (init.c): Drop -e option to grep. Not necessary and + Solaris /bin/grep does not not like it. From Peter Schauer. + +2002-06-26 Tom Tromey + + * command.h (add_setshow_cmd): Declare. + (add_setshow_cmd_full): Declare. + * cli/cli-decode.c (add_setshow_cmd): No longer static. Now + returns void. Use add_setshow_cmd_full. + (add_setshow_cmd_full): New function. + (add_setshow_auto_boolean_cmd): Use add_setshow_cmd_full. + (add_setshow_boolean_cmd): Likewise. + +2002-06-26 Jason Thorpe + + * config/vax/tm-vax.h: Protect from multiple inclusion. + (TARGET_UPAGES, TARGET_NBPG, STACK_END_ADDR) + (SIGTRAMP_START, SIGTRAMP_END, SIGCONTEXT_PC_OFFSET): Move to... + * config/vax/tm-vaxbsd.h: ...here. New file. + * config/vax/vax.mt (TM_FILE): Set to tm-vaxbsd.h. + +2002-06-26 Jason Thorpe + + * config/vax/tm-vax.h (BREAKPOINT): Remove. + (BELIEVE_PCC_PROMOTION): Remove. + (AP_REGNUM): Move to... + * config/vax/nm-vax.h: ...here. + * vax-tdep.c: Use VAX_AP_REGNUM instead of AP_REGNUM. + (vax_breakpoint_from_pc): New function. + (vax_gdbarch_init): Initialize gdbarch_breakpoint_from_pc + and gdbarch_believe_pcc_promotion. + +2002-06-26 Jason Thorpe + + * Makefile.in (vax_tdep_h): Define. + (vax-tdep.o): Use $(vax_tdep_h). + * vax-tdep.c (vax_gdbarch_init): Use generic OS ABI framework. + (vax_dump_tdep): New function. + (_initialize_vax_tdep): Register vax_dump_tdep. + * vax-tdep.h: Include osabi.h. + (struct gdbarch_tdep): New. + +2002-06-26 Andrew Cagney + + * frame.h (deprecated_generic_find_dummy_frame): Rename + generic_find_dummy_frame. + * blockframe.c (generic_find_dummy_frame): Make static. + (deprecated_generic_find_dummy_frame): New function. + * sh-tdep.c (sh_nofp_frame_init_saved_regs): Replace + generic_find_dummy_frame with deprecated_find_dummy_frame. + (sh64_nofp_frame_init_saved_regs): Ditto. + (sh_fp_frame_init_saved_regs): Ditto. + * s390-tdep.c (s390_frame_saved_pc_nofix): Ditto. + (s390_frame_chain): Ditto. + * cris-tdep.c (cris_frame_init_saved_regs): Ditto. + +2002-06-26 Grace Sainsbury + + * config/m68k/tm-m68k.h: Rearrange code so macros not in the + gdbarch vector are at the top. + (NUM_REGS): Remove. + (FP_REGNUM, SP_REGNUM, PS_REGNUM, PC_REGNUM, FP0_REGNUM): Remove. + (FRAME_ARGS_ADDRESS): Remove. + (FRAME_LOCALS_ADDRESS): Remove. + (FRAME_NUM_ARGS): Remove. + (FRAME_ARGS_SKIP): Remove. + * m68k-tdep.c (enum): Add eumeration of special register numbers. + (m68k_gdbarch_init): Add gdbarch initializations for macros + undefined in tm-m68k.h + +2002-06-26 Grace Sainsbury + + * monitor.h: Add the function regname to monitor_ops + structure. This way NUM_REGS does not have to be a constant. + * monitor.c (monitor_fetch_register): Added support for regname + function. The function is called if the array regnames is NULL. + (monitor_store_register): Same. + * cpu32bug-rom.c (cpu32bug_regname): Add function. Replaces + regnames array. + (init_cpu32bug_cmds): set cpu32bug_cmds.regnames to NULL, + cpu32bug_cmds.regname to point to new function. + * abug-rom.c (abug_regname): Same as above. + (init_abug_cmds): Same. + * dbug-rom.c (dbug_regname): Same as above. + (init_dbug_cmds): Same. + * remote-est.c (est_regname): Same. + (init_est_cmds): Same. + * rom68k-rom.c (rom68k_regname): Same. + (init_rom68k_cmds): Same. + +2002-06-25 Tom Tromey + + * breakpoint.c (delete_command): Don't repeat `delete' commands. + +2002-06-25 Andrew Cagney + + * infrun.c (stop_registers): Change variable's type to ``struct + regcache'''. + (xmalloc_inferior_status): Delete function. + (free_inferior_status): Delete function. + (normal_stop): Use regcache_cpy. + (struct inferior_status): Change type of fields ``stop_registers'' + and ``registers'' to ``struct regcache''. + (write_inferior_status_register): Use regcache_write. + (save_inferior_status): Instead of calling + xmalloc_inferior_status, allocate the inf_status buffer directly. + Use regcache_dup_no_passthrough and regcache_dup to save the + buffers. + (restore_inferior_status): Use regcache_xfree and regcache_cpy. + Replace the stop_registers regcache instead of overriding it. Use + regcache_xfree. Instead of calling free_inferior_status, xfree + the buffer directly. + (discard_inferior_status): Use regcache_xfree. Instead of calling + free_inferior_status, xfree the buffer directly. + (build_infrun): Use regcache_xmalloc. + (_initialize_infrun): Delete redundant call to build_infrun. + + * Makefile.in (infcmd.o): Add $(regcache_h). + + * infcmd.c: Include "regcache.h". + (run_stack_dummy): Use deprecated_grub_regcache_for_registers to + obtain the address of `stop_registers' register buffer. + (print_return_value): Ditto. + + * inferior.h (struct regcache): Add opaque declaration. + (stop_registers): Change variable's declared type to ``struct + regcache''. + +2002-06-24 Tom Tromey + + * cli/cli-decode.c (add_show_from_set): Fixed typo in comment. + * target.c (initialize_targets): Fixed typo in + trust-readonly-sections `show' documentation. + + * main.c: Marked all strings with _(). + +2002-06-24 Don Howard + + * memattr.c (create_mem_region): Treat hi == 0 as a special case + that means max CORE_ADDR+1. + (lookup_mem_region): Ditto. + (mem_info_command): Ditto. + +2002-06-24 Grace Sainsbury + + * config/m68k/tm-m68k.h (DECR_PC_AFTER_BREAK): Remove. + (REGISTER_BYTES_OK): Remove. + (REGISTER_BYTES): Remove. + (STORE_STRUCT_RETURN): Remove. + (DEPRECATED_EXTRACT_RETURN_VALUE): Remove. + (STORE_RETURN_VALUE): Remove. + (DEPRECATED_EXTRACT_STRUCT_VALUE_ADDRESS): Remove. + (FRAME_CHAIN): Remove. + (FRAMELESS_FUNCTION_INVOCATION): Remove. + (FRAME_SAVED_PC): Remove. + * m68k-tdep.c (m68k_register_bytes_ok):Add. + (m68k_store_struct_return): Add. + (m68k_deprecated_extract_return_value): Add. + (m68k_deprecated_extract_struct_value_address): Add. + (m68k_store_return_value): Add. + (m68k_frame_chain): Add. + (m68k_frameless_function_invocation): Add. + (m68k_frame_saved_pc): Add. + (m68k_gdbarch_init): added set_gdbarch calls for new + functions and deleted macros. + +2002-06-23 Tom Tromey + + * Makefile.in (HFILES_NO_SRCDIR): Remove old files. + (ALLDEPFILES): Likewise. + (udiheaders): Removed. + (udip2soc.o): Likewise. + (udi2go32.o): Likewise. + (udr.o): Likewise. + (HFILES_WITH_SRCDIR): Don't mention udiheaders. + +2002-06-22 Andrew Cagney + + * infrun.c (_initialize_infrun): Delete unnecessary call to + build_infrun. + + * regcache.h: Update comments describing the regcache_cpy family + of functions. + (regcache_save, regcache_restore): Delete declaration. + (regcache_save_no_passthrough): Delete declaration. + (regcache_restore_no_passthrough): Delete declaration. + * regcache.c (regcache_save): Delete function. + (regcache_save_no_passthrough): Delete function. + (regcache_restore): Delete function. + (regcache_restore_no_passthrough): Delete function. + +2002-06-21 Andrew Cagney + + * config/m68k/tm-m68k.h: Fix typo. + (FRAME_INIT_SAVED_REGS): Define when non-multi-arch. + (m68k_frame_init_saved_regs): Declare. + +2002-06-21 Jim Blandy + + Remove some vestiges of Harris 88k support. + * dwarf2read.c (decode_locdesc): Remove `#if' block for Harris 88k + register numbering quirk. + * elfread.c (elf_symtab_read): Remove `#if' block for skipping + odd symbols occurring in Harris 88k ELF targets. + +2002-06-21 Tom Tromey + + * gdb_locale.h: New file. + * Makefile.in (GDB_CFLAGS): Define LOCALEDIR. + (defs_h): Added gdb_locale.h. + * configure, config.in: Rebuilt. + * configure.in (PACKAGE): Define. + * defs.h: Include gdb_locale.h. + * main.c (captured_main): Call setlocale, bindtextdomain, + textdomain. + +2002-06-21 Dave Brolley + + From Stan Shebs, Jim Blandy, Mark Salter, Kevin Buettner: + * config/frv/frv.mt: New file. + * config/frv/tm-frv.h: New file. + * configure.tgt: Support frv-*-*. + * Makefile.in (frv-tdep.o): New target. + * frv-tdep.c: New file. + * NEWS: Mention frv. + +2002-06-21 Dave Brolley + + * MAINTAINERS: Add self to "Write After Approval" list. + +2002-06-21 Grace Sainsbury + + * config/m68k/tm-m68k.h (REGISTER_BYTE, REGISTER_RAW_SIZE) + (REGISTER_VIRTUAL_SIZE, MAX_REGISTER_RAW_SIZE) + (REGISTER_VIRTUAL_TYPE, REGISTER_NAMES, TARGET_LONG_DOUBLE_FORMAT) + (FUNCTION_START_OFFSET, SKIP_PROLOGUE, SAVED_PC_AFTER_CALL) + (INNER_THAN, STACK_ALIGN, REGISTER_SIZE): Remove macros. + + * m68k-tdep.c: Include arch-utils.h + (m68k_register_raw_size): Add. + (m68k_register_virtual_size): Add. + (m68k_register_virtual_type): Add. + (m68k_register_name): Add. + (m68k_stack_align): Add. + (m68k_register_byte): Add. + (m68k_gdbarch_init): Add set_gdbarch calls for macros removed in + tm-m68k.h. + +2002-06-21 Grace Sainsbury + + * m68k-tdep.c (m68k_frame_init_saved_regs): Replace + m68k_find_saved_regs. + (m68k_pop_frame): Removed saved_regs structure, and replaced + references to it with frame->saved_regs. + (m68k_gdbarch_init): Added function calls to initialize the + gdbarch structure. + (m68k_fix_call_dummy): Add. + * config/m68k/tm-m68k.h: (FRAME_FIND_SAVED_REGS): Remove. + (CALL_DUMMY): Remove. + (CALL_DUMMY_LENGTH): Remove. + (CALL_DUMMY_START_OFFSET): Remove. + (CALL_DUMMY_BREAKPOINT_OFFSET): Remove. + (FIX_CALL_DUMMY): Remove. + (PUSH_DUMMY_FRAME): Remove. + (POP_FRAME): Remove. + +2002-06-19 Pierre Muller + + * parse.c (parse_fprintf): New function used to avoid calls to + fprintf in bison parser generated debug code. + * parser-defs.h: Declaration of new parse_fprintf function. + * ada-exp.y, c-exp.y, f-exp.y, jv-exp.y, m2-exp.y, p-exp.y: + Set YYDEBUG to 1 by default. + Set YYFPRINTF as parse_fprintf. + +2002-06-21 Michal Ludvig + + * dwarf2cfi.c (read_encoded_pointer): Don't handle pointer + encoding anymore. + (pointer_encoding, enum ptr_encoding): New. + (execute_cfa_program): Take care about pointer encoding. + (dwarf2_build_frame_info): Only call parse_frame_info for + .debug_frame and .eh_frame. + (parse_frame_info): New, derived from former dwarf2_build_frame_info. + fixed augmentation handling, added relative addressing, + ignore duplicate FDEs. Added comments. + * dwarf2cfi.c: Reindented. + +2002-06-20 Elena Zannoni + + * event-top.c (command_handler): Don't use space_at_cmd_start + unless there is sbrk() on the host. Assign time and space data + to union fields of the appropriate length. + +2002-06-20 Michal Ludvig + + * x86-64-tdep.c (x86_64_register_nr2name): Rename to + x86_64_register_name. Return type changed to 'const char *'. + (x86_64_register_name2nr): Rename to x86_64_register_number. + (x86_64_gdbarch_init): Update to reflect the change. + * x86-64-tdep.h: Ditto. + * x86-64-linux-nat.c (x86_64_fxsave_offset) + (supply_fpregset): Ditto. + +2002-06-19 Andrew Cagney + + * regcache.h: Update copyright. + (struct regcache, struct gdbarch): Add opaque declarations. + (current_regcache): Declare global variable. + (regcache_read, regcache_write): Add gdbarch parameter. + (regcache_save, regcache_save_no_passthrough) + (regcache_restore, regcache_restore_no_passthrough) + (regcache_dup, regcache_dup_no_passthrough) + (regcache_cpy, regcache_cpy_no_passthrough) + (deprecated_grub_regcache_for_registers) + (deprecated_grub_regcache_for_register_valid) + (regcache_valid_p): Add function declarations. + + * regcache.c: Update copyright. + (regcache_descr_handle): New global variable. + (struct regcache_descr): Define. + (init_legacy_regcache_descr, init_regcache_descr): New functions. + (regcache_descr, xfree_regcache_descr): New functions. + (struct regcache): Define. + (regcache_xmalloc, regcache_xfree): New functions. + (regcache_cpy, regcache_cpy_no_passthrough): New functions. + (regcache_dup, regcache_dup_no_passthrough): New functions. + (regcache_valid_p, regcache_read_as_address): New functions. + (deprecated_grub_regcache_for_registers): New function. + (deprecated_grub_regcache_for_register_valid): New function. + (current_regcache): New global variable. + (register_buffer): Add regcache parameter. Update calls. + (regcache_read, regcache_write): Add regcache parameter. Rewrite. + (read_register_gen, write_register_gen): Update register_buffer + call. Test for legacy_p instead of gdbarch_register_read_p or + gdbarch_register_write_p. + (regcache_collect): Update register_buffer call. + (build_regcache): Rewrite. Use deprecated grub functions. + (regcache_save, regcache_save_no_passthrough): New functions. + (regcache_restore, regcache_restore_no_passthrough): New + functions. + (_initialize_regcache): Create the regcache_data_handle. Swap + current_regcache global variable. + + * sh-tdep.c (sh_pseudo_register_read): Add current_regcache + parameter to regcache_read and regcache_write calls. + (sh4_register_read): Ditto. + (sh64_pseudo_register_read): Ditto. + (sh64_register_read): Ditto. + (sh_pseudo_register_write): Ditto. + (sh4_register_write): Ditto. + (sh64_pseudo_register_write): Ditto. + (sh64_register_write): Ditto. + + * defs.h (XCALLOC): Define. + +2002-06-19 Grace Sainsbury + + * config/m68k/tm-m68k.h (GDB_MULTI_ARCH): Added (set to 0). + * m68k-tdep.c (m68k_gdbarch_init): Added. + (m68k_dump_tdep): Added. + +2002-06-19 Daniel Jacobowitz + + * ada-lang.c (fill_in_ada_prototype): Update comment. + +2002-06-19 Daniel Jacobowitz + + * mips-tdep.c (enum mips_abi): Explicitly start at 0. Add + MIPS_ABI_LAST. + (mips_abi_string, mips_abi_strings): New. + (struct gdbarch_tdep): Remove mips_abi_string, add found_abi. + (mips_gdbarch_init): Set tdep->found_abi. Don't set + tdep->mips_abi_string. Honor mips_abi_string. Default to + O32 if no ABI is found. + (mips_dump_tdep): Use mips_abi_strings. + (mips_abi_update): New function. + (_initialize_mips_tdep): Initialize mips_abi_string. Add + ``set mips abi'' and ``show mips abi''. Check the size of + mips_abi_strings. + +2002-06-19 Andrew Cagney + + * i386-linux-tdep.c (i386_linux_register_name): Make return type + constant. + +2002-06-18 Joel Brobecker + + * alpha-tdep.c (heuristic_proc_desc): Compute the size of the + current frame using only the first stack size adjustment. All + subsequent size adjustments are not considered to be part of + the "static" part of the current frame. + Compute the address of the saved registers relative to the + Frame Pointer ($fp) instead of the Stack Pointer if $fp is + in use in this frame. + +2002-06-18 Don Howard + + * valops.c (value_ind): Use value_at_lazy() when dereferencing + type int expressions. Thanks to Jim Blandy for + suggesting this solution. + +2002-06-18 Andrew Cagney + + * config/romp/xm-rtbsd.h: Delete file. + * config/romp/rtbsd.mh: Delete file. + +2002-06-18 Keith Seitz + + * breakpoint.c (condition_command): Post breakpoint_modify + when a condition is added to an existing breakpoint. + (commands_command): Likewise for commands. + (set_ignore_count): Likewise for ignore counts. + If no tty, do not simply return, still need to send event + notification. + (ignore_command): Only print a newline if the command came + from a tty. + Don't call breakpoints_changed, since this is now properly + handled by set_ignore_count. + +2002-06-18 Andrew Cagney + + * MAINTAINERS: Note that cris-elf target can be compiled with + -Werror. + * cris-tdep.c (cris_register_name): Make return type constant. + (cris_breakpoint_from_pc): Ditto. + +2002-06-18 Michal Ludvig + + * frame.h (struct frame_info): Change type of context to + 'struct context'. + +2002-06-17 Andrew Cagney + + * gdbarch.sh (REGISTER_NAME): Change return type a constant string + pointer. + * gdbarch.h, gdbarch.c: Regenerate. + * config/mips/tm-mips.h (mips_register_name): Update. + * i386-tdep.h (i386_register_name): Update. + * mips-tdep.c (mips_register_name): Update + * alpha-tdep.c (alpha_register_name): Update. + * arch-utils.c (legacy_register_name): Update. + * arch-utils.h (legacy_register_name): Update. + * avr-tdep.c (avr_register_name): Update. + * ia64-tdep.c (ia64_register_name): Update. + * i386-tdep.c (i386_register_name): Update. + * sparc-tdep.c (sparc32_register_name): Update. + (sparc64_register_name): Update. + (sparclite_register_name): Update. + (sparclet_register_name): Update. + * sh-tdep.c (sh_generic_register_name): Update. + (sh_sh_register_name): Update. + (sh_sh3_register_name): Update. + (sh_sh3e_register_name): Update. + (sh_sh_dsp_register_name): Update. + (sh_sh3_dsp_register_name): Update. + (sh_sh4_register_name): Update. + (sh_sh64_register_name): Update. + * s390-tdep.c (s390_register_name): Update. + * rs6000-tdep.c (rs6000_register_name): Update. + * ns32k-tdep.c (ns32k_register_name_32082): Update. + (ns32k_register_name_32382): Update. + * d10v-tdep.c (d10v_ts2_register_name): Update. + (d10v_ts3_register_name): Update. + * xstormy16-tdep.c (xstormy16_register_name): Update. + * vax-tdep.c (vax_register_name): Update. + * v850-tdep.c (v850_register_name): Update. + * m68hc11-tdep.c (m68hc11_register_name): Update. + * mn10300-tdep.c (mn10300_generic_register_name): Update. + (am33_register_name): Update. + +2002-06-17 Grace Sainsbury + + * m68k-tdep.c: Reindented. + +2002-06-17 Andrew Cagney + + * gdb_indent.sh: Add prgregset_t, fpregset_t, and gregset_t to the + list of predefined types. + +2002-06-16 Mark Kettenis + + * config/i386/tm-i386.h (REGISTER_VIRTUAL_TYPE, + REGISTER_CONVERTIBLE, REGISTER_CONVERT_TO_VIRTUAL, + REGISTER_CONVERT_TO_RAW): Remove defines. + (i386_register_virtual_type, i386_register_convertible, + i386_register_convert_to_virtual, i386_register_convert_to_raw): + Remove prototypes. + * i386-tdep.c (i386_gdbarch_init): Adjust for removal of the + macros mentioned above. + + * config/i386/tm-i386lynx.h (SAVED_PC_AFTER_CALL): Remove define. + (i386lynx_saved_pc_after_call): Remove prototype. + * i386ly-tdep.c: Include "i386-tdep.h". + (i386lynx_saved_pc_after_call): Make static. Use + read_memory_nobpt instead of read_memory. Use + read_memory_unsigned_integer instead of read_memory_integer. + (i386lynx_init_abi): New function. + (i386lynx_coff_osabi_sniffer): New function. + (_initialize_i386bsd_tdep): New function. + + * config/i386/tm-i386.h (PARM_BOUNDARY, CALL_DUMMY, + CALL_DUMMY_LENGTH, CALL_DUMMY_START_OFFSET, + CALL_DUMMY_BREAKPOINT_OFFSET, FIX_CALL_DUMMY): Remove defines. + (i386_fix_call_dummy): Remove prototype. + * i386-tdep.c (i386_call_dummy_words): New variable. + (i386_gdbarch_init): Adjust for removal of the + macros mentioned above. + +2002-06-15 Andrew Cagney + + * command.h (add_setshow_auto_boolean_cmd): Replace + add_set_auto_boolean_cmd. + * cli/cli-decode.c (add_setshow_auto_boolean_cmd): Replace + add_set_auto_boolean_cmd. + * cli/cli-decode.h (add_set_auto_boolean_cmd): Delete declaration. + * mips-tdep.c (_initialize_mips_tdep): Update ``set mips + mask-address'' command. + (show_mask_address): Add cmd parameter. + * remote.c (add_packet_config_cmd): Update. Change type of + set_func and show_func to cmd_sfunc_ftype. + (_initialize_remote): Update `set remote Z-packet' + (show_remote_protocol_qSymbol_packet_cmd): Add cmd parameter. + (show_remote_protocol_e_packet_cmd): Ditto. + (show_remote_protocol_E_packet_cmd): Ditto. + (show_remote_protocol_P_packet_cmd): Ditto. + (show_remote_protocol_Z_software_bp_packet_cmd): Ditto. + (show_remote_protocol_Z_hardware_bp_packet_cmd): Ditto. + (show_remote_protocol_Z_write_wp_packet_cmd): Ditto. + (show_remote_protocol_Z_read_wp_packet_cmd): Ditto. + (show_remote_protocol_Z_access_wp_packet_cmd): Ditto. + (show_remote_protocol_Z_packet_cmd): Ditto. + (show_remote_protocol_binary_download_cmd): Ditto. + (show_remote_cmd): Pass NULL to all of above. + +2002-06-15 Mark Kettenis + + * config/i386/tm-i386.h (PUSH_ARGUMENTS, STORE_STRUCT_RETURN, + DEPRECATED_EXTRACT_RETURN_VALUE, STORE_RETURN_VALUE, + DEPRECATED_EXTRACT_STRUCT_VALUE_ADDRESS, PUSH_DUMMY_FRAME, + POP_FRAME): Remove defines. + (i386_push_arguments, i386_store_struct_return, + i386_extract_return_value, i386_store_return_value, + i386_extract_struct_value_address, i386_push_dummy_frame, + i386_pop_frame): Renove prototypes. + * i386-tdep.c (i386_gdbarch_init): Adjust for removal of the + macros mentioned above. + +2002-06-15 Andrew Cagney + + * cli/cli-decode.c (add_setshow_boolean_cmd): Replace + add_set_boolean_cmd. + (add_setshow_cmd): New function. + * command.h (add_setshow_boolean_cmd): Replace + add_set_boolean_cmd. + * remote-rdi.c (_initialize_remote_rdi): Update ``set rdiheartbeat'' + and ``set rdiromatzero''. + * maint.c (_initialize_maint_cmds): Update commented out code. + * cli/cli-decode.h (add_set_boolean_cmd): Delete declaration. + * target.c (initialize_targets): Update `set + trust-readonly-sections'. + * remote.c (_initialize_remote): Update `set remotebreak'. + +2002-06-15 Mark Kettenis + + * config/i386/tm-i386.h (FUNCTION_START_OFFSET, INNER_THAN, + BREAKPOINT, DECR_PC_AFTER_BREAK): Removed. + * i386-tdep.c (i386_skip_prologue): Adjust function signature to + fit into multi-arch framework. + (i386_breakpoint_from_pc): New function. + (i386_gdbarch_init): Adjust for removal of the macros mentioned + above. + + * config/i386/tm-i386.h (FRAMELESS_FUNCTION_INVOCATION, + FRAME_ARGS_ADDRESS, FRAME_LOCALS_ADDRESS, FRAME_NUM_ARGS, + FRAME_ARGS_SKIP, FRAME_INIT_SAVED_REGS): Remove defines. + (i386_frameless_function_invocation, i386_frame_num_args, + i386_frame_init_saved_regs): Remove prototypes. + * i386-tdep.c (i386_gdbarch_init): Adjust for removal of the + macros mentioned above. + +2002-06-15 Andrew Cagney + + * cli/cli-decode.c (set_cmd_cfunc): Update. + (set_cmd_sfunc): Update. + * command.h (cmd_cfunc_ftype, cmd_sfunc_ftype): Declare. + (set_cmd_sfunc, set_cmd_cfunc): Update. + * cli/cli-decode.h: Update. + +2002-06-15 Mark Kettenis + + * i386-sol2-tdep.c (i386_sol2_osabi_sniffer): New function. + (_initialize_i386_sol2_tdep): Register i386_sol2_osabi_sniffer. + +2002-06-15 Andrew Cagney + + * defs.h (auto_boolean): Declare enum. + * command.h (cmd_auto_boolean): Delete enum. + * mips-tdep.c (mask_address_var): Update. + (mips_mask_address_p): Update. + (show_mask_address): Update. + * remote.c (struct packet_config): Update. + (update_packet_config): Update. + (show_packet_config_cmd): Update. + (packet_ok): Update. + (add_packet_config_cmd): Update. + (_initialize_remote): + * command.h: Update. + * cli/cli-setshow.c (parse_auto_binary_operation): Update. + (do_setshow_command): Update. + * cli/cli-decode.c (add_set_auto_boolean_cmd): Update. + * cli/cli-decode.h: Update. + +2002-06-15 Mark Kettenis + + * config/i386/tm-cygwin.h, config/i386/tm-fbsd.h, + config/i386/tm-go32.h, config/i386/tm-i386gnu.h, + config/i386/tm-i386sol2.h, config/i386/tm-i386v4.h, + config/i386/tm-linux.h, config/i386/tm-nbsd.h, + config/i386/tm-obsd.h (HAVE_I387_REGS): Remove define. + * config/i386/tm-i386.h: Unconditionally define FLOAT_INFO. + + * i386-tdep.c (i386_coff_osabi_sniffer): Add "coff-go32" to the + list of DJGPP COFF targets. + + * config/i386/tm-i386.h (REGISTER_SIZE): Remove define. + (NUM_GREGS, NUM_FREGS, NUM_SSE_REGS): Remove defines. + (FP_REGNUM, SP_REGNUM, PC_REGNUM, PS_REGNUM): Remove defines. + (FP0_REGNUM): Remove define. + (MAX_REGISTER_RAW_SIZE, MAX_REGISTER_VIRTUAL_SIZE, + MAX_REGISTER_VIRTUAL_SIZE): Remove define. + (i386_register_virtual_size): Remove protoype. + * i386-tdep.c (i386_register_virtual_size): Removed. + (i386_extract_return_value, i386_store_return_value): Use + FP0_REGNUM instead of NUM_FREGS to determine whether the + floating-point registers are available. + (i386_gdbarch_init): Tweak FIXME about FPU registers. + Adjust for removal of macros mentioned above. + +2002-06-15 Mark Kettenis + + * i386v4-nat.c: Include "i386-tdep.h". Reformat and tweak various + comments. + (fill_gregset, supply_gregset, supply_fpregset, fill_fpregset): + Remove prototypes. + (supply_gregset, fill_gregset): Remove use of register keyword and + remove declaration for regmap. Use I386_NUM_GREGS instead of + NUM_REGS and NUM_FREGS. + (FPREGSET_FSAVE_OFFSET): Remove. + (supply_fpregset, fill_fpregset): Use FPO_REGNUM instead of + NUM_FREGS to determine whether the floating-point registers are + available. + + * i386gnu-nat.c (supply_gregset, gnu_fetch_registers, + gnu_store_registers): Replace usage of NUM_GREGS with + I386_NUM_GREGS. + + * i386-linux-nat.c (OLD_CANNOT_FETCH_REGISTER, + OLD_CANNOT_STORE_REGISTER, supply_gregset, fill_gregset): Replace + usage of NUM_GREGS with I386_NUM_GREGS. + + * i386-linux-nat.c (fill_gregset): Remove redundant parentheses. + + * i386bsd-nat.c: Include "i386-tdep.h". + (supply_gregset, fill_gregset): Replace usage of NUM_GREGS with + I386_NUM_GREGS. + + * i386v-nat.c: Remove copnditional inclusion of , + and associated comment. They no longer make any sense, since we + don't use this file anymore on Linux. + + * config/i386/tm-i386.h (MAX_NUM_REGS): Removed. + * i386-tdep.c (i386_register_offset, i386_register_size): Use + I386_SSE_NUM_REGS instead of MAX_NUM_REGS for the number of + elements in these arrays. + (_initialize_i386_tdep): Use I386_SSE_NUM_REGS instead of + MAX_NUM_REGS. + +2002-06-15 Mark Kettenis + + * osabi.h (gdb_osabi): Add GDB_OSABI_LYNXOS. + * osabi.c (gdb_osabi_names): Add entry for "LynxOS". + +2002-06-14 Andrew Cagney + + * gdbarch.sh (DEPRECATED_EXTRACT_RETURN_VALUE): Rename + EXTRACT_RETURN_VALUE. + (DEPRECATED_EXTRACT_STRUCT_VALUE_ADDRESS): Rename + EXTRACT_STRUCT_VALUE_ADDRESS. + * gdbarch.h, gdbarch.c: Regenerate. + + * values.c (value_being_returned): Handle + DEPRECATED_EXTRACT_STRUCT_VALUE_ADDRESS. + (EXTRACT_RETURN_VALUE): Define as DEPRECATED_EXTRACT_RETURN_VALUE. + + * arm-linux-tdep.c (arm_linux_init_abi): Update. + * arm-tdep.c (arm_gdbarch_init): Update. + * avr-tdep.c (avr_gdbarch_init): Update. + * cris-tdep.c (cris_gdbarch_init): Update. + * d10v-tdep.c (d10v_gdbarch_init): Update. + * ia64-tdep.c (ia64_gdbarch_init): Update. + * m68hc11-tdep.c (m68hc11_gdbarch_init): Update. + * rs6000-tdep.c (rs6000_gdbarch_init): Update. + * s390-tdep.c (s390_gdbarch_init): Update. + * sh-tdep.c (sh_gdbarch_init): Update. + * s390-tdep.c (s390_gdbarch_init): Update. + * sparc-tdep.c (sparc_gdbarch_init): Update. + * ns32k-tdep.c (ns32k_gdbarch_init): Update. + * v850-tdep.c (v850_gdbarch_init): Update. + * vax-tdep.c (vax_gdbarch_init): Update. + * x86-64-tdep.c (x86_64_gdbarch_init): Update. + * xstormy16-tdep.c (xstormy16_gdbarch_init): Update. + + * config/arc/tm-arc.h: Update. + * config/d30v/tm-d30v.h: Update. + * config/fr30/tm-fr30.h: Update. + * config/h8300/tm-h8300.h: Update. + * config/h8500/tm-h8500.h: Update. + * config/i386/tm-i386.h: Update. + * config/i386/tm-ptx.h: Update. + * config/i386/tm-symmetry.h: Update. + * config/i960/tm-i960.h: Update. + * config/m32r/tm-m32r.h: Update. + * config/m68k/tm-delta68.h: Update. + * config/m68k/tm-linux.h: Update. + * config/m68k/tm-m68k.h: Update. + * config/m88k/tm-m88k.h: Update. + * config/mcore/tm-mcore.h: Update. + * config/mips/tm-mips.h: Update. + * config/mn10200/tm-mn10200.h: Update. + * config/pa/tm-hppa.h: Update. + * config/pa/tm-hppa64.h: Update. + * config/sparc/tm-sp64.h: Update. + * config/sparc/tm-sparc.h: Update. + * config/sparc/tm-sparclet.h: Update. + * config/z8k/tm-z8k.h: Update. + +2002-06-14 Andrew Cagney + + * Makefile.in (i386_linux_tdep_h): Define. + (i386_tdep_h, i387_tdep_h): Define. + (i386-linux-nat.o): Add $(i386_linux_tdep_h), + $(i386_tdep_h) and $(i387_tdep_h). + * i386-linux-nat.c: Include "i386-linux-tdep.h". + +2002-06-14 Mark Kettenis + + * config/i386/tm-i386.h (START_INFERIOR_TRAPS_EXPECTED): Removed. + Already covered by the default. + + * config/i386/tm-i386.h (TARGET_LONG_DOUBLE_FORMAT, + TARGET_LONG_DOUBLE_BIT): Remove. * i386-tdep.c + (i386_gdbarch_init): Initialize long_double_format and long_double + bit. + + * config/i386/i386sol2.mt (TDEPFILES): Add i386-sol2-tdep.o and + i386bsd-tdep.o. Remove solib.o, solib-svr4.o and solib-legacy.o. + Move these to ... + * config/i386/i386sol2.mh: ... here. + * config/i386/tm-i386sol2.h (STAB_REG_TO_REGNUM): Remove define. + (sigtramp_saved_pc, I386V4_SIGTRAMP_SAVED_PC): Don't #undef. + (SIGCONTEXT_PC_OFFSET): Remove define. + (IN_SIGTRAMP): Remove define. + * i386-sol2-tdep.c: New file. + + * config/i386/i386nw.mt (TM_FILE): Change to tm-i386.h. + * config/i386/tm-i386nw.h: Removed. + + * config/i386/tm-fbsd.h (STAB_REG_TO_REGNUM, + USE_STRUCT_CONVENTION): Remove defines. + (JB_ELEMENT_SIZE, JB_PC, GET_LONGJMP_TARGET): Remove defines. + (get_longjmp_target): Remove prototype. + (IN_SIGTRAMP): Remove define. + (i386bsd_in_sigtramp): Remove prototype. + (i386bsd_sigtramp_start, i386bsd_sigtramp_end): Turn into a + function. Update comment accordingly + (SIGTRAMP_START, SIGTRAMP): Adjust definition accordingly. + (FRAME_SAVED_PC): Remove define. + (i386bsd_frame_saved_pc): Remove prototype. + * config/i386/tm-nbsd.h (JB_ELEMENT_SIZE, JB_PC, + GET_LONGJMP_TARGET): Remove defines. + (get_longjmp_target): Remove prototype. + (IN_SIGTRAMP): Remove define. + (i386bsd_in_sigtramp): Remove prototype. + (i386bsd_sigtramp_start, i386bsd_sigtramp_end): Turn into a + function. Update comment accordingly + (SIGTRAMP_START, SIGTRAMP): Adjust definition accordingly. + (FRAME_SAVED_PC): Remove define. + (i386bsd_frame_saved_pc): Remove prototype. + * config/i386/tm-nbsdaout.h (i386nbsd_aout_use_struct_convention): + Remove prototype. + (USE_STRUCT_CONVENTION): Remove prototype. + * i386bsd-nat.c (i386bsd_sigcontext_pc_offset): Remove + declaration. + (_initialize_i386bsd_nat): Revise logic to determine some + constants at compile time when compiling a native GDB. Warn if + things don't match up with what we expect. + * i386bsd-tdep.c (i386bsd_sigtramp_start, i386bsd_sigtramp_end): + Remove variables. + (i386bsd_in_sigtramp): Rename tp i386bsd_pc_in_sigtramp. Rewrite + to use date stored in `struct gdbarch_tdep'. + (i386bsd_sigcontext_offset): Remove varaible. + (i386bsd_sigtramp_saved_pc): Make public. Rewrite to use data + stored in `struct gdbarch_tdep'. + (i386bsd_frame_saved_pc): Make static. + (i386bsd_sigtramp_start, i386bsd_sigtramp_end): New functions. + (i386bsd_sc_pc_offset, i386nbsd_sc_pc_offset, + i386fbsd_sigtramp_start, i386fbsd_sigtramp_end, + i386fbsd4_sc_pc_offset): New variables. + (i386bsd_init_abi, i386nbsd_init_abi, i386nbsdelf_init_abi, + i386fbsdaout_init_abi, i386fbsd_init_abi, i386fbsd4_init_abi): New + functions. + (i386bsd_aout_osabi_sniffer, _initialize_i386bsd_tdep): New + functions. + * i386fbsd-nat.c (_initialize_i386fbsd_nat): Fix type in comment. + Modify the value of i386fbsd_sigtramp_start and + i386fbsd_sigtramp_end instead of i386bsd_sigtramp_start and + i386fbsd_sigtramp_end. + * i386nbsd-tdep.c: (i386nbsd_aout_use_struct_convention): Remove + function. + + * config/i386/tm-linux.h (I386_LINUX_ORIG_EAX_REGNUM): Move + define to i386-linux-tdep.h. + (NUM_REGS, MAX_NUM_REGS, REGISTER_BYTES, REGISTER_NAME, + REGISTER_BYTE, REGISTER_RAW_SIZE, STAB_REG_TO_REGNUM): Remove + defines. + (i386_linux_register_name, i386_linux_register_byte, + i386_linux_register_raw_size): Remove prototypes. + (i386_linux_svr4_fetch_link_map_offsets): Remove prototype. + (SVR4_FETCH_LINK_MAP_OFFSETS): Remove define. + (IN_SIGTRAMP, FRAME_CHAIN, FRAME_SAVED_PC, SAVED_PC_AFTER_CALL, + TARGET_WRITE_PC): Remove defines. + (i386_linux_in_sigtramp, i386_linux_frame_chain, + i386_linux_frame_saved_pc, i386_linux_saved_pc_after_call, + i386_linux_write_pc): Remove prototypes. + (JB_ELEMENT_SIZE, JB_PC, GET_LONGJMP_TARGET): Remove defines. + (get_longjmp_target): Remove prototype. + * i386-linux-tdep.h: New file. + * i386-linux-nat.c: Include "i386-linux-tdep.h". + * i386-linux-tdep.c: Include "i386-tdep.h" and + "i386-linux-tdep.h". + (i386_linux_register_name, i386_linux_register_byte, + i386_linux_register_raw_size, i386_linux_in_sigtramp, + i386_linux_write_pc, i386_linux_svr4_fetch_link_map_offsets): + Make static. + (i386_linux_init_abi): New function. + (_initialize_i386_linux_tdep): New function. + + * config/i386/tm-i386.h (SAVED_PC_AFTER_CALL): Remove define. + (i386_saved_pc_after_call): Remove prototype. + (MAX_NUM_REGS): Increase to deal with Linux's orig_eax "register". + (REGISTER_NAME, STAB_REG_TO_REGNUM, SDB_REG_TO_REGNUM, + DWARF_REG_TO_REGNUM, DWARF2_REG_TO_REGNUM): Remove defines. + (i386_register_name, i386_stab_reg_to_regnum, + i386_dwarf_reg_to_regnum): Remove prototypes. + (SIZEOF_GREGS, SIZEOF_FPU_REGS, SIZEOF_FPU_CTL_REGS, + SIZEOF_SSE_REGS): Remove defines. + (REGISTER_BYTES): Remove define. + (REGISTER_BYTE, REGISTER_RAW_SIZE): Remove defines. + (i386_register_byte, i386_register_raw_size): Remove prototypes. + (FRAME_CHAIN, FRAME_SAVED_PC): Remove defines. + (i386_frame_chain, i386_frame_saved_pc): Remove prototypes. + * config/i386/tm-i386v4.h (FRAME_CHAIN_VALID): Remove define. + (JB_ELEMENT_SIZE, JB_PC, JB_EBX, JB_ESI, JB_EDI, JB_EBP, JB_ESP, + JB_EDX, GET_LONGJMP_TARGET): Remove defines. + (get_longjmp_target): Remove prototype. + (I386V4_SIGTRAMP_SAVED_PC, IN_SIGTRAMP): Remove defines. + (sigtramp_saved_pc): Remove define. + (i386v4_sigtramp_saved_pc): Remove prototype. + * config/i386/tm-go32.h (FRAME_CHAIN, + FRAMELESS_FUNCTION_INVOCATION, FRAME_SAVED_PC): Remove defines. + (i386go32_frame_saved_pc): Remove prototype. + (JB_ELEMENT_SIZE, JB_PC, GET_LONGJMP_TARGET): Remove defines. + (get_longjmp_target): Remove prototype. + * i386-tdep.h: Include "osabi.h". + (enum i386_abi): Removed. + (enum struct_return): New enum. + (struct gdbarch_tdep): Remove abi member, add osabi, jb_pc_offset, + struct_return, sigtramp_saved_pc, sigtramp_start, sigtramp_end and + sc_pc_offset members. + (i386_gdbarch_register_os_abi): Remove prototype. + (I386_NUM_GREGS, I386_NUM_FREGS, I386_NUM_XREGS, + I386_SSE_NUM_REGS): New defines. + (I386_SIZEOF_GREGS, I386_SIZEOF_FREGS, I386_SIZEOF_XREGS, + I386_SSE_SIZEOF_REGS): New defines. + (i386_register_name, i386_register_byte, i386_register_raw_size): + New prototypes. + (i386_elf_init_abi, i386_svr4_init_abi): New prototypes. + (i386bsd_sigtramp_saved_pc): New prototype. + * i386-tdep.c: Don't include "elf-bfd.h". + (i386_stab_reg_to_regnum, i386_dwarf_reg_to_regnum, + i386_frame_chain, i386_saved_pc_after_call): Make static. + (i386_frame_saved_pc): Rewrite to call architecture dependent + function to deal with signal handlers. Make static. + (i386go32_frame_saved_pc): Removed. + [GET_LONGJMP_TARGET] (JB_PC, JB_ELEMENT_SIZE, get_longjmp_target): + Removed. + (i386_get_longjmp_target): New function. + (default_struct_convention, pcc_struct_convention, + reg_struct_convention, valid_conventions, struct_convention): New + variables. + (i386_use_struct_convention): New function. + (i386v4_sigtramp_saved_pc): Renamed to + i386_svr4_sigtramp_saved_pc. Made static. Moved. + (i386_pc_in_sigtramp): New function. + (i386_abi_names): Removed. + (ABI_TAG_OS_GNU_LINUX, ABI_TAG_OS_GNU_HURD, + ABI_TAG_OS_GNU_SOLARIS, ABI_TAG_OS_FREEBSD, ABI_TAG_OS_NETBSD): + Removed. + (process_note_sections, i386_elf_abi_from_note, i386_elf_abi, + i386_gdbarch_register_os_abi): Removed. + (struct i386_abi_handler): Removed. + (i386_abi_handler_list): Removed. + (i386_svr4_pc_in_sigtramp, i386_go32_pc_in_sigtramp): New + functions. + (i386_elf_init_abi, i386_svr4_init_abi, i386_go32_init_abi, + i386_nw_init_abi): New functions. + (i386_gdbarch_init): Rewritten to use generic OS ABI framework. + Use set_gdbarch_xxx() calls instead of relying on macros for a + number of calls. + (i386_coff_osabi_sniffer, i386_nlm_osabi_sniffer): New functions. + (_initialize_i386_tdep): Add new 'struct-convcention' command. + Register the various architecture variants defined in this file. + +2002-06-14 Daniel Jacobowitz + + * gdbtypes.h (TYPE_FLAG_VARARGS): Update comment. + (struct main_type): Remove arg_types member. Update comments for + struct field. + (TYPE_ARG_TYPES): Remove. + (TYPE_FN_FIELD_ARGS): Update. + (smash_to_method_type): Update prototype. + + * c-typeprint.c (cp_type_print_method_args): Take method type + instead of argument list. Use new argument layout. Simplify. + (c_type_print_args): Use new argument layout. Simplify. + (c_type_print_base): Update call to cp_type_print_method_args. + * dwarf2read.c (dwarf2_add_member_fn): Remove unneeded type + argument; use die->type instead. Update call to + smash_to_method_type. + (read_structure_scope): Update call to dwarf2_add_member_fn. + * gdbtypes.c (allocate_stub_method): Update comment. + (smash_to_method_type): Take new NARGS and VARARGS arguments. + Use new argument layout. + (check_stub_method): Use new argument layout. Don't count + void as an argument. + (print_arg_types): Update comments. Use new argument layout. + (recursive_dump_type): Don't print arg_types member. + * hpread.c (hpread_read_struct_type): Use new argument layout. + (fixup_class_method_type): Likewise. + (hpread_type_lookup): Likewise. + * stabsread.c (read_type): Update calls to read_args and + smash_to_method_type. + (read_args): Use new argument layout. Simplify. + * valops.c (typecmp): Use new argument layout. Update parameters + and comments. Simplify. + (hand_function_call): Use new argument layout. + (search_struct_method): Update call to typecmp. + (find_overload_match): Use new argument layout. + +2002-06-13 Daniel Jacobowitz + + * NEWS: Mention multithreaded debug support for gdbserver. + +2002-06-13 Daniel Jacobowitz + + * MAINTAINERS: Mention NEWS. + +2002-06-13 Daniel Jacobowitz + + * mips-tdep.c (PROC_SYMBOL): Add warning comment. + (struct mips_objfile_private, compare_pdr_entries): New. + (non_heuristic_proc_desc): Read the ".pdr" section if it + is present. + +2002-06-12 Andrew Cagney + + * arm-tdep.c (arm_push_arguments): Rewrite using a two-pass loop. + (arm_debug): New static variable. + (_initialize_arm_tdep): Add ``set debug arm'' command. + +2002-06-12 Andrew Cagney + + * Makefile.in (sim_arm_h): Define. + (arm-tdep.o): Add $(sim_arm_h) and $(gdb_assert_h). + * arm-tdep.c: Include "gdb/sim-arm.h" and "gdb_assert.h". + (arm_register_sim_regno): New function, map an internal REGNUM + onto a simulator register number. + (arm_gdbarch_init): Set register_sim_regno. + +2002-06-09 Aldy Hernandez + + * MAINTAINERS: Add self. + +2002-06-11 Jim Blandy + + * source.c (source_info): Mention whether the symtab has + information about preprocessor macros. + + Call the command `info macro', not `show macro'. + * macrocmd.c (info_macro_command): Renamed from `show_macro_command'. + Fix error message. + (_initialize_macrocmd): Register `info_macro_command' in + `infolist', not `showlist'. + +2002-06-11 Daniel Jacobowitz + + * mips-tdep.c (MIPS_FPU_TYPE, FP_REGISTER_DOUBLE, MIPS_EABI) + (MIPS_LAST_FP_ARG_REGNUM, MIPS_LAST_ARG_REGNUM) + (MIPS_DEFAULT_SAVED_REGSIZE, MIPS_REGS_HAVE_HOME_P) + (MIPS_DEFAULT_STACK_ARGSIZE, GDB_TARGET_IS_MIPS64) + (MIPS_DEFAULT_MASK_ADDRESS_P): Remove obsolete definitions. Define + unconditionally. + (set_mipsfpu_single_command, set_mipsfpu_double_command) + (set_mipsfpu_none_command): Remove if (GDB_MULTI_ARCH). + (_initialize_mips_tdep): Remove dead code. + * config/mips/tm-irix5.h (MIPS_LAST_ARG_REGNUM) + (MIPS_DEFAULT_STACK_ARGSIZE, MIPS_REGS_HAVE_HOME_P): Remove. + * config/mips/tm-irix6.h (MIPS_LAST_ARG_REGNUM) + (MIPS_DEFAULT_STACK_ARGSIZE, MIPS_REGS_HAVE_HOME_P): Remove. + * config/mips/tm-mips.h (MIPS_EABI, MIPS_LAST_ARG_REGNUM, + MIPS_LAST_FP_ARG_REGNUM): Remove. + +2002-06-11 Michal Ludvig + + * dwarf2cfi.c (unwind_tmp_obstack_init): New. + (unwind_tmp_obstack_free, parse_frame_info) + (update_context, cfi_read_fp, cfi_write_fp) + (cfi_frame_chain, cfi_init_extra_frame_info) + (cfi_virtual_frame_pointer): Use the above function. + * dwarf2cfi.c: Reindented (using 'indent dwarf2cfi.c'). + +2002-06-11 Corinna Vinschen + + * v850-tdep.c (v850_type_is_scalar): New function. + (v850_use_struct_convention): Match current gcc implementation + as close as possible. + (v850_push_arguments): Fix stack_offset handling. Don't write + struct_addr into register. This is done by v850_store_struct_return. + (v850_extract_return_value): Care for structs. + (v850_store_return_value): Ditto. + (v850_store_struct_return): Actually write address. + +2002-06-11 Michal Ludvig + + * x86-64-tdep.c (x86_64_skip_prologue): Fix to work on functions + without debug information too. + +2002-06-10 Andrew Cagney + + * gdbarch.sh (PRINT_FLOAT_INFO): Add frame and ui_file parameters. + Make multi-arch pure. + * gdbarch.h, gdbarch.c: Re-generate. + * arm-tdep.c (arm_print_float_info): Update. + * arch-utils.h (default_print_float_info): Update. + * arch-utils.c (default_print_float_info): Update. + * infcmd.c (float_info): Update call. + +2002-06-10 Andrew Cagney + + * Makefile.in (init.c): Move the call to _initialize_gdbtypes to + the front of the initialize list. + +2002-06-10 Andrew Cagney + + * infrun.c (struct inferior_status): Replace fields + selected_frame_address and selected_level with field + selected_frame_id. + (save_inferior_status): Update. Use get_frame_id. + (struct restore_selected_frame_args): Delete. + (restore_selected_frame): Update. Use frame_find_by_id. + (restore_inferior_status): Update. + + * breakpoint.h (struct breakpoint): Change type of + watchpoint_frame to frame_id. + * breakpoint.c (insert_breakpoints): Use frame_find_by_id. Remove + call to get_current_frame. + (do_enable_breakpoint): Use frame_find_by_id. Remove call to + get_current_frame. + (watchpoint_check): Use frame_find_by_id. + + * frame.h (record_selected_frame): Delete declaration. + * stack.c (record_selected_frame): Delete function. + + * frame.h (struct frame_id): Define. + (get_frame_id): Declare. + (frame_find_by_id): Declare. + * frame.c (frame_find_by_id): New function. + (get_frame_id): New function. + +2002-06-10 Andrey Volkov + + * ser-e7kpc.c: Fix duplicated define and call of + _initialize_ser_e7000pc + +2002-06-09 Daniel Jacobowitz + + * signals/signals.c (target_signal_from_host): Fix #ifdef + SIGRTMIN case. + (do_target_signal_to_host): Likewise. + +2002-06-09 Daniel Jacobowitz + + * mips-tdep.c (mips_find_abi_section): New function. + (mips_gdbarch_init): Call it. + +2002-06-09 Mark Kettenis + + * solib-svr4.c (init_fetch_link_map_offsets): Simply return + legacy_fetch_link_map_offsets. Adjust comment to reflect reality + after Andrew's 2002-06-08 gdbarch change. + +2002-06-09 Mark Kettenis + + * i386-linux-nat.c (suppy_gregset): Don't supply + I386_LINUX_ORIG_EAX_REGNUM if there isn't room for it in GDB's + register cache. + (fill_gregset): Don't fetch it under the same circumstances. + +2002-06-09 Andrew Cagney + + * Makefile.in (callback_h): Define. + (remote_sim_h): Update path to remote-sim.h. + (remote-rdp.o): Add $(callback_h). + (remote-sim.o): Use $(callback_h). + * remote-sim.c: Include "gdb/callback.h" and "gdb/remote-sim.h". + * remote-rdp.c: Include "gdb/callback.h". + +2002-06-09 Mark Kettenis + + * osabi.h (gdb_osabi): Add GDB_OSABI_GO32 and GDB_OSABI_NETWARE. + * osabi.c (gdb_osabi_names): Add "DJGPP" and "NetWare". + +2002-06-08 Andrew Cagney + + * sparcl-tdep.c: Use __CYGWIN__ instead of __CYGWIN32__. + * rdi-share/serpardr.c: Ditto. + * rdi-share/unixcomm.c: Ditto. + * rdi-share/serdrv.c: Ditto. + * rdi-share/hostchan.h: Ditto. + * rdi-share/hostchan.c: Ditto. + * rdi-share/host.h: Ditto. + * rdi-share/devsw.c: Ditto. + + * objfiles.h: Change type of obj_private to void pointer. + * pa64solib.c: Update copyright. Don't include "assert.h", use + strcmp instead of STREQ, use LONGEST, do not use PTR + * somsolib.c: Ditto. + + * config/djgpp/fnchange.lst: Fix problems with bfd/elf32-i386.c, + bfd/elf32-i386qnx.c, bfd/elf32-sh.c, bfd/elf32-sh64-nbsd.c, + bfd/elf64-sh64-nbsd.c bfd/elf64-sh64.c. + +2002-06-08 Andrew Cagney + + * frame.c (GET_SAVED_REGISTER): Delete macro definition. + (default_get_saved_register): Delete function. + * gdbarch.sh (GET_SAVED_REGISTER): Set default to + generic_unwind_get_saved_register. + * gdbarch.h, gdbarch.c: Re-generate. + +2002-06-08 Andrew Cagney + + * gdbarch.sh (FRAME_CHAIN_VALID): Set default to + generic_func_frame_chain_valid. + * gdbarch.h, gdbarch.c: Re-generate. + * blockframe.c (generic_func_frame_chain_valid): Only check + PC_IN_CALL_DUMMY when generic dummy frames. Don't worry about + passing FP to PC_IN_CALL_DUMMY. + Fix PR gdb/360. + +2002-06-08 Andrew Cagney + + * gdbarch.sh (struct gdbarch_data): Add field init_p. + (register_gdbarch_data): Initialize init_p. + (gdbarch_data): Initialize data pointer using the init function. + (init_gdbarch_data): Delete function. + (gdbarch_update_p): Update. + (initialize_non_multiarch): Update. + (struct gdbarch): Add field initialized_p. + * gdbarch.h, gdbarch.c: Re-generate. + +2002-06-07 Michal Ludvig + + * x86-64-linux-nat.c (x86_64_fxsave_offset): New. + (supply_fpregset, fill_fpregset): Don't call i387_*_fxsave, + better do the things actually here. + * x86-64-tdep.c (x86_64_register_name2nr): New. + (x86_64_register_name): Renamed to x86_64_register_nr2name. + (x86_64_gdbarch_init): Respect the above change. + * x86-64-tdep.h (x86_64_register_name2nr) + (x86_64_register_nr2name): Add prototypes. + * config/i386/x86-64linux.mt (TDEPFILES): Remove i387-tdep.o. + +2002-06-06 Michael Snyder + + * d10v-tdep.c (d10v_push_arguments): Handle struct_return. + Delete extra braces and re-indent. + (d10v_store_return_value): Char return values + must be shifted over by one byte in R0. + (d10v_extract_return_value): Delete extra braces, re-indent. + +2002-06-06 Elena Zannoni + + * d10v-tdep.c (d10v_read_sp, d10v_read_fp): Add prototype. + (d10v_register_virtual_type): Make $fp and $sp be pointer to data. + (d10v_integer_to_address): Rewrite. + (d10v_frame_init_saved_regs): When reading fp and sp registers use + the d10v specific functions which take care of converting to the + correct space. + +2002-06-06 Elena Zannoni + + * config/djgpp/fnchange.lst: Add testsuite files altivec-abi.c, + altivec-abi.exp, altivec-regs.c, altivec-regs.exp. + +2002-06-02 Andrew Cagney + + * config/alpha/nm-linux.h: Add "config/" prefix to tm, nm and xm + includes. + * config/tm-linux.h: Ditto. + * config/alpha/tm-alphalinux.h: Ditto. + * config/arm/nm-linux.h, config/arm/tm-linux.h: Ditto. + * config/arm/xm-nbsd.h, config/i386/nm-gnu.h: Ditto. + * config/i386/nm-i386lynx.h, config/i386/nm-i386sol2.h: Ditto. + * config/i386/nm-i386v4.h, config/i386/nm-i386v42mp.h: Ditto. + * config/i386/nm-linux.h, config/i386/nm-m3.h: Ditto. + * config/i386/nm-ptx4.h, config/i386/nm-x86-64.h: Ditto. + * config/i386/tm-i386gnu.h, config/i386/tm-i386lynx.h: Ditto. + * config/i386/tm-i386m3.h, config/i386/tm-i386sco5.h: Ditto. + * config/i386/tm-i386v4.h, config/i386/tm-linux.h: Ditto. + * config/i386/tm-ptx4.h, config/i386/tm-vxworks.h: Ditto. + * config/i386/xm-i386v4.h, config/i386/xm-nbsd.h: Ditto. + * config/i386/xm-ptx.h, config/i386/xm-ptx4.h: Ditto. + * config/i960/tm-vx960.h, config/ia64/nm-aix.h: Ditto. + * config/ia64/nm-linux.h, config/ia64/tm-aix.h: Ditto. + * config/ia64/tm-linux.h, config/ia64/xm-aix.h: Ditto. + * config/m68k/nm-linux.h, config/m68k/nm-m68klynx.h: Ditto. + * config/m68k/nm-sysv4.h, config/m68k/tm-linux.h: Ditto. + * config/m68k/tm-m68klynx.h, config/m68k/tm-m68kv4.h: Ditto. + * config/m68k/tm-sun2os4.h, config/m68k/tm-sun3os4.h: Ditto. + * config/m68k/tm-vx68.h, config/m68k/xm-m68kv4.h: Ditto. + * config/m68k/xm-nbsd.h, config/m88k/nm-delta88v4.h: Ditto. + * config/m88k/tm-delta88v4.h, config/m88k/xm-delta88v4.h: Ditto. + * config/mips/nm-irix5.h, config/mips/nm-linux.h: Ditto. + * config/mips/tm-linux.h, config/mips/tm-mips64.h: Ditto. + * config/mips/tm-mipsm3.h, config/mips/tm-mipsv4.h: Ditto. + * config/mips/tm-vxmips.h, config/mips/xm-irix5.h: Ditto. + * config/mips/xm-mipsv4.h, config/ns32k/xm-nbsd.h: Ditto. + * config/pa/nm-hppao.h, config/powerpc/nm-linux.h: Ditto. + * config/powerpc/tm-linux.h, config/powerpc/tm-vxworks.h: Ditto. + * config/powerpc/xm-aix.h, config/rs6000/nm-rs6000ly.h: Ditto. + * config/rs6000/tm-rs6000ly.h, config/rs6000/xm-aix4.h: Ditto. + * config/sh/tm-linux.h, config/sparc/nm-linux.h: Ditto. + * config/sparc/nm-sparclynx.h, config/sparc/nm-sun4sol2.h: Ditto. + * config/sparc/tm-linux.h, config/sparc/tm-sp64linux.h: Ditto. + * config/sparc/tm-sp64sim.h, config/sparc/tm-sparclynx.h: Ditto. + * config/sparc/tm-sun4os4.h, config/sparc/tm-sun4sol2.h: Ditto. + * config/sparc/tm-vxsparc.h, config/sparc/xm-sun4sol2.h: Ditto. + +2002-05-04 Aidan Skinner + + * ada-exp.tab.c: New file + * ada-exp.y: New file + * ada-lang.c: New file + * ada-lang.h: New file + * ada-lex.c: New file + * ada-lex.l: New file + * ada-tasks.c: New file + * ada-typeprint.c: New file + * ada-valprint.c: New file + +2002-06-02 Jason Thorpe + + * ppcnbsd-tdep.c (ppcnbsd_init_abi): Don't set + use_struct_convention to ppc_sysv_abi_broken_use_struct_convention. + +2002-06-02 Jason Thorpe + + * config/rs6000/aix4.mt (TDEPFILES): Use ppc-sysv-tdep.o + insetead of ppc-linux-tdep.o. + * config/rs6000/rs6000.mt (TDEPFILES): Likewise. + * config/rs6000/rs6000lynx.mt (TDEPFILES): Likewise. + +2002-06-02 Andrew Cagney + + 2002-05-07 Christian Groessler + * z8k-tdep.c (z8k_print_register_hook): Fix display of 32 and 64 + bit register contents for little endian hosts. + +2002-06-01 Andrew Cagney + + * MAINTAINERS: Mention that any `HP/UX reader' can be changed by + any maintainer. + +2002-06-01 Andrew Cagney + + * gdbarch.h: Regenerate. + +2002-06-01 Andrew Cagney + + * MAINTAINERS: Add everyone to write-after-approval list. + +2002-06-01 Andrew Cagney + + * stack.c (frame_info): Use frame_register_unwind instead of + saved_regs. Mention when the SP is on the stack or in a register. + + * frame.h (frame_register_unwind_ftype): Define. Document. + (struct frame_info): Add field register_unwind and + register_unwind_cache. + (frame_register_unwind): Declare. + (generic_unwind_get_saved_register): Declare. + + * frame.c (frame_register_unwind): New function. + (generic_unwind_get_saved_register): New function. + + * blockframe.c (generic_call_dummy_register_unwind): New function. + (frame_saved_regs_register_unwind): New function. + (set_unwind_by_pc): New function. + (create_new_frame): New function. + (get_prev_frame): New function. + +2002-05-30 Andrew Cagney + + * a29k-share/: Delete directory. + * remote-vx29k.c: Delete file. + +2002-05-30 Jason Thorpe + + * config/djgpp/fnchange.lst: Add ns32knbsd-nat.c, ns32knbsd-tdep.c, + ppcnbsd-nat.c, ppcnbsd-tdep.c, sparcnbsd-nat.c, and sparcnbsd-tdep.c. + +2002-05-30 Jason Thorpe + + * Makefile.in (ALLDEPFILES): Add sparc64nbsd-nat.c, + sparcnbsd-nat.c, and sparcnbsd-tdep.c. + (sparc64nbsd-nat.o) + (sparcnbsd-nat.o) + (sparcnbsd-tdep.o): New dependency lists. + * NEWS: Note new UltraSPARC NetBSD native configuration. + * configure.host (sparc64-*-netbsd*): New host. + * configure.tgt (sparc-*-netbsdelf*) + (sparc-*-netbsd*): Set gdb_target to nbsd. + (sparc64-*-netbsd*): New target. + * sparc64nbsd-nat.c: New file. + * sparcnbsd-nat.c: New file. + * sparcnbsd-tdep.c: New file. + * sparcnbsd-tdep.h: New file. + * config/sparc/nbsd.mt: New file. + * config/sparc/nbsd64.mh: New file. + * config/sparc/nbsd64.mt: New file. + * config/sparc/nbsdaout.mh (NATDEPFILES): Remove corelow.o, + sparc-nat.o, and solib.o. Add sparcnbsd-nat.o. + (HOST_IPC): Remove. + * config/sparc/nbsdaout.mt: Remove. + * config/sparc/nbsdelf.mh (NATDEPFILES): Remove corelow.o, + sparc-nat.o, and solib.o. Add sparcnbsd-nat.o. + (HOST_IPC): Remove. + * config/sparc/nbsdelf.mt: Remove. + * config/sparc/nm-nbsd.h: Update copyright years. Remove all + sparc-nat.c compatiblity defines. + * config/sparc/tm-nbsd.h: Update copyright years. Include solib.h. + (GDB_MULTI_ARCH): Set to GDB_MULTI_ARCH_PARTIAL. + * config/sparc/tm-nbsd64.h: New file. + * config/sparc/tm-nbsdaout.h: Remove. + * config/sparc/xm-nbsd.h: Remove. + +2002-05-30 Jason Thorpe + + * Makefile.in (sparc-tdep.o): Add osabi.h to dependency list. + * sparc-tdep.c: Include osabi.h. + (gdbarch_tdep): Add osabi member. + (_initialize_sparc_tdep): Use gdbarch_register. + (sparc_gdbarch_init): Use generic OS ABI framework. + (sparc_dump_tdep): New function. + +2002-05-30 Kevin Buettner + + * corefile.c (do_captured_read_memory_integer): Return non-zero + result. + (safe_read_memory_integer): Copy result of memory read when + status is non-zero. Also, add comments. + +2002-05-20 Jason Thorpe + + * Makefile.in (ppc_tdep_h): Define. + (ppc-linux-nat.o) + (ppc-linux-tdep.o) + (rs6000-tdep.o): Use $(ppc_tdep_h). + (ppc-sysv-tdep.o) + (ppcnbsd-nat.o) + (ppcnbsd-tdep.o): New dependency lists. + * ppc-tdep.h: Use generic OS ABI framework. + * ppc-linux-tdep.c (_initialize_ppc_linux_tdep) + (ppc_linux_init_abi): New functions. + (ppc_sysv_abi_broken_use_struct_convention) + (ppc_sysv_abi_use_struct_convention) + (ppc_sysv_abi_push_arguments): Move to... + * ppc-sysv-tdep.c: ...here. + * ppcnbsd-nat.c: Don't include gdbcore.h and regcache.h. + * rs6000-tdep.c (process_note_abi_tag_sections) + (get_elfosabi): Remove. + (rs6000_gdbarch_init): Use generic OS ABI framework. + (rs6000_dump_tdep): New function. + (_initialize_rs6000_tdep): Use gdbarch_register. + * config/powerpc/linux.mt (TDEPFILES): Add ppc-sysv-tdep.o. + * config/powerpc/nbsd.mh (NATDEPFILES): Remove solib-legacy.o. + * config/powerpc/aix.mt (TDEPFILES): Use ppc-sysv-tdep.o instead + of ppc-linux-tdep.o. + * config/powerpc/nbsd.mt (TDEPFILES): Likewise. + * config/powerpc/ppc-eabi.mt (TDEPFILES): Likewise. + * config/powerpc/ppc-sim.mt (TDEPFILES): Likewise. + * config/powerpc/ppcle-eabi.mt (TDEPFILES): Likewise. + * config/powerpc/ppcle-sim.mt (TDEPFILES): Likewise. + * config/powerpc/vxworks.mt (TDEPFILES): Likewise. + +2002-05-29 Jim Blandy + + * macroscope.c (default_macro_scope): Put `void' in empty argument + list. + +2002-05-29 Andrew Cagney + + * Makefile.in (arch-utils.o): Add $(sim_regno_h). + * arch-utils.c: Include "sim-regno.h". + * gdbarch.sh: Don't include "sim-regno.h". + * gdbarch.h, gdbarch.c: Regenerate. + * sim-regno.h (legacy_register_sim_regno): Move declaration from + here. + * arch-utils.h (legacy_register_sim_regno): To here. + * remote-sim.c (legacy_register_sim_regno): Move function from + here. + * arch-utils.c (legacy_register_sim_regno): To here. + +2002-05-28 Andrew Cagney + + * sim-regno.h: New file. + * Makefile.in (sim_regno_h): Define. + (d10v-tdep.o, remote-sim.o): Add dependency on $(sim_regno_h). + * remote-sim.c: Include "sim-regno.h" and "gdb_assert.h". + (legacy_register_sim_regno): New function. + (one2one_register_sim_regno): New function. + (gdbsim_fetch_register): Rewrite. + (gdbsim_store_register): Only store a register when + REGISTER_SIM_REGNO is valid. + * d10v-tdep.c: Include "sim-regno.h". + (d10v_ts2_register_sim_regno): Add legacy_regiter_sim_regno check. + (d10v_ts3_register_sim_regno): Ditto. + * gdbarch.sh: Include "sim-regno.h". + (REGISTER_SIM_REGNO): Set default to legacy_register_sim_regno. + * gdbarch.h, gdbarch.c: Regenerate. + * arch-utils.h (default_register_sim_regno): Delete declaration. + * arch-utils.c (default_register_sim_regno): Delete function. + +2002-05-28 Jason Thorpe + + * ppcnbsd-nat.c: Rewrite. + * ppcnbsd-tdep.c: New file. + * ppcnbsd-tdep.h: New file. + * config/powerpc/nbsd.mh (NATDEPFILES): Remove corelow.o, + solib.o, and solib-svr4.o. + * config/powerpc/nbsd.mt (TDEPFILES): Add ppcnbsd-tdep.o, + nbsd-tdep.o, and corelow.o. + +2002-05-28 Andrew Cagney + + * MAINTAINERS (--enable-gdb-build-warnings): Rewrite script to use + `tr' and `sed'. Mention that `broken' targets are not expected to + build. + +2002-05-27 Michal Ludvig + + * x86-64-tdep.c (x86_64_skip_prologue): Remove obsolete note. + Let PC point right after the prologue before looking up symbols. + +2002-05-27 Martin M. Hunt + + * i386-tdep.c (i386_register_virtual_type): Return + builtin_type_vec128i for SSE registers. + + * gdbtypes.h (builtin_type_vec128i): Declare. + + * gdbtypes.c (build_builtin_type_vec128i): New function. + (builtin_type_v2_double, builtin_type_v4_int64): New types. + (builtin_type_vec128i): New type for SSE2 128-bit registers. + (build_gdbtypes): Initialize new builtin vector types. + (_initialize_gdbtypes): Register new vector types with gdbarch. + +2002-05-26 Jason Thorpe + + * MAINTAINERS: ns32k is not longer an obsolete candidate, + since it has been multi-arch'd. + * NEWS: Note that ns32k-*-* is now partial multi-arch. + Move Alpha and VAX multi-arch news entries to same section + as other multi-arch news. + +2002-05-26 Jason Thorpe + + * ns32k-tdep.c: include gdbtypes.h, inferior.h, regcache.h, + target.s, arch-utils.h, ns32k-tdep.h. Make many functions + static. Rename some register numbers to put them in ns32k-tdep + private namespace. + (ns32k_get_saved_register, ns32k_gdbarch_init_32082, + ns32k_gdbarch_init_32382, ns32k_gdbarch_init, ns32k_dump_tdep): New + functions. + (_initialize_ns32k_tdep): Use gdbarch_register. + * ns32k-tdep.h: New file. + * ns32knbsd-tdep.c: New file. + * config/ns32k/nbsdaout.mt (TDEPFILES): Add ns32knbsd-tdep.o. + * config/ns32k/tm-nbsd.h: Include "ns32k/tm-ns32k.h". + (IN_SOLIB_CALL_TRAMPOLINE, REGISTER_NAME, NUM_REGS, + REGISTER_BYTES, REGISTER_BYTE): Remove. + * config/ns32k/tm-ns32k.h: New file. + * config/ns32k/tm-umax.h: Remove. + +2002-05-26 Jason Thorpe + + * ns32k-tdep.c (ns32k_saved_pc_after_call, + ns32k_store_struct_return, ns32k_extract_return_value, + ns32k_store_return_value, ns32k_extract_struct_value_address): New + functions. + * config/ns32k/tm-umax.h (SAVED_PC_AFTER_CALL): Define as + ns32k_saved_pc_after_call. + (STORE_STRUCT_RETURN): Define as ns32k_store_struct_return. + (EXTRACT_RETURN_VALUE): Define as ns32k_extract_return_value. + (STORE_RETURN_VALUE): Define as ns32k_store_return_value. + (EXTRACT_STRUCT_VALUE_ADDRESS): Define as + ns32k_extract_struct_value_address. + +2002-05-26 Jason Thorpe + + * ns32k-tdep.c (ns32k_call_dummy_words, sizeof_ns32k_call_dummy_words, + ns32k_fix_call_dummy): New. + * config/ns32k/tm-umax.h (CALL_DUMMY_WORDS): Define as + ns32k_call_dummy_words. + (SIZEOF_CALL_DUMMY_WORDS): Define as sizeof_ns32k_call_dummy_words. + (CALL_DUMMY, CALL_DUMMY_LENGTH, CALL_DUMMY_ADDR, + CALL_DUMMY_NARGS): Remove. + (FIX_CALL_DUMMY): Define as ns32k_fix_call_dummy. + +2002-05-26 Jason Thorpe + + * ns32k-tdep.c (ns32k_breakpoint_from_pc, ns32k_frame_chain, + ns32k_frame_saved_pc, ns32k_frame_args_address, + ns32k_frame_locals_address, ns32k_frame_init_saved_regs, + ns32k_push_dummy_frame, ns32k_pop_frame): New functions. + * config/ns32k/tm-nbsd.h (FRAME_SAVED_PC): Remove. + * config/ns32k/tm-umax.h (INNER_THAN): Define as core_addr_lessthan. + (BREAKPOINT_FROM_PC): Define as ns32k_breakpoint_from_pc. + (BREAKPOINT): Remove.. + (FRAME_CHAIN): Define as ns32k_frame_chain. + (FRAME_SAVED_PC): Define as ns32k_frame_saved_pc. + (FRAME_ARGS_ADDRESS): Define as ns32k_frame_args_address. + (FRAME_LOCALS_ADDRESS): Define as ns32k_frame_locals_address. + (FRAME_FIND_SAVED_REGS): Remove. + (FRAME_INIT_SAVED_REGS): Define as ns32k_frame_init_saved_regs. + (PUSH_DUMMY_FRAME): Define as ns32k_push_dummy_frame. + (POP_FRAME): Define as ns32k_pop_frame. + +2002-05-26 Jason Thorpe + + * ns32k-tdep.c (ns32k_register_byte_32082, + ns32k_register_byte_32382, ns32k_register_raw_size, + ns32k_register_virtual_size, ns32k_register_virtual_type): New + functions. + * config/ns32k/tm-nbsd.h (REGISTER_BYTE): Define as + ns32k_register_byte_32382. + * config/ns32k/tm-umax.h: Update copyright years. + (REGISTER_BYTE): Define as ns32k_register_byte_32082. + (REGISTER_RAW_SIZE): Define as ns32k_register_raw_size. + (REGISTER_VIRTUAL_SIZE): Define as ns32k_register_virtual_size. + (REGISTER_VIRTUAL_TYPE): Define as ns32k_register_virtual_type. + (ns32k_get_enter_addr): Fix prototype. + +2002-05-26 Jason Thorpe + + * ns32k-tdep.c: Update copyright years. + (ns32k_register_name_32082): New function. + (ns32k_register_name_32382): Ditto. + * config/ns32k/tm-nbsd.h (REGISTER_NAMES): Remove. + (REGISTER_NAME): Define as ns32k_register_name_32382. + * config/ns32k/tm-umax.h (REGISTER_NAMES): Remove. + (REGISTER_NAME): Define as ns32k_register_name_32082. + +2002-05-24 Jim Blandy + + * dwarf2read.c (free_line_header): Use xfree, not free. + +2002-05-24 Jason Thorpe + + * config/djgpp/fnchange.lst: Add alphabsd-nat.c, + alphabsd-tdep.c, mipsnbsd-nat.c, and mipsnbsd-tdep.c + +2002-05-23 Andrew Cagney + + * PROBLEMS: Mention s390 and FreeBSD 4.4 build problems. + +2002-05-23 Andrew Cagney + + From Ross Alexander at NEC Europe: + * config/pa/hpux11w.mh (NATDEPFILES): Add solib.o. + +2002-05-23 Michael Snyder + + * cli/cli-dump.c (restore_command): Use parse_and_eval_long + for input, rather than parse_and_eval_address. + +2002-05-23 Andrew Cagney + + * d10v-tdep.c: Include "gdb/sim-d10v.h" instead of "sim-d10v.h". + * Makefile.in (sim_d10v_h): Update definition. + +2002-05-24 Andrew Cagney + + * d10v-tdep.c (d10v_gdbarch_init): Revert old code included in + change `2002-05-22 Michael Snyder' below. + (d10v_push_arguments): Ditto. + (d10v_extract_return_value): Ditto. + +2002-05-23 Jim Blandy + + * macrotab.c (check_for_redefinition): Don't complain if the new + definition is the same as the previous one. Take more arguments + to allow the comparison. + (macro_define_object, macro_define_function): Pass more arguments + to check_for_redefinition. + +2002-05-22 Michael Snyder + + * d10v-tdep.c: Change a few macros to enums for ease of debugging. + (d10v_frame_chain_valid): Add PC_IN_CALL_DUMMY clause. + (d10v_frame_saved_pc): Add PC_IN_CALL_DUMMY clause. + (d10v_frame_chain): Bail immediately if PC_IN_CALL_DUMMY. + Don't bail if return_pc is PC_IN_CALL_DUMMY. + Add a temp variable to save a call (and a memory read). + (d10v_init_extra_frame_info): Get fi->pc from callee's return_pc + if possible (so that PC_IN_CALL_DUMMY will work). + +2002-05-22 Corinna Vinschen + + * MAINTAINERS: Remove status `OBSOLETE' from v850. + +2002-05-22 Michal Ludvig + + * dwarf2cfi.c (frame_state_for): Added safety check for a valid + fde->cie_ptr. + (dwarf2_build_frame_info): Corrected handling of eh_frame. + (dwarf2_build_frame_info): Add offset to fde->initial_location + so that frames of shared libraries are mapped correctly. + (execute_stack_op): Change type of 'result' from ULONGEST to + CORE_ADDR. + +2002-05-22 Jason Thorpe + + * config/alpha/tm-nbsd.h: Include solib.h. + +2002-05-22 Jason Thorpe + + * alphanbsd-tdep.c (alphanbsd_sigtramp_offset): Don't make + assumptions about the host's byte order. + +2002-05-22 Jason Thorpe + + * Makefile.in (alphanbsd-tdep.o, shnbsd-tdep.o): Add solib-svr4.h + to dependency list. + * alphanbsd-tdep.c: Include solib-svr4.h. + * shnbsd-tdep.c: Ditto. + +2002-05-22 Jason Thorpe + + * Makefile.in (armnbsd-tdep.o): Add solib-svr4.h and + nbsd-tdep.h to dependency list. + * configure.host (arm*-*-netbsdelf*, arm*-*-netbsd*, + i[3456]86-*-netbsdaout*, i[3456]86-*-netbsd*, m68*-*-netbsd*, + ns32k-*-netbsd*, sparc-*-netbsdaout*, sparc-*-netbsd*): Use + nbsdaout.mh and nbsdelf.mh consistently. + * configure.tgt (i[3456]86-*-netbsd*, m68*-*-netbsd*, + ns32k-*-netbsd*, sparc-*-netbsdelf*, sparc-*-netbsd*) Use + nbsdaout.mt and nbsdelf.mh consistently. + * armnbsd-tdep.c: Include nbsd-tdep.h and solib-svr4.h. + (arm_netbsd_elf_init_abi): Use set_solib_svr4_fetch_link_map_offsets + to set nbsd_ilp32_solib_svr4_fetch_link_map_offsets. + * config/nm-nbsd.h: Garbage-collect SVR4_SHARED_LIBS. Move + a.out shared library stuff from here... + * config/nm-nbsdaout.h: ...to here. + * config/tm-nbsd.h: Remove. + * config/alpha/nm-nbsd.h (SVR4_SHARED_LIBS): Remove. + * config/arm/nbsd.mh: Remove. + * config/arm/nbsd.mt (TDEPFILES): Remove solib-sunos.o, add + nbsd-tdep.o. + * config/arm/nbsdaout.mh: New file. + * config/arm/nbsdelf.mh: New file. + * config/arm/nm-nbsdaout.h: New file. + * config/i386/nbsd.mh: Remove. + * config/i386/nbsd.mt: Remove. + * config/i386/nbsdaout.mh: New file. + * config/i386/nbsdaout.mt: New file. + * config/i386/nbsdelf.mh (NAT_FILE): Use nm-nbsd.h. + * config/i386/nbsdelf.mt (TM_FILE): Use tm-nbsd.h. + * config/i386/nm-nbsd.h (REGISTER_U_ADDR, + i386_register_u_addr): Remove. + * config/i386/nm-nbsdaout.h: New file. + * config/i386/nm-nbsdelf.h: Remove. + * config/i386/tm-nbsd.h: Don't include config/tm-nbsd.h. + (USE_STRUCT_CONVENTION): Remove. + * config/i386/tm-nbsdaout.h: New file. + * config/i386/tm-nbsdelf.h: Remove. + * config/m68k/nbsd.mh: Remove. + * config/m68k/nbsd.mt: Remove. + * config/m68k/nbsdaout.mh: New file. + * config/m68k/nbsdaout.mt: New file. + * config/m68k/nm-nbsd.h: Use config/nm-nbsd.h. + * config/m68k/nm-nbsdaout.h: New file. + * config/m68k/tm-nbsd.h: Don't include config/tm-nbsd.h. + (IN_SOLIB_CALL_TRAMPOLINE): Define. + * config/ns32k/nbsd.mh: Remove. + * config/ns32k/nbsd.mt: Remove. + * config/ns32k/nbsdaout.mh: New file. + * config/ns32k/nbsdaout.mt: New file. + * config/ns32k/nm-nbsd.h: Include config/nm-nbsd.h. + * config/ns32k/nm-nbsdaout.h: New file. + * config/ns32k/tm-nbsd.h: Don't include config/tm-nbsd.h. + (IN_SOLIB_CALL_TRAMPOLINE): Define. + * config/powerpc/nm-nbsd.h: Include config/nm-nbsd.h. + (SVR4_SHARED_LIBS): Remove. + * config/powerpc/tm-nbsd.h: Dont' include config/tm-nbsd.h. + * config/sparc/nbsd.mh: Remove. + * config/sparc/nbsd.mt: Remove. + * config/sparc/nbsdaout.mh: New file. + * config/sparc/nbsdaout.mt: New file. + * config/sparc/nbsdelf.mh (NAT_FILE): Use nm-nbsd.h. + * config/sparc/nbsdelf.mt: New file. + * config/sparc/nm-nbsdaout.h: New file. + * config/sparc/nm-nbsdelf.h: Remove. + * config/sparc/tm-nbsd.h: Don't include config/tm-nbsd.h. + * config/sparc/tm-nbsdaout.h: New file. + +2002-05-21 Jason Thorpe + + * Makefile.in (ALLDEPFILES): Add mipsnbsd-nat.c and + mipsnbsd-tdep.c + (mipsnbsd-nat.o, mipsnbsd-tdep.o): New dependency lists. + +2002-05-21 Jason Thorpe + + * Makefile.in (ALLDEPFILES): Add shnbsd-tdep.c and + shnbsd-nat.c. + (shnbsd-tdep.o, shnbsd-nat.o): New dependency lists. + +2002-05-21 Jason Thorpe + + * NEWS: Note new MIPS NetBSD native configuration. + * configure.host (mips*-*-netbsd*): New host. + * configure.tgt (mips*-*-netbsd*): New target. + * mipsnbsd-nat.c: New file. + * mipsnbsd-tdep.c: New file. + * mipsnbsd-tdep.h: New file. + * config/mips/nbsd.mh: New file. + * config/mips/nbsd.mt: New file. + * config/mips/nm-nbsd.h: New file. + * config/mips/tm-nbsd.h: New file. + +2002-05-21 Jason Thorpe + + * Makefile.in (SFILES): Add osabi.c. + (COMMON_OBS): Add osabi.o. + (osabi.o): New dependency list. + * osabi.c: New file. + * osabi.h: New file. + * doc/gdbint.texinfo: Document new generic OS ABI framework. + + * Makefile.in (alpha_tdep_h): Define and use instead of + alpha-tdep.h. + * alpha-tdep.c (alpha_abi_names, process_note_abi_tag_sections, + get_elfosabi, alpha_abi_handler_list, alpha_gdbarch_register_os_abi): + Remove. + (alpha_gdbarch_init, alpha_dump_tdep): Use generic OS ABI framework. + * alpha-tdep.h: Include osabi.h. + (alpha_abi): Remove. + (gdbarch_tdep): Use generic OS ABI framework. + * alpha-linux-tdep.c (_initialize_alpha_linux_tdep): Use + gdbarch_register_osabi. + * alpha-osf1-tdep.c (_initialize_alpha_osf1_tdep): Likewise. + * alphafbsd-tdep.c (_initialize_alphafbsd_tdep): Likewise. + * alphanbsd-tdep.c (_initialize_alphanbsd_tdep): Likewise. + + * Makefile.in (sh_tdep_h): Add osabi.h. + * sh-tdep.h (sh_osabi): Remove. + (gdbarch_tdep): Use generic OS ABI framework. + * sh-tdep.c (sh_osabi_names, process_note_abi_tag_sections, + sh_osabi_handler_list, sh_gdbarch_register_os_abi): Remove. + (sh_gdbarch_init, sh_dump_tdep): Use generic OS ABI framework. + * shnbsd-tdep.c (_initialize_shnbsd_tdep): Use gdbarch_register_osabi. + + * Makefile.in (arm_tdep_h): Define and use instead of arm-tdep.h. + * arm-linux-tdep.c (_initialize_arm_linux_tdep): Use + gdbarch_register_osabi. + * arm-tdep.c (arm_abi_names, process_note_abi_tag_sections, + arm_abi_handler_list, arm_gdbarch_register_os_abi): Remove. + (get_elfosabi): Rename to... + (arm_elf_osabi_sniffer): ...this. Adjust to use generic OS + ABI framework support routines. + (arm_gdbarch_init): Use generic OS ABI framework. + (arm_dump_tdep): Likewise. + (_initialize_arm_tdep): Likewise. + * arm-tdep.h: Include osabi.h. + (arm_abi): Remove. + (gdbarch_tdep): Remove arm_abi and abi_name members. Add + osabi member. + (arm_gdbarch_register_os_abi): Remove prototype. + * armnbsd-tdep.c (arm_netbsd_aout_osabi_sniffer): New function. + (_initialize_arm_netbsd_tdep): Use gdbarch_register_osabi. + + * Makefile.in (mips-tdep.o): Add osabi.h to dependency list. + * mips-tdep.c: Include osabi.h. + (gdbarch_tdep, mips_gdbarch_init, mips_dump_tdep): Use generic + OS ABI framework. + +2002-05-20 Kazu Hirata + + * h8300-tdep.c: Fix formatting. + +2002-05-20 Elena Zannoni + + * rs6000-tdep.c (rs6000_do_registers_info): Simplify code for + printing vector registers. + +2002-05-19 Andrew Cagney + + From Fernando Nasser: + * remote.c (remote_async_open_1): Re-throw the exception when the + connection fails. + (remote_cisco_open): Ditto. + (remote_open_1): Ditto. + +2002-05-19 Andrew Cagney + + * remote.c (remote_start_remote_dummy): Add uiout parameter. + (remote_start_remote): Add uiout parameter. Pass through to + remote_start_remote_dummy. + (remote_open_1): Use catch_exception instead of catch_errors. + (remote_async_open_1): Ditto. + (remote_cisco_open): Ditto. + +2002-05-19 Andrew Cagney + + * remote.c (remote_start_remote): Replace PTR with void pointer. + (sigint_remote_twice_token, sigint_remote_token): Ditto. Make + static. + +2002-05-18 Andrew Cagney + + * gdb_indent.sh: Allow the script to be run in the sim directory. + +2002-05-18 Mark Kettenis + + * config/i386/nm-cygwin.h (NO_PTRACE_H): Remove define. + * config/i386/nm-go32.h (NO_PTRACE_H): Remove define. + + * corelow.c (core_open): Only call set_gdbarch_from_file if + exec_bfd is NULL. + +2002-05-17 Andrey Volkov + + * h8300-tdep.c: Add support of EXR register + * config/h8300/tm-h8300.h: Ditto. + +2002-05-17 Andrey Volkov + + * h8300-tdep.c: Add additional CCR flags (I,UI,H,U) + +2002-05-17 Andrey Volkov + + * h8300-tdep.c: Change literal regnums to REGNO. + +2002-05-17 Jim Blandy + + * NEWS: Note addition of macro support. + + Expand preprocessor macros in C expressions. + * c-lang.h: #include "macroexp.h", for macro_lookup_ftype. + (scan_macro_expansion, scanning_macro_expansion, + finished_macro_expansion): New function declarations. + (expression_macro_lookup_func, expression_macro_lookup_baton): New + variable declarations. + * parser-defs.h (expression_context_pc): New declaration. + * parse.c (expression_context_pc): New variable. + (parse_exp_1): Set expression_context_pc, as well as + expression_context_block. + * c-exp.y (yylex): If we're not already reading the result of a + macro expansion, try to macro-expand the next token. When we're + done scanning a macro expansion, switch back to the mainline text. + Commas and `if's in a macro's expansion don't terminate the input. + * c-lang.c: #include "macroscope.h" and "gdb_assert.h". + (macro_original_text, macro_expanded_text, + expression_macro_lookup_func, expression_macro_lookup_baton): New + variables. + (scan_macro_expansion, scanning_macro_expansion, + finished_macro_expansion, scan_macro_cleanup, null_macro_lookup, + c_preprocess_and_parse): New functions. + (c_language_defn, cplus_language_defn, asm_language_defn): Call + c_preprocess_and_parse, instead of c_parse. + * Makefile.in (c_lang_h): Note that this #includes macroexp.h. + (c-lang.o): Note dependency on macroscope.h and gdb_assert.h. + +Fri May 17 14:26:19 2002 J"orn Rennecke + + * sh-tdep.c (gdb_print_insn_sh64): Delete. + (gdb_print_insn_sh): Just set info->endian and use print_insn_sh. + (sh_gdbarch_init): Always use gdb_print_insn_sh. + +2002-05-17 Corinna Vinschen + + * NEWS: Add section for multi-arched targets. Add v850 to that section. + +2002-05-17 Jason Thorpe + + * Makefile.in (sh_tdep_h): Define and use. + * config/sh/tm-sh.h (sh_osabi, sh_abi, gdbarch_tdep, + register enum): Move to... + * * sh-tdep.h: ...here. + * sh-tdep.c: Include sh-tdep.h. + * sh3-rom.c: Likewise. + * shnbsd-tdep.c: Likewise. + +2002-05-16 Michael Snyder + + * arm-tdep.c: Spelling fix in comment. + +2002-05-16 Jim Blandy + + Add commands for manually expanding macros and showing their + definitions. + * macrocmd.c, macroscope.c, macroscope.h: New files. + * Makefile.in (SFILES): Add macrocmd.c, macroscope.c. + (macroscope_h): New variable. + (HFILES_NO_SRCDIR): Add macroscope.h. + (COMMON_OBS): Add macrocmd.o, macroscope.o. + (macroscope.o, macrocmd.o): New rules. + + Teach the Dwarf 2 reader to read macro information. + * dwarf2read.c: #include "macrotab.h". + (dwarf_macinfo_buffer): New variable. + (struct dwarf2_pinfo): New members: dwarf_macinfo_buffer, and + dwarf_macinfo_size. + (DWARF_MACINFO_BUFFER, DWARF_MACINFO_SIZE): New macros. + (dwarf2_missing_macinfo_section, dwarf2_macros_too_long, + dwarf2_macros_not_terminated, dwarf2_macro_outside_file, + dwarf2_macro_unmatched_end_file, dwarf2_macro_malformed_definition, + dwarf2_macro_spaces_in_definition): New complaints. + (dwarf2_has_info): Initialize dwarf_macinfo_offset. + (dwarf2_build_psymtabs): Read the .dwarf_macinfo section. + (dwarf2_build_psymtabs_hard): Record the buffer and its size in + the partial symbol table. + (psymtab_to_symtab_1): Set the macinfo buffer and size globals + from what's recorded in the partial symbol table. + (read_file_scope): If the compilation unit has a + `DW_AT_macro_info' attribute, read its macro information. + * Makefile.in (dwarf2read.o): Depend on macrotab.h. + +2002-05-16 Daniel Jacobowitz + + Fix PR gdb/546 + * ser-tcp.c: Don't include . + +2002-05-16 Stephane Carrez + + * MAINTAINERS: Update my email address. + +2002-05-16 Richard Earnshaw + + * config/arm/nm-nbsd.h: Use "config/nm-nbsd.h" to include generic + include file of the same name. + +2002-05-16 Corinna Vinschen + + * configure.tgt: Mark v850 as multi-arched. + * config/v850/tm-v850.h: Remove file. + * config/v850/v850.mt: Eliminate TM_FILE. + +2002-05-16 Corinna Vinschen + + * v850-tdep.c: Full multi-arch. + * config/v850/tm-v850.h: Eliminate or move to v850-tdep.c everything. + Define GDB_MULTI_ARCH to 2. + +2002-05-16 Pierre Muller + + * p-exp.y (current_type): New static variable. + Carries the type of the expression at the position that is parsed. + (push_current_type, pop_current_type): Two new functions. Used + to store/restore current_type in expression on specific tokens. + (search_field): New static variable. Set to one after parsing a point + as at that point only a FIELDNAME token should be searched. + (FIELDNAME): New token. After a point only a token belonging to + current_type type definition is allowed. + (all over token rules): reset and change current_type according + to rules. + (exp '[' rule): insert implicit array index field if + exp is a pascal string type. + +2002-05-16 Corinna Vinschen + + * v850-tdep.c: Fix comment for v850_scan_prologue. Remove extra + frame info. Use frame_info's saved_regs instead of matching member + in extra_frame_info throughout. + (v850_frame_init_saved_regs): New function. + (v850_init_extra_frame_info): Move most functionality into + v850_frame_init_saved_regs(). + * config/v850/tm-v850.h (EXTRA_FRAME_INFO): Remove definition. + (v850_frame_find_saved_regs): Remove declaration. + (FRAME_FIND_SAVED_REGS): Remove definition. + (v850_frame_init_saved_regs): Add declaration. + (FRAME_INIT_SAVED_REGS): Add definition. + +2002-05-16 Corinna Vinschen + + * v850-tdep.c: Begin multi-arch'ing v850. + (v850_target_architecture_hook): Remove function. + (v850_gdbarch_init): New function. Add code previously in + v850_target_architecture_hook(). + (_initialize_v850_tdep): Don't set target_architecture_hook. + Call register_gdbarch_init() instead. + +2002-05-16 Daniel Jacobowitz + + * gdbtypes.h (struct cplus_struct_type): Remove args field. + * hpread.c (hpread_read_struct_type): Remove assignments to args. + (fixup_class_method_type): Likewise. + +2002-05-15 Jim Blandy + + Add macro structures to GDB's symbol tables. Nobody puts anything + in them yet. + * symtab.h (struct symtab): New member: `macro_table'. + * buildsym.h (pending_macros): New global variable. + * buildsym.c: #include "macrotab.h". + (buildsym_init): Initialize `pending_macros'. + (end_symtab): If we found macro information while reading a CU's + debugging info, do build a symtab structure for it. Make the + symtab point to the macro information, and clear the + `pending_macros' pointer which held it while we were reading the + debug info. + (really_free_pendings): Free any pending macro table. + * objfiles.h (struct objfile): New member: `macro_cache'. + * objfiles.c (allocate_objfile): Set allocate and free functions + for the macro cache's objstack. + (free_objfile): Empty the macro cache's obstack. + * symfile.c (reread_symbols): Empty the macro cache's obstack, and + set new allocate and free functions for it. + * solib-sunos.c (allocate_rt_common_objfile): Set allocate and + free functions for the macro cache's objstack. (Why is this + function building its own objfile?) + * symmisc.c (print_objfile_statistics): Print statistics on the + macro bcache. + * Makefile.in: Note that buildsym.o depends on macrotab.h. + +2002-05-15 Richard Earnshaw + + * config/arm/nm-nbsd.h: Use <> for include of config/nm-nbsd.h. + (REGISTER_U_ADDR): Delete definition. + (arm_register_u_addr): Delete declaration. + +2002-05-15 Richard Earnshaw + + * arm-linux-tdep.c (ARM_LINUX_JB_PC): Renamed from JB_PC. + (ARM_LINUX_JB_ELEMENT_SIZE): Likewise. + +2002-05-14 Andrew Cagney + + * regcache.c (register_valid): Revise comments refering to "Not + available" and "unavailable". + * frame.c (frame_register_read): Ditto. + * findvar.c (value_of_register): Ditto. + +2002-05-15 Andrew Cagney + + * Makefile.in (remote_sim_h): Replace remote-sim_h. + (remote-sim.o): Update dependencies. + (d10v-tdep.o): Specify dependencies. + (sim_d10v_h): Define. + +2002-05-14 Jim Blandy + + * macroexp.c (init_buffer, gather_arguments, expand): Use NULL, not 0. + * macrotab.c (macro_lookup_inclusion, find_definition, + new_macro_table): Same. + + * macroexp.c (currently_rescanning, expand): Use `strcmp () == 0', + not `! strcmp ()'. This is a dubious improvement. + * macrotab.c (macro_lookup_inclusion, find_definition): Same. + + * macrotab.c (macro_lookup_inclusion): Initialize `best_depth', + although it's not necessary, to avoid a warning. + +2002-05-14 Daniel Jacobowitz + + * gdbtypes.h: Update accessor macros to use TYPE_MAIN_TYPE. + (TYPE_CONST, TYPE_VOLATILE, TYPE_CODE_SPACE, TYPE_DATA_SPACE): Use + TYPE_INSTANCE_FLAGS. + (struct main_type): New. + (struct type): Move most members to struct main_type. Change + cv_type and as_type to new type_chain member. Add instance_flags. + (TYPE_MAIN_TYPE, TYPE_CHAIN, TYPE_INSTANCE_FLAGS): New macros. + (TYPE_CV_TYPE, TYPE_AS_TYPE): Remove. + (finish_cv_type): Remove prototype. + * gdbtypes.c (alloc_type): Update comment. Allocate TYPE_MAIN_TYPE. + Set TYPE_CHAIN. + (alloc_type_instance): New function. + (smash_type): New function. + (make_pointer_type, make_reference_type, make_function_type) + (smash_to_member_type, smash_to_method_type): Call smash_type. + (make_qualified_type): New function. + (make_type_with_address_space): Call make_qualified_type. + (make_cv_type): Likewise. + (finish_cv_type): Remove unnecessary function. + (replace_type): Update comment. Copy TYPE_MAIN_TYPE. + (recursive_dump_type): Dump TYPE_CHAIN and TYPE_INSTANCE_FLAGS; + remove TYPE_CV_TYPE and TYPE_AS_TYPE. + * c-typeprint.c (c_type_print_modifier): Use TYPE_INSTANCE_FLAGS. + * dwarf2read.c (read_structure_scope): Don't call finish_cv_type. + * hpread.c (hpread_read_struct_type): Likewise. + * stabsread.c (read_struct_type): Likewise. + +2002-05-14 Elena Zannoni + + * configure.tgt: Add a catch all sh* target, for cases like + sh[2,3,4]-elf and sh-hms. + +2002-05-14 Keith Seitz + + * event-loop.c (create_file_handler): Don't do anything but + update data when we are given a fd which we are already + monitoring. + +2002-05-14 Michal Ludvig + + * dwarf2cfi.c (context_cpy): Copy registers correctly. + (update_context): Use __func__ in warnings. + +2002-05-14 Daniel Jacobowitz + + * ser-tcp.c: Include . Rename tcp_open + and tcp_close to net_open and net_close. + (net_open): Accept "udp:" and "tcp:" specifications. Connect + using UDP if requested. Don't try to disable Nagle on UDP + sockets. + * remote.c (remote_serial_open): New function. Warn about UDP. + (remote_open_1, remote_async_open_1, remote_cisco_open): Call it. + +2002-05-13 Elena Zannoni + + * MAINTAINERS: List sh-elf as buildable with ,-Werror. + +2002-05-13 Elena Zannoni + + * configure.tgt: Remove sh-hms target. + * MAINTAINERS: Don't list sh-hms as a separate target. + +2002-05-13 Jim Blandy + + Add first preprocessor macro-expansion files. + * macroexp.c, macroexp.h, macrotab.c, macrotab.h: New files. + * Makefile.in (SFILES): Add macrotab.c, macroexp.c. + (splay_tree_h, macroexp_h, macrotab_h): New variable. + (HFILES_NO_SRCDIR): Add macrotab.h, macroexp.h. + (COMMON_OBS): Add macrotab.o, macroexp.o. + (macroexp.o, macrotab.o): New rules. + +2002-05-13 Andrew Cagney + + * config/m88k/tm-m88k.h: Update copyright. + (m88k_target_write_pc): Declare + (TARGET_WRITE_PC): Redefine using m88k_target_write_pc. + (M88K_NNPC_REGNUM): Rename NNPC_REGNUM. + (SHIFT_INST_REGS): Update definition. + * m88k-tdep.c (m88k_target_write_pc): New function. Implement + using old definition of TARGET_WRITE_PC. + * regcache.c (generic_target_write_pc): Delete code handling + NNPC_REGNUM. + * gdbarch.sh (NNPC_REGNUM): Delete. + * gdbarch.h, gdbarch.c: Regenerate. + +2002-05-13 Richard Earnshaw + + * builtin-regs.c (value_of_builtin_reg): Correctly calculate the + builtin reg number. + +2002-05-13 Daniel Jacobowitz + + * ax-gdb.c (gen_sign_extend, gen_fetch, gen_usual_unary) + (gen_cast, gen_scale, gen_add, gen_sub, gen_binop, gen_deref) + (gen_address_of, gen_struct_ref, gen_repeat): Use type + access macros. + * c-typeprint.c (cp_type_print_method_args): Likewise. + (c_type_print_args): Likewise. + * d10v-tdep.c (d10v_push_arguments): Likewise. + (d10v_extract_return_value): Likewise. + * expprint.c (print_subexp): Likewise. + * gdbtypes.c (lookup_primitive_typename): Likewise. + (lookup_template_type, add_mangled_type, print_arg_types): Likewise. + * gdbtypes.h (TYPE_UNSIGNED, TYPE_NOSIGN, TYPE_STUB) + (TYPE_TARGET_STUB, TYPE_STATIC, TYPE_CONST, TYPE_VOLATILE) + (TYPE_PROTOTYPED, TYPE_INCOMPLETE, TYPE_CODE_SPACE, TYPE_VARARGS) + (TYPE_VECTOR): Likewise. + * hpread.c (hpread_read_struct_type) + (fix_static_member_physnames, fixup_class_method_type) + (hpread_type_lookup): Likewise. + * mdebugread.c (parse_symbol, parse_type): Likewise. + * p-lang.c (is_pascal_string_type): Likewise. + * valops.c (hand_function_call): Likewise. + * x86-64-tdep.c (classify_argument): Likewise. + + * hpread.c (hpread_read_function_type) + (hpread_read_doc_function_type): Call replace_type. + * dstread.c (create_new_type): Delete. + (decode_dst_structure, process_dst_function): Call alloc_type. + Use type access macros. + +2002-05-12 Mark Kettenis + + * i387-tdep.c (i387_supply_fxsave): Skip the SSE registers if + the're not supported by the current architecture. + (i387_fill_fxsave): Likewise. + +2002-05-12 Fred Fish + + * symfile.c (default_symfile_offsets): Arrange for uninitialized + sect_index_xxx members to index the first slot in section_offsets + if all of the section_offsets are zero. + +2002-05-12 Mark Kettenis + + * configure.tgt (sparc-*openbsd): Remove entry accidentially + checked in with last change. + +2002-05-12 Mark Kettenis + + * configure.tgt (i[3456]86-*-unixware*, i[3456]86-*-unixware2*): + Remove targets. These are canonicalized to i386-*-sysv4.2uw by + config.sub. + +2002-05-12 Daniel Jacobowitz + + * Makefile.in: Update dependencies. + +2002-05-11 Andrew Cagney + + * language.c (local_hex_string_custom): Simplify. Do not depend + on PRINTF_HAS_LONG_LONG or CC_HAS_LONG_LONG. + + * memattr.c (mem_info_command): Replace calls to + longest_local_hex_string and longest_local_hex_string_custom. + * buildsym.c (make_blockvector): Ditto. + * solib.c (info_sharedlibrary_command): Ditto. + * tracepoint.c (tracepoints_info): Ditto. + * symtab.c (print_msymbol_info): Ditto. + + * language.c (local_hex_string): Delete. + (local_hex_string_custom): Delete. + (longest_local_hex_string): Rename to local_hex_string. + (longest_local_hex_string_custom): Rename to + local_hex_string_custom. + * language.h (local_hex_string): Change parameter type to LONGEST. + (local_hex_string_custom): Ditto. + (longest_local_hex_string): Delete declaration. + (longest_local_hex_string_custom): Ditto. + + * solib.c: Update copyright. + * memattr.c: Update copyright. + +2002-05-11 Andrew Cagney + + * arch-utils.h (legacy_register_to_value): Declare. + (legacy_value_to_register): Declare. + (legacy_convert_register_p): Declare. + * arch-utils.c (legacy_register_to_value): New function. + (legacy_value_to_register): New function. + (legacy_convert_register_p): New function. + + * gdbarch.sh (REGISTER_TO_VALUE): Define. + (VALUE_TO_REGISTER): Define. + (CONVERT_REGISTER_P): Define. + * gdbarch.h, gdbarch.c: Regenerate. + + * valops.c (value_assign): Use CONVERT_REGISTER_P and + VALUE_TO_REGISTER. + * findvar.c (value_from_register): Use REGISTER_TO_VALUE and + CONVERT_REGISTER_P. + +2005-05-11 Daniel Jacobowitz + Peter Schauer + + * Makefile.in: Update dependencies for valops.c. + * valops.c: Include "gdb_assert.h". + (typecmp): Skip THIS parameter to methods. + (find_method_list): Remove static_memfuncp argument, + update callers. Check for stub methods. + (find_value_oload_method_list): Don't set *static_memfuncp. + (find_overload_match): Don't check for stub methods. Assert + that methods are not stubbed. Handle static methods. + (value_find_oload_method_list): Remove static_memfuncp argument. + * gdbtypes.c (check_stub_method): Do not add THIS pointer + to the argument list for static stub methods. + * value.h (value_find_oload_method_list): Update prototype. + +2002-05-11 Andrew Cagney + + * arch-utils.h (generic_register_size): Declare. + (generic_register_raw_size, generic_register_virtual_size): Delete + declarations. + * arch-utils.c (generic_register_raw_size): Delete. + (generic_register_size): New function. + (generic_register_virtual_size): Delete. + + * gdbarch.sh (REGISTER_RAW_SIZE, REGISTER_VIRTUAL_SIZE): Make + default generic_register_size. + * gdbarch.h, gdbarch.c: Re-generate. + + * d10v-tdep.c (d10v_gdbarch_init): Use generic_register_size for + register_virtual_size. + * x86-64-tdep.c (x86_64_gdbarch_init): Ditto. + * rs6000-tdep.c (rs6000_gdbarch_init): Ditto. + +2002-05-11 Andrew Cagney + + * gdbarch.sh (gdbarch_data): Add gdbarch parameter. + * gdbarch.h, gdbarch.c: Regenerate. + * gnu-v3-abi.c: Update copyright. + (vtable_address_point_offset): Update. + (gnuv3_rtti_type): Update. + (gnuv3_baseclass_offset): Update. + * solib-svr4.c (svr4_fetch_link_map_offsets): Update. + (init_fetch_link_map_offsets): Update. + * remote.c (get_remote_state): Update. + +2002-05-11 Daniel Jacobowitz + + * TODO: Remove value_headof/value_from_vtable_info comment. + * printcmd.c (print_command_1): Don't call value_from_vtable_info. + * values.c (value_headof, value_from_vtable_info): Delete. + * value.h (value_from_vtable_info): Delete prototype. + +2002-05-11 Andrew Cagney + + * Makefile.in: Replace gdb_assert.h with $(gdb_assert_h), + gdb_string.h with $(gdb_string_h) and gdb_regex.h with + $(gdb_regex_h). + (gdb_assert_h): Define. + (gdb_wait_h): Define. + (gdb_regex_h): Define. + +2002-05-11 Daniel Jacobowitz + + From Peter Schauer : + * linespec.c (find_methods): Handle GCC 3.x template constructors. + +2002-05-11 Jason Thorpe + + * nbsd-tdep.c: Fix comment. + +2002-05-11 Jason Thorpe + + * Makefile.in (ALLDEPFILES): Add nbsd-tdep.c. + (alphanbsd-tdep.o): Add nbsd-tdep.h to dependency list. + (nbsd-tdep.o): New dependency list. + * alphanbsd-tdep.c: Don't include solib-svr4.h. Include + nbsd-tdep.h. + (alphanbsd_solib_svr4_fetch_link_map_offsets): Remove. + (alphanbsd_init_abi): Use nbsd_lp64_solib_svr4_fetch_link_map_offsets. + * nbsd-tdep.c: New file. + * nbsd-tdep.h: New file. + * shnbsd-tdep.c: Don't include solib-svr4.h. Include + nbsd-tdep.h. + (shnbsd_solib_svr4_fetch_link_map_offsets): Remove. + (shnbsd_init_abi): Use nbsd_ilp32_solib_svr4_fetch_link_map_offsets. + * config/alpha/nbsd.mt (TDEPFILES): Add nbsd-tdep.o. + * config/sh/nbsd.mt (TDEPFILES): Ditto. + +2002-05-11 Jason Thorpe + + * config/alpha/nbsd.mh (NATDEPFILES): Remove corelow.o. + * config/alpha/nbsd.mt (TDEPFILES): Add corelow.o. + * config/i386/nbsd.mh (NATDEPFILES): Remove corelow.o. + * config/i386/nbsd.mt (TDEPFILES): Add corelow.o. + * config/i386/nbsdelf.mh (NATDEPFILES): Remove corelow.o. + * config/i386/nbsdelf.mt (TDEPFILES): Add corelow.o. + +2002-05-11 Jason Thorpe + + * config/i386/nbsd.mh (NATDEPFILES): Use line continuations. + * config/i386/nbsdelf.mh (NATDEPFILES): Likewise. + * config/m68k/nbsd.mh (NATDEPFILES): Likewise. + * config/ns32k/nbsd.mh (NATDEPFILES): Likewise. + * config/powerpc/nbsd.mh (NATDEPFILES): Likewise. + * config/sparc/nbsd.mh (NATDEPFILES): Likewise. + * config/sparc/nbsdelf.mh (NATDEPFILES): Likewise. + +2002-05-11 Jason Thorpe + + * i386nbsd-nat.c: Delete file. Move fetch_core_registers and + fetch_elfcore_registers to... + * i386nbsd-tdep.c: ...here. + (i386nbsd_use_struct_convention): Rename to... + (i386nbsd_aout_use_struct_convention): ...this. + (i386nbsd_supply_reg): New function. + (i386nbsd_fill_reg): New function. + (fetch_core_registers): Use i386nbsd_supply_reg. + (fetch_elfcore_registers): Likewise. + (_initialize_i386nbsd_tdep): New function. + * config/i386/nbsd.mh (NATDEPFILES): Remove i386nbsd-nat.o. + * config/i386/nbsdelf.mh (NATDEPFILES): Likewise. + * config/i386/nbsdelf.mt (TDEPFILES): Add i386nbsd-tdep.o. + * config/i386/tm-nbsd.h (i386nbsd_use_struct_convention): Rename to... + (i386nbsd_aout_use_struct_convention): ...this. + +2002-05-11 Jason Thorpe + + * shnbsd-nat.c (fetch_inferior_registers): Use shnbsd_supply_reg. + (store_inferior_registers): Use shnbsd_fill_reg. + * shnbsd-tdep.c (sh_nbsd_supply_registers, + sh_nbsd_supply_register): Collapse into... + (shnbsd_supply_reg): ...this. + (sh_nbsd_fill_registers, sh_nbsd_fill_register): Collapse into... + (shnbsd_fill_reg): ...this. + (sh_nbsd_solib_svr4_fetch_link_map_offsets): Rename to... + (shnbsd_solib_svr4_fetch_link_map_offsets): ...this. + (fetch_core_registers): Use shnbsd_supply_reg. + (fetch_elfcore_registers): Use shnbsd_supply_reg. + (sh_nbsd_core_fns): Rename to... + (shnbsd_core_fns): ...this. + (sh_nbsd_elfcore_fns): Rename to... + (shnbsd_elfcore_fns): ...this. + (sh_nbsd_init_abi): Rename to... + (shnbsd_init_abi): ...this. + (_initialize_sh_nbsd_tdep): Rename to... + (_initialize_shnbsd_tdep): ...this. + * shnbsd-tdep.h (sh_nbsd_supply_registers, + sh_nbsd_supply_register, sh_nbsd_fill_registers, + sh_nbsd_fill_register): Remove prototypes. + (shnbsd_supply_reg, shnbsd_fill_reg): Add prototypes. + +2002-05-11 Jason Thorpe + + * Makefile.in (ALLDEPFILES): Remove i387-nat.c. + (i387-nat.o): Delete dependency list. + (go32-nat.o): Change i387-nat.h to i387-tdep.h. + (x86-64-linux-nat.o): Likewise. + * i387-nat.c: Delete file, moving contents to... + * i387-tdep.c: ...here. + * i387-nat.h: Rename... + * i387-tdep.h: ...to this. + * go32-nat.c: Include i387-tdep.h instead of i387-nat.h. + * i386-linux-nat.c: Likewise. + * i386bsd-nat.c: Likewise. + * i386gnu-nat.c: Likewise. + * i386nbsd-nat.c: Likewise. + * i386v4-nat.c: Likewise. + * x86-64-linux-nat.c: Likewise. + * config/i386/fbsd.mh (NATDEPFILES): Remove i387-nat.o. + * config/i386/go32.mh (NATDEPFILES): Likewise. + * config/i386/i386gnu.mh (NATDEPFILES): Likewise. + * config/i386/i386sol2.mh (NATDEPFILES): Likewise. + * config/i386/i386v42mp.mh (NATDEPFILES): Likewise. + * config/i386/linux.mh (NATDEPFILES): Likewise. + * config/i386/nbsd.mh (NATDEPFILES): Likewise. + * config/i386/nbsdelf.mh (NATDEPFILES): Likewise. + * config/i386/obsd.mh (NATDEPFILES): Likewise. + * config/i386/x86-64linux.mh (NATDEPFILES): Likewise. + +2002-05-11 Jason Thorpe + + * Makefile.in (ALLDEPFILES): Remove alphanbsd-nat.c. + (alphanbsd-nat.o): Remove dependency list. + (alphanbsd-tdep.o): Add $(regcache_h) to dependency list. + * alphanbsd-nat.c: Delete. Contents moved to... + * alphanbsd-tdep.c: ...here. + (_initialize_alphanbsd_tdep): Register core functions. + * config/alpha/nbsd.mh (NATDEPFILES): Remove alphanbsd-nat.o. + +2002-05-11 Jason Thorpe + + * Makefile.in (ALLDEPFILES): Add alphabsd-tdep.c. + (alphabsd-nat.o): Depend on alphabsd-tdep.h. + (alphanbsd-nat.o): Likewise. + (alphabsd-tdep.o): New dependency list. + * alphabsd-nat.c (supply_gregset): Use alphabsd_supply_reg. + (fill_gregset): Use alphabsd_fill_reg. + (supply_fpregset): Use alphabsd_supply_fpreg. + (fill_fpregset): Use alphabsd_fill_fpreg. + (fetch_inferior_registers): Use struct reg and struct fpreg + rather than gregset_t and fpregset_t. Use alphabsd_supply_reg + and alphabsd_supply_fpreg. + (store_inferior_registers): Use struct reg and struct fpreg + rather than gregset_t and fpregset_t. Use alphabsd_fill_reg + and alphabsd_fill_fpreg. + * alphabsd-tdep.c: New file. + * alphabsd-tdep.h: New file. + * alphanbsd-nat.c (fetch_core_registers): Use alphabsd_supply_fpreg. + (fetch_elfcore_registers): Use alphabsd_supply_reg and + alphabsd_supply_fpreg. + * config/alpha/fbsd.mt (TDEPFILES): Add alphabsd-tdep.o. + * config/alpha/nbsd.mt (TDEPFILES): Likewise. + +2002-05-11 Eric Christopher + + * mips-tdep.c (mips_double_register_type): Fix thinko. + (mips_single_register_type): Ditto. + * MAINTAINERS: Add self. + +2002-05-11 Mark Kettenis + + * i387-nat.c (i387_supply_register, i387_fill_fsave, + i387_supply_fxsave, i387_fill_fxsave): Rewrite in order to do the + right thing on architectures with different endianness and/or + integer sizes. + +2002-05-10 Jason Thorpe + + From Christian Limpach + * configure.in: Change sed expression which comments out + NATDEPFILES to also comment out continuation lines. + * configure: Regenerate. + +2002-05-10 Elena Zannoni + + * sh-tdep.c: Clean up code erroneously reintroduced by previous + big patch. + +2002-05-10 Elena Zannoni + + * sh-tdep.c: Include correct file. + +2002-05-10 Elena Zannoni + + New support for sh64-elf (sh5) target. + + * configure.tgt: For sh64-elf target, default to sh-elf. + + * config/sh/tm-sh.h (enum sh-abi): Possible ABI's. + (struct gdbarch_tdep): Add new fields for new registers and ABI + info. + + * sh-tdep.c: Include elf-bfd.h, elf/sh.h, gdb/sim-sh.h. + (NUM_PSEUDO_REGS_SH_MEDIA, NUM_PSEUDO_REGS_SH_COMPACT, + MSYMBOL_IS_SPECIAL, IS_ISA32_ADDR, MAKE_ISA32_ADDR, + UNMAKE_ISA32_ADDR, IS_PTABSL_R18, IS_STS_R0, IS_STS_PR, + IS_MOV_TO_R15, IS_MOV_R14, IS_STQ_R18_R14, IS_STQ_R18_R15, + IS_STL_R18_R15, IS_STQ_R14_R15, IS_STL_R14_R15, IS_ADDIL_SP_MEDIA, + IS_ADDI_SP_MEDIA, IS_ADDL_SP_FP_MEDIA, IS_ADD_SP_FP_MEDIA, + IS_MOV_SP_FP_MEDIA, IS_MOV_R0, IS_MOVL_R0, IS_ADD_SP_R0, + IS_MOV_R14_R0, IS_MEDIA_IND_ARG_MOV, IS_MEDIA_ARG_MOV, + IS_MEDIA_MOV_TO_R14, IS_COMPACT_IND_ARG_MOV, IS_COMPACT_ARG_MOV, + IS_COMPACT_MOV_TO_R14, IS_JSR_R0, IS_NOP): New macros. + (sh_sh64_register_name, sh64_elf_make_msymbol_special, + pc_is_isa32, sh_sh64_breakpoint_from_pc, look_for_args_moves, + sh64_skip_prologue_hard_way, sh64_use_struct_convention, + gdb_print_insn_sh64, translate_insn_rn, sh64_frame_chain, + sh64_get_saved_pr, fpp_reg_base_num, is_media_pseudo, + sh64_get_gdb_regnum, sh64_media_reg_base_num, + sh64_compact_reg_base_num, translate_rn_to_arch_reg_num, + sign_extend, sh64_nofp_frame_init_saved_regs, + sh64_init_extra_frame_info, sh64_get_saved_register, + sh64_extract_struct_value_address, sh64_pop_frame, + sh64_push_arguments, sh64_extract_return_value, + sh64_store_return_value, sh64_show_media_regs, + sh64_show_compact_regs, sh64_show_regs, sh_sh64_register_byte, + sh_sh64_register_raw_size, sh_sh64_register_virtual_size, + sh_sh64_register_virtual_type, + sh_sh64_register_convert_to_virtual, + sh_sh64_register_convert_to_raw, sh64_pseudo_register_read, + sh64_register_read, sh64_pseudo_register_write, + sh64_register_write, do_fv_c_register_info, do_dr_c_register_info, + do_r_c_register_info, do_fpp_register_info, do_cr_c_register_info, + sh64_do_pseudo_register, sh_compact_do_registers_info, + sh64_do_registers_info, sh_gdbarch_init): New functions. + +2002-05-10 Elena Zannoni + + * sh-tdep.c (sh_breakpoint_from_pc): Add 'const' to return type. + +2002-05-10 Daniel Jacobowitz + + * linespec.c (decode_line_1): Check for a double quote after + a filename correctly. + +2002-05-10 Jim Blandy + + Properly track the size of the current objfile's .debug_line section. + * dwarf2read.c (struct dwarf2_pinfo): New member: dwarf_line_size. + (DWARF_LINE_SIZE): New macro. + (dwarf2_build_psymtabs_hard): Record the line section's size in + the partial symbol table. + (psymtab_to_symtab_1): Restore dwarf_line_size from the partial + symbol table. + +2002-05-10 Petr Sorfa + + * ia64-tdep.c: Handle breakpoints on L instruction type + in MLX instruction bundle by moving the breakpoint to + the third slot (X instruction type) as L holds only data. + +2002-05-10 Kevin Buettner + + * dbxread.c (discarding_local_symbols_complaint): New complaint. + (process_one_symbol): Complain about discarding local symbols + due to a misplaced N_LBRAC entry. + +2002-05-09 Elena Zannoni + + From Daniel Berlin + * linespec.c (find_toplevel_char): '<' and '>' also increase and + decrease the depth we are at, in the case of templates. + +2002-05-09 Daniel Jacobowitz + + * mips-tdep.c (mips_float_register_type): New function. + (mips_double_register_type): New function. + (mips_print_register): Use them. + (do_fp_register_row): Likewise. + +2002-05-09 Daniel Jacobowitz + + * signals/signals.c (signals): Remove conditional compilation around + Mach-specific signals. Move them to after TARGET_SIGNAL_DEFAULT. + (target_signal_from_name): Loop until TARGET_SIGNAL_LAST. + +2002-05-09 Michael Snyder + + * remote-rdp.c (remote_rdp_can_run): Remove. + +2002-05-09 Tom Tromey + + * jv-valprint.c (java_val_print): Handle `char' as a special case + of TYPE_CODE_INT. + +2002-05-09 Michael Snyder + + * arm-tdep.c (arm_scan_prologue): Accept strb r(0123),[r11,#-nn], + strh r(0123),[r11,#-nn], str r(0123),[r11,#-nn], as well as + strb r(0123),[sp,#nn], strh r(0123),[sp,#nn] and + str r(0123),[sp,#nn]. + (arm_skip_prologue): Ditto. Also make disassembly + order-independent by placing it in a loop. + +2002-05-06 Michael Snyder + + * stabsread.c (read_type): Add recognition for new attribute: + "@V;" means that an array type is actually a vector. + This is analogous to the vector flag that's been added to dwarf2. + +2002-05-09 Mark Kettenis + + * i386-tdep.h (i386_abi): New enum. + (struct gdbarch_tdep): Replace os_ident member with abi. + (i386_gdbarch_register_os_abi): New prototype. + * i386-tdep.c (i386_abi_names): New array. + (process_note_abi_tag_sections): Removed. + (process_note_sections): New function. + (i386_elf_abi_from_note, i386_elf_abi): New functions. + (struct i386_abi_handler): New struct. + (i386_abi_handler_list): New variable. + (i386_gdbarch_register_os_abi): New function. + (i386_gdbarch_init): Adapt for the changes given above. + +2002-05-08 Daniel Jacobowitz + + * gregset.h: Say "GNU/Linux". + +2002-05-08 Elena Zannoni + + * gdbtypes.c : Add new builtin type for 64 bit vectors. + (build_gdbtypes): Build builtin_type_v2_float. + (_initialize_gdbtypes): Register new builtin type. + +2002-05-08 Andrew Cagney + + * gdbarch.sh (init_gdbarch_swap): Do not clear the swap section. + (clear_gdbarch_swap): New function. + (initialize_non_multiarch): Call. + (gdbarch_update_p): Before calling init(), swap out and clear the + existing architecture. + * gdbarch.c: Regenerate. + +2002-05-08 Jason Thorpe + + * config/djgpp/fnchange.lst: Add alphanbsd-nat.c and + alphanbsd-tdep.c. + +2002-05-08 Jason Thorpe + + * sh-nbsd-nat.c: Rename to... + * shnbsd-nat.c: ...this. + * sh-nbsd-tdep.c: Rename to... + * shnbsd-tdep.c: ...this. + * sh-nbsd-tdep.h: Rename to... + * shnbsd-tdep.h: ...this. + * config/sh/nbsd.mh: Use shnbsd-nat.o. + * config/sh/nbsd.mt: Use shnbsd-tdep.o. + +2002-05-08 Richard Earnshaw + + * remote-rdi.c (_initializie_remote_rdi): Use ANSI-style string + concatenation for command help messages. + +2002-05-08 Jason Thorpe + + * NEWS: Note new sh*-*-netbsdelf* configuration. + * configure.host: Set gdb_host_cpu to sh for all sh*. + (sh*-*-netbsdelf*): New host. + * configure.tgt: Set gdb_target_cpu to sh for all sh*. + (sh*-*-netbsdelf*): New target. + * sh-nbsd-nat.c: New file. + * sh-nbsd-tdep.c: New file. + * sh-nbsd-tdep.h: New file. + * config/sh/nbsd.mh: New file. + * config/sh/nbsd.mt: New file. + * config/sh/nm-nbsd.h: New file. + * config/sh/tm-nbsd.h: New file. + +2002-05-08 Jason Thorpe + + * sh-tdep.c (sh_osabi_names): Declare. + (process_note_abi_tag_sections): New function. + (get_elfosabi): Ditto. + (sh_gdbarch_register_os_abi): Ditto. + (sh_dump_tdep): Ditto. + _initialize_sh_tdep): Use gdbarch_register to register + sh_gdbarch_init and sh_dump_tdep. + * config/sh/tm-sh.h (sh_osabi): Declare. + (gdbarch_tdep): Add sh_osabi and osabi_name members. + +2002-05-07 Andrew Cagney + + * arm-tdep.c (arm_skip_prologue): Handle generic dummy frames. + (thumb_scan_prologue): Ditto. + (arm_find_callers_reg): Ditto. + (arm_frame_chain): Ditto. + (arm_init_extra_frame_info): Ditto. + (arm_frame_saved_pc): Ditto. + (arm_pop_frame): Ditto. + (arm_push_return_address): New function. + (arm_gdbarch_init): Initialize use_generic_dummy_frames, + call_dummy_location, call_dummy_breakpoint_offset_p, + call_dummy_breakpoint_offset, call_dummy_p, + call_dummy_stack_adjust_p, call_dummy_words, + sizeof_call_dummy_words, call_dummy_start_offset, + call_dummy_length, fix_call_dummy, pc_in_call_dummy, + call_dummy_address, push_return_address and push_dummy_frame for + generic dummy frames. + +2002-05-07 Jason Thorpe + + * sh-tdep.c (sh_nofp_frame_init_saved_regs): Fix error in + size computation for alloca. + (sh_fp_frame_init_saved_regs): Likewise. + +2002-05-07 Richard Earnshaw + + * arm-tdep.h (ARM_MAX_REGISTER_RAW_SIZE): Define. + (ARM_MAX_REGISTER_VIRTUAL_SIZE): Define. + * arm-tdep.c (arm_store_return_value): Use them. + Use FP_REGISTER_RAW_SIZE when setting the FPA return value. + * remote-rdp.c (remote_rdp_fetch_register): Use + ARM_MAX_REGISTER_RAW_SIZE. + (remote_rdp_store_register): Likewise. + +2002-05-07 Michal Ludvig + + * dwarf2cfi.c: Code cleanup, removed unused variables, + added default labels to switch {} statements. + * x86-64-tdep.c: Ditto. + * x86-64-linux-nat.c: Ditto. + +2002-05-07 Jason Thorpe + + * solib.h: Protect against multiple inclusion. + +2002-05-06 Jim Blandy + + Add first preprocessor macro-expansion files. + * macroexp.c, macroexp.h, macrotab.c, macrotab.h: New files. + * Makefile.in (SFILES): Add macrotab.c, macroexp.c. + (splay_tree_h, macroexp_h, macrotab_h): New variable. + (HFILES_NO_SRCDIR): Add macrotab.h, macroexp.h. + (COMMON_OBS): Add macrotab.o, macroexp.o. + (macroexp.o, macrotab.o): New rules. + + Separate the job of reading the line number info statement program + header (...expialidocious) out into its own function. + * dwarf2read.c (struct line_head, struct filenames, struct + directories): Replace with... + (struct line_header): New structure, containing the full + contents of the statement program header, including the + include directory and file name tables. + (read_file_scope): If we have line number info, instead of just + calling dwarf_decode_lines to do all the work, call + dwarf_decode_line_header first to get a `struct line_header' + containing the data in the statement program header, and then + pass that to dwarf_decode_lines, which will pick up where that + left off. Be sure to clean up the `struct line_header' object. + (dwarf_decode_line_header, free_line_header, add_include_dir, + add_file_name): New functions. + (dwarf_decode_lines): Move all the code to read the statement + program header into dwarf_decode_line_header. Take the line + header it built as the first argument, instead of the offset to + the compilation unit's line number info. Use the new `struct + line_header' type instead of the old structures. No need to do + cleanups here now, since we don't allocate anything. + (dwarf2_statement_list_fits_in_line_number_section, + dwarf2_line_header_too_long): New complaints. + +2002-05-06 Elena Zannoni + + * gdbtypes.c (init_vector_type): New function. + (build_builtin_type_vec128): Simplify the representation of SIMD + registers. + (build_gdbtypes): Initialize new builtin vector types. + (_initialize_gdbtypes): Register new vector types with gdbarch. + (builtin_type_v4_float, builtin_type_v4_int32, + builtin_type_v8_int16, builtin_type_v16_int8, + builtin_type_v2_int32, builtin_type_v4_int16, + builtin_type_v8_int8): New (renamed) SIMD types. + +2002-05-06 Mark Kettenis + + * i387-nat.c (i387_fill_fsave): Use regcache_collect. + (i387_fill_fxsave): Likewise. + +2002-05-05 Alexandre Oliva + + * alpha-tdep.c (alpha_extract_return_value): Don't use + non-constant array size in prototype. + +2002-05-04 Andrew Cagney + + From Brian Taylor : + * ui-out.c (ui_out_field_core_addr): Use the function + longest_local_hex_string_custom'to format addresses > 32 bits + wide. + + * ui-out.c (ui_out_field_core_addr): Update comment. + +2002-05-04 Andrew Cagney + + * stack.c (select_and_print_frame): Make static. Delete the + parameter `level'. + (func_command): Update call. + (select_frame_command): Delete code computing the frame level. + * frame.h (select_and_print_frame): Delete declaration. + +2002-05-04 Andrew Cagney + + * sparc-tdep.c (sparc_get_saved_register): Comment why + get_prev_frame call is safe. + +2002-05-04 Andrew Cagney + + * frame.h (select_frame): Delete level parameter. + * stack.c (select_frame): Update. Use frame_relative_level to + obtain the frame's level. + (select_and_print_frame): Update call. + (select_frame_command): Ditto. + (up_silently_base): Ditto. + (down_silently_base): Ditto. + * ocd.c (ocd_start_remote): Ditto. + * remote-rdp.c (remote_rdp_open): Ditto. + * remote-mips.c (mips_initialize): Ditto. + (common_open): Ditto. + * remote-e7000.c (e7000_start_remote): Ditto. + * m3-nat.c (select_thread): Ditto. + * hppa-tdep.c (child_get_current_exception_event): Ditto. + (child_get_current_exception_event): Ditto. + * varobj.c (varobj_create): Ditto. + (varobj_update): Ditto. + (c_value_of_root): Ditto. + * tracepoint.c (finish_tfind_command): Ditto. + * corelow.c (core_open): Ditto. + * arch-utils.c (generic_prepare_to_proceed): Ditto. + * thread.c (info_threads_command): Ditto. + (switch_to_thread): Ditto. + * infrun.c (normal_stop): Ditto. + (restore_selected_frame): Ditto. + (restore_inferior_status): Ditto. + * breakpoint.c (insert_breakpoints): Ditto. + (watchpoint_check): Ditto. + (bpstat_stop_status): Ditto. + (do_enable_breakpoint): Ditto. + * blockframe.c (flush_cached_frames): Ditto. + (reinit_frame_cache): Ditto. + +2002-05-04 Andrew Cagney + + * MAINTAINERS (Host/Native): Add Jason Thorpe as NetBSD + maintainer. + +2002-05-04 Jim Blandy + + * gdbtypes.c (replace_type): Doc fix. + +2002-05-04 Andrew Cagney + + * valprint.c (strcat_longest): Delete commented out function. + Update copyright. + +2002-05-04 Andrew Cagney + + * MAINTAINERS: Mark a29k as deleted. + * NEWS: Mention that a29k was removed. Add OBSOLETE section. + Move new configurations to the top. + * configure.tgt: Remove a29k. + * config/a29k/tm-vx29k.h: Delete. + * config/a29k/vx29k.mt: Delete. + * config/a29k/tm-a29k.h: Delete. + * config/a29k/a29k-udi.mt: Delete. + * config/a29k/a29k.mt: Delete. + * a29k-tdep.c: Delete. + * remote-udi.c: Delete. + * remote-mm.c: Delete. + * remote-eb.c: Delete. + * remote-adapt.c: Delete. + * Makefile.in: Remove obsolete code. + * config/s390/s390x.mt: Ditto. + * config/s390/s390.mt: Ditto. + * config/sparc/sparclynx.mh: Ditto. + * config/sparc/linux.mh: Ditto. + * config/pa/hppaosf.mh: Ditto. + * config/pa/hppabsd.mh: Ditto. + * config/ns32k/nbsd.mt: Ditto. + * config/mips/vr5000.mt: Ditto. + * config/m68k/sun3os4.mh: Ditto. + * config/m68k/nbsd.mt: Ditto. + * config/m68k/m68klynx.mh: Ditto. + * config/m32r/m32r.mt: Ditto. + * config/i386/x86-64linux.mt: Ditto. + * config/i386/nbsdelf.mt: Ditto. + * config/i386/nbsd.mt: Ditto. + * config/i386/i386lynx.mh: Ditto. + +2002-05-04 Andrew Cagney + + * target.c (debug_print_register): New function. Handle oversize + registers. + (debug_to_fetch_registers): Call. + (debug_to_store_registers): Call. + +2002-05-03 Jim Blandy + + * stabsread.c (cleanup_undefined_types): Use replace_type, not memcpy. + (read_type): Doc fix. + * gdbtypes.c (replace_type): Doc fix. + + * stabsread.c (multiply_defined_struct): New complaint. + (read_struct_type): If the type we were passed isn't empty, or + incomplete, don't read the new struct type into it; complain, + and return the original type unchanged. Take a new `type_code' + argument, which is the type code for the new type. + (read_type): Rather than storing the type's type code here, pass + it as an argument to read_struct_type, and let that take care of + storing it. That way, we don't overwrite the original type code, + so read_struct_type can use it to decide whether we're overwriting + something we shouldn't. + (complain_about_struct_wipeout): New function. + +2002-05-03 Andrew Cagney + + * gdbarch.sh: Assert that gdbarch is non-NULL. + * gdbarch.c: Regenerate. + +2002-05-03 Jason Merrill + + * gnu-v3-abi.c (gnuv3_rtti_type): If we get confused, just warn + and return NULL. + +2002-05-03 Michal Ludvig + + * x86-64-tdep.c (x86_64_dwarf2gdb_regno_map), + (x86_64_dwarf2gdb_regno_map_length), + (x86_64_dwarf2_reg_to_regnum): Added. + (x86_64_gdbarch_init): Added registration of x86_64_dwarf2_reg_to_regnum. + (x86_64_gdbarch_init): Renamed from i386_gdbarch_init. + (_initialize_x86_64_tdep): Synced with the change above. + (x86_64_skip_prologue): Reformulated message. + +2002-05-03 Pierre Muller + + * f-exp.y: Also use new prev_lexptr variable + to improve error reporting. Based on Michael Snyder + 2002-04-24 dated patch to c-exp.y. + * jv-exp.y: Likewise. + * m2-exp.y: Likewise. + +2002-05-02 Elena Zannoni + + * valops.c (value_arg_coerce): Don't coerce arrays to pointers if + we are dealing with vectors. + +2002-05-02 Pierre Muller + + * config/m68k/tm-nbsd.h: Obvious fix, + correct machine name. + +2002-05-02 Pierre Muller + + * p-typeprint.c (pascal_type_print_base): Add support + for TYPE_CODE_STRING and TYPE_CODE_BITSTRING. + +2002-05-02 Pierre Muller + + * p-lang.c (pascal_create_fundamental_type): Use TYPE_CODE_CHAR + for fondamental pascal 'char' type. + +2002-05-02 Pierre Muller + + * p-lang.h (is_pascal_string_type): Declaration changed, + new sixth argument of type char ** added. + * p-lang.c (is_pascal_string_type): Implementation + changed. Args length_pos, length_size, string_pos, char_size + can now be NULL. New argument arrayname set to the field + name of the char array. Return value set to char array + field index plus one. + * p-valprint.c (pascal_val_print): Adapt to new declaration of + is_pascal_string_type function. + +2002-05-02 Andrew Cagney + + * gdbarch.sh (gdbarch_update_p): Revert 2002-05-02 Andrew Cagney + change. + * gdbarch.c: Regenerate. + +2002-05-02 Andrew Cagney + + * gdbarch.sh (gdbarch_update_p): Swap out the old architecture + before probing for a new one. Detect errorenous gdbarch_init + functions. + * gdbarch.c: Regenerate. + +2002-05-01 Andrew Cagney + + * config/mn10200/tm-mn10200.h: Include "symfile.h" and "symtab.h". + * config/mcore/tm-mcore.h: Ditto. Update copyright. + * config/v850/tm-v850.h: Ditto. Update copyright. + +2002-04-30 Andrew Cagney + + * cris-tdep.c (cris_gdbarch_init): Use arches instead of + current_gdbarch. + +2002-04-30 Michael Snyder + + * arm-tdep.c: Whitespace clean-ups. + (arm_skip_prologue): Fix thinko; two lines + should have been removed as part of 4/24 change. + +2002-04-30 Kevin Buettner + + * rs6000-tdep.c: Added comment describing how fpscr register + numbers were chosen. + +2002-04-30 Michael Snyder + + * gnu-nat.c (gnu_find_memory_regions): Fix merge botch. + +2002-04-29 Elena Zannoni + + * hpread.c (DNTT_TYPE_VECTOR): Rename from TYPE_VECTOR. + (DNTT_TYPE_VECTOR_LENGTH): Rename from TYPE_VECTOR_LENGTH. + (hpread_symfile_init, hpread_lookup_type): Substitute throughout. + +2002-04-29 Kevin Buettner + + From Louis Hamilton : + * rs6000-tdep.c (coff/xcoff.h, libxcoff.h): Include. + * xcoffread.c (coff/xcoff.h, libxcoff.h): Likewise. + * rs6000-tdep.c (rs6000_gdbarch_init): Use bfd_xcoff_is_xcoff64(), + not bfd-private xcoff data, to determine wordsize. + * xcoffread.c (read_xcoff_xymtab, read_symbol_lineno): Likewise. + +2002-04-29 Andrew Cagney + + GDB 5.2 released from 5.2 branch. + +2002-04-29 Michal Ludvig + + * x86-64-linux-nat.c (fill_gregset): Explicit cast to avoid warning. + * x86-64-tdep.c (i386_gdbarch_init): Ditto. + (x86_64_register_info_table): Added comments with register numbers. + +2002-04-29 Elena Zannoni + + * rs6000-tdep.c (rs6000_extract_return_value, + rs6000_store_return_value): Handle returning vectors. + (rs6000_gdbarch_init): Use + ppc_sysv_abi_broken_use_struct_convention for native sysv cases. + * ppc-linux-tdep.c (ppc_sysv_abi_broken_use_struct_convention): + New function. + (ppc_sysv_abi_use_struct_convention): Deal with functions returning + vectors. + (ppc_sysv_abi_push_arguments): Handle vector parameters. + * ppc-tdep.h (ppc_sysv_abi_broken_use_struct_convention): Export. + +2002-04-24 Pierre Muller + + * hpread.c (hpread_psymtab_to_symtab_1, + hpread_psymtab_to_symtab): Replace fprintf tab_to_s...) + with fprintf_unfiltered (gdb_stderr,...). + +2002-04-24 Pierre Muller + + * remote-array.c (printf_monitor, write_monitor, + array_insert_breakpoint, array_remove_breakpoint ): + Replace fprintf (stderr,... + with fprintf_unfiltered (gdb_stderr,.... + * remote-es.c: Likewise. + * remote-os9k.c: Likewise. + * remote-st.c: Likewise. + +2002-04-28 Andreas Schwab + + * config/s390/s390.mh (NATDEPFILES): Remove solib.o, add + linux-proc.o and gcore.o. + +2002-04-26 Michal Ludvig + + * x86-64-tdep.c (x86_64_skip_prologue): Print note when debugging + code without frame pointers. + +2002-04-26 Andrew Cagney + + * sparc-tdep.c (sparc_gdbarch_init): Add comment explaining why + ON_STACK is needed. + +2002-04-26 Ben Elliston + + * target.c (do_xfer_memory): Correct reference to the new option + "trust-readonly-sections". + +2002-04-26 Elena Zannoni + + * gdbtypes.h (TYPE_FLAG_VECTOR, TYPE_VECTOR): Define. + * gdbtypes.c (recursive_dump_type): Output the vector flag. + * dwarf2read.c (dwarf_attr_name): Handle new attribute for + vectors. + (read_array_type): Record the fact that this array type is really a + vector (i.e. are passed in by value). + +2002-04-26 Jason Thorpe + + * alpha-tdep.h (gdbarch_tdep): Add sigcontext_addr member. + * alpha-tdep.c (alpha_sigcontext_addr): New function. + (alpha_find_saved_regs): Use alpha_sigcontext_addr. + (alpha_gdbarch_init): Initialize tdep->sigcontext_addr. + * alpha-linux-tdep.c: Include frame.h. + (alpha_linux_sigcontext_addr): New function. + (alpha_linux_init_abi): Set tdep->sigcontext_addr to + alpha_linux_sigcontext_addr. + * alpha-osf1-tdep.c: Include gdbcore.h. + (alpha_osf1_sigcontext_addr): New function. + (alpha_osf1_init_abi): Set tdep->sigcontext_addr to + alpha_osf1_sigcontext_addr. + * config/alpha/tm-alpha.h (SIGCONTEXT_ADDR): Remove. + * config/alpha/tm-alphalinux.h (SIGCONTEXT_ADDR): Remove. + +2002-04-26 Andrew Cagney + + * stack.c (selected_frame_level): + (select_frame): Do not set selected_frame_level. + * frame.h (selected_frame_level): Delete declaration. + +2002-04-26 Andrew Cagney + + * rs6000-tdep.c (rs6000_gdbarch_init): Only set + convert_from_func_ptr-addr when AIX / PowerOpen. + +2002-04-25 Andrew Cagney + + * valops.c (hand_function_call): Call + generic_save_call_dummy_addr. + * frame.h (generic_save_call_dummy_addr): Declare. + * blockframe.c (struct dummy_frame): Add fields call_lo and + call_hi. + (generic_find_dummy_frame): Check for PC in range call_lo to + call_hi instead of entry_point_address. + (generic_pc_in_call_dummy): Search the dummy frames for a PC in + the call_lo to call_hi range. Allow for DECR_PC_AFTER_BREAK. + (generic_save_call_dummy_addr): New function. + +2002-04-24 David S. Miller + + * sparc-tdep.c (sparc_gdbarch_skip_prologue): Kill, duplicates + sparc_skip_prologue. + (sparc_skip_prologue): Kill frameless_p arg, and use line number + information to find prologue when possible. + (sparc_prologue_frameless_p): Call examine_prologue directly. + (sparc_gdbarch_init): Update set_gdbarch_skip_prologue call. + * config/sparc/tm-sparc.h (sparc_skip_prologue): Update for killed + second argument. + (SKIP_PROLOGUE): Likewise. + +2002-04-25 Jason Thorpe + + * alpha-tdep.c (alpha_skip_prologue_internal): Remove + GDB_TARGET_HAS_SHARED_LIBS #ifdef and update comment to + indicate that the condition it was testing is always true. + * config/alpha/nm-linux.h (GDB_TARGET_HAS_SHARED_LIBS): Remove. + * config/alpha/nm-nbsd.h (GDB_TARGET_HAS_SHARED_LIBS): Ditto. + * config/alpha/nm-osf.h (GDB_TARGET_HAS_SHARED_LIBS): Ditto. + +2002-04-25 Jason Thorpe + + * alpha-tdep.h (gdbarch_tdep): Add jb_pc and jb_elt_size members. + * alpha-linux-tdep.c (alpha_linux_init_abi): Initialize + tdep->jb_pc and tdep->jb_elt_size. + * alpha-osf1-tdep.c (alpha_osf1_init_abi): Likewise. + * alphafbsd-tdep.c (alphafbsd_init_abi): Likewise. + * alphanbsd-tdep.c (alphanbsd_init_abi): Likewise. + * alpha-nat.c (get_longjmp_target): Remove. + (JB_ELEMENT_SIZE): Ditto. + (JB_PC): Ditto. + * alpha-tdep.c (alpha_get_longjmp_target): New function. + (alpha_gdbarch_init): Default tdep->jb_pc to -1. If the + OS ABI sets jb_pc to a valid value, set gdbarch_get_longjmp_target + to alpha_get_longjmp_target. + (alpha_dump_tdep): Report tdep->jb_pc and tdep->jb_elt_size. + * config/alpha/nm-linux.h (GET_LONGJMP_TARGET): Remove. + * config/alpha/nm-osf.h (GET_LONGJMP_TARGET): Remove. + +2002-04-25 Andrew Cagney + + * README: Update to GDB 5.2. + +2002-04-25 Andrew Cagney + + * gdbarch.sh (LC_ALL): Set to `c'. + +2002-04-25 Theodore A. Roth + + * avr-tdep.c: Ran through gdb_indent.sh. + +2002-04-25 Theodore A. Roth + + * MAINTAINERS: Add myself as AVR maintainer. + * NEWS: Note new target avr. + +2002-04-25 Theodore A. Roth + + * Makefile.in: Add support for AVR target. + * configure.tgt: Add support for AVR target. + * avr-tdep.c: New file + * config/avr/avr.mt: New file. + +2002-04-25 Theodore A. Roth + + * MAINTAINERS: Add myself to write-after-approval. + +2002-04-24 Pierre Muller + + * f-lang.c (get_bf_for_fcn): Replace fprintf (stderr,... + with fprintf_unfiltered (gdb_stderr,.... + +2002-04-25 Pierre Muller + + Fix PR gdb/508. + * symfile.c (add_filename_language): Fix wrong xrealloc size argument. + +2002-04-25 Pierre Muller + + * p-exp.y: Also use new prev_lexptr variable + to improve error reporting. Based on Michael Snyder + 2002-04-24 dated patch to c-exp.y. + +2002-04-25 Jason Thorpe + + * alpha-tdep.c (alpha_breakpoint_from_pc): New function. + (alpha_gdbarch_init): Set gdbarch_breakpoint_from_pc to + alpha_breakpoint_from_pc. Set gdbarch_function_start_offset + to 0. + * config/alpha/tm-alpha.h: Remove forward decls of struct type + and struct value. + (FUNCTION_START_OFFSET): Remove. + (BREAKPOINT): Ditto. + +2002-04-25 Jason Thorpe + + * MAINTAINERS: Reflect that multi-arch is enabled for VAX. + * NEWS: Ditto. + +2002-04-24 Jason Thorpe + + * alpha-linux-tdep.c (alpha_linux_pc_in_sigtramp): New function. + (alpha_linux_init_abi): Set gdbarch_pc_in_sigtramp to + alpha_linux_pc_in_sigtramp. + * alpha-osf1-tdep.c (alpha_osf1_pc_in_sigtramp): New function. + (alpha_osf1_init_abi): Set gdbarch_pc_in_sigtramp to + alpha_osf1_pc_in_sigtramp. + * alpha-tdep.c (alpha_osf_in_sigtramp): Remove. + * alphafbsd-tdep.c (alphafbsd_pc_in_sigtramp): New function. + (alphafbsd_init_abi): Set gdbarch_pc_in_sigtramp to + alphafbsd_pc_in_sigtramp. + * alphanbsd-tdep.c (alphanbsd_pc_in_sigtramp): New function. + (alphanbsd_init_abi): Set gdbarch_pc_in_sigtramp to + alphanbsd_pc_in_sigtramp. + * config/alpha/tm-alpha.h (IN_SIGTRAMP): Remove. + * config/alpha/tm-alphalinux.h (IN_SIGTRAMP): Remove. + +2002-04-24 Jason Thorpe + + * config/alpha/nbsd.mh (NATDEPFILES): Remove solib-legacy.o. + +2002-04-24 Jason Thorpe + + * Makefile.in (ALLDEPFILES): Add alphanbsd-nat.c and + alphanbsd-tdep.c. + (alphanbsd-nat.o): New dependency list. + (alphanbsd-tdep.o): Ditto. + * NEWS: Note new native NetBSD/alpha configuration. + * alphanbsd-nat.c: New file. + * alphanbsd-tdep.c: Ditto. + * configure.host (alpha*-*-netbsd*): New host. + * configure.tgt (alpha*-*-netbsd*): New target. + * config/alpha/nbsd.mh: New file. + * config/alpha/nbsd.mt: Ditto. + * config/alpha/nm-nbsd.h: Ditto. + * config/alpha/tm-nbsd.h: Ditto. + +2002-04-24 Jason Thorpe + + * Makefile.in (ALLDEPFILES): Add alpha-osf1-tdep.c. + (alpha-osf1-tdep.o): New dependency list. + * alpha-tdep.h (gdbarch_tdep): Add dynamic_sigtramp_offset + and skip_sigtramp_frame members. + * alpha-linux-tdep.c: Include gdbcore.h. + (alpha_linux_sigtramp_offset): Change return type to LONGEST. + (alpha_linux_init_abi): Initialize tdep->dynamic_sigtramp_offset. + * alpha-osf1-tdep.c: New file. + * alpha-tdep.c (alpha_osf_skip_sigtramp_frame): Moved to + alpha-osf1-dep.c. + (alpha_frame_past_sigtramp_frame): New function. + (alpha_dynamic_sigtramp_offset): Ditto. + (alpha_proc_desc_is_dyn_sigtramp): Ditto. + (alpha_set_proc_desc_is_dyn_sigtramp): Ditto. + (ALPHA_PROC_SIGTRAMP_MAGIC): Define. + (push_sigtramp_desc): Use alpha_set_proc_desc_is_dyn_sigtramp. + (after_prologue): Use alpha_proc_desc_is_dyn_sigtramp. + (find_proc_desc): Use alpha_dynamic_sigtramp_offset. + (alpha_frame_chain): Use alpha_frame_past_sigtramp_frame. + (alpha_init_extra_frame_info): Use alpha_proc_desc_is_dyn_sigtramp. + (alpha_pop_frame): Use alpha_proc_desc_is_dyn_sigtramp. + (alpha_gdbarch_init): Initialize tdep->dynamic_sigtramp_offset + and tdep->skip_sigtramp_frame. Set gdbarch_skip_trampoline_code + to find_solib_trampoline_target. + * config/alpha/alpha-osf1.mt (TDEPFILES): Add alpha-osf1-tdep.o. + * config/alpha/tm-alpha.h: Remove inclusion of regcache.h. + (SKIP_TRAMPOLINE_CODE): Remove. + (PROC_DESC_IS_DYN_SIGTRAMP): Ditto. + (SET_PROC_DESC_IS_DYN_SIGTRAMP): Ditto. + (DYNAMIC_SIGTRAMP_OFFSET): Ditto. + (FRAME_PAST_SIGTRAMP_FRAME): Ditto. + * config/alpha/tm-alphalinux.h (PROC_DESC_IS_DYN_SIGTRAMP): Remove. + (PROC_SIGTRAMP_MAGIC): Ditto. + (PROC_DESC_IS_DYN_SIGTRAMP): Ditto. + (SET_PROC_DESC_IS_DYN_SIGTRAMP): Ditto. + (SET_PROC_DESC_IS_DYN_SIGTRAMP): Ditto. + (DYNAMIC_SIGTRAMP_OFFSET): Ditto. + (FRAME_PAST_SIGTRAMP_FRAME): Ditto. + +2002-04-24 Jason Thorpe + + * NEWS: Note that Alpha targets are now multi-arch. + +2002-04-24 Michael Snyder + + * parser-defs.h (prev_lexptr): New external variable. + * parse.c (parse_exp_1): Set prev_lexptr to null before + calling the language-specific parser. + * c-exp.y (yylex): Set prev_lexptr to start of current token. + (yyerror): Use prev_lexptr in error reporting. + +2002-04-24 Daniel Jacobowitz + + * config/i386/tm-linux.h: Define FILL_FPXREGSET. + * gregset.h: If FILL_FPXREGSET is defined, provide + gdb_fpxregset_t, supply_fpxregset, and fill_fpxregset. + * linux-proc.c (linux_do_thread_registers): If FILL_FPXREGSET + is defined, call fill_fpxregset. + +2002-04-24 Roland McGrath + + * config/i386/i386gnu.mh (NATDEPFILES): Add core-regset.o here. + * i386gnu-nat.c [HAVE_SYS_PROCFS_H] + (supply_gregset, supply_fpregset): New functions. + + * gnu-nat.c (gnu_find_memory_regions): New function. + (init_gnu_ops): Set `to_find_memory_regions' hook to that. + (gnu_xfer_memory): Add a cast. + +2002-04-24 Michael Snyder + + * arm-tdep.c (arm_scan_prologue): Move "mov ip, sp" into the + loop. Add handling for "str lr, [sp, #-4]!" and for saves + of argument regs ("str r(0123), [r11, #-nn"]). + (arm_skip_prologue): Better handling for frameless functions. + Treat "mov ip, sp" as optional. Recognize "str lr, [sp, #-4]". + (arm_skip_prologue): Recognize str r(0123), [r11, #-nn]. + +Wed Apr 24 14:22:21 2002 Andrew Cagney + + * arm-tdep.c (arm_gdbarch_init): Add comment that NUM_REGS nor + NUM_PSEUDO_REGS can be used. + +2002-04-24 Andrew Cagney + + * arch-utils.h: Update copyright. + + * gdbarch.sh (PC_IN_SIGTRAMP): Add. + * gdbarch.h, gdbarch.c: Re-generate. + + * inferior.h (IN_SIGTRAMP): Delete definition. + * arch-utils.c (legacy_pc_in_sigtramp): New function. + * arch-utils.h (legacy_pc_in_sigtramp): Declare. + + * mips-tdep.c (mips_init_extra_frame_info): Use PC_IN_SIGTRAMP. + (mips_dump_tdep): Do not print value of IN_SIGTRAMP. + * hppa-tdep.c (pc_in_interrupt_handler): Use PC_IN_SIGTRAMP. + (find_proc_framesize): Ditto. + * alpha-tdep.c (alpha_osf_skip_sigtramp_frame): Ditto. + (alpha_init_extra_frame_info): Ditto. + * infrun.c (handle_inferior_event): Ditto. + (handle_inferior_event): Ditto. + (check_sigtramp2): Ditto. + * blockframe.c (create_new_frame): Ditto. + (get_prev_frame): Ditto. + * ppc-linux-tdep.c: Update comments. + * i386-linux-tdep.c: Update comments. + * breakpoint.c (bpstat_what): Update comment. + +2002-04-24 David S. Miller + + * i960-tdep.c (register_in_window_p): New function. + (i960_find_saved_register): Use it instead of + REGISTER_IN_WINDOW_P. + * config/i960/tm-i960.h (REGISTER_IN_WINDOW): Delete. + + * symtab.h (find_stab_function_addr): Kill extern. + * minsyms.c (find_stab_function_addr): Remove from here... + * dbxread.c: ... to here, and mark it static. + +2002-04-20 David S. Miller + + * sparc-tdep.c (sparc_pop_frame): Only need to allocate + SPARC_INTREG_SIZE * 16 bytes for reg_temp. + +2002-04-21 David S. Miller + + * remote-vxsparc.c (vx_read_register): Fix typo, we want + REGISTER_RAW_SIZE of SP_REGNUM not CORE_ADDR. + (vx_write_register): Likewise. + +2002-04-23 J. Brobecker + + * source.c (is_regular_file): New function. + (openp): Check wether file to open is a regular file + to avoid opening directories. + +2002-04-22 Jason Thorpe + + * findvar.c (extract_signed_integer): Cast printf argument + to suppress format warning. + (extract_unsigned_integer): Likewise. + * infcmd.c (registers_info): Likewise. + * top.c (get_prompt_1): Likewise. + * valops.c (value_assign): Likewise. + * valprint.c (print_decimal): Likewise. + +2002-04-22 H.J. Lu (hjl@gnu.org) + + * c-exp.y (typebase): Support + + [long|long long|short] [signed|unsigned] [int|] + + and + + signed [long|long long|short] int + +2002-04-22 Jason Thorpe + + * Makefile.in (vax-tdep.o): Add $(arch_utils_h), $(inferior_h), + and vax-tdep.h. + * vax-tdep.h: New file. + * vax-tdep.c: Include inferior.h, arch-utils.h, and vax-tdep.h. + Make several routines static. + (vax_get_saved_register): New function. + (vax_gdbarch_init): New function. + (_initialize_vax_tdep): Register vax_gdbarch_init. + * config/vax/tm-vax.h: Set GDB_MULTI_ARCH to GDB_MULTI_ARCH_PARTIAL. + Remove macros now under the control of gdbarch. + +2002-04-22 Michael Snyder + + * arm-tdep.c (arm_skip_prologue): Recognize "sub sp, sp, #nn". + Some whitespace and coding standards tweaks. + +2002-04-22 Jason Thorpe + + * vax-tdep.c: Include regcache.h. + (vax_call_dummy_words): New. + (sizeof_vax_call_dummy_words): New. + (vax_fix_call_dummy): New function. + (vax_saved_pc_after_call): Ditto. + * config/vax/tm-vax.h: Don't include regcache.h. + (SAVED_PC_AFTER_CALL): Use vax_saved_pc_after_call. + (CALL_DUMMY): Remove. + (CALL_DUMMY_WORDS): Define. + (SIZEOF_CALL_DUMMY_WORDS): Define. + (FIX_CALL_DUMMY): Use vax_fix_call_dummy. + +2002-04-18 Michael Snyder + + * arm-tdep.h: Change regnum defines to enums for ease of debugging. + +2002-04-22 Jason Thorpe + + * vax-tdep.c (vax_frame_chain): New function. + (vax_push_dummy_frame): Ditto. + (vax_pop_frame): Ditto. + * config/vax/tm-vax.h (FRAME_CHAIN): vax_frame_chain. + (FRAMELESS_FUNCTION_INVOCATION): Use + generic_frameless_function_invocation_not. + (PUSH_DUMMY_FRAME): Use vax_push_dummy_frame. + (POP_FRAME): Use vax_pop_frame. + +2002-04-22 Jason Thorpe + + * vax-tdep.c (vax_store_struct_return): New function. + (vax_extract_return_value): Ditto. + (vax_store_return_value): Ditto. + (vax_extract_struct_value_address): Ditto. + * config/vax/tm-vax.h (STORE_STRUCT_RETURN): Use + vax_store_struct_return. + (EXTRACT_RETURN_VALUE): Use vax_extract_return_value. + (STORE_RETURN_VALUE): Use vax_store_return_value. + (EXTRACT_STRUCT_VALUE_ADDRESS): Use vax_extract_struct_value_address. + +2002-04-22 Jason Thorpe + + * vax-tdep.c (vax_frame_saved_pc): New function. + (vax_frame_args_address_correct): Ditto. + (vax_frame_args_address): Ditto. + (vax_frame_locals_address): Ditto. + (vax_frame_num_args): Move code to be in proximity to + other frame-related functions. + * config/vax/tm-vax.h (INNER_THAN): Use core_addr_lessthan. + (FRAME_SAVED_PC): Use vax_frame_saved_pc. + (FRAME_ARGS_ADDRESS_CORRECT): Use vax_frame_args_address_correct. + (FRAME_ARGS_ADDRESS): Use vax_frame_args_address. + (FRAME_LOCALS_ADDRESS): Use vax_frame_locals_address. + +2002-04-22 H.J. Lu (hjl@gnu.org) + + * Makefile.in (FLAGS_TO_PASS): Add libdir, mandir, datadir and + includedir. + +2002-04-22 Jason Thorpe + + * vax-tdep.c (vax_frame_init_saved_regs): New function. + * config/vax/tm-vax.h (FRAME_FIND_SAVED_REGS): Remove. + (FRAME_INIT_SAVED_REGS): New macro. + +2002-04-22 Jason Thorpe + + * MAINTAINERS: Reflect that the Alpha target has been multi-arch'd. + +2002-04-22 Jason Thorpe + + * alpha-nat.c (get_longjmp_target): Use ALPHA_* constants + where needed. + (fetch_osf_core_registers): Likewise. + (supply_gregset): Likewise. + +2002-04-22 J. Brobecker + + * symfile.h (get_section_index): Define. + * symfile.c (get_section_index): New function. + * mdebugread.c (SC_IS_SBSS): New macro. + (SC_IS_BSS): Return true for the scBss storage class only, as + the scSBss storage class refers to the .sbss section. + (parse_partial_symbols): Discard the symbols which associated + section does not exist. + Make sure to use the .sbss section index for symbols which + storage class is scBss, rather than using the .bss section index. + +2002-04-22 Jason Thorpe + + * vax-tdep.c: Update copyright years. + (vax_register_name): New function. + (vax_register_byte): Ditto. + (vax_register_raw_size): Ditto. + (vax_register_virtual_size): Ditto. + (vax_register_virtual_type): Ditto. + * config/vax/tm-vax.h: Update copyright years. + (REGISTER_NAMES): Remove. + (REGISTER_NAME): Define. + (REGISTER_BYTE): Use vax_register_byte. + (REGISTER_RAW_SIZE): Use vax_register_raw_size. + (REGISTER_VIRTUAL_SIZE): Use vax_register_virtual_size. + (REGISTER_VIRTUAL_TYPE): Use vax_register_virtual_type. + +2002-04-21 Andrew Cagney + + * config/sparc/tm-sparc.h (sparc_skip_prologue): Restore + declaration + * arc-tdep.c (arc_prologue_frameless_p): Fix syntax error. + +2002-04-21 David S. Miller + + * arch-utils.c (generic_prologue_frameless_p): Kill + SKIP_PROLOGUE_FRAMELESS_P code. + * config/arc/tm-arc.h (SKIP_PROLOGUE_FRAMELESS_P): Delete + references. + (PROLOGUE_FRAMELESS_P, arc_prologue_frameless_p): New. + * arc-tdep.c (arc_prologue_frameless_p): Implement. + * config/arc/tm-sparc.h (SKIP_PROLOGUE_FRAMELESS_P): Delete + references. + (PROLOGUE_FRAMELESS_P, sparc_prologue_frameless_p): New. + * sparc-tdep.c (sparc_prologue_frameless_p): Implement. + (sparc_gdbarch_init): Pass it to + set_gdbarch_prologue_frameless_p. + +2002-04-21 Jason Thorpe + + * Makefile.in (ALLDEPFILES): Add alphabsd-nat.c. + (alphabsd-nat.o): New dependency list. + +2002-04-21 Jason Thorpe + + * Makefile.in (ALLDEPFILES): Add alpha-linux-tdep.c and + alphafbsd-tdep.c. + (alpha-linux-tdep.o): New dependency list. + (alphafbsd-tdep.o): Likewise. + +2002-04-21 Jason Thorpe + + * alpha-linux-tdep.c: New file. Move alpha_linux_sigtramp_offset + to here... + * alpha-tdep.c: ...from here. + * config/alpha/alpha-linux.mt (TDEPFILES): Add alpha-linux-tdep.o. + +2002-04-21 Jason Thorpe + + * config/alpha/tm-alpha.h: Move alpha_software_single_step + prototype from here... + * alpha-tdep.h: ...to here. + +2002-04-21 Andrew Cagney + + * frame.h (selected_frame_level): Document as deprecated. + (frame_relative_level): Declare. + * stack.c (frame_relative_level): New function. + (selected_frame_level): Document as deprecated. + (select_frame): Do not set the selected_frame_level. + + * stack.c (frame_info, record_selected_frame): Update. + (frame_command, current_frame_command): Update. + (up_silently_base, up_command, down_silently_base): Update. + (down_command): Update. + * inflow.c (kill_command): Update. + * tracepoint.c (finish_tfind_command): Update. + * corelow.c (core_open): Update. + * thread.c (info_threads_command): Update. + (do_captured_thread_select): Update. + * infcmd.c (finish_command): Update. + * breakpoint.c (insert_breakpoints, do_enable_breakpoint): Update. + +2002-04-21 Jason Thorpe + + * config/alpha/tm-fbsd.h (FRAME_CHAIN_VALID): Remove. + +2002-04-21 Andrew Cagney + + * arm-tdep.c (arm_breakpoint_from_pc): Make static. Make return + type const. + +2002-04-21 Jason Thorpe + + * alphafbsd-tdep.c: Update copyright years. Include + alpha-tdep.h. + (alphafbsd_use_struct_convention): Make static. + (alphafbsd_init_abi): New function. + (_initialize_alphafbsd_tdep): New function. + * config/alpha/tm-fbsd.h: Update copyright years. + (USE_STRUCT_CONVENTION): Remove. + +2002-04-21 Jason Thorpe + + * alpha-tdep.c (alpha_abi_handler): New structure to describe + an Alpha ABI variant. + (alpha_abi_handler_list): Declare. + (alpha_gdbarch_register_os_abi): New function. + (alpha_gdbarch_init): Give registered ABI variant handlers a + chance to tweak the gdbarch once we have set up defaults. + * alpha-tdep.h: Prototype alpha_gdbarch_register_os_abi. + +2002-04-21 Jason Thorpe + + * alpha-tdep.c (alpha_gdbarch_init): Set coerce_float_to_double + to standard_coerce_float_to_double. + * config/alpha/tm-alpha.h (COERCE_FLOAT_TO_DOUBLE): Remove. + +2002-04-21 Jason Thorpe + + * alpha-tdep.h (gdbarch_tdep): Add vm_min_address member. + * alpha-tdep.c (heuristic_proc_start): Use vm_min_address + from gdbarch_tdep rather than a constant. + (alpha_gdbarch_init): Initialize tdep->vm_min_address to + the default text address for all Alpha Unix ABIs. + (alpha_dump_tdep): Report the value of tdep->vm_min_address. + * config/alpha/tm-alpha.h (VM_MIN_ADDRESS): Delete. + +2002-04-21 Jason Thorpe + + * alpha-tdep.h: New file. Includes several Alpha target constants + taken from... + * config/alpha/tm-alpha.h: ...here. Remove macros that we now + let gdbarch deal with. + (GDB_MULTI_ARCH): Define as GDB_MULTI_ARCH_PARTIAL. + * Makefile.in (alpha-nat.o): Add alpha-tdep.h and $(BFD_SRC)/elf-bfd + to dependency list. + * alpha-nat.c: Include alpha-tdep.h. Update for adjusted + Alpha target register names. + * alphabsd-nat.c: Likewise. + * alpha-tdep.c: Include alpha-tdep.h. Update for adjusted + Alpha target register names. Make serveral routines static. + (alpha_get_saved_register): New function. + (alpha_abi_names): New. + (process_note_abi_tag_sections): New function. + (get_elfosabi): New function. + (alpha_gdbarch_init): New function. + (alpha_dump_tdep): New function. + (_initialize_alpha_tdep): Register alpha_gdbarch_init. + +2002-04-21 Andrew Cagney + + * frame.c (find_saved_register): Delete #ifdef + HAVE_REGISTER_WINDOWS code. + * config/sparc/tm-sparc.h: Update comments. + * config/i960/tm-i960.h (HAVE_REGISTER_WINDOWS): Delete macro. + +2002-04-21 Andrew Cagney + + * i960-tdep.c (i960_find_saved_register): New function. + (i960_get_saved_register): New function. + * config/i960/tm-i960.h (GET_SAVED_REGISTER): Define. + (i960_get_saved_register): Declare. + * config/i960/tm-i960.h, i960-tdep.c: Update copyright. + +2002-04-20 David S. Miller + + * sparc-nat.c (store-inferior_registers): Fix ambiguous else. + +2002-04-20 Andrew Cagney + + * arm-tdep.c (arm_gdbarch_init): Use gdbarch_num_pseudo_regs + instead of NUM_PSEUDO_REGS. + +2002-04-20 David S. Miller + + * config/sparc/tm-linux.h (GDB_MULTI_ARCH): Define to + GDB_MULTI_ARCH_PARTIAL + * config/sparc/tm-sp64linux.h (GDB_MULTI_ARCH): Do not + define, let tm-sp64.h do it. + +2002-04-20 Jason Thorpe + + * frame.c (find_saved_register): Avoid a NULL pointer + dereference and actually walk the frame list. + +2002-04-20 Andrew Cagney + + * gdbarch.sh (gdbarch_update_p): Keep the list of architectures + sorted in most most-recent-used order. Document. + * gdbarch.h, gdbarch.c: Regenerate. + +2002-04-19 Andrew Cagney + + * sparc-tdep.c (sparc_get_saved_register): Use get_prev_frame + instead of ->prev. + * z8k-tdep.c (z8k_frame_chain): Do not use ->prev. + * s390-tdep.c (s390_frame_chain): Do not use ->prev. + * rs6000-tdep.c (frame_get_saved_regs): Use rs6000_frame_chain() + instead of ->prev. + +2002-04-19 Elena Zannoni + + Fix PR gdb/471. + * gdbtypes.c (init_simd_type): Rewrite using new functions. + (build_builtin_type_vec128): Ditto. + (append_composite_type_field): Fix calculation of type length in + union case. + +2002-04-19 Eli Zaretskii + + * config/djgpp/README: Update. + + * go32-nat.c (store_register): Cast &a_tss to `char *' to avoid a + compiler warnings. + +2002-04-19 Jason Thorpe + + * alpha-tdep.c (setup_arbitrary_frame): Rename... + (alpha_setup_arbitrary_frame): ...to this. + * config/alpha/tm-alpha.h (SETUP_ARBITRARY_FRAME): Update + for alpha_setup_arbitrary_frame. + +2002-04-18 Andrew Cagney + + * gdbarch.sh (BREAKPOINT_FROM_PC): Return a const buffer. + * gdbarch.h, gdbarch.c: Regenerate. + + * defs.h (breakpoint_from_pc_fn): Delete type definition. + * target.h (memory_breakpoint_from_pc): Update declaration. + * config/mcore/tm-mcore.h (mcore_breakpoint_from_p): Ditto. + + * arch-utils.c (legacy_breakpoint_from_pc): Update return type. + * mcore-tdep.c (mcore_breakpoint_from_pc): Ditto. + * mem-break.c (memory_breakpoint_from_pc): Ditto. + * rs6000-tdep.c (rs6000_breakpoint_from_pc): Ditto. + * s390-tdep.c (s390_breakpoint_from_pc): Ditto + * xstormy16-tdep.c (xstormy16_breakpoint_from_pc): Ditto. + * mn10300-tdep.c (mn10300_breakpoint_from_pc): Ditto. + * mips-tdep.c (mips_breakpoint_from_pc): Ditto. + * m68hc11-tdep.c (m68hc11_breakpoint_from_pc): Ditto. + * ia64-tdep.c (ia64_breakpoint_from_pc): Ditto. + * d10v-tdep.c (d10v_breakpoint_from_pc): Ditto. + * arch-utils.c (legacy_breakpoint_from_pc): Ditto.. + + * mem-break.c (default_memory_insert_breakpoint): Make `bp' a + const pointer. + * monitor.c (monitor_insert_breakpoint): Ditto. + * rs6000-tdep.c (rs6000_software_single_step): Ditto for `breakp'. + + * config/mcore/tm-mcore.h: Update copyright. + * mem-break.c: Ditto. + * xstormy16-tdep.c: Ditto. + +2002-04-18 Pierre Muller + + * p-exp.y: Add precedence rule for '^' token. + This removes the shift/reduce conflicts. + Remove the comment concerning these shift/reduce conflicts. + +2002-04-18 Elena Zannoni + + * rs6000-tdep.c (COMMON_UISA_NOFP_REGS): New macro. + (registers_powerpc_nofp): New register set for processors + without floating point unit. + +2002-04-18 David S. Miller + + * MAINTAINERS: Add myself to write-after-approval. + +2002-04-17 Michael Snyder + + * MAINTAINERS: Add myself as co-maintainer of testsuite/gdb.asm. + +2002-04-17 Andrew Cagney + + * rs6000-tdep.c (frame_initial_stack_address): Use + frame_register_read to read the alloca_reg. + +2002-04-17 Andrew Cagney + + * frame.c (find_saved_register): Find saved registers in the next + not prev frame. + Fix PR gdb/365. + +2002-04-17 Andrew Cagney + + * gdbarch.sh (LANG): Set to ``c''. + +2002-04-15 Andrew Cagney + + * PROBLEMS: Mention hppa2.0-hp-hpux10.20 compile problems. + +2002-04-15 Andrew Cagney + + * bcache.c: Include and after "defs.h". + Update copyright. + + * hpread.c (hpread_get_lntt): Add declaration. + Also fix PR gdb/391. + +2002-04-14 Andrew Cagney + + * acinclude.m4 (AM_PROG_CC_STDC): Import from automake 1.6. + * aclocal.m4, configure: Re-generate. + Fix PR gdb/391. + +2002-04-14 Elena Zannoni + + * mi/mi-cmd-disas.c (dump_insns): Use TARGET_PRINT_INSN + instead of tm_print_insn. + +2002-04-14 Elena Zannoni + + * ppc-bdm.c (bdm_ppc_fetch_registers): Fix typo. + +2002-04-14 Andrew Cagney + + * config/pa/tm-hppa.h (FRAME_CHAIN_COMBINE): Delete macro. + * blockframe.c (FRAME_CHAIN_COMBINE): Delete macro. + (get_prev_frame): Do not call FRAME_CHAIN_COMBINE. + +2002-04-12 Don Howard + + * cli/cli-cmds.c (init_cli_cmds): Add new user settable value: + max_user_call_depth. + (init_cmd_lists): Initialize the new value; + * cli/cli-script.c (execute_user_command): Limit the call depth of + user defined commands. This avoids a core-dump when user commands + are infinitly recursive. + +2002-04-12 Kevin Buettner + + * ppc-tdep.h (struct gdbarch_tdep): Add new member ``lr_frame_offset''. + * rs6000-tdep.c (rs6000_frame_saved_pc): Use ``lr_frame_offset'' + from tdep struct instead of DEFAULT_LR_SAVE. + (rs6000_gdbarch_init): Initialize ``lr_frame_offset''. + * config/powerpc/tm-ppc-eabi.h (DEFAULT_LR_SAVE): Delete. + * config/rs6000/tm-rs6000.h (DEFAULT_LR_SAVE): Delete. + +2002-04-12 Michael Snyder + + * Remote.c: Spelling fix. + * gcore.c (default_derive_heap_segment): Use bfd_section_name. + If no symbol found for "sbrk", try "_sbrk". + (make_output_phdrs): Use bfd_section_name. + (gcore_copy_callback): Use bfd_section_name. + * eval.c: Indentation fix-ups. + * d10v-tdep.c (d10v_make_iaddr): Make it idempotent, + in case it gets applied to an address that is already + in the instruction space. + * cli/cli-decode.c (help_list): Allow long lines to wrap. + * symfile.c: Fix indentation, long lines. + * source.c: White space fix-up. + +2002-04-12 Andrew Cagney + + * defs.h (read_relative_register_raw_bytes): Delete declaration. + * frame.c (frame_register_read): New function. Return non-zero on + success. + (read_relative_register_raw_bytes_for_frame): Delete. + (read_relative_register_raw_bytes): Delete. + * frame.h (frame_register_read): Declare. + * d30v-tdep.c: Update Copyright. Use frame_register_read. + * sh-tdep.c: Ditto. + * infcmd.c (do_registers_info): Ditto. + * hppa-tdep.c: Ditto. + * rs6000-tdep.c: Ditto. + * h8500-tdep.c: Ditto. + * mips-tdep.c: Ditto. + * h8300-tdep.c: Ditto. + * z8k-tdep.c: Ditto. + +2002-04-12 Kevin Buettner + + From Jimi X : + * rs6000-tdep.c (rs6000_gdbarch_init): Use rs6000_* methods for + 64-bit SysV ABI. + +2002-04-12 Kevin Buettner + + From Jimi X : + * rs6000-tdep.c (rs6000_gdbarch_init): Compute ``wordsize'' from + bfd info. + +2002-04-12 Kevin Buettner + + From Jimi X : + * rs6000-tdep.c (powerpc64, 630, rs64ii, rs64iii): Define + register sets for these processor variants. + +2002-04-11 Daniel Jacobowitz + + * regformats/reg-ppc.dat: Support FPSCR. + +2002-04-11 Kevin Buettner + + * ppc-tdep.h (struct gdbarch_tdep): Add new field ``ppc_fpscr_regnum''. + * ppc-bdm.c (bdm_ppc_fetch_registers, bdm_ppc_store_registers): + Add fpscr as an invalid/unfetchable register. + * ppc-linux-nat.c (ppc_register_u_addr, store_register) + (fetch_ppc_registers, store_ppc_registers, supply_fpregset) + (fill_fpregset): Add support for register fpscr. + (fetch_ppc_registers, store_ppc_registers, supply_gregset) + (fill_gregset): Account for the fact that register ``mq'' might + not exist. + * rs6000-tdep.c (PPC_UISA_SPRS): Use (unused) slot 70 for fpscr. + (registers_power): Add fpscr to register set at slot 71. + (rs6000_gdbarch_init): Account for the fact that ``mq'' doesn't + exist on most PPC architectures. Initialize ppc_fpscr_regnum. + +2002-04-11 Michael Snyder + + * configure.in: Autoconfiscate _SYSCALL32 define for solaris. + * configure: Regenerate. + * config.in: Regenerate. + * acconfig.h: Add define for _SYSCALL32. + * core-sol2.c: Remove #define _SYSCALL32. + * solib-legacy.c: Remove #define _SYSCALL32. + +2002-04-10 Andrew Cagney + + * stack.c (select_frame): Cleanup internal error message, do not + use %p. + +2002-04-10 Andrew Cagney + + * stack.c (select_frame): Check that selected_frame and the + specified level are as expected. + * blockframe.c (get_prev_frame): Set the `level' from next_frame. + Update copyright. + * frame.h (struct frame_info): Add field `level'. Update + copyright. + Work-in-progress PR gdb/464. + +2002-04-10 Andrew Cagney + + * maint.c (maint_print_section_info): Rename print_section_info. + (print_bfd_section_info, print_objfile_section_info): Update. + * inferior.h (struct gdbarch): Add opaque declaration. + * gdbarch.sh: Add include of "inferior.h" to gdbarch.sh. + * gdbarch.h: Regenerate. + +2002-04-10 Michal Ludvig + + * x86-64-linux-nat.c (child_resume, child_xfer_memory): Delete. + (PTRACE_XFER_TYPE): Moved to config/i386/nm-x86-64.h. + (kernel_u_size): Added. + * config/i386/nm-x86-64.h (CHILD_XFER_MEMORY, CHILD_RESUME): Delete. + (PTRACE_XFER_TYPE): Moved here from config/i386/nm-x86-64.h. + +2002-04-04 Jim Ingham + + * valarith.c (find_size_for_pointer_math): New function, either returns + the size for a pointer's target, returns 1 for void *, or errors for + incomplete types. + (value_add, value_sub): use find_size_for_pointer_math. + +2002-04-09 Daniel Jacobowitz + + * linux-low.c (linux_look_up_symbols): New hook. + (linux_target_ops): Add linux_look_up_symbols. + * remote-utils.c (decode_address): New function. + (look_up_one_symbol): New function. + * server.c (handle_query): Call target look_up_symbols hook. + * server.h (look_up_one_symbol): Add prototype. + * target.h (struct target_ops): Add look_up_symbols hook. + +2002-04-09 Andrew Cagney + + * frame.c (read_relative_register_raw_bytes_for_frame): Do not + override FP_REGNUM with frame->fp. Update copyright. + * parse.c (num_std_regs, std_regs): Delete. + (target_map_name_to_register): Do not search std_regs. Update + function description. + * parser-defs.h (num_std_regs, std_regs, struct std_regs): Delete + declarations. Update copyright. + Fix PR gdb/251. + +2002-04-09 Daniel Jacobowitz + + * symtab.h (ALL_BLOCK_SYMBOLS): Don't dereference the pointer + after the last symbol in a block. + +2002-04-09 Pierre Muller + + * p-exp.y (yylex): Handle also the fact that is_a_field_of_this + is non zero as a found symbol. + +2002-04-08 Andrew Cagney + + * findvar.c: Include "builtin-regs.h". + (value_of_register): Call value_of_builtin_reg when applicable. + * parse.c: Include "builtin-regs.h" and "gdb_assert.h". + (target_map_name_to_register): Call + builtin_reg_map_name_to_regnum. + * Makefile.in (SFILES): Add builtin-regs.c and std-regs.c. + (COMMON_OBS): Add builtin-regs.o and std-regs.o. + (builtin_regs_h): Define. + (builtin-regs.o): New target. + (findvar.o): Add $(builtin_regs_h). + * builtin-regs.c, builtin-regs.h: New files. + * std-regs.c: New file. + Partial fix for PR gdb/251. + +2002-04-08 Kevin Buettner + + * rs6000-tdep.c (rs6000_gdbarch_init): Don't set tm_print_insn; + it's no longer required. + +2002-04-08 Andrew Cagney + + * Makefile.in (gdbtk-wrapper.o): Add missing dependencies. + +2002-04-08 Kevin Buettner + + From Jimi X : + * rs6000-tdep.c (rs6000_software_single_step): Use + rs6000_breakpoint_from_pc() to fetch breakpoint instruction + and size. Use target_insert_breakpoint() and + target_remove_breakpoint() to insert and remove breakpoints + instead of explicit memory reads and writes. + +2002-04-08 Kevin Buettner + + * config/powerpc/tm-ppc-eabi.h (ELF_OBJECT_FORMAT): Delete. + * rs6000-tdep.c (rs6000_push_arguments): Eliminate + ELF_OBJECT_FORMAT ifdef. + +2002-04-08 Kevin Buettner + + From Jimi X : + * rs6000-tdep.c (rs6000_gdbarch_init): Use set_gdbarch_print_insn(). + +2002-04-08 Kevin Buettner + + From Jimi X : + * rs6000-tdep.c (rs6000_fix_call_dummy): Delete unused macro + definitions for TOC_ADDR_OFFSET and TARGET_ADDR_OFFSET. + +2002-04-07 Mark Kettenis + + * fbsd-proc.c (child_pid_to_exec_file, fbsd_find_memory_regions): + s/asprintf/xasprintf/. + (fbsd_make_corefile_notes): s/strdup/xstrdup/. + +2002-04-07 Andrew Cagney + + I believe Jeff Law denies responsability for this one: + * config/pa/hpux11w.mh (MH_CFLAGS): Add -Dvfork=fork. + * config/pa/hpux11.mh (MH_CFLAGS): Add -Dvfork=fork. + * config/pa/hpux1020.mh (MH_CFLAGS): Add -Dvfork=fork. + Work-around for PR gdb/366. + +2002-04-07 Elena Zannoni + + * remote-e7000.c (write_small, e7000_read_inferior_memory, + e7000_read_inferior_memory_large, e7000_insert_breakpoint, + e7000_remove_breakpoint): Use paddr_nz() to print addresses. + +2002-04-07 Elena Zannoni + + * sh-tdep.c (sh_fp_frame_init_saved_regs, + sh_nofp_frame_init_saved_regs): Use alloca() for 'where' + information. + +2002-04-07 Andrew Cagney + + * MAINTAINERS (Misc): List Daniel Jacobowitz as the GDBSERVER + maintainer. + +2002-04-07 Andrew Cagney + + * README (Reporting Bugs in GDB): Document the bug web page as the + prefered way of submitting bugs. + Fix PR gdb/402. + +2002-04-06 Andrew Cagney + + * gdbarch.sh (FP_REGNUM, PC_REGNUM, SP_REGNUM): Allow default of + -1. Update comment. + * gdbarch.h, gdbarch.c: Re-generate. + +2002-04-07 Andreas Schwab + + * m68klinux-nat.c (fill_fpregset): Properly pass address of + buffer to regcache_collect. + +2002-04-06 Andrew Cagney + + * gdbarch.sh (PS_REGNUM): Add. Document. Default to -1. + * gdbarch.c, gdbarch.h: Re-generate. + +2002-04-06 Andrew Cagney + + * symtab.c (lookup_symtab): Remove ``const'' from ``rp'' + declaration. Fix -Werror. + +2002-04-05 Daniel Jacobowitz + + * gdbarch.sh (initialize_non_multiarch): Call init_gdbarch_swap. + * gdbarch.c: Regenerate. + +2002-04-05 Michael Snyder + + * breakpoint.c (clear_command): Rewrite middle section to + combine two loops with identical control conditions. + Add a cleanup to eliminate a memory leak. + * cli/cli-dump.c (restore_section_callback): Use paddr_nz. + +2002-04-05 H.J. Lu (hjl@gnu.org) + + * solib-svr4.c (bkpt_names): Add "__start". + +2002-04-04 Andrew Cagney + + * sparc-tdep.c (sparc_push_dummy_frame): Use GDB_TARGET_IS_SPARC64 + as test for 64 bit target. + +2002-04-05 Andrew Cagney + + * h8500-tdep.c (h8500_write_fp): Delete function. + * dwarf2cfi.c (cfi_write_fp): Document as not used. + * mips-tdep.c (mips_gdbarch_init): Do not set write_fp. + * ia64-tdep.c (ia64_gdbarch_init): Do not set write_fp. + * m68hc11-tdep.c (m68hc11_gdbarch_init): Do not set write_fp. + * rs6000-tdep.c (rs6000_gdbarch_init): Do not set write_fp. + * s390-tdep.c (s390_gdbarch_init): Do not set write_fp. + (s390_write_fp): + * sh-tdep.c (sh_gdbarch_init): Do not set write_fp. + * x86-64-tdep.c (i386_gdbarch_init): Do not set write_fp. + * d10v-tdep.c (d10v_gdbarch_init): Do not set write_fp. + (d10v_write_fp): Delete function. + * inferior.h (write_fp, generic_target_write_fp): Delete + declarations. + * regcache.c (generic_target_write_fp): Delete function. + (write_fp): Delete function. + * gdbarch.sh (TARGET_WRITE_FP): Delete. + * gdbarch.h, gdbarch.c: Regenerate. + * config/v850/tm-v850.h (TARGET_WRITE_FP): Delete macro. + * config/sparc/tm-sp64.h (TARGET_WRITE_FP): Delete macro. + (sparc64_write_fp): Delete declaration. + * config/h8500/tm-h8500.h (TARGET_WRITE_FP): Delete macro. + (h8500_write_fp): Delete declaration. + +2002-04-04 Andrew Cagney + + * sparc-tdep.c (sparc64_write_fp): Delete. + (sparc_push_dummy_frame): Replace write_fp call with code to store + the FP directly. + (sparc_gdbarch_init): Do not initialize write_fp. + +2002-04-05 Kevin Buettner + + * rs6000-tdep.c (skip_prologue): Eliminate unused/unreachable + clause. + +2002-03-29 Jim Blandy + + * stack.c (get_selected_block): Add new argument `addr_in_block', + used to return the exact code address we used to select the block, + not just the block. + * blockframe.c (get_frame_block, get_current_block): Same. + * frame.h (get_frame_block, get_current_block, + get_selected_block): Update declarations. + * linespec.c, stack.c, blockframe.c, breakpoint.c, findvar.c, + linespec.c, varobj.c, printcmd.c, symtab.c: Callers changed. + +2002-04-05 Michael Snyder + + * breakpoint.c (insert_breakpoints): Change 'hw' to 'hardware in + warning message. + +2002-04-05 J. Brobecker + + * utils.c (xfullpath): New function. + * defs.h (xfullpath): Add declaration. + * source.c (openp): Use xfullpath in place of gdb_realpath to + avoid resolving the basename part of filenames when the + associated file is a symbolic link. This fixes a potential + inconsistency between the filenames known to GDB and the + filenames it prints in the annotations. + * symtab.c (lookup_symtab): Use the new xfullpath function, in order + to be able to match a filename with either the real filename, or + the name of any symbolic link to this file. + (lookup_partial_symtab): Ditto. + +2002-04-04 Michael Snyder + + * breakpoint.c: Add support for hardware breakpoints in overlays. + (overlay_events_enabled): New state variable. + (insert_breakpoints): Use overlay_events_enabled to decide + whether to attempt to set a breakpoint at the overlay load addr. + Handle bp_hardware_breakpoint as well as bp_breakpoint. + (remove_breakpoint): Use overlay_events_enabled to decide + whether breakpoints need to be removed from overlay load addr. + Handle bp_hardware_breakpoint as well as bp_breakpoint. + (bpstat_stop_status): Handle bp_hardware_breakpoint in overlays. + (create_overlay_event_breakpoint, enable_overlay_breakpoints, + disable_overlay_breakpoints): Update overlay_events_enabled. + +2002-04-04 Daniel Jacobowitz + + * dwarf2read.c (struct function_range): New. + (cu_first_fn, cu_last_fn, cu_cached_fn): New. + (check_cu_functions): New. + (read_file_scope): Initialize global function lists. + Call dwarf_decode_line after processing children. + (read_func_scope): Add to global function list. + (dwarf_decode_lines): Call check_cu_functions everywhere + record_line is called. Call record_line with a linenumber + of 0 to mark sequence ends. + +2002-04-04 Michal Ludvig + + * x86-64-linux-nat.c (child_xfer_memory): x86-64 ptrace() ABI + change sync with glibc. + +2002-04-03 Jim Blandy + + * configure.in: Call AC_C_INLINE. + * configure: Regenerated. + +2002-04-01 Daniel Jacobowitz + + * rs6000-tdep.c: Change #include of "bfd/libcoff.h" + and "bfd/libbfd.h" to "libcoff.h" and "libbfd.h". + +2002-03-31 Mark Kettenis + + * NEWS: Mention gcore support on FreeBSD/i386. + + * fbsd-proc.c: New file. + * config/i386/nm-fbsd.h (CHILD_PID_TO_EXEC_FILE): Define. + * config/i386/fbsd.mh (NATDEPFILES): Add gcore.o and fbsd-proc.o. + + * lin-lwp.c (child_wait): Check SAVE_ERRNO instead of ERRNO in + while statement. + +2002-03-29 Jim Blandy + + * cli/cli-dump.c (_initialize_cli_dump): Older GCC's tolerate + unescaped newlines in string literals, but newer ones don't. So + escape them. + +2002-03-26 Michael Snyder + Andrew Cagney + + * cli/cli-dump.c: New file. Dump memory to file, + restore file to memory. + * cli/cli-dump.h: New file. + * Makefile.in: Add rules, dependencies for cli-dump.o. + * NEWS: Mention new commands. + +2002-03-28 Michael Snyder + + * symfile.c (symbol_file_add): Move test for null symbols to later. + +2002-03-27 Andrew Cagney + + From veksler at il.ibm.com: + * utils.c (gdb_realpath): If canonicalize_file_name fails, return + the xstrduped original path. + Fix PR gdb/417. + +2002-03-27 Michael Snyder + + * breakpoint.c (_initialize_breakpoint): Clean up help string. + * infcmd.c (_initialize_infcmd): Ditto. + * language.c (_initialize_language): Ditto. + * symfile.c (_initialize_symfile): Ditto. + * top.c (_init_main): Ditto. + * cli/cli-cmds.c (init_cli_cmds): Ditto. + +2002-03-27 Elena Zannoni + + * rs6000-tdep.c (struct rs6000_framedata): Add fields for AltiVec + vector registers handling. + (skip_prologue): Handle new AltiVec instructions. Fill in new + fields of frame data. + (frame_get_saved_regs): Fill in information for AltiVec registers. + +2002-03-27 Jim Blandy + + * symtab.h (SYMBOL_INIT_MANGLED_NAME): Turn this macro's body into + a function; leave this macro here to invoke that function. + (symbol_init_mangled_name): Declaration for that function. + * symtab.c (symbol_init_mangled_name): New function. + +2002-03-27 Andrew Cagney + + * valarith.c: Replace strerror with safe_strerror. + * tracepoint.c: Ditto. + * lin-lwp.c: Ditto. + * go32-nat.c: Ditto. + * inflow.c: Ditto. + * gnu-nat.c: Ditto. + +2002-03-27 Andreas Schwab + + * event-top.c (command_line_handler): Remove useless if. + +2002-03-27 Andreas Jaeger + + * dwarf2cfi.c: Give credit to Daniel Berlin, reformat copyright + comment. + +2002-03-27 Michal Ludvig + + * x86-64-tdep.h (X86_64_NUM_REGS, X86_64_NUM_GREGS): Delete #defines. + (x86_64_num_regs, x86_64_num_gregs): Added extern variables. + * x86-64-linux-nat.c (x86_64_regmap): Swapped RBX <> RDX, added DS, ES, FS, GS. + (x86_64_linux_dr_get_status, supply_gregset), + (fill_gregset): Changed X86_64_NUM_GREGS to x86_64_num_gregs. + * x86-64-tdep.c (x86_64_register_raw_size_table): Delete. + (x86_64_register_info_table): Add. + (X86_64_NUM_REGS, X86_64_NUM_GREGS): Add. + (x86_64_register_raw_size, x86_64_register_virtual_type), + (x86_64_register_name, _initialize_x86_64_tdep): Changed to reflect new + general x86_64_register_info_table. + (i386_gdbarch_init): gdbarch_register_bytes is now set + dynamicaly during initialization. + * regformats/reg-x86-64.dat: Synced with changes to registers above. + * gdbserver/linux-x86-64-low.c: Ditto. + +2002-03-27 Daniel Jacobowitz + + * gdbserver/server.c (main): Call target_signal_to_host_p + and target_signal_to_host on signals received from the remote. + * gdbserver/remote-utils.c (prepare_resume_reply): Call + target_signal_from_host on signals sent to the remote. + * gdbserver/server.h: Add prototypes. Include "gdb/signals.h". + * gdbserver/Makefile.in: Add signals.o. Add -I${INCLUDE_DIR}. + +2002-03-27 Daniel Jacobowitz + + * signals/signals.c: Include "server.h" in gdbserver build. + (target_signal_from_name): Don't use STREQ. + (_initialize_signals): Likewise. Don't include function in + gdbserver build. + +2002-03-27 Daniel Jacobowitz + + * signals.c: Moved to... + * signals/signals.c: Here. + * Makefile (signals.o): Update. + +2002-03-26 Jeff Law (law@redhat.com) + + * somread.c (som_symtab_read): Remove some commented out code and + updated related comments. Do not set the minimal symbol table to + mst_solib_trampoline for ST_ENTRY symbols with SS_LOCAL scope + in a dynamic executable. + * hppa-tdep.c (find_proc_framesize): Sanely handle the case + where we are unable to find the minimal symbol for the given + PC value. + +2002-03-25 Jeff Law (law@redhat.com) + + * linux-proc.c (read_mapping): Scan up to end of line for filename. + +2002-03-25 Michal Ludvig + + * x86-64-tdep.c (x86_64_skip_prologue): Rewritten from scratch. + +2002-03-23 Andrew Cagney + + * command.h: Update copyright. + (struct cmd_list_element): Replace definition with opaque + declaration. + (enum cmd_types): Document that it will eventually be moved to + cli/cli-decode.h + (CMD_DEPRECATED, DEPRECATED_WARN_USER): Delete macros. + (MALLOCED_REPLACEMENT): Delete macro. + * Makefile.in (cli_decode_h): Add $(command_h). + (top.o, completer.o, maint.o): Add dependency on $(cli_decode_h). + * top.c: Include "cli/cli-decode.h". + * completer.c: Include "cli/cli-decode.h". + * maint.c: Include "cli/cli-decode.h". + * cli/cli-decode.h: Include "command.h". + (enum command_class): Delete. + (enum cmd_types): Comment out. + (enum cmd_auto_boolean): Delete. + (enum var_types): Delete. + +2002-03-23 Andrew Cagney + + * cli/cli-decode.c: Include "gdb_assert.h". + (add_set_or_show_cmd): New static function. + (add_set_cmd): Rewrite. Use add_set_or_show_cmd. + (add_show_from_set): Rewrite. Use add_set_or_show_cmd. Don't copy + all fields, such as func, from the set command. + +2002-03-23 Andrew Cagney + + * MAINTAINERS (sh-elf): Change warning flag to -w. + +2002-03-23 Andrew Cagney + + * defs.h (error): Add printf format attribute. + * thread-db.c (thread_from_lwp): Fix error format string. + * stack.c (parse_frame_specification): Ditto. + * cli/cli-decode.c (undef_cmd_error): Ditto. + * scm-lang.c (scm_lookup_name): Ditto. + * tracepoint.c (trace_error): Ditto. + * remote-utils.c (usage): Ditto. + * remote.c (compare_sections_command): Ditto. + Fix PR gdb/328. + +2002-03-22 Andrew Cagney + + * gdbtypes.c (append_composite_type_field): New function. + (init_composite_type): New function. + * gdbtypes.h (append_composite_type_field): Declare. + (init_composite_type): Ditto. + +2002-03-22 Elena Zannoni + + * ppc-linux-tdep.c (ppc_sysv_abi_use_struct_convention): New + function. + * ppc-tdep.h (ppc_sysv_abi_use_struct_convention): Export. + * rs6000-tdep.c (rs6000_gdbarch_init): Use different + structure returning convention for SYSV ABI case, but not + for GNU/Linux, FreeBSD, or NetBSD. + +2002-03-22 Daniel Jacobowitz + + * symtab.h (lookup_block_symbol): Add mangled_name argument + to prototype. + + * symmisc.c (maintenance_check_symtabs): Call lookup_block_symbol + with new mangled_name argument. + * linespec.c (decode_line_1): Likewise. + * valops (value_of_this): Likewise. + * symtab.c (lookup_transparent_type): Likewise. + (lookup_symbol_aux): Likewise. Accept new mangled_name argument. + (lookup_symbol): If we are given a mangled name, pass it down + to lookup_symbol_aux. + (lookup_block_symbol): If we are given a mangled name to check + against, only return symbols which match it. + +2002-03-22 Christopher Faylor + + * win32-nat.c (child_create_inferior): Check for proper shell to use + here, in case the user changes it on the fly. + (_initialize_inftarg): Remove shell path considerations. + +2002-03-21 Elena Zannoni + + * rs6000-tdep.c (rs6000_gdbarch_init): Use correct max size value + for gdbarch_max_register_raw_size and max_register_virtual_size. + Adjust copyright year. + +2002-03-21 Daniel Jacobowitz + + * dbxread.c (process_one_symbol): Extend the first N_SLINE + in a function to cover the entire beginning of the function + as well if it does not already. + +2002-03-21 Tom Rix + + * rs6000-nat.c (rs6000_ptrace32): Renamed from ptrace32. + (rs6000_ptrace64): Renamed from ptrace64. + +2002-03-20 Martin M. Hunt + + * gdbserver/remote-utils.c (remote_open): Don't call + getprotobyname, we're all using TCP here so just use + IPPROTO_TCP. + * gdbserver/gdbreplay.c (remote_open): Ditto. + +2002-03-20 Martin M. Hunt + + * regcache.c (_initialize_regcache): No need to call + build_regcache() at this time; it gets called whenever + the gdbarch changes. + +2002-03-20 David O'Brien + + * sparc-nat.c: Include sys/param.h where possible. + +2002-03-20 Daniel Jacobowitz + + Fix PR gdb/422. + * c-lang.c (c_create_fundamental_type): Handle FT_COMPLEX, + FT_DBL_PREC_COMPLEX, and FT_EXT_PREC_COMPLEX. + * dwarf2read.c (read_base_type): Set TYPE_TARGET_TYPE for + complex types. + * stabsread.c (rs6000_builtin_type): Likewise. + (read_sun_floating_type): Likewise. + +2002-03-19 Peter Schauer + + * stabsread.c (read_member_functions): Remove skip code for duplicate + constructor/destructor methods. Use standard parsing for these + methods and just do not chain them to the list of methods after + parsing. + +2002-03-19 Alexandre Oliva + + * coffread.c: Remove redundant static declarations. Replace + occurrences of `PTR' with `void *'. + * elfread.c, mdebugread.c, minsyms.c, mipsread.c: Likewise. + * top.h (quit_cover): Likewise. + * defs.h (catch_errors): Likewise. + +2002-03-18 Andrew Cagney + + * defs.h (XMALLOC): Define. + * gdb-events.sh (XMALLOC): Delete macro. + * gdb-events.c, gdb-events.h: Regenerate. + * gdbarch.sh (XMALLOC): Delete macro. + * gdbarch.c: Regenerate. + * serial.c (XMALLOC): Delete macro. + * ui-file.c (XMALLOC): Ditto. + * ser-unix.h (XMALLOC): Ditto. + * sh-tdep.c (XMALLOC): Ditto. + * ui-out.c (XMALLOC): Ditto. + * utils.c (XMALLOC): Ditto. + * i386-tdep.c (XMALLOC): Ditto. + * gdb-events.c (XMALLOC): Ditto. + * d10v-tdep.c (XMALLOC): Ditto. + * cli-out.c (XMALLOC): Ditto. + + * cli-out.c, d10v-tdep.c, gdb-events.c: Update copyright. + * gdb-events.sh, i386-tdep.c, ser-unix.h, serial.c: Ditto. + * ui-file.c, ui-out.c: Ditto. + +2002-03-18 Andrew Cagney + + * command.h (struct cmd_list_element): Add field context. + (set_cmd_context, get_cmd_context): Declare. + * cli/cli-decode.h: Ditto. + * cli/cli-decode.c (get_cmd_context): New function. + (set_cmd_context): New function. + (add_cmd): Initialize context. + Part of fixing PR gdb/145 and PR gdb/146. + +2002-03-17 Andrew Cagney + + * cli/cli-decode.c (cmd_type): New function. + * command.h (cmd_type): Declare. + * infrun.c (set_schedlock_func): Call function cmd_type. + * kod.c (kod_set_os): Call cmd_type. + * cris-tdep.c (cris_version_update): Use function cmd_type. + (cris_mode_update, cris_abi_update): Ditto. + + * command.h: (execute_cmd_post_hook): Declare. + (execute_cmd_pre_hook): Declare. + * cli/cli-script.c (clear_hook_in_cleanup): New function. + (execute_cmd_post_hook, execute_cmd_pre_hook): New + functions. Execute pre/post hook while ensuring that afterwords + hook_in is cleared. + * top.c (execute_command): Use execute_cmd_post_hook, and + execute_cmd_pre_hook to execute pre/post commands. + * infrun.c (normal_stop): Pass stop_command and not pre_hook to + hook_stop_stub. + (hook_stop_stub): Call execute_cmd_pre_hook. + +2002-03-17 Andrew Cagney + + * kod.c (kod_set_os): Revert previous change. Is called by ``info + set'' and this leads to a core dump. Move xstrdup of + operating_system to after check that it is not NULL. + +2002-03-17 Andrew Cagney + + * kod.c (kod_set_os): Remove unnecessary check that + ``command->type'' is set_cmd. + + * valprint.c (set_input_radix): Use input_radix. + (set_output_radix): Use output_radix. + (set_input_radix_1, set_output_radix_1): Add FIXME - bad radix + isn't reverted. + +2002-03-16 Andrew Cagney + + * value.h (struct value): Delete field ``substring_addr''. Change + aligner fields to force_doublest_align, force_longest_align, + force_core_addr_align and force_pointer_aligh. + + * value.h (struct value): Fix typo in above change. + +2002-03-16 Peter Schauer + + * ia64-tdep.c (ia64_gdbarch_init): Call set_gdbarch_frame_args_skip, + to fix internal_error from ``maintenance print architecture''. + +2002-03-16 Peter Schauer + + * cp-valprint.c (cp_is_vtbl_ptr_type): Handle vtbl field type + for gcc versions after gcc-2.8.1. + +2002-03-16 Peter Schauer + + * eval.c (evaluate_subexp_standard): Fix setup of ``this'' pointer + for method resolution. Restore adjustment of ``this'' pointer after + calling value_struct_elt, which was accidentally removed during the + HP merge. + +2002-03-15 Andrew Cagney + + * eval.c (evaluate_subexp_standard): Pass ``selected_frame'' to + value_of_register. + * findvar.c (value_of_register): Add ``frame'' parameter. Pass to + get_saved_register. + * value.h (value_of_register): Update. + +2002-03-14 Richard Henderson + + * configure.in: Detect declaration for canonicalize_file_name. + * utils.c (canonicalize_file_name): Declare, if needed. + (gdb_realpath): Prefer realpath if available and usable. + * config.in, configure: Rebuild. + +2002-03-14 Richard Henderson + + * dwarf2read.c (read_array_type): Accept DW_FORM_data8 as + a constant array bound. + + * MAINTAINERS: Add myself to write-after-approval. + +2002-03-14 Michael Snyder + + * symfile.c (syms_from_objfile): Return immediately if no syms. + (symbol_file_add): Return immediately if no syms. + (find_sym_fns): Return immediately if no syms. + +2002-03-13 Michal Ludvig + + * gdbserver/remote-util.c (remote_open): Print remote-side's + IP address when remote debugging over the network. + +2002-03-12 David O'Brien + + * config/sparc/fbsd.mh: Fix copyright. + * config/sparc/fbsd.mt: Likewise. + +2002-03-11 Richard Earnshaw + + * MAINTAINERS: Fix typo in name of gdb warnings option. + (x86-64): Fix formating so that this can be parsed by awk. + +2002-03-10 Daniel Jacobowitz + + * Makefile.in (defs_h): Add $(INCLUDE_DIR)/gdb/signals.h. + * defs.h: Include "gdb/signals.h". + (enum target_signal): Move to $(INCLUDE_DIR)/gdb/signals.h. + +2002-03-10 Michal Ludvig + + * x86-64-tdep.h (sys/reg.h, x86_64_regmap): Moved to x86-64-linux-nat.c + * x86-64-linux-nat.c (sys/reg.h, x86_64_regmap): Moved here + from x86-64-tdep.h + +2002-03-10 Daniel Jacobowitz + Don Howard + + * mips-tdep.c (ST0_FR): Define. + (mips2_fp_compat): New function, temporarily disabled. + (mips_read_fp_register_single): New function. + (mips_read_fp_register_double): New function. + (mips_print_register): Use them. + (do_fp_register_row): Likewise. + +2002-03-09 Andrew Cagney + + * MAINTAINERS: Add Jim Ingham and Klee Dienes to ``write after + approval''. + +2002-03-08 Peter Schauer + + * stabsread.c (read_member_functions): Fix is_stub test for + static member functions, improve comment. + +2002-03-07 Richard Earnshaw + + * remote-rdi.c (myprint): Replace 'PTR' with 'void *'. + (mywrite, mywritec, mypause, myreadc, mygets): Likewise. + (_initialize_remote_rdi): Use add_set_boolean_cmd to register + commands that set boolean values. + (arm_rdi_remove_breakpoint): Rewrite to avoid uninitialized warning. + (arm_rdi_resume): Always initialize PC. + (arm_rdi_open): Don't use rslt as a boolean. + (arm_rdi_create_inferior, arm_rdi_close, arm_rdi_resume) + (arm_rdi_fetch_registers, arm_rdi_store_registers) + (arm_rdi_xfer_memory, arm_rdi_files_info, arm_rdi_kill) + (arm_rdi_insert_breakpoint, arm_rdi_remove_breakpoint): Likewise. + +2002-03-06 Alexandre Oliva + + * configure.in (gdb_cv_bigtoc): Check for -bbigtoc on AIX. + * configure: Rebuilt. + +2002-03-06 Stephane Carrez + + * m68hc11-tdep.c (_initialize_m68hc11_tdep): Don't set tm_print_insn. + (m68hc11_gdbarch_init): But use set_gdbarch_print_insn instead. + +2002-03-06 Andrew Cagney + + * cli/cli-decode.c (set_cmd_completer): New function. + * command.h (set_cmd_completer): Declare. + * cli/cli-decode.h (set_cmd_completer): Ditto. + + * breakpoint.c (_initialize_breakpoint): Use set_cmd_completer. + * cli/cli-cmds.c (init_cli_cmds): Ditto. + * win32-nat.c (_initialize_inftarg): Ditto. + * remote-rdi.c (_initialize_remote_rdi): Ditto. + * proc-api.c (_initialize_proc_api): Ditto. + * hppa-tdep.c (_initialize_hppa_tdep): Ditto. + * source.c (_initialize_source): Ditto. + * exec.c (_initialize_exec): Ditto. + * solib.c (_initialize_solib): Ditto. + * top.c (init_main): Ditto. + * tracepoint.c (_initialize_tracepoint): Ditto. + * symfile.c (_initialize_symfile): Ditto. + * printcmd.c (_initialize_printcmd): Ditto. + * infcmd.c (_initialize_infcmd): Ditto. + * corefile.c (_initialize_core): Ditto. + +2002-03-05 Andrew Cagney + + * MAINTAINERS (Past Maintainers): Add Frank Ch. Eigler. + +2002-03-05 Andrew Cagney + + * MAINTAINERS: Fix Mac OS X and Objective-C/C++. + +2002-03-05 Andrew Cagney + + * NEWS: Update headings, 5.2 has branched. + +2002-03-04 Daniel Jacobowitz + + * gdbserver/linux-low.c (PTRACE_XFER_TYPE): Change to long. + (num_regs, regmap): Move inside HAVE_LINUX_USRREGS. + (register_addr, REGISTER_RAW_SIZE): Likewise. + (usr_store_inferior_registers): Use PTRACE_XFER_TYPE. + * gdbserver/linux-x86-64-low.c: Remove extra #endif. + +2002-03-03 Michal Ludvig + + * MAINTAINERS (x86-64): Add myself. + * x86-64-tdep.c (x86_64_push_arguments): Fixed typo naregs->nregs, + changed value_ptr -> struct value * + +2002-03-01 David O'Brien + + * configure.host (sparc64-*-freebsd): Add. + * configure.tgt: Likewise. + * config/sparc/fbsd.mh: New file. + * config/sparc/fbsd.mt: Likewise. + * config/sparc/nm-fbsd.h: Likewise. + * config/sparc/tm-fbsd.h: Likewise. + +2002-03-01 Daniel Jacobowitz + + * config/djgpp/fnchange.lst: Add regformats/reg-i386-linux.dat and + regformats/reg-s390x.dat. + +2002-03-01 Andrew Cagney + + * utils.c: Add FIXME explaining true/false problem. + +2002-02-28 Andrew Cagney + + * MAINTAINERS (Past Maintainers): Add J.T. Conklin. + +2002-02-28 Michael Chastain + + * MAINTAINERS: Fix typo: gdb.satbs -> gdb.stabs . + +2002-02-28 Daniel Jacobowitz + + * gdbserver/linux-s390-low.c: New file. + * regformats/reg-s390.dat: New file. + * regformats/reg-s390x.dat: New file. + * gdbserver/configure.srv: Add S/390. + * gdbserver/Makefile.in: Add S/390. + * configure.tgt: Enable gdbserver for S/390. + +2002-02-28 Eli Zaretskii + + * go32-nat.c (_initialize_go32_nat): Don't use periods in the + first line of the doc string for "info dos", except at the end of + the sentence, since the short help stops at the first period. + +2002-02-28 Jason Merrill + + * dwarf2read.c (dwarf_cfi_name): Add new codes. + +2002-02-27 Fred Fish + + * blockframe.c (generic_fix_call_dummy): Fix obvious typo in + comment (dumy -> dummy). + +2002-02-27 Peter Schauer + + * symtab.c (gdb_mangle_name): Handle fully mangled v3 abi physnames. + +2002-02-27 Rodney Brown + + * utils.c (gdb_realpath): Add pathconf fallback for sco3.2v5. + +2002-02-27 Daniel Jacobowitz + + * gdbserver/acconfig.h: New file. + * gdbserver/i387-fp.c: New file. + * gdbserver/i387-fp.h: New file. + * gdbserver/linux-x86-64.c: New file. + * regformats/reg-x86-64.dat: New file. + * configure.tgt: Add x86_64-*-linux* gdbserver support. + * gdbserver/configure.srv: Add x86_64-*-linux* and regset support. + * gdbserver/configure.in: Add support for regsets. + * gdbserver/config.in: Regenerate. + * gdbserver/configure: Regenerate. + * gdbserver/Makefile.in: Likewise. Add $(linux_low_h). + * gdbserver/linux-low.h: New file. + * gdbserver/linux-low.c: Include "linux-low.h". Add support + for regsets. + * gdbserver/linux-arm-low.c: Include "linux-low.h". + * gdbserver/linux-ia64-low.c: Include "linux-low.h". + * gdbserver/linux-m68k-low.c: Include "linux-low.h". + * gdbserver/linux-mips-low.c: Include "linux-low.h". + * gdbserver/linux-ppc-low.c: Include "linux-low.h". + * gdbserver/linux-sh-low.c: Include "linux-low.h". + * gdbserver/linux-i386-low.c: Include "linux-low.h". Include + "i387-fp.h". Add PTRACE_GETREGS and friends. + * gdbserver/regcache.c (supply_register): New function. + (supply_register_by_name): New function. + (collect_register): New function. + (collect_register_by_name): New function. + +2002-02-27 Daniel Jacobowitz + + * gdbserver/Makefile.in (INTERNAL_CFLAGS): Remove -DGDBSERVER. + (config.status): Add configure.srv dependency. + (server_h): Add config.h dependency. + +2002-02-27 Daniel Jacobowitz + + * regformats/reg-i386-linux.dat: New file, with $orig_eax. + * gdbserver/Makefile.in: Add rules for reg-i386-linux.o. + * gdbserver/configure.srv: Change i386-*-linux* to use + reg-i386-linux.o. + +2002-02-26 Andrew Cagney + + * x86-64-tdep.c: Re-indent. Update copyright date. + +2002-02-26 Andrew Cagney + + From Michal Ludvig : + * x86-64-tdep.c (value.h): Delete. + (gdb_assert.h): Include. + (x86_64_register_convert_to_virtual, + x86_64_register_convert_to_raw ): Add check which lets only + floating-point values to be converted. + (value_push): Delete. + (x86_64_push_arguments): Order of arguments pushed on stack fixed. + (i386_gdbarch_init): Number of register_bytes fixed. + +2002-02-26 Andrew Cagney + + * MAINTAINERS: Add x86-64 target. + +2002-02-26 Andrew Cagney + + * memattr.c (mem_command): Eliminate ``true'' and ``false''. + * osfsolib.c (solib_map_sections): Ditto. + * irix5-nat.c (solib_map_sections): Ditto. + * corelow.c (gdb_check_format): Ditto. + * symfile.c (symfile_bfd_open): Ditto. + * solib.c (solib_map_sections): Ditto. + Fix PR gdb/354. + +2002-02-26 Andrew Cagney + + * remote.c (_initialize_remote): By default, disable ``e'' and + ``E'' step out-of-range packets. + +2002-02-26 Andreas Schwab + + * config/m68k/tm-linux.h (FRAME_SAVED_PC): Define as + m68k_linux_frame_saved_pc. + (IN_SIGTRAMP): Define as m68k_linux_in_sigtramp instead of + in_sigtramp. + (SIGCONTEXT_PC_OFFSET): Remove. + * m68klinux-nat.c (m68k_linux_frame_saved_pc, + m68k_linux_sigtramp_saved_pc): New functions. + (IS_SIGTRAMP, IS_RT_SIGTRAMP): Define. + (SIGCONTEXT_PC_OFFSET): Moved here from config/m68k/tm-linux.h. + (UCONTEXT_PC_OFFSET): Define. + (m68k_linux_in_sigtramp): Renamed from in_sigtramp, handle both + non-RT and RT signal trampolines. + +2002-02-26 Richard Earnshaw + + * config/arm/tm-embed.h (TARGET_UPAGES): Delete. + (TARGET_NBPG, STACK_END_ADDR): Delete + (VARIABLES_INSIDE_BLOCK): Delete. + +2002-02-25 Andrew Cagney + + * utils.c (perror_with_name): Make string parameter constant. + (print_sys_errmsg): Ditto. + (query): Ditto. + * defs.h (perror_with_name): Update. + (print_sys_errmsg): Update. + (query): Update. + +2002-02-25 Daniel Jacobowitz + + From Eliot Dresselhaus : + * gdbserver/linux-mips-low.c (cannot_fetch_register): Fix typo. + +2002-02-25 Peter Schauer + + * rs6000-nat.c (set_host_arch): Do not switch to a new architecture + if it already matches the current architecture from the exec file. + Include arch-utils.h for gdbarch_info_init prototype. + * Makefile.in (rs6000-nat.o): Update dependencies. + +2002-02-25 Eli Zaretskii + + * config/djgpp/djconfig.sh: Set NM=nm and CFLAGS="-g -O2" in the + list of exported variables. + +2002-02-24 Daniel Jacobowitz + + * gdbserver/configure.srv: New file. + * gdbserver/configure.in: Use configure.srv instead + of the host/target makefile fragments. Set GDBSERVER_DEPFILES + from it. + * gdbserver/configure: Regenerated. + * gdbserver/terminal.h: New file. + * gdbserver/Makefile.in: Update for configure changes. Remove + more unneeded include paths. + +2002-02-24 Andrew Cagney + + From wiz at danbala: + * config/sparc/tm-sp64.h: Fix grammar and typos. + Fix PR gdb/287. + +2002-02-24 Andrew Cagney + + * lin-lwp.c, thread-db.c, defs.h, cris-tdep.c: Replace ``Linux'' + with either ``GNU/Linux'' or ``Linux kernel''. Update copyright. + * m68klinux-nat.c, sparc-linux-nat.c, x86-64-linux-nat.c: Ditto. + * x86-64-linux-tdep.c, gregset.h, gdb_wait.h: Ditto. + * ia64-linux-nat.c, infrun.c, linux-proc.c: Ditto. + * proc-service.c, i386-linux-tdep.c, ppc-linux-tdep.c: Ditto. + * s390-tdep.c: Ditto. + * config/nm-linux.h, config/alpha/nm-linux.h: Ditto. + * config/alpha/tm-alpha.h, config/alpha/tm-alphalinux.h: + * config/alpha/xm-alphalinux.h, config/i386/nm-linux.h: Ditto. + * config/i386/nm-x86-64.h, config/i386/tm-linux.h: Ditto. + * config/m68k/tm-linux.h, config/mips/nm-linux.h: Ditto. + * config/mips/tm-linux.h, config/mips/xm-linux.h: Ditto. + * config/powerpc/tm-linux.h, config/s390/nm-linux.h: Ditto. + * config/s390/tm-linux.h, config/sh/tm-linux.h: Ditto. + * config/sparc/nm-linux.h, config/sparc/tm-linux.h: Ditto. + * config/sparc/tm-sp64linux.h, config/sparc/xm-linux.h: Ditto. + Fix PR gdb/378. + +2002-02-23 Andrew Cagney + + * lin-thread.c: Delete file. + * configure.in (gdb_cv_struct_reg_r_gs): Update comment to refer + to gdb_proc_service.h. + * configure: Re-generate. + + * ocd.c (ocd_open): Do not try to open the "ocd" device. + * serial.c (serial_open): Delete check for "ocd". + Fix PR gdb/349. + + * Makefile.in (linux-thread.o): Delete target. + * linux-thread.c: Delete file. + + * config/djgpp/fnchange.lst: Rename bfd/elf32-sh64.c. Tweak other + renamed SH files to be consistent. + + * symtab.c (sort_search_symbols): Use xfree. + +2002-02-23 Richard Earnshaw + + * arm-linux-tdep.c (arm_linux_init_abi): Register + IN_SOLIB_CALL_TRAMPOLINE and SKIP_TRAMPOLINE_CODE + * config/arm/tm-linux.h (IN_SOLIB_CALL_TRAMPOLINE): Replace old + definition with undef, since we don't want the sysvr4 definition. + (SKIP_TRAMPOLINE_CODE): Likewise. + +2002-02-23 Andrew Cagney + + From 2002-02-22 Alfred M. Szmidt : + + * configure.in: (AC_CHECK_FUNCS) Added test for + canonicalize_file_name Regenerated. + * config.in, configure: Regenerated. + * utils.c: (gdb_realpath) If HAVE_CANONICALIZE_FILE_NAME is + defined use canonicalize_file_name. + +2002-02-23 Michael Chastain + + * MAINTAINERS: Remove Michael Chastain from "paper trail" list. + +2002-02-23 Andrew Cagney + + * README: Remove references to cygnus.com. + * MAINTAINERS: Change Past Maintainer addresses to ``foo at bar + dot com'' form. Remove references to cygnus.com and sourceware. + +2002-02-23 Andrew Cagney + + From 2002-02-19 Paul Eggert : + * Makefile.in (VER): Change "head -1" to "sed q", since POSIX + 1003.1-2001 no longer allows "head -1". + * gdb/Makefile.in (version.c): Likewise. + * gdb/doc/Makefile.in (GDBvn.texi): Likewise. + * gdb/CONTRIBUTE: Change "diff -c3" to "diff -c", which is + equivalent. POSIX 1003.1-2001 no longer allows "diff -c3". + +2002-02-23 Andrew Cagney + + * cli/cli-decode.c (cmd_cfunc_eq): New function. + * command.h (cmd_cfunc_eq): Declare. + * cli/cli-decode.h (cmd_cfunc_eq): Ditto. + + * cli/cli-cmds.h (is_complete_command): Change parameter to a + ``struct cmd_list_element *''. + * cli/cli-cmds.c (is_complete_command): Update. Use + cmd_cfunc_eq. + * top.c (execute_command): Pass the command to + is_complete_command. + * tracepoint.c: Replace function.cfunc with cmd_cfunc_eq. + +2002-02-23 Andrew Cagney + + From 2002-02-20 Martin Schwidefsky : + * config/s390/tm-s390.h (GDB_TARGET_IS_ESAME): Use renamed + architecture defines. + * s390-tdep.c (s390_gdbarch_init): Likewise. + +2002-02-23 Richard Earnshaw + + * arm-linux-tdep.c (arm_linux_extract_return_value): Make static. + (arm_linux_push_arguments): Likewise. + (arm_linux_init_abi): Register them. Also register linux-specific + call_dummy_words. + (find_minsym_and_objfile): Use strcmp, not STREQ. + * config/arm/tm-linux.h (CALL_DUMMY_WORDS): Delete. + (arm_linux_call_dummy_words): Delete declaration. + (EXTRACT_RETURN_VALUE, PUSH_ARGUMENTS): Delete. + (arm_linux_extract_return_value, arm_linux_push_arguments): Delete + declarations. + (LOWEST_PC): Delete. + +2002-02-23 Peter Schauer + + * maint.c (print_section_info): Do not prepend `0x' to filepos + output, it will be handled by local_hex_string_custom. + +2002-02-23 Richard Earnshaw + + * arm-linux-nat.c (store_newfpe_single): Use regcache_collect. + (store_newfpe_double, store_newfpe_extended, store_fpregister) + (store_register, store_regs, fill_gregset, fill_fpregset): Likewise. + +2002-02-22 Jim Blandy + + Indicate that the bcache functions don't change the strings + they're passed. + * bcache.h (bcache, hash): Add `const' keywords to declarations. + * bcache.c (bcache, hash): Add `const' keywords to definitions. + +2002-02-22 Pierre Muller + + * win32-nat.c (child_create_inferior): Fix create flags setting bug. + +2002-02-21 Christopher Faylor + + * win32-nat.c (register_loaded_dll): Just use raw name when we can't + find the complete path to a loaded DLL. + +2002-02-21 Fred Fish + + * dbxread.c (process_one_symbol): When finding an N_FUN symbol + that marks the end of the range of a function, enter a line number + entry that has a line number of zero and a PC offset that matches + the end of the function. This starts a range of PC's for which no + line number information is known. + * symtab.c (find_pc_sect_line): If our best fit is in a range of + PC's for which no line number info is found (line number is zero) + then we didn't find any valid line information. + * symtab.h: Document use of zero line number entry. + +2002-02-21 Elena Zannoni + + * ppc-linux-nat.c (PTRACE_GETVRREGS, PTRACE_SETVRREGS): Define. + (have_ptrace_getvrregs): Define for run time checks. + (gdb_vrregset_t): New type for Altivec register handling. + (fetch_register, store_register): Fetch/store altivec register + when needed. + (fetch_altivec_register, store_altivec_register): New functions. + (supply_vrregset, fill_vrregset): New functions. + (fetch_altivec_registers, store_altivec_registers): New functions. + (fetch_ppc_registers, store_ppc_registers): Fetch/store altivec + registers as well. + +2002-02-21 Jiri Smid + + * config/i386/x86-64linux.mh (NATDEPFILES): Remove x86-64-nat.o. + +2002-02-21 Richard Earnshaw + + * Makefile.in (armnbsd-nat.o): Update dependencies. + * armnbsd-nat.c (supply_gregset): New function. Common code to + supply the integer register set. + (supply_fparegset): New function. Similar for FPA registers. + (fetch_regs, fetch_fp_regs): Use them. + (fetch_core_registers): Likewise. + (fetch_elfcore_registers): New function. + (arm_netbsd_elfcore_fns): New core-file type specification. + (_initialize_arm_netbsd_nat): Register it. + +2002-02-21 Richard Earnshaw + + * armnbsd-nat.c: Include gdbcore.h. + (FETCH_INFERIOR_REGISTERS): Just error if this isn't defined. + (fetch_regs, fetch_fp_regs, store_regs, store_fp_regs): Add explicit + 'void' to declaration, to shut up ARI. + (fetch_core_registers): Make static. Rewrite using supply_register. + (arm_netbsd_core_fns): New core-file type specification. + (_initialize_arm_netbsd_nat): New function. + +2002-02-21 Christopher Faylor + + * win32-nat.c (register_loaded_dll): Correctly check for invalid handle + value. + +2002-02-20 Christopher Faylor + + * win32-nat.c (register_loaded_dll): Handle case where FindFirstFile + fails. + +2002-02-20 Daniel Jacobowitz + + * jv-exp.y (parse_number): Change type of implicit longs + to builtin_type_uint64. + +2002-02-20 Daniel Jacobowitz + + * gdbserver/linux-low.c (mywait): Change argument to waitpid + to be an integer instead of a `union wait'. + +2002-02-20 Daniel Jacobowitz + + * mips-linux-nat.c: Call the operating system GNU/Linux. + * mips-linux-tdep.c: Likewise. + * mips-tdep.c: Likewise. + +2002-02-20 Daniel Jacobowitz + + Fix PR gdb/265. + * jv-exp.y (parse_number): Handle 64-bit integers. + +2002-02-20 Daniel Jacobowitz + + * gdbserver/configure.in: Remove AM_PROC_CC_STDC. Change + AC_STDC_HEADERS to AC_HEADER_STDC. + * gdbserver/configure: Regenerated. + +2002-02-20 Richard Earnshaw + + * arc-tdep.c (get_longjmp_target): Only compile this function if JB_PC + is defined. + * sparc-tdep.c (get_longjmp_target): Likewise. + +2002-02-20 Richard Earnshaw + + * News: Add news about ARM and Multi-arch. Mention the new target + arm*-*-netbsd*. + +2002-02-19 Jim Blandy + + * stabsread.c (error_type_complaint): Improve error message. + +2002-02-19 Daniel Jacobowitz + + * gdbserver/README: Update documentation. + * gdbserver/configure.in: Update configury to match documentation. + * gdbserver/Makefile.in: Likewise. + * gdbserver/configure: Regenerated. + * gdbserver/aclocal.m4: New file, generated by aclocal. + * gdbserver/config.in: New file, generated by autoheader. + +2002-02-19 Richard Earnshaw + + * config/djgpp/fnchange.lst: Add change rules for armnbsd-tdep.c and + armnbsd-nat.c. + +2002-02-19 Richard Earnshaw + + * arm-tdep.h (enum arm_float_model): New enum. + (struct gdbarch_tdep): Add fp_model. + * arm-tdep.c (arm_gdbarch_init): Set fp_model in tdep. Defer setting + up floating-point conversions until we know the floating-point model + in use by the inferior. Don't complain about being unable to + determine the ABI of the inferior when we don't have one. + (arm_extract_return_value): Support different floating-point models. + (arm_store_return_value): Likewise. + * armnbsd-tdep.c (arm_netbsd_aout_init_abi): Set fp_model in tdep to + ARM_FLOAT_SOFT. + (arm_netbsd_elf_init_abi): Set fp_model to ARM_FLOAT_SOFT_VFP. + +2002-02-19 Peter Schauer + + * i386-tdep.c (i386_gdbarch_init): Eliminate incorrect use + of ``current_gdbarch''. + +2002-02-19 Richard Earnshaw + + * armnbsd-nat.c : ANSIfy all function declarations. + (fetch_register, fetch_regs, fetch_fp_register, fetch_fp_regs): New. + (fetch_inferior_registers): Re-implement in terms of above. + (store_register, store_regs, store_fp_register, store_fp_regs): New. + (store_inferior_registers): Re-implement in terms of above. + +2002-02-19 Richard Earnshaw + + * arm-linux-nat.c: Linux -> GNU/Linux when not talking about the + kernel. + * arm-linux-tdep.c: Likewise. + * config/arm/tm-linux.h: Likewise. + +2002-02-19 Richard Earnshaw + + * configure.tgt (arm*-*-netbsd*): This variant is now fully multi-arch. + * config/arm/nbsd.mt (TM_FILE): Delete. + * config/arm/tm-nbsd.h: Delete. + +2002-02-19 Richard Earnshaw + + * arm-tdep.c (arm_gdbarch_init): Initialize TARGET_CHAR_SIGNED. + Initialize CALL_DUMMY_LENGTH. + +2002-02-19 Richard Earnshaw + + * armnbsd-tdep.c (arm_netbsd_aout_in_solib_call_trampoline): New + function. + (arm_netbsd_aout_init_abi): Initialize IN_SOLIB_CALL_TRAMPOLINE. + * config/arm/tm-nbsd.h: Don't include config/tm-nbsd.h, it only + defines one thing and that is incorrect for this port. + (IN_SOLIB_CALL_TRAMPOLINE): Delete. + +2002-02-18 Pierre Muller + + * go32-nat.c: add i386-tdep.h include to import FP_REGNUM_P macro. + +2002-02-18 Pierre Muller + + * win32-nat.c (display_selector): New function. Displays information + about the information returned by GetThreadSelectorEntry API function. + (display_selectors): New function. Displays the infomation of + the selector given as argument, or of CS, DS ans FS selectors + if no argument is given. + ( _initialize_inftarg): Add "w32" as info prefix command. + Add "info w32 selector" as command calling display_selectors. + +2002-02-19 Pierre Muller + + * i386-tdep.c (get_longjmp_target): Fix compilation failure + by setting dummy values to JB_PC and JB_ELEMENT_SIZE + if not defined. + +2002-02-18 Richard Earnshaw + + * config/arm/nbsd.mt (TDEPFILES): Add solib-sunos.o. + +2002-02-18 Richard Earnshaw + + * arm-tdep.c (arm_set_call_dummy_breakpoint_offset): New function. + (arm_fix_call_dummy): Call it. + (arm_call_dummy_breakpoint_offset): Delete. + (arm_gdbarch_init): Initialize call_dummy_breakpoint_offset. + * config/arm/tm-arm.h (CALL_DUMMY_BREAKPOINT_OFFSET): Delete. + +2002-02-18 Andrew Cagney + + * gdbarch.sh (FRAME_CHAIN_VALID): Only require at level 2. + Default to func_frame_chain_valid. + * gdbarch.h, gdbarch.c: Re-generate. + * frame.h (FRAME_CHAIN_VALID): Delete definition. + +2002-02-18 Elena Zannoni + + * ppc-linux-nat.c: Update copyright. + (fetch_register, store_register): Add tid parameter, don't compute + tid here. + (fetch_ppc_registers, store_ppc_registers): Add tid + parameter. Pass it along to callees. + (fetch_inferior_registers, store_inferior_registers): Compute tid + here, and pass it to calleed functions. + (fill_gregset, supply_fpregset): Clean up formatting. + +2002-02-18 Richard Earnshaw + + * arm-tdep.c (arm_gdbarch_init): Initialize coerce_float_to_double. + * config/arm/tm-arm.h (COERCE_FLOAT_TO_DOUBLE): Delete. + +2002-02-18 Richard Earnshaw + + * gdbarch.sh (GET_LONGJMP_TARGET): Add rule. + * gdbarch.c gdbarch.h: Regenerate. + * breakpoint.c (create_longjmp_breakpoint): Always compile this + function. + (breakpoint_reset): Test GET_LONGJMP_TARGET_P(). + * infrun.c (GET_LONGJMP_TARGET): Delete default definition. + (handle_inferior_event): Test GET_LONGJMP_TARGET_P(). + + * arm-tdep.h (struct gdbarch_tdep): Add jb_pc and jb_elt_size fields. + * arm-tdep.c (arm_get_longjmp_target): New function. + (arm_gdbarch_init): Initialize jb_pc to -1. If ABI handler changes + this to a positive value register arm_get_longjmp_target as the + longjmp handler. + * arm-linux-tdep.c (arm_get_longjmp_target): Delete. + (arm_linux_init_abi): Set up longjmp description in tdep. + * armnbsd-nat.c (get_longjmp_target): Delete. + * armnbsd-tdep.c (arm_netbsd_init_abi_common): Set up longjmp + description in tdep. + * config/arm/tm-nbsd.h (JB_ELEMENT_SIZE, JB_PC): Delete. + (get_longjmp_target): Delete declaration. + (GET_LONGJMP_TARGET): Delete. + * config/arm/tm-linux.h (arm_get_longjmp_target): Delete declaration. + (GET_LONGJMP_TARGET): Delete. + +2002-02-17 Kevin Buettner + + From Peter Schauer : + * ia64-tdep.c (ia64_gdbarch_init): Eliminate incorrect use + of ``current_gdbarch''. + +2002-02-17 Tom Tromey + + * cli/cli-cmds.c (compare_strings): New function. + (complete_command): Only print each unique item once. + * completer.h (complete_line): Declare. + * completer.c (complete_line): New function. + (line_completion_function): Use it. + +2002-02-16 Andrew Cagney + + * gdbarch.sh (TARGET_LONG_DOUBLE_BIT): Default to 64. + * gdbarch.h, gdbarch.c: Re-generate. + +2002-02-16 Daniel Jacobowitz + + * valarith.c (value_x_unop): Fix decrement; support post-decrement. + +2002-02-16 Daniel Jacobowitz + + From Peter Schauer : + * valops.c (value_arg_coerce): Don't take the address of a reference + to convert an argument to a reference. + +2002-02-15 Christopher Faylor + + * win32-nat.c (get_image_name): New function. + (handle_load_dll): Use get_image_name function. + (get_child_debug_event): Avoid registering debug events until possibly + execed process is started. + (child_create_inferior): Allow invocation via shell so that command + line redirection, etc. works ok. + (_initialize_inftarg): Add new command: "set shell" to control whether + a shell is used to start a process. + +2002-02-15 Daniel Jacobowitz + + * gdbserver/linux-mips-low.c (cannot_fetch_register): Use find_regno + instead of find_register_by_number. + (cannot_store_register): Likewise. + +2002-02-14 Pierre Muller + + * dwarf2read.c: Replace fprintf (stderr, ...) by + fprintf_unfiltered (gdb_stderr, ...). + +2002-02-15 Daniel Jacobowitz + + * gdbserver/gdbserver.1: Document --attach. + +2002-02-15 Richard Earnshaw + + * arm-tdep.h (struct gdbarch_tdep): Add fields for breakpoint + descriptions. + * arm-tdep.c (arm_default_arm_le_breakpoint) + (arm_default_arm_be_breakpoint, arm_default_thumb_le_breakpoint) + (arm_default_thumb_be_breakpoint): New. Initialize them from + traditional breakpoint defines. + (arm_breakpoint_from_pc): Use new gdbarch_tdep entries. + (arm_gdbarch_init): Initialize new breakpoint variables. + * arm-linux-tdep.c (arm_linux_arm_le_breakpoint): New. + (arm_linux_init_abi): Initialize linux-specific breakpoint. + * armnbsd-tdep.c (arm_nbsd_arm_le_breakpoint): New. + (arm_netbsd_aout_init_abi, arm_netbsd_elf_init_abi): Split common + code out to ... + (arm_netbsd_init_abi_common): ... here; new function. + * config/arm/tm-arm.h (ARM_LE_BREAKPOINT, ARM_BE_BREAKPOINT) + (THUMB_LE_BREAKPOINT, THUMB_BE_BREAKPOINT): Delete. + * config/arm/tm-linux.h (ARM_LE_BREAKPOINT): Delete. + * config/arm/tm-nbsd.h (ARM_LE_BREAKPOINT): Delete. + +2002-02-15 Richard Earnshaw + + * arm-tdep.h (enum arm_abi): New enum. + (struct gdbarch_tdep): New structure. + (LOWEST_PC): Provide a default. + (arm_gdbarch_register_os_abi): Declare new function. + * arm-tdep.c (arm_abi_names): New array. + (process_note_abi_tag_sections): New function. + (get_elfosabi): New function. + (arm_gdbarch_register_os_abi): New function. + (arm_gdbarch_init): Try to determine the ABI of the inferior. If + support for that ABI has been built in, then call the appropriate + configuration routine. Use gdbarch_num_regs() to get the number + of registers. + (arm_dump_tdep): New function. + (arm_init_abi_eabi_v1, arm_init_abi_eabi_v2, arm_init_abi_apcs): New + place-holder functions. + (_initialize_arm_tdep): Register them. + * config/arm/tm-arm.h (LOWEST_PC): Delete. + + * armnbsd-tdep.c: New file. + * Makefile.in (armnbsd-tdep.o): Add dependencies. + * config/arm/nbsd.mt (TDEPFILES): Add it. + * config/arm/tm-nbsd.h (LOWEST_PC): Delete. + + * armnbsd-nat.c: Include regcache.h. + * Makefile.in (armnbsd-nat.o): Update dependency list. + + * arm-tdep.c (arm_get_next_pc): Use printf_filtered for error message. + +2002-02-14 Daniel Jacobowitz + + * gdbserver/Makefile.in: Fix typos in target rules. + +2002-02-14 Daniel Jacobowitz + + Fix part of PR gdb/267. + * linespec.c (find_methods): Handle constructors specially for now. + +2002-02-14 Corinna Vinschen + + * arm-tdep.c (arm_push_arguments): Eliminate special float type + handling. + * config/arm/tm-arm.h (COERCE_FLOAT_TO_DOUBLE): Define to call + standard_coerce_float_to_double(). + +2002-02-14 Christopher Faylor + + * config/i386/xm-cygwin.h: Revert inadvertent reinclusion of + GDBINIT_FILENAME. + +2002-02-14 Elena Zannoni + + * rs6000-tdep.c (rs6000_gdbarch_init): Don't call + find_variant_by_name, because it confuses the multiarch + framework. Return NULL if there isn't an architecture with the + user supplied name, instead of forcing a different one without + recording the change with the multiarch machinery. + (find_variant_by_name): Delete. + +2002-02-14 Peter Schauer + + * config/i386/i386sol2.mh (NATDEPFILES): Add i387-nat.o, needed by + i386v4-nat.o now. Add gcore.o, Solaris x86 supports gcore. + +2002-02-13 Martin M. Hunt + + * stack.c (print_frame_info_base): When calling + print_frame_info_listing_hook, set current_source_symtab. + +2002-02-14 Daniel Jacobowitz + + * gdbserver/Makefile.in: Add regformats directory to INCLUDE_CFLAGS, + and remove unused $(INCLUDE_DIR). + Add regcache.c to OBS. + Add generated register protocol files to clean target. + Update dependencies for new objects, obsolete old target code. + + * gdbserver/linux-low.c: Remove all platform-specific code to + new files. Remove various dead code. Update to use regcache + functionality. + * gdbserver/remote-utils.c (fromhex): Add return statement + to quiet warning. + (putpkt): Dynamically allocate buf2 because PBUFSIZ is no longer + constant. + (input_interrupt): Add integer parameter to match prototype + of a signal handler. + (outreg): Use register_data (). + (prepare_resume_reply): Use gdbserver_expedite_regs. + * gdbserver/server.c (main): Dynamically allocate own_buf because + PBUFSIZ is no longer constant. Use registers_to_string () and + registers_from_string (). + * gdbserver/server.h: No longer include "defs.h". Add prototypes + for error (), fatal (), and warning (). Update definition of + PBUFSIZ to use regcache functionality. Add include guard. + * gdbserver/utils.c (fatal): Add missing ``const''. + (warning): New function. + + * regformats/regdat.sh: Include "regcache.h" in generated files. + Provide init_registers () function. + * regformats/regdef.h: Add prototype for set_register_cache (). + Add include guard. + + * gdbserver/linux-arm-low.c: New file. + * gdbserver/linux-i386-low.c: New file. + * gdbserver/linux-ia64-low.c: New file. + * gdbserver/linux-m68k-low.c: New file. + * gdbserver/linux-mips-low.c: New file. + * gdbserver/linux-ppc-low.c: New file. + * gdbserver/linux-sh-low.c: New file. + + * gdbserver/regcache.c: New file. + * gdbserver/regcache.h: New file. + + * gdbserver/low-linux.c: Removed obsolete file. + +2002-02-14 Daniel Jacobowitz + + * config/arm/linux.mt: Update GDBSERVER_DEPFILES. + * config/i386/linux.mt: Likewise. + * config/ia64/linux.mt: Likewise. + * config/m68k/linux.mh: Likewise. + * config/powerpc/linux.mh: Likewise. + * config/mips/linux.mt: Likewise. + + * config/sh/linux.mt: Add GDBSERVER_DEPFILES. + + * config/i386/i386lynx.mh: Mark gdbserver variables + as (currently) obsolete for this target. + * config/i386/nbsd.mt: Likewise. + * config/i386/nbsdelf.mt: Likewise. + * config/m32r/m32r.mt: Likewise. + * config/m68k/m68klynx.mh: Likewise. + * config/m68k/nbsd.mt: Likewise. + * config/m68k/sun3os4.mh: Likewise. + * config/mips/vr5000.mt: Likewise. + * config/ns32k/nbsd.mt: Likewise. + * config/pa/hppabsd.mh: Likewise. + * config/pa/hppaosf.mh: Likewise. + * config/powerpc/nbsd.mt: Likewise. + * config/rs6000/rs6000lynx.mh: Likewise. + * config/s390/s390.mt: Likewise. + * config/s390/s390x.mt: Likewise. + * config/sparc/sparclynx.mh: Likewise. + * config/sparc/sun4os4.mh: Likewise. + * config/i386/x86-64linux.mt: Likewise. + * config/sparc/linux.mh: Likewise. + +2002-02-14 Daniel Jacobowitz + + * configure.tgt: Configure gdbserver only for known working + targets. Set ${build_gdbserver} instead of modifying ${configdirs}. + * configure.in: Check ${build_gdbserver}. Put gdbserver/ into + SUBDIRS if it is configured. Update comment for ${nativefile}. + * configure: Regenerated. + +2002-02-13 Michael Snyder + + * config/i386/i386v42mp.mh: Add gcore.o to NATDEPFILES. + + * gcore.c (gcore_command): Use gcore_default_target instead of NULL. + (default_gcore_mach): Just return 0, work around a problem in bfd. + (default_gcore_target): OK to return NULL if exec_bfd is null. + (make_mem_sec): Use a cast, avoid a warning. + + * procfs.c (find_memory_regions_callback): Use a cast instead of + calling host_pointer_to_address (which complains if + sizeof (host pointer) != sizeof (target pointer)). + (procfs_make_note_section): Avoid overflow in psargs string. + + * procfs.c (procfs_make_note_section): Make the default + implementation return an error. + +2002-02-13 Rodney Brown + + * procfs.c (procfs_make_note_section): Provide a default definition + (for alpha-dec-osf4.0f). Fix typos. + +2002-02-13 Elena Zannoni + + * linux-proc.c: Add include of regcache.h. + * Makefile.in (linux-proc.o): Add dependency on regcache.h. + +2002-02-13 Andrew Cagney + + From 2002-01-18 Greg McGary : + * memattr.c (create_mem_region): Disallow useless empty region. + Regions are half-open intervals, so allow [A..B) [B..C) as + non-overlapping. + +2002-02-13 Michael Chastain + + * defs.h: Kill CONST_PTR. + * c-lang.h (c_builtin_types): Change CONST_PTR to simple "const". + * c-lang.c (c_builtin_types): Likewise. + * ch-lang.c (ch_builtin_types): Likewise. + * f-lang.c (f_builtin_types): Likewise. + * language.c (unknown_builtin_types): Likewise. + * m2-lang.c (m2_builtin_types): Likewise. + * p-lang.c (pascal_builtin_types): Likewise. + * scm-lang.c (c_builtin_types): Likewise. + +2002-02-13 Keith Seitz + + * arm-tdep.h (arm_get_next_pc): Add declaration. + +2002-02-13 Richard Earnshaw + + * arm-tdep.c (arm_use_struct_convention): Make static. Move to be + with other related struct-returning functions. + (arm_extract_struct_value_address): New function. + (arm_gdbarch_init): Initialize the above in multi-arch vector. Also + initialize float_format, double_format and long_double_format as + appropriate to the endianness of the target. + * config/arm/tm-arm.h (TARGET_DOUBLE_FORMAT): Delete. + (arm_use_struct_convention): Delete declaration. + (USE_STRUCT_CONVENTION, EXTRACT_STRUCT_VALUE_ADDRESS): Delete. + +2002-02-13 Keith Seitz + + * defs.h (core_addr_to_string_nz): New function. + +2002-02-13 Mark Kettenis + + Apply missing bits of 2002-01-15 patch. + * i386v4-nat.c (supply_fpregset): Use i387_supply_fsave. + (fill_fpregset): Use i387_fill_fsave. + +2002-02-12 Keith Seitz + + * utils.c (core_addr_to_string): Use phex instead of phex_nz. + (core_addr_to_string_nz): New function. + +2002-02-11 Richard Earnshaw + + * arm-linux-nat.c: Really include arm-tdep.h. + * config/arm/tm-linux.h (struct type, struct value): Declare. + +2002-02-11 Michael Snyder + + * procfs.c: Include elf-bfd.h (for elfcore_write functions). + (gcore section): Ifdef for Solaris and Unixware only. + (procfs_do_thread_registers): Unixware needs one lwpstatus + per thread (not one prstatus or pstatus). + (procfs_make_note_section): Iterate only over kernel threads (lwps), + not over all gdb threads. For unixware, call elfcore_write_pstatus + once before iterating over threads. + +2002-02-11 Richard Earnshaw + + * arm-tdep.h: New file. + * arm-tdep.c: Include arm-tdep.h. + (arm_addr_bits_remove, arm_smash_text_address, arm_saved_pc_after_call) + (arm_skip_prologue, arm_call_dummy_words, arm_fix_call_dummy) + (arm_print_float_info, arm_register_type, convert_to_extended) + (arm_elf_make_msymbols_special, arm_coff_make_msymbol_special) + (arm_extract_return_value, arm_register_name): Make static. + (arm_software_single_step): Similarly. Fix types in declaration. + (arm_register_byte, arm_register_raw_size, arm_register_virtual_size) + (arm_store_return_value, arm_store_struct_return): New functions. + (arm_gdbarch_init): Register the above functions. Also register + call_dummy_start_offset, sizeof_call_dummy_words, + function_start_offset, inner_than, decr_pc_after_break, fp_regnum, + sp_regnum, pc_regnum, register_bytes, num_regs, max_register_raw_size, + max_register_virtual_size, register_size. Set up + prologue_cache.saved_regs here, rather than ... + (_initialize_arm_tdep): ... here. + * config/arm/tm-arm.h (struct type, struct value): Delete forward + declarations. + (arm_addr_bits_remove, arm_smash_text_address, arm_saved_pc_after_call) + (arm_skip_prologue, arm_call_dummy_words, arm_fix_call_dummy) + (arm_print_float_info, arm_register_type, convert_to_extended) + (arm_elf_make_msymbols_special, arm_coff_make_msymbol_special) + (arm_extract_return_value, arm_register_name): Delete declarations. + (SMASH_TEXT_ADDRESS, ADDR_BITS_REMOVE, FUNCTION_START_OFFSET) + (SKIP_PROLOGUE, SAVED_PC_AFTER_CALL, INNER_THAN, BREAKPOINT_FROM_PC) + (DECR_PC_AFTER_BREAK, PRINT_FLOAT_INFO, REGISTER_SIZE, NUM_REGS) + (REGISTER_NAME, REGISTER_BYTES, REGISTER_BYTE, REGISTER_RAW_SIZE) + (REGISTER_VIRTUAL_SIZE, MAX_REGISTER_RAW_SIZE) + (MAX_REGISTER_VIRTUAL_SIZE, REGISTER_VIRTUAL_TYPE, STORE_STRUCT_RETURN) + (EXTRACT_RETURN_VALUE, STORE_RETURN_VALUE, CALL_DUMMY_WORDS) + (SIZEOF_CALL_DUMMY_WORDS, CALL_DUMMY_START_OFFSET, FIX_CALL_DUMMY) + (SOFTWARE_SINGLE_STEP_P, SOFTWARE_SINGLE_STEP) + (ELF_MAKE_MSYMBOL_SPECIAL, COFF_MAKE_MSYMBOL_SPECIAL) Delete. + (arm_pc_is_thumb, arm_pc_is_thumb_dummy, thumb_get_next_pc) + (arm_get_next_pc): No-longer static -- these are needed by the RDI + interface. + * arm-linux-nat.c arm-linux-tdep.c armnbsd-nat.c: Include arm-tdep.h. + * remote-rdi.c remote-rdp.c: Likewise. + * Makefile.in (arm-linux-nat.o, arm-linux-tdep.o arm-tdep.o) + (armnbsd-nat.o, remote-rdi.o, remote_rdp.o): Update dependencies. + * config/arm/tm-nbsd.h (SOFTWARE_SINGLE_STEP_P): Delete bogus + definition. + + * arm-tdep.h (ARM_A1_REGNUM, ARM_A4_REGNUM, ARM_AP_REGNUM) + (ARM_SP_REGNUM, ARM_LR_REGNUM, ARM_PC_REGNUM, ARM_F0_REGNUM) + (ARM_F3_REGNUM, ARM_F7_REGNUM, ARM_FPS_REGNUM, ARM_PS_REGNUM): Renamed + from non-ARM_ prefixed definitions. + * arm-tdep.c armnbsd-nat.c arm-linux-nat.c arm-linux-tdep.c: Update + all uses of above. + * remote-rdi.c remote-rdp.c: Likewise. + * arm-linux-nat.c (ARM_CPSR_REGNUM): Renamed from CPSR_REGNUM. + +2002-02-11 Richard Earnshaw + + * arm-tdep.c (arm_frameless_function_invocation) + (arm_frame_args_address, arm_frame_locals_address, arm_frame_num_args) + (arm_frame_chain, arm_init_extra_frame_info, arm_frame_saved_pc) + (arm_read_fp, arm_frame_init_saved_regs, arm_push_dummy_frame) + (arm_pop_frame, arm_get_next_pc): Make static. + (arm_gdbarch_init): Register above in gdbarch structure. + (arm_read_fp): Renamed from arm_target_read_fp. + (arm_pc_is_thumb, arm_pc_is_thumb_dummy): Make static. + * config/arm/tm-arm.h (arm_frameless_function_invocation) + (arm_frame_args_address, arm_frame_locals_address, arm_frame_num_args) + (arm_frame_chain, arm_init_extra_frame_info, arm_frame_saved_pc) + (arm_target_read_fp, arm_frame_init_saved_regs, arm_push_dummy_frame) + (arm_pop_frame, arm_get_next_pc, arm_pc_is_thumb) + (arm_pc_is_thumb_dummy): Delete declarations. + (INIT_EXTRA_FRAME_INFO, TARGET_READ_FP, FRAME_CHAIN) + (FRAMELESS_FUNCTION_INVOCATION, FRAME_SAVED_PC, FRAME_ARGS_ADDRESS) + (FRAME_LOCALS_ADDRESS, FRAME_NUM_ARGS, FRAME_ARGS_SKIP) + (FRAME_INIT_SAVED_REGS, PUSH_DUMMY_FRAME, POP_FRAME): Delete. + +2002-02-10 Daniel Jacobowitz + + * symtab.c (compare_search_syms): New function. + (sort_search_symbols): New function. + (search_symbols): Sort symbols after searching rather than + before. + +2002-02-10 Andrew Cagney + + * NEWS: Linux -> GNU/Linux. + +2002-02-10 Andrew Cagney + + * gdbarch.sh: For for level one methods, disallow a definition + when partially multi-arched. Add comments explaining rationale. + * gdbarch.h: Re-generate. + +2002-02-10 Andrew Cagney + + * gdbarch.sh (EXTRA_STACK_ALIGNMENT_NEEDED): Don't require when + multi-arch partial. + +2002-02-10 Andrew Cagney + + * gdbarch.sh: Map LEVEL onto a symbolic GT_LEVEL. Exit on bad + field. Use diff -u. + * gdbarch.c: Re-generate. + +2002-02-10 Andrew Cagney + + * config/mips/tm-mips.h (CALL_DUMMY_LOCATION): Delete. + * gdbarch.sh (PUSH_RETURN_ADDRESS): Don't require when multi-arch + partial. + +2002-02-10 Andrew Cagney + + * gdbarch.sh (REGISTER_CONVERTIBLE): Don't require when + multi-arch partial. + (PUSH_ARGUMENTS): Switch to using predefault. + * gdbarch.c: Regenerate. + +2002-02-10 Andrew Cagney + + * valops.c (PUSH_ARGUMENTS): Delete definition. + * gdbarch.sh (PUSH_ARGUMENTS): Don't require when multi-arch + partial. Default to default_push_arguments. + * gdbarch.h, gdbarch.c: Regenerate. + +2002-02-09 Andrew Cagney + + * defs.h (throw_exception): Rename return_to_top_level. Update + comments. + * utils.c (error_stream, internal_verror, quit): Ditto. + * top.c (throw_exception, catcher): Ditto. + * sparclet-rom.c (sparclet_load): Ditto. + * remote.c (interrupt_query, minitelnet): Ditto. + * remote-sds.c (interrupt_query): Ditto. + * remote-mips.c (mips_error, mips_kill): Ditto. + * ocd.c (interrupt_query): Ditto. + * monitor.c (monitor_interrupt_query): Ditto. + * m3-nat.c (suspend_all_threads, thread_resume_command): Ditto. + * target.h: Update comment. + + * m3-nat.c, ocd.c, sparclet-rom.c: Update copyright. + +2002-02-09 Andrew Cagney + + * gdbarch.sh (TARGET_LONG_DOUBLE_FORMAT): Default to + default_double_format. + * gdbarch.h, gdbarch.c: Re-generate. + * findvar.c (floatformat_unknown): Delete variable definition. + * doublest.h (floatformat_unknown): Delete variable declaration. + +2002-02-09 Jim Blandy + + * stabsread.c (read_type): Add code to parse Sun's syntax for + prototyped function types. + +2002-02-09 Andrew Cagney + + * Makefile.in (SUBDIR_CLI_INITS): Set to SUBDIR_CLI_SRCS. + (SUBDIR_MI_INITS): Set to SUBDIR_MI_SRCS. + +2002-02-09 Peter Schauer + + * xcoffsolib.c (_initialize_xcoffsolib): Renamed from + _initialize_solib. Fixes name clash with solib.c:_initialize_solib, + now _initialize_xcoffsolib gets called again and overrides the + commands from solib.c in a native configuration. + +2002-02-09 Mark Kettenis + + * doublest.c (store_typed_floating): Don't try to return a value. + Fixes PR gdb/290. + +2002-02-08 Jim Blandy + + * c-typeprint.c (c_type_print_varspec_suffix): If a function type + is prototyped and has no arguments, print its argument list as + `(void)'. + +2002-02-08 Chris Demetriou + + * MAINTAINERS (write-after-approval): Add myself. + (paper-trail): I've escaped! + +2002-02-08 Christopher Faylor + + * win32-nat.c (cygwin_pid_to_str): Revert 2002-02-08 change xasprintf + changes. + (_initialize_check_for_gdb_ini): Ditto. + +2002-02-08 Martin M. Hunt + + * win32-nat.c (cygwin_pid_to_str): Fix typo. + xaprintf -> xasprintf. + +2002-02-08 Pierre Muller + + * win32-nat.c: Remove use of printf and sprintf functions. + +2002-02-08 Richard Earnshaw + + * arm-tdep.c (arm_frame_chain_valid): Make static. + (arm_push_arguments): Likewise. + (arm_gdbarch_init): New function. + (_initialize_arm_tdep): Call it. + * config/arm/tm-arm.h (GDB_MULTI_ARCH): Set to 1. + (TARGET_DOUBLE_FORMAT): Test TARGET_BYTE_ORDER, not target_byte_order. + (FRAME_CHAIN_VALID): Delete. + (arm_frame_chain_valid): Delete declaration. + (PUSH_ARGUMENTS): Delete. + (arm_push_arguments): Delete declaration. + (CALL_DUMMY_P): Delete. + +2002-02-08 Andrew Cagney + Corinna Vinschen + + * gdbtypes.c (build_gdbtypes): Disable setting a specific float format + on builtin float types. + +2002-02-08 Daniel Jacobowitz + + * utils.c: Include before "bfd.h". + * tui/tui-hooks.c: Likewise. + * tui/tui.c: Likewise. + * tui/tuiCommand.c: Likewise. + * tui/tuiData.c: Likewise. + * tui/tuiDataWin.c: Likewise. + * tui/tuiDisassem.c: Likewise. + * tui/tuiGeneralWin.c: Likewise. + * tui/tuiIO.c: Likewise. + * tui/tuiLayout.c: Likewise. + * tui/tuiRegs.c: Likewise. + * tui/tuiSource.c: Likewise. + * tui/tuiSourceWin.c: Likewise. + * tui/tuiStack.c: Likewise. + * tui/tuiWin.c: Likewise. + +2002-02-07 Elena Zannoni + + * sh-tdep.c (sh_nofp_frame_init_saved_regs): Extend where[] array + to include space for pseudoregs as well. Update loops accordingly. + (sh_fp_frame_init_saved_regs): Ditto. + (sh_init_extra_frame_info, sh_pop_frame): Split long lines. + +2002-02-07 Andrew Cagney + + * MAINTAINERS: Andreas Schwab is GNU/Linux m68k maintainer. + Add Richard Earnshaw to Arm maintainers. + +2002-02-07 Andrew Cagney + + * defs.h (warning_begin): Delete declaration. + + * config/powerpc/tm-ppcle-eabi.h (TARGET_BYTE_ORDER_DEFAULT): + Delete macro. + +2002-02-07 Michael Snyder + + * solib-legacy.c (legacy_svr4_fetch_link_map_offsets): + Logic bug, remove misplaced else. + +2002-02-07 Klee Dienes + + * fork-inferior.c (fork_inferior): Add '!' to the list of + characters that need to be quoted when building a string for the + shell. Quote '!' specifically with a backslash, since CSH chokes + when trying to evaluate "str!str". + +2002-02-06 Nick Clifton + + * rdi-share/host.h: Only provide a typedef for bool if it is not + defined. + +2002-02-04 Michael Snyder + + * breakpoint.h (enum bptype): Add new overlay event bp type. + (enable_overlay_breakpoints, disable_overlay_breakpoints): Export. + + * breakpoint.c (create_internal_breakpoint): New function. + (internal_breakpoint_number): Moved into create_internal_breakpoint. + (create_longjmp_breakpoint): Use create_internal_breakpoint. + (create_thread_event_breakpoint): Ditto. + (create_solib_event_breakpoint): Ditto. + (create_overlay_event_breakpoint): New function. + (enable_overlay_breakpoints, disable_overlay_breakpoints): New funcs. + (update_breakpoints_after_exec): Delete and re-initialize + overlay event breakpoints after an exec. Add FIXME comment + about longjmp breakpoint. + (print_it_typical): Ignore overlay event breakpoints. + (print_one_breakpoint): Ditto. + (mention): Ditto. + (bpstat_what): Do not stop for overlay event breakpoints. + (delete_breakpoint): Don't delete overlay event breakpoints. + (breakpoint_re_set_one): Delete the overlay event breakpoint. + (breakpoint_re_set): Re-create overlay event breakpoint. + + * symfile.c (overlay_auto_command): Enable overlay breakpoints. + (overlay_manual_command): Disable overlay breakpoints. + (overlay_off_command): Disable overlay breakpoints. + +2002-02-06 Richard Earnshaw + + * arm-tdep.c: Include elf-bfd.h and coff/internal.h. + (MSYMBOL_SET_SPECIAL, MSYMBOL_IS_SPECIAL, MSYMBOL_SIZE): Move defines + to here from config/tm-arm.h. + (coff_sym_is_thumb): Make static. + (arm_elf_make_msymbol_special): New function. + (arm_coff_make_msymbol_special): New function. + * config/arm/tm-arm.h (MSYMBOL_SET_SPECIAL): Delete definition. + (MSYMBOL_IS_SPECIAL, MSYMBOL_SIZE): Likewise. + (coff_sym_is_thumb): Delete declaration. + (arm_elf_make_msymbol_special): Declare. + (arm_coff_make_msymbol_special): Declare. + (ELF_MAKE_MSYMBOL_SPECIAL): Call arm_elf_make_msymbol_special. + (COFF_MAKE_MSYMBOL_SPECIAL): Call arm_coff_make_msymbol_special. + +2002-02-06 Richard Earnshaw + + * arm-tdep.c (arm_software_single_step): ANSIfy function declaration. + +2002-02-06 Richard Earnshaw + + * gdbarch.sh (PRINT_FLOAT_INFO): Add rule. + * gdbarch.c gdbarch.h: Regenerate. + * arch-utils.c (default_print_float_info): New function. + * arch-utils.h (default_print_float_info): Prototype it. + * infcmd.c (float_info): Call PRINT_FLOAT_INFO. + * doc/gdbint.texinfo (FLOAT_INFO): Mark as deprecated. + (PRINT_FLOAT_INFO): Document it. + + * arm-tdep.c (arm_print_float_info): Renamed from arm_float_info. + * config/arm/tm-arm.h (FLOAT_INFO): Delete. + (PRINT_FLOAT_INFO): Define. + +2002-02-06 Pierre Muller + + * win32-nat.c (_initialize_check_for_gdb_ini): + Add typecast to sprintf argument to suppress a warning. + +2002-02-05 Pierre Muller + + * win32-nat.c (last_sig): Changed type of variable to target_signal, + to allow easier handling of pass state. + (DEBUG_EXCEPTION_SIMPLE): New macro, used in handle_exception, + that gives exception name and address. + (handle_exception): Use DEBUG_EXCEPTION_SIMPLE macro + and set last_sig value to ourstatus->value.sig. Some missing + exceptions added. + (child_continue): Correctly report continue_status. + (get_child_debug_event,do_initial_child_stuff): Set last_sig to + TARGET_SIGNAL_0 (new default value). + (child_resume): consider sig argument passed to decide if + the exception should be passed to debuggee or not. + +2002-02-05 Michael Snyder + + * regcache.c (fetch_register): Call target_fetch_register + only if we don't call FETCH_PSEUDO_REGISTER. + (store_register): Call target_store_register only if we + don't call STORE_PSEUDO_REGISTER. + +2002-02-05 Elena Zannoni + + * gdbarch.sh: Add definitions for COFF_MAKEMSYMBOL_SPECIAL and + ELF_MAKE_MSYMBOL_SPECIAL. + * gdbarch.c, gdbarch.h: Regenerate. + * arch-utils.c (default_make_msymbol_special): New function. + * arch-utils.h (default_make_msymbol_special): Export. + * elfread.c (elf_symtab_read): Compile use of + ELF_MAKE_MSYMBOL_SPECIAL unconditionally because it is now + multiarched. + * coffread.c (coff_symtab_read): Ditto, for + COFF_MAKE_MSYMBOL_SPECIAL. + +2002-02-05 Jim Blandy + + * solib-svr4.c (svr4_truncate_ptr): New function. + (svr4_relocate_section_addresses): Do the address arithmetic with + the appropriate truncation for target addresses, even when + CORE_ADDR is larger than a target address. + +2002-02-05 Daniel Jacobowitz + + * gdbserver/linux-low.c (mywait): Cast second argument of waitpid + to (int *). + +2002-02-05 Daniel Jacobowitz + + * gdbserver/linux-low.c (kill_inferior): Remove commented out + code. + +2002-02-05 Daniel Jacobowitz + + * c-valprint.c (c_val_print): Handle TYPE_CODE_COMPLEX. + +2002-02-05 Daniel Jacobowitz + + * gdbserver/linux-low.c: Remove unused include files. + +2002-02-05 Daniel Jacobowitz + + * gdbserver/linux-low.c: Define PTRACE_ARG3_TYPE. + (read_inferior_memory): Use it. + (write_inferior_memory): Likewise. + +2002-02-05 Daniel Jacobowitz + + * gdbserver/linux-low.c (create_inferior): Call strerror instead of + grubbing through sys_errlist. + +2002-02-05 Daniel Jacobowitz + + * gdbserver/linux-low.c: New file, copied exactly from low-linux.c. + +2002-02-04 Pierre Muller + * win32-nat.c (handle_exception): Handle Ctrl-Break exception. + +2002-02-04 Andrew Cagney + + * cli/cli-decode.c (do_cfunc, set_cmd_cfunc): New functions. + (do_sfunc, set_cmd_sfunc): New functions. + + * command.h (struct cmd_list_element): Add field func. + * cli/cli-decode.h (struct cmd_list_element): Ditto. + * command.h (set_cmd_sfunc, set_cmd_cfunc): Declare. + * cli/cli-decode.h: Ditto. + + * cli/cli-decode.c (help_cmd): Test for func not cfunc/sfunc. + (help_all, help_cmd_list): Ditto. + (find_cmd, complete_on_cmdlist): Ditto. + * top.c (execute_command): Ditto. + + * cli/cli-setshow.c (do_setshow_command): Call func instead of + function.sfunc. + + * infcmd.c (notice_args_read): Fix function signature. + + * cli/cli-cmds.c (init_cli_cmds): Use set_cmd_sfunc. + * cli/cli-decode.c (add_set_cmd): Ditto. + * utils.c (initialize_utils): Ditto. + * maint.c (_initialize_maint_cmds): Ditto. + * infrun.c (_initialize_infrun): Ditto. + * demangle.c (_initialize_demangler): Ditto. + * remote.c (add_packet_config_cmd): Ditto. + * mips-tdep.c (_initialize_mips_tdep): Ditto. + * cris-tdep.c (_initialize_cris_tdep): Ditto. + * proc-api.c (_initialize_proc_api): Ditto. + * kod.c (_initialize_kod): Ditto. + * valprint.c (_initialize_valprint): Ditto. + * top.c (init_main): Ditto. + * infcmd.c (_initialize_infcmd): Ditto. + * corefile.c (_initialize_core): Ditto. + * arm-tdep.c (_initialize_arm_tdep): Ditto. + * arch-utils.c (initialize_current_architecture): Ditto. + (_initialize_gdbarch_utils): Ditto. + * alpha-tdep.c (_initialize_alpha_tdep): Ditto. + + * cli/cli-decode.c (add_cmd): Use set_cmd_cfunc. + * wince.c (_initialize_inftarg): Ditto. + * symfile.c (_initialize_symfile): Ditto. + * mips-tdep.c (_initialize_mips_tdep): Ditto. + * language.c (_initialize_language): Ditto. + * arc-tdep.c (_initialize_arc_tdep): Ditto. + +2002-02-04 Michael Snyder + + * memattr.c (_initialize_mem): Elaborate the help for 'mem' command. + +2002-02-04 Daniel Jacobowitz + + * gdbserver/Makefile.in: Add regformats directory to INCLUDE_CFLAGS. + Add rules for building the register data files. + +2002-02-04 Daniel Jacobowitz + + * regformats/regdat.sh: Add braces to the definition of + expedite_regs_${arch}. + +2002-02-04 Daniel Jacobowitz + + * regformats/regdef.h (struct reg): Add comment describing the + requirements for offset and size fields. + +2002-02-04 Andreas Schwab + + * config/ia64/linux.mh: Don't set NAT_CLIBS and REGEX. + * config/ia64/linux.mt: Don't set GDBSERVER_LIBS. + +2002-02-04 Richard Earnshaw + + * gdbarch.sh (copyright): Update years in generated header. + (SMASH_TEXT_ADDRESS): Add rule. + * gdbarch.h, gdbarch.c: Re-generate. + * coffread.c: Multi-arch uses of SMASH_TEXT_ADDRESS. + * dbxread.c: Likewise. + * dwarfread.c: Likewise. + * elfread.c: Likewise. + * somread.c: Likewise. + + * arm-tdep.c (arm_smash_text_address): New function. + * config/arm/tm-arm.h (SMASH_TEXT_ADDRESS): Define in terms of above. + +2002-02-04 Pierre Muller + + Add support for hardware watchpoints on win32 native. + * win32-nat.c (CONTEXT_DEBUG_DR macro): Add use of + CONTEXT_DEBUG_REGISTERS. + (dr variable): New variable. Static array containing a local copy + of debug registers. + (debug_registers_changed): New variable. Reflects when debug registers + are changed and need to be written to inferior. + (debug_registers_used): New variable. Reflects when any debug register + was set, used when new threads are created. + (cygwin_set_dr, cygwin_set_dr7, cygwin_get_dr6): New functions used by + i386-nat code. + (thread_rec): Set dr array if id is the thread of current_event . + (child_continue, child_resume): Change the debug registers for all + threads if debug_registers_changed. + (child_add_thread): Change the debug registers if debug_registers_used. + * config/i386/cygwin.mh: Add use of i386-nat.o file. + Link nm.h to new nm-cygwin.h file. + + config/i386/nm-cygwin.h: New file. Contains the macros used for use + of hardware registers. + +2002-02-03 Andrew Cagney + + * valprint.c (print_floating): Allow non TYPE_CODE_FLT types. + Restore behavour broken by 2002-01-20 Andrew Cagney + IEEE_FLOAT removal. + +2002-02-03 Daniel Jacobowitz + + * c-valprint.c (c_val_print): Pass a proper valaddr to + cp_print_class_method. + * valops.c (search_struct_method): If there is only one method + and args is NULL, return that method. + +2002-02-03 Daniel Jacobowitz + + * gdbtypes.c (init_simd_type): Use TYPE_TAG_NAME instead of + accessing tag_name directly. + +2002-02-03 Daniel Jacobowitz + + * ax-gdb.c (find_field): Use TYPE_TAG_NAME instead + of accessing tag_name directly. + +2002-02-03 Daniel Jacobowitz + + PR gdb/280 + * gdbtypes.c (replace_type): New function. + * gdbtypes.h (replace_type): Add prototype. + * stabsread.c (read_type): Use replace_type. + +2002-02-03 Richard Earnshaw + + * Makefile.in (memattr.o): Add missing dependencies rule. + +2002-02-03 Peter Schauer + + * breakpoint.c (break_at_finish_command): Really export. + (break_at_finish_at_depth_command): Ditto. + (tbreak_at_finish_command): Ditto. + * hppa-tdep.c: Include completer.h. + * Makefile.in (hppa-tdep.o): Add dependency on $(completer_h). + (COMMON_OBS): Remove duplicate ui-file.o, frame.o, doublest.o. + +2002-02-01 Andrew Cagney + + * utils.c (do_write): New function. + (error_stream): Rewrite combining the code from error_begin and + verror. + (verror): Rewrite using error_stream. + (error_begin): Delete function. + +2002-02-01 Andrew Cagney + + * utils.c (error_begin): Make static. + * defs.h (error_begin): Delete declaration. + + * linespec.c (cplusplus_error): Replace cplusplus_hint. + (decode_line_1): Use cplusplus_error instead of error_begin, + cplusplus_hint and return_to_top_level. + * coffread.c (coff_symfile_read): Use error instead of error_begin + and return_to_top_level. + * infrun.c (default_skip_permanent_breakpoint): Ditto. + +2002-02-01 Andrew Cagney + + * language.h (type_error, range_error): Make string parameter + constant. + * language.c (warning_pre_print): Delete extern declaration. + * dwarfread.c (warning_pre_print): Ditto. + * language.c (type_error, range_error): Rewrite to use verror and + vwarning instead of warning_begin. + +2002-02-01 Michael Snyder + + * breakpoint.c (breakpoint_re_set): Delete ancient #if 0 code. + (set_ignore_count): Move misplaced comment back where it belongs. + +2002-02-01 Andrew Cagney + + * command.h (NO_FUNCTION): Delete macro. + * cli/cli-decode.h (NO_FUNCTION): Ditto. + * top.c (execute_command): Replace NO_FUNCTION with NULL. + * tracepoint.c (_initialize_tracepoint): Ditto. + * cli/cli-decode.c (add_set_cmd): Ditto. + * cli/cli-cmds.c (init_cli_cmds): Ditto. + +2002-02-01 Daniel Jacobowitz + + * gnu-v3-abi.c (gnuv3_virtual_fn_field): Update comments. + Update ``this'' pointer when calling virtual functions. + +2002-02-01 Michael Snyder + + * breakpoint.c (create_temp_exception_breakpoint): Delete. + * hppa-tdep.c: Deprecate xbreak, txbreak and bx commands. + +2002-02-01 Daniel Jacobowitz + + * regformats/reg-arm.dat: New file. + * regformats/reg-i386.dat: New file. + * regformats/reg-ia64.dat: New file. + * regformats/reg-m68k.dat: New file. + * regformats/reg-mips.dat: New file. + * regformats/reg-ppc.dat: New file. + * regformats/reg-sh.dat: New file. + * regformats/regdef.h: New file. + * regformats/regdat.sh: New file. + +2002-02-01 Richard Earnshaw + + * arm-tdep.c (arm_frameless_function_invocation): Add some comments. + (arm_frame_args_address, arm_frame_locals_address): New functions. + (arm_frame_num_args): New function. + * config/tm-arm.h (FRAME_ARGS_ADDRESS): Call arm_frame_args_address. + (FRAME_LOCALS_ADDRESS): Call arm_frame_locals_address. + (FRMA_NUM_ARGS): Call arm_frame_num_args. + +2002-01-31 Michael Snyder + + * breakpoint.c (break_at_finish_command): Export. + (break_at_finish_at_depth_command): Export. + (tbreak_at_finish_command): Export. + (_initialize_breakpoint): Delete "xbreak" and "txbreak" commands. + * hppa-tdep.c (_initialize_hppa_tdep): Add "xbreak" and + "txbreak" commands, which are HPPA specific. + + * printcmd.c (disassemble_command): Remove an ancient + artifact of an old merge. + + * symfile.h (enum overlay_debugging_state): + Define enum constant values for overlay mode. + * symfile.c (overlay_debugging): Use enums instead of literals. + (overlay_is_mapped, overlay_auto_command, + overlay_manual_command): Ditto. + + * breakpoint.c (insert_breakpoints, remove_breakpoint, + breakpoint_here_p, breakpoint_inserted_here_p, + breakpoint_thread_match, bpstat_stop_status, + describe_other_breakpoints, check_duplicates, clear_command): + Coding standard fixes. + + * target.c (target_xfer_memory): Add spaces, coding standard. + (do_xfer_memory): Add missing line to trust-readonly + code: check bfd SEC_READONLY flag for section. + +2002-01-31 Andrew Cagney + + * PROBLEMS: Fix typo, 5.1->5.1.1. + +2002-01-30 Daniel Jacobowitz + + * symtab.c (find_pc_sect_psymtab): Do not search psymtabs for + data symbols, since we search based on textlow and texthigh. + (find_pc_sect_symtab): Likewise. + +2002-01-30 Andrew Cagney + + * defs.h (vwarning): Declare. + * utils.c (vwarning): New function. + (warning): Call vwarning. + (warning_begin): Delete function. + + * rs6000-nat.c (vmap_ldinfo): Use the function warning to print + the warning message. + * d10v-tdep.c (d10v_address_to_pointer) [0]: Delete call to + warning_begin. + +2002-01-30 Michael Snyder + + * NEWS: Mention "set trust-readonly-sections" command. + Mention generate-core-file command. + +2002-01-15 Michael Snyder + + * target.c: New command, "set trust-readonly-sections on". + (do_xfer_memory): Honor the suggestion to trust readonly sections + by reading them from the object file instead of from the target. + (initialize_targets): Register command "set trust-readonly-sections". + +2002-01-29 Andrew Cagney + + * parse.c (target_map_name_to_register): Simplify, search regs and + pseudo-regs using a single loop. + +2002-01-30 Andrew Cagney + + * PROBLEMS: Note that the i386 fix was missing from 5.1.1. + +2002-01-15 Rodney Brown + + * config/i386/tm-i386v4.h: Define HAVE_I387_REGS. + * config/i386/i386v42mp.mh: Add i387-nat.o . + * i386v4-nat.c: Include i387-nat.h. + (supply_fpregset): Use i387_supply_fsave. + (fill_fpregset): Use i387_fill_fsave. + +2002-01-30 Richard Earnshaw + + * arm-tdep.c (arm_call_dummy_words): Define. + * arm-linux-tdep.c (arm_linux_call_dummy_words): Define. + * config/arm/tm-arm.h (CALL_DUMMY_P): Define. + (CALL_DUMMY_WORDS): Define. + (arm_call_dummy_words): Declare. + * config/arm/tm-linux.h (CALL_DUMMY_WORDS): Define. + (arm_linux_call_dummy_words): Declare. + +2002-01-30 Andreas Schwab + + * m68klinux-nat.c: Fix last change to use regcache_collect + instead of referencing registers[] directly. + +2002-01-29 Andrew Cagney + + * parse.c (target_map_name_to_register): Delete code wrapped in + #ifdef REGISTER_NAME_ALIAS_HOOK. + +2002-01-28 Michael Snyder + + * regcache.c (legacy_read_register_gen): Need to be able to + read pseudo-register as well as real register. + (legacy_write_register_gen): Ditto. + +2002-01-28 Andrew Cagney + + * config/mips/tm-wince.h (TARGET_BYTE_ORDER): Delete. + * config/sparc/tm-sparc.h (TARGET_BYTE_ORDER): Delete. + * config/ns32k/tm-umax.h (TARGET_BYTE_ORDER): Delete. + * config/ia64/tm-ia64.h (TARGET_BYTE_ORDER): Delete. + * config/m32r/tm-m32r.h (TARGET_BYTE_ORDER): Delete. + * config/m68k/tm-m68k.h (TARGET_BYTE_ORDER): Delete. + * config/m88k/tm-m88k.h (TARGET_BYTE_ORDER): Delete. + * config/mn10200/tm-mn10200.h (TARGET_BYTE_ORDER): Delete. + * config/pa/tm-hppa.h (TARGET_BYTE_ORDER): Delete. + * config/sh/tm-wince.h (TARGET_BYTE_ORDER): Delete. + * config/v850/tm-v850.h (TARGET_BYTE_ORDER): Delete. + * config/vax/tm-vax.h (TARGET_BYTE_ORDER): Delete. + * config/z8k/tm-z8k.h (TARGET_BYTE_ORDER): Delete. + * config/i960/tm-i960.h (TARGET_BYTE_ORDER): Delete. + * config/i386/tm-i386.h (TARGET_BYTE_ORDER): Delete. + * config/h8500/tm-h8500.h (TARGET_BYTE_ORDER): Delete. + * config/h8300/tm-h8300.h (TARGET_BYTE_ORDER): Delete. + * config/fr30/tm-fr30.h (TARGET_BYTE_ORDER): Delete. + * config/d30v/tm-d30v.h (TARGET_BYTE_ORDER): Delete. + * config/alpha/tm-alpha.h (TARGET_BYTE_ORDER): Delete. + +2002-01-28 Andrew Cagney + + * arch-utils.c (TARGET_BYTE_ORDER_DEFAULT): Delete macro. + (target_byte_order): Initialize to BFD_ENDIAN_BIG. + (initialize_current_architecture): Update target_byte_order using + information from BFD. + * config/mcore/tm-mcore.h (TARGET_BYTE_ORDER_DEFAULT): + * config/arm/tm-arm.h (TARGET_BYTE_ORDER_DEFAULT): Delete. + +2002-01-28 Andrew Cagney + + * config/vax/tm-vax.h (INVALID_FLOAT): Move macro from here... + * vax-tdep.c (INVALID_FLOAT): To here. Document why it is broken. + + * rs6000-tdep.c (rs6000_do_registers_info): Delete code wrapped in + #ifdef INVALID_FLOAT. + * infcmd.c (do_registers_info): Ditto. + * values.c (unpack_double): Ditto. Add comment. + + * config/ns32k/tm-umax.h (INVALID_FLOAT): Delete macro that was + already commented out. + +2002-01-26 Andreas Schwab + + * config/m68k/nm-linux.h (FETCH_INFERIOR_REGISTERS): Define. + * m68klinux-nat.c: Update ptrace interface for fetching/storing + registers and add support for PTRACE_GETREGS. + +2002-01-24 Andrew Cagney + + GDB 5.1.1 released from 5.1 branch. + * NEWS: Add 5.1.1 news. + * README: Sync with 5.1 branch. + +2002-01-23 Fred Fish + + * mdebugread.c (parse_partial_symbols): Only copy stabstring1 to + stabstring on initial malloc. Reallocing will copy it for us, + if necessary. + +2002-01-23 Elena Zannoni + + * Makefile.in (hpread_h): Delete. + (HFILES_NO_SRCDIR): Remove hpread.h. + (ALLDEPFILES): Remove hp-psymtab-read.c and hp-symtab-read.c. + (hpread.o): Update dependencies. + (hp-psymtab-read.o, hp-symtab-read.o): Remove. + + * hp-psymtab-read.c: Remove file. + * hp-symtab-read.c: Remove file. + * hpread.h: Remove file. + + * hpread.c: Merge all contents of hp-psymtab-read.c, + hp-symtab-read.c and hpread.h into this file, as it was prior to + January 1999. + + * config/pa/hpux11w.mh, config/pa/hpux11.mh, + config/pa/hpux1020.mh, config/pa/hppaosf.mh, + config/pa/hppahpux.mh, config/pa/hppabsd.mh (NATDEPFILES): + Remove hp-psymtab-read.o and hp-symtab-read.o, add hpread.o. + +2002-01-23 Elena Zannoni + + * ppc-linux-nat.c (ppc_register_u_addr, supply_gregset, + fill_gregset): Call gdbarch_tdep() just once, assign result to + variable and use that, instead of calling the function several + times. + +2002-01-24 Alexandre Oliva + + * configure.host: Accept sparcv9 as alias for sparc64. + * configure.tgt: Likewise. + +2002-01-22 Kevin Buettner + + * solib-aix5.c (build_so_list_from_mapfile) + (aix5_relocate_main_executable): Fix xcalloc() calls so order of + arguments is not reversed. + * solib-sunos.c (sunos_relocate_main_executable): Likewise. + * solib-svr4.c (svr4_relocate_main_executable): Likewise. + +2002-01-22 Elena Zannoni + + * sh-tdep.c (sh_pseudo_register_read): New function. Renamed and + modified version of obsolete sh_fetch_pseudo_register. + (sh_fetch_pseudo_register): Rename to sh_pseudo_register_read. + (sh4_register_read): New function. + (sh_pseudo_register_write): New function. Renamed and modified + version of obsolete sh_store_pseudo_register. + (sh_store_pseudo_register): Rename to sh_pseudo_register_write. + (sh4_register_write): New function. + (sh_gdbarch_init): Remove setting of gdbarch function + fetch_pseudo_register and store_pseudo_register. Remove setting of + register_convert_to_raw, register_convert_to_virtual, + register_convertible. + (sh_sh4_register_convertible): Delete. No longer needed. All is + taken care by architecture specific functions + register_read/register_write. + (sh_sh4_register_convert_to_virtual): Make static. + (sh_sh4_register_convert_to_raw): Ditto. + +2002-01-22 Andrew Cagney + + * doublest.c (floatformat_is_negative): Assert FMT is non NULL. + (floatformat_is_nan, floatformat_mantissa): Ditto. + + * gdbtypes.c (_initialize_gdbtypes): Initialize TYPE_FLOATFORMAT + for builtin_type_ieee_single_little, builtin_type_ieee_double_big, + builtin_type_ieee_double_little, + builtin_type_ieee_double_littlebyte_bigword, + builtin_type_m68881_ext, builtin_type_i960_ext, + builtin_type_m88110_ext, builtin_type_m88110_harris_ext, + builtin_type_arm_ext_big, builtin_type_arm_ext_littlebyte_bigword, + builtin_type_ia64_spill_big, builtin_type_ia64_spill_little and + builtin_type_ia64_quad_big, builtin_type_ia64_quad_little. + +2002-01-22 Corinna Vinschen + + * xstormy16-tdep.c (xstormy16_scan_prologue): Add frameless + parameter. Set frameless flag if it exists and depended of + whether the scanned function is frameless or not. + (xstormy16_skip_prologue): If function is frameless, return + result of xstormy16_scan_prologue(). + (xstormy16_frame_init_saved_regs): Adjust xstormy16_scan_prologue() + call. + +2002-01-21 Elena Zannoni + + * sh-tdep.c (sh_fp_frame_init_saved_regs, sh_push_arguments, + sh_generic_show_regs, sh3_show_regs, sh3e_show_regs, + sh3_dsp_show_regs, sh4_show_regs, sh_dsp_show_regs, + sh_sh4_register_byte, sh_sh4_register_raw_size, + sh_sh3e_register_virtual_type, sh_sh4_register_virtual_type, + sh_sh4_register_convertible, sh_sh4_register_convert_to_virtual, + sh_sh4_register_convert_to_raw, sh_fetch_pseudo_register, + sh_store_pseudo_register, sh_do_pseudo_register): Call + gdbarch_tdep() just once, assign result to variable and use that, + instead of calling the function several times. + +2002-01-20 Mark Kettenis + + * go32-nat.c (fetch_register): Use FP_REGNUM_P and FPC_REGNUM_P + macros instead of LAST_FPU_CTRL_REGNUM. + (store_register): Likewise. + +2002-01-21 Jim Blandy + + * infcmd.c (run_command): Check that the `exec' target layer's BFD + is up-to-date before running the program, not just when a program + exits. + +2002-01-21 Fred Fish + + * arm-tdep.c (thumb_skip_prologue): Quit scanning prologue + when we have found all instructions we are looking for. + +2002-01-21 Richard Earnshaw + + * arm-tdep.c (arm_register_name): New function. + (arm_registers_names): Make static. + * config/arm/tm-arm.h (arm_register_names): Delete declaration. + (arm_register_name): Declare. + (REGISTER_NAME): Use it. + +2002-01-21 Richard Earnshaw + Kevin Buettner + + Convert arm targets to new FRAME interface. + * arm-tdep.c (struct frame_extra_info): Remove fsr. + (arm_frame_find_save_regs): Delete. + (arm_frame_init_saved_regs): New. + (arm_init_extra_frame_info): Alloacte saved_regs as required. + Allocate extra_info as required. Convert all uses of fsr.regs + to use saved_regs, similarly all uses of EXTRA_FRAME_INFO fields + to use extra_info. + (thumb_scan_prologue, arm_scan_prologue, arm_find_callers_reg) + (arm_frame_chain, arm_frame_saved_pc, arm_pop_frame): Likewise. + (check_prologue_cache, save_prologue_cache): Likewise. + (_initialize_arm_tdep): Ensure prologue_cache is correctly set up. + * config/arm/tm-arm.h (EXTRA_FRAME_INFO): Delete. + (FRAME_FIND_SAVED_REGS): Delete. + (arm_frame_find_saved_regs): Delete prototype. + (arm_frame_init_saved_regs): New prototype. + (FRAME_INIT_SAVED_REGS): Define. + +2002-01-20 Andrew Cagney + + * config/arc/tm-arc.h (IEEE_FLOAT): Delete. + +2002-01-20 Andrew Cagney + + From Jeff Law : + * infttrace.c: Include . + (child_pid_to_exec_file): Revamp. Use pstat call to get the + exec file if the ttrace equivalent fails. + +2002-01-20 Andrew Cagney + + * rdi-share/devsw.c (openLogFile): Delete unused ``struct tm lt''. + (closeLogFile): Ditto. + +2002-01-20 Michael Chastain + + * top.c (print_gdb_version): Bump copyright year to 2002. + +2002-01-20 Andrew Cagney + + * MAINTAINERS (Blanket Write Privs): Add Kevin Buettner, Elena + Zannoni and Eli Zaretskii. + +2002-01-20 Daniel Jacobowitz + + * buildsym.c: Update copyright years. + * c-typeprint.c: Likewise. + * dwarf2read.c: Likewise. + * f-typeprint.c: Likewise. + * gdbtypes.c: Likewise. + * gdbtypes.h: Likewise. + * hp-symtab-read.c: Likewise. + * hpread.c: Likewise. + * mdebugread.c: Likewise. + * p-typeprint.c: Likewise. + +2002-01-20 Andrew Cagney + + * remote-sim.c (gdbsim_open): Simplify code testing the macro + TARGET_BYTE_ORDER_SELECTABLE_P. Assume the target is always + byte-order selectable. + * sparc-tdep.c (sparc_target_architecture_hook): Ditto. + * arch-utils.c: Ditto. + (set_endian): Ditto. + (set_endian_from_file): Ditto. + * gdbserver/low-sim.c (create_inferior): Ditto. + * gdbarch.sh: Ditto. + * gdbarch.h: Re-generate. + * config/powerpc/tm-ppc-eabi.h (TARGET_BYTE_ORDER_SELECTABLE_P): + * config/sparc/tm-sparclite.h (TARGET_BYTE_ORDER_SELECTABLE): + * config/sparc/tm-sparclet.h (TARGET_BYTE_ORDER_SELECTABLE): + * config/mcore/tm-mcore.h (TARGET_BYTE_ORDER_SELECTABLE_P): + * config/arm/tm-wince.h (TARGET_BYTE_ORDER_SELECTABLE_P): + * config/arm/tm-linux.h (TARGET_BYTE_ORDER_SELECTABLE_P): + * config/arc/tm-arc.h (TARGET_BYTE_ORDER_SELECTABLE): + * config/arm/tm-arm.h (TARGET_BYTE_ORDER_SELECTABLE_P): Delete + macro definition. + * config/mips/tm-wince.h: Remove #undef of macro + TARGET_BYTE_ORDER_SELECTABLE. + * config/sh/tm-wince.h: Ditto. + +2002-01-20 Daniel Jacobowitz + + * gdbtypes.h (struct cplus_struct_type): Add is_artificial to + member function fields. Add accessor macro + TYPE_FN_FIELD_ARTIFICIAL. + * dwarf2read.c (dwarf2_add_member_fn): Check for artificial methods. + * c-typeprint.c (c_type_print_base): Skip artificial member + functions. + +2002-01-20 Daniel Jacobowitz + + * f-typeprint.c: Delete unused function f_type_print_args. + * p-typeprint.c: Delete unused function pascal_type_print_args. + +2002-01-20 Daniel Jacobowitz + + * gdbtypes.h (struct type): Fix whitespace. Remove obsolete + comment. Add ``artificial'' to ``union field_location''. + + * dwarf2read.c: Remove ad-hoc TYPE_FIELD_ARTIFICIAL. + + * buildsym.c (finish_block): Initialize TYPE_FIELD_ARTIFICIAL to 0. + * mdebugread.c (parse_symbol): Likewise. + * stabsread.c (define_symbol): Likewise. + * hp-symtab-read.c (hpread_function_type): Likewise, instead of + initializing TYPE_FIELD_BITPOS to n (obsolete). + (hpread_doc_function_type): Likewise. + * hpread.c (hpread_function_type): Likewise. + +2002-01-20 Andrew Cagney + + * configure.in (host_makefile_frag): Only require a host makefile + fragment when a native build. + * configure: Re-generate. + +2002-01-20 Andrew Cagney + + * doublest.h (floatformat_from_type): Declare. + * doublest.c (floatformat_from_type): New function. + (convert_typed_floating): Use. + + * valprint.c (print_floating): Replace checks for IEEE_FLOAT with + call to function floatformat_from_type. + + * gdbarch.sh (IEEE_FLOAT): Delete. + * gdbarch.h, gdbarch.c: Re-generate. + * config/i960/tm-i960.h (IEEE_FLOAT): Delete macro. + * config/i386/tm-i386.h (IEEE_FLOAT): Ditto. + * config/z8k/tm-z8k.h (IEEE_FLOAT): Ditto. + * config/sparc/tm-sparc.h (IEEE_FLOAT): Ditto. + * config/pa/tm-hppa.h (IEEE_FLOAT): Ditto. + * config/m88k/tm-m88k.h (IEEE_FLOAT): Ditto. + * config/m68k/tm-m68k.h (IEEE_FLOAT): Ditto. + * config/h8500/tm-h8500.h (IEEE_FLOAT): Ditto. + * config/h8300/tm-h8300.h (IEEE_FLOAT): Ditto. + * config/fr30/tm-fr30.h (IEEE_FLOAT): Ditto. + * config/arm/tm-arm.h (IEEE_FLOAT): Ditto. + * config/alpha/tm-alpha.h (IEEE_FLOAT): Ditto. + + * s390-tdep.c (s390_gdbarch_init): Do not set ieee_float. + * x86-64-tdep.c (i386_gdbarch_init): Ditto. + * sparc-tdep.c (sparc_gdbarch_init): Ditto. + * sh-tdep.c (sh_gdbarch_init): Ditto. + * mips-tdep.c (mips_gdbarch_init): Ditto. + * m68hc11-tdep.c (m68hc11_gdbarch_init): Ditto. + * cris-tdep.c (cris_gdbarch_init): Ditto. + +2002-01-20 Jiri Smid + + * configure.host, configure.tgt: Support x86-64. + * NEWS: Note new target x86-64. + + * config/i386/x86-64linux.mh (NATDEPFILES): x86-64-nat.o removed. + * x86-64-linux-nat.c (x86_64_register_u_addr): New function. + * config/i386/nm-x86-64.h (ATTACH_LWP): Removed. + * Makefile.in (x86-64-tdep.o, x86-64-linux-tdep.o, + x86-64-linux-nat.o): Fix dependencies. + +2002-01-19 Andrew Cagney + + * utils.c: Remove #ifndef MALLOC_INCOMPATIBLE. + * config/sparc/xm-sun4os4.h (PTRACE_ARG3_TYPE): Move macro .... + * config/sparc/nm-sun4os4.h (PTRACE_ARG3_TYPE): ... to here. + * config/sparc/xm-sun4os4.h: Delete file. + * config/sparc/sun4os4.mh (XM_FILE): Delete makefile variable. + +2002-01-19 Andrew Cagney + + * config/sparc/sparclynx.mh (XM_FILE): Delete. + * config/rs6000/rs6000lynx.mh (XM_FILE): Delete. + * config/m68k/m68klynx.mh (XM_FILE): Delete. + * config/i386/i386lynx.mh (XM_FILE): Delete. + * config/rs6000/xm-rs6000ly.h: Delete file. + * config/sparc/xm-sparclynx.h: Delete file. + * config/m68k/xm-m68klynx.h: Delete file. + * config/i386/xm-i386lynx.h: Delete file. + * config/xm-lynx.h: Delete file. + * config/djgpp/fnchange.lst: Update. + +2002-01-19 Jason Thorpe + + * alpha-tdep.c (alpha_register_byte): New function. + (alpha_register_raw_size): Ditto. + (alpha_register_virtual_size): Ditto. + (alpha_skip_prologue_internal): Renamed from + alpha_skip_prologue. + (alpha_skip_prologue): New version that calls + alpha_skip_prologue_internal. + (alpha_in_lenient_prologue): Use alpha_skip_prologue_internal. + * config/alpha/tm-alpha.h (SKIP_PROLOGUE): Remove + second argument from alpha_skip_prologue. + (REGISTER_BYTE): Use alpha_register_byte. + (REGISTER_RAW_SIZE): Use alpha_register_raw_size. + (REGISTER_VIRTUAL_SIZE): Use alpha_register_virtual_size. + (FRAMELESS_FUNCTION_INVOCATION): Use + generic_frameless_function_invocation_not. + (FRAME_NUM_ARGS): Use frame_num_args_unknown. + (COERCE_FLOAT_TO_DOUBLE): Use standard_coerce_float_to_double. + +2002-01-19 Andrew Cagney + + * config/mips/xm-news-mips.h: Delete file. + * config/mips/news-mips.mh (XM_FILE): Delete makefile variable. + + * config/m88k/xm-m88k.h: Delete file. + * config/m88k/xm-dgux.h: Do not include xm-m88k.h. + * config/m88k/xm-delta88v4.h: Ditto. + * config/m88k/xm-delta88.h: Ditto. + + * config/alpha/xm-fbsd.h: Delete file. + * config/alpha/fbsd.mh (XM_FILE): Delete makefile variable. + + * config/sparc/xm-sparc.h: Delete file. + * Makefile.in (xm-sun4os4.h): Delete dependency. + * config/sparc/xm-sun4sol2.h: Do not include xm-sparc.h. + * config/sparc/xm-sun4os4.h: Ditto. + * config/sparc/xm-linux.h: Ditto. + + * config/i386/xm-windows.h: Delete file. + +2002-01-19 Andrew Cagney + + * utils.c: Include for MAXPATHLEN. + (gdb_realpath): Use MAXPATHLEN when PATH_MAX is not defined. + +2002-01-19 Jason Thorpe + + * alpha-tdep.c (alpha_call_dummy_words): New. + * config/alpha/tm-alpha.h (CALL_DUMMY): Remove. + (CALL_DUMMY_P): Define. + (CALL_DUMMY_WORDS): Define. + (SIZEOF_CALL_DUMMY_WORDS): Define. + +2002-01-19 Per Bothner + + * gnu-v3-abi.c (gnuv3_rtti_type): Guard that vtable_symbol_name + isn't NULL, which can happen with some gcj-3.x-produced code. + +2002-01-19 Jason Thorpe + + * alpha-tdep.c (alpha_register_virtual_type): New function. + (alpha_init_frame_pc_first): Ditto. + (alpha_fix_call_dummy): Ditto. + (alpha_store_struct_return): Ditto. + (alpha_extract_struct_value_address): Ditto. + * config/alpha/tm-alpha.h (REGISTER_VIRTUAL_TYPE): Use + alpha_register_virtual_type. + (STORE_STRUCT_RETURN): Use alpha_store_struct_return. + (EXTRACT_STRUCT_VALUE_ADDRESS): Use + alpha_extract_struct_value_address. + (FIX_CALL_DUMMY): Use alpha_fix_call_dummy. + (INIT_FRAME_PC): Use init_frame_pc_noop. + (INIT_FRAME_PC_FIRST): Use alpha_init_frame_pc_first. + +2002-01-19 Mark Kettenis + + * i386gnu-nat.c: Include "i386-tdep.h". + (fetch_fpregs): Simplify code dealing with uninitialized floating + point states such that it doesn't require FP7_REGNUM. + +2002-01-18 Jason Thorpe + + * alpha-tdep.c (frame_extra_info): New. + (alpha_find_saved_regs): Make static. Use + frame->extra_info. + (alpha_frame_init_saved_regs): New function. + (alpha_frame_saved_pc): Use frame->extra_info. + (temp_saved_regs): Don't declare as struct frame_saved_regs. + (heuristic_proc_desc): Adjust for temp_saved_regs changes. + (init_extra_frame_info): Rename to... + (alpha_init_extra_frame_info): ...this. Use frame->extra_info. + (alpha_print_extra_frame_info): New function. + (alpha_frame_locals_address): Ditto. + (alpha_frame_args_address): Ditto. + (alpha_pop_frame): Use frame->extra_info. + * config/alpha/tm-alpha.h (FRAME_ARGS_ADDRESS): Use + alpha_frame_args_address. + (FRAME_LOCALS_ADDRESS): Use alpha_frame_locals_address. + (alpha_find_saved_regs): Remove prototype. + (FRAME_INIT_SAVED_REGS): Use alpha_frame_init_saved_regs. + (EXTRA_FRAME_INFO): Remove. + (INIT_EXTRA_FRAME_INFO): Use alpha_init_extra_frame_info. + (PRINT_EXTRA_FRAME_INFO): Use alpha_print_extra_frame_info. + +2002-01-18 Jason Thorpe + + * alpha-tdep.c (alpha_osf_in_sigtramp): New function. + (alpha_cannot_fetch_register): Ditto. + (alpha_cannot_store_register): Ditto. + (alpha_register_convertible): Ditto. + (alpha_use_struct_convention): Ditto. + * config/alpha/tm-alpha.h: Update copyright years. + (IN_SIGTRAMP): Use alpha_osf_in_sigtramp. + (INNER_THAN): Use core_addr_lessthan. + (CANNOT_FETCH_REGISTER): Use alpha_cannot_fetch_register. + (CANNOT_STORE_REGISTER): Use alpha_cannot_store_register. + (REGISTER_CONVERTIBLE): Use alpha_register_convertible. + (USE_STRUCT_CONVENTION): Use alpha_use_struct_convention. + (FRAME_CHAIN): Remove unnecessary cast. + +2002-01-18 Andrew Cagney + + * NEWS: Document that testsuite/gdb.hp/gdb.threads-hp/ is + obsolete. + +2002-01-18 Andrew Cagney + + * infptrace.c: Remove ATTRIBUTE_UNUSED. Update copyright. + * monitor.c, remote-array.c, remote-bug.c: Ditto. + * remote-e7000.c, remote-es.c, remote-mips.c: Ditto. + * remote-nindy.c, remote-os9k.c, remote-rdi.c: Ditto. + * remote-rdp.c, remote-sds.c, remote-sim.c: Ditto. + * remote-st.c, remote-vx.c, remote.c, win32-nat.c: Ditto. + * x86-64-linux-nat.c: Ditto. + +2002-01-18 Jason Thorpe + + * alpha-tdep.c (alpha_register_name): New function. + * config/alpha/tm-alpha.h (REGISTER_NAMES): Remove. + (REGISTER_NAME): Define. + +2002-01-18 Jason Thorpe + + * config/nm-nbsd.h (KERNEL_U_ADDR): Remove. + +2002-01-18 Jason Thorpe + + * alpha-tdep.c: Update copyright years. + (alpha_next_pc): New function. + (alpha_software_single_step): Ditto. + * config/alpha/tm-alpha.h: Add prototype for + alpha_software_single_step. + +2002-01-18 Jason Thorpe + + * alphabsd-nat.c: Update copyright years. + (fill_gregset): Use regcache_collect. + (fill_fpregset): Likewise. + (fetch_inferior_registers): Only fetch integer registers + if requested to do so. + (store_inferior_registers): Only store integer registers + if requested to do so. + +2002-01-17 Andrew Cagney + + * config/alpha/alpha-osf3.mh (XDEPFILES): Delete. + * config/alpha/alpha-osf2.mh (XDEPFILES): Delete. + * config/alpha/alpha-osf1.mh (XDEPFILES): Delete. + * config/alpha/alpha-linux.mh (XDEPFILES): Delete. + * config/alpha/fbsd.mh (XDEPFILES): Delete. + * config/arm/linux.mh (XDEPFILES): Delete. + * config/arm/nbsd.mh (XDEPFILES): Delete. + * config/i386/i386dgux.mh (XDEPFILES): Delete. + * config/i386/i386sol2.mh (XDEPFILES): Delete. + * config/i386/i386m3.mh (XDEPFILES): Delete. + (NATDEPFILES): Move i387-tdep.o and core-aout.o to here. + * config/i386/i386gnu.mh (XDEPFILES): Delete. + * config/i386/fbsd.mh (XDEPFILES): Delete. + * config/i386/i386bsd.mh (XDEPFILES): Delete. + * config/i386/i386sco5.mh (XDEPFILES): Delete. + * config/i386/i386v4.mh (XDEPFILES): Delete. + * config/i386/i386v42mp.mh (XDEPFILES): Delete. + * config/i386/i386sco4.mh (XDEPFILES): Delete. + * config/i386/i386aix.mh (XDEPFILES): Delete. + * config/i386/go32.mh (XDEPFILES): Delete. + * config/i386/cygwin.mh (XDEPFILES): Delete. + * config/i386/i386lynx.mh (XDEPFILES): Delete. + * config/i386/i386mach.mh (XDEPFILES): Delete. + * config/i386/i386v32.mh (XDEPFILES): Delete. + * config/i386/linux.mh (XDEPFILES): Delete. + * config/i386/nbsdelf.mh (XDEPFILES): Delete. + * config/i386/ncr3000.mh (XDEPFILES): Delete. + * config/i386/i386mk.mh (NATDEPFILES): Rename XDEPFILES. + * config/i386/i386sco.mh (XDEPFILES): Delete. + * config/i386/i386v.mh (XDEPFILES): Delete. + * config/i386/nbsd.mh (XDEPFILES): Delete. + * config/i386/ptx.mh (NATDEPFILES): Rename XDEPFILES. + * config/i386/ptx4.mh (NATDEPFILES): Rename XDEPFILES. + * config/i386/symmetry.mh (XDEPFILES): Delete. + * config/i386/obsd.mh (XDEPFILES): Delete. + * config/i386/x86-64linux.mh (XDEPFILES): Delete. + * config/ia64/linux.mh (XDEPFILES): Delete. + * config/ia64/aix.mh (XDEPFILES): Delete. + * config/m68k/apollo68b.mh (XDEPFILES): Delete. + * config/m68k/dpx2.mh (XDEPFILES): Delete. + * config/m68k/3b1.mh (NATDEPFILES): Rename XDEPFILES. + * config/m68k/apollo68v.mh (XDEPFILES): Delete. + * config/m68k/hp300bsd.mh (XDEPFILES): Delete. + * config/m68k/linux.mh (XDEPFILES): Delete. + * config/m68k/m68klynx.mh (XDEPFILES): Delete. + * config/m68k/m68kv4.mh (XDEPFILES): Delete. + * config/m68k/nbsd.mh (XDEPFILES): Delete. + * config/m68k/sun2os3.mh (XDEPFILES): Delete. + * config/m68k/sun2os4.mh (XDEPFILES): Delete. + * config/m68k/sun3os3.mh (XDEPFILES): Delete. + * config/m68k/sun3os4.mh (XDEPFILES): Delete. + * config/m88k/delta88.mh (XDEPFILES): Delete. + * config/m88k/delta88v4.mh (XDEPFILES): Delete. + * config/m88k/m88k.mh (XDEPFILES): Delete. + * config/mips/littlemips.mh (NATDEPFILES): Rename XDEPFILES. + * config/mips/linux.mh (XDEPFILES): Delete. + * config/mips/irix6.mh (XDEPFILES): Delete. + * config/mips/irix5.mh (XDEPFILES): Delete. + * config/mips/irix4.mh (XDEPFILES): Delete. + * config/mips/irix3.mh (XDEPFILES): Delete. + * config/mips/decstation.mh (XDEPFILES): Delete. + * config/mips/mipsm3.mh (XDEPFILES): Delete. + (NATDEPFILES): Move core-aout.o to here. + * config/ns32k/nbsd.mh (XDEPFILES): Delete. + * config/pa/hpux1020.mh (XDEPFILES): Delete. + * config/pa/hppabsd.mh (XDEPFILES): Delete. + * config/pa/hppahpux.mh (XDEPFILES): Delete. + * config/pa/hpux11w.mh (XDEPFILES): Delete. + * config/pa/hppaosf.mh (XDEPFILES): Delete. + * config/pa/hpux11.mh (XDEPFILES): Delete. + * config/powerpc/aix.mh (XDEPFILES): Delete. + * config/powerpc/nbsd.mh (XDEPFILES): Delete. + * config/powerpc/linux.mh (XDEPFILES): Delete. + * config/romp/rtbsd.mh: Rename XDEPFILES. + * config/rs6000/rs6000lynx.mh (XDEPFILES): Delete. + * config/rs6000/aix4.mh (XDEPFILES): Delete. + * config/rs6000/rs6000.mh (XDEPFILES): Delete. + * config/s390/s390.mh (XDEPFILES): Delete. + * config/vax/vaxbsd.mh (NATDEPFILES): Rename XDEPFILES. + * config/sparc/sun4sol2.mh (XDEPFILES): Delete. + * config/sparc/sun4os4.mh (XDEPFILES): Delete. + * config/sparc/sparclynx.mh (XDEPFILES): Delete. + * config/sparc/nbsdelf.mh (XDEPFILES): Delete. + * config/sparc/nbsd.mh (XDEPFILES): Delete. + * config/sparc/linux.mh (XDEPFILES): Delete. + * config/vax/vaxult.mh (XDEPFILES): Delete. + * config/vax/vaxult2.mh (XDEPFILES): Delete. + * Makefile.in (DEPFILES): Remove XDEPFILES. + +2002-01-17 Andrew Cagney + + * utils.c (internal_verror): Fix comments, default is yes not no. + Update queries to match. Default to quit and dump core. + +2002-01-17 Andrew Cagney + + * breakpoint.c: Update assuming #if UI_OUT is always true. Update + copyright. + * defs.h, event-top.c, gdbcmd.h: Ditto. + * infcmd.c, infrun.c, main.c, printcmd.c, remote.c: Ditto. + * source.c, stack.c, symfile.c, symtab.c, thread.c: Ditto. + * top.c, cli/cli-cmds.c, cli/cli-decode.c: Ditto. + * cli/cli-script.c, cli/cli-script.h, cli/cli-setshow.c: Ditto. + * mi/ChangeLog, mi/mi-cmd-break.c, mi/mi-cmd-stack.c: Ditto. + * mi/mi-main.c:Ditto. + + * stack.c, symfile.c: Update copyright. + +2002-01-17 Daniel Jacobowitz + + * gdbserver/low-hppabsd.c, gdbserver/low-lynx.c, + gdbserver/low-nbsd.c, gdbserver/low-sim.c, + gdbserver/low-sparc.c, gdbserver/low-sun3.c, + gdbserver/low-linux.c, gdbserver/server.c: Correct copyright notices. + +2002-01-17 Daniel Jacobowitz + + * gdbserver/low-hppabsd.c (myattach): New function, returning -1. + * gdbserver/low-lynx.c (myattach): Likewise. + * gdbserver/low-nbsd.c (myattach): Likewise. + * gdbserver/low-sim.c (myattach): Likewise. + * gdbserver/low-sparc.c (myattach): Likewise. + * gdbserver/low-sun3.c (myattach): Likewise. + + * gdbserver/low-linux.c (myattach): New function. + + * gdbserver/server.c (attach_inferior): New function. + (main): Handle "--attach". + +2002-01-16 Andrew Cagney + + * MAINTAINERS (language support): Daniel Jacobwitz is C++ + maintainer. + +2002-01-15 Daniel Jacobowitz + + * c-typeprint.c (is_type_conversion_operator): Add additional + check for non-conversion operators. + +2002-01-15 Michael Snyder + + * linux-proc.c: Add "info proc" command, a la procfs.c. + (read_mapping): New function, abstract and re-use code. + (linux_find_memory_regions): Use new func read_mapping. + (linux_info_proc_cmd): New function, implement "info proc". + (_initialize_linux_proc): Add new command "info proc". + +2002-01-15 Michael Snyder + + * symfile.c (generic_load): Use bfd_map_over_sections method + instead of manipulating bfd structure members directly. + (add_section_size_callback): New function, bfd sections callback + used by generic_load. + (load_sections_callback): New function, bfd sections callback + used by generic_load. + +2002-01-15 Elena Zannoni + + [Based on work by Jim Blandy] + * gdbtypes.h (builtin_type_v16qi, builtin_type_v8hi): Export. + (builtin_type_vec128): Export. + * gdbtypes.c (builtin_type_v16qi, builtin_type_v8hi): New SIMD + types. + (builtin_type_vec128): New builtin type for 128 bit vector + registers. + (build_gdbtypes): Initialize builtin_type_v16qi and + builtin_type_v8hi. Create the vec128 register builtin type + structure. + (build_builtin_type_vec128): New function. + (_initialize_gdbtypes): Register builtin_type_v16qi and + builtin_type_v8hi with gdbarch. Same for builtin_type_vec128. + * rs6000-tdep.c (rs6000_register_virtual_type): Change type of + AltiVec register to new builtin type. + +2001-01-15 Daniel Jacobowitz + + * stabsread.c (read_type): Pass dbx_lookup_type (typenums) + to make_cv_type. + +2002-01-14 Andrew Cagney + + * config/pa/tm-hppa.h (DEPRECATED_CLEAN_UP_REGISTER_VALUE): Rename + CLEAN_UP_REGISTER_VALUE. + * regcache.c (supply_register): Update only call. + +2002-01-14 Andrew Cagney + + * configure.tgt: Mark a29k-*-aout*, a29k-*-coff*, a29k-*-elf*, + a29k-*-ebmon*, a29k-*-kern*, a29k-*-none*, a29k-*-udi* and + a29k-*-vxworks* targets as obsolete. + +2002-01-14 Michael Snyder + + * linux-proc.c (linux_do_thread_registers): Ignore fpxregs + until we can resolve portability issues. + * gregset.h: Remove references to fpxregs. + * gcore.c (gcore_command): Initialize note_sec to NULL. + +2002-01-13 Andrew Cagney + + * signals.c (target_signal_to_name): Rewrite. Only use + signals[].name when in bounds and non-NULL. + +2002-01-13 Andrew Cagney + + From Petr Ledvina : + * signals.c (target_signal_to_name): Verify that SIG is within the + bounds of the signals array. + +2002-01-13 Andrew Cagney + + * MAINTAINERS: Remove arm-coff and arm-pe from target list. + +2002-01-13 Keith Seitz + + * stack.c (print_frame_info_base): Print the frame's pc + only if when print_frame_info_listing_hook is not defined. + +2002-01-13 Keith Seitz + + * varobj.c (varobj_set_value): Make sure that there were no + errors evaluating the object before attempting to set its + value. + value_cast now properly adjusts VALUE_ADDRESS for baseclasses, + so this offset adjustment is no longer necessary. + (create_child): Don't set the error flag if the child is + a CPLUS_FAKE_CHILD. + (value_of_child): If value_fetch_lazy fails, return NULL + so that callers will be notified that an error occurred. + (c_value_of_variable): Delay check of variable's validity + until later. We actually want all structs and unions to have + the value "{...}". + Do not return "???" for variables which could not be evaluated. + This error condition must be returned to the caller so that it + can get the error condition from gdb. + (cplus_name_of_child): Adjust index for vptr before figuring + out the name of the child. + (cplus_value_of_child): If a child's (real) parent is not valid, + don't even bother trying to give a value for it. Just return + an error. Change all instances in this function. + (cplus_type_of_child): If our parent is one of the "fake" + parents, we need to get at the type of the real parent, and + derive the child's true type using this information. + +2002-01-13 Andrew Cagney + + From 2002-01-09 John Marshall : + * CONTRIBUTE, README, TODO: Change sourceware.cygnus.com to + sources.redhat.com, and tweak some related URLs which had + suffered from linkrot. + +2002-01-13 Andrew Cagney + + From Jeff law: + * hppa-tdep.c (hppa_push_arguments): Correct handling of 5-7 byte + structures passed in registers. + +2002-01-13 Eli Zaretskii + + * go32-nat.c (save_npx) [__DJGPP_MINOR__ < 3]: Remove extraneous + white space which prevented compilation. Reported by DSK + . + +2002-01-11 Michael Snyder + + * symfile.c (build_section_addr_info_from_section_tab): + Use bfd access method instead of manipulating bfd directly. + (syms_from_objfile): Ditto. + (simple_overlay_update_1): Ditto. + (simple_overlay_update): Ditto. + (generic_load): Ditto. + (overlay_unmapped_address): FIXME comment, bfd access methods. + (sections_overlap): FIXME comment, bfd access methods. + (pc_in_mapped_range): FIXME comment, bfd access methods. + (pc_in_unmapped_range): FIXME comment, bfd access methods. + (section_is_mapped): FIXME comment, bfd access methods. + (section_is_overlay): FIXME comment, bfd access methods. + + * symfile.c (generic_load): Whitespace and long line cleanups. + Remove duplicate variable, change several local variables to + more appropriate data types. + (print_transfer_performance): Use %lu instead of %ld for ulongs. + +2002-01-12 Andrew Cagney + + From Peter Schauer: + * language.c (longest_local_hex_string_custom): Use phex_nz to + convert NUM to a hex string. + +2002-01-12 Elena Zannoni + + * sh-tdep.c (sh_gdbarch_init): Move setting of long_bit earlier in + the function. + Update Copyright year. + +2002-01-12 Andrew Cagney + + * language.c (longest_raw_hex_string): Delete unused function. + +2002-01-11 Petr Sorfa + + * MAINTAINERS (write-after-approval): Add myself. + * dwarf2read.c (read_tag_string_type): Handling of + DW_AT_byte_size. + (read_tag_string_type): FORTRAN fix to prevent propagation of + first string size. + (set_cu_language): Handling of DW_LANG_Fortran95 + +2002-01-11 Richard Earnshaw + + * armnbsd-nat.c (fetch_inferior_registers): Change inferior_pid -> + GETPID(inferior_ptid). + (store_inferior_registers): Likewise. + +2002-01-10 Jason Merrill + + * dwarf2read.c (decode_locdesc): Implement DW_OP_litn, DW_OP_dup. + Fix DW_OP_minus. + +2002-01-10 Andrew Cagney + + * config/djgpp/fnchange.lst: Add renames for bfd/ChangeLog-0001 + and bfd/elf32-sh-nbsd.c. + +2002-01-10 Michael Snyder + + * NEWS: Mention --pid and corefile/proc-id behavior change. + + * Makefile.in: Add rules for gcore.o and linux-proc.o. + * gcore.c: Include cli/cli-decode.h instead of command.h. + + * main.c (captured_main): Add new command line option "--pid". + If the second command line argument (following the symbol-file) + begins with a digit, try to attach to it before trying to open + it as a corefile. + (print_gdb_help): Document the "--pid" argument. + +2002-01-10 Eli Zaretskii + + * completer.c (command_completer): New function. + + * completer.h : Add prototype. + + * cli/cli-cmds.c (init_cli_cmds): Make command_completer be the + completer for the "help" command. + +2002-01-09 Jason Merrill + + * c-typeprint.c (is_type_conversion_operator): Fix thinko. + +2002-01-09 Michael Snyder + + * i386-linux-nat.c (fill_fpxregset): Make global. + (store_fpxregset): Ditto. + + * gregset.h (gdb_fpxregset_t): Define. + (supply_fpxregset): Prototype. + (fill_fpxregset): Prototype. + + * exec.c (exec_make_note_section): Don't call elfcore_write_prpsinfo. + +2002-01-09 Richard Earnshaw + + * config/arm/arm-tdep.h (arm_software_single_step): Remove PARAMS. + * config/arm/nm-nbsd.h (arm_register_u_addr): Likewise. + * config/arm/tm-nbsd.h (get_longjmp_target): Likewise. + +2002-01-09 Andrew Cagney + + * MAINTAINERS: Update target maintainer rules so that any + Maintainer can approve a tested patch for a maintenance-only + target. + +2002-01-09 Richard Earnshaw + + * MAINTAINERS (write-after-approval): Add myself. + + * arm-tdep.c (arm_init_extra_frame_info): Cast NULL argument to + IN_SIGTRAMP. + +2002-01-08 Michael Snyder + + * linux-proc.c (child_pid_to_exec_file): Use readlink to get the + real name of the executable, rather than the /proc name. + +2002-01-03 Michael Snyder + + Implement a "generate-core-file" command in gdb, save target state. + * gcore.c: New file. Implement new command 'generate-core-file'. + Save a corefile image of the current state of the inferior. + * linux-proc.c: Add linux-specific code for saving corefiles. + * target.h (struct target_ops): Add new target vectors for saving + corefiles; to_find_memory_regions and to_make_corefile_notes. + (target_find_memory_regions): New macro. + (target_make_corefile_notes): New macro. + * target.c (update_current_target): Inherit new target methods. + (dummy_find_memory_regions): New place-holder method. + (dummy_make_corefile_notes): New place-holder method. + (init_dummy_target): Initialize new dummy target vectors. + * exec.c (exec_set_find_memory_regions): New function. + Allow the exec_ops vector for memory regions to be taken over. + (exec_make_note_section): New function, target vector method. + * defs.h (exec_set_find_memory_regions): Export prototype. + * procfs.c (proc_find_memory_regions): New function, corefile method. + (procfs_make_note_section): New function, corefile method. + (init_procfs_ops): Set new target vector pointers. + (find_memory_regions_callback): New function. + (procfs_do_thread_registers): New function. + (procfs_corefile_thread_callback): New function. + * sol-thread.c (sol_find_memory_regions): New function. + (sol_make_note_section): New function. + (init_sol_thread_ops): Initialize new target vectors. + * inftarg.c (inftarg_set_find_memory_regions): New function. + Allow to_find_memory_regions vector to be taken over. + (inftarg_set_make_corefile_notes): New function. + Allow to_make_corefile_notes vector to be taken over. + * thread-db.c (thread_db_new_objfile): Don't activate thread-db + interface layer if not target_has_execution (may be a corefile). + * config/i386/linux.mh: Add gcore.o to NATDEPFILES. + * config/sparc/sun4sol2.mh: Ditto. + * config/alpha/alpha-linux.mh: Ditto. + * config/arm/linux.mh: Ditto. + * config/i386/x86-64linux.mh: Ditto. + * config/ia64/linux.mh: Ditto. + * config/m68k/linux.mh: Ditto. + * config/mips/linux.mh: Ditto. + * config/powerpc/linux.mh: Ditto. + * config/sparc/linux.mh: Ditto. + +2002-01-07 Michael Snyder + + * arm-linux-nat.c: Remove references to regcache.c internal data + (registers[] and register_valid[]). + +2002-01-07 Michael Snyder + + * linux-proc.c: New file. Implement child_pid_to_exec_file, + so that attaching to a pid will automatically read the process's + symbol file and shlibs. + * Makefile.in: Add rule for linux-proc.o. + * config/nm-linux.h: Define CHILD_PID_TO_EXEC_FILE. + * config/alpha/alpha-linux.mh: Add linux-proc.o to NATDEPFILES. + * config/arm/linux.mh: Ditto. + * config/i386/linux.mh: Ditto. + * config/i386/x86-64linux.mh: Ditto. + * config/ia64/linux.mh: Ditto. + * config/m68k/linux.mh: Ditto. + * config/mips/linux.mh: Ditto. + * config/powerpc/linux.mh: Ditto. + * config/sparc/linux.mh: Ditto. + +2002-01-06 Pierre Muller + + * win32-nat.c: Add i386-tdep.h dependency. + +2002-01-07 Michael Snyder + + * solib.c (info_sharedlibrary_command): Use TARGET_PTR_BIT + instead of bfd_get_arch_size. Don't bail out just because + there's no exec_bfd. + + * cp-valprint.c (cp_print_value): FIXME comment, alloca size. + * p-valprint.c (pascal_object_print_value): Ditto. + * somread.c (som_symtab_read): Ditto. + * symfile.c (simple_free_overlay_region_table): Ditto. + * valops.c (value_assign): Ditto. + + * tracepoint.c (tracepoint_save_command): From Klee Dienes -- + use tilde_expand and strerror for opening save-tracepoints file. + + * thread-db.c (thread_db_new_objfile): Indendation fix. + + * infptrace.c (GDB_MAX_ALLOCA): New define. + (child_xfer_memory): Use xmalloc/xfree instead of alloca if the + size of the buffer exceeds GDB_MAX_ALLOCA (default 1 megabyte, + can be overridden with whatever value is appropriate to the host). + * infttrace.c (child_xfer_memory): Add FIXME warning about use of + alloca to allocate potentially large buffer. + * rs6000-nat.c (child_xfer_memory): Ditto. + * symm-nat.c (child_xfer_memory): Ditto. + * x86-64-linux-nat.c (child_xfer_memory): Ditto. + +2002-01-07 Jackie Smith Cashion + + From Nick Clifton + * d10v-tdep.c: Set STACK_START to 0x200bffe. + +2002-01-07 Michael Snyder + + * solib-legacy.c (legacy_svr4_fetch_link_map_offsets): + Don't use exec_bfd if it's NULL. + +2002-01-06 Mark Kettenis + + * valops.c (value_arg_coerce): Fix formatting. + +2002-01-06 Andrew Cagney + + * hp-psymtab-read.c: Include "gdb_string.h" instead of . + * gnu-nat.c: Ditto. + +2002-01-06 Andrew Cagney + + * MAINTAINERS: Note that alpha-dec-osf4.0a, arc-elf, arm-coff, + arm-elf, arm-pe, d30v-elf, fr30-elf, h8300hms, h8500hms, + i960-coff, m32r-elf, m68k-elf, m88k, mcore-elf, mn10200-elf, + ns32k-netbsd, hppa1.1-hp-proelf, v850-elf, vax-dec-vms5.5 and + z8k-coff have not been multi-arched. Update z8k-coff build + status. + +2002-01-06 Andrew Cagney + + * MAINTAINERS: Mark a29k target as obsolete. + * Makefile.in (a29k-tdep.o, remote-adapt.o, remote-eb.o) + (remote-mm.o, remote-udi.o): Obsolete. Remove references in + comments. + * NEWS: Note that a29k targets are obsolete. + * a29k-tdep.c: Mark as obsolete. + * configure.tgt: Mark a29k-*-aout*, a29k-*-coff*, a29k-*-elf*, + a29k-*-ebmon*, a29k-*-kern*, a29k-*-none*, a29k-*-udi* and + a29k-*-vxworks* targets as obsolete. + * remote-adapt.c: Obsolete. + * remote-eb.c: Obsolete. + * remote-mm.c: Obsolete. + * remote-udi.c: Obsolete. + * config/a29k/a29k-udi.mt: Obsolete. + * config/a29k/a29k.mt: Obsolete. + * config/a29k/tm-a29k.h: Obsolete. + * config/a29k/tm-vx29k.h: Obsolete. + * config/a29k/vx29k.mt: Obsolete. + +2002-01-05 Andrew Cagney + + * rs6000-tdep.c (rs6000_do_registers_info): Replace BIG_ENDIAN + with BFD_ENDIAN_BIG. + +2002-01-05 Andrew Cagney + + * configure.in (AC_CHECK_HEADERS): Do not check for . + * configure, config.in: Re-generate. + * config/vax/xm-vaxbsd.h: Do not include . + * defs.h: Do not include . + +2002-01-05 Jason Thorpe + + * acconfig.h (HAVE_PT_GETXMMREGS): New. + * config.in: Regenerate. + * configure.in: Update copyright years. + Add test for PT_GETXMMREGS supplied by . + * configure: Regenerate. + * i386bsd-nat.c: Update copyright years. + (fill_gregset): Use regcache_collect. + (fetch_inferior_registers): Only fetch integer registers + if requested to do so. Add support for XMM registers + using PT_GETXMMREGS. + (store_inferior_registers): Only store integer registers + if requested to do so. Add support for XMM registers + using PT_SETXMMREGS. + * i386nbsd-nat.c (fetch_inferior_registers): Remove. + (store_inferior_registers): Remove. + (fetch_core_registers): Use supply_gregset and i387_supply_fsave. + (fetch_elfcore_registers): New function. + (i386nbsd_elfcore_fns): New. + (_initialize_i386nbsd_nat): Register i386nbsd_elfcore_fns. + * config/i386/nbsd.mh (NATDEPFILES): Add i387-nat.o and + i386bsd-nat.o. + * config/i386/nbsdelf.mh (NATDEPFILES): Likewise. + * config/i386/nbsd.mt (TDEPFILES): Add i386bsd-nat.o. + * config/i386/nbsdelf.mt (TDEPFILES): Likewise. + * config/i386/tm-nbsd.h: Update copyright years. + (HAVE_SSE_REGS): Define. + (IN_SIGTRAMP): Define as i386bsd_in_sigtramp. + (SIGTRAMP_START): Redefine as i386bsd_sigtramp_start. + (SIGTRAMP_END): Redefine as i386bsd_sigtramp_end. + (SIGCONTEXT_PC_OFFSET): Remove. + (FRAME_SAVED_PC): Define as i386bsd_frame_saved_pc. + +2002-01-05 Andrew Cagney + + * configure.tgt: Remove powerpc-*-macos* target. + * config/m68k/xm-mpw.h: Delete file. + * config/xm-mpw.h: Delete file. + * ser-mac.c: Delete file. + * mpw-make.sed: Delete file. + * mpw-config.in: Delete file. + * mac-xdep.c: Delete file. + * mac-gdb.r: Delete file. + * mac-defs.h: Delete file. + * mac-nat.c: Delete file. + * config/powerpc/macos.mh: Delete file. + * config/powerpc/macos.mt: Delete file. + * config/powerpc/nm-macos.h: Delete file. + * config/powerpc/tm-macos.h: Delete file. + * source.c (openp, open_source_file): Remove obsolete code. + * top.c (gdb_readline): Ditto. + * utils.c (query): Ditto. + * event-top.c (display_gdb_prompt): Ditto. + * Makefile.in (ser-mac.o): Delete obsolete target. + * NEWS: Update. + +2002-01-04 Andrew Cagney + + * defs.h (BIG_ENDIAN): Delete macro definition. + * a29k-tdep.c, arch-utils.c, arm-tdep.c, ax-gdb.c, ch-exp.c, + coffread.c, cris-tdep.c, d10v-tdep.c, d30v-tdep.c, defs.h, + findvar.c, infcmd.c, mem-break.c, mips-tdep.c, mn10300-tdep.c, + printcmd.c, remote-os9k.c, remote-rdi.c, remote-rdp.c, + remote-sim.c, remote.c, rs6000-tdep.c, sh-tdep.c, sparcl-tdep.c, + stabsread.c, valops.c, valprint.c, config/a29k/tm-a29k.h, + config/a29k/tm-vx29k.h, config/arm/tm-arm.h, + config/d30v/tm-d30v.h, config/fr30/tm-fr30.h, + config/h8300/tm-h8300.h, config/h8500/tm-h8500.h, + config/m32r/tm-m32r.h, config/m68k/tm-m68k.h, + config/m88k/tm-m88k.h, config/mips/tm-mips.h, config/pa/tm-hppa.h, + config/sparc/tm-sparc.h, config/z8k/tm-z8k.h, mi/mi-cmd-disas.c, + mi/mi-main.c: Replace BIG_ENDIAN with BFD_ENDIAN_BIG. + * gdbarch.sh: Replace BIG_ENDIAN with BFD_ENDIAN_BIG. + * gdbarch.c: Re-generate. + +2002-01-04 Daniel Jacobowitz + + * thread-db.c (thread_db_new_objfile): Do not enable thread_db + for core files. + +2002-01-04 Jason Thorpe + + * config/arm/nbsd.mh (XDEPFILES): Remove ser-tcp.o. + +2002-01-04 Andrew Cagney + + * value.h (value_ptr): Delete typedef. + +2002-01-04 Jason Thorpe + + * i386nbsd-nat.c: Update copyright years. + Include i386-tdep.h. + +2002-01-04 Elena Zannoni + + * stabsread.c: Update copyright years. + + From Debashis Mahata : + (read_struct_fields): Deal with Sun C compiler erroneous stab + output for structs and unions. + Fix PR gdb/269. + +2002-01-04 Daniel Jacobowitz + + * p-valprint.c: Include "cp-abi.h" for baseclass_offset + prototype. + +2002-01-04 Daniel Jacobowitz + + * cp-abi.c: Fix whitespace. + (baseclass_offset): New wrapper function. + * cp-abi.h (baseclass_offset): Add prototype. + (struct cp_abi_ops): Add baseclass_offset pointer. + + * valops.c (vb_match): Move to... + * gnu-v2-abi.c (vb_match): here. + * valops.c (baseclass_offset): Move to... + * gnu-v2-abi.c (gnuv2_baseclass_offset): here, and rename. + + * gnu-v3-abi.c (gnuv3_baseclass_offset): New function. + + * gnu-v2-abi.c (init_gnuv2_ops): Initialize baseclass_offset. + * gnu-v3-abi.c (init_gnuv3_ops): Likewise. + * hpacc-abi.c (init_hpacc_ops): Likewise. + +2002-01-04 Daniel Jacobowitz + + * valops.c (find_overload_match): Accept obj as a + reference parameter. Update it before returning. + * value.h (find_overload_match): Update prototype. + * eval.c (evaluate_subexp_standard): Pass object to + find_overload_match by reference. + +2002-01-03 Andrew Cagney + + * valarith.c: Replace value_ptr with struct value pointer. Remove + register attribute from value declarations. + * valops.c: Ditto. + * value.h: Ditto. + * scm-lang.c (scm_lookup_name): Ditto. + +2002-01-03 Michael Snyder + + Abstract the functionality of iterating over mapped memory + regions into a general purpose iterator function. + * procfs.c (iterate_over_mappings): New function, general purpose + iterator for memory sections. + (proc_iterate_over_mappings): Reimplement using iterate_over_mappings. + (solib_mappings_callback): New function, callback for above. + (info_proc_mappings): Reimpliment using iterate_over_mappings. + (info_mappings_callback): New function, callback for above. + + * procfs.c (proc_set_watchpoint): Add cast to suppress warning. + +2002-01-01 Mark Kettenis + + * i386-tdep.h (struct gdbarch_tdep): Add `os_ident' member. + * i386-tdep.c: Include "elf-bfd.h". + (process_note_abi_tag_sections): New function. + (i386_gdbarch_init): Add code to recognize various OS/ABI + combinations. + + * maint.c (_initialize_maint_cmds): Add missing \ in + string-literal. + +For older changes see ChangeLog-2001 + +Local Variables: +mode: change-log +left-margin: 8 +fill-column: 74 +version-control: never +End: diff --git a/gdb/alpha-mdebug-tdep.c b/gdb/alpha-mdebug-tdep.c new file mode 100644 index 0000000..153ed11 --- /dev/null +++ b/gdb/alpha-mdebug-tdep.c @@ -0,0 +1,386 @@ +/* Target-dependent mdebug code for the ALPHA architecture. + Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 + Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#include "defs.h" +#include "frame.h" +#include "frame-unwind.h" +#include "frame-base.h" +#include "symtab.h" +#include "gdbcore.h" +#include "block.h" +#include "gdb_assert.h" + +#include "alpha-tdep.h" + +/* FIXME: Some of this code should perhaps be merged with mips. */ + +/* *INDENT-OFF* */ +/* Layout of a stack frame on the alpha: + + | | + pdr members: | 7th ... nth arg, | + | `pushed' by caller. | + | | +----------------|-------------------------------|<-- old_sp == vfp + ^ ^ ^ ^ | | + | | | | | | + | |localoff | Copies of 1st .. 6th | + | | | | | argument if necessary. | + | | | v | | + | | | --- |-------------------------------|<-- LOCALS_ADDRESS + | | | | | + | | | | Locals and temporaries. | + | | | | | + | | | |-------------------------------| + | | | | | + |-fregoffset | Saved float registers. | + | | | | F9 | + | | | | . | + | | | | . | + | | | | F2 | + | | v | | + | | -------|-------------------------------| + | | | | + | | | Saved registers. | + | | | S6 | + |-regoffset | . | + | | | . | + | | | S0 | + | | | pdr.pcreg | + | v | | + | ----------|-------------------------------| + | | | + frameoffset | Argument build area, gets | + | | 7th ... nth arg for any | + | | called procedure. | + v | | + -------------|-------------------------------|<-- sp + | | +*/ +/* *INDENT-ON* */ + +#define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) +#define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset) +#define PROC_FRAME_REG(proc) ((proc)->pdr.framereg) +#define PROC_REG_MASK(proc) ((proc)->pdr.regmask) +#define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask) +#define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset) +#define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset) +#define PROC_PC_REG(proc) ((proc)->pdr.pcreg) +#define PROC_LOCALOFF(proc) ((proc)->pdr.localoff) + +/* Locate the mdebug PDR for the given PC. Return null if one can't + be found; you'll have to fall back to other methods in that case. */ + +static alpha_extra_func_info_t +find_proc_desc (CORE_ADDR pc) +{ + struct block *b = block_for_pc (pc); + alpha_extra_func_info_t proc_desc = NULL; + struct symbol *sym = NULL; + + if (b) + { + CORE_ADDR startaddr; + find_pc_partial_function (pc, NULL, &startaddr, NULL); + + if (startaddr > BLOCK_START (b)) + /* This is the "pathological" case referred to in a comment in + print_frame_info. It might be better to move this check into + symbol reading. */ + sym = NULL; + else + sym = lookup_symbol (MIPS_EFI_SYMBOL_NAME, b, LABEL_DOMAIN, 0, NULL); + } + + if (sym) + { + proc_desc = (alpha_extra_func_info_t) SYMBOL_VALUE (sym); + + /* If we never found a PDR for this function in symbol reading, + then examine prologues to find the information. */ + if (proc_desc->pdr.framereg == -1) + proc_desc = NULL; + } + + return proc_desc; +} + +/* This returns the PC of the first inst after the prologue. If we can't + find the prologue, then return 0. */ + +static CORE_ADDR +alpha_mdebug_after_prologue (CORE_ADDR pc, alpha_extra_func_info_t proc_desc) +{ + if (proc_desc) + { + /* If function is frameless, then we need to do it the hard way. I + strongly suspect that frameless always means prologueless... */ + if (PROC_FRAME_REG (proc_desc) == ALPHA_SP_REGNUM + && PROC_FRAME_OFFSET (proc_desc) == 0) + return 0; + } + + return alpha_after_prologue (pc); +} + +/* Return non-zero if we *might* be in a function prologue. Return zero + if we are definitively *not* in a function prologue. */ + +static int +alpha_mdebug_in_prologue (CORE_ADDR pc, alpha_extra_func_info_t proc_desc) +{ + CORE_ADDR after_prologue_pc = alpha_mdebug_after_prologue (pc, proc_desc); + return (after_prologue_pc == 0 || pc < after_prologue_pc); +} + + +/* Frame unwinder that reads mdebug PDRs. */ + +struct alpha_mdebug_unwind_cache +{ + alpha_extra_func_info_t proc_desc; + CORE_ADDR vfp; + CORE_ADDR *saved_regs; +}; + +/* Extract all of the information about the frame from PROC_DESC + and store the resulting register save locations in the structure. */ + +static struct alpha_mdebug_unwind_cache * +alpha_mdebug_frame_unwind_cache (struct frame_info *next_frame, + void **this_prologue_cache) +{ + struct alpha_mdebug_unwind_cache *info; + alpha_extra_func_info_t proc_desc; + ULONGEST vfp; + CORE_ADDR pc, reg_position; + unsigned long mask; + int ireg, returnreg; + + if (*this_prologue_cache) + return *this_prologue_cache; + + info = FRAME_OBSTACK_ZALLOC (struct alpha_mdebug_unwind_cache); + *this_prologue_cache = info; + pc = frame_pc_unwind (next_frame); + + /* ??? We don't seem to be able to cache the lookup of the PDR + from alpha_mdebug_frame_p. It'd be nice if we could change + the arguments to that function. Oh well. */ + proc_desc = find_proc_desc (pc); + info->proc_desc = proc_desc; + gdb_assert (proc_desc != NULL); + + info->saved_regs = frame_obstack_zalloc (SIZEOF_FRAME_SAVED_REGS); + + /* The VFP of the frame is at FRAME_REG+FRAME_OFFSET. */ + frame_unwind_unsigned_register (next_frame, PROC_FRAME_REG (proc_desc), &vfp); + vfp += PROC_FRAME_OFFSET (info->proc_desc); + info->vfp = vfp; + + /* Fill in the offsets for the registers which gen_mask says were saved. */ + + reg_position = vfp + PROC_REG_OFFSET (proc_desc); + mask = PROC_REG_MASK (proc_desc); + returnreg = PROC_PC_REG (proc_desc); + + /* Note that RA is always saved first, regardless of its actual + register number. */ + if (mask & (1 << returnreg)) + { + /* Clear bit for RA so we don't save it again later. */ + mask &= ~(1 << returnreg); + + info->saved_regs[returnreg] = reg_position; + reg_position += 8; + } + + for (ireg = 0; ireg <= 31; ++ireg) + if (mask & (1 << ireg)) + { + info->saved_regs[ireg] = reg_position; + reg_position += 8; + } + + reg_position = vfp + PROC_FREG_OFFSET (proc_desc); + mask = PROC_FREG_MASK (proc_desc); + + for (ireg = 0; ireg <= 31; ++ireg) + if (mask & (1 << ireg)) + { + info->saved_regs[ALPHA_FP0_REGNUM + ireg] = reg_position; + reg_position += 8; + } + + return info; +} + +/* Given a GDB frame, determine the address of the calling function's + frame. This will be used to create a new GDB frame struct. */ + +static void +alpha_mdebug_frame_this_id (struct frame_info *next_frame, + void **this_prologue_cache, + struct frame_id *this_id) +{ + struct alpha_mdebug_unwind_cache *info + = alpha_mdebug_frame_unwind_cache (next_frame, this_prologue_cache); + + *this_id = frame_id_build (info->vfp, frame_func_unwind (next_frame)); +} + +/* Retrieve the value of REGNUM in FRAME. Don't give up! */ + +static void +alpha_mdebug_frame_prev_register (struct frame_info *next_frame, + void **this_prologue_cache, + int regnum, int *optimizedp, + enum lval_type *lvalp, CORE_ADDR *addrp, + int *realnump, void *bufferp) +{ + struct alpha_mdebug_unwind_cache *info + = alpha_mdebug_frame_unwind_cache (next_frame, this_prologue_cache); + + /* The PC of the previous frame is stored in the link register of + the current frame. Frob regnum so that we pull the value from + the correct place. */ + if (regnum == ALPHA_PC_REGNUM) + regnum = PROC_PC_REG (info->proc_desc); + + /* For all registers known to be saved in the current frame, + do the obvious and pull the value out. */ + if (info->saved_regs[regnum]) + { + *optimizedp = 0; + *lvalp = lval_memory; + *addrp = info->saved_regs[regnum]; + *realnump = -1; + if (bufferp != NULL) + get_frame_memory (next_frame, *addrp, bufferp, ALPHA_REGISTER_SIZE); + return; + } + + /* The stack pointer of the previous frame is computed by popping + the current stack frame. */ + if (regnum == ALPHA_SP_REGNUM) + { + *optimizedp = 0; + *lvalp = not_lval; + *addrp = 0; + *realnump = -1; + if (bufferp != NULL) + store_unsigned_integer (bufferp, ALPHA_REGISTER_SIZE, info->vfp); + return; + } + + /* Otherwise assume the next frame has the same register value. */ + frame_register (next_frame, regnum, optimizedp, lvalp, addrp, + realnump, bufferp); +} + +static const struct frame_unwind alpha_mdebug_frame_unwind = { + NORMAL_FRAME, + alpha_mdebug_frame_this_id, + alpha_mdebug_frame_prev_register +}; + +const struct frame_unwind * +alpha_mdebug_frame_sniffer (struct frame_info *next_frame) +{ + CORE_ADDR pc = frame_pc_unwind (next_frame); + alpha_extra_func_info_t proc_desc; + + /* If this PC does not map to a PDR, then clearly this isn't an + mdebug frame. */ + proc_desc = find_proc_desc (pc); + if (proc_desc == NULL) + return NULL; + + /* If we're in the prologue, the PDR for this frame is not yet valid. + Say no here and we'll fall back on the heuristic unwinder. */ + if (alpha_mdebug_in_prologue (pc, proc_desc)) + return NULL; + + return &alpha_mdebug_frame_unwind; +} + +static CORE_ADDR +alpha_mdebug_frame_base_address (struct frame_info *next_frame, + void **this_prologue_cache) +{ + struct alpha_mdebug_unwind_cache *info + = alpha_mdebug_frame_unwind_cache (next_frame, this_prologue_cache); + + return info->vfp; +} + +static CORE_ADDR +alpha_mdebug_frame_locals_address (struct frame_info *next_frame, + void **this_prologue_cache) +{ + struct alpha_mdebug_unwind_cache *info + = alpha_mdebug_frame_unwind_cache (next_frame, this_prologue_cache); + + return info->vfp - PROC_LOCALOFF (info->proc_desc); +} + +static CORE_ADDR +alpha_mdebug_frame_args_address (struct frame_info *next_frame, + void **this_prologue_cache) +{ + struct alpha_mdebug_unwind_cache *info + = alpha_mdebug_frame_unwind_cache (next_frame, this_prologue_cache); + + return info->vfp - ALPHA_NUM_ARG_REGS * 8; +} + +static const struct frame_base alpha_mdebug_frame_base = { + &alpha_mdebug_frame_unwind, + alpha_mdebug_frame_base_address, + alpha_mdebug_frame_locals_address, + alpha_mdebug_frame_args_address +}; + +static const struct frame_base * +alpha_mdebug_frame_base_sniffer (struct frame_info *next_frame) +{ + CORE_ADDR pc = frame_pc_unwind (next_frame); + alpha_extra_func_info_t proc_desc; + + /* If this PC does not map to a PDR, then clearly this isn't an + mdebug frame. */ + proc_desc = find_proc_desc (pc); + if (proc_desc == NULL) + return NULL; + + return &alpha_mdebug_frame_base; +} + + +void +alpha_mdebug_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) +{ + struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + + frame_unwind_append_sniffer (gdbarch, alpha_mdebug_frame_sniffer); + frame_base_append_sniffer (gdbarch, alpha_mdebug_frame_base_sniffer); +} diff --git a/gdb/amd64-nat.c b/gdb/amd64-nat.c new file mode 100644 index 0000000..fb0efcf --- /dev/null +++ b/gdb/amd64-nat.c @@ -0,0 +1,144 @@ +/* Native-dependent code for AMD64. + + Copyright 2003 Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#include "defs.h" +#include "gdbarch.h" +#include "regcache.h" + +#include "gdb_assert.h" + +#include "i386-tdep.h" +#include "x86-64-tdep.h" + +/* The following bits of code help with implementing debugging 32-bit + code natively on AMD64. The idea is to define two mappings between + the register number as used by GDB and the register set used by the + host to represent the general-purpose registers; one for 32-bit + code and one for 64-bit code. The mappings are specified by the + follwing variables and consist of an array of offsets within the + register set indexed by register number, and the number of + registers supported by the mapping. We don't need mappings for the + floating-point and SSE registers, since the difference between + 64-bit and 32-bit variants are negligable. The difference in the + number of SSE registers is already handled by the target code. */ + +/* General-purpose register mapping for native 32-bit code. */ +int *amd64_native_gregset32_reg_offset; +int amd64_native_gregset32_num_regs = I386_NUM_GREGS; + +/* General-purpose register mapping for native 64-bit code. */ +int *amd64_native_gregset64_reg_offset; +int amd64_native_gregset64_num_regs = X86_64_NUM_GREGS; + +/* Return the offset of REGNUM within the appropriate native + general-purpose register set. */ + +static int +amd64_native_gregset_reg_offset (int regnum) +{ + int *reg_offset = amd64_native_gregset64_reg_offset; + int num_regs = amd64_native_gregset64_num_regs; + + gdb_assert (regnum >= 0); + + if (gdbarch_ptr_bit (current_gdbarch) == 32) + { + reg_offset = amd64_native_gregset32_reg_offset; + num_regs = amd64_native_gregset32_num_regs; + } + + if (num_regs > NUM_REGS) + num_regs = NUM_REGS; + + if (regnum < num_regs && regnum < NUM_REGS) + return reg_offset[regnum]; + + return -1; +} + +/* Return whether the native general-purpose register set supplies + register REGNUM. */ + +int +amd64_native_gregset_supplies_p (int regnum) +{ + return (amd64_native_gregset_reg_offset (regnum) != -1); +} + + +/* Supply register REGNUM, whose contents are store in BUF, to + REGCACHE. If REGNUM is -1, supply all appropriate registers. */ + +void +amd64_supply_native_gregset (struct regcache *regcache, + const void *gregs, int regnum) +{ + const char *regs = gregs; + int num_regs = amd64_native_gregset64_num_regs; + int i; + + if (gdbarch_ptr_bit (current_gdbarch) == 32) + num_regs = amd64_native_gregset32_num_regs; + + if (num_regs > NUM_REGS) + num_regs = NUM_REGS; + + for (i = 0; i < num_regs; i++) + { + if (regnum == -1 || regnum == i) + { + int offset = amd64_native_gregset_reg_offset (i); + + if (offset != -1) + regcache_raw_supply (current_regcache, i, regs + offset); + } + } +} + +/* Collect register REGNUM from REGCACHE and store its contents in + GREGS. If REGNUM is -1, collect and store all appropriate + registers. */ + +void +amd64_collect_native_gregset (const struct regcache *regcache, + void *gregs, int regnum) +{ + char *regs = gregs; + int num_regs = amd64_native_gregset64_num_regs; + int i; + + if (gdbarch_ptr_bit (current_gdbarch) == 32) + num_regs = amd64_native_gregset32_num_regs; + + if (num_regs > NUM_REGS) + num_regs = NUM_REGS; + + for (i = 0; i < num_regs; i++) + { + if (regnum == -1 || regnum == i) + { + int offset = amd64_native_gregset_reg_offset (i); + + if (offset != -1) + regcache_raw_collect (current_regcache, i, regs + offset); + } + } +} diff --git a/gdb/amd64-nat.h b/gdb/amd64-nat.h new file mode 100644 index 0000000..edf6df8 --- /dev/null +++ b/gdb/amd64-nat.h @@ -0,0 +1,53 @@ +/* Native-dependent code for AMD64. + + Copyright 2003 Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#ifndef AMD64_NAT_H +#define AMD64_NAT_H 1 + +struct regcache; + +/* General-purpose register set description for native 32-bit code. */ +extern int *amd64_native_gregset32_reg_offset; +extern int amd64_native_gregset32_num_regs; + +/* General-purpose register set description for native 64-bit code. */ +extern int *amd64_native_gregset64_reg_offset; +extern int amd64_native_gregset64_num_regs; + +/* Return whether the native general-purpose register set supplies + register REGNUM. */ + +extern int amd64_native_gregset_supplies_p (int regnum); + +/* Supply register REGNUM, whose contents are store in BUF, to + REGCACHE. If REGNUM is -1, supply all appropriate registers. */ + +extern void amd64_supply_native_gregset (struct regcache *regcache, + const void *gregs, int regnum); + +/* Collect register REGNUM from REGCACHE and store its contents in + GREGS. If REGNUM is -1, collect and store all appropriate + registers. */ + +extern void amd64_collect_native_gregset (const struct regcache *regcache, + void *gregs, int regnum); + +#endif /* amd64-nat.h */ diff --git a/gdb/amd64bsd-nat.c b/gdb/amd64bsd-nat.c new file mode 100644 index 0000000..6c85f20 --- /dev/null +++ b/gdb/amd64bsd-nat.c @@ -0,0 +1,107 @@ +/* Native-dependent code for AMD64 BSD's. + + Copyright 2003 Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#include "defs.h" +#include "inferior.h" +#include "regcache.h" + +/* We include to make sure `struct fxsave64' is defined on + NetBSD, since NetBSD's needs it. */ +#include "gdb_assert.h" +#include +#include +#include +#include + +#include "x86-64-tdep.h" +#include "amd64-nat.h" + + +/* Fetch register REGNUM from the inferior. If REGNUM is -1, do this + for all registers (including the floating-point registers). */ + +void +fetch_inferior_registers (int regnum) +{ + if (regnum == -1 || amd64_native_gregset_supplies_p (regnum)) + { + struct reg regs; + + if (ptrace (PT_GETREGS, PIDGET (inferior_ptid), + (PTRACE_ARG3_TYPE) ®s, 0) == -1) + perror_with_name ("Couldn't get registers"); + + amd64_supply_native_gregset (current_regcache, ®s, -1); + if (regnum != -1) + return; + } + + if (regnum == -1 || regnum >= X86_64_ST0_REGNUM) + { + struct fpreg fpregs; + + if (ptrace (PT_GETFPREGS, PIDGET (inferior_ptid), + (PTRACE_ARG3_TYPE) &fpregs, 0) == -1) + perror_with_name ("Couldn't get floating point status"); + + x86_64_supply_fxsave (current_regcache, -1, &fpregs); + } +} + +/* Store register REGNUM back into the inferior. If REGNUM is -1, do + this for all registers (including the floating-point registers). */ + +void +store_inferior_registers (int regnum) +{ + if (regnum == -1 || amd64_native_gregset_supplies_p (regnum)) + { + struct reg regs; + + if (ptrace (PT_GETREGS, PIDGET (inferior_ptid), + (PTRACE_ARG3_TYPE) ®s, 0) == -1) + perror_with_name ("Couldn't get registers"); + + amd64_collect_native_gregset (current_regcache, ®s, regnum); + + if (ptrace (PT_SETREGS, PIDGET (inferior_ptid), + (PTRACE_ARG3_TYPE) ®s, 0) == -1) + perror_with_name ("Couldn't write registers"); + + if (regnum != -1) + return; + } + + if (regnum == -1 || regnum >= X86_64_ST0_REGNUM) + { + struct fpreg fpregs; + + if (ptrace (PT_GETFPREGS, PIDGET (inferior_ptid), + (PTRACE_ARG3_TYPE) &fpregs, 0) == -1) + perror_with_name ("Couldn't get floating point status"); + + x86_64_fill_fxsave ((char *) &fpregs, regnum); + + if (ptrace (PT_SETFPREGS, PIDGET (inferior_ptid), + (PTRACE_ARG3_TYPE) &fpregs, 0) == -1) + perror_with_name ("Couldn't write floating point status"); + } +} diff --git a/gdb/amd64fbsd-nat.c b/gdb/amd64fbsd-nat.c new file mode 100644 index 0000000..2354fa3 --- /dev/null +++ b/gdb/amd64fbsd-nat.c @@ -0,0 +1,233 @@ +/* Native-dependent code for FreeBSD/amd64. + + Copyright 2003 Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#include "defs.h" +#include "inferior.h" +#include "regcache.h" + +#include "gdb_assert.h" +#include +#include +#include +#include +#include +#include + +#ifdef HAVE_SYS_PROCFS_H +#include +#endif + +#ifndef HAVE_GREGSET_T +typedef struct reg gregset_t; +#endif + +#ifndef HAVE_FPREGSET_T +typedef struct fpreg fpregset_t; +#endif + +#include "gregset.h" +#include "x86-64-tdep.h" +#include "amd64-nat.h" + + +/* Offset to the gregset_t location where REG is stored. */ +#define REG_OFFSET(reg) offsetof (gregset_t, reg) + +/* At reg_offset[REGNUM] you'll find the offset to the gregset_t + location where the GDB register REGNUM is stored. Unsupported + registers are marked with `-1'. */ +static int reg_offset[] = +{ + REG_OFFSET (r_rax), + REG_OFFSET (r_rbx), + REG_OFFSET (r_rcx), + REG_OFFSET (r_rdx), + REG_OFFSET (r_rsi), + REG_OFFSET (r_rdi), + REG_OFFSET (r_rbp), + REG_OFFSET (r_rsp), + REG_OFFSET (r_r8), + REG_OFFSET (r_r9), + REG_OFFSET (r_r10), + REG_OFFSET (r_r11), + REG_OFFSET (r_r12), + REG_OFFSET (r_r13), + REG_OFFSET (r_r14), + REG_OFFSET (r_r15), + REG_OFFSET (r_rip), + REG_OFFSET (r_rflags), + -1, + -1, + -1, + -1 +}; + + +/* Mapping between the general-purpose registers in FreeBSD/amd64 + `struct reg' format and GDB's register cache layout for + FreeBSD/i386. + + Note that most FreeBSD/amd64 registers are 64-bit, while the + FreeBSD/i386 registers are all 32-bit, but since we're + little-endian we get away with that. */ + +/* From . */ +static int amd64fbsd32_r_reg_offset[I386_NUM_GREGS] = +{ + 14 * 8, 13 * 8, /* %eax, %ecx */ + 12 * 8, 11 * 8, /* %edx, %ebx */ + 20 * 8, 10 * 8, /* %esp, %ebp */ + 9 * 8, 8 * 8, /* %esi, %edi */ + 17 * 8, 19 * 8, /* %eip, %eflags */ + 18 * 8, 21 * 8, /* %cs, %ss */ + -1, -1, -1, -1 /* %ds, %es, %fs, %gs */ +}; + + +/* Transfering the registers between GDB, inferiors and core files. */ + +/* Fill GDB's register array with the general-purpose register values + in *GREGSETP. */ + +void +supply_gregset (gregset_t *gregsetp) +{ + amd64_supply_native_gregset (current_regcache, gregsetp, -1); +} + +/* Fill register REGNUM (if it is a general-purpose register) in + *GREGSETPS with the value in GDB's register array. If REGNUM is -1, + do this for all registers. */ + +void +fill_gregset (gregset_t *gregsetp, int regnum) +{ + amd64_collect_native_gregset (current_regcache, gregsetp, regnum); +} + +/* Fill GDB's register array with the floating-point register values + in *FPREGSETP. */ + +void +supply_fpregset (fpregset_t *fpregsetp) +{ + x86_64_supply_fxsave (current_regcache, -1, fpregsetp); +} + +/* Fill register REGNUM (if it is a floating-point register) in + *FPREGSETP with the value in GDB's register array. If REGNUM is -1, + do this for all registers. */ + +void +fill_fpregset (fpregset_t *fpregsetp, int regnum) +{ + x86_64_fill_fxsave ((char *) fpregsetp, regnum); +} + + +/* Provide a prototype to silence -Wmissing-prototypes. */ +void _initialize_amd64fbsd_nat (void); + +void +_initialize_amd64fbsd_nat (void) +{ + int offset; + + amd64_native_gregset32_reg_offset = amd64fbsd32_r_reg_offset; + amd64_native_gregset64_reg_offset = reg_offset; + + /* To support the recognition of signal handlers, i386bsd-tdep.c + hardcodes some constants. Inclusion of this file means that we + are compiling a native debugger, which means that we can use the + system header files and sysctl(3) to get at the relevant + information. */ + +#define SC_REG_OFFSET amd64fbsd_sc_reg_offset + + /* We only check the program counter, stack pointer and frame + pointer since these members of `struct sigcontext' are essential + for providing backtraces. */ + +#define SC_RIP_OFFSET SC_REG_OFFSET[X86_64_RIP_REGNUM] +#define SC_RSP_OFFSET SC_REG_OFFSET[X86_64_RSP_REGNUM] +#define SC_RBP_OFFSET SC_REG_OFFSET[X86_64_RBP_REGNUM] + + /* Override the default value for the offset of the program counter + in the sigcontext structure. */ + offset = offsetof (struct sigcontext, sc_rip); + + if (SC_RIP_OFFSET != offset) + { + warning ("\ +offsetof (struct sigcontext, sc_rip) yields %d instead of %d.\n\ +Please report this to .", + offset, SC_RIP_OFFSET); + } + + SC_RIP_OFFSET = offset; + + /* Likewise for the stack pointer. */ + offset = offsetof (struct sigcontext, sc_rsp); + + if (SC_RSP_OFFSET != offset) + { + warning ("\ +offsetof (struct sigcontext, sc_rsp) yields %d instead of %d.\n\ +Please report this to .", + offset, SC_RSP_OFFSET); + } + + SC_RSP_OFFSET = offset; + + /* And the frame pointer. */ + offset = offsetof (struct sigcontext, sc_rbp); + + if (SC_RBP_OFFSET != offset) + { + warning ("\ +offsetof (struct sigcontext, sc_rbp) yields %d instead of %d.\n\ +Please report this to .", + offset, SC_RBP_OFFSET); + } + + SC_RBP_OFFSET = offset; + + /* FreeBSD provides a kern.ps_strings sysctl that we can use to + locate the sigtramp. That way we can still recognize a sigtramp + if its location is changed in a new kernel. Of course this is + still based on the assumption that the sigtramp is placed + directly under the location where the program arguments and + environment can be found. */ + { + int mib[2]; + long ps_strings; + size_t len; + + mib[0] = CTL_KERN; + mib[1] = KERN_PS_STRINGS; + len = sizeof (ps_strings); + if (sysctl (mib, 2, &ps_strings, &len, NULL, 0) == 0) + { + amd64fbsd_sigtramp_start = ps_strings - 32; + amd64fbsd_sigtramp_end = ps_strings; + } + } +} diff --git a/gdb/amd64fbsd-tdep.c b/gdb/amd64fbsd-tdep.c new file mode 100644 index 0000000..bb44ec0 --- /dev/null +++ b/gdb/amd64fbsd-tdep.c @@ -0,0 +1,133 @@ +/* Target-dependent code for FreeBSD/amd64. + + Copyright 2003 Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#include "defs.h" +#include "arch-utils.h" +#include "frame.h" +#include "gdbcore.h" +#include "regcache.h" +#include "osabi.h" + +#include "gdb_string.h" + +#include "x86-64-tdep.h" + +/* Support for signal handlers. */ + +/* Assuming NEXT_FRAME is for a frame following a BSD sigtramp + routine, return the address of the associated sigcontext structure. */ + +static CORE_ADDR +amd64fbsd_sigcontext_addr (struct frame_info *next_frame) +{ + CORE_ADDR sp; + + /* The `struct sigcontext' (which really is an `ucontext_t' on + FreeBSD/amd64) lives at a fixed offset in the signal frame. See + . */ + sp = frame_unwind_register_unsigned (next_frame, X86_64_RSP_REGNUM); + return sp + 16; +} + +/* FreeBSD 5.1-RELEASE or later. */ + +/* Mapping between the general-purpose registers in `struct reg' + format and GDB's register cache layout. + + Note that some registers are 32-bit, but since we're little-endian + we get away with that. */ + +/* From . */ +static int amd64fbsd_r_reg_offset[] = +{ + 14 * 8, 11 * 8, /* %rax, %rbx */ + 13 * 8, 12 * 8, /* %rcx, %rdx */ + 9 * 8, 8 * 8, /* %rsi, %rdi */ + 10 * 8, 20 * 8, /* %rbp, %rsp */ + 7 * 8, 6 * 8, 5 * 8, 4 * 8, /* %r8 ... */ + 3 * 8, 2 * 8, 1 * 8, 0 * 8, /* ... %r15 */ + 17 * 8, 19 * 8, /* %rip, %eflags */ + -1, -1, /* %ds, %es */ + -1, -1 /* %fs, %gs */ +}; + +/* Location of the signal trampoline. */ +CORE_ADDR amd64fbsd_sigtramp_start = 0x7fffffffffc0; +CORE_ADDR amd64fbsd_sigtramp_end = 0x7fffffffffe0; + +/* From . */ +int amd64fbsd_sc_reg_offset[X86_64_NUM_GREGS] = +{ + 24 + 6 * 8, /* %rax */ + 24 + 7 * 8, /* %rbx */ + 24 + 3 * 8, /* %rcx */ + 24 + 2 * 8, /* %rdx */ + 24 + 1 * 8, /* %rsi */ + 24 + 0 * 8, /* %rdi */ + 24 + 8 * 8, /* %rbp */ + 24 + 22 * 8, /* %rsp */ + 24 + 4 * 8, /* %r8 */ + 24 + 5 * 8, /* %r9 */ + 24 + 9 * 8, /* %r10 */ + 24 + 10 * 8, /* %r11 */ + 24 + 11 * 8, /* %r12 */ + 24 + 12 * 8, /* %r13 */ + 24 + 13 * 8, /* %r14 */ + 24 + 14 * 8, /* %r15 */ + 24 + 19 * 8, /* %rip */ + 24 + 21 * 8, /* %eflags */ + -1, /* %ds */ + -1, /* %es */ + -1, /* %fs */ + -1 /* %gs */ +}; + +void +amd64fbsd_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) +{ + struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + + /* Obviously FreeBSD is BSD-based. */ + i386bsd_init_abi (info, gdbarch); + + tdep->gregset_reg_offset = amd64fbsd_r_reg_offset; + tdep->gregset_num_regs = ARRAY_SIZE (amd64fbsd_r_reg_offset); + tdep->sizeof_gregset = 22 * 8; + + x86_64_init_abi (info, gdbarch); + + tdep->sigtramp_start = amd64fbsd_sigtramp_start; + tdep->sigtramp_end = amd64fbsd_sigtramp_end; + tdep->sigcontext_addr = amd64fbsd_sigcontext_addr; + tdep->sc_reg_offset = amd64fbsd_sc_reg_offset; + tdep->sc_num_regs = ARRAY_SIZE (amd64fbsd_sc_reg_offset); +} + + +/* Provide a prototype to silence -Wmissing-prototypes. */ +void _initialize_amd64fbsd_tdep (void); + +void +_initialize_amd64fbsd_tdep (void) +{ + gdbarch_register_osabi (bfd_arch_i386, bfd_mach_x86_64, + GDB_OSABI_FREEBSD_ELF, amd64fbsd_init_abi); +} diff --git a/gdb/amd64nbsd-nat.c b/gdb/amd64nbsd-nat.c new file mode 100644 index 0000000..4af22fe --- /dev/null +++ b/gdb/amd64nbsd-nat.c @@ -0,0 +1,68 @@ +/* Native-dependent code for NetBSD/amd64. + + Copyright 2003 Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#include "defs.h" + +#include "gdb_assert.h" + +#include "x86-64-tdep.h" +#include "amd64-nat.h" + +/* Mapping between the general-purpose registers in NetBSD/amd64 + `struct reg' format and GDB's register cache layout for + NetBSD/i386. + + Note that most (if not all) NetBSD/amd64 registers are 64-bit, + while the NetBSD/i386 registers are all 32-bit, but since we're + little-endian we get away with that. */ + +/* From . */ +static int amd64nbsd32_r_reg_offset[] = +{ + 14 * 8, /* %eax */ + 3 * 8, /* %ecx */ + 2 * 8, /* %edx */ + 13 * 8, /* %ebx */ + 24 * 8, /* %esp */ + 12 * 8, /* %ebp */ + 1 * 8, /* %esi */ + 0 * 8, /* %edi */ + 21 * 8, /* %eip */ + 23 * 8, /* %eflags */ + -1, /* %cs */ + -1, /* %ss */ + 18 * 8, /* %ds */ + 17 * 8, /* %es */ + 16 * 8, /* %fs */ + 15 * 8 /* %gs */ +}; + + +/* Provide a prototype to silence -Wmissing-prototypes. */ +void _initialize_amd64nbsd_nat (void); + +void +_initialize_amd64nbsd_nat (void) +{ + amd64_native_gregset32_reg_offset = amd64nbsd32_r_reg_offset; + amd64_native_gregset32_num_regs = ARRAY_SIZE (amd64nbsd32_r_reg_offset); + amd64_native_gregset64_reg_offset = amd64nbsd_r_reg_offset; +} diff --git a/gdb/amd64nbsd-tdep.c b/gdb/amd64nbsd-tdep.c new file mode 100644 index 0000000..5500ed1 --- /dev/null +++ b/gdb/amd64nbsd-tdep.c @@ -0,0 +1,129 @@ +/* Target-dependent code for NetBSD/amd64. + + Copyright 2003 Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#include "defs.h" +#include "arch-utils.h" +#include "frame.h" +#include "gdbcore.h" +#include "osabi.h" + +#include "gdb_assert.h" + +#include "nbsd-tdep.h" +#include "x86-64-tdep.h" + +/* Support for signal handlers. */ + +/* Assuming NEXT_FRAME is for a frame following a BSD sigtramp + routine, return the address of the associated sigcontext structure. */ + +static CORE_ADDR +amd64nbsd_sigcontext_addr (struct frame_info *next_frame) +{ + CORE_ADDR sp; + + /* The stack pointer points at `struct sigcontext' upon entry of a + signal trampoline. */ + sp = frame_unwind_register_unsigned (next_frame, X86_64_RSP_REGNUM); + return sp; +} + +/* NetBSD 2.0 or later. */ + +/* Mapping between the general-purpose registers in `struct reg' + format and GDB's register cache layout. */ + +/* From . */ +int amd64nbsd_r_reg_offset[] = +{ + 14 * 8, /* %rax */ + 13 * 8, /* %rbx */ + 3 * 8, /* %rcx */ + 2 * 8, /* %rdx */ + 1 * 8, /* %rsi */ + 0 * 8, /* %rdi */ + 12 * 8, /* %rbp */ + 24 * 8, /* %rsp */ + 4 * 8, /* %r8 .. */ + 5 * 8, + 6 * 8, + 7 * 8, + 8 * 8, + 9 * 8, + 10 * 8, + 11 * 8, /* ... %r15 */ + 21 * 8, /* %rip */ + 23 * 8, /* %eflags */ + 18 * 8, /* %ds */ + 17 * 8, /* %es */ + 16 * 8, /* %fs */ + 15 * 8 /* %gs */ +}; + +static void +amd64nbsd_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) +{ + struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + int *sc_reg_offset; + int i; + + /* Initialize general-purpose register set details first. */ + tdep->gregset_reg_offset = amd64nbsd_r_reg_offset; + tdep->gregset_num_regs = ARRAY_SIZE (amd64nbsd_r_reg_offset); + tdep->sizeof_gregset = 26 * 8; + + x86_64_init_abi (info, gdbarch); + + tdep->jb_pc_offset = 7 * 8; + + /* NetBSD has its own convention for signal trampolines. */ + set_gdbarch_pc_in_sigtramp (gdbarch, nbsd_pc_in_sigtramp); + + /* Initialize the array with register offsets in `struct + sigcontext'. This `struct sigcontext' has an sc_mcontext member + at offset 32, and in we have an explicit comment + saying that `struct reg' is the same as mcontext.__gregs. */ + tdep->sc_num_regs = ARRAY_SIZE (amd64nbsd_r_reg_offset); + tdep->sc_reg_offset = XCALLOC (tdep->sc_num_regs, int); + for (i = 0; i < tdep->sc_num_regs; i++) + { + if (amd64nbsd_r_reg_offset[i] < 0) + tdep->sc_reg_offset[i] = -1; + else + tdep->sc_reg_offset[i] = 32 + amd64nbsd_r_reg_offset[i]; + } + + tdep->sigcontext_addr = amd64nbsd_sigcontext_addr; +} + + +/* Provide a prototype to silence -Wmissing-prototypes. */ +void _initialize_amd64nbsd_tdep (void); + +void +_initialize_amd64nbsd_ndep (void) +{ + /* The NetBSD/amd64 native dependent code makes this assumption. */ + gdb_assert (ARRAY_SIZE (amd64nbsd_r_reg_offset) == X86_64_NUM_GREGS); + + gdbarch_register_osabi (bfd_arch_i386, bfd_mach_x86_64, + GDB_OSABI_NETBSD_ELF, amd64nbsd_init_abi); +} diff --git a/gdb/bfd-target.c b/gdb/bfd-target.c new file mode 100644 index 0000000..ee16d85 --- /dev/null +++ b/gdb/bfd-target.c @@ -0,0 +1,131 @@ +/* Very simple "bfd" target, for GDB, the GNU debugger. + + Copyright 2003 Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#include "defs.h" +#include "target.h" +#include "bfd-target.h" +#include "gdb_assert.h" +#include "gdb_string.h" + +/* Locate all mappable sections of a BFD file, filling in a target + section for each. */ + +struct section_closure +{ + struct section_table *end; +}; + +static void +add_to_section_table (struct bfd *abfd, struct bfd_section *asect, + void *closure) +{ + struct section_closure *pp = closure; + flagword aflag; + + /* NOTE: cagney/2003-10-22: Is this pruning useful? */ + aflag = bfd_get_section_flags (abfd, asect); + if (!(aflag & SEC_ALLOC)) + return; + if (bfd_section_size (abfd, asect) == 0) + return; + pp->end->bfd = abfd; + pp->end->the_bfd_section = asect; + pp->end->addr = bfd_section_vma (abfd, asect); + pp->end->endaddr = pp->end->addr + bfd_section_size (abfd, asect); + pp->end++; +} + +void +build_target_sections_from_bfd (struct target_ops *targ, struct bfd *abfd) +{ + unsigned count; + struct section_table *start; + struct section_closure cl; + + count = bfd_count_sections (abfd); + target_resize_to_sections (targ, count); + start = targ->to_sections; + cl.end = targ->to_sections; + bfd_map_over_sections (abfd, add_to_section_table, &cl); + gdb_assert (cl.end - start <= count); +} + +LONGEST +target_bfd_xfer_partial (struct target_ops *ops, + enum target_object object, + const char *annex, void *readbuf, + const void *writebuf, ULONGEST offset, LONGEST len) +{ + switch (object) + { + case TARGET_OBJECT_MEMORY: + { + struct section_table *s = target_section_by_addr (ops, offset); + if (s == NULL) + return -1; + /* If the length extends beyond the section, truncate it. Be + careful to not suffer from overflow (wish S contained a + length). */ + if ((offset - s->addr + len) > (s->endaddr - s->addr)) + len = (s->endaddr - s->addr) - (offset - s->addr); + if (readbuf != NULL + && !bfd_get_section_contents (s->bfd, s->the_bfd_section, + readbuf, offset - s->addr, len)) + return -1; +#if 1 + if (writebuf != NULL) + return -1; +#else + /* FIXME: cagney/2003-10-31: The BFD interface doesn't yet + take a const buffer. */ + if (writebuf != NULL + && !bfd_set_section_contents (s->bfd, s->the_bfd_section, + writebuf, offset - s->addr, len)) + return -1; +#endif + return len; + } + default: + return -1; + } +} + +void +target_bfd_xclose (struct target_ops *t, int quitting) +{ + bfd_close (t->to_data); + xfree (t->to_sections); + xfree (t); +} + +struct target_ops * +target_bfd_reopen (struct bfd *bfd) +{ + struct target_ops *t = XZALLOC (struct target_ops); + t->to_shortname = "bfd"; + t->to_longname = "BFD backed target"; + t->to_doc = "You should never see this"; + t->to_xfer_partial = target_bfd_xfer_partial; + t->to_xclose = target_bfd_xclose; + t->to_data = bfd; + build_target_sections_from_bfd (t, bfd); + return t; +} diff --git a/gdb/bfd-target.h b/gdb/bfd-target.h new file mode 100644 index 0000000..61a51c8 --- /dev/null +++ b/gdb/bfd-target.h @@ -0,0 +1,39 @@ +/* Very simple "bfd" target, for GDB, the GNU debugger. + + Copyright 2003 Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#ifndef BFD_TARGET_H +#define BFD_TARGET_H + +struct bfd; +struct target_ops; + +/* Given an existing BFD, re-open it as a "struct target_ops". On + close, it will also close the corresponding BFD (which is like + freopen and fdopen). */ +struct target_ops *target_bfd_reopen (struct bfd *bfd); + +/* Map over ABFD's sections, creating corresponding entries in the + target's section table. */ + +void build_target_sections_from_bfd (struct target_ops *targ, + struct bfd *abfd); + +#endif diff --git a/gdb/block.c b/gdb/block.c new file mode 100644 index 0000000..28b1181 --- /dev/null +++ b/gdb/block.c @@ -0,0 +1,295 @@ +/* Block-related functions for the GNU debugger, GDB. + + Copyright 2003 Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#include "defs.h" +#include "block.h" +#include "symtab.h" +#include "symfile.h" +#include "gdb_obstack.h" +#include "cp-support.h" + +/* This is used by struct block to store namespace-related info for + C++ files, namely using declarations and the current namespace in + scope. */ + +struct block_namespace_info +{ + const char *scope; + struct using_direct *using; +}; + +static void block_initialize_namespace (struct block *block, + struct obstack *obstack); + +/* Return Nonzero if block a is lexically nested within block b, + or if a and b have the same pc range. + Return zero otherwise. */ + +int +contained_in (const struct block *a, const struct block *b) +{ + if (!a || !b) + return 0; + return BLOCK_START (a) >= BLOCK_START (b) + && BLOCK_END (a) <= BLOCK_END (b); +} + + +/* Return the symbol for the function which contains a specified + lexical block, described by a struct block BL. */ + +struct symbol * +block_function (const struct block *bl) +{ + while (BLOCK_FUNCTION (bl) == 0 && BLOCK_SUPERBLOCK (bl) != 0) + bl = BLOCK_SUPERBLOCK (bl); + + return BLOCK_FUNCTION (bl); +} + +/* Return the blockvector immediately containing the innermost lexical block + containing the specified pc value and section, or 0 if there is none. + PINDEX is a pointer to the index value of the block. If PINDEX + is NULL, we don't pass this information back to the caller. */ + +struct blockvector * +blockvector_for_pc_sect (CORE_ADDR pc, struct bfd_section *section, + int *pindex, struct symtab *symtab) +{ + struct block *b; + int bot, top, half; + struct blockvector *bl; + + if (symtab == 0) /* if no symtab specified by caller */ + { + /* First search all symtabs for one whose file contains our pc */ + symtab = find_pc_sect_symtab (pc, section); + if (symtab == 0) + return 0; + } + + bl = BLOCKVECTOR (symtab); + b = BLOCKVECTOR_BLOCK (bl, 0); + + /* Then search that symtab for the smallest block that wins. */ + /* Use binary search to find the last block that starts before PC. */ + + bot = 0; + top = BLOCKVECTOR_NBLOCKS (bl); + + while (top - bot > 1) + { + half = (top - bot + 1) >> 1; + b = BLOCKVECTOR_BLOCK (bl, bot + half); + if (BLOCK_START (b) <= pc) + bot += half; + else + top = bot + half; + } + + /* Now search backward for a block that ends after PC. */ + + while (bot >= 0) + { + b = BLOCKVECTOR_BLOCK (bl, bot); + if (BLOCK_END (b) > pc) + { + if (pindex) + *pindex = bot; + return bl; + } + bot--; + } + return 0; +} + +/* Return the blockvector immediately containing the innermost lexical block + containing the specified pc value, or 0 if there is none. + Backward compatibility, no section. */ + +struct blockvector * +blockvector_for_pc (CORE_ADDR pc, int *pindex) +{ + return blockvector_for_pc_sect (pc, find_pc_mapped_section (pc), + pindex, NULL); +} + +/* Return the innermost lexical block containing the specified pc value + in the specified section, or 0 if there is none. */ + +struct block * +block_for_pc_sect (CORE_ADDR pc, struct bfd_section *section) +{ + struct blockvector *bl; + int index; + + bl = blockvector_for_pc_sect (pc, section, &index, NULL); + if (bl) + return BLOCKVECTOR_BLOCK (bl, index); + return 0; +} + +/* Return the innermost lexical block containing the specified pc value, + or 0 if there is none. Backward compatibility, no section. */ + +struct block * +block_for_pc (CORE_ADDR pc) +{ + return block_for_pc_sect (pc, find_pc_mapped_section (pc)); +} + +/* Now come some functions designed to deal with C++ namespace issues. + The accessors are safe to use even in the non-C++ case. */ + +/* This returns the namespace that BLOCK is enclosed in, or "" if it + isn't enclosed in a namespace at all. This travels the chain of + superblocks looking for a scope, if necessary. */ + +const char * +block_scope (const struct block *block) +{ + for (; block != NULL; block = BLOCK_SUPERBLOCK (block)) + { + if (BLOCK_NAMESPACE (block) != NULL + && BLOCK_NAMESPACE (block)->scope != NULL) + return BLOCK_NAMESPACE (block)->scope; + } + + return ""; +} + +/* Set BLOCK's scope member to SCOPE; if needed, allocate memory via + OBSTACK. (It won't make a copy of SCOPE, however, so that already + has to be allocated correctly.) */ + +void +block_set_scope (struct block *block, const char *scope, + struct obstack *obstack) +{ + block_initialize_namespace (block, obstack); + + BLOCK_NAMESPACE (block)->scope = scope; +} + +/* This returns the first using directives associated to BLOCK, if + any. */ + +/* FIXME: carlton/2003-04-23: This uses the fact that we currently + only have using directives in static blocks, because we only + generate using directives from anonymous namespaces. Eventually, + when we support using directives everywhere, we'll want to replace + this by some iterator functions. */ + +struct using_direct * +block_using (const struct block *block) +{ + const struct block *static_block = block_static_block (block); + + if (static_block == NULL + || BLOCK_NAMESPACE (static_block) == NULL) + return NULL; + else + return BLOCK_NAMESPACE (static_block)->using; +} + +/* Set BLOCK's using member to USING; if needed, allocate memory via + OBSTACK. (It won't make a copy of USING, however, so that already + has to be allocated correctly.) */ + +void +block_set_using (struct block *block, + struct using_direct *using, + struct obstack *obstack) +{ + block_initialize_namespace (block, obstack); + + BLOCK_NAMESPACE (block)->using = using; +} + +/* If BLOCK_NAMESPACE (block) is NULL, allocate it via OBSTACK and + ititialize its members to zero. */ + +static void +block_initialize_namespace (struct block *block, struct obstack *obstack) +{ + if (BLOCK_NAMESPACE (block) == NULL) + { + BLOCK_NAMESPACE (block) + = obstack_alloc (obstack, sizeof (struct block_namespace_info)); + BLOCK_NAMESPACE (block)->scope = NULL; + BLOCK_NAMESPACE (block)->using = NULL; + } +} + +/* Return the static block associated to BLOCK. Return NULL if block + is NULL or if block is a global block. */ + +const struct block * +block_static_block (const struct block *block) +{ + if (block == NULL || BLOCK_SUPERBLOCK (block) == NULL) + return NULL; + + while (BLOCK_SUPERBLOCK (BLOCK_SUPERBLOCK (block)) != NULL) + block = BLOCK_SUPERBLOCK (block); + + return block; +} + +/* Return the static block associated to BLOCK. Return NULL if block + is NULL. */ + +const struct block * +block_global_block (const struct block *block) +{ + if (block == NULL) + return NULL; + + while (BLOCK_SUPERBLOCK (block) != NULL) + block = BLOCK_SUPERBLOCK (block); + + return block; +} + +/* Allocate a block on OBSTACK, and initialize its elements to + zero/NULL. This is useful for creating "dummy" blocks that don't + correspond to actual source files. + + Warning: it sets the block's BLOCK_DICT to NULL, which isn't a + valid value. If you really don't want the block to have a + dictionary, then you should subsequently set its BLOCK_DICT to + dict_create_linear (obstack, NULL). */ + +struct block * +allocate_block (struct obstack *obstack) +{ + struct block *bl = obstack_alloc (obstack, sizeof (struct block)); + + BLOCK_START (bl) = 0; + BLOCK_END (bl) = 0; + BLOCK_FUNCTION (bl) = NULL; + BLOCK_SUPERBLOCK (bl) = NULL; + BLOCK_DICT (bl) = NULL; + BLOCK_NAMESPACE (bl) = NULL; + BLOCK_GCC_COMPILED (bl) = 0; + + return bl; +} diff --git a/gdb/block.h b/gdb/block.h new file mode 100644 index 0000000..38d037e --- /dev/null +++ b/gdb/block.h @@ -0,0 +1,176 @@ +/* Code dealing with blocks for GDB. + + Copyright 2003 Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#ifndef BLOCK_H +#define BLOCK_H + +/* Opaque declarations. */ + +struct symbol; +struct symtab; +struct block_namespace_info; +struct using_direct; +struct obstack; +struct dictionary; + +/* All of the name-scope contours of the program + are represented by `struct block' objects. + All of these objects are pointed to by the blockvector. + + Each block represents one name scope. + Each lexical context has its own block. + + The blockvector begins with some special blocks. + The GLOBAL_BLOCK contains all the symbols defined in this compilation + whose scope is the entire program linked together. + The STATIC_BLOCK contains all the symbols whose scope is the + entire compilation excluding other separate compilations. + Blocks starting with the FIRST_LOCAL_BLOCK are not special. + + Each block records a range of core addresses for the code that + is in the scope of the block. The STATIC_BLOCK and GLOBAL_BLOCK + give, for the range of code, the entire range of code produced + by the compilation that the symbol segment belongs to. + + The blocks appear in the blockvector + in order of increasing starting-address, + and, within that, in order of decreasing ending-address. + + This implies that within the body of one function + the blocks appear in the order of a depth-first tree walk. */ + +struct block +{ + + /* Addresses in the executable code that are in this block. */ + + CORE_ADDR startaddr; + CORE_ADDR endaddr; + + /* The symbol that names this block, if the block is the body of a + function; otherwise, zero. */ + + struct symbol *function; + + /* The `struct block' for the containing block, or 0 if none. + + The superblock of a top-level local block (i.e. a function in the + case of C) is the STATIC_BLOCK. The superblock of the + STATIC_BLOCK is the GLOBAL_BLOCK. */ + + struct block *superblock; + + /* This is used to store the symbols in the block. */ + + struct dictionary *dict; + + /* Used for language-specific info. */ + + union + { + struct + { + /* Contains information about namespace-related info relevant to + this block: using directives and the current namespace + scope. */ + + struct block_namespace_info *namespace; + } + cplus_specific; + } + language_specific; + + /* Version of GCC used to compile the function corresponding + to this block, or 0 if not compiled with GCC. When possible, + GCC should be compatible with the native compiler, or if that + is not feasible, the differences should be fixed during symbol + reading. As of 16 Apr 93, this flag is never used to distinguish + between gcc2 and the native compiler. + + If there is no function corresponding to this block, this meaning + of this flag is undefined. */ + + unsigned char gcc_compile_flag; +}; + +#define BLOCK_START(bl) (bl)->startaddr +#define BLOCK_END(bl) (bl)->endaddr +#define BLOCK_FUNCTION(bl) (bl)->function +#define BLOCK_SUPERBLOCK(bl) (bl)->superblock +#define BLOCK_GCC_COMPILED(bl) (bl)->gcc_compile_flag +#define BLOCK_DICT(bl) (bl)->dict +#define BLOCK_NAMESPACE(bl) (bl)->language_specific.cplus_specific.namespace + +/* Macro to loop through all symbols in a block BL, in no particular + order. ITER helps keep track of the iteration, and should be a + struct dict_iterator. SYM points to the current symbol. */ + +#define ALL_BLOCK_SYMBOLS(block, iter, sym) \ + ALL_DICT_SYMBOLS (BLOCK_DICT (block), iter, sym) + +struct blockvector +{ + /* Number of blocks in the list. */ + int nblocks; + /* The blocks themselves. */ + struct block *block[1]; +}; + +#define BLOCKVECTOR_NBLOCKS(blocklist) (blocklist)->nblocks +#define BLOCKVECTOR_BLOCK(blocklist,n) (blocklist)->block[n] + +/* Special block numbers */ + +#define GLOBAL_BLOCK 0 +#define STATIC_BLOCK 1 +#define FIRST_LOCAL_BLOCK 2 + +extern struct symbol *block_function (const struct block *); + +extern int contained_in (const struct block *, const struct block *); + +extern struct blockvector *blockvector_for_pc (CORE_ADDR, int *); + +extern struct blockvector *blockvector_for_pc_sect (CORE_ADDR, asection *, + int *, struct symtab *); + +extern struct block *block_for_pc (CORE_ADDR); + +extern struct block *block_for_pc_sect (CORE_ADDR, asection *); + +extern const char *block_scope (const struct block *block); + +extern void block_set_scope (struct block *block, const char *scope, + struct obstack *obstack); + +extern struct using_direct *block_using (const struct block *block); + +extern void block_set_using (struct block *block, + struct using_direct *using, + struct obstack *obstack); + +extern const struct block *block_static_block (const struct block *block); + +extern const struct block *block_global_block (const struct block *block); + +extern struct block *allocate_block (struct obstack *obstack); + +#endif /* BLOCK_H */ diff --git a/gdb/cli/cli-interp.c b/gdb/cli/cli-interp.c new file mode 100644 index 0000000..6abb24d --- /dev/null +++ b/gdb/cli/cli-interp.c @@ -0,0 +1,157 @@ +/* CLI Definitions for GDB, the GNU debugger. + + Copyright 2002, 2003 Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#include "defs.h" +#include "interps.h" +#include "wrapper.h" +#include "event-top.h" +#include "ui-out.h" +#include "cli-out.h" +#include "top.h" /* for "execute_command" */ +#include "gdb_string.h" + +struct ui_out *cli_uiout; + +/* These are the ui_out and the interpreter for the console interpreter. */ + +/* Longjmp-safe wrapper for "execute_command" */ +static int do_captured_execute_command (struct ui_out *uiout, void *data); +static enum gdb_rc safe_execute_command (struct ui_out *uiout, char *command, + int from_tty); +struct captured_execute_command_args +{ + char *command; + int from_tty; +}; + +/* These implement the cli out interpreter: */ + +static void * +cli_interpreter_init (void) +{ + return NULL; +} + +static int +cli_interpreter_resume (void *data) +{ + struct ui_file *stream; + + /*sync_execution = 1; */ + + /* gdb_setup_readline will change gdb_stdout. If the CLI was previously + writing to gdb_stdout, then set it to the new gdb_stdout afterwards. */ + + stream = cli_out_set_stream (cli_uiout, gdb_stdout); + if (stream != gdb_stdout) + { + cli_out_set_stream (cli_uiout, stream); + stream = NULL; + } + + gdb_setup_readline (); + + if (stream != NULL) + cli_out_set_stream (cli_uiout, gdb_stdout); + + return 1; +} + +static int +cli_interpreter_suspend (void *data) +{ + gdb_disable_readline (); + return 1; +} + +/* Don't display the prompt if we are set quiet. */ +static int +cli_interpreter_display_prompt_p (void *data) +{ + if (interp_quiet_p (NULL)) + return 0; + else + return 1; +} + +static int +cli_interpreter_exec (void *data, const char *command_str) +{ + int result; + struct ui_file *old_stream; + + /* FIXME: cagney/2003-02-01: Need to const char *propogate + safe_execute_command. */ + char *str = strcpy (alloca (strlen (command_str) + 1), command_str); + + /* gdb_stdout could change between the time cli_uiout was initialized + and now. Since we're probably using a different interpreter which has + a new ui_file for gdb_stdout, use that one instead of the default. + + It is important that it gets reset everytime, since the user could + set gdb to use a different interpreter. */ + old_stream = cli_out_set_stream (cli_uiout, gdb_stdout); + result = safe_execute_command (cli_uiout, str, 1); + cli_out_set_stream (cli_uiout, old_stream); + return result; +} + +static int +do_captured_execute_command (struct ui_out *uiout, void *data) +{ + struct captured_execute_command_args *args = + (struct captured_execute_command_args *) data; + execute_command (args->command, args->from_tty); + return GDB_RC_OK; +} + +static enum gdb_rc +safe_execute_command (struct ui_out *uiout, char *command, int from_tty) +{ + struct captured_execute_command_args args; + args.command = command; + args.from_tty = from_tty; + return catch_exceptions (uiout, do_captured_execute_command, &args, + NULL, RETURN_MASK_ALL); +} + + +/* standard gdb initialization hook */ +extern initialize_file_ftype _initialize_cli_interp; /* -Wmissing-prototypes */ + +void +_initialize_cli_interp (void) +{ + static const struct interp_procs procs = { + cli_interpreter_init, /* init_proc */ + cli_interpreter_resume, /* resume_proc */ + cli_interpreter_suspend, /* suspend_proc */ + cli_interpreter_exec, /* exec_proc */ + cli_interpreter_display_prompt_p /* prompt_proc_p */ + }; + struct interp *cli_interp; + + /* Create a default uiout builder for the CLI. */ + cli_uiout = cli_out_new (gdb_stdout); + cli_interp = interp_new (INTERP_CONSOLE, NULL, cli_uiout, &procs); + + interp_add (cli_interp); +} diff --git a/gdb/cli/cli-logging.c b/gdb/cli/cli-logging.c new file mode 100644 index 0000000..db34b0d --- /dev/null +++ b/gdb/cli/cli-logging.c @@ -0,0 +1,205 @@ +/* Command-line output logging for GDB, the GNU debugger. + + Copyright 2003 + Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#include "defs.h" +#include "gdbcmd.h" +#include "ui-out.h" + +#include "gdb_string.h" + +/* These hold the pushed copies of the gdb output files. + If NULL then nothing has yet been pushed. */ +struct saved_output_files +{ + struct ui_file *out; + struct ui_file *err; + struct ui_file *log; + struct ui_file *targ; +}; +static struct saved_output_files saved_output; +static char *saved_filename; + +static char *logging_filename; +int logging_overwrite, logging_redirect; + +/* If we've pushed output files, close them and pop them. */ +static void +pop_output_files (void) +{ + /* Only delete one of the files -- they are all set to the same + value. */ + ui_file_delete (gdb_stdout); + gdb_stdout = saved_output.out; + gdb_stderr = saved_output.err; + gdb_stdlog = saved_output.log; + gdb_stdtarg = saved_output.targ; + saved_output.out = NULL; + saved_output.err = NULL; + saved_output.log = NULL; + saved_output.targ = NULL; + + ui_out_redirect (uiout, NULL); +} + +/* This is a helper for the `set logging' command. */ +static void +handle_redirections (int from_tty) +{ + struct ui_file *output; + + if (saved_filename != NULL) + { + fprintf_unfiltered (gdb_stdout, "Already logging to %s.\n", + saved_filename); + return; + } + + output = gdb_fopen (logging_filename, logging_overwrite ? "w" : "a"); + if (output == NULL) + perror_with_name ("set logging"); + + /* Redirects everything to gdb_stdout while this is running. */ + if (!logging_redirect) + { + output = tee_file_new (gdb_stdout, 0, output, 1); + if (output == NULL) + perror_with_name ("set logging"); + if (from_tty) + fprintf_unfiltered (gdb_stdout, "Copying output to %s.\n", + logging_filename); + } + else if (from_tty) + fprintf_unfiltered (gdb_stdout, "Redirecting output to %s.\n", + logging_filename); + + saved_filename = xstrdup (logging_filename); + saved_output.out = gdb_stdout; + saved_output.err = gdb_stderr; + saved_output.log = gdb_stdlog; + saved_output.targ = gdb_stdtarg; + + gdb_stdout = output; + gdb_stderr = output; + gdb_stdlog = output; + gdb_stdtarg = output; + + if (ui_out_redirect (uiout, gdb_stdout) < 0) + warning ("Current output protocol does not support redirection"); +} + +static void +set_logging_on (char *args, int from_tty) +{ + char *rest = args; + if (rest && *rest) + { + xfree (logging_filename); + logging_filename = xstrdup (rest); + } + handle_redirections (from_tty); +} + +static void +set_logging_off (char *args, int from_tty) +{ + if (saved_filename == NULL) + return; + + pop_output_files (); + if (from_tty) + fprintf_unfiltered (gdb_stdout, "Done logging to %s.\n", saved_filename); + xfree (saved_filename); + saved_filename = NULL; +} + +static void +set_logging_command (char *args, int from_tty) +{ + printf_unfiltered ("\"set logging\" lets you log output to a file.\n"); + printf_unfiltered ("Usage: set logging on [FILENAME]\n"); + printf_unfiltered (" set logging off\n"); + printf_unfiltered (" set logging file FILENAME\n"); + printf_unfiltered (" set logging overwrite [on|off]\n"); + printf_unfiltered (" set logging redirect [on|off]\n"); +} + +void +show_logging_command (char *args, int from_tty) +{ + if (saved_filename) + printf_unfiltered ("Currently logging to \"%s\".\n", saved_filename); + if (saved_filename == NULL + || strcmp (logging_filename, saved_filename) != 0) + printf_unfiltered ("Future logs will be written to %s.\n", + logging_filename); + + if (logging_overwrite) + printf_unfiltered ("Logs will overwrite the log file.\n"); + else + printf_unfiltered ("Logs will be appended to the log file.\n"); + + if (logging_redirect) + printf_unfiltered ("Output will be sent only to the log file.\n"); + else + printf_unfiltered ("Output will be logged and displayed.\n"); +} + +void +_initialize_cli_logging (void) +{ + static struct cmd_list_element *set_logging_cmdlist, *show_logging_cmdlist; + + + add_prefix_cmd ("logging", class_support, set_logging_command, + "Set logging options", &set_logging_cmdlist, + "set logging ", 0, &setlist); + add_prefix_cmd ("logging", class_support, show_logging_command, + "Show logging options", &show_logging_cmdlist, + "show logging ", 0, &showlist); + add_setshow_boolean_cmd ("overwrite", class_support, &logging_overwrite, + "Set whether logging overwrites or appends " + "to the log file.\n", + "Show whether logging overwrites or appends " + "to the log file.\n", + NULL, NULL, &set_logging_cmdlist, &show_logging_cmdlist); + add_setshow_boolean_cmd ("redirect", class_support, &logging_redirect, + "Set the logging output mode.\n" + "If redirect is off, output will go to both the " + "screen and the log file.\n" + "If redirect is on, output will go only to the log " + "file.", + "Show the logging output mode.\n" + "If redirect is off, output will go to both the " + "screen and the log file.\n" + "If redirect is on, output will go only to the log " + "file.", + NULL, NULL, &set_logging_cmdlist, &show_logging_cmdlist); + add_setshow_cmd ("file", class_support, var_filename, &logging_filename, + "Set the current logfile.", "Show the current logfile.", + NULL, NULL, &set_logging_cmdlist, &show_logging_cmdlist); + add_cmd ("on", class_support, set_logging_on, + "Enable logging.", &set_logging_cmdlist); + add_cmd ("off", class_support, set_logging_off, + "Disable logging.", &set_logging_cmdlist); + + logging_filename = xstrdup ("gdb.txt"); +} diff --git a/gdb/coff-pe-read.c b/gdb/coff-pe-read.c new file mode 100644 index 0000000..2d1e854 --- /dev/null +++ b/gdb/coff-pe-read.c @@ -0,0 +1,346 @@ +/* Read the export table symbols from a portable executable and + convert to internal format, for GDB. Used as a last resort if no + debugging symbols recognized. + + Copyright 2003 Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. + + Contributed by Raoul M. Gough (RaoulGough@yahoo.co.uk). */ + +#include "coff-pe-read.h" + +#include "bfd.h" + +#include "defs.h" +#include "gdbtypes.h" + +#include "symtab.h" +#include "symfile.h" +#include "objfiles.h" + +/* Internal section information */ + +struct read_pe_section_data +{ + CORE_ADDR vma_offset; /* Offset to loaded address of section. */ + unsigned long rva_start; /* Start offset within the pe. */ + unsigned long rva_end; /* End offset within the pe. */ + enum minimal_symbol_type ms_type; /* Type to assign symbols in section. */ +}; + +#define PE_SECTION_INDEX_TEXT 0 +#define PE_SECTION_INDEX_DATA 1 +#define PE_SECTION_INDEX_BSS 2 +#define PE_SECTION_TABLE_SIZE 3 +#define PE_SECTION_INDEX_INVALID -1 + +/* Get the index of the named section in our own array, which contains + text, data and bss in that order. Return PE_SECTION_INDEX_INVALID + if passed an unrecognised section name. */ + +static int +read_pe_section_index (const char *section_name) +{ + if (strcmp (section_name, ".text") == 0) + { + return PE_SECTION_INDEX_TEXT; + } + + else if (strcmp (section_name, ".data") == 0) + { + return PE_SECTION_INDEX_DATA; + } + + else if (strcmp (section_name, ".bss") == 0) + { + return PE_SECTION_INDEX_BSS; + } + + else + { + return PE_SECTION_INDEX_INVALID; + } +} + +/* Record the virtual memory address of a section. */ + +static void +get_section_vmas (bfd *abfd, asection *sectp, void *context) +{ + struct read_pe_section_data *sections = context; + int sectix = read_pe_section_index (sectp->name); + + if (sectix != PE_SECTION_INDEX_INVALID) + { + /* Data within the section start at rva_start in the pe and at + bfd_get_section_vma() within memory. Store the offset. */ + + sections[sectix].vma_offset + = bfd_get_section_vma (abfd, sectp) - sections[sectix].rva_start; + } +} + +/* Create a minimal symbol entry for an exported symbol. */ + +static void +add_pe_exported_sym (char *sym_name, + unsigned long func_rva, + const struct read_pe_section_data *section_data, + const char *dll_name, struct objfile *objfile) +{ + /* Add the stored offset to get the loaded address of the symbol. */ + + CORE_ADDR vma = func_rva + section_data->vma_offset; + + char *qualified_name = 0; + int dll_name_len = strlen (dll_name); + int count; + + /* Generate a (hopefully unique) qualified name using the first part + of the dll name, e.g. KERNEL32!AddAtomA. This matches the style + used by windbg from the "Microsoft Debugging Tools for Windows". */ + + qualified_name = xmalloc (dll_name_len + strlen (sym_name) + 2); + + strncpy (qualified_name, dll_name, dll_name_len); + qualified_name[dll_name_len] = '!'; + strcpy (qualified_name + dll_name_len + 1, sym_name); + + prim_record_minimal_symbol (qualified_name, + vma, section_data->ms_type, objfile); + + xfree (qualified_name); + + /* Enter the plain name as well, which might not be unique. */ + prim_record_minimal_symbol (sym_name, vma, section_data->ms_type, objfile); +} + +/* Truncate a dll_name at the first dot character. */ + +static void +read_pe_truncate_name (char *dll_name) +{ + while (*dll_name) + { + if ((*dll_name) == '.') + { + *dll_name = '\0'; /* truncates and causes loop exit. */ + } + + else + { + ++dll_name; + } + } +} + +/* Low-level support functions, direct from the ld module pe-dll.c. */ +static unsigned int +pe_get16 (bfd *abfd, int where) +{ + unsigned char b[2]; + + bfd_seek (abfd, (file_ptr) where, SEEK_SET); + bfd_bread (b, (bfd_size_type) 2, abfd); + return b[0] + (b[1] << 8); +} + +static unsigned int +pe_get32 (bfd *abfd, int where) +{ + unsigned char b[4]; + + bfd_seek (abfd, (file_ptr) where, SEEK_SET); + bfd_bread (b, (bfd_size_type) 4, abfd); + return b[0] + (b[1] << 8) + (b[2] << 16) + (b[3] << 24); +} + +static unsigned int +pe_as32 (void *ptr) +{ + unsigned char *b = ptr; + + return b[0] + (b[1] << 8) + (b[2] << 16) + (b[3] << 24); +} + +/* Read the (non-debug) export symbol table from a portable + executable. Code originally lifted from the ld function + pe_implied_import_dll in pe-dll.c. */ + +void +read_pe_exported_syms (struct objfile *objfile) +{ + bfd *dll = objfile->obfd; + unsigned long pe_header_offset, opthdr_ofs, num_entries, i; + unsigned long export_rva, export_size, nsections, secptr, expptr; + unsigned long exp_funcbase; + unsigned char *expdata, *erva; + unsigned long name_rvas, ordinals, nexp, ordbase; + char *dll_name; + + /* Array elements are for text, data and bss in that order + Initialization with start_rva > end_rva guarantees that + unused sections won't be matched. */ + struct read_pe_section_data section_data[PE_SECTION_TABLE_SIZE] + = { {0, 1, 0, mst_text}, + {0, 1, 0, mst_data}, + {0, 1, 0, mst_bss} + }; + + struct cleanup *back_to = 0; + + char const *target = bfd_get_target (objfile->obfd); + + if ((strcmp (target, "pe-i386") != 0) && (strcmp (target, "pei-i386") != 0)) + { + /* This is not an i386 format file. Abort now, because the code + is untested on anything else. *FIXME* test on further + architectures and loosen or remove this test. */ + return; + } + + /* Get pe_header, optional header and numbers of export entries. */ + pe_header_offset = pe_get32 (dll, 0x3c); + opthdr_ofs = pe_header_offset + 4 + 20; + num_entries = pe_get32 (dll, opthdr_ofs + 92); + + if (num_entries < 1) /* No exports. */ + { + return; + } + + export_rva = pe_get32 (dll, opthdr_ofs + 96); + export_size = pe_get32 (dll, opthdr_ofs + 100); + nsections = pe_get16 (dll, pe_header_offset + 4 + 2); + secptr = (pe_header_offset + 4 + 20 + + pe_get16 (dll, pe_header_offset + 4 + 16)); + expptr = 0; + + /* Get the rva and size of the export section. */ + for (i = 0; i < nsections; i++) + { + char sname[8]; + unsigned long secptr1 = secptr + 40 * i; + unsigned long vaddr = pe_get32 (dll, secptr1 + 12); + unsigned long vsize = pe_get32 (dll, secptr1 + 16); + unsigned long fptr = pe_get32 (dll, secptr1 + 20); + + bfd_seek (dll, (file_ptr) secptr1, SEEK_SET); + bfd_bread (sname, (bfd_size_type) 8, dll); + + if (vaddr <= export_rva && vaddr + vsize > export_rva) + { + expptr = fptr + (export_rva - vaddr); + if (export_rva + export_size > vaddr + vsize) + export_size = vsize - (export_rva - vaddr); + break; + } + } + + if (export_size == 0) + { + /* Empty export table. */ + return; + } + + /* Scan sections and store the base and size of the relevant sections. */ + for (i = 0; i < nsections; i++) + { + unsigned long secptr1 = secptr + 40 * i; + unsigned long vsize = pe_get32 (dll, secptr1 + 8); + unsigned long vaddr = pe_get32 (dll, secptr1 + 12); + unsigned long flags = pe_get32 (dll, secptr1 + 36); + char sec_name[9]; + int sectix; + + sec_name[8] = '\0'; + bfd_seek (dll, (file_ptr) secptr1 + 0, SEEK_SET); + bfd_bread (sec_name, (bfd_size_type) 8, dll); + + sectix = read_pe_section_index (sec_name); + + if (sectix != PE_SECTION_INDEX_INVALID) + { + section_data[sectix].rva_start = vaddr; + section_data[sectix].rva_end = vaddr + vsize; + } + } + + expdata = (unsigned char *) xmalloc (export_size); + back_to = make_cleanup (xfree, expdata); + + bfd_seek (dll, (file_ptr) expptr, SEEK_SET); + bfd_bread (expdata, (bfd_size_type) export_size, dll); + erva = expdata - export_rva; + + nexp = pe_as32 (expdata + 24); + name_rvas = pe_as32 (expdata + 32); + ordinals = pe_as32 (expdata + 36); + ordbase = pe_as32 (expdata + 16); + exp_funcbase = pe_as32 (expdata + 28); + + /* Use internal dll name instead of full pathname. */ + dll_name = pe_as32 (expdata + 12) + erva; + + bfd_map_over_sections (dll, get_section_vmas, section_data); + + /* Adjust the vma_offsets in case this PE got relocated. This + assumes that *all* sections share the same relocation offset + as the text section. */ + for (i = 0; i < PE_SECTION_TABLE_SIZE; i++) + { + section_data[i].vma_offset + += ANOFFSET (objfile->section_offsets, SECT_OFF_TEXT (objfile)); + } + + printf_filtered ("Minimal symbols from %s...", dll_name); + wrap_here (""); + + /* Truncate name at first dot. Should maybe also convert to all + lower case for convenience on Windows. */ + read_pe_truncate_name (dll_name); + + /* Iterate through the list of symbols. */ + for (i = 0; i < nexp; i++) + { + /* Pointer to the names vector. */ + unsigned long name_rva = pe_as32 (erva + name_rvas + i * 4); + + /* Pointer to the function address vector. */ + unsigned long func_rva = pe_as32 (erva + exp_funcbase + i * 4); + + /* Find this symbol's section in our own array. */ + int sectix = 0; + + for (sectix = 0; sectix < PE_SECTION_TABLE_SIZE; ++sectix) + { + if ((func_rva >= section_data[sectix].rva_start) + && (func_rva < section_data[sectix].rva_end)) + { + add_pe_exported_sym (erva + name_rva, + func_rva, + section_data + sectix, dll_name, objfile); + break; + } + } + } + + /* discard expdata. */ + do_cleanups (back_to); +} diff --git a/gdb/coff-pe-read.h b/gdb/coff-pe-read.h new file mode 100644 index 0000000..c5d4e68 --- /dev/null +++ b/gdb/coff-pe-read.h @@ -0,0 +1,32 @@ +/* Interface to coff-pe-read.c (portable-executable-specific symbol reader). + + Copyright 2003 Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. + + Contributed by Raoul M. Gough (RaoulGough@yahoo.co.uk). */ + +#if !defined (COFF_PE_READ_H) +#define COFF_PE_READ_H + +struct objfile; + +/* Read the export table and convert it to minimal symbol table entries */ +extern void read_pe_exported_syms (struct objfile *objfile); + +#endif /* !defined (COFF_PE_READ_H) */ diff --git a/gdb/config/arm/tm-nbsd.h b/gdb/config/arm/tm-nbsd.h new file mode 100644 index 0000000..97bca68 --- /dev/null +++ b/gdb/config/arm/tm-nbsd.h @@ -0,0 +1,26 @@ +/* Macro definitions for ARM running under NetBSD. + Copyright 2003 Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#ifndef TM_NBSD_H +#define TM_NBSD_H + +#include "solib.h" + +#endif /* TM_NBSD_H */ diff --git a/gdb/config/i386/fbsd64.mh b/gdb/config/i386/fbsd64.mh new file mode 100644 index 0000000..eaa801f --- /dev/null +++ b/gdb/config/i386/fbsd64.mh @@ -0,0 +1,7 @@ +# Host: FreeBSD/amd64 + +XM_FILE= xm-i386.h + +NAT_FILE= nm-fbsd64.h +# NOTE: Do not spread NATDEPFILES over several lines - it hurts BSD make. +NATDEPFILES= fork-child.o infptrace.o inftarg.o solib.o solib-svr4.o solib-legacy.o amd64-nat.o amd64bsd-nat.o amd64fbsd-nat.o gcore.o fbsd-proc.o diff --git a/gdb/config/i386/fbsd64.mt b/gdb/config/i386/fbsd64.mt new file mode 100644 index 0000000..3a66a15 --- /dev/null +++ b/gdb/config/i386/fbsd64.mt @@ -0,0 +1,2 @@ +# Target: FreeBSD/amd64 +TDEPFILES= x86-64-tdep.o amd64fbsd-tdep.o i386-tdep.o i387-tdep.o i386bsd-tdep.o i386fbsd-tdep.o corelow.o diff --git a/gdb/config/i386/interix.mh b/gdb/config/i386/interix.mh new file mode 100644 index 0000000..23311d6 --- /dev/null +++ b/gdb/config/i386/interix.mh @@ -0,0 +1,9 @@ +# Host: Intel 386 running Interix +XDEPFILES= +NATDEPFILES= corelow.o core-regset.o fork-child.o i386-interix-nat.o \ + procfs.o proc-api.o proc-events.o proc-flags.o proc-why.o +NAT_FILE= nm-interix.h +XM_FILE= xm-interix.h +# The below may be temporary; mmalloc relies on sbrk() at the moment +MMALLOC= +MMALLOC_CFLAGS=-DNO_MMALLOC diff --git a/gdb/config/i386/interix.mt b/gdb/config/i386/interix.mt new file mode 100644 index 0000000..8d60962 --- /dev/null +++ b/gdb/config/i386/interix.mt @@ -0,0 +1,3 @@ +# Target: Intel 386 running Interix +TDEPFILES= i386-tdep.o i387-tdep.o i386-interix-tdep.o solib.o solib-pei.o +TM_FILE= tm-i386.h diff --git a/gdb/config/i386/nbsd64.mh b/gdb/config/i386/nbsd64.mh new file mode 100644 index 0000000..5acd167 --- /dev/null +++ b/gdb/config/i386/nbsd64.mh @@ -0,0 +1,7 @@ +# Host: NetBSD/amd64 + +XM_FILE= xm-i386.h + +NAT_FILE= nm-nbsd.h +# NOTE: Do not spread NATDEPFILES over several lines - it hurts BSD make. +NATDEPFILES= fork-child.o infptrace.o inftarg.o solib.o solib-svr4.o solib-legacy.o corelow.o amd64-nat.o amd64bsd-nat.o amd64nbsd-nat.o diff --git a/gdb/config/i386/nbsd64.mt b/gdb/config/i386/nbsd64.mt new file mode 100644 index 0000000..6d73660 --- /dev/null +++ b/gdb/config/i386/nbsd64.mt @@ -0,0 +1,2 @@ +# Target: NetBSD/amd64 +TDEPFILES= x86-64-tdep.o amd64nbsd-tdep.o i386-tdep.o i387-tdep.o nbsd-tdep.o diff --git a/gdb/config/i386/nm-fbsd64.h b/gdb/config/i386/nm-fbsd64.h new file mode 100644 index 0000000..e5b66df --- /dev/null +++ b/gdb/config/i386/nm-fbsd64.h @@ -0,0 +1,42 @@ +/* Native-dependent definitions for FreeBSD/amd64. + Copyright 2003 + Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#ifndef NM_FBSD64_H +#define NM_FBSD64_H + +/* Type of the third argument to the `ptrace' system call. */ +#define PTRACE_ARG3_TYPE caddr_t + +/* Override copies of {fetch,store}_inferior_registers in `infptrace.c'. */ +#define FETCH_INFERIOR_REGISTERS + +/* Override child_pid_to_exec_file in 'inftarg.c'. */ +#define CHILD_PID_TO_EXEC_FILE + +/* We can attach and detach. */ +#define ATTACH_DETACH + + +/* Shared library support. */ + +#include "solib.h" + +#endif /* nm-fbsd64.h */ diff --git a/gdb/config/i386/nm-interix.h b/gdb/config/i386/nm-interix.h new file mode 100644 index 0000000..b8b003a --- /dev/null +++ b/gdb/config/i386/nm-interix.h @@ -0,0 +1,35 @@ +/* Native-dependent definitions for Intel 386 running Interix, for GDB. + Copyright 1986, 1987, 1989, 1992, 1996 Free Software Foundation, Inc. + +This file is part of GDB. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef NM_INTERIX_H +#define NM_INTERIX_H + +/* Be shared lib aware. */ +#include "solib.h" + +/* submodes of USE_PROC_FS. */ +#define UNIXWARE + +/* It's ALMOST coff; bfd does the same thing. Mostly used in coffread.c. */ +#define COFF_IMAGE_WITH_PE + +/* Turn on our own child_pid_to_exec_file. */ +#define CHILD_PID_TO_EXEC_FILE + +#endif /* NM_INTERIX_H */ diff --git a/gdb/config/i386/nm-nto.h b/gdb/config/i386/nm-nto.h new file mode 100644 index 0000000..34d9903 --- /dev/null +++ b/gdb/config/i386/nm-nto.h @@ -0,0 +1,6 @@ +#ifndef _NM_NTO_H +#define _NM_NTO_H + +/* This file needed to build a native debugger. */ + +#endif diff --git a/gdb/config/i386/nto.mh b/gdb/config/i386/nto.mh new file mode 100644 index 0000000..f412579 --- /dev/null +++ b/gdb/config/i386/nto.mh @@ -0,0 +1,7 @@ +# Host: Intel 386 running QNX. + +NAT_FILE= nm-nto.h + +NATDEPFILES= nto-procfs.o + +XM_FILE= xm-i386.h diff --git a/gdb/config/i386/nto.mt b/gdb/config/i386/nto.mt new file mode 100644 index 0000000..6655f3e --- /dev/null +++ b/gdb/config/i386/nto.mt @@ -0,0 +1,4 @@ +# Target: Intel 386 running qnx6. +TDEPFILES = i386-tdep.o i387-tdep.o corelow.o solib.o solib-svr4.o \ + i386-nto-tdep.o nto-tdep.o remote-nto.o +TM_FILE = tm-nto.h diff --git a/gdb/config/i386/tm-nto.h b/gdb/config/i386/tm-nto.h new file mode 100644 index 0000000..ff5eb78 --- /dev/null +++ b/gdb/config/i386/tm-nto.h @@ -0,0 +1,33 @@ +/* QNX Neutrino target header. + + Copyright 2003 Free Software Foundation, Inc. + + This code was donated by QNX Software Systems Ltd. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#ifndef TM_NTO_H +#define TM_NTO_H 1 + +/* Pick up most of what we need from the generic i386 target include file. */ +#include "i386/tm-i386.h" +#include "tm-nto.h" + +#include "solib.h" + +#endif /* TM_NTO_H */ diff --git a/gdb/config/powerpc/nm-ppc64-linux.h b/gdb/config/powerpc/nm-ppc64-linux.h new file mode 100644 index 0000000..5d1c7b6 --- /dev/null +++ b/gdb/config/powerpc/nm-ppc64-linux.h @@ -0,0 +1,27 @@ +/* IBM PowerPC64 native-dependent macros for GDB, the GNU debugger. + Copyright 2003 Free Software Foundation, Inc. + +This file is part of GDB. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ + +#ifndef NM_PPC64_LINUX_H + +#include "config/powerpc/nm-linux.h" + +#define PTRACE_ARG3_TYPE void * +#define PTRACE_XFER_TYPE long + +#endif /* NM_PPC64_LINUX_H */ diff --git a/gdb/config/powerpc/ppc64-linux.mh b/gdb/config/powerpc/ppc64-linux.mh new file mode 100644 index 0000000..dd81586 --- /dev/null +++ b/gdb/config/powerpc/ppc64-linux.mh @@ -0,0 +1,19 @@ +# Host: PowerPC64, running Linux + +XM_FILE= xm-linux.h +XM_CLIBS= + +NAT_FILE= nm-ppc64-linux.h +NATDEPFILES= infptrace.o inftarg.o fork-child.o linux-proc.o \ + ppc-linux-nat.o proc-service.o thread-db.o lin-lwp.o \ + gcore.o linux-nat.o + +# The PowerPC has severe limitations on TOC size, and uses them even +# for non-PIC code. GDB overflows those tables when compiling with +# -mfull-toc (the default), so we need to ask GCC to use as few TOC +# entries as possible. +MH_CFLAGS= -mminimal-toc + +# The dynamically loaded libthread_db needs access to symbols in the +# gdb executable. +LOADLIBES= -ldl -rdynamic diff --git a/gdb/config/tm-nto.h b/gdb/config/tm-nto.h new file mode 100644 index 0000000..359ff06 --- /dev/null +++ b/gdb/config/tm-nto.h @@ -0,0 +1,61 @@ +/* Target machine sub-description for QNX Neutrino version 6. + This is included by other tm-*.h files to specify nto specific + stuff. + + Copyright 2003 Free Software Foundation, Inc. + + This code was donated by QNX Software Systems Ltd. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#ifndef _TM_QNXNTO_H +#define _TM_QNXNTO_H + +#include "tm-sysv4.h" + +/* Setup the valid realtime signal range. */ +#define REALTIME_LO 41 +#define REALTIME_HI 56 + +/* Set up the undefined useable signals. */ +#define RAW_SIGNAL_LO 32 +#define RAW_SIGNAL_HI (REALTIME_LO - 1) + +#define TARGET_SIGNAL_RAW_VALUES \ +TARGET_SIGNAL_RAW0, \ +TARGET_SIGNAL_RAW1, \ +TARGET_SIGNAL_RAW2, \ +TARGET_SIGNAL_RAW3, \ +TARGET_SIGNAL_RAW4, \ +TARGET_SIGNAL_RAW5, \ +TARGET_SIGNAL_RAW6, \ +TARGET_SIGNAL_RAW7, \ +TARGET_SIGNAL_RAW8 + +#define TARGET_SIGNAL_RAW_TABLE \ +{"SIGNAL32", "Signal 32"}, \ +{"SIGNAL33", "Signal 33"}, \ +{"SIGNAL34", "Signal 34"}, \ +{"SIGNAL35", "Signal 35"}, \ +{"SIGNAL36", "Signal 36"}, \ +{"SIGNAL37", "Signal 37"}, \ +{"SIGNAL38", "Signal 38"}, \ +{"SIGNAL39", "Signal 39"}, \ +{"SIGNAL40", "Signal 40"} + +#endif /* _TM_QNXNTO_H */ diff --git a/gdb/cp-namespace.c b/gdb/cp-namespace.c new file mode 100644 index 0000000..044b473 --- /dev/null +++ b/gdb/cp-namespace.c @@ -0,0 +1,788 @@ +/* Helper routines for C++ support in GDB. + Copyright 2003 Free Software Foundation, Inc. + + Contributed by David Carlton and by Kealia, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#include "defs.h" +#include "cp-support.h" +#include "gdb_obstack.h" +#include "symtab.h" +#include "symfile.h" +#include "gdb_assert.h" +#include "block.h" +#include "objfiles.h" +#include "gdbtypes.h" +#include "dictionary.h" +#include "command.h" + +/* When set, the file that we're processing seems to have debugging + info for C++ namespaces, so cp-namespace.c shouldn't try to guess + namespace info itself. */ + +unsigned char processing_has_namespace_info; + +/* If processing_has_namespace_info is nonzero, this string should + contain the name of the current namespace. The string is + temporary; copy it if you need it. */ + +/* FIXME: carlton/2003-06-12: This isn't entirely reliable: currently, + we get mislead by DW_AT_specification. */ + +const char *processing_current_namespace; + +/* List of using directives that are active in the current file. */ + +static struct using_direct *using_list; + +static struct using_direct *cp_add_using (const char *name, + unsigned int inner_len, + unsigned int outer_len, + struct using_direct *next); + +static struct using_direct *cp_copy_usings (struct using_direct *using, + struct obstack *obstack); + +static struct symbol *lookup_namespace_scope (const char *name, + const char *linkage_name, + const struct block *block, + const domain_enum domain, + struct symtab **symtab, + const char *scope, + int scope_len); + +static struct symbol *lookup_symbol_file (const char *name, + const char *linkage_name, + const struct block *block, + const domain_enum domain, + struct symtab **symtab, + int anonymous_namespace); + +static void initialize_namespace_symtab (struct objfile *objfile); + +static struct block *get_possible_namespace_block (struct objfile *objfile); + +static void free_namespace_block (struct symtab *symtab); + +static int check_possible_namespace_symbols_loop (const char *name, + int len, + struct objfile *objfile); + +static int check_one_possible_namespace_symbol (const char *name, + int len, + struct objfile *objfile); + +static +struct symbol *lookup_possible_namespace_symbol (const char *name, + struct symtab **symtab); + +static void maintenance_cplus_namespace (char *args, int from_tty); + +/* Set up support for dealing with C++ namespace info in the current + symtab. */ + +void cp_initialize_namespace () +{ + processing_has_namespace_info = 0; + using_list = NULL; +} + +/* Add all the using directives we've gathered to the current symtab. + STATIC_BLOCK should be the symtab's static block; OBSTACK is used + for allocation. */ + +void +cp_finalize_namespace (struct block *static_block, + struct obstack *obstack) +{ + if (using_list != NULL) + { + block_set_using (static_block, + cp_copy_usings (using_list, obstack), + obstack); + using_list = NULL; + } +} + +/* Check to see if SYMBOL refers to an object contained within an + anonymous namespace; if so, add an appropriate using directive. */ + +/* Optimize away strlen ("(anonymous namespace)"). */ + +#define ANONYMOUS_NAMESPACE_LEN 21 + +void +cp_scan_for_anonymous_namespaces (const struct symbol *symbol) +{ + if (!processing_has_namespace_info + && SYMBOL_CPLUS_DEMANGLED_NAME (symbol) != NULL) + { + const char *name = SYMBOL_CPLUS_DEMANGLED_NAME (symbol); + unsigned int previous_component; + unsigned int next_component; + const char *len; + + /* Start with a quick-and-dirty check for mention of "(anonymous + namespace)". */ + + if (!cp_is_anonymous (name)) + return; + + previous_component = 0; + next_component = cp_find_first_component (name + previous_component); + + while (name[next_component] == ':') + { + if ((next_component - previous_component) == ANONYMOUS_NAMESPACE_LEN + && strncmp (name + previous_component, + "(anonymous namespace)", + ANONYMOUS_NAMESPACE_LEN) == 0) + { + /* We've found a component of the name that's an + anonymous namespace. So add symbols in it to the + namespace given by the previous component if there is + one, or to the global namespace if there isn't. */ + cp_add_using_directive (name, + previous_component == 0 + ? 0 : previous_component - 2, + next_component); + } + /* The "+ 2" is for the "::". */ + previous_component = next_component + 2; + next_component = (previous_component + + cp_find_first_component (name + + previous_component)); + } + } +} + +/* Add a using directive to using_list. NAME is the start of a string + that should contain the namespaces we want to add as initial + substrings, OUTER_LENGTH is the end of the outer namespace, and + INNER_LENGTH is the end of the inner namespace. If the using + directive in question has already been added, don't add it + twice. */ + +void +cp_add_using_directive (const char *name, unsigned int outer_length, + unsigned int inner_length) +{ + struct using_direct *current; + struct using_direct *new; + + /* Has it already been added? */ + + for (current = using_list; current != NULL; current = current->next) + { + if ((strncmp (current->inner, name, inner_length) == 0) + && (strlen (current->inner) == inner_length) + && (strlen (current->outer) == outer_length)) + return; + } + + using_list = cp_add_using (name, inner_length, outer_length, + using_list); +} + +/* Record the namespace that the function defined by SYMBOL was + defined in, if necessary. BLOCK is the associated block; use + OBSTACK for allocation. */ + +void +cp_set_block_scope (const struct symbol *symbol, + struct block *block, + struct obstack *obstack) +{ + /* Make sure that the name was originally mangled: if not, there + certainly isn't any namespace information to worry about! */ + + if (SYMBOL_CPLUS_DEMANGLED_NAME (symbol) != NULL) + { +#if 0 + /* FIXME: carlton/2003-06-12: As mentioned above, + 'processing_has_namespace_info' currently isn't entirely + reliable, so let's always use demangled names to get this + information for now. */ + + if (processing_has_namespace_info) + { + block_set_scope + (block, obsavestring (processing_current_namespace, + strlen (processing_current_namespace), + obstack), + obstack); + } + else +#endif + { + /* Try to figure out the appropriate namespace from the + demangled name. */ + + /* FIXME: carlton/2003-04-15: If the function in question is + a method of a class, the name will actually include the + name of the class as well. This should be harmless, but + is a little unfortunate. */ + + const char *name = SYMBOL_CPLUS_DEMANGLED_NAME (symbol); + unsigned int prefix_len = cp_entire_prefix_len (name); + + block_set_scope (block, + obsavestring (name, prefix_len, obstack), + obstack); + } + } +} + +/* Test whether or not NAMESPACE looks like it mentions an anonymous + namespace; return nonzero if so. */ + +int +cp_is_anonymous (const char *namespace) +{ + return (strstr (namespace, "(anonymous namespace)") + != NULL); +} + +/* Create a new struct using direct whose inner namespace is the + initial substring of NAME of leng INNER_LEN and whose outer + namespace is the initial substring of NAME of length OUTER_LENGTH. + Set its next member in the linked list to NEXT; allocate all memory + using xmalloc. It copies the strings, so NAME can be a temporary + string. */ + +static struct using_direct * +cp_add_using (const char *name, + unsigned int inner_len, + unsigned int outer_len, + struct using_direct *next) +{ + struct using_direct *retval; + + gdb_assert (outer_len < inner_len); + + retval = xmalloc (sizeof (struct using_direct)); + retval->inner = savestring (name, inner_len); + retval->outer = savestring (name, outer_len); + retval->next = next; + + return retval; +} + +/* Make a copy of the using directives in the list pointed to by + USING, using OBSTACK to allocate memory. Free all memory pointed + to by USING via xfree. */ + +static struct using_direct * +cp_copy_usings (struct using_direct *using, + struct obstack *obstack) +{ + if (using == NULL) + { + return NULL; + } + else + { + struct using_direct *retval + = obstack_alloc (obstack, sizeof (struct using_direct)); + retval->inner = obsavestring (using->inner, strlen (using->inner), + obstack); + retval->outer = obsavestring (using->outer, strlen (using->outer), + obstack); + retval->next = cp_copy_usings (using->next, obstack); + + xfree (using->inner); + xfree (using->outer); + xfree (using); + + return retval; + } +} + +/* The C++-specific version of name lookup for static and global + names. This makes sure that names get looked for in all namespaces + that are in scope. NAME is the natural name of the symbol that + we're looking for, LINKAGE_NAME (which is optional) is its linkage + name, BLOCK is the block that we're searching within, DOMAIN says + what kind of symbols we're looking for, and if SYMTAB is non-NULL, + we should store the symtab where we found the symbol in it. */ + +struct symbol * +cp_lookup_symbol_nonlocal (const char *name, + const char *linkage_name, + const struct block *block, + const domain_enum domain, + struct symtab **symtab) +{ + return lookup_namespace_scope (name, linkage_name, block, domain, + symtab, block_scope (block), 0); +} + +/* Lookup NAME at namespace scope (or, in C terms, in static and + global variables). SCOPE is the namespace that the current + function is defined within; only consider namespaces whose length + is at least SCOPE_LEN. Other arguments are as in + cp_lookup_symbol_nonlocal. + + For example, if we're within a function A::B::f and looking for a + symbol x, this will get called with NAME = "x", SCOPE = "A::B", and + SCOPE_LEN = 0. It then calls itself with NAME and SCOPE the same, + but with SCOPE_LEN = 1. And then it calls itself with NAME and + SCOPE the same, but with SCOPE_LEN = 4. This third call looks for + "A::B::x"; if it doesn't find it, then the second call looks for + "A::x", and if that call fails, then the first call looks for + "x". */ + +static struct symbol * +lookup_namespace_scope (const char *name, + const char *linkage_name, + const struct block *block, + const domain_enum domain, + struct symtab **symtab, + const char *scope, + int scope_len) +{ + char *namespace; + + if (scope[scope_len] != '\0') + { + /* Recursively search for names in child namespaces first. */ + + struct symbol *sym; + int new_scope_len = scope_len; + + /* If the current scope is followed by "::", skip past that. */ + if (new_scope_len != 0) + { + gdb_assert (scope[new_scope_len] == ':'); + new_scope_len += 2; + } + new_scope_len += cp_find_first_component (scope + new_scope_len); + sym = lookup_namespace_scope (name, linkage_name, block, + domain, symtab, + scope, new_scope_len); + if (sym != NULL) + return sym; + } + + /* Okay, we didn't find a match in our children, so look for the + name in the current namespace. */ + + namespace = alloca (scope_len + 1); + strncpy (namespace, scope, scope_len); + namespace[scope_len] = '\0'; + return cp_lookup_symbol_namespace (namespace, name, linkage_name, + block, domain, symtab); +} + +/* Look up NAME in the C++ namespace NAMESPACE, applying the using + directives that are active in BLOCK. Other arguments are as in + cp_lookup_symbol_nonlocal. */ + +struct symbol * +cp_lookup_symbol_namespace (const char *namespace, + const char *name, + const char *linkage_name, + const struct block *block, + const domain_enum domain, + struct symtab **symtab) +{ + const struct using_direct *current; + struct symbol *sym; + + /* First, go through the using directives. If any of them add new + names to the namespace we're searching in, see if we can find a + match by applying them. */ + + for (current = block_using (block); + current != NULL; + current = current->next) + { + if (strcmp (namespace, current->outer) == 0) + { + sym = cp_lookup_symbol_namespace (current->inner, + name, + linkage_name, + block, + domain, + symtab); + if (sym != NULL) + return sym; + } + } + + /* We didn't find anything by applying any of the using directives + that are still applicable; so let's see if we've got a match + using the current namespace. */ + + if (namespace[0] == '\0') + { + return lookup_symbol_file (name, linkage_name, block, + domain, symtab, 0); + } + else + { + char *concatenated_name + = alloca (strlen (namespace) + 2 + strlen (name) + 1); + strcpy (concatenated_name, namespace); + strcat (concatenated_name, "::"); + strcat (concatenated_name, name); + sym = lookup_symbol_file (concatenated_name, linkage_name, + block, domain, symtab, + cp_is_anonymous (namespace)); + return sym; + } +} + +/* Look up NAME in BLOCK's static block and in global blocks. If + ANONYMOUS_NAMESPACE is nonzero, the symbol in question is located + within an anonymous namespace. Other arguments are as in + cp_lookup_symbol_nonlocal. */ + +static struct symbol * +lookup_symbol_file (const char *name, + const char *linkage_name, + const struct block *block, + const domain_enum domain, + struct symtab **symtab, + int anonymous_namespace) +{ + struct symbol *sym = NULL; + + sym = lookup_symbol_static (name, linkage_name, block, domain, symtab); + if (sym != NULL) + return sym; + + if (anonymous_namespace) + { + /* Symbols defined in anonymous namespaces have external linkage + but should be treated as local to a single file nonetheless. + So we only search the current file's global block. */ + + const struct block *global_block = block_global_block (block); + + if (global_block != NULL) + sym = lookup_symbol_aux_block (name, linkage_name, global_block, + domain, symtab); + } + else + { + sym = lookup_symbol_global (name, linkage_name, domain, symtab); + } + + if (sym != NULL) + return sym; + + /* Now call "lookup_possible_namespace_symbol". Symbols in here + claim to be associated to namespaces, but this claim might be + incorrect: the names in question might actually correspond to + classes instead of namespaces. But if they correspond to + classes, then we should have found a match for them above. So if + we find them now, they should be genuine. */ + + /* FIXME: carlton/2003-06-12: This is a hack and should eventually + be deleted: see comments below. */ + + if (domain == VAR_DOMAIN) + { + sym = lookup_possible_namespace_symbol (name, symtab); + if (sym != NULL) + return sym; + } + + return NULL; +} + +/* Look up a type named NESTED_NAME that is nested inside the C++ + class or namespace given by PARENT_TYPE, from within the context + given by BLOCK. Return NULL if there is no such nested type. */ + +/* FIXME: carlton/2003-09-24: For now, this only works for nested + namespaces; the patch to make this work on other sorts of nested + types is next on my TODO list. */ + +struct type * +cp_lookup_nested_type (struct type *parent_type, + const char *nested_name, + const struct block *block) +{ + switch (TYPE_CODE (parent_type)) + { + case TYPE_CODE_NAMESPACE: + { + const char *parent_name = TYPE_TAG_NAME (parent_type); + struct symbol *sym = cp_lookup_symbol_namespace (parent_name, + nested_name, + NULL, + block, + VAR_DOMAIN, + NULL); + if (sym == NULL || SYMBOL_CLASS (sym) != LOC_TYPEDEF) + return NULL; + else + return SYMBOL_TYPE (sym); + } + default: + internal_error (__FILE__, __LINE__, + "cp_lookup_nested_type called on a non-namespace."); + } +} + +/* Now come functions for dealing with symbols associated to + namespaces. (They're used to store the namespaces themselves, not + objects that live in the namespaces.) These symbols come in two + varieties: if we run into a DW_TAG_namespace DIE, then we know that + we have a namespace, so dwarf2read.c creates a symbol for it just + like normal. But, unfortunately, versions of GCC through at least + 3.3 don't generate those DIE's. Our solution is to try to guess + their existence by looking at demangled names. This might cause us + to misidentify classes as namespaces, however. So we put those + symbols in a special block (one per objfile), and we only search + that block as a last resort. */ + +/* FIXME: carlton/2003-06-12: Once versions of GCC that generate + DW_TAG_namespace have been out for a year or two, we should get rid + of all of this "possible namespace" nonsense. */ + +/* Allocate everything necessary for the possible namespace block + associated to OBJFILE. */ + +static void +initialize_namespace_symtab (struct objfile *objfile) +{ + struct symtab *namespace_symtab; + struct blockvector *bv; + struct block *bl; + + namespace_symtab = allocate_symtab ("<>", objfile); + namespace_symtab->language = language_cplus; + namespace_symtab->free_code = free_nothing; + namespace_symtab->dirname = NULL; + + bv = obstack_alloc (&objfile->symbol_obstack, + sizeof (struct blockvector) + + FIRST_LOCAL_BLOCK * sizeof (struct block *)); + BLOCKVECTOR_NBLOCKS (bv) = FIRST_LOCAL_BLOCK + 1; + BLOCKVECTOR (namespace_symtab) = bv; + + /* Allocate empty GLOBAL_BLOCK and STATIC_BLOCK. */ + + bl = allocate_block (&objfile->symbol_obstack); + BLOCK_DICT (bl) = dict_create_linear (&objfile->symbol_obstack, + NULL); + BLOCKVECTOR_BLOCK (bv, GLOBAL_BLOCK) = bl; + bl = allocate_block (&objfile->symbol_obstack); + BLOCK_DICT (bl) = dict_create_linear (&objfile->symbol_obstack, + NULL); + BLOCKVECTOR_BLOCK (bv, STATIC_BLOCK) = bl; + + /* Allocate the possible namespace block; we put it where the first + local block will live, though I don't think there's any need to + pretend that it's actually a local block (e.g. by setting + BLOCK_SUPERBLOCK appropriately). We don't use the global or + static block because we don't want it searched during the normal + search of all global/static blocks in lookup_symbol: we only want + it used as a last resort. */ + + /* NOTE: carlton/2003-09-11: I considered not associating the fake + symbols to a block/symtab at all. But that would cause problems + with lookup_symbol's SYMTAB argument and with block_found, so + having a symtab/block for this purpose seems like the best + solution for now. */ + + bl = allocate_block (&objfile->symbol_obstack); + BLOCK_DICT (bl) = dict_create_hashed_expandable (); + BLOCKVECTOR_BLOCK (bv, FIRST_LOCAL_BLOCK) = bl; + + namespace_symtab->free_func = free_namespace_block; + + objfile->cp_namespace_symtab = namespace_symtab; +} + +/* Locate the possible namespace block associated to OBJFILE, + allocating it if necessary. */ + +static struct block * +get_possible_namespace_block (struct objfile *objfile) +{ + if (objfile->cp_namespace_symtab == NULL) + initialize_namespace_symtab (objfile); + + return BLOCKVECTOR_BLOCK (BLOCKVECTOR (objfile->cp_namespace_symtab), + FIRST_LOCAL_BLOCK); +} + +/* Free the dictionary associated to the possible namespace block. */ + +static void +free_namespace_block (struct symtab *symtab) +{ + struct block *possible_namespace_block; + + possible_namespace_block = BLOCKVECTOR_BLOCK (BLOCKVECTOR (symtab), + FIRST_LOCAL_BLOCK); + gdb_assert (possible_namespace_block != NULL); + dict_free (BLOCK_DICT (possible_namespace_block)); +} + +/* Ensure that there are symbols in the possible namespace block + associated to OBJFILE for all initial substrings of NAME that look + like namespaces or classes. NAME should end in a member variable: + it shouldn't consist solely of namespaces. */ + +void +cp_check_possible_namespace_symbols (const char *name, struct objfile *objfile) +{ + check_possible_namespace_symbols_loop (name, + cp_find_first_component (name), + objfile); +} + +/* This is a helper loop for cp_check_possible_namespace_symbols; it + ensures that there are symbols in the possible namespace block + associated to OBJFILE for all namespaces that are initial + substrings of NAME of length at least LEN. It returns 1 if a + previous loop had already created the shortest such symbol and 0 + otherwise. + + This function assumes that if there is already a symbol associated + to a substring of NAME of a given length, then there are already + symbols associated to all substrings of NAME whose length is less + than that length. So if cp_check_possible_namespace_symbols has + been called once with argument "A::B::C::member", then that will + create symbols "A", "A::B", and "A::B::C". If it is then later + called with argument "A::B::D::member", then the new call will + generate a new symbol for "A::B::D", but once it sees that "A::B" + has already been created, it doesn't bother checking to see if "A" + has also been created. */ + +static int +check_possible_namespace_symbols_loop (const char *name, int len, + struct objfile *objfile) +{ + if (name[len] == ':') + { + int done; + int next_len = len + 2; + + next_len += cp_find_first_component (name + next_len); + done = check_possible_namespace_symbols_loop (name, next_len, + objfile); + + if (!done) + done = check_one_possible_namespace_symbol (name, len, objfile); + + return done; + } + else + return 0; +} + +/* Check to see if there's already a possible namespace symbol in + OBJFILE whose name is the initial substring of NAME of length LEN. + If not, create one and return 0; otherwise, return 1. */ + +static int +check_one_possible_namespace_symbol (const char *name, int len, + struct objfile *objfile) +{ + struct block *block = get_possible_namespace_block (objfile); + char *name_copy = obsavestring (name, len, &objfile->symbol_obstack); + struct symbol *sym = lookup_block_symbol (block, name_copy, NULL, + VAR_DOMAIN); + + if (sym == NULL) + { + struct type *type = init_type (TYPE_CODE_NAMESPACE, 0, 0, + name_copy, objfile); + TYPE_TAG_NAME (type) = TYPE_NAME (type); + + sym = obstack_alloc (&objfile->symbol_obstack, sizeof (struct symbol)); + memset (sym, 0, sizeof (struct symbol)); + SYMBOL_LANGUAGE (sym) = language_cplus; + SYMBOL_SET_NAMES (sym, name_copy, len, objfile); + SYMBOL_CLASS (sym) = LOC_TYPEDEF; + SYMBOL_TYPE (sym) = type; + SYMBOL_DOMAIN (sym) = VAR_DOMAIN; + + dict_add_symbol (BLOCK_DICT (block), sym); + + return 0; + } + else + { + obstack_free (&objfile->symbol_obstack, name_copy); + + return 1; + } +} + +/* Look for a symbol named NAME in all the possible namespace blocks. + If one is found, return it; if SYMTAB is non-NULL, set *SYMTAB to + equal the symtab where it was found. */ + +static struct symbol * +lookup_possible_namespace_symbol (const char *name, struct symtab **symtab) +{ + struct objfile *objfile; + + ALL_OBJFILES (objfile) + { + struct symbol *sym; + + sym = lookup_block_symbol (get_possible_namespace_block (objfile), + name, NULL, VAR_DOMAIN); + + if (sym != NULL) + { + if (symtab != NULL) + *symtab = objfile->cp_namespace_symtab; + + return sym; + } + } + + return NULL; +} + +/* Print out all the possible namespace symbols. */ + +static void +maintenance_cplus_namespace (char *args, int from_tty) +{ + struct objfile *objfile; + printf_unfiltered ("Possible namespaces:\n"); + ALL_OBJFILES (objfile) + { + struct dict_iterator iter; + struct symbol *sym; + + ALL_BLOCK_SYMBOLS (get_possible_namespace_block (objfile), iter, sym) + { + printf_unfiltered ("%s\n", SYMBOL_PRINT_NAME (sym)); + } + } +} + +void +_initialize_cp_namespace (void) +{ + add_cmd ("namespace", class_maintenance, maintenance_cplus_namespace, + "Print the list of possible C++ namespaces.", + &maint_cplus_cmd_list); +} diff --git a/gdb/dictionary.c b/gdb/dictionary.c new file mode 100644 index 0000000..3802000 --- /dev/null +++ b/gdb/dictionary.c @@ -0,0 +1,836 @@ +/* Routines for name->symbol lookups in GDB. + + Copyright 2003 Free Software Foundation, Inc. + + Contributed by David Carlton and by Kealia, + Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or (at + your option) any later version. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#include "defs.h" +#include "gdb_obstack.h" +#include "symtab.h" +#include "buildsym.h" +#include "gdb_assert.h" +#include "dictionary.h" + +/* This file implements dictionaries, which are tables that associate + symbols to names. They are represented by an opaque type 'struct + dictionary'. That type has various internal implementations, which + you can choose between depending on what properties you need + (e.g. fast lookup, order-preserving, expandable). + + Each dictionary starts with a 'virtual function table' that + contains the functions that actually implement the various + operations that dictionaries provide. (Note, however, that, for + the sake of client code, we also provide some functions that can be + implemented generically in terms of the functions in the vtable.) + + To add a new dictionary implementation , what you should do + is: + + * Add a new element DICT_ to dict_type. + + * Create a new structure dictionary_. If your new + implementation is a variant of an existing one, make sure that + their structs have the same initial data members. Define accessor + macros for your new data members. + + * Implement all the functions in dict_vector as static functions, + whose name is the same as the corresponding member of dict_vector + plus _. You don't have to do this for those members where + you can reuse existing generic functions + (e.g. add_symbol_nonexpandable, free_obstack) or in the case where + your new implementation is a variant of an existing implementation + and where the variant doesn't affect the member function in + question. + + * Define a static const struct dict_vector dict__vector. + + * Define a function dict_create_ to create these + gizmos. Add its declaration to dictionary.h. + + To add a new operation on all existing implementations, what + you should do is: + + * Add a new member to struct dict_vector. + + * If there is useful generic behavior , define a static + function _something_informative that implements that behavior. + (E.g. add_symbol_nonexpandable, free_obstack.) + + * For every implementation that should have its own specific + behavior for , define a static function _ + implementing it. + + * Modify all existing dict_vector_'s to include the appropriate + member. + + * Define a function dict_ that looks up in the dict_vector + and calls the appropriate function. Add a declaration for + dict_ to dictionary.h. + +*/ + +/* An enum representing the various implementations of dictionaries. + Used only for debugging. */ + +enum dict_type + { + /* Symbols are stored in a fixed-size hash table. */ + DICT_HASHED, + /* Symbols are stored in an expandable hash table. */ + DICT_HASHED_EXPANDABLE, + /* Symbols are stored in a fixed-size array. */ + DICT_LINEAR, + /* Symbols are stored in an expandable array. */ + DICT_LINEAR_EXPANDABLE, + }; + +/* The virtual function table. */ + +struct dict_vector +{ + /* The type of the dictionary. This is only here to make debugging + a bit easier; it's not actually used. */ + enum dict_type type; + /* The function to free a dictionary. */ + void (*free) (struct dictionary *dict); + /* Add a symbol to a dictionary, if possible. */ + void (*add_symbol) (struct dictionary *dict, struct symbol *sym); + /* Iterator functions. */ + struct symbol *(*iterator_first) (const struct dictionary *dict, + struct dict_iterator *iterator); + struct symbol *(*iterator_next) (struct dict_iterator *iterator); + /* Functions to iterate over symbols with a given name. */ + struct symbol *(*iter_name_first) (const struct dictionary *dict, + const char *name, + struct dict_iterator *iterator); + struct symbol *(*iter_name_next) (const char *name, + struct dict_iterator *iterator); + /* A size function, for maint print symtabs. */ + int (*size) (const struct dictionary *dict); +}; + +/* Now comes the structs used to store the data for different + implementations. If two implementations have data in common, put + the common data at the top of their structs, ordered in the same + way. */ + +struct dictionary_hashed +{ + int nbuckets; + struct symbol **buckets; +}; + +struct dictionary_hashed_expandable +{ + /* How many buckets we currently have. */ + int nbuckets; + struct symbol **buckets; + /* How many syms we currently have; we need this so we will know + when to add more buckets. */ + int nsyms; +}; + +struct dictionary_linear +{ + int nsyms; + struct symbol **syms; +}; + +struct dictionary_linear_expandable +{ + /* How many symbols we currently have. */ + int nsyms; + struct symbol **syms; + /* How many symbols we can store before needing to reallocate. */ + int capacity; +}; + +/* And now, the star of our show. */ + +struct dictionary +{ + const struct dict_vector *vector; + union + { + struct dictionary_hashed hashed; + struct dictionary_hashed_expandable hashed_expandable; + struct dictionary_linear linear; + struct dictionary_linear_expandable linear_expandable; + } + data; +}; + +/* Accessor macros. */ + +#define DICT_VECTOR(d) (d)->vector + +/* These can be used for DICT_HASHED_EXPANDABLE, too. */ + +#define DICT_HASHED_NBUCKETS(d) (d)->data.hashed.nbuckets +#define DICT_HASHED_BUCKETS(d) (d)->data.hashed.buckets +#define DICT_HASHED_BUCKET(d,i) DICT_HASHED_BUCKETS (d) [i] + +#define DICT_HASHED_EXPANDABLE_NSYMS(d) (d)->data.hashed_expandable.nsyms + +/* These can be used for DICT_LINEAR_EXPANDABLEs, too. */ + +#define DICT_LINEAR_NSYMS(d) (d)->data.linear.nsyms +#define DICT_LINEAR_SYMS(d) (d)->data.linear.syms +#define DICT_LINEAR_SYM(d,i) DICT_LINEAR_SYMS (d) [i] + +#define DICT_LINEAR_EXPANDABLE_CAPACITY(d) \ + (d)->data.linear_expandable.capacity + +/* The initial size of a DICT_*_EXPANDABLE dictionary. */ + +#define DICT_EXPANDABLE_INITIAL_CAPACITY 10 + +/* This calculates the number of buckets we'll use in a hashtable, + given the number of symbols that it will contain. */ + +#define DICT_HASHTABLE_SIZE(n) ((n)/5 + 1) + +/* Accessor macros for dict_iterators; they're here rather than + dictionary.h because code elsewhere should treat dict_iterators as + opaque. */ + +/* The dictionary that the iterator is associated to. */ +#define DICT_ITERATOR_DICT(iter) (iter)->dict +/* For linear dictionaries, the index of the last symbol returned; for + hashed dictionaries, the bucket of the last symbol returned. */ +#define DICT_ITERATOR_INDEX(iter) (iter)->index +/* For hashed dictionaries, this points to the last symbol returned; + otherwise, this is unused. */ +#define DICT_ITERATOR_CURRENT(iter) (iter)->current + +/* Declarations of functions for vectors. */ + +/* Functions that might work across a range of dictionary types. */ + +static void add_symbol_nonexpandable (struct dictionary *dict, + struct symbol *sym); + +static void free_obstack (struct dictionary *dict); + +/* Functions for DICT_HASHED and DICT_HASHED_EXPANDABLE + dictionaries. */ + +static struct symbol *iterator_first_hashed (const struct dictionary *dict, + struct dict_iterator *iterator); + +static struct symbol *iterator_next_hashed (struct dict_iterator *iterator); + +static struct symbol *iter_name_first_hashed (const struct dictionary *dict, + const char *name, + struct dict_iterator *iterator); + +static struct symbol *iter_name_next_hashed (const char *name, + struct dict_iterator *iterator); + +/* Functions only for DICT_HASHED. */ + +static int size_hashed (const struct dictionary *dict); + +/* Functions only for DICT_HASHED_EXPANDABLE. */ + +static void free_hashed_expandable (struct dictionary *dict); + +static void add_symbol_hashed_expandable (struct dictionary *dict, + struct symbol *sym); + +static int size_hashed_expandable (const struct dictionary *dict); + +/* Functions for DICT_LINEAR and DICT_LINEAR_EXPANDABLE + dictionaries. */ + +static struct symbol *iterator_first_linear (const struct dictionary *dict, + struct dict_iterator *iterator); + +static struct symbol *iterator_next_linear (struct dict_iterator *iterator); + +static struct symbol *iter_name_first_linear (const struct dictionary *dict, + const char *name, + struct dict_iterator *iterator); + +static struct symbol *iter_name_next_linear (const char *name, + struct dict_iterator *iterator); + +static int size_linear (const struct dictionary *dict); + +/* Functions only for DICT_LINEAR_EXPANDABLE. */ + +static void free_linear_expandable (struct dictionary *dict); + +static void add_symbol_linear_expandable (struct dictionary *dict, + struct symbol *sym); + +/* Various vectors that we'll actually use. */ + +static const struct dict_vector dict_hashed_vector = + { + DICT_HASHED, /* type */ + free_obstack, /* free */ + add_symbol_nonexpandable, /* add_symbol */ + iterator_first_hashed, /* iteractor_first */ + iterator_next_hashed, /* iterator_next */ + iter_name_first_hashed, /* iter_name_first */ + iter_name_next_hashed, /* iter_name_next */ + size_hashed, /* size */ + }; + +static const struct dict_vector dict_hashed_expandable_vector = + { + DICT_HASHED_EXPANDABLE, /* type */ + free_hashed_expandable, /* free */ + add_symbol_hashed_expandable, /* add_symbol */ + iterator_first_hashed, /* iteractor_first */ + iterator_next_hashed, /* iterator_next */ + iter_name_first_hashed, /* iter_name_first */ + iter_name_next_hashed, /* iter_name_next */ + size_hashed_expandable, /* size */ + }; + +static const struct dict_vector dict_linear_vector = + { + DICT_LINEAR, /* type */ + free_obstack, /* free */ + add_symbol_nonexpandable, /* add_symbol */ + iterator_first_linear, /* iteractor_first */ + iterator_next_linear, /* iterator_next */ + iter_name_first_linear, /* iter_name_first */ + iter_name_next_linear, /* iter_name_next */ + size_linear, /* size */ + }; + +static const struct dict_vector dict_linear_expandable_vector = + { + DICT_LINEAR_EXPANDABLE, /* type */ + free_linear_expandable, /* free */ + add_symbol_linear_expandable, /* add_symbol */ + iterator_first_linear, /* iteractor_first */ + iterator_next_linear, /* iterator_next */ + iter_name_first_linear, /* iter_name_first */ + iter_name_next_linear, /* iter_name_next */ + size_linear, /* size */ + }; + +/* Declarations of helper functions (i.e. ones that don't go into + vectors). */ + +static struct symbol *iterator_hashed_advance (struct dict_iterator *iter); + +static void insert_symbol_hashed (struct dictionary *dict, + struct symbol *sym); + +static void expand_hashtable (struct dictionary *dict); + +/* The creation functions. */ + +/* Create a dictionary implemented via a fixed-size hashtable. All + memory it uses is allocated on OBSTACK; the environment is + initialized from SYMBOL_LIST. */ + +struct dictionary * +dict_create_hashed (struct obstack *obstack, + const struct pending *symbol_list) +{ + struct dictionary *retval; + int nsyms = 0, nbuckets, i; + struct symbol **buckets; + const struct pending *list_counter; + + retval = obstack_alloc (obstack, sizeof (struct dictionary)); + DICT_VECTOR (retval) = &dict_hashed_vector; + + /* Calculate the number of symbols, and allocate space for them. */ + for (list_counter = symbol_list; + list_counter != NULL; + list_counter = list_counter->next) + { + nsyms += list_counter->nsyms; + } + nbuckets = DICT_HASHTABLE_SIZE (nsyms); + DICT_HASHED_NBUCKETS (retval) = nbuckets; + buckets = obstack_alloc (obstack, nbuckets * sizeof (struct symbol *)); + memset (buckets, 0, nbuckets * sizeof (struct symbol *)); + DICT_HASHED_BUCKETS (retval) = buckets; + + /* Now fill the buckets. */ + for (list_counter = symbol_list; + list_counter != NULL; + list_counter = list_counter->next) + { + for (i = list_counter->nsyms - 1; i >= 0; --i) + { + insert_symbol_hashed (retval, list_counter->symbol[i]); + } + } + + return retval; +} + +/* Create a dictionary implemented via a hashtable that grows as + necessary. The dictionary is initially empty; to add symbols to + it, call dict_add_symbol(). Call dict_free() when you're done with + it. */ + +extern struct dictionary * +dict_create_hashed_expandable (void) +{ + struct dictionary *retval; + + retval = xmalloc (sizeof (struct dictionary)); + DICT_VECTOR (retval) = &dict_hashed_expandable_vector; + DICT_HASHED_NBUCKETS (retval) = DICT_EXPANDABLE_INITIAL_CAPACITY; + DICT_HASHED_BUCKETS (retval) = xcalloc (DICT_EXPANDABLE_INITIAL_CAPACITY, + sizeof (struct symbol *)); + DICT_HASHED_EXPANDABLE_NSYMS (retval) = 0; + + return retval; +} + +/* Create a dictionary implemented via a fixed-size array. All memory + it uses is allocated on OBSTACK; the environment is initialized + from the SYMBOL_LIST. The symbols are ordered in the same order + that they're found in SYMBOL_LIST. */ + +struct dictionary * +dict_create_linear (struct obstack *obstack, + const struct pending *symbol_list) +{ + struct dictionary *retval; + int nsyms = 0, i, j; + struct symbol **syms; + const struct pending *list_counter; + + retval = obstack_alloc (obstack, sizeof (struct dictionary)); + DICT_VECTOR (retval) = &dict_linear_vector; + + /* Calculate the number of symbols, and allocate space for them. */ + for (list_counter = symbol_list; + list_counter != NULL; + list_counter = list_counter->next) + { + nsyms += list_counter->nsyms; + } + DICT_LINEAR_NSYMS (retval) = nsyms; + syms = obstack_alloc (obstack, nsyms * sizeof (struct symbol *)); + DICT_LINEAR_SYMS (retval) = syms; + + /* Now fill in the symbols. Start filling in from the back, so as + to preserve the original order of the symbols. */ + for (list_counter = symbol_list, j = nsyms - 1; + list_counter != NULL; + list_counter = list_counter->next) + { + for (i = list_counter->nsyms - 1; + i >= 0; + --i, --j) + { + syms[j] = list_counter->symbol[i]; + } + } + + return retval; +} + +/* Create a dictionary implemented via an array that grows as + necessary. The dictionary is initially empty; to add symbols to + it, call dict_add_symbol(). Call dict_free() when you're done with + it. */ + +struct dictionary * +dict_create_linear_expandable (void) +{ + struct dictionary *retval; + + retval = xmalloc (sizeof (struct dictionary)); + DICT_VECTOR (retval) = &dict_linear_expandable_vector; + DICT_LINEAR_NSYMS (retval) = 0; + DICT_LINEAR_EXPANDABLE_CAPACITY (retval) + = DICT_EXPANDABLE_INITIAL_CAPACITY; + DICT_LINEAR_SYMS (retval) + = xmalloc (DICT_LINEAR_EXPANDABLE_CAPACITY (retval) + * sizeof (struct symbol *)); + + return retval; +} + +/* The functions providing the dictionary interface. */ + +/* Free the memory used by a dictionary that's not on an obstack. (If + any.) */ + +void +dict_free (struct dictionary *dict) +{ + (DICT_VECTOR (dict))->free (dict); +} + +/* Add SYM to DICT. DICT had better be expandable. */ + +void +dict_add_symbol (struct dictionary *dict, struct symbol *sym) +{ + (DICT_VECTOR (dict))->add_symbol (dict, sym); +} + +/* Initialize ITERATOR to point at the first symbol in DICT, and + return that first symbol, or NULL if DICT is empty. */ + +struct symbol * +dict_iterator_first (const struct dictionary *dict, + struct dict_iterator *iterator) +{ + return (DICT_VECTOR (dict))->iterator_first (dict, iterator); +} + +/* Advance ITERATOR, and return the next symbol, or NULL if there are + no more symbols. */ + +struct symbol * +dict_iterator_next (struct dict_iterator *iterator) +{ + return (DICT_VECTOR (DICT_ITERATOR_DICT (iterator))) + ->iterator_next (iterator); +} + +struct symbol * +dict_iter_name_first (const struct dictionary *dict, + const char *name, + struct dict_iterator *iterator) +{ + return (DICT_VECTOR (dict))->iter_name_first (dict, name, iterator); +} + +struct symbol * +dict_iter_name_next (const char *name, struct dict_iterator *iterator) +{ + return (DICT_VECTOR (DICT_ITERATOR_DICT (iterator))) + ->iter_name_next (name, iterator); +} + +int +dict_size (const struct dictionary *dict) +{ + return (DICT_VECTOR (dict))->size (dict); +} + +/* Now come functions (well, one function, currently) that are + implemented generically by means of the vtable. Typically, they're + rarely used. */ + +/* Test to see if DICT is empty. */ + +int +dict_empty (struct dictionary *dict) +{ + struct dict_iterator iter; + + return (dict_iterator_first (dict, &iter) == NULL); +} + + +/* The functions implementing the dictionary interface. */ + +/* Generic functions, where appropriate. */ + +static void +free_obstack (struct dictionary *dict) +{ + /* Do nothing! */ +} + +static void +add_symbol_nonexpandable (struct dictionary *dict, struct symbol *sym) +{ + internal_error (__FILE__, __LINE__, + "dict_add_symbol: non-expandable dictionary"); +} + +/* Functions for DICT_HASHED and DICT_HASHED_EXPANDABLE. */ + +static struct symbol * +iterator_first_hashed (const struct dictionary *dict, + struct dict_iterator *iterator) +{ + DICT_ITERATOR_DICT (iterator) = dict; + DICT_ITERATOR_INDEX (iterator) = -1; + return iterator_hashed_advance (iterator); +} + +static struct symbol * +iterator_next_hashed (struct dict_iterator *iterator) +{ + const struct dictionary *dict = DICT_ITERATOR_DICT (iterator); + struct symbol *next; + + next = DICT_ITERATOR_CURRENT (iterator)->hash_next; + + if (next == NULL) + return iterator_hashed_advance (iterator); + else + { + DICT_ITERATOR_CURRENT (iterator) = next; + return next; + } +} + +static struct symbol * +iterator_hashed_advance (struct dict_iterator *iterator) +{ + const struct dictionary *dict = DICT_ITERATOR_DICT (iterator); + int nbuckets = DICT_HASHED_NBUCKETS (dict); + int i; + + for (i = DICT_ITERATOR_INDEX (iterator) + 1; i < nbuckets; ++i) + { + struct symbol *sym = DICT_HASHED_BUCKET (dict, i); + + if (sym != NULL) + { + DICT_ITERATOR_INDEX (iterator) = i; + DICT_ITERATOR_CURRENT (iterator) = sym; + return sym; + } + } + + return NULL; +} + +static struct symbol * +iter_name_first_hashed (const struct dictionary *dict, + const char *name, + struct dict_iterator *iterator) +{ + unsigned int hash_index + = msymbol_hash_iw (name) % DICT_HASHED_NBUCKETS (dict); + struct symbol *sym; + + DICT_ITERATOR_DICT (iterator) = dict; + + /* Loop through the symbols in the given bucket, breaking when SYM + first matches. If SYM never matches, it will be set to NULL; + either way, we have the right return value. */ + + for (sym = DICT_HASHED_BUCKET (dict, hash_index); + sym != NULL; + sym = sym->hash_next) + { + /* Warning: the order of arguments to strcmp_iw matters! */ + if (strcmp_iw (SYMBOL_NATURAL_NAME (sym), name) == 0) + { + break; + } + + } + + DICT_ITERATOR_CURRENT (iterator) = sym; + return sym; +} + +static struct symbol * +iter_name_next_hashed (const char *name, struct dict_iterator *iterator) +{ + struct symbol *next; + + for (next = DICT_ITERATOR_CURRENT (iterator)->hash_next; + next != NULL; + next = next->hash_next) + { + if (strcmp_iw (SYMBOL_NATURAL_NAME (next), name) == 0) + break; + } + + DICT_ITERATOR_CURRENT (iterator) = next; + + return next; +} + +/* Insert SYM into DICT. */ + +static void +insert_symbol_hashed (struct dictionary *dict, + struct symbol *sym) +{ + unsigned int hash_index; + struct symbol **buckets = DICT_HASHED_BUCKETS (dict); + + hash_index = (msymbol_hash_iw (SYMBOL_NATURAL_NAME (sym)) + % DICT_HASHED_NBUCKETS (dict)); + sym->hash_next = buckets[hash_index]; + buckets[hash_index] = sym; +} + +static int +size_hashed (const struct dictionary *dict) +{ + return DICT_HASHED_NBUCKETS (dict); +} + +/* Functions only for DICT_HASHED_EXPANDABLE. */ + +static void +free_hashed_expandable (struct dictionary *dict) +{ + xfree (DICT_HASHED_BUCKETS (dict)); + xfree (dict); +} + +static void +add_symbol_hashed_expandable (struct dictionary *dict, + struct symbol *sym) +{ + int nsyms = ++DICT_HASHED_EXPANDABLE_NSYMS (dict); + + if (DICT_HASHTABLE_SIZE (nsyms) > DICT_HASHED_NBUCKETS (dict)) + expand_hashtable (dict); + + insert_symbol_hashed (dict, sym); + DICT_HASHED_EXPANDABLE_NSYMS (dict) = nsyms; +} + +static int +size_hashed_expandable (const struct dictionary *dict) +{ + return DICT_HASHED_EXPANDABLE_NSYMS (dict); +} + +static void +expand_hashtable (struct dictionary *dict) +{ + int old_nbuckets = DICT_HASHED_NBUCKETS (dict); + struct symbol **old_buckets = DICT_HASHED_BUCKETS (dict); + int new_nbuckets = 2*old_nbuckets + 1; + struct symbol **new_buckets = xcalloc (new_nbuckets, + sizeof (struct symbol *)); + int i; + + DICT_HASHED_NBUCKETS (dict) = new_nbuckets; + DICT_HASHED_BUCKETS (dict) = new_buckets; + + for (i = 0; i < old_nbuckets; ++i) { + struct symbol *sym, *next_sym; + + sym = old_buckets[i]; + if (sym != NULL) { + for (next_sym = sym->hash_next; + next_sym != NULL; + next_sym = sym->hash_next) { + insert_symbol_hashed (dict, sym); + sym = next_sym; + } + + insert_symbol_hashed (dict, sym); + } + } + + xfree (old_buckets); +} + +/* Functions for DICT_LINEAR and DICT_LINEAR_EXPANDABLE. */ + +static struct symbol * +iterator_first_linear (const struct dictionary *dict, + struct dict_iterator *iterator) +{ + DICT_ITERATOR_DICT (iterator) = dict; + DICT_ITERATOR_INDEX (iterator) = 0; + return DICT_LINEAR_NSYMS (dict) ? DICT_LINEAR_SYM (dict, 0) : NULL; +} + +static struct symbol * +iterator_next_linear (struct dict_iterator *iterator) +{ + const struct dictionary *dict = DICT_ITERATOR_DICT (iterator); + + if (++DICT_ITERATOR_INDEX (iterator) >= DICT_LINEAR_NSYMS (dict)) + return NULL; + else + return DICT_LINEAR_SYM (dict, DICT_ITERATOR_INDEX (iterator)); +} + +static struct symbol * +iter_name_first_linear (const struct dictionary *dict, + const char *name, + struct dict_iterator *iterator) +{ + DICT_ITERATOR_DICT (iterator) = dict; + DICT_ITERATOR_INDEX (iterator) = -1; + + return iter_name_next_linear (name, iterator); +} + +static struct symbol * +iter_name_next_linear (const char *name, struct dict_iterator *iterator) +{ + const struct dictionary *dict = DICT_ITERATOR_DICT (iterator); + int i, nsyms = DICT_LINEAR_NSYMS (dict); + struct symbol *sym, *retval = NULL; + + for (i = DICT_ITERATOR_INDEX (iterator) + 1; i < nsyms; ++i) + { + sym = DICT_LINEAR_SYM (dict, i); + if (strcmp_iw (SYMBOL_NATURAL_NAME (sym), name) == 0) + { + retval = sym; + break; + } + } + + DICT_ITERATOR_INDEX (iterator) = i; + + return retval; +} + +static int +size_linear (const struct dictionary *dict) +{ + return DICT_LINEAR_NSYMS (dict); +} + +/* Functions only for DICT_LINEAR_EXPANDABLE. */ + +static void +free_linear_expandable (struct dictionary *dict) +{ + xfree (DICT_LINEAR_SYMS (dict)); + xfree (dict); +} + + +static void +add_symbol_linear_expandable (struct dictionary *dict, + struct symbol *sym) +{ + int nsyms = ++DICT_LINEAR_NSYMS (dict); + + /* Do we have enough room? If not, grow it. */ + if (nsyms > DICT_LINEAR_EXPANDABLE_CAPACITY (dict)) { + DICT_LINEAR_EXPANDABLE_CAPACITY (dict) *= 2; + DICT_LINEAR_SYMS (dict) + = xrealloc (DICT_LINEAR_SYMS (dict), + DICT_LINEAR_EXPANDABLE_CAPACITY (dict) + * sizeof (struct symbol *)); + } + + DICT_LINEAR_SYM (dict, nsyms - 1) = sym; +} diff --git a/gdb/dictionary.h b/gdb/dictionary.h new file mode 100644 index 0000000..75edd7f --- /dev/null +++ b/gdb/dictionary.h @@ -0,0 +1,156 @@ +/* Routines for name->symbol lookups in GDB. + + Copyright 2003 Free Software Foundation, Inc. + + Contributed by David Carlton and by Kealia, + Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or (at + your option) any later version. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#ifndef DICTIONARY_H +#define DICTIONARY_H + +/* An opaque type for dictionaries; only dictionary.c should know + about its innards. */ + +struct dictionary; + +/* Other types needed for declarations. */ + +struct symbol; +struct obstack; +struct pending; + + +/* The creation functions for various implementations of + dictionaries. */ + +/* Create a dictionary implemented via a fixed-size hashtable. All + memory it uses is allocated on OBSTACK; the environment is + initialized from SYMBOL_LIST. */ + +extern struct dictionary *dict_create_hashed (struct obstack *obstack, + const struct pending + *symbol_list); + +/* Create a dictionary implemented via a hashtable that grows as + necessary. The dictionary is initially empty; to add symbols to + it, call dict_add_symbol(). Call dict_free() when you're done with + it. */ + +extern struct dictionary *dict_create_hashed_expandable (void); + +/* Create a dictionary implemented via a fixed-size array. All memory + it uses is allocated on OBSTACK; the environment is initialized + from the SYMBOL_LIST. The symbols are ordered in the same order + that they're found in SYMBOL_LIST. */ + +extern struct dictionary *dict_create_linear (struct obstack *obstack, + const struct pending + *symbol_list); + +/* Create a dictionary implemented via an array that grows as + necessary. The dictionary is initially empty; to add symbols to + it, call dict_add_symbol(). Call dict_free() when you're done with + it. */ + +extern struct dictionary *dict_create_linear_expandable (void); + + +/* The functions providing the interface to dictionaries. Note that + the most common parts of the interface, namely symbol lookup, are + only provided via iterator functions. */ + +/* Free the memory used by a dictionary that's not on an obstack. (If + any.) */ + +extern void dict_free (struct dictionary *dict); + +/* Add a symbol to an expandable dictionary. */ + +extern void dict_add_symbol (struct dictionary *dict, struct symbol *sym); + +/* Is the dictionary empty? */ + +extern int dict_empty (struct dictionary *dict); + +/* A type containing data that is used when iterating over all symbols + in a dictionary. Don't ever look at its innards; this type would + be opaque if we didn't need to be able to allocate it on the + stack. */ + +struct dict_iterator +{ + /* The dictionary that this iterator is associated to. */ + const struct dictionary *dict; + /* The next two members are data that is used in a way that depends + on DICT's implementation type. */ + int index; + struct symbol *current; +}; + +/* Initialize ITERATOR to point at the first symbol in DICT, and + return that first symbol, or NULL if DICT is empty. */ + +extern struct symbol *dict_iterator_first (const struct dictionary *dict, + struct dict_iterator *iterator); + +/* Advance ITERATOR, and return the next symbol, or NULL if there are + no more symbols. Don't call this if you've previously received + NULL from dict_iterator_first or dict_iterator_next on this + iteration. */ + +extern struct symbol *dict_iterator_next (struct dict_iterator *iterator); + +/* Initialize ITERATOR to point at the first symbol in DICT whose + SYMBOL_BEST_NAME is NAME (as tested using strcmp_iw), and return + that first symbol, or NULL if there are no such symbols. */ + +extern struct symbol *dict_iter_name_first (const struct dictionary *dict, + const char *name, + struct dict_iterator *iterator); + +/* Advance ITERATOR to point at the next symbol in DICT whose + SYMBOL_BEST_NAME is NAME (as tested using strcmp_iw), or NULL if + there are no more such symbols. Don't call this if you've + previously received NULL from dict_iterator_first or + dict_iterator_next on this iteration. And don't call it unless + ITERATOR was created by a previous call to dict_iter_name_first + with the same NAME. */ + +extern struct symbol *dict_iter_name_next (const char *name, + struct dict_iterator *iterator); + +/* Return some notion of the size of the dictionary: the number of + symbols if we have that, the number of hash buckets otherwise. */ + +extern int dict_size (const struct dictionary *dict); + +/* Macro to loop through all symbols in a dictionary DICT, in no + particular order. ITER is a struct dict_iterator (NOTE: __not__ a + struct dict_iterator *), and SYM points to the current symbol. + + It's implemented as a single loop, so you can terminate the loop + early by a break if you desire. */ + +#define ALL_DICT_SYMBOLS(dict, iter, sym) \ + for ((sym) = dict_iterator_first ((dict), &(iter)); \ + (sym); \ + (sym) = dict_iterator_next (&(iter))) + +#endif /* DICTIONARY_H */ diff --git a/gdb/doc/annotate.texinfo b/gdb/doc/annotate.texinfo new file mode 100644 index 0000000..901c6e1 --- /dev/null +++ b/gdb/doc/annotate.texinfo @@ -0,0 +1,832 @@ +\input texinfo @c -*-texinfo-*- +@c %**start of header +@setfilename annotate.info + +@c This is a dir.info fragment to support semi-automated addition of +@c manuals to an info tree. +@dircategory Programming & development tools. +@direntry +* Annotate: (annotate). The obsolete annotation interface. +@end direntry + +@c +@include gdb-cfg.texi +@c +@settitle @value{GDBN}'s Obsolete Annotations +@setchapternewpage off +@c %**end of header + +@set EDITION 1.0 +@set DATE July 2003 + +@c NOTE: cagney/2003-07-28: +@c Don't make this migration doccument an appendix of GDB's user guide. +@c By keeping this separate, the size of the user guide is contained. If +@c the user guide to get much bigger it would need to switch to a larger, +@c more expensive, form factor and would drive up the manuals publication +@c cost. Having a smaller cheaper manual helps the GNU Press with its sales. + +@ifinfo +This file documents @value{GDBN}'s obsolete annotations. + +Copyright 1994, 1995, 2000, 2001, 2003 Free Software Foundation, Inc. + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License, Version 1.1 or +any later version published by the Free Software Foundation; with no +Invariant Sections, with no Front-Cover Texts, and with no Back-Cover +Texts. A copy of the license is included in the section entitled ``GNU +Free Documentation License''. + +@end ifinfo + +@titlepage +@title @value{GDBN}'s Obsolete Annotations +@subtitle Edition @value{EDITION} +@subtitle @value{DATE} +@author Free Software Foundation +@page +@vskip 0pt plus 1filll +Copyright @copyright{} 1994, 1995, 2000, 2001, 2003 Free Software +Foundation, Inc. + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License, Version 1.1 or +any later version published by the Free Software Foundation; with no +Invariant Sections, with no Front-Cover Texts, and with no Back-Cover +Texts. A copy of the license is included in the section entitled ``GNU +Free Documentation License''. +@end titlepage + +@ifinfo +@node Top +@top GDB Annotations + +This document describes the obsolete level two annotation interface +implemented in older @value{GDBN} versions. + +@ignore +This is Edition @value{EDITION}, @value{DATE}. +@end ignore +@end ifinfo + +@menu +* Annotations Overview:: What annotations are; the general syntax. +* Limitations:: Limitations of the annotation interface. +* Migrating to GDB/MI:: Migrating to GDB/MI +* Server Prefix:: Issuing a command without affecting user state. +* Value Annotations:: Values are marked as such. +* Frame Annotations:: Stack frames are annotated. +* Displays:: @value{GDBN} can be told to display something periodically. +* Prompting:: Annotations marking @value{GDBN}'s need for input. +* Errors:: Annotations for error messages. +* Breakpoint Info:: Information on breakpoints. +* Invalidation:: Some annotations describe things now invalid. +* Annotations for Running:: + Whether the program is running, how it stopped, etc. +* Source Annotations:: Annotations describing source code. + +* GNU Free Documentation License:: +@end menu + +@contents + +@node Annotations Overview +@chapter What is an Annotation? +@cindex annotations + +To produce obsolete level two annotations, start @value{GDBN} with the +@code{--annotate=2} option. + +Annotations start with a newline character, two @samp{control-z} +characters, and the name of the annotation. If there is no additional +information associated with this annotation, the name of the annotation +is followed immediately by a newline. If there is additional +information, the name of the annotation is followed by a space, the +additional information, and a newline. The additional information +cannot contain newline characters. + +Any output not beginning with a newline and two @samp{control-z} +characters denotes literal output from @value{GDBN}. Currently there is +no need for @value{GDBN} to output a newline followed by two +@samp{control-z} characters, but if there was such a need, the +annotations could be extended with an @samp{escape} annotation which +means those three characters as output. + +A simple example of starting up @value{GDBN} with annotations is: + +@smallexample +$ gdb --annotate=2 +GNU GDB 5.0 +Copyright 2000 Free Software Foundation, Inc. +GDB is free software, covered by the GNU General Public License, +and you are welcome to change it and/or distribute copies of it +under certain conditions. +Type "show copying" to see the conditions. +There is absolutely no warranty for GDB. Type "show warranty" +for details. +This GDB was configured as "sparc-sun-sunos4.1.3" + +^Z^Zpre-prompt +(gdb) +^Z^Zprompt +quit + +^Z^Zpost-prompt +$ +@end smallexample + +Here @samp{quit} is input to @value{GDBN}; the rest is output from +@value{GDBN}. The three lines beginning @samp{^Z^Z} (where @samp{^Z} +denotes a @samp{control-z} character) are annotations; the rest is +output from @value{GDBN}. + +@node Limitations +@chapter Limitations of the Annotation Interface + +The level two annotations mechanism is known to have a number of +technical and architectural limitations. As a consequence, in 2001, +with the release of @value{GDBN} 5.1 and the addition of @sc{gdb/mi}, +the annotation interface was marked as deprecated. + +This chapter discusses the known problems. + +@section Dependant on @sc{cli} output + +The annotation interface works by interspersing markups with +@value{GDBN} normal command-line interpreter output. Unfortunately, this +makes the annotation client dependant on not just the annotations, but +also the @sc{cli} output. This is because the client is forced to +assume that specific @value{GDBN} commands provide specific information. +Any change to @value{GDBN}'s @sc{cli} output modifies or removes that +information and, consequently, likely breaks the client. + +Since the @sc{gdb/mi} output is independant of the @sc{cli}, it does not +have this problem. + +@section Scalability + +The annotation interface relies on value annotations (@pxref{Value +Annotations}) and the display mechanism as a way of obtaining up-to-date +value information. These mechanisms are not scalable. + +In a graphical environment, where many values can be displayed +simultaneously, a serious performance problem occurs when the client +tries to first extract from @value{GDBN}, and then re-display, all those +values. The client should instead only request and update the values +that changed. + +The @sc{gdb/mi} Variable Objects provide just that mechanism. + +@section Correctness + +The annotation interface assumes that a variable's value can only be +changed when the target is running. This assumption is not correct. A +single assignment to a single variable can result in the entire target, +and all displayed values, needing an update. + +The @sc{gdb/mi} Variable Objects include a mechanism for efficiently +reporting such changes. + +@section Reliability + +The @sc{gdb/mi} interface includes a dedicated test directory +(@file{gdb/gdb.mi}), and any addition or fix to @sc{gdb/mi} must include +testsuite changes. + +@section Maintainability + +The annotation mechanism was implemented by interspersing @sc{cli} print +statements with various annotations. As a consequence, any @sc{cli} +output change can alter the annotation output. + +Since the @sc{gdb/mi} output is independant of the @sc{cli}, and the +@sc{gdb/mi} is increasingly implemented independant of the @sc{cli} +code, its long term maintenance is much easier. + +@node Migrating to GDB/MI +@chapter Migrating to @sc{gdb/mi} + +By using the @samp{interp mi} command, it is possible for annotation +clients to invoke @sc{gdb/mi} commands, and hence access the +@sc{gdb/mi}. By doing this, existing annotation clients have a +migration path from this obsolete interface to @sc{gdb/mi}. + +@node Server Prefix +@chapter The Server Prefix +@cindex server prefix for annotations + +To issue a command to @value{GDBN} without affecting certain aspects of +the state which is seen by users, prefix it with @samp{server }. This +means that this command will not affect the command history, nor will it +affect @value{GDBN}'s notion of which command to repeat if @key{RET} is +pressed on a line by itself. + +The server prefix does not affect the recording of values into the value +history; to print a value without recording it into the value history, +use the @code{output} command instead of the @code{print} command. + +@node Value Annotations +@chapter Values + +@emph{Value Annotations have been removed. @sc{gdb/mi} instead provides +Variable Objects.} + +@cindex annotations for values +When a value is printed in various contexts, @value{GDBN} uses +annotations to delimit the value from the surrounding text. + +@findex value-history-begin +@findex value-history-value +@findex value-history-end +If a value is printed using @code{print} and added to the value history, +the annotation looks like + +@smallexample +^Z^Zvalue-history-begin @var{history-number} @var{value-flags} +@var{history-string} +^Z^Zvalue-history-value +@var{the-value} +^Z^Zvalue-history-end +@end smallexample + +@noindent +where @var{history-number} is the number it is getting in the value +history, @var{history-string} is a string, such as @samp{$5 = }, which +introduces the value to the user, @var{the-value} is the output +corresponding to the value itself, and @var{value-flags} is @samp{*} for +a value which can be dereferenced and @samp{-} for a value which cannot. + +@findex value-begin +@findex value-end +If the value is not added to the value history (it is an invalid float +or it is printed with the @code{output} command), the annotation is similar: + +@smallexample +^Z^Zvalue-begin @var{value-flags} +@var{the-value} +^Z^Zvalue-end +@end smallexample + +@findex arg-begin +@findex arg-name-end +@findex arg-value +@findex arg-end +When @value{GDBN} prints an argument to a function (for example, in the output +from the @code{backtrace} command), it annotates it as follows: + +@smallexample +^Z^Zarg-begin +@var{argument-name} +^Z^Zarg-name-end +@var{separator-string} +^Z^Zarg-value @var{value-flags} +@var{the-value} +^Z^Zarg-end +@end smallexample + +@noindent +where @var{argument-name} is the name of the argument, +@var{separator-string} is text which separates the name from the value +for the user's benefit (such as @samp{=}), and @var{value-flags} and +@var{the-value} have the same meanings as in a +@code{value-history-begin} annotation. + +@findex field-begin +@findex field-name-end +@findex field-value +@findex field-end +When printing a structure, @value{GDBN} annotates it as follows: + +@smallexample +^Z^Zfield-begin @var{value-flags} +@var{field-name} +^Z^Zfield-name-end +@var{separator-string} +^Z^Zfield-value +@var{the-value} +^Z^Zfield-end +@end smallexample + +@noindent +where @var{field-name} is the name of the field, @var{separator-string} +is text which separates the name from the value for the user's benefit +(such as @samp{=}), and @var{value-flags} and @var{the-value} have the +same meanings as in a @code{value-history-begin} annotation. + +When printing an array, @value{GDBN} annotates it as follows: + +@smallexample +^Z^Zarray-section-begin @var{array-index} @var{value-flags} +@end smallexample + +@noindent +where @var{array-index} is the index of the first element being +annotated and @var{value-flags} has the same meaning as in a +@code{value-history-begin} annotation. This is followed by any number +of elements, where is element can be either a single element: + +@findex elt +@smallexample +@samp{,} @var{whitespace} ; @r{omitted for the first element} +@var{the-value} +^Z^Zelt +@end smallexample + +or a repeated element + +@findex elt-rep +@findex elt-rep-end +@smallexample +@samp{,} @var{whitespace} ; @r{omitted for the first element} +@var{the-value} +^Z^Zelt-rep @var{number-of-repetitions} +@var{repetition-string} +^Z^Zelt-rep-end +@end smallexample + +In both cases, @var{the-value} is the output for the value of the +element and @var{whitespace} can contain spaces, tabs, and newlines. In +the repeated case, @var{number-of-repetitions} is the number of +consecutive array elements which contain that value, and +@var{repetition-string} is a string which is designed to convey to the +user that repetition is being depicted. + +@findex array-section-end +Once all the array elements have been output, the array annotation is +ended with + +@smallexample +^Z^Zarray-section-end +@end smallexample + +@node Frame Annotations +@chapter Frames + +@emph{Value Annotations have been removed. @sc{gdb/mi} instead provides +a number of frame commands.} + +@emph{Frame annotations are no longer available. The @sc{gdb/mi} +provides @samp{-stack-list-arguments}, @samp{-stack-list-locals}, and +@samp{-stack-list-frames} commands.} + +@cindex annotations for frames +Whenever @value{GDBN} prints a frame, it annotates it. For example, this applies +to frames printed when @value{GDBN} stops, output from commands such as +@code{backtrace} or @code{up}, etc. + +@findex frame-begin +The frame annotation begins with + +@smallexample +^Z^Zframe-begin @var{level} @var{address} +@var{level-string} +@end smallexample + +@noindent +where @var{level} is the number of the frame (0 is the innermost frame, +and other frames have positive numbers), @var{address} is the address of +the code executing in that frame, and @var{level-string} is a string +designed to convey the level to the user. @var{address} is in the form +@samp{0x} followed by one or more lowercase hex digits (note that this +does not depend on the language). The frame ends with + +@findex frame-end +@smallexample +^Z^Zframe-end +@end smallexample + +Between these annotations is the main body of the frame, which can +consist of + +@itemize @bullet +@item +@findex function-call +@smallexample +^Z^Zfunction-call +@var{function-call-string} +@end smallexample + +where @var{function-call-string} is text designed to convey to the user +that this frame is associated with a function call made by @value{GDBN} to a +function in the program being debugged. + +@item +@findex signal-handler-caller +@smallexample +^Z^Zsignal-handler-caller +@var{signal-handler-caller-string} +@end smallexample + +where @var{signal-handler-caller-string} is text designed to convey to +the user that this frame is associated with whatever mechanism is used +by this operating system to call a signal handler (it is the frame which +calls the signal handler, not the frame for the signal handler itself). + +@item +A normal frame. + +@findex frame-address +@findex frame-address-end +This can optionally (depending on whether this is thought of as +interesting information for the user to see) begin with + +@smallexample +^Z^Zframe-address +@var{address} +^Z^Zframe-address-end +@var{separator-string} +@end smallexample + +where @var{address} is the address executing in the frame (the same +address as in the @code{frame-begin} annotation, but printed in a form +which is intended for user consumption---in particular, the syntax varies +depending on the language), and @var{separator-string} is a string +intended to separate this address from what follows for the user's +benefit. + +@findex frame-function-name +@findex frame-args +Then comes + +@smallexample +^Z^Zframe-function-name +@var{function-name} +^Z^Zframe-args +@var{arguments} +@end smallexample + +where @var{function-name} is the name of the function executing in the +frame, or @samp{??} if not known, and @var{arguments} are the arguments +to the frame, with parentheses around them (each argument is annotated +individually as well, @pxref{Value Annotations}). + +@findex frame-source-begin +@findex frame-source-file +@findex frame-source-file-end +@findex frame-source-line +@findex frame-source-end +If source information is available, a reference to it is then printed: + +@smallexample +^Z^Zframe-source-begin +@var{source-intro-string} +^Z^Zframe-source-file +@var{filename} +^Z^Zframe-source-file-end +: +^Z^Zframe-source-line +@var{line-number} +^Z^Zframe-source-end +@end smallexample + +where @var{source-intro-string} separates for the user's benefit the +reference from the text which precedes it, @var{filename} is the name of +the source file, and @var{line-number} is the line number within that +file (the first line is line 1). + +@findex frame-where +If @value{GDBN} prints some information about where the frame is from (which +library, which load segment, etc.; currently only done on the RS/6000), +it is annotated with + +@smallexample +^Z^Zframe-where +@var{information} +@end smallexample + +Then, if source is to actually be displayed for this frame (for example, +this is not true for output from the @code{backtrace} command), then a +@code{source} annotation (@pxref{Source Annotations}) is displayed. Unlike +most annotations, this is output instead of the normal text which would be +output, not in addition. +@end itemize + +@node Displays +@chapter Displays + +@emph{Display Annotations have been removed. @sc{gdb/mi} instead +provides Variable Objects.} + +@findex display-begin +@findex display-number-end +@findex display-format +@findex display-expression +@findex display-expression-end +@findex display-value +@findex display-end +@cindex annotations for display +When @value{GDBN} is told to display something using the @code{display} command, +the results of the display are annotated: + +@smallexample +^Z^Zdisplay-begin +@var{number} +^Z^Zdisplay-number-end +@var{number-separator} +^Z^Zdisplay-format +@var{format} +^Z^Zdisplay-expression +@var{expression} +^Z^Zdisplay-expression-end +@var{expression-separator} +^Z^Zdisplay-value +@var{value} +^Z^Zdisplay-end +@end smallexample + +@noindent +where @var{number} is the number of the display, @var{number-separator} +is intended to separate the number from what follows for the user, +@var{format} includes information such as the size, format, or other +information about how the value is being displayed, @var{expression} is +the expression being displayed, @var{expression-separator} is intended +to separate the expression from the text that follows for the user, +and @var{value} is the actual value being displayed. + +@node Prompting +@chapter Annotation for @value{GDBN} Input + +@cindex annotations for prompts +When @value{GDBN} prompts for input, it annotates this fact so it is possible +to know when to send output, when the output from a given command is +over, etc. + +Different kinds of input each have a different @dfn{input type}. Each +input type has three annotations: a @code{pre-} annotation, which +denotes the beginning of any prompt which is being output, a plain +annotation, which denotes the end of the prompt, and then a @code{post-} +annotation which denotes the end of any echo which may (or may not) be +associated with the input. For example, the @code{prompt} input type +features the following annotations: + +@smallexample +^Z^Zpre-prompt +^Z^Zprompt +^Z^Zpost-prompt +@end smallexample + +The input types are + +@table @code +@findex pre-prompt +@findex prompt +@findex post-prompt +@item prompt +When @value{GDBN} is prompting for a command (the main @value{GDBN} prompt). + +@findex pre-commands +@findex commands +@findex post-commands +@item commands +When @value{GDBN} prompts for a set of commands, like in the @code{commands} +command. The annotations are repeated for each command which is input. + +@findex pre-overload-choice +@findex overload-choice +@findex post-overload-choice +@item overload-choice +When @value{GDBN} wants the user to select between various overloaded functions. + +@findex pre-query +@findex query +@findex post-query +@item query +When @value{GDBN} wants the user to confirm a potentially dangerous operation. + +@findex pre-prompt-for-continue +@findex prompt-for-continue +@findex post-prompt-for-continue +@item prompt-for-continue +When @value{GDBN} is asking the user to press return to continue. Note: Don't +expect this to work well; instead use @code{set height 0} to disable +prompting. This is because the counting of lines is buggy in the +presence of annotations. +@end table + +@node Errors +@chapter Errors +@cindex annotations for errors, warnings and interrupts + +@findex quit +@smallexample +^Z^Zquit +@end smallexample + +This annotation occurs right before @value{GDBN} responds to an interrupt. + +@findex error +@smallexample +^Z^Zerror +@end smallexample + +This annotation occurs right before @value{GDBN} responds to an error. + +Quit and error annotations indicate that any annotations which @value{GDBN} was +in the middle of may end abruptly. For example, if a +@code{value-history-begin} annotation is followed by a @code{error}, one +cannot expect to receive the matching @code{value-history-end}. One +cannot expect not to receive it either, however; an error annotation +does not necessarily mean that @value{GDBN} is immediately returning all the way +to the top level. + +@findex error-begin +A quit or error annotation may be preceded by + +@smallexample +^Z^Zerror-begin +@end smallexample + +Any output between that and the quit or error annotation is the error +message. + +Warning messages are not yet annotated. +@c If we want to change that, need to fix warning(), type_error(), +@c range_error(), and possibly other places. + +@node Breakpoint Info +@chapter Information on Breakpoints + +@emph{Breakpoint Annotations have been removed. @sc{gdb/mi} instead +provides breakpoint commands.} + +@cindex annotations for breakpoints +The output from the @code{info breakpoints} command is annotated as follows: + +@findex breakpoints-headers +@findex breakpoints-table +@smallexample +^Z^Zbreakpoints-headers +@var{header-entry} +^Z^Zbreakpoints-table +@end smallexample + +@noindent +where @var{header-entry} has the same syntax as an entry (see below) but +instead of containing data, it contains strings which are intended to +convey the meaning of each field to the user. This is followed by any +number of entries. If a field does not apply for this entry, it is +omitted. Fields may contain trailing whitespace. Each entry consists +of: + +@findex record +@findex field +@smallexample +^Z^Zrecord +^Z^Zfield 0 +@var{number} +^Z^Zfield 1 +@var{type} +^Z^Zfield 2 +@var{disposition} +^Z^Zfield 3 +@var{enable} +^Z^Zfield 4 +@var{address} +^Z^Zfield 5 +@var{what} +^Z^Zfield 6 +@var{frame} +^Z^Zfield 7 +@var{condition} +^Z^Zfield 8 +@var{ignore-count} +^Z^Zfield 9 +@var{commands} +@end smallexample + +Note that @var{address} is intended for user consumption---the syntax +varies depending on the language. + +The output ends with + +@findex breakpoints-table-end +@smallexample +^Z^Zbreakpoints-table-end +@end smallexample + +@node Invalidation +@chapter Invalidation Notices + +@cindex annotations for invalidation messages +The following annotations say that certain pieces of state may have +changed. + +@table @code +@findex frames-invalid +@item ^Z^Zframes-invalid + +The frames (for example, output from the @code{backtrace} command) may +have changed. + +@findex breakpoints-invalid +@item ^Z^Zbreakpoints-invalid + +The breakpoints may have changed. For example, the user just added or +deleted a breakpoint. +@end table + +@node Annotations for Running +@chapter Running the Program +@cindex annotations for running programs + +@findex starting +@findex stopping +When the program starts executing due to a @value{GDBN} command such as +@code{step} or @code{continue}, + +@smallexample +^Z^Zstarting +@end smallexample + +is output. When the program stops, + +@smallexample +^Z^Zstopped +@end smallexample + +is output. Before the @code{stopped} annotation, a variety of +annotations describe how the program stopped. + +@table @code +@findex exited +@item ^Z^Zexited @var{exit-status} +The program exited, and @var{exit-status} is the exit status (zero for +successful exit, otherwise nonzero). + +@findex signalled +@findex signal-name +@findex signal-name-end +@findex signal-string +@findex signal-string-end +@item ^Z^Zsignalled +The program exited with a signal. After the @code{^Z^Zsignalled}, the +annotation continues: + +@smallexample +@var{intro-text} +^Z^Zsignal-name +@var{name} +^Z^Zsignal-name-end +@var{middle-text} +^Z^Zsignal-string +@var{string} +^Z^Zsignal-string-end +@var{end-text} +@end smallexample + +@noindent +where @var{name} is the name of the signal, such as @code{SIGILL} or +@code{SIGSEGV}, and @var{string} is the explanation of the signal, such +as @code{Illegal Instruction} or @code{Segmentation fault}. +@var{intro-text}, @var{middle-text}, and @var{end-text} are for the +user's benefit and have no particular format. + +@findex signal +@item ^Z^Zsignal +The syntax of this annotation is just like @code{signalled}, but @value{GDBN} is +just saying that the program received the signal, not that it was +terminated with it. + +@findex breakpoint +@item ^Z^Zbreakpoint @var{number} +The program hit breakpoint number @var{number}. + +@findex watchpoint +@item ^Z^Zwatchpoint @var{number} +The program hit watchpoint number @var{number}. +@end table + +@node Source Annotations +@chapter Displaying Source +@cindex annotations for source display + +@findex source +The following annotation is used instead of displaying source code: + +@smallexample +^Z^Zsource @var{filename}:@var{line}:@var{character}:@var{middle}:@var{addr} +@end smallexample + +where @var{filename} is an absolute file name indicating which source +file, @var{line} is the line number within that file (where 1 is the +first line in the file), @var{character} is the character position +within the file (where 0 is the first character in the file) (for most +debug formats this will necessarily point to the beginning of a line), +@var{middle} is @samp{middle} if @var{addr} is in the middle of the +line, or @samp{beg} if @var{addr} is at the beginning of the line, and +@var{addr} is the address in the target program associated with the +source which is being displayed. @var{addr} is in the form @samp{0x} +followed by one or more lowercase hex digits (note that this does not +depend on the language). + +@include fdl.texi + +@ignore +@node Index +@unnumbered Index + +@printindex fn +@end ignore + +@bye diff --git a/gdb/doc/observer.texi b/gdb/doc/observer.texi new file mode 100644 index 0000000..de48a19 --- /dev/null +++ b/gdb/doc/observer.texi @@ -0,0 +1,70 @@ +@c -*-texinfo-*- +@node GDB Observers +@appendix @value{GDBN} Currently available observers + +@section Implementation rationale +@cindex observers implementation rationale + +An @dfn{observer} is an entity which is interested in being notified +when GDB reaches certain states, or certain events occur in GDB. +The entity being observed is called the @dfn{subject}. To receive +notifications, the observer attaches a callback to the subject. +One subject can have several observers. + +@file{observer.c} implements an internal generic low-level event +notification mechanism. This generic event notification mechanism is +then re-used to implement the exported high-level notification +management routines for all possible notifications. + +The current implementation of the generic observer provides support +for contextual data. This contextual data is given to the subject +when attaching the callback. In return, the subject will provide +this contextual data back to the observer as a parameter of the +callback. + +Note that the current support for the contextual data is only partial, +as it lacks a mechanism that would deallocate this data when the +callback is detached. This is not a problem so far, as this contextual +data is only used internally to hold a function pointer. Later on, if +a certain observer needs to provide support for user-level contextual +data, then the generic notification mechanism will need to be +enhanced to allow the observer to provide a routine to deallocate the +data when attaching the callback. + +The observer implementation is also currently not reentrant. +In particular, it is therefore not possible to call the attach +or detach routines during a notification. + +@section @code{normal_stop} Notifications +@cindex @code{normal_stop} observer +@cindex notification about inferior execution stop + +@value{GDBN} notifies all @code{normal_stop} observers when the +inferior execution has just stopped, the associated messages and +annotations have been printed, and the control is about to be returned +to the user. + +Note that the @code{normal_stop} notification is not emitted when +the execution stops due to a breakpoint, and this breakpoint has +a condition that is not met. If the breakpoint has any associated +commands list, the commands are executed after the notification +is emitted. + +The following interface is available to manage @code{normal_stop} +observers: + +@deftypefun extern struct observer *observer_attach_normal_stop (observer_normal_stop_ftype *@var{f}) +Attach the given @code{normal_stop} callback function @var{f} and +return the associated observer. +@end deftypefun + +@deftypefun extern void observer_detach_normal_stop (struct observer *@var{observer}); +Remove @var{observer} from the list of observers to be notified when +a @code{normal_stop} event occurs. +@end deftypefun + +@deftypefun extern void observer_notify_normal_stop (void); +Send a notification to all @code{normal_stop} observers. +@end deftypefun + + diff --git a/gdb/dummy-frame.c b/gdb/dummy-frame.c new file mode 100644 index 0000000..3b10c51 --- /dev/null +++ b/gdb/dummy-frame.c @@ -0,0 +1,466 @@ +/* Code dealing with dummy stack frames, for GDB, the GNU debugger. + + Copyright 1986, 1987, 1988, 1989, 1990, 1991, 1992, 1993, 1994, + 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software + Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + + +#include "defs.h" +#include "dummy-frame.h" +#include "regcache.h" +#include "frame.h" +#include "inferior.h" +#include "gdb_assert.h" +#include "frame-unwind.h" +#include "command.h" +#include "gdbcmd.h" + +static void dummy_frame_this_id (struct frame_info *next_frame, + void **this_prologue_cache, + struct frame_id *this_id); + +/* Dummy frame. This saves the processor state just prior to setting + up the inferior function call. Older targets save the registers + on the target stack (but that really slows down function calls). */ + +struct dummy_frame +{ + struct dummy_frame *next; + + /* These values belong to the caller (the previous frame, the frame + that this unwinds back to). */ + CORE_ADDR pc; + CORE_ADDR fp; + CORE_ADDR sp; + CORE_ADDR top; + struct frame_id id; + struct regcache *regcache; + + /* Address range of the call dummy code. Look for PC in the range + [LO..HI) (after allowing for DECR_PC_AFTER_BREAK). */ + CORE_ADDR call_lo; + CORE_ADDR call_hi; +}; + +static struct dummy_frame *dummy_frame_stack = NULL; + +/* Function: find_dummy_frame(pc, fp, sp) + + Search the stack of dummy frames for one matching the given PC and + FP/SP. Unlike pc_in_dummy_frame(), this function doesn't need to + adjust for DECR_PC_AFTER_BREAK. This is because it is only legal + to call this function after the PC has been adjusted. */ + +static struct dummy_frame * +find_dummy_frame (CORE_ADDR pc, CORE_ADDR fp) +{ + struct dummy_frame *dummyframe; + + for (dummyframe = dummy_frame_stack; dummyframe != NULL; + dummyframe = dummyframe->next) + { + /* Does the PC fall within the dummy frame's breakpoint + instruction. If not, discard this one. */ + if (!(pc >= dummyframe->call_lo && pc < dummyframe->call_hi)) + continue; + /* Does the FP match? */ + if (dummyframe->top != 0) + { + /* If the target architecture explicitly saved the + top-of-stack before the inferior function call, assume + that that same architecture will always pass in an FP + (frame base) value that eactly matches that saved TOS. + Don't check the saved SP and SP as they can lead to false + hits. */ + if (fp != dummyframe->top) + continue; + } + else + { + /* An older target that hasn't explicitly or implicitly + saved the dummy frame's top-of-stack. Try matching the + FP against the saved SP and FP. NOTE: If you're trying + to fix a problem with GDB not correctly finding a dummy + frame, check the comments that go with FRAME_ALIGN() and + UNWIND_DUMMY_ID(). */ + if (fp != dummyframe->fp && fp != dummyframe->sp) + continue; + } + /* The FP matches this dummy frame. */ + return dummyframe; + } + + return NULL; +} + +struct regcache * +deprecated_find_dummy_frame_regcache (CORE_ADDR pc, CORE_ADDR fp) +{ + struct dummy_frame *dummy = find_dummy_frame (pc, fp); + if (dummy != NULL) + return dummy->regcache; + else + return NULL; +} + +char * +deprecated_generic_find_dummy_frame (CORE_ADDR pc, CORE_ADDR fp) +{ + struct regcache *regcache = deprecated_find_dummy_frame_regcache (pc, fp); + if (regcache == NULL) + return NULL; + return deprecated_grub_regcache_for_registers (regcache); +} + +/* Function: pc_in_call_dummy (pc, sp, fp) + + Return true if the PC falls in a dummy frame created by gdb for an + inferior call. The code below which allows DECR_PC_AFTER_BREAK is + for infrun.c, which may give the function a PC without that + subtracted out. */ + +int +generic_pc_in_call_dummy (CORE_ADDR pc, CORE_ADDR sp, CORE_ADDR fp) +{ + return pc_in_dummy_frame (pc); +} + +/* Return non-zero if the PC falls in a dummy frame. + + The code below which allows DECR_PC_AFTER_BREAK is for infrun.c, + which may give the function a PC without that subtracted out. + + FIXME: cagney/2002-11-23: This is silly. Surely "infrun.c" can + figure out what the real PC (as in the resume address) is BEFORE + calling this function (Oh, and I'm not even sure that this function + is called with an decremented PC, the call to pc_in_call_dummy() in + that file is conditional on + !DEPRECATED_CALL_DUMMY_BREAKPOINT_OFFSET_P yet generic dummy + targets set DEPRECATED_CALL_DUMMY_BREAKPOINT_OFFSET. True?). */ + +int +pc_in_dummy_frame (CORE_ADDR pc) +{ + struct dummy_frame *dummyframe; + for (dummyframe = dummy_frame_stack; + dummyframe != NULL; + dummyframe = dummyframe->next) + { + if ((pc >= dummyframe->call_lo) + && (pc < dummyframe->call_hi + DECR_PC_AFTER_BREAK)) + return 1; + } + return 0; +} + +/* Function: read_register_dummy + Find a saved register from before GDB calls a function in the inferior */ + +CORE_ADDR +deprecated_read_register_dummy (CORE_ADDR pc, CORE_ADDR fp, int regno) +{ + struct regcache *dummy_regs = deprecated_find_dummy_frame_regcache (pc, fp); + + if (dummy_regs) + { + /* NOTE: cagney/2002-08-12: Replaced a call to + regcache_raw_read_as_address() with a call to + regcache_cooked_read_unsigned(). The old, ...as_address + function was eventually calling extract_unsigned_integer (nee + extract_address) to unpack the registers value. The below is + doing an unsigned extract so that it is functionally + equivalent. The read needs to be cooked as, otherwise, it + will never correctly return the value of a register in the + [NUM_REGS .. NUM_REGS+NUM_PSEUDO_REGS) range. */ + ULONGEST val; + regcache_cooked_read_unsigned (dummy_regs, regno, &val); + return val; + } + else + return 0; +} + +/* Save all the registers on the dummy frame stack. Most ports save the + registers on the target stack. This results in lots of unnecessary memory + references, which are slow when debugging via a serial line. Instead, we + save all the registers internally, and never write them to the stack. The + registers get restored when the called function returns to the entry point, + where a breakpoint is laying in wait. */ + +void +generic_push_dummy_frame (void) +{ + struct dummy_frame *dummy_frame; + CORE_ADDR fp = get_frame_base (get_current_frame ()); + + /* check to see if there are stale dummy frames, + perhaps left over from when a longjump took us out of a + function that was called by the debugger */ + + dummy_frame = dummy_frame_stack; + while (dummy_frame) + if (INNER_THAN (dummy_frame->fp, fp)) /* stale -- destroy! */ + { + dummy_frame_stack = dummy_frame->next; + regcache_xfree (dummy_frame->regcache); + xfree (dummy_frame); + dummy_frame = dummy_frame_stack; + } + else + dummy_frame = dummy_frame->next; + + dummy_frame = xmalloc (sizeof (struct dummy_frame)); + dummy_frame->regcache = regcache_xmalloc (current_gdbarch); + + dummy_frame->pc = read_pc (); + dummy_frame->sp = read_sp (); + dummy_frame->top = 0; + dummy_frame->fp = fp; + dummy_frame->id = get_frame_id (get_current_frame ()); + regcache_cpy (dummy_frame->regcache, current_regcache); + dummy_frame->next = dummy_frame_stack; + dummy_frame_stack = dummy_frame; +} + +void +generic_save_dummy_frame_tos (CORE_ADDR sp) +{ + dummy_frame_stack->top = sp; +} + +/* Record the upper/lower bounds on the address of the call dummy. */ + +void +generic_save_call_dummy_addr (CORE_ADDR lo, CORE_ADDR hi) +{ + dummy_frame_stack->call_lo = lo; + dummy_frame_stack->call_hi = hi; +} + +/* Restore the machine state from either the saved dummy stack or a + real stack frame. */ + +void +generic_pop_current_frame (void (*popper) (struct frame_info * frame)) +{ + struct frame_info *frame = get_current_frame (); + if (get_frame_type (frame) == DUMMY_FRAME) + /* NOTE: cagney/2002-22-23: Does this ever occure? Surely a dummy + frame will have already been poped by the "infrun.c" code. */ + generic_pop_dummy_frame (); + else + (*popper) (frame); +} + +/* Discard the innermost dummy frame from the dummy frame stack + (passed in as a parameter). */ + +static void +discard_innermost_dummy (struct dummy_frame **stack) +{ + struct dummy_frame *tbd = (*stack); + (*stack) = (*stack)->next; + regcache_xfree (tbd->regcache); + xfree (tbd); +} + +void +generic_pop_dummy_frame (void) +{ + struct dummy_frame *dummy_frame = dummy_frame_stack; + + /* FIXME: what if the first frame isn't the right one, eg.. + because one call-by-hand function has done a longjmp into another one? */ + + if (!dummy_frame) + error ("Can't pop dummy frame!"); + regcache_cpy (current_regcache, dummy_frame->regcache); + flush_cached_frames (); + + discard_innermost_dummy (&dummy_frame_stack); +} + +/* Given a call-dummy dummy-frame, return the registers. Here the + register value is taken from the local copy of the register buffer. */ + +static void +dummy_frame_prev_register (struct frame_info *next_frame, + void **this_prologue_cache, + int regnum, int *optimized, + enum lval_type *lvalp, CORE_ADDR *addrp, + int *realnum, void *bufferp) +{ + struct dummy_frame *dummy; + struct frame_id id; + + /* Call the ID method which, if at all possible, will set the + prologue cache. */ + dummy_frame_this_id (next_frame, this_prologue_cache, &id); + dummy = (*this_prologue_cache); + gdb_assert (dummy != NULL); + + /* Describe the register's location. Generic dummy frames always + have the register value in an ``expression''. */ + *optimized = 0; + *lvalp = not_lval; + *addrp = 0; + *realnum = -1; + + /* If needed, find and return the value of the register. */ + if (bufferp != NULL) + { + /* Return the actual value. */ + /* Use the regcache_cooked_read() method so that it, on the fly, + constructs either a raw or pseudo register from the raw + register cache. */ + regcache_cooked_read (dummy->regcache, regnum, bufferp); + } +} + +/* Assuming that THIS frame is a dummy (remember, the NEXT and not + THIS frame is passed in), return the ID of THIS frame. That ID is + determined by examining the NEXT frame's unwound registers using + the method unwind_dummy_id(). As a side effect, THIS dummy frame's + dummy cache is located and and saved in THIS_PROLOGUE_CACHE. */ + +static void +dummy_frame_this_id (struct frame_info *next_frame, + void **this_prologue_cache, + struct frame_id *this_id) +{ + struct dummy_frame *dummy = (*this_prologue_cache); + if (dummy != NULL) + { + (*this_id) = dummy->id; + return; + } + /* When unwinding a normal frame, the stack structure is determined + by analyzing the frame's function's code (be it using brute force + prologue analysis, or the dwarf2 CFI). In the case of a dummy + frame, that simply isn't possible. The The PC is either the + program entry point, or some random address on the stack. Trying + to use that PC to apply standard frame ID unwind techniques is + just asking for trouble. */ + if (gdbarch_unwind_dummy_id_p (current_gdbarch)) + { + /* Use an architecture specific method to extract the prev's + dummy ID from the next frame. Note that this method uses + frame_register_unwind to obtain the register values needed to + determine the dummy frame's ID. */ + (*this_id) = gdbarch_unwind_dummy_id (current_gdbarch, next_frame); + } + else if (frame_relative_level (next_frame) < 0) + { + /* We're unwinding a sentinel frame, the PC of which is pointing + at a stack dummy. Fake up the dummy frame's ID using the + same sequence as is found a traditional unwinder. Once all + architectures supply the unwind_dummy_id method, this code + can go away. */ + (*this_id) = frame_id_build (deprecated_read_fp (), read_pc ()); + } + else if (legacy_frame_p (current_gdbarch) + && get_prev_frame (next_frame)) + { + /* Things are looking seriously grim! Assume that the legacy + get_prev_frame code has already created THIS frame and linked + it in to the frame chain (a pretty bold assumption), extract + the ID from THIS base / pc. */ + (*this_id) = frame_id_build (get_frame_base (get_prev_frame (next_frame)), + get_frame_pc (get_prev_frame (next_frame))); + } + else + { + /* Ouch! We're not trying to find the innermost frame's ID yet + we're trying to unwind to a dummy. The architecture must + provide the unwind_dummy_id() method. Abandon the unwind + process but only after first warning the user. */ + internal_warning (__FILE__, __LINE__, + "Missing unwind_dummy_id architecture method"); + (*this_id) = null_frame_id; + return; + } + (*this_prologue_cache) = find_dummy_frame ((*this_id).code_addr, + (*this_id).stack_addr); +} + +static struct frame_unwind dummy_frame_unwind = +{ + DUMMY_FRAME, + dummy_frame_this_id, + dummy_frame_prev_register +}; + +const struct frame_unwind * +dummy_frame_sniffer (struct frame_info *next_frame) +{ + CORE_ADDR pc = frame_pc_unwind (next_frame); + if (DEPRECATED_PC_IN_CALL_DUMMY_P () + ? DEPRECATED_PC_IN_CALL_DUMMY (pc, 0, 0) + : pc_in_dummy_frame (pc)) + return &dummy_frame_unwind; + else + return NULL; +} + +static void +fprint_dummy_frames (struct ui_file *file) +{ + struct dummy_frame *s; + for (s = dummy_frame_stack; s != NULL; s = s->next) + { + gdb_print_host_address (s, file); + fprintf_unfiltered (file, ":"); + fprintf_unfiltered (file, " pc=0x%s", paddr (s->pc)); + fprintf_unfiltered (file, " fp=0x%s", paddr (s->fp)); + fprintf_unfiltered (file, " sp=0x%s", paddr (s->sp)); + fprintf_unfiltered (file, " top=0x%s", paddr (s->top)); + fprintf_unfiltered (file, " id="); + fprint_frame_id (file, s->id); + fprintf_unfiltered (file, " call_lo=0x%s", paddr (s->call_lo)); + fprintf_unfiltered (file, " call_hi=0x%s", paddr (s->call_hi)); + fprintf_unfiltered (file, "\n"); + } +} + +static void +maintenance_print_dummy_frames (char *args, int from_tty) +{ + if (args == NULL) + fprint_dummy_frames (gdb_stdout); + else + { + struct ui_file *file = gdb_fopen (args, "w"); + if (file == NULL) + perror_with_name ("maintenance print dummy-frames"); + fprint_dummy_frames (file); + ui_file_delete (file); + } +} + +extern void _initialize_dummy_frame (void); + +void +_initialize_dummy_frame (void) +{ + add_cmd ("dummy-frames", class_maintenance, maintenance_print_dummy_frames, + "Print the contents of the internal dummy-frame stack.", + &maintenanceprintlist); + +} diff --git a/gdb/dummy-frame.h b/gdb/dummy-frame.h new file mode 100644 index 0000000..cde9eb7 --- /dev/null +++ b/gdb/dummy-frame.h @@ -0,0 +1,86 @@ +/* Code dealing with dummy stack frames, for GDB, the GNU debugger. + + Copyright 2002 Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#if !defined (DUMMY_FRAME_H) +#define DUMMY_FRAME_H 1 + +struct frame_info; +struct regcache; +struct frame_unwind; +struct frame_id; + +/* GENERIC DUMMY FRAMES + + The following code serves to maintain the dummy stack frames for + inferior function calls (ie. when gdb calls into the inferior via + call_function_by_hand). This code saves the machine state before + the call in host memory, so we must maintain an independent stack + and keep it consistant etc. I am attempting to make this code + generic enough to be used by many targets. + + The cheapest and most generic way to do CALL_DUMMY on a new target + is probably to define CALL_DUMMY to be empty, + DEPRECATED_CALL_DUMMY_LENGTH to zero, and CALL_DUMMY_LOCATION to + AT_ENTRY. Then you must remember to define PUSH_RETURN_ADDRESS, + because no call instruction will be being executed by the target. + Also DEPRECATED_FRAME_CHAIN_VALID as + generic_{file,func}_frame_chain_valid and do not set + DEPRECATED_FIX_CALL_DUMMY. */ + +/* If the PC falls in a dummy frame, return a dummy frame + unwinder. */ + +extern const struct frame_unwind *dummy_frame_sniffer (struct frame_info *next_frame); + +/* Does the PC fall in a dummy frame? + + This function is used by "frame.c" when creating a new `struct + frame_info'. + + Note that there is also very similar code in breakpoint.c (where + the bpstat stop reason is computed). It is looking for a PC + falling on a dummy_frame breakpoint. Perhaphs this, and that code + should be combined? + + Architecture dependant code, that has access to a frame, should not + use this function. Instead (get_frame_type() == DUMMY_FRAME) + should be used. + + Hmm, but what about threads? When the dummy-frame code tries to + relocate a dummy frame's saved registers it definitly needs to + differentiate between threads (otherwize it will do things like + clean-up the wrong threads frames). However, when just trying to + identify a dummy-frame that shouldn't matter. The wost that can + happen is that a thread is marked as sitting in a dummy frame when, + in reality, its corrupted its stack, to the point that a PC is + pointing into a dummy frame. */ + +extern int pc_in_dummy_frame (CORE_ADDR pc); + +/* Return the regcache that belongs to the dummy-frame identifed by PC + and FP, or NULL if no such frame exists. */ +/* FIXME: cagney/2002-11-08: The function only exists because of + deprecated_generic_get_saved_register. Eliminate that function and + this, to, can go. */ + +extern struct regcache *deprecated_find_dummy_frame_regcache (CORE_ADDR pc, + CORE_ADDR fp); +#endif /* !defined (DUMMY_FRAME_H) */ diff --git a/gdb/dwarf2-frame.c b/gdb/dwarf2-frame.c new file mode 100644 index 0000000..59f4481 --- /dev/null +++ b/gdb/dwarf2-frame.c @@ -0,0 +1,1583 @@ +/* Frame unwinder for frames with DWARF Call Frame Information. + + Copyright 2003 Free Software Foundation, Inc. + + Contributed by Mark Kettenis. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#include "defs.h" +#include "dwarf2expr.h" +#include "elf/dwarf2.h" +#include "frame.h" +#include "frame-base.h" +#include "frame-unwind.h" +#include "gdbcore.h" +#include "gdbtypes.h" +#include "symtab.h" +#include "objfiles.h" +#include "regcache.h" + +#include "gdb_assert.h" +#include "gdb_string.h" + +#include "complaints.h" +#include "dwarf2-frame.h" + +/* Call Frame Information (CFI). */ + +/* Common Information Entry (CIE). */ + +struct dwarf2_cie +{ + /* Offset into the .debug_frame section where this CIE was found. + Used to identify this CIE. */ + ULONGEST cie_pointer; + + /* Constant that is factored out of all advance location + instructions. */ + ULONGEST code_alignment_factor; + + /* Constants that is factored out of all offset instructions. */ + LONGEST data_alignment_factor; + + /* Return address column. */ + ULONGEST return_address_register; + + /* Instruction sequence to initialize a register set. */ + unsigned char *initial_instructions; + unsigned char *end; + + /* Encoding of addresses. */ + unsigned char encoding; + + /* True if a 'z' augmentation existed. */ + unsigned char saw_z_augmentation; + + struct dwarf2_cie *next; +}; + +/* Frame Description Entry (FDE). */ + +struct dwarf2_fde +{ + /* CIE for this FDE. */ + struct dwarf2_cie *cie; + + /* First location associated with this FDE. */ + CORE_ADDR initial_location; + + /* Number of bytes of program instructions described by this FDE. */ + CORE_ADDR address_range; + + /* Instruction sequence. */ + unsigned char *instructions; + unsigned char *end; + + struct dwarf2_fde *next; +}; + +static struct dwarf2_fde *dwarf2_frame_find_fde (CORE_ADDR *pc); + + +/* Structure describing a frame state. */ + +enum dwarf2_reg_rule +{ + /* Make certain that 0 maps onto the correct enum value; the + corresponding structure is being initialized using memset zero. + This indicates that CFI didn't provide any information at all + about a register, leaving how to obtain its value totally + unspecified. */ + REG_UNSPECIFIED = 0, + /* The term "undefined" comes from the DWARF2 CFI spec which this + code is moddeling; it indicates that the register's value is + "undefined". GCC uses the less formal term "unsaved". Its + definition is a combination of REG_UNDEFINED and REG_UNSPECIFIED. + The failure to differentiate the two helps explain a few problems + with the CFI generated by GCC. */ + REG_UNDEFINED, + REG_SAVED_OFFSET, + REG_SAVED_REG, + REG_SAVED_EXP, + REG_SAME_VALUE +}; + +struct dwarf2_frame_state +{ + /* Each register save state can be described in terms of a CFA slot, + another register, or a location expression. */ + struct dwarf2_frame_state_reg_info + { + struct dwarf2_frame_state_reg + { + union { + LONGEST offset; + ULONGEST reg; + unsigned char *exp; + } loc; + ULONGEST exp_len; + enum dwarf2_reg_rule how; + } *reg; + int num_regs; + + /* Used to implement DW_CFA_remember_state. */ + struct dwarf2_frame_state_reg_info *prev; + } regs; + + LONGEST cfa_offset; + ULONGEST cfa_reg; + unsigned char *cfa_exp; + enum { + CFA_UNSET, + CFA_REG_OFFSET, + CFA_EXP + } cfa_how; + + /* The PC described by the current frame state. */ + CORE_ADDR pc; + + /* Initial register set from the CIE. + Used to implement DW_CFA_restore. */ + struct dwarf2_frame_state_reg_info initial; + + /* The information we care about from the CIE. */ + LONGEST data_align; + ULONGEST code_align; + ULONGEST retaddr_column; +}; + +/* Store the length the expression for the CFA in the `cfa_reg' field, + which is unused in that case. */ +#define cfa_exp_len cfa_reg + +/* Assert that the register set RS is large enough to store NUM_REGS + columns. If necessary, enlarge the register set. */ + +static void +dwarf2_frame_state_alloc_regs (struct dwarf2_frame_state_reg_info *rs, + int num_regs) +{ + size_t size = sizeof (struct dwarf2_frame_state_reg); + + if (num_regs <= rs->num_regs) + return; + + rs->reg = (struct dwarf2_frame_state_reg *) + xrealloc (rs->reg, num_regs * size); + + /* Initialize newly allocated registers. */ + memset (rs->reg + rs->num_regs, 0, (num_regs - rs->num_regs) * size); + rs->num_regs = num_regs; +} + +/* Copy the register columns in register set RS into newly allocated + memory and return a pointer to this newly created copy. */ + +static struct dwarf2_frame_state_reg * +dwarf2_frame_state_copy_regs (struct dwarf2_frame_state_reg_info *rs) +{ + size_t size = rs->num_regs * sizeof (struct dwarf2_frame_state_reg_info); + struct dwarf2_frame_state_reg *reg; + + reg = (struct dwarf2_frame_state_reg *) xmalloc (size); + memcpy (reg, rs->reg, size); + + return reg; +} + +/* Release the memory allocated to register set RS. */ + +static void +dwarf2_frame_state_free_regs (struct dwarf2_frame_state_reg_info *rs) +{ + if (rs) + { + dwarf2_frame_state_free_regs (rs->prev); + + xfree (rs->reg); + xfree (rs); + } +} + +/* Release the memory allocated to the frame state FS. */ + +static void +dwarf2_frame_state_free (void *p) +{ + struct dwarf2_frame_state *fs = p; + + dwarf2_frame_state_free_regs (fs->initial.prev); + dwarf2_frame_state_free_regs (fs->regs.prev); + xfree (fs->initial.reg); + xfree (fs->regs.reg); + xfree (fs); +} + + +/* Helper functions for execute_stack_op. */ + +static CORE_ADDR +read_reg (void *baton, int reg) +{ + struct frame_info *next_frame = (struct frame_info *) baton; + int regnum; + char *buf; + + regnum = DWARF2_REG_TO_REGNUM (reg); + + buf = (char *) alloca (register_size (current_gdbarch, regnum)); + frame_unwind_register (next_frame, regnum, buf); + return extract_typed_address (buf, builtin_type_void_data_ptr); +} + +static void +read_mem (void *baton, char *buf, CORE_ADDR addr, size_t len) +{ + read_memory (addr, buf, len); +} + +static void +no_get_frame_base (void *baton, unsigned char **start, size_t *length) +{ + internal_error (__FILE__, __LINE__, + "Support for DW_OP_fbreg is unimplemented"); +} + +static CORE_ADDR +no_get_tls_address (void *baton, CORE_ADDR offset) +{ + internal_error (__FILE__, __LINE__, + "Support for DW_OP_GNU_push_tls_address is unimplemented"); +} + +static CORE_ADDR +execute_stack_op (unsigned char *exp, ULONGEST len, + struct frame_info *next_frame, CORE_ADDR initial) +{ + struct dwarf_expr_context *ctx; + CORE_ADDR result; + + ctx = new_dwarf_expr_context (); + ctx->baton = next_frame; + ctx->read_reg = read_reg; + ctx->read_mem = read_mem; + ctx->get_frame_base = no_get_frame_base; + ctx->get_tls_address = no_get_tls_address; + + dwarf_expr_push (ctx, initial); + dwarf_expr_eval (ctx, exp, len); + result = dwarf_expr_fetch (ctx, 0); + + if (ctx->in_reg) + result = read_reg (next_frame, result); + + free_dwarf_expr_context (ctx); + + return result; +} + + +static void +execute_cfa_program (unsigned char *insn_ptr, unsigned char *insn_end, + struct frame_info *next_frame, + struct dwarf2_frame_state *fs) +{ + CORE_ADDR pc = frame_pc_unwind (next_frame); + int bytes_read; + + while (insn_ptr < insn_end && fs->pc <= pc) + { + unsigned char insn = *insn_ptr++; + ULONGEST utmp, reg; + LONGEST offset; + + if ((insn & 0xc0) == DW_CFA_advance_loc) + fs->pc += (insn & 0x3f) * fs->code_align; + else if ((insn & 0xc0) == DW_CFA_offset) + { + reg = insn & 0x3f; + insn_ptr = read_uleb128 (insn_ptr, insn_end, &utmp); + offset = utmp * fs->data_align; + dwarf2_frame_state_alloc_regs (&fs->regs, reg + 1); + fs->regs.reg[reg].how = REG_SAVED_OFFSET; + fs->regs.reg[reg].loc.offset = offset; + } + else if ((insn & 0xc0) == DW_CFA_restore) + { + gdb_assert (fs->initial.reg); + reg = insn & 0x3f; + dwarf2_frame_state_alloc_regs (&fs->regs, reg + 1); + fs->regs.reg[reg] = fs->initial.reg[reg]; + } + else + { + switch (insn) + { + case DW_CFA_set_loc: + fs->pc = dwarf2_read_address (insn_ptr, insn_end, &bytes_read); + insn_ptr += bytes_read; + break; + + case DW_CFA_advance_loc1: + utmp = extract_unsigned_integer (insn_ptr, 1); + fs->pc += utmp * fs->code_align; + insn_ptr++; + break; + case DW_CFA_advance_loc2: + utmp = extract_unsigned_integer (insn_ptr, 2); + fs->pc += utmp * fs->code_align; + insn_ptr += 2; + break; + case DW_CFA_advance_loc4: + utmp = extract_unsigned_integer (insn_ptr, 4); + fs->pc += utmp * fs->code_align; + insn_ptr += 4; + break; + + case DW_CFA_offset_extended: + insn_ptr = read_uleb128 (insn_ptr, insn_end, ®); + insn_ptr = read_uleb128 (insn_ptr, insn_end, &utmp); + offset = utmp * fs->data_align; + dwarf2_frame_state_alloc_regs (&fs->regs, reg + 1); + fs->regs.reg[reg].how = REG_SAVED_OFFSET; + fs->regs.reg[reg].loc.offset = offset; + break; + + case DW_CFA_restore_extended: + gdb_assert (fs->initial.reg); + insn_ptr = read_uleb128 (insn_ptr, insn_end, ®); + dwarf2_frame_state_alloc_regs (&fs->regs, reg + 1); + fs->regs.reg[reg] = fs->initial.reg[reg]; + break; + + case DW_CFA_undefined: + insn_ptr = read_uleb128 (insn_ptr, insn_end, ®); + dwarf2_frame_state_alloc_regs (&fs->regs, reg + 1); + fs->regs.reg[reg].how = REG_UNDEFINED; + break; + + case DW_CFA_same_value: + insn_ptr = read_uleb128 (insn_ptr, insn_end, ®); + dwarf2_frame_state_alloc_regs (&fs->regs, reg + 1); + fs->regs.reg[reg].how = REG_SAME_VALUE; + break; + + case DW_CFA_register: + insn_ptr = read_uleb128 (insn_ptr, insn_end, ®); + insn_ptr = read_uleb128 (insn_ptr, insn_end, &utmp); + dwarf2_frame_state_alloc_regs (&fs->regs, reg + 1); + fs->regs.reg[reg].how = REG_SAVED_REG; + fs->regs.reg[reg].loc.reg = utmp; + break; + + case DW_CFA_remember_state: + { + struct dwarf2_frame_state_reg_info *new_rs; + + new_rs = XMALLOC (struct dwarf2_frame_state_reg_info); + *new_rs = fs->regs; + fs->regs.reg = dwarf2_frame_state_copy_regs (&fs->regs); + fs->regs.prev = new_rs; + } + break; + + case DW_CFA_restore_state: + { + struct dwarf2_frame_state_reg_info *old_rs = fs->regs.prev; + + gdb_assert (old_rs); + + xfree (fs->regs.reg); + fs->regs = *old_rs; + xfree (old_rs); + } + break; + + case DW_CFA_def_cfa: + insn_ptr = read_uleb128 (insn_ptr, insn_end, &fs->cfa_reg); + insn_ptr = read_uleb128 (insn_ptr, insn_end, &utmp); + fs->cfa_offset = utmp; + fs->cfa_how = CFA_REG_OFFSET; + break; + + case DW_CFA_def_cfa_register: + insn_ptr = read_uleb128 (insn_ptr, insn_end, &fs->cfa_reg); + fs->cfa_how = CFA_REG_OFFSET; + break; + + case DW_CFA_def_cfa_offset: + insn_ptr = read_uleb128 (insn_ptr, insn_end, &fs->cfa_offset); + /* cfa_how deliberately not set. */ + break; + + case DW_CFA_def_cfa_expression: + insn_ptr = read_uleb128 (insn_ptr, insn_end, &fs->cfa_exp_len); + fs->cfa_exp = insn_ptr; + fs->cfa_how = CFA_EXP; + insn_ptr += fs->cfa_exp_len; + break; + + case DW_CFA_expression: + insn_ptr = read_uleb128 (insn_ptr, insn_end, ®); + dwarf2_frame_state_alloc_regs (&fs->regs, reg + 1); + insn_ptr = read_uleb128 (insn_ptr, insn_end, &utmp); + fs->regs.reg[reg].loc.exp = insn_ptr; + fs->regs.reg[reg].exp_len = utmp; + fs->regs.reg[reg].how = REG_SAVED_EXP; + insn_ptr += utmp; + break; + + case DW_CFA_nop: + break; + + case DW_CFA_GNU_args_size: + /* Ignored. */ + insn_ptr = read_uleb128 (insn_ptr, insn_end, &utmp); + break; + + default: + internal_error (__FILE__, __LINE__, "Unknown CFI encountered."); + } + } + } + + /* Don't allow remember/restore between CIE and FDE programs. */ + dwarf2_frame_state_free_regs (fs->regs.prev); + fs->regs.prev = NULL; +} + +struct dwarf2_frame_cache +{ + /* DWARF Call Frame Address. */ + CORE_ADDR cfa; + + /* Saved registers, indexed by GDB register number, not by DWARF + register number. */ + struct dwarf2_frame_state_reg *reg; +}; + +static struct dwarf2_frame_cache * +dwarf2_frame_cache (struct frame_info *next_frame, void **this_cache) +{ + struct cleanup *old_chain; + const int num_regs = NUM_REGS + NUM_PSEUDO_REGS; + struct dwarf2_frame_cache *cache; + struct dwarf2_frame_state *fs; + struct dwarf2_fde *fde; + + if (*this_cache) + return *this_cache; + + /* Allocate a new cache. */ + cache = FRAME_OBSTACK_ZALLOC (struct dwarf2_frame_cache); + cache->reg = FRAME_OBSTACK_CALLOC (num_regs, struct dwarf2_frame_state_reg); + + /* Allocate and initialize the frame state. */ + fs = XMALLOC (struct dwarf2_frame_state); + memset (fs, 0, sizeof (struct dwarf2_frame_state)); + old_chain = make_cleanup (dwarf2_frame_state_free, fs); + + /* Unwind the PC. + + Note that if NEXT_FRAME is never supposed to return (i.e. a call + to abort), the compiler might optimize away the instruction at + NEXT_FRAME's return address. As a result the return address will + point at some random instruction, and the CFI for that + instruction is probably worthless to us. GCC's unwinder solves + this problem by substracting 1 from the return address to get an + address in the middle of a presumed call instruction (or the + instruction in the associated delay slot). This should only be + done for "normal" frames and not for resume-type frames (signal + handlers, sentinel frames, dummy frames). The function + frame_unwind_address_in_block does just this. It's not clear how + reliable the method is though; there is the potential for the + register state pre-call being different to that on return. */ + fs->pc = frame_unwind_address_in_block (next_frame); + + /* Find the correct FDE. */ + fde = dwarf2_frame_find_fde (&fs->pc); + gdb_assert (fde != NULL); + + /* Extract any interesting information from the CIE. */ + fs->data_align = fde->cie->data_alignment_factor; + fs->code_align = fde->cie->code_alignment_factor; + fs->retaddr_column = fde->cie->return_address_register; + + /* First decode all the insns in the CIE. */ + execute_cfa_program (fde->cie->initial_instructions, + fde->cie->end, next_frame, fs); + + /* Save the initialized register set. */ + fs->initial = fs->regs; + fs->initial.reg = dwarf2_frame_state_copy_regs (&fs->regs); + + /* Then decode the insns in the FDE up to our target PC. */ + execute_cfa_program (fde->instructions, fde->end, next_frame, fs); + + /* Caclulate the CFA. */ + switch (fs->cfa_how) + { + case CFA_REG_OFFSET: + cache->cfa = read_reg (next_frame, fs->cfa_reg); + cache->cfa += fs->cfa_offset; + break; + + case CFA_EXP: + cache->cfa = + execute_stack_op (fs->cfa_exp, fs->cfa_exp_len, next_frame, 0); + break; + + default: + internal_error (__FILE__, __LINE__, "Unknown CFA rule."); + } + + /* Initialize things so that all registers are marked as + unspecified. */ + { + int regnum; + + for (regnum = 0; regnum < num_regs; regnum++) + cache->reg[regnum].how = REG_UNSPECIFIED; + } + + /* Go through the DWARF2 CFI generated table and save its register + location information in the cache. */ + { + int column; /* CFI speak for "register number". */ + + for (column = 0; column < fs->regs.num_regs; column++) + { + int regnum; + + /* Skip the return address column. */ + if (column == fs->retaddr_column) + /* NOTE: cagney/2003-06-07: Is this right? What if + RETADDR_COLUMN corresponds to a real register (and, + worse, that isn't the PC_REGNUM)? I'm guessing that the + PC_REGNUM further down is trying to handle this. That + can't be right though; PC_REGNUM may not be valid (it can + be negative). I think, instead when RETADDR_COLUM isn't + a real register, it should map itself onto + frame_pc_unwind. */ + continue; + + /* Use the GDB register number as the destination index. */ + regnum = DWARF2_REG_TO_REGNUM (column); + + /* If there's no corresponding GDB register, ignore it. */ + if (regnum < 0 || regnum >= num_regs) + continue; + + /* NOTE: cagney/2003-09-05: CFI should specify the disposition + of all debug info registers. If it doesn't, complain (but + not too loudly). It turns out that GCC assumes that an + unspecified register implies "same value" when CFI (draft + 7) specifies nothing at all. Such a register could equally + be interpreted as "undefined". Also note that this check + isn't sufficient; it only checks that all registers in the + range [0 .. max column] are specified, and won't detect + problems when a debug info register falls outside of the + table. We need a way of iterating through all the valid + DWARF2 register numbers. */ + if (fs->regs.reg[column].how == REG_UNSPECIFIED) + complaint (&symfile_complaints, + "Incomplete CFI data; unspecified registers at 0x%s", + paddr (fs->pc)); + + cache->reg[regnum] = fs->regs.reg[column]; + } + } + + /* Store the location of the return addess. If the return address + column (adjusted) is not the same as GDB's PC_REGNUM, then this + implies a copy from the return address column register. */ + if (fs->retaddr_column < fs->regs.num_regs + && fs->regs.reg[fs->retaddr_column].how != REG_UNDEFINED) + { + /* See comment above about a possibly negative PC_REGNUM. If + this assertion fails, it's a problem with this code and not + the architecture. */ + gdb_assert (PC_REGNUM >= 0); + cache->reg[PC_REGNUM] = fs->regs.reg[fs->retaddr_column]; + } + else + { + if (DWARF2_REG_TO_REGNUM (fs->retaddr_column) != PC_REGNUM) + { + /* See comment above about PC_REGNUM being negative. If + this assertion fails, it's a problem with this code and + not the architecture. */ + gdb_assert (PC_REGNUM >= 0); + cache->reg[PC_REGNUM].loc.reg = fs->retaddr_column; + cache->reg[PC_REGNUM].how = REG_SAVED_REG; + } + } + + do_cleanups (old_chain); + + *this_cache = cache; + return cache; +} + +static void +dwarf2_frame_this_id (struct frame_info *next_frame, void **this_cache, + struct frame_id *this_id) +{ + struct dwarf2_frame_cache *cache = + dwarf2_frame_cache (next_frame, this_cache); + + (*this_id) = frame_id_build (cache->cfa, frame_func_unwind (next_frame)); +} + +static void +dwarf2_frame_prev_register (struct frame_info *next_frame, void **this_cache, + int regnum, int *optimizedp, + enum lval_type *lvalp, CORE_ADDR *addrp, + int *realnump, void *valuep) +{ + struct dwarf2_frame_cache *cache = + dwarf2_frame_cache (next_frame, this_cache); + + switch (cache->reg[regnum].how) + { + case REG_UNDEFINED: + /* If CFI explicitly specified that the value isn't defined, + mark it as optimized away; the value isn't available. */ + *optimizedp = 1; + *lvalp = not_lval; + *addrp = 0; + *realnump = -1; + if (regnum == SP_REGNUM) + { + /* GCC defines the CFA as the value of the stack pointer + just before the call instruction is executed. Do other + compilers use the same definition? */ + /* DWARF V3 Draft 7 p102: Typically, the CFA is defined to + be the value of the stack pointer at the call site in the + previous frame (which may be different from its value on + entry to the current frame). */ + /* DWARF V3 Draft 7 p103: The first column of the rules + defines the rule which computes the CFA value; it may be + either a register and a signed offset that are added + together or a DWARF expression that is evaluated. */ + /* FIXME: cagney/2003-07-07: I don't understand this. The + CFI info should have provided unwind information for the + SP register and then pointed ->cfa_reg at it, not the + reverse. Assuming that SP_REGNUM isn't negative, there + is a very real posibility that CFA is an offset from some + other register, having nothing to do with the unwound SP + value. */ + /* FIXME: cagney/2003-09-05: I think I understand. GDB was + lumping the two states "unspecified" and "undefined" + together. Here SP_REGNUM was "unspecified", GCC assuming + that in such a case CFA would be used. This branch of + the if statement should be deleted - the problem of + SP_REGNUM is now handed by the case REG_UNSPECIFIED + below. */ + *optimizedp = 0; + if (valuep) + { + /* Store the value. */ + store_typed_address (valuep, builtin_type_void_data_ptr, + cache->cfa); + } + } + else if (valuep) + { + /* In some cases, for example %eflags on the i386, we have + to provide a sane value, even though this register wasn't + saved. Assume we can get it from NEXT_FRAME. */ + frame_unwind_register (next_frame, regnum, valuep); + } + break; + + case REG_SAVED_OFFSET: + *optimizedp = 0; + *lvalp = lval_memory; + *addrp = cache->cfa + cache->reg[regnum].loc.offset; + *realnump = -1; + if (valuep) + { + /* Read the value in from memory. */ + read_memory (*addrp, valuep, + register_size (current_gdbarch, regnum)); + } + break; + + case REG_SAVED_REG: + regnum = DWARF2_REG_TO_REGNUM (cache->reg[regnum].loc.reg); + frame_register_unwind (next_frame, regnum, + optimizedp, lvalp, addrp, realnump, valuep); + break; + + case REG_SAVED_EXP: + *optimizedp = 0; + *lvalp = lval_memory; + *addrp = execute_stack_op (cache->reg[regnum].loc.exp, + cache->reg[regnum].exp_len, + next_frame, cache->cfa); + *realnump = -1; + if (valuep) + { + /* Read the value in from memory. */ + read_memory (*addrp, valuep, + register_size (current_gdbarch, regnum)); + } + break; + + case REG_UNSPECIFIED: + /* GCC, in its infinite wisdom decided to not provide unwind + information for registers that are "same value". Since + DWARF2 (3 draft 7) doesn't define such behavior, said + registers are actually undefined (which is different to CFI + "undefined"). Code above issues a complaint about this. + Here just fudge the books, assume GCC, and that the value is + more inner on the stack. */ + if (SP_REGNUM >= 0 && regnum == SP_REGNUM) + { + /* Can things get worse? Yep! One of the registers GCC + forgot to provide unwind information for was the stack + pointer. Outch! GCC appears to assumes that the CFA + address can be used - after all it points to the inner + most address of the previous frame before the function + call and that's always the same as the stack pointer on + return, right? Wrong. See GCC's i386 STDCALL option for + an ABI that has a different entry and return stack + pointer. */ + /* DWARF V3 Draft 7 p102: Typically, the CFA is defined to + be the value of the stack pointer at the call site in the + previous frame (which may be different from its value on + entry to the current frame). */ + /* DWARF V3 Draft 7 p103: The first column of the rules + defines the rule which computes the CFA value; it may be + either a register and a signed offset that are added + together or a DWARF expression that is evaluated. */ + /* NOTE: cagney/2003-09-05: Should issue a complaint. + Unfortunately it turns out that DWARF2 CFI has a problem. + Since CFI specifies the location at which a register was + saved (not its value) it isn't possible to specify + something like "unwound(REG) == REG + constant" using CFI + as will almost always occure with the stack pointer. I + guess CFI should be point SP at CFA. Ref: danielj, + "Describing unsaved stack pointers", posted to dwarf2 + list 2003-08-15. */ + *optimizedp = 0; + *lvalp = not_lval; + *addrp = 0; + *realnump = -1; + if (valuep) + /* Store the value. */ + store_typed_address (valuep, builtin_type_void_data_ptr, + cache->cfa); + } + else + /* Assume that the register can be found in the next inner + most frame. */ + frame_register_unwind (next_frame, regnum, + optimizedp, lvalp, addrp, realnump, valuep); + break; + + case REG_SAME_VALUE: + frame_register_unwind (next_frame, regnum, + optimizedp, lvalp, addrp, realnump, valuep); + break; + + default: + internal_error (__FILE__, __LINE__, "Unknown register rule."); + } +} + +static const struct frame_unwind dwarf2_frame_unwind = +{ + NORMAL_FRAME, + dwarf2_frame_this_id, + dwarf2_frame_prev_register +}; + +const struct frame_unwind * +dwarf2_frame_sniffer (struct frame_info *next_frame) +{ + /* Grab an address that is guarenteed to reside somewhere within the + function. frame_pc_unwind(), for a no-return next function, can + end up returning something past the end of this function's body. */ + CORE_ADDR block_addr = frame_unwind_address_in_block (next_frame); + if (dwarf2_frame_find_fde (&block_addr)) + return &dwarf2_frame_unwind; + + return NULL; +} + + +/* There is no explicitly defined relationship between the CFA and the + location of frame's local variables and arguments/parameters. + Therefore, frame base methods on this page should probably only be + used as a last resort, just to avoid printing total garbage as a + response to the "info frame" command. */ + +static CORE_ADDR +dwarf2_frame_base_address (struct frame_info *next_frame, void **this_cache) +{ + struct dwarf2_frame_cache *cache = + dwarf2_frame_cache (next_frame, this_cache); + + return cache->cfa; +} + +static const struct frame_base dwarf2_frame_base = +{ + &dwarf2_frame_unwind, + dwarf2_frame_base_address, + dwarf2_frame_base_address, + dwarf2_frame_base_address +}; + +const struct frame_base * +dwarf2_frame_base_sniffer (struct frame_info *next_frame) +{ + CORE_ADDR pc = frame_pc_unwind (next_frame); + if (dwarf2_frame_find_fde (&pc)) + return &dwarf2_frame_base; + + return NULL; +} + +/* A minimal decoding of DWARF2 compilation units. We only decode + what's needed to get to the call frame information. */ + +struct comp_unit +{ + /* Keep the bfd convenient. */ + bfd *abfd; + + struct objfile *objfile; + + /* Linked list of CIEs for this object. */ + struct dwarf2_cie *cie; + + /* Address size for this unit - from unit header. */ + unsigned char addr_size; + + /* Pointer to the .debug_frame section loaded into memory. */ + char *dwarf_frame_buffer; + + /* Length of the loaded .debug_frame section. */ + unsigned long dwarf_frame_size; + + /* Pointer to the .debug_frame section. */ + asection *dwarf_frame_section; + + /* Base for DW_EH_PE_datarel encodings. */ + bfd_vma dbase; + + /* Base for DW_EH_PE_textrel encodings. */ + bfd_vma tbase; +}; + +const struct objfile_data *dwarf2_frame_data; + +static unsigned int +read_1_byte (bfd *bfd, char *buf) +{ + return bfd_get_8 (abfd, (bfd_byte *) buf); +} + +static unsigned int +read_4_bytes (bfd *abfd, char *buf) +{ + return bfd_get_32 (abfd, (bfd_byte *) buf); +} + +static ULONGEST +read_8_bytes (bfd *abfd, char *buf) +{ + return bfd_get_64 (abfd, (bfd_byte *) buf); +} + +static ULONGEST +read_unsigned_leb128 (bfd *abfd, char *buf, unsigned int *bytes_read_ptr) +{ + ULONGEST result; + unsigned int num_read; + int shift; + unsigned char byte; + + result = 0; + shift = 0; + num_read = 0; + + do + { + byte = bfd_get_8 (abfd, (bfd_byte *) buf); + buf++; + num_read++; + result |= ((byte & 0x7f) << shift); + shift += 7; + } + while (byte & 0x80); + + *bytes_read_ptr = num_read; + + return result; +} + +static LONGEST +read_signed_leb128 (bfd *abfd, char *buf, unsigned int *bytes_read_ptr) +{ + LONGEST result; + int shift; + unsigned int num_read; + unsigned char byte; + + result = 0; + shift = 0; + num_read = 0; + + do + { + byte = bfd_get_8 (abfd, (bfd_byte *) buf); + buf++; + num_read++; + result |= ((byte & 0x7f) << shift); + shift += 7; + } + while (byte & 0x80); + + if ((shift < 32) && (byte & 0x40)) + result |= -(1 << shift); + + *bytes_read_ptr = num_read; + + return result; +} + +static ULONGEST +read_initial_length (bfd *abfd, char *buf, unsigned int *bytes_read_ptr) +{ + LONGEST result; + + result = bfd_get_32 (abfd, (bfd_byte *) buf); + if (result == 0xffffffff) + { + result = bfd_get_64 (abfd, (bfd_byte *) buf + 4); + *bytes_read_ptr = 12; + } + else + *bytes_read_ptr = 4; + + return result; +} + + +/* Pointer encoding helper functions. */ + +/* GCC supports exception handling based on DWARF2 CFI. However, for + technical reasons, it encodes addresses in its FDE's in a different + way. Several "pointer encodings" are supported. The encoding + that's used for a particular FDE is determined by the 'R' + augmentation in the associated CIE. The argument of this + augmentation is a single byte. + + The address can be encoded as 2 bytes, 4 bytes, 8 bytes, or as a + LEB128. This is encoded in bits 0, 1 and 2. Bit 3 encodes whether + the address is signed or unsigned. Bits 4, 5 and 6 encode how the + address should be interpreted (absolute, relative to the current + position in the FDE, ...). Bit 7, indicates that the address + should be dereferenced. */ + +static unsigned char +encoding_for_size (unsigned int size) +{ + switch (size) + { + case 2: + return DW_EH_PE_udata2; + case 4: + return DW_EH_PE_udata4; + case 8: + return DW_EH_PE_udata8; + default: + internal_error (__FILE__, __LINE__, "Unsupported address size"); + } +} + +static unsigned int +size_of_encoded_value (unsigned char encoding) +{ + if (encoding == DW_EH_PE_omit) + return 0; + + switch (encoding & 0x07) + { + case DW_EH_PE_absptr: + return TYPE_LENGTH (builtin_type_void_data_ptr); + case DW_EH_PE_udata2: + return 2; + case DW_EH_PE_udata4: + return 4; + case DW_EH_PE_udata8: + return 8; + default: + internal_error (__FILE__, __LINE__, "Invalid or unsupported encoding"); + } +} + +static CORE_ADDR +read_encoded_value (struct comp_unit *unit, unsigned char encoding, + char *buf, unsigned int *bytes_read_ptr) +{ + int ptr_len = size_of_encoded_value (DW_EH_PE_absptr); + ptrdiff_t offset; + CORE_ADDR base; + + /* GCC currently doesn't generate DW_EH_PE_indirect encodings for + FDE's. */ + if (encoding & DW_EH_PE_indirect) + internal_error (__FILE__, __LINE__, + "Unsupported encoding: DW_EH_PE_indirect"); + + *bytes_read_ptr = 0; + + switch (encoding & 0x70) + { + case DW_EH_PE_absptr: + base = 0; + break; + case DW_EH_PE_pcrel: + base = bfd_get_section_vma (unit->bfd, unit->dwarf_frame_section); + base += (buf - unit->dwarf_frame_buffer); + break; + case DW_EH_PE_datarel: + base = unit->dbase; + break; + case DW_EH_PE_textrel: + base = unit->tbase; + break; + case DW_EH_PE_aligned: + base = 0; + offset = buf - unit->dwarf_frame_buffer; + if ((offset % ptr_len) != 0) + { + *bytes_read_ptr = ptr_len - (offset % ptr_len); + buf += *bytes_read_ptr; + } + break; + default: + internal_error (__FILE__, __LINE__, "Invalid or unsupported encoding"); + } + + if ((encoding & 0x0f) == 0x00) + encoding |= encoding_for_size (ptr_len); + + switch (encoding & 0x0f) + { + case DW_EH_PE_udata2: + *bytes_read_ptr += 2; + return (base + bfd_get_16 (unit->abfd, (bfd_byte *) buf)); + case DW_EH_PE_udata4: + *bytes_read_ptr += 4; + return (base + bfd_get_32 (unit->abfd, (bfd_byte *) buf)); + case DW_EH_PE_udata8: + *bytes_read_ptr += 8; + return (base + bfd_get_64 (unit->abfd, (bfd_byte *) buf)); + case DW_EH_PE_sdata2: + *bytes_read_ptr += 2; + return (base + bfd_get_signed_16 (unit->abfd, (bfd_byte *) buf)); + case DW_EH_PE_sdata4: + *bytes_read_ptr += 4; + return (base + bfd_get_signed_32 (unit->abfd, (bfd_byte *) buf)); + case DW_EH_PE_sdata8: + *bytes_read_ptr += 8; + return (base + bfd_get_signed_64 (unit->abfd, (bfd_byte *) buf)); + default: + internal_error (__FILE__, __LINE__, "Invalid or unsupported encoding"); + } +} + + +/* GCC uses a single CIE for all FDEs in a .debug_frame section. + That's why we use a simple linked list here. */ + +static struct dwarf2_cie * +find_cie (struct comp_unit *unit, ULONGEST cie_pointer) +{ + struct dwarf2_cie *cie = unit->cie; + + while (cie) + { + if (cie->cie_pointer == cie_pointer) + return cie; + + cie = cie->next; + } + + return NULL; +} + +static void +add_cie (struct comp_unit *unit, struct dwarf2_cie *cie) +{ + cie->next = unit->cie; + unit->cie = cie; +} + +/* Find the FDE for *PC. Return a pointer to the FDE, and store the + inital location associated with it into *PC. */ + +static struct dwarf2_fde * +dwarf2_frame_find_fde (CORE_ADDR *pc) +{ + struct objfile *objfile; + + ALL_OBJFILES (objfile) + { + struct dwarf2_fde *fde; + CORE_ADDR offset; + + fde = objfile_data (objfile, dwarf2_frame_data); + if (fde == NULL) + continue; + + gdb_assert (objfile->section_offsets); + offset = ANOFFSET (objfile->section_offsets, SECT_OFF_TEXT (objfile)); + + while (fde) + { + if (*pc >= fde->initial_location + offset + && *pc < fde->initial_location + offset + fde->address_range) + { + *pc = fde->initial_location + offset; + return fde; + } + + fde = fde->next; + } + } + + return NULL; +} + +static void +add_fde (struct comp_unit *unit, struct dwarf2_fde *fde) +{ + fde->next = objfile_data (unit->objfile, dwarf2_frame_data); + set_objfile_data (unit->objfile, dwarf2_frame_data, fde); +} + +#ifdef CC_HAS_LONG_LONG +#define DW64_CIE_ID 0xffffffffffffffffULL +#else +#define DW64_CIE_ID ~0 +#endif + +static char *decode_frame_entry (struct comp_unit *unit, char *start, + int eh_frame_p); + +/* Decode the next CIE or FDE. Return NULL if invalid input, otherwise + the next byte to be processed. */ +static char * +decode_frame_entry_1 (struct comp_unit *unit, char *start, int eh_frame_p) +{ + char *buf; + LONGEST length; + unsigned int bytes_read; + int dwarf64_p; + ULONGEST cie_id; + ULONGEST cie_pointer; + char *end; + + buf = start; + length = read_initial_length (unit->abfd, buf, &bytes_read); + buf += bytes_read; + end = buf + length; + + /* Are we still within the section? */ + if (end > unit->dwarf_frame_buffer + unit->dwarf_frame_size) + return NULL; + + if (length == 0) + return end; + + /* Distinguish between 32 and 64-bit encoded frame info. */ + dwarf64_p = (bytes_read == 12); + + /* In a .eh_frame section, zero is used to distinguish CIEs from FDEs. */ + if (eh_frame_p) + cie_id = 0; + else if (dwarf64_p) + cie_id = DW64_CIE_ID; + else + cie_id = DW_CIE_ID; + + if (dwarf64_p) + { + cie_pointer = read_8_bytes (unit->abfd, buf); + buf += 8; + } + else + { + cie_pointer = read_4_bytes (unit->abfd, buf); + buf += 4; + } + + if (cie_pointer == cie_id) + { + /* This is a CIE. */ + struct dwarf2_cie *cie; + char *augmentation; + + /* Record the offset into the .debug_frame section of this CIE. */ + cie_pointer = start - unit->dwarf_frame_buffer; + + /* Check whether we've already read it. */ + if (find_cie (unit, cie_pointer)) + return end; + + cie = (struct dwarf2_cie *) + obstack_alloc (&unit->objfile->psymbol_obstack, + sizeof (struct dwarf2_cie)); + cie->initial_instructions = NULL; + cie->cie_pointer = cie_pointer; + + /* The encoding for FDE's in a normal .debug_frame section + depends on the target address size as specified in the + Compilation Unit Header. */ + cie->encoding = encoding_for_size (unit->addr_size); + + /* Check version number. */ + if (read_1_byte (unit->abfd, buf) != DW_CIE_VERSION) + return NULL; + buf += 1; + + /* Interpret the interesting bits of the augmentation. */ + augmentation = buf; + buf = augmentation + strlen (augmentation) + 1; + + /* The GCC 2.x "eh" augmentation has a pointer immediately + following the augmentation string, so it must be handled + first. */ + if (augmentation[0] == 'e' && augmentation[1] == 'h') + { + /* Skip. */ + buf += TYPE_LENGTH (builtin_type_void_data_ptr); + augmentation += 2; + } + + cie->code_alignment_factor = + read_unsigned_leb128 (unit->abfd, buf, &bytes_read); + buf += bytes_read; + + cie->data_alignment_factor = + read_signed_leb128 (unit->abfd, buf, &bytes_read); + buf += bytes_read; + + cie->return_address_register = read_1_byte (unit->abfd, buf); + buf += 1; + + cie->saw_z_augmentation = (*augmentation == 'z'); + if (cie->saw_z_augmentation) + { + ULONGEST length; + + length = read_unsigned_leb128 (unit->abfd, buf, &bytes_read); + buf += bytes_read; + if (buf > end) + return NULL; + cie->initial_instructions = buf + length; + augmentation++; + } + + while (*augmentation) + { + /* "L" indicates a byte showing how the LSDA pointer is encoded. */ + if (*augmentation == 'L') + { + /* Skip. */ + buf++; + augmentation++; + } + + /* "R" indicates a byte indicating how FDE addresses are encoded. */ + else if (*augmentation == 'R') + { + cie->encoding = *buf++; + augmentation++; + } + + /* "P" indicates a personality routine in the CIE augmentation. */ + else if (*augmentation == 'P') + { + /* Skip. */ + buf += size_of_encoded_value (*buf++); + augmentation++; + } + + /* Otherwise we have an unknown augmentation. + Bail out unless we saw a 'z' prefix. */ + else + { + if (cie->initial_instructions == NULL) + return end; + + /* Skip unknown augmentations. */ + buf = cie->initial_instructions; + break; + } + } + + cie->initial_instructions = buf; + cie->end = end; + + add_cie (unit, cie); + } + else + { + /* This is a FDE. */ + struct dwarf2_fde *fde; + + /* In an .eh_frame section, the CIE pointer is the delta between the + address within the FDE where the CIE pointer is stored and the + address of the CIE. Convert it to an offset into the .eh_frame + section. */ + if (eh_frame_p) + { + cie_pointer = buf - unit->dwarf_frame_buffer - cie_pointer; + cie_pointer -= (dwarf64_p ? 8 : 4); + } + + /* In either case, validate the result is still within the section. */ + if (cie_pointer >= unit->dwarf_frame_size) + return NULL; + + fde = (struct dwarf2_fde *) + obstack_alloc (&unit->objfile->psymbol_obstack, + sizeof (struct dwarf2_fde)); + fde->cie = find_cie (unit, cie_pointer); + if (fde->cie == NULL) + { + decode_frame_entry (unit, unit->dwarf_frame_buffer + cie_pointer, + eh_frame_p); + fde->cie = find_cie (unit, cie_pointer); + } + + gdb_assert (fde->cie != NULL); + + fde->initial_location = + read_encoded_value (unit, fde->cie->encoding, buf, &bytes_read); + buf += bytes_read; + + fde->address_range = + read_encoded_value (unit, fde->cie->encoding & 0x0f, buf, &bytes_read); + buf += bytes_read; + + /* A 'z' augmentation in the CIE implies the presence of an + augmentation field in the FDE as well. The only thing known + to be in here at present is the LSDA entry for EH. So we + can skip the whole thing. */ + if (fde->cie->saw_z_augmentation) + { + ULONGEST length; + + length = read_unsigned_leb128 (unit->abfd, buf, &bytes_read); + buf += bytes_read + length; + if (buf > end) + return NULL; + } + + fde->instructions = buf; + fde->end = end; + + add_fde (unit, fde); + } + + return end; +} + +/* Read a CIE or FDE in BUF and decode it. */ +static char * +decode_frame_entry (struct comp_unit *unit, char *start, int eh_frame_p) +{ + enum { NONE, ALIGN4, ALIGN8, FAIL } workaround = NONE; + char *ret; + const char *msg; + ptrdiff_t start_offset; + + while (1) + { + ret = decode_frame_entry_1 (unit, start, eh_frame_p); + if (ret != NULL) + break; + + /* We have corrupt input data of some form. */ + + /* ??? Try, weakly, to work around compiler/assembler/linker bugs + and mismatches wrt padding and alignment of debug sections. */ + /* Note that there is no requirement in the standard for any + alignment at all in the frame unwind sections. Testing for + alignment before trying to interpret data would be incorrect. + + However, GCC traditionally arranged for frame sections to be + sized such that the FDE length and CIE fields happen to be + aligned (in theory, for performance). This, unfortunately, + was done with .align directives, which had the side effect of + forcing the section to be aligned by the linker. + + This becomes a problem when you have some other producer that + creates frame sections that are not as strictly aligned. That + produces a hole in the frame info that gets filled by the + linker with zeros. + + The GCC behaviour is arguably a bug, but it's effectively now + part of the ABI, so we're now stuck with it, at least at the + object file level. A smart linker may decide, in the process + of compressing duplicate CIE information, that it can rewrite + the entire output section without this extra padding. */ + + start_offset = start - unit->dwarf_frame_buffer; + if (workaround < ALIGN4 && (start_offset & 3) != 0) + { + start += 4 - (start_offset & 3); + workaround = ALIGN4; + continue; + } + if (workaround < ALIGN8 && (start_offset & 7) != 0) + { + start += 8 - (start_offset & 7); + workaround = ALIGN8; + continue; + } + + /* Nothing left to try. Arrange to return as if we've consumed + the entire input section. Hopefully we'll get valid info from + the other of .debug_frame/.eh_frame. */ + workaround = FAIL; + ret = unit->dwarf_frame_buffer + unit->dwarf_frame_size; + break; + } + + switch (workaround) + { + case NONE: + break; + + case ALIGN4: + complaint (&symfile_complaints, + "Corrupt data in %s:%s; align 4 workaround apparently succeeded", + unit->dwarf_frame_section->owner->filename, + unit->dwarf_frame_section->name); + break; + + case ALIGN8: + complaint (&symfile_complaints, + "Corrupt data in %s:%s; align 8 workaround apparently succeeded", + unit->dwarf_frame_section->owner->filename, + unit->dwarf_frame_section->name); + break; + + default: + complaint (&symfile_complaints, + "Corrupt data in %s:%s", + unit->dwarf_frame_section->owner->filename, + unit->dwarf_frame_section->name); + break; + } + + return ret; +} + + + +/* FIXME: kettenis/20030504: This still needs to be integrated with + dwarf2read.c in a better way. */ + +/* Imported from dwarf2read.c. */ +extern asection *dwarf_frame_section; +extern asection *dwarf_eh_frame_section; + +/* Imported from dwarf2read.c. */ +extern char *dwarf2_read_section (struct objfile *objfile, asection *sectp); + +void +dwarf2_build_frame_info (struct objfile *objfile) +{ + struct comp_unit unit; + char *frame_ptr; + + /* Build a minimal decoding of the DWARF2 compilation unit. */ + unit.abfd = objfile->obfd; + unit.objfile = objfile; + unit.addr_size = objfile->obfd->arch_info->bits_per_address / 8; + unit.dbase = 0; + unit.tbase = 0; + + /* First add the information from the .eh_frame section. That way, + the FDEs from that section are searched last. */ + if (dwarf_eh_frame_section) + { + asection *got, *txt; + + unit.cie = NULL; + unit.dwarf_frame_buffer = dwarf2_read_section (objfile, + dwarf_eh_frame_section); + + unit.dwarf_frame_size + = bfd_get_section_size_before_reloc (dwarf_eh_frame_section); + unit.dwarf_frame_section = dwarf_eh_frame_section; + + /* FIXME: kettenis/20030602: This is the DW_EH_PE_datarel base + that is used for the i386/amd64 target, which currently is + the only target in GCC that supports/uses the + DW_EH_PE_datarel encoding. */ + got = bfd_get_section_by_name (unit.abfd, ".got"); + if (got) + unit.dbase = got->vma; + + /* GCC emits the DW_EH_PE_textrel encoding type on sh and ia64 + so far. */ + txt = bfd_get_section_by_name (unit.abfd, ".text"); + if (txt) + unit.tbase = txt->vma; + + frame_ptr = unit.dwarf_frame_buffer; + while (frame_ptr < unit.dwarf_frame_buffer + unit.dwarf_frame_size) + frame_ptr = decode_frame_entry (&unit, frame_ptr, 1); + } + + if (dwarf_frame_section) + { + unit.cie = NULL; + unit.dwarf_frame_buffer = dwarf2_read_section (objfile, + dwarf_frame_section); + unit.dwarf_frame_size + = bfd_get_section_size_before_reloc (dwarf_frame_section); + unit.dwarf_frame_section = dwarf_frame_section; + + frame_ptr = unit.dwarf_frame_buffer; + while (frame_ptr < unit.dwarf_frame_buffer + unit.dwarf_frame_size) + frame_ptr = decode_frame_entry (&unit, frame_ptr, 0); + } +} + +/* Provide a prototype to silence -Wmissing-prototypes. */ +void _initialize_dwarf2_frame (void); + +void +_initialize_dwarf2_frame (void) +{ + dwarf2_frame_data = register_objfile_data (); +} diff --git a/gdb/dwarf2-frame.h b/gdb/dwarf2-frame.h new file mode 100644 index 0000000..c9c106f --- /dev/null +++ b/gdb/dwarf2-frame.h @@ -0,0 +1,44 @@ +/* Frame unwinder for frames with DWARF Call Frame Information. + + Copyright 2003 Free Software Foundation, Inc. + + Contributed by Mark Kettenis. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#ifndef DWARF2_FRAME_H +#define DWARF2_FRAME_H 1 + +struct objfile; +struct frame_info; + +/* Return the frame unwind methods for the function that contains PC, + or NULL if it can't be handled by DWARF CFI frame unwinder. */ + +const struct frame_unwind *dwarf2_frame_sniffer (struct frame_info *next_frame); + +/* Return the frame base methods for the function that contains PC, or + NULL if it can't be handled by the DWARF CFI frame unwinder. */ + +const struct frame_base *dwarf2_frame_base_sniffer (struct frame_info *next_frame); + +/* Register the DWARF CFI for OBJFILE. */ + +void dwarf2_frame_build_info (struct objfile *objfile); + +#endif /* dwarf2-frame.h */ diff --git a/gdb/dwarf2expr.c b/gdb/dwarf2expr.c new file mode 100644 index 0000000..cf00929 --- /dev/null +++ b/gdb/dwarf2expr.c @@ -0,0 +1,670 @@ +/* Dwarf2 Expression Evaluator + Copyright 2001, 2002, 2003 Free Software Foundation, Inc. + Contributed by Daniel Berlin (dan@dberlin.org) + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#include "defs.h" +#include "symtab.h" +#include "gdbtypes.h" +#include "value.h" +#include "gdbcore.h" +#include "elf/dwarf2.h" +#include "dwarf2expr.h" + +/* Local prototypes. */ + +static void execute_stack_op (struct dwarf_expr_context *, + unsigned char *, unsigned char *); + +/* Create a new context for the expression evaluator. */ + +struct dwarf_expr_context * +new_dwarf_expr_context (void) +{ + struct dwarf_expr_context *retval; + retval = xcalloc (1, sizeof (struct dwarf_expr_context)); + retval->stack_len = 0; + retval->stack_allocated = 10; + retval->stack = xmalloc (retval->stack_allocated * sizeof (CORE_ADDR)); + return retval; +} + +/* Release the memory allocated to CTX. */ + +void +free_dwarf_expr_context (struct dwarf_expr_context *ctx) +{ + xfree (ctx->stack); + xfree (ctx); +} + +/* Expand the memory allocated to CTX's stack to contain at least + NEED more elements than are currently used. */ + +static void +dwarf_expr_grow_stack (struct dwarf_expr_context *ctx, size_t need) +{ + if (ctx->stack_len + need > ctx->stack_allocated) + { + size_t newlen = ctx->stack_len + need + 10; + ctx->stack = xrealloc (ctx->stack, + newlen * sizeof (CORE_ADDR)); + ctx->stack_allocated = newlen; + } +} + +/* Push VALUE onto CTX's stack. */ + +void +dwarf_expr_push (struct dwarf_expr_context *ctx, CORE_ADDR value) +{ + dwarf_expr_grow_stack (ctx, 1); + ctx->stack[ctx->stack_len++] = value; +} + +/* Pop the top item off of CTX's stack. */ + +void +dwarf_expr_pop (struct dwarf_expr_context *ctx) +{ + if (ctx->stack_len <= 0) + error ("dwarf expression stack underflow"); + ctx->stack_len--; +} + +/* Retrieve the N'th item on CTX's stack. */ + +CORE_ADDR +dwarf_expr_fetch (struct dwarf_expr_context *ctx, int n) +{ + if (ctx->stack_len < n) + error ("Asked for position %d of stack, stack only has %d elements on it\n", + n, ctx->stack_len); + return ctx->stack[ctx->stack_len - (1 + n)]; + +} + +/* Evaluate the expression at ADDR (LEN bytes long) using the context + CTX. */ + +void +dwarf_expr_eval (struct dwarf_expr_context *ctx, unsigned char *addr, + size_t len) +{ + execute_stack_op (ctx, addr, addr + len); +} + +/* Decode the unsigned LEB128 constant at BUF into the variable pointed to + by R, and return the new value of BUF. Verify that it doesn't extend + past BUF_END. */ + +unsigned char * +read_uleb128 (unsigned char *buf, unsigned char *buf_end, ULONGEST * r) +{ + unsigned shift = 0; + ULONGEST result = 0; + unsigned char byte; + + while (1) + { + if (buf >= buf_end) + error ("read_uleb128: Corrupted DWARF expression."); + + byte = *buf++; + result |= (byte & 0x7f) << shift; + if ((byte & 0x80) == 0) + break; + shift += 7; + } + *r = result; + return buf; +} + +/* Decode the signed LEB128 constant at BUF into the variable pointed to + by R, and return the new value of BUF. Verify that it doesn't extend + past BUF_END. */ + +unsigned char * +read_sleb128 (unsigned char *buf, unsigned char *buf_end, LONGEST * r) +{ + unsigned shift = 0; + LONGEST result = 0; + unsigned char byte; + + while (1) + { + if (buf >= buf_end) + error ("read_sleb128: Corrupted DWARF expression."); + + byte = *buf++; + result |= (byte & 0x7f) << shift; + shift += 7; + if ((byte & 0x80) == 0) + break; + } + if (shift < (sizeof (*r) * 8) && (byte & 0x40) != 0) + result |= -(1 << shift); + + *r = result; + return buf; +} + +/* Read an address from BUF, and verify that it doesn't extend past + BUF_END. The address is returned, and *BYTES_READ is set to the + number of bytes read from BUF. */ + +CORE_ADDR +dwarf2_read_address (unsigned char *buf, unsigned char *buf_end, int *bytes_read) +{ + CORE_ADDR result; + + if (buf_end - buf < TARGET_ADDR_BIT / TARGET_CHAR_BIT) + error ("dwarf2_read_address: Corrupted DWARF expression."); + + *bytes_read = TARGET_ADDR_BIT / TARGET_CHAR_BIT; + /* NOTE: cagney/2003-05-22: This extract is assuming that a DWARF 2 + address is always unsigned. That may or may not be true. */ + result = extract_unsigned_integer (buf, TARGET_ADDR_BIT / TARGET_CHAR_BIT); + return result; +} + +/* Return the type of an address, for unsigned arithmetic. */ + +static struct type * +unsigned_address_type (void) +{ + switch (TARGET_ADDR_BIT / TARGET_CHAR_BIT) + { + case 2: + return builtin_type_uint16; + case 4: + return builtin_type_uint32; + case 8: + return builtin_type_uint64; + default: + internal_error (__FILE__, __LINE__, + "Unsupported address size.\n"); + } +} + +/* Return the type of an address, for signed arithmetic. */ + +static struct type * +signed_address_type (void) +{ + switch (TARGET_ADDR_BIT / TARGET_CHAR_BIT) + { + case 2: + return builtin_type_int16; + case 4: + return builtin_type_int32; + case 8: + return builtin_type_int64; + default: + internal_error (__FILE__, __LINE__, + "Unsupported address size.\n"); + } +} + +/* The engine for the expression evaluator. Using the context in CTX, + evaluate the expression between OP_PTR and OP_END. */ + +static void +execute_stack_op (struct dwarf_expr_context *ctx, unsigned char *op_ptr, + unsigned char *op_end) +{ + ctx->in_reg = 0; + + while (op_ptr < op_end) + { + enum dwarf_location_atom op = *op_ptr++; + CORE_ADDR result; + ULONGEST uoffset, reg; + LONGEST offset; + int bytes_read; + + switch (op) + { + case DW_OP_lit0: + case DW_OP_lit1: + case DW_OP_lit2: + case DW_OP_lit3: + case DW_OP_lit4: + case DW_OP_lit5: + case DW_OP_lit6: + case DW_OP_lit7: + case DW_OP_lit8: + case DW_OP_lit9: + case DW_OP_lit10: + case DW_OP_lit11: + case DW_OP_lit12: + case DW_OP_lit13: + case DW_OP_lit14: + case DW_OP_lit15: + case DW_OP_lit16: + case DW_OP_lit17: + case DW_OP_lit18: + case DW_OP_lit19: + case DW_OP_lit20: + case DW_OP_lit21: + case DW_OP_lit22: + case DW_OP_lit23: + case DW_OP_lit24: + case DW_OP_lit25: + case DW_OP_lit26: + case DW_OP_lit27: + case DW_OP_lit28: + case DW_OP_lit29: + case DW_OP_lit30: + case DW_OP_lit31: + result = op - DW_OP_lit0; + break; + + case DW_OP_addr: + result = dwarf2_read_address (op_ptr, op_end, &bytes_read); + op_ptr += bytes_read; + break; + + case DW_OP_const1u: + result = extract_unsigned_integer (op_ptr, 1); + op_ptr += 1; + break; + case DW_OP_const1s: + result = extract_signed_integer (op_ptr, 1); + op_ptr += 1; + break; + case DW_OP_const2u: + result = extract_unsigned_integer (op_ptr, 2); + op_ptr += 2; + break; + case DW_OP_const2s: + result = extract_signed_integer (op_ptr, 2); + op_ptr += 2; + break; + case DW_OP_const4u: + result = extract_unsigned_integer (op_ptr, 4); + op_ptr += 4; + break; + case DW_OP_const4s: + result = extract_signed_integer (op_ptr, 4); + op_ptr += 4; + break; + case DW_OP_const8u: + result = extract_unsigned_integer (op_ptr, 8); + op_ptr += 8; + break; + case DW_OP_const8s: + result = extract_signed_integer (op_ptr, 8); + op_ptr += 8; + break; + case DW_OP_constu: + op_ptr = read_uleb128 (op_ptr, op_end, &uoffset); + result = uoffset; + break; + case DW_OP_consts: + op_ptr = read_sleb128 (op_ptr, op_end, &offset); + result = offset; + break; + + /* The DW_OP_reg operations are required to occur alone in + location expressions. */ + case DW_OP_reg0: + case DW_OP_reg1: + case DW_OP_reg2: + case DW_OP_reg3: + case DW_OP_reg4: + case DW_OP_reg5: + case DW_OP_reg6: + case DW_OP_reg7: + case DW_OP_reg8: + case DW_OP_reg9: + case DW_OP_reg10: + case DW_OP_reg11: + case DW_OP_reg12: + case DW_OP_reg13: + case DW_OP_reg14: + case DW_OP_reg15: + case DW_OP_reg16: + case DW_OP_reg17: + case DW_OP_reg18: + case DW_OP_reg19: + case DW_OP_reg20: + case DW_OP_reg21: + case DW_OP_reg22: + case DW_OP_reg23: + case DW_OP_reg24: + case DW_OP_reg25: + case DW_OP_reg26: + case DW_OP_reg27: + case DW_OP_reg28: + case DW_OP_reg29: + case DW_OP_reg30: + case DW_OP_reg31: + if (op_ptr != op_end && *op_ptr != DW_OP_piece) + error ("DWARF-2 expression error: DW_OP_reg operations must be " + "used either alone or in conjuction with DW_OP_piece."); + + result = op - DW_OP_reg0; + ctx->in_reg = 1; + + break; + + case DW_OP_regx: + op_ptr = read_uleb128 (op_ptr, op_end, ®); + if (op_ptr != op_end && *op_ptr != DW_OP_piece) + error ("DWARF-2 expression error: DW_OP_reg operations must be " + "used either alone or in conjuction with DW_OP_piece."); + + result = reg; + ctx->in_reg = 1; + break; + + case DW_OP_breg0: + case DW_OP_breg1: + case DW_OP_breg2: + case DW_OP_breg3: + case DW_OP_breg4: + case DW_OP_breg5: + case DW_OP_breg6: + case DW_OP_breg7: + case DW_OP_breg8: + case DW_OP_breg9: + case DW_OP_breg10: + case DW_OP_breg11: + case DW_OP_breg12: + case DW_OP_breg13: + case DW_OP_breg14: + case DW_OP_breg15: + case DW_OP_breg16: + case DW_OP_breg17: + case DW_OP_breg18: + case DW_OP_breg19: + case DW_OP_breg20: + case DW_OP_breg21: + case DW_OP_breg22: + case DW_OP_breg23: + case DW_OP_breg24: + case DW_OP_breg25: + case DW_OP_breg26: + case DW_OP_breg27: + case DW_OP_breg28: + case DW_OP_breg29: + case DW_OP_breg30: + case DW_OP_breg31: + { + op_ptr = read_sleb128 (op_ptr, op_end, &offset); + result = (ctx->read_reg) (ctx->baton, op - DW_OP_breg0); + result += offset; + } + break; + case DW_OP_bregx: + { + op_ptr = read_uleb128 (op_ptr, op_end, ®); + op_ptr = read_sleb128 (op_ptr, op_end, &offset); + result = (ctx->read_reg) (ctx->baton, reg); + result += offset; + } + break; + case DW_OP_fbreg: + { + unsigned char *datastart; + size_t datalen; + unsigned int before_stack_len; + + op_ptr = read_sleb128 (op_ptr, op_end, &offset); + /* Rather than create a whole new context, we simply + record the stack length before execution, then reset it + afterwards, effectively erasing whatever the recursive + call put there. */ + before_stack_len = ctx->stack_len; + /* FIXME: cagney/2003-03-26: This code should be using + get_frame_base_address(), and then implement a dwarf2 + specific this_base method. */ + (ctx->get_frame_base) (ctx->baton, &datastart, &datalen); + dwarf_expr_eval (ctx, datastart, datalen); + result = dwarf_expr_fetch (ctx, 0); + if (ctx->in_reg) + result = (ctx->read_reg) (ctx->baton, result); + result = result + offset; + ctx->stack_len = before_stack_len; + ctx->in_reg = 0; + } + break; + case DW_OP_dup: + result = dwarf_expr_fetch (ctx, 0); + break; + + case DW_OP_drop: + dwarf_expr_pop (ctx); + goto no_push; + + case DW_OP_pick: + offset = *op_ptr++; + result = dwarf_expr_fetch (ctx, offset); + break; + + case DW_OP_over: + result = dwarf_expr_fetch (ctx, 1); + break; + + case DW_OP_rot: + { + CORE_ADDR t1, t2, t3; + + if (ctx->stack_len < 3) + error ("Not enough elements for DW_OP_rot. Need 3, have %d\n", + ctx->stack_len); + t1 = ctx->stack[ctx->stack_len - 1]; + t2 = ctx->stack[ctx->stack_len - 2]; + t3 = ctx->stack[ctx->stack_len - 3]; + ctx->stack[ctx->stack_len - 1] = t2; + ctx->stack[ctx->stack_len - 2] = t3; + ctx->stack[ctx->stack_len - 3] = t1; + goto no_push; + } + + case DW_OP_deref: + case DW_OP_deref_size: + case DW_OP_abs: + case DW_OP_neg: + case DW_OP_not: + case DW_OP_plus_uconst: + /* Unary operations. */ + result = dwarf_expr_fetch (ctx, 0); + dwarf_expr_pop (ctx); + + switch (op) + { + case DW_OP_deref: + { + char *buf = alloca (TARGET_ADDR_BIT / TARGET_CHAR_BIT); + int bytes_read; + + (ctx->read_mem) (ctx->baton, buf, result, + TARGET_ADDR_BIT / TARGET_CHAR_BIT); + result = dwarf2_read_address (buf, + buf + (TARGET_ADDR_BIT + / TARGET_CHAR_BIT), + &bytes_read); + } + break; + + case DW_OP_deref_size: + { + char *buf = alloca (TARGET_ADDR_BIT / TARGET_CHAR_BIT); + int bytes_read; + + (ctx->read_mem) (ctx->baton, buf, result, *op_ptr++); + result = dwarf2_read_address (buf, + buf + (TARGET_ADDR_BIT + / TARGET_CHAR_BIT), + &bytes_read); + } + break; + + case DW_OP_abs: + if ((signed int) result < 0) + result = -result; + break; + case DW_OP_neg: + result = -result; + break; + case DW_OP_not: + result = ~result; + break; + case DW_OP_plus_uconst: + op_ptr = read_uleb128 (op_ptr, op_end, ®); + result += reg; + break; + } + break; + + case DW_OP_and: + case DW_OP_div: + case DW_OP_minus: + case DW_OP_mod: + case DW_OP_mul: + case DW_OP_or: + case DW_OP_plus: + case DW_OP_shl: + case DW_OP_shr: + case DW_OP_shra: + case DW_OP_xor: + case DW_OP_le: + case DW_OP_ge: + case DW_OP_eq: + case DW_OP_lt: + case DW_OP_gt: + case DW_OP_ne: + { + /* Binary operations. Use the value engine to do computations in + the right width. */ + CORE_ADDR first, second; + enum exp_opcode binop; + struct value *val1, *val2; + + second = dwarf_expr_fetch (ctx, 0); + dwarf_expr_pop (ctx); + + first = dwarf_expr_fetch (ctx, 1); + dwarf_expr_pop (ctx); + + val1 = value_from_longest (unsigned_address_type (), first); + val2 = value_from_longest (unsigned_address_type (), second); + + switch (op) + { + case DW_OP_and: + binop = BINOP_BITWISE_AND; + break; + case DW_OP_div: + binop = BINOP_DIV; + case DW_OP_minus: + binop = BINOP_SUB; + break; + case DW_OP_mod: + binop = BINOP_MOD; + break; + case DW_OP_mul: + binop = BINOP_MUL; + break; + case DW_OP_or: + binop = BINOP_BITWISE_IOR; + break; + case DW_OP_plus: + binop = BINOP_ADD; + break; + case DW_OP_shl: + binop = BINOP_LSH; + break; + case DW_OP_shr: + binop = BINOP_RSH; + case DW_OP_shra: + binop = BINOP_RSH; + val1 = value_from_longest (signed_address_type (), first); + break; + case DW_OP_xor: + binop = BINOP_BITWISE_XOR; + break; + case DW_OP_le: + binop = BINOP_LEQ; + break; + case DW_OP_ge: + binop = BINOP_GEQ; + break; + case DW_OP_eq: + binop = BINOP_EQUAL; + break; + case DW_OP_lt: + binop = BINOP_LESS; + break; + case DW_OP_gt: + binop = BINOP_GTR; + break; + case DW_OP_ne: + binop = BINOP_NOTEQUAL; + break; + default: + internal_error (__FILE__, __LINE__, + "Can't be reached."); + } + result = value_as_long (value_binop (val1, val2, binop)); + } + break; + + case DW_OP_GNU_push_tls_address: + /* Variable is at a constant offset in the thread-local + storage block into the objfile for the current thread and + the dynamic linker module containing this expression. Here + we return returns the offset from that base. The top of the + stack has the offset from the beginning of the thread + control block at which the variable is located. Nothing + should follow this operator, so the top of stack would be + returned. */ + result = dwarf_expr_fetch (ctx, 0); + dwarf_expr_pop (ctx); + result = (ctx->get_tls_address) (ctx->baton, result); + break; + + case DW_OP_skip: + offset = extract_signed_integer (op_ptr, 2); + op_ptr += 2; + op_ptr += offset; + goto no_push; + + case DW_OP_bra: + offset = extract_signed_integer (op_ptr, 2); + op_ptr += 2; + if (dwarf_expr_fetch (ctx, 0) != 0) + op_ptr += offset; + dwarf_expr_pop (ctx); + goto no_push; + + case DW_OP_nop: + goto no_push; + + default: + error ("Unhandled dwarf expression opcode"); + } + + /* Most things push a result value. */ + dwarf_expr_push (ctx, result); + no_push:; + } +} diff --git a/gdb/dwarf2expr.h b/gdb/dwarf2expr.h new file mode 100644 index 0000000..0a60edb --- /dev/null +++ b/gdb/dwarf2expr.h @@ -0,0 +1,96 @@ +/* Dwarf2 Expression Evaluator + Copyright 2001, 2002, 2003 Free Software Foundation, Inc. + Contributed by Daniel Berlin (dan@dberlin.org) + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#if !defined (DWARF2EXPR_H) +#define DWARF2EXPR_H + +/* The expression evaluator works with a dwarf_expr_context, describing + its current state and its callbacks. */ +struct dwarf_expr_context +{ + /* The stack of values, allocated with xmalloc. */ + CORE_ADDR *stack; + + /* The number of values currently pushed on the stack, and the + number of elements allocated to the stack. */ + int stack_len, stack_allocated; + + /* An opaque argument provided by the caller, which will be passed + to all of the callback functions. */ + void *baton; + + /* Return the value of register number REGNUM. */ + CORE_ADDR (*read_reg) (void *baton, int regnum); + + /* Read LENGTH bytes at ADDR into BUF. */ + void (*read_mem) (void *baton, char *buf, CORE_ADDR addr, + size_t length); + + /* Return the location expression for the frame base attribute, in + START and LENGTH. The result must be live until the current + expression evaluation is complete. */ + void (*get_frame_base) (void *baton, unsigned char **start, + size_t *length); + + /* Return the thread-local storage address for + DW_OP_GNU_push_tls_address. */ + CORE_ADDR (*get_tls_address) (void *baton, CORE_ADDR offset); + +#if 0 + /* Not yet implemented. */ + + /* Return the location expression for the dwarf expression + subroutine in the die at OFFSET in the current compilation unit. + The result must be live until the current expression evaluation + is complete. */ + unsigned char *(*get_subr) (void *baton, off_t offset, size_t *length); + + /* Return the `object address' for DW_OP_push_object_address. */ + CORE_ADDR (*get_object_address) (void *baton); +#endif + + /* The current depth of dwarf expression recursion, via DW_OP_call*, + DW_OP_fbreg, DW_OP_push_object_address, etc., and the maximum + depth we'll tolerate before raising an error. */ + int recursion_depth, max_recursion_depth; + + /* Non-zero if the result is in a register. The register number + will be on the expression stack. */ + int in_reg; +}; + +struct dwarf_expr_context *new_dwarf_expr_context (void); +void free_dwarf_expr_context (struct dwarf_expr_context *ctx); + +void dwarf_expr_push (struct dwarf_expr_context *ctx, CORE_ADDR value); +void dwarf_expr_pop (struct dwarf_expr_context *ctx); +void dwarf_expr_eval (struct dwarf_expr_context *ctx, unsigned char *addr, + size_t len); +CORE_ADDR dwarf_expr_fetch (struct dwarf_expr_context *ctx, int n); + + +unsigned char *read_uleb128 (unsigned char *buf, unsigned char *buf_end, + ULONGEST * r); +unsigned char *read_sleb128 (unsigned char *buf, unsigned char *buf_end, + LONGEST * r); +CORE_ADDR dwarf2_read_address (unsigned char *buf, unsigned char *buf_end, + int *bytes_read); + +#endif diff --git a/gdb/dwarf2loc.c b/gdb/dwarf2loc.c new file mode 100644 index 0000000..fac5c4a --- /dev/null +++ b/gdb/dwarf2loc.c @@ -0,0 +1,545 @@ +/* DWARF 2 location expression support for GDB. + Copyright 2003 Free Software Foundation, Inc. + Contributed by Daniel Jacobowitz, MontaVista Software, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or (at + your option) any later version. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#include "defs.h" +#include "ui-out.h" +#include "value.h" +#include "frame.h" +#include "gdbcore.h" +#include "target.h" +#include "inferior.h" +#include "ax.h" +#include "ax-gdb.h" +#include "regcache.h" +#include "objfiles.h" + +#include "elf/dwarf2.h" +#include "dwarf2expr.h" +#include "dwarf2loc.h" + +#include "gdb_string.h" + +#ifndef DWARF2_REG_TO_REGNUM +#define DWARF2_REG_TO_REGNUM(REG) (REG) +#endif + +/* A helper function for dealing with location lists. Given a + symbol baton (BATON) and a pc value (PC), find the appropriate + location expression, set *LOCEXPR_LENGTH, and return a pointer + to the beginning of the expression. Returns NULL on failure. + + For now, only return the first matching location expression; there + can be more than one in the list. */ + +static char * +find_location_expression (struct dwarf2_loclist_baton *baton, + size_t *locexpr_length, CORE_ADDR pc) +{ + CORE_ADDR base_address = baton->base_address; + CORE_ADDR low, high; + char *loc_ptr, *buf_end; + unsigned int addr_size = TARGET_ADDR_BIT / TARGET_CHAR_BIT, length; + CORE_ADDR base_mask = ~(~(CORE_ADDR)1 << (addr_size * 8 - 1)); + + loc_ptr = baton->data; + buf_end = baton->data + baton->size; + + while (1) + { + low = dwarf2_read_address (loc_ptr, buf_end, &length); + loc_ptr += length; + high = dwarf2_read_address (loc_ptr, buf_end, &length); + loc_ptr += length; + + /* An end-of-list entry. */ + if (low == 0 && high == 0) + return NULL; + + /* A base-address-selection entry. */ + if ((low & base_mask) == base_mask) + { + base_address = high; + continue; + } + + /* Otherwise, a location expression entry. */ + low += base_address; + high += base_address; + + length = extract_unsigned_integer (loc_ptr, 2); + loc_ptr += 2; + + if (pc >= low && pc < high) + { + *locexpr_length = length; + return loc_ptr; + } + + loc_ptr += length; + } +} + +/* This is the baton used when performing dwarf2 expression + evaluation. */ +struct dwarf_expr_baton +{ + struct frame_info *frame; + struct objfile *objfile; +}; + +/* Helper functions for dwarf2_evaluate_loc_desc. */ + +/* Using the frame specified in BATON, read register REGNUM. The lval + type will be returned in LVALP, and for lval_memory the register + save address will be returned in ADDRP. */ +static CORE_ADDR +dwarf_expr_read_reg (void *baton, int dwarf_regnum) +{ + struct dwarf_expr_baton *debaton = (struct dwarf_expr_baton *) baton; + CORE_ADDR result, save_addr; + enum lval_type lval_type; + char *buf; + int optimized, regnum, realnum, regsize; + + regnum = DWARF2_REG_TO_REGNUM (dwarf_regnum); + regsize = register_size (current_gdbarch, regnum); + buf = (char *) alloca (regsize); + + frame_register (debaton->frame, regnum, &optimized, &lval_type, &save_addr, + &realnum, buf); + /* NOTE: cagney/2003-05-22: This extract is assuming that a DWARF 2 + address is always unsigned. That may or may not be true. */ + result = extract_unsigned_integer (buf, regsize); + + return result; +} + +/* Read memory at ADDR (length LEN) into BUF. */ + +static void +dwarf_expr_read_mem (void *baton, char *buf, CORE_ADDR addr, size_t len) +{ + read_memory (addr, buf, len); +} + +/* Using the frame specified in BATON, find the location expression + describing the frame base. Return a pointer to it in START and + its length in LENGTH. */ +static void +dwarf_expr_frame_base (void *baton, unsigned char **start, size_t * length) +{ + /* FIXME: cagney/2003-03-26: This code should be using + get_frame_base_address(), and then implement a dwarf2 specific + this_base method. */ + struct symbol *framefunc; + struct dwarf_expr_baton *debaton = (struct dwarf_expr_baton *) baton; + + framefunc = get_frame_function (debaton->frame); + + if (SYMBOL_LOCATION_FUNCS (framefunc) == &dwarf2_loclist_funcs) + { + struct dwarf2_loclist_baton *symbaton; + symbaton = SYMBOL_LOCATION_BATON (framefunc); + *start = find_location_expression (symbaton, length, + get_frame_pc (debaton->frame)); + } + else + { + struct dwarf2_locexpr_baton *symbaton; + symbaton = SYMBOL_LOCATION_BATON (framefunc); + *length = symbaton->size; + *start = symbaton->data; + } + + if (*start == NULL) + error ("Could not find the frame base for \"%s\".", + SYMBOL_NATURAL_NAME (framefunc)); +} + +/* Using the objfile specified in BATON, find the address for the + current thread's thread-local storage with offset OFFSET. */ +static CORE_ADDR +dwarf_expr_tls_address (void *baton, CORE_ADDR offset) +{ + struct dwarf_expr_baton *debaton = (struct dwarf_expr_baton *) baton; + CORE_ADDR addr; + + if (target_get_thread_local_address_p ()) + addr = target_get_thread_local_address (inferior_ptid, + debaton->objfile, + offset); + /* It wouldn't be wrong here to try a gdbarch method, too; finding + TLS is an ABI-specific thing. But we don't do that yet. */ + else + error ("Cannot find thread-local variables on this target"); + + return addr; +} + +/* Evaluate a location description, starting at DATA and with length + SIZE, to find the current location of variable VAR in the context + of FRAME. */ +static struct value * +dwarf2_evaluate_loc_desc (struct symbol *var, struct frame_info *frame, + unsigned char *data, unsigned short size, + struct objfile *objfile) +{ + CORE_ADDR result; + struct value *retval; + struct dwarf_expr_baton baton; + struct dwarf_expr_context *ctx; + + if (size == 0) + { + retval = allocate_value (SYMBOL_TYPE (var)); + VALUE_LVAL (retval) = not_lval; + VALUE_OPTIMIZED_OUT (retval) = 1; + } + + baton.frame = frame; + baton.objfile = objfile; + + ctx = new_dwarf_expr_context (); + ctx->baton = &baton; + ctx->read_reg = dwarf_expr_read_reg; + ctx->read_mem = dwarf_expr_read_mem; + ctx->get_frame_base = dwarf_expr_frame_base; + ctx->get_tls_address = dwarf_expr_tls_address; + + dwarf_expr_eval (ctx, data, size); + result = dwarf_expr_fetch (ctx, 0); + + if (ctx->in_reg) + { + int regnum = DWARF2_REG_TO_REGNUM (result); + retval = value_from_register (SYMBOL_TYPE (var), regnum, frame); + } + else + { + retval = allocate_value (SYMBOL_TYPE (var)); + VALUE_BFD_SECTION (retval) = SYMBOL_BFD_SECTION (var); + + VALUE_LVAL (retval) = lval_memory; + VALUE_LAZY (retval) = 1; + VALUE_ADDRESS (retval) = result; + } + + free_dwarf_expr_context (ctx); + + return retval; +} + + + + + +/* Helper functions and baton for dwarf2_loc_desc_needs_frame. */ + +struct needs_frame_baton +{ + int needs_frame; +}; + +/* Reads from registers do require a frame. */ +static CORE_ADDR +needs_frame_read_reg (void *baton, int regnum) +{ + struct needs_frame_baton *nf_baton = baton; + nf_baton->needs_frame = 1; + return 1; +} + +/* Reads from memory do not require a frame. */ +static void +needs_frame_read_mem (void *baton, char *buf, CORE_ADDR addr, size_t len) +{ + memset (buf, 0, len); +} + +/* Frame-relative accesses do require a frame. */ +static void +needs_frame_frame_base (void *baton, unsigned char **start, size_t * length) +{ + static char lit0 = DW_OP_lit0; + struct needs_frame_baton *nf_baton = baton; + + *start = &lit0; + *length = 1; + + nf_baton->needs_frame = 1; +} + +/* Thread-local accesses do require a frame. */ +static CORE_ADDR +needs_frame_tls_address (void *baton, CORE_ADDR offset) +{ + struct needs_frame_baton *nf_baton = baton; + nf_baton->needs_frame = 1; + return 1; +} + +/* Return non-zero iff the location expression at DATA (length SIZE) + requires a frame to evaluate. */ + +static int +dwarf2_loc_desc_needs_frame (unsigned char *data, unsigned short size) +{ + struct needs_frame_baton baton; + struct dwarf_expr_context *ctx; + int in_reg; + + baton.needs_frame = 0; + + ctx = new_dwarf_expr_context (); + ctx->baton = &baton; + ctx->read_reg = needs_frame_read_reg; + ctx->read_mem = needs_frame_read_mem; + ctx->get_frame_base = needs_frame_frame_base; + ctx->get_tls_address = needs_frame_tls_address; + + dwarf_expr_eval (ctx, data, size); + + in_reg = ctx->in_reg; + + free_dwarf_expr_context (ctx); + + return baton.needs_frame || in_reg; +} + +static void +dwarf2_tracepoint_var_ref (struct symbol * symbol, struct agent_expr * ax, + struct axs_value * value, unsigned char *data, + int size) +{ + if (size == 0) + error ("Symbol \"%s\" has been optimized out.", + SYMBOL_PRINT_NAME (symbol)); + + if (size == 1 + && data[0] >= DW_OP_reg0 + && data[0] <= DW_OP_reg31) + { + value->kind = axs_lvalue_register; + value->u.reg = data[0] - DW_OP_reg0; + } + else if (data[0] == DW_OP_regx) + { + ULONGEST reg; + read_uleb128 (data + 1, data + size, ®); + value->kind = axs_lvalue_register; + value->u.reg = reg; + } + else if (data[0] == DW_OP_fbreg) + { + /* And this is worse than just minimal; we should honor the frame base + as above. */ + int frame_reg; + LONGEST frame_offset; + unsigned char *buf_end; + + buf_end = read_sleb128 (data + 1, data + size, &frame_offset); + if (buf_end != data + size) + error ("Unexpected opcode after DW_OP_fbreg for symbol \"%s\".", + SYMBOL_PRINT_NAME (symbol)); + + TARGET_VIRTUAL_FRAME_POINTER (ax->scope, &frame_reg, &frame_offset); + ax_reg (ax, frame_reg); + ax_const_l (ax, frame_offset); + ax_simple (ax, aop_add); + + ax_const_l (ax, frame_offset); + ax_simple (ax, aop_add); + value->kind = axs_lvalue_memory; + } + else + error ("Unsupported DWARF opcode in the location of \"%s\".", + SYMBOL_PRINT_NAME (symbol)); +} + +/* Return the value of SYMBOL in FRAME using the DWARF-2 expression + evaluator to calculate the location. */ +static struct value * +locexpr_read_variable (struct symbol *symbol, struct frame_info *frame) +{ + struct dwarf2_locexpr_baton *dlbaton = SYMBOL_LOCATION_BATON (symbol); + struct value *val; + val = dwarf2_evaluate_loc_desc (symbol, frame, dlbaton->data, dlbaton->size, + dlbaton->objfile); + + return val; +} + +/* Return non-zero iff we need a frame to evaluate SYMBOL. */ +static int +locexpr_read_needs_frame (struct symbol *symbol) +{ + struct dwarf2_locexpr_baton *dlbaton = SYMBOL_LOCATION_BATON (symbol); + return dwarf2_loc_desc_needs_frame (dlbaton->data, dlbaton->size); +} + +/* Print a natural-language description of SYMBOL to STREAM. */ +static int +locexpr_describe_location (struct symbol *symbol, struct ui_file *stream) +{ + /* FIXME: be more extensive. */ + struct dwarf2_locexpr_baton *dlbaton = SYMBOL_LOCATION_BATON (symbol); + + if (dlbaton->size == 1 + && dlbaton->data[0] >= DW_OP_reg0 + && dlbaton->data[0] <= DW_OP_reg31) + { + int regno = DWARF2_REG_TO_REGNUM (dlbaton->data[0] - DW_OP_reg0); + fprintf_filtered (stream, + "a variable in register %s", REGISTER_NAME (regno)); + return 1; + } + + /* The location expression for a TLS variable looks like this (on a + 64-bit LE machine): + + DW_AT_location : 10 byte block: 3 4 0 0 0 0 0 0 0 e0 + (DW_OP_addr: 4; DW_OP_GNU_push_tls_address) + + 0x3 is the encoding for DW_OP_addr, which has an operand as long + as the size of an address on the target machine (here is 8 + bytes). 0xe0 is the encoding for DW_OP_GNU_push_tls_address. + The operand represents the offset at which the variable is within + the thread local storage. */ + + if (dlbaton->size > 1 + && dlbaton->data[dlbaton->size - 1] == DW_OP_GNU_push_tls_address) + if (dlbaton->data[0] == DW_OP_addr) + { + int bytes_read; + CORE_ADDR offset = dwarf2_read_address (&dlbaton->data[1], + &dlbaton->data[dlbaton->size - 1], + &bytes_read); + fprintf_filtered (stream, + "a thread-local variable at offset %s in the " + "thread-local storage for `%s'", + paddr_nz (offset), dlbaton->objfile->name); + return 1; + } + + + fprintf_filtered (stream, + "a variable with complex or multiple locations (DWARF2)"); + return 1; +} + + +/* Describe the location of SYMBOL as an agent value in VALUE, generating + any necessary bytecode in AX. + + NOTE drow/2003-02-26: This function is extremely minimal, because + doing it correctly is extremely complicated and there is no + publicly available stub with tracepoint support for me to test + against. When there is one this function should be revisited. */ + +static void +locexpr_tracepoint_var_ref (struct symbol * symbol, struct agent_expr * ax, + struct axs_value * value) +{ + struct dwarf2_locexpr_baton *dlbaton = SYMBOL_LOCATION_BATON (symbol); + + dwarf2_tracepoint_var_ref (symbol, ax, value, dlbaton->data, dlbaton->size); +} + +/* The set of location functions used with the DWARF-2 expression + evaluator. */ +struct location_funcs dwarf2_locexpr_funcs = { + locexpr_read_variable, + locexpr_read_needs_frame, + locexpr_describe_location, + locexpr_tracepoint_var_ref +}; + + +/* Wrapper functions for location lists. These generally find + the appropriate location expression and call something above. */ + +/* Return the value of SYMBOL in FRAME using the DWARF-2 expression + evaluator to calculate the location. */ +static struct value * +loclist_read_variable (struct symbol *symbol, struct frame_info *frame) +{ + struct dwarf2_loclist_baton *dlbaton = SYMBOL_LOCATION_BATON (symbol); + struct value *val; + unsigned char *data; + size_t size; + + data = find_location_expression (dlbaton, &size, + frame ? get_frame_pc (frame) : 0); + if (data == NULL) + error ("Variable \"%s\" is not available.", SYMBOL_NATURAL_NAME (symbol)); + + val = dwarf2_evaluate_loc_desc (symbol, frame, data, size, dlbaton->objfile); + + return val; +} + +/* Return non-zero iff we need a frame to evaluate SYMBOL. */ +static int +loclist_read_needs_frame (struct symbol *symbol) +{ + /* If there's a location list, then assume we need to have a frame + to choose the appropriate location expression. With tracking of + global variables this is not necessarily true, but such tracking + is disabled in GCC at the moment until we figure out how to + represent it. */ + + return 1; +} + +/* Print a natural-language description of SYMBOL to STREAM. */ +static int +loclist_describe_location (struct symbol *symbol, struct ui_file *stream) +{ + /* FIXME: Could print the entire list of locations. */ + fprintf_filtered (stream, "a variable with multiple locations"); + return 1; +} + +/* Describe the location of SYMBOL as an agent value in VALUE, generating + any necessary bytecode in AX. */ +static void +loclist_tracepoint_var_ref (struct symbol * symbol, struct agent_expr * ax, + struct axs_value * value) +{ + struct dwarf2_loclist_baton *dlbaton = SYMBOL_LOCATION_BATON (symbol); + unsigned char *data; + size_t size; + + data = find_location_expression (dlbaton, &size, ax->scope); + if (data == NULL) + error ("Variable \"%s\" is not available.", SYMBOL_NATURAL_NAME (symbol)); + + dwarf2_tracepoint_var_ref (symbol, ax, value, data, size); +} + +/* The set of location functions used with the DWARF-2 expression + evaluator and location lists. */ +struct location_funcs dwarf2_loclist_funcs = { + loclist_read_variable, + loclist_read_needs_frame, + loclist_describe_location, + loclist_tracepoint_var_ref +}; diff --git a/gdb/dwarf2loc.h b/gdb/dwarf2loc.h new file mode 100644 index 0000000..321cb03 --- /dev/null +++ b/gdb/dwarf2loc.h @@ -0,0 +1,68 @@ +/* Dwarf2 location expression support for GDB. + Copyright 2003 Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#if !defined (DWARF2LOC_H) +#define DWARF2LOC_H + +/* This header is private to the DWARF-2 reader. It is shared between + dwarf2read.c and dwarf2loc.c. */ + +/* The symbol location baton types used by the DWARF-2 reader (i.e. + SYMBOL_LOCATION_BATON for a LOC_COMPUTED symbol). "struct + dwarf2_locexpr_baton" is for a symbol with a single location + expression; "struct dwarf2_loclist_baton" is for a symbol with a + location list. */ + +struct dwarf2_locexpr_baton +{ + /* Pointer to the start of the location expression. */ + unsigned char *data; + + /* Length of the location expression. */ + unsigned short size; + + /* The objfile containing the symbol whose location we're computing. */ + struct objfile *objfile; +}; + +struct dwarf2_loclist_baton +{ + /* The initial base address for the location list, based on the compilation + unit. */ + CORE_ADDR base_address; + + /* Pointer to the start of the location list. */ + unsigned char *data; + + /* Length of the location list. */ + unsigned short size; + + /* The objfile containing the symbol whose location we're computing. */ + /* Used (only???) by thread local variables. The objfile in which + this symbol is defined. To find a thread-local variable (e.g., a + variable declared with the `__thread' storage class), we may need + to know which object file it's in. */ + struct objfile *objfile; +}; + +extern struct location_funcs dwarf2_locexpr_funcs; +extern struct location_funcs dwarf2_loclist_funcs; + +#endif diff --git a/gdb/exec.h b/gdb/exec.h new file mode 100644 index 0000000..e9c2d17 --- /dev/null +++ b/gdb/exec.h @@ -0,0 +1,39 @@ +/* Work with executable files, for GDB, the GNU debugger. + + Copyright 2003 Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#ifndef EXEC_H +#define EXEC_H + +#include "target.h" + +struct section_table; +struct target_ops; +struct bfd; + +struct target_ops exec_ops; + +/* Builds a section table, given args BFD, SECTABLE_PTR, SECEND_PTR. + Returns 0 if OK, 1 on error. */ + +extern int build_section_table (struct bfd *, struct section_table **, + struct section_table **); + +#endif diff --git a/gdb/frame-base.c b/gdb/frame-base.c new file mode 100644 index 0000000..66a0106 --- /dev/null +++ b/gdb/frame-base.c @@ -0,0 +1,150 @@ +/* Definitions for frame address handler, for GDB, the GNU debugger. + + Copyright 2003 Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#include "defs.h" +#include "frame-base.h" +#include "frame.h" + +/* A default frame base implementations. If it wasn't for the old + DEPRECATED_FRAME_LOCALS_ADDRESS and DEPRECATED_FRAME_ARGS_ADDRESS, + these could be combined into a single function. All architectures + really need to override this. */ + +static CORE_ADDR +default_frame_base_address (struct frame_info *next_frame, void **this_cache) +{ + struct frame_info *this_frame = get_prev_frame (next_frame); + return get_frame_base (this_frame); /* sigh! */ +} + +static CORE_ADDR +default_frame_locals_address (struct frame_info *next_frame, void **this_cache) +{ + if (DEPRECATED_FRAME_LOCALS_ADDRESS_P ()) + { + /* This is bad. The computation of per-frame locals address + should use a per-frame frame-base. */ + struct frame_info *this_frame = get_prev_frame (next_frame); + return DEPRECATED_FRAME_LOCALS_ADDRESS (this_frame); + } + return default_frame_base_address (next_frame, this_cache); +} + +static CORE_ADDR +default_frame_args_address (struct frame_info *next_frame, void **this_cache) +{ + if (DEPRECATED_FRAME_ARGS_ADDRESS_P ()) + { + struct frame_info *this_frame = get_prev_frame (next_frame); + return DEPRECATED_FRAME_ARGS_ADDRESS (this_frame); + } + return default_frame_base_address (next_frame, this_cache); +} + +const struct frame_base default_frame_base = { + NULL, /* No parent. */ + default_frame_base_address, + default_frame_locals_address, + default_frame_args_address +}; + +static struct gdbarch_data *frame_base_data; + +struct frame_base_table +{ + frame_base_sniffer_ftype **sniffer; + const struct frame_base *default_base; + int nr; +}; + +static void * +frame_base_init (struct gdbarch *gdbarch) +{ + struct frame_base_table *table = XCALLOC (1, struct frame_base_table); + table->default_base = &default_frame_base; + return table; +} + +static struct frame_base_table * +frame_base_table (struct gdbarch *gdbarch) +{ + struct frame_base_table *table = gdbarch_data (gdbarch, frame_base_data); + if (table == NULL) + { + /* ULGH, called during architecture initialization. Patch + things up. */ + table = frame_base_init (gdbarch); + set_gdbarch_data (gdbarch, frame_base_data, table); + } + return table; +} + +/* Append a predicate to the end of the table. */ +static void +append_predicate (struct frame_base_table *table, + frame_base_sniffer_ftype *sniffer) +{ + table->sniffer = xrealloc (table->sniffer, + ((table->nr + 1) + * sizeof (frame_base_sniffer_ftype *))); + table->sniffer[table->nr] = sniffer; + table->nr++; +} + +void +frame_base_append_sniffer (struct gdbarch *gdbarch, + frame_base_sniffer_ftype *sniffer) +{ + struct frame_base_table *table = frame_base_table (gdbarch); + append_predicate (table, sniffer); +} + +void +frame_base_set_default (struct gdbarch *gdbarch, + const struct frame_base *default_base) +{ + struct frame_base_table *table = frame_base_table (gdbarch); + table->default_base = default_base; +} + +const struct frame_base * +frame_base_find_by_frame (struct frame_info *next_frame) +{ + struct gdbarch *gdbarch = get_frame_arch (next_frame); + struct frame_base_table *table = frame_base_table (gdbarch); + int i; + for (i = 0; i < table->nr; i++) + { + const struct frame_base *desc = NULL; + desc = table->sniffer[i] (next_frame); + if (desc != NULL) + return desc; + } + return table->default_base; +} + +extern initialize_file_ftype _initialize_frame_base; /* -Wmissing-prototypes */ + +void +_initialize_frame_base (void) +{ + frame_base_data = register_gdbarch_data (frame_base_init); +} diff --git a/gdb/frame-base.h b/gdb/frame-base.h new file mode 100644 index 0000000..680e9d5 --- /dev/null +++ b/gdb/frame-base.h @@ -0,0 +1,93 @@ +/* Definitions for a frame base, for GDB, the GNU debugger. + + Copyright 2003 Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#if !defined (FRAME_BASE_H) +#define FRAME_BASE_H 1 + +struct frame_info; +struct frame_id; +struct frame_unwind; +struct frame_base; +struct gdbarch; +struct regcache; + +/* Assuming the frame chain: (outer) prev <-> this <-> next (inner); + and that this is a `normal frame'; use the NEXT frame, and its + register unwind method, to determine the address of THIS frame's + `base'. + + The exact meaning of `base' is highly dependant on the type of the + debug info. It is assumed that dwarf2, stabs, ... will each + provide their own methods. + + A typical implmentation will return the same value for base, + locals-base and args-base. That value, however, will likely be + different to the frame ID's stack address. */ + +/* A generic base address. */ + +typedef CORE_ADDR (frame_this_base_ftype) (struct frame_info *next_frame, + void **this_base_cache); + +/* The base address of the frame's local variables. */ + +typedef CORE_ADDR (frame_this_locals_ftype) (struct frame_info *next_frame, + void **this_base_cache); + +/* The base address of the frame's arguments / parameters. */ + +typedef CORE_ADDR (frame_this_args_ftype) (struct frame_info *next_frame, + void **this_base_cache); + +struct frame_base +{ + /* If non-NULL, a low-level unwinder that shares its implementation + with this high-level frame-base method. */ + const struct frame_unwind *unwind; + frame_this_base_ftype *this_base; + frame_this_locals_ftype *this_locals; + frame_this_args_ftype *this_args; +}; + +/* Given the NEXT frame, return the frame base methods for THIS frame, + or NULL if it can't handle THIS frame. */ + +typedef const struct frame_base *(frame_base_sniffer_ftype) (struct frame_info *next_frame); + +/* Append a frame base sniffer to the list. The sniffers are polled + in the order that they are appended. */ + +extern void frame_base_append_sniffer (struct gdbarch *gdbarch, + frame_base_sniffer_ftype *sniffer); + +/* Set the default frame base. If all else fails, this one is + returned. If this isn't set, the default is to use legacy code + that uses things like the frame ID's base (ulgh!). */ + +extern void frame_base_set_default (struct gdbarch *gdbarch, + const struct frame_base *def); + +/* Iterate through the list of frame base handlers until one returns + an implementation. */ + +extern const struct frame_base *frame_base_find_by_frame (struct frame_info *next_frame); + +#endif diff --git a/gdb/frame-unwind.c b/gdb/frame-unwind.c new file mode 100644 index 0000000..fc5a821 --- /dev/null +++ b/gdb/frame-unwind.c @@ -0,0 +1,99 @@ +/* Definitions for frame unwinder, for GDB, the GNU debugger. + + Copyright 2003 Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#include "defs.h" +#include "frame.h" +#include "frame-unwind.h" +#include "gdb_assert.h" +#include "dummy-frame.h" + +static struct gdbarch_data *frame_unwind_data; + +struct frame_unwind_table +{ + frame_unwind_sniffer_ftype **sniffer; + int nr; +}; + +/* Append a predicate to the end of the table. */ +static void +append_predicate (struct frame_unwind_table *table, + frame_unwind_sniffer_ftype *sniffer) +{ + table->sniffer = xrealloc (table->sniffer, ((table->nr + 1) + * sizeof (frame_unwind_sniffer_ftype *))); + table->sniffer[table->nr] = sniffer; + table->nr++; +} + +static void * +frame_unwind_init (struct gdbarch *gdbarch) +{ + struct frame_unwind_table *table = XCALLOC (1, struct frame_unwind_table); + append_predicate (table, dummy_frame_sniffer); + return table; +} + +void +frame_unwind_append_sniffer (struct gdbarch *gdbarch, + frame_unwind_sniffer_ftype *sniffer) +{ + struct frame_unwind_table *table = + gdbarch_data (gdbarch, frame_unwind_data); + if (table == NULL) + { + /* ULGH, called during architecture initialization. Patch + things up. */ + table = frame_unwind_init (gdbarch); + set_gdbarch_data (gdbarch, frame_unwind_data, table); + } + append_predicate (table, sniffer); +} + +const struct frame_unwind * +frame_unwind_find_by_frame (struct frame_info *next_frame) +{ + int i; + struct gdbarch *gdbarch = get_frame_arch (next_frame); + struct frame_unwind_table *table = gdbarch_data (gdbarch, frame_unwind_data); + if (!DEPRECATED_USE_GENERIC_DUMMY_FRAMES) + /* Seriously old code. Don't even try to use this new mechanism. + (Note: The variable USE_GENERIC_DUMMY_FRAMES is deprecated, not + the dummy frame mechanism. All architectures should be using + generic dummy frames). */ + return legacy_saved_regs_unwind; + for (i = 0; i < table->nr; i++) + { + const struct frame_unwind *desc; + desc = table->sniffer[i] (next_frame); + if (desc != NULL) + return desc; + } + return legacy_saved_regs_unwind; +} + +extern initialize_file_ftype _initialize_frame_unwind; /* -Wmissing-prototypes */ + +void +_initialize_frame_unwind (void) +{ + frame_unwind_data = register_gdbarch_data (frame_unwind_init); +} diff --git a/gdb/frame-unwind.h b/gdb/frame-unwind.h new file mode 100644 index 0000000..8d17280 --- /dev/null +++ b/gdb/frame-unwind.h @@ -0,0 +1,141 @@ +/* Definitions for a frame unwinder, for GDB, the GNU debugger. + + Copyright 2003 Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#if !defined (FRAME_UNWIND_H) +#define FRAME_UNWIND_H 1 + +struct frame_info; +struct frame_id; +struct frame_unwind; +struct gdbarch; +struct regcache; + +#include "frame.h" /* For enum frame_type. */ + +/* The following unwind functions assume a chain of frames forming the + sequence: (outer) prev <-> this <-> next (inner). All the + functions are called with called with the next frame's `struct + frame_info' and and this frame's prologue cache. + + THIS frame's register values can be obtained by unwinding NEXT + frame's registers (a recursive operation). + + THIS frame's prologue cache can be used to cache information such + as where this frame's prologue stores the previous frame's + registers. */ + +/* Assuming the frame chain: (outer) prev <-> this <-> next (inner); + use the NEXT frame, and its register unwind method, to determine + the frame ID of THIS frame. + + A frame ID provides an invariant that can be used to re-identify an + instance of a frame. It is a combination of the frame's `base' and + the frame's function's code address. + + Traditionally, THIS frame's ID was determined by examining THIS + frame's function's prologue, and identifying the register/offset + used as THIS frame's base. + + Example: An examination of THIS frame's prologue reveals that, on + entry, it saves the PC(+12), SP(+8), and R1(+4) registers + (decrementing the SP by 12). Consequently, the frame ID's base can + be determined by adding 12 to the THIS frame's stack-pointer, and + the value of THIS frame's SP can be obtained by unwinding the NEXT + frame's SP. + + THIS_PROLOGUE_CACHE can be used to share any prolog analysis data + with the other unwind methods. Memory for that cache should be + allocated using frame_obstack_zalloc(). */ + +typedef void (frame_this_id_ftype) (struct frame_info *next_frame, + void **this_prologue_cache, + struct frame_id *this_id); + +/* Assuming the frame chain: (outer) prev <-> this <-> next (inner); + use the NEXT frame, and its register unwind method, to unwind THIS + frame's registers (returning the value of the specified register + REGNUM in the previous frame). + + Traditionally, THIS frame's registers were unwound by examining + THIS frame's function's prologue and identifying which registers + that prolog code saved on the stack. + + Example: An examination of THIS frame's prologue reveals that, on + entry, it saves the PC(+12), SP(+8), and R1(+4) registers + (decrementing the SP by 12). Consequently, the value of the PC + register in the previous frame is found in memory at SP+12, and + THIS frame's SP can be obtained by unwinding the NEXT frame's SP. + + Why not pass in THIS_FRAME? By passing in NEXT frame and THIS + cache, the supplied parameters are consistent with the sibling + function THIS_ID. + + Can the code call ``frame_register (get_prev_frame (NEXT_FRAME))''? + Won't the call frame_register (THIS_FRAME) be faster? Well, + ignoring the possability that the previous frame does not yet + exist, the ``frame_register (FRAME)'' function is expanded to + ``frame_register_unwind (get_next_frame (FRAME)'' and hence that + call will expand to ``frame_register_unwind (get_next_frame + (get_prev_frame (NEXT_FRAME)))''. Might as well call + ``frame_register_unwind (NEXT_FRAME)'' directly. + + THIS_PROLOGUE_CACHE can be used to share any prolog analysis data + with the other unwind methods. Memory for that cache should be + allocated using frame_obstack_zalloc(). */ + +typedef void (frame_prev_register_ftype) (struct frame_info *next_frame, + void **this_prologue_cache, + int prev_regnum, + int *optimized, + enum lval_type * lvalp, + CORE_ADDR *addrp, + int *realnump, void *valuep); + +struct frame_unwind +{ + /* The frame's type. Should this instead be a collection of + predicates that test the frame for various attributes? */ + enum frame_type type; + /* Should an attribute indicating the frame's address-in-block go + here? */ + frame_this_id_ftype *this_id; + frame_prev_register_ftype *prev_register; +}; + +/* Given the NEXT frame, take a wiff of THIS frame's registers (namely + the PC and attributes) and if it is the applicable unwinder return + the unwind methods, or NULL if it is not. */ + +typedef const struct frame_unwind *(frame_unwind_sniffer_ftype) (struct frame_info *next_frame); + +/* Add a frame sniffer to the list. The predicates are polled in the + order that they are appended. The initial list contains the dummy + frame sniffer. */ + +extern void frame_unwind_append_sniffer (struct gdbarch *gdbarch, + frame_unwind_sniffer_ftype *sniffer); + +/* Iterate through the next frame's sniffers until one returns with an + unwinder implementation. */ + +extern const struct frame_unwind *frame_unwind_find_by_frame (struct frame_info *next_frame); + +#endif diff --git a/gdb/gdb_gcore.sh b/gdb/gdb_gcore.sh new file mode 100755 index 0000000..9b42808 --- /dev/null +++ b/gdb/gdb_gcore.sh @@ -0,0 +1,81 @@ +#!/bin/sh + +# Copyright 2003 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# Please email any bugs, comments, and/or additions to this file to: +# bug-gdb@prep.ai.mit.edu + +# +# gcore.sh +# Script to generate a core file of a running program. +# It starts up gdb, attaches to the given PID and invokes the gcore command. +# + +if [ "$#" -eq "0" ] +then + echo "usage: gcore [-o filename] pid" + exit 2 +fi + +# Need to check for -o option, but set default basename to "core". +name=core + +if [ "$1" = "-o" ] +then + if [ "$#" -lt "3" ] + then + # Not enough arguments. + echo "usage: gcore [-o filename] pid" + exit 2 + fi + name=$2 + + # Shift over to start of pid list + shift; shift +fi + +# Initialise return code. +rc=0 + +# Loop through pids +for pid in $* +do + # Write gdb script for pid $pid. + + # Avoid need for temporary files by using funky "here + # document" feature of sh. + + /usr/bin/gdb > /dev/null << EOF + attach $pid + gcore $name.$pid + detach + quit +EOF + + if [ -r $name.$pid ] ; then + rc=0 + else + echo gcore: failed to create $name.$pid + rc=1 + break + fi + + +done + +exit $rc + diff --git a/gdb/glibc-tdep.c b/gdb/glibc-tdep.c new file mode 100644 index 0000000..04bb683 --- /dev/null +++ b/gdb/glibc-tdep.c @@ -0,0 +1,101 @@ +/* Target-dependent code for the GNU C Library (glibc). + + Copyright 2002, 2003 Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#include "defs.h" +#include "frame.h" +#include "symtab.h" +#include "symfile.h" +#include "objfiles.h" + +#include "glibc-tdep.h" + +/* Calling functions in shared libraries. */ + +/* Find the minimal symbol named NAME, and return both the minsym + struct and its objfile. This probably ought to be in minsym.c, but + everything there is trying to deal with things like C++ and + SOFUN_ADDRESS_MAYBE_TURQUOISE, ... Since this is so simple, it may + be considered too special-purpose for general consumption. */ + +static struct minimal_symbol * +find_minsym_and_objfile (char *name, struct objfile **objfile_p) +{ + struct objfile *objfile; + + ALL_OBJFILES (objfile) + { + struct minimal_symbol *msym; + + ALL_OBJFILE_MSYMBOLS (objfile, msym) + { + if (SYMBOL_LINKAGE_NAME (msym) + && strcmp (SYMBOL_LINKAGE_NAME (msym), name) == 0) + { + *objfile_p = objfile; + return msym; + } + } + } + + return 0; +} + +/* See the comments for SKIP_SOLIB_RESOLVER at the top of infrun.c. + This function: + 1) decides whether a PLT has sent us into the linker to resolve + a function reference, and + 2) if so, tells us where to set a temporary breakpoint that will + trigger when the dynamic linker is done. */ + +CORE_ADDR +glibc_skip_solib_resolver (struct gdbarch *gdbarch, CORE_ADDR pc) +{ + /* The GNU dynamic linker is part of the GNU C library, and is used + by all GNU systems (GNU/Hurd, GNU/Linux). An unresolved PLT + entry points to "_dl_runtime_resolve", which calls "fixup" to + patch the PLT, and then passes control to the function. + + We look for the symbol `_dl_runtime_resolve', and find `fixup' in + the same objfile. If we are at the entry point of `fixup', then + we set a breakpoint at the return address (at the top of the + stack), and continue. + + It's kind of gross to do all these checks every time we're + called, since they don't change once the executable has gotten + started. But this is only a temporary hack --- upcoming versions + of GNU/Linux will provide a portable, efficient interface for + debugging programs that use shared libraries. */ + + struct objfile *objfile; + struct minimal_symbol *resolver + = find_minsym_and_objfile ("_dl_runtime_resolve", &objfile); + + if (resolver) + { + struct minimal_symbol *fixup + = lookup_minimal_symbol ("fixup", NULL, objfile); + + if (fixup && SYMBOL_VALUE_ADDRESS (fixup) == pc) + return frame_pc_unwind (get_current_frame ()); + } + + return 0; +} diff --git a/gdb/glibc-tdep.h b/gdb/glibc-tdep.h new file mode 100644 index 0000000..75598d5 --- /dev/null +++ b/gdb/glibc-tdep.h @@ -0,0 +1,30 @@ +/* Target-dependent code for the GNU C Library (glibc). + + Copyright 2002, 2003 Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#ifndef GLIBC_TDEP_H +#define GLIBC_TDEP_H + +struct gdbarch; + +extern CORE_ADDR glibc_skip_solib_resolver (struct gdbarch *gdbarch, + CORE_ADDR); + +#endif /* glibc-tdep.h */ diff --git a/gdb/hppa-hpux-tdep.c b/gdb/hppa-hpux-tdep.c new file mode 100644 index 0000000..f9757c9 --- /dev/null +++ b/gdb/hppa-hpux-tdep.c @@ -0,0 +1,176 @@ +/* Target-dependent code for HPUX running on PA-RISC, for GDB. + + Copyright 2002, 2003 Free Software Foundation, Inc. + +This file is part of GDB. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include "defs.h" +#include "arch-utils.h" +#include "gdbcore.h" +#include "osabi.h" +#include "gdb_string.h" +#include "frame.h" + +/* Forward declarations. */ +extern void _initialize_hppa_hpux_tdep (void); +extern initialize_file_ftype _initialize_hppa_hpux_tdep; + +/* FIXME: brobecker 2002-12-25. The following functions will eventually + become static, after the multiarching conversion is done. */ +int hppa_hpux_pc_in_sigtramp (CORE_ADDR pc, char *name); +void hppa32_hpux_frame_saved_pc_in_sigtramp (struct frame_info *fi, + CORE_ADDR *tmp); +void hppa32_hpux_frame_base_before_sigtramp (struct frame_info *fi, + CORE_ADDR *tmp); +void hppa32_hpux_frame_find_saved_regs_in_sigtramp (struct frame_info *fi, + CORE_ADDR *fsr); +void hppa64_hpux_frame_saved_pc_in_sigtramp (struct frame_info *fi, + CORE_ADDR *tmp); +void hppa64_hpux_frame_base_before_sigtramp (struct frame_info *fi, + CORE_ADDR *tmp); +void hppa64_hpux_frame_find_saved_regs_in_sigtramp (struct frame_info *fi, + CORE_ADDR *fsr); + +int +hppa_hpux_pc_in_sigtramp (CORE_ADDR pc, char *name) +{ + /* Actually, for a PA running HPUX the kernel calls the signal handler + without an intermediate trampoline. Luckily the kernel always sets + the return pointer for the signal handler to point to _sigreturn. */ + return (name && (strcmp ("_sigreturn", name) == 0)); +} + +/* For hppa32_hpux_frame_saved_pc_in_sigtramp, + hppa32_hpux_frame_base_before_sigtramp and + hppa32_hpux_frame_find_saved_regs_in_sigtramp: + + The signal context structure pointer is always saved at the base + of the frame which "calls" the signal handler. We only want to find + the hardware save state structure, which lives 10 32bit words into + sigcontext structure. + + Within the hardware save state structure, registers are found in the + same order as the register numbers in GDB. + + At one time we peeked at %r31 rather than the PC queues to determine + what instruction took the fault. This was done on purpose, but I don't + remember why. Looking at the PC queues is really the right way, and + I don't remember why that didn't work when this code was originally + written. */ + +void +hppa32_hpux_frame_saved_pc_in_sigtramp (struct frame_info *fi, CORE_ADDR *tmp) +{ + *tmp = read_memory_integer (get_frame_base (fi) + (43 * 4), 4); +} + +void +hppa32_hpux_frame_base_before_sigtramp (struct frame_info *fi, + CORE_ADDR *tmp) +{ + *tmp = read_memory_integer (get_frame_base (fi) + (40 * 4), 4); +} + +void +hppa32_hpux_frame_find_saved_regs_in_sigtramp (struct frame_info *fi, + CORE_ADDR *fsr) +{ + int i; + const CORE_ADDR tmp = get_frame_base (fi) + (10 * 4); + + for (i = 0; i < NUM_REGS; i++) + { + if (i == SP_REGNUM) + fsr[SP_REGNUM] = read_memory_integer (tmp + SP_REGNUM * 4, 4); + else + fsr[i] = tmp + i * 4; + } +} + +/* For hppa64_hpux_frame_saved_pc_in_sigtramp, + hppa64_hpux_frame_base_before_sigtramp and + hppa64_hpux_frame_find_saved_regs_in_sigtramp: + + These functions are the PA64 ABI equivalents of the 32bits counterparts + above. See the comments there. + + For PA64, the save_state structure is at an offset of 24 32-bit words + from the sigcontext structure. The 64 bit general registers are at an + offset of 640 bytes from the beginning of the save_state structure, + and the floating pointer register are at an offset of 256 bytes from + the beginning of the save_state structure. */ + +void +hppa64_hpux_frame_saved_pc_in_sigtramp (struct frame_info *fi, CORE_ADDR *tmp) +{ + *tmp = read_memory_integer + (get_frame_base (fi) + (24 * 4) + 640 + (33 * 8), 8); +} + +void +hppa64_hpux_frame_base_before_sigtramp (struct frame_info *fi, + CORE_ADDR *tmp) +{ + *tmp = read_memory_integer + (get_frame_base (fi) + (24 * 4) + 640 + (30 * 8), 8); +} + +void +hppa64_hpux_frame_find_saved_regs_in_sigtramp (struct frame_info *fi, + CORE_ADDR *fsr) +{ + int i; + const CORE_ADDR tmp1 = get_frame_base (fi) + (24 * 4) + 640; + const CORE_ADDR tmp2 = get_frame_base (fi) + (24 * 4) + 256; + + for (i = 0; i < NUM_REGS; i++) + { + if (i == SP_REGNUM) + fsr[SP_REGNUM] = read_memory_integer (tmp1 + SP_REGNUM * 8, 8); + else if (i >= FP0_REGNUM) + fsr[i] = tmp2 + (i - FP0_REGNUM) * 8; + else + fsr[i] = tmp1 + i * 8; + } +} + +static void +hppa_hpux_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) +{ + set_gdbarch_pc_in_sigtramp (gdbarch, hppa_hpux_pc_in_sigtramp); +} + +static void +hppa_hpux_som_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) +{ + hppa_hpux_init_abi (info, gdbarch); +} + +static void +hppa_hpux_elf_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) +{ + hppa_hpux_init_abi (info, gdbarch); +} + +void +_initialize_hppa_hpux_tdep (void) +{ + gdbarch_register_osabi (bfd_arch_hppa, 0, GDB_OSABI_HPUX_SOM, + hppa_hpux_som_init_abi); + gdbarch_register_osabi (bfd_arch_hppa, bfd_mach_hppa20w, GDB_OSABI_HPUX_ELF, + hppa_hpux_elf_init_abi); +} diff --git a/gdb/hppa-tdep.h b/gdb/hppa-tdep.h new file mode 100644 index 0000000..05a4e89 --- /dev/null +++ b/gdb/hppa-tdep.h @@ -0,0 +1,32 @@ +/* Common target dependent code for GDB on HPPA systems. + Copyright 2003 Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#ifndef HPPA_TDEP_H +#define HPPA_TDEP_H + +/* Target-dependent structure in gdbarch. */ +struct gdbarch_tdep +{ + /* The number of bytes in an address. For now, this field is designed + to allow us to differentiate hppa32 from hppa64 targets. */ + int bytes_per_address; +}; + +#endif /* HPPA_TDEP_H */ diff --git a/gdb/i386-cygwin-tdep.c b/gdb/i386-cygwin-tdep.c new file mode 100644 index 0000000..443f8f7 --- /dev/null +++ b/gdb/i386-cygwin-tdep.c @@ -0,0 +1,61 @@ +/* Target-dependent code for Cygwin running on i386's, for GDB. + + Copyright 2003 Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#include "defs.h" +#include "osabi.h" + +#include "gdb_string.h" + +#include "i386-tdep.h" + +static void +i386_cygwin_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) +{ + struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + + tdep->struct_return = reg_struct_return; +} + +static enum gdb_osabi +i386_cygwin_osabi_sniffer (bfd * abfd) +{ + char *target_name = bfd_get_target (abfd); + + /* Interix also uses pei-i386. + We need a way to distinguish between the two. */ + if (strcmp (target_name, "pei-i386") == 0) + return GDB_OSABI_CYGWIN; + + return GDB_OSABI_UNKNOWN; +} + +/* Provide a prototype to silence -Wmissing-prototypes. */ +void _initialize_i386_cygwin_tdep (void); + +void +_initialize_i386_cygwin_tdep (void) +{ + gdbarch_register_osabi_sniffer (bfd_arch_i386, bfd_target_coff_flavour, + i386_cygwin_osabi_sniffer); + + gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_CYGWIN, + i386_cygwin_init_abi); +} diff --git a/gdb/i386-interix-nat.c b/gdb/i386-interix-nat.c new file mode 100644 index 0000000..91b9be2 --- /dev/null +++ b/gdb/i386-interix-nat.c @@ -0,0 +1,190 @@ +/* Native-dependent code for Interix running on i386's, for GDB. + Copyright 2002 Free Software Foundation, Inc. + +This file is part of GDB. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include "defs.h" + +#include +#include +#include + +#include +#include "gdb_string.h" +#include "gdbcore.h" +#include "gregset.h" +#include "regcache.h" + +typedef unsigned long greg_t; + +/* This is a duplicate of the table in i386-linux-nat.c. */ + +static int regmap[] = { + EAX, ECX, EDX, EBX, + UESP, EBP, ESI, EDI, + EIP, EFL, CS, SS, + DS, ES, FS, GS, +}; + +/* Forward declarations. */ +extern void _initialize_core_interix (void); +extern initialize_file_ftype _initialize_core_interix; + +/* Given a pointer to a general register set in /proc format (gregset_t *), + unpack the register contents and supply them as gdb's idea of the current + register values. */ + +void +supply_gregset (gregset_t *gregsetp) +{ + int regi; + greg_t *regp = (greg_t *) & gregsetp->gregs; + + for (regi = 0; regi < I386_NUM_GREGS; regi++) + { + supply_register (regi, (char *) (regp + regmap[regi])); + } +} + +/* Store GDB's value for REGNO in *GREGSETP. If REGNO is -1, do all + of them. */ + +void +fill_gregset (gregset_t *gregsetp, int regno) +{ + int regi; + greg_t *regp = (greg_t *) gregsetp->gregs; + + for (regi = 0; regi < I386_NUM_GREGS; regi++) + if (regno == -1 || regi == regno) + regcache_collect (regi, (void *) (regp + regmap[regi])); +} + +/* Fill GDB's register file with the floating-point register values in + *FPREGSETP. */ + +void +supply_fpregset (fpregset_t *fpregsetp) +{ + i387_supply_fsave (current_regcache, -1, fpregsetp); +} + +/* Given a pointer to a floating point register set in (fpregset_t *) + format, update all of the registers from gdb's idea of the current + floating point register set. */ + +void +fill_fpregset (fpregset_t *fpregsetp, int regno) +{ + i387_fill_fsave ((char *) fpregsetp, regno); +} + +/* Read the values of either the general register set (WHICH equals 0) + or the floating point register set (WHICH equals 2) from the core + file data (pointed to by CORE_REG_SECT), and update gdb's idea of + their current values. The CORE_REG_SIZE parameter is compared to + the size of the gregset or fpgregset structures (as appropriate) to + validate the size of the structure from the core file. The + REG_ADDR parameter is ignored. */ + +static void +fetch_core_registers (char *core_reg_sect, unsigned core_reg_size, int which, + CORE_ADDR reg_addr) +{ + gdb_gregset_t gregset; + gdb_fpregset_t fpregset; + + if (which == 0) + { + if (core_reg_size != sizeof (gregset)) + { + warning ("wrong size gregset struct in core file"); + } + else + { + memcpy ((char *) &gregset, core_reg_sect, sizeof (gregset)); + supply_gregset (&gregset); + } + } + else if (which == 2) + { + if (core_reg_size != sizeof (fpregset)) + { + warning ("wrong size fpregset struct in core file"); + } + else + { + memcpy ((char *) &fpregset, core_reg_sect, sizeof (fpregset)); + supply_fpregset (&fpregset); + } + } +} + +#include + +static struct core_fns interix_core_fns = +{ + bfd_target_coff_flavour, /* core_flavour (more or less) */ + default_check_format, /* check_format */ + default_core_sniffer, /* core_sniffer */ + fetch_core_registers, /* core_read_registers */ + NULL /* next */ +}; + +void +_initialize_core_interix (void) +{ + add_core_fns (&interix_core_fns); +} + +/* We don't have a /proc/pid/file or /proc/pid/exe to read a link from, + so read it from the same place ps gets the name. */ + +char * +child_pid_to_exec_file (int pid) +{ + char *path; + char *buf; + int fd, c; + char *p; + + xasprintf (&path, "/proc/%d/stat", pid); + buf = xcalloc (MAXPATHLEN + 1, sizeof (char)); + make_cleanup (xfree, path); + make_cleanup (xfree, buf); + + fd = open (path, O_RDONLY); + + if (fd < 0) + return NULL; + + /* Skip over "Argv0\t". */ + lseek (fd, 6, SEEK_SET); + + c = read (fd, buf, MAXPATHLEN); + close (fd); + + if (c < 0) + return NULL; + + buf[c] = '\0'; /* Ensure null termination. */ + p = strchr (buf, '\n'); + if (p != NULL) + *p = '\0'; + + return buf; +} diff --git a/gdb/i386-interix-tdep.c b/gdb/i386-interix-tdep.c new file mode 100644 index 0000000..ea9f8c4 --- /dev/null +++ b/gdb/i386-interix-tdep.c @@ -0,0 +1,359 @@ +/* Target-dependent code for Interix running on i386's, for GDB. + Copyright 2002 Free Software Foundation, Inc. + +This file is part of GDB. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include "defs.h" +#include "arch-utils.h" + +#include "frame.h" +#include "gdb_string.h" +#include "gdb-stabs.h" +#include "gdbcore.h" +#include "gdbtypes.h" +#include "i386-tdep.h" +#include "inferior.h" +#include "libbfd.h" +#include "objfiles.h" +#include "osabi.h" +#include "regcache.h" + +/* offsetof (mcontext_t, gregs.gregs[EBP]) */ +static const int mcontext_EBP_greg_offset = 180; + +/* offsetof (mcontext_t, gregs.gregs[EIP]) */ +static const int mcontext_EIP_greg_offset = 184; + +/* offsetof (mcontext_t, gregs.gregs[UESP]) */ +static const int mcontext_UESP_greg_offset = 196; + +/* offsetof (mcontext_t, gregs.reserved[1]) */ +static const int mcontext_syscall_greg_offset = 4; + +/* offsetof (_JUMP_BUFFER, Eip) */ +static const int jump_buffer_Eip_offset = 20; + +/* See procfs.c and *interix*.h in config/[alpha,i386]. */ +/* ??? These should be static, but this needs a bit of work before this + can be done. */ +CORE_ADDR tramp_start; +CORE_ADDR tramp_end; +CORE_ADDR null_start; +CORE_ADDR null_end; +int winver; /* Windows NT version number */ + +/* Forward declarations. */ +extern void _initialize_i386_interix_tdep (void); +extern initialize_file_ftype _initialize_i386_interix_tdep; + +/* Adjust the section offsets in an objfile structure so that it's correct + for the type of symbols being read (or undo it with the _restore + arguments). + + If main programs ever start showing up at other than the default Image + Base, this is where that would likely be applied. */ + +void +pei_adjust_objfile_offsets (struct objfile *objfile, + enum objfile_adjusts type) +{ + int i; + CORE_ADDR symbols_offset; + + switch (type) + { + case adjust_for_symtab: + symbols_offset = NONZERO_LINK_BASE (objfile->obfd); + break; + case adjust_for_symtab_restore: + symbols_offset = -NONZERO_LINK_BASE (objfile->obfd); + break; + case adjust_for_stabs: + case adjust_for_stabs_restore: + case adjust_for_dwarf: + case adjust_for_dwarf_restore: + default: + return; + } + + for (i = 0; i < objfile->num_sections; i++) + { + (objfile->section_offsets)->offsets[i] += symbols_offset; + } +} + +static int +i386_interix_pc_in_sigtramp (CORE_ADDR pc, char *name) +{ + /* This is sufficient, where used, but is NOT a complete test; There + is more in DEPRECATED_INIT_EXTRA_FRAME_INFO + (a.k.a. interix_back_one_frame). */ + return ((pc >= tramp_start && pc < tramp_end) + || (pc >= null_start && pc < null_end)); +} + +static int +i386_interix_in_solib_call_trampoline (CORE_ADDR pc, char *name) +{ + return i386_pe_skip_trampoline_code (pc, name); +} + +static CORE_ADDR +i386_interix_skip_trampoline_code (CORE_ADDR pc) +{ + return i386_pe_skip_trampoline_code (pc, 0); +} + +static int +i386_interix_frame_chain_valid (CORE_ADDR chain, struct frame_info *thisframe) +{ + /* In the context where this is used, we get the saved PC before we've + successfully unwound far enough to be sure what we've got (it may + be a signal handler caller). If we're dealing with a signal + handler caller, this will return valid, which is fine. If not, + it'll make the correct test. */ + return ((get_frame_type (thisframe) == SIGTRAMP_FRAME) + || (chain != 0 + && !deprecated_inside_entry_file (read_memory_integer + (thisframe->frame + 4, 4)))); +} + +/* We want to find the previous frame, which on Interix is tricky when + signals are involved; set frame->frame appropriately, and also get + the pc and tweak tye frame's type; this replaces a boatload of + nested macros, as well. */ +static void +i386_interix_back_one_frame (int fromleaf, struct frame_info *frame) +{ + CORE_ADDR ra; + CORE_ADDR fm; + CORE_ADDR context; + long t; + + if (frame == NULL) + internal_error (__FILE__, __LINE__, "unexpected NULL frame"); + + if (fromleaf) + { + frame->pc = DEPRECATED_SAVED_PC_AFTER_CALL (frame->next); + return; + } + + if (!frame->next) + { + frame->pc = read_pc (); + + /* Part of the signal stuff... See below. */ + if (stopped_by_random_signal) + { + /* We know we're in a system call mini-frame; was it + NullApi or something else? */ + ra = DEPRECATED_SAVED_PC_AFTER_CALL (frame); + if (ra >= null_start && ra < null_end) + deprecated_set_frame_type (frame, SIGTRAMP_FRAME); + /* There might also be an indirect call to the mini-frame, + putting one more return address on the stack. (XP only, + I think?) This can't (reasonably) return the address of the + signal handler caller unless it's that situation, so this + is safe. */ + ra = read_memory_unsigned_integer (read_register (SP_REGNUM) + 4, 4); + if (ra >= null_start && ra < null_end) + deprecated_set_frame_type (frame, SIGTRAMP_FRAME); + } + return; + } + + if (!(get_frame_type (frame->next) == SIGTRAMP_FRAME)) + { + frame->pc = read_memory_integer (frame->next->frame + 4, 4); + return; + } + + /* This is messy (actually AWFUL)... The "trampoline" might be 2, 3 + or all 5 entities on the frame. + + Chunk 1 will be present when we're actually in a signal handler. + Chunk 2 will be present when an asynchronous signal (one that + didn't come in with a system call) is present. + We may not (yet) be in the handler, if we're just returning + from the call. + When we're actually in a handler taken from an asynchronous + signal, both will be present. + + Chunk 1: + PdxSignalDeliverer's frame + + Context struct -- not accounted for in any frame + + Chunk 2: + + PdxNullPosixApi's frame + + PdxNullApiCaller's frame + + Context struct = 0x230 not accounted for in any frame + + The symbol names come from examining objdumps of psxdll.dll; + they don't appear in the runtime image. + + For gdb's purposes, we can pile all this into one frame. */ + + ra = frame->next->pc; + /* Are we already pointing at PdxNullPosixApi? We are if + this is a signal frame, we're at next-to-top, and were stopped + by a random signal (if it wasn't the right address under + these circumstances, we wouldn't be here at all by tests above + on the prior frame). */ + if (frame->next->next == NULL && stopped_by_random_signal) + { + /* We're pointing at the frame FOR PdxNullApi. */ + fm = frame->frame; + } + else + { + /* No... We must be pointing at the frame that was called + by PdxSignalDeliverer; back up across the whole mess. */ + + /* Extract the frame for PdxSignalDeliverer. Note: + DEPRECATED_FRAME_CHAIN used the "old" frame pointer because + we were a deliverer. Get the address of the context record + that's on here frameless. */ + context = read_memory_integer (frame->frame, 4); /* an Arg */ + + /* Now extract the frame pointer contained in the context. */ + fm = read_memory_integer (context + mcontext_EBP_greg_offset, 4); + + ra = read_memory_integer (context + mcontext_EIP_greg_offset, 4); + + /* We need to know if we're in a system call because we'll be + in a syscall mini-frame, if so, and the rules are different. */ + t = (long) read_memory_integer (context + mcontext_syscall_greg_offset, + 4); + /* t contains 0 if running free, 1 if blocked on a system call, + and 2 if blocked on an exception message (e.g. a trap); + we don't expect to get here with a 2. */ + if (t != 1) + { + /* Not at a system call, therefore it can't be NullApi. */ + frame->pc = ra; + frame->frame = fm; + return; + } + + /* It's a system call... Mini frame, then look for NullApi. */ + /* Get the RA (on the stack) associated with this... It's + a system call mini-frame. */ + ra = read_memory_integer (context + mcontext_UESP_greg_offset, 4); + + if (winver >= 51) + { + /* Newer versions of Windows NT interpose another return + address (but no other "stack frame" stuff) that we need + to simply ignore here. */ + ra += 4; + } + + ra = read_memory_integer (ra, 4); + + if (!(ra >= null_start && ra < null_end)) + { + /* No Null API present; we're done. */ + frame->pc = ra; + frame->frame = fm; + return; + } + } + + /* At this point, we're looking at the frame for PdxNullPosixApi, + in either case. + + PdxNullPosixApi is called by PdxNullApiCaller (which in turn + is called by _PdxNullApiCaller (note the _).) + PdxNullPosixApiCaller (no _) is a frameless function. + + The saved frame pointer is as fm, but it's not of interest + to us because it skips us over the saved context, which is + the wrong thing to do, because it skips the interrrupted + routine! PdxNullApiCaller takes as its only argument the + address of the context of the interrupded function (which + is really in no frame, but jammed on the stack by the system) + + So: fm+0: saved bp + fm+4: return address to _PdxNullApiCaller + fm+8: arg to PdxNullApiCaller pushed by _Pdx... */ + + fm = read_memory_integer (fm + 0x8, 4); + + /* Extract the second context record. */ + + ra = read_memory_integer (fm + mcontext_EIP_greg_offset, 4); + fm = read_memory_integer (fm + mcontext_EBP_greg_offset, 4); + + frame->frame = fm; + frame->pc = ra; + + return; +} + +static CORE_ADDR +i386_interix_frame_saved_pc (struct frame_info *fi) +{ + /* Assume that we've already unwound enough to have the caller's address + if we're dealing with a signal handler caller (And if that fails, + return 0). */ + if ((get_frame_type (fi) == SIGTRAMP_FRAME)) + return fi->next ? fi->next->pc : 0; + else + return read_memory_integer (fi->frame + 4, 4); +} + +static void +i386_interix_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) +{ + struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + + tdep->struct_return = reg_struct_return; + tdep->jb_pc_offset = jump_buffer_Eip_offset; + + set_gdbarch_decr_pc_after_break (gdbarch, 0); + set_gdbarch_pc_in_sigtramp (gdbarch, i386_interix_pc_in_sigtramp); + set_gdbarch_in_solib_call_trampoline (gdbarch, + i386_interix_in_solib_call_trampoline); + set_gdbarch_skip_trampoline_code (gdbarch, + i386_interix_skip_trampoline_code); + set_gdbarch_deprecated_init_extra_frame_info (gdbarch, i386_interix_back_one_frame); + set_gdbarch_deprecated_frame_chain_valid (gdbarch, i386_interix_frame_chain_valid); + set_gdbarch_deprecated_frame_saved_pc (gdbarch, i386_interix_frame_saved_pc); + set_gdbarch_name_of_malloc (gdbarch, "_malloc"); +} + +static enum gdb_osabi +i386_interix_osabi_sniffer (bfd * abfd) +{ + char *target_name = bfd_get_target (abfd); + + if (strcmp (target_name, "pei-i386") == 0) + return GDB_OSABI_INTERIX; + + return GDB_OSABI_UNKNOWN; +} + +void +_initialize_i386_interix_tdep (void) +{ + gdbarch_register_osabi_sniffer (bfd_arch_i386, bfd_target_coff_flavour, + i386_interix_osabi_sniffer); + + gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_INTERIX, + i386_interix_init_abi); +} diff --git a/gdb/i386-nto-tdep.c b/gdb/i386-nto-tdep.c new file mode 100644 index 0000000..a80c7a4 --- /dev/null +++ b/gdb/i386-nto-tdep.c @@ -0,0 +1,305 @@ +/* i386-nto-tdep.c - i386 specific functionality for QNX Neutrino. + + Copyright 2003 Free Software Foundation, Inc. + + Contributed by QNX Software Systems Ltd. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#include "gdb_string.h" +#include "gdb_assert.h" +#include "defs.h" +#include "frame.h" +#include "target.h" +#include "regcache.h" +#include "solib-svr4.h" +#include "i386-tdep.h" +#include "nto-tdep.h" +#include "osabi.h" +#include "i387-tdep.h" + +#ifndef X86_CPU_FXSR +#define X86_CPU_FXSR (1L << 12) +#endif + +/* Why 13? Look in our /usr/include/x86/context.h header at the + x86_cpu_registers structure and you'll see an 'exx' junk register + that is just filler. Don't ask me, ask the kernel guys. */ +#define NUM_GPREGS 13 + +/* Map a GDB register number to an offset in the reg structure. */ +static int regmap[] = { + (7 * 4), /* eax */ + (6 * 4), /* ecx */ + (5 * 4), /* edx */ + (4 * 4), /* ebx */ + (11 * 4), /* esp */ + (2 * 4), /* epb */ + (1 * 4), /* esi */ + (0 * 4), /* edi */ + (8 * 4), /* eip */ + (10 * 4), /* eflags */ + (9 * 4), /* cs */ + (12 * 4), /* ss */ + (-1 * 4) /* filler */ +}; + +/* Given a gdb regno, return the offset into Neutrino's register structure + or -1 if register is unknown. */ +static int +nto_reg_offset (int regno) +{ + return (regno >= 0 && regno < NUM_GPREGS) ? regmap[regno] : -1; +} + +static void +i386nto_supply_gregset (char *gpregs) +{ + unsigned regno; + int empty = 0; + + for (regno = 0; regno < FP0_REGNUM; regno++) + { + int offset = nto_reg_offset (regno); + if (offset == -1) + supply_register (regno, (char *) &empty); + else + supply_register (regno, gpregs + offset); + } +} + +static void +i386nto_supply_fpregset (char *fpregs) +{ + if (nto_cpuinfo_valid && nto_cpuinfo_flags | X86_CPU_FXSR) + i387_supply_fxsave (current_regcache, -1, fpregs); + else + i387_supply_fsave (current_regcache, -1, fpregs); +} + +static void +i386nto_supply_regset (int regset, char *data) +{ + switch (regset) + { + case NTO_REG_GENERAL: /* QNX has different ordering of GP regs than GDB. */ + i386nto_supply_gregset (data); + break; + case NTO_REG_FLOAT: + i386nto_supply_fpregset (data); + break; + } +} + +static int +i386nto_regset_id (int regno) +{ + if (regno == -1) + return NTO_REG_END; + else if (regno < FP0_REGNUM) + return NTO_REG_GENERAL; + else if (regno < FPC_REGNUM) + return NTO_REG_FLOAT; + + return -1; /* Error. */ +} + +static int +i386nto_register_area (int regno, int regset, unsigned *off) +{ + int len; + + *off = 0; + if (regset == NTO_REG_GENERAL) + { + if (regno == -1) + return NUM_GPREGS * 4; + + *off = nto_reg_offset (regno); + if (*off == -1) + return 0; + return 4; + } + else if (regset == NTO_REG_FLOAT) + { + unsigned off_adjust, regsize, regset_size; + + if (nto_cpuinfo_valid && nto_cpuinfo_flags | X86_CPU_FXSR) + { + off_adjust = 32; + regsize = 16; + regset_size = 512; + } + else + { + off_adjust = 28; + regsize = 10; + regset_size = 128; + } + + if (regno == -1) + return regset_size; + + *off = (regno - FP0_REGNUM) * regsize + off_adjust; + return 10; + /* Why 10 instead of regsize? GDB only stores 10 bytes per FP + register so if we're sending a register back to the target, + we only want pdebug to write 10 bytes so as not to clobber + the reserved 6 bytes in the fxsave structure. */ + } + return -1; +} + +static int +i386nto_regset_fill (int regset, char *data) +{ + if (regset == NTO_REG_GENERAL) + { + int regno; + + for (regno = 0; regno < NUM_GPREGS; regno++) + { + int offset = nto_reg_offset (regno); + if (offset != -1) + regcache_collect (regno, data + offset); + } + } + else if (regset == NTO_REG_FLOAT) + { + if (nto_cpuinfo_valid && nto_cpuinfo_flags | X86_CPU_FXSR) + i387_fill_fxsave (data, -1); + else + i387_fill_fsave (data, -1); + } + else + return -1; + + return 0; +} + +static struct link_map_offsets * +i386nto_svr4_fetch_link_map_offsets (void) +{ + static struct link_map_offsets lmo; + static struct link_map_offsets *lmp = NULL; + + if (lmp == NULL) + { + lmp = &lmo; + + lmo.r_debug_size = 8; /* The actual size is 20 bytes, but + only 8 bytes are used. */ + lmo.r_map_offset = 4; + lmo.r_map_size = 4; + + lmo.link_map_size = 20; /* The actual size is 552 bytes, but + only 20 bytes are used. */ + lmo.l_addr_offset = 0; + lmo.l_addr_size = 4; + + lmo.l_name_offset = 4; + lmo.l_name_size = 4; + + lmo.l_next_offset = 12; + lmo.l_next_size = 4; + + lmo.l_prev_offset = 16; + lmo.l_prev_size = 4; + } + + return lmp; +} + +static int +i386nto_pc_in_sigtramp (CORE_ADDR pc, char *name) +{ + return name && strcmp ("__signalstub", name) == 0; +} + +#define I386_NTO_SIGCONTEXT_OFFSET 136 + +/* Assuming NEXT_FRAME is a frame following a QNX Neutrino sigtramp + routine, return the address of the associated sigcontext structure. */ + +static CORE_ADDR +i386nto_sigcontext_addr (struct frame_info *next_frame) +{ + char buf[4]; + CORE_ADDR sp; + + frame_unwind_register (next_frame, SP_REGNUM, buf); + sp = extract_unsigned_integer (buf, 4); + + return sp + I386_NTO_SIGCONTEXT_OFFSET; +} + +static void +init_i386nto_ops (void) +{ + current_nto_target.nto_regset_id = i386nto_regset_id; + current_nto_target.nto_supply_gregset = i386nto_supply_gregset; + current_nto_target.nto_supply_fpregset = i386nto_supply_fpregset; + current_nto_target.nto_supply_altregset = nto_dummy_supply_regset; + current_nto_target.nto_supply_regset = i386nto_supply_regset; + current_nto_target.nto_register_area = i386nto_register_area; + current_nto_target.nto_regset_fill = i386nto_regset_fill; + current_nto_target.nto_fetch_link_map_offsets = + i386nto_svr4_fetch_link_map_offsets; +} + +static void +i386nto_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) +{ + struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + + /* NTO uses ELF. */ + i386_elf_init_abi (info, gdbarch); + + /* Neutrino rewinds to look more normal. */ + set_gdbarch_decr_pc_after_break (gdbarch, 0); + + /* NTO has shared libraries. */ + set_gdbarch_in_solib_call_trampoline (gdbarch, in_plt_section); + set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target); + + set_gdbarch_pc_in_sigtramp (gdbarch, i386nto_pc_in_sigtramp); + tdep->sigcontext_addr = i386nto_sigcontext_addr; + tdep->sc_pc_offset = 56; + tdep->sc_sp_offset = 68; + + /* Setjmp()'s return PC saved in EDX (5). */ + tdep->jb_pc_offset = 20; /* 5x32 bit ints in. */ + + set_solib_svr4_fetch_link_map_offsets (gdbarch, + i386nto_svr4_fetch_link_map_offsets); + + /* Our loader handles solib relocations slightly differently than svr4. */ + TARGET_SO_RELOCATE_SECTION_ADDRESSES = nto_relocate_section_addresses; + + /* Supply a nice function to find our solibs. */ + TARGET_SO_FIND_AND_OPEN_SOLIB = nto_find_and_open_solib; + + init_i386nto_ops (); +} + +void +_initialize_i386nto_tdep (void) +{ + gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_QNXNTO, + i386nto_init_abi); +} diff --git a/gdb/i386fbsd-tdep.c b/gdb/i386fbsd-tdep.c new file mode 100644 index 0000000..786de7d --- /dev/null +++ b/gdb/i386fbsd-tdep.c @@ -0,0 +1,171 @@ +/* Target-dependent code for FreeBSD/i386. + + Copyright 2003 Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#include "defs.h" +#include "arch-utils.h" +#include "osabi.h" + +#include "i386-tdep.h" +#include "i387-tdep.h" + +/* FreeBSD 3.0-RELEASE or later. */ + +/* From . */ +static int i386fbsd_r_reg_offset[] = +{ + 9 * 4, 8 * 4, 7 * 4, 6 * 4, /* %eax, %ecx, %edx, %ebx */ + 15 * 4, 4 * 4, /* %esp, %ebp */ + 3 * 4, 2 * 4, /* %esi, %edi */ + 12 * 4, 14 * 4, /* %eip, %eflags */ + 13 * 4, 16 * 4, /* %cs, %ss */ + 1 * 4, 0 * 4, -1, -1 /* %ds, %es, %fs, %gs */ +}; + +CORE_ADDR i386fbsd_sigtramp_start = 0xbfbfdf20; +CORE_ADDR i386fbsd_sigtramp_end = 0xbfbfdff0; + +/* From . */ +static int i386fbsd_sc_reg_offset[] = +{ + 8 + 14 * 4, /* %eax */ + 8 + 13 * 4, /* %ecx */ + 8 + 12 * 4, /* %edx */ + 8 + 11 * 4, /* %ebx */ + 8 + 0 * 4, /* %esp */ + 8 + 1 * 4, /* %ebp */ + 8 + 10 * 4, /* %esi */ + 8 + 9 * 4, /* %edi */ + 8 + 3 * 4, /* %eip */ + 8 + 4 * 4, /* %eflags */ + 8 + 7 * 4, /* %cs */ + 8 + 8 * 4, /* %ss */ + 8 + 6 * 4, /* %ds */ + 8 + 5 * 4, /* %es */ + 8 + 15 * 4, /* %fs */ + 8 + 16 * 4 /* %gs */ +}; + +static void +i386fbsdaout_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) +{ + struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + + /* Obviously FreeBSD is BSD-based. */ + i386bsd_init_abi (info, gdbarch); + + /* FreeBSD has a different `struct reg', and reserves some space for + its FPU emulator in `struct fpreg'. */ + tdep->gregset_reg_offset = i386fbsd_r_reg_offset; + tdep->gregset_num_regs = ARRAY_SIZE (i386fbsd_r_reg_offset); + tdep->sizeof_gregset = 18 * 4; + tdep->sizeof_fpregset = 176; + + /* FreeBSD uses -freg-struct-return by default. */ + tdep->struct_return = reg_struct_return; + + /* FreeBSD uses a different memory layout. */ + tdep->sigtramp_start = i386fbsd_sigtramp_start; + tdep->sigtramp_end = i386fbsd_sigtramp_end; + + /* FreeBSD has a more complete `struct sigcontext'. */ + tdep->sc_reg_offset = i386fbsd_sc_reg_offset; + tdep->sc_num_regs = ARRAY_SIZE (i386fbsd_sc_reg_offset); +} + +static void +i386fbsd_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) +{ + /* It's almost identical to FreeBSD a.out. */ + i386fbsdaout_init_abi (info, gdbarch); + + /* Except that it uses ELF. */ + i386_elf_init_abi (info, gdbarch); + + /* FreeBSD ELF uses SVR4-style shared libraries. */ + set_gdbarch_in_solib_call_trampoline (gdbarch, + generic_in_solib_call_trampoline); +} + +/* FreeBSD 4.0-RELEASE or later. */ + +/* From . */ +static int i386fbsd4_r_reg_offset[] = +{ + 10 * 4, 9 * 4, 8 * 4, 7 * 4, /* %eax, %ecx, %edx, %ebx */ + 16 * 4, 5 * 4, /* %esp, %ebp */ + 4 * 4, 3 * 4, /* %esi, %edi */ + 13 * 4, 15 * 4, /* %eip, %eflags */ + 14 * 4, 17 * 4, /* %cs, %ss */ + 2 * 4, 1 * 4, 0 * 4, 18 * 4 /* %ds, %es, %fs, %gs */ +}; + +/* From . */ +int i386fbsd4_sc_reg_offset[] = +{ + 20 + 11 * 4, /* %eax */ + 20 + 10 * 4, /* %ecx */ + 20 + 9 * 4, /* %edx */ + 20 + 8 * 4, /* %ebx */ + 20 + 17 * 4, /* %esp */ + 20 + 6 * 4, /* %ebp */ + 20 + 5 * 4, /* %esi */ + 20 + 4 * 4, /* %edi */ + 20 + 14 * 4, /* %eip */ + 20 + 16 * 4, /* %eflags */ + 20 + 15 * 4, /* %cs */ + 20 + 18 * 4, /* %ss */ + 20 + 3 * 4, /* %ds */ + 20 + 2 * 4, /* %es */ + 20 + 1 * 4, /* %fs */ + 20 + 0 * 4 /* %gs */ +}; + +static void +i386fbsd4_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) +{ + struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + + /* Inherit stuff from older releases. We assume that FreeBSD + 4.0-RELEASE always uses ELF. */ + i386fbsd_init_abi (info, gdbarch); + + /* FreeBSD 4.0 introduced a new `struct reg'. */ + tdep->gregset_reg_offset = i386fbsd4_r_reg_offset; + tdep->gregset_num_regs = ARRAY_SIZE (i386fbsd4_r_reg_offset); + tdep->sizeof_gregset = 19 * 4; + + /* FreeBSD 4.0 introduced a new `struct sigcontext'. */ + tdep->sc_reg_offset = i386fbsd4_sc_reg_offset; + tdep->sc_num_regs = ARRAY_SIZE (i386fbsd4_sc_reg_offset); +} + + +/* Provide a prototype to silence -Wmissing-prototypes. */ +void _initialize_i386fbsd_tdep (void); + +void +_initialize_i386fbsd_tdep (void) +{ + gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_FREEBSD_AOUT, + i386fbsdaout_init_abi); + gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_FREEBSD_ELF, + i386fbsd4_init_abi); +} diff --git a/gdb/infcall.c b/gdb/infcall.c new file mode 100644 index 0000000..0956f34 --- /dev/null +++ b/gdb/infcall.c @@ -0,0 +1,1140 @@ +/* Perform an inferior function call, for GDB, the GNU debugger. + + Copyright 1986, 1987, 1988, 1989, 1990, 1991, 1992, 1993, 1994, + 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software + Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#include "defs.h" +#include "breakpoint.h" +#include "target.h" +#include "regcache.h" +#include "inferior.h" +#include "gdb_assert.h" +#include "block.h" +#include "gdbcore.h" +#include "language.h" +#include "symfile.h" +#include "gdbcmd.h" +#include "command.h" +#include "gdb_string.h" +#include "infcall.h" + +/* NOTE: cagney/2003-04-16: What's the future of this code? + + GDB needs an asynchronous expression evaluator, that means an + asynchronous inferior function call implementation, and that in + turn means restructuring the code so that it is event driven. */ + +/* How you should pass arguments to a function depends on whether it + was defined in K&R style or prototype style. If you define a + function using the K&R syntax that takes a `float' argument, then + callers must pass that argument as a `double'. If you define the + function using the prototype syntax, then you must pass the + argument as a `float', with no promotion. + + Unfortunately, on certain older platforms, the debug info doesn't + indicate reliably how each function was defined. A function type's + TYPE_FLAG_PROTOTYPED flag may be clear, even if the function was + defined in prototype style. When calling a function whose + TYPE_FLAG_PROTOTYPED flag is clear, GDB consults this flag to + decide what to do. + + For modern targets, it is proper to assume that, if the prototype + flag is clear, that can be trusted: `float' arguments should be + promoted to `double'. For some older targets, if the prototype + flag is clear, that doesn't tell us anything. The default is to + trust the debug information; the user can override this behavior + with "set coerce-float-to-double 0". */ + +static int coerce_float_to_double_p = 1; + +/* This boolean tells what gdb should do if a signal is received while + in a function called from gdb (call dummy). If set, gdb unwinds + the stack and restore the context to what as it was before the + call. + + The default is to stop in the frame where the signal was received. */ + +int unwind_on_signal_p = 0; + +/* Perform the standard coercions that are specified + for arguments to be passed to C functions. + + If PARAM_TYPE is non-NULL, it is the expected parameter type. + IS_PROTOTYPED is non-zero if the function declaration is prototyped. */ + +static struct value * +value_arg_coerce (struct value *arg, struct type *param_type, + int is_prototyped) +{ + struct type *arg_type = check_typedef (VALUE_TYPE (arg)); + struct type *type + = param_type ? check_typedef (param_type) : arg_type; + + switch (TYPE_CODE (type)) + { + case TYPE_CODE_REF: + if (TYPE_CODE (arg_type) != TYPE_CODE_REF + && TYPE_CODE (arg_type) != TYPE_CODE_PTR) + { + arg = value_addr (arg); + VALUE_TYPE (arg) = param_type; + return arg; + } + break; + case TYPE_CODE_INT: + case TYPE_CODE_CHAR: + case TYPE_CODE_BOOL: + case TYPE_CODE_ENUM: + /* If we don't have a prototype, coerce to integer type if necessary. */ + if (!is_prototyped) + { + if (TYPE_LENGTH (type) < TYPE_LENGTH (builtin_type_int)) + type = builtin_type_int; + } + /* Currently all target ABIs require at least the width of an integer + type for an argument. We may have to conditionalize the following + type coercion for future targets. */ + if (TYPE_LENGTH (type) < TYPE_LENGTH (builtin_type_int)) + type = builtin_type_int; + break; + case TYPE_CODE_FLT: + if (!is_prototyped && coerce_float_to_double_p) + { + if (TYPE_LENGTH (type) < TYPE_LENGTH (builtin_type_double)) + type = builtin_type_double; + else if (TYPE_LENGTH (type) > TYPE_LENGTH (builtin_type_double)) + type = builtin_type_long_double; + } + break; + case TYPE_CODE_FUNC: + type = lookup_pointer_type (type); + break; + case TYPE_CODE_ARRAY: + /* Arrays are coerced to pointers to their first element, unless + they are vectors, in which case we want to leave them alone, + because they are passed by value. */ + if (current_language->c_style_arrays) + if (!TYPE_VECTOR (type)) + type = lookup_pointer_type (TYPE_TARGET_TYPE (type)); + break; + case TYPE_CODE_UNDEF: + case TYPE_CODE_PTR: + case TYPE_CODE_STRUCT: + case TYPE_CODE_UNION: + case TYPE_CODE_VOID: + case TYPE_CODE_SET: + case TYPE_CODE_RANGE: + case TYPE_CODE_STRING: + case TYPE_CODE_BITSTRING: + case TYPE_CODE_ERROR: + case TYPE_CODE_MEMBER: + case TYPE_CODE_METHOD: + case TYPE_CODE_COMPLEX: + default: + break; + } + + return value_cast (type, arg); +} + +/* Determine a function's address and its return type from its value. + Calls error() if the function is not valid for calling. */ + +CORE_ADDR +find_function_addr (struct value *function, struct type **retval_type) +{ + struct type *ftype = check_typedef (VALUE_TYPE (function)); + enum type_code code = TYPE_CODE (ftype); + struct type *value_type; + CORE_ADDR funaddr; + + /* If it's a member function, just look at the function + part of it. */ + + /* Determine address to call. */ + if (code == TYPE_CODE_FUNC || code == TYPE_CODE_METHOD) + { + funaddr = VALUE_ADDRESS (function); + value_type = TYPE_TARGET_TYPE (ftype); + } + else if (code == TYPE_CODE_PTR) + { + funaddr = value_as_address (function); + ftype = check_typedef (TYPE_TARGET_TYPE (ftype)); + if (TYPE_CODE (ftype) == TYPE_CODE_FUNC + || TYPE_CODE (ftype) == TYPE_CODE_METHOD) + { + funaddr = gdbarch_convert_from_func_ptr_addr (current_gdbarch, + funaddr, + ¤t_target); + value_type = TYPE_TARGET_TYPE (ftype); + } + else + value_type = builtin_type_int; + } + else if (code == TYPE_CODE_INT) + { + /* Handle the case of functions lacking debugging info. + Their values are characters since their addresses are char */ + if (TYPE_LENGTH (ftype) == 1) + funaddr = value_as_address (value_addr (function)); + else + /* Handle integer used as address of a function. */ + funaddr = (CORE_ADDR) value_as_long (function); + + value_type = builtin_type_int; + } + else + error ("Invalid data type for function to be called."); + + *retval_type = value_type; + return funaddr; +} + +/* Call breakpoint_auto_delete on the current contents of the bpstat + pointed to by arg (which is really a bpstat *). */ + +static void +breakpoint_auto_delete_contents (void *arg) +{ + breakpoint_auto_delete (*(bpstat *) arg); +} + +static CORE_ADDR +legacy_push_dummy_code (struct gdbarch *gdbarch, + CORE_ADDR sp, CORE_ADDR funaddr, int using_gcc, + struct value **args, int nargs, + struct type *value_type, + CORE_ADDR *real_pc, CORE_ADDR *bp_addr) +{ + /* CALL_DUMMY is an array of words (DEPRECATED_REGISTER_SIZE), but + each word is in host byte order. Before calling + DEPRECATED_FIX_CALL_DUMMY, we byteswap it and remove any extra + bytes which might exist because ULONGEST is bigger than + DEPRECATED_REGISTER_SIZE. */ + /* NOTE: This is pretty wierd, as the call dummy is actually a + sequence of instructions. But CISC machines will have to pack + the instructions into DEPRECATED_REGISTER_SIZE units (and so will + RISC machines for which INSTRUCTION_SIZE is not + DEPRECATED_REGISTER_SIZE). */ + /* NOTE: This is pretty stupid. CALL_DUMMY should be in strict + target byte order. */ + CORE_ADDR start_sp; + ULONGEST *dummy = alloca (DEPRECATED_SIZEOF_CALL_DUMMY_WORDS); + int sizeof_dummy1 = (DEPRECATED_REGISTER_SIZE + * DEPRECATED_SIZEOF_CALL_DUMMY_WORDS + / sizeof (ULONGEST)); + char *dummy1 = alloca (sizeof_dummy1); + memcpy (dummy, DEPRECATED_CALL_DUMMY_WORDS, + DEPRECATED_SIZEOF_CALL_DUMMY_WORDS); + if (INNER_THAN (1, 2)) + { + /* Stack grows down */ + sp -= sizeof_dummy1; + start_sp = sp; + } + else + { + /* Stack grows up */ + start_sp = sp; + sp += sizeof_dummy1; + } + /* NOTE: cagney/2002-09-10: Don't bother re-adjusting the stack + after allocating space for the call dummy. A target can specify + a SIZEOF_DUMMY1 (via DEPRECATED_SIZEOF_CALL_DUMMY_WORDS) such + that all local alignment requirements are met. */ + /* Create a call sequence customized for this function and the + number of arguments for it. */ + { + int i; + for (i = 0; i < (int) (DEPRECATED_SIZEOF_CALL_DUMMY_WORDS / sizeof (dummy[0])); + i++) + store_unsigned_integer (&dummy1[i * DEPRECATED_REGISTER_SIZE], + DEPRECATED_REGISTER_SIZE, + (ULONGEST) dummy[i]); + } + /* NOTE: cagney/2003-04-22: This computation of REAL_PC, BP_ADDR and + DUMMY_ADDR is pretty messed up. It comes from constant tinkering + with the values. Instead a DEPRECATED_FIX_CALL_DUMMY replacement + (PUSH_DUMMY_BREAKPOINT?) should just do everything. */ +#ifdef GDB_TARGET_IS_HPPA + (*real_pc) = DEPRECATED_FIX_CALL_DUMMY (dummy1, start_sp, funaddr, nargs, + args, value_type, using_gcc); +#else + if (DEPRECATED_FIX_CALL_DUMMY_P ()) + { + /* gdb_assert (CALL_DUMMY_LOCATION == ON_STACK) true? */ + DEPRECATED_FIX_CALL_DUMMY (dummy1, start_sp, funaddr, nargs, args, + value_type, using_gcc); + } + (*real_pc) = start_sp; +#endif + /* Yes, the offset is applied to the real_pc and not the dummy addr. + Ulgh! Blame the HP/UX target. */ + (*bp_addr) = (*real_pc) + DEPRECATED_CALL_DUMMY_BREAKPOINT_OFFSET; + /* Yes, the offset is applied to the real_pc and not the + dummy_addr. Ulgh! Blame the HP/UX target. */ + (*real_pc) += DEPRECATED_CALL_DUMMY_START_OFFSET; + write_memory (start_sp, (char *) dummy1, sizeof_dummy1); + if (DEPRECATED_USE_GENERIC_DUMMY_FRAMES) + generic_save_call_dummy_addr (start_sp, start_sp + sizeof_dummy1); + return sp; +} + +static CORE_ADDR +generic_push_dummy_code (struct gdbarch *gdbarch, + CORE_ADDR sp, CORE_ADDR funaddr, int using_gcc, + struct value **args, int nargs, + struct type *value_type, + CORE_ADDR *real_pc, CORE_ADDR *bp_addr) +{ + /* Something here to findout the size of a breakpoint and then + allocate space for it on the stack. */ + int bplen; + /* This code assumes frame align. */ + gdb_assert (gdbarch_frame_align_p (gdbarch)); + /* Force the stack's alignment. The intent is to ensure that the SP + is aligned to at least a breakpoint instruction's boundary. */ + sp = gdbarch_frame_align (gdbarch, sp); + /* Allocate space for, and then position the breakpoint on the + stack. */ + if (gdbarch_inner_than (gdbarch, 1, 2)) + { + CORE_ADDR bppc = sp; + gdbarch_breakpoint_from_pc (gdbarch, &bppc, &bplen); + sp = gdbarch_frame_align (gdbarch, sp - bplen); + (*bp_addr) = sp; + /* Should the breakpoint size/location be re-computed here? */ + } + else + { + (*bp_addr) = sp; + gdbarch_breakpoint_from_pc (gdbarch, bp_addr, &bplen); + sp = gdbarch_frame_align (gdbarch, sp + bplen); + } + /* Inferior resumes at the function entry point. */ + (*real_pc) = funaddr; + return sp; +} + +/* Provide backward compatibility. Once DEPRECATED_FIX_CALL_DUMMY is + eliminated, this can be simplified. */ + +static CORE_ADDR +push_dummy_code (struct gdbarch *gdbarch, + CORE_ADDR sp, CORE_ADDR funaddr, int using_gcc, + struct value **args, int nargs, + struct type *value_type, + CORE_ADDR *real_pc, CORE_ADDR *bp_addr) +{ + if (gdbarch_push_dummy_code_p (gdbarch)) + return gdbarch_push_dummy_code (gdbarch, sp, funaddr, using_gcc, + args, nargs, value_type, real_pc, bp_addr); + else if (DEPRECATED_FIX_CALL_DUMMY_P ()) + return legacy_push_dummy_code (gdbarch, sp, funaddr, using_gcc, + args, nargs, value_type, real_pc, bp_addr); + else + return generic_push_dummy_code (gdbarch, sp, funaddr, using_gcc, + args, nargs, value_type, real_pc, bp_addr); +} + +/* All this stuff with a dummy frame may seem unnecessarily complicated + (why not just save registers in GDB?). The purpose of pushing a dummy + frame which looks just like a real frame is so that if you call a + function and then hit a breakpoint (get a signal, etc), "backtrace" + will look right. Whether the backtrace needs to actually show the + stack at the time the inferior function was called is debatable, but + it certainly needs to not display garbage. So if you are contemplating + making dummy frames be different from normal frames, consider that. */ + +/* Perform a function call in the inferior. + ARGS is a vector of values of arguments (NARGS of them). + FUNCTION is a value, the function to be called. + Returns a value representing what the function returned. + May fail to return, if a breakpoint or signal is hit + during the execution of the function. + + ARGS is modified to contain coerced values. */ + +struct value * +call_function_by_hand (struct value *function, int nargs, struct value **args) +{ + CORE_ADDR sp; + CORE_ADDR dummy_addr; + struct type *value_type; + unsigned char struct_return; + CORE_ADDR struct_addr = 0; + struct regcache *retbuf; + struct cleanup *retbuf_cleanup; + struct inferior_status *inf_status; + struct cleanup *inf_status_cleanup; + CORE_ADDR funaddr; + int using_gcc; /* Set to version of gcc in use, or zero if not gcc */ + CORE_ADDR real_pc; + struct type *ftype = check_typedef (SYMBOL_TYPE (function)); + CORE_ADDR bp_addr; + + if (!target_has_execution) + noprocess (); + + /* Create a cleanup chain that contains the retbuf (buffer + containing the register values). This chain is create BEFORE the + inf_status chain so that the inferior status can cleaned up + (restored or discarded) without having the retbuf freed. */ + retbuf = regcache_xmalloc (current_gdbarch); + retbuf_cleanup = make_cleanup_regcache_xfree (retbuf); + + /* A cleanup for the inferior status. Create this AFTER the retbuf + so that this can be discarded or applied without interfering with + the regbuf. */ + inf_status = save_inferior_status (1); + inf_status_cleanup = make_cleanup_restore_inferior_status (inf_status); + + if (DEPRECATED_PUSH_DUMMY_FRAME_P ()) + { + /* DEPRECATED_PUSH_DUMMY_FRAME is responsible for saving the + inferior registers (and frame_pop() for restoring them). (At + least on most machines) they are saved on the stack in the + inferior. */ + DEPRECATED_PUSH_DUMMY_FRAME; + } + else + { + /* FIXME: cagney/2003-02-26: Step zero of this little tinker is + to extract the generic dummy frame code from the architecture + vector. Hence this direct call. + + A follow-on change is to modify this interface so that it takes + thread OR frame OR ptid as a parameter, and returns a dummy + frame handle. The handle can then be used further down as a + parameter to generic_save_dummy_frame_tos(). Hmm, thinking + about it, since everything is ment to be using generic dummy + frames, why not even use some of the dummy frame code to here - + do a regcache dup and then pass the duped regcache, along with + all the other stuff, at one single point. + + In fact, you can even save the structure's return address in the + dummy frame and fix one of those nasty lost struct return edge + conditions. */ + generic_push_dummy_frame (); + } + + /* Ensure that the initial SP is correctly aligned. */ + { + CORE_ADDR old_sp = read_sp (); + if (gdbarch_frame_align_p (current_gdbarch)) + { + sp = gdbarch_frame_align (current_gdbarch, old_sp); + /* NOTE: cagney/2003-08-13: Skip the "red zone". For some + ABIs, a function can use memory beyond the inner most stack + address. AMD64 called that region the "red zone". Skip at + least the "red zone" size before allocating any space on + the stack. */ + if (INNER_THAN (1, 2)) + sp -= gdbarch_frame_red_zone_size (current_gdbarch); + else + sp += gdbarch_frame_red_zone_size (current_gdbarch); + /* Still aligned? */ + gdb_assert (sp == gdbarch_frame_align (current_gdbarch, sp)); + /* NOTE: cagney/2002-09-18: + + On a RISC architecture, a void parameterless generic dummy + frame (i.e., no parameters, no result) typically does not + need to push anything the stack and hence can leave SP and + FP. Similarly, a frameless (possibly leaf) function does + not push anything on the stack and, hence, that too can + leave FP and SP unchanged. As a consequence, a sequence of + void parameterless generic dummy frame calls to frameless + functions will create a sequence of effectively identical + frames (SP, FP and TOS and PC the same). This, not + suprisingly, results in what appears to be a stack in an + infinite loop --- when GDB tries to find a generic dummy + frame on the internal dummy frame stack, it will always + find the first one. + + To avoid this problem, the code below always grows the + stack. That way, two dummy frames can never be identical. + It does burn a few bytes of stack but that is a small price + to pay :-). */ + if (sp == old_sp) + { + if (INNER_THAN (1, 2)) + /* Stack grows down. */ + sp = gdbarch_frame_align (current_gdbarch, old_sp - 1); + else + /* Stack grows up. */ + sp = gdbarch_frame_align (current_gdbarch, old_sp + 1); + } + gdb_assert ((INNER_THAN (1, 2) && sp <= old_sp) + || (INNER_THAN (2, 1) && sp >= old_sp)); + } + else + /* FIXME: cagney/2002-09-18: Hey, you loose! + + Who knows how badly aligned the SP is! + + If the generic dummy frame ends up empty (because nothing is + pushed) GDB won't be able to correctly perform back traces. + If a target is having trouble with backtraces, first thing to + do is add FRAME_ALIGN() to the architecture vector. If that + fails, try unwind_dummy_id(). + + If the ABI specifies a "Red Zone" (see the doco) the code + below will quietly trash it. */ + sp = old_sp; + } + + funaddr = find_function_addr (function, &value_type); + CHECK_TYPEDEF (value_type); + + { + struct block *b = block_for_pc (funaddr); + /* If compiled without -g, assume GCC 2. */ + using_gcc = (b == NULL ? 2 : BLOCK_GCC_COMPILED (b)); + } + + /* Are we returning a value using a structure return or a normal + value return? */ + + struct_return = using_struct_return (value_type, using_gcc); + + /* Determine the location of the breakpoint (and possibly other + stuff) that the called function will return to. The SPARC, for a + function returning a structure or union, needs to make space for + not just the breakpoint but also an extra word containing the + size (?) of the structure being passed. */ + + /* The actual breakpoint (at BP_ADDR) is inserted separatly so there + is no need to write that out. */ + + switch (CALL_DUMMY_LOCATION) + { + case ON_STACK: + /* "dummy_addr" is here just to keep old targets happy. New + targets return that same information via "sp" and "bp_addr". */ + if (INNER_THAN (1, 2)) + { + sp = push_dummy_code (current_gdbarch, sp, funaddr, + using_gcc, args, nargs, value_type, + &real_pc, &bp_addr); + dummy_addr = sp; + } + else + { + dummy_addr = sp; + sp = push_dummy_code (current_gdbarch, sp, funaddr, + using_gcc, args, nargs, value_type, + &real_pc, &bp_addr); + } + break; + case AT_ENTRY_POINT: + if (DEPRECATED_FIX_CALL_DUMMY_P ()) + { + /* Sigh. Some targets use DEPRECATED_FIX_CALL_DUMMY to + shove extra stuff onto the stack or into registers. That + code should be in PUSH_DUMMY_CALL, however, in the mean + time ... */ + /* If the target is manipulating DUMMY1, it looses big time. */ + void *dummy1 = NULL; + DEPRECATED_FIX_CALL_DUMMY (dummy1, sp, funaddr, nargs, args, + value_type, using_gcc); + } + real_pc = funaddr; + dummy_addr = entry_point_address (); + if (DEPRECATED_CALL_DUMMY_ADDRESS_P ()) + /* Override it. */ + dummy_addr = DEPRECATED_CALL_DUMMY_ADDRESS (); + /* Make certain that the address points at real code, and not a + function descriptor. */ + dummy_addr = gdbarch_convert_from_func_ptr_addr (current_gdbarch, + dummy_addr, + ¤t_target); + /* A call dummy always consists of just a single breakpoint, so + it's address is the same as the address of the dummy. */ + bp_addr = dummy_addr; + break; + case AT_SYMBOL: + /* Some executables define a symbol __CALL_DUMMY_ADDRESS whose + address is the location where the breakpoint should be + placed. Once all targets are using the overhauled frame code + this can be deleted - ON_STACK is a better option. */ + { + struct minimal_symbol *sym; + + sym = lookup_minimal_symbol ("__CALL_DUMMY_ADDRESS", NULL, NULL); + real_pc = funaddr; + if (sym) + dummy_addr = SYMBOL_VALUE_ADDRESS (sym); + else + dummy_addr = entry_point_address (); + /* Make certain that the address points at real code, and not + a function descriptor. */ + dummy_addr = gdbarch_convert_from_func_ptr_addr (current_gdbarch, + dummy_addr, + ¤t_target); + /* A call dummy always consists of just a single breakpoint, + so it's address is the same as the address of the dummy. */ + bp_addr = dummy_addr; + break; + } + default: + internal_error (__FILE__, __LINE__, "bad switch"); + } + + if (DEPRECATED_USE_GENERIC_DUMMY_FRAMES) + /* Save where the breakpoint is going to be inserted so that the + dummy-frame code is later able to re-identify it. */ + generic_save_call_dummy_addr (bp_addr, bp_addr + 1); + + if (nargs < TYPE_NFIELDS (ftype)) + error ("too few arguments in function call"); + + { + int i; + for (i = nargs - 1; i >= 0; i--) + { + int prototyped; + struct type *param_type; + + /* FIXME drow/2002-05-31: Should just always mark methods as + prototyped. Can we respect TYPE_VARARGS? Probably not. */ + if (TYPE_CODE (ftype) == TYPE_CODE_METHOD) + prototyped = 1; + else if (i < TYPE_NFIELDS (ftype)) + prototyped = TYPE_PROTOTYPED (ftype); + else + prototyped = 0; + + if (i < TYPE_NFIELDS (ftype)) + param_type = TYPE_FIELD_TYPE (ftype, i); + else + param_type = NULL; + + args[i] = value_arg_coerce (args[i], param_type, prototyped); + + /* elz: this code is to handle the case in which the function + to be called has a pointer to function as parameter and the + corresponding actual argument is the address of a function + and not a pointer to function variable. In aCC compiled + code, the calls through pointers to functions (in the body + of the function called by hand) are made via + $$dyncall_external which requires some registers setting, + this is taken care of if we call via a function pointer + variable, but not via a function address. In cc this is + not a problem. */ + + if (using_gcc == 0) + { + if (param_type != NULL && TYPE_CODE (ftype) != TYPE_CODE_METHOD) + { + /* if this parameter is a pointer to function. */ + if (TYPE_CODE (param_type) == TYPE_CODE_PTR) + if (TYPE_CODE (TYPE_TARGET_TYPE (param_type)) == TYPE_CODE_FUNC) + /* elz: FIXME here should go the test about the + compiler used to compile the target. We want to + issue the error message only if the compiler + used was HP's aCC. If we used HP's cc, then + there is no problem and no need to return at + this point. */ + /* Go see if the actual parameter is a variable of + type pointer to function or just a function. */ + if (args[i]->lval == not_lval) + { + char *arg_name; + if (find_pc_partial_function ((CORE_ADDR) args[i]->aligner.contents[0], &arg_name, NULL, NULL)) + error ("\ +You cannot use function <%s> as argument. \n\ +You must use a pointer to function type variable. Command ignored.", arg_name); + } + } + } + } + } + + if (DEPRECATED_REG_STRUCT_HAS_ADDR_P ()) + { + int i; + /* This is a machine like the sparc, where we may need to pass a + pointer to the structure, not the structure itself. */ + for (i = nargs - 1; i >= 0; i--) + { + struct type *arg_type = check_typedef (VALUE_TYPE (args[i])); + if ((TYPE_CODE (arg_type) == TYPE_CODE_STRUCT + || TYPE_CODE (arg_type) == TYPE_CODE_UNION + || TYPE_CODE (arg_type) == TYPE_CODE_ARRAY + || TYPE_CODE (arg_type) == TYPE_CODE_STRING + || TYPE_CODE (arg_type) == TYPE_CODE_BITSTRING + || TYPE_CODE (arg_type) == TYPE_CODE_SET + || (TYPE_CODE (arg_type) == TYPE_CODE_FLT + && TYPE_LENGTH (arg_type) > 8) + ) + && DEPRECATED_REG_STRUCT_HAS_ADDR (using_gcc, arg_type)) + { + CORE_ADDR addr; + int len; /* = TYPE_LENGTH (arg_type); */ + int aligned_len; + arg_type = check_typedef (VALUE_ENCLOSING_TYPE (args[i])); + len = TYPE_LENGTH (arg_type); + + if (DEPRECATED_STACK_ALIGN_P ()) + /* MVS 11/22/96: I think at least some of this + stack_align code is really broken. Better to let + PUSH_ARGUMENTS adjust the stack in a target-defined + manner. */ + aligned_len = DEPRECATED_STACK_ALIGN (len); + else + aligned_len = len; + if (INNER_THAN (1, 2)) + { + /* stack grows downward */ + sp -= aligned_len; + /* ... so the address of the thing we push is the + stack pointer after we push it. */ + addr = sp; + } + else + { + /* The stack grows up, so the address of the thing + we push is the stack pointer before we push it. */ + addr = sp; + sp += aligned_len; + } + /* Push the structure. */ + write_memory (addr, VALUE_CONTENTS_ALL (args[i]), len); + /* The value we're going to pass is the address of the + thing we just pushed. */ + /*args[i] = value_from_longest (lookup_pointer_type (value_type), + (LONGEST) addr); */ + args[i] = value_from_pointer (lookup_pointer_type (arg_type), + addr); + } + } + } + + + /* Reserve space for the return structure to be written on the + stack, if necessary. Make certain that the value is correctly + aligned. */ + + if (struct_return) + { + int len = TYPE_LENGTH (value_type); + if (DEPRECATED_STACK_ALIGN_P ()) + /* NOTE: cagney/2003-03-22: Should rely on frame align, rather + than stack align to force the alignment of the stack. */ + len = DEPRECATED_STACK_ALIGN (len); + if (INNER_THAN (1, 2)) + { + /* Stack grows downward. Align STRUCT_ADDR and SP after + making space for the return value. */ + sp -= len; + if (gdbarch_frame_align_p (current_gdbarch)) + sp = gdbarch_frame_align (current_gdbarch, sp); + struct_addr = sp; + } + else + { + /* Stack grows upward. Align the frame, allocate space, and + then again, re-align the frame??? */ + if (gdbarch_frame_align_p (current_gdbarch)) + sp = gdbarch_frame_align (current_gdbarch, sp); + struct_addr = sp; + sp += len; + if (gdbarch_frame_align_p (current_gdbarch)) + sp = gdbarch_frame_align (current_gdbarch, sp); + } + } + + /* elz: on HPPA no need for this extra alignment, maybe it is needed + on other architectures. This is because all the alignment is + taken care of in the above code (ifdef DEPRECATED_REG_STRUCT_HAS_ADDR) + and in hppa_push_arguments */ + /* NOTE: cagney/2003-03-24: The below code is very broken. Given an + odd sized parameter the below will mis-align the stack. As was + suggested back in '96, better to let PUSH_ARGUMENTS handle it. */ + if (DEPRECATED_EXTRA_STACK_ALIGNMENT_NEEDED) + { + /* MVS 11/22/96: I think at least some of this stack_align code + is really broken. Better to let push_dummy_call() adjust the + stack in a target-defined manner. */ + if (DEPRECATED_STACK_ALIGN_P () && INNER_THAN (1, 2)) + { + /* If stack grows down, we must leave a hole at the top. */ + int len = 0; + int i; + for (i = nargs - 1; i >= 0; i--) + len += TYPE_LENGTH (VALUE_ENCLOSING_TYPE (args[i])); + if (DEPRECATED_CALL_DUMMY_STACK_ADJUST_P ()) + len += DEPRECATED_CALL_DUMMY_STACK_ADJUST; + sp -= DEPRECATED_STACK_ALIGN (len) - len; + } + } + + /* Create the dummy stack frame. Pass in the call dummy address as, + presumably, the ABI code knows where, in the call dummy, the + return address should be pointed. */ + if (gdbarch_push_dummy_call_p (current_gdbarch)) + /* When there is no push_dummy_call method, should this code + simply error out. That would the implementation of this method + for all ABIs (which is probably a good thing). */ + sp = gdbarch_push_dummy_call (current_gdbarch, funaddr, current_regcache, + bp_addr, nargs, args, sp, struct_return, + struct_addr); + else if (DEPRECATED_PUSH_ARGUMENTS_P ()) + /* Keep old targets working. */ + sp = DEPRECATED_PUSH_ARGUMENTS (nargs, args, sp, struct_return, + struct_addr); + else + sp = legacy_push_arguments (nargs, args, sp, struct_return, struct_addr); + + if (DEPRECATED_PUSH_RETURN_ADDRESS_P ()) + /* for targets that use no CALL_DUMMY */ + /* There are a number of targets now which actually don't write + any CALL_DUMMY instructions into the target, but instead just + save the machine state, push the arguments, and jump directly + to the callee function. Since this doesn't actually involve + executing a JSR/BSR instruction, the return address must be set + up by hand, either by pushing onto the stack or copying into a + return-address register as appropriate. Formerly this has been + done in PUSH_ARGUMENTS, but that's overloading its + functionality a bit, so I'm making it explicit to do it here. */ + /* NOTE: cagney/2003-04-22: The first parameter ("real_pc") has + been replaced with zero, it turns out that no implementation + used that parameter. This occured because the value being + supplied - the address of the called function's entry point + instead of the address of the breakpoint that the called + function should return to - wasn't useful. */ + sp = DEPRECATED_PUSH_RETURN_ADDRESS (0, sp); + + /* NOTE: cagney/2003-03-23: Diable this code when there is a + push_dummy_call() method. Since that method will have already + handled any alignment issues, the code below is entirely + redundant. */ + if (!gdbarch_push_dummy_call_p (current_gdbarch) + && DEPRECATED_STACK_ALIGN_P () && !INNER_THAN (1, 2)) + { + /* If stack grows up, we must leave a hole at the bottom, note + that sp already has been advanced for the arguments! */ + if (DEPRECATED_CALL_DUMMY_STACK_ADJUST_P ()) + sp += DEPRECATED_CALL_DUMMY_STACK_ADJUST; + sp = DEPRECATED_STACK_ALIGN (sp); + } + +/* XXX This seems wrong. For stacks that grow down we shouldn't do + anything here! */ + /* MVS 11/22/96: I think at least some of this stack_align code is + really broken. Better to let PUSH_ARGUMENTS adjust the stack in + a target-defined manner. */ + if (DEPRECATED_CALL_DUMMY_STACK_ADJUST_P ()) + if (INNER_THAN (1, 2)) + { + /* stack grows downward */ + sp -= DEPRECATED_CALL_DUMMY_STACK_ADJUST; + } + + /* Store the address at which the structure is supposed to be + written. */ + /* NOTE: 2003-03-24: Since PUSH_ARGUMENTS can (and typically does) + store the struct return address, this call is entirely redundant. */ + if (struct_return && DEPRECATED_STORE_STRUCT_RETURN_P ()) + DEPRECATED_STORE_STRUCT_RETURN (struct_addr, sp); + + /* Write the stack pointer. This is here because the statements + above might fool with it. On SPARC, this write also stores the + register window into the right place in the new stack frame, + which otherwise wouldn't happen (see store_inferior_registers in + sparc-nat.c). */ + /* NOTE: cagney/2003-03-23: Since the architecture method + push_dummy_call() should have already stored the stack pointer + (as part of creating the fake call frame), and none of the code + following that call adjusts the stack-pointer value, the below + call is entirely redundant. */ + if (DEPRECATED_DUMMY_WRITE_SP_P ()) + DEPRECATED_DUMMY_WRITE_SP (sp); + + if (gdbarch_unwind_dummy_id_p (current_gdbarch)) + { + /* Sanity. The exact same SP value is returned by + PUSH_DUMMY_CALL, saved as the dummy-frame TOS, and used by + unwind_dummy_id to form the frame ID's stack address. */ + gdb_assert (DEPRECATED_USE_GENERIC_DUMMY_FRAMES); + generic_save_dummy_frame_tos (sp); + } + else if (DEPRECATED_SAVE_DUMMY_FRAME_TOS_P ()) + DEPRECATED_SAVE_DUMMY_FRAME_TOS (sp); + + /* Now proceed, having reached the desired place. */ + clear_proceed_status (); + + /* Create a momentary breakpoint at the return address of the + inferior. That way it breaks when it returns. */ + + { + struct breakpoint *bpt; + struct symtab_and_line sal; + struct frame_id frame; + init_sal (&sal); /* initialize to zeroes */ + sal.pc = bp_addr; + sal.section = find_pc_overlay (sal.pc); + /* Set up a frame ID for the dummy frame so we can pass it to + set_momentary_breakpoint. We need to give the breakpoint a + frame ID so that the breakpoint code can correctly re-identify + the dummy breakpoint. */ + if (gdbarch_unwind_dummy_id_p (current_gdbarch)) + { + /* Sanity. The exact same SP value is returned by + PUSH_DUMMY_CALL, saved as the dummy-frame TOS, and used by + unwind_dummy_id to form the frame ID's stack address. */ + gdb_assert (DEPRECATED_USE_GENERIC_DUMMY_FRAMES); + frame = frame_id_build (sp, sal.pc); + } + else + { + /* The assumption here is that push_dummy_call() returned the + stack part of the frame ID. Unfortunately, many older + architectures were, via a convoluted mess, relying on the + poorly defined and greatly overloaded + DEPRECATED_TARGET_READ_FP or DEPRECATED_FP_REGNUM to supply + the value. */ + if (DEPRECATED_TARGET_READ_FP_P ()) + frame = frame_id_build (DEPRECATED_TARGET_READ_FP (), sal.pc); + else if (DEPRECATED_FP_REGNUM >= 0) + frame = frame_id_build (read_register (DEPRECATED_FP_REGNUM), sal.pc); + else + frame = frame_id_build (sp, sal.pc); + } + bpt = set_momentary_breakpoint (sal, frame, bp_call_dummy); + bpt->disposition = disp_del; + } + + /* Execute a "stack dummy", a piece of code stored in the stack by + the debugger to be executed in the inferior. + + The dummy's frame is automatically popped whenever that break is + hit. If that is the first time the program stops, + call_function_by_hand returns to its caller with that frame + already gone and sets RC to 0. + + Otherwise, set RC to a non-zero value. If the called function + receives a random signal, we do not allow the user to continue + executing it as this may not work. The dummy frame is poped and + we return 1. If we hit a breakpoint, we leave the frame in place + and return 2 (the frame will eventually be popped when we do hit + the dummy end breakpoint). */ + + { + struct cleanup *old_cleanups = make_cleanup (null_cleanup, 0); + int saved_async = 0; + + /* If all error()s out of proceed ended up calling normal_stop + (and perhaps they should; it already does in the special case + of error out of resume()), then we wouldn't need this. */ + make_cleanup (breakpoint_auto_delete_contents, &stop_bpstat); + + disable_watchpoints_before_interactive_call_start (); + proceed_to_finish = 1; /* We want stop_registers, please... */ + + if (target_can_async_p ()) + saved_async = target_async_mask (0); + + proceed (real_pc, TARGET_SIGNAL_0, 0); + + if (saved_async) + target_async_mask (saved_async); + + enable_watchpoints_after_interactive_call_stop (); + + discard_cleanups (old_cleanups); + } + + if (stopped_by_random_signal || !stop_stack_dummy) + { + /* Find the name of the function we're about to complain about. */ + const char *name = NULL; + { + struct symbol *symbol = find_pc_function (funaddr); + if (symbol) + name = SYMBOL_PRINT_NAME (symbol); + else + { + /* Try the minimal symbols. */ + struct minimal_symbol *msymbol = lookup_minimal_symbol_by_pc (funaddr); + if (msymbol) + name = SYMBOL_PRINT_NAME (msymbol); + } + if (name == NULL) + { + /* Can't use a cleanup here. It is discarded, instead use + an alloca. */ + char *tmp = xstrprintf ("at %s", local_hex_string (funaddr)); + char *a = alloca (strlen (tmp) + 1); + strcpy (a, tmp); + xfree (tmp); + name = a; + } + } + if (stopped_by_random_signal) + { + /* We stopped inside the FUNCTION because of a random + signal. Further execution of the FUNCTION is not + allowed. */ + + if (unwind_on_signal_p) + { + /* The user wants the context restored. */ + + /* We must get back to the frame we were before the + dummy call. */ + frame_pop (get_current_frame ()); + + /* FIXME: Insert a bunch of wrap_here; name can be very + long if it's a C++ name with arguments and stuff. */ + error ("\ +The program being debugged was signaled while in a function called from GDB.\n\ +GDB has restored the context to what it was before the call.\n\ +To change this behavior use \"set unwindonsignal off\"\n\ +Evaluation of the expression containing the function (%s) will be abandoned.", + name); + } + else + { + /* The user wants to stay in the frame where we stopped + (default).*/ + /* If we restored the inferior status (via the cleanup), + we would print a spurious error message (Unable to + restore previously selected frame), would write the + registers from the inf_status (which is wrong), and + would do other wrong things. */ + discard_cleanups (inf_status_cleanup); + discard_inferior_status (inf_status); + /* FIXME: Insert a bunch of wrap_here; name can be very + long if it's a C++ name with arguments and stuff. */ + error ("\ +The program being debugged was signaled while in a function called from GDB.\n\ +GDB remains in the frame where the signal was received.\n\ +To change this behavior use \"set unwindonsignal on\"\n\ +Evaluation of the expression containing the function (%s) will be abandoned.", + name); + } + } + + if (!stop_stack_dummy) + { + /* We hit a breakpoint inside the FUNCTION. */ + /* If we restored the inferior status (via the cleanup), we + would print a spurious error message (Unable to restore + previously selected frame), would write the registers + from the inf_status (which is wrong), and would do other + wrong things. */ + discard_cleanups (inf_status_cleanup); + discard_inferior_status (inf_status); + /* The following error message used to say "The expression + which contained the function call has been discarded." + It is a hard concept to explain in a few words. Ideally, + GDB would be able to resume evaluation of the expression + when the function finally is done executing. Perhaps + someday this will be implemented (it would not be easy). */ + /* FIXME: Insert a bunch of wrap_here; name can be very long if it's + a C++ name with arguments and stuff. */ + error ("\ +The program being debugged stopped while in a function called from GDB.\n\ +When the function (%s) is done executing, GDB will silently\n\ +stop (instead of continuing to evaluate the expression containing\n\ +the function call).", name); + } + + /* The above code errors out, so ... */ + internal_error (__FILE__, __LINE__, "... should not be here"); + } + + /* If we get here the called FUNCTION run to completion. */ + + /* On normal return, the stack dummy has been popped already. */ + regcache_cpy_no_passthrough (retbuf, stop_registers); + + /* Restore the inferior status, via its cleanup. At this stage, + leave the RETBUF alone. */ + do_cleanups (inf_status_cleanup); + + /* Figure out the value returned by the function. */ + if (struct_return) + { + /* NOTE: cagney/2003-09-27: This assumes that PUSH_DUMMY_CALL + has correctly stored STRUCT_ADDR in the target. In the past + that hasn't been the case, the old MIPS PUSH_ARGUMENTS + (PUSH_DUMMY_CALL precursor) would silently move the location + of the struct return value making STRUCT_ADDR bogus. If + you're seeing problems with values being returned using the + "struct return convention", check that PUSH_DUMMY_CALL isn't + playing tricks. */ + struct value *retval = value_at (value_type, struct_addr, NULL); + do_cleanups (retbuf_cleanup); + return retval; + } + else + { + /* The non-register case was handled above. */ + struct value *retval = register_value_being_returned (value_type, + retbuf); + do_cleanups (retbuf_cleanup); + return retval; + } +} + +void _initialize_infcall (void); + +void +_initialize_infcall (void) +{ + add_setshow_boolean_cmd ("coerce-float-to-double", class_obscure, + &coerce_float_to_double_p, "\ +Set coercion of floats to doubles when calling functions\n\ +Variables of type float should generally be converted to doubles before\n\ +calling an unprototyped function, and left alone when calling a prototyped\n\ +function. However, some older debug info formats do not provide enough\n\ +information to determine that a function is prototyped. If this flag is\n\ +set, GDB will perform the conversion for a function it considers\n\ +unprototyped.\n\ +The default is to perform the conversion.\n", "\ +Show coercion of floats to doubles when calling functions\n\ +Variables of type float should generally be converted to doubles before\n\ +calling an unprototyped function, and left alone when calling a prototyped\n\ +function. However, some older debug info formats do not provide enough\n\ +information to determine that a function is prototyped. If this flag is\n\ +set, GDB will perform the conversion for a function it considers\n\ +unprototyped.\n\ +The default is to perform the conversion.\n", + NULL, NULL, &setlist, &showlist); + + add_setshow_boolean_cmd ("unwindonsignal", no_class, + &unwind_on_signal_p, "\ +Set unwinding of stack if a signal is received while in a call dummy.\n\ +The unwindonsignal lets the user determine what gdb should do if a signal\n\ +is received while in a function called from gdb (call dummy). If set, gdb\n\ +unwinds the stack and restore the context to what as it was before the call.\n\ +The default is to stop in the frame where the signal was received.", "\ +Set unwinding of stack if a signal is received while in a call dummy.\n\ +The unwindonsignal lets the user determine what gdb should do if a signal\n\ +is received while in a function called from gdb (call dummy). If set, gdb\n\ +unwinds the stack and restore the context to what as it was before the call.\n\ +The default is to stop in the frame where the signal was received.", + NULL, NULL, &setlist, &showlist); +} diff --git a/gdb/infcall.h b/gdb/infcall.h new file mode 100644 index 0000000..05d06e0 --- /dev/null +++ b/gdb/infcall.h @@ -0,0 +1,43 @@ +/* Perform an inferior function call, for GDB, the GNU debugger. + + Copyright 2003 Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#ifndef INFCALL_H +#define INFCALL_H + +struct value; +struct type; + +extern CORE_ADDR find_function_addr (struct value *function, + struct type **retval_type); + +/* Perform a function call in the inferior. + + ARGS is a vector of values of arguments (NARGS of them). FUNCTION + is a value, the function to be called. Returns a value + representing what the function returned. May fail to return, if a + breakpoint or signal is hit during the execution of the function. + + ARGS is modified to contain coerced values. */ + +extern struct value *call_function_by_hand (struct value *function, int nargs, + struct value **args); + +#endif diff --git a/gdb/inflow.h b/gdb/inflow.h new file mode 100644 index 0000000..1cbfa71 --- /dev/null +++ b/gdb/inflow.h @@ -0,0 +1,51 @@ +/* Low level interface to ptrace, for GDB when running under Unix. + + Copyright 2003 Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#ifndef INFLOW_H +#define INFLOW_H + +#include "terminal.h" /* For HAVE_TERMIOS et.al. */ + +#ifdef HAVE_TERMIOS +#define PROCESS_GROUP_TYPE pid_t +#endif + +#ifdef HAVE_TERMIO +#define PROCESS_GROUP_TYPE int +#endif + +#ifdef HAVE_SGTTY +#ifdef SHORT_PGRP +/* This is only used for the ultra. Does it have pid_t? */ +#define PROCESS_GROUP_TYPE short +#else +#define PROCESS_GROUP_TYPE int +#endif +#endif /* sgtty */ + +#ifdef PROCESS_GROUP_TYPE +/* Process group for us and the inferior. Saved and restored just like + {our,inferior}_ttystate. */ +extern PROCESS_GROUP_TYPE our_process_group; +extern PROCESS_GROUP_TYPE inferior_process_group; +#endif + +#endif diff --git a/gdb/infttrace.h b/gdb/infttrace.h new file mode 100644 index 0000000..d3330e3 --- /dev/null +++ b/gdb/infttrace.h @@ -0,0 +1,28 @@ +/* Low level Unix child interface to ttrace, for GDB when running under HP-UX. + + Copyright 2003 Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#ifndef INFTTRACE_H +#define INFTTRACE_H + +extern int parent_attach_all (int, PTRACE_ARG3_TYPE, int); +extern pid_t hppa_switched_threads (pid_t gdb_pid); + +#endif diff --git a/gdb/interps.c b/gdb/interps.c new file mode 100644 index 0000000..82e9af6 --- /dev/null +++ b/gdb/interps.c @@ -0,0 +1,486 @@ +/* Manages interpreters for GDB, the GNU debugger. + + Copyright 2000, 2002, 2003 Free Software Foundation, Inc. + + Written by Jim Ingham of Apple Computer, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +/* This is just a first cut at separating out the "interpreter" + functions of gdb into self-contained modules. There are a couple + of open areas that need to be sorted out: + + 1) The interpreter explicitly contains a UI_OUT, and can insert itself + into the event loop, but it doesn't explicitly contain hooks for readline. + I did this because it seems to me many interpreters won't want to use + the readline command interface, and it is probably simpler to just let + them take over the input in their resume proc. */ + +#include "defs.h" +#include "gdbcmd.h" +#include "ui-out.h" +#include "event-loop.h" +#include "event-top.h" +#include "interps.h" +#include "completer.h" +#include "gdb_string.h" +#include "gdb-events.h" +#include "gdb_assert.h" +#include "top.h" /* For command_loop. */ + +struct interp +{ + /* This is the name in "-i=" and set interpreter. */ + const char *name; + + /* Interpreters are stored in a linked list, this is the next + one... */ + struct interp *next; + + /* This is a cookie that an instance of the interpreter can use. + This is a bit confused right now as the exact initialization + sequence for it, and how it relates to the interpreter's uiout + object is a bit confused. */ + void *data; + + /* Has the init_proc been run? */ + int inited; + + /* This is the ui_out used to collect results for this interpreter. + It can be a formatter for stdout, as is the case for the console + & mi outputs, or it might be a result formatter. */ + struct ui_out *interpreter_out; + + const struct interp_procs *procs; + int quiet_p; +}; + +/* Functions local to this file. */ +static void initialize_interps (void); +static char **interpreter_completer (char *text, char *word); + +/* The magic initialization routine for this module. */ + +void _initialize_interpreter (void); + +/* Variables local to this file: */ + +static struct interp *interp_list = NULL; +static struct interp *current_interpreter = NULL; + +static int interpreter_initialized = 0; + +/* interp_new - This allocates space for a new interpreter, + fills the fields from the inputs, and returns a pointer to the + interpreter. */ +struct interp * +interp_new (const char *name, void *data, struct ui_out *uiout, + const struct interp_procs *procs) +{ + struct interp *new_interp; + + new_interp = XMALLOC (struct interp); + + new_interp->name = xstrdup (name); + new_interp->data = data; + new_interp->interpreter_out = uiout; + new_interp->quiet_p = 0; + new_interp->procs = procs; + new_interp->inited = 0; + + return new_interp; +} + +/* Add interpreter INTERP to the gdb interpreter list. The + interpreter must not have previously been added. */ +void +interp_add (struct interp *interp) +{ + if (!interpreter_initialized) + initialize_interps (); + + gdb_assert (interp_lookup (interp->name) == NULL); + + interp->next = interp_list; + interp_list = interp; +} + +/* This sets the current interpreter to be INTERP. If INTERP has not + been initialized, then this will also run the init proc. If the + init proc is successful, return 1, if it fails, set the old + interpreter back in place and return 0. If we can't restore the + old interpreter, then raise an internal error, since we are in + pretty bad shape at this point. */ +int +interp_set (struct interp *interp) +{ + struct interp *old_interp = current_interpreter; + int first_time = 0; + + + char buffer[64]; + + if (current_interpreter != NULL) + { + do_all_continuations (); + ui_out_flush (uiout); + if (current_interpreter->procs->suspend_proc + && !current_interpreter->procs->suspend_proc (current_interpreter-> + data)) + { + error ("Could not suspend interpreter \"%s\"\n", + current_interpreter->name); + } + } + else + { + first_time = 1; + } + + current_interpreter = interp; + + /* We use interpreter_p for the "set interpreter" variable, so we need + to make sure we have a malloc'ed copy for the set command to free. */ + if (interpreter_p != NULL + && strcmp (current_interpreter->name, interpreter_p) != 0) + { + xfree (interpreter_p); + + interpreter_p = xstrdup (current_interpreter->name); + } + + uiout = interp->interpreter_out; + + /* Run the init proc. If it fails, try to restore the old interp. */ + + if (!interp->inited) + { + if (interp->procs->init_proc != NULL) + { + interp->data = interp->procs->init_proc (); + } + interp->inited = 1; + } + + /* Clear out any installed interpreter hooks/event handlers. */ + clear_interpreter_hooks (); + + if (interp->procs->resume_proc != NULL + && (!interp->procs->resume_proc (interp->data))) + { + if (old_interp == NULL || !interp_set (old_interp)) + internal_error (__FILE__, __LINE__, + "Failed to initialize new interp \"%s\" %s", + interp->name, "and could not restore old interp!\n"); + return 0; + } + + /* Finally, put up the new prompt to show that we are indeed here. + Also, display_gdb_prompt for the console does some readline magic + which is needed for the console interpreter, at least... */ + + if (!first_time) + { + if (!interp_quiet_p (interp)) + { + sprintf (buffer, "Switching to interpreter \"%.24s\".\n", + interp->name); + ui_out_text (uiout, buffer); + } + display_gdb_prompt (NULL); + } + + return 1; +} + +/* interp_lookup - Looks up the interpreter for NAME. If no such + interpreter exists, return NULL, otherwise return a pointer to the + interpreter. */ +struct interp * +interp_lookup (const char *name) +{ + struct interp *interp; + + if (name == NULL || strlen (name) == 0) + return NULL; + + for (interp = interp_list; interp != NULL; interp = interp->next) + { + if (strcmp (interp->name, name) == 0) + return interp; + } + + return NULL; +} + +/* Returns the current interpreter. */ + +struct ui_out * +interp_ui_out (struct interp *interp) +{ + if (interp != NULL) + return interp->interpreter_out; + + return current_interpreter->interpreter_out; +} + +/* Returns true if the current interp is the passed in name. */ +int +current_interp_named_p (const char *interp_name) +{ + if (current_interpreter) + return (strcmp (current_interpreter->name, interp_name) == 0); + + return 0; +} + +/* This is called in display_gdb_prompt. If the proc returns a zero + value, display_gdb_prompt will return without displaying the + prompt. */ +int +current_interp_display_prompt_p (void) +{ + if (current_interpreter == NULL + || current_interpreter->procs->prompt_proc_p == NULL) + return 0; + else + return current_interpreter->procs->prompt_proc_p (current_interpreter-> + data); +} + +/* Run the current command interpreter's main loop. */ +void +current_interp_command_loop (void) +{ + /* Somewhat messy. For the moment prop up all the old ways of + selecting the command loop. `command_loop_hook' should be + deprecated. */ + if (command_loop_hook != NULL) + command_loop_hook (); + else if (current_interpreter != NULL + && current_interpreter->procs->command_loop_proc != NULL) + current_interpreter->procs->command_loop_proc (current_interpreter->data); + else if (event_loop_p) + cli_command_loop (); + else + command_loop (); +} + +int +interp_quiet_p (struct interp *interp) +{ + if (interp != NULL) + return interp->quiet_p; + else + return current_interpreter->quiet_p; +} + +static int +interp_set_quiet (struct interp *interp, int quiet) +{ + int old_val = interp->quiet_p; + interp->quiet_p = quiet; + return old_val; +} + +/* interp_exec - This executes COMMAND_STR in the current + interpreter. */ +int +interp_exec_p (struct interp *interp) +{ + return interp->procs->exec_proc != NULL; +} + +int +interp_exec (struct interp *interp, const char *command_str) +{ + if (interp->procs->exec_proc != NULL) + { + return interp->procs->exec_proc (interp->data, command_str); + } + return 0; +} + +/* A convenience routine that nulls out all the + common command hooks. Use it when removing your interpreter in its + suspend proc. */ +void +clear_interpreter_hooks (void) +{ + init_ui_hook = 0; + print_frame_info_listing_hook = 0; + /*print_frame_more_info_hook = 0; */ + query_hook = 0; + warning_hook = 0; + create_breakpoint_hook = 0; + delete_breakpoint_hook = 0; + modify_breakpoint_hook = 0; + interactive_hook = 0; + registers_changed_hook = 0; + readline_begin_hook = 0; + readline_hook = 0; + readline_end_hook = 0; + register_changed_hook = 0; + memory_changed_hook = 0; + context_hook = 0; + target_wait_hook = 0; + call_command_hook = 0; + error_hook = 0; + error_begin_hook = 0; + command_loop_hook = 0; + clear_gdb_event_hooks (); +} + +/* This is a lazy init routine, called the first time + the interpreter module is used. I put it here just in case, but I haven't + thought of a use for it yet. I will probably bag it soon, since I don't + think it will be necessary. */ +static void +initialize_interps (void) +{ + interpreter_initialized = 1; + /* Don't know if anything needs to be done here... */ +} + +static void +interpreter_exec_cmd (char *args, int from_tty) +{ + struct interp *old_interp, *interp_to_use; + char **prules = NULL; + char **trule = NULL; + unsigned int nrules; + unsigned int i; + int old_quiet, use_quiet; + + prules = buildargv (args); + if (prules == NULL) + { + error ("unable to parse arguments"); + } + + nrules = 0; + if (prules != NULL) + { + for (trule = prules; *trule != NULL; trule++) + { + nrules++; + } + } + + if (nrules < 2) + error ("usage: interpreter-exec [ ... ]"); + + old_interp = current_interpreter; + + interp_to_use = interp_lookup (prules[0]); + if (interp_to_use == NULL) + error ("Could not find interpreter \"%s\".", prules[0]); + + /* Temporarily set interpreters quiet */ + old_quiet = interp_set_quiet (old_interp, 1); + use_quiet = interp_set_quiet (interp_to_use, 1); + + if (!interp_set (interp_to_use)) + error ("Could not switch to interpreter \"%s\".", prules[0]); + + for (i = 1; i < nrules; i++) + { + if (!interp_exec (interp_to_use, prules[i])) + { + interp_set (old_interp); + interp_set_quiet (interp_to_use, old_quiet); + error ("error in command: \"%s\".", prules[i]); + break; + } + } + + interp_set (old_interp); + interp_set_quiet (interp_to_use, use_quiet); + interp_set_quiet (old_interp, old_quiet); +} + +/* List the possible interpreters which could complete the given text. */ +static char ** +interpreter_completer (char *text, char *word) +{ + int alloced = 0; + int textlen; + int num_matches; + char **matches; + struct interp *interp; + + /* We expect only a very limited number of interpreters, so just + allocate room for all of them. */ + for (interp = interp_list; interp != NULL; interp = interp->next) + ++alloced; + matches = (char **) xmalloc (alloced * sizeof (char *)); + + num_matches = 0; + textlen = strlen (text); + for (interp = interp_list; interp != NULL; interp = interp->next) + { + if (strncmp (interp->name, text, textlen) == 0) + { + matches[num_matches] = + (char *) xmalloc (strlen (word) + strlen (interp->name) + 1); + if (word == text) + strcpy (matches[num_matches], interp->name); + else if (word > text) + { + /* Return some portion of interp->name */ + strcpy (matches[num_matches], interp->name + (word - text)); + } + else + { + /* Return some of text plus interp->name */ + strncpy (matches[num_matches], word, text - word); + matches[num_matches][text - word] = '\0'; + strcat (matches[num_matches], interp->name); + } + ++num_matches; + } + } + + if (num_matches == 0) + { + xfree (matches); + matches = NULL; + } + else if (num_matches < alloced) + { + matches = (char **) xrealloc ((char *) matches, ((num_matches + 1) + * sizeof (char *))); + matches[num_matches] = NULL; + } + + return matches; +} + +/* This just adds the "interpreter-exec" command. */ +void +_initialize_interpreter (void) +{ + struct cmd_list_element *c; + + c = add_cmd ("interpreter-exec", class_support, + interpreter_exec_cmd, + "Execute a command in an interpreter. It takes two arguments:\n\ +The first argument is the name of the interpreter to use.\n\ +The second argument is the command to execute.\n", &cmdlist); + set_cmd_completer (c, interpreter_completer); +} diff --git a/gdb/interps.h b/gdb/interps.h new file mode 100644 index 0000000..d24cf6a --- /dev/null +++ b/gdb/interps.h @@ -0,0 +1,75 @@ +/* Manages interpreters for GDB, the GNU debugger. + + Copyright 2000, 2002, 2003 Free Software Foundation, Inc. + + Written by Jim Ingham of Apple Computer, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#ifndef INTERPS_H +#define INTERPS_H + +struct ui_out; +struct interp; + +extern int interp_resume (struct interp *interp); +extern int interp_suspend (struct interp *interp); +extern int interp_prompt_p (struct interp *interp); +extern int interp_exec_p (struct interp *interp); +extern int interp_exec (struct interp *interp, const char *command); +extern int interp_quiet_p (struct interp *interp); + +typedef void *(interp_init_ftype) (void); +typedef int (interp_resume_ftype) (void *data); +typedef int (interp_suspend_ftype) (void *data); +typedef int (interp_prompt_p_ftype) (void *data); +typedef int (interp_exec_ftype) (void *data, const char *command); +typedef void (interp_command_loop_ftype) (void *data); + +struct interp_procs +{ + interp_init_ftype *init_proc; + interp_resume_ftype *resume_proc; + interp_suspend_ftype *suspend_proc; + interp_exec_ftype *exec_proc; + interp_prompt_p_ftype *prompt_proc_p; + interp_command_loop_ftype *command_loop_proc; +}; + +extern struct interp *interp_new (const char *name, void *data, + struct ui_out *uiout, + const struct interp_procs *procs); +extern void interp_add (struct interp *interp); +extern int interp_set (struct interp *interp); +extern struct interp *interp_lookup (const char *name); +extern struct ui_out *interp_ui_out (struct interp *interp); + +extern int current_interp_named_p (const char *name); +extern int current_interp_display_prompt_p (void); +extern void current_interp_command_loop (void); + +extern void clear_interpreter_hooks (void); + +/* well-known interpreters */ +#define INTERP_CONSOLE "console" +#define INTERP_MI1 "mi1" +#define INTERP_MI2 "mi2" +#define INTERP_MI3 "mi3" +#define INTERP_MI "mi" + +#endif diff --git a/gdb/libunwind-frame.c b/gdb/libunwind-frame.c new file mode 100644 index 0000000..bf0c36d --- /dev/null +++ b/gdb/libunwind-frame.c @@ -0,0 +1,387 @@ +/* Frame unwinder for frames using the libunwind library. + + Copyright 2003 Free Software Foundation, Inc. + + Written by Jeff Johnston, contributed by Red Hat Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#include "defs.h" + +#include "inferior.h" +#include "frame.h" +#include "frame-base.h" +#include "frame-unwind.h" +#include "gdbcore.h" +#include "gdbtypes.h" +#include "symtab.h" +#include "objfiles.h" +#include "regcache.h" + +#include + +#include "gdb_assert.h" +#include "gdb_string.h" + +#include "libunwind-frame.h" + +#include "complaints.h" + +static int libunwind_initialized; +static struct gdbarch_data *libunwind_descr_handle; + +#ifndef LIBUNWIND_SO +#define LIBUNWIND_SO "libunwind.so" +#endif + +/* Required function pointers from libunwind. */ +static int (*unw_get_reg_p) (unw_cursor_t *, unw_regnum_t, unw_word_t *); +static int (*unw_get_fpreg_p) (unw_cursor_t *, unw_regnum_t, unw_fpreg_t *); +static int (*unw_get_saveloc_p) (unw_cursor_t *, unw_regnum_t, unw_save_loc_t *); +static int (*unw_step_p) (unw_cursor_t *); +static int (*unw_init_remote_p) (unw_cursor_t *, unw_addr_space_t, void *); +static unw_addr_space_t (*unw_create_addr_space_p) (unw_accessors_t *, int); +static int (*unw_search_unwind_table_p) (unw_addr_space_t, unw_word_t, unw_dyn_info_t *, + unw_proc_info_t *, int, void *); +static unw_word_t (*unw_find_dyn_list_p) (unw_addr_space_t, unw_dyn_info_t *, + void *); + + +struct libunwind_frame_cache +{ + CORE_ADDR base; + CORE_ADDR func_addr; + unw_cursor_t cursor; +}; + +/* We need to qualify the function names with a platform-specific prefix to match + the names used by the libunwind library. The UNW_OBJ macro is provided by the + libunwind.h header file. */ +#define STRINGIFY2(name) #name +#define STRINGIFY(name) STRINGIFY2(name) + +static char *get_reg_name = STRINGIFY(UNW_OBJ(get_reg)); +static char *get_fpreg_name = STRINGIFY(UNW_OBJ(get_fpreg)); +static char *get_saveloc_name = STRINGIFY(UNW_OBJ(get_save_loc)); +static char *step_name = STRINGIFY(UNW_OBJ(step)); +static char *init_remote_name = STRINGIFY(UNW_OBJ(init_remote)); +static char *create_addr_space_name = STRINGIFY(UNW_OBJ(create_addr_space)); +static char *search_unwind_table_name = STRINGIFY(UNW_OBJ(search_unwind_table)); +static char *find_dyn_list_name = STRINGIFY(UNW_OBJ(find_dyn_list)); + +static struct libunwind_descr * +libunwind_descr (struct gdbarch *gdbarch) +{ + return gdbarch_data (gdbarch, libunwind_descr_handle); +} + +static void * +libunwind_descr_init (struct gdbarch *gdbarch) +{ + struct libunwind_descr *descr = GDBARCH_OBSTACK_ZALLOC (gdbarch, + struct libunwind_descr); + return descr; +} + +void +libunwind_frame_set_descr (struct gdbarch *gdbarch, struct libunwind_descr *descr) +{ + struct libunwind_descr *arch_descr; + + gdb_assert (gdbarch != NULL); + + arch_descr = gdbarch_data (gdbarch, libunwind_descr_handle); + + if (arch_descr == NULL) + { + /* First time here. Must initialize data area. */ + arch_descr = libunwind_descr_init (gdbarch); + set_gdbarch_data (gdbarch, libunwind_descr_handle, arch_descr); + } + + /* Copy new descriptor info into arch descriptor. */ + arch_descr->gdb2uw = descr->gdb2uw; + arch_descr->uw2gdb = descr->uw2gdb; + arch_descr->is_fpreg = descr->is_fpreg; + arch_descr->accessors = descr->accessors; +} + +static struct libunwind_frame_cache * +libunwind_frame_cache (struct frame_info *next_frame, void **this_cache) +{ + unw_accessors_t *acc; + unw_addr_space_t as; + unw_word_t fp; + unw_regnum_t uw_sp_regnum; + struct libunwind_frame_cache *cache; + struct libunwind_descr *descr; + int i, ret; + + if (*this_cache) + return *this_cache; + + /* Allocate a new cache. */ + cache = FRAME_OBSTACK_ZALLOC (struct libunwind_frame_cache); + + cache->func_addr = frame_func_unwind (next_frame); + + /* Get a libunwind cursor to the previous frame. We do this by initializing + a cursor. Libunwind treats a new cursor as the top of stack and will get + the current register set via the libunwind register accessor. Now, we + provide the platform-specific accessors and we set up the register accessor to use + the frame register unwinding interfaces so that we properly get the registers for + the current frame rather than the top. We then use the unw_step function to + move the libunwind cursor back one frame. We can later use this cursor to find previous + registers via the unw_get_reg interface which will invoke libunwind's special logic. */ + descr = libunwind_descr (get_frame_arch (next_frame)); + acc = descr->accessors; + as = unw_create_addr_space_p (acc, + TARGET_BYTE_ORDER == BFD_ENDIAN_BIG + ? __BIG_ENDIAN + : __LITTLE_ENDIAN); + + unw_init_remote_p (&cache->cursor, as, next_frame); + unw_step_p (&cache->cursor); + + /* To get base address, get sp from previous frame. */ + uw_sp_regnum = descr->gdb2uw (SP_REGNUM); + ret = unw_get_reg_p (&cache->cursor, uw_sp_regnum, &fp); + if (ret < 0) + error ("Can't get libunwind sp register."); + + cache->base = (CORE_ADDR)fp; + + *this_cache = cache; + return cache; +} + +unw_word_t +libunwind_find_dyn_list (unw_addr_space_t as, unw_dyn_info_t *di, void *arg) +{ + return unw_find_dyn_list_p (as, di, arg); +} + +static const struct frame_unwind libunwind_frame_unwind = +{ + NORMAL_FRAME, + libunwind_frame_this_id, + libunwind_frame_prev_register +}; + +/* Verify if there is sufficient libunwind information for the frame to use + libunwind frame unwinding. */ +const struct frame_unwind * +libunwind_frame_sniffer (struct frame_info *next_frame) +{ + unw_cursor_t cursor; + unw_accessors_t *acc; + unw_addr_space_t as; + struct libunwind_descr *descr; + int i, ret; + + /* To test for libunwind unwind support, initialize a cursor to the current frame and try to back + up. We use this same method when setting up the frame cache (see libunwind_frame_cache()). + If libunwind returns success for this operation, it means that it has found sufficient + libunwind unwinding information to do so. */ + + descr = libunwind_descr (get_frame_arch (next_frame)); + acc = descr->accessors; + as = unw_create_addr_space_p (acc, + TARGET_BYTE_ORDER == BFD_ENDIAN_BIG + ? __BIG_ENDIAN + : __LITTLE_ENDIAN); + + ret = unw_init_remote_p (&cursor, as, next_frame); + + if (ret >= 0) + ret = unw_step_p (&cursor); + + if (ret < 0) + return NULL; + + return &libunwind_frame_unwind; +} + +void +libunwind_frame_this_id (struct frame_info *next_frame, void **this_cache, + struct frame_id *this_id) +{ + struct libunwind_frame_cache *cache = + libunwind_frame_cache (next_frame, this_cache); + + (*this_id) = frame_id_build (cache->base, cache->func_addr); +} + +void +libunwind_frame_prev_register (struct frame_info *next_frame, void **this_cache, + int regnum, int *optimizedp, + enum lval_type *lvalp, CORE_ADDR *addrp, + int *realnump, void *valuep) +{ + struct libunwind_frame_cache *cache = + libunwind_frame_cache (next_frame, this_cache); + + void *ptr; + unw_cursor_t *c; + unw_save_loc_t sl; + int i, ret; + unw_word_t intval; + unw_fpreg_t fpval; + unw_regnum_t uw_regnum; + struct libunwind_descr *descr; + + /* Convert from gdb register number to libunwind register number. */ + descr = libunwind_descr (get_frame_arch (next_frame)); + uw_regnum = descr->gdb2uw (regnum); + + gdb_assert (regnum >= 0); + + if (!target_has_registers) + error ("No registers."); + + *optimizedp = 0; + *addrp = 0; + *lvalp = not_lval; + *realnump = -1; + + memset (valuep, 0, register_size (current_gdbarch, regnum)); + + if (uw_regnum < 0) + return; + + /* To get the previous register, we use the libunwind register APIs with + the cursor we have already pushed back to the previous frame. */ + + if (descr->is_fpreg (uw_regnum)) + { + ret = unw_get_fpreg_p (&cache->cursor, uw_regnum, &fpval); + ptr = &fpval; + } + else + { + ret = unw_get_reg_p (&cache->cursor, uw_regnum, &intval); + ptr = &intval; + } + + if (ret < 0) + return; + + memcpy (valuep, ptr, register_size (current_gdbarch, regnum)); + + if (unw_get_saveloc_p (&cache->cursor, uw_regnum, &sl) < 0) + return; + + switch (sl.type) + { + case UNW_SLT_NONE: + *optimizedp = 1; + break; + + case UNW_SLT_MEMORY: + *lvalp = lval_memory; + *addrp = sl.u.addr; + break; + + case UNW_SLT_REG: + *lvalp = lval_register; + *realnump = regnum; + break; + } +} + +CORE_ADDR +libunwind_frame_base_address (struct frame_info *next_frame, void **this_cache) +{ + struct libunwind_frame_cache *cache = + libunwind_frame_cache (next_frame, this_cache); + + return cache->base; +} + +/* The following is a glue routine to call the libunwind unwind table + search function to get unwind information for a specified ip address. */ +int +libunwind_search_unwind_table (void *as, long ip, void *di, + void *pi, int need_unwind_info, void *args) +{ + return unw_search_unwind_table_p (*(unw_addr_space_t *)as, (unw_word_t )ip, + di, pi, need_unwind_info, args); +} + +static int +libunwind_load (void) +{ + void *handle; + + handle = dlopen (LIBUNWIND_SO, RTLD_NOW); + if (handle == NULL) + return 0; + + /* Initialize pointers to the dynamic library functions we will use. */ + + unw_get_reg_p = dlsym (handle, get_reg_name); + if (unw_get_reg_p == NULL) + return 0; + + unw_get_fpreg_p = dlsym (handle, get_fpreg_name); + if (unw_get_fpreg_p == NULL) + return 0; + + unw_get_saveloc_p = dlsym (handle, get_saveloc_name); + if (unw_get_saveloc_p == NULL) + return 0; + + unw_step_p = dlsym (handle, step_name); + if (unw_step_p == NULL) + return 0; + + unw_init_remote_p = dlsym (handle, init_remote_name); + if (unw_init_remote_p == NULL) + return 0; + + unw_create_addr_space_p = dlsym (handle, create_addr_space_name); + if (unw_create_addr_space_p == NULL) + return 0; + + unw_search_unwind_table_p = dlsym (handle, search_unwind_table_name); + if (unw_search_unwind_table_p == NULL) + return 0; + + unw_find_dyn_list_p = dlsym (handle, find_dyn_list_name); + if (unw_find_dyn_list_p == NULL) + return 0; + + return 1; +} + +int +libunwind_is_initialized (void) +{ + return libunwind_initialized; +} + +/* Provide a prototype to silence -Wmissing-prototypes. */ +void _initialize_libunwind_frame (void); + +void +_initialize_libunwind_frame (void) +{ + libunwind_descr_handle = register_gdbarch_data (libunwind_descr_init); + + libunwind_initialized = libunwind_load (); +} diff --git a/gdb/libunwind-frame.h b/gdb/libunwind-frame.h new file mode 100644 index 0000000..bacdf87 --- /dev/null +++ b/gdb/libunwind-frame.h @@ -0,0 +1,63 @@ +/* Frame unwinder for frames with libunwind frame information. + + Copyright 2003 Free Software Foundation, Inc. + + Contributed by Jeff Johnston. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#ifdef HAVE_LIBUNWIND_H + +#ifndef LIBUNWIND_FRAME_H +#define LIBUNWIND_FRAME_H 1 + +#include "libunwind.h" + +struct frame_info; + +struct libunwind_descr +{ + int (*gdb2uw) (int); + int (*uw2gdb) (int); + int (*is_fpreg) (int); + void *accessors; +}; + +const struct frame_unwind *libunwind_frame_sniffer (struct frame_info *next_frame); + +void libunwind_frame_set_descr (struct gdbarch *arch, struct libunwind_descr *descr); + +void libunwind_frame_this_id (struct frame_info *next_frame, void **this_cache, + struct frame_id *this_id); +void libunwind_frame_prev_register (struct frame_info *next_frame, void **this_cache, + int regnum, int *optimizedp, + enum lval_type *lvalp, CORE_ADDR *addrp, + int *realnump, void *valuep); +CORE_ADDR libunwind_frame_base_address (struct frame_info *next_frame, void **this_cache); + +int libunwind_is_initialized (void); + +int libunwind_search_unwind_table (void *as, long ip, void *di, + void *pi, int need_unwind_info, void *args); + +unw_word_t libunwind_find_dyn_list (unw_addr_space_t, unw_dyn_info_t *, + void *); + +#endif /* libunwind-frame.h */ + +#endif /* HAVE_LIBUNWIND_H */ diff --git a/gdb/linux-nat.c b/gdb/linux-nat.c new file mode 100644 index 0000000..2680422 --- /dev/null +++ b/gdb/linux-nat.c @@ -0,0 +1,520 @@ +/* GNU/Linux native-dependent code common to multiple platforms. + Copyright (C) 2003 Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#include "defs.h" +#include "inferior.h" +#include "target.h" + +#include "gdb_wait.h" +#include + +#include "linux-nat.h" + +/* If the system headers did not provide the constants, hard-code the normal + values. */ +#ifndef PTRACE_EVENT_FORK + +#define PTRACE_SETOPTIONS 0x4200 +#define PTRACE_GETEVENTMSG 0x4201 + +/* options set using PTRACE_SETOPTIONS */ +#define PTRACE_O_TRACESYSGOOD 0x00000001 +#define PTRACE_O_TRACEFORK 0x00000002 +#define PTRACE_O_TRACEVFORK 0x00000004 +#define PTRACE_O_TRACECLONE 0x00000008 +#define PTRACE_O_TRACEEXEC 0x00000010 +#define PTRACE_O_TRACEVFORKDONE 0x00000020 +#define PTRACE_O_TRACEEXIT 0x00000040 + +/* Wait extended result codes for the above trace options. */ +#define PTRACE_EVENT_FORK 1 +#define PTRACE_EVENT_VFORK 2 +#define PTRACE_EVENT_CLONE 3 +#define PTRACE_EVENT_EXEC 4 +#define PTRACE_EVENT_VFORKDONE 5 +#define PTRACE_EVENT_EXIT 6 + +#endif /* PTRACE_EVENT_FORK */ + +/* We can't always assume that this flag is available, but all systems + with the ptrace event handlers also have __WALL, so it's safe to use + here. */ +#ifndef __WALL +#define __WALL 0x40000000 /* Wait for any child. */ +#endif + +extern struct target_ops child_ops; + +static int linux_parent_pid; + +struct simple_pid_list +{ + int pid; + struct simple_pid_list *next; +}; +struct simple_pid_list *stopped_pids; + +/* This variable is a tri-state flag: -1 for unknown, 0 if PTRACE_O_TRACEFORK + can not be used, 1 if it can. */ + +static int linux_supports_tracefork_flag = -1; + +/* If we have PTRACE_O_TRACEFORK, this flag indicates whether we also have + PTRACE_O_TRACEVFORKDONE. */ + +static int linux_supports_tracevforkdone_flag = -1; + + +/* Trivial list manipulation functions to keep track of a list of + new stopped processes. */ +static void +add_to_pid_list (struct simple_pid_list **listp, int pid) +{ + struct simple_pid_list *new_pid = xmalloc (sizeof (struct simple_pid_list)); + new_pid->pid = pid; + new_pid->next = *listp; + *listp = new_pid; +} + +static int +pull_pid_from_list (struct simple_pid_list **listp, int pid) +{ + struct simple_pid_list **p; + + for (p = listp; *p != NULL; p = &(*p)->next) + if ((*p)->pid == pid) + { + struct simple_pid_list *next = (*p)->next; + xfree (*p); + *p = next; + return 1; + } + return 0; +} + +void +linux_record_stopped_pid (int pid) +{ + add_to_pid_list (&stopped_pids, pid); +} + + +/* A helper function for linux_test_for_tracefork, called after fork (). */ + +static void +linux_tracefork_child (void) +{ + int ret; + + ptrace (PTRACE_TRACEME, 0, 0, 0); + kill (getpid (), SIGSTOP); + fork (); + exit (0); +} + +/* Determine if PTRACE_O_TRACEFORK can be used to follow fork events. We + create a child process, attach to it, use PTRACE_SETOPTIONS to enable + fork tracing, and let it fork. If the process exits, we assume that + we can't use TRACEFORK; if we get the fork notification, and we can + extract the new child's PID, then we assume that we can. */ + +static void +linux_test_for_tracefork (void) +{ + int child_pid, ret, status; + long second_pid; + + child_pid = fork (); + if (child_pid == -1) + perror_with_name ("linux_test_for_tracefork: fork"); + + if (child_pid == 0) + linux_tracefork_child (); + + ret = waitpid (child_pid, &status, 0); + if (ret == -1) + perror_with_name ("linux_test_for_tracefork: waitpid"); + else if (ret != child_pid) + error ("linux_test_for_tracefork: waitpid: unexpected result %d.", ret); + if (! WIFSTOPPED (status)) + error ("linux_test_for_tracefork: waitpid: unexpected status %d.", status); + + linux_supports_tracefork_flag = 0; + + ret = ptrace (PTRACE_SETOPTIONS, child_pid, 0, PTRACE_O_TRACEFORK); + if (ret != 0) + { + ptrace (PTRACE_KILL, child_pid, 0, 0); + waitpid (child_pid, &status, 0); + return; + } + + /* Check whether PTRACE_O_TRACEVFORKDONE is available. */ + ret = ptrace (PTRACE_SETOPTIONS, child_pid, 0, + PTRACE_O_TRACEFORK | PTRACE_O_TRACEVFORKDONE); + linux_supports_tracevforkdone_flag = (ret == 0); + + ptrace (PTRACE_CONT, child_pid, 0, 0); + ret = waitpid (child_pid, &status, 0); + if (ret == child_pid && WIFSTOPPED (status) + && status >> 16 == PTRACE_EVENT_FORK) + { + second_pid = 0; + ret = ptrace (PTRACE_GETEVENTMSG, child_pid, 0, &second_pid); + if (ret == 0 && second_pid != 0) + { + int second_status; + + linux_supports_tracefork_flag = 1; + waitpid (second_pid, &second_status, 0); + ptrace (PTRACE_DETACH, second_pid, 0, 0); + } + } + + if (WIFSTOPPED (status)) + { + ptrace (PTRACE_DETACH, child_pid, 0, 0); + waitpid (child_pid, &status, 0); + } +} + +/* Return non-zero iff we have tracefork functionality available. + This function also sets linux_supports_tracefork_flag. */ + +static int +linux_supports_tracefork (void) +{ + if (linux_supports_tracefork_flag == -1) + linux_test_for_tracefork (); + return linux_supports_tracefork_flag; +} + +static int +linux_supports_tracevforkdone (void) +{ + if (linux_supports_tracefork_flag == -1) + linux_test_for_tracefork (); + return linux_supports_tracevforkdone_flag; +} + + +void +linux_enable_event_reporting (ptid_t ptid) +{ + int pid = ptid_get_pid (ptid); + int options; + + if (! linux_supports_tracefork ()) + return; + + options = PTRACE_O_TRACEFORK | PTRACE_O_TRACEVFORK | PTRACE_O_TRACEEXEC; + if (linux_supports_tracevforkdone ()) + options |= PTRACE_O_TRACEVFORKDONE; + + /* Do not enable PTRACE_O_TRACEEXIT until GDB is more prepared to support + read-only process state. */ + + ptrace (PTRACE_SETOPTIONS, pid, 0, options); +} + +void +child_post_attach (int pid) +{ + linux_enable_event_reporting (pid_to_ptid (pid)); +} + +void +linux_child_post_startup_inferior (ptid_t ptid) +{ + linux_enable_event_reporting (ptid); +} + +#ifndef LINUX_CHILD_POST_STARTUP_INFERIOR +void +child_post_startup_inferior (ptid_t ptid) +{ + linux_child_post_startup_inferior (ptid); +} +#endif + +int +child_follow_fork (int follow_child) +{ + ptid_t last_ptid; + struct target_waitstatus last_status; + int has_vforked; + int parent_pid, child_pid; + + get_last_target_status (&last_ptid, &last_status); + has_vforked = (last_status.kind == TARGET_WAITKIND_VFORKED); + parent_pid = ptid_get_pid (last_ptid); + child_pid = last_status.value.related_pid; + + if (! follow_child) + { + /* We're already attached to the parent, by default. */ + + /* Before detaching from the child, remove all breakpoints from + it. (This won't actually modify the breakpoint list, but will + physically remove the breakpoints from the child.) */ + /* If we vforked this will remove the breakpoints from the parent + also, but they'll be reinserted below. */ + detach_breakpoints (child_pid); + + fprintf_filtered (gdb_stdout, + "Detaching after fork from child process %d.\n", + child_pid); + + ptrace (PTRACE_DETACH, child_pid, 0, 0); + + if (has_vforked) + { + if (linux_supports_tracevforkdone ()) + { + int status; + + ptrace (PTRACE_CONT, parent_pid, 0, 0); + waitpid (parent_pid, &status, __WALL); + if ((status >> 16) != PTRACE_EVENT_VFORKDONE) + warning ("Unexpected waitpid result %06x when waiting for " + "vfork-done", status); + } + else + { + /* We can't insert breakpoints until the child has + finished with the shared memory region. We need to + wait until that happens. Ideal would be to just + call: + - ptrace (PTRACE_SYSCALL, parent_pid, 0, 0); + - waitpid (parent_pid, &status, __WALL); + However, most architectures can't handle a syscall + being traced on the way out if it wasn't traced on + the way in. + + We might also think to loop, continuing the child + until it exits or gets a SIGTRAP. One problem is + that the child might call ptrace with PTRACE_TRACEME. + + There's no simple and reliable way to figure out when + the vforked child will be done with its copy of the + shared memory. We could step it out of the syscall, + two instructions, let it go, and then single-step the + parent once. When we have hardware single-step, this + would work; with software single-step it could still + be made to work but we'd have to be able to insert + single-step breakpoints in the child, and we'd have + to insert -just- the single-step breakpoint in the + parent. Very awkward. + + In the end, the best we can do is to make sure it + runs for a little while. Hopefully it will be out of + range of any breakpoints we reinsert. Usually this + is only the single-step breakpoint at vfork's return + point. */ + + usleep (10000); + } + + /* Since we vforked, breakpoints were removed in the parent + too. Put them back. */ + reattach_breakpoints (parent_pid); + } + } + else + { + char child_pid_spelling[40]; + + /* Needed to keep the breakpoint lists in sync. */ + if (! has_vforked) + detach_breakpoints (child_pid); + + /* Before detaching from the parent, remove all breakpoints from it. */ + remove_breakpoints (); + + fprintf_filtered (gdb_stdout, + "Attaching after fork to child process %d.\n", + child_pid); + + /* If we're vforking, we may want to hold on to the parent until + the child exits or execs. At exec time we can remove the old + breakpoints from the parent and detach it; at exit time we + could do the same (or even, sneakily, resume debugging it - the + child's exec has failed, or something similar). + + This doesn't clean up "properly", because we can't call + target_detach, but that's OK; if the current target is "child", + then it doesn't need any further cleanups, and lin_lwp will + generally not encounter vfork (vfork is defined to fork + in libpthread.so). + + The holding part is very easy if we have VFORKDONE events; + but keeping track of both processes is beyond GDB at the + moment. So we don't expose the parent to the rest of GDB. + Instead we quietly hold onto it until such time as we can + safely resume it. */ + + if (has_vforked) + linux_parent_pid = parent_pid; + else + target_detach (NULL, 0); + + inferior_ptid = pid_to_ptid (child_pid); + push_target (&child_ops); + + /* Reset breakpoints in the child as appropriate. */ + follow_inferior_reset_breakpoints (); + } + + return 0; +} + +ptid_t +linux_handle_extended_wait (int pid, int status, + struct target_waitstatus *ourstatus) +{ + int event = status >> 16; + + if (event == PTRACE_EVENT_CLONE) + internal_error (__FILE__, __LINE__, + "unexpected clone event"); + + if (event == PTRACE_EVENT_FORK || event == PTRACE_EVENT_VFORK) + { + unsigned long new_pid; + int ret; + + ptrace (PTRACE_GETEVENTMSG, pid, 0, &new_pid); + + /* If we haven't already seen the new PID stop, wait for it now. */ + if (! pull_pid_from_list (&stopped_pids, new_pid)) + { + /* The new child has a pending SIGSTOP. We can't affect it until it + hits the SIGSTOP, but we're already attached. + + It won't be a clone (we didn't ask for clones in the event mask) + so we can just call waitpid and wait for the SIGSTOP. */ + do { + ret = waitpid (new_pid, &status, 0); + } while (ret == -1 && errno == EINTR); + if (ret == -1) + perror_with_name ("waiting for new child"); + else if (ret != new_pid) + internal_error (__FILE__, __LINE__, + "wait returned unexpected PID %d", ret); + else if (!WIFSTOPPED (status) || WSTOPSIG (status) != SIGSTOP) + internal_error (__FILE__, __LINE__, + "wait returned unexpected status 0x%x", status); + } + + ourstatus->kind = (event == PTRACE_EVENT_FORK) + ? TARGET_WAITKIND_FORKED : TARGET_WAITKIND_VFORKED; + ourstatus->value.related_pid = new_pid; + return inferior_ptid; + } + + if (event == PTRACE_EVENT_EXEC) + { + ourstatus->kind = TARGET_WAITKIND_EXECD; + ourstatus->value.execd_pathname + = xstrdup (child_pid_to_exec_file (pid)); + + if (linux_parent_pid) + { + detach_breakpoints (linux_parent_pid); + ptrace (PTRACE_DETACH, linux_parent_pid, 0, 0); + + linux_parent_pid = 0; + } + + return inferior_ptid; + } + + internal_error (__FILE__, __LINE__, + "unknown ptrace event %d", event); +} + + +int +child_insert_fork_catchpoint (int pid) +{ + if (! linux_supports_tracefork ()) + error ("Your system does not support fork catchpoints."); + + return 0; +} + +int +child_insert_vfork_catchpoint (int pid) +{ + if (!linux_supports_tracefork ()) + error ("Your system does not support vfork catchpoints."); + + return 0; +} + +int +child_insert_exec_catchpoint (int pid) +{ + if (!linux_supports_tracefork ()) + error ("Your system does not support exec catchpoints."); + + return 0; +} + +void +kill_inferior (void) +{ + int status; + int pid = PIDGET (inferior_ptid); + struct target_waitstatus last; + ptid_t last_ptid; + int ret; + + if (pid == 0) + return; + + /* If we're stopped while forking and we haven't followed yet, kill the + other task. We need to do this first because the parent will be + sleeping if this is a vfork. */ + + get_last_target_status (&last_ptid, &last); + + if (last.kind == TARGET_WAITKIND_FORKED + || last.kind == TARGET_WAITKIND_VFORKED) + { + ptrace (PT_KILL, last.value.related_pid); + ptrace_wait (null_ptid, &status); + } + + /* Kill the current process. */ + ptrace (PT_KILL, pid, (PTRACE_ARG3_TYPE) 0, 0); + ret = ptrace_wait (null_ptid, &status); + + /* We might get a SIGCHLD instead of an exit status. This is + aggravated by the first kill above - a child has just died. */ + + while (ret == pid && WIFSTOPPED (status)) + { + ptrace (PT_KILL, pid, (PTRACE_ARG3_TYPE) 0, 0); + ret = ptrace_wait (null_ptid, &status); + } + + target_mourn_inferior (); +} diff --git a/gdb/linux-nat.h b/gdb/linux-nat.h new file mode 100644 index 0000000..23730bb --- /dev/null +++ b/gdb/linux-nat.h @@ -0,0 +1,82 @@ +/* Native debugging support for GNU/Linux (LWP layer). + Copyright 2000, 2001, 2002, 2003 Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +/* Structure describing an LWP. */ + +struct lwp_info +{ + /* The process id of the LWP. This is a combination of the LWP id + and overall process id. */ + ptid_t ptid; + + /* Non-zero if this LWP is cloned. In this context "cloned" means + that the LWP is reporting to its parent using a signal other than + SIGCHLD. */ + int cloned; + + /* Non-zero if we sent this LWP a SIGSTOP (but the LWP didn't report + it back yet). */ + int signalled; + + /* Non-zero if this LWP is stopped. */ + int stopped; + + /* Non-zero if this LWP will be/has been resumed. Note that an LWP + can be marked both as stopped and resumed at the same time. This + happens if we try to resume an LWP that has a wait status + pending. We shouldn't let the LWP run until that wait status has + been processed, but we should not report that wait status if GDB + didn't try to let the LWP run. */ + int resumed; + + /* If non-zero, a pending wait status. */ + int status; + + /* Non-zero if we were stepping this LWP. */ + int step; + + /* Next LWP in list. */ + struct lwp_info *next; +}; + +/* Read/write to target memory via the Linux kernel's "proc file + system". */ +struct mem_attrib; +struct target_ops; +struct target_waitstatus; + +extern int linux_proc_xfer_memory (CORE_ADDR addr, char *myaddr, int len, + int write, struct mem_attrib *attrib, + struct target_ops *target); + +/* Find process PID's pending signal set from /proc/pid/status. */ +void linux_proc_pending_signals (int pid, sigset_t *pending, sigset_t *blocked, sigset_t *ignored); + +/* linux-nat functions for handling fork events. */ +extern void linux_record_stopped_pid (int pid); +extern void linux_enable_event_reporting (ptid_t ptid); +extern ptid_t linux_handle_extended_wait (int pid, int status, + struct target_waitstatus *ourstatus); +extern void linux_child_post_startup_inferior (ptid_t ptid); + +/* Iterator function for lin-lwp's lwp list. */ +struct lwp_info *iterate_over_lwps (int (*callback) (struct lwp_info *, + void *), + void *data); diff --git a/gdb/m68k-tdep.h b/gdb/m68k-tdep.h new file mode 100644 index 0000000..702e4fc --- /dev/null +++ b/gdb/m68k-tdep.h @@ -0,0 +1,88 @@ +/* Common target dependent code for the Motorola 68000 series. + Copyright 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1999, 2000, 2001, 2003 + Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#ifndef M68K_TDEP_H +#define M68K_TDEP_H + +struct frame_info; + +/* Register numbers of various important registers. + Note that some of these values are "real" register numbers, + and correspond to the general registers of the machine, + and some are "phony" register numbers which are too large + to be actual register numbers as far as the user is concerned + but do serve to get the desired values when passed to read_register. */ + +enum +{ + M68K_D0_REGNUM = 0, + M68K_D1_REGNUM = 1, + M68K_A0_REGNUM = 8, + M68K_A1_REGNUM = 9, + M68K_FP_REGNUM = 14, /* Contains address of executing stack frame */ + M68K_SP_REGNUM = 15, /* Contains address of top of stack */ + M68K_PS_REGNUM = 16, /* Contains processor status */ + M68K_PC_REGNUM = 17, /* Contains program counter */ + M68K_FP0_REGNUM = 18, /* Floating point register 0 */ + M68K_FPC_REGNUM = 26, /* 68881 control register */ + M68K_FPS_REGNUM = 27, /* 68881 status register */ + M68K_FPI_REGNUM = 28 +}; + +#define M68K_NUM_REGS (M68K_FPI_REGNUM + 1) + +/* Size of the largest register. */ +#define M68K_MAX_REGISTER_SIZE 12 + +struct m68k_sigtramp_info +{ + /* Address of sigcontext. */ + CORE_ADDR sigcontext_addr; + + /* Offset of registers in `struct sigcontext'. */ + int *sc_reg_offset; +}; + +/* Convention for returning structures. */ + +enum struct_return +{ + pcc_struct_return, /* Return "short" structures in memory. */ + reg_struct_return /* Return "short" structures in registers. */ +}; + +/* Target-dependent structure in gdbarch. */ +struct gdbarch_tdep +{ + /* Offset to PC value in the jump buffer. If this is negative, + longjmp support will be disabled. */ + int jb_pc; + /* The size of each entry in the jump buffer. */ + size_t jb_elt_size; + + /* Get info about sigtramp. */ + struct m68k_sigtramp_info (*get_sigtramp_info) (struct frame_info *); + + /* Convention for returning structures. */ + enum struct_return struct_return; +}; + +#endif /* M68K_TDEP_H */ diff --git a/gdb/m68klinux-tdep.c b/gdb/m68klinux-tdep.c new file mode 100644 index 0000000..b39eebe --- /dev/null +++ b/gdb/m68klinux-tdep.c @@ -0,0 +1,312 @@ +/* Motorola m68k target-dependent support for GNU/Linux. + + Copyright 1996, 1998, 2000, 2001, 2002, 2003 Free Software Foundation, + Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#include "defs.h" +#include "gdbcore.h" +#include "doublest.h" +#include "floatformat.h" +#include "frame.h" +#include "target.h" +#include "gdb_string.h" +#include "gdbtypes.h" +#include "osabi.h" +#include "regcache.h" +#include "objfiles.h" +#include "symtab.h" +#include "m68k-tdep.h" + +/* Offsets (in target ints) into jmp_buf. */ + +#define M68K_LINUX_JB_ELEMENT_SIZE 4 +#define M68K_LINUX_JB_PC 7 + +/* Check whether insn1 and insn2 are parts of a signal trampoline. */ + +#define IS_SIGTRAMP(insn1, insn2) \ + (/* addaw #20,sp; moveq #119,d0; trap #0 */ \ + (insn1 == 0xdefc0014 && insn2 == 0x70774e40) \ + /* moveq #119,d0; trap #0 */ \ + || insn1 == 0x70774e40) + +#define IS_RT_SIGTRAMP(insn1, insn2) \ + (/* movel #173,d0; trap #0 */ \ + (insn1 == 0x203c0000 && insn2 == 0x00ad4e40) \ + /* moveq #82,d0; notb d0; trap #0 */ \ + || (insn1 == 0x70524600 && (insn2 >> 16) == 0x4e40)) + +/* Return non-zero if PC points into the signal trampoline. For the + sake of m68k_linux_get_sigtramp_info we also distinguish between + non-RT and RT signal trampolines. */ + +static int +m68k_linux_pc_in_sigtramp (CORE_ADDR pc, char *name) +{ + CORE_ADDR sp; + char buf[12]; + unsigned long insn0, insn1, insn2; + + if (read_memory_nobpt (pc - 4, buf, sizeof (buf))) + return 0; + insn1 = extract_unsigned_integer (buf + 4, 4); + insn2 = extract_unsigned_integer (buf + 8, 4); + if (IS_SIGTRAMP (insn1, insn2)) + return 1; + if (IS_RT_SIGTRAMP (insn1, insn2)) + return 2; + + insn0 = extract_unsigned_integer (buf, 4); + if (IS_SIGTRAMP (insn0, insn1)) + return 1; + if (IS_RT_SIGTRAMP (insn0, insn1)) + return 2; + + insn0 = ((insn0 << 16) & 0xffffffff) | (insn1 >> 16); + insn1 = ((insn1 << 16) & 0xffffffff) | (insn2 >> 16); + if (IS_SIGTRAMP (insn0, insn1)) + return 1; + if (IS_RT_SIGTRAMP (insn0, insn1)) + return 2; + + return 0; +} + +/* From . */ +static int m68k_linux_sigcontext_reg_offset[M68K_NUM_REGS] = +{ + 2 * 4, /* %d0 */ + 3 * 4, /* %d1 */ + -1, /* %d2 */ + -1, /* %d3 */ + -1, /* %d4 */ + -1, /* %d5 */ + -1, /* %d6 */ + -1, /* %d7 */ + 4 * 4, /* %a0 */ + 5 * 4, /* %a1 */ + -1, /* %a2 */ + -1, /* %a3 */ + -1, /* %a4 */ + -1, /* %a5 */ + -1, /* %fp */ + 1 * 4, /* %sp */ + 5 * 4 + 2, /* %sr */ + 6 * 4 + 2, /* %pc */ + 8 * 4, /* %fp0 */ + 11 * 4, /* %fp1 */ + -1, /* %fp2 */ + -1, /* %fp3 */ + -1, /* %fp4 */ + -1, /* %fp5 */ + -1, /* %fp6 */ + -1, /* %fp7 */ + 14 * 4, /* %fpcr */ + 15 * 4, /* %fpsr */ + 16 * 4 /* %fpiaddr */ +}; + +/* From . */ +static int m68k_linux_ucontext_reg_offset[M68K_NUM_REGS] = +{ + 6 * 4, /* %d0 */ + 7 * 4, /* %d1 */ + 8 * 4, /* %d2 */ + 9 * 4, /* %d3 */ + 10 * 4, /* %d4 */ + 11 * 4, /* %d5 */ + 12 * 4, /* %d6 */ + 13 * 4, /* %d7 */ + 14 * 4, /* %a0 */ + 15 * 4, /* %a1 */ + 16 * 4, /* %a2 */ + 17 * 4, /* %a3 */ + 18 * 4, /* %a4 */ + 19 * 4, /* %a5 */ + 20 * 4, /* %fp */ + 21 * 4, /* %sp */ + 23 * 4, /* %sr */ + 22 * 4, /* %pc */ + 27 * 4, /* %fp0 */ + 30 * 4, /* %fp1 */ + 33 * 4, /* %fp2 */ + 36 * 4, /* %fp3 */ + 39 * 4, /* %fp4 */ + 42 * 4, /* %fp5 */ + 45 * 4, /* %fp6 */ + 48 * 4, /* %fp7 */ + 24 * 4, /* %fpcr */ + 25 * 4, /* %fpsr */ + 26 * 4 /* %fpiaddr */ +}; + + +/* Get info about saved registers in sigtramp. */ + +static struct m68k_sigtramp_info +m68k_linux_get_sigtramp_info (struct frame_info *next_frame) +{ + CORE_ADDR sp; + char buf[4]; + struct m68k_sigtramp_info info; + + frame_unwind_register (next_frame, M68K_SP_REGNUM, buf); + sp = extract_unsigned_integer (buf, 4); + + /* Get sigcontext address, it is the third parameter on the stack. */ + info.sigcontext_addr = read_memory_unsigned_integer (sp + 8, 4); + + if (m68k_linux_pc_in_sigtramp (frame_pc_unwind (next_frame), 0) == 2) + info.sc_reg_offset = m68k_linux_ucontext_reg_offset; + else + info.sc_reg_offset = m68k_linux_sigcontext_reg_offset; + return info; +} + +/* Extract from an array REGBUF containing the (raw) register state, a + function return value of TYPE, and copy that, in virtual format, + into VALBUF. */ + +static void +m68k_linux_extract_return_value (struct type *type, struct regcache *regcache, + void *valbuf) +{ + int len = TYPE_LENGTH (type); + char buf[M68K_MAX_REGISTER_SIZE]; + + if (TYPE_CODE (type) == TYPE_CODE_STRUCT + && TYPE_NFIELDS (type) == 1) + { + m68k_linux_extract_return_value (TYPE_FIELD_TYPE (type, 0), regcache, + valbuf); + return; + } + + if (TYPE_CODE (type) == TYPE_CODE_FLT) + { + regcache_raw_read (regcache, M68K_FP0_REGNUM, buf); + convert_typed_floating (buf, builtin_type_m68881_ext, valbuf, type); + } + else if (TYPE_CODE (type) == TYPE_CODE_PTR) + regcache_raw_read (regcache, M68K_A0_REGNUM, valbuf); + else + { + if (len <= 4) + { + regcache_raw_read (regcache, M68K_D0_REGNUM, buf); + memcpy (valbuf, buf + (4 - len), len); + } + else if (len <= 8) + { + regcache_raw_read (regcache, M68K_D0_REGNUM, buf); + memcpy (valbuf, buf + (8 - len), len - 4); + regcache_raw_read (regcache, M68K_D1_REGNUM, + (char *) valbuf + (len - 4)); + } + else + internal_error (__FILE__, __LINE__, + "Cannot extract return value of %d bytes long.", len); + } +} + +/* Write into the appropriate registers a function return value stored + in VALBUF of type TYPE, given in virtual format. */ + +static void +m68k_linux_store_return_value (struct type *type, struct regcache *regcache, + const void *valbuf) +{ + int len = TYPE_LENGTH (type); + + if (TYPE_CODE (type) == TYPE_CODE_STRUCT + && TYPE_NFIELDS (type) == 1) + { + m68k_linux_store_return_value (TYPE_FIELD_TYPE (type, 0), regcache, + valbuf); + return; + } + + if (TYPE_CODE (type) == TYPE_CODE_FLT) + { + char buf[M68K_MAX_REGISTER_SIZE]; + convert_typed_floating (valbuf, type, buf, builtin_type_m68881_ext); + regcache_raw_write (regcache, M68K_FP0_REGNUM, buf); + } + else if (TYPE_CODE (type) == TYPE_CODE_PTR) + regcache_raw_write (regcache, M68K_A0_REGNUM, valbuf); + else + { + if (len <= 4) + regcache_raw_write_part (regcache, M68K_D0_REGNUM, + 4 - len, len, valbuf); + else if (len <= 8) + { + regcache_raw_write_part (regcache, M68K_D1_REGNUM, 8 - len, + len - 4, valbuf); + regcache_raw_write (regcache, M68K_D0_REGNUM, + (char *) valbuf + (len - 4)); + } + else + internal_error (__FILE__, __LINE__, + "Cannot store return value of %d bytes long.", len); + } +} + +/* Extract from an array REGBUF containing the (raw) register state + the address in which a function should return its structure value, + as a CORE_ADDR. */ + +static CORE_ADDR +m68k_linux_extract_struct_value_address (struct regcache *regcache) +{ + char buf[4]; + + regcache_cooked_read (regcache, M68K_A0_REGNUM, buf); + return extract_unsigned_integer (buf, 4); +} + +static void +m68k_linux_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) +{ + struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + + tdep->jb_pc = M68K_LINUX_JB_PC; + tdep->jb_elt_size = M68K_LINUX_JB_ELEMENT_SIZE; + tdep->get_sigtramp_info = m68k_linux_get_sigtramp_info; + tdep->struct_return = reg_struct_return; + + set_gdbarch_extract_return_value (gdbarch, m68k_linux_extract_return_value); + set_gdbarch_store_return_value (gdbarch, m68k_linux_store_return_value); + set_gdbarch_extract_struct_value_address (gdbarch, + m68k_linux_extract_struct_value_address); + + set_gdbarch_pc_in_sigtramp (gdbarch, m68k_linux_pc_in_sigtramp); + + /* Shared library handling. */ + set_gdbarch_in_solib_call_trampoline (gdbarch, in_plt_section); + set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target); +} + +void +_initialize_m68k_linux_tdep (void) +{ + gdbarch_register_osabi (bfd_arch_m68k, 0, GDB_OSABI_LINUX, + m68k_linux_init_abi); +} diff --git a/gdb/mi/mi-cmd-env.c b/gdb/mi/mi-cmd-env.c new file mode 100644 index 0000000..ec0fa35 --- /dev/null +++ b/gdb/mi/mi-cmd-env.c @@ -0,0 +1,260 @@ +/* MI Command Set - environment commands. + + Copyright 2002, 2003 Free Software Foundation, Inc. + + Contributed by Red Hat Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#include "defs.h" +#include "inferior.h" +#include "value.h" +#include "mi-out.h" +#include "mi-cmds.h" +#include "mi-getopt.h" +#include "symtab.h" +#include "target.h" +#include "environ.h" +#include "command.h" +#include "ui-out.h" +#include "top.h" + +#include "gdb_string.h" +#include "gdb_stat.h" + +static void env_cli_command (const char *cli, const char *args); +static void env_mod_path (char *dirname, char **which_path); +extern void _initialize_mi_cmd_env (void); + +static const char path_var_name[] = "PATH"; +static char *orig_path = NULL; + +/* The following is copied from mi-main.c so for m1 and below we can + perform old behavior and use cli commands. If ARGS is non-null, + append it to the CMD. */ +static void +env_execute_cli_command (const char *cmd, const char *args) +{ + if (cmd != 0) + { + struct cleanup *old_cleanups; + char *run; + if (args != NULL) + xasprintf (&run, "%s %s", cmd, args); + else + run = xstrdup (cmd); + old_cleanups = make_cleanup (xfree, run); + execute_command ( /*ui */ run, 0 /*from_tty */ ); + do_cleanups (old_cleanups); + return; + } +} + + +/* Print working directory. */ +enum mi_cmd_result +mi_cmd_env_pwd (char *command, char **argv, int argc) +{ + if (argc > 0) + error ("mi_cmd_env_pwd: No arguments required"); + + if (mi_version (uiout) < 2) + { + env_execute_cli_command ("pwd", NULL); + return MI_CMD_DONE; + } + + /* Otherwise the mi level is 2 or higher. */ + + getcwd (gdb_dirbuf, sizeof (gdb_dirbuf)); + ui_out_field_string (uiout, "cwd", gdb_dirbuf); + + return MI_CMD_DONE; +} + +/* Change working directory. */ +enum mi_cmd_result +mi_cmd_env_cd (char *command, char **argv, int argc) +{ + if (argc == 0 || argc > 1) + error ("mi_cmd_env_cd: Usage DIRECTORY"); + + env_execute_cli_command ("cd", argv[0]); + + return MI_CMD_DONE; +} + +static void +env_mod_path (char *dirname, char **which_path) +{ + if (dirname == 0 || dirname[0] == '\0') + return; + + /* Call add_path with last arg 0 to indicate not to parse for + separator characters. */ + add_path (dirname, which_path, 0); +} + +/* Add one or more directories to start of executable search path. */ +enum mi_cmd_result +mi_cmd_env_path (char *command, char **argv, int argc) +{ + char *exec_path; + char *env; + int reset = 0; + int optind = 0; + int i; + char *optarg; + enum opt + { + RESET_OPT + }; + static struct mi_opt opts[] = + { + {"r", RESET_OPT, 0}, + 0 + }; + + dont_repeat (); + + if (mi_version (uiout) < 2) + { + for (i = argc - 1; i >= 0; --i) + env_execute_cli_command ("path", argv[i]); + return MI_CMD_DONE; + } + + /* Otherwise the mi level is 2 or higher. */ + while (1) + { + int opt = mi_getopt ("mi_cmd_env_path", argc, argv, opts, + &optind, &optarg); + if (opt < 0) + break; + switch ((enum opt) opt) + { + case RESET_OPT: + reset = 1; + break; + } + } + argv += optind; + argc -= optind; + + + if (reset) + { + /* Reset implies resetting to original path first. */ + exec_path = xstrdup (orig_path); + } + else + { + /* Otherwise, get current path to modify. */ + env = get_in_environ (inferior_environ, path_var_name); + + /* Can be null if path is not set. */ + if (!env) + env = ""; + exec_path = xstrdup (env); + } + + for (i = argc - 1; i >= 0; --i) + env_mod_path (argv[i], &exec_path); + + set_in_environ (inferior_environ, path_var_name, exec_path); + xfree (exec_path); + env = get_in_environ (inferior_environ, path_var_name); + ui_out_field_string (uiout, "path", env); + + return MI_CMD_DONE; +} + +/* Add zero or more directories to the front of the source path. */ +enum mi_cmd_result +mi_cmd_env_dir (char *command, char **argv, int argc) +{ + int i; + int optind = 0; + int reset = 0; + char *optarg; + enum opt + { + RESET_OPT + }; + static struct mi_opt opts[] = + { + {"r", RESET_OPT, 0}, + 0 + }; + + dont_repeat (); + + if (mi_version (uiout) < 2) + { + for (i = argc - 1; i >= 0; --i) + env_execute_cli_command ("dir", argv[i]); + return MI_CMD_DONE; + } + + /* Otherwise mi level is 2 or higher. */ + while (1) + { + int opt = mi_getopt ("mi_cmd_env_dir", argc, argv, opts, + &optind, &optarg); + if (opt < 0) + break; + switch ((enum opt) opt) + { + case RESET_OPT: + reset = 1; + break; + } + } + argv += optind; + argc -= optind; + + if (reset) + { + /* Reset means setting to default path first. */ + xfree (source_path); + init_source_path (); + } + + for (i = argc - 1; i >= 0; --i) + env_mod_path (argv[i], &source_path); + init_last_source_visited (); + + ui_out_field_string (uiout, "source-path", source_path); + forget_cached_source_info (); + + return MI_CMD_DONE; +} + +void +_initialize_mi_cmd_env (void) +{ + char *env; + + /* We want original execution path to reset to, if desired later. */ + env = get_in_environ (inferior_environ, path_var_name); + + /* Can be null if path is not set. */ + if (!env) + env = ""; + orig_path = xstrdup (env); +} diff --git a/gdb/mi/mi-cmd-file.c b/gdb/mi/mi-cmd-file.c new file mode 100644 index 0000000..eb1d67a --- /dev/null +++ b/gdb/mi/mi-cmd-file.c @@ -0,0 +1,67 @@ +/* MI Command Set - breakpoint and watchpoint commands. + Copyright 2000, 2001, 2002 Free Software Foundation, Inc. + Contributed by Cygnus Solutions (a Red Hat company). + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#include "defs.h" +#include "mi-cmds.h" +#include "mi-getopt.h" +#include "ui-out.h" +#include "symtab.h" +#include "source.h" + +/* Return to the client the absolute path and line number of the + current file being executed. */ + +enum mi_cmd_result +mi_cmd_file_list_exec_source_file(char *command, char **argv, int argc) +{ + struct symtab_and_line st; + int optind = 0; + char *optarg; + + if ( !mi_valid_noargs("mi_cmd_file_list_exec_source_file", argc, argv) ) + error ("mi_cmd_file_list_exec_source_file: Usage: No args"); + + + /* Set the default file and line, also get them */ + set_default_source_symtab_and_line(); + st = get_current_source_symtab_and_line(); + + /* We should always get a symtab. + Apparently, filename does not need to be tested for NULL. + The documentation in symtab.h suggests it will always be correct */ + if (!st.symtab) + error ("mi_cmd_file_list_exec_source_file: No symtab"); + + /* Extract the fullname if it is not known yet */ + if (st.symtab->fullname == NULL) + symtab_to_filename (st.symtab); + + /* We may not be able to open the file (not available). */ + if (st.symtab->fullname == NULL) + error ("mi_cmd_file_list_exec_source_file: File not found"); + + /* Print to the user the line, filename and fullname */ + ui_out_field_int (uiout, "line", st.line); + ui_out_field_string (uiout, "file", st.symtab->filename); + ui_out_field_string (uiout, "fullname", st.symtab->fullname); + + return MI_CMD_DONE; +} diff --git a/gdb/mi/mi-interp.c b/gdb/mi/mi-interp.c new file mode 100644 index 0000000..b72d7ef --- /dev/null +++ b/gdb/mi/mi-interp.c @@ -0,0 +1,427 @@ +/* MI Interpreter Definitions and Commands for GDB, the GNU debugger. + + Copyright 2002, 2003 Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#include "defs.h" +#include "gdb_string.h" +#include "interps.h" +#include "event-top.h" +#include "event-loop.h" +#include "inferior.h" +#include "ui-out.h" +#include "top.h" + +#include "mi-main.h" +#include "mi-cmds.h" +#include "mi-out.h" +#include "mi-console.h" + +struct mi_interp +{ + /* MI's output channels */ + struct ui_file *out; + struct ui_file *err; + struct ui_file *log; + struct ui_file *targ; + struct ui_file *event_channel; + + /* This is the interpreter for the mi... */ + struct interp *mi2_interp; + struct interp *mi1_interp; + struct interp *mi_interp; +}; + +/* These are the interpreter setup, etc. functions for the MI interpreter */ +static void mi_execute_command_wrapper (char *cmd); +static void mi_command_loop (int mi_version); +static char *mi_input (char *); + +/* These are hooks that we put in place while doing interpreter_exec + so we can report interesting things that happened "behind the mi's + back" in this command */ +static int mi_interp_query_hook (const char *ctlstr, va_list ap); +static char *mi_interp_read_one_line_hook (char *prompt, int repeat, + char *anno); + +static void mi3_command_loop (void); +static void mi2_command_loop (void); +static void mi1_command_loop (void); + +static void mi_insert_notify_hooks (void); +static void mi_remove_notify_hooks (void); + +static void * +mi_interpreter_init (void) +{ + struct mi_interp *mi = XMALLOC (struct mi_interp); + + /* Why is this a part of the mi architecture? */ + + mi_setup_architecture_data (); + + /* HACK: We need to force stdout/stderr to point at the console. This avoids + any potential side effects caused by legacy code that is still + using the TUI / fputs_unfiltered_hook. So we set up output channels for + this now, and swap them in when we are run. */ + + raw_stdout = stdio_fileopen (stdout); + + /* Create MI channels */ + mi->out = mi_console_file_new (raw_stdout, "~", '"'); + mi->err = mi_console_file_new (raw_stdout, "&", '"'); + mi->log = mi->err; + mi->targ = mi_console_file_new (raw_stdout, "@", '"'); + mi->event_channel = mi_console_file_new (raw_stdout, "=", 0); + + return mi; +} + +static int +mi_interpreter_resume (void *data) +{ + struct mi_interp *mi = data; + /* As per hack note in mi_interpreter_init, swap in the output channels... */ + + gdb_setup_readline (); + + if (event_loop_p) + { + /* These overwrite some of the initialization done in + _intialize_event_loop. */ + call_readline = gdb_readline2; + input_handler = mi_execute_command_wrapper; + add_file_handler (input_fd, stdin_event_handler, 0); + async_command_editing_p = 0; + /* FIXME: This is a total hack for now. PB's use of the MI implicitly + relies on a bug in the async support which allows asynchronous + commands to leak through the commmand loop. The bug involves + (but is not limited to) the fact that sync_execution was + erroneously initialized to 0. Duplicate by initializing it + thus here... */ + sync_execution = 0; + } + + gdb_stdout = mi->out; + /* Route error and log output through the MI */ + gdb_stderr = mi->err; + gdb_stdlog = mi->log; + /* Route target output through the MI. */ + gdb_stdtarg = mi->targ; + + /* Replace all the hooks that we know about. There really needs to + be a better way of doing this... */ + clear_interpreter_hooks (); + + show_load_progress = mi_load_progress; + + /* If we're _the_ interpreter, take control. */ + if (current_interp_named_p (INTERP_MI1)) + command_loop_hook = mi1_command_loop; + else if (current_interp_named_p (INTERP_MI2)) + command_loop_hook = mi2_command_loop; + else if (current_interp_named_p (INTERP_MI3)) + command_loop_hook = mi3_command_loop; + else + command_loop_hook = mi2_command_loop; + + return 1; +} + +static int +mi_interpreter_suspend (void *data) +{ + gdb_disable_readline (); + return 1; +} + +static int +mi_interpreter_exec (void *data, const char *command) +{ + char *tmp = alloca (strlen (command) + 1); + strcpy (tmp, command); + mi_execute_command_wrapper (tmp); + return 1; +} + +/* Never display the default gdb prompt in mi case. */ +static int +mi_interpreter_prompt_p (void *data) +{ + return 0; +} + +static void +mi_interpreter_exec_continuation (struct continuation_arg *arg) +{ + bpstat_do_actions (&stop_bpstat); + if (!target_executing) + { + fputs_unfiltered ("*stopped", raw_stdout); + mi_out_put (uiout, raw_stdout); + fputs_unfiltered ("\n", raw_stdout); + fputs_unfiltered ("(gdb) \n", raw_stdout); + gdb_flush (raw_stdout); + do_exec_cleanups (ALL_CLEANUPS); + } + else if (target_can_async_p ()) + { + add_continuation (mi_interpreter_exec_continuation, NULL); + } +} + +enum mi_cmd_result +mi_cmd_interpreter_exec (char *command, char **argv, int argc) +{ + struct interp *interp_to_use; + enum mi_cmd_result result = MI_CMD_DONE; + int i; + struct interp_procs *procs; + + if (argc < 2) + { + xasprintf (&mi_error_message, + "mi_cmd_interpreter_exec: Usage: -interpreter-exec interp command"); + return MI_CMD_ERROR; + } + + interp_to_use = interp_lookup (argv[0]); + if (interp_to_use == NULL) + { + xasprintf (&mi_error_message, + "mi_cmd_interpreter_exec: could not find interpreter \"%s\"", + argv[0]); + return MI_CMD_ERROR; + } + + if (!interp_exec_p (interp_to_use)) + { + xasprintf (&mi_error_message, + "mi_cmd_interpreter_exec: interpreter \"%s\" does not support command execution", + argv[0]); + return MI_CMD_ERROR; + } + + /* Insert the MI out hooks, making sure to also call the interpreter's hooks + if it has any. */ + /* KRS: We shouldn't need this... Events should be installed and they should + just ALWAYS fire something out down the MI channel... */ + mi_insert_notify_hooks (); + + /* Now run the code... */ + + for (i = 1; i < argc; i++) + { + char *buff = NULL; + /* Do this in a cleaner way... We want to force execution to be + asynchronous for commands that run the target. */ + if (target_can_async_p () && (strcmp (argv[0], "console") == 0)) + { + int len = strlen (argv[i]); + buff = xmalloc (len + 2); + memcpy (buff, argv[i], len); + buff[len] = '&'; + buff[len + 1] = '\0'; + } + + /* We had to set sync_execution = 0 for the mi (well really for Project + Builder's use of the mi - particularly so interrupting would work. + But for console commands to work, we need to initialize it to 1 - + since that is what the cli expects - before running the command, + and then set it back to 0 when we are done. */ + sync_execution = 1; + if (interp_exec (interp_to_use, argv[i]) < 0) + { + mi_error_last_message (); + result = MI_CMD_ERROR; + break; + } + xfree (buff); + do_exec_error_cleanups (ALL_CLEANUPS); + sync_execution = 0; + } + + mi_remove_notify_hooks (); + + /* Okay, now let's see if the command set the inferior going... + Tricky point - have to do this AFTER resetting the interpreter, since + changing the interpreter will clear out all the continuations for + that interpreter... */ + + if (target_can_async_p () && target_executing) + { + fputs_unfiltered ("^running\n", raw_stdout); + add_continuation (mi_interpreter_exec_continuation, NULL); + } + + return result; +} + +/* + * mi_insert_notify_hooks - This inserts a number of hooks that are meant to produce + * async-notify ("=") MI messages while running commands in another interpreter + * using mi_interpreter_exec. The canonical use for this is to allow access to + * the gdb CLI interpreter from within the MI, while still producing MI style output + * when actions in the CLI command change gdb's state. +*/ + +static void +mi_insert_notify_hooks (void) +{ + query_hook = mi_interp_query_hook; +} + +static void +mi_remove_notify_hooks (void) +{ + query_hook = NULL; +} + +static int +mi_interp_query_hook (const char *ctlstr, va_list ap) +{ + return 1; +} + +static char * +mi_interp_read_one_line_hook (char *prompt, int repeat, char *anno) +{ + static char buff[256]; + printf_unfiltered ("=read-one-line,prompt=\"%s\"\n", prompt); + gdb_flush (gdb_stdout); + (void) fgets (buff, sizeof (buff), stdin); + buff[(strlen (buff) - 1)] = 0; + return buff; +} + +static void +output_control_change_notification (char *notification) +{ + printf_unfiltered ("^"); + printf_unfiltered ("%s\n", notification); + gdb_flush (gdb_stdout); +} + +static void +mi_execute_command_wrapper (char *cmd) +{ + mi_execute_command (cmd, stdin == instream); +} + +static void +mi1_command_loop (void) +{ + mi_command_loop (1); +} + +static void +mi2_command_loop (void) +{ + mi_command_loop (2); +} + +static void +mi3_command_loop (void) +{ + mi_command_loop (3); +} + +static void +mi_command_loop (int mi_version) +{ +#if 0 + /* HACK: Force stdout/stderr to point at the console. This avoids + any potential side effects caused by legacy code that is still + using the TUI / fputs_unfiltered_hook */ + raw_stdout = stdio_fileopen (stdout); + /* Route normal output through the MIx */ + gdb_stdout = mi_console_file_new (raw_stdout, "~", '"'); + /* Route error and log output through the MI */ + gdb_stderr = mi_console_file_new (raw_stdout, "&", '"'); + gdb_stdlog = gdb_stderr; + /* Route target output through the MI. */ + gdb_stdtarg = mi_console_file_new (raw_stdout, "@", '"'); + /* HACK: Poke the ui_out table directly. Should we be creating a + mi_out object wired up to the above gdb_stdout / gdb_stderr? */ + uiout = mi_out_new (mi_version); + /* HACK: Override any other interpreter hooks. We need to create a + real event table and pass in that. */ + init_ui_hook = 0; + /* command_loop_hook = 0; */ + print_frame_info_listing_hook = 0; + query_hook = 0; + warning_hook = 0; + create_breakpoint_hook = 0; + delete_breakpoint_hook = 0; + modify_breakpoint_hook = 0; + interactive_hook = 0; + registers_changed_hook = 0; + readline_begin_hook = 0; + readline_hook = 0; + readline_end_hook = 0; + register_changed_hook = 0; + memory_changed_hook = 0; + context_hook = 0; + target_wait_hook = 0; + call_command_hook = 0; + error_hook = 0; + error_begin_hook = 0; + show_load_progress = mi_load_progress; +#endif + /* Turn off 8 bit strings in quoted output. Any character with the + high bit set is printed using C's octal format. */ + sevenbit_strings = 1; + /* Tell the world that we're alive */ + fputs_unfiltered ("(gdb) \n", raw_stdout); + gdb_flush (raw_stdout); + if (!event_loop_p) + simplified_command_loop (mi_input, mi_execute_command); + else + start_event_loop (); +} + +static char * +mi_input (char *buf) +{ + return gdb_readline (NULL); +} + +extern initialize_file_ftype _initialize_mi_interp; /* -Wmissing-prototypes */ + +void +_initialize_mi_interp (void) +{ + static const struct interp_procs procs = + { + mi_interpreter_init, /* init_proc */ + mi_interpreter_resume, /* resume_proc */ + mi_interpreter_suspend, /* suspend_proc */ + mi_interpreter_exec, /* exec_proc */ + mi_interpreter_prompt_p /* prompt_proc_p */ + }; + + /* The various interpreter levels. */ + interp_add (interp_new (INTERP_MI1, NULL, mi_out_new (1), &procs)); + interp_add (interp_new (INTERP_MI2, NULL, mi_out_new (2), &procs)); + interp_add (interp_new (INTERP_MI3, NULL, mi_out_new (3), &procs)); + + /* "mi" selects the most recent released version. "mi2" was + released as part of GDB 6.0. */ + interp_add (interp_new (INTERP_MI, NULL, mi_out_new (2), &procs)); +} diff --git a/gdb/mi/mi-main.h b/gdb/mi/mi-main.h new file mode 100644 index 0000000..8e504c6 --- /dev/null +++ b/gdb/mi/mi-main.h @@ -0,0 +1,33 @@ +/* MI Internal Functions for GDB, the GNU debugger. + + Copyright 2003 Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#ifndef MI_MAIN_H +#define MI_MAIN_H + +extern void mi_setup_architecture_data (void); + +extern void mi_load_progress (const char *section_name, + unsigned long sent_so_far, + unsigned long total_section, + unsigned long total_sent, + unsigned long grand_total); +#endif + diff --git a/gdb/mi/mi-symbol-cmds.c b/gdb/mi/mi-symbol-cmds.c new file mode 100644 index 0000000..1d86d21 --- /dev/null +++ b/gdb/mi/mi-symbol-cmds.c @@ -0,0 +1,67 @@ +/* MI Command Set - symbol commands. + Copyright 2003 Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#include "defs.h" +#include "mi-cmds.h" +#include "symtab.h" +#include "ui-out.h" + +/* SYMBOL-LIST-LINES: + + Print the list of all pc addresses and lines of code for + the provided (full or base) source file name. The entries + are sorted in ascending PC order. */ + +enum mi_cmd_result +mi_cmd_symbol_list_lines (char *command, char **argv, int argc) +{ + char *filename; + struct symtab *s; + int i; + struct cleanup *cleanup_stack, *cleanup_tuple; + + if (argc != 1) + error ("mi_cmd_symbol_list_lines: Usage: SOURCE_FILENAME"); + + filename = argv[0]; + s = lookup_symtab (filename); + + if (s == NULL) + error ("mi_cmd_symbol_list_lines: Unknown source file name."); + + /* Now, dump the associated line table. The pc addresses are already + sorted by increasing values in the symbol table, so no need to + perform any other sorting. */ + + cleanup_stack = make_cleanup_ui_out_list_begin_end (uiout, "lines"); + + if (LINETABLE (s) != NULL && LINETABLE (s)->nitems > 0) + for (i = 0; i < LINETABLE (s)->nitems; i++) + { + cleanup_tuple = make_cleanup_ui_out_tuple_begin_end (uiout, NULL); + ui_out_field_core_addr (uiout, "pc", LINETABLE (s)->item[i].pc); + ui_out_field_int (uiout, "line", LINETABLE (s)->item[i].line); + do_cleanups (cleanup_tuple); + } + + do_cleanups (cleanup_stack); + + return MI_CMD_DONE; +} diff --git a/gdb/mips-tdep.h b/gdb/mips-tdep.h new file mode 100644 index 0000000..7a00ffa --- /dev/null +++ b/gdb/mips-tdep.h @@ -0,0 +1,77 @@ +/* Target-dependent header for the MIPS architecture, for GDB, the GNU Debugger. + + Copyright 2002, 2003 Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#ifndef MIPS_TDEP_H +#define MIPS_TDEP_H + +struct gdbarch; + +/* All the possible MIPS ABIs. */ +enum mips_abi + { + MIPS_ABI_UNKNOWN = 0, + MIPS_ABI_N32, + MIPS_ABI_O32, + MIPS_ABI_N64, + MIPS_ABI_O64, + MIPS_ABI_EABI32, + MIPS_ABI_EABI64, + MIPS_ABI_LAST + }; + +/* Return the MIPS ABI associated with GDBARCH. */ +enum mips_abi mips_abi (struct gdbarch *gdbarch); + +/* For wince :-(. */ +extern CORE_ADDR mips_next_pc (CORE_ADDR pc); + +/* Return the "MIPS" register size. Just a short cut to the BFD + architecture's word size. */ +extern int mips_regsize (struct gdbarch *gdbarch); + +/* Return the current index for various MIPS registers. */ +struct mips_regnum +{ + int pc; + int fp0; + int fp_implementation_revision; + int fp_control_status; + int badvaddr; /* Bad vaddr for addressing exception. */ + int cause; /* Describes last exception. */ + int hi; /* Multiply/divide temp. */ + int lo; /* ... */ +}; +extern const struct mips_regnum *mips_regnum (struct gdbarch *gdbarch); + +enum { + MIPS_EMBED_LO_REGNUM = 33, + MIPS_EMBED_HI_REGNUM = 34, + MIPS_EMBED_BADVADDR_REGNUM = 35, + MIPS_EMBED_CAUSE_REGNUM = 36, + MIPS_EMBED_PC_REGNUM = 37, + MIPS_EMBED_FP0_REGNUM = 38 +}; + +/* Defined in mips-tdep.c and used in remote-mips.c */ +extern void deprecated_mips_set_processor_regs_hack (void); + + +#endif /* MIPS_TDEP_H */ diff --git a/gdb/nto-procfs.c b/gdb/nto-procfs.c new file mode 100644 index 0000000..00b4096 --- /dev/null +++ b/gdb/nto-procfs.c @@ -0,0 +1,1389 @@ +/* Machine independent support for QNX Neutrino /proc (process file system) + for GDB. Written by Colin Burgess at QNX Software Systems Limited. + + Copyright 2003 Free Software Foundation, Inc. + + Contributed by QNX Software Systems Ltd. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#include "defs.h" + +#include +#include +#include +#include +#include +#include +#include "gdb_dirent.h" +#include + +#include "gdb_string.h" +#include "gdbcore.h" +#include "inferior.h" +#include "target.h" +#include "objfiles.h" +#include "gdbthread.h" +#include "nto-tdep.h" +#include "command.h" +#include "regcache.h" + +#define NULL_PID 0 +#define _DEBUG_FLAG_TRACE (_DEBUG_FLAG_TRACE_EXEC|_DEBUG_FLAG_TRACE_RD|\ + _DEBUG_FLAG_TRACE_WR|_DEBUG_FLAG_TRACE_MODIFY) + +static struct target_ops procfs_ops; + +int ctl_fd; + +static void (*ofunc) (); + +static procfs_run run; + +static void procfs_open (char *, int); + +static int procfs_can_run (void); + +static ptid_t procfs_wait (ptid_t, struct target_waitstatus *); + +static int procfs_xfer_memory (CORE_ADDR, char *, int, int, + struct mem_attrib *attrib, + struct target_ops *); + +static void procfs_fetch_registers (int); + +static void notice_signals (void); + +static void init_procfs_ops (void); + +static ptid_t do_attach (ptid_t ptid); + +static int procfs_can_use_hw_breakpoint (int, int, int); + +static int procfs_insert_hw_breakpoint (CORE_ADDR, char *); + +static int procfs_remove_hw_breakpoint (CORE_ADDR addr, char *); + +static int procfs_insert_hw_watchpoint (CORE_ADDR addr, int len, int type); + +static int procfs_remove_hw_watchpoint (CORE_ADDR addr, int len, int type); + +static int procfs_stopped_by_watchpoint (void); + +/* These two globals are only ever set in procfs_open(), but are + referenced elsewhere. 'nto_procfs_node' is a flag used to say + whether we are local, or we should get the current node descriptor + for the remote QNX node. */ +static char nto_procfs_path[PATH_MAX] = { "/proc" }; +static unsigned nto_procfs_node = ND_LOCAL_NODE; + +/* Return the current QNX Node, or error out. This is a simple + wrapper for the netmgr_strtond() function. The reason this + is required is because QNX node descriptors are transient so + we have to re-acquire them every time. */ +static unsigned +nto_node(void) +{ + unsigned node; + + if (ND_NODE_CMP(nto_procfs_node, ND_LOCAL_NODE) == 0) + return ND_LOCAL_NODE; + + node = netmgr_strtond(nto_procfs_path,0); + if (node == -1) + error ("Lost the QNX node. Debug session probably over."); + + return (node); +} + +/* This is called when we call 'target procfs ' from the (gdb) prompt. + For QNX6 (nto), the only valid arg will be a QNX node string, + eg: "/net/some_node". If arg is not a valid QNX node, we will + default to local. */ +static void +procfs_open (char *arg, int from_tty) +{ + char *nodestr; + char *endstr; + char buffer[50]; + int fd, total_size; + procfs_sysinfo *sysinfo; + + /* Set the default node used for spawning to this one, + and only override it if there is a valid arg. */ + + nto_procfs_node = ND_LOCAL_NODE; + nodestr = arg ? xstrdup (arg) : arg; + + init_thread_list (); + + if (nodestr) + { + nto_procfs_node = netmgr_strtond (nodestr, &endstr); + if (nto_procfs_node == -1) + { + if (errno == ENOTSUP) + printf_filtered ("QNX Net Manager not found.\n"); + printf_filtered ("Invalid QNX node %s: error %d (%s).\n", nodestr, + errno, safe_strerror (errno)); + xfree (nodestr); + nodestr = NULL; + nto_procfs_node = ND_LOCAL_NODE; + } + else if (*endstr) + { + if (*(endstr - 1) == '/') + *(endstr - 1) = 0; + else + *endstr = 0; + } + } + snprintf (nto_procfs_path, PATH_MAX - 1, "%s%s", nodestr ? nodestr : "", "/proc"); + if (nodestr) + xfree (nodestr); + + fd = open (nto_procfs_path, O_RDONLY); + if (fd == -1) + { + printf_filtered ("Error opening %s : %d (%s)\n", nto_procfs_path, errno, + safe_strerror (errno)); + error ("Invalid procfs arg"); + } + + sysinfo = (void *) buffer; + if (devctl (fd, DCMD_PROC_SYSINFO, sysinfo, sizeof buffer, 0) != EOK) + { + printf_filtered ("Error getting size: %d (%s)\n", errno, + safe_strerror (errno)); + close (fd); + error ("Devctl failed."); + } + else + { + total_size = sysinfo->total_size; + sysinfo = alloca (total_size); + if (!sysinfo) + { + printf_filtered ("Memory error: %d (%s)\n", errno, + safe_strerror (errno)); + close (fd); + error ("alloca failed."); + } + else + { + if (devctl (fd, DCMD_PROC_SYSINFO, sysinfo, total_size, 0) != EOK) + { + printf_filtered ("Error getting sysinfo: %d (%s)\n", errno, + safe_strerror (errno)); + close (fd); + error ("Devctl failed."); + } + else + { + if (sysinfo->type != + nto_map_arch_to_cputype (TARGET_ARCHITECTURE->arch_name)) + { + close (fd); + error ("Invalid target CPU."); + } + } + } + } + close (fd); + printf_filtered ("Debugging using %s\n", nto_procfs_path); +} + +static void +procfs_set_thread (ptid_t ptid) +{ + pid_t tid; + + tid = ptid_get_tid (ptid); + devctl (ctl_fd, DCMD_PROC_CURTHREAD, &tid, sizeof (tid), 0); +} + +/* Return nonzero if the thread TH is still alive. */ +static int +procfs_thread_alive (ptid_t ptid) +{ + pid_t tid; + + tid = ptid_get_tid (ptid); + if (devctl (ctl_fd, DCMD_PROC_CURTHREAD, &tid, sizeof (tid), 0) == EOK) + return 1; + return 0; +} + +void +procfs_find_new_threads (void) +{ + procfs_status status; + pid_t pid; + ptid_t ptid; + + if (ctl_fd == -1) + return; + + pid = ptid_get_pid (inferior_ptid); + + for (status.tid = 1;; ++status.tid) + { + if (devctl (ctl_fd, DCMD_PROC_TIDSTATUS, &status, sizeof (status), 0) + != EOK && status.tid != 0) + break; + ptid = ptid_build (pid, 0, status.tid); + if (!in_thread_list (ptid)) + add_thread (ptid); + } + return; +} + +void +procfs_pidlist (char *args, int from_tty) +{ + DIR *dp = NULL; + struct dirent *dirp = NULL; + int fd = -1; + char buf[512]; + procfs_info *pidinfo = NULL; + procfs_debuginfo *info = NULL; + procfs_status *status = NULL; + pid_t num_threads = 0; + pid_t pid; + char name[512]; + + dp = opendir (nto_procfs_path); + if (dp == NULL) + { + fprintf_unfiltered (gdb_stderr, "failed to opendir \"%s\" - %d (%s)", + nto_procfs_path, errno, safe_strerror (errno)); + return; + } + + /* Start scan at first pid. */ + rewinddir (dp); + + do + { + /* Get the right pid and procfs path for the pid. */ + do + { + dirp = readdir (dp); + if (dirp == NULL) + { + closedir (dp); + return; + } + snprintf (buf, 511, "%s/%s/as", nto_procfs_path, dirp->d_name); + pid = atoi (dirp->d_name); + } + while (pid == 0); + + /* Open the procfs path. */ + fd = open (buf, O_RDONLY); + if (fd == -1) + { + fprintf_unfiltered (gdb_stderr, "failed to open %s - %d (%s)\n", + buf, errno, safe_strerror (errno)); + closedir (dp); + return; + } + + pidinfo = (procfs_info *) buf; + if (devctl (fd, DCMD_PROC_INFO, pidinfo, sizeof (buf), 0) != EOK) + { + fprintf_unfiltered (gdb_stderr, + "devctl DCMD_PROC_INFO failed - %d (%s)\n", errno, + safe_strerror (errno)); + break; + } + num_threads = pidinfo->num_threads; + + info = (procfs_debuginfo *) buf; + if (devctl (fd, DCMD_PROC_MAPDEBUG_BASE, info, sizeof (buf), 0) != EOK) + strcpy (name, "unavailable"); + else + strcpy (name, info->path); + + /* Collect state info on all the threads. */ + status = (procfs_status *) buf; + for (status->tid = 1; status->tid <= num_threads; status->tid++) + { + if (devctl (fd, DCMD_PROC_TIDSTATUS, status, sizeof (buf), 0) != EOK + && status->tid != 0) + break; + if (status->tid != 0) + printf_filtered ("%s - %d/%d\n", name, pid, status->tid); + } + close (fd); + } + while (dirp != NULL); + + close (fd); + closedir (dp); + return; +} + +void +procfs_meminfo (char *args, int from_tty) +{ + procfs_mapinfo *mapinfos = NULL; + static int num_mapinfos = 0; + procfs_mapinfo *mapinfo_p, *mapinfo_p2; + int flags = ~0, err, num, i, j; + + struct + { + procfs_debuginfo info; + char buff[_POSIX_PATH_MAX]; + } map; + + struct info + { + unsigned addr; + unsigned size; + unsigned flags; + unsigned debug_vaddr; + unsigned long long offset; + }; + + struct printinfo + { + unsigned long long ino; + unsigned dev; + struct info text; + struct info data; + char name[256]; + } printme; + + /* Get the number of map entrys. */ + err = devctl (ctl_fd, DCMD_PROC_MAPINFO, NULL, 0, &num); + if (err != EOK) + { + printf ("failed devctl num mapinfos - %d (%s)\n", err, safe_strerror (err)); + return; + } + + mapinfos = xmalloc (num * sizeof (procfs_mapinfo)); + + num_mapinfos = num; + mapinfo_p = mapinfos; + + /* Fill the map entrys. */ + err = devctl (ctl_fd, DCMD_PROC_MAPINFO, mapinfo_p, num + * sizeof (procfs_mapinfo), &num); + if (err != EOK) + { + printf ("failed devctl mapinfos - %d (%s)\n", err, safe_strerror (err)); + xfree (mapinfos); + return; + } + + num = min (num, num_mapinfos); + + /* Run through the list of mapinfos, and store the data and text info + so we can print it at the bottom of the loop. */ + for (mapinfo_p = mapinfos, i = 0; i < num; i++, mapinfo_p++) + { + if (!(mapinfo_p->flags & flags)) + mapinfo_p->ino = 0; + + if (mapinfo_p->ino == 0) /* Already visited. */ + continue; + + map.info.vaddr = mapinfo_p->vaddr; + + err = devctl (ctl_fd, DCMD_PROC_MAPDEBUG, &map, sizeof (map), 0); + if (err != EOK) + continue; + + memset (&printme, 0, sizeof printme); + printme.dev = mapinfo_p->dev; + printme.ino = mapinfo_p->ino; + printme.text.addr = mapinfo_p->vaddr; + printme.text.size = mapinfo_p->size; + printme.text.flags = mapinfo_p->flags; + printme.text.offset = mapinfo_p->offset; + printme.text.debug_vaddr = map.info.vaddr; + strcpy (printme.name, map.info.path); + + /* Check for matching data. */ + for (mapinfo_p2 = mapinfos, j = 0; j < num; j++, mapinfo_p2++) + { + if (mapinfo_p2->vaddr != mapinfo_p->vaddr + && mapinfo_p2->ino == mapinfo_p->ino + && mapinfo_p2->dev == mapinfo_p->dev) + { + map.info.vaddr = mapinfo_p2->vaddr; + err = + devctl (ctl_fd, DCMD_PROC_MAPDEBUG, &map, sizeof (map), 0); + if (err != EOK) + continue; + + if (strcmp (map.info.path, printme.name)) + continue; + + /* Lower debug_vaddr is always text, if nessessary, swap. */ + if ((int) map.info.vaddr < (int) printme.text.debug_vaddr) + { + memcpy (&(printme.data), &(printme.text), + sizeof (printme.data)); + printme.text.addr = mapinfo_p2->vaddr; + printme.text.size = mapinfo_p2->size; + printme.text.flags = mapinfo_p2->flags; + printme.text.offset = mapinfo_p2->offset; + printme.text.debug_vaddr = map.info.vaddr; + } + else + { + printme.data.addr = mapinfo_p2->vaddr; + printme.data.size = mapinfo_p2->size; + printme.data.flags = mapinfo_p2->flags; + printme.data.offset = mapinfo_p2->offset; + printme.data.debug_vaddr = map.info.vaddr; + } + mapinfo_p2->ino = 0; + } + } + mapinfo_p->ino = 0; + + printf_filtered ("%s\n", printme.name); + printf_filtered ("\ttext=%08x bytes @ 0x%08x\n", printme.text.size, + printme.text.addr); + printf_filtered ("\t\tflags=%08x\n", printme.text.flags); + printf_filtered ("\t\tdebug=%08x\n", printme.text.debug_vaddr); + printf_filtered ("\t\toffset=%016llx\n", printme.text.offset); + if (printme.data.size) + { + printf_filtered ("\tdata=%08x bytes @ 0x%08x\n", printme.data.size, + printme.data.addr); + printf_filtered ("\t\tflags=%08x\n", printme.data.flags); + printf_filtered ("\t\tdebug=%08x\n", printme.data.debug_vaddr); + printf_filtered ("\t\toffset=%016llx\n", printme.data.offset); + } + printf_filtered ("\tdev=0x%x\n", printme.dev); + printf_filtered ("\tino=0x%x\n", (unsigned int) printme.ino); + } + xfree (mapinfos); + return; +} + +/* Print status information about what we're accessing. */ +static void +procfs_files_info (struct target_ops *ignore) +{ + printf_unfiltered ("\tUsing the running image of %s %s via %s.\n", + attach_flag ? "attached" : "child", + target_pid_to_str (inferior_ptid), nto_procfs_path); +} + +/* Mark our target-struct as eligible for stray "run" and "attach" commands. */ +static int +procfs_can_run (void) +{ + return 1; +} + +/* Attach to process PID, then initialize for debugging it. */ +static void +procfs_attach (char *args, int from_tty) +{ + char *exec_file; + int pid; + + if (!args) + error_no_arg ("process-id to attach"); + + pid = atoi (args); + + if (pid == getpid ()) + error ("Attaching GDB to itself is not a good idea..."); + + if (from_tty) + { + exec_file = (char *) get_exec_file (0); + + if (exec_file) + printf_unfiltered ("Attaching to program `%s', %s\n", exec_file, + target_pid_to_str (pid_to_ptid (pid))); + else + printf_unfiltered ("Attaching to %s\n", + target_pid_to_str (pid_to_ptid (pid))); + + gdb_flush (gdb_stdout); + } + inferior_ptid = do_attach (pid_to_ptid (pid)); + push_target (&procfs_ops); +} + +static void +procfs_post_attach (pid_t pid) +{ +#ifdef SOLIB_CREATE_INFERIOR_HOOK + if (exec_bfd) + SOLIB_CREATE_INFERIOR_HOOK (pid); +#endif +} + +static ptid_t +do_attach (ptid_t ptid) +{ + procfs_status status; + struct sigevent event; + char path[PATH_MAX]; + + snprintf (path, PATH_MAX - 1, "%s/%d/as", nto_procfs_path, PIDGET (ptid)); + ctl_fd = open (path, O_RDWR); + if (ctl_fd == -1) + error ("Couldn't open proc file %s, error %d (%s)", path, errno, + safe_strerror (errno)); + if (devctl (ctl_fd, DCMD_PROC_STOP, &status, sizeof (status), 0) != EOK) + error ("Couldn't stop process"); + + /* Define a sigevent for process stopped notification. */ + event.sigev_notify = SIGEV_SIGNAL_THREAD; + event.sigev_signo = SIGUSR1; + event.sigev_code = 0; + event.sigev_value.sival_ptr = NULL; + event.sigev_priority = -1; + devctl (ctl_fd, DCMD_PROC_EVENT, &event, sizeof (event), 0); + + if (devctl (ctl_fd, DCMD_PROC_STATUS, &status, sizeof (status), 0) == EOK + && status.flags & _DEBUG_FLAG_STOPPED) + SignalKill (nto_node(), PIDGET (ptid), 0, SIGCONT, 0, 0); + attach_flag = 1; + nto_init_solib_absolute_prefix (); + return ptid; +} + +/* Ask the user what to do when an interrupt is received. */ +static void +interrupt_query (void) +{ + target_terminal_ours (); + + if (query ("Interrupted while waiting for the program.\n\ +Give up (and stop debugging it)? ")) + { + target_mourn_inferior (); + throw_exception (RETURN_QUIT); + } + + target_terminal_inferior (); +} + +/* The user typed ^C twice. */ +static void +nto_interrupt_twice (int signo) +{ + signal (signo, ofunc); + interrupt_query (); + signal (signo, nto_interrupt_twice); +} + +static void +nto_interrupt (int signo) +{ + /* If this doesn't work, try more severe steps. */ + signal (signo, nto_interrupt_twice); + + target_stop (); +} + +static ptid_t +procfs_wait (ptid_t ptid, struct target_waitstatus *ourstatus) +{ + sigset_t set; + siginfo_t info; + procfs_status status; + static int exit_signo = 0; /* To track signals that cause termination. */ + + ourstatus->kind = TARGET_WAITKIND_SPURIOUS; + + if (ptid_equal (inferior_ptid, null_ptid)) + { + ourstatus->kind = TARGET_WAITKIND_STOPPED; + ourstatus->value.sig = TARGET_SIGNAL_0; + exit_signo = 0; + return null_ptid; + } + + sigemptyset (&set); + sigaddset (&set, SIGUSR1); + + devctl (ctl_fd, DCMD_PROC_STATUS, &status, sizeof (status), 0); + while (!(status.flags & _DEBUG_FLAG_ISTOP)) + { + ofunc = (void (*)()) signal (SIGINT, nto_interrupt); + sigwaitinfo (&set, &info); + signal (SIGINT, ofunc); + devctl (ctl_fd, DCMD_PROC_STATUS, &status, sizeof (status), 0); + } + + if (status.flags & _DEBUG_FLAG_SSTEP) + { + ourstatus->kind = TARGET_WAITKIND_STOPPED; + ourstatus->value.sig = TARGET_SIGNAL_TRAP; + } + /* Was it a breakpoint? */ + else if (status.flags & _DEBUG_FLAG_TRACE) + { + ourstatus->kind = TARGET_WAITKIND_STOPPED; + ourstatus->value.sig = TARGET_SIGNAL_TRAP; + } + else if (status.flags & _DEBUG_FLAG_ISTOP) + { + switch (status.why) + { + case _DEBUG_WHY_SIGNALLED: + ourstatus->kind = TARGET_WAITKIND_STOPPED; + ourstatus->value.sig = + target_signal_from_host (status.info.si_signo); + exit_signo = 0; + break; + case _DEBUG_WHY_FAULTED: + ourstatus->kind = TARGET_WAITKIND_STOPPED; + if (status.info.si_signo == SIGTRAP) + { + ourstatus->value.sig = 0; + exit_signo = 0; + } + else + { + ourstatus->value.sig = + target_signal_from_host (status.info.si_signo); + exit_signo = ourstatus->value.sig; + } + break; + + case _DEBUG_WHY_TERMINATED: + { + int waitval = 0; + + waitpid (PIDGET (inferior_ptid), &waitval, WNOHANG); + if (exit_signo) + { + /* Abnormal death. */ + ourstatus->kind = TARGET_WAITKIND_SIGNALLED; + ourstatus->value.sig = exit_signo; + } + else + { + /* Normal death. */ + ourstatus->kind = TARGET_WAITKIND_EXITED; + ourstatus->value.integer = WEXITSTATUS (waitval); + } + exit_signo = 0; + break; + } + + case _DEBUG_WHY_REQUESTED: + /* We are assuming a requested stop is due to a SIGINT. */ + ourstatus->kind = TARGET_WAITKIND_STOPPED; + ourstatus->value.sig = TARGET_SIGNAL_INT; + exit_signo = 0; + break; + } + } + + return inferior_ptid; +} + +/* Read the current values of the inferior's registers, both the + general register set and floating point registers (if supported) + and update gdb's idea of their current values. */ +static void +procfs_fetch_registers (int regno) +{ + union + { + procfs_greg greg; + procfs_fpreg fpreg; + procfs_altreg altreg; + } + reg; + int regsize; + + procfs_set_thread (inferior_ptid); + if (devctl (ctl_fd, DCMD_PROC_GETGREG, ®, sizeof (reg), ®size) == EOK) + nto_supply_gregset ((char *) ®.greg); + if (devctl (ctl_fd, DCMD_PROC_GETFPREG, ®, sizeof (reg), ®size) + == EOK) + nto_supply_fpregset ((char *) ®.fpreg); + if (devctl (ctl_fd, DCMD_PROC_GETALTREG, ®, sizeof (reg), ®size) + == EOK) + nto_supply_altregset ((char *) ®.altreg); +} + +/* Copy LEN bytes to/from inferior's memory starting at MEMADDR + from/to debugger memory starting at MYADDR. Copy from inferior + if DOWRITE is zero or to inferior if DOWRITE is nonzero. + + Returns the length copied, which is either the LEN argument or + zero. This xfer function does not do partial moves, since procfs_ops + doesn't allow memory operations to cross below us in the target stack + anyway. */ +static int +procfs_xfer_memory (CORE_ADDR memaddr, char *myaddr, int len, int dowrite, + struct mem_attrib *attrib, struct target_ops *target) +{ + int nbytes = 0; + + if (lseek (ctl_fd, (off_t) memaddr, SEEK_SET) == (off_t) memaddr) + { + if (dowrite) + nbytes = write (ctl_fd, myaddr, len); + else + nbytes = read (ctl_fd, myaddr, len); + if (nbytes < 0) + nbytes = 0; + } + return (nbytes); +} + +/* Take a program previously attached to and detaches it. + The program resumes execution and will no longer stop + on signals, etc. We'd better not have left any breakpoints + in the program or it'll die when it hits one. */ +static void +procfs_detach (char *args, int from_tty) +{ + int siggnal = 0; + + if (from_tty) + { + char *exec_file = get_exec_file (0); + if (exec_file == 0) + exec_file = ""; + printf_unfiltered ("Detaching from program: %s %s\n", + exec_file, target_pid_to_str (inferior_ptid)); + gdb_flush (gdb_stdout); + } + if (args) + siggnal = atoi (args); + + if (siggnal) + SignalKill (nto_node(), PIDGET (inferior_ptid), 0, siggnal, 0, 0); + + close (ctl_fd); + ctl_fd = -1; + init_thread_list (); + inferior_ptid = null_ptid; + attach_flag = 0; + unpush_target (&procfs_ops); /* Pop out of handling an inferior. */ +} + +static int +procfs_breakpoint (CORE_ADDR addr, int type, int size) +{ + procfs_break brk; + + brk.type = type; + brk.addr = addr; + brk.size = size; + errno = devctl (ctl_fd, DCMD_PROC_BREAK, &brk, sizeof (brk), 0); + if (errno != EOK) + return 1; + return 0; +} + +static int +procfs_insert_breakpoint (CORE_ADDR addr, char *contents_cache) +{ + return procfs_breakpoint (addr, _DEBUG_BREAK_EXEC, 0); +} + +static int +procfs_remove_breakpoint (CORE_ADDR addr, char *contents_cache) +{ + return procfs_breakpoint (addr, _DEBUG_BREAK_EXEC, -1); +} + +static int +procfs_insert_hw_breakpoint (CORE_ADDR addr, char *contents_cache) +{ + return procfs_breakpoint (addr, _DEBUG_BREAK_EXEC | _DEBUG_BREAK_HW, 0); +} + +static int +procfs_remove_hw_breakpoint (CORE_ADDR addr, char *contents_cache) +{ + return procfs_breakpoint (addr, _DEBUG_BREAK_EXEC | _DEBUG_BREAK_HW, -1); +} + +static void +procfs_resume (ptid_t ptid, int step, enum target_signal signo) +{ + int signal_to_pass; + procfs_status status; + + if (ptid_equal (inferior_ptid, null_ptid)) + return; + + procfs_set_thread (ptid_equal (ptid, minus_one_ptid) ? inferior_ptid : + ptid); + + run.flags = _DEBUG_RUN_FAULT | _DEBUG_RUN_TRACE; + if (step) + run.flags |= _DEBUG_RUN_STEP; + + sigemptyset ((sigset_t *) &run.fault); + sigaddset ((sigset_t *) &run.fault, FLTBPT); + sigaddset ((sigset_t *) &run.fault, FLTTRACE); + sigaddset ((sigset_t *) &run.fault, FLTILL); + sigaddset ((sigset_t *) &run.fault, FLTPRIV); + sigaddset ((sigset_t *) &run.fault, FLTBOUNDS); + sigaddset ((sigset_t *) &run.fault, FLTIOVF); + sigaddset ((sigset_t *) &run.fault, FLTIZDIV); + sigaddset ((sigset_t *) &run.fault, FLTFPE); + /* Peter V will be changing this at some point. */ + sigaddset ((sigset_t *) &run.fault, FLTPAGE); + + run.flags |= _DEBUG_RUN_ARM; + + sigemptyset (&run.trace); + notice_signals (); + signal_to_pass = target_signal_to_host (signo); + + if (signal_to_pass) + { + devctl (ctl_fd, DCMD_PROC_STATUS, &status, sizeof (status), 0); + signal_to_pass = target_signal_to_host (signo); + if (status.why & (_DEBUG_WHY_SIGNALLED | _DEBUG_WHY_FAULTED)) + { + if (signal_to_pass != status.info.si_signo) + { + SignalKill (nto_node(), PIDGET (inferior_ptid), 0, signal_to_pass, + 0, 0); + run.flags |= _DEBUG_RUN_CLRFLT | _DEBUG_RUN_CLRSIG; + } + else /* Let it kill the program without telling us. */ + sigdelset (&run.trace, signal_to_pass); + } + } + else + run.flags |= _DEBUG_RUN_CLRSIG | _DEBUG_RUN_CLRFLT; + + errno = devctl (ctl_fd, DCMD_PROC_RUN, &run, sizeof (run), 0); + if (errno != EOK) + { + perror ("run error!\n"); + return; + } +} + +static void +procfs_mourn_inferior (void) +{ + if (!ptid_equal (inferior_ptid, null_ptid)) + { + SignalKill (nto_node(), PIDGET (inferior_ptid), 0, SIGKILL, 0, 0); + close (ctl_fd); + } + inferior_ptid = null_ptid; + init_thread_list (); + unpush_target (&procfs_ops); + generic_mourn_inferior (); + attach_flag = 0; +} + +/* This function breaks up an argument string into an argument + vector suitable for passing to execvp(). + E.g., on "run a b c d" this routine would get as input + the string "a b c d", and as output it would fill in argv with + the four arguments "a", "b", "c", "d". The only additional + functionality is simple quoting. The gdb command: + run a "b c d" f + will fill in argv with the three args "a", "b c d", "e". */ +static void +breakup_args (char *scratch, char **argv) +{ + char *pp, *cp = scratch; + char quoting = 0; + + for (;;) + { + /* Scan past leading separators. */ + quoting = 0; + while (*cp == ' ' || *cp == '\t' || *cp == '\n') + cp++; + + /* Break if at end of string. */ + if (*cp == '\0') + break; + + /* Take an arg. */ + if (*cp == '"') + { + cp++; + quoting = strchr (cp, '"') ? 1 : 0; + } + + *argv++ = cp; + + /* Scan for next arg separator. */ + pp = cp; + if (quoting) + cp = strchr (pp, '"'); + if ((cp == NULL) || (!quoting)) + cp = strchr (pp, ' '); + if (cp == NULL) + cp = strchr (pp, '\t'); + if (cp == NULL) + cp = strchr (pp, '\n'); + + /* No separators => end of string => break. */ + if (cp == NULL) + { + pp = cp; + break; + } + + /* Replace the separator with a terminator. */ + *cp++ = '\0'; + } + + /* Execv requires a null-terminated arg vector. */ + *argv = NULL; +} + +static void +procfs_create_inferior (char *exec_file, char *allargs, char **env) +{ + struct inheritance inherit; + pid_t pid; + int flags, errn; + char **argv, *args; + char *in = "", *out = "", *err = ""; + int fd, fds[3]; + sigset_t set; + + argv = xmalloc (((strlen (allargs) + 1) / (unsigned) 2 + 2) * + sizeof (*argv)); + argv[0] = get_exec_file (1); + if (!argv[0]) + { + if (exec_file) + argv[0] = exec_file; + else + return; + } + + args = xstrdup (allargs); + breakup_args (args, exec_file ? &argv[1] : &argv[0]); + + argv = nto_parse_redirection (argv, &in, &out, &err); + + fds[0] = STDIN_FILENO; + fds[1] = STDOUT_FILENO; + fds[2] = STDERR_FILENO; + + /* If the user specified I/O via gdb's --tty= arg, use it, but only + if the i/o is not also being specified via redirection. */ + if (inferior_io_terminal) + { + if (!in[0]) + in = inferior_io_terminal; + if (!out[0]) + out = inferior_io_terminal; + if (!err[0]) + err = inferior_io_terminal; + } + + if (in[0]) + { + fd = open (in, O_RDONLY); + if (fd == -1) + perror (in); + else + fds[0] = fd; + } + if (out[0]) + { + fd = open (out, O_WRONLY); + if (fd == -1) + perror (out); + else + fds[1] = fd; + } + if (err[0]) + { + fd = open (err, O_WRONLY); + if (fd == -1) + perror (err); + else + fds[2] = fd; + } + + /* Clear any pending SIGUSR1's but keep the behavior the same. */ + signal (SIGUSR1, signal (SIGUSR1, SIG_IGN)); + + sigemptyset (&set); + sigaddset (&set, SIGUSR1); + sigprocmask (SIG_UNBLOCK, &set, NULL); + + memset (&inherit, 0, sizeof (inherit)); + + if (ND_NODE_CMP (nto_procfs_node, ND_LOCAL_NODE) != 0) + { + inherit.nd = nto_node(); + inherit.flags |= SPAWN_SETND; + inherit.flags &= ~SPAWN_EXEC; + } + inherit.flags |= SPAWN_SETGROUP | SPAWN_HOLD; + inherit.pgroup = SPAWN_NEWPGROUP; + pid = spawnp (argv[0], 3, fds, &inherit, argv, + ND_NODE_CMP (nto_procfs_node, ND_LOCAL_NODE) == 0 ? env : 0); + xfree (args); + + sigprocmask (SIG_BLOCK, &set, NULL); + + if (pid == -1) + error ("Error spawning %s: %d (%s)", argv[0], errno, safe_strerror (errno)); + + if (fds[0] != STDIN_FILENO) + close (fds[0]); + if (fds[1] != STDOUT_FILENO) + close (fds[1]); + if (fds[2] != STDERR_FILENO) + close (fds[2]); + + inferior_ptid = do_attach (pid_to_ptid (pid)); + + attach_flag = 0; + flags = _DEBUG_FLAG_KLC; /* Kill-on-Last-Close flag. */ + errn = devctl (ctl_fd, DCMD_PROC_SET_FLAG, &flags, sizeof (flags), 0); + if (errn != EOK) + { + /* FIXME: expected warning? */ + /* warning( "Failed to set Kill-on-Last-Close flag: errno = %d(%s)\n", + errn, strerror(errn) ); */ + } + push_target (&procfs_ops); + target_terminal_init (); + +#ifdef SOLIB_CREATE_INFERIOR_HOOK + if (exec_bfd != NULL + || (symfile_objfile != NULL && symfile_objfile->obfd != NULL)) + SOLIB_CREATE_INFERIOR_HOOK (pid); +#endif +} + +static void +procfs_stop (void) +{ + devctl (ctl_fd, DCMD_PROC_STOP, NULL, 0, 0); +} + +static void +procfs_kill_inferior (void) +{ + target_mourn_inferior (); +} + +/* Store register REGNO, or all registers if REGNO == -1, from the contents + of REGISTERS. */ +static void +procfs_prepare_to_store (void) +{ +} + +/* Fill buf with regset and return devctl cmd to do the setting. Return + -1 if we fail to get the regset. Store size of regset in regsize. */ +static int +get_regset (int regset, char *buf, int bufsize, int *regsize) +{ + int dev_get, dev_set; + switch (regset) + { + case NTO_REG_GENERAL: + dev_get = DCMD_PROC_GETGREG; + dev_set = DCMD_PROC_SETGREG; + break; + + case NTO_REG_FLOAT: + dev_get = DCMD_PROC_GETFPREG; + dev_set = DCMD_PROC_SETFPREG; + break; + + case NTO_REG_ALT: + dev_get = DCMD_PROC_GETALTREG; + dev_set = DCMD_PROC_SETALTREG; + break; + + case NTO_REG_SYSTEM: + default: + return -1; + } + if (devctl (ctl_fd, dev_get, &buf, bufsize, regsize) != EOK) + return -1; + + return dev_set; +} + +void +procfs_store_registers (int regno) +{ + union + { + procfs_greg greg; + procfs_fpreg fpreg; + procfs_altreg altreg; + } + reg; + unsigned off; + int len, regset, regsize, dev_set, err; + char *data; + + if (ptid_equal (inferior_ptid, null_ptid)) + return; + procfs_set_thread (inferior_ptid); + + if (regno == -1) + { + for (regset = NTO_REG_GENERAL; regset < NTO_REG_END; regset++) + { + dev_set = get_regset (regset, (char *) ®, + sizeof (reg), ®size); + if (dev_set == -1) + continue; + + if (nto_regset_fill (regset, (char *) ®) == -1) + continue; + + err = devctl (ctl_fd, dev_set, ®, regsize, 0); + if (err != EOK) + fprintf_unfiltered (gdb_stderr, + "Warning unable to write regset %d: %s\n", + regno, safe_strerror (err)); + } + } + else + { + regset = nto_regset_id (regno); + if (regset == -1) + return; + + dev_set = get_regset (regset, (char *) ®, sizeof (reg), ®size); + if (dev_set == -1) + return; + + len = nto_register_area (regno, regset, &off); + + if (len < 1) + return; + + regcache_collect (regno, (char *) ® + off); + + err = devctl (ctl_fd, dev_set, ®, regsize, 0); + if (err != EOK) + fprintf_unfiltered (gdb_stderr, + "Warning unable to write regset %d: %s\n", regno, + safe_strerror (err)); + } +} + +static void +notice_signals (void) +{ + int signo; + + for (signo = 1; signo < NSIG; signo++) + { + if (signal_stop_state (target_signal_from_host (signo)) == 0 + && signal_print_state (target_signal_from_host (signo)) == 0 + && signal_pass_state (target_signal_from_host (signo)) == 1) + sigdelset (&run.trace, signo); + else + sigaddset (&run.trace, signo); + } +} + +/* When the user changes the state of gdb's signal handling via the + "handle" command, this function gets called to see if any change + in the /proc interface is required. It is also called internally + by other /proc interface functions to initialize the state of + the traced signal set. */ +static void +procfs_notice_signals (ptid_t ptid) +{ + sigemptyset (&run.trace); + notice_signals (); +} + +static struct tidinfo * +procfs_thread_info (pid_t pid, short tid) +{ +/* NYI */ + return NULL; +} + +char * +procfs_pid_to_str (ptid_t ptid) +{ + static char buf[1024]; + int pid, tid, n; + struct tidinfo *tip; + + pid = ptid_get_pid (ptid); + tid = ptid_get_tid (ptid); + + n = snprintf (buf, 1023, "process %d", pid); + +#if 0 /* NYI */ + tip = procfs_thread_info (pid, tid); + if (tip != NULL) + snprintf (&buf[n], 1023, " (state = 0x%02x)", tip->state); +#endif + + return buf; +} + +static void +init_procfs_ops (void) +{ + procfs_ops.to_shortname = "procfs"; + procfs_ops.to_longname = "QNX Neutrino procfs child process"; + procfs_ops.to_doc = + "QNX Neutrino procfs child process (started by the \"run\" command).\n\ + target procfs "; + procfs_ops.to_open = procfs_open; + procfs_ops.to_attach = procfs_attach; + procfs_ops.to_post_attach = procfs_post_attach; + procfs_ops.to_detach = procfs_detach; + procfs_ops.to_resume = procfs_resume; + procfs_ops.to_wait = procfs_wait; + procfs_ops.to_fetch_registers = procfs_fetch_registers; + procfs_ops.to_store_registers = procfs_store_registers; + procfs_ops.to_prepare_to_store = procfs_prepare_to_store; + procfs_ops.to_xfer_memory = procfs_xfer_memory; + procfs_ops.to_files_info = procfs_files_info; + procfs_ops.to_insert_breakpoint = procfs_insert_breakpoint; + procfs_ops.to_remove_breakpoint = procfs_remove_breakpoint; + procfs_ops.to_can_use_hw_breakpoint = procfs_can_use_hw_breakpoint; + procfs_ops.to_insert_hw_breakpoint = procfs_insert_hw_breakpoint; + procfs_ops.to_remove_hw_breakpoint = procfs_remove_breakpoint; + procfs_ops.to_insert_watchpoint = procfs_insert_hw_watchpoint; + procfs_ops.to_remove_watchpoint = procfs_remove_hw_watchpoint; + procfs_ops.to_stopped_by_watchpoint = procfs_stopped_by_watchpoint; + procfs_ops.to_terminal_init = terminal_init_inferior; + procfs_ops.to_terminal_inferior = terminal_inferior; + procfs_ops.to_terminal_ours_for_output = terminal_ours_for_output; + procfs_ops.to_terminal_ours = terminal_ours; + procfs_ops.to_terminal_info = child_terminal_info; + procfs_ops.to_kill = procfs_kill_inferior; + procfs_ops.to_create_inferior = procfs_create_inferior; + procfs_ops.to_mourn_inferior = procfs_mourn_inferior; + procfs_ops.to_can_run = procfs_can_run; + procfs_ops.to_notice_signals = procfs_notice_signals; + procfs_ops.to_thread_alive = procfs_thread_alive; + procfs_ops.to_find_new_threads = procfs_find_new_threads; + procfs_ops.to_pid_to_str = procfs_pid_to_str; + procfs_ops.to_stop = procfs_stop; + procfs_ops.to_stratum = process_stratum; + procfs_ops.to_has_all_memory = 1; + procfs_ops.to_has_memory = 1; + procfs_ops.to_has_stack = 1; + procfs_ops.to_has_registers = 1; + procfs_ops.to_has_execution = 1; + procfs_ops.to_magic = OPS_MAGIC; + procfs_ops.to_have_continuable_watchpoint = 1; +} + +#define OSTYPE_NTO 1 + +void +_initialize_procfs (void) +{ + sigset_t set; + + init_procfs_ops (); + add_target (&procfs_ops); + + /* We use SIGUSR1 to gain control after we block waiting for a process. + We use sigwaitevent to wait. */ + sigemptyset (&set); + sigaddset (&set, SIGUSR1); + sigprocmask (SIG_BLOCK, &set, NULL); + + /* Set up trace and fault sets, as gdb expects them. */ + sigemptyset (&run.trace); + notice_signals (); + + /* Stuff some information. */ + nto_cpuinfo_flags = SYSPAGE_ENTRY (cpuinfo)->flags; + nto_cpuinfo_valid = 1; + + add_info ("pidlist", procfs_pidlist, "pidlist"); + add_info ("meminfo", procfs_meminfo, "memory information"); +} + + +static int +procfs_hw_watchpoint (int addr, int len, int type) +{ + procfs_break brk; + + switch (type) + { + case 1: /* Read. */ + brk.type = _DEBUG_BREAK_RD; + break; + case 2: /* Read/Write. */ + brk.type = _DEBUG_BREAK_RW; + break; + default: /* Modify. */ +/* FIXME: brk.type = _DEBUG_BREAK_RWM gives EINVAL for some reason. */ + brk.type = _DEBUG_BREAK_RW; + } + brk.type |= _DEBUG_BREAK_HW; /* Always ask for HW. */ + brk.addr = addr; + brk.size = len; + + errno = devctl (ctl_fd, DCMD_PROC_BREAK, &brk, sizeof (brk), 0); + if (errno != EOK) + { + perror ("Failed to set hardware watchpoint"); + return -1; + } + return 0; +} + +static int +procfs_can_use_hw_breakpoint (int type, int cnt, int othertype) +{ + return 1; +} + +static int +procfs_remove_hw_watchpoint (CORE_ADDR addr, int len, int type) +{ + return procfs_hw_watchpoint (addr, -1, type); +} + +static int +procfs_insert_hw_watchpoint (CORE_ADDR addr, int len, int type) +{ + return procfs_hw_watchpoint (addr, len, type); +} + +static int +procfs_stopped_by_watchpoint (void) +{ + return 0; +} diff --git a/gdb/nto-tdep.c b/gdb/nto-tdep.c new file mode 100644 index 0000000..056b93f --- /dev/null +++ b/gdb/nto-tdep.c @@ -0,0 +1,337 @@ +/* nto-tdep.c - general QNX Neutrino target functionality. + + Copyright 2003 Free Software Foundation, Inc. + + Contributed by QNX Software Systems Ltd. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#include "gdb_stat.h" +#include "gdb_string.h" +#include "nto-tdep.h" +#include "top.h" +#include "cli/cli-decode.h" +#include "cli/cli-cmds.h" +#include "inferior.h" +#include "gdbarch.h" +#include "bfd.h" +#include "elf-bfd.h" +#include "solib-svr4.h" +#include "gdbcore.h" + +#ifdef __CYGWIN__ +#include +#endif + +#ifdef __CYGWIN__ +static char default_nto_target[] = "C:\\QNXsdk\\target\\qnx6"; +#elif defined(__sun__) || defined(linux) +static char default_nto_target[] = "/opt/QNXsdk/target/qnx6"; +#else +static char default_nto_target[] = ""; +#endif + +struct nto_target_ops current_nto_target; + +static char * +nto_target (void) +{ + char *p = getenv ("QNX_TARGET"); + +#ifdef __CYGWIN__ + static char buf[PATH_MAX]; + if (p) + cygwin_conv_to_posix_path (p, buf); + else + cygwin_conv_to_posix_path (default_nto_target, buf); + return buf; +#else + return p ? p : default_nto_target; +#endif +} + +/* Take a string such as i386, rs6000, etc. and map it onto CPUTYPE_X86, + CPUTYPE_PPC, etc. as defined in nto-share/dsmsgs.h. */ +int +nto_map_arch_to_cputype (const char *arch) +{ + if (!strcmp (arch, "i386") || !strcmp (arch, "x86")) + return CPUTYPE_X86; + if (!strcmp (arch, "rs6000") || !strcmp (arch, "powerpc")) + return CPUTYPE_PPC; + if (!strcmp (arch, "mips")) + return CPUTYPE_MIPS; + if (!strcmp (arch, "arm")) + return CPUTYPE_ARM; + if (!strcmp (arch, "sh")) + return CPUTYPE_SH; + return CPUTYPE_UNKNOWN; +} + +int +nto_find_and_open_solib (char *solib, unsigned o_flags, char **temp_pathname) +{ + char *buf, arch_path[PATH_MAX], *nto_root, *endian; + const char *arch; + char *path_fmt = "%s/lib:%s/usr/lib:%s/usr/photon/lib\ +:%s/usr/photon/dll:%s/lib/dll"; + + nto_root = nto_target (); + if (strcmp (TARGET_ARCHITECTURE->arch_name, "i386") == 0) + { + arch = "x86"; + endian = ""; + } + else if (strcmp (TARGET_ARCHITECTURE->arch_name, "rs6000") == 0 + || strcmp (TARGET_ARCHITECTURE->arch_name, "powerpc") == 0) + { + arch = "ppc"; + endian = "be"; + } + else + { + arch = TARGET_ARCHITECTURE->arch_name; + endian = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? "be" : "le"; + } + + sprintf (arch_path, "%s/%s%s", nto_root, arch, endian); + + buf = alloca (strlen (path_fmt) + strlen (arch_path) * 5 + 1); + sprintf (buf, path_fmt, arch_path, arch_path, arch_path, arch_path, + arch_path); + + return openp (buf, 1, solib, o_flags, 0, temp_pathname); +} + +void +nto_init_solib_absolute_prefix (void) +{ + char buf[PATH_MAX * 2], arch_path[PATH_MAX]; + char *nto_root, *endian; + const char *arch; + + nto_root = nto_target (); + if (strcmp (TARGET_ARCHITECTURE->arch_name, "i386") == 0) + { + arch = "x86"; + endian = ""; + } + else if (strcmp (TARGET_ARCHITECTURE->arch_name, "rs6000") == 0 + || strcmp (TARGET_ARCHITECTURE->arch_name, "powerpc") == 0) + { + arch = "ppc"; + endian = "be"; + } + else + { + arch = TARGET_ARCHITECTURE->arch_name; + endian = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? "be" : "le"; + } + + sprintf (arch_path, "%s/%s%s", nto_root, arch, endian); + + sprintf (buf, "set solib-absolute-prefix %s", arch_path); + execute_command (buf, 0); +} + +char ** +nto_parse_redirection (char *pargv[], char **pin, char **pout, char **perr) +{ + char **argv; + char *in, *out, *err, *p; + int argc, i, n; + + for (n = 0; pargv[n]; n++); + if (n == 0) + return NULL; + in = ""; + out = ""; + err = ""; + + argv = xcalloc (n + 1, sizeof argv[0]); + argc = n; + for (i = 0, n = 0; n < argc; n++) + { + p = pargv[n]; + if (*p == '>') + { + p++; + if (*p) + out = p; + else + out = pargv[++n]; + } + else if (*p == '<') + { + p++; + if (*p) + in = p; + else + in = pargv[++n]; + } + else if (*p++ == '2' && *p++ == '>') + { + if (*p == '&' && *(p + 1) == '1') + err = out; + else if (*p) + err = p; + else + err = pargv[++n]; + } + else + argv[i++] = pargv[n]; + } + *pin = in; + *pout = out; + *perr = err; + return argv; +} + +/* The struct lm_info, LM_ADDR, and nto_truncate_ptr are copied from + solib-svr4.c to support nto_relocate_section_addresses + which is different from the svr4 version. */ + +struct lm_info +{ + /* Pointer to copy of link map from inferior. The type is char * + rather than void *, so that we may use byte offsets to find the + various fields without the need for a cast. */ + char *lm; +}; + +static CORE_ADDR +LM_ADDR (struct so_list *so) +{ + struct link_map_offsets *lmo = nto_fetch_link_map_offsets (); + + return (CORE_ADDR) extract_signed_integer (so->lm_info->lm + + lmo->l_addr_offset, + lmo->l_addr_size); +} + +static CORE_ADDR +nto_truncate_ptr (CORE_ADDR addr) +{ + if (TARGET_PTR_BIT == sizeof (CORE_ADDR) * 8) + /* We don't need to truncate anything, and the bit twiddling below + will fail due to overflow problems. */ + return addr; + else + return addr & (((CORE_ADDR) 1 << TARGET_PTR_BIT) - 1); +} + +Elf_Internal_Phdr * +find_load_phdr (bfd *abfd) +{ + Elf_Internal_Phdr *phdr; + unsigned int i; + + if (!elf_tdata (abfd)) + return NULL; + + phdr = elf_tdata (abfd)->phdr; + for (i = 0; i < elf_elfheader (abfd)->e_phnum; i++, phdr++) + { + if (phdr->p_type == PT_LOAD && (phdr->p_flags & PF_X)) + return phdr; + } + return NULL; +} + +void +nto_relocate_section_addresses (struct so_list *so, struct section_table *sec) +{ + /* Neutrino treats the l_addr base address field in link.h as different than + the base address in the System V ABI and so the offset needs to be + calculated and applied to relocations. */ + Elf_Internal_Phdr *phdr = find_load_phdr (sec->bfd); + unsigned vaddr = phdr ? phdr->p_vaddr : 0; + + sec->addr = nto_truncate_ptr (sec->addr + LM_ADDR (so) - vaddr); + sec->endaddr = nto_truncate_ptr (sec->endaddr + LM_ADDR (so) - vaddr); +} + +static void +fetch_core_registers (char *core_reg_sect, unsigned core_reg_size, + int which, CORE_ADDR reg_addr) +{ + nto_regset_t regset; + +/* See corelow.c:get_core_registers for values of WHICH. */ + if (which == 0) + { + memcpy ((char *) ®set, core_reg_sect, + min (core_reg_size, sizeof (regset))); + nto_supply_gregset ((char *) ®set); + } + else if (which == 2) + { + memcpy ((char *) ®set, core_reg_sect, + min (core_reg_size, sizeof (regset))); + nto_supply_fpregset ((char *) ®set); + } +} + +void +nto_dummy_supply_regset (char *regs) +{ + /* Do nothing. */ +} + +/* Register that we are able to handle ELF file formats using standard + procfs "regset" structures. */ +static struct core_fns regset_core_fns = { + bfd_target_elf_flavour, /* core_flavour */ + default_check_format, /* check_format */ + default_core_sniffer, /* core_sniffer */ + fetch_core_registers, /* core_read_registers */ + NULL /* next */ +}; + +void +_initialize_nto_tdep (void) +{ + add_setshow_cmd ("nto-debug", class_maintenance, var_zinteger, + &nto_internal_debugging, "Set QNX NTO internal debugging.\n\ +When non-zero, nto specific debug info is\n\ +displayed. Different information is displayed\n\ +for different positive values.", "Show QNX NTO internal debugging.\n", + NULL, NULL, &setdebuglist, &showdebuglist); + + /* We use SIG45 for pulses, or something, so nostop, noprint + and pass them. */ + signal_stop_update (target_signal_from_name ("SIG45"), 0); + signal_print_update (target_signal_from_name ("SIG45"), 0); + signal_pass_update (target_signal_from_name ("SIG45"), 1); + + /* By default we don't want to stop on these two, but we do want to pass. */ +#if defined(SIGSELECT) + signal_stop_update (SIGSELECT, 0); + signal_print_update (SIGSELECT, 0); + signal_pass_update (SIGSELECT, 1); +#endif + +#if defined(SIGPHOTON) + signal_stop_update (SIGPHOTON, 0); + signal_print_update (SIGPHOTON, 0); + signal_pass_update (SIGPHOTON, 1); +#endif + + /* Register core file support. */ + add_core_fns (®set_core_fns); +} diff --git a/gdb/nto-tdep.h b/gdb/nto-tdep.h new file mode 100644 index 0000000..e22e8fd --- /dev/null +++ b/gdb/nto-tdep.h @@ -0,0 +1,156 @@ +/* nto-tdep.h - QNX Neutrino target header. + + Copyright 2003 Free Software Foundation, Inc. + + Contributed by QNX Software Systems Ltd. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#ifndef _NTO_TDEP_H +#define _NTO_TDEP_H + +#include "defs.h" +#include "solist.h" + +/* Generic functions in nto-tdep.c. */ + +extern void nto_init_solib_absolute_prefix (void); + +char **nto_parse_redirection (char *start_argv[], char **in, + char **out, char **err); + +int proc_iterate_over_mappings (int (*func) (int, CORE_ADDR)); + +void nto_relocate_section_addresses (struct so_list *, struct section_table *); + +int nto_map_arch_to_cputype (const char *); + +int nto_find_and_open_solib (char *, unsigned, char **); + +/* Dummy function for initializing nto_target_ops on targets which do + not define a particular regset. */ +void nto_dummy_supply_regset (char *regs); + +/* Target operations defined for Neutrino targets (-nto-tdep.c). */ + +struct nto_target_ops +{ + int nto_internal_debugging; + unsigned nto_cpuinfo_flags; + int nto_cpuinfo_valid; + + int (*nto_regset_id) (int); + void (*nto_supply_gregset) (char *); + void (*nto_supply_fpregset) (char *); + void (*nto_supply_altregset) (char *); + void (*nto_supply_regset) (int, char *); + int (*nto_register_area) (int, int, unsigned *); + int (*nto_regset_fill) (int, char *); + struct link_map_offsets *(*nto_fetch_link_map_offsets) (void); +}; + +extern struct nto_target_ops current_nto_target; + +/* For 'maintenance debug nto-debug' command. */ +#define nto_internal_debugging \ + (current_nto_target.nto_internal_debugging) + +/* The CPUINFO flags from the remote. Currently used by + i386 for fxsave but future proofing other hosts. + This is initialized in procfs_attach or nto_start_remote + depending on our host/target. It would only be invalid + if we were talking to an older pdebug which didn't support + the cpuinfo message. */ +#define nto_cpuinfo_flags \ + (current_nto_target.nto_cpuinfo_flags) + +/* True if successfully retrieved cpuinfo from remote. */ +#define nto_cpuinfo_valid \ + (current_nto_target.nto_cpuinfo_valid) + +/* Given a register, return an id that represents the Neutrino + regset it came from. If reg == -1 update all regsets. */ +#define nto_regset_id(reg) \ + (*current_nto_target.nto_regset_id) (reg) + +#define nto_supply_gregset(regs) \ + (*current_nto_target.nto_supply_gregset) (regs) + +#define nto_supply_fpregset(regs) \ + (*current_nto_target.nto_supply_fpregset) (regs) + +#define nto_supply_altregset(regs) \ + (*current_nto_target.nto_supply_altregset) (regs) + +/* Given a regset, tell gdb about registers stored in data. */ +#define nto_supply_regset(regset, data) \ + (*current_nto_target.nto_supply_regset) (regset, data) + +/* Given a register and regset, calculate the offset into the regset + and stuff it into the last argument. If regno is -1, calculate the + size of the entire regset. Returns length of data, -1 if unknown + regset, 0 if unknown register. */ +#define nto_register_area(reg, regset, off) \ + (*current_nto_target.nto_register_area) (reg, regset, off) + +/* Build the Neutrino register set info into the data buffer. + Return -1 if unknown regset, 0 otherwise. */ +#define nto_regset_fill(regset, data) \ + (*current_nto_target.nto_regset_fill) (regset, data) + +/* Gives the fetch_link_map_offsets function exposure outside of + solib-svr4.c so that we can override relocate_section_addresses(). */ +#define nto_fetch_link_map_offsets() \ + (*current_nto_target.nto_fetch_link_map_offsets) () + +/* Keep this consistant with neutrino syspage.h. */ +enum +{ + CPUTYPE_X86, + CPUTYPE_PPC, + CPUTYPE_MIPS, + CPUTYPE_SPARE, + CPUTYPE_ARM, + CPUTYPE_SH, + CPUTYPE_UNKNOWN +}; + +enum +{ + OSTYPE_QNX4, + OSTYPE_NTO +}; + +/* These correspond to the DSMSG_* versions in dsmsgs.h. */ +enum +{ + NTO_REG_GENERAL, + NTO_REG_FLOAT, + NTO_REG_SYSTEM, + NTO_REG_ALT, + NTO_REG_END +}; + +typedef char qnx_reg64[8]; + +typedef struct _debug_regs +{ + qnx_reg64 padding[1024]; +} nto_regset_t; + +#endif diff --git a/gdb/observer.c b/gdb/observer.c new file mode 100644 index 0000000..fce5f92 --- /dev/null +++ b/gdb/observer.c @@ -0,0 +1,222 @@ +/* GDB Notifications to Observers. + Copyright 2003 Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +/* An observer is an entity who is interested in being notified when GDB + reaches certain states, or certain events occur in GDB. The entity being + observed is called the Subject. To receive notifications, the observer + attaches a callback to the subject. One subject can have several + observers. + + This file implements an internal generic low-level event notification + mechanism based on the Observer paradigm described in the book "Design + Patterns". This generic event notification mechansim is then re-used + to implement the exported high-level notification management routines + for all possible notifications. + + The current implementation of the generic observer provides support + for contextual data. This contextual data is given to the subject + when attaching the callback. In return, the subject will provide + this contextual data back to the observer as a parameter of the + callback. + + FIXME: The current support for the contextual data is only partial, + as it lacks a mechanism that would deallocate this data when the + callback is detached. This is not a problem so far, as this contextual + data is only used internally to hold a function pointer. Later on, + if a certain observer needs to provide support for user-level + contextual data, then the generic notification mechanism will need + need to be enhanced to allow the observer to provide a routine to + deallocate the data when attaching the callback. + + This file is currently maintained by hand, but the long term plan + if the number of different notifications starts growing is to create + a new script (observer.sh) that would generate this file, and the + associated documentation. */ + +#include "defs.h" +#include "observer.h" + +/* The internal generic observer. */ + +typedef void (generic_observer_notification_ftype) (const void *data, + const void *args); + +struct observer +{ + generic_observer_notification_ftype *notify; + /* No memory management needed for the following field for now. */ + void *data; +}; + +/* A list of observers, maintained by the subject. A subject is + actually represented by its list of observers. */ + +struct observer_list +{ + struct observer_list *next; + struct observer *observer; +}; + +/* Allocate a struct observer_list, intended to be used as a node + in the list of observers maintained by a subject. */ + +static struct observer_list * +xalloc_observer_list_node (void) +{ + struct observer_list *node = XMALLOC (struct observer_list); + node->observer = XMALLOC (struct observer); + return node; +} + +/* The opposite of xalloc_observer_list_node, frees the memory for + the given node. */ + +static void +xfree_observer_list_node (struct observer_list *node) +{ + xfree (node->observer); + xfree (node); +} + +/* Attach the callback NOTIFY to a SUBJECT. The DATA is also stored, + in order for the subject to provide it back to the observer during + a notification. */ + +static struct observer * +generic_observer_attach (struct observer_list **subject, + generic_observer_notification_ftype * notify, + void *data) +{ + struct observer_list *observer_list = xalloc_observer_list_node (); + + observer_list->next = *subject; + observer_list->observer->notify = notify; + observer_list->observer->data = data; + *subject = observer_list; + + return observer_list->observer; +} + +/* Remove the given OBSERVER from the SUBJECT. Once detached, OBSERVER + should no longer be used, as it is no longer valid. */ + +static void +generic_observer_detach (struct observer_list **subject, + const struct observer *observer) +{ + struct observer_list *previous_node = NULL; + struct observer_list *current_node = *subject; + + while (current_node != NULL) + { + if (current_node->observer == observer) + { + if (previous_node != NULL) + previous_node->next = current_node->next; + else + *subject = current_node->next; + xfree_observer_list_node (current_node); + return; + } + previous_node = current_node; + current_node = current_node->next; + } + + /* We should never reach this point. However, this should not be + a very serious error, so simply report a warning to the user. */ + warning ("Failed to detach observer"); +} + +/* Send a notification to all the observers of SUBJECT. ARGS is passed to + all observers as an argument to the notification callback. */ + +static void +generic_observer_notify (struct observer_list *subject, const void *args) +{ + struct observer_list *current_node = subject; + + while (current_node != NULL) + { + (*current_node->observer->notify) (current_node->observer->data, args); + current_node = current_node->next; + } +} + +/* normal_stop notifications. */ + +static struct observer_list *normal_stop_subject = NULL; + +static void +observer_normal_stop_notification_stub (const void *data, + const void *unused_args) +{ + observer_normal_stop_ftype *notify = (observer_normal_stop_ftype *) data; + (*notify) (); +} + +struct observer * +observer_attach_normal_stop (observer_normal_stop_ftype *f) +{ + return generic_observer_attach (&normal_stop_subject, + &observer_normal_stop_notification_stub, + (void *) f); +} + +void +observer_detach_normal_stop (struct observer *observer) +{ + generic_observer_detach (&normal_stop_subject, observer); +} + +void +observer_notify_normal_stop (void) +{ + generic_observer_notify (normal_stop_subject, NULL); +} + +/* The following code is only used to unit-test the observers from our + testsuite. DO NOT USE IT within observer.c (or anywhere else for + that matter)! */ + +/* If we define these variables and functions as `static', the + compiler will optimize them out. */ + +int observer_test_first_observer = 0; +int observer_test_second_observer = 0; +int observer_test_third_observer = 0; + +void +observer_test_first_notification_function (void) +{ + observer_test_first_observer++; +} + +void +observer_test_second_notification_function (void) +{ + observer_test_second_observer++; +} + +void +observer_test_third_notification_function (void) +{ + observer_test_third_observer++; +} + diff --git a/gdb/observer.h b/gdb/observer.h new file mode 100644 index 0000000..8b9a6db --- /dev/null +++ b/gdb/observer.h @@ -0,0 +1,35 @@ +/* GDB Notifications to Observers. + Copyright 2003 Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#ifndef OBSERVER_H +#define OBSERVER_H + +struct observer; + +/* normal_stop notifications. */ + +typedef void (observer_normal_stop_ftype) (void); + +extern struct observer * + observer_attach_normal_stop (observer_normal_stop_ftype *f); +extern void observer_detach_normal_stop (struct observer *observer); +extern void observer_notify_normal_stop (void); + +#endif /* OBSERVER_H */ diff --git a/gdb/reggroups.c b/gdb/reggroups.c new file mode 100644 index 0000000..7dd0562 --- /dev/null +++ b/gdb/reggroups.c @@ -0,0 +1,288 @@ +/* Register groupings for GDB, the GNU debugger. + + Copyright 2002, 2003 Free Software Foundation, Inc. + + Contributed by Red Hat. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#include "defs.h" +#include "reggroups.h" +#include "gdbtypes.h" +#include "gdb_assert.h" +#include "regcache.h" +#include "command.h" +#include "gdbcmd.h" /* For maintenanceprintlist. */ + +/* Individual register groups. */ + +struct reggroup +{ + const char *name; + enum reggroup_type type; +}; + +struct reggroup * +reggroup_new (const char *name, enum reggroup_type type) +{ + struct reggroup *group = XMALLOC (struct reggroup); + group->name = name; + group->type = type; + return group; +} + +/* Register group attributes. */ + +const char * +reggroup_name (struct reggroup *group) +{ + return group->name; +} + +enum reggroup_type +reggroup_type (struct reggroup *group) +{ + return group->type; +} + +/* A linked list of groups for the given architecture. */ + +struct reggroup_el +{ + struct reggroup *group; + struct reggroup_el *next; +}; + +struct reggroups +{ + struct reggroup_el *first; + struct reggroup_el **last; +}; + +static struct gdbarch_data *reggroups_data; + +static void * +reggroups_init (struct gdbarch *gdbarch) +{ + struct reggroups *groups = GDBARCH_OBSTACK_ZALLOC (gdbarch, + struct reggroups); + groups->last = &groups->first; + return groups; +} + +/* Add a register group (with attribute values) to the pre-defined + list. */ + +static void +add_group (struct reggroups *groups, struct reggroup *group, + struct reggroup_el *el) +{ + gdb_assert (group != NULL); + el->group = group; + el->next = NULL; + (*groups->last) = el; + groups->last = &el->next; +} + +void +reggroup_add (struct gdbarch *gdbarch, struct reggroup *group) +{ + struct reggroups *groups = gdbarch_data (gdbarch, reggroups_data); + + if (groups == NULL) + { + /* ULGH, called during architecture initialization. Patch + things up. */ + groups = reggroups_init (gdbarch); + set_gdbarch_data (gdbarch, reggroups_data, groups); + } + add_group (groups, group, + GDBARCH_OBSTACK_ZALLOC (gdbarch, struct reggroup_el)); +} + +/* The default register groups for an architecture. */ + +static struct reggroups default_groups = { NULL, &default_groups.first }; + +/* A register group iterator. */ + +struct reggroup * +reggroup_next (struct gdbarch *gdbarch, struct reggroup *last) +{ + struct reggroups *groups; + struct reggroup_el *el; + + /* Don't allow this function to be called during architecture + creation. If there are no groups, use the default groups list. */ + groups = gdbarch_data (gdbarch, reggroups_data); + gdb_assert (groups != NULL); + if (groups->first == NULL) + groups = &default_groups; + + /* Return the first/next reggroup. */ + if (last == NULL) + return groups->first->group; + for (el = groups->first; el != NULL; el = el->next) + { + if (el->group == last) + { + if (el->next != NULL) + return el->next->group; + else + return NULL; + } + } + return NULL; +} + +/* Is REGNUM a member of REGGROUP? */ +int +default_register_reggroup_p (struct gdbarch *gdbarch, int regnum, + struct reggroup *group) +{ + int vector_p; + int float_p; + int raw_p; + + if (REGISTER_NAME (regnum) == NULL + || *REGISTER_NAME (regnum) == '\0') + return 0; + if (group == all_reggroup) + return 1; + vector_p = TYPE_VECTOR (register_type (gdbarch, regnum)); + float_p = TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT; + /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs + (gdbarch), as not all architectures are multi-arch. */ + raw_p = regnum < NUM_REGS; + if (group == float_reggroup) + return float_p; + if (group == vector_reggroup) + return vector_p; + if (group == general_reggroup) + return (!vector_p && !float_p); + if (group == save_reggroup || group == restore_reggroup) + return raw_p; + return 0; +} + +/* Dump out a table of register groups for the current architecture. */ + +static void +reggroups_dump (struct gdbarch *gdbarch, struct ui_file *file) +{ + struct reggroup *group = NULL; + + do + { + /* Group name. */ + { + const char *name; + if (group == NULL) + name = "Group"; + else + name = reggroup_name (group); + fprintf_unfiltered (file, " %-10s", name); + } + + /* Group type. */ + { + const char *type; + if (group == NULL) + type = "Type"; + else + { + switch (reggroup_type (group)) + { + case USER_REGGROUP: + type = "user"; + break; + case INTERNAL_REGGROUP: + type = "internal"; + break; + default: + internal_error (__FILE__, __LINE__, "bad switch"); + } + } + fprintf_unfiltered (file, " %-10s", type); + } + + /* Note: If you change this, be sure to also update the + documentation. */ + + fprintf_unfiltered (file, "\n"); + + group = reggroup_next (gdbarch, group); + } + while (group != NULL); +} + +static void +maintenance_print_reggroups (char *args, int from_tty) +{ + if (args == NULL) + reggroups_dump (current_gdbarch, gdb_stdout); + else + { + struct ui_file *file = gdb_fopen (args, "w"); + if (file == NULL) + perror_with_name ("maintenance print reggroups"); + reggroups_dump (current_gdbarch, file); + ui_file_delete (file); + } +} + +/* Pre-defined register groups. */ +static struct reggroup general_group = { "general", USER_REGGROUP }; +static struct reggroup float_group = { "float", USER_REGGROUP }; +static struct reggroup system_group = { "system", USER_REGGROUP }; +static struct reggroup vector_group = { "vector", USER_REGGROUP }; +static struct reggroup all_group = { "all", USER_REGGROUP }; +static struct reggroup save_group = { "save", INTERNAL_REGGROUP }; +static struct reggroup restore_group = { "restore", INTERNAL_REGGROUP }; + +struct reggroup *const general_reggroup = &general_group; +struct reggroup *const float_reggroup = &float_group; +struct reggroup *const system_reggroup = &system_group; +struct reggroup *const vector_reggroup = &vector_group; +struct reggroup *const all_reggroup = &all_group; +struct reggroup *const save_reggroup = &save_group; +struct reggroup *const restore_reggroup = &restore_group; + +extern initialize_file_ftype _initialize_reggroup; /* -Wmissing-prototypes */ + +void +_initialize_reggroup (void) +{ + reggroups_data = register_gdbarch_data (reggroups_init); + + /* The pre-defined list of groups. */ + add_group (&default_groups, general_reggroup, XMALLOC (struct reggroup_el)); + add_group (&default_groups, float_reggroup, XMALLOC (struct reggroup_el)); + add_group (&default_groups, system_reggroup, XMALLOC (struct reggroup_el)); + add_group (&default_groups, vector_reggroup, XMALLOC (struct reggroup_el)); + add_group (&default_groups, all_reggroup, XMALLOC (struct reggroup_el)); + add_group (&default_groups, save_reggroup, XMALLOC (struct reggroup_el)); + add_group (&default_groups, restore_reggroup, XMALLOC (struct reggroup_el)); + + add_cmd ("reggroups", class_maintenance, + maintenance_print_reggroups, "\ +Print the internal register group names.\n\ +Takes an optional file parameter.", + &maintenanceprintlist); + +} diff --git a/gdb/reggroups.h b/gdb/reggroups.h new file mode 100644 index 0000000..22c0a6f --- /dev/null +++ b/gdb/reggroups.h @@ -0,0 +1,64 @@ +/* Register groupings for GDB, the GNU debugger. + + Copyright 2002 Free Software Foundation, Inc. + + Contributed by Red Hat. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#ifndef REGGROUPS_H +#define REGGROUPS_H + +struct gdbarch; +struct reggroup; + +enum reggroup_type { USER_REGGROUP, INTERNAL_REGGROUP }; + +/* Pre-defined, user visible, register groups. */ +extern struct reggroup *const general_reggroup; +extern struct reggroup *const float_reggroup; +extern struct reggroup *const system_reggroup; +extern struct reggroup *const vector_reggroup; +extern struct reggroup *const all_reggroup; + +/* Pre-defined, internal, register groups. */ +extern struct reggroup *const save_reggroup; +extern struct reggroup *const restore_reggroup; + +/* Create a new local register group. */ +extern struct reggroup *reggroup_new (const char *name, + enum reggroup_type type); + +/* Add a register group (with attribute values) to the pre-defined list. */ +extern void reggroup_add (struct gdbarch *gdbarch, struct reggroup *group); + +/* Register group attributes. */ +extern const char *reggroup_name (struct reggroup *reggroup); +extern enum reggroup_type reggroup_type (struct reggroup *reggroup); + +/* Interator for the architecture's register groups. Pass in NULL, + returns the first group. Pass in a group, returns the next group, + or NULL when the last group is reached. */ +extern struct reggroup *reggroup_next (struct gdbarch *gdbarch, + struct reggroup *last); + +/* Is REGNUM a member of REGGROUP? */ +extern int default_register_reggroup_p (struct gdbarch *gdbarch, int regnum, + struct reggroup *reggroup); + +#endif diff --git a/gdb/regset.h b/gdb/regset.h new file mode 100644 index 0000000..6172f0f --- /dev/null +++ b/gdb/regset.h @@ -0,0 +1,41 @@ +/* Manage register sets. + + Copyright 2003 Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#ifndef REGSET_H +#define REGSET_H 1 + +struct gdbarch; +struct regcache; + +/* Data structure describing a register set. */ + +struct regset +{ + /* Data pointer for private use by the methods below, presumably + providing some sort of description of the register set. */ + const void *descr; + + /* Function supplying a register set to a register cache. */ + void (*supply_regset) (const struct regset *, struct regcache *, + int, const void *, size_t); +}; + +#endif /* regset.h */ diff --git a/gdb/remote-fileio.c b/gdb/remote-fileio.c new file mode 100644 index 0000000..fd57617 --- /dev/null +++ b/gdb/remote-fileio.c @@ -0,0 +1,1379 @@ +/* Remote File-I/O communications + + Copyright 2003 Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +/* See the GDB User Guide for details of the GDB remote protocol. */ + +#include "defs.h" +#include "gdb_string.h" +#include "gdbcmd.h" +#include "remote.h" +#include "gdb/fileio.h" +#include "gdb_wait.h" +#include "gdb_stat.h" +#include "remote-fileio.h" + +#include +#include +#ifdef __CYGWIN__ +#include /* For cygwin_conv_to_full_posix_path. */ +#endif +#include + +static struct { + int *fd_map; + int fd_map_size; +} remote_fio_data; + +#define FIO_FD_INVALID -1 +#define FIO_FD_CONSOLE_IN -2 +#define FIO_FD_CONSOLE_OUT -3 + +static int remote_fio_system_call_allowed = 0; + +static int +remote_fileio_init_fd_map (void) +{ + int i; + + if (!remote_fio_data.fd_map) + { + remote_fio_data.fd_map = (int *) xmalloc (10 * sizeof (int)); + remote_fio_data.fd_map_size = 10; + remote_fio_data.fd_map[0] = FIO_FD_CONSOLE_IN; + remote_fio_data.fd_map[1] = FIO_FD_CONSOLE_OUT; + remote_fio_data.fd_map[2] = FIO_FD_CONSOLE_OUT; + for (i = 3; i < 10; ++i) + remote_fio_data.fd_map[i] = FIO_FD_INVALID; + } + return 3; +} + +static int +remote_fileio_resize_fd_map (void) +{ + if (!remote_fio_data.fd_map) + return remote_fileio_init_fd_map (); + remote_fio_data.fd_map_size += 10; + remote_fio_data.fd_map = + (int *) xrealloc (remote_fio_data.fd_map, + remote_fio_data.fd_map_size * sizeof (int)); + return remote_fio_data.fd_map_size - 10; +} + +static int +remote_fileio_next_free_fd (void) +{ + int i; + + for (i = 0; i < remote_fio_data.fd_map_size; ++i) + if (remote_fio_data.fd_map[i] == FIO_FD_INVALID) + return i; + return remote_fileio_resize_fd_map (); +} + +static int +remote_fileio_fd_to_targetfd (int fd) +{ + int target_fd = remote_fileio_next_free_fd (); + remote_fio_data.fd_map[target_fd] = fd; + return target_fd; +} + +static int +remote_fileio_map_fd (int target_fd) +{ + remote_fileio_init_fd_map (); + if (target_fd < 0 || target_fd >= remote_fio_data.fd_map_size) + return FIO_FD_INVALID; + return remote_fio_data.fd_map[target_fd]; +} + +static void +remote_fileio_close_target_fd (int target_fd) +{ + remote_fileio_init_fd_map (); + if (target_fd >= 0 && target_fd < remote_fio_data.fd_map_size) + remote_fio_data.fd_map[target_fd] = FIO_FD_INVALID; +} + +static int +remote_fileio_oflags_to_host (long flags) +{ + int hflags = 0; + + if (flags & FILEIO_O_CREAT) + hflags |= O_CREAT; + if (flags & FILEIO_O_EXCL) + hflags |= O_EXCL; + if (flags & FILEIO_O_TRUNC) + hflags |= O_TRUNC; + if (flags & FILEIO_O_APPEND) + hflags |= O_APPEND; + if (flags & FILEIO_O_RDONLY) + hflags |= O_RDONLY; + if (flags & FILEIO_O_WRONLY) + hflags |= O_WRONLY; + if (flags & FILEIO_O_RDWR) + hflags |= O_RDWR; +/* On systems supporting binary and text mode, always open files in + binary mode. */ +#ifdef O_BINARY + hflags |= O_BINARY; +#endif + return hflags; +} + +static mode_t +remote_fileio_mode_to_host (long mode, int open_call) +{ + mode_t hmode = 0; + + if (!open_call) + { + if (mode & FILEIO_S_IFREG) + hmode |= S_IFREG; + if (mode & FILEIO_S_IFDIR) + hmode |= S_IFDIR; + if (mode & FILEIO_S_IFCHR) + hmode |= S_IFCHR; + } + if (mode & FILEIO_S_IRUSR) + hmode |= S_IRUSR; + if (mode & FILEIO_S_IWUSR) + hmode |= S_IWUSR; + if (mode & FILEIO_S_IXUSR) + hmode |= S_IXUSR; + if (mode & FILEIO_S_IRGRP) + hmode |= S_IRGRP; + if (mode & FILEIO_S_IWGRP) + hmode |= S_IWGRP; + if (mode & FILEIO_S_IXGRP) + hmode |= S_IXGRP; + if (mode & FILEIO_S_IROTH) + hmode |= S_IROTH; + if (mode & FILEIO_S_IWOTH) + hmode |= S_IWOTH; + if (mode & FILEIO_S_IXOTH) + hmode |= S_IXOTH; + return hmode; +} + +static LONGEST +remote_fileio_mode_to_target (mode_t mode) +{ + mode_t tmode = 0; + + if (mode & S_IFREG) + tmode |= FILEIO_S_IFREG; + if (mode & S_IFDIR) + tmode |= FILEIO_S_IFDIR; + if (mode & S_IFCHR) + tmode |= FILEIO_S_IFCHR; + if (mode & S_IRUSR) + tmode |= FILEIO_S_IRUSR; + if (mode & S_IWUSR) + tmode |= FILEIO_S_IWUSR; + if (mode & S_IXUSR) + tmode |= FILEIO_S_IXUSR; + if (mode & S_IRGRP) + tmode |= FILEIO_S_IRGRP; + if (mode & S_IWGRP) + tmode |= FILEIO_S_IWGRP; + if (mode & S_IXGRP) + tmode |= FILEIO_S_IXGRP; + if (mode & S_IROTH) + tmode |= FILEIO_S_IROTH; + if (mode & S_IWOTH) + tmode |= FILEIO_S_IWOTH; + if (mode & S_IXOTH) + tmode |= FILEIO_S_IXOTH; + return tmode; +} + +static int +remote_fileio_errno_to_target (int error) +{ + switch (error) + { + case EPERM: + return FILEIO_EPERM; + case ENOENT: + return FILEIO_ENOENT; + case EINTR: + return FILEIO_EINTR; + case EIO: + return FILEIO_EIO; + case EBADF: + return FILEIO_EBADF; + case EACCES: + return FILEIO_EACCES; + case EFAULT: + return FILEIO_EFAULT; + case EBUSY: + return FILEIO_EBUSY; + case EEXIST: + return FILEIO_EEXIST; + case ENODEV: + return FILEIO_ENODEV; + case ENOTDIR: + return FILEIO_ENOTDIR; + case EISDIR: + return FILEIO_EISDIR; + case EINVAL: + return FILEIO_EINVAL; + case ENFILE: + return FILEIO_ENFILE; + case EMFILE: + return FILEIO_EMFILE; + case EFBIG: + return FILEIO_EFBIG; + case ENOSPC: + return FILEIO_ENOSPC; + case ESPIPE: + return FILEIO_ESPIPE; + case EROFS: + return FILEIO_EROFS; + case ENOSYS: + return FILEIO_ENOSYS; + case ENAMETOOLONG: + return FILEIO_ENAMETOOLONG; + } + return FILEIO_EUNKNOWN; +} + +static int +remote_fileio_seek_flag_to_host (long num, int *flag) +{ + if (!flag) + return 0; + switch (num) + { + case FILEIO_SEEK_SET: + *flag = SEEK_SET; + break; + case FILEIO_SEEK_CUR: + *flag = SEEK_CUR; + break; + case FILEIO_SEEK_END: + *flag = SEEK_END; + break; + default: + return -1; + } + return 0; +} + +static int +remote_fileio_extract_long (char **buf, LONGEST *retlong) +{ + char *c; + int sign = 1; + + if (!buf || !*buf || !**buf || !retlong) + return -1; + c = strchr (*buf, ','); + if (c) + *c++ = '\0'; + else + c = strchr (*buf, '\0'); + while (strchr ("+-", **buf)) + { + if (**buf == '-') + sign = -sign; + ++*buf; + } + for (*retlong = 0; **buf; ++*buf) + { + *retlong <<= 4; + if (**buf >= '0' && **buf <= '9') + *retlong += **buf - '0'; + else if (**buf >= 'a' && **buf <= 'f') + *retlong += **buf - 'a' + 10; + else if (**buf >= 'A' && **buf <= 'F') + *retlong += **buf - 'A' + 10; + else + return -1; + } + *retlong *= sign; + *buf = c; + return 0; +} + +static int +remote_fileio_extract_int (char **buf, long *retint) +{ + int ret; + LONGEST retlong; + + if (!retint) + return -1; + ret = remote_fileio_extract_long (buf, &retlong); + if (!ret) + *retint = (long) retlong; + return ret; +} + +static int +remote_fileio_extract_ptr_w_len (char **buf, CORE_ADDR *ptrval, int *length) +{ + char *c; + LONGEST retlong; + + if (!buf || !*buf || !**buf || !ptrval || !length) + return -1; + c = strchr (*buf, '/'); + if (!c) + return -1; + *c++ = '\0'; + if (remote_fileio_extract_long (buf, &retlong)) + return -1; + *ptrval = (CORE_ADDR) retlong; + *buf = c; + if (remote_fileio_extract_long (buf, &retlong)) + return -1; + *length = (int) retlong; + return 0; +} + +/* Convert to big endian */ +static void +remote_fileio_to_be (LONGEST num, char *buf, int bytes) +{ + int i; + + for (i = 0; i < bytes; ++i) + buf[i] = (num >> (8 * (bytes - i - 1))) & 0xff; +} + +static void +remote_fileio_to_fio_int (long num, fio_int_t fnum) +{ + remote_fileio_to_be ((LONGEST) num, (char *) fnum, 4); +} + +static void +remote_fileio_to_fio_uint (long num, fio_uint_t fnum) +{ + remote_fileio_to_be ((LONGEST) num, (char *) fnum, 4); +} + +static void +remote_fileio_to_fio_mode (mode_t num, fio_mode_t fnum) +{ + remote_fileio_to_be (remote_fileio_mode_to_target(num), (char *) fnum, 4); +} + +static void +remote_fileio_to_fio_time (time_t num, fio_time_t fnum) +{ + remote_fileio_to_be ((LONGEST) num, (char *) fnum, 4); +} + +static void +remote_fileio_to_fio_long (LONGEST num, fio_long_t fnum) +{ + remote_fileio_to_be (num, (char *) fnum, 8); +} + +static void +remote_fileio_to_fio_ulong (LONGEST num, fio_ulong_t fnum) +{ + remote_fileio_to_be (num, (char *) fnum, 8); +} + +static void +remote_fileio_to_fio_stat (struct stat *st, struct fio_stat *fst) +{ + /* `st_dev' is set in the calling function */ + remote_fileio_to_fio_uint ((long) st->st_ino, fst->fst_ino); + remote_fileio_to_fio_mode (st->st_mode, fst->fst_mode); + remote_fileio_to_fio_uint ((long) st->st_nlink, fst->fst_nlink); + remote_fileio_to_fio_uint ((long) st->st_uid, fst->fst_uid); + remote_fileio_to_fio_uint ((long) st->st_gid, fst->fst_gid); + remote_fileio_to_fio_uint ((long) st->st_rdev, fst->fst_rdev); + remote_fileio_to_fio_ulong ((LONGEST) st->st_size, fst->fst_size); + remote_fileio_to_fio_ulong ((LONGEST) st->st_blksize, fst->fst_blksize); + remote_fileio_to_fio_ulong ((LONGEST) st->st_blocks, fst->fst_blocks); + remote_fileio_to_fio_time (st->st_atime, fst->fst_atime); + remote_fileio_to_fio_time (st->st_mtime, fst->fst_mtime); + remote_fileio_to_fio_time (st->st_ctime, fst->fst_ctime); +} + +static void +remote_fileio_to_fio_timeval (struct timeval *tv, struct fio_timeval *ftv) +{ + remote_fileio_to_fio_time (tv->tv_sec, ftv->ftv_sec); + remote_fileio_to_fio_long (tv->tv_usec, ftv->ftv_usec); +} + +static int remote_fio_ctrl_c_flag = 0; +static int remote_fio_no_longjmp = 0; + +#if defined (HAVE_SIGACTION) && defined (SA_RESTART) +static struct sigaction remote_fio_sa; +static struct sigaction remote_fio_osa; +#else +static void (*remote_fio_ofunc)(int); +#endif + +static void +remote_fileio_sig_init (void) +{ +#if defined (HAVE_SIGACTION) && defined (SA_RESTART) + remote_fio_sa.sa_handler = SIG_IGN; + sigemptyset (&remote_fio_sa.sa_mask); + remote_fio_sa.sa_flags = 0; + sigaction (SIGINT, &remote_fio_sa, &remote_fio_osa); +#else + remote_fio_ofunc = signal (SIGINT, SIG_IGN); +#endif +} + +static void +remote_fileio_sig_set (void (*sigint_func)(int)) +{ +#if defined (HAVE_SIGACTION) && defined (SA_RESTART) + remote_fio_sa.sa_handler = sigint_func; + sigemptyset (&remote_fio_sa.sa_mask); + remote_fio_sa.sa_flags = 0; + sigaction (SIGINT, &remote_fio_sa, NULL); +#else + signal (SIGINT, sigint_func); +#endif +} + +static void +remote_fileio_sig_exit (void) +{ +#if defined (HAVE_SIGACTION) && defined (SA_RESTART) + sigaction (SIGINT, &remote_fio_osa, NULL); +#else + signal (SIGINT, remote_fio_ofunc); +#endif +} + +static void +remote_fileio_ctrl_c_signal_handler (int signo) +{ + remote_fileio_sig_set (SIG_IGN); + remote_fio_ctrl_c_flag = 1; + if (!remote_fio_no_longjmp) + throw_exception (RETURN_QUIT); + remote_fileio_sig_set (remote_fileio_ctrl_c_signal_handler); +} + +static void +remote_fileio_reply (int retcode, int error) +{ + char buf[32]; + + remote_fileio_sig_set (SIG_IGN); + strcpy (buf, "F"); + if (retcode < 0) + { + strcat (buf, "-"); + retcode = -retcode; + } + sprintf (buf + strlen (buf), "%x", retcode); + if (error || remote_fio_ctrl_c_flag) + { + if (error && remote_fio_ctrl_c_flag) + error = FILEIO_EINTR; + if (error < 0) + { + strcat (buf, "-"); + error = -error; + } + sprintf (buf + strlen (buf), ",%x", error); + if (remote_fio_ctrl_c_flag) + strcat (buf, ",C"); + } + remote_fileio_sig_set (remote_fileio_ctrl_c_signal_handler); + putpkt (buf); +} + +static void +remote_fileio_ioerror (void) +{ + remote_fileio_reply (-1, FILEIO_EIO); +} + +static void +remote_fileio_badfd (void) +{ + remote_fileio_reply (-1, FILEIO_EBADF); +} + +static void +remote_fileio_return_errno (int retcode) +{ + remote_fileio_reply (retcode, + retcode < 0 ? remote_fileio_errno_to_target (errno) : 0); +} + +static void +remote_fileio_return_success (int retcode) +{ + remote_fileio_reply (retcode, 0); +} + +/* Wrapper function for remote_write_bytes() which has the disadvantage to + write only one packet, regardless of the requested number of bytes to + transfer. This wrapper calls remote_write_bytes() as often as needed. */ +static int +remote_fileio_write_bytes (CORE_ADDR memaddr, char *myaddr, int len) +{ + int ret = 0, written; + + while (len > 0 && (written = remote_write_bytes (memaddr, myaddr, len)) > 0) + { + len -= written; + memaddr += written; + myaddr += written; + ret += written; + } + return ret; +} + +static void +remote_fileio_func_open (char *buf) +{ + CORE_ADDR ptrval; + int length, retlength; + long num; + int flags, fd; + mode_t mode; + char *pathname; + struct stat st; + + /* 1. Parameter: Ptr to pathname / length incl. trailing zero */ + if (remote_fileio_extract_ptr_w_len (&buf, &ptrval, &length)) + { + remote_fileio_ioerror (); + return; + } + /* 2. Parameter: open flags */ + if (remote_fileio_extract_int (&buf, &num)) + { + remote_fileio_ioerror (); + return; + } + flags = remote_fileio_oflags_to_host (num); + /* 3. Parameter: open mode */ + if (remote_fileio_extract_int (&buf, &num)) + { + remote_fileio_ioerror (); + return; + } + mode = remote_fileio_mode_to_host (num, 1); + + /* Request pathname using 'm' packet */ + pathname = alloca (length); + retlength = remote_read_bytes (ptrval, pathname, length); + if (retlength != length) + { + remote_fileio_ioerror (); + return; + } + + /* Check if pathname exists and is not a regular file or directory. If so, + return an appropriate error code. Same for trying to open directories + for writing. */ + if (!stat (pathname, &st)) + { + if (!S_ISREG (st.st_mode) && !S_ISDIR (st.st_mode)) + { + remote_fileio_reply (-1, FILEIO_ENODEV); + return; + } + if (S_ISDIR (st.st_mode) + && ((flags & O_WRONLY) == O_WRONLY || (flags & O_RDWR) == O_RDWR)) + { + remote_fileio_reply (-1, FILEIO_EISDIR); + return; + } + } + + remote_fio_no_longjmp = 1; + fd = open (pathname, flags, mode); + if (fd < 0) + { + remote_fileio_return_errno (-1); + return; + } + + fd = remote_fileio_fd_to_targetfd (fd); + remote_fileio_return_success (fd); +} + +static void +remote_fileio_func_close (char *buf) +{ + long num; + int fd; + + /* Parameter: file descriptor */ + if (remote_fileio_extract_int (&buf, &num)) + { + remote_fileio_ioerror (); + return; + } + fd = remote_fileio_map_fd ((int) num); + if (fd == FIO_FD_INVALID) + { + remote_fileio_badfd (); + return; + } + + remote_fio_no_longjmp = 1; + if (fd != FIO_FD_CONSOLE_IN && fd != FIO_FD_CONSOLE_OUT && close (fd)) + remote_fileio_return_errno (-1); + remote_fileio_close_target_fd ((int) num); + remote_fileio_return_success (0); +} + +static void +remote_fileio_func_read (char *buf) +{ + long target_fd, num; + LONGEST lnum; + CORE_ADDR ptrval; + int fd, ret, retlength; + char *buffer; + size_t length; + off_t old_offset, new_offset; + + /* 1. Parameter: file descriptor */ + if (remote_fileio_extract_int (&buf, &target_fd)) + { + remote_fileio_ioerror (); + return; + } + fd = remote_fileio_map_fd ((int) target_fd); + if (fd == FIO_FD_INVALID) + { + remote_fileio_badfd (); + return; + } + /* 2. Parameter: buffer pointer */ + if (remote_fileio_extract_long (&buf, &lnum)) + { + remote_fileio_ioerror (); + return; + } + ptrval = (CORE_ADDR) lnum; + /* 3. Parameter: buffer length */ + if (remote_fileio_extract_int (&buf, &num)) + { + remote_fileio_ioerror (); + return; + } + length = (size_t) num; + + switch (fd) + { + case FIO_FD_CONSOLE_OUT: + remote_fileio_badfd (); + return; + case FIO_FD_CONSOLE_IN: + { + static char *remaining_buf = NULL; + static int remaining_length = 0; + + buffer = (char *) xmalloc (32768); + if (remaining_buf) + { + remote_fio_no_longjmp = 1; + if (remaining_length > length) + { + memcpy (buffer, remaining_buf, length); + memmove (remaining_buf, remaining_buf + length, + remaining_length - length); + remaining_length -= length; + ret = length; + } + else + { + memcpy (buffer, remaining_buf, remaining_length); + xfree (remaining_buf); + remaining_buf = NULL; + ret = remaining_length; + } + } + else + { + ret = ui_file_read (gdb_stdtargin, buffer, 32767); + remote_fio_no_longjmp = 1; + if (ret > 0 && (size_t)ret > length) + { + remaining_buf = (char *) xmalloc (ret - length); + remaining_length = ret - length; + memcpy (remaining_buf, buffer + length, remaining_length); + ret = length; + } + } + } + break; + default: + buffer = (char *) xmalloc (length); + /* POSIX defines EINTR behaviour of read in a weird way. It's allowed + for read() to return -1 even if "some" bytes have been read. It + has been corrected in SUSv2 but that doesn't help us much... + Therefore a complete solution must check how many bytes have been + read on EINTR to return a more reliable value to the target */ + old_offset = lseek (fd, 0, SEEK_CUR); + remote_fio_no_longjmp = 1; + ret = read (fd, buffer, length); + if (ret < 0 && errno == EINTR) + { + new_offset = lseek (fd, 0, SEEK_CUR); + /* If some data has been read, return the number of bytes read. + The Ctrl-C flag is set in remote_fileio_reply() anyway */ + if (old_offset != new_offset) + ret = new_offset - old_offset; + } + break; + } + + if (ret > 0) + { + retlength = remote_fileio_write_bytes (ptrval, buffer, ret); + if (retlength != ret) + ret = -1; /* errno has been set to EIO in remote_fileio_write_bytes() */ + } + + if (ret < 0) + remote_fileio_return_errno (-1); + else + remote_fileio_return_success (ret); + + xfree (buffer); +} + +static void +remote_fileio_func_write (char *buf) +{ + long target_fd, num; + LONGEST lnum; + CORE_ADDR ptrval; + int fd, ret, retlength; + char *buffer; + size_t length; + + /* 1. Parameter: file descriptor */ + if (remote_fileio_extract_int (&buf, &target_fd)) + { + remote_fileio_ioerror (); + return; + } + fd = remote_fileio_map_fd ((int) target_fd); + if (fd == FIO_FD_INVALID) + { + remote_fileio_badfd (); + return; + } + /* 2. Parameter: buffer pointer */ + if (remote_fileio_extract_long (&buf, &lnum)) + { + remote_fileio_ioerror (); + return; + } + ptrval = (CORE_ADDR) lnum; + /* 3. Parameter: buffer length */ + if (remote_fileio_extract_int (&buf, &num)) + { + remote_fileio_ioerror (); + return; + } + length = (size_t) num; + + buffer = (char *) xmalloc (length); + retlength = remote_read_bytes (ptrval, buffer, length); + if (retlength != length) + { + xfree (buffer); + remote_fileio_ioerror (); + return; + } + + remote_fio_no_longjmp = 1; + switch (fd) + { + case FIO_FD_CONSOLE_IN: + remote_fileio_badfd (); + return; + case FIO_FD_CONSOLE_OUT: + ui_file_write (target_fd == 1 ? gdb_stdtarg : gdb_stdtargerr, buffer, + length); + gdb_flush (target_fd == 1 ? gdb_stdtarg : gdb_stdtargerr); + ret = length; + break; + default: + ret = write (fd, buffer, length); + if (ret < 0 && errno == EACCES) + errno = EBADF; /* Cygwin returns EACCESS when writing to a R/O file.*/ + break; + } + + if (ret < 0) + remote_fileio_return_errno (-1); + else + remote_fileio_return_success (ret); + + xfree (buffer); +} + +static void +remote_fileio_func_lseek (char *buf) +{ + long num; + LONGEST lnum; + int fd, flag; + off_t offset, ret; + + /* 1. Parameter: file descriptor */ + if (remote_fileio_extract_int (&buf, &num)) + { + remote_fileio_ioerror (); + return; + } + fd = remote_fileio_map_fd ((int) num); + if (fd == FIO_FD_INVALID) + { + remote_fileio_badfd (); + return; + } + else if (fd == FIO_FD_CONSOLE_IN || fd == FIO_FD_CONSOLE_OUT) + { + remote_fileio_reply (-1, FILEIO_ESPIPE); + return; + } + + /* 2. Parameter: offset */ + if (remote_fileio_extract_long (&buf, &lnum)) + { + remote_fileio_ioerror (); + return; + } + offset = (off_t) lnum; + /* 3. Parameter: flag */ + if (remote_fileio_extract_int (&buf, &num)) + { + remote_fileio_ioerror (); + return; + } + if (remote_fileio_seek_flag_to_host (num, &flag)) + { + remote_fileio_reply (-1, FILEIO_EINVAL); + return; + } + + remote_fio_no_longjmp = 1; + ret = lseek (fd, offset, flag); + + if (ret == (off_t) -1) + remote_fileio_return_errno (-1); + else + remote_fileio_return_success (ret); +} + +static void +remote_fileio_func_rename (char *buf) +{ + CORE_ADDR ptrval; + int length, retlength; + char *oldpath, *newpath; + int ret, of, nf; + struct stat ost, nst; + + /* 1. Parameter: Ptr to oldpath / length incl. trailing zero */ + if (remote_fileio_extract_ptr_w_len (&buf, &ptrval, &length)) + { + remote_fileio_ioerror (); + return; + } + /* Request oldpath using 'm' packet */ + oldpath = alloca (length); + retlength = remote_read_bytes (ptrval, oldpath, length); + if (retlength != length) + { + remote_fileio_ioerror (); + return; + } + /* 2. Parameter: Ptr to newpath / length incl. trailing zero */ + if (remote_fileio_extract_ptr_w_len (&buf, &ptrval, &length)) + { + remote_fileio_ioerror (); + return; + } + /* Request newpath using 'm' packet */ + newpath = alloca (length); + retlength = remote_read_bytes (ptrval, newpath, length); + if (retlength != length) + { + remote_fileio_ioerror (); + return; + } + + /* Only operate on regular files and directories */ + of = stat (oldpath, &ost); + nf = stat (newpath, &nst); + if ((!of && !S_ISREG (ost.st_mode) && !S_ISDIR (ost.st_mode)) + || (!nf && !S_ISREG (nst.st_mode) && !S_ISDIR (nst.st_mode))) + { + remote_fileio_reply (-1, FILEIO_EACCES); + return; + } + + remote_fio_no_longjmp = 1; + ret = rename (oldpath, newpath); + + if (ret == -1) + { + /* Special case: newpath is a non-empty directory. Some systems + return ENOTEMPTY, some return EEXIST. We coerce that to be + always EEXIST. */ + if (errno == ENOTEMPTY) + errno = EEXIST; +#ifdef __CYGWIN__ + /* Workaround some Cygwin problems with correct errnos. */ + if (errno == EACCES) + { + if (!of && !nf && S_ISDIR (nst.st_mode)) + { + if (S_ISREG (ost.st_mode)) + errno = EISDIR; + else + { + char oldfullpath[PATH_MAX + 1]; + char newfullpath[PATH_MAX + 1]; + int len; + + cygwin_conv_to_full_posix_path (oldpath, oldfullpath); + cygwin_conv_to_full_posix_path (newpath, newfullpath); + len = strlen (oldfullpath); + if (newfullpath[len] == '/' + && !strncmp (oldfullpath, newfullpath, len)) + errno = EINVAL; + else + errno = EEXIST; + } + } + } +#endif + + remote_fileio_return_errno (-1); + } + else + remote_fileio_return_success (ret); +} + +static void +remote_fileio_func_unlink (char *buf) +{ + CORE_ADDR ptrval; + int length, retlength; + char *pathname; + int ret; + struct stat st; + + /* Parameter: Ptr to pathname / length incl. trailing zero */ + if (remote_fileio_extract_ptr_w_len (&buf, &ptrval, &length)) + { + remote_fileio_ioerror (); + return; + } + /* Request pathname using 'm' packet */ + pathname = alloca (length); + retlength = remote_read_bytes (ptrval, pathname, length); + if (retlength != length) + { + remote_fileio_ioerror (); + return; + } + + /* Only operate on regular files (and directories, which allows to return + the correct return code) */ + if (!stat (pathname, &st) && !S_ISREG (st.st_mode) && !S_ISDIR (st.st_mode)) + { + remote_fileio_reply (-1, FILEIO_ENODEV); + return; + } + + remote_fio_no_longjmp = 1; + ret = unlink (pathname); + + if (ret == -1) + remote_fileio_return_errno (-1); + else + remote_fileio_return_success (ret); +} + +static void +remote_fileio_func_stat (char *buf) +{ + CORE_ADDR ptrval; + int ret, length, retlength; + char *pathname; + LONGEST lnum; + struct stat st; + struct fio_stat fst; + + /* 1. Parameter: Ptr to pathname / length incl. trailing zero */ + if (remote_fileio_extract_ptr_w_len (&buf, &ptrval, &length)) + { + remote_fileio_ioerror (); + return; + } + /* Request pathname using 'm' packet */ + pathname = alloca (length); + retlength = remote_read_bytes (ptrval, pathname, length); + if (retlength != length) + { + remote_fileio_ioerror (); + return; + } + + /* 2. Parameter: Ptr to struct stat */ + if (remote_fileio_extract_long (&buf, &lnum)) + { + remote_fileio_ioerror (); + return; + } + ptrval = (CORE_ADDR) lnum; + + remote_fio_no_longjmp = 1; + ret = stat (pathname, &st); + + if (ret == -1) + { + remote_fileio_return_errno (-1); + return; + } + /* Only operate on regular files and directories */ + if (!ret && !S_ISREG (st.st_mode) && !S_ISDIR (st.st_mode)) + { + remote_fileio_reply (-1, FILEIO_EACCES); + return; + } + if (ptrval) + { + remote_fileio_to_fio_stat (&st, &fst); + remote_fileio_to_fio_uint (0, fst.fst_dev); + + retlength = remote_fileio_write_bytes (ptrval, (char *) &fst, sizeof fst); + if (retlength != sizeof fst) + { + remote_fileio_return_errno (-1); + return; + } + } + remote_fileio_return_success (ret); +} + +static void +remote_fileio_func_fstat (char *buf) +{ + CORE_ADDR ptrval; + int fd, ret, retlength; + long target_fd; + LONGEST lnum; + struct stat st; + struct fio_stat fst; + struct timeval tv; + + /* 1. Parameter: file descriptor */ + if (remote_fileio_extract_int (&buf, &target_fd)) + { + remote_fileio_ioerror (); + return; + } + fd = remote_fileio_map_fd ((int) target_fd); + if (fd == FIO_FD_INVALID) + { + remote_fileio_badfd (); + return; + } + /* 2. Parameter: Ptr to struct stat */ + if (remote_fileio_extract_long (&buf, &lnum)) + { + remote_fileio_ioerror (); + return; + } + ptrval = (CORE_ADDR) lnum; + + remote_fio_no_longjmp = 1; + if (fd == FIO_FD_CONSOLE_IN || fd == FIO_FD_CONSOLE_OUT) + { + remote_fileio_to_fio_uint (1, fst.fst_dev); + st.st_mode = S_IFCHR | (fd == FIO_FD_CONSOLE_IN ? S_IRUSR : S_IWUSR); + st.st_nlink = 1; + st.st_uid = getuid (); + st.st_gid = getgid (); + st.st_rdev = 0; + st.st_size = 0; + st.st_blksize = 512; + st.st_blocks = 0; + if (!gettimeofday (&tv, NULL)) + st.st_atime = st.st_mtime = st.st_ctime = tv.tv_sec; + else + st.st_atime = st.st_mtime = st.st_ctime = (time_t) 0; + ret = 0; + } + else + ret = fstat (fd, &st); + + if (ret == -1) + { + remote_fileio_return_errno (-1); + return; + } + if (ptrval) + { + remote_fileio_to_fio_stat (&st, &fst); + + retlength = remote_fileio_write_bytes (ptrval, (char *) &fst, sizeof fst); + if (retlength != sizeof fst) + { + remote_fileio_return_errno (-1); + return; + } + } + remote_fileio_return_success (ret); +} + +static void +remote_fileio_func_gettimeofday (char *buf) +{ + LONGEST lnum; + CORE_ADDR ptrval; + int ret, retlength; + struct timeval tv; + struct fio_timeval ftv; + + /* 1. Parameter: struct timeval pointer */ + if (remote_fileio_extract_long (&buf, &lnum)) + { + remote_fileio_ioerror (); + return; + } + ptrval = (CORE_ADDR) lnum; + /* 2. Parameter: some pointer value... */ + if (remote_fileio_extract_long (&buf, &lnum)) + { + remote_fileio_ioerror (); + return; + } + /* ...which has to be NULL */ + if (lnum) + { + remote_fileio_reply (-1, FILEIO_EINVAL); + return; + } + + remote_fio_no_longjmp = 1; + ret = gettimeofday (&tv, NULL); + + if (ret == -1) + { + remote_fileio_return_errno (-1); + return; + } + + if (ptrval) + { + remote_fileio_to_fio_timeval (&tv, &ftv); + + retlength = remote_fileio_write_bytes (ptrval, (char *) &ftv, sizeof ftv); + if (retlength != sizeof ftv) + { + remote_fileio_return_errno (-1); + return; + } + } + remote_fileio_return_success (ret); +} + +static void +remote_fileio_func_isatty (char *buf) +{ + long target_fd; + int fd; + + /* Parameter: file descriptor */ + if (remote_fileio_extract_int (&buf, &target_fd)) + { + remote_fileio_ioerror (); + return; + } + remote_fio_no_longjmp = 1; + fd = remote_fileio_map_fd ((int) target_fd); + remote_fileio_return_success (fd == FIO_FD_CONSOLE_IN || + fd == FIO_FD_CONSOLE_OUT ? 1 : 0); +} + +static void +remote_fileio_func_system (char *buf) +{ + CORE_ADDR ptrval; + int ret, length, retlength; + char *cmdline; + + /* Check if system(3) has been explicitely allowed using the + `set remote system-call-allowed 1' command. If not, return + EPERM */ + if (!remote_fio_system_call_allowed) + { + remote_fileio_reply (-1, FILEIO_EPERM); + return; + } + + /* Parameter: Ptr to commandline / length incl. trailing zero */ + if (remote_fileio_extract_ptr_w_len (&buf, &ptrval, &length)) + { + remote_fileio_ioerror (); + return; + } + /* Request commandline using 'm' packet */ + cmdline = alloca (length); + retlength = remote_read_bytes (ptrval, cmdline, length); + if (retlength != length) + { + remote_fileio_ioerror (); + return; + } + + remote_fio_no_longjmp = 1; + ret = system (cmdline); + + if (ret == -1) + remote_fileio_return_errno (-1); + else + remote_fileio_return_success (WEXITSTATUS (ret)); +} + +static struct { + char *name; + void (*func)(char *); +} remote_fio_func_map[] = { + "open", remote_fileio_func_open, + "close", remote_fileio_func_close, + "read", remote_fileio_func_read, + "write", remote_fileio_func_write, + "lseek", remote_fileio_func_lseek, + "rename", remote_fileio_func_rename, + "unlink", remote_fileio_func_unlink, + "stat", remote_fileio_func_stat, + "fstat", remote_fileio_func_fstat, + "gettimeofday", remote_fileio_func_gettimeofday, + "isatty", remote_fileio_func_isatty, + "system", remote_fileio_func_system, + NULL, NULL +}; + +static int +do_remote_fileio_request (struct ui_out *uiout, void *buf_arg) +{ + char *buf = buf_arg; + char *c; + int idx; + + remote_fileio_sig_set (remote_fileio_ctrl_c_signal_handler); + + c = strchr (++buf, ','); + if (c) + *c++ = '\0'; + else + c = strchr (buf, '\0'); + for (idx = 0; remote_fio_func_map[idx].name; ++idx) + if (!strcmp (remote_fio_func_map[idx].name, buf)) + break; + if (!remote_fio_func_map[idx].name) /* ERROR: No such function. */ + return RETURN_ERROR; + remote_fio_func_map[idx].func (c); + return 0; +} + +void +remote_fileio_request (char *buf) +{ + int ex; + + remote_fileio_sig_init (); + + remote_fio_ctrl_c_flag = 0; + remote_fio_no_longjmp = 0; + + ex = catch_exceptions (uiout, do_remote_fileio_request, (void *)buf, + NULL, RETURN_MASK_ALL); + switch (ex) + { + case RETURN_ERROR: + remote_fileio_reply (-1, FILEIO_ENOSYS); + break; + case RETURN_QUIT: + remote_fileio_reply (-1, FILEIO_EINTR); + break; + default: + break; + } + + remote_fileio_sig_exit (); +} + +static void +set_system_call_allowed (char *args, int from_tty) +{ + if (args) + { + char *arg_end; + int val = strtoul (args, &arg_end, 10); + if (*args && *arg_end == '\0') + { + remote_fio_system_call_allowed = !!val; + return; + } + } + error ("Illegal argument for \"set remote system-call-allowed\" command"); +} + +static void +show_system_call_allowed (char *args, int from_tty) +{ + if (args) + error ("Garbage after \"show remote system-call-allowed\" command: `%s'", args); + printf_unfiltered ("Calling host system(3) call from target is %sallowed\n", + remote_fio_system_call_allowed ? "" : "not "); +} + +void +initialize_remote_fileio (struct cmd_list_element *remote_set_cmdlist, + struct cmd_list_element *remote_show_cmdlist) +{ + add_cmd ("system-call-allowed", no_class, + set_system_call_allowed, + "Set if the host system(3) call is allowed for the target.\n", + &remote_set_cmdlist); + add_cmd ("system-call-allowed", no_class, + show_system_call_allowed, + "Show if the host system(3) call is allowed for the target.\n", + &remote_show_cmdlist); +} diff --git a/gdb/remote-fileio.h b/gdb/remote-fileio.h new file mode 100644 index 0000000..68c6450 --- /dev/null +++ b/gdb/remote-fileio.h @@ -0,0 +1,38 @@ +/* Remote File-I/O communications + + Copyright 2003 Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +/* See the GDB User Guide for details of the GDB remote protocol. */ + +#ifndef REMOTE_FILEIO_H +#define REMOTE_FILEIO_H + +struct cmd_list_element; + +/* Unified interface to remote fileio, called in remote.c from + remote_wait () and remote_async_wait () */ +extern void remote_fileio_request (char *buf); + +/* Called from _initialize_remote () */ +extern void initialize_remote_fileio ( + struct cmd_list_element *remote_set_cmdlist, + struct cmd_list_element *remote_show_cmdlist); + +#endif diff --git a/gdb/remote-m32r-sdi.c b/gdb/remote-m32r-sdi.c new file mode 100644 index 0000000..7f0b90c --- /dev/null +++ b/gdb/remote-m32r-sdi.c @@ -0,0 +1,1673 @@ +/* Remote debugging interface for M32R/SDI. + + Copyright 2003 Free Software Foundation, Inc. + + Contributed by Renesas Technology Co. + Written by Kei Sakamoto . + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#include "defs.h" +#include "gdbcmd.h" +#include "gdbcore.h" +#include "inferior.h" +#include "target.h" +#include "regcache.h" +#include "gdb_string.h" +#include +#include +#include +#include +#include +#include +#include + + +#include "serial.h" + +/* Descriptor for I/O to remote machine. */ + +static struct serial *sdi_desc = NULL; + +#define SDI_TIMEOUT 30 + + +#define SDIPORT 3232 + +static char chip_name[64]; + +static int step_mode; +static unsigned long last_pc_addr = 0xffffffff; +static unsigned char last_pc_addr_data[2]; + +static int mmu_on = 0; + +static int use_ib_breakpoints = 1; + +#define MAX_BREAKPOINTS 1024 +static int max_ib_breakpoints; +static unsigned long bp_address[MAX_BREAKPOINTS]; +static unsigned char bp_data[MAX_BREAKPOINTS][4]; +static const unsigned char ib_bp_entry_enable[] = { + 0x00, 0x00, 0x00, 0x06 +}; +static const unsigned char ib_bp_entry_disable[] = { + 0x00, 0x00, 0x00, 0x00 +}; + +/* dbt -> nop */ +static const unsigned char dbt_bp_entry[] = { + 0x10, 0xe0, 0x70, 0x00 +}; + +#define MAX_ACCESS_BREAKS 4 +static int max_access_breaks; +static unsigned long ab_address[MAX_ACCESS_BREAKS]; +static unsigned int ab_type[MAX_ACCESS_BREAKS]; +static unsigned int ab_size[MAX_ACCESS_BREAKS]; +static CORE_ADDR hit_watchpoint_addr = 0; + +static int interrupted = 0; + +/* Forward data declarations */ +extern struct target_ops m32r_ops; + + +/* Commands */ +#define SDI_OPEN 1 +#define SDI_CLOSE 2 +#define SDI_RELEASE 3 +#define SDI_READ_CPU_REG 4 +#define SDI_WRITE_CPU_REG 5 +#define SDI_READ_MEMORY 6 +#define SDI_WRITE_MEMORY 7 +#define SDI_EXEC_CPU 8 +#define SDI_STOP_CPU 9 +#define SDI_WAIT_FOR_READY 10 +#define SDI_GET_ATTR 11 +#define SDI_SET_ATTR 12 +#define SDI_STATUS 13 + +/* Attributes */ +#define SDI_ATTR_NAME 1 +#define SDI_ATTR_BRK 2 +#define SDI_ATTR_ABRK 3 +#define SDI_ATTR_CACHE 4 +#define SDI_CACHE_TYPE_M32102 0 +#define SDI_CACHE_TYPE_CHAOS 1 +#define SDI_ATTR_MEM_ACCESS 5 +#define SDI_MEM_ACCESS_DEBUG_DMA 0 +#define SDI_MEM_ACCESS_MON_CODE 1 + +/* Registers */ +#define SDI_REG_R0 0 +#define SDI_REG_R1 1 +#define SDI_REG_R2 2 +#define SDI_REG_R3 3 +#define SDI_REG_R4 4 +#define SDI_REG_R5 5 +#define SDI_REG_R6 6 +#define SDI_REG_R7 7 +#define SDI_REG_R8 8 +#define SDI_REG_R9 9 +#define SDI_REG_R10 10 +#define SDI_REG_R11 11 +#define SDI_REG_R12 12 +#define SDI_REG_FP 13 +#define SDI_REG_LR 14 +#define SDI_REG_SP 15 +#define SDI_REG_PSW 16 +#define SDI_REG_CBR 17 +#define SDI_REG_SPI 18 +#define SDI_REG_SPU 19 +#define SDI_REG_CR4 20 +#define SDI_REG_EVB 21 +#define SDI_REG_BPC 22 +#define SDI_REG_CR7 23 +#define SDI_REG_BBPSW 24 +#define SDI_REG_CR9 25 +#define SDI_REG_CR10 26 +#define SDI_REG_CR11 27 +#define SDI_REG_CR12 28 +#define SDI_REG_WR 29 +#define SDI_REG_BBPC 30 +#define SDI_REG_PBP 31 +#define SDI_REG_ACCH 32 +#define SDI_REG_ACCL 33 +#define SDI_REG_ACC1H 34 +#define SDI_REG_ACC1L 35 + + +/* Low level communication functions */ + +/* Check an ack packet from the target */ +static int +get_ack (void) +{ + int c; + + if (!sdi_desc) + return -1; + + c = serial_readchar (sdi_desc, SDI_TIMEOUT); + + if (c < 0) + return -1; + + if (c != '+') /* error */ + return -1; + + return 0; +} + +/* Send data to the target and check an ack packet */ +static int +send_data (void *buf, int len) +{ + int ret; + + if (!sdi_desc) + return -1; + + if (serial_write (sdi_desc, buf, len) != 0) + return -1; + + if (get_ack () == -1) + return -1; + + return len; +} + +/* Receive data from the target */ +static int +recv_data (void *buf, int len) +{ + int total = 0; + int c; + + if (!sdi_desc) + return -1; + + while (total < len) + { + c = serial_readchar (sdi_desc, SDI_TIMEOUT); + + if (c < 0) + return -1; + + ((unsigned char *) buf)[total++] = c; + } + + return len; +} + +/* Store unsigned long parameter on packet */ +static void +store_long_parameter (void *buf, long val) +{ + val = htonl (val); + memcpy (buf, &val, 4); +} + +/* Check if MMU is on */ +static void +check_mmu_status (void) +{ + unsigned long val; + unsigned char buf[2]; + + /* Read PC address */ + buf[0] = SDI_READ_CPU_REG; + buf[1] = SDI_REG_BPC; + if (send_data (buf, 2) == -1) + return; + recv_data (&val, 4); + val = ntohl (val); + if ((val & 0xc0000000) == 0x80000000) + { + mmu_on = 1; + return; + } + + /* Read EVB address */ + buf[0] = SDI_READ_CPU_REG; + buf[1] = SDI_REG_EVB; + if (send_data (buf, 2) == -1) + return; + recv_data (&val, 4); + val = ntohl (val); + if ((val & 0xc0000000) == 0x80000000) + { + mmu_on = 1; + return; + } + + mmu_on = 0; +} + + +/* This is called not only when we first attach, but also when the + user types "run" after having attached. */ +static void +m32r_create_inferior (char *execfile, char *args, char **env) +{ + CORE_ADDR entry_pt; + + if (args && *args) + error ("Cannot pass arguments to remote STDEBUG process"); + + if (execfile == 0 || exec_bfd == 0) + error ("No executable file specified"); + + if (remote_debug) + fprintf_unfiltered (gdb_stdlog, "m32r_create_inferior(%s,%s)\n", execfile, + args); + + entry_pt = bfd_get_start_address (exec_bfd); + + /* The "process" (board) is already stopped awaiting our commands, and + the program is already downloaded. We just set its PC and go. */ + + clear_proceed_status (); + + /* Tell wait_for_inferior that we've started a new process. */ + init_wait_for_inferior (); + + /* Set up the "saved terminal modes" of the inferior + based on what modes we are starting it with. */ + target_terminal_init (); + + /* Install inferior's terminal modes. */ + target_terminal_inferior (); + + proceed (entry_pt, TARGET_SIGNAL_DEFAULT, 0); +} + +/* Open a connection to a remote debugger. + NAME is the filename used for communication. */ + +static void +m32r_open (char *args, int from_tty) +{ + struct hostent *host_ent; + struct sockaddr_in server_addr; + char *port_str, hostname[256]; + int port; + unsigned char buf[2]; + int i, n; + int yes = 1; + + if (remote_debug) + fprintf_unfiltered (gdb_stdlog, "m32r_open(%d)\n", from_tty); + + target_preopen (from_tty); + + push_target (&m32r_ops); + + if (args == NULL) + sprintf (hostname, "localhost:%d", SDIPORT); + else + { + port_str = strchr (args, ':'); + if (port_str == NULL) + sprintf (hostname, "%s:%d", args, SDIPORT); + else + strcpy (hostname, args); + } + + sdi_desc = serial_open (hostname); + if (!sdi_desc) + error ("Connection refused\n"); + + if (get_ack () == -1) + error ("Cannot connect to SDI target\n"); + + buf[0] = SDI_OPEN; + if (send_data (buf, 1) == -1) + error ("Cannot connect to SDI target\n"); + + /* Get maximum number of ib breakpoints */ + buf[0] = SDI_GET_ATTR; + buf[1] = SDI_ATTR_BRK; + send_data (buf, 2); + recv_data (buf, 1); + max_ib_breakpoints = buf[0]; + if (remote_debug) + printf_filtered ("Max IB Breakpoints = %d\n", max_ib_breakpoints); + + /* Initialize breakpoints. */ + for (i = 0; i < MAX_BREAKPOINTS; i++) + bp_address[i] = 0xffffffff; + + /* Get maximum number of access breaks. */ + buf[0] = SDI_GET_ATTR; + buf[1] = SDI_ATTR_ABRK; + send_data (buf, 2); + recv_data (buf, 1); + max_access_breaks = buf[0]; + if (remote_debug) + printf_filtered ("Max Access Breaks = %d\n", max_access_breaks); + + /* Initialize access breask. */ + for (i = 0; i < MAX_ACCESS_BREAKS; i++) + ab_address[i] = 0x00000000; + + check_mmu_status (); + + /* Get the name of chip on target board. */ + buf[0] = SDI_GET_ATTR; + buf[1] = SDI_ATTR_NAME; + send_data (buf, 2); + recv_data (chip_name, 64); + + if (from_tty) + printf_filtered ("Remote %s connected to %s\n", target_shortname, + chip_name); +} + +/* Close out all files and local state before this target loses control. */ + +static void +m32r_close (int quitting) +{ + unsigned char buf[1]; + + if (remote_debug) + fprintf_unfiltered (gdb_stdlog, "m32r_close(%d)\n", quitting); + + if (sdi_desc) + { + buf[0] = SDI_CLOSE; + send_data (buf, 1); + serial_close (sdi_desc); + sdi_desc = NULL; + } + + inferior_ptid = null_ptid; + return; +} + +/* Tell the remote machine to resume. */ + +static void +m32r_resume (ptid_t ptid, int step, enum target_signal sig) +{ + unsigned long pc_addr, bp_addr, ab_addr; + unsigned char buf[13]; + int i; + + if (remote_debug) + { + if (step) + fprintf_unfiltered (gdb_stdlog, "\nm32r_resume(step)\n"); + else + fprintf_unfiltered (gdb_stdlog, "\nm32r_resume(cont)\n"); + } + + check_mmu_status (); + + pc_addr = read_pc (); + if (remote_debug) + fprintf_unfiltered (gdb_stdlog, "pc <= 0x%lx\n", pc_addr); + + /* At pc address there is a parallel instruction with +2 offset, + so we have to make it a serial instruction or avoid it. */ + if (pc_addr == last_pc_addr) + { + /* Avoid a parallel nop. */ + if (last_pc_addr_data[0] == 0xf0 && last_pc_addr_data[1] == 0x00) + { + pc_addr += 2; + /* Now we can forget this instruction. */ + last_pc_addr = 0xffffffff; + } + /* Clear a parallel bit. */ + else + { + buf[0] = SDI_WRITE_MEMORY; + if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) + store_long_parameter (buf + 1, pc_addr); + else + store_long_parameter (buf + 1, pc_addr - 1); + store_long_parameter (buf + 5, 1); + buf[9] = last_pc_addr_data[0] & 0x7f; + send_data (buf, 10); + } + } + + /* Set PC. */ + buf[0] = SDI_WRITE_CPU_REG; + buf[1] = SDI_REG_BPC; + store_long_parameter (buf + 2, pc_addr); + send_data (buf, 6); + + /* step mode. */ + step_mode = step; + if (step) + { + /* Set PBP. */ + buf[0] = SDI_WRITE_CPU_REG; + buf[1] = SDI_REG_PBP; + store_long_parameter (buf + 2, pc_addr | 1); + send_data (buf, 6); + } + else + { + int ib_breakpoints; + + if (use_ib_breakpoints) + ib_breakpoints = max_ib_breakpoints; + else + ib_breakpoints = 0; + + /* Set ib breakpoints. */ + for (i = 0; i < ib_breakpoints; i++) + { + bp_addr = bp_address[i]; + if (bp_addr != 0xffffffff && bp_addr != pc_addr) + { + /* Set PBP. */ + buf[0] = SDI_WRITE_MEMORY; + store_long_parameter (buf + 1, 0xffff8000 + 4 * i); + store_long_parameter (buf + 5, 4); + if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) + { + buf[9] = ib_bp_entry_enable[0]; + buf[10] = ib_bp_entry_enable[1]; + buf[11] = ib_bp_entry_enable[2]; + buf[12] = ib_bp_entry_enable[3]; + } + else + { + buf[9] = ib_bp_entry_enable[3]; + buf[10] = ib_bp_entry_enable[2]; + buf[11] = ib_bp_entry_enable[1]; + buf[12] = ib_bp_entry_enable[0]; + } + send_data (buf, 13); + + buf[0] = SDI_WRITE_MEMORY; + store_long_parameter (buf + 1, 0xffff8080 + 4 * i); + store_long_parameter (buf + 5, 4); + store_unsigned_integer (buf + 9, 4, bp_addr); + send_data (buf, 13); + } + } + + /* Set dbt breakpoints. */ + for (i = ib_breakpoints; i < MAX_BREAKPOINTS; i++) + { + bp_addr = bp_address[i]; + if (bp_addr != 0xffffffff && bp_addr != pc_addr) + { + if (!mmu_on) + bp_addr &= 0x7fffffff; + + /* Write DBT instruction. */ + buf[0] = SDI_WRITE_MEMORY; + if ((bp_addr & 2) == 0 && bp_addr != (pc_addr & 0xfffffffc)) + { + store_long_parameter (buf + 1, bp_addr); + store_long_parameter (buf + 5, 4); + if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) + { + buf[9] = dbt_bp_entry[0]; + buf[10] = dbt_bp_entry[1]; + buf[11] = dbt_bp_entry[2]; + buf[12] = dbt_bp_entry[3]; + } + else + { + buf[9] = dbt_bp_entry[3]; + buf[10] = dbt_bp_entry[2]; + buf[11] = dbt_bp_entry[1]; + buf[12] = dbt_bp_entry[0]; + } + send_data (buf, 13); + } + else + { + if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) + store_long_parameter (buf + 1, bp_addr); + else if ((bp_addr & 2) == 0) + store_long_parameter (buf + 1, bp_addr + 2); + else + store_long_parameter (buf + 1, bp_addr - 2); + store_long_parameter (buf + 5, 2); + if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) + { + buf[9] = dbt_bp_entry[0]; + buf[10] = dbt_bp_entry[1]; + } + else + { + buf[9] = dbt_bp_entry[1]; + buf[10] = dbt_bp_entry[0]; + } + send_data (buf, 11); + } + } + } + + /* Set access breaks. */ + for (i = 0; i < max_access_breaks; i++) + { + ab_addr = ab_address[i]; + if (ab_addr != 0x00000000) + { + /* DBC register */ + buf[0] = SDI_WRITE_MEMORY; + store_long_parameter (buf + 1, 0xffff8100 + 4 * i); + store_long_parameter (buf + 5, 4); + if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) + { + buf[9] = 0x00; + buf[10] = 0x00; + buf[11] = 0x00; + switch (ab_type[i]) + { + case 0: /* write watch */ + buf[12] = 0x86; + break; + case 1: /* read watch */ + buf[12] = 0x46; + break; + case 2: /* access watch */ + buf[12] = 0x06; + break; + } + } + else + { + switch (ab_type[i]) + { + case 0: /* write watch */ + buf[9] = 0x86; + break; + case 1: /* read watch */ + buf[9] = 0x46; + break; + case 2: /* access watch */ + buf[9] = 0x06; + break; + } + buf[10] = 0x00; + buf[11] = 0x00; + buf[12] = 0x00; + } + send_data (buf, 13); + + /* DBAH register */ + buf[0] = SDI_WRITE_MEMORY; + store_long_parameter (buf + 1, 0xffff8180 + 4 * i); + store_long_parameter (buf + 5, 4); + store_unsigned_integer (buf + 9, 4, ab_addr); + send_data (buf, 13); + + /* DBAL register */ + buf[0] = SDI_WRITE_MEMORY; + store_long_parameter (buf + 1, 0xffff8200 + 4 * i); + store_long_parameter (buf + 5, 4); + store_long_parameter (buf + 9, 0xffffffff); + send_data (buf, 13); + + /* DBD register */ + buf[0] = SDI_WRITE_MEMORY; + store_long_parameter (buf + 1, 0xffff8280 + 4 * i); + store_long_parameter (buf + 5, 4); + store_long_parameter (buf + 9, 0x00000000); + send_data (buf, 13); + + /* DBDM register */ + buf[0] = SDI_WRITE_MEMORY; + store_long_parameter (buf + 1, 0xffff8300 + 4 * i); + store_long_parameter (buf + 5, 4); + store_long_parameter (buf + 9, 0x00000000); + send_data (buf, 13); + } + } + + /* Unset PBP. */ + buf[0] = SDI_WRITE_CPU_REG; + buf[1] = SDI_REG_PBP; + store_long_parameter (buf + 2, 0x00000000); + send_data (buf, 6); + } + + buf[0] = SDI_EXEC_CPU; + send_data (buf, 1); + + /* Without this, some commands which require an active target (such as kill) + won't work. This variable serves (at least) double duty as both the pid + of the target process (if it has such), and as a flag indicating that a + target is active. These functions should be split out into seperate + variables, especially since GDB will someday have a notion of debugging + several processes. */ + inferior_ptid = pid_to_ptid (32); + + return; +} + +/* Wait until the remote machine stops, then return, + storing status in STATUS just as `wait' would. */ + +static void +gdb_cntrl_c (int signo) +{ + if (remote_debug) + fprintf_unfiltered (gdb_stdlog, "interrupt\n"); + interrupted = 1; +} + +static ptid_t +m32r_wait (ptid_t ptid, struct target_waitstatus *status) +{ + static RETSIGTYPE (*prev_sigint) (); + unsigned long bp_addr, pc_addr; + long i; + unsigned char buf[13]; + unsigned long val; + int ret, c; + + if (remote_debug) + fprintf_unfiltered (gdb_stdlog, "m32r_wait()\n"); + + status->kind = TARGET_WAITKIND_EXITED; + status->value.sig = 0; + + interrupted = 0; + prev_sigint = signal (SIGINT, gdb_cntrl_c); + + /* Wait for ready */ + buf[0] = SDI_WAIT_FOR_READY; + if (serial_write (sdi_desc, buf, 1) != 0) + error ("Remote connection closed"); + + while (1) + { + c = serial_readchar (sdi_desc, SDI_TIMEOUT); + if (c < 0) + error ("Remote connection closed"); + + if (c == '-') /* error */ + { + status->kind = TARGET_WAITKIND_STOPPED; + status->value.sig = TARGET_SIGNAL_HUP; + return inferior_ptid; + } + else if (c == '+') /* stopped */ + break; + + if (interrupted) + ret = serial_write (sdi_desc, "!", 1); /* packet to interrupt */ + else + ret = serial_write (sdi_desc, ".", 1); /* packet to wait */ + if (ret != 0) + error ("Remote connection closed"); + } + + status->kind = TARGET_WAITKIND_STOPPED; + if (interrupted) + status->value.sig = TARGET_SIGNAL_INT; + else + status->value.sig = TARGET_SIGNAL_TRAP; + + interrupted = 0; + signal (SIGINT, prev_sigint); + + check_mmu_status (); + + /* Recover parallel bit. */ + if (last_pc_addr != 0xffffffff) + { + buf[0] = SDI_WRITE_MEMORY; + if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) + store_long_parameter (buf + 1, last_pc_addr); + else + store_long_parameter (buf + 1, last_pc_addr - 1); + store_long_parameter (buf + 5, 1); + buf[9] = last_pc_addr_data[0]; + send_data (buf, 10); + last_pc_addr = 0xffffffff; + } + + /* Breakpoints are inserted only for "next" command */ + if (!step_mode) + { + int ib_breakpoints; + + if (use_ib_breakpoints) + ib_breakpoints = max_ib_breakpoints; + else + ib_breakpoints = 0; + + /* Set back pc by 2 if m32r is stopped with dbt. */ + buf[0] = SDI_READ_CPU_REG; + buf[1] = SDI_REG_BPC; + send_data (buf, 2); + recv_data (&val, 4); + pc_addr = ntohl (val) - 2; + for (i = ib_breakpoints; i < MAX_BREAKPOINTS; i++) + { + if (pc_addr == bp_address[i]) + { + buf[0] = SDI_WRITE_CPU_REG; + buf[1] = SDI_REG_BPC; + store_long_parameter (buf + 2, pc_addr); + send_data (buf, 6); + + /* If there is a parallel instruction with +2 offset at pc + address, we have to take care of it later. */ + if ((pc_addr & 0x2) != 0) + { + if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) + { + if ((bp_data[i][2] & 0x80) != 0) + { + last_pc_addr = pc_addr; + last_pc_addr_data[0] = bp_data[i][2]; + last_pc_addr_data[1] = bp_data[i][3]; + } + } + else + { + if ((bp_data[i][1] & 0x80) != 0) + { + last_pc_addr = pc_addr; + last_pc_addr_data[0] = bp_data[i][1]; + last_pc_addr_data[1] = bp_data[i][0]; + } + } + } + break; + } + } + + /* Remove ib breakpoints. */ + for (i = 0; i < ib_breakpoints; i++) + { + if (bp_address[i] != 0xffffffff) + { + buf[0] = SDI_WRITE_MEMORY; + store_long_parameter (buf + 1, 0xffff8000 + 4 * i); + store_long_parameter (buf + 5, 4); + buf[9] = ib_bp_entry_disable[0]; + buf[10] = ib_bp_entry_disable[1]; + buf[11] = ib_bp_entry_disable[2]; + buf[12] = ib_bp_entry_disable[3]; + send_data (buf, 13); + } + } + /* Remove dbt breakpoints. */ + for (i = ib_breakpoints; i < MAX_BREAKPOINTS; i++) + { + bp_addr = bp_address[i]; + if (bp_addr != 0xffffffff) + { + if (!mmu_on) + bp_addr &= 0x7fffffff; + buf[0] = SDI_WRITE_MEMORY; + store_long_parameter (buf + 1, bp_addr & 0xfffffffc); + store_long_parameter (buf + 5, 4); + buf[9] = bp_data[i][0]; + buf[10] = bp_data[i][1]; + buf[11] = bp_data[i][2]; + buf[12] = bp_data[i][3]; + send_data (buf, 13); + } + } + + /* Remove access breaks. */ + hit_watchpoint_addr = 0; + for (i = 0; i < max_access_breaks; i++) + { + if (ab_address[i] != 0x00000000) + { + buf[0] = SDI_READ_MEMORY; + store_long_parameter (buf + 1, 0xffff8100 + 4 * i); + store_long_parameter (buf + 5, 4); + serial_write (sdi_desc, buf, 9); + c = serial_readchar (sdi_desc, SDI_TIMEOUT); + if (c != '-' && recv_data (buf, 4) != -1) + { + if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) + { + if ((buf[3] & 0x1) == 0x1) + hit_watchpoint_addr = ab_address[i]; + } + else + { + if ((buf[0] & 0x1) == 0x1) + hit_watchpoint_addr = ab_address[i]; + } + } + + buf[0] = SDI_WRITE_MEMORY; + store_long_parameter (buf + 1, 0xffff8100 + 4 * i); + store_long_parameter (buf + 5, 4); + store_long_parameter (buf + 9, 0x00000000); + send_data (buf, 13); + } + } + + if (remote_debug) + fprintf_unfiltered (gdb_stdlog, "pc => 0x%lx\n", pc_addr); + } + else + last_pc_addr = 0xffffffff; + + return inferior_ptid; +} + +/* Terminate the open connection to the remote debugger. + Use this when you want to detach and do something else + with your gdb. */ +static void +m32r_detach (char *args, int from_tty) +{ + if (remote_debug) + fprintf_unfiltered (gdb_stdlog, "m32r_detach(%d)\n", from_tty); + + m32r_resume (inferior_ptid, 0, 0); + + /* calls m32r_close to do the real work */ + pop_target (); + if (from_tty) + fprintf_unfiltered (gdb_stdlog, "Ending remote %s debugging\n", + target_shortname); +} + +/* Return the id of register number REGNO. */ + +static int +get_reg_id (int regno) +{ + switch (regno) + { + case 20: + return SDI_REG_BBPC; + case 21: + return SDI_REG_BPC; + case 22: + return SDI_REG_ACCL; + case 23: + return SDI_REG_ACCH; + case 24: + return SDI_REG_EVB; + } + + return regno; +} + +/* Read the remote registers into the block REGS. */ + +static void m32r_fetch_register (int); + +static void +m32r_fetch_registers (void) +{ + int regno; + + for (regno = 0; regno < NUM_REGS; regno++) + m32r_fetch_register (regno); +} + +/* Fetch register REGNO, or all registers if REGNO is -1. + Returns errno value. */ +static void +m32r_fetch_register (int regno) +{ + unsigned long val, val2, regid; + unsigned char buf[2]; + + if (regno == -1) + m32r_fetch_registers (); + else + { + char buffer[MAX_REGISTER_SIZE]; + + regid = get_reg_id (regno); + buf[0] = SDI_READ_CPU_REG; + buf[1] = regid; + send_data (buf, 2); + recv_data (&val, 4); + val = ntohl (val); + + if (regid == SDI_REG_PSW) + { + buf[0] = SDI_READ_CPU_REG; + buf[1] = SDI_REG_BBPSW; + send_data (buf, 2); + recv_data (&val2, 4); + val2 = ntohl (val2); + val = ((0x00c1 & val2) << 8) | ((0xc100 & val) >> 8); + } + + if (remote_debug) + fprintf_unfiltered (gdb_stdlog, "m32r_fetch_register(%d,0x%08lx)\n", + regno, val); + + /* We got the number the register holds, but gdb expects to see a + value in the target byte ordering. */ + store_unsigned_integer (buffer, 4, val); + supply_register (regno, buffer); + } + return; +} + +/* Store the remote registers from the contents of the block REGS. */ + +static void m32r_store_register (int); + +static void +m32r_store_registers (void) +{ + int regno; + + for (regno = 0; regno < NUM_REGS; regno++) + m32r_store_register (regno); + + registers_changed (); +} + +/* Store register REGNO, or all if REGNO == 0. + Return errno value. */ +static void +m32r_store_register (int regno) +{ + int regid; + ULONGEST regval, tmp; + unsigned char buf[6]; + + if (regno == -1) + m32r_store_registers (); + else + { + regcache_cooked_read_unsigned (current_regcache, regno, ®val); + regid = get_reg_id (regno); + + if (regid == SDI_REG_PSW) + { + unsigned long psw, bbpsw; + + buf[0] = SDI_READ_CPU_REG; + buf[1] = SDI_REG_PSW; + send_data (buf, 2); + recv_data (&psw, 4); + psw = ntohl (psw); + + buf[0] = SDI_READ_CPU_REG; + buf[1] = SDI_REG_BBPSW; + send_data (buf, 2); + recv_data (&bbpsw, 4); + bbpsw = ntohl (bbpsw); + + tmp = (0x00c1 & psw) | ((0x00c1 & regval) << 8); + buf[0] = SDI_WRITE_CPU_REG; + buf[1] = SDI_REG_PSW; + store_long_parameter (buf + 2, tmp); + send_data (buf, 6); + + tmp = (0x0030 & bbpsw) | ((0xc100 & regval) >> 8); + buf[0] = SDI_WRITE_CPU_REG; + buf[1] = SDI_REG_BBPSW; + store_long_parameter (buf + 2, tmp); + send_data (buf, 6); + } + else + { + buf[0] = SDI_WRITE_CPU_REG; + buf[1] = regid; + store_long_parameter (buf + 2, regval); + send_data (buf, 6); + } + + if (remote_debug) + fprintf_unfiltered (gdb_stdlog, "m32r_store_register(%d,0x%08lu)\n", + regno, (unsigned long) regval); + } +} + +/* Get ready to modify the registers array. On machines which store + individual registers, this doesn't need to do anything. On machines + which store all the registers in one fell swoop, this makes sure + that registers contains all the registers from the program being + debugged. */ + +static void +m32r_prepare_to_store (void) +{ + /* Do nothing, since we can store individual regs */ + if (remote_debug) + fprintf_unfiltered (gdb_stdlog, "m32r_prepare_to_store()\n"); +} + +static void +m32r_files_info (struct target_ops *target) +{ + char *file = "nothing"; + + if (exec_bfd) + { + file = bfd_get_filename (exec_bfd); + printf_filtered ("\tAttached to %s running program %s\n", + chip_name, file); + } +} + +/* Read/Write memory. */ +static int +m32r_xfer_memory (CORE_ADDR memaddr, char *myaddr, int len, + int write, + struct mem_attrib *attrib, struct target_ops *target) +{ + unsigned long taddr; + unsigned char buf[0x2000]; + int ret, c; + + taddr = memaddr; + + if (!mmu_on) + { + if ((taddr & 0xa0000000) == 0x80000000) + taddr &= 0x7fffffff; + } + + if (remote_debug) + { + if (write) + fprintf_unfiltered (gdb_stdlog, "m32r_xfer_memory(%08lx,%d,write)\n", + memaddr, len); + else + fprintf_unfiltered (gdb_stdlog, "m32r_xfer_memory(%08lx,%d,read)\n", + memaddr, len); + } + + if (write) + { + buf[0] = SDI_WRITE_MEMORY; + store_long_parameter (buf + 1, taddr); + store_long_parameter (buf + 5, len); + if (len < 0x1000) + { + memcpy (buf + 9, myaddr, len); + ret = send_data (buf, len + 9) - 9; + } + else + { + if (serial_write (sdi_desc, buf, 9) != 0) + { + if (remote_debug) + fprintf_unfiltered (gdb_stdlog, + "m32r_xfer_memory() failed\n"); + return 0; + } + ret = send_data (myaddr, len); + } + } + else + { + buf[0] = SDI_READ_MEMORY; + store_long_parameter (buf + 1, taddr); + store_long_parameter (buf + 5, len); + if (serial_write (sdi_desc, buf, 9) != 0) + { + if (remote_debug) + fprintf_unfiltered (gdb_stdlog, "m32r_xfer_memory() failed\n"); + return 0; + } + + c = serial_readchar (sdi_desc, SDI_TIMEOUT); + if (c < 0 || c == '-') + { + if (remote_debug) + fprintf_unfiltered (gdb_stdlog, "m32r_xfer_memory() failed\n"); + return 0; + } + + ret = recv_data (myaddr, len); + } + + if (ret <= 0) + { + if (remote_debug) + fprintf_unfiltered (gdb_stdlog, "m32r_xfer_memory() fails\n"); + return 0; + } + + return ret; +} + +static void +m32r_kill (void) +{ + if (remote_debug) + fprintf_unfiltered (gdb_stdlog, "m32r_kill()\n"); + + inferior_ptid = null_ptid; + + return; +} + +/* Clean up when a program exits. + + The program actually lives on in the remote processor's RAM, and may be + run again without a download. Don't leave it full of breakpoint + instructions. */ + +static void +m32r_mourn_inferior (void) +{ + if (remote_debug) + fprintf_unfiltered (gdb_stdlog, "m32r_mourn_inferior()\n"); + + remove_breakpoints (); + generic_mourn_inferior (); +} + +static int +m32r_insert_breakpoint (CORE_ADDR addr, char *shadow) +{ + int ib_breakpoints; + unsigned char buf[13]; + int i, c; + + if (remote_debug) + fprintf_unfiltered (gdb_stdlog, "m32r_insert_breakpoint(%08lx,\"%s\")\n", + addr, shadow); + + if (use_ib_breakpoints) + ib_breakpoints = max_ib_breakpoints; + else + ib_breakpoints = 0; + + for (i = 0; i < MAX_BREAKPOINTS; i++) + { + if (bp_address[i] == 0xffffffff) + { + bp_address[i] = addr; + if (i >= ib_breakpoints) + { + buf[0] = SDI_READ_MEMORY; + if (mmu_on) + store_long_parameter (buf + 1, addr & 0xfffffffc); + else + store_long_parameter (buf + 1, addr & 0x7ffffffc); + store_long_parameter (buf + 5, 4); + serial_write (sdi_desc, buf, 9); + c = serial_readchar (sdi_desc, SDI_TIMEOUT); + if (c != '-') + recv_data (bp_data[i], 4); + } + return 0; + } + } + + error ("Too many breakpoints"); + return 1; +} + +static int +m32r_remove_breakpoint (CORE_ADDR addr, char *shadow) +{ + int i; + + if (remote_debug) + fprintf_unfiltered (gdb_stdlog, "m32r_remove_breakpoint(%08lx,\"%s\")\n", + addr, shadow); + + for (i = 0; i < MAX_BREAKPOINTS; i++) + { + if (bp_address[i] == addr) + { + bp_address[i] = 0xffffffff; + break; + } + } + + return 0; +} + +static void +m32r_load (char *args, int from_tty) +{ + struct cleanup *old_chain; + asection *section; + bfd *pbfd; + bfd_vma entry; + char *filename; + int quiet; + int nostart; + time_t start_time, end_time; /* Start and end times of download */ + unsigned long data_count; /* Number of bytes transferred to memory */ + int ret; + static RETSIGTYPE (*prev_sigint) (); + + /* for direct tcp connections, we can do a fast binary download */ + quiet = 0; + nostart = 0; + filename = NULL; + + while (*args != '\000') + { + char *arg; + + while (isspace (*args)) + args++; + + arg = args; + + while ((*args != '\000') && !isspace (*args)) + args++; + + if (*args != '\000') + *args++ = '\000'; + + if (*arg != '-') + filename = arg; + else if (strncmp (arg, "-quiet", strlen (arg)) == 0) + quiet = 1; + else if (strncmp (arg, "-nostart", strlen (arg)) == 0) + nostart = 1; + else + error ("Unknown option `%s'", arg); + } + + if (!filename) + filename = get_exec_file (1); + + pbfd = bfd_openr (filename, gnutarget); + if (pbfd == NULL) + { + perror_with_name (filename); + return; + } + old_chain = make_cleanup_bfd_close (pbfd); + + if (!bfd_check_format (pbfd, bfd_object)) + error ("\"%s\" is not an object file: %s", filename, + bfd_errmsg (bfd_get_error ())); + + start_time = time (NULL); + data_count = 0; + + interrupted = 0; + prev_sigint = signal (SIGINT, gdb_cntrl_c); + + for (section = pbfd->sections; section; section = section->next) + { + if (bfd_get_section_flags (pbfd, section) & SEC_LOAD) + { + bfd_vma section_address; + bfd_size_type section_size; + file_ptr fptr; + int n; + + section_address = bfd_section_lma (pbfd, section); + section_size = bfd_get_section_size_before_reloc (section); + + if (!mmu_on) + { + if ((section_address & 0xa0000000) == 0x80000000) + section_address &= 0x7fffffff; + } + + if (!quiet) + printf_filtered ("[Loading section %s at 0x%lx (%d bytes)]\n", + bfd_get_section_name (pbfd, section), + section_address, (int) section_size); + + fptr = 0; + + data_count += section_size; + + n = 0; + while (section_size > 0) + { + char unsigned buf[0x1000 + 9]; + int count; + + count = min (section_size, 0x1000); + + buf[0] = SDI_WRITE_MEMORY; + store_long_parameter (buf + 1, section_address); + store_long_parameter (buf + 5, count); + + bfd_get_section_contents (pbfd, section, buf + 9, fptr, count); + if (send_data (buf, count + 9) <= 0) + error ("Error while downloading %s section.", + bfd_get_section_name (pbfd, section)); + + if (!quiet) + { + printf_unfiltered ("."); + if (n++ > 60) + { + printf_unfiltered ("\n"); + n = 0; + } + gdb_flush (gdb_stdout); + } + + section_address += count; + fptr += count; + section_size -= count; + + if (interrupted) + break; + } + + if (!quiet && !interrupted) + { + printf_unfiltered ("done.\n"); + gdb_flush (gdb_stdout); + } + } + + if (interrupted) + { + printf_unfiltered ("Interrupted.\n"); + break; + } + } + + interrupted = 0; + signal (SIGINT, prev_sigint); + + end_time = time (NULL); + + /* Make the PC point at the start address */ + if (exec_bfd) + write_pc (bfd_get_start_address (exec_bfd)); + + inferior_ptid = null_ptid; /* No process now */ + + /* This is necessary because many things were based on the PC at the time + that we attached to the monitor, which is no longer valid now that we + have loaded new code (and just changed the PC). Another way to do this + might be to call normal_stop, except that the stack may not be valid, + and things would get horribly confused... */ + + clear_symtab_users (); + + if (!nostart) + { + entry = bfd_get_start_address (pbfd); + + if (!quiet) + printf_unfiltered ("[Starting %s at 0x%lx]\n", filename, entry); + } + + print_transfer_performance (gdb_stdout, data_count, 0, + end_time - start_time); + + do_cleanups (old_chain); +} + +static void +m32r_stop (void) +{ + unsigned char buf[1]; + + if (remote_debug) + fprintf_unfiltered (gdb_stdlog, "m32r_stop()\n"); + + buf[0] = SDI_STOP_CPU; + send_data (buf, 1); + + return; +} + + +/* Tell whether this target can support a hardware breakpoint. + This implements the TARGET_CAN_USE_HARDWARE_WATCHPOINT macro. */ + +int +m32r_can_use_hardware_watchpoint (void) +{ + return max_access_breaks; +} + +/* Set a data watchpoint. ADDR and LEN should be obvious. TYPE is 0 + for a write watchpoint, 1 for a read watchpoint, or 2 for a read/write + watchpoint. */ + +int +m32r_set_watchpoint (CORE_ADDR addr, int len, int type) +{ + int i; + + if (remote_debug) + fprintf_unfiltered (gdb_stdlog, "m32r_set_watchpoint(%08lx,%d,%d)\n", + addr, len, type); + + for (i = 0; i < MAX_ACCESS_BREAKS; i++) + { + if (ab_address[i] == 0x00000000) + { + ab_address[i] = addr; + ab_size[i] = len; + ab_type[i] = type; + return 0; + } + } + + error ("Too many watchpoints"); + return 1; +} + +int +m32r_remove_watchpoint (CORE_ADDR addr, int len, int type) +{ + int i; + + if (remote_debug) + fprintf_unfiltered (gdb_stdlog, "m32r_remove_watchpoint(%08lx,%d,%d)\n", + addr, len, type); + + for (i = 0; i < MAX_ACCESS_BREAKS; i++) + { + if (ab_address[i] == addr) + { + ab_address[i] = 0x00000000; + break; + } + } + + return 0; +} + +CORE_ADDR +m32r_stopped_data_address (void) +{ + return hit_watchpoint_addr; +} + +int +m32r_stopped_by_watchpoint (void) +{ + return (hit_watchpoint_addr != 0x00000000); +} + + +static void +sdireset_command (char *args, int from_tty) +{ + unsigned char buf[1]; + + if (remote_debug) + fprintf_unfiltered (gdb_stdlog, "m32r_sdireset()\n"); + + buf[0] = SDI_OPEN; + send_data (buf, 1); + + inferior_ptid = null_ptid; +} + + +static void +sdistatus_command (char *args, int from_tty) +{ + unsigned char buf[4096]; + int i, c; + + if (remote_debug) + fprintf_unfiltered (gdb_stdlog, "m32r_sdireset()\n"); + + if (!sdi_desc) + return; + + buf[0] = SDI_STATUS; + send_data (buf, 1); + for (i = 0; i < 4096; i++) + { + c = serial_readchar (sdi_desc, SDI_TIMEOUT); + if (c < 0) + return; + buf[i] = c; + if (c == 0) + break; + } + + printf_filtered ("%s", buf); +} + + +static void +debug_chaos_command (char *args, int from_tty) +{ + unsigned char buf[3]; + + buf[0] = SDI_SET_ATTR; + buf[1] = SDI_ATTR_CACHE; + buf[2] = SDI_CACHE_TYPE_CHAOS; + send_data (buf, 3); +} + + +static void +use_debug_dma_command (char *args, int from_tty) +{ + unsigned char buf[3]; + + buf[0] = SDI_SET_ATTR; + buf[1] = SDI_ATTR_MEM_ACCESS; + buf[2] = SDI_MEM_ACCESS_DEBUG_DMA; + send_data (buf, 3); +} + +static void +use_mon_code_command (char *args, int from_tty) +{ + unsigned char buf[3]; + + buf[0] = SDI_SET_ATTR; + buf[1] = SDI_ATTR_MEM_ACCESS; + buf[2] = SDI_MEM_ACCESS_MON_CODE; + send_data (buf, 3); +} + + +static void +use_ib_breakpoints_command (char *args, int from_tty) +{ + use_ib_breakpoints = 1; +} + +static void +use_dbt_breakpoints_command (char *args, int from_tty) +{ + use_ib_breakpoints = 0; +} + + +/* Define the target subroutine names */ + +struct target_ops m32r_ops; + +static void +init_m32r_ops (void) +{ + m32r_ops.to_shortname = "m32rsdi"; + m32r_ops.to_longname = "Remote M32R debugging over SDI interface"; + m32r_ops.to_doc = "Use an M32R board using SDI debugging protocol."; + m32r_ops.to_open = m32r_open; + m32r_ops.to_close = m32r_close; + m32r_ops.to_detach = m32r_detach; + m32r_ops.to_resume = m32r_resume; + m32r_ops.to_wait = m32r_wait; + m32r_ops.to_fetch_registers = m32r_fetch_register; + m32r_ops.to_store_registers = m32r_store_register; + m32r_ops.to_prepare_to_store = m32r_prepare_to_store; + m32r_ops.to_xfer_memory = m32r_xfer_memory; + m32r_ops.to_files_info = m32r_files_info; + m32r_ops.to_insert_breakpoint = m32r_insert_breakpoint; + m32r_ops.to_remove_breakpoint = m32r_remove_breakpoint; + m32r_ops.to_kill = m32r_kill; + m32r_ops.to_load = m32r_load; + m32r_ops.to_create_inferior = m32r_create_inferior; + m32r_ops.to_mourn_inferior = m32r_mourn_inferior; + m32r_ops.to_stop = m32r_stop; + m32r_ops.to_stratum = process_stratum; + m32r_ops.to_has_all_memory = 1; + m32r_ops.to_has_memory = 1; + m32r_ops.to_has_stack = 1; + m32r_ops.to_has_registers = 1; + m32r_ops.to_has_execution = 1; + m32r_ops.to_magic = OPS_MAGIC; +}; + + +extern initialize_file_ftype _initialize_remote_m32r; + +void +_initialize_remote_m32r (void) +{ + int i; + + init_m32r_ops (); + + /* Initialize breakpoints. */ + for (i = 0; i < MAX_BREAKPOINTS; i++) + bp_address[i] = 0xffffffff; + + /* Initialize access breaks. */ + for (i = 0; i < MAX_ACCESS_BREAKS; i++) + ab_address[i] = 0x00000000; + + add_target (&m32r_ops); + + add_com ("sdireset", class_obscure, sdireset_command, + "Reset SDI connection."); + + add_com ("sdistatus", class_obscure, sdistatus_command, + "Show status of SDI connection."); + + add_com ("debug_chaos", class_obscure, debug_chaos_command, + "Debug M32R/Chaos."); + + add_com ("use_debug_dma", class_obscure, use_debug_dma_command, + "Use debug DMA mem access."); + add_com ("use_mon_code", class_obscure, use_mon_code_command, + "Use mon code mem access."); + + add_com ("use_ib_break", class_obscure, use_ib_breakpoints_command, + "Set breakpoints by IB break."); + add_com ("use_dbt_break", class_obscure, use_dbt_breakpoints_command, + "Set breakpoints by dbt."); +} diff --git a/gdb/sentinel-frame.c b/gdb/sentinel-frame.c new file mode 100644 index 0000000..94c1ee3 --- /dev/null +++ b/gdb/sentinel-frame.c @@ -0,0 +1,92 @@ +/* Code dealing with register stack frames, for GDB, the GNU debugger. + + Copyright 1986, 1987, 1988, 1989, 1990, 1991, 1992, 1993, 1994, + 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software + Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + + +#include "defs.h" +#include "regcache.h" +#include "sentinel-frame.h" +#include "inferior.h" +#include "frame-unwind.h" + +struct frame_unwind_cache +{ + struct regcache *regcache; +}; + +void * +sentinel_frame_cache (struct regcache *regcache) +{ + struct frame_unwind_cache *cache = + FRAME_OBSTACK_ZALLOC (struct frame_unwind_cache); + cache->regcache = regcache; + return cache; +} + +/* Here the register value is taken direct from the register cache. */ + +static void +sentinel_frame_prev_register (struct frame_info *next_frame, + void **this_prologue_cache, + int regnum, int *optimized, + enum lval_type *lvalp, CORE_ADDR *addrp, + int *realnum, void *bufferp) +{ + struct frame_unwind_cache *cache = *this_prologue_cache; + /* Describe the register's location. A reg-frame maps all registers + onto the corresponding hardware register. */ + *optimized = 0; + *lvalp = lval_register; + *addrp = register_offset_hack (current_gdbarch, regnum); + *realnum = regnum; + + /* If needed, find and return the value of the register. */ + if (bufferp != NULL) + { + /* Return the actual value. */ + /* Use the regcache_cooked_read() method so that it, on the fly, + constructs either a raw or pseudo register from the raw + register cache. */ + regcache_cooked_read (cache->regcache, regnum, bufferp); + } +} + +static void +sentinel_frame_this_id (struct frame_info *next_frame, + void **this_prologue_cache, + struct frame_id *this_id) +{ + /* The sentinel frame is used as a starting point for creating the + previous (inner most) frame. That frame's THIS_ID method will be + called to determine the inner most frame's ID. Not this one. */ + internal_error (__FILE__, __LINE__, "sentinel_frame_this_id called"); +} + +const struct frame_unwind sentinel_frame_unwinder = +{ + /* Should the sentinel frame be given a special type? */ + NORMAL_FRAME, + sentinel_frame_this_id, + sentinel_frame_prev_register +}; + +const struct frame_unwind *const sentinel_frame_unwind = &sentinel_frame_unwinder; diff --git a/gdb/sentinel-frame.h b/gdb/sentinel-frame.h new file mode 100644 index 0000000..9b69f42 --- /dev/null +++ b/gdb/sentinel-frame.h @@ -0,0 +1,41 @@ +/* Code dealing with register stack frames, for GDB, the GNU debugger. + + Copyright 2003 Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#if !defined (SENTINEL_FRAME_H) +#define SENTINEL_FRAME_H 1 + +struct frame_unwind; +struct regcache; + +/* Implement the sentinel frame. The sentinel frame terminates the + inner most end of the frame chain. If unwound, it returns the + information need to construct an inner-most frame. */ + +/* Pump prime the sentinel frame's cache. Since this needs the + REGCACHE provide that here. */ + +extern void *sentinel_frame_cache (struct regcache *regcache); + +/* At present there is only one type of sentinel frame. */ + +extern const struct frame_unwind *const sentinel_frame_unwind; + +#endif /* !defined (SENTINEL_FRAME_H) */ diff --git a/gdb/sh64-tdep.c b/gdb/sh64-tdep.c new file mode 100644 index 0000000..ac080ac --- /dev/null +++ b/gdb/sh64-tdep.c @@ -0,0 +1,2904 @@ +/* Target-dependent code for Renesas Super-H, for GDB. + Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 + Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +/* + Contributed by Steve Chamberlain + sac@cygnus.com + */ + +#include "defs.h" +#include "frame.h" +#include "symtab.h" +#include "symfile.h" +#include "gdbtypes.h" +#include "gdbcmd.h" +#include "gdbcore.h" +#include "value.h" +#include "dis-asm.h" +#include "inferior.h" +#include "gdb_string.h" +#include "arch-utils.h" +#include "floatformat.h" +#include "regcache.h" +#include "doublest.h" +#include "osabi.h" + +#include "elf-bfd.h" +#include "solib-svr4.h" + +/* sh flags */ +#include "elf/sh.h" +/* registers numbers shared with the simulator */ +#include "gdb/sim-sh.h" + +/* Information that is dependent on the processor variant. */ +enum sh_abi + { + SH_ABI_UNKNOWN, + SH_ABI_32, + SH_ABI_64 + }; + +struct gdbarch_tdep + { + enum sh_abi sh_abi; + }; + +/* Registers of SH5 */ +enum + { + R0_REGNUM = 0, + DEFAULT_RETURN_REGNUM = 2, + STRUCT_RETURN_REGNUM = 2, + ARG0_REGNUM = 2, + ARGLAST_REGNUM = 9, + FLOAT_ARGLAST_REGNUM = 11, + PR_REGNUM = 18, + SR_REGNUM = 65, + DR0_REGNUM = 141, + DR_LAST_REGNUM = 172, + /* FPP stands for Floating Point Pair, to avoid confusion with + GDB's FP0_REGNUM, which is the number of the first Floating + point register. Unfortunately on the sh5, the floating point + registers are called FR, and the floating point pairs are called FP. */ + FPP0_REGNUM = 173, + FPP_LAST_REGNUM = 204, + FV0_REGNUM = 205, + FV_LAST_REGNUM = 220, + R0_C_REGNUM = 221, + R_LAST_C_REGNUM = 236, + PC_C_REGNUM = 237, + GBR_C_REGNUM = 238, + MACH_C_REGNUM = 239, + MACL_C_REGNUM = 240, + PR_C_REGNUM = 241, + T_C_REGNUM = 242, + FPSCR_C_REGNUM = 243, + FPUL_C_REGNUM = 244, + FP0_C_REGNUM = 245, + FP_LAST_C_REGNUM = 260, + DR0_C_REGNUM = 261, + DR_LAST_C_REGNUM = 268, + FV0_C_REGNUM = 269, + FV_LAST_C_REGNUM = 272, + FPSCR_REGNUM = SIM_SH64_FPCSR_REGNUM, + SSR_REGNUM = SIM_SH64_SSR_REGNUM, + SPC_REGNUM = SIM_SH64_SPC_REGNUM, + TR7_REGNUM = SIM_SH64_TR0_REGNUM + 7, + FP_LAST_REGNUM = SIM_SH64_FR0_REGNUM + SIM_SH64_NR_FP_REGS - 1 + }; + + +/* Define other aspects of the stack frame. + we keep a copy of the worked out return pc lying around, since it + is a useful bit of info */ + +struct frame_extra_info +{ + CORE_ADDR return_pc; + int leaf_function; + int f_offset; +}; + +static const char * +sh64_register_name (int reg_nr) +{ + static char *register_names[] = + { + /* SH MEDIA MODE (ISA 32) */ + /* general registers (64-bit) 0-63 */ + "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", + "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", + "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", + "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", + "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", + "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", + "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", + "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63", + + /* pc (64-bit) 64 */ + "pc", + + /* status reg., saved status reg., saved pc reg. (64-bit) 65-67 */ + "sr", "ssr", "spc", + + /* target registers (64-bit) 68-75*/ + "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7", + + /* floating point state control register (32-bit) 76 */ + "fpscr", + + /* single precision floating point registers (32-bit) 77-140*/ + "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", + "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", + "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23", + "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31", + "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39", + "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47", + "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55", + "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63", + + /* double precision registers (pseudo) 141-172 */ + "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14", + "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30", + "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46", + "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62", + + /* floating point pairs (pseudo) 173-204*/ + "fp0", "fp2", "fp4", "fp6", "fp8", "fp10", "fp12", "fp14", + "fp16", "fp18", "fp20", "fp22", "fp24", "fp26", "fp28", "fp30", + "fp32", "fp34", "fp36", "fp38", "fp40", "fp42", "fp44", "fp46", + "fp48", "fp50", "fp52", "fp54", "fp56", "fp58", "fp60", "fp62", + + /* floating point vectors (4 floating point regs) (pseudo) 205-220*/ + "fv0", "fv4", "fv8", "fv12", "fv16", "fv20", "fv24", "fv28", + "fv32", "fv36", "fv40", "fv44", "fv48", "fv52", "fv56", "fv60", + + /* SH COMPACT MODE (ISA 16) (all pseudo) 221-272*/ + "r0_c", "r1_c", "r2_c", "r3_c", "r4_c", "r5_c", "r6_c", "r7_c", + "r8_c", "r9_c", "r10_c", "r11_c", "r12_c", "r13_c", "r14_c", "r15_c", + "pc_c", + "gbr_c", "mach_c", "macl_c", "pr_c", "t_c", + "fpscr_c", "fpul_c", + "fr0_c", "fr1_c", "fr2_c", "fr3_c", "fr4_c", "fr5_c", "fr6_c", "fr7_c", + "fr8_c", "fr9_c", "fr10_c", "fr11_c", "fr12_c", "fr13_c", "fr14_c", "fr15_c", + "dr0_c", "dr2_c", "dr4_c", "dr6_c", "dr8_c", "dr10_c", "dr12_c", "dr14_c", + "fv0_c", "fv4_c", "fv8_c", "fv12_c", + /* FIXME!!!! XF0 XF15, XD0 XD14 ?????*/ + }; + + if (reg_nr < 0) + return NULL; + if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) + return NULL; + return register_names[reg_nr]; +} + +#define NUM_PSEUDO_REGS_SH_MEDIA 80 +#define NUM_PSEUDO_REGS_SH_COMPACT 51 + +/* Macros and functions for setting and testing a bit in a minimal + symbol that marks it as 32-bit function. The MSB of the minimal + symbol's "info" field is used for this purpose. + + ELF_MAKE_MSYMBOL_SPECIAL + tests whether an ELF symbol is "special", i.e. refers + to a 32-bit function, and sets a "special" bit in a + minimal symbol to mark it as a 32-bit function + MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */ + +#define MSYMBOL_IS_SPECIAL(msym) \ + (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0) + +static void +sh64_elf_make_msymbol_special (asymbol *sym, struct minimal_symbol *msym) +{ + if (msym == NULL) + return; + + if (((elf_symbol_type *)(sym))->internal_elf_sym.st_other == STO_SH5_ISA32) + { + MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) | 0x80000000); + SYMBOL_VALUE_ADDRESS (msym) |= 1; + } +} + +/* ISA32 (shmedia) function addresses are odd (bit 0 is set). Here + are some macros to test, set, or clear bit 0 of addresses. */ +#define IS_ISA32_ADDR(addr) ((addr) & 1) +#define MAKE_ISA32_ADDR(addr) ((addr) | 1) +#define UNMAKE_ISA32_ADDR(addr) ((addr) & ~1) + +static int +pc_is_isa32 (bfd_vma memaddr) +{ + struct minimal_symbol *sym; + + /* If bit 0 of the address is set, assume this is a + ISA32 (shmedia) address. */ + if (IS_ISA32_ADDR (memaddr)) + return 1; + + /* A flag indicating that this is a ISA32 function is stored by elfread.c in + the high bit of the info field. Use this to decide if the function is + ISA16 or ISA32. */ + sym = lookup_minimal_symbol_by_pc (memaddr); + if (sym) + return MSYMBOL_IS_SPECIAL (sym); + else + return 0; +} + +static const unsigned char * +sh64_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) +{ + /* The BRK instruction for shmedia is + 01101111 11110101 11111111 11110000 + which translates in big endian mode to 0x6f, 0xf5, 0xff, 0xf0 + and in little endian mode to 0xf0, 0xff, 0xf5, 0x6f */ + + /* The BRK instruction for shcompact is + 00000000 00111011 + which translates in big endian mode to 0x0, 0x3b + and in little endian mode to 0x3b, 0x0*/ + + if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) + { + if (pc_is_isa32 (*pcptr)) + { + static unsigned char big_breakpoint_media[] = {0x6f, 0xf5, 0xff, 0xf0}; + *pcptr = UNMAKE_ISA32_ADDR (*pcptr); + *lenptr = sizeof (big_breakpoint_media); + return big_breakpoint_media; + } + else + { + static unsigned char big_breakpoint_compact[] = {0x0, 0x3b}; + *lenptr = sizeof (big_breakpoint_compact); + return big_breakpoint_compact; + } + } + else + { + if (pc_is_isa32 (*pcptr)) + { + static unsigned char little_breakpoint_media[] = {0xf0, 0xff, 0xf5, 0x6f}; + *pcptr = UNMAKE_ISA32_ADDR (*pcptr); + *lenptr = sizeof (little_breakpoint_media); + return little_breakpoint_media; + } + else + { + static unsigned char little_breakpoint_compact[] = {0x3b, 0x0}; + *lenptr = sizeof (little_breakpoint_compact); + return little_breakpoint_compact; + } + } +} + +/* Prologue looks like + [mov.l ,@-r15]... + [sts.l pr,@-r15] + [mov.l r14,@-r15] + [mov r15,r14] + + Actually it can be more complicated than this. For instance, with + newer gcc's: + + mov.l r14,@-r15 + add #-12,r15 + mov r15,r14 + mov r4,r1 + mov r5,r2 + mov.l r6,@(4,r14) + mov.l r7,@(8,r14) + mov.b r1,@r14 + mov r14,r1 + mov r14,r1 + add #2,r1 + mov.w r2,@r1 + + */ + +/* PTABS/L Rn, TRa 0110101111110001nnnnnnl00aaa0000 + with l=1 and n = 18 0110101111110001010010100aaa0000 */ +#define IS_PTABSL_R18(x) (((x) & 0xffffff8f) == 0x6bf14a00) + +/* STS.L PR,@-r0 0100000000100010 + r0-4-->r0, PR-->(r0) */ +#define IS_STS_R0(x) ((x) == 0x4022) + +/* STS PR, Rm 0000mmmm00101010 + PR-->Rm */ +#define IS_STS_PR(x) (((x) & 0xf0ff) == 0x2a) + +/* MOV.L Rm,@(disp,r15) 00011111mmmmdddd + Rm-->(dispx4+r15) */ +#define IS_MOV_TO_R15(x) (((x) & 0xff00) == 0x1f00) + +/* MOV.L R14,@(disp,r15) 000111111110dddd + R14-->(dispx4+r15) */ +#define IS_MOV_R14(x) (((x) & 0xfff0) == 0x1fe0) + +/* ST.Q R14, disp, R18 101011001110dddddddddd0100100000 + R18-->(dispx8+R14) */ +#define IS_STQ_R18_R14(x) (((x) & 0xfff003ff) == 0xace00120) + +/* ST.Q R15, disp, R18 101011001111dddddddddd0100100000 + R18-->(dispx8+R15) */ +#define IS_STQ_R18_R15(x) (((x) & 0xfff003ff) == 0xacf00120) + +/* ST.L R15, disp, R18 101010001111dddddddddd0100100000 + R18-->(dispx4+R15) */ +#define IS_STL_R18_R15(x) (((x) & 0xfff003ff) == 0xa8f00120) + +/* ST.Q R15, disp, R14 1010 1100 1111 dddd dddd dd00 1110 0000 + R14-->(dispx8+R15) */ +#define IS_STQ_R14_R15(x) (((x) & 0xfff003ff) == 0xacf000e0) + +/* ST.L R15, disp, R14 1010 1000 1111 dddd dddd dd00 1110 0000 + R14-->(dispx4+R15) */ +#define IS_STL_R14_R15(x) (((x) & 0xfff003ff) == 0xa8f000e0) + +/* ADDI.L R15,imm,R15 1101 0100 1111 ssss ssss ss00 1111 0000 + R15 + imm --> R15 */ +#define IS_ADDIL_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd4f000f0) + +/* ADDI R15,imm,R15 1101 0000 1111 ssss ssss ss00 1111 0000 + R15 + imm --> R15 */ +#define IS_ADDI_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd0f000f0) + +/* ADD.L R15,R63,R14 0000 0000 1111 1000 1111 1100 1110 0000 + R15 + R63 --> R14 */ +#define IS_ADDL_SP_FP_MEDIA(x) ((x) == 0x00f8fce0) + +/* ADD R15,R63,R14 0000 0000 1111 1001 1111 1100 1110 0000 + R15 + R63 --> R14 */ +#define IS_ADD_SP_FP_MEDIA(x) ((x) == 0x00f9fce0) + +#define IS_MOV_SP_FP_MEDIA(x) (IS_ADDL_SP_FP_MEDIA(x) || IS_ADD_SP_FP_MEDIA(x)) + +/* MOV #imm, R0 1110 0000 ssss ssss + #imm-->R0 */ +#define IS_MOV_R0(x) (((x) & 0xff00) == 0xe000) + +/* MOV.L @(disp,PC), R0 1101 0000 iiii iiii */ +#define IS_MOVL_R0(x) (((x) & 0xff00) == 0xd000) + +/* ADD r15,r0 0011 0000 1111 1100 + r15+r0-->r0 */ +#define IS_ADD_SP_R0(x) ((x) == 0x30fc) + +/* MOV.L R14 @-R0 0010 0000 1110 0110 + R14-->(R0-4), R0-4-->R0 */ +#define IS_MOV_R14_R0(x) ((x) == 0x20e6) + +/* ADD Rm,R63,Rn Rm+R63-->Rn 0000 00mm mmmm 1001 1111 11nn nnnn 0000 + where Rm is one of r2-r9 which are the argument registers. */ +/* FIXME: Recognize the float and double register moves too! */ +#define IS_MEDIA_IND_ARG_MOV(x) \ +((((x) & 0xfc0ffc0f) == 0x0009fc00) && (((x) & 0x03f00000) >= 0x00200000 && ((x) & 0x03f00000) <= 0x00900000)) + +/* ST.Q Rn,0,Rm Rm-->Rn+0 1010 11nn nnnn 0000 0000 00mm mmmm 0000 + or ST.L Rn,0,Rm Rm-->Rn+0 1010 10nn nnnn 0000 0000 00mm mmmm 0000 + where Rm is one of r2-r9 which are the argument registers. */ +#define IS_MEDIA_ARG_MOV(x) \ +(((((x) & 0xfc0ffc0f) == 0xac000000) || (((x) & 0xfc0ffc0f) == 0xa8000000)) \ + && (((x) & 0x000003f0) >= 0x00000020 && ((x) & 0x000003f0) <= 0x00000090)) + +/* ST.B R14,0,Rn Rn-->(R14+0) 1010 0000 1110 0000 0000 00nn nnnn 0000*/ +/* ST.W R14,0,Rn Rn-->(R14+0) 1010 0100 1110 0000 0000 00nn nnnn 0000*/ +/* ST.L R14,0,Rn Rn-->(R14+0) 1010 1000 1110 0000 0000 00nn nnnn 0000*/ +/* FST.S R14,0,FRn Rn-->(R14+0) 1011 0100 1110 0000 0000 00nn nnnn 0000*/ +/* FST.D R14,0,DRn Rn-->(R14+0) 1011 1100 1110 0000 0000 00nn nnnn 0000*/ +#define IS_MEDIA_MOV_TO_R14(x) \ +((((x) & 0xfffffc0f) == 0xa0e00000) \ +|| (((x) & 0xfffffc0f) == 0xa4e00000) \ +|| (((x) & 0xfffffc0f) == 0xa8e00000) \ +|| (((x) & 0xfffffc0f) == 0xb4e00000) \ +|| (((x) & 0xfffffc0f) == 0xbce00000)) + +/* MOV Rm, Rn Rm-->Rn 0110 nnnn mmmm 0011 + where Rm is r2-r9 */ +#define IS_COMPACT_IND_ARG_MOV(x) \ +((((x) & 0xf00f) == 0x6003) && (((x) & 0x00f0) >= 0x0020) && (((x) & 0x00f0) <= 0x0090)) + +/* compact direct arg move! + MOV.L Rn, @r14 0010 1110 mmmm 0010 */ +#define IS_COMPACT_ARG_MOV(x) \ +(((((x) & 0xff0f) == 0x2e02) && (((x) & 0x00f0) >= 0x0020) && ((x) & 0x00f0) <= 0x0090)) + +/* MOV.B Rm, @R14 0010 1110 mmmm 0000 + MOV.W Rm, @R14 0010 1110 mmmm 0001 */ +#define IS_COMPACT_MOV_TO_R14(x) \ +((((x) & 0xff0f) == 0x2e00) || (((x) & 0xff0f) == 0x2e01)) + +#define IS_JSR_R0(x) ((x) == 0x400b) +#define IS_NOP(x) ((x) == 0x0009) + + +/* MOV r15,r14 0110111011110011 + r15-->r14 */ +#define IS_MOV_SP_FP(x) ((x) == 0x6ef3) + +/* ADD #imm,r15 01111111iiiiiiii + r15+imm-->r15 */ +#define IS_ADD_SP(x) (((x) & 0xff00) == 0x7f00) + +/* Skip any prologue before the guts of a function */ + +/* Skip the prologue using the debug information. If this fails we'll + fall back on the 'guess' method below. */ +static CORE_ADDR +after_prologue (CORE_ADDR pc) +{ + struct symtab_and_line sal; + CORE_ADDR func_addr, func_end; + + /* If we can not find the symbol in the partial symbol table, then + there is no hope we can determine the function's start address + with this code. */ + if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end)) + return 0; + + /* Get the line associated with FUNC_ADDR. */ + sal = find_pc_line (func_addr, 0); + + /* There are only two cases to consider. First, the end of the source line + is within the function bounds. In that case we return the end of the + source line. Second is the end of the source line extends beyond the + bounds of the current function. We need to use the slow code to + examine instructions in that case. */ + if (sal.end < func_end) + return sal.end; + else + return 0; +} + +static CORE_ADDR +look_for_args_moves (CORE_ADDR start_pc, int media_mode) +{ + CORE_ADDR here, end; + int w; + int insn_size = (media_mode ? 4 : 2); + + for (here = start_pc, end = start_pc + (insn_size * 28); here < end;) + { + if (media_mode) + { + w = read_memory_integer (UNMAKE_ISA32_ADDR (here), insn_size); + here += insn_size; + if (IS_MEDIA_IND_ARG_MOV (w)) + { + /* This must be followed by a store to r14, so the argument + is where the debug info says it is. This can happen after + the SP has been saved, unfortunately. */ + + int next_insn = read_memory_integer (UNMAKE_ISA32_ADDR (here), + insn_size); + here += insn_size; + if (IS_MEDIA_MOV_TO_R14 (next_insn)) + start_pc = here; + } + else if (IS_MEDIA_ARG_MOV (w)) + { + /* These instructions store directly the argument in r14. */ + start_pc = here; + } + else + break; + } + else + { + w = read_memory_integer (here, insn_size); + w = w & 0xffff; + here += insn_size; + if (IS_COMPACT_IND_ARG_MOV (w)) + { + /* This must be followed by a store to r14, so the argument + is where the debug info says it is. This can happen after + the SP has been saved, unfortunately. */ + + int next_insn = 0xffff & read_memory_integer (here, insn_size); + here += insn_size; + if (IS_COMPACT_MOV_TO_R14 (next_insn)) + start_pc = here; + } + else if (IS_COMPACT_ARG_MOV (w)) + { + /* These instructions store directly the argument in r14. */ + start_pc = here; + } + else if (IS_MOVL_R0 (w)) + { + /* There is a function that gcc calls to get the arguments + passed correctly to the function. Only after this + function call the arguments will be found at the place + where they are supposed to be. This happens in case the + argument has to be stored into a 64-bit register (for + instance doubles, long longs). SHcompact doesn't have + access to the full 64-bits, so we store the register in + stack slot and store the address of the stack slot in + the register, then do a call through a wrapper that + loads the memory value into the register. A SHcompact + callee calls an argument decoder + (GCC_shcompact_incoming_args) that stores the 64-bit + value in a stack slot and stores the address of the + stack slot in the register. GCC thinks the argument is + just passed by transparent reference, but this is only + true after the argument decoder is called. Such a call + needs to be considered part of the prologue. */ + + /* This must be followed by a JSR @r0 instruction and by + a NOP instruction. After these, the prologue is over! */ + + int next_insn = 0xffff & read_memory_integer (here, insn_size); + here += insn_size; + if (IS_JSR_R0 (next_insn)) + { + next_insn = 0xffff & read_memory_integer (here, insn_size); + here += insn_size; + + if (IS_NOP (next_insn)) + start_pc = here; + } + } + else + break; + } + } + + return start_pc; +} + +static CORE_ADDR +sh64_skip_prologue_hard_way (CORE_ADDR start_pc) +{ + CORE_ADDR here, end; + int updated_fp = 0; + int insn_size = 4; + int media_mode = 1; + + if (!start_pc) + return 0; + + if (pc_is_isa32 (start_pc) == 0) + { + insn_size = 2; + media_mode = 0; + } + + for (here = start_pc, end = start_pc + (insn_size * 28); here < end;) + { + + if (media_mode) + { + int w = read_memory_integer (UNMAKE_ISA32_ADDR (here), insn_size); + here += insn_size; + if (IS_STQ_R18_R14 (w) || IS_STQ_R18_R15 (w) || IS_STQ_R14_R15 (w) + || IS_STL_R14_R15 (w) || IS_STL_R18_R15 (w) + || IS_ADDIL_SP_MEDIA (w) || IS_ADDI_SP_MEDIA (w) || IS_PTABSL_R18 (w)) + { + start_pc = here; + } + else if (IS_MOV_SP_FP (w) || IS_MOV_SP_FP_MEDIA(w)) + { + start_pc = here; + updated_fp = 1; + } + else + if (updated_fp) + { + /* Don't bail out yet, we may have arguments stored in + registers here, according to the debug info, so that + gdb can print the frames correctly. */ + start_pc = look_for_args_moves (here - insn_size, media_mode); + break; + } + } + else + { + int w = 0xffff & read_memory_integer (here, insn_size); + here += insn_size; + + if (IS_STS_R0 (w) || IS_STS_PR (w) + || IS_MOV_TO_R15 (w) || IS_MOV_R14 (w) + || IS_MOV_R0 (w) || IS_ADD_SP_R0 (w) || IS_MOV_R14_R0 (w)) + { + start_pc = here; + } + else if (IS_MOV_SP_FP (w)) + { + start_pc = here; + updated_fp = 1; + } + else + if (updated_fp) + { + /* Don't bail out yet, we may have arguments stored in + registers here, according to the debug info, so that + gdb can print the frames correctly. */ + start_pc = look_for_args_moves (here - insn_size, media_mode); + break; + } + } + } + + return start_pc; +} + +static CORE_ADDR +sh_skip_prologue (CORE_ADDR pc) +{ + CORE_ADDR post_prologue_pc; + + /* See if we can determine the end of the prologue via the symbol table. + If so, then return either PC, or the PC after the prologue, whichever + is greater. */ + post_prologue_pc = after_prologue (pc); + + /* If after_prologue returned a useful address, then use it. Else + fall back on the instruction skipping code. */ + if (post_prologue_pc != 0) + return max (pc, post_prologue_pc); + else + return sh64_skip_prologue_hard_way (pc); +} + +/* Immediately after a function call, return the saved pc. + Can't always go through the frames for this because on some machines + the new frame is not set up until the new function executes + some instructions. + + The return address is the value saved in the PR register + 4 */ +static CORE_ADDR +sh_saved_pc_after_call (struct frame_info *frame) +{ + return (ADDR_BITS_REMOVE (read_register (PR_REGNUM))); +} + +/* Should call_function allocate stack space for a struct return? */ +static int +sh64_use_struct_convention (int gcc_p, struct type *type) +{ + return (TYPE_LENGTH (type) > 8); +} + +/* Store the address of the place in which to copy the structure the + subroutine will return. This is called from call_function. + + We store structs through a pointer passed in R2 */ +static void +sh64_store_struct_return (CORE_ADDR addr, CORE_ADDR sp) +{ + write_register (STRUCT_RETURN_REGNUM, (addr)); +} + +/* Disassemble an instruction. */ +static int +gdb_print_insn_sh (bfd_vma memaddr, disassemble_info *info) +{ + info->endian = TARGET_BYTE_ORDER; + return print_insn_sh (memaddr, info); +} + +/* Given a register number RN as it appears in an assembly + instruction, find the corresponding register number in the GDB + scheme. */ +static int +translate_insn_rn (int rn, int media_mode) +{ + /* FIXME: this assumes that the number rn is for a not pseudo + register only. */ + if (media_mode) + return rn; + else + { + /* These registers don't have a corresponding compact one. */ + /* FIXME: This is probably not enough. */ +#if 0 + if ((rn >= 16 && rn <= 63) || (rn >= 93 && rn <= 140)) + return rn; +#endif + if (rn >= 0 && rn <= R0_C_REGNUM) + return R0_C_REGNUM + rn; + else + return rn; + } +} + +/* Given a GDB frame, determine the address of the calling function's + frame. This will be used to create a new GDB frame struct, and + then DEPRECATED_INIT_EXTRA_FRAME_INFO and DEPRECATED_INIT_FRAME_PC + will be called for the new frame. + + For us, the frame address is its stack pointer value, so we look up + the function prologue to determine the caller's sp value, and return it. */ +static CORE_ADDR +sh64_frame_chain (struct frame_info *frame) +{ + if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame), + get_frame_base (frame), + get_frame_base (frame))) + return get_frame_base (frame); /* dummy frame same as caller's frame */ + if (get_frame_pc (frame) + && !deprecated_inside_entry_file (get_frame_pc (frame))) + { + int media_mode = pc_is_isa32 (get_frame_pc (frame)); + int size; + if (gdbarch_tdep (current_gdbarch)->sh_abi == SH_ABI_32) + size = 4; + else + size = register_size (current_gdbarch, + translate_insn_rn (DEPRECATED_FP_REGNUM, + media_mode)); + return read_memory_integer (get_frame_base (frame) + + get_frame_extra_info (frame)->f_offset, + size); + } + else + return 0; +} + +static CORE_ADDR +sh64_get_saved_pr (struct frame_info *fi, int pr_regnum) +{ + int media_mode = 0; + + for (; fi; fi = get_next_frame (fi)) + if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi), get_frame_base (fi), + get_frame_base (fi))) + /* When the caller requests PR from the dummy frame, we return + PC because that's where the previous routine appears to have + done a call from. */ + return deprecated_read_register_dummy (get_frame_pc (fi), + get_frame_base (fi), pr_regnum); + else + { + DEPRECATED_FRAME_INIT_SAVED_REGS (fi); + if (!get_frame_pc (fi)) + return 0; + + media_mode = pc_is_isa32 (get_frame_pc (fi)); + + if (deprecated_get_frame_saved_regs (fi)[pr_regnum] != 0) + { + int gdb_reg_num = translate_insn_rn (pr_regnum, media_mode); + int size = ((gdbarch_tdep (current_gdbarch)->sh_abi == SH_ABI_32) + ? 4 + : register_size (current_gdbarch, gdb_reg_num)); + return read_memory_integer (deprecated_get_frame_saved_regs (fi)[pr_regnum], size); + } + } + return read_register (pr_regnum); +} + +/* For vectors of 4 floating point registers. */ +static int +fv_reg_base_num (int fv_regnum) +{ + int fp_regnum; + + fp_regnum = FP0_REGNUM + + (fv_regnum - FV0_REGNUM) * 4; + return fp_regnum; +} + +/* For double precision floating point registers, i.e 2 fp regs.*/ +static int +dr_reg_base_num (int dr_regnum) +{ + int fp_regnum; + + fp_regnum = FP0_REGNUM + + (dr_regnum - DR0_REGNUM) * 2; + return fp_regnum; +} + +/* For pairs of floating point registers */ +static int +fpp_reg_base_num (int fpp_regnum) +{ + int fp_regnum; + + fp_regnum = FP0_REGNUM + + (fpp_regnum - FPP0_REGNUM) * 2; + return fp_regnum; +} + +static int +is_media_pseudo (int rn) +{ + return (rn >= DR0_REGNUM && rn <= FV_LAST_REGNUM); +} + +static int +sh64_get_gdb_regnum (int gcc_regnum, CORE_ADDR pc) +{ + return translate_insn_rn (gcc_regnum, pc_is_isa32 (pc)); +} + +static int +sh64_media_reg_base_num (int reg_nr) +{ + int base_regnum = -1; + + if (reg_nr >= DR0_REGNUM + && reg_nr <= DR_LAST_REGNUM) + base_regnum = dr_reg_base_num (reg_nr); + + else if (reg_nr >= FPP0_REGNUM + && reg_nr <= FPP_LAST_REGNUM) + base_regnum = fpp_reg_base_num (reg_nr); + + else if (reg_nr >= FV0_REGNUM + && reg_nr <= FV_LAST_REGNUM) + base_regnum = fv_reg_base_num (reg_nr); + + return base_regnum; +} + +/* *INDENT-OFF* */ +/* + SH COMPACT MODE (ISA 16) (all pseudo) 221-272 + GDB_REGNUM BASE_REGNUM + r0_c 221 0 + r1_c 222 1 + r2_c 223 2 + r3_c 224 3 + r4_c 225 4 + r5_c 226 5 + r6_c 227 6 + r7_c 228 7 + r8_c 229 8 + r9_c 230 9 + r10_c 231 10 + r11_c 232 11 + r12_c 233 12 + r13_c 234 13 + r14_c 235 14 + r15_c 236 15 + + pc_c 237 64 + gbr_c 238 16 + mach_c 239 17 + macl_c 240 17 + pr_c 241 18 + t_c 242 19 + fpscr_c 243 76 + fpul_c 244 109 + + fr0_c 245 77 + fr1_c 246 78 + fr2_c 247 79 + fr3_c 248 80 + fr4_c 249 81 + fr5_c 250 82 + fr6_c 251 83 + fr7_c 252 84 + fr8_c 253 85 + fr9_c 254 86 + fr10_c 255 87 + fr11_c 256 88 + fr12_c 257 89 + fr13_c 258 90 + fr14_c 259 91 + fr15_c 260 92 + + dr0_c 261 77 + dr2_c 262 79 + dr4_c 263 81 + dr6_c 264 83 + dr8_c 265 85 + dr10_c 266 87 + dr12_c 267 89 + dr14_c 268 91 + + fv0_c 269 77 + fv4_c 270 81 + fv8_c 271 85 + fv12_c 272 91 +*/ +/* *INDENT-ON* */ +static int +sh64_compact_reg_base_num (int reg_nr) +{ + int base_regnum = -1; + + /* general register N maps to general register N */ + if (reg_nr >= R0_C_REGNUM + && reg_nr <= R_LAST_C_REGNUM) + base_regnum = reg_nr - R0_C_REGNUM; + + /* floating point register N maps to floating point register N */ + else if (reg_nr >= FP0_C_REGNUM + && reg_nr <= FP_LAST_C_REGNUM) + base_regnum = reg_nr - FP0_C_REGNUM + FP0_REGNUM; + + /* double prec register N maps to base regnum for double prec register N */ + else if (reg_nr >= DR0_C_REGNUM + && reg_nr <= DR_LAST_C_REGNUM) + base_regnum = dr_reg_base_num (DR0_REGNUM + + reg_nr - DR0_C_REGNUM); + + /* vector N maps to base regnum for vector register N */ + else if (reg_nr >= FV0_C_REGNUM + && reg_nr <= FV_LAST_C_REGNUM) + base_regnum = fv_reg_base_num (FV0_REGNUM + + reg_nr - FV0_C_REGNUM); + + else if (reg_nr == PC_C_REGNUM) + base_regnum = PC_REGNUM; + + else if (reg_nr == GBR_C_REGNUM) + base_regnum = 16; + + else if (reg_nr == MACH_C_REGNUM + || reg_nr == MACL_C_REGNUM) + base_regnum = 17; + + else if (reg_nr == PR_C_REGNUM) + base_regnum = 18; + + else if (reg_nr == T_C_REGNUM) + base_regnum = 19; + + else if (reg_nr == FPSCR_C_REGNUM) + base_regnum = FPSCR_REGNUM; /*???? this register is a mess. */ + + else if (reg_nr == FPUL_C_REGNUM) + base_regnum = FP0_REGNUM + 32; + + return base_regnum; +} + +/* Given a register number RN (according to the gdb scheme) , return + its corresponding architectural register. In media mode, only a + subset of the registers is pseudo registers. For compact mode, all + the registers are pseudo. */ +static int +translate_rn_to_arch_reg_num (int rn, int media_mode) +{ + + if (media_mode) + { + if (!is_media_pseudo (rn)) + return rn; + else + return sh64_media_reg_base_num (rn); + } + else + /* All compact registers are pseudo. */ + return sh64_compact_reg_base_num (rn); +} + +static int +sign_extend (int value, int bits) +{ + value = value & ((1 << bits) - 1); + return (value & (1 << (bits - 1)) + ? value | (~((1 << bits) - 1)) + : value); +} + +static void +sh64_nofp_frame_init_saved_regs (struct frame_info *fi) +{ + int *where = (int *) alloca ((NUM_REGS + NUM_PSEUDO_REGS) * sizeof (int)); + int rn; + int have_fp = 0; + int fp_regnum; + int sp_regnum; + int depth; + int pc; + int opc; + int insn; + int r0_val = 0; + int media_mode = 0; + int insn_size; + int gdb_register_number; + int register_number; + char *dummy_regs = deprecated_generic_find_dummy_frame (get_frame_pc (fi), + get_frame_base (fi)); + struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); + + if (deprecated_get_frame_saved_regs (fi) == NULL) + frame_saved_regs_zalloc (fi); + else + memset (deprecated_get_frame_saved_regs (fi), 0, SIZEOF_FRAME_SAVED_REGS); + + if (dummy_regs) + { + /* DANGER! This is ONLY going to work if the char buffer format of + the saved registers is byte-for-byte identical to the + CORE_ADDR regs[NUM_REGS] format used by struct frame_saved_regs! */ + memcpy (deprecated_get_frame_saved_regs (fi), dummy_regs, SIZEOF_FRAME_SAVED_REGS); + return; + } + + get_frame_extra_info (fi)->leaf_function = 1; + get_frame_extra_info (fi)->f_offset = 0; + + for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++) + where[rn] = -1; + + depth = 0; + + /* Loop around examining the prologue insns until we find something + that does not appear to be part of the prologue. But give up + after 20 of them, since we're getting silly then. */ + + pc = get_frame_func (fi); + if (!pc) + { + deprecated_update_frame_pc_hack (fi, 0); + return; + } + + if (pc_is_isa32 (pc)) + { + media_mode = 1; + insn_size = 4; + } + else + { + media_mode = 0; + insn_size = 2; + } + + /* The frame pointer register is general register 14 in shmedia and + shcompact modes. In sh compact it is a pseudo register. Same goes + for the stack pointer register, which is register 15. */ + fp_regnum = translate_insn_rn (DEPRECATED_FP_REGNUM, media_mode); + sp_regnum = translate_insn_rn (SP_REGNUM, media_mode); + + for (opc = pc + (insn_size * 28); pc < opc; pc += insn_size) + { + insn = read_memory_integer (media_mode ? UNMAKE_ISA32_ADDR (pc) : pc, + insn_size); + + if (media_mode == 0) + { + if (IS_STS_PR (insn)) + { + int next_insn = read_memory_integer (pc + insn_size, insn_size); + if (IS_MOV_TO_R15 (next_insn)) + { + int reg_nr = PR_C_REGNUM; + + where[reg_nr] = depth - ((((next_insn & 0xf) ^ 0x8) - 0x8) << 2); + get_frame_extra_info (fi)->leaf_function = 0; + pc += insn_size; + } + } + else if (IS_MOV_R14 (insn)) + { + where[fp_regnum] = depth - ((((insn & 0xf) ^ 0x8) - 0x8) << 2); + } + + else if (IS_MOV_R0 (insn)) + { + /* Put in R0 the offset from SP at which to store some + registers. We are interested in this value, because it + will tell us where the given registers are stored within + the frame. */ + r0_val = ((insn & 0xff) ^ 0x80) - 0x80; + } + else if (IS_ADD_SP_R0 (insn)) + { + /* This instruction still prepares r0, but we don't care. + We already have the offset in r0_val. */ + } + else if (IS_STS_R0 (insn)) + { + /* Store PR at r0_val-4 from SP. Decrement r0 by 4*/ + int reg_nr = PR_C_REGNUM; + where[reg_nr] = depth - (r0_val - 4); + r0_val -= 4; + get_frame_extra_info (fi)->leaf_function = 0; + } + else if (IS_MOV_R14_R0 (insn)) + { + /* Store R14 at r0_val-4 from SP. Decrement r0 by 4 */ + where[fp_regnum] = depth - (r0_val - 4); + r0_val -= 4; + } + + else if (IS_ADD_SP (insn)) + { + depth -= ((insn & 0xff) ^ 0x80) - 0x80; + } + else if (IS_MOV_SP_FP (insn)) + break; + } + else + { + if (IS_ADDIL_SP_MEDIA (insn) + || IS_ADDI_SP_MEDIA (insn)) + { + depth -= sign_extend ((((insn & 0xffc00) ^ 0x80000) - 0x80000) >> 10, 9); + } + + else if (IS_STQ_R18_R15 (insn)) + { + where[PR_REGNUM] = + depth - (sign_extend ((insn & 0xffc00) >> 10, 9) << 3); + get_frame_extra_info (fi)->leaf_function = 0; + } + + else if (IS_STL_R18_R15 (insn)) + { + where[PR_REGNUM] = + depth - (sign_extend ((insn & 0xffc00) >> 10, 9) << 2); + get_frame_extra_info (fi)->leaf_function = 0; + } + + else if (IS_STQ_R14_R15 (insn)) + { + where[fp_regnum] = depth - (sign_extend ((insn & 0xffc00) >> 10, 9) << 3); + } + + else if (IS_STL_R14_R15 (insn)) + { + where[fp_regnum] = depth - (sign_extend ((insn & 0xffc00) >> 10, 9) << 2); + } + + else if (IS_MOV_SP_FP_MEDIA (insn)) + break; + } + } + + /* Now we know how deep things are, we can work out their addresses. */ + for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++) + { + register_number = translate_rn_to_arch_reg_num (rn, media_mode); + + if (where[rn] >= 0) + { + if (rn == fp_regnum) + have_fp = 1; + + /* Watch out! saved_regs is only for the real registers, and + doesn't include space for the pseudo registers. */ + deprecated_get_frame_saved_regs (fi)[register_number] + = get_frame_base (fi) - where[rn] + depth; + } + else + deprecated_get_frame_saved_regs (fi)[register_number] = 0; + } + + if (have_fp) + { + /* SP_REGNUM is 15. For shmedia 15 is the real register. For + shcompact 15 is the arch register corresponding to the pseudo + register r15 which still is the SP register. */ + /* The place on the stack where fp is stored contains the sp of + the caller. */ + /* Again, saved_registers contains only space for the real + registers, so we store in DEPRECATED_FP_REGNUM position. */ + int size; + if (tdep->sh_abi == SH_ABI_32) + size = 4; + else + size = register_size (current_gdbarch, fp_regnum); + deprecated_get_frame_saved_regs (fi)[sp_regnum] + = read_memory_integer (deprecated_get_frame_saved_regs (fi)[fp_regnum], + size); + } + else + deprecated_get_frame_saved_regs (fi)[sp_regnum] = get_frame_base (fi); + + get_frame_extra_info (fi)->f_offset = depth - where[fp_regnum]; +} + +/* Initialize the extra info saved in a FRAME */ +static void +sh64_init_extra_frame_info (int fromleaf, struct frame_info *fi) +{ + int media_mode = pc_is_isa32 (get_frame_pc (fi)); + + frame_extra_info_zalloc (fi, sizeof (struct frame_extra_info)); + + if (get_next_frame (fi)) + deprecated_update_frame_pc_hack (fi, DEPRECATED_FRAME_SAVED_PC (get_next_frame (fi))); + + if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi), get_frame_base (fi), + get_frame_base (fi))) + { + /* We need to setup fi->frame here because call_function_by_hand + gets it wrong by assuming it's always FP. */ + deprecated_update_frame_base_hack (fi, deprecated_read_register_dummy (get_frame_pc (fi), get_frame_base (fi), SP_REGNUM)); + get_frame_extra_info (fi)->return_pc = + deprecated_read_register_dummy (get_frame_pc (fi), + get_frame_base (fi), PC_REGNUM); + get_frame_extra_info (fi)->f_offset = -(DEPRECATED_CALL_DUMMY_LENGTH + 4); + get_frame_extra_info (fi)->leaf_function = 0; + return; + } + else + { + DEPRECATED_FRAME_INIT_SAVED_REGS (fi); + get_frame_extra_info (fi)->return_pc = + sh64_get_saved_pr (fi, PR_REGNUM); + } +} + +static void +sh64_get_saved_register (char *raw_buffer, int *optimized, CORE_ADDR *addrp, + struct frame_info *frame, int regnum, + enum lval_type *lval) +{ + int media_mode; + int live_regnum = regnum; + struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); + + if (!target_has_registers) + error ("No registers."); + + /* Normal systems don't optimize out things with register numbers. */ + if (optimized != NULL) + *optimized = 0; + + if (addrp) /* default assumption: not found in memory */ + *addrp = 0; + + if (raw_buffer) + memset (raw_buffer, 0, sizeof (raw_buffer)); + + /* We must do this here, before the following while loop changes + frame, and makes it NULL. If this is a media register number, + but we are in compact mode, it will become the corresponding + compact pseudo register. If there is no corresponding compact + pseudo-register what do we do?*/ + media_mode = pc_is_isa32 (get_frame_pc (frame)); + live_regnum = translate_insn_rn (regnum, media_mode); + + /* Note: since the current frame's registers could only have been + saved by frames INTERIOR TO the current frame, we skip examining + the current frame itself: otherwise, we would be getting the + previous frame's registers which were saved by the current frame. */ + + while (frame && ((frame = get_next_frame (frame)) != NULL)) + { + if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame), + get_frame_base (frame), + get_frame_base (frame))) + { + if (lval) /* found it in a CALL_DUMMY frame */ + *lval = not_lval; + if (raw_buffer) + memcpy (raw_buffer, + (deprecated_generic_find_dummy_frame (get_frame_pc (frame), get_frame_base (frame)) + + DEPRECATED_REGISTER_BYTE (regnum)), + register_size (current_gdbarch, regnum)); + return; + } + + DEPRECATED_FRAME_INIT_SAVED_REGS (frame); + if (deprecated_get_frame_saved_regs (frame) != NULL + && deprecated_get_frame_saved_regs (frame)[regnum] != 0) + { + if (lval) /* found it saved on the stack */ + *lval = lval_memory; + if (regnum == SP_REGNUM) + { + if (raw_buffer) /* SP register treated specially */ + store_unsigned_integer (raw_buffer, + register_size (current_gdbarch, + regnum), + deprecated_get_frame_saved_regs (frame)[regnum]); + } + else + { /* any other register */ + + if (addrp) + *addrp = deprecated_get_frame_saved_regs (frame)[regnum]; + if (raw_buffer) + { + int size; + if (tdep->sh_abi == SH_ABI_32 + && (live_regnum == DEPRECATED_FP_REGNUM + || live_regnum == PR_REGNUM)) + size = 4; + else + size = register_size (current_gdbarch, live_regnum); + if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE) + read_memory (deprecated_get_frame_saved_regs (frame)[regnum], + raw_buffer, size); + else + read_memory (deprecated_get_frame_saved_regs (frame)[regnum], + raw_buffer + + register_size (current_gdbarch, live_regnum) + - size, + size); + } + } + return; + } + } + + /* If we get thru the loop to this point, it means the register was + not saved in any frame. Return the actual live-register value. */ + + if (lval) /* found it in a live register */ + *lval = lval_register; + if (addrp) + *addrp = DEPRECATED_REGISTER_BYTE (live_regnum); + if (raw_buffer) + deprecated_read_register_gen (live_regnum, raw_buffer); +} + +static CORE_ADDR +sh64_extract_struct_value_address (char *regbuf) +{ + return (extract_unsigned_integer ((regbuf + DEPRECATED_REGISTER_BYTE (STRUCT_RETURN_REGNUM)), + register_size (current_gdbarch, + STRUCT_RETURN_REGNUM))); +} + +static CORE_ADDR +sh_frame_saved_pc (struct frame_info *frame) +{ + return (get_frame_extra_info (frame)->return_pc); +} + +/* Discard from the stack the innermost frame, restoring all saved registers. + Used in the 'return' command. */ +static void +sh64_pop_frame (void) +{ + struct frame_info *frame = get_current_frame (); + CORE_ADDR fp; + int regnum; + struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); + + int media_mode = pc_is_isa32 (get_frame_pc (frame)); + + if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame), + get_frame_base (frame), + get_frame_base (frame))) + generic_pop_dummy_frame (); + else + { + fp = get_frame_base (frame); + DEPRECATED_FRAME_INIT_SAVED_REGS (frame); + + /* Copy regs from where they were saved in the frame */ + for (regnum = 0; regnum < NUM_REGS + NUM_PSEUDO_REGS; regnum++) + if (deprecated_get_frame_saved_regs (frame)[regnum]) + { + int size; + if (tdep->sh_abi == SH_ABI_32 + && (regnum == DEPRECATED_FP_REGNUM + || regnum == PR_REGNUM)) + size = 4; + else + size = register_size (current_gdbarch, + translate_insn_rn (regnum, media_mode)); + write_register (regnum, + read_memory_integer (deprecated_get_frame_saved_regs (frame)[regnum], + size)); + } + + write_register (PC_REGNUM, get_frame_extra_info (frame)->return_pc); + write_register (SP_REGNUM, fp + 8); + } + flush_cached_frames (); +} + +static CORE_ADDR +sh_frame_align (struct gdbarch *ignore, CORE_ADDR sp) +{ + return sp & ~3; +} + +/* Function: push_arguments + Setup the function arguments for calling a function in the inferior. + + On the Renesas SH architecture, there are four registers (R4 to R7) + which are dedicated for passing function arguments. Up to the first + four arguments (depending on size) may go into these registers. + The rest go on the stack. + + Arguments that are smaller than 4 bytes will still take up a whole + register or a whole 32-bit word on the stack, and will be + right-justified in the register or the stack word. This includes + chars, shorts, and small aggregate types. + + Arguments that are larger than 4 bytes may be split between two or + more registers. If there are not enough registers free, an argument + may be passed partly in a register (or registers), and partly on the + stack. This includes doubles, long longs, and larger aggregates. + As far as I know, there is no upper limit to the size of aggregates + that will be passed in this way; in other words, the convention of + passing a pointer to a large aggregate instead of a copy is not used. + + An exceptional case exists for struct arguments (and possibly other + aggregates such as arrays) if the size is larger than 4 bytes but + not a multiple of 4 bytes. In this case the argument is never split + between the registers and the stack, but instead is copied in its + entirety onto the stack, AND also copied into as many registers as + there is room for. In other words, space in registers permitting, + two copies of the same argument are passed in. As far as I can tell, + only the one on the stack is used, although that may be a function + of the level of compiler optimization. I suspect this is a compiler + bug. Arguments of these odd sizes are left-justified within the + word (as opposed to arguments smaller than 4 bytes, which are + right-justified). + + If the function is to return an aggregate type such as a struct, it + is either returned in the normal return value register R0 (if its + size is no greater than one byte), or else the caller must allocate + space into which the callee will copy the return value (if the size + is greater than one byte). In this case, a pointer to the return + value location is passed into the callee in register R2, which does + not displace any of the other arguments passed in via registers R4 + to R7. */ + +/* R2-R9 for integer types and integer equivalent (char, pointers) and + non-scalar (struct, union) elements (even if the elements are + floats). + FR0-FR11 for single precision floating point (float) + DR0-DR10 for double precision floating point (double) + + If a float is argument number 3 (for instance) and arguments number + 1,2, and 4 are integer, the mapping will be: + arg1 -->R2, arg2 --> R3, arg3 -->FR0, arg4 --> R5. I.e. R4 is not used. + + If a float is argument number 10 (for instance) and arguments number + 1 through 10 are integer, the mapping will be: + arg1->R2, arg2->R3, arg3->R4, arg4->R5, arg5->R6, arg6->R7, arg7->R8, + arg8->R9, arg9->(0,SP)stack(8-byte aligned), arg10->FR0, arg11->stack(16,SP). + I.e. there is hole in the stack. + + Different rules apply for variable arguments functions, and for functions + for which the prototype is not known. */ + +static CORE_ADDR +sh64_push_arguments (int nargs, struct value **args, CORE_ADDR sp, + int struct_return, CORE_ADDR struct_addr) +{ + int stack_offset, stack_alloc; + int int_argreg; + int float_argreg; + int double_argreg; + int float_arg_index = 0; + int double_arg_index = 0; + int argnum; + struct type *type; + CORE_ADDR regval; + char *val; + char valbuf[8]; + char valbuf_tmp[8]; + int len; + int argreg_size; + int fp_args[12]; + + memset (fp_args, 0, sizeof (fp_args)); + + /* first force sp to a 8-byte alignment */ + sp = sp & ~7; + + /* The "struct return pointer" pseudo-argument has its own dedicated + register */ + + if (struct_return) + write_register (STRUCT_RETURN_REGNUM, struct_addr); + + /* Now make sure there's space on the stack */ + for (argnum = 0, stack_alloc = 0; argnum < nargs; argnum++) + stack_alloc += ((TYPE_LENGTH (VALUE_TYPE (args[argnum])) + 7) & ~7); + sp -= stack_alloc; /* make room on stack for args */ + + /* Now load as many as possible of the first arguments into + registers, and push the rest onto the stack. There are 64 bytes + in eight registers available. Loop thru args from first to last. */ + + int_argreg = ARG0_REGNUM; + float_argreg = FP0_REGNUM; + double_argreg = DR0_REGNUM; + + for (argnum = 0, stack_offset = 0; argnum < nargs; argnum++) + { + type = VALUE_TYPE (args[argnum]); + len = TYPE_LENGTH (type); + memset (valbuf, 0, sizeof (valbuf)); + + if (TYPE_CODE (type) != TYPE_CODE_FLT) + { + argreg_size = register_size (current_gdbarch, int_argreg); + + if (len < argreg_size) + { + /* value gets right-justified in the register or stack word */ + if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) + memcpy (valbuf + argreg_size - len, + (char *) VALUE_CONTENTS (args[argnum]), len); + else + memcpy (valbuf, (char *) VALUE_CONTENTS (args[argnum]), len); + + val = valbuf; + } + else + val = (char *) VALUE_CONTENTS (args[argnum]); + + while (len > 0) + { + if (int_argreg > ARGLAST_REGNUM) + { + /* must go on the stack */ + write_memory (sp + stack_offset, val, argreg_size); + stack_offset += 8;/*argreg_size;*/ + } + /* NOTE WELL!!!!! This is not an "else if" clause!!! + That's because some *&^%$ things get passed on the stack + AND in the registers! */ + if (int_argreg <= ARGLAST_REGNUM) + { + /* there's room in a register */ + regval = extract_unsigned_integer (val, argreg_size); + write_register (int_argreg, regval); + } + /* Store the value 8 bytes at a time. This means that + things larger than 8 bytes may go partly in registers + and partly on the stack. FIXME: argreg is incremented + before we use its size. */ + len -= argreg_size; + val += argreg_size; + int_argreg++; + } + } + else + { + val = (char *) VALUE_CONTENTS (args[argnum]); + if (len == 4) + { + /* Where is it going to be stored? */ + while (fp_args[float_arg_index]) + float_arg_index ++; + + /* Now float_argreg points to the register where it + should be stored. Are we still within the allowed + register set? */ + if (float_arg_index <= FLOAT_ARGLAST_REGNUM) + { + /* Goes in FR0...FR11 */ + deprecated_write_register_gen (FP0_REGNUM + float_arg_index, + val); + fp_args[float_arg_index] = 1; + /* Skip the corresponding general argument register. */ + int_argreg ++; + } + else + ; + /* Store it as the integers, 8 bytes at the time, if + necessary spilling on the stack. */ + + } + else if (len == 8) + { + /* Where is it going to be stored? */ + while (fp_args[double_arg_index]) + double_arg_index += 2; + /* Now double_argreg points to the register + where it should be stored. + Are we still within the allowed register set? */ + if (double_arg_index < FLOAT_ARGLAST_REGNUM) + { + /* Goes in DR0...DR10 */ + /* The numbering of the DRi registers is consecutive, + i.e. includes odd numbers. */ + int double_register_offset = double_arg_index / 2; + int regnum = DR0_REGNUM + + double_register_offset; +#if 0 + if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE) + { + memset (valbuf_tmp, 0, sizeof (valbuf_tmp)); + DEPRECATED_REGISTER_CONVERT_TO_VIRTUAL (regnum, + type, val, + valbuf_tmp); + val = valbuf_tmp; + } +#endif + /* Note: must use write_register_gen here instead + of regcache_raw_write, because + regcache_raw_write works only for real + registers, not pseudo. write_register_gen will + call the gdbarch function to do register + writes, and that will properly know how to deal + with pseudoregs. */ + deprecated_write_register_gen (regnum, val); + fp_args[double_arg_index] = 1; + fp_args[double_arg_index + 1] = 1; + /* Skip the corresponding general argument register. */ + int_argreg ++; + } + else + ; + /* Store it as the integers, 8 bytes at the time, if + necessary spilling on the stack. */ + } + } + } + return sp; +} + +/* Function: push_return_address (pc) + Set up the return address for the inferior function call. + Needed for targets where we don't actually execute a JSR/BSR instruction */ + +static CORE_ADDR +sh64_push_return_address (CORE_ADDR pc, CORE_ADDR sp) +{ + write_register (PR_REGNUM, entry_point_address ()); + return sp; +} + +/* Find a function's return value in the appropriate registers (in + regbuf), and copy it into valbuf. Extract from an array REGBUF + containing the (raw) register state a function return value of type + TYPE, and copy that, in virtual format, into VALBUF. */ +static void +sh64_extract_return_value (struct type *type, char *regbuf, char *valbuf) +{ + int offset; + int return_register; + int len = TYPE_LENGTH (type); + + if (TYPE_CODE (type) == TYPE_CODE_FLT) + { + if (len == 4) + { + /* Return value stored in FP0_REGNUM */ + return_register = FP0_REGNUM; + offset = DEPRECATED_REGISTER_BYTE (return_register); + memcpy (valbuf, (char *) regbuf + offset, len); + } + else if (len == 8) + { + /* return value stored in DR0_REGNUM */ + DOUBLEST val; + + return_register = DR0_REGNUM; + offset = DEPRECATED_REGISTER_BYTE (return_register); + + if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE) + floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword, + (char *) regbuf + offset, &val); + else + floatformat_to_doublest (&floatformat_ieee_double_big, + (char *) regbuf + offset, &val); + store_typed_floating (valbuf, type, val); + } + } + else + { + if (len <= 8) + { + /* Result is in register 2. If smaller than 8 bytes, it is padded + at the most significant end. */ + return_register = DEFAULT_RETURN_REGNUM; + if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) + offset = DEPRECATED_REGISTER_BYTE (return_register) + + register_size (current_gdbarch, return_register) - len; + else + offset = DEPRECATED_REGISTER_BYTE (return_register); + memcpy (valbuf, (char *) regbuf + offset, len); + } + else + error ("bad size for return value"); + } +} + +/* Write into appropriate registers a function return value + of type TYPE, given in virtual format. + If the architecture is sh4 or sh3e, store a function's return value + in the R0 general register or in the FP0 floating point register, + depending on the type of the return value. In all the other cases + the result is stored in r0, left-justified. */ + +static void +sh64_store_return_value (struct type *type, char *valbuf) +{ + char buf[64]; /* more than enough... */ + int len = TYPE_LENGTH (type); + + if (TYPE_CODE (type) == TYPE_CODE_FLT) + { + if (len == 4) + { + /* Return value stored in FP0_REGNUM */ + deprecated_write_register_gen (FP0_REGNUM, valbuf); + } + if (len == 8) + { + /* return value stored in DR0_REGNUM */ + /* FIXME: Implement */ + } + } + else + { + int return_register = DEFAULT_RETURN_REGNUM; + int offset = 0; + + if (len <= register_size (current_gdbarch, return_register)) + { + /* Pad with zeros. */ + memset (buf, 0, register_size (current_gdbarch, return_register)); + if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE) + offset = 0; /*register_size (current_gdbarch, + return_register) - len;*/ + else + offset = register_size (current_gdbarch, return_register) - len; + + memcpy (buf + offset, valbuf, len); + deprecated_write_register_gen (return_register, buf); + } + else + deprecated_write_register_gen (return_register, valbuf); + } +} + +static void +sh64_show_media_regs (void) +{ + int i; + + printf_filtered ("PC=%s SR=%016llx \n", + paddr (read_register (PC_REGNUM)), + (long long) read_register (SR_REGNUM)); + + printf_filtered ("SSR=%016llx SPC=%016llx \n", + (long long) read_register (SSR_REGNUM), + (long long) read_register (SPC_REGNUM)); + printf_filtered ("FPSCR=%016lx\n ", + (long) read_register (FPSCR_REGNUM)); + + for (i = 0; i < 64; i = i + 4) + printf_filtered ("\nR%d-R%d %016llx %016llx %016llx %016llx\n", + i, i + 3, + (long long) read_register (i + 0), + (long long) read_register (i + 1), + (long long) read_register (i + 2), + (long long) read_register (i + 3)); + + printf_filtered ("\n"); + + for (i = 0; i < 64; i = i + 8) + printf_filtered ("FR%d-FR%d %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", + i, i + 7, + (long) read_register (FP0_REGNUM + i + 0), + (long) read_register (FP0_REGNUM + i + 1), + (long) read_register (FP0_REGNUM + i + 2), + (long) read_register (FP0_REGNUM + i + 3), + (long) read_register (FP0_REGNUM + i + 4), + (long) read_register (FP0_REGNUM + i + 5), + (long) read_register (FP0_REGNUM + i + 6), + (long) read_register (FP0_REGNUM + i + 7)); +} + +static void +sh64_show_compact_regs (void) +{ + int i; + + printf_filtered ("PC=%s \n", + paddr (read_register (PC_C_REGNUM))); + + printf_filtered ("GBR=%08lx MACH=%08lx MACL=%08lx PR=%08lx T=%08lx\n", + (long) read_register (GBR_C_REGNUM), + (long) read_register (MACH_C_REGNUM), + (long) read_register (MACL_C_REGNUM), + (long) read_register (PR_C_REGNUM), + (long) read_register (T_C_REGNUM)); + printf_filtered ("FPSCR=%08lx FPUL=%08lx\n", + (long) read_register (FPSCR_C_REGNUM), + (long) read_register (FPUL_C_REGNUM)); + + for (i = 0; i < 16; i = i + 4) + printf_filtered ("\nR%d-R%d %08lx %08lx %08lx %08lx\n", + i, i + 3, + (long) read_register (i + 0), + (long) read_register (i + 1), + (long) read_register (i + 2), + (long) read_register (i + 3)); + + printf_filtered ("\n"); + + for (i = 0; i < 16; i = i + 8) + printf_filtered ("FR%d-FR%d %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", + i, i + 7, + (long) read_register (FP0_REGNUM + i + 0), + (long) read_register (FP0_REGNUM + i + 1), + (long) read_register (FP0_REGNUM + i + 2), + (long) read_register (FP0_REGNUM + i + 3), + (long) read_register (FP0_REGNUM + i + 4), + (long) read_register (FP0_REGNUM + i + 5), + (long) read_register (FP0_REGNUM + i + 6), + (long) read_register (FP0_REGNUM + i + 7)); +} + +/* FIXME!!! This only shows the registers for shmedia, excluding the + pseudo registers. */ +void +sh64_show_regs (void) +{ + if (deprecated_selected_frame + && pc_is_isa32 (get_frame_pc (deprecated_selected_frame))) + sh64_show_media_regs (); + else + sh64_show_compact_regs (); +} + +/* *INDENT-OFF* */ +/* + SH MEDIA MODE (ISA 32) + general registers (64-bit) 0-63 +0 r0, r1, r2, r3, r4, r5, r6, r7, +64 r8, r9, r10, r11, r12, r13, r14, r15, +128 r16, r17, r18, r19, r20, r21, r22, r23, +192 r24, r25, r26, r27, r28, r29, r30, r31, +256 r32, r33, r34, r35, r36, r37, r38, r39, +320 r40, r41, r42, r43, r44, r45, r46, r47, +384 r48, r49, r50, r51, r52, r53, r54, r55, +448 r56, r57, r58, r59, r60, r61, r62, r63, + + pc (64-bit) 64 +512 pc, + + status reg., saved status reg., saved pc reg. (64-bit) 65-67 +520 sr, ssr, spc, + + target registers (64-bit) 68-75 +544 tr0, tr1, tr2, tr3, tr4, tr5, tr6, tr7, + + floating point state control register (32-bit) 76 +608 fpscr, + + single precision floating point registers (32-bit) 77-140 +612 fr0, fr1, fr2, fr3, fr4, fr5, fr6, fr7, +644 fr8, fr9, fr10, fr11, fr12, fr13, fr14, fr15, +676 fr16, fr17, fr18, fr19, fr20, fr21, fr22, fr23, +708 fr24, fr25, fr26, fr27, fr28, fr29, fr30, fr31, +740 fr32, fr33, fr34, fr35, fr36, fr37, fr38, fr39, +772 fr40, fr41, fr42, fr43, fr44, fr45, fr46, fr47, +804 fr48, fr49, fr50, fr51, fr52, fr53, fr54, fr55, +836 fr56, fr57, fr58, fr59, fr60, fr61, fr62, fr63, + +TOTAL SPACE FOR REGISTERS: 868 bytes + +From here on they are all pseudo registers: no memory allocated. +REGISTER_BYTE returns the register byte for the base register. + + double precision registers (pseudo) 141-172 + dr0, dr2, dr4, dr6, dr8, dr10, dr12, dr14, + dr16, dr18, dr20, dr22, dr24, dr26, dr28, dr30, + dr32, dr34, dr36, dr38, dr40, dr42, dr44, dr46, + dr48, dr50, dr52, dr54, dr56, dr58, dr60, dr62, + + floating point pairs (pseudo) 173-204 + fp0, fp2, fp4, fp6, fp8, fp10, fp12, fp14, + fp16, fp18, fp20, fp22, fp24, fp26, fp28, fp30, + fp32, fp34, fp36, fp38, fp40, fp42, fp44, fp46, + fp48, fp50, fp52, fp54, fp56, fp58, fp60, fp62, + + floating point vectors (4 floating point regs) (pseudo) 205-220 + fv0, fv4, fv8, fv12, fv16, fv20, fv24, fv28, + fv32, fv36, fv40, fv44, fv48, fv52, fv56, fv60, + + SH COMPACT MODE (ISA 16) (all pseudo) 221-272 + r0_c, r1_c, r2_c, r3_c, r4_c, r5_c, r6_c, r7_c, + r8_c, r9_c, r10_c, r11_c, r12_c, r13_c, r14_c, r15_c, + pc_c, + gbr_c, mach_c, macl_c, pr_c, t_c, + fpscr_c, fpul_c, + fr0_c, fr1_c, fr2_c, fr3_c, fr4_c, fr5_c, fr6_c, fr7_c, + fr8_c, fr9_c, fr10_c, fr11_c, fr12_c, fr13_c, fr14_c, fr15_c + dr0_c, dr2_c, dr4_c, dr6_c, dr8_c, dr10_c, dr12_c, dr14_c + fv0_c, fv4_c, fv8_c, fv12_c +*/ +/* *INDENT-ON* */ +static int +sh64_register_byte (int reg_nr) +{ + int base_regnum = -1; + + /* If it is a pseudo register, get the number of the first floating + point register that is part of it. */ + if (reg_nr >= DR0_REGNUM + && reg_nr <= DR_LAST_REGNUM) + base_regnum = dr_reg_base_num (reg_nr); + + else if (reg_nr >= FPP0_REGNUM + && reg_nr <= FPP_LAST_REGNUM) + base_regnum = fpp_reg_base_num (reg_nr); + + else if (reg_nr >= FV0_REGNUM + && reg_nr <= FV_LAST_REGNUM) + base_regnum = fv_reg_base_num (reg_nr); + + /* sh compact pseudo register. FPSCR is a pathological case, need to + treat it as special. */ + else if ((reg_nr >= R0_C_REGNUM + && reg_nr <= FV_LAST_C_REGNUM) + && reg_nr != FPSCR_C_REGNUM) + base_regnum = sh64_compact_reg_base_num (reg_nr); + + /* Now return the offset in bytes within the register cache. */ + /* sh media pseudo register, i.e. any of DR, FFP, FV registers. */ + if (reg_nr >= DR0_REGNUM + && reg_nr <= FV_LAST_REGNUM) + return (base_regnum - FP0_REGNUM + 1) * 4 + + (TR7_REGNUM + 1) * 8; + + /* sh compact pseudo register: general register */ + if ((reg_nr >= R0_C_REGNUM + && reg_nr <= R_LAST_C_REGNUM)) + return (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG + ? base_regnum * 8 + 4 + : base_regnum * 8); + + /* sh compact pseudo register: */ + if (reg_nr == PC_C_REGNUM + || reg_nr == GBR_C_REGNUM + || reg_nr == MACL_C_REGNUM + || reg_nr == PR_C_REGNUM) + return (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG + ? base_regnum * 8 + 4 + : base_regnum * 8); + + if (reg_nr == MACH_C_REGNUM) + return base_regnum * 8; + + if (reg_nr == T_C_REGNUM) + return base_regnum * 8; /* FIXME??? how do we get bit 0? Do we have to? */ + + /* sh compact pseudo register: floating point register */ + else if (reg_nr >= FP0_C_REGNUM + && reg_nr <= FV_LAST_C_REGNUM) + return (base_regnum - FP0_REGNUM) * 4 + + (TR7_REGNUM + 1) * 8 + 4; + + else if (reg_nr == FPSCR_C_REGNUM) + /* This is complicated, for now return the beginning of the + architectural FPSCR register. */ + return (TR7_REGNUM + 1) * 8; + + else if (reg_nr == FPUL_C_REGNUM) + return ((base_regnum - FP0_REGNUM) * 4 + + (TR7_REGNUM + 1) * 8 + 4); + + /* It is not a pseudo register. */ + /* It is a 64 bit register. */ + else if (reg_nr <= TR7_REGNUM) + return reg_nr * 8; + + /* It is a 32 bit register. */ + else if (reg_nr == FPSCR_REGNUM) + return (FPSCR_REGNUM * 8); + + /* It is floating point 32-bit register */ + else + return ((TR7_REGNUM + 1) * 8 + + (reg_nr - FP0_REGNUM + 1) * 4); +} + +static struct type * +sh64_build_float_register_type (int high) +{ + struct type *temp; + + temp = create_range_type (NULL, builtin_type_int, 0, high); + return create_array_type (NULL, builtin_type_float, temp); +} + +/* Return the GDB type object for the "standard" data type + of data in register REG_NR. */ +static struct type * +sh64_register_type (struct gdbarch *gdbarch, int reg_nr) +{ + if ((reg_nr >= FP0_REGNUM + && reg_nr <= FP_LAST_REGNUM) + || (reg_nr >= FP0_C_REGNUM + && reg_nr <= FP_LAST_C_REGNUM)) + return builtin_type_float; + else if ((reg_nr >= DR0_REGNUM + && reg_nr <= DR_LAST_REGNUM) + || (reg_nr >= DR0_C_REGNUM + && reg_nr <= DR_LAST_C_REGNUM)) + return builtin_type_double; + else if (reg_nr >= FPP0_REGNUM + && reg_nr <= FPP_LAST_REGNUM) + return sh64_build_float_register_type (1); + else if ((reg_nr >= FV0_REGNUM + && reg_nr <= FV_LAST_REGNUM) + ||(reg_nr >= FV0_C_REGNUM + && reg_nr <= FV_LAST_C_REGNUM)) + return sh64_build_float_register_type (3); + else if (reg_nr == FPSCR_REGNUM) + return builtin_type_int; + else if (reg_nr >= R0_C_REGNUM + && reg_nr < FP0_C_REGNUM) + return builtin_type_int; + else + return builtin_type_long_long; +} + +static void +sh64_register_convert_to_virtual (int regnum, struct type *type, + char *from, char *to) +{ + if (TARGET_BYTE_ORDER != BFD_ENDIAN_LITTLE) + { + /* It is a no-op. */ + memcpy (to, from, register_size (current_gdbarch, regnum)); + return; + } + + if ((regnum >= DR0_REGNUM + && regnum <= DR_LAST_REGNUM) + || (regnum >= DR0_C_REGNUM + && regnum <= DR_LAST_C_REGNUM)) + { + DOUBLEST val; + floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword, + from, &val); + store_typed_floating (to, type, val); + } + else + error ("sh64_register_convert_to_virtual called with non DR register number"); +} + +static void +sh64_register_convert_to_raw (struct type *type, int regnum, + const void *from, void *to) +{ + if (TARGET_BYTE_ORDER != BFD_ENDIAN_LITTLE) + { + /* It is a no-op. */ + memcpy (to, from, register_size (current_gdbarch, regnum)); + return; + } + + if ((regnum >= DR0_REGNUM + && regnum <= DR_LAST_REGNUM) + || (regnum >= DR0_C_REGNUM + && regnum <= DR_LAST_C_REGNUM)) + { + DOUBLEST val = deprecated_extract_floating (from, TYPE_LENGTH(type)); + floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword, + &val, to); + } + else + error ("sh64_register_convert_to_raw called with non DR register number"); +} + +static void +sh64_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, + int reg_nr, void *buffer) +{ + int base_regnum; + int portion; + int offset = 0; + char temp_buffer[MAX_REGISTER_SIZE]; + + if (reg_nr >= DR0_REGNUM + && reg_nr <= DR_LAST_REGNUM) + { + base_regnum = dr_reg_base_num (reg_nr); + + /* Build the value in the provided buffer. */ + /* DR regs are double precision registers obtained by + concatenating 2 single precision floating point registers. */ + for (portion = 0; portion < 2; portion++) + regcache_raw_read (regcache, base_regnum + portion, + (temp_buffer + + register_size (gdbarch, base_regnum) * portion)); + + /* We must pay attention to the endianness. */ + sh64_register_convert_to_virtual (reg_nr, + gdbarch_register_type (gdbarch, + reg_nr), + temp_buffer, buffer); + + } + + else if (reg_nr >= FPP0_REGNUM + && reg_nr <= FPP_LAST_REGNUM) + { + base_regnum = fpp_reg_base_num (reg_nr); + + /* Build the value in the provided buffer. */ + /* FPP regs are pairs of single precision registers obtained by + concatenating 2 single precision floating point registers. */ + for (portion = 0; portion < 2; portion++) + regcache_raw_read (regcache, base_regnum + portion, + ((char *) buffer + + register_size (gdbarch, base_regnum) * portion)); + } + + else if (reg_nr >= FV0_REGNUM + && reg_nr <= FV_LAST_REGNUM) + { + base_regnum = fv_reg_base_num (reg_nr); + + /* Build the value in the provided buffer. */ + /* FV regs are vectors of single precision registers obtained by + concatenating 4 single precision floating point registers. */ + for (portion = 0; portion < 4; portion++) + regcache_raw_read (regcache, base_regnum + portion, + ((char *) buffer + + register_size (gdbarch, base_regnum) * portion)); + } + + /* sh compact pseudo registers. 1-to-1 with a shmedia register */ + else if (reg_nr >= R0_C_REGNUM + && reg_nr <= T_C_REGNUM) + { + base_regnum = sh64_compact_reg_base_num (reg_nr); + + /* Build the value in the provided buffer. */ + regcache_raw_read (regcache, base_regnum, temp_buffer); + if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) + offset = 4; + memcpy (buffer, temp_buffer + offset, 4); /* get LOWER 32 bits only????*/ + } + + else if (reg_nr >= FP0_C_REGNUM + && reg_nr <= FP_LAST_C_REGNUM) + { + base_regnum = sh64_compact_reg_base_num (reg_nr); + + /* Build the value in the provided buffer. */ + /* Floating point registers map 1-1 to the media fp regs, + they have the same size and endianness. */ + regcache_raw_read (regcache, base_regnum, buffer); + } + + else if (reg_nr >= DR0_C_REGNUM + && reg_nr <= DR_LAST_C_REGNUM) + { + base_regnum = sh64_compact_reg_base_num (reg_nr); + + /* DR_C regs are double precision registers obtained by + concatenating 2 single precision floating point registers. */ + for (portion = 0; portion < 2; portion++) + regcache_raw_read (regcache, base_regnum + portion, + (temp_buffer + + register_size (gdbarch, base_regnum) * portion)); + + /* We must pay attention to the endianness. */ + sh64_register_convert_to_virtual (reg_nr, + gdbarch_register_type (gdbarch, + reg_nr), + temp_buffer, buffer); + } + + else if (reg_nr >= FV0_C_REGNUM + && reg_nr <= FV_LAST_C_REGNUM) + { + base_regnum = sh64_compact_reg_base_num (reg_nr); + + /* Build the value in the provided buffer. */ + /* FV_C regs are vectors of single precision registers obtained by + concatenating 4 single precision floating point registers. */ + for (portion = 0; portion < 4; portion++) + regcache_raw_read (regcache, base_regnum + portion, + ((char *) buffer + + register_size (gdbarch, base_regnum) * portion)); + } + + else if (reg_nr == FPSCR_C_REGNUM) + { + int fpscr_base_regnum; + int sr_base_regnum; + unsigned int fpscr_value; + unsigned int sr_value; + unsigned int fpscr_c_value; + unsigned int fpscr_c_part1_value; + unsigned int fpscr_c_part2_value; + + fpscr_base_regnum = FPSCR_REGNUM; + sr_base_regnum = SR_REGNUM; + + /* Build the value in the provided buffer. */ + /* FPSCR_C is a very weird register that contains sparse bits + from the FPSCR and the SR architectural registers. + Specifically: */ + /* *INDENT-OFF* */ + /* + FPSRC_C bit + 0 Bit 0 of FPSCR + 1 reserved + 2-17 Bit 2-18 of FPSCR + 18-20 Bits 12,13,14 of SR + 21-31 reserved + */ + /* *INDENT-ON* */ + /* Get FPSCR into a local buffer */ + regcache_raw_read (regcache, fpscr_base_regnum, temp_buffer); + /* Get value as an int. */ + fpscr_value = extract_unsigned_integer (temp_buffer, 4); + /* Get SR into a local buffer */ + regcache_raw_read (regcache, sr_base_regnum, temp_buffer); + /* Get value as an int. */ + sr_value = extract_unsigned_integer (temp_buffer, 4); + /* Build the new value. */ + fpscr_c_part1_value = fpscr_value & 0x3fffd; + fpscr_c_part2_value = (sr_value & 0x7000) << 6; + fpscr_c_value = fpscr_c_part1_value | fpscr_c_part2_value; + /* Store that in out buffer!!! */ + store_unsigned_integer (buffer, 4, fpscr_c_value); + /* FIXME There is surely an endianness gotcha here. */ + } + + else if (reg_nr == FPUL_C_REGNUM) + { + base_regnum = sh64_compact_reg_base_num (reg_nr); + + /* FPUL_C register is floating point register 32, + same size, same endianness. */ + regcache_raw_read (regcache, base_regnum, buffer); + } +} + +static void +sh64_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, + int reg_nr, const void *buffer) +{ + int base_regnum, portion; + int offset; + char temp_buffer[MAX_REGISTER_SIZE]; + + if (reg_nr >= DR0_REGNUM + && reg_nr <= DR_LAST_REGNUM) + { + base_regnum = dr_reg_base_num (reg_nr); + /* We must pay attention to the endianness. */ + sh64_register_convert_to_raw (gdbarch_register_type (gdbarch, reg_nr), + reg_nr, + buffer, temp_buffer); + + /* Write the real regs for which this one is an alias. */ + for (portion = 0; portion < 2; portion++) + regcache_raw_write (regcache, base_regnum + portion, + (temp_buffer + + register_size (gdbarch, + base_regnum) * portion)); + } + + else if (reg_nr >= FPP0_REGNUM + && reg_nr <= FPP_LAST_REGNUM) + { + base_regnum = fpp_reg_base_num (reg_nr); + + /* Write the real regs for which this one is an alias. */ + for (portion = 0; portion < 2; portion++) + regcache_raw_write (regcache, base_regnum + portion, + ((char *) buffer + + register_size (gdbarch, + base_regnum) * portion)); + } + + else if (reg_nr >= FV0_REGNUM + && reg_nr <= FV_LAST_REGNUM) + { + base_regnum = fv_reg_base_num (reg_nr); + + /* Write the real regs for which this one is an alias. */ + for (portion = 0; portion < 4; portion++) + regcache_raw_write (regcache, base_regnum + portion, + ((char *) buffer + + register_size (gdbarch, + base_regnum) * portion)); + } + + /* sh compact general pseudo registers. 1-to-1 with a shmedia + register but only 4 bytes of it. */ + else if (reg_nr >= R0_C_REGNUM + && reg_nr <= T_C_REGNUM) + { + base_regnum = sh64_compact_reg_base_num (reg_nr); + /* reg_nr is 32 bit here, and base_regnum is 64 bits. */ + if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) + offset = 4; + else + offset = 0; + /* Let's read the value of the base register into a temporary + buffer, so that overwriting the last four bytes with the new + value of the pseudo will leave the upper 4 bytes unchanged. */ + regcache_raw_read (regcache, base_regnum, temp_buffer); + /* Write as an 8 byte quantity */ + memcpy (temp_buffer + offset, buffer, 4); + regcache_raw_write (regcache, base_regnum, temp_buffer); + } + + /* sh floating point compact pseudo registers. 1-to-1 with a shmedia + registers. Both are 4 bytes. */ + else if (reg_nr >= FP0_C_REGNUM + && reg_nr <= FP_LAST_C_REGNUM) + { + base_regnum = sh64_compact_reg_base_num (reg_nr); + regcache_raw_write (regcache, base_regnum, buffer); + } + + else if (reg_nr >= DR0_C_REGNUM + && reg_nr <= DR_LAST_C_REGNUM) + { + base_regnum = sh64_compact_reg_base_num (reg_nr); + for (portion = 0; portion < 2; portion++) + { + /* We must pay attention to the endianness. */ + sh64_register_convert_to_raw (gdbarch_register_type (gdbarch, + reg_nr), + reg_nr, + buffer, temp_buffer); + + regcache_raw_write (regcache, base_regnum + portion, + (temp_buffer + + register_size (gdbarch, + base_regnum) * portion)); + } + } + + else if (reg_nr >= FV0_C_REGNUM + && reg_nr <= FV_LAST_C_REGNUM) + { + base_regnum = sh64_compact_reg_base_num (reg_nr); + + for (portion = 0; portion < 4; portion++) + { + regcache_raw_write (regcache, base_regnum + portion, + ((char *) buffer + + register_size (gdbarch, + base_regnum) * portion)); + } + } + + else if (reg_nr == FPSCR_C_REGNUM) + { + int fpscr_base_regnum; + int sr_base_regnum; + unsigned int fpscr_value; + unsigned int sr_value; + unsigned int old_fpscr_value; + unsigned int old_sr_value; + unsigned int fpscr_c_value; + unsigned int fpscr_mask; + unsigned int sr_mask; + + fpscr_base_regnum = FPSCR_REGNUM; + sr_base_regnum = SR_REGNUM; + + /* FPSCR_C is a very weird register that contains sparse bits + from the FPSCR and the SR architectural registers. + Specifically: */ + /* *INDENT-OFF* */ + /* + FPSRC_C bit + 0 Bit 0 of FPSCR + 1 reserved + 2-17 Bit 2-18 of FPSCR + 18-20 Bits 12,13,14 of SR + 21-31 reserved + */ + /* *INDENT-ON* */ + /* Get value as an int. */ + fpscr_c_value = extract_unsigned_integer (buffer, 4); + + /* Build the new values. */ + fpscr_mask = 0x0003fffd; + sr_mask = 0x001c0000; + + fpscr_value = fpscr_c_value & fpscr_mask; + sr_value = (fpscr_value & sr_mask) >> 6; + + regcache_raw_read (regcache, fpscr_base_regnum, temp_buffer); + old_fpscr_value = extract_unsigned_integer (temp_buffer, 4); + old_fpscr_value &= 0xfffc0002; + fpscr_value |= old_fpscr_value; + store_unsigned_integer (temp_buffer, 4, fpscr_value); + regcache_raw_write (regcache, fpscr_base_regnum, temp_buffer); + + regcache_raw_read (regcache, sr_base_regnum, temp_buffer); + old_sr_value = extract_unsigned_integer (temp_buffer, 4); + old_sr_value &= 0xffff8fff; + sr_value |= old_sr_value; + store_unsigned_integer (temp_buffer, 4, sr_value); + regcache_raw_write (regcache, sr_base_regnum, temp_buffer); + } + + else if (reg_nr == FPUL_C_REGNUM) + { + base_regnum = sh64_compact_reg_base_num (reg_nr); + regcache_raw_write (regcache, base_regnum, buffer); + } +} + +/* Floating point vector of 4 float registers. */ +static void +do_fv_register_info (struct gdbarch *gdbarch, struct ui_file *file, + int fv_regnum) +{ + int first_fp_reg_num = fv_reg_base_num (fv_regnum); + fprintf_filtered (file, "fv%d\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n", + fv_regnum - FV0_REGNUM, + (int) read_register (first_fp_reg_num), + (int) read_register (first_fp_reg_num + 1), + (int) read_register (first_fp_reg_num + 2), + (int) read_register (first_fp_reg_num + 3)); +} + +/* Floating point vector of 4 float registers, compact mode. */ +static void +do_fv_c_register_info (int fv_regnum) +{ + int first_fp_reg_num = sh64_compact_reg_base_num (fv_regnum); + printf_filtered ("fv%d_c\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n", + fv_regnum - FV0_C_REGNUM, + (int) read_register (first_fp_reg_num), + (int) read_register (first_fp_reg_num + 1), + (int) read_register (first_fp_reg_num + 2), + (int) read_register (first_fp_reg_num + 3)); +} + +/* Pairs of single regs. The DR are instead double precision + registers. */ +static void +do_fpp_register_info (int fpp_regnum) +{ + int first_fp_reg_num = fpp_reg_base_num (fpp_regnum); + + printf_filtered ("fpp%d\t0x%08x\t0x%08x\n", + fpp_regnum - FPP0_REGNUM, + (int) read_register (first_fp_reg_num), + (int) read_register (first_fp_reg_num + 1)); +} + +/* Double precision registers. */ +static void +do_dr_register_info (struct gdbarch *gdbarch, struct ui_file *file, + int dr_regnum) +{ + int first_fp_reg_num = dr_reg_base_num (dr_regnum); + + fprintf_filtered (file, "dr%d\t0x%08x%08x\n", + dr_regnum - DR0_REGNUM, + (int) read_register (first_fp_reg_num), + (int) read_register (first_fp_reg_num + 1)); +} + +/* Double precision registers, compact mode. */ +static void +do_dr_c_register_info (int dr_regnum) +{ + int first_fp_reg_num = sh64_compact_reg_base_num (dr_regnum); + + printf_filtered ("dr%d_c\t0x%08x%08x\n", + dr_regnum - DR0_C_REGNUM, + (int) read_register (first_fp_reg_num), + (int) read_register (first_fp_reg_num +1)); +} + +/* General register in compact mode. */ +static void +do_r_c_register_info (int r_c_regnum) +{ + int regnum = sh64_compact_reg_base_num (r_c_regnum); + + printf_filtered ("r%d_c\t0x%08x\n", + r_c_regnum - R0_C_REGNUM, + /*FIXME!!!*/ (int) read_register (regnum)); +} + +/* FIXME:!! THIS SHOULD TAKE CARE OF GETTING THE RIGHT PORTION OF THE + shmedia REGISTERS. */ +/* Control registers, compact mode. */ +static void +do_cr_c_register_info (int cr_c_regnum) +{ + switch (cr_c_regnum) + { + case 237: printf_filtered ("pc_c\t0x%08x\n", (int) read_register (cr_c_regnum)); + break; + case 238: printf_filtered ("gbr_c\t0x%08x\n", (int) read_register (cr_c_regnum)); + break; + case 239: printf_filtered ("mach_c\t0x%08x\n", (int) read_register (cr_c_regnum)); + break; + case 240: printf_filtered ("macl_c\t0x%08x\n", (int) read_register (cr_c_regnum)); + break; + case 241: printf_filtered ("pr_c\t0x%08x\n", (int) read_register (cr_c_regnum)); + break; + case 242: printf_filtered ("t_c\t0x%08x\n", (int) read_register (cr_c_regnum)); + break; + case 243: printf_filtered ("fpscr_c\t0x%08x\n", (int) read_register (cr_c_regnum)); + break; + case 244: printf_filtered ("fpul_c\t0x%08x\n", (int)read_register (cr_c_regnum)); + break; + } +} + +static void +sh_do_fp_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum) +{ /* do values for FP (float) regs */ + char *raw_buffer; + double flt; /* double extracted from raw hex data */ + int inv; + int j; + + /* Allocate space for the float. */ + raw_buffer = (char *) alloca (register_size (gdbarch, FP0_REGNUM)); + + /* Get the data in raw format. */ + if (!frame_register_read (get_selected_frame (), regnum, raw_buffer)) + error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum)); + + /* Get the register as a number */ + flt = unpack_double (builtin_type_float, raw_buffer, &inv); + + /* Print the name and some spaces. */ + fputs_filtered (REGISTER_NAME (regnum), file); + print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), file); + + /* Print the value. */ + if (inv) + fprintf_filtered (file, ""); + else + fprintf_filtered (file, "%-10.9g", flt); + + /* Print the fp register as hex. */ + fprintf_filtered (file, "\t(raw 0x"); + for (j = 0; j < register_size (gdbarch, regnum); j++) + { + int idx = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? j + : register_size (gdbarch, regnum) - 1 - j; + fprintf_filtered (file, "%02x", (unsigned char) raw_buffer[idx]); + } + fprintf_filtered (file, ")"); + fprintf_filtered (file, "\n"); +} + +static void +sh64_do_pseudo_register (int regnum) +{ + /* All the sh64-compact mode registers are pseudo registers. */ + + if (regnum < NUM_REGS + || regnum >= NUM_REGS + NUM_PSEUDO_REGS_SH_MEDIA + NUM_PSEUDO_REGS_SH_COMPACT) + internal_error (__FILE__, __LINE__, + "Invalid pseudo register number %d\n", regnum); + + else if ((regnum >= DR0_REGNUM + && regnum <= DR_LAST_REGNUM)) + do_dr_register_info (current_gdbarch, gdb_stdout, regnum); + + else if ((regnum >= DR0_C_REGNUM + && regnum <= DR_LAST_C_REGNUM)) + do_dr_c_register_info (regnum); + + else if ((regnum >= FV0_REGNUM + && regnum <= FV_LAST_REGNUM)) + do_fv_register_info (current_gdbarch, gdb_stdout, regnum); + + else if ((regnum >= FV0_C_REGNUM + && regnum <= FV_LAST_C_REGNUM)) + do_fv_c_register_info (regnum); + + else if (regnum >= FPP0_REGNUM + && regnum <= FPP_LAST_REGNUM) + do_fpp_register_info (regnum); + + else if (regnum >= R0_C_REGNUM + && regnum <= R_LAST_C_REGNUM) + /* FIXME, this function will not print the right format. */ + do_r_c_register_info (regnum); + else if (regnum >= FP0_C_REGNUM + && regnum <= FP_LAST_C_REGNUM) + /* This should work also for pseudoregs. */ + sh_do_fp_register (current_gdbarch, gdb_stdout, regnum); + else if (regnum >= PC_C_REGNUM + && regnum <= FPUL_C_REGNUM) + do_cr_c_register_info (regnum); +} + +static void +sh_do_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum) +{ + char raw_buffer[MAX_REGISTER_SIZE]; + + fputs_filtered (REGISTER_NAME (regnum), file); + print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), file); + + /* Get the data in raw format. */ + if (!frame_register_read (get_selected_frame (), regnum, raw_buffer)) + fprintf_filtered (file, "*value not available*\n"); + + val_print (gdbarch_register_type (gdbarch, regnum), raw_buffer, 0, 0, + file, 'x', 1, 0, Val_pretty_default); + fprintf_filtered (file, "\t"); + val_print (gdbarch_register_type (gdbarch, regnum), raw_buffer, 0, 0, + file, 0, 1, 0, Val_pretty_default); + fprintf_filtered (file, "\n"); +} + +static void +sh_print_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum) +{ + if (regnum < 0 || regnum >= NUM_REGS + NUM_PSEUDO_REGS) + internal_error (__FILE__, __LINE__, + "Invalid register number %d\n", regnum); + + else if (regnum >= 0 && regnum < NUM_REGS) + { + if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == TYPE_CODE_FLT) + sh_do_fp_register (gdbarch, file, regnum); /* FP regs */ + else + sh_do_register (gdbarch, file, regnum); /* All other regs */ + } + + else if (regnum < NUM_REGS + NUM_PSEUDO_REGS) + sh64_do_pseudo_register (regnum); +} + +static void +sh_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, + struct frame_info *frame, int regnum, int fpregs) +{ + if (regnum != -1) /* do one specified register */ + { + if (*(REGISTER_NAME (regnum)) == '\0') + error ("Not a valid register for the current processor type"); + + sh_print_register (gdbarch, file, regnum); + } + else + /* do all (or most) registers */ + { + regnum = 0; + while (regnum < NUM_REGS) + { + /* If the register name is empty, it is undefined for this + processor, so don't display anything. */ + if (REGISTER_NAME (regnum) == NULL + || *(REGISTER_NAME (regnum)) == '\0') + { + regnum++; + continue; + } + + if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == TYPE_CODE_FLT) + { + if (fpregs) + { + /* true for "INFO ALL-REGISTERS" command */ + sh_do_fp_register (gdbarch, file, regnum); /* FP regs */ + regnum ++; + } + else + regnum += FP_LAST_REGNUM - FP0_REGNUM; /* skip FP regs */ + } + else + { + sh_do_register (gdbarch, file, regnum); /* All other regs */ + regnum++; + } + } + + if (fpregs) + while (regnum < NUM_REGS + NUM_PSEUDO_REGS) + { + sh64_do_pseudo_register (regnum); + regnum++; + } + } +} + +static void +sh_compact_do_registers_info (int regnum, int fpregs) +{ + if (regnum != -1) /* do one specified register */ + { + if (*(REGISTER_NAME (regnum)) == '\0') + error ("Not a valid register for the current processor type"); + + if (regnum >= 0 && regnum < R0_C_REGNUM) + error ("Not a valid register for the current processor mode."); + + sh_print_register (current_gdbarch, gdb_stdout, regnum); + } + else + /* do all compact registers */ + { + regnum = R0_C_REGNUM; + while (regnum < NUM_REGS + NUM_PSEUDO_REGS) + { + sh64_do_pseudo_register (regnum); + regnum++; + } + } +} + +static void +sh64_do_registers_info (int regnum, int fpregs) +{ + if (pc_is_isa32 (get_frame_pc (deprecated_selected_frame))) + sh_print_registers_info (current_gdbarch, gdb_stdout, + deprecated_selected_frame, regnum, fpregs); + else + sh_compact_do_registers_info (regnum, fpregs); +} + +#ifdef SVR4_SHARED_LIBS + +/* Fetch (and possibly build) an appropriate link_map_offsets structure + for native i386 linux targets using the struct offsets defined in + link.h (but without actual reference to that file). + + This makes it possible to access i386-linux shared libraries from + a gdb that was not built on an i386-linux host (for cross debugging). + */ + +struct link_map_offsets * +sh_linux_svr4_fetch_link_map_offsets (void) +{ + static struct link_map_offsets lmo; + static struct link_map_offsets *lmp = 0; + + if (lmp == 0) + { + lmp = &lmo; + + lmo.r_debug_size = 8; /* 20 not actual size but all we need */ + + lmo.r_map_offset = 4; + lmo.r_map_size = 4; + + lmo.link_map_size = 20; /* 552 not actual size but all we need */ + + lmo.l_addr_offset = 0; + lmo.l_addr_size = 4; + + lmo.l_name_offset = 4; + lmo.l_name_size = 4; + + lmo.l_next_offset = 12; + lmo.l_next_size = 4; + + lmo.l_prev_offset = 16; + lmo.l_prev_size = 4; + } + + return lmp; +} +#endif /* SVR4_SHARED_LIBS */ + +gdbarch_init_ftype sh64_gdbarch_init; + +struct gdbarch * +sh64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) +{ + static LONGEST sh64_call_dummy_words[] = {0}; + struct gdbarch *gdbarch; + struct gdbarch_tdep *tdep; + + /* If there is already a candidate, use it. */ + arches = gdbarch_list_lookup_by_info (arches, &info); + if (arches != NULL) + return arches->gdbarch; + + /* None found, create a new architecture from the information + provided. */ + tdep = XMALLOC (struct gdbarch_tdep); + gdbarch = gdbarch_alloc (&info, tdep); + + /* NOTE: cagney/2002-12-06: This can be deleted when this arch is + ready to unwind the PC first (see frame.c:get_prev_frame()). */ + set_gdbarch_deprecated_init_frame_pc (gdbarch, deprecated_init_frame_pc_default); + + /* Determine the ABI */ + if (info.abfd && bfd_get_arch_size (info.abfd) == 64) + { + /* If the ABI is the 64-bit one, it can only be sh-media. */ + tdep->sh_abi = SH_ABI_64; + set_gdbarch_ptr_bit (gdbarch, 8 * TARGET_CHAR_BIT); + set_gdbarch_long_bit (gdbarch, 8 * TARGET_CHAR_BIT); + } + else + { + /* If the ABI is the 32-bit one it could be either media or + compact. */ + tdep->sh_abi = SH_ABI_32; + set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT); + set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT); + } + + set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT); + set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT); + set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT); + set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT); + set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); + set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); + + set_gdbarch_sp_regnum (gdbarch, 15); + set_gdbarch_deprecated_fp_regnum (gdbarch, 14); + + set_gdbarch_print_insn (gdbarch, gdb_print_insn_sh); + set_gdbarch_register_sim_regno (gdbarch, legacy_register_sim_regno); + + set_gdbarch_write_pc (gdbarch, generic_target_write_pc); + + set_gdbarch_skip_prologue (gdbarch, sh_skip_prologue); + set_gdbarch_inner_than (gdbarch, core_addr_lessthan); + set_gdbarch_decr_pc_after_break (gdbarch, 0); + set_gdbarch_function_start_offset (gdbarch, 0); + + set_gdbarch_frame_args_skip (gdbarch, 0); + set_gdbarch_frameless_function_invocation (gdbarch, frameless_look_for_prologue); + set_gdbarch_believe_pcc_promotion (gdbarch, 1); + + set_gdbarch_deprecated_frame_saved_pc (gdbarch, sh_frame_saved_pc); + set_gdbarch_deprecated_saved_pc_after_call (gdbarch, sh_saved_pc_after_call); + set_gdbarch_frame_align (gdbarch, sh_frame_align); + + set_gdbarch_num_pseudo_regs (gdbarch, NUM_PSEUDO_REGS_SH_MEDIA + NUM_PSEUDO_REGS_SH_COMPACT); + set_gdbarch_fp0_regnum (gdbarch, SIM_SH64_FR0_REGNUM); + set_gdbarch_pc_regnum (gdbarch, 64); + + /* The number of real registers is the same whether we are in + ISA16(compact) or ISA32(media). */ + set_gdbarch_num_regs (gdbarch, SIM_SH64_NR_REGS); + set_gdbarch_deprecated_register_bytes (gdbarch, + ((SIM_SH64_NR_FP_REGS + 1) * 4) + + (SIM_SH64_NR_REGS - SIM_SH64_NR_FP_REGS -1) * 8); + + set_gdbarch_register_name (gdbarch, sh64_register_name); + set_gdbarch_register_type (gdbarch, sh64_register_type); + set_gdbarch_deprecated_store_return_value (gdbarch, sh64_store_return_value); + set_gdbarch_deprecated_register_byte (gdbarch, sh64_register_byte); + set_gdbarch_pseudo_register_read (gdbarch, sh64_pseudo_register_read); + set_gdbarch_pseudo_register_write (gdbarch, sh64_pseudo_register_write); + + set_gdbarch_deprecated_do_registers_info (gdbarch, sh64_do_registers_info); + set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, sh64_nofp_frame_init_saved_regs); + set_gdbarch_breakpoint_from_pc (gdbarch, sh64_breakpoint_from_pc); + set_gdbarch_deprecated_call_dummy_words (gdbarch, sh64_call_dummy_words); + set_gdbarch_deprecated_sizeof_call_dummy_words (gdbarch, sizeof (sh64_call_dummy_words)); + + set_gdbarch_deprecated_init_extra_frame_info (gdbarch, sh64_init_extra_frame_info); + set_gdbarch_deprecated_frame_chain (gdbarch, sh64_frame_chain); + set_gdbarch_deprecated_get_saved_register (gdbarch, sh64_get_saved_register); + set_gdbarch_deprecated_extract_return_value (gdbarch, sh64_extract_return_value); + set_gdbarch_deprecated_push_arguments (gdbarch, sh64_push_arguments); + set_gdbarch_deprecated_push_return_address (gdbarch, sh64_push_return_address); + set_gdbarch_deprecated_dummy_write_sp (gdbarch, deprecated_write_sp); + set_gdbarch_deprecated_store_struct_return (gdbarch, sh64_store_struct_return); + set_gdbarch_deprecated_extract_struct_value_address (gdbarch, sh64_extract_struct_value_address); + set_gdbarch_use_struct_convention (gdbarch, sh64_use_struct_convention); + set_gdbarch_deprecated_pop_frame (gdbarch, sh64_pop_frame); + set_gdbarch_elf_make_msymbol_special (gdbarch, + sh64_elf_make_msymbol_special); + + /* Hook in ABI-specific overrides, if they have been registered. */ + gdbarch_init_osabi (info, gdbarch); + + return gdbarch; +} diff --git a/gdb/sparc-tdep.h b/gdb/sparc-tdep.h new file mode 100644 index 0000000..7c119b4 --- /dev/null +++ b/gdb/sparc-tdep.h @@ -0,0 +1,22 @@ +/* Target-dependent code for the SPARC for GDB, the GNU debugger. + + Copyright 2003 Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +extern int sparc_y_regnum (void); diff --git a/gdb/sparc64-tdep.c b/gdb/sparc64-tdep.c new file mode 100644 index 0000000..b605a1d --- /dev/null +++ b/gdb/sparc64-tdep.c @@ -0,0 +1,1500 @@ +/* Target-dependent code for UltraSPARC. + + Copyright 2003 Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#include "defs.h" +#include "arch-utils.h" +#include "floatformat.h" +#include "frame.h" +#include "frame-base.h" +#include "frame-unwind.h" +#include "gdbcore.h" +#include "gdbtypes.h" +#include "osabi.h" +#include "regcache.h" +#include "target.h" +#include "value.h" + +#include "gdb_assert.h" +#include "gdb_string.h" + +#include "sparc64-tdep.h" + +/* This file implements the The SPARC 64-bit ABI as defined by the + section "Low-Level System Information" of the SPARC Compliance + Definition (SCD) 2.4.1, which is the 64-bit System V psABI for + SPARC. */ + +/* Please use the sparc32_-prefix for 32-bit specific code, the + sparc64_-prefix for 64-bit specific code and the sparc_-prefix for + code can handle both. */ + +/* The stack pointer is offset from the stack frame by a BIAS of 2047 + (0x7ff) for 64-bit code. BIAS is likely to be defined on SPARC + hosts, so undefine it first. */ +#undef BIAS +#define BIAS 2047 + +/* Macros to extract fields from SPARC instructions. */ +#define X_OP(i) (((i) >> 30) & 0x3) +#define X_A(i) (((i) >> 29) & 1) +#define X_COND(i) (((i) >> 25) & 0xf) +#define X_OP2(i) (((i) >> 22) & 0x7) +#define X_IMM22(i) ((i) & 0x3fffff) +#define X_OP3(i) (((i) >> 19) & 0x3f) +/* Sign extension macros. */ +#define X_DISP22(i) ((X_IMM22 (i) ^ 0x200000) - 0x200000) +#define X_DISP19(i) ((((i) & 0x7ffff) ^ 0x40000) - 0x40000) + +/* Fetch the instruction at PC. Instructions are always big-endian + even if the processor operates in little-endian mode. */ + +static unsigned long +sparc_fetch_instruction (CORE_ADDR pc) +{ + unsigned char buf[4]; + unsigned long insn; + int i; + + read_memory (pc, buf, sizeof (buf)); + + insn = 0; + for (i = 0; i < sizeof (buf); i++) + insn = (insn << 8) | buf[i]; + return insn; +} + +/* The functions on this page are intended to be used to classify + function arguments. */ + +/* Return the contents if register REGNUM as an address. */ + +static CORE_ADDR +sparc_address_from_register (int regnum) +{ + ULONGEST addr; + + regcache_cooked_read_unsigned (current_regcache, regnum, &addr); + return addr; +} + +/* Check whether TYPE is "Integral or Pointer". */ + +static int +sparc64_integral_or_pointer_p (const struct type *type) +{ + switch (TYPE_CODE (type)) + { + case TYPE_CODE_INT: + case TYPE_CODE_BOOL: + case TYPE_CODE_CHAR: + case TYPE_CODE_ENUM: + case TYPE_CODE_RANGE: + { + int len = TYPE_LENGTH (type); + gdb_assert (len == 1 || len == 2 || len == 4 || len == 8); + } + return 1; + case TYPE_CODE_PTR: + case TYPE_CODE_REF: + { + int len = TYPE_LENGTH (type); + gdb_assert (len == 8); + } + return 1; + default: + break; + } + + return 0; +} + +/* Check whether TYPE is "Floating". */ + +static int +sparc64_floating_p (const struct type *type) +{ + switch (TYPE_CODE (type)) + { + case TYPE_CODE_FLT: + { + int len = TYPE_LENGTH (type); + gdb_assert (len == 4 || len == 8 || len == 16); + } + return 1; + default: + break; + } + + return 0; +} + +/* Check whether TYPE is "Structure or Union". */ + +static int +sparc64_structure_or_union_p (const struct type *type) +{ + switch (TYPE_CODE (type)) + { + case TYPE_CODE_STRUCT: + case TYPE_CODE_UNION: + return 1; + default: + break; + } + + return 0; +} + +/* UltraSPARC architecture specific information. */ + +struct gdbarch_tdep +{ + /* Offset of saved PC in jmp_buf. */ + int jb_pc_offset; +}; + +/* Register information. */ + +struct sparc64_register_info +{ + char *name; + struct type **type; +}; + +static struct sparc64_register_info sparc64_register_info[] = +{ + { "g0", &builtin_type_int64 }, + { "g1", &builtin_type_int64 }, + { "g2", &builtin_type_int64 }, + { "g3", &builtin_type_int64 }, + { "g4", &builtin_type_int64 }, + { "g5", &builtin_type_int64 }, + { "g6", &builtin_type_int64 }, + { "g7", &builtin_type_int64 }, + + { "o0", &builtin_type_int64 }, + { "o1", &builtin_type_int64 }, + { "o2", &builtin_type_int64 }, + { "o3", &builtin_type_int64 }, + { "o4", &builtin_type_int64 }, + { "o5", &builtin_type_int64 }, + { "sp", &builtin_type_void_data_ptr }, + { "o7", &builtin_type_int64 }, + + { "l0", &builtin_type_int64 }, + { "l1", &builtin_type_int64 }, + { "l2", &builtin_type_int64 }, + { "l3", &builtin_type_int64 }, + { "l4", &builtin_type_int64 }, + { "l5", &builtin_type_int64 }, + { "l6", &builtin_type_int64 }, + { "l7", &builtin_type_int64 }, + + { "i0", &builtin_type_int64 }, + { "i1", &builtin_type_int64 }, + { "i2", &builtin_type_int64 }, + { "i3", &builtin_type_int64 }, + { "i4", &builtin_type_int64 }, + { "i5", &builtin_type_int64 }, + { "fp", &builtin_type_void_data_ptr }, + { "i7", &builtin_type_int64 }, + + { "f0", &builtin_type_float }, + { "f1", &builtin_type_float }, + { "f2", &builtin_type_float }, + { "f3", &builtin_type_float }, + { "f4", &builtin_type_float }, + { "f5", &builtin_type_float }, + { "f6", &builtin_type_float }, + { "f7", &builtin_type_float }, + { "f8", &builtin_type_float }, + { "f9", &builtin_type_float }, + { "f10", &builtin_type_float }, + { "f11", &builtin_type_float }, + { "f12", &builtin_type_float }, + { "f13", &builtin_type_float }, + { "f14", &builtin_type_float }, + { "f15", &builtin_type_float }, + { "f16", &builtin_type_float }, + { "f17", &builtin_type_float }, + { "f18", &builtin_type_float }, + { "f19", &builtin_type_float }, + { "f20", &builtin_type_float }, + { "f21", &builtin_type_float }, + { "f22", &builtin_type_float }, + { "f23", &builtin_type_float }, + { "f24", &builtin_type_float }, + { "f25", &builtin_type_float }, + { "f26", &builtin_type_float }, + { "f27", &builtin_type_float }, + { "f28", &builtin_type_float }, + { "f29", &builtin_type_float }, + { "f30", &builtin_type_float }, + { "f31", &builtin_type_float }, + { "f32", &builtin_type_double }, + { "f34", &builtin_type_double }, + { "f36", &builtin_type_double }, + { "f38", &builtin_type_double }, + { "f40", &builtin_type_double }, + { "f42", &builtin_type_double }, + { "f44", &builtin_type_double }, + { "f46", &builtin_type_double }, + { "f48", &builtin_type_double }, + { "f50", &builtin_type_double }, + { "f52", &builtin_type_double }, + { "f54", &builtin_type_double }, + { "f56", &builtin_type_double }, + { "f58", &builtin_type_double }, + { "f60", &builtin_type_double }, + { "f62", &builtin_type_double }, + + { "pc", &builtin_type_void_func_ptr }, + { "npc", &builtin_type_void_func_ptr }, + + /* This raw register contains the contents of %cwp, %pstate, %asi + and %ccr as laid out in a %tstate register. */ + /* FIXME: Give it a name until we start using register groups. */ + { "state", &builtin_type_int64 }, + + { "fsr", &builtin_type_int64 }, + { "fprs", &builtin_type_int64 }, + + /* "Although Y is a 64-bit register, its high-order 32 bits are + reserved and always read as 0." */ + { "y", &builtin_type_int64 } +}; + +/* Total number of registers. */ +#define SPARC64_NUM_REGS \ + (sizeof (sparc64_register_info) / sizeof (sparc64_register_info[0])) + +/* We provide the aliases %d0..%d62 and %q0..%q60 for the floating + registers as "psuedo" registers. */ + +static struct sparc64_register_info sparc64_pseudo_register_info[] = +{ + { "cwp", &builtin_type_int64 }, + { "pstate", &builtin_type_int64 }, + { "asi", &builtin_type_int64 }, + { "ccr", &builtin_type_int64 }, + + { "d0", &builtin_type_double }, + { "d2", &builtin_type_double }, + { "d4", &builtin_type_double }, + { "d6", &builtin_type_double }, + { "d8", &builtin_type_double }, + { "d10", &builtin_type_double }, + { "d12", &builtin_type_double }, + { "d14", &builtin_type_double }, + { "d16", &builtin_type_double }, + { "d18", &builtin_type_double }, + { "d20", &builtin_type_double }, + { "d22", &builtin_type_double }, + { "d24", &builtin_type_double }, + { "d26", &builtin_type_double }, + { "d28", &builtin_type_double }, + { "d30", &builtin_type_double }, + { "d32", &builtin_type_double }, + { "d34", &builtin_type_double }, + { "d36", &builtin_type_double }, + { "d38", &builtin_type_double }, + { "d40", &builtin_type_double }, + { "d42", &builtin_type_double }, + { "d44", &builtin_type_double }, + { "d46", &builtin_type_double }, + { "d48", &builtin_type_double }, + { "d50", &builtin_type_double }, + { "d52", &builtin_type_double }, + { "d54", &builtin_type_double }, + { "d56", &builtin_type_double }, + { "d58", &builtin_type_double }, + { "d60", &builtin_type_double }, + { "d62", &builtin_type_double }, + + { "q0", &builtin_type_long_double }, + { "q4", &builtin_type_long_double }, + { "q8", &builtin_type_long_double }, + { "q12", &builtin_type_long_double }, + { "q16", &builtin_type_long_double }, + { "q20", &builtin_type_long_double }, + { "q24", &builtin_type_long_double }, + { "q28", &builtin_type_long_double }, + { "q32", &builtin_type_long_double }, + { "q36", &builtin_type_long_double }, + { "q40", &builtin_type_long_double }, + { "q44", &builtin_type_long_double }, + { "q48", &builtin_type_long_double }, + { "q52", &builtin_type_long_double }, + { "q56", &builtin_type_long_double }, + { "q60", &builtin_type_long_double } +}; + +/* Total number of pseudo registers. */ +#define SPARC64_NUM_PSEUDO_REGS \ + (sizeof (sparc64_pseudo_register_info) \ + / sizeof (sparc64_pseudo_register_info[0])) + +/* Return the name of register REGNUM. */ + +static const char * +sparc64_register_name (int regnum) +{ + if (regnum >= 0 && regnum < SPARC64_NUM_REGS) + return sparc64_register_info[regnum].name; + + if (regnum >= SPARC64_NUM_REGS + && regnum < SPARC64_NUM_REGS + SPARC64_NUM_PSEUDO_REGS) + return sparc64_pseudo_register_info[regnum - SPARC64_NUM_REGS].name; + + return NULL; +} + +/* Return the GDB type object for the "standard" data type of data in + register REGNUM. */ + +static struct type * +sparc64_register_type (struct gdbarch *gdbarch, int regnum) +{ + if (regnum >= SPARC64_NUM_REGS + && regnum < SPARC64_NUM_REGS + SPARC64_NUM_PSEUDO_REGS) + return *sparc64_pseudo_register_info[regnum - SPARC64_NUM_REGS].type; + + gdb_assert (regnum >= 0 && regnum < SPARC64_NUM_REGS); + return *sparc64_register_info[regnum].type; +} + +static void +sparc64_pseudo_register_read (struct gdbarch *gdbarch, + struct regcache *regcache, + int regnum, void *buf) +{ + gdb_assert (regnum >= SPARC64_NUM_REGS); + + if (regnum >= SPARC64_D0_REGNUM && regnum <= SPARC64_D30_REGNUM) + { + regnum = SPARC_F0_REGNUM + 2 * (regnum - SPARC64_D0_REGNUM); + regcache_raw_read (regcache, regnum, buf); + regcache_raw_read (regcache, regnum + 1, ((char *)buf) + 4); + } + else if (regnum >= SPARC64_D32_REGNUM && regnum <= SPARC64_D62_REGNUM) + { + regnum = SPARC64_F32_REGNUM + (regnum - SPARC64_D32_REGNUM); + regcache_raw_read (regcache, regnum, buf); + } + else if (regnum >= SPARC64_Q0_REGNUM && regnum <= SPARC64_Q28_REGNUM) + { + regnum = SPARC_F0_REGNUM + 4 * (regnum - SPARC64_Q0_REGNUM); + regcache_raw_read (regcache, regnum, buf); + regcache_raw_read (regcache, regnum + 1, ((char *)buf) + 4); + regcache_raw_read (regcache, regnum + 2, ((char *)buf) + 8); + regcache_raw_read (regcache, regnum + 3, ((char *)buf) + 12); + } + else if (regnum >= SPARC64_Q32_REGNUM && regnum <= SPARC64_Q60_REGNUM) + { + regnum = SPARC64_F32_REGNUM + 2 * (regnum - SPARC64_Q32_REGNUM); + regcache_raw_read (regcache, regnum, buf); + regcache_raw_read (regcache, regnum + 1, ((char *)buf) + 8); + } + else if (regnum == SPARC64_CWP_REGNUM + || regnum == SPARC64_PSTATE_REGNUM + || regnum == SPARC64_ASI_REGNUM + || regnum == SPARC64_CCR_REGNUM) + { + ULONGEST state; + + regcache_raw_read_unsigned (regcache, SPARC64_STATE_REGNUM, &state); + switch (regnum) + { + case SPARC64_CWP_REGNUM: + state = (state >> 0) & ((1 << 5) - 1); + break; + case SPARC64_PSTATE_REGNUM: + state = (state >> 8) & ((1 << 12) - 1); + break; + case SPARC64_ASI_REGNUM: + state = (state >> 24) & ((1 << 8) - 1); + break; + case SPARC64_CCR_REGNUM: + state = (state >> 32) & ((1 << 8) - 1); + break; + } + store_unsigned_integer (buf, 8, state); + } +} + +static void +sparc64_pseudo_register_write (struct gdbarch *gdbarch, + struct regcache *regcache, + int regnum, const void *buf) +{ + gdb_assert (regnum >= SPARC64_NUM_REGS); + + if (regnum >= SPARC64_D0_REGNUM && regnum <= SPARC64_D30_REGNUM) + { + regnum = SPARC_F0_REGNUM + 2 * (regnum - SPARC64_D0_REGNUM); + regcache_raw_write (regcache, regnum, buf); + regcache_raw_write (regcache, regnum + 1, ((const char *)buf) + 4); + } + else if (regnum >= SPARC64_D32_REGNUM && regnum <= SPARC64_D62_REGNUM) + { + regnum = SPARC64_F32_REGNUM + (regnum - SPARC64_D32_REGNUM); + regcache_raw_write (regcache, regnum, buf); + } + else if (regnum >= SPARC64_Q0_REGNUM && regnum <= SPARC64_Q28_REGNUM) + { + regnum = SPARC_F0_REGNUM + 4 * (regnum - SPARC64_Q0_REGNUM); + regcache_raw_write (regcache, regnum, buf); + regcache_raw_write (regcache, regnum + 1, ((const char *)buf) + 4); + regcache_raw_write (regcache, regnum + 2, ((const char *)buf) + 8); + regcache_raw_write (regcache, regnum + 3, ((const char *)buf) + 12); + } + else if (regnum >= SPARC64_Q32_REGNUM && regnum <= SPARC64_Q60_REGNUM) + { + regnum = SPARC64_F32_REGNUM + 2 * (regnum - SPARC64_Q32_REGNUM); + regcache_raw_write (regcache, regnum, buf); + regcache_raw_write (regcache, regnum + 1, ((const char *)buf) + 8); + } + else if (regnum == SPARC64_CWP_REGNUM + || regnum == SPARC64_PSTATE_REGNUM + || regnum == SPARC64_ASI_REGNUM + || regnum == SPARC64_CCR_REGNUM) + { + ULONGEST state, bits; + + regcache_raw_read_unsigned (regcache, SPARC64_STATE_REGNUM, &state); + bits = extract_unsigned_integer (buf, 8); + switch (regnum) + { + case SPARC64_CWP_REGNUM: + state |= ((bits & ((1 << 5) - 1)) << 0); + break; + case SPARC64_PSTATE_REGNUM: + state |= ((bits & ((1 << 12) - 1)) << 8); + break; + case SPARC64_ASI_REGNUM: + state |= ((bits & ((1 << 8) - 1)) << 24); + break; + case SPARC64_CCR_REGNUM: + state |= ((bits & ((1 << 8) - 1)) << 32); + break; + } + regcache_raw_write_unsigned (regcache, SPARC64_STATE_REGNUM, state); + } +} + +/* Use the program counter to determine the contents and size of a + breakpoint instruction. Return a pointer to a string of bytes that + encode a breakpoint instruction, store the length of the string in + *LEN and optionally adjust *PC to point to the correct memory + location for inserting the breakpoint. */ + +static const unsigned char * +sparc_breakpoint_from_pc (CORE_ADDR *pc, int *len) +{ + static unsigned char break_insn[] = { 0x91, 0xd0, 0x20, 0x01 }; + + *len = sizeof (break_insn); + return break_insn; +} + + +struct sparc64_frame_cache +{ + /* Base address. */ + CORE_ADDR base; + CORE_ADDR pc; + + /* Do we have a frame? */ + int frameless_p; +}; + +/* Allocate and initialize a frame cache. */ + +static struct sparc64_frame_cache * +sparc64_alloc_frame_cache (void) +{ + struct sparc64_frame_cache *cache; + int i; + + cache = FRAME_OBSTACK_ZALLOC (struct sparc64_frame_cache); + + /* Base address. */ + cache->base = 0; + cache->pc = 0; + + /* Frameless until proven otherwise. */ + cache->frameless_p = 1; + + return cache; +} + +static CORE_ADDR +sparc64_analyze_prologue (CORE_ADDR pc, CORE_ADDR current_pc, + struct sparc64_frame_cache *cache) +{ + unsigned long insn; + + if (current_pc <= pc) + return current_pc; + + /* Check whether the function starts with a SAVE instruction. */ + insn = sparc_fetch_instruction (pc); + if (X_OP (insn) == 2 && X_OP3 (insn) == 0x3c) + { + cache->frameless_p = 0; + return pc + 4; + } + + return pc; +} + +static CORE_ADDR +sparc64_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) +{ + return frame_unwind_register_unsigned (next_frame, SPARC64_PC_REGNUM); +} + +/* Return PC of first real instruction of the function starting at + START_PC. */ + +static CORE_ADDR +sparc64_skip_prologue (CORE_ADDR start_pc) +{ + struct symtab_and_line sal; + CORE_ADDR func_start, func_end; + struct sparc64_frame_cache cache; + + /* This is the preferred method, find the end of the prologue by + using the debugging information. */ + if (find_pc_partial_function (start_pc, NULL, &func_start, &func_end)) + { + sal = find_pc_line (func_start, 0); + + if (sal.end < func_end + && start_pc <= sal.end) + return sal.end; + } + + return sparc64_analyze_prologue (start_pc, 0xffffffffffffffffUL, &cache); +} + +/* Normal frames. */ + +static struct sparc64_frame_cache * +sparc64_frame_cache (struct frame_info *next_frame, void **this_cache) +{ + struct sparc64_frame_cache *cache; + + if (*this_cache) + return *this_cache; + + cache = sparc64_alloc_frame_cache (); + *this_cache = cache; + + /* In priciple, for normal frames, %fp (%i6) holds the frame + pointer, which holds the base address for the current stack + frame. */ + + cache->base = frame_unwind_register_unsigned (next_frame, SPARC_FP_REGNUM); + if (cache->base == 0) + return cache; + + cache->pc = frame_func_unwind (next_frame); + if (cache->pc != 0) + sparc64_analyze_prologue (cache->pc, frame_pc_unwind (next_frame), cache); + + if (cache->frameless_p) + { + /* We didn't find a valid frame, which means that CACHE->base + currently holds the frame pointer for our calling frame. */ + cache->base = frame_unwind_register_unsigned (next_frame, + SPARC_SP_REGNUM); + } + + return cache; +} + +static void +sparc64_frame_this_id (struct frame_info *next_frame, void **this_cache, + struct frame_id *this_id) +{ + struct sparc64_frame_cache *cache = + sparc64_frame_cache (next_frame, this_cache); + + /* This marks the outermost frame. */ + if (cache->base == 0) + return; + + (*this_id) = frame_id_build (cache->base, cache->pc); +} + +static void +sparc64_frame_prev_register (struct frame_info *next_frame, void **this_cache, + int regnum, int *optimizedp, + enum lval_type *lvalp, CORE_ADDR *addrp, + int *realnump, void *valuep) +{ + struct sparc64_frame_cache *cache = + sparc64_frame_cache (next_frame, this_cache); + + if (regnum == SPARC64_PC_REGNUM || regnum == SPARC64_NPC_REGNUM) + { + *optimizedp = 0; + *lvalp = not_lval; + *addrp = 0; + *realnump = -1; + if (valuep) + { + CORE_ADDR pc = (regnum == SPARC64_NPC_REGNUM) ? 4 : 0; + + regnum = cache->frameless_p ? SPARC_O7_REGNUM : SPARC_I7_REGNUM; + pc += frame_unwind_register_unsigned (next_frame, regnum) + 8; + store_unsigned_integer (valuep, 8, pc); + } + return; + } + + /* The previous frame's `local' and `in' registers have been saved + in the register save area. */ + if (!cache->frameless_p + && regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) + { + *optimizedp = 0; + *lvalp = lval_memory; + *addrp = cache->base + BIAS + (regnum - SPARC_L0_REGNUM) * 8; + *realnump = -1; + if (valuep) + { + struct gdbarch *gdbarch = get_frame_arch (next_frame); + + /* Read the value in from memory. */ + read_memory (*addrp, valuep, register_size (gdbarch, regnum)); + } + return; + } + + /* The previous frame's `out' registers are accessable as the + current frame's `in' registers. */ + if (!cache->frameless_p + && regnum >= SPARC_O0_REGNUM && regnum <= SPARC_O7_REGNUM) + regnum += (SPARC_I0_REGNUM - SPARC_O0_REGNUM); + + frame_register_unwind (next_frame, regnum, + optimizedp, lvalp, addrp, realnump, valuep); +} + +static const struct frame_unwind sparc64_frame_unwind = +{ + NORMAL_FRAME, + sparc64_frame_this_id, + sparc64_frame_prev_register +}; + +static const struct frame_unwind * +sparc64_frame_sniffer (struct frame_info *next_frame) +{ + return &sparc64_frame_unwind; +} + + +static CORE_ADDR +sparc64_frame_base_address (struct frame_info *next_frame, void **this_cache) +{ + struct sparc64_frame_cache *cache = + sparc64_frame_cache (next_frame, this_cache); + + /* ??? Should we take BIAS into account here? */ + return cache->base; +} + +static const struct frame_base sparc64_frame_base = +{ + &sparc64_frame_unwind, + sparc64_frame_base_address, + sparc64_frame_base_address, + sparc64_frame_base_address +}; + +static struct frame_id +sparc_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) +{ + CORE_ADDR sp; + + sp = frame_unwind_register_unsigned (next_frame, SPARC_SP_REGNUM); + return frame_id_build (sp, frame_pc_unwind (next_frame)); +} + +/* Check whether TYPE must be 16-byte aligned. */ + +static int +sparc64_16_byte_align_p (struct type *type) +{ + if (sparc64_floating_p (type) && TYPE_LENGTH (type) == 16) + return 1; + + if (sparc64_structure_or_union_p (type)) + { + int i; + + for (i = 0; i < TYPE_NFIELDS (type); i++) + if (sparc64_16_byte_align_p (TYPE_FIELD_TYPE (type, i))) + return 1; + } + + return 0; +} + +/* Store floating fields of element ELEMENT of an "parameter array" + that has type TYPE and is stored at BITPOS in VALBUF in the + apropriate registers of REGCACHE. This function can be called + recursively and therefore handles floating types in addition to + structures. */ + +static void +sparc64_store_floating_fields (struct regcache *regcache, struct type *type, + char *valbuf, int element, int bitpos) +{ + gdb_assert (element < 16); + + if (sparc64_floating_p (type)) + { + int len = TYPE_LENGTH (type); + int regnum; + + if (len == 16) + { + gdb_assert (bitpos == 0); + gdb_assert ((element % 2) == 0); + + regnum = SPARC64_Q0_REGNUM + element / 2; + regcache_cooked_write (regcache, regnum, valbuf); + } + else if (len == 8) + { + gdb_assert (bitpos == 0 || bitpos == 64); + + regnum = SPARC64_D0_REGNUM + element + bitpos / 64; + regcache_cooked_write (regcache, regnum, valbuf + (bitpos / 8)); + } + else + { + gdb_assert (len == 4); + gdb_assert (bitpos % 32 == 0 && bitpos >= 0 && bitpos < 128); + + regnum = SPARC_F0_REGNUM + element * 2 + bitpos / 32; + regcache_cooked_write (regcache, regnum, valbuf + (bitpos / 8)); + } + } + else if (sparc64_structure_or_union_p (type)) + { + int i; + + for (i = 0; i < TYPE_NFIELDS (type); i++) + sparc64_store_floating_fields (regcache, TYPE_FIELD_TYPE (type, i), + valbuf, element, + bitpos + TYPE_FIELD_BITPOS (type, i)); + } +} + +/* Fetch floating fields from a variable of type TYPE from the + appropriate registers for BITPOS in REGCACHE and store it at BITPOS + in VALBUF. This function can be called recursively and therefore + handles floating types in addition to structures. */ + +static void +sparc64_extract_floating_fields (struct regcache *regcache, struct type *type, + char *valbuf, int bitpos) +{ + if (sparc64_floating_p (type)) + { + int len = TYPE_LENGTH (type); + int regnum; + + if (len == 16) + { + gdb_assert (bitpos == 0 || bitpos == 128); + + regnum = SPARC64_Q0_REGNUM + bitpos / 128; + regcache_cooked_read (regcache, regnum, valbuf + (bitpos / 8)); + } + else if (len == 8) + { + gdb_assert (bitpos % 64 == 0 && bitpos >= 0 && bitpos < 256); + + regnum = SPARC64_D0_REGNUM + bitpos / 64; + regcache_cooked_read (regcache, regnum, valbuf + (bitpos / 8)); + } + else + { + gdb_assert (len == 4); + gdb_assert (bitpos % 32 == 0 && bitpos >= 0 && bitpos < 256); + + regnum = SPARC_F0_REGNUM + bitpos / 32; + regcache_cooked_read (regcache, regnum, valbuf + (bitpos / 8)); + } + } + else if (sparc64_structure_or_union_p (type)) + { + int i; + + for (i = 0; i < TYPE_NFIELDS (type); i++) + sparc64_extract_floating_fields (regcache, TYPE_FIELD_TYPE (type, i), + valbuf, + bitpos + TYPE_FIELD_BITPOS (type, i)); + } +} + +/* Store the NARGS arguments ARGS and STRUCT_ADDR (if STRUCT_RETURN is + non-zero) in REGCACHE and on the stack (starting from address SP). */ + +static CORE_ADDR +sparc64_store_arguments (struct regcache *regcache, int nargs, + struct value **args, CORE_ADDR sp, + int struct_return, CORE_ADDR struct_addr) +{ + /* Number of extended words in the "parameter array". */ + int num_elements = 0; + int element = 0; + int i; + + /* Take BIAS into account. */ + sp += BIAS; + + /* First we calculate the number of extended words in the "parameter + array". While doing so we also convert some of the arguments. */ + + if (struct_return) + num_elements++; + + for (i = 0; i < nargs; i++) + { + struct type *type = VALUE_TYPE (args[i]); + int len = TYPE_LENGTH (type); + + if (sparc64_structure_or_union_p (type)) + { + /* Structure or Union arguments. */ + if (len <= 16) + { + if (num_elements % 2 && sparc64_16_byte_align_p (type)) + num_elements++; + num_elements += ((len + 7) / 8); + } + else + { + /* The psABI says that "Structures or unions larger than + sixteen bytes are copied by the caller and passed + indirectly; the caller will pass the address of a + correctly aligned structure value. This sixty-four + bit address will occupy one word in the parameter + array, and may be promoted to an %o register like any + other pointer value." Allocate memory for these + values on the stack. */ + sp -= len; + + /* Use 16-byte alignment for these values. That's + always correct, and wasting a few bytes shouldn't be + a problem. */ + sp &= ~0xf; + + write_memory (sp, VALUE_CONTENTS (args[i]), len); + args[i] = value_from_pointer (lookup_pointer_type (type), sp); + num_elements++; + } + } + else if (sparc64_floating_p (type)) + { + /* Floating arguments. */ + + if (len == 16) + { + /* The psABI says that "Each quad-precision parameter + value will be assigned to two extended words in the + parameter array. */ + num_elements += 2; + + /* The psABI says that "Long doubles must be + quad-aligned, and thus a hole might be introduced + into the parameter array to force alignment." Skip + an element if necessary. */ + if (num_elements % 2) + num_elements++; + } + else + num_elements++; + } + else + { + /* Integral and pointer arguments. */ + gdb_assert (sparc64_integral_or_pointer_p (type)); + + /* The psABI says that "Each argument value of integral type + smaller than an extended word will be widened by the + caller to an extended word according to the signed-ness + of the argument type." */ + if (len < 8) + args[i] = value_cast (builtin_type_int64, args[i]); + num_elements++; + } + } + + /* Allocate the "parameter array". */ + sp -= num_elements * 8; + + /* The psABI says that "Every stack frame must be 16-byte aligned." */ + sp &= ~0xf; + + /* Now we store the arguments in to the "paramater array". Some + Integer or Pointer arguments and Structure or Union arguments + will be passed in %o registers. Some Floating arguments and + floating members of structures are passed in floating-point + registers. However, for functions with variable arguments, + floating arguments are stored in an %0 register, and for + functions without a prototype floating arguments are stored in + both a floating-point and an %o registers, or a floating-point + register and memory. To simplify the logic here we always pass + arguments in memory, an %o register, and a floating-point + register if appropriate. This should be no problem since the + contents of any unused memory or registers in the "parameter + array" are undefined. */ + + if (struct_return) + { + regcache_cooked_write_unsigned (regcache, SPARC_O0_REGNUM, struct_addr); + element++; + } + + for (i = 0; i < nargs; i++) + { + char *valbuf = VALUE_CONTENTS (args[i]); + struct type *type = VALUE_TYPE (args[i]); + int len = TYPE_LENGTH (type); + int regnum = -1; + char buf[16]; + + if (sparc64_structure_or_union_p (type)) + { + /* Structure or Union arguments. */ + gdb_assert (len <= 16); + memset (buf, 0, sizeof (buf)); + valbuf = memcpy (buf, valbuf, len); + + if (element % 2 && sparc64_16_byte_align_p (type)) + element++; + + if (element < 6) + { + regnum = SPARC_O0_REGNUM + element; + if (len > 8 && element < 5) + regcache_cooked_write (regcache, regnum + 1, valbuf + 8); + } + + if (element < 16) + sparc64_store_floating_fields (regcache, type, valbuf, element, 0); + } + else if (sparc64_floating_p (type)) + { + /* Floating arguments. */ + if (len == 16) + { + if (element % 2) + element++; + if (element < 16) + regnum = SPARC64_Q0_REGNUM + element / 2; + } + else if (len == 8) + { + if (element < 16) + regnum = SPARC64_D0_REGNUM + element; + } + else + { + /* The psABI says "Each single-precision parameter value + will be assigned to one extended word in the + parameter array, and right-justified within that + word; the left half (even floatregister) is + undefined." Even though the psABI says that "the + left half is undefined", set it to zero here. */ + memset (buf, 0, 4); + valbuf = memcpy (buf + 4, valbuf, 4); + len = 8; + if (element < 16) + regnum = SPARC64_D0_REGNUM; + } + } + else + { + /* Integral and pointer arguments. */ + gdb_assert (len == 8); + if (element < 6) + regnum = SPARC_O0_REGNUM + element; + } + + if (regnum != -1) + { + regcache_cooked_write (regcache, regnum, valbuf); + + /* If we're storing the value in a floating-point register, + also store it in the corresponding %0 register(s). */ + if (regnum >= SPARC64_D0_REGNUM && regnum <= SPARC64_D10_REGNUM) + { + gdb_assert (element < 6); + regnum = SPARC_O0_REGNUM + element; + regcache_cooked_write (regcache, regnum, valbuf); + } + else if (regnum >= SPARC64_Q0_REGNUM && regnum <= SPARC64_Q8_REGNUM) + { + gdb_assert (element < 6); + regnum = SPARC_O0_REGNUM + element; + regcache_cooked_write (regcache, regnum, valbuf); + regcache_cooked_write (regcache, regnum + 1, valbuf); + } + } + + /* Always store the argument in memeory. */ + write_memory (sp + element * 8, valbuf, len); + element += ((len + 7) / 8); + } + + gdb_assert (element == num_elements); + + /* Take BIAS into account. */ + sp -= BIAS; + return sp; +} + +static CORE_ADDR +sparc64_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr, + struct regcache *regcache, CORE_ADDR bp_addr, + int nargs, struct value **args, CORE_ADDR sp, + int struct_return, CORE_ADDR struct_addr) +{ + /* Set return address. */ + regcache_cooked_write_unsigned (regcache, SPARC_O7_REGNUM, bp_addr - 8); + + /* Set up function arguments. */ + sp = sparc64_store_arguments (regcache, nargs, args, sp, + struct_return, struct_addr); + + /* Allocate the register save area. */ + sp -= 16 * 8; + + /* Stack should be 16-byte aligned at this point. */ + gdb_assert ((sp + BIAS) % 16 == 0); + + /* Finally, update the stack pointer. */ + regcache_cooked_write_unsigned (regcache, SPARC_SP_REGNUM, sp); + + return sp; +} + + +/* Extract from an array REGBUF containing the (raw) register state, a + function return value of TYPE, and copy that into VALBUF. */ + +static void +sparc64_extract_return_value (struct type *type, struct regcache *regcache, + void *valbuf) +{ + int len = TYPE_LENGTH (type); + char buf[32]; + int i; + + if (sparc64_structure_or_union_p (type)) + { + /* Structure or Union return values. */ + gdb_assert (len <= 32); + + for (i = 0; i < ((len + 7) / 8); i++) + regcache_cooked_read (regcache, SPARC_O0_REGNUM + i, buf + i * 8); + if (TYPE_CODE (type) != TYPE_CODE_UNION) + sparc64_extract_floating_fields (regcache, type, buf, 0); + memcpy (valbuf, buf, len); + } + else if (sparc64_floating_p (type)) + { + /* Floating return values. */ + for (i = 0; i < len / 4; i++) + regcache_cooked_read (regcache, SPARC_F0_REGNUM + i, buf + i * 4); + memcpy (valbuf, buf, len); + } + else + { + /* Integral and pointer return values. */ + gdb_assert (sparc64_integral_or_pointer_p (type)); + + /* Just stripping off any unused bytes should preserve the + signed-ness just fine. */ + regcache_cooked_read (regcache, SPARC_O0_REGNUM, buf); + memcpy (valbuf, buf + 8 - len, len); + } +} + +/* Write into the appropriate registers a function return value stored + in VALBUF of type TYPE. */ + +static void +sparc64_store_return_value (struct type *type, struct regcache *regcache, + const void *valbuf) +{ + int len = TYPE_LENGTH (type); + char buf[16]; + int i; + + if (sparc64_structure_or_union_p (type)) + { + /* Structure or Union return values. */ + gdb_assert (len <= 32); + + /* Simplify matters by storing the complete value (including + floating members) into %o0 and %o1. Floating members are + also store in the appropriate floating-point registers. */ + memset (buf, 0, sizeof (buf)); + memcpy (buf, valbuf, len); + for (i = 0; i < ((len + 7) / 8); i++) + regcache_cooked_write (regcache, SPARC_O0_REGNUM + i, buf + i * 4); + if (TYPE_CODE (type) != TYPE_CODE_UNION) + sparc64_store_floating_fields (regcache, type, buf, 0, 0); + } + else if (sparc64_floating_p (type)) + { + /* Floating return values. */ + memcpy (buf, valbuf, len); + for (i = 0; i < len / 4; i++) + regcache_cooked_write (regcache, SPARC_F0_REGNUM + i, buf + i * 4); + } + else + { + /* Integral and pointer return values. */ + gdb_assert (sparc64_integral_or_pointer_p (type)); + + /* ??? Do we need to do any sign-extension here? */ + memset (buf, 0, 8); + memcpy (buf + 8 - len, valbuf, len); + regcache_cooked_write (regcache, SPARC_O0_REGNUM, buf); + } +} + +/* Extract from REGCACHE, which contains the (raw) register state, the + address in which a function should return its structure value, as a + CORE_ADDR. */ + +static CORE_ADDR +sparc_extract_struct_value_address (struct regcache *regcache) +{ + ULONGEST addr; + + regcache_cooked_read_unsigned (regcache, SPARC_O0_REGNUM, &addr); + return addr; +} + +static int +sparc64_use_struct_convention (int gcc_p, struct type *type) +{ + /* Structure and union types up to 32 bytes in size are returned in + registers. */ + return (TYPE_LENGTH (type) > 32); +} + + +/* The SPARC Architecture doesn't have hardware single-step support, + and most operating systems don't implement it either, so we provide + software single-step mechanism. */ + +static CORE_ADDR +sparc_analyze_control_transfer (CORE_ADDR pc, CORE_ADDR *npc) +{ + unsigned long insn = sparc_fetch_instruction (pc); + int conditional_p = X_COND (insn) & 0x7; + int branch_p = 0; + long offset = 0; /* Must be signed for sign-extend. */ + + if (X_OP (insn) == 0 && X_OP2 (insn) == 3 && (insn & 0x1000000) == 0) + { + /* Branch on Integer Register with Prediction (BPr). */ + branch_p = 1; + conditional_p = 1; + } + else if (X_OP (insn) == 0 && X_OP2 (insn) == 6) + { + /* Branch on Floating-Point Condition Codes (FBfcc). */ + branch_p = 1; + offset = 4 * X_DISP22 (insn); + } + else if (X_OP (insn) == 0 && X_OP2 (insn) == 5) + { + /* Branch on Floating-Point Condition Codes with Prediction + (FBPfcc). */ + branch_p = 1; + offset = 4 * X_DISP19 (insn); + } + else if (X_OP (insn) == 0 && X_OP2 (insn) == 2) + { + /* Branch on Integer Condition Codes (Bicc). */ + branch_p = 1; + offset = 4 * X_DISP22 (insn); + } + else if (X_OP (insn) == 0 && X_OP2 (insn) == 1) + { + /* Branch on Integer Condition Codes with Prediction (BPcc). */ + branch_p = 1; + offset = 4 * X_DISP19 (insn); + } + + /* FIXME: Handle DONE and RETRY instructions. */ + + /* FIXME: Handle the Trap instruction. */ + + if (branch_p) + { + if (conditional_p) + { + /* For conditional branches, return nPC + 4 iff the annul + bit is 1. */ + return (X_A (insn) ? *npc + 4 : 0); + } + else + { + /* For unconditional branches, return the target if its + specified condition is "always" and return nPC + 4 if the + condition is "never". If the annul bit is 1, set *NPC to + zero. */ + if (X_COND (insn) == 0x0) + pc = *npc, offset = 4; + if (X_A (insn)) + *npc = 0; + + gdb_assert (offset != 0); + return pc + offset; + } + } + + return 0; +} + +void +sparc_software_single_step (enum target_signal sig, int insert_breakpoints_p) +{ + static CORE_ADDR npc, nnpc; + static char npc_save[4], nnpc_save[4]; + + if (insert_breakpoints_p) + { + CORE_ADDR pc; + + pc = sparc_address_from_register (SPARC64_PC_REGNUM); + npc = sparc_address_from_register (SPARC64_NPC_REGNUM); + + /* Analyze the instruction at PC. */ + nnpc = sparc_analyze_control_transfer (pc, &npc); + if (npc != 0) + target_insert_breakpoint (npc, npc_save); + if (nnpc != 0) + target_insert_breakpoint (nnpc, nnpc_save); + + /* Assert that we have set at least one breakpoint. */ + gdb_assert (npc != 0 || nnpc != 0); + } + else + { + if (npc != 0) + target_remove_breakpoint (npc, npc_save); + if (nnpc != 0) + target_remove_breakpoint (nnpc, nnpc_save); + + npc = 0; + nnpc = 0; + } +} + + +static struct gdbarch * +sparc64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) +{ + struct gdbarch_tdep *tdep; + struct gdbarch *gdbarch; + + /* If there is already a candidate, use it. */ + arches = gdbarch_list_lookup_by_info (arches, &info); + if (arches != NULL) + return arches->gdbarch; + + /* Allocate space for the new architecture. */ + tdep = XMALLOC (struct gdbarch_tdep); + gdbarch = gdbarch_alloc (&info, tdep); + + set_gdbarch_long_bit (gdbarch, 64); + set_gdbarch_long_long_bit (gdbarch, 64); + set_gdbarch_ptr_bit (gdbarch, 64); + set_gdbarch_long_double_bit (gdbarch, 128); + + set_gdbarch_num_regs (gdbarch, SPARC64_NUM_REGS); + set_gdbarch_register_name (gdbarch, sparc64_register_name); + set_gdbarch_register_type (gdbarch, sparc64_register_type); + set_gdbarch_num_pseudo_regs (gdbarch, SPARC64_NUM_PSEUDO_REGS); + set_gdbarch_pseudo_register_read (gdbarch, sparc64_pseudo_register_read); + set_gdbarch_pseudo_register_write (gdbarch, sparc64_pseudo_register_write); + + /* Register numbers of various important registers. */ + set_gdbarch_sp_regnum (gdbarch, SPARC_SP_REGNUM); /* %sp */ + set_gdbarch_pc_regnum (gdbarch, SPARC64_PC_REGNUM); /* %pc */ + set_gdbarch_deprecated_npc_regnum (gdbarch, SPARC64_NPC_REGNUM); + set_gdbarch_fp0_regnum (gdbarch, SPARC_F0_REGNUM); /* %f0 */ + + /* Call dummy code. */ + set_gdbarch_push_dummy_call (gdbarch, sparc64_push_dummy_call); + + set_gdbarch_extract_return_value (gdbarch, sparc64_extract_return_value); + set_gdbarch_store_return_value (gdbarch, sparc64_store_return_value); + set_gdbarch_extract_struct_value_address + (gdbarch, sparc_extract_struct_value_address); + set_gdbarch_use_struct_convention (gdbarch, sparc64_use_struct_convention); + + set_gdbarch_skip_prologue (gdbarch, sparc64_skip_prologue); + + /* Stack grows downward. */ + set_gdbarch_inner_than (gdbarch, core_addr_lessthan); + + set_gdbarch_breakpoint_from_pc (gdbarch, sparc_breakpoint_from_pc); + set_gdbarch_decr_pc_after_break (gdbarch, 0); + set_gdbarch_function_start_offset (gdbarch, 0); + + set_gdbarch_frame_args_skip (gdbarch, 8); + + set_gdbarch_print_insn (gdbarch, print_insn_sparc); + + set_gdbarch_software_single_step (gdbarch, sparc_software_single_step); + + set_gdbarch_unwind_dummy_id (gdbarch, sparc_unwind_dummy_id); + + set_gdbarch_unwind_pc (gdbarch, sparc64_unwind_pc); + + frame_base_set_default (gdbarch, &sparc64_frame_base); + + /* Hook in ABI-specific overrides, if they have been registered. */ + gdbarch_init_osabi (info, gdbarch); + + frame_unwind_append_sniffer (gdbarch, sparc64_frame_sniffer); + + return gdbarch; +} + +/* Helper functions for dealing with register windows. */ + +void +sparc_supply_rwindow (CORE_ADDR sp, int regnum) +{ + int offset = 0; + char buf[8]; + int i; + + if (sp & 1) + { + /* Registers are 64-bit. */ + sp += BIAS; + + for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) + { + if (regnum == i || regnum == -1) + { + target_read_memory (sp + ((i - SPARC_L0_REGNUM) * 8), buf, 8); + supply_register (i, buf); + } + } + } + else + { + /* Registers are 32-bit. Toss any sign-extension of the stack + pointer. */ + sp &= 0xffffffffUL; + + /* Clear out the top half of the temporary buffer, and put the + register value in the bottom half if we're in 64-bit mode. */ + if (gdbarch_ptr_bit (current_gdbarch) == 64) + { + memset (buf, 0, 4); + offset = 4; + } + + for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) + { + if (regnum == i || regnum == -1) + { + target_read_memory (sp + ((i - SPARC_L0_REGNUM) * 4), + buf + offset, 4); + supply_register (i, buf); + } + } + } +} + +void +sparc_fill_rwindow (CORE_ADDR sp, int regnum) +{ + int offset = 0; + char buf[8]; + int i; + + if (sp & 1) + { + /* Registers are 64-bit. */ + sp += BIAS; + + for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) + { + if (regnum == -1 || regnum == SPARC_SP_REGNUM || regnum == i) + { + regcache_collect (i, buf); + target_write_memory (sp + ((i - SPARC_L0_REGNUM) * 8), buf, 8); + } + } + } + else + { + /* Registers are 32-bit. Toss any sign-extension of the stack + pointer. */ + sp &= 0xffffffffUL; + + /* Only use the bottom half if we're in 64-bit mode. */ + if (gdbarch_ptr_bit (current_gdbarch) == 64) + offset = 4; + + for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) + { + if (regnum == -1 || regnum == SPARC_SP_REGNUM || regnum == i) + { + regcache_collect (i, buf); + target_write_memory (sp + ((i - SPARC_L0_REGNUM) * 4), + buf + offset, 4); + } + } + } +} + + +/* Provide a prototype to silence -Wmissing-prototypes. */ +void _initialize_sparc64_tdep (void); + +void +_initialize_sparc64_tdep (void) +{ + register_gdbarch_init (bfd_arch_sparc, sparc64_gdbarch_init); +} diff --git a/gdb/sparc64-tdep.h b/gdb/sparc64-tdep.h new file mode 100644 index 0000000..e7b910d --- /dev/null +++ b/gdb/sparc64-tdep.h @@ -0,0 +1,103 @@ +/* Target-dependent code for UltraSPARC. + + Copyright 2003 Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#ifndef SPARC64_TDEP_H +#define SPARC62_TDEP_H 1 + +/* Register numbers of various important registers. */ + +enum sparc_regnum +{ + SPARC_G0_REGNUM, /* %g0 */ + SPARC_G1_REGNUM, + SPARC_G2_REGNUM, + SPARC_G3_REGNUM, + SPARC_G4_REGNUM, + SPARC_G5_REGNUM, + SPARC_G6_REGNUM, + SPARC_G7_REGNUM, /* %g7 */ + SPARC_O0_REGNUM, /* %o0 */ + SPARC_O1_REGNUM, + SPARC_O2_REGNUM, + SPARC_O3_REGNUM, + SPARC_O4_REGNUM, + SPARC_O5_REGNUM, + SPARC_SP_REGNUM, /* %sp (%o6) */ + SPARC_O7_REGNUM, /* %o7 */ + SPARC_L0_REGNUM, /* %l0 */ + SPARC_L1_REGNUM, + SPARC_L2_REGNUM, + SPARC_L3_REGNUM, + SPARC_L4_REGNUM, + SPARC_L5_REGNUM, + SPARC_L6_REGNUM, + SPARC_L7_REGNUM, /* %l7 */ + SPARC_I0_REGNUM, /* %i0 */ + SPARC_I1_REGNUM, + SPARC_I2_REGNUM, + SPARC_I3_REGNUM, + SPARC_I4_REGNUM, + SPARC_I5_REGNUM, + SPARC_FP_REGNUM, /* %fp (%i6) */ + SPARC_I7_REGNUM, /* %i7 */ + SPARC_F0_REGNUM, /* %f0 */ + SPARC_F31_REGNUM = SPARC_F0_REGNUM + 31 /* %f31 */ +}; + +enum sparc64_regnum +{ + SPARC64_F32_REGNUM = SPARC_F0_REGNUM + 32, /* %f32 */ + SPARC64_F62_REGNUM = SPARC64_F32_REGNUM + 15, /* %f62 */ + SPARC64_PC_REGNUM, /* %pc */ + SPARC64_NPC_REGNUM, /* %npc */ + SPARC64_STATE_REGNUM, + SPARC64_FSR_REGNUM, /* %fsr */ + SPARC64_FPRS_REGNUM, /* %fprs */ + SPARC64_Y_REGNUM, /* %y */ + + /* Pseudo registers. */ + SPARC64_CWP_REGNUM, /* %cwp */ + SPARC64_PSTATE_REGNUM, /* %pstate */ + SPARC64_ASI_REGNUM, /* %asi */ + SPARC64_CCR_REGNUM, /* %ccr */ + SPARC64_D0_REGNUM, /* %d0 */ + SPARC64_D10_REGNUM = SPARC64_D0_REGNUM + 5, /* %d10 */ + SPARC64_D30_REGNUM = SPARC64_D0_REGNUM + 15, /* %d30 */ + SPARC64_D32_REGNUM = SPARC64_D0_REGNUM + 16, /* %d32 */ + SPARC64_D62_REGNUM = SPARC64_D0_REGNUM + 31, /* %d62 */ + SPARC64_Q0_REGNUM, /* %q0 */ + SPARC64_Q8_REGNUM = SPARC64_Q0_REGNUM + 2, /* %q8 */ + SPARC64_Q28_REGNUM = SPARC64_Q0_REGNUM + 7, /* %q28 */ + SPARC64_Q32_REGNUM = SPARC64_Q0_REGNUM + 8, /* %q32 */ + SPARC64_Q60_REGNUM = SPARC64_Q0_REGNUM + 15 /* %q60 */ +}; + +extern void sparc_supply_rwindow (CORE_ADDR sp, int regnum); +extern void sparc_fill_rwindow (CORE_ADDR sp, int regnum); + +/* Functions exported from sparc64fbsd-tdep.c. */ + +extern void sparc64fbsd_supply_reg (const char *regs, int regnum); +extern void sparc64fbsd_fill_reg (char *regs, int regnum); +extern void sparc64fbsd_supply_fpreg (const char *regs, int regnum); +extern void sparc64fbsd_fill_fpreg (char *regs, int regnum); + +#endif /* sparc64-tdep.h */ diff --git a/gdb/sparc64fbsd-nat.c b/gdb/sparc64fbsd-nat.c new file mode 100644 index 0000000..26c58d8 --- /dev/null +++ b/gdb/sparc64fbsd-nat.c @@ -0,0 +1,80 @@ +/* Native-dependent code for FreeBSD/sparc64. + + Copyright 2003 Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#include "defs.h" + +#include "sparc64-tdep.h" +#include "sparcbsd-nat.h" + +/* Determine whether `struct reg' contains register REGNUM. */ + +static int +sparc64fbsd_reg_supplies_p (int regnum) +{ + /* Integer registers. */ + if ((regnum >= SPARC_G0_REGNUM && regnum <= SPARC_G7_REGNUM) + || (regnum >= SPARC_O0_REGNUM && regnum <= SPARC_O7_REGNUM) + || (regnum >= SPARC_L0_REGNUM && regnum <= SPARC_L7_REGNUM) + || (regnum >= SPARC_I0_REGNUM && regnum <= SPARC_I7_REGNUM)) + return 1; + + /* Control registers. */ + if (regnum == SPARC64_PC_REGNUM + || regnum == SPARC64_NPC_REGNUM + || regnum == SPARC64_STATE_REGNUM + || regnum == SPARC64_FPRS_REGNUM + || regnum == SPARC64_Y_REGNUM) + return 1; + + return 0; +} + +/* Determine whether `struct fpreg' contains register REGNUM. */ + +static int +sparc64fbsd_fpreg_supplies_p (int regnum) +{ + /* Floating-point registers. */ + if ((regnum >= SPARC_F0_REGNUM && regnum <= SPARC_F31_REGNUM) + || (regnum >= SPARC64_F32_REGNUM && regnum <= SPARC64_F62_REGNUM)) + return 1; + + /* Control registers. */ + if (regnum == SPARC64_FSR_REGNUM) + return 1; + + return 0; +} + +/* Provide a prototype to silence -Wmissing-prototypes. */ +void _initialize_sparc64fbsd_nat (void); + +void +_initialize_sparc64fbsd_nat (void) +{ + sparcbsd_supply_reg = sparc64fbsd_supply_reg; + sparcbsd_fill_reg = sparc64fbsd_fill_reg; + sparcbsd_supply_fpreg = sparc64fbsd_supply_fpreg; + sparcbsd_fill_fpreg = sparc64fbsd_fill_fpreg; + + sparcbsd_reg_supplies_p = sparc64fbsd_reg_supplies_p; + sparcbsd_fpreg_supplies_p = sparc64fbsd_fpreg_supplies_p; +} diff --git a/gdb/sparc64fbsd-tdep.c b/gdb/sparc64fbsd-tdep.c new file mode 100644 index 0000000..2b910c1 --- /dev/null +++ b/gdb/sparc64fbsd-tdep.c @@ -0,0 +1,237 @@ +/* Target-dependent code for FreeBSD/sparc64. + + Copyright 2003 Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#include "defs.h" +#include "gdbcore.h" +#include "osabi.h" +#include "regcache.h" +#include "target.h" + +#include "gdb_string.h" + +#include "sparc64-tdep.h" + +/* From . */ + +/* Offset of registers in `struct reg'. */ +int sparc64fbsd_r_global_offset = (0 * 8); +int sparc64fbsd_r_out_offset = (8 * 8); +int sparc64fbsd_r_fprs_offset = (16 * 8); +int sparc64fbsd_r_tnpc_offset = (24 * 8); +int sparc64fbsd_r_tpc_offset = (25 * 8); +int sparc64fbsd_r_tstate_offset = (26 * 8); +int sparc64fbsd_r_y_offset = (28 * 8); + +/* Size of `struct reg' and `struct fpreg'. */ +int sparc64fbsd_sizeof_struct_reg = 256; +int sparc64fbsd_sizeof_struct_fpreg = 272; + +void +sparc64fbsd_supply_reg (const char *regs, int regnum) +{ + char buf[8]; + int i; + + if (regnum == SPARC64_PC_REGNUM || regnum == -1) + supply_register (SPARC64_PC_REGNUM, regs + sparc64fbsd_r_tpc_offset); + + if (regnum == SPARC64_NPC_REGNUM || regnum == -1) + supply_register (SPARC64_NPC_REGNUM, regs + sparc64fbsd_r_tnpc_offset); + + if (regnum == SPARC64_STATE_REGNUM || regnum == -1) + supply_register (SPARC64_STATE_REGNUM, regs + sparc64fbsd_r_tstate_offset); + + if (regnum == SPARC64_FPRS_REGNUM || regnum == -1) + supply_register (SPARC64_FPRS_REGNUM, regs + sparc64fbsd_r_fprs_offset); + + if (regnum == SPARC64_Y_REGNUM || regnum == -1) + supply_register (SPARC64_Y_REGNUM, regs + sparc64fbsd_r_y_offset); + + if ((regnum >= SPARC_G0_REGNUM && regnum <= SPARC_G7_REGNUM) || regnum == -1) + { + if (regnum == SPARC_G0_REGNUM || regnum == -1) + supply_register (SPARC_G0_REGNUM, NULL); /* %g0 is always zero. */ + for (i = SPARC_G1_REGNUM; i <= SPARC_G7_REGNUM; i++) + { + if (regnum == i || regnum == -1) + supply_register (i, (regs + sparc64fbsd_r_global_offset + + ((i - SPARC_G0_REGNUM) * 8))); + } + } + + if ((regnum >= SPARC_O0_REGNUM && regnum <= SPARC_O7_REGNUM) || regnum == -1) + { + for (i = SPARC_O0_REGNUM; i <= SPARC_O7_REGNUM; i++) + { + if (regnum == i || regnum == -1) + supply_register (i, (regs + sparc64fbsd_r_out_offset + + ((i - SPARC_O0_REGNUM) * 8))); + } + } + + /* Inputs and Locals are stored onto the stack by by the kernel. */ + if ((regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) || regnum == -1) + { + ULONGEST sp; + + regcache_cooked_read_unsigned (current_regcache, SPARC_SP_REGNUM, &sp); + sparc_supply_rwindow (sp, regnum); + } +} + +void +sparc64fbsd_fill_reg (char *regs, int regnum) +{ + char buf[8]; + int i; + + if (regnum == SPARC64_PC_REGNUM || regnum == -1) + regcache_collect (SPARC64_PC_REGNUM, regs + sparc64fbsd_r_tpc_offset); + + if (regnum == SPARC64_NPC_REGNUM || regnum == -1) + regcache_collect (SPARC64_NPC_REGNUM, regs + sparc64fbsd_r_tnpc_offset); + + if (regnum == SPARC64_FPRS_REGNUM || regnum == -1) + regcache_collect (SPARC64_FPRS_REGNUM, regs + sparc64fbsd_r_fprs_offset); + + if (regnum == SPARC64_Y_REGNUM || regnum == -1) + regcache_collect (SPARC64_Y_REGNUM, regs + sparc64fbsd_r_y_offset); + + if ((regnum >= SPARC_G0_REGNUM && regnum <= SPARC_G7_REGNUM) || regnum == -1) + { + /* %g0 is always zero. */ + for (i = SPARC_G1_REGNUM; i <= SPARC_G7_REGNUM; i++) + { + if (regnum == i || regnum == -1) + regcache_collect (i, (regs + sparc64fbsd_r_global_offset + + ((i - SPARC_G0_REGNUM) * 8))); + } + } + + if ((regnum >= SPARC_O0_REGNUM && regnum <= SPARC_O7_REGNUM) || regnum == -1) + { + for (i = SPARC_O0_REGNUM; i <= SPARC_O7_REGNUM; i++) + { + if (regnum == i || regnum == -1) + regcache_collect (i, (regs + sparc64fbsd_r_out_offset + + ((i - SPARC_O0_REGNUM) * 8))); + } + } + + /* Responsibility for the stack regs is pushed off onto the caller. */ +} + +void +sparc64fbsd_supply_fpreg (const char *fpregs, int regnum) +{ + int i; + + for (i = 0; i < 32; i++) + { + if (regnum == (SPARC_F0_REGNUM + i) || regnum == -1) + supply_register (SPARC_F0_REGNUM + i, fpregs + (i * 4)); + } + + for (i = 0; i < 16; i++) + { + if (regnum == (SPARC64_F32_REGNUM + i) || regnum == -1) + supply_register (SPARC64_F32_REGNUM + i, fpregs + (32 * 4) + (i * 8)); + } + + if (regnum == SPARC64_FSR_REGNUM || regnum == -1) + supply_register (SPARC64_FSR_REGNUM, fpregs + (32 * 4) + (16 * 8)); +} + +void +sparc64fbsd_fill_fpreg (char *fpregs, int regnum) +{ + int i; + + for (i = 0; i < 32; i++) + { + if (regnum == (SPARC_F0_REGNUM + i) || regnum == -1) + regcache_collect (SPARC_F0_REGNUM + i, fpregs + (i * 4)); + } + + for (i = 0; i < 16; i++) + { + if (regnum == (SPARC64_F32_REGNUM + i) || regnum == -1) + regcache_collect (SPARC64_F32_REGNUM + i, fpregs + (32 * 4) + (i * 8)); + } + + if (regnum == SPARC64_FSR_REGNUM || regnum == -1) + regcache_collect (SPARC64_FSR_REGNUM, fpregs + (32 * 4) + (16 * 8)); +} + + +static void +fetch_core_registers (char *core_reg_sect, unsigned core_reg_size, int which, + CORE_ADDR ignore) +{ + switch (which) + { + case 0: /* Integer registers */ + if (core_reg_size != sparc64fbsd_sizeof_struct_reg) + warning ("Wrong size register set in core file."); + else + sparc64fbsd_supply_reg (core_reg_sect, -1); + break; + + case 2: /* Floating pointer registers */ + if (core_reg_size != sparc64fbsd_sizeof_struct_fpreg) + warning ("Wrong size FP register set in core file."); + else + sparc64fbsd_supply_fpreg (core_reg_sect, -1); + break; + + default: + /* Don't know what kind of register request this is; just ignore it. */ + break; + } +} + +static struct core_fns sparc64fbsd_core_fns = +{ + bfd_target_elf_flavour, /* core_flavour */ + default_check_format, /* check_format */ + default_core_sniffer, /* core_sniffer */ + fetch_core_registers, /* core_read_registers */ + NULL +}; + + +static void +sparc64fbsd_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) +{ + /* Nothing yet. */ +} + +/* Provide a prototype to silence -Wmissing-prototypes. */ +void _initialize_sparc64fbsd_tdep (void); + +void +_initialize_sparc64fbsd_tdep (void) +{ + gdbarch_register_osabi (bfd_arch_sparc, bfd_mach_sparc_v9, + GDB_OSABI_FREEBSD_ELF, sparc64fbsd_init_abi); + + add_core_fns (&sparc64fbsd_core_fns); +} diff --git a/gdb/sparcbsd-nat.c b/gdb/sparcbsd-nat.c new file mode 100644 index 0000000..8ab9537 --- /dev/null +++ b/gdb/sparcbsd-nat.c @@ -0,0 +1,126 @@ +/* Native-dependent code for SPARC BSD's. + + Copyright 2002, 2003 Free Software Foundation, Inc. + Based on code contributed by Wasabi Systems, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#include "defs.h" +#include "inferior.h" +#include "regcache.h" + +/* FIXME: Should be changed to sparc-tdep.h when the old code is gone. */ +#include "sparc64-tdep.h" +#include "sparcbsd-nat.h" + +#include +#include +#include + +/* Functions translating between `struct reg' and `struct fpreg' and + GDB's register cache. */ +void (*sparcbsd_supply_reg)(const char *, int); +void (*sparcbsd_fill_reg)(char *, int); +void (*sparcbsd_supply_fpreg)(const char *, int); +void (*sparcbsd_fill_fpreg)(char *, int); + +/* Functions indication whether `struct reg' or `struct fpreg' provides + a certain register. */ +int (*sparcbsd_reg_supplies_p)(int); +int (*sparcbsd_fpreg_supplies_p)(int); + +void +fetch_inferior_registers (int regnum) +{ + if (regnum == -1 || sparcbsd_reg_supplies_p (regnum)) + { + struct reg regs; + + if (ptrace (PT_GETREGS, PIDGET (inferior_ptid), + (PTRACE_ARG3_TYPE) ®s, 0) == -1) + perror_with_name ("Couldn't get registers"); + + sparcbsd_supply_reg ((char *) ®s, regnum); + if (regnum != -1) + return; + } + + if (regnum == -1 || sparcbsd_fpreg_supplies_p (regnum)) + { + struct fpreg fpregs; + + if (ptrace (PT_GETFPREGS, PIDGET (inferior_ptid), + (PTRACE_ARG3_TYPE) &fpregs, 0) == -1) + perror_with_name ("Couldn't get floating-point registers"); + + sparcbsd_supply_fpreg ((char *) &fpregs, regnum); + if (regnum != -1) + return; + } +} + +void +store_inferior_registers (int regnum) +{ + if (regnum == -1 || sparcbsd_reg_supplies_p (regnum)) + { + struct reg regs; + + if (ptrace (PT_GETREGS, PIDGET (inferior_ptid), + (PTRACE_ARG3_TYPE) ®s, 0) == -1) + perror_with_name ("Couldn't get registers"); + + sparcbsd_fill_reg ((char *) ®s, regnum); + + if (ptrace (PT_SETREGS, PIDGET (inferior_ptid), + (PTRACE_ARG3_TYPE) ®s, 0) == -1) + perror_with_name ("Couldn't write registers"); + + /* Deal with the stack regs. */ + if (regnum == -1 || regnum == SPARC_SP_REGNUM + || (regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM)) + { + ULONGEST sp; + + regcache_cooked_read_unsigned (current_regcache, + SPARC_SP_REGNUM, &sp); + sparc_fill_rwindow (sp, regnum); + } + + if (regnum != -1) + return; + } + + if (regnum == -1 || sparcbsd_fpreg_supplies_p (regnum)) + { + struct fpreg fpregs; + + if (ptrace (PT_GETFPREGS, PIDGET (inferior_ptid), + (PTRACE_ARG3_TYPE) &fpregs, 0) == -1) + perror_with_name ("Couldn't get floating-point registers"); + + sparcbsd_fill_fpreg ((char *) &fpregs, regnum); + + if (ptrace (PT_SETFPREGS, PIDGET (inferior_ptid), + (PTRACE_ARG3_TYPE) &fpregs, 0) == -1) + perror_with_name ("Couldn't write floating-point registers"); + + if (regnum != -1) + return; + } +} diff --git a/gdb/sparcbsd-nat.h b/gdb/sparcbsd-nat.h new file mode 100644 index 0000000..326d669 --- /dev/null +++ b/gdb/sparcbsd-nat.h @@ -0,0 +1,37 @@ +/* Native-dependent code for SPARC BSD's. + + Copyright 2003 Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#ifndef SPARCBSD_NAT_H +#define SPARCBSD_NAT_H + +/* Functions translating between `struct reg' and `struct fpreg' and + GDB's register cache. */ +extern void (*sparcbsd_supply_reg)(const char *, int); +extern void (*sparcbsd_fill_reg)(char *, int); +extern void (*sparcbsd_supply_fpreg)(const char *, int); +extern void (*sparcbsd_fill_fpreg)(char *, int); + +/* Functions indication whether `struct reg' or `struct fpreg' provides + a certain register. */ +extern int (*sparcbsd_reg_supplies_p)(int); +extern int (*sparcbsd_fpreg_supplies_p)(int); + +#endif /* sparcbsd-nat.h */ diff --git a/gdb/stack.h b/gdb/stack.h new file mode 100644 index 0000000..0891c94 --- /dev/null +++ b/gdb/stack.h @@ -0,0 +1,27 @@ +/* Stack manipulation commands, for GDB the GNU Debugger. + + Copyright 2003 Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#ifndef STACK_H +#define STACK_H + +void select_frame_command (char *level_exp, int from_tty); + +#endif /* #ifndef STACK_H */ diff --git a/gdb/testsuite/gdb.arch/e500-abi.c b/gdb/testsuite/gdb.arch/e500-abi.c new file mode 100644 index 0000000..e215612 --- /dev/null +++ b/gdb/testsuite/gdb.arch/e500-abi.c @@ -0,0 +1,106 @@ +#include + +/* Test PowerPC SPU extensions. */ + +#define vector __attribute__((vector_size(8))) + +vector unsigned short f_vec; +vector short g_vec; +vector float h_vec; +vector float i_vec; +vector unsigned int l_vec; +vector int m_vec; +vector int n_vec; + +/* dummy variables used in the testfile */ +vector unsigned int a_vec_d = {1, 1}; +vector int b_vec_d = {0, 0}; +vector float c_vec_d = {1.0, 1.0}; +vector unsigned int d_vec_d = {0, 0}; +vector int e_vec_d = {1, 1}; +vector unsigned short f_vec_d = {1, 1, 1, 1}; +vector short g_vec_d = {1, 1, 1, 1}; +vector float h_vec_d = {1.0, 1.0}; +vector float i_vec_d = {2.0, 2.0}; +vector unsigned int l_vec_d = {0, 0}; +vector int m_vec_d = {0, 0}; + + +vector int +vec_func (vector unsigned int a_vec_f, + vector int b_vec_f, + vector float c_vec_f, + vector unsigned int d_vec_f, + vector int e_vec_f, + vector unsigned short f_vec_f, + vector short g_vec_f, + vector float h_vec_f, + vector float i_vec_f, + vector unsigned int l_vec_f, + vector int m_vec_f) +{ + vector int n_vec; + + + int x,y,z; + x = 2; + y = 3; + + z = x + y; + z++; + n_vec = __ev_and(a_vec_f, b_vec_f); + n_vec = __ev_or(c_vec_f, d_vec_f); + n_vec = __ev_or(e_vec_f, f_vec_f); + n_vec = __ev_and(g_vec_f, h_vec_f); + n_vec = __ev_and(i_vec_f, l_vec_f); + n_vec = __ev_or(m_vec_f, a_vec_f); + + return n_vec; +} + +void marker(void) {}; + +int +main (void) +{ + vector unsigned int a_vec; + vector int b_vec; + vector float c_vec; + vector unsigned int d_vec; + vector int e_vec; + + vector int res_vec; + + a_vec = (vector unsigned int)__ev_create_u64 ((uint64_t) 55); + b_vec = __ev_create_s64 ((int64_t) 66); + c_vec = (vector float) __ev_create_fs (3.14F, 2.18F); + d_vec = (vector unsigned int) __ev_create_u32 ((uint32_t) 5, (uint32_t) 4); + e_vec = (vector int) __ev_create_s32 ((int32_t) 5, (int32_t) 6); + f_vec = (vector unsigned short) __ev_create_u16 ((uint16_t) 6, (uint16_t) 6, (uint16_t) 7, (uint16_t) 1); + g_vec = (vector short) __ev_create_s16 ((int16_t) 6, (int16_t) 6, (int16_t) 7, (int16_t) 9); + h_vec = (vector float) __ev_create_sfix32_fs (3.0F, 2.0F); + i_vec = (vector float) __ev_create_ufix32_fs (3.0F, 2.0F); + l_vec = (vector unsigned int) __ev_create_ufix32_u32 (3U, 5U); + m_vec = (vector int) __ev_create_sfix32_s32 (6, 9); + + marker (); + +#if 0 +/* This line is useful for cut-n-paste from a gdb session. */ +vec_func(a_vec,b_vec,c_vec,d_vec,e_vec,f_vec,g_vec,h_vec,i_vec,l_vec,m_vec) +#endif + + res_vec = vec_func (a_vec, /* goes in r3 */ + b_vec, /* goes in r4 */ + c_vec, /* goes in r5 */ + d_vec, /* goes in r6 */ + e_vec, /* goes in r7 */ + f_vec, /* goes in r8 */ + g_vec, /* goes in r9 */ + h_vec, /* goes in r10 */ + i_vec, /* goes in stack */ + l_vec, /* goes in stack */ + m_vec); /* goes in stack */ + + return 0; +} diff --git a/gdb/testsuite/gdb.arch/e500-abi.exp b/gdb/testsuite/gdb.arch/e500-abi.exp new file mode 100644 index 0000000..0d11ad3 --- /dev/null +++ b/gdb/testsuite/gdb.arch/e500-abi.exp @@ -0,0 +1,90 @@ +# Copyright 2003 Free Software Foundation, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. +# +# Please email any bugs, comments, and/or additions to this file to: +# bug-gdb@prep.ai.mit.edu +# + +# Tests for Powerpc e500 ABI + + +if $tracelevel then { + strace $tracelevel +} + +# +# This file uses e500-abi.c for input. +# + +set prms_id 0 +set bug_id 0 + +if ![istarget "powerpc-*eabispe"] then { + verbose "Skipping e500 abi tests." + return +} + +set testfile "e500-abi" +set binfile ${objdir}/${subdir}/${testfile} + +set src1 ${srcdir}/${subdir}/${testfile}.c + +if { [gdb_compile ${src1} ${binfile} executable {debug additional_flags=-w}] != "" } { + gdb_suppress_entire_file "Testcase compile failed, so all tests in this file will automatically fail." +} + +gdb_start +gdb_reinitialize_dir $srcdir/$subdir +gdb_load ${binfile} + +# +# Run to `main' where we begin our tests. +# + +if ![runto_main] then { + gdb_suppress_tests +} + +gdb_test "b marker" "Breakpoint 2 at.*file.*e500-abi.c, line \[0-9\]+." "break marker" +gdb_test "continue" "Breakpoint 2.*marker.*e500-abi.c.*" "continue to marker" +gdb_test "finish" "Run till exit from .0.*marker.*at.*e500-abi.c.*main \\(\\) at.*e500-abi.c.*res_vec = vec_func \\(a_vec,.*goes in r3.*" "back to main (1)" + +# now all the arguments of vec_func are initialized + +set pattern "vec_func .a_vec_f=.0, 55., b_vec_f=.0, 66., c_vec_f=.3.14.*2.18.*, d_vec_f=.5, 4., e_vec_f=.5, 6., f_vec_f=.6, 6, 7, 1., g_vec_f=.6, 6, 7, 9., h_vec_f=.3, 2., i_vec_f=.3, 2., l_vec_f=.3, 5., m_vec_f=.6, 9.." + +set pattern1 $pattern +append pattern1 " at.*e500-abi.c.*x = 2;" + +# Now let's call the function. This function has > 8 args, +# the last ones will go on the stack. +gdb_test "p vec_func(a_vec,b_vec,c_vec,d_vec,e_vec,f_vec,g_vec,h_vec,i_vec,l_vec,m_vec)" \ +".\[0-9\]+ = .6, 63." "call inferior function with vectors (1) " + +# Let's call the function again with dummy arguments. This is to clean +# up the contents of the ev registers before the next call. +gdb_test "p vec_func(a_vec_d,b_vec_d,c_vec_d,d_vec_d,e_vec_d,f_vec_d,g_vec_d,h_vec_d,i_vec_d,l_vec_d,m_vec_d)" \ +".\[0-9\]+ = .1, 1." "call inferior function with vectors (2) " + +# Let's step into the function, to see if the args are printed correctly. +gdb_test "step" \ + $pattern1 \ + "step into vec_func" + +# Let's see if the result is returned correctly. +gdb_test "finish" \ + "Run till exit from .0.* at.*e500-abi.c.*main.*res_vec = vec_func .a_vec,.*goes in r3.*Value returned is.*= .6, 63." \ + "vector value returned correctly" diff --git a/gdb/testsuite/gdb.arch/e500-regs.c b/gdb/testsuite/gdb.arch/e500-regs.c new file mode 100644 index 0000000..bae5f39 --- /dev/null +++ b/gdb/testsuite/gdb.arch/e500-regs.c @@ -0,0 +1,38 @@ +#include +#include + +#define vector __attribute__((vector_size(8))) + + +vector int +vector_fun (vector int a, vector int b) +{ + vector int c; + a = (vector int) __ev_create_s32 (2, 2); + b = (vector int) __ev_create_s32 (3, 3); + + c = __ev_and (a, b); + return c; +} + +int +main () +{ + vector int y; + vector int x; + vector int z; + int a; + + /* This line may look unnecessary but we do need it, because we want to + have a line to do a next over (so that gdb refetches the registers) + and we don't want the code to change any vector registers. + The splat operations below modify the VRs, + so we don't want to execute them yet. */ + a = 9; + x = (vector int) __ev_create_s32 (-2, -2); + y = (vector int) __ev_create_s32 (1, 1); + + z = vector_fun (x, y); + + return 0; +} diff --git a/gdb/testsuite/gdb.arch/e500-regs.exp b/gdb/testsuite/gdb.arch/e500-regs.exp new file mode 100644 index 0000000..9224704 --- /dev/null +++ b/gdb/testsuite/gdb.arch/e500-regs.exp @@ -0,0 +1,229 @@ +# Copyright 2003 Free Software Foundation, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. +# +# Please email any bugs, comments, and/or additions to this file to: +# bug-gdb@prep.ai.mit.edu +# + +# Tests for Powerpc E500 register setting and fetching + +if $tracelevel then { + strace $tracelevel +} + +# +# Test the use of registers, especially E500 registers, for Powerpc. +# This file uses e500-regs.c for input. +# + +set prms_id 0 +set bug_id 0 + +if ![istarget "powerpc-*eabispe"] then { + verbose "Skipping e500 register tests." + return +} + +set testfile "e500-regs" +set binfile ${objdir}/${subdir}/${testfile} +set src1 ${srcdir}/${subdir}/${testfile}.c + +if { [gdb_compile ${src1} ${binfile} executable {debug additional_flags=-w}] != "" } { + gdb_suppress_entire_file "Testcase compile failed, so all tests in this file will automatically fail." +} + +gdb_start +gdb_reinitialize_dir $srcdir/$subdir +gdb_load ${binfile} + +# +# Run to `main' where we begin our tests. +# + +if ![runto_main] then { + gdb_suppress_tests +} + +# set all the registers integer portions to 1 +for {set i 0} {$i < 32} {incr i 1} { + for {set j 0} {$j < 2} {incr j 1} { + gdb_test "set \$ev$i.v2_int32\[$j\] = 1" "" "set reg ev$i.v4si.f\[$j\]" + } +} + +# Now execute some target code, so that GDB's register cache is flushed. + +#gdb_test "next" "" "" + +send_gdb "show endian\n" +gdb_expect { + -re "(The target endianness is set automatically .currently )(big|little)( endian.*)$gdb_prompt $" { + pass "endianness" + set endianness $expect_out(2,string) + } + -re ".*$gdb_prompt $" { + fail "couldn't get endianness" + } + timeout { fail "(timeout) endianness" } +} + +# And then read the E500 registers back, to see that +# a) the register write above worked, and +# b) the register read (below) also works. + +if {$endianness == "big"} { +set vector_register ".uint64 = 0x100000001, v2_float = .0x0, 0x0., v2_int32 = .0x1, 0x1., v4_int16 = .0x0, 0x1, 0x0, 0x1., v8_int8 = .0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.." +} else { +set vector_register ".uint64 = 0x100000001, v2_float = .0x0, 0x0., v2_int32 = .0x1, 0x1., v4_int16 = .0x1, 0x0, 0x1, 0x0., v8_int8 = .0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0.." +} + +for {set i 0} {$i < 32} {incr i 1} { + gdb_test "info reg ev$i" "ev$i.*$vector_register" "info reg ev$i" +} + +# Test wether the GPRs are updated accordingly. (GPRs are just the lower +# 32 bits of the EV registers.) + +set general_register "0x1\[ \t\]+1" + +for {set i 0} {$i < 32} {incr i 1} { + gdb_test "info reg r$i" "r$i.*$general_register" "info reg r$i" +} + +# Now redo the same tests, but using the print command. +# Note: in LE case, the char array is printed WITHOUT the last character. +# Gdb treats the terminating null char in the array like the terminating +# null char in a string and doesn't print it. This is not a failure, but +# the way gdb works. + +if {$endianness == "big"} { + set decimal_vector ".uint64 = 4294967297, v2_float = .1.*e-45, 1.*e-45., v2_int32 = .1, 1., v4_int16 = .0, 1, 0, 1., v8_int8 = ..000.000.000.001.000.000.000.001.." +} else { + set decimal_vector ".uint64 = 0x0000000100000001, v2_float = .1.*e-45, 1.*e-45., v2_int32 = .1, 1., v4_int16 = .1, 0, 1, 0., v8_int8 = ..001.000.000.000.001.000.000.000.001.000.000.000.001.000.000.." +} + +for {set i 0} {$i < 32} {incr i 1} { + gdb_test "print \$ev$i" ".* = $decimal_vector" "print ev$i" +} + +for {set i 0} {$i < 32} {incr i 1} { + set pattern$i ".*ev$i.*" + append pattern$i $vector_register +} + +send_gdb "info vector\n" +gdb_expect_list "info vector" ".*$gdb_prompt $" { +[$pattern0] +[$pattern1] +[$pattern2] +[$pattern3] +[$pattern4] +[$pattern5] +[$pattern6] +[$pattern7] +[$pattern8] +[$pattern9] +[$pattern10] +[$pattern11] +[$pattern12] +[$pattern13] +[$pattern14] +[$pattern15] +[$pattern16] +[$pattern17] +[$pattern18] +[$pattern19] +[$pattern20] +[$pattern21] +[$pattern22] +[$pattern23] +[$pattern24] +[$pattern25] +[$pattern26] +[$pattern27] +[$pattern28] +[$pattern29] +[$pattern30] +[$pattern31] +} + +# We must restart everything, because we have set important registers to +# some unusual values. + +gdb_exit +gdb_start +gdb_reinitialize_dir $srcdir/$subdir +gdb_load ${binfile} +if ![runto_main] then { + gdb_suppress_tests +} + +gdb_test "break vector_fun" \ + "Breakpoint 2 at.*e500-regs.c, line \[0-9\]+\\." \ + "Set breakpoint at vector_fun" + +# Actually it is nuch easier to see these results printed in hex. +# gdb_test "set output-radix 16" \ +# "Output radix now set to decimal 16, hex 10, octal 20." \ +# "Set output radix to hex" + +gdb_test "continue" \ + "Breakpoint 2, vector_fun .a=.-2, -2., b=.1, 1.*e500-regs.c.*ev_create_s32 .2, 2.;" \ + "continue to vector_fun" + +# Do a next over the assignment to vector 'a'. +gdb_test "next" ".*b = \\(vector int\\) __ev_create_s32 \\(3, 3\\);" \ + "next (1)" + +# Do a next over the assignment to vector 'b'. +gdb_test "next" "c = __ev_and \\(a, b\\);" \ + "next (2)" + +# Now 'a' should be '0x02020202...' and 'b' should be '0x03030303...' +gdb_test "print/x a" \ + ".*= .0x2, 0x2." \ + "print vector parameter a" + +gdb_test "print/x b" \ + ".*= .0x3, 0x3." \ + "print vector parameter b" + +# If we do an 'up' now, and print 'x' and 'y' we should see the values they +# have in main, not the values they have in vector_fun. +gdb_test "up" ".1.*main \\(\\) at.*e500-regs.c.*z = vector_fun \\(x, y\\);" \ + "up to main" + +gdb_test "print x" \ + ".*= .-2, -2." \ + "print vector x" + +gdb_test "print y" \ + ".*= .1, 1." \ + "print vector y" + +# now go back to vector_func and do a finish, to see if we can print the return +# value correctly. + +gdb_test "down" \ + ".0 vector_fun \\(a=.2, 2., b=.3, 3.\\) at.*e500-regs.c.*c = __ev_and \\(a, b\\);" \ + "down to vector_fun" + +gdb_test "finish" \ + "Run till exit from .0 vector_fun \\(a=.2, 2., b=.3, 3.\\) at.*e500-regs.c.*main \\(\\) at.*e500-regs.c.*z = vector_fun \\(x, y\\);.*Value returned is.*= .2, 2." \ + "finish returned correct value" + + + diff --git a/gdb/testsuite/gdb.arch/gdb1291.c b/gdb/testsuite/gdb.arch/gdb1291.c new file mode 100755 index 0000000..2178f70 --- /dev/null +++ b/gdb/testsuite/gdb.arch/gdb1291.c @@ -0,0 +1,44 @@ +/* Copyright 2003 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + + Please email any bugs, comments, and/or additions to this file to: + bug-gdb@gnu.org + + This file is part of the gdb testsuite. */ + +void sub (void); + +main() +{ + sub(); +} + +asm(".text\n" + " .align 5\n" + "sub:\n" + " mov.l r14,@-r15\n" + " mov.w .STACK2,r3\n" + " sub r3,r15\n" + " mov r15,r14\n" + " mov.w .STACK2,r7\n" + " add r7,r14\n" + " mov r14,r15\n" + " mov.l @r15+,r14\n" + " rts\n" + " nop\n" + " .align 1\n" + ".STACK2:\n" + " .short 260\n"); diff --git a/gdb/testsuite/gdb.arch/gdb1291.exp b/gdb/testsuite/gdb.arch/gdb1291.exp new file mode 100644 index 0000000..2c1f4cc --- /dev/null +++ b/gdb/testsuite/gdb.arch/gdb1291.exp @@ -0,0 +1,62 @@ +# Copyright 2003 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# Please email any bugs, comments, and/or additions to this file to: +# bug-gdb@gnu.org + +# This file is part of the gdb testsuite. + +# Tests for PR:1291. Ensure that backtrace works properly for stack +# frames greater than 256 bytes. + +if $tracelevel { + strace $tracelevel +} + +# Test SH backtraces with >256 byte frame stack. (PR:1291) + +set prms_id 0 +set bug_id 0 + +if ![istarget "sh-*-*"] then { + verbose "Skipping SH backtrace tests." + return +} + +set testfile "gdb1291" +set srcfile ${testfile}.c +set binfile ${objdir}/${subdir}/${testfile} +if { [gdb_compile "${srcdir}/${subdir}/${srcfile}" "${binfile}" executable {debug}] != "" } { + gdb_suppress_entire_file "Testcase compile failed, so all tests in this file will automatically fail." +} + +gdb_exit +gdb_start +gdb_reinitialize_dir $srcdir/$subdir +gdb_load ${binfile} + +# +# Run to `main' where we begin our tests. +# + +if ![runto_main] then { + gdb_suppress_tests +} + +gdb_test "b sub" "Breakpoint 2*" "set breakpoint" +gdb_test "c" "Breakpoint 2*" "get to sub" +gdb_test "bt" "#0\[ \t\]*$hex \\(\\) at sh-bt.*\r\n#1\[ \t\]*$hex in main.*" \ + "backtrace in gdb1291" diff --git a/gdb/testsuite/gdb.arch/gdb1431.c b/gdb/testsuite/gdb.arch/gdb1431.c new file mode 100755 index 0000000..0041042 --- /dev/null +++ b/gdb/testsuite/gdb.arch/gdb1431.c @@ -0,0 +1,63 @@ +/* Copyright 2003 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + + Please email any bugs, comments, and/or additions to this file to: + bug-gdb@gnu.org + + This file is part of the gdb testsuite. */ + +void sub1 (void); +void sub2 (void); + +main() +{ + sub1(); + sub2(); +} + +asm(".text\n" + " .align 5\n" + "sub1:\n" + " mov.l r14,@-r15\n" + " add #-128,r15\n" + " add #-128,r15\n" + " mov r15,r14\n" + " mov.w .STACK1,r7\n" + " add r7,r14\n" + " mov r14,r15\n" + " mov.l @r15+,r14\n" + " rts\n" + " nop\n" + " .align 1\n" + ".STACK1:\n" + " .short 256\n"); + +asm(".text\n" + " .align 5\n" + "sub2:\n" + " mov.l r14,@-r15\n" + " mov.w .STACK2,r3\n" + " sub r3,r15\n" + " mov r15,r14\n" + " mov.w .STACK2,r7\n" + " add r7,r14\n" + " mov r14,r15\n" + " mov.l @r15+,r14\n" + " rts\n" + " nop\n" + " .align 1\n" + ".STACK2:\n" + " .short 260\n"); diff --git a/gdb/testsuite/gdb.arch/gdb1431.exp b/gdb/testsuite/gdb.arch/gdb1431.exp new file mode 100644 index 0000000..15bff46 --- /dev/null +++ b/gdb/testsuite/gdb.arch/gdb1431.exp @@ -0,0 +1,66 @@ +# Copyright 2003 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# Please email any bugs, comments, and/or additions to this file to: +# bug-gdb@gnu.org + +# This file is part of the gdb testsuite. + +# Tests for PR:1431. Catch gdb not continuing to second function properly. + +if $tracelevel { + strace $tracelevel +} + +# Observe that the until command doesn't go all the way to sub2. + +set prms_id 0 +set bug_id 0 + +if ![istarget "sh-*-*"] then { + verbose "Skipping SH backtrace tests." + return +} + +set testfile "gdb1431" +set srcfile ${testfile}.c +set binfile ${objdir}/${subdir}/${testfile} +if { [gdb_compile "${srcdir}/${subdir}/${srcfile}" "${binfile}" executable {debug}] != "" } { + gdb_suppress_entire_file "Testcase compile failed, so all tests in this file will automatically fail." +} + +gdb_exit +gdb_start +gdb_reinitialize_dir $srcdir/$subdir +gdb_load ${binfile} + +# +# Run to `main' where we begin our tests. +# + +if ![runto_main] then { + gdb_suppress_tests +} + +gdb_test "u sub1" "sub1*" "get to sub1" +gdb_test "bt" "#0\[ \t\]*$hex \\(\\) at sh-bt.*\r\n#1\[ \t\]*$hex in main.*" \ + "backtrace in gdb1291" + +kfail "gdb/1431" "u sub2" +# This is what we would expect to be able to do: +#gdb_test "u sub2" "sub2*" "get to sub2" +#gdb_test "bt" "#0\[ \t\]*$hex \\(\\) at sh-bt.*\r\n#1\[ \t\]*$hex in main.*" \ +# "backtrace in gdb1291" diff --git a/gdb/testsuite/gdb.arch/i386-prologue.c b/gdb/testsuite/gdb.arch/i386-prologue.c new file mode 100644 index 0000000..4c92a9c --- /dev/null +++ b/gdb/testsuite/gdb.arch/i386-prologue.c @@ -0,0 +1,37 @@ +void gdb1253 (void); +void gdb1338 (void); + +int +main (void) +{ + gdb1253 (); + gdb1338 (); + return 0; +} + +/* Relevant part of the prologue from symtab/1253. */ + +asm(".text\n" + " .align 8\n" + "gdb1253:\n" + " pushl %ebp\n" + " xorl %ecx, %ecx\n" + " movl %esp, %ebp\n" + " pushl %edi\n" + " int $0x03\n" + " leave\n" + " ret\n"); + +/* Relevant part of the prologue from backtrace/1338. */ + +asm(".text\n" + " .align 8\n" + "gdb1338:\n" + " pushl %edi\n" + " pushl %esi\n" + " pushl %ebx\n" + " int $0x03\n" + " popl %ebx\n" + " popl %esi\n" + " popl %edi\n" + " ret\n"); diff --git a/gdb/testsuite/gdb.arch/i386-prologue.exp b/gdb/testsuite/gdb.arch/i386-prologue.exp new file mode 100644 index 0000000..f1c1e72 --- /dev/null +++ b/gdb/testsuite/gdb.arch/i386-prologue.exp @@ -0,0 +1,78 @@ +# Copyright 2003 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# Please email any bugs, comments, and/or additions to this file to: +# bug-gdb@gnu.org + +# This file is part of the gdb testsuite. + +if $tracelevel { + strace $tracelevel +} + +# Test i386 prologue analyzer. + +set prms_id 0 +set bug_id 0 + +if ![istarget "i?86-*-*"] then { + verbose "Skipping i386 prologue tests." + return +} + +set testfile "i386-prologue" +set srcfile ${testfile}.c +set binfile ${objdir}/${subdir}/${testfile} +if { [gdb_compile "${srcdir}/${subdir}/${srcfile}" "${binfile}" executable {debug}] != "" } { + gdb_suppress_entire_file "Testcase compile failed, so all tests in this file will automatically fail." +} + +gdb_exit +gdb_start +gdb_reinitialize_dir $srcdir/$subdir +gdb_load ${binfile} + +# +# Run to `main' where we begin our tests. +# + +if ![runto_main] then { + gdb_suppress_tests +} + +# Testcase from symtab/1253. + +gdb_test "continue" "Program received signal SIGTRAP.*" "continue to gdb1253" + +gdb_test "backtrace 10" \ + "#0\[ \t\]*$hex in gdb1253.*\r\n#1\[ \t\]*$hex in main.*" \ + "backtrace in gdb1253" + +gdb_test "info frame" \ + ".*Saved registers:.*ebp at.*edi at.*eip at.*" \ + "saved registers in gdb1253" + +# Testcase from backtrace/1338. + +gdb_test "continue" "Program received signal SIGTRAP.*" "continue to gdb1338" + +gdb_test "backtrace 10" \ + "#0\[ \t\]*$hex in gdb1338.*\r\n#1\[ \t\]*$hex in main.*" \ + "backtrace in gdb1338" + +gdb_test "info frame" \ + ".*Saved registers:.*ebx at.*esi at.*edi at.*eip at.*" \ + "saved registers in gdb1338" diff --git a/gdb/testsuite/gdb.arch/i386-unwind.c b/gdb/testsuite/gdb.arch/i386-unwind.c new file mode 100644 index 0000000..6d10ecb --- /dev/null +++ b/gdb/testsuite/gdb.arch/i386-unwind.c @@ -0,0 +1,42 @@ +/* Unwinder test program. + + Copyright 2003 Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +void +trap (void) +{ + asm ("int $0x03"); +} + +/* Make sure that main directly follows a function without an + epilogue. */ + +asm(".text\n" + " .align 8\n" + " .globl gdb1435\n" + "gdb1435:\n" + " pushl %ebp\n" + " mov %esp, %ebp\n" + " call trap\n" + " .globl main\n" + "main:\n" + " pushl %ebp\n" + " mov %esp, %ebp\n" + " call gdb1435\n"); diff --git a/gdb/testsuite/gdb.arch/i386-unwind.exp b/gdb/testsuite/gdb.arch/i386-unwind.exp new file mode 100644 index 0000000..9c3130f --- /dev/null +++ b/gdb/testsuite/gdb.arch/i386-unwind.exp @@ -0,0 +1,68 @@ +# Copyright 2003 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# Please email any bugs, comments, and/or additions to this file to: +# bug-gdb@gnu.org + +# This file is part of the gdb testsuite. + +if $tracelevel { + strace $tracelevel +} + +# Test i386 unwinder. + +set prms_id 0 +set bug_id 0 + +if ![istarget "i?86-*-*"] then { + verbose "Skipping i386 unwinder tests." + return +} + +set testfile "i386-unwind" +set srcfile ${testfile}.c +set binfile ${objdir}/${subdir}/${testfile} +if { [gdb_compile "${srcdir}/${subdir}/${srcfile}" "${binfile}" executable {debug}] != "" } { + gdb_suppress_entire_file "Testcase compile failed, so all tests in this file will automatically fail." +} + +gdb_exit +gdb_start +gdb_reinitialize_dir $srcdir/$subdir +gdb_load ${binfile} + +# Testcase for backtrace/1435. + +# We use gdb_run_cmd so this stands a chance to work for remote +# targets too. +gdb_run_cmd + +gdb_expect { + -re "Program received signal SIGTRAP.*$gdb_prompt $" { + pass "run past gdb1435" + } + -re ".*$gdb_prompt $" { + fail "run past gdb1435" + } + timeout { + fail "run past gdb1435 (timeout)" + } +} + +gdb_test "backtrace 10" \ + "#1\[ \t]*$hex in gdb1435.*\r\n#2\[ \t\]*$hex in main.*" \ + "backtrace past gdb1435" diff --git a/gdb/testsuite/gdb.asm/alpha.inc b/gdb/testsuite/gdb.asm/alpha.inc new file mode 100644 index 0000000..f9741c4 --- /dev/null +++ b/gdb/testsuite/gdb.asm/alpha.inc @@ -0,0 +1,62 @@ + comment "subroutine declare" + .macro gdbasm_declare name + .ent \name +\name: + .endm + + comment "subroutine prologue" + .macro gdbasm_enter + .frame $30, 16, $26, 0 + .mask 0x04000000, -16 + ldgp $gp, 0($27) + subq $sp, 16, $sp + stq $26, 0($sp) + .prologue 1 + .endm + + comment "subroutine epilogue" + .macro gdbasm_leave + ldq $26, 0($sp) + addq $sp, 16, $sp + ret + .endm + + comment "subroutine end" + .macro gdbasm_end name + .end \name + .endm + + comment "subroutine call" + /* Can't use ldgp here because the finish-frame test expects the + pc to wind up on the next line. That's ok, we're all local. */ + .macro gdbasm_call subr + jsr $26, \subr + .endm + + .macro gdbasm_several_nops + nop + nop + nop + nop + .endm + + comment "exit (0)" + .macro gdbasm_exit0 + lda $16, 0($31) + lda $0, 1($31) + callsys + .endm + + comment "crt0 startup" + .macro gdbasm_startup + .frame $31, 0, $31, 0 + .prologue + ldgp $gp, 0($27) + .endm + + comment "Declare a data variable" + .macro gdbasm_datavar name value + .data +\name: + .long \value + .endm diff --git a/gdb/testsuite/gdb.asm/empty.inc b/gdb/testsuite/gdb.asm/empty.inc new file mode 100644 index 0000000..e786488 --- /dev/null +++ b/gdb/testsuite/gdb.asm/empty.inc @@ -0,0 +1 @@ + comment "empty" diff --git a/gdb/testsuite/gdb.asm/frv.inc b/gdb/testsuite/gdb.asm/frv.inc new file mode 100644 index 0000000..e8f3b8f --- /dev/null +++ b/gdb/testsuite/gdb.asm/frv.inc @@ -0,0 +1,54 @@ + comment "subroutine prologue" + .macro gdbasm_enter + addi sp,#-16,sp + sti fp, @(sp,0) + mov sp, fp + movsg lr, gr5 + sti gr5, @(fp,8) + .endm + + comment "subroutine epilogue" + .macro gdbasm_leave + ldi @(fp,8), gr5 + ld @(fp,gr0), fp + addi sp,#16,sp + jmpl @(gr5,gr0) + .endm + + .macro gdbasm_call subr + call \subr + .endm + + .macro gdbasm_several_nops + nop + nop + nop + nop + .endm + + comment "exit (0)" + .macro gdbasm_exit0 + comment "Don't know how to exit, but this will certainly halt..." + ldi @(gr0,0), gr5 + .endm + + comment "crt0 startup" + .macro gdbasm_startup + call .Lcall +.Lcall: movsg lr, gr4 + sethi #gprelhi(.Lcall), gr5 + setlo #gprello(.Lcall), gr5 + sub gr4, gr5, gr16 + + sethi #gprelhi(_stack), sp + setlo #gprello(_stack), sp + setlos #0, fp + add sp, gr16, sp + .endm + + comment "Declare a data variable" + .macro gdbasm_datavar name value + .data +\name: + .long \value + .endm diff --git a/gdb/testsuite/gdb.asm/ia64.inc b/gdb/testsuite/gdb.asm/ia64.inc new file mode 100644 index 0000000..d55cd22 --- /dev/null +++ b/gdb/testsuite/gdb.asm/ia64.inc @@ -0,0 +1,49 @@ + comment "subroutine prologue" + .macro gdbasm_enter + alloc r33=ar.pfs,0,2,0,0 + mov r32=b0 + nop.i 0 + .endm + + comment "subroutine epilogue" + .macro gdbasm_leave + nop.m 0 + mov ar.pfs=r33 + mov b0=r32 + nop.m 0 + nop.f 0 + br.ret.sptk.many b0 + .endm + + .macro gdbasm_call subr + nop.m 0 + nop.f 0 + br.call.sptk.many b0=\subr + .endm + + .macro gdbasm_several_nops + nop.m 0 + nop.i 0 + nop.i 0 + .endm + + comment "exit (0)" + .macro gdbasm_exit0 + break.m 0x0 + nop.m 0 + nop.i 0 + .endm + + comment "crt0 startup" + .macro gdbasm_startup + mov r32=r0 + nop.i 0 + nop.i 0 + .endm + + comment "Declare a data variable" + .macro gdbasm_datavar name value + .data +\name: + .long \value + .endm diff --git a/gdb/testsuite/gdb.asm/m68hc11.inc b/gdb/testsuite/gdb.asm/m68hc11.inc new file mode 100644 index 0000000..90795e3 --- /dev/null +++ b/gdb/testsuite/gdb.asm/m68hc11.inc @@ -0,0 +1,49 @@ + comment "subroutine prologue" + .macro gdbasm_enter + ldx _.frame + pshx + sts _.frame + .endm + + comment "subroutine epilogue" + .macro gdbasm_leave + pulx + stx _.frame + rts + .endm + + .macro gdbasm_call subr + jsr \subr + .endm + + .macro gdbasm_several_nops + nop + nop + nop + nop + .endm + + comment "exit (0)" + .macro gdbasm_exit0 + clra + clrb + wai + .endm + + comment "crt0 startup" + .macro gdbasm_startup + .sect .data + .globl _.frame +_.frame: .word 0 + .previous + lds #0x2000 + clr _.frame + clr _.frame+1 + .endm + + comment "Declare a data variable" + .macro gdbasm_datavar name value + .data +\name: + .long \value + .endm diff --git a/gdb/testsuite/gdb.asm/m68k.inc b/gdb/testsuite/gdb.asm/m68k.inc new file mode 100644 index 0000000..fadf54b --- /dev/null +++ b/gdb/testsuite/gdb.asm/m68k.inc @@ -0,0 +1,38 @@ + comment "subroutine prologue" + .macro gdbasm_enter + link %a6,#0 + .endm + + comment "subroutine epilogue" + .macro gdbasm_leave + unlk %a6 + rts + .endm + + .macro gdbasm_call subr + jbsr \subr + .endm + + .macro gdbasm_several_nops + nop + nop + nop + nop + .endm + + comment "exit (0)" + .macro gdbasm_exit0 + illegal + .endm + + comment "crt0 startup" + .macro gdbasm_startup + lea 0,%a6 + .endm + + comment "Declare a data variable" + .macro gdbasm_datavar name value + .data +\name: + .long \value + .endm diff --git a/gdb/testsuite/gdb.asm/netbsd.inc b/gdb/testsuite/gdb.asm/netbsd.inc new file mode 100644 index 0000000..9446966 --- /dev/null +++ b/gdb/testsuite/gdb.asm/netbsd.inc @@ -0,0 +1,12 @@ + comment "netbsd .note" + +.section ".note.netbsd.ident", "a" + .p2align 2 + + .long 7 + .long 4 + .long 1 + .ascii "NetBSD\0\0" + .long 105010000 + + .p2align 2 diff --git a/gdb/testsuite/gdb.asm/s390x.inc b/gdb/testsuite/gdb.asm/s390x.inc new file mode 100644 index 0000000..4e5bf2e --- /dev/null +++ b/gdb/testsuite/gdb.asm/s390x.inc @@ -0,0 +1,68 @@ +### entry point code + .macro gdbasm_startup + + # Align the stack pointer to an 8-byte boundary. + lghi %r0,-16 + ngr %r15,%r0 + + # Reserve space for the standard stack frame: + # back chain, and space for the callee to save its registers. + aghi %r15,-168 + + # Zero this frame's back chain pointer. + xc 0(8,%r15),0(%r15) + .endm + + +### Call a function. + .macro gdbasm_call subr + brasl %r14, \subr + .endm + + +### Exit with a zero status. + .macro gdbasm_exit0 + lghi %r2, 0 + svc 1 + .endm + +### Standard subroutine prologue. + .macro gdbasm_enter + + # Save all the callee-saves registers. What the heck. + stmg %r6,%r15,48(%r15) + + # Allocate the stack frame, and write the back chain pointer. + # Keep the original SP in %r11. + lgr %r11,%r15 + aghi %r15,-168 + stg %r11,0(%r15) + .endm + + +### Standard subroutine epilogue. + .macro gdbasm_leave + + # Restore all our registers. This also pops the frame, and + # restores our return address. + lmg %r6,%r15,216(%r15) + + # Jump to the return address. + br %r14 + + .endm + +### Several nops. + .macro gdbasm_several_nops + lr %r0, %r0 + lr %r0, %r0 + lr %r0, %r0 + lr %r0, %r0 + .endm + +### Declare an `int' variable. + .macro gdbasm_datavar name value + .data +\name: + .long \value + .endm diff --git a/gdb/testsuite/gdb.asm/sh.inc b/gdb/testsuite/gdb.asm/sh.inc new file mode 100644 index 0000000..88a24c3 --- /dev/null +++ b/gdb/testsuite/gdb.asm/sh.inc @@ -0,0 +1,85 @@ +# You'll find a bunch of nop opcodes in the below macros. They are +# there to keep the code correctly aligned. Be careful to maintain +# them when changing the code. + + comment "subroutine declare" + .macro gdbasm_declare name + .align 1 + .global \name +\name: + .endm + + comment "subroutine prologue" + .macro gdbasm_enter + mov.l r14,@-r15 + sts.l pr,@-r15 + mov r15,r14 + nop + .endm + + comment "subroutine epilogue" + .macro gdbasm_leave + mov r14,r15 + lds.l @r15+,pr + mov.l @r15+,r14 + rts + nop + nop + .endm + + comment "subroutine end" + .macro gdbasm_end name + .size \name, .-_foo1 + .align 1 + .endm + + comment "subroutine call" + .macro gdbasm_call subr + mov.l .Lconst\@,r1 + bra .Lafterconst\@ + nop + nop +.Lconst\@: + .align 2 + .long \subr + .align 1 +.Lafterconst\@: + jsr @r1 + nop + .endm + + .macro gdbasm_several_nops + nop + nop + nop + nop + .endm + + comment "exit (0)" + .macro gdbasm_exit0 + sleep + nop + .endm + + comment "crt0 startup" + .macro gdbasm_startup + mov.l .stackaddr,r15 + bra .afterstackaddr + nop + nop + .align 2 +.stackaddr: + .long 196608 ! 0x30000 + .align 1 +.afterstackaddr: + .endm + + comment "Declare a data variable" + .macro gdbasm_datavar name value + .data + .align 2 + .type \name, @object + .size \name, 4 +\name: + .long \value + .endm diff --git a/gdb/testsuite/gdb.base/advance.c b/gdb/testsuite/gdb.base/advance.c new file mode 100644 index 0000000..8066dee --- /dev/null +++ b/gdb/testsuite/gdb.base/advance.c @@ -0,0 +1,50 @@ + +static int x; + +int foo (int a) +{ + int b = a + 10; + return b; +} + +int bar (int y) +{ + int z = y + 20; + return z; +} + +void func() +{ + x = x + 5; + func2 (); +} + +int func2 () +{ + x = 6; +} + +int func3 () +{ + x = 4; +} + +void marker1 () +{ +} + +int +main () +{ + int result; + int b, c; + c = 5; + b = 3; /* advance this location */ + + func (c); /* stop here after leaving current frame */ + marker1 (); /* stop here after leaving current frame */ + func3 (); /* break here */ + result = bar (b + foo (c)); + return 0; /* advance malformed */ +} + diff --git a/gdb/testsuite/gdb.base/advance.exp b/gdb/testsuite/gdb.base/advance.exp new file mode 100644 index 0000000..e5061d8 --- /dev/null +++ b/gdb/testsuite/gdb.base/advance.exp @@ -0,0 +1,95 @@ +# Copyright 2003 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +# Please email any bugs, comments, and/or additions to this file to: +# bug-gdb@prep.ai.mit.edu + +# advance.exp -- Expect script to test 'advance' in gdb + +if $tracelevel then { + strace $tracelevel +} + +set testfile advance +set srcfile ${testfile}.c +set binfile ${objdir}/${subdir}/${testfile} + +remote_exec build "rm -f ${binfile}" +if { [gdb_compile "${srcdir}/${subdir}/${srcfile}" "${binfile}" executable {debug}] != "" } { + gdb_suppress_entire_file "Testcase compile failed, so all tests in this file will automatically fail." +} + +gdb_exit +gdb_start +gdb_reinitialize_dir $srcdir/$subdir +gdb_load ${binfile} + +if ![runto_main] then { + fail "Can't run to main" + return 0 +} + +# Verify that "advance " works. (This is really just syntactic +# sugar for "tbreak ; continue".) +# +gdb_test "advance [gdb_get_line_number "advance this location"]" \ + "main .* at .*:.*b = 3.*advance this location.*" \ + "advance line number" + +# Verify that a malformed "advance" is gracefully caught. +# +gdb_test "advance [gdb_get_line_number "advance malformed"] then stop" \ + "Junk at end of arguments." "malformed advance" + +# Verify that "advance " works. +# +gdb_test "advance func" \ + "func.*at.*x = x \\+ 5." \ + "advance func" + +# Verify that "advance " when funcname is NOT called by the current +# frame, stops at the end of the current frame. +# +# gdb can legitimately stop on either the current line or the next line, +# depending on whether the machine instruction for 'call' on the current +# line has more instructions after it or not. +# +gdb_test "advance func3" \ + "(in main|).*(func \\(c\\)|marker1 \\(\\)).*stop here after leaving current frame..."\ + "advance function not called by current frame" + +# break at main again +# +gdb_test "break [gdb_get_line_number "break here"]" \ + ".*Breakpoint.* at .*" \ + "set breakpoint at call to func3" +gdb_test "continue" \ + ".*Breakpoint ${decimal}, main.*func3.*break here.*" \ + "continue to call to func3 in main" + +# Verify that "advance " when funcname is called as parameter to +# another function works. +# +gdb_test "advance foo" \ + "foo \\(a=5\\).*int b = a \\+ 10;"\ + "advance function called as param" + +# Verify that we get an error if we use 'advance' w/o argument +# +gdb_test "advance" \ + "Argument required \\(a location\\)."\ + "advance with no argument" + diff --git a/gdb/testsuite/gdb.base/annota3.c b/gdb/testsuite/gdb.base/annota3.c new file mode 100644 index 0000000..6a13ee9 --- /dev/null +++ b/gdb/testsuite/gdb.base/annota3.c @@ -0,0 +1,51 @@ +#include +#include + +#ifdef __sh__ +#define signal(a,b) /* Signals not supported on this target - make them go away */ +#endif + + +#ifdef PROTOTYPES +void +handle_USR1 (int sig) +{ +} +#else +void +handle_USR1 (sig) + int sig; +{ +} +#endif + +int value; + +#ifdef PROTOTYPES +int +main (void) +#else +int +main () +#endif +{ + int my_array[3] = { 1, 2, 3 }; + + value = 7; + +#ifdef SIGUSR1 + signal (SIGUSR1, handle_USR1); +#endif + + printf ("value is %d\n", value); + printf ("my_array[2] is %d\n", my_array[2]); + + { + int i; + for (i = 0; i < 5; i++) + value++; + } + + return 0; +} + diff --git a/gdb/testsuite/gdb.base/annota3.exp b/gdb/testsuite/gdb.base/annota3.exp new file mode 100644 index 0000000..93086ef --- /dev/null +++ b/gdb/testsuite/gdb.base/annota3.exp @@ -0,0 +1,408 @@ +# Copyright 2003 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# Please email any bugs, comments, and/or additions to this file to: +# bug-gdb@prep.ai.mit.edu + +# This file was written by Elena Zannoni (ezannoni@cygnus.com) + +if $tracelevel then { + strace $tracelevel +} + + +# are we on a target board? If so, don't run these tests. +# note: this is necessary because we cannot use runto_main (which would +# work for remote targets too) because of the different prompt we get +# when using annotation level 2. +# +if [is_remote target] then { + return 0 +} + + +# +# test running programs +# +set prms_id 0 +set bug_id 0 + +set testfile "annota3" +set srcfile ${testfile}.c +set binfile ${objdir}/${subdir}/${testfile} + +if { [gdb_compile "${srcdir}/${subdir}/${srcfile}" "${binfile}" executable {debug additional_flags=-w}] != "" } { + gdb_suppress_entire_file "Testcase compile failed, so all tests in this file will automatically fail." +} + + +gdb_exit +gdb_start +gdb_reinitialize_dir $srcdir/$subdir +gdb_load ${binfile} + +if [target_info exists gdb_stub] { + gdb_step_for_stub; +} + +# +# the line at which break main will put the breakpoint +# +set main_line 32 + +# The commands we test here produce many lines of output; disable "press +# to continue" prompts. +send_gdb "set height 0\n" +gdb_expect -re "$gdb_prompt $" + +# +# break at main +# +gdb_test "break main" \ + "Breakpoint.*at.* file .*$srcfile, line.*" \ + "breakpoint main" + + +# NOTE: this prompt is OK only when the annotation level is > 1 + +# NOTE: When this prompt is in use the gdb_test procedure cannot be +# used because it assumes that the last char after the gdb_prompt is a +# white space. This is not true with this annotated prompt. So we must +# use send_gdb and gdb_expect or gdb_expect_list. + +set old_gdb_prompt $gdb_prompt +set gdb_prompt "\r\n\032\032pre-prompt\r\n$gdb_prompt \r\n\032\032prompt\r\n" + + + +# +# set the annotation level to 3 +# +# of course, this will test: +# annotate-pre-prompt +# annotate-prompt +# annotate-post-prompt (in the next block) +# +send_gdb "set annotate 3\n" +gdb_expect_list "annotation set at level 3" "\r\n$gdb_prompt$" { + "set annotate 3" +} + + +# +# info break: +# +send_gdb "info break\n" +gdb_expect_list "breakpoint info" "$gdb_prompt$" { + "\r\n\032\032post-prompt\r\n" + "Num Type Disp Enb Address +What\r\n" + "1 breakpoint keep y 0x\[0-9a-zA-Z\]+ +in main at .*annota3.c:32\r\n" +} + + +# +# run to a break point will test: +# +#exp_internal 1 +send_gdb "run\n" +gdb_expect_list "run until main breakpoint" "$gdb_prompt$" { + "\r\n\032\032post-prompt\r\n" + "Starting program: .*annota3 \r\n" + "\(\r\n\032\032\(frames-invalid|breakpoints-invalid\)\r\n\)+" + "\r\n\032\032starting\r\n" + "\(\r\n\032\032\(frames-invalid|breakpoints-invalid\)\r\n\)+" + "\r\n\032\032breakpoint 1\r\n" + "\r\n" + "Breakpoint 1, main \\(\\) at .*annota3.c:32\r\n" + "\r\n\032\032source.*annota3.c:32:.*:beg:0x\[0-9a-z\]+\r\n" + "\r\n\032\032stopped\r\n" +} +#exp_internal 0 +#exit 0 + +# +# Let's do a next, to get to a point where the array is initialized +# We don't care about the annotated output for this operation, it is the same as +# the one produced by run above +# +send_gdb "next\n" +gdb_expect_list "go after array init line" "$gdb_prompt$" { + "\r\n\032\032post-prompt\r\n" + "\r\n\032\032starting\r\n" + "\(\r\n\032\032frames-invalid\r\n\)+" + "\r\n\032\032source .*annota3.c:\[0-9\]+:\[0-9\]+:beg:0x\[0-9a-z\]+\r\n" + "\r\n\032\032stopped\r\n" +} + + +# +# printing the array: +# +send_gdb "print my_array\n" +gdb_expect_list "print array" "$gdb_prompt$" { + "\r\n\032\032post-prompt\r\n" + ".*= .1, 2, 3.\r\n" +} + + +# +# this should generate an error message, so to test: +# annotate-error-begin +# FIXME: annotate-error not tested +# + +#exp_internal 1 +send_gdb "print non_existent_value\n" +gdb_expect_list "print non_existent_value" "$gdb_prompt$" { + "\r\n\032\032post-prompt\r\n" + "\r\n\032\032error-begin\r\n" + "No symbol \"non_existent_value\" in current context.\r\n" + "\r\n\032\032error\r\n" +} + + +# +# break at signal handler +# +send_gdb "break handle_USR1\n" +gdb_expect_list "breakpoint handle_USR1" "$gdb_prompt$" { + "\r\n\032\032post-prompt\r\n" + "\r\n\032\032breakpoints-invalid\r\n" + "Breakpoint.*at 0x\[0-9a-z\]+: file.*annota3.c, line.*\r\n" +} + +# +# break at printf. When we are stopped at printf, we can test +# +send_gdb "break printf\n" +gdb_expect_list "breakpoint printf" "$gdb_prompt$" { + "\r\n\032\032post-prompt\r\n" + "\r\n\032\032breakpoints-invalid\r\n" + "Breakpoint.*at 0x\[0-9a-z\]+.*" +} + +# +# get to printf +# +send_gdb "continue\n" +gdb_expect_list "continue to printf" "$gdb_prompt$" { + "\r\n\032\032post-prompt\r\n" + "Continuing.\r\n" + "\r\n\032\032starting\r\n" + "\r\n\032\032frames-invalid\r\n" + "\r\n\032\032breakpoint 3\r\n" + "\r\n" + "Breakpoint 3, \[^\r\n\]*\r\n" + "\r\n\032\032stopped\r\n" +} + +send_gdb "backtrace\n" +gdb_expect_list "backtrace from shlibrary" "$gdb_prompt$" { + "\r\n\032\032post-prompt\r\n" + "#0 .* printf \[^\r\n\]*\r\n" + "#1 .* main \[^\r\n\]*\r\n" +} + + +# +# test printing a frame with some arguments: +# +send_gdb "signal SIGUSR1\n" +gdb_expect_list "send SIGUSR1" "$gdb_prompt$" { + "\r\n\032\032post-prompt\r\n" + "Continuing with signal SIGUSR1.\r\n" + "\r\n\032\032starting\r\n" + "\r\n\032\032frames-invalid\r\n" + "\r\n\032\032breakpoint 2\r\n" + "Breakpoint 2, handle_USR1 \\(sig=\[0-9\]+\\) at .*annota3.c:\[0-9\]+\r\n" + "\r\n\032\032source .*annota3.c:\[0-9\]+:\[0-9\]+:beg:0x\[0-9a-z\]+\r\n" + "\r\n\032\032stopped\r\n" +} + + +# +# test: +# +verbose "match_max local is: [match_max]" +verbose "match_max default is: [match_max -d]" +# This is necessary because a 2000 buffer is not enought to get everything +# up to the prompt ad the test gets a timeout. +match_max 3000 +verbose "match_max now is: [match_max]" +send_gdb "backtrace\n" +gdb_expect_list "backtrace @ signal handler" "$gdb_prompt$" { + "#0 +handle_USR1 \[^\r\n\]+\r\n" + "#1 +.signal handler called.\r\n" + "#2 .* printf \[^\r\n\]+\r\n" + "#3 .* main \[^\r\n\]+\r\n" +} + +# +# delete all the breakpoints +# +send_gdb "delete 1\n" +gdb_expect_list "delete bp 1" "$gdb_prompt$" { + "\r\n\032\032post-prompt\r\n" +} + +send_gdb "delete 2\n" +gdb_expect_list "delete bp 2" "$gdb_prompt$" { + "\r\n\032\032post-prompt\r\n" +} + +send_gdb "delete 3\n" +gdb_expect_list "delete bp 3" "$gdb_prompt$" { + "\r\n\032\032post-prompt\r\n" +} + +# +# break at main, after value is initialized. This is in preparation +# to test the annotate output for the display command. +# +send_gdb "break main\n" +gdb_expect_list "break at 28" "$gdb_prompt$" { + "\r\n\032\032post-prompt\r\n" + "\r\n\032\032breakpoints-invalid\r\n" + "Breakpoint 4 at 0x\[0-9a-z\]+: file .*annota3.c, line 32.\r\n" +} + +# +# display the value +# +send_gdb "display value\n" +gdb_expect_list "set up display" "$gdb_prompt$" { + "\r\n\032\032post-prompt\r\n" + "1: value = 7\r\n" +} + + +# should ask query. Test annotate-query. +# we don't care about anything else here, only the query. + +send_gdb "run\n" +gdb_expect { + -re "pre-query.*already.*\\(y or n\\).*query\r\n" { + send_gdb "y\n" + gdb_expect { + -re ".*post-query.*$gdb_prompt$" \ + { pass "re-run" } + -re ".*$gdb_prompt$" { fail "re-run" } + timeout { fail "re-run (timeout)" } + } + } + -re ".*$gdb_prompt$" { fail "re-run" } + timeout { fail "re-run (timeout)" } +} + +# +# Test that breakpoints-invalid is issued once and only once for +# breakpoint ignore count changes, after annotation stopped. +# +send_gdb "break 46\n" +gdb_expect_list "break at 46" "$gdb_prompt$" { + "\r\n\032\032post-prompt\r\n" + "\r\n\032\032breakpoints-invalid\r\n" + "Breakpoint 5 at 0x\[0-9a-z\]+: file .*annota3.c, line 46.\r\n" +} + +send_gdb "ignore 5 4\n" +gdb_expect_list "ignore 5 4" "$gdb_prompt$" { + "\r\n\032\032post-prompt\r\n" + "Will ignore next 4 crossings of breakpoint 5" + "\r\n\032\032breakpoints-invalid\r\n" + "\r\n" +} + +send_gdb "continue\n" +gdb_expect_list "annotate ignore count change" "$gdb_prompt$" { + "\r\n\032\032post-prompt\r\n" + "\(\r\n\032\032frames-invalid\r\n\)+" + "\r\n\032\032breakpoint 5\r\n" + "Breakpoint 5, main \\(\\) at .*annota3.c:46\r\n" + "\r\n\032\032source .*annota3.c:46:\[0-9\]+:beg:0x\[0-9a-z\]+\r\n" + "1: value = 11\r\n" + "\r\n\032\032stopped\r\n" + "\r\n\032\032breakpoints-invalid\r\n" +} + +# check that ignore command is working, or the above can provide +# misleading assurance ... + +send_gdb "next\n" +gdb_expect_list "next to exit loop" "$gdb_prompt$" { + "\r\n\032\032post-prompt\r\n" + "\r\n\032\032starting\r\n" + "\(\r\n\032\032frames-invalid\r\n\)+" + "\r\n\032\032source.*annota3.c:\[0-9\]+:\[0-9\]+:beg:0x\[0-9a-z\]+\r\n" + "1: value = 12\r\n" + "\r\n\032\032stopped\r\n" +} + +send_gdb "next\n" +gdb_expect_list "breakpoint ignore count" "$gdb_prompt$" { + "\r\n\032\032post-prompt\r\n" + "\r\n\032\032starting\r\n" + "\(\r\n\032\032frames-invalid\r\n\)+" + "\r\n\032\032source.*annota3.c:49:\[0-9\]+:beg:0x\[0-9a-z\]+\r\n" + "1: value = 12\r\n" + "\r\n\032\032stopped\r\n" +} + +# +# Send a signal that is not handled +# +# SIGTRAP signals are dropped before they get to the inferior process +# on hpux11. In theory, this behaivor can be controlled by setting +# TTEO_NORM_SIGTRAP in the inferior, but doing so did not cause +# the signal to be properly delivered. +# +# It has been verified that other signals will be delivered. However, +# rather than twiddle the test, I choose to leave it as-is as it +# exposes an interesting failure on hpux11. +setup_xfail hppa*-*-hpux11* +send_gdb "signal SIGTRAP\n" +gdb_expect_list "signal sent" "$gdb_prompt$" { + "\r\n\032\032post-prompt\r\n" + "Continuing with signal SIGTRAP.\r\n" + "\r\n\032\032starting\r\n" + "\r\n\032\032frames-invalid\r\n" + "\r\n\032\032frames-invalid\r\n" + "\r\n\032\032signalled\r\n" + "\r\nProgram terminated with signal SIGTRAP, Trace.breakpoint trap.\r\n" + "The program no longer exists.\r\n" + "\r\n\032\032stopped\r\n" +} + + +# Check for production of a core file +# and remove it! + +set exec_output [remote_exec build "ls core"] + +if [ regexp "core not found" $exec_output] { + pass "No core dumped" +} else { + if [ regexp "No such file or directory" $exec_output] { + pass "No core dumped" + } else { + remote_exec build "rm -f core" + pass "Core dumped and removed" + } +} + +# restore the original prompt for the rest of the testsuite + +set gdb_prompt $old_gdb_prompt diff --git a/gdb/testsuite/gdb.base/args.c b/gdb/testsuite/gdb.base/args.c new file mode 100644 index 0000000..d564120 --- /dev/null +++ b/gdb/testsuite/gdb.base/args.c @@ -0,0 +1,12 @@ +#include + +int +main (int argc, char **argv) +{ + int i = 0; + printf ("%d\n", argc); + while (i < argc) + printf ("%s\n", argv[i++]); + + return 0; +} diff --git a/gdb/testsuite/gdb.base/args.exp b/gdb/testsuite/gdb.base/args.exp new file mode 100644 index 0000000..4f50ef0 --- /dev/null +++ b/gdb/testsuite/gdb.base/args.exp @@ -0,0 +1,89 @@ +# Copyright 2003 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# Please email any bugs, comments, and/or additions to this file to: +# bug-gdb@prep.ai.mit.edu + +# This is a test for the gdb invocation option --args. + +if $tracelevel then { + strace $tracelevel +} + + +global GDBFLAGS + +# Skip test if target does not support argument passing. +if [target_info exists noargs] { + return; +} + +# No loading needs to be done when the target is `exec'. Some targets +# require that the program be loaded, however. +proc args_load {} { + global binfile + if [target_info exists is_simulator] { + gdb_load ${binfile} + } +} + +set testfile "args" +set srcfile ${testfile}.c +set binfile ${objdir}/${subdir}/${testfile} + +if { [gdb_compile "${srcdir}/${subdir}/${srcfile}" "${binfile}" executable {debug additional_flags=-w}] != "" } { + gdb_suppress_entire_file "Testcase compile failed, so all tests in this file will automatically fail." +} + +# +# Test that the --args are processed correctly. +# +set old_gdbflags $GDBFLAGS +set GDBFLAGS "--args $binfile 1 3" +gdb_exit +gdb_start +gdb_reinitialize_dir $srcdir/$subdir +args_load +gdb_test "run" \ + "Starting program.*args(\\.exe)? 1 3.*3\r\n.*args\r\n1\r\n3.*Program exited normally." \ + "correct args printed" + +# +# Test that the --args are processed correctly even if one of them is empty. +# +set GDBFLAGS "--args $binfile 1 '' 3" +gdb_exit +gdb_start +gdb_reinitialize_dir $srcdir/$subdir +args_load +gdb_test "run" \ + "Starting program.*args(\\.exe)? 1 \\\\'\\\\' 3.*4\r\n.*args\r\n1\r\n''\r\n3.*Program exited normally." \ + "correct args printed, one empty" + +# +# try with 2 empty args +# +set GDBFLAGS "--args $binfile 1 '' '' 3" +gdb_exit +gdb_start +gdb_reinitialize_dir $srcdir/$subdir +args_load +gdb_test "run" \ + "Starting program.*args(\\.exe)? 1 \\\\'\\\\' \\\\'\\\\' 3.*5\r\n.*args\r\n1\r\n''\r\n''\r\n3.*Program exited normally." \ + "correct args printed, two empty" + +set GDBFLAGS $old_gdbflags + diff --git a/gdb/testsuite/gdb.base/bang.exp b/gdb/testsuite/gdb.base/bang.exp new file mode 100644 index 0000000..f584074 --- /dev/null +++ b/gdb/testsuite/gdb.base/bang.exp @@ -0,0 +1,41 @@ +# Copyright 2003 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# This is a test that verifies that GDB is able to "run" when the name +# of the executable file contains a '!'. + +if $tracelevel then { + strace $tracelevel +} + +set testfile "args" +set srcfile ${testfile}.c +set binfile ${objdir}/${subdir}/bang! + +if { [gdb_compile "${srcdir}/${subdir}/${srcfile}" "${binfile}" executable {debug additional_flags=-w}] != "" } { + gdb_suppress_entire_file "Testcase compile failed, so all tests in this file will automatically fail." +} + +gdb_exit +gdb_start +gdb_reinitialize_dir $srcdir/$subdir +gdb_load ${binfile} + +# Verify that we can run the program and that it terminates normally. +gdb_test "run" \ + ".*Program exited normally\." \ + "run program" + diff --git a/gdb/testsuite/gdb.base/break1.c b/gdb/testsuite/gdb.base/break1.c new file mode 100644 index 0000000..2ed8b2a --- /dev/null +++ b/gdb/testsuite/gdb.base/break1.c @@ -0,0 +1,44 @@ +/* This testcase is part of GDB, the GNU debugger. + + Copyright 1992, 1993, 1994, 1995, 1999, 2002, 2003 Free Software + Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + + Please email any bugs, comments, and/or additions to this file to: + bug-gdb@prep.ai.mit.edu */ + +/* The code for this file was extracted from the gdb testsuite + testcase "break.c". */ + +/* The following functions do nothing useful. They are included + simply as places to try setting breakpoints at. They are + explicitly "one-line functions" to verify that this case works + (some versions of gcc have or have had problems with this). + + These functions are in a separate source file to prevent an + optimizing compiler from inlining them and optimizing them away. */ + +#ifdef PROTOTYPES +int marker1 (void) { return (0); } /* set breakpoint 15 here */ +int marker2 (int a) { return (1); } /* set breakpoint 8 here */ +void marker3 (char *a, char *b) {} /* set breakpoint 17 here */ +void marker4 (long d) {} /* set breakpoint 14 here */ +#else +int marker1 () { return (0); } /* set breakpoint 16 here */ +int marker2 (a) int a; { return (1); } /* set breakpoint 9 here */ +void marker3 (a, b) char *a, *b; {} /* set breakpoint 18 here */ +void marker4 (d) long d; {} /* set breakpoint 13 here */ +#endif diff --git a/gdb/testsuite/gdb.base/complex.c b/gdb/testsuite/gdb.base/complex.c new file mode 100644 index 0000000..98cdd29 --- /dev/null +++ b/gdb/testsuite/gdb.base/complex.c @@ -0,0 +1,49 @@ +/* Test taken from GCC. Verify that we can print a structure containing + a complex number. */ + +typedef __complex__ float cf; +struct x { char c; cf f; } __attribute__ ((__packed__)); +struct unpacked_x { char c; cf f; }; +extern void f4 (struct unpacked_x*); +extern void f3 (void); +extern void f2 (struct x*); +extern void f1 (void); +int +main (void) +{ + f1 (); + f3 (); + exit (0); +} + +void +f1 (void) +{ + struct x s; + s.f = 1; + s.c = 42; + f2 (&s); +} + +void +f2 (struct x *y) +{ + if (y->f != 1 || y->c != 42) + abort (); +} + +void +f3 (void) +{ + struct unpacked_x s; + s.f = 1; + s.c = 42; + f4 (&s); +} + +void +f4 (struct unpacked_x *y) +{ + if (y->f != 1 || y->c != 42) + abort (); +} diff --git a/gdb/testsuite/gdb.base/complex.exp b/gdb/testsuite/gdb.base/complex.exp new file mode 100644 index 0000000..fac7f4f --- /dev/null +++ b/gdb/testsuite/gdb.base/complex.exp @@ -0,0 +1,63 @@ +# Copyright 2003 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# Please email any bugs, comments, and/or additions to this file to: +# bug-gdb@prep.ai.mit.edu + +if $tracelevel then { + strace $tracelevel +} + +set bug_id 0 + +set testfile complex +set srcfile ${testfile}.c +set binfile ${objdir}/${subdir}/${testfile} +set options debug + +if { [gdb_compile "${srcdir}/${subdir}/${srcfile}" "${binfile}" executable $options] != "" } { + # No support for __complex__, presumably. + unsupported "print complex packed value in C" + unsupported "print complex value in C" + return 0 +} + +# Start with a fresh gdb. + +if [get_compiler_info ${binfile}] { + return -1 +} + +gdb_exit +gdb_start +gdb_reinitialize_dir $srcdir/$subdir +gdb_load $binfile + +if [runto f2] then { + get_debug_format + if { [test_compiler_info gcc-2-*] && [test_debug_format "DWARF 2"] } then { + setup_xfail "*-*-*" + } + gdb_test "p *y" "\\\$\[0-9\]* = \{c = 42 '\\*', f = 1 \\+ 0 \\* I\}" \ + "print complex packed value in C" +} + +if [runto f4] then { + gdb_test "p *y" "\\\$\[0-9\]* = \{c = 42 '\\*', f = 1 \\+ 0 \\* I\}" \ + "print complex value in C" +} + +return 0 diff --git a/gdb/testsuite/gdb.base/detach.exp b/gdb/testsuite/gdb.base/detach.exp new file mode 100644 index 0000000..1f86fec --- /dev/null +++ b/gdb/testsuite/gdb.base/detach.exp @@ -0,0 +1,77 @@ +# Copyright 2003 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +# Please email any bugs, comments, and/or additions to this file to: +# bug-gdb@prep.ai.mit.edu + +# Test running a program from the GDB prompt and then detaching it. +# NOTE: This test could be much more thorough. + +if $tracelevel then { + strace $tracelevel +} + +set prms_id 0 +set bug_id 0 + +# Only GNU/Linux is known to support this. +if { ! [istarget "*-*-linux*"] } { + return 0 +} + +# Are we on a target board? +if [is_remote target] then { + return 0 +} + +set testfile "attach" +set srcfile ${testfile}.c +set binfile ${objdir}/${subdir}/${testfile} +set escapedbinfile [string_to_regexp ${objdir}/${subdir}/${testfile}] + +if { [gdb_compile "${srcdir}/${subdir}/${srcfile}" "${binfile}" executable {debug}] != "" } { + gdb_suppress_entire_file "Testcase compile failed, so all tests in this file will automatically fail." +} + +proc do_detach_tests {} { + global srcdir + global binfile + global escapedbinfile + global subdir + global pass + + runto_main + gdb_test "set should_exit = 1" "" "set should_exit, $pass" + gdb_test "detach" "Detaching from program: .*$escapedbinfile, .*" "detach, $pass" +} + +# Start with a fresh gdb +gdb_exit +gdb_start +gdb_reinitialize_dir $srcdir/$subdir +gdb_load ${binfile} + +global pass +set pass "one" +do_detach_tests + +# Wait a moment and do it again. +exec sleep 1 + +set pass "two" +do_detach_tests + +return 0 diff --git a/gdb/testsuite/gdb.base/fileio.c b/gdb/testsuite/gdb.base/fileio.c new file mode 100644 index 0000000..591b3b6 --- /dev/null +++ b/gdb/testsuite/gdb.base/fileio.c @@ -0,0 +1,503 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +/* TESTS : + * - open(const char *pathname, int flags, mode_t mode); +1) Attempt to create file that already exists - EEXIST +2) Attempt to open a directory for writing - EISDIR +3) Pathname does not exist - ENOENT +4) Open for write but no write permission - EACCES + +read(int fd, void *buf, size_t count); +1) Read using invalid file descriptor - EBADF + +write(int fd, const void *buf, size_t count); +1) Write using invalid file descriptor - EBADF +2) Attempt to write to read-only file - EBADF + +lseek(int fildes, off_t offset, int whence); +1) Seeking on an invalid file descriptor - EBADF +2) Invalid "whence" (3rd param) value - EINVAL + +close(int fd); +1) Attempt to close an invalid file descriptor - EBADF + +stat(const char *file_name, struct stat *buf); +1) Pathname is a null string - ENOENT +2) Pathname does not exist - ENOENT + +fstat(int filedes, struct stat *buf); +1) Attempt to stat using an invalid file descriptor - EBADF + +isatty (int desc); +Not applicable. We will test that it returns 1 when expected and a case +where it should return 0. + +rename(const char *oldpath, const char *newpath); +1) newpath is an existing directory, but oldpath is not a directory. - EISDIR +2) newpath is a non-empty directory. - ENOTEMPTY or EEXIST +3) newpath is a subdirectory of old path. - EINVAL +4) oldpath does not exist. - ENOENT + +unlink(const char *pathname); +1) pathname does not have write access. - EACCES +2) pathname does not exist. - ENOENT + +time(time_t *t); +Not applicable. + +system (const char * string); +1) Invalid string/command. - returns 127. */ + +static const char *strerrno (int err); + +#define FILENAME "foo.fileio.test" +#define RENAMED "bar.fileio.test" +#define NONEXISTANT "nofoo.fileio.test" +#define NOWRITE "nowrt.fileio.test" +#define TESTDIR1 "dir1.fileio.test" +#define TESTDIR2 "dir2.fileio.test" +#define TESTSUBDIR "dir1.fileio.test/subdir.fileio.test" + +#define STRING "Hello World" + +int +test_open () +{ + int ret; + + /* Test opening */ + errno = 0; + ret = open (FILENAME, O_CREAT | O_TRUNC | O_RDONLY, S_IWUSR | S_IRUSR); + printf ("open 1: ret = %d, errno = %d %s\n", ret, errno, + ret >= 0 ? "OK" : ""); + if (ret >= 0) + close (ret); + /* Creating an already existing file (created by fileio.exp) */ + errno = 0; + ret = open (FILENAME, O_CREAT | O_EXCL | O_WRONLY, S_IWUSR | S_IRUSR); + printf ("open 2: ret = %d, errno = %d %s\n", ret, errno, + strerrno (errno)); + if (ret >= 0) + close (ret); + /* Open directory (for writing) */ + errno = 0; + ret = open (".", O_WRONLY); + printf ("open 3: ret = %d, errno = %d %s\n", ret, errno, + strerrno (errno)); + if (ret >= 0) + close (ret); + /* Opening nonexistant file */ + errno = 0; + ret = open (NONEXISTANT, O_RDONLY); + printf ("open 4: ret = %d, errno = %d %s\n", ret, errno, + strerrno (errno)); + if (ret >= 0) + close (ret); + /* Open for write but no write permission */ + errno = 0; + ret = open (NOWRITE, O_CREAT | O_RDONLY, S_IRUSR | S_IWUSR); + if (ret >= 0) + { + close (ret); + errno = 0; + ret = open (NOWRITE, O_WRONLY); + printf ("open 5: ret = %d, errno = %d %s\n", ret, errno, + strerrno (errno)); + if (ret >= 0) + close (ret); + } + else + printf ("open 5: ret = %d, errno = %d\n", ret, errno); +} + +int +test_write () +{ + int fd, ret; + + /* Test writing */ + errno = 0; + fd = open (FILENAME, O_WRONLY); + if (fd >= 0) + { + errno = 0; + ret = write (fd, STRING, strlen (STRING)); + printf ("write 1: ret = %d, errno = %d %s\n", ret, errno, + ret == strlen (STRING) ? "OK" : ""); + close (fd); + } + else + printf ("write 1: ret = %d, errno = %d\n", ret, errno); + /* Write using invalid file descriptor */ + errno = 0; + ret = write (999, STRING, strlen (STRING)); + printf ("write 2: ret = %d, errno = %d, %s\n", ret, errno, + strerrno (errno)); + /* Write to a read-only file */ + errno = 0; + fd = open (FILENAME, O_RDONLY); + if (fd >= 0) + { + errno = 0; + ret = write (fd, STRING, strlen (STRING)); + printf ("write 3: ret = %d, errno = %d %s\n", ret, errno, + strerrno (errno)); + } + else + printf ("write 3: ret = %d, errno = %d\n", ret, errno); +} + +int +test_read () +{ + int fd, ret; + char buf[16]; + + /* Test reading */ + errno = 0; + fd = open (FILENAME, O_RDONLY); + if (fd >= 0) + { + memset (buf, 0, 16); + errno = 0; + ret = read (fd, buf, 16); + buf[15] = '\0'; /* Don't trust anybody... */ + if (ret == strlen (STRING)) + printf ("read 1: %s %s\n", buf, !strcmp (buf, STRING) ? "OK" : ""); + else + printf ("read 1: ret = %d, errno = %d\n", ret, errno); + close (fd); + } + else + printf ("read 1: ret = %d, errno = %d\n", ret, errno); + /* Read using invalid file descriptor */ + errno = 0; + ret = read (999, buf, 16); + printf ("read 2: ret = %d, errno = %d %s\n", ret, errno, + strerrno (errno)); +} + +int +test_lseek () +{ + int fd; + off_t ret = 0; + + /* Test seeking */ + errno = 0; + fd = open (FILENAME, O_RDONLY); + if (fd >= 0) + { + errno = 0; + ret = lseek (fd, 0, SEEK_CUR); + printf ("lseek 1: ret = %ld, errno = %d, %s\n", (long) ret, errno, + ret == 0 ? "OK" : ""); + errno = 0; + ret = lseek (fd, 0, SEEK_END); + printf ("lseek 2: ret = %ld, errno = %d, %s\n", (long) ret, errno, + ret == 11 ? "OK" : ""); + errno = 0; + ret = lseek (fd, 3, SEEK_SET); + printf ("lseek 3: ret = %ld, errno = %d, %s\n", (long) ret, errno, + ret == 3 ? "OK" : ""); + close (fd); + } + else + { + printf ("lseek 1: ret = %d, errno = %d\n", ret, errno); + printf ("lseek 2: ret = %d, errno = %d\n", ret, errno); + printf ("lseek 3: ret = %d, errno = %d\n", ret, errno); + } + /* Seeking on an invalid file descriptor */ + +} + +int +test_close () +{ + int fd, ret; + + /* Test close */ + errno = 0; + fd = open (FILENAME, O_RDONLY); + if (fd >= 0) + { + errno = 0; + ret = close (fd); + printf ("close 1: ret = %d, errno = %d, %s\n", ret, errno, + ret == 0 ? "OK" : ""); + } + else + printf ("close 1: ret = %d, errno = %d\n", ret, errno); + /* Close an invalid file descriptor */ + errno = 0; + ret = close (999); + printf ("close 2: ret = %d, errno = %d, %s\n", ret, errno, + strerrno (errno)); +} + +int +test_stat () +{ + int ret; + struct stat st; + + /* Test stat */ + errno = 0; + ret = stat (FILENAME, &st); + if (!ret) + printf ("stat 1: ret = %d, errno = %d %s\n", ret, errno, + st.st_size == 11 ? "OK" : ""); + else + printf ("stat 1: ret = %d, errno = %d\n", ret, errno); + /* NULL pathname */ + errno = 0; + ret = stat (NULL, &st); + printf ("stat 2: ret = %d, errno = %d %s\n", ret, errno, + strerrno (errno)); + /* Empty pathname */ + errno = 0; + ret = stat ("", &st); + printf ("stat 3: ret = %d, errno = %d %s\n", ret, errno, + strerrno (errno)); + /* Nonexistant file */ + errno = 0; + ret = stat (NONEXISTANT, &st); + printf ("stat 4: ret = %d, errno = %d %s\n", ret, errno, + strerrno (errno)); +} + +int +test_fstat () +{ + int fd, ret; + struct stat st; + + /* Test fstat */ + errno = 0; + fd = open (FILENAME, O_RDONLY); + if (fd >= 0) + { + errno = 0; + ret = fstat (fd, &st); + if (!ret) + printf ("fstat 1: ret = %d, errno = %d %s\n", ret, errno, + st.st_size == 11 ? "OK" : ""); + else + printf ("fstat 1: ret = %d, errno = %d\n", ret, errno); + close (fd); + } + else + printf ("fstat 1: ret = %d, errno = %d\n", ret, errno); + /* Fstat using invalid file descriptor */ + errno = 0; + ret = fstat (999, &st); + printf ("fstat 2: ret = %d, errno = %d %s\n", ret, errno, + strerrno (errno)); +} + +int +test_isatty () +{ + int fd; + + /* Check std I/O */ + printf ("isatty 1: stdin %s\n", isatty (0) ? "yes OK" : "no"); + printf ("isatty 2: stdout %s\n", isatty (1) ? "yes OK" : "no"); + printf ("isatty 3: stderr %s\n", isatty (2) ? "yes OK" : "no"); + /* Check invalid fd */ + printf ("isatty 4: invalid %s\n", isatty (999) ? "yes" : "no OK"); + /* Check open file */ + fd = open (FILENAME, O_RDONLY); + if (fd >= 0) + { + printf ("isatty 5: file %s\n", isatty (fd) ? "yes" : "no OK"); + close (fd); + } + else + printf ("isatty 5: file couldn't open\n"); +} + + +int +test_system () +{ + /* + * Requires test framework to switch on "set remote system-call-allowed 1" + */ + int ret; + char sys[512]; + + /* This test prepares the directory for test_rename() */ + sprintf (sys, "mkdir -p %s %s", TESTSUBDIR, TESTDIR2); + ret = system (sys); + if (ret == 127) + printf ("system 1: ret = %d /bin/sh unavailable???\n", ret); + else + printf ("system 1: ret = %d %s\n", ret, ret == 0 ? "OK" : ""); + /* Invalid command (just guessing ;-) ) */ + ret = system ("wrtzlpfrmpft"); + printf ("system 2: ret = %d %s\n", ret, WEXITSTATUS (ret) == 127 ? "OK" : ""); +} + +int +test_rename () +{ + int ret; + struct stat st; + + /* Test rename */ + errno = 0; + ret = rename (FILENAME, RENAMED); + if (!ret) + { + errno = 0; + ret = stat (FILENAME, &st); + if (ret && errno == ENOENT) + { + errno = 0; + ret = stat (RENAMED, &st); + printf ("rename 1: ret = %d, errno = %d %s\n", ret, errno, + strerrno (errno)); + errno = 0; + } + else + printf ("rename 1: ret = %d, errno = %d\n", ret, errno); + } + else + printf ("rename 1: ret = %d, errno = %d\n", ret, errno); + /* newpath is existing directory, oldpath is not a directory */ + errno = 0; + ret = rename (RENAMED, TESTDIR2); + printf ("rename 2: ret = %d, errno = %d %s\n", ret, errno, + strerrno (errno)); + /* newpath is a non-empty directory */ + errno = 0; + ret = rename (TESTDIR2, TESTDIR1); + printf ("rename 3: ret = %d, errno = %d %s\n", ret, errno, + strerrno (errno)); + /* newpath is a subdirectory of old path */ + errno = 0; + ret = rename (TESTDIR1, TESTSUBDIR); + printf ("rename 4: ret = %d, errno = %d %s\n", ret, errno, + strerrno (errno)); + /* oldpath does not exist */ + errno = 0; + ret = rename (NONEXISTANT, FILENAME); + printf ("rename 5: ret = %d, errno = %d %s\n", ret, errno, + strerrno (errno)); +} + +int +test_unlink () +{ + int ret; + char name[256]; + char sys[512]; + + /* Test unlink */ + errno = 0; + ret = unlink (RENAMED); + printf ("unlink 1: ret = %d, errno = %d %s\n", ret, errno, + strerrno (errno)); + /* No write access */ + sprintf (name, "%s/%s", TESTDIR2, FILENAME); + errno = 0; + ret = open (name, O_CREAT | O_RDONLY, S_IRUSR | S_IWUSR); + if (ret >= 0) + { + sprintf (sys, "chmod -w %s", TESTDIR2); + ret = system (sys); + if (!ret) + { + errno = 0; + ret = unlink (name); + printf ("unlink 2: ret = %d, errno = %d %s\n", ret, errno, + strerrno (errno)); + } + else + printf ("unlink 2: ret = %d chmod failed\n", ret, errno); + } + else + printf ("unlink 2: ret = %d, errno = %d\n", ret, errno); + /* pathname doesn't exist */ + errno = 0; + ret = unlink (NONEXISTANT); + printf ("unlink 3: ret = %d, errno = %d %s\n", ret, errno, + strerrno (errno)); +} + +int +test_time () +{ + time_t ret, t; + + errno = 0; + ret = time (&t); + printf ("time 1: ret = %ld, errno = %d, t = %ld %s\n", (long) ret, errno, (long) t, ret == t ? "OK" : ""); + errno = 0; + ret = time (NULL); + printf ("time 2: ret = %ld, errno = %d, t = %ld %s\n", + (long) ret, errno, (long) t, ret >= t && ret < t + 10 ? "OK" : ""); +} + +static const char * +strerrno (int err) +{ + switch (err) + { + case 0: return "OK"; +#ifdef EACCES + case EACCES: return "EACCES"; +#endif +#ifdef EBADF + case EBADF: return "EBADF"; +#endif +#ifdef EEXIST + case EEXIST: return "EEXIST"; +#endif +#ifdef EFAULT + case EFAULT: return "EFAULT"; +#endif +#ifdef EINVAL + case EINVAL: return "EINVAL"; +#endif +#ifdef EISDIR + case EISDIR: return "EISDIR"; +#endif +#ifdef ENOENT + case ENOENT: return "ENOENT"; +#endif +#ifdef ENOTEMPTY + case ENOTEMPTY: return "ENOTEMPTY"; +#endif + default: return "E??"; + } +} + +int +main () +{ + /* Don't change the order of the calls. They partly depend on each other */ + test_open (); + test_write (); + test_read (); + test_lseek (); + test_close (); + test_stat (); + test_fstat (); + test_isatty (); + test_system (); + test_rename (); + test_unlink (); + test_time (); + return 0; +} diff --git a/gdb/testsuite/gdb.base/fileio.exp b/gdb/testsuite/gdb.base/fileio.exp new file mode 100644 index 0000000..128cbb6 --- /dev/null +++ b/gdb/testsuite/gdb.base/fileio.exp @@ -0,0 +1,271 @@ +# Copyright 2002, 2003 +# Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# Please email any bugs, comments, and/or additions to this file to: +# bug-gdb@prep.ai.mit.edu + +# This file was written by Corinna Vinschen + +if [target_info exists gdb,nofileio] { + verbose "Skipping fileio.exp because of no fileio capabilities." + continue +} + +if $tracelevel then { + strace $tracelevel +} + +set prms_id 0 +set bug_id 0 + +set testfile "fileio" +set srcfile ${testfile}.c +set binfile ${objdir}/${subdir}/${testfile} + +if { [gdb_compile "${srcdir}/${subdir}/${srcfile}" "${binfile}" executable {debug}] != "" } { + gdb_suppress_entire_file "Testcase compile failed, so all tests in this file will automatically fail." +} + +# Create and source the file that provides information about the compiler +# used to compile the test case. + +if [get_compiler_info ${binfile}] { + return -1; +} + +remote_exec build {sh -xc test\ -r\ dir2.fileio.test\ &&\ chmod\ -f\ +w\ dir2.fileio.test} +remote_exec build {sh -xc rm\ -rf\ *.fileio.test} + +set oldtimeout $timeout +set timeout [expr "$timeout + 60"] + +# Start with a fresh gdb. + +gdb_exit +gdb_start +gdb_reinitialize_dir $srcdir/$subdir +gdb_load ${binfile} +send_gdb "set print sevenbit-strings\n" ; gdb_expect -re "$gdb_prompt $" +send_gdb "set print address off\n" ; gdb_expect -re "$gdb_prompt $" +send_gdb "set width 0\n" ; gdb_expect -re "$gdb_prompt $" + + +if ![runto_main] then { + perror "couldn't run to breakpoint" + continue +} + +send_gdb "tbreak 81\n" ; gdb_expect -re "$gdb_prompt $" +gdb_test continue \ +"Continuing\\..*open 1:.*OK.*test_open \\(\\) at.*$srcfile:81.*" \ +"Open a file" + +send_gdb "tbreak 88\n" ; gdb_expect -re "$gdb_prompt $" +gdb_test continue \ +"Continuing\\..*open 2:.*EEXIST.*test_open \\(\\) at.*$srcfile:88.*" \ +"Creating already existing file returns EEXIST" + +send_gdb "tbreak 95\n" ; gdb_expect -re "$gdb_prompt $" +gdb_test continue \ +"Continuing\\..*open 3:.*EISDIR.*test_open \\(\\) at.*$srcfile:95.*" \ +"Open directory for writing returns EISDIR" + +send_gdb "tbreak 102\n" ; gdb_expect -re "$gdb_prompt $" +gdb_test continue \ +"Continuing\\..*open 4:.*ENOENT.*test_open \\(\\) at.*$srcfile:102.*" \ +"Opening nonexistant file returns ENOENT" + +send_gdb "tbreak 109\n" ; gdb_expect -re "$gdb_prompt $" +send_gdb "continue\n" ; gdb_expect -re "$gdb_prompt $" +catch "system \"chmod -f -w nowrt.fileio.test\"" + +send_gdb "tbreak 119\n" ; gdb_expect -re "$gdb_prompt $" +gdb_test continue \ +"Continuing\\..*open 5:.*EACCES.*test_open \\(\\) at.*$srcfile:119.*" \ +"Open for write but no write permission returns EACCES" + +send_gdb "tbreak 140\n" ; gdb_expect -re "$gdb_prompt $" +gdb_test continue \ +"Continuing\\..*write 1:.*OK.*test_write \\(\\) at.*$srcfile:140.*" \ +"Writing to a file" + +send_gdb "tbreak 145\n" ; gdb_expect -re "$gdb_prompt $" +gdb_test continue \ +"Continuing\\..*write 2:.*EBADF.*test_write \\(\\) at.*$srcfile:145.*" \ +"Write using invalid file descriptor returns EBADF" + +send_gdb "tbreak 156\n" ; gdb_expect -re "$gdb_prompt $" +gdb_test continue \ +"Continuing\\..*write 3:.*EBADF.*test_write \\(\\) at.*$srcfile:156.*" \ +"Writing to a read-only file returns EBADF" + +send_gdb "tbreak 182\n" ; gdb_expect -re "$gdb_prompt $" +gdb_test continue \ +"Continuing\\..*read 1:.*OK.*test_read \\(\\) at.*$srcfile:182.*" \ +"Reading from a file" + +send_gdb "tbreak 186\n" ; gdb_expect -re "$gdb_prompt $" +gdb_test continue \ +"Continuing\\..*read 2:.*EBADF.*test_read \\(\\) at.*$srcfile:186.*" \ +"Read using invalid file descriptor returns EBADF" + +send_gdb "tbreak 221\n" ; gdb_expect -re "$gdb_prompt $" +gdb_test continue \ +"Continuing\\..*lseek 1:.*OK.*lseek 2:.*OK.*lseek 3:.*OK.*test_lseek \\(\\) at.*$srcfile:221.*" \ +"Lseeking a file" + +send_gdb "tbreak 241\n" ; gdb_expect -re "$gdb_prompt $" +gdb_test continue \ +"Continuing\\..*close 1:.*OK.*test_close \\(\\) at.*$srcfile:241.*" \ +"Closing a file" + +send_gdb "tbreak 245\n" ; gdb_expect -re "$gdb_prompt $" +gdb_test continue \ +"Continuing\\..*close 2:.*EBADF.*test_close \\(\\) at.*$srcfile:245.*" \ +"Closing an invalid file descriptor returns EBADF" + +send_gdb "tbreak 262\n" ; gdb_expect -re "$gdb_prompt $" +gdb_test continue \ +"Continuing\\..*stat 1:.*OK.*test_stat \\(\\) at.*$srcfile:262.*" \ +"Stat a file" + +send_gdb "tbreak 267\n" ; gdb_expect -re "$gdb_prompt $" +gdb_test continue \ + "Continuing\\..*stat 2:.*(ENOENT|EFAULT).*test_stat \\(\\) at.*$srcfile:267.*" \ +"Stat a NULL pathname returns ENOENT or EFAULT" + +send_gdb "tbreak 272\n" ; gdb_expect -re "$gdb_prompt $" +gdb_test continue \ +"Continuing\\..*stat 3:.*ENOENT.*test_stat \\(\\) at.*$srcfile:272.*" \ +"Stat an empty pathname returns ENOENT" + +send_gdb "tbreak 276\n" ; gdb_expect -re "$gdb_prompt $" +gdb_test continue \ +"Continuing\\..*stat 4:.*ENOENT.*test_stat \\(\\) at.*$srcfile:276.*" \ +"Stat a nonexistant file returns ENOENT" + +send_gdb "tbreak 301\n" ; gdb_expect -re "$gdb_prompt $" +gdb_test continue \ +"Continuing\\..*fstat 1:.*OK.*test_fstat \\(\\) at.*$srcfile:301.*" \ +"Fstat an open file" + +send_gdb "tbreak 305\n" ; gdb_expect -re "$gdb_prompt $" +gdb_test continue \ +"Continuing\\..*fstat 2:.*EBADF.*test_fstat \\(\\) at.*$srcfile:305.*" \ +"Fstat an invalid file descriptor returns EBADF" + +send_gdb "tbreak 314\n" ; gdb_expect -re "$gdb_prompt $" +gdb_test continue \ +"Continuing\\..*isatty 1:.*OK.*test_isatty \\(\\) at.*$srcfile:314.*" \ +"Isatty (stdin)" + +send_gdb "tbreak 315\n" ; gdb_expect -re "$gdb_prompt $" +gdb_test continue \ +"Continuing\\..*isatty 2:.*OK.*test_isatty \\(\\) at.*$srcfile:315.*" \ +"Isatty (stdout)" + +send_gdb "tbreak 317\n" ; gdb_expect -re "$gdb_prompt $" +gdb_test continue \ +"Continuing\\..*isatty 3:.*OK.*test_isatty \\(\\) at.*$srcfile:317.*" \ +"Isatty (stderr)" + +send_gdb "tbreak 319\n" ; gdb_expect -re "$gdb_prompt $" +gdb_test continue \ +"Continuing\\..*isatty 4:.*OK.*test_isatty \\(\\) at.*$srcfile:319.*" \ +"Isatty (invalid fd)" + +send_gdb "tbreak 327\n" ; gdb_expect -re "$gdb_prompt $" +gdb_test continue \ +"Continuing\\..*isatty 5:.*OK.*test_isatty \\(\\) at.*$srcfile:327.*" \ +"Isatty (open file)" + +send_gdb "set remote system-call-allowed 1\n"; gdb_expect -re ".*$gdb_prompt $" +send_gdb "tbreak 347\n" ; gdb_expect -re "$gdb_prompt $" +gdb_test continue \ +"Continuing\\..*system 1:.*OK.*test_system \\(\\) at.*$srcfile:347.*" \ +"System(3) call" + +# Is this ok? POSIX says system returns a waitpid status? +send_gdb "tbreak 349\n" ; gdb_expect -re "$gdb_prompt $" +gdb_test continue \ +"Continuing\\..*system 2:.*OK.*test_system \\(\\) at.*$srcfile:349.*" \ +"System with invalid command returns 127" + +send_gdb "tbreak 378\n" ; gdb_expect -re "$gdb_prompt $" +gdb_test continue \ +"Continuing\\..*rename 1:.*OK.*test_rename \\(\\) at.*$srcfile:378.*" \ +"Rename a file" + +send_gdb "tbreak 383\n" ; gdb_expect -re "$gdb_prompt $" +gdb_test continue \ +"Continuing\\..*rename 2:.*EISDIR.*test_rename \\(\\) at.*$srcfile:383.*" \ +"Renaming a file to existing directory returns EISDIR" + +send_gdb "tbreak 388\n" ; gdb_expect -re "$gdb_prompt $" +gdb_test continue \ + "Continuing\\..*rename 3:.*(ENOTEMPTY|EEXIST).*test_rename \\(\\) at.*$srcfile:388.*" \ +"Renaming a directory to a non-empty directory returns ENOTEMPTY or EEXIST" + +send_gdb "tbreak 393\n" ; gdb_expect -re "$gdb_prompt $" +gdb_test continue \ +"Continuing\\..*rename 4:.*EINVAL.*test_rename \\(\\) at.*$srcfile:393.*" \ +"Renaming a directory to a subdir of itself returns EINVAL" + +send_gdb "tbreak 397\n" ; gdb_expect -re "$gdb_prompt $" +gdb_test continue \ +"Continuing\\..*rename 5:.*ENOENT.*test_rename \\(\\) at.*$srcfile:397.*" \ +"Renaming a nonexistant file returns ENOENT" + +send_gdb "tbreak 412\n" ; gdb_expect -re "$gdb_prompt $" +gdb_test continue \ +"Continuing\\..*unlink 1:.*OK.*test_unlink \\(\\) at.*$srcfile:412.*" \ +"Unlink a file" + +send_gdb "tbreak 432\n" ; gdb_expect -re "$gdb_prompt $" +# This test fails on Cygwin because unlink() succeeds on Win32 systems +# in that situation. +if [ishost *cygwin*] { + setup_xfail "*-*-*" +} +gdb_test continue \ +"Continuing\\..*unlink 2:.*EACCES.*test_unlink \\(\\) at.*$srcfile:432.*" \ +"Unlinking a file in a directory w/o write access returns EACCES" + +send_gdb "tbreak 436\n" ; gdb_expect -re "$gdb_prompt $" +gdb_test continue \ +"Continuing\\..*unlink 3:.*ENOENT.*test_unlink \\(\\) at.*$srcfile:436.*" \ +"Unlinking a nonexistant file returns ENOENT" + +send_gdb "tbreak 446\n" ; gdb_expect -re "$gdb_prompt $" +gdb_test continue \ +"Continuing\\..*time 1:.*OK.*test_time \\(\\) at.*$srcfile:446.*" \ +"Time(2) call returns the same value as in parameter" + +sleep 2 +send_gdb "tbreak 450\n" ; gdb_expect -re "$gdb_prompt $" +gdb_test continue \ +"Continuing\\..*time 2:.*OK.*test_time \\(\\) at.*$srcfile:450.*" \ +"Time(2) returns feasible values" + +send_gdb "quit\n" +send_gdb "y\n" + +remote_exec build {sh -xc test\ -r\ dir2.fileio.test\ &&\ chmod\ -f\ +w\ dir2.fileio.test} +remote_exec build {sh -xc rm\ -rf\ *.fileio.test} + +set timeout $oldtimeout +return 0 diff --git a/gdb/testsuite/gdb.base/float.exp b/gdb/testsuite/gdb.base/float.exp new file mode 100644 index 0000000..6c80fbb --- /dev/null +++ b/gdb/testsuite/gdb.base/float.exp @@ -0,0 +1,78 @@ +# Copyright 2003 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# Please email any bugs, comments, and/or additions to this file to: +# bug-gdb@gnu.org + +# This file is part of the gdb testsuite. + +if $tracelevel { + strace $tracelevel +} + +# +# Test floating-point related functionality. +# + +set prms_id 0 +set bug_id 0 + +set testfile "run" +set srcfile ${testfile}.c +set binfile ${objdir}/${subdir}/${testfile} +if { [gdb_compile "${srcdir}/${subdir}/${srcfile}" "${binfile}" executable {debug}] != "" } { + gdb_suppress_entire_file "Testcase compile failed, so all tests in this file will automatically fail." +} + +gdb_exit +gdb_start +gdb_reinitialize_dir $srcdir/$subdir +gdb_load ${binfile} + +# Set it up at a breakpoint so we have its registers. + +if ![runto_main] then { + perror "couldn't run to breakpoint" + continue +} + +# Test "info float". + +if { [istarget "alpha*-*-*"] } then { + gdb_test "info float" "f0.*" "info float" +} elseif { [istarget "arm*-*-*"] || \ + [istarget "xscale*-*-*"] || \ + [istarget "strongarm*-*-*"] } then { + gdb_test "info float" "Software FPU type.*mask:.*flags:.*" "info float" +} elseif { [istarget "i?86-*-*"] || [istarget "x86_64-*-*"] } then { + gdb_test "info float" "R7:.*Status Word:.*Opcode:.*" "info float" +} elseif [istarget "ia64-*-*"] then { + gdb_test "info float" "f0.*f1.*f127.*" "info float" +} elseif [istarget "m68k-*-*"] then { + gdb_test "info float" "fp0.*fp1.*fp7.*" "info float" +} elseif [istarget "sh*-*"] then { + # SH may or may not have an FPU + gdb_test_multiple "info float" "info float" { + -re "fpul.*fr0.*fr1.*fr15.*$gdb_prompt $" { + pass "info float (with FPU)" + } + -re "No floating.point info available for this processor.*" { + pass "info float (without FPU)" + } + } +} else { + gdb_test "info float" "No floating.point info available for this processor." "info float" +} diff --git a/gdb/testsuite/gdb.base/freebpcmd.c b/gdb/testsuite/gdb.base/freebpcmd.c new file mode 100644 index 0000000..52d9f30 --- /dev/null +++ b/gdb/testsuite/gdb.base/freebpcmd.c @@ -0,0 +1,15 @@ +int +main (int argc, char **argv) +{ + int i; + +#ifdef usestubs + set_debug_traps(); + breakpoint(); +#endif + + for (i = 0; i < 100; i++) + printf (">>> %d\n", i); /* euphonium */ + + return 0; +} diff --git a/gdb/testsuite/gdb.base/freebpcmd.exp b/gdb/testsuite/gdb.base/freebpcmd.exp new file mode 100644 index 0000000..f952139 --- /dev/null +++ b/gdb/testsuite/gdb.base/freebpcmd.exp @@ -0,0 +1,121 @@ +# Copyright 2003 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + + +# This is a regression test for the following bug, as of 2003-12-12: +# +# Set a breakpoint which will be hit many times. Attach a complex set +# of commands to it, including a "continue" command. Run the program, +# so that the breakpoint is hit, its commands get executed, and the +# program continues and hits the breakpoint again. You will see +# messages like "warning: Invalid control type in command structure.", +# or maybe GDB will crash. +# +# When the breakpoint is hit, bpstat_stop_status copies the +# breakpoint's command tree to the bpstat. bpstat_do_actions then +# calls execute_control_command to run the commands. The 'continue' +# command invokes the following chain of calls: +# +# continue_command +# -> clear_proceed_status +# -> bpstat_clear +# -> free_command_lines +# -> frees the commands we are currently running. +# +# When control does eventually return to execute_control_command, GDB +# continues to walk the tree of freed command nodes, resulting in the +# error messages and / or crashes. +# +# Since this bug depends on storage being reused between the time that +# we continue and the time that we fall back to bpstat_do_actions, the +# reproduction recipe is more delicate than I would like. I welcome +# suggestions for improving this. + +set prms_id 0 +set bug_id 0 + +set testfile "freebpcmd" +set srcfile ${testfile}.c +set srcfile1 ${testfile}1.c +set binfile ${objdir}/${subdir}/${testfile} + +if { [gdb_compile "${srcdir}/${subdir}/${srcfile}" "${binfile}" executable {debug}] != "" } { + gdb_suppress_entire_file "Testcase compile failed, so all tests in this file will automatically fail." +} + +gdb_exit +gdb_start +gdb_reinitialize_dir $srcdir/$subdir +gdb_load ${binfile} + +gdb_test "break [gdb_get_line_number "euphonium"]" "" "set breakpoint" + +# The goal of all this is to make sure that there's plenty of memory +# churn, and different amounts of it each time the inferior stops; +# this seems to make GDB crash more reliably. +set lines {{if (i%2) == 0} + {echo "even "} + {print i} + {else} + {echo "odd "} + {print i} + {end} + {set variable $foo = 0} + {set variable $j = 0} + {while $j < i} + {set variable $foo += $j} + {set variable $j++} + {end} + {print $foo} + {if i != 40} + {c} + {end} + {end}} + +send_gdb "commands\n" +for {set i 0} {$i < [llength $lines]} {incr i} { + gdb_expect { + -re ".*>" { + send_gdb "[lindex $lines $i]\n" + } + -re "$gdb_prompt $" { + set reason "got top-level prompt early" + break + } + timeout { + set reason "timeout" + break + } + } +} +if {$i >= [llength $lines]} { + pass "send breakpoint commands" +} else { + fail "send breakpoint commands ($reason)" +} + +gdb_run_cmd +gdb_test_multiple "" "run program with breakpoint commands" { + -re "warning: Invalid control type in command structure" { + fail "run program with breakpoint commands" + } + -re "$gdb_prompt $" { + pass "run program with breakpoint commands" + } + eof { + fail "run program with breakpoint commands (GDB died)" + } +} diff --git a/gdb/testsuite/gdb.base/gdb1056.exp b/gdb/testsuite/gdb.base/gdb1056.exp new file mode 100644 index 0000000..623f837 --- /dev/null +++ b/gdb/testsuite/gdb.base/gdb1056.exp @@ -0,0 +1,48 @@ +# Copyright 2003 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# Test for PR gdb/1056. +# 2003-10-18 Michael Chastain + +if $tracelevel then { + strace $tracelevel +} + +# test SIGFPE (such as division by 0) inside gdb itself + +set prms_id 0 +set bug_id 0 + +gdb_start + +# When SIGFPE happens, the operating system may restart the +# offending instruction after the signal handler returns, +# rather than proceeding to the next instruction. This happens +# on i686-pc-linux-gnu with a linux kernel. If gdb has a naive +# signal handler that just returns, then it will restart the +# broken instruction and gdb gets an endless stream of SIGFPE's +# and makes no progress. +# +# On a broken gdb this test will just time out. + +gdb_test_multiple "print 1/0" "" { + -re ".*$gdb_prompt $" { + pass "print 1/0" + } + timeout { + kfail "gdb/1056" "print 1/0" + } +} diff --git a/gdb/testsuite/gdb.base/gdb1090.c b/gdb/testsuite/gdb.base/gdb1090.c new file mode 100644 index 0000000..cd9e2cd --- /dev/null +++ b/gdb/testsuite/gdb.base/gdb1090.c @@ -0,0 +1,48 @@ +/* Test program for multi-register variable. + Copyright 2003 Free Software Foundation, Inc. + + This file is part of the gdb testsuite. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. + + This file was written by Michael Elizabeth Chastain (mec@shout.net). */ + +struct s_2_by_4 +{ + int field_0; + int field_1; +}; + +void marker (struct s_2_by_4 s_whatever) +{ + s_whatever = s_whatever; + return; +} + +void foo () +{ + /* I want this variable in a register but I can't really force it */ + register struct s_2_by_4 s24; + s24.field_0 = 1170; + s24.field_1 = 64701; + marker (s24); + return; +} + +int main () +{ + foo (); +} diff --git a/gdb/testsuite/gdb.base/gdb1090.exp b/gdb/testsuite/gdb.base/gdb1090.exp new file mode 100644 index 0000000..20da3b1 --- /dev/null +++ b/gdb/testsuite/gdb.base/gdb1090.exp @@ -0,0 +1,67 @@ +# Copyright 2003 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# Tests for PR gdb/1090. +# 2003-02-23 Michael Chastain + +# This file is part of the gdb testsuite. + +if $tracelevel then { + strace $tracelevel + } + +# +# test running programs +# +set prms_id 0 +set bug_id 0 + +set testfile "gdb1090" +set srcfile ${testfile}.c +set binfile ${objdir}/${subdir}/${testfile} + +if { [gdb_compile "${srcdir}/${subdir}/${srcfile}" "${binfile}" executable {debug}] != "" } { + gdb_suppress_entire_file "Testcase compile failed, so all tests in this file will automatically fail." +} + +gdb_exit +gdb_start +gdb_reinitialize_dir $srcdir/$subdir +gdb_load ${binfile} + +if ![runto marker] then { + perror "couldn't run to breakpoint" + continue +} +gdb_test "up" ".*foo.*" "up from marker" + +send_gdb "print s24\n" +gdb_expect { + -re "\\\$\[0-9\]* = \\{field_0 = 1170, field_1 = 64701\\}\r\n$gdb_prompt $" { + pass "print s24" + } + -re "\\\$\[0-9\]* = \\{field_0 = 1170, field_1 = .*\\}\r\n$gdb_prompt $" { + # happens with gcc 2.95.3, which actually puts s24 in registers. + # gdb cannot find the second register and prints garbage. + kfail "gdb/1090" "print s24" + } + -re ".*$gdb_prompt $" { + fail "print s24" + } + timeout { + fail "print s24 (timeout)" + } +} diff --git a/gdb/testsuite/gdb.base/gdb1250.c b/gdb/testsuite/gdb.base/gdb1250.c new file mode 100644 index 0000000..0af58d9 --- /dev/null +++ b/gdb/testsuite/gdb.base/gdb1250.c @@ -0,0 +1,61 @@ +/* Test program for stack trace through noreturn function. + + Copyright 2003 Free Software Foundation, Inc. + + This file is part of the gdb testsuite. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. + + This file was written by Michael Elizabeth Chastain (mec@shout.net). */ + +#include + +int global = 0; + +/* Foo, gcc thinks 'gamma' is a reserved identifier. + http://gcc.gnu.org/bugzilla/show_bug.cgi?id=12213 + I am not interested in testing that point so just avoid the word. + -- chastain 2003-09-08. */ +void my_gamma (int *parray) +{ + return; +} + +void beta () +{ + int array [4]; + array [0] = global++; + array [1] = global++; + array [2] = global++; + array [3] = global++; + my_gamma (array); + abort (); +} + +int alpha () +{ + global++; + beta (); + return 0; +} + +int main () +{ + int i; + global++; + i = alpha (); + return i; +} diff --git a/gdb/testsuite/gdb.base/gdb1250.exp b/gdb/testsuite/gdb.base/gdb1250.exp new file mode 100644 index 0000000..60a6f59 --- /dev/null +++ b/gdb/testsuite/gdb.base/gdb1250.exp @@ -0,0 +1,80 @@ +# Copyright 2003 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# Tests for PR gdb/1250. +# 2003-07-15 Michael Chastain + +# This file is part of the gdb testsuite. + +if $tracelevel then { + strace $tracelevel + } + +# +# test running programs +# +set prms_id 0 +set bug_id 0 + +set testfile "gdb1250" +set srcfile ${testfile}.c +set binfile ${objdir}/${subdir}/${testfile} + +if { [gdb_compile "${srcdir}/${subdir}/${srcfile}" "${binfile}" executable {debug}] != "" } { + gdb_suppress_entire_file "Testcase compile failed, so all tests in this file will automatically fail." +} + +gdb_exit +gdb_start +gdb_reinitialize_dir $srcdir/$subdir +gdb_load ${binfile} + +if ![runto abort] then { + perror "couldn't run to breakpoint" + continue +} + +# See http://sources.redhat.com/gdb/bugs/1250 +# +# In a nutshell: the function 'beta' ends with a call to 'abort', which +# is a noreturn function. So the last instruction of 'beta' is a call +# to 'abort'. When gdb looks for information about the caller of +# 'beta', it looks at the instruction after the call to 'abort' -- which +# is the first instruction of 'alpha'! So gdb uses the wrong frame +# information. It thinks that the test program is in 'alpha' and that +# the prologue "push %ebp / mov %esp,%ebp" has not been executed yet, +# and grabs the wrong values. +# +# By the nature of the bug, it could pass if the C compiler is not smart +# enough to implement 'abort' as a noreturn function. This is okay. +# The real point is that users often put breakpoints on noreturn +# functions such as 'abort' or some kind of exitting function, and those +# breakpoints should work. + +gdb_test_multiple "backtrace" "backtrace from abort" { + -re "#0.*abort.*\r\n#1.*beta.*\r\n#2.*alpha.*\r\n#3.*main.*\r\n$gdb_prompt $" { + pass "backtrace from abort" + } + -re "#0.*abort.*\r\n#1.*beta.*\r\n$gdb_prompt $" { + # This happens with gdb HEAD as of 2003-07-13, with gcc 3.3, + # binutils 2.14, either -gdwarf-2 or -gstabs+, on native + # i686-pc-linux-gnu. + # + # gdb gets 'abort' and 'beta' right and then goes into the + # weeds. + kfail "gdb/1250" "backtrace from abort" + } +} diff --git a/gdb/testsuite/gdb.base/gdb_history b/gdb/testsuite/gdb.base/gdb_history new file mode 100644 index 0000000..cc22f69 --- /dev/null +++ b/gdb/testsuite/gdb.base/gdb_history @@ -0,0 +1,256 @@ +add-symbol-file +append +append binary +append memory +append value +append binary memory +append binary value +attach +break +b +br +bre +brea +backtrace +bt +ba +bac +continue +c +call +catch +cd +clear +commands +condition +core-file +d +delete +define +delete breakpoints +delete display +detach +directory +dis +disa +disable +disable breakpoints +disable display +disassemble +display +do +document +down +down-silently +dump +dump binary +dump ihex +dump memory +dump srec +dump tekhex +dump value +dump binary memory +dump binary value +dump ihex memory +dump ihex value +dump srec memory +dump srec value +dump tekhex memory +dump tekhex value +echo +enable breakpoints delete +enable breakpoints once +enable breakpoints +enable delete +enable display +enable once +enable +exec-file +f +frame +fg +file +finish +forward-search +gcore +generate-core-file +h +help +handle +i +info +ignore +info address +info all-registers +info args +info bogus-gdb-command +info breakpoints +info catch +info copying +info display +info f +info frame +info files +info float +info functions +info locals +info program +info registers +info s +info stack +info set +info symbol +info source +info sources +info target +info terminal +info types +info variables +info warranty +info watchpoints +inspect +jump +kill +l +list +load +n +next +ni +nexti +output +overlay +overlay on +overlay manual +overlay auto +overlay off +overlay list +overlay map +overlay unmap +overlay manual +overlay map +overlay unmap +p +print +printf +ptype +pwd +r +run +rbreak +restore +return +reverse-search +s +step +search +section +set annotate +set args +set c +set ch +set check +set check range +set check type +set complaints +set confirm +set environment +set height +set history expansion +set history filename +set history save +set history size +set history +set language +set listsize +set p +set pr +set print +set print address +set print array +set print asm-demangle +set print demangle +set print elements +set print object +set print pretty +set print sevenbit-strings +set print union +set print vtbl +set radix +set symbol-reloading +set variable +set verbose +set width +set write +set +shell echo Hi dad! +show annotate +show args +show c +show ch +show check +show check range +show check type +show commands +show complaints +show confirm +show convenience +show directories +show editing +show height +show history expansion +show history filename +show history save +show history size +show history +show language +show listsize +show p +show pr +show print +show paths +show print address +show print array +show print asm-demangle +show print demangle +show print elements +show print object +show print pretty +show print sevenbit-strings +show print union +show print vtbl +show prompt +show radix +show symbol-reloading +show user +show values +show verbose +show version +show width +show write +show +si +stepi +signal +source +s +step +symbol-file +target child +target procfs +target core +target exec +target remote +target +tbreak +tty +u +until +undisplay +unset environment +unset +up-silently +watch +whatis +where +x diff --git a/gdb/testsuite/gdb.base/psymtab.exp b/gdb/testsuite/gdb.base/psymtab.exp new file mode 100644 index 0000000..8c2abff --- /dev/null +++ b/gdb/testsuite/gdb.base/psymtab.exp @@ -0,0 +1,72 @@ +# Copyright 2003 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# Please email any bugs, comments, and/or additions to this file to: +# bug-gdb@prep.ai.mit.edu + +# This file is part of the gdb testsuite + +# This is intended to be a repository for tests that partial symbols +# are working properly. If multiple tests are added, make sure that +# you exit and restart GDB between tests. + +if $tracelevel then { + strace $tracelevel +} + +# +# test running programs +# + +set prms_id 0 +set bug_id 0 + +if { [skip_cplus_tests] } { continue } + +set testfile "psymtab" +set binfile ${objdir}/${subdir}/${testfile} + +if { [gdb_compile "${srcdir}/${subdir}/${testfile}1.c" "${testfile}1.o" object {debug}] != "" } { + gdb_suppress_entire_file "Testcase compile failed, so all tests in this file will automatically fail." +} + +if { [gdb_compile "${srcdir}/${subdir}/${testfile}2.c" "${testfile}2.o" object {debug}] != "" } { + gdb_suppress_entire_file "Testcase compile failed, so all tests in this file will automatically fail." +} + +if { [gdb_compile "${testfile}1.o ${testfile}2.o" ${binfile} executable {debug}] != "" } { + gdb_suppress_entire_file "Testcase compile failed, so all tests in this file will automatically fail." +} + +# Create and source the file that provides information about the compiler +# used to compile the test case. +if [get_compiler_info ${binfile}] { + return -1; +} + +gdb_exit +gdb_start +gdb_reinitialize_dir $srcdir/$subdir +gdb_load ${binfile} + +# This test is looking for a bug that manifested itself when GDB was +# looking for a partial symbol such that there wasn't such a partial +# symbol in the psymtab, but such that the last psym in the psymtab +# had the right name but the wrong namespace. Here, searching for +# zzz::dummy currently causes a search for 'zzz' in STRUCT_NAMESPACE +# without a preceding search for 'zzz' in VAR_NAMESPACE. + +gdb_test "break zzz::dummy" "Can't find member of namespace, class, struct, or union named \"zzz::dummy\"\r\n.*" "Don't search past end of psymtab." diff --git a/gdb/testsuite/gdb.base/psymtab1.c b/gdb/testsuite/gdb.base/psymtab1.c new file mode 100644 index 0000000..1482f27 --- /dev/null +++ b/gdb/testsuite/gdb.base/psymtab1.c @@ -0,0 +1,4 @@ +int main () +{ + return 0; +} diff --git a/gdb/testsuite/gdb.base/psymtab2.c b/gdb/testsuite/gdb.base/psymtab2.c new file mode 100644 index 0000000..eeaa5ed --- /dev/null +++ b/gdb/testsuite/gdb.base/psymtab2.c @@ -0,0 +1,3 @@ +extern int zzz; + +int zzz = 123; diff --git a/gdb/testsuite/gdb.base/shreloc.c b/gdb/testsuite/gdb.base/shreloc.c new file mode 100644 index 0000000..6867362 --- /dev/null +++ b/gdb/testsuite/gdb.base/shreloc.c @@ -0,0 +1,18 @@ +#if defined(_WIN32) || defined(__CYGWIN__) +# define ATTRIBUTES __attribute((__dllimport__)) +#else +# define ATTRIBUTES +#endif + +extern ATTRIBUTES void fn_1 (int); +extern ATTRIBUTES void fn_2 (int); +extern ATTRIBUTES int extern_var_1; +extern ATTRIBUTES int extern_var_2; + +int main () +{ + fn_1 (extern_var_1); + fn_2 (extern_var_2); + + return 0; +} diff --git a/gdb/testsuite/gdb.base/shreloc.exp b/gdb/testsuite/gdb.base/shreloc.exp new file mode 100644 index 0000000..55ec1e7 --- /dev/null +++ b/gdb/testsuite/gdb.base/shreloc.exp @@ -0,0 +1,262 @@ +# Copyright (C) 2003 Free Software Foundation, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. +# + +# Please email any bugs, comments, and/or additions to this file to: +# bug-gdb@prep.ai.mit.edu + +# Tests for shared object file relocation. If two shared objects have +# the same load address (actually, overlapping load spaces), one of +# them gets relocated at load-time. Check that gdb gets the right +# values for the debugging and minimal symbols. + +if {[istarget *-elf*] || [istarget *-coff] || [istarget *-aout]} then { + verbose "test skipped - shared object files not supported by this target." + return 0 +} + +if $tracelevel then { + strace $tracelevel +} + +# +# This file uses shreloc.c, shreloc1.c and shreloc2.c +# + +set prms_id 0 +set bug_id 0 + +set workdir ${objdir}/${subdir} + +foreach module [list "shreloc" "shreloc1" "shreloc2"] { + if {[gdb_compile "${srcdir}/${subdir}/${module}.c" "${workdir}/${module}.o" object {debug}] != ""} { + untested "Couldn't compile ${module}.c" + return -1 + } +} + +set additional_flags "additional_flags=-shared" + +if {([istarget "*pc-cygwin"] || [istarget "*pc-mingw32"]) } { + set additional_flags "${additional_flags} -Wl,--image-base,0x04000000" +} + +foreach module [list "shreloc1" "shreloc2"] { + if {[gdb_compile "${workdir}/${module}.o" "${workdir}/${module}.dll" executable [list debug $additional_flags]] != ""} { + untested "Couldn't link ${module}.dll" + return -1 + } +} + +if {[gdb_compile [list "${workdir}/shreloc.o" "${workdir}/shreloc1.dll" "${workdir}/shreloc2.dll"] "${workdir}/shreloc" executable debug] != ""} { + untested "Couldn't link shreloc executable" + return -1 +} + +gdb_exit +gdb_start +gdb_reinitialize_dir $srcdir/$subdir +gdb_load ${workdir}/shreloc + +# Load up the shared objects +if ![runto_main] then { + fail "Can't run to main" + return 0 +} + +proc get_var_address { var } { + global gdb_prompt hex + + send_gdb "print &${var}\n" + # Match output like: + # $1 = (int *) 0x0 + # $5 = (int (*)()) 0 + # $6 = (int (*)()) 0x24 + gdb_expect { + -re "\\\$\[0-9\]+ = \\(.*\\) (0|$hex)( <${var}>)?\[\r\n\]+${gdb_prompt} $" + { + pass "get address of ${var}" + if { $expect_out(1,string) == "0" } { + return "0x0" + } else { + return $expect_out(1,string) + } + } + -re "${gdb_prompt} $" + { fail "get address of ${var} (unknown output)" } + timeout + { fail "get address of ${var} (timeout)" } + } + return "" +} + +# +# Check debugging symbol relocations +# + +# Check extern function for relocation +set fn_1_addr [get_var_address fn_1] +set fn_2_addr [get_var_address fn_2] + +if { "${fn_1_addr}" == "${fn_2_addr}" } { + fail "relocated extern functions have different addresses" +} else { + pass "relocated extern functions have different addresses" +} + +# Check extern var for relocation +set extern_var_1_addr [get_var_address extern_var_1] +set extern_var_2_addr [get_var_address extern_var_2] + +if { "${extern_var_1_addr}" == "${extern_var_2_addr}" } { + fail "relocated extern variables have different addresses" +} else { + pass "relocated extern variables have different addresses" +} + +# Check static var for relocation +set static_var_1_addr [get_var_address static_var_1] +set static_var_2_addr [get_var_address static_var_2] + +if { "${static_var_1_addr}" == "${static_var_2_addr}" } { + fail "relocated static variables have different addresses" +} else { + pass "relocated static variables have different addresses" +} + +# +# Check minimal symbol relocations +# + +proc send_gdb_discard { command } { + # Send a command to gdb and discard output up to the next prompt + + global gdb_prompt + + send_gdb "${command}\n" + + # Discard output + gdb_expect { + -re ".*\[\r\n]+${gdb_prompt} $" { + return 1 + } + timeout { + fail "{$command} (timeout)" + return 0 + } + } +} + +proc get_msym_addrs { var msymfile } { + # Extract the list of values for symbols matching var in the + # minimal symbol output file + + global gdb_prompt hex + set result "" + + send_gdb "shell grep -E \" ${var}(\[ \t\]+.*)?\$\" ${msymfile}\n" + + while 1 { + gdb_expect { + -re "\[\[\]\[ 0-9\]+\] . (${hex}) ${var}(\[ \t\]+\[^\r\n\]*)?\[\r\n\]+" { + set result [concat $result $expect_out(1,string)] + } + + -re "$gdb_prompt $" { + pass "get_msym_addrs ${var} (${result})" + return "${result}" + } + + -re "\[^\r\n\]*\[\r\n\]+" { + # Skip + } + + timeout { + fail "get_msym_addrs ${var} (timeout)" + return -1 + } + } + } +} + +proc check_same {var msymfile} { + # Check that the minimal symbol values matching var are the same + + set len [llength [lsort -unique [get_msym_addrs "${var}" "${msymfile}"]]] + + if { $len == 1 } { + return 1 + } else { + return 0 + } +} + +proc check_different {var msymfile} { + # Check that the minimal symbol values matching var are different + + set addr_list [lsort [get_msym_addrs "${var}" "${msymfile}"]] + set prev "" + + if { [llength ${addr_list}] < 2 } { + return 0 + } + + foreach addr ${addr_list} { + if { ${prev} == ${addr} } { + return 0 + } + set prev ${addr} + } + + return 1 +} + +set msymfile "${workdir}/shreloc.txt" + +if [send_gdb_discard "maint print msymbols ${msymfile}"] { + if {[check_different "static_var_\[12\]" "${msymfile}"]} { + pass "(msymbol) relocated static vars have different addresses" + } else { + fail "(msymbol) relocated static vars have different addresses" + } + + if {[check_different "extern_var_\[12\]" "${msymfile}"]} { + pass "(msymbol) relocated extern vars have different addresses" + } else { + fail "(msymbol) relocated extern vars have different addresses" + } + + if {[check_different "fn_\[12\]" "${msymfile}"]} { + pass "(msymbol) relocated functions have different addresses" + } else { + fail "(msymbol) relocated functions have different addresses" + } +} + +if {([istarget "*pc-cygwin"] || [istarget "*pc-mingw32"]) } { + # + # We know the names of some absolute symbols included in the + # portable-executable (DLL) format. Check that they didn't get + # relocated. + # + # A better approach would be include absolute symbols via the assembler. + # + if {[check_same "_minor_os_version__" "${msymfile}"]} { + pass "Absolute symbols not relocated" + } else { + fail "Absolute symbols not relocated" + } +} diff --git a/gdb/testsuite/gdb.base/shreloc1.c b/gdb/testsuite/gdb.base/shreloc1.c new file mode 100644 index 0000000..b1bffde --- /dev/null +++ b/gdb/testsuite/gdb.base/shreloc1.c @@ -0,0 +1,10 @@ +#if defined(_WIN32) || defined(__CYGWIN__) +# define ATTRIBUTES __attribute((__dllexport__)) +#else +# define ATTRIBUTES +#endif + +static int static_var_1; + +ATTRIBUTES void fn_1 (int unused) { } +ATTRIBUTES int extern_var_1 = 0; diff --git a/gdb/testsuite/gdb.base/shreloc2.c b/gdb/testsuite/gdb.base/shreloc2.c new file mode 100644 index 0000000..1459093 --- /dev/null +++ b/gdb/testsuite/gdb.base/shreloc2.c @@ -0,0 +1,10 @@ +#if defined(_WIN32) || defined(__CYGWIN__) +# define ATTRIBUTES __attribute((__dllexport__)) +#else +# define ATTRIBUTES +#endif + +static int static_var_2; + +ATTRIBUTES void fn_2 (int unused) { } +ATTRIBUTES int extern_var_2 = 0; diff --git a/gdb/testsuite/gdb.base/store.c b/gdb/testsuite/gdb.base/store.c new file mode 100644 index 0000000..545515d --- /dev/null +++ b/gdb/testsuite/gdb.base/store.c @@ -0,0 +1,295 @@ +/* Check that GDB can correctly update a value, living in a register, + in the target. This pretty much relies on the compiler taking heed + of requests for values to be stored in registers. */ + +/* NOTE: carlton/2002-12-05: These functions were all static, but for + whatever reason that caused GCC 3.1 to optimize away some of the + function calls within main even when no optimization flags were + passed. */ + +typedef signed char charest; + +charest +add_charest (register charest u, register charest v) +{ + return u + v; +} + +short +add_short (register short u, register short v) +{ + return u + v; +} + +int +add_int (register int u, register int v) +{ + return u + v; +} + +long +add_long (register long u, register long v) +{ + return u + v; +} + +typedef long long longest; + +longest +add_longest (register longest u, register longest v) +{ + return u + v; +} + +float +add_float (register float u, register float v) +{ + return u + v; +} + +double +add_double (register double u, register double v) +{ + return u + v; +} + +typedef long double doublest; + +doublest +add_doublest (register doublest u, register doublest v) +{ + return u + v; +} + +/* */ + +charest +wack_charest (register charest u, register charest v) +{ + register charest l = u, r = v; + l = add_charest (l, r); + return l + r; +} + +short +wack_short (register short u, register short v) +{ + register short l = u, r = v; + l = add_short (l, r); + return l + r; +} + +int +wack_int (register int u, register int v) +{ + register int l = u, r = v; + l = add_int (l, r); + return l + r; +} + +long +wack_long (register long u, register long v) +{ + register long l = u, r = v; + l = add_long (l, r); + return l + r; +} + +long +wack_longest (register longest u, register longest v) +{ + register longest l = u, r = v; + l = add_longest (l, r); + return l + r; +} + +float +wack_float (register float u, register float v) +{ + register float l = u, r = v; + l = add_float (l, r); + return l + r; +} + +double +wack_double (register double u, register double v) +{ + register double l = u, r = v; + l = add_double (l, r); + return l + r; +} + +doublest +wack_doublest (register doublest u, register doublest v) +{ + register doublest l = u, r = v; + l = add_doublest (l, r); + return l + r; +} + +/* */ + +struct s_1 { short s[1]; } z_1, s_1; +struct s_2 { short s[2]; } z_2, s_2; +struct s_3 { short s[3]; } z_3, s_3; +struct s_4 { short s[4]; } z_4, s_4; + +struct s_1 +add_struct_1 (struct s_1 s) +{ + int i; + for (i = 0; i < sizeof (s) / sizeof (s.s[0]); i++) + { + s.s[i] = s.s[i] + s.s[i]; + } + return s; +} + +struct s_2 +add_struct_2 (struct s_2 s) +{ + int i; + for (i = 0; i < sizeof (s) / sizeof (s.s[0]); i++) + { + s.s[i] = s.s[i] + s.s[i]; + } + return s; +} + +struct s_3 +add_struct_3 (struct s_3 s) +{ + int i; + for (i = 0; i < sizeof (s) / sizeof (s.s[0]); i++) + { + s.s[i] = s.s[i] + s.s[i]; + } + return s; +} + +struct s_4 +add_struct_4 (struct s_4 s) +{ + int i; + for (i = 0; i < sizeof (s) / sizeof (s.s[0]); i++) + { + s.s[i] = s.s[i] + s.s[i]; + } + return s; +} + +struct s_1 +wack_struct_1 (void) +{ + int i; register struct s_1 u = z_1; + for (i = 0; i < sizeof (s_1) / sizeof (s_1.s[0]); i++) { s_1.s[i] = i + 1; } + u = add_struct_1 (u); + return u; +} + +struct s_2 +wack_struct_2 (void) +{ + int i; register struct s_2 u = z_2; + for (i = 0; i < sizeof (s_2) / sizeof (s_2.s[0]); i++) { s_2.s[i] = i + 1; } + u = add_struct_2 (u); + return u; +} + +struct s_3 +wack_struct_3 (void) +{ + int i; register struct s_3 u = z_3; + for (i = 0; i < sizeof (s_3) / sizeof (s_3.s[0]); i++) { s_3.s[i] = i + 1; } + u = add_struct_3 (u); + return u; +} + +struct s_4 +wack_struct_4 (void) +{ + int i; register struct s_4 u = z_4; + for (i = 0; i < sizeof (s_4) / sizeof (s_4.s[0]); i++) { s_4.s[i] = i + 1; } + u = add_struct_4 (u); + return u; +} + +/* */ + +struct f_1 {unsigned i:1;unsigned j:1;unsigned k:1; } f_1 = {1,1,1}, F_1; +struct f_2 {unsigned i:2;unsigned j:2;unsigned k:2; } f_2 = {1,1,1}, F_2; +struct f_3 {unsigned i:3;unsigned j:3;unsigned k:3; } f_3 = {1,1,1}, F_3; +struct f_4 {unsigned i:4;unsigned j:4;unsigned k:4; } f_4 = {1,1,1}, F_4; + +struct f_1 +wack_field_1 (void) +{ + register struct f_1 u = f_1; + return u; +} + +struct f_2 +wack_field_2 (void) +{ + register struct f_2 u = f_2; + return u; +} + +struct f_3 +wack_field_3 (void) +{ + register struct f_3 u = f_3; + return u; +} + +struct f_4 +wack_field_4 (void) +{ + register struct f_4 u = f_4; + return u; +} + +/* */ + +int +main () +{ + /* These calls are for current frame test. */ + wack_charest (-1, -2); + wack_short (-1, -2); + wack_int (-1, -2); + wack_long (-1, -2); + wack_longest (-1, -2); + wack_float (-1, -2); + wack_double (-1, -2); + wack_doublest (-1, -2); + + /* These calls are for up frame. */ + wack_charest (-1, -2); + wack_short (-1, -2); + wack_int (-1, -2); + wack_long (-1, -2); + wack_longest (-1, -2); + wack_float (-1, -2); + wack_double (-1, -2); + wack_doublest (-1, -2); + + /* These calls are for current frame test. */ + wack_struct_1 (); + wack_struct_2 (); + wack_struct_3 (); + wack_struct_4 (); + + /* These calls are for up frame. */ + wack_struct_1 (); + wack_struct_2 (); + wack_struct_3 (); + wack_struct_4 (); + + wack_field_1 (); + wack_field_2 (); + wack_field_3 (); + wack_field_4 (); + + return 0; +} diff --git a/gdb/testsuite/gdb.base/store.exp b/gdb/testsuite/gdb.base/store.exp new file mode 100644 index 0000000..49e05ef --- /dev/null +++ b/gdb/testsuite/gdb.base/store.exp @@ -0,0 +1,181 @@ +# Copyright 2002, 2003 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# Please email any bugs, comments, and/or additions to this file to: +# bug-gdb@gnu.org + +if $tracelevel { + strace $tracelevel +} + +# +# test running programs +# +set prms_id 0 +set bug_id 0 + +set testfile "store" +set srcfile ${testfile}.c +set binfile ${objdir}/${subdir}/${testfile} +if { [gdb_compile "${srcdir}/${subdir}/${srcfile}" "${binfile}" executable {debug}] != "" } { + gdb_suppress_entire_file "Testcase compile failed, so all tests in this file will automatically fail." +} + +if [get_compiler_info ${binfile}] { + return -1; +} + +gdb_exit +gdb_start +gdb_reinitialize_dir $srcdir/$subdir +gdb_load ${binfile} + +# +# set it up at a breakpoint so we can play with the variable values +# + +if ![runto_main] then { + perror "couldn't run to breakpoint" + continue +} + +# + +proc check_set { t l r new add } { + global gdb_prompt + gdb_test "tbreak wack_${t}" + gdb_test "continue" "register ${t} l = u, r = v;" "continue to wack_${t}" + gdb_test "next" "l = add_${t} .l, r.;" "next ${t}" + gdb_test "print l" " = ${l}" "print old l - ${t}" + gdb_test "print r" " = ${r}" "print old r - ${t}" + gdb_test "set variable l = 4" + gdb_test "print l" " = ${new}" "print new l - ${t}" + gdb_test "next" "return l \\+ r;" + gdb_test "print l" " = ${add}" "print add - ${t}" +} + +check_set "charest" "-1 .*" "-2 .*" "4 ..004." "2 ..002." +check_set "short" "-1" "-2" "4" "2" +check_set "int" "-1" "-2" "4" "2" +check_set "long" "-1" "-2" "4" "2" +check_set "longest" "-1" "-2" "4" "2" +check_set "float" "-1" "-2" "4" "2" +check_set "double" "-1" "-2" "4" "2" +check_set "doublest" "-1" "-2" "4" "2" + +# + +proc up_set { t l r new } { + global gdb_prompt + gdb_test "tbreak add_${t}" + gdb_test "continue" "return u . v;" "continue to add_${t}" + gdb_test "up" "l = add_${t} .l, r.;" "up ${t}" + gdb_test "print l" " = ${l}" "up print old l - ${t}" + gdb_test "print r" " = ${r}" "up print old r - ${t}" + gdb_test "set variable l = 4" + gdb_test "print l" " = ${new}" "up print new l - ${t}" +} + +up_set "charest" "-1 .*" "-2 .*" "4 ..004." +up_set "short" "-1" "-2" "4" +up_set "int" "-1" "-2" "4" +up_set "long" "-1" "-2" "4" +up_set "longest" "-1" "-2" "4" +up_set "float" "-1" "-2" "4" +up_set "double" "-1" "-2" "4" +up_set "doublest" "-1" "-2" "4" + +# + +proc check_struct { t old new } { + global gdb_prompt + gdb_test "tbreak wack_struct_${t}" + gdb_test "continue" "int i; register struct s_${t} u = z_${t};" \ + "continue set struct ${t}" + gdb_test "next 2" "add_struct_${t} .u.;" + gdb_test "print u" " = ${old}" "old check struct ${t}" + gdb_test "set variable u = s_${t}" + gdb_test "print u" " = ${new}" "new check struct ${t}" +} + +check_struct "1" "{s = \\{0}}" "{s = \\{1}}" +check_struct "2" "{s = \\{0, 0}}" "{s = \\{1, 2}}" +check_struct "3" "{s = \\{0, 0, 0}}" "{s = \\{1, 2, 3}}" +check_struct "4" "{s = \\{0, 0, 0, 0}}" "{s = \\{1, 2, 3, 4}}" + +proc up_struct { t old new } { + global gdb_prompt + gdb_test "tbreak add_struct_${t}" + gdb_test "continue" "for .i = 0; i < sizeof .s. / sizeof .s.s.0..; i..." \ + "continue up struct ${t}" + gdb_test "up" "u = add_struct_${t} .u.;" "up struct ${t}" + gdb_test "print u" " = ${old}" "old up struct ${t}" + gdb_test "set variable u = s_${t}" + gdb_test "print u" " = ${new}" "new up struct ${t}" +} + +up_struct "1" "{s = \\{0}}" "{s = \\{1}}" +up_struct "2" "{s = \\{0, 0}}" "{s = \\{1, 2}}" +up_struct "3" "{s = \\{0, 0, 0}}" "{s = \\{1, 2, 3}}" +up_struct "4" "{s = \\{0, 0, 0, 0}}" "{s = \\{1, 2, 3, 4}}" + +# + +proc check_field { t } { + global gdb_prompt + gdb_test "tbreak wack_field_${t}" + gdb_test "continue" "register struct f_${t} u = f_${t};" \ + "continue field ${t}" + + # Match either the return statement, or the line immediatly after + # it. The compiler can end up merging the return statement into + # the return instruction. + gdb_test "next" "(return u;|\})" "next field ${t}" + + gdb_test "print u" " = {i = 1, j = 1, k = 1}" "old field ${t}" + gdb_test "set variable u = F_${t}" + gdb_test "print u" " = {i = 0, j = 0, k = 0}" "new field ${t}" + + gdb_test "set variable u = F_${t}, u.i = f_${t}.i" + gdb_test "print u" " = {i = 1, j = 0, k = 0}" "f_${t}.i" + + gdb_test "set variable u = F_${t}, u.j = f_${t}.j" + gdb_test "print u" " = {i = 0, j = 1, k = 0}" "f_${t}.j" + + gdb_test "set variable u = F_${t}, u.k = f_${t}.k" + gdb_test "print u" " = {i = 0, j = 0, k = 1}" "f_${t}.k" + + gdb_test "set variable u = f_${t}, u.i = F_${t}.i" + gdb_test "print u" " = {i = 0, j = 1, k = 1}" "F_${t}.i" + + gdb_test "set variable u = f_${t}, u.j = F_${t}.j" + gdb_test "print u" " = {i = 1, j = 0, k = 1}" "F_${t}.j" + + gdb_test "set variable u = f_${t}, u.k = F_${t}.k" + gdb_test "print u" " = {i = 1, j = 1, k = 0}" "F_${t}.k" + +} + +check_field 1 +check_field 2 +check_field 3 +check_field 4 + +# + +# WANTED: A fairly portable way of convincing the compiler to split a +# value across memory and registers. + diff --git a/gdb/testsuite/gdb.base/until.exp b/gdb/testsuite/gdb.base/until.exp new file mode 100644 index 0000000..033005d --- /dev/null +++ b/gdb/testsuite/gdb.base/until.exp @@ -0,0 +1,94 @@ +# Copyright 2003 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +# Please email any bugs, comments, and/or additions to this file to: +# bug-gdb@prep.ai.mit.edu + +# until.exp -- Expect script to test 'until' in gdb + +if $tracelevel then { + strace $tracelevel +} + +set testfile "break" +set srcfile ${testfile}.c +set srcfile1 ${testfile}1.c +set binfile ${objdir}/${subdir}/${testfile} + +if { [gdb_compile "${srcdir}/${subdir}/${srcfile}" "${binfile}0.o" object {debug additional_flags=-w}] != "" } { + gdb_suppress_entire_file "Testcase compile failed, so all tests in this file will automatically fail." +} + +if { [gdb_compile "${srcdir}/${subdir}/${srcfile1}" "${binfile}1.o" object {debug additional_flags=-w}] != "" } { + gdb_suppress_entire_file "Testcase compile failed, so all tests in this file will automatically fail." +} + +if { [gdb_compile "${binfile}0.o ${binfile}1.o" "${binfile}" executable {debug additional_flags=-w}] != "" } { + gdb_suppress_entire_file "Testcase compile failed, so all tests in this file will automatically fail." +} + +gdb_exit +gdb_start +gdb_reinitialize_dir $srcdir/$subdir +gdb_load ${binfile} + +set bp_location1 [gdb_get_line_number "set breakpoint 1 here"] +set bp_location19 [gdb_get_line_number "set breakpoint 19 here"] +set bp_location20 [gdb_get_line_number "set breakpoint 20 here"] +set bp_location21 [gdb_get_line_number "set breakpoint 21 here"] + +if ![runto_main] then { + fail "Can't run to main" + return 0 +} + +# Verify that "until " works. (This is really just syntactic +# sugar for "tbreak ; continue".) +# +gdb_test "until $bp_location1" \ + "main .* at .*:$bp_location1.*" \ + "until line number" + +# Verify that a malformed "advance" is gracefully caught. +# +gdb_test "until 80 then stop" \ + "Junk at end of arguments." "malformed until" + +# Rerun up to factorial, outer invocation +if { ![runto factorial] } then { gdb_suppress_tests; } +delete_breakpoints + +# At this point, 'until' should continue the inferior up to when all the +# inner invocations of factorial() are completed and we are back at this +# frame. +# +gdb_test "until $bp_location19" \ + "factorial.*value=720.*at.*${srcfile}:$bp_location19.*return \\(value\\).*" \ + "until factorial, recursive function" + +# Run to a function called by main +# +if { ![runto marker2] } then { gdb_suppress_tests; } +delete_breakpoints + +# Now issue an until with another function, not called by the current +# frame, as argument. This should not work, i.e. the program should +# stop at main, the caller, where we put the 'guard' breakpoint. +# +gdb_test "until marker3" \ + "($hex in |)main.*argc.*argv.*envp.*at.*${srcfile}:($bp_location20.*marker2 \\(43\\)|$bp_location21.*marker3 \\(.stack., .trace.\\)).*" \ + "until func, not called by current frame" + diff --git a/gdb/testsuite/gdb.cp/Makefile.in b/gdb/testsuite/gdb.cp/Makefile.in new file mode 100644 index 0000000..8f4a90e --- /dev/null +++ b/gdb/testsuite/gdb.cp/Makefile.in @@ -0,0 +1,16 @@ +VPATH = @srcdir@ +srcdir = @srcdir@ + +EXECUTABLES = ambiguous annota2 anon-union cplusfuncs cttiadd \ + derivation inherit local member-ptr method misc \ + overload ovldbreak ref-typ ref-typ2 templates userdef virtfunc namespace ref-types + +all info install-info dvi install uninstall installcheck check: + @echo "Nothing to be done for $@..." + +clean mostlyclean: + -rm -f *~ *.o *.ci + -rm -f core ${EXECUTABLES} + +distclean maintainer-clean realclean: clean + -rm -f Makefile config.status config.log diff --git a/gdb/testsuite/gdb.cp/ambiguous.cc b/gdb/testsuite/gdb.cp/ambiguous.cc new file mode 100644 index 0000000..6ee7bc1 --- /dev/null +++ b/gdb/testsuite/gdb.cp/ambiguous.cc @@ -0,0 +1,110 @@ + +void marker1() +{ + return; +} + +class A1 { +public: + int x; + int y; +}; + +class A2 { +public: + int x; + int y; +}; + +class A3 { +public: + int x; + int y; +}; + +class X : public A1, public A2 { +public: + int z; +}; + +class L : public A1 { +public: + int z; +}; + +class LV : public virtual A1 { +public: + int z; +}; + +class M : public A2 { +public: + int w; +}; + +class N : public L, public M { +public: + int r; +}; + +class K : public A1 { +public: + int i; +}; + +class KV : public virtual A1 { +public: + int i; +}; + +class J : public K, public L { +public: + int j; +}; + +class JV : public KV, public LV { +public: + int jv; +}; + +class JVA1 : public KV, public LV, public A1 { +public: + int jva1; +}; + +class JVA2 : public KV, public LV, public A2 { +public: + int jva2; +}; + +class JVA1V : public KV, public LV, public virtual A1 { +public: + int jva1v; +}; + +int main() +{ + A1 a1; + A2 a2; + A3 a3; + X x; + L l; + M m; + N n; + K k; + J j; + JV jv; + JVA1 jva1; + JVA2 jva2; + JVA1V jva1v; + + int i; + + i += k.i + m.w + a1.x + a2.x + a3.x + x.z + l.z + n.r + j.j; + + marker1(); + +} + + + diff --git a/gdb/testsuite/gdb.cp/ambiguous.exp b/gdb/testsuite/gdb.cp/ambiguous.exp new file mode 100644 index 0000000..6385dcb --- /dev/null +++ b/gdb/testsuite/gdb.cp/ambiguous.exp @@ -0,0 +1,237 @@ +# Copyright 1998, 1999, 2003 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# Please email any bugs, comments, and/or additions to this file to: +# bug-gdb@prep.ai.mit.edu + +# This file is part of the gdb testsuite + +# tests relating to ambiguous class members +# Written by Satish Pai 1997-07-28 + +# This file is part of the gdb testsuite + +if $tracelevel then { + strace $tracelevel + } + +# +# test running programs +# + +set prms_id 0 +set bug_id 0 + +if { [skip_cplus_tests] } { continue } + +set testfile "ambiguous" +set srcfile ${testfile}.cc +set binfile ${objdir}/${subdir}/${testfile} + +if [get_compiler_info ${binfile} "c++"] { + return -1; +} + +if { [test_compiler_info gcc-*] } then { continue } + +if { [gdb_compile "${srcdir}/${subdir}/${srcfile}" "${binfile}" executable {debug c++}] != "" } { + gdb_suppress_entire_file "Testcase compile failed, so all tests in this file will automatically fail." +} + + +gdb_exit +gdb_start +gdb_reinitialize_dir $srcdir/$subdir +gdb_load ${binfile} + + +# +# set it up at a breakpoint so we can play with the variable values +# +if ![runto_main] then { + perror "couldn't run to breakpoint" + continue +} + +send_gdb "break marker1\n" ; gdb_expect -re ".*$gdb_prompt $" + send_gdb "cont\n" + gdb_expect { + -re "Break.* marker1 \\(\\) at .*:$decimal.*$gdb_prompt $" { + send_gdb "up\n" + gdb_expect { + -re ".*$gdb_prompt $" { pass "up from marker1" } + timeout { fail "up from marker1" } + } + } + -re "$gdb_prompt $" { fail "continue to marker1" } + timeout { fail "(timeout) continue to marker1" } + } + +# print out various class objects' members. The values aren't +# important, just check that the warning is emitted at the +# right times. + +# X is derived from A1 and A2; both A1 and A2 have a member 'x' +send_gdb "print x.x\n" +gdb_expect { + -re "warning: x ambiguous; using X::A2::x. Use a cast to disambiguate.\r\n\\$\[0-9\]* = \[-\]*\[0-9\]*\r\n$gdb_prompt $" { + pass "print x.x" + } + -re "warning: x ambiguous; using X::A1::x. Use a cast to disambiguate.\r\n\\$\[0-9\]* = \[-\]*\[0-9\]*\r\n$gdb_prompt $" { + pass "print x.x" + } + -re ".*$gdb_prompt $" { fail "print x.x" } + timeout { fail "(timeout) print x.x" } +} + + +# N is derived from A1 and A2, but not immediately -- two steps +# up in the hierarchy. Both A1 and A2 have a member 'x'. +send_gdb "print n.x\n" +gdb_expect { + -re "warning: x ambiguous; using N::M::A2::x. Use a cast to disambiguate.\r\n\\$\[0-9\]* = \[-\]*\[0-9\]*\r\n$gdb_prompt $" { + pass "print n.x" + } + -re "warning: x ambiguous; using N::L::A1::x. Use a cast to disambiguate.\r\n\\$\[0-9\]* = \[-\]*\[0-9\]*\r\n$gdb_prompt $" { + pass "print n.x" + } + -re ".*$gdb_prompt $" { fail "print n.x" } + timeout { fail "(timeout) print n.x" } +} + +# J is derived from A1 twice. A1 has a member x. +send_gdb "print j.x\n" +gdb_expect { + -re "warning: x ambiguous; using J::L::A1::x. Use a cast to disambiguate.\r\n\\$\[0-9\]* = \[-\]*\[0-9\]*\r\n$gdb_prompt $" { + pass "print j.x" + } + -re "warning: x ambiguous; using J::K::A1::x. Use a cast to disambiguate.\r\n\\$\[0-9\]* = \[-\]*\[0-9\]*\r\n$gdb_prompt $" { + pass "print j.x" + } + -re ".*$gdb_prompt $" { fail "print j.x" } + timeout { fail "(timeout) print j.x" } +} + +# JV is derived from A1 but A1 is a virtual base. Should not +# report an ambiguity in this case. +send_gdb "print jv.x\n" +gdb_expect { + -re "warning: x ambiguous.*Use a cast to disambiguate.\r\n\\$\[0-9\]* = \[-\]*\[0-9\]*\r\n$gdb_prompt $" { + fail "print jv.x (ambiguity reported)" + } + -re "\\$\[0-9\]* = \[-\]*\[0-9\]*\r\n$gdb_prompt $" { pass "print jv.x" } + -re ".*$gdb_prompt $" { fail "print jv.x (??)" } + timeout { fail "(timeout) print jv.x" } +} + +# JVA1 is derived from A1; A1 occurs as a virtual base in two +# ancestors, and as a non-virtual immediate base. Ambiguity must +# be reported. +send_gdb "print jva1.x\n" +gdb_expect { + -re "warning: x ambiguous; using JVA1::A1::x. Use a cast to disambiguate.\r\n\\$\[0-9\]* = \[-\]*\[0-9\]*\r\n$gdb_prompt $" { + pass "print jva1.x" + } + -re "warning: x ambiguous; using JVA1::KV::A1::x. Use a cast to disambiguate.\r\n\\$\[0-9\]* = \[-\]*\[0-9\]*\r\n$gdb_prompt $" { + pass "print jva1.x" + } + -re ".*$gdb_prompt $" { fail "print jva1.x" } + timeout { fail "(timeout) print jva1.x" } +} + +# JVA2 is derived from A1 & A2; A1 occurs as a virtual base in two +# ancestors, and A2 is a non-virtual immediate base. Ambiguity must +# be reported as A1 and A2 both have a member 'x'. +send_gdb "print jva2.x\n" +gdb_expect { + -re "warning: x ambiguous; using JVA2::A2::x. Use a cast to disambiguate.\r\n\\$\[0-9\]* = \[-\]*\[0-9\]*\r\n$gdb_prompt $" { + pass "print jva2.x" + } + -re "warning: x ambiguous; using JVA2::KV::A1::x. Use a cast to disambiguate.\r\n\\$\[0-9\]* = \[-\]*\[0-9\]*\r\n$gdb_prompt $" { + pass "print jva2.x" + } + -re ".*$gdb_prompt $" { fail "print jva2.x" } + timeout { fail "(timeout) print jva2.x" } +} + +# JVA1V is derived from A1; A1 occurs as a virtual base in two +# ancestors, and also as a virtual immediate base. Ambiguity must +# not be reported. +send_gdb "print jva1v.x\n" +gdb_expect { + -re "warning: x ambiguous.*Use a cast to disambiguate.\r\n\\$\[0-9\]* = \[-\]*\[0-9\]*\r\n$gdb_prompt $" { + fail "print jva1v.x (ambiguity reported)" + } + -re "\\$\[0-9\]* = \[-\]*\[0-9\]*\r\n$gdb_prompt $" { pass "print jva1v.x" } + -re ".*$gdb_prompt $" { fail "print jva1v.x (??)" } + timeout { fail "(timeout) print jva1v.x" } +} + +# Now check for ambiguous bases. + +# J is derived from A1 twice; report ambiguity if a J is +# cast to an A1. +send_gdb "print (A1)j\n" +gdb_expect { + -re "warning: A1 ambiguous; using J::L::A1. Use a cast to disambiguate.\r\n\\$\[0-9\]* = \{x = \[-\]*\[0-9\]*, y = \[-\]*\[0-9\]*\}\r\n$gdb_prompt $" { + pass "print (A1)j" + } + -re "warning: A1 ambiguous; using J::K::A1. Use a cast to disambiguate.\r\n\\$\[0-9\]* = \{x = \[-\]*\[0-9\]*, y = \[-\]*\[0-9\]*\}\r\n$gdb_prompt $" { + pass "print (A1)j" + } + -re ".*$gdb_prompt $" { fail "print (A1)j" } + timeout { fail "(timeout) print (A1)j" } +} + +# JV is derived from A1 twice, but A1 is a virtual base; should +# not report ambiguity when a JV is cast to an A1. +send_gdb "print (A1)jv\n" +gdb_expect { + -re "warning: A1 ambiguous.*Use a cast to disambiguate.\r\n\\$\[0-9\]* = \{x = \[-\]*\[0-9\]*, y = \[-\]*\[0-9\]*\}\r\n$gdb_prompt $" { + fail "print (A1)jv (ambiguity reported)" + } + -re "\\$\[0-9\]* = \{x = \[-\]*\[0-9\]*, y = \[-\]*\[0-9\]*\}\r\n$gdb_prompt $" { pass "print (A1)jv" } + -re ".*$gdb_prompt $" { fail "print (A1)jv (??)" } + timeout { fail "(timeout) print (A1)jv" } +} + +# JVA1 is derived from A1; A1 is a virtual base and also a +# non-virtual base. Must report ambiguity if a JVA1 is cast to an A1. +send_gdb "print (A1)jva1\n" +gdb_expect { + -re "warning: A1 ambiguous; using JVA1::A1. Use a cast to disambiguate.\r\n\\$\[0-9\]* = \{x = \[-\]*\[0-9\]*, y = \[-\]*\[0-9\]*\}\r\n$gdb_prompt $" { + pass "print (A1)jva1" + } + -re "warning: A1 ambiguous; using JVA1::KV::A1. Use a cast to disambiguate.\r\n\\$\[0-9\]* = \{x = \[-\]*\[0-9\]*, y = \[-\]*\[0-9\]*\}\r\n$gdb_prompt $" { + pass "print (A1)jva1" + } + -re ".*$gdb_prompt $" { fail "print (A1)jva1" } + timeout { fail "(timeout) print (A1)jva1" } +} + +# JVA1V is derived from A1; A1 is a virtual base indirectly +# and also directly; must not report ambiguity when a JVA1V is cast to an A1. +send_gdb "print (A1)jva1v\n" +gdb_expect { + -re "warning: A1 ambiguous.*Use a cast to disambiguate.\r\n\\$\[0-9\]* = \{x = \[-\]*\[0-9\]*, y = \[-\]*\[0-9\]*\}\r\n$gdb_prompt $" { + fail "print (A1)jva1v (ambiguity reported)" + } + -re "\\$\[0-9\]* = \{x = \[-\]*\[0-9\]*, y = \[-\]*\[0-9\]*\}\r\n$gdb_prompt $" { pass "print (A1)jva1v" + } + -re ".*$gdb_prompt $" { fail "print (A1)jva1v (??)" } + timeout { fail "(timeout) print (A1)jva1v" } +} + diff --git a/gdb/testsuite/gdb.cp/annota2.cc b/gdb/testsuite/gdb.cp/annota2.cc new file mode 100644 index 0000000..234752e --- /dev/null +++ b/gdb/testsuite/gdb.cp/annota2.cc @@ -0,0 +1,28 @@ +#include + +class A { +public: + int x; + int y; + int foo (int arg); +}; + + +int A::foo (int arg) +{ + x += arg; + return arg *2; +} + +int main() +{ + A a; + + a.x = 0; + a.x = 1; + a.y = 2; + + printf ("a.x is %d\n", a.x); + return 0; +} + diff --git a/gdb/testsuite/gdb.cp/annota2.exp b/gdb/testsuite/gdb.cp/annota2.exp new file mode 100644 index 0000000..f4f2433 --- /dev/null +++ b/gdb/testsuite/gdb.cp/annota2.exp @@ -0,0 +1,234 @@ +# Copyright 1999, 2000, 2001, 2002, 2003 +# Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# Please email any bugs, comments, and/or additions to this file to: +# bug-gdb@prep.ai.mit.edu + +# This file was written by Elena Zannoni (ezannoni@cygnus.com) + +if $tracelevel then { + strace $tracelevel +} + + +# +# test running programs +# +set prms_id 0 +set bug_id 0 + +if { [skip_cplus_tests] } { continue } + +set testfile "annota2" +set srcfile ${testfile}.cc +set binfile ${objdir}/${subdir}/${testfile} + +if { [gdb_compile "${srcdir}/${subdir}/${srcfile}" "${binfile}" executable {debug c++ additional_flags=-w}] != "" } { + gdb_suppress_entire_file "Testcase compile failed, so all tests in this file will automatically fail." +} + +# are we on a target board? If so, don't run these tests. +# note: this is necessary because we cannot use runto_main (which would +# work for remote targets too) because of the different prompt we get +# when using annotation level 2. +# +if [is_remote target] then { + return 0 +} + + +gdb_exit +gdb_start +gdb_reinitialize_dir $srcdir/$subdir +gdb_load ${binfile} + +if [target_info exists gdb_stub] { + gdb_step_for_stub; +} + +# +# line number where we need to stop in main +# +set main_line 25 + +# The commands we test here produce many lines of output; disable "press +# to continue" prompts. +send_gdb "set height 0\n" +gdb_expect -re "$gdb_prompt $" + +# +# break at main +# +gdb_test "break 25" \ + "Breakpoint.*at.* file .*$srcfile, line.*" \ + "breakpoint main" + + +# +# NOTE: this prompt is OK only when the annotation level is > 1 +# NOTE: When this prompt is in use the gdb_test procedure cannot be used because +# it assumes that the last char of the gdb_prompt is a white space. This is not +# true with this annotated prompt. So we must use send_gdb and gdb_expect. +# + +set old_gdb_prompt $gdb_prompt +set gdb_prompt "\r\n\032\032pre-prompt\r\n$gdb_prompt \r\n\032\032prompt\r\n" + +send_gdb "set annotate 2\n" +gdb_expect { + -re "set annotate 2\r\n$gdb_prompt$" { pass "annotation set at level 2" } + -re ".*$gdb_prompt$" { fail "annotation set at level 2" } + timeout { fail "annotation set at level 2 (timeout)" } + } + +send_gdb "run\n" + gdb_expect { + -re "$main_line.*$gdb_prompt$" { pass "run until main breakpoint" } + -re ".*$gdb_prompt$" { fail "run until main breakpoint" } + timeout { fail "run until main breakpoint (timeout)" } + } + +# +# print class 'a' with public fields. +# this will test: +# annotate-field-begin +# annotate-field-name-end +# annotate-field-value +# annotate-field-end +# +send_gdb "print a\n" +gdb_expect { + -re "\r\n\032\032post-prompt\r\n\r\n\032\032value-history-begin 1 -\r\n.*= \r\n\032\032value-history-value\r\n\\{\r\n\032\032field-begin -\r\nx\r\n\032\032field-name-end\r\n = \r\n\032\032field-value\r\n1\r\n\032\032field-end\r\n, \r\n\032\032field-begin -\r\ny\r\n\032\032field-name-end\r\n = \r\n\032\032field-value\r\n2\r\n\032\032field-end\r\n\\}\r\n\r\n\032\032value-history-end\r\n$gdb_prompt$" \ + { pass "print class" } + -re ".*$gdb_prompt$" { fail "print class" } + timeout { fail "print class (timeout)" } +} + +# +# continue until exit +# this will test: +# annotate-exited +# +send_gdb "continue\n" +gdb_expect { + -re "\r\n\032\032post-prompt\r\nContinuing.\r\n\r\n\032\032starting\r\n\r\n\032\032frames-invalid\r\na.x is 1\r\n\r\n\032\032frames-invalid\r\n\r\n\032\032exited 0\r\n\r\nProgram exited normally.\r\n\r\n\032\032frames-invalid\r\n\r\n\032\032stopped\r\n$gdb_prompt$" \ + { pass "continue until exit" } + -re ".*$gdb_prompt$" { fail "continue to exit" } + timeout { fail "continue to exit (timeout)" } +} + +# +# delete all breakpoints +# +send_gdb "delete\n" +gdb_expect { + -re ".*Delete all breakpoints. \\(y or n\\) \r\n\032\032query.*$" { + send_gdb "y\n" + gdb_expect { + -re "\r\n\032\032post-query\r\n$gdb_prompt$" { pass "delete bps" } + -re ".*$gdb_prompt$" { fail "delete bps" } + timeout { fail "delete bps (timeout)" } + } + } + -re ".*$gdb_prompt$" { fail "delete bps" } + timeout { fail "delete bps (timeout)" } +} + +# +# break at first line of main. +# +send_gdb "break 22\n" +gdb_expect { + -re "\r\n\032\032post-prompt\r\n\r\n\032\032breakpoints-invalid\r\nBreakpoint.*at $hex: file.*$srcfile, line.*\r\n$gdb_prompt$" \ + { pass "breakpoint at main" } + -re ".*$gdb_prompt$" { fail "break at main" } + timeout { fail "break at main (timeout)" } +} + +# +# change value of main_line +# +set main_line 22 + +# +# run program up to breakpoint. +# + + +send_gdb "run\n" + gdb_expect { + -re "$main_line.*$gdb_prompt$" { pass "run until main breakpoint" } + -re ".*$gdb_prompt$" { fail "run until main breakpoint" } + timeout { fail "run until main breakpoint (timeout)" } + } + +# +# set up a watch point on a.x +# +send_gdb "watch a.x\n" +gdb_expect { + -re "\r\n\032\032post-prompt\r\n\r\n\032\032breakpoints-invalid\r\n.*atchpoint 3: a.x\r\n$gdb_prompt$" \ + { pass "set watch on a.x" } + -re ".*$gdb_prompt$" { fail "set watch on a.x" } + timeout { fail "set watch on a.x (timeout)" } +} + +# +# do a next, so that the watchpoint triggers. This will test: +# annotate-watchpoint +# +send_gdb "next\n" +gdb_expect { + -re "\r\n\032\032post-prompt\r\n\r\n\032\032starting\r\n\r\n\032\032frames-invalid\r\n\r\n\032\032frames-invalid\r\n\r\n\032\032frames-invalid\r\n\r\n\032\032watchpoint 3\r\n.*atchpoint 3: a.x\r\n\r\nOld value = 0\r\nNew value = 1\r\n\r\n\032\032frame-begin 0 $hex\r\n\r\n\032\032frame-function-name\r\nmain\r\n\032\032frame-args\r\n \\(\\)\r\n\032\032frame-source-begin\r\n at \r\n\032\032frame-source-file\r\n.*$srcfile\r\n\032\032frame-source-file-end\r\n:\r\n\032\032frame-source-line\r\n$decimal\r\n\032\032frame-source-end\r\n\r\n\r\n\032\032source .*$srcfile.*beg:$hex\r\n\r\n\032\032frame-end\r\n\r\n\032\032stopped\r\n$gdb_prompt$" \ + { pass "watch triggered on a.x" } + -re "\r\n\032\032post-prompt\r\n\r\n\032\032starting\r\n\r\n\032\032frames-invalid\r\n\r\n\032\032frames-invalid\r\n\r\n\032\032frames-invalid\r\n\r\n\032\032frames-invalid\r\n\r\n\032\032watchpoint 3\r\n\.*atchpoint 3: a.x\r\n\r\nOld value = 0\r\nNew value = 1\r\n\r\n\032\032frame-begin 0 $hex\r\n\r\n\032\032frame-function-name\r\nmain\r\n\032\032frame-args\r\n \\(\\)\r\n\032\032frame-source-begin\r\n at \r\n\032\032frame-source-file\r\n.*$srcfile\r\n\032\032frame-source-file-end\r\n:\r\n\032\032frame-source-line\r\n$decimal\r\n\032\032frame-source-end\r\n\r\n\r\n\032\032source .*$srcfile.*beg:$hex\r\n\r\n\032\032frame-end\r\n\r\n\032\032stopped\r\n.*$gdb_prompt$" \ + { pass "watch triggered on a.x" } + -re "\r\n\032\032post-prompt\r\n\r\n\032\032starting\r\n\r\n\032\032frames-invalid\r\n\r\n\032\032source .*$srcfile.*beg:$hex\r\n\r\n\032\032frame-end\r\n\r\n\032\032stopped\r\n$gdb_prompt$" \ + { kfail "gdb/38" "watch triggered on a.x" } + -re ".*$gdb_prompt$" { fail "watch triggered on a.x" } + timeout { fail "watch triggered on a.x (timeout)" } +} + + +# +# send ^C to gdb, so that the quit() function gets called +# and annotate-quit is tested +# test: +# annotate-quit +# +# This test sometimes fails, but not reproducibly. See gdb/544. +# +send_gdb "\003" +gdb_expect { + -re "\r\n\032\032error-begin\r\nQuit\r\n\r\n\032\032quit\r\n$gdb_prompt$" \ + { pass "annotate-quit" } + -re "$gdb_prompt$" { kfail "gdb/544" "annotate-quit" } + -re ".*$gdb_prompt$" { fail "annotate-quit" } + timeout { fail "annotate-quit (timeout)" } +} + +# +# FIXME: the testsuite does not currently have tests for +# annotate_catchpoints and annotate_function_call +# and a few variants of the annotations that are +# tested (marked by FIXME on the annot?.exp files) +# + +# reinstall the old prompt for the rest of the testsuite. + +set gdb_prompt $old_gdb_prompt + diff --git a/gdb/testsuite/gdb.cp/annota3.cc b/gdb/testsuite/gdb.cp/annota3.cc new file mode 100644 index 0000000..234752e --- /dev/null +++ b/gdb/testsuite/gdb.cp/annota3.cc @@ -0,0 +1,28 @@ +#include + +class A { +public: + int x; + int y; + int foo (int arg); +}; + + +int A::foo (int arg) +{ + x += arg; + return arg *2; +} + +int main() +{ + A a; + + a.x = 0; + a.x = 1; + a.y = 2; + + printf ("a.x is %d\n", a.x); + return 0; +} + diff --git a/gdb/testsuite/gdb.cp/annota3.exp b/gdb/testsuite/gdb.cp/annota3.exp new file mode 100644 index 0000000..c75a289 --- /dev/null +++ b/gdb/testsuite/gdb.cp/annota3.exp @@ -0,0 +1,238 @@ +# Copyright 2003 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# Please email any bugs, comments, and/or additions to this file to: +# bug-gdb@prep.ai.mit.edu + +# This file was written by Elena Zannoni (ezannoni@cygnus.com) + +if $tracelevel then { + strace $tracelevel +} + + +# +# test running programs +# +set prms_id 0 +set bug_id 0 + +if { [skip_cplus_tests] } { continue } + +set testfile "annota3" +set srcfile ${testfile}.cc +set binfile ${objdir}/${subdir}/${testfile} + +if { [gdb_compile "${srcdir}/${subdir}/${srcfile}" "${binfile}" executable {debug c++ additional_flags=-w}] != "" } { + gdb_suppress_entire_file "Testcase compile failed, so all tests in this file will automatically fail." +} + +# are we on a target board? If so, don't run these tests. +# note: this is necessary because we cannot use runto_main (which would +# work for remote targets too) because of the different prompt we get +# when using annotation level 2. +# +if [is_remote target] then { + return 0 +} + + +gdb_exit +gdb_start +gdb_reinitialize_dir $srcdir/$subdir +gdb_load ${binfile} + +if [target_info exists gdb_stub] { + gdb_step_for_stub; +} + +# +# line number where we need to stop in main +# +set main_line 25 + +# The commands we test here produce many lines of output; disable "press +# to continue" prompts. +send_gdb "set height 0\n" +gdb_expect -re "$gdb_prompt $" + +# +# break at main +# +gdb_test "break 25" \ + "Breakpoint.*at.* file .*$srcfile, line.*" \ + "breakpoint main" + + +# +# NOTE: this prompt is OK only when the annotation level is > 1 +# NOTE: When this prompt is in use the gdb_test procedure cannot be used because +# it assumes that the last char of the gdb_prompt is a white space. This is not +# true with this annotated prompt. So we must use send_gdb and gdb_expect. +# + +set old_gdb_prompt $gdb_prompt +set gdb_prompt "\r\n\032\032pre-prompt\r\n$gdb_prompt \r\n\032\032prompt\r\n" + +send_gdb "set annotate 3\n" +gdb_expect_list "annotation set at level 3" "\r\n$gdb_prompt$" { + "set annotate 3" +} + +send_gdb "run\n" +gdb_expect_list "first run until main breakpoint" "$gdb_prompt$" { + "\r\n\032\032post-prompt\r\n" + "Starting program: .*annota3 \r\n" + "\(\r\n\032\032\(frames-invalid|breakpoints-invalid\)\r\n\)+" + "\r\n\032\032starting\r\n" + "\(\r\n\032\032\(frames-invalid|breakpoints-invalid\)\r\n\)+" + "\r\n\032\032breakpoint 1\r\n" + "\r\n" + "Breakpoint 1, main \\(\\) at .*annota3.cc:25\r\n" + "\r\n\032\032source.*annota3.cc:25:.*:beg:0x\[0-9a-z\]+\r\n" + "\r\n\032\032stopped\r\n" +} + +# +# print class 'a' with public fields. +# +send_gdb "print a\n" +gdb_expect_list "print class" "$gdb_prompt$" { + "\r\n\032\032post-prompt\r\n" + ".*= \\{x = 1, y = 2\\}\r\n" +} + +# +# continue until exit +# this will test: +# annotate-exited +# +send_gdb "continue\n" +gdb_expect_list "continue to exit" "$gdb_prompt$" { + "\r\n\032\032post-prompt\r\n" + "Continuing.\r\n" + "\r\n\032\032starting\r\n" + "\r\n\032\032frames-invalid\r\n" + "a.x is 1\r\n" + "\r\n\032\032frames-invalid\r\n" + "\r\n\032\032exited 0\r\n" + "\r\n" + "Program exited normally.\r\n" + "\r\n\032\032frames-invalid\r\n" + "\r\n\032\032stopped\r\n" +} + +# +# delete all breakpoints +# +send_gdb "delete\n" +gdb_expect { + -re ".*Delete all breakpoints. \\(y or n\\) \r\n\032\032query.*$" { + send_gdb "y\n" + gdb_expect { + -re "\r\n\032\032post-query\r\n$gdb_prompt$" { pass "delete bps" } + -re ".*$gdb_prompt$" { fail "delete bps" } + timeout { fail "delete bps (timeout)" } + } + } + -re ".*$gdb_prompt$" { fail "delete bps" } + timeout { fail "delete bps (timeout)" } +} + +# +# break at first line of main. +# +send_gdb "break 22\n" +gdb_expect_list "break at main" "$gdb_prompt$" { + "\r\n\032\032post-prompt\r\n" + "\r\n\032\032breakpoints-invalid\r\n" + "Breakpoint.*at 0x\[a-z0-9\]+: file.*annota3.cc, line 22.\r\n" +} + +# +# run program up to breakpoint. +# + + +send_gdb "run\n" +gdb_expect_list "second run until main breakpoint" "$gdb_prompt$" { + "\r\n\032\032post-prompt\r\n" + "\(\r\n\032\032\(frames-invalid|breakpoints-invalid\)\r\n\)+" + "\r\n\032\032starting\r\n" + "\(\r\n\032\032\(frames-invalid|breakpoints-invalid\)\r\n\)+" + "\r\n\032\032breakpoint 2\r\n" + "\r\n" + "Breakpoint 2, main \\(\\) at .*annota3.cc:22\r\n" + "\r\n\032\032source.*annota3.cc:22:.*:beg:0x\[0-9a-z\]+\r\n" + "\r\n\032\032stopped\r\n" +} + +# +# set up a watch point on a.x +# +send_gdb "watch a.x\n" +gdb_expect_list "set watch on a.x" "$gdb_prompt$" { + "\r\n\032\032post-prompt\r\n" + "\r\n\032\032breakpoints-invalid\r\n" + ".*atchpoint 3: a.x\r\n" \ +} + +# +# do a next, so that the watchpoint triggers. This will test: +# annotate-watchpoint +# +send_gdb "next\n" +gdb_expect { + -re "\r\n\032\032post-prompt\r\n\r\n\032\032starting\r\n\(\r\n\032\032frames-invalid\r\n\)+\r\n\032\032watchpoint 3\r\n.*atchpoint 3: a.x\r\n\r\nOld value = 0\r\nNew value = 1\r\nmain \\(\\) at .*$srcfile:$decimal\r\n\r\n\032\032source .*$srcfile.*beg:$hex\r\n\r\n\032\032stopped\r\n.*$gdb_prompt$" { + pass "watch triggered on a.x" + } + -re "\r\n\032\032post-prompt\r\n\r\n\032\032starting\r\n\r\n\032\032frames-invalid\r\n\r\n\032\032source .*$srcfile.*beg:$hex\r\n\r\n\032\032stopped\r\n$gdb_prompt$" { + kfail "gdb/38" "watch triggered on a.x" + } + -re ".*$gdb_prompt$" { + fail "watch triggered on a.x" + } + timeout { + fail "watch triggered on a.x (timeout)" + } +} + +# +# send ^C to gdb, so that the quit() function gets called +# and annotate-quit is tested +# test: +# annotate-quit +# +# This test sometimes fails, but not reproducibly. See gdb/544. +# +send_gdb "\003" +gdb_expect_list "annotate-quit" "$gdb_prompt$" { + "\r\n\032\032error-begin\r\n" + "Quit\r\n" + "\r\n\032\032quit\r\n" +} + +# +# FIXME: the testsuite does not currently have tests for +# annotate_catchpoints and annotate_function_call +# and a few variants of the annotations that are +# tested (marked by FIXME on the annot?.exp files) +# + +# reinstall the old prompt for the rest of the testsuite. + +set gdb_prompt $old_gdb_prompt + diff --git a/gdb/testsuite/gdb.cp/anon-union.cc b/gdb/testsuite/gdb.cp/anon-union.cc new file mode 100644 index 0000000..0b3fd13 --- /dev/null +++ b/gdb/testsuite/gdb.cp/anon-union.cc @@ -0,0 +1,55 @@ + +struct Foo { + union { + int zero; + unsigned int one; + } num1; + struct X { + int rock; + unsigned int rock2; + }; + union { + int pebble; + X x; + union { + int qux; + unsigned int mux; + }; + unsigned int boulder; + }; + union { + int paper; + unsigned int cloth; + }; + union { + int two; + unsigned int three; + } num2; +}; + +union Bar { + int x; + unsigned int y; +}; + + +int main() +{ + Foo foo = {0, 0}; + + foo.paper = 33; + foo.pebble = 44; + foo.mux = 55; + + Bar bar = {0}; + + union { + int z; + unsigned int w; + }; w = 0; + + bar.x = 33; + + w = 45; + +} diff --git a/gdb/testsuite/gdb.cp/anon-union.exp b/gdb/testsuite/gdb.cp/anon-union.exp new file mode 100644 index 0000000..0d5c777 --- /dev/null +++ b/gdb/testsuite/gdb.cp/anon-union.exp @@ -0,0 +1,348 @@ +# Tests for anonymous union support. +# Copyright 1998, 1999, 2003 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# Please email any bugs, comments, and/or additions to this file to: +# bug-gdb@prep.ai.mit.edu + +# Written by Satish Pai 1997-08-19 + +# This file is part of the gdb testsuite + +if $tracelevel then { + strace $tracelevel + } + +# +# test running programs +# + +set prms_id 0 +set bug_id 0 + +if { [skip_cplus_tests] } { continue } + +set testfile "anon-union" +set srcfile ${testfile}.cc +set binfile ${objdir}/${subdir}/${testfile} + +if { [gdb_compile "${srcdir}/${subdir}/${srcfile}" "${binfile}" executable {debug c++}] != "" } { + perror "Testcase compile failed" 0 + continue +} + +# Start with a fresh gdb +gdb_exit +gdb_start +gdb_reinitialize_dir $srcdir/$subdir +gdb_load ${binfile} + + +if ![runto_main] then { + perror "couldn't run to breakpoint" + continue +} + +send_gdb "set width 0\n" +gdb_expect -re "$gdb_prompt $" + +#send_gdb "ptype foo\n" +#gdb_expect { +# -re "\r\n$gdb_prompt $" { +# pass "ptype foo" +# } +# -re ".*$gdb_prompt $" { fail "ptype foo" } +# timeout { fail "(timeout) ptype foo" } +#} + +#send_gdb "ptype bar\n" +#gdb_expect { +# -re "\r\n$gdb_prompt $" { +# pass "ptype foo" +# } +# -re ".*$gdb_prompt $" { fail "ptype foo" } +# timeout { fail "(timeout) ptype foo" } +#} + +# NOTE: Add -- ptype foo.x, etc. when things are working + +#Initialize foo +send_gdb "next\n" +gdb_expect { + -re "40\[ \t\]*foo.paper = 33;\r\n$gdb_prompt $" { + pass "next 1" + } + -re ".*$gdb_prompt $" { fail "next 1" } + timeout { fail "(timeout) next 1" } +} + +# Print out the big anon union. +send_gdb "print foo\n" +gdb_expect { + -re "\\$\[0-9\]* = \{num1 = \{zero = 0, one = 0\}, \{pebble = 0, x = \{rock = 0, rock2 = 0\}, \{qux = 0, mux = 0\}, boulder = 0\}, \{paper = 0, cloth = 0\}, num2 = \{two = 0, three = 0\}\}\r\n$gdb_prompt $" { + pass "print foo 1" + } + -re ".*$gdb_prompt $" { fail "print foo 1" } + timeout { fail "(timeout) print foo 1" } +} + +# Step over assignment to member + +send_gdb "next\n" +gdb_expect { + -re "41\[ \t\]*foo.pebble = 44;\r\n$gdb_prompt $" { + pass "next 1" + } + -re ".*$gdb_prompt $" { fail "next 1" } + timeout { fail "(timeout) next 1" } +} + +# Now print out anon union again +send_gdb "print foo\n" +gdb_expect { + -re "\\$\[0-9\]* = \{num1 = \{zero = 0, one = 0\}, \{pebble = 0, x = \{rock = 0, rock2 = 0\}, \{qux = 0, mux = 0\}, boulder = 0\}, \{paper = 33, cloth = 33\}, num2 = \{two = 0, three = 0\}\}\r\n$gdb_prompt $" { + pass "print foo 2" + } + -re ".*$gdb_prompt $" { fail "print foo 2" } + timeout { fail "(timeout) print foo 2" } +} + +# Modify the member just set +send_gdb "set var foo.cloth = 35\n" +gdb_expect { + -re "\r\n$gdb_prompt $" { + pass "set var foo.cloth" + } + timeout { fail "(timeout) set var foo.cloth" } +} + +# Now print out anon union again to see if the right member was set +send_gdb "print foo\n" +gdb_expect { + -re "\\$\[0-9\]* = \{num1 = \{zero = 0, one = 0\}, \{pebble = 0, x = \{rock = 0, rock2 = 0\}, \{qux = 0, mux = 0\}, boulder = 0\}, \{paper = 35, cloth = 35\}, num2 = \{two = 0, three = 0\}\}\r\n$gdb_prompt $" { + pass "print foo 3" + } + -re ".*$gdb_prompt $" { fail "print foo 3" } + timeout { fail "(timeout) print foo 3" } +} + + +# Step over next assignment to member + +send_gdb "next\n" +gdb_expect { + -re "42\[ \t\]*foo.mux = 55;\r\n$gdb_prompt $" { + pass "next 2" + } + -re ".*$gdb_prompt $" { fail "next 2" } + timeout { fail "(timeout) next 2" } +} + +# Now print out anon union again +send_gdb "print foo\n" +gdb_expect { + -re "\\$\[0-9\]* = \{num1 = \{zero = 0, one = 0\}, \{pebble = 44, x = \{rock = 44, rock2 = 0\}, \{qux = 44, mux = 44\}, boulder = 44\}, \{paper = 35, cloth = 35\}, num2 = \{two = 0, three = 0\}\}\r\n$gdb_prompt $" { + pass "print foo 4" + } + -re ".*$gdb_prompt $" { fail "print foo 4" } + timeout { fail "(timeout) print foo 4" } +} + +# Modify the member just set +send_gdb "set var foo.pebble = 45\n" +gdb_expect { + -re "\r\n$gdb_prompt $" { + pass "set var foo.pebble" + } + timeout { fail "(timeout) set var foo.pebble" } +} + +# Now print out anon union again to see if the right member was set +send_gdb "print foo\n" +gdb_expect { + -re "\\$\[0-9\]* = \{num1 = \{zero = 0, one = 0\}, \{pebble = 45, x = \{rock = 45, rock2 = 0\}, \{qux = 45, mux = 45\}, boulder = 45\}, \{paper = 35, cloth = 35\}, num2 = \{two = 0, three = 0\}\}\r\n$gdb_prompt $" { + pass "print foo 5" + } + -re ".*$gdb_prompt $" { fail "print foo 5" } + timeout { fail "(timeout) print foo 5" } +} + +# Modify another member at a different level +send_gdb "set var foo.qux = 46\n" +gdb_expect { + -re "\r\n$gdb_prompt $" { + pass "set var foo.qux" + } + timeout { fail "(timeout) set var foo.qux" } +} + +# Now print out anon union again to see if the right member was set +send_gdb "print foo\n" +gdb_expect { + -re "\\$\[0-9\]* = \{num1 = \{zero = 0, one = 0\}, \{pebble = 46, x = \{rock = 46, rock2 = 0\}, \{qux = 46, mux = 46\}, boulder = 46\}, \{paper = 35, cloth = 35\}, num2 = \{two = 0, three = 0\}\}\r\n$gdb_prompt $" { + pass "print foo 6" + } + -re ".*$gdb_prompt $" { fail "print foo 6" } + timeout { fail "(timeout) print foo 6" } +} + +# Modify the member at another level, but not the first one in the union +send_gdb "set var foo.mux = 47\n" +gdb_expect { + -re "\r\n$gdb_prompt $" { + pass "set var foo.mux" + } + timeout { fail "(timeout) set var foo.mux" } +} + +# Now print out anon union again to see if things worked +send_gdb "print foo\n" +gdb_expect { + -re "\\$\[0-9\]* = \{num1 = \{zero = 0, one = 0\}, \{pebble = 47, x = \{rock = 47, rock2 = 0\}, \{qux = 47, mux = 47\}, boulder = 47\}, \{paper = 35, cloth = 35\}, num2 = \{two = 0, three = 0\}\}\r\n$gdb_prompt $" { + pass "print foo 7" + } + -re ".*$gdb_prompt $" { fail "print foo 7" } + timeout { fail "(timeout) print foo 7" } +} + +# Modify a member of a struct in an anon union +send_gdb "set var foo.x.rock = 48\n" +gdb_expect { + -re "\r\n$gdb_prompt $" { + pass "set var foo.x.rock" + } + timeout { fail "(timeout) set var foo.x.rock" } +} + +# Now print out anon union again to see if things worked +send_gdb "print foo\n" +gdb_expect { + -re "\\$\[0-9\]* = \{num1 = \{zero = 0, one = 0\}, \{pebble = 48, x = \{rock = 48, rock2 = 0\}, \{qux = 48, mux = 48\}, boulder = 48\}, \{paper = 35, cloth = 35\}, num2 = \{two = 0, three = 0\}\}\r\n$gdb_prompt $" { + pass "print foo 8" + } + -re ".*$gdb_prompt $" { fail "print foo 8" } + timeout { fail "(timeout) print foo 8" } +} + +# Modify a member of a struct in an anon union, but something +# that doesn't alias to some other union member +send_gdb "set var foo.x.rock2 = 49\n" +gdb_expect { + -re "\r\n$gdb_prompt $" { + pass "set var foo.x.rock2" + } + timeout { fail "(timeout) set var foo.x.rock2" } +} + +# Now print out anon union again to see if things worked +send_gdb "print foo\n" +gdb_expect { + -re "\\$\[0-9\]* = \{num1 = \{zero = 0, one = 0\}, \{pebble = 48, x = \{rock = 48, rock2 = 49\}, \{qux = 48, mux = 48\}, boulder = 48\}, \{paper = 35, cloth = 35\}, num2 = \{two = 0, three = 0\}\}\r\n$gdb_prompt $" { + pass "print foo 9" + } + -re ".*$gdb_prompt $" { fail "print foo 9" } + timeout { fail "(timeout) print foo 9" } +} + + +# Step over next four assignments +send_gdb "next 4\n" +gdb_expect { + -re "53\[ \t\]*w = 45;\r\n$gdb_prompt $" { + pass "next 3" + } + -re ".*$gdb_prompt $" { fail "next 3" } + timeout { fail "(timeout) next 3" } +} + +# Tests for anon unions that are not members of a class or struct + +send_gdb "print w\n" +gdb_expect { + -re "\\$\[0-9\]* = 0\r\n$gdb_prompt $" { + pass "print w 1" + } + -re ".*$gdb_prompt $" { fail "print w 1" } + timeout { fail "(timeout) print w 1" } +} + +send_gdb "print z\n" +gdb_expect { + -re "\\$\[0-9\]* = 0\r\n$gdb_prompt $" { + pass "print z 1" + } + -re ".*$gdb_prompt $" { fail "print z 1" } + timeout { fail "(timeout) print z 1" } +} + +# Step over next assignment to w +send_gdb "next\n" +gdb_expect { + -re "55\[ \t\]*\}\r\n$gdb_prompt $" { + pass "next 4" + } + -re ".*$gdb_prompt $" { fail "next 4" } + timeout { fail "(timeout) next 4" } +} + +# See if the change in value is noticed +send_gdb "print w\n" +gdb_expect { + -re "\\$\[0-9\]* = 45\r\n$gdb_prompt $" { + pass "print w 2" + } + -re ".*$gdb_prompt $" { fail "print w 2" } + timeout { fail "(timeout) print w 2" } +} + +# See if z shows the same value +send_gdb "print z\n" +gdb_expect { + -re "\\$\[0-9\]* = 45\r\n$gdb_prompt $" { + pass "print z 2" + } + -re ".*$gdb_prompt $" { fail "print z 2" } + timeout { fail "(timeout) print z 2" } +} + +# Set the anon union member +send_gdb "set var z = 27\n" +gdb_expect { + -re "\r\n$gdb_prompt $" { + pass "set var z" + } + timeout { fail "(timeout) set var z" } +} + +# See if the change in value is noticed +send_gdb "print w\n" +gdb_expect { + -re "\\$\[0-9\]* = 27\r\n$gdb_prompt $" { + pass "print w 3" + } + -re ".*$gdb_prompt $" { fail "print w 3" } + timeout { fail "(timeout) print w 3" } +} + +# See if z shows the same value +send_gdb "print z\n" +gdb_expect { + -re "\\$\[0-9\]* = 27\r\n$gdb_prompt $" { + pass "print z 3" + } + -re ".*$gdb_prompt $" { fail "print z 3" } + timeout { fail "(timeout) print z 3" } +} diff --git a/gdb/testsuite/gdb.cp/casts.cc b/gdb/testsuite/gdb.cp/casts.cc new file mode 100644 index 0000000..831add9 --- /dev/null +++ b/gdb/testsuite/gdb.cp/casts.cc @@ -0,0 +1,20 @@ +struct A +{ + int a; + A (int aa): a (aa) {} +}; + +struct B: public A +{ + int b; + B (int aa, int bb): A (aa), b(bb) {} +}; + +int +main (int argc, char **argv) +{ + A *a = new B(42, 1729); + B *b = (B *) a; + + return 0; /* breakpoint spot: casts.exp: 1 */ +} diff --git a/gdb/testsuite/gdb.cp/casts.exp b/gdb/testsuite/gdb.cp/casts.exp new file mode 100644 index 0000000..5b6cabe --- /dev/null +++ b/gdb/testsuite/gdb.cp/casts.exp @@ -0,0 +1,85 @@ +# Copyright 2002, 2003 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# Please email any bugs, comments, and/or additions to this file to: +# bug-gdb@prep.ai.mit.edu + +# This file is part of the gdb testsuite + +# Test casting, especially between class types or pointer-to-class +# types. + +# This file is part of the gdb testsuite + +if $tracelevel then { + strace $tracelevel + } + +# +# test running programs +# + +set prms_id 0 +set bug_id 0 + +if { [skip_cplus_tests] } { continue } + +set testfile "casts" +set srcfile ${testfile}.cc +set binfile ${objdir}/${subdir}/${testfile} + +if [get_compiler_info ${binfile} "c++"] { + return -1; +} + +if { [gdb_compile "${srcdir}/${subdir}/${srcfile}" "${binfile}" executable {debug c++}] != "" } { + gdb_suppress_entire_file "Testcase compile failed, so all tests in this file will automatically fail." +} + + +gdb_exit +gdb_start +gdb_reinitialize_dir $srcdir/$subdir +gdb_load ${binfile} + +if ![runto_main] then { + perror "couldn't run to breakpoint" + continue +} + +gdb_test "break [gdb_get_line_number "casts.exp: 1"]" \ + "Breakpoint.*at.* file .*" \ + "" + +gdb_test "continue" "Breakpoint .* at .*casts.cc.*" "" + +# Casting a pointer to a base class to a pointer to a derived class +# should yield the entire derived class. Until August 2002, GDB got +# the enclosing type on `(B *) a' wrong: while the value's static type +# was `B *', as it should be, the enclosing type (which is supposed to +# be the dynamic type) was `A *'. It's senseless to have a static +# type derived from the dynamic type; it should be the other way +# 'round. Dereferencing this oddly typed pointer yielded a value in +# which only the base class's members were initialized, since GDB uses +# the enclosing type to decide how many bytes to read. Members from +# the derived class were garbage, from GDB's address space. +gdb_test "print * (B *) a" ".* = { = {a = 42}, b = 1729}" \ + "cast base class pointer to derived class pointer" + +# Check also that we get the same results from letting the compiler do +# the dereference. +gdb_test "print * b" ".* = { = {a = 42}, b = 1729}" \ + "let compiler cast base class pointer to derived class pointer" diff --git a/gdb/testsuite/gdb.cp/class2.cc b/gdb/testsuite/gdb.cp/class2.cc new file mode 100644 index 0000000..16cf988 --- /dev/null +++ b/gdb/testsuite/gdb.cp/class2.cc @@ -0,0 +1,66 @@ +/* This testcase is part of GDB, the GNU debugger. + + Copyright 2003 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + + Please email any bugs, comments, and/or additions to this file to: + bug-gdb@prep.ai.mit.edu */ + +struct A +{ + virtual ~A (); + int a1; +}; + +A::~A() +{ + a1 = 800; +} + +struct B : public A +{ + virtual ~B (); + int b1; + int b2; +}; + +B::~B() +{ + a1 = 900; + b1 = 901; + b2 = 902; +} + +// Stop the compiler from optimizing away data. +void refer (A *) +{ + ; +} + +int main (void) +{ + A alpha, *aap, *abp; + B beta, *bbp; + + alpha.a1 = 100; + beta.a1 = 200; beta.b1 = 201; beta.b2 = 202; + + aap = α refer (aap); + abp = β refer (abp); + bbp = β refer (bbp); + + return 0; // marker return 0 +} // marker close brace diff --git a/gdb/testsuite/gdb.cp/class2.exp b/gdb/testsuite/gdb.cp/class2.exp new file mode 100644 index 0000000..9d55345 --- /dev/null +++ b/gdb/testsuite/gdb.cp/class2.exp @@ -0,0 +1,115 @@ +# Copyright 2003 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +if $tracelevel then { + strace $tracelevel + } + +if { [skip_cplus_tests] } { continue } + +set prms_id 0 +set bug_id 0 + +set testfile "class2" +set srcfile ${testfile}.cc +set binfile ${objdir}/${subdir}/${testfile} + +# Create and source the file that provides information about the compiler +# used to compile the test case. +if [get_compiler_info ${binfile} "c++"] { + return -1 +} + +if { [gdb_compile "${srcdir}/${subdir}/${srcfile}" "${binfile}" executable {debug c++}] != "" } { + gdb_suppress_entire_file "Testcase compile failed, so all tests in this file will automatically fail." +} + +gdb_exit +gdb_start +gdb_reinitialize_dir $srcdir/$subdir +gdb_load ${binfile} + +# Start with "set print object off". + +gdb_test "set print object off" "" + +if ![runto_main] then { + perror "couldn't run to main" + continue +} + +get_debug_format + +gdb_test "break [gdb_get_line_number "marker return 0"]" \ + "Breakpoint.*at.* file .*" "" + +gdb_test "continue" "Breakpoint .* at .*" "" + +# Access the "A" object. + +gdb_test "print alpha" \ + "= {.*a1 = 100.*}" \ + "print alpha at marker return 0" + +# Access the "B" object. + +gdb_test "print beta" \ + "= {.*a1 = 200.*b1 = 201.*b2 = 202}" \ + "print beta at marker return 0" + +# Access the "A" object through an "A *" pointer. + +gdb_test_multiple "print * aap" "print * aap at marker return 0" { + -re "= {.*a1 = 100.*}\r\n$gdb_prompt $" { + # gcc 2.95.3 -gstabs+ + # gcc 3.3.2 -gdwarf-2 + # gcc 3.3.2 -gstabs+ + pass "print * aap at marker return 0" + } + -re "= {.*a1 = .*}\r\n$gdb_prompt $" { + if { [test_compiler_info gcc-2-*] && [test_debug_format "DWARF 2"] } { + # gcc 2.95.3 -gdwarf-2 + setup_kfail "gdb/1465" "*-*-*" + } + fail "print * aap at marker return 0" + } +} + +# Access the "B" object through a "B *" pointer. + +gdb_test "print * bbp" \ + "= {.*a1 = 200.*b1 = 201.*b2 = 202}" \ + "print * bbp at marker return 0" + +# Access the "B" object through an "A *" pointer. +# This should print using the "A" type. + +gdb_test_multiple "print * abp" "print * abp at marker return 0, s-p-o off" { + -re "= {.*a1 = 200.*b1 = .*b2 = .*}\r\n$gdb_prompt $" { + # This would violate the documentation for "set print object off". + fail "print * abp at marker return 0, s-p-o off" + } + -re "= {.*a1 = 200.*}\r\n$gdb_prompt $" { + pass "print * abp at marker return 0, s-p-o off" + } +} + +# Access the "B" object through a "B *" pointer expression. +# This should print using the "B" type. + +gdb_test "print * (B *) abp" \ + "= {.*a1 = 200.*b1 = 201.*b2 = 202}" \ + "print * (B *) abp at marker return 0" diff --git a/gdb/testsuite/gdb.cp/classes.exp b/gdb/testsuite/gdb.cp/classes.exp new file mode 100644 index 0000000..60f5ab7 --- /dev/null +++ b/gdb/testsuite/gdb.cp/classes.exp @@ -0,0 +1,924 @@ +# Copyright 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, +# 2003 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# Please email any bugs, comments, and/or additions to this file to: +# bug-gdb@prep.ai.mit.edu + +# This file was written by Fred Fish. (fnf@cygnus.com) + +set ws "\[\r\n\t \]+" +set nl "\[\r\n\]+" + +if $tracelevel then { + strace $tracelevel +} + +if { [skip_cplus_tests] } { continue } + +set testfile "misc" +set srcfile ${testfile}.cc +set binfile ${objdir}/${subdir}/${testfile} + +# Create and source the file that provides information about the compiler +# used to compile the test case. + +if [get_compiler_info ${binfile} "c++"] { + return -1 +} + +if { [gdb_compile "${srcdir}/${subdir}/${srcfile}" "${binfile}" executable {debug c++}] != "" } { + gdb_suppress_entire_file "Testcase compile failed, so all tests in this file will automatically fail." +} + +# +# Test ptype of class objects. +# + +proc test_ptype_class_objects {} { + global gdb_prompt + global ws + global nl + + # Note that struct members are public by default, so we don't print + # "public:" for the public members of structs. + # Accept it if gdb just fails to distinguish between + # class and struct, and everything else is OK. + + send_gdb "ptype struct default_public_struct\n" + gdb_expect { + -re "type = struct default_public_struct \{${ws}int a;${ws}int b;$nl\}$nl$gdb_prompt $" { + pass "ptype struct default_public_struct" + } + -re "type = class default_public_struct \{$nl.*int a;${ws}int b;$nl.*\}$nl$gdb_prompt $" { + pass "ptype struct default_public_struct" + } + -re ".*$gdb_prompt $" { fail "ptype struct default_public_struct" } + timeout { fail "ptype struct default_public_struct (timeout)" ; return } + } + + # Note that struct members are public by default, so we don't print + # "public:" for the public members of structs. + # Accept it if gdb just fails to distinguish between + # class and struct, and everything else is OK. + + send_gdb "ptype struct explicit_public_struct\n" + gdb_expect { + -re "type = struct explicit_public_struct \{${ws}int a;${ws}int b;$nl.*\}$nl$gdb_prompt $" { + pass "ptype struct explicit_public_struct" + } + -re "type = class explicit_public_struct \{$nl.*int a;${ws}int b;$nl.*\}$nl$gdb_prompt $" { + pass "ptype struct explicit_public_struct" + } + -re ".*$gdb_prompt $" { fail "ptype struct explicit_public_struct" } + timeout { fail "ptype struct explicit_public_struct (timeout)" ; return } + } + + # Accept it if gdb just fails to distinguish between + # class and struct, and everything else is OK. + + send_gdb "ptype struct protected_struct\n" + gdb_expect { + -re "type = struct protected_struct \{${ws}protected:${ws}int a;${ws}int b;$nl\}$nl$gdb_prompt $" { + pass "ptype struct protected_struct" + } + -re "type = class protected_struct \{${ws}protected:${ws}int a;${ws}int b;$nl.*\}$nl$gdb_prompt $" { + pass "ptype struct protected_struct" + } + -re ".*$gdb_prompt $" { fail "ptype struct protected_struct" } + timeout { fail "ptype struct protected_struct (timeout)" ; return } + } + + # Accept it if gdb just fails to distinguish between + # class and struct, and everything else is OK. + + send_gdb "ptype struct private_struct\n" + gdb_expect { + -re "type = struct private_struct \{${ws}private:${ws}int a;${ws}int b;$nl\}$nl$gdb_prompt $" { + pass "ptype struct private_struct" + } + -re "type = class private_struct \{${ws}private:${ws}int a;${ws}int b;$nl.*\}$nl$gdb_prompt $" { + pass "ptype struct private_struct" + } + -re ".*$gdb_prompt $" { fail "ptype struct private_struct" } + timeout { fail "ptype struct private_struct (timeout)" ; return } + } + + # Accept it if gdb just fails to distinguish between + # class and struct, and everything else is OK. + + send_gdb "ptype struct mixed_protection_struct\n" + gdb_expect { + -re "type = struct mixed_protection_struct \{${ws}int a;${ws}int b;${ws}private:${ws}int c;${ws}int d;${ws}protected:${ws}int e;${ws}int f;${ws}public:${ws}int g;${ws}private:${ws}int h;${ws}protected:${ws}int i;$nl\}$nl$gdb_prompt $" { + pass "ptype struct mixed_protection_struct" + } + -re "type = struct mixed_protection_struct \{${ws}public:${ws}int a;${ws}int b;${ws}private:${ws}int c;${ws}int d;${ws}protected:${ws}int e;${ws}int f;${ws}public:${ws}int g;${ws}private:${ws}int h;${ws}protected:${ws}int i;$nl.*\}$nl$gdb_prompt $" { + pass "ptype struct mixed_protection_struct (extra public)" + } + -re "type = class mixed_protection_struct \{${ws}public:${ws}int a;${ws}int b;${ws}private:${ws}int c;${ws}int d;${ws}protected:${ws}int e;${ws}int f;${ws}public:${ws}int g;${ws}private:${ws}int h;${ws}protected:${ws}int i;$nl.*\}$nl$gdb_prompt $" { + pass "ptype struct mixed_protection_struct" + } + -re ".*$gdb_prompt $" { fail "ptype struct mixed_protection_struct" } + timeout { fail "ptype struct mixed_protection_struct (timeout)" ; return } + } + + # Accept it if gdb just fails to distinguish between + # class and struct, and everything else is OK. + + send_gdb "ptype class public_class\n" + gdb_expect { + -re "type = class public_class \{${ws}public:${ws}int a;${ws}int b;$nl.*\}$nl$gdb_prompt $" { + pass "ptype class public_class" + } + -re "type = struct public_class \{${ws}int a;${ws}int b;$nl\}$nl$gdb_prompt $" { + pass "ptype class public_class" + } + -re ".*$gdb_prompt $" { fail "ptype class public_class" } + timeout { fail "ptype class public_class (timeout)" ; return } + } + + send_gdb "ptype class protected_class\n" + gdb_expect { + -re "type = class protected_class \{${ws}protected:${ws}int a;${ws}int b;$nl.*\}$nl$gdb_prompt $" { + pass "ptype class protected_class" + } + -re "type = struct protected_class \{${ws}int a;${ws}int b;$nl\}$nl$gdb_prompt $" { + fail "ptype class protected_class" + } + -re ".*$gdb_prompt $" { fail "ptype class protected_class" } + timeout { fail "ptype class protected_class (timeout)" ; return } + } + + # Accept it if gdb just emits a superflous "private:" + # attribute, since classes default to private and for consistency with + # structs (where we don't print the "public:" attribute) we don't print + # the "private:" attribute. + + send_gdb "ptype class default_private_class\n" + gdb_expect { + -re "type = class default_private_class \{${ws}int a;${ws}int b;$nl.*\}$nl$gdb_prompt $" { + pass "ptype class default_private_class" + } + -re "type = class default_private_class \{${ws}private:${ws}int a;${ws}int b;$nl.*\}$nl$gdb_prompt $" { + pass "ptype class default_private_class" + } + -re ".*$gdb_prompt $" { fail "ptype class default_private_class" } + timeout { fail "ptype class default_private_class (timeout)" ; return } + } + + send_gdb "ptype class explicit_private_class\n" + gdb_expect { + -re "type = class explicit_private_class \{${ws}private:${ws}int a;${ws}int b;$nl.*\}$nl$gdb_prompt $" { + pass "ptype class explicit_private_class" + } + -re "type = class explicit_private_class \{${ws}int a;${ws}int b;$nl.*\}$nl$gdb_prompt $" { + pass "ptype class explicit_private_class" + } + -re "type = struct explicit_private_class \{${ws}int a;${ws}int b;$nl.*\}$nl$gdb_prompt $" { + fail "ptype class explicit_private_class" + } + -re ".*$gdb_prompt $" { fail "ptype class explicit_private_class" } + timeout { fail "ptype class explicit_private_class (timeout)" ; return } + } + + send_gdb "ptype class mixed_protection_class\n" + gdb_expect { + -re "type = class mixed_protection_class \{${ws}public:${ws}int a;${ws}int b;${ws}private:${ws}int c;${ws}int d;${ws}protected:${ws}int e;${ws}int f;${ws}public:${ws}int g;${ws}private:${ws}int h;${ws}protected:${ws}int i;$nl.*\}$nl$gdb_prompt $" { + pass "ptype class mixed_protection_class" + } + -re "type = struct mixed_protection_class \{${ws}int a;${ws}int b;${ws}int c;${ws}int d;${ws}int e;${ws}int f;${ws}int g;${ws}int h;${ws}int i;$nl.*\}$nl$gdb_prompt $" { + fail "ptype class mixed_protection_class" + } + -re ".*$gdb_prompt $" { fail "ptype class mixed_protection_class" } + timeout { fail "ptype class mixed_protection_class (timeout)" ; return } + } + + # This class does not use any C++-specific features, so it's fine for + # it to print as "struct". + send_gdb "ptype class A\n" + gdb_expect { + -re "type = (class|struct) A \{(${ws}public:|)${ws}int a;${ws}int x;((${ws}A & operator=\\(A const ?&\\);)|(${ws}A\\((A const|const A) ?&\\);)|(${ws}A\\((void|)\\);))*${ws}\}$nl$gdb_prompt $" { + pass "ptype class A" + } + -re ".*$gdb_prompt $" { + fail "ptype class A" + } + timeout { + fail "ptype class A (timeout)" + return + } + } + + send_gdb "ptype class B\n" + gdb_expect { + -re "type = class B : public A \{${ws}public:${ws}int b;${ws}int x;${ws}B & operator=\\(B const ?&\\);${ws}B\\((B const|const B) ?&\\);${ws}B\\((void|)\\);${ws}\}$nl$gdb_prompt $" { + pass "ptype class B" + } + -re "type = class B : public A \{${ws}public:${ws}int b;${ws}int x;((${ws}B & operator=\\(B const ?&\\);)|(${ws}B\\(B const ?&\\);)|(${ws}B\\((void|)\\);))*${ws}\}$nl$gdb_prompt $" { + pass "ptype class B (obsolescent gcc or gdb)" + } + -re ".*$gdb_prompt $" { + fail "ptype class B" + } + timeout { + fail "ptype class B (timeout)" + return + } + } + + send_gdb "ptype class C\n" + gdb_expect { + -re "type = class C : public A \{${ws}public:${ws}int c;${ws}int x;${ws}C & operator=\\(C const ?&\\);${ws}C\\((C const|const C) ?&\\);${ws}C\\((void|)\\);${ws}\}$nl$gdb_prompt $" { + pass "ptype class C" + } + -re "type = class C : public A \{${ws}public:${ws}int c;${ws}int x;((${ws}C & operator=\\(C const ?&\\);)|(${ws}C\\(C const ?&\\);)|(${ws}C\\((void|)\\);))*${ws}\}$nl$gdb_prompt $" { + pass "ptype class C (obsolescent gcc or gdb)" + } + -re ".*$gdb_prompt $" { + fail "ptype class C" + } + timeout { + fail "ptype class C (timeout)" + return + } + } + + send_gdb "ptype class D\n" + gdb_expect { + -re "type = class D : public B, public C \{${ws}public:${ws}int d;${ws}int x;${ws}D & operator=\\(D const ?&\\);${ws}D\\((D const|const D) ?&\\);${ws}D\\((void|)\\);${ws}\}$nl$gdb_prompt $" { + pass "ptype class D" + } + -re "type = class D : public B, public C \{${ws}public:${ws}int d;${ws}int x;((${ws}D & operator=\\(D const ?&\\);)|(${ws}D\\(D const ?&\\);)|(${ws}D\\((void|)\\);))*${ws}\}$nl$gdb_prompt $" { + pass "ptype class D (obsolescent gcc or gdb)" + } + -re ".*$gdb_prompt $" { + fail "ptype class D" + } + timeout { + fail "ptype class D (timeout)" + return + } + } + + send_gdb "ptype class E\n" + gdb_expect { + -re "type = class E : public D \{${ws}public:${ws}int e;${ws}int x;${ws}E & operator=\\(E const ?&\\);${ws}E\\((E const|const E) ?&\\);${ws}E\\((void|)\\);${ws}\}$nl$gdb_prompt $" { + pass "ptype class E" + } + -re "type = class E : public D \{${ws}public:${ws}int e;${ws}int x;((${ws}E & operator=\\(E const ?&\\);)|(${ws}E\\((E const|const E) ?&\\);)|(${ws}E\\((void|)\\);))*${ws}\}$nl$gdb_prompt $" { + pass "ptype class E" + } + -re ".*$gdb_prompt $" { + fail "ptype class E" + } + timeout { + fail "ptype class E (timeout)" + return + } + } + + # With g++ 2.x and stabs debug info, we misinterpret static methods + # whose name matches their argument mangling. + send_gdb "ptype class Static\n" + gdb_expect { + -re "type = (class|struct) Static \{(${ws}public:|)${ws}Static & operator=\\(Static const ?&\\);${ws}Static\\((Static const|const Static) ?&\\);${ws}Static\\((void|)\\);${ws}static void ii\\(int, int\\);${ws}\}$nl$gdb_prompt $" { + pass "ptype class Static" + } + -re "type = (class|struct) Static \{(${ws}public:|)${ws}static void ii\\(int, int\\);${ws}\}$nl$gdb_prompt $" { + pass "ptype class Static" + } + -re ".*$gdb_prompt $" { + fail "ptype class Static" + } + timeout { + fail "ptype class Static (timeout)" + return + } + } + + send_gdb "ptype class vA\n" + gdb_expect { + -re "type = (class|struct) vA \{(${ws}public:|)${ws}int va;${ws}int vx;${ws}\}$nl$gdb_prompt $" { + pass "ptype class vA" + } + -re "type = (class|struct) vA \{(${ws}public:|)${ws}int va;${ws}int vx;${ws}vA & operator=\\(vA const ?&\\);${ws}vA\\((vA const|const vA) ?&\\);${ws}vA\\((void|)\\);${ws}\}$nl$gdb_prompt $" { + pass "ptype class vA" + } + -re "type = (class|struct) vA \{(${ws}public:|)${ws}int va;${ws}int vx;((${ws}vA & operator=\\(vA const ?&\\);)|(${ws}vA\\(vA const ?&\\);)|(${ws}vA\\((void|)\\);))*${ws}\}$nl$gdb_prompt $" { + pass "ptype class vA (obsolescent gcc or gdb)" + } + -re ".*$gdb_prompt $" { + fail "ptype class vA" + } + timeout { + fail "ptype class vA (timeout)" + return + } + } + + # Accept the form with embedded GNU style mangled virtual table constructs + # for now, but with a FIXME. At some future point, gdb should use a + # portable representation for the virtual table constructs. + + # The format of a g++ virtual base pointer. + set vbptr "(_vb\[$.\]|__vb_)\[0-9\]?" + + send_gdb "ptype class vB\n" + gdb_expect { + -re "type = class vB : public virtual vA \{${ws}public:${ws}int vb;${ws}int vx;${ws}vB & operator=\\(vB const ?&\\);${ws}vB\\((vB const|const vB) ?&\\);${ws}vB\\((void|)\\);${ws}\}$nl$gdb_prompt $" { + pass "ptype class vB" + } + -re "type = class vB : public virtual vA \{${ws}private:${ws}vA \\*${vbptr}vA;${ws}public:${ws}int vb;${ws}int vx;${ws}vB & operator=\\(vB const ?&\\);${ws}vB\\(int, vB const ?&\\);${ws}vB\\(int\\);${ws}\}$nl$gdb_prompt $" { + setup_xfail "*-*-*" + fail "ptype class vB (FIXME: non-portable virtual table constructs)" + } + -re "type = class vB : public virtual vA \{${ws}public:${ws}int vb;${ws}int vx;${ws}\}$nl$gdb_prompt $" { + pass "ptype class vB" + } + -re "type = class vB : public virtual vA \{${ws}private:${ws}vA \\*_vb.vA;${ws}public:${ws}int vb;${ws}int vx;((${ws}vB & operator=\\(vB const ?&\\);)|(${ws}vB\\(int, vB const ?&\\);)|(${ws}vB\\(int\\);))*${ws}\}$nl$gdb_prompt $" { + setup_xfail "*-*-*" + fail "ptype class vB (FIXME) (obsolescent gcc or gdb)" + } + -re ".*$gdb_prompt $" { + fail "ptype class vB" + } + timeout { + fail "ptype class vB (timeout)" + return + } + } + + # Accept the form with embedded GNU style mangled virtual table constructs + # for now, but with a FIXME. At some future point, gdb should use a + # portable representation for the virtual table constructs. + + send_gdb "ptype class vC\n" + gdb_expect { + -re "type = class vC : public virtual vA \{${ws}public:${ws}int vc;${ws}int vx;${ws}vC & operator=\\(vC const ?&\\);${ws}vC\\((vC const|const vC) ?&\\);${ws}vC\\((void|)\\);${ws}\}$nl$gdb_prompt $" { + pass "ptype class vC" + } + -re "type = class vC : public virtual vA \{${ws}private:${ws}vA \\*${vbptr}vA;${ws}public:${ws}int vc;${ws}int vx;${ws}vC & operator=\\(vC const ?&\\);${ws}vC\\(int, vC const ?&\\);${ws}vC\\(int\\);${ws}\}$nl$gdb_prompt $" { + setup_xfail "*-*-*" + fail "ptype class vC (FIXME: non-portable virtual table constructs)" + } + -re "type = class vC : public virtual vA \{${ws}public:${ws}int vc;${ws}int vx;${ws}\}$nl$gdb_prompt $" { + pass "ptype class vC" + } + -re "type = class vC : public virtual vA \{${ws}private:${ws}vA \\*_vb.vA;${ws}public:${ws}int vc;${ws}int vx;((${ws}vC & operator=\\(vC const ?&\\);)|(${ws}vC\\(int, vC const ?&\\);)|(${ws}vC\\(int\\);))*${ws}\}$nl$gdb_prompt $" { + setup_xfail "*-*-*" + fail "ptype class vC (FIXME) (obsolescent gcc or gdb)" + } + -re ".*$gdb_prompt $" { + fail "ptype class vC" + } + timeout { + fail "ptype class vC (timeout)" + return + } + } + + # Accept the form with embedded GNU style mangled virtual table constructs + # for now, but with a FIXME. At some future point, gdb should use a + # portable representation for the virtual table constructs. + + send_gdb "ptype class vD\n" + gdb_expect { + -re "type = class vD : public virtual vB, public virtual vC \{${ws}public:${ws}int vd;${ws}int vx;${ws}vD & operator=\\(vD const ?&\\);${ws}vD\\((vD const|const vD) ?&\\);${ws}vD\\((void|)\\);${ws}\}$nl$gdb_prompt $" { + pass "ptype class vD" + } + -re "type = class vD : public virtual vB, public virtual vC \{${ws}private:${ws}vC \\*${vbptr}vC;${ws}vB \\*${vbptr}vB;${ws}public:${ws}int vd;${ws}int vx;${ws}vD & operator=\\(vD const ?&\\);${ws}vD\\(int, vD const ?&\\);${ws}vD\\(int\\);${ws}\}$nl$gdb_prompt $" { + setup_xfail "*-*-*" + fail "ptype class vD (FIXME: non-portable virtual table constructs)" + } + -re "type = class vD : public virtual vB, public virtual vC \{${ws}public:${ws}int vd;${ws}int vx;${ws}\}$nl$gdb_prompt $" { + pass "ptype class vD" + } + -re "type = class vD : public virtual vB, public virtual vC \{${ws}private:${ws}vC \\*_vb.vC;${ws}vB \\*_vb.vB;${ws}public:${ws}int vd;${ws}int vx;((${ws}vD & operator=\\(vD const ?&\\);)|(${ws}vD\\(int, vD const ?&\\);)|(${ws}vD\\(int\\);))*${ws}\}$nl$gdb_prompt $" { + setup_xfail "*-*-*" + fail "ptype class vD (FIXME) (obsolescent gcc or gdb)" + } + -re ".*$gdb_prompt $" { + fail "ptype class vD" + } + timeout { + fail "ptype class vD (timeout)" + return + } + } + + # Accept the form with embedded GNU style mangled virtual table constructs + # for now, but with a FIXME. At some future point, gdb should use a + # portable representation for the virtual table constructs. + + send_gdb "ptype class vE\n" + gdb_expect { + -re "type = class vE : public virtual vD \{${ws}public:${ws}int ve;${ws}int vx;${ws}vE & operator=\\(vE const ?&\\);${ws}vE\\((vE const|const vE) ?&\\);${ws}vE\\((void|)\\);${ws}\}$nl$gdb_prompt $" { + pass "ptype class vE" + } + -re "type = class vE : public virtual vD \{${ws}private:${ws}vD \\*${vbptr}vD;${ws}public:${ws}int ve;${ws}int vx;${ws}vE & operator=\\(vE const ?&\\);${ws}vE\\(int, vE const ?&\\);${ws}vE\\(int\\);${ws}\}$nl$gdb_prompt $" { + setup_xfail "*-*-*" + fail "ptype class vE (FIXME: non-portable virtual table constructs)" + } + -re "type = class vE : public virtual vD \{${ws}public:${ws}int ve;${ws}int vx;${ws}\}$nl$gdb_prompt $" { + pass "ptype class vE" + } + -re "type = class vE : public virtual vD \{${ws}private:${ws}vD \\*_vb.vD;${ws}public:${ws}int ve;${ws}int vx;((${ws}vE & operator=\\(vE const ?&\\);)|(${ws}vE\\(int, vE const ?&\\);)|(${ws}vE\\(int\\);))*${ws}\}$nl$gdb_prompt $" { + setup_xfail "*-*-*" + fail "ptype class vE (FIXME) (obsolescent gcc or gdb)" + } + -re ".*$gdb_prompt $" { + fail "ptype class vE" + } + timeout { + fail "ptype class vE (timeout)" + return + } + } + + send_gdb "ptype class Base1\n" + gdb_expect { + -re "type = class Base1 \{${ws}public:${ws}int x;${ws}Base1 & operator=\\(Base1 const ?&\\);${ws}Base1\\(((Base1 const)|(const Base1)) ?&\\);${ws}Base1\\(int\\);${ws}\}$nl$gdb_prompt $" { + pass "ptype class Base1" + } + -re "type = class Base1 \{${ws}public:${ws}int x;${ws}Base1\\(int\\);${ws}\}$nl$gdb_prompt $" { + pass "ptype class Base1" + } + -re "type = class Base1 \{${ws}public:${ws}int x;((${ws}Base1 & operator=\\(Base1 const ?&\\);)|(${ws}Base1\\(Base1 const ?&\\);)|(${ws}Base1\\(int\\);))*${ws}\}$nl$gdb_prompt $" { + pass "ptype class Base1 (obsolescent gcc or gdb)" + } + -re ".*$gdb_prompt $" { + fail "ptype class Base1" + } + timeout { + fail "ptype class Base1 (timeout)" + return + } + } + + send_gdb "ptype class Foo\n" + gdb_expect { + -re "type = class Foo \{${ws}public:${ws}int x;${ws}int y;${ws}static int st;\r\n${ws}Foo\\(int, int\\);${ws}int operator!\\((void|)\\);${ws}operator int\\((void|)\\);${ws}int times\\(int\\);$nl\}$nl$gdb_prompt $" { + pass "ptype class Foo" + } + -re "type = class Foo \{${ws}public:${ws}int x;${ws}int y;${ws}static int st;${ws}Foo & operator=\\(Foo const ?&\\);${ws}Foo\\((Foo const|const Foo) ?&\\);${ws}Foo\\(int, int\\);${ws}int operator!\\((void|)\\);${ws}operator int\\((void|)\\);${ws}int times\\(int\\);${ws}\}$nl$gdb_prompt $" { + pass "ptype class Foo" + } + -re "type = class Foo \{${ws}public:${ws}int x;${ws}int y;${ws}static int st;((${ws}Foo & operator=\\(Foo const ?&\\);)|(${ws}Foo\\(Foo const ?&\\);)|(${ws}Foo\\(int, int\\);)|(${ws}int operator!\\((void|)\\);)|(${ws}int operator int\\((void|)\\);)|(${ws}int times\\(int\\);))*${ws}\}$nl$gdb_prompt $" { + pass "ptype class Foo (obsolescent gcc or gdb)" + } + -re ".*$gdb_prompt $" { + fail "ptype class Foo" + } + timeout { + fail "ptype class Foo (timeout)" + return + } + } + + send_gdb "ptype class Bar\n" + gdb_expect { + -re "type = class Bar : public Base1, public Foo \{${ws}public:${ws}int z;${ws}Bar & operator=\\(Bar const ?&\\);${ws}Bar\\((Bar const|const Bar) ?&\\);${ws}Bar\\(int, int, int\\);${ws}\}$nl$gdb_prompt $" { + pass "ptype class Bar" + } + -re "type = class Bar : public Base1, public Foo \{${ws}public:${ws}int z;((${ws}Bar & operator=\\(Bar const ?&\\);)|(${ws}Bar\\(Bar const ?&\\);)|(${ws}Bar\\(int, int, int\\);))*${ws}\}$nl$gdb_prompt $" { + pass "ptype class Bar (obsolescent gcc or gdb)" + } + -re ".*$gdb_prompt $" { + fail "ptype class Bar" + } + timeout { + fail "ptype class Bar (timeout)" + return + } + } +} + +# +# Test simple access to class members. +# + +proc test_non_inherited_member_access {} { + global gdb_prompt + + # Print non-inherited members of g_A. + + gdb_test "print g_A.a" ".* = 1" "g_A.a incorrect" + + gdb_test "print g_A.x" ".* = 2" "g_A.x incorrect" + + # Print non-inherited members of g_B. + + gdb_test "print g_B.b" ".* = 5" "g_B.b incorrect" + + gdb_test "print g_B.x" ".* = 6" "g_B.x incorrect" + + # Print non-inherited members of g_C. + + gdb_test "print g_C.c" ".* = 9" "g_C.c incorrect" + + gdb_test "print g_C.x" ".* = 10" "g_C.x incorrect" + + # Print non-inherited members of g_D. + + gdb_test "print g_D.d" ".* = 19" "g_D.d incorrect" + + gdb_test "print g_D.x" ".* = 20" "g_D.x incorrect" + + # Print non-inherited members of g_E. + + gdb_test "print g_E.e" ".* = 31" "g_E.e incorrect" + + gdb_test "print g_E.x" ".* = 32" "g_E.x incorrect" +} + +# +# Try access to non-members that are members of another class. +# Should give errors. +# + +proc test_wrong_class_members {} { + global gdb_prompt + + gdb_test "print g_A.b" "There is no member( or method|) named b." "print g_A.b should be error" + + gdb_test "print g_B.c" "There is no member( or method|) named c." "print g_B.c should be error" + + gdb_test "print g_B.d" "There is no member( or method|) named d." "print g_B.d should be error" + + gdb_test "print g_C.b" "There is no member( or method|) named b." "print g_C.b should be error" + + gdb_test "print g_C.d" "There is no member( or method|) named d." "print g_C.d should be error" + + gdb_test "print g_D.e" "There is no member( or method|) named e." "print g_D.e should be error" +} + +# +# Try access to non-members that are not members of any class. +# Should give errors. +# + +proc test_nonexistent_members {} { + global gdb_prompt + + gdb_test "print g_A.y" "There is no member( or method|) named y." "print g_A.y should be error" + + gdb_test "print g_B.z" "There is no member( or method|) named z." "print g_B.z should be error" + + gdb_test "print g_C.q" "There is no member( or method|) named q." "print g_C.q should be error" + + gdb_test "print g_D.p" "There is no member( or method|) named p." "print g_D.p should be error" +} + +# +# Call a method that expects a base class parameter with base, inherited, +# and unrelated class arguments. +# + +proc test_method_param_class {} { + gdb_test "call class_param.Aptr_a (&g_A)" ".* = 1" "base class param->a" + gdb_test "call class_param.Aptr_x (&g_A)" ".* = 2" "base class param->x" + gdb_test "call class_param.Aptr_a (&g_B)" ".* = 3" "inherited class param->a" + gdb_test "call class_param.Aptr_x (&g_B)" ".* = 4" "inherited class param->x" + gdb_test "call class_param.Aref_a (g_A)" ".* = 1" "base class (¶m)->a" + gdb_test "call class_param.Aref_x (g_A)" ".* = 2" "base class (¶m)->x" + gdb_test "call class_param.Aref_a (g_B)" ".* = 3" "inherited class (¶m)->a" + gdb_test "call class_param.Aref_x (g_B)" ".* = 4" "inherited class (¶m)->x" + gdb_test "call class_param.Aval_a (g_A)" ".* = 1" "base class param.a" + gdb_test "call class_param.Aval_x (g_A)" ".* = 2" "base class param.x" + gdb_test "call class_param.Aval_a (g_B)" ".* = 3" "inherited class param.a" + gdb_test "call class_param.Aval_x (g_B)" ".* = 4" "inherited class param.x" + + gdb_test "call class_param.Aptr_a (&foo)" "Cannot resolve .*" "unrelated class *param" + gdb_test "call class_param.Aref_a (foo)" "Cannot resolve .*" "unrelated class ¶m" + gdb_test "call class_param.Aval_a (foo)" "Cannot resolve .*" "unrelated class param" +} + +# +# Examine a class with an enum field. +# + +proc test_enums {} { + global gdb_prompt + global hp_aCC_compiler + + # print the object + send_gdb "print obj_with_enum\n" + gdb_expect { + -re "\\$\[0-9\]* = \\{priv_enum = red, x = 0\\}.*$gdb_prompt $" { pass "print obj_with_enum (1)" } + -re "$gdb_prompt $" { fail "print obj_with_enum (1)" } + timeout { fail "(timeout) print obj_with_enum (1)" } + } + + send_gdb "next\n" + gdb_expect { + -re "$gdb_prompt $" { pass "next" } + timeout { fail "(timeout) next" } + } + + # print the object again + send_gdb "print obj_with_enum\n" + gdb_expect { + -re "\\$\[0-9\]* = \\{priv_enum = green, x = 0\\}.*$gdb_prompt $" { pass "print obj_with_enum (2)" } + -re "$gdb_prompt $" { fail "print obj_with_enum (2)" } + timeout { fail "(timeout) print obj_with_enum (2)" } + } + + # print out the enum member + send_gdb "print obj_with_enum.priv_enum\n" + gdb_expect { + -re "\\$\[0-9\]* = green.*$gdb_prompt $" { pass "print obj_with_enum.priv_enum" } + -re "$gdb_prompt $" { fail "print obj_with_enum.priv_enum" } + timeout { fail "(timeout) print obj_with_enum.priv_enum" } + } + + # ptype on the enum member + # The third success case is a little dubious, but it's not clear what + # ought to be required of a ptype on a private enum... -sts 19990324 + send_gdb "ptype obj_with_enum.priv_enum\n" + gdb_expect { + -re "type = enum ClassWithEnum::PrivEnum \\{red, green, blue, yellow = 42\\}.*$gdb_prompt $" { pass "ptype obj_with_enum.priv_enum" } + -re "type = enum PrivEnum \\{red, green, blue, yellow = 42\\}.*$gdb_prompt $" { pass "ptype obj_with_enum.priv_enum" } + -re "type = enum \\{red, green, blue, yellow = 42\\}.*$gdb_prompt $" { pass "ptype obj_with_enum.priv_enum" } + -re "$gdb_prompt $" { fail "ptype obj_with_enum.priv_enum" } + timeout { fail "(timeout) ptype obj_with_enum.priv_enum" } + } + + # ptype on the object + send_gdb "ptype obj_with_enum\n" + gdb_expect { + -re "type = class ClassWithEnum \\{\r\n\[ \t\]*public:\r\n\[ \t\]*(enum |)ClassWithEnum::PrivEnum priv_enum;\r\n\[ \t\]*int x;\r\n\\}\r\n$gdb_prompt $" { pass "ptype obj_with_enum" } + -re "type = class ClassWithEnum \\{\r\n\[ \t\]*public:\r\n\[ \t\]*(enum |)PrivEnum priv_enum;\r\n\[ \t\]*int x;.*\\}\r\n$gdb_prompt $" + { + # NOTE: carlton/2003-02-28: One could certainly argue that + # this output is acceptable: PrivEnum is a member of + # ClassWithEnum, so there's no need to explicitly qualify + # its name with "ClassWithEnum::". The truth, though, is + # that GDB is simply forgetting that PrivEnum is a member + # of ClassWithEnum, so we do that output for a bad reason + # instead of a good reason. Under stabs, we probably + # can't get this right; under DWARF-2, we can. + kfail "gdb/57" "ptype obj_with_enum" + } + -re "$gdb_prompt $" { fail "ptype obj_with_enum" } + timeout { fail "(timeout) ptype obj_with_enum" } + } + + # We'll do this test twice, because of a parser bug: see + # PR gdb/826. + + send_gdb "print (ClassWithEnum::PrivEnum) 42\n" + gdb_expect { + -re "\\$\[0-9\]* = yellow.*$gdb_prompt $" { pass "print (ClassWithEnum::PrivEnum) 42" } + -re "A parse error in expression, near `42'.\r\n$gdb_prompt $" { + # bison 1.35 + kfail "gdb/826" "print (ClassWithEnum::PrivEnum) 42" + } + -re "A syntax error in expression, near `42'.\r\n$gdb_prompt $" { + # bison 1.875 + kfail "gdb/826" "print (ClassWithEnum::PrivEnum) 42" + } + -re "$gdb_prompt $" { fail "print (ClassWithEnum::PrivEnum) 42" } + timeout { fail "(timeout) print (ClassWithEnum::PrivEnum) 42" } + } + + send_gdb "print ('ClassWithEnum::PrivEnum') 42\n" + gdb_expect { + -re "\\$\[0-9\]* = yellow.*$gdb_prompt $" { pass "print ('ClassWithEnum::PrivEnum') 42" } + -re "No symbol \"ClassWithEnum::PrivEnum\" in current context.\r\n$gdb_prompt $" + { kfail "gdb/57" "print ('ClassWithEnum::PrivEnum') 42" } + -re "$gdb_prompt $" { fail "print ('ClassWithEnum::PrivEnum') 42" } + timeout { fail "(timeout) print ('ClassWithEnum::PrivEnum') 42" } + } +} + +# +# Pointers to class members +# + +proc test_pointers_to_class_members {} { + global gdb_prompt + global decimal + global nl + + gdb_test "print Bar::z" ".* = .int\[ \]*\[( \]*Bar::&\[)\]+\[ \]*Bar::z" "print Bar::z" + + gdb_test "print &Foo::x" ".* = .int\[ \]*\[( \]*Foo::\[*)\]+\[ \]*&Foo::x" "print &Foo::x" + + gdb_test "print (int)&Foo::x" ".* = 0" "print (int)&Foo::x" + + send_gdb "print (int)&Bar::y == 2*sizeof(int)\n" + gdb_expect { + -re ".* = true$nl$gdb_prompt $" { + pass "print (int)&Bar::y == 2*sizeof(int)" + } + -re "There is no field named y.*$gdb_prompt $" { + setup_xfail "*-*-*" + fail "print (int)&Bar::y == 2*sizeof(int)" + } + -re ".*$gdb_prompt $" { fail "print (int)&Bar::y == 2*sizeof(int)" } + timeout { fail "print (int)&Bar::y == 2*sizeof(int) (timeout)" ; return } + } + + send_gdb "next 2\n" + setup_xfail "*-*-*" + gdb_expect { + -re "$decimal\[ \t\]+inheritance3 \[)(\]+;$nl$gdb_prompt $" {} + -re ".*$gdb_prompt $" { fail "next to inheritance3" ; return } + } + clear_xfail "*-*-*" + + gdb_test "print (int)pmi == sizeof(int)" ".* = false" "print (int)pmi == sizeof(int)" +} + +# +# Test static members. +# + +proc test_static_members {} { + global gdb_prompt + global hex + global nl + + send_gdb "print Foo::st\n" + gdb_expect { + -re ".* = 100$nl$gdb_prompt $" { + pass "print Foo::st" + } + -re "There is no field named st.*$gdb_prompt $" { + setup_xfail "*-*-*" + fail "print Foo::st" + } + -re ".*$gdb_prompt $" { fail "print Foo::st" } + timeout { fail "print Foo::st (timeout)" ; return } + } + + send_gdb "set foo.st = 200\n" + gdb_expect { + -re ".*$gdb_prompt $" {} + } + + send_gdb "print bar.st\n" + gdb_expect { + -re ".* = 200$nl$gdb_prompt $" { + pass "print bar.st" + } + -re "There is no member( or method|) named st.*$gdb_prompt $" { + setup_xfail "*-*-*" + fail "print bar.st" + } + -re ".*$gdb_prompt $" { fail "print bar.st" } + timeout { fail "print bar.st (timeout)" ; return } + } + + send_gdb "print &foo.st\n" + gdb_expect { + -re ".* = .int \[*)\]+ $hex$nl$gdb_prompt $" { + pass "print &foo.st" + } + -re "There is no member( or method|) named st.*$gdb_prompt $" { + setup_xfail "*-*-*" + fail "print &foo.st" + } + -re ".*$gdb_prompt $" { fail "print &foo.st" } + timeout { fail "print &foo.st (timeout)" ; return } + } + + set got_bar_st 0 + send_gdb "print &Bar::st\n" + gdb_expect { + -re ".* = .int \[*)\]+ $hex$nl$gdb_prompt $" { + pass "print &Bar::st" + set got_bar_st 1 + } + -re "There is no field named st.*$gdb_prompt $" { + setup_xfail "*-*-*" + fail "print &Bar::st" + } + -re ".*$gdb_prompt $" { fail "print &Bar::st" } + timeout { fail "print &Bar::st (timeout)" ; return } + } + + if $got_bar_st then { + gdb_test "print *\$" ".* = 200" "print *\$" + } + + gdb_test "set print static-members off" "" + gdb_test "print csi" \ + "{x = 10, y = 20}" \ + "print csi without static members" + gdb_test "print cnsi" \ + "{x = 30, y = 40}" \ + "print cnsi without static members" + + gdb_test "set print static-members on" "" + gdb_test "print csi" \ + "{x = 10, y = 20, static null = {x = 0, y = 0, static null = }}" \ + "print csi with static members" + gdb_test "print cnsi" \ + "{x = 30, y = 40, static null = {x = 0, y = 0, static null = , static yy = {z = 5, static xx = {x = 1, y = 2, static null = , static yy = }}}, static yy = }" \ + "print cnsi with static members" +} + +proc do_tests {} { + global prms_id + global bug_id + global subdir + global objdir + global srcdir + global binfile + global gdb_prompt + + set prms_id 0 + set bug_id 0 + + # Start with a fresh gdb. + + gdb_exit + gdb_start + gdb_reinitialize_dir $srcdir/$subdir + gdb_load $binfile + + send_gdb "set language c++\n" + gdb_expect -re "$gdb_prompt $" + send_gdb "set width 0\n" + gdb_expect -re "$gdb_prompt $" + + runto_main + test_ptype_class_objects + + if [ runto 'inheritance2' ] then { + test_non_inherited_member_access + test_wrong_class_members + test_nonexistent_members + test_method_param_class + } + + gdb_breakpoint enums2 + if [ gdb_continue "enums2(\\(\\)|)" ]==0 then { + gdb_test "finish" "" "" + test_enums + } + + if [istarget "mips-idt-*"] then { + # Restart because IDT/SIM runs out of file descriptors. + gdb_exit + gdb_start + gdb_reinitialize_dir $srcdir/$subdir + gdb_load $binfile + } + + if [ runto_main ] then { + test_pointers_to_class_members + test_static_members + } + + if [istarget "mips-idt-*"] then { + # Restart because IDT/SIM runs out of file descriptors. + gdb_exit + gdb_start + gdb_reinitialize_dir $srcdir/$subdir + gdb_load $binfile + } + + if [ runto marker_reg1 ] then { + + gdb_test "finish" "Run till exit from.*" "finish from marker_reg1" + + send_gdb "print v.method ()\n" + gdb_expect { + -re "= 82.*$gdb_prompt $" { + pass "calling method for small class" + } + -re "Address requested for identifier .v. which is in register.*$gdb_prompt $" { + setup_xfail "*-*-*" 2972 + fail "calling method for small class" + } + -re ".*$gdb_prompt $" { fail "calling method for small class" } + timeout { fail "calling method for small class (timeout)" } + eof { fail "calling method for small class (eof)" } + } + } + +} + +do_tests + +send_gdb "maint demangle inheritance1__Fv\n" +gdb_expect { + -re "inheritance1\\(void\\).*$gdb_prompt $" { pass "demangle" } + -re ".*$gdb_prompt $" { fail "demangle" } + timeout { fail "(timeout) demangle" } +} diff --git a/gdb/testsuite/gdb.cp/cplusfuncs.cc b/gdb/testsuite/gdb.cp/cplusfuncs.cc new file mode 100644 index 0000000..7f033d6 --- /dev/null +++ b/gdb/testsuite/gdb.cp/cplusfuncs.cc @@ -0,0 +1,196 @@ +#include + +class foo { +public: + foo (int); + foo (int, const char *); + foo (foo&); + ~foo (); + + void operator * (foo&); + void operator % (foo&); + void operator - (foo&); + void operator >> (foo&); + void operator != (foo&); + void operator > (foo&); + void operator >= (foo&); + void operator | (foo&); + void operator && (foo&); + void operator ! (void); + void operator ++ (int); + void operator = (foo&); + void operator += (foo&); + void operator *= (foo&); + void operator %= (foo&); + void operator >>= (foo&); + void operator |= (foo&); + void operator , (foo&); + void operator / (foo&); + void operator + (foo&); + void operator << (foo&); + void operator == (foo&); + void operator < (foo&); + void operator <= (foo&); + void operator & (foo&); + void operator ^ (foo&); + void operator || (foo&); + void operator ~ (void); + void operator -- (int); + foo* operator -> (void); + void operator -= (foo&); + void operator /= (foo&); + void operator <<= (foo&); + void operator &= (foo&); + void operator ^= (foo&); + void operator ->* (foo&); + void operator [] (foo&); + void operator () (foo&); + void* operator new (size_t) throw (); + void operator delete (void *); + /**/ operator int (); + /**/ operator char* (); + + int foofunc (int); // forced to have int return type, which is required + int foofunc (int, signed char *); // forced to have int return type, which is required + int ifoo; + const char *ccpfoo; +}; + +#ifdef usestubs +extern "C" { + void set_debug_traps(); + void breakpoint(); +}; +#endif + +int main () { +#ifdef usestubs + set_debug_traps(); + breakpoint(); +#endif + int z=3; +} + +foo::foo (int i) { ifoo = i;} +foo::foo (int i, const char *ccp) { ifoo = i; ccpfoo = ccp; } +foo::foo (foo& afoo) { afoo.ifoo = 0; } +foo::~foo () {} + +void foo::operator * (foo& afoo) { afoo.ifoo = 0; } +void foo::operator % (foo& afoo) { afoo.ifoo = 0; } +void foo::operator - (foo& afoo) { afoo.ifoo = 0; } +void foo::operator >> (foo& afoo) { afoo.ifoo = 0; } +void foo::operator != (foo& afoo) { afoo.ifoo = 0; } +void foo::operator > (foo& afoo) { afoo.ifoo = 0; } +void foo::operator >= (foo& afoo) { afoo.ifoo = 0; } +void foo::operator | (foo& afoo) { afoo.ifoo = 0; } +void foo::operator && (foo& afoo) { afoo.ifoo = 0; } +void foo::operator ! (void) {} +void foo::operator ++ (int ival) { ival = 0; } +void foo::operator = (foo& afoo) { afoo.ifoo = 0; } +void foo::operator += (foo& afoo) { afoo.ifoo = 0; } +void foo::operator *= (foo& afoo) { afoo.ifoo = 0; } +void foo::operator %= (foo& afoo) { afoo.ifoo = 0; } +void foo::operator >>= (foo& afoo) { afoo.ifoo = 0; } +void foo::operator |= (foo& afoo) { afoo.ifoo = 0; } +void foo::operator , (foo& afoo) { afoo.ifoo = 0; } +void foo::operator / (foo& afoo) { afoo.ifoo = 0; } +void foo::operator + (foo& afoo) { afoo.ifoo = 0; } +void foo::operator << (foo& afoo) { afoo.ifoo = 0; } +void foo::operator == (foo& afoo) { afoo.ifoo = 0; } +void foo::operator < (foo& afoo) { afoo.ifoo = 0; } +void foo::operator <= (foo& afoo) { afoo.ifoo = 0; } +void foo::operator & (foo& afoo) { afoo.ifoo = 0; } +void foo::operator ^ (foo& afoo) { afoo.ifoo = 0; } +void foo::operator || (foo& afoo) { afoo.ifoo = 0; } +void foo::operator ~ (void) {} +void foo::operator -- (int ival) { ival = 0; } +foo* foo::operator -> (void) {return this;} +void foo::operator -= (foo& afoo) { afoo.ifoo = 0; } +void foo::operator /= (foo& afoo) { afoo.ifoo = 0; } +void foo::operator <<= (foo& afoo) { afoo.ifoo = 0; } +void foo::operator &= (foo& afoo) { afoo.ifoo = 0; } +void foo::operator ^= (foo& afoo) { afoo.ifoo = 0; } +void foo::operator ->* (foo& afoo) { afoo.ifoo = 0; } +void foo::operator [] (foo& afoo) { afoo.ifoo = 0; } +void foo::operator () (foo& afoo) { afoo.ifoo = 0; } +void* foo::operator new (size_t ival) throw () { ival = 0; return 0; } +void foo::operator delete (void *ptr) { ptr = 0; } +/**/ foo::operator int () { return 0; } +/**/ foo::operator char* () { return 0; } + +/* Some functions to test overloading by varying one argument type. */ + +void overload1arg (void) { } +void overload1arg (char arg) { arg = 0; } +void overload1arg (signed char arg) { arg = 0; } +void overload1arg (unsigned char arg) { arg = 0; } +void overload1arg (short arg) { arg = 0; } +void overload1arg (unsigned short arg) { arg = 0; } +void overload1arg (int arg) { arg = 0; } +void overload1arg (unsigned int arg) { arg = 0; } +void overload1arg (long arg) { arg = 0; } +void overload1arg (unsigned long arg) { arg = 0; } +void overload1arg (float arg) { arg = 0; } +void overload1arg (double arg) { arg = 0; } + +/* Some functions to test overloading by varying argument count. */ + +void overloadargs (int a1) { a1 = 0; } +void overloadargs (int a1, int a2) { a1 = a2 = 0; } +void overloadargs (int a1, int a2, int a3) { a1 = a2 = a3 = 0; } +void overloadargs (int a1, int a2, int a3, int a4) + { a1 = a2 = a3 = a4 = 0; } +void overloadargs (int a1, int a2, int a3, int a4, int a5) + { a1 = a2 = a3 = a4 = a5 = 0; } +void overloadargs (int a1, int a2, int a3, int a4, int a5, int a6) + { a1 = a2 = a3 = a4 = a5 = a6 = 0; } +void overloadargs (int a1, int a2, int a3, int a4, int a5, int a6, int a7) + { a1 = a2 = a3 = a4 = a5 = a6 = a7 = 0; } +void overloadargs (int a1, int a2, int a3, int a4, int a5, int a6, int a7, + int a8) + { a1 = a2 = a3 = a4 = a5 = a6 = a7 = a8 = 0; } +void overloadargs (int a1, int a2, int a3, int a4, int a5, int a6, int a7, + int a8, int a9) + { a1 = a2 = a3 = a4 = a5 = a6 = a7 = a8 = a9 = 0; } +void overloadargs (int a1, int a2, int a3, int a4, int a5, int a6, int a7, + int a8, int a9, int a10) + { a1 = a2 = a3 = a4 = a5 = a6 = a7 = a8 = a9 = + a10 = 0; } +void overloadargs (int a1, int a2, int a3, int a4, int a5, int a6, int a7, + int a8, int a9, int a10, int a11) + { a1 = a2 = a3 = a4 = a5 = a6 = a7 = a8 = a9 = + a10 = a11 == 0; } + +/* Some hairy function definitions. + Use typedefs to help maintain sanity. */ + +typedef int (*PFPc_i)(char *); +typedef short (*PFPl_s)(long *); +typedef short (*PFPc_s)(char *); +typedef int (*PFl_i)(long); +typedef PFl_i (*PFPc_PFl_i)(char *); +typedef PFl_i (*PFPi_PFl_i)(int *); +typedef PFl_i (*PFPFPc_i_PFl_i)(PFPc_i); +typedef PFl_i (*PFs_PFl_i)(short); +typedef int (*PFPFPl_s_i)(PFPl_s); +typedef int (*PFPFPc_s_i)(PFPc_s); + +PFs_PFl_i hairyfunc1 (int arg) { arg = 0; return 0; } +int hairyfunc2 (PFPc_i arg) { arg = 0; return 0; } +int hairyfunc3 (PFPFPl_s_i arg) { arg = 0; return 0; } +int hairyfunc4 (PFPFPc_s_i arg) { arg = 0; return 0; } +int hairyfunc5 (PFPc_PFl_i arg) { arg = 0; return 0; } +int hairyfunc6 (PFPi_PFl_i arg) { arg = 0; return 0; } +int hairyfunc7 (PFPFPc_i_PFl_i arg) { arg = 0; return 0; } + +/* gdb has two demanglers (one for g++ 2.95, one for g++ 3). + These marker functions help me figure out which demangler is in use. */ + +char * dm_type_char_star (char * p) { return p; } +int dm_type_foo_ref (foo & foo) { return foo.ifoo; } +int * dm_type_int_star (int * p) { return p; } +long * dm_type_long_star (long * p) { return p; } +int dm_type_unsigned_int (unsigned int i) { return i; } +int dm_type_void (void) { return 0; } +void * dm_type_void_star (void * p) { return p; } diff --git a/gdb/testsuite/gdb.cp/cplusfuncs.exp b/gdb/testsuite/gdb.cp/cplusfuncs.exp new file mode 100644 index 0000000..0a5e1b3 --- /dev/null +++ b/gdb/testsuite/gdb.cp/cplusfuncs.exp @@ -0,0 +1,564 @@ +# Copyright 1992, 1997, 1999, 2001, 2002, 2003 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# Please email any bugs, comments, and/or additions to this file to: +# bug-gdb@prep.ai.mit.edu + +# This file was written by Fred Fish. (fnf@cygnus.com) +# Adapted for g++ 3.0 ABI by Michael Chastain. (chastain@redhat.com) + +if $tracelevel then { + strace $tracelevel +} + +if { [skip_cplus_tests] } { continue } + +set testfile "cplusfuncs" +set srcfile ${testfile}.cc +set binfile ${objdir}/${subdir}/${testfile} + +if { [get_compiler_info $binfile "c++"] } { + return -1 +} + +if { [gdb_compile "${srcdir}/${subdir}/${srcfile}" "${binfile}" executable {debug c++}] != "" } { + gdb_suppress_entire_file "Testcase compile failed, so all tests in this file will automatically fail." +} + +# +# g++ changed its ABI between 2.95 and 3.0. gdb has two demanglers +# for the two different styles. The two demanglers have some subtle +# discrepancies in their output. +# +# old demangler new demangler +# --- --------- --- --------- +# "operator, " "operator," +# "char *" "char*" +# "int *" "int*" +# "long *" "long*" +# "void *" "void*" +# "foo &" "foo&" +# "unsigned int" "unsigned" +# "void" "" +# +# I probe for the forms in use. +# The defaults are for the v3 demangler (as of 2001-02-13). +# + +set dm_operator_comma "," +set dm_type_char_star "char*" +set dm_type_char_star_quoted "char\\*" +set dm_type_foo_ref "foo&" +set dm_type_int_star "int*" +set dm_type_long_star "long*" +set dm_type_unsigned_int "unsigned" +set dm_type_void "" +set dm_type_void_star "void*" + +proc probe_demangler { } { + global gdb_prompt + global dm_operator_comma + global dm_type_char_star + global dm_type_char_star_quoted + global dm_type_foo_ref + global dm_type_int_star + global dm_type_long_star + global dm_type_unsigned_int + global dm_type_void + global dm_type_void_star + + send_gdb "print &'foo::operator,(foo&)'\n" + gdb_expect { + -re ".*foo::operator, \\(.*foo.*&.*\\).*\r\n$gdb_prompt $" { + # v2 demangler + set dm_operator_comma ", " + pass "detect dm_operator_comma" + } + -re ".*foo::operator,\\(.*foo.*&.*\\).*\r\n$gdb_prompt $" { + # v3 demangler + pass "detect dm_operator_comma" + } + -re ".*$gdb_prompt $" { + fail "detect dm_operator_comma" + } + timeout { + fail "detect dm_operator_comma" + } + } + + send_gdb "print &'dm_type_char_star'\n" + gdb_expect { + -re ".*dm_type_char_star\\(char \\*\\).*\r\n$gdb_prompt $" { + # v2 demangler + set dm_type_char_star "char *" + set dm_type_char_star_quoted "char \\*" + pass "detect dm_type_char_star" + } + -re ".*dm_type_char_star\\(char\\*\\).*\r\n$gdb_prompt $" { + # v3 demangler + pass "detect dm_type_char_star" + } + -re ".*$gdb_prompt $" { + fail "detect dm_type_char_star" + } + timeout { + fail "detect dm_type_char_star (timeout)" + } + } + + send_gdb "print &'dm_type_foo_ref'\n" + gdb_expect { + -re ".*dm_type_foo_ref\\(foo &\\).*\r\n$gdb_prompt $" { + # v2 demangler + set dm_type_foo_ref "foo &" + pass "detect dm_type_foo_ref" + } + -re ".*dm_type_foo_ref\\(foo&\\).*\r\n$gdb_prompt $" { + # v3 demangler + pass "detect dm_type_foo_ref" + } + -re ".*$gdb_prompt $" { + fail "detect dm_type_foo_ref" + } + timeout { + fail "detect dm_type_foo_ref (timeout)" + } + } + + send_gdb "print &'dm_type_int_star'\n" + gdb_expect { + -re ".*dm_type_int_star\\(int \\*\\).*\r\n$gdb_prompt $" { + # v2 demangler + set dm_type_int_star "int *" + pass "detect dm_type_int_star" + } + -re ".*dm_type_int_star\\(int\\*\\).*\r\n$gdb_prompt $" { + # v3 demangler + pass "detect dm_type_int_star" + } + -re ".*$gdb_prompt $" { + fail "detect dm_type_int_star" + } + timeout { + fail "detect dm_type_int_star (timeout)" + } + } + + send_gdb "print &'dm_type_long_star'\n" + gdb_expect { + -re ".*dm_type_long_star\\(long \\*\\).*\r\n$gdb_prompt $" { + # v2 demangler + set dm_type_long_star "long *" + pass "detect dm_type_long_star" + } + -re ".*dm_type_long_star\\(long\\*\\).*\r\n$gdb_prompt $" { + # v3 demangler + pass "detect dm_type_long_star" + } + -re ".*$gdb_prompt $" { + fail "detect dm_type_long_star" + } + timeout { + fail "detect dm_type_long_star (timeout)" + } + } + + send_gdb "print &'dm_type_unsigned_int'\n" + gdb_expect { + -re ".*dm_type_unsigned_int\\(unsigned int\\).*\r\n$gdb_prompt $" { + # v2 demangler + set dm_type_unsigned_int "unsigned int" + pass "detect dm_type_unsigned_int" + } + -re ".*dm_type_unsigned_int\\(unsigned\\).*\r\n$gdb_prompt $" { + # v3 demangler + pass "detect dm_type_unsigned_int" + } + -re ".*$gdb_prompt $" { + fail "detect dm_type_unsigned_int" + } + timeout { + fail "detect dm_unsigned int (timeout)" + } + } + + send_gdb "print &'dm_type_void'\n" + gdb_expect { + -re ".*dm_type_void\\(void\\).*\r\n$gdb_prompt $" { + # v2 demangler + set dm_type_void "void" + pass "detect dm_type_void" + } + -re ".*dm_type_void\\(\\).*\r\n$gdb_prompt $" { + # v3 demangler + pass "detect dm_type_void" + } + -re ".*$gdb_prompt $" { + fail "detect dm_type_void" + } + timeout { + fail "detect dm_type_void (timeout)" + } + } + + send_gdb "print &'dm_type_void_star'\n" + gdb_expect { + -re ".*dm_type_void_star\\(void \\*\\).*\r\n$gdb_prompt $" { + # v2 demangler + set dm_type_void_star "void *" + pass "detect dm_type_void_star" + } + -re ".*dm_type_void_star\\(void\\*\\).*\r\n$gdb_prompt $" { + # v3 demangler + pass "detect dm_type_void_star" + } + -re ".*$gdb_prompt $" { + fail "detect dm_type_void_star" + } + timeout { + fail "detect dm_type_void_star (timeout)" + } + } +} + +# +# Lookup a specific C++ function and print the demangled type. +# This form accepts the demangled type as a regexp. +# + +proc info_func_regexp { name demangled } { + global gdb_prompt + + send_gdb "info function $name\n" + gdb_expect { + -re ".*File .*:\r\n(class |)$demangled\r\n.*$gdb_prompt $" { + pass "info function for \"$name\"" + } + -re ".*$gdb_prompt $" { + fail "info function for \"$name\"" + } + timeout { + fail "info function for \"$name\" (timeout)" + } + } +} + +# +# Lookup a specific C++ function and print the demangled type. +# This form accepts the demangled type as a literal string. +# + +proc info_func { name demangled } { + info_func_regexp "$name" [string_to_regexp "$demangled"] +} + +# +# Print the address of a function. +# This checks that I can lookup a fully qualified C++ function. +# This also checks the argument types on the return string. + +# Note: carlton/2003-01-16: If you modify this, make a corresponding +# modification to print_addr_2_kfail. + +proc print_addr_2 { name good } { + global gdb_prompt + global hex + + set good_pattern [string_to_regexp $good] + + send_gdb "print &'$name'\n" + gdb_expect { + -re ".* = .* $hex <$good_pattern>\r\n$gdb_prompt $" { + pass "print &'$name'" + } + -re ".*$gdb_prompt $" { + fail "print &'$name'" + } + timeout { + fail "print &'$name' (timeout)" + } + } +} + +# NOTE: carlton/2003-01-16: hairyfunc5-6 fail on GCC 3.x (for at least +# x=1 and x=2.1). So I'm modifying print_addr_2 to accept a failure +# condition. FIXME: It would be nice if the failure condition were +# conditional on the compiler version, but I'm not sufficiently +# motivated. I did hardwire in the versions of char * and int *, +# which will give some compiler-specificity to the failure. + +proc print_addr_2_kfail { name good bad bugid } { + global gdb_prompt + global hex + + set good_pattern [string_to_regexp $good] + set bad_pattern [string_to_regexp $bad] + + send_gdb "print &'$name'\n" + gdb_expect { + -re ".* = .* $hex <$good_pattern>\r\n$gdb_prompt $" { + pass "print &'$name'" + } + -re ".* = .* $hex <$bad_pattern>\r\n$gdb_prompt $" { + kfail $bugid "print &'$name'" + } + -re ".*$gdb_prompt $" { + fail "print &'$name'" + } + timeout { + fail "print &'$name' (timeout)" + } + } +} + +# +# Simple interfaces to print_addr_2. +# + +proc print_addr { name } { + print_addr_2 "$name" "$name" +} + +# +# Test name demangling for operators. +# +# The '(' at the end of each regex input pattern is so that we match only +# the one we are looking for. I.E. "operator&" would match both +# "operator&(foo &)" and "operator&&(foo &)". +# +# gdb-gnats bug gdb/18: +# "gdb can't parse "info func operator*" or "info func operator\*". +# The star in "operator*" is interpreted as a regexp, but the "\*" +# in "operator\*" is not a legal operator. +# + +proc test_lookup_operator_functions {} { + global dm_operator_comma + global dm_type_char_star + global dm_type_char_star_quoted + global dm_type_foo_ref + global dm_type_void + global dm_type_void_star + + # operator* requires quoting so that GDB does not treat it as a regexp. + info_func "operator\\*(" "void foo::operator*($dm_type_foo_ref);" + info_func "operator%(" "void foo::operator%($dm_type_foo_ref);" + info_func "operator-(" "void foo::operator-($dm_type_foo_ref);" + info_func "operator>>(" "void foo::operator>>($dm_type_foo_ref);" + info_func "operator!=(" "void foo::operator!=($dm_type_foo_ref);" + info_func "operator>(" "void foo::operator>($dm_type_foo_ref);" + info_func "operator>=(" "void foo::operator>=($dm_type_foo_ref);" + info_func "operator|(" "void foo::operator|($dm_type_foo_ref);" + info_func "operator&&(" "void foo::operator&&($dm_type_foo_ref);" + info_func "operator!(" "void foo::operator!($dm_type_void);" + info_func "operator++(" "void foo::operator++(int);" + info_func "operator=(" "void foo::operator=($dm_type_foo_ref);" + info_func "operator+=(" "void foo::operator+=($dm_type_foo_ref);" + # operator*= requires quoting so that GDB does not treat it as a regexp. + info_func "operator\\*=(" "void foo::operator*=($dm_type_foo_ref);" + info_func "operator%=(" "void foo::operator%=($dm_type_foo_ref);" + info_func "operator>>=(" "void foo::operator>>=($dm_type_foo_ref);" + info_func "operator|=(" "void foo::operator|=($dm_type_foo_ref);" + info_func "operator$dm_operator_comma\(" \ + "void foo::operator$dm_operator_comma\($dm_type_foo_ref);" + info_func "operator/(" "void foo::operator/($dm_type_foo_ref);" + info_func "operator+(" "void foo::operator+($dm_type_foo_ref);" + info_func "operator<<(" "void foo::operator<<($dm_type_foo_ref);" + info_func "operator==(" "void foo::operator==($dm_type_foo_ref);" + info_func "operator<(" "void foo::operator<($dm_type_foo_ref);" + info_func "operator<=(" "void foo::operator<=($dm_type_foo_ref);" + info_func "operator&(" "void foo::operator&($dm_type_foo_ref);" + info_func "operator^(" "void foo::operator^($dm_type_foo_ref);" + info_func "operator||(" "void foo::operator||($dm_type_foo_ref);" + info_func "operator~(" "void foo::operator~($dm_type_void);" + info_func "operator--(" "void foo::operator--(int);" + info_func "operator->(" "foo *foo::operator->($dm_type_void);" + info_func "operator-=(" "void foo::operator-=($dm_type_foo_ref);" + info_func "operator/=(" "void foo::operator/=($dm_type_foo_ref);" + info_func "operator<<=(" "void foo::operator<<=($dm_type_foo_ref);" + info_func "operator&=(" "void foo::operator&=($dm_type_foo_ref);" + info_func "operator^=(" "void foo::operator^=($dm_type_foo_ref);" + # operator->* requires quoting so that GDB does not treat it as a regexp. + info_func "operator->\\*(" "void foo::operator->*($dm_type_foo_ref);" + + # operator[] needs double backslashes, so that a single backslash + # will be sent to GDB, preventing the square brackets from being + # evaluated as a regular expression. + info_func "operator\\\[\\\](" "void foo::operator\[\]($dm_type_foo_ref);" + + # These are gnarly because they might end with 'static'. + set dm_type_void_star_regexp [string_to_regexp $dm_type_void_star] + info_func_regexp "operator new(" "void \\*foo::operator new\\(.*\\)(| static);" + info_func_regexp "operator delete(" "void foo::operator delete\\($dm_type_void_star_regexp\\)(| static);" + + info_func "operator int(" "int foo::operator int($dm_type_void);" + info_func "operator()(" "void foo::operator()($dm_type_foo_ref);" + info_func "operator $dm_type_char_star_quoted\(" \ + "char *foo::operator $dm_type_char_star\($dm_type_void);" + +} + + +proc test_paddr_operator_functions {} { + global hex + global hp_aCC_compiler + global dm_operator_comma + global dm_type_char_star + global dm_type_foo_ref + global dm_type_long_star + global dm_type_unsigned_int + global dm_type_void + global dm_type_void_star + + print_addr "foo::operator*($dm_type_foo_ref)" + print_addr "foo::operator%($dm_type_foo_ref)" + print_addr "foo::operator-($dm_type_foo_ref)" + print_addr "foo::operator>>($dm_type_foo_ref)" + print_addr "foo::operator!=($dm_type_foo_ref)" + print_addr "foo::operator>($dm_type_foo_ref)" + print_addr "foo::operator>=($dm_type_foo_ref)" + print_addr "foo::operator|($dm_type_foo_ref)" + print_addr "foo::operator&&($dm_type_foo_ref)" + print_addr "foo::operator!($dm_type_void)" + print_addr "foo::operator++(int)" + print_addr "foo::operator=($dm_type_foo_ref)" + print_addr "foo::operator+=($dm_type_foo_ref)" + print_addr "foo::operator*=($dm_type_foo_ref)" + print_addr "foo::operator%=($dm_type_foo_ref)" + print_addr "foo::operator>>=($dm_type_foo_ref)" + print_addr "foo::operator|=($dm_type_foo_ref)" + print_addr "foo::operator$dm_operator_comma\($dm_type_foo_ref)" + print_addr "foo::operator/($dm_type_foo_ref)" + print_addr "foo::operator+($dm_type_foo_ref)" + print_addr "foo::operator<<($dm_type_foo_ref)" + print_addr "foo::operator==($dm_type_foo_ref)" + print_addr "foo::operator<($dm_type_foo_ref)" + print_addr "foo::operator<=($dm_type_foo_ref)" + print_addr "foo::operator&($dm_type_foo_ref)" + print_addr "foo::operator^($dm_type_foo_ref)" + print_addr "foo::operator||($dm_type_foo_ref)" + print_addr "foo::operator~($dm_type_void)" + print_addr "foo::operator--(int)" + print_addr "foo::operator->($dm_type_void)" + print_addr "foo::operator-=($dm_type_foo_ref)" + print_addr "foo::operator/=($dm_type_foo_ref)" + print_addr "foo::operator<<=($dm_type_foo_ref)" + print_addr "foo::operator&=($dm_type_foo_ref)" + print_addr "foo::operator^=($dm_type_foo_ref)" + print_addr "foo::operator->*($dm_type_foo_ref)" + print_addr "foo::operator\[\]($dm_type_foo_ref)" + print_addr "foo::operator()($dm_type_foo_ref)" + + gdb_test "print &'foo::operator new'" \ + " = .* $hex " + if { !$hp_aCC_compiler } { + print_addr "foo::operator delete($dm_type_void_star)" + } else { + gdb_test "print &'foo::operator delete($dm_type_void_star) static'" \ + " = .*(0x\[0-9a-f\]+|) " + } + + print_addr "foo::operator int($dm_type_void)" + print_addr "foo::operator $dm_type_char_star\($dm_type_void)" +} + +# +# Test overloaded functions (1 arg). +# + +proc test_paddr_overloaded_functions {} { + global dm_type_unsigned_int + global dm_type_void + + print_addr "overload1arg($dm_type_void)" + print_addr "overload1arg(char)" + print_addr "overload1arg(signed char)" + print_addr "overload1arg(unsigned char)" + print_addr "overload1arg(short)" + print_addr "overload1arg(unsigned short)" + print_addr "overload1arg(int)" + print_addr "overload1arg($dm_type_unsigned_int)" + print_addr "overload1arg(long)" + print_addr "overload1arg(unsigned long)" + print_addr "overload1arg(float)" + print_addr "overload1arg(double)" + + print_addr "overloadargs(int)" + print_addr "overloadargs(int, int)" + print_addr "overloadargs(int, int, int)" + print_addr "overloadargs(int, int, int, int)" + print_addr "overloadargs(int, int, int, int, int)" + print_addr "overloadargs(int, int, int, int, int, int)" + print_addr "overloadargs(int, int, int, int, int, int, int)" + print_addr "overloadargs(int, int, int, int, int, int, int, int)" + print_addr "overloadargs(int, int, int, int, int, int, int, int, int)" + print_addr "overloadargs(int, int, int, int, int, int, int, int, int, int)" + print_addr "overloadargs(int, int, int, int, int, int, int, int, int, int, int)" +} + +proc test_paddr_hairy_functions {} { + global gdb_prompt + global hex + global dm_type_char_star + global dm_type_int_star + global dm_type_long_star + + print_addr_2 "hairyfunc1" "hairyfunc1(int)" + print_addr_2 "hairyfunc2" "hairyfunc2(int (*)($dm_type_char_star))" + print_addr_2 "hairyfunc3" "hairyfunc3(int (*)(short (*)($dm_type_long_star)))" + print_addr_2 "hairyfunc4" "hairyfunc4(int (*)(short (*)($dm_type_char_star)))" + + # gdb-gnats bug gdb/19: + # "gdb v3 demangler fails on hairyfunc5 hairyfunc6 hairyfunc7" + print_addr_2_kfail "hairyfunc5" "hairyfunc5(int (*(*)($dm_type_char_star))(long))" "hairyfunc5(int (*)(long) (*)(char*))" "gdb/19" + print_addr_2_kfail "hairyfunc6" "hairyfunc6(int (*(*)($dm_type_int_star))(long))" "hairyfunc6(int (*)(long) (*)(int*))" "gdb/19" + print_addr_2_kfail "hairyfunc7" "hairyfunc7(int (*(*)(int (*)($dm_type_char_star)))(long))" "hairyfunc7(int (*)(long) (*)(int (*)(char*)))" "gdb/19" +} + +proc do_tests {} { + global prms_id + global bug_id + global subdir + global objdir + global srcdir + global binfile + global gdb_prompt + + set prms_id 0 + set bug_id 0 + + # Start with a fresh gdb. + + gdb_exit + gdb_start + gdb_reinitialize_dir $srcdir/$subdir + gdb_load $binfile + + send_gdb "set language c++\n" + gdb_expect -re "$gdb_prompt $" + send_gdb "set width 0\n" + gdb_expect -re "$gdb_prompt $" + + runto_main + + probe_demangler + test_paddr_overloaded_functions + test_paddr_operator_functions + test_paddr_hairy_functions + test_lookup_operator_functions +} + +do_tests diff --git a/gdb/testsuite/gdb.cp/ctti.exp b/gdb/testsuite/gdb.cp/ctti.exp new file mode 100644 index 0000000..1bc005a --- /dev/null +++ b/gdb/testsuite/gdb.cp/ctti.exp @@ -0,0 +1,269 @@ +# Copyright 1998, 1999, 2001, 2003 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# Please email any bugs, comments, and/or additions to this file to: +# bug-gdb@prep.ai.mit.edu + + +# This file is part of the gdb testsuite +# file written by Elena Zannoni (ezannoni@cygnus.com) +# +# source files cttiadd.cc, cttiadd1.cc, cttiadd2.cc, cttiadd3.cc +# + + +if $tracelevel then { + strace $tracelevel +} + +if { [skip_cplus_tests] } { continue } + +# Check to see if we have an executable to test. If not, then either we +# haven't tried to compile one, or the compilation failed for some reason. +# In either case, just notify the user and skip the tests in this file. + +set testfile "cttiadd" +set srcfile ${testfile}.cc +set srcfile1 ${testfile}1.cc +set srcfile2 ${testfile}2.cc +set srcfile3 ${testfile}3.cc +set binfile ${objdir}/${subdir}/${testfile} + +if [get_compiler_info ${binfile} "c++"] { + return -1; +} + +if { [test_compiler_info gcc-*] } then { continue } + +#if { [gdb_compile "${srcdir}/${subdir}/${srcfile} ${srcdir}/${subdir}/${srcfile1} ${srcdir}/${subdir}/${srcfile2} ${srcdir}/${subdir}/${srcfile3}" "${binfile}" executable {debug c++}] != "" } { +# gdb_suppress_entire_file "Testcase compile failed, so all tests in this file will automatically fail." +#} + +set cmdline "$CXX_FOR_TARGET ${srcdir}/${subdir}/${srcfile} ${srcdir}/${subdir}/${srcfile1} ${srcdir}/${subdir}/${srcfile2} ${srcdir}/${subdir}/${srcfile3} -g -o ${binfile}" + +remote_exec build $cmdline + +gdb_exit +gdb_start +gdb_reinitialize_dir $srcdir/$subdir +gdb_load ${binfile} + + + +if ![runto_main] then { + perror "couldn't run to breakpoint" + continue +} + + +send_gdb "n\n" +gdb_expect { + -re "$decimal.*i = 2;.*$gdb_prompt $" { + pass "next " + } + -re ".*$gdb_prompt $" { fail "next " } + timeout { fail "next " } + } + + +send_gdb "n\n" +gdb_expect { + -re "$decimal.*f = 4.5;.*$gdb_prompt $" { + pass "next " + } + -re ".*$gdb_prompt $" { fail "next " } + timeout { fail "next " } + } + +send_gdb "n\n" +gdb_expect { + -re "$decimal.*c = add\\(c, c\\);.*$gdb_prompt $" { + pass "next " + } + -re ".*$gdb_prompt $" { fail "next " } + timeout { fail "next " } + } + +send_gdb "n\n" +gdb_expect { + -re "$decimal.*i = add\\(i, i\\);.*$gdb_prompt $" { + pass "next " + } + -re ".*$gdb_prompt $" { fail "next " } + timeout { fail "next " } + } + +send_gdb "n\n" +gdb_expect { + -re "$decimal.*f = add\\(f, f\\);.*$gdb_prompt $" { + pass "next " + } + -re ".*$gdb_prompt $" { fail "next " } + timeout { fail "next " } + } + +send_gdb "n\n" +gdb_expect { + -re "$decimal.*add1\\(\\);.*$gdb_prompt $" { + pass "next " + } + -re ".*$gdb_prompt $" { fail "next " } + timeout { fail "next " } + } + +send_gdb "print c\n" +gdb_expect { + -re ".$decimal = -62.*\r\n$gdb_prompt $" { + pass "print value of c" + } + -re ".*$gdb_prompt $" { fail "print value of c" } + timeout { fail "(timeout) print value of c" } + } + + +send_gdb "print f\n" +gdb_expect { + -re ".$decimal = 9\r\n$gdb_prompt $" { + pass "print value of f" + } + -re ".*$gdb_prompt $" { fail "print value of f" } + timeout { fail "(timeout) print value of f" } + } + + +send_gdb "print i\n" +gdb_expect { + -re ".$decimal = 4\r\n$gdb_prompt $" { + pass "print value of i" + } + -re ".*$gdb_prompt $" { fail "print value of i" } + timeout { fail "(timeout) print value of i" } + } + + + +send_gdb "print add(2,2)\n" +gdb_expect { + -re ".$decimal = 4\r\n$gdb_prompt $" { + pass "print value of add(2,2)" + } + -re ".*$gdb_prompt $" { fail "print value of add(2,2)" } + timeout { fail "(timeout) print value of add(2,2)" } + } + +send_gdb "print add(2.3,2.3)\n" +gdb_expect { + -re ".$decimal = 4\\.5\[0-9\]+\r\n$gdb_prompt $" { + pass "print value of add(2.3,2.3)" + } + -re ".*$gdb_prompt $" { fail "print value of add(2.3,2.3)" } + timeout { fail "(timeout) print value of add(2.3,2.3)" } + } + +send_gdb "print add('A','A')\n" +gdb_expect { + -re ".$decimal = -126.*202.\r\n$gdb_prompt $" { + pass "print value of add('A','A')" + } + -re ".*$gdb_prompt $" { fail "print value of add('A','A')" } + timeout { fail "(timeout) print value of add('A','A')" } + } + + +send_gdb "print add2(2,2)\n" +gdb_expect { + -re ".$decimal = 4\r\n$gdb_prompt $" { + pass "print value of add2(2,2)" + } + -re ".*$gdb_prompt $" { fail "print value of add2(2,2)" } + timeout { fail "(timeout) print value of add2(2,2)" } + } + +send_gdb "print add2(2.3,2.3)\n" +gdb_expect { + -re ".$decimal = 4\\.5\[0-9\]+\r\n$gdb_prompt $" { + pass "print value of add2(2.3,2.3)" + } + -re ".*$gdb_prompt $" { fail "print value of add2(2.3,2.3)" } + timeout { fail "(timeout) print value of add2(2.3,2.3)" } + } + +send_gdb "print add2('A','A')\n" +gdb_expect { + -re ".$decimal = -126.*202.\r\n$gdb_prompt $" { + pass "print value of add2('A','A')" + } + -re ".*$gdb_prompt $" { fail "print value of add2('A','A')" } + timeout { fail "(timeout) print value of add2('A','A')" } + } + +send_gdb "print add3(2,2)\n" +gdb_expect { + -re ".$decimal = 4\r\n$gdb_prompt $" { + pass "print value of add3(2,2)" + } + -re ".*$gdb_prompt $" { fail "print value of add3(2,2)" } + timeout { fail "(timeout) print value of add3(2,2)" } + } + +send_gdb "print add3(2.3,2.3)\n" +gdb_expect { + -re ".$decimal = 4\\.5\[0-9\]+\r\n$gdb_prompt $" { + pass "print value of add3(2.3,2.3)" + } + -re ".*$gdb_prompt $" { fail "print value of add3(2.3,2.3)" } + timeout { fail "(timeout) print value of add3(2.3,2.3)" } + } + +send_gdb "print add3('A','A')\n" +gdb_expect { + -re ".$decimal = -126.*202.\r\n$gdb_prompt $" { + pass "print value of add3('A','A')" + } + -re ".*$gdb_prompt $" { fail "print value of add3('A','A')" } + timeout { fail "(timeout) print value of add3('A','A')" } + } + +send_gdb "print add4(2,2)\n" +gdb_expect { + -re ".$decimal = 4\r\n$gdb_prompt $" { + pass "print value of add4(2,2)" + } + -re ".*$gdb_prompt $" { fail "print value of add4(2,2)" } + timeout { fail "(timeout) print value of add4(2,2)" } + } + +send_gdb "print add4(2.3,2.3)\n" +gdb_expect { + -re ".$decimal = 4\\.5\[0-9\]+\r\n$gdb_prompt $" { + pass "print value of add4(2.3,2.3)" + } + -re ".*$gdb_prompt $" { fail "print value of add4(2.3,2.3)" } + timeout { fail "(timeout) print value of add4(2.3,2.3)" } + } + +send_gdb "print add4('A','A')\n" +gdb_expect { + -re ".$decimal = -126.*202.\r\n$gdb_prompt $" { + pass "print value of add4('A','A')" + } + -re ".*$gdb_prompt $" { fail "print value of add4('A','A')" } + timeout { fail "(timeout) print value of add4('A','A')" } + } + + +gdb_exit +return 0 diff --git a/gdb/testsuite/gdb.cp/cttiadd.cc b/gdb/testsuite/gdb.cp/cttiadd.cc new file mode 100644 index 0000000..1f50fae --- /dev/null +++ b/gdb/testsuite/gdb.cp/cttiadd.cc @@ -0,0 +1,29 @@ +template T add(T v1, T v2) +{ + T v3; + v3 = v1; + v3 += v2; + return v3; + } + +int main() +{ + char c; + int i; + float f; + extern void add1(); + extern void subr2(); + extern void subr3(); + + c = 'a'; + i = 2; + f = 4.5; + + c = add(c, c); + i = add(i, i); + f = add(f, f); + + add1(); + subr2(); + subr3(); +} diff --git a/gdb/testsuite/gdb.cp/cttiadd1.cc b/gdb/testsuite/gdb.cp/cttiadd1.cc new file mode 100644 index 0000000..7113ece --- /dev/null +++ b/gdb/testsuite/gdb.cp/cttiadd1.cc @@ -0,0 +1,16 @@ +template T add(T v1, T v2); + +void add1() +{ + char c; + int i; + float f; + + c = 'b'; + i = 3; + f = 6.5; + + c = add(c, c); + i = add(i, i); + f = add(f, f); +} diff --git a/gdb/testsuite/gdb.cp/cttiadd2.cc b/gdb/testsuite/gdb.cp/cttiadd2.cc new file mode 100644 index 0000000..d0d9891 --- /dev/null +++ b/gdb/testsuite/gdb.cp/cttiadd2.cc @@ -0,0 +1,22 @@ +template T add2(T v1, T v2) +{ + T v3; + v3 = v1; + v3 += v2; + return v3; +} + +void subr2() +{ + char c; + int i; + float f; + + c = 'b'; + i = 3; + f = 6.5; + + c = add2(c, c); + i = add2(i, i); + f = add2(f, f); +} diff --git a/gdb/testsuite/gdb.cp/cttiadd3.cc b/gdb/testsuite/gdb.cp/cttiadd3.cc new file mode 100644 index 0000000..7ba1b01 --- /dev/null +++ b/gdb/testsuite/gdb.cp/cttiadd3.cc @@ -0,0 +1,33 @@ +template T add3(T v1, T v2) +{ + T v3; + v3 = v1; + v3 += v2; + return v3; +} + +template T add4(T v1, T v2) +{ + T v3; + v3 = v1; + v3 += v2; + return v3; +} + +void subr3() +{ + char c; + int i; + float f; + + c = 'b'; + i = 3; + f = 6.5; + + c = add3(c, c); + i = add3(i, i); + f = add3(f, f); + c = add4(c, c); + i = add4(i, i); + f = add4(f, f); +} diff --git a/gdb/testsuite/gdb.cp/demangle.exp b/gdb/testsuite/gdb.cp/demangle.exp new file mode 100644 index 0000000..7bd9fc5 --- /dev/null +++ b/gdb/testsuite/gdb.cp/demangle.exp @@ -0,0 +1,1582 @@ +# Copyright (C) 1992, 1997, 1999, 2003 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# Please email any bugs, comments, and/or additions to this file to: +# bug-gdb@prep.ai.mit.edu + +# This file was written by Fred Fish. (fnf@cygnus.com) + +if $tracelevel then { + strace $tracelevel +} + +if { [skip_cplus_tests] } { continue } + +### The demangling style we last sent to GDB. +set current_demangling_style none + +### Set GDB's current demangling style to STYLE. Subsequent calls to +### test_demangle will include STYLE in the test name when reporting +### passes and failures. +proc set_demangling_style {style} { + global gdb_prompt + global current_demangling_style + + send_gdb "set demangle-style $style\n" + gdb_expect { + -re "set demangle-style $style\[\r\n\]+$gdb_prompt $" { + pass "$style: set demangle-style" + } + -re ".*$gdb_prompt $" { + fail "$style: set demangle-style" + error "set_demangling_style: set style" + } + timeout { + fail "$style: set demangle-style (timeout)" + error "set_demangling_style: set style" + } + } + + send_gdb "show demangle-style\n" + gdb_expect { + -re "The current C\[+\]+ demangling style is \"$style\".\r\n$gdb_prompt $" { + pass "$style: check demangling style" + } + -re ".*$gdb_prompt $" { + fail "$style: check demangling style" + error "set_demangling_style: check style" + } + timeout { + fail "$style: check demangling style (timeout)" + error "set_demangling_style: check style" + } + } + + set current_demangling_style $style +} + + +### Utility function for test_demangling and test_demangling_exact. +proc test_demangling_core {tester test result} { + global current_demangling_style + + if {! [regexp {^([^ ]+): (.+)$} $test dummy style name]} { + error "bad test name passed to test_demangling" + } + + if {[string compare $style $current_demangling_style]} { + set_demangling_style $style + } + + $tester "maintenance demangle $name" $result $test +} + +### Demangle an identifier, and check that the result matches a pattern. +### +### TEST should be of the form "STYLE: NAME", where STYLE is the name +### of a demangling style (like "gnu" or "arm"), and NAME is a mangled +### identifier to demangle. Pass when the result matches the regular +### expression RESULT. Report passes and fails using TEST as the name +### of the test. +### +### Why don't we just pass the STYLE and NAME as two separate +### arguments, or let the style be a global variable? That would be +### cleaner. However, doing it this way means that: +### +### 1) the name of the test, as recorded in the summary and log, +### appears verbatim in the script, and +### +### 2) that test names are unique, even though we try to demangle the same +### identifiers using several different mangling styles. +### +### This makes it a lot easier for people tracking down failures to +### find the one they care about. + +proc test_demangling {test result} { + test_demangling_core gdb_test $test $result +} + +### Like test_demangling, above, except that RESULT is not a regexp, +### but a string that must match exactly. + +proc test_demangling_exact {test result} { + test_demangling_core gdb_test_exact $test $result +} + + + +# +# Test gnu style name demangling +# + +proc test_gnu_style_demangling {} { + global gdb_prompt + + test_demangling "gnu: Abort__FP6EditoriPCc" \ + "Abort\[(\]+Editor \[*\]+, int, (const char|char const) \[*\]+\[)\]+" + test_demangling_exact "gnu: AddAlignment__9ivTSolverUiP12ivInteractorP7ivTGlue" "ivTSolver::AddAlignment(unsigned int, ivInteractor *, ivTGlue *)" + test_demangling "gnu: Append__15NameChooserViewPCc" \ + "NameChooserView::Append\[(\]+(const char|char const) \[*\]+\[)\]+" + test_demangling_exact "gnu: ArrowheadIntersects__9ArrowLineP9ArrowheadR6BoxObjP7Graphic" "ArrowLine::ArrowheadIntersects(Arrowhead *, BoxObj &, Graphic *)" + test_demangling_exact "gnu: AtEnd__13ivRubberGroup" "ivRubberGroup::AtEnd(void)" + test_demangling_exact "gnu: BgFilter__9ivTSolverP12ivInteractor" "ivTSolver::BgFilter(ivInteractor *)" + test_demangling "gnu: BitPatterntoa__FRC10BitPatternccc" \ + "BitPatterntoa\[(\]+(const BitPattern|BitPattern const) &, char, char, char\[)\]+" + test_demangling_exact "gnu: Check__6UArrayi" "UArray::Check(int)" + test_demangling_exact "gnu: CoreConstDecls__8TextCodeR7ostream" "TextCode::CoreConstDecls(ostream &)" + test_demangling_exact "gnu: Detach__8StateVarP12StateVarView" "StateVar::Detach(StateVarView *)" + test_demangling_exact "gnu: Done__9ComponentG8Iterator" "Component::Done(Iterator)" + test_demangling "gnu: DrawDestinationTransformedImage__FP7_XImageiiT0iiUlUiiiUiUlUlP4_XGCRC13ivTransformeriiii" \ + "DrawDestinationTransformedImage\[(\]+_XImage \[*\]+, int, int, _XImage \[*\]+, int, int, unsigned long, unsigned int, int, int, unsigned int, unsigned long, unsigned long, _XGC \[*\]+, (const ivTransformer|ivTransformer const) &, int, int, int, int\[)\]+" + + test_demangling "gnu: Edit__12StringEditorPCcii" \ + "StringEditor::Edit\[(\]+(const char|char const) \[*\]+, int, int\[)\]+" + test_demangling_exact "gnu: Effect__11RelateManipR7ivEvent" "RelateManip::Effect(ivEvent &)" + test_demangling "gnu: FilterName__FPCc" \ + "FilterName\[(\]+(const char|char const) \[*\]+\[)\]+" + test_demangling "gnu: Filter__6PSTextPCci" \ + "PSText::Filter\[(\]+(const char|char const) \[*\]+, int\[)\]+" + test_demangling "gnu: FindColor__7CatalogPCciii" \ + "Catalog::FindColor\[(\]+(const char|char const) \[*\]+, int, int, int\[)\]+" + test_demangling_exact "gnu: FindFixed__FRP4CNetP4CNet" "FindFixed(CNet *&, CNet *)" + test_demangling "gnu: FindFont__7CatalogPCcN21" \ + "Catalog::FindFont\[(\]+(const char|char const) \[*\]+, (const char|char const) \[*\]+, (const char|char const) \[*\]+\[)\]+" + test_demangling_exact "gnu: Fix48_abort__FR8twolongs" "Fix48_abort(twolongs &)" + test_demangling_exact "gnu: GetBarInfo__15iv2_6_VScrollerP13ivPerspectiveRiT2" "iv2_6_VScroller::GetBarInfo(ivPerspective *, int &, int &)" + test_demangling_exact "gnu: GetBgColor__C9ivPainter" "ivPainter::GetBgColor(void) const" + + test_demangling "gnu: Iisdouble__FPC6IntRep" \ + "Iisdouble\[(\]+(const IntRep|IntRep const) \[*\]+\[)\]+" + test_demangling_exact "gnu: InsertBody__15H_PullrightMenuii" "H_PullrightMenu::InsertBody(int, int)" + test_demangling_exact "gnu: InsertCharacter__9TextManipc" "TextManip::InsertCharacter(char)" + + test_demangling_exact "gnu: InsertToplevel__7ivWorldP12ivInteractorT1" "ivWorld::InsertToplevel(ivInteractor *, ivInteractor *)" + test_demangling_exact "gnu: InsertToplevel__7ivWorldP12ivInteractorT1iiUi" "ivWorld::InsertToplevel(ivInteractor *, ivInteractor *, int, int, unsigned int)" + test_demangling "gnu: IsADirectory__FPCcR4stat" \ + "IsADirectory\[(\]+(const char|char const) \[*\]+, stat &\[)\]+" + test_demangling_exact "gnu: IsAGroup__FP11GraphicViewP11GraphicComp" "IsAGroup(GraphicView *, GraphicComp *)" + test_demangling_exact "gnu: IsA__10ButtonCodeUl" "ButtonCode::IsA(unsigned long)" + + test_demangling_exact "gnu: ReadName__FR7istreamPc" "ReadName(istream &, char *)" + test_demangling_exact "gnu: Redraw__13StringBrowseriiii" "StringBrowser::Redraw(int, int, int, int)" + test_demangling_exact "gnu: Rotate__13ivTransformerf" "ivTransformer::Rotate(float)" + test_demangling_exact "gnu: Rotated__C13ivTransformerf" "ivTransformer::Rotated(float) const" + test_demangling_exact "gnu: Round__Ff" "Round(float)" + + test_demangling_exact "gnu: SetExport__16MemberSharedNameUi" "MemberSharedName::SetExport(unsigned int)" + test_demangling_exact "gnu: Set__14ivControlState13ControlStatusUi" "ivControlState::Set(ControlStatus, unsigned int)" + test_demangling_exact "gnu: Set__5DFacePcii" "DFace::Set(char *, int, int)" + + test_demangling_exact "gnu: VConvert__9ivTSolverP12ivInteractorRP8TElementT2" "ivTSolver::VConvert(ivInteractor *, TElement *&, TElement *&)" + test_demangling_exact "gnu: VConvert__9ivTSolverP7ivTGlueRP8TElement" "ivTSolver::VConvert(ivTGlue *, TElement *&)" + test_demangling_exact "gnu: VOrder__9ivTSolverUiRP12ivInteractorT2" "ivTSolver::VOrder(unsigned int, ivInteractor *&, ivInteractor *&)" + test_demangling "gnu: Valid__7CatalogPCcRP4Tool" \ + "Catalog::Valid\[(\]+(const char|char const) \[*\]+, Tool \[*\]+&\[)\]+" + test_demangling_exact "gnu: _10PageButton\$__both" "PageButton::__both" + test_demangling_exact "gnu: _3RNG\$singleMantissa" "RNG::singleMantissa" + test_demangling_exact "gnu: _5IComp\$_release" "IComp::_release" + test_demangling_exact "gnu: _\$_10BitmapComp" "BitmapComp::~BitmapComp(void)" + + test_demangling_exact "gnu: _\$_9__io_defs" "__io_defs::~__io_defs(void)" + test_demangling_exact "gnu: _\$_Q23foo3bar" "foo::bar::~bar(void)" + test_demangling_exact "gnu: _\$_Q33foo3bar4bell" "foo::bar::bell::~bell(void)" + test_demangling_exact "gnu: __10ivTelltaleiP7ivGlyph" "ivTelltale::ivTelltale(int, ivGlyph *)" + test_demangling_exact "gnu: __10ivViewportiP12ivInteractorUi" "ivViewport::ivViewport(int, ivInteractor *, unsigned int)" + test_demangling_exact "gnu: __10ostrstream" "ostrstream::ostrstream(void)" + test_demangling_exact "gnu: __10ostrstreamPcii" "ostrstream::ostrstream(char *, int, int)" + test_demangling "gnu: __11BasicDialogiPCcP13ivButtonStateN22Ui" \ + "BasicDialog::BasicDialog\[(\]+int, (const char|char const) \[*\]+, ivButtonState \[*\]+, (const char|char const) \[*\]+, (const char|char const) \[*\]+, unsigned int\[)\]+" + test_demangling_exact "gnu: __11BitmapTablei" "BitmapTable::BitmapTable(int)" + test_demangling_exact "gnu: __12ViewportCodeP12ViewportComp" "ViewportCode::ViewportCode(ViewportComp *)" + test_demangling "gnu: __12iv2_6_BorderiPCci" \ + "iv2_6_Border::iv2_6_Border\[(\]+int, (const char|char const) \[*\]+, int\[)\]+" + test_demangling_exact "gnu: __12iv2_6_Borderii" "iv2_6_Border::iv2_6_Border(int, int)" + test_demangling "gnu: __12ivBackgroundiP7ivGlyphPC7ivColor" \ + "ivBackground::ivBackground\[(\]+int, ivGlyph \[*\]+, (const ivColor|ivColor const) \[*\]+\[)\]+" + test_demangling_exact "gnu: __12ivBreak_Listl" "ivBreak_List::ivBreak_List(long)" + test_demangling "gnu: __14TextInteractoriPCcUi" \ + "TextInteractor::TextInteractor\[(\]+int, (const char|char const) \[*\]+, unsigned int\[)\]+" + test_demangling_exact "gnu: __14iv2_6_MenuItemiP12ivInteractor" "iv2_6_MenuItem::iv2_6_MenuItem(int, ivInteractor *)" + test_demangling "gnu: __14iv2_6_MenuItemiPCcP12ivInteractor" \ + "iv2_6_MenuItem::iv2_6_MenuItem\[(\]+int, (const char|char const) \[*\]+, ivInteractor \[*\]+\[)\]+" + + test_demangling_exact "gnu: __20DisplayList_IteratorR11DisplayList" "DisplayList_Iterator::DisplayList_Iterator(DisplayList &)" + test_demangling_exact "gnu: __3fooRT0" "foo::foo(foo &)" + test_demangling_exact "gnu: __3fooiN31" "foo::foo(int, int, int, int)" + test_demangling "gnu: __3fooiPCc" \ + "foo::foo\[(\]+int, (const char|char const) \[*\]+\[)\]+" + test_demangling_exact "gnu: __3fooiRT0iT2iT2" "foo::foo(int, foo &, int, foo &, int, foo &)" + test_demangling "gnu: __6GetOptiPPcPCc" \ + "GetOpt::GetOpt\[(\]+int, char \[*\]+\[*\]+, (const char|char const) \[*\]+\[)\]+" + test_demangling_exact "gnu: __6KeyMapPT0" "KeyMap::KeyMap(KeyMap *)" + test_demangling "gnu: __7ivWorldPCcRiPPcPC12ivOptionDescPC14ivPropertyData" \ + "ivWorld::ivWorld\[(\]+(const char|char const) \[*\]+, int &, char \[*\]+\[*\]+, (const ivOptionDesc|ivOptionDesc const) \[*\]+, (const ivPropertyData|ivPropertyData const) \[*\]+\[)\]+" + test_demangling "gnu: __7procbufPCci" \ + "procbuf::procbuf\[(\]+(const char|char const) \[*\]+, int\[)\]+" + test_demangling_exact "gnu: __8ArrowCmdP6EditorUiUi" "ArrowCmd::ArrowCmd(Editor *, unsigned int, unsigned int)" + + test_demangling_exact "gnu: __9F_EllipseiiiiP7Graphic" "F_Ellipse::F_Ellipse(int, int, int, int, Graphic *)" + test_demangling_exact "gnu: __9FrameDataP9FrameCompi" "FrameData::FrameData(FrameComp *, int)" + test_demangling_exact "gnu: __9HVGraphicP9CanvasVarP7Graphic" "HVGraphic::HVGraphic(CanvasVar *, Graphic *)" + test_demangling_exact "gnu: __Q23foo3bar" "foo::bar::bar(void)" + test_demangling_exact "gnu: __Q33foo3bar4bell" "foo::bar::bell::bell(void)" + test_demangling_exact "gnu: __aa__3fooRT0" "foo::operator&&(foo &)" + test_demangling_exact "gnu: __aad__3fooRT0" "foo::operator&=(foo &)" + test_demangling_exact "gnu: __ad__3fooRT0" "foo::operator&(foo &)" + test_demangling_exact "gnu: __adv__3fooRT0" "foo::operator/=(foo &)" + test_demangling_exact "gnu: __aer__3fooRT0" "foo::operator^=(foo &)" + test_demangling_exact "gnu: __als__3fooRT0" "foo::operator<<=(foo &)" + test_demangling_exact "gnu: __amd__3fooRT0" "foo::operator%=(foo &)" + test_demangling_exact "gnu: __ami__3fooRT0" "foo::operator-=(foo &)" + test_demangling_exact "gnu: __aml__3FixRT0" "Fix::operator*=(Fix &)" + test_demangling_exact "gnu: __aml__5Fix16i" "Fix16::operator*=(int)" + test_demangling_exact "gnu: __aml__5Fix32RT0" "Fix32::operator*=(Fix32 &)" + test_demangling_exact "gnu: __aor__3fooRT0" "foo::operator|=(foo &)" + test_demangling_exact "gnu: __apl__3fooRT0" "foo::operator+=(foo &)" + test_demangling_exact "gnu: __ars__3fooRT0" "foo::operator>>=(foo &)" + + test_demangling_exact "gnu: __as__3fooRT0" "foo::operator=(foo &)" + test_demangling_exact "gnu: __cl__3fooRT0" "foo::operator()(foo &)" + test_demangling_exact "gnu: __cl__6Normal" "Normal::operator()(void)" + test_demangling_exact "gnu: __cl__6Stringii" "String::operator()(int, int)" + test_demangling_exact "gnu: __cm__3fooRT0" "foo::operator, (foo &)" + test_demangling_exact "gnu: __co__3foo" "foo::operator~(void)" + test_demangling_exact "gnu: __dl__3fooPv" "foo::operator delete(void *)" + test_demangling_exact "gnu: __dv__3fooRT0" "foo::operator/(foo &)" + test_demangling_exact "gnu: __eq__3fooRT0" "foo::operator==(foo &)" + test_demangling_exact "gnu: __er__3fooRT0" "foo::operator^(foo &)" + test_demangling_exact "gnu: __ge__3fooRT0" "foo::operator>=(foo &)" + test_demangling_exact "gnu: __gt__3fooRT0" "foo::operator>(foo &)" + test_demangling_exact "gnu: __le__3fooRT0" "foo::operator<=(foo &)" + test_demangling_exact "gnu: __ls__3fooRT0" "foo::operator<<(foo &)" + test_demangling_exact "gnu: __ls__FR7ostreamPFR3ios_R3ios" "operator<<(ostream &, ios &(*)(ios &))" + test_demangling_exact "gnu: __ls__FR7ostreamR3Fix" "operator<<(ostream &, Fix &)" + test_demangling_exact "gnu: __lt__3fooRT0" "foo::operator<(foo &)" + test_demangling_exact "gnu: __md__3fooRT0" "foo::operator%(foo &)" + test_demangling_exact "gnu: __mi__3fooRT0" "foo::operator-(foo &)" + test_demangling_exact "gnu: __ml__3fooRT0" "foo::operator*(foo &)" + test_demangling_exact "gnu: __mm__3fooi" "foo::operator--(int)" + + test_demangling_exact "gnu: __ne__3fooRT0" "foo::operator!=(foo &)" + test_demangling "gnu: __ne__FRC7ComplexT0" \ + "operator!=\[(\]+(const Complex|Complex const) &, (const Complex|Complex const) &\[)\]+" + test_demangling "gnu: __ne__FRC7Complexd" \ + "operator!=\[(\]+(const Complex|Complex const) &, double\[)\]+" + test_demangling "gnu: __ne__FRC9SubStringRC6String" \ + "operator!=\[(\]+(const SubString|SubString const) &, (const String|String const) &\[)\]+" + test_demangling_exact "gnu: __nt__3foo" "foo::operator!(void)" + test_demangling_exact "gnu: __nw__3fooi" "foo::operator new(int)" + test_demangling_exact "gnu: __oo__3fooRT0" "foo::operator||(foo &)" + test_demangling_exact "gnu: __opPc__3foo" "foo::operator char *(void)" + test_demangling_exact "gnu: __opi__3foo" "foo::operator int(void)" + test_demangling_exact "gnu: __or__3fooRT0" "foo::operator|(foo &)" + test_demangling_exact "gnu: __pl__3fooRT0" "foo::operator+(foo &)" + test_demangling_exact "gnu: __pp__3fooi" "foo::operator++(int)" + test_demangling_exact "gnu: __rf__3foo" "foo::operator->(void)" + test_demangling_exact "gnu: __rm__3fooRT0" "foo::operator->*(foo &)" + test_demangling_exact "gnu: __rs__3fooRT0" "foo::operator>>(foo &)" + test_demangling "gnu: __vc__3fooRT0" "foo::operator\\\[\\\]\\(foo &\\)" + test_demangling "gnu: _gsub__6StringRC5RegexPCci" \ + "String::_gsub\[(\]+(const Regex|Regex const) &, (const char|char const) \[*\]+, int\[)\]+" + test_demangling_exact "gnu: _new_Fix__FUs" "_new_Fix(unsigned short)" + + # gcc 2.4.5 (and earlier) style virtual tables. We want to continue to + # correctly demangle these even if newer compilers use a different form. + test_demangling_exact "gnu: _vt.foo" "foo virtual table" + test_demangling_exact "gnu: _vt.foo.bar" "foo::bar virtual table" + test_demangling_exact "gnu: _vt\$foo" "foo virtual table" + test_demangling_exact "gnu: _vt\$foo\$bar" "foo::bar virtual table" + + test_demangling_exact "gnu: append__7ivGlyphPT0" "ivGlyph::append(ivGlyph *)" + test_demangling "gnu: arg__FRC7Complex" \ + "arg\[(\]+(const Complex|Complex const) &\[)\]+" + test_demangling_exact "gnu: clearok__FP7_win_sti" "clearok(_win_st *, int)" + + test_demangling_exact "gnu: complexfunc2__FPFPc_i" "complexfunc2(int (*)(char *))" + test_demangling_exact "gnu: complexfunc3__FPFPFPl_s_i" "complexfunc3(int (*)(short (*)(long *)))" + test_demangling_exact "gnu: complexfunc4__FPFPFPc_s_i" "complexfunc4(int (*)(short (*)(char *)))" + test_demangling_exact "gnu: complexfunc5__FPFPc_PFl_i" "complexfunc5(int (*(*)(char *))(long))" + test_demangling_exact "gnu: complexfunc6__FPFPi_PFl_i" "complexfunc6(int (*(*)(int *))(long))" + test_demangling_exact "gnu: complexfunc7__FPFPFPc_i_PFl_i" "complexfunc7(int (*(*)(int (*)(char *)))(long))" + test_demangling "gnu: contains__C9BitStringRC10BitPattern" \ + "BitString::contains\[(\]+(const BitPattern|BitPattern const) &\[)\]+ const" + test_demangling "gnu: contains__C9BitStringRC12BitSubStringi" \ + "BitString::contains\[(\]+(const BitSubString|BitSubString const) &, int\[)\]+ const" + test_demangling "gnu: contains__C9BitStringRT0" \ + "BitString::contains\[(\]+(const BitString|BitString const) &\[)\]+ const" + test_demangling "gnu: div__FPC6IntRepT0P6IntRep" \ + "div\[(\]+(const IntRep|IntRep const) \[*\]+, (const IntRep|IntRep const) \[*\]+, IntRep \[*\]+\[)\]+" + test_demangling "gnu: div__FPC6IntReplP6IntRep" \ + "div\[(\]+(const IntRep|IntRep const) \[*\]+, long, IntRep \[*\]+\[)\]+" + test_demangling "gnu: div__FRC8RationalT0R8Rational" \ + "div\[(\]+(const Rational|Rational const) &, (const Rational|Rational const) &, Rational &\[)\]+" + test_demangling "gnu: divide__FRC7IntegerT0R7IntegerT2" \ + "divide\[(\]+(const Integer|Integer const) &, (const Integer|Integer const) &, Integer &, Integer &\[)\]+" + test_demangling "gnu: divide__FRC7IntegerlR7IntegerRl" \ + "divide\[(\]+(const Integer|Integer const) &, long, Integer &, long &\[)\]+" + test_demangling "gnu: enable__14DocumentViewerPCcUi" \ + "DocumentViewer::enable\[(\]+(const char|char const) \[*\]+, unsigned int\[)\]+" + + test_demangling_exact "gnu: foo__FiN30" "foo(int, int, int, int)" + test_demangling_exact "gnu: foo__FiR3fooiT1iT1" "foo(int, foo &, int, foo &, int, foo &)" + test_demangling_exact "gnu: foo___3barl" "bar::foo_(long)" + test_demangling_exact "gnu: insert__15ivClippingStacklRP8_XRegion" "ivClippingStack::insert(long, _XRegion *&)" + test_demangling_exact "gnu: insert__16ChooserInfo_ListlR11ChooserInfo" "ChooserInfo_List::insert(long, ChooserInfo &)" + test_demangling_exact "gnu: insert__17FontFamilyRepListlRP15ivFontFamilyRep" "FontFamilyRepList::insert(long, ivFontFamilyRep *&)" + test_demangling_exact "gnu: leaveok__FP7_win_stc" "leaveok(_win_st *, char)" + test_demangling_exact "gnu: left_mover__C7ivMFKitP12ivAdjustableP7ivStyle" "ivMFKit::left_mover(ivAdjustable *, ivStyle *) const" + test_demangling "gnu: matches__C9BitStringRC10BitPatterni" \ + "BitString::matches\[(\]+(const BitPattern|BitPattern const) &, int\[)\]+ const" + test_demangling "gnu: matches__C9SubStringRC5Regex" \ + "SubString::matches\[(\]+(const Regex|Regex const) &\[)\]+ const" + + test_demangling_exact "gnu: overload1arg__FSc" "overload1arg(signed char)" + test_demangling_exact "gnu: overload1arg__FUc" "overload1arg(unsigned char)" + test_demangling_exact "gnu: overload1arg__FUi" "overload1arg(unsigned int)" + test_demangling_exact "gnu: overload1arg__FUl" "overload1arg(unsigned long)" + test_demangling_exact "gnu: overload1arg__FUs" "overload1arg(unsigned short)" + test_demangling_exact "gnu: overload1arg__Fc" "overload1arg(char)" + test_demangling_exact "gnu: overload1arg__Fd" "overload1arg(double)" + test_demangling_exact "gnu: overload1arg__Ff" "overload1arg(float)" + test_demangling_exact "gnu: overload1arg__Fi" "overload1arg(int)" + test_demangling_exact "gnu: overload1arg__Fl" "overload1arg(long)" + test_demangling_exact "gnu: overload1arg__Fs" "overload1arg(short)" + test_demangling_exact "gnu: overload1arg__Fv" "overload1arg(void)" + test_demangling_exact "gnu: overloadargs__Fi" "overloadargs(int)" + test_demangling_exact "gnu: overloadargs__Fii" "overloadargs(int, int)" + test_demangling_exact "gnu: overloadargs__Fiii" "overloadargs(int, int, int)" + test_demangling_exact "gnu: overloadargs__Fiiii" "overloadargs(int, int, int, int)" + + test_demangling_exact "gnu: overloadargs__Fiiiii" "overloadargs(int, int, int, int, int)" + test_demangling_exact "gnu: overloadargs__Fiiiiii" "overloadargs(int, int, int, int, int, int)" + test_demangling_exact "gnu: overloadargs__Fiiiiiii" "overloadargs(int, int, int, int, int, int, int)" + test_demangling_exact "gnu: overloadargs__Fiiiiiiii" "overloadargs(int, int, int, int, int, int, int, int)" + test_demangling_exact "gnu: overloadargs__Fiiiiiiiii" "overloadargs(int, int, int, int, int, int, int, int, int)" + test_demangling_exact "gnu: overloadargs__Fiiiiiiiiii" "overloadargs(int, int, int, int, int, int, int, int, int, int)" + test_demangling_exact "gnu: overloadargs__Fiiiiiiiiiii" "overloadargs(int, int, int, int, int, int, int, int, int, int, int)" + test_demangling "gnu: pick__13ivCompositionP8ivCanvasRC12ivAllocationiR5ivHit" \ + "ivComposition::pick\[(\]+ivCanvas \[*\]+, (const ivAllocation|ivAllocation const) &, int, ivHit &\[)\]+" + test_demangling "gnu: pointer__C11ivHScrollerRC7ivEventRC12ivAllocation" \ + "ivHScroller::pointer\[(\]+(const ivEvent|ivEvent const) &, (const ivAllocation|ivAllocation const) &\[)\]+ const" + test_demangling_exact "gnu: poke__8ivRasterUlUlffff" "ivRaster::poke(unsigned long, unsigned long, float, float, float, float)" + test_demangling_exact "gnu: polar__Fdd" "polar(double, double)" + test_demangling "gnu: read__10osStdInputRPCc" \ + "osStdInput::read\[(\]+(const char|char const) \[*\]+&\[)\]+" + + test_demangling_exact "gnu: scale__13ivTransformerff" "ivTransformer::scale(float, float)" + test_demangling "gnu: scanw__12CursesWindowPCce" \ + "CursesWindow::scanw\[(\]+(const char|char const) \[*\]+,...\[)\]+" + test_demangling "gnu: scmp__FPCcT0" \ + "scmp\[(\]+(const char|char const) \[*\]+, (const char|char const) \[*\]+\[)\]+" + test_demangling_exact "gnu: sgetn__7filebufPci" "filebuf::sgetn(char *, int)" + test_demangling_exact "gnu: shift__FP5_FrepiT0" "shift(_Frep *, int, _Frep *)" + test_demangling_exact "gnu: test__C6BitSeti" "BitSet::test(int) const" + test_demangling_exact "gnu: test__C6BitSetii" "BitSet::test(int, int) const" + test_demangling "gnu: testbit__FRC7Integerl" \ + "testbit\[(\]+(const Integer|Integer const) &, long\[)\]+" + test_demangling_exact "gnu: text_source__8Documentl" "Document::text_source(long)" + test_demangling_exact "gnu: variance__6Erlangd" "Erlang::variance(double)" + test_demangling "gnu: vform__8iostreamPCcPc" \ + "iostream::vform\[(\]+(const char|char const) \[*\]+, char \[*\]+\[)\]+" + test_demangling_exact "gnu: view__14DocumentViewerP8ItemViewP11TabularItem" "DocumentViewer::view(ItemView *, TabularItem *)" + test_demangling_exact "gnu: xy_extents__11ivExtensionffff" "ivExtension::xy_extents(float, float, float, float)" + test_demangling_exact "gnu: zero__8osMemoryPvUi" "osMemory::zero(void *, unsigned int)" + test_demangling_exact "gnu: _2T4\$N" "T4::N" + test_demangling_exact "gnu: _Q22T42t1\$N" "T4::t1::N" + test_demangling_exact "gnu: get__2T1" "T1::get(void)" + test_demangling_exact "gnu: get__Q22T11a" "T1::a::get(void)" + test_demangling_exact "gnu: get__Q32T11a1b" "T1::a::b::get(void)" + test_demangling_exact "gnu: get__Q42T11a1b1c" "T1::a::b::c::get(void)" + test_demangling_exact "gnu: get__Q52T11a1b1c1d" "T1::a::b::c::d::get(void)" + test_demangling_exact "gnu: put__2T1i" "T1::put(int)" + test_demangling_exact "gnu: put__Q22T11ai" "T1::a::put(int)" + test_demangling_exact "gnu: put__Q32T11a1bi" "T1::a::b::put(int)" + test_demangling_exact "gnu: put__Q42T11a1b1ci" "T1::a::b::c::put(int)" + test_demangling_exact "gnu: put__Q52T11a1b1c1di" "T1::a::b::c::d::put(int)" + + test_demangling_exact "gnu: bar__3fooPv" "foo::bar(void *)" + test_demangling "gnu: bar__3fooPCv" \ + "foo::bar\[(\]+(const void|void const) *\[*\]+\[)\]+" + test_demangling_exact "gnu: bar__C3fooPv" "foo::bar(void *) const" + test_demangling "gnu: bar__C3fooPCv" \ + "foo::bar\[(\]+(const void|void const) *\[*\]+\[)\]+ const" + test_demangling_exact "gnu: __eq__3fooRT0" "foo::operator==(foo &)" + test_demangling "gnu: __eq__3fooRC3foo" \ + "foo::operator==\[(\]+(const foo|foo const) &\[)\]+" + test_demangling_exact "gnu: __eq__C3fooR3foo" "foo::operator==(foo &) const" + test_demangling "gnu: __eq__C3fooRT0" \ + "foo::operator==\[(\]+(const foo|foo const) &\[)\]+ const" + + test_demangling_exact "gnu: elem__t6vector1Zdi" "vector::elem(int)" + test_demangling_exact "gnu: elem__t6vector1Zii" "vector::elem(int)" + test_demangling_exact "gnu: __t6vector1Zdi" "vector::vector(int)" + test_demangling_exact "gnu: __t6vector1Zii" "vector::vector(int)" + test_demangling_exact "gnu: _\$_t6vector1Zdi" "vector::~vector(int)" + test_demangling_exact "gnu: _\$_t6vector1Zii" "vector::~vector(int)" + + test_demangling_exact "gnu: __nw__t2T11ZcUi" "T1::operator new(unsigned int)" + test_demangling_exact "gnu: __nw__t2T11Z1tUi" "T1::operator new(unsigned int)" + test_demangling_exact "gnu: __dl__t2T11ZcPv" "T1::operator delete(void *)" + test_demangling_exact "gnu: __dl__t2T11Z1tPv" "T1::operator delete(void *)" + test_demangling_exact "gnu: __t2T11Zci" "T1::T1(int)" + test_demangling_exact "gnu: __t2T11Zc" "T1::T1(void)" + test_demangling_exact "gnu: __t2T11Z1ti" "T1::T1(int)" + test_demangling_exact "gnu: __t2T11Z1t" "T1::T1(void)" + + test_demangling_exact "gnu: __Q2t4List1Z10VHDLEntity3Pix" \ + "List::Pix::Pix(void)" + + test_demangling_exact "gnu: __Q2t4List1Z10VHDLEntity3PixPQ2t4List1Z10VHDLEntity7element" \ + "List::Pix::Pix(List::element *)" + + test_demangling_exact "gnu: __Q2t4List1Z10VHDLEntity3PixRCQ2t4List1Z10VHDLEntity3Pix" \ + "List::Pix::Pix(List::Pix const &)" + + test_demangling_exact "gnu: __Q2t4List1Z10VHDLEntity7elementRC10VHDLEntityPT0" \ + "List::element::element(VHDLEntity const &, List::element *)" + + test_demangling_exact "gnu: __Q2t4List1Z10VHDLEntity7elementRCQ2t4List1Z10VHDLEntity7element" \ + "List::element::element(List::element const &)" + + test_demangling_exact "gnu: __cl__C11VHDLLibraryGt4PixX3Z11VHDLLibraryZ14VHDLLibraryRepZt4List1Z10VHDLEntity" \ + "VHDLLibrary::operator()(PixX >) const" + + test_demangling_exact "gnu: __cl__Ct4List1Z10VHDLEntityRCQ2t4List1Z10VHDLEntity3Pix" \ + "List::operator()(List::Pix const &) const" + + test_demangling_exact "gnu: __ne__FPvRCQ2t4List1Z10VHDLEntity3Pix" \ + "operator!=(void *, List::Pix const &)" + + test_demangling_exact "gnu: __ne__FPvRCt4PixX3Z11VHDLLibraryZ14VHDLLibraryRepZt4List1Z10VHDLEntity" \ + "operator!=(void *, PixX > const &)" + + test_demangling_exact "gnu: __t4List1Z10VHDLEntityRCt4List1Z10VHDLEntity" \ + "List::List(List const &)" + + test_demangling_exact "gnu: __t4PixX3Z11VHDLLibraryZ14VHDLLibraryRepZt4List1Z10VHDLEntity" \ + "PixX >::PixX(void)" + + test_demangling_exact "gnu: __t4PixX3Z11VHDLLibraryZ14VHDLLibraryRepZt4List1Z10VHDLEntityP14VHDLLibraryRepGQ2t4List1Z10VHDLEntity3Pix" \ + "PixX >::PixX(VHDLLibraryRep *, List::Pix)" + + test_demangling_exact "gnu: __t4PixX3Z11VHDLLibraryZ14VHDLLibraryRepZt4List1Z10VHDLEntityRCt4PixX3Z11VHDLLibraryZ14VHDLLibraryRepZt4List1Z10VHDLEntity" \ + "PixX >::PixX(PixX > const &)" + + test_demangling_exact "gnu: nextE__C11VHDLLibraryRt4PixX3Z11VHDLLibraryZ14VHDLLibraryRepZt4List1Z10VHDLEntity" \ + "VHDLLibrary::nextE(PixX > &) const" + + test_demangling_exact "gnu: next__Ct4List1Z10VHDLEntityRQ2t4List1Z10VHDLEntity3Pix" \ + "List::next(List::Pix &) const" + + test_demangling_exact "gnu: _GLOBAL_\$D\$set" "global destructors keyed to set" + + test_demangling_exact "gnu: _GLOBAL_\$I\$set" "global constructors keyed to set" + + test_demangling_exact "gnu: __as__t5ListS1ZUiRCt5ListS1ZUi" \ + "ListS::operator=(ListS const &)" + + test_demangling_exact "gnu: __cl__Ct5ListS1ZUiRCQ2t5ListS1ZUi3Vix" \ + "ListS::operator()(ListS::Vix const &) const" + + test_demangling_exact "gnu: __cl__Ct5SetLS1ZUiRCQ2t5SetLS1ZUi3Vix" \ + "SetLS::operator()(SetLS::Vix const &) const" + + test_demangling_exact "gnu: __t10ListS_link1ZUiRCUiPT0" \ + "ListS_link::ListS_link(unsigned int const &, ListS_link *)" + + test_demangling_exact "gnu: __t10ListS_link1ZUiRCt10ListS_link1ZUi" \ + "ListS_link::ListS_link(ListS_link const &)" + + test_demangling_exact "gnu: __t5ListS1ZUiRCt5ListS1ZUi" \ + "ListS::ListS(ListS const &)" + + test_demangling_exact "gnu: next__Ct5ListS1ZUiRQ2t5ListS1ZUi3Vix" \ + "ListS::next(ListS::Vix &) const" + + test_demangling_exact "gnu: __ne__FPvRCQ2t5SetLS1ZUi3Vix" \ + "operator!=(void *, SetLS::Vix const &)" + test_demangling_exact "gnu: __t8ListElem1Z5LabelRt4List1Z5Label" \ + "ListElem = \{a = 1, aa = 2\}, = \{b = 3, bb = 4\}, = \{c = 5, cc = 6\}, d = 7, dd = 8\}\r\n$gdb_prompt $" { + pass "print value of d_instance" + } + -re ".\[0-9\]* = \{ = \{a = 1, aa = 2\}, = \{b = 3, bb = 4\}, = \{c = 5, cc = 6\}, d = 7, dd = 8\}\r\n$gdb_prompt $" { + pass "print value of d_instance" + } + -re ".*$gdb_prompt $" { fail "print value of d_instance" } + timeout { fail "(timeout) print value of d_instance" } + } + + if { [test_compiler_info gcc-*] } then { + send_gdb "ptype d_instance\n" + gdb_expect { + -re "type = class D : private A, public B, (protected|private) C \{\r\n\[\t \]*public:\r\n\[\t \]*int d;\r\n\[\t \]*int dd;\[\r\n\t ]+D & operator=\\(D const ?&\\);\[\r\n\t ]+D\\((D const|const D) ?&\\);\[\r\n\t \]+D\\((void|)\\);\r\n\[\t \]*int dfoo\\((void|)\\);\r\n\[\t \]*int foo\\((void|)\\);\r\n\}.*$gdb_prompt $" { pass "ptype d_instance" } + -re "type = class D : private A, public B, (protected|private) C \{\r\n\[\t \]*public:\r\n\[\t \]*int d;\r\n\[\t \]*int dd;\[\r\n\t ]+D & operator=\\(D const ?&\\);\[\r\n\t ]+D\\((D const|const D) ?&\\);\[\r\n\t \]+D\\((void|)\\);\r\n\[\t \]*int dfoo\\((void|)\\);\r\n\[\t \]*int foo\\((void|)\\);\r\n\}.*$gdb_prompt $" { pass "ptype d_instance" } + -re "type = class D : private A, public B, (protected|private) C \{\r\n\[\t \]*public:\r\n\[\t \]*int d;\r\n\[\t \]*int dd;\[\r\n\t \]+D\\(void\\);\r\n\[\t \]*int dfoo\\((void|)\\);\r\n\[\t \]*int foo\\((void|)\\);\r\n\}.*$gdb_prompt $" { pass "ptype d_instance" } + -re ".*$gdb_prompt $" { fail "ptype d_instance" } + timeout { fail "(timeout) ptype d_instance" } + } + } else { + send_gdb "ptype d_instance\n" + gdb_expect { + -re "type = class D : private A, public B, protected C \{\r\n\[\t \]*public:\r\n\[\t \]*int d;\r\n\[\t \]*int dd;\[\r\n\t \]+D\\(void\\);\r\n\[\t \]*int dfoo\\((void|)\\);\r\n\[\t \]*int foo\\((void|)\\);\r\n\}.*$gdb_prompt $" { pass "ptype d_instance" } + -re ".*$gdb_prompt $" { fail "ptype d_instance" } + timeout { fail "(timeout) ptype d_instance" } + } + } + + +send_gdb "print e_instance\n" +gdb_expect { + -re ".\[0-9\]* = \{ = \{a = 1, aa = 2\}, = \{b = 3, bb = 4\}, = \{c = 5, cc = 6\}, e = 9, ee = 10\}\r\n$gdb_prompt $" { + pass "print value of e_instance" + } + -re ".\[0-9\]* = \{ = \{a = 1, aa = 2\}, = \{b = 3, bb = 4\}, = \{c = 5, cc = 6\}, e = 9, ee = 10\}\r\n$gdb_prompt $" { + pass "print value of e_instance" + } + -re ".*$gdb_prompt $" { fail "print value of e_instance" } + timeout { fail "(timeout) print value of e_instance" } + } + + if { [test_compiler_info gcc-*] } then { + send_gdb "ptype e_instance\n" + gdb_expect { + -re "type = class E : public A, private B, (protected|private) C \{\r\n\[\t \]*public:\r\n\[\t \]*int e;\r\n\[\t \]*int ee;\[\r\n\t ]+E & operator=\\(E const ?&\\);\[\r\n\t ]+E\\((E const|const E) ?&\\);\[\r\n\t \]+E\\((void|)\\);\r\n\[\t \]*int efoo\\((void|)\\);\r\n\[\t \]*int foo\\((void|)\\);\r\n\}.*$gdb_prompt $" { pass "ptype e_instance" } + -re "type = class E : public A, private B, (protected|private) C \{\r\n\[\t \]*public:\r\n\[\t \]*int e;\r\n\[\t \]*int ee;\[\r\n\t \]+E\\((void|)\\);\r\n\[\t \]*int efoo\\((void|)\\);\r\n\[\t \]*int foo\\((void|)\\);\r\n\}.*$gdb_prompt $" { pass "ptype e_instance" } + -re ".*$gdb_prompt $" { fail "ptype e_instance" } + timeout { fail "(timeout) ptype e_instance" } + } + } else { + send_gdb "ptype e_instance\n" + gdb_expect { + -re "type = class E : public A, private B, protected C \{\r\n\[\t \]*public:\r\n\[\t \]*int e;\r\n\[\t \]*int ee;\[\r\n\t \]+E\\((void|)\\);\r\n\[\t \]*int efoo\\((void|)\\);\r\n\[\t \]*int foo\\((void|)\\);\r\n\}.*$gdb_prompt $" { pass "ptype e_instance" } + -re ".*$gdb_prompt $" { fail "ptype e_instance" } + timeout { fail "(timeout) ptype e_instance" } + } + } + + +send_gdb "print f_instance\n" +gdb_expect { + -re ".\[0-9\]* = \{ = \{a = 1, aa = 2\}, = \{b = 3, bb = 4\}, = \{c = 5, cc = 6\}, f = 11, ff = 12\}\r\n$gdb_prompt $" { + pass "print value of f_instance" + } + -re ".\[0-9\]* = \{ = \{a = 1, aa = 2\}, = \{b = 3, bb = 4\}, = \{c = 5, cc = 6\}, f = 11, ff = 12\}\r\n$gdb_prompt $" { + pass "print value of f_instance" + } + -re ".*$gdb_prompt $" { fail "print value of f_instance" } + timeout { fail "(timeout) print value of f_instance" } + } + +send_gdb "ptype f_instance\n" +gdb_expect { + -re "type = class F : private A, public B, private C \{\r\n\[\t \]*public:\r\n\[\t \]*int f;\r\n\[\t \]*int ff;\[\r\n\t ]+F & operator=\\(F const ?&\\);\[\r\n\t ]+F\\((F const|const F) ?&\\);\[\r\n\t \]+F\\((void|)\\);\r\n\[\t \]*int ffoo\\((void|)\\);\r\n\[\t \]*int foo\\((void|)\\);\r\n\}.*$gdb_prompt $" { pass "ptype f_instance" } + -re "type = class F : private A, public B, private C \{\r\n\[\t \]*public:\r\n\[\t \]*int f;\r\n\[\t \]*int ff;\[\r\n\t \]+F\\((void|)\\);\r\n\[\t \]*int ffoo\\((void|)\\);\r\n\[\t \]*int foo\\((void|)\\);\r\n\}.*$gdb_prompt $" { pass "ptype f_instance" } + -re ".*$gdb_prompt $" { fail "ptype f_instance" } + timeout { fail "(timeout) ptype f_instance" } +} + + + +send_gdb "print d_instance.a\n" +gdb_expect { + -re ".\[0-9\]* = 1.*$gdb_prompt $" { + pass "print value of d_instance.a" + } + -re ".*$gdb_prompt $" { fail "print value of d_instance.a" } + timeout { fail "(timeout) print value of d_instance.a" } + } + +send_gdb "print d_instance.aa\n" +gdb_expect { + -re ".\[0-9\]* = 2.*$gdb_prompt $" { + pass "print value of d_instance.aa" + } + -re ".*$gdb_prompt $" { fail "print value of d_instance.aa" } + timeout { fail "(timeout) print value of d_instance.aa" } + } + +send_gdb "print d_instance.b\n" +gdb_expect { + -re ".\[0-9\]* = 3.*$gdb_prompt $" { + pass "print value of d_instance.b" + } + -re ".*$gdb_prompt $" { fail "print value of d_instance.b" } + timeout { fail "(timeout) print value of d_instance.b" } + } + +send_gdb "print d_instance.bb\n" +gdb_expect { + -re ".\[0-9\]* = 4.*$gdb_prompt $" { + pass "print value of d_instance.bb" + } + -re ".*$gdb_prompt $" { fail "print value of d_instance.bb" } + timeout { fail "(timeout) print value of d_instance.bb" } + } + +send_gdb "print d_instance.c\n" +gdb_expect { + -re ".\[0-9\]* = 5.*$gdb_prompt $" { + pass "print value of d_instance.c" + } + -re ".*$gdb_prompt $" { fail "print value of d_instance.c" } + timeout { fail "(timeout) print value of d_instance.c" } + } + +send_gdb "print d_instance.cc\n" +gdb_expect { + -re ".\[0-9\]* = 6.*$gdb_prompt $" { + pass "print value of d_instance.cc" + } + -re ".*$gdb_prompt $" { fail "print value of d_instance.cc" } + timeout { fail "(timeout) print value of d_instance.cc" } + } + +send_gdb "print d_instance.d\n" +gdb_expect { + -re ".\[0-9\]* = 7.*$gdb_prompt $" { + pass "print value of d_instance.d" + } + -re ".*$gdb_prompt $" { fail "print value of d_instance.d" } + timeout { fail "(timeout) print value of d_instance.d" } + } + +send_gdb "print d_instance.dd\n" +gdb_expect { + -re ".\[0-9\]* = 8.*$gdb_prompt $" { + pass "print value of d_instance.dd" + } + -re ".*$gdb_prompt $" { fail "print value of d_instance.dd" } + timeout { fail "(timeout) print value of d_instance.dd" } + } + +send_gdb "print g_instance.a\n" +gdb_expect { + -re "warning.*$gdb_prompt $" { + # The compiler doesn't think this is ambiguous. + fail "print value of g_instance.a" + } + -re ".\[0-9\]* = 15.*$gdb_prompt $" { + pass "print value of g_instance.a" + } + -re ".*$gdb_prompt $" { fail "print value of g_instance.a" } + timeout { fail "(timeout) print value of g_instance.a" } + } + +send_gdb "print g_instance.b\n" +gdb_expect { + -re "warning.*$gdb_prompt $" { + # The compiler doesn't think this is ambiguous. + fail "print value of g_instance.b" + } + -re ".\[0-9\]* = 16.*$gdb_prompt $" { + pass "print value of g_instance.b" + } + -re ".*$gdb_prompt $" { fail "print value of g_instance.b" } + timeout { fail "(timeout) print value of g_instance.b" } + } + +send_gdb "print g_instance.c\n" +gdb_expect { + -re "warning.*$gdb_prompt $" { + # The compiler doesn't think this is ambiguous. + fail "print value of g_instance.c" + } + -re ".\[0-9\]* = 17.*$gdb_prompt $" { + pass "print value of g_instance.c" + } + -re ".*$gdb_prompt $" { fail "print value of g_instance.c" } + timeout { fail "(timeout) print value of g_instance.c" } + } + +send_gdb "print g_instance.afoo()\n" +gdb_expect { + -re ".\[0-9\]* = 1.*$gdb_prompt $" { + pass "print value of g_instance.afoo()" + } + -re ".*$gdb_prompt $" { fail "print value of g_instance.afoo()" } + timeout { fail "(timeout) print value of g_instance.afoo()" } + } + + +# If GDB fails to restore the selected frame properly after the +# inferior function call above (see GDB PR 1155 for an explanation of +# why this might happen), all the subsequent tests will fail. We +# should detect report that failure, but let the marker call finish so +# that the rest of the tests can run undisturbed. +gdb_test_multiple "frame" "re-selected 'main' frame after inferior call" { + -re "#0 marker1.*$gdb_prompt $" { + setup_kfail "gdb/1155" s390-*-linux-gnu + fail "re-selected 'main' frame after inferior call" + gdb_test "finish" ".*main.*at .*derivation.cc:.*// marker1-returns-here.*" \ + "finish call to marker1" + } + -re "#1 ($hex in )?main.*$gdb_prompt $" { + pass "re-selected 'main' frame after inferior call" + } +} + +send_gdb "print g_instance.bfoo()\n" +gdb_expect { + -re ".\[0-9\]* = 2.*$gdb_prompt $" { + pass "print value of g_instance.bfoo()" + } + -re ".*$gdb_prompt $" { fail "print value of g_instance.bfoo()" } + timeout { fail "(timeout) print value of g_instance.bfoo()" } + } + +send_gdb "print g_instance.cfoo()\n" +gdb_expect { + -re ".\[0-9\]* = 3.*$gdb_prompt $" { + pass "print value of g_instance.cfoo()" + } + -re ".*$gdb_prompt $" { fail "print value of g_instance.cfoo()" } + timeout { fail "(timeout) print value of g_instance.cfoo()" } + } diff --git a/gdb/testsuite/gdb.cp/gdb1355.cc b/gdb/testsuite/gdb.cp/gdb1355.cc new file mode 100644 index 0000000..a53ca20 --- /dev/null +++ b/gdb/testsuite/gdb.cp/gdb1355.cc @@ -0,0 +1,35 @@ +struct mystruct +{ + int m_int; + char m_char; + long int m_long_int; + unsigned int m_unsigned_int; + long unsigned int m_long_unsigned_int; + // long long int m_long_long_int; + // long long unsigned int m_long_long_unsigned_int; + short int m_short_int; + short unsigned int m_short_unsigned_int; + unsigned char m_unsigned_char; + float m_float; + double m_double; + long double m_long_double; + // complex int m_complex_int; + // complex float m_complex_float; + // complex long double m_complex_long_double; + // wchar_t m_wchar_t; + bool m_bool; +}; + +struct mystruct s1 = +{ + 117, 'a', 118, 119, 120, + // 121, 122, + 123, 124, 'b', 125.0, 126.0, 127.0, + // complex int, complex float, complex long double, wchar_t, + true +}; + +int main () +{ + return 0; +} diff --git a/gdb/testsuite/gdb.cp/gdb1355.exp b/gdb/testsuite/gdb.cp/gdb1355.exp new file mode 100644 index 0000000..11f16d5 --- /dev/null +++ b/gdb/testsuite/gdb.cp/gdb1355.exp @@ -0,0 +1,119 @@ +# Copyright 2003 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# Tests for PR gdb/1355, which is a reference to PR gcc/12066. +# 2003-08-26 Michael Chastain + +# This file is part of the gdb testsuite. + +set ws "\[\r\n\t \]*" +set nl "\[\r\n\]+" + +if $tracelevel then { + strace $tracelevel + } + +if { [skip_cplus_tests] } { continue } + +# +# test running programs +# +set prms_id 0 +set bug_id 0 + +set testfile "gdb1355" +set srcfile ${testfile}.cc +set binfile ${objdir}/${subdir}/${testfile} + +if { [gdb_compile "${srcdir}/${subdir}/${srcfile}" "${binfile}" executable {debug c++}] != "" } { + gdb_suppress_entire_file "Testcase compile failed, so all tests in this file will automatically fail." +} + +if [get_compiler_info ${binfile} "c++"] { + return -1 +} + +gdb_exit +gdb_start +gdb_reinitialize_dir $srcdir/$subdir +gdb_load ${binfile} + +if ![runto_main] then { + perror "couldn't run to main" + continue +} + +# See http://sources.redhat.com/gdb/bugs/1355 +# See http://gcc.gnu.org/bugzilla/show_bug.cgi?id=12066 +# +# g++ -gstabs+ does not emit stabs for fundamental types. +# They get emitted later inside other types, so they have no names +# and gdb cannot handle them. + +set s_head "${ws}(struct|class) mystruct \{(${ws}public:|)" +set s_tail ".*" + +set f_i "${ws}int m_int;" +set f_c "${ws}char m_char;" +set f_li "${ws}long int m_long_int;" +set f_ui "${ws}unsigned int m_unsigned_int;" +set f_lui "${ws}long unsigned int m_long_unsigned_int;" +set f_si "${ws}short int m_short_int;" +set f_sui "${ws}short unsigned int m_short_unsigned_int;" +set f_uc "${ws}unsigned char m_unsigned_char;" +set f_f "${ws}float m_float;" +set f_d "${ws}double m_double;" +set f_ld "${ws}long double m_long_double;" +set f_b "${ws}bool m_bool;" + +set itc "" +set bad_i "${ws}(${itc}|int) m_int;"; +set bad_c "${ws}(${itc}|char) m_char;" +set bad_li "${ws}(${itc}|long int) m_long_int;" +set bad_ui "${ws}(${itc}|unsigned int) m_unsigned_int;" +set bad_lui "${ws}(${itc}|long unsigned int) m_long_unsigned_int;" +set bad_si "${ws}(${itc}|short int) m_short_int;" +set bad_sui "${ws}(${itc}|short unsigned int) m_short_unsigned_int;" +set bad_uc "${ws}(${itc}|unsigned char) m_unsigned_char;" +set bad_f "${ws}(${itc}|float) m_float;" +set bad_d "${ws}(${itc}|double) m_double;" +set bad_ld "${ws}(${itc}|long double) m_long_double;" +set bad_b "${ws}(${itc}|bool) m_bool;" + +gdb_test_multiple "ptype s1" "ptype s1" { + -re "type = ${s_head}${f_i}${f_c}${f_li}${f_ui}${f_lui}${f_si}${f_sui}${f_uc}${f_f}${f_d}${f_ld}${f_b}${s_tail}\}$nl$gdb_prompt $" { + pass "ptype s1" + } + -re "type = ${s_head}${bad_i}${bad_c}${bad_li}${bad_ui}${bad_lui}${bad_si}${bad_sui}${bad_uc}${bad_f}${bad_d}${bad_ld}${bad_b}${s_tail}\}$nl$gdb_prompt $" { + # This happened with gcc HEAD 2003-08-20 08:00:00 UTC, -gstabs+. + kfail "gdb/1355" "ptype s1" + } +} + +gdb_test_multiple "print s1" "print s1" { + -re "$decimal = \{m_int = 117, m_char = 97 'a', m_long_int = 118, m_unsigned_int = 119, m_long_unsigned_int = 120, m_short_int = 123, m_short_unsigned_int = 124, m_unsigned_char = 98 'b', m_float = 125, m_double = 126, m_long_double = 127, m_bool = true\}$nl$gdb_prompt $" { + pass "print s1" + } + -re "$decimal = \{m_int = 117, m_char = 97 'a', m_long_int = 118, m_unsigned_int = 119, m_long_unsigned_int = 120, m_short_int = 123, m_short_unsigned_int = 124, m_unsigned_char = 98 'b', m_float = 125, m_double = 126, m_long_double = 127, m_bool = 117\}$nl$gdb_prompt $" { + # This pattern is very picky, but if more different output + # shows up, I can just add more arms. -- chastain 2003-08-26 + # + # This happened with gcc HEAD 2003-08-20 08:00:00 UTC, -gstabs+. + # Look at the value of m_bool. It looks like gdb latched onto + # random int type and then used the data at structure offset 0. + kfail "gdb/1355" "print s1" + } +} diff --git a/gdb/testsuite/gdb.cp/hang.H b/gdb/testsuite/gdb.cp/hang.H new file mode 100644 index 0000000..26fec87 --- /dev/null +++ b/gdb/testsuite/gdb.cp/hang.H @@ -0,0 +1,12 @@ +struct A +{ + struct B *b_ptr_in_a; +}; + +struct C +{ + struct B + { + int member_of_B_in_C; + }; +}; diff --git a/gdb/testsuite/gdb.cp/hang.exp b/gdb/testsuite/gdb.cp/hang.exp new file mode 100644 index 0000000..4c117a1 --- /dev/null +++ b/gdb/testsuite/gdb.cp/hang.exp @@ -0,0 +1,128 @@ +# Copyright (C) 2002 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# Please email any bugs, comments, and/or additions to this file to: +# bug-gdb@prep.ai.mit.edu + +if $tracelevel then { + strace $tracelevel +} + +set prms_id 0 +set bug_id 0 + +if { [skip_cplus_tests] } { continue } + +set testfile hang +set binfile ${objdir}/${subdir}/${testfile} + +foreach file {hang1 hang2 hang3} { + if {[gdb_compile "${srcdir}/${subdir}/${file}.C" "${file}.o" object {c++ debug}] != ""} { + gdb_suppress_entire_file "Testcase compile failed, so all tests in this file will automatically fail." + } +} + +if {[gdb_compile "hang1.o hang2.o hang3.o" ${binfile} executable {c++ debug}] != "" } { + gdb_suppress_entire_file "Testcase compile failed, so all tests in this file will automatically fail." +} + + +gdb_exit +gdb_start +gdb_reinitialize_dir $srcdir/$subdir +gdb_load ${binfile} + + +# As of May 1, 2002, GDB hangs trying to read the debug info for the +# `hang2.o' compilation unit from the executable `hang', when compiled +# by g++ 2.96 with STABS debugging info. Here's what's going on, as +# best as I can tell. +# +# The definition of `struct A' in `hang.H' refers to `struct B' as an +# incomplete type. The stabs declare type number (1,3) to be a cross- +# reference type, `xsB:'. +# +# The definition of `struct C' contains a nested definition for +# `struct B' --- or more properly, `struct C::B'. However, the stabs +# fail to qualify the structure tag: it just looks like a definition +# for `struct B'. I think this is a compiler bug, but perhaps GCC +# doesn't emit qualified names for a reason. +# +# `hang.H' gets #included by both `hang1.C' and `hang2.C'. So the +# stabs for `struct A', the incomplete `struct B', and `struct C' +# appear in both hang1.o's and hang2.o's stabs. +# +# When those two files are linked together, since hang2.o appears +# later in the command line, its #inclusion of `hang.H' gets replaced +# with an N_EXCL stab, referring back to hang1.o's stabs for the +# header file. +# +# When GDB builds psymtabs for the executable hang, it notes that +# hang2.o's stabs contain an N_EXCL referring to a header that appears +# in full in hang1.o's stabs. So hang2.o's psymtab lists a dependency +# on hang1.o's psymtab. +# +# When the user types the command `print var_in_b', GDB scans the +# psymtabs for a symbol by that name, and decides to read full symbols +# for `hang2.o'. +# +# Since `hang2.o''s psymtab lists `hang1.o' as a dependency, GDB first +# reads `hang1.o''s symbols. When GDB sees `(1,3)=xsB:', it creates a +# type object for `struct B', sets its TYPE_FLAG_STUB flag, and +# records it as type number `(1,3)'. +# +# When GDB finds the definition of `struct C::B', since the stabs +# don't indicate that the type is nested within C, it treats it as +# a definition of `struct B'. +# +# When GDB is finished reading `hang1.o''s symbols, it calls +# `cleanup_undefined_types'. This function mistakes the definition of +# `struct C::B' for a definition for `struct B', and overwrites the +# incomplete type object for the real `struct B', using `memcpy'. Now +# stabs type number `(1,3)' refers to this (incorrect) complete type. +# Furthermore, the `memcpy' simply copies the original's `cv_type' +# field to the target, giving the target a corrupt `cv_type' ring: the +# chain does not point back to the target type. +# +# Having satisfied `hang2.o''s psymtab's dependencies, GDB begins to +# read `hang2.o''s symbols. These contain the true definition for +# `struct B', which refers to type number `(1,3)' as the type it's +# defining. GDB looks up type `(1,3)', and finds the (incorrect) +# complete type established by the call to `cleanup_undefined_types' +# above. However, it doesn't notice that the type is already defined, +# and passes it to `read_struct_type', which then writes the new +# definition's size, field list, etc. into the type object which +# already has those fields initialized. Adding insult to injury, +# `read_struct_type' then calls `finish_cv_type'; since the `memcpy' +# in `cleanup_undefined_types' corrupted the target type's `cv_type' +# ring, `finish_cv_type' enters an infinite loop. + +# This checks that GDB recognizes when a structure is about to be +# overwritten, and refuses, with a complaint. +gdb_test "print var_in_b" " = 1729" "doesn't overwrite struct type" + +# This checks that cleanup_undefined_types doesn't create corrupt +# cv_type chains. Note that var_in_hang3 does need to be declared in +# a separate compilation unit, whose psymtab depends on hang1.o's +# psymtab. Otherwise, GDB won't call cleanup_undefined_types (as it +# finishes hang1.o's symbols) before it calls make_cv_type (while +# reading hang3.o's symbols). +# +# The bug only happens when you compile with -gstabs+; Otherwise, GCC +# won't include the `const' qualifier on `const_B_ptr' in `hang3.o''s +# STABS, so GDB won't try to create a const variant of the smashed +# struct type, and get caught by the corrupted cv_type chain. +gdb_test "print var_in_hang3" " = 42" "doesn't corrupt cv_type chain" diff --git a/gdb/testsuite/gdb.cp/hang1.C b/gdb/testsuite/gdb.cp/hang1.C new file mode 100644 index 0000000..4b04d77 --- /dev/null +++ b/gdb/testsuite/gdb.cp/hang1.C @@ -0,0 +1,3 @@ +#include "hang.H" + +int main (int argc, char **argv) { return 0; } diff --git a/gdb/testsuite/gdb.cp/hang2.C b/gdb/testsuite/gdb.cp/hang2.C new file mode 100644 index 0000000..59732f8 --- /dev/null +++ b/gdb/testsuite/gdb.cp/hang2.C @@ -0,0 +1,8 @@ +#include "hang.H" + +struct B +{ + int member_of_B; +}; + +int var_in_b = 1729; diff --git a/gdb/testsuite/gdb.cp/hang3.C b/gdb/testsuite/gdb.cp/hang3.C new file mode 100644 index 0000000..92c82fa --- /dev/null +++ b/gdb/testsuite/gdb.cp/hang3.C @@ -0,0 +1,4 @@ +#include "hang.H" + +const struct B *const_B_ptr; +int var_in_hang3 = 42; diff --git a/gdb/testsuite/gdb.cp/inherit.exp b/gdb/testsuite/gdb.cp/inherit.exp new file mode 100644 index 0000000..993bfb1 --- /dev/null +++ b/gdb/testsuite/gdb.cp/inherit.exp @@ -0,0 +1,1018 @@ +# Copyright 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 +# Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# Please email any bugs, comments, and/or additions to this file to: +# bug-gdb@prep.ai.mit.edu + +# This file was written by Fred Fish. (fnf@cygnus.com) + +set ws "\[\r\n\t \]+" +set nl "\[\r\n\]+" + +# The format of a g++ virtual base pointer. +set vbptr "(_vb\[$.\]|__vb_)\[0-9\]?" + +if $tracelevel then { + strace $tracelevel +} + +if { [skip_cplus_tests] } { continue } + +# Note - create separate "inherit" executable from misc.cc + +set testfile "inherit" +set srcfile misc.cc +set binfile ${objdir}/${subdir}/${testfile} + + +# Create and source the file that provides information about the compiler +# used to compile the test case. + +if [get_compiler_info ${binfile} "c++"] { + return -1 +} + +if { [gdb_compile "${srcdir}/${subdir}/${srcfile}" "${binfile}" executable {debug c++}] != "" } { + gdb_suppress_entire_file "Testcase compile failed, so all tests in this file will automatically fail." +} + +# +# Single inheritance, print individual members. +# + +proc test_print_si_members {} { + # Print all members of g_A using fully qualified form. + + gdb_test "print g_A.A::a" ".* = 1" "print g_A.A::a" + + gdb_test "print g_A.A::x" ".* = 2" "print g_A.A::x" + + # Print members of g_A using nonambiguous compact form. + + gdb_test "print g_A.a" ".* = 1" "print g_A.a" + + gdb_test "print g_A.x" ".* = 2" "print g_A.x" + + # Print all members of g_B using fully qualified form. + + gdb_test "print g_B.A::a" ".* = 3" "print g_B.A::a" + + gdb_test "print g_B.A::x" ".* = 4" "print g_B.A::x" + + gdb_test "print g_B.B::b" ".* = 5" "print g_B.B::b" + + gdb_test "print g_B.B::x" ".* = 6" "print g_B.B::x" + + # Print members of g_B using nonambiguous compact form. + + gdb_test "print g_B.a" ".* = 3" "print g_B.a" + + gdb_test "print g_B.b" ".* = 5" "print g_B.b" + + gdb_test "print g_B.x" ".* = 6" "print g_B.x" + + # Print all members of g_C using fully qualified form. + + gdb_test "print g_C.A::a" ".* = 7" "print g_C.A::a" + + gdb_test "print g_C.A::x" ".* = 8" "print g_C.A::x" + + gdb_test "print g_C.C::c" ".* = 9" "print g_C.C::c" + + gdb_test "print g_C.C::x" ".* = 10" "print g_C.C::x" + + # Print members of g_C using nonambiguous compact form. + + gdb_test "print g_C.a" ".* = 7" "print g_C.a" + + gdb_test "print g_C.c" ".* = 9" "print g_C.c" + + gdb_test "print g_C.x" ".* = 10" "print g_C.x" +} + +# +# Single inheritance, print type definitions. +# + +proc test_ptype_si {} { + global gdb_prompt + global ws + global nl + global hp_aCC_compiler + + # Print class A as a type. + + send_gdb "ptype A\n" + gdb_expect { + -re "type = class A \{$nl.*\[ \]*int a;$nl\[ \]*int x;$nl.*\[ \]*\}$nl$gdb_prompt $" { + pass "ptype A (FIXME)" + } + -re "type = struct A \{$nl\[ \]*int a;$nl\[ \]*int x;$nl\[ \]*\}$nl$gdb_prompt $" { + setup_xfail "*-*-*" + fail "ptype A (FIXME)" + } + -re ".*$gdb_prompt $" { fail "ptype A" } + timeout { fail "ptype A (timeout)" ; return } + } + + # Print class A as an explicit class. + + send_gdb "ptype class A\n" + gdb_expect { + -re "type = class A \{$nl.*\[ \]*int a;$nl\[ \]*int x;$nl.*\[ \]*\}$nl$gdb_prompt $" { + pass "ptype class A (FIXME)" + } + -re "type = struct A \{$nl\[ \]*int a;$nl\[ \]*int x;$nl\[ \]*\}$nl$gdb_prompt $" { + if {!$hp_aCC_compiler} {setup_xfail "*-*-*"} + fail "ptype class A (FIXME)" + } + -re ".*$gdb_prompt $" { fail "ptype class A" } + timeout { fail "ptype class A (timeout)" ; return } + } + + # Print type of an object of type A. + + send_gdb "ptype g_A\n" + gdb_expect { + -re "type = class A \{$nl.*\[ \]*int a;$nl\[ \]*int x;$nl.*\[ \]*\}$nl$gdb_prompt $" { + pass "ptype g_A (FIXME)" + } + -re "type = struct A \{$nl\[ \]*int a;$nl\[ \]*int x;$nl\[ \]*\}$nl$gdb_prompt $" { + if {!$hp_aCC_compiler} {setup_xfail "*-*-*"} + fail "ptype g_A (FIXME)" + } + -re ".*$gdb_prompt $" { fail "ptype g_A" } + timeout { fail "ptype g_A (timeout)" ; return } + } + + # Print class B as a type. + + gdb_test "ptype B" "type = class B : public A \{$nl\[ \]*public:$nl\[ \]*int b;$nl\[ \]*int x;$nl.*\}" "ptype B" + + # Print class B as an explicit class. + + gdb_test "ptype class B" "type = class B : public A \{$nl\[ \]*public:$nl\[ \]*int b;$nl\[ \]*int x;$nl.*\}" "ptype class B" + + # Print type of an object of type B. + + gdb_test "ptype g_B" "type = class B : public A \{$nl\[ \]*public:$nl\[ \]*int b;$nl\[ \]*int x;$nl.*\}" "ptype g_B" + + # Print class C as a type. + + gdb_test "ptype C" "type = class C : public A \{$nl\[ \]*public:$nl\[ \]*int c;$nl\[ \]*int x;$nl.*\}" "ptype C" + + # Print class C as an explicit class. + + gdb_test "ptype class C" "type = class C : public A \{$nl\[ \]*public:$nl\[ \]*int c;$nl\[ \]*int x;$nl.*\}" "ptype class C" + + # Print type of an object of type g_C. + + gdb_test "ptype g_C" "type = class C : public A \{$nl\[ \]*public:$nl\[ \]*int c;$nl\[ \]*int x;$nl.*\}" "ptype g_C" + + # gcc cygnus-2.3.3 (Q1) has this bug, but it was fixed as of + # cygnus-2.3.3-930417. PR 2819. + send_gdb "ptype tagless_struct\n" + gdb_expect { + -re "type = class \{${ws}public:${ws}int one;${ws}int two;${ws}tagless_struct & operator=\\(tagless_struct (const ?)?&\\);${ws}tagless_struct\\(tagless_struct (const ?)?&\\);${ws}tagless_struct\\(\\);${ws}\}$nl$gdb_prompt $" { + pass "ptype tagless struct" + } + -re "type = class \{${ws}public:${ws}int one;${ws}int two;;${ws}\}$nl$gdb_prompt $" { + pass "ptype tagless struct" + } + -re "type = (struct|class).*\{.*int one;.*int two;.*\}$nl$gdb_prompt $" { + pass "ptype tagless struct (obsolete gcc or gdb)" + } + -re ".*$gdb_prompt $" { + fail "ptype tagless struct" + } + timeout { + fail "ptype tagless struct (timeout)" + } + } + + send_gdb "ptype v_tagless\n" + gdb_expect { + -re "type = class \{${ws}public:${ws}int one;${ws}int two;${ws}tagless_struct & operator=\\(tagless_struct (const ?)?&\\);${ws}tagless_struct\\(tagless_struct (const ?)?&\\);${ws}tagless_struct\\(\\);${ws}\}$nl$gdb_prompt $" { + pass "ptype variable of type tagless struct" + } + -re "type = class \{${ws}public:${ws}int one;${ws}int two;;${ws}\}$nl$gdb_prompt $" { + pass "ptype tagless struct" + } + -re "type = (struct|class).*\{.*int one;.*int two;.*\}$nl$gdb_prompt $" { + pass "ptype variable of type tagless struct (obsolete gcc or gdb)" + } + -re ".*$gdb_prompt $" { + fail "ptype variable of type tagless struct" + } + timeout { + fail "ptype variable of type tagless struct (timeout)" + } + } +} + +# +# Single inheritance, print complete classes. +# + +proc test_print_si_classes {} { + # Print all members of g_A. + + gdb_test "print g_A" ".* = \{a = 1, x = 2\}" "print g_A" + + # Print all members of g_B. + + gdb_test "print g_B" ".* = \{\<(class |)A\> = \{a = 3, x = 4\}, b = 5, x = 6\}" "print g_B" + + # Print all members of g_C. + + gdb_test "print g_C" ".* = \{\<(class |)A\> = \{a = 7, x = 8\}, c = 9, x = 10\}" "print g_C" +} + +# +# Single inheritance, print anonymous unions. +# GDB versions prior to 4.14 entered an infinite loop when printing +# the type of a class containing an anonymous union, and they were also +# incapable of printing the member of an anonymous union. +# We test the printing of the member first, and perform the other tests +# only if the test succeeds, to avoid the infinite loop. +# + +proc test_print_anon_union {} { + global gdb_prompt + global ws + global nl + + gdb_test "print g_anon_union.a" ".* = 2" "print anonymous union member" + send_gdb "print g_anon_union\n" + gdb_expect { + -re ".* = \{one = 1, ( = |)\{a = 2, b = 2\}\}$nl$gdb_prompt $" { + pass "print variable of type anonymous union" + } + -re ".* = .*\{one = 1, ( = |)\{a = 2, b = .*\}\}$nl$gdb_prompt $" { + pass "print variable of type anonymous union (obsolete gcc or gdb)" + } + -re ".*$nl$gdb_prompt $" { + fail "print variable of type anonymous union" + } + timeout { + fail "print variableof type anonymous union (timeout)" + } + } + send_gdb "ptype g_anon_union\n" + gdb_expect { + -re "type = class class_with_anon_union \{${ws}public:${ws}int one;${ws}union \{${ws}public:${ws}int a;${ws}long int b;${ws}union \{\.\.\.\} & operator=\\(union \{\.\.\.\} &\\);${ws}\\\$_0 \\(union \{\.\.\.\} &\\);${ws}\\\$_0 \\(\\);${ws}\};${ws}class_with_anon_union & operator=\\(class_with_anon_union const &\\);${ws}class_with_anon_union\\(class_with_anon_union const &\\);${ws}class_with_anon_union\\(void\\);${ws}\}$nl$gdb_prompt $" { + pass "print type of anonymous union" + } + -re "type = class class_with_anon_union \{${ws}public:${ws}int one;${ws}union \{${ws}int a;${ws}long int b;${ws}\};${ws}class_with_anon_union & operator=\\(class_with_anon_union const ?&\\);${ws}class_with_anon_union\\(class_with_anon_union const ?&\\);${ws}class_with_anon_union\\((void|)\\);${ws}\}$nl$gdb_prompt $" { + pass "print type of anonymous union" + } + -re "type = class class_with_anon_union \{${ws}public:${ws}int one;${ws}union \{${ws}int a;${ws}long int b;${ws}\};${ws}\}$nl$gdb_prompt $" { + pass "print type of anonymous union" + } + -re "type = (struct|class).*\{.*int one;.*union \{.*int a;.*(long|long int|int) b;.*\};.*\}$nl$gdb_prompt $" { + pass "print type of anonymous union (obsolete gcc or gdb)" + } + -re ".*$nl$gdb_prompt $" { + fail "print type of anonymous union" + } + timeout { + fail "print type of anonymous union (timeout)" + } + } +} + +# +# Multiple inheritance, print individual members. +# + +proc test_print_mi_members {} { + global gdb_prompt + global nl + global hp_aCC_compiler + + # Print all members of g_A. + + gdb_test "print g_A.A::a" ".* = 1" "print g_A.A::a" + + gdb_test "print g_A.A::x" ".* = 2" "print g_A.A::x" + + # Print all members of g_B. + + gdb_test "print g_B.A::a" ".* = 3" "print g_B.A::a" + + gdb_test "print g_B.A::x" ".* = 4" "print g_B.A::x" + + gdb_test "print g_B.B::b" ".* = 5" "print g_B.B::b" + + gdb_test "print g_B.B::x" ".* = 6" "print g_B.B::x" + + # Print all members of g_C. + + gdb_test "print g_C.A::a" ".* = 7" "print g_C.A::a" + + gdb_test "print g_C.A::x" ".* = 8" "print g_C.A::x" + + gdb_test "print g_C.C::c" ".* = 9" "print g_C.C::c" + + gdb_test "print g_C.C::x" ".* = 10" "print g_C.C::x" + + # Print all members of g_D. + + # The following is ambiguous, and gdb should detect this. + # For now, accept gdb's behavior as an expected failure if it + # simply prints either member correctly. + + send_gdb "print g_D.A::a\n" + gdb_expect { + -re "warning: A ambiguous; using D::C::A. Use a cast to disambiguate.$nl\\$\[0-9\]* = 15$nl$gdb_prompt $" { + pass "print g_D.A::a" + } + -re "warning: A ambiguous; using D::B::A. Use a cast to disambiguate.$nl\\$\[0-9\]* = 11$nl$gdb_prompt $" { + pass "print g_D.A::a (using B)" + } + -re ".* = 15$nl$gdb_prompt $" { + kfail "gdb/68" "print g_D.A::a" + } + -re ".* = 11$nl$gdb_prompt $" { + kfail "gdb/68" "print g_D.A::a" + } + -re ".*$gdb_prompt $" { fail "print g_D.A::a" } + timeout { fail "print g_D.A::a (timeout)" ; return } + } + + # The following is ambiguous, and gdb should detect this. + # For now, accept gdb's behavior as an expected failure if it + # simply prints either member correctly. + + send_gdb "print g_D.A::x\n" + gdb_expect { + -re "warning: A ambiguous; using D::C::A. Use a cast to disambiguate.$nl\\$\[0-9\]* = 16$nl$gdb_prompt $" { + pass "print g_D.A::x" + } + -re "warning: A ambiguous; using D::B::A. Use a cast to disambiguate.$nl\\$\[0-9\]* = 12$nl$gdb_prompt $" { + pass "print g_D.A::x (using B)" + } + -re ".* = 16$nl$gdb_prompt $" { + kfail "gdb/68" "print g_D.A::x" + } + -re ".* = 12$nl$gdb_prompt $" { + kfail "gdb/68" "print g_D.A::x" + } + -re ".*$gdb_prompt $" { fail "print g_D.A::x" } + timeout { fail "print g_D.A::x (timeout)" ; return } + } + + gdb_test "print g_D.B::b" ".* = 13" "print g_D.B::b" + + gdb_test "print g_D.B::x" ".* = 14" "print g_D.B::x" + + gdb_test "print g_D.C::c" ".* = 17" "print g_D.C::c" + + gdb_test "print g_D.C::x" ".* = 18" "print g_D.C::x" + + gdb_test "print g_D.D::d" ".* = 19" "print g_D.D::d" + + gdb_test "print g_D.D::x" ".* = 20" "print g_D.D::x" + + # Print all members of g_E. + + # The following is ambiguous, and gdb should detect this. + # For now, accept gdb's behavior as an expected failure if it + # simply prints either member correctly. + + send_gdb "print g_E.A::a\n" + gdb_expect { + -re ".* = 21$nl$gdb_prompt $" { + kfail "gdb/68" "print g_E.A::a" + } + -re ".* = 25$nl$gdb_prompt $" { + kfail "gdb/68" "print g_E.A::a" + } + -re ".*$gdb_prompt $" { fail "print g_E.A::a" } + timeout { fail "print g_E.A::a (timeout)" ; return } + } + + # The following is ambiguous, and gdb should detect this. + # For now, accept gdb's behavior as an expected failure if it + # simply prints either member correctly. + + send_gdb "print g_E.A::x\n" + gdb_expect { + -re "warning: A ambiguous; using E::D::C::A. Use a cast to disambiguate.$nl\\$\[0-9\]* = 26$nl$gdb_prompt $" { + pass "print g_E.A::x" + } + -re "warning: A ambiguous; using E::D::B::A. Use a cast to disambiguate.$nl\\$\[0-9\]* = 22$nl$gdb_prompt $" { + pass "print g_E.A::x (using B)" + } + -re ".* = 26$nl$gdb_prompt $" { + kfail "gdb/68" "print g_E.A::x" + } + -re ".* = 22$nl$gdb_prompt $" { + kfail "gdb/68" "print g_E.A::x" + } + -re ".*$gdb_prompt $" { fail "print g_E.A::x" } + timeout { fail "print g_E.A::x (timeout)" ; return } + } + + gdb_test "print g_E.B::b" ".* = 23" "print g_E.B::b" + + gdb_test "print g_E.B::x" ".* = 24" "print g_E.B::x" + + gdb_test "print g_E.C::c" ".* = 27" "print g_E.C::c" + + gdb_test "print g_E.C::x" ".* = 28" "print g_E.C::x" + + gdb_test "print g_E.D::d" ".* = 29" "print g_E.D::d" + + gdb_test "print g_E.D::x" ".* = 30" "print g_E.D::x" + + gdb_test "print g_E.E::e" ".* = 31" "print g_E.E::e" + + gdb_test "print g_E.E::x" ".* = 32" "print g_E.E::x" +} + +# +# Multiple inheritance, print type definitions. +# + +proc test_ptype_mi {} { + global nl + + gdb_test "ptype D" "type = class D : public B, public C \{$nl\[ \]*public:$nl\[ \]*int d;$nl\[ \]*int x;$nl.*\}" "ptype D" + + gdb_test "ptype class D" "type = class D : public B, public C \{$nl\[ \]*public:$nl\[ \]*int d;$nl\[ \]*int x;$nl.*\}" "ptype class D" + + gdb_test "ptype g_D" "type = class D : public B, public C \{$nl\[ \]*public:$nl\[ \]*int d;$nl\[ \]*int x;$nl.*\}" "ptype g_D" + + gdb_test "ptype E" "type = class E : public D \{$nl\[ \]*public:$nl\[ \]*int e;$nl\[ \]*int x;$nl.*\}" "ptype E" + + gdb_test "ptype class E" "type = class E : public D \{$nl\[ \]*public:$nl\[ \]*int e;$nl\[ \]*int x;$nl.*\}" "ptype class E" + + gdb_test "ptype g_E" "type = class E : public D \{$nl\[ \]*public:$nl\[ \]*int e;$nl\[ \]*int x;$nl.*\}" "ptype g_E" +} + +# +# Multiple inheritance, print complete classes. +# + +proc test_print_mi_classes {} { + # Print all members of g_D. + + gdb_test "print g_D" ".* = \{\<(class |)B\> = \{\<(class |)A\> = \{a = 11, x = 12\}, b = 13, x = 14\}, \<(class |)C\> = \{\<(class |)A\> = \{a = 15, x = 16\}, c = 17, x = 18\}, d = 19, x = 20\}" "print g_D" + + # Print all members of g_E. + + gdb_test "print g_E" ".* = \{\<(class |)D\> = \{\<(class |)B\> = \{\<(class |)A\> = \{a = 21, x = 22\}, b = 23, x = 24\}, \<(class |)C\> = \{\<(class |)A\> = \{a = 25, x = 26\}, c = 27, x = 28\}, d = 29, x = 30\}, e = 31, x = 32\}" "print g_E" +} + +# +# Single virtual inheritance, print individual members. +# + +proc test_print_svi_members {} { + global gdb_prompt + global decimal + global nl + + # Print all members of g_vA. + + gdb_test "print g_vA.vA::va" ".* = 1" "print g_vA.vA::va" + + gdb_test "print g_vA.vA::vx" ".* = 2" "print g_vA.vA::vx" + + # Print members of g_vA using compact form. + + gdb_test "print g_vA.va" ".* = 1" "print g_vA.va" + + gdb_test "print g_vA.vx" ".* = 2" "print g_vA.vx" + + # Print all members of g_vB. + + send_gdb "print g_vB.vA::va\n" + gdb_expect { + -re ".* = 3$nl$gdb_prompt $" { pass "print g_vB.vA::va" } + -re ".*virtual baseclass botch.*$gdb_prompt $" { + # Does not happen with gcc cygnus-2.4.5-930828 + fail "print g_vB.vA::va (known bug with gcc cygnus-2.4.5-930417)" + # Many of the rest of these tests have the same problem. + return 0 + } + -re ".*$gdb_prompt $" { fail "print g_vB.vA::va" } + timeout { fail "print g_vB.vA::va (timeout)" ; return } + } + + gdb_test "print g_vB.vA::vx" ".* = 4" "print g_vB.vA::vx" + + gdb_test "print g_vB.vB::vb" ".* = 5" "print g_vB.vB::vb" + + gdb_test "print g_vB.vB::vx" ".* = 6" "print g_vB.vB::vx" + + # Print members of g_vB using compact form. + + gdb_test "print g_vB.va" ".* = 3" "print g_vB.va" + + gdb_test "print g_vB.vb" ".* = 5" "print g_vB.vb" + + gdb_test "print g_vB.vx" ".* = 6" "print g_vB.vx" + + # Print all members of g_vC. + + gdb_test "print g_vC.vA::va" ".* = 7" "print g_vC.vA::va" + + gdb_test "print g_vC.vA::vx" ".* = 8" "print g_vC.vA::vx" + + gdb_test "print g_vC.vC::vc" ".* = 9" "print g_vC.vC::vc" + + gdb_test "print g_vC.vC::vx" ".* = 10" "print g_vC.vC::vx" + + # Print members of g_vC using compact form. + + gdb_test "print g_vC.va" ".* = 7" "print g_vC.va" + + gdb_test "print g_vC.vc" ".* = 9" "print g_vC.vc" + + gdb_test "print g_vC.vx" ".* = 10" "print g_vC.vx" +} + +# +# Single virtual inheritance, print type definitions. +# + +proc test_ptype_vi {} { + global gdb_prompt + global ws + global nl + global vbptr + + # This class does not use any C++-specific features, so it's fine for + # it to print as "struct". + send_gdb "ptype vA\n" + gdb_expect { + -re "type = class vA \{$nl\[ \]*public:$nl\[ \]*int va;$nl\[ \]*int vx;$nl.*\}$nl$gdb_prompt $" { + pass "ptype vA" + } + -re "type = struct vA \{$nl\[ \]*int va;$nl\[ \]*int vx;$nl\}$nl$gdb_prompt $" { + pass "ptype vA" + } + -re ".*$gdb_prompt $" { fail "ptype vA" } + timeout { fail "ptype vA (timeout)" ; return } + } + + # This class does not use any C++-specific features, so it's fine for + # it to print as "struct". + send_gdb "ptype class vA\n" + gdb_expect { + -re "type = class vA \{$nl\[ \]*public:$nl\[ \]*int va;$nl\[ \]*int vx;$nl.*\}$nl$gdb_prompt $" { + pass "ptype class vA" + } + -re "type = struct vA \{$nl\[ \]*int va;$nl\[ \]*int vx;$nl\}$nl$gdb_prompt $" { + pass "ptype class vA" + } + -re ".*$gdb_prompt $" { fail "ptype class vA" } + timeout { fail "ptype class vA (timeout)" ; return } + } + + # This class does not use any C++-specific features, so it's fine for + # it to print as "struct". + send_gdb "ptype g_vA\n" + gdb_expect { + -re "type = class vA \{$nl\[ \]*public:$nl\[ \]*int va;$nl\[ \]*int vx;$nl.*\}$nl$gdb_prompt $" { + pass "ptype g_vA" + } + -re "type = struct vA \{$nl\[ \]*int va;$nl\[ \]*int vx;$nl\}$nl$gdb_prompt $" { + pass "ptype g_vA" + } + -re ".*$gdb_prompt $" { fail "ptype g_vA" } + timeout { fail "ptype g_vA (timeout)" ; return } + } + + send_gdb "ptype vB\n" + gdb_expect { + -re "ptype vB${nl}type = class vB : public virtual vA \{$nl private:${ws}vA \\*${vbptr}vA;$nl public:${ws}int vb;${ws}int vx;$nl.*\}$nl$gdb_prompt $" { + pass "ptype vB" + } + -re "ptype vB${nl}type = class vB : public virtual vA \{$nl public:${ws}int vb;${ws}int vx;$nl.*\}$nl$gdb_prompt $" { + pass "ptype vB (aCC)" + } + -re ".*$gdb_prompt $" { fail "ptype vB" } + timeout { fail "ptype vB (timeout)" } + } + + send_gdb "ptype class vB\n" + gdb_expect { + -re "type = class vB : public virtual vA \{$nl\[ \]*private:$nl\[ \]*vA \\*${vbptr}vA;$nl\[ \]*public:$nl\[ \]*int vb;$nl\[ \]*int vx;$nl.*\}$nl$gdb_prompt $" { + pass "ptype class vB" + } + -re "type = class vB : public virtual vA \{$nl\[ \]*public:$nl\[ \]*int vb;$nl\[ \]*int vx;$nl.*\}$nl$gdb_prompt $" { + pass "ptype class vB (aCC)" + } + -re ".*$gdb_prompt $" { fail "ptype class vB" } + timeout { fail "ptype class vB (timeout)" } + } + + send_gdb "ptype g_vB\n" + gdb_expect { + -re "type = class vB : public virtual vA \{$nl\[ \]*private:$nl\[ \]*vA \\*${vbptr}vA;$nl\[ \]*public:$nl\[ \]*int vb;$nl\[ \]*int vx;$nl.*\}$nl$gdb_prompt $" { + pass "ptype g_vB" + } + -re "type = class vB : public virtual vA \{$nl\[ \]*public:$nl\[ \]*int vb;$nl\[ \]*int vx;$nl.*\}$nl$gdb_prompt $" { + pass "ptype g_vB (aCC)" + } + -re ".*$gdb_prompt $" { fail "ptype g_vB" } + timeout { fail "ptype g_vB (timeout)" } + } + + send_gdb "ptype vC\n" + gdb_expect { + -re "type = class vC : public virtual vA \{$nl\[ \]*private:$nl\[ \]*vA \\*${vbptr}vA;$nl\[ \]*public:$nl\[ \]*int vc;$nl\[ \]*int vx;$nl.*\}$nl$gdb_prompt $" { + pass "ptype vC" + } + -re "type = class vC : public virtual vA \{$nl\[ \]*public:$nl\[ \]*int vc;$nl\[ \]*int vx;$nl.*\}$nl$gdb_prompt $" { + pass "ptype vC (aCC)" + } + -re ".*$gdb_prompt $" { fail "ptype vC" } + timeout { fail "ptype vC (timeout)" } + } + + send_gdb "ptype class vC\n" + gdb_expect { + -re "type = class vC : public virtual vA \{$nl\[ \]*private:$nl\[ \]*vA \\*${vbptr}vA;$nl\[ \]*public:$nl\[ \]*int vc;$nl\[ \]*int vx;$nl.*\}$nl$gdb_prompt $" { + pass "ptype class vC" + } + -re "type = class vC : public virtual vA \{$nl\[ \]*public:$nl\[ \]*int vc;$nl\[ \]*int vx;$nl.*\}$nl$gdb_prompt $" { + pass "ptype class vC (aCC)" + } + -re ".*$gdb_prompt $" { fail "ptype class vC" } + timeout { fail "ptype class vC (timeout)" } + } + + send_gdb "ptype g_vC\n" + gdb_expect { + -re "type = class vC : public virtual vA \{$nl\[ \]*private:$nl\[ \]*vA \\*${vbptr}vA;$nl\[ \]*public:$nl\[ \]*int vc;$nl\[ \]*int vx;$nl.*\}$nl$gdb_prompt $" { + pass "ptype g_vC" + } + -re "type = class vC : public virtual vA \{$nl\[ \]*public:$nl\[ \]*int vc;$nl\[ \]*int vx;$nl.*\}$nl$gdb_prompt $" { + pass "ptype g_vC (aCC)" + } + -re ".*$gdb_prompt $" { fail "ptype g_vC" } + timeout { fail "ptype g_vC (timeout)" } + } +} + +# +# Single virtual inheritance, print complete classes. +# + +proc test_print_svi_classes {} { + global gdb_prompt + global hex + global decimal + global nl + global vbptr + + # Print all members of g_vA. + + gdb_test "print g_vA" ".* = \{va = 1, vx = 2\}" "print g_vA" + + # Print all members of g_vB. + + send_gdb "print g_vB\n" + gdb_expect { + -re ".* = \{\ = \{va = 3, vx = 4\}, vb = 5, vx = 6, Virtual table at $hex\}$nl$gdb_prompt $" { + pass "print g_vB (aCC)" + } + -re ".* = \{\ = \{va = 3, vx = 4\}, vb = 5, vx = 6, __vfp = $hex\}$nl$gdb_prompt $" { + pass "print g_vB (aCC)" + } + -re ".* = \{\ = \{va = 3, vx = 4\}, ${vbptr}vA = $hex, vb = 5, vx = 6\}$nl$gdb_prompt $" { + pass "print g_vB" + } + -re ".* = \{\ = \{va = 3, vx = 4\}, _vptr.vB = $hex, vb = 5, vx = 6\}$nl$gdb_prompt $" { + pass "print g_vB (FIXME v3 vtbl ptr)" + } + -re ".* = \{\ = \{va = 3, vx = 4\}, _vptr.vB = $hex , vb = 5, vx = 6\}$nl$gdb_prompt $" { + # Happens with gcc 3.3 -gstabs+ + # Does not happen with gcc 3.2.3 -gstabs+. + # Does not happen gcc HEAD%20030624 (pre-3.4) -gstabs+. + # -- chastain 2003-06-29 + pass "print g_vB" + } + + -re ".*invalid address 0x0.*$gdb_prompt $" { + # Does not happen with gcc cygnus-2.4.5-930828 + fail "print g_vB (known bug with gcc cygnus-2.4.5-930417)" + # Many of the rest of these tests have the same problem. + return 0 + } + -re ".*$gdb_prompt $" { fail "print g_vB" } + timeout { fail "print g_vB (timeout)" ; return } + } + + # Print all members of g_vC. + + send_gdb "print g_vC\n" + gdb_expect { + -re ".* = \{\ = \{va = 7, vx = 8\}, vc = 9, vx = 10, Virtual table at $hex\}$nl$gdb_prompt $" { + pass "print g_vC (aCC)" + } + -re ".* = \{\ = \{va = 7, vx = 8\}, vc = 9, vx = 10, __vfp = $hex\}$nl$gdb_prompt $" { + pass "print g_vC (aCC)" + } + -re ".* = \{\ = \{va = 7, vx = 8\}, ${vbptr}vA = $hex, vc = 9, vx = 10\}$nl$gdb_prompt $" { + pass "print g_vC" + } + -re ".* = \{\ = \{va = 7, vx = 8\}, _vptr.vC = $hex, vc = 9, vx = 10\}$nl$gdb_prompt $" { + pass "print g_vC (FIXME v3 vtbl ptr)" + } + -re ".* = \{\ = \{va = 7, vx = 8\}, _vptr.vC = $hex , vc = 9, vx = 10\}$nl$gdb_prompt $" { + # Happens with gcc 3.3 -gstabs+ + # Does not happen with gcc 3.2.3 -gstabs+. + # Does not happen gcc HEAD%20030624 (pre-3.4) -gstabs+. + # -- chastain 2003-06-29 + pass "print g_vC" + } + -re ".*$gdb_prompt $" { fail "print g_vC" } + timeout { fail "print g_vC (timeout)" } + } +} + +# +# Multiple virtual inheritance, print individual members. +# + +proc test_print_mvi_members {} { + global gdb_prompt + global decimal + global nl + + # Print all members of g_vD. + + send_gdb "print g_vD.vA::va\n" + gdb_expect { + -re ".* = 19$nl$gdb_prompt $" { pass "print g_vD.vA::va" } + -re ".*virtual baseclass botch.*$gdb_prompt $" { + # Does not happen with gcc cygnus-2.4.5-930828 + fail "print g_vD.vA::va (known bug with gcc cygnus-2.4.5-930417)" + # Many of the rest of these tests have the same problem. + return 0 + } + -re ".*$gdb_prompt $" { fail "print g_vD.vA::va" } + timeout { fail "print g_vD.vA::va (timeout)" ; return } + } + + gdb_test "print g_vD.vA::vx" ".* = 20" "print g_vD.vA::vx" + + gdb_test "print g_vD.vB::vb" ".* = 21" "print g_vD.vB::vb" + + gdb_test "print g_vD.vB::vx" ".* = 22" "print g_vD.vB::vx" + + gdb_test "print g_vD.vC::vc" ".* = 23" "print g_vD.vC::vc" + + gdb_test "print g_vD.vC::vx" ".* = 24" "print g_vD.vC::vx" + + gdb_test "print g_vD.vD::vd" ".* = 25" "print g_vD.vD::vd" + + gdb_test "print g_vD.vD::vx" ".* = 26" "print g_vD.vD::vx" + + # Print all members of g_vE. + + gdb_test "print g_vE.vA::va" ".* = 0" "print g_vE.vA::va" + + gdb_test "print g_vE.vA::vx" ".* = 0" "print g_vE.vA::vx" + + gdb_test "print g_vE.vB::vb" ".* = 0" "print g_vE.vB::vb" + + gdb_test "print g_vE.vB::vx" ".* = 0" "print g_vE.vB::vx" + + gdb_test "print g_vE.vC::vc" ".* = 0" "print g_vE.vC::vc" + + gdb_test "print g_vE.vC::vx" ".* = 0" "print g_vE.vC::vx" + + gdb_test "print g_vE.vD::vd" ".* = 0" "print g_vE.vD::vd" + + gdb_test "print g_vE.vD::vx" ".* = 0" "print g_vE.vD::vx" + + gdb_test "print g_vE.vE::ve" ".* = 27" "print g_vE.vE::ve" + + gdb_test "print g_vE.vE::vx" ".* = 28" "print g_vE.vE::vx" +} + +# +# Multiple virtual inheritance, print type definitions. +# + +proc test_ptype_mvi {} { + global gdb_prompt + global ws + global nl + global vbptr + + send_gdb "ptype vD\n" + gdb_expect { + -re "type = class vD : public virtual vB, public virtual vC \{${ws}private:${ws}vC \\*${vbptr}vC;${ws}vB \\*${vbptr}vB;${ws}public:${ws}int vd;${ws}int vx;$nl.*\}.*$gdb_prompt $" { + pass "ptype vD" + } + -re ".*class vD : public virtual vB, public virtual vC \{${ws}public:${ws}int vd;${ws}int vx;.*\}.*$gdb_prompt $" { + pass "ptype vD" + } + -re ".*$gdb_prompt $" { fail "ptype vD" } + timeout { fail "(timeout) ptype vD" } + } + + send_gdb "ptype class vD\n" + gdb_expect { + -re "type = class vD : public virtual vB, public virtual vC \{${ws}private:${ws}vC \\*${vbptr}vC;${ws}vB \\*${vbptr}vB;${ws}public:${ws}int vd;${ws}int vx;$nl.*\}.*$gdb_prompt $" { + pass "ptype class vD" + } + -re ".*class vD : public virtual vB, public virtual vC \{${ws}public:${ws}int vd;${ws}int vx;.*\}.*$gdb_prompt $" { + pass "ptype class vD" + } + -re ".*$gdb_prompt $" { fail "ptype class vD" } + timeout { fail "(timeout) ptype class vD" } + } + + send_gdb "ptype g_vD\n" + gdb_expect { + -re "type = class vD : public virtual vB, public virtual vC \{${ws}private:${ws}vC \\*${vbptr}vC;${ws}vB \\*${vbptr}vB;${ws}public:${ws}int vd;${ws}int vx;$nl.*\}.*$gdb_prompt $" { + pass "ptype g_vD" + } + -re ".*class vD : public virtual vB, public virtual vC \{${ws}public:${ws}int vd;${ws}int vx;\r\n.*\}.*$gdb_prompt $" { + pass "ptype g_vD" + } + -re ".*$gdb_prompt $" { fail "ptype g_vD" } + timeout { fail "(timeout) ptype g_vD" } + } + + send_gdb "ptype vE\n" + gdb_expect { + -re "type = class vE : public virtual vD \{${ws}private:${ws}vD \\*${vbptr}vD;${ws}public:${ws}int ve;${ws}int vx;$nl.*\}.*$gdb_prompt $" { + pass "ptype vE" + } + -re ".*class vE : public virtual vD \{${ws}public:${ws}int ve;${ws}int vx;\r\n.*\}.*$gdb_prompt $" { + pass "ptype vE" + } + -re ".*$gdb_prompt $" { fail "ptype vE" } + timeout { fail "(timeout) ptype vE" } + } + + send_gdb "ptype class vE\n" + gdb_expect { + -re "type = class vE : public virtual vD \{${ws}private:${ws}vD \\*${vbptr}vD;${ws}public:${ws}int ve;${ws}int vx;$nl.*\}.*$gdb_prompt $" { + pass "ptype class vE" + } + -re "type = class vE : public virtual vD \{${ws}public:${ws}int ve;${ws}int vx;\r\n.*\}.*$gdb_prompt $" { + pass "ptype class vE" + } + -re ".*$gdb_prompt $" { fail "ptype class vE" } + timeout { fail "(timeout) ptype class vE" } + } + + send_gdb "ptype g_vE\n" + gdb_expect { + -re "type = class vE : public virtual vD \{${ws}private:${ws}vD \\*${vbptr}vD;${ws}public:${ws}int ve;${ws}int vx;$nl.*\}.*$gdb_prompt $" { + pass "ptype g_vE" + } + -re "type = class vE : public virtual vD \{${ws}public:${ws}int ve;${ws}int vx;\r\n.*\}.*$gdb_prompt $" { + pass "ptype g_vE" + } + -re ".*$gdb_prompt $" { fail "ptype g_vE" } + timeout { fail "(timeout) ptype g_vE" } + } +} + +# +# Multiple virtual inheritance, print complete classes. +# + +proc test_print_mvi_classes {} { + global gdb_prompt + global hex + global decimal + global nl + global vbptr + + # Print all members of g_vD. + + send_gdb "print g_vD\n" + gdb_expect { + -re ".* = \{\ = \{\ = \{va = 19, vx = 20\}, vb = 21, vx = 22, Virtual table at $hex\}, \ = \{vc = 23, vx = 24, Virtual table at $hex\}, vd = 25, vx = 26, Virtual table at $hex\}$nl$gdb_prompt $" { + pass "print g_vD (aCC)" + } + -re ".* = \{\ = \{\ = \{va = 19, vx = 20\}, vb = 21, vx = 22, __vfp = $hex\}, \ = \{vc = 23, vx = 24, __vfp = $hex\}, vd = 25, vx = 26, __vfp = $hex\}$nl$gdb_prompt $" { + pass "print g_vD (aCC)" + } + -re ".* = \{\ = \{\ = \{va = 19, vx = 20\}, ${vbptr}vA = $hex, vb = 21, vx = 22\}, \ = \{${vbptr}vA = $hex, vc = 23, vx = 24\}, ${vbptr}vC = $hex, ${vbptr}vB = $hex, vd = 25, vx = 26\}$nl$gdb_prompt $" { + pass "print g_vD" + } + -re ".* = \{\ = \{\ = \{va = 19, vx = 20\}, _vptr.vB = $hex, vb = 21, vx = 22\}, \ = \{_vptr.vC = $hex, vc = 23, vx = 24\}, _vptr.vD = $hex, vd = 25, vx = 26\}$nl$gdb_prompt $" { + pass "print g_vD (FIXME v3 vtbl ptr)" + } + -re ".* = \{\ = \{\ = \{va = 19, vx = 20\}, _vptr.vB = $hex, vb = 21, vx = 22\}, \ = \{_vptr.vC = $hex , vc = 23, vx = 24\}, _vptr.vD = $hex, vd = 25, vx = 26\}$nl$gdb_prompt $" { + # Happens with gcc 3.3 -gstabs+ + # Does not happen with gcc 3.2.3 -gstabs+. + # Does not happen gcc HEAD%20030624 (pre-3.4) -gstabs+. + # -- chastain 2003-06-29 + pass "print g_vD" + } + -re ".*invalid address 0x0.*$gdb_prompt $" { + # Does not happen with gcc cygnus-2.4.5-930828 + fail "print g_vD (known bug with gcc cygnus-2.4.5-930417)" + # Many of the rest of these tests have the same problem. + return 0 + } + -re ".*$gdb_prompt $" { fail "print g_vD" } + timeout { fail "print g_vD (timeout)" ; return } + } + + # Print all members of g_vE. + + send_gdb "print g_vE\n" + gdb_expect { + -re ".* = \{\ = \{\ = \{\ = \{va = 0, vx = 0\}, vb = 0, vx = 0, Virtual table at $hex\}, \ = \{vc = 0, vx = 0, Virtual table at $hex\}, vd = 0, vx = 0, Virtual table at $hex\}, ve = 27, vx = 28, Virtual table at $hex\}$nl$gdb_prompt $" { + pass "print g_vE (aCC)" + } + -re ".* = \{\ = \{\ = \{\ = \{va = 0, vx = 0\}, vb = 0, vx = 0, __vfp = $hex\}, \ = \{vc = 0, vx = 0, __vfp = $hex\}, vd = 0, vx = 0, __vfp = $hex\}, ve = 27, vx = 28, __vfp = $hex\}$nl$gdb_prompt $" { + pass "print g_vE (aCC)" + } + -re ".* = \{\ = \{\ = \{\ = \{va = 0, vx = 0\}, ${vbptr}vA = $hex, vb = 0, vx = 0\}, \ = \{${vbptr}vA = $hex, vc = 0, vx = 0\}, ${vbptr}vC = $hex, ${vbptr}vB = $hex, vd = 0, vx = 0\}, ${vbptr}vD = $hex, ve = 27, vx = 28\}$nl$gdb_prompt $" { + pass "print g_vE" + } + -re ".* = \{\ = \{\ = \{\ = \{va = 0, vx = 0\}, _vptr.vB = $hex *(\)?, vb = 0, vx = 0\}, \ = \{_vptr.vC = $hex *(\)?, vc = 0, vx = 0\}, _vptr.vD = $hex, vd = 0, vx = 0\}, _vptr.vE = $hex, ve = 27, vx = 28\}$nl$gdb_prompt $" { + pass "print g_vE (FIXME v3 vtbl ptr)" + } + -re ".*$gdb_prompt $" { fail "print g_vE" } + timeout { fail "print g_vE (timeout)" } + } +} + +proc do_tests {} { + global prms_id + global bug_id + global subdir + global objdir + global srcdir + global binfile + + set prms_id 0 + set bug_id 0 + + # Start with a fresh gdb. + + gdb_exit + gdb_start + gdb_reinitialize_dir $srcdir/$subdir + gdb_load $binfile + + gdb_test "set language c++" "" + gdb_test "set width 0" "" + + # Get the debug format for the compiled test case. + + if { ![ runto_main] } { + gdb_suppress_tests; + } + + test_ptype_si + test_ptype_mi + test_ptype_vi + test_ptype_mvi + + gdb_stop_suppressing_tests; + + if { ![ runto 'inheritance2' ] } { + gdb_suppress_tests; + } + + test_print_si_members + test_print_si_classes + test_print_mi_members + test_print_mi_classes + test_print_anon_union + + gdb_stop_suppressing_tests; + + if { ![ runto 'inheritance4' ] } { + gdb_suppress_tests; + } + + test_print_svi_members + test_print_svi_classes + test_print_mvi_members + test_print_mvi_classes +} + +do_tests diff --git a/gdb/testsuite/gdb.cp/local.cc b/gdb/testsuite/gdb.cp/local.cc new file mode 100644 index 0000000..85fd6e1 --- /dev/null +++ b/gdb/testsuite/gdb.cp/local.cc @@ -0,0 +1,66 @@ +// Tests for local types + +void marker1 (void) +{ +} + +void marker2 (void) +{ +} + +int foobar (int x) +{ + class Local { + public: + int loc1; + char loc_foo (char c) + { + return c + 3; + } + }; + + Local l; + static Local l1; + char c; + + marker1 (); + + l.loc1 = 23; + + c = l.loc_foo('x'); + return c + 2; +} + +int main() +{ + int c; + + c = foobar (31); + + { // inner block + class InnerLocal { + public: + char ilc; + int * ip; + int il_foo (unsigned const char & uccr) + { + return uccr + 333; + } + class NestedInnerLocal { + public: + int nil; + int nil_foo (int i) + { + return i * 27; + } + }; + NestedInnerLocal nest1; + }; + + InnerLocal il; + + il.ilc = 'b'; + il.ip = &c; + marker2(); + } +} diff --git a/gdb/testsuite/gdb.cp/local.exp b/gdb/testsuite/gdb.cp/local.exp new file mode 100644 index 0000000..21ceb7a --- /dev/null +++ b/gdb/testsuite/gdb.cp/local.exp @@ -0,0 +1,228 @@ +# Copyright 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# Please email any bugs, comments, and/or additions to this file to: +# bug-gdb@prep.ai.mit.edu + +# tests for local variables +# Written by Satish Pai 1997-07-08 +# Cleaned by Michael Chastain 2002-04-08 + + +# This file is part of the gdb testsuite + +if $tracelevel then { + strace $tracelevel + } + +# +# test running programs +# +set prms_id 0 +set bug_id 0 + +if { [skip_cplus_tests] } { continue } + +set testfile "local" +set srcfile ${testfile}.cc +set binfile ${objdir}/${subdir}/${testfile} + +if { [gdb_compile "${srcdir}/${subdir}/${srcfile}" "${binfile}" executable {debug c++}] != "" } { + gdb_suppress_entire_file "Testcase compile failed, so all tests in this file will automatically fail." +} + +if [get_compiler_info $binfile "c++"] { + return -1 +} + +gdb_exit +gdb_start +gdb_reinitialize_dir $srcdir/$subdir +gdb_load ${binfile} + + +# +# set it up at a breakpoint so we can play with the variable values +# +if ![runto_main] then { + perror "couldn't run to breakpoint" + continue +} + +if ![runto 'marker1'] then { + perror "couldn't run to marker1" + continue +} + +gdb_test "up" ".*foobar.*" "up from marker1" + +# Local classes in g++ get names like "main.1::InnerLocal", just like local +# static variables. Some targets use "___" instead of ".". + +# --- +# Pattern 1: +# PASS +# dwarf-2 +# gcc 2.95.3 +# +# Pattern 2: +# FAIL +# This has a duplicate "char loc_foo" line. This is a bug. +# Historically this has been an XFAIL. +# dwarf-2 +# gcc 2.96-rh, 3.0.4, gcc-3_1-branch, HEAD +# +# Pattern 3: +# PASS +# stabs+ +# gcc 2.95.3, 2.96-rh, 3.0.4, gcc-3_1-branch, HEAD +# +# Pattern 4: +# This an old pattern from the hppa aCC version of this file. +# I left it alone. +# +# chastain 2002-04-08 + +set sep "(\[.\]|___)\[0-9\]" + +send_gdb "ptype Local\n" +gdb_expect { + -re "type = class Local \{\[\r\n\t \]*public:\[\r\n\t \]*int loc1;\[\r\n\t \]*char loc_foo\\((const *|)char\\);\[\r\n\t \]*\}.*$gdb_prompt $" { pass "ptype Local" } + -re "type = class Local \{\[\r\n\t \]*public:\[\r\n\t \]*int loc1;\[\r\n\t \]*char loc_foo\\((const *|)char\\);\[\r\n\t \]*char loc_foo\\((const *|)char\\);\[\r\n\t \]*\}.*$gdb_prompt $" { + kfail "gdb/483" "ptype Local" + } + -re "type = class Local \{\[\r\n\t \]*public:\[\r\n\t \]*int loc1;\[\r\n\t \]*Local & operator *=\\((foobar__Fi${sep}::|)Local const *&\\);\[\r\n\t \]*Local\\((foobar__Fi${sep}::|)Local const *&\\);\[\r\n\t \]*Local\\((void|)\\);\[\r\n\t \]*char loc_foo\\(char\\);\[\r\n\t \]*\}.*$gdb_prompt $" { pass "ptype Local" } + -re "type = class Local \{\r\n\[\t \]*public:\r\n\[\t \]*int loc1;\r\n\r\n\[\t \]*char loc_foo\\(char\\);\r\n\[\t \]*\\(Local at.*local\\.cc:\[0-9\]*\\)\r\n\}.*$gdb_prompt $" { xpass "ptype Local (old aCC)" } + -re ".*$gdb_prompt $" { fail "ptype Local" } + timeout { fail "(timeout) ptype Local" } +} + +gdb_test "break marker2" +gdb_test "continue" "Continuing\\..*Breakpoint \[0-9\]+, marker2.*" \ + "continuing to marker2" + +gdb_test "up" ".*main.*" "up from marker2" + +# Make sure that `Local' isn't in scope here; it's local to foobar. +# setup_kfail "gdb/825" +send_gdb "ptype Local\n" +set eol "\[\t \]*\[\r\n\]+\[\t \]*" +gdb_expect { + -re "No symbol \"Local\" in current context.*${gdb_prompt} $" { + pass "Local out of scope" + } + -re "ptype Local${eol}type = class Local {${eol} public:${eol} int loc1;${eol}.*${eol} char loc_foo\\(char\\);${eol}}${eol}${gdb_prompt} " { + # GCC emits STABS debugging information in a way that doesn't + # properly preserve the scoping of local classes. I think + # we'd need to start using Sun's extensions to stabs to get + # this right. + kfail gdb/825 "Local out of scope" + } + -re ".*${gdb_prompt} $" { + fail "Local out of scope" + } + timeout { + fail "Local out of scope (timeout)" + } +} + + +# DTS CLLbs14316 and CLLbs17058 +# coulter - I added a clause for HP's aCC compiler. We print out the type +# as xx instead of const unsigned char, but we still have an expected failure +# because of two reasons: +# There is a number at the end of InnerLocal4 which should not be there, +# DTS CLLbs14316 +# The line number for the class +# setup_xfail "hppa*-*-*" CLLbs14316 + +# --- +# Pattern 1: +# PASS +# dwarf-2 +# 2.95.3, 2.96-rh, 3.0.4, 3.1, gcc-3_1-branch, HEAD +# +# Pattern 2: +# PASS +# stabs+ +# 2.95.3, 2.96-rh, 3.0.4, 3.1, gcc-3_1-branch, HEAD +# +# Pattern 3: +# Old hppa pattern. +# +# Pattern 4: +# Old hppa pattern. +# +# chastain 2002-05-27 + +send_gdb "ptype InnerLocal\n" +gdb_expect { + -re "type = class InnerLocal \{\[\r\n\t \]*public:\[\r\n\t \]*char ilc;\[\r\n\t \]*int \\* *ip;\[\r\n\t \]*(InnerLocal::|)NestedInnerLocal nest1;\[\r\n\t \]*int il_foo\\((unsigned char const|const unsigned char) *&\\);\[\r\n\t \]*\}.*$gdb_prompt $" { pass "ptype InnerLocal (pattern 1)" } + -re "type = class InnerLocal \{\[\r\n\t \]*public:\[\r\n\t \]*char ilc;\[\r\n\t \]*int \\* *ip;\[\r\n\t \]*(InnerLocal::|)NestedInnerLocal nest1;\[\r\n\t \]*InnerLocal *& operator *=\\((main${sep}::|)InnerLocal const *&\\);\[\r\n\t \]*InnerLocal\\((main${sep}::|)InnerLocal const *&\\);\[\r\n\t \]*InnerLocal\\((void|)\\);\[\r\n\t \]*int il_foo\\(unsigned char const *&\\);\[\r\n\t \]*\}.*$gdb_prompt $" { pass "ptype InnerLocal (pattern 2)" } + -re "type = class InnerLocal \{\r\n\[\t \]*public:\r\n\[\t \]*char ilc;\r\n\[\t \]*int \\*ip;\r\n\[\t \]*InnerLocal::NestedInnerLocal nest1;\r\n\r\n\[\t \]*.int il_foo\\(unsigned char const &\\);\r\n\[\t \]*\}\[\t \]*\\(Local at.*local\\.cc:36\\).*$gdb_prompt $" { pass "ptype InnerLocal (old HP aCC)" } + -re "type = class InnerLocal \{\r\n\[\t \]*public:\r\n\[\t \]*char ilc;\r\n\[\t \]*int \\*ip;\r\n\[\t \]*class InnerLocal4::NestedInnerLocal nest1;\r\n\r\n\[\t \]*int il_foo\\(unsigned char const &\\);\r\n\[\t \]*\\(Local at.*local\.cc:\[0-9\]+\\)\r\n\}.*$gdb_prompt $" { pass "ptype InnerLocal (old HP aCC)" } + -re ".*$gdb_prompt $" { fail "ptype InnerLocal" } + timeout { fail "(timeout) ptype InnerLocal" } +} + +#--- +# Pattern 1: +# PASS +# dwarf-2 +# gcc 2.95.3, 2.96-rh, 3.0.4, gcc-3_1-branch, HEAD +# +# Pattern 2: +# PASS +# stabs+ +# gcc 2.95.3, 2.96-rh, 3.0.4, gcc-3_1-branch, HEAD +# +# chastain 2002-04-08 + +send_gdb "ptype NestedInnerLocal\n" +gdb_expect { + -re "type = class NestedInnerLocal \{\[\r\n\t \]*public:\[\r\n\t \]*int nil;\[\r\n\t \]*int nil_foo\\(int\\);\[\r\n\t \]*\}.*$gdb_prompt $" { pass "ptype NestedInnerLocal" } + -re "type = class NestedInnerLocal \{\[\r\n\t \]*public:\[\r\n\t \]*int nil;\[\r\n\t \]*NestedInnerLocal *& *operator *= *\\((main${sep}::|)InnerLocal::NestedInnerLocal const *&\\);\[\r\n\t \]*NestedInnerLocal\\((main${sep}::|)InnerLocal::NestedInnerLocal const *&\\);\[\r\n\t \]*NestedInnerLocal\\((void|)\\);\[\r\n\t \]*int nil_foo\\(int\\);\[\r\n\t \]*\}.*$gdb_prompt $" { pass "ptype NestedInnerLocal" } + -re ".*$gdb_prompt $" { fail "ptype NestedInnerLocal" } + timeout { fail "(timeout) ptype NestedInnerLocal" } +} + +# gdb incorrectly interprets the NestedInnerLocal in +# InnerLocal::NestedInnerLocal as field name instead of a type name; +# See CLLbs14784. + +#--- +# Pattern 3: +# FAIL +# The comment above, about CLLbs14784, is still correct. +# dwarf-2 +# gcc 2.95.3, 2.96-rh, 3.0.4, gcc-3_1-branch, HEAD +# stabs+ +# gcc 2.95.3, 2.96-rh, 3.0.4, gcc-3_1-branch, HEAD +# +# chastain 2002-04-08 + +send_gdb "ptype InnerLocal::NestedInnerLocal\n" +gdb_expect { + -re "type = class InnerLocal::NestedInnerLocal \{\[\r\n\t \]*public:\[\r\n\t \]*int nil;\[\r\n\t \]*int nil_foo\\(int\\);\[\r\n\t \]*\}.*$gdb_prompt $" { pass "ptype InnerLocal::NestedInnerLocal" } + -re "type = class InnerLocal::NestedInnerLocal \{\[\r\n\t \]*public:\[\r\n\t \]*int nil;\[\r\n\t \]*NestedInnerLocal *& *operator *= *\\((main${sep}::|)InnerLocal::NestedInnerLocal const *&\\);\[\r\n\t \]*NestedInnerLocal\\((main${sep}::|)InnerLocal::NestedInnerLocal const *&\\);\[\r\n\t \]*NestedInnerLocal\\((void|)\\);\[\r\n\t \]*int nil_foo\\(int\\);\[\r\n\t \]*\}.*$gdb_prompt $" { pass "ptype InnerLocal::NestedInnerLocal" } + -re "There is no field named NestedInnerLocal.*$gdb_prompt $" { + setup_kfail "gdb/482" *-*-* + fail "ptype InnerLocal::NestedInnerLocal" + } + -re "No symbol .*NestedInnerLocal.* in current context.*$gdb_prompt $" { fail "ptype InnerLocal::NestedInnerLocal (bogus symbol lookup)" } + -re ".*$gdb_prompt $" { fail "ptype InnerLocal::NestedInnerLocal" } + timeout { fail "(timeout) ptype InnerLocal::NestedInnerLocal" } +} diff --git a/gdb/testsuite/gdb.cp/m-data.cc b/gdb/testsuite/gdb.cp/m-data.cc new file mode 100644 index 0000000..c97e719 --- /dev/null +++ b/gdb/testsuite/gdb.cp/m-data.cc @@ -0,0 +1,64 @@ +// 2002-05-13 + +enum region { oriental, egyptian, greek, etruscan, roman }; + +// Test one. +class gnu_obj_1 +{ +protected: + typedef region antiquities; + const bool test; + const int key1; + long key2; + + antiquities value; + +public: + gnu_obj_1(antiquities a, long l): test(true), key1(5), key2(l), value(a) {} +}; + +// Test two. +template +class gnu_obj_2: public virtual gnu_obj_1 +{ +protected: + antiquities value_derived; + +public: + gnu_obj_2(antiquities b): gnu_obj_1(oriental, 7), value_derived(b) { } +}; + +// Test three. +template +class gnu_obj_3 +{ +protected: + typedef region antiquities; + gnu_obj_2 data; + +public: + gnu_obj_3(antiquities b): data(etruscan) { } +}; + +int shadow = 0; + +class C +{ +public: + C (int x) : shadow (x) {} + void marker () {} +private: + int shadow; +}; + +int main() +{ + gnu_obj_1 test1(egyptian, 4589); + gnu_obj_2 test2(roman); + gnu_obj_3 test3(greek); + + C theC (1); // breakpoint: first-constructs-done + theC.marker (); + + return 0; +} diff --git a/gdb/testsuite/gdb.cp/m-data.exp b/gdb/testsuite/gdb.cp/m-data.exp new file mode 100644 index 0000000..85adb5e --- /dev/null +++ b/gdb/testsuite/gdb.cp/m-data.exp @@ -0,0 +1,119 @@ +# Copyright 2002 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# Tests for member data +# 2002-05-13 Benjamin Kosnik + +# This file is part of the gdb testsuite + +if $tracelevel then { + strace $tracelevel + } + +if { [skip_cplus_tests] } { continue } + +# +# test running programs +# +set prms_id 0 +set bug_id 0 + +set testfile "m-data" +set srcfile ${testfile}.cc +set binfile ${objdir}/${subdir}/${testfile} + +if { [gdb_compile "${srcdir}/${subdir}/${srcfile}" "${binfile}" executable {debug c++}] != "" } { + gdb_suppress_entire_file "Testcase compile failed, so all tests in this file will automatically fail." +} + +if [get_compiler_info ${binfile} "c++"] { + return -1 +} + +gdb_exit +gdb_start +gdb_reinitialize_dir $srcdir/$subdir +gdb_load ${binfile} + + +if ![runto_main] then { + perror "couldn't run to breakpoint" + continue +} + +# First, run to after we've constructed all the gnu_obj_N's: + +gdb_breakpoint [gdb_get_line_number "first-constructs-done"] +gdb_continue_to_breakpoint "end of first constructors" + +# One. + +# simple object, const bool +gdb_test "print test1.test" "\\$\[0-9\]* = true" "simple object, const bool" + +# simple object, const int +gdb_test "print test1.key1" "\\$\[0-9\]* = 5" "simple object, const int" + +# simple object, long +gdb_test "print test1.key2" "\\$\[0-9\]* = 4589" "simple object, long" + +# simple object, enum +gdb_test "print test1.value" "\\$\[0-9\]* = egyptian" "simple object, enum" + +# Two. + +# derived template object, base const bool +gdb_test "print test2.test" "\\$\[0-9\]* = true" "derived template object, base const bool" + +# derived template object, base const int +gdb_test "print test2.key1" "\\$\[0-9\]* = 5" "derived template object, base const int" + +# derived template object, base long +gdb_test "print test2.key2" "\\$\[0-9\]* = 7" "derived template object, base long" + +# derived template object, base enum +gdb_test "print test2.value" "\\$\[0-9\]* = oriental" "derived template object, base enum" + +# derived template object, enum +gdb_test "print test2.value_derived" "\\$\[0-9\]* = roman" "derived template object, derived enum" + +# Three. + +# template object, derived template data member's base const bool +gdb_test "print test3.data.test" "\\$\[0-9\]* = true" "template object, const bool" + +# template object, derived template data member's base const int +gdb_test "print test3.data.key1" "\\$\[0-9\]* = 5" "template object, const int" + +# template object, derived template data member's base long +gdb_test "print test3.data.key2" "\\$\[0-9\]* = 7" "template object, long" + +# template object, derived template data member's base enum +gdb_test "print test3.data.value" "\\$\[0-9\]* = oriental" "template object, base enum" + +# template object, derived template data member's enum +gdb_test "print test3.data.value_derived" "\\$\[0-9]\* = etruscan" "template object, derived enum" + +# Now some tests for shadowing (see PR gdb/804): + +gdb_breakpoint "C::marker" +gdb_continue_to_breakpoint "continue to shadow breakpoint" + +gdb_test "print shadow" "\\$\[0-9]\* = 1" "shadowing member" +gdb_test "print ::shadow" "\\$\[0-9]\* = 0" "shadowed global variable" + +gdb_exit +return 0 diff --git a/gdb/testsuite/gdb.cp/m-static.cc b/gdb/testsuite/gdb.cp/m-static.cc new file mode 100644 index 0000000..6d08cb0 --- /dev/null +++ b/gdb/testsuite/gdb.cp/m-static.cc @@ -0,0 +1,72 @@ +// 2002-05-13 + +enum region { oriental, egyptian, greek, etruscan, roman }; + +// Test one. +class gnu_obj_1 +{ +protected: + typedef region antiquities; + static const bool test = true; + static const int key1 = 5; + static long key2; + + static antiquities value; + +public: + gnu_obj_1(antiquities a, long l) {} +}; + +const bool gnu_obj_1::test; +const int gnu_obj_1::key1; +long gnu_obj_1::key2 = 77; +gnu_obj_1::antiquities gnu_obj_1::value = oriental; + + +// Test two. +template +class gnu_obj_2: public virtual gnu_obj_1 +{ +public: + static antiquities value_derived; + +public: + gnu_obj_2(antiquities b): gnu_obj_1(oriental, 7) { } +}; + +template +typename gnu_obj_2::antiquities gnu_obj_2::value_derived = etruscan; + +// Test three. +template +class gnu_obj_3 +{ +public: + typedef region antiquities; + static gnu_obj_2 data; + +public: + gnu_obj_3(antiquities b) { } +}; + +template +gnu_obj_2 gnu_obj_3::data(etruscan); + +// 2002-08-16 +// Test four. +#include "m-static.h" + +// instantiate templates explicitly so their static members will exist +template class gnu_obj_2; +template class gnu_obj_2; +template class gnu_obj_3; + +int main() +{ + gnu_obj_1 test1(egyptian, 4589); + gnu_obj_2 test2(roman); + gnu_obj_3 test3(greek); + gnu_obj_4 test4; + + return 0; // breakpoint: constructs-done +} diff --git a/gdb/testsuite/gdb.cp/m-static.exp b/gdb/testsuite/gdb.cp/m-static.exp new file mode 100644 index 0000000..d291135 --- /dev/null +++ b/gdb/testsuite/gdb.cp/m-static.exp @@ -0,0 +1,128 @@ +# Copyright 2002 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# Tests for member static data +# 2002-05-13 Benjamin Kosnik +# 2002-08-22 David Carlton + +# This file is part of the gdb testsuite + +if $tracelevel then { + strace $tracelevel + } + +if { [skip_cplus_tests] } { continue } + +# +# test running programs +# +set prms_id 0 +set bug_id 0 + +set testfile "m-static" +set srcfile ${testfile}.cc +set srcfile1 ${testfile}1.cc +set binfile ${objdir}/${subdir}/${testfile} + +if { [gdb_compile "${srcdir}/${subdir}/${srcfile} ${srcdir}/${subdir}/${srcfile1}" "${binfile}" executable {debug c++}] != "" } { + gdb_suppress_entire_file "Testcase compile failed, so all tests in this file will automatically fail." +} + +if [get_compiler_info ${binfile} "c++"] { + return -1 +} + +gdb_exit +gdb_start +gdb_reinitialize_dir $srcdir/$subdir +gdb_load ${binfile} + + +if ![runto_main] then { + perror "couldn't run to breakpoint" + continue +} + +# First, run to after we've constructed all the objects: + +gdb_breakpoint [gdb_get_line_number "constructs-done"] +gdb_continue_to_breakpoint "end of constructors" + + +# One. + +# simple object, static const bool +gdb_test "print test1.test" "\\$\[0-9\]* = true" "simple object, static const bool" + +# simple object, static const int +gdb_test "print test1.key1" "\\$\[0-9\]* = 5" "simple object, static const int" + +# simple object, static long +gdb_test "print test1.key2" "\\$\[0-9\]* = 77" "simple object, static long" + +# simple object, static enum +gdb_test "print test1.value" "\\$\[0-9\]* = oriental" "simple object, static enum" + +# Two. + +# derived template object, base static const bool +gdb_test "print test2.test" "\\$\[0-9\]* = true" "derived template object, base static const bool" + +# derived template object, base static const int +gdb_test "print test2.key1" "\\$\[0-9\]* = 5" "derived template object, base static const int" + +# derived template object, base static long +gdb_test "print test2.key2" "\\$\[0-9\]* = 77" "derived template object, base static long" + +# derived template object, base static enum +gdb_test "print test2.value" "\\$\[0-9\].* = oriental" "derived template object, base static enum" + +# derived template object, static enum +gdb_test "print test2.value_derived" "\\$\[0-9\].* = etruscan" "derived template object, static enum" + +# Three. + +# template object, static derived template data member's base static const bool +gdb_test "print test3.data.test" "\\$\[0-9\].* = true" "template object, static const bool" + +# template object, static derived template data member's base static const int +gdb_test "print test3.data.key1" "\\$\[0-9\].* = 5" "template object, static const int" + +# template object, static derived template data member's base static long +gdb_test "print test3.data.key2" "\\$\[0-9\].* = 77" "template object, static long" + +# template object, static derived template data member's base static enum +gdb_test "print test3.data.value" "\\$\[0-9\].* = oriental" "template object, static enum" + +# template object, static derived template data member's static enum +gdb_test "print test3.data.value_derived" "\\$\[0-9\].* = etruscan" "template object, static derived enum" + +# 2002-08-16 +# Four. + +# static const int initialized in another file. +gdb_test "print test4.elsewhere" "\\$\[0-9\].* = 221" "static const int initialized elsewhere" + +# static const int that nobody initializes. From PR gdb/635. +gdb_test "print test4.nowhere" "field nowhere is nonexistent or has been optimised out" "static const int initialized nowhere" + +# Perhaps at some point test4 should also include a test for a static +# const int that was initialized in the header file. But I'm not sure +# that GDB's current behavior in such situations is either consistent +# across platforms or optimal, so I'm not including one now. + +gdb_exit +return 0 diff --git a/gdb/testsuite/gdb.cp/m-static.h b/gdb/testsuite/gdb.cp/m-static.h new file mode 100644 index 0000000..137d3b7 --- /dev/null +++ b/gdb/testsuite/gdb.cp/m-static.h @@ -0,0 +1,11 @@ +// 2002-08-16 + +class gnu_obj_4 +{ + public: + static const int elsewhere; + static const int nowhere; + // At some point, perhaps: + // static const int everywhere = 317; +}; + diff --git a/gdb/testsuite/gdb.cp/m-static1.cc b/gdb/testsuite/gdb.cp/m-static1.cc new file mode 100644 index 0000000..302a5ad --- /dev/null +++ b/gdb/testsuite/gdb.cp/m-static1.cc @@ -0,0 +1,5 @@ +// 2002-08-16 + +#include "m-static.h" + +const int gnu_obj_4::elsewhere = 221; diff --git a/gdb/testsuite/gdb.cp/maint.exp b/gdb/testsuite/gdb.cp/maint.exp new file mode 100644 index 0000000..710e14a --- /dev/null +++ b/gdb/testsuite/gdb.cp/maint.exp @@ -0,0 +1,126 @@ +# Copyright 2003 Free Software Foundation Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# Please email any bugs, comments, and/or additions to this file to: +# bug-gdb@prep.ai.mit.edu + + +# This file tests C++-specific maintenance commands and help on those. + +# Currently, no source file is used. + +if $tracelevel then { + strace $tracelevel + } + +# Test the help messages. + +proc test_help {} { + set first_component_help "Print the first class/namespace component of NAME" + set namespace_help "Print the list of possible C\\+\\+ namespaces" + + set multiple_help_body "List of maintenance cplus subcommands:\r\n\r\nmaintenance cplus first_component -- ${first_component_help}\r\nmaintenance cplus namespace -- ${namespace_help}\r\n\r\nType \"help maintenance cplus\" followed by maintenance cplus subcommand name for full documentation.\r\nCommand name abbreviations are allowed if unambiguous." + + set help_maint_cp "C\\+\\+ maintenance commands.\r\n\r\n${multiple_help_body}" + + gdb_test "help maintenance cplus" "${help_maint_cp}" + gdb_test "help maint cp" "${help_maint_cp}" + gdb_test "maint cp" "\"maintenance cplus\" must be followed by the name of a command.\r\n${multiple_help_body}" + + gdb_test "help maint cp first_component" "${first_component_help}." + gdb_test "help maint cp namespace" "${namespace_help}." +} + +# This is used when NAME should contain only a single component. Be +# careful to make sure that parentheses get escaped properly. +proc test_single_component {name} { + set matchname [string_to_regexp "$name"] + gdb_test "maint cp first_component $name" "$matchname" +} + +# This is used when NAME is invalid. +proc test_invalid_name {name} { + set matchname [string_to_regexp "$name"] + gdb_test "maint cp first_component $name" \ + "During symbol reading, unexpected demangled name '$matchname'.\r\n$matchname" +} + +proc test_first_component {} { + # The function in question might complain; make sure that we see + # all complaints. + + gdb_test "set complaints -1" "" + + test_single_component "foo" + test_single_component "operator<<" + test_single_component "operator>>" + test_single_component "operator ->" + test_single_component "operator()" + test_single_component "operator>" + test_single_component "operator<" + test_single_component "operator ->" + test_single_component "operator ->" + + test_single_component "foo()" + test_single_component "foo(int)" + test_single_component "foo(X::Y)" + test_single_component "foo(X::Y, A::B)" + test_single_component "foo(std::basic_streambuf >)" + test_single_component "operator>(X::Y)" + + # Operator names can show up in weird places. + + test_single_component "int operator<< ()" + test_single_component "T" + + # NOTE: carlton/2003-04-23: I've only seen the first of these + # produced by the demangler, but I'm including two more just to be + # on the safe side. + test_single_component "int foo<&(operator<<(C, C))>()" + test_single_component "int foo<&operator<<(C, C)>()" + test_single_component "int foo()" + + gdb_test "maint cp first_component foo::bar" "foo" + gdb_test "maint cp first_component foo::bar::baz" "foo" + gdb_test "maint cp first_component C::bar" "C" + gdb_test "maint cp first_component C > >::bar" "C > >" + + # Make sure we behave appropriately on invalid input. + + # NOTE: carlton/2003-06-25: As of today, the demangler can in fact + # produce examples like the third case below: there really should + # be a space between the two <'s. See PR gdb/1245. + + test_invalid_name "foo<" + test_invalid_name "foo(" + test_invalid_name "bool operator<" +} + +proc test_namespace {} { + # There's not a lot we can do to test this. + + gdb_test "maint cp namespace" "Possible namespaces:" +} + +gdb_exit +gdb_start + +test_help +test_first_component +test_namespace + +gdb_exit +return 0 diff --git a/gdb/testsuite/gdb.cp/member-ptr.cc b/gdb/testsuite/gdb.cp/member-ptr.cc new file mode 100644 index 0000000..4beb926 --- /dev/null +++ b/gdb/testsuite/gdb.cp/member-ptr.cc @@ -0,0 +1,106 @@ +extern "C" { +#include +} + + +class A { +public: + A(); + int foo (int x); + int bar (int y); + virtual int baz (int z); + char c; + int j; + int jj; + static int s; +}; + +class B { +public: + static int s; +}; + +int A::s = 10; +int B::s = 20; + +A::A() +{ + c = 'x'; + j = 5; +} + +int A::foo (int dummy) +{ + j += 3; + return j + dummy; +} + +int A::bar (int dummy) +{ + int r; + j += 13; + r = this->foo(15); + return r + j + 2 * dummy; +} + +int A::baz (int dummy) +{ + int r; + j += 15; + r = this->foo(15); + return r + j + 12 * dummy; +} + +int fum (int dummy) +{ + return 2 + 13 * dummy; +} + +typedef int (A::*PMF)(int); + +typedef int A::*PMI; + +int main () +{ + A a; + A * a_p; + PMF pmf; + + PMF * pmf_p; + PMI pmi; + + a.j = 121; + a.jj = 1331; + + int k; + + a_p = &a; + + pmi = &A::j; + pmf = &A::bar; + pmf_p = &pmf; + + pmi = NULL; + + k = (a.*pmf)(3); + + pmi = &A::jj; + pmf = &A::foo; + pmf_p = &pmf; + + k = (a.*pmf)(4); + + k = (a.**pmf_p)(5); + + k = a.*pmi; + + + k = a.bar(2); + + k += fum (4); + + B b; + + k += b.s; + +} diff --git a/gdb/testsuite/gdb.cp/member-ptr.exp b/gdb/testsuite/gdb.cp/member-ptr.exp new file mode 100644 index 0000000..8243785 --- /dev/null +++ b/gdb/testsuite/gdb.cp/member-ptr.exp @@ -0,0 +1,549 @@ +# Copyright 1998, 1999, 2003 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# Please email any bugs, comments, and/or additions to this file to: +# bug-gdb@prep.ai.mit.edu +# Tests for pointer-to-member support +# Written by Satish Pai 1997-08-19 + +# This file is part of the gdb testsuite + + +if $tracelevel then { + strace $tracelevel + } + +if { [skip_cplus_tests] } { continue } + +# +# test running programs +# + +# Start with a fresh gdb +gdb_exit +gdb_start +gdb_reinitialize_dir $srcdir/$subdir + +set prms_id 0 +set bug_id 0 + +set testfile "member-ptr" +set srcfile ${testfile}.cc +set binfile ${objdir}/${subdir}/${testfile} + +# Create and source the file that provides information about the compiler +# used to compile the test case. + +if [get_compiler_info ${binfile} "c++"] { + return -1 +} + +# Nearly all of these tests fail when compiled with G++, so just give up +# until GDB gets enhanced. -sts 1999-06-22 + +if { [test_compiler_info gcc-*] } then { + continue +} + +if { [gdb_compile "${srcdir}/${subdir}/${srcfile}" "${binfile}" executable {debug c++}] != "" } { + gdb_suppress_entire_file "Testcase compile failed, so all tests in this file will automatically fail." +} + + +gdb_exit +gdb_start +gdb_reinitialize_dir $srcdir/$subdir +gdb_load ${binfile} + + +if ![runto_main] then { + perror "couldn't run to breakpoint" + continue +} + +send_gdb "break 83\n" +gdb_expect { + -re "Breakpoint \[0-9\]*.*line 83\\.\r\n$gdb_prompt $" { + pass "set break at 83" + } + -re ".*$gdb_prompt $" { fail "set break at 83" } + timeout { fail "(timeout) set break at 83" } +} + +send_gdb "continue\n" +gdb_expect { + -re "Continuing\\.\r\n\r\nBreakpoint.*at.*member-ptr\\.cc:83\r\n83\[ \t]*pmi = NULL;\r\n$gdb_prompt $" { + pass "continue to 83" + } + -re ".*$gdb_prompt $" { fail "continue to 83" } + timeout { fail "(timeout) continue to 83" } +} + +# ptype on pointer to data member + +send_gdb "ptype pmi\n" +gdb_expect { + -re "type = int \\( A::\\*\\)\r\n$gdb_prompt $" { + pass "ptype pmi" + } + -re ".*$gdb_prompt $" { fail "ptype pmi" } + timeout { fail "(timeout) ptype pmi" } +} + +# print pointer to data member + +setup_xfail "hppa*-*-*" CLLbs16901 +send_gdb "print pmi\n" +gdb_expect { + -re "\\$\[0-9\]* = \\(int \\( A::\\*\\)\\) &A::j\r\n$gdb_prompt $" { + pass "print pmi" + } + -re ".*$gdb_prompt $" { fail "print pmi" } + timeout { fail "(timeout) print pmi" } +} + + +# print dereferenced pointer to data member + +setup_xfail "hppa*-*-*" CLLbs16901 +send_gdb "print a.*pmi\n" +gdb_expect { + -re "\\$\[0-9\]* = 121\r\n$gdb_prompt $" { + pass "print a.*pmi" + } + -re ".*$gdb_prompt $" { fail "print a.*pmi" } + timeout { fail "(timeout) print a.*pmi" } +} + +# print dereferenced pointer to data member +# this time, dereferenced through a pointer + +setup_xfail "hppa*-*-*" CLLbs16901 +send_gdb "print a_p->*pmi\n" +gdb_expect { + -re "\\$\[0-9\]* = 121\r\n$gdb_prompt $" { + pass "print a->*pmi" + } + -re ".*$gdb_prompt $" { fail "print a->*pmi" } + timeout { fail "(timeout) print a->*pmi" } +} + + +# set the pointer to data member + +send_gdb "set var pmi = &A::jj\n" +gdb_expect { + -re "$gdb_prompt $" { + pass "set var (not really a pass)" + } + timeout { fail "(timeout) " } +} + +# Now print the pointer again + +send_gdb "print pmi\n" +gdb_expect { + -re "\\$\[0-9\]* = \\(int \\( A::\\*\\)\\) &A::jj\r\n$gdb_prompt $" { + pass "print pmi after setting" + } + -re ".*$gdb_prompt $" { fail "print pmi after setting" } + timeout { fail "(timeout) print pmi after setting" } +} + +# print dereferenced pointer to data member again + +send_gdb "print a.*pmi\n" +gdb_expect { + -re "\\$\[0-9\]* = 1331\r\n$gdb_prompt $" { + pass "print a.*pmi after setting" + } + -re ".*$gdb_prompt $" { fail "print a.*pmi after setting" } + timeout { fail "(timeout) print a.*pmi after setting" } +} + +# set the pointer to data member back to A::j + +send_gdb "set var pmi = &A::j\n" +gdb_expect { + -re "$gdb_prompt $" { + pass "set var back to A::j (not really a pass)" + } + timeout { fail "(timeout) set var pmi" } +} + +# print dereferenced pointer to data member yet again (extra check, why not) + +send_gdb "print a.*pmi\n" +gdb_expect { + -re "\\$\[0-9\]* = 121\r\n$gdb_prompt $" { + pass "print a.*pmi after resetting" + } + -re ".*$gdb_prompt $" { fail "print a.*pmi after resetting" } + timeout { fail "(timeout) print a.*pmi after resetting" } +} + +# Set the data member pointed to. + +send_gdb "print a.*pmi = 33\n" +gdb_expect { + -re "\\$\[0-9\]* = 33\r\n$gdb_prompt $" { + pass "print command to set" + } + -re ".*$gdb_prompt $" { fail "print command to set" } + timeout { fail "(timeout) print command to set" } +} + +# Now check that the data really was changed +send_gdb "print a.*pmi\n" +gdb_expect { + -re "\\$\[0-9\]* = 33\r\n$gdb_prompt $" { + pass "print a.*pmi after setting member pointed to" + } + -re ".*$gdb_prompt $" { fail "print a.*pmi after setting member pointed to" } + timeout { fail "(timeout) print a.*pmi after setting member pointed to" } +} + +# Double-check by printing a. +setup_xfail "hppa*-*-*" CLLbs16901 +send_gdb "print a\n" +gdb_expect { + -re "\\$\[0-9\]* = \{c = 120 'x', j = 33, jj = 1331, static s = 10, Virtual table at $hex\}\r\n$gdb_prompt $" { + pass "print a after setting member pointed to by pmi" + } + -re ".*$gdb_prompt $" { fail "print a after setting member pointed to by pmi" } + timeout { fail "(timeout) print a after setting member pointed to by pmi" } +} + + +# Set the data member pointed to, using ->* + +send_gdb "print a_p->*pmi = 44\n" +gdb_expect { + -re "\\$\[0-9\]* = 44\r\n$gdb_prompt $" { + pass "print command to set (->)" + } + -re ".*$gdb_prompt $" { fail "print command to set (->)" } + timeout { fail "(timeout) print command to set (->)" } +} + +# Now check that the data really was changed +send_gdb "print a_p->*pmi\n" +gdb_expect { + -re "\\$\[0-9\]* = 44\r\n$gdb_prompt $" { + pass "print a_p->*pmi after setting member pointed to" + } + -re ".*$gdb_prompt $" { fail "print a_p->*pmi after setting member pointed to" } + timeout { fail "(timeout) print a_p->*pmi after setting member pointed to" } +} + +# Double-check by printing a. +setup_xfail "hppa*-*-*" CLLbs16901 +send_gdb "print a\n" +gdb_expect { + -re "\\$\[0-9\]* = \{c = 120 'x', j = 44, jj = 1331, static s = 10, Virtual table at $hex\}\r\n$gdb_prompt $" { + pass "print a after setting member pointed to by pmi (->) " + } + -re ".*$gdb_prompt $" { fail "print a after setting member pointed to by pmi (->) " } + timeout { fail "(timeout) print a after setting member pointed to by pmi (->) " } +} + + +# Do a ptype on the dereferenced pointer to member +# pai/1997-08-20 Doesn't work + +# send_gdb "ptype a.*pmi\n" +# gdb_expect { +# -re "type = int\r\n$gdb_prompt $" { +# pass "ptype a.*pmi" +# } +# -re ".*$gdb_prompt $" { fail "ptype a.*pmi" } +# timeout { fail "(timeout) ptype a.*pmi" } +#} + +# Try to dereference the pointer to data member without any object + +send_gdb "print *pmi\n" +gdb_expect { + -re "Attempt to dereference pointer to member without an object\r\n$gdb_prompt $" { + pass "attempt to print ptr to member without object" + } + -re ".*$gdb_prompt $" { fail "attempt to print ptr to member without object" } + timeout { fail "(timeout) attempt to print ptr to member without object" } +} + +# Try to ptype a dereference of the pointer to data member without any object + +send_gdb "ptype *pmi\n" +gdb_expect { + -re "Attempt to dereference pointer to member without an object\r\n$gdb_prompt $" { + pass "attempt to ptype ptr to member without object" + } + -re ".*$gdb_prompt $" { fail "attempt to ptype ptr to member without object" } + timeout { fail "(timeout) attempt to ptype ptr to member without object" } +} + +# Ptype a pointer to a method. + +setup_xfail "hppa*-*-*" CLLbs16901 +send_gdb "ptype pmf\n" +gdb_expect { + -re "type = int \\( A::\\*\\)\\(\\.\\.\\.\\)\r\n$gdb_prompt $" { + pass "ptype pmf" + } + -re ".*$gdb_prompt $" { fail "ptype pmf" } + timeout { fail "(timeout) ptype pmf" } +} + +# print a pointer to a method + +setup_xfail "hppa*-*-*" CLLbs16901 +send_gdb "print pmf\n" +gdb_expect { + -re "\\$\[0-9\]* = \\(int \\( A::\\*\\)\\(\\.\\.\\.\\)\\) \\?\\? \r\n$gdb_prompt $" { + pass "print pmf" + } + -re ".*$gdb_prompt $" { fail "print pmf" } + timeout { fail "(timeout) print pmf" } +} + + +# Ptype a pointer to a pointer to a method + +setup_xfail "hppa*-*-*" CLLbs16901 +send_gdb "ptype pmf_p\n" +gdb_expect { + -re "type = int \\( A::\\*\\*\\)\\(\\.\\.\\.\\)\r\n$gdb_prompt $" { + pass "ptype pmf_p" + } + -re ".*$gdb_prompt $" { fail "ptype pmf_p" } + timeout { fail "(timeout) ptype pmf_p" } +} + +# print a pointer to a pointer to a method + +setup_xfail "hppa*-*-*" CLLbs16901 +send_gdb "print pmf_p\n" +gdb_expect { + -re "\\$\[0-9\]* = \\(int \\( A::\\*\\*\\)\\(\\.\\.\\.\\)\\) $hex\r\n$gdb_prompt $" { + pass "print pmf_p" + } + -re ".*$gdb_prompt $" { fail "print pmf_p" } + timeout { fail "(timeout) print pmf_p" } +} + +# print dereferenced pointer to method + +setup_xfail "hppa*-*-*" CLLbs16901 +send_gdb "print a.*pmf\n" +gdb_expect { + -re "Pointers to methods not supported with HP aCC\r\n$gdb_prompt $" { + pass "print a.*pmf (known aCC limitation)" + } + -re ".*$gdb_prompt $" { fail "print a.*pmf" } + timeout { fail "(timeout) print a.*pmf" } +} + +# print dereferenced pointer to method, using ->* + +setup_xfail "hppa*-*-*" CLLbs16901 +send_gdb "print a_p->*pmf\n" +gdb_expect { + -re "Pointers to methods not supported with HP aCC\r\n$gdb_prompt $" { + pass "print a_p->*pmf (known aCC limitation)" + } + -re ".*$gdb_prompt $" { fail "print a_p->*pmf" } + timeout { fail "(timeout) print a_p->*pmf" } +} + +# set the pointer to data member + +setup_xfail "hppa*-*-*" +send_gdb "set var pmf = &A::foo\n" +gdb_expect { + -re "Assignment to pointers to methods not implemented with HP aCC\r\n$gdb_prompt $" { + pass "set var pmf (known aCC limitation)" + } + -re ".*$gdb_prompt $" { fail "set var pmf" } + timeout { fail "(timeout) set var pmf" } +} + +# Try to dereference the pointer to method without any object + +setup_xfail "hppa*-*-*" CLLbs16901 +send_gdb "print *pmf\n" +gdb_expect { + -re "Attempt to dereference pointer to member without an object\r\n$gdb_prompt $" { + pass "attempt to print ptr to method without object" + } + -re ".*$gdb_prompt $" { fail "attempt to print ptr to method without object" } + timeout { fail "(timeout) attempt to print ptr to method without object" } +} + +# Try to ptype a dereference of the pointer to method without any object + +send_gdb "ptype *pmi\n" +gdb_expect { + -re "Attempt to dereference pointer to member without an object\r\n$gdb_prompt $" { + pass "attempt to ptype ptr to member without object" + } + -re ".*$gdb_prompt $" { fail "attempt to ptype ptr to member without object" } + timeout { fail "(timeout) attempt to ptype ptr to member without object" } +} + +# Check cast of pointer to member to integer +setup_xfail "hppa*-*-*" CLLbs16901 +send_gdb "print (int) pmi\n" +gdb_expect { + -re "\\$\[0-9\]* = 8\r\n$gdb_prompt $" { + pass "casting pmi to int" + } + -re ".*$gdb_prompt $" { fail "casting pmi to int" } + timeout { fail "(timeout) casting pmi to int" } +} + +# Check cast of pointer to method to integer +setup_xfail "hppa*-*-*" CLLbs16901 +send_gdb "print (int) pmf\n" +gdb_expect { + -re "Pointers to methods not supported with HP aCC\r\n$gdb_prompt $" { + pass "casting pmf to int (known aCC limitation)" + } + -re ".*$gdb_prompt $" { fail "casting pmf to int" } + timeout { fail "(timeout) casting pmf to int" } +} + +# Try to invoke a function through a pointer to data member +setup_xfail "hppa*-*-*" CLLbs16901 +send_gdb "print (a.*pmi)(3)\n" +gdb_expect { + -re "Not implemented: function invocation through pointer to method with HP aCC\r\n$gdb_prompt $" { + pass "print (a.*pmi)(3) -- error message should be different" + } + -re ".*$gdb_prompt $" { fail "print (a.*pmi)(3)" } + timeout { fail "(timeout) print (a.*pmi)(3)" } +} + +# Try to invoke a function through a pointer to a method +setup_xfail "hppa*-*-*" CLLbs16901 +send_gdb "print (a.*pmf)(3)\n" +gdb_expect { + -re "Not implemented: function invocation through pointer to method with HP aCC\r\n$gdb_prompt $" { + pass "print (a.*pmi)(3) -- known aCC limitation" + } + -re ".*$gdb_prompt $" { fail "print (a.*pmf)(3)" } + timeout { fail "(timeout) print (a.*pmf)(3)" } +} + + +# Go past assignment of NULL to pmi +setup_xfail "hppa*-*-*" CLLbs16901 +send_gdb "next\n" +gdb_expect { + -re "\r\n85\[ \t\]*k = \\(a.\\*pmf\\)\\(3\\);\r\n$gdb_prompt $" { + pass "next past 83" + } + -re ".*$gdb_prompt $" { fail "next past 83" } + timeout { fail "(timeout) next past 83" } +} + +#send_gdb "print pmi\n" +#gdb_expect { +# -re "Attempted dereference of null pointer-to-member\r\n$gdb_prompt $" { +# pass "" +# } +# -re ".*$gdb_prompt $" { fail "" } +# timeout { fail "(timeout) " } +#} + +# Dereference the null pointer to member +setup_xfail "hppa*-*-*" CLLbs16901 +send_gdb "print a.*pmi\n" +gdb_expect { + -re "Attempted dereference of null pointer-to-member\r\n$gdb_prompt $" { + pass "print a.*NULL" + } + -re ".*$gdb_prompt $" { fail "print a.*NULL" } + timeout { fail "(timeout) print a.*NULL" } +} + + +# Go to another part of the program +send_gdb "break 91\n" +gdb_expect { + -re "Breakpoint \[0-9\]*.*line 91\\.\r\n$gdb_prompt $" { + pass "set break at 91" + } + -re ".*$gdb_prompt $" { fail "set break at 91" } + timeout { fail "(timeout) set break at 91" } +} + +setup_xfail "hppa*-*-*" CLLbs16901 +send_gdb "continue\n" +gdb_expect { + -re "Continuing\\.\r\n\r\nBreakpoint.*at.*member-ptr\\.cc:91\r\n91\[ \t]*k = \\(a.\\*pmf\\)\\(4\\);\r\n$gdb_prompt $" { + pass "continue to 91" + } + -re ".*$gdb_prompt $" { fail "continue to 91" } + timeout { fail "(timeout) continue to 91" } +} + + +# Now check again that pmi works even when not set to +# something that's at the beginning of the object + +setup_xfail "hppa*-*-*" CLLbs16901 +send_gdb "print pmi\n" +gdb_expect { + -re "\\$\[0-9\]* = \\(int \\( A::\\*\\)\\) &A::jj\r\n$gdb_prompt $" { + pass "print pmi (2)" + } + -re ".*$gdb_prompt $" { fail "print pmi (2)" } + timeout { fail "(timeout) print pmi (2)" } +} + + +# print dereferenced pointer to data member + +setup_xfail "hppa*-*-*" CLLbs16901 +send_gdb "print a.*pmi\n" +gdb_expect { + -re "\\$\[0-9\]* = 1331\r\n$gdb_prompt $" { + pass "print a.*pmi (2)" + } + -re ".*$gdb_prompt $" { fail "print a.*pmi (2)" } + timeout { fail "(timeout) print a.*pmi (2)" } +} + +# print dereferenced pointer to data member +# this time, dereferenced through a pointer + +setup_xfail "hppa*-*-*" CLLbs16901 +send_gdb "print a_p->*pmi\n" +gdb_expect { + -re "\\$\[0-9\]* = 1331\r\n$gdb_prompt $" { + pass "print a->*pmi" + } + -re ".*$gdb_prompt $" { fail "print a->*pmi (2)" } + timeout { fail "(timeout) print a->*pmi (2)" } +} + + +# p a.*pmf - fail + +# p pmi + +# p a.*pmi + diff --git a/gdb/testsuite/gdb.cp/method.cc b/gdb/testsuite/gdb.cp/method.cc new file mode 100644 index 0000000..949b027 --- /dev/null +++ b/gdb/testsuite/gdb.cp/method.cc @@ -0,0 +1,80 @@ +// Class funk has a constructor and an ordinary method +// Test for CHFts23426 + +class funk +{ +public: + funk(); + void getFunky(int a, int b); + int data_; +}; + +funk::funk() + : data_(33) +{ +} + +void funk::getFunky(int a, int b) +{ + int res; + res = a + b - data_; + data_ = res; +} + +// Class A has const and volatile methods + +class A { +public: + int x; + int y; + int foo (int arg); + int bar (int arg) const; + int baz (int arg, char c) volatile; + int qux (int arg, float f) const volatile; +}; + +int A::foo (int arg) +{ + x += arg; + return arg *2; +} + +int A::bar (int arg) const +{ + return arg + 2 * x; +} + +int A::baz (int arg, char c) volatile +{ + return arg - 2 * x + c; +} + +int A::qux (int arg, float f) const volatile +{ + if (f > 0) + return 2 * arg - x; + else + return 2 * arg + x; +} + + +int main() +{ + A a; + int k; + + k = 10; + a.x = k * 2; + + k = a.foo(13); + + k += a.bar(15); + + // Test for CHFts23426 follows + funk f; + f.getFunky(1, 2); + return 0; +} + + + diff --git a/gdb/testsuite/gdb.cp/method.exp b/gdb/testsuite/gdb.cp/method.exp new file mode 100644 index 0000000..729b930 --- /dev/null +++ b/gdb/testsuite/gdb.cp/method.exp @@ -0,0 +1,194 @@ +# Copyright 1998, 1999, 2001, 2002, 2003 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# Please email any bugs, comments, and/or additions to this file to: +# bug-gdb@prep.ai.mit.edu + +# tests for misc. C++ method stuff +# Written by Satish Pai 1997-07-08 + +# This file is part of the gdb testsuite + +# This tests: +# 0. method arguments are correct +# 1. access to class data members inside method scopes +# 2. correct param types for methods in ptype. +# 3. const and volatile methods + +# (#0 and #1 above relate to an HP specific problem -- GDB must correctly +# integrate FPARAM symbols in HP debug info into the local var list +# for the function or method's block.) + +if $tracelevel then { + strace $tracelevel + } + +# +# test running programs +# +set prms_id 0 +set bug_id 0 + +if { [skip_cplus_tests] } { continue } + +set testfile "method" +set srcfile ${testfile}.cc +set binfile ${objdir}/${subdir}/${testfile} + +if { [gdb_compile "${srcdir}/${subdir}/${srcfile}" "${binfile}" executable {debug c++}] != "" } { + gdb_suppress_entire_file "Testcase compile failed, so all tests in this file will automatically fail." +} + +if [get_compiler_info $binfile "c++"] { + return -1 +} + +gdb_exit +gdb_start +gdb_reinitialize_dir $srcdir/$subdir +gdb_load ${binfile} + + +# +# set it up at a breakpoint so we can play with the variable values +# +if ![runto_main] then { + perror "couldn't run to breakpoint" + continue +} + +gdb_test "break A::foo" \ + "Breakpoint \[0-9\]* at $hex.*file .*method.cc, line 38\\." + +gdb_test "continue" \ + "Continuing\\.\r\n\r\nBreakpoint \[0-9\]*, A::foo(\\(int\\)|) \\(this=$hex, arg=13\\) at .*method\\.cc:38\r\n38\[\t \]*x \\+= arg;" \ + "continue to A::foo" + +# Check ability to access this-relative stuff. + +gdb_test "print x" \ + "\\$\[0-9\]* = 20" \ + "print x in A::foo" + +# Check access to this pointer + +gdb_test "print this" \ + "\\$\[0-9\]* = \\((class |)A *\\* *(const|)\\) $hex" \ + "print this in A::foo" + +# Now do everything over again for A::bar, because sometimes processing one method +# (the first one) is fine, but the second one's debug info gets munged beyond recognition. + +gdb_test "break A::bar" \ + "Breakpoint \[0-9\]* at $hex.*file .*method.cc, line 44\\." + +gdb_test "continue" \ + "Continuing\\.\r\n\r\nBreakpoint \[0-9\]*, A::bar(|\\(int\\) const| const) \\(this=$hex, arg=15\\) at .*method\\.cc:44\r\n44\[\t \]*return arg \\+ 2 \\* x;" \ + "continue to A::bar" + +# Check ability to access this-relative stuff. + +gdb_test "print x" \ + "\\$\[0-9\]* = 33" \ + "print x in A::bar" + +# Check access to this pointer + +get_debug_format + +send_gdb "print this\n" +gdb_expect { + -re "\\$\[0-9\]* = \\(const (class |)A *\\* *(const|)\\) $hex\r\n$gdb_prompt $" { + pass "print this in A::bar" + } + -re "\\$\[0-9\]* = \\((class |)A *\\* *(const|)\\) $hex\r\n$gdb_prompt $" { + # gcc versions up to 3.0.4 with -gstabs+ do not emit "const" indicators, + # so the output is "A *". It should be "const A *" or "const A * const". + setup_xfail_format "stabs" + fail "print this in A::bar (missing const)" + } + -re "\\$\[0-9\]* = \\(const (class |)\{\\.\\.\\.\} *\\* *(const|)\\) $hex\r\n$gdb_prompt $" { + # gcc versions gcc-3_1-branch%20020404 and HEAD%20020404 with -gstabs+ + # produce good stabs, but gdb prints "const class {...} *" const. + # This is PR gdb/277. + # setup_kfail "gdb/277" + fail "print this in A::bar (gdb/277)" + } + -re ".*$gdb_prompt $" { fail "print this in A::bar" } + timeout { fail "(timeout) print this in A::bar" } +} + +# Check again with funk::getFunky (this is the original test case +# for CHFts23426); sometimes having a constructor with no arguments +# will nuke the debug info read in for other methods in the class. + +gdb_test "break 21" \ + "Breakpoint \[0-9\]* at $hex.*file .*method.cc, line 21\\." + +gdb_test "continue" \ + "Continuing\\.\r\n\r\nBreakpoint \[0-9\]*, funk::getFunky(\\(int, int\\)|) \\(this=$hex, a=1, b=2\\) at .*method\\.cc:21\r\n21\[\t \]*data_ = res;" \ + "continue to 21" + +# Check ability to access this-relative stuff. + +gdb_test "print data_" \ + "\\$\[0-9\]* = 33" \ + "print data_ in funk::getFunky" + +# Check access to this pointer + +gdb_test "print this" \ + "\\$\[0-9\]* = \\((class |)funk *\\* *(const|)\\) $hex" \ + "print this in funk::getFunky" + +# Check access to local variable + +gdb_test "print res" \ + "\\$\[0-9\]* = -30" \ + "print res in funk::getFunky" + +# Check ptype of class -- should show const/volatile methods + +send_gdb "ptype A\n" +gdb_expect { + -re "type = class A \{\r\n\[ \]*public:\r\n\[ \]*int x;\r\n\[ \]*int y;\r\n\r\n\[ \]*int foo\\(int\\);\r\n\[ \]*int bar\\(int\\) const;\r\n\[ \]*int baz\\(int, char\\) volatile;\r\n\[ \]*int qux\\(int, float\\) (const volatile|volatile const);\r\n\}\r\n$gdb_prompt $" { + pass "ptype A" + } + -re "type = class A \{\r\n\[ \]*public:\r\n\[ \]*int x;\r\n\[ \]*int y;\r\n\r\n\[ \]*A & operator=\\(A const ?&\\);\r\n\[ \]*A\\(A const ?&\\);\r\n\[ \]*A\\((void|)\\);\r\n\[ \]*int foo\\(int\\);\r\n\[ \]*int bar\\(int\\) const;\r\n\[ \]*int baz\\(int, char\\) volatile;\r\n\[ \]*int qux\\(int, float\\) (const volatile|volatile const);\r\n\}\r\n$gdb_prompt $" { + pass "ptype A" + } + -re "type = class A \{\r\n\[ \]*public:\r\n\[ \]*int x;\r\n\[ \]*int y;\r\n\r\n\[ \]*int foo\\(int\\);\r\n\[ \]*int bar\\(int\\) const;\r\n\[ \]*int baz\\(int, char\\);\r\n\[ \]*int qux\\(int, float\\) const;\r\n\}\r\n$gdb_prompt $" { + pass "ptype A (HP aCC bug -- volatile not indicated)" + } + -re "type = class A \{\r\n\[ \]*public:\r\n\[ \]*int x;\r\n\[ \]*int y;\r\n\r\n\[ \]*int foo\\(int\\);\r\n\[ \]*int bar\\(int\\) const;\r\n\[ \]*int baz\\(int, char\\) volatile;\r\n\[ \]*int qux\\(int, float\\) const volatile;\r\n\}\r\n$gdb_prompt $" { + pass "ptype A" + } + -re ".*$gdb_prompt $" { fail "ptype A" } + timeout { fail "(timeout) ptype A" } +} + +send_gdb "cont\n" +gdb_expect { + -re "Continuing.\r\n\r\nProgram exited normally.*$gdb_prompt $" { + pass "finish program" + } + -re "Continuing.* EXIT code 0.*Program exited normally.*$gdb_prompt $" { + pass "finish program (exit wrapper)" + } + -re ".*$gdb_prompt $" { fail "finish program" } + default:{ fail "finish program (timeout)" } +} + diff --git a/gdb/testsuite/gdb.cp/misc.cc b/gdb/testsuite/gdb.cp/misc.cc new file mode 100644 index 0000000..286c02b --- /dev/null +++ b/gdb/testsuite/gdb.cp/misc.cc @@ -0,0 +1,587 @@ +// Test various -*- C++ -*- things. + +// ====================== basic C++ types ======================= +bool v_bool; +bool v_bool_array[2]; + +typedef struct fleep fleep; +struct fleep { int a; } s; + +// ====================== simple class structures ======================= + +struct default_public_struct { + // defaults to public: + int a; + int b; +}; + +struct explicit_public_struct { + public: + int a; + int b; +}; + +struct protected_struct { + protected: + int a; + int b; +}; + +struct private_struct { + private: + int a; + int b; +}; + +struct mixed_protection_struct { + public: + int a; + int b; + private: + int c; + int d; + protected: + int e; + int f; + public: + int g; + private: + int h; + protected: + int i; +}; + +class public_class { + public: + int a; + int b; +}; + +class protected_class { + protected: + int a; + int b; +}; + +class default_private_class { + // defaults to private: + int a; + int b; +}; + +class explicit_private_class { + private: + int a; + int b; +}; + +class mixed_protection_class { + public: + int a; + int b; + private: + int c; + int d; + protected: + int e; + int f; + public: + int g; + private: + int h; + protected: + int i; +}; + +class const_vol_method_class { +public: + int a; + int b; + int foo (int &) const; + int bar (int &) volatile; + int baz (int &) const volatile; +}; + +int const_vol_method_class::foo (int & ir) const +{ + return ir + 3; +} +int const_vol_method_class::bar (int & ir) volatile +{ + return ir + 4; +} +int const_vol_method_class::baz (int & ir) const volatile +{ + return ir + 5; +} + +// ========================= simple inheritance ========================== + +class A { + public: + int a; + int x; +}; + +A g_A; + +class B : public A { + public: + int b; + int x; +}; + +B g_B; + +class C : public A { + public: + int c; + int x; +}; + +C g_C; + +class D : public B, public C { + public: + int d; + int x; +}; + +D g_D; + +class E : public D { + public: + int e; + int x; +}; + +E g_E; + +class class_with_anon_union +{ + public: + int one; + union + { + int a; + long b; + }; +}; + +class_with_anon_union g_anon_union; + +void inheritance2 (void) +{ +} + +void inheritance1 (void) +{ + int ival; + int *intp; + + // {A::a, A::x} + + g_A.A::a = 1; + g_A.A::x = 2; + + // {{A::a,A::x},B::b,B::x} + + g_B.A::a = 3; + g_B.A::x = 4; + g_B.B::b = 5; + g_B.B::x = 6; + + // {{A::a,A::x},C::c,C::x} + + g_C.A::a = 7; + g_C.A::x = 8; + g_C.C::c = 9; + g_C.C::x = 10; + + // {{{A::a,A::x},B::b,B::x},{{A::a,A::x},C::c,C::x},D::d,D::x} + + // The following initialization code is non-portable, but allows us + // to initialize all members of g_D until we can fill in the missing + // initialization code with legal C++ code. + + for (intp = (int *) &g_D, ival = 11; + intp < ((int *) &g_D + sizeof (g_D) / sizeof (int)); + intp++, ival++) + { + *intp = ival; + } + + // Overlay the nonportable initialization with legal initialization. + + // ????? = 11; (g_D.A::a = 11; is ambiguous) + // ????? = 12; (g_D.A::x = 12; is ambiguous) +/* djb 6-3-2000 + + This should take care of it. Rather than try to initialize using an ambiguous + construct, use 2 unambiguous ones for each. Since the ambiguous a/x member is + coming from C, and B, initialize D's C::a, and B::a, and D's C::x and B::x. + */ + g_D.C::a = 15; + g_D.C::x = 12; + g_D.B::a = 11; + g_D.B::x = 12; + g_D.B::b = 13; + g_D.B::x = 14; + // ????? = 15; + // ????? = 16; + g_D.C::c = 17; + g_D.C::x = 18; + g_D.D::d = 19; + g_D.D::x = 20; + + + // {{{{A::a,A::x},B::b,B::x},{{A::a,A::x},C::c,C::x},D::d,D::x}},E::e,E::x} + + // The following initialization code is non-portable, but allows us + // to initialize all members of g_D until we can fill in the missing + // initialization code with legal C++ code. + + for (intp = (int *) &g_E, ival = 21; + intp < ((int *) &g_E + sizeof (g_E) / sizeof (int)); + intp++, ival++) + { + *intp = ival; + } + + // Overlay the nonportable initialization with legal initialization. + + // ????? = 21; (g_E.A::a = 21; is ambiguous) + // ????? = 22; (g_E.A::x = 22; is ambiguous) + g_E.B::b = 23; + g_E.B::x = 24; + // ????? = 25; + // ????? = 26; + g_E.C::c = 27; + g_E.C::x = 28; + g_E.D::d = 29; + g_E.D::x = 30; + g_E.E::e = 31; + g_E.E::x = 32; + + g_anon_union.one = 1; + g_anon_union.a = 2; + + inheritance2 (); +} + +// ======================== static member functions ===================== + +class Static { +public: + static void ii(int, int); +}; +void Static::ii (int, int) { } + +// ======================== virtual base classes========================= + +class vA { + public: + int va; + int vx; +}; + +vA g_vA; + +class vB : public virtual vA { + public: + int vb; + int vx; +}; + +vB g_vB; + +class vC : public virtual vA { + public: + int vc; + int vx; +}; + +vC g_vC; + +class vD : public virtual vB, public virtual vC { + public: + int vd; + int vx; +}; + +vD g_vD; + +class vE : public virtual vD { + public: + int ve; + int vx; +}; + +vE g_vE; + +void inheritance4 (void) +{ +} + +void inheritance3 (void) +{ + int ival; + int *intp; + + // {vA::va, vA::vx} + + g_vA.vA::va = 1; + g_vA.vA::vx = 2; + + // {{vA::va, vA::vx}, vB::vb, vB::vx} + + g_vB.vA::va = 3; + g_vB.vA::vx = 4; + g_vB.vB::vb = 5; + g_vB.vB::vx = 6; + + // {{vA::va, vA::vx}, vC::vc, vC::vx} + + g_vC.vA::va = 7; + g_vC.vA::vx = 8; + g_vC.vC::vc = 9; + g_vC.vC::vx = 10; + + // {{{{vA::va, vA::vx}, vB::vb, vB::vx}, vC::vc, vC::vx}, vD::vd,vD::vx} + + g_vD.vA::va = 11; + g_vD.vA::vx = 12; + g_vD.vB::vb = 13; + g_vD.vB::vx = 14; + g_vD.vC::vc = 15; + g_vD.vC::vx = 16; + g_vD.vD::vd = 17; + g_vD.vD::vx = 18; + + + // {{{{{vA::va,vA::vx},vB::vb,vB::vx},vC::vc,vC::vx},vD::vd,vD::vx},vE::ve,vE::vx} + + g_vD.vA::va = 19; + g_vD.vA::vx = 20; + g_vD.vB::vb = 21; + g_vD.vB::vx = 22; + g_vD.vC::vc = 23; + g_vD.vC::vx = 24; + g_vD.vD::vd = 25; + g_vD.vD::vx = 26; + g_vE.vE::ve = 27; + g_vE.vE::vx = 28; + + inheritance4 (); +} + +// ====================================================================== + +class Base1 { + public: + int x; + Base1(int i) { x = i; } +}; + +class Foo +{ + public: + int x; + int y; + static int st; + Foo (int i, int j) { x = i; y = j; } + int operator! (); + operator int (); + int times (int y); +}; + +class Bar : public Base1, public Foo { + public: + int z; + Bar (int i, int j, int k) : Base1 (10*k), Foo (i, j) { z = k; } +}; + +int Foo::operator! () { return !x; } + +int Foo::times (int y) { return x * y; } + +int Foo::st = 100; + +Foo::operator int() { return x; } + +Foo foo(10, 11); +Bar bar(20, 21, 22); + +class ClassWithEnum { +public: + enum PrivEnum { red, green, blue, yellow = 42 }; + PrivEnum priv_enum; + int x; +}; + +void enums2 (void) +{ +} + +/* classes.exp relies on statement order in this function for testing + enumeration fields. */ + +void enums1 () +{ + ClassWithEnum obj_with_enum; + obj_with_enum.priv_enum = ClassWithEnum::red; + obj_with_enum.x = 0; + enums2 (); + obj_with_enum.priv_enum = ClassWithEnum::green; +} + +class ClassParam { +public: + int Aptr_a (A *a) { return a->a; } + int Aptr_x (A *a) { return a->x; } + int Aref_a (A &a) { return a.a; } + int Aref_x (A &a) { return a.x; } + int Aval_a (A a) { return a.a; } + int Aval_x (A a) { return a.x; } +}; + +ClassParam class_param; + +class Contains_static_instance +{ + public: + int x; + int y; + Contains_static_instance (int i, int j) { x = i; y = j; } + static Contains_static_instance null; +}; + +Contains_static_instance Contains_static_instance::null(0,0); +Contains_static_instance csi(10,20); + +class Contains_nested_static_instance +{ + public: + class Nested + { + public: + Nested(int i) : z(i) {} + int z; + static Contains_nested_static_instance xx; + }; + + Contains_nested_static_instance(int i, int j) : x(i), y(j) {} + + int x; + int y; + + static Contains_nested_static_instance null; + static Nested yy; +}; + +Contains_nested_static_instance Contains_nested_static_instance::null(0, 0); +Contains_nested_static_instance::Nested Contains_nested_static_instance::yy(5); +Contains_nested_static_instance + Contains_nested_static_instance::Nested::xx(1,2); +Contains_nested_static_instance cnsi(30,40); + +typedef struct { + int one; + int two; +} tagless_struct; +tagless_struct v_tagless; + +/* Try to get the compiler to allocate a class in a register. */ +class small { + public: + int x; + int method (); +}; + +int +small::method () +{ + return x + 5; +} + +void marker_reg1 () {} + +int +register_class () +{ + /* We don't call any methods for v, so gcc version cygnus-2.3.3-930220 + might put this variable in a register. This is a lose, though, because + it means that GDB can't call any methods for that variable. */ + register small v; + + int i; + + /* Perform a computation sufficiently complicated that optimizing compilers + won't optimized out the variable. If some compiler constant-folds this + whole loop, maybe using a parameter to this function here would help. */ + v.x = 0; + for (i = 0; i < 13; ++i) + v.x += i; + --v.x; /* v.x is now 77 */ + marker_reg1 (); + return v.x + 5; +} + +void dummy() +{ + v_bool = true; + v_bool_array[0] = false; + v_bool_array[1] = v_bool; +} + +void use_methods () +{ + /* Refer to methods so that they don't get optimized away. */ + int i; + i = class_param.Aptr_a (&g_A); + i = class_param.Aptr_x (&g_A); + i = class_param.Aref_a (g_A); + i = class_param.Aref_x (g_A); + i = class_param.Aval_a (g_A); + i = class_param.Aval_x (g_A); +} + + +int +main() +{ +#ifdef usestubs + set_debug_traps(); + breakpoint(); +#endif + dummy(); + inheritance1 (); + inheritance3 (); + enums1 (); + register_class (); + + /* FIXME: pmi gets optimized out. Need to do some more computation with + it or something. (No one notices, because the test is xfail'd anyway, + but that probably won't always be true...). */ + int Foo::* pmi = &Foo::y; + + /* Make sure the AIX linker doesn't remove the variable. */ + v_tagless.one = 5; + + use_methods (); + + return foo.*pmi; +} + +/* Create an instance for some classes, otherwise they get optimized away. */ + +default_public_struct default_public_s; +explicit_public_struct explicit_public_s; +protected_struct protected_s; +private_struct private_s; +mixed_protection_struct mixed_protection_s; +public_class public_c; +protected_class protected_c; +default_private_class default_private_c; +explicit_private_class explicit_private_c; +mixed_protection_class mixed_protection_c; diff --git a/gdb/testsuite/gdb.cp/misc.exp b/gdb/testsuite/gdb.cp/misc.exp new file mode 100644 index 0000000..a2d122f --- /dev/null +++ b/gdb/testsuite/gdb.cp/misc.exp @@ -0,0 +1,159 @@ +# Copyright 1992, 1994, 1995, 1996, 1997, 1999, 2002 Free Software +# Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# Please email any bugs, comments, and/or additions to this file to: +# bug-gdb@prep.ai.mit.edu + +# This file was written by Fred Fish. (fnf@cygnus.com) + +if $tracelevel then { + strace $tracelevel +} + +if { [skip_cplus_tests] } { continue } + +set testfile "misc" +set srcfile ${testfile}.cc +set binfile ${objdir}/${subdir}/${testfile} +if { [gdb_compile "${srcdir}/${subdir}/${srcfile}" "${binfile}" executable {debug c++}] != "" } { + gdb_suppress_entire_file "Testcase compile failed, so all tests in this file will automatically fail." +} + +# +# Deduce language of main() +# + +proc deduce_language_of_main {} { + global gdb_prompt + + # See what language gdb thinks main() is, prior to reading full symbols. + # I think this fails for COFF targets. + send_gdb "show language\n" + gdb_expect { + -re ".* source language is \"auto; currently c\[+\]+\".*$gdb_prompt $" { + pass "deduced language is C++, before full symbols" + } + -re ".*$gdb_prompt $" { + fail "source language not correct for C++ (psymtabs only)" + return + } + timeout { + fail "can't show language (timeout)" + return + } + } + + runto_main + + # See if our idea of the language has changed. + + send_gdb "show language\n" + gdb_expect { + -re ".* source language is \"auto; currently c\[+\]+\".*$gdb_prompt $" { + pass "deduced language is C++, after full symbols" + } + -re ".*$gdb_prompt $" { + fail "source language not correct for C++ (full symbols)" + return + } + timeout { + fail "can't show language (timeout)" + return + } + } +} + +proc test_expr { args } { + if { [llength $args] % 2 } { + warning "an even # of arguments should be passed to test_expr" + } + set last_ent [expr [llength $args] - 1]; + set testname [lindex $args $last_ent]; + if [gdb_test [lindex $args 0] "" "$testname (setup)"] { + gdb_suppress_tests; + } + for {set x 1} {$x < $last_ent} {set x [expr $x + 2]} { + if [gdb_test [lindex $args $x] [lindex $args [expr $x + 1]] "$testname ([lindex $args $x])"] { + gdb_suppress_tests; + } + } + gdb_stop_suppressing_tests; +} + +proc do_tests {} { + global prms_id + global bug_id + global subdir + global objdir + global srcdir + global binfile + global gdb_prompt + + set prms_id 0 + set bug_id 0 + + # Start with a fresh gdb. + + gdb_exit + gdb_start + gdb_reinitialize_dir $srcdir/$subdir + gdb_load $binfile + + deduce_language_of_main + # Check for fixes for PRs 8916 and 8630 + gdb_test "print s.a" ".* = 0" "print s.a for foo struct (known gcc 2.7.2 and earlier bug)" +} + +do_tests + +test_expr "set language c++" \ + "print 1 == 1" "print.*\\$\[0-9\]* = true" \ + "print 1 == 2" "print.*\\$\[0-9\]* = false" \ + "print as bool" + +# Test bool type printing, etc. +# Note: Language is already set to C++ above! +gdb_test "print v_bool" "\\$\[0-9\]* = false" "print a bool var" + +# set a bool variable +test_expr "set variable v_bool = true" \ + "print v_bool" "\\$\[0-9\]* = true" \ + "set a bool var" + +# next print an array of bool +gdb_test "print v_bool_array" "\\$\[0-9\]* = \\{false, false\\}" "print a bool array" + +# set elements of a bool array +test_expr "set variable v_bool_array\[1\] = true" \ + "print v_bool_array" "\\$\[0-9\]* = \\{false, true\\}" \ + "set a bool array elem" + +# bool constants +gdb_test "print true" "\\$\[0-9\]* = true" "print true" +gdb_test "print false" "\\$\[0-9\]* = false" "print false" + +# arithmetic conversions +gdb_test "print 1 + true" "\\$\[0-9\]* = 2" "1 + true" +gdb_test "print 3 + false" "\\$\[0-9\]* = 3" "3 + false" +gdb_test "print 1 < 2 < 3" "\\$\[0-9\]* = true" "1 < 2 < 3" +gdb_test "print 2 < 1 > 4" "\\$\[0-9\]* = false" "2 < 1 > 4" +gdb_test "print (bool)43" "\\$\[0-9\]* = true" "(bool)43" +gdb_test "print (bool)0" "\\$\[0-9\]* = false" "(bool)0" +gdb_test "print (bool)17.93" "\\$\[0-9\]* = true" "(bool)17.93" +gdb_test "print (bool)0.0" "\\$\[0-9\]* = false" "(bool)0.0" +gdb_test "print (int)true" "\\$\[0-9\]* = 1" "(int)true" +gdb_test "print (int)false" "\\$\[0-9\]* = 0" "(int)false" diff --git a/gdb/testsuite/gdb.cp/namespace.cc b/gdb/testsuite/gdb.cp/namespace.cc new file mode 100644 index 0000000..a0814ee --- /dev/null +++ b/gdb/testsuite/gdb.cp/namespace.cc @@ -0,0 +1,182 @@ +namespace AAA { + char c; + int i; + int A_xyzq (int); + char xyzq (char); + class inA { + public: + int xx; + int fum (int); + }; +}; + +int AAA::inA::fum (int i) +{ + return 10 + i; +} + +namespace BBB { + char c; + int i; + int B_xyzq (int); + char xyzq (char); + + namespace CCC { + char xyzq (char); + }; + + class Class { + public: + char xyzq (char); + int dummy; + }; +}; + +int AAA::A_xyzq (int x) +{ + return 2 * x; +} + +char AAA::xyzq (char c) +{ + return 'a'; +} + + +int BBB::B_xyzq (int x) +{ + return 3 * x; +} + +char BBB::xyzq (char c) +{ + return 'b'; +} + +char BBB::CCC::xyzq (char c) +{ + return 'z'; +} + +char BBB::Class::xyzq (char c) +{ + return 'o'; +} + +void marker1(void) +{ + return; +} + +namespace +{ + int X = 9; + + namespace G + { + int Xg = 10; + + namespace + { + int XgX = 11; + } + } +} + +namespace C +{ + int c = 1; + int shadow = 12; + + namespace + { + int cX = 6; + + namespace F + { + int cXf = 7; + + namespace + { + int cXfX = 8; + } + } + } + + namespace C + { + int cc = 2; + } + + namespace E + { + int ce = 4; + } + + namespace D + { + int cd = 3; + int shadow = 13; + + namespace E + { + int cde = 5; + } + + void marker2 (void) + { + // NOTE: carlton/2003-04-23: I'm listing the expressions that I + // plan to have GDB try to print out, just to make sure that the + // compiler and I agree which ones should be legal! It's easy + // to screw up when testing the boundaries of namespace stuff. + c; + //cc; + C::cc; + cd; + //C::D::cd; + E::cde; + shadow; + //E::ce; + cX; + F::cXf; + F::cXfX; + X; + G::Xg; + //cXOtherFile; + //XOtherFile; + G::XgX; + + return; + } + + } +} + +int main () +{ + using AAA::inA; + char c1; + + using namespace BBB; + + c1 = xyzq ('x'); + c1 = AAA::xyzq ('x'); + c1 = BBB::CCC::xyzq ('m'); + + inA ina; + + ina.xx = 33; + + int y; + + y = AAA::A_xyzq (33); + y += B_xyzq (44); + + BBB::Class cl; + + c1 = cl.xyzq('e'); + + marker1(); + + C::D::marker2 (); +} diff --git a/gdb/testsuite/gdb.cp/namespace.exp b/gdb/testsuite/gdb.cp/namespace.exp new file mode 100644 index 0000000..228d791 --- /dev/null +++ b/gdb/testsuite/gdb.cp/namespace.exp @@ -0,0 +1,259 @@ +# Copyright 1997, 1998, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# Please email any bugs, comments, and/or additions to this file to: +# bug-gdb@prep.ai.mit.edu + +# tests for namespaces +# Originally written by Satish Pai 1997-07-23 + +# This file is part of the gdb testsuite + +# Note: The original tests were geared to the HP aCC compiler, +# which has an idiosyncratic way of emitting debug info +# for namespaces. +# Note: As of 2000-06-03, these pass under g++ - djb + + +if $tracelevel then { + strace $tracelevel + } + +set prms_id 0 +set bug_id 0 + +if { [skip_cplus_tests] } { continue } + +set testfile "namespace" +set srcfile ${testfile}.cc +set objfile ${objdir}/${subdir}/${testfile}.o +set srcfile1 ${testfile}1.cc +set objfile1 ${objdir}/${subdir}/${testfile}1.o +set binfile ${objdir}/${subdir}/${testfile} + +if [get_compiler_info ${binfile}] { + return -1; +} + +if { [gdb_compile "${srcdir}/${subdir}/${srcfile}" "${objfile}" object {debug c++}] != "" } { + gdb_suppress_entire_file "Testcase compile failed, so all tests in this file will automatically fail." +} + +if { [gdb_compile "${srcdir}/${subdir}/${srcfile1}" "${objfile1}" object {debug c++}] != "" } { + gdb_suppress_entire_file "Testcase compile failed, so all tests in this file will automatically fail." +} + +if { [gdb_compile "${objfile} ${objfile1}" "${binfile}" executable {debug c++}] != "" } { + gdb_suppress_entire_file "Testcase compile failed, so all tests in this file will automatically fail." +} + +gdb_exit +gdb_start +gdb_reinitialize_dir $srcdir/$subdir +gdb_load ${binfile} + + +# +# set it up at a breakpoint so we can play with the variable values +# +if ![runto_main] then { + perror "couldn't run to breakpoint" + continue +} + +if ![runto 'marker1'] then { + perror "couldn't run to marker1" + continue +} + +gdb_test "up" ".*main.*" "up from marker1" + +# Access a data item inside a namespace using colons and +# single quotes :-( + +# NOTE: carlton/2003-09-24: the quotes are becoming less necessary (or +# even desirable.) For tests where it should still work with quotes, +# I'm including versions both with and without quotes; for tests that +# shouldn't work with quotes, I'm only including one version. + +send_gdb "print 'AAA::c'\n" +gdb_expect { + -re "\\$\[0-9\]* = 0 '\\\\(0|000)'\r\n$gdb_prompt $" { pass "print 'AAA::c'" } + -re ".*$gdb_prompt $" { fail "print 'AAA::c'" } + timeout { fail "(timeout) print 'AAA::c'" } +} + +send_gdb "print AAA::c\n" +gdb_expect { + -re "\\$\[0-9\]* = 0 '\\\\(0|000)'\r\n$gdb_prompt $" { pass "print AAA::c" } + -re ".*$gdb_prompt $" { fail "print AAA::c" } + timeout { fail "(timeout) print AAA::c" } +} + +# An object declared using "using". + +send_gdb "print ina\n" +gdb_expect { + -re "\\$\[0-9\]+ = {xx = 33}.*$gdb_prompt $" { + pass "print ina" + } + -re ".*$gdb_prompt $" { fail "print ina" } + timeout { fail "(timeout) print ina" } +} + +send_gdb "ptype ina\n" +gdb_expect { + -re "type = class (AAA::|)inA \{\r\n\[ \]*public:\r\n\[ \]*int xx;\r\n\[ \]*\r\n\[ \]*.*int fum\\(int\\);\r\n\}\r\n$gdb_prompt $" { + pass "ptype ina" + } + -re ".*$gdb_prompt $" { fail "ptype ina" } + timeout { fail "(timeout) ptype ina" } +} + +# Check all functions are known to GDB + +setup_xfail hppa*-*-*11* CLLbs14869 +send_gdb "info func xyzq\n" +gdb_expect { + -re "All functions.*File.*namespace.cc:\r\nint AAA::A_xyzq\\(int\\);\r\nint BBB::B_xyzq\\(int\\);\r\nchar AAA::xyzq\\(char\\);\r\nchar BBB::xyzq\\(char\\);\r\nchar BBB::CCC::xyzq\\(char\\);\r\nchar BBB::Class::xyzq\\(char\\);\r\n$gdb_prompt $" { + pass "info func xyzq" + } + -re "All functions.*File.*namespace.cc:\r\nint AAA::A_xyzq\\(int\\);\r\nchar AAA::xyzq\\(char\\);\r\nint BBB::B_xyzq\\(int\\);\r\nchar BBB::CCC::xyzq\\(char\\);\r\nchar BBB::Class::xyzq\\(char\\);\r\nchar BBB::xyzq\\(char\\);\r\n$gdb_prompt $" { + pass "info func xyzq" + } + -re ".*$gdb_prompt $" { fail "info func xyzq" } + timeout { fail "(timeout) info func xyzq" } +} + +# Call a function in a namespace + +send_gdb "print 'AAA::xyzq'('x')\n" +gdb_expect { + -re "\\$\[0-9\]* = 97 'a'\r\n$gdb_prompt $" { + pass "print 'AAA::xyzq'('x')" + } + -re ".*$gdb_prompt $" { fail "print 'AAA::xyzq'('x')" } + timeout { fail "(timeout) print 'AAA::xyzq'('x')" } +} + +send_gdb "print AAA::xyzq('x')\n" +gdb_expect { + -re "\\$\[0-9\]* = 97 'a'\r\n$gdb_prompt $" { + pass "print AAA::xyzq('x')" + } + -re ".*$gdb_prompt $" { fail "print AAA::xyzq('x')" } + timeout { fail "(timeout) print AAA::xyzq('x')" } +} + +# Break on a function in a namespace + +send_gdb "break AAA::xyzq\n" +gdb_expect { + -re "Breakpoint.*at $hex: file.*namespace.cc, line 42\\.\r\n$gdb_prompt $" { + pass "break AAA::xyzq" + } + -re ".*$gdb_prompt $" { fail "break AAA::xyzq" } + timeout { fail "(timeout) break AAA::xyzq" } +} + +# Call a function in a nested namespace + +send_gdb "print 'BBB::CCC::xyzq'('x')\n" +gdb_expect { + -re "\\$\[0-9\]* = 122 'z'\r\n$gdb_prompt $" { + pass "print 'BBB::CCC::xyzq'('x')" + } + -re ".*$gdb_prompt $" { fail "print 'BBB::CCC::xyzq'('x')" } + timeout { fail "(timeout) print 'BBB::CCC::xyzq'('x')" } +} + +send_gdb "print BBB::CCC::xyzq('x')\n" +gdb_expect { + -re "\\$\[0-9\]* = 122 'z'\r\n$gdb_prompt $" { + pass "print BBB::CCC::xyzq('x')" + } + -re ".*$gdb_prompt $" { fail "print BBB::CCC::xyzq('x')" } + timeout { fail "(timeout) print BBB::CCC::xyzq('x')" } +} + +# Break on a function in a nested namespace + +send_gdb "break BBB::CCC::xyzq\n" +gdb_expect { + -re "Breakpoint.*at $hex: file.*namespace.cc, line 58\\.\r\n$gdb_prompt $" { + pass "break BBB::CCC::xyzq" + } + -re ".*$gdb_prompt $" { fail "break BBB::CCC::xyzq" } + timeout { fail "(timeout) break BBB::CCC::xyzq" } +} + +# Print address of a function in a class in a namespace + +send_gdb "print 'BBB::Class::xyzq'\n" +gdb_expect { + -re "\\$\[0-9\]* = \{char \\((BBB::|)Class \\*( const|), (char|int)\\)\} $hex \r\n$gdb_prompt $" { + pass "print 'BBB::Class::xyzq'" + } + -re ".*$gdb_prompt $" { fail "print 'BBB::Class::xyzq'" } + timeout { fail "(timeout) print 'BBB::Class::xyzq'" } +} + +# Break on a function in a class in a namespace + +send_gdb "break BBB::Class::xyzq\n" +gdb_expect { + -re "Breakpoint.*at $hex: file.*namespace.cc, line 63\\.\r\n$gdb_prompt $" { + pass "break BBB::Class::xyzq" + } + -re ".*$gdb_prompt $" { fail "break BBB::Class::xyzq" } + timeout { fail "(timeout) break BBB::Class::xyzq" } +} + +# Test to see if the appropriate namespaces are in scope when trying +# to print out stuff from within a function defined within a +# namespace. + +if ![runto "C::D::marker2"] then { + perror "couldn't run to marker2" + continue +} + +gdb_test "print c" "\\$\[0-9\].* = 1" +gdb_test "print cc" "No symbol \"cc\" in current context." +gdb_test "print 'C::cc'" "\\$\[0-9\].* = 2" +gdb_test "print C::cc" "\\$\[0-9\].* = 2" +gdb_test "print cd" "\\$\[0-9\].* = 3" +gdb_test "print C::D::cd" "No type \"D\" in namespace \"C::C\"." +gdb_test "print 'E::cde'" "\\$\[0-9\].* = 5" +gdb_test "print E::cde" "\\$\[0-9\].* = 5" +gdb_test "print shadow" "\\$\[0-9\].* = 13" +gdb_test "print E::ce" "No symbol \"ce\" in namespace \"C::D::E\"." +gdb_test "print cOtherFile" "\\$\[0-9\].* = 316" +gdb_test "ptype C" "type = namespace C::C" +gdb_test "ptype E" "type = namespace C::D::E" + +# Some anonymous namespace tests. + +gdb_test "print cX" "\\$\[0-9\].* = 6" +gdb_test "print 'F::cXf'" "\\$\[0-9\].* = 7" +gdb_test "print F::cXf" "\\$\[0-9\].* = 7" +gdb_test "print F::cXfX" "\\$\[0-9\].* = 8" +gdb_test "print X" "\\$\[0-9\].* = 9" +gdb_test "print 'G::Xg'" "\\$\[0-9\].* = 10" +gdb_test "print G::Xg" "\\$\[0-9\].* = 10" +gdb_test "print G::XgX" "\\$\[0-9\].* = 11" +gdb_test "print cXOtherFile" "No symbol \"cXOtherFile\" in current context." +gdb_test "print XOtherFile" "No symbol \"XOtherFile\" in current context." diff --git a/gdb/testsuite/gdb.cp/namespace1.cc b/gdb/testsuite/gdb.cp/namespace1.cc new file mode 100644 index 0000000..4a5900a --- /dev/null +++ b/gdb/testsuite/gdb.cp/namespace1.cc @@ -0,0 +1,31 @@ +/* Copyright 2003 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + + Please email any bugs, comments, and/or additions to this file to: + bug-gdb@prep.ai.mit.edu */ + +namespace C +{ + namespace { + int cXOtherFile = 29; + }; + + int cOtherFile = 316; +} + +namespace { + int XOtherFile = 317; +} diff --git a/gdb/testsuite/gdb.cp/overload.cc b/gdb/testsuite/gdb.cp/overload.cc new file mode 100644 index 0000000..56afc96 --- /dev/null +++ b/gdb/testsuite/gdb.cp/overload.cc @@ -0,0 +1,168 @@ +#include + +class foo { +public: + foo (int); + foo (int, const char *); + foo (foo&); + ~foo (); + void foofunc (int); + void foofunc (int, signed char *); + int ifoo; + const char *ccpfoo; + +int overload1arg (void); +int overload1arg (char); +int overload1arg (signed char); +int overload1arg (unsigned char); +int overload1arg (short); +int overload1arg (unsigned short); +int overload1arg (int); +int overload1arg (unsigned int); +int overload1arg (long); +int overload1arg (unsigned long); +int overload1arg (float); +int overload1arg (double); + +int overloadfnarg (void); +int overloadfnarg (int); +int overloadfnarg (int, int (*) (int)); + +int overloadargs (int a1); +int overloadargs (int a1, int a2); +int overloadargs (int a1, int a2, int a3); +int overloadargs (int a1, int a2, int a3, int a4); +int overloadargs (int a1, int a2, int a3, int a4, int a5); +int overloadargs (int a1, int a2, int a3, int a4, int a5, int a6); +int overloadargs (int a1, int a2, int a3, int a4, int a5, int a6, int a7); +int overloadargs (int a1, int a2, int a3, int a4, int a5, int a6, int a7, int a8); +int overloadargs (int a1, int a2, int a3, int a4, int a5, int a6, int a7, int a8, int a9); +int overloadargs (int a1, int a2, int a3, int a4, int a5, int a6, int a7, + int a8, int a9, int a10); +int overloadargs (int a1, int a2, int a3, int a4, int a5, int a6, int a7, + int a8, int a9, int a10, int a11); + + +}; + +int intToChar (char c) +{ + return 297; +} + +void marker1() +{} + +int main () +{ + char arg2 = 2; + signed char arg3 =3; + unsigned char arg4 =4; + short arg5 =5; + unsigned short arg6 =6; + int arg7 =7; + unsigned int arg8 =8; + long arg9 =9; + unsigned long arg10 =10; + float arg11 =100.0; + double arg12 = 200.0; + + char *str = (char *) "A"; + foo foo_instance1(111); + foo foo_instance2(222, str); + foo foo_instance3(foo_instance2); + + #ifdef usestubs + set_debug_traps(); + breakpoint(); + #endif + + // Verify that intToChar should work: + intToChar(1); + + marker1(); // marker1-returns-here + return 0; // marker1-returns-here +} + +foo::foo (int i) { ifoo = i; ccpfoo = NULL; } +foo::foo (int i, const char *ccp) { ifoo = i; ccpfoo = ccp; } +foo::foo (foo& afoo) { ifoo = afoo.ifoo; ccpfoo = afoo.ccpfoo;} +foo::~foo () {} + + +/* Some functions to test overloading by varying one argument type. */ + +int foo::overload1arg (void) { return 1; } +int foo::overload1arg (char arg) { arg = 0; return 2;} +int foo::overload1arg (signed char arg) { arg = 0; return 3;} +int foo::overload1arg (unsigned char arg) { arg = 0; return 4;} +int foo::overload1arg (short arg) { arg = 0; return 5;} +int foo::overload1arg (unsigned short arg) { arg = 0; return 6;} +int foo::overload1arg (int arg) { arg = 0; return 7;} +int foo::overload1arg (unsigned int arg) { arg = 0; return 8;} +int foo::overload1arg (long arg) { arg = 0; return 9;} +int foo::overload1arg (unsigned long arg) { arg = 0; return 10;} +int foo::overload1arg (float arg) { arg = 0; return 11;} +int foo::overload1arg (double arg) { arg = 0; return 12;} + +/* Test to see that we can explicitly request overloaded functions + with function pointers in the prototype. */ + +int foo::overloadfnarg (void) { return ifoo * 20; } +int foo::overloadfnarg (int arg) { arg = 0; return 13;} +int foo::overloadfnarg (int arg, int (*foo) (int)) { return foo(arg); } + +/* Some functions to test overloading by varying argument count. */ + +int foo::overloadargs (int a1) +{ a1 = 0; +return 1;} + +int foo::overloadargs (int a1, int a2) +{ a1 = a2 = 0; +return 2;} + +int foo::overloadargs (int a1, int a2, int a3) +{ a1 = a2 = a3 = 0; +return 3;} + +int foo::overloadargs (int a1, int a2, int a3, int a4) +{ a1 = a2 = a3 = a4 = 0; +return 4;} + +int foo::overloadargs (int a1, int a2, int a3, int a4, int a5) +{ a1 = a2 = a3 = a4 = a5 = 0; +return 5;} + +int foo::overloadargs (int a1, int a2, int a3, int a4, int a5, int a6) +{ a1 = a2 = a3 = a4 = a5 = a6 = 0; +return 6;} + +int foo::overloadargs (int a1, int a2, int a3, int a4, int a5, int a6, int a7) +{ a1 = a2 = a3 = a4 = a5 = a6 = a7 = 0; +return 7;} + +int foo::overloadargs (int a1, int a2, int a3, int a4, int a5, int a6, int a7, + int a8) +{ a1 = a2 = a3 = a4 = a5 = a6 = a7 = a8 = 0; +return 8;} + +int foo::overloadargs (int a1, int a2, int a3, int a4, int a5, int a6, int a7, + int a8, int a9) +{ + a1 = a2 = a3 = a4 = a5 = a6 = a7 = a8 = a9 = 0; + return 9; +} + +int foo::overloadargs (int a1, int a2, int a3, int a4, int a5, int a6, int a7, + int a8, int a9, int a10) + { a1 = a2 = a3 = a4 = a5 = a6 = a7 = a8 = a9 = + a10 = 0; return 10;} + +int foo::overloadargs (int a1, int a2, int a3, int a4, int a5, int a6, int a7, + int a8, int a9, int a10, int a11) + { a1 = a2 = a3 = a4 = a5 = a6 = a7 = a8 = a9 = + a10 = a11 = 0; return 11;} + + + diff --git a/gdb/testsuite/gdb.cp/overload.exp b/gdb/testsuite/gdb.cp/overload.exp new file mode 100644 index 0000000..3e14678 --- /dev/null +++ b/gdb/testsuite/gdb.cp/overload.exp @@ -0,0 +1,400 @@ +# Copyright 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# Please email any bugs, comments, and/or additions to this file to: +# bug-gdb@prep.ai.mit.edu + +# written by Elena Zannoni (ezannoni@cygnus.com) + +# This file is part of the gdb testsuite +# +# tests for overloaded member functions. Command Line calls +# + + +if $tracelevel then { + strace $tracelevel + } + +# +# test running programs +# +set prms_id 0 +set bug_id 0 + +if { [skip_cplus_tests] } { continue } + +set testfile "overload" +set srcfile ${testfile}.cc +set binfile ${objdir}/${subdir}/${testfile} + +if { [gdb_compile "${srcdir}/${subdir}/${srcfile}" "${binfile}" executable {debug c++}] != "" } { + gdb_suppress_entire_file "Testcase compile failed, so all tests in this file will automatically fail." +} + +if [get_compiler_info ${binfile} "c++"] { + return -1 +} + +gdb_exit +gdb_start +gdb_reinitialize_dir $srcdir/$subdir +gdb_load ${binfile} + +# set it up at a breakpoint so we can play with the variable values +# +if ![runto_main] then { + perror "couldn't run to breakpoint" + continue +} + +if ![runto 'marker1'] then { + perror "couldn't run to marker1" + continue +} + +gdb_test "up" ".*main.*" "up from marker1" + +send_gdb "print foo_instance1\n" +gdb_expect { + -re ".\[0-9\]* = \{ifoo = 111, ccpfoo = 0x0\}\r\n$gdb_prompt $" { + pass "print foo_instance1" + } + -re ".*$gdb_prompt $" { fail "print foo_instance1" } + timeout { fail "(timeout) print foo_instance1" } + } + + +setup_xfail "hppa*-*-*" CLLbs16901 +send_gdb "ptype foo_instance1\n" +gdb_expect { + -re "type = class foo \{.*public:.*int ifoo;.*const char \\*ccpfoo;.*foo\\(int\\);.*foo\\(int, (const char|char const) \\*\\);.*foo\\(foo &\\);.*~foo\\(void\\);.*void foofunc\\(int\\);.*void foofunc\\(int, signed char \\*\\);.*int overload1arg\\(void\\);.*int overload1arg\\(char\\);.*int overload1arg\\(signed char\\);.*int overload1arg\\(unsigned char\\);.*int overload1arg\\(short\\);.*int overload1arg\\(unsigned short\\);.*int overload1arg\\(int\\);.*int overload1arg\\(unsigned int\\);.*int overload1arg\\(long\\);.*int overload1arg\\(unsigned long\\);.*int overload1arg\\(float\\);.*int overload1arg\\(double\\);.*int overloadargs\\(int\\);.*int overloadargs\\(int, int\\);.*int overloadargs\\(int, int, int\\);.*int overloadargs\\(int, int, int, int\\);.*int overloadargs\\(int, int, int, int, int\\);.*int overloadargs\\(int, int, int, int, int, int\\);.*int overloadargs\\(int, int, int, int, int, int, int\\);.*int overloadargs\\(int, int, int, int, int, int, int, int\\);.*int overloadargs\\(int, int, int, int, int, int, int, int, int\\);.*int overloadargs\\(int, int, int, int, int, int, int, int, int, int\\);.*int overloadargs\\(int, int, int, int, int, int, int, int, int, int, int\\);\r\n\}\r\n$gdb_prompt $" { + pass "ptype foo_instance1 (HP aCC -- known quirk with ~foo parameter list)" + } + -re "type = class foo .*int overloadargs\\(int, int, int, int, int, int, int, int, int, int, int\\);\r\n\}\r\n$gdb_prompt $" { + pass "ptype foo_instance1 (shorter match)" + } + -re ".*$gdb_prompt $" { fail "ptype foo_instance1" } + timeout { fail "(timeout) ptype foo_instance1" } + } + +send_gdb "print foo_instance2\n" +gdb_expect { + -re ".\[0-9\]* = \{ifoo = 222, ccpfoo = $hex \"A\"\}\r\n$gdb_prompt $" { + pass "print foo_instance2" + } + -re ".*$gdb_prompt $" { fail "print foo_instance2" } + timeout { fail "(timeout) print foo_instance2" } + } + +send_gdb "print foo_instance3\n" +gdb_expect { + -re ".\[0-9\]* = \{ifoo = 222, ccpfoo = $hex \"A\"\}\r\n$gdb_prompt $" { + pass "print foo_instance3" + } + -re ".*$gdb_prompt $" { fail "print foo_instance3" } + timeout { fail "(timeout) print foo_instance3" } + } + + +send_gdb "print foo_instance1.overloadargs(1)\n" +gdb_expect { + -re ".\[0-9\]* = 1\r\n$gdb_prompt $" { + pass "print call overloaded func 1 arg" + } + -re ".*$gdb_prompt $" { fail "print call overloaded func 1 arg" } + timeout { fail "(timeout) print call overloaded func 1 arg" } + } + + +# If GDB fails to restore the selected frame properly after the +# inferior function call above (see GDB PR 1155 for an explanation of +# why this might happen), all the subsequent tests will fail. We +# should detect and report that failure, but let the marker call +# finish so that the rest of the tests can run undisturbed. +gdb_test_multiple "frame" "re-selected 'main' frame after inferior call" { + -re "#0 marker1.*$gdb_prompt $" { + setup_kfail "gdb/1155" s390-*-linux-gnu + fail "re-selected 'main' frame after inferior call" + gdb_test "finish" ".*main.*at .*overload.cc:.*// marker1-returns-here.*" \ + "finish call to marker1" + } + -re "#1 ($hex in )?main.*$gdb_prompt $" { + pass "re-selected 'main' frame after inferior call" + } +} + + +send_gdb "print foo_instance1.overloadargs(1, 2)\n" +gdb_expect { + -re ".\[0-9\]* = 2\r\n$gdb_prompt $" { + pass "print call overloaded func 2 args" + } + -re ".*$gdb_prompt $" { fail "print call overloaded func 2 args" } + timeout { fail "(timeout) print call overloaded func 2 args" } + } + + +send_gdb "print foo_instance1.overloadargs(1, 2, 3)\n" +gdb_expect { + -re ".\[0-9\]* = 3\r\n$gdb_prompt $" { + pass "print call overloaded func 3 args" + } + -re ".*$gdb_prompt $" { fail "print call overloaded func 3 args" } + timeout { fail "(timeout) print call overloaded func 3 args" } + } + + +send_gdb "print foo_instance1.overloadargs(1, 2, 3, 4)\n" +gdb_expect { + -re ".\[0-9\]* = 4\r\n$gdb_prompt $" { + pass "print call overloaded func 4 args" + } + -re ".*$gdb_prompt $" { fail "print call overloaded func 4 args" } + timeout { fail "(timeout) print call overloaded func 4 args" } + } + + +send_gdb "print foo_instance1.overloadargs(1, 2, 3, 4, 5)\n" +gdb_expect { + -re ".\[0-9\]* = 5\r\n$gdb_prompt $" { + pass "print call overloaded func 5 args" + } + -re ".*$gdb_prompt $" { fail "print call overloaded func 5 args" } + timeout { fail "(timeout) print call overloaded func 5 args" } + } + + +send_gdb "print foo_instance1.overloadargs(1, 2, 3, 4, 5, 6)\n" +gdb_expect { + -re ".\[0-9\]* = 6\r\n$gdb_prompt $" { + pass "print call overloaded func 6 args" + } + -re ".*$gdb_prompt $" { fail "print call overloaded func 6 args" } + timeout { fail "(timeout) print call overloaded func 6 args" } + } + + +send_gdb "print foo_instance1.overloadargs(1, 2, 3, 4, 5, 6, 7)\n" +gdb_expect { + -re ".\[0-9\]* = 7\r\n$gdb_prompt $" { + pass "print call overloaded func 7 args" + } + -re ".*$gdb_prompt $" { fail "print call overloaded func 7 args" } + timeout { fail "(timeout) print call overloaded func 7 args" } + } + + +send_gdb "print foo_instance1.overloadargs(1, 2, 3, 4, 5, 6, 7, 8)\n" +gdb_expect { + -re ".\[0-9\]* = 8\r\n$gdb_prompt $" { + pass "print call overloaded func 8 args" + } + -re ".*$gdb_prompt $" { fail "print call overloaded func 8 args" } + timeout { fail "(timeout) print call overloaded func 8 args" } + } + + +send_gdb "print foo_instance1.overloadargs(1, 2, 3, 4, 5, 6, 7, 8, 9)\n" +gdb_expect { + -re ".\[0-9\]* = 9\r\n$gdb_prompt $" { + pass "print call overloaded func 9 args" + } + -re ".*$gdb_prompt $" { fail "print call overloaded func 9 args" } + timeout { fail "(timeout) print call overloaded func 9 args" } + } + + +send_gdb "print foo_instance1.overloadargs(1, 2, 3, 4, 5, 6, 7, 8, 9, 10)\n" +gdb_expect { + -re ".\[0-9\]* = 10\r\n$gdb_prompt $" { + pass "print call overloaded func 10 args" + } + -re ".*$gdb_prompt $" { fail "print call overloaded func 10 args" } + timeout { fail "(timeout) print call overloaded func 10 args" } + } + + +send_gdb "print foo_instance1.overloadargs(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11)\n" +gdb_expect { + -re ".\[0-9\]* = 11\r\n$gdb_prompt $" { + pass "print call overloaded func 11 args" + } + -re ".*$gdb_prompt $" { fail "print call overloaded func 11 args" } + timeout { fail "(timeout) print call overloaded func 11 args" } + } + + +send_gdb "print foo_instance1.overload1arg()\n" +gdb_expect { + -re ".\[0-9\]* = 1\r\n$gdb_prompt $" { + pass "print call overloaded func void arg" + } + -re ".*$gdb_prompt $" { fail "print call overloaded func void arg" } + timeout { fail "(timeout) print call overloaded func void arg" } + } + + +send_gdb "print foo_instance1.overload1arg((char)arg2)\n" +gdb_expect { + -re ".\[0-9\]* = 2\r\n$gdb_prompt $" { + pass "print call overloaded func char arg" + } + -re ".*$gdb_prompt $" { fail "print call overloaded func char arg" } + timeout { fail "(timeout) print call overloaded func char arg" } + } + + +send_gdb "print foo_instance1.overload1arg((signed char)arg3)\n" +gdb_expect { + -re ".\[0-9\]* = 3\r\n$gdb_prompt $" { + pass "print call overloaded func signed char arg" + } + -re ".*$gdb_prompt $" { fail "print call overloaded func signed char arg" } + timeout { fail "(timeout) print call overloaded func signed char arg" } + } + + +send_gdb "print foo_instance1.overload1arg((unsigned char)arg4)\n" +gdb_expect { + -re ".\[0-9\]* = 4\r\n$gdb_prompt $" { + pass "print call overloaded func unsigned char arg" + } + -re ".*$gdb_prompt $" { fail "print call overloaded func unsigned char arg" } + timeout { fail "(timeout) print call overloaded func unsigned char arg" } + } + + +send_gdb "print foo_instance1.overload1arg((short)arg5)\n" +gdb_expect { + -re ".\[0-9\]* = 5\r\n$gdb_prompt $" { + pass "print call overloaded func short arg" + } + -re ".*$gdb_prompt $" { fail "print call overloaded func short arg" } + timeout { fail "(timeout) print call overloaded func short arg" } + } + + +send_gdb "print foo_instance1.overload1arg((unsigned short)arg6)\n" +gdb_expect { + -re ".\[0-9\]* = 6\r\n$gdb_prompt $" { + pass "print call overloaded func unsigned short arg" + } + -re ".*$gdb_prompt $" { fail "print call overloaded func unsigned short arg" } + timeout { fail "(timeout) print call overloaded func unsigned short arg" } + } + + +send_gdb "print foo_instance1.overload1arg((int)arg7)\n" +gdb_expect { + -re ".\[0-9\]* = 7\r\n$gdb_prompt $" { + pass "print call overloaded func int arg" + } + -re ".*$gdb_prompt $" { fail "print call overloaded func int arg" } + timeout { fail "(timeout) print call overloaded func int arg" } + } + + +send_gdb "print foo_instance1.overload1arg((unsigned int)arg8)\n" +gdb_expect { + -re ".\[0-9\]* = 8\r\n$gdb_prompt $" { + pass "print call overloaded func unsigned int arg" + } + -re ".*$gdb_prompt $" { fail "print call overloaded func unsigned int arg" } + timeout { fail "(timeout) print call overloaded func unsigned int arg" } + } + + +send_gdb "print foo_instance1.overload1arg((long)arg9)\n" +gdb_expect { + -re ".\[0-9\]* = 9\r\n$gdb_prompt $" { + pass "print call overloaded func long arg" + } + -re ".*$gdb_prompt $" { fail "print call overloaded func long arg" } + timeout { fail "(timeout) print call overloaded func long arg" } + } + + +send_gdb "print foo_instance1.overload1arg((unsigned long)arg10)\n" +gdb_expect { + -re ".\[0-9\]* = 10\r\n$gdb_prompt $" { + pass "print call overloaded func unsigned long arg" + } + -re ".*$gdb_prompt $" { fail "print call overloaded func unsigned long arg" } + timeout { fail "(timeout) print call overloaded func unsigned long arg" } + } + + +send_gdb "print foo_instance1.overload1arg((float)arg11)\n" +gdb_expect { + -re ".\[0-9\]* = 11\r\n$gdb_prompt $" { + pass "print call overloaded func float arg" + } + -re ".*$gdb_prompt $" { fail "print call overloaded func float arg" } + timeout { fail "(timeout) print call overloaded func float arg" } + } + + +send_gdb "print foo_instance1.overload1arg((double)arg12)\n" +gdb_expect { + -re ".\[0-9\]* = 12\r\n$gdb_prompt $" { + pass "print call overloaded func double arg" + } + -re ".*$gdb_prompt $" { fail "print call overloaded func double arg" } + timeout { fail "(timeout) print call overloaded func double arg" } + } + +# Now some tests to see if we can list overloaded functions properly: + +gdb_test "set listsize 1" "" "" +# send_gdb "set listsize 1\n" +# gdb_expect -re ".*$gdb_prompt $" + +# +# Decide whether to use "()" or "(void)" +# + +send_gdb "info func overloadfnarg\n" +gdb_expect { + -re ".*overloadfnarg\\(void\\).*$gdb_prompt $" { + gdb_test "list foo::overloadfnarg(void)"\ + ".*int foo::overloadfnarg.*\\(void\\).*" \ + "list overloaded function with no args" + } + -re ".*overloadfnarg\\(\\).*$gdb_prompt $" { + gdb_test "list foo::overloadfnarg()"\ + ".*int foo::overloadfnarg.*\\(void\\).*" \ + "list overloaded function with no args" + } + -re ".*$gdb_prompt $" { + fail "list overloaded function with no args (no matching symbol)" + } +} + +gdb_test "list foo::overloadfnarg(int)"\ + "int foo::overloadfnarg.*\\(int arg\\).*" \ + "list overloaded function with int arg" + +gdb_test "list foo::overloadfnarg(int, int (*)(int))" \ + "int foo::overloadfnarg.*\\(int arg, int \\(\\*foo\\) \\(int\\)\\).*" \ + "list overloaded function with function ptr args" + +# This one crashes GDB. Don't know why yet. +gdb_test "list \"foo::overloadfnarg(int, int (*)(int))\"" \ + "int foo::overloadfnarg.*\\(int arg, int \\(\\*foo\\) \\(int\\)\\).*" \ + "list overloaded function with function ptr args - quotes around argument" + +gdb_test "print intToChar(1)" ".\[0-9\]* = 297" diff --git a/gdb/testsuite/gdb.cp/ovldbreak.cc b/gdb/testsuite/gdb.cp/ovldbreak.cc new file mode 100644 index 0000000..9a5b5cb --- /dev/null +++ b/gdb/testsuite/gdb.cp/ovldbreak.cc @@ -0,0 +1,177 @@ +#include + +class foo { +public: + foo (int); + foo (int, const char *); + foo (foo&); + ~foo (); + void foofunc (int); + void foofunc (int, signed char *); + int ifoo; + const char *ccpfoo; + +int overload1arg (void); +int overload1arg (char); +int overload1arg (signed char); +int overload1arg (unsigned char); +int overload1arg (short); +int overload1arg (unsigned short); +int overload1arg (int); +int overload1arg (unsigned int); +int overload1arg (long); +int overload1arg (unsigned long); +int overload1arg (float); +int overload1arg (double); + +int overloadargs (int a1); +int overloadargs (int a1, int a2); +int overloadargs (int a1, int a2, int a3); +int overloadargs (int a1, int a2, int a3, int a4); +int overloadargs (int a1, int a2, int a3, int a4, int a5); +int overloadargs (int a1, int a2, int a3, int a4, int a5, int a6); +int overloadargs (int a1, int a2, int a3, int a4, int a5, int a6, int a7); +int overloadargs (int a1, int a2, int a3, int a4, int a5, int a6, int a7, int a8); +int overloadargs (int a1, int a2, int a3, int a4, int a5, int a6, int a7, int a8, int a9); +int overloadargs (int a1, int a2, int a3, int a4, int a5, int a6, int a7, + int a8, int a9, int a10); +int overloadargs (int a1, int a2, int a3, int a4, int a5, int a6, int a7, + int a8, int a9, int a10, int a11); + + +}; + +void marker1() +{} + +int main () +{ + char arg2 = 2; + signed char arg3 =3; + unsigned char arg4 =4; + short arg5 =5; + unsigned short arg6 =6; + int arg7 =7; + unsigned int arg8 =8; + long arg9 =9; + unsigned long arg10 =10; + float arg11 =100.0; + double arg12 = 200.0; + + char ch='A'; + foo foo_instance1(111); + foo foo_instance2(222, &ch); + foo foo_instance3(foo_instance2); + + foo_instance1.overload1arg(); + foo_instance1.overload1arg(arg2); + foo_instance1.overload1arg(arg3); + foo_instance1.overload1arg(arg4); + foo_instance1.overload1arg(arg5); + foo_instance1.overload1arg(arg6); + foo_instance1.overload1arg(arg7); + foo_instance1.overload1arg(arg8); + foo_instance1.overload1arg(arg9); + foo_instance1.overload1arg(arg10); + foo_instance1.overload1arg(arg11); + foo_instance1.overload1arg(arg12); + + foo_instance1.overloadargs(1); + foo_instance1.overloadargs(1, 2); + foo_instance1.overloadargs(1, 2, 3); + foo_instance1.overloadargs(1, 2, 3, 4); + foo_instance1.overloadargs(1, 2, 3, 4, 5); + foo_instance1.overloadargs(1, 2, 3, 4, 5, 6); + foo_instance1.overloadargs(1, 2, 3, 4, 5, 6, 7); + foo_instance1.overloadargs(1, 2, 3, 4, 5, 6, 7, 8); + foo_instance1.overloadargs(1, 2, 3, 4, 5, 6, 7, 8, 9); + foo_instance1.overloadargs(1, 2, 3, 4, 5, 6, 7, 8, 9, 10); + foo_instance1.overloadargs(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11); + + + #ifdef usestubs + set_debug_traps(); + breakpoint(); + #endif + + + marker1(); + return 0; +} + +foo::foo (int i) { ifoo = i;} +foo::foo (int i, const char *ccp) { ifoo = i; ccpfoo = ccp; } +foo::foo (foo& afoo) { ifoo = afoo.ifoo; ccpfoo = afoo.ccpfoo;} +foo::~foo () {} + + +/* Some functions to test overloading by varying one argument type. */ + +int foo::overload1arg (void) { return 1; } +int foo::overload1arg (char arg) { arg = 0; return 2;} +int foo::overload1arg (signed char arg) { arg = 0; return 3;} +int foo::overload1arg (unsigned char arg) { arg = 0; return 4;} +int foo::overload1arg (short arg) { arg = 0; return 5;} +int foo::overload1arg (unsigned short arg) { arg = 0; return 6;} +int foo::overload1arg (int arg) { arg = 0; return 7;} +int foo::overload1arg (unsigned int arg) { arg = 0; return 8;} +int foo::overload1arg (long arg) { arg = 0; return 9;} +int foo::overload1arg (unsigned long arg) { arg = 0; return 10;} +int foo::overload1arg (float arg) { arg = 0; return 11;} +int foo::overload1arg (double arg) { arg = 0; return 12;} + + +/* Some functions to test overloading by varying argument count. */ + +int foo::overloadargs (int a1) +{ a1 = 0; +return 1;} + +int foo::overloadargs (int a1, int a2) +{ a1 = a2 = 0; +return 2;} + +int foo::overloadargs (int a1, int a2, int a3) +{ a1 = a2 = a3 = 0; +return 3;} + +int foo::overloadargs (int a1, int a2, int a3, int a4) +{ a1 = a2 = a3 = a4 = 0; +return 4;} + +int foo::overloadargs (int a1, int a2, int a3, int a4, int a5) +{ a1 = a2 = a3 = a4 = a5 = 0; +return 5;} + +int foo::overloadargs (int a1, int a2, int a3, int a4, int a5, int a6) +{ a1 = a2 = a3 = a4 = a5 = a6 = 0; +return 6;} + +int foo::overloadargs (int a1, int a2, int a3, int a4, int a5, int a6, int a7) +{ a1 = a2 = a3 = a4 = a5 = a6 = a7 = 0; +return 7;} + +int foo::overloadargs (int a1, int a2, int a3, int a4, int a5, int a6, int a7, + int a8) +{ a1 = a2 = a3 = a4 = a5 = a6 = a7 = a8 = 0; +return 8;} + +int foo::overloadargs (int a1, int a2, int a3, int a4, int a5, int a6, int a7, + int a8, int a9) +{ + a1 = a2 = a3 = a4 = a5 = a6 = a7 = a8 = a9 = 0; + return 9; +} + +int foo::overloadargs (int a1, int a2, int a3, int a4, int a5, int a6, int a7, + int a8, int a9, int a10) + { a1 = a2 = a3 = a4 = a5 = a6 = a7 = a8 = a9 = + a10 = 0; return 10;} + +int foo::overloadargs (int a1, int a2, int a3, int a4, int a5, int a6, int a7, + int a8, int a9, int a10, int a11) + { a1 = a2 = a3 = a4 = a5 = a6 = a7 = a8 = a9 = + a10 = a11 = 0; return 11;} + + + diff --git a/gdb/testsuite/gdb.cp/ovldbreak.exp b/gdb/testsuite/gdb.cp/ovldbreak.exp new file mode 100644 index 0000000..043243d --- /dev/null +++ b/gdb/testsuite/gdb.cp/ovldbreak.exp @@ -0,0 +1,360 @@ +# Copyright (C) 1998, 1999, 2001 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# Please email any bugs, comments, and/or additions to this file to: +# bug-gdb@prep.ai.mit.edu + +# written by Elena Zannoni (ezannoni@cygnus.com) +# modified by Michael Chastain (chastain@redhat.com) + +# This file is part of the gdb testsuite +# +# tests for overloaded member functions. Set breakpoints on +# overloaded member functions +# + + +if $tracelevel then { + strace $tracelevel + } + +# +# test running programs +# +set prms_id 0 +set bug_id 0 + +if { [skip_cplus_tests] } { continue } + +set testfile "ovldbreak" +set srcfile ${testfile}.cc +set binfile ${objdir}/${subdir}/${testfile} + +if { [gdb_compile "${srcdir}/${subdir}/${srcfile}" "${binfile}" executable {debug c++}] != "" } { + gdb_suppress_entire_file "Testcase compile failed, so all tests in this file will automatically fail." +} + +gdb_exit +gdb_start +gdb_reinitialize_dir $srcdir/$subdir +gdb_load ${binfile} + +# set it up at a breakpoint so we can play with the variable values +# +if ![runto_main] then { + perror "couldn't run to breakpoint" + continue +} + + + +# When I ask gdb to set a breakpoint on an overloaded function, +# gdb gives me a choice menu. I might get stuck in that choice menu +# (for example, if C++ name mangling is not working properly). +# +# This procedure issues a command that works at either the menu +# prompt or the command prompt to get back to the command prompt. +# +# Note that an empty line won't do it (it means 'repeat the previous command' +# at top level). A line with a single space in it works nicely. + +proc take_gdb_out_of_choice_menu {} { + global gdb_prompt + send_gdb " \n" + gdb_expect { + -re ".*$gdb_prompt $" { + } + timeout { + perror "could not resynchronize to command prompt (timeout)" + continue + } + } +} + + + +# This procedure sets an overloaded breakpoint. +# When I ask for such a breakpoint, gdb gives me a menu of 'cancel' 'all' +# and a bunch of choices. I then choose from that menu by number. + +proc set_bp_overloaded {name expectedmenu mychoice bpnumber linenumber} { + global gdb_prompt hex srcfile + + # Get into the overload menu. + send_gdb "break $name\n" + gdb_expect { + -re "$expectedmenu" { + pass "bp menu for $name choice $mychoice" + + # Choose my choice. + send_gdb "$mychoice\n" + gdb_expect { + -re "Breakpoint $bpnumber at $hex: file.*$srcfile, line $linenumber.\r\n$gdb_prompt $" { + pass "set bp $bpnumber on $name $mychoice line $linenumber" + } + -re ".*$gdb_prompt $" { + fail "set bp $bpnumber on $name $mychoice line $linenumber (bad bp)" + } + timeout { + fail "set bp $bpnumber on $name $mychoice line $linenumber (timeout)" + take_gdb_out_of_choice_menu + } + } + } + -re ".*\r\n> " { + fail "bp menu for $name choice $mychoice (bad menu)" + take_gdb_out_of_choice_menu + } + -re ".*$gdb_prompt $" { + fail "bp menu for $name choice $mychoice (no menu)" + } + timeout { + fail "bp menu for $name choice $mychoice (timeout)" + take_gdb_out_of_choice_menu + } + } +} + +# This is the expected menu for overload1arg. +# Note the arg type variations on lines 6 and 13. +# This accommodates different versions of g++. + +set menu_overload1arg "\\\[0\\\] cancel\r\n\\\[1\\\] all\r\n\\\[2\\\] foo::overload1arg\\(double\\) at.*$srcfile:121\r\n\\\[3\\\] foo::overload1arg\\(float\\) at.*$srcfile:120\r\n\\\[4\\\] foo::overload1arg\\(unsigned long\\) at.*$srcfile:119\r\n\\\[5\\\] foo::overload1arg\\(long\\) at.*$srcfile:118\r\n\\\[6\\\] foo::overload1arg\\((unsigned int|unsigned)\\) at.*$srcfile:117\r\n\\\[7\\\] foo::overload1arg\\(int\\) at.*$srcfile:116\r\n\\\[8\\\] foo::overload1arg\\(unsigned short\\) at.*$srcfile:115\r\n\\\[9\\\] foo::overload1arg\\(short\\) at.*$srcfile:114\r\n\\\[10\\\] foo::overload1arg\\(unsigned char\\) at.*$srcfile:113\r\n\\\[11\\\] foo::overload1arg\\(signed char\\) at.*$srcfile:112\r\n\\\[12\\\] foo::overload1arg\\(char\\) at.*$srcfile:111\r\n\\\[13\\\] foo::overload1arg\\((void|)\\) at.*$srcfile:110\r\n> $" + + + +# Set breakpoints on foo::overload1arg, one by one. + +set_bp_overloaded "foo::overload1arg" "$menu_overload1arg" 12 2 111 +set_bp_overloaded "foo::overload1arg" "$menu_overload1arg" 11 3 112 +set_bp_overloaded "foo::overload1arg" "$menu_overload1arg" 10 4 113 +set_bp_overloaded "foo::overload1arg" "$menu_overload1arg" 9 5 114 +set_bp_overloaded "foo::overload1arg" "$menu_overload1arg" 8 6 115 +set_bp_overloaded "foo::overload1arg" "$menu_overload1arg" 7 7 116 +set_bp_overloaded "foo::overload1arg" "$menu_overload1arg" 6 8 117 +set_bp_overloaded "foo::overload1arg" "$menu_overload1arg" 5 9 118 +set_bp_overloaded "foo::overload1arg" "$menu_overload1arg" 4 10 119 +set_bp_overloaded "foo::overload1arg" "$menu_overload1arg" 3 11 120 +set_bp_overloaded "foo::overload1arg" "$menu_overload1arg" 2 12 121 +set_bp_overloaded "foo::overload1arg" "$menu_overload1arg" 13 13 110 + + + +# Verify the breakpoints. + +gdb_test "info break" \ + "Num Type\[\t \]+Disp Enb Address\[\t \]+What.* +\[0-9\]+\[\t \]+breakpoint keep y\[\t \]+$hex\[\t \]+in main at.*$srcfile:49\r +\[\t \]+breakpoint already hit 1 time\r +\[0-9\]+\[\t \]+breakpoint keep y\[\t \]+$hex\[\t \]+in foo::overload1arg\\(char\\) at.*$srcfile:111\r +\[0-9\]+\[\t \]+breakpoint keep y\[\t \]+$hex\[\t \]+in foo::overload1arg\\(signed char\\) at.*$srcfile:112\r +\[0-9\]+\[\t \]+breakpoint keep y\[\t \]+$hex\[\t \]+in foo::overload1arg\\(unsigned char\\) at.*$srcfile:113\r +\[0-9\]+\[\t \]+breakpoint keep y\[\t \]+$hex\[\t \]+in foo::overload1arg\\(short\\) at.*$srcfile:114\r +\[0-9\]+\[\t \]+breakpoint keep y\[\t \]+$hex\[\t \]+in foo::overload1arg\\(unsigned short\\) at.*$srcfile:115\r +\[0-9\]+\[\t \]+breakpoint keep y\[\t \]+$hex\[\t \]+in foo::overload1arg\\(int\\) at.*$srcfile:116\r +\[0-9\]+\[\t \]+breakpoint keep y\[\t \]+$hex\[\t \]+in foo::overload1arg\\((unsigned|unsigned int)\\) at.*$srcfile:117\r +\[0-9\]+\[\t \]+breakpoint keep y\[\t \]+$hex\[\t \]+in foo::overload1arg\\(long\\) at.*$srcfile:118\r +\[0-9\]+\[\t \]+breakpoint keep y\[\t \]+$hex\[\t \]+in foo::overload1arg\\(unsigned long\\) at.*$srcfile:119\r +\[0-9\]+\[\t \]+breakpoint keep y\[\t \]+$hex\[\t \]+in foo::overload1arg\\(float\\) at.*$srcfile:120\r +\[0-9\]+\[\t \]+breakpoint keep y\[\t \]+$hex\[\t \]+in foo::overload1arg\\(double\\) at.*$srcfile:121\r +\[0-9\]+\[\t \]+breakpoint keep y\[\t \]+$hex\[\t \]+in foo::overload1arg\\((void|)\\) at.*$srcfile:110" \ + "breakpoint info (after setting one-by-one)" + + + +# Test choice "cancel". +# This is copy-and-paste from set_bp_overloaded. + +send_gdb "break foo::overload1arg\n" +gdb_expect { + -re "$menu_overload1arg" { + pass "bp menu for foo::overload1arg choice cancel" + # Choose cancel. + send_gdb "0\n" + gdb_expect { + -re "canceled\r\n$gdb_prompt $" { + pass "set bp on overload1arg canceled" + } + -re "cancelled\r\n$gdb_prompt $" { + pass "set bp on overload1arg canceled" + } + -re ".*$gdb_prompt $" { + fail "set bp on overload1arg canceled (bad message)" + } + timeout { + fail "set bp on overload1arg canceled (timeout)" + take_gdb_out_of_choice_menu + } + } + } + -re ".*\r\n> " { + fail "bp menu for foo::overload1arg choice cancel (bad menu)" + take_gdb_out_of_choice_menu + } + -re ".*$gdb_prompt $" { + fail "bp menu for foo::overload1arg choice cancel (no menu)" + } + timeout { + fail "bp menu for foo::overload1arg choice cancel (timeout)" + take_gdb_out_of_choice_menu + } +} + +gdb_test "info break" \ + "Num Type\[\t \]+Disp Enb Address\[\t \]+What.* +\[0-9\]+\[\t \]+breakpoint keep y\[\t \]+$hex\[\t \]+in main at.*$srcfile:49\r +\[\t \]+breakpoint already hit 1 time\r +\[0-9\]+\[\t \]+breakpoint keep y\[\t \]+$hex\[\t \]+in foo::overload1arg\\(char\\) at.*$srcfile:111\r +\[0-9\]+\[\t \]+breakpoint keep y\[\t \]+$hex\[\t \]+in foo::overload1arg\\(signed char\\) at.*$srcfile:112\r +\[0-9\]+\[\t \]+breakpoint keep y\[\t \]+$hex\[\t \]+in foo::overload1arg\\(unsigned char\\) at.*$srcfile:113\r +\[0-9\]+\[\t \]+breakpoint keep y\[\t \]+$hex\[\t \]+in foo::overload1arg\\(short\\) at.*$srcfile:114\r +\[0-9\]+\[\t \]+breakpoint keep y\[\t \]+$hex\[\t \]+in foo::overload1arg\\(unsigned short\\) at.*$srcfile:115\r +\[0-9\]+\[\t \]+breakpoint keep y\[\t \]+$hex\[\t \]+in foo::overload1arg\\(int\\) at.*$srcfile:116\r +\[0-9\]+\[\t \]+breakpoint keep y\[\t \]+$hex\[\t \]+in foo::overload1arg\\((unsigned|unsigned int)\\) at.*$srcfile:117\r +\[0-9\]+\[\t \]+breakpoint keep y\[\t \]+$hex\[\t \]+in foo::overload1arg\\(long\\) at.*$srcfile:118\r +\[0-9\]+\[\t \]+breakpoint keep y\[\t \]+$hex\[\t \]+in foo::overload1arg\\(unsigned long\\) at.*$srcfile:119\r +\[0-9\]+\[\t \]+breakpoint keep y\[\t \]+$hex\[\t \]+in foo::overload1arg\\(float\\) at.*$srcfile:120\r +\[0-9\]+\[\t \]+breakpoint keep y\[\t \]+$hex\[\t \]+in foo::overload1arg\\(double\\) at.*$srcfile:121\r +\[0-9\]+\[\t \]+breakpoint keep y\[\t \]+$hex\[\t \]+in foo::overload1arg\\((void|)\\) at.*$srcfile:110" \ + "breakpoint info (after cancel)" + + + +# Delete these breakpoints. + +send_gdb "delete breakpoints\n" +gdb_expect { + -re "Delete all breakpoints.* $" { + send_gdb "y\n" + gdb_expect { + -re ".*$gdb_prompt $" { + pass "delete all breakpoints" + } + timeout { + fail "delete all breakpoints (timeout)" + } + } + } + timeout { + fail "delete all breakpoints (timeout)" + } +} + +gdb_test "info breakpoints" "No breakpoints or watchpoints." "breakpoint info (after delete)" + + + +# Test choice "all". +# This is copy-and-paste from set_bp_overloaded. + +send_gdb "break foo::overload1arg\n" +gdb_expect { + -re "$menu_overload1arg" { + pass "bp menu for foo::overload1arg choice all" + # Choose all. + send_gdb "1\n" + gdb_expect { + -re "Breakpoint $decimal at $hex: file.*$srcfile, line 121.\r\nBreakpoint $decimal at $hex: file.*$srcfile, line 120.\r\nBreakpoint $decimal at $hex: file.*$srcfile, line 119.\r\nBreakpoint $decimal at $hex: file.*$srcfile, line 118.\r\nBreakpoint $decimal at $hex: file.*$srcfile, line 117.\r\nBreakpoint $decimal at $hex: file.*$srcfile, line 116.\r\nBreakpoint $decimal at $hex: file.*$srcfile, line 115.\r\nBreakpoint $decimal at $hex: file.*$srcfile, line 114.\r\nBreakpoint $decimal at $hex: file.*$srcfile, line 113.\r\nBreakpoint $decimal at $hex: file.*$srcfile, line 112.\r\nBreakpoint $decimal at $hex: file.*$srcfile, line 111.\r\nBreakpoint $decimal at $hex: file.*$srcfile, line 110.\r\nwarning: Multiple breakpoints were set.\r\nwarning: Use the .delete. command to delete unwanted breakpoints.\r\n$gdb_prompt $" { + pass "set bp on overload1arg all" + } + -re ".*$gdb_prompt $" { + fail "set bp on overload1arg all (bad message)" + } + timeout { + fail "set bp on overload1arg all (timeout)" + take_gdb_out_of_choice_menu + } + } + } + -re ".*\r\n> " { + fail "bp menu for foo::overload1arg choice all (bad menu)" + take_gdb_out_of_choice_menu + } + -re ".*$gdb_prompt $" { + fail "bp menu for foo::overload1arg choice all (no menu)" + } + timeout { + fail "bp menu for foo::overload1arg choice all (timeout)" + take_gdb_out_of_choice_menu + } +} + +gdb_test "info break" \ + "Num Type\[\t \]+Disp Enb Address\[\t \]+What.* +\[0-9\]+\[\t \]+breakpoint keep y\[\t \]+$hex\[\t \]+in foo::overload1arg\\(double\\) at.*$srcfile:121\r +\[0-9\]+\[\t \]+breakpoint keep y\[\t \]+$hex\[\t \]+in foo::overload1arg\\(float\\) at.*$srcfile:120\r +\[0-9\]+\[\t \]+breakpoint keep y\[\t \]+$hex\[\t \]+in foo::overload1arg\\(unsigned long\\) at.*$srcfile:119\r +\[0-9\]+\[\t \]+breakpoint keep y\[\t \]+$hex\[\t \]+in foo::overload1arg\\(long\\) at.*$srcfile:118\r +\[0-9\]+\[\t \]+breakpoint keep y\[\t \]+$hex\[\t \]+in foo::overload1arg\\((unsigned|unsigned int)\\) at.*$srcfile:117\r +\[0-9\]+\[\t \]+breakpoint keep y\[\t \]+$hex\[\t \]+in foo::overload1arg\\(int\\) at.*$srcfile:116\r +\[0-9\]+\[\t \]+breakpoint keep y\[\t \]+$hex\[\t \]+in foo::overload1arg\\(unsigned short\\) at.*$srcfile:115\r +\[0-9\]+\[\t \]+breakpoint keep y\[\t \]+$hex\[\t \]+in foo::overload1arg\\(short\\) at.*$srcfile:114\r +\[0-9\]+\[\t \]+breakpoint keep y\[\t \]+$hex\[\t \]+in foo::overload1arg\\(unsigned char\\) at.*$srcfile:113\r +\[0-9\]+\[\t \]+breakpoint keep y\[\t \]+$hex\[\t \]+in foo::overload1arg\\(signed char\\) at.*$srcfile:112\r +\[0-9\]+\[\t \]+breakpoint keep y\[\t \]+$hex\[\t \]+in foo::overload1arg\\(char\\) at.*$srcfile:111\r +\[0-9\]+\[\t \]+breakpoint keep y\[\t \]+$hex\[\t \]+in foo::overload1arg\\((void|)\\) at.*$srcfile:110" \ + "breakpoint info (after setting on all)" + + + +# Run through each breakpoint. + +# NOTE: carlton/2003-02-03: I'm seeing failures on some of the tests, +# with the wrong arg being printed out. Michael Chastain sees +# failures at times, too, albeit fewer than I do. + +proc continue_to_bp_overloaded {might_kfail bpnumber argtype actuals} { + global gdb_prompt hex decimal srcfile + + send_gdb "continue\n" + gdb_expect { + -re "Continuing.\r\n\r\nBreakpoint ${bpnumber}, (${hex} in )?foo::overload1arg(\\(${argtype}\\))? \\(this=${hex}(, )?${actuals}\\) at.*${srcfile}:${decimal}\r\n${decimal}\[\t \]+int foo::overload1arg \\(${argtype}( arg)?\\).*\r\n.*$gdb_prompt $" { + pass "continue to bp overloaded : ${argtype}" + } + -re "Continuing.\r\n\r\nBreakpoint ${bpnumber}, (${hex} in )?foo::overload1arg(\\(${argtype}\\))? \\(this=${hex}, arg=.*\\) at.*${srcfile}:${decimal}\r\n${decimal}\[\t \]+int foo::overload1arg \\(${argtype}( arg)?\\).*\r\n.*$gdb_prompt $" { + if $might_kfail { + kfail "gdb/1025" "continue to bp overloaded : ${argtype}" + } else { + fail "continue to bp overloaded : ${argtype}" + } + } + -re ".*$gdb_prompt $" { + fail "continue to bp overloaded : ${argtype}" + } + timeout { + fail "continue to bp overloaded : ${argtype} (timeout)" + } + } +} + +continue_to_bp_overloaded 0 25 "(void|)" "" +continue_to_bp_overloaded 1 24 "char" "arg=2 \\'\\\\002\\'" +continue_to_bp_overloaded 1 23 "signed char" "arg=3 \\'\\\\003\\'" +continue_to_bp_overloaded 1 22 "unsigned char" "arg=4 \\'\\\\004\\'" +continue_to_bp_overloaded 1 21 "short" "arg=5" +continue_to_bp_overloaded 1 20 "unsigned short" "arg=6" +continue_to_bp_overloaded 0 19 "int" "arg=7" +continue_to_bp_overloaded 0 18 "(unsigned|unsigned int)" "arg=8" +continue_to_bp_overloaded 0 17 "long" "arg=9" +continue_to_bp_overloaded 0 16 "unsigned long" "arg=10" +continue_to_bp_overloaded 0 15 "float" "arg=100" +continue_to_bp_overloaded 1 14 "double" "arg=200" + + + +# That's all, folks. + +gdb_continue_to_end "finish program" diff --git a/gdb/testsuite/gdb.cp/pr-1023.cc b/gdb/testsuite/gdb.cp/pr-1023.cc new file mode 100644 index 0000000..7583084 --- /dev/null +++ b/gdb/testsuite/gdb.cp/pr-1023.cc @@ -0,0 +1,20 @@ +class myClass +{ + public: + myClass() {}; + ~myClass() {}; + void performUnblocking( short int cell_index ); + void performBlocking( int cell_index ); +}; + +void myClass::performUnblocking( short int cell_index ) {} + +void myClass::performBlocking( int cell_index ) {} + +int main () +{ + myClass mc; + mc.performBlocking (0); + mc.performUnblocking (0); +} + diff --git a/gdb/testsuite/gdb.cp/pr-1023.exp b/gdb/testsuite/gdb.cp/pr-1023.exp new file mode 100644 index 0000000..c8c9802 --- /dev/null +++ b/gdb/testsuite/gdb.cp/pr-1023.exp @@ -0,0 +1,79 @@ +# Copyright 2003 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# Tests for PR gdb/1023. +# 2003-02-03 Michael Chastain + +# This file is part of the gdb testsuite. + +if $tracelevel then { + strace $tracelevel + } + +if { [skip_cplus_tests] } { continue } + +# +# test running programs +# +set prms_id 0 +set bug_id 0 + +set testfile "pr-1023" +set srcfile ${testfile}.cc +set binfile ${objdir}/${subdir}/${testfile} + +if { [gdb_compile "${srcdir}/${subdir}/${srcfile}" "${binfile}" executable {debug c++}] != "" } { + gdb_suppress_entire_file "Testcase compile failed, so all tests in this file will automatically fail." +} + +if [get_compiler_info ${binfile} "c++"] { + return -1 +} + +gdb_exit +gdb_start +gdb_reinitialize_dir $srcdir/$subdir +gdb_load ${binfile} + +if ![runto_main] then { + perror "couldn't run to breakpoint" + continue +} + +send_gdb "break myClass::performBlocking\n" +gdb_expect { + -re "Breakpoint $decimal at $hex: file .*$srcfile, line 12.*$gdb_prompt $" { + pass "break myClass::performBlocking" + } + -re "the class myClass does not have any method named performBlocking.*$gdb_prompt $" { + # fails with gcc 2.95.3 -gstabs+, native i686-pc-linux-gnu + # -- chastain 2003-02-03 + kfail "gdb/1023" "break myClass::performBlocking" + } + -re ".*$gdb_prompt $" { + fail "break myClass::performBlocking" + } + timeout { + fail "break myClass::performBlocking (timeout)" + } +} + +gdb_test \ + "break myClass::performUnblocking" \ + "Breakpoint $decimal at $hex: file .*$srcfile, line 10.*" + +gdb_exit +return 0 diff --git a/gdb/testsuite/gdb.cp/pr-1210.cc b/gdb/testsuite/gdb.cp/pr-1210.cc new file mode 100644 index 0000000..5747e5d --- /dev/null +++ b/gdb/testsuite/gdb.cp/pr-1210.cc @@ -0,0 +1,19 @@ +class A +{ +}; + +class B : virtual public A +{ +}; + +class C : public A +{ + protected: + B myB; +}; + +int main() +{ + C *obj = new C(); + return 0; +} diff --git a/gdb/testsuite/gdb.cp/pr-1210.exp b/gdb/testsuite/gdb.cp/pr-1210.exp new file mode 100644 index 0000000..3ff850d --- /dev/null +++ b/gdb/testsuite/gdb.cp/pr-1210.exp @@ -0,0 +1,76 @@ +# Copyright 2003 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# Tests for PR gdb/1210. + +# This file is part of the gdb testsuite. + +if $tracelevel then { + strace $tracelevel +} + +if { [skip_cplus_tests] } { continue } + +# +# test running programs +# +set prms_id 0 +set bug_id 0 + +set testfile "pr-1210" +set srcfile ${testfile}.cc +set binfile ${objdir}/${subdir}/${testfile} + +if { [gdb_compile "${srcdir}/${subdir}/${srcfile}" "${binfile}" executable {debug c++}] != "" } { + gdb_suppress_entire_file "Testcase compile failed, so all tests in this file will automatically fail." +} + +if [get_compiler_info ${binfile} "c++"] { + return -1 +} + +gdb_exit +gdb_start +gdb_reinitialize_dir $srcdir/$subdir +gdb_load ${binfile} + +if ![runto_main] then { + perror "couldn't run to breakpoint" + continue +} + +gdb_test "next" ".*return 0;" "step past initialization" + +gdb_test_multiple "print *obj" "" { + -re "Cannot access memory.*$gdb_prompt $" { + fail "print *obj" + } + -re " = { = {}, myB = { = {}.*}}\r\n$gdb_prompt $" { + pass "print *obj" + } +} + +gdb_test_multiple "print obj->myB" "" { + -re "Cannot access memory.*$gdb_prompt $" { + fail "print obj->myB" + } + -re " = { = {}.*}\r\n$gdb_prompt $" { + pass "print obj->myB" + } +} + +gdb_exit +return 0 diff --git a/gdb/testsuite/gdb.cp/pr-574.cc b/gdb/testsuite/gdb.cp/pr-574.cc new file mode 100644 index 0000000..eb06b61 --- /dev/null +++ b/gdb/testsuite/gdb.cp/pr-574.cc @@ -0,0 +1,22 @@ +/* + An attempt to replicate PR gdb/574 with a shorter program. + + Printing out *theB failed if the program was compiled with GCC 2.95. +*/ + +class A { +public: + virtual void foo() {}; // Stick in a virtual function. + int a; // Stick in a data member. +}; + +class B : public A { + static int b; // Stick in a static data member. +}; + +int main() +{ + B *theB = new B; + + return 0; // breakpoint: constructs-done +} diff --git a/gdb/testsuite/gdb.cp/pr-574.exp b/gdb/testsuite/gdb.cp/pr-574.exp new file mode 100644 index 0000000..5beacd1 --- /dev/null +++ b/gdb/testsuite/gdb.cp/pr-574.exp @@ -0,0 +1,72 @@ +# Copyright 2002 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# Tests for the bug mentioned in PR gdb/574. It's a bit +# idiosyncratic, so I gave it its own file. + +# 2002-08-16 David Carlton + +# This file is part of the gdb testsuite + +if $tracelevel then { + strace $tracelevel + } + +if { [skip_cplus_tests] } { continue } + +# +# test running programs +# +set prms_id 0 +set bug_id 0 + +set testfile "pr-574" +set srcfile ${testfile}.cc +set binfile ${objdir}/${subdir}/${testfile} + +if { [gdb_compile "${srcdir}/${subdir}/${srcfile}" "${binfile}" executable {debug c++}] != "" } { + gdb_suppress_entire_file "Testcase compile failed, so all tests in this file will automatically fail." +} + +if [get_compiler_info ${binfile} "c++"] { + return -1 +} + +gdb_exit +gdb_start +gdb_reinitialize_dir $srcdir/$subdir +gdb_load ${binfile} + + +if ![runto_main] then { + perror "couldn't run to breakpoint" + continue +} + +# First, run to after we've constructed the object: + +gdb_breakpoint [gdb_get_line_number "constructs-done"] +gdb_continue_to_breakpoint "end of constructors" + +# This failed, as long as the code was compiled with GCC v. 2. + +# Different compilers order the data for differently, so I'm not +# matching the result exactly. + +gdb_test "print *theB" "\\$\[0-9\]* = { = {\[^}\]*}, static b = }" "PR gdb/574" + +gdb_exit +return 0 diff --git a/gdb/testsuite/gdb.cp/printmethod.cc b/gdb/testsuite/gdb.cp/printmethod.cc new file mode 100644 index 0000000..d32e1b1 --- /dev/null +++ b/gdb/testsuite/gdb.cp/printmethod.cc @@ -0,0 +1,14 @@ +/* Create some objects, and try to print out their methods. */ + +class A { +public: + virtual void virt() {}; + void nonvirt() {}; +}; + +int main() +{ + A *theA = new A; + + return 0; // breakpoint: constructs-done +} diff --git a/gdb/testsuite/gdb.cp/printmethod.exp b/gdb/testsuite/gdb.cp/printmethod.exp new file mode 100644 index 0000000..a45393f --- /dev/null +++ b/gdb/testsuite/gdb.cp/printmethod.exp @@ -0,0 +1,69 @@ +# Copyright 2002, 2003 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# This tries to print out methods of classes. + +# 2002-08-16 David Carlton + +# This file is part of the gdb testsuite + +if $tracelevel then { + strace $tracelevel + } + +if { [skip_cplus_tests] } { continue } + +# +# test running programs +# +set prms_id 0 +set bug_id 0 + +set testfile "printmethod" +set srcfile ${testfile}.cc +set binfile ${objdir}/${subdir}/${testfile} + +if { [gdb_compile "${srcdir}/${subdir}/${srcfile}" "${binfile}" executable {debug c++}] != "" } { + gdb_suppress_entire_file "Testcase compile failed, so all tests in this file will automatically fail." +} + +if [get_compiler_info ${binfile} "c++"] { + return -1 +} + +gdb_exit +gdb_start +gdb_reinitialize_dir $srcdir/$subdir +gdb_load ${binfile} + + +if ![runto_main] then { + perror "couldn't run to breakpoint" + continue +} + +# First, run to after we've constructed the object: + +gdb_breakpoint [gdb_get_line_number "constructs-done"] +gdb_continue_to_breakpoint "end of constructors" + +# The first of these is for PR gdb/653. + +gdb_test "print theA->virt" "\\$\[0-9\]* = &A::virt\\((void|)\\)" "print virtual method." +gdb_test "print theA->nonvirt" "Cannot take address of a method" "print nonvirtual method." + +gdb_exit +return 0 diff --git a/gdb/testsuite/gdb.cp/psmang.exp b/gdb/testsuite/gdb.cp/psmang.exp new file mode 100644 index 0000000..31dd346 --- /dev/null +++ b/gdb/testsuite/gdb.cp/psmang.exp @@ -0,0 +1,226 @@ +# Copyright 2002 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# Please email any bugs, comments, and/or additions to this file to: +# bug-gdb@prep.ai.mit.edu + +# This file is part of the gdb testsuite + +# Looking up methods by name, in programs with multiple compilation units. + +# ====== PLEASE BE VERY CAREFUL WHEN CHANGING THIS TEST. ===== +# +# The bug we're testing for (circa October 2002) is very sensitive to +# various conditions that are hard to control directly in the test +# suite. If you change the test, please revert this change, and make +# sure the test still fails: +# +# 2002-08-29 Jim Blandy +# +# * symtab.c (lookup_symbol_aux): In the cases where we find a +# minimal symbol of an appropriate name and use its address to +# select a symtab to read and search, use `name' (as passed to us) +# as the demangled name when searching the symtab's global and +# static blocks, not the minsym's name. +# +# The original bug was that you'd try to set a breakpoint on a method +# (e.g., `break s::method1'), and you'd get an error, but if you +# repeated the command, it would work the second time: +# +# (gdb) break s::method1 +# the class s does not have any method named method1 +# Hint: try 's::method1 or 's::method1 +# (Note leading single quote.) +# (gdb) break s::method1 +# Breakpoint 1 at 0x804841b: file psmang1.cc, line 13. +# (gdb) +# +# We observed this bug first using Stabs, and then using Dwarf 2. +# +# The problem was in lookup_symbol_aux: when looking up s::method1, it +# would fail to find it in any symtabs, find the minsym with the +# corresponding mangled name (say, `_ZN1S7method1Ev'), pass the +# minsym's address to find_pc_sect_symtab to look up the symtab +# (causing the compilation unit's full symbols to be read in), and +# then look up the symbol in that symtab's global block. All that is +# correct. However, it would pass the minsym's name as the NAME +# argument to lookup_block_symbol; a minsym's name is mangled, whereas +# lookup_block_symbol's NAME argument should be demangled. +# +# This is a pretty simple bug, but it turns out to be a bear to +# construct a test for. That's why this test case is so delicate. If +# you can see how to make it less so, please contribute a patch. +# +# Here are the twists: +# +# The bug only manifests itself when we call lookup_symbol to look up +# a method name (like "s::method1" or "s::method2"), and that method's +# definition is in a compilation unit for which we have read partial +# symbols, but not full symbols. The partial->full conversion must be +# caused by that specific lookup. (If we already have full symbols +# for the method's compilation unit, we won't need to look up the +# minsym, find the symtab for the minsym's address, and then call +# lookup_block_symbol; it's that last call where things go awry.) +# +# Now, when asked to set a breakpoint at `s::method1', GDB will first +# look up `s' to see if that is, in fact, the name of a class, and +# then look up 's::method1'. So we have to make sure that looking up +# `s' doesn't cause full symbols to be read for the compilation unit +# containing the definition of `s::method1'. +# +# The partial symbol tables for `psmang1.cc' and `psmang2.cc' will +# both have entries for `s'; GDB will read full symbols for whichever +# compilation unit's partial symbol table appears first in the +# objfile's list. The order in which compilation units appear in the +# partial symbol table list depends on how the program is linked, and +# how the debug info reader does the partial symbol scan. Ideally, +# the test shouldn't rely on them appearing in any particular order. +# +# So, since we don't know which compilation unit's full symbols are +# going to get read, we simply try looking up one method from each of +# the two compilation units. One of them has to come after the other +# in the partial symbol table list, so whichever comes later will +# still need its partial symbols read by the time we go to look up +# 's::methodX'. +# +# Second twist: don't move the common definition of `struct s' into a +# header file. If the compiler emits identical stabs for the +# #inclusion of that header file into psmang1.cc and into psmang2.cc, +# then the linker will do stabs compression, and replace one of the +# BINCL/EINCL regions with an EXCL stab, pointing to the other +# BINCL/EINCL region. GDB will read this, and record that the +# compilation unit that got the EXCL depends on the compilation unit +# that kept the BINCL/EINCL. Then, when it decides it needs to read +# full symbols for the former, it'll also read full symbols for the +# latter. Now, if it just so happens that the compilation unit that +# got the EXCL is also the first one with a definition of `s' in the +# partial symbol table list, then that first probe for `s' will cause +# both compilation units' full symbols to be read --- again defeating +# the test. +# +# We could work around this by having three compilation units, or by +# ensuring that the header file produces different stabs each time +# it's #included, but it seems simplest just to avoid compilation unit +# dependencies altogether, drop the header file, and duplicate the +# (pretty trivial) struct definition. +# +# Note that #including any header file at all into both compilation +# units --- say, --- could create this sort of dependency. +# +# This is the aspect of the test which the debug format is most likely +# to affect, I think. The different formats create different kinds of +# inter-CU dependencies, which could mask the bug. It might be +# possible for the test to check that at least one of the partial +# symtabs remains unread, and fail otherwise --- the failure +# indicating that the test itself isn't going to catch the bug it was +# meant to, not that GDB is misbehaving. +# +# Third twist: given the way lookup_block_symbol is written, it's +# possible to find the symbol even when it gets passed a mangled name +# for its NAME parameter. There are three ways lookup_block_symbol +# might search a block, depending on how it was constructed: +# +# linear search. In this case, this bug will never manifest itself, +# since we check every symbol against NAME using SYMBOL_MATCHES_NAME. +# Since that macro checks its second argument (NAME) against both the +# mangled and demangled names of the symbol, this will always find the +# symbol successfully, so, no bug. +# +# hash table. If both the mangled and demangled names hash to the +# same bucket, then you'll again find the symbol "by accident", since +# we search the entire bucket using SYMBOL_SOURCE_NAME. Since GDB +# chooses the number of buckets based on the number of symbols, small +# compilation units may have only one hash bucket; in this case, the +# search always succeeds, even though we hashed on the wrong name. +# This test works around that by having a lot of dummy variables, +# making it less likely that the mangled and demangled names fall in +# the same bucket. +# +# binary search. (GDB 5.2 produced these sorts of blocks, and this +# test tries to detect the bug there, but subsequent versions of GDB +# almost never build them, and they may soon be removed entirely.) In +# this case, the symbols in the block are sorted by their +# SYMBOL_SOURCE_NAME (whose behavior depends on the current demangling +# setting, so that's wrong, but let's try to stay focussed). +# lookup_block_symbol does a binary search comparing NAME with +# SYMBOL_SOURCE_NAME until the range has been narrowed down to only a +# few symbols; then it starts a linear search forward from the lower +# end of that range, until it reaches a symbol whose +# SYMBOL_SOURCE_NAME follows NAME in lexicographic order. This means +# that, if you're doing a binary search for a mangled name in a block +# sorted by SYMBOL_SOURCE_NAME, you might find the symbol `by +# accident' if the mangled and demangled names happen to fall near +# each other in the ordering. The initial version of this patch used +# a class called `S'; all the other symbols in the compilation unit +# started with lower-case letters, so the demangled name `S::method1' +# sorted at the same place as the mangled name `_ZN1S7method1Ev': at +# the very beginning. Using a lower-case 's' as the name ensures that +# the demangled name falls after all the dummy symbols introduced for +# the hash table, as described above. +# +# This is all so tortured, someone will probably come up with still +# other ways this test could fail to do its job. If you need to make +# revisions, please be very careful. + +if $tracelevel then { + strace $tracelevel +} + +# +# test running programs +# + +set prms_id 0 +set bug_id 0 + +if { [skip_cplus_tests] } { continue } + +set testfile "psmang" +set binfile ${objdir}/${subdir}/${testfile} + +if [get_compiler_info ${binfile} "c++"] { + return -1; +} + +if { [gdb_compile "${srcdir}/${subdir}/${testfile}1.cc" "${testfile}1.o" object {debug c++}] != "" } { + gdb_suppress_entire_file "Testcase compile failed, so all tests in this file will automatically fail." +} + +if { [gdb_compile "${srcdir}/${subdir}/${testfile}2.cc" "${testfile}2.o" object {debug c++}] != "" } { + gdb_suppress_entire_file "Testcase compile failed, so all tests in this file will automatically fail." +} + +if { [gdb_compile "${testfile}1.o ${testfile}2.o" ${binfile} executable {debug c++}] != "" } { + gdb_suppress_entire_file "Testcase compile failed, so all tests in this file will automatically fail." +} + + +gdb_exit +gdb_start +gdb_reinitialize_dir $srcdir/$subdir +gdb_load ${binfile} + +gdb_test "break s::method1" "Breakpoint .* at .*: file .*psmang1.cc.*" + +# We have to exit and restart GDB here, to make sure that all the +# compilation units are psymtabs again. + +gdb_exit +gdb_start +gdb_reinitialize_dir $srcdir/$subdir +gdb_load ${binfile} + +gdb_test "break s::method2" "Breakpoint .* at .*: file .*psmang2.cc.*" diff --git a/gdb/testsuite/gdb.cp/psmang1.cc b/gdb/testsuite/gdb.cp/psmang1.cc new file mode 100644 index 0000000..19a9283 --- /dev/null +++ b/gdb/testsuite/gdb.cp/psmang1.cc @@ -0,0 +1,159 @@ +/* Do not move this definition into a header file! See the comments + in psmang.exp. */ +struct s +{ + int value; + void method1 (void); + void method2 (void); +}; + +void +s::method1 () +{ + value = 42; +} + +int +main (int argc, char **argv) +{ + s si; + + si.method1 (); + si.method2 (); +} + + +/* The presence of these variables ensures there will be so many + symbols in psmang1.cc's symtab's global block that it will have a + non-trivial hash table. When there are only a very few symbols, + the block only has one hash bucket, so even if we compute the hash + value for the wrong symbol name, we'll still find a symbol that + matches. */ +int ax; +int bx; +int a1x; +int b1x; +int a2x; +int b2x; +int a12x; +int b12x; +int a3x; +int b3x; +int a13x; +int b13x; +int a23x; +int b23x; +int a123x; +int b123x; +int a4x; +int b4x; +int a14x; +int b14x; +int a24x; +int b24x; +int a124x; +int b124x; +int a34x; +int b34x; +int a134x; +int b134x; +int a234x; +int b234x; +int a1234x; +int b1234x; +int a5x; +int b5x; +int a15x; +int b15x; +int a25x; +int b25x; +int a125x; +int b125x; +int a35x; +int b35x; +int a135x; +int b135x; +int a235x; +int b235x; +int a1235x; +int b1235x; +int a45x; +int b45x; +int a145x; +int b145x; +int a245x; +int b245x; +int a1245x; +int b1245x; +int a345x; +int b345x; +int a1345x; +int b1345x; +int a2345x; +int b2345x; +int a12345x; +int b12345x; +int a6x; +int b6x; +int a16x; +int b16x; +int a26x; +int b26x; +int a126x; +int b126x; +int a36x; +int b36x; +int a136x; +int b136x; +int a236x; +int b236x; +int a1236x; +int b1236x; +int a46x; +int b46x; +int a146x; +int b146x; +int a246x; +int b246x; +int a1246x; +int b1246x; +int a346x; +int b346x; +int a1346x; +int b1346x; +int a2346x; +int b2346x; +int a12346x; +int b12346x; +int a56x; +int b56x; +int a156x; +int b156x; +int a256x; +int b256x; +int a1256x; +int b1256x; +int a356x; +int b356x; +int a1356x; +int b1356x; +int a2356x; +int b2356x; +int a12356x; +int b12356x; +int a456x; +int b456x; +int a1456x; +int b1456x; +int a2456x; +int b2456x; +int a12456x; +int b12456x; +int a3456x; +int b3456x; +int a13456x; +int b13456x; +int a23456x; +int b23456x; +int a123456x; +int b123456x; diff --git a/gdb/testsuite/gdb.cp/psmang2.cc b/gdb/testsuite/gdb.cp/psmang2.cc new file mode 100644 index 0000000..b9b1bb5 --- /dev/null +++ b/gdb/testsuite/gdb.cp/psmang2.cc @@ -0,0 +1,152 @@ +#include + +/* Do not move this definition into a header file! See the comments + in psmang.exp. */ +struct s +{ + int value; + void method1 (void); + void method2 (void); +}; + +void +s::method2 (void) +{ + printf ("%d\n", value); +} + + +/* The presence of these variables ensures there will be so many + symbols in psmang2.cc's symtab's global block that it will have a + non-trivial hash table. When there are only a very few symbols, + the block only has one hash bucket, so even if we compute the hash + value for the wrong symbol name, we'll still find a symbol that + matches. */ +int a; +int b; +int a1; +int b1; +int a2; +int b2; +int a12; +int b12; +int a3; +int b3; +int a13; +int b13; +int a23; +int b23; +int a123; +int b123; +int a4; +int b4; +int a14; +int b14; +int a24; +int b24; +int a124; +int b124; +int a34; +int b34; +int a134; +int b134; +int a234; +int b234; +int a1234; +int b1234; +int a5; +int b5; +int a15; +int b15; +int a25; +int b25; +int a125; +int b125; +int a35; +int b35; +int a135; +int b135; +int a235; +int b235; +int a1235; +int b1235; +int a45; +int b45; +int a145; +int b145; +int a245; +int b245; +int a1245; +int b1245; +int a345; +int b345; +int a1345; +int b1345; +int a2345; +int b2345; +int a12345; +int b12345; +int a6; +int b6; +int a16; +int b16; +int a26; +int b26; +int a126; +int b126; +int a36; +int b36; +int a136; +int b136; +int a236; +int b236; +int a1236; +int b1236; +int a46; +int b46; +int a146; +int b146; +int a246; +int b246; +int a1246; +int b1246; +int a346; +int b346; +int a1346; +int b1346; +int a2346; +int b2346; +int a12346; +int b12346; +int a56; +int b56; +int a156; +int b156; +int a256; +int b256; +int a1256; +int b1256; +int a356; +int b356; +int a1356; +int b1356; +int a2356; +int b2356; +int a12356; +int b12356; +int a456; +int b456; +int a1456; +int b1456; +int a2456; +int b2456; +int a12456; +int b12456; +int a3456; +int b3456; +int a13456; +int b13456; +int a23456; +int b23456; +int a123456; +int b123456; diff --git a/gdb/testsuite/gdb.cp/ref-types.cc b/gdb/testsuite/gdb.cp/ref-types.cc new file mode 100644 index 0000000..23cc510 --- /dev/null +++ b/gdb/testsuite/gdb.cp/ref-types.cc @@ -0,0 +1,79 @@ +int main2(void); + +void marker1 (void) +{ + +} + + + +int main(void) +{ + short s; + short &rs = s; + short *ps; + short *&rps = ps; + short as[4]; + short (&ras)[4] = as; + s = -1; + ps = &s; + as[0] = 0; + as[1] = 1; + as[2] = 2; + as[3] = 3; + + #ifdef usestubs + set_debug_traps(); + breakpoint(); + #endif + marker1(); + + main2(); + + return 0; +} + +int f() +{ + int f1; + f1 = 1; + return f1; +} + +int main2(void) +{ + char C; + unsigned char UC; + short S; + unsigned short US; + int I; + unsigned int UI; + long L; + unsigned long UL; + float F; + double D; + char &rC = C; + unsigned char &rUC = UC; + short &rS = S; + unsigned short &rUS = US; + int &rI = I; + unsigned int &rUI = UI; + long &rL = L; + unsigned long &rUL = UL; + float &rF = F; + double &rD = D; + C = 'A'; + UC = 21; + S = -14; + US = 7; + I = 102; + UI = 1002; + L = -234; + UL = 234; + F = 1.25E10; + D = -1.375E-123; + I = f(); + + return 0; + +} diff --git a/gdb/testsuite/gdb.cp/ref-types.exp b/gdb/testsuite/gdb.cp/ref-types.exp new file mode 100644 index 0000000..dd06f02 --- /dev/null +++ b/gdb/testsuite/gdb.cp/ref-types.exp @@ -0,0 +1,663 @@ +# Tests for reference types with short type variables in GDB. +# Copyright 1998, 1999, 2000 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# Please email any bugs, comments, and/or additions to this file to: +# bug-gdb@prep.ai.mit.edu + +# written by Elena Zannoni (ezannoni@cygnus.com) + +if $tracelevel then { + strace $tracelevel + } + +# +# test running programs +# +set prms_id 0 +set bug_id 0 + +if { [skip_cplus_tests] } { continue } + +set testfile "ref-types" +set srcfile ${testfile}.cc +set binfile ${objdir}/${subdir}/${testfile} + +if { [gdb_compile "${srcdir}/${subdir}/${srcfile}" "${binfile}" executable {debug c++}] != "" } { + gdb_suppress_entire_file "Testcase compile failed, so all tests in this file will automatically fail." +} + +gdb_exit +gdb_start +gdb_reinitialize_dir $srcdir/$subdir +gdb_load ${binfile} + + +# +# set it up at a breakpoint so we can play with the variable values +# +if ![runto_main] then { + perror "couldn't run to breakpoint" + continue +} + +if ![runto 'marker1'] then { + perror "couldn't run to marker1" + continue +} + +gdb_test "up" ".*main.*" "up from marker1 1" + +proc gdb_start_again {} { + global srcdir + global subdir + global binfile + global gdb_prompt + global decimal + + gdb_start + gdb_reinitialize_dir $srcdir/$subdir + gdb_load ${binfile} + + source ${binfile}.ci + + # + # set it up at a breakpoint so we can play with the variable values + # + if ![runto_main] then { + perror "couldn't run to breakpoint" + continue + } + + if ![runto 'marker1'] then { + perror "couldn't run to marker1" + continue + } + + gdb_test "up" ".*main.*" "up from marker1 2" +} + + + +send_gdb "print s\n" +gdb_expect { + -re ".\[0-9\]* = -1.*$gdb_prompt $" { + pass "print value of s" + } + -re ".*$gdb_prompt $" { fail "print value of s" } + timeout { fail "(timeout) print value of s" } + } + + +send_gdb "ptype s\n" +gdb_expect { + -re "type = short.*$gdb_prompt $" { pass "ptype s" } + -re ".*$gdb_prompt $" { fail "ptype s" } + timeout { fail "(timeout) ptype s" } +} + + +send_gdb "print *ps\n" +gdb_expect { + -re ".\[0-9\]* = -1.*$gdb_prompt $" { + pass "print value of ps" + } + -re ".*$gdb_prompt $" { fail "print value of ps" } + timeout { fail "(timeout) print value of ps" } + } + + +send_gdb "ptype ps\n" +gdb_expect { + -re "type = short \*.*$gdb_prompt $" { pass "ptype ps" } + -re ".*$gdb_prompt $" { fail "ptype ps" } + timeout { fail "(timeout) ptype ps" } +} + +send_gdb "print as\[0\]\n" +gdb_expect { + -re ".\[0-9\]* = 0.*$gdb_prompt $" { + pass "print value of as\[0\]" + } + -re ".*$gdb_prompt $" { fail "print value of as\[0\]" } + timeout { fail "(timeout) print value of as\[0\]" } + } + + +send_gdb "ptype as\n" +gdb_expect { + -re "type = short \\\[4\\\].*$gdb_prompt $" { pass "ptype as" } + -re "type = short int \\\[4\\\].*$gdb_prompt $" { pass "ptype as" } + -re ".*$gdb_prompt $" { fail "ptype as" } + timeout { fail "(timeout) ptype as" } +} + +send_gdb "print as\[1\]\n" +gdb_expect { + -re ".\[0-9\]* = 1.*$gdb_prompt $" { + pass "print value of as\[1\]" + } + -re ".*$gdb_prompt $" { fail "print value of as\[1\]" } + timeout { fail "(timeout) print value of as\[1\]" } + } + +send_gdb "print as\[2\]\n" +gdb_expect { + -re ".\[0-9\]* = 2.*$gdb_prompt $" { + pass "print value of as\[2\]" + } + -re ".*$gdb_prompt $" { fail "print value of as\[2\]" } + timeout { fail "(timeout) print value of as\[2\]" } + } + +send_gdb "print as\[3\]\n" +gdb_expect { + -re ".\[0-9\]* = 3.*$gdb_prompt $" { + pass "print value of as\[3\]" + } + -re ".*$gdb_prompt $" { fail "print value of as\[3\]" } + timeout { fail "(timeout) print value of as\[3\]" } + } + +send_gdb "print rs\n" +gdb_expect { + -re ".\[0-9\]* = \\(short &\\) @$hex: -1.*$gdb_prompt $" { + pass "print value of rs" + } + -re ".\[0-9\]* = \\(short int &\\) @$hex: -1.*$gdb_prompt $" { + pass "print value of rs" + } + -re ".*$gdb_prompt $" { fail "print value of rs" } + timeout { fail "(timeout) print value of rs" } + eof { fail "print rs ($GDB dumped core) (FIXME)" ; gdb_start_again ; } + + } + +send_gdb "ptype rs\n" +gdb_expect { + -re "type = short &.*$gdb_prompt $" { pass "ptype rs" } + -re "type = short int &.*$gdb_prompt $" { pass "ptype rs" } + -re ".*$gdb_prompt $" { fail "ptype rs" } + timeout { fail "(timeout) ptype rs" } +} + + +send_gdb "print *rps\n" +gdb_expect { + -re ".\[0-9\]* = -1.*$gdb_prompt $" { + pass "print value of *rps" + } + -re ".*$gdb_prompt $" { fail "print value of *rps" } + timeout { fail "(timeout) print value of *rps" } + } + + +send_gdb "ptype rps\n" +gdb_expect { + -re "type = short \\*&.*$gdb_prompt $" { pass "ptype rps" } + -re "type = short int \\*&.*$gdb_prompt $" { pass "ptype rps" } + -re ".*$gdb_prompt $" { fail "ptype rps" } + timeout { fail "(timeout) ptype rps" } +} + + + +send_gdb "print ras\[0\]\n" +gdb_expect { + -re ".\[0-9\]* = 0.*$gdb_prompt $" { + pass "print value of ras\[0\]" + } + -re ".*$gdb_prompt $" { fail "print value of ras\[0\]" } + timeout { fail "(timeout) print value of ras\[0\]" } + } + + +send_gdb "ptype ras\n" +gdb_expect { + -re "type = short \\\(&\\\)\\\[4\\\].*$gdb_prompt $" { pass "ptype ras" } + -re "type = short int \\\(&\\\)\\\[4\\\].*$gdb_prompt $" { pass "ptype ras" } + -re ".*$gdb_prompt $" { fail "ptype ras" } + timeout { fail "(timeout) ptype ras" } +} + +send_gdb "print ras\[1\]\n" +gdb_expect { + -re ".\[0-9\]* = 1.*$gdb_prompt $" { + pass "print value of ras\[1\]" + } + -re ".*$gdb_prompt $" { fail "print value of ras\[1\]" } + timeout { fail "(timeout) print value of ras\[1\]" } + } + +send_gdb "print ras\[2\]\n" +gdb_expect { + -re ".\[0-9\]* = 2.*$gdb_prompt $" { + pass "print value of ras\[2\]" + } + -re ".*$gdb_prompt $" { fail "print value of ras\[2\]" } + timeout { fail "(timeout) print value of ras\[2\]" } + } + +send_gdb "print ras\[3\]\n" +gdb_expect { + -re ".\[0-9\]* = 3.*$gdb_prompt $" { + pass "print value of ras\[3\]" + } + -re ".*$gdb_prompt $" { fail "print value of ras\[3\]" } + timeout { fail "(timeout) print value of ras\[3\]" } + } + + +if ![runto 'f'] then { + perror "couldn't run to f" + continue +} + +gdb_test "up" ".main2.*" "up from f" + +send_gdb "print C\n" +gdb_expect { + -re ".\[0-9\]* = 65 \'A\'.*$gdb_prompt $" { + pass "print value of C" + } + -re ".*$gdb_prompt $" { fail "print value of C" } + timeout { fail "(timeout) print value of C" } + } + + +send_gdb "ptype C\n" +gdb_expect { + -re "type = char.*$gdb_prompt $" { pass "ptype C" } + -re ".*$gdb_prompt $" { fail "ptype C" } + timeout { fail "(timeout) ptype C" } +} + + +send_gdb "print UC\n" +gdb_expect { + -re ".\[0-9\]* = 21 '\.025'\.*$gdb_prompt $" { + pass "print value of UC" + } + -re ".*$gdb_prompt $" { fail "print value of UC" } + timeout { fail "(timeout) print value of UC" } + } + + +send_gdb "ptype UC\n" +gdb_expect { + -re "type = unsigned char.*$gdb_prompt $" { pass "ptype UC" } + -re ".*$gdb_prompt $" { fail "ptype UC" } + timeout { fail "(timeout) ptype UC" } +} + + +send_gdb "print S\n" +gdb_expect { + -re ".\[0-9\]* = -14.*$gdb_prompt $" { + pass "print value of S" + } + -re ".*$gdb_prompt $" { fail "print value of S" } + timeout { fail "(timeout) print value of S" } + } + + +send_gdb "ptype S\n" +gdb_expect { + -re "type = short.*$gdb_prompt $" { pass "ptype S" } + -re ".*$gdb_prompt $" { fail "ptype S" } + timeout { fail "(timeout) ptype S" } +} + + +send_gdb "print US\n" +gdb_expect { + -re ".\[0-9\]* = 7.*$gdb_prompt $" { + pass "print value of US" + } + -re ".*$gdb_prompt $" { fail "print value of US" } + timeout { fail "(timeout) print value of US" } + } + + +send_gdb "ptype US\n" +gdb_expect { + -re "type = unsigned short.*$gdb_prompt $" { pass "ptype US" } + -re "type = short unsigned.*$gdb_prompt $" { pass "ptype US" } + -re ".*$gdb_prompt $" { fail "ptype US" } + timeout { fail "(timeout) ptype US" } +} + + +send_gdb "print I\n" +gdb_expect { + -re ".\[0-9\]* = 102.*$gdb_prompt $" { + pass "print value of I" + } + -re ".*$gdb_prompt $" { fail "print value of I" } + timeout { fail "(timeout) print value of I" } + } + + +send_gdb "ptype I\n" +gdb_expect { + -re "type = int.*$gdb_prompt $" { pass "ptype I" } + -re ".*$gdb_prompt $" { fail "ptype I" } + timeout { fail "(timeout) ptype I" } +} + + +send_gdb "print UI\n" +gdb_expect { + -re ".\[0-9\]* = 1002.*$gdb_prompt $" { + pass "print value of UI" + } + -re ".*$gdb_prompt $" { fail "print value of UI" } + timeout { fail "(timeout) print value of UI" } + } + + +send_gdb "ptype UI\n" +gdb_expect { + -re "type = unsigned int.*$gdb_prompt $" { pass "ptype UI" } + -re ".*$gdb_prompt $" { fail "ptype UI" } + timeout { fail "(timeout) ptype UI" } +} + + +send_gdb "print L\n" +gdb_expect { + -re ".\[0-9\]* = -234.*$gdb_prompt $" { + pass "print value of L" + } + -re ".*$gdb_prompt $" { fail "print value of L" } + timeout { fail "(timeout) print value of L" } + } + + +send_gdb "ptype L\n" +gdb_expect { + -re "type = long.*$gdb_prompt $" { pass "ptype L" } + -re ".*$gdb_prompt $" { fail "ptype L" } + timeout { fail "(timeout) ptype L" } +} + + +send_gdb "print UL\n" +gdb_expect { + -re ".\[0-9\]* = 234.*$gdb_prompt $" { + pass "print value of UL" + } + -re ".*$gdb_prompt $" { fail "print value of UL" } + timeout { fail "(timeout) print value of UL" } + } + + +send_gdb "ptype UL\n" +gdb_expect { + -re "type = unsigned long.*$gdb_prompt $" { pass "ptype UL" } + -re "type = long unsigned.*$gdb_prompt $" { pass "ptype UL" } + -re ".*$gdb_prompt $" { fail "ptype UL" } + timeout { fail "(timeout) ptype UL" } +} + + +send_gdb "print F\n" +gdb_expect { + -re ".\[0-9\]* = 1.2\[0-9\]*e\\+10.*$gdb_prompt $" { + pass "print value of F" + } + -re ".*$gdb_prompt $" { fail "print value of F" } + timeout { fail "(timeout) print value of F" } + } + + + +send_gdb "ptype F\n" +gdb_expect { + -re "type = float.*$gdb_prompt $" { pass "ptype F" } + -re ".*$gdb_prompt $" { fail "ptype F" } + timeout { fail "(timeout) ptype F" } +} + + +send_gdb "print D\n" +gdb_expect { + -re ".\[0-9\]* = -1.375e-123.*$gdb_prompt $" { + pass "print value of D" + } + -re ".*$gdb_prompt $" { fail "print value of D" } + timeout { fail "(timeout) print value of D" } + } + + +send_gdb "ptype D\n" +gdb_expect { + -re "type = double.*$gdb_prompt $" { pass "ptype D" } + -re ".*$gdb_prompt $" { fail "ptype D" } + timeout { fail "(timeout) ptype D" } +} + + + +# +# test reference types +# + + + + +send_gdb "ptype rC\n" +gdb_expect { + -re "type = char &.*$gdb_prompt $" { pass "ptype rC" } + -re ".*$gdb_prompt $" { fail "ptype rC" } + timeout { fail "(timeout) ptype rC" } +} + + + + +send_gdb "ptype rUC\n" +gdb_expect { + -re "type = unsigned char &.*$gdb_prompt $" { pass "ptype rUC" } + -re ".*$gdb_prompt $" { fail "ptype rUC" } + timeout { fail "(timeout) ptype rUC" } +} + + + +send_gdb "ptype rS\n" +gdb_expect { + -re "type = short &.*$gdb_prompt $" { pass "ptype rS" } + -re "type = short int &.*$gdb_prompt $" { pass "ptype rS" } + -re ".*$gdb_prompt $" { fail "ptype rS" } + timeout { fail "(timeout) ptype rS" } +} + + + +send_gdb "ptype rUS\n" +gdb_expect { + -re "type = unsigned short &.*$gdb_prompt $" { pass "ptype rUS" } + -re "type = short unsigned int &.*$gdb_prompt $" { pass "ptype rUS" } + -re ".*$gdb_prompt $" { fail "ptype rUS" } + timeout { fail "(timeout) ptype rUS" } +} + + +send_gdb "ptype rI\n" +gdb_expect { + -re "type = int &.*$gdb_prompt $" { pass "ptype rI" } + -re ".*$gdb_prompt $" { fail "ptype rI" } + timeout { fail "(timeout) ptype rI" } +} + + + +send_gdb "ptype rUI\n" +gdb_expect { + -re "type = unsigned int &.*$gdb_prompt $" { pass "ptype rUI" } + -re ".*$gdb_prompt $" { fail "ptype rUI" } + timeout { fail "(timeout) ptype rUI" } +} + + + +send_gdb "ptype rL\n" +gdb_expect { + -re "type = long &.*$gdb_prompt $" { pass "ptype rL" } + -re "type = long int &.*$gdb_prompt $" { pass "ptype rL" } + -re ".*$gdb_prompt $" { fail "ptype rL" } + timeout { fail "(timeout) ptype rL" } +} + + +send_gdb "ptype rUL\n" +gdb_expect { + -re "type = unsigned long &.*$gdb_prompt $" { pass "ptype rUL" } + -re "type = long unsigned int &.*$gdb_prompt $" { pass "ptype rUL" } + -re ".*$gdb_prompt $" { fail "ptype rUL" } + timeout { fail "(timeout) ptype rUL" } +} + + +send_gdb "ptype rF\n" +gdb_expect { + -re "type = float &.*$gdb_prompt $" { pass "ptype rF" } + -re ".*$gdb_prompt $" { fail "ptype rF" } + timeout { fail "(timeout) ptype rF" } +} + + +send_gdb "ptype rD\n" +gdb_expect { + -re "type = double &.*$gdb_prompt $" { pass "ptype rD" } + -re ".*$gdb_prompt $" { fail "ptype rD" } + timeout { fail "(timeout) ptype rD" } +} + + +send_gdb "print rC\n" +gdb_expect { + -re ".\[0-9\]* = \\(char &\\) @$hex: 65 \'A\'.*$gdb_prompt $" { + pass "print value of rC" + } + -re ".*$gdb_prompt $" { fail "print value of rC" } + timeout { fail "(timeout) print value of rC" } + } + + +send_gdb "print rUC\n" +gdb_expect { + -re ".\[0-9\]* = \\(unsigned char &\\) @$hex: 21 \'.025\'.*$gdb_prompt $" { + pass "print value of rUC" + } + -re ".*$gdb_prompt $" { fail "print value of rUC" } + timeout { fail "(timeout) print value of rUC" } + } + + +send_gdb "print rS\n" +gdb_expect { + -re ".\[0-9\]* = \\(short &\\) @$hex: -14.*$gdb_prompt $" { + pass "print value of rS" + } + -re ".\[0-9\]* = \\(short int &\\) @$hex: -14.*$gdb_prompt $" { + pass "print value of rS" + } + -re ".*$gdb_prompt $" { fail "print value of rS" } + timeout { fail "(timeout) print value of rS" } + } + + +send_gdb "print rUS\n" +gdb_expect { + -re ".\[0-9\]* = \\(unsigned short &\\) @$hex: 7.*$gdb_prompt $" { + pass "print value of rUS" + } + -re ".\[0-9\]* = \\(short unsigned int &\\) @$hex: 7.*$gdb_prompt $" { + pass "print value of rUS" + } + -re ".*$gdb_prompt $" { fail "print value of rUS" } + timeout { fail "(timeout) print value of rUS" } + } + + +send_gdb "print rI\n" +gdb_expect { + -re ".\[0-9\]* = \\(int &\\) @$hex: 102.*$gdb_prompt $" { + pass "print value of rI" + } + -re ".*$gdb_prompt $" { fail "print value of rI" } + timeout { fail "(timeout) print value of rI" } + } + + +send_gdb "print rUI\n" +gdb_expect { + -re ".\[0-9\]* = \\(unsigned int &\\) @$hex: 1002.*$gdb_prompt $" { + pass "print value of UI" + } + -re ".*$gdb_prompt $" { fail "print value of rUI" } + timeout { fail "(timeout) print value of rUI" } + } + + +send_gdb "print rL\n" +gdb_expect { + -re ".\[0-9\]* = \\(long &\\) @$hex: -234.*$gdb_prompt $" { + pass "print value of rL" + } + -re ".\[0-9\]* = \\(long int &\\) @$hex: -234.*$gdb_prompt $" { + pass "print value of rL" + } + -re ".*$gdb_prompt $" { fail "print value of rL" } + timeout { fail "(timeout) print value of rL" } + } + + + +send_gdb "print rUL\n" +gdb_expect { + -re ".\[0-9\]* = \\(unsigned long &\\) @$hex: 234.*$gdb_prompt $" { + pass "print value of rUL" + } + -re ".\[0-9\]* = \\(long unsigned int &\\) @$hex: 234.*$gdb_prompt $" { + pass "print value of rUL" + } + -re ".*$gdb_prompt $" { fail "print value of rUL" } + timeout { fail "(timeout) print value of rUL" } + } + + +send_gdb "print rF\n" +gdb_expect { + -re ".\[0-9\]* = \\(float &\\) @$hex: 1.2\[0-9\]*e\\+10.*$gdb_prompt $" { + pass "print value of rF" + } + -re ".*$gdb_prompt $" { fail "print value of rF" } + timeout { fail "(timeout) print value of rF" } + } + + +send_gdb "print rD\n" +gdb_expect { + -re ".\[0-9\]* = \\(double &\\) @$hex: -1.375e-123.*$gdb_prompt $" { + pass "print value of rD" + } + -re ".*$gdb_prompt $" { fail "print value of rD" } + timeout { fail "(timeout) print value of rD" } + } + diff --git a/gdb/testsuite/gdb.cp/rtti.exp b/gdb/testsuite/gdb.cp/rtti.exp new file mode 100644 index 0000000..6177f80 --- /dev/null +++ b/gdb/testsuite/gdb.cp/rtti.exp @@ -0,0 +1,137 @@ +# Copyright 2003 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# This file is part of the gdb testsuite. + +# This contains tests for GDB's use of RTTI information. This stems +# from a bug reported in PR gdb/488 and other places, which leads to +# statements like 'warning: can't find class named 'C::D', as given by +# C++ RTTI'. It arises from GDB not knowing about classes that are +# defined in namespaces. + +# NOTE: carlton/2003-05-16: I suspect it could arise from nested class +# issues, too, and even once we fix that, there might be situations +# (involving templates, in particular) where this problem triggers +# because GDB and GCC have different ideas what a class is called. + +if $tracelevel then { + strace $tracelevel + } + +if { [skip_cplus_tests] } { continue } + +# +# test running programs +# +set prms_id 0 +set bug_id 0 + +set testfile "rtti" +set srcfile1 "${srcdir}/${subdir}/${testfile}1.cc" +set objfile1 "${objdir}/${subdir}/${testfile}1.o" +set srcfile2 "${srcdir}/${subdir}/${testfile}2.cc" +set objfile2 "${objdir}/${subdir}/${testfile}2.o" +set binfile ${objdir}/${subdir}/${testfile} + +# gdb_get_line_number needs this to be called srcfile. +set srcfile "${srcfile1}" + +if { [gdb_compile "${srcfile1}" "${objfile1}" object {debug c++}] != "" } { + gdb_suppress_entire_file "Testcase compile failed, so all tests in this file will automatically fail." +} + +if { [gdb_compile "${srcfile2}" "${objfile2}" object {debug c++}] != "" } { + gdb_suppress_entire_file "Testcase compile failed, so all tests in this file will automatically fail." +} + +if { [gdb_compile "${objfile1} ${objfile2}" "${binfile}" executable {debug c++}] != "" } { + gdb_suppress_entire_file "Testcase compile failed, so all tests in this file will automatically fail." +} + +if [get_compiler_info ${binfile} "c++"] { + return -1 +} + +gdb_exit +gdb_start +gdb_reinitialize_dir $srcdir/$subdir +gdb_load ${binfile} + + +if ![runto_main] then { + perror "couldn't run to breakpoint" + continue +} + +# First, run to after we've constructed the object: + +gdb_breakpoint [gdb_get_line_number "constructs-done"] +gdb_continue_to_breakpoint "end of constructors" + +gdb_test_multiple "print *e1" "print *e1" { + -re "warning: RTTI symbol not found for class 'n1::D1'.*$gdb_prompt $" { + # gdb HEAD 2003-12-05 + kfail "gdb/488" "print *e1" + } + -re "warning: can't find class named `n1::D1', as given by C\\+\\+ RTTI.*$gdb_prompt $" { + # gdb 6.0 + kfail "gdb/488" "print *e1" + } + -re "\\$\[0-9\]* = { = .*}\r\n$gdb_prompt $" { + pass "print *e1" + } + -re "\\$\[0-9\]* = { = .*}\r\n$gdb_prompt $" { + # NOTE: carlton/2003-05-16: If code is compiled by GCC2, we + # don't print the warning (for no particular reason), but we + # still call the class via the wrong name; PR gdb/57 is our + # catch-all PR for nested type problems. + kfail "gdb/57" "print *e1" + } +} + +# NOTE: carlton/2003-05-16: This test fails on my branch with an +# "" message because, within rtt1.cc, GDB has no way +# of knowing that the class is called 'n2::D2' instead of just 'D2'. +# This is an artifical test case, though: if we were using these +# classes in a more substantial way, G++ would emit more debug info. +# As is, I don't think there's anything that GDB can do about this +# case until G++ starts emitting DW_TAG_namespace info; when that part +# of the branch gets merged in, then we'll probably want to convert +# that fail branch to an xfail. + +gdb_test_multiple "print *e2" "print *e2" { + -re "warning: RTTI symbol not found for class 'n2::D2'.*$gdb_prompt $" { + # gdb HEAD 2003-12-05 + kfail "gdb/488" "print *e2" + } + -re "warning: can't find class named `n2::D2', as given by C\\+\\+ RTTI.*$gdb_prompt $" { + # gdb 6.0 + kfail "gdb/488" "print *e2" + } + -re "\\$\[0-9\]* = \r\n$gdb_prompt $" { + # See above NOTE. + fail "print *e2" + } + -re "\\$\[0-9\]* = { = .*}\r\n$gdb_prompt $" { + pass "print *e2" + } + -re "\\$\[0-9\]* = { = .*}\r\n$gdb_prompt $" { + kfail "gdb/57" "print *e2" + } +} + +gdb_exit +return 0 diff --git a/gdb/testsuite/gdb.cp/rtti.h b/gdb/testsuite/gdb.cp/rtti.h new file mode 100644 index 0000000..879896d --- /dev/null +++ b/gdb/testsuite/gdb.cp/rtti.h @@ -0,0 +1,48 @@ +/* Code to go along with tests in rtti.exp. + + Copyright 2003 Free Software Foundation, Inc. + + Contributed by David Carlton and by Kealia, + Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or (at + your option) any later version. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +namespace n2 { + + class C2; + + class Base2 { + public: + virtual ~Base2() { } + }; + + + class C2: public Base2 { + public: + }; + + class D2 : public C2{ + public: + D2(C2 *, C2 *); + + C2* expr_1_; + C2* expr_2_; + }; + + extern C2 *create2(); +} diff --git a/gdb/testsuite/gdb.cp/rtti1.cc b/gdb/testsuite/gdb.cp/rtti1.cc new file mode 100644 index 0000000..6e9d862 --- /dev/null +++ b/gdb/testsuite/gdb.cp/rtti1.cc @@ -0,0 +1,67 @@ +/* Code to go along with tests in rtti.exp. + + Copyright 2003 Free Software Foundation, Inc. + + Contributed by David Carlton and by Kealia, + Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or (at + your option) any later version. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#include "rtti.h" + +namespace n1 { + + class C1; + + class Base1 { + public: + virtual ~Base1() { } + }; + + + class C1: public Base1 { + public: + }; + + class D1 : public C1{ + public: + D1(C1 *, C1 *); + + C1* expr_1_; + C1* expr_2_; + }; + + D1::D1(C1 *expr_1, C1 *expr_2) + : expr_1_(expr_1), expr_2_(expr_2) { } + + C1 *create1() { + return new D1(0, 0); + } + +} // n1 + +int main() +{ + using namespace n1; + using namespace n2; + + C1 *e1 = create1(); + C2 *e2 = create2(); + + return 0; // constructs-done +} diff --git a/gdb/testsuite/gdb.cp/rtti2.cc b/gdb/testsuite/gdb.cp/rtti2.cc new file mode 100644 index 0000000..8bb1ed6 --- /dev/null +++ b/gdb/testsuite/gdb.cp/rtti2.cc @@ -0,0 +1,36 @@ +/* Code to go along with tests in rtti.exp. + + Copyright 2003 Free Software Foundation, Inc. + + Contributed by David Carlton and by Kealia, + Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or (at + your option) any later version. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#include "rtti.h" + +namespace n2 { + + D2::D2(C2 *expr_1, C2 *expr_2) + : expr_1_(expr_1), expr_2_(expr_2) { } + + C2 *create2() { + return new D2(0, 0); + } + +} diff --git a/gdb/testsuite/gdb.cp/templates.cc b/gdb/testsuite/gdb.cp/templates.cc new file mode 100644 index 0000000..c13f18b --- /dev/null +++ b/gdb/testsuite/gdb.cp/templates.cc @@ -0,0 +1,785 @@ +/* This test code is from Wendell Baker (wbaker@comet.berkeley.edu) */ + +#include + +int a_i; +char a_c; +double a_d; + +typedef void *Pix; + +int +f(int i) +{ return 0; } + +int +f(int i, char c) +{ return 0; } + +int +f(int i, char c, double d) +{ return 0; } + +int +f(int i, char c, double d, char *cs) +{ return 0; } + +int +f(int i, char c, double d, char *cs, void (*fig)(int, char)) +{ return 0; } + +int +f(int i, char c, double d, char *cs, void (*fig)(char, int)) +{ return 0; } + +class R { +public: + int i; +}; +class S { +public: + int i; +}; +class T { +public: + int i; +}; + +char g(char, const char, volatile char) +{ return 'c'; } +char g(R, char&, const char&, volatile char&) +{ return 'c'; } +char g(char*, const char*, volatile char*) +{ return 'c'; } +char g(S, char*&, const char*&, volatile char*&) +{ return 'c'; } + +signed char g(T,signed char, const signed char, volatile signed char) +{ return 'c'; } +signed char g(T, R, signed char&, const signed char&, volatile signed char&) +{ return 'c'; } +signed char g(T, signed char*, const signed char*, volatile signed char*) +{ return 'c'; } +signed char g(T, S, signed char*&, const signed char*&, volatile signed char*&) +{ return 'c'; } + +unsigned char g(unsigned char, const unsigned char, volatile unsigned char) +{ return 'c'; } +unsigned char g(R, unsigned char&, const unsigned char&, volatile unsigned char&) +{ return 'c'; } +unsigned char g(unsigned char*, const unsigned char*, volatile unsigned char*) +{ return 'c'; } +unsigned char g(S, unsigned char*&, const unsigned char*&, volatile unsigned char*&) +{ return 'c'; } + +short g(short, const short, volatile short) +{ return 0; } +short g(R, short&, const short&, volatile short&) +{ return 0; } +short g(short*, const short*, volatile short*) +{ return 0; } +short g(S, short*&, const short*&, volatile short*&) +{ return 0; } + +signed short g(T, signed short, const signed short, volatile signed short) +{ return 0; } +signed short g(T, R, signed short&, const signed short&, volatile signed short&) +{ return 0; } +signed short g(T, signed short*, const signed short*, volatile signed short*) +{ return 0; } +signed short g(T, S, double, signed short*&, const signed short*&, volatile signed short*&) +{ return 0; } + +unsigned short g(unsigned short, const unsigned short, volatile unsigned short) +{ return 0; } +unsigned short g(R, unsigned short&, const unsigned short&, volatile unsigned short&) +{ return 0; } +unsigned short g(unsigned short*, const unsigned short*, volatile unsigned short*) +{ return 0; } +unsigned short g(S, unsigned short*&, const unsigned short*&, volatile unsigned short*&) +{ return 0; } + +int g(int, const int, volatile int) +{ return 0; } +int g(R, int&, const int&, volatile int&) +{ return 0; } +int g(int*, const int*, volatile int*) +{ return 0; } +int g(S, int*&, const int*&, volatile int*&) +{ return 0; } + +signed int g(T, signed int, const signed int, volatile signed int) +{ return 0; } +signed int g(T, R, signed int&, const signed int&, volatile signed int&) +{ return 0; } +signed int g(T, signed int*, const signed int*, volatile signed int*) +{ return 0; } +signed int g(T, S, signed int*&, const signed int*&, volatile signed int*&) +{ return 0; } + +unsigned int g(unsigned int, const unsigned int, volatile unsigned int) +{ return 0; } +unsigned int g(R, unsigned int&, const unsigned int&, volatile unsigned int&) +{ return 0; } +unsigned int g(unsigned int*, const unsigned int*, volatile unsigned int*) +{ return 0; } +unsigned int g(S, unsigned int*&, const unsigned int*&, volatile unsigned int*&) +{ return 0; } + +long g(long, const long, volatile long) +{ return 0; } +long g(R, long&, const long&, volatile long&) +{ return 0; } +long g(long*, const long*, volatile long*) +{ return 0; } +long g(S, long*&, const long*&, volatile long*&) +{ return 0; } + +signed long g(T, signed long, const signed long, volatile signed long) +{ return 0; } +signed long g(T, R, signed long&, const signed long&, volatile signed long&) +{ return 0; } +signed long g(T, signed long*, const signed long*, volatile signed long*) +{ return 0; } +signed long g(T, S, signed long*&, const signed long*&, volatile signed long*&) +{ return 0; } + +unsigned long g(unsigned long, const unsigned long, volatile unsigned long) +{ return 0; } +unsigned long g(S, unsigned long&, const unsigned long&, volatile unsigned long&) +{ return 0; } +unsigned long g(unsigned long*, const unsigned long*, volatile unsigned long*) +{ return 0; } +unsigned long g(S, unsigned long*&, const unsigned long*&, volatile unsigned long*&) +{ return 0; } + +#ifdef __GNUC__ +long long g(long long, const long long, volatile long long) +{ return 0; } +long long g(S, long long&, const long long&, volatile long long&) +{ return 0; } +long long g(long long*, const long long*, volatile long long*) +{ return 0; } +long long g(R, long long*&, const long long*&, volatile long long*&) +{ return 0; } + +signed long long g(T, signed long long, const signed long long, volatile signed long long) +{ return 0; } +signed long long g(T, R, signed long long&, const signed long long&, volatile signed long long&) +{ return 0; } +signed long long g(T, signed long long*, const signed long long*, volatile signed long long*) +{ return 0; } +signed long long g(T, S, signed long long*&, const signed long long*&, volatile signed long long*&) +{ return 0; } + +unsigned long long g(unsigned long long, const unsigned long long, volatile unsigned long long) +{ return 0; } +unsigned long long g(R, unsigned long long*, const unsigned long long*, volatile unsigned long long*) +{ return 0; } +unsigned long long g(unsigned long long&, const unsigned long long&, volatile unsigned long long&) +{ return 0; } +unsigned long long g(S, unsigned long long*&, const unsigned long long*&, volatile unsigned long long*&) +{ return 0; } +#endif + +float g(float, const float, volatile float) +{ return 0; } +float g(char, float&, const float&, volatile float&) +{ return 0; } +float g(float*, const float*, volatile float*) +{ return 0; } +float g(char, float*&, const float*&, volatile float*&) +{ return 0; } + +double g(double, const double, volatile double) +{ return 0; } +double g(char, double&, const double&, volatile double&) +{ return 0; } +double g(double*, const double*, volatile double*) +{ return 0; } +double g(char, double*&, const double*&, volatile double*&) +{ return 0; } + +#ifdef __GNUC__ +long double g(long double, const long double, volatile long double) +{ return 0; } +long double g(char, long double&, const long double&, volatile long double&) +{ return 0; } +long double g(long double*, const long double*, volatile long double*) +{ return 0; } +long double g(char, long double*&, const long double*&, volatile long double*&) +{ return 0; } +#endif + +class c { +public: + c(int) {}; + int i; +}; + +class c g(c, const c, volatile c) +{ return 0; } +c g(char, c&, const c&, volatile c&) +{ return 0; } +c g(c*, const c*, volatile c*) +{ return 0; } +c g(char, c*&, const c*&, volatile c*&) +{ return 0; } + +/* +void h(char = 'a') +{ } +void h(char, signed char = 'a') +{ } +void h(unsigned char = 'a') +{ } +*/ +/* +void h(char = (char)'a') +{ } +void h(char, signed char = (signed char)'a') +{ } +void h(unsigned char = (unsigned char)'a') +{ } + + +void h(short = (short)43) +{ } +void h(char, signed short = (signed short)43) +{ } +void h(unsigned short = (unsigned short)43) +{ } + +void h(int = (int)43) +{ } +void h(char, signed int = (signed int)43) +{ } +void h(unsigned int = (unsigned int)43) +{ } + + +void h(long = (long)43) +{ } +void h(char, signed long = (signed long)43) +{ } +void h(unsigned long = (unsigned long)43) +{ } + +#ifdef __GNUC__ +void h(long long = 43) +{ } +void h(char, signed long long = 43) +{ } +void h(unsigned long long = 43) +{ } +#endif + +void h(float = 4.3e-10) +{ } +void h(double = 4.3) +{ } +#ifdef __GNUC__ +void h(long double = 4.33e33) +{ } +#endif +*/ + +/* An unneeded printf() definition - actually, just a stub - used to occupy + this space. It has been removed and replaced with this comment which + exists to occupy some lines so that templates.exp won't need adjustment. */ + +class T1 { +public: + static void* operator new(size_t) throw (); + static void operator delete(void *pointer); + + void operator=(const T1&); + T1& operator=(int); + + int operator==(int) const; + int operator==(const T1&) const; + int operator!=(int) const; + int operator!=(const T1&) const; + + int operator<=(int) const; + int operator<=(const T1&) const; + int operator<(int) const; + int operator<(const T1&) const; + int operator>=(int) const; + int operator>=(const T1&) const; + int operator>(int) const; + int operator>(const T1&) const; + + void operator+(int) const; + T1& operator+(const T1&) const; + void operator+=(int) const; + T1& operator+=(const T1&) const; + + T1& operator++() const; + + void operator-(int) const; + T1& operator-(const T1&) const; + void operator-=(int) const; + T1& operator-=(const T1&) const; + + T1& operator--() const; + + void operator*(int) const; + T1& operator*(const T1&) const; + void operator*=(int) const; + T1& operator*=(const T1&) const; + + void operator/(int) const; + T1& operator/(const T1&) const; + void operator/=(int) const; + T1& operator/=(const T1&) const; + + void operator%(int) const; + T1& operator%(const T1&) const; + void operator%=(int) const; + T1& operator%=(const T1&) const; + + void operator&&(int) const; + T1& operator&&(const T1&) const; + + void operator||(int) const; + T1& operator||(const T1&) const; + + void operator&(int) const; + T1& operator&(const T1&) const; + void operator&=(int) const; + T1& operator&=(const T1&) const; + + void operator|(int) const; + T1& operator|(const T1&) const; + void operator|=(int) const; + T1& operator|=(const T1&) const; + + void operator^(int) const; + T1& operator^(const T1&) const; + void operator^=(int) const; + T1& operator^=(const T1&) const; + + T1& operator!() const; + T1& operator~() const; +}; + +void* +T1::operator new(size_t) throw () +{ return 0; } + +void +T1::operator delete(void *pointer) +{ } + +class T2 { +public: + T2(int i): integer(i) + { } + int integer; +}; + +int operator==(const T2&, const T2&) +{ return 0; } +int operator==(const T2&, char) +{ return 0; } +int operator!=(const T2&, const T2&) +{ return 0; } +int operator!=(const T2&, char) +{ return 0; } + +int operator<=(const T2&, const T2&) +{ return 0; } +int operator<=(const T2&, char) +{ return 0; } +int operator<(const T2&, const T2&) +{ return 0; } +int operator<(const T2&, char) +{ return 0; } +int operator>=(const T2&, const T2&) +{ return 0; } +int operator>=(const T2&, char) +{ return 0; } +int operator>(const T2&, const T2&) +{ return 0; } +int operator>(const T2&, char) +{ return 0; } + +T2 operator+(const T2 t, int i) +{ return t.integer + i; } +T2 operator+(const T2 a, const T2& b) +{ return a.integer + b.integer; } +T2& operator+=(T2& t, int i) +{ t.integer += i; return t; } +T2& operator+=(T2& a, const T2& b) +{ a.integer += b.integer; return a; } + +T2 operator-(const T2 t, int i) +{ return t.integer - i; } +T2 operator-(const T2 a, const T2& b) +{ return a.integer - b.integer; } +T2& operator-=(T2& t, int i) +{ t.integer -= i; return t; } +T2& operator-=(T2& a, const T2& b) +{ a.integer -= b.integer; return a; } + +T2 operator*(const T2 t, int i) +{ return t.integer * i; } +T2 operator*(const T2 a, const T2& b) +{ return a.integer * b.integer; } +T2& operator*=(T2& t, int i) +{ t.integer *= i; return t; } +T2& operator*=(T2& a, const T2& b) +{ a.integer *= b.integer; return a; } + +T2 operator/(const T2 t, int i) +{ return t.integer / i; } +T2 operator/(const T2 a, const T2& b) +{ return a.integer / b.integer; } +T2& operator/=(T2& t, int i) +{ t.integer /= i; return t; } +T2& operator/=(T2& a, const T2& b) +{ a.integer /= b.integer; return a; } + +T2 operator%(const T2 t, int i) +{ return t.integer % i; } +T2 operator%(const T2 a, const T2& b) +{ return a.integer % b.integer; } +T2& operator%=(T2& t, int i) +{ t.integer %= i; return t; } +T2& operator%=(T2& a, const T2& b) +{ a.integer %= b.integer; return a; } + +template +class T5 { +public: + T5(int); + T5(const T5&); + ~T5(); + static void* operator new(size_t) throw (); + static void operator delete(void *pointer); + int value(); + + static T X; + T x; + int val; +}; + +template +T5::T5(int v) +{ val = v; } + +template +T5::T5(const T5&) +{} + +template +T5::~T5() +{} + +template +void* +T5::operator new(size_t) throw () +{ return 0; } + +template +void +T5::operator delete(void *pointer) +{ } + +template +int +T5::value() +{ return val; } + + +#if ! defined(__GNUC__) || defined(GCC_BUG) +template +T T5::X; +#endif + + + + +T5 t5c(1); +T5 t5i(2); +T5 t5fi1(3); +T5 t5fi2(4); + + + + + + +class x { +public: + int (*manage[5])(double, + void *(*malloc)(unsigned size), + void (*free)(void *pointer)); + int (*device[5])(int open(const char *, unsigned mode, unsigned perms, int extra), + int *(*read)(int fd, void *place, unsigned size), + int *(*write)(int fd, void *place, unsigned size), + void (*close)(int fd)); +}; +T5 t5x(5); + +#if !defined(__GNUC__) || (__GNUC__ > 2) || (__GNUC__ == 2 && __GNUC_MINOR__ >= 6) +template class T5; +template class T5; +template class T5; +template class T5; +template class T5; +#endif + +class T7 { +public: + static int get(); + static void put(int); +}; + +int +T7::get() +{ return 1; } + +void +T7::put(int i) +{ + // nothing +} + +// More template kinds. GDB 4.16 didn't handle these, but +// Wildebeest does. Note: Assuming HP aCC is used to compile +// this file; with g++ or HP cfront or other compilers the +// demangling may not get done correctly. + +// Ordinary template, to be instantiated with different types +template +class Foo { +public: + int x; + T t; + T foo (int, T); +}; + + +template T Foo::foo (int i, T tt) +{ + return tt; +} + +// Template with int parameter + +template +class Bar { +public: + int x; + T t; + T bar (int, T); +}; + + +template T Bar::bar (int i, T tt) +{ + if (i < sz) + return tt; + else + return 0; +} + +// function template with int parameter +template int dummy (T tt, int i) +{ + return tt; +} + +// Template with partial specializations +template +class Spec { +public: + int x; + T1 spec (T2); +}; + +template +T1 Spec::spec (T2 t2) +{ + return 0; +} + +template +class Spec { +public: + int x; + T spec (T*); +}; + +template +T Spec::spec (T * tp) +{ + return *tp; +} + +// Template with char parameter +template +class Baz { +public: + int x; + T t; + T baz (int, T); +}; + +template T Baz::baz (int i, T tt) +{ + if (i < sz) + return tt; + else + return 0; +} + +// Template with char * parameter +template +class Qux { +public: + int x; + T t; + T qux (int, T); +}; + +template T Qux::qux (int i, T tt) +{ + if (sz[0] == 'q') + return tt; + else + return 0; +} + +// Template with a function pointer parameter +template +class Qux1 { +public: + int x; + T t; + T qux (int, T); +}; + +template T Qux1::qux (int i, T tt) +{ + if (f != 0) + return tt; + else + return 0; +} + +// Some functions to provide as arguments to template +int gf1 (int a) { + return a * 2 + 13; +} +int gf2 (int a) { + return a * 2 + 26; +} + +char string[3]; + + +// Template for nested instantiations + +template +class Garply { +public: + int x; + T t; + T garply (int, T); +}; + +template T Garply::garply (int i, T tt) +{ + if (i > x) + return tt; + else + { + x += i; + return tt; + } +} + + +int main() +{ + int i; +#ifdef usestubs + set_debug_traps(); + breakpoint(); +#endif + i = i + 1; + + // New tests added here + + Foo fint={0,0}; + Foo fchar={0,0}; + Foo fvpchar = {0, 0}; + + Bar bint; + Bar 3)> bint2; + + Baz bazint; + Baz bazint2; + + Qux quxint2; + Qux quxint; + + Qux1 qux11; + + int x = fint.foo(33, 47); + char c = fchar.foo(33, 'x'); + volatile char * cp = fvpchar.foo(33, 0); + + int y = dummy (400, 600); + + int z = bint.bar(55, 66); + z += bint2.bar(55, 66); + + c = bazint2.baz(4, 'y'); + c = quxint2.qux(4, 'z'); + + y = bazint.baz(4,3); + y = quxint.qux(4, 22); + y += qux11.qux(4, 22); + + y *= gf1(y) - gf2(y); + + Spec sic; + Spec siip; + + sic.spec ('c'); + siip.spec (&x); + + Garply f; + Garply fc; + f.x = 13; + + Garply > nf; + nf.x = 31; + + x = f.garply (3, 4); + + fc = nf.garply (3, fc); + + y = x + fc.x; + + + return 0; + +} + + + + + + + + + + + + + diff --git a/gdb/testsuite/gdb.cp/templates.exp b/gdb/testsuite/gdb.cp/templates.exp new file mode 100644 index 0000000..68c5cdf --- /dev/null +++ b/gdb/testsuite/gdb.cp/templates.exp @@ -0,0 +1,516 @@ +# Copyright 1992, 1994, 1995, 1996, 1997, 1999, 2000, 2002, 2003 +# Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# Please email any bugs, comments, and/or additions to this file to: +# bug-gdb@prep.ai.mit.edu + +# This file was written by Fred Fish. (fnf@cygnus.com) + +set ws "\[\r\n\t \]+" + +if $tracelevel then { + strace $tracelevel +} + +if { [skip_cplus_tests] } { continue } + +set testfile "templates" +set srcfile ${testfile}.cc +set binfile ${objdir}/${subdir}/${testfile} + +# Create and source the file that provides information about the compiler +# used to compile the test case. +if [get_compiler_info ${binfile} "c++"] { + return -1 +} +source ${binfile}.ci + +if { [gdb_compile "${srcdir}/${subdir}/${srcfile}" "${binfile}" executable {debug c++}] != "" } { + gdb_suppress_entire_file "Testcase compile failed, so all tests in this file will automatically fail." +} + +# +# Test printing of the types of templates. +# + +proc test_ptype_of_templates {} { + global gdb_prompt + global ws + + send_gdb "ptype T5\n" + gdb_expect { + -re "type = class T5 \{${ws}public:${ws}static int X;${ws}int x;${ws}int val;${ws}T5 & operator=\\(T5 const ?&\\);${ws}T5\\(int\\);${ws}T5\\((T5 const|const T5) ?&\\);${ws}~T5\\((void|)\\);${ws}static void \\* operator new\\(unsigned( int| long)?\\);${ws}static void operator delete\\(void ?\\*\\);${ws}int value\\((void|)\\);${ws}\}\r\n$gdb_prompt $" { + pass "ptype T5" + } + -re "type = class T5 \\{${ws}public:${ws}static int X;${ws}int x;${ws}int val;${ws}${ws}T5 \\(int\\);${ws}T5 \\(const class T5 &\\);${ws}void ~T5 \\(int\\);${ws}static void \\* new \\(unsigned int\\);${ws}static void delete \\(void ?\\*\\);${ws}int value \\((void|)\\);${ws}\\}${ws}$gdb_prompt $" { pass "ptype T5 -- new with unsigned int" } + -re "type = class T5 \\{.*public:.*static int X;.*int x;.*int val;.*T5 \\(int\\);.*T5 \\(const class T5 &\\);.*void ~T5 \\(int\\);.*static void \\* new \\(unsigned long\\);.*static void delete \\(void ?\\*\\);.*int value \\((void|)\\);.*\\}\r\n$gdb_prompt $" { pass "ptype T5 -- new with unsigned long" } + -re "type = class T5 \{${ws}public:${ws}static int X;${ws}int x;${ws}int val;((${ws}T5 & operator=\\(T5 const ?&\\);)|(${ws}T5\\(int\\);)|(${ws}T5\\((T5 const|const T5) ?&\\);)|(${ws}~T5\\((void|)\\);)|(${ws}static void \\* operator new\\(unsigned( int| long)?\\);)|(${ws}static void operator delete\\(void ?\\*\\);)|(${ws}int value\\((void|)\\);))*${ws}\}\r\n$gdb_prompt $" { + pass "ptype T5 (obsolescent gcc or gdb)" + } + -re "type = class T5 \{${ws}public:${ws}static int X;${ws}int x;${ws}int val;${ws}void T5\\(int\\);${ws}void T5\\((T5 const|const T5) ?&\\);${ws}~T5\\(int\\);${ws}static void \\* operator new\\(unsigned( int| long|)\\);${ws}static void operator delete\\(void ?\\*\\);${ws}int value\\((void|)\\);${ws}\}\r\n$gdb_prompt $" { + # This also triggers gdb/1113... + kfail "gdb/1111" "ptype T5" + } + -re ".*$gdb_prompt $" { + fail "ptype T5" + } + timeout { + fail "ptype T5 (timeout)" + } + } + + send_gdb "ptype t5i\n" + gdb_expect { + -re "type = class T5 \\{${ws}public:${ws}static int X;${ws}int x;${ws}int val;\r\n${ws}T5\\(int\\);${ws}T5\\(T5 const ?&\\);${ws}~T5\\((void|)\\);${ws}static void \\* operator new\\(unsigned( int| long)?\\);${ws}static void operator delete\\(void ?\\*\\);${ws}int value\\((void|)\\);${ws}\\}\r\n$gdb_prompt $" { pass "ptype T5 -- with several fixes from 4.17" } + -re "type = class T5 \\{${ws}public:${ws}static int X;${ws}int x;${ws}int val;\r\n${ws}T5 \\(int\\);${ws}T5 \\(const class T5 &\\);${ws}void ~T5 \\(int\\);${ws}static void \\* new \\(unsigned int\\);${ws}static void delete \\(void ?\\*\\);${ws}int value \\((void|)\\);${ws}\\}\r\n$gdb_prompt $" { pass "ptype t5i -- new with unsigned int" } + -re "type = class T5 \\{${ws}public:${ws}static int X;${ws}int x;${ws}int val;\r\n${ws}T5 \\(int\\);${ws}T5 \\(const class T5 &\\);${ws}void ~T5 \\(int\\);${ws}static void \\* new \\(unsigned long\\);${ws}static void delete \\(void ?\\*\\);${ws}int value \\((void|)\\);${ws}\\}\r\n$gdb_prompt $" { pass "ptype t5i -- new with unsigned long" } + -re "type = class T5 \{.*public:.*static int X;.*int x;.*int val;.*.*T5 \\(int\\);.*.*void ~T5 \\(int\\).*.*.*int value \\((void|)\\);.*\}.*$gdb_prompt $" { + pass "ptype t5i" + } + -re "type = class T5 \{${ws}public:${ws}static int X;${ws}int x;${ws}int val;${ws}T5 & operator=\\(T5 const ?&\\);${ws}T5\\(int\\);${ws}T5\\((T5 const|const T5) ?&\\);${ws}~T5\\((void|)\\);${ws}static void \\* operator new\\(unsigned( int| long)?\\);${ws}static void operator delete\\(void ?\\*\\);${ws}int value\\((void|)\\);${ws}\}\r\n$gdb_prompt $" { + pass "ptype t5i" + } + -re "type = class T5 \{${ws}public:${ws}static int X;${ws}int x;${ws}int val;((${ws}T5 & operator=\\(T5 const ?&\\);)|(${ws}T5\\(int\\);)|(${ws}T5\\(T5 const ?&\\);)|(${ws}~T5\\((void|)\\);)|(${ws}static void \\* operator new\\(unsigned( int| long)?\\);)|(${ws}static void operator delete\\(void ?\\*\\);)|(${ws}int value\\((void|)\\);))*${ws}\}\r\n$gdb_prompt $" { + pass "ptype t5i (obsolescent gcc or gdb)" + } + -re "type = class T5 \{${ws}public:${ws}static int X;${ws}int x;${ws}int val;${ws}void T5\\(int\\);${ws}void T5\\((T5 const|const T5) ?&\\);${ws}~T5\\(int\\);${ws}static void \\* operator new\\(unsigned( int| long|)\\);${ws}static void operator delete\\(void ?\\*\\);${ws}int value\\((void|)\\);${ws}\}\r\n$gdb_prompt $" { + # This also triggers gdb/1113... + kfail "gdb/1111" "ptype T5" + } + -re ".*$gdb_prompt $" { + fail "ptype t5i" + } + timeout { + fail "ptype t5i (timeout)" + } + } +} + +# +# Test breakpoint setting on template methods. +# + +proc test_template_breakpoints {} { + global gdb_prompt + global testfile + global srcdir + global hp_aCC_compiler + + send_gdb "break T5::T5\n" + gdb_expect { + -re "0. cancel.*\[\r\n\]*.1. all.*\[\r\n\]*.2. T5::T5\\(int\\) at .*\[\r\n\]*.3. T5::T5\\((T5 const|const T5) ?&\\) at .*\[\r\n\]*> $" { + gdb_test "0" \ + "canceled" \ + "constructor breakpoint (obsolete format!)" + } + -re ".0. cancel\[\r\n\]*.1. all\[\r\n\]*.2. T5::T5\\((T5 const|const T5) ?&\\) at .*templates.cc:.*\[\r\n\]*.3. T5::T5\\(int\\) at .*templates.cc:.*\[\r\n\]*> $" { + gdb_test "0" \ + "canceled" \ + "constructor breakpoint" + } + -re "0. cancel.*\[\r\n\]*.1. all.*\[\r\n\]*.2. T5 at .*\[\r\n\]*.3. T5 at .*\[\r\n\]*> $" { + setup_kfail "gdb/1062" "*-*-*" + gdb_test "0" \ + "nonsense intended to insure that this test fails" \ + "constructor breakpoint" + } + -re ".*\n> $" { + gdb_test "0" \ + "nonsense intended to insure that this test fails" \ + "constructor breakpoint (bad menu choices)" + } + -re ".*$gdb_prompt $" { fail "constructor breakpoint" } + default { fail "constructor breakpoint (timeout)" } + } + +# See CLLbs14792 + if {$hp_aCC_compiler} {setup_xfail hppa*-*-* CLLbs14792} + + gdb_test_multiple "break T5::~T5" "destructor_breakpoint" { + -re "Breakpoint.*at.* file .*${testfile}.cc, line.*$gdb_prompt $" + { + pass "destructor breakpoint" + } + -re "the class `T5' does not have destructor defined\r\nHint: try 'T5::~T5 or 'T5::~T5\r\n\\(Note leading single quote.\\)\r\n$gdb_prompt $" + { + kfail "gdb/1112" "destructor breakpoint" + } + } + + gdb_test "break T5::value" \ + "Breakpoint.*at.* file .*${testfile}.cc, line.*" \ + "value method breakpoint" + + delete_breakpoints +} + +# +# Test calling of template methods. +# + +proc test_template_calls {} { + global gdb_prompt + global hp_aCC_compiler + + if [target_info exists gdb,cannot_call_functions] { + setup_xfail "*-*-*" 2416 + fail "This target can not call functions" + return + } + + if {!$hp_aCC_compiler} {setup_xfail hppa*-*-*} + send_gdb "print t5i.value()\n" + gdb_expect { + -re ".* = 2\[\r\n\]*$gdb_prompt $" { pass "print t5i.value()" } + -re "Cannot invoke functions on this machine.*$gdb_prompt $" { + fail "print t5i.value()" + } + -re "Cannot resolve .* to any overloaded instance.*$gdb_prompt $" { + setup_xfail hppa*-*-* CLLbs16899 + xfail "print t5i.value" + } + -re ".*$gdb_prompt $" { fail "print t5i.value()" } + timeout { fail "print t5i.value() (timeout)" } + } +} + + +proc do_tests {} { + global prms_id + global bug_id + global subdir + global objdir + global srcdir + global binfile + global gdb_prompt + global supports_template_debugging + + set prms_id 0 + set bug_id 0 + + # Start with a fresh gdb. + + gdb_exit + gdb_start + gdb_reinitialize_dir $srcdir/$subdir + gdb_load $binfile + + if { !$supports_template_debugging } { + warning "compiler lacks debugging info for templates; tests suppressed." 0 + return + } + + runto_main + + test_ptype_of_templates + test_template_breakpoints + + if [ runto_main] { + test_template_calls + } +} + +do_tests + + +# More tests for different kinds of template parameters, +# templates with partial specializations, nested templates, etc. +# These have been tested only with HP aCC. They probably won't +# work with other compilers because of differences in mangling +# schemes. +# Added by Satish Pai 1997-09-25 +# As of 2000-06-03, C++ support has been improved to the point that g++ can +# pass all of theses, excluding what appears to be one that exposes a stabs bug. - djb + +# I don't know how HP could be passing these tests without this. They +# weren't breakpointing past a point where the below expressions were +# initialized in the actual source. - djb + +send_gdb "b 770\n" +gdb_expect { + -re ".*$gdb_prompt $" +} +send_gdb "c\n" +gdb_expect { + -re ".*$gdb_prompt $" +} +send_gdb "print fint\n" +gdb_expect { + -re "\\$\[0-9\]* = \\{x = 0, t = 0\\}\r\n$gdb_prompt $" { pass "print fint" } + -re "$gdb_prompt $" { fail "print fint" } + timeout { fail "(timeout) print fint" } +} + +send_gdb "print fvpchar\n" +gdb_expect { + -re "\\$\[0-9\]* = \\{x = 0, t = 0x0\\}\r\n$gdb_prompt $" { pass "print fvpchar" } + -re "$gdb_prompt $" { fail "print fvpchar" } + timeout { fail "(timeout) print fvpchar" } +} + +# Template Foo + +# Neither stabs nor DWARF-2 contains type information about templates +# (as opposed to instantiations of templates), so in those +# circumstances we expect GDB to not find a symbol. HP has a debug +# format that contains more info, though, so it's also correct to +# print out template info. (This affects several subsequent tests as +# well.) + +# NOTE: carlton/2003-02-26: However, because of a bug in the way GDB +# handles nested types, we don't get this right in the DWARF-2 case. + +send_gdb "ptype Foo\n" +gdb_expect { + -re "type = template <(class |)T> (class |)Foo \\{\r\n\[ \t\]*public:\r\n\[ \t\]*int x;\r\n\[ \t\]*T t;\r\n\\}\r\ntemplate instantiations:\r\n\[ \t\]*(class |)Foo\r\n\[ \t\]*(class |)Foo\r\n\[ \t\]*(class |)Foo\r\n$gdb_prompt $" { pass "ptype Foo" } + -re "type = template <(class |)T> (class |)Foo \\{\r\n\[ \t\]*public:\r\n\[ \t\]*int x;\r\n\[ \t\]*T t;\r\n\\}\r\n$gdb_prompt $" { xfail "ptype Foo" } + -re "type = class Foo \\{\r\n\[ \t\]*public:\r\n\[ \t\]*int x;\r\n\[ \t\]*int t;\r\n\r\n\[ \t\]*int foo\\(int, int\\);\r\n\\}\r\n$gdb_prompt $" + { # GCC 3.1, DWARF-2 output. + kfail "gdb/57" "ptype Foo" } + -re "No symbol \"Foo\" in current context.\r\n$gdb_prompt $" + { # GCC 2.95.3, stabs+ output. + pass "ptype Foo" } + -re "$gdb_prompt $" { fail "ptype Foo" } + timeout { fail "(timeout) ptype Foo" } +} +# -re "type = class Foo \\{\r\n\[ \t\]*public:\r\n\[ \t\]*int x;\r\n\[ \t\]*int t;\r\n\r\n\[ \t\]*int foo(int, int);\r\n\\}\r\n$gdb_prompt $" + +# ptype Foo + +send_gdb "ptype fint\n" +gdb_expect { + -re "type = (class |)Foo \\{\r\n\[ \t\]*public:\r\n\[ \t\]*int x;\r\n\[ \t\]*int t;\r\n\r\n\[ \t\]*.*int foo\\(int, int\\);\r\n\\}\r\n$gdb_prompt $" { pass "ptype fint" } + -re "$gdb_prompt $" { fail "ptype fint" } + timeout { fail "(timeout) ptype fint" } +} + +# ptype Foo + +send_gdb "ptype fchar\n" +gdb_expect { + -re "type = (class |)Foo \\{\r\n\[ \t\]*public:\r\n\[ \t\]*int x;\r\n\[ \t\]*char t;\r\n\r\n\[ \t\]*.*char foo\\(int, char\\);\r\n\\}\r\n$gdb_prompt $" { pass "ptype fchar" } + -re "$gdb_prompt $" { fail "ptype fchar" } + timeout { fail "(timeout) ptype fchar" } +} + +# ptype Foo + +send_gdb "ptype fvpchar\n" +gdb_expect { + -re "type = (class |)Foo \\{\r\n\[ \t\]*public:\r\n\[ \t\]*int x;\r\n\[ \t\]*.*char.*\\*t;\r\n\r\n\[ \t\]*.*char \\* foo\\(int,.*char.*\\*\\);\r\n\\}\r\n$gdb_prompt $" { pass "ptype fvpchar" } + -re "$gdb_prompt $" { fail "ptype fvpchar" } + timeout { fail "(timeout) ptype fvpchar" } +} + +# print a function from Foo + +# This test is sensitive to whitespace matching, so we'll do it twice, +# varying the spacing, because of PR gdb/33. + +send_gdb "print Foo::foo\n" +gdb_expect { + -re "\\$\[0-9\]* = \\{.*char \\*\\((class |)Foo \\*(| const), int, .*char \\*\\)\\} $hex ::foo\\(int, .*char.*\\*\\)>\r\n$gdb_prompt $" { pass "print Foo::foo" } + -re "No symbol \"Foo\" in current context.\r\n$gdb_prompt $" + { + # This used to be a kfail gdb/33, but it shouldn't occur any more now. + fail "print Foo::foo" + } + -re "$gdb_prompt $" { fail "print Foo::foo" } + timeout { fail "(timeout) print Foo::foo" } +} + +send_gdb "print Foo::foo\n" +gdb_expect { + -re "\\$\[0-9\]* = \\{.*char \\*\\((class |)Foo \\*(| const), int, .*char \\*\\)\\} $hex ::foo\\(int, .*char.*\\*\\)>\r\n$gdb_prompt $" { pass "print Foo::foo" } + -re "No symbol \"Foo\" in current context.\r\n$gdb_prompt $" + { + # This used to be a kfail gdb/33, but it shouldn't occur any more now. + fail "print Foo::foo" + } + -re "$gdb_prompt $" { fail "print Foo::foo" } + timeout { fail "(timeout) print Foo::foo" } +} + +# Template Bar + +# same as Foo for g++ +send_gdb "ptype Bar\n" +gdb_expect { + -re "type = template <(class |)T, (class |)sz> (class |)Bar \\{\r\n\[ \t\]*public:\r\n\[ \t\]*int x;\r\n\[ \t\]*T t;\r\n\\}\r\ntemplate instantiations:\r\n\[ \t\]*(class |)Bar\r\n\[ \t\]*(class |)Bar\r\n$gdb_prompt $" { pass "ptype Bar" } + -re "type = <(class |)T, (class |)sz> (class |)Bar \\{\r\n\[ \t\]*public:\r\n\[ \t\]*int x;\r\n\[ \t\]*T t;\r\n\\}\r\n$gdb_prompt $" { xfail "ptype Bar" } + -re "ptype Bar\r\ntype = class Bar {\r\n\[ \t\]*public:\r\n\[ \t\]*int x;\r\n\[ \t\]*int t;\r\n\r\n\[ \t\]*int bar\\(int, int\\);\r\n}\r\n$gdb_prompt $" + { # GCC 3.1, DWARF-2 output. + kfail "gdb/57" "ptype Bar" } + -re "No symbol \"Bar\" in current context.\r\n$gdb_prompt $" + { # GCC 2.95.3, stabs+ output. + pass "ptype Bar" } + -re "$gdb_prompt $" { fail "ptype Bar" } + timeout { fail "(timeout) ptype Bar" } +} + + +# ptype Bar + +send_gdb "ptype bint\n" +gdb_expect { + -re "type = (class |)Bar \\{\r\n\[ \t\]*public:\r\n\[ \t\]*int x;\r\n\[ \t\]*int t;\r\n\r\n\[ \t\]*.*int bar\\(int, int\\);\r\n\\}\r\n$gdb_prompt $" { pass "ptype bint" } + -re "$gdb_prompt $" { fail "ptype bint" } + timeout { fail "(timeout) ptype bint" } +} + +# ptype Bar3)> + +send_gdb "ptype bint2\n" +gdb_expect { + -re "type = (class |)Bar \\{\r\n\[ \t\]*public:\r\n\[ \t\]*int x;\r\n\[ \t\]*int t;\r\n\r\n\[ \t\]*.*int bar\\(int, int\\);\r\n\\}\r\n$gdb_prompt $" { pass "ptype bint2" } + -re "$gdb_prompt $" { fail "ptype bint2" } + timeout { fail "(timeout) ptype bint2" } +} + +# Template Baz + +# Same as Foo, for g++ +send_gdb "ptype Baz\n" +gdb_expect { + -re "type = template <(class |)T, (class |)sz> (class |)Baz \\{\r\n\[ \t\]*public:\r\n\[ \t\]*int x;\r\n\[ \t\]*T t;\r\n\\}\r\ntemplate instantiations:\r\n\[ \t\]*(class |)Baz\r\n\[ \t\]*(class |)Baz\r\n$gdb_prompt $" { pass "ptype Baz" } + -re "type = <(class |)T, (class |)sz> (class |)Baz \\{\r\n\[ \t\]*public:\r\n\[ \t\]*int x;\r\n\[ \t\]*T t;\r\n\\}\r\n$gdb_prompt $" { xfail "ptype Baz" } + -re "type = class Baz {\r\n\[ \t\]*public:\r\n\[ \t\]*int x;\r\n\[ \t\]*int t;\r\n\r\n\[ \t\]*int baz\\(int, int\\);\r\n}\r\n$gdb_prompt $" + { # GCC 3.1, DWARF-2 output. + kfail "gdb/57" "ptype Baz" } + -re "No symbol \"Baz\" in current context.\r\n$gdb_prompt $" + { # GCC 2.95.3, stabs+ output. + pass "ptype Baz" } + -re "$gdb_prompt $" { fail "ptype Baz" } + timeout { fail "(timeout) ptype Baz" } +} + + +# ptype Baz + +send_gdb "ptype bazint\n" +gdb_expect { + -re "type = (class |)Baz \\{\r\n\[ \t\]*public:\r\n\[ \t\]*int x;\r\n\[ \t\]*int t;\r\n\r\n\[ \t\]*.*int baz\\(int, int\\);\r\n\\}\r\n$gdb_prompt $" { pass "ptype bazint" } + -re "$gdb_prompt $" { fail "ptype bazint" } + timeout { fail "(timeout) ptype bazint" } +} + +# ptype Baz + +send_gdb "ptype bazint2\n" +gdb_expect { + -re "type = (class |)Baz \\{\r\n\[ \t\]*public:\r\n\[ \t\]*int x;\r\n\[ \t\]*char t;\r\n\r\n\[ \t\]*.*char baz\\(int, char\\);\r\n\\}\r\n$gdb_prompt $" { pass "ptype bazint2" } + -re "$gdb_prompt $" { fail "ptype bazint2" } + timeout { fail "(timeout) ptype bazint2" } +} + +# Template Qux +# Same as Foo for g++ +send_gdb "ptype Qux\n" +gdb_expect { + -re "type = template <(class |)T, (class |)sz> (class |)Qux \\{\r\n\[ \t\]*public:\r\n\[ \t\]*int x;\r\n\[ \t\]*T t;\r\n\\}\r\ntemplate instantiations:\r\n\[ \t\]*(class |)Qux\r\n\[ \t\]*(class |)Qux\r\n$gdb_prompt $" { pass "ptype Qux" } + -re ".*type = template <(class |)T.*, (class |)sz> (class |)Qux \\{\r\n\[ \t\]*public:\r\n\[ \t\]*int x;\r\n\[ \t\]*T t;\r\n\\}.*$gdb_prompt $" { pass "ptype Qux" } + -re "type = class Qux {\r\n\[ \t\]*public:\r\n\[ \t\]*int x;\r\n\[ \t\]*char t;\r\n\r\n\[ \t\]*char qux\\(int, char\\);\r\n}\r\n$gdb_prompt $" + { # GCC 3.1, DWARF-2 output. + kfail "gdb/57" "ptype Qux" } + -re "No symbol \"Qux\" in current context.\r\n$gdb_prompt $" + { # GCC 2.95.3, stabs+ output. + pass "ptype Qux" } + -re "$gdb_prompt $" { fail "ptype Qux" } + timeout { fail "(timeout) ptype Qux" } +} + +# pt Qux + +send_gdb "ptype quxint\n" +gdb_expect { + -re "type = class Qux \\{\r\n\[ \t\]*public:\r\n\[ \t\]*int x;\r\n\[ \t\]*int t;\r\n\r\n\[ \t\]*.*int qux\\(int, int\\);\r\n\\}\r\n$gdb_prompt $" { pass "ptype quxint" } + -re "$gdb_prompt $" { fail "ptype quxint" } + timeout { fail "(timeout) ptype quxint" } +} + +# pt Qux + +# commented out this as quxint2 declaration was commented out in +# templates.exp -- ovidiu +# send_gdb "ptype quxint2\n" +# gdb_expect { +# -re "type = class Qux \\{\r\n\[ \t\]*public:\r\n\[ \t\]*int x;\r\n\[ \t\]*char t;\r\n\r\n\[ \t\]*char qux\\(int, char\\);\r\n\\}\r\n$gdb_prompt $" { pass "ptype quxint2" } +# -re "$gdb_prompt $" { fail "ptype quxint2" } +# timeout { fail "(timeout) ptype quxint2" } +# } + +# Template Spec + +# Same as Foo for g++ +send_gdb "ptype Spec\n" +gdb_expect { + -re "type = template <(class |)T1, (class |)T2> (class |)Spec \\{\r\n\[ \t\]*public:\r\n\[ \t\]*int x;\r\n\\}\r\ntemplate instantiations:\r\n\[ \t\]*(class |)Spec\r\n\[ \t\]*(class |)Spec\r\n$gdb_prompt $" { pass "ptype Spec" } + -re "type = <(class |)T1, (class |)T2> (class |)Spec \\{\r\n\[ \t\]*public:\r\n\[ \t\]*int x;\r\n\\}\r\n$gdb_prompt $" { xfail "ptype Spec" } + -re "type = class Spec {\r\n\[ \t\]*public:\r\n\[ \t\]*int x;\r\n\r\n\[ \t\]*int spec\\(char\\);\r\n}\r\n$gdb_prompt $" + { # GCC 3.1, DWARF-2 output. + kfail "gdb/57" "ptype Spec" } + -re "No symbol \"Spec\" in current context.\r\n$gdb_prompt $" + { # GCC 2.95.3, stabs+ output. + pass "ptype Spec" } + -re "$gdb_prompt $" { fail "ptype Spec" } + timeout { fail "(timeout) ptype Spec" } +} + +# pt Spec + +send_gdb "ptype siip\n" +gdb_expect { + -re "type = class Spec \\{\r\n\[ \t\]*public:\r\n\[ \t\]*int x;\r\n\r\n\[ \t\]*.*int spec\\(int ?\\*\\);\r\n\\}\r\n$gdb_prompt $" { pass "ptype siip" } + -re "$gdb_prompt $" { fail "ptype siip" } + timeout { fail "(timeout) ptype siip" } +} + +# pt Garply + +send_gdb "ptype Garply\n" +gdb_expect { + -re "type = class Garply \\{\r\n\[ \t\]*public:\r\n\[ \t\]*int x;\r\n\[ \t\]*int t;\r\n\r\n\[ \t\]*.*int garply\\(int, int\\);\r\n\\}\r\n$gdb_prompt $" { pass "ptype Garply" } + -re "$gdb_prompt $" { fail "ptype Garply" } + timeout { fail "(timeout) ptype Garply" } +} + +# ptype of nested template name + +send_gdb "ptype Garply >\n" +gdb_expect { + -re "type = (class |)Garply > \\{\r\n\[ \t\]*public:\r\n\[ \t\]*int x;\r\n\[ \t\]*.*(class |)Garply t;\r\n\r\n\[ \t\]*.*(class |)Garply garply\\(int, (class |)Garply\\);\r\n\\}\r\n$gdb_prompt $" { pass "ptype Garply >" } + -re "$gdb_prompt $" { fail "ptype Garply >" } + timeout { fail "(timeout) ptype Garply >" } +} + +# print out a function from a nested template name + +send_gdb "print Garply >::garply\n" +gdb_expect { + -re "\\$\[0-9\]* = \\{(class |)Garply \\((class |)Garply > \\*(| const), int, (class |)Garply\\)\\} $hex \[ \t\]*>::garply\\(int, (class |)Garply\\)>\r\n$gdb_prompt $" { pass "print Garply >::garply" } + -re ".*$gdb_prompt $" { fail "print Garply >::garply" } + timeout { fail "print Garply >::garply (timeout)" } +} + +# djb - 06-03-2000 +# Now should work fine +send_gdb "break Garply >::garply\n" +gdb_expect { + -re "Breakpoint \[0-9\]* at $hex: file .*templates.cc, line.*\r\n$gdb_prompt $" { pass "break Garply >::garply" } + -re ".*$gdb_prompt $" { fail "break Garply >::garply" } + timeout { fail "break Garply >::garply (timeout)" } +} diff --git a/gdb/testsuite/gdb.cp/try_catch.cc b/gdb/testsuite/gdb.cp/try_catch.cc new file mode 100644 index 0000000..e13dd64 --- /dev/null +++ b/gdb/testsuite/gdb.cp/try_catch.cc @@ -0,0 +1,121 @@ +// 2002-05-27 + +#include +#include +#include + +enum region { oriental, egyptian, greek, etruscan, roman }; + +// Test one. +class gnu_obj_1 +{ +public: + typedef region antiquities; + const bool test; + const int key1; + long key2; + + antiquities value; + + gnu_obj_1(antiquities a, long l): test(true), key1(5), key2(l), value(a) {} +}; + +// Test two. +template +class gnu_obj_2: public virtual gnu_obj_1 +{ +public: + antiquities value_derived; + + gnu_obj_2(antiquities b): gnu_obj_1(oriental, 7), value_derived(b) { } +}; + +// Test three. +template +class gnu_obj_3 +{ +public: + typedef region antiquities; + gnu_obj_2 data; + + gnu_obj_3(antiquities b): data(etruscan) { } +}; + +int main() +{ + bool test = true; + const int i = 5; + int j = i; + gnu_obj_2 test2(roman); + gnu_obj_3 test3(greek); + + // 1 + try + { + ++j; + throw gnu_obj_1(egyptian, 4589); // marker 1-throw + } + catch (gnu_obj_1& obj) + { + ++j; + if (obj.value != egyptian) // marker 1-catch + test &= false; + if (obj.key2 != 4589) + test &= false; + } + catch (...) + { + j = 0; + test &= false; + } + + // 2 + try + { + ++j; // marker 2-start + try + { + ++j; // marker 2-next + try + { + ++j; + throw gnu_obj_1(egyptian, 4589); // marker 2-throw + } + catch (gnu_obj_1& obj) + { + ++j; + if (obj.value != egyptian) // marker 2-catch + test &= false; + if (obj.key2 != 4589) + test &= false; + } + } + catch (gnu_obj_1& obj) + { + ++j; + if (obj.value != egyptian) + test &= false; + if (obj.key2 != 4589) + test &= false; + } + } + catch (...) + { + j = 0; + test &= false; + } + + // 3 use standard library + using namespace std; + try + { + if (j < 100) + throw invalid_argument("gdb.1"); // marker 3-throw + } + catch (exception& obj) + { + if (obj.what() != "gdb.1") // marker 3-catch + test &= false; + } + return 0; +} diff --git a/gdb/testsuite/gdb.cp/try_catch.exp b/gdb/testsuite/gdb.cp/try_catch.exp new file mode 100644 index 0000000..1473e20 --- /dev/null +++ b/gdb/testsuite/gdb.cp/try_catch.exp @@ -0,0 +1,82 @@ +# Copyright 2002 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# Tests for member data +# 2002-05-27 Benjamin Kosnik + +# This file is part of the gdb testsuite + +if $tracelevel then { + strace $tracelevel + } + +if { [skip_cplus_tests] } { continue } + +# +# test running programs +# +set prms_id 0 +set bug_id 0 + +set testfile "try_catch" +set srcfile ${testfile}.cc +set binfile ${objdir}/${subdir}/${testfile} + +if { [gdb_compile "${srcdir}/${subdir}/${srcfile}" "${binfile}" executable {debug c++}] != "" } { + gdb_suppress_entire_file "Testcase compile failed, so all tests in this file will automatically fail." +} + +if [get_compiler_info ${binfile} "c++"] { + return -1 +} + +gdb_exit +gdb_start +gdb_reinitialize_dir $srcdir/$subdir +gdb_load ${binfile} + + +if ![runto_main] then { + perror "couldn't run to breakpoint" + continue +} + +gdb_breakpoint [gdb_get_line_number "marker 1-throw"] +gdb_continue_to_breakpoint "marker 1-throw" + +gdb_breakpoint [gdb_get_line_number "marker 1-catch"] +gdb_continue_to_breakpoint "marker 1-catch" + +gdb_breakpoint [gdb_get_line_number "marker 2-start"] +gdb_continue_to_breakpoint "marker 2-start" + +gdb_breakpoint [gdb_get_line_number "marker 2-next"] +gdb_continue_to_breakpoint "marker 2-next" + +gdb_breakpoint [gdb_get_line_number "marker 2-throw"] +gdb_continue_to_breakpoint "marker 2-throw" + +gdb_breakpoint [gdb_get_line_number "marker 2-catch"] +gdb_continue_to_breakpoint "marker 2-catch" + +gdb_breakpoint [gdb_get_line_number "marker 3-throw"] +gdb_continue_to_breakpoint "marker 3-throw" + +gdb_breakpoint [gdb_get_line_number "marker 3-catch"] +gdb_continue_to_breakpoint "marker 3-catch" + +gdb_exit +return 0 diff --git a/gdb/testsuite/gdb.cp/userdef.cc b/gdb/testsuite/gdb.cp/userdef.cc new file mode 100644 index 0000000..0bb88a2 --- /dev/null +++ b/gdb/testsuite/gdb.cp/userdef.cc @@ -0,0 +1,341 @@ +#include + +using namespace std; + +void marker1() +{ + return; +} + +class A1 { + int x; + int y; + +friend ostream& operator<<(ostream& outs, A1 one); + +public: + + A1(int a, int b) + { + x=a; + y=b; + } + +A1 operator+=(int value); +A1 operator+(const A1&); +A1 operator-(const A1&); +A1 operator%(const A1&); +int operator==(const A1&); +int operator!=(const A1&); +int operator&&(const A1&); +int operator||(const A1&); +A1 operator<<(int); +A1 operator>>(int); +A1 operator|(const A1&); +A1 operator^(const A1&); +A1 operator&(const A1&); +int operator<(const A1&); +int operator<=(const A1&); +int operator>=(const A1&); +int operator>(const A1&); +A1 operator*(const A1&); +A1 operator/(const A1&); +A1 operator=(const A1&); + +A1 operator~(); +A1 operator-(); +int operator!(); +A1 operator++(); +A1 operator++(int); +A1 operator--(); +A1 operator--(int); + +}; + + +A1 A1::operator+(const A1& second) +{ + A1 sum(0,0); + sum.x = x + second.x; + sum.y = y + second.y; + + return (sum); +} + +A1 A1::operator*(const A1& second) +{ + A1 product(0,0); + product.x = this->x * second.x; + product.y = this->y * second.y; + + return product; +} + +A1 A1::operator-(const A1& second) +{ + A1 diff(0,0); + diff.x = x - second.x; + diff.y = y - second.y; + + return diff; +} + +A1 A1::operator/(const A1& second) +{ + A1 div(0,0); + div.x = x / second.x; + div.y = y / second.y; + + return div; +} + +A1 A1::operator%(const A1& second) +{ + A1 rem(0,0); + rem.x = x % second.x; + rem.y = y % second.y; + + return rem; +} + +int A1::operator==(const A1& second) +{ + int a = (x == second.x); + int b = (y == second.y); + + return (a && b); +} + +int A1::operator!=(const A1& second) +{ + int a = (x != second.x); + int b = (y != second.y); + + return (a || b); +} + +int A1::operator&&(const A1& second) +{ + return ( x && second.x); +} + +int A1::operator||(const A1& second) +{ + return ( x || second.x); +} + +A1 A1::operator<<(int value) +{ + A1 lshft(0,0); + lshft.x = x << value; + lshft.y = y << value; + + return lshft; +} + +A1 A1::operator>>(int value) +{ + A1 rshft(0,0); + rshft.x = x >> value; + rshft.y = y >> value; + + return rshft; +} + +A1 A1::operator|(const A1& second) +{ + A1 abitor(0,0); + abitor.x = x | second.x; + abitor.y = y | second.y; + + return abitor; +} + +A1 A1::operator^(const A1& second) +{ + A1 axor(0,0); + axor.x = x ^ second.x; + axor.y = y ^ second.y; + + return axor; +} + +A1 A1::operator&(const A1& second) +{ + A1 abitand(0,0); + abitand.x = x & second.x; + abitand.y = y & second.y; + + return abitand; +} + +int A1::operator<(const A1& second) +{ + A1 b(0,0); + b.x = 3; + return (x < second.x); +} + +int A1::operator<=(const A1& second) +{ + return (x <= second.x); +} + +int A1::operator>=(const A1& second) +{ + return (x >= second.x); +} + +int A1::operator>(const A1& second) +{ + return (x > second.x); +} + +int A1::operator!(void) +{ + return (!x); +} + +A1 A1::operator-(void) +{ + A1 neg(0,0); + neg.x = -x; + neg.y = -y; + + return (neg); +} + +A1 A1::operator~(void) +{ + A1 acompl(0,0); + acompl.x = ~x; + acompl.y = ~y; + + return (acompl); +} + +A1 A1::operator++() // pre increment +{ + x = x +1; + + return (*this); +} + +A1 A1::operator++(int) // post increment +{ + y = y +1; + + return (*this); +} + +A1 A1::operator--() // pre decrement +{ + x = x -1; + + return (*this); +} + +A1 A1::operator--(int) // post decrement +{ + y = y -1; + + return (*this); +} + + +A1 A1::operator=(const A1& second) +{ + + x = second.x; + y = second.y; + + return (*this); +} + +A1 A1::operator+=(int value) +{ + + x += value; + y += value; + + return (*this); +} + +ostream& operator<<(ostream& outs, A1 one) +{ + return (outs << endl << "x = " << one.x << endl << "y = " << one.y << endl << "-------" << endl); +} + +int main (void) +{ + A1 one(2,3); + A1 two(4,5); + A1 three(0,0); + int val; + + marker1(); // marker1-returns-here + cout << one; // marker1-returns-here + cout << two; + three = one + two; + cout << "+ " << three; + three = one - two; + cout << "- " << three; + three = one * two; + cout <<"* " << three; + three = one / two; + cout << "/ " << three; + three = one % two; + cout << "% " << three; + three = one | two; + cout << "| " <= two; + cout << ">= " << val << endl << "-----"< two; + cout << "> " << val << endl << "-----"<> 2; + cout << "rsh " << three; + + three = one; + cout << " = "<< three; + three += 5; + cout << " += "<< three; + + val = (!one); + cout << "! " << val << endl << "-----"< two" "\\\$\[0-9\]* = 0\[\r\n\]" + +gdb_test "print one >= two" "\\\$\[0-9\]* = 0\[\r\n\]" + +gdb_test "print one == two" "\\\$\[0-9\]* = 0\[\r\n\]" + +gdb_test "print one != two" "\\\$\[0-9\]* = 1\[\r\n\]" + +# Can't really check the output of this one without knowing +# target integer width. Make sure we don't try to call +# the iostreams operator instead, though. +gdb_test "print one << 31" "\\\$\[0-9\]* = {x = -?\[0-9\]*, y = -?\[0-9\]*}" + +# Should be fine even on < 32-bit targets. +gdb_test "print one >> 31" "\\\$\[0-9\]* = {x = 0, y = 0}" + +gdb_test "print !one" "\\\$\[0-9\]* = 0\[\r\n\]" + +# Assumes 2's complement. So does everything... +gdb_test "print ~one" "\\\$\[0-9\]* = {x = -3, y = -4}" + +gdb_test "print -one" "\\\$\[0-9\]* = {x = -2, y = -3}" + +gdb_test "print one++" "\\\$\[0-9\]* = {x = 2, y = 4}" + +gdb_test "print ++one" "\\\$\[0-9\]* = {x = 3, y = 4}" + +gdb_test "print one--" "\\\$\[0-9\]* = {x = 3, y = 3}" + +gdb_test "print --one" "\\\$\[0-9\]* = {x = 2, y = 3}" + +gdb_test "print one += 7" "\\\$\[0-9\]* = {x = 9, y = 10}" + +gdb_test "print two = one" "\\\$\[0-9\]* = {x = 9, y = 10}" + +# Check that GDB tolerates whitespace in operator names. +gdb_test "break A1::'operator+'" ".*Breakpoint $decimal at.*" +gdb_test "break A1::'operator +'" ".*Breakpoint $decimal at.*" + +gdb_exit +return 0 diff --git a/gdb/testsuite/gdb.cp/virtfunc.cc b/gdb/testsuite/gdb.cp/virtfunc.cc new file mode 100644 index 0000000..005de9d --- /dev/null +++ b/gdb/testsuite/gdb.cp/virtfunc.cc @@ -0,0 +1,201 @@ +// Pls try the following program on virtual functions and try to do print on +// most of the code in main(). Almost none of them works ! + +// +// The inheritance structure is: +// +// V : VA VB +// A : (V) +// B : A +// D : AD (V) +// C : (V) +// E : B (V) D C +// + +class VA +{ +public: + int va; +}; + +class VB +{ +public: + int vb; + int fvb(); + virtual int vvb(); +}; + +class V : public VA, public VB +{ +public: + int f(); + virtual int vv(); + int w; +}; + +class A : virtual public V +{ +public: + virtual int f(); +private: + int a; +}; + +class B : public A +{ +public: + int f(); +private: + int b; +}; + +class C : public virtual V +{ +public: + int c; +}; + +class AD +{ +public: + virtual int vg() = 0; +}; + +class D : public AD, virtual public V +{ +public: + static void s(); + virtual int vg(); + virtual int vd(); + int fd(); + int d; +}; + +class E : public B, virtual public V, public D, public C +{ +public: + int f(); + int vg(); + int vv(); + int e; +}; + +D dd; +D* ppd = ⅆ +AD* pAd = ⅆ + +A a; +B b; +C c; +D d; +E e; +V v; +VB vb; + + +A* pAa = &a; +A* pAe = &e; + +B* pBe = &e; + +D* pDd = &d; +D* pDe = &e; + +V* pVa = &a; +V* pVv = &v; +V* pVe = &e; +V* pVd = &d; + +AD* pADe = &e; + +E* pEe = &e; + +VB* pVB = &vb; + +void init() +{ + a.vb = 1; + b.vb = 2; + c.vb = 3; + d.vb = 4; + e.vb = 5; + v.vb = 6; + vb.vb = 7; + + d.d = 1; + e.d = 2; +} + +extern "C" int printf(const char *, ...); + +int all_count = 0; +int failed_count = 0; + +#define TEST(EXPR, EXPECTED) \ + ret = EXPR; \ + if (ret != EXPECTED) {\ + printf("Failed %s is %d, should be %d!\n", #EXPR, ret, EXPECTED); \ + failed_count++; } \ + all_count++; + +int ret; + +void test_calls() +{ + TEST(pAe->f(), 20); + TEST(pAa->f(), 1); + + TEST(pDe->vg(), 202); + TEST(pADe->vg(), 202); + TEST(pDd->vg(), 101); + + TEST(pEe->vvb(), 411); + + TEST(pVB->vvb(), 407); + + TEST(pBe->vvb(), 411); + TEST(pDe->vvb(), 411); + + TEST(pEe->vd(), 282); + TEST(pEe->fvb(), 311); + + TEST(pEe->D::vg(), 102); + printf("Did %d tests, of which %d failed.\n", all_count, failed_count); +} +#ifdef usestubs +extern "C" { + void set_debug_traps(); + void breakpoint(); +}; +#endif + +int main() +{ +#ifdef usestubs + set_debug_traps(); + breakpoint(); +#endif + init(); + + e.w = 7; + e.vb = 11; + + test_calls(); + return 0; + +} + +int A::f() {return 1;} +int B::f() {return 2;} +void D::s() {} +int E::f() {return 20;} +int D::vg() {return 100+d;} +int E::vg() {return 200+d;} +int V::f() {return 600+w;} +int V::vv() {return 400+w;} +int E::vv() {return 450+w;} +int D::fd() {return 250+d;} +int D::vd() {return 280+d;} +int VB::fvb() {return 300+vb;} +int VB::vvb() {return 400+vb;} diff --git a/gdb/testsuite/gdb.cp/virtfunc.exp b/gdb/testsuite/gdb.cp/virtfunc.exp new file mode 100644 index 0000000..ff36c27 --- /dev/null +++ b/gdb/testsuite/gdb.cp/virtfunc.exp @@ -0,0 +1,947 @@ +# Copyright 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 +# Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# Please email any bugs, comments, and/or additions to this file to: +# bug-gdb@prep.ai.mit.edu + +# This file was written by Fred Fish. (fnf@cygnus.com) + +set ws "\[\r\n\t \]+" +set nl "\[\r\n\]+" + +if $tracelevel then { + strace $tracelevel +} + +if { [skip_cplus_tests] } { continue } + +set testfile "virtfunc" +set srcfile ${testfile}.cc +set binfile ${objdir}/${subdir}/${testfile} + +if [get_compiler_info ${binfile} "c++"] { + return -1 +} + +source ${binfile}.ci + +if { [gdb_compile "${srcdir}/${subdir}/${srcfile}" "${binfile}" executable {c++ debug}] != "" } { + gdb_suppress_entire_file "Testcase compile failed, so all tests in this file will automatically fail." +} + +proc gdb_virtfunc_init {} { + global srcdir subdir binfile + global gdb_prompt + + gdb_reinitialize_dir $srcdir/$subdir + gdb_load $binfile + + send_gdb "set language c++\n" + gdb_expect -re "$gdb_prompt $" + send_gdb "set width 0\n" + gdb_expect -re "$gdb_prompt $" +} + +proc gdb_virtfunc_restart {} { + gdb_exit; + gdb_start; + gdb_virtfunc_init; + runto 'test_calls'; +} + +# +# Test printing of the types of various classes. +# + +proc test_ptype_of_classes {} { + global gdb_prompt + global ws + global nl + + # This used to be a fail if it printed "struct" not "class". But + # since this struct doesn't use any special C++ features, it is + # considered right for GDB to print it as "struct". + send_gdb "ptype VA\n" + gdb_expect { + -re "type = (struct|class) VA \{(${ws}public:|)${ws}int va;${ws}VA & operator=\\(VA const ?&\\);${ws}VA\\((VA const|const VA) ?&\\);${ws}VA\\((void|)\\);${ws}\}.*$gdb_prompt $" { + pass "ptype VA" + } + -re "type = (struct|class) VA \{(${ws}public:|)${ws}int va;((${ws}VA & operator=\\(VA const ?&\\);)|(${ws}VA\\(VA const ?&\\);)|(${ws}VA\\((void|)\\);))*${ws}\}.*$gdb_prompt $" { + pass "ptype VA (obsolescent gcc or gdb)" + } + -re ".*$gdb_prompt $" { + fail "ptype VA" + } + timeout { + fail "ptype VA (timeout)" + } + } + + send_gdb "ptype VB\n" + gdb_expect { + -re "type = class VB \{${ws}public:${ws}int vb;${ws}VB & operator=\\(VB const ?&\\);${ws}VB\\((VB const|const VB) ?&\\);${ws}VB\\((void|)\\);${ws}int fvb\\((void|)\\);${ws}virtual int vvb\\((void|)\\);${ws}\}.*$gdb_prompt $" { + pass "ptype VB" + } + -re "type = class VB \{${ws}public:${ws}int vb;${ws}int fvb \\((void|)\\);${ws}virtual int vvb \\((void|)\\);${ws}\}.*$gdb_prompt $" { + pass "ptype VB (aCC)" + } + -re "type = class VB \{${ws}public:${ws}int vb;((${ws}VB & operator=\\(VB const ?&\\);)|(${ws}VB\\(VB const ?&\\);)|(${ws}VB\\((void|)\\);)|(${ws}int fvb\\((void|)\\);)|(${ws}virtual int vvb\\((void|)\\);))*${ws}\}.*$gdb_prompt $" { + pass "ptype VB (obsolescent gcc or gdb)" + } + -re ".*$gdb_prompt $" { + fail "ptype VB" + } + timeout { + fail "ptype VB (timeout)" + } + } + + send_gdb "ptype V\n" + gdb_expect { + -re "type = class V : public VA, public VB \{${ws}public:${ws}int w;${ws}V & operator=\\(V const ?&\\);${ws}V\\((V const|const V) ?&\\);${ws}V\\((void|)\\);${ws}int f\\((void|)\\);${ws}virtual int vv\\((void|)\\);${ws}\}$nl$gdb_prompt $" { + pass "ptype V" + } + -re "type = class V : public VA, public VB \{${ws}public:${ws}int w;${ws}int f \\((void|)\\);${ws}virtual int vv \\((void|)\\);${ws}\}$nl$gdb_prompt $" { + pass "ptype V (aCC)" + } + -re "type = class V : public VA, public VB \{${ws}public:${ws}int w;((${ws}V & operator=\\(V const ?&\\);)|(${ws}V\\(V const ?&\\);)|(${ws}V\\((void|)\\);)|(${ws}int f\\((void|)\\);)|(${ws}virtual int vv\\((void|)\\);))*${ws}\}$nl$gdb_prompt $" { + pass "ptype V (obsolescent gcc or gdb)" + } + -re ".*$gdb_prompt $" { + fail "ptype V" + } + timeout { + fail "ptype V (timeout)" + } + } + + # The format of a g++ virtual base pointer. + set vbptr "(_vb\[$.\]|__vb_)\[0-9\]?" + + send_gdb "ptype A\n" + gdb_expect { + -re "type = class A : public virtual V \{${ws}private:${ws}V \\*${vbptr}V;${ws}int a;${ws}public:${ws}A & operator=\\(A const ?&\\);${ws}A\\(int, A const ?&\\);${ws}A\\(int\\);${ws}virtual int f\\((void|)\\);${ws}\}$nl$gdb_prompt $" { + pass "ptype A" + } + -re "type = class A : public virtual V \{${ws}private:${ws}int a;${ws}public:${ws}A & operator=\\(A const ?&\\);${ws}A\\((A const|const A) ?&\\);${ws}A\\((void|)\\);${ws}virtual int f\\((void|)\\);${ws}\}$nl$gdb_prompt $" { + pass "ptype A" + } + -re "type = class A : public virtual V \{${ws}private:${ws}int a;${ws}public:${ws}virtual int f\\((void|)\\);${ws}\}$nl$gdb_prompt $" { + pass "ptype A (aCC)" + } + -re "type = class A : public virtual V \{${ws}private:${ws}V \\*${vbptr}V;${ws}int a;${ws}public:((${ws}A & operator=\\(A const ?&\\);)|(${ws}A\\(int, A const ?&\\);)|(${ws}A\\(int\\);)|(${ws}virtual int f\\((void|)\\);))*${ws}\}$nl$gdb_prompt $" { + pass "ptype A (obsolescent gcc or gdb)" + } + -re "type = class A : public virtual V \{${ws}private:${ws}V \\*${vbptr}FOO;${ws}int a;${ws}public:${ws}virtual int f.void.;${ws}\}$nl$gdb_prompt $" { + # This happens because the type is defined only after it is + # too late. + fail "ptype A (known failure with gcc cygnus-2.4.5-930417)" + # Many of the rest of these tests have the same problem. + return 0 + } + -re ".*$gdb_prompt $" { + fail "ptype A" + } + timeout { + fail "ptype A (timeout)" + } + } + + send_gdb "ptype B\n" + gdb_expect { + -re "type = class B : public A \{${ws}private:${ws}int b;${ws}public:${ws}B & operator=\\(B const ?&\\);${ws}B\\(int, B const ?&\\);${ws}B\\(int\\);${ws}virtual int f\\((void|)\\);${ws}\}$nl$gdb_prompt $" { + pass "ptype B" + } + -re "type = class B : public A \{${ws}private:${ws}int b;${ws}public:${ws}B & operator=\\(B const ?&\\);${ws}B\\((B const|const B) ?&\\);${ws}B\\((void|)\\);${ws}virtual int f\\((void|)\\);${ws}\}$nl$gdb_prompt $" { + pass "ptype B" + } + -re "type = class B : public A \{${ws}private:${ws}int b;${ws}public:${ws}virtual int f \\((void|)\\);${ws}\}$nl$gdb_prompt $" { + pass "ptype B (aCC)" + } + -re "type = class B : public A \{${ws}private:${ws}int b;${ws}public:((${ws}B & operator=\\(B const ?&\\);)|(${ws}B\\(int, B const ?&\\);)|(${ws}B\\(int\\);)|(${ws}virtual int f\\((void|)\\);))*${ws}\}$nl$gdb_prompt $" { + pass "ptype B (obsolescent gcc or gdb)" + } + -re ".*$gdb_prompt $" { + fail "ptype B" + } + timeout { + fail "ptype B (timeout)" + } + } + + send_gdb "ptype C\n" + gdb_expect { + -re "type = class C : public virtual V \{${ws}private:${ws}V \\*${vbptr}V;${ws}public:${ws}int c;${ws}C & operator=\\(C const ?&\\);${ws}C\\(int, C const ?&\\);${ws}C\\(int\\);${ws}\}$nl$gdb_prompt $" { + pass "ptype C" + } + -re "type = class C : public virtual V \{${ws}public:${ws}int c;${ws}C & operator=\\(C const ?&\\);${ws}C\\((C const|const C) ?&\\);${ws}C\\((void|)\\);${ws}\}$nl$gdb_prompt $" { + pass "ptype C" + } + -re "type = class C : public virtual V \{${ws}public:${ws}int c;${ws}\}$nl$gdb_prompt $" { + pass "ptype C (aCC)" + } + -re "type = class C : public virtual V \{${ws}private:${ws}V \\*${vbptr}V;${ws}public:${ws}int c;((${ws}C & operator=\\(C const ?&\\);)|(${ws}C\\(int, C const ?&\\);)|(${ws}C\\(int\\);))*${ws}\}$nl$gdb_prompt $" { + pass "ptype C (obsolescent gcc or gdb)" + } + -re ".*$gdb_prompt $" { + fail "ptype C" + } + timeout { + fail "ptype C (timeout)" + } + } + + send_gdb "ptype AD\n" + gdb_expect { + -re "type = class AD \{${ws}public:${ws}AD & operator=\\(AD const ?&\\);${ws}AD\\((AD const|const AD) ?&\\);${ws}AD\\((void|)\\);${ws}virtual int vg\\((void|)\\);${ws}\}$nl$gdb_prompt $" { + pass "ptype AD" + } + -re "type = class AD \{${ws}public:${ws}virtual int vg \\((void|)\\);${ws}\}$nl$gdb_prompt $" { + pass "ptype AD (aCC)" + } + -re "type = class AD \{${ws}public:((${ws}AD & operator=\\(AD const ?&\\);)|(${ws}AD\\(AD const ?&\\);)|(${ws}AD\\((void|)\\);)|(${ws}virtual int vg\\((void|)\\);))*${ws}\}$nl$gdb_prompt $" { + pass "ptype AD (obsolescent gcc or gdb)" + } + -re ".*$gdb_prompt $" { + fail "ptype AD" + } + timeout { + fail "ptype AD (timeout)" + } + } + + send_gdb "ptype D\n" + gdb_expect { + -re "type = class D : public AD, public virtual V \{${ws}private:${ws}V \\*${vbptr}V;${ws}public:${ws}int d;${ws}D & operator=\\(D const ?&\\);${ws}D\\(int, D const ?&\\);${ws}D\\(int\\);${ws}static void s\\((void|)\\);${ws}virtual int vg\\((void|)\\);${ws}virtual int vd\\((void|)\\);${ws}int fd\\((void|)\\);${ws}\}$nl$gdb_prompt $" { + pass "ptype D" + } + -re "type = class D : public AD, public virtual V \{${ws}public:${ws}int d;${ws}D & operator=\\(D const ?&\\);${ws}D\\((D const|const D) ?&\\);${ws}D\\((void|)\\);${ws}static void s\\((void|)\\);${ws}virtual int vg\\((void|)\\);${ws}virtual int vd\\((void|)\\);${ws}int fd\\((void|)\\);${ws}\}$nl$gdb_prompt $" { + pass "ptype D" + } + -re "type = class D : public AD, public virtual V \{${ws}public:${ws}int d;${ws}static void s\\((void|)\\);${ws}virtual int vg\\((void|)\\);${ws}virtual int vd\\((void|)\\);${ws}int fd\\((void|)\\);${ws}\}$nl$gdb_prompt $" { + pass "ptype D (aCC)" + } + -re "type = class D : public AD, public virtual V \{${ws}private:${ws}V \\*${vbptr}V;${ws}public:${ws}int d;((${ws}D & operator=\\(D const ?&\\);)|(${ws}D\\(int, D const ?&\\);)|(${ws}D\\(int\\);)|(${ws}static void s\\((void|)\\);)|(${ws}virtual int vg\\((void|)\\);)|(${ws}virtual int vd\\((void|)\\);)|(${ws}int fd\\((void|)\\);))*${ws}\}$nl$gdb_prompt $" { + pass "ptype D (obsolescent gcc or gdb)" + } + -re ".*$gdb_prompt $" { + fail "ptype D" + } + timeout { + fail "ptype D (timeout)" + } + } + + send_gdb "ptype E\n" + gdb_expect { + -re "type = class E : public B, public virtual V, public D, public C \{${ws}public:${ws}int e;${ws}E & operator=\\(E const ?&\\);${ws}E\\(int, E const ?&\\);${ws}E\\(int\\);${ws}virtual int f\\((void|)\\);${ws}virtual int vg\\((void|)\\);${ws}virtual int vv\\((void|)\\);${ws}\}$nl$gdb_prompt $" { + pass "ptype E" + } + -re "type = class E : public B, public virtual V, public D, public C \{${ws}public:${ws}int e;${ws}E & operator=\\(E const ?&\\);${ws}E\\((E const|const E) ?&\\);${ws}E\\((void|)\\);${ws}virtual int f\\((void|)\\);${ws}virtual int vg\\((void|)\\);${ws}virtual int vv\\((void|)\\);${ws}\}$nl$gdb_prompt $" { + pass "ptype E" + } + -re "type = class E : public B, public virtual V, public D, public C \{${ws}public:${ws}int e;${ws}virtual int f \\((void|)\\);${ws}virtual int vg \\((void|)\\);${ws}virtual int vv \\((void|)\\);${ws}\}$nl$gdb_prompt $" { + pass "ptype E (aCC)" + } + -re "type = class E : public B, public virtual V, public D, public C \{${ws}public:${ws}int e;((${ws}E & operator=\\(E const ?&\\);)|(${ws}E\\(int, E const ?&\\);)|(${ws}E\\(int\\);)|(${ws}virtual int f\\((void|)\\);)|(${ws}virtual int vg\\((void|)\\);)|(${ws}virtual int vv\\((void|)\\);))*${ws}\}$nl$gdb_prompt $" { + pass "ptype E (obsolescent gcc or gdb)" + } + -re ".*$gdb_prompt $" { + fail "ptype E" + } + timeout { + fail "ptype E (timeout)" + } + } + + send_gdb "ptype dd\n" + gdb_expect { + -re "type = class D : public AD, public virtual V \{${ws}private:${ws}V \\*${vbptr}V;${ws}public:${ws}int d;${ws}D & operator=\\(D const ?&\\);${ws}D\\(int, D const ?&\\);${ws}D\\(int\\);${ws}static void s\\((void|)\\);${ws}virtual int vg\\((void|)\\);${ws}virtual int vd\\((void|)\\);${ws}int fd\\((void|)\\);${ws}\}$nl$gdb_prompt $" { + pass "ptype dd" + } + -re "type = class D : public AD, public virtual V \{${ws}public:${ws}int d;${ws}D & operator=\\(D const ?&\\);${ws}D\\((D const|const D) ?&\\);${ws}D\\((void|)\\);${ws}static void s\\((void|)\\);${ws}virtual int vg\\((void|)\\);${ws}virtual int vd\\((void|)\\);${ws}int fd\\((void|)\\);${ws}\}$nl$gdb_prompt $" { + pass "ptype dd" + } + -re "type = class D : public AD, public virtual V \{${ws}public:${ws}int d;${ws}static void s\\((void|)\\);${ws}virtual int vg\\((void|)\\);${ws}virtual int vd\\((void|)\\);${ws}int fd\\((void|)\\);${ws}\}$nl$gdb_prompt $" { + pass "ptype dd (aCC)" + } + -re "type = class D : public AD, public virtual V \{${ws}private:${ws}V \\*${vbptr}V;${ws}public:${ws}int d;((${ws}D & operator=\\(D const ?&\\);)|(${ws}D\\(int, D const ?&\\);)|(${ws}D\\(int\\);)|(${ws}static void s\\((void|)\\);)|(${ws}virtual int vg\\((void|)\\);)|(${ws}virtual int vd\\((void|)\\);)|(${ws}int fd\\((void|)\\);))*${ws}\}$nl$gdb_prompt $" { + pass "ptype dd (obsolescent gcc or gdb)" + } + -re ".*$gdb_prompt $" { + fail "ptype dd" + } + timeout { + fail "ptype dd (timeout)" + } + } + + send_gdb "ptype ppd\n" + gdb_expect { + -re "type = class D : public AD, public virtual V \{${ws}private:${ws}V \\*${vbptr}V;${ws}public:${ws}int d;${ws}D & operator=\\(D const ?&\\);${ws}D\\(int, D const ?&\\);${ws}D\\(int\\);${ws}static void s\\((void|)\\);${ws}virtual int vg\\((void|)\\);${ws}virtual int vd\\((void|)\\);${ws}int fd\\((void|)\\);${ws}\} \[*\]+$nl$gdb_prompt $" { + pass "ptype ppd" + } + -re "type = class D : public AD, public virtual V \{${ws}public:${ws}int d;${ws}D & operator=\\(D const ?&\\);${ws}D\\((D const|const D) ?&\\);${ws}D\\((void|)\\);${ws}static void s\\((void|)\\);${ws}virtual int vg\\((void|)\\);${ws}virtual int vd\\((void|)\\);${ws}int fd\\((void|)\\);${ws}\} \[*\]+$nl$gdb_prompt $" { + pass "ptype ppd" + } + -re "type = class D : public AD, public virtual V \{${ws}public:${ws}int d;${ws}static void s\\((void|)\\);${ws}virtual int vg\\((void|)\\);${ws}virtual int vd\\((void|)\\);${ws}int fd\\((void|)\\);${ws}\} \[*\]+$nl$gdb_prompt $" { + pass "ptype ppd (aCC)" + } + -re "type = class D : public AD, public virtual V \{${ws}private:${ws}V \\*${vbptr}V;${ws}public:${ws}int d;((${ws}D & operator=\\(D const ?&\\);)|(${ws}D\\(int, D const ?&\\);)|(${ws}D\\(int\\);)|(${ws}static void s\\((void|)\\);)|(${ws}virtual int vg\\((void|)\\);)|(${ws}virtual int vd\\((void|)\\);)|(${ws}int fd\\((void|)\\);))*${ws}\} \[*\]+$nl$gdb_prompt $" { + pass "ptype ppd (obsolescent gcc or gdb)" + } + -re ".*$gdb_prompt $" { + fail "ptype ppd" + } + timeout { + fail "ptype ppd (timeout)" + } + } + + send_gdb "ptype pAd\n" + gdb_expect { + -re "type = class AD \{${ws}public:${ws}AD & operator=\\(AD const ?&\\);${ws}AD\\((AD const|const AD) ?&\\);${ws}AD\\((void|)\\);${ws}virtual int vg\\((void|)\\);${ws}\} \[*\]+$nl$gdb_prompt $" { + pass "ptype pAd" + } + -re "type = class AD \{${ws}public:${ws}virtual int vg \\((void|)\\);${ws}\} \[*\]+$nl$gdb_prompt $" { + pass "ptype pAd (aCC)" + } + -re "type = class AD \{${ws}public:((${ws}AD & operator=\\(AD const ?&\\);)|(${ws}AD\\(AD const ?&\\);)|(${ws}AD\\((void|)\\);)|(${ws}virtual int vg\\((void|)\\);))*${ws}\} \[*\]+$nl$gdb_prompt $" { + pass "ptype pAd (obsolescent gcc or gdb)" + } + -re ".*$gdb_prompt $" { + fail "ptype pAd" + } + timeout { + fail "ptype pAd (timeout)" + } + } + + send_gdb "ptype a\n" + gdb_expect { + -re "type = class A : public virtual V \{${ws}private:${ws}V \\*${vbptr}V;${ws}int a;${ws}public:${ws}A & operator=\\(A const ?&\\);${ws}A\\(int, A const ?&\\);${ws}A\\(int\\);${ws}virtual int f\\((void|)\\);${ws}\}$nl$gdb_prompt $" { + pass "ptype a" + } + -re "type = class A : public virtual V \{${ws}private:${ws}int a;${ws}public:${ws}A & operator=\\(A const ?&\\);${ws}A\\((A const|const A) ?&\\);${ws}A\\((void|)\\);${ws}virtual int f\\((void|)\\);${ws}\}$nl$gdb_prompt $" { + pass "ptype a" + } + -re "type = class A : public virtual V \{${ws}private:${ws}int a;${ws}public:${ws}virtual int f\\((void|)\\);${ws}\}$nl$gdb_prompt $" { + pass "ptype a (aCC)" + } + -re "type = class A : public virtual V \{${ws}private:${ws}V \\*${vbptr}V;${ws}int a;${ws}public:((${ws}A & operator=\\(A const ?&\\);)|(${ws}A\\(int, A const ?&\\);)|(${ws}A\\(int\\);)|(${ws}virtual int f\\((void|)\\);))*${ws}\}$nl$gdb_prompt $" { + pass "ptype a (obsolescent gcc or gdb)" + } + -re ".*$gdb_prompt $" { + fail "ptype a" + } + timeout { + fail "ptype a (timeout)" + } + } + + send_gdb "ptype b\n" + gdb_expect { + -re "type = class B : public A \{${ws}private:${ws}int b;${ws}public:${ws}B & operator=\\(B const ?&\\);${ws}B\\(int, B const ?&\\);${ws}B\\(int\\);${ws}virtual int f\\((void|)\\);${ws}\}$nl$gdb_prompt $" { + pass "ptype b" + } + -re "type = class B : public A \{${ws}private:${ws}int b;${ws}public:${ws}B & operator=\\(B const ?&\\);${ws}B\\((B const|const B) ?&\\);${ws}B\\((void|)\\);${ws}virtual int f\\((void|)\\);${ws}\}$nl$gdb_prompt $" { + pass "ptype b" + } + -re "type = class B : public A \{${ws}private:${ws}int b;${ws}public:${ws}virtual int f \\((void|)\\);${ws}\}$nl$gdb_prompt $" { + pass "ptype b (aCC)" + } + -re "type = class B : public A \{${ws}private:${ws}int b;${ws}public:((${ws}B & operator=\\(B const ?&\\);)|(${ws}B\\(int, B const ?&\\);)|(${ws}B\\(int\\);)|(${ws}virtual int f\\((void|)\\);))*${ws}\}$nl$gdb_prompt $" { + pass "ptype b (obsolescent gcc or gdb)" + } + -re ".*$gdb_prompt $" { + fail "ptype b" + } + timeout { + fail "ptype b (timeout)" + } + } + + send_gdb "ptype c\n" + gdb_expect { + -re "type = class C : public virtual V \{${ws}private:${ws}V \\*${vbptr}V;${ws}public:${ws}int c;${ws}C & operator=\\(C const ?&\\);${ws}C\\(int, C const ?&\\);${ws}C\\(int\\);${ws}\}$nl$gdb_prompt $" { + pass "ptype c" + } + -re "type = class C : public virtual V \{${ws}public:${ws}int c;${ws}C & operator=\\(C const ?&\\);${ws}C\\((C const|const C) ?&\\);${ws}C\\((void|)\\);${ws}\}$nl$gdb_prompt $" { + pass "ptype c" + } + -re "type = class C : public virtual V \{${ws}public:${ws}int c;${ws}\}$nl$gdb_prompt $" { + pass "ptype c (aCC)" + } + -re "type = class C : public virtual V \{${ws}private:${ws}V \\*${vbptr}V;${ws}public:${ws}int c;((${ws}C & operator=\\(C const ?&\\);)|(${ws}C\\(int, C const ?&\\);)|(${ws}C\\(int\\);))*${ws}\}$nl$gdb_prompt $" { + pass "ptype c (obsolescent gcc or gdb)" + } + -re ".*$gdb_prompt $" { + fail "ptype c" + } + timeout { + fail "ptype c (timeout)" + } + } + + send_gdb "ptype d\n" + gdb_expect { + -re "type = class D : public AD, public virtual V \{${ws}private:${ws}V \\*${vbptr}V;${ws}public:${ws}int d;${ws}D & operator=\\(D const ?&\\);${ws}D\\(int, D const ?&\\);${ws}D\\(int\\);${ws}static void s\\((void|)\\);${ws}virtual int vg\\((void|)\\);${ws}virtual int vd\\((void|)\\);${ws}int fd\\((void|)\\);${ws}\}$nl$gdb_prompt $" { + pass "ptype d" + } + -re "type = class D : public AD, public virtual V \{${ws}public:${ws}int d;${ws}D & operator=\\(D const ?&\\);${ws}D\\((D const|const D) ?&\\);${ws}D\\((void|)\\);${ws}static void s\\((void|)\\);${ws}virtual int vg\\((void|)\\);${ws}virtual int vd\\((void|)\\);${ws}int fd\\((void|)\\);${ws}\}$nl$gdb_prompt $" { + pass "ptype d" + } + -re "type = class D : public AD, public virtual V \{${ws}public:${ws}int d;${ws}static void s\\((void|)\\);${ws}virtual int vg\\((void|)\\);${ws}virtual int vd\\((void|)\\);${ws}int fd\\((void|)\\);${ws}\}$nl$gdb_prompt $" { + pass "ptype d (aCC)" + } + -re "type = class D : public AD, public virtual V \{${ws}private:${ws}V \\*${vbptr}V;${ws}public:${ws}int d;((${ws}D & operator=\\(D const ?&\\);)|(${ws}D\\(int, D const ?&\\);)|(${ws}D\\(int\\);)|(${ws}static void s\\((void|)\\);)|(${ws}virtual int vg\\((void|)\\);)|(${ws}virtual int vd\\((void|)\\);)|(${ws}int fd\\((void|)\\);))*${ws}\}$nl$gdb_prompt $" { + pass "ptype d (obsolescent gcc or gdb)" + } + -re ".*$gdb_prompt $" { + fail "ptype d" + } + timeout { + fail "ptype d (timeout)" + } + } + + send_gdb "ptype e\n" + gdb_expect { + -re "type = class E : public B, public virtual V, public D, public C \{${ws}public:${ws}int e;${ws}E & operator=\\(E const ?&\\);${ws}E\\(int, E const ?&\\);${ws}E\\(int\\);${ws}virtual int f\\((void|)\\);${ws}virtual int vg\\((void|)\\);${ws}virtual int vv\\((void|)\\);${ws}\}$nl$gdb_prompt $" { + pass "ptype e" + } + -re "type = class E : public B, public virtual V, public D, public C \{${ws}public:${ws}int e;${ws}E & operator=\\(E const ?&\\);${ws}E\\((E const|const E) ?&\\);${ws}E\\((void|)\\);${ws}virtual int f\\((void|)\\);${ws}virtual int vg\\((void|)\\);${ws}virtual int vv\\((void|)\\);${ws}\}$nl$gdb_prompt $" { + pass "ptype e" + } + -re "type = class E : public B, public virtual V, public D, public C \{${ws}public:${ws}int e;${ws}virtual int f \\((void|)\\);${ws}virtual int vg \\((void|)\\);${ws}virtual int vv \\((void|)\\);${ws}\}$nl$gdb_prompt $" { + pass "ptype e (aCC)" + } + -re "type = class E : public B, public virtual V, public D, public C \{${ws}public:${ws}int e;((${ws}E & operator=\\(E const ?&\\);)|(${ws}E\\(int, E const ?&\\);)|(${ws}E\\(int\\);)|(${ws}virtual int f\\((void|)\\);)|(${ws}virtual int vg\\((void|)\\);)|(${ws}virtual int vv\\((void|)\\);))*${ws}\}$nl$gdb_prompt $" { + pass "ptype e (obsolescent gcc or gdb)" + } + -re ".*$gdb_prompt $" { + fail "ptype e" + } + timeout { + fail "ptype e (timeout)" + } + } + + send_gdb "ptype v\n" + gdb_expect { + -re "type = class V : public VA, public VB \{${ws}public:${ws}int w;${ws}V & operator=\\(V const ?&\\);${ws}V\\((V const|const V) ?&\\);${ws}V\\((void|)\\);${ws}int f\\((void|)\\);${ws}virtual int vv\\((void|)\\);${ws}\}$nl$gdb_prompt $" { + pass "ptype v" + } + -re "type = class V : public VA, public VB \{${ws}public:${ws}int w;${ws}int f \\((void|)\\);${ws}virtual int vv \\((void|)\\);${ws}\}$nl$gdb_prompt $" { + pass "ptype v (aCC)" + } + -re "type = class V : public VA, public VB \{${ws}public:${ws}int w;((${ws}V & operator=\\(V const ?&\\);)|(${ws}V\\(V const ?&\\);)|(${ws}V\\((void|)\\);)|(${ws}int f\\((void|)\\);)|(${ws}virtual int vv\\((void|)\\);))*${ws}\}$nl$gdb_prompt $" { + pass "ptype v (obsolescent gcc or gdb)" + } + -re ".*$gdb_prompt $" { + fail "ptype v" + } + timeout { + fail "ptype v (timeout)" + } + } + + send_gdb "ptype vb\n" + gdb_expect { + -re "type = class VB \{${ws}public:${ws}int vb;${ws}VB & operator=\\(VB const ?&\\);${ws}VB\\((VB const|const VB) ?&\\);${ws}VB\\((void|)\\);${ws}int fvb\\((void|)\\);${ws}virtual int vvb\\((void|)\\);${ws}\}$nl$gdb_prompt $" { + pass "ptype vb" + } + -re "type = class VB \{${ws}public:${ws}int vb;${ws}int fvb \\((void|)\\);${ws}virtual int vvb \\((void|)\\);${ws}\}$nl$gdb_prompt $" { + pass "ptype vb (aCC)" + } + -re "type = class VB \{${ws}public:${ws}int vb;((${ws}VB & operator=\\(VB const ?&\\);)|(${ws}VB\\(VB const ?&\\);)|(${ws}VB\\((void|)\\);)|(${ws}int fvb\\((void|)\\);)|(${ws}virtual int vvb\\((void|)\\);))*${ws}\}$nl$gdb_prompt $" { + pass "ptype vb (obsolescent gcc or gdb)" + } + -re ".*$gdb_prompt $" { + fail "ptype vb" + } + timeout { + fail "ptype vb (timeout)" + } + } + + send_gdb "ptype pAa\n" + gdb_expect { + -re "type = class A : public virtual V \{${ws}private:${ws}V \\*${vbptr}V;${ws}int a;${ws}public:${ws}A & operator=\\(A const ?&\\);${ws}A\\(int, A const ?&\\);${ws}A\\(int\\);${ws}virtual int f\\((void|)\\);${ws}\} \[*\]+$nl$gdb_prompt $" { + pass "ptype pAa" + } + -re "type = class A : public virtual V \{${ws}private:${ws}int a;${ws}public:${ws}A & operator=\\(A const ?&\\);${ws}A\\((A const|const A) ?&\\);${ws}A\\((void|)\\);${ws}virtual int f\\((void|)\\);${ws}\} \[*\]+$nl$gdb_prompt $" { + pass "ptype pAa" + } + -re "type = class A : public virtual V \{${ws}private:${ws}int a;${ws}public:${ws}virtual int f\\((void|)\\);${ws}\} \[*\]+$nl$gdb_prompt $" { + pass "ptype pAa (aCC)" + } + -re "type = class A : public virtual V \{${ws}private:${ws}V \\*${vbptr}V;${ws}int a;${ws}public:((${ws}A & operator=\\(A const ?&\\);)|(${ws}A\\(int, A const ?&\\);)|(${ws}A\\(int\\);)|(${ws}virtual int f\\((void|)\\);))*${ws}\} \[*\]+$nl$gdb_prompt $" { + pass "ptype pAa (obsolescent gcc or gdb)" + } + -re ".*$gdb_prompt $" { + fail "ptype pAa" + } + timeout { + fail "ptype pAa (timeout)" + } + } + + send_gdb "ptype pAe\n" + gdb_expect { + -re "type = class A : public virtual V \{${ws}private:${ws}V \\*${vbptr}V;${ws}int a;${ws}public:${ws}A & operator=\\(A const ?&\\);${ws}A\\(int, A const ?&\\);${ws}A\\(int\\);${ws}virtual int f\\((void|)\\);${ws}\} \[*\]+$nl$gdb_prompt $" { + pass "ptype pAe" + } + -re "type = class A : public virtual V \{${ws}private:${ws}int a;${ws}public:${ws}A & operator=\\(A const ?&\\);${ws}A\\((A const|const A) ?&\\);${ws}A\\((void|)\\);${ws}virtual int f\\((void|)\\);${ws}\} \[*\]+$nl$gdb_prompt $" { + pass "ptype pAe" + } + -re "type = class A : public virtual V \{${ws}private:${ws}int a;${ws}public:${ws}virtual int f\\((void|)\\);${ws}\} \[*\]+$nl$gdb_prompt $" { + pass "ptype pAe (aCC)" + } + -re "type = class A : public virtual V \{${ws}private:${ws}V \\*${vbptr}V;${ws}int a;${ws}public:((${ws}A & operator=\\(A const ?&\\);)|(${ws}A\\(int, A const ?&\\);)|(${ws}A\\(int\\);)|(${ws}virtual int f\\((void|)\\);))*${ws}\} \[*\]+$nl$gdb_prompt $" { + pass "ptype pAe (obsolescent gcc or gdb)" + } + -re ".*$gdb_prompt $" { + fail "ptype pAe" + } + timeout { + fail "ptype pAe (timeout)" + } + } + + send_gdb "ptype pBe\n" + gdb_expect { + -re "type = class B : public A \{${ws}private:${ws}int b;${ws}public:${ws}B & operator=\\(B const ?&\\);${ws}B\\(int, B const ?&\\);${ws}B\\(int\\);${ws}virtual int f\\((void|)\\);${ws}\} \[*\]+$nl$gdb_prompt $" { + pass "ptype pBe" + } + -re "type = class B : public A \{${ws}private:${ws}int b;${ws}public:${ws}B & operator=\\(B const ?&\\);${ws}B\\((B const|const B) ?&\\);${ws}B\\((void|)\\);${ws}virtual int f\\((void|)\\);${ws}\} \[*\]+$nl$gdb_prompt $" { + pass "ptype pBe" + } + -re "type = class B : public A \{${ws}private:${ws}int b;${ws}public:${ws}virtual int f \\((void|)\\);${ws}\} \[*\]+$nl$gdb_prompt $" { + pass "ptype pBe (aCC)" + } + -re "type = class B : public A \{${ws}private:${ws}int b;${ws}public:((${ws}B & operator=\\(B const ?&\\);)|(${ws}B\\(int, B const ?&\\);)|(${ws}B\\(int\\);)|(${ws}virtual int f\\((void|)\\);))*${ws}\} \[*\]+$nl$gdb_prompt $" { + pass "ptype pBe (obsolescent gcc or gdb)" + } + -re ".*$gdb_prompt $" { + fail "ptype pBe" + } + timeout { + fail "ptype pBe (timeout)" + } + } + + send_gdb "ptype pDd\n" + gdb_expect { + -re "type = class D : public AD, public virtual V \{${ws}private:${ws}V \\*${vbptr}V;${ws}public:${ws}int d;${ws}D & operator=\\(D const ?&\\);${ws}D\\(int, D const ?&\\);${ws}D\\(int\\);${ws}static void s\\((void|)\\);${ws}virtual int vg\\((void|)\\);${ws}virtual int vd\\((void|)\\);${ws}int fd\\((void|)\\);${ws}\} \[*\]+$nl$gdb_prompt $" { + pass "ptype pDd" + } + -re "type = class D : public AD, public virtual V \{${ws}public:${ws}int d;${ws}D & operator=\\(D const ?&\\);${ws}D\\((D const|const D) ?&\\);${ws}D\\((void|)\\);${ws}static void s\\((void|)\\);${ws}virtual int vg\\((void|)\\);${ws}virtual int vd\\((void|)\\);${ws}int fd\\((void|)\\);${ws}\} \[*\]+$nl$gdb_prompt $" { + pass "ptype pDd" + } + -re "type = class D : public AD, public virtual V \{${ws}public:${ws}int d;${ws}static void s\\((void|)\\);${ws}virtual int vg\\((void|)\\);${ws}virtual int vd\\((void|)\\);${ws}int fd\\((void|)\\);${ws}\} \[*\]+$nl$gdb_prompt $" { + pass "ptype pDd (aCC)" + } + -re "type = class D : public AD, public virtual V \{${ws}private:${ws}V \\*${vbptr}V;${ws}public:${ws}int d;((${ws}D & operator=\\(D const ?&\\);)|(${ws}D\\(int, D const ?&\\);)|(${ws}D\\(int\\);)|(${ws}static void s\\((void|)\\);)|(${ws}virtual int vg\\((void|)\\);)|(${ws}virtual int vd\\((void|)\\);)|(${ws}int fd\\((void|)\\);))*${ws}\} \[*\]+$nl$gdb_prompt $" { + pass "ptype pDd (obsolescent gcc or gdb)" + } + -re ".*$gdb_prompt $" { + fail "ptype pDd" + } + timeout { + fail "ptype pDd (timeout)" + } + } + + send_gdb "ptype pDe\n" + gdb_expect { + -re "type = class D : public AD, public virtual V \{${ws}private:${ws}V \\*${vbptr}V;${ws}public:${ws}int d;${ws}D & operator=\\(D const ?&\\);${ws}D\\(int, D const ?&\\);${ws}D\\(int\\);${ws}static void s\\((void|)\\);${ws}virtual int vg\\((void|)\\);${ws}virtual int vd\\((void|)\\);${ws}int fd\\((void|)\\);${ws}\} \[*\]+$nl$gdb_prompt $" { + pass "ptype pDe" + } + -re "type = class D : public AD, public virtual V \{${ws}public:${ws}int d;${ws}D & operator=\\(D const ?&\\);${ws}D\\((D const|const D) ?&\\);${ws}D\\((void|)\\);${ws}static void s\\((void|)\\);${ws}virtual int vg\\((void|)\\);${ws}virtual int vd\\((void|)\\);${ws}int fd\\((void|)\\);${ws}\} \[*\]+$nl$gdb_prompt $" { + pass "ptype pDe" + } + -re "type = class D : public AD, public virtual V \{${ws}public:${ws}int d;${ws}static void s\\((void|)\\);${ws}virtual int vg\\((void|)\\);${ws}virtual int vd\\((void|)\\);${ws}int fd\\((void|)\\);${ws}\} \[*\]+$nl$gdb_prompt $" { + pass "ptype pDe (aCC)" + } + -re "type = class D : public AD, public virtual V \{${ws}private:${ws}V \\*${vbptr}V;${ws}public:${ws}int d;((${ws}D & operator=\\(D const ?&\\);)|(${ws}D\\(int, D const ?&\\);)|(${ws}D\\(int\\);)|(${ws}static void s\\((void|)\\);)|(${ws}virtual int vg\\((void|)\\);)|(${ws}virtual int vd\\((void|)\\);)|(${ws}int fd\\((void|)\\);))*${ws}\} \[*\]+$nl$gdb_prompt $" { + pass "ptype pDe (obsolescent gcc or gdb)" + } + -re ".*$gdb_prompt $" { + fail "ptype pDe" + } + timeout { + fail "ptype pDe (timeout)" + } + } + + send_gdb "ptype pVa\n" + gdb_expect { + -re "type = class V : public VA, public VB \{${ws}public:${ws}int w;${ws}V & operator=\\(V const ?&\\);${ws}V\\((V const|const V) ?&\\);${ws}V\\((void|)\\);${ws}int f\\((void|)\\);${ws}virtual int vv\\((void|)\\);${ws}\} \[*\]+$nl$gdb_prompt $" { + pass "ptype pVa" + } + -re "type = class V : public VA, public VB \{${ws}public:${ws}int w;${ws}int f \\((void|)\\);${ws}virtual int vv \\((void|)\\);${ws}\} \[*\]+$nl$gdb_prompt $" { + pass "ptype pVa (aCC)" + } + -re "type = class V : public VA, public VB \{${ws}public:${ws}int w;((${ws}V & operator=\\(V const ?&\\);)|(${ws}V\\(V const ?&\\);)|(${ws}V\\((void|)\\);)|(${ws}int f\\((void|)\\);)|(${ws}virtual int vv\\((void|)\\);))*${ws}\} \[*\]+$nl$gdb_prompt $" { + pass "ptype pVa (obsolescent gcc or gdb)" + } + -re ".*$gdb_prompt $" { + fail "ptype pVa" + } + timeout { + fail "ptype pVa (timeout)" + } + } + + send_gdb "ptype pVv\n" + gdb_expect { + -re "type = class V : public VA, public VB \{${ws}public:${ws}int w;${ws}V & operator=\\(V const ?&\\);${ws}V\\((V const|const V) ?&\\);${ws}V\\((void|)\\);${ws}int f\\((void|)\\);${ws}virtual int vv\\((void|)\\);${ws}\} \[*\]+$nl$gdb_prompt $" { + pass "ptype pVv" + } + -re "type = class V : public VA, public VB \{${ws}public:${ws}int w;${ws}int f \\((void|)\\);${ws}virtual int vv \\((void|)\\);${ws}\} \[*\]+$nl$gdb_prompt $" { + pass "ptype pVv (aCC)" + } + -re "type = class V : public VA, public VB \{${ws}public:${ws}int w;((${ws}V & operator=\\(V const ?&\\);)|(${ws}V\\(V const ?&\\);)|(${ws}V\\((void|)\\);)|(${ws}int f\\((void|)\\);)|(${ws}virtual int vv\\((void|)\\);))*${ws}\} \[*\]+$nl$gdb_prompt $" { + pass "ptype pVv (obsolescent gcc or gdb)" + } + -re ".*$gdb_prompt $" { + fail "ptype pVv" + } + timeout { + fail "ptype pVv (timeout)" + } + } + + send_gdb "ptype pVe\n" + gdb_expect { + -re "type = class V : public VA, public VB \{${ws}public:${ws}int w;${ws}V & operator=\\(V const ?&\\);${ws}V\\((V const|const V) ?&\\);${ws}V\\((void|)\\);${ws}int f\\((void|)\\);${ws}virtual int vv\\((void|)\\);${ws}\} \[*\]+$nl$gdb_prompt $" { + pass "ptype pVe" + } + -re "type = class V : public VA, public VB \{${ws}public:${ws}int w;${ws}int f \\((void|)\\);${ws}virtual int vv \\((void|)\\);${ws}\} \[*\]+$nl$gdb_prompt $" { + pass "ptype pVe (aCC)" + } + -re "type = class V : public VA, public VB \{${ws}public:${ws}int w;((${ws}V & operator=\\(V const ?&\\);)|(${ws}V\\(V const ?&\\);)|(${ws}V\\((void|)\\);)|(${ws}int f\\((void|)\\);)|(${ws}virtual int vv\\((void|)\\);))*${ws}\} \[*\]+$nl$gdb_prompt $" { + pass "ptype pVe (obsolescent gcc or gdb)" + } + -re ".*$gdb_prompt $" { + fail "ptype pVe" + } + timeout { + fail "ptype pVe (timeout)" + } + } + + send_gdb "ptype pVd\n" + gdb_expect { + -re "type = class V : public VA, public VB \{${ws}public:${ws}int w;${ws}V & operator=\\(V const ?&\\);${ws}V\\((V const|const V) ?&\\);${ws}V\\((void|)\\);${ws}int f\\((void|)\\);${ws}virtual int vv\\((void|)\\);${ws}\} \[*\]+$nl$gdb_prompt $" { + pass "ptype pVd" + } + -re "type = class V : public VA, public VB \{${ws}public:${ws}int w;${ws}int f \\((void|)\\);${ws}virtual int vv \\((void|)\\);${ws}\} \[*\]+$nl$gdb_prompt $" { + pass "ptype pVd (aCC)" + } + -re "type = class V : public VA, public VB \{${ws}public:${ws}int w;((${ws}V & operator=\\(V const ?&\\);)|(${ws}V\\(V const ?&\\);)|(${ws}V\\((void|)\\);)|(${ws}int f\\((void|)\\);)|(${ws}virtual int vv\\((void|)\\);))*${ws}\} \[*\]+$nl$gdb_prompt $" { + pass "ptype pVd (obsolescent gcc or gdb)" + } + -re ".*$gdb_prompt $" { + fail "ptype pVd" + } + timeout { + fail "ptype pVd (timeout)" + } + } + + send_gdb "ptype pADe\n" + gdb_expect { + -re "type = class AD \{${ws}public:${ws}AD & operator=\\(AD const ?&\\);${ws}AD\\((AD const|const AD) ?&\\);${ws}AD\\((void|)\\);${ws}virtual int vg\\((void|)\\);${ws}\} \[*\]+$nl$gdb_prompt $" { + pass "ptype pADe" + } + -re "type = class AD \{${ws}public:${ws}virtual int vg \\((void|)\\);${ws}\} \[*\]+$nl$gdb_prompt $" { + pass "ptype pADe (aCC)" + } + -re "type = class AD \{${ws}public:((${ws}AD & operator=\\(AD const ?&\\);)|(${ws}AD\\(AD const ?&\\);)|(${ws}AD\\((void|)\\);)|(${ws}virtual int vg\\((void|)\\);))*${ws}\} \[*\]+$nl$gdb_prompt $" { + pass "ptype pADe (obsolescent gcc or gdb)" + } + -re ".*$gdb_prompt $" { + fail "ptype pADe" + } + timeout { + fail "ptype pADe (timeout)" + } + } + + send_gdb "ptype pEe\n" + gdb_expect { + -re "type = class E : public B, public virtual V, public D, public C \{${ws}public:${ws}int e;${ws}E & operator=\\(E const ?&\\);${ws}E\\(int, E const ?&\\);${ws}E\\(int\\);${ws}virtual int f\\((void|)\\);${ws}virtual int vg\\((void|)\\);${ws}virtual int vv\\((void|)\\);${ws}\} \[*\]+$nl$gdb_prompt $" { + pass "ptype pEe" + } + -re "type = class E : public B, public virtual V, public D, public C \{${ws}public:${ws}int e;${ws}E & operator=\\(E const ?&\\);${ws}E\\((E const|const E) ?&\\);${ws}E\\((void|)\\);${ws}virtual int f\\((void|)\\);${ws}virtual int vg\\((void|)\\);${ws}virtual int vv\\((void|)\\);${ws}\} \[*\]+$nl$gdb_prompt $" { + pass "ptype pEe" + } + -re "type = class E : public B, public virtual V, public D, public C \{${ws}public:${ws}int e;${ws}virtual int f \\((void|)\\);${ws}virtual int vg \\((void|)\\);${ws}virtual int vv \\((void|)\\);${ws}\} \[*\]+$nl$gdb_prompt $" { + pass "ptype pEe (aCC)" + } + -re "type = class E : public B, public virtual V, public D, public C \{${ws}public:${ws}int e;((${ws}E & operator=\\(E const ?&\\);)|(${ws}E\\(int, E const ?&\\);)|(${ws}E\\(int\\);)|(${ws}virtual int f\\((void|)\\);)|(${ws}virtual int vg\\((void|)\\);)|(${ws}virtual int vv\\((void|)\\);))*${ws}\} \[*\]+$nl$gdb_prompt $" { + pass "ptype pEe (obsolescent gcc or gdb)" + } + -re ".*$gdb_prompt $" { + fail "ptype pEe" + } + timeout { + fail "ptype pEe (timeout)" + } + } + + send_gdb "ptype pVB\n" + gdb_expect { + -re "type = class VB \{${ws}public:${ws}int vb;${ws}VB & operator=\\(VB const ?&\\);${ws}VB\\((VB const|const VB) ?&\\);${ws}VB\\((void|)\\);${ws}int fvb\\((void|)\\);${ws}virtual int vvb\\((void|)\\);${ws}\} \[*\]+$nl$gdb_prompt $" { + pass "ptype pVB" + } + -re "type = class VB \{${ws}public:${ws}int vb;${ws}int fvb \\((void|)\\);${ws}virtual int vvb \\((void|)\\);${ws}\} \[*\]+$nl$gdb_prompt $" { + pass "ptype pVB (aCC)" + } + -re "type = class VB \{${ws}public:${ws}int vb;((${ws}VB & operator=\\(VB const ?&\\);)|(${ws}VB\\(VB const ?&\\);)|(${ws}VB\\((void|)\\);)|(${ws}int fvb\\((void|)\\);)|(${ws}virtual int vvb\\((void|)\\);))*${ws}\} \[*\]+$nl$gdb_prompt $" { + pass "ptype pVB (obsolescent gcc or gdb)" + } + -re ".*$gdb_prompt $" { + fail "ptype pVB" + } + timeout { + fail "ptype pVB (timeout)" + } + } +} + +# +# Test calling of virtual functions. +# + +proc test_virtual_calls {} { + global gdb_prompt + global GDB + global nl + + if [target_info exists gdb,cannot_call_functions] { + setup_xfail "*-*-*" 2416 + fail "This target can not call functions" + return 0 + } + + send_gdb "print pAe->f()\n" + gdb_expect { + -re ".* = 20$nl$gdb_prompt $" { pass "print pAe->f()" } + -re "Cannot invoke functions on this machine.*$gdb_prompt $" { + fail "print pAe->f() (cannot invoke functions, skipping virtual calls)" + return 0 + } + -re ".*Cannot access memory at address 0x8.*$gdb_prompt $" { + fail "print pAe->f() \ +(known failure with gcc cygnus-2.4.5-930417, skipping virtual calls)" + return 0 + } + -re "Cannot resolve .* to any overloaded instance.*$gdb_prompt $" { + setup_xfail hppa*-*-* CLLbs16899 + fail "print pAe->f()" + } + -re ".*$gdb_prompt $" { fail "print pAe->f()" } + timeout { fail "print pAe->f() (timeout)" } + eof { fail "print pAe->f() ($GDB dumped core) (FIXME)" ; gdb_virtfunc_restart; return } + } + + send_gdb "print pAa->f()\n" + gdb_expect { + -re ".* = 1$nl$gdb_prompt $" { pass "print pAa->f()" } + -re "Cannot resolve .* to any overloaded instance.*$gdb_prompt $" { + setup_xfail hppa*-*-* CLLbs16899 + fail "print pAa->f()" + } + -re ".*$gdb_prompt $" { fail "print pAa->f()" } + timeout { fail "print pAa->f() (timeout)" } + eof { fail "print pAa->f() ($GDB dumped core) (FIXME)" ; gdb_virtfunc_restart; return } + } + + send_gdb "print pDe->vg()\n" + gdb_expect { + -re ".* = 202$nl$gdb_prompt $" { pass "print pDe->vg()" } + -re "Cannot resolve .* to any overloaded instance.*$gdb_prompt $" { + setup_xfail hppa*-*-* CLLbs16899 + fail "print pDe->vg()" + } + -re ".*$gdb_prompt $" { fail "print pDe->vg()" } + timeout { fail "print pDe->vg() (timeout)" } + eof { fail "print pDe->vg() ($GDB dumped core) (FIXME)" ; gdb_virtfunc_restart; return } + } + + send_gdb "print pADe->vg()\n" + gdb_expect { + -re ".* = 202$nl$gdb_prompt $" { pass "print pADe->vg()" } + -re "Cannot resolve .* to any overloaded instance.*$gdb_prompt $" { + setup_xfail hppa*-*-* CLLbs16899 + fail "print pADe->vg()" + } + -re ".*$gdb_prompt $" { fail "print pADe->vg()" } + timeout { fail "print pADe->vg() (timeout)" } + eof { fail "print pADe->vg() ($GDB dumped core) (FIXME)" ; gdb_virtfunc_restart; return } + } + + send_gdb "print pDd->vg()\n" + gdb_expect { + -re ".* = 101$nl$gdb_prompt $" { pass "print pDd->vg()" } + -re "Cannot resolve .* to any overloaded instance.*$gdb_prompt $" { + setup_xfail hppa*-*-* CLLbs16899 + fail "print pDd->vg()" + } + -re ".*$gdb_prompt $" { fail "print pDd->vg()" } + timeout { fail "print pDd->vg() (timeout)" } + eof { fail "print pDd->vg() ($GDB dumped core) (FIXME)" ; gdb_virtfunc_restart; return } + } + + send_gdb "print pEe->vvb()\n" + gdb_expect { + -re ".* = 411$nl$gdb_prompt $" { pass "print pEe->vvb()" } + -re "Cannot resolve .* to any overloaded instance.*$gdb_prompt $" { + setup_xfail hppa*-*-* CLLbs16899 + fail "print pEe->vvb()" + } + -re ".*$gdb_prompt $" { fail "print pEe->vvb()" } + timeout { fail "print pEe->vvb() (timeout)" } + eof { fail "print pEe->vvb() ($GDB dumped core) (FIXME)" ; gdb_virtfunc_restart; return } + } + + send_gdb "print pVB->vvb()\n" + gdb_expect { + -re ".* = 407$nl$gdb_prompt $" { pass "print pVB->vvb()" } + -re "Cannot resolve .* to any overloaded instance.*$gdb_prompt $" { + setup_xfail hppa*-*-* CLLbs16899 + fail "print pVB->vvb()" + } + -re ".*$gdb_prompt $" { fail "print pVB->vvb()" } + timeout { fail "print pVB->vvb() (timeout)" } + eof { fail "print pVB->vvb() ($GDB dumped core) (FIXME)" ; gdb_virtfunc_restart; return } + } + + send_gdb "print pBe->vvb()\n" + gdb_expect { + -re ".* = 411$nl$gdb_prompt $" { pass "print pBe->vvb()" } + -re "Cannot resolve .* to any overloaded instance.*$gdb_prompt $" { + setup_xfail hppa*-*-* CLLbs16899 + fail "print pBe->vvb()" + } + -re ".*$gdb_prompt $" { fail "print pBe->vvb()" } + timeout { fail "print pBe->vvb() (timeout)" } + eof { fail "print pBe->vvb() ($GDB dumped core) (FIXME)" ; gdb_virtfunc_restart; return } + } + + send_gdb "print pDe->vvb()\n" + gdb_expect { + -re ".* = 411$nl$gdb_prompt $" { pass "print pDe->vvb()" } + -re "Cannot resolve .* to any overloaded instance.*$gdb_prompt $" { + setup_xfail hppa*-*-* CLLbs16899 + fail "print pDe->vvb()" + } + -re ".*$gdb_prompt $" { fail "print pDe->vvb()" } + timeout { fail "print pDe->vvb() (timeout)" } + eof { fail "print pDe->vvb() ($GDB dumped core) (FIXME)" ; gdb_virtfunc_restart; return } + } + + send_gdb "print pEe->vd()\n" + gdb_expect { + -re ".* = 282$nl$gdb_prompt $" { pass "print pEe->vd()" } + -re "Cannot resolve .* to any overloaded instance.*$gdb_prompt $" { + setup_xfail hppa*-*-* CLLbs16899 + fail "print pEe->vd()" + } + -re ".*$gdb_prompt $" { fail "print pEe->vd()" } + timeout { fail "print pEe->vd() (timeout)" } + eof { fail "print pEe->vd() ($GDB dumped core) (FIXME)" ; gdb_virtfunc_restart; return } + } + + send_gdb "print pEe->fvb()\n" + gdb_expect { + -re ".* = 311$nl$gdb_prompt $" { pass "print pEe->fvb()" } + -re "Cannot resolve .* to any overloaded instance.*$gdb_prompt $" { + setup_xfail hppa*-*-* CLLbs16899 + fail "print pEe->fvb()" + } + -re ".*$gdb_prompt $" { fail "print pEe->fvb()" } + timeout { fail "print pEe->fvb() (timeout)" } + eof { fail "print pEe->fvb() ($GDB dumped core) (FIXME)" ; gdb_virtfunc_restart; return } + } + + # fails on target=native, host=i686-pc-linux-gnu%rh-7.2, + # gdb=HEAD%2002-02-16, gcc=2.95.3, goption=-gdwarf-2. + # + # fails on target=native, host=i686-pc-linux-gnu%rh-7.2, + # gdb=HEAD%2002-02-16, gcc=2.95.3, goption=-gstabs+. + # + # fails on target=native, host=i686-pc-linux-gnu%rh-7.2, + # gdb=HEAD%2002-02-16, gcc=3.0.3, goption=-gdwarf-2. + # + # fails on target=native, host=i686-pc-linux-gnu%rh-7.2, + # gdb=HEAD%2002-02-16, gcc=3.0.3, goption=-gstabs+. + # + # fails on target=native, host=i686-pc-linux-gnu%rh-7.2, + # gdb=HEAD%2002-02-16, gcc=3.0.4-20020215, goption=-gdwarf-2. + # + # fails on target=native, host=i686-pc-linux-gnu%rh-7.2, + # gdb=HEAD%2002-02-16, gcc=3.0.4-20020215, goption=-gstabs+. + # + # fails on target=native, host=i686-pc-linux-gnu%rh-7.2, + # gdb=HEAD%2002-02-16, gcc=gcc-3_0-branch%2002-02-16, goption=-gdwarf-2. + # + # fails on target=native, host=i686-pc-linux-gnu%rh-7.2, + # gdb=HEAD%2002-02-16, gcc=gcc-3_0-branch%2002-02-16, goption=-gstabs+. + # + # fails on target=native, host=i686-pc-linux-gnu%rh-7.2, + # gdb=HEAD%2002-02-16, gcc=HEAD%2002-02-16, goption=-gdwarf-2. + # + # fails on target=native, host=i686-pc-linux-gnu%rh-7.2, + # gdb=HEAD%2002-02-16, gcc=HEAD%2002-02-16, goption=-gstabs+. + # + # -- chastain 2002-02-20 + + send_gdb "print pEe->D::vg()\n" + gdb_expect { + -re ".* = 102$nl$gdb_prompt $" { pass "print pEe->D::vg()" } + -re "Attempt to take address of value not located in memory.\r\n$gdb_prompt $" + { kfail "gdb/1064" "print pEe->D::vg()" } + -re ".*$gdb_prompt $" { fail "print pEe->D::vg()" } + timeout { fail "print pEe->D::vg() (timeout)" } + eof { fail "print pEe->D::vg() ($GDB dumped core) (FIXME)" ; gdb_virtfunc_restart; return } + } +} + +proc do_tests {} { + global prms_id + global bug_id + + set prms_id 0 + set bug_id 0 + + gdb_start; + gdb_virtfunc_init; + + runto_main + + test_ptype_of_classes + + if [ runto 'test_calls' ] then { + test_virtual_calls + } +} + +do_tests diff --git a/gdb/testsuite/gdb.disasm/t01_mov.exp b/gdb/testsuite/gdb.disasm/t01_mov.exp new file mode 100644 index 0000000..50910e9 --- /dev/null +++ b/gdb/testsuite/gdb.disasm/t01_mov.exp @@ -0,0 +1,2088 @@ +# Copyright (C) 2003 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# Please email any bugs, comments, and/or additions to this file to: +# bug-gdb@prep.ai.mit.edu + +# This file was written by Michael Snyder (msnyder@redhat.com) + +if $tracelevel then { + strace $tracelevel +} + +if ![istarget "h8300*-*-*"] { + verbose "Tests ignored for all but h8300s based targets." + return +} + +set prms_id 0 +set bug_id 0 + +set testfile "t01_mov" +set srcfile ${srcdir}/${subdir}/${testfile}.s +set objfile ${objdir}/${subdir}/${testfile}.o +set binfile ${objdir}/${subdir}/${testfile}.x + +set asm-flags ""; +set link-flags "-m h8300sxelf"; + + +if {[target_assemble $srcfile $objfile "${asm-flags}"] != ""} then { + gdb_suppress_entire_file "Testcase assembly failed, so all tests in this file will automatically fail." +} + +if {[target_link $objfile $binfile "${link-flags}"] != ""} then { + gdb_suppress_entire_file "Testcase link failed, so all tests in this file will automatically fail." +} + +gdb_start +gdb_reinitialize_dir $srcdir/$subdir +gdb_load $binfile + +gdb_test "x/i _start" "mov.b #0x12(:8|),r3h" \ + "mov.b #0x12:8,r3h" +gdb_test "x" "mov.b #0x12(:8|),@er3" \ + "mov.b #0x12:8,@er3" +gdb_test "x" "mov.b #0x12(:8|),@\\(0x1:2,er3\\)" \ + "mov.b #0x12:8,@(0x1:2,er3)" +gdb_test "x" "mov.b #0x12(:8|),@-er3" \ + "mov.b #0x12:8,@-er3" +gdb_test "x" "mov.b #0x12(:8|),@er3\\+" \ + "mov.b #0x12:8,@er3+" +gdb_test "x" "mov.b #0x12(:8|),@er3-" \ + "mov.b #0x12:8,@er3-" +gdb_test "x" "mov.b #0x12(:8|),@\\+er3" \ + "mov.b #0x12:8,@+er3" +gdb_test "x" "mov.b #0x12(:8|),@\\(0x1234:16,er3\\)" \ + "mov.b #0x12:8,@(0x1234:16,er3)" +gdb_test "x" "mov.b #0x12(:8|),@\\(0x12345678:32,er3\\)" \ + "mov.b #0x12:8,@(0x12345678:32,er3)" +gdb_test "x" "mov.b #0x12(:8|),@\\(0x1234:16,r3l.b\\)" \ + "mov.b #0x12:8,@(0x1234:16,r3l.b)" +gdb_test "x" "mov.b #0x12(:8|),@\\(0x1234:16,r3.w\\)" \ + "mov.b #0x12:8,@(0x1234:16,r3.w)" +gdb_test "x" "mov.b #0x12(:8|),@\\(0x1234:16,er3.l\\)" \ + "mov.b #0x12:8,@(0x1234:16,er3.l)" +gdb_test "x" "mov.b #0x12(:8|),@\\(0x12345678:32,r3l.b\\)" \ + "mov.b #0x12:8,@(0x12345678:32,r3l.b)" +gdb_test "x" "mov.b #0x12(:8|),@\\(0x12345678:32,r3.w\\)" \ + "mov.b #0x12:8,@(0x12345678:32,r3.w)" +gdb_test "x" "mov.b #0x12(:8|),@\\(0x12345678:32,er3.l\\)" \ + "mov.b #0x12:8,@(0x12345678:32,er3.l)" +gdb_test "x" "mov.b #0x12(:8|),@0x1234:16" \ + "mov.b #0x12:8,@0x1234:16" +gdb_test "x" "mov.b #0x12(:8|),@0x12345678:32" \ + "mov.b #0x12:8,@0x12345678:32" +gdb_test "x" "mov.b #0x1(:4|),@0x1234:16" \ + "mov.b #0x1:4,@0x1234:16" +gdb_test "x" "mov.b #0x1(:4|),@0x12345678:32" \ + "mov.b #0x1:4,@0x12345678:32" +gdb_test "x" "mov.b r3h,r1h" \ + "mov.b r3h,r1h" +gdb_test "x" "mov.b r3h,@er1" \ + "mov.b r3h,@er1" +gdb_test "x" "mov.b r3h,@\\(0x1:2,er1\\)" \ + "mov.b r3h,@(0x1:2,er1)" +gdb_test "x" "mov.b r3h,@-er1" \ + "mov.b r3h,@-er1" +gdb_test "x" "mov.b r3h,@er1\\+" \ + "mov.b r3h,@er1+" +gdb_test "x" "mov.b r3h,@er1-" \ + "mov.b r3h,@er1-" +gdb_test "x" "mov.b r3h,@\\+er1" \ + "mov.b r3h,@+er1" +gdb_test "x" "mov.b r3h,@\\(0x1234:16,er1\\)" \ + "mov.b r3h,@(0x1234:16,er1)" +gdb_test "x" "mov.b r3h,@\\(0x12345678:32,er1\\)" \ + "mov.b r3h,@(0x12345678:32,er1)" +gdb_test "x" "mov.b r3h,@\\(0x1234:16,r1l.b\\)" \ + "mov.b r3h,@(0x1234:16,r1l.b)" +gdb_test "x" "mov.b r3h,@\\(0x1234:16,r1.w\\)" \ + "mov.b r3h,@(0x1234:16,r1.w)" +gdb_test "x" "mov.b r3h,@\\(0x1234:16,er1.l\\)" \ + "mov.b r3h,@(0x1234:16,er1.l)" +gdb_test "x" "mov.b r3h,@\\(0x12345678:32,r1l.b\\)" \ + "mov.b r3h,@(0x12345678:32,r1l.b)" +gdb_test "x" "mov.b r3h,@\\(0x12345678:32,r1.w\\)" \ + "mov.b r3h,@(0x12345678:32,r1.w)" +gdb_test "x" "mov.b r3h,@\\(0x12345678:32,er1.l\\)" \ + "mov.b r3h,@(0x12345678:32,er1.l)" +gdb_test "x" "mov.b r3h,@0x12(:8|)" \ + "mov.b r3h,@0x12:8" +gdb_test "x" "mov.b r3h,@0x1234:16" \ + "mov.b r3h,@0x1234:16" +gdb_test "x" "mov.b r3h,@0x12345678:32" \ + "mov.b r3h,@0x12345678:32" +gdb_test "x" "mov.b @er3,r1h" \ + "mov.b @er3,r1h" +gdb_test "x" "mov.b @\\(0x1:2,er3\\),r1h" \ + "mov.b @(0x1:2,er3),r1h" +gdb_test "x" "mov.b @er3\\+,r1h" \ + "mov.b @er3+,r1h" +gdb_test "x" "mov.b @-er3,r1h" \ + "mov.b @-er3,r1h" +gdb_test "x" "mov.b @\\+er3,r1h" \ + "mov.b @+er3,r1h" +gdb_test "x" "mov.b @er3-,r1h" \ + "mov.b @er3-,r1h" +gdb_test "x" "mov.b @\\(0x1234:16,er3\\),r1h" \ + "mov.b @(0x1234:16,er3),r1h" +gdb_test "x" "mov.b @\\(0x12345678:32,er3\\),r1h" \ + "mov.b @(0x12345678:32,er3),r1h" +gdb_test "x" "mov.b @\\(0x1234:16,r3l.b\\),r1h" \ + "mov.b @(0x1234:16,r3l.b),r1h" +gdb_test "x" "mov.b @\\(0x1234:16,r3.w\\),r1h" \ + "mov.b @(0x1234:16,r3.w),r1h" +gdb_test "x" "mov.b @\\(0x1234:16,er3.l\\),r1h" \ + "mov.b @(0x1234:16,er3.l),r1h" +gdb_test "x" "mov.b @\\(0x12345678:32,r3l.b\\),r1h" \ + "mov.b @(0x12345678:32,r3l.b),r1h" +gdb_test "x" "mov.b @\\(0x12345678:32,r3.w\\),r1h" \ + "mov.b @(0x12345678:32,r3.w),r1h" +gdb_test "x" "mov.b @\\(0x12345678:32,er3.l\\),r1h" \ + "mov.b @(0x12345678:32,er3.l),r1h" +gdb_test "x" "mov.b @0x12(:8|),r3h" \ + "mov.b @0x12:8,r3h" +gdb_test "x" "mov.b @0x1234:16,r3h" \ + "mov.b @0x1234:16,r3h" +gdb_test "x" "mov.b @0x12345678:32,r3h" \ + "mov.b @0x12345678:32,r3h" +gdb_test "x" "mov.b @er3,@er1" \ + "mov.b @er3,@er1" +gdb_test "x" "mov.b @er3,@\\(0x1:2,er1\\)" \ + "mov.b @er3,@(0x1:2,er1)" +gdb_test "x" "mov.b @er3,@er1\\+" \ + "mov.b @er3,@er1+" +gdb_test "x" "mov.b @er3,@-er1" \ + "mov.b @er3,@-er1" +gdb_test "x" "mov.b @er3,@\\+er1" \ + "mov.b @er3,@+er1" +gdb_test "x" "mov.b @er3,@er1-" \ + "mov.b @er3,@er1-" +gdb_test "x" "mov.b @er3,@\\(0x1234:16,er1\\)" \ + "mov.b @er3,@(0x1234:16,er1)" +gdb_test "x" "mov.b @er3,@\\(0x12345678:32,er1\\)" \ + "mov.b @er3,@(0x12345678:32,er1)" +gdb_test "x" "mov.b @er3,@\\(0x1234:16,r1l.b\\)" \ + "mov.b @er3,@(0x1234:16,r1l.b)" +gdb_test "x" "mov.b @er3,@\\(0x1234:16,r1.w\\)" \ + "mov.b @er3,@(0x1234:16,r1.w)" +gdb_test "x" "mov.b @er3,@\\(0x1234:16,er1.l\\)" \ + "mov.b @er3,@(0x1234:16,er1.l)" +gdb_test "x" "mov.b @er3,@\\(0x12345678:32,r1l.b\\)" \ + "mov.b @er3,@(0x12345678:32,r1l.b)" +gdb_test "x" "mov.b @er3,@\\(0x12345678:32,r1.w\\)" \ + "mov.b @er3,@(0x12345678:32,r1.w)" +gdb_test "x" "mov.b @er3,@\\(0x12345678:32,er1.l\\)" \ + "mov.b @er3,@(0x12345678:32,er1.l)" +gdb_test "x" "mov.b @er3,@0x1234:16" \ + "mov.b @er3,@0x1234:16" +gdb_test "x" "mov.b @er3,@0x12345678:32" \ + "mov.b @er3,@0x12345678:32" +gdb_test "x" "mov.b @\\(0x1:2,er3\\),@er1" \ + "mov.b @(0x1:2,er3),@er1" +gdb_test "x" "mov.b @\\(0x1:2,er3\\),@\\(0x1:2,er1\\)" \ + "mov.b @(0x1:2,er3),@(0x1:2,er1)" +gdb_test "x" "mov.b @\\(0x1:2,er3\\),@er1\\+" \ + "mov.b @(0x1:2,er3),@er1+" +gdb_test "x" "mov.b @\\(0x1:2,er3\\),@-er1" \ + "mov.b @(0x1:2,er3),@-er1" +gdb_test "x" "mov.b @\\(0x1:2,er3\\),@\\+er1" \ + "mov.b @(0x1:2,er3),@+er1" +gdb_test "x" "mov.b @\\(0x1:2,er3\\),@er1-" \ + "mov.b @(0x1:2,er3),@er1-" +gdb_test "x" "mov.b @\\(0x1:2,er3\\),@\\(0x1234:16,er1\\)" \ + "mov.b @(0x1:2,er3),@(0x1234:16,er1)" +gdb_test "x" "mov.b @\\(0x1:2,er3\\),@\\(0x12345678:32,er1\\)" \ + "mov.b @(0x1:2,er3),@(0x12345678:32,er1)" +gdb_test "x" "mov.b @\\(0x1:2,er3\\),@\\(0x1234:16,r1l.b\\)" \ + "mov.b @(0x1:2,er3),@(0x1234:16,r1l.b)" +gdb_test "x" "mov.b @\\(0x1:2,er3\\),@\\(0x1234:16,r1.w\\)" \ + "mov.b @(0x1:2,er3),@(0x1234:16,r1.w)" +gdb_test "x" "mov.b @\\(0x1:2,er3\\),@\\(0x1234:16,er1.l\\)" \ + "mov.b @(0x1:2,er3),@(0x1234:16,er1.l)" +gdb_test "x" "mov.b @\\(0x1:2,er3\\),@\\(0x12345678:32,r1l.b\\)" \ + "mov.b @(0x1:2,er3),@(0x12345678:32,r1l.b)" +gdb_test "x" "mov.b @\\(0x1:2,er3\\),@\\(0x12345678:32,r1.w\\)" \ + "mov.b @(0x1:2,er3),@(0x12345678:32,r1.w)" +gdb_test "x" "mov.b @\\(0x1:2,er3\\),@\\(0x12345678:32,er1.l\\)" \ + "mov.b @(0x1:2,er3),@(0x12345678:32,er1.l)" +gdb_test "x" "mov.b @\\(0x1:2,er3\\),@0x1234:16" \ + "mov.b @(0x1:2,er3),@0x1234:16" +gdb_test "x" "mov.b @\\(0x1:2,er3\\),@0x12345678:32" \ + "mov.b @(0x1:2,er3),@0x12345678:32" +gdb_test "x" "mov.b @-er3,@er1" \ + "mov.b @-er3,@er1" +gdb_test "x" "mov.b @-er3,@\\(0x1:2,er1\\)" \ + "mov.b @-er3,@(0x1:2,er1)" +gdb_test "x" "mov.b @-er3,@er1\\+" \ + "mov.b @-er3,@er1+" +gdb_test "x" "mov.b @-er3,@-er1" \ + "mov.b @-er3,@-er1" +gdb_test "x" "mov.b @-er3,@\\+er1" \ + "mov.b @-er3,@+er1" +gdb_test "x" "mov.b @-er3,@er1-" \ + "mov.b @-er3,@er1-" +gdb_test "x" "mov.b @-er3,@\\(0x1234:16,er1\\)" \ + "mov.b @-er3,@(0x1234:16,er1)" +gdb_test "x" "mov.b @-er3,@\\(0x12345678:32,er1\\)" \ + "mov.b @-er3,@(0x12345678:32,er1)" +gdb_test "x" "mov.b @-er3,@\\(0x1234:16,r1l.b\\)" \ + "mov.b @-er3,@(0x1234:16,r1l.b)" +gdb_test "x" "mov.b @-er3,@\\(0x1234:16,r1.w\\)" \ + "mov.b @-er3,@(0x1234:16,r1.w)" +gdb_test "x" "mov.b @-er3,@\\(0x1234:16,er1.l\\)" \ + "mov.b @-er3,@(0x1234:16,er1.l)" +gdb_test "x" "mov.b @-er3,@\\(0x12345678:32,r1l.b\\)" \ + "mov.b @-er3,@(0x12345678:32,r1l.b)" +gdb_test "x" "mov.b @-er3,@\\(0x12345678:32,r1.w\\)" \ + "mov.b @-er3,@(0x12345678:32,r1.w)" +gdb_test "x" "mov.b @-er3,@\\(0x12345678:32,er1.l\\)" \ + "mov.b @-er3,@(0x12345678:32,er1.l)" +gdb_test "x" "mov.b @-er3,@0x1234:16" \ + "mov.b @-er3,@0x1234:16" +gdb_test "x" "mov.b @-er3,@0x12345678:32" \ + "mov.b @-er3,@0x12345678:32" +gdb_test "x" "mov.b @er3\\+,@er1" \ + "mov.b @er3+,@er1" +gdb_test "x" "mov.b @er3\\+,@\\(0x1:2,er1\\)" \ + "mov.b @er3+,@(0x1:2,er1)" +gdb_test "x" "mov.b @er3\\+,@er1\\+" \ + "mov.b @er3+,@er1+" +gdb_test "x" "mov.b @er3\\+,@-er1" \ + "mov.b @er3+,@-er1" +gdb_test "x" "mov.b @er3\\+,@\\+er1" \ + "mov.b @er3+,@+er1" +gdb_test "x" "mov.b @er3\\+,@er1-" \ + "mov.b @er3+,@er1-" +gdb_test "x" "mov.b @er3\\+,@\\(0x1234:16,er1\\)" \ + "mov.b @er3+,@(0x1234:16,er1)" +gdb_test "x" "mov.b @er3\\+,@\\(0x12345678:32,er1\\)" \ + "mov.b @er3+,@(0x12345678:32,er1)" +gdb_test "x" "mov.b @er3\\+,@\\(0x1234:16,r1l.b\\)" \ + "mov.b @er3+,@(0x1234:16,r1l.b)" +gdb_test "x" "mov.b @er3\\+,@\\(0x1234:16,r1.w\\)" \ + "mov.b @er3+,@(0x1234:16,r1.w)" +gdb_test "x" "mov.b @er3\\+,@\\(0x1234:16,er1.l\\)" \ + "mov.b @er3+,@(0x1234:16,er1.l)" +gdb_test "x" "mov.b @er3\\+,@\\(0x12345678:32,r1l.b\\)" \ + "mov.b @er3+,@(0x12345678:32,r1l.b)" +gdb_test "x" "mov.b @er3\\+,@\\(0x12345678:32,r1.w\\)" \ + "mov.b @er3+,@(0x12345678:32,r1.w)" +gdb_test "x" "mov.b @er3\\+,@\\(0x12345678:32,er1.l\\)" \ + "mov.b @er3+,@(0x12345678:32,er1.l)" +gdb_test "x" "mov.b @er3\\+,@0x1234:16" \ + "mov.b @er3+,@0x1234:16" +gdb_test "x" "mov.b @er3\\+,@0x12345678:32" \ + "mov.b @er3+,@0x12345678:32" +gdb_test "x" "mov.b @er3-,@er1" \ + "mov.b @er3-,@er1" +gdb_test "x" "mov.b @er3-,@\\(0x1:2,er1\\)" \ + "mov.b @er3-,@(0x1:2,er1)" +gdb_test "x" "mov.b @er3-,@er1\\+" \ + "mov.b @er3-,@er1+" +gdb_test "x" "mov.b @er3-,@-er1" \ + "mov.b @er3-,@-er1" +gdb_test "x" "mov.b @er3-,@\\+er1" \ + "mov.b @er3-,@+er1" +gdb_test "x" "mov.b @er3-,@er1-" \ + "mov.b @er3-,@er1-" +gdb_test "x" "mov.b @er3-,@\\(0x1234:16,er1\\)" \ + "mov.b @er3-,@(0x1234:16,er1)" +gdb_test "x" "mov.b @er3-,@\\(0x12345678:32,er1\\)" \ + "mov.b @er3-,@(0x12345678:32,er1)" +gdb_test "x" "mov.b @er3-,@\\(0x1234:16,r1l.b\\)" \ + "mov.b @er3-,@(0x1234:16,r1l.b)" +gdb_test "x" "mov.b @er3-,@\\(0x1234:16,r1.w\\)" \ + "mov.b @er3-,@(0x1234:16,r1.w)" +gdb_test "x" "mov.b @er3-,@\\(0x1234:16,er1.l\\)" \ + "mov.b @er3-,@(0x1234:16,er1.l)" +gdb_test "x" "mov.b @er3-,@\\(0x12345678:32,r1l.b\\)" \ + "mov.b @er3-,@(0x12345678:32,r1l.b)" +gdb_test "x" "mov.b @er3-,@\\(0x12345678:32,r1.w\\)" \ + "mov.b @er3-,@(0x12345678:32,r1.w)" +gdb_test "x" "mov.b @er3-,@\\(0x12345678:32,er1.l\\)" \ + "mov.b @er3-,@(0x12345678:32,er1.l)" +gdb_test "x" "mov.b @er3-,@0x1234:16" \ + "mov.b @er3-,@0x1234:16" +gdb_test "x" "mov.b @er3-,@0x12345678:32" \ + "mov.b @er3-,@0x12345678:32" +gdb_test "x" "mov.b @\\+er3,@er1" \ + "mov.b @+er3,@er1" +gdb_test "x" "mov.b @\\+er3,@\\(0x1:2,er1\\)" \ + "mov.b @+er3,@(0x1:2,er1)" +gdb_test "x" "mov.b @\\+er3,@er1\\+" \ + "mov.b @+er3,@er1+" +gdb_test "x" "mov.b @\\+er3,@-er1" \ + "mov.b @+er3,@-er1" +gdb_test "x" "mov.b @\\+er3,@\\+er1" \ + "mov.b @+er3,@+er1" +gdb_test "x" "mov.b @\\+er3,@er1-" \ + "mov.b @+er3,@er1-" +gdb_test "x" "mov.b @\\+er3,@\\(0x1234:16,er1\\)" \ + "mov.b @+er3,@(0x1234:16,er1)" +gdb_test "x" "mov.b @\\+er3,@\\(0x12345678:32,er1\\)" \ + "mov.b @+er3,@(0x12345678:32,er1)" +gdb_test "x" "mov.b @\\+er3,@\\(0x1234:16,r1l.b\\)" \ + "mov.b @+er3,@(0x1234:16,r1l.b)" +gdb_test "x" "mov.b @\\+er3,@\\(0x1234:16,r1.w\\)" \ + "mov.b @+er3,@(0x1234:16,r1.w)" +gdb_test "x" "mov.b @\\+er3,@\\(0x1234:16,er1.l\\)" \ + "mov.b @+er3,@(0x1234:16,er1.l)" +gdb_test "x" "mov.b @\\+er3,@\\(0x12345678:32,r1l.b\\)" \ + "mov.b @+er3,@(0x12345678:32,r1l.b)" +gdb_test "x" "mov.b @\\+er3,@\\(0x12345678:32,r1.w\\)" \ + "mov.b @+er3,@(0x12345678:32,r1.w)" +gdb_test "x" "mov.b @\\+er3,@\\(0x12345678:32,er1.l\\)" \ + "mov.b @+er3,@(0x12345678:32,er1.l)" +gdb_test "x" "mov.b @\\+er3,@0x1234:16" \ + "mov.b @+er3,@0x1234:16" +gdb_test "x" "mov.b @\\+er3,@0x12345678:32" \ + "mov.b @+er3,@0x12345678:32" +gdb_test "x" "mov.b @\\(0x1234:16,er3\\),@er1" \ + "mov.b @(0x1234:16,er3),@er1" +gdb_test "x" "mov.b @\\(0x1234:16,er3\\),@\\(0x1:2,er1\\)" \ + "mov.b @(0x1234:16,er3),@(0x1:2,er1)" +gdb_test "x" "mov.b @\\(0x1234:16,er3\\),@er1\\+" \ + "mov.b @(0x1234:16,er3),@er1+" +gdb_test "x" "mov.b @\\(0x1234:16,er3\\),@-er1" \ + "mov.b @(0x1234:16,er3),@-er1" +gdb_test "x" "mov.b @\\(0x1234:16,er3\\),@\\+er1" \ + "mov.b @(0x1234:16,er3),@+er1" +gdb_test "x" "mov.b @\\(0x1234:16,er3\\),@er1-" \ + "mov.b @(0x1234:16,er3),@er1-" +gdb_test "x" "mov.b @\\(0x1234:16,er3\\),@\\(0x9abc(:16|),er1\\)" \ + "mov.b @(0x1234:16,er3),@(0x9abc:16,er1)" +gdb_test "x" "mov.b @\\(0x1234:16,er3\\),@\\(0x9abcdef0:32,er1\\)" \ + "mov.b @(0x1234:16,er3),@(0x9abcdef0:32,er1)" +gdb_test "x" "mov.b @\\(0x1234:16,er3\\),@\\(0x9abc(:16|),r1l.b\\)" \ + "mov.b @(0x1234:16,er3),@(0x9abc:16,r1l.b)" +gdb_test "x" "mov.b @\\(0x1234:16,er3\\),@\\(0x9abc(:16|),r1.w\\)" \ + "mov.b @(0x1234:16,er3),@(0x9abc:16,r1.w)" +gdb_test "x" "mov.b @\\(0x1234:16,er3\\),@\\(0x9abc(:16|),er1.l\\)" \ + "mov.b @(0x1234:16,er3),@(0x9abc:16,er1.l)" +gdb_test "x" "mov.b @\\(0x1234:16,er3\\),@\\(0x9abcdef0:32,r1l.b\\)" \ + "mov.b @(0x1234:16,er3),@(0x9abcdef0:32,r1l.b)" +gdb_test "x" "mov.b @\\(0x1234:16,er3\\),@\\(0x9abcdef0:32,r1.w\\)" \ + "mov.b @(0x1234:16,er3),@(0x9abcdef0:32,r1.w)" +gdb_test "x" "mov.b @\\(0x1234:16,er3\\),@\\(0x9abcdef0:32,er1.l\\)" \ + "mov.b @(0x1234:16,er3),@(0x9abcdef0:32,er1.l)" +gdb_test "x" "mov.b @\\(0x1234:16,er3\\),@0x9abc(:16|)" \ + "mov.b @(0x1234:16,er3),@0x9abc:16" +gdb_test "x" "mov.b @\\(0x1234:16,er3\\),@0x9abcdef0:32" \ + "mov.b @(0x1234:16,er3),@0x9abcdef0:32" +gdb_test "x" "mov.b @\\(0x12345678:32,er3\\),@er1" \ + "mov.b @(0x12345678:32,er3),@er1" +gdb_test "x" "mov.b @\\(0x12345678:32,er3\\),@\\(0x1:2,er1\\)" \ + "mov.b @(0x12345678:32,er3),@(0x1:2,er1)" +gdb_test "x" "mov.b @\\(0x12345678:32,er3\\),@er1\\+" \ + "mov.b @(0x12345678:32,er3),@er1+" +gdb_test "x" "mov.b @\\(0x12345678:32,er3\\),@-er1" \ + "mov.b @(0x12345678:32,er3),@-er1" +gdb_test "x" "mov.b @\\(0x12345678:32,er3\\),@\\+er1" \ + "mov.b @(0x12345678:32,er3),@+er1" +gdb_test "x" "mov.b @\\(0x12345678:32,er3\\),@er1-" \ + "mov.b @(0x12345678:32,er3),@er1-" +gdb_test "x" "mov.b @\\(0x12345678:32,er3\\),@\\(0x9abc(:16|),er1\\)" \ + "mov.b @(0x12345678:32,er3),@(0x9abc:16,er1)" +gdb_test "x" "mov.b @\\(0x12345678:32,er3\\),@\\(0x9abcdef0:32,er1\\)" \ + "mov.b @(0x12345678:32,er3),@(0x9abcdef0:32,er1)" +gdb_test "x" "mov.b @\\(0x12345678:32,er3\\),@\\(0x9abc(:16|),r1l.b\\)" \ + "mov.b @(0x12345678:32,er3),@(0x9abc:16,r1l.b)" +gdb_test "x" "mov.b @\\(0x12345678:32,er3\\),@\\(0x9abc(:16|),r1.w\\)" \ + "mov.b @(0x12345678:32,er3),@(0x9abc:16,r1.w)" +gdb_test "x" "mov.b @\\(0x12345678:32,er3\\),@\\(0x9abc(:16|),er1.l\\)" \ + "mov.b @(0x12345678:32,er3),@(0x9abc:16,er1.l)" +gdb_test "x" "mov.b @\\(0x12345678:32,er3\\),@\\(0x9abcdef0:32,r1l.b\\)" \ + "mov.b @(0x12345678:32,er3),@(0x9abcdef0:32,r1l.b)" +gdb_test "x" "mov.b @\\(0x12345678:32,er3\\),@\\(0x9abcdef0:32,r1.w\\)" \ + "mov.b @(0x12345678:32,er3),@(0x9abcdef0:32,r1.w)" +gdb_test "x" "mov.b @\\(0x12345678:32,er3\\),@\\(0x9abcdef0:32,er1.l\\)" \ + "mov.b @(0x12345678:32,er3),@(0x9abcdef0:32,er1.l)" +gdb_test "x" "mov.b @\\(0x12345678:32,er3\\),@0x9abc(:16|)" \ + "mov.b @(0x12345678:32,er3),@0x9abc:16" +gdb_test "x" "mov.b @\\(0x12345678:32,er3\\),@0x9abcdef0:32" \ + "mov.b @(0x12345678:32,er3),@0x9abcdef0:32" +gdb_test "x" "mov.b @\\(0x1234:16,r3l.b\\),@er1" \ + "mov.b @(0x1234:16,r3l.b),@er1" +gdb_test "x" "mov.b @\\(0x1234:16,r3l.b\\),@\\(0x1:2,er1\\)" \ + "mov.b @(0x1234:16,r3l.b),@(0x1:2,er1)" +gdb_test "x" "mov.b @\\(0x1234:16,r3l.b\\),@er1\\+" \ + "mov.b @(0x1234:16,r3l.b),@er1+" +gdb_test "x" "mov.b @\\(0x1234:16,r3l.b\\),@-er1" \ + "mov.b @(0x1234:16,r3l.b),@-er1" +gdb_test "x" "mov.b @\\(0x1234:16,r3l.b\\),@\\+er1" \ + "mov.b @(0x1234:16,r3l.b),@+er1" +gdb_test "x" "mov.b @\\(0x1234:16,r3l.b\\),@er1-" \ + "mov.b @(0x1234:16,r3l.b),@er1-" +gdb_test "x" "mov.b @\\(0x1234:16,r3l.b\\),@\\(0x9abc(:16|),r1l.b\\)" \ + "mov.b @(0x1234:16,r3l.b),@(0x9abc:16,r1l.b)" +gdb_test "x" "mov.b @\\(0x1234:16,r3l.b\\),@\\(0x9abc(:16|),r1.w\\)" \ + "mov.b @(0x1234:16,r3l.b),@(0x9abc:16,r1.w)" +gdb_test "x" "mov.b @\\(0x1234:16,r3l.b\\),@\\(0x9abc(:16|),er1.l\\)" \ + "mov.b @(0x1234:16,r3l.b),@(0x9abc:16,er1.l)" +gdb_test "x" "mov.b @\\(0x1234:16,r3l.b\\),@\\(0x9abcdef0:32,r1l.b\\)" \ + "mov.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,r1l.b)" +gdb_test "x" "mov.b @\\(0x1234:16,r3l.b\\),@\\(0x9abcdef0:32,r1.w\\)" \ + "mov.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,r1.w)" +gdb_test "x" "mov.b @\\(0x1234:16,r3l.b\\),@\\(0x9abcdef0:32,er1.l\\)" \ + "mov.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1.l)" +gdb_test "x" "mov.b @\\(0x1234:16,r3l.b\\),@0x9abc(:16|)" \ + "mov.b @(0x1234:16,r3l.b),@0x9abc:16" +gdb_test "x" "mov.b @\\(0x1234:16,r3l.b\\),@0x9abcdef0:32" \ + "mov.b @(0x1234:16,r3l.b),@0x9abcdef0:32" +gdb_test "x" "mov.b @\\(0x1234:16,r3.w\\),@er1" \ + "mov.b @(0x1234:16,r3.w),@er1" +gdb_test "x" "mov.b @\\(0x1234:16,r3.w\\),@\\(0x1:2,er1\\)" \ + "mov.b @(0x1234:16,r3.w),@(0x1:2,er1)" +gdb_test "x" "mov.b @\\(0x1234:16,r3.w\\),@er1\\+" \ + "mov.b @(0x1234:16,r3.w),@er1+" +gdb_test "x" "mov.b @\\(0x1234:16,r3.w\\),@-er1" \ + "mov.b @(0x1234:16,r3.w),@-er1" +gdb_test "x" "mov.b @\\(0x1234:16,r3.w\\),@\\+er1" \ + "mov.b @(0x1234:16,r3.w),@+er1" +gdb_test "x" "mov.b @\\(0x1234:16,r3.w\\),@er1-" \ + "mov.b @(0x1234:16,r3.w),@er1-" +gdb_test "x" "mov.b @\\(0x1234:16,r3.w\\),@\\(0x9abc(:16|),er1\\)" \ + "mov.b @(0x1234:16,r3.w),@(0x9abc:16,er1)" +gdb_test "x" "mov.b @\\(0x1234:16,r3.w\\),@\\(0x9abcdef0:32,er1\\)" \ + "mov.b @(0x1234:16,r3.w),@(0x9abcdef0:32,er1)" +gdb_test "x" "mov.b @\\(0x1234:16,r3.w\\),@\\(0x9abc(:16|),r3l.b\\)" \ + "mov.b @(0x1234:16,r3.w),@(0x9abc:16,r3l.b)" +gdb_test "x" "mov.b @\\(0x1234:16,r3.w\\),@\\(0x9abc(:16|),r3.w\\)" \ + "mov.b @(0x1234:16,r3.w),@(0x9abc:16,r3.w)" +gdb_test "x" "mov.b @\\(0x1234:16,r3.w\\),@\\(0x9abc(:16|),er3.l\\)" \ + "mov.b @(0x1234:16,r3.w),@(0x9abc:16,er3.l)" +gdb_test "x" "mov.b @\\(0x1234:16,r3.w\\),@\\(0x9abcdef0:32,r3l.b\\)" \ + "mov.b @(0x1234:16,r3.w),@(0x9abcdef0:32,r3l.b)" +gdb_test "x" "mov.b @\\(0x1234:16,r3.w\\),@\\(0x9abcdef0:32,r3.w\\)" \ + "mov.b @(0x1234:16,r3.w),@(0x9abcdef0:32,r3.w)" +gdb_test "x" "mov.b @\\(0x1234:16,r3.w\\),@\\(0x9abcdef0:32,er3.l\\)" \ + "mov.b @(0x1234:16,r3.w),@(0x9abcdef0:32,er3.l)" +gdb_test "x" "mov.b @\\(0x1234:16,r3.w\\),@0x9abc(:16|)" \ + "mov.b @(0x1234:16,r3.w),@0x9abc:16" +gdb_test "x" "mov.b @\\(0x1234:16,r3.w\\),@0x9abcdef0:32" \ + "mov.b @(0x1234:16,r3.w),@0x9abcdef0:32" +gdb_test "x" "mov.b @\\(0x1234:16,er3.l\\),@er1" \ + "mov.b @(0x1234:16,er3.l),@er1" +gdb_test "x" "mov.b @\\(0x1234:16,er3.l\\),@\\(0x1:2,er1\\)" \ + "mov.b @(0x1234:16,er3.l),@(0x1:2,er1)" +gdb_test "x" "mov.b @\\(0x1234:16,er3.l\\),@er1\\+" \ + "mov.b @(0x1234:16,er3.l),@er1+" +gdb_test "x" "mov.b @\\(0x1234:16,er3.l\\),@-er1" \ + "mov.b @(0x1234:16,er3.l),@-er1" +gdb_test "x" "mov.b @\\(0x1234:16,er3.l\\),@\\+er1" \ + "mov.b @(0x1234:16,er3.l),@+er1" +gdb_test "x" "mov.b @\\(0x1234:16,er3.l\\),@er1-" \ + "mov.b @(0x1234:16,er3.l),@er1-" +gdb_test "x" "mov.b @\\(0x1234:16,er3.l\\),@\\(0x9abc(:16|),er1\\)" \ + "mov.b @(0x1234:16,er3.l),@(0x9abc:16,er1)" +gdb_test "x" "mov.b @\\(0x1234:16,er3.l\\),@\\(0x9abcdef0:32,er1\\)" \ + "mov.b @(0x1234:16,er3.l),@(0x9abcdef0:32,er1)" +gdb_test "x" "mov.b @\\(0x1234:16,er3.l\\),@\\(0x9abc(:16|),r3l.b\\)" \ + "mov.b @(0x1234:16,er3.l),@(0x9abc:16,r3l.b)" +gdb_test "x" "mov.b @\\(0x1234:16,er3.l\\),@\\(0x9abc(:16|),r3.w\\)" \ + "mov.b @(0x1234:16,er3.l),@(0x9abc:16,r3.w)" +gdb_test "x" "mov.b @\\(0x1234:16,er3.l\\),@\\(0x9abc(:16|),er3.l\\)" \ + "mov.b @(0x1234:16,er3.l),@(0x9abc:16,er3.l)" +gdb_test "x" "mov.b @\\(0x1234:16,er3.l\\),@\\(0x9abcdef0:32,r3l.b\\)" \ + "mov.b @(0x1234:16,er3.l),@(0x9abcdef0:32,r3l.b)" +gdb_test "x" "mov.b @\\(0x1234:16,er3.l\\),@\\(0x9abcdef0:32,r3.w\\)" \ + "mov.b @(0x1234:16,er3.l),@(0x9abcdef0:32,r3.w)" +gdb_test "x" "mov.b @\\(0x1234:16,er3.l\\),@\\(0x9abcdef0:32,er3.l\\)" \ + "mov.b @(0x1234:16,er3.l),@(0x9abcdef0:32,er3.l)" +gdb_test "x" "mov.b @\\(0x1234:16,er3.l\\),@0x9abc(:16|)" \ + "mov.b @(0x1234:16,er3.l),@0x9abc:16" +gdb_test "x" "mov.b @\\(0x1234:16,er3.l\\),@0x9abcdef0:32" \ + "mov.b @(0x1234:16,er3.l),@0x9abcdef0:32" +gdb_test "x" "mov.b @\\(0x12345678:32,r3l.b\\),@er1" \ + "mov.b @(0x12345678:32,r3l.b),@er1" +gdb_test "x" "mov.b @\\(0x12345678:32,r3l.b\\),@\\(0x1:2,er1\\)" \ + "mov.b @(0x12345678:32,r3l.b),@(0x1:2,er1)" +gdb_test "x" "mov.b @\\(0x12345678:32,r3l.b\\),@er1\\+" \ + "mov.b @(0x12345678:32,r3l.b),@er1+" +gdb_test "x" "mov.b @\\(0x12345678:32,r3l.b\\),@-er1" \ + "mov.b @(0x12345678:32,r3l.b),@-er1" +gdb_test "x" "mov.b @\\(0x12345678:32,r3l.b\\),@\\+er1" \ + "mov.b @(0x12345678:32,r3l.b),@+er1" +gdb_test "x" "mov.b @\\(0x12345678:32,r3l.b\\),@er1-" \ + "mov.b @(0x12345678:32,r3l.b),@er1-" +gdb_test "x" "mov.b @\\(0x12345678:32,r3l.b\\),@\\(0x9abc(:16|),er1\\)" \ + "mov.b @(0x12345678:32,r3l.b),@(0x9abc:16,er1)" +gdb_test "x" "mov.b @\\(0x12345678:32,r3l.b\\),@\\(0x9abcdef0:32,er1\\)" \ + "mov.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1)" +gdb_test "x" "mov.b @\\(0x12345678:32,r3l.b\\),@\\(0x9abc(:16|),r3l.b\\)" \ + "mov.b @(0x12345678:32,r3l.b),@(0x9abc:16,r3l.b)" +gdb_test "x" "mov.b @\\(0x12345678:32,r3l.b\\),@\\(0x9abc(:16|),r3.w\\)" \ + "mov.b @(0x12345678:32,r3l.b),@(0x9abc:16,r3.w)" +gdb_test "x" "mov.b @\\(0x12345678:32,r3l.b\\),@\\(0x9abc(:16|),er3.l\\)" \ + "mov.b @(0x12345678:32,r3l.b),@(0x9abc:16,er3.l)" +gdb_test "x" "mov.b\t@\\(0x12345678:32,r3l.b\\),@\\(0x9abcdef0:32,r3l.b\\)" \ + "mov.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r3l.b)" +gdb_test "x" "mov.b @\\(0x12345678:32,r3l.b\\),@\\(0x9abcdef0:32,r3.w\\)" \ + "mov.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r3.w)" +gdb_test "x" "mov.b\t@\\(0x12345678:32,r3l.b\\),@\\(0x9abcdef0:32,er3.l\\)" \ + "mov.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er3.l)" +gdb_test "x" "mov.b @\\(0x12345678:32,r3l.b\\),@0x9abc(:16|)" \ + "mov.b @(0x12345678:32,r3l.b),@0x9abc:16" +gdb_test "x" "mov.b @\\(0x12345678:32,r3l.b\\),@0x9abcdef0:32" \ + "mov.b @(0x12345678:32,r3l.b),@0x9abcdef0:32" +gdb_test "x" "mov.b @\\(0x12345678:32,r3.w\\),@er1" \ + "mov.b @(0x12345678:32,r3.w),@er1" +gdb_test "x" "mov.b @\\(0x12345678:32,r3.w\\),@\\(0x1:2,er1\\)" \ + "mov.b @(0x12345678:32,r3.w),@(0x1:2,er1)" +gdb_test "x" "mov.b @\\(0x12345678:32,r3.w\\),@er1\\+" \ + "mov.b @(0x12345678:32,r3.w),@er1+" +gdb_test "x" "mov.b @\\(0x12345678:32,r3.w\\),@-er1" \ + "mov.b @(0x12345678:32,r3.w),@-er1" +gdb_test "x" "mov.b @\\(0x12345678:32,r3.w\\),@\\+er1" \ + "mov.b @(0x12345678:32,r3.w),@+er1" +gdb_test "x" "mov.b @\\(0x12345678:32,r3.w\\),@er1-" \ + "mov.b @(0x12345678:32,r3.w),@er1-" +gdb_test "x" "mov.b @\\(0x12345678:32,r3.w\\),@\\(0x9abc(:16|),er1\\)" \ + "mov.b @(0x12345678:32,r3.w),@(0x9abc:16,er1)" +gdb_test "x" "mov.b @\\(0x12345678:32,r3.w\\),@\\(0x9abcdef0:32,er1\\)" \ + "mov.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1)" +gdb_test "x" "mov.b @\\(0x12345678:32,r3.w\\),@\\(0x9abc(:16|),r3l.b\\)" \ + "mov.b @(0x12345678:32,r3.w),@(0x9abc:16,r3l.b)" +gdb_test "x" "mov.b @\\(0x12345678:32,r3.w\\),@\\(0x9abc(:16|),r3.w\\)" \ + "mov.b @(0x12345678:32,r3.w),@(0x9abc:16,r3.w)" +gdb_test "x" "mov.b @\\(0x12345678:32,r3.w\\),@\\(0x9abc(:16|),er3.l\\)" \ + "mov.b @(0x12345678:32,r3.w),@(0x9abc:16,er3.l)" +gdb_test "x" "mov.b @\\(0x12345678:32,r3.w\\),@\\(0x9abcdef0:32,r3l.b\\)" \ + "mov.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,r3l.b)" +gdb_test "x" "mov.b @\\(0x12345678:32,r3.w\\),@\\(0x9abcdef0:32,r3.w\\)" \ + "mov.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,r3.w)" +gdb_test "x" "mov.b @\\(0x12345678:32,r3.w\\),@\\(0x9abcdef0:32,er3.l\\)" \ + "mov.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,er3.l)" +gdb_test "x" "mov.b @\\(0x12345678:32,r3.w\\),@0x9abc(:16|)" \ + "mov.b @(0x12345678:32,r3.w),@0x9abc:16" +gdb_test "x" "mov.b @\\(0x12345678:32,r3.w\\),@0x9abcdef0:32" \ + "mov.b @(0x12345678:32,r3.w),@0x9abcdef0:32" +gdb_test "x" "mov.b @\\(0x12345678:32,er3.l\\),@er1" \ + "mov.b @(0x12345678:32,er3.l),@er1" +gdb_test "x" "mov.b @\\(0x12345678:32,er3.l\\),@\\(0x1:2,er1\\)" \ + "mov.b @(0x12345678:32,er3.l),@(0x1:2,er1)" +gdb_test "x" "mov.b @\\(0x12345678:32,er3.l\\),@er1\\+" \ + "mov.b @(0x12345678:32,er3.l),@er1+" +gdb_test "x" "mov.b @\\(0x12345678:32,er3.l\\),@-er1" \ + "mov.b @(0x12345678:32,er3.l),@-er1" +gdb_test "x" "mov.b @\\(0x12345678:32,er3.l\\),@\\+er1" \ + "mov.b @(0x12345678:32,er3.l),@+er1" +gdb_test "x" "mov.b @\\(0x12345678:32,er3.l\\),@er1-" \ + "mov.b @(0x12345678:32,er3.l),@er1-" +gdb_test "x" "mov.b @\\(0x12345678:32,er3.l\\),@\\(0x9abc(:16|),er1\\)" \ + "mov.b @(0x12345678:32,er3.l),@(0x9abc:16,er1)" +gdb_test "x" "mov.b @\\(0x12345678:32,er3.l\\),@\\(0x9abcdef0:32,er1\\)" \ + "mov.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1)" +gdb_test "x" "mov.b @\\(0x12345678:32,er3.l\\),@\\(0x9abc(:16|),r3l.b\\)" \ + "mov.b @(0x12345678:32,er3.l),@(0x9abc:16,r3l.b)" +gdb_test "x" "mov.b @\\(0x12345678:32,er3.l\\),@\\(0x9abc(:16|),r3.w\\)" \ + "mov.b @(0x12345678:32,er3.l),@(0x9abc:16,r3.w)" +gdb_test "x" "mov.b @\\(0x12345678:32,er3.l\\),@\\(0x9abc(:16|),er3.l\\)" \ + "mov.b @(0x12345678:32,er3.l),@(0x9abc:16,er3.l)" +gdb_test "x" "mov.b @\\(0x12345678:32,er3.l\\),@\\(0x9abcdef0:32,r3l.b\\)" \ + "mov.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,r3l.b)" +gdb_test "x" "mov.b @\\(0x12345678:32,er3.l\\),@\\(0x9abcdef0:32,r3.w\\)" \ + "mov.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,r3.w)" +gdb_test "x" "mov.b @\\(0x12345678:32,er3.l\\),@\\(0x9abcdef0:32,er3.l\\)" \ + "mov.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,er3.l)" +gdb_test "x" "mov.b @\\(0x12345678:32,er3.l\\),@0x9abc(:16|)" \ + "mov.b @(0x12345678:32,er3.l),@0x9abc:16" +gdb_test "x" "mov.b @\\(0x12345678:32,er3.l\\),@0x9abcdef0:32" \ + "mov.b @(0x12345678:32,er3.l),@0x9abcdef0:32" +gdb_test "x" "mov.b @0x1234:16,@er1" \ + "mov.b @0x1234:16,@er1" +gdb_test "x" "mov.b @0x1234:16,@\\(0x1:2,er1\\)" \ + "mov.b @0x1234:16,@(0x1:2,er1)" +gdb_test "x" "mov.b @0x1234:16,@er1\\+" \ + "mov.b @0x1234:16,@er1+" +gdb_test "x" "mov.b @0x1234:16,@-er1" \ + "mov.b @0x1234:16,@-er1" +gdb_test "x" "mov.b @0x1234:16,@\\+er1" \ + "mov.b @0x1234:16,@+er1" +gdb_test "x" "mov.b @0x1234:16,@er1-" \ + "mov.b @0x1234:16,@er1-" +gdb_test "x" "mov.b @0x1234:16,@\\(0x9abc(:16|),er1\\)" \ + "mov.b @0x1234:16,@(0x9abc:16,er1)" +gdb_test "x" "mov.b @0x1234:16,@\\(0x9abcdef0:32,er1\\)" \ + "mov.b @0x1234:16,@(0x9abcdef0:32,er1)" +gdb_test "x" "mov.b @0x1234:16,@\\(0x9abc(:16|),r3l.b\\)" \ + "mov.b @0x1234:16,@(0x9abc:16,r3l.b)" +gdb_test "x" "mov.b @0x1234:16,@\\(0x9abc(:16|),r3.w\\)" \ + "mov.b @0x1234:16,@(0x9abc:16,r3.w)" +gdb_test "x" "mov.b @0x1234:16,@\\(0x9abc(:16|),er3.l\\)" \ + "mov.b @0x1234:16,@(0x9abc:16,er3.l)" +gdb_test "x" "mov.b @0x1234:16,@\\(0x9abcdef0:32,r3l.b\\)" \ + "mov.b @0x1234:16,@(0x9abcdef0:32,r3l.b)" +gdb_test "x" "mov.b @0x1234:16,@\\(0x9abcdef0:32,r3.w\\)" \ + "mov.b @0x1234:16,@(0x9abcdef0:32,r3.w)" +gdb_test "x" "mov.b @0x1234:16,@\\(0x9abcdef0:32,er3.l\\)" \ + "mov.b @0x1234:16,@(0x9abcdef0:32,er3.l)" +gdb_test "x" "mov.b @0x1234:16,@0x9abc(:16|)" \ + "mov.b @0x1234:16,@0x9abc:16" +gdb_test "x" "mov.b @0x1234:16,@0x9abcdef0:32" \ + "mov.b @0x1234:16,@0x9abcdef0:32" +gdb_test "x" "mov.b @0x12345678:32,@er1" \ + "mov.b @0x12345678:32,@er1" +gdb_test "x" "mov.b @0x12345678:32,@\\(0x1:2,er1\\)" \ + "mov.b @0x12345678:32,@(0x1:2,er1)" +gdb_test "x" "mov.b @0x12345678:32,@er1\\+" \ + "mov.b @0x12345678:32,@er1+" +gdb_test "x" "mov.b @0x12345678:32,@-er1" \ + "mov.b @0x12345678:32,@-er1" +gdb_test "x" "mov.b @0x12345678:32,@\\+er1" \ + "mov.b @0x12345678:32,@+er1" +gdb_test "x" "mov.b @0x12345678:32,@er1-" \ + "mov.b @0x12345678:32,@er1-" +gdb_test "x" "mov.b @0x12345678:32,@\\(0x9abc(:16|),er1\\)" \ + "mov.b @0x12345678:32,@(0x9abc:16,er1)" +gdb_test "x" "mov.b @0x12345678:32,@\\(0x9abcdef0:32,er1\\)" \ + "mov.b @0x12345678:32,@(0x9abcdef0:32,er1)" +gdb_test "x" "mov.b @0x12345678:32,@\\(0x9abc(:16|),r3l.b\\)" \ + "mov.b @0x12345678:32,@(0x9abc:16,r3l.b)" +gdb_test "x" "mov.b @0x12345678:32,@\\(0x9abc(:16|),r3.w\\)" \ + "mov.b @0x12345678:32,@(0x9abc:16,r3.w)" +gdb_test "x" "mov.b @0x12345678:32,@\\(0x9abc(:16|),er3.l\\)" \ + "mov.b @0x12345678:32,@(0x9abc:16,er3.l)" +gdb_test "x" "mov.b @0x12345678:32,@\\(0x9abcdef0:32,r3l.b\\)" \ + "mov.b @0x12345678:32,@(0x9abcdef0:32,r3l.b)" +gdb_test "x" "mov.b @0x12345678:32,@\\(0x9abcdef0:32,r3.w\\)" \ + "mov.b @0x12345678:32,@(0x9abcdef0:32,r3.w)" +gdb_test "x" "mov.b @0x12345678:32,@\\(0x9abcdef0:32,er3.l\\)" \ + "mov.b @0x12345678:32,@(0x9abcdef0:32,er3.l)" +gdb_test "x" "mov.b @0x12345678:32,@0x9abc(:16|)" \ + "mov.b @0x12345678:32,@0x9abc:16" +gdb_test "x" "mov.b @0x12345678:32,@0x9abcdef0:32" \ + "mov.b @0x12345678:32,@0x9abcdef0:32" +gdb_test "x" "mov.w #0x1234(:16|),r1" \ + "mov.w #0x1234:16,r1" +gdb_test "x" "mov.w #0x1(:3|),r3" \ + "mov.w #0x1:3,r3" +gdb_test "x" "mov.w #0x1234(:16|),@er1" \ + "mov.w #0x1234:16,@er1" +gdb_test "x" "mov.w #0x1234(:16|),@\\(0x2:2,er1\\)" \ + "mov.w #0x1234:16,@(0x2:2,er1)" +gdb_test "x" "mov.w #0x1234(:16|),@er1\\+" \ + "mov.w #0x1234:16@er1+" +gdb_test "x" "mov.w #0x1234(:16|),@-er1" \ + "mov.w #0x1234:16,@-er1" +gdb_test "x" "mov.w #0x1234(:16|),@\\+er1" \ + "mov.w #0x1234:16,@+er1" +gdb_test "x" "mov.w #0x1234(:16|),@er1-" \ + "mov.w #0x1234:16,@er1-" +gdb_test "x" "mov.w #0x1234(:16|),@\\(0x1234:16,er1\\)" \ + "mov.w #0x1234:16,@(0x1234:16,er1)" +gdb_test "x" "mov.w #0x1234(:16|),@\\(0x12345678:32,er1\\)" \ + "mov.w #0x1234:16,@(0x12345678:32,er1)" +gdb_test "x" "mov.w #0x1234(:16|),@\\(0x1234:16,r3l.b\\)" \ + "mov.w #0x1234:16,@(0x1234:16,r3l.b)" +gdb_test "x" "mov.w #0x1234(:16|),@\\(0x1234:16,r3.w\\)" \ + "mov.w #0x1234:16,@(0x1234:16,r3.w)" +gdb_test "x" "mov.w #0x1234(:16|),@\\(0x1234:16,er3.l\\)" \ + "mov.w #0x1234:16,@(0x1234:16,er3.l)" +gdb_test "x" "mov.w #0x1234(:16|),@\\(0x12345678:32,r3l.b\\)" \ + "mov.w #0x1234:16,@(0x12345678:32,r3l.b)" +gdb_test "x" "mov.w #0x1234(:16|),@\\(0x12345678:32,r3.w\\)" \ + "mov.w #0x1234:16,@(0x12345678:32,r3.w)" +gdb_test "x" "mov.w #0x1234(:16|),@\\(0x12345678:32,er3.l\\)" \ + "mov.w #0x1234:16,@(0x12345678:32,er3.l)" +gdb_test "x" "mov.w #0x1234(:16|),@0x1234:16" \ + "mov.w #0x1234:16,@0x1234:16" +gdb_test "x" "mov.w #0x1234(:16|),@0x12345678:32" \ + "mov.w #0x1234:16,@0x12345678:32" +gdb_test "x" "mov.w #0x12(:8|),@er1" \ + "mov.w #0x12:8,@er1" +gdb_test "x" "mov.w #0x12(:8|),@\\(0x2:2,er1\\)" \ + "mov.w #0x12:8,@(0x2:2,er1)" +gdb_test "x" "mov.w #0x12(:8|),@er1\\+" \ + "mov.w #0x12:8,@er1+" +gdb_test "x" "mov.w #0x12(:8|),@-er1" \ + "mov.w #0x12:8,@-er1" +gdb_test "x" "mov.w #0x12(:8|),@\\+er1" \ + "mov.w #0x12:8,@+er1" +gdb_test "x" "mov.w #0x12(:8|),@er1-" \ + "mov.w #0x12:8,@er1-" +gdb_test "x" "mov.w #0x12(:8|),@\\(0x1234:16,er1\\)" \ + "mov.w #0x12:8,@(0x1234:16,er1)" +gdb_test "x" "mov.w #0x12(:8|),@\\(0x12345678:32,er1\\)" \ + "mov.w #0x12:8,@(0x12345678:32,er1)" +gdb_test "x" "mov.w #0x12(:8|),@\\(0x1234:16,r3l.b\\)" \ + "mov.w #0x12:8,@(0x1234:16,r3l.b)" +gdb_test "x" "mov.w #0x12(:8|),@\\(0x1234:16,r3.w\\)" \ + "mov.w #0x12:8,@(0x1234:16,r3.w)" +gdb_test "x" "mov.w #0x12(:8|),@\\(0x1234:16,er3.l\\)" \ + "mov.w #0x12:8,@(0x1234:16,er3.l)" +gdb_test "x" "mov.w #0x12(:8|),@\\(0x12345678:32,r3l.b\\)" \ + "mov.w #0x12:8,@(0x12345678:32,r3l.b)" +gdb_test "x" "mov.w #0x12(:8|),@\\(0x12345678:32,r3.w\\)" \ + "mov.w #0x12:8,@(0x12345678:32,r3.w)" +gdb_test "x" "mov.w #0x12(:8|),@\\(0x12345678:32,er3.l\\)" \ + "mov.w #0x12:8,@(0x12345678:32,er3.l)" +gdb_test "x" "mov.w #0x12(:8|),@0x1234:16" \ + "mov.w #0x12:8,@0x1234:16" +gdb_test "x" "mov.w #0x12(:8|),@0x12345678:32" \ + "mov.w #0x12:8,@0x12345678:32" +gdb_test "x" "mov.w #0x1(:4|),@0x1234:16" \ + "mov.w #0x1:4,@0x1234:16" +gdb_test "x" "mov.w #0x1(:4|),@0x12345678:32" \ + "mov.w #0x1:4,@0x12345678:32" +gdb_test "x" "mov.w r2,r1" \ + "mov.w r2,r1" +gdb_test "x" "mov.w r2,@er1" \ + "mov.w r2,@er1" +gdb_test "x" "mov.w r2,@\\(0x2:2,er1\\)" \ + "mov.w r2,@(0x2:2,er1)" +gdb_test "x" "mov.w r2,@er1\\+" \ + "mov.w r2,@er1+" +gdb_test "x" "mov.w r2,@-er1" \ + "mov.w r2,@-er1" +gdb_test "x" "mov.w r2,@\\+er1" \ + "mov.w r2,@+er1" +gdb_test "x" "mov.w r2,@er1-" \ + "mov.w r2,@er1-" +gdb_test "x" "mov.w r2,@\\(0x1234:16,er1\\)" \ + "mov.w r2,@(0x1234:16,er1)" +gdb_test "x" "mov.w r2,@\\(0x12345678:32,er1\\)" \ + "mov.w r2,@(0x12345678:32,er1)" +gdb_test "x" "mov.w r2,@\\(0x1234:16,r3l.b\\)" \ + "mov.w r2,@(0x1234:16,r3l.b)" +gdb_test "x" "mov.w r2,@\\(0x1234:16,r3.w\\)" \ + "mov.w r2,@(0x1234:16,r3.w)" +gdb_test "x" "mov.w r2,@\\(0x1234:16,er3.l\\)" \ + "mov.w r2,@(0x1234:16,er3.l)" +gdb_test "x" "mov.w r2,@\\(0x12345678:32,r3l.b\\)" \ + "mov.w r2,@(0x12345678:32,r3l.b)" +gdb_test "x" "mov.w r2,@\\(0x12345678:32,r3.w\\)" \ + "mov.w r2,@(0x12345678:32,r3.w)" +gdb_test "x" "mov.w r2,@\\(0x12345678:32,er3.l\\)" \ + "mov.w r2,@(0x12345678:32,er3.l)" +gdb_test "x" "mov.w r2,@0x1234:16" \ + "mov.w r2,@0x1234:16" +gdb_test "x" "mov.w r2,@0x12345678:32" \ + "mov.w r2,@0x12345678:32" +gdb_test "x" "mov.w @er2,r1" \ + "mov.w @er2,r1" +gdb_test "x" "mov.w @\\(0x2:2,er2\\),r1" \ + "mov.w @(0x2:2,er2),r1" +gdb_test "x" "mov.w @er2\\+,r1" \ + "mov.w @er2+,r1" +gdb_test "x" "mov.w @-er2,r1" \ + "mov.w @-er2,r1" +gdb_test "x" "mov.w @\\+er2,r1" \ + "mov.w @+er2,r1" +gdb_test "x" "mov.w @er2-,r1" \ + "mov.w @er2-,r1" +gdb_test "x" "mov.w @\\(0x1234:16,er1\\),r1" \ + "mov.w @(0x1234:16,er1),r1" +gdb_test "x" "mov.w @\\(0x12345678:32,er1\\),r1" \ + "mov.w @(0x12345678:32,er1),r1" +gdb_test "x" "mov.w @\\(0x1234:16,r3l.b\\),r1" \ + "mov.w @(0x1234:16,r3l.b),r1" +gdb_test "x" "mov.w @\\(0x1234:16,r3.w\\),r1" \ + "mov.w @(0x1234:16,r3.w),r1" +gdb_test "x" "mov.w @\\(0x1234:16,er3.l\\),r1" \ + "mov.w @(0x1234:16,er3.l),r1" +gdb_test "x" "mov.w @\\(0x12345678:32,r3l.b\\),r1" \ + "mov.w @(0x12345678:32,r3l.b),r1" +gdb_test "x" "mov.w @\\(0x12345678:32,r3.w\\),r1" \ + "mov.w @(0x12345678:32,r3.w),r1" +gdb_test "x" "mov.w @\\(0x12345678:32,er3.l\\),r1" \ + "mov.w @(0x12345678:32,er3.l),r1" +gdb_test "x" "mov.w @0x1234:16,r1" \ + "mov.w @0x1234:16,r1" +gdb_test "x" "mov.w @0x12345678:32,r1" \ + "mov.w @0x12345678:32,r1" +gdb_test "x" "mov.w @er2,@er1" \ + "mov.w @er2,@er1" +gdb_test "x" "mov.w @er2,@\\(0x2:2,er1\\)" \ + "mov.w @er2,@(0x2:2,er1)" +gdb_test "x" "mov.w @er2,@er1\\+" \ + "mov.w @er2,@er1+" +gdb_test "x" "mov.w @er2,@-er1" \ + "mov.w @er2,@-er1" +gdb_test "x" "mov.w @er2,@\\+er1" \ + "mov.w @er2,@+er1" +gdb_test "x" "mov.w @er2,@er1-" \ + "mov.w @er2,@er1-" +gdb_test "x" "mov.w @er2,@\\(0x1234:16,er1\\)" \ + "mov.w @er2,@(0x1234:16,er1)" +gdb_test "x" "mov.w @er2,@\\(0x12345678:32,er1\\)" \ + "mov.w @er2,@(0x12345678:32,er1)" +gdb_test "x" "mov.w @er2,@\\(0x1234:16,r3l.b\\)" \ + "mov.w @er2,@(0x1234:16,r3l.b)" +gdb_test "x" "mov.w @er2,@\\(0x1234:16,r3.w\\)" \ + "mov.w @er2,@(0x1234:16,r3.w)" +gdb_test "x" "mov.w @er2,@\\(0x1234:16,er3.l\\)" \ + "mov.w @er2,@(0x1234:16,er3.l)" +gdb_test "x" "mov.w @er2,@\\(0x12345678:32,r3l.b\\)" \ + "mov.w @er2,@(0x12345678:32,r3l.b)" +gdb_test "x" "mov.w @er2,@\\(0x12345678:32,r3.w\\)" \ + "mov.w @er2,@(0x12345678:32,r3.w)" +gdb_test "x" "mov.w @er2,@\\(0x12345678:32,er3.l\\)" \ + "mov.w @er2,@(0x12345678:32,er3.l)" +gdb_test "x" "mov.w @er2,@0x1234:16" \ + "mov.w @er2,@0x1234:16" +gdb_test "x" "mov.w @er2,@0x12345678:32" \ + "mov.w @er2,@0x12345678:32" +gdb_test "x" "mov.w @\\(0x2:2,er2\\),@er1" \ + "mov.w @(0x2:2,er2),@er1" +gdb_test "x" "mov.w @\\(0x2:2,er2\\),@\\(0x2:2,er1\\)" \ + "mov.w @(0x2:2,er2),@(0x2:2,er1)" +gdb_test "x" "mov.w @\\(0x2:2,er2\\),@er1\\+" \ + "mov.w @(0x2:2,er2),@er1+" +gdb_test "x" "mov.w @\\(0x2:2,er2\\),@-er1" \ + "mov.w @(0x2:2,er2),@-er1" +gdb_test "x" "mov.w @\\(0x2:2,er2\\),@\\+er1" \ + "mov.w @(0x2:2,er2),@+er1" +gdb_test "x" "mov.w @\\(0x2:2,er2\\),@er1-" \ + "mov.w @(0x2:2,er2),@er1-" +gdb_test "x" "mov.w @\\(0x2:2,er2\\),@\\(0x1234:16,er1\\)" \ + "mov.w @(0x2:2,er2),@(0x1234:16,er1)" +gdb_test "x" "mov.w @\\(0x2:2,er2\\),@\\(0x12345678:32,er1\\)" \ + "mov.w @(0x2:2,er2),@(0x12345678:32,er1)" +gdb_test "x" "mov.w @\\(0x2:2,er2\\),@\\(0x1234:16,r3l.b\\)" \ + "mov.w @(0x2:2,er2),@(0x1234:16,r3l.b)" +gdb_test "x" "mov.w @\\(0x2:2,er2\\),@\\(0x1234:16,r3.w\\)" \ + "mov.w @(0x2:2,er2),@(0x1234:16,r3.w)" +gdb_test "x" "mov.w @\\(0x2:2,er2\\),@\\(0x1234:16,er3.l\\)" \ + "mov.w @(0x2:2,er2),@(0x1234:16,er3.l)" +gdb_test "x" "mov.w @\\(0x2:2,er2\\),@\\(0x12345678:32,r3l.b\\)" \ + "mov.w @(0x2:2,er2),@(0x12345678:32,r3l.b)" +gdb_test "x" "mov.w @\\(0x2:2,er2\\),@\\(0x12345678:32,r3.w\\)" \ + "mov.w @(0x2:2,er2),@(0x12345678:32,r3.w)" +gdb_test "x" "mov.w @\\(0x2:2,er2\\),@\\(0x12345678:32,er3.l\\)" \ + "mov.w @(0x2:2,er2),@(0x12345678:32,er3.l)" +gdb_test "x" "mov.w @\\(0x2:2,er2\\),@0x1234:16" \ + "mov.w @(0x2:2,er2),@0x1234:16" +gdb_test "x" "mov.w @\\(0x2:2,er2\\),@0x12345678:32" \ + "mov.w @(0x2:2,er2),@0x12345678:32" +gdb_test "x" "mov.w @-er2,@er1" \ + "mov.w @-er2,@er1" +gdb_test "x" "mov.w @-er2,@\\(0x2:2,er1\\)" \ + "mov.w @-er2,@(0x2:2,er1)" +gdb_test "x" "mov.w @-er2,@er1\\+" \ + "mov.w @-er2,@er1+" +gdb_test "x" "mov.w @-er2,@-er1" \ + "mov.w @-er2,@-er1" +gdb_test "x" "mov.w @-er2,@\\+er1" \ + "mov.w @-er2,@+er1" +gdb_test "x" "mov.w @-er2,@er1-" \ + "mov.w @-er2,@er1-" +gdb_test "x" "mov.w @-er2,@\\(0x1234:16,er1\\)" \ + "mov.w @-er2,@(0x1234:16,er1)" +gdb_test "x" "mov.w @-er2,@\\(0x12345678:32,er1\\)" \ + "mov.w @-er2,@(0x12345678:32,er1)" +gdb_test "x" "mov.w @-er2,@\\(0x1234:16,r3l.b\\)" \ + "mov.w @-er2,@(0x1234:16,r3l.b)" +gdb_test "x" "mov.w @-er2,@\\(0x1234:16,r3.w\\)" \ + "mov.w @-er2,@(0x1234:16,r3.w)" +gdb_test "x" "mov.w @-er2,@\\(0x1234:16,er3.l\\)" \ + "mov.w @-er2,@(0x1234:16,er3.l)" +gdb_test "x" "mov.w @-er2,@\\(0x12345678:32,r3l.b\\)" \ + "mov.w @-er2,@(0x12345678:32,r3l.b)" +gdb_test "x" "mov.w @-er2,@\\(0x12345678:32,r3.w\\)" \ + "mov.w @-er2,@(0x12345678:32,r3.w)" +gdb_test "x" "mov.w @-er2,@\\(0x12345678:32,er3.l\\)" \ + "mov.w @-er2,@(0x12345678:32,er3.l)" +gdb_test "x" "mov.w @-er2,@0x1234:16" \ + "mov.w @-er2,@0x1234:16" +gdb_test "x" "mov.w @-er2,@0x12345678:32" \ + "mov.w @-er2,@0x12345678:32" +gdb_test "x" "mov.w @er2\\+,@er1" \ + "mov.w @er2+,@er1" +gdb_test "x" "mov.w @er2\\+,@\\(0x2:2,er1\\)" \ + "mov.w @er2+,@(0x2:2,er1)" +gdb_test "x" "mov.w @er2\\+,@er1\\+" \ + "mov.w @er2+,@er1+" +gdb_test "x" "mov.w @er2\\+,@-er1" \ + "mov.w @er2+,@-er1" +gdb_test "x" "mov.w @er2\\+,@\\+er1" \ + "mov.w @er2+,@+er1" +gdb_test "x" "mov.w @er2\\+,@er1-" \ + "mov.w @er2+,@er1-" +gdb_test "x" "mov.w @er2\\+,@\\(0x1234:16,er1\\)" \ + "mov.w @er2+,@(0x1234:16,er1)" +gdb_test "x" "mov.w @er2\\+,@\\(0x12345678:32,er1\\)" \ + "mov.w @er2+,@(0x12345678:32,er1)" +gdb_test "x" "mov.w @er2\\+,@\\(0x1234:16,r3l.b\\)" \ + "mov.w @er2+,@(0x1234:16,r3l.b)" +gdb_test "x" "mov.w @er2\\+,@\\(0x1234:16,r3.w\\)" \ + "mov.w @er2+,@(0x1234:16,r3.w)" +gdb_test "x" "mov.w @er2\\+,@\\(0x1234:16,er3.l\\)" \ + "mov.w @er2+,@(0x1234:16,er3.l)" +gdb_test "x" "mov.w @er2\\+,@\\(0x12345678:32,r3l.b\\)" \ + "mov.w @er2+,@(0x12345678:32,r3l.b)" +gdb_test "x" "mov.w @er2\\+,@\\(0x12345678:32,r3.w\\)" \ + "mov.w @er2+,@(0x12345678:32,r3.w)" +gdb_test "x" "mov.w @er2\\+,@\\(0x12345678:32,er3.l\\)" \ + "mov.w @er2+,@(0x12345678:32,er3.l)" +gdb_test "x" "mov.w @er2\\+,@0x1234:16" \ + "mov.w @er2+,@0x1234:16" +gdb_test "x" "mov.w @er2\\+,@0x12345678:32" \ + "mov.w @er2+,@0x12345678:32" +gdb_test "x" "mov.w @er2-,@er1" \ + "mov.w @er2-,@er1" +gdb_test "x" "mov.w @er2-,@\\(0x2:2,er1\\)" \ + "mov.w @er2-,@(0x2:2,er1)" +gdb_test "x" "mov.w @er2-,@er1\\+" \ + "mov.w @er2-,@er1+" +gdb_test "x" "mov.w @er2-,@-er1" \ + "mov.w @er2-,@-er1" +gdb_test "x" "mov.w @er2-,@\\+er1" \ + "mov.w @er2-,@+er1" +gdb_test "x" "mov.w @er2-,@er1-" \ + "mov.w @er2-,@er1-" +gdb_test "x" "mov.w @er2-,@\\(0x1234:16,er1\\)" \ + "mov.w @er2-,@(0x1234:16,er1)" +gdb_test "x" "mov.w @er2-,@\\(0x12345678:32,er1\\)" \ + "mov.w @er2-,@(0x12345678:32,er1)" +gdb_test "x" "mov.w @er2-,@\\(0x1234:16,r3l.b\\)" \ + "mov.w @er2-,@(0x1234:16,r3l.b)" +gdb_test "x" "mov.w @er2-,@\\(0x1234:16,r3.w\\)" \ + "mov.w @er2-,@(0x1234:16,r3.w)" +gdb_test "x" "mov.w @er2-,@\\(0x1234:16,er3.l\\)" \ + "mov.w @er2-,@(0x1234:16,er3.l)" +gdb_test "x" "mov.w @er2-,@\\(0x12345678:32,r3l.b\\)" \ + "mov.w @er2-,@(0x12345678:32,r3l.b)" +gdb_test "x" "mov.w @er2-,@\\(0x12345678:32,r3.w\\)" \ + "mov.w @er2-,@(0x12345678:32,r3.w)" +gdb_test "x" "mov.w @er2-,@\\(0x12345678:32,er3.l\\)" \ + "mov.w @er2-,@(0x12345678:32,er3.l)" +gdb_test "x" "mov.w @er2-,@0x1234:16" \ + "mov.w @er2-,@0x1234:16" +gdb_test "x" "mov.w @er2-,@0x12345678:32" \ + "mov.w @er2-,@0x12345678:32" +gdb_test "x" "mov.w @\\+er2,@er1" \ + "mov.w @+er2,@er1" +gdb_test "x" "mov.w @\\+er2,@\\(0x2:2,er1\\)" \ + "mov.w @+er2,@(0x2:2,er1)" +gdb_test "x" "mov.w @\\+er2,@er1\\+" \ + "mov.w @+er2,@er1+" +gdb_test "x" "mov.w @\\+er2,@-er1" \ + "mov.w @+er2,@-er1" +gdb_test "x" "mov.w @\\+er2,@\\+er1" \ + "mov.w @+er2,@+er1" +gdb_test "x" "mov.w @\\+er2,@er1-" \ + "mov.w @+er2,@er1-" +gdb_test "x" "mov.w @\\+er2,@\\(0x1234:16,er1\\)" \ + "mov.w @+er2,@(0x1234:16,er1)" +gdb_test "x" "mov.w @\\+er2,@\\(0x12345678:32,er1\\)" \ + "mov.w @+er2,@(0x12345678:32,er1)" +gdb_test "x" "mov.w @\\+er2,@\\(0x1234:16,r3l.b\\)" \ + "mov.w @+er2,@(0x1234:16,r3l.b)" +gdb_test "x" "mov.w @\\+er2,@\\(0x1234:16,r3.w\\)" \ + "mov.w @+er2,@(0x1234:16,r3.w)" +gdb_test "x" "mov.w @\\+er2,@\\(0x1234:16,er3.l\\)" \ + "mov.w @+er2,@(0x1234:16,er3.l)" +gdb_test "x" "mov.w @\\+er2,@\\(0x12345678:32,r3l.b\\)" \ + "mov.w @+er2,@(0x12345678:32,r3l.b)" +gdb_test "x" "mov.w @\\+er2,@\\(0x12345678:32,r3.w\\)" \ + "mov.w @+er2,@(0x12345678:32,r3.w)" +gdb_test "x" "mov.w @\\+er2,@\\(0x12345678:32,er3.l\\)" \ + "mov.w @+er2,@(0x12345678:32,er3.l)" +gdb_test "x" "mov.w @\\+er2,@0x1234:16" \ + "mov.w @+er2,@0x1234:16" +gdb_test "x" "mov.w @\\+er2,@0x12345678:32" \ + "mov.w @+er2,@0x12345678:32" +gdb_test "x" "mov.w @\\(0x1234:16,er2\\),@er1" \ + "mov.w @(0x1234:16,er2),@er1" +gdb_test "x" "mov.w @\\(0x1234:16,er2\\),@\\(0x2:2,er1\\)" \ + "mov.w @(0x1234:16,er2),@(0x2:2,er1)" +gdb_test "x" "mov.w @\\(0x1234:16,er2\\),@er1\\+" \ + "mov.w @(0x1234:16,er2),@er1+" +gdb_test "x" "mov.w @\\(0x1234:16,er2\\),@-er1" \ + "mov.w @(0x1234:16,er2),@-er1" +gdb_test "x" "mov.w @\\(0x1234:16,er2\\),@\\+er1" \ + "mov.w @(0x1234:16,er2),@+er1" +gdb_test "x" "mov.w @\\(0x1234:16,er2\\),@er1-" \ + "mov.w @(0x1234:16,er2),@er1-" +gdb_test "x" "mov.w @\\(0x1234:16,er2\\),@\\(0x9abc(:16|),er1\\)" \ + "mov.w @(0x1234:16,er2),@(0x9abc:16,er1)" +gdb_test "x" "mov.w @\\(0x1234:16,er2\\),@\\(0x9abcdef0:32,er1\\)" \ + "mov.w @(0x1234:16,er2),@(0x9abcdef0:32,er1)" +gdb_test "x" "mov.w @\\(0x1234:16,er2\\),@\\(0x9abc(:16|),r3l.b\\)" \ + "mov.w @(0x1234:16,er2),@(0x9abc:16,r3l.b)" +gdb_test "x" "mov.w @\\(0x1234:16,er2\\),@\\(0x9abc(:16|),r3.w\\)" \ + "mov.w @(0x1234:16,er2),@(0x9abc:16,r3.w)" +gdb_test "x" "mov.w @\\(0x1234:16,er2\\),@\\(0x9abc(:16|),er3.l\\)" \ + "mov.w @(0x1234:16,er2),@(0x9abc:16,er3.l)" +gdb_test "x" "mov.w @\\(0x1234:16,er2\\),@\\(0x9abcdef0:32,r3l.b\\)" \ + "mov.w @(0x1234:16,er2),@(0x9abcdef0:32,r3l.b)" +gdb_test "x" "mov.w @\\(0x1234:16,er2\\),@\\(0x9abcdef0:32,r3.w\\)" \ + "mov.w @(0x1234:16,er2),@(0x9abcdef0:32,r3.w)" +gdb_test "x" "mov.w @\\(0x1234:16,er2\\),@\\(0x9abcdef0:32,er3.l\\)" \ + "mov.w @(0x1234:16,er2),@(0x9abcdef0:32,er3.l)" +gdb_test "x" "mov.w @\\(0x1234:16,er2\\),@0x9abc(:16|)" \ + "mov.w @(0x1234:16,er2),@0x9abc:16" +gdb_test "x" "mov.w @\\(0x1234:16,er2\\),@0x9abcdef0:32" \ + "mov.w @(0x1234:16,er2),@0x9abcdef0:32" +gdb_test "x" "mov.w @\\(0x12345678:32,er2\\),@er1" \ + "mov.w @(0x12345678:32,er2),@er1" +gdb_test "x" "mov.w @\\(0x12345678:32,er2\\),@\\(0x2:2,er1\\)" \ + "mov.w @(0x12345678:32,er2),@(0x2:2,er1)" +gdb_test "x" "mov.w @\\(0x12345678:32,er2\\),@er1\\+" \ + "mov.w @(0x12345678:32,er2),@er1+" +gdb_test "x" "mov.w @\\(0x12345678:32,er2\\),@-er1" \ + "mov.w @(0x12345678:32,er2),@-er1" +gdb_test "x" "mov.w @\\(0x12345678:32,er2\\),@\\+er1" \ + "mov.w @(0x12345678:32,er2),@+er1" +gdb_test "x" "mov.w @\\(0x12345678:32,er2\\),@er1-" \ + "mov.w @(0x12345678:32,er2),@er1-" +gdb_test "x" "mov.w @\\(0x12345678:32,er2\\),@\\(0x9abc(:16|),er1\\)" \ + "mov.w @(0x12345678:32,er2),@(0x9abc:16,er1)" +gdb_test "x" "mov.w @\\(0x12345678:32,er2\\),@\\(0x9abcdef0:32,er1\\)" \ + "mov.w @(0x12345678:32,er2),@(0x9abcdef0:32,er1)" +gdb_test "x" "mov.w @\\(0x12345678:32,er2\\),@\\(0x9abc(:16|),r3l.b\\)" \ + "mov.w @(0x12345678:32,er2),@(0x9abc:16,r3l.b)" +gdb_test "x" "mov.w @\\(0x12345678:32,er2\\),@\\(0x9abc(:16|),r3.w\\)" \ + "mov.w @(0x12345678:32,er2),@(0x9abc:16,r3.w)" +gdb_test "x" "mov.w @\\(0x12345678:32,er2\\),@\\(0x9abc(:16|),er3.l\\)" \ + "mov.w @(0x12345678:32,er2),@(0x9abc:16,er3.l)" +gdb_test "x" "mov.w @\\(0x12345678:32,er2\\),@\\(0x9abcdef0:32,r3l.b\\)" \ + "mov.w @(0x12345678:32,er2),@(0x9abcdef0:32,r3l.b)" +gdb_test "x" "mov.w @\\(0x12345678:32,er2\\),@\\(0x9abcdef0:32,r3.w\\)" \ + "mov.w @(0x12345678:32,er2),@(0x9abcdef0:32,r3.w)" +gdb_test "x" "mov.w @\\(0x12345678:32,er2\\),@\\(0x9abcdef0:32,er3.l\\)" \ + "mov.w @(0x12345678:32,er2),@(0x9abcdef0:32,er3.l)" +gdb_test "x" "mov.w @\\(0x12345678:32,er2\\),@0x9abc(:16|)" \ + "mov.w @(0x12345678:32,er2),@0x9abc:16" +gdb_test "x" "mov.w @\\(0x12345678:32,er2\\),@0x9abcdef0:32" \ + "mov.w @(0x12345678:32,er2),@0x9abcdef0:32" +gdb_test "x" "mov.w @\\(0x1234:16,r3l.b\\),@er1" \ + "mov.w @(0x1234:16,r3l.b),@er1" +gdb_test "x" "mov.w @\\(0x1234:16,r3l.b\\),@\\(0x2:2,er1\\)" \ + "mov.w @(0x1234:16,r3l.b),@(0x2:2,er1)" +gdb_test "x" "mov.w @\\(0x1234:16,r3l.b\\),@er1\\+" \ + "mov.w @(0x1234:16,r3l.b),@er1+" +gdb_test "x" "mov.w @\\(0x1234:16,r3l.b\\),@-er1" \ + "mov.w @(0x1234:16,r3l.b),@-er1" +gdb_test "x" "mov.w @\\(0x1234:16,r3l.b\\),@\\+er1" \ + "mov.w @(0x1234:16,r3l.b),@+er1" +gdb_test "x" "mov.w @\\(0x1234:16,r3l.b\\),@er1-" \ + "mov.w @(0x1234:16,r3l.b),@er1-" +gdb_test "x" "mov.w @\\(0x1234:16,r3l.b\\),@\\(0x9abc(:16|),er1\\)" \ + "mov.w @(0x1234:16,r3l.b),@(0x9abc:16,er1)" +gdb_test "x" "mov.w @\\(0x1234:16,r3l.b\\),@\\(0x9abcdef0:32,er1\\)" \ + "mov.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1)" +gdb_test "x" "mov.w @\\(0x1234:16,r3l.b\\),@\\(0x9abc(:16|),r3l.b\\)" \ + "mov.w @(0x1234:16,r3l.b),@(0x9abc:16,r3l.b)" +gdb_test "x" "mov.w @\\(0x1234:16,r3l.b\\),@\\(0x9abc(:16|),r3.w\\)" \ + "mov.w @(0x1234:16,r3l.b),@(0x9abc:16,r3.w)" +gdb_test "x" "mov.w @\\(0x1234:16,r3l.b\\),@\\(0x9abc(:16|),er3.l\\)" \ + "mov.w @(0x1234:16,r3l.b),@(0x9abc:16,er3.l)" +gdb_test "x" "mov.w @\\(0x1234:16,r3l.b\\),@\\(0x9abcdef0:32,r3l.b\\)" \ + "mov.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,r3l.b)" +gdb_test "x" "mov.w @\\(0x1234:16,r3l.b\\),@\\(0x9abcdef0:32,r3.w\\)" \ + "mov.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,r3.w)" +gdb_test "x" "mov.w @\\(0x1234:16,r3l.b\\),@\\(0x9abcdef0:32,er3.l\\)" \ + "mov.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,er3.l)" +gdb_test "x" "mov.w @\\(0x1234:16,r3l.b\\),@0x9abc(:16|)" \ + "mov.w @(0x1234:16,r3l.b),@0x9abc:16" +gdb_test "x" "mov.w @\\(0x1234:16,r3l.b\\),@0x9abcdef0:32" \ + "mov.w @(0x1234:16,r3l.b),@0x9abcdef0:32" +gdb_test "x" "mov.w @\\(0x1234:16,r3.w\\),@er1" \ + "mov.w @(0x1234:16,r3.w),@er1" +gdb_test "x" "mov.w @\\(0x1234:16,r3.w\\),@\\(0x2:2,er1\\)" \ + "mov.w @(0x1234:16,r3.w),@(0x2:2,er1)" +gdb_test "x" "mov.w @\\(0x1234:16,r3.w\\),@er1\\+" \ + "mov.w @(0x1234:16,r3.w),@er1+" +gdb_test "x" "mov.w @\\(0x1234:16,r3.w\\),@-er1" \ + "mov.w @(0x1234:16,r3.w),@-er1" +gdb_test "x" "mov.w @\\(0x1234:16,r3.w\\),@\\+er1" \ + "mov.w @(0x1234:16,r3.w),@+er1" +gdb_test "x" "mov.w @\\(0x1234:16,r3.w\\),@er1-" \ + "mov.w @(0x1234:16,r3.w),@er1-" +gdb_test "x" "mov.w @\\(0x1234:16,r3.w\\),@\\(0x9abc(:16|),er1\\)" \ + "mov.w @(0x1234:16,r3.w),@(0x9abc:16,er1)" +gdb_test "x" "mov.w @\\(0x1234:16,r3.w\\),@\\(0x9abcdef0:32,er1\\)" \ + "mov.w @(0x1234:16,r3.w),@(0x9abcdef0:32,er1)" +gdb_test "x" "mov.w @\\(0x1234:16,r3.w\\),@\\(0x9abc(:16|),r3l.b\\)" \ + "mov.w @(0x1234:16,r3.w),@(0x9abc:16,r3l.b)" +gdb_test "x" "mov.w @\\(0x1234:16,r3.w\\),@\\(0x9abc(:16|),r3.w\\)" \ + "mov.w @(0x1234:16,r3.w),@(0x9abc:16,r3.w)" +gdb_test "x" "mov.w @\\(0x1234:16,r3.w\\),@\\(0x9abc(:16|),er3.l\\)" \ + "mov.w @(0x1234:16,r3.w),@(0x9abc:16,er3.l)" +gdb_test "x" "mov.w @\\(0x1234:16,r3.w\\),@\\(0x9abcdef0:32,r3l.b\\)" \ + "mov.w @(0x1234:16,r3.w),@(0x9abcdef0:32,r3l.b)" +gdb_test "x" "mov.w @\\(0x1234:16,r3.w\\),@\\(0x9abcdef0:32,r3.w\\)" \ + "mov.w @(0x1234:16,r3.w),@(0x9abcdef0:32,r3.w)" +gdb_test "x" "mov.w @\\(0x1234:16,r3.w\\),@\\(0x9abcdef0:32,er3.l\\)" \ + "mov.w @(0x1234:16,r3.w),@(0x9abcdef0:32,er3.l)" +gdb_test "x" "mov.w @\\(0x1234:16,r3.w\\),@0x9abc(:16|)" \ + "mov.w @(0x1234:16,r3.w),@0x9abc:16" +gdb_test "x" "mov.w @\\(0x1234:16,r3.w\\),@0x9abcdef0:32" \ + "mov.w @(0x1234:16,r3.w),@0x9abcdef0:32" +gdb_test "x" "mov.w @\\(0x1234:16,er3.l\\),@er1" \ + "mov.w @(0x1234:16,er3.l),@er1" +gdb_test "x" "mov.w @\\(0x1234:16,er3.l\\),@\\(0x2:2,er1\\)" \ + "mov.w @(0x1234:16,er3.l),@(0x2:2,er1)" +gdb_test "x" "mov.w @\\(0x1234:16,er3.l\\),@er1\\+" \ + "mov.w @(0x1234:16,er3.l),@er1+" +gdb_test "x" "mov.w @\\(0x1234:16,er3.l\\),@-er1" \ + "mov.w @(0x1234:16,er3.l),@-er1" +gdb_test "x" "mov.w @\\(0x1234:16,er3.l\\),@\\+er1" \ + "mov.w @(0x1234:16,er3.l),@+er1" +gdb_test "x" "mov.w @\\(0x1234:16,er3.l\\),@er1-" \ + "mov.w @(0x1234:16,er3.l),@er1-" +gdb_test "x" "mov.w @\\(0x1234:16,er3.l\\),@\\(0x9abc(:16|),er1\\)" \ + "mov.w @(0x1234:16,er3.l),@(0x9abc:16,er1)" +gdb_test "x" "mov.w @\\(0x1234:16,er3.l\\),@\\(0x9abcdef0:32,er1\\)" \ + "mov.w @(0x1234:16,er3.l),@(0x9abcdef0:32,er1)" +gdb_test "x" "mov.w @\\(0x1234:16,er3.l\\),@\\(0x9abc(:16|),r3l.b\\)" \ + "mov.w @(0x1234:16,er3.l),@(0x9abc:16,r3l.b)" +gdb_test "x" "mov.w @\\(0x1234:16,er3.l\\),@\\(0x9abc(:16|),r3.w\\)" \ + "mov.w @(0x1234:16,er3.l),@(0x9abc:16,r3.w)" +gdb_test "x" "mov.w @\\(0x1234:16,er3.l\\),@\\(0x9abc(:16|),er3.l\\)" \ + "mov.w @(0x1234:16,er3.l),@(0x9abc:16,er3.l)" +gdb_test "x" "mov.w @\\(0x1234:16,er3.l\\),@\\(0x9abcdef0:32,r3l.b\\)" \ + "mov.w @(0x1234:16,er3.l),@(0x9abcdef0:32,r3l.b)" +gdb_test "x" "mov.w @\\(0x1234:16,er3.l\\),@\\(0x9abcdef0:32,r3.w\\)" \ + "mov.w @(0x1234:16,er3.l),@(0x9abcdef0:32,r3.w)" +gdb_test "x" "mov.w @\\(0x1234:16,er3.l\\),@\\(0x9abcdef0:32,er3.l\\)" \ + "mov.w @(0x1234:16,er3.l),@(0x9abcdef0:32,er3.l)" +gdb_test "x" "mov.w @\\(0x1234:16,er3.l\\),@0x9abc(:16|)" \ + "mov.w @(0x1234:16,er3.l),@0x9abc:16" +gdb_test "x" "mov.w @\\(0x1234:16,er3.l\\),@0x9abcdef0:32" \ + "mov.w @(0x1234:16,er3.l),@0x9abcdef0:32" +gdb_test "x" "mov.w @\\(0x12345678:32,r3l.b\\),@er1" \ + "mov.w @(0x12345678:32,r3l.b),@er1" +gdb_test "x" "mov.w @\\(0x12345678:32,r3l.b\\),@\\(0x2:2,er1\\)" \ + "mov.w @(0x12345678:32,r3l.b),@(0x2:2,er1)" +gdb_test "x" "mov.w @\\(0x12345678:32,r3l.b\\),@er1\\+" \ + "mov.w @(0x12345678:32,r3l.b),@er1+" +gdb_test "x" "mov.w @\\(0x12345678:32,r3l.b\\),@-er1" \ + "mov.w @(0x12345678:32,r3l.b),@-er1" +gdb_test "x" "mov.w @\\(0x12345678:32,r3l.b\\),@\\+er1" \ + "mov.w @(0x12345678:32,r3l.b),@+er1" +gdb_test "x" "mov.w @\\(0x12345678:32,r3l.b\\),@er1-" \ + "mov.w @(0x12345678:32,r3l.b),@er1-" +gdb_test "x" "mov.w @\\(0x12345678:32,r3l.b\\),@\\(0x9abc(:16|),er1\\)" \ + "mov.w @(0x12345678:32,r3l.b),@(0x9abc:16,er1)" +gdb_test "x" "mov.w @\\(0x12345678:32,r3l.b\\),@\\(0x9abcdef0:32,er1\\)" \ + "mov.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1)" +gdb_test "x" "mov.w @\\(0x12345678:32,r3l.b\\),@\\(0x9abc(:16|),r3l.b\\)" \ + "mov.w @(0x12345678:32,r3l.b),@(0x9abc:16,r3l.b)" +gdb_test "x" "mov.w @\\(0x12345678:32,r3l.b\\),@\\(0x9abc(:16|),r3.w\\)" \ + "mov.w @(0x12345678:32,r3l.b),@(0x9abc:16,r3.w)" +gdb_test "x" "mov.w @\\(0x12345678:32,r3l.b\\),@\\(0x9abc(:16|),er3.l\\)" \ + "mov.w @(0x12345678:32,r3l.b),@(0x9abc:16,er3.l)" +gdb_test "x" "mov.w\t@\\(0x12345678:32,r3l.b\\),@\\(0x9abcdef0:32,r3l.b\\)" \ + "mov.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r3l.b)" +gdb_test "x" "mov.w @\\(0x12345678:32,r3l.b\\),@\\(0x9abcdef0:32,r3.w\\)" \ + "mov.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r3.w)" +gdb_test "x" "mov.w\t@\\(0x12345678:32,r3l.b\\),@\\(0x9abcdef0:32,er3.l\\)" \ + "mov.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er3.l)" +gdb_test "x" "mov.w @\\(0x12345678:32,r3l.b\\),@0x9abc(:16|)" \ + "mov.w @(0x12345678:32,r3l.b),@0x9abc:16" +gdb_test "x" "mov.w @\\(0x12345678:32,r3l.b\\),@0x9abcdef0:32" \ + "mov.w @(0x12345678:32,r3l.b),@0x9abcdef0:32" +gdb_test "x" "mov.w @\\(0x12345678:32,r3.w\\),@er1" \ + "mov.w @(0x12345678:32,r3.w),@er1" +gdb_test "x" "mov.w @\\(0x12345678:32,r3.w\\),@\\(0x2:2,er1\\)" \ + "mov.w @(0x12345678:32,r3.w),@(0x2:2,er1)" +gdb_test "x" "mov.w @\\(0x12345678:32,r3.w\\),@er1\\+" \ + "mov.w @(0x12345678:32,r3.w),@er1+" +gdb_test "x" "mov.w @\\(0x12345678:32,r3.w\\),@-er1" \ + "mov.w @(0x12345678:32,r3.w),@-er1" +gdb_test "x" "mov.w @\\(0x12345678:32,r3.w\\),@\\+er1" \ + "mov.w @(0x12345678:32,r3.w),@+er1" +gdb_test "x" "mov.w @\\(0x12345678:32,r3.w\\),@er1-" \ + "mov.w @(0x12345678:32,r3.w),@er1-" +gdb_test "x" "mov.w @\\(0x12345678:32,r3.w\\),@\\(0x9abc(:16|),er1\\)" \ + "mov.w @(0x12345678:32,r3.w),@(0x9abc:16,er1)" +gdb_test "x" "mov.w @\\(0x12345678:32,r3.w\\),@\\(0x9abcdef0:32,er1\\)" \ + "mov.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1)" +gdb_test "x" "mov.w @\\(0x12345678:32,r3.w\\),@\\(0x9abc(:16|),r3l.b\\)" \ + "mov.w @(0x12345678:32,r3.w),@(0x9abc:16,r3l.b)" +gdb_test "x" "mov.w @\\(0x12345678:32,r3.w\\),@\\(0x9abc(:16|),r3.w\\)" \ + "mov.w @(0x12345678:32,r3.w),@(0x9abc:16,r3.w)" +gdb_test "x" "mov.w @\\(0x12345678:32,r3.w\\),@\\(0x9abc(:16|),er3.l\\)" \ + "mov.w @(0x12345678:32,r3.w),@(0x9abc:16,er3.l)" +gdb_test "x" "mov.w @\\(0x12345678:32,r3.w\\),@\\(0x9abcdef0:32,r3l.b\\)" \ + "mov.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,r3l.b)" +gdb_test "x" "mov.w @\\(0x12345678:32,r3.w\\),@\\(0x9abcdef0:32,r3.w\\)" \ + "mov.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,r3.w)" +gdb_test "x" "mov.w @\\(0x12345678:32,r3.w\\),@\\(0x9abcdef0:32,er3.l\\)" \ + "mov.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,er3.l)" +gdb_test "x" "mov.w @\\(0x12345678:32,r3.w\\),@0x9abc(:16|)" \ + "mov.w @(0x12345678:32,r3.w),@0x9abc:16" +gdb_test "x" "mov.w @\\(0x12345678:32,r3.w\\),@0x9abcdef0:32" \ + "mov.w @(0x12345678:32,r3.w),@0x9abcdef0:32" +gdb_test "x" "mov.w @\\(0x12345678:32,er3.l\\),@er1" \ + "mov.w @(0x12345678:32,er3.l),@er1" +gdb_test "x" "mov.w @\\(0x12345678:32,er3.l\\),@\\(0x2:2,er1\\)" \ + "mov.w @(0x12345678:32,er3.l),@(0x2:2,er1)" +gdb_test "x" "mov.w @\\(0x12345678:32,er3.l\\),@er1\\+" \ + "mov.w @(0x12345678:32,er3.l),@er1+" +gdb_test "x" "mov.w @\\(0x12345678:32,er3.l\\),@-er1" \ + "mov.w @(0x12345678:32,er3.l),@-er1" +gdb_test "x" "mov.w @\\(0x12345678:32,er3.l\\),@\\+er1" \ + "mov.w @(0x12345678:32,er3.l),@+er1" +gdb_test "x" "mov.w @\\(0x12345678:32,er3.l\\),@er1-" \ + "mov.w @(0x12345678:32,er3.l),@er1-" +gdb_test "x" "mov.w @\\(0x12345678:32,er3.l\\),@\\(0x9abc(:16|),er1\\)" \ + "mov.w @(0x12345678:32,er3.l),@(0x9abc:16,er1)" +gdb_test "x" "mov.w @\\(0x12345678:32,er3.l\\),@\\(0x9abcdef0:32,er1\\)" \ + "mov.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1)" +gdb_test "x" "mov.w @\\(0x12345678:32,er3.l\\),@\\(0x9abc(:16|),r3l.b\\)" \ + "mov.w @(0x12345678:32,er3.l),@(0x9abc:16,r3l.b)" +gdb_test "x" "mov.w @\\(0x12345678:32,er3.l\\),@\\(0x9abc(:16|),r3.w\\)" \ + "mov.w @(0x12345678:32,er3.l),@(0x9abc:16,r3.w)" +gdb_test "x" "mov.w @\\(0x12345678:32,er3.l\\),@\\(0x9abc(:16|),er3.l\\)" \ + "mov.w @(0x12345678:32,er3.l),@(0x9abc:16,er3.l)" +gdb_test "x" "mov.w @\\(0x12345678:32,er3.l\\),@\\(0x9abcdef0:32,r3l.b\\)" \ + "mov.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,r3l.b)" +gdb_test "x" "mov.w @\\(0x12345678:32,er3.l\\),@\\(0x9abcdef0:32,r3.w\\)" \ + "mov.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,r3.w)" +gdb_test "x" "mov.w @\\(0x12345678:32,er3.l\\),@\\(0x9abcdef0:32,er3.l\\)" \ + "mov.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,er3.l)" +gdb_test "x" "mov.w @\\(0x12345678:32,er3.l\\),@0x9abc(:16|)" \ + "mov.w @(0x12345678:32,er3.l),@0x9abc:16" +gdb_test "x" "mov.w @\\(0x12345678:32,er3.l\\),@0x9abcdef0:32" \ + "mov.w @(0x12345678:32,er3.l),@0x9abcdef0:32" +gdb_test "x" "mov.w @0x1234:16,@er1" \ + "mov.w @0x1234:16,@er1" +gdb_test "x" "mov.w @0x1234:16,@\\(0x2:2,er1\\)" \ + "mov.w @0x1234:16,@(0x2:2,er1)" +gdb_test "x" "mov.w @0x1234:16,@er1\\+" \ + "mov.w @0x1234:16,@er1+" +gdb_test "x" "mov.w @0x1234:16,@-er1" \ + "mov.w @0x1234:16,@-er1" +gdb_test "x" "mov.w @0x1234:16,@\\+er1" \ + "mov.w @0x1234:16,@+er1" +gdb_test "x" "mov.w @0x1234:16,@er1-" \ + "mov.w @0x1234:16,@er1-" +gdb_test "x" "mov.w @0x1234:16,@\\(0x9abc(:16|),er1\\)" \ + "mov.w @0x1234:16,@(0x9abc:16,er1)" +gdb_test "x" "mov.w @0x1234:16,@\\(0x9abcdef0:32,er1\\)" \ + "mov.w @0x1234:16,@(0x9abcdef0:32,er1)" +gdb_test "x" "mov.w @0x1234:16,@\\(0x9abc(:16|),r3l.b\\)" \ + "mov.w @0x1234:16,@(0x9abc:16,r3l.b)" +gdb_test "x" "mov.w @0x1234:16,@\\(0x9abc(:16|),r3.w\\)" \ + "mov.w @0x1234:16,@(0x9abc:16,r3.w)" +gdb_test "x" "mov.w @0x1234:16,@\\(0x9abc(:16|),er3.l\\)" \ + "mov.w @0x1234:16,@(0x9abc:16,er3.l)" +gdb_test "x" "mov.w @0x1234:16,@\\(0x9abcdef0:32,r3l.b\\)" \ + "mov.w @0x1234:16,@(0x9abcdef0:32,r3l.b)" +gdb_test "x" "mov.w @0x1234:16,@\\(0x9abcdef0:32,r3.w\\)" \ + "mov.w @0x1234:16,@(0x9abcdef0:32,r3.w)" +gdb_test "x" "mov.w @0x1234:16,@\\(0x9abcdef0:32,er3.l\\)" \ + "mov.w @0x1234:16,@(0x9abcdef0:32,er3.l)" +gdb_test "x" "mov.w @0x1234:16,@0x9abc(:16|)" \ + "mov.w @0x1234:16,@0x9abc:16" +gdb_test "x" "mov.w @0x1234:16,@0x9abcdef0:32" \ + "mov.w @0x1234:16,@0x9abcdef0:32" +gdb_test "x" "mov.w @0x12345678:32,@er1" \ + "mov.w @0x12345678:32,@er1" +gdb_test "x" "mov.w @0x12345678:32,@\\(0x2:2,er1\\)" \ + "mov.w @0x12345678:32,@(0x2:2,er1)" +gdb_test "x" "mov.w @0x12345678:32,@er1\\+" \ + "mov.w @0x12345678:32,@er1+" +gdb_test "x" "mov.w @0x12345678:32,@-er1" \ + "mov.w @0x12345678:32,@-er1" +gdb_test "x" "mov.w @0x12345678:32,@\\+er1" \ + "mov.w @0x12345678:32,@+er1" +gdb_test "x" "mov.w @0x12345678:32,@er1-" \ + "mov.w @0x12345678:32,@er1-" +gdb_test "x" "mov.w @0x12345678:32,@\\(0x9abc(:16|),er1\\)" \ + "mov.w @0x12345678:32,@(0x9abc:16,er1)" +gdb_test "x" "mov.w @0x12345678:32,@\\(0x9abcdef0:32,er1\\)" \ + "mov.w @0x12345678:32,@(0x9abcdef0:32,er1)" +gdb_test "x" "mov.w @0x12345678:32,@\\(0x9abc(:16|),r3l.b\\)" \ + "mov.w @0x12345678:32,@(0x9abc:16,r3l.b)" +gdb_test "x" "mov.w @0x12345678:32,@\\(0x9abc(:16|),r3.w\\)" \ + "mov.w @0x12345678:32,@(0x9abc:16,r3.w)" +gdb_test "x" "mov.w @0x12345678:32,@\\(0x9abc(:16|),er3.l\\)" \ + "mov.w @0x12345678:32,@(0x9abc:16,er3.l)" +gdb_test "x" "mov.w @0x12345678:32,@\\(0x9abcdef0:32,r3l.b\\)" \ + "mov.w @0x12345678:32,@(0x9abcdef0:32,r3l.b)" +gdb_test "x" "mov.w @0x12345678:32,@\\(0x9abcdef0:32,r3.w\\)" \ + "mov.w @0x12345678:32,@(0x9abcdef0:32,r3.w)" +gdb_test "x" "mov.w @0x12345678:32,@\\(0x9abcdef0:32,er3.l\\)" \ + "mov.w @0x12345678:32,@(0x9abcdef0:32,er3.l)" +gdb_test "x" "mov.w @0x12345678:32,@0x9abc(:16|)" \ + "mov.w @0x12345678:32,@0x9abc:16" +gdb_test "x" "mov.w @0x12345678:32,@0x9abcdef0:32" \ + "mov.w @0x12345678:32,@0x9abcdef0:32" +gdb_test "x" "mov.l #0x12345678(:32|),er1" \ + "mov.l #0x12345678:32,er1" +gdb_test "x" "mov.l #0x1234(:16|),er1" \ + "mov.l #0x1234:16,er1" +gdb_test "x" "mov.l #0x1(:3|),er3" \ + "mov.l #0x1:3,er3" +gdb_test "x" "mov.l #0x12345678(:32|),@er1" \ + "mov.l #0x12345678:32,@er1" +gdb_test "x" "mov.l #0x12345678(:32|),@\\(0x4:2,er1\\)" \ + "mov.l #0x12345678:32,@(0x4:2,er1)" +gdb_test "x" "mov.l #0x12345678(:32|),@-er1" \ + "mov.l #0x12345678:32,@-er1" +gdb_test "x" "mov.l #0x12345678(:32|),@er1\\+" \ + "mov.l #0x12345678:32,@er1+" +gdb_test "x" "mov.l #0x12345678(:32|),@er1-" \ + "mov.l #0x12345678:32,@er1-" +gdb_test "x" "mov.l #0x12345678(:32|),@\\+er1" \ + "mov.l #0x12345678:32,@+er1" +gdb_test "x" "mov.l #0x12345678(:32|),@\\(0x1234:16,er1\\)" \ + "mov.l #0x12345678:32,@(0x1234:16,er1)" +gdb_test "x" "mov.l #0x12345678(:32|),@\\(0x12345678:32,er1\\)" \ + "mov.l #0x12345678:32,@(0x12345678:32,er1)" +gdb_test "x" "mov.l #0x12345678(:32|),@\\(0x1234:16,r3l.b\\)" \ + "mov.l #0x12345678:32,@(0x1234:16,r3l.b)" +gdb_test "x" "mov.l #0x12345678(:32|),@\\(0x1234:16,r3.w\\)" \ + "mov.l #0x12345678:32,@(0x1234:16,r3.w)" +gdb_test "x" "mov.l #0x12345678(:32|),@\\(0x1234:16,er3.l\\)" \ + "mov.l #0x12345678:32,@(0x1234:16,er3.l)" +gdb_test "x" "mov.l #0x12345678(:32|),@\\(0x12345678:32,r3l.b\\)" \ + "mov.l #0x12345678:32,@(0x12345678:32,r3l.b)" +gdb_test "x" "mov.l #0x12345678(:32|),@\\(0x12345678:32,r3.w\\)" \ + "mov.l #0x12345678:32,@(0x12345678:32,r3.w)" +gdb_test "x" "mov.l #0x12345678(:32|),@\\(0x12345678:32,er3.l\\)" \ + "mov.l #0x12345678:32,@(0x12345678:32,er3.l)" +gdb_test "x" "mov.l #0x12345678(:32|),@0x1234:16" \ + "mov.l #0x12345678:32,@0x1234:16" +gdb_test "x" "mov.l #0x12345678(:32|),@0x12345678:32" \ + "mov.l #0x12345678:32,@0x12345678:32" +gdb_test "x" "mov.l #0x1234(:16|),@er1" \ + "mov.l #0x1234:16,@er1" +gdb_test "x" "mov.l #0x1234(:16|),@\\(0x4:2,er1\\)" \ + "mov.l #0x1234:16,@\\(0x4:2,er1)" +gdb_test "x" "mov.l #0x1234(:16|),@-er1" \ + "mov.l #0x1234:16,@-er1" +gdb_test "x" "mov.l #0x1234(:16|),@er1\\+" \ + "mov.l #0x1234:16,@er1+" +gdb_test "x" "mov.l #0x1234(:16|),@er1-" \ + "mov.l #0x1234:16,@er1-" +gdb_test "x" "mov.l #0x1234(:16|),@\\+er1" \ + "mov.l #0x1234:16,@+er1" +gdb_test "x" "mov.l #0x1234(:16|),@\\(0x1234:16,er1\\)" \ + "mov.l #0x1234:16,@(0x1234:16,er1)" +gdb_test "x" "mov.l #0x1234(:16|),@\\(0x12345678:32,er1\\)" \ + "mov.l #0x1234:16,@(0x12345678:32,er1)" +gdb_test "x" "mov.l #0x1234(:16|),@\\(0x1234:16,r3l.b\\)" \ + "mov.l #0x1234:16,@(0x1234:16,r3l.b)" +gdb_test "x" "mov.l #0x1234(:16|),@\\(0x1234:16,r3.w\\)" \ + "mov.l #0x1234:16,@(0x1234:16,r3.w)" +gdb_test "x" "mov.l #0x1234(:16|),@\\(0x1234:16,er3.l\\)" \ + "mov.l #0x1234:16,@(0x1234:16,er3.l)" +gdb_test "x" "mov.l #0x1234(:16|),@\\(0x12345678:32,r3l.b\\)" \ + "mov.l #0x1234:16,@(0x12345678:32,r3l.b)" +gdb_test "x" "mov.l #0x1234(:16|),@\\(0x12345678:32,r3.w\\)" \ + "mov.l #0x1234:16,@(0x12345678:32,r3.w)" +gdb_test "x" "mov.l #0x1234(:16|),@\\(0x12345678:32,er3.l\\)" \ + "mov.l #0x1234:16,@(0x12345678:32,er3.l)" +gdb_test "x" "mov.l #0x1234(:16|),@0x1234:16" \ + "mov.l #0x1234:16,@0x1234:16" +gdb_test "x" "mov.l #0x1234(:16|),@0x12345678:32" \ + "mov.l #0x1234:16,@0x12345678:32" +gdb_test "x" "mov.l #0x12(:8|),@er1" \ + "mov.l #0x12:8,@er1" +gdb_test "x" "mov.l #0x12(:8|),@\\(0x4:2,er1\\)" \ + "mov.l #0x12:8,@(0x4:2,er1)" +gdb_test "x" "mov.l #0x12(:8|),@-er1" \ + "mov.l #0x12:8,@-er1" +gdb_test "x" "mov.l #0x12(:8|),@er1\\+" \ + "mov.l #0x12:8,@er1+" +gdb_test "x" "mov.l #0x12(:8|),@er1-" \ + "mov.l #0x12:8,@er1-" +gdb_test "x" "mov.l #0x12(:8|),@\\+er1" \ + "mov.l #0x12:8,@+er1" +gdb_test "x" "mov.l #0x12(:8|),@\\(0x1234:16,er1\\)" \ + "mov.l #0x12:8,@(0x1234:16,er1)" +gdb_test "x" "mov.l #0x12(:8|),@\\(0x12345678:32,er1\\)" \ + "mov.l #0x12:8,@(0x12345678:32,er1)" +gdb_test "x" "mov.l #0x12(:8|),@\\(0x1234:16,r3l.b\\)" \ + "mov.l #0x12:8,@(0x1234:16,r3l.b)" +gdb_test "x" "mov.l #0x12(:8|),@\\(0x1234:16,r3.w\\)" \ + "mov.l #0x12:8,@(0x1234:16,r3.w)" +gdb_test "x" "mov.l #0x12(:8|),@\\(0x1234:16,er3.l\\)" \ + "mov.l #0x12:8,@(0x1234:16,er3.l)" +gdb_test "x" "mov.l #0x12(:8|),@\\(0x12345678:32,r3l.b\\)" \ + "mov.l #0x12:8,@(0x12345678:32,r3l.b)" +gdb_test "x" "mov.l #0x12(:8|),@\\(0x12345678:32,r3.w\\)" \ + "mov.l #0x12:8,@(0x12345678:32,r3.w)" +gdb_test "x" "mov.l #0x12(:8|),@\\(0x12345678:32,er3.l\\)" \ + "mov.l #0x12:8,@\\(0x12345678:32,er3.l)" +gdb_test "x" "mov.l #0x12(:8|),@0x1234:16" \ + "mov.l #0x12:8,@0x1234:16" +gdb_test "x" "mov.l #0x12(:8|),@0x12345678:32" \ + "mov.l #0x12:8,@0x12345678:32" +gdb_test "x" "mov.l er2,er1" \ + "mov.l er2,er1" +gdb_test "x" "mov.l er2,@er1" \ + "mov.l er2,@er1" +gdb_test "x" "mov.l er2,@\\(0x4:2,er1\\)" \ + "mov.l er2,@(0x4:2,er1)" +gdb_test "x" "mov.l er2,@-er1" \ + "mov.l er2,@-er1" +gdb_test "x" "mov.l er2,@er1\\+" \ + "mov.l er2,@er1+" +gdb_test "x" "mov.l er2,@er1-" \ + "mov.l er2,@er1-" +gdb_test "x" "mov.l er2,@\\+er1" \ + "mov.l er2,@+er1" +gdb_test "x" "mov.l er2,@\\(0x1234:16,er1\\)" \ + "mov.l er2,@(0x1234:16,er1)" +gdb_test "x" "mov.l er2,@\\(0x12345678:32,er1\\)" \ + "mov.l er2,@(0x12345678:32,er1)" +gdb_test "x" "mov.l er2,@\\(0x1234:16,r3l.b\\)" \ + "mov.l er2,@(0x1234:16,r3l.b)" +gdb_test "x" "mov.l er2,@\\(0x1234:16,r3.w\\)" \ + "mov.l er2,@(0x1234:16,r3.w)" +gdb_test "x" "mov.l er2,@\\(0x1234:16,er3.l\\)" \ + "mov.l er2,@(0x1234:16,er3.l)" +gdb_test "x" "mov.l er2,@\\(0x12345678:32,r3l.b\\)" \ + "mov.l er2,@(0x12345678:32,r3l.b)" +gdb_test "x" "mov.l er2,@\\(0x12345678:32,r3.w\\)" \ + "mov.l er2,@(0x12345678:32,r3.w)" +gdb_test "x" "mov.l er2,@\\(0x12345678:32,er3.l\\)" \ + "mov.l er2,@(0x12345678:32,er3.l)" +gdb_test "x" "mov.l er2,@0x1234:16" \ + "mov.l er2,@0x1234:16" +gdb_test "x" "mov.l er2,@0x12345678:32" \ + "mov.l er2,@0x12345678:32" +gdb_test "x" "mov.l @er2,er1" \ + "mov.l @er2,er1" +gdb_test "x" "mov.l @\\(0x4:2,er2\\),er1" \ + "mov.l @(0x4:2,er2),er1" +gdb_test "x" "mov.l @er2\\+,er1" \ + "mov.l @er2+,er1" +gdb_test "x" "mov.l @-er2,er1" \ + "mov.l @-er2,er1" +gdb_test "x" "mov.l @\\+er2,er1" \ + "mov.l @+er2,er1" +gdb_test "x" "mov.l @er2-,er1" \ + "mov.l @er2-,er1" +gdb_test "x" "mov.l @\\(0x1234:16,er1\\),er1" \ + "mov.l @(0x1234:16,er1),er1" +gdb_test "x" "mov.l @\\(0x12345678:32,er1\\),er1" \ + "mov.l @(0x12345678:32,er1),er1" +gdb_test "x" "mov.l @\\(0x1234:16,r3l.b\\),er1" \ + "mov.l @(0x1234:16,r3l.b),er1" +gdb_test "x" "mov.l @\\(0x1234:16,r3.w\\),er1" \ + "mov.l @(0x1234:16,r3.w),er1" +gdb_test "x" "mov.l @\\(0x1234:16,er3.l\\),er1" \ + "mov.l @(0x1234:16,er3.l),er1" +gdb_test "x" "mov.l @\\(0x12345678:32,r3l.b\\),er1" \ + "mov.l @(0x12345678:32,r3l.b),er1" +gdb_test "x" "mov.l @\\(0x12345678:32,r3.w\\),er1" \ + "mov.l @(0x12345678:32,r3.w),er1" +gdb_test "x" "mov.l @\\(0x12345678:32,er3.l\\),er1" \ + "mov.l @(0x12345678:32,er3.l),er1" +gdb_test "x" "mov.l @0x1234:16,er1" \ + "mov.l @0x1234:16,er1" +gdb_test "x" "mov.l @0x12345678:32,er1" \ + "mov.l @0x12345678:32,er1" +gdb_test "x" "mov.l @er2,@er1" \ + "mov.l @er2,@er1" +gdb_test "x" "mov.l @er2,@\\(0x4:2,er1\\)" \ + "mov.l @er2,@(0x4:2,er1)" +gdb_test "x" "mov.l @er2,@er1\\+" \ + "mov.l @er2,@er1+" +gdb_test "x" "mov.l @er2,@-er1" \ + "mov.l @er2,@-er1" +gdb_test "x" "mov.l @er2,@\\+er1" \ + "mov.l @er2,@+er1" +gdb_test "x" "mov.l @er2,@er1-" \ + "mov.l @er2,@er1-" +gdb_test "x" "mov.l @er2,@\\(0x1234:16,er1\\)" \ + "mov.l @er2,@(0x1234:16,er1)" +gdb_test "x" "mov.l @er2,@\\(0x12345678:32,er1\\)" \ + "mov.l @er2,@(0x12345678:32,er1)" +gdb_test "x" "mov.l @er2,@\\(0x1234:16,r3l.b\\)" \ + "mov.l @er2,@(0x1234:16,r3l.b)" +gdb_test "x" "mov.l @er2,@\\(0x1234:16,r3.w\\)" \ + "mov.l @er2,@(0x1234:16,r3.w)" +gdb_test "x" "mov.l @er2,@\\(0x1234:16,er3.l\\)" \ + "mov.l @er2,@(0x1234:16,er3.l)" +gdb_test "x" "mov.l @er2,@\\(0x12345678:32,r3l.b\\)" \ + "mov.l @er2,@(0x12345678:32,r3l.b)" +gdb_test "x" "mov.l @er2,@\\(0x12345678:32,r3.w\\)" \ + "mov.l @er2,@(0x12345678:32,r3.w)" +gdb_test "x" "mov.l @er2,@\\(0x12345678:32,er3.l\\)" \ + "mov.l @er2,@(0x12345678:32,er3.l)" +gdb_test "x" "mov.l @er2,@0x1234:16" \ + "mov.l @er2,@0x1234:16" +gdb_test "x" "mov.l @er2,@0x12345678:32" \ + "mov.l @er2,@0x12345678:32" +gdb_test "x" "mov.l @\\(0x4:2,er2\\),@er1" \ + "mov.l @(0x4:2,er2),@er1" +gdb_test "x" "mov.l @\\(0x4:2,er2\\),@\\(0x4:2,er1\\)" \ + "mov.l @(0x4:2,er2),@(0x4:2,er1)" +gdb_test "x" "mov.l @\\(0x4:2,er2\\),@er1\\+" \ + "mov.l @(0x4:2,er2),@er1+" +gdb_test "x" "mov.l @\\(0x4:2,er2\\),@-er1" \ + "mov.l @(0x4:2,er2),@-er1" +gdb_test "x" "mov.l @\\(0x4:2,er2\\),@\\+er1" \ + "mov.l @(0x4:2,er2),@+er1" +gdb_test "x" "mov.l @\\(0x4:2,er2\\),@er1-" \ + "mov.l @(0x4:2,er2),@er1-" +gdb_test "x" "mov.l @\\(0x4:2,er2\\),@\\(0x1234:16,er1\\)" \ + "mov.l @(0x4:2,er2),@(0x1234:16,er1)" +gdb_test "x" "mov.l @\\(0x4:2,er2\\),@\\(0x12345678:32,er1\\)" \ + "mov.l @(0x4:2,er2),@(0x12345678:32,er1)" +gdb_test "x" "mov.l @\\(0x4:2,er2\\),@\\(0x1234:16,r3l.b\\)" \ + "mov.l @(0x4:2,er2),@(0x1234:16,r3l.b)" +gdb_test "x" "mov.l @\\(0x4:2,er2\\),@\\(0x1234:16,r3.w\\)" \ + "mov.l @(0x4:2,er2),@(0x1234:16,r3.w)" +gdb_test "x" "mov.l @\\(0x4:2,er2\\),@\\(0x1234:16,er3.l\\)" \ + "mov.l @(0x4:2,er2),@(0x1234:16,er3.l)" +gdb_test "x" "mov.l @\\(0x4:2,er2\\),@\\(0x12345678:32,r3l.b\\)" \ + "mov.l @(0x4:2,er2),@(0x12345678:32,r3l.b)" +gdb_test "x" "mov.l @\\(0x4:2,er2\\),@\\(0x12345678:32,r3.w\\)" \ + "mov.l @(0x4:2,er2),@(0x12345678:32,r3.w)" +gdb_test "x" "mov.l @\\(0x4:2,er2\\),@\\(0x12345678:32,er3.l\\)" \ + "mov.l @(0x4:2,er2),@(0x12345678:32,er3.l)" +gdb_test "x" "mov.l @\\(0x4:2,er2\\),@0x1234:16" \ + "mov.l @(0x4:2,er2),@0x1234:16" +gdb_test "x" "mov.l @\\(0x4:2,er2\\),@0x12345678:32" \ + "mov.l @(0x4:2,er2),@0x12345678:32" +gdb_test "x" "mov.l @-er2,@er1" \ + "mov.l @-er2,@er1" +gdb_test "x" "mov.l @-er2,@\\(0x4:2,er1\\)" \ + "mov.l @-er2,@(0x4:2,er1)" +gdb_test "x" "mov.l @-er2,@er1\\+" \ + "mov.l @-er2,@er1+" +gdb_test "x" "mov.l @-er2,@-er1" \ + "mov.l @-er2,@-er1" +gdb_test "x" "mov.l @-er2,@\\+er1" \ + "mov.l @-er2,@+er1" +gdb_test "x" "mov.l @-er2,@er1-" \ + "mov.l @-er2,@er1-" +gdb_test "x" "mov.l @-er2,@\\(0x1234:16,er1\\)" \ + "mov.l @-er2,@(0x1234:16,er1)" +gdb_test "x" "mov.l @-er2,@\\(0x12345678:32,er1\\)" \ + "mov.l @-er2,@(0x12345678:32,er1)" +gdb_test "x" "mov.l @-er2,@\\(0x1234:16,r3l.b\\)" \ + "mov.l @-er2,@(0x1234:16,r3l.b)" +gdb_test "x" "mov.l @-er2,@\\(0x1234:16,r3.w\\)" \ + "mov.l @-er2,@(0x1234:16,r3.w)" +gdb_test "x" "mov.l @-er2,@\\(0x1234:16,er3.l\\)" \ + "mov.l @-er2,@(0x1234:16,er3.l)" +gdb_test "x" "mov.l @-er2,@\\(0x12345678:32,r3l.b\\)" \ + "mov.l @-er2,@(0x12345678:32,r3l.b)" +gdb_test "x" "mov.l @-er2,@\\(0x12345678:32,r3.w\\)" \ + "mov.l @-er2,@(0x12345678:32,r3.w)" +gdb_test "x" "mov.l @-er2,@\\(0x12345678:32,er3.l\\)" \ + "mov.l @-er2,@(0x12345678:32,er3.l)" +gdb_test "x" "mov.l @-er2,@0x1234:16" \ + "mov.l @-er2,@0x1234:16" +gdb_test "x" "mov.l @-er2,@0x12345678:32" \ + "mov.l @-er2,@0x12345678:32" +gdb_test "x" "mov.l @er2\\+,@er1" \ + "mov.l @er2+,@er1" +gdb_test "x" "mov.l @er2\\+,@\\(0x4:2,er1\\)" \ + "mov.l @er2+,@(0x4:2,er1)" +gdb_test "x" "mov.l @er2\\+,@er1\\+" \ + "mov.l @er2+,@er1+" +gdb_test "x" "mov.l @er2\\+,@-er1" \ + "mov.l @er2+,@-er1" +gdb_test "x" "mov.l @er2\\+,@\\+er1" \ + "mov.l @er2+,@+er1" +gdb_test "x" "mov.l @er2\\+,@er1-" \ + "mov.l @er2+,@er1-" +gdb_test "x" "mov.l @er2\\+,@\\(0x1234:16,er1\\)" \ + "mov.l @er2+,@(0x1234:16,er1)" +gdb_test "x" "mov.l @er2\\+,@\\(0x12345678:32,er1\\)" \ + "mov.l @er2+,@(0x12345678:32,er1)" +gdb_test "x" "mov.l @er2\\+,@\\(0x1234:16,r3l.b\\)" \ + "mov.l @er2+,@(0x1234:16,r3l.b)" +gdb_test "x" "mov.l @er2\\+,@\\(0x1234:16,r3.w\\)" \ + "mov.l @er2+,@(0x1234:16,r3.w)" +gdb_test "x" "mov.l @er2\\+,@\\(0x1234:16,er3.l\\)" \ + "mov.l @er2+,@(0x1234:16,er3.l)" +gdb_test "x" "mov.l @er2\\+,@\\(0x12345678:32,r3l.b\\)" \ + "mov.l @er2+,@(0x12345678:32,r3l.b)" +gdb_test "x" "mov.l @er2\\+,@\\(0x12345678:32,r3.w\\)" \ + "mov.l @er2+,@(0x12345678:32,r3.w)" +gdb_test "x" "mov.l @er2\\+,@\\(0x12345678:32,er3.l\\)" \ + "mov.l @er2+,@(0x12345678:32,er3.l)" +gdb_test "x" "mov.l @er2\\+,@0x1234:16" \ + "mov.l @er2+,@0x1234:16" +gdb_test "x" "mov.l @er2\\+,@0x12345678:32" \ + "mov.l @er2+,@0x12345678:32" +gdb_test "x" "mov.l @er2-,@er1" \ + "mov.l @er2-,@er1" +gdb_test "x" "mov.l @er2-,@\\(0x4:2,er1\\)" \ + "mov.l @er2-,@(0x4:2,er1)" +gdb_test "x" "mov.l @er2-,@er1\\+" \ + "mov.l @er2-,@er1+" +gdb_test "x" "mov.l @er2-,@-er1" \ + "mov.l @er2-,@-er1" +gdb_test "x" "mov.l @er2-,@\\+er1" \ + "mov.l @er2-,@+er1" +gdb_test "x" "mov.l @er2-,@er1-" \ + "mov.l @er2-,@er1-" +gdb_test "x" "mov.l @er2-,@\\(0x1234:16,er1\\)" \ + "mov.l @er2-,@(0x1234:16,er1)" +gdb_test "x" "mov.l @er2-,@\\(0x12345678:32,er1\\)" \ + "mov.l @er2-,@(0x12345678:32,er1)" +gdb_test "x" "mov.l @er2-,@\\(0x1234:16,r3l.b\\)" \ + "mov.l @er2-,@(0x1234:16,r3l.b)" +gdb_test "x" "mov.l @er2-,@\\(0x1234:16,r3.w\\)" \ + "mov.l @er2-,@(0x1234:16,r3.w)" +gdb_test "x" "mov.l @er2-,@\\(0x1234:16,er3.l\\)" \ + "mov.l @er2-,@(0x1234:16,er3.l)" +gdb_test "x" "mov.l @er2-,@\\(0x12345678:32,r3l.b\\)" \ + "mov.l @er2-,@(0x12345678:32,r3l.b)" +gdb_test "x" "mov.l @er2-,@\\(0x12345678:32,r3.w\\)" \ + "mov.l @er2-,@(0x12345678:32,r3.w)" +gdb_test "x" "mov.l @er2-,@\\(0x12345678:32,er3.l\\)" \ + "mov.l @er2-,@(0x12345678:32,er3.l)" +gdb_test "x" "mov.l @er2-,@0x1234:16" \ + "mov.l @er2-,@0x1234:16" +gdb_test "x" "mov.l @er2-,@0x12345678:32" \ + "mov.l @er2-,@0x12345678:32" +gdb_test "x" "mov.l @\\+er2,@er1" \ + "mov.l @+er2,@er1" +gdb_test "x" "mov.l @\\+er2,@\\(0x4:2,er1\\)" \ + "mov.l @+er2,@(0x4:2,er1)" +gdb_test "x" "mov.l @\\+er2,@er1\\+" \ + "mov.l @+er2,@er1+" +gdb_test "x" "mov.l @\\+er2,@-er1" \ + "mov.l @+er2,@-er1" +gdb_test "x" "mov.l @\\+er2,@\\+er1" \ + "mov.l @+er2,@+er1" +gdb_test "x" "mov.l @\\+er2,@er1-" \ + "mov.l @+er2,@er1-" +gdb_test "x" "mov.l @\\+er2,@\\(0x1234:16,er1\\)" \ + "mov.l @+er2,@(0x1234:16,er1)" +gdb_test "x" "mov.l @\\+er2,@\\(0x12345678:32,er1\\)" \ + "mov.l @+er2,@(0x12345678:32,er1)" +gdb_test "x" "mov.l @\\+er2,@\\(0x1234:16,r3l.b\\)" \ + "mov.l @+er2,@(0x1234:16,r3l.b)" +gdb_test "x" "mov.l @\\+er2,@\\(0x1234:16,r3.w\\)" \ + "mov.l @+er2,@(0x1234:16,r3.w)" +gdb_test "x" "mov.l @\\+er2,@\\(0x1234:16,er3.l\\)" \ + "mov.l @+er2,@(0x1234:16,er3.l)" +gdb_test "x" "mov.l @\\+er2,@\\(0x12345678:32,r3l.b\\)" \ + "mov.l @+er2,@(0x12345678:32,r3l.b)" +gdb_test "x" "mov.l @\\+er2,@\\(0x12345678:32,r3.w\\)" \ + "mov.l @+er2,@(0x12345678:32,r3.w)" +gdb_test "x" "mov.l @\\+er2,@\\(0x12345678:32,er3.l\\)" \ + "mov.l @+er2,@(0x12345678:32,er3.l)" +gdb_test "x" "mov.l @\\+er2,@0x1234:16" \ + "mov.l @+er2,@0x1234:16" +gdb_test "x" "mov.l @\\+er2,@0x12345678:32" \ + "mov.l @+er2,@0x12345678:32" +gdb_test "x" "mov.l @\\(0x1234:16,er2\\),@er1" \ + "mov.l @(0x1234:16,er2),@er1" +gdb_test "x" "mov.l @\\(0x1234:16,er2\\),@\\(0x4:2,er1\\)" \ + "mov.l @(0x1234:16,er2),@(0x4:2,er1)" +gdb_test "x" "mov.l @\\(0x1234:16,er2\\),@er1\\+" \ + "mov.l @(0x1234:16,er2),@er1+" +gdb_test "x" "mov.l @\\(0x1234:16,er2\\),@-er1" \ + "mov.l @(0x1234:16,er2),@-er1" +gdb_test "x" "mov.l @\\(0x1234:16,er2\\),@\\+er1" \ + "mov.l @(0x1234:16,er2),@+er1" +gdb_test "x" "mov.l @\\(0x1234:16,er2\\),@er1-" \ + "mov.l @(0x1234:16,er2),@er1-" +gdb_test "x" "mov.l @\\(0x1234:16,er2\\),@\\(0x9abc(:16|),er1\\)" \ + "mov.l @(0x1234:16,er2),@(0x9abc:16,er1)" +gdb_test "x" "mov.l @\\(0x1234:16,er2\\),@\\(0x9abcdef0:32,er1\\)" \ + "mov.l @(0x1234:16,er2),@(0x9abcdef0:32,er1)" +gdb_test "x" "mov.l @\\(0x1234:16,er2\\),@\\(0x9abc(:16|),r3l.b\\)" \ + "mov.l @(0x1234:16,er2),@(0x9abc:16,r3l.b)" +gdb_test "x" "mov.l @\\(0x1234:16,er2\\),@\\(0x9abc(:16|),r3.w\\)" \ + "mov.l @(0x1234:16,er2),@(0x9abc:16,r3.w)" +gdb_test "x" "mov.l @\\(0x1234:16,er2\\),@\\(0x9abc(:16|),er3.l\\)" \ + "mov.l @(0x1234:16,er2),@(0x9abc:16,er3.l)" +gdb_test "x" "mov.l @\\(0x1234:16,er2\\),@\\(0x9abcdef0:32,r3l.b\\)" \ + "mov.l @(0x1234:16,er2),@(0x9abcdef0:32,r3l.b)" +gdb_test "x" "mov.l @\\(0x1234:16,er2\\),@\\(0x9abcdef0:32,r3.w\\)" \ + "mov.l @(0x1234:16,er2),@(0x9abcdef0:32,r3.w)" +gdb_test "x" "mov.l @\\(0x1234:16,er2\\),@\\(0x9abcdef0:32,er3.l\\)" \ + "mov.l @(0x1234:16,er2),@(0x9abcdef0:32,er3.l)" +gdb_test "x" "mov.l @\\(0x1234:16,er2\\),@0x9abc(:16|)" \ + "mov.l @(0x1234:16,er2),@0x9abc:16" +gdb_test "x" "mov.l @\\(0x1234:16,er2\\),@0x9abcdef0:32" \ + "mov.l @(0x1234:16,er2),@0x9abcdef0:32" +gdb_test "x" "mov.l @\\(0x12345678:32,er2\\),@er1" \ + "mov.l @(0x12345678:32,er2),@er1" +gdb_test "x" "mov.l @\\(0x12345678:32,er2\\),@\\(0x4:2,er1\\)" \ + "mov.l @(0x12345678:32,er2),@(0x4:2,er1)" +gdb_test "x" "mov.l @\\(0x12345678:32,er2\\),@er1\\+" \ + "mov.l @(0x12345678:32,er2),@er1+" +gdb_test "x" "mov.l @\\(0x12345678:32,er2\\),@-er1" \ + "mov.l @(0x12345678:32,er2),@-er1" +gdb_test "x" "mov.l @\\(0x12345678:32,er2\\),@\\+er1" \ + "mov.l @(0x12345678:32,er2),@+er1" +gdb_test "x" "mov.l @\\(0x12345678:32,er2\\),@er1-" \ + "mov.l @(0x12345678:32,er2),@er1-" +gdb_test "x" "mov.l @\\(0x12345678:32,er2\\),@\\(0x9abc(:16|),er1\\)" \ + "mov.l @(0x12345678:32,er2),@(0x9abc:16,er1)" +gdb_test "x" "mov.l @\\(0x12345678:32,er2\\),@\\(0x9abcdef0:32,er1\\)" \ + "mov.l @(0x12345678:32,er2),@(0x9abcdef0:32,er1)" +gdb_test "x" "mov.l @\\(0x12345678:32,er2\\),@\\(0x9abc(:16|),r3l.b\\)" \ + "mov.l @(0x12345678:32,er2),@(0x9abc:16,r3l.b)" +gdb_test "x" "mov.l @\\(0x12345678:32,er2\\),@\\(0x9abc(:16|),r3.w\\)" \ + "mov.l @(0x12345678:32,er2),@(0x9abc:16,r3.w)" +gdb_test "x" "mov.l @\\(0x12345678:32,er2\\),@\\(0x9abc(:16|),er3.l\\)" \ + "mov.l @(0x12345678:32,er2),@(0x9abc:16,er3.l)" +gdb_test "x" "mov.l @\\(0x12345678:32,er2\\),@\\(0x9abcdef0:32,r3l.b\\)" \ + "mov.l @(0x12345678:32,er2),@(0x9abcdef0:32,r3l.b)" +gdb_test "x" "mov.l @\\(0x12345678:32,er2\\),@\\(0x9abcdef0:32,r3.w\\)" \ + "mov.l @(0x12345678:32,er2),@(0x9abcdef0:32,r3.w)" +gdb_test "x" "mov.l @\\(0x12345678:32,er2\\),@\\(0x9abcdef0:32,er3.l\\)" \ + "mov.l @(0x12345678:32,er2),@(0x9abcdef0:32,er3.l)" +gdb_test "x" "mov.l @\\(0x12345678:32,er2\\),@0x9abc(:16|)" \ + "mov.l @(0x12345678:32,er2),@0x9abc:16" +gdb_test "x" "mov.l @\\(0x12345678:32,er2\\),@0x9abcdef0:32" \ + "mov.l @(0x12345678:32,er2),@0x9abcdef0:32" +gdb_test "x" "mov.l @\\(0x1234:16,r3l.b\\),@er1" \ + "mov.l @(0x1234:16,r3l.b),@er1" +gdb_test "x" "mov.l @\\(0x1234:16,r3l.b\\),@\\(0x4:2,er1\\)" \ + "mov.l @(0x1234:16,r3l.b),@(0x4:2,er1)" +gdb_test "x" "mov.l @\\(0x1234:16,r3l.b\\),@er1\\+" \ + "mov.l @(0x1234:16,r3l.b),@er1+" +gdb_test "x" "mov.l @\\(0x1234:16,r3l.b\\),@-er1" \ + "mov.l @(0x1234:16,r3l.b),@-er1" +gdb_test "x" "mov.l @\\(0x1234:16,r3l.b\\),@\\+er1" \ + "mov.l @(0x1234:16,r3l.b),@+er1" +gdb_test "x" "mov.l @\\(0x1234:16,r3l.b\\),@er1-" \ + "mov.l @(0x1234:16,r3l.b),@er1-" +gdb_test "x" "mov.l @\\(0x1234:16,r3l.b\\),@\\(0x9abc(:16|),er1\\)" \ + "mov.l @(0x1234:16,r3l.b),@(0x9abc:16,er1)" +gdb_test "x" "mov.l @\\(0x1234:16,r3l.b\\),@\\(0x9abcdef0:32,er1\\)" \ + "mov.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1)" +gdb_test "x" "mov.l @\\(0x1234:16,r3l.b\\),@\\(0x9abc(:16|),r3l.b\\)" \ + "mov.l @(0x1234:16,r3l.b),@(0x9abc:16,r3l.b)" +gdb_test "x" "mov.l @\\(0x1234:16,r3l.b\\),@\\(0x9abc(:16|),r3.w\\)" \ + "mov.l @(0x1234:16,r3l.b),@(0x9abc:16,r3.w)" +gdb_test "x" "mov.l @\\(0x1234:16,r3l.b\\),@\\(0x9abc(:16|),er3.l\\)" \ + "mov.l @(0x1234:16,r3l.b),@(0x9abc:16,er3.l)" +gdb_test "x" "mov.l @\\(0x1234:16,r3l.b\\),@\\(0x9abcdef0:32,r3l.b\\)" \ + "mov.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,r3l.b)" +gdb_test "x" "mov.l @\\(0x1234:16,r3l.b\\),@\\(0x9abcdef0:32,r3.w\\)" \ + "mov.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,r3.w)" +gdb_test "x" "mov.l @\\(0x1234:16,r3l.b\\),@\\(0x9abcdef0:32,er3.l\\)" \ + "mov.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,er3.l)" +gdb_test "x" "mov.l @\\(0x1234:16,r3l.b\\),@0x9abc(:16|)" \ + "mov.l @(0x1234:16,r3l.b),@0x9abc:16" +gdb_test "x" "mov.l @\\(0x1234:16,r3l.b\\),@0x9abcdef0:32" \ + "mov.l @(0x1234:16,r3l.b),@0x9abcdef0:32" +gdb_test "x" "mov.l @\\(0x1234:16,r3.w\\),@er1" \ + "mov.l @(0x1234:16,r3.w),@er1" +gdb_test "x" "mov.l @\\(0x1234:16,r3.w\\),@\\(0x4:2,er1\\)" \ + "mov.l @(0x1234:16,r3.w),@(0x4:2,er1)" +gdb_test "x" "mov.l @\\(0x1234:16,r3.w\\),@er1\\+" \ + "mov.l @(0x1234:16,r3.w),@er1+" +gdb_test "x" "mov.l @\\(0x1234:16,r3.w\\),@-er1" \ + "mov.l @(0x1234:16,r3.w),@-er1" +gdb_test "x" "mov.l @\\(0x1234:16,r3.w\\),@\\+er1" \ + "mov.l @(0x1234:16,r3.w),@+er1" +gdb_test "x" "mov.l @\\(0x1234:16,r3.w\\),@er1-" \ + "mov.l @(0x1234:16,r3.w),@er1-" +gdb_test "x" "mov.l @\\(0x1234:16,r3.w\\),@\\(0x9abc(:16|),er1\\)" \ + "mov.l @(0x1234:16,r3.w),@(0x9abc:16,er1)" +gdb_test "x" "mov.l @\\(0x1234:16,r3.w\\),@\\(0x9abcdef0:32,er1\\)" \ + "mov.l @(0x1234:16,r3.w),@(0x9abcdef0:32,er1)" +gdb_test "x" "mov.l @\\(0x1234:16,r3.w\\),@\\(0x9abc(:16|),r3l.b\\)" \ + "mov.l @(0x1234:16,r3.w),@(0x9abc:16,r3l.b)" +gdb_test "x" "mov.l @\\(0x1234:16,r3.w\\),@\\(0x9abc(:16|),r3.w\\)" \ + "mov.l @(0x1234:16,r3.w),@(0x9abc:16,r3.w)" +gdb_test "x" "mov.l @\\(0x1234:16,r3.w\\),@\\(0x9abc(:16|),er3.l\\)" \ + "mov.l @(0x1234:16,r3.w),@(0x9abc:16,er3.l)" +gdb_test "x" "mov.l @\\(0x1234:16,r3.w\\),@\\(0x9abcdef0:32,r3l.b\\)" \ + "mov.l @(0x1234:16,r3.w),@(0x9abcdef0:32,r3l.b)" +gdb_test "x" "mov.l @\\(0x1234:16,r3.w\\),@\\(0x9abcdef0:32,r3.w\\)" \ + "mov.l @(0x1234:16,r3.w),@(0x9abcdef0:32,r3.w)" +gdb_test "x" "mov.l @\\(0x1234:16,r3.w\\),@\\(0x9abcdef0:32,er3.l\\)" \ + "mov.l @(0x1234:16,r3.w),@(0x9abcdef0:32,er3.l)" +gdb_test "x" "mov.l @\\(0x1234:16,r3.w\\),@0x9abc(:16|)" \ + "mov.l @(0x1234:16,r3.w),@0x9abc:16" +gdb_test "x" "mov.l @\\(0x1234:16,r3.w\\),@0x9abcdef0:32" \ + "mov.l @(0x1234:16,r3.w),@0x9abcdef0:32" +gdb_test "x" "mov.l @\\(0x1234:16,er3.l\\),@er1" \ + "mov.l @(0x1234:16,er3.l),@er1" +gdb_test "x" "mov.l @\\(0x1234:16,er3.l\\),@\\(0x4:2,er1\\)" \ + "mov.l @(0x1234:16,er3.l),@(0x4:2,er1)" +gdb_test "x" "mov.l @\\(0x1234:16,er3.l\\),@er1\\+" \ + "mov.l @(0x1234:16,er3.l),@er1+" +gdb_test "x" "mov.l @\\(0x1234:16,er3.l\\),@-er1" \ + "mov.l @(0x1234:16,er3.l),@-er1" +gdb_test "x" "mov.l @\\(0x1234:16,er3.l\\),@\\+er1" \ + "mov.l @(0x1234:16,er3.l),@+er1" +gdb_test "x" "mov.l @\\(0x1234:16,er3.l\\),@er1-" \ + "mov.l @(0x1234:16,er3.l),@er1-" +gdb_test "x" "mov.l @\\(0x1234:16,er3.l\\),@\\(0x9abc(:16|),er1\\)" \ + "mov.l @(0x1234:16,er3.l),@(0x9abc16,er1)" +gdb_test "x" "mov.l @\\(0x1234:16,er3.l\\),@\\(0x9abcdef0:32,er1\\)" \ + "mov.l @(0x1234:16,er3.l),@(0x9abcdef0:32,er1)" +gdb_test "x" "mov.l @\\(0x1234:16,er3.l\\),@\\(0x9abc(:16|),r3l.b\\)" \ + "mov.l @(0x1234:16,er3.l),@(0x9abc16,r3l.b)" +gdb_test "x" "mov.l @\\(0x1234:16,er3.l\\),@\\(0x9abc(:16|),r3.w\\)" \ + "mov.l @(0x1234:16,er3.l),@(0x9abc:16,r3.w)" +gdb_test "x" "mov.l @\\(0x1234:16,er3.l\\),@\\(0x9abc(:16|),er3.l\\)" \ + "mov.l @(0x1234:16,er3.l),@(0x9abc:16,er3.l)" +gdb_test "x" "mov.l @\\(0x1234:16,er3.l\\),@\\(0x9abcdef0:32,r3l.b\\)" \ + "mov.l @(0x1234:16,er3.l),@(0x9abcdef0:32,r3l.b)" +gdb_test "x" "mov.l @\\(0x1234:16,er3.l\\),@\\(0x9abcdef0:32,r3.w\\)" \ + "mov.l @(0x1234:16,er3.l),@(0x9abcdef0:32,r3.w)" +gdb_test "x" "mov.l @\\(0x1234:16,er3.l\\),@\\(0x9abcdef0:32,er3.l\\)" \ + "mov.l @(0x1234:16,er3.l),@(0x9abcdef0:32,er3.l)" +gdb_test "x" "mov.l @\\(0x1234:16,er3.l\\),@0x9abc(:16|)" \ + "mov.l @(0x1234:16,er3.l),@0x9abc:16" +gdb_test "x" "mov.l @\\(0x1234:16,er3.l\\),@0x9abcdef0:32" \ + "mov.l @(0x1234:16,er3.l),@0x9abcdef0:32" +gdb_test "x" "mov.l @\\(0x12345678:32,r3l.b\\),@er1" \ + "mov.l @(0x12345678:32,r3l.b),@er1" +gdb_test "x" "mov.l @\\(0x12345678:32,r3l.b\\),@\\(0x4:2,er1\\)" \ + "mov.l @(0x12345678:32,r3l.b),@(0x4:2,er1)" +gdb_test "x" "mov.l @\\(0x12345678:32,r3l.b\\),@er1\\+" \ + "mov.l @(0x12345678:32,r3l.b),@er1+" +gdb_test "x" "mov.l @\\(0x12345678:32,r3l.b\\),@-er1" \ + "mov.l @(0x12345678:32,r3l.b),@-er1" +gdb_test "x" "mov.l @\\(0x12345678:32,r3l.b\\),@\\+er1" \ + "mov.l @(0x12345678:32,r3l.b),@+er1" +gdb_test "x" "mov.l @\\(0x12345678:32,r3l.b\\),@er1-" \ + "mov.l @(0x12345678:32,r3l.b),@er1-" +gdb_test "x" "mov.l @\\(0x12345678:32,r3l.b\\),@\\(0x9abc(:16|),er1\\)" \ + "mov.l @(0x12345678:32,r3l.b),@(0x9abc:16,er1)" +gdb_test "x" "mov.l @\\(0x12345678:32,r3l.b\\),@\\(0x9abcdef0:32,er1\\)" \ + "mov.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1)" +gdb_test "x" "mov.l @\\(0x12345678:32,r3l.b\\),@\\(0x9abc(:16|),r3l.b\\)" \ + "mov.l @(0x12345678:32,r3l.b),@(0x9abc:16,r3l.b)" +gdb_test "x" "mov.l @\\(0x12345678:32,r3l.b\\),@\\(0x9abc(:16|),r3.w\\)" \ + "mov.l @(0x12345678:32,r3l.b),@(0x9abc:16,r3.w)" +gdb_test "x" "mov.l @\\(0x12345678:32,r3l.b\\),@\\(0x9abc(:16|),er3.l\\)" \ + "mov.l @(0x12345678:32,r3l.b),@(0x9abc:16,er3.l)" +gdb_test "x" "mov.l @\\(0x12345678:32,r3l.b\\),@\\(0x9abcdef0:32,r3l.b\\)" \ + "mov.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r3l.b)" +gdb_test "x" "mov.l @\\(0x12345678:32,r3l.b\\),@\\(0x9abcdef0:32,r3.w\\)" \ + "mov.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r3.w)" +gdb_test "x" "mov.l @\\(0x12345678:32,r3l.b\\),@\\(0x9abcdef0:32,er3.l\\)" \ + "mov.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er3.l)" +gdb_test "x" "mov.l @\\(0x12345678:32,r3l.b\\),@0x9abc(:16|)" \ + "mov.l @(0x12345678:32,r3l.b),@0x9abc:16" +gdb_test "x" "mov.l @\\(0x12345678:32,r3l.b\\),@0x9abcdef0:32" \ + "mov.l @(0x12345678:32,r3l.b),@0x9abcdef0:32" +gdb_test "x" "mov.l @\\(0x12345678:32,r3.w\\),@er1" \ + "mov.l @(0x12345678:32,r3.w),@er1" +gdb_test "x" "mov.l @\\(0x12345678:32,r3.w\\),@\\(0x4:2,er1\\)" \ + "mov.l @(0x12345678:32,r3.w),@(0x4:2,er1)" +gdb_test "x" "mov.l @\\(0x12345678:32,r3.w\\),@er1\\+" \ + "mov.l @(0x12345678:32,r3.w),@er1+" +gdb_test "x" "mov.l @\\(0x12345678:32,r3.w\\),@-er1" \ + "mov.l @(0x12345678:32,r3.w),@-er1" +gdb_test "x" "mov.l @\\(0x12345678:32,r3.w\\),@\\+er1" \ + "mov.l @(0x12345678:32,r3.w),@+er1" +gdb_test "x" "mov.l @\\(0x12345678:32,r3.w\\),@er1-" \ + "mov.l @(0x12345678:32,r3.w),@er1-" +gdb_test "x" "mov.l @\\(0x12345678:32,r3.w\\),@\\(0x9abc(:16|),er1\\)" \ + "mov.l @(0x12345678:32,r3.w),@(0x9abc:16,er1)" +gdb_test "x" "mov.l @\\(0x12345678:32,r3.w\\),@\\(0x9abcdef0:32,er1\\)" \ + "mov.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1)" +gdb_test "x" "mov.l @\\(0x12345678:32,r3.w\\),@\\(0x9abc(:16|),r3l.b\\)" \ + "mov.l @(0x12345678:32,r3.w),@(0x9abc:16,r3l.b)" +gdb_test "x" "mov.l @\\(0x12345678:32,r3.w\\),@\\(0x9abc(:16|),r3.w\\)" \ + "mov.l @(0x12345678:32,r3.w),@(0x9abc:16,r3.w)" +gdb_test "x" "mov.l @\\(0x12345678:32,r3.w\\),@\\(0x9abc(:16|),er3.l\\)" \ + "mov.l @(0x12345678:32,r3.w),@(0x9abc:16,er3.l)" +gdb_test "x" "mov.l @\\(0x12345678:32,r3.w\\),@\\(0x9abcdef0:32,r3l.b\\)" \ + "mov.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,r3l.b)" +gdb_test "x" "mov.l @\\(0x12345678:32,r3.w\\),@\\(0x9abcdef0:32,r3.w\\)" \ + "mov.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,r3.w)" +gdb_test "x" "mov.l @\\(0x12345678:32,r3.w\\),@\\(0x9abcdef0:32,er3.l\\)" \ + "mov.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,er3.l)" +gdb_test "x" "mov.l @\\(0x12345678:32,r3.w\\),@0x9abc(:16|)" \ + "mov.l @(0x12345678:32,r3.w),@0x9abc:16" +gdb_test "x" "mov.l @\\(0x12345678:32,r3.w\\),@0x9abcdef0:32" \ + "mov.l @(0x12345678:32,r3.w),@0x9abcdef0:32" +gdb_test "x" "mov.l @\\(0x12345678:32,er3.l\\),@er1" \ + "mov.l @(0x12345678:32,er3.l),@er1" +gdb_test "x" "mov.l @\\(0x12345678:32,er3.l\\),@\\(0x4:2,er1\\)" \ + "mov.l @(0x12345678:32,er3.l),@(0x4:2,er1)" +gdb_test "x" "mov.l @\\(0x12345678:32,er3.l\\),@er1\\+" \ + "mov.l @(0x12345678:32,er3.l),@er1+" +gdb_test "x" "mov.l @\\(0x12345678:32,er3.l\\),@-er1" \ + "mov.l @(0x12345678:32,er3.l),@-er1" +gdb_test "x" "mov.l @\\(0x12345678:32,er3.l\\),@\\+er1" \ + "mov.l @(0x12345678:32,er3.l),@+er1" +gdb_test "x" "mov.l @\\(0x12345678:32,er3.l\\),@er1-" \ + "mov.l @(0x12345678:32,er3.l),@er1-" +gdb_test "x" "mov.l @\\(0x12345678:32,er3.l\\),@\\(0x9abc(:16|),er1\\)" \ + "mov.l @(0x12345678:32,er3.l),@(0x9abc:16,er1)" +gdb_test "x" "mov.l @\\(0x12345678:32,er3.l\\),@\\(0x9abcdef0:32,er1\\)" \ + "mov.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1)" +gdb_test "x" "mov.l @\\(0x12345678:32,er3.l\\),@\\(0x9abc(:16|),r3l.b\\)" \ + "mov.l @(0x12345678:32,er3.l),@(0x9abc:16,r3l.b)" +gdb_test "x" "mov.l @\\(0x12345678:32,er3.l\\),@\\(0x9abc(:16|),r3.w\\)" \ + "mov.l @(0x12345678:32,er3.l),@(0x9abc:16,r3.w)" +gdb_test "x" "mov.l @\\(0x12345678:32,er3.l\\),@\\(0x9abc(:16|),er3.l\\)" \ + "mov.l @(0x12345678:32,er3.l),@(0x9abc:16,er3.l)" +gdb_test "x" "mov.l @\\(0x12345678:32,er3.l\\),@\\(0x9abcdef0:32,r3l.b\\)" \ + "mov.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,r3l.b)" +gdb_test "x" "mov.l @\\(0x12345678:32,er3.l\\),@\\(0x9abcdef0:32,r3.w\\)" \ + "mov.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,r3.w)" +gdb_test "x" "mov.l\t@\\(0x12345678:32,er3.l\\),@\\(0x9abcdef0:32,er3.l\\)" \ + "mov.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,er3.l)" +gdb_test "x" "mov.l @\\(0x12345678:32,er3.l\\),@0x9abc(:16|)" \ + "mov.l @(0x12345678:32,er3.l),@0x9abc:16" +gdb_test "x" "mov.l @\\(0x12345678:32,er3.l\\),@0x9abcdef0:32" \ + "mov.l @(0x12345678:32,er3.l),@0x9abcdef0:32" +gdb_test "x" "mov.l @0x1234:16,@er1" \ + "mov.l @0x1234:16,@er1" +gdb_test "x" "mov.l @0x1234:16,@\\(0x4:2,er1\\)" \ + "mov.l @0x1234:16,@(0x4:2,er1)" +gdb_test "x" "mov.l @0x1234:16,@er1\\+" \ + "mov.l @0x1234:16,@er1+" +gdb_test "x" "mov.l @0x1234:16,@-er1" \ + "mov.l @0x1234:16,@-er1" +gdb_test "x" "mov.l @0x1234:16,@\\+er1" \ + "mov.l @0x1234:16,@+er1" +gdb_test "x" "mov.l @0x1234:16,@er1-" \ + "mov.l @0x1234:16,@er1-" +gdb_test "x" "mov.l @0x1234:16,@\\(0x9abc(:16|),er1\\)" \ + "mov.l @0x1234:16,@(0x9abc:16,er1)" +gdb_test "x" "mov.l @0x1234:16,@\\(0x9abcdef0:32,er1\\)" \ + "mov.l @0x1234:16,@(0x9abcdef0:32,er1)" +gdb_test "x" "mov.l @0x1234:16,@\\(0x9abc(:16|),r3l.b\\)" \ + "mov.l @0x1234:16,@(0x9abc:16,r3l.b)" +gdb_test "x" "mov.l @0x1234:16,@\\(0x9abc(:16|),r3.w\\)" \ + "mov.l @0x1234:16,@(0x9abc:16,r3.w)" +gdb_test "x" "mov.l @0x1234:16,@\\(0x9abc(:16|),er3.l\\)" \ + "mov.l @0x1234:16,@(0x9abc:16,er3.l)" +gdb_test "x" "mov.l @0x1234:16,@\\(0x9abcdef0:32,r3l.b\\)" \ + "mov.l @0x1234:16,@(0x9abcdef0:32,r3l.b)" +gdb_test "x" "mov.l @0x1234:16,@\\(0x9abcdef0:32,r3.w\\)" \ + "mov.l @0x1234:16,@(0x9abcdef0:32,r3.w)" +gdb_test "x" "mov.l @0x1234:16,@\\(0x9abcdef0:32,er3.l\\)" \ + "mov.l @0x1234:16,@(0x9abcdef0:32,er3.l)" +gdb_test "x" "mov.l @0x1234:16,@0x9abc(:16|)" \ + "mov.l @0x1234:16,@0x9abc:16" +gdb_test "x" "mov.l @0x1234:16,@0x9abcdef0:32" \ + "mov.l @0x1234:16,@0x9abcdef0:32" +gdb_test "x" "mov.l @0x12345678:32,@er1" \ + "mov.l @0x12345678:32,@er1" +gdb_test "x" "mov.l @0x12345678:32,@\\(0x4:2,er1\\)" \ + "mov.l @0x12345678:32,@(0x4:2,er1)" +gdb_test "x" "mov.l @0x12345678:32,@er1\\+" \ + "mov.l @0x12345678:32,@er1+" +gdb_test "x" "mov.l @0x12345678:32,@-er1" \ + "mov.l @0x12345678:32,@-er1" +gdb_test "x" "mov.l @0x12345678:32,@\\+er1" \ + "mov.l @0x12345678:32,@+er1" +gdb_test "x" "mov.l @0x12345678:32,@er1-" \ + "mov.l @0x12345678:32,@er1-" +gdb_test "x" "mov.l @0x12345678:32,@\\(0x9abc(:16|),er1\\)" \ + "mov.l @0x12345678:32,@(0x9abc:16,er1)" +gdb_test "x" "mov.l @0x12345678:32,@\\(0x9abcdef0:32,er1\\)" \ + "mov.l @0x12345678:32,@(0x9abcdef0:32,er1)" +gdb_test "x" "mov.l @0x12345678:32,@\\(0x9abc(:16|),r3l.b\\)" \ + "mov.l @0x12345678:32,@(0x9abc:16,r3l.b)" +gdb_test "x" "mov.l @0x12345678:32,@\\(0x9abc(:16|),r3.w\\)" \ + "mov.l @0x12345678:32,@(0x9abc:16,r3.w)" +gdb_test "x" "mov.l @0x12345678:32,@\\(0x9abc(:16|),er3.l\\)" \ + "mov.l @0x12345678:32,@(0x9abc:16,er3.l)" +gdb_test "x" "mov.l @0x12345678:32,@\\(0x9abcdef0:32,r3l.b\\)" \ + "mov.l @0x12345678:32,@(0x9abcdef0:32,r3l.b)" +gdb_test "x" "mov.l @0x12345678:32,@\\(0x9abcdef0:32,r3.w\\)" \ + "mov.l @0x12345678:32,@(0x9abcdef0:32,r3.w)" +gdb_test "x" "mov.l @0x12345678:32,@\\(0x9abcdef0:32,er3.l\\)" \ + "mov.l @0x12345678:32,@(0x9abcdef0:32,er3.l)" +gdb_test "x" "mov.l @0x12345678:32,@0x9abc(:16|)" \ + "mov.l @0x12345678:32,@0x9abc:16" +gdb_test "x" "mov.l @0x12345678:32,@0x9abcdef0:32" \ + "mov.l @0x12345678:32,@0x9abcdef0:32" +gdb_test "x" "movtpe(.b|) r2h,@0x1234:16" \ + "movtpe.b r2h,@0x1234:16" +gdb_test "x" "movfpe(.b|) @0x1234:16,r1h" \ + "movfpe.b @0x1234:16,r1h" +gdb_test "x" "ldm(.l|) @sp\\+,(\\(|)er0-er1(\\)|)" \ + "ldm.l @sp+,er0-er1" +gdb_test "x" "ldm(.l|) @sp\\+,(\\(|)er1-er2(\\)|)" \ + "ldm.l @sp+,er1-er2" +gdb_test "x" "ldm(.l|) @sp\\+,(\\(|)er2-er3(\\)|)" \ + "ldm.l @sp+,er2-er3" +gdb_test "x" "ldm(.l|) @sp\\+,(\\(|)er3-er4(\\)|)" \ + "ldm.l @sp+,er3-er4" +gdb_test "x" "ldm(.l|) @sp\\+,(\\(|)er4-er5(\\)|)" \ + "ldm.l @sp+,er4-er5" +gdb_test "x" "ldm(.l|) @sp\\+,(\\(|)er5-er6(\\)|)" \ + "ldm.l @sp+,er5-er6" +gdb_test "x" "ldm(.l|) @sp\\+,(\\(|)er6-er7(\\)|)" \ + "ldm.l @sp+,er6-er7" +gdb_test "x" "ldm(.l|) @sp\\+,(\\(|)er0-er2(\\)|)" \ + "ldm.l @sp+,er0-er2" +gdb_test "x" "ldm(.l|) @sp\\+,(\\(|)er1-er3(\\)|)" \ + "ldm.l @sp+,er1-er3" +gdb_test "x" "ldm(.l|) @sp\\+,(\\(|)er2-er4(\\)|)" \ + "ldm.l @sp+,er2-er4" +gdb_test "x" "ldm(.l|) @sp\\+,(\\(|)er3-er5(\\)|)" \ + "ldm.l @sp+,er3-er5" +gdb_test "x" "ldm(.l|) @sp\\+,(\\(|)er4-er6(\\)|)" \ + "ldm.l @sp+,er4-er6" +gdb_test "x" "ldm(.l|) @sp\\+,(\\(|)er5-er7(\\)|)" \ + "ldm.l @sp+,er5-er7" +gdb_test "x" "ldm(.l|) @sp\\+,(\\(|)er0-er3(\\)|)" \ + "ldm.l @sp+,er0-er3" +gdb_test "x" "ldm(.l|) @sp\\+,(\\(|)er1-er4(\\)|)" \ + "ldm.l @sp+,er1-er4" +gdb_test "x" "ldm(.l|) @sp\\+,(\\(|)er2-er5(\\)|)" \ + "ldm.l @sp+,er2-er5" +gdb_test "x" "ldm(.l|) @sp\\+,(\\(|)er3-er6(\\)|)" \ + "ldm.l @sp+,er3-er6" +gdb_test "x" "ldm(.l|) @sp\\+,(\\(|)er4-er7(\\)|)" \ + "ldm.l @sp+,er4-er7" +gdb_test "x" "stm(.l) (\\(|)er0-er1(\\)|),@-sp" \ + "stm.l er0-er1,@-sp" +gdb_test "x" "stm(.l) (\\(|)er1-er2(\\)|),@-sp" \ + "stm.l er1-er2,@-sp" +gdb_test "x" "stm(.l) (\\(|)er2-er3(\\)|),@-sp" \ + "stm.l er2-er3,@-sp" +gdb_test "x" "stm(.l) (\\(|)er3-er4(\\)|),@-sp" \ + "stm.l er3-er4,@-sp" +gdb_test "x" "stm(.l) (\\(|)er4-er5(\\)|),@-sp" \ + "stm.l er4-er5,@-sp" +gdb_test "x" "stm(.l) (\\(|)er5-er6(\\)|),@-sp" \ + "stm.l er5-er6,@-sp" +gdb_test "x" "stm(.l) (\\(|)er6-er7(\\)|),@-sp" \ + "stm.l er6-er7,@-sp" +gdb_test "x" "stm(.l) (\\(|)er0-er2(\\)|),@-sp" \ + "stm.l er0-er2,@-sp" +gdb_test "x" "stm(.l) (\\(|)er1-er3(\\)|),@-sp" \ + "stm.l er1-er3,@-sp" +gdb_test "x" "stm(.l) (\\(|)er2-er4(\\)|),@-sp" \ + "stm.l er2-er4,@-sp" +gdb_test "x" "stm(.l) (\\(|)er3-er5(\\)|),@-sp" \ + "stm.l er3-er5,@-sp" +gdb_test "x" "stm(.l) (\\(|)er4-er6(\\)|),@-sp" \ + "stm.l er4-er6,@-sp" +gdb_test "x" "stm(.l) (\\(|)er5-er7(\\)|),@-sp" \ + "stm.l er5-er7,@-sp" +gdb_test "x" "stm(.l) (\\(|)er0-er3(\\)|),@-sp" \ + "stm.l er0-er3,@-sp" +gdb_test "x" "stm(.l) (\\(|)er1-er4(\\)|),@-sp" \ + "stm.l er1-er4,@-sp" +gdb_test "x" "stm(.l) (\\(|)er2-er5(\\)|),@-sp" \ + "stm.l er2-er5,@-sp" +gdb_test "x" "stm(.l) (\\(|)er3-er6(\\)|),@-sp" \ + "stm.l er3-er6,@-sp" +gdb_test "x" "stm(.l) (\\(|)er4-er7(\\)|),@-sp" \ + "stm.l er4-er7,@-sp" +gdb_test "x" "eepmov.b(\t|)" \ + "eepmov.b" +gdb_test "x" "eepmov.w(\t|)" \ + "eepmov.w" +gdb_test "x" "movmd.b(\t|)" \ + "movmd.b" +gdb_test "x" "movmd.w(\t|)" \ + "movmd.w" +gdb_test "x" "movmd.l(\t|)" \ + "movmd.l" +gdb_test "x" "movsd.b\t\\.\\+4 \\($hex\\)" \ + "movsd.b .+4" diff --git a/gdb/testsuite/gdb.disasm/t01_mov.s b/gdb/testsuite/gdb.disasm/t01_mov.s new file mode 100644 index 0000000..fab7fb9 --- /dev/null +++ b/gdb/testsuite/gdb.disasm/t01_mov.s @@ -0,0 +1,1107 @@ +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;mov +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + .h8300sx + .text + .global _start +_start: + mov.b #0x12:8,r3h ;f312 + mov.b #0x12:8,@er3 ;017d0312 + mov.b #0x12:8,@(0x1:2,er3) ;017d1312 + mov.b #0x12:8,@-er3 ;017db312 + mov.b #0x12:8,@er3+ ;017d8312 + mov.b #0x12:8,@er3- ;017da312 + mov.b #0x12:8,@+er3 ;017d9312 + mov.b #0x12:8,@(0x1234:16,er3) ;017dc3121234 + mov.b #0x12:8,@(0x12345678:32,er3) ;017dcb1212345678 + mov.b #0x12:8,@(0x1234:16,r3l.b) ;017dd3121234 + mov.b #0x12:8,@(0x1234:16,r3.w) ;017de3121234 + mov.b #0x12:8,@(0x1234:16,er3.l) ;017df3121234 + mov.b #0x12:8,@(0x12345678:32,r3l.b) ;017ddb1212345678 + mov.b #0x12:8,@(0x12345678:32,r3.w) ;017deb1212345678 + mov.b #0x12:8,@(0x12345678:32,er3.l) ;017dfb1212345678 + mov.b #0x12:8,@0x1234:16 ;017d40121234 + mov.b #0x12:8,@0x12345678:32 ;017d481212345678 + + mov.b #0x1:4,@0x1234:16 ;6ad11234 + mov.b #0x1:4,@0x12345678:32 ;6af112345678 + + mov.b r3h,r1h ;0c31 + + mov.b r3h,@er1 ;6893 + mov.b r3h,@(0x1:2,er1) ;01716893 + mov.b r3h,@-er1 ;6c93 + mov.b r3h,@er1+ ;01736c93 + mov.b r3h,@er1- ;01716c93 + mov.b r3h,@+er1 ;01726c93 + mov.b r3h,@(0x1234:16,er1) ;6e931234 + mov.b r3h,@(0x12345678:32,er1) ;78106aa312345678 + mov.b r3h,@(0x1234:16,r1l.b) ;01716e931234 + mov.b r3h,@(0x1234:16,r1.w) ;01726e931234 + mov.b r3h,@(0x1234:16,er1.l) ;01736e931234 + mov.b r3h,@(0x12345678:32,r1l.b) ;78116aa312345678 + mov.b r3h,@(0x12345678:32,r1.w) ;78126aa312345678 + mov.b r3h,@(0x12345678:32,er1.l) ;78136aa312345678 + mov.b r3h,@0xffffff12:8 ;3312 + mov.b r3h,@0x1234:16 ;6a831234 + mov.b r3h,@0x12345678:32 ;6aa312345678 + + mov.b @er3,r1h ;6831 + mov.b @(0x1:2,er3),r1h ;01716831 + mov.b @er3+,r1h ;6c31 + mov.b @-er3,r1h ;01736c31 + mov.b @+er3,r1h ;01716c31 + mov.b @er3-,r1h ;01726c31 + mov.b @(0x1234:16,er3),r1h ;6e311234 + mov.b @(0x12345678:32,er3),r1h ;78306a2112345678 + mov.b @(0x1234:16,r3l.b),r1h ;01716e311234 + mov.b @(0x1234:16,r3.w),r1h ;01726e311234 + mov.b @(0x1234:16,er3.l),r1h ;01736e311234 + mov.b @(0x12345678:32,r3l.b),r1h ;78316a2112345678 + mov.b @(0x12345678:32,r3.w),r1h ;78326a2112345678 + mov.b @(0x12345678:32,er3.l),r1h ;78336a2112345678 + mov.b @0xffffff12:8,r3h ;2312 + mov.b @0x1234:16,r3h ;6a031234 + mov.b @0x12345678:32,r3h ;6a2312345678 + + mov.b @er3,@er1 ;01780301 + mov.b @er3,@(0x1:2,er1) ;01780311 + mov.b @er3,@er1+ ;01780381 + mov.b @er3,@-er1 ;017803b1 + mov.b @er3,@+er1 ;01780391 + mov.b @er3,@er1- ;017803a1 + mov.b @er3,@(0x1234:16,er1) ;017803c11234 + mov.b @er3,@(0x12345678:32,er1) ;017803c912345678 + mov.b @er3,@(0x1234:16,r1l.b) ;017803d11234 + mov.b @er3,@(0x1234:16,r1.w) ;017803e11234 + mov.b @er3,@(0x1234:16,er1.l) ;017803f11234 + mov.b @er3,@(0x12345678:32,r1l.b) ;017803d912345678 + mov.b @er3,@(0x12345678:32,r1.w) ;017803e912345678 + mov.b @er3,@(0x12345678:32,er1.l) ;017803f912345678 + mov.b @er3,@0x1234:16 ;017803401234 + mov.b @er3,@0x12345678:32 ;0178034812345678 + + mov.b @(0x1:2,er3),@er1 ;01781301 + mov.b @(0x1:2,er3),@(0x1:2,er1) ;01781311 + mov.b @(0x1:2,er3),@er1+ ;01781381 + mov.b @(0x1:2,er3),@-er1 ;017813b1 + mov.b @(0x1:2,er3),@+er1 ;01781391 + mov.b @(0x1:2,er3),@er1- ;017813a1 + mov.b @(0x1:2,er3),@(0x1234:16,er1) ;017813c11234 + mov.b @(0x1:2,er3),@(0x12345678:32,er1) ;017813c912345678 + mov.b @(0x1:2,er3),@(0x1234:16,r1l.b) ;017813d11234 + mov.b @(0x1:2,er3),@(0x1234:16,r1.w) ;017813e11234 + mov.b @(0x1:2,er3),@(0x1234:16,er1.l) ;017813f11234 + mov.b @(0x1:2,er3),@(0x12345678:32,r1l.b) ;017813d912345678 + mov.b @(0x1:2,er3),@(0x12345678:32,r1.w) ;017813e912345678 + mov.b @(0x1:2,er3),@(0x12345678:32,er1.l) ;017813f912345678 + mov.b @(0x1:2,er3),@0x1234:16 ;017813401234 + mov.b @(0x1:2,er3),@0x12345678:32 ;0178134812345678 + + mov.b @-er3,@er1 ;0178b301 + mov.b @-er3,@(0x1:2,er1) ;0178b311 + mov.b @-er3,@er1+ ;0178b381 + mov.b @-er3,@-er1 ;0178b3b1 + mov.b @-er3,@+er1 ;0178b391 + mov.b @-er3,@er1- ;0178b3a1 + mov.b @-er3,@(0x1234:16,er1) ;0178b3c11234 + mov.b @-er3,@(0x12345678:32,er1) ;0178b3c912345678 + mov.b @-er3,@(0x1234:16,r1l.b) ;0178b3d11234 + mov.b @-er3,@(0x1234:16,r1.w) ;0178b3e11234 + mov.b @-er3,@(0x1234:16,er1.l) ;0178b3f11234 + mov.b @-er3,@(0x12345678:32,r1l.b) ;0178b3d912345678 + mov.b @-er3,@(0x12345678:32,r1.w) ;0178b3e912345678 + mov.b @-er3,@(0x12345678:32,er1.l) ;0178b3f912345678 + mov.b @-er3,@0x1234:16 ;0178b3401234 + mov.b @-er3,@0x12345678:32 ;0178b34812345678 + + mov.b @er3+,@er1 ;01788301 + mov.b @er3+,@(0x1:2,er1) ;01788311 + mov.b @er3+,@er1+ ;01788381 + mov.b @er3+,@-er1 ;017883b1 + mov.b @er3+,@+er1 ;01788391 + mov.b @er3+,@er1- ;017883a1 + mov.b @er3+,@(0x1234:16,er1) ;017883c11234 + mov.b @er3+,@(0x12345678:32,er1) ;017883c912345678 + mov.b @er3+,@(0x1234:16,r1l.b) ;017883d11234 + mov.b @er3+,@(0x1234:16,r1.w) ;017883e11234 + mov.b @er3+,@(0x1234:16,er1.l) ;017883f11234 + mov.b @er3+,@(0x12345678:32,r1l.b) ;017883d912345678 + mov.b @er3+,@(0x12345678:32,r1.w) ;017883e912345678 + mov.b @er3+,@(0x12345678:32,er1.l) ;017883f912345678 + mov.b @er3+,@0x1234:16 ;017883401234 + mov.b @er3+,@0x12345678:32 ;0178834812345678 + + mov.b @er3-,@er1 ;0178a301 + mov.b @er3-,@(0x1:2,er1) ;0178a311 + mov.b @er3-,@er1+ ;0178a381 + mov.b @er3-,@-er1 ;0178a3b1 + mov.b @er3-,@+er1 ;0178a391 + mov.b @er3-,@er1- ;0178a3a1 + mov.b @er3-,@(0x1234:16,er1) ;0178a3c11234 + mov.b @er3-,@(0x12345678:32,er1) ;0178a3c912345678 + mov.b @er3-,@(0x1234:16,r1l.b) ;0178a3d11234 + mov.b @er3-,@(0x1234:16,r1.w) ;0178a3e11234 + mov.b @er3-,@(0x1234:16,er1.l) ;0178a3f11234 + mov.b @er3-,@(0x12345678:32,r1l.b) ;0178a3d912345678 + mov.b @er3-,@(0x12345678:32,r1.w) ;0178a3e912345678 + mov.b @er3-,@(0x12345678:32,er1.l) ;0178a3f912345678 + mov.b @er3-,@0x1234:16 ;0178a3401234 + mov.b @er3-,@0x12345678:32 ;0178a34812345678 + + mov.b @+er3,@er1 ;01789301 + mov.b @+er3,@(0x1:2,er1) ;01789311 + mov.b @+er3,@er1+ ;01789381 + mov.b @+er3,@-er1 ;017893b1 + mov.b @+er3,@+er1 ;01789391 + mov.b @+er3,@er1- ;017893a1 + mov.b @+er3,@(0x1234:16,er1) ;017893c11234 + mov.b @+er3,@(0x12345678:32,er1) ;017893c912345678 + mov.b @+er3,@(0x1234:16,r1l.b) ;017893d11234 + mov.b @+er3,@(0x1234:16,r1.w) ;017893e11234 + mov.b @+er3,@(0x1234:16,er1.l) ;017893f11234 + mov.b @+er3,@(0x12345678:32,r1l.b) ;017893d912345678 + mov.b @+er3,@(0x12345678:32,r1.w) ;017893e912345678 + mov.b @+er3,@(0x12345678:32,er1.l) ;017893f912345678 + mov.b @+er3,@0x1234:16 ;017893401234 + mov.b @+er3,@0x12345678:32 ;0178934812345678 + + mov.b @(0x1234:16,er3),@er1 ;0178c3011234 + mov.b @(0x1234:16,er3),@(0x1:2,er1) ;0178c3111234 + mov.b @(0x1234:16,er3),@er1+ ;0178c3811234 + mov.b @(0x1234:16,er3),@-er1 ;0178c3b11234 + mov.b @(0x1234:16,er3),@+er1 ;0178c3911234 + mov.b @(0x1234:16,er3),@er1- ;0178c3a11234 + mov.b @(0x1234:16,er3),@(0xffff9abc:16,er1) ;0178c3c112349abc + mov.b @(0x1234:16,er3),@(0x9abcdef0:32,er1) ;0178c3c912349abcdef0 + mov.b @(0x1234:16,er3),@(0xffff9abc:16,r1l.b) ;0178c3d112349abc + mov.b @(0x1234:16,er3),@(0xffff9abc:16,r1.w) ;0178c3e112349abc + mov.b @(0x1234:16,er3),@(0xffff9abc:16,er1.l) ;0178c3f112349abc + mov.b @(0x1234:16,er3),@(0x9abcdef0:32,r1l.b) ;0178c3d912349abcdef0 + mov.b @(0x1234:16,er3),@(0x9abcdef0:32,r1.w) ;0178c3e912349abcdef0 + mov.b @(0x1234:16,er3),@(0x9abcdef0:32,er1.l) ;0178c3f912349abcdef0 + mov.b @(0x1234:16,er3),@0xffff9abc:16 ;0178c34012349abc + mov.b @(0x1234:16,er3),@0x9abcdef0:32 ;0178c34812349abcdef0 + + mov.b @(0x12345678:32,er3),@er1 ;0178cb0112345678 + mov.b @(0x12345678:32,er3),@(0x1:2,er1) ;0178cb1112345678 + mov.b @(0x12345678:32,er3),@er1+ ;0178cb8112345678 + mov.b @(0x12345678:32,er3),@-er1 ;0178cbb112345678 + mov.b @(0x12345678:32,er3),@+er1 ;0178cb9112345678 + mov.b @(0x12345678:32,er3),@er1- ;0178cba112345678 + mov.b @(0x12345678:32,er3),@(0xffff9abc:16,er1) ;0178cbc1123456789abc + mov.b @(0x12345678:32,er3),@(0x9abcdef0:32,er1) ;0178cbc9123456789abcdef0 + mov.b @(0x12345678:32,er3),@(0xffff9abc:16,r1l.b) ;0178cbd1123456789abc + mov.b @(0x12345678:32,er3),@(0xffff9abc:16,r1.w) ;0178cbe1123456789abc + mov.b @(0x12345678:32,er3),@(0xffff9abc:16,er1.l) ;0178cbf1123456789abc + mov.b @(0x12345678:32,er3),@(0x9abcdef0:32,r1l.b) ;0178cbd9123456789abcdef0 + mov.b @(0x12345678:32,er3),@(0x9abcdef0:32,r1.w) ;0178cbe9123456789abcdef0 + mov.b @(0x12345678:32,er3),@(0x9abcdef0:32,er1.l) ;0178cbf9123456789abcdef0 + mov.b @(0x12345678:32,er3),@0xffff9abc:16 ;0178cb40123456789abc + mov.b @(0x12345678:32,er3),@0x9abcdef0:32 ;0178cb48123456789abcdef0 + + mov.b @(0x1234:16,r3l.b),@er1 ;0178d3011234 + mov.b @(0x1234:16,r3l.b),@(0x1:2,er1) ;0178d3111234 + mov.b @(0x1234:16,r3l.b),@er1+ ;0178d3811234 + mov.b @(0x1234:16,r3l.b),@-er1 ;0178d3b11234 + mov.b @(0x1234:16,r3l.b),@+er1 ;0178d3911234 + mov.b @(0x1234:16,r3l.b),@er1- ;0178d3a11234 + mov.b @(0x1234:16,r3l.b),@(0xffff9abc:16,r1l.b) ;0178d3d112349abc + mov.b @(0x1234:16,r3l.b),@(0xffff9abc:16,r1.w) ;0178d3e112349abc + mov.b @(0x1234:16,r3l.b),@(0xffff9abc:16,er1.l) ;0178d3f112349abc + mov.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,r1l.b) ;0178d3d912349abcdef0 + mov.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,r1.w) ;0178d3e912349abcdef0 + mov.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1.l) ;0178d3f912349abcdef0 + mov.b @(0x1234:16,r3l.b),@0xffff9abc:16 ;0178d34012349abc + mov.b @(0x1234:16,r3l.b),@0x9abcdef0:32 ;0178d34812349abcdef0 + + mov.b @(0x1234:16,r3.w),@er1 ;0178e3011234 + mov.b @(0x1234:16,r3.w),@(0x1:2,er1) ;0178e3111234 + mov.b @(0x1234:16,r3.w),@er1+ ;0178e3811234 + mov.b @(0x1234:16,r3.w),@-er1 ;0178e3b11234 + mov.b @(0x1234:16,r3.w),@+er1 ;0178e3911234 + mov.b @(0x1234:16,r3.w),@er1- ;0178e3a11234 + mov.b @(0x1234:16,r3.w),@(0xffff9abc:16,er1) ;0178e3c112349abc + mov.b @(0x1234:16,r3.w),@(0x9abcdef0:32,er1) ;0178e3c912349abcdef0 + mov.b @(0x1234:16,r3.w),@(0xffff9abc:16,r3l.b) ;0178e3d312349abc + mov.b @(0x1234:16,r3.w),@(0xffff9abc:16,r3.w) ;0178e3e312349abc + mov.b @(0x1234:16,r3.w),@(0xffff9abc:16,er3.l) ;0178e3f312349abc + mov.b @(0x1234:16,r3.w),@(0x9abcdef0:32,r3l.b) ;0178e3db12349abcdef0 + mov.b @(0x1234:16,r3.w),@(0x9abcdef0:32,r3.w) ;0178e3eb12349abcdef0 + mov.b @(0x1234:16,r3.w),@(0x9abcdef0:32,er3.l) ;0178e3fb12349abcdef0 + mov.b @(0x1234:16,r3.w),@0xffff9abc:16 ;0178e34012349abc + mov.b @(0x1234:16,r3.w),@0x9abcdef0:32 ;0178e34812349abcdef0 + + mov.b @(0x1234:16,er3.l),@er1 ;0178f3011234 + mov.b @(0x1234:16,er3.l),@(0x1:2,er1) ;0178f3111234 + mov.b @(0x1234:16,er3.l),@er1+ ;0178f3811234 + mov.b @(0x1234:16,er3.l),@-er1 ;0178f3b11234 + mov.b @(0x1234:16,er3.l),@+er1 ;0178f3911234 + mov.b @(0x1234:16,er3.l),@er1- ;0178f3a11234 + mov.b @(0x1234:16,er3.l),@(0xffff9abc:16,er1) ;0178f3c112349abc + mov.b @(0x1234:16,er3.l),@(0x9abcdef0:32,er1) ;0178f3c912349abcdef0 + mov.b @(0x1234:16,er3.l),@(0xffff9abc:16,r3l.b) ;0178f3d312349abc + mov.b @(0x1234:16,er3.l),@(0xffff9abc:16,r3.w) ;0178f3e312349abc + mov.b @(0x1234:16,er3.l),@(0xffff9abc:16,er3.l) ;0178f3f312349abc + mov.b @(0x1234:16,er3.l),@(0x9abcdef0:32,r3l.b) ;0178f3db12349abcdef0 + mov.b @(0x1234:16,er3.l),@(0x9abcdef0:32,r3.w) ;0178f3eb12349abcdef0 + mov.b @(0x1234:16,er3.l),@(0x9abcdef0:32,er3.l) ;0178f3fb12349abcdef0 + mov.b @(0x1234:16,er3.l),@0xffff9abc:16 ;0178f34012349abc + mov.b @(0x1234:16,er3.l),@0x9abcdef0:32 ;0178f34812349abcdef0 + + mov.b @(0x12345678:32,r3l.b),@er1 ;0178db0112345678 + mov.b @(0x12345678:32,r3l.b),@(0x1:2,er1) ;0178db1112345678 + mov.b @(0x12345678:32,r3l.b),@er1+ ;0178db8112345678 + mov.b @(0x12345678:32,r3l.b),@-er1 ;0178dbb112345678 + mov.b @(0x12345678:32,r3l.b),@+er1 ;0178db9112345678 + mov.b @(0x12345678:32,r3l.b),@er1- ;0178dba112345678 + mov.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,er1) ;0178dbc1123456789abc + mov.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1) ;0178dbc9123456789abcdef0 + mov.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,r3l.b) ;0178dbd3123456789abc + mov.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,r3.w) ;0178dbe3123456789abc + mov.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,er3.l) ;0178dbf3123456789abc + mov.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r3l.b) ;0178dbdb123456789abcdef0 + mov.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r3.w) ;0178dbeb123456789abcdef0 + mov.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er3.l) ;0178dbfb123456789abcdef0 + mov.b @(0x12345678:32,r3l.b),@0xffff9abc:16 ;0178db40123456789abc + mov.b @(0x12345678:32,r3l.b),@0x9abcdef0:32 ;0178db48123456789abcdef0 + + mov.b @(0x12345678:32,r3.w),@er1 ;0178eb0112345678 + mov.b @(0x12345678:32,r3.w),@(0x1:2,er1) ;0178eb1112345678 + mov.b @(0x12345678:32,r3.w),@er1+ ;0178eb8112345678 + mov.b @(0x12345678:32,r3.w),@-er1 ;0178ebb112345678 + mov.b @(0x12345678:32,r3.w),@+er1 ;0178eb9112345678 + mov.b @(0x12345678:32,r3.w),@er1- ;0178eba112345678 + mov.b @(0x12345678:32,r3.w),@(0xffff9abc:16,er1) ;0178ebc1123456789abc + mov.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1) ;0178ebc9123456789abcdef0 + mov.b @(0x12345678:32,r3.w),@(0xffff9abc:16,r3l.b) ;0178ebd3123456789abc + mov.b @(0x12345678:32,r3.w),@(0xffff9abc:16,r3.w) ;0178ebe3123456789abc + mov.b @(0x12345678:32,r3.w),@(0xffff9abc:16,er3.l) ;0178ebf3123456789abc + mov.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,r3l.b) ;0178ebdb123456789abcdef0 + mov.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,r3.w) ;0178ebeb123456789abcdef0 + mov.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,er3.l) ;0178ebfb123456789abcdef0 + mov.b @(0x12345678:32,r3.w),@0xffff9abc:16 ;0178eb40123456789abc + mov.b @(0x12345678:32,r3.w),@0x9abcdef0:32 ;0178eb48123456789abcdef0 + + mov.b @(0x12345678:32,er3.l),@er1 ;0178fb0112345678 + mov.b @(0x12345678:32,er3.l),@(0x1:2,er1) ;0178fb1112345678 + mov.b @(0x12345678:32,er3.l),@er1+ ;0178fb8112345678 + mov.b @(0x12345678:32,er3.l),@-er1 ;0178fbb112345678 + mov.b @(0x12345678:32,er3.l),@+er1 ;0178fb9112345678 + mov.b @(0x12345678:32,er3.l),@er1- ;0178fba112345678 + mov.b @(0x12345678:32,er3.l),@(0xffff9abc:16,er1) ;0178fbc1123456789abc + mov.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1) ;0178fbc9123456789abcdef0 + mov.b @(0x12345678:32,er3.l),@(0xffff9abc:16,r3l.b) ;0178fbd3123456789abc + mov.b @(0x12345678:32,er3.l),@(0xffff9abc:16,r3.w) ;0178fbe3123456789abc + mov.b @(0x12345678:32,er3.l),@(0xffff9abc:16,er3.l) ;0178fbf3123456789abc + mov.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,r3l.b) ;0178fbdb123456789abcdef0 + mov.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,r3.w) ;0178fbeb123456789abcdef0 + mov.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,er3.l) ;0178fbfb123456789abcdef0 + mov.b @(0x12345678:32,er3.l),@0xffff9abc:16 ;0178fb40123456789abc + mov.b @(0x12345678:32,er3.l),@0x9abcdef0:32 ;0178fb48123456789abcdef0 + + mov.b @0x1234:16,@er1 ;017840011234 + mov.b @0x1234:16,@(0x1:2,er1) ;017840111234 + mov.b @0x1234:16,@er1+ ;017840811234 + mov.b @0x1234:16,@-er1 ;017840b11234 + mov.b @0x1234:16,@+er1 ;017840911234 + mov.b @0x1234:16,@er1- ;017840a11234 + mov.b @0x1234:16,@(0xffff9abc:16,er1) ;017840c112349abc + mov.b @0x1234:16,@(0x9abcdef0:32,er1) ;017840c912349abcdef0 + mov.b @0x1234:16,@(0xffff9abc:16,r3l.b) ;017840d312349abc + mov.b @0x1234:16,@(0xffff9abc:16,r3.w) ;017840e312349abc + mov.b @0x1234:16,@(0xffff9abc:16,er3.l) ;017840f312349abc + mov.b @0x1234:16,@(0x9abcdef0:32,r3l.b) ;017840db12349abcdef0 + mov.b @0x1234:16,@(0x9abcdef0:32,r3.w) ;017840eb12349abcdef0 + mov.b @0x1234:16,@(0x9abcdef0:32,er3.l) ;017840fb12349abcdef0 + mov.b @0x1234:16,@0xffff9abc:16 ;0178404012349abc + mov.b @0x1234:16,@0x9abcdef0:32 ;0178404812349abcdef0 + + mov.b @0x12345678:32,@er1 ;0178480112345678 + mov.b @0x12345678:32,@(0x1:2,er1) ;0178481112345678 + mov.b @0x12345678:32,@er1+ ;0178488112345678 + mov.b @0x12345678:32,@-er1 ;017848b112345678 + mov.b @0x12345678:32,@+er1 ;0178489112345678 + mov.b @0x12345678:32,@er1- ;017848a112345678 + mov.b @0x12345678:32,@(0xffff9abc:16,er1) ;017848c1123456789abc + mov.b @0x12345678:32,@(0x9abcdef0:32,er1) ;017848c9123456789abcdef0 + mov.b @0x12345678:32,@(0xffff9abc:16,r3l.b) ;017848d3123456789abc + mov.b @0x12345678:32,@(0xffff9abc:16,r3.w) ;017848e3123456789abc + mov.b @0x12345678:32,@(0xffff9abc:16,er3.l) ;017848f3123456789abc + mov.b @0x12345678:32,@(0x9abcdef0:32,r3l.b) ;017848db123456789abcdef0 + mov.b @0x12345678:32,@(0x9abcdef0:32,r3.w) ;017848eb123456789abcdef0 + mov.b @0x12345678:32,@(0x9abcdef0:32,er3.l) ;017848fb123456789abcdef0 + mov.b @0x12345678:32,@0xffff9abc:16 ;01784840123456789abc + mov.b @0x12345678:32,@0x9abcdef0:32 ;01784848123456789abcdef0 + + mov.w #0x1234:16,r1 ;79011234 + mov.w #0x1:3,r3 ;0f13 + mov.w #0x1234:16,@er1 ;797412340100 + mov.w #0x1234:16,@(0x2:2,er1) ;797412341100 + mov.w #0x1234:16,@er1+ ;797412348100 + mov.w #0x1234:16,@-er1 ;79741234b100 + mov.w #0x1234:16,@+er1 ;797412349100 + mov.w #0x1234:16,@er1- ;79741234a100 + mov.w #0x1234:16,@(0x1234:16,er1) ;79741234c1001234 + mov.w #0x1234:16,@(0x12345678:32,er1) ;79741234c90012345678 + mov.w #0x1234:16,@(0x1234:16,r3l.b) ;79741234d3001234 + mov.w #0x1234:16,@(0x1234:16,r3.w) ;79741234e3001234 + mov.w #0x1234:16,@(0x1234:16,er3.l) ;79741234f3001234 + mov.w #0x1234:16,@(0x12345678:32,r3l.b) ;79741234db0012345678 + mov.w #0x1234:16,@(0x12345678:32,r3.w) ;79741234eb0012345678 + mov.w #0x1234:16,@(0x12345678:32,er3.l) ;79741234fb0012345678 + mov.w #0x1234:16,@0x1234:16 ;7974123440001234 + mov.w #0x1234:16,@0x12345678:32 ;79741234480012345678 + + mov.w #0x12:8,@er1 ;015d0112 + mov.w #0x12:8,@(0x2:2,er1) ;015d1112 + mov.w #0x12:8,@er1+ ;015d8112 + mov.w #0x12:8,@-er1 ;015db112 + mov.w #0x12:8,@+er1 ;015d9112 + mov.w #0x12:8,@er1- ;015da112 + mov.w #0x12:8,@(0x1234:16,er1) ;015dc1121234 + mov.w #0x12:8,@(0x12345678:32,er1) ;015dc91212345678 + mov.w #0x12:8,@(0x1234:16,r3l.b) ;015dd3121234 + mov.w #0x12:8,@(0x1234:16,r3.w) ;015de3121234 + mov.w #0x12:8,@(0x1234:16,er3.l) ;015df3121234 + mov.w #0x12:8,@(0x12345678:32,r3l.b) ;015ddb1212345678 + mov.w #0x12:8,@(0x12345678:32,r3.w) ;015deb1212345678 + mov.w #0x12:8,@(0x12345678:32,er3.l) ;015dfb1212345678 + mov.w #0x12:8,@0x1234:16 ;015d40121234 + mov.w #0x12:8,@0x12345678:32 ;015d481212345678 + + mov.w #0x1:4,@0x1234:16 ;6bd11234 + mov.w #0x1:4,@0x12345678:32 ;6bf112345678 + + mov.w r2,r1 ;0d21 + + mov.w r2,@er1 ;6992 + mov.w r2,@(0x2:2,er1) ;01516992 + mov.w r2,@er1+ ;01536d92 + mov.w r2,@-er1 ;6d92 + mov.w r2,@+er1 ;01526d92 + mov.w r2,@er1- ;01516d92 + mov.w r2,@(0x1234:16,er1) ;6f921234 + mov.w r2,@(0x12345678:32,er1) ;78106ba212345678 + mov.w r2,@(0x1234:16,r3l.b) ;01516fb21234 + mov.w r2,@(0x1234:16,r3.w) ;01526fb21234 + mov.w r2,@(0x1234:16,er3.l) ;01536fb21234 + mov.w r2,@(0x12345678:32,r3l.b) ;78316ba212345678 + mov.w r2,@(0x12345678:32,r3.w) ;78326ba212345678 + mov.w r2,@(0x12345678:32,er3.l) ;78336ba212345678 + mov.w r2,@0x1234:16 ;6b821234 + mov.w r2,@0x12345678:32 ;6ba212345678 + + mov.w @er2,r1 ;6921 + mov.w @(0x2:2,er2),r1 ;01516921 + mov.w @er2+,r1 ;6d21 + mov.w @-er2,r1 ;01536d21 + mov.w @+er2,r1 ;01516d21 + mov.w @er2-,r1 ;01526d21 + mov.w @(0x1234:16,er1),r1 ;6f111234 + mov.w @(0x12345678:32,er1),r1 ;78106b2112345678 + mov.w @(0x1234:16,r3l.b),r1 ;01516f311234 + mov.w @(0x1234:16,r3.w),r1 ;01526f311234 + mov.w @(0x1234:16,er3.l),r1 ;01536f311234 + mov.w @(0x12345678:32,r3l.b),r1 ;78316b2112345678 + mov.w @(0x12345678:32,r3.w),r1 ;78326b2112345678 + mov.w @(0x12345678:32,er3.l),r1 ;78336b2112345678 + mov.w @0x1234:16,r1 ;6b011234 + mov.w @0x12345678:32,r1 ;6b2112345678 + + mov.w @er2,@er1 ;01580201 + mov.w @er2,@(0x2:2,er1) ;01580211 + mov.w @er2,@er1+ ;01580281 + mov.w @er2,@-er1 ;015802b1 + mov.w @er2,@+er1 ;01580291 + mov.w @er2,@er1- ;015802a1 + mov.w @er2,@(0x1234:16,er1) ;015802c11234 + mov.w @er2,@(0x12345678:32,er1) ;015802c912345678 + mov.w @er2,@(0x1234:16,r3l.b) ;015802d31234 + mov.w @er2,@(0x1234:16,r3.w) ;015802e31234 + mov.w @er2,@(0x1234:16,er3.l) ;015802f31234 + mov.w @er2,@(0x12345678:32,r3l.b) ;015802db12345678 + mov.w @er2,@(0x12345678:32,r3.w) ;015802eb12345678 + mov.w @er2,@(0x12345678:32,er3.l) ;015802fb12345678 + mov.w @er2,@0x1234:16 ;015802401234 + mov.w @er2,@0x12345678:32 ;0158024812345678 + + mov.w @(0x2:2,er2),@er1 ;01581201 + mov.w @(0x2:2,er2),@(0x2:2,er1) ;01581211 + mov.w @(0x2:2,er2),@er1+ ;01581281 + mov.w @(0x2:2,er2),@-er1 ;015812b1 + mov.w @(0x2:2,er2),@+er1 ;01581291 + mov.w @(0x2:2,er2),@er1- ;015812a1 + mov.w @(0x2:2,er2),@(0x1234:16,er1) ;015812c11234 + mov.w @(0x2:2,er2),@(0x12345678:32,er1) ;015812c912345678 + mov.w @(0x2:2,er2),@(0x1234:16,r3l.b) ;015812d31234 + mov.w @(0x2:2,er2),@(0x1234:16,r3.w) ;015812e31234 + mov.w @(0x2:2,er2),@(0x1234:16,er3.l) ;015812f31234 + mov.w @(0x2:2,er2),@(0x12345678:32,r3l.b) ;015812db12345678 + mov.w @(0x2:2,er2),@(0x12345678:32,r3.w) ;015812eb12345678 + mov.w @(0x2:2,er2),@(0x12345678:32,er3.l) ;015812fb12345678 + mov.w @(0x2:2,er2),@0x1234:16 ;015812401234 + mov.w @(0x2:2,er2),@0x12345678:32 ;0158124812345678 + + mov.w @-er2,@er1 ;0158b201 + mov.w @-er2,@(0x2:2,er1) ;0158b211 + mov.w @-er2,@er1+ ;0158b281 + mov.w @-er2,@-er1 ;0158b2b1 + mov.w @-er2,@+er1 ;0158b291 + mov.w @-er2,@er1- ;0158b2a1 + mov.w @-er2,@(0x1234:16,er1) ;0158b2c11234 + mov.w @-er2,@(0x12345678:32,er1) ;0158b2c912345678 + mov.w @-er2,@(0x1234:16,r3l.b) ;0158b2d31234 + mov.w @-er2,@(0x1234:16,r3.w) ;0158b2e31234 + mov.w @-er2,@(0x1234:16,er3.l) ;0158b2f31234 + mov.w @-er2,@(0x12345678:32,r3l.b) ;0158b2db12345678 + mov.w @-er2,@(0x12345678:32,r3.w) ;0158b2eb12345678 + mov.w @-er2,@(0x12345678:32,er3.l) ;0158b2fb12345678 + mov.w @-er2,@0x1234:16 ;0158b2401234 + mov.w @-er2,@0x12345678:32 ;0158b24812345678 + + mov.w @er2+,@er1 ;01588201 + mov.w @er2+,@(0x2:2,er1) ;01588211 + mov.w @er2+,@er1+ ;01588281 + mov.w @er2+,@-er1 ;015882b1 + mov.w @er2+,@+er1 ;01588291 + mov.w @er2+,@er1- ;015882a1 + mov.w @er2+,@(0x1234:16,er1) ;015882c11234 + mov.w @er2+,@(0x12345678:32,er1) ;015882c912345678 + mov.w @er2+,@(0x1234:16,r3l.b) ;015882d31234 + mov.w @er2+,@(0x1234:16,r3.w) ;015882e31234 + mov.w @er2+,@(0x1234:16,er3.l) ;015882f31234 + mov.w @er2+,@(0x12345678:32,r3l.b) ;015882db12345678 + mov.w @er2+,@(0x12345678:32,r3.w) ;015882eb12345678 + mov.w @er2+,@(0x12345678:32,er3.l) ;015882fb12345678 + mov.w @er2+,@0x1234:16 ;015882401234 + mov.w @er2+,@0x12345678:32 ;0158824812345678 + + mov.w @er2-,@er1 ;0158a201 + mov.w @er2-,@(0x2:2,er1) ;0158a211 + mov.w @er2-,@er1+ ;0158a281 + mov.w @er2-,@-er1 ;0158a2b1 + mov.w @er2-,@+er1 ;0158a291 + mov.w @er2-,@er1- ;0158a2a1 + mov.w @er2-,@(0x1234:16,er1) ;0158a2c11234 + mov.w @er2-,@(0x12345678:32,er1) ;0158a2c912345678 + mov.w @er2-,@(0x1234:16,r3l.b) ;0158a2d31234 + mov.w @er2-,@(0x1234:16,r3.w) ;0158a2e31234 + mov.w @er2-,@(0x1234:16,er3.l) ;0158a2f31234 + mov.w @er2-,@(0x12345678:32,r3l.b) ;0158a2db12345678 + mov.w @er2-,@(0x12345678:32,r3.w) ;0158a2eb12345678 + mov.w @er2-,@(0x12345678:32,er3.l) ;0158a2fb12345678 + mov.w @er2-,@0x1234:16 ;0158a2401234 + mov.w @er2-,@0x12345678:32 ;0158a24812345678 + + mov.w @+er2,@er1 ;01589201 + mov.w @+er2,@(0x2:2,er1) ;01589211 + mov.w @+er2,@er1+ ;01589281 + mov.w @+er2,@-er1 ;015892b1 + mov.w @+er2,@+er1 ;01589291 + mov.w @+er2,@er1- ;015892a1 + mov.w @+er2,@(0x1234:16,er1) ;015892c11234 + mov.w @+er2,@(0x12345678:32,er1) ;015892c912345678 + mov.w @+er2,@(0x1234:16,r3l.b) ;015892d31234 + mov.w @+er2,@(0x1234:16,r3.w) ;015892e31234 + mov.w @+er2,@(0x1234:16,er3.l) ;015892f31234 + mov.w @+er2,@(0x12345678:32,r3l.b) ;015892db12345678 + mov.w @+er2,@(0x12345678:32,r3.w) ;015892eb12345678 + mov.w @+er2,@(0x12345678:32,er3.l) ;015892fb12345678 + mov.w @+er2,@0x1234:16 ;015892401234 + mov.w @+er2,@0x12345678:32 ;0158924812345678 + + mov.w @(0x1234:16,er2),@er1 ;0158c2011234 + mov.w @(0x1234:16,er2),@(0x2:2,er1) ;0158c2111234 + mov.w @(0x1234:16,er2),@er1+ ;0158c2811234 + mov.w @(0x1234:16,er2),@-er1 ;0158c2b11234 + mov.w @(0x1234:16,er2),@+er1 ;0158c2911234 + mov.w @(0x1234:16,er2),@er1- ;0158c2a11234 + mov.w @(0x1234:16,er2),@(0xffff9abc:16,er1) ;0158c2c112349abc + mov.w @(0x1234:16,er2),@(0x9abcdef0:32,er1) ;0158c2c912349abcdef0 + mov.w @(0x1234:16,er2),@(0xffff9abc:16,r3l.b) ;0158c2d312349abc + mov.w @(0x1234:16,er2),@(0xffff9abc:16,r3.w) ;0158c2e312349abc + mov.w @(0x1234:16,er2),@(0xffff9abc:16,er3.l) ;0158c2f312349abc + mov.w @(0x1234:16,er2),@(0x9abcdef0:32,r3l.b) ;0158c2db12349abcdef0 + mov.w @(0x1234:16,er2),@(0x9abcdef0:32,r3.w) ;0158c2eb12349abcdef0 + mov.w @(0x1234:16,er2),@(0x9abcdef0:32,er3.l) ;0158c2fb12349abcdef0 + mov.w @(0x1234:16,er2),@0xffff9abc:16 ;0158c24012349abc + mov.w @(0x1234:16,er2),@0x9abcdef0:32 ;0158c24812349abcdef0 + + mov.w @(0x12345678:32,er2),@er1 ;0158ca0112345678 + mov.w @(0x12345678:32,er2),@(0x2:2,er1) ;0158ca1112345678 + mov.w @(0x12345678:32,er2),@er1+ ;0158ca8112345678 + mov.w @(0x12345678:32,er2),@-er1 ;0158cab112345678 + mov.w @(0x12345678:32,er2),@+er1 ;0158ca9112345678 + mov.w @(0x12345678:32,er2),@er1- ;0158caa112345678 + mov.w @(0x12345678:32,er2),@(0xffff9abc:16,er1) ;0158cac1123456789abc + mov.w @(0x12345678:32,er2),@(0x9abcdef0:32,er1) ;0158cac9123456789abcdef0 + mov.w @(0x12345678:32,er2),@(0xffff9abc:16,r3l.b) ;0158cad3123456789abc + mov.w @(0x12345678:32,er2),@(0xffff9abc:16,r3.w) ;0158cae3123456789abc + mov.w @(0x12345678:32,er2),@(0xffff9abc:16,er3.l) ;0158caf3123456789abc + mov.w @(0x12345678:32,er2),@(0x9abcdef0:32,r3l.b) ;0158cadb123456789abcdef0 + mov.w @(0x12345678:32,er2),@(0x9abcdef0:32,r3.w) ;0158caeb123456789abcdef0 + mov.w @(0x12345678:32,er2),@(0x9abcdef0:32,er3.l) ;0158cafb123456789abcdef0 + mov.w @(0x12345678:32,er2),@0xffff9abc:16 ;0158ca40123456789abc + mov.w @(0x12345678:32,er2),@0x9abcdef0:32 ;0158ca48123456789abcdef0 + + mov.w @(0x1234:16,r3l.b),@er1 ;0158d3011234 + mov.w @(0x1234:16,r3l.b),@(0x2:2,er1) ;0158d3111234 + mov.w @(0x1234:16,r3l.b),@er1+ ;0158d3811234 + mov.w @(0x1234:16,r3l.b),@-er1 ;0158d3b11234 + mov.w @(0x1234:16,r3l.b),@+er1 ;0158d3911234 + mov.w @(0x1234:16,r3l.b),@er1- ;0158d3a11234 + mov.w @(0x1234:16,r3l.b),@(0xffff9abc:16,er1) ;0158d3c112349abc + mov.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1) ;0158d3c912349abcdef0 + mov.w @(0x1234:16,r3l.b),@(0xffff9abc:16,r3l.b) ;0158d3d312349abc + mov.w @(0x1234:16,r3l.b),@(0xffff9abc:16,r3.w) ;0158d3e312349abc + mov.w @(0x1234:16,r3l.b),@(0xffff9abc:16,er3.l) ;0158d3f312349abc + mov.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,r3l.b) ;0158d3db12349abcdef0 + mov.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,r3.w) ;0158d3eb12349abcdef0 + mov.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,er3.l) ;0158d3fb12349abcdef0 + mov.w @(0x1234:16,r3l.b),@0xffff9abc:16 ;0158d34012349abc + mov.w @(0x1234:16,r3l.b),@0x9abcdef0:32 ;0158d34812349abcdef0 + + mov.w @(0x1234:16,r3.w),@er1 ;0158e3011234 + mov.w @(0x1234:16,r3.w),@(0x2:2,er1) ;0158e3111234 + mov.w @(0x1234:16,r3.w),@er1+ ;0158e3811234 + mov.w @(0x1234:16,r3.w),@-er1 ;0158e3b11234 + mov.w @(0x1234:16,r3.w),@+er1 ;0158e3911234 + mov.w @(0x1234:16,r3.w),@er1- ;0158e3a11234 + mov.w @(0x1234:16,r3.w),@(0xffff9abc:16,er1) ;0158e3c112349abc + mov.w @(0x1234:16,r3.w),@(0x9abcdef0:32,er1) ;0158e3c912349abcdef0 + mov.w @(0x1234:16,r3.w),@(0xffff9abc:16,r3l.b) ;0158e3d312349abc + mov.w @(0x1234:16,r3.w),@(0xffff9abc:16,r3.w) ;0158e3e312349abc + mov.w @(0x1234:16,r3.w),@(0xffff9abc:16,er3.l) ;0158e3f312349abc + mov.w @(0x1234:16,r3.w),@(0x9abcdef0:32,r3l.b) ;0158e3db12349abcdef0 + mov.w @(0x1234:16,r3.w),@(0x9abcdef0:32,r3.w) ;0158e3eb12349abcdef0 + mov.w @(0x1234:16,r3.w),@(0x9abcdef0:32,er3.l) ;0158e3fb12349abcdef0 + mov.w @(0x1234:16,r3.w),@0xffff9abc:16 ;0158e34012349abc + mov.w @(0x1234:16,r3.w),@0x9abcdef0:32 ;0158e34812349abcdef0 + + mov.w @(0x1234:16,er3.l),@er1 ;0158f3011234 + mov.w @(0x1234:16,er3.l),@(0x2:2,er1) ;0158f3111234 + mov.w @(0x1234:16,er3.l),@er1+ ;0158f3811234 + mov.w @(0x1234:16,er3.l),@-er1 ;0158f3b11234 + mov.w @(0x1234:16,er3.l),@+er1 ;0158f3911234 + mov.w @(0x1234:16,er3.l),@er1- ;0158f3a11234 + mov.w @(0x1234:16,er3.l),@(0xffff9abc:16,er1) ;0158f3c112349abc + mov.w @(0x1234:16,er3.l),@(0x9abcdef0:32,er1) ;0158f3c912349abcdef0 + mov.w @(0x1234:16,er3.l),@(0xffff9abc:16,r3l.b) ;0158f3d312349abc + mov.w @(0x1234:16,er3.l),@(0xffff9abc:16,r3.w) ;0158f3e312349abc + mov.w @(0x1234:16,er3.l),@(0xffff9abc:16,er3.l) ;0158f3f312349abc + mov.w @(0x1234:16,er3.l),@(0x9abcdef0:32,r3l.b) ;0158f3db12349abcdef0 + mov.w @(0x1234:16,er3.l),@(0x9abcdef0:32,r3.w) ;0158f3eb12349abcdef0 + mov.w @(0x1234:16,er3.l),@(0x9abcdef0:32,er3.l) ;0158f3fb12349abcdef0 + mov.w @(0x1234:16,er3.l),@0xffff9abc:16 ;0158f34012349abc + mov.w @(0x1234:16,er3.l),@0x9abcdef0:32 ;0158f34812349abcdef0 + + mov.w @(0x12345678:32,r3l.b),@er1 ;0158db0112345678 + mov.w @(0x12345678:32,r3l.b),@(0x2:2,er1) ;0158db1112345678 + mov.w @(0x12345678:32,r3l.b),@er1+ ;0158db8112345678 + mov.w @(0x12345678:32,r3l.b),@-er1 ;0158dbb112345678 + mov.w @(0x12345678:32,r3l.b),@+er1 ;0158db9112345678 + mov.w @(0x12345678:32,r3l.b),@er1- ;0158dba112345678 + mov.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,er1) ;0158dbc1123456789abc + mov.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1) ;0158dbc9123456789abcdef0 + mov.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,r3l.b) ;0158dbd3123456789abc + mov.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,r3.w) ;0158dbe3123456789abc + mov.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,er3.l) ;0158dbf3123456789abc + mov.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r3l.b) ;0158dbdb123456789abcdef0 + mov.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r3.w) ;0158dbeb123456789abcdef0 + mov.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er3.l) ;0158dbfb123456789abcdef0 + mov.w @(0x12345678:32,r3l.b),@0xffff9abc:16 ;0158db40123456789abc + mov.w @(0x12345678:32,r3l.b),@0x9abcdef0:32 ;0158db48123456789abcdef0 + + mov.w @(0x12345678:32,r3.w),@er1 ;0158eb0112345678 + mov.w @(0x12345678:32,r3.w),@(0x2:2,er1) ;0158eb1112345678 + mov.w @(0x12345678:32,r3.w),@er1+ ;0158eb8112345678 + mov.w @(0x12345678:32,r3.w),@-er1 ;0158ebb112345678 + mov.w @(0x12345678:32,r3.w),@+er1 ;0158eb9112345678 + mov.w @(0x12345678:32,r3.w),@er1- ;0158eba112345678 + mov.w @(0x12345678:32,r3.w),@(0xffff9abc:16,er1) ;0158ebc1123456789abc + mov.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1) ;0158ebc9123456789abcdef0 + mov.w @(0x12345678:32,r3.w),@(0xffff9abc:16,r3l.b) ;0158ebd3123456789abc + mov.w @(0x12345678:32,r3.w),@(0xffff9abc:16,r3.w) ;0158ebe3123456789abc + mov.w @(0x12345678:32,r3.w),@(0xffff9abc:16,er3.l) ;0158ebf3123456789abc + mov.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,r3l.b) ;0158ebdb123456789abcdef0 + mov.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,r3.w) ;0158ebeb123456789abcdef0 + mov.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,er3.l) ;0158ebfb123456789abcdef0 + mov.w @(0x12345678:32,r3.w),@0xffff9abc:16 ;0158eb40123456789abc + mov.w @(0x12345678:32,r3.w),@0x9abcdef0:32 ;0158eb48123456789abcdef0 + + mov.w @(0x12345678:32,er3.l),@er1 ;0158fb0112345678 + mov.w @(0x12345678:32,er3.l),@(0x2:2,er1) ;0158fb1112345678 + mov.w @(0x12345678:32,er3.l),@er1+ ;0158fb8112345678 + mov.w @(0x12345678:32,er3.l),@-er1 ;0158fbb112345678 + mov.w @(0x12345678:32,er3.l),@+er1 ;0158fb9112345678 + mov.w @(0x12345678:32,er3.l),@er1- ;0158fba112345678 + mov.w @(0x12345678:32,er3.l),@(0xffff9abc:16,er1) ;0158fbc1123456789abc + mov.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1) ;0158fbc9123456789abcdef0 + mov.w @(0x12345678:32,er3.l),@(0xffff9abc:16,r3l.b) ;0158fbd3123456789abc + mov.w @(0x12345678:32,er3.l),@(0xffff9abc:16,r3.w) ;0158fbe3123456789abc + mov.w @(0x12345678:32,er3.l),@(0xffff9abc:16,er3.l) ;0158fbf3123456789abc + mov.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,r3l.b) ;0158fbdb123456789abcdef0 + mov.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,r3.w) ;0158fbeb123456789abcdef0 + mov.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,er3.l) ;0158fbfb123456789abcdef0 + mov.w @(0x12345678:32,er3.l),@0xffff9abc:16 ;0158fb40123456789abc + mov.w @(0x12345678:32,er3.l),@0x9abcdef0:32 ;0158fb48123456789abcdef0 + + mov.w @0x1234:16,@er1 ;015840011234 + mov.w @0x1234:16,@(0x2:2,er1) ;015840111234 + mov.w @0x1234:16,@er1+ ;015840811234 + mov.w @0x1234:16,@-er1 ;015840b11234 + mov.w @0x1234:16,@+er1 ;015840911234 + mov.w @0x1234:16,@er1- ;015840a11234 + mov.w @0x1234:16,@(0xffff9abc:16,er1) ;015840c112349abc + mov.w @0x1234:16,@(0x9abcdef0:32,er1) ;015840c912349abcdef0 + mov.w @0x1234:16,@(0xffff9abc:16,r3l.b) ;015840d312349abc + mov.w @0x1234:16,@(0xffff9abc:16,r3.w) ;015840e312349abc + mov.w @0x1234:16,@(0xffff9abc:16,er3.l) ;015840f312349abc + mov.w @0x1234:16,@(0x9abcdef0:32,r3l.b) ;015840db12349abcdef0 + mov.w @0x1234:16,@(0x9abcdef0:32,r3.w) ;015840eb12349abcdef0 + mov.w @0x1234:16,@(0x9abcdef0:32,er3.l) ;015840fb12349abcdef0 + mov.w @0x1234:16,@0xffff9abc:16 ;0158404012349abc + mov.w @0x1234:16,@0x9abcdef0:32 ;0158404812349abcdef0 + + mov.w @0x12345678:32,@er1 ;0158480112345678 + mov.w @0x12345678:32,@(0x2:2,er1) ;0158481112345678 + mov.w @0x12345678:32,@er1+ ;0158488112345678 + mov.w @0x12345678:32,@-er1 ;015848b112345678 + mov.w @0x12345678:32,@+er1 ;0158489112345678 + mov.w @0x12345678:32,@er1- ;015848a112345678 + mov.w @0x12345678:32,@(0xffff9abc:16,er1) ;015848c1123456789abc + mov.w @0x12345678:32,@(0x9abcdef0:32,er1) ;015848c9123456789abcdef0 + mov.w @0x12345678:32,@(0xffff9abc:16,r3l.b) ;015848d3123456789abc + mov.w @0x12345678:32,@(0xffff9abc:16,r3.w) ;015848e3123456789abc + mov.w @0x12345678:32,@(0xffff9abc:16,er3.l) ;015848f3123456789abc + mov.w @0x12345678:32,@(0x9abcdef0:32,r3l.b) ;015848db123456789abcdef0 + mov.w @0x12345678:32,@(0x9abcdef0:32,r3.w) ;015848eb123456789abcdef0 + mov.w @0x12345678:32,@(0x9abcdef0:32,er3.l) ;015848fb123456789abcdef0 + mov.w @0x12345678:32,@0xffff9abc:16 ;01584840123456789abc + mov.w @0x12345678:32,@0x9abcdef0:32 ;01584848123456789abcdef0 + + mov.l #0x12345678:32,er1 ;7a0112345678 + + mov.l #0x1234:16,er1 ;7a091234 + + mov.l #0x1:3,er3 ;0f9b + + mov.l #0x12345678:32,@er1 ;7a74123456780100 + mov.l #0x12345678:32,@(0x4:2,er1) ;7a74123456781100 + mov.l #0x12345678:32,@-er1 ;7a7412345678b100 + mov.l #0x12345678:32,@er1+ ;7a74123456788100 + mov.l #0x12345678:32,@er1- ;7a7412345678a100 + mov.l #0x12345678:32,@+er1 ;7a74123456789100 + mov.l #0x12345678:32,@(0x1234:16,er1) ;7a7412345678c1001234 + mov.l #0x12345678:32,@(0x12345678:32,er1) ;7a7412345678c90012345678 + mov.l #0x12345678:32,@(0x1234:16,r3l.b) ;7a7412345678d3001234 + mov.l #0x12345678:32,@(0x1234:16,r3.w) ;7a7412345678e3001234 + mov.l #0x12345678:32,@(0x1234:16,er3.l) ;7a7412345678f3001234 + mov.l #0x12345678:32,@(0x12345678:32,r3l.b) ;7a7412345678db0012345678 + mov.l #0x12345678:32,@(0x12345678:32,r3.w) ;7a7412345678eb0012345678 + mov.l #0x12345678:32,@(0x12345678:32,er3.l) ;7a7412345678fb0012345678 + mov.l #0x12345678:32,@0x1234:16 ;7a741234567840001234 + mov.l #0x12345678:32,@0x12345678:32 ;7a7412345678480012345678 + + mov.l #0x1234:16,@er1 ;7a7c12340100 + mov.l #0x1234:16,@(0x4:2,er1) ;7a7c12341100 + mov.l #0x1234:16,@-er1 ;7a7c1234b100 + mov.l #0x1234:16,@er1+ ;7a7c12348100 + mov.l #0x1234:16,@er1- ;7a7c1234a100 + mov.l #0x1234:16,@+er1 ;7a7c12349100 + mov.l #0x1234:16,@(0x1234:16,er1) ;7a7c1234c1001234 + mov.l #0x1234:16,@(0x12345678:32,er1) ;7a7c1234c90012345678 + mov.l #0x1234:16,@(0x1234:16,r3l.b) ;7a7c1234d3001234 + mov.l #0x1234:16,@(0x1234:16,r3.w) ;7a7c1234e3001234 + mov.l #0x1234:16,@(0x1234:16,er3.l) ;7a7c1234f3001234 + mov.l #0x1234:16,@(0x12345678:32,r3l.b) ;7a7c1234db0012345678 + mov.l #0x1234:16,@(0x12345678:32,r3.w) ;7a7c1234eb0012345678 + mov.l #0x1234:16,@(0x12345678:32,er3.l) ;7a7c1234fb0012345678 + mov.l #0x1234:16,@0x1234:16 ;7a7c123440001234 + mov.l #0x1234:16,@0x12345678:32 ;7a7c1234480012345678 + + mov.l #0x12:8,@er1 ;010d0112 + mov.l #0x12:8,@(0x4:2,er1) ;010d1112 + mov.l #0x12:8,@-er1 ;010db112 + mov.l #0x12:8,@er1+ ;010d8112 + mov.l #0x12:8,@er1- ;010da112 + mov.l #0x12:8,@+er1 ;010d9112 + mov.l #0x12:8,@(0x1234:16,er1) ;010dc1121234 + mov.l #0x12:8,@(0x12345678:32,er1) ;010dc91212345678 + mov.l #0x12:8,@(0x1234:16,r3l.b) ;010dd3121234 + mov.l #0x12:8,@(0x1234:16,r3.w) ;010de3121234 + mov.l #0x12:8,@(0x1234:16,er3.l) ;010df3121234 + mov.l #0x12:8,@(0x12345678:32,r3l.b) ;010ddb1212345678 + mov.l #0x12:8,@(0x12345678:32,r3.w) ;010deb1212345678 + mov.l #0x12:8,@(0x12345678:32,er3.l) ;010dfb1212345678 + mov.l #0x12:8,@0x1234:16 ;010d40121234 + mov.l #0x12:8,@0x12345678:32 ;010d481212345678 + + mov.l er2,er1 ;0fa1 + + mov.l er2,@er1 ;01006992 + mov.l er2,@(0x4:2,er1) ;01016992 + mov.l er2,@-er1 ;01006d92 + mov.l er2,@er1+ ;01036d92 + mov.l er2,@er1- ;01016d92 + mov.l er2,@+er1 ;01026d92 + mov.l er2,@(0x1234:16,er1) ;01006f921234 + mov.l er2,@(0x12345678:32,er1) ;78906ba212345678 + mov.l er2,@(0x1234:16,r3l.b) ;01016fb21234 + mov.l er2,@(0x1234:16,r3.w) ;01026fb21234 + mov.l er2,@(0x1234:16,er3.l) ;01036fb21234 + mov.l er2,@(0x12345678:32,r3l.b) ;78b16ba212345678 + mov.l er2,@(0x12345678:32,r3.w) ;78b26ba212345678 + mov.l er2,@(0x12345678:32,er3.l) ;78b36ba212345678 + mov.l er2,@0x1234:16 ;01006b821234 + mov.l er2,@0x12345678:32 ;01006ba212345678 + + mov.l @er2,er1 ;01006921 + mov.l @(0x4:2,er2),er1 ;01016921 + mov.l @er2+,er1 ;01006d21 + mov.l @-er2,er1 ;01036d21 + mov.l @+er2,er1 ;01016d21 + mov.l @er2-,er1 ;01026d21 + mov.l @(0x1234:16,er1),er1 ;01006f111234 + mov.l @(0x12345678:32,er1),er1 ;78906b2112345678 + mov.l @(0x1234:16,r3l.b),er1 ;01016f311234 + mov.l @(0x1234:16,r3.w),er1 ;01026f311234 + mov.l @(0x1234:16,er3.l),er1 ;01036f311234 + mov.l @(0x12345678:32,r3l.b),er1 ;78b16b2112345678 + mov.l @(0x12345678:32,r3.w),er1 ;78b26b2112345678 + mov.l @(0x12345678:32,er3.l),er1 ;78b36b2112345678 + mov.l @0x1234:16,er1 ;01006b011234 + mov.l @0x12345678:32,er1 ;01006b2112345678 + + mov.l @er2,@er1 ;01080201 + mov.l @er2,@(0x4:2,er1) ;01080211 + mov.l @er2,@er1+ ;01080281 + mov.l @er2,@-er1 ;010802b1 + mov.l @er2,@+er1 ;01080291 + mov.l @er2,@er1- ;010802a1 + mov.l @er2,@(0x1234:16,er1) ;010802c11234 + mov.l @er2,@(0x12345678:32,er1) ;010802c912345678 + mov.l @er2,@(0x1234:16,r3l.b) ;010802d31234 + mov.l @er2,@(0x1234:16,r3.w) ;010802e31234 + mov.l @er2,@(0x1234:16,er3.l) ;010802f31234 + mov.l @er2,@(0x12345678:32,r3l.b) ;010802db12345678 + mov.l @er2,@(0x12345678:32,r3.w) ;010802eb12345678 + mov.l @er2,@(0x12345678:32,er3.l) ;010802fb12345678 + mov.l @er2,@0x1234:16 ;010802401234 + mov.l @er2,@0x12345678:32 ;0108024812345678 + + mov.l @(0x4:2,er2),@er1 ;01081201 + mov.l @(0x4:2,er2),@(0x4:2,er1) ;01081211 + mov.l @(0x4:2,er2),@er1+ ;01081281 + mov.l @(0x4:2,er2),@-er1 ;010812b1 + mov.l @(0x4:2,er2),@+er1 ;01081291 + mov.l @(0x4:2,er2),@er1- ;010812a1 + mov.l @(0x4:2,er2),@(0x1234:16,er1) ;010812c11234 + mov.l @(0x4:2,er2),@(0x12345678:32,er1) ;010812c912345678 + mov.l @(0x4:2,er2),@(0x1234:16,r3l.b) ;010812d31234 + mov.l @(0x4:2,er2),@(0x1234:16,r3.w) ;010812e31234 + mov.l @(0x4:2,er2),@(0x1234:16,er3.l) ;010812f31234 + mov.l @(0x4:2,er2),@(0x12345678:32,r3l.b) ;010812db12345678 + mov.l @(0x4:2,er2),@(0x12345678:32,r3.w) ;010812eb12345678 + mov.l @(0x4:2,er2),@(0x12345678:32,er3.l) ;010812fb12345678 + mov.l @(0x4:2,er2),@0x1234:16 ;010812401234 + mov.l @(0x4:2,er2),@0x12345678:32 ;0108124812345678 + + mov.l @-er2,@er1 ;0108b201 + mov.l @-er2,@(0x4:2,er1) ;0108b211 + mov.l @-er2,@er1+ ;0108b281 + mov.l @-er2,@-er1 ;0108b2b1 + mov.l @-er2,@+er1 ;0108b291 + mov.l @-er2,@er1- ;0108b2a1 + mov.l @-er2,@(0x1234:16,er1) ;0108b2c11234 + mov.l @-er2,@(0x12345678:32,er1) ;0108b2c912345678 + mov.l @-er2,@(0x1234:16,r3l.b) ;0108b2d31234 + mov.l @-er2,@(0x1234:16,r3.w) ;0108b2e31234 + mov.l @-er2,@(0x1234:16,er3.l) ;0108b2f31234 + mov.l @-er2,@(0x12345678:32,r3l.b) ;0108b2db12345678 + mov.l @-er2,@(0x12345678:32,r3.w) ;0108b2eb12345678 + mov.l @-er2,@(0x12345678:32,er3.l) ;0108b2fb12345678 + mov.l @-er2,@0x1234:16 ;0108b2401234 + mov.l @-er2,@0x12345678:32 ;0108b24812345678 + + mov.l @er2+,@er1 ;01088201 + mov.l @er2+,@(0x4:2,er1) ;01088211 + mov.l @er2+,@er1+ ;01088281 + mov.l @er2+,@-er1 ;010882b1 + mov.l @er2+,@+er1 ;01088291 + mov.l @er2+,@er1- ;010882a1 + mov.l @er2+,@(0x1234:16,er1) ;010882c11234 + mov.l @er2+,@(0x12345678:32,er1) ;010882c912345678 + mov.l @er2+,@(0x1234:16,r3l.b) ;010882d31234 + mov.l @er2+,@(0x1234:16,r3.w) ;010882e31234 + mov.l @er2+,@(0x1234:16,er3.l) ;010882f31234 + mov.l @er2+,@(0x12345678:32,r3l.b) ;010882db12345678 + mov.l @er2+,@(0x12345678:32,r3.w) ;010882eb12345678 + mov.l @er2+,@(0x12345678:32,er3.l) ;010882fb12345678 + mov.l @er2+,@0x1234:16 ;010882401234 + mov.l @er2+,@0x12345678:32 ;0108824812345678 + + mov.l @er2-,@er1 ;0108a201 + mov.l @er2-,@(0x4:2,er1) ;0108a211 + mov.l @er2-,@er1+ ;0108a281 + mov.l @er2-,@-er1 ;0108a2b1 + mov.l @er2-,@+er1 ;0108a291 + mov.l @er2-,@er1- ;0108a2a1 + mov.l @er2-,@(0x1234:16,er1) ;0108a2c11234 + mov.l @er2-,@(0x12345678:32,er1) ;0108a2c912345678 + mov.l @er2-,@(0x1234:16,r3l.b) ;0108a2d31234 + mov.l @er2-,@(0x1234:16,r3.w) ;0108a2e31234 + mov.l @er2-,@(0x1234:16,er3.l) ;0108a2f31234 + mov.l @er2-,@(0x12345678:32,r3l.b) ;0108a2db12345678 + mov.l @er2-,@(0x12345678:32,r3.w) ;0108a2eb12345678 + mov.l @er2-,@(0x12345678:32,er3.l) ;0108a2fb12345678 + mov.l @er2-,@0x1234:16 ;0108a2401234 + mov.l @er2-,@0x12345678:32 ;0108a24812345678 + + mov.l @+er2,@er1 ;01089201 + mov.l @+er2,@(0x4:2,er1) ;01089211 + mov.l @+er2,@er1+ ;01089281 + mov.l @+er2,@-er1 ;010892b1 + mov.l @+er2,@+er1 ;01089291 + mov.l @+er2,@er1- ;010892a1 + mov.l @+er2,@(0x1234:16,er1) ;010892c11234 + mov.l @+er2,@(0x12345678:32,er1) ;010892c912345678 + mov.l @+er2,@(0x1234:16,r3l.b) ;010892d31234 + mov.l @+er2,@(0x1234:16,r3.w) ;010892e31234 + mov.l @+er2,@(0x1234:16,er3.l) ;010892f31234 + mov.l @+er2,@(0x12345678:32,r3l.b) ;010892db12345678 + mov.l @+er2,@(0x12345678:32,r3.w) ;010892eb12345678 + mov.l @+er2,@(0x12345678:32,er3.l) ;010892fb12345678 + mov.l @+er2,@0x1234:16 ;010892401234 + mov.l @+er2,@0x12345678:32 ;0108924812345678 + + mov.l @(0x1234:16,er2),@er1 ;0108c2011234 + mov.l @(0x1234:16,er2),@(0x4:2,er1) ;0108c2111234 + mov.l @(0x1234:16,er2),@er1+ ;0108c2811234 + mov.l @(0x1234:16,er2),@-er1 ;0108c2b11234 + mov.l @(0x1234:16,er2),@+er1 ;0108c2911234 + mov.l @(0x1234:16,er2),@er1- ;0108c2a11234 + mov.l @(0x1234:16,er2),@(0xffff9abc:16,er1) ;0108c2c112349abc + mov.l @(0x1234:16,er2),@(0x9abcdef0:32,er1) ;0108c2c912349abcdef0 + mov.l @(0x1234:16,er2),@(0xffff9abc:16,r3l.b) ;0108c2d312349abc + mov.l @(0x1234:16,er2),@(0xffff9abc:16,r3.w) ;0108c2e312349abc + mov.l @(0x1234:16,er2),@(0xffff9abc:16,er3.l) ;0108c2f312349abc + mov.l @(0x1234:16,er2),@(0x9abcdef0:32,r3l.b) ;0108c2db12349abcdef0 + mov.l @(0x1234:16,er2),@(0x9abcdef0:32,r3.w) ;0108c2eb12349abcdef0 + mov.l @(0x1234:16,er2),@(0x9abcdef0:32,er3.l) ;0108c2fb12349abcdef0 + mov.l @(0x1234:16,er2),@0xffff9abc:16 ;0108c24012349abc + mov.l @(0x1234:16,er2),@0x9abcdef0:32 ;0108c24812349abcdef0 + + mov.l @(0x12345678:32,er2),@er1 ;0108ca0112345678 + mov.l @(0x12345678:32,er2),@(0x4:2,er1) ;0108ca1112345678 + mov.l @(0x12345678:32,er2),@er1+ ;0108ca8112345678 + mov.l @(0x12345678:32,er2),@-er1 ;0108cab112345678 + mov.l @(0x12345678:32,er2),@+er1 ;0108ca9112345678 + mov.l @(0x12345678:32,er2),@er1- ;0108caa112345678 + mov.l @(0x12345678:32,er2),@(0xffff9abc:16,er1) ;0108cac1123456789abc + mov.l @(0x12345678:32,er2),@(0x9abcdef0:32,er1) ;0108cac9123456789abcdef0 + mov.l @(0x12345678:32,er2),@(0xffff9abc:16,r3l.b) ;0108cad3123456789abc + mov.l @(0x12345678:32,er2),@(0xffff9abc:16,r3.w) ;0108cae3123456789abc + mov.l @(0x12345678:32,er2),@(0xffff9abc:16,er3.l) ;0108caf3123456789abc + mov.l @(0x12345678:32,er2),@(0x9abcdef0:32,r3l.b) ;0108cadb123456789abcdef0 + mov.l @(0x12345678:32,er2),@(0x9abcdef0:32,r3.w) ;0108caeb123456789abcdef0 + mov.l @(0x12345678:32,er2),@(0x9abcdef0:32,er3.l) ;0108cafb123456789abcdef0 + mov.l @(0x12345678:32,er2),@0xffff9abc:16 ;0108ca40123456789abc + mov.l @(0x12345678:32,er2),@0x9abcdef0:32 ;0108ca48123456789abcdef0 + + mov.l @(0x1234:16,r3l.b),@er1 ;0108d3011234 + mov.l @(0x1234:16,r3l.b),@(0x4:2,er1) ;0108d3111234 + mov.l @(0x1234:16,r3l.b),@er1+ ;0108d3811234 + mov.l @(0x1234:16,r3l.b),@-er1 ;0108d3b11234 + mov.l @(0x1234:16,r3l.b),@+er1 ;0108d3911234 + mov.l @(0x1234:16,r3l.b),@er1- ;0108d3a11234 + mov.l @(0x1234:16,r3l.b),@(0xffff9abc:16,er1) ;0108d3c112349abc + mov.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1) ;0108d3c912349abcdef0 + mov.l @(0x1234:16,r3l.b),@(0xffff9abc:16,r3l.b) ;0108d3d312349abc + mov.l @(0x1234:16,r3l.b),@(0xffff9abc:16,r3.w) ;0108d3e312349abc + mov.l @(0x1234:16,r3l.b),@(0xffff9abc:16,er3.l) ;0108d3f312349abc + mov.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,r3l.b) ;0108d3db12349abcdef0 + mov.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,r3.w) ;0108d3eb12349abcdef0 + mov.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,er3.l) ;0108d3fb12349abcdef0 + mov.l @(0x1234:16,r3l.b),@0xffff9abc:16 ;0108d34012349abc + mov.l @(0x1234:16,r3l.b),@0x9abcdef0:32 ;0108d34812349abcdef0 + + mov.l @(0x1234:16,r3.w),@er1 ;0108e3011234 + mov.l @(0x1234:16,r3.w),@(0x4:2,er1) ;0108e3111234 + mov.l @(0x1234:16,r3.w),@er1+ ;0108e3811234 + mov.l @(0x1234:16,r3.w),@-er1 ;0108e3b11234 + mov.l @(0x1234:16,r3.w),@+er1 ;0108e3911234 + mov.l @(0x1234:16,r3.w),@er1- ;0108e3a11234 + mov.l @(0x1234:16,r3.w),@(0xffff9abc:16,er1) ;0108e3c112349abc + mov.l @(0x1234:16,r3.w),@(0x9abcdef0:32,er1) ;0108e3c912349abcdef0 + mov.l @(0x1234:16,r3.w),@(0xffff9abc:16,r3l.b) ;0108e3d312349abc + mov.l @(0x1234:16,r3.w),@(0xffff9abc:16,r3.w) ;0108e3e312349abc + mov.l @(0x1234:16,r3.w),@(0xffff9abc:16,er3.l) ;0108e3f312349abc + mov.l @(0x1234:16,r3.w),@(0x9abcdef0:32,r3l.b) ;0108e3db12349abcdef0 + mov.l @(0x1234:16,r3.w),@(0x9abcdef0:32,r3.w) ;0108e3eb12349abcdef0 + mov.l @(0x1234:16,r3.w),@(0x9abcdef0:32,er3.l) ;0108e3fb12349abcdef0 + mov.l @(0x1234:16,r3.w),@0xffff9abc:16 ;0108e34012349abc + mov.l @(0x1234:16,r3.w),@0x9abcdef0:32 ;0108e34812349abcdef0 + + mov.l @(0x1234:16,er3.l),@er1 ;0108f3011234 + mov.l @(0x1234:16,er3.l),@(0x4:2,er1) ;0108f3111234 + mov.l @(0x1234:16,er3.l),@er1+ ;0108f3811234 + mov.l @(0x1234:16,er3.l),@-er1 ;0108f3b11234 + mov.l @(0x1234:16,er3.l),@+er1 ;0108f3911234 + mov.l @(0x1234:16,er3.l),@er1- ;0108f3a11234 + mov.l @(0x1234:16,er3.l),@(0xffff9abc:16,er1) ;0108f3c112349abc + mov.l @(0x1234:16,er3.l),@(0x9abcdef0:32,er1) ;0108f3c912349abcdef0 + mov.l @(0x1234:16,er3.l),@(0xffff9abc:16,r3l.b) ;0108f3d312349abc + mov.l @(0x1234:16,er3.l),@(0xffff9abc:16,r3.w) ;0108f3e312349abc + mov.l @(0x1234:16,er3.l),@(0xffff9abc:16,er3.l) ;0108f3f312349abc + mov.l @(0x1234:16,er3.l),@(0x9abcdef0:32,r3l.b) ;0108f3db12349abcdef0 + mov.l @(0x1234:16,er3.l),@(0x9abcdef0:32,r3.w) ;0108f3eb12349abcdef0 + mov.l @(0x1234:16,er3.l),@(0x9abcdef0:32,er3.l) ;0108f3fb12349abcdef0 + mov.l @(0x1234:16,er3.l),@0xffff9abc:16 ;0108f34012349abc + mov.l @(0x1234:16,er3.l),@0x9abcdef0:32 ;0108f34812349abcdef0 + + mov.l @(0x12345678:32,r3l.b),@er1 ;0108db0112345678 + mov.l @(0x12345678:32,r3l.b),@(0x4:2,er1) ;0108db1112345678 + mov.l @(0x12345678:32,r3l.b),@er1+ ;0108db8112345678 + mov.l @(0x12345678:32,r3l.b),@-er1 ;0108dbb112345678 + mov.l @(0x12345678:32,r3l.b),@+er1 ;0108db9112345678 + mov.l @(0x12345678:32,r3l.b),@er1- ;0108dba112345678 + mov.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,er1) ;0108dbc1123456789abc + mov.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1) ;0108dbc9123456789abcdef0 + mov.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,r3l.b) ;0108dbd3123456789abc + mov.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,r3.w) ;0108dbe3123456789abc + mov.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,er3.l) ;0108dbf3123456789abc + mov.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r3l.b) ;0108dbdb123456789abcdef0 + mov.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r3.w) ;0108dbeb123456789abcdef0 + mov.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er3.l) ;0108dbfb123456789abcdef0 + mov.l @(0x12345678:32,r3l.b),@0xffff9abc:16 ;0108db40123456789abc + mov.l @(0x12345678:32,r3l.b),@0x9abcdef0:32 ;0108db48123456789abcdef0 + + mov.l @(0x12345678:32,r3.w),@er1 ;0108eb0112345678 + mov.l @(0x12345678:32,r3.w),@(0x4:2,er1) ;0108eb1112345678 + mov.l @(0x12345678:32,r3.w),@er1+ ;0108eb8112345678 + mov.l @(0x12345678:32,r3.w),@-er1 ;0108ebb112345678 + mov.l @(0x12345678:32,r3.w),@+er1 ;0108eb9112345678 + mov.l @(0x12345678:32,r3.w),@er1- ;0108eba112345678 + mov.l @(0x12345678:32,r3.w),@(0xffff9abc:16,er1) ;0108ebc1123456789abc + mov.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1) ;0108ebc9123456789abcdef0 + mov.l @(0x12345678:32,r3.w),@(0xffff9abc:16,r3l.b) ;0108ebd3123456789abc + mov.l @(0x12345678:32,r3.w),@(0xffff9abc:16,r3.w) ;0108ebe3123456789abc + mov.l @(0x12345678:32,r3.w),@(0xffff9abc:16,er3.l) ;0108ebf3123456789abc + mov.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,r3l.b) ;0108ebdb123456789abcdef0 + mov.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,r3.w) ;0108ebeb123456789abcdef0 + mov.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,er3.l) ;0108ebfb123456789abcdef0 + mov.l @(0x12345678:32,r3.w),@0xffff9abc:16 ;0108eb40123456789abc + mov.l @(0x12345678:32,r3.w),@0x9abcdef0:32 ;0108eb48123456789abcdef0 + + mov.l @(0x12345678:32,er3.l),@er1 ;0108fb0112345678 + mov.l @(0x12345678:32,er3.l),@(0x4:2,er1) ;0108fb1112345678 + mov.l @(0x12345678:32,er3.l),@er1+ ;0108fb8112345678 + mov.l @(0x12345678:32,er3.l),@-er1 ;0108fbb112345678 + mov.l @(0x12345678:32,er3.l),@+er1 ;0108fb9112345678 + mov.l @(0x12345678:32,er3.l),@er1- ;0108fba112345678 + mov.l @(0x12345678:32,er3.l),@(0xffff9abc:16,er1) ;0108fbc1123456789abc + mov.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1) ;0108fbc9123456789abcdef0 + mov.l @(0x12345678:32,er3.l),@(0xffff9abc:16,r3l.b) ;0108fbd3123456789abc + mov.l @(0x12345678:32,er3.l),@(0xffff9abc:16,r3.w) ;0108fbe3123456789abc + mov.l @(0x12345678:32,er3.l),@(0xffff9abc:16,er3.l) ;0108fbf3123456789abc + mov.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,r3l.b) ;0108fbdb123456789abcdef0 + mov.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,r3.w) ;0108fbeb123456789abcdef0 + mov.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,er3.l) ;0108fbfb123456789abcdef0 + mov.l @(0x12345678:32,er3.l),@0xffff9abc:16 ;0108fb40123456789abc + mov.l @(0x12345678:32,er3.l),@0x9abcdef0:32 ;0108fb48123456789abcdef0 + + mov.l @0x1234:16,@er1 ;010840011234 + mov.l @0x1234:16,@(0x4:2,er1) ;010840111234 + mov.l @0x1234:16,@er1+ ;010840811234 + mov.l @0x1234:16,@-er1 ;010840b11234 + mov.l @0x1234:16,@+er1 ;010840911234 + mov.l @0x1234:16,@er1- ;010840a11234 + mov.l @0x1234:16,@(0xffff9abc:16,er1) ;010840c112349abc + mov.l @0x1234:16,@(0x9abcdef0:32,er1) ;010840c912349abcdef0 + mov.l @0x1234:16,@(0xffff9abc:16,r3l.b) ;010840d312349abc + mov.l @0x1234:16,@(0xffff9abc:16,r3.w) ;010840e312349abc + mov.l @0x1234:16,@(0xffff9abc:16,er3.l) ;010840f312349abc + mov.l @0x1234:16,@(0x9abcdef0:32,r3l.b) ;010840db12349abcdef0 + mov.l @0x1234:16,@(0x9abcdef0:32,r3.w) ;010840eb12349abcdef0 + mov.l @0x1234:16,@(0x9abcdef0:32,er3.l) ;010840fb12349abcdef0 + mov.l @0x1234:16,@0xffff9abc:16 ;0108404012349abc + mov.l @0x1234:16,@0x9abcdef0:32 ;0108404812349abcdef0 + + mov.l @0x12345678:32,@er1 ;0108480112345678 + mov.l @0x12345678:32,@(0x4:2,er1) ;0108481112345678 + mov.l @0x12345678:32,@er1+ ;0108488112345678 + mov.l @0x12345678:32,@-er1 ;010848b112345678 + mov.l @0x12345678:32,@+er1 ;0108489112345678 + mov.l @0x12345678:32,@er1- ;010848a112345678 + mov.l @0x12345678:32,@(0xffff9abc:16,er1) ;010848c1123456789abc + mov.l @0x12345678:32,@(0x9abcdef0:32,er1) ;010848c9123456789abcdef0 + mov.l @0x12345678:32,@(0xffff9abc:16,r3l.b) ;010848d3123456789abc + mov.l @0x12345678:32,@(0xffff9abc:16,r3.w) ;010848e3123456789abc + mov.l @0x12345678:32,@(0xffff9abc:16,er3.l) ;010848f3123456789abc + mov.l @0x12345678:32,@(0x9abcdef0:32,r3l.b) ;010848db123456789abcdef0 + mov.l @0x12345678:32,@(0x9abcdef0:32,r3.w) ;010848eb123456789abcdef0 + mov.l @0x12345678:32,@(0x9abcdef0:32,er3.l) ;010848fb123456789abcdef0 + mov.l @0x12345678:32,@0xffff9abc:16 ;01084840123456789abc + mov.l @0x12345678:32,@0x9abcdef0:32 ;01084848123456789abcdef0 + + movtpe.b r2h,@0x1234:16 ;6ac21234 + movfpe.b @0x1234:16,r1h ;6a411234 + + ldm @sp+,(er0-er1) ;01106d71 + ldm @sp+,(er1-er2) ;01106d72 + ldm @sp+,(er2-er3) ;01106d73 + ldm @sp+,(er3-er4) ;01106d74 + ldm @sp+,(er4-er5) ;01106d75 + ldm @sp+,(er5-er6) ;01106d76 + ldm @sp+,(er6-er7) ;01106d77 + + ldm @sp+,(er0-er2) ;01206d72 + ldm @sp+,(er1-er3) ;01206d73 + ldm @sp+,(er2-er4) ;01206d74 + ldm @sp+,(er3-er5) ;01206d75 + ldm @sp+,(er4-er6) ;01206d76 + ldm @sp+,(er5-er7) ;01206d77 + + ldm @sp+,(er0-er3) ;01306d73 + ldm @sp+,(er1-er4) ;01306d74 + ldm @sp+,(er2-er5) ;01306d75 + ldm @sp+,(er3-er6) ;01306d76 + ldm @sp+,(er4-er7) ;01306d77 + + stm (er0-er1),@-sp ;01106df0 + stm (er1-er2),@-sp ;01106df1 + stm (er2-er3),@-sp ;01106df2 + stm (er3-er4),@-sp ;01106df3 + stm (er4-er5),@-sp ;01106df4 + stm (er5-er6),@-sp ;01106df5 + stm (er6-er7),@-sp ;01106df6 + + stm (er0-er2),@-sp ;01206df0 + stm (er1-er3),@-sp ;01206df1 + stm (er2-er4),@-sp ;01206df2 + stm (er3-er5),@-sp ;01206df3 + stm (er4-er6),@-sp ;01206df4 + stm (er5-er7),@-sp ;01206df5 + + stm (er0-er3),@-sp ;01306df0 + stm (er1-er4),@-sp ;01306df1 + stm (er2-er5),@-sp ;01306df2 + stm (er3-er6),@-sp ;01306df3 + stm (er4-er7),@-sp ;01306df4 + + eepmov.b ;7b5c598f + + eepmov.w ;7bd4598f + + movmd.b ;7b94 + movmd.w ;7ba4 + movmd.l ;7bb4 + movsd.b label ;7b840004 + nop ;0000 + nop ;0000 +label: + + .end + diff --git a/gdb/testsuite/gdb.disasm/t02_mova.exp b/gdb/testsuite/gdb.disasm/t02_mova.exp new file mode 100644 index 0000000..899bbfd --- /dev/null +++ b/gdb/testsuite/gdb.disasm/t02_mova.exp @@ -0,0 +1,486 @@ +# Copyright (C) 2003 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# Please email any bugs, comments, and/or additions to this file to: +# bug-gdb@prep.ai.mit.edu + +# This file was written by Michael Snyder (msnyder@redhat.com) + +if $tracelevel then { + strace $tracelevel +} + +if ![istarget "h8300*-*-*"] { + verbose "Tests ignored for all but h8300s based targets." + return +} + +set prms_id 0 +set bug_id 0 + +set testfile "t02_mova" +set srcfile ${srcdir}/${subdir}/${testfile}.s +set objfile ${objdir}/${subdir}/${testfile}.o +set binfile ${objdir}/${subdir}/${testfile}.x + +set asm-flags ""; +set link-flags "-m h8300sxelf"; + + +if {[target_assemble $srcfile $objfile "${asm-flags}"] != ""} then { + gdb_suppress_entire_file "Testcase assembly failed, so all tests in this file will automatically fail." +} + +if {[target_link $objfile $binfile "${link-flags}"] != ""} then { + gdb_suppress_entire_file "Testcase link failed, so all tests in this file will automatically fail." +} + +gdb_start +gdb_reinitialize_dir $srcdir/$subdir +gdb_load $binfile + +gdb_test "x /i _start" "mova/b.l\t@\\(0x1234(:16|),r3l.b\\),er1" \ + "mova/b.c @(0x1234:16,r3l.b),er1" +gdb_test "x" "mova/b.l\t@\\(0x1234(:16|),r3.w\\),er1" \ + "mova/b.c @(0x1234:16,r3.w),er1" +gdb_test "x" "mova/w.l\t@\\(0x1234(:16|),r3l.b\\),er1" \ + "mova/w.c @(0x1234:16,r3l.b),er1" +gdb_test "x" "mova/w.l\t@\\(0x1234(:16|),r3.w\\),er1" \ + "mova/w.c @(0x1234:16,r3.w),er1" +gdb_test "x" "mova/l.l\t@\\(0x1234(:16|),r3l.b\\),er1" \ + "mova/l.c @(0x1234:16,r3l.b),er1" +gdb_test "x" "mova/l.l\t@\\(0x1234(:16|),r3.w\\),er1" \ + "mova/l.c @(0x1234:16,r3.w),er1" +gdb_test "x" "mova/b.l\t@\\(0x12345678(:32|),r3l.b\\),er1" \ + "mova/b.c @(0x12345678:32,r3l.b),er1" +gdb_test "x" "mova/b.l\t@\\(0x12345678(:32|),r3.w\\),er1" \ + "mova/b.c @(0x12345678:32,r3.w),er1" +gdb_test "x" "mova/w.l\t@\\(0x12345678(:32|),r3l.b\\),er1" \ + "mova/w.c @(0x12345678:32,r3l.b),er1" +gdb_test "x" "mova/w.l\t@\\(0x12345678(:32|),r3.w\\),er1" \ + "mova/w.c @(0x12345678:32,r3.w),er1" +gdb_test "x" "mova/l.l\t@\\(0x12345678(:32|),r3l.b\\),er1" \ + "mova/l.c @(0x12345678:32,r3l.b),er1" +gdb_test "x" "mova/l.l\t@\\(0x12345678(:32|),r3.w\\),er1" \ + "mova/l.c @(0x12345678:32,r3.w),er1" +gdb_test "x" "mova/b.l\t@\\(0x1234(:16|),r3l.b\\),er1" \ + "mova/b.l @(0x1234:16,r3l.b),er1" +gdb_test "x" "mova/b.l\t@\\(0x1234(:16|),r3.w\\),er1" \ + "mova/b.l @(0x1234:16,r3.w),er1" +gdb_test "x" "mova/w.l\t@\\(0x1234(:16|),r3l.b\\),er1" \ + "mova/w.l @(0x1234:16,r3l.b),er1" +gdb_test "x" "mova/w.l\t@\\(0x1234(:16|),r3.w\\),er1" \ + "mova/w.l @(0x1234:16,r3.w),er1" +gdb_test "x" "mova/l.l\t@\\(0x1234(:16|),r3l.b\\),er1" \ + "mova/l.l @(0x1234:16,r3l.b),er1" +gdb_test "x" "mova/l.l\t@\\(0x1234(:16|),r3.w\\),er1" \ + "mova/l.l @(0x1234:16,r3.w),er1" +gdb_test "x" "mova/b.l\t@\\(0x12345678(:32|),r3l.b\\),er1" \ + "mova/b.l @(0x12345678:32,r3l.b),er1" +gdb_test "x" "mova/b.l\t@\\(0x12345678(:32|),r3.w\\),er1" \ + "mova/b.l @(0x12345678:32,r3.w),er1" +gdb_test "x" "mova/w.l\t@\\(0x12345678(:32|),r3l.b\\),er1" \ + "mova/w.l @(0x12345678:32,r3l.b),er1" +gdb_test "x" "mova/w.l\t@\\(0x12345678(:32|),r3.w\\),er1" \ + "mova/w.l @(0x12345678:32,r3.w),er1" +gdb_test "x" "mova/l.l\t@\\(0x12345678(:32|),r3l.b\\),er1" \ + "mova/l.l @(0x12345678:32,r3l.b),er1" +gdb_test "x" "mova/l.l\t@\\(0x12345678(:32|),r3.w\\),er1" \ + "mova/l.l @(0x12345678:32,r3.w),er1" +gdb_test "x" "mova/b.l\t@\\(0x1234(:16|),@er2.b\\),er1" \ + "mova/b.l @(0x1234:16,@er2.b),er1" +gdb_test "x" "mova/b.l\t@\\(0x1234(:16|),@\\(0x1(:2|),er2\\).b\\),er1" \ + "mova/b.l @(0x1234:16,@(0x1:2,er2).b),er1" +gdb_test "x" "mova/b.l\t@\\(0x1234(:16|),@er2\\+.b\\),er1" \ + "mova/b.l @(0x1234:16,@er2+.b),er1" +gdb_test "x" "mova/b.l\t@\\(0x1234(:16|),@-er2.b\\),er1" \ + "mova/b.l @(0x1234:16,@-er2.b),er1" +gdb_test "x" "mova/b.l\t@\\(0x1234(:16|),@\\+er2.b\\),er1" \ + "mova/b.l @(0x1234:16,@+er2.b),er1" +gdb_test "x" "mova/b.l\t@\\(0x1234(:16|),@er2-.b\\),er1" \ + "mova/b.l @(0x1234:16,@er2-.b),er1" +gdb_test "x" "mova/b.l\t@\\(0x1234(:16|),@\\(0x9abc(:16|),er2\\).b\\),er1" \ + "mova/b.l @(0x1234:16,@(0x9abc:16,er2).b),er1" +gdb_test "x" "mova/b.l\t@\\(0x1234(:16|),@\\(0x9abcdef0(:32|),er2\\).b\\),er1" \ + "mova/b.l @(0x1234:16,@(0x9abcdef0:32,er2).b),er1" +gdb_test "x" "mova/b.l\t@\\(0x1234(:16|),@\\(0x9abc(:16|),r2l.b\\).b\\),er1" \ + "mova/b.l @(0x1234:16,@(0x9abc:16,r2l.b).b),er1" +gdb_test "x" "mova/b.l\t@\\(0x1234(:16|),@\\(0x9abc(:16|),r2.w\\).b\\),er1" \ + "mova/b.l @(0x1234:16,@(0x9abc:16,r2.w).b),er1" +gdb_test "x" "mova/b.l\t@\\(0x1234(:16|),@\\(0x9abc(:16|),er2.l\\).b\\),er1" \ + "mova/b.l @(0x1234:16,@(0x9abc:16,er2.l).b),er1" +gdb_test "x" "mova/b.l\t@\\(0x1234(:16|),@\\(0x9abcdef0(:32|),r2l.b\\).b\\),er1" \ + "mova/b.l @(0x1234:16,@(0x9abcdef0:32,r2l.b).b),er1" +gdb_test "x" "mova/b.l\t@\\(0x1234(:16|),@\\(0x9abcdef0(:32|),r2.w\\).b\\),er1" \ + "mova/b.l @(0x1234:16,@(0x9abcdef0:32,r2.w).b),er1" +gdb_test "x" "mova/b.l\t@\\(0x1234(:16|),@\\(0x9abcdef0(:32|),er2.l\\).b\\),er1" \ + "mova/b.l @(0x1234:16,@(0x9abcdef0:32,er2.l).b),er1" +gdb_test "x" "mova/b.l\t@\\(0x1234(:16|),@0x9abc(:16|).b\\),er1" \ + "mova/b.l @(0x1234:16,@0x9abc:16.b),er1" +gdb_test "x" "mova/b.l\t@\\(0x1234(:16|),@0x9abcdef0(:32|).b\\),er1" \ + "mova/b.l @(0x1234:16,@0x9abcdef0:32.b),er1" +gdb_test "x" "mova/b.l\t@\\(0x1234(:16|),@er2.w\\),er1" \ + "mova/b.l @(0x1234:16,@er2.w),er1" +gdb_test "x" "mova/b.l\t@\\(0x1234(:16|),@\\(0x2(:2|),er2\\).w\\),er1" \ + "mova/b.l @(0x1234:16,@(0x2:2,er2).w),er1" +gdb_test "x" "mova/b.l\t@\\(0x1234(:16|),@er2\\+.w\\),er1" \ + "mova/b.l @(0x1234:16,@er2+.w),er1" +gdb_test "x" "mova/b.l\t@\\(0x1234(:16|),@-er2.w\\),er1" \ + "mova/b.l @(0x1234:16,@-er2.w),er1" +gdb_test "x" "mova/b.l\t@\\(0x1234(:16|),@\\+er2.w\\),er1" \ + "mova/b.l @(0x1234:16,@+er2.w),er1" +gdb_test "x" "mova/b.l\t@\\(0x1234(:16|),@er2-.w\\),er1" \ + "mova/b.l @(0x1234:16,@er2-.w),er1" +gdb_test "x" "mova/b.l\t@\\(0x1234(:16|),@\\(0x9abc(:16|),er2\\).w\\),er1" \ + "mova/b.l @(0x1234:16,@(0x9abc:16,er2).w),er1" +gdb_test "x" "mova/b.l\t@\\(0x1234(:16|),@\\(0x9abcdef0(:32|),er2\\).w\\),er1" \ + "mova/b.l @(0x1234:16,@(0x9abcdef0:32,er2).w),er1" +gdb_test "x" "mova/b.l\t@\\(0x1234(:16|),@\\(0x9abc(:16|),r2l.b\\).w\\),er1" \ + "mova/b.l @(0x1234:16,@(0x9abc:16,r2l.b).w),er1" +gdb_test "x" "mova/b.l\t@\\(0x1234(:16|),@\\(0x9abc(:16|),r2.w\\).w\\),er1" \ + "mova/b.l @(0x1234:16,@(0x9abc:16,r2.w).w),er1" +gdb_test "x" "mova/b.l\t@\\(0x1234(:16|),@\\(0x9abc(:16|),er2.l\\).w\\),er1" \ + "mova/b.l @(0x1234:16,@(0x9abc:16,er2.l).w),er1" +gdb_test "x" "mova/b.l\t@\\(0x1234(:16|),@\\(0x9abcdef0(:32|),r2l.b\\).w\\),er1" \ + "mova/b.l @(0x1234:16,@(0x9abcdef0:32,r2l.b).w),er1" +gdb_test "x" "mova/b.l\t@\\(0x1234(:16|),@\\(0x9abcdef0(:32|),r2.w\\).w\\),er1" \ + "mova/b.l @(0x1234:16,@(0x9abcdef0:32,r2.w).w),er1" +gdb_test "x" "mova/b.l\t@\\(0x1234(:16|),@\\(0x9abcdef0(:32|),er2.l\\).w\\),er1" \ + "mova/b.l @(0x1234:16,@(0x9abcdef0:32,er2.l).w),er1" +gdb_test "x" "mova/b.l\t@\\(0x1234(:16|),@0x9abc(:16|).w\\),er1" \ + "mova/b.l @(0x1234:16,@0x9abc:16.w),er1" +gdb_test "x" "mova/b.l\t@\\(0x1234(:16|),@0x9abcdef0(:32|).w\\),er1" \ + "mova/b.l @(0x1234:16,@0x9abcdef0:32.w),er1" +gdb_test "x" "mova/w.l\t@\\(0x1234(:16|),@er2.b\\),er1" \ + "mova/w.l @(0x1234:16,@er2.b),er1" +gdb_test "x" "mova/w.l\t@\\(0x1234(:16|),@\\(0x1(:2|),er2\\).b\\),er1" \ + "mova/w.l @(0x1234:16,@(0x1:2,er2).b),er1" +gdb_test "x" "mova/w.l\t@\\(0x1234(:16|),@er2\\+.b\\),er1" \ + "mova/w.l @(0x1234:16,@er2+.b),er1" +gdb_test "x" "mova/w.l\t@\\(0x1234(:16|),@-er2.b\\),er1" \ + "mova/w.l @(0x1234:16,@-er2.b),er1" +gdb_test "x" "mova/w.l\t@\\(0x1234(:16|),@\\+er2.b\\),er1" \ + "mova/w.l @(0x1234:16,@+er2.b),er1" +gdb_test "x" "mova/w.l\t@\\(0x1234(:16|),@er2-.b\\),er1" \ + "mova/w.l @(0x1234:16,@er2-.b),er1" +gdb_test "x" "mova/w.l\t@\\(0x1234(:16|),@\\(0x9abc(:16|),er2\\).b\\),er1" \ + "mova/w.l @(0x1234:16,@(0x9abc:16,er2).b),er1" +gdb_test "x" "mova/w.l\t@\\(0x1234(:16|),@\\(0x9abcdef0(:32|),er2\\).b\\),er1" \ + "mova/w.l @(0x1234:16,@(0x9abcdef0:32,er2).b),er1" +gdb_test "x" "mova/w.l\t@\\(0x1234(:16|),@\\(0x9abc(:16|),r2l.b\\).b\\),er1" \ + "mova/w.l @(0x1234:16,@(0x9abc:16,r2l.b).b),er1" +gdb_test "x" "mova/w.l\t@\\(0x1234(:16|),@\\(0x9abc(:16|),r2.w\\).b\\),er1" \ + "mova/w.l @(0x1234:16,@(0x9abc:16,r2.w).b),er1" +gdb_test "x" "mova/w.l\t@\\(0x1234(:16|),@\\(0x9abc(:16|),er2.l\\).b\\),er1" \ + "mova/w.l @(0x1234:16,@(0x9abc:16,er2.l).b),er1" +gdb_test "x" "mova/w.l\t@\\(0x1234(:16|),@\\(0x9abcdef0(:32|),r2l.b\\).b\\),er1" \ + "mova/w.l @(0x1234:16,@(0x9abcdef0:32,r2l.b).b),er1" +gdb_test "x" "mova/w.l\t@\\(0x1234(:16|),@\\(0x9abcdef0(:32|),r2.w\\).b\\),er1" \ + "mova/w.l @(0x1234:16,@(0x9abcdef0:32,r2.w).b),er1" +gdb_test "x" "mova/w.l\t@\\(0x1234(:16|),@\\(0x9abcdef0(:32|),er2.l\\).b\\),er1" \ + "mova/w.l @(0x1234:16,@(0x9abcdef0:32,er2.l).b),er1" +gdb_test "x" "mova/w.l\t@\\(0x1234(:16|),@0x9abc(:16|).b\\),er1" \ + "mova/w.l @(0x1234:16,@0x9abc:16.b),er1" +gdb_test "x" "mova/w.l\t@\\(0x1234(:16|),@0x9abcdef0(:32|).b\\),er1" \ + "mova/w.l @(0x1234:16,@0x9abcdef0:32.b),er1" +gdb_test "x" "mova/w.l\t@\\(0x1234(:16|),@er2.w\\),er1" \ + "mova/w.l @(0x1234:16,@er2.w),er1" +gdb_test "x" "mova/w.l\t@\\(0x1234(:16|),@\\(0x2(:2|),er2\\).w\\),er1" \ + "mova/w.l @(0x1234:16,@(0x2:2,er2).w),er1" +gdb_test "x" "mova/w.l\t@\\(0x1234(:16|),@er2\\+.w\\),er1" \ + "mova/w.l @(0x1234:16,@er2+.w),er1" +gdb_test "x" "mova/w.l\t@\\(0x1234(:16|),@-er2.w\\),er1" \ + "mova/w.l @(0x1234:16,@-er2.w),er1" +gdb_test "x" "mova/w.l\t@\\(0x1234(:16|),@\\+er2.w\\),er1" \ + "mova/w.l @(0x1234:16,@+er2.w),er1" +gdb_test "x" "mova/w.l\t@\\(0x1234(:16|),@er2-.w\\),er1" \ + "mova/w.l @(0x1234:16,@er2-.w),er1" +gdb_test "x" "mova/w.l\t@\\(0x1234(:16|),@\\(0x9abc(:16|),er2\\).w\\),er1" \ + "mova/w.l @(0x1234:16,@(0x9abc:16,er2).w),er1" +gdb_test "x" "mova/w.l\t@\\(0x1234(:16|),@\\(0x9abcdef0(:32|),er2\\).w\\),er1" \ + "mova/w.l @(0x1234:16,@(0x9abcdef0:32,er2).w),er1" +gdb_test "x" "mova/w.l\t@\\(0x1234(:16|),@\\(0x9abc(:16|),r2l.b\\).w\\),er1" \ + "mova/w.l @(0x1234:16,@(0x9abc:16,r2l.b).w),er1" +gdb_test "x" "mova/w.l\t@\\(0x1234(:16|),@\\(0x9abc(:16|),r2.w\\).w\\),er1" \ + "mova/w.l @(0x1234:16,@(0x9abc:16,r2.w).w),er1" +gdb_test "x" "mova/w.l\t@\\(0x1234(:16|),@\\(0x9abc(:16|),er2.l\\).w\\),er1" \ + "mova/w.l @(0x1234:16,@(0x9abc:16,er2.l).w),er1" +gdb_test "x" "mova/w.l\t@\\(0x1234(:16|),@\\(0x9abcdef0(:32|),r2l.b\\).w\\),er1" \ + "mova/w.l @(0x1234:16,@(0x9abcdef0:32,r2l.b).w),er1" +gdb_test "x" "mova/w.l\t@\\(0x1234(:16|),@\\(0x9abcdef0(:32|),r2.w\\).w\\),er1" \ + "mova/w.l @(0x1234:16,@(0x9abcdef0:32,r2.w).w),er1" +gdb_test "x" "mova/w.l\t@\\(0x1234(:16|),@\\(0x9abcdef0(:32|),er2.l\\).w\\),er1" \ + "mova/w.l @(0x1234:16,@(0x9abcdef0:32,er2.l).w),er1" +gdb_test "x" "mova/w.l\t@\\(0x1234(:16|),@0x9abc(:16|).w\\),er1" \ + "mova/w.l @(0x1234:16,@0x9abc:16.w),er1" +gdb_test "x" "mova/w.l\t@\\(0x1234(:16|),@0x9abcdef0(:32|).w\\),er1" \ + "mova/w.l @(0x1234:16,@0x9abcdef0:32.w),er1" +gdb_test "x" "mova/l.l\t@\\(0x1234(:16|),@er2.b\\),er1" \ + "mova/l.l @(0x1234:16,@er2.b),er1" +gdb_test "x" "mova/l.l\t@\\(0x1234(:16|),@\\(0x1(:2|),er2\\).b\\),er1" \ + "mova/l.l @(0x1234:16,@(0x1:2,er2).b),er1" +gdb_test "x" "mova/l.l\t@\\(0x1234(:16|),@er2\\+.b\\),er1" \ + "mova/l.l @(0x1234:16,@er2+.b),er1" +gdb_test "x" "mova/l.l\t@\\(0x1234(:16|),@-er2.b\\),er1" \ + "mova/l.l @(0x1234:16,@-er2.b),er1" +gdb_test "x" "mova/l.l\t@\\(0x1234(:16|),@\\+er2.b\\),er1" \ + "mova/l.l @(0x1234:16,@+er2.b),er1" +gdb_test "x" "mova/l.l\t@\\(0x1234(:16|),@er2-.b\\),er1" \ + "mova/l.l @(0x1234:16,@er2-.b),er1" +gdb_test "x" "mova/l.l\t@\\(0x1234(:16|),@\\(0x9abc(:16|),er2\\).b\\),er1" \ + "mova/l.l @(0x1234:16,@(0x9abc:16,er2).b),er1" +gdb_test "x" "mova/l.l\t@\\(0x1234(:16|),@\\(0x9abcdef0(:32|),er2\\).b\\),er1" \ + "mova/l.l @(0x1234:16,@(0x9abcdef0:32,er2).b),er1" +gdb_test "x" "mova/l.l\t@\\(0x1234(:16|),@\\(0x9abc(:16|),r2l.b\\).b\\),er1" \ + "mova/l.l @(0x1234:16,@(0x9abc:16,r2l.b).b),er1" +gdb_test "x" "mova/l.l\t@\\(0x1234(:16|),@\\(0x9abc(:16|),r2.w\\).b\\),er1" \ + "mova/l.l @(0x1234:16,@(0x9abc:16,r2.w).b),er1" +gdb_test "x" "mova/l.l\t@\\(0x1234(:16|),@\\(0x9abc(:16|),er2.l\\).b\\),er1" \ + "mova/l.l @(0x1234:16,@(0x9abc:16,er2.l).b),er1" +gdb_test "x" "mova/l.l\t@\\(0x1234(:16|),@\\(0x9abcdef0(:32|),r2l.b\\).b\\),er1" \ + "mova/l.l @(0x1234:16,@(0x9abcdef0:32,r2l.b).b),er1" +gdb_test "x" "mova/l.l\t@\\(0x1234(:16|),@\\(0x9abcdef0(:32|),r2.w\\).b\\),er1" \ + "mova/l.l @(0x1234:16,@(0x9abcdef0:32,r2.w).b),er1" +gdb_test "x" "mova/l.l\t@\\(0x1234(:16|),@\\(0x9abcdef0(:32|),er2.l\\).b\\),er1" \ + "mova/l.l @(0x1234:16,@(0x9abcdef0:32,er2.l).b),er1" +gdb_test "x" "mova/l.l\t@\\(0x1234(:16|),@0x9abc(:16|).b\\),er1" \ + "mova/l.l @(0x1234:16,@0x9abc:16.b),er1" +gdb_test "x" "mova/l.l\t@\\(0x1234(:16|),@0x9abcdef0(:32|).b\\),er1" \ + "mova/l.l @(0x1234:16,@0x9abcdef0:32.b),er1" +gdb_test "x" "mova/l.l\t@\\(0x1234(:16|),@er2.w\\),er1" \ + "mova/l.l @(0x1234:16,@er2.w),er1" +gdb_test "x" "mova/l.l\t@\\(0x1234(:16|),@\\(0x2(:2|),er2\\).w\\),er1" \ + "mova/l.l @(0x1234:16,@(0x2:2,er2).w),er1" +gdb_test "x" "mova/l.l\t@\\(0x1234(:16|),@er2\\+.w\\),er1" \ + "mova/l.l @(0x1234:16,@er2+.w),er1" +gdb_test "x" "mova/l.l\t@\\(0x1234(:16|),@-er2.w\\),er1" \ + "mova/l.l @(0x1234:16,@-er2.w),er1" +gdb_test "x" "mova/l.l\t@\\(0x1234(:16|),@\\+er2.w\\),er1" \ + "mova/l.l @(0x1234:16,@+er2.w),er1" +gdb_test "x" "mova/l.l\t@\\(0x1234(:16|),@er2-.w\\),er1" \ + "mova/l.l @(0x1234:16,@er2-.w),er1" +gdb_test "x" "mova/l.l\t@\\(0x1234(:16|),@\\(0x9abc(:16|),er2\\).w\\),er1" \ + "mova/l.l @(0x1234:16,@(0x9abc:16,er2).w),er1" +gdb_test "x" "mova/l.l\t@\\(0x1234(:16|),@\\(0x9abcdef0(:32|),er2\\).w\\),er1" \ + "mova/l.l @(0x1234:16,@(0x9abcdef0:32,er2).w),er1" +gdb_test "x" "mova/l.l\t@\\(0x1234(:16|),@\\(0x9abc(:16|),r2l.b\\).w\\),er1" \ + "mova/l.l @(0x1234:16,@(0x9abc:16,r2l.b).w),er1" +gdb_test "x" "mova/l.l\t@\\(0x1234(:16|),@\\(0x9abc(:16|),r2.w\\).w\\),er1" \ + "mova/l.l @(0x1234:16,@(0x9abc:16,r2.w).w),er1" +gdb_test "x" "mova/l.l\t@\\(0x1234(:16|),@\\(0x9abc(:16|),er2.l\\).w\\),er1" \ + "mova/l.l @(0x1234:16,@(0x9abc:16,er2.l).w),er1" +gdb_test "x" "mova/l.l\t@\\(0x1234(:16|),@\\(0x9abcdef0(:32|),r2l.b\\).w\\),er1" \ + "mova/l.l @(0x1234:16,@(0x9abcdef0:32,r2l.b).w),er1" +gdb_test "x" "mova/l.l\t@\\(0x1234(:16|),@\\(0x9abcdef0(:32|),r2.w\\).w\\),er1" \ + "mova/l.l @(0x1234:16,@(0x9abcdef0:32,r2.w).w),er1" +gdb_test "x" "mova/l.l\t@\\(0x1234(:16|),@\\(0x9abcdef0(:32|),er2.l\\).w\\),er1" \ + "mova/l.l @(0x1234:16,@(0x9abcdef0:32,er2.l).w),er1" +gdb_test "x" "mova/l.l\t@\\(0x1234(:16|),@0x9abc(:16|).w\\),er1" \ + "mova/l.l @(0x1234:16,@0x9abc:16.w),er1" +gdb_test "x" "mova/l.l\t@\\(0x1234(:16|),@0x9abcdef0(:32|).w\\),er1" \ + "mova/l.l @(0x1234:16,@0x9abcdef0:32.w),er1" +gdb_test "x" "mova/b.l\t@\\(0x12345678(:32|),@er2.b\\),er1" \ + "mova/b.l @(0x12345678:32,@er2.b),er1" +gdb_test "x" "mova/b.l\t@\\(0x12345678(:32|),@\\(0x1(:2|),er2\\).b\\),er1" \ + "mova/b.l @(0x12345678:32,@(0x1:2,er2).b),er1" +gdb_test "x" "mova/b.l\t@\\(0x12345678(:32|),@er2\\+.b\\),er1" \ + "mova/b.l @(0x12345678:32,@er2+.b),er1" +gdb_test "x" "mova/b.l\t@\\(0x12345678(:32|),@-er2.b\\),er1" \ + "mova/b.l @(0x12345678:32,@-er2.b),er1" +gdb_test "x" "mova/b.l\t@\\(0x12345678(:32|),@\\+er2.b\\),er1" \ + "mova/b.l @(0x12345678:32,@+er2.b),er1" +gdb_test "x" "mova/b.l\t@\\(0x12345678(:32|),@er2-.b\\),er1" \ + "mova/b.l @(0x12345678:32,@er2-.b),er1" +gdb_test "x" "mova/b.l\t@\\(0x12345678(:32|),@\\(0x9abc(:16|),er2\\).b\\),er1" \ + "mova/b.l @(0x12345678:32,@(0x9abc:16,er2).b),er1" +gdb_test "x" "mova/b.l\t@\\(0x12345678(:32|),@\\(0x9abcdef0(:32|),er2\\).b\\),er1" \ + "mova/b.l @(0x12345678:32,@(0x9abcdef0:32,er2).b),er1" +gdb_test "x" "mova/b.l\t@\\(0x12345678(:32|),@\\(0x9abc(:16|),r2l.b\\).b\\),er1" \ + "mova/b.l @(0x12345678:32,@(0x9abc:16,r2l.b).b),er1" +gdb_test "x" "mova/b.l\t@\\(0x12345678(:32|),@\\(0x9abc(:16|),r2.w\\).b\\),er1" \ + "mova/b.l @(0x12345678:32,@(0x9abc:16,r2.w).b),er1" +gdb_test "x" "mova/b.l\t@\\(0x12345678(:32|),@\\(0x9abc(:16|),er2.l\\).b\\),er1" \ + "mova/b.l @(0x12345678:32,@(0x9abc:16,er2.l).b),er1" +gdb_test "x" "mova/b.l\t@\\(0x12345678(:32|),@\\(0x9abcdef0(:32|),r2l.b\\).b\\),er1" \ + "mova/b.l @(0x12345678:32,@(0x9abcdef0:32,r2l.b).b),er1" +gdb_test "x" "mova/b.l\t@\\(0x12345678(:32|),@\\(0x9abcdef0(:32|),r2.w\\).b\\),er1" \ + "mova/b.l @(0x12345678:32,@(0x9abcdef0:32,r2.w).b),er1" +gdb_test "x" "mova/b.l\t@\\(0x12345678(:32|),@\\(0x9abcdef0(:32|),er2.l\\).b\\),er1" \ + "mova/b.l @(0x12345678:32,@(0x9abcdef0:32,er2.l).b),er1" +gdb_test "x" "mova/b.l\t@\\(0x12345678(:32|),@0x9abc(:16|).b\\),er1" \ + "mova/b.l @(0x12345678:32,@0x9abc:16.b),er1" +gdb_test "x" "mova/b.l\t@\\(0x12345678(:32|),@0x9abcdef0(:32|).b\\),er1" \ + "mova/b.l @(0x12345678:32,@0x9abcdef0:32.b),er1" +gdb_test "x" "mova/b.l\t@\\(0x12345678(:32|),@er2.w\\),er1" \ + "mova/b.l @(0x12345678:32,@er2.w),er1" +gdb_test "x" "mova/b.l\t@\\(0x12345678(:32|),@\\(0x2(:2|),er2\\).w\\),er1" \ + "mova/b.l @(0x12345678:32,@(0x2:2,er2).w),er1" +gdb_test "x" "mova/b.l\t@\\(0x12345678(:32|),@er2\\+.w\\),er1" \ + "mova/b.l @(0x12345678:32,@er2+.w),er1" +gdb_test "x" "mova/b.l\t@\\(0x12345678(:32|),@-er2.w\\),er1" \ + "mova/b.l @(0x12345678:32,@-er2.w),er1" +gdb_test "x" "mova/b.l\t@\\(0x12345678(:32|),@\\+er2.w\\),er1" \ + "mova/b.l @(0x12345678:32,@+er2.w),er1" +gdb_test "x" "mova/b.l\t@\\(0x12345678(:32|),@er2-.w\\),er1" \ + "mova/b.l @(0x12345678:32,@er2-.w),er1" +gdb_test "x" "mova/b.l\t@\\(0x12345678(:32|),@\\(0x9abc(:16|),er2\\).w\\),er1" \ + "mova/b.l @(0x12345678:32,@(0x9abc:16,er2).w),er1" +gdb_test "x" "mova/b.l\t@\\(0x12345678(:32|),@\\(0x9abcdef0(:32|),er2\\).w\\),er1" \ + "mova/b.l @(0x12345678:32,@(0x9abcdef0:32,er2).w),er1" +gdb_test "x" "mova/b.l\t@\\(0x12345678(:32|),@\\(0x9abc(:16|),r2l.b\\).w\\),er1" \ + "mova/b.l @(0x12345678:32,@(0x9abc:16,r2l.b).w),er1" +gdb_test "x" "mova/b.l\t@\\(0x12345678(:32|),@\\(0x9abc(:16|),r2.w\\).w\\),er1" \ + "mova/b.l @(0x12345678:32,@(0x9abc:16,r2.w).w),er1" +gdb_test "x" "mova/b.l\t@\\(0x12345678(:32|),@\\(0x9abc(:16|),er2.l\\).w\\),er1" \ + "mova/b.l @(0x12345678:32,@(0x9abc:16,er2.l).w),er1" +gdb_test "x" "mova/b.l\t@\\(0x12345678(:32|),@\\(0x9abcdef0(:32|),r2l.b\\).w\\),er1" \ + "mova/b.l @(0x12345678:32,@(0x9abcdef0:32,r2l.b).w),er1" +gdb_test "x" "mova/b.l\t@\\(0x12345678(:32|),@\\(0x9abcdef0(:32|),r2.w\\).w\\),er1" \ + "mova/b.l @(0x12345678:32,@(0x9abcdef0:32,r2.w).w),er1" +gdb_test "x" "mova/b.l\t@\\(0x12345678(:32|),@\\(0x9abcdef0(:32|),er2.l\\).w\\),er1" \ + "mova/b.l @(0x12345678:32,@(0x9abcdef0:32,er2.l).w),er1" +gdb_test "x" "mova/b.l\t@\\(0x12345678(:32|),@0x9abc(:16|).w\\),er1" \ + "mova/b.l @(0x12345678:32,@0x9abc:16.w),er1" +gdb_test "x" "mova/b.l\t@\\(0x12345678(:32|),@0x9abcdef0(:32|).w\\),er1" \ + "mova/b.l @(0x12345678:32,@0x9abcdef0:32.w),er1" +gdb_test "x" "mova/w.l\t@\\(0x12345678(:32|),@er2.b\\),er1" \ + "mova/w.l @(0x12345678:32,@er2.b),er1" +gdb_test "x" "mova/w.l\t@\\(0x12345678(:32|),@\\(0x1(:2|),er2\\).b\\),er1" \ + "mova/w.l @(0x12345678:32,@(0x1:2,er2).b),er1" +gdb_test "x" "mova/w.l\t@\\(0x12345678(:32|),@er2\\+.b\\),er1" \ + "mova/w.l @(0x12345678:32,@er2+.b),er1" +gdb_test "x" "mova/w.l\t@\\(0x12345678(:32|),@-er2.b\\),er1" \ + "mova/w.l @(0x12345678:32,@-er2.b),er1" +gdb_test "x" "mova/w.l\t@\\(0x12345678(:32|),@\\+er2.b\\),er1" \ + "mova/w.l @(0x12345678:32,@+er2.b),er1" +gdb_test "x" "mova/w.l\t@\\(0x12345678(:32|),@er2-.b\\),er1" \ + "mova/w.l @(0x12345678:32,@er2-.b),er1" +gdb_test "x" "mova/w.l\t@\\(0x12345678(:32|),@\\(0x9abc(:16|),er2\\).b\\),er1" \ + "mova/w.l @(0x12345678:32,@(0x9abc:16,er2).b),er1" +gdb_test "x" "mova/w.l\t@\\(0x12345678(:32|),@\\(0x9abcdef0(:32|),er2\\).b\\),er1" \ + "mova/w.l @(0x12345678:32,@(0x9abcdef0:32,er2).b),er1" +gdb_test "x" "mova/w.l\t@\\(0x12345678(:32|),@\\(0x9abc(:16|),r2l.b\\).b\\),er1" \ + "mova/w.l @(0x12345678:32,@(0x9abc:16,r2l.b).b),er1" +gdb_test "x" "mova/w.l\t@\\(0x12345678(:32|),@\\(0x9abc(:16|),r2.w\\).b\\),er1" \ + "mova/w.l @(0x12345678:32,@(0x9abc:16,r2.w).b),er1" +gdb_test "x" "mova/w.l\t@\\(0x12345678(:32|),@\\(0x9abc(:16|),er2.l\\).b\\),er1" \ + "mova/w.l @(0x12345678:32,@(0x9abc:16,er2.l).b),er1" +gdb_test "x" "mova/w.l\t@\\(0x12345678(:32|),@\\(0x9abcdef0(:32|),r2l.b\\).b\\),er1" \ + "mova/w.l @(0x12345678:32,@(0x9abcdef0:32,r2l.b).b),er1" +gdb_test "x" "mova/w.l\t@\\(0x12345678(:32|),@\\(0x9abcdef0(:32|),r2.w\\).b\\),er1" \ + "mova/w.l @(0x12345678:32,@(0x9abcdef0:32,r2.w).b),er1" +gdb_test "x" "mova/w.l\t@\\(0x12345678(:32|),@\\(0x9abcdef0(:32|),er2.l\\).b\\),er1" \ + "mova/w.l @(0x12345678:32,@(0x9abcdef0:32,er2.l).b),er1" +gdb_test "x" "mova/w.l\t@\\(0x12345678(:32|),@0x9abc(:16|).b\\),er1" \ + "mova/w.l @(0x12345678:32,@0x9abc:16.b),er1" +gdb_test "x" "mova/w.l\t@\\(0x12345678(:32|),@0x9abcdef0(:32|).b\\),er1" \ + "mova/w.l @(0x12345678:32,@0x9abcdef0:32.b),er1" +gdb_test "x" "mova/w.l\t@\\(0x12345678(:32|),@er2.w\\),er1" \ + "mova/w.l @(0x12345678:32,@er2.w),er1" +gdb_test "x" "mova/w.l\t@\\(0x12345678(:32|),@\\(0x2(:2|),er2\\).w\\),er1" \ + "mova/w.l @(0x12345678:32,@(0x2:2,er2).w),er1" +gdb_test "x" "mova/w.l\t@\\(0x12345678(:32|),@er2\\+.w\\),er1" \ + "mova/w.l @(0x12345678:32,@er2+.w),er1" +gdb_test "x" "mova/w.l\t@\\(0x12345678(:32|),@-er2.w\\),er1" \ + "mova/w.l @(0x12345678:32,@-er2.w),er1" +gdb_test "x" "mova/w.l\t@\\(0x12345678(:32|),@\\+er2.w\\),er1" \ + "mova/w.l @(0x12345678:32,@+er2.w),er1" +gdb_test "x" "mova/w.l\t@\\(0x12345678(:32|),@er2-.w\\),er1" \ + "mova/w.l @(0x12345678:32,@er2-.w),er1" +gdb_test "x" "mova/w.l\t@\\(0x12345678(:32|),@\\(0x9abc(:16|),er2\\).w\\),er1" \ + "mova/w.l @(0x12345678:32,@(0x9abc:16,er2).w),er1" +gdb_test "x" "mova/w.l\t@\\(0x12345678(:32|),@\\(0x9abcdef0(:32|),er2\\).w\\),er1" \ + "mova/w.l @(0x12345678:32,@(0x9abcdef0:32,er2).w),er1" +gdb_test "x" "mova/w.l\t@\\(0x12345678(:32|),@\\(0x9abc(:16|),r2l.b\\).w\\),er1" \ + "mova/w.l @(0x12345678:32,@(0x9abc:16,r2l.b).w),er1" +gdb_test "x" "mova/w.l\t@\\(0x12345678(:32|),@\\(0x9abc(:16|),r2.w\\).w\\),er1" \ + "mova/w.l @(0x12345678:32,@(0x9abc:16,r2.w).w),er1" +gdb_test "x" "mova/w.l\t@\\(0x12345678(:32|),@\\(0x9abc(:16|),er2.l\\).w\\),er1" \ + "mova/w.l @(0x12345678:32,@(0x9abc:16,er2.l).w),er1" +gdb_test "x" "mova/w.l\t@\\(0x12345678(:32|),@\\(0x9abcdef0(:32|),r2l.b\\).w\\),er1" \ + "mova/w.l @(0x12345678:32,@(0x9abcdef0:32,r2l.b).w),er1" +gdb_test "x" "mova/w.l\t@\\(0x12345678(:32|),@\\(0x9abcdef0(:32|),r2.w\\).w\\),er1" \ + "mova/w.l @(0x12345678:32,@(0x9abcdef0:32,r2.w).w),er1" +gdb_test "x" "mova/w.l\t@\\(0x12345678(:32|),@\\(0x9abcdef0(:32|),er2.l\\).w\\),er1" \ + "mova/w.l @(0x12345678:32,@(0x9abcdef0:32,er2.l).w),er1" +gdb_test "x" "mova/w.l\t@\\(0x12345678(:32|),@0x9abc(:16|).w\\),er1" \ + "mova/w.l @(0x12345678:32,@0x9abc:16.w),er1" +gdb_test "x" "mova/w.l\t@\\(0x12345678(:32|),@0x9abcdef0(:32|).w\\),er1" \ + "mova/w.l @(0x12345678:32,@0x9abcdef0:32.w),er1" +gdb_test "x" "mova/l.l\t@\\(0x12345678(:32|),@er2.b\\),er1" \ + "mova/l.l @(0x12345678:32,@er2.b),er1" +gdb_test "x" "mova/l.l\t@\\(0x12345678(:32|),@\\(0x1(:2|),er2\\).b\\),er1" \ + "mova/l.l @(0x12345678:32,@(0x1:2,er2).b),er1" +gdb_test "x" "mova/l.l\t@\\(0x12345678(:32|),@er2\\+.b\\),er1" \ + "mova/l.l @(0x12345678:32,@er2+.b),er1" +gdb_test "x" "mova/l.l\t@\\(0x12345678(:32|),@-er2.b\\),er1" \ + "mova/l.l @(0x12345678:32,@-er2.b),er1" +gdb_test "x" "mova/l.l\t@\\(0x12345678(:32|),@\\+er2.b\\),er1" \ + "mova/l.l @(0x12345678:32,@+er2.b),er1" +gdb_test "x" "mova/l.l\t@\\(0x12345678(:32|),@er2-.b\\),er1" \ + "mova/l.l @(0x12345678:32,@er2-.b),er1" +gdb_test "x" "mova/l.l\t@\\(0x12345678(:32|),@\\(0x9abc(:16|),er2\\).b\\),er1" \ + "mova/l.l @(0x12345678:32,@(0x9abc:16,er2).b),er1" +gdb_test "x" "mova/l.l\t@\\(0x12345678(:32|),@\\(0x9abcdef0(:32|),er2\\).b\\),er1" \ + "mova/l.l @(0x12345678:32,@(0x9abcdef0:32,er2).b),er1" +gdb_test "x" "mova/l.l\t@\\(0x12345678(:32|),@\\(0x9abc(:16|),r2l.b\\).b\\),er1" \ + "mova/l.l @(0x12345678:32,@(0x9abc:16,r2l.b).b),er1" +gdb_test "x" "mova/l.l\t@\\(0x12345678(:32|),@\\(0x9abc(:16|),r2.w\\).b\\),er1" \ + "mova/l.l @(0x12345678:32,@(0x9abc:16,r2.w).b),er1" +gdb_test "x" "mova/l.l\t@\\(0x12345678(:32|),@\\(0x9abc(:16|),er2.l\\).b\\),er1" \ + "mova/l.l @(0x12345678:32,@(0x9abc:16,er2.l).b),er1" +gdb_test "x" "mova/l.l\t@\\(0x12345678(:32|),@\\(0x9abcdef0(:32|),r2l.b\\).b\\),er1" \ + "mova/l.l @(0x12345678:32,@(0x9abcdef0:32,r2l.b).b),er1" +gdb_test "x" "mova/l.l\t@\\(0x12345678(:32|),@\\(0x9abcdef0(:32|),r2.w\\).b\\),er1" \ + "mova/l.l @(0x12345678:32,@(0x9abcdef0:32,r2.w).b),er1" +gdb_test "x" "mova/l.l\t@\\(0x12345678(:32|),@\\(0x9abcdef0(:32|),er2.l\\).b\\),er1" \ + "mova/l.l @(0x12345678:32,@(0x9abcdef0:32,er2.l).b),er1" +gdb_test "x" "mova/l.l\t@\\(0x12345678(:32|),@0x9abc(:16|).b\\),er1" \ + "mova/l.l @(0x12345678:32,@0x9abc:16.b),er1" +gdb_test "x" "mova/l.l\t@\\(0x12345678(:32|),@0x9abcdef0(:32|).b\\),er1" \ + "mova/l.l @(0x12345678:32,@0x9abcdef0:32.b),er1" +gdb_test "x" "mova/l.l\t@\\(0x12345678(:32|),@er2.w\\),er1" \ + "mova/l.l @(0x12345678:32,@er2.w),er1" +gdb_test "x" "mova/l.l\t@\\(0x12345678(:32|),@\\(0x2(:2|),er2\\).w\\),er1" \ + "mova/l.l @(0x12345678:32,@(0x2:2,er2).w),er1" +gdb_test "x" "mova/l.l\t@\\(0x12345678(:32|),@er2\\+.w\\),er1" \ + "mova/l.l @(0x12345678:32,@er2+.w),er1" +gdb_test "x" "mova/l.l\t@\\(0x12345678(:32|),@-er2.w\\),er1" \ + "mova/l.l @(0x12345678:32,@-er2.w),er1" +gdb_test "x" "mova/l.l\t@\\(0x12345678(:32|),@\\+er2.w\\),er1" \ + "mova/l.l @(0x12345678:32,@+er2.w),er1" +gdb_test "x" "mova/l.l\t@\\(0x12345678(:32|),@er2-.w\\),er1" \ + "mova/l.l @(0x12345678:32,@er2-.w),er1" +gdb_test "x" "mova/l.l\t@\\(0x12345678(:32|),@\\(0x9abc(:16|),er2\\).w\\),er1" \ + "mova/l.l @(0x12345678:32,@(0x9abc:16,er2).w),er1" +gdb_test "x" "mova/l.l\t@\\(0x12345678(:32|),@\\(0x9abcdef0(:32|),er2\\).w\\),er1" \ + "mova/l.l @(0x12345678:32,@(0x9abcdef0:32,er2).w),er1" +gdb_test "x" "mova/l.l\t@\\(0x12345678(:32|),@\\(0x9abc(:16|),r2l.b\\).w\\),er1" \ + "mova/l.l @(0x12345678:32,@(0x9abc:16,r2l.b).w),er1" +gdb_test "x" "mova/l.l\t@\\(0x12345678(:32|),@\\(0x9abc(:16|),r2.w\\).w\\),er1" \ + "mova/l.l @(0x12345678:32,@(0x9abc:16,r2.w).w),er1" +gdb_test "x" "mova/l.l\t@\\(0x12345678(:32|),@\\(0x9abc(:16|),er2.l\\).w\\),er1" \ + "mova/l.l @(0x12345678:32,@(0x9abc:16,er2.l).w),er1" +gdb_test "x" "mova/l.l\t@\\(0x12345678(:32|),@\\(0x9abcdef0(:32|),r2l.b\\).w\\),er1" \ + "mova/l.l @(0x12345678:32,@(0x9abcdef0:32,r2l.b).w),er1" +gdb_test "x" "mova/l.l\t@\\(0x12345678(:32|),@\\(0x9abcdef0(:32|),r2.w\\).w\\),er1" \ + "mova/l.l @(0x12345678:32,@(0x9abcdef0:32,r2.w).w),er1" +gdb_test "x" "mova/l.l\t@\\(0x12345678(:32|),@\\(0x9abcdef0(:32|),er2.l\\).w\\),er1" \ + "mova/l.l @(0x12345678:32,@(0x9abcdef0:32,er2.l).w),er1" +gdb_test "x" "mova/l.l\t@\\(0x12345678(:32|),@0x9abc(:16|).w\\),er1" \ + "mova/l.l @(0x12345678:32,@0x9abc:16.w),er1" +gdb_test "x" "mova/l.l\t@\\(0x12345678(:32|),@0x9abcdef0(:32|).w\\),er1" \ + "mova/l.l @(0x12345678:32,@0x9abcdef0:32.w),er1" diff --git a/gdb/testsuite/gdb.disasm/t02_mova.s b/gdb/testsuite/gdb.disasm/t02_mova.s new file mode 100644 index 0000000..8a2e228 --- /dev/null +++ b/gdb/testsuite/gdb.disasm/t02_mova.s @@ -0,0 +1,238 @@ +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;mova +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + .h8300sx + .text + .global _start +_start: + mova/b.c @(0x1234:16,r3l.b),er1 ;7A891234 + mova/b.c @(0x1234:16,r3.w),er1 ;7A991234 + mova/w.c @(0x1234:16,r3l.b),er1 ;7AA91234 + mova/w.c @(0x1234:16,r3.w),er1 ;7AB91234 + mova/l.c @(0x1234:16,r3l.b),er1 ;7AC91234 + mova/l.c @(0x1234:16,r3.w),er1 ;7AD91234 + mova/b.c @(0x12345678:32,r3l.b),er1 ;7A8112345678 + mova/b.c @(0x12345678:32,r3.w),er1 ;7A9112345678 + mova/w.c @(0x12345678:32,r3l.b),er1 ;7AA112345678 + mova/w.c @(0x12345678:32,r3.w),er1 ;7AB112345678 + mova/l.c @(0x12345678:32,r3l.b),er1 ;7AC112345678 + mova/l.c @(0x12345678:32,r3.w),er1 ;7AD112345678 + + mova/b.l @(0x1234:16,r3l.b),er1 ;78B87A891234 + mova/b.l @(0x1234:16,r3.w),er1 ;78397A991234 + mova/w.l @(0x1234:16,r3l.b),er1 ;78B87AA91234 + mova/w.l @(0x1234:16,r3.w),er1 ;78397AB91234 + mova/l.l @(0x1234:16,r3l.b),er1 ;78B87AC91234 + mova/l.l @(0x1234:16,r3.w),er1 ;78397AD91234 + mova/b.l @(0x12345678:32,r3l.b),er1 ;78B87A8112345678 + mova/b.l @(0x12345678:32,r3.w),er1 ;78397A9112345678 + mova/w.l @(0x12345678:32,r3l.b),er1 ;78B87AA112345678 + mova/w.l @(0x12345678:32,r3.w),er1 ;78397AB112345678 + mova/l.l @(0x12345678:32,r3l.b),er1 ;78B87AC112345678 + mova/l.l @(0x12345678:32,r3.w),er1 ;78397AD112345678 + + mova/b.l @(0x1234:16,@er2.b),er1 ;017F02811234 + mova/b.l @(0x1234:16,@(0x1:2,er2).b),er1 ;017F12811234 + mova/b.l @(0x1234:16,@er2+.b),er1 ;017F82811234 + mova/b.l @(0x1234:16,@-er2.b),er1 ;017FB2811234 + mova/b.l @(0x1234:16,@+er2.b),er1 ;017F92811234 + mova/b.l @(0x1234:16,@er2-.b),er1 ;017FA2811234 + mova/b.l @(0x1234:16,@(0xFFFF9ABC:16,er2).b),er1 ;017FC2819ABC1234 + mova/b.l @(0x1234:16,@(0x9ABCDEF0:32,er2).b),er1 ;017FCA819ABCDEF01234 + mova/b.l @(0x1234:16,@(0xFFFF9ABC:16,r2L.b).b),er1 ;017FD2819ABC1234 + mova/b.l @(0x1234:16,@(0xFFFF9ABC:16,r2.w).b),er1 ;017FE2819ABC1234 + mova/b.l @(0x1234:16,@(0xFFFF9ABC:16,er2.l).b),er1 ;017FF2819ABC1234 + mova/b.l @(0x1234:16,@(0x9ABCDEF0:32,r2L.b).b),er1 ;017FDA819ABCDEF01234 + mova/b.l @(0x1234:16,@(0x9ABCDEF0:32,r2.w).b),er1 ;017FEA819ABCDEF01234 + mova/b.l @(0x1234:16,@(0x9ABCDEF0:32,er2.l).b),er1 ;017FFA819ABCDEF01234 + mova/b.l @(0x1234:16,@0xFFFF9ABC:16.b),er1 ;017F40819ABC1234 + mova/b.l @(0x1234:16,@0x9ABCDEF0:32.b),er1 ;017F48819ABCDEF01234 + + mova/b.l @(0x1234:16,@er2.w),er1 ;015F02911234 + mova/b.l @(0x1234:16,@(0x2:2,er2).w),er1 ;015F12911234 + mova/b.l @(0x1234:16,@er2+.w),er1 ;015F82911234 + mova/b.l @(0x1234:16,@-er2.w),er1 ;015FB2911234 + mova/b.l @(0x1234:16,@+er2.w),er1 ;015F92911234 + mova/b.l @(0x1234:16,@er2-.w),er1 ;015FA2911234 + mova/b.l @(0x1234:16,@(0xFFFF9ABC:16,er2).w),er1 ;015FC2919ABC1234 + mova/b.l @(0x1234:16,@(0x9ABCDEF0:32,er2).w),er1 ;015FCA919ABCDEF01234 + mova/b.l @(0x1234:16,@(0xFFFF9ABC:16,r2L.b).w),er1 ;015FD2919ABC1234 + mova/b.l @(0x1234:16,@(0xFFFF9ABC:16,r2.w).w),er1 ;015FE2919ABC1234 + mova/b.l @(0x1234:16,@(0xFFFF9ABC:16,er2.l).w),er1 ;015FF2919ABC1234 + mova/b.l @(0x1234:16,@(0x9ABCDEF0:32,r2L.b).w),er1 ;015FDA919ABCDEF01234 + mova/b.l @(0x1234:16,@(0x9ABCDEF0:32,r2.w).w),er1 ;015FEA919ABCDEF01234 + mova/b.l @(0x1234:16,@(0x9ABCDEF0:32,er2.l).w),er1 ;015FFA919ABCDEF01234 + mova/b.l @(0x1234:16,@0xFFFF9ABC:16.w),er1 ;015F40919ABC1234 + mova/b.l @(0x1234:16,@0x9ABCDEF0:32.w),er1 ;015F48919ABCDEF01234 + + mova/w.l @(0x1234:16,@er2.b),er1 ;017F02A11234 + mova/w.l @(0x1234:16,@(0x1:2,er2).b),er1 ;017F12A11234 + mova/w.l @(0x1234:16,@er2+.b),er1 ;017F82A11234 + mova/w.l @(0x1234:16,@-er2.b),er1 ;017FB2A11234 + mova/w.l @(0x1234:16,@+er2.b),er1 ;017F92A11234 + mova/w.l @(0x1234:16,@er2-.b),er1 ;017FA2A11234 + mova/w.l @(0x1234:16,@(0xFFFF9ABC:16,er2).b),er1 ;017FC2A19ABC1234 + mova/w.l @(0x1234:16,@(0x9ABCDEF0:32,er2).b),er1 ;017FCAA19ABCDEF01234 + mova/w.l @(0x1234:16,@(0xFFFF9ABC:16,r2L.b).b),er1 ;017FD2A19ABC1234 + mova/w.l @(0x1234:16,@(0xFFFF9ABC:16,r2.w).b),er1 ;017FE2A19ABC1234 + mova/w.l @(0x1234:16,@(0xFFFF9ABC:16,er2.l).b),er1 ;017FF2A19ABC1234 + mova/w.l @(0x1234:16,@(0x9ABCDEF0:32,r2L.b).b),er1 ;017FDAA19ABCDEF01234 + mova/w.l @(0x1234:16,@(0x9ABCDEF0:32,r2.w).b),er1 ;017FEAA19ABCDEF01234 + mova/w.l @(0x1234:16,@(0x9ABCDEF0:32,er2.l).b),er1 ;017FFAA19ABCDEF01234 + mova/w.l @(0x1234:16,@0xFFFF9ABC:16.b),er1 ;017F40A19ABC1234 + mova/w.l @(0x1234:16,@0x9ABCDEF0:32.b),er1 ;017F48A19ABCDEF01234 + + mova/w.l @(0x1234:16,@er2.w),er1 ;015F02B11234 + mova/w.l @(0x1234:16,@(0x2:2,er2).w),er1 ;015F12B11234 + mova/w.l @(0x1234:16,@er2+.w),er1 ;015F82B11234 + mova/w.l @(0x1234:16,@-er2.w),er1 ;015FB2B11234 + mova/w.l @(0x1234:16,@+er2.w),er1 ;015F92B11234 + mova/w.l @(0x1234:16,@er2-.w),er1 ;015FA2B11234 + mova/w.l @(0x1234:16,@(0xFFFF9ABC:16,er2).w),er1 ;015FC2B19ABC1234 + mova/w.l @(0x1234:16,@(0x9ABCDEF0:32,er2).w),er1 ;015FCAB19ABCDEF01234 + mova/w.l @(0x1234:16,@(0xFFFF9ABC:16,r2L.b).w),er1 ;015FD2B19ABC1234 + mova/w.l @(0x1234:16,@(0xFFFF9ABC:16,r2.w).w),er1 ;015FE2B19ABC1234 + mova/w.l @(0x1234:16,@(0xFFFF9ABC:16,er2.l).w),er1 ;015FF2B19ABC1234 + mova/w.l @(0x1234:16,@(0x9ABCDEF0:32,r2L.b).w),er1 ;015FDAB19ABCDEF01234 + mova/w.l @(0x1234:16,@(0x9ABCDEF0:32,r2.w).w),er1 ;015FEAB19ABCDEF01234 + mova/w.l @(0x1234:16,@(0x9ABCDEF0:32,er2.l).w),er1 ;015FFAB19ABCDEF01234 + mova/w.l @(0x1234:16,@0xFFFF9ABC:16.w),er1 ;015F40B19ABC1234 + mova/w.l @(0x1234:16,@0x9ABCDEF0:32.w),er1 ;015F48B19ABCDEF01234 + + mova/l.l @(0x1234:16,@er2.b),er1 ;017F02C11234 + mova/l.l @(0x1234:16,@(0x1:2,er2).b),er1 ;017F12C11234 + mova/l.l @(0x1234:16,@er2+.b),er1 ;017F82C11234 + mova/l.l @(0x1234:16,@-er2.b),er1 ;017FB2C11234 + mova/l.l @(0x1234:16,@+er2.b),er1 ;017F92C11234 + mova/l.l @(0x1234:16,@er2-.b),er1 ;017FA2C11234 + mova/l.l @(0x1234:16,@(0xFFFF9ABC:16,er2).b),er1 ;017FC2C19ABC1234 + mova/l.l @(0x1234:16,@(0x9ABCDEF0:32,er2).b),er1 ;017FCAC19ABCDEF01234 + mova/l.l @(0x1234:16,@(0xFFFF9ABC:16,r2L.b).b),er1 ;017FD2C19ABC1234 + mova/l.l @(0x1234:16,@(0xFFFF9ABC:16,r2.w).b),er1 ;017FE2C19ABC1234 + mova/l.l @(0x1234:16,@(0xFFFF9ABC:16,er2.l).b),er1 ;017FF2C19ABC1234 + mova/l.l @(0x1234:16,@(0x9ABCDEF0:32,r2L.b).b),er1 ;017FDAC19ABCDEF01234 + mova/l.l @(0x1234:16,@(0x9ABCDEF0:32,r2.w).b),er1 ;017FEAC19ABCDEF01234 + mova/l.l @(0x1234:16,@(0x9ABCDEF0:32,er2.l).b),er1 ;017FFAC19ABCDEF01234 + mova/l.l @(0x1234:16,@0xFFFF9ABC:16.b),er1 ;017F40C19ABC1234 + mova/l.l @(0x1234:16,@0x9ABCDEF0:32.b),er1 ;017F48C19ABCDEF01234 + + mova/l.l @(0x1234:16,@er2.w),er1 ;015F02D11234 + mova/l.l @(0x1234:16,@(0x2:2,er2).w),er1 ;015F12D11234 + mova/l.l @(0x1234:16,@er2+.w),er1 ;015F82D11234 + mova/l.l @(0x1234:16,@-er2.w),er1 ;015FB2D11234 + mova/l.l @(0x1234:16,@+er2.w),er1 ;015F92D11234 + mova/l.l @(0x1234:16,@er2-.w),er1 ;015FA2D11234 + mova/l.l @(0x1234:16,@(0xFFFF9ABC:16,er2).w),er1 ;015FC2D19ABC1234 + mova/l.l @(0x1234:16,@(0x9ABCDEF0:32,er2).w),er1 ;015FCAD19ABCDEF01234 + mova/l.l @(0x1234:16,@(0xFFFF9ABC:16,r2L.b).w),er1 ;015FD2D19ABC1234 + mova/l.l @(0x1234:16,@(0xFFFF9ABC:16,r2.w).w),er1 ;015FE2D19ABC1234 + mova/l.l @(0x1234:16,@(0xFFFF9ABC:16,er2.l).w),er1 ;015FF2D19ABC1234 + mova/l.l @(0x1234:16,@(0x9ABCDEF0:32,r2L.b).w),er1 ;015FDAD19ABCDEF01234 + mova/l.l @(0x1234:16,@(0x9ABCDEF0:32,r2.w).w),er1 ;015FEAD19ABCDEF01234 + mova/l.l @(0x1234:16,@(0x9ABCDEF0:32,er2.l).w),er1 ;015FFAD19ABCDEF01234 + mova/l.l @(0x1234:16,@0xFFFF9ABC:16.w),er1 ;015F40D19ABC1234 + mova/l.l @(0x1234:16,@0x9ABCDEF0:32.w),er1 ;015F48D19ABCDEF01234 + + mova/b.l @(0x12345678:32,@er2.b),er1 ;017F028912345678 + mova/b.l @(0x12345678:32,@(0x1:2,er2).b),er1 ;017F128912345678 + mova/b.l @(0x12345678:32,@er2+.b),er1 ;017F828912345678 + mova/b.l @(0x12345678:32,@-er2.b),er1 ;017FB28912345678 + mova/b.l @(0x12345678:32,@+er2.b),er1 ;017F928912345678 + mova/b.l @(0x12345678:32,@er2-.b),er1 ;017FA28912345678 + mova/b.l @(0x12345678:32,@(0xFFFF9ABC:16,er2).b),er1 ;017FC2899ABC12345678 + mova/b.l @(0x12345678:32,@(0x9ABCDEF0:32,er2).b),er1 ;017FCA899ABCDEF012345678 + mova/b.l @(0x12345678:32,@(0xFFFF9ABC:16,r2L.b).b),er1 ;017FD2899ABC12345678 + mova/b.l @(0x12345678:32,@(0xFFFF9ABC:16,r2.w).b),er1 ;017FE2899ABC12345678 + mova/b.l @(0x12345678:32,@(0xFFFF9ABC:16,er2.l).b),er1 ;017FF2899ABC12345678 + mova/b.l @(0x12345678:32,@(0x9ABCDEF0:32,r2L.b).b),er1 ;017FDA899ABCDEF012345678 + mova/b.l @(0x12345678:32,@(0x9ABCDEF0:32,r2.w).b),er1 ;017FEA899ABCDEF012345678 + mova/b.l @(0x12345678:32,@(0x9ABCDEF0:32,er2.l).b),er1 ;017FFA899ABCDEF012345678 + mova/b.l @(0x12345678:32,@0xFFFF9ABC:16.b),er1 ;017F40899ABC12345678 + mova/b.l @(0x12345678:32,@0x9ABCDEF0:32.b),er1 ;017F48899ABCDEF012345678 + + mova/b.l @(0x12345678:32,@er2.w),er1 ;015F029912345678 + mova/b.l @(0x12345678:32,@(0x2:2,er2).w),er1 ;015F129912345678 + mova/b.l @(0x12345678:32,@er2+.w),er1 ;015F829912345678 + mova/b.l @(0x12345678:32,@-er2.w),er1 ;015FB29912345678 + mova/b.l @(0x12345678:32,@+er2.w),er1 ;015F929912345678 + mova/b.l @(0x12345678:32,@er2-.w),er1 ;015FA29912345678 + mova/b.l @(0x12345678:32,@(0xFFFF9ABC:16,er2).w),er1 ;015FC2999ABC12345678 + mova/b.l @(0x12345678:32,@(0x9ABCDEF0:32,er2).w),er1 ;015FCA999ABCDEF012345678 + mova/b.l @(0x12345678:32,@(0xFFFF9ABC:16,r2L.b).w),er1 ;015FD2999ABC12345678 + mova/b.l @(0x12345678:32,@(0xFFFF9ABC:16,r2.w).w),er1 ;015FE2999ABC12345678 + mova/b.l @(0x12345678:32,@(0xFFFF9ABC:16,er2.l).w),er1 ;015FF2999ABC12345678 + mova/b.l @(0x12345678:32,@(0x9ABCDEF0:32,r2L.b).w),er1 ;015FDA999ABCDEF012345678 + mova/b.l @(0x12345678:32,@(0x9ABCDEF0:32,r2.w).w),er1 ;015FEA999ABCDEF012345678 + mova/b.l @(0x12345678:32,@(0x9ABCDEF0:32,er2.l).w),er1 ;015FFA999ABCDEF012345678 + mova/b.l @(0x12345678:32,@0xFFFF9ABC:16.w),er1 ;015F40999ABC12345678 + mova/b.l @(0x12345678:32,@0x9ABCDEF0:32.w),er1 ;015F48999ABCDEF012345678 + + mova/w.l @(0x12345678:32,@er2.b),er1 ;017F02A912345678 + mova/w.l @(0x12345678:32,@(0x1:2,er2).b),er1 ;017F12A912345678 + mova/w.l @(0x12345678:32,@er2+.b),er1 ;017F82A912345678 + mova/w.l @(0x12345678:32,@-er2.b),er1 ;017FB2A912345678 + mova/w.l @(0x12345678:32,@+er2.b),er1 ;017F92A912345678 + mova/w.l @(0x12345678:32,@er2-.b),er1 ;017FA2A912345678 + mova/w.l @(0x12345678:32,@(0xFFFF9ABC:16,er2).b),er1 ;017FC2A99ABC12345678 + mova/w.l @(0x12345678:32,@(0x9ABCDEF0:32,er2).b),er1 ;017FCAA99ABCDEF012345678 + mova/w.l @(0x12345678:32,@(0xFFFF9ABC:16,r2L.b).b),er1 ;017FD2A99ABC12345678 + mova/w.l @(0x12345678:32,@(0xFFFF9ABC:16,r2.w).b),er1 ;017FE2A99ABC12345678 + mova/w.l @(0x12345678:32,@(0xFFFF9ABC:16,er2.l).b),er1 ;017FF2A99ABC12345678 + mova/w.l @(0x12345678:32,@(0x9ABCDEF0:32,r2L.b).b),er1 ;017FDAA99ABCDEF012345678 + mova/w.l @(0x12345678:32,@(0x9ABCDEF0:32,r2.w).b),er1 ;017FEAA99ABCDEF012345678 + mova/w.l @(0x12345678:32,@(0x9ABCDEF0:32,er2.l).b),er1 ;017FFAA99ABCDEF012345678 + mova/w.l @(0x12345678:32,@0xFFFF9ABC:16.b),er1 ;017F40A99ABC12345678 + mova/w.l @(0x12345678:32,@0x9ABCDEF0:32.b),er1 ;017F48A99ABCDEF012345678 + + mova/w.l @(0x12345678:32,@er2.w),er1 ;015F02B912345678 + mova/w.l @(0x12345678:32,@(0x2:2,er2).w),er1 ;015F12B912345678 + mova/w.l @(0x12345678:32,@er2+.w),er1 ;015F82B912345678 + mova/w.l @(0x12345678:32,@-er2.w),er1 ;015FB2B912345678 + mova/w.l @(0x12345678:32,@+er2.w),er1 ;015F92B912345678 + mova/w.l @(0x12345678:32,@er2-.w),er1 ;015FA2B912345678 + mova/w.l @(0x12345678:32,@(0xFFFF9ABC:16,er2).w),er1 ;015FC2B99ABC12345678 + mova/w.l @(0x12345678:32,@(0x9ABCDEF0:32,er2).w),er1 ;015FCAB99ABCDEF012345678 + mova/w.l @(0x12345678:32,@(0xFFFF9ABC:16,r2L.b).w),er1 ;015FD2B99ABC12345678 + mova/w.l @(0x12345678:32,@(0xFFFF9ABC:16,r2.w).w),er1 ;015FE2B99ABC12345678 + mova/w.l @(0x12345678:32,@(0xFFFF9ABC:16,er2.l).w),er1 ;015FF2B99ABC12345678 + mova/w.l @(0x12345678:32,@(0x9ABCDEF0:32,r2L.b).w),er1 ;015FDAB99ABCDEF012345678 + mova/w.l @(0x12345678:32,@(0x9ABCDEF0:32,r2.w).w),er1 ;015FEAB99ABCDEF012345678 + mova/w.l @(0x12345678:32,@(0x9ABCDEF0:32,er2.l).w),er1 ;015FFAB99ABCDEF012345678 + mova/w.l @(0x12345678:32,@0xFFFF9ABC:16.w),er1 ;015F40B99ABC12345678 + mova/w.l @(0x12345678:32,@0x9ABCDEF0:32.w),er1 ;015F48B99ABCDEF012345678 + + mova/l.l @(0x12345678:32,@er2.b),er1 ;017F02C912345678 + mova/l.l @(0x12345678:32,@(0x1:2,er2).b),er1 ;017F12C912345678 + mova/l.l @(0x12345678:32,@er2+.b),er1 ;017F82C912345678 + mova/l.l @(0x12345678:32,@-er2.b),er1 ;017FB2C912345678 + mova/l.l @(0x12345678:32,@+er2.b),er1 ;017F92C912345678 + mova/l.l @(0x12345678:32,@er2-.b),er1 ;017FA2C912345678 + mova/l.l @(0x12345678:32,@(0xFFFF9ABC:16,er2).b),er1 ;017FC2C99ABC12345678 + mova/l.l @(0x12345678:32,@(0x9ABCDEF0:32,er2).b),er1 ;017FCAC99ABCDEF012345678 + mova/l.l @(0x12345678:32,@(0xFFFF9ABC:16,r2L.b).b),er1 ;017FD2C99ABC12345678 + mova/l.l @(0x12345678:32,@(0xFFFF9ABC:16,r2.w).b),er1 ;017FE2C99ABC12345678 + mova/l.l @(0x12345678:32,@(0xFFFF9ABC:16,er2.l).b),er1 ;017FF2C99ABC12345678 + mova/l.l @(0x12345678:32,@(0x9ABCDEF0:32,r2L.b).b),er1 ;017FDAC99ABCDEF012345678 + mova/l.l @(0x12345678:32,@(0x9ABCDEF0:32,r2.w).b),er1 ;017FEAC99ABCDEF012345678 + mova/l.l @(0x12345678:32,@(0x9ABCDEF0:32,er2.l).b),er1 ;017FFAC99ABCDEF012345678 + mova/l.l @(0x12345678:32,@0xFFFF9ABC:16.b),er1 ;017F40C99ABC12345678 + mova/l.l @(0x12345678:32,@0x9ABCDEF0:32.b),er1 ;017F48C99ABCDEF012345678 + + mova/l.l @(0x12345678:32,@er2.w),er1 ;015F02D912345678 + mova/l.l @(0x12345678:32,@(0x2:2,er2).w),er1 ;015F12D912345678 + mova/l.l @(0x12345678:32,@er2+.w),er1 ;015F82D912345678 + mova/l.l @(0x12345678:32,@-er2.w),er1 ;015FB2D912345678 + mova/l.l @(0x12345678:32,@+er2.w),er1 ;015F92D912345678 + mova/l.l @(0x12345678:32,@er2-.w),er1 ;015FA2D912345678 + mova/l.l @(0x12345678:32,@(0xFFFF9ABC:16,er2).w),er1 ;015FC2D99ABC12345678 + mova/l.l @(0x12345678:32,@(0x9ABCDEF0:32,er2).w),er1 ;015FCAD99ABCDEF012345678 + mova/l.l @(0x12345678:32,@(0xFFFF9ABC:16,r2L.b).w),er1 ;015FD2D99ABC12345678 + mova/l.l @(0x12345678:32,@(0xFFFF9ABC:16,r2.w).w),er1 ;015FE2D99ABC12345678 + mova/l.l @(0x12345678:32,@(0xFFFF9ABC:16,er2.l).w),er1 ;015FF2D99ABC12345678 + mova/l.l @(0x12345678:32,@(0x9ABCDEF0:32,r2L.b).w),er1 ;015FDAD99ABCDEF012345678 + mova/l.l @(0x12345678:32,@(0x9ABCDEF0:32,r2.w).w),er1 ;015FEAD99ABCDEF012345678 + mova/l.l @(0x12345678:32,@(0x9ABCDEF0:32,er2.l).w),er1 ;015FFAD99ABCDEF012345678 + mova/l.l @(0x12345678:32,@0xFFFF9ABC:16.w),er1 ;015F40D99ABC12345678 + mova/l.l @(0x12345678:32,@0x9ABCDEF0:32.w),er1 ;015F48D99ABCDEF012345678 + + .end diff --git a/gdb/testsuite/gdb.disasm/t03_add.exp b/gdb/testsuite/gdb.disasm/t03_add.exp new file mode 100644 index 0000000..5128fb9 --- /dev/null +++ b/gdb/testsuite/gdb.disasm/t03_add.exp @@ -0,0 +1,1876 @@ +# Copyright (C) 2003 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# Please email any bugs, comments, and/or additions to this file to: +# bug-gdb@prep.ai.mit.edu + +# This file was written by Michael Snyder (msnyder@redhat.com) + +if $tracelevel then { + strace $tracelevel +} + +if ![istarget "h8300*-*-*"] { + verbose "Tests ignored for all but h8300s based targets." + return +} + +set prms_id 0 +set bug_id 0 + +set testfile "t03_add" +set srcfile ${srcdir}/${subdir}/${testfile}.s +set objfile ${objdir}/${subdir}/${testfile}.o +set binfile ${objdir}/${subdir}/${testfile}.x + +set asm-flags ""; +set link-flags "-m h8300sxelf"; + + +if {[target_assemble $srcfile $objfile "${asm-flags}"] != ""} then { + gdb_suppress_entire_file "Testcase assembly failed, so all tests in this file will automatically fail." +} + +if {[target_link $objfile $binfile "${link-flags}"] != ""} then { + gdb_suppress_entire_file "Testcase link failed, so all tests in this file will automatically fail." +} + +gdb_start +gdb_reinitialize_dir $srcdir/$subdir +gdb_load $binfile + +gdb_test "x /i _start" "add.b\t#0x12(:8|),r1h" \ + "add.b #0x12:8,r1h" +gdb_test "x" "add.b\t#0x12(:8|),@er1" \ + "add.b #0x12:8,@er1" +gdb_test "x" "add.b\t#0x12(:8|),@\\(0x3(:2|),er1\\)" \ + "add.b #0x12:8,@(0x3:2,er1)" +gdb_test "x" "add.b\t#0x12(:8|),@er1\\+" \ + "add.b #0x12:8,@er1+" +gdb_test "x" "add.b\t#0x12(:8|),@-er1" \ + "add.b #0x12:8,@-er1" +gdb_test "x" "add.b\t#0x12(:8|),@\\+er1" \ + "add.b #0x12:8,@+er1" +gdb_test "x" "add.b\t#0x12(:8|),@er1-" \ + "add.b #0x12:8,@er1-" +gdb_test "x" "add.b\t#0x12(:8|),@\\(0x1234(:16|),er1\\)" \ + "add.b #0x12:8,@(0x1234:16,er1)" +gdb_test "x" "add.b\t#0x12(:8|),@\\(0x12345678(:32|),er1\\)" \ + "add.b #0x12:8,@(0x12345678:32,er1)" +gdb_test "x" "add.b\t#0x12(:8|),@\\(0x1234(:16|),r2l.b\\)" \ + "add.b #0x12:8,@(0x1234:16,r2l.b)" +gdb_test "x" "add.b\t#0x12(:8|),@\\(0x1234(:16|),r2.w\\)" \ + "add.b #0x12:8,@(0x1234:16,r2.w)" +gdb_test "x" "add.b\t#0x12(:8|),@\\(0x1234(:16|),er2.l\\)" \ + "add.b #0x12:8,@(0x1234:16,er2.l)" +gdb_test "x" "add.b\t#0x12(:8|),@\\(0x12345678(:32|),r2l.b\\)" \ + "add.b #0x12:8,@(0x12345678:32,r2l.b)" +gdb_test "x" "add.b\t#0x12(:8|),@\\(0x12345678(:32|),r2.w\\)" \ + "add.b #0x12:8,@(0x12345678:32,r2.w)" +gdb_test "x" "add.b\t#0x12(:8|),@\\(0x12345678(:32|),er2.l\\)" \ + "add.b #0x12:8,@(0x12345678:32,er2.l)" +gdb_test "x" "add.b\t#0x12(:8|),@0x9a(:8|)" \ + "add.b #0x12:8,@0x9a:8" +gdb_test "x" "add.b\t#0x12(:8|),@0x1234(:16|)" \ + "add.b #0x12:8,@0x1234:16" +gdb_test "x" "add.b\t#0x12(:8|),@0x12345678(:32|)" \ + "add.b #0x12:8,@0x12345678:32" +gdb_test "x" "add.b\tr3h,r1h" \ + "add.b r3h,r1h" +gdb_test "x" "add.b\tr3h,@er1" \ + "add.b r3h,@er1" +gdb_test "x" "add.b\tr3h,@\\(0x3(:2|),er1\\)" \ + "add.b r3h,@(0x3:2,er1)" +gdb_test "x" "add.b\tr3h,@er1\\+" \ + "add.b r3h,@er1+" +gdb_test "x" "add.b\tr3h,@-er1" \ + "add.b r3h,@-er1" +gdb_test "x" "add.b\tr3h,@\\+er1" \ + "add.b r3h,@+er1" +gdb_test "x" "add.b\tr3h,@er1-" \ + "add.b r3h,@er1-" +gdb_test "x" "add.b\tr3h,@\\(0x1234(:16|),er1\\)" \ + "add.b r3h,@(0x1234:16,er1)" +gdb_test "x" "add.b\tr3h,@\\(0x12345678(:32|),er1\\)" \ + "add.b r3h,@(0x12345678:32,er1)" +gdb_test "x" "add.b\tr3h,@\\(0x1234(:16|),r2l.b\\)" \ + "add.b r3h,@(0x1234:16,r2l.b)" +gdb_test "x" "add.b\tr3h,@\\(0x1234(:16|),r2.w\\)" \ + "add.b r3h,@(0x1234:16,r2.w)" +gdb_test "x" "add.b\tr3h,@\\(0x1234(:16|),er2.l\\)" \ + "add.b r3h,@(0x1234:16,er2.l)" +gdb_test "x" "add.b\tr3h,@\\(0x12345678(:32|),r2l.b\\)" \ + "add.b r3h,@(0x12345678:32,r2l.b)" +gdb_test "x" "add.b\tr3h,@\\(0x12345678(:32|),r2.w\\)" \ + "add.b r3h,@(0x12345678:32,r2.w)" +gdb_test "x" "add.b\tr3h,@\\(0x12345678(:32|),er2.l\\)" \ + "add.b r3h,@(0x12345678:32,er2.l)" +gdb_test "x" "add.b\tr3h,@0x12(:8|)" \ + "add.b r3h,@0x12:8" +gdb_test "x" "add.b\tr3h,@0x1234(:16|)" \ + "add.b r3h,@0x1234:16" +gdb_test "x" "add.b\tr3h,@0x12345678(:32|)" \ + "add.b r3h,@0x12345678:32" +gdb_test "x" "add.b\t@er3,r1h" \ + "add.b @er3,r1h" +gdb_test "x" "add.b\t@\\(0x3(:2|),er3\\),r1h" \ + "add.b @(0x3:2,er3),r1h" +gdb_test "x" "add.b\t@er3\\+,r1h" \ + "add.b @er3+,r1h" +gdb_test "x" "add.b\t@-er3,r1h" \ + "add.b @-er3,r1h" +gdb_test "x" "add.b\t@\\+er3,r1h" \ + "add.b @+er3,r1h" +gdb_test "x" "add.b\t@er3-,r1h" \ + "add.b @er3-,r1h" +gdb_test "x" "add.b\t@\\(0x1234(:16|),er1\\),r1h" \ + "add.b @(0x1234:16,er1),r1h" +gdb_test "x" "add.b\t@\\(0x12345678(:32|),er1\\),r1h" \ + "add.b @(0x12345678:32,er1),r1h" +gdb_test "x" "add.b\t@\\(0x1234(:16|),r2l.b\\),r1h" \ + "add.b @(0x1234:16,r2l.b),r1h" +gdb_test "x" "add.b\t@\\(0x1234(:16|),r2.w\\),r1h" \ + "add.b @(0x1234:16,r2.w),r1h" +gdb_test "x" "add.b\t@\\(0x1234(:16|),er2.l\\),r1h" \ + "add.b @(0x1234:16,er2.l),r1h" +gdb_test "x" "add.b\t@\\(0x12345678(:32|),r2l.b\\),r1h" \ + "add.b @(0x12345678:32,r2l.b),r1h" +gdb_test "x" "add.b\t@\\(0x12345678(:32|),r2.w\\),r1h" \ + "add.b @(0x12345678:32,r2.w),r1h" +gdb_test "x" "add.b\t@\\(0x12345678(:32|),er2.l\\),r1h" \ + "add.b @(0x12345678:32,er2.l),r1h" +gdb_test "x" "add.b\t@0x12(:8|),r1h" \ + "add.b @0x12:8,r1h" +gdb_test "x" "add.b\t@0x1234(:16|),r1h" \ + "add.b @0x1234:16,r1h" +gdb_test "x" "add.b\t@0x12345678(:32|),r1h" \ + "add.b @0x12345678:32,r1h" +gdb_test "x" "add.b\t@er3,@er1" \ + "add.b @er3,@er1" +gdb_test "x" "add.b\t@er3,@\\(0x3(:2|),er1\\)" \ + "add.b @er3,@(0x3:2,er1)" +gdb_test "x" "add.b\t@er3,@-er1" \ + "add.b @er3,@-er1" +gdb_test "x" "add.b\t@er3,@er1\\+" \ + "add.b @er3,@er1+" +gdb_test "x" "add.b\t@er3,@er1-" \ + "add.b @er3,@er1-" +gdb_test "x" "add.b\t@er3,@\\+er1" \ + "add.b @er3,@+er1" +gdb_test "x" "add.b\t@er3,@\\(0x9abc(:16|),er1\\)" \ + "add.b @er3,@(0x9abc:16,er1)" +gdb_test "x" "add.b\t@er3,@\\(0x9abcdef0(:32|),er1\\)" \ + "add.b @er3,@(0x9abcdef0:32,er1)" +gdb_test "x" "add.b\t@er3,@\\(0x9abc(:16|),r2l.b\\)" \ + "add.b @er3,@(0x9abc:16,r2l.b)" +gdb_test "x" "add.b\t@er3,@\\(0x9abc(:16|),r2.w\\)" \ + "add.b @er3,@(0x9abc:16,r2.w)" +gdb_test "x" "add.b\t@er3,@\\(0x9abc(:16|),er2.l\\)" \ + "add.b @er3,@(0x9abc:16,er2.l)" +gdb_test "x" "add.b\t@er3,@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "add.b @er3,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "add.b\t@er3,@\\(0x9abcdef0(:32|),r2.w\\)" \ + "add.b @er3,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "add.b\t@er3,@\\(0x9abcdef0(:32|),er2.l\\)" \ + "add.b @er3,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "add.b\t@er3,@0x9abc(:16|)" \ + "add.b @er3,@0x9abc:16" +gdb_test "x" "add.b\t@er3,@0x9abcdef0(:32|)" \ + "add.b @er3,@0x9abcdef0:32" +gdb_test "x" "add.b\t@-er3,@er1" \ + "add.b @-er3,@er1" +gdb_test "x" "add.b\t@-er3,@\\(0x3(:2|),er1\\)" \ + "add.b @-er3,@(0x3:2,er1)" +gdb_test "x" "add.b\t@-er3,@-er1" \ + "add.b @-er3,@-er1" +gdb_test "x" "add.b\t@-er3,@er1\\+" \ + "add.b @-er3,@er1+" +gdb_test "x" "add.b\t@-er3,@er1-" \ + "add.b @-er3,@er1-" +gdb_test "x" "add.b\t@-er3,@\\+er1" \ + "add.b @-er3,@+er1" +gdb_test "x" "add.b\t@-er3,@\\(0x9abc(:16|),er1\\)" \ + "add.b @-er3,@(0x9abc:16,er1)" +gdb_test "x" "add.b\t@-er3,@\\(0x9abcdef0(:32|),er1\\)" \ + "add.b @-er3,@(0x9abcdef0:32,er1)" +gdb_test "x" "add.b\t@-er3,@\\(0x9abc(:16|),r2l.b\\)" \ + "add.b @-er3,@(0x9abc:16,r2l.b)" +gdb_test "x" "add.b\t@-er3,@\\(0x9abc(:16|),r2.w\\)" \ + "add.b @-er3,@(0x9abc:16,r2.w)" +gdb_test "x" "add.b\t@-er3,@\\(0x9abc(:16|),er2.l\\)" \ + "add.b @-er3,@(0x9abc:16,er2.l)" +gdb_test "x" "add.b\t@-er3,@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "add.b @-er3,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "add.b\t@-er3,@\\(0x9abcdef0(:32|),r2.w\\)" \ + "add.b @-er3,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "add.b\t@-er3,@\\(0x9abcdef0(:32|),er2.l\\)" \ + "add.b @-er3,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "add.b\t@-er3,@0x9abc(:16|)" \ + "add.b @-er3,@0x9abc:16" +gdb_test "x" "add.b\t@-er3,@0x9abcdef0(:32|)" \ + "add.b @-er3,@0x9abcdef0:32" +gdb_test "x" "add.b\t@er3\\+,@er1" \ + "add.b @er3+,@er1" +gdb_test "x" "add.b\t@er3\\+,@\\(0x3(:2|),er1\\)" \ + "add.b @er3+,@(0x3:2,er1)" +gdb_test "x" "add.b\t@er3\\+,@-er1" \ + "add.b @er3+,@-er1" +gdb_test "x" "add.b\t@er3\\+,@er1\\+" \ + "add.b @er3+,@er1+" +gdb_test "x" "add.b\t@er3\\+,@er1-" \ + "add.b @er3+,@er1-" +gdb_test "x" "add.b\t@er3\\+,@\\+er1" \ + "add.b @er3+,@+er1" +gdb_test "x" "add.b\t@er3\\+,@\\(0x9abc(:16|),er1\\)" \ + "add.b @er3+,@(0x9abc:16,er1)" +gdb_test "x" "add.b\t@er3\\+,@\\(0x9abcdef0(:32|),er1\\)" \ + "add.b @er3+,@(0x9abcdef0:32,er1)" +gdb_test "x" "add.b\t@er3\\+,@\\(0x9abc(:16|),r2l.b\\)" \ + "add.b @er3+,@(0x9abc:16,r2l.b)" +gdb_test "x" "add.b\t@er3\\+,@\\(0x9abc(:16|),r2.w\\)" \ + "add.b @er3+,@(0x9abc:16,r2.w)" +gdb_test "x" "add.b\t@er3\\+,@\\(0x9abc(:16|),er2.l\\)" \ + "add.b @er3+,@(0x9abc:16,er2.l)" +gdb_test "x" "add.b\t@er3\\+,@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "add.b @er3+,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "add.b\t@er3\\+,@\\(0x9abcdef0(:32|),r2.w\\)" \ + "add.b @er3+,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "add.b\t@er3\\+,@\\(0x9abcdef0(:32|),er2.l\\)" \ + "add.b @er3+,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "add.b\t@er3\\+,@0x9abc(:16|)" \ + "add.b @er3+,@0x9abc:16" +gdb_test "x" "add.b\t@er3\\+,@0x9abcdef0(:32|)" \ + "add.b @er3+,@0x9abcdef0:32" +gdb_test "x" "add.b\t@er3-,@er1" \ + "add.b @er3-,@er1" +gdb_test "x" "add.b\t@er3-,@\\(0x3(:2|),er1\\)" \ + "add.b @er3-,@(0x3:2,er1)" +gdb_test "x" "add.b\t@er3-,@-er1" \ + "add.b @er3-,@-er1" +gdb_test "x" "add.b\t@er3-,@er1\\+" \ + "add.b @er3-,@er1+" +gdb_test "x" "add.b\t@er3-,@er1-" \ + "add.b @er3-,@er1-" +gdb_test "x" "add.b\t@er3-,@\\+er1" \ + "add.b @er3-,@+er1" +gdb_test "x" "add.b\t@er3-,@\\(0x9abc(:16|),er1\\)" \ + "add.b @er3-,@(0x9abc:16,er1)" +gdb_test "x" "add.b\t@er3-,@\\(0x9abcdef0(:32|),er1\\)" \ + "add.b @er3-,@(0x9abcdef0:32,er1)" +gdb_test "x" "add.b\t@er3-,@\\(0x9abc(:16|),r2l.b\\)" \ + "add.b @er3-,@(0x9abc:16,r2l.b)" +gdb_test "x" "add.b\t@er3-,@\\(0x9abc(:16|),r2.w\\)" \ + "add.b @er3-,@(0x9abc:16,r2.w)" +gdb_test "x" "add.b\t@er3-,@\\(0x9abc(:16|),er2.l\\)" \ + "add.b @er3-,@(0x9abc:16,er2.l)" +gdb_test "x" "add.b\t@er3-,@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "add.b @er3-,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "add.b\t@er3-,@\\(0x9abcdef0(:32|),r2.w\\)" \ + "add.b @er3-,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "add.b\t@er3-,@\\(0x9abcdef0(:32|),er2.l\\)" \ + "add.b @er3-,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "add.b\t@er3-,@0x9abc(:16|)" \ + "add.b @er3-,@0x9abc:16" +gdb_test "x" "add.b\t@er3-,@0x9abcdef0(:32|)" \ + "add.b @er3-,@0x9abcdef0:32" +gdb_test "x" "add.b\t@\\+er3,@er1" \ + "add.b @+er3,@er1" +gdb_test "x" "add.b\t@\\+er3,@\\(0x3(:2|),er1\\)" \ + "add.b @+er3,@(0x3:2,er1)" +gdb_test "x" "add.b\t@\\+er3,@-er1" \ + "add.b @+er3,@-er1" +gdb_test "x" "add.b\t@\\+er3,@er1\\+" \ + "add.b @+er3,@er1+" +gdb_test "x" "add.b\t@\\+er3,@er1-" \ + "add.b @+er3,@er1-" +gdb_test "x" "add.b\t@\\+er3,@\\+er1" \ + "add.b @+er3,@+er1" +gdb_test "x" "add.b\t@\\+er3,@\\(0x9abc(:16|),er1\\)" \ + "add.b @+er3,@(0x9abc:16,er1)" +gdb_test "x" "add.b\t@\\+er3,@\\(0x9abcdef0(:32|),er1\\)" \ + "add.b @+er3,@(0x9abcdef0:32,er1)" +gdb_test "x" "add.b\t@\\+er3,@\\(0x9abc(:16|),r2l.b\\)" \ + "add.b @+er3,@(0x9abc:16,r2l.b)" +gdb_test "x" "add.b\t@\\+er3,@\\(0x9abc(:16|),r2.w\\)" \ + "add.b @+er3,@(0x9abc:16,r2.w)" +gdb_test "x" "add.b\t@\\+er3,@\\(0x9abc(:16|),er2.l\\)" \ + "add.b @+er3,@(0x9abc:16,er2.l)" +gdb_test "x" "add.b\t@\\+er3,@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "add.b @+er3,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "add.b\t@\\+er3,@\\(0x9abcdef0(:32|),r2.w\\)" \ + "add.b @+er3,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "add.b\t@\\+er3,@\\(0x9abcdef0(:32|),er2.l\\)" \ + "add.b @+er3,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "add.b\t@\\+er3,@0x9abc(:16|)" \ + "add.b @+er3,@0x9abc:16" +gdb_test "x" "add.b\t@\\+er3,@0x9abcdef0(:32|)" \ + "add.b @+er3,@0x9abcdef0:32" +gdb_test "x" "add.b\t@\\(0x1234(:16|),er3\\),@er1" \ + "add.b @(0x1234:16,er3),@er1" +gdb_test "x" "add.b\t@\\(0x1234(:16|),er3\\),@\\(0x3(:2|),er1\\)" \ + "add.b @(0x1234:16,er3),@(0x3:2,er1)" +gdb_test "x" "add.b\t@\\(0x1234(:16|),er3\\),@-er1" \ + "add.b @(0x1234:16,er3),@-er1" +gdb_test "x" "add.b\t@\\(0x1234(:16|),er3\\),@er1\\+" \ + "add.b @(0x1234:16,er3),@er1+" +gdb_test "x" "add.b\t@\\(0x1234(:16|),er3\\),@er1-" \ + "add.b @(0x1234:16,er3),@er1-" +gdb_test "x" "add.b\t@\\(0x1234(:16|),er3\\),@\\+er1" \ + "add.b @(0x1234:16,er3),@+er1" +gdb_test "x" "add.b\t@\\(0x1234(:16|),er3\\),@\\(0x9abc(:16|),er1\\)" \ + "add.b @(0x1234:16,er3),@(0x9abc:16,er1)" +gdb_test "x" "add.b\t@\\(0x1234(:16|),er3\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "add.b @(0x1234:16,er3),@(0x9abcdef0:32,er1)" +gdb_test "x" "add.b\t@\\(0x1234(:16|),er3\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "add.b @(0x1234:16,er3),@(0x9abc:16,r2l.b)" +gdb_test "x" "add.b\t@\\(0x1234(:16|),er3\\),@\\(0x9abc(:16|),r2.w\\)" \ + "add.b @(0x1234:16,er3),@(0x9abc:16,r2.w)" +gdb_test "x" "add.b\t@\\(0x1234(:16|),er3\\),@\\(0x9abc(:16|),er2.l\\)" \ + "add.b @(0x1234:16,er3),@(0x9abc:16,er2.l)" +gdb_test "x" "add.b\t@\\(0x1234(:16|),er3\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "add.b @(0x1234:16,er3),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "add.b\t@\\(0x1234(:16|),er3\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "add.b @(0x1234:16,er3),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "add.b\t@\\(0x1234(:16|),er3\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "add.b @(0x1234:16,er3),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "add.b\t@\\(0x1234(:16|),er3\\),@0x9abc(:16|)" \ + "add.b @(0x1234:16,er3),@0x9abc:16" +gdb_test "x" "add.b\t@\\(0x1234(:16|),er3\\),@0x9abcdef0(:32|)" \ + "add.b @(0x1234:16,er3),@0x9abcdef0:32" +gdb_test "x" "add.b\t@\\(0x12345678(:32|),er3\\),@er1" \ + "add.b @(0x12345678:32,er3),@er1" +gdb_test "x" "add.b\t@\\(0x12345678(:32|),er3\\),@\\(0x3(:2|),er1\\)" \ + "add.b @(0x12345678:32,er3),@(0x3:2,er1)" +gdb_test "x" "add.b\t@\\(0x12345678(:32|),er3\\),@-er1" \ + "add.b @(0x12345678:32,er3),@-er1" +gdb_test "x" "add.b\t@\\(0x12345678(:32|),er3\\),@er1\\+" \ + "add.b @(0x12345678:32,er3),@er1+" +gdb_test "x" "add.b\t@\\(0x12345678(:32|),er3\\),@er1-" \ + "add.b @(0x12345678:32,er3),@er1-" +gdb_test "x" "add.b\t@\\(0x12345678(:32|),er3\\),@\\+er1" \ + "add.b @(0x12345678:32,er3),@+er1" +gdb_test "x" "add.b\t@\\(0x12345678(:32|),er3\\),@\\(0x9abc(:16|),er1\\)" \ + "add.b @(0x12345678:32,er3),@(0x9abc:16,er1)" +gdb_test "x" "add.b\t@\\(0x12345678(:32|),er3\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "add.b @(0x12345678:32,er3),@(0x9abcdef0:32,er1)" +gdb_test "x" "add.b\t@\\(0x12345678(:32|),er3\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "add.b @(0x12345678:32,er3),@(0x9abc:16,r2l.b)" +gdb_test "x" "add.b\t@\\(0x12345678(:32|),er3\\),@\\(0x9abc(:16|),r2.w\\)" \ + "add.b @(0x12345678:32,er3),@(0x9abc:16,r2.w)" +gdb_test "x" "add.b\t@\\(0x12345678(:32|),er3\\),@\\(0x9abc(:16|),er2.l\\)" \ + "add.b @(0x12345678:32,er3),@(0x9abc:16,er2.l)" +gdb_test "x" "add.b\t@\\(0x12345678(:32|),er3\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "add.b @(0x12345678:32,er3),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "add.b\t@\\(0x12345678(:32|),er3\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "add.b @(0x12345678:32,er3),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "add.b\t@\\(0x12345678(:32|),er3\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "add.b @(0x12345678:32,er3),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "add.b\t@\\(0x12345678(:32|),er3\\),@0x9abc(:16|)" \ + "add.b @(0x12345678:32,er3),@0x9abc:16" +gdb_test "x" "add.b\t@\\(0x12345678(:32|),er3\\),@0x9abcdef0(:32|)" \ + "add.b @(0x12345678:32,er3),@0x9abcdef0:32" +gdb_test "x" "add.b\t@\\(0x1234(:16|),r3l.b\\),@er1" \ + "add.b @(0x1234:16,r3l.b),@er1" +gdb_test "x" "add.b\t@\\(0x1234(:16|),r3l.b\\),@\\(0x3(:2|),er1\\)" \ + "add.b @(0x1234:16,r3l.b),@(0x3:2,er1)" +gdb_test "x" "add.b\t@\\(0x1234(:16|),r3l.b\\),@-er1" \ + "add.b @(0x1234:16,r3l.b),@-er1" +gdb_test "x" "add.b\t@\\(0x1234(:16|),r3l.b\\),@er1\\+" \ + "add.b @(0x1234:16,r3l.b),@er1+" +gdb_test "x" "add.b\t@\\(0x1234(:16|),r3l.b\\),@er1-" \ + "add.b @(0x1234:16,r3l.b),@er1-" +gdb_test "x" "add.b\t@\\(0x1234(:16|),r3l.b\\),@\\+er1" \ + "add.b @(0x1234:16,r3l.b),@+er1" +gdb_test "x" "add.b\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abc(:16|),er1\\)" \ + "add.b @(0x1234:16,r3l.b),@(0x9abc:16,er1)" +gdb_test "x" "add.b\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "add.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1)" +gdb_test "x" "add.b\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "add.b @(0x1234:16,r3l.b),@(0x9abc:16,r2l.b)" +gdb_test "x" "add.b\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abc(:16|),r2.w\\)" \ + "add.b @(0x1234:16,r3l.b),@(0x9abc:16,r2.w)" +gdb_test "x" "add.b\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abc(:16|),er2.l\\)" \ + "add.b @(0x1234:16,r3l.b),@(0x9abc:16,er2.l)" +gdb_test "x" "add.b\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "add.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "add.b\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "add.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "add.b\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "add.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "add.b\t@\\(0x1234(:16|),r3l.b\\),@0x9abc(:16|)" \ + "add.b @(0x1234:16,r3l.b),@0x9abc:16" +gdb_test "x" "add.b\t@\\(0x1234(:16|),r3l.b\\),@0x9abcdef0(:32|)" \ + "add.b @(0x1234:16,r3l.b),@0x9abcdef0:32" +gdb_test "x" "add.b\t@\\(0x1234(:16|),r3.w\\),@er1" \ + "add.b @(0x1234:16,r3.w),@er1" +gdb_test "x" "add.b\t@\\(0x1234(:16|),r3.w\\),@\\(0x3(:2|),er1\\)" \ + "add.b @(0x1234:16,r3.w),@(0x3:2,er1)" +gdb_test "x" "add.b\t@\\(0x1234(:16|),r3.w\\),@-er1" \ + "add.b @(0x1234:16,r3.w),@-er1" +gdb_test "x" "add.b\t@\\(0x1234(:16|),r3.w\\),@er1\\+" \ + "add.b @(0x1234:16,r3.w),@er1+" +gdb_test "x" "add.b\t@\\(0x1234(:16|),r3.w\\),@er1-" \ + "add.b @(0x1234:16,r3.w),@er1-" +gdb_test "x" "add.b\t@\\(0x1234(:16|),r3.w\\),@\\+er1" \ + "add.b @(0x1234:16,r3.w),@+er1" +gdb_test "x" "add.b\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abc(:16|),er1\\)" \ + "add.b @(0x1234:16,r3.w),@(0x9abc:16,er1)" +gdb_test "x" "add.b\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "add.b @(0x1234:16,r3.w),@(0x9abcdef0:32,er1)" +gdb_test "x" "add.b\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "add.b @(0x1234:16,r3.w),@(0x9abc:16,r2l.b)" +gdb_test "x" "add.b\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abc(:16|),r2.w\\)" \ + "add.b @(0x1234:16,r3.w),@(0x9abc:16,r2.w)" +gdb_test "x" "add.b\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abc(:16|),er2.l\\)" \ + "add.b @(0x1234:16,r3.w),@(0x9abc:16,er2.l)" +gdb_test "x" "add.b\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "add.b @(0x1234:16,r3.w),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "add.b\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "add.b @(0x1234:16,r3.w),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "add.b\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "add.b @(0x1234:16,r3.w),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "add.b\t@\\(0x1234(:16|),r3.w\\),@0x9abc(:16|)" \ + "add.b @(0x1234:16,r3.w),@0x9abc:16" +gdb_test "x" "add.b\t@\\(0x1234(:16|),r3.w\\),@0x9abcdef0(:32|)" \ + "add.b @(0x1234:16,r3.w),@0x9abcdef0:32" +gdb_test "x" "add.b\t@\\(0x1234(:16|),er3.l\\),@er1" \ + "add.b @(0x1234:16,er3.l),@er1" +gdb_test "x" "add.b\t@\\(0x1234(:16|),er3.l\\),@\\(0x3(:2|),er1\\)" \ + "add.b @(0x1234:16,er3.l),@(0x3:2,er1)" +gdb_test "x" "add.b\t@\\(0x1234(:16|),er3.l\\),@-er1" \ + "add.b @(0x1234:16,er3.l),@-er1" +gdb_test "x" "add.b\t@\\(0x1234(:16|),er3.l\\),@er1\\+" \ + "add.b @(0x1234:16,er3.l),@er1+" +gdb_test "x" "add.b\t@\\(0x1234(:16|),er3.l\\),@er1-" \ + "add.b @(0x1234:16,er3.l),@er1-" +gdb_test "x" "add.b\t@\\(0x1234(:16|),er3.l\\),@\\+er1" \ + "add.b @(0x1234:16,er3.l),@+er1" +gdb_test "x" "add.b\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abc(:16|),er1\\)" \ + "add.b @(0x1234:16,er3.l),@(0x9abc:16,er1)" +gdb_test "x" "add.b\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "add.b @(0x1234:16,er3.l),@(0x9abcdef0:32,er1)" +gdb_test "x" "add.b\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "add.b @(0x1234:16,er3.l),@(0x9abc:16,r2l.b)" +gdb_test "x" "add.b\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abc(:16|),r2.w\\)" \ + "add.b @(0x1234:16,er3.l),@(0x9abc:16,r2.w)" +gdb_test "x" "add.b\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abc(:16|),er2.l\\)" \ + "add.b @(0x1234:16,er3.l),@(0x9abc:16,er2.l)" +gdb_test "x" "add.b\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "add.b @(0x1234:16,er3.l),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "add.b\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "add.b @(0x1234:16,er3.l),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "add.b\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "add.b @(0x1234:16,er3.l),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "add.b\t@\\(0x1234(:16|),er3.l\\),@0x9abc(:16|)" \ + "add.b @(0x1234:16,er3.l),@0x9abc:16" +gdb_test "x" "add.b\t@\\(0x1234(:16|),er3.l\\),@0x9abcdef0(:32|)" \ + "add.b @(0x1234:16,er3.l),@0x9abcdef0:32" +gdb_test "x" "add.b\t@\\(0x12345678(:32|),r3l.b\\),@er1" \ + "add.b @(0x12345678:32,r3l.b),@er1" +gdb_test "x" "add.b\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x3(:2|),er1\\)" \ + "add.b @(0x12345678:32,r3l.b),@(0x3:2,er1)" +gdb_test "x" "add.b\t@\\(0x12345678(:32|),r3l.b\\),@-er1" \ + "add.b @(0x12345678:32,r3l.b),@-er1" +gdb_test "x" "add.b\t@\\(0x12345678(:32|),r3l.b\\),@er1\\+" \ + "add.b @(0x12345678:32,r3l.b),@er1+" +gdb_test "x" "add.b\t@\\(0x12345678(:32|),r3l.b\\),@er1-" \ + "add.b @(0x12345678:32,r3l.b),@er1-" +gdb_test "x" "add.b\t@\\(0x12345678(:32|),r3l.b\\),@\\+er1" \ + "add.b @(0x12345678:32,r3l.b),@+er1" +gdb_test "x" "add.b\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abc(:16|),er1\\)" \ + "add.b @(0x12345678:32,r3l.b),@(0x9abc:16,er1)" +gdb_test "x" "add.b\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "add.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1)" +gdb_test "x" "add.b\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "add.b @(0x12345678:32,r3l.b),@(0x9abc:16,r2l.b)" +gdb_test "x" "add.b\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abc(:16|),r2.w\\)" \ + "add.b @(0x12345678:32,r3l.b),@(0x9abc:16,r2.w)" +gdb_test "x" "add.b\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abc(:16|),er2.l\\)" \ + "add.b @(0x12345678:32,r3l.b),@(0x9abc:16,er2.l)" +gdb_test "x" "add.b\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "add.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "add.b\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "add.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "add.b\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "add.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "add.b\t@\\(0x12345678(:32|),r3l.b\\),@0x9abc(:16|)" \ + "add.b @(0x12345678:32,r3l.b),@0x9abc:16" +gdb_test "x" "add.b\t@\\(0x12345678(:32|),r3l.b\\),@0x9abcdef0(:32|)" \ + "add.b @(0x12345678:32,r3l.b),@0x9abcdef0:32" +gdb_test "x" "add.b\t@\\(0x12345678(:32|),r3.w\\),@er1" \ + "add.b @(0x12345678:32,r3.w),@er1" +gdb_test "x" "add.b\t@\\(0x12345678(:32|),r3.w\\),@\\(0x3(:2|),er1\\)" \ + "add.b @(0x12345678:32,r3.w),@(0x3:2,er1)" +gdb_test "x" "add.b\t@\\(0x12345678(:32|),r3.w\\),@-er1" \ + "add.b @(0x12345678:32,r3.w),@-er1" +gdb_test "x" "add.b\t@\\(0x12345678(:32|),r3.w\\),@er1\\+" \ + "add.b @(0x12345678:32,r3.w),@er1+" +gdb_test "x" "add.b\t@\\(0x12345678(:32|),r3.w\\),@er1-" \ + "add.b @(0x12345678:32,r3.w),@er1-" +gdb_test "x" "add.b\t@\\(0x12345678(:32|),r3.w\\),@\\+er1" \ + "add.b @(0x12345678:32,r3.w),@+er1" +gdb_test "x" "add.b\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abc(:16|),er1\\)" \ + "add.b @(0x12345678:32,r3.w),@(0x9abc:16,er1)" +gdb_test "x" "add.b\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "add.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1)" +gdb_test "x" "add.b\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "add.b @(0x12345678:32,r3.w),@(0x9abc:16,r2l.b)" +gdb_test "x" "add.b\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abc(:16|),r2.w\\)" \ + "add.b @(0x12345678:32,r3.w),@(0x9abc:16,r2.w)" +gdb_test "x" "add.b\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abc(:16|),er2.l\\)" \ + "add.b @(0x12345678:32,r3.w),@(0x9abc:16,er2.l)" +gdb_test "x" "add.b\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "add.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "add.b\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "add.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "add.b\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "add.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "add.b\t@\\(0x12345678(:32|),r3.w\\),@0x9abc(:16|)" \ + "add.b @(0x12345678:32,r3.w),@0x9abc:16" +gdb_test "x" "add.b\t@\\(0x12345678(:32|),r3.w\\),@0x9abcdef0(:32|)" \ + "add.b @(0x12345678:32,r3.w),@0x9abcdef0:32" +gdb_test "x" "add.b\t@\\(0x12345678(:32|),er3.l\\),@er1" \ + "add.b @(0x12345678:32,er3.l),@er1" +gdb_test "x" "add.b\t@\\(0x12345678(:32|),er3.l\\),@\\(0x3(:2|),er1\\)" \ + "add.b @(0x12345678:32,er3.l),@(0x3:2,er1)" +gdb_test "x" "add.b\t@\\(0x12345678(:32|),er3.l\\),@-er1" \ + "add.b @(0x12345678:32,er3.l),@-er1" +gdb_test "x" "add.b\t@\\(0x12345678(:32|),er3.l\\),@er1\\+" \ + "add.b @(0x12345678:32,er3.l),@er1+" +gdb_test "x" "add.b\t@\\(0x12345678(:32|),er3.l\\),@er1-" \ + "add.b @(0x12345678:32,er3.l),@er1-" +gdb_test "x" "add.b\t@\\(0x12345678(:32|),er3.l\\),@\\+er1" \ + "add.b @(0x12345678:32,er3.l),@+er1" +gdb_test "x" "add.b\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abc(:16|),er1\\)" \ + "add.b @(0x12345678:32,er3.l),@(0x9abc:16,er1)" +gdb_test "x" "add.b\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "add.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1)" +gdb_test "x" "add.b\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "add.b @(0x12345678:32,er3.l),@(0x9abc:16,r2l.b)" +gdb_test "x" "add.b\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abc(:16|),r2.w\\)" \ + "add.b @(0x12345678:32,er3.l),@(0x9abc:16,r2.w)" +gdb_test "x" "add.b\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abc(:16|),er2.l\\)" \ + "add.b @(0x12345678:32,er3.l),@(0x9abc:16,er2.l)" +gdb_test "x" "add.b\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "add.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "add.b\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "add.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "add.b\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "add.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "add.b\t@\\(0x12345678(:32|),er3.l\\),@0x9abc(:16|)" \ + "add.b @(0x12345678:32,er3.l),@0x9abc:16" +gdb_test "x" "add.b\t@\\(0x12345678(:32|),er3.l\\),@0x9abcdef0(:32|)" \ + "add.b @(0x12345678:32,er3.l),@0x9abcdef0:32" +gdb_test "x" "add.b\t@0x1234(:16|),@er1" \ + "add.b @0x1234:16,@er1" +gdb_test "x" "add.b\t@0x1234(:16|),@\\(0x3(:2|),er1\\)" \ + "add.b @0x1234:16,@(0x3:2,er1)" +gdb_test "x" "add.b\t@0x1234(:16|),@-er1" \ + "add.b @0x1234:16,@-er1" +gdb_test "x" "add.b\t@0x1234(:16|),@er1\\+" \ + "add.b @0x1234:16,@er1+" +gdb_test "x" "add.b\t@0x1234(:16|),@er1-" \ + "add.b @0x1234:16,@er1-" +gdb_test "x" "add.b\t@0x1234(:16|),@\\+er1" \ + "add.b @0x1234:16,@+er1" +gdb_test "x" "add.b\t@0x1234(:16|),@\\(0x9abc(:16|),er1\\)" \ + "add.b @0x1234:16,@(0x9abc:16,er1)" +gdb_test "x" "add.b\t@0x1234(:16|),@\\(0x9abcdef0(:32|),er1\\)" \ + "add.b @0x1234:16,@(0x9abcdef0:32,er1)" +gdb_test "x" "add.b\t@0x1234(:16|),@\\(0x9abc(:16|),r2l.b\\)" \ + "add.b @0x1234:16,@(0x9abc:16,r2l.b)" +gdb_test "x" "add.b\t@0x1234(:16|),@\\(0x9abc(:16|),r2.w\\)" \ + "add.b @0x1234:16,@(0x9abc:16,r2.w)" +gdb_test "x" "add.b\t@0x1234(:16|),@\\(0x9abc(:16|),er2.l\\)" \ + "add.b @0x1234:16,@(0x9abc:16,er2.l)" +gdb_test "x" "add.b\t@0x1234(:16|),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "add.b @0x1234:16,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "add.b\t@0x1234(:16|),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "add.b @0x1234:16,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "add.b\t@0x1234(:16|),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "add.b @0x1234:16,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "add.b\t@0x1234(:16|),@0x9abc(:16|)" \ + "add.b @0x1234:16,@0x9abc:16" +gdb_test "x" "add.b\t@0x1234(:16|),@0x9abcdef0(:32|)" \ + "add.b @0x1234:16,@0x9abcdef0:32" +gdb_test "x" "add.b\t@0x12345678(:32|),@er1" \ + "add.b @0x12345678:32,@er1" +gdb_test "x" "add.b\t@0x12345678(:32|),@\\(0x3(:2|),er1\\)" \ + "add.b @0x12345678:32,@(0x3:2,er1)" +gdb_test "x" "add.b\t@0x12345678(:32|),@-er1" \ + "add.b @0x12345678:32,@-er1" +gdb_test "x" "add.b\t@0x12345678(:32|),@er1\\+" \ + "add.b @0x12345678:32,@er1+" +gdb_test "x" "add.b\t@0x12345678(:32|),@er1-" \ + "add.b @0x12345678:32,@er1-" +gdb_test "x" "add.b\t@0x12345678(:32|),@\\+er1" \ + "add.b @0x12345678:32,@+er1" +gdb_test "x" "add.b\t@0x12345678(:32|),@\\(0x9abc(:16|),er1\\)" \ + "add.b @0x12345678:32,@(0x9abc:16,er1)" +gdb_test "x" "add.b\t@0x12345678(:32|),@\\(0x9abcdef0(:32|),er1\\)" \ + "add.b @0x12345678:32,@(0x9abcdef0:32,er1)" +gdb_test "x" "add.b\t@0x12345678(:32|),@\\(0x9abc(:16|),r2l.b\\)" \ + "add.b @0x12345678:32,@(0x9abc:16,r2l.b)" +gdb_test "x" "add.b\t@0x12345678(:32|),@\\(0x9abc(:16|),r2.w\\)" \ + "add.b @0x12345678:32,@(0x9abc:16,r2.w)" +gdb_test "x" "add.b\t@0x12345678(:32|),@\\(0x9abc(:16|),er2.l\\)" \ + "add.b @0x12345678:32,@(0x9abc:16,er2.l)" +gdb_test "x" "add.b\t@0x12345678(:32|),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "add.b @0x12345678:32,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "add.b\t@0x12345678(:32|),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "add.b @0x12345678:32,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "add.b\t@0x12345678(:32|),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "add.b @0x12345678:32,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "add.b\t@0x12345678(:32|),@0x9abc(:16|)" \ + "add.b @0x12345678:32,@0x9abc:16" +gdb_test "x" "add.b\t@0x12345678(:32|),@0x9abcdef0(:32|)" \ + "add.b @0x12345678:32,@0x9abcdef0:32" +gdb_test "x" "add.w\t#0x1234(:16|),r1" \ + "add.w #0x1234:16,r1" +gdb_test "x" "add.w\t#0x7(:3|),r2" \ + "add.w #0x7:3,r2" +gdb_test "x" "add.w\t#0x1234(:16|),@er1" \ + "add.w #0x1234:16,@er1" +gdb_test "x" "add.w\t#0x1234(:16|),@\\(0x6(:2|),er1\\)" \ + "add.w #0x1234:16,@(0x6:2,er1)" +gdb_test "x" "add.w\t#0x1234(:16|),@er1\\+" \ + "add.w #0x1234:16,@er1+" +gdb_test "x" "add.w\t#0x1234(:16|),@-er1" \ + "add.w #0x1234:16,@-er1" +gdb_test "x" "add.w\t#0x1234(:16|),@\\+er1" \ + "add.w #0x1234:16,@+er1" +gdb_test "x" "add.w\t#0x1234(:16|),@er1-" \ + "add.w #0x1234:16,@er1-" +gdb_test "x" "add.w\t#0x1234(:16|),@\\(0x9abc(:16|),er1\\)" \ + "add.w #0x1234:16,@(0x9abc:16,er1)" +gdb_test "x" "add.w\t#0x1234(:16|),@\\(0x9abcdef0(:32|),er1\\)" \ + "add.w #0x1234:16,@(0x9abcdef0:32,er1)" +gdb_test "x" "add.w\t#0x1234(:16|),@\\(0x9abc(:16|),r2l.b\\)" \ + "add.w #0x1234:16,@(0x9abc:16,r2l.b)" +gdb_test "x" "add.w\t#0x1234(:16|),@\\(0x9abc(:16|),r2.w\\)" \ + "add.w #0x1234:16,@(0x9abc:16,r2.w)" +gdb_test "x" "add.w\t#0x1234(:16|),@\\(0x9abc(:16|),er2.l\\)" \ + "add.w #0x1234:16,@(0x9abc:16,er2.l)" +gdb_test "x" "add.w\t#0x1234(:16|),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "add.w #0x1234:16,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "add.w\t#0x1234(:16|),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "add.w #0x1234:16,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "add.w\t#0x1234(:16|),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "add.w #0x1234:16,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "add.w\t#0x1234(:16|),@0x9abc(:16|)" \ + "add.w #0x1234:16,@0x9abc:16" +gdb_test "x" "add.w\t#0x1234(:16|),@0x9abcdef0(:32|)" \ + "add.w #0x1234:16,@0x9abcdef0:32" +gdb_test "x" "add.w\t#0x7(:3|),@er1" \ + "add.w #0x7:3,@er1" +gdb_test "x" "add.w\t#0x7(:3|),@0x1234(:16|)" \ + "add.w #0x7:3,@0x1234:16" +gdb_test "x" "add.w\t#0x7(:3|),@0x12345678(:32|)" \ + "add.w #0x7:3,@0x12345678:32" +gdb_test "x" "add.w\tr3,r1" \ + "add.w r3,r1" +gdb_test "x" "add.w\tr3,@er1" \ + "add.w r3,@er1" +gdb_test "x" "add.w\tr3,@\\(0x6(:2|),er1\\)" \ + "add.w r3,@(0x6:2,er1)" +gdb_test "x" "add.w\tr3,@er1\\+" \ + "add.w r3,@er1+" +gdb_test "x" "add.w\tr3,@-er1" \ + "add.w r3,@-er1" +gdb_test "x" "add.w\tr3,@\\+er1" \ + "add.w r3,@+er1" +gdb_test "x" "add.w\tr3,@er1-" \ + "add.w r3,@er1-" +gdb_test "x" "add.w\tr3,@\\(0x1234(:16|),er1\\)" \ + "add.w r3,@(0x1234:16,er1)" +gdb_test "x" "add.w\tr3,@\\(0x12345678(:32|),er1\\)" \ + "add.w r3,@(0x12345678:32,er1)" +gdb_test "x" "add.w\tr3,@\\(0x1234(:16|),r2l.b\\)" \ + "add.w r3,@(0x1234:16,r2l.b)" +gdb_test "x" "add.w\tr3,@\\(0x1234(:16|),r2.w\\)" \ + "add.w r3,@(0x1234:16,r2.w)" +gdb_test "x" "add.w\tr3,@\\(0x1234(:16|),er2.l\\)" \ + "add.w r3,@(0x1234:16,er2.l)" +gdb_test "x" "add.w\tr3,@\\(0x12345678(:32|),r2l.b\\)" \ + "add.w r3,@(0x12345678:32,r2l.b)" +gdb_test "x" "add.w\tr3,@\\(0x12345678(:32|),r2.w\\)" \ + "add.w r3,@(0x12345678:32,r2.w)" +gdb_test "x" "add.w\tr3,@\\(0x12345678(:32|),er2.l\\)" \ + "add.w r3,@(0x12345678:32,er2.l)" +gdb_test "x" "add.w\tr3,@0x1234(:16|)" \ + "add.w r3,@0x1234:16" +gdb_test "x" "add.w\tr3,@0x12345678(:32|)" \ + "add.w r3,@0x12345678:32" +gdb_test "x" "add.w\t@er3,r1" \ + "add.w @er3,r1" +gdb_test "x" "add.w\t@\\(0x6(:2|),er1\\),r1" \ + "add.w @(0x6:2,er1),r1" +gdb_test "x" "add.w\t@er3\\+,r1" \ + "add.w @er3+,r1" +gdb_test "x" "add.w\t@-er3,r1" \ + "add.w @-er3,r1" +gdb_test "x" "add.w\t@\\+er3,r1" \ + "add.w @+er3,r1" +gdb_test "x" "add.w\t@er3-,r1" \ + "add.w @er3-,r1" +gdb_test "x" "add.w\t@\\(0x1234(:16|),er1\\),r1" \ + "add.w @(0x1234:16,er1),r1" +gdb_test "x" "add.w\t@\\(0x12345678(:32|),er1\\),r1" \ + "add.w @(0x12345678:32,er1),r1" +gdb_test "x" "add.w\t@\\(0x1234(:16|),r2l.b\\),r1" \ + "add.w @(0x1234:16,r2l.b),r1" +gdb_test "x" "add.w\t@\\(0x1234(:16|),r2.w\\),r1" \ + "add.w @(0x1234:16,r2.w),r1" +gdb_test "x" "add.w\t@\\(0x1234(:16|),er2.l\\),r1" \ + "add.w @(0x1234:16,er2.l),r1" +gdb_test "x" "add.w\t@\\(0x12345678(:32|),r2l.b\\),r1" \ + "add.w @(0x12345678:32,r2l.b),r1" +gdb_test "x" "add.w\t@\\(0x12345678(:32|),r2.w\\),r1" \ + "add.w @(0x12345678:32,r2.w),r1" +gdb_test "x" "add.w\t@\\(0x12345678(:32|),er2.l\\),r1" \ + "add.w @(0x12345678:32,er2.l),r1" +gdb_test "x" "add.w\t@0x1234(:16|),r1" \ + "add.w @0x1234:16,r1" +gdb_test "x" "add.w\t@0x12345678(:32|),r1" \ + "add.w @0x12345678:32,r1" +gdb_test "x" "add.w\t@er3,@er1" \ + "add.w @er3,@er1" +gdb_test "x" "add.w\t@er3,@\\(0x6(:2|),er1\\)" \ + "add.w @er3,@(0x6:2,er1)" +gdb_test "x" "add.w\t@er3,@-er1" \ + "add.w @er3,@-er1" +gdb_test "x" "add.w\t@er3,@er1\\+" \ + "add.w @er3,@er1+" +gdb_test "x" "add.w\t@er3,@er1-" \ + "add.w @er3,@er1-" +gdb_test "x" "add.w\t@er3,@\\+er1" \ + "add.w @er3,@+er1" +gdb_test "x" "add.w\t@er3,@\\(0x9abc(:16|),er1\\)" \ + "add.w @er3,@(0x9abc:16,er1)" +gdb_test "x" "add.w\t@er3,@\\(0x9abcdef0(:32|),er1\\)" \ + "add.w @er3,@(0x9abcdef0:32,er1)" +gdb_test "x" "add.w\t@er3,@\\(0x9abc(:16|),r2l.b\\)" \ + "add.w @er3,@(0x9abc:16,r2l.b)" +gdb_test "x" "add.w\t@er3,@\\(0x9abc(:16|),r2.w\\)" \ + "add.w @er3,@(0x9abc:16,r2.w)" +gdb_test "x" "add.w\t@er3,@\\(0x9abc(:16|),er2.l\\)" \ + "add.w @er3,@(0x9abc:16,er2.l)" +gdb_test "x" "add.w\t@er3,@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "add.w @er3,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "add.w\t@er3,@\\(0x9abcdef0(:32|),r2.w\\)" \ + "add.w @er3,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "add.w\t@er3,@\\(0x9abcdef0(:32|),er2.l\\)" \ + "add.w @er3,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "add.w\t@er3,@0x9abc(:16|)" \ + "add.w @er3,@0x9abc:16" +gdb_test "x" "add.w\t@er3,@0x9abcdef0(:32|)" \ + "add.w @er3,@0x9abcdef0:32" +gdb_test "x" "add.w\t@-er3,@er1" \ + "add.w @-er3,@er1" +gdb_test "x" "add.w\t@-er3,@\\(0x6(:2|),er1\\)" \ + "add.w @-er3,@(0x6:2,er1)" +gdb_test "x" "add.w\t@-er3,@-er1" \ + "add.w @-er3,@-er1" +gdb_test "x" "add.w\t@-er3,@er1\\+" \ + "add.w @-er3,@er1+" +gdb_test "x" "add.w\t@-er3,@er1-" \ + "add.w @-er3,@er1-" +gdb_test "x" "add.w\t@-er3,@\\+er1" \ + "add.w @-er3,@+er1" +gdb_test "x" "add.w\t@-er3,@\\(0x9abc(:16|),er1\\)" \ + "add.w @-er3,@(0x9abc:16,er1)" +gdb_test "x" "add.w\t@-er3,@\\(0x9abcdef0(:32|),er1\\)" \ + "add.w @-er3,@(0x9abcdef0:32,er1)" +gdb_test "x" "add.w\t@-er3,@\\(0x9abc(:16|),r2l.b\\)" \ + "add.w @-er3,@(0x9abc:16,r2l.b)" +gdb_test "x" "add.w\t@-er3,@\\(0x9abc(:16|),r2.w\\)" \ + "add.w @-er3,@(0x9abc:16,r2.w)" +gdb_test "x" "add.w\t@-er3,@\\(0x9abc(:16|),er2.l\\)" \ + "add.w @-er3,@(0x9abc:16,er2.l)" +gdb_test "x" "add.w\t@-er3,@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "add.w @-er3,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "add.w\t@-er3,@\\(0x9abcdef0(:32|),r2.w\\)" \ + "add.w @-er3,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "add.w\t@-er3,@\\(0x9abcdef0(:32|),er2.l\\)" \ + "add.w @-er3,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "add.w\t@-er3,@0x9abc(:16|)" \ + "add.w @-er3,@0x9abc:16" +gdb_test "x" "add.w\t@-er3,@0x9abcdef0(:32|)" \ + "add.w @-er3,@0x9abcdef0:32" +gdb_test "x" "add.w\t@er3\\+,@er1" \ + "add.w @er3+,@er1" +gdb_test "x" "add.w\t@er3\\+,@\\(0x6(:2|),er1\\)" \ + "add.w @er3+,@(0x6:2,er1)" +gdb_test "x" "add.w\t@er3\\+,@-er1" \ + "add.w @er3+,@-er1" +gdb_test "x" "add.w\t@er3\\+,@er1\\+" \ + "add.w @er3+,@er1+" +gdb_test "x" "add.w\t@er3\\+,@er1-" \ + "add.w @er3+,@er1-" +gdb_test "x" "add.w\t@er3\\+,@\\+er1" \ + "add.w @er3+,@+er1" +gdb_test "x" "add.w\t@er3\\+,@\\(0x9abc(:16|),er1\\)" \ + "add.w @er3+,@(0x9abc:16,er1)" +gdb_test "x" "add.w\t@er3\\+,@\\(0x9abcdef0(:32|),er1\\)" \ + "add.w @er3+,@(0x9abcdef0:32,er1)" +gdb_test "x" "add.w\t@er3\\+,@\\(0x9abc(:16|),r2l.b\\)" \ + "add.w @er3+,@(0x9abc:16,r2l.b)" +gdb_test "x" "add.w\t@er3\\+,@\\(0x9abc(:16|),r2.w\\)" \ + "add.w @er3+,@(0x9abc:16,r2.w)" +gdb_test "x" "add.w\t@er3\\+,@\\(0x9abc(:16|),er2.l\\)" \ + "add.w @er3+,@(0x9abc:16,er2.l)" +gdb_test "x" "add.w\t@er3\\+,@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "add.w @er3+,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "add.w\t@er3\\+,@\\(0x9abcdef0(:32|),r2.w\\)" \ + "add.w @er3+,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "add.w\t@er3\\+,@\\(0x9abcdef0(:32|),er2.l\\)" \ + "add.w @er3+,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "add.w\t@er3\\+,@0x9abc(:16|)" \ + "add.w @er3+,@0x9abc:16" +gdb_test "x" "add.w\t@er3\\+,@0x9abcdef0(:32|)" \ + "add.w @er3+,@0x9abcdef0:32" +gdb_test "x" "add.w\t@er3-,@er1" \ + "add.w @er3-,@er1" +gdb_test "x" "add.w\t@er3-,@\\(0x6(:2|),er1\\)" \ + "add.w @er3-,@(0x6:2,er1)" +gdb_test "x" "add.w\t@er3-,@-er1" \ + "add.w @er3-,@-er1" +gdb_test "x" "add.w\t@er3-,@er1\\+" \ + "add.w @er3-,@er1+" +gdb_test "x" "add.w\t@er3-,@er1-" \ + "add.w @er3-,@er1-" +gdb_test "x" "add.w\t@er3-,@\\+er1" \ + "add.w @er3-,@+er1" +gdb_test "x" "add.w\t@er3-,@\\(0x9abc(:16|),er1\\)" \ + "add.w @er3-,@(0x9abc:16,er1)" +gdb_test "x" "add.w\t@er3-,@\\(0x9abcdef0(:32|),er1\\)" \ + "add.w @er3-,@(0x9abcdef0:32,er1)" +gdb_test "x" "add.w\t@er3-,@\\(0x9abc(:16|),r2l.b\\)" \ + "add.w @er3-,@(0x9abc:16,r2l.b)" +gdb_test "x" "add.w\t@er3-,@\\(0x9abc(:16|),r2.w\\)" \ + "add.w @er3-,@(0x9abc:16,r2.w)" +gdb_test "x" "add.w\t@er3-,@\\(0x9abc(:16|),er2.l\\)" \ + "add.w @er3-,@(0x9abc:16,er2.l)" +gdb_test "x" "add.w\t@er3-,@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "add.w @er3-,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "add.w\t@er3-,@\\(0x9abcdef0(:32|),r2.w\\)" \ + "add.w @er3-,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "add.w\t@er3-,@\\(0x9abcdef0(:32|),er2.l\\)" \ + "add.w @er3-,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "add.w\t@er3-,@0x9abc(:16|)" \ + "add.w @er3-,@0x9abc:16" +gdb_test "x" "add.w\t@er3-,@0x9abcdef0(:32|)" \ + "add.w @er3-,@0x9abcdef0:32" +gdb_test "x" "add.w\t@\\+er3,@er1" \ + "add.w @+er3,@er1" +gdb_test "x" "add.w\t@\\+er3,@\\(0x6(:2|),er1\\)" \ + "add.w @+er3,@(0x6:2,er1)" +gdb_test "x" "add.w\t@\\+er3,@-er1" \ + "add.w @+er3,@-er1" +gdb_test "x" "add.w\t@\\+er3,@er1\\+" \ + "add.w @+er3,@er1+" +gdb_test "x" "add.w\t@\\+er3,@er1-" \ + "add.w @+er3,@er1-" +gdb_test "x" "add.w\t@\\+er3,@\\+er1" \ + "add.w @+er3,@+er1" +gdb_test "x" "add.w\t@\\+er3,@\\(0x9abc(:16|),er1\\)" \ + "add.w @+er3,@(0x9abc:16,er1)" +gdb_test "x" "add.w\t@\\+er3,@\\(0x9abcdef0(:32|),er1\\)" \ + "add.w @+er3,@(0x9abcdef0:32,er1)" +gdb_test "x" "add.w\t@\\+er3,@\\(0x9abc(:16|),r2l.b\\)" \ + "add.w @+er3,@(0x9abc:16,r2l.b)" +gdb_test "x" "add.w\t@\\+er3,@\\(0x9abc(:16|),r2.w\\)" \ + "add.w @+er3,@(0x9abc:16,r2.w)" +gdb_test "x" "add.w\t@\\+er3,@\\(0x9abc(:16|),er2.l\\)" \ + "add.w @+er3,@(0x9abc:16,er2.l)" +gdb_test "x" "add.w\t@\\+er3,@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "add.w @+er3,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "add.w\t@\\+er3,@\\(0x9abcdef0(:32|),r2.w\\)" \ + "add.w @+er3,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "add.w\t@\\+er3,@\\(0x9abcdef0(:32|),er2.l\\)" \ + "add.w @+er3,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "add.w\t@\\+er3,@0x9abc(:16|)" \ + "add.w @+er3,@0x9abc:16" +gdb_test "x" "add.w\t@\\+er3,@0x9abcdef0(:32|)" \ + "add.w @+er3,@0x9abcdef0:32" +gdb_test "x" "add.w\t@\\(0x1234(:16|),er3\\),@er1" \ + "add.w @(0x1234:16,er3),@er1" +gdb_test "x" "add.w\t@\\(0x1234(:16|),er3\\),@\\(0x6(:2|),er1\\)" \ + "add.w @(0x1234:16,er3),@(0x6:2,er1)" +gdb_test "x" "add.w\t@\\(0x1234(:16|),er3\\),@-er1" \ + "add.w @(0x1234:16,er3),@-er1" +gdb_test "x" "add.w\t@\\(0x1234(:16|),er3\\),@er1\\+" \ + "add.w @(0x1234:16,er3),@er1+" +gdb_test "x" "add.w\t@\\(0x1234(:16|),er3\\),@er1-" \ + "add.w @(0x1234:16,er3),@er1-" +gdb_test "x" "add.w\t@\\(0x1234(:16|),er3\\),@\\+er1" \ + "add.w @(0x1234:16,er3),@+er1" +gdb_test "x" "add.w\t@\\(0x1234(:16|),er3\\),@\\(0x9abc(:16|),er1\\)" \ + "add.w @(0x1234:16,er3),@(0x9abc:16,er1)" +gdb_test "x" "add.w\t@\\(0x1234(:16|),er3\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "add.w @(0x1234:16,er3),@(0x9abcdef0:32,er1)" +gdb_test "x" "add.w\t@\\(0x1234(:16|),er3\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "add.w @(0x1234:16,er3),@(0x9abc:16,r2l.b)" +gdb_test "x" "add.w\t@\\(0x1234(:16|),er3\\),@\\(0x9abc(:16|),r2.w\\)" \ + "add.w @(0x1234:16,er3),@(0x9abc:16,r2.w)" +gdb_test "x" "add.w\t@\\(0x1234(:16|),er3\\),@\\(0x9abc(:16|),er2.l\\)" \ + "add.w @(0x1234:16,er3),@(0x9abc:16,er2.l)" +gdb_test "x" "add.w\t@\\(0x1234(:16|),er3\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "add.w @(0x1234:16,er3),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "add.w\t@\\(0x1234(:16|),er3\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "add.w @(0x1234:16,er3),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "add.w\t@\\(0x1234(:16|),er3\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "add.w @(0x1234:16,er3),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "add.w\t@\\(0x1234(:16|),er3\\),@0x9abc(:16|)" \ + "add.w @(0x1234:16,er3),@0x9abc:16" +gdb_test "x" "add.w\t@\\(0x1234(:16|),er3\\),@0x9abcdef0(:32|)" \ + "add.w @(0x1234:16,er3),@0x9abcdef0:32" +gdb_test "x" "add.w\t@\\(0x12345678(:32|),er3\\),@er1" \ + "add.w @(0x12345678:32,er3),@er1" +gdb_test "x" "add.w\t@\\(0x12345678(:32|),er3\\),@\\(0x6(:2|),er1\\)" \ + "add.w @(0x12345678:32,er3),@(0x6:2,er1)" +gdb_test "x" "add.w\t@\\(0x12345678(:32|),er3\\),@-er1" \ + "add.w @(0x12345678:32,er3),@-er1" +gdb_test "x" "add.w\t@\\(0x12345678(:32|),er3\\),@er1\\+" \ + "add.w @(0x12345678:32,er3),@er1+" +gdb_test "x" "add.w\t@\\(0x12345678(:32|),er3\\),@er1-" \ + "add.w @(0x12345678:32,er3),@er1-" +gdb_test "x" "add.w\t@\\(0x12345678(:32|),er3\\),@\\+er1" \ + "add.w @(0x12345678:32,er3),@+er1" +gdb_test "x" "add.w\t@\\(0x12345678(:32|),er3\\),@\\(0x9abc(:16|),er1\\)" \ + "add.w @(0x12345678:32,er3),@(0x9abc:16,er1)" +gdb_test "x" "add.w\t@\\(0x12345678(:32|),er3\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "add.w @(0x12345678:32,er3),@(0x9abcdef0:32,er1)" +gdb_test "x" "add.w\t@\\(0x12345678(:32|),er3\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "add.w @(0x12345678:32,er3),@(0x9abc:16,r2l.b)" +gdb_test "x" "add.w\t@\\(0x12345678(:32|),er3\\),@\\(0x9abc(:16|),r2.w\\)" \ + "add.w @(0x12345678:32,er3),@(0x9abc:16,r2.w)" +gdb_test "x" "add.w\t@\\(0x12345678(:32|),er3\\),@\\(0x9abc(:16|),er2.l\\)" \ + "add.w @(0x12345678:32,er3),@(0x9abc:16,er2.l)" +gdb_test "x" "add.w\t@\\(0x12345678(:32|),er3\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "add.w @(0x12345678:32,er3),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "add.w\t@\\(0x12345678(:32|),er3\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "add.w @(0x12345678:32,er3),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "add.w\t@\\(0x12345678(:32|),er3\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "add.w @(0x12345678:32,er3),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "add.w\t@\\(0x12345678(:32|),er3\\),@0x9abc(:16|)" \ + "add.w @(0x12345678:32,er3),@0x9abc:16" +gdb_test "x" "add.w\t@\\(0x12345678(:32|),er3\\),@0x9abcdef0(:32|)" \ + "add.w @(0x12345678:32,er3),@0x9abcdef0:32" +gdb_test "x" "add.w\t@\\(0x1234(:16|),r3l.b\\),@er1" \ + "add.w @(0x1234:16,r3l.b),@er1" +gdb_test "x" "add.w\t@\\(0x1234(:16|),r3l.b\\),@\\(0x6(:2|),er1\\)" \ + "add.w @(0x1234:16,r3l.b),@(0x6:2,er1)" +gdb_test "x" "add.w\t@\\(0x1234(:16|),r3l.b\\),@-er1" \ + "add.w @(0x1234:16,r3l.b),@-er1" +gdb_test "x" "add.w\t@\\(0x1234(:16|),r3l.b\\),@er1\\+" \ + "add.w @(0x1234:16,r3l.b),@er1+" +gdb_test "x" "add.w\t@\\(0x1234(:16|),r3l.b\\),@er1-" \ + "add.w @(0x1234:16,r3l.b),@er1-" +gdb_test "x" "add.w\t@\\(0x1234(:16|),r3l.b\\),@\\+er1" \ + "add.w @(0x1234:16,r3l.b),@+er1" +gdb_test "x" "add.w\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abc(:16|),er1\\)" \ + "add.w @(0x1234:16,r3l.b),@(0x9abc:16,er1)" +gdb_test "x" "add.w\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "add.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1)" +gdb_test "x" "add.w\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "add.w @(0x1234:16,r3l.b),@(0x9abc:16,r2l.b)" +gdb_test "x" "add.w\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abc(:16|),r2.w\\)" \ + "add.w @(0x1234:16,r3l.b),@(0x9abc:16,r2.w)" +gdb_test "x" "add.w\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abc(:16|),er2.l\\)" \ + "add.w @(0x1234:16,r3l.b),@(0x9abc:16,er2.l)" +gdb_test "x" "add.w\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "add.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "add.w\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "add.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "add.w\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "add.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "add.w\t@\\(0x1234(:16|),r3l.b\\),@0x9abc(:16|)" \ + "add.w @(0x1234:16,r3l.b),@0x9abc:16" +gdb_test "x" "add.w\t@\\(0x1234(:16|),r3l.b\\),@0x9abcdef0(:32|)" \ + "add.w @(0x1234:16,r3l.b),@0x9abcdef0:32" +gdb_test "x" "add.w\t@\\(0x1234(:16|),r3.w\\),@er1" \ + "add.w @(0x1234:16,r3.w),@er1" +gdb_test "x" "add.w\t@\\(0x1234(:16|),r3.w\\),@\\(0x6(:2|),er1\\)" \ + "add.w @(0x1234:16,r3.w),@(0x6:2,er1)" +gdb_test "x" "add.w\t@\\(0x1234(:16|),r3.w\\),@-er1" \ + "add.w @(0x1234:16,r3.w),@-er1" +gdb_test "x" "add.w\t@\\(0x1234(:16|),r3.w\\),@er1\\+" \ + "add.w @(0x1234:16,r3.w),@er1+" +gdb_test "x" "add.w\t@\\(0x1234(:16|),r3.w\\),@er1-" \ + "add.w @(0x1234:16,r3.w),@er1-" +gdb_test "x" "add.w\t@\\(0x1234(:16|),r3.w\\),@\\+er1" \ + "add.w @(0x1234:16,r3.w),@+er1" +gdb_test "x" "add.w\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abc(:16|),er1\\)" \ + "add.w @(0x1234:16,r3.w),@(0x9abc:16,er1)" +gdb_test "x" "add.w\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "add.w @(0x1234:16,r3.w),@(0x9abcdef0:32,er1)" +gdb_test "x" "add.w\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "add.w @(0x1234:16,r3.w),@(0x9abc:16,r2l.b)" +gdb_test "x" "add.w\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abc(:16|),r2.w\\)" \ + "add.w @(0x1234:16,r3.w),@(0x9abc:16,r2.w)" +gdb_test "x" "add.w\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abc(:16|),er2.l\\)" \ + "add.w @(0x1234:16,r3.w),@(0x9abc:16,er2.l)" +gdb_test "x" "add.w\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "add.w @(0x1234:16,r3.w),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "add.w\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "add.w @(0x1234:16,r3.w),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "add.w\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "add.w @(0x1234:16,r3.w),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "add.w\t@\\(0x1234(:16|),r3.w\\),@0x9abc(:16|)" \ + "add.w @(0x1234:16,r3.w),@0x9abc:16" +gdb_test "x" "add.w\t@\\(0x1234(:16|),r3.w\\),@0x9abcdef0(:32|)" \ + "add.w @(0x1234:16,r3.w),@0x9abcdef0:32" +gdb_test "x" "add.w\t@\\(0x1234(:16|),er3.l\\),@er1" \ + "add.w @(0x1234:16,er3.l),@er1" +gdb_test "x" "add.w\t@\\(0x1234(:16|),er3.l\\),@\\(0x6(:2|),er1\\)" \ + "add.w @(0x1234:16,er3.l),@(0x6:2,er1)" +gdb_test "x" "add.w\t@\\(0x1234(:16|),er3.l\\),@-er1" \ + "add.w @(0x1234:16,er3.l),@-er1" +gdb_test "x" "add.w\t@\\(0x1234(:16|),er3.l\\),@er1\\+" \ + "add.w @(0x1234:16,er3.l),@er1+" +gdb_test "x" "add.w\t@\\(0x1234(:16|),er3.l\\),@er1-" \ + "add.w @(0x1234:16,er3.l),@er1-" +gdb_test "x" "add.w\t@\\(0x1234(:16|),er3.l\\),@\\+er1" \ + "add.w @(0x1234:16,er3.l),@+er1" +gdb_test "x" "add.w\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abc(:16|),er1\\)" \ + "add.w @(0x1234:16,er3.l),@(0x9abc:16,er1)" +gdb_test "x" "add.w\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "add.w @(0x1234:16,er3.l),@(0x9abcdef0:32,er1)" +gdb_test "x" "add.w\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "add.w @(0x1234:16,er3.l),@(0x9abc:16,r2l.b)" +gdb_test "x" "add.w\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abc(:16|),r2.w\\)" \ + "add.w @(0x1234:16,er3.l),@(0x9abc:16,r2.w)" +gdb_test "x" "add.w\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abc(:16|),er2.l\\)" \ + "add.w @(0x1234:16,er3.l),@(0x9abc:16,er2.l)" +gdb_test "x" "add.w\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "add.w @(0x1234:16,er3.l),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "add.w\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "add.w @(0x1234:16,er3.l),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "add.w\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "add.w @(0x1234:16,er3.l),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "add.w\t@\\(0x1234(:16|),er3.l\\),@0x9abc(:16|)" \ + "add.w @(0x1234:16,er3.l),@0x9abc:16" +gdb_test "x" "add.w\t@\\(0x1234(:16|),er3.l\\),@0x9abcdef0(:32|)" \ + "add.w @(0x1234:16,er3.l),@0x9abcdef0:32" +gdb_test "x" "add.w\t@\\(0x12345678(:32|),r3l.b\\),@er1" \ + "add.w @(0x12345678:32,r3l.b),@er1" +gdb_test "x" "add.w\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x6(:2|),er1\\)" \ + "add.w @(0x12345678:32,r3l.b),@(0x6:2,er1)" +gdb_test "x" "add.w\t@\\(0x12345678(:32|),r3l.b\\),@-er1" \ + "add.w @(0x12345678:32,r3l.b),@-er1" +gdb_test "x" "add.w\t@\\(0x12345678(:32|),r3l.b\\),@er1\\+" \ + "add.w @(0x12345678:32,r3l.b),@er1+" +gdb_test "x" "add.w\t@\\(0x12345678(:32|),r3l.b\\),@er1-" \ + "add.w @(0x12345678:32,r3l.b),@er1-" +gdb_test "x" "add.w\t@\\(0x12345678(:32|),r3l.b\\),@\\+er1" \ + "add.w @(0x12345678:32,r3l.b),@+er1" +gdb_test "x" "add.w\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abc(:16|),er1\\)" \ + "add.w @(0x12345678:32,r3l.b),@(0x9abc:16,er1)" +gdb_test "x" "add.w\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "add.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1)" +gdb_test "x" "add.w\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "add.w @(0x12345678:32,r3l.b),@(0x9abc:16,r2l.b)" +gdb_test "x" "add.w\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abc(:16|),r2.w\\)" \ + "add.w @(0x12345678:32,r3l.b),@(0x9abc:16,r2.w)" +gdb_test "x" "add.w\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abc(:16|),er2.l\\)" \ + "add.w @(0x12345678:32,r3l.b),@(0x9abc:16,er2.l)" +gdb_test "x" "add.w\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "add.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "add.w\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "add.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "add.w\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "add.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "add.w\t@\\(0x12345678(:32|),r3l.b\\),@0x9abc(:16|)" \ + "add.w @(0x12345678:32,r3l.b),@0x9abc:16" +gdb_test "x" "add.w\t@\\(0x12345678(:32|),r3l.b\\),@0x9abcdef0(:32|)" \ + "add.w @(0x12345678:32,r3l.b),@0x9abcdef0:32" +gdb_test "x" "add.w\t@\\(0x12345678(:32|),r3.w\\),@er1" \ + "add.w @(0x12345678:32,r3.w),@er1" +gdb_test "x" "add.w\t@\\(0x12345678(:32|),r3.w\\),@\\(0x6(:2|),er1\\)" \ + "add.w @(0x12345678:32,r3.w),@(0x6:2,er1)" +gdb_test "x" "add.w\t@\\(0x12345678(:32|),r3.w\\),@-er1" \ + "add.w @(0x12345678:32,r3.w),@-er1" +gdb_test "x" "add.w\t@\\(0x12345678(:32|),r3.w\\),@er1\\+" \ + "add.w @(0x12345678:32,r3.w),@er1+" +gdb_test "x" "add.w\t@\\(0x12345678(:32|),r3.w\\),@er1-" \ + "add.w @(0x12345678:32,r3.w),@er1-" +gdb_test "x" "add.w\t@\\(0x12345678(:32|),r3.w\\),@\\+er1" \ + "add.w @(0x12345678:32,r3.w),@+er1" +gdb_test "x" "add.w\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abc(:16|),er1\\)" \ + "add.w @(0x12345678:32,r3.w),@(0x9abc:16,er1)" +gdb_test "x" "add.w\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "add.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1)" +gdb_test "x" "add.w\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "add.w @(0x12345678:32,r3.w),@(0x9abc:16,r2l.b)" +gdb_test "x" "add.w\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abc(:16|),r2.w\\)" \ + "add.w @(0x12345678:32,r3.w),@(0x9abc:16,r2.w)" +gdb_test "x" "add.w\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abc(:16|),er2.l\\)" \ + "add.w @(0x12345678:32,r3.w),@(0x9abc:16,er2.l)" +gdb_test "x" "add.w\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "add.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "add.w\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "add.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "add.w\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "add.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "add.w\t@\\(0x12345678(:32|),r3.w\\),@0x9abc(:16|)" \ + "add.w @(0x12345678:32,r3.w),@0x9abc:16" +gdb_test "x" "add.w\t@\\(0x12345678(:32|),r3.w\\),@0x9abcdef0(:32|)" \ + "add.w @(0x12345678:32,r3.w),@0x9abcdef0:32" +gdb_test "x" "add.w\t@\\(0x12345678(:32|),er3.l\\),@er1" \ + "add.w @(0x12345678:32,er3.l),@er1" +gdb_test "x" "add.w\t@\\(0x12345678(:32|),er3.l\\),@\\(0x6(:2|),er1\\)" \ + "add.w @(0x12345678:32,er3.l),@(0x6:2,er1)" +gdb_test "x" "add.w\t@\\(0x12345678(:32|),er3.l\\),@-er1" \ + "add.w @(0x12345678:32,er3.l),@-er1" +gdb_test "x" "add.w\t@\\(0x12345678(:32|),er3.l\\),@er1\\+" \ + "add.w @(0x12345678:32,er3.l),@er1+" +gdb_test "x" "add.w\t@\\(0x12345678(:32|),er3.l\\),@er1-" \ + "add.w @(0x12345678:32,er3.l),@er1-" +gdb_test "x" "add.w\t@\\(0x12345678(:32|),er3.l\\),@\\+er1" \ + "add.w @(0x12345678:32,er3.l),@+er1" +gdb_test "x" "add.w\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abc(:16|),er1\\)" \ + "add.w @(0x12345678:32,er3.l),@(0x9abc:16,er1)" +gdb_test "x" "add.w\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "add.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1)" +gdb_test "x" "add.w\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "add.w @(0x12345678:32,er3.l),@(0x9abc:16,r2l.b)" +gdb_test "x" "add.w\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abc(:16|),r2.w\\)" \ + "add.w @(0x12345678:32,er3.l),@(0x9abc:16,r2.w)" +gdb_test "x" "add.w\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abc(:16|),er2.l\\)" \ + "add.w @(0x12345678:32,er3.l),@(0x9abc:16,er2.l)" +gdb_test "x" "add.w\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "add.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "add.w\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "add.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "add.w\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "add.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "add.w\t@\\(0x12345678(:32|),er3.l\\),@0x9abc(:16|)" \ + "add.w @(0x12345678:32,er3.l),@0x9abc:16" +gdb_test "x" "add.w\t@\\(0x12345678(:32|),er3.l\\),@0x9abcdef0(:32|)" \ + "add.w @(0x12345678:32,er3.l),@0x9abcdef0:32" +gdb_test "x" "add.w\t@0x1234(:16|),@er1" \ + "add.w @0x1234:16,@er1" +gdb_test "x" "add.w\t@0x1234(:16|),@\\(0x6(:2|),er1\\)" \ + "add.w @0x1234:16,@(0x6:2,er1)" +gdb_test "x" "add.w\t@0x1234(:16|),@-er1" \ + "add.w @0x1234:16,@-er1" +gdb_test "x" "add.w\t@0x1234(:16|),@er1\\+" \ + "add.w @0x1234:16,@er1+" +gdb_test "x" "add.w\t@0x1234(:16|),@er1-" \ + "add.w @0x1234:16,@er1-" +gdb_test "x" "add.w\t@0x1234(:16|),@\\+er1" \ + "add.w @0x1234:16,@+er1" +gdb_test "x" "add.w\t@0x1234(:16|),@\\(0x9abc(:16|),er1\\)" \ + "add.w @0x1234:16,@(0x9abc:16,er1)" +gdb_test "x" "add.w\t@0x1234(:16|),@\\(0x9abcdef0(:32|),er1\\)" \ + "add.w @0x1234:16,@(0x9abcdef0:32,er1)" +gdb_test "x" "add.w\t@0x1234(:16|),@\\(0x9abc(:16|),r2l.b\\)" \ + "add.w @0x1234:16,@(0x9abc:16,r2l.b)" +gdb_test "x" "add.w\t@0x1234(:16|),@\\(0x9abc(:16|),r2.w\\)" \ + "add.w @0x1234:16,@(0x9abc:16,r2.w)" +gdb_test "x" "add.w\t@0x1234(:16|),@\\(0x9abc(:16|),er2.l\\)" \ + "add.w @0x1234:16,@(0x9abc:16,er2.l)" +gdb_test "x" "add.w\t@0x1234(:16|),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "add.w @0x1234:16,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "add.w\t@0x1234(:16|),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "add.w @0x1234:16,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "add.w\t@0x1234(:16|),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "add.w @0x1234:16,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "add.w\t@0x1234(:16|),@0x9abc(:16|)" \ + "add.w @0x1234:16,@0x9abc:16" +gdb_test "x" "add.w\t@0x1234(:16|),@0x9abcdef0(:32|)" \ + "add.w @0x1234:16,@0x9abcdef0:32" +gdb_test "x" "add.w\t@0x12345678(:32|),@er1" \ + "add.w @0x12345678:32,@er1" +gdb_test "x" "add.w\t@0x12345678(:32|),@\\(0x6(:2|),er1\\)" \ + "add.w @0x12345678:32,@(0x6:2,er1)" +gdb_test "x" "add.w\t@0x12345678(:32|),@-er1" \ + "add.w @0x12345678:32,@-er1" +gdb_test "x" "add.w\t@0x12345678(:32|),@er1\\+" \ + "add.w @0x12345678:32,@er1+" +gdb_test "x" "add.w\t@0x12345678(:32|),@er1-" \ + "add.w @0x12345678:32,@er1-" +gdb_test "x" "add.w\t@0x12345678(:32|),@\\+er1" \ + "add.w @0x12345678:32,@+er1" +gdb_test "x" "add.w\t@0x12345678(:32|),@\\(0x9abc(:16|),er1\\)" \ + "add.w @0x12345678:32,@(0x9abc:16,er1)" +gdb_test "x" "add.w\t@0x12345678(:32|),@\\(0x9abcdef0(:32|),er1\\)" \ + "add.w @0x12345678:32,@(0x9abcdef0:32,er1)" +gdb_test "x" "add.w\t@0x12345678(:32|),@\\(0x9abc(:16|),r2l.b\\)" \ + "add.w @0x12345678:32,@(0x9abc:16,r2l.b)" +gdb_test "x" "add.w\t@0x12345678(:32|),@\\(0x9abc(:16|),r2.w\\)" \ + "add.w @0x12345678:32,@(0x9abc:16,r2.w)" +gdb_test "x" "add.w\t@0x12345678(:32|),@\\(0x9abc(:16|),er2.l\\)" \ + "add.w @0x12345678:32,@(0x9abc:16,er2.l)" +gdb_test "x" "add.w\t@0x12345678(:32|),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "add.w @0x12345678:32,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "add.w\t@0x12345678(:32|),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "add.w @0x12345678:32,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "add.w\t@0x12345678(:32|),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "add.w @0x12345678:32,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "add.w\t@0x12345678(:32|),@0x9abc(:16|)" \ + "add.w @0x12345678:32,@0x9abc:16" +gdb_test "x" "add.w\t@0x12345678(:32|),@0x9abcdef0(:32|)" \ + "add.w @0x12345678:32,@0x9abcdef0:32" +gdb_test "x" "add.l\t#0x12345678(:32|),er1" \ + "add.l #0x12345678:32,er1" +gdb_test "x" "add.l\t#0x1234(:16|),er1" \ + "add.l #0x1234:16,er1" +gdb_test "x" "add.l\t#0x7(:3|),er2" \ + "add.l #0x7:3,er2" +gdb_test "x" "add.l\t#0x12345678(:32|),@er1" \ + "add.l #0x12345678:32,@er1" +gdb_test "x" "add.l\t#0x12345678(:32|),@\\(0xc(:2|),er1\\)" \ + "add.l #0x12345678:32,@(0xc:2,er1)" +gdb_test "x" "add.l\t#0x12345678(:32|),@er1\\+" \ + "add.l #0x12345678:32,@er1+" +gdb_test "x" "add.l\t#0x12345678(:32|),@-er1" \ + "add.l #0x12345678:32,@-er1" +gdb_test "x" "add.l\t#0x12345678(:32|),@\\+er1" \ + "add.l #0x12345678:32,@+er1" +gdb_test "x" "add.l\t#0x12345678(:32|),@er1-" \ + "add.l #0x12345678:32,@er1-" +gdb_test "x" "add.l\t#0x12345678(:32|),@\\(0x9abc(:16|),er1\\)" \ + "add.l #0x12345678:32,@(0x9abc:16,er1)" +gdb_test "x" "add.l\t#0x12345678(:32|),@\\(0x9abcdef0(:32|),er1\\)" \ + "add.l #0x12345678:32,@(0x9abcdef0:32,er1)" +gdb_test "x" "add.l\t#0x12345678(:32|),@\\(0x9abc(:16|),r2l.b\\)" \ + "add.l #0x12345678:32,@(0x9abc:16,r2l.b)" +gdb_test "x" "add.l\t#0x12345678(:32|),@\\(0x9abc(:16|),r2.w\\)" \ + "add.l #0x12345678:32,@(0x9abc:16,r2.w)" +gdb_test "x" "add.l\t#0x12345678(:32|),@\\(0x9abc(:16|),er2.l\\)" \ + "add.l #0x12345678:32,@(0x9abc:16,er2.l)" +gdb_test "x" "add.l\t#0x12345678(:32|),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "add.l #0x12345678:32,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "add.l\t#0x12345678(:32|),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "add.l #0x12345678:32,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "add.l\t#0x12345678(:32|),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "add.l #0x12345678:32,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "add.l\t#0x12345678(:32|),@0x9abc(:16|)" \ + "add.l #0x12345678:32,@0x9abc:16" +gdb_test "x" "add.l\t#0x12345678(:32|),@0x9abcdef0(:32|)" \ + "add.l #0x12345678:32,@0x9abcdef0:32" +gdb_test "x" "add.l\t#0x1234(:16|),@er1" \ + "add.l #0x1234:16,@er1" +gdb_test "x" "add.l\t#0x1234(:16|),@\\(0xc(:2|),er1\\)" \ + "add.l #0x1234:16,@(0xc:2,er1)" +gdb_test "x" "add.l\t#0x1234(:16|),@er1\\+" \ + "add.l #0x1234:16,@er1+" +gdb_test "x" "add.l\t#0x1234(:16|),@-er1" \ + "add.l #0x1234:16,@-er1" +gdb_test "x" "add.l\t#0x1234(:16|),@\\+er1" \ + "add.l #0x1234:16,@+er1" +gdb_test "x" "add.l\t#0x1234(:16|),@er1-" \ + "add.l #0x1234:16,@er1-" +gdb_test "x" "add.l\t#0x1234(:16|),@\\(0x9abc(:16|),er1\\)" \ + "add.l #0x1234:16,@(0x9abc:16,er1)" +gdb_test "x" "add.l\t#0x1234(:16|),@\\(0x9abcdef0(:32|),er1\\)" \ + "add.l #0x1234:16,@(0x9abcdef0:32,er1)" +gdb_test "x" "add.l\t#0x1234(:16|),@\\(0x9abc(:16|),r2l.b\\)" \ + "add.l #0x1234:16,@(0x9abc:16,r2l.b)" +gdb_test "x" "add.l\t#0x1234(:16|),@\\(0x9abc(:16|),r2.w\\)" \ + "add.l #0x1234:16,@(0x9abc:16,r2.w)" +gdb_test "x" "add.l\t#0x1234(:16|),@\\(0x9abc(:16|),er2.l\\)" \ + "add.l #0x1234:16,@(0x9abc:16,er2.l)" +gdb_test "x" "add.l\t#0x1234(:16|),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "add.l #0x1234:16,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "add.l\t#0x1234(:16|),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "add.l #0x1234:16,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "add.l\t#0x1234(:16|),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "add.l #0x1234:16,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "add.l\t#0x1234(:16|),@0x9abc(:16|)" \ + "add.l #0x1234:16,@0x9abc:16" +gdb_test "x" "add.l\t#0x1234(:16|),@0x9abcdef0(:32|)" \ + "add.l #0x1234:16,@0x9abcdef0:32" +gdb_test "x" "add.l\ter3,er1" \ + "add.l er3,er1" +gdb_test "x" "add.l\ter3,@er1" \ + "add.l er3,@er1" +gdb_test "x" "add.l\ter3,@\\(0xc(:2|),er1\\)" \ + "add.l er3,@(0xc:2,er1)" +gdb_test "x" "add.l\ter3,@er1\\+" \ + "add.l er3,@er1+" +gdb_test "x" "add.l\ter3,@-er1" \ + "add.l er3,@-er1" +gdb_test "x" "add.l\ter3,@\\+er1" \ + "add.l er3,@+er1" +gdb_test "x" "add.l\ter3,@er1-" \ + "add.l er3,@er1-" +gdb_test "x" "add.l\ter3,@\\(0x1234(:16|),er1\\)" \ + "add.l er3,@(0x1234:16,er1)" +gdb_test "x" "add.l\ter3,@\\(0x12345678(:32|),er1\\)" \ + "add.l er3,@(0x12345678:32,er1)" +gdb_test "x" "add.l\ter3,@\\(0x1234(:16|),r2l.b\\)" \ + "add.l er3,@(0x1234:16,r2l.b)" +gdb_test "x" "add.l\ter3,@\\(0x1234(:16|),r2.w\\)" \ + "add.l er3,@(0x1234:16,r2.w)" +gdb_test "x" "add.l\ter3,@\\(0x1234(:16|),er2.l\\)" \ + "add.l er3,@(0x1234:16,er2.l)" +gdb_test "x" "add.l\ter3,@\\(0x12345678(:32|),r2l.b\\)" \ + "add.l er3,@(0x12345678:32,r2l.b)" +gdb_test "x" "add.l\ter3,@\\(0x12345678(:32|),r2.w\\)" \ + "add.l er3,@(0x12345678:32,r2.w)" +gdb_test "x" "add.l\ter3,@\\(0x12345678(:32|),er2.l\\)" \ + "add.l er3,@(0x12345678:32,er2.l)" +gdb_test "x" "add.l\ter3,@0x1234(:16|)" \ + "add.l er3,@0x1234:16" +gdb_test "x" "add.l\ter3,@0x12345678(:32|)" \ + "add.l er3,@0x12345678:32" +gdb_test "x" "add.l\t@er3,er1" \ + "add.l @er3,er1" +gdb_test "x" "add.l\t@\\(0xc(:2|),er3\\),er1" \ + "add.l @(0xc:2,er3),er1" +gdb_test "x" "add.l\t@er3\\+,er1" \ + "add.l @er3+,er1" +gdb_test "x" "add.l\t@-er3,er1" \ + "add.l @-er3,er1" +gdb_test "x" "add.l\t@\\+er3,er1" \ + "add.l @+er3,er1" +gdb_test "x" "add.l\t@er3-,er1" \ + "add.l @er3-,er1" +gdb_test "x" "add.l\t@\\(0x1234(:16|),er1\\),er1" \ + "add.l @(0x1234:16,er1),er1" +gdb_test "x" "add.l\t@\\(0x12345678(:32|),er1\\),er1" \ + "add.l @(0x12345678:32,er1),er1" +gdb_test "x" "add.l\t@\\(0x1234(:16|),r2l.b\\),er1" \ + "add.l @(0x1234:16,r2l.b),er1" +gdb_test "x" "add.l\t@\\(0x1234(:16|),r2.w\\),er1" \ + "add.l @(0x1234:16,r2.w),er1" +gdb_test "x" "add.l\t@\\(0x1234(:16|),er2.l\\),er1" \ + "add.l @(0x1234:16,er2.l),er1" +gdb_test "x" "add.l\t@\\(0x12345678(:32|),r2l.b\\),er1" \ + "add.l @(0x12345678:32,r2l.b),er1" +gdb_test "x" "add.l\t@\\(0x12345678(:32|),r2.w\\),er1" \ + "add.l @(0x12345678:32,r2.w),er1" +gdb_test "x" "add.l\t@\\(0x12345678(:32|),er2.l\\),er1" \ + "add.l @(0x12345678:32,er2.l),er1" +gdb_test "x" "add.l\t@0x1234(:16|),er1" \ + "add.l @0x1234:16,er1" +gdb_test "x" "add.l\t@0x12345678(:32|),er1" \ + "add.l @0x12345678:32,er1" +gdb_test "x" "add.l\t@er3,@er1" \ + "add.l @er3,@er1" +gdb_test "x" "add.l\t@er3,@\\(0xc(:2|),er1\\)" \ + "add.l @er3,@(0xc:2,er1)" +gdb_test "x" "add.l\t@er3,@-er1" \ + "add.l @er3,@-er1" +gdb_test "x" "add.l\t@er3,@er1\\+" \ + "add.l @er3,@er1+" +gdb_test "x" "add.l\t@er3,@er1-" \ + "add.l @er3,@er1-" +gdb_test "x" "add.l\t@er3,@\\+er1" \ + "add.l @er3,@+er1" +gdb_test "x" "add.l\t@er3,@\\(0x9abc(:16|),er1\\)" \ + "add.l @er3,@(0x9abc:16,er1)" +gdb_test "x" "add.l\t@er3,@\\(0x9abcdef0(:32|),er1\\)" \ + "add.l @er3,@(0x9abcdef0:32,er1)" +gdb_test "x" "add.l\t@er3,@\\(0x9abc(:16|),r2l.b\\)" \ + "add.l @er3,@(0x9abc:16,r2l.b)" +gdb_test "x" "add.l\t@er3,@\\(0x9abc(:16|),r2.w\\)" \ + "add.l @er3,@(0x9abc:16,r2.w)" +gdb_test "x" "add.l\t@er3,@\\(0x9abc(:16|),er2.l\\)" \ + "add.l @er3,@(0x9abc:16,er2.l)" +gdb_test "x" "add.l\t@er3,@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "add.l @er3,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "add.l\t@er3,@\\(0x9abcdef0(:32|),r2.w\\)" \ + "add.l @er3,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "add.l\t@er3,@\\(0x9abcdef0(:32|),er2.l\\)" \ + "add.l @er3,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "add.l\t@er3,@0x9abc(:16|)" \ + "add.l @er3,@0x9abc:16" +gdb_test "x" "add.l\t@er3,@0x9abcdef0(:32|)" \ + "add.l @er3,@0x9abcdef0:32" +gdb_test "x" "add.l\t@\\(0xc(:2|),er3\\),@er1" \ + "add.l @(0xc:2,er3),@er1" +gdb_test "x" "add.l\t@\\(0xc(:2|),er3\\),@\\(0xc(:2|),er1\\)" \ + "add.l @(0xc:2,er3),@(0xc:2,er1)" +gdb_test "x" "add.l\t@\\(0xc(:2|),er3\\),@-er1" \ + "add.l @(0xc:2,er3),@-er1" +gdb_test "x" "add.l\t@\\(0xc(:2|),er3\\),@er1\\+" \ + "add.l @(0xc:2,er3),@er1+" +gdb_test "x" "add.l\t@\\(0xc(:2|),er3\\),@er1-" \ + "add.l @(0xc:2,er3),@er1-" +gdb_test "x" "add.l\t@\\(0xc(:2|),er3\\),@\\+er1" \ + "add.l @(0xc:2,er3),@+er1" +gdb_test "x" "add.l\t@\\(0xc(:2|),er3\\),@\\(0x9abc(:16|),er1\\)" \ + "add.l @(0xc:2,er3),@(0x9abc:16,er1)" +gdb_test "x" "add.l\t@\\(0xc(:2|),er3\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "add.l @(0xc:2,er3),@(0x9abcdef0:32,er1)" +gdb_test "x" "add.l\t@\\(0xc(:2|),er3\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "add.l @(0xc:2,er3),@(0x9abc:16,r2l.b)" +gdb_test "x" "add.l\t@\\(0xc(:2|),er3\\),@\\(0x9abc(:16|),r2.w\\)" \ + "add.l @(0xc:2,er3),@(0x9abc:16,r2.w)" +gdb_test "x" "add.l\t@\\(0xc(:2|),er3\\),@\\(0x9abc(:16|),er2.l\\)" \ + "add.l @(0xc:2,er3),@(0x9abc:16,er2.l)" +gdb_test "x" "add.l\t@\\(0xc(:2|),er3\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "add.l @(0xc:2,er3),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "add.l\t@\\(0xc(:2|),er3\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "add.l @(0xc:2,er3),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "add.l\t@\\(0xc(:2|),er3\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "add.l @(0xc:2,er3),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "add.l\t@\\(0xc(:2|),er3\\),@0x9abc(:16|)" \ + "add.l @(0xc:2,er3),@0x9abc:16" +gdb_test "x" "add.l\t@\\(0xc(:2|),er3\\),@0x9abcdef0(:32|)" \ + "add.l @(0xc:2,er3),@0x9abcdef0:32" +gdb_test "x" "add.l\t@-er3,@er1" \ + "add.l @-er3,@er1" +gdb_test "x" "add.l\t@-er3,@\\(0xc(:2|),er1\\)" \ + "add.l @-er3,@(0xc:2,er1)" +gdb_test "x" "add.l\t@-er3,@-er1" \ + "add.l @-er3,@-er1" +gdb_test "x" "add.l\t@-er3,@er1\\+" \ + "add.l @-er3,@er1+" +gdb_test "x" "add.l\t@-er3,@er1-" \ + "add.l @-er3,@er1-" +gdb_test "x" "add.l\t@-er3,@\\+er1" \ + "add.l @-er3,@+er1" +gdb_test "x" "add.l\t@-er3,@\\(0x9abc(:16|),er1\\)" \ + "add.l @-er3,@(0x9abc:16,er1)" +gdb_test "x" "add.l\t@-er3,@\\(0x9abcdef0(:32|),er1\\)" \ + "add.l @-er3,@(0x9abcdef0:32,er1)" +gdb_test "x" "add.l\t@-er3,@\\(0x9abc(:16|),r2l.b\\)" \ + "add.l @-er3,@(0x9abc:16,r2l.b)" +gdb_test "x" "add.l\t@-er3,@\\(0x9abc(:16|),r2.w\\)" \ + "add.l @-er3,@(0x9abc:16,r2.w)" +gdb_test "x" "add.l\t@-er3,@\\(0x9abc(:16|),er2.l\\)" \ + "add.l @-er3,@(0x9abc:16,er2.l)" +gdb_test "x" "add.l\t@-er3,@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "add.l @-er3,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "add.l\t@-er3,@\\(0x9abcdef0(:32|),r2.w\\)" \ + "add.l @-er3,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "add.l\t@-er3,@\\(0x9abcdef0(:32|),er2.l\\)" \ + "add.l @-er3,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "add.l\t@-er3,@0x9abc(:16|)" \ + "add.l @-er3,@0x9abc:16" +gdb_test "x" "add.l\t@-er3,@0x9abcdef0(:32|)" \ + "add.l @-er3,@0x9abcdef0:32" +gdb_test "x" "add.l\t@er3\\+,@er1" \ + "add.l @er3+,@er1" +gdb_test "x" "add.l\t@er3\\+,@\\(0xc(:2|),er1\\)" \ + "add.l @er3+,@(0xc:2,er1)" +gdb_test "x" "add.l\t@er3\\+,@-er1" \ + "add.l @er3+,@-er1" +gdb_test "x" "add.l\t@er3\\+,@er1\\+" \ + "add.l @er3+,@er1+" +gdb_test "x" "add.l\t@er3\\+,@er1-" \ + "add.l @er3+,@er1-" +gdb_test "x" "add.l\t@er3\\+,@\\+er1" \ + "add.l @er3+,@+er1" +gdb_test "x" "add.l\t@er3\\+,@\\(0x9abc(:16|),er1\\)" \ + "add.l @er3+,@(0x9abc:16,er1)" +gdb_test "x" "add.l\t@er3\\+,@\\(0x9abcdef0(:32|),er1\\)" \ + "add.l @er3+,@(0x9abcdef0:32,er1)" +gdb_test "x" "add.l\t@er3\\+,@\\(0x9abc(:16|),r2l.b\\)" \ + "add.l @er3+,@(0x9abc:16,r2l.b)" +gdb_test "x" "add.l\t@er3\\+,@\\(0x9abc(:16|),r2.w\\)" \ + "add.l @er3+,@(0x9abc:16,r2.w)" +gdb_test "x" "add.l\t@er3\\+,@\\(0x9abc(:16|),er2.l\\)" \ + "add.l @er3+,@(0x9abc:16,er2.l)" +gdb_test "x" "add.l\t@er3\\+,@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "add.l @er3+,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "add.l\t@er3\\+,@\\(0x9abcdef0(:32|),r2.w\\)" \ + "add.l @er3+,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "add.l\t@er3\\+,@\\(0x9abcdef0(:32|),er2.l\\)" \ + "add.l @er3+,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "add.l\t@er3\\+,@0x9abc(:16|)" \ + "add.l @er3+,@0x9abc:16" +gdb_test "x" "add.l\t@er3\\+,@0x9abcdef0(:32|)" \ + "add.l @er3+,@0x9abcdef0:32" +gdb_test "x" "add.l\t@er3-,@er1" \ + "add.l @er3-,@er1" +gdb_test "x" "add.l\t@er3-,@\\(0xc(:2|),er1\\)" \ + "add.l @er3-,@(0xc:2,er1)" +gdb_test "x" "add.l\t@er3-,@-er1" \ + "add.l @er3-,@-er1" +gdb_test "x" "add.l\t@er3-,@er1\\+" \ + "add.l @er3-,@er1+" +gdb_test "x" "add.l\t@er3-,@er1-" \ + "add.l @er3-,@er1-" +gdb_test "x" "add.l\t@er3-,@\\+er1" \ + "add.l @er3-,@+er1" +gdb_test "x" "add.l\t@er3-,@\\(0x9abc(:16|),er1\\)" \ + "add.l @er3-,@(0x9abc:16,er1)" +gdb_test "x" "add.l\t@er3-,@\\(0x9abcdef0(:32|),er1\\)" \ + "add.l @er3-,@(0x9abcdef0:32,er1)" +gdb_test "x" "add.l\t@er3-,@\\(0x9abc(:16|),r2l.b\\)" \ + "add.l @er3-,@(0x9abc:16,r2l.b)" +gdb_test "x" "add.l\t@er3-,@\\(0x9abc(:16|),r2.w\\)" \ + "add.l @er3-,@(0x9abc:16,r2.w)" +gdb_test "x" "add.l\t@er3-,@\\(0x9abc(:16|),er2.l\\)" \ + "add.l @er3-,@(0x9abc:16,er2.l)" +gdb_test "x" "add.l\t@er3-,@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "add.l @er3-,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "add.l\t@er3-,@\\(0x9abcdef0(:32|),r2.w\\)" \ + "add.l @er3-,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "add.l\t@er3-,@\\(0x9abcdef0(:32|),er2.l\\)" \ + "add.l @er3-,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "add.l\t@er3-,@0x9abc(:16|)" \ + "add.l @er3-,@0x9abc:16" +gdb_test "x" "add.l\t@er3-,@0x9abcdef0(:32|)" \ + "add.l @er3-,@0x9abcdef0:32" +gdb_test "x" "add.l\t@\\+er3,@er1" \ + "add.l @+er3,@er1" +gdb_test "x" "add.l\t@\\+er3,@\\(0xc(:2|),er1\\)" \ + "add.l @+er3,@(0xc:2,er1)" +gdb_test "x" "add.l\t@\\+er3,@-er1" \ + "add.l @+er3,@-er1" +gdb_test "x" "add.l\t@\\+er3,@er1\\+" \ + "add.l @+er3,@er1+" +gdb_test "x" "add.l\t@\\+er3,@er1-" \ + "add.l @+er3,@er1-" +gdb_test "x" "add.l\t@\\+er3,@\\+er1" \ + "add.l @+er3,@+er1" +gdb_test "x" "add.l\t@\\+er3,@\\(0x9abc(:16|),er1\\)" \ + "add.l @+er3,@(0x9abc:16,er1)" +gdb_test "x" "add.l\t@\\+er3,@\\(0x9abcdef0(:32|),er1\\)" \ + "add.l @+er3,@(0x9abcdef0:32,er1)" +gdb_test "x" "add.l\t@\\+er3,@\\(0x9abc(:16|),r2l.b\\)" \ + "add.l @+er3,@(0x9abc:16,r2l.b)" +gdb_test "x" "add.l\t@\\+er3,@\\(0x9abc(:16|),r2.w\\)" \ + "add.l @+er3,@(0x9abc:16,r2.w)" +gdb_test "x" "add.l\t@\\+er3,@\\(0x9abc(:16|),er2.l\\)" \ + "add.l @+er3,@(0x9abc:16,er2.l)" +gdb_test "x" "add.l\t@\\+er3,@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "add.l @+er3,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "add.l\t@\\+er3,@\\(0x9abcdef0(:32|),r2.w\\)" \ + "add.l @+er3,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "add.l\t@\\+er3,@\\(0x9abcdef0(:32|),er2.l\\)" \ + "add.l @+er3,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "add.l\t@\\+er3,@0x9abc(:16|)" \ + "add.l @+er3,@0x9abc:16" +gdb_test "x" "add.l\t@\\+er3,@0x9abcdef0(:32|)" \ + "add.l @+er3,@0x9abcdef0:32" +gdb_test "x" "add.l\t@\\(0x1234(:16|),er3\\),@er1" \ + "add.l @(0x1234:16,er3),@er1" +gdb_test "x" "add.l\t@\\(0x1234(:16|),er3\\),@\\(0xc(:2|),er1\\)" \ + "add.l @(0x1234:16,er3),@(0xc:2,er1)" +gdb_test "x" "add.l\t@\\(0x1234(:16|),er3\\),@-er1" \ + "add.l @(0x1234:16,er3),@-er1" +gdb_test "x" "add.l\t@\\(0x1234(:16|),er3\\),@er1\\+" \ + "add.l @(0x1234:16,er3),@er1+" +gdb_test "x" "add.l\t@\\(0x1234(:16|),er3\\),@er1-" \ + "add.l @(0x1234:16,er3),@er1-" +gdb_test "x" "add.l\t@\\(0x1234(:16|),er3\\),@\\+er1" \ + "add.l @(0x1234:16,er3),@+er1" +gdb_test "x" "add.l\t@\\(0x1234(:16|),er3\\),@\\(0x9abc(:16|),er1\\)" \ + "add.l @(0x1234:16,er3),@(0x9abc:16,er1)" +gdb_test "x" "add.l\t@\\(0x1234(:16|),er3\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "add.l @(0x1234:16,er3),@(0x9abcdef0:32,er1)" +gdb_test "x" "add.l\t@\\(0x1234(:16|),er3\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "add.l @(0x1234:16,er3),@(0x9abc:16,r2l.b)" +gdb_test "x" "add.l\t@\\(0x1234(:16|),er3\\),@\\(0x9abc(:16|),r2.w\\)" \ + "add.l @(0x1234:16,er3),@(0x9abc:16,r2.w)" +gdb_test "x" "add.l\t@\\(0x1234(:16|),er3\\),@\\(0x9abc(:16|),er2.l\\)" \ + "add.l @(0x1234:16,er3),@(0x9abc:16,er2.l)" +gdb_test "x" "add.l\t@\\(0x1234(:16|),er3\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "add.l @(0x1234:16,er3),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "add.l\t@\\(0x1234(:16|),er3\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "add.l @(0x1234:16,er3),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "add.l\t@\\(0x1234(:16|),er3\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "add.l @(0x1234:16,er3),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "add.l\t@\\(0x1234(:16|),er3\\),@0x9abc(:16|)" \ + "add.l @(0x1234:16,er3),@0x9abc:16" +gdb_test "x" "add.l\t@\\(0x1234(:16|),er3\\),@0x9abcdef0(:32|)" \ + "add.l @(0x1234:16,er3),@0x9abcdef0:32" +gdb_test "x" "add.l\t@\\(0x12345678(:32|),er3\\),@er1" \ + "add.l @(0x12345678:32,er3),@er1" +gdb_test "x" "add.l\t@\\(0x12345678(:32|),er3\\),@\\(0xc(:2|),er1\\)" \ + "add.l @(0x12345678:32,er3),@(0xc:2,er1)" +gdb_test "x" "add.l\t@\\(0x12345678(:32|),er3\\),@-er1" \ + "add.l @(0x12345678:32,er3),@-er1" +gdb_test "x" "add.l\t@\\(0x12345678(:32|),er3\\),@er1\\+" \ + "add.l @(0x12345678:32,er3),@er1+" +gdb_test "x" "add.l\t@\\(0x12345678(:32|),er3\\),@er1-" \ + "add.l @(0x12345678:32,er3),@er1-" +gdb_test "x" "add.l\t@\\(0x12345678(:32|),er3\\),@\\+er1" \ + "add.l @(0x12345678:32,er3),@+er1" +gdb_test "x" "add.l\t@\\(0x12345678(:32|),er3\\),@\\(0x9abc(:16|),er1\\)" \ + "add.l @(0x12345678:32,er3),@(0x9abc:16,er1)" +gdb_test "x" "add.l\t@\\(0x12345678(:32|),er3\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "add.l @(0x12345678:32,er3),@(0x9abcdef0:32,er1)" +gdb_test "x" "add.l\t@\\(0x12345678(:32|),er3\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "add.l @(0x12345678:32,er3),@(0x9abc:16,r2l.b)" +gdb_test "x" "add.l\t@\\(0x12345678(:32|),er3\\),@\\(0x9abc(:16|),r2.w\\)" \ + "add.l @(0x12345678:32,er3),@(0x9abc:16,r2.w)" +gdb_test "x" "add.l\t@\\(0x12345678(:32|),er3\\),@\\(0x9abc(:16|),er2.l\\)" \ + "add.l @(0x12345678:32,er3),@(0x9abc:16,er2.l)" +gdb_test "x" "add.l\t@\\(0x12345678(:32|),er3\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "add.l @(0x12345678:32,er3),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "add.l\t@\\(0x12345678(:32|),er3\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "add.l @(0x12345678:32,er3),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "add.l\t@\\(0x12345678(:32|),er3\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "add.l @(0x12345678:32,er3),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "add.l\t@\\(0x12345678(:32|),er3\\),@0x9abc(:16|)" \ + "add.l @(0x12345678:32,er3),@0x9abc:16" +gdb_test "x" "add.l\t@\\(0x12345678(:32|),er3\\),@0x9abcdef0(:32|)" \ + "add.l @(0x12345678:32,er3),@0x9abcdef0:32" +gdb_test "x" "add.l\t@\\(0x1234(:16|),r3l.b\\),@er1" \ + "add.l @(0x1234:16,r3l.b),@er1" +gdb_test "x" "add.l\t@\\(0x1234(:16|),r3l.b\\),@\\(0xc(:2|),er1\\)" \ + "add.l @(0x1234:16,r3l.b),@(0xc:2,er1)" +gdb_test "x" "add.l\t@\\(0x1234(:16|),r3l.b\\),@-er1" \ + "add.l @(0x1234:16,r3l.b),@-er1" +gdb_test "x" "add.l\t@\\(0x1234(:16|),r3l.b\\),@er1\\+" \ + "add.l @(0x1234:16,r3l.b),@er1+" +gdb_test "x" "add.l\t@\\(0x1234(:16|),r3l.b\\),@er1-" \ + "add.l @(0x1234:16,r3l.b),@er1-" +gdb_test "x" "add.l\t@\\(0x1234(:16|),r3l.b\\),@\\+er1" \ + "add.l @(0x1234:16,r3l.b),@+er1" +gdb_test "x" "add.l\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abc(:16|),er1\\)" \ + "add.l @(0x1234:16,r3l.b),@(0x9abc:16,er1)" +gdb_test "x" "add.l\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "add.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1)" +gdb_test "x" "add.l\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "add.l @(0x1234:16,r3l.b),@(0x9abc:16,r2l.b)" +gdb_test "x" "add.l\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abc(:16|),r2.w\\)" \ + "add.l @(0x1234:16,r3l.b),@(0x9abc:16,r2.w)" +gdb_test "x" "add.l\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abc(:16|),er2.l\\)" \ + "add.l @(0x1234:16,r3l.b),@(0x9abc:16,er2.l)" +gdb_test "x" "add.l\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "add.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "add.l\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "add.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "add.l\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "add.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "add.l\t@\\(0x1234(:16|),r3l.b\\),@0x9abc(:16|)" \ + "add.l @(0x1234:16,r3l.b),@0x9abc:16" +gdb_test "x" "add.l\t@\\(0x1234(:16|),r3l.b\\),@0x9abcdef0(:32|)" \ + "add.l @(0x1234:16,r3l.b),@0x9abcdef0:32" +gdb_test "x" "add.l\t@\\(0x1234(:16|),r3.w\\),@er1" \ + "add.l @(0x1234:16,r3.w),@er1" +gdb_test "x" "add.l\t@\\(0x1234(:16|),r3.w\\),@\\(0xc(:2|),er1\\)" \ + "add.l @(0x1234:16,r3.w),@(0xc:2,er1)" +gdb_test "x" "add.l\t@\\(0x1234(:16|),r3.w\\),@-er1" \ + "add.l @(0x1234:16,r3.w),@-er1" +gdb_test "x" "add.l\t@\\(0x1234(:16|),r3.w\\),@er1\\+" \ + "add.l @(0x1234:16,r3.w),@er1+" +gdb_test "x" "add.l\t@\\(0x1234(:16|),r3.w\\),@er1-" \ + "add.l @(0x1234:16,r3.w),@er1-" +gdb_test "x" "add.l\t@\\(0x1234(:16|),r3.w\\),@\\+er1" \ + "add.l @(0x1234:16,r3.w),@+er1" +gdb_test "x" "add.l\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abc(:16|),er1\\)" \ + "add.l @(0x1234:16,r3.w),@(0x9abc:16,er1)" +gdb_test "x" "add.l\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "add.l @(0x1234:16,r3.w),@(0x9abcdef0:32,er1)" +gdb_test "x" "add.l\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "add.l @(0x1234:16,r3.w),@(0x9abc:16,r2l.b)" +gdb_test "x" "add.l\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abc(:16|),r2.w\\)" \ + "add.l @(0x1234:16,r3.w),@(0x9abc:16,r2.w)" +gdb_test "x" "add.l\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abc(:16|),er2.l\\)" \ + "add.l @(0x1234:16,r3.w),@(0x9abc:16,er2.l)" +gdb_test "x" "add.l\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "add.l @(0x1234:16,r3.w),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "add.l\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "add.l @(0x1234:16,r3.w),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "add.l\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "add.l @(0x1234:16,r3.w),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "add.l\t@\\(0x1234(:16|),r3.w\\),@0x9abc(:16|)" \ + "add.l @(0x1234:16,r3.w),@0x9abc:16" +gdb_test "x" "add.l\t@\\(0x1234(:16|),r3.w\\),@0x9abcdef0(:32|)" \ + "add.l @(0x1234:16,r3.w),@0x9abcdef0:32" +gdb_test "x" "add.l\t@\\(0x1234(:16|),er3.l\\),@er1" \ + "add.l @(0x1234:16,er3.l),@er1" +gdb_test "x" "add.l\t@\\(0x1234(:16|),er3.l\\),@\\(0xc(:2|),er1\\)" \ + "add.l @(0x1234:16,er3.l),@(0xc:2,er1)" +gdb_test "x" "add.l\t@\\(0x1234(:16|),er3.l\\),@-er1" \ + "add.l @(0x1234:16,er3.l),@-er1" +gdb_test "x" "add.l\t@\\(0x1234(:16|),er3.l\\),@er1\\+" \ + "add.l @(0x1234:16,er3.l),@er1+" +gdb_test "x" "add.l\t@\\(0x1234(:16|),er3.l\\),@er1-" \ + "add.l @(0x1234:16,er3.l),@er1-" +gdb_test "x" "add.l\t@\\(0x1234(:16|),er3.l\\),@\\+er1" \ + "add.l @(0x1234:16,er3.l),@+er1" +gdb_test "x" "add.l\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abc(:16|),er1\\)" \ + "add.l @(0x1234:16,er3.l),@(0x9abc:16,er1)" +gdb_test "x" "add.l\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "add.l @(0x1234:16,er3.l),@(0x9abcdef0:32,er1)" +gdb_test "x" "add.l\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "add.l @(0x1234:16,er3.l),@(0x9abc:16,r2l.b)" +gdb_test "x" "add.l\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abc(:16|),r2.w\\)" \ + "add.l @(0x1234:16,er3.l),@(0x9abc:16,r2.w)" +gdb_test "x" "add.l\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abc(:16|),er2.l\\)" \ + "add.l @(0x1234:16,er3.l),@(0x9abc:16,er2.l)" +gdb_test "x" "add.l\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "add.l @(0x1234:16,er3.l),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "add.l\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "add.l @(0x1234:16,er3.l),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "add.l\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "add.l @(0x1234:16,er3.l),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "add.l\t@\\(0x1234(:16|),er3.l\\),@0x9abc(:16|)" \ + "add.l @(0x1234:16,er3.l),@0x9abc:16" +gdb_test "x" "add.l\t@\\(0x1234(:16|),er3.l\\),@0x9abcdef0(:32|)" \ + "add.l @(0x1234:16,er3.l),@0x9abcdef0:32" +gdb_test "x" "add.l\t@\\(0x12345678(:32|),r3l.b\\),@er1" \ + "add.l @(0x12345678:32,r3l.b),@er1" +gdb_test "x" "add.l\t@\\(0x12345678(:32|),r3l.b\\),@\\(0xc(:2|),er1\\)" \ + "add.l @(0x12345678:32,r3l.b),@(0xc:2,er1)" +gdb_test "x" "add.l\t@\\(0x12345678(:32|),r3l.b\\),@-er1" \ + "add.l @(0x12345678:32,r3l.b),@-er1" +gdb_test "x" "add.l\t@\\(0x12345678(:32|),r3l.b\\),@er1\\+" \ + "add.l @(0x12345678:32,r3l.b),@er1+" +gdb_test "x" "add.l\t@\\(0x12345678(:32|),r3l.b\\),@er1-" \ + "add.l @(0x12345678:32,r3l.b),@er1-" +gdb_test "x" "add.l\t@\\(0x12345678(:32|),r3l.b\\),@\\+er1" \ + "add.l @(0x12345678:32,r3l.b),@+er1" +gdb_test "x" "add.l\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abc(:16|),er1\\)" \ + "add.l @(0x12345678:32,r3l.b),@(0x9abc:16,er1)" +gdb_test "x" "add.l\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "add.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1)" +gdb_test "x" "add.l\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "add.l @(0x12345678:32,r3l.b),@(0x9abc:16,r2l.b)" +gdb_test "x" "add.l\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abc(:16|),r2.w\\)" \ + "add.l @(0x12345678:32,r3l.b),@(0x9abc:16,r2.w)" +gdb_test "x" "add.l\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abc(:16|),er2.l\\)" \ + "add.l @(0x12345678:32,r3l.b),@(0x9abc:16,er2.l)" +gdb_test "x" "add.l\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "add.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "add.l\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "add.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "add.l\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "add.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "add.l\t@\\(0x12345678(:32|),r3l.b\\),@0x9abc(:16|)" \ + "add.l @(0x12345678:32,r3l.b),@0x9abc:16" +gdb_test "x" "add.l\t@\\(0x12345678(:32|),r3l.b\\),@0x9abcdef0(:32|)" \ + "add.l @(0x12345678:32,r3l.b),@0x9abcdef0:32" +gdb_test "x" "add.l\t@\\(0x12345678(:32|),r3.w\\),@er1" \ + "add.l @(0x12345678:32,r3.w),@er1" +gdb_test "x" "add.l\t@\\(0x12345678(:32|),r3.w\\),@\\(0xc(:2|),er1\\)" \ + "add.l @(0x12345678:32,r3.w),@(0xc:2,er1)" +gdb_test "x" "add.l\t@\\(0x12345678(:32|),r3.w\\),@-er1" \ + "add.l @(0x12345678:32,r3.w),@-er1" +gdb_test "x" "add.l\t@\\(0x12345678(:32|),r3.w\\),@er1\\+" \ + "add.l @(0x12345678:32,r3.w),@er1+" +gdb_test "x" "add.l\t@\\(0x12345678(:32|),r3.w\\),@er1-" \ + "add.l @(0x12345678:32,r3.w),@er1-" +gdb_test "x" "add.l\t@\\(0x12345678(:32|),r3.w\\),@\\+er1" \ + "add.l @(0x12345678:32,r3.w),@+er1" +gdb_test "x" "add.l\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abc(:16|),er1\\)" \ + "add.l @(0x12345678:32,r3.w),@(0x9abc:16,er1)" +gdb_test "x" "add.l\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "add.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1)" +gdb_test "x" "add.l\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "add.l @(0x12345678:32,r3.w),@(0x9abc:16,r2l.b)" +gdb_test "x" "add.l\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abc(:16|),r2.w\\)" \ + "add.l @(0x12345678:32,r3.w),@(0x9abc:16,r2.w)" +gdb_test "x" "add.l\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abc(:16|),er2.l\\)" \ + "add.l @(0x12345678:32,r3.w),@(0x9abc:16,er2.l)" +gdb_test "x" "add.l\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "add.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "add.l\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "add.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "add.l\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "add.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "add.l\t@\\(0x12345678(:32|),r3.w\\),@0x9abc(:16|)" \ + "add.l @(0x12345678:32,r3.w),@0x9abc:16" +gdb_test "x" "add.l\t@\\(0x12345678(:32|),r3.w\\),@0x9abcdef0(:32|)" \ + "add.l @(0x12345678:32,r3.w),@0x9abcdef0:32" +gdb_test "x" "add.l\t@\\(0x12345678(:32|),er3.l\\),@er1" \ + "add.l @(0x12345678:32,er3.l),@er1" +gdb_test "x" "add.l\t@\\(0x12345678(:32|),er3.l\\),@\\(0xc(:2|),er1\\)" \ + "add.l @(0x12345678:32,er3.l),@(0xc:2,er1)" +gdb_test "x" "add.l\t@\\(0x12345678(:32|),er3.l\\),@-er1" \ + "add.l @(0x12345678:32,er3.l),@-er1" +gdb_test "x" "add.l\t@\\(0x12345678(:32|),er3.l\\),@er1\\+" \ + "add.l @(0x12345678:32,er3.l),@er1+" +gdb_test "x" "add.l\t@\\(0x12345678(:32|),er3.l\\),@er1-" \ + "add.l @(0x12345678:32,er3.l),@er1-" +gdb_test "x" "add.l\t@\\(0x12345678(:32|),er3.l\\),@\\+er1" \ + "add.l @(0x12345678:32,er3.l),@+er1" +gdb_test "x" "add.l\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abc(:16|),er1\\)" \ + "add.l @(0x12345678:32,er3.l),@(0x9abc:16,er1)" +gdb_test "x" "add.l\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "add.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1)" +gdb_test "x" "add.l\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "add.l @(0x12345678:32,er3.l),@(0x9abc:16,r2l.b)" +gdb_test "x" "add.l\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abc(:16|),r2.w\\)" \ + "add.l @(0x12345678:32,er3.l),@(0x9abc:16,r2.w)" +gdb_test "x" "add.l\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abc(:16|),er2.l\\)" \ + "add.l @(0x12345678:32,er3.l),@(0x9abc:16,er2.l)" +gdb_test "x" "add.l\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "add.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "add.l\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "add.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "add.l\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "add.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "add.l\t@\\(0x12345678(:32|),er3.l\\),@0x9abc(:16|)" \ + "add.l @(0x12345678:32,er3.l),@0x9abc:16" +gdb_test "x" "add.l\t@\\(0x12345678(:32|),er3.l\\),@0x9abcdef0(:32|)" \ + "add.l @(0x12345678:32,er3.l),@0x9abcdef0:32" +gdb_test "x" "add.l\t@0x1234(:16|),@er1" \ + "add.l @0x1234:16,@er1" +gdb_test "x" "add.l\t@0x1234(:16|),@\\(0xc(:2|),er1\\)" \ + "add.l @0x1234:16,@(0xc:2,er1)" +gdb_test "x" "add.l\t@0x1234(:16|),@-er1" \ + "add.l @0x1234:16,@-er1" +gdb_test "x" "add.l\t@0x1234(:16|),@er1\\+" \ + "add.l @0x1234:16,@er1+" +gdb_test "x" "add.l\t@0x1234(:16|),@er1-" \ + "add.l @0x1234:16,@er1-" +gdb_test "x" "add.l\t@0x1234(:16|),@\\+er1" \ + "add.l @0x1234:16,@+er1" +gdb_test "x" "add.l\t@0x1234(:16|),@\\(0x9abc(:16|),er1\\)" \ + "add.l @0x1234:16,@(0x9abc:16,er1)" +gdb_test "x" "add.l\t@0x1234(:16|),@\\(0x9abcdef0(:32|),er1\\)" \ + "add.l @0x1234:16,@(0x9abcdef0:32,er1)" +gdb_test "x" "add.l\t@0x1234(:16|),@\\(0x9abc(:16|),r2l.b\\)" \ + "add.l @0x1234:16,@(0x9abc:16,r2l.b)" +gdb_test "x" "add.l\t@0x1234(:16|),@\\(0x9abc(:16|),r2.w\\)" \ + "add.l @0x1234:16,@(0x9abc:16,r2.w)" +gdb_test "x" "add.l\t@0x1234(:16|),@\\(0x9abc(:16|),er2.l\\)" \ + "add.l @0x1234:16,@(0x9abc:16,er2.l)" +gdb_test "x" "add.l\t@0x1234(:16|),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "add.l @0x1234:16,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "add.l\t@0x1234(:16|),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "add.l @0x1234:16,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "add.l\t@0x1234(:16|),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "add.l @0x1234:16,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "add.l\t@0x1234(:16|),@0x9abc(:16|)" \ + "add.l @0x1234:16,@0x9abc:16" +gdb_test "x" "add.l\t@0x1234(:16|),@0x9abcdef0(:32|)" \ + "add.l @0x1234:16,@0x9abcdef0:32" +gdb_test "x" "add.l\t@0x12345678(:32|),@er1" \ + "add.l @0x12345678:32,@er1" +gdb_test "x" "add.l\t@0x12345678(:32|),@\\(0xc(:2|),er1\\)" \ + "add.l @0x12345678:32,@(0xc:2,er1)" +gdb_test "x" "add.l\t@0x12345678(:32|),@-er1" \ + "add.l @0x12345678:32,@-er1" +gdb_test "x" "add.l\t@0x12345678(:32|),@er1\\+" \ + "add.l @0x12345678:32,@er1+" +gdb_test "x" "add.l\t@0x12345678(:32|),@er1-" \ + "add.l @0x12345678:32,@er1-" +gdb_test "x" "add.l\t@0x12345678(:32|),@\\+er1" \ + "add.l @0x12345678:32,@+er1" +gdb_test "x" "add.l\t@0x12345678(:32|),@\\(0x9abc(:16|),er1\\)" \ + "add.l @0x12345678:32,@(0x9abc:16,er1)" +gdb_test "x" "add.l\t@0x12345678(:32|),@\\(0x9abcdef0(:32|),er1\\)" \ + "add.l @0x12345678:32,@(0x9abcdef0:32,er1)" +gdb_test "x" "add.l\t@0x12345678(:32|),@\\(0x9abc(:16|),r2l.b\\)" \ + "add.l @0x12345678:32,@(0x9abc:16,r2l.b)" +gdb_test "x" "add.l\t@0x12345678(:32|),@\\(0x9abc(:16|),r2.w\\)" \ + "add.l @0x12345678:32,@(0x9abc:16,r2.w)" +gdb_test "x" "add.l\t@0x12345678(:32|),@\\(0x9abc(:16|),er2.l\\)" \ + "add.l @0x12345678:32,@(0x9abc:16,er2.l)" +gdb_test "x" "add.l\t@0x12345678(:32|),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "add.l @0x12345678:32,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "add.l\t@0x12345678(:32|),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "add.l @0x12345678:32,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "add.l\t@0x12345678(:32|),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "add.l @0x12345678:32,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "add.l\t@0x12345678(:32|),@0x9abc(:16|)" \ + "add.l @0x12345678:32,@0x9abc:16" +gdb_test "x" "add.l\t@0x12345678(:32|),@0x9abcdef0(:32|)" \ + "add.l @0x12345678:32,@0x9abcdef0:32" diff --git a/gdb/testsuite/gdb.disasm/t03_add.s b/gdb/testsuite/gdb.disasm/t03_add.s new file mode 100644 index 0000000..a20aded --- /dev/null +++ b/gdb/testsuite/gdb.disasm/t03_add.s @@ -0,0 +1,978 @@ +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;arith_1 +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + .h8300sx + .text + .global _start +_start: + add.b #0x12:8,r1h ;8112 + add.b #0x12:8,@er1 ;7d108012 + add.b #0x12:8,@(0x3:2,er1) ;017768188012 + add.b #0x12:8,@er1+ ;01746c188012 + add.b #0x12:8,@-er1 ;01776c188012 + add.b #0x12:8,@+er1 ;01756c188012 + add.b #0x12:8,@er1- ;01766c188012 + add.b #0x12:8,@(0x1234:16,er1) ;01746e1812348012 + add.b #0x12:8,@(0x12345678:32,er1) ;78146a28123456788012 + add.b #0x12:8,@(0x1234:16,r2l.b) ;01756e2812348012 + add.b #0x12:8,@(0x1234:16,r2.w) ;01766e2812348012 + add.b #0x12:8,@(0x1234:16,er2.l) ;01776e2812348012 + add.b #0x12:8,@(0x12345678:32,r2l.b) ;78256a28123456788012 + add.b #0x12:8,@(0x12345678:32,r2.w) ;78266a28123456788012 + add.b #0x12:8,@(0x12345678:32,er2.l) ;78276a28123456788012 + add.b #0x12:8,@0xffffff9a:8 ;7f9a8012 + add.b #0x12:8,@0x1234:16 ;6a1812348012 + add.b #0x12:8,@0x12345678:32 ;6a38123456788012 + + add.b r3h,r1h ;0831 + + add.b r3h,@er1 ;7d100830 + add.b r3h,@(0x3:2,er1) ;01793113 + add.b r3h,@er1+ ;01798113 + add.b r3h,@-er1 ;0179b113 + add.b r3h,@+er1 ;01799113 + add.b r3h,@er1- ;0179a113 + add.b r3h,@(0x1234:16,er1) ;0179c1131234 + add.b r3h,@(0x12345678:32,er1) ;0179c91312345678 + add.b r3h,@(0x1234:16,r2l.b) ;0179d2131234 + add.b r3h,@(0x1234:16,r2.w) ;0179e2131234 + add.b r3h,@(0x1234:16,er2.l) ;0179f2131234 + add.b r3h,@(0x12345678:32,r2l.b) ;0179da1312345678 + add.b r3h,@(0x12345678:32,r2.w) ;0179ea1312345678 + add.b r3h,@(0x12345678:32,er2.l) ;0179fa1312345678 + add.b r3h,@0xffffff12:8 ;7f120830 + add.b r3h,@0x1234:16 ;6a1812340830 + add.b r3h,@0x12345678:32 ;6a38123456780830 + + add.b @er3,r1h ;7c300801 + add.b @(0x3:2,er3),r1h ;017a3311 + add.b @er3+,r1h ;017a8311 + add.b @-er3,r1h ;017ab311 + add.b @+er3,r1h ;017a9311 + add.b @er3-,r1h ;017aa311 + add.b @(0x1234:16,er1),r1h ;017ac1111234 + add.b @(0x12345678:32,er1),r1h ;017ac91112345678 + add.b @(0x1234:16,r2l.b),r1h ;017ad2111234 + add.b @(0x1234:16,r2.w),r1h ;017ae2111234 + add.b @(0x1234:16,er2.l),r1h ;017af2111234 + add.b @(0x12345678:32,r2l.b),r1h ;017ada1112345678 + add.b @(0x12345678:32,r2.w),r1h ;017aea1112345678 + add.b @(0x12345678:32,er2.l),r1h ;017afa1112345678 + add.b @0xffffff12:8,r1h ;7e120801 + add.b @0x1234:16,r1h ;6a1012340801 + add.b @0x12345678:32,r1h ;6a30123456780801 + + add.b @er3,@er1 ;7c350110 + add.b @er3,@(3:2,er1) ;7c353110 + add.b @er3,@-er1 ;7c35b110 + add.b @er3,@er1+ ;7c358110 + add.b @er3,@er1- ;7c35a110 + add.b @er3,@+er1 ;7c359110 + add.b @er3,@(0xffff9abc:16,er1) ;7c35c1109abc + add.b @er3,@(0x9abcdef0:32,er1) ;7c35c9109abcdef0 + add.b @er3,@(0xffff9abc:16,r2l.b) ;7c35d2109abc + add.b @er3,@(0xffff9abc:16,r2.w) ;7c35e2109abc + add.b @er3,@(0xffff9abc:16,er2.l) ;7c35f2109abc + add.b @er3,@(0x9abcdef0:32,r2l.b) ;7c35da109abcdef0 + add.b @er3,@(0x9abcdef0:32,r2.w) ;7c35ea109abcdef0 + add.b @er3,@(0x9abcdef0:32,er2.l) ;7c35fa109abcdef0 + add.b @er3,@0xffff9abc:16 ;7c3540109abc + add.b @er3,@0x9abcdef0:32 ;7c3548109abcdef0 + + add.b @-er3,@er1 ;01776c3c0110 + add.b @-er3,@(3:2,er1) ;01776c3c3110 + add.b @-er3,@-er1 ;01776c3cb110 + add.b @-er3,@er1+ ;01776c3c8110 + add.b @-er3,@er1- ;01776c3ca110 + add.b @-er3,@+er1 ;01776c3c9110 + add.b @-er3,@(0xffff9abc:16,er1) ;01776c3cc1109abc + add.b @-er3,@(0x9abcdef0:32,er1) ;01776c3cc9109abcdef0 + add.b @-er3,@(0xffff9abc:16,r2l.b) ;01776c3cd2109abc + add.b @-er3,@(0xffff9abc:16,r2.w) ;01776c3ce2109abc + add.b @-er3,@(0xffff9abc:16,er2.l) ;01776c3cf2109abc + add.b @-er3,@(0x9abcdef0:32,r2l.b) ;01776c3cda109abcdef0 + add.b @-er3,@(0x9abcdef0:32,r2.w) ;01776c3cea109abcdef0 + add.b @-er3,@(0x9abcdef0:32,er2.l) ;01776c3cfa109abcdef0 + add.b @-er3,@0xffff9abc:16 ;01776c3c40109abc + add.b @-er3,@0x9abcdef0:32 ;01776c3c48109abcdef0 + + add.b @er3+,@er1 ;01746c3c0110 + add.b @er3+,@(3:2,er1) ;01746c3c3110 + add.b @er3+,@-er1 ;01746c3cb110 + add.b @er3+,@er1+ ;01746c3c8110 + add.b @er3+,@er1- ;01746c3ca110 + add.b @er3+,@+er1 ;01746c3c9110 + add.b @er3+,@(0xffff9abc:16,er1) ;01746c3cc1109abc + add.b @er3+,@(0x9abcdef0:32,er1) ;01746c3cc9109abcdef0 + add.b @er3+,@(0xffff9abc:16,r2l.b) ;01746c3cd2109abc + add.b @er3+,@(0xffff9abc:16,r2.w) ;01746c3ce2109abc + add.b @er3+,@(0xffff9abc:16,er2.l) ;01746c3cf2109abc + add.b @er3+,@(0x9abcdef0:32,r2l.b) ;01746c3cda109abcdef0 + add.b @er3+,@(0x9abcdef0:32,r2.w) ;01746c3cea109abcdef0 + add.b @er3+,@(0x9abcdef0:32,er2.l) ;01746c3cfa109abcdef0 + add.b @er3+,@0xffff9abc:16 ;01746c3c40109abc + add.b @er3+,@0x9abcdef0:32 ;01746c3c48109abcdef0 + + add.b @er3-,@er1 ;01766c3c0110 + add.b @er3-,@(3:2,er1) ;01766c3c3110 + add.b @er3-,@-er1 ;01766c3cb110 + add.b @er3-,@er1+ ;01766c3c8110 + add.b @er3-,@er1- ;01766c3ca110 + add.b @er3-,@+er1 ;01766c3c9110 + add.b @er3-,@(0xffff9abc:16,er1) ;01766c3cc1109abc + add.b @er3-,@(0x9abcdef0:32,er1) ;01766c3cc9109abcdef0 + add.b @er3-,@(0xffff9abc:16,r2l.b) ;01766c3cd2109abc + add.b @er3-,@(0xffff9abc:16,r2.w) ;01766c3ce2109abc + add.b @er3-,@(0xffff9abc:16,er2.l) ;01766c3cf2109abc + add.b @er3-,@(0x9abcdef0:32,r2l.b) ;01766c3cda109abcdef0 + add.b @er3-,@(0x9abcdef0:32,r2.w) ;01766c3cea109abcdef0 + add.b @er3-,@(0x9abcdef0:32,er2.l) ;01766c3cfa109abcdef0 + add.b @er3-,@0xffff9abc:16 ;01766c3c40109abc + add.b @er3-,@0x9abcdef0:32 ;01766c3c48109abcdef0 + + add.b @+er3,@er1 ;01756c3c0110 + add.b @+er3,@(3:2,er1) ;01756c3c3110 + add.b @+er3,@-er1 ;01756c3cb110 + add.b @+er3,@er1+ ;01756c3c8110 + add.b @+er3,@er1- ;01756c3ca110 + add.b @+er3,@+er1 ;01756c3c9110 + add.b @+er3,@(0xffff9abc:16,er1) ;01756c3cc1109abc + add.b @+er3,@(0x9abcdef0:32,er1) ;01756c3cc9109abcdef0 + add.b @+er3,@(0xffff9abc:16,r2l.b) ;01756c3cd2109abc + add.b @+er3,@(0xffff9abc:16,r2.w) ;01756c3ce2109abc + add.b @+er3,@(0xffff9abc:16,er2.l) ;01756c3cf2109abc + add.b @+er3,@(0x9abcdef0:32,r2l.b) ;01756c3cda109abcdef0 + add.b @+er3,@(0x9abcdef0:32,r2.w) ;01756c3cea109abcdef0 + add.b @+er3,@(0x9abcdef0:32,er2.l) ;01756c3cfa109abcdef0 + add.b @+er3,@0xffff9abc:16 ;01756c3c40109abc + add.b @+er3,@0x9abcdef0:32 ;01756c3c48109abcdef0 + + add.b @(0x1234:16,er3),@er1 ;01746e3c12340110 + add.b @(0x1234:16,er3),@(3:2,er1) ;01746e3c12343110 + add.b @(0x1234:16,er3),@-er1 ;01746e3c1234b110 + add.b @(0x1234:16,er3),@er1+ ;01746e3c12348110 + add.b @(0x1234:16,er3),@er1- ;01746e3c1234a110 + add.b @(0x1234:16,er3),@+er1 ;01746e3c12349110 + add.b @(0x1234:16,er3),@(0xffff9abc:16,er1) ;01746e3c1234c1109abc + add.b @(0x1234:16,er3),@(0x9abcdef0:32,er1) ;01746e3c1234c9109abcdef0 + add.b @(0x1234:16,er3),@(0xffff9abc:16,r2l.b) ;01746e3c1234d2109abc + add.b @(0x1234:16,er3),@(0xffff9abc:16,r2.w) ;01746e3c1234e2109abc + add.b @(0x1234:16,er3),@(0xffff9abc:16,er2.l) ;01746e3c1234f2109abc + add.b @(0x1234:16,er3),@(0x9abcdef0:32,r2l.b) ;01746e3c1234da109abcdef0 + add.b @(0x1234:16,er3),@(0x9abcdef0:32,r2.w) ;01746e3c1234ea109abcdef0 + add.b @(0x1234:16,er3),@(0x9abcdef0:32,er2.l) ;01746e3c1234fa109abcdef0 + add.b @(0x1234:16,er3),@0xffff9abc:16 ;01746e3c123440109abc + add.b @(0x1234:16,er3),@0x9abcdef0:32 ;01746e3c123448109abcdef0 + + add.b @(0x12345678:32,er3),@er1 ;78346a2c123456780110 + add.b @(0x12345678:32,er3),@(3:2,er1) ;78346a2c123456783110 + add.b @(0x12345678:32,er3),@-er1 ;78346a2c12345678b110 + add.b @(0x12345678:32,er3),@er1+ ;78346a2c123456788110 + add.b @(0x12345678:32,er3),@er1- ;78346a2c12345678a110 + add.b @(0x12345678:32,er3),@+er1 ;78346a2c123456789110 + add.b @(0x12345678:32,er3),@(0xffff9abc:16,er1) ;78346a2c12345678c1109abc + add.b @(0x12345678:32,er3),@(0x9abcdef0:32,er1) ;78346a2c12345678c9109abcdef0 + add.b @(0x12345678:32,er3),@(0xffff9abc:16,r2l.b) ;78346a2c12345678d2109abc + add.b @(0x12345678:32,er3),@(0xffff9abc:16,r2.w) ;78346a2c12345678e2109abc + add.b @(0x12345678:32,er3),@(0xffff9abc:16,er2.l) ;78346a2c12345678f2109abc + add.b @(0x12345678:32,er3),@(0x9abcdef0:32,r2l.b) ;78346a2c12345678da109abcdef0 + add.b @(0x12345678:32,er3),@(0x9abcdef0:32,r2.w) ;78346a2c12345678ea109abcdef0 + add.b @(0x12345678:32,er3),@(0x9abcdef0:32,er2.l) ;78346a2c12345678fa109abcdef0 + add.b @(0x12345678:32,er3),@0xffff9abc:16 ;78346a2c1234567840109abc + add.b @(0x12345678:32,er3),@0x9abcdef0:32 ;78346a2c1234567848109abcdef0 + + add.b @(0x1234:16,r3l.b),@er1 ;01756e3c12340110 + add.b @(0x1234:16,r3l.b),@(3:2,er1) ;01756e3c12343110 + add.b @(0x1234:16,r3l.b),@-er1 ;01756e3c1234b110 + add.b @(0x1234:16,r3l.b),@er1+ ;01756e3c12348110 + add.b @(0x1234:16,r3l.b),@er1- ;01756e3c1234a110 + add.b @(0x1234:16,r3l.b),@+er1 ;01756e3c12349110 + add.b @(0x1234:16,r3l.b),@(0xffff9abc:16,er1) ;01756e3c1234c1109abc + add.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1) ;01756e3c1234c9109abcdef0 + add.b @(0x1234:16,r3l.b),@(0xffff9abc:16,r2l.b) ;01756e3c1234d2109abc + add.b @(0x1234:16,r3l.b),@(0xffff9abc:16,r2.w) ;01756e3c1234e2109abc + add.b @(0x1234:16,r3l.b),@(0xffff9abc:16,er2.l) ;01756e3c1234f2109abc + add.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2l.b) ;01756e3c1234da109abcdef0 + add.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2.w) ;01756e3c1234ea109abcdef0 + add.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,er2.l) ;01756e3c1234fa109abcdef0 + add.b @(0x1234:16,r3l.b),@0xffff9abc:16 ;01756e3c123440109abc + add.b @(0x1234:16,r3l.b),@0x9abcdef0:32 ;01756e3c123448109abcdef0 + + add.b @(0x1234:16,r3.w),@er1 ;01766e3c12340110 + add.b @(0x1234:16,r3.w),@(3:2,er1) ;01766e3c12343110 + add.b @(0x1234:16,r3.w),@-er1 ;01766e3c1234b110 + add.b @(0x1234:16,r3.w),@er1+ ;01766e3c12348110 + add.b @(0x1234:16,r3.w),@er1- ;01766e3c1234a110 + add.b @(0x1234:16,r3.w),@+er1 ;01766e3c12349110 + add.b @(0x1234:16,r3.w),@(0xffff9abc:16,er1) ;01766e3c1234c1109abc + add.b @(0x1234:16,r3.w),@(0x9abcdef0:32,er1) ;01766e3c1234c9109abcdef0 + add.b @(0x1234:16,r3.w),@(0xffff9abc:16,r2l.b) ;01766e3c1234d2109abc + add.b @(0x1234:16,r3.w),@(0xffff9abc:16,r2.w) ;01766e3c1234e2109abc + add.b @(0x1234:16,r3.w),@(0xffff9abc:16,er2.l) ;01766e3c1234f2109abc + add.b @(0x1234:16,r3.w),@(0x9abcdef0:32,r2l.b) ;01766e3c1234da109abcdef0 + add.b @(0x1234:16,r3.w),@(0x9abcdef0:32,r2.w) ;01766e3c1234ea109abcdef0 + add.b @(0x1234:16,r3.w),@(0x9abcdef0:32,er2.l) ;01766e3c1234fa109abcdef0 + add.b @(0x1234:16,r3.w),@0xffff9abc:16 ;01766e3c123440109abc + add.b @(0x1234:16,r3.w),@0x9abcdef0:32 ;01766e3c123448109abcdef0 + + add.b @(0x1234:16,er3.l),@er1 ;01776e3c12340110 + add.b @(0x1234:16,er3.l),@(3:2,er1) ;01776e3c12343110 + add.b @(0x1234:16,er3.l),@-er1 ;01776e3c1234b110 + add.b @(0x1234:16,er3.l),@er1+ ;01776e3c12348110 + add.b @(0x1234:16,er3.l),@er1- ;01776e3c1234a110 + add.b @(0x1234:16,er3.l),@+er1 ;01776e3c12349110 + add.b @(0x1234:16,er3.l),@(0xffff9abc:16,er1) ;01776e3c1234c1109abc + add.b @(0x1234:16,er3.l),@(0x9abcdef0:32,er1) ;01776e3c1234c9109abcdef0 + add.b @(0x1234:16,er3.l),@(0xffff9abc:16,r2l.b) ;01776e3c1234d2109abc + add.b @(0x1234:16,er3.l),@(0xffff9abc:16,r2.w) ;01776e3c1234e2109abc + add.b @(0x1234:16,er3.l),@(0xffff9abc:16,er2.l) ;01776e3c1234f2109abc + add.b @(0x1234:16,er3.l),@(0x9abcdef0:32,r2l.b) ;01776e3c1234da109abcdef0 + add.b @(0x1234:16,er3.l),@(0x9abcdef0:32,r2.w) ;01776e3c1234ea109abcdef0 + add.b @(0x1234:16,er3.l),@(0x9abcdef0:32,er2.l) ;01776e3c1234fa109abcdef0 + add.b @(0x1234:16,er3.l),@0xffff9abc:16 ;01776e3c123440109abc + add.b @(0x1234:16,er3.l),@0x9abcdef0:32 ;01776e3c123448109abcdef0 + + add.b @(0x12345678:32,r3l.b),@er1 ;78356a2c123456780110 + add.b @(0x12345678:32,r3l.b),@(3:2,er1) ;78356a2c123456783110 + add.b @(0x12345678:32,r3l.b),@-er1 ;78356a2c12345678b110 + add.b @(0x12345678:32,r3l.b),@er1+ ;78356a2c123456788110 + add.b @(0x12345678:32,r3l.b),@er1- ;78356a2c12345678a110 + add.b @(0x12345678:32,r3l.b),@+er1 ;78356a2c123456789110 + add.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,er1) ;78356a2c12345678c1109abc + add.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1) ;78356a2c12345678c9109abcdef0 + add.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2l.b) ;78356a2c12345678d2109abc + add.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2.w) ;78356a2c12345678e2109abc + add.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,er2.l) ;78356a2c12345678f2109abc + add.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2l.b) ;78356a2c12345678da109abcdef0 + add.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2.w) ;78356a2c12345678ea109abcdef0 + add.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er2.l) ;78356a2c12345678fa109abcdef0 + add.b @(0x12345678:32,r3l.b),@0xffff9abc:16 ;78356a2c1234567840109abc + add.b @(0x12345678:32,r3l.b),@0x9abcdef0:32 ;78356a2c1234567848109abcdef0 + + add.b @(0x12345678:32,r3.w),@er1 ;78366a2c123456780110 + add.b @(0x12345678:32,r3.w),@(3:2,er1) ;78366a2c123456783110 + add.b @(0x12345678:32,r3.w),@-er1 ;78366a2c12345678b110 + add.b @(0x12345678:32,r3.w),@er1+ ;78366a2c123456788110 + add.b @(0x12345678:32,r3.w),@er1- ;78366a2c12345678a110 + add.b @(0x12345678:32,r3.w),@+er1 ;78366a2c123456789110 + add.b @(0x12345678:32,r3.w),@(0xffff9abc:16,er1) ;78366a2c12345678c1109abc + add.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1) ;78366a2c12345678c9109abcdef0 + add.b @(0x12345678:32,r3.w),@(0xffff9abc:16,r2l.b) ;78366a2c12345678d2109abc + add.b @(0x12345678:32,r3.w),@(0xffff9abc:16,r2.w) ;78366a2c12345678e2109abc + add.b @(0x12345678:32,r3.w),@(0xffff9abc:16,er2.l) ;78366a2c12345678f2109abc + add.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2l.b) ;78366a2c12345678da109abcdef0 + add.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2.w) ;78366a2c12345678ea109abcdef0 + add.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,er2.l) ;78366a2c12345678fa109abcdef0 + add.b @(0x12345678:32,r3.w),@0xffff9abc:16 ;78366a2c1234567840109abc + add.b @(0x12345678:32,r3.w),@0x9abcdef0:32 ;78366a2c1234567848109abcdef0 + + add.b @(0x12345678:32,er3.l),@er1 ;78376a2c123456780110 + add.b @(0x12345678:32,er3.l),@(3:2,er1) ;78376a2c123456783110 + add.b @(0x12345678:32,er3.l),@-er1 ;78376a2c12345678b110 + add.b @(0x12345678:32,er3.l),@er1+ ;78376a2c123456788110 + add.b @(0x12345678:32,er3.l),@er1- ;78376a2c12345678a110 + add.b @(0x12345678:32,er3.l),@+er1 ;78376a2c123456789110 + add.b @(0x12345678:32,er3.l),@(0xffff9abc:16,er1) ;78376a2c12345678c1109abc + add.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1) ;78376a2c12345678c9109abcdef0 + add.b @(0x12345678:32,er3.l),@(0xffff9abc:16,r2l.b) ;78376a2c12345678d2109abc + add.b @(0x12345678:32,er3.l),@(0xffff9abc:16,r2.w) ;78376a2c12345678e2109abc + add.b @(0x12345678:32,er3.l),@(0xffff9abc:16,er2.l) ;78376a2c12345678f2109abc + add.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2l.b) ;78376a2c12345678da109abcdef0 + add.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2.w) ;78376a2c12345678ea109abcdef0 + add.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,er2.l) ;78376a2c12345678fa109abcdef0 + add.b @(0x12345678:32,er3.l),@0xffff9abc:16 ;78376a2c1234567840109abc + add.b @(0x12345678:32,er3.l),@0x9abcdef0:32 ;78376a2c1234567848109abcdef0 + + add.b @0x1234:16,@er1 ;6a1512340110 + add.b @0x1234:16,@(3:2,er1) ;6a1512343110 + add.b @0x1234:16,@-er1 ;6a151234b110 + add.b @0x1234:16,@er1+ ;6a1512348110 + add.b @0x1234:16,@er1- ;6a151234a110 + add.b @0x1234:16,@+er1 ;6a1512349110 + add.b @0x1234:16,@(0xffff9abc:16,er1) ;6a151234c1109abc + add.b @0x1234:16,@(0x9abcdef0:32,er1) ;6a151234c9109abcdef0 + add.b @0x1234:16,@(0xffff9abc:16,r2l.b) ;6a151234d2109abc + add.b @0x1234:16,@(0xffff9abc:16,r2.w) ;6a151234e2109abc + add.b @0x1234:16,@(0xffff9abc:16,er2.l) ;6a151234f2109abc + add.b @0x1234:16,@(0x9abcdef0:32,r2l.b) ;6a151234da109abcdef0 + add.b @0x1234:16,@(0x9abcdef0:32,r2.w) ;6a151234ea109abcdef0 + add.b @0x1234:16,@(0x9abcdef0:32,er2.l) ;6a151234fa109abcdef0 + add.b @0x1234:16,@0xffff9abc:16 ;6a15123440109abc + add.b @0x1234:16,@0x9abcdef0:32 ;6a15123448109abcdef0 + + add.b @0x12345678:32,@er1 ;6a35123456780110 + add.b @0x12345678:32,@(3:2,er1) ;6a35123456783110 + add.b @0x12345678:32,@-er1 ;6a3512345678b110 + add.b @0x12345678:32,@er1+ ;6a35123456788110 + add.b @0x12345678:32,@er1- ;6a3512345678a110 + add.b @0x12345678:32,@+er1 ;6a35123456789110 + add.b @0x12345678:32,@(0xffff9abc:16,er1) ;6a3512345678c1109abc + add.b @0x12345678:32,@(0x9abcdef0:32,er1) ;6a3512345678c9109abcdef0 + add.b @0x12345678:32,@(0xffff9abc:16,r2l.b) ;6a3512345678d2109abc + add.b @0x12345678:32,@(0xffff9abc:16,r2.w) ;6a3512345678e2109abc + add.b @0x12345678:32,@(0xffff9abc:16,er2.l) ;6a3512345678f2109abc + add.b @0x12345678:32,@(0x9abcdef0:32,r2l.b) ;6a3512345678da109abcdef0 + add.b @0x12345678:32,@(0x9abcdef0:32,r2.w) ;6a3512345678ea109abcdef0 + add.b @0x12345678:32,@(0x9abcdef0:32,er2.l) ;6a3512345678fa109abcdef0 + add.b @0x12345678:32,@0xffff9abc:16 ;6a351234567840109abc + add.b @0x12345678:32,@0x9abcdef0:32 ;6a351234567848109abcdef0 + + add.w #0x1234:16,r1 ;79111234 + add.w #0x7:3,r2 ;0a72 + add.w #0x1234:16,@er1 ;015e01101234 + add.w #0x1234:16,@(0x6:2,er1) ;015e31101234 + add.w #0x1234:16,@er1+ ;015e81101234 + add.w #0x1234:16,@-er1 ;015eb1101234 + add.w #0x1234:16,@+er1 ;015e91101234 + add.w #0x1234:16,@er1- ;015ea1101234 + add.w #0x1234:16,@(0xffff9abc:16,er1) ;015ec1109abc1234 + add.w #0x1234:16,@(0x9abcdef0:32,er1) ;015ec9109abcdef01234 + add.w #0x1234:16,@(0xffff9abc:16,r2l.b) ;015ed2109abc1234 + add.w #0x1234:16,@(0xffff9abc:16,r2.w) ;015ee2109abc1234 + add.w #0x1234:16,@(0xffff9abc:16,er2.l) ;015ef2109abc1234 + add.w #0x1234:16,@(0x9abcdef0:32,r2l.b) ;015eda109abcdef01234 + add.w #0x1234:16,@(0x9abcdef0:32,r2.w) ;015eea109abcdef01234 + add.w #0x1234:16,@(0x9abcdef0:32,er2.l) ;015efa109abcdef01234 + add.w #0x1234:16,@0xffff9abc:16 ;015e40109abc1234 + add.w #0x1234:16,@0x9abcdef0:32 ;015e48109abcdef01234 + + add.w #0x7:3,@er1 ;7d900a70 + add.w #0x7:3,@0x1234:16 ;6b1812340a70 + add.w #0x7:3,@0x12345678:32 ;6b38123456780a70 + + add.w r3,r1 ;0931 + + add.w r3,@er1 ;7d900930 + add.w r3,@(0x6:2,er1) ;01593113 + add.w r3,@er1+ ;01598113 + add.w r3,@-er1 ;0159b113 + add.w r3,@+er1 ;01599113 + add.w r3,@er1- ;0159a113 + add.w r3,@(0x1234:16,er1) ;0159c1131234 + add.w r3,@(0x12345678:32,er1) ;0159c91312345678 + add.w r3,@(0x1234:16,r2l.b) ;0159d2131234 + add.w r3,@(0x1234:16,r2.w) ;0159e2131234 + add.w r3,@(0x1234:16,er2.l) ;0159f2131234 + add.w r3,@(0x12345678:32,r2l.b) ;0159da1312345678 + add.w r3,@(0x12345678:32,r2.w) ;0159ea1312345678 + add.w r3,@(0x12345678:32,er2.l) ;0159fa1312345678 + add.w r3,@0x1234:16 ;6b1812340930 + add.w r3,@0x12345678:32 ;6b38123456780930 + + add.w @er3,r1 ;7cb00901 + add.w @(0x6:2,er1),r1 ;015a3111 + add.w @er3+,r1 ;015a8311 + add.w @-er3,r1 ;015ab311 + add.w @+er3,r1 ;015a9311 + add.w @er3-,r1 ;015aa311 + add.w @(0x1234:16,er1),r1 ;015ac1111234 + add.w @(0x12345678:32,er1),r1 ;015ac91112345678 + add.w @(0x1234:16,r2l.b),r1 ;015ad2111234 + add.w @(0x1234:16,r2.w),r1 ;015ae2111234 + add.w @(0x1234:16,er2.l),r1 ;015af2111234 + add.w @(0x12345678:32,r2l.b),r1 ;015ada1112345678 + add.w @(0x12345678:32,r2.w),r1 ;015aea1112345678 + add.w @(0x12345678:32,er2.l),r1 ;015afa1112345678 + add.w @0x1234:16,r1 ;6b1012340901 + add.w @0x12345678:32,r1 ;6b30123456780901 + + add.w @er3,@er1 ;7cb50110 + add.w @er3,@(6:2,er1) ;7cb53110 + add.w @er3,@-er1 ;7cb5b110 + add.w @er3,@er1+ ;7cb58110 + add.w @er3,@er1- ;7cb5a110 + add.w @er3,@+er1 ;7cb59110 + add.w @er3,@(0xffff9abc:16,er1) ;7cb5c1109abc + add.w @er3,@(0x9abcdef0:32,er1) ;7cb5c9109abcdef0 + add.w @er3,@(0xffff9abc:16,r2l.b) ;7cb5d2109abc + add.w @er3,@(0xffff9abc:16,r2.w) ;7cb5e2109abc + add.w @er3,@(0xffff9abc:16,er2.l) ;7cb5f2109abc + add.w @er3,@(0x9abcdef0:32,r2l.b) ;7cb5da109abcdef0 + add.w @er3,@(0x9abcdef0:32,r2.w) ;7cb5ea109abcdef0 + add.w @er3,@(0x9abcdef0:32,er2.l) ;7cb5fa109abcdef0 + add.w @er3,@0xffff9abc:16 ;7cb540109abc + add.w @er3,@0x9abcdef0:32 ;7cb548109abcdef0 + + add.w @-er3,@er1 ;01576d3c0110 + add.w @-er3,@(6:2,er1) ;01576d3c3110 + add.w @-er3,@-er1 ;01576d3cb110 + add.w @-er3,@er1+ ;01576d3c8110 + add.w @-er3,@er1- ;01576d3ca110 + add.w @-er3,@+er1 ;01576d3c9110 + add.w @-er3,@(0xffff9abc:16,er1) ;01576d3cc1109abc + add.w @-er3,@(0x9abcdef0:32,er1) ;01576d3cc9109abcdef0 + add.w @-er3,@(0xffff9abc:16,r2l.b) ;01576d3cd2109abc + add.w @-er3,@(0xffff9abc:16,r2.w) ;01576d3ce2109abc + add.w @-er3,@(0xffff9abc:16,er2.l) ;01576d3cf2109abc + add.w @-er3,@(0x9abcdef0:32,r2l.b) ;01576d3cda109abcdef0 + add.w @-er3,@(0x9abcdef0:32,r2.w) ;01576d3cea109abcdef0 + add.w @-er3,@(0x9abcdef0:32,er2.l) ;01576d3cfa109abcdef0 + add.w @-er3,@0xffff9abc:16 ;01576d3c40109abc + add.w @-er3,@0x9abcdef0:32 ;01576d3c48109abcdef0 + + add.w @er3+,@er1 ;01546d3c0110 + add.w @er3+,@(6:2,er1) ;01546d3c3110 + add.w @er3+,@-er1 ;01546d3cb110 + add.w @er3+,@er1+ ;01546d3c8110 + add.w @er3+,@er1- ;01546d3ca110 + add.w @er3+,@+er1 ;01546d3c9110 + add.w @er3+,@(0xffff9abc:16,er1) ;01546d3cc1109abc + add.w @er3+,@(0x9abcdef0:32,er1) ;01546d3cc9109abcdef0 + add.w @er3+,@(0xffff9abc:16,r2l.b) ;01546d3cd2109abc + add.w @er3+,@(0xffff9abc:16,r2.w) ;01546d3ce2109abc + add.w @er3+,@(0xffff9abc:16,er2.l) ;01546d3cf2109abc + add.w @er3+,@(0x9abcdef0:32,r2l.b) ;01546d3cda109abcdef0 + add.w @er3+,@(0x9abcdef0:32,r2.w) ;01546d3cea109abcdef0 + add.w @er3+,@(0x9abcdef0:32,er2.l) ;01546d3cfa109abcdef0 + add.w @er3+,@0xffff9abc:16 ;01546d3c40109abc + add.w @er3+,@0x9abcdef0:32 ;01546d3c48109abcdef0 + + add.w @er3-,@er1 ;01566d3c0110 + add.w @er3-,@(6:2,er1) ;01566d3c3110 + add.w @er3-,@-er1 ;01566d3cb110 + add.w @er3-,@er1+ ;01566d3c8110 + add.w @er3-,@er1- ;01566d3ca110 + add.w @er3-,@+er1 ;01566d3c9110 + add.w @er3-,@(0xffff9abc:16,er1) ;01566d3cc1109abc + add.w @er3-,@(0x9abcdef0:32,er1) ;01566d3cc9109abcdef0 + add.w @er3-,@(0xffff9abc:16,r2l.b) ;01566d3cd2109abc + add.w @er3-,@(0xffff9abc:16,r2.w) ;01566d3ce2109abc + add.w @er3-,@(0xffff9abc:16,er2.l) ;01566d3cf2109abc + add.w @er3-,@(0x9abcdef0:32,r2l.b) ;01566d3cda109abcdef0 + add.w @er3-,@(0x9abcdef0:32,r2.w) ;01566d3cea109abcdef0 + add.w @er3-,@(0x9abcdef0:32,er2.l) ;01566d3cfa109abcdef0 + add.w @er3-,@0xffff9abc:16 ;01566d3c40109abc + add.w @er3-,@0x9abcdef0:32 ;01566d3c48109abcdef0 + + add.w @+er3,@er1 ;01556d3c0110 + add.w @+er3,@(6:2,er1) ;01556d3c3110 + add.w @+er3,@-er1 ;01556d3cb110 + add.w @+er3,@er1+ ;01556d3c8110 + add.w @+er3,@er1- ;01556d3ca110 + add.w @+er3,@+er1 ;01556d3c9110 + add.w @+er3,@(0xffff9abc:16,er1) ;01556d3cc1109abc + add.w @+er3,@(0x9abcdef0:32,er1) ;01556d3cc9109abcdef0 + add.w @+er3,@(0xffff9abc:16,r2l.b) ;01556d3cd2109abc + add.w @+er3,@(0xffff9abc:16,r2.w) ;01556d3ce2109abc + add.w @+er3,@(0xffff9abc:16,er2.l) ;01556d3cf2109abc + add.w @+er3,@(0x9abcdef0:32,r2l.b) ;01556d3cda109abcdef0 + add.w @+er3,@(0x9abcdef0:32,r2.w) ;01556d3cea109abcdef0 + add.w @+er3,@(0x9abcdef0:32,er2.l) ;01556d3cfa109abcdef0 + add.w @+er3,@0xffff9abc:16 ;01556d3c40109abc + add.w @+er3,@0x9abcdef0:32 ;01556d3c48109abcdef0 + + add.w @(0x1234:16,er3),@er1 ;01546f3c12340110 + add.w @(0x1234:16,er3),@(6:2,er1) ;01546f3c12343110 + add.w @(0x1234:16,er3),@-er1 ;01546f3c1234b110 + add.w @(0x1234:16,er3),@er1+ ;01546f3c12348110 + add.w @(0x1234:16,er3),@er1- ;01546f3c1234a110 + add.w @(0x1234:16,er3),@+er1 ;01546f3c12349110 + add.w @(0x1234:16,er3),@(0xffff9abc:16,er1) ;01546f3c1234c1109abc + add.w @(0x1234:16,er3),@(0x9abcdef0:32,er1) ;01546f3c1234c9109abcdef0 + add.w @(0x1234:16,er3),@(0xffff9abc:16,r2l.b) ;01546f3c1234d2109abc + add.w @(0x1234:16,er3),@(0xffff9abc:16,r2.w) ;01546f3c1234e2109abc + add.w @(0x1234:16,er3),@(0xffff9abc:16,er2.l) ;01546f3c1234f2109abc + add.w @(0x1234:16,er3),@(0x9abcdef0:32,r2l.b) ;01546f3c1234da109abcdef0 + add.w @(0x1234:16,er3),@(0x9abcdef0:32,r2.w) ;01546f3c1234ea109abcdef0 + add.w @(0x1234:16,er3),@(0x9abcdef0:32,er2.l) ;01546f3c1234fa109abcdef0 + add.w @(0x1234:16,er3),@0xffff9abc:16 ;01546f3c123440109abc + add.w @(0x1234:16,er3),@0x9abcdef0:32 ;01546f3c123448109abcdef0 + + add.w @(0x12345678:32,er3),@er1 ;78346b2c123456780110 + add.w @(0x12345678:32,er3),@(6:2,er1) ;78346b2c123456783110 + add.w @(0x12345678:32,er3),@-er1 ;78346b2c12345678b110 + add.w @(0x12345678:32,er3),@er1+ ;78346b2c123456788110 + add.w @(0x12345678:32,er3),@er1- ;78346b2c12345678a110 + add.w @(0x12345678:32,er3),@+er1 ;78346b2c123456789110 + add.w @(0x12345678:32,er3),@(0xffff9abc:16,er1) ;78346b2c12345678c1109abc + add.w @(0x12345678:32,er3),@(0x9abcdef0:32,er1) ;78346b2c12345678c9109abcdef0 + add.w @(0x12345678:32,er3),@(0xffff9abc:16,r2l.b) ;78346b2c12345678d2109abc + add.w @(0x12345678:32,er3),@(0xffff9abc:16,r2.w) ;78346b2c12345678e2109abc + add.w @(0x12345678:32,er3),@(0xffff9abc:16,er2.l) ;78346b2c12345678f2109abc + add.w @(0x12345678:32,er3),@(0x9abcdef0:32,r2l.b) ;78346b2c12345678da109abcdef0 + add.w @(0x12345678:32,er3),@(0x9abcdef0:32,r2.w) ;78346b2c12345678ea109abcdef0 + add.w @(0x12345678:32,er3),@(0x9abcdef0:32,er2.l) ;78346b2c12345678fa109abcdef0 + add.w @(0x12345678:32,er3),@0xffff9abc:16 ;78346b2c1234567840109abc + add.w @(0x12345678:32,er3),@0x9abcdef0:32 ;78346b2c1234567848109abcdef0 + + add.w @(0x1234:16,r3l.b),@er1 ;01556f3c12340110 + add.w @(0x1234:16,r3l.b),@(6:2,er1) ;01556f3c12343110 + add.w @(0x1234:16,r3l.b),@-er1 ;01556f3c1234b110 + add.w @(0x1234:16,r3l.b),@er1+ ;01556f3c12348110 + add.w @(0x1234:16,r3l.b),@er1- ;01556f3c1234a110 + add.w @(0x1234:16,r3l.b),@+er1 ;01556f3c12349110 + add.w @(0x1234:16,r3l.b),@(0xffff9abc:16,er1) ;01556f3c1234c1109abc + add.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1) ;01556f3c1234c9109abcdef0 + add.w @(0x1234:16,r3l.b),@(0xffff9abc:16,r2l.b) ;01556f3c1234d2109abc + add.w @(0x1234:16,r3l.b),@(0xffff9abc:16,r2.w) ;01556f3c1234e2109abc + add.w @(0x1234:16,r3l.b),@(0xffff9abc:16,er2.l) ;01556f3c1234f2109abc + add.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2l.b) ;01556f3c1234da109abcdef0 + add.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2.w) ;01556f3c1234ea109abcdef0 + add.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,er2.l) ;01556f3c1234fa109abcdef0 + add.w @(0x1234:16,r3l.b),@0xffff9abc:16 ;01556f3c123440109abc + add.w @(0x1234:16,r3l.b),@0x9abcdef0:32 ;01556f3c123448109abcdef0 + + add.w @(0x1234:16,r3.w),@er1 ;01566f3c12340110 + add.w @(0x1234:16,r3.w),@(6:2,er1) ;01566f3c12343110 + add.w @(0x1234:16,r3.w),@-er1 ;01566f3c1234b110 + add.w @(0x1234:16,r3.w),@er1+ ;01566f3c12348110 + add.w @(0x1234:16,r3.w),@er1- ;01566f3c1234a110 + add.w @(0x1234:16,r3.w),@+er1 ;01566f3c12349110 + add.w @(0x1234:16,r3.w),@(0xffff9abc:16,er1) ;01566f3c1234c1109abc + add.w @(0x1234:16,r3.w),@(0x9abcdef0:32,er1) ;01566f3c1234c9109abcdef0 + add.w @(0x1234:16,r3.w),@(0xffff9abc:16,r2l.b) ;01566f3c1234d2109abc + add.w @(0x1234:16,r3.w),@(0xffff9abc:16,r2.w) ;01566f3c1234e2109abc + add.w @(0x1234:16,r3.w),@(0xffff9abc:16,er2.l) ;01566f3c1234f2109abc + add.w @(0x1234:16,r3.w),@(0x9abcdef0:32,r2l.b) ;01566f3c1234da109abcdef0 + add.w @(0x1234:16,r3.w),@(0x9abcdef0:32,r2.w) ;01566f3c1234ea109abcdef0 + add.w @(0x1234:16,r3.w),@(0x9abcdef0:32,er2.l) ;01566f3c1234fa109abcdef0 + add.w @(0x1234:16,r3.w),@0xffff9abc:16 ;01566f3c123440109abc + add.w @(0x1234:16,r3.w),@0x9abcdef0:32 ;01566f3c123448109abcdef0 + + add.w @(0x1234:16,er3.l),@er1 ;01576f3c12340110 + add.w @(0x1234:16,er3.l),@(6:2,er1) ;01576f3c12343110 + add.w @(0x1234:16,er3.l),@-er1 ;01576f3c1234b110 + add.w @(0x1234:16,er3.l),@er1+ ;01576f3c12348110 + add.w @(0x1234:16,er3.l),@er1- ;01576f3c1234a110 + add.w @(0x1234:16,er3.l),@+er1 ;01576f3c12349110 + add.w @(0x1234:16,er3.l),@(0xffff9abc:16,er1) ;01576f3c1234c1109abc + add.w @(0x1234:16,er3.l),@(0x9abcdef0:32,er1) ;01576f3c1234c9109abcdef0 + add.w @(0x1234:16,er3.l),@(0xffff9abc:16,r2l.b) ;01576f3c1234d2109abc + add.w @(0x1234:16,er3.l),@(0xffff9abc:16,r2.w) ;01576f3c1234e2109abc + add.w @(0x1234:16,er3.l),@(0xffff9abc:16,er2.l) ;01576f3c1234f2109abc + add.w @(0x1234:16,er3.l),@(0x9abcdef0:32,r2l.b) ;01576f3c1234da109abcdef0 + add.w @(0x1234:16,er3.l),@(0x9abcdef0:32,r2.w) ;01576f3c1234ea109abcdef0 + add.w @(0x1234:16,er3.l),@(0x9abcdef0:32,er2.l) ;01576f3c1234fa109abcdef0 + add.w @(0x1234:16,er3.l),@0xffff9abc:16 ;01576f3c123440109abc + add.w @(0x1234:16,er3.l),@0x9abcdef0:32 ;01576f3c123448109abcdef0 + + add.w @(0x12345678:32,r3l.b),@er1 ;78356b2c123456780110 + add.w @(0x12345678:32,r3l.b),@(6:2,er1) ;78356b2c123456783110 + add.w @(0x12345678:32,r3l.b),@-er1 ;78356b2c12345678b110 + add.w @(0x12345678:32,r3l.b),@er1+ ;78356b2c123456788110 + add.w @(0x12345678:32,r3l.b),@er1- ;78356b2c12345678a110 + add.w @(0x12345678:32,r3l.b),@+er1 ;78356b2c123456789110 + add.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,er1) ;78356b2c12345678c1109abc + add.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1) ;78356b2c12345678c9109abcdef0 + add.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2l.b) ;78356b2c12345678d2109abc + add.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2.w) ;78356b2c12345678e2109abc + add.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,er2.l) ;78356b2c12345678f2109abc + add.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2l.b) ;78356b2c12345678da109abcdef0 + add.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2.w) ;78356b2c12345678ea109abcdef0 + add.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er2.l) ;78356b2c12345678fa109abcdef0 + add.w @(0x12345678:32,r3l.b),@0xffff9abc:16 ;78356b2c1234567840109abc + add.w @(0x12345678:32,r3l.b),@0x9abcdef0:32 ;78356b2c1234567848109abcdef0 + + add.w @(0x12345678:32,r3.w),@er1 ;78366b2c123456780110 + add.w @(0x12345678:32,r3.w),@(6:2,er1) ;78366b2c123456783110 + add.w @(0x12345678:32,r3.w),@-er1 ;78366b2c12345678b110 + add.w @(0x12345678:32,r3.w),@er1+ ;78366b2c123456788110 + add.w @(0x12345678:32,r3.w),@er1- ;78366b2c12345678a110 + add.w @(0x12345678:32,r3.w),@+er1 ;78366b2c123456789110 + add.w @(0x12345678:32,r3.w),@(0xffff9abc:16,er1) ;78366b2c12345678c1109abc + add.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1) ;78366b2c12345678c9109abcdef0 + add.w @(0x12345678:32,r3.w),@(0xffff9abc:16,r2l.b) ;78366b2c12345678d2109abc + add.w @(0x12345678:32,r3.w),@(0xffff9abc:16,r2.w) ;78366b2c12345678e2109abc + add.w @(0x12345678:32,r3.w),@(0xffff9abc:16,er2.l) ;78366b2c12345678f2109abc + add.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2l.b) ;78366b2c12345678da109abcdef0 + add.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2.w) ;78366b2c12345678ea109abcdef0 + add.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,er2.l) ;78366b2c12345678fa109abcdef0 + add.w @(0x12345678:32,r3.w),@0xffff9abc:16 ;78366b2c1234567840109abc + add.w @(0x12345678:32,r3.w),@0x9abcdef0:32 ;78366b2c1234567848109abcdef0 + + add.w @(0x12345678:32,er3.l),@er1 ;78376b2c123456780110 + add.w @(0x12345678:32,er3.l),@(6:2,er1) ;78376b2c123456783110 + add.w @(0x12345678:32,er3.l),@-er1 ;78376b2c12345678b110 + add.w @(0x12345678:32,er3.l),@er1+ ;78376b2c123456788110 + add.w @(0x12345678:32,er3.l),@er1- ;78376b2c12345678a110 + add.w @(0x12345678:32,er3.l),@+er1 ;78376b2c123456789110 + add.w @(0x12345678:32,er3.l),@(0xffff9abc:16,er1) ;78376b2c12345678c1109abc + add.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1) ;78376b2c12345678c9109abcdef0 + add.w @(0x12345678:32,er3.l),@(0xffff9abc:16,r2l.b) ;78376b2c12345678d2109abc + add.w @(0x12345678:32,er3.l),@(0xffff9abc:16,r2.w) ;78376b2c12345678e2109abc + add.w @(0x12345678:32,er3.l),@(0xffff9abc:16,er2.l) ;78376b2c12345678f2109abc + add.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2l.b) ;78376b2c12345678da109abcdef0 + add.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2.w) ;78376b2c12345678ea109abcdef0 + add.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,er2.l) ;78376b2c12345678fa109abcdef0 + add.w @(0x12345678:32,er3.l),@0xffff9abc:16 ;78376b2c1234567840109abc + add.w @(0x12345678:32,er3.l),@0x9abcdef0:32 ;78376b2c1234567848109abcdef0 + + add.w @0x1234:16,@er1 ;6b1512340110 + add.w @0x1234:16,@(6:2,er1) ;6b1512343110 + add.w @0x1234:16,@-er1 ;6b151234b110 + add.w @0x1234:16,@er1+ ;6b1512348110 + add.w @0x1234:16,@er1- ;6b151234a110 + add.w @0x1234:16,@+er1 ;6b1512349110 + add.w @0x1234:16,@(0xffff9abc:16,er1) ;6b151234c1109abc + add.w @0x1234:16,@(0x9abcdef0:32,er1) ;6b151234c9109abcdef0 + add.w @0x1234:16,@(0xffff9abc:16,r2l.b) ;6b151234d2109abc + add.w @0x1234:16,@(0xffff9abc:16,r2.w) ;6b151234e2109abc + add.w @0x1234:16,@(0xffff9abc:16,er2.l) ;6b151234f2109abc + add.w @0x1234:16,@(0x9abcdef0:32,r2l.b) ;6b151234da109abcdef0 + add.w @0x1234:16,@(0x9abcdef0:32,r2.w) ;6b151234ea109abcdef0 + add.w @0x1234:16,@(0x9abcdef0:32,er2.l) ;6b151234fa109abcdef0 + add.w @0x1234:16,@0xffff9abc:16 ;6b15123440109abc + add.w @0x1234:16,@0x9abcdef0:32 ;6b15123448109abcdef0 + + add.w @0x12345678:32,@er1 ;6b35123456780110 + add.w @0x12345678:32,@(6:2,er1) ;6b35123456783110 + add.w @0x12345678:32,@-er1 ;6b3512345678b110 + add.w @0x12345678:32,@er1+ ;6b35123456788110 + add.w @0x12345678:32,@er1- ;6b3512345678a110 + add.w @0x12345678:32,@+er1 ;6b35123456789110 + add.w @0x12345678:32,@(0xffff9abc:16,er1) ;6b3512345678c1109abc + add.w @0x12345678:32,@(0x9abcdef0:32,er1) ;6b3512345678c9109abcdef0 + add.w @0x12345678:32,@(0xffff9abc:16,r2l.b) ;6b3512345678d2109abc + add.w @0x12345678:32,@(0xffff9abc:16,r2.w) ;6b3512345678e2109abc + add.w @0x12345678:32,@(0xffff9abc:16,er2.l) ;6b3512345678f2109abc + add.w @0x12345678:32,@(0x9abcdef0:32,r2l.b) ;6b3512345678da109abcdef0 + add.w @0x12345678:32,@(0x9abcdef0:32,r2.w) ;6b3512345678ea109abcdef0 + add.w @0x12345678:32,@(0x9abcdef0:32,er2.l) ;6b3512345678fa109abcdef0 + add.w @0x12345678:32,@0xffff9abc:16 ;6b351234567840109abc + add.w @0x12345678:32,@0x9abcdef0:32 ;6b351234567848109abcdef0 + + add.l #0x12345678:32,er1 ;7a1112345678 + add.l #0x1234:16,er1 ;7a191234 + add.l #0x7:3,er2 ;0afa + add.l #0x12345678:32,@er1 ;010e011812345678 + add.l #0x12345678:32,@(0xc:2,er1) ;010e311812345678 + add.l #0x12345678:32,@er1+ ;010e811812345678 + add.l #0x12345678:32,@-er1 ;010eb11812345678 + add.l #0x12345678:32,@+er1 ;010e911812345678 + add.l #0x12345678:32,@er1- ;010ea11812345678 + add.l #0x12345678:32,@(0xffff9abc:16,er1) ;010ec1189abc12345678 + add.l #0x12345678:32,@(0x9abcdef0:32,er1) ;010ec9189abcdef012345678 + add.l #0x12345678:32,@(0xffff9abc:16,r2l.b) ;010ed2189abc12345678 + add.l #0x12345678:32,@(0xffff9abc:16,r2.w) ;010ee2189abc12345678 + add.l #0x12345678:32,@(0xffff9abc:16,er2.l) ;010ef2189abc12345678 + add.l #0x12345678:32,@(0x9abcdef0:32,r2l.b) ;010eda189abcdef012345678 + add.l #0x12345678:32,@(0x9abcdef0:32,r2.w) ;010eea189abcdef012345678 + add.l #0x12345678:32,@(0x9abcdef0:32,er2.l) ;010efa189abcdef012345678 + add.l #0x12345678:32,@0xffff9abc:16 ;010e40189abc12345678 + add.l #0x12345678:32,@0x9abcdef0:32 ;010e48189abcdef012345678 + add.l #0x1234:16,@er1 ;010e01101234 + add.l #0x1234:16,@(0xc:2,er1) ;010e31101234 + add.l #0x1234:16,@er1+ ;010e81101234 + add.l #0x1234:16,@-er1 ;010eb1101234 + add.l #0x1234:16,@+er1 ;010e91101234 + add.l #0x1234:16,@er1- ;010ea1101234 + add.l #0x1234:16,@(0xffff9abc:16,er1) ;010ec1109abc1234 + add.l #0x1234:16,@(0x9abcdef0:32,er1) ;010ec9109abcdef01234 + add.l #0x1234:16,@(0xffff9abc:16,r2l.b) ;010ed2109abc1234 + add.l #0x1234:16,@(0xffff9abc:16,r2.w) ;010ee2109abc1234 + add.l #0x1234:16,@(0xffff9abc:16,er2.l) ;010ef2109abc1234 + add.l #0x1234:16,@(0x9abcdef0:32,r2l.b) ;010eda109abcdef01234 + add.l #0x1234:16,@(0x9abcdef0:32,r2.w) ;010eea109abcdef01234 + add.l #0x1234:16,@(0x9abcdef0:32,er2.l) ;010efa109abcdef01234 + add.l #0x1234:16,@0xffff9abc:16 ;010e40109abc1234 + add.l #0x1234:16,@0x9abcdef0:32 ;010e48109abcdef01234 + + add.l er3,er1 ;0ab1 + + add.l er3,@er1 ;01090113 + add.l er3,@(0xc:2,er1) ;01093113 + add.l er3,@er1+ ;01098113 + add.l er3,@-er1 ;0109b113 + add.l er3,@+er1 ;01099113 + add.l er3,@er1- ;0109a113 + add.l er3,@(0x1234:16,er1) ;0109c1131234 + add.l er3,@(0x12345678:32,er1) ;0109c91312345678 + add.l er3,@(0x1234:16,r2l.b) ;0109d2131234 + add.l er3,@(0x1234:16,r2.w) ;0109e2131234 + add.l er3,@(0x1234:16,er2.l) ;0109f2131234 + add.l er3,@(0x12345678:32,r2l.b) ;0109da1312345678 + add.l er3,@(0x12345678:32,r2.w) ;0109ea1312345678 + add.l er3,@(0x12345678:32,er2.l) ;0109fa1312345678 + add.l er3,@0x1234:16 ;010940131234 + add.l er3,@0x12345678:32 ;0109481312345678 + + add.l @er3,er1 ;010a0311 + add.l @(0xc:2,er3),er1 ;010a3311 + add.l @er3+,er1 ;010a8311 + add.l @-er3,er1 ;010ab311 + add.l @+er3,er1 ;010a9311 + add.l @er3-,er1 ;010aa311 + add.l @(0x1234:16,er1),er1 ;010ac1111234 + add.l @(0x12345678:32,er1),er1 ;010ac91112345678 + add.l @(0x1234:16,r2l.b),er1 ;010ad2111234 + add.l @(0x1234:16,r2.w),er1 ;010ae2111234 + add.l @(0x1234:16,er2.l),er1 ;010af2111234 + add.l @(0x12345678:32,r2l.b),er1 ;010ada1112345678 + add.l @(0x12345678:32,r2.w),er1 ;010aea1112345678 + add.l @(0x12345678:32,er2.l),er1 ;010afa1112345678 + add.l @0x1234:16,er1 ;010a40111234 + add.l @0x12345678:32,er1 ;010a481112345678 + + add.l @er3,@er1 ;0104693c0110 + add.l @er3,@(0xc:2,er1) ;0104693c3110 + add.l @er3,@-er1 ;0104693cb110 + add.l @er3,@er1+ ;0104693c8110 + add.l @er3,@er1- ;0104693ca110 + add.l @er3,@+er1 ;0104693c9110 + add.l @er3,@(0xffff9abc:16,er1) ;0104693cc1109abc + add.l @er3,@(0x9abcdef0:32,er1) ;0104693cc9109abcdef0 + add.l @er3,@(0xffff9abc:16,r2l.b) ;0104693cd2109abc + add.l @er3,@(0xffff9abc:16,r2.w) ;0104693ce2109abc + add.l @er3,@(0xffff9abc:16,er2.l) ;0104693cf2109abc + add.l @er3,@(0x9abcdef0:32,r2l.b) ;0104693cda109abcdef0 + add.l @er3,@(0x9abcdef0:32,r2.w) ;0104693cea109abcdef0 + add.l @er3,@(0x9abcdef0:32,er2.l) ;0104693cfa109abcdef0 + add.l @er3,@0xffff9abc:16 ;0104693c40109abc + add.l @er3,@0x9abcdef0:32 ;0104693c48109abcdef0 + + add.l @(0xc:2,er3),@er1 ;0107693c0110 + add.l @(0xc:2,er3),@(0xc:2,er1) ;0107693c3110 + add.l @(0xc:2,er3),@-er1 ;0107693cb110 + add.l @(0xc:2,er3),@er1+ ;0107693c8110 + add.l @(0xc:2,er3),@er1- ;0107693ca110 + add.l @(0xc:2,er3),@+er1 ;0107693c9110 + add.l @(0xc:2,er3),@(0xffff9abc:16,er1) ;0107693cc1109abc + add.l @(0xc:2,er3),@(0x9abcdef0:32,er1) ;0107693cc9109abcdef0 + add.l @(0xc:2,er3),@(0xffff9abc:16,r2l.b) ;0107693cd2109abc + add.l @(0xc:2,er3),@(0xffff9abc:16,r2.w) ;0107693ce2109abc + add.l @(0xc:2,er3),@(0xffff9abc:16,er2.l) ;0107693cf2109abc + add.l @(0xc:2,er3),@(0x9abcdef0:32,r2l.b) ;0107693cda109abcdef0 + add.l @(0xc:2,er3),@(0x9abcdef0:32,r2.w) ;0107693cea109abcdef0 + add.l @(0xc:2,er3),@(0x9abcdef0:32,er2.l) ;0107693cfa109abcdef0 + add.l @(0xc:2,er3),@0xffff9abc:16 ;0107693c40109abc + add.l @(0xc:2,er3),@0x9abcdef0:32 ;0107693c48109abcdef0 + + add.l @-er3,@er1 ;01076d3c0110 + add.l @-er3,@(0xc:2,er1) ;01076d3c3110 + add.l @-er3,@-er1 ;01076d3cb110 + add.l @-er3,@er1+ ;01076d3c8110 + add.l @-er3,@er1- ;01076d3ca110 + add.l @-er3,@+er1 ;01076d3c9110 + add.l @-er3,@(0xffff9abc:16,er1) ;01076d3cc1109abc + add.l @-er3,@(0x9abcdef0:32,er1) ;01076d3cc9109abcdef0 + add.l @-er3,@(0xffff9abc:16,r2l.b) ;01076d3cd2109abc + add.l @-er3,@(0xffff9abc:16,r2.w) ;01076d3ce2109abc + add.l @-er3,@(0xffff9abc:16,er2.l) ;01076d3cf2109abc + add.l @-er3,@(0x9abcdef0:32,r2l.b) ;01076d3cda109abcdef0 + add.l @-er3,@(0x9abcdef0:32,r2.w) ;01076d3cea109abcdef0 + add.l @-er3,@(0x9abcdef0:32,er2.l) ;01076d3cfa109abcdef0 + add.l @-er3,@0xffff9abc:16 ;01076d3c40109abc + add.l @-er3,@0x9abcdef0:32 ;01076d3c48109abcdef0 + + add.l @er3+,@er1 ;01046d3c0110 + add.l @er3+,@(0xc:2,er1) ;01046d3c3110 + add.l @er3+,@-er1 ;01046d3cb110 + add.l @er3+,@er1+ ;01046d3c8110 + add.l @er3+,@er1- ;01046d3ca110 + add.l @er3+,@+er1 ;01046d3c9110 + add.l @er3+,@(0xffff9abc:16,er1) ;01046d3cc1109abc + add.l @er3+,@(0x9abcdef0:32,er1) ;01046d3cc9109abcdef0 + add.l @er3+,@(0xffff9abc:16,r2l.b) ;01046d3cd2109abc + add.l @er3+,@(0xffff9abc:16,r2.w) ;01046d3ce2109abc + add.l @er3+,@(0xffff9abc:16,er2.l) ;01046d3cf2109abc + add.l @er3+,@(0x9abcdef0:32,r2l.b) ;01046d3cda109abcdef0 + add.l @er3+,@(0x9abcdef0:32,r2.w) ;01046d3cea109abcdef0 + add.l @er3+,@(0x9abcdef0:32,er2.l) ;01046d3cfa109abcdef0 + add.l @er3+,@0xffff9abc:16 ;01046d3c40109abc + add.l @er3+,@0x9abcdef0:32 ;01046d3c48109abcdef0 + + add.l @er3-,@er1 ;01066d3c0110 + add.l @er3-,@(0xc:2,er1) ;01066d3c3110 + add.l @er3-,@-er1 ;01066d3cb110 + add.l @er3-,@er1+ ;01066d3c8110 + add.l @er3-,@er1- ;01066d3ca110 + add.l @er3-,@+er1 ;01066d3c9110 + add.l @er3-,@(0xffff9abc:16,er1) ;01066d3cc1109abc + add.l @er3-,@(0x9abcdef0:32,er1) ;01066d3cc9109abcdef0 + add.l @er3-,@(0xffff9abc:16,r2l.b) ;01066d3cd2109abc + add.l @er3-,@(0xffff9abc:16,r2.w) ;01066d3ce2109abc + add.l @er3-,@(0xffff9abc:16,er2.l) ;01066d3cf2109abc + add.l @er3-,@(0x9abcdef0:32,r2l.b) ;01066d3cda109abcdef0 + add.l @er3-,@(0x9abcdef0:32,r2.w) ;01066d3cea109abcdef0 + add.l @er3-,@(0x9abcdef0:32,er2.l) ;01066d3cfa109abcdef0 + add.l @er3-,@0xffff9abc:16 ;01066d3c40109abc + add.l @er3-,@0x9abcdef0:32 ;01066d3c48109abcdef0 + + add.l @+er3,@er1 ;01056d3c0110 + add.l @+er3,@(0xc:2,er1) ;01056d3c3110 + add.l @+er3,@-er1 ;01056d3cb110 + add.l @+er3,@er1+ ;01056d3c8110 + add.l @+er3,@er1- ;01056d3ca110 + add.l @+er3,@+er1 ;01056d3c9110 + add.l @+er3,@(0xffff9abc:16,er1) ;01056d3cc1109abc + add.l @+er3,@(0x9abcdef0:32,er1) ;01056d3cc9109abcdef0 + add.l @+er3,@(0xffff9abc:16,r2l.b) ;01056d3cd2109abc + add.l @+er3,@(0xffff9abc:16,r2.w) ;01056d3ce2109abc + add.l @+er3,@(0xffff9abc:16,er2.l) ;01056d3cf2109abc + add.l @+er3,@(0x9abcdef0:32,r2l.b) ;01056d3cda109abcdef0 + add.l @+er3,@(0x9abcdef0:32,r2.w) ;01056d3cea109abcdef0 + add.l @+er3,@(0x9abcdef0:32,er2.l) ;01056d3cfa109abcdef0 + add.l @+er3,@0xffff9abc:16 ;01056d3c40109abc + add.l @+er3,@0x9abcdef0:32 ;01056d3c48109abcdef0 + + add.l @(0x1234:16,er3),@er1 ;01046f3c12340110 + add.l @(0x1234:16,er3),@(0xc:2,er1) ;01046f3c12343110 + add.l @(0x1234:16,er3),@-er1 ;01046f3c1234b110 + add.l @(0x1234:16,er3),@er1+ ;01046f3c12348110 + add.l @(0x1234:16,er3),@er1- ;01046f3c1234a110 + add.l @(0x1234:16,er3),@+er1 ;01046f3c12349110 + add.l @(0x1234:16,er3),@(0xffff9abc:16,er1) ;01046f3c1234c1109abc + add.l @(0x1234:16,er3),@(0x9abcdef0:32,er1) ;01046f3c1234c9109abcdef0 + add.l @(0x1234:16,er3),@(0xffff9abc:16,r2l.b) ;01046f3c1234d2109abc + add.l @(0x1234:16,er3),@(0xffff9abc:16,r2.w) ;01046f3c1234e2109abc + add.l @(0x1234:16,er3),@(0xffff9abc:16,er2.l) ;01046f3c1234f2109abc + add.l @(0x1234:16,er3),@(0x9abcdef0:32,r2l.b) ;01046f3c1234da109abcdef0 + add.l @(0x1234:16,er3),@(0x9abcdef0:32,r2.w) ;01046f3c1234ea109abcdef0 + add.l @(0x1234:16,er3),@(0x9abcdef0:32,er2.l) ;01046f3c1234fa109abcdef0 + add.l @(0x1234:16,er3),@0xffff9abc:16 ;01046f3c123440109abc + add.l @(0x1234:16,er3),@0x9abcdef0:32 ;01046f3c123448109abcdef0 + + add.l @(0x12345678:32,er3),@er1 ;78b46b2c123456780110 + add.l @(0x12345678:32,er3),@(0xc:2,er1) ;78b46b2c123456783110 + add.l @(0x12345678:32,er3),@-er1 ;78b46b2c12345678b110 + add.l @(0x12345678:32,er3),@er1+ ;78b46b2c123456788110 + add.l @(0x12345678:32,er3),@er1- ;78b46b2c12345678a110 + add.l @(0x12345678:32,er3),@+er1 ;78b46b2c123456789110 + add.l @(0x12345678:32,er3),@(0xffff9abc:16,er1) ;78b46b2c12345678c1109abc + add.l @(0x12345678:32,er3),@(0x9abcdef0:32,er1) ;78b46b2c12345678c9109abcdef0 + add.l @(0x12345678:32,er3),@(0xffff9abc:16,r2l.b) ;78b46b2c12345678d2109abc + add.l @(0x12345678:32,er3),@(0xffff9abc:16,r2.w) ;78b46b2c12345678e2109abc + add.l @(0x12345678:32,er3),@(0xffff9abc:16,er2.l) ;78b46b2c12345678f2109abc + add.l @(0x12345678:32,er3),@(0x9abcdef0:32,r2l.b) ;78b46b2c12345678da109abcdef0 + add.l @(0x12345678:32,er3),@(0x9abcdef0:32,r2.w) ;78b46b2c12345678ea109abcdef0 + add.l @(0x12345678:32,er3),@(0x9abcdef0:32,er2.l) ;78b46b2c12345678fa109abcdef0 + add.l @(0x12345678:32,er3),@0xffff9abc:16 ;78b46b2c1234567840109abc + add.l @(0x12345678:32,er3),@0x9abcdef0:32 ;78b46b2c1234567848109abcdef0 + + add.l @(0x1234:16,r3l.b),@er1 ;01056f3c12340110 + add.l @(0x1234:16,r3l.b),@(0xc:2,er1) ;01056f3c12343110 + add.l @(0x1234:16,r3l.b),@-er1 ;01056f3c1234b110 + add.l @(0x1234:16,r3l.b),@er1+ ;01056f3c12348110 + add.l @(0x1234:16,r3l.b),@er1- ;01056f3c1234a110 + add.l @(0x1234:16,r3l.b),@+er1 ;01056f3c12349110 + add.l @(0x1234:16,r3l.b),@(0xffff9abc:16,er1) ;01056f3c1234c1109abc + add.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1) ;01056f3c1234c9109abcdef0 + add.l @(0x1234:16,r3l.b),@(0xffff9abc:16,r2l.b) ;01056f3c1234d2109abc + add.l @(0x1234:16,r3l.b),@(0xffff9abc:16,r2.w) ;01056f3c1234e2109abc + add.l @(0x1234:16,r3l.b),@(0xffff9abc:16,er2.l) ;01056f3c1234f2109abc + add.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2l.b) ;01056f3c1234da109abcdef0 + add.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2.w) ;01056f3c1234ea109abcdef0 + add.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,er2.l) ;01056f3c1234fa109abcdef0 + add.l @(0x1234:16,r3l.b),@0xffff9abc:16 ;01056f3c123440109abc + add.l @(0x1234:16,r3l.b),@0x9abcdef0:32 ;01056f3c123448109abcdef0 + + add.l @(0x1234:16,r3.w),@er1 ;01066f3c12340110 + add.l @(0x1234:16,r3.w),@(0xc:2,er1) ;01066f3c12343110 + add.l @(0x1234:16,r3.w),@-er1 ;01066f3c1234b110 + add.l @(0x1234:16,r3.w),@er1+ ;01066f3c12348110 + add.l @(0x1234:16,r3.w),@er1- ;01066f3c1234a110 + add.l @(0x1234:16,r3.w),@+er1 ;01066f3c12349110 + add.l @(0x1234:16,r3.w),@(0xffff9abc:16,er1) ;01066f3c1234c1109abc + add.l @(0x1234:16,r3.w),@(0x9abcdef0:32,er1) ;01066f3c1234c9109abcdef0 + add.l @(0x1234:16,r3.w),@(0xffff9abc:16,r2l.b) ;01066f3c1234d2109abc + add.l @(0x1234:16,r3.w),@(0xffff9abc:16,r2.w) ;01066f3c1234e2109abc + add.l @(0x1234:16,r3.w),@(0xffff9abc:16,er2.l) ;01066f3c1234f2109abc + add.l @(0x1234:16,r3.w),@(0x9abcdef0:32,r2l.b) ;01066f3c1234da109abcdef0 + add.l @(0x1234:16,r3.w),@(0x9abcdef0:32,r2.w) ;01066f3c1234ea109abcdef0 + add.l @(0x1234:16,r3.w),@(0x9abcdef0:32,er2.l) ;01066f3c1234fa109abcdef0 + add.l @(0x1234:16,r3.w),@0xffff9abc:16 ;01066f3c123440109abc + add.l @(0x1234:16,r3.w),@0x9abcdef0:32 ;01066f3c123448109abcdef0 + + add.l @(0x1234:16,er3.l),@er1 ;01076f3c12340110 + add.l @(0x1234:16,er3.l),@(0xc:2,er1) ;01076f3c12343110 + add.l @(0x1234:16,er3.l),@-er1 ;01076f3c1234b110 + add.l @(0x1234:16,er3.l),@er1+ ;01076f3c12348110 + add.l @(0x1234:16,er3.l),@er1- ;01076f3c1234a110 + add.l @(0x1234:16,er3.l),@+er1 ;01076f3c12349110 + add.l @(0x1234:16,er3.l),@(0xffff9abc:16,er1) ;01076f3c1234c1109abc + add.l @(0x1234:16,er3.l),@(0x9abcdef0:32,er1) ;01076f3c1234c9109abcdef0 + add.l @(0x1234:16,er3.l),@(0xffff9abc:16,r2l.b) ;01076f3c1234d2109abc + add.l @(0x1234:16,er3.l),@(0xffff9abc:16,r2.w) ;01076f3c1234e2109abc + add.l @(0x1234:16,er3.l),@(0xffff9abc:16,er2.l) ;01076f3c1234f2109abc + add.l @(0x1234:16,er3.l),@(0x9abcdef0:32,r2l.b) ;01076f3c1234da109abcdef0 + add.l @(0x1234:16,er3.l),@(0x9abcdef0:32,r2.w) ;01076f3c1234ea109abcdef0 + add.l @(0x1234:16,er3.l),@(0x9abcdef0:32,er2.l) ;01076f3c1234fa109abcdef0 + add.l @(0x1234:16,er3.l),@0xffff9abc:16 ;01076f3c123440109abc + add.l @(0x1234:16,er3.l),@0x9abcdef0:32 ;01076f3c123448109abcdef0 + + add.l @(0x12345678:32,r3l.b),@er1 ;78b56b2c123456780110 + add.l @(0x12345678:32,r3l.b),@(0xc:2,er1) ;78b56b2c123456783110 + add.l @(0x12345678:32,r3l.b),@-er1 ;78b56b2c12345678b110 + add.l @(0x12345678:32,r3l.b),@er1+ ;78b56b2c123456788110 + add.l @(0x12345678:32,r3l.b),@er1- ;78b56b2c12345678a110 + add.l @(0x12345678:32,r3l.b),@+er1 ;78b56b2c123456789110 + add.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,er1) ;78b56b2c12345678c1109abc + add.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1) ;78b56b2c12345678c9109abcdef0 + add.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2l.b) ;78b56b2c12345678d2109abc + add.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2.w) ;78b56b2c12345678e2109abc + add.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,er2.l) ;78b56b2c12345678f2109abc + add.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2l.b) ;78b56b2c12345678da109abcdef0 + add.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2.w) ;78b56b2c12345678ea109abcdef0 + add.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er2.l) ;78b56b2c12345678fa109abcdef0 + add.l @(0x12345678:32,r3l.b),@0xffff9abc:16 ;78b56b2c1234567840109abc + add.l @(0x12345678:32,r3l.b),@0x9abcdef0:32 ;78b56b2c1234567848109abcdef0 + + add.l @(0x12345678:32,r3.w),@er1 ;78b66b2c123456780110 + add.l @(0x12345678:32,r3.w),@(0xc:2,er1) ;78b66b2c123456783110 + add.l @(0x12345678:32,r3.w),@-er1 ;78b66b2c12345678b110 + add.l @(0x12345678:32,r3.w),@er1+ ;78b66b2c123456788110 + add.l @(0x12345678:32,r3.w),@er1- ;78b66b2c12345678a110 + add.l @(0x12345678:32,r3.w),@+er1 ;78b66b2c123456789110 + add.l @(0x12345678:32,r3.w),@(0xffff9abc:16,er1) ;78b66b2c12345678c1109abc + add.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1) ;78b66b2c12345678c9109abcdef0 + add.l @(0x12345678:32,r3.w),@(0xffff9abc:16,r2l.b) ;78b66b2c12345678d2109abc + add.l @(0x12345678:32,r3.w),@(0xffff9abc:16,r2.w) ;78b66b2c12345678e2109abc + add.l @(0x12345678:32,r3.w),@(0xffff9abc:16,er2.l) ;78b66b2c12345678f2109abc + add.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2l.b) ;78b66b2c12345678da109abcdef0 + add.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2.w) ;78b66b2c12345678ea109abcdef0 + add.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,er2.l) ;78b66b2c12345678fa109abcdef0 + add.l @(0x12345678:32,r3.w),@0xffff9abc:16 ;78b66b2c1234567840109abc + add.l @(0x12345678:32,r3.w),@0x9abcdef0:32 ;78b66b2c1234567848109abcdef0 + + add.l @(0x12345678:32,er3.l),@er1 ;78b76b2c123456780110 + add.l @(0x12345678:32,er3.l),@(0xc:2,er1) ;78b76b2c123456783110 + add.l @(0x12345678:32,er3.l),@-er1 ;78b76b2c12345678b110 + add.l @(0x12345678:32,er3.l),@er1+ ;78b76b2c123456788110 + add.l @(0x12345678:32,er3.l),@er1- ;78b76b2c12345678a110 + add.l @(0x12345678:32,er3.l),@+er1 ;78b76b2c123456789110 + add.l @(0x12345678:32,er3.l),@(0xffff9abc:16,er1) ;78b76b2c12345678c1109abc + add.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1) ;78b76b2c12345678c9109abcdef0 + add.l @(0x12345678:32,er3.l),@(0xffff9abc:16,r2l.b) ;78b76b2c12345678d2109abc + add.l @(0x12345678:32,er3.l),@(0xffff9abc:16,r2.w) ;78b76b2c12345678e2109abc + add.l @(0x12345678:32,er3.l),@(0xffff9abc:16,er2.l) ;78b76b2c12345678f2109abc + add.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2l.b) ;78b76b2c12345678da109abcdef0 + add.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2.w) ;78b76b2c12345678ea109abcdef0 + add.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,er2.l) ;78b76b2c12345678fa109abcdef0 + add.l @(0x12345678:32,er3.l),@0xffff9abc:16 ;78b76b2c1234567840109abc + add.l @(0x12345678:32,er3.l),@0x9abcdef0:32 ;78b76b2c1234567848109abcdef0 + + add.l @0x1234:16,@er1 ;01046b0c12340110 + add.l @0x1234:16,@(0xc:2,er1) ;01046b0c12343110 + add.l @0x1234:16,@-er1 ;01046b0c1234b110 + add.l @0x1234:16,@er1+ ;01046b0c12348110 + add.l @0x1234:16,@er1- ;01046b0c1234a110 + add.l @0x1234:16,@+er1 ;01046b0c12349110 + add.l @0x1234:16,@(0xffff9abc:16,er1) ;01046b0c1234c1109abc + add.l @0x1234:16,@(0x9abcdef0:32,er1) ;01046b0c1234c9109abcdef0 + add.l @0x1234:16,@(0xffff9abc:16,r2l.b) ;01046b0c1234d2109abc + add.l @0x1234:16,@(0xffff9abc:16,r2.w) ;01046b0c1234e2109abc + add.l @0x1234:16,@(0xffff9abc:16,er2.l) ;01046b0c1234f2109abc + add.l @0x1234:16,@(0x9abcdef0:32,r2l.b) ;01046b0c1234da109abcdef0 + add.l @0x1234:16,@(0x9abcdef0:32,r2.w) ;01046b0c1234ea109abcdef0 + add.l @0x1234:16,@(0x9abcdef0:32,er2.l) ;01046b0c1234fa109abcdef0 + add.l @0x1234:16,@0xffff9abc:16 ;01046b0c123440109abc + add.l @0x1234:16,@0x9abcdef0:32 ;01046b0c123448109abcdef0 + + add.l @0x12345678:32,@er1 ;01046b2c123456780110 + add.l @0x12345678:32,@(0xc:2,er1) ;01046b2c123456783110 + add.l @0x12345678:32,@-er1 ;01046b2c12345678b110 + add.l @0x12345678:32,@er1+ ;01046b2c123456788110 + add.l @0x12345678:32,@er1- ;01046b2c12345678a110 + add.l @0x12345678:32,@+er1 ;01046b2c123456789110 + add.l @0x12345678:32,@(0xffff9abc:16,er1) ;01046b2c12345678c1109abc + add.l @0x12345678:32,@(0x9abcdef0:32,er1) ;01046b2c12345678c9109abcdef0 + add.l @0x12345678:32,@(0xffff9abc:16,r2l.b) ;01046b2c12345678d2109abc + add.l @0x12345678:32,@(0xffff9abc:16,r2.w) ;01046b2c12345678e2109abc + add.l @0x12345678:32,@(0xffff9abc:16,er2.l) ;01046b2c12345678f2109abc + add.l @0x12345678:32,@(0x9abcdef0:32,r2l.b) ;01046b2c12345678da109abcdef0 + add.l @0x12345678:32,@(0x9abcdef0:32,r2.w) ;01046b2c12345678ea109abcdef0 + add.l @0x12345678:32,@(0x9abcdef0:32,er2.l) ;01046b2c12345678fa109abcdef0 + add.l @0x12345678:32,@0xffff9abc:16 ;01046b2c1234567840109abc + add.l @0x12345678:32,@0x9abcdef0:32 ;01046b2c1234567848109abcdef0 + + .end diff --git a/gdb/testsuite/gdb.disasm/t04_sub.exp b/gdb/testsuite/gdb.disasm/t04_sub.exp new file mode 100644 index 0000000..e3a5213 --- /dev/null +++ b/gdb/testsuite/gdb.disasm/t04_sub.exp @@ -0,0 +1,1874 @@ +# Copyright (C) 2003 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# Please email any bugs, comments, and/or additions to this file to: +# bug-gdb@prep.ai.mit.edu + +# This file was written by Michael Snyder (msnyder@redhat.com) + +if $tracelevel then { + strace $tracelevel +} + +if ![istarget "h8300*-*-*"] { + verbose "Tests ignored for all but h8300s based targets." + return +} + +set prms_id 0 +set bug_id 0 + +set testfile "t04_sub" +set srcfile ${srcdir}/${subdir}/${testfile}.s +set objfile ${objdir}/${subdir}/${testfile}.o +set binfile ${objdir}/${subdir}/${testfile}.x + +set asm-flags ""; +set link-flags "-m h8300sxelf"; + + +if {[target_assemble $srcfile $objfile "${asm-flags}"] != ""} then { + gdb_suppress_entire_file "Testcase assembly failed, so all tests in this file will automatically fail." +} + +if {[target_link $objfile $binfile "${link-flags}"] != ""} then { + gdb_suppress_entire_file "Testcase link failed, so all tests in this file will automatically fail." +} + +gdb_start +gdb_reinitialize_dir $srcdir/$subdir +gdb_load $binfile + +gdb_test "x /i _start" "sub.b\t#0x12(:8|),@er1" \ + "sub.b #0x12:8,@er1" +gdb_test "x" "sub.b\t#0x12(:8|),@\\(0x3(:2|),er1\\)" \ + "sub.b #0x12:8,@(0x3:2,er1)" +gdb_test "x" "sub.b\t#0x12(:8|),@er1\\+" \ + "sub.b #0x12:8,@er1+" +gdb_test "x" "sub.b\t#0x12(:8|),@-er1" \ + "sub.b #0x12:8,@-er1" +gdb_test "x" "sub.b\t#0x12(:8|),@\\+er1" \ + "sub.b #0x12:8,@+er1" +gdb_test "x" "sub.b\t#0x12(:8|),@er1-" \ + "sub.b #0x12:8,@er1-" +gdb_test "x" "sub.b\t#0x12(:8|),@\\(0x1234(:16|),er1\\)" \ + "sub.b #0x12:8,@(0x1234:16,er1)" +gdb_test "x" "sub.b\t#0x12(:8|),@\\(0x12345678(:32|),er1\\)" \ + "sub.b #0x12:8,@(0x12345678:32,er1)" +gdb_test "x" "sub.b\t#0x12(:8|),@\\(0x1234(:16|),r2l.b\\)" \ + "sub.b #0x12:8,@(0x1234:16,r2l.b)" +gdb_test "x" "sub.b\t#0x12(:8|),@\\(0x1234(:16|),r2.w\\)" \ + "sub.b #0x12:8,@(0x1234:16,r2.w)" +gdb_test "x" "sub.b\t#0x12(:8|),@\\(0x1234(:16|),er2.l\\)" \ + "sub.b #0x12:8,@(0x1234:16,er2.l)" +gdb_test "x" "sub.b\t#0x12(:8|),@\\(0x12345678(:32|),r2l.b\\)" \ + "sub.b #0x12:8,@(0x12345678:32,r2l.b)" +gdb_test "x" "sub.b\t#0x12(:8|),@\\(0x12345678(:32|),r2.w\\)" \ + "sub.b #0x12:8,@(0x12345678:32,r2.w)" +gdb_test "x" "sub.b\t#0x12(:8|),@\\(0x12345678(:32|),er2.l\\)" \ + "sub.b #0x12:8,@(0x12345678:32,er2.l)" +gdb_test "x" "sub.b\t#0x12(:8|),@0x9a(:8|)" \ + "sub.b #0x12:8,@0x9a:8" +gdb_test "x" "sub.b\t#0x12(:8|),@0x1234(:16|)" \ + "sub.b #0x12:8,@0x1234:16" +gdb_test "x" "sub.b\t#0x12(:8|),@0x12345678(:32|)" \ + "sub.b #0x12:8,@0x12345678:32" +gdb_test "x" "sub.b\tr3h,r1h" \ + "sub.b r3h,r1h" +gdb_test "x" "sub.b\tr3h,@er1" \ + "sub.b r3h,@er1" +gdb_test "x" "sub.b\tr3h,@\\(0x3(:2|),er1\\)" \ + "sub.b r3h,@(0x3:2,er1)" +gdb_test "x" "sub.b\tr3h,@er1\\+" \ + "sub.b r3h,@er1+" +gdb_test "x" "sub.b\tr3h,@-er1" \ + "sub.b r3h,@-er1" +gdb_test "x" "sub.b\tr3h,@\\+er1" \ + "sub.b r3h,@+er1" +gdb_test "x" "sub.b\tr3h,@er1-" \ + "sub.b r3h,@er1-" +gdb_test "x" "sub.b\tr3h,@\\(0x1234(:16|),er1\\)" \ + "sub.b r3h,@(0x1234:16,er1)" +gdb_test "x" "sub.b\tr3h,@\\(0x12345678(:32|),er1\\)" \ + "sub.b r3h,@(0x12345678:32,er1)" +gdb_test "x" "sub.b\tr3h,@\\(0x1234(:16|),r2l.b\\)" \ + "sub.b r3h,@(0x1234:16,r2l.b)" +gdb_test "x" "sub.b\tr3h,@\\(0x1234(:16|),r2.w\\)" \ + "sub.b r3h,@(0x1234:16,r2.w)" +gdb_test "x" "sub.b\tr3h,@\\(0x1234(:16|),er2.l\\)" \ + "sub.b r3h,@(0x1234:16,er2.l)" +gdb_test "x" "sub.b\tr3h,@\\(0x12345678(:32|),r2l.b\\)" \ + "sub.b r3h,@(0x12345678:32,r2l.b)" +gdb_test "x" "sub.b\tr3h,@\\(0x12345678(:32|),r2.w\\)" \ + "sub.b r3h,@(0x12345678:32,r2.w)" +gdb_test "x" "sub.b\tr3h,@\\(0x12345678(:32|),er2.l\\)" \ + "sub.b r3h,@(0x12345678:32,er2.l)" +gdb_test "x" "sub.b\tr3h,@0x12(:8|)" \ + "sub.b r3h,@0x12:8" +gdb_test "x" "sub.b\tr3h,@0x1234(:16|)" \ + "sub.b r3h,@0x1234:16" +gdb_test "x" "sub.b\tr3h,@0x12345678(:32|)" \ + "sub.b r3h,@0x12345678:32" +gdb_test "x" "sub.b\t@er3,r1h" \ + "sub.b @er3,r1h" +gdb_test "x" "sub.b\t@\\(0x3(:2|),er3\\),r1h" \ + "sub.b @(0x3:2,er3),r1h" +gdb_test "x" "sub.b\t@er3\\+,r1h" \ + "sub.b @er3+,r1h" +gdb_test "x" "sub.b\t@-er3,r1h" \ + "sub.b @-er3,r1h" +gdb_test "x" "sub.b\t@\\+er3,r1h" \ + "sub.b @+er3,r1h" +gdb_test "x" "sub.b\t@er3-,r1h" \ + "sub.b @er3-,r1h" +gdb_test "x" "sub.b\t@\\(0x1234(:16|),er1\\),r1h" \ + "sub.b @(0x1234:16,er1),r1h" +gdb_test "x" "sub.b\t@\\(0x12345678(:32|),er1\\),r1h" \ + "sub.b @(0x12345678:32,er1),r1h" +gdb_test "x" "sub.b\t@\\(0x1234(:16|),r2l.b\\),r1h" \ + "sub.b @(0x1234:16,r2l.b),r1h" +gdb_test "x" "sub.b\t@\\(0x1234(:16|),r2.w\\),r1h" \ + "sub.b @(0x1234:16,r2.w),r1h" +gdb_test "x" "sub.b\t@\\(0x1234(:16|),er2.l\\),r1h" \ + "sub.b @(0x1234:16,er2.l),r1h" +gdb_test "x" "sub.b\t@\\(0x12345678(:32|),r2l.b\\),r1h" \ + "sub.b @(0x12345678:32,r2l.b),r1h" +gdb_test "x" "sub.b\t@\\(0x12345678(:32|),r2.w\\),r1h" \ + "sub.b @(0x12345678:32,r2.w),r1h" +gdb_test "x" "sub.b\t@\\(0x12345678(:32|),er2.l\\),r1h" \ + "sub.b @(0x12345678:32,er2.l),r1h" +gdb_test "x" "sub.b\t@0x12(:8|),r1h" \ + "sub.b @0x12:8,r1h" +gdb_test "x" "sub.b\t@0x1234(:16|),r1h" \ + "sub.b @0x1234:16,r1h" +gdb_test "x" "sub.b\t@0x12345678(:32|),r1h" \ + "sub.b @0x12345678:32,r1h" +gdb_test "x" "sub.b\t@er3,@er1" \ + "sub.b @er3,@er1" +gdb_test "x" "sub.b\t@er3,@\\(0x3(:2|),er1\\)" \ + "sub.b @er3,@(0x3:2,er1)" +gdb_test "x" "sub.b\t@er3,@-er1" \ + "sub.b @er3,@-er1" +gdb_test "x" "sub.b\t@er3,@er1\\+" \ + "sub.b @er3,@er1+" +gdb_test "x" "sub.b\t@er3,@er1-" \ + "sub.b @er3,@er1-" +gdb_test "x" "sub.b\t@er3,@\\+er1" \ + "sub.b @er3,@+er1" +gdb_test "x" "sub.b\t@er3,@\\(0x9abc(:16|),er1\\)" \ + "sub.b @er3,@(0x9abc:16,er1)" +gdb_test "x" "sub.b\t@er3,@\\(0x9abcdef0(:32|),er1\\)" \ + "sub.b @er3,@(0x9abcdef0:32,er1)" +gdb_test "x" "sub.b\t@er3,@\\(0x9abc(:16|),r2l.b\\)" \ + "sub.b @er3,@(0x9abc:16,r2l.b)" +gdb_test "x" "sub.b\t@er3,@\\(0x9abc(:16|),r2.w\\)" \ + "sub.b @er3,@(0x9abc:16,r2.w)" +gdb_test "x" "sub.b\t@er3,@\\(0x9abc(:16|),er2.l\\)" \ + "sub.b @er3,@(0x9abc:16,er2.l)" +gdb_test "x" "sub.b\t@er3,@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "sub.b @er3,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "sub.b\t@er3,@\\(0x9abcdef0(:32|),r2.w\\)" \ + "sub.b @er3,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "sub.b\t@er3,@\\(0x9abcdef0(:32|),er2.l\\)" \ + "sub.b @er3,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "sub.b\t@er3,@0x9abc(:16|)" \ + "sub.b @er3,@0x9abc:16" +gdb_test "x" "sub.b\t@er3,@0x9abcdef0(:32|)" \ + "sub.b @er3,@0x9abcdef0:32" +gdb_test "x" "sub.b\t@-er3,@er1" \ + "sub.b @-er3,@er1" +gdb_test "x" "sub.b\t@-er3,@\\(0x3(:2|),er1\\)" \ + "sub.b @-er3,@(0x3:2,er1)" +gdb_test "x" "sub.b\t@-er3,@-er1" \ + "sub.b @-er3,@-er1" +gdb_test "x" "sub.b\t@-er3,@er1\\+" \ + "sub.b @-er3,@er1+" +gdb_test "x" "sub.b\t@-er3,@er1-" \ + "sub.b @-er3,@er1-" +gdb_test "x" "sub.b\t@-er3,@\\+er1" \ + "sub.b @-er3,@+er1" +gdb_test "x" "sub.b\t@-er3,@\\(0x9abc(:16|),er1\\)" \ + "sub.b @-er3,@(0x9abc:16,er1)" +gdb_test "x" "sub.b\t@-er3,@\\(0x9abcdef0(:32|),er1\\)" \ + "sub.b @-er3,@(0x9abcdef0:32,er1)" +gdb_test "x" "sub.b\t@-er3,@\\(0x9abc(:16|),r2l.b\\)" \ + "sub.b @-er3,@(0x9abc:16,r2l.b)" +gdb_test "x" "sub.b\t@-er3,@\\(0x9abc(:16|),r2.w\\)" \ + "sub.b @-er3,@(0x9abc:16,r2.w)" +gdb_test "x" "sub.b\t@-er3,@\\(0x9abc(:16|),er2.l\\)" \ + "sub.b @-er3,@(0x9abc:16,er2.l)" +gdb_test "x" "sub.b\t@-er3,@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "sub.b @-er3,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "sub.b\t@-er3,@\\(0x9abcdef0(:32|),r2.w\\)" \ + "sub.b @-er3,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "sub.b\t@-er3,@\\(0x9abcdef0(:32|),er2.l\\)" \ + "sub.b @-er3,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "sub.b\t@-er3,@0x9abc(:16|)" \ + "sub.b @-er3,@0x9abc:16" +gdb_test "x" "sub.b\t@-er3,@0x9abcdef0(:32|)" \ + "sub.b @-er3,@0x9abcdef0:32" +gdb_test "x" "sub.b\t@er3\\+,@er1" \ + "sub.b @er3+,@er1" +gdb_test "x" "sub.b\t@er3\\+,@\\(0x3(:2|),er1\\)" \ + "sub.b @er3+,@(0x3:2,er1)" +gdb_test "x" "sub.b\t@er3\\+,@-er1" \ + "sub.b @er3+,@-er1" +gdb_test "x" "sub.b\t@er3\\+,@er1\\+" \ + "sub.b @er3+,@er1+" +gdb_test "x" "sub.b\t@er3\\+,@er1-" \ + "sub.b @er3+,@er1-" +gdb_test "x" "sub.b\t@er3\\+,@\\+er1" \ + "sub.b @er3+,@+er1" +gdb_test "x" "sub.b\t@er3\\+,@\\(0x9abc(:16|),er1\\)" \ + "sub.b @er3+,@(0x9abc:16,er1)" +gdb_test "x" "sub.b\t@er3\\+,@\\(0x9abcdef0(:32|),er1\\)" \ + "sub.b @er3+,@(0x9abcdef0:32,er1)" +gdb_test "x" "sub.b\t@er3\\+,@\\(0x9abc(:16|),r2l.b\\)" \ + "sub.b @er3+,@(0x9abc:16,r2l.b)" +gdb_test "x" "sub.b\t@er3\\+,@\\(0x9abc(:16|),r2.w\\)" \ + "sub.b @er3+,@(0x9abc:16,r2.w)" +gdb_test "x" "sub.b\t@er3\\+,@\\(0x9abc(:16|),er2.l\\)" \ + "sub.b @er3+,@(0x9abc:16,er2.l)" +gdb_test "x" "sub.b\t@er3\\+,@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "sub.b @er3+,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "sub.b\t@er3\\+,@\\(0x9abcdef0(:32|),r2.w\\)" \ + "sub.b @er3+,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "sub.b\t@er3\\+,@\\(0x9abcdef0(:32|),er2.l\\)" \ + "sub.b @er3+,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "sub.b\t@er3\\+,@0x9abc(:16|)" \ + "sub.b @er3+,@0x9abc:16" +gdb_test "x" "sub.b\t@er3\\+,@0x9abcdef0(:32|)" \ + "sub.b @er3+,@0x9abcdef0:32" +gdb_test "x" "sub.b\t@er3-,@er1" \ + "sub.b @er3-,@er1" +gdb_test "x" "sub.b\t@er3-,@\\(0x3(:2|),er1\\)" \ + "sub.b @er3-,@(0x3:2,er1)" +gdb_test "x" "sub.b\t@er3-,@-er1" \ + "sub.b @er3-,@-er1" +gdb_test "x" "sub.b\t@er3-,@er1\\+" \ + "sub.b @er3-,@er1+" +gdb_test "x" "sub.b\t@er3-,@er1-" \ + "sub.b @er3-,@er1-" +gdb_test "x" "sub.b\t@er3-,@\\+er1" \ + "sub.b @er3-,@+er1" +gdb_test "x" "sub.b\t@er3-,@\\(0x9abc(:16|),er1\\)" \ + "sub.b @er3-,@(0x9abc:16,er1)" +gdb_test "x" "sub.b\t@er3-,@\\(0x9abcdef0(:32|),er1\\)" \ + "sub.b @er3-,@(0x9abcdef0:32,er1)" +gdb_test "x" "sub.b\t@er3-,@\\(0x9abc(:16|),r2l.b\\)" \ + "sub.b @er3-,@(0x9abc:16,r2l.b)" +gdb_test "x" "sub.b\t@er3-,@\\(0x9abc(:16|),r2.w\\)" \ + "sub.b @er3-,@(0x9abc:16,r2.w)" +gdb_test "x" "sub.b\t@er3-,@\\(0x9abc(:16|),er2.l\\)" \ + "sub.b @er3-,@(0x9abc:16,er2.l)" +gdb_test "x" "sub.b\t@er3-,@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "sub.b @er3-,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "sub.b\t@er3-,@\\(0x9abcdef0(:32|),r2.w\\)" \ + "sub.b @er3-,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "sub.b\t@er3-,@\\(0x9abcdef0(:32|),er2.l\\)" \ + "sub.b @er3-,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "sub.b\t@er3-,@0x9abc(:16|)" \ + "sub.b @er3-,@0x9abc:16" +gdb_test "x" "sub.b\t@er3-,@0x9abcdef0(:32|)" \ + "sub.b @er3-,@0x9abcdef0:32" +gdb_test "x" "sub.b\t@\\+er3,@er1" \ + "sub.b @+er3,@er1" +gdb_test "x" "sub.b\t@\\+er3,@\\(0x3(:2|),er1\\)" \ + "sub.b @+er3,@(0x3:2,er1)" +gdb_test "x" "sub.b\t@\\+er3,@-er1" \ + "sub.b @+er3,@-er1" +gdb_test "x" "sub.b\t@\\+er3,@er1\\+" \ + "sub.b @+er3,@er1+" +gdb_test "x" "sub.b\t@\\+er3,@er1-" \ + "sub.b @+er3,@er1-" +gdb_test "x" "sub.b\t@\\+er3,@\\+er1" \ + "sub.b @+er3,@+er1" +gdb_test "x" "sub.b\t@\\+er3,@\\(0x9abc(:16|),er1\\)" \ + "sub.b @+er3,@(0x9abc:16,er1)" +gdb_test "x" "sub.b\t@\\+er3,@\\(0x9abcdef0(:32|),er1\\)" \ + "sub.b @+er3,@(0x9abcdef0:32,er1)" +gdb_test "x" "sub.b\t@\\+er3,@\\(0x9abc(:16|),r2l.b\\)" \ + "sub.b @+er3,@(0x9abc:16,r2l.b)" +gdb_test "x" "sub.b\t@\\+er3,@\\(0x9abc(:16|),r2.w\\)" \ + "sub.b @+er3,@(0x9abc:16,r2.w)" +gdb_test "x" "sub.b\t@\\+er3,@\\(0x9abc(:16|),er2.l\\)" \ + "sub.b @+er3,@(0x9abc:16,er2.l)" +gdb_test "x" "sub.b\t@\\+er3,@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "sub.b @+er3,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "sub.b\t@\\+er3,@\\(0x9abcdef0(:32|),r2.w\\)" \ + "sub.b @+er3,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "sub.b\t@\\+er3,@\\(0x9abcdef0(:32|),er2.l\\)" \ + "sub.b @+er3,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "sub.b\t@\\+er3,@0x9abc(:16|)" \ + "sub.b @+er3,@0x9abc:16" +gdb_test "x" "sub.b\t@\\+er3,@0x9abcdef0(:32|)" \ + "sub.b @+er3,@0x9abcdef0:32" +gdb_test "x" "sub.b\t@\\(0x1234(:16|),er3\\),@er1" \ + "sub.b @(0x1234:16,er3),@er1" +gdb_test "x" "sub.b\t@\\(0x1234(:16|),er3\\),@\\(0x3(:2|),er1\\)" \ + "sub.b @(0x1234:16,er3),@(0x3:2,er1)" +gdb_test "x" "sub.b\t@\\(0x1234(:16|),er3\\),@-er1" \ + "sub.b @(0x1234:16,er3),@-er1" +gdb_test "x" "sub.b\t@\\(0x1234(:16|),er3\\),@er1\\+" \ + "sub.b @(0x1234:16,er3),@er1+" +gdb_test "x" "sub.b\t@\\(0x1234(:16|),er3\\),@er1-" \ + "sub.b @(0x1234:16,er3),@er1-" +gdb_test "x" "sub.b\t@\\(0x1234(:16|),er3\\),@\\+er1" \ + "sub.b @(0x1234:16,er3),@+er1" +gdb_test "x" "sub.b\t@\\(0x1234(:16|),er3\\),@\\(0x9abc(:16|),er1\\)" \ + "sub.b @(0x1234:16,er3),@(0x9abc:16,er1)" +gdb_test "x" "sub.b\t@\\(0x1234(:16|),er3\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "sub.b @(0x1234:16,er3),@(0x9abcdef0:32,er1)" +gdb_test "x" "sub.b\t@\\(0x1234(:16|),er3\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "sub.b @(0x1234:16,er3),@(0x9abc:16,r2l.b)" +gdb_test "x" "sub.b\t@\\(0x1234(:16|),er3\\),@\\(0x9abc(:16|),r2.w\\)" \ + "sub.b @(0x1234:16,er3),@(0x9abc:16,r2.w)" +gdb_test "x" "sub.b\t@\\(0x1234(:16|),er3\\),@\\(0x9abc(:16|),er2.l\\)" \ + "sub.b @(0x1234:16,er3),@(0x9abc:16,er2.l)" +gdb_test "x" "sub.b\t@\\(0x1234(:16|),er3\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "sub.b @(0x1234:16,er3),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "sub.b\t@\\(0x1234(:16|),er3\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "sub.b @(0x1234:16,er3),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "sub.b\t@\\(0x1234(:16|),er3\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "sub.b @(0x1234:16,er3),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "sub.b\t@\\(0x1234(:16|),er3\\),@0x9abc(:16|)" \ + "sub.b @(0x1234:16,er3),@0x9abc:16" +gdb_test "x" "sub.b\t@\\(0x1234(:16|),er3\\),@0x9abcdef0(:32|)" \ + "sub.b @(0x1234:16,er3),@0x9abcdef0:32" +gdb_test "x" "sub.b\t@\\(0x12345678(:32|),er3\\),@er1" \ + "sub.b @(0x12345678:32,er3),@er1" +gdb_test "x" "sub.b\t@\\(0x12345678(:32|),er3\\),@\\(0x3(:2|),er1\\)" \ + "sub.b @(0x12345678:32,er3),@(0x3:2,er1)" +gdb_test "x" "sub.b\t@\\(0x12345678(:32|),er3\\),@-er1" \ + "sub.b @(0x12345678:32,er3),@-er1" +gdb_test "x" "sub.b\t@\\(0x12345678(:32|),er3\\),@er1\\+" \ + "sub.b @(0x12345678:32,er3),@er1+" +gdb_test "x" "sub.b\t@\\(0x12345678(:32|),er3\\),@er1-" \ + "sub.b @(0x12345678:32,er3),@er1-" +gdb_test "x" "sub.b\t@\\(0x12345678(:32|),er3\\),@\\+er1" \ + "sub.b @(0x12345678:32,er3),@+er1" +gdb_test "x" "sub.b\t@\\(0x12345678(:32|),er3\\),@\\(0x9abc(:16|),er1\\)" \ + "sub.b @(0x12345678:32,er3),@(0x9abc:16,er1)" +gdb_test "x" "sub.b\t@\\(0x12345678(:32|),er3\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "sub.b @(0x12345678:32,er3),@(0x9abcdef0:32,er1)" +gdb_test "x" "sub.b\t@\\(0x12345678(:32|),er3\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "sub.b @(0x12345678:32,er3),@(0x9abc:16,r2l.b)" +gdb_test "x" "sub.b\t@\\(0x12345678(:32|),er3\\),@\\(0x9abc(:16|),r2.w\\)" \ + "sub.b @(0x12345678:32,er3),@(0x9abc:16,r2.w)" +gdb_test "x" "sub.b\t@\\(0x12345678(:32|),er3\\),@\\(0x9abc(:16|),er2.l\\)" \ + "sub.b @(0x12345678:32,er3),@(0x9abc:16,er2.l)" +gdb_test "x" "sub.b\t@\\(0x12345678(:32|),er3\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "sub.b @(0x12345678:32,er3),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "sub.b\t@\\(0x12345678(:32|),er3\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "sub.b @(0x12345678:32,er3),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "sub.b\t@\\(0x12345678(:32|),er3\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "sub.b @(0x12345678:32,er3),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "sub.b\t@\\(0x12345678(:32|),er3\\),@0x9abc(:16|)" \ + "sub.b @(0x12345678:32,er3),@0x9abc:16" +gdb_test "x" "sub.b\t@\\(0x12345678(:32|),er3\\),@0x9abcdef0(:32|)" \ + "sub.b @(0x12345678:32,er3),@0x9abcdef0:32" +gdb_test "x" "sub.b\t@\\(0x1234(:16|),r3l.b\\),@er1" \ + "sub.b @(0x1234:16,r3l.b),@er1" +gdb_test "x" "sub.b\t@\\(0x1234(:16|),r3l.b\\),@\\(0x3(:2|),er1\\)" \ + "sub.b @(0x1234:16,r3l.b),@(0x3:2,er1)" +gdb_test "x" "sub.b\t@\\(0x1234(:16|),r3l.b\\),@-er1" \ + "sub.b @(0x1234:16,r3l.b),@-er1" +gdb_test "x" "sub.b\t@\\(0x1234(:16|),r3l.b\\),@er1\\+" \ + "sub.b @(0x1234:16,r3l.b),@er1+" +gdb_test "x" "sub.b\t@\\(0x1234(:16|),r3l.b\\),@er1-" \ + "sub.b @(0x1234:16,r3l.b),@er1-" +gdb_test "x" "sub.b\t@\\(0x1234(:16|),r3l.b\\),@\\+er1" \ + "sub.b @(0x1234:16,r3l.b),@+er1" +gdb_test "x" "sub.b\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abc(:16|),er1\\)" \ + "sub.b @(0x1234:16,r3l.b),@(0x9abc:16,er1)" +gdb_test "x" "sub.b\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "sub.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1)" +gdb_test "x" "sub.b\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "sub.b @(0x1234:16,r3l.b),@(0x9abc:16,r2l.b)" +gdb_test "x" "sub.b\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abc(:16|),r2.w\\)" \ + "sub.b @(0x1234:16,r3l.b),@(0x9abc:16,r2.w)" +gdb_test "x" "sub.b\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abc(:16|),er2.l\\)" \ + "sub.b @(0x1234:16,r3l.b),@(0x9abc:16,er2.l)" +gdb_test "x" "sub.b\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "sub.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "sub.b\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "sub.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "sub.b\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "sub.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "sub.b\t@\\(0x1234(:16|),r3l.b\\),@0x9abc(:16|)" \ + "sub.b @(0x1234:16,r3l.b),@0x9abc:16" +gdb_test "x" "sub.b\t@\\(0x1234(:16|),r3l.b\\),@0x9abcdef0(:32|)" \ + "sub.b @(0x1234:16,r3l.b),@0x9abcdef0:32" +gdb_test "x" "sub.b\t@\\(0x1234(:16|),r3.w\\),@er1" \ + "sub.b @(0x1234:16,r3.w),@er1" +gdb_test "x" "sub.b\t@\\(0x1234(:16|),r3.w\\),@\\(0x3(:2|),er1\\)" \ + "sub.b @(0x1234:16,r3.w),@(0x3:2,er1)" +gdb_test "x" "sub.b\t@\\(0x1234(:16|),r3.w\\),@-er1" \ + "sub.b @(0x1234:16,r3.w),@-er1" +gdb_test "x" "sub.b\t@\\(0x1234(:16|),r3.w\\),@er1\\+" \ + "sub.b @(0x1234:16,r3.w),@er1+" +gdb_test "x" "sub.b\t@\\(0x1234(:16|),r3.w\\),@er1-" \ + "sub.b @(0x1234:16,r3.w),@er1-" +gdb_test "x" "sub.b\t@\\(0x1234(:16|),r3.w\\),@\\+er1" \ + "sub.b @(0x1234:16,r3.w),@+er1" +gdb_test "x" "sub.b\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abc(:16|),er1\\)" \ + "sub.b @(0x1234:16,r3.w),@(0x9abc:16,er1)" +gdb_test "x" "sub.b\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "sub.b @(0x1234:16,r3.w),@(0x9abcdef0:32,er1)" +gdb_test "x" "sub.b\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "sub.b @(0x1234:16,r3.w),@(0x9abc:16,r2l.b)" +gdb_test "x" "sub.b\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abc(:16|),r2.w\\)" \ + "sub.b @(0x1234:16,r3.w),@(0x9abc:16,r2.w)" +gdb_test "x" "sub.b\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abc(:16|),er2.l\\)" \ + "sub.b @(0x1234:16,r3.w),@(0x9abc:16,er2.l)" +gdb_test "x" "sub.b\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "sub.b @(0x1234:16,r3.w),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "sub.b\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "sub.b @(0x1234:16,r3.w),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "sub.b\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "sub.b @(0x1234:16,r3.w),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "sub.b\t@\\(0x1234(:16|),r3.w\\),@0x9abc(:16|)" \ + "sub.b @(0x1234:16,r3.w),@0x9abc:16" +gdb_test "x" "sub.b\t@\\(0x1234(:16|),r3.w\\),@0x9abcdef0(:32|)" \ + "sub.b @(0x1234:16,r3.w),@0x9abcdef0:32" +gdb_test "x" "sub.b\t@\\(0x1234(:16|),er3.l\\),@er1" \ + "sub.b @(0x1234:16,er3.l),@er1" +gdb_test "x" "sub.b\t@\\(0x1234(:16|),er3.l\\),@\\(0x3(:2|),er1\\)" \ + "sub.b @(0x1234:16,er3.l),@(0x3:2,er1)" +gdb_test "x" "sub.b\t@\\(0x1234(:16|),er3.l\\),@-er1" \ + "sub.b @(0x1234:16,er3.l),@-er1" +gdb_test "x" "sub.b\t@\\(0x1234(:16|),er3.l\\),@er1\\+" \ + "sub.b @(0x1234:16,er3.l),@er1+" +gdb_test "x" "sub.b\t@\\(0x1234(:16|),er3.l\\),@er1-" \ + "sub.b @(0x1234:16,er3.l),@er1-" +gdb_test "x" "sub.b\t@\\(0x1234(:16|),er3.l\\),@\\+er1" \ + "sub.b @(0x1234:16,er3.l),@+er1" +gdb_test "x" "sub.b\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abc(:16|),er1\\)" \ + "sub.b @(0x1234:16,er3.l),@(0x9abc:16,er1)" +gdb_test "x" "sub.b\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "sub.b @(0x1234:16,er3.l),@(0x9abcdef0:32,er1)" +gdb_test "x" "sub.b\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "sub.b @(0x1234:16,er3.l),@(0x9abc:16,r2l.b)" +gdb_test "x" "sub.b\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abc(:16|),r2.w\\)" \ + "sub.b @(0x1234:16,er3.l),@(0x9abc:16,r2.w)" +gdb_test "x" "sub.b\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abc(:16|),er2.l\\)" \ + "sub.b @(0x1234:16,er3.l),@(0x9abc:16,er2.l)" +gdb_test "x" "sub.b\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "sub.b @(0x1234:16,er3.l),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "sub.b\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "sub.b @(0x1234:16,er3.l),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "sub.b\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "sub.b @(0x1234:16,er3.l),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "sub.b\t@\\(0x1234(:16|),er3.l\\),@0x9abc(:16|)" \ + "sub.b @(0x1234:16,er3.l),@0x9abc:16" +gdb_test "x" "sub.b\t@\\(0x1234(:16|),er3.l\\),@0x9abcdef0(:32|)" \ + "sub.b @(0x1234:16,er3.l),@0x9abcdef0:32" +gdb_test "x" "sub.b\t@\\(0x12345678(:32|),r3l.b\\),@er1" \ + "sub.b @(0x12345678:32,r3l.b),@er1" +gdb_test "x" "sub.b\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x3(:2|),er1\\)" \ + "sub.b @(0x12345678:32,r3l.b),@(0x3:2,er1)" +gdb_test "x" "sub.b\t@\\(0x12345678(:32|),r3l.b\\),@-er1" \ + "sub.b @(0x12345678:32,r3l.b),@-er1" +gdb_test "x" "sub.b\t@\\(0x12345678(:32|),r3l.b\\),@er1\\+" \ + "sub.b @(0x12345678:32,r3l.b),@er1+" +gdb_test "x" "sub.b\t@\\(0x12345678(:32|),r3l.b\\),@er1-" \ + "sub.b @(0x12345678:32,r3l.b),@er1-" +gdb_test "x" "sub.b\t@\\(0x12345678(:32|),r3l.b\\),@\\+er1" \ + "sub.b @(0x12345678:32,r3l.b),@+er1" +gdb_test "x" "sub.b\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abc(:16|),er1\\)" \ + "sub.b @(0x12345678:32,r3l.b),@(0x9abc:16,er1)" +gdb_test "x" "sub.b\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "sub.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1)" +gdb_test "x" "sub.b\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "sub.b @(0x12345678:32,r3l.b),@(0x9abc:16,r2l.b)" +gdb_test "x" "sub.b\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abc(:16|),r2.w\\)" \ + "sub.b @(0x12345678:32,r3l.b),@(0x9abc:16,r2.w)" +gdb_test "x" "sub.b\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abc(:16|),er2.l\\)" \ + "sub.b @(0x12345678:32,r3l.b),@(0x9abc:16,er2.l)" +gdb_test "x" "sub.b\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "sub.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "sub.b\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "sub.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "sub.b\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "sub.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "sub.b\t@\\(0x12345678(:32|),r3l.b\\),@0x9abc(:16|)" \ + "sub.b @(0x12345678:32,r3l.b),@0x9abc:16" +gdb_test "x" "sub.b\t@\\(0x12345678(:32|),r3l.b\\),@0x9abcdef0(:32|)" \ + "sub.b @(0x12345678:32,r3l.b),@0x9abcdef0:32" +gdb_test "x" "sub.b\t@\\(0x12345678(:32|),r3.w\\),@er1" \ + "sub.b @(0x12345678:32,r3.w),@er1" +gdb_test "x" "sub.b\t@\\(0x12345678(:32|),r3.w\\),@\\(0x3(:2|),er1\\)" \ + "sub.b @(0x12345678:32,r3.w),@(0x3:2,er1)" +gdb_test "x" "sub.b\t@\\(0x12345678(:32|),r3.w\\),@-er1" \ + "sub.b @(0x12345678:32,r3.w),@-er1" +gdb_test "x" "sub.b\t@\\(0x12345678(:32|),r3.w\\),@er1\\+" \ + "sub.b @(0x12345678:32,r3.w),@er1+" +gdb_test "x" "sub.b\t@\\(0x12345678(:32|),r3.w\\),@er1-" \ + "sub.b @(0x12345678:32,r3.w),@er1-" +gdb_test "x" "sub.b\t@\\(0x12345678(:32|),r3.w\\),@\\+er1" \ + "sub.b @(0x12345678:32,r3.w),@+er1" +gdb_test "x" "sub.b\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abc(:16|),er1\\)" \ + "sub.b @(0x12345678:32,r3.w),@(0x9abc:16,er1)" +gdb_test "x" "sub.b\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "sub.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1)" +gdb_test "x" "sub.b\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "sub.b @(0x12345678:32,r3.w),@(0x9abc:16,r2l.b)" +gdb_test "x" "sub.b\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abc(:16|),r2.w\\)" \ + "sub.b @(0x12345678:32,r3.w),@(0x9abc:16,r2.w)" +gdb_test "x" "sub.b\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abc(:16|),er2.l\\)" \ + "sub.b @(0x12345678:32,r3.w),@(0x9abc:16,er2.l)" +gdb_test "x" "sub.b\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "sub.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "sub.b\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "sub.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "sub.b\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "sub.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "sub.b\t@\\(0x12345678(:32|),r3.w\\),@0x9abc(:16|)" \ + "sub.b @(0x12345678:32,r3.w),@0x9abc:16" +gdb_test "x" "sub.b\t@\\(0x12345678(:32|),r3.w\\),@0x9abcdef0(:32|)" \ + "sub.b @(0x12345678:32,r3.w),@0x9abcdef0:32" +gdb_test "x" "sub.b\t@\\(0x12345678(:32|),er3.l\\),@er1" \ + "sub.b @(0x12345678:32,er3.l),@er1" +gdb_test "x" "sub.b\t@\\(0x12345678(:32|),er3.l\\),@\\(0x3(:2|),er1\\)" \ + "sub.b @(0x12345678:32,er3.l),@(0x3:2,er1)" +gdb_test "x" "sub.b\t@\\(0x12345678(:32|),er3.l\\),@-er1" \ + "sub.b @(0x12345678:32,er3.l),@-er1" +gdb_test "x" "sub.b\t@\\(0x12345678(:32|),er3.l\\),@er1\\+" \ + "sub.b @(0x12345678:32,er3.l),@er1+" +gdb_test "x" "sub.b\t@\\(0x12345678(:32|),er3.l\\),@er1-" \ + "sub.b @(0x12345678:32,er3.l),@er1-" +gdb_test "x" "sub.b\t@\\(0x12345678(:32|),er3.l\\),@\\+er1" \ + "sub.b @(0x12345678:32,er3.l),@+er1" +gdb_test "x" "sub.b\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abc(:16|),er1\\)" \ + "sub.b @(0x12345678:32,er3.l),@(0x9abc:16,er1)" +gdb_test "x" "sub.b\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "sub.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1)" +gdb_test "x" "sub.b\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "sub.b @(0x12345678:32,er3.l),@(0x9abc:16,r2l.b)" +gdb_test "x" "sub.b\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abc(:16|),r2.w\\)" \ + "sub.b @(0x12345678:32,er3.l),@(0x9abc:16,r2.w)" +gdb_test "x" "sub.b\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abc(:16|),er2.l\\)" \ + "sub.b @(0x12345678:32,er3.l),@(0x9abc:16,er2.l)" +gdb_test "x" "sub.b\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "sub.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "sub.b\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "sub.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "sub.b\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "sub.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "sub.b\t@\\(0x12345678(:32|),er3.l\\),@0x9abc(:16|)" \ + "sub.b @(0x12345678:32,er3.l),@0x9abc:16" +gdb_test "x" "sub.b\t@\\(0x12345678(:32|),er3.l\\),@0x9abcdef0(:32|)" \ + "sub.b @(0x12345678:32,er3.l),@0x9abcdef0:32" +gdb_test "x" "sub.b\t@0x1234(:16|),@er1" \ + "sub.b @0x1234:16,@er1" +gdb_test "x" "sub.b\t@0x1234(:16|),@\\(0x3(:2|),er1\\)" \ + "sub.b @0x1234:16,@(0x3:2,er1)" +gdb_test "x" "sub.b\t@0x1234(:16|),@-er1" \ + "sub.b @0x1234:16,@-er1" +gdb_test "x" "sub.b\t@0x1234(:16|),@er1\\+" \ + "sub.b @0x1234:16,@er1+" +gdb_test "x" "sub.b\t@0x1234(:16|),@er1-" \ + "sub.b @0x1234:16,@er1-" +gdb_test "x" "sub.b\t@0x1234(:16|),@\\+er1" \ + "sub.b @0x1234:16,@+er1" +gdb_test "x" "sub.b\t@0x1234(:16|),@\\(0x9abc(:16|),er1\\)" \ + "sub.b @0x1234:16,@(0x9abc:16,er1)" +gdb_test "x" "sub.b\t@0x1234(:16|),@\\(0x9abcdef0(:32|),er1\\)" \ + "sub.b @0x1234:16,@(0x9abcdef0:32,er1)" +gdb_test "x" "sub.b\t@0x1234(:16|),@\\(0x9abc(:16|),r2l.b\\)" \ + "sub.b @0x1234:16,@(0x9abc:16,r2l.b)" +gdb_test "x" "sub.b\t@0x1234(:16|),@\\(0x9abc(:16|),r2.w\\)" \ + "sub.b @0x1234:16,@(0x9abc:16,r2.w)" +gdb_test "x" "sub.b\t@0x1234(:16|),@\\(0x9abc(:16|),er2.l\\)" \ + "sub.b @0x1234:16,@(0x9abc:16,er2.l)" +gdb_test "x" "sub.b\t@0x1234(:16|),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "sub.b @0x1234:16,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "sub.b\t@0x1234(:16|),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "sub.b @0x1234:16,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "sub.b\t@0x1234(:16|),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "sub.b @0x1234:16,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "sub.b\t@0x1234(:16|),@0x9abc(:16|)" \ + "sub.b @0x1234:16,@0x9abc:16" +gdb_test "x" "sub.b\t@0x1234(:16|),@0x9abcdef0(:32|)" \ + "sub.b @0x1234:16,@0x9abcdef0:32" +gdb_test "x" "sub.b\t@0x12345678(:32|),@er1" \ + "sub.b @0x12345678:32,@er1" +gdb_test "x" "sub.b\t@0x12345678(:32|),@\\(0x3(:2|),er1\\)" \ + "sub.b @0x12345678:32,@(0x3:2,er1)" +gdb_test "x" "sub.b\t@0x12345678(:32|),@-er1" \ + "sub.b @0x12345678:32,@-er1" +gdb_test "x" "sub.b\t@0x12345678(:32|),@er1\\+" \ + "sub.b @0x12345678:32,@er1+" +gdb_test "x" "sub.b\t@0x12345678(:32|),@er1-" \ + "sub.b @0x12345678:32,@er1-" +gdb_test "x" "sub.b\t@0x12345678(:32|),@\\+er1" \ + "sub.b @0x12345678:32,@+er1" +gdb_test "x" "sub.b\t@0x12345678(:32|),@\\(0x9abc(:16|),er1\\)" \ + "sub.b @0x12345678:32,@(0x9abc:16,er1)" +gdb_test "x" "sub.b\t@0x12345678(:32|),@\\(0x9abcdef0(:32|),er1\\)" \ + "sub.b @0x12345678:32,@(0x9abcdef0:32,er1)" +gdb_test "x" "sub.b\t@0x12345678(:32|),@\\(0x9abc(:16|),r2l.b\\)" \ + "sub.b @0x12345678:32,@(0x9abc:16,r2l.b)" +gdb_test "x" "sub.b\t@0x12345678(:32|),@\\(0x9abc(:16|),r2.w\\)" \ + "sub.b @0x12345678:32,@(0x9abc:16,r2.w)" +gdb_test "x" "sub.b\t@0x12345678(:32|),@\\(0x9abc(:16|),er2.l\\)" \ + "sub.b @0x12345678:32,@(0x9abc:16,er2.l)" +gdb_test "x" "sub.b\t@0x12345678(:32|),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "sub.b @0x12345678:32,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "sub.b\t@0x12345678(:32|),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "sub.b @0x12345678:32,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "sub.b\t@0x12345678(:32|),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "sub.b @0x12345678:32,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "sub.b\t@0x12345678(:32|),@0x9abc(:16|)" \ + "sub.b @0x12345678:32,@0x9abc:16" +gdb_test "x" "sub.b\t@0x12345678(:32|),@0x9abcdef0(:32|)" \ + "sub.b @0x12345678:32,@0x9abcdef0:32" +gdb_test "x" "sub.w\t#0x1234(:16|),r1" \ + "sub.w #0x1234:16,r1" +gdb_test "x" "sub.w\t#0x7(:3|),r2" \ + "sub.w #0x7:3,r2" +gdb_test "x" "sub.w\t#0x1234(:16|),@er1" \ + "sub.w #0x1234:16,@er1" +gdb_test "x" "sub.w\t#0x1234(:16|),@\\(0x6(:2|),er1\\)" \ + "sub.w #0x1234:16,@(0x6:2,er1)" +gdb_test "x" "sub.w\t#0x1234(:16|),@er1\\+" \ + "sub.w #0x1234:16,@er1+" +gdb_test "x" "sub.w\t#0x1234(:16|),@-er1" \ + "sub.w #0x1234:16,@-er1" +gdb_test "x" "sub.w\t#0x1234(:16|),@\\+er1" \ + "sub.w #0x1234:16,@+er1" +gdb_test "x" "sub.w\t#0x1234(:16|),@er1-" \ + "sub.w #0x1234:16,@er1-" +gdb_test "x" "sub.w\t#0x1234(:16|),@\\(0x9abc(:16|),er1\\)" \ + "sub.w #0x1234:16,@(0x9abc:16,er1)" +gdb_test "x" "sub.w\t#0x1234(:16|),@\\(0x9abcdef0(:32|),er1\\)" \ + "sub.w #0x1234:16,@(0x9abcdef0:32,er1)" +gdb_test "x" "sub.w\t#0x1234(:16|),@\\(0x9abc(:16|),r2l.b\\)" \ + "sub.w #0x1234:16,@(0x9abc:16,r2l.b)" +gdb_test "x" "sub.w\t#0x1234(:16|),@\\(0x9abc(:16|),r2.w\\)" \ + "sub.w #0x1234:16,@(0x9abc:16,r2.w)" +gdb_test "x" "sub.w\t#0x1234(:16|),@\\(0x9abc(:16|),er2.l\\)" \ + "sub.w #0x1234:16,@(0x9abc:16,er2.l)" +gdb_test "x" "sub.w\t#0x1234(:16|),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "sub.w #0x1234:16,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "sub.w\t#0x1234(:16|),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "sub.w #0x1234:16,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "sub.w\t#0x1234(:16|),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "sub.w #0x1234:16,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "sub.w\t#0x1234(:16|),@0x9abc(:16|)" \ + "sub.w #0x1234:16,@0x9abc:16" +gdb_test "x" "sub.w\t#0x1234(:16|),@0x9abcdef0(:32|)" \ + "sub.w #0x1234:16,@0x9abcdef0:32" +gdb_test "x" "sub.w\t#0x7(:3|),@er1" \ + "sub.w #0x7:3,@er1" +gdb_test "x" "sub.w\t#0x7(:3|),@0x1234(:16|)" \ + "sub.w #0x7:3,@0x1234:16" +gdb_test "x" "sub.w\t#0x7(:3|),@0x12345678(:32|)" \ + "sub.w #0x7:3,@0x12345678:32" +gdb_test "x" "sub.w\tr3,r1" \ + "sub.w r3,r1" +gdb_test "x" "sub.w\tr3,@er1" \ + "sub.w r3,@er1" +gdb_test "x" "sub.w\tr3,@\\(0x6(:2|),er1\\)" \ + "sub.w r3,@(0x6:2,er1)" +gdb_test "x" "sub.w\tr3,@er1\\+" \ + "sub.w r3,@er1+" +gdb_test "x" "sub.w\tr3,@-er1" \ + "sub.w r3,@-er1" +gdb_test "x" "sub.w\tr3,@\\+er1" \ + "sub.w r3,@+er1" +gdb_test "x" "sub.w\tr3,@er1-" \ + "sub.w r3,@er1-" +gdb_test "x" "sub.w\tr3,@\\(0x1234(:16|),er1\\)" \ + "sub.w r3,@(0x1234:16,er1)" +gdb_test "x" "sub.w\tr3,@\\(0x12345678(:32|),er1\\)" \ + "sub.w r3,@(0x12345678:32,er1)" +gdb_test "x" "sub.w\tr3,@\\(0x1234(:16|),r2l.b\\)" \ + "sub.w r3,@(0x1234:16,r2l.b)" +gdb_test "x" "sub.w\tr3,@\\(0x1234(:16|),r2.w\\)" \ + "sub.w r3,@(0x1234:16,r2.w)" +gdb_test "x" "sub.w\tr3,@\\(0x1234(:16|),er2.l\\)" \ + "sub.w r3,@(0x1234:16,er2.l)" +gdb_test "x" "sub.w\tr3,@\\(0x12345678(:32|),r2l.b\\)" \ + "sub.w r3,@(0x12345678:32,r2l.b)" +gdb_test "x" "sub.w\tr3,@\\(0x12345678(:32|),r2.w\\)" \ + "sub.w r3,@(0x12345678:32,r2.w)" +gdb_test "x" "sub.w\tr3,@\\(0x12345678(:32|),er2.l\\)" \ + "sub.w r3,@(0x12345678:32,er2.l)" +gdb_test "x" "sub.w\tr3,@0x1234(:16|)" \ + "sub.w r3,@0x1234:16" +gdb_test "x" "sub.w\tr3,@0x12345678(:32|)" \ + "sub.w r3,@0x12345678:32" +gdb_test "x" "sub.w\t@er3,r1" \ + "sub.w @er3,r1" +gdb_test "x" "sub.w\t@\\(0x6(:2|),er3\\),r1" \ + "sub.w @(0x6:2,er3),r1" +gdb_test "x" "sub.w\t@er3\\+,r1" \ + "sub.w @er3+,r1" +gdb_test "x" "sub.w\t@-er3,r1" \ + "sub.w @-er3,r1" +gdb_test "x" "sub.w\t@\\+er3,r1" \ + "sub.w @+er3,r1" +gdb_test "x" "sub.w\t@er3-,r1" \ + "sub.w @er3-,r1" +gdb_test "x" "sub.w\t@\\(0x1234(:16|),er1\\),r1" \ + "sub.w @(0x1234:16,er1),r1" +gdb_test "x" "sub.w\t@\\(0x12345678(:32|),er1\\),r1" \ + "sub.w @(0x12345678:32,er1),r1" +gdb_test "x" "sub.w\t@\\(0x1234(:16|),r2l.b\\),r1" \ + "sub.w @(0x1234:16,r2l.b),r1" +gdb_test "x" "sub.w\t@\\(0x1234(:16|),r2.w\\),r1" \ + "sub.w @(0x1234:16,r2.w),r1" +gdb_test "x" "sub.w\t@\\(0x1234(:16|),er2.l\\),r1" \ + "sub.w @(0x1234:16,er2.l),r1" +gdb_test "x" "sub.w\t@\\(0x12345678(:32|),r2l.b\\),r1" \ + "sub.w @(0x12345678:32,r2l.b),r1" +gdb_test "x" "sub.w\t@\\(0x12345678(:32|),r2.w\\),r1" \ + "sub.w @(0x12345678:32,r2.w),r1" +gdb_test "x" "sub.w\t@\\(0x12345678(:32|),er2.l\\),r1" \ + "sub.w @(0x12345678:32,er2.l),r1" +gdb_test "x" "sub.w\t@0x1234(:16|),r1" \ + "sub.w @0x1234:16,r1" +gdb_test "x" "sub.w\t@0x12345678(:32|),r1" \ + "sub.w @0x12345678:32,r1" +gdb_test "x" "sub.w\t@er3,@er1" \ + "sub.w @er3,@er1" +gdb_test "x" "sub.w\t@er3,@\\(0x6(:2|),er1\\)" \ + "sub.w @er3,@(0x6:2,er1)" +gdb_test "x" "sub.w\t@er3,@-er1" \ + "sub.w @er3,@-er1" +gdb_test "x" "sub.w\t@er3,@er1\\+" \ + "sub.w @er3,@er1+" +gdb_test "x" "sub.w\t@er3,@er1-" \ + "sub.w @er3,@er1-" +gdb_test "x" "sub.w\t@er3,@\\+er1" \ + "sub.w @er3,@+er1" +gdb_test "x" "sub.w\t@er3,@\\(0x9abc(:16|),er1\\)" \ + "sub.w @er3,@(0x9abc:16,er1)" +gdb_test "x" "sub.w\t@er3,@\\(0x9abcdef0(:32|),er1\\)" \ + "sub.w @er3,@(0x9abcdef0:32,er1)" +gdb_test "x" "sub.w\t@er3,@\\(0x9abc(:16|),r2l.b\\)" \ + "sub.w @er3,@(0x9abc:16,r2l.b)" +gdb_test "x" "sub.w\t@er3,@\\(0x9abc(:16|),r2.w\\)" \ + "sub.w @er3,@(0x9abc:16,r2.w)" +gdb_test "x" "sub.w\t@er3,@\\(0x9abc(:16|),er2.l\\)" \ + "sub.w @er3,@(0x9abc:16,er2.l)" +gdb_test "x" "sub.w\t@er3,@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "sub.w @er3,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "sub.w\t@er3,@\\(0x9abcdef0(:32|),r2.w\\)" \ + "sub.w @er3,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "sub.w\t@er3,@\\(0x9abcdef0(:32|),er2.l\\)" \ + "sub.w @er3,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "sub.w\t@er3,@0x9abc(:16|)" \ + "sub.w @er3,@0x9abc:16" +gdb_test "x" "sub.w\t@er3,@0x9abcdef0(:32|)" \ + "sub.w @er3,@0x9abcdef0:32" +gdb_test "x" "sub.w\t@-er3,@er1" \ + "sub.w @-er3,@er1" +gdb_test "x" "sub.w\t@-er3,@\\(0x6(:2|),er1\\)" \ + "sub.w @-er3,@(0x6:2,er1)" +gdb_test "x" "sub.w\t@-er3,@-er1" \ + "sub.w @-er3,@-er1" +gdb_test "x" "sub.w\t@-er3,@er1\\+" \ + "sub.w @-er3,@er1+" +gdb_test "x" "sub.w\t@-er3,@er1-" \ + "sub.w @-er3,@er1-" +gdb_test "x" "sub.w\t@-er3,@\\+er1" \ + "sub.w @-er3,@+er1" +gdb_test "x" "sub.w\t@-er3,@\\(0x9abc(:16|),er1\\)" \ + "sub.w @-er3,@(0x9abc:16,er1)" +gdb_test "x" "sub.w\t@-er3,@\\(0x9abcdef0(:32|),er1\\)" \ + "sub.w @-er3,@(0x9abcdef0:32,er1)" +gdb_test "x" "sub.w\t@-er3,@\\(0x9abc(:16|),r2l.b\\)" \ + "sub.w @-er3,@(0x9abc:16,r2l.b)" +gdb_test "x" "sub.w\t@-er3,@\\(0x9abc(:16|),r2.w\\)" \ + "sub.w @-er3,@(0x9abc:16,r2.w)" +gdb_test "x" "sub.w\t@-er3,@\\(0x9abc(:16|),er2.l\\)" \ + "sub.w @-er3,@(0x9abc:16,er2.l)" +gdb_test "x" "sub.w\t@-er3,@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "sub.w @-er3,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "sub.w\t@-er3,@\\(0x9abcdef0(:32|),r2.w\\)" \ + "sub.w @-er3,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "sub.w\t@-er3,@\\(0x9abcdef0(:32|),er2.l\\)" \ + "sub.w @-er3,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "sub.w\t@-er3,@0x9abc(:16|)" \ + "sub.w @-er3,@0x9abc:16" +gdb_test "x" "sub.w\t@-er3,@0x9abcdef0(:32|)" \ + "sub.w @-er3,@0x9abcdef0:32" +gdb_test "x" "sub.w\t@er3\\+,@er1" \ + "sub.w @er3+,@er1" +gdb_test "x" "sub.w\t@er3\\+,@\\(0x6(:2|),er1\\)" \ + "sub.w @er3+,@(0x6:2,er1)" +gdb_test "x" "sub.w\t@er3\\+,@-er1" \ + "sub.w @er3+,@-er1" +gdb_test "x" "sub.w\t@er3\\+,@er1\\+" \ + "sub.w @er3+,@er1+" +gdb_test "x" "sub.w\t@er3\\+,@er1-" \ + "sub.w @er3+,@er1-" +gdb_test "x" "sub.w\t@er3\\+,@\\+er1" \ + "sub.w @er3+,@+er1" +gdb_test "x" "sub.w\t@er3\\+,@\\(0x9abc(:16|),er1\\)" \ + "sub.w @er3+,@(0x9abc:16,er1)" +gdb_test "x" "sub.w\t@er3\\+,@\\(0x9abcdef0(:32|),er1\\)" \ + "sub.w @er3+,@(0x9abcdef0:32,er1)" +gdb_test "x" "sub.w\t@er3\\+,@\\(0x9abc(:16|),r2l.b\\)" \ + "sub.w @er3+,@(0x9abc:16,r2l.b)" +gdb_test "x" "sub.w\t@er3\\+,@\\(0x9abc(:16|),r2.w\\)" \ + "sub.w @er3+,@(0x9abc:16,r2.w)" +gdb_test "x" "sub.w\t@er3\\+,@\\(0x9abc(:16|),er2.l\\)" \ + "sub.w @er3+,@(0x9abc:16,er2.l)" +gdb_test "x" "sub.w\t@er3\\+,@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "sub.w @er3+,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "sub.w\t@er3\\+,@\\(0x9abcdef0(:32|),r2.w\\)" \ + "sub.w @er3+,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "sub.w\t@er3\\+,@\\(0x9abcdef0(:32|),er2.l\\)" \ + "sub.w @er3+,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "sub.w\t@er3\\+,@0x9abc(:16|)" \ + "sub.w @er3+,@0x9abc:16" +gdb_test "x" "sub.w\t@er3\\+,@0x9abcdef0(:32|)" \ + "sub.w @er3+,@0x9abcdef0:32" +gdb_test "x" "sub.w\t@er3-,@er1" \ + "sub.w @er3-,@er1" +gdb_test "x" "sub.w\t@er3-,@\\(0x6(:2|),er1\\)" \ + "sub.w @er3-,@(0x6:2,er1)" +gdb_test "x" "sub.w\t@er3-,@-er1" \ + "sub.w @er3-,@-er1" +gdb_test "x" "sub.w\t@er3-,@er1\\+" \ + "sub.w @er3-,@er1+" +gdb_test "x" "sub.w\t@er3-,@er1-" \ + "sub.w @er3-,@er1-" +gdb_test "x" "sub.w\t@er3-,@\\+er1" \ + "sub.w @er3-,@+er1" +gdb_test "x" "sub.w\t@er3-,@\\(0x9abc(:16|),er1\\)" \ + "sub.w @er3-,@(0x9abc:16,er1)" +gdb_test "x" "sub.w\t@er3-,@\\(0x9abcdef0(:32|),er1\\)" \ + "sub.w @er3-,@(0x9abcdef0:32,er1)" +gdb_test "x" "sub.w\t@er3-,@\\(0x9abc(:16|),r2l.b\\)" \ + "sub.w @er3-,@(0x9abc:16,r2l.b)" +gdb_test "x" "sub.w\t@er3-,@\\(0x9abc(:16|),r2.w\\)" \ + "sub.w @er3-,@(0x9abc:16,r2.w)" +gdb_test "x" "sub.w\t@er3-,@\\(0x9abc(:16|),er2.l\\)" \ + "sub.w @er3-,@(0x9abc:16,er2.l)" +gdb_test "x" "sub.w\t@er3-,@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "sub.w @er3-,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "sub.w\t@er3-,@\\(0x9abcdef0(:32|),r2.w\\)" \ + "sub.w @er3-,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "sub.w\t@er3-,@\\(0x9abcdef0(:32|),er2.l\\)" \ + "sub.w @er3-,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "sub.w\t@er3-,@0x9abc(:16|)" \ + "sub.w @er3-,@0x9abc:16" +gdb_test "x" "sub.w\t@er3-,@0x9abcdef0(:32|)" \ + "sub.w @er3-,@0x9abcdef0:32" +gdb_test "x" "sub.w\t@\\+er3,@er1" \ + "sub.w @+er3,@er1" +gdb_test "x" "sub.w\t@\\+er3,@\\(0x6(:2|),er1\\)" \ + "sub.w @+er3,@(0x6:2,er1)" +gdb_test "x" "sub.w\t@\\+er3,@-er1" \ + "sub.w @+er3,@-er1" +gdb_test "x" "sub.w\t@\\+er3,@er1\\+" \ + "sub.w @+er3,@er1+" +gdb_test "x" "sub.w\t@\\+er3,@er1-" \ + "sub.w @+er3,@er1-" +gdb_test "x" "sub.w\t@\\+er3,@\\+er1" \ + "sub.w @+er3,@+er1" +gdb_test "x" "sub.w\t@\\+er3,@\\(0x9abc(:16|),er1\\)" \ + "sub.w @+er3,@(0x9abc:16,er1)" +gdb_test "x" "sub.w\t@\\+er3,@\\(0x9abcdef0(:32|),er1\\)" \ + "sub.w @+er3,@(0x9abcdef0:32,er1)" +gdb_test "x" "sub.w\t@\\+er3,@\\(0x9abc(:16|),r2l.b\\)" \ + "sub.w @+er3,@(0x9abc:16,r2l.b)" +gdb_test "x" "sub.w\t@\\+er3,@\\(0x9abc(:16|),r2.w\\)" \ + "sub.w @+er3,@(0x9abc:16,r2.w)" +gdb_test "x" "sub.w\t@\\+er3,@\\(0x9abc(:16|),er2.l\\)" \ + "sub.w @+er3,@(0x9abc:16,er2.l)" +gdb_test "x" "sub.w\t@\\+er3,@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "sub.w @+er3,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "sub.w\t@\\+er3,@\\(0x9abcdef0(:32|),r2.w\\)" \ + "sub.w @+er3,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "sub.w\t@\\+er3,@\\(0x9abcdef0(:32|),er2.l\\)" \ + "sub.w @+er3,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "sub.w\t@\\+er3,@0x9abc(:16|)" \ + "sub.w @+er3,@0x9abc:16" +gdb_test "x" "sub.w\t@\\+er3,@0x9abcdef0(:32|)" \ + "sub.w @+er3,@0x9abcdef0:32" +gdb_test "x" "sub.w\t@\\(0x1234(:16|),er3\\),@er1" \ + "sub.w @(0x1234:16,er3),@er1" +gdb_test "x" "sub.w\t@\\(0x1234(:16|),er3\\),@\\(0x6(:2|),er1\\)" \ + "sub.w @(0x1234:16,er3),@(0x6:2,er1)" +gdb_test "x" "sub.w\t@\\(0x1234(:16|),er3\\),@-er1" \ + "sub.w @(0x1234:16,er3),@-er1" +gdb_test "x" "sub.w\t@\\(0x1234(:16|),er3\\),@er1\\+" \ + "sub.w @(0x1234:16,er3),@er1+" +gdb_test "x" "sub.w\t@\\(0x1234(:16|),er3\\),@er1-" \ + "sub.w @(0x1234:16,er3),@er1-" +gdb_test "x" "sub.w\t@\\(0x1234(:16|),er3\\),@\\+er1" \ + "sub.w @(0x1234:16,er3),@+er1" +gdb_test "x" "sub.w\t@\\(0x1234(:16|),er3\\),@\\(0x9abc(:16|),er1\\)" \ + "sub.w @(0x1234:16,er3),@(0x9abc:16,er1)" +gdb_test "x" "sub.w\t@\\(0x1234(:16|),er3\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "sub.w @(0x1234:16,er3),@(0x9abcdef0:32,er1)" +gdb_test "x" "sub.w\t@\\(0x1234(:16|),er3\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "sub.w @(0x1234:16,er3),@(0x9abc:16,r2l.b)" +gdb_test "x" "sub.w\t@\\(0x1234(:16|),er3\\),@\\(0x9abc(:16|),r2.w\\)" \ + "sub.w @(0x1234:16,er3),@(0x9abc:16,r2.w)" +gdb_test "x" "sub.w\t@\\(0x1234(:16|),er3\\),@\\(0x9abc(:16|),er2.l\\)" \ + "sub.w @(0x1234:16,er3),@(0x9abc:16,er2.l)" +gdb_test "x" "sub.w\t@\\(0x1234(:16|),er3\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "sub.w @(0x1234:16,er3),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "sub.w\t@\\(0x1234(:16|),er3\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "sub.w @(0x1234:16,er3),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "sub.w\t@\\(0x1234(:16|),er3\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "sub.w @(0x1234:16,er3),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "sub.w\t@\\(0x1234(:16|),er3\\),@0x9abc(:16|)" \ + "sub.w @(0x1234:16,er3),@0x9abc:16" +gdb_test "x" "sub.w\t@\\(0x1234(:16|),er3\\),@0x9abcdef0(:32|)" \ + "sub.w @(0x1234:16,er3),@0x9abcdef0:32" +gdb_test "x" "sub.w\t@\\(0x12345678(:32|),er3\\),@er1" \ + "sub.w @(0x12345678:32,er3),@er1" +gdb_test "x" "sub.w\t@\\(0x12345678(:32|),er3\\),@\\(0x6(:2|),er1\\)" \ + "sub.w @(0x12345678:32,er3),@(0x6:2,er1)" +gdb_test "x" "sub.w\t@\\(0x12345678(:32|),er3\\),@-er1" \ + "sub.w @(0x12345678:32,er3),@-er1" +gdb_test "x" "sub.w\t@\\(0x12345678(:32|),er3\\),@er1\\+" \ + "sub.w @(0x12345678:32,er3),@er1+" +gdb_test "x" "sub.w\t@\\(0x12345678(:32|),er3\\),@er1-" \ + "sub.w @(0x12345678:32,er3),@er1-" +gdb_test "x" "sub.w\t@\\(0x12345678(:32|),er3\\),@\\+er1" \ + "sub.w @(0x12345678:32,er3),@+er1" +gdb_test "x" "sub.w\t@\\(0x12345678(:32|),er3\\),@\\(0x9abc(:16|),er1\\)" \ + "sub.w @(0x12345678:32,er3),@(0x9abc:16,er1)" +gdb_test "x" "sub.w\t@\\(0x12345678(:32|),er3\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "sub.w @(0x12345678:32,er3),@(0x9abcdef0:32,er1)" +gdb_test "x" "sub.w\t@\\(0x12345678(:32|),er3\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "sub.w @(0x12345678:32,er3),@(0x9abc:16,r2l.b)" +gdb_test "x" "sub.w\t@\\(0x12345678(:32|),er3\\),@\\(0x9abc(:16|),r2.w\\)" \ + "sub.w @(0x12345678:32,er3),@(0x9abc:16,r2.w)" +gdb_test "x" "sub.w\t@\\(0x12345678(:32|),er3\\),@\\(0x9abc(:16|),er2.l\\)" \ + "sub.w @(0x12345678:32,er3),@(0x9abc:16,er2.l)" +gdb_test "x" "sub.w\t@\\(0x12345678(:32|),er3\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "sub.w @(0x12345678:32,er3),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "sub.w\t@\\(0x12345678(:32|),er3\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "sub.w @(0x12345678:32,er3),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "sub.w\t@\\(0x12345678(:32|),er3\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "sub.w @(0x12345678:32,er3),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "sub.w\t@\\(0x12345678(:32|),er3\\),@0x9abc(:16|)" \ + "sub.w @(0x12345678:32,er3),@0x9abc:16" +gdb_test "x" "sub.w\t@\\(0x12345678(:32|),er3\\),@0x9abcdef0(:32|)" \ + "sub.w @(0x12345678:32,er3),@0x9abcdef0:32" +gdb_test "x" "sub.w\t@\\(0x1234(:16|),r3l.b\\),@er1" \ + "sub.w @(0x1234:16,r3l.b),@er1" +gdb_test "x" "sub.w\t@\\(0x1234(:16|),r3l.b\\),@\\(0x6(:2|),er1\\)" \ + "sub.w @(0x1234:16,r3l.b),@(0x6:2,er1)" +gdb_test "x" "sub.w\t@\\(0x1234(:16|),r3l.b\\),@-er1" \ + "sub.w @(0x1234:16,r3l.b),@-er1" +gdb_test "x" "sub.w\t@\\(0x1234(:16|),r3l.b\\),@er1\\+" \ + "sub.w @(0x1234:16,r3l.b),@er1+" +gdb_test "x" "sub.w\t@\\(0x1234(:16|),r3l.b\\),@er1-" \ + "sub.w @(0x1234:16,r3l.b),@er1-" +gdb_test "x" "sub.w\t@\\(0x1234(:16|),r3l.b\\),@\\+er1" \ + "sub.w @(0x1234:16,r3l.b),@+er1" +gdb_test "x" "sub.w\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abc(:16|),er1\\)" \ + "sub.w @(0x1234:16,r3l.b),@(0x9abc:16,er1)" +gdb_test "x" "sub.w\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "sub.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1)" +gdb_test "x" "sub.w\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "sub.w @(0x1234:16,r3l.b),@(0x9abc:16,r2l.b)" +gdb_test "x" "sub.w\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abc(:16|),r2.w\\)" \ + "sub.w @(0x1234:16,r3l.b),@(0x9abc:16,r2.w)" +gdb_test "x" "sub.w\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abc(:16|),er2.l\\)" \ + "sub.w @(0x1234:16,r3l.b),@(0x9abc:16,er2.l)" +gdb_test "x" "sub.w\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "sub.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "sub.w\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "sub.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "sub.w\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "sub.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "sub.w\t@\\(0x1234(:16|),r3l.b\\),@0x9abc(:16|)" \ + "sub.w @(0x1234:16,r3l.b),@0x9abc:16" +gdb_test "x" "sub.w\t@\\(0x1234(:16|),r3l.b\\),@0x9abcdef0(:32|)" \ + "sub.w @(0x1234:16,r3l.b),@0x9abcdef0:32" +gdb_test "x" "sub.w\t@\\(0x1234(:16|),r3.w\\),@er1" \ + "sub.w @(0x1234:16,r3.w),@er1" +gdb_test "x" "sub.w\t@\\(0x1234(:16|),r3.w\\),@\\(0x6(:2|),er1\\)" \ + "sub.w @(0x1234:16,r3.w),@(0x6:2,er1)" +gdb_test "x" "sub.w\t@\\(0x1234(:16|),r3.w\\),@-er1" \ + "sub.w @(0x1234:16,r3.w),@-er1" +gdb_test "x" "sub.w\t@\\(0x1234(:16|),r3.w\\),@er1\\+" \ + "sub.w @(0x1234:16,r3.w),@er1+" +gdb_test "x" "sub.w\t@\\(0x1234(:16|),r3.w\\),@er1-" \ + "sub.w @(0x1234:16,r3.w),@er1-" +gdb_test "x" "sub.w\t@\\(0x1234(:16|),r3.w\\),@\\+er1" \ + "sub.w @(0x1234:16,r3.w),@+er1" +gdb_test "x" "sub.w\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abc(:16|),er1\\)" \ + "sub.w @(0x1234:16,r3.w),@(0x9abc:16,er1)" +gdb_test "x" "sub.w\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "sub.w @(0x1234:16,r3.w),@(0x9abcdef0:32,er1)" +gdb_test "x" "sub.w\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "sub.w @(0x1234:16,r3.w),@(0x9abc:16,r2l.b)" +gdb_test "x" "sub.w\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abc(:16|),r2.w\\)" \ + "sub.w @(0x1234:16,r3.w),@(0x9abc:16,r2.w)" +gdb_test "x" "sub.w\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abc(:16|),er2.l\\)" \ + "sub.w @(0x1234:16,r3.w),@(0x9abc:16,er2.l)" +gdb_test "x" "sub.w\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "sub.w @(0x1234:16,r3.w),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "sub.w\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "sub.w @(0x1234:16,r3.w),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "sub.w\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "sub.w @(0x1234:16,r3.w),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "sub.w\t@\\(0x1234(:16|),r3.w\\),@0x9abc(:16|)" \ + "sub.w @(0x1234:16,r3.w),@0x9abc:16" +gdb_test "x" "sub.w\t@\\(0x1234(:16|),r3.w\\),@0x9abcdef0(:32|)" \ + "sub.w @(0x1234:16,r3.w),@0x9abcdef0:32" +gdb_test "x" "sub.w\t@\\(0x1234(:16|),er3.l\\),@er1" \ + "sub.w @(0x1234:16,er3.l),@er1" +gdb_test "x" "sub.w\t@\\(0x1234(:16|),er3.l\\),@\\(0x6(:2|),er1\\)" \ + "sub.w @(0x1234:16,er3.l),@(0x6:2,er1)" +gdb_test "x" "sub.w\t@\\(0x1234(:16|),er3.l\\),@-er1" \ + "sub.w @(0x1234:16,er3.l),@-er1" +gdb_test "x" "sub.w\t@\\(0x1234(:16|),er3.l\\),@er1\\+" \ + "sub.w @(0x1234:16,er3.l),@er1+" +gdb_test "x" "sub.w\t@\\(0x1234(:16|),er3.l\\),@er1-" \ + "sub.w @(0x1234:16,er3.l),@er1-" +gdb_test "x" "sub.w\t@\\(0x1234(:16|),er3.l\\),@\\+er1" \ + "sub.w @(0x1234:16,er3.l),@+er1" +gdb_test "x" "sub.w\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abc(:16|),er1\\)" \ + "sub.w @(0x1234:16,er3.l),@(0x9abc:16,er1)" +gdb_test "x" "sub.w\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "sub.w @(0x1234:16,er3.l),@(0x9abcdef0:32,er1)" +gdb_test "x" "sub.w\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "sub.w @(0x1234:16,er3.l),@(0x9abc:16,r2l.b)" +gdb_test "x" "sub.w\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abc(:16|),r2.w\\)" \ + "sub.w @(0x1234:16,er3.l),@(0x9abc:16,r2.w)" +gdb_test "x" "sub.w\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abc(:16|),er2.l\\)" \ + "sub.w @(0x1234:16,er3.l),@(0x9abc:16,er2.l)" +gdb_test "x" "sub.w\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "sub.w @(0x1234:16,er3.l),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "sub.w\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "sub.w @(0x1234:16,er3.l),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "sub.w\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "sub.w @(0x1234:16,er3.l),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "sub.w\t@\\(0x1234(:16|),er3.l\\),@0x9abc(:16|)" \ + "sub.w @(0x1234:16,er3.l),@0x9abc:16" +gdb_test "x" "sub.w\t@\\(0x1234(:16|),er3.l\\),@0x9abcdef0(:32|)" \ + "sub.w @(0x1234:16,er3.l),@0x9abcdef0:32" +gdb_test "x" "sub.w\t@\\(0x12345678(:32|),r3l.b\\),@er1" \ + "sub.w @(0x12345678:32,r3l.b),@er1" +gdb_test "x" "sub.w\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x6(:2|),er1\\)" \ + "sub.w @(0x12345678:32,r3l.b),@(0x6:2,er1)" +gdb_test "x" "sub.w\t@\\(0x12345678(:32|),r3l.b\\),@-er1" \ + "sub.w @(0x12345678:32,r3l.b),@-er1" +gdb_test "x" "sub.w\t@\\(0x12345678(:32|),r3l.b\\),@er1\\+" \ + "sub.w @(0x12345678:32,r3l.b),@er1+" +gdb_test "x" "sub.w\t@\\(0x12345678(:32|),r3l.b\\),@er1-" \ + "sub.w @(0x12345678:32,r3l.b),@er1-" +gdb_test "x" "sub.w\t@\\(0x12345678(:32|),r3l.b\\),@\\+er1" \ + "sub.w @(0x12345678:32,r3l.b),@+er1" +gdb_test "x" "sub.w\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abc(:16|),er1\\)" \ + "sub.w @(0x12345678:32,r3l.b),@(0x9abc:16,er1)" +gdb_test "x" "sub.w\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "sub.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1)" +gdb_test "x" "sub.w\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "sub.w @(0x12345678:32,r3l.b),@(0x9abc:16,r2l.b)" +gdb_test "x" "sub.w\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abc(:16|),r2.w\\)" \ + "sub.w @(0x12345678:32,r3l.b),@(0x9abc:16,r2.w)" +gdb_test "x" "sub.w\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abc(:16|),er2.l\\)" \ + "sub.w @(0x12345678:32,r3l.b),@(0x9abc:16,er2.l)" +gdb_test "x" "sub.w\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "sub.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "sub.w\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "sub.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "sub.w\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "sub.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "sub.w\t@\\(0x12345678(:32|),r3l.b\\),@0x9abc(:16|)" \ + "sub.w @(0x12345678:32,r3l.b),@0x9abc:16" +gdb_test "x" "sub.w\t@\\(0x12345678(:32|),r3l.b\\),@0x9abcdef0(:32|)" \ + "sub.w @(0x12345678:32,r3l.b),@0x9abcdef0:32" +gdb_test "x" "sub.w\t@\\(0x12345678(:32|),r3.w\\),@er1" \ + "sub.w @(0x12345678:32,r3.w),@er1" +gdb_test "x" "sub.w\t@\\(0x12345678(:32|),r3.w\\),@\\(0x6(:2|),er1\\)" \ + "sub.w @(0x12345678:32,r3.w),@(0x6:2,er1)" +gdb_test "x" "sub.w\t@\\(0x12345678(:32|),r3.w\\),@-er1" \ + "sub.w @(0x12345678:32,r3.w),@-er1" +gdb_test "x" "sub.w\t@\\(0x12345678(:32|),r3.w\\),@er1\\+" \ + "sub.w @(0x12345678:32,r3.w),@er1+" +gdb_test "x" "sub.w\t@\\(0x12345678(:32|),r3.w\\),@er1-" \ + "sub.w @(0x12345678:32,r3.w),@er1-" +gdb_test "x" "sub.w\t@\\(0x12345678(:32|),r3.w\\),@\\+er1" \ + "sub.w @(0x12345678:32,r3.w),@+er1" +gdb_test "x" "sub.w\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abc(:16|),er1\\)" \ + "sub.w @(0x12345678:32,r3.w),@(0x9abc:16,er1)" +gdb_test "x" "sub.w\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "sub.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1)" +gdb_test "x" "sub.w\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "sub.w @(0x12345678:32,r3.w),@(0x9abc:16,r2l.b)" +gdb_test "x" "sub.w\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abc(:16|),r2.w\\)" \ + "sub.w @(0x12345678:32,r3.w),@(0x9abc:16,r2.w)" +gdb_test "x" "sub.w\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abc(:16|),er2.l\\)" \ + "sub.w @(0x12345678:32,r3.w),@(0x9abc:16,er2.l)" +gdb_test "x" "sub.w\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "sub.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "sub.w\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "sub.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "sub.w\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "sub.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "sub.w\t@\\(0x12345678(:32|),r3.w\\),@0x9abc(:16|)" \ + "sub.w @(0x12345678:32,r3.w),@0x9abc:16" +gdb_test "x" "sub.w\t@\\(0x12345678(:32|),r3.w\\),@0x9abcdef0(:32|)" \ + "sub.w @(0x12345678:32,r3.w),@0x9abcdef0:32" +gdb_test "x" "sub.w\t@\\(0x12345678(:32|),er3.l\\),@er1" \ + "sub.w @(0x12345678:32,er3.l),@er1" +gdb_test "x" "sub.w\t@\\(0x12345678(:32|),er3.l\\),@\\(0x6(:2|),er1\\)" \ + "sub.w @(0x12345678:32,er3.l),@(0x6:2,er1)" +gdb_test "x" "sub.w\t@\\(0x12345678(:32|),er3.l\\),@-er1" \ + "sub.w @(0x12345678:32,er3.l),@-er1" +gdb_test "x" "sub.w\t@\\(0x12345678(:32|),er3.l\\),@er1\\+" \ + "sub.w @(0x12345678:32,er3.l),@er1+" +gdb_test "x" "sub.w\t@\\(0x12345678(:32|),er3.l\\),@er1-" \ + "sub.w @(0x12345678:32,er3.l),@er1-" +gdb_test "x" "sub.w\t@\\(0x12345678(:32|),er3.l\\),@\\+er1" \ + "sub.w @(0x12345678:32,er3.l),@+er1" +gdb_test "x" "sub.w\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abc(:16|),er1\\)" \ + "sub.w @(0x12345678:32,er3.l),@(0x9abc:16,er1)" +gdb_test "x" "sub.w\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "sub.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1)" +gdb_test "x" "sub.w\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "sub.w @(0x12345678:32,er3.l),@(0x9abc:16,r2l.b)" +gdb_test "x" "sub.w\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abc(:16|),r2.w\\)" \ + "sub.w @(0x12345678:32,er3.l),@(0x9abc:16,r2.w)" +gdb_test "x" "sub.w\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abc(:16|),er2.l\\)" \ + "sub.w @(0x12345678:32,er3.l),@(0x9abc:16,er2.l)" +gdb_test "x" "sub.w\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "sub.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "sub.w\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "sub.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "sub.w\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "sub.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "sub.w\t@\\(0x12345678(:32|),er3.l\\),@0x9abc(:16|)" \ + "sub.w @(0x12345678:32,er3.l),@0x9abc:16" +gdb_test "x" "sub.w\t@\\(0x12345678(:32|),er3.l\\),@0x9abcdef0(:32|)" \ + "sub.w @(0x12345678:32,er3.l),@0x9abcdef0:32" +gdb_test "x" "sub.w\t@0x1234(:16|),@er1" \ + "sub.w @0x1234:16,@er1" +gdb_test "x" "sub.w\t@0x1234(:16|),@\\(0x6(:2|),er1\\)" \ + "sub.w @0x1234:16,@(0x6:2,er1)" +gdb_test "x" "sub.w\t@0x1234(:16|),@-er1" \ + "sub.w @0x1234:16,@-er1" +gdb_test "x" "sub.w\t@0x1234(:16|),@er1\\+" \ + "sub.w @0x1234:16,@er1+" +gdb_test "x" "sub.w\t@0x1234(:16|),@er1-" \ + "sub.w @0x1234:16,@er1-" +gdb_test "x" "sub.w\t@0x1234(:16|),@\\+er1" \ + "sub.w @0x1234:16,@+er1" +gdb_test "x" "sub.w\t@0x1234(:16|),@\\(0x9abc(:16|),er1\\)" \ + "sub.w @0x1234:16,@(0x9abc:16,er1)" +gdb_test "x" "sub.w\t@0x1234(:16|),@\\(0x9abcdef0(:32|),er1\\)" \ + "sub.w @0x1234:16,@(0x9abcdef0:32,er1)" +gdb_test "x" "sub.w\t@0x1234(:16|),@\\(0x9abc(:16|),r2l.b\\)" \ + "sub.w @0x1234:16,@(0x9abc:16,r2l.b)" +gdb_test "x" "sub.w\t@0x1234(:16|),@\\(0x9abc(:16|),r2.w\\)" \ + "sub.w @0x1234:16,@(0x9abc:16,r2.w)" +gdb_test "x" "sub.w\t@0x1234(:16|),@\\(0x9abc(:16|),er2.l\\)" \ + "sub.w @0x1234:16,@(0x9abc:16,er2.l)" +gdb_test "x" "sub.w\t@0x1234(:16|),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "sub.w @0x1234:16,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "sub.w\t@0x1234(:16|),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "sub.w @0x1234:16,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "sub.w\t@0x1234(:16|),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "sub.w @0x1234:16,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "sub.w\t@0x1234(:16|),@0x9abc(:16|)" \ + "sub.w @0x1234:16,@0x9abc:16" +gdb_test "x" "sub.w\t@0x1234(:16|),@0x9abcdef0(:32|)" \ + "sub.w @0x1234:16,@0x9abcdef0:32" +gdb_test "x" "sub.w\t@0x12345678(:32|),@er1" \ + "sub.w @0x12345678:32,@er1" +gdb_test "x" "sub.w\t@0x12345678(:32|),@\\(0x6(:2|),er1\\)" \ + "sub.w @0x12345678:32,@(0x6:2,er1)" +gdb_test "x" "sub.w\t@0x12345678(:32|),@-er1" \ + "sub.w @0x12345678:32,@-er1" +gdb_test "x" "sub.w\t@0x12345678(:32|),@er1\\+" \ + "sub.w @0x12345678:32,@er1+" +gdb_test "x" "sub.w\t@0x12345678(:32|),@er1-" \ + "sub.w @0x12345678:32,@er1-" +gdb_test "x" "sub.w\t@0x12345678(:32|),@\\+er1" \ + "sub.w @0x12345678:32,@+er1" +gdb_test "x" "sub.w\t@0x12345678(:32|),@\\(0x9abc(:16|),er1\\)" \ + "sub.w @0x12345678:32,@(0x9abc:16,er1)" +gdb_test "x" "sub.w\t@0x12345678(:32|),@\\(0x9abcdef0(:32|),er1\\)" \ + "sub.w @0x12345678:32,@(0x9abcdef0:32,er1)" +gdb_test "x" "sub.w\t@0x12345678(:32|),@\\(0x9abc(:16|),r2l.b\\)" \ + "sub.w @0x12345678:32,@(0x9abc:16,r2l.b)" +gdb_test "x" "sub.w\t@0x12345678(:32|),@\\(0x9abc(:16|),r2.w\\)" \ + "sub.w @0x12345678:32,@(0x9abc:16,r2.w)" +gdb_test "x" "sub.w\t@0x12345678(:32|),@\\(0x9abc(:16|),er2.l\\)" \ + "sub.w @0x12345678:32,@(0x9abc:16,er2.l)" +gdb_test "x" "sub.w\t@0x12345678(:32|),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "sub.w @0x12345678:32,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "sub.w\t@0x12345678(:32|),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "sub.w @0x12345678:32,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "sub.w\t@0x12345678(:32|),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "sub.w @0x12345678:32,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "sub.w\t@0x12345678(:32|),@0x9abc(:16|)" \ + "sub.w @0x12345678:32,@0x9abc:16" +gdb_test "x" "sub.w\t@0x12345678(:32|),@0x9abcdef0(:32|)" \ + "sub.w @0x12345678:32,@0x9abcdef0:32" +gdb_test "x" "sub.l\t#0x12345678(:32|),er1" \ + "sub.l #0x12345678:32,er1" +gdb_test "x" "sub.l\t#0x1234(:16|),er1" \ + "sub.l #0x1234:16,er1" +gdb_test "x" "sub.l\t#0x7(:3|),er2" \ + "sub.l #0x7:3,er2" +gdb_test "x" "sub.l\t#0x12345678(:32|),@er1" \ + "sub.l #0x12345678:32,@er1" +gdb_test "x" "sub.l\t#0x12345678(:32|),@\\(0xc(:2|),er1\\)" \ + "sub.l #0x12345678:32,@(0xc:2,er1)" +gdb_test "x" "sub.l\t#0x12345678(:32|),@er1\\+" \ + "sub.l #0x12345678:32,@er1+" +gdb_test "x" "sub.l\t#0x12345678(:32|),@-er1" \ + "sub.l #0x12345678:32,@-er1" +gdb_test "x" "sub.l\t#0x12345678(:32|),@\\+er1" \ + "sub.l #0x12345678:32,@+er1" +gdb_test "x" "sub.l\t#0x12345678(:32|),@er1-" \ + "sub.l #0x12345678:32,@er1-" +gdb_test "x" "sub.l\t#0x12345678(:32|),@\\(0x9abc(:16|),er1\\)" \ + "sub.l #0x12345678:32,@(0x9abc:16,er1)" +gdb_test "x" "sub.l\t#0x12345678(:32|),@\\(0x9abcdef0(:32|),er1\\)" \ + "sub.l #0x12345678:32,@(0x9abcdef0:32,er1)" +gdb_test "x" "sub.l\t#0x12345678(:32|),@\\(0x9abc(:16|),r2l.b\\)" \ + "sub.l #0x12345678:32,@(0x9abc:16,r2l.b)" +gdb_test "x" "sub.l\t#0x12345678(:32|),@\\(0x9abc(:16|),r2.w\\)" \ + "sub.l #0x12345678:32,@(0x9abc:16,r2.w)" +gdb_test "x" "sub.l\t#0x12345678(:32|),@\\(0x9abc(:16|),er2.l\\)" \ + "sub.l #0x12345678:32,@(0x9abc:16,er2.l)" +gdb_test "x" "sub.l\t#0x12345678(:32|),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "sub.l #0x12345678:32,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "sub.l\t#0x12345678(:32|),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "sub.l #0x12345678:32,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "sub.l\t#0x12345678(:32|),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "sub.l #0x12345678:32,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "sub.l\t#0x12345678(:32|),@0x9abc(:16|)" \ + "sub.l #0x12345678:32,@0x9abc:16" +gdb_test "x" "sub.l\t#0x12345678(:32|),@0x9abcdef0(:32|)" \ + "sub.l #0x12345678:32,@0x9abcdef0:32" +gdb_test "x" "sub.l\t#0x1234(:16|),@er1" \ + "sub.l #0x1234:16,@er1" +gdb_test "x" "sub.l\t#0x1234(:16|),@\\(0xc(:2|),er1\\)" \ + "sub.l #0x1234:16,@(0xc:2,er1)" +gdb_test "x" "sub.l\t#0x1234(:16|),@er1\\+" \ + "sub.l #0x1234:16,@er1+" +gdb_test "x" "sub.l\t#0x1234(:16|),@-er1" \ + "sub.l #0x1234:16,@-er1" +gdb_test "x" "sub.l\t#0x1234(:16|),@\\+er1" \ + "sub.l #0x1234:16,@+er1" +gdb_test "x" "sub.l\t#0x1234(:16|),@er1-" \ + "sub.l #0x1234:16,@er1-" +gdb_test "x" "sub.l\t#0x1234(:16|),@\\(0x9abc(:16|),er1\\)" \ + "sub.l #0x1234:16,@(0x9abc:16,er1)" +gdb_test "x" "sub.l\t#0x1234(:16|),@\\(0x9abcdef0(:32|),er1\\)" \ + "sub.l #0x1234:16,@(0x9abcdef0:32,er1)" +gdb_test "x" "sub.l\t#0x1234(:16|),@\\(0x9abc(:16|),r2l.b\\)" \ + "sub.l #0x1234:16,@(0x9abc:16,r2l.b)" +gdb_test "x" "sub.l\t#0x1234(:16|),@\\(0x9abc(:16|),r2.w\\)" \ + "sub.l #0x1234:16,@(0x9abc:16,r2.w)" +gdb_test "x" "sub.l\t#0x1234(:16|),@\\(0x9abc(:16|),er2.l\\)" \ + "sub.l #0x1234:16,@(0x9abc:16,er2.l)" +gdb_test "x" "sub.l\t#0x1234(:16|),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "sub.l #0x1234:16,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "sub.l\t#0x1234(:16|),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "sub.l #0x1234:16,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "sub.l\t#0x1234(:16|),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "sub.l #0x1234:16,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "sub.l\t#0x1234(:16|),@0x9abc(:16|)" \ + "sub.l #0x1234:16,@0x9abc:16" +gdb_test "x" "sub.l\t#0x1234(:16|),@0x9abcdef0(:32|)" \ + "sub.l #0x1234:16,@0x9abcdef0:32" +gdb_test "x" "sub.l\ter3,er1" \ + "sub.l er3,er1" +gdb_test "x" "sub.l\ter3,@er1" \ + "sub.l er3,@er1" +gdb_test "x" "sub.l\ter3,@\\(0xc(:2|),er1\\)" \ + "sub.l er3,@(0xc:2,er1)" +gdb_test "x" "sub.l\ter3,@er1\\+" \ + "sub.l er3,@er1+" +gdb_test "x" "sub.l\ter3,@-er1" \ + "sub.l er3,@-er1" +gdb_test "x" "sub.l\ter3,@\\+er1" \ + "sub.l er3,@+er1" +gdb_test "x" "sub.l\ter3,@er1-" \ + "sub.l er3,@er1-" +gdb_test "x" "sub.l\ter3,@\\(0x1234(:16|),er1\\)" \ + "sub.l er3,@(0x1234:16,er1)" +gdb_test "x" "sub.l\ter3,@\\(0x12345678(:32|),er1\\)" \ + "sub.l er3,@(0x12345678:32,er1)" +gdb_test "x" "sub.l\ter3,@\\(0x1234(:16|),r2l.b\\)" \ + "sub.l er3,@(0x1234:16,r2l.b)" +gdb_test "x" "sub.l\ter3,@\\(0x1234(:16|),r2.w\\)" \ + "sub.l er3,@(0x1234:16,r2.w)" +gdb_test "x" "sub.l\ter3,@\\(0x1234(:16|),er2.l\\)" \ + "sub.l er3,@(0x1234:16,er2.l)" +gdb_test "x" "sub.l\ter3,@\\(0x12345678(:32|),r2l.b\\)" \ + "sub.l er3,@(0x12345678:32,r2l.b)" +gdb_test "x" "sub.l\ter3,@\\(0x12345678(:32|),r2.w\\)" \ + "sub.l er3,@(0x12345678:32,r2.w)" +gdb_test "x" "sub.l\ter3,@\\(0x12345678(:32|),er2.l\\)" \ + "sub.l er3,@(0x12345678:32,er2.l)" +gdb_test "x" "sub.l\ter3,@0x1234(:16|)" \ + "sub.l er3,@0x1234:16" +gdb_test "x" "sub.l\ter3,@0x12345678(:32|)" \ + "sub.l er3,@0x12345678:32" +gdb_test "x" "sub.l\t@er3,er1" \ + "sub.l @er3,er1" +gdb_test "x" "sub.l\t@\\(0xc(:2|),er3\\),er1" \ + "sub.l @(0xc:2,er3),er1" +gdb_test "x" "sub.l\t@er3\\+,er1" \ + "sub.l @er3+,er1" +gdb_test "x" "sub.l\t@-er3,er1" \ + "sub.l @-er3,er1" +gdb_test "x" "sub.l\t@\\+er3,er1" \ + "sub.l @+er3,er1" +gdb_test "x" "sub.l\t@er3-,er1" \ + "sub.l @er3-,er1" +gdb_test "x" "sub.l\t@\\(0x1234(:16|),er1\\),er1" \ + "sub.l @(0x1234:16,er1),er1" +gdb_test "x" "sub.l\t@\\(0x12345678(:32|),er1\\),er1" \ + "sub.l @(0x12345678:32,er1),er1" +gdb_test "x" "sub.l\t@\\(0x1234(:16|),r2l.b\\),er1" \ + "sub.l @(0x1234:16,r2l.b),er1" +gdb_test "x" "sub.l\t@\\(0x1234(:16|),r2.w\\),er1" \ + "sub.l @(0x1234:16,r2.w),er1" +gdb_test "x" "sub.l\t@\\(0x1234(:16|),er2.l\\),er1" \ + "sub.l @(0x1234:16,er2.l),er1" +gdb_test "x" "sub.l\t@\\(0x12345678(:32|),r2l.b\\),er1" \ + "sub.l @(0x12345678:32,r2l.b),er1" +gdb_test "x" "sub.l\t@\\(0x12345678(:32|),r2.w\\),er1" \ + "sub.l @(0x12345678:32,r2.w),er1" +gdb_test "x" "sub.l\t@\\(0x12345678(:32|),er2.l\\),er1" \ + "sub.l @(0x12345678:32,er2.l),er1" +gdb_test "x" "sub.l\t@0x1234(:16|),er1" \ + "sub.l @0x1234:16,er1" +gdb_test "x" "sub.l\t@0x12345678(:32|),er1" \ + "sub.l @0x12345678:32,er1" +gdb_test "x" "sub.l\t@er3,@er1" \ + "sub.l @er3,@er1" +gdb_test "x" "sub.l\t@er3,@\\(0xc(:2|),er1\\)" \ + "sub.l @er3,@(0xc:2,er1)" +gdb_test "x" "sub.l\t@er3,@-er1" \ + "sub.l @er3,@-er1" +gdb_test "x" "sub.l\t@er3,@er1\\+" \ + "sub.l @er3,@er1+" +gdb_test "x" "sub.l\t@er3,@er1-" \ + "sub.l @er3,@er1-" +gdb_test "x" "sub.l\t@er3,@\\+er1" \ + "sub.l @er3,@+er1" +gdb_test "x" "sub.l\t@er3,@\\(0x9abc(:16|),er1\\)" \ + "sub.l @er3,@(0x9abc:16,er1)" +gdb_test "x" "sub.l\t@er3,@\\(0x9abcdef0(:32|),er1\\)" \ + "sub.l @er3,@(0x9abcdef0:32,er1)" +gdb_test "x" "sub.l\t@er3,@\\(0x9abc(:16|),r2l.b\\)" \ + "sub.l @er3,@(0x9abc:16,r2l.b)" +gdb_test "x" "sub.l\t@er3,@\\(0x9abc(:16|),r2.w\\)" \ + "sub.l @er3,@(0x9abc:16,r2.w)" +gdb_test "x" "sub.l\t@er3,@\\(0x9abc(:16|),er2.l\\)" \ + "sub.l @er3,@(0x9abc:16,er2.l)" +gdb_test "x" "sub.l\t@er3,@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "sub.l @er3,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "sub.l\t@er3,@\\(0x9abcdef0(:32|),r2.w\\)" \ + "sub.l @er3,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "sub.l\t@er3,@\\(0x9abcdef0(:32|),er2.l\\)" \ + "sub.l @er3,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "sub.l\t@er3,@0x9abc(:16|)" \ + "sub.l @er3,@0x9abc:16" +gdb_test "x" "sub.l\t@er3,@0x9abcdef0(:32|)" \ + "sub.l @er3,@0x9abcdef0:32" +gdb_test "x" "sub.l\t@\\(0xc(:2|),er3\\),@er1" \ + "sub.l @(0xc:2,er3),@er1" +gdb_test "x" "sub.l\t@\\(0xc(:2|),er3\\),@\\(0xc(:2|),er1\\)" \ + "sub.l @(0xc:2,er3),@(0xc:2,er1)" +gdb_test "x" "sub.l\t@\\(0xc(:2|),er3\\),@-er1" \ + "sub.l @(0xc:2,er3),@-er1" +gdb_test "x" "sub.l\t@\\(0xc(:2|),er3\\),@er1\\+" \ + "sub.l @(0xc:2,er3),@er1+" +gdb_test "x" "sub.l\t@\\(0xc(:2|),er3\\),@er1-" \ + "sub.l @(0xc:2,er3),@er1-" +gdb_test "x" "sub.l\t@\\(0xc(:2|),er3\\),@\\+er1" \ + "sub.l @(0xc:2,er3),@+er1" +gdb_test "x" "sub.l\t@\\(0xc(:2|),er3\\),@\\(0x9abc(:16|),er1\\)" \ + "sub.l @(0xc:2,er3),@(0x9abc:16,er1)" +gdb_test "x" "sub.l\t@\\(0xc(:2|),er3\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "sub.l @(0xc:2,er3),@(0x9abcdef0:32,er1)" +gdb_test "x" "sub.l\t@\\(0xc(:2|),er3\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "sub.l @(0xc:2,er3),@(0x9abc:16,r2l.b)" +gdb_test "x" "sub.l\t@\\(0xc(:2|),er3\\),@\\(0x9abc(:16|),r2.w\\)" \ + "sub.l @(0xc:2,er3),@(0x9abc:16,r2.w)" +gdb_test "x" "sub.l\t@\\(0xc(:2|),er3\\),@\\(0x9abc(:16|),er2.l\\)" \ + "sub.l @(0xc:2,er3),@(0x9abc:16,er2.l)" +gdb_test "x" "sub.l\t@\\(0xc(:2|),er3\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "sub.l @(0xc:2,er3),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "sub.l\t@\\(0xc(:2|),er3\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "sub.l @(0xc:2,er3),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "sub.l\t@\\(0xc(:2|),er3\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "sub.l @(0xc:2,er3),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "sub.l\t@\\(0xc(:2|),er3\\),@0x9abc(:16|)" \ + "sub.l @(0xc:2,er3),@0x9abc:16" +gdb_test "x" "sub.l\t@\\(0xc(:2|),er3\\),@0x9abcdef0(:32|)" \ + "sub.l @(0xc:2,er3),@0x9abcdef0:32" +gdb_test "x" "sub.l\t@-er3,@er1" \ + "sub.l @-er3,@er1" +gdb_test "x" "sub.l\t@-er3,@\\(0xc(:2|),er1\\)" \ + "sub.l @-er3,@(0xc:2,er1)" +gdb_test "x" "sub.l\t@-er3,@-er1" \ + "sub.l @-er3,@-er1" +gdb_test "x" "sub.l\t@-er3,@er1\\+" \ + "sub.l @-er3,@er1+" +gdb_test "x" "sub.l\t@-er3,@er1-" \ + "sub.l @-er3,@er1-" +gdb_test "x" "sub.l\t@-er3,@\\+er1" \ + "sub.l @-er3,@+er1" +gdb_test "x" "sub.l\t@-er3,@\\(0x9abc(:16|),er1\\)" \ + "sub.l @-er3,@(0x9abc:16,er1)" +gdb_test "x" "sub.l\t@-er3,@\\(0x9abcdef0(:32|),er1\\)" \ + "sub.l @-er3,@(0x9abcdef0:32,er1)" +gdb_test "x" "sub.l\t@-er3,@\\(0x9abc(:16|),r2l.b\\)" \ + "sub.l @-er3,@(0x9abc:16,r2l.b)" +gdb_test "x" "sub.l\t@-er3,@\\(0x9abc(:16|),r2.w\\)" \ + "sub.l @-er3,@(0x9abc:16,r2.w)" +gdb_test "x" "sub.l\t@-er3,@\\(0x9abc(:16|),er2.l\\)" \ + "sub.l @-er3,@(0x9abc:16,er2.l)" +gdb_test "x" "sub.l\t@-er3,@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "sub.l @-er3,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "sub.l\t@-er3,@\\(0x9abcdef0(:32|),r2.w\\)" \ + "sub.l @-er3,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "sub.l\t@-er3,@\\(0x9abcdef0(:32|),er2.l\\)" \ + "sub.l @-er3,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "sub.l\t@-er3,@0x9abc(:16|)" \ + "sub.l @-er3,@0x9abc:16" +gdb_test "x" "sub.l\t@-er3,@0x9abcdef0(:32|)" \ + "sub.l @-er3,@0x9abcdef0:32" +gdb_test "x" "sub.l\t@er3\\+,@er1" \ + "sub.l @er3+,@er1" +gdb_test "x" "sub.l\t@er3\\+,@\\(0xc(:2|),er1\\)" \ + "sub.l @er3+,@(0xc:2,er1)" +gdb_test "x" "sub.l\t@er3\\+,@-er1" \ + "sub.l @er3+,@-er1" +gdb_test "x" "sub.l\t@er3\\+,@er1\\+" \ + "sub.l @er3+,@er1+" +gdb_test "x" "sub.l\t@er3\\+,@er1-" \ + "sub.l @er3+,@er1-" +gdb_test "x" "sub.l\t@er3\\+,@\\+er1" \ + "sub.l @er3+,@+er1" +gdb_test "x" "sub.l\t@er3\\+,@\\(0x9abc(:16|),er1\\)" \ + "sub.l @er3+,@(0x9abc:16,er1)" +gdb_test "x" "sub.l\t@er3\\+,@\\(0x9abcdef0(:32|),er1\\)" \ + "sub.l @er3+,@(0x9abcdef0:32,er1)" +gdb_test "x" "sub.l\t@er3\\+,@\\(0x9abc(:16|),r2l.b\\)" \ + "sub.l @er3+,@(0x9abc:16,r2l.b)" +gdb_test "x" "sub.l\t@er3\\+,@\\(0x9abc(:16|),r2.w\\)" \ + "sub.l @er3+,@(0x9abc:16,r2.w)" +gdb_test "x" "sub.l\t@er3\\+,@\\(0x9abc(:16|),er2.l\\)" \ + "sub.l @er3+,@(0x9abc:16,er2.l)" +gdb_test "x" "sub.l\t@er3\\+,@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "sub.l @er3+,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "sub.l\t@er3\\+,@\\(0x9abcdef0(:32|),r2.w\\)" \ + "sub.l @er3+,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "sub.l\t@er3\\+,@\\(0x9abcdef0(:32|),er2.l\\)" \ + "sub.l @er3+,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "sub.l\t@er3\\+,@0x9abc(:16|)" \ + "sub.l @er3+,@0x9abc:16" +gdb_test "x" "sub.l\t@er3\\+,@0x9abcdef0(:32|)" \ + "sub.l @er3+,@0x9abcdef0:32" +gdb_test "x" "sub.l\t@er3-,@er1" \ + "sub.l @er3-,@er1" +gdb_test "x" "sub.l\t@er3-,@\\(0xc(:2|),er1\\)" \ + "sub.l @er3-,@(0xc:2,er1)" +gdb_test "x" "sub.l\t@er3-,@-er1" \ + "sub.l @er3-,@-er1" +gdb_test "x" "sub.l\t@er3-,@er1\\+" \ + "sub.l @er3-,@er1+" +gdb_test "x" "sub.l\t@er3-,@er1-" \ + "sub.l @er3-,@er1-" +gdb_test "x" "sub.l\t@er3-,@\\+er1" \ + "sub.l @er3-,@+er1" +gdb_test "x" "sub.l\t@er3-,@\\(0x9abc(:16|),er1\\)" \ + "sub.l @er3-,@(0x9abc:16,er1)" +gdb_test "x" "sub.l\t@er3-,@\\(0x9abcdef0(:32|),er1\\)" \ + "sub.l @er3-,@(0x9abcdef0:32,er1)" +gdb_test "x" "sub.l\t@er3-,@\\(0x9abc(:16|),r2l.b\\)" \ + "sub.l @er3-,@(0x9abc:16,r2l.b)" +gdb_test "x" "sub.l\t@er3-,@\\(0x9abc(:16|),r2.w\\)" \ + "sub.l @er3-,@(0x9abc:16,r2.w)" +gdb_test "x" "sub.l\t@er3-,@\\(0x9abc(:16|),er2.l\\)" \ + "sub.l @er3-,@(0x9abc:16,er2.l)" +gdb_test "x" "sub.l\t@er3-,@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "sub.l @er3-,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "sub.l\t@er3-,@\\(0x9abcdef0(:32|),r2.w\\)" \ + "sub.l @er3-,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "sub.l\t@er3-,@\\(0x9abcdef0(:32|),er2.l\\)" \ + "sub.l @er3-,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "sub.l\t@er3-,@0x9abc(:16|)" \ + "sub.l @er3-,@0x9abc:16" +gdb_test "x" "sub.l\t@er3-,@0x9abcdef0(:32|)" \ + "sub.l @er3-,@0x9abcdef0:32" +gdb_test "x" "sub.l\t@\\+er3,@er1" \ + "sub.l @+er3,@er1" +gdb_test "x" "sub.l\t@\\+er3,@\\(0xc(:2|),er1\\)" \ + "sub.l @+er3,@(0xc:2,er1)" +gdb_test "x" "sub.l\t@\\+er3,@-er1" \ + "sub.l @+er3,@-er1" +gdb_test "x" "sub.l\t@\\+er3,@er1\\+" \ + "sub.l @+er3,@er1+" +gdb_test "x" "sub.l\t@\\+er3,@er1-" \ + "sub.l @+er3,@er1-" +gdb_test "x" "sub.l\t@\\+er3,@\\+er1" \ + "sub.l @+er3,@+er1" +gdb_test "x" "sub.l\t@\\+er3,@\\(0x9abc(:16|),er1\\)" \ + "sub.l @+er3,@(0x9abc:16,er1)" +gdb_test "x" "sub.l\t@\\+er3,@\\(0x9abcdef0(:32|),er1\\)" \ + "sub.l @+er3,@(0x9abcdef0:32,er1)" +gdb_test "x" "sub.l\t@\\+er3,@\\(0x9abc(:16|),r2l.b\\)" \ + "sub.l @+er3,@(0x9abc:16,r2l.b)" +gdb_test "x" "sub.l\t@\\+er3,@\\(0x9abc(:16|),r2.w\\)" \ + "sub.l @+er3,@(0x9abc:16,r2.w)" +gdb_test "x" "sub.l\t@\\+er3,@\\(0x9abc(:16|),er2.l\\)" \ + "sub.l @+er3,@(0x9abc:16,er2.l)" +gdb_test "x" "sub.l\t@\\+er3,@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "sub.l @+er3,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "sub.l\t@\\+er3,@\\(0x9abcdef0(:32|),r2.w\\)" \ + "sub.l @+er3,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "sub.l\t@\\+er3,@\\(0x9abcdef0(:32|),er2.l\\)" \ + "sub.l @+er3,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "sub.l\t@\\+er3,@0x9abc(:16|)" \ + "sub.l @+er3,@0x9abc:16" +gdb_test "x" "sub.l\t@\\+er3,@0x9abcdef0(:32|)" \ + "sub.l @+er3,@0x9abcdef0:32" +gdb_test "x" "sub.l\t@\\(0x1234(:16|),er3\\),@er1" \ + "sub.l @(0x1234:16,er3),@er1" +gdb_test "x" "sub.l\t@\\(0x1234(:16|),er3\\),@\\(0xc(:2|),er1\\)" \ + "sub.l @(0x1234:16,er3),@(0xc:2,er1)" +gdb_test "x" "sub.l\t@\\(0x1234(:16|),er3\\),@-er1" \ + "sub.l @(0x1234:16,er3),@-er1" +gdb_test "x" "sub.l\t@\\(0x1234(:16|),er3\\),@er1\\+" \ + "sub.l @(0x1234:16,er3),@er1+" +gdb_test "x" "sub.l\t@\\(0x1234(:16|),er3\\),@er1-" \ + "sub.l @(0x1234:16,er3),@er1-" +gdb_test "x" "sub.l\t@\\(0x1234(:16|),er3\\),@\\+er1" \ + "sub.l @(0x1234:16,er3),@+er1" +gdb_test "x" "sub.l\t@\\(0x1234(:16|),er3\\),@\\(0x9abc(:16|),er1\\)" \ + "sub.l @(0x1234:16,er3),@(0x9abc:16,er1)" +gdb_test "x" "sub.l\t@\\(0x1234(:16|),er3\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "sub.l @(0x1234:16,er3),@(0x9abcdef0:32,er1)" +gdb_test "x" "sub.l\t@\\(0x1234(:16|),er3\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "sub.l @(0x1234:16,er3),@(0x9abc:16,r2l.b)" +gdb_test "x" "sub.l\t@\\(0x1234(:16|),er3\\),@\\(0x9abc(:16|),r2.w\\)" \ + "sub.l @(0x1234:16,er3),@(0x9abc:16,r2.w)" +gdb_test "x" "sub.l\t@\\(0x1234(:16|),er3\\),@\\(0x9abc(:16|),er2.l\\)" \ + "sub.l @(0x1234:16,er3),@(0x9abc:16,er2.l)" +gdb_test "x" "sub.l\t@\\(0x1234(:16|),er3\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "sub.l @(0x1234:16,er3),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "sub.l\t@\\(0x1234(:16|),er3\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "sub.l @(0x1234:16,er3),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "sub.l\t@\\(0x1234(:16|),er3\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "sub.l @(0x1234:16,er3),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "sub.l\t@\\(0x1234(:16|),er3\\),@0x9abc(:16|)" \ + "sub.l @(0x1234:16,er3),@0x9abc:16" +gdb_test "x" "sub.l\t@\\(0x1234(:16|),er3\\),@0x9abcdef0(:32|)" \ + "sub.l @(0x1234:16,er3),@0x9abcdef0:32" +gdb_test "x" "sub.l\t@\\(0x12345678(:32|),er3\\),@er1" \ + "sub.l @(0x12345678:32,er3),@er1" +gdb_test "x" "sub.l\t@\\(0x12345678(:32|),er3\\),@\\(0xc(:2|),er1\\)" \ + "sub.l @(0x12345678:32,er3),@(0xc:2,er1)" +gdb_test "x" "sub.l\t@\\(0x12345678(:32|),er3\\),@-er1" \ + "sub.l @(0x12345678:32,er3),@-er1" +gdb_test "x" "sub.l\t@\\(0x12345678(:32|),er3\\),@er1\\+" \ + "sub.l @(0x12345678:32,er3),@er1+" +gdb_test "x" "sub.l\t@\\(0x12345678(:32|),er3\\),@er1-" \ + "sub.l @(0x12345678:32,er3),@er1-" +gdb_test "x" "sub.l\t@\\(0x12345678(:32|),er3\\),@\\+er1" \ + "sub.l @(0x12345678:32,er3),@+er1" +gdb_test "x" "sub.l\t@\\(0x12345678(:32|),er3\\),@\\(0x9abc(:16|),er1\\)" \ + "sub.l @(0x12345678:32,er3),@(0x9abc:16,er1)" +gdb_test "x" "sub.l\t@\\(0x12345678(:32|),er3\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "sub.l @(0x12345678:32,er3),@(0x9abcdef0:32,er1)" +gdb_test "x" "sub.l\t@\\(0x12345678(:32|),er3\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "sub.l @(0x12345678:32,er3),@(0x9abc:16,r2l.b)" +gdb_test "x" "sub.l\t@\\(0x12345678(:32|),er3\\),@\\(0x9abc(:16|),r2.w\\)" \ + "sub.l @(0x12345678:32,er3),@(0x9abc:16,r2.w)" +gdb_test "x" "sub.l\t@\\(0x12345678(:32|),er3\\),@\\(0x9abc(:16|),er2.l\\)" \ + "sub.l @(0x12345678:32,er3),@(0x9abc:16,er2.l)" +gdb_test "x" "sub.l\t@\\(0x12345678(:32|),er3\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "sub.l @(0x12345678:32,er3),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "sub.l\t@\\(0x12345678(:32|),er3\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "sub.l @(0x12345678:32,er3),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "sub.l\t@\\(0x12345678(:32|),er3\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "sub.l @(0x12345678:32,er3),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "sub.l\t@\\(0x12345678(:32|),er3\\),@0x9abc(:16|)" \ + "sub.l @(0x12345678:32,er3),@0x9abc:16" +gdb_test "x" "sub.l\t@\\(0x12345678(:32|),er3\\),@0x9abcdef0(:32|)" \ + "sub.l @(0x12345678:32,er3),@0x9abcdef0:32" +gdb_test "x" "sub.l\t@\\(0x1234(:16|),r3l.b\\),@er1" \ + "sub.l @(0x1234:16,r3l.b),@er1" +gdb_test "x" "sub.l\t@\\(0x1234(:16|),r3l.b\\),@\\(0xc(:2|),er1\\)" \ + "sub.l @(0x1234:16,r3l.b),@(0xc:2,er1)" +gdb_test "x" "sub.l\t@\\(0x1234(:16|),r3l.b\\),@-er1" \ + "sub.l @(0x1234:16,r3l.b),@-er1" +gdb_test "x" "sub.l\t@\\(0x1234(:16|),r3l.b\\),@er1\\+" \ + "sub.l @(0x1234:16,r3l.b),@er1+" +gdb_test "x" "sub.l\t@\\(0x1234(:16|),r3l.b\\),@er1-" \ + "sub.l @(0x1234:16,r3l.b),@er1-" +gdb_test "x" "sub.l\t@\\(0x1234(:16|),r3l.b\\),@\\+er1" \ + "sub.l @(0x1234:16,r3l.b),@+er1" +gdb_test "x" "sub.l\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abc(:16|),er1\\)" \ + "sub.l @(0x1234:16,r3l.b),@(0x9abc:16,er1)" +gdb_test "x" "sub.l\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "sub.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1)" +gdb_test "x" "sub.l\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "sub.l @(0x1234:16,r3l.b),@(0x9abc:16,r2l.b)" +gdb_test "x" "sub.l\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abc(:16|),r2.w\\)" \ + "sub.l @(0x1234:16,r3l.b),@(0x9abc:16,r2.w)" +gdb_test "x" "sub.l\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abc(:16|),er2.l\\)" \ + "sub.l @(0x1234:16,r3l.b),@(0x9abc:16,er2.l)" +gdb_test "x" "sub.l\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "sub.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "sub.l\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "sub.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "sub.l\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "sub.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "sub.l\t@\\(0x1234(:16|),r3l.b\\),@0x9abc(:16|)" \ + "sub.l @(0x1234:16,r3l.b),@0x9abc:16" +gdb_test "x" "sub.l\t@\\(0x1234(:16|),r3l.b\\),@0x9abcdef0(:32|)" \ + "sub.l @(0x1234:16,r3l.b),@0x9abcdef0:32" +gdb_test "x" "sub.l\t@\\(0x1234(:16|),r3.w\\),@er1" \ + "sub.l @(0x1234:16,r3.w),@er1" +gdb_test "x" "sub.l\t@\\(0x1234(:16|),r3.w\\),@\\(0xc(:2|),er1\\)" \ + "sub.l @(0x1234:16,r3.w),@(0xc:2,er1)" +gdb_test "x" "sub.l\t@\\(0x1234(:16|),r3.w\\),@-er1" \ + "sub.l @(0x1234:16,r3.w),@-er1" +gdb_test "x" "sub.l\t@\\(0x1234(:16|),r3.w\\),@er1\\+" \ + "sub.l @(0x1234:16,r3.w),@er1+" +gdb_test "x" "sub.l\t@\\(0x1234(:16|),r3.w\\),@er1-" \ + "sub.l @(0x1234:16,r3.w),@er1-" +gdb_test "x" "sub.l\t@\\(0x1234(:16|),r3.w\\),@\\+er1" \ + "sub.l @(0x1234:16,r3.w),@+er1" +gdb_test "x" "sub.l\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abc(:16|),er1\\)" \ + "sub.l @(0x1234:16,r3.w),@(0x9abc:16,er1)" +gdb_test "x" "sub.l\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "sub.l @(0x1234:16,r3.w),@(0x9abcdef0:32,er1)" +gdb_test "x" "sub.l\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "sub.l @(0x1234:16,r3.w),@(0x9abc:16,r2l.b)" +gdb_test "x" "sub.l\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abc(:16|),r2.w\\)" \ + "sub.l @(0x1234:16,r3.w),@(0x9abc:16,r2.w)" +gdb_test "x" "sub.l\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abc(:16|),er2.l\\)" \ + "sub.l @(0x1234:16,r3.w),@(0x9abc:16,er2.l)" +gdb_test "x" "sub.l\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "sub.l @(0x1234:16,r3.w),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "sub.l\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "sub.l @(0x1234:16,r3.w),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "sub.l\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "sub.l @(0x1234:16,r3.w),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "sub.l\t@\\(0x1234(:16|),r3.w\\),@0x9abc(:16|)" \ + "sub.l @(0x1234:16,r3.w),@0x9abc:16" +gdb_test "x" "sub.l\t@\\(0x1234(:16|),r3.w\\),@0x9abcdef0(:32|)" \ + "sub.l @(0x1234:16,r3.w),@0x9abcdef0:32" +gdb_test "x" "sub.l\t@\\(0x1234(:16|),er3.l\\),@er1" \ + "sub.l @(0x1234:16,er3.l),@er1" +gdb_test "x" "sub.l\t@\\(0x1234(:16|),er3.l\\),@\\(0xc(:2|),er1\\)" \ + "sub.l @(0x1234:16,er3.l),@(0xc:2,er1)" +gdb_test "x" "sub.l\t@\\(0x1234(:16|),er3.l\\),@-er1" \ + "sub.l @(0x1234:16,er3.l),@-er1" +gdb_test "x" "sub.l\t@\\(0x1234(:16|),er3.l\\),@er1\\+" \ + "sub.l @(0x1234:16,er3.l),@er1+" +gdb_test "x" "sub.l\t@\\(0x1234(:16|),er3.l\\),@er1-" \ + "sub.l @(0x1234:16,er3.l),@er1-" +gdb_test "x" "sub.l\t@\\(0x1234(:16|),er3.l\\),@\\+er1" \ + "sub.l @(0x1234:16,er3.l),@+er1" +gdb_test "x" "sub.l\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abc(:16|),er1\\)" \ + "sub.l @(0x1234:16,er3.l),@(0x9abc:16,er1)" +gdb_test "x" "sub.l\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "sub.l @(0x1234:16,er3.l),@(0x9abcdef0:32,er1)" +gdb_test "x" "sub.l\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "sub.l @(0x1234:16,er3.l),@(0x9abc:16,r2l.b)" +gdb_test "x" "sub.l\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abc(:16|),r2.w\\)" \ + "sub.l @(0x1234:16,er3.l),@(0x9abc:16,r2.w)" +gdb_test "x" "sub.l\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abc(:16|),er2.l\\)" \ + "sub.l @(0x1234:16,er3.l),@(0x9abc:16,er2.l)" +gdb_test "x" "sub.l\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "sub.l @(0x1234:16,er3.l),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "sub.l\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "sub.l @(0x1234:16,er3.l),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "sub.l\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "sub.l @(0x1234:16,er3.l),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "sub.l\t@\\(0x1234(:16|),er3.l\\),@0x9abc(:16|)" \ + "sub.l @(0x1234:16,er3.l),@0x9abc:16" +gdb_test "x" "sub.l\t@\\(0x1234(:16|),er3.l\\),@0x9abcdef0(:32|)" \ + "sub.l @(0x1234:16,er3.l),@0x9abcdef0:32" +gdb_test "x" "sub.l\t@\\(0x12345678(:32|),r3l.b\\),@er1" \ + "sub.l @(0x12345678:32,r3l.b),@er1" +gdb_test "x" "sub.l\t@\\(0x12345678(:32|),r3l.b\\),@\\(0xc(:2|),er1\\)" \ + "sub.l @(0x12345678:32,r3l.b),@(0xc:2,er1)" +gdb_test "x" "sub.l\t@\\(0x12345678(:32|),r3l.b\\),@-er1" \ + "sub.l @(0x12345678:32,r3l.b),@-er1" +gdb_test "x" "sub.l\t@\\(0x12345678(:32|),r3l.b\\),@er1\\+" \ + "sub.l @(0x12345678:32,r3l.b),@er1+" +gdb_test "x" "sub.l\t@\\(0x12345678(:32|),r3l.b\\),@er1-" \ + "sub.l @(0x12345678:32,r3l.b),@er1-" +gdb_test "x" "sub.l\t@\\(0x12345678(:32|),r3l.b\\),@\\+er1" \ + "sub.l @(0x12345678:32,r3l.b),@+er1" +gdb_test "x" "sub.l\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abc(:16|),er1\\)" \ + "sub.l @(0x12345678:32,r3l.b),@(0x9abc:16,er1)" +gdb_test "x" "sub.l\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "sub.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1)" +gdb_test "x" "sub.l\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "sub.l @(0x12345678:32,r3l.b),@(0x9abc:16,r2l.b)" +gdb_test "x" "sub.l\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abc(:16|),r2.w\\)" \ + "sub.l @(0x12345678:32,r3l.b),@(0x9abc:16,r2.w)" +gdb_test "x" "sub.l\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abc(:16|),er2.l\\)" \ + "sub.l @(0x12345678:32,r3l.b),@(0x9abc:16,er2.l)" +gdb_test "x" "sub.l\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "sub.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "sub.l\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "sub.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "sub.l\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "sub.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "sub.l\t@\\(0x12345678(:32|),r3l.b\\),@0x9abc(:16|)" \ + "sub.l @(0x12345678:32,r3l.b),@0x9abc:16" +gdb_test "x" "sub.l\t@\\(0x12345678(:32|),r3l.b\\),@0x9abcdef0(:32|)" \ + "sub.l @(0x12345678:32,r3l.b),@0x9abcdef0:32" +gdb_test "x" "sub.l\t@\\(0x12345678(:32|),r3.w\\),@er1" \ + "sub.l @(0x12345678:32,r3.w),@er1" +gdb_test "x" "sub.l\t@\\(0x12345678(:32|),r3.w\\),@\\(0xc(:2|),er1\\)" \ + "sub.l @(0x12345678:32,r3.w),@(0xc:2,er1)" +gdb_test "x" "sub.l\t@\\(0x12345678(:32|),r3.w\\),@-er1" \ + "sub.l @(0x12345678:32,r3.w),@-er1" +gdb_test "x" "sub.l\t@\\(0x12345678(:32|),r3.w\\),@er1\\+" \ + "sub.l @(0x12345678:32,r3.w),@er1+" +gdb_test "x" "sub.l\t@\\(0x12345678(:32|),r3.w\\),@er1-" \ + "sub.l @(0x12345678:32,r3.w),@er1-" +gdb_test "x" "sub.l\t@\\(0x12345678(:32|),r3.w\\),@\\+er1" \ + "sub.l @(0x12345678:32,r3.w),@+er1" +gdb_test "x" "sub.l\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abc(:16|),er1\\)" \ + "sub.l @(0x12345678:32,r3.w),@(0x9abc:16,er1)" +gdb_test "x" "sub.l\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "sub.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1)" +gdb_test "x" "sub.l\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "sub.l @(0x12345678:32,r3.w),@(0x9abc:16,r2l.b)" +gdb_test "x" "sub.l\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abc(:16|),r2.w\\)" \ + "sub.l @(0x12345678:32,r3.w),@(0x9abc:16,r2.w)" +gdb_test "x" "sub.l\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abc(:16|),er2.l\\)" \ + "sub.l @(0x12345678:32,r3.w),@(0x9abc:16,er2.l)" +gdb_test "x" "sub.l\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "sub.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "sub.l\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "sub.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "sub.l\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "sub.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "sub.l\t@\\(0x12345678(:32|),r3.w\\),@0x9abc(:16|)" \ + "sub.l @(0x12345678:32,r3.w),@0x9abc:16" +gdb_test "x" "sub.l\t@\\(0x12345678(:32|),r3.w\\),@0x9abcdef0(:32|)" \ + "sub.l @(0x12345678:32,r3.w),@0x9abcdef0:32" +gdb_test "x" "sub.l\t@\\(0x12345678(:32|),er3.l\\),@er1" \ + "sub.l @(0x12345678:32,er3.l),@er1" +gdb_test "x" "sub.l\t@\\(0x12345678(:32|),er3.l\\),@\\(0xc(:2|),er1\\)" \ + "sub.l @(0x12345678:32,er3.l),@(0xc:2,er1)" +gdb_test "x" "sub.l\t@\\(0x12345678(:32|),er3.l\\),@-er1" \ + "sub.l @(0x12345678:32,er3.l),@-er1" +gdb_test "x" "sub.l\t@\\(0x12345678(:32|),er3.l\\),@er1\\+" \ + "sub.l @(0x12345678:32,er3.l),@er1+" +gdb_test "x" "sub.l\t@\\(0x12345678(:32|),er3.l\\),@er1-" \ + "sub.l @(0x12345678:32,er3.l),@er1-" +gdb_test "x" "sub.l\t@\\(0x12345678(:32|),er3.l\\),@\\+er1" \ + "sub.l @(0x12345678:32,er3.l),@+er1" +gdb_test "x" "sub.l\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abc(:16|),er1\\)" \ + "sub.l @(0x12345678:32,er3.l),@(0x9abc:16,er1)" +gdb_test "x" "sub.l\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "sub.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1)" +gdb_test "x" "sub.l\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "sub.l @(0x12345678:32,er3.l),@(0x9abc:16,r2l.b)" +gdb_test "x" "sub.l\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abc(:16|),r2.w\\)" \ + "sub.l @(0x12345678:32,er3.l),@(0x9abc:16,r2.w)" +gdb_test "x" "sub.l\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abc(:16|),er2.l\\)" \ + "sub.l @(0x12345678:32,er3.l),@(0x9abc:16,er2.l)" +gdb_test "x" "sub.l\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "sub.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "sub.l\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "sub.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "sub.l\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "sub.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "sub.l\t@\\(0x12345678(:32|),er3.l\\),@0x9abc(:16|)" \ + "sub.l @(0x12345678:32,er3.l),@0x9abc:16" +gdb_test "x" "sub.l\t@\\(0x12345678(:32|),er3.l\\),@0x9abcdef0(:32|)" \ + "sub.l @(0x12345678:32,er3.l),@0x9abcdef0:32" +gdb_test "x" "sub.l\t@0x1234(:16|),@er1" \ + "sub.l @0x1234:16,@er1" +gdb_test "x" "sub.l\t@0x1234(:16|),@\\(0xc(:2|),er1\\)" \ + "sub.l @0x1234:16,@(0xc:2,er1)" +gdb_test "x" "sub.l\t@0x1234(:16|),@-er1" \ + "sub.l @0x1234:16,@-er1" +gdb_test "x" "sub.l\t@0x1234(:16|),@er1\\+" \ + "sub.l @0x1234:16,@er1+" +gdb_test "x" "sub.l\t@0x1234(:16|),@er1-" \ + "sub.l @0x1234:16,@er1-" +gdb_test "x" "sub.l\t@0x1234(:16|),@\\+er1" \ + "sub.l @0x1234:16,@+er1" +gdb_test "x" "sub.l\t@0x1234(:16|),@\\(0x9abc(:16|),er1\\)" \ + "sub.l @0x1234:16,@(0x9abc:16,er1)" +gdb_test "x" "sub.l\t@0x1234(:16|),@\\(0x9abcdef0(:32|),er1\\)" \ + "sub.l @0x1234:16,@(0x9abcdef0:32,er1)" +gdb_test "x" "sub.l\t@0x1234(:16|),@\\(0x9abc(:16|),r2l.b\\)" \ + "sub.l @0x1234:16,@(0x9abc:16,r2l.b)" +gdb_test "x" "sub.l\t@0x1234(:16|),@\\(0x9abc(:16|),r2.w\\)" \ + "sub.l @0x1234:16,@(0x9abc:16,r2.w)" +gdb_test "x" "sub.l\t@0x1234(:16|),@\\(0x9abc(:16|),er2.l\\)" \ + "sub.l @0x1234:16,@(0x9abc:16,er2.l)" +gdb_test "x" "sub.l\t@0x1234(:16|),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "sub.l @0x1234:16,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "sub.l\t@0x1234(:16|),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "sub.l @0x1234:16,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "sub.l\t@0x1234(:16|),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "sub.l @0x1234:16,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "sub.l\t@0x1234(:16|),@0x9abc(:16|)" \ + "sub.l @0x1234:16,@0x9abc:16" +gdb_test "x" "sub.l\t@0x1234(:16|),@0x9abcdef0(:32|)" \ + "sub.l @0x1234:16,@0x9abcdef0:32" +gdb_test "x" "sub.l\t@0x12345678(:32|),@er1" \ + "sub.l @0x12345678:32,@er1" +gdb_test "x" "sub.l\t@0x12345678(:32|),@\\(0xc(:2|),er1\\)" \ + "sub.l @0x12345678:32,@(0xc:2,er1)" +gdb_test "x" "sub.l\t@0x12345678(:32|),@-er1" \ + "sub.l @0x12345678:32,@-er1" +gdb_test "x" "sub.l\t@0x12345678(:32|),@er1\\+" \ + "sub.l @0x12345678:32,@er1+" +gdb_test "x" "sub.l\t@0x12345678(:32|),@er1-" \ + "sub.l @0x12345678:32,@er1-" +gdb_test "x" "sub.l\t@0x12345678(:32|),@\\+er1" \ + "sub.l @0x12345678:32,@+er1" +gdb_test "x" "sub.l\t@0x12345678(:32|),@\\(0x9abc(:16|),er1\\)" \ + "sub.l @0x12345678:32,@(0x9abc:16,er1)" +gdb_test "x" "sub.l\t@0x12345678(:32|),@\\(0x9abcdef0(:32|),er1\\)" \ + "sub.l @0x12345678:32,@(0x9abcdef0:32,er1)" +gdb_test "x" "sub.l\t@0x12345678(:32|),@\\(0x9abc(:16|),r2l.b\\)" \ + "sub.l @0x12345678:32,@(0x9abc:16,r2l.b)" +gdb_test "x" "sub.l\t@0x12345678(:32|),@\\(0x9abc(:16|),r2.w\\)" \ + "sub.l @0x12345678:32,@(0x9abc:16,r2.w)" +gdb_test "x" "sub.l\t@0x12345678(:32|),@\\(0x9abc(:16|),er2.l\\)" \ + "sub.l @0x12345678:32,@(0x9abc:16,er2.l)" +gdb_test "x" "sub.l\t@0x12345678(:32|),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "sub.l @0x12345678:32,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "sub.l\t@0x12345678(:32|),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "sub.l @0x12345678:32,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "sub.l\t@0x12345678(:32|),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "sub.l @0x12345678:32,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "sub.l\t@0x12345678(:32|),@0x9abc(:16|)" \ + "sub.l @0x12345678:32,@0x9abc:16" +gdb_test "x" "sub.l\t@0x12345678(:32|),@0x9abcdef0(:32|)" \ + "sub.l @0x12345678:32,@0x9abcdef0:32" diff --git a/gdb/testsuite/gdb.disasm/t04_sub.s b/gdb/testsuite/gdb.disasm/t04_sub.s new file mode 100644 index 0000000..e89b614 --- /dev/null +++ b/gdb/testsuite/gdb.disasm/t04_sub.s @@ -0,0 +1,977 @@ +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;arith_1 +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + .h8300sx + .text + .global _start +_start: + sub.b #0x12:8,@er1 ;7d10a112 + sub.b #0x12:8,@(0x3:2,er1) ;01776818a112 + sub.b #0x12:8,@er1+ ;01746c18a112 + sub.b #0x12:8,@-er1 ;01776c18a112 + sub.b #0x12:8,@+er1 ;01756c18a112 + sub.b #0x12:8,@er1- ;01766c18a112 + sub.b #0x12:8,@(0x1234:16,er1) ;01746e181234a112 + sub.b #0x12:8,@(0x12345678:32,er1) ;78146a2812345678a112 + sub.b #0x12:8,@(0x1234:16,r2l.b) ;01756e281234a112 + sub.b #0x12:8,@(0x1234:16,r2.w) ;01766e281234a112 + sub.b #0x12:8,@(0x1234:16,er2.l) ;01776e281234a112 + sub.b #0x12:8,@(0x12345678:32,r2l.b) ;78256a2812345678a112 + sub.b #0x12:8,@(0x12345678:32,r2.w) ;78266a2812345678a112 + sub.b #0x12:8,@(0x12345678:32,er2.l) ;78276a2812345678a112 + sub.b #0x12:8,@0xffffff9a:8 ;7f9aa112 + sub.b #0x12:8,@0x1234:16 ;6a181234a112 + sub.b #0x12:8,@0x12345678:32 ;6a3812345678a112 + + sub.b r3h,r1h ;1831 + + sub.b r3h,@er1 ;7d101830 + sub.b r3h,@(0x3:2,er1) ;01793133 + sub.b r3h,@er1+ ;01798133 + sub.b r3h,@-er1 ;0179b133 + sub.b r3h,@+er1 ;01799133 + sub.b r3h,@er1- ;0179a133 + sub.b r3h,@(0x1234:16,er1) ;0179c1331234 + sub.b r3h,@(0x12345678:32,er1) ;0179c93312345678 + sub.b r3h,@(0x1234:16,r2l.b) ;0179d2331234 + sub.b r3h,@(0x1234:16,r2.w) ;0179e2331234 + sub.b r3h,@(0x1234:16,er2.l) ;0179f2331234 + sub.b r3h,@(0x12345678:32,r2l.b) ;0179da3312345678 + sub.b r3h,@(0x12345678:32,r2.w) ;0179ea3312345678 + sub.b r3h,@(0x12345678:32,er2.l) ;0179fa3312345678 + sub.b r3h,@0xffffff12:8 ;7f121830 + sub.b r3h,@0x1234:16 ;6a1812341830 + sub.b r3h,@0x12345678:32 ;6a38123456781830 + + sub.b @er3,r1h ;7c301801 + sub.b @(0x3:2,er3),r1h ;017a3331 + sub.b @er3+,r1h ;017a8331 + sub.b @-er3,r1h ;017ab331 + sub.b @+er3,r1h ;017a9331 + sub.b @er3-,r1h ;017aa331 + sub.b @(0x1234:16,er1),r1h ;017ac1311234 + sub.b @(0x12345678:32,er1),r1h ;017ac93112345678 + sub.b @(0x1234:16,r2l.b),r1h ;017ad2311234 + sub.b @(0x1234:16,r2.w),r1h ;017ae2311234 + sub.b @(0x1234:16,er2.l),r1h ;017af2311234 + sub.b @(0x12345678:32,r2l.b),r1h ;017ada3112345678 + sub.b @(0x12345678:32,r2.w),r1h ;017aea3112345678 + sub.b @(0x12345678:32,er2.l),r1h ;017afa3112345678 + sub.b @0xffffff12:8,r1h ;7e121801 + sub.b @0x1234:16,r1h ;6a1012341801 + sub.b @0x12345678:32,r1h ;6a30123456781801 + + sub.b @er3,@er1 ;7c350130 + sub.b @er3,@(3:2,er1) ;7c353130 + sub.b @er3,@-er1 ;7c35b130 + sub.b @er3,@er1+ ;7c358130 + sub.b @er3,@er1- ;7c35a130 + sub.b @er3,@+er1 ;7c359130 + sub.b @er3,@(0xffff9abc:16,er1) ;7c35c1309abc + sub.b @er3,@(0x9abcdef0:32,er1) ;7c35c9309abcdef0 + sub.b @er3,@(0xffff9abc:16,r2l.b) ;7c35d2309abc + sub.b @er3,@(0xffff9abc:16,r2.w) ;7c35e2309abc + sub.b @er3,@(0xffff9abc:16,er2.l) ;7c35f2309abc + sub.b @er3,@(0x9abcdef0:32,r2l.b) ;7c35da309abcdef0 + sub.b @er3,@(0x9abcdef0:32,r2.w) ;7c35ea309abcdef0 + sub.b @er3,@(0x9abcdef0:32,er2.l) ;7c35fa309abcdef0 + sub.b @er3,@0xffff9abc:16 ;7c3540309abc + sub.b @er3,@0x9abcdef0:32 ;7c3548309abcdef0 + + sub.b @-er3,@er1 ;01776c3c0130 + sub.b @-er3,@(3:2,er1) ;01776c3c3130 + sub.b @-er3,@-er1 ;01776c3cb130 + sub.b @-er3,@er1+ ;01776c3c8130 + sub.b @-er3,@er1- ;01776c3ca130 + sub.b @-er3,@+er1 ;01776c3c9130 + sub.b @-er3,@(0xffff9abc:16,er1) ;01776c3cc1309abc + sub.b @-er3,@(0x9abcdef0:32,er1) ;01776c3cc9309abcdef0 + sub.b @-er3,@(0xffff9abc:16,r2l.b) ;01776c3cd2309abc + sub.b @-er3,@(0xffff9abc:16,r2.w) ;01776c3ce2309abc + sub.b @-er3,@(0xffff9abc:16,er2.l) ;01776c3cf2309abc + sub.b @-er3,@(0x9abcdef0:32,r2l.b) ;01776c3cda309abcdef0 + sub.b @-er3,@(0x9abcdef0:32,r2.w) ;01776c3cea309abcdef0 + sub.b @-er3,@(0x9abcdef0:32,er2.l) ;01776c3cfa309abcdef0 + sub.b @-er3,@0xffff9abc:16 ;01776c3c40309abc + sub.b @-er3,@0x9abcdef0:32 ;01776c3c48309abcdef0 + + sub.b @er3+,@er1 ;01746c3c0130 + sub.b @er3+,@(3:2,er1) ;01746c3c3130 + sub.b @er3+,@-er1 ;01746c3cb130 + sub.b @er3+,@er1+ ;01746c3c8130 + sub.b @er3+,@er1- ;01746c3ca130 + sub.b @er3+,@+er1 ;01746c3c9130 + sub.b @er3+,@(0xffff9abc:16,er1) ;01746c3cc1309abc + sub.b @er3+,@(0x9abcdef0:32,er1) ;01746c3cc9309abcdef0 + sub.b @er3+,@(0xffff9abc:16,r2l.b) ;01746c3cd2309abc + sub.b @er3+,@(0xffff9abc:16,r2.w) ;01746c3ce2309abc + sub.b @er3+,@(0xffff9abc:16,er2.l) ;01746c3cf2309abc + sub.b @er3+,@(0x9abcdef0:32,r2l.b) ;01746c3cda309abcdef0 + sub.b @er3+,@(0x9abcdef0:32,r2.w) ;01746c3cea309abcdef0 + sub.b @er3+,@(0x9abcdef0:32,er2.l) ;01746c3cfa309abcdef0 + sub.b @er3+,@0xffff9abc:16 ;01746c3c40309abc + sub.b @er3+,@0x9abcdef0:32 ;01746c3c48309abcdef0 + + sub.b @er3-,@er1 ;01766c3c0130 + sub.b @er3-,@(3:2,er1) ;01766c3c3130 + sub.b @er3-,@-er1 ;01766c3cb130 + sub.b @er3-,@er1+ ;01766c3c8130 + sub.b @er3-,@er1- ;01766c3ca130 + sub.b @er3-,@+er1 ;01766c3c9130 + sub.b @er3-,@(0xffff9abc:16,er1) ;01766c3cc1309abc + sub.b @er3-,@(0x9abcdef0:32,er1) ;01766c3cc9309abcdef0 + sub.b @er3-,@(0xffff9abc:16,r2l.b) ;01766c3cd2309abc + sub.b @er3-,@(0xffff9abc:16,r2.w) ;01766c3ce2309abc + sub.b @er3-,@(0xffff9abc:16,er2.l) ;01766c3cf2309abc + sub.b @er3-,@(0x9abcdef0:32,r2l.b) ;01766c3cda309abcdef0 + sub.b @er3-,@(0x9abcdef0:32,r2.w) ;01766c3cea309abcdef0 + sub.b @er3-,@(0x9abcdef0:32,er2.l) ;01766c3cfa309abcdef0 + sub.b @er3-,@0xffff9abc:16 ;01766c3c40309abc + sub.b @er3-,@0x9abcdef0:32 ;01766c3c48309abcdef0 + + sub.b @+er3,@er1 ;01756c3c0130 + sub.b @+er3,@(3:2,er1) ;01756c3c3130 + sub.b @+er3,@-er1 ;01756c3cb130 + sub.b @+er3,@er1+ ;01756c3c8130 + sub.b @+er3,@er1- ;01756c3ca130 + sub.b @+er3,@+er1 ;01756c3c9130 + sub.b @+er3,@(0xffff9abc:16,er1) ;01756c3cc1309abc + sub.b @+er3,@(0x9abcdef0:32,er1) ;01756c3cc9309abcdef0 + sub.b @+er3,@(0xffff9abc:16,r2l.b) ;01756c3cd2309abc + sub.b @+er3,@(0xffff9abc:16,r2.w) ;01756c3ce2309abc + sub.b @+er3,@(0xffff9abc:16,er2.l) ;01756c3cf2309abc + sub.b @+er3,@(0x9abcdef0:32,r2l.b) ;01756c3cda309abcdef0 + sub.b @+er3,@(0x9abcdef0:32,r2.w) ;01756c3cea309abcdef0 + sub.b @+er3,@(0x9abcdef0:32,er2.l) ;01756c3cfa309abcdef0 + sub.b @+er3,@0xffff9abc:16 ;01756c3c40309abc + sub.b @+er3,@0x9abcdef0:32 ;01756c3c48309abcdef0 + + sub.b @(0x1234:16,er3),@er1 ;01746e3c12340130 + sub.b @(0x1234:16,er3),@(3:2,er1) ;01746e3c12343130 + sub.b @(0x1234:16,er3),@-er1 ;01746e3c1234b130 + sub.b @(0x1234:16,er3),@er1+ ;01746e3c12348130 + sub.b @(0x1234:16,er3),@er1- ;01746e3c1234a130 + sub.b @(0x1234:16,er3),@+er1 ;01746e3c12349130 + sub.b @(0x1234:16,er3),@(0xffff9abc:16,er1) ;01746e3c1234c1309abc + sub.b @(0x1234:16,er3),@(0x9abcdef0:32,er1) ;01746e3c1234c9309abcdef0 + sub.b @(0x1234:16,er3),@(0xffff9abc:16,r2l.b) ;01746e3c1234d2309abc + sub.b @(0x1234:16,er3),@(0xffff9abc:16,r2.w) ;01746e3c1234e2309abc + sub.b @(0x1234:16,er3),@(0xffff9abc:16,er2.l) ;01746e3c1234f2309abc + sub.b @(0x1234:16,er3),@(0x9abcdef0:32,r2l.b) ;01746e3c1234da309abcdef0 + sub.b @(0x1234:16,er3),@(0x9abcdef0:32,r2.w) ;01746e3c1234ea309abcdef0 + sub.b @(0x1234:16,er3),@(0x9abcdef0:32,er2.l) ;01746e3c1234fa309abcdef0 + sub.b @(0x1234:16,er3),@0xffff9abc:16 ;01746e3c123440309abc + sub.b @(0x1234:16,er3),@0x9abcdef0:32 ;01746e3c123448309abcdef0 + + sub.b @(0x12345678:32,er3),@er1 ;78346a2c123456780130 + sub.b @(0x12345678:32,er3),@(3:2,er1) ;78346a2c123456783130 + sub.b @(0x12345678:32,er3),@-er1 ;78346a2c12345678b130 + sub.b @(0x12345678:32,er3),@er1+ ;78346a2c123456788130 + sub.b @(0x12345678:32,er3),@er1- ;78346a2c12345678a130 + sub.b @(0x12345678:32,er3),@+er1 ;78346a2c123456789130 + sub.b @(0x12345678:32,er3),@(0xffff9abc:16,er1) ;78346a2c12345678c1309abc + sub.b @(0x12345678:32,er3),@(0x9abcdef0:32,er1) ;78346a2c12345678c9309abcdef0 + sub.b @(0x12345678:32,er3),@(0xffff9abc:16,r2l.b) ;78346a2c12345678d2309abc + sub.b @(0x12345678:32,er3),@(0xffff9abc:16,r2.w) ;78346a2c12345678e2309abc + sub.b @(0x12345678:32,er3),@(0xffff9abc:16,er2.l) ;78346a2c12345678f2309abc + sub.b @(0x12345678:32,er3),@(0x9abcdef0:32,r2l.b) ;78346a2c12345678da309abcdef0 + sub.b @(0x12345678:32,er3),@(0x9abcdef0:32,r2.w) ;78346a2c12345678ea309abcdef0 + sub.b @(0x12345678:32,er3),@(0x9abcdef0:32,er2.l) ;78346a2c12345678fa309abcdef0 + sub.b @(0x12345678:32,er3),@0xffff9abc:16 ;78346a2c1234567840309abc + sub.b @(0x12345678:32,er3),@0x9abcdef0:32 ;78346a2c1234567848309abcdef0 + + sub.b @(0x1234:16,r3l.b),@er1 ;01756e3c12340130 + sub.b @(0x1234:16,r3l.b),@(3:2,er1) ;01756e3c12343130 + sub.b @(0x1234:16,r3l.b),@-er1 ;01756e3c1234b130 + sub.b @(0x1234:16,r3l.b),@er1+ ;01756e3c12348130 + sub.b @(0x1234:16,r3l.b),@er1- ;01756e3c1234a130 + sub.b @(0x1234:16,r3l.b),@+er1 ;01756e3c12349130 + sub.b @(0x1234:16,r3l.b),@(0xffff9abc:16,er1) ;01756e3c1234c1309abc + sub.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1) ;01756e3c1234c9309abcdef0 + sub.b @(0x1234:16,r3l.b),@(0xffff9abc:16,r2l.b) ;01756e3c1234d2309abc + sub.b @(0x1234:16,r3l.b),@(0xffff9abc:16,r2.w) ;01756e3c1234e2309abc + sub.b @(0x1234:16,r3l.b),@(0xffff9abc:16,er2.l) ;01756e3c1234f2309abc + sub.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2l.b) ;01756e3c1234da309abcdef0 + sub.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2.w) ;01756e3c1234ea309abcdef0 + sub.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,er2.l) ;01756e3c1234fa309abcdef0 + sub.b @(0x1234:16,r3l.b),@0xffff9abc:16 ;01756e3c123440309abc + sub.b @(0x1234:16,r3l.b),@0x9abcdef0:32 ;01756e3c123448309abcdef0 + + sub.b @(0x1234:16,r3.w),@er1 ;01766e3c12340130 + sub.b @(0x1234:16,r3.w),@(3:2,er1) ;01766e3c12343130 + sub.b @(0x1234:16,r3.w),@-er1 ;01766e3c1234b130 + sub.b @(0x1234:16,r3.w),@er1+ ;01766e3c12348130 + sub.b @(0x1234:16,r3.w),@er1- ;01766e3c1234a130 + sub.b @(0x1234:16,r3.w),@+er1 ;01766e3c12349130 + sub.b @(0x1234:16,r3.w),@(0xffff9abc:16,er1) ;01766e3c1234c1309abc + sub.b @(0x1234:16,r3.w),@(0x9abcdef0:32,er1) ;01766e3c1234c9309abcdef0 + sub.b @(0x1234:16,r3.w),@(0xffff9abc:16,r2l.b) ;01766e3c1234d2309abc + sub.b @(0x1234:16,r3.w),@(0xffff9abc:16,r2.w) ;01766e3c1234e2309abc + sub.b @(0x1234:16,r3.w),@(0xffff9abc:16,er2.l) ;01766e3c1234f2309abc + sub.b @(0x1234:16,r3.w),@(0x9abcdef0:32,r2l.b) ;01766e3c1234da309abcdef0 + sub.b @(0x1234:16,r3.w),@(0x9abcdef0:32,r2.w) ;01766e3c1234ea309abcdef0 + sub.b @(0x1234:16,r3.w),@(0x9abcdef0:32,er2.l) ;01766e3c1234fa309abcdef0 + sub.b @(0x1234:16,r3.w),@0xffff9abc:16 ;01766e3c123440309abc + sub.b @(0x1234:16,r3.w),@0x9abcdef0:32 ;01766e3c123448309abcdef0 + + sub.b @(0x1234:16,er3.l),@er1 ;01776e3c12340130 + sub.b @(0x1234:16,er3.l),@(3:2,er1) ;01776e3c12343130 + sub.b @(0x1234:16,er3.l),@-er1 ;01776e3c1234b130 + sub.b @(0x1234:16,er3.l),@er1+ ;01776e3c12348130 + sub.b @(0x1234:16,er3.l),@er1- ;01776e3c1234a130 + sub.b @(0x1234:16,er3.l),@+er1 ;01776e3c12349130 + sub.b @(0x1234:16,er3.l),@(0xffff9abc:16,er1) ;01776e3c1234c1309abc + sub.b @(0x1234:16,er3.l),@(0x9abcdef0:32,er1) ;01776e3c1234c9309abcdef0 + sub.b @(0x1234:16,er3.l),@(0xffff9abc:16,r2l.b) ;01776e3c1234d2309abc + sub.b @(0x1234:16,er3.l),@(0xffff9abc:16,r2.w) ;01776e3c1234e2309abc + sub.b @(0x1234:16,er3.l),@(0xffff9abc:16,er2.l) ;01776e3c1234f2309abc + sub.b @(0x1234:16,er3.l),@(0x9abcdef0:32,r2l.b) ;01776e3c1234da309abcdef0 + sub.b @(0x1234:16,er3.l),@(0x9abcdef0:32,r2.w) ;01776e3c1234ea309abcdef0 + sub.b @(0x1234:16,er3.l),@(0x9abcdef0:32,er2.l) ;01776e3c1234fa309abcdef0 + sub.b @(0x1234:16,er3.l),@0xffff9abc:16 ;01776e3c123440309abc + sub.b @(0x1234:16,er3.l),@0x9abcdef0:32 ;01776e3c123448309abcdef0 + + sub.b @(0x12345678:32,r3l.b),@er1 ;78356a2c123456780130 + sub.b @(0x12345678:32,r3l.b),@(3:2,er1) ;78356a2c123456783130 + sub.b @(0x12345678:32,r3l.b),@-er1 ;78356a2c12345678b130 + sub.b @(0x12345678:32,r3l.b),@er1+ ;78356a2c123456788130 + sub.b @(0x12345678:32,r3l.b),@er1- ;78356a2c12345678a130 + sub.b @(0x12345678:32,r3l.b),@+er1 ;78356a2c123456789130 + sub.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,er1) ;78356a2c12345678c1309abc + sub.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1) ;78356a2c12345678c9309abcdef0 + sub.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2l.b) ;78356a2c12345678d2309abc + sub.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2.w) ;78356a2c12345678e2309abc + sub.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,er2.l) ;78356a2c12345678f2309abc + sub.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2l.b) ;78356a2c12345678da309abcdef0 + sub.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2.w) ;78356a2c12345678ea309abcdef0 + sub.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er2.l) ;78356a2c12345678fa309abcdef0 + sub.b @(0x12345678:32,r3l.b),@0xffff9abc:16 ;78356a2c1234567840309abc + sub.b @(0x12345678:32,r3l.b),@0x9abcdef0:32 ;78356a2c1234567848309abcdef0 + + sub.b @(0x12345678:32,r3.w),@er1 ;78366a2c123456780130 + sub.b @(0x12345678:32,r3.w),@(3:2,er1) ;78366a2c123456783130 + sub.b @(0x12345678:32,r3.w),@-er1 ;78366a2c12345678b130 + sub.b @(0x12345678:32,r3.w),@er1+ ;78366a2c123456788130 + sub.b @(0x12345678:32,r3.w),@er1- ;78366a2c12345678a130 + sub.b @(0x12345678:32,r3.w),@+er1 ;78366a2c123456789130 + sub.b @(0x12345678:32,r3.w),@(0xffff9abc:16,er1) ;78366a2c12345678c1309abc + sub.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1) ;78366a2c12345678c9309abcdef0 + sub.b @(0x12345678:32,r3.w),@(0xffff9abc:16,r2l.b) ;78366a2c12345678d2309abc + sub.b @(0x12345678:32,r3.w),@(0xffff9abc:16,r2.w) ;78366a2c12345678e2309abc + sub.b @(0x12345678:32,r3.w),@(0xffff9abc:16,er2.l) ;78366a2c12345678f2309abc + sub.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2l.b) ;78366a2c12345678da309abcdef0 + sub.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2.w) ;78366a2c12345678ea309abcdef0 + sub.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,er2.l) ;78366a2c12345678fa309abcdef0 + sub.b @(0x12345678:32,r3.w),@0xffff9abc:16 ;78366a2c1234567840309abc + sub.b @(0x12345678:32,r3.w),@0x9abcdef0:32 ;78366a2c1234567848309abcdef0 + + sub.b @(0x12345678:32,er3.l),@er1 ;78376a2c123456780130 + sub.b @(0x12345678:32,er3.l),@(3:2,er1) ;78376a2c123456783130 + sub.b @(0x12345678:32,er3.l),@-er1 ;78376a2c12345678b130 + sub.b @(0x12345678:32,er3.l),@er1+ ;78376a2c123456788130 + sub.b @(0x12345678:32,er3.l),@er1- ;78376a2c12345678a130 + sub.b @(0x12345678:32,er3.l),@+er1 ;78376a2c123456789130 + sub.b @(0x12345678:32,er3.l),@(0xffff9abc:16,er1) ;78376a2c12345678c1309abc + sub.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1) ;78376a2c12345678c9309abcdef0 + sub.b @(0x12345678:32,er3.l),@(0xffff9abc:16,r2l.b) ;78376a2c12345678d2309abc + sub.b @(0x12345678:32,er3.l),@(0xffff9abc:16,r2.w) ;78376a2c12345678e2309abc + sub.b @(0x12345678:32,er3.l),@(0xffff9abc:16,er2.l) ;78376a2c12345678f2309abc + sub.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2l.b) ;78376a2c12345678da309abcdef0 + sub.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2.w) ;78376a2c12345678ea309abcdef0 + sub.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,er2.l) ;78376a2c12345678fa309abcdef0 + sub.b @(0x12345678:32,er3.l),@0xffff9abc:16 ;78376a2c1234567840309abc + sub.b @(0x12345678:32,er3.l),@0x9abcdef0:32 ;78376a2c1234567848309abcdef0 + + sub.b @0x1234:16,@er1 ;6a1512340130 + sub.b @0x1234:16,@(3:2,er1) ;6a1512343130 + sub.b @0x1234:16,@-er1 ;6a151234b130 + sub.b @0x1234:16,@er1+ ;6a1512348130 + sub.b @0x1234:16,@er1- ;6a151234a130 + sub.b @0x1234:16,@+er1 ;6a1512349130 + sub.b @0x1234:16,@(0xffff9abc:16,er1) ;6a151234c1309abc + sub.b @0x1234:16,@(0x9abcdef0:32,er1) ;6a151234c9309abcdef0 + sub.b @0x1234:16,@(0xffff9abc:16,r2l.b) ;6a151234d2309abc + sub.b @0x1234:16,@(0xffff9abc:16,r2.w) ;6a151234e2309abc + sub.b @0x1234:16,@(0xffff9abc:16,er2.l) ;6a151234f2309abc + sub.b @0x1234:16,@(0x9abcdef0:32,r2l.b) ;6a151234da309abcdef0 + sub.b @0x1234:16,@(0x9abcdef0:32,r2.w) ;6a151234ea309abcdef0 + sub.b @0x1234:16,@(0x9abcdef0:32,er2.l) ;6a151234fa309abcdef0 + sub.b @0x1234:16,@0xffff9abc:16 ;6a15123440309abc + sub.b @0x1234:16,@0x9abcdef0:32 ;6a15123448309abcdef0 + + sub.b @0x12345678:32,@er1 ;6a35123456780130 + sub.b @0x12345678:32,@(3:2,er1) ;6a35123456783130 + sub.b @0x12345678:32,@-er1 ;6a3512345678b130 + sub.b @0x12345678:32,@er1+ ;6a35123456788130 + sub.b @0x12345678:32,@er1- ;6a3512345678a130 + sub.b @0x12345678:32,@+er1 ;6a35123456789130 + sub.b @0x12345678:32,@(0xffff9abc:16,er1) ;6a3512345678c1309abc + sub.b @0x12345678:32,@(0x9abcdef0:32,er1) ;6a3512345678c9309abcdef0 + sub.b @0x12345678:32,@(0xffff9abc:16,r2l.b) ;6a3512345678d2309abc + sub.b @0x12345678:32,@(0xffff9abc:16,r2.w) ;6a3512345678e2309abc + sub.b @0x12345678:32,@(0xffff9abc:16,er2.l) ;6a3512345678f2309abc + sub.b @0x12345678:32,@(0x9abcdef0:32,r2l.b) ;6a3512345678da309abcdef0 + sub.b @0x12345678:32,@(0x9abcdef0:32,r2.w) ;6a3512345678ea309abcdef0 + sub.b @0x12345678:32,@(0x9abcdef0:32,er2.l) ;6a3512345678fa309abcdef0 + sub.b @0x12345678:32,@0xffff9abc:16 ;6a351234567840309abc + sub.b @0x12345678:32,@0x9abcdef0:32 ;6a351234567848309abcdef0 + + sub.w #0x1234:16,r1 ;79311234 + sub.w #7:3,r2 ;1a72 + sub.w #0x1234:16,@er1 ;015e01301234 + sub.w #0x1234:16,@(0x6:2,er1) ;015e31301234 + sub.w #0x1234:16,@er1+ ;015e81301234 + sub.w #0x1234:16,@-er1 ;015eb1301234 + sub.w #0x1234:16,@+er1 ;015e91301234 + sub.w #0x1234:16,@er1- ;015ea1301234 + sub.w #0x1234:16,@(0xffff9abc:16,er1) ;015ec1309abc1234 + sub.w #0x1234:16,@(0x9abcdef0:32,er1) ;015ec9309abcdef01234 + sub.w #0x1234:16,@(0xffff9abc:16,r2l.b) ;015ed2309abc1234 + sub.w #0x1234:16,@(0xffff9abc:16,r2.w) ;015ee2309abc1234 + sub.w #0x1234:16,@(0xffff9abc:16,er2.l) ;015ef2309abc1234 + sub.w #0x1234:16,@(0x9abcdef0:32,r2l.b) ;015eda309abcdef01234 + sub.w #0x1234:16,@(0x9abcdef0:32,r2.w) ;015eea309abcdef01234 + sub.w #0x1234:16,@(0x9abcdef0:32,er2.l) ;015efa309abcdef01234 + sub.w #0x1234:16,@0xffff9abc:16 ;015e40309abc1234 + sub.w #0x1234:16,@0x9abcdef0:32 ;015e48309abcdef01234 + + sub.w #0x7:3,@er1 ;7d901a70 + sub.w #0x7:3,@0x1234:16 ;6b1812341a70 + sub.w #0x7:3,@0x12345678:32 ;6b38123456781a70 + + sub.w r3,r1 ;1931 + + sub.w r3,@er1 ;7d901930 + sub.w r3,@(0x6:2,er1) ;01593133 + sub.w r3,@er1+ ;01598133 + sub.w r3,@-er1 ;0159b133 + sub.w r3,@+er1 ;01599133 + sub.w r3,@er1- ;0159a133 + sub.w r3,@(0x1234:16,er1) ;0159c1331234 + sub.w r3,@(0x12345678:32,er1) ;0159c93312345678 + sub.w r3,@(0x1234:16,r2l.b) ;0159d2331234 + sub.w r3,@(0x1234:16,r2.w) ;0159e2331234 + sub.w r3,@(0x1234:16,er2.l) ;0159f2331234 + sub.w r3,@(0x12345678:32,r2l.b) ;0159da3312345678 + sub.w r3,@(0x12345678:32,r2.w) ;0159ea3312345678 + sub.w r3,@(0x12345678:32,er2.l) ;0159fa3312345678 + sub.w r3,@0x1234:16 ;6b1812341930 + sub.w r3,@0x12345678:32 ;6b38123456781930 + + sub.w @er3,r1 ;7cb01901 + sub.w @(0x6:2,er3),r1 ;015a3331 + sub.w @er3+,r1 ;015a8331 + sub.w @-er3,r1 ;015ab331 + sub.w @+er3,r1 ;015a9331 + sub.w @er3-,r1 ;015aa331 + sub.w @(0x1234:16,er1),r1 ;015ac1311234 + sub.w @(0x12345678:32,er1),r1 ;015ac93112345678 + sub.w @(0x1234:16,r2l.b),r1 ;015ad2311234 + sub.w @(0x1234:16,r2.w),r1 ;015ae2311234 + sub.w @(0x1234:16,er2.l),r1 ;015af2311234 + sub.w @(0x12345678:32,r2l.b),r1 ;015ada3112345678 + sub.w @(0x12345678:32,r2.w),r1 ;015aea3112345678 + sub.w @(0x12345678:32,er2.l),r1 ;015afa3112345678 + sub.w @0x1234:16,r1 ;6b1012341901 + sub.w @0x12345678:32,r1 ;6b30123456781901 + + sub.w @er3,@er1 ;7cb50130 + sub.w @er3,@(6:2,er1) ;7cb53130 + sub.w @er3,@-er1 ;7cb5b130 + sub.w @er3,@er1+ ;7cb58130 + sub.w @er3,@er1- ;7cb5a130 + sub.w @er3,@+er1 ;7cb59130 + sub.w @er3,@(0xffff9abc:16,er1) ;7cb5c1309abc + sub.w @er3,@(0x9abcdef0:32,er1) ;7cb5c9309abcdef0 + sub.w @er3,@(0xffff9abc:16,r2l.b) ;7cb5d2309abc + sub.w @er3,@(0xffff9abc:16,r2.w) ;7cb5e2309abc + sub.w @er3,@(0xffff9abc:16,er2.l) ;7cb5f2309abc + sub.w @er3,@(0x9abcdef0:32,r2l.b) ;7cb5da309abcdef0 + sub.w @er3,@(0x9abcdef0:32,r2.w) ;7cb5ea309abcdef0 + sub.w @er3,@(0x9abcdef0:32,er2.l) ;7cb5fa309abcdef0 + sub.w @er3,@0xffff9abc:16 ;7cb540309abc + sub.w @er3,@0x9abcdef0:32 ;7cb548309abcdef0 + + sub.w @-er3,@er1 ;01576d3c0130 + sub.w @-er3,@(6:2,er1) ;01576d3c3130 + sub.w @-er3,@-er1 ;01576d3cb130 + sub.w @-er3,@er1+ ;01576d3c8130 + sub.w @-er3,@er1- ;01576d3ca130 + sub.w @-er3,@+er1 ;01576d3c9130 + sub.w @-er3,@(0xffff9abc:16,er1) ;01576d3cc1309abc + sub.w @-er3,@(0x9abcdef0:32,er1) ;01576d3cc9309abcdef0 + sub.w @-er3,@(0xffff9abc:16,r2l.b) ;01576d3cd2309abc + sub.w @-er3,@(0xffff9abc:16,r2.w) ;01576d3ce2309abc + sub.w @-er3,@(0xffff9abc:16,er2.l) ;01576d3cf2309abc + sub.w @-er3,@(0x9abcdef0:32,r2l.b) ;01576d3cda309abcdef0 + sub.w @-er3,@(0x9abcdef0:32,r2.w) ;01576d3cea309abcdef0 + sub.w @-er3,@(0x9abcdef0:32,er2.l) ;01576d3cfa309abcdef0 + sub.w @-er3,@0xffff9abc:16 ;01576d3c40309abc + sub.w @-er3,@0x9abcdef0:32 ;01576d3c48309abcdef0 + + sub.w @er3+,@er1 ;01546d3c0130 + sub.w @er3+,@(6:2,er1) ;01546d3c3130 + sub.w @er3+,@-er1 ;01546d3cb130 + sub.w @er3+,@er1+ ;01546d3c8130 + sub.w @er3+,@er1- ;01546d3ca130 + sub.w @er3+,@+er1 ;01546d3c9130 + sub.w @er3+,@(0xffff9abc:16,er1) ;01546d3cc1309abc + sub.w @er3+,@(0x9abcdef0:32,er1) ;01546d3cc9309abcdef0 + sub.w @er3+,@(0xffff9abc:16,r2l.b) ;01546d3cd2309abc + sub.w @er3+,@(0xffff9abc:16,r2.w) ;01546d3ce2309abc + sub.w @er3+,@(0xffff9abc:16,er2.l) ;01546d3cf2309abc + sub.w @er3+,@(0x9abcdef0:32,r2l.b) ;01546d3cda309abcdef0 + sub.w @er3+,@(0x9abcdef0:32,r2.w) ;01546d3cea309abcdef0 + sub.w @er3+,@(0x9abcdef0:32,er2.l) ;01546d3cfa309abcdef0 + sub.w @er3+,@0xffff9abc:16 ;01546d3c40309abc + sub.w @er3+,@0x9abcdef0:32 ;01546d3c48309abcdef0 + + sub.w @er3-,@er1 ;01566d3c0130 + sub.w @er3-,@(6:2,er1) ;01566d3c3130 + sub.w @er3-,@-er1 ;01566d3cb130 + sub.w @er3-,@er1+ ;01566d3c8130 + sub.w @er3-,@er1- ;01566d3ca130 + sub.w @er3-,@+er1 ;01566d3c9130 + sub.w @er3-,@(0xffff9abc:16,er1) ;01566d3cc1309abc + sub.w @er3-,@(0x9abcdef0:32,er1) ;01566d3cc9309abcdef0 + sub.w @er3-,@(0xffff9abc:16,r2l.b) ;01566d3cd2309abc + sub.w @er3-,@(0xffff9abc:16,r2.w) ;01566d3ce2309abc + sub.w @er3-,@(0xffff9abc:16,er2.l) ;01566d3cf2309abc + sub.w @er3-,@(0x9abcdef0:32,r2l.b) ;01566d3cda309abcdef0 + sub.w @er3-,@(0x9abcdef0:32,r2.w) ;01566d3cea309abcdef0 + sub.w @er3-,@(0x9abcdef0:32,er2.l) ;01566d3cfa309abcdef0 + sub.w @er3-,@0xffff9abc:16 ;01566d3c40309abc + sub.w @er3-,@0x9abcdef0:32 ;01566d3c48309abcdef0 + + sub.w @+er3,@er1 ;01556d3c0130 + sub.w @+er3,@(6:2,er1) ;01556d3c3130 + sub.w @+er3,@-er1 ;01556d3cb130 + sub.w @+er3,@er1+ ;01556d3c8130 + sub.w @+er3,@er1- ;01556d3ca130 + sub.w @+er3,@+er1 ;01556d3c9130 + sub.w @+er3,@(0xffff9abc:16,er1) ;01556d3cc1309abc + sub.w @+er3,@(0x9abcdef0:32,er1) ;01556d3cc9309abcdef0 + sub.w @+er3,@(0xffff9abc:16,r2l.b) ;01556d3cd2309abc + sub.w @+er3,@(0xffff9abc:16,r2.w) ;01556d3ce2309abc + sub.w @+er3,@(0xffff9abc:16,er2.l) ;01556d3cf2309abc + sub.w @+er3,@(0x9abcdef0:32,r2l.b) ;01556d3cda309abcdef0 + sub.w @+er3,@(0x9abcdef0:32,r2.w) ;01556d3cea309abcdef0 + sub.w @+er3,@(0x9abcdef0:32,er2.l) ;01556d3cfa309abcdef0 + sub.w @+er3,@0xffff9abc:16 ;01556d3c40309abc + sub.w @+er3,@0x9abcdef0:32 ;01556d3c48309abcdef0 + + sub.w @(0x1234:16,er3),@er1 ;01546f3c12340130 + sub.w @(0x1234:16,er3),@(6:2,er1) ;01546f3c12343130 + sub.w @(0x1234:16,er3),@-er1 ;01546f3c1234b130 + sub.w @(0x1234:16,er3),@er1+ ;01546f3c12348130 + sub.w @(0x1234:16,er3),@er1- ;01546f3c1234a130 + sub.w @(0x1234:16,er3),@+er1 ;01546f3c12349130 + sub.w @(0x1234:16,er3),@(0xffff9abc:16,er1) ;01546f3c1234c1309abc + sub.w @(0x1234:16,er3),@(0x9abcdef0:32,er1) ;01546f3c1234c9309abcdef0 + sub.w @(0x1234:16,er3),@(0xffff9abc:16,r2l.b) ;01546f3c1234d2309abc + sub.w @(0x1234:16,er3),@(0xffff9abc:16,r2.w) ;01546f3c1234e2309abc + sub.w @(0x1234:16,er3),@(0xffff9abc:16,er2.l) ;01546f3c1234f2309abc + sub.w @(0x1234:16,er3),@(0x9abcdef0:32,r2l.b) ;01546f3c1234da309abcdef0 + sub.w @(0x1234:16,er3),@(0x9abcdef0:32,r2.w) ;01546f3c1234ea309abcdef0 + sub.w @(0x1234:16,er3),@(0x9abcdef0:32,er2.l) ;01546f3c1234fa309abcdef0 + sub.w @(0x1234:16,er3),@0xffff9abc:16 ;01546f3c123440309abc + sub.w @(0x1234:16,er3),@0x9abcdef0:32 ;01546f3c123448309abcdef0 + + sub.w @(0x12345678:32,er3),@er1 ;78346b2c123456780130 + sub.w @(0x12345678:32,er3),@(6:2,er1) ;78346b2c123456783130 + sub.w @(0x12345678:32,er3),@-er1 ;78346b2c12345678b130 + sub.w @(0x12345678:32,er3),@er1+ ;78346b2c123456788130 + sub.w @(0x12345678:32,er3),@er1- ;78346b2c12345678a130 + sub.w @(0x12345678:32,er3),@+er1 ;78346b2c123456789130 + sub.w @(0x12345678:32,er3),@(0xffff9abc:16,er1) ;78346b2c12345678c1309abc + sub.w @(0x12345678:32,er3),@(0x9abcdef0:32,er1) ;78346b2c12345678c9309abcdef0 + sub.w @(0x12345678:32,er3),@(0xffff9abc:16,r2l.b) ;78346b2c12345678d2309abc + sub.w @(0x12345678:32,er3),@(0xffff9abc:16,r2.w) ;78346b2c12345678e2309abc + sub.w @(0x12345678:32,er3),@(0xffff9abc:16,er2.l) ;78346b2c12345678f2309abc + sub.w @(0x12345678:32,er3),@(0x9abcdef0:32,r2l.b) ;78346b2c12345678da309abcdef0 + sub.w @(0x12345678:32,er3),@(0x9abcdef0:32,r2.w) ;78346b2c12345678ea309abcdef0 + sub.w @(0x12345678:32,er3),@(0x9abcdef0:32,er2.l) ;78346b2c12345678fa309abcdef0 + sub.w @(0x12345678:32,er3),@0xffff9abc:16 ;78346b2c1234567840309abc + sub.w @(0x12345678:32,er3),@0x9abcdef0:32 ;78346b2c1234567848309abcdef0 + + sub.w @(0x1234:16,r3l.b),@er1 ;01556f3c12340130 + sub.w @(0x1234:16,r3l.b),@(6:2,er1) ;01556f3c12343130 + sub.w @(0x1234:16,r3l.b),@-er1 ;01556f3c1234b130 + sub.w @(0x1234:16,r3l.b),@er1+ ;01556f3c12348130 + sub.w @(0x1234:16,r3l.b),@er1- ;01556f3c1234a130 + sub.w @(0x1234:16,r3l.b),@+er1 ;01556f3c12349130 + sub.w @(0x1234:16,r3l.b),@(0xffff9abc:16,er1) ;01556f3c1234c1309abc + sub.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1) ;01556f3c1234c9309abcdef0 + sub.w @(0x1234:16,r3l.b),@(0xffff9abc:16,r2l.b) ;01556f3c1234d2309abc + sub.w @(0x1234:16,r3l.b),@(0xffff9abc:16,r2.w) ;01556f3c1234e2309abc + sub.w @(0x1234:16,r3l.b),@(0xffff9abc:16,er2.l) ;01556f3c1234f2309abc + sub.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2l.b) ;01556f3c1234da309abcdef0 + sub.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2.w) ;01556f3c1234ea309abcdef0 + sub.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,er2.l) ;01556f3c1234fa309abcdef0 + sub.w @(0x1234:16,r3l.b),@0xffff9abc:16 ;01556f3c123440309abc + sub.w @(0x1234:16,r3l.b),@0x9abcdef0:32 ;01556f3c123448309abcdef0 + + sub.w @(0x1234:16,r3.w),@er1 ;01566f3c12340130 + sub.w @(0x1234:16,r3.w),@(6:2,er1) ;01566f3c12343130 + sub.w @(0x1234:16,r3.w),@-er1 ;01566f3c1234b130 + sub.w @(0x1234:16,r3.w),@er1+ ;01566f3c12348130 + sub.w @(0x1234:16,r3.w),@er1- ;01566f3c1234a130 + sub.w @(0x1234:16,r3.w),@+er1 ;01566f3c12349130 + sub.w @(0x1234:16,r3.w),@(0xffff9abc:16,er1) ;01566f3c1234c1309abc + sub.w @(0x1234:16,r3.w),@(0x9abcdef0:32,er1) ;01566f3c1234c9309abcdef0 + sub.w @(0x1234:16,r3.w),@(0xffff9abc:16,r2l.b) ;01566f3c1234d2309abc + sub.w @(0x1234:16,r3.w),@(0xffff9abc:16,r2.w) ;01566f3c1234e2309abc + sub.w @(0x1234:16,r3.w),@(0xffff9abc:16,er2.l) ;01566f3c1234f2309abc + sub.w @(0x1234:16,r3.w),@(0x9abcdef0:32,r2l.b) ;01566f3c1234da309abcdef0 + sub.w @(0x1234:16,r3.w),@(0x9abcdef0:32,r2.w) ;01566f3c1234ea309abcdef0 + sub.w @(0x1234:16,r3.w),@(0x9abcdef0:32,er2.l) ;01566f3c1234fa309abcdef0 + sub.w @(0x1234:16,r3.w),@0xffff9abc:16 ;01566f3c123440309abc + sub.w @(0x1234:16,r3.w),@0x9abcdef0:32 ;01566f3c123448309abcdef0 + + sub.w @(0x1234:16,er3.l),@er1 ;01576f3c12340130 + sub.w @(0x1234:16,er3.l),@(6:2,er1) ;01576f3c12343130 + sub.w @(0x1234:16,er3.l),@-er1 ;01576f3c1234b130 + sub.w @(0x1234:16,er3.l),@er1+ ;01576f3c12348130 + sub.w @(0x1234:16,er3.l),@er1- ;01576f3c1234a130 + sub.w @(0x1234:16,er3.l),@+er1 ;01576f3c12349130 + sub.w @(0x1234:16,er3.l),@(0xffff9abc:16,er1) ;01576f3c1234c1309abc + sub.w @(0x1234:16,er3.l),@(0x9abcdef0:32,er1) ;01576f3c1234c9309abcdef0 + sub.w @(0x1234:16,er3.l),@(0xffff9abc:16,r2l.b) ;01576f3c1234d2309abc + sub.w @(0x1234:16,er3.l),@(0xffff9abc:16,r2.w) ;01576f3c1234e2309abc + sub.w @(0x1234:16,er3.l),@(0xffff9abc:16,er2.l) ;01576f3c1234f2309abc + sub.w @(0x1234:16,er3.l),@(0x9abcdef0:32,r2l.b) ;01576f3c1234da309abcdef0 + sub.w @(0x1234:16,er3.l),@(0x9abcdef0:32,r2.w) ;01576f3c1234ea309abcdef0 + sub.w @(0x1234:16,er3.l),@(0x9abcdef0:32,er2.l) ;01576f3c1234fa309abcdef0 + sub.w @(0x1234:16,er3.l),@0xffff9abc:16 ;01576f3c123440309abc + sub.w @(0x1234:16,er3.l),@0x9abcdef0:32 ;01576f3c123448309abcdef0 + + sub.w @(0x12345678:32,r3l.b),@er1 ;78356b2c123456780130 + sub.w @(0x12345678:32,r3l.b),@(6:2,er1) ;78356b2c123456783130 + sub.w @(0x12345678:32,r3l.b),@-er1 ;78356b2c12345678b130 + sub.w @(0x12345678:32,r3l.b),@er1+ ;78356b2c123456788130 + sub.w @(0x12345678:32,r3l.b),@er1- ;78356b2c12345678a130 + sub.w @(0x12345678:32,r3l.b),@+er1 ;78356b2c123456789130 + sub.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,er1) ;78356b2c12345678c1309abc + sub.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1) ;78356b2c12345678c9309abcdef0 + sub.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2l.b) ;78356b2c12345678d2309abc + sub.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2.w) ;78356b2c12345678e2309abc + sub.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,er2.l) ;78356b2c12345678f2309abc + sub.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2l.b) ;78356b2c12345678da309abcdef0 + sub.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2.w) ;78356b2c12345678ea309abcdef0 + sub.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er2.l) ;78356b2c12345678fa309abcdef0 + sub.w @(0x12345678:32,r3l.b),@0xffff9abc:16 ;78356b2c1234567840309abc + sub.w @(0x12345678:32,r3l.b),@0x9abcdef0:32 ;78356b2c1234567848309abcdef0 + + sub.w @(0x12345678:32,r3.w),@er1 ;78366b2c123456780130 + sub.w @(0x12345678:32,r3.w),@(6:2,er1) ;78366b2c123456783130 + sub.w @(0x12345678:32,r3.w),@-er1 ;78366b2c12345678b130 + sub.w @(0x12345678:32,r3.w),@er1+ ;78366b2c123456788130 + sub.w @(0x12345678:32,r3.w),@er1- ;78366b2c12345678a130 + sub.w @(0x12345678:32,r3.w),@+er1 ;78366b2c123456789130 + sub.w @(0x12345678:32,r3.w),@(0xffff9abc:16,er1) ;78366b2c12345678c1309abc + sub.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1) ;78366b2c12345678c9309abcdef0 + sub.w @(0x12345678:32,r3.w),@(0xffff9abc:16,r2l.b) ;78366b2c12345678d2309abc + sub.w @(0x12345678:32,r3.w),@(0xffff9abc:16,r2.w) ;78366b2c12345678e2309abc + sub.w @(0x12345678:32,r3.w),@(0xffff9abc:16,er2.l) ;78366b2c12345678f2309abc + sub.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2l.b) ;78366b2c12345678da309abcdef0 + sub.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2.w) ;78366b2c12345678ea309abcdef0 + sub.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,er2.l) ;78366b2c12345678fa309abcdef0 + sub.w @(0x12345678:32,r3.w),@0xffff9abc:16 ;78366b2c1234567840309abc + sub.w @(0x12345678:32,r3.w),@0x9abcdef0:32 ;78366b2c1234567848309abcdef0 + + sub.w @(0x12345678:32,er3.l),@er1 ;78376b2c123456780130 + sub.w @(0x12345678:32,er3.l),@(6:2,er1) ;78376b2c123456783130 + sub.w @(0x12345678:32,er3.l),@-er1 ;78376b2c12345678b130 + sub.w @(0x12345678:32,er3.l),@er1+ ;78376b2c123456788130 + sub.w @(0x12345678:32,er3.l),@er1- ;78376b2c12345678a130 + sub.w @(0x12345678:32,er3.l),@+er1 ;78376b2c123456789130 + sub.w @(0x12345678:32,er3.l),@(0xffff9abc:16,er1) ;78376b2c12345678c1309abc + sub.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1) ;78376b2c12345678c9309abcdef0 + sub.w @(0x12345678:32,er3.l),@(0xffff9abc:16,r2l.b) ;78376b2c12345678d2309abc + sub.w @(0x12345678:32,er3.l),@(0xffff9abc:16,r2.w) ;78376b2c12345678e2309abc + sub.w @(0x12345678:32,er3.l),@(0xffff9abc:16,er2.l) ;78376b2c12345678f2309abc + sub.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2l.b) ;78376b2c12345678da309abcdef0 + sub.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2.w) ;78376b2c12345678ea309abcdef0 + sub.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,er2.l) ;78376b2c12345678fa309abcdef0 + sub.w @(0x12345678:32,er3.l),@0xffff9abc:16 ;78376b2c1234567840309abc + sub.w @(0x12345678:32,er3.l),@0x9abcdef0:32 ;78376b2c1234567848309abcdef0 + + sub.w @0x1234:16,@er1 ;6b1512340130 + sub.w @0x1234:16,@(6:2,er1) ;6b1512343130 + sub.w @0x1234:16,@-er1 ;6b151234b130 + sub.w @0x1234:16,@er1+ ;6b1512348130 + sub.w @0x1234:16,@er1- ;6b151234a130 + sub.w @0x1234:16,@+er1 ;6b1512349130 + sub.w @0x1234:16,@(0xffff9abc:16,er1) ;6b151234c1309abc + sub.w @0x1234:16,@(0x9abcdef0:32,er1) ;6b151234c9309abcdef0 + sub.w @0x1234:16,@(0xffff9abc:16,r2l.b) ;6b151234d2309abc + sub.w @0x1234:16,@(0xffff9abc:16,r2.w) ;6b151234e2309abc + sub.w @0x1234:16,@(0xffff9abc:16,er2.l) ;6b151234f2309abc + sub.w @0x1234:16,@(0x9abcdef0:32,r2l.b) ;6b151234da309abcdef0 + sub.w @0x1234:16,@(0x9abcdef0:32,r2.w) ;6b151234ea309abcdef0 + sub.w @0x1234:16,@(0x9abcdef0:32,er2.l) ;6b151234fa309abcdef0 + sub.w @0x1234:16,@0xffff9abc:16 ;6b15123440309abc + sub.w @0x1234:16,@0x9abcdef0:32 ;6b15123448309abcdef0 + + sub.w @0x12345678:32,@er1 ;6b35123456780130 + sub.w @0x12345678:32,@(6:2,er1) ;6b35123456783130 + sub.w @0x12345678:32,@-er1 ;6b3512345678b130 + sub.w @0x12345678:32,@er1+ ;6b35123456788130 + sub.w @0x12345678:32,@er1- ;6b3512345678a130 + sub.w @0x12345678:32,@+er1 ;6b35123456789130 + sub.w @0x12345678:32,@(0xffff9abc:16,er1) ;6b3512345678c1309abc + sub.w @0x12345678:32,@(0x9abcdef0:32,er1) ;6b3512345678c9309abcdef0 + sub.w @0x12345678:32,@(0xffff9abc:16,r2l.b) ;6b3512345678d2309abc + sub.w @0x12345678:32,@(0xffff9abc:16,r2.w) ;6b3512345678e2309abc + sub.w @0x12345678:32,@(0xffff9abc:16,er2.l) ;6b3512345678f2309abc + sub.w @0x12345678:32,@(0x9abcdef0:32,r2l.b) ;6b3512345678da309abcdef0 + sub.w @0x12345678:32,@(0x9abcdef0:32,r2.w) ;6b3512345678ea309abcdef0 + sub.w @0x12345678:32,@(0x9abcdef0:32,er2.l) ;6b3512345678fa309abcdef0 + sub.w @0x12345678:32,@0xffff9abc:16 ;6b351234567840309abc + sub.w @0x12345678:32,@0x9abcdef0:32 ;6b351234567848309abcdef0 + + sub.l #0x12345678:32,er1 ;7a3112345678 + sub.l #0x1234:16,er1 ;7a391234 + sub.l #0x7:3,er2 ;1afa + sub.l #0x12345678:32,@er1 ;010e013812345678 + sub.l #0x12345678:32,@(0xc:2,er1) ;010e313812345678 + sub.l #0x12345678:32,@er1+ ;010e813812345678 + sub.l #0x12345678:32,@-er1 ;010eb13812345678 + sub.l #0x12345678:32,@+er1 ;010e913812345678 + sub.l #0x12345678:32,@er1- ;010ea13812345678 + sub.l #0x12345678:32,@(0xffff9abc:16,er1) ;010ec1389abc12345678 + sub.l #0x12345678:32,@(0x9abcdef0:32,er1) ;010ec9389abcdef012345678 + sub.l #0x12345678:32,@(0xffff9abc:16,r2l.b) ;010ed2389abc12345678 + sub.l #0x12345678:32,@(0xffff9abc:16,r2.w) ;010ee2389abc12345678 + sub.l #0x12345678:32,@(0xffff9abc:16,er2.l) ;010ef2389abc12345678 + sub.l #0x12345678:32,@(0x9abcdef0:32,r2l.b) ;010eda389abcdef012345678 + sub.l #0x12345678:32,@(0x9abcdef0:32,r2.w) ;010eea389abcdef012345678 + sub.l #0x12345678:32,@(0x9abcdef0:32,er2.l) ;010efa389abcdef012345678 + sub.l #0x12345678:32,@0xffff9abc:16 ;010e40389abc12345678 + sub.l #0x12345678:32,@0x9abcdef0:32 ;010e48389abcdef012345678 + sub.l #0x1234:16,@er1 ;010e01301234 + sub.l #0x1234:16,@(0xc:2,er1) ;010e31301234 + sub.l #0x1234:16,@er1+ ;010e81301234 + sub.l #0x1234:16,@-er1 ;010eb1301234 + sub.l #0x1234:16,@+er1 ;010e91301234 + sub.l #0x1234:16,@er1- ;010ea1301234 + sub.l #0x1234:16,@(0xffff9abc:16,er1) ;010ec1309abc1234 + sub.l #0x1234:16,@(0x9abcdef0:32,er1) ;010ec9309abcdef01234 + sub.l #0x1234:16,@(0xffff9abc:16,r2l.b) ;010ed2309abc1234 + sub.l #0x1234:16,@(0xffff9abc:16,r2.w) ;010ee2309abc1234 + sub.l #0x1234:16,@(0xffff9abc:16,er2.l) ;010ef2309abc1234 + sub.l #0x1234:16,@(0x9abcdef0:32,r2l.b) ;010eda309abcdef01234 + sub.l #0x1234:16,@(0x9abcdef0:32,r2.w) ;010eea309abcdef01234 + sub.l #0x1234:16,@(0x9abcdef0:32,er2.l) ;010efa309abcdef01234 + sub.l #0x1234:16,@0xffff9abc:16 ;010e40309abc1234 + sub.l #0x1234:16,@0x9abcdef0:32 ;010e48309abcdef01234 + + sub.l er3,er1 ;1ab1 + + sub.l er3,@er1 ;01090133 + sub.l er3,@(0xc:2,er1) ;01093133 + sub.l er3,@er1+ ;01098133 + sub.l er3,@-er1 ;0109b133 + sub.l er3,@+er1 ;01099133 + sub.l er3,@er1- ;0109a133 + sub.l er3,@(0x1234:16,er1) ;0109c1331234 + sub.l er3,@(0x12345678:32,er1) ;0109c93312345678 + sub.l er3,@(0x1234:16,r2l.b) ;0109d2331234 + sub.l er3,@(0x1234:16,r2.w) ;0109e2331234 + sub.l er3,@(0x1234:16,er2.l) ;0109f2331234 + sub.l er3,@(0x12345678:32,r2l.b) ;0109da3312345678 + sub.l er3,@(0x12345678:32,r2.w) ;0109ea3312345678 + sub.l er3,@(0x12345678:32,er2.l) ;0109fa3312345678 + sub.l er3,@0x1234:16 ;010940331234 + sub.l er3,@0x12345678:32 ;0109483312345678 + + sub.l @er3,er1 ;010a0331 + sub.l @(0xc:2,er3),er1 ;010a3331 + sub.l @er3+,er1 ;010a8331 + sub.l @-er3,er1 ;010ab331 + sub.l @+er3,er1 ;010a9331 + sub.l @er3-,er1 ;010aa331 + sub.l @(0x1234:16,er1),er1 ;010ac1311234 + sub.l @(0x12345678:32,er1),er1 ;010ac93112345678 + sub.l @(0x1234:16,r2l.b),er1 ;010ad2311234 + sub.l @(0x1234:16,r2.w),er1 ;010ae2311234 + sub.l @(0x1234:16,er2.l),er1 ;010af2311234 + sub.l @(0x12345678:32,r2l.b),er1 ;010ada3112345678 + sub.l @(0x12345678:32,r2.w),er1 ;010aea3112345678 + sub.l @(0x12345678:32,er2.l),er1 ;010afa3112345678 + sub.l @0x1234:16,er1 ;010a40311234 + sub.l @0x12345678:32,er1 ;010a483112345678 + + sub.l @er3,@er1 ;0104693c0130 + sub.l @er3,@(0xc:2,er1) ;0104693c3130 + sub.l @er3,@-er1 ;0104693cb130 + sub.l @er3,@er1+ ;0104693c8130 + sub.l @er3,@er1- ;0104693ca130 + sub.l @er3,@+er1 ;0104693c9130 + sub.l @er3,@(0xffff9abc:16,er1) ;0104693cc1309abc + sub.l @er3,@(0x9abcdef0:32,er1) ;0104693cc9309abcdef0 + sub.l @er3,@(0xffff9abc:16,r2l.b) ;0104693cd2309abc + sub.l @er3,@(0xffff9abc:16,r2.w) ;0104693ce2309abc + sub.l @er3,@(0xffff9abc:16,er2.l) ;0104693cf2309abc + sub.l @er3,@(0x9abcdef0:32,r2l.b) ;0104693cda309abcdef0 + sub.l @er3,@(0x9abcdef0:32,r2.w) ;0104693cea309abcdef0 + sub.l @er3,@(0x9abcdef0:32,er2.l) ;0104693cfa309abcdef0 + sub.l @er3,@0xffff9abc:16 ;0104693c40309abc + sub.l @er3,@0x9abcdef0:32 ;0104693c48309abcdef0 + + sub.l @(0xc:2,er3),@er1 ;0107693c0130 + sub.l @(0xc:2,er3),@(0xc:2,er1) ;0107693c3130 + sub.l @(0xc:2,er3),@-er1 ;0107693cb130 + sub.l @(0xc:2,er3),@er1+ ;0107693c8130 + sub.l @(0xc:2,er3),@er1- ;0107693ca130 + sub.l @(0xc:2,er3),@+er1 ;0107693c9130 + sub.l @(0xc:2,er3),@(0xffff9abc:16,er1) ;0107693cc1309abc + sub.l @(0xc:2,er3),@(0x9abcdef0:32,er1) ;0107693cc9309abcdef0 + sub.l @(0xc:2,er3),@(0xffff9abc:16,r2l.b) ;0107693cd2309abc + sub.l @(0xc:2,er3),@(0xffff9abc:16,r2.w) ;0107693ce2309abc + sub.l @(0xc:2,er3),@(0xffff9abc:16,er2.l) ;0107693cf2309abc + sub.l @(0xc:2,er3),@(0x9abcdef0:32,r2l.b) ;0107693cda309abcdef0 + sub.l @(0xc:2,er3),@(0x9abcdef0:32,r2.w) ;0107693cea309abcdef0 + sub.l @(0xc:2,er3),@(0x9abcdef0:32,er2.l) ;0107693cfa309abcdef0 + sub.l @(0xc:2,er3),@0xffff9abc:16 ;0107693c40309abc + sub.l @(0xc:2,er3),@0x9abcdef0:32 ;0107693c48309abcdef0 + + sub.l @-er3,@er1 ;01076d3c0130 + sub.l @-er3,@(0xc:2,er1) ;01076d3c3130 + sub.l @-er3,@-er1 ;01076d3cb130 + sub.l @-er3,@er1+ ;01076d3c8130 + sub.l @-er3,@er1- ;01076d3ca130 + sub.l @-er3,@+er1 ;01076d3c9130 + sub.l @-er3,@(0xffff9abc:16,er1) ;01076d3cc1309abc + sub.l @-er3,@(0x9abcdef0:32,er1) ;01076d3cc9309abcdef0 + sub.l @-er3,@(0xffff9abc:16,r2l.b) ;01076d3cd2309abc + sub.l @-er3,@(0xffff9abc:16,r2.w) ;01076d3ce2309abc + sub.l @-er3,@(0xffff9abc:16,er2.l) ;01076d3cf2309abc + sub.l @-er3,@(0x9abcdef0:32,r2l.b) ;01076d3cda309abcdef0 + sub.l @-er3,@(0x9abcdef0:32,r2.w) ;01076d3cea309abcdef0 + sub.l @-er3,@(0x9abcdef0:32,er2.l) ;01076d3cfa309abcdef0 + sub.l @-er3,@0xffff9abc:16 ;01076d3c40309abc + sub.l @-er3,@0x9abcdef0:32 ;01076d3c48309abcdef0 + + sub.l @er3+,@er1 ;01046d3c0130 + sub.l @er3+,@(0xc:2,er1) ;01046d3c3130 + sub.l @er3+,@-er1 ;01046d3cb130 + sub.l @er3+,@er1+ ;01046d3c8130 + sub.l @er3+,@er1- ;01046d3ca130 + sub.l @er3+,@+er1 ;01046d3c9130 + sub.l @er3+,@(0xffff9abc:16,er1) ;01046d3cc1309abc + sub.l @er3+,@(0x9abcdef0:32,er1) ;01046d3cc9309abcdef0 + sub.l @er3+,@(0xffff9abc:16,r2l.b) ;01046d3cd2309abc + sub.l @er3+,@(0xffff9abc:16,r2.w) ;01046d3ce2309abc + sub.l @er3+,@(0xffff9abc:16,er2.l) ;01046d3cf2309abc + sub.l @er3+,@(0x9abcdef0:32,r2l.b) ;01046d3cda309abcdef0 + sub.l @er3+,@(0x9abcdef0:32,r2.w) ;01046d3cea309abcdef0 + sub.l @er3+,@(0x9abcdef0:32,er2.l) ;01046d3cfa309abcdef0 + sub.l @er3+,@0xffff9abc:16 ;01046d3c40309abc + sub.l @er3+,@0x9abcdef0:32 ;01046d3c48309abcdef0 + + sub.l @er3-,@er1 ;01066d3c0130 + sub.l @er3-,@(0xc:2,er1) ;01066d3c3130 + sub.l @er3-,@-er1 ;01066d3cb130 + sub.l @er3-,@er1+ ;01066d3c8130 + sub.l @er3-,@er1- ;01066d3ca130 + sub.l @er3-,@+er1 ;01066d3c9130 + sub.l @er3-,@(0xffff9abc:16,er1) ;01066d3cc1309abc + sub.l @er3-,@(0x9abcdef0:32,er1) ;01066d3cc9309abcdef0 + sub.l @er3-,@(0xffff9abc:16,r2l.b) ;01066d3cd2309abc + sub.l @er3-,@(0xffff9abc:16,r2.w) ;01066d3ce2309abc + sub.l @er3-,@(0xffff9abc:16,er2.l) ;01066d3cf2309abc + sub.l @er3-,@(0x9abcdef0:32,r2l.b) ;01066d3cda309abcdef0 + sub.l @er3-,@(0x9abcdef0:32,r2.w) ;01066d3cea309abcdef0 + sub.l @er3-,@(0x9abcdef0:32,er2.l) ;01066d3cfa309abcdef0 + sub.l @er3-,@0xffff9abc:16 ;01066d3c40309abc + sub.l @er3-,@0x9abcdef0:32 ;01066d3c48309abcdef0 + + sub.l @+er3,@er1 ;01056d3c0130 + sub.l @+er3,@(0xc:2,er1) ;01056d3c3130 + sub.l @+er3,@-er1 ;01056d3cb130 + sub.l @+er3,@er1+ ;01056d3c8130 + sub.l @+er3,@er1- ;01056d3ca130 + sub.l @+er3,@+er1 ;01056d3c9130 + sub.l @+er3,@(0xffff9abc:16,er1) ;01056d3cc1309abc + sub.l @+er3,@(0x9abcdef0:32,er1) ;01056d3cc9309abcdef0 + sub.l @+er3,@(0xffff9abc:16,r2l.b) ;01056d3cd2309abc + sub.l @+er3,@(0xffff9abc:16,r2.w) ;01056d3ce2309abc + sub.l @+er3,@(0xffff9abc:16,er2.l) ;01056d3cf2309abc + sub.l @+er3,@(0x9abcdef0:32,r2l.b) ;01056d3cda309abcdef0 + sub.l @+er3,@(0x9abcdef0:32,r2.w) ;01056d3cea309abcdef0 + sub.l @+er3,@(0x9abcdef0:32,er2.l) ;01056d3cfa309abcdef0 + sub.l @+er3,@0xffff9abc:16 ;01056d3c40309abc + sub.l @+er3,@0x9abcdef0:32 ;01056d3c48309abcdef0 + + sub.l @(0x1234:16,er3),@er1 ;01046f3c12340130 + sub.l @(0x1234:16,er3),@(0xc:2,er1) ;01046f3c12343130 + sub.l @(0x1234:16,er3),@-er1 ;01046f3c1234b130 + sub.l @(0x1234:16,er3),@er1+ ;01046f3c12348130 + sub.l @(0x1234:16,er3),@er1- ;01046f3c1234a130 + sub.l @(0x1234:16,er3),@+er1 ;01046f3c12349130 + sub.l @(0x1234:16,er3),@(0xffff9abc:16,er1) ;01046f3c1234c1309abc + sub.l @(0x1234:16,er3),@(0x9abcdef0:32,er1) ;01046f3c1234c9309abcdef0 + sub.l @(0x1234:16,er3),@(0xffff9abc:16,r2l.b) ;01046f3c1234d2309abc + sub.l @(0x1234:16,er3),@(0xffff9abc:16,r2.w) ;01046f3c1234e2309abc + sub.l @(0x1234:16,er3),@(0xffff9abc:16,er2.l) ;01046f3c1234f2309abc + sub.l @(0x1234:16,er3),@(0x9abcdef0:32,r2l.b) ;01046f3c1234da309abcdef0 + sub.l @(0x1234:16,er3),@(0x9abcdef0:32,r2.w) ;01046f3c1234ea309abcdef0 + sub.l @(0x1234:16,er3),@(0x9abcdef0:32,er2.l) ;01046f3c1234fa309abcdef0 + sub.l @(0x1234:16,er3),@0xffff9abc:16 ;01046f3c123440309abc + sub.l @(0x1234:16,er3),@0x9abcdef0:32 ;01046f3c123448309abcdef0 + + sub.l @(0x12345678:32,er3),@er1 ;78b46b2c123456780130 + sub.l @(0x12345678:32,er3),@(0xc:2,er1) ;78b46b2c123456783130 + sub.l @(0x12345678:32,er3),@-er1 ;78b46b2c12345678b130 + sub.l @(0x12345678:32,er3),@er1+ ;78b46b2c123456788130 + sub.l @(0x12345678:32,er3),@er1- ;78b46b2c12345678a130 + sub.l @(0x12345678:32,er3),@+er1 ;78b46b2c123456789130 + sub.l @(0x12345678:32,er3),@(0xffff9abc:16,er1) ;78b46b2c12345678c1309abc + sub.l @(0x12345678:32,er3),@(0x9abcdef0:32,er1) ;78b46b2c12345678c9309abcdef0 + sub.l @(0x12345678:32,er3),@(0xffff9abc:16,r2l.b) ;78b46b2c12345678d2309abc + sub.l @(0x12345678:32,er3),@(0xffff9abc:16,r2.w) ;78b46b2c12345678e2309abc + sub.l @(0x12345678:32,er3),@(0xffff9abc:16,er2.l) ;78b46b2c12345678f2309abc + sub.l @(0x12345678:32,er3),@(0x9abcdef0:32,r2l.b) ;78b46b2c12345678da309abcdef0 + sub.l @(0x12345678:32,er3),@(0x9abcdef0:32,r2.w) ;78b46b2c12345678ea309abcdef0 + sub.l @(0x12345678:32,er3),@(0x9abcdef0:32,er2.l) ;78b46b2c12345678fa309abcdef0 + sub.l @(0x12345678:32,er3),@0xffff9abc:16 ;78b46b2c1234567840309abc + sub.l @(0x12345678:32,er3),@0x9abcdef0:32 ;78b46b2c1234567848309abcdef0 + + sub.l @(0x1234:16,r3l.b),@er1 ;01056f3c12340130 + sub.l @(0x1234:16,r3l.b),@(0xc:2,er1) ;01056f3c12343130 + sub.l @(0x1234:16,r3l.b),@-er1 ;01056f3c1234b130 + sub.l @(0x1234:16,r3l.b),@er1+ ;01056f3c12348130 + sub.l @(0x1234:16,r3l.b),@er1- ;01056f3c1234a130 + sub.l @(0x1234:16,r3l.b),@+er1 ;01056f3c12349130 + sub.l @(0x1234:16,r3l.b),@(0xffff9abc:16,er1) ;01056f3c1234c1309abc + sub.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1) ;01056f3c1234c9309abcdef0 + sub.l @(0x1234:16,r3l.b),@(0xffff9abc:16,r2l.b) ;01056f3c1234d2309abc + sub.l @(0x1234:16,r3l.b),@(0xffff9abc:16,r2.w) ;01056f3c1234e2309abc + sub.l @(0x1234:16,r3l.b),@(0xffff9abc:16,er2.l) ;01056f3c1234f2309abc + sub.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2l.b) ;01056f3c1234da309abcdef0 + sub.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2.w) ;01056f3c1234ea309abcdef0 + sub.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,er2.l) ;01056f3c1234fa309abcdef0 + sub.l @(0x1234:16,r3l.b),@0xffff9abc:16 ;01056f3c123440309abc + sub.l @(0x1234:16,r3l.b),@0x9abcdef0:32 ;01056f3c123448309abcdef0 + + sub.l @(0x1234:16,r3.w),@er1 ;01066f3c12340130 + sub.l @(0x1234:16,r3.w),@(0xc:2,er1) ;01066f3c12343130 + sub.l @(0x1234:16,r3.w),@-er1 ;01066f3c1234b130 + sub.l @(0x1234:16,r3.w),@er1+ ;01066f3c12348130 + sub.l @(0x1234:16,r3.w),@er1- ;01066f3c1234a130 + sub.l @(0x1234:16,r3.w),@+er1 ;01066f3c12349130 + sub.l @(0x1234:16,r3.w),@(0xffff9abc:16,er1) ;01066f3c1234c1309abc + sub.l @(0x1234:16,r3.w),@(0x9abcdef0:32,er1) ;01066f3c1234c9309abcdef0 + sub.l @(0x1234:16,r3.w),@(0xffff9abc:16,r2l.b) ;01066f3c1234d2309abc + sub.l @(0x1234:16,r3.w),@(0xffff9abc:16,r2.w) ;01066f3c1234e2309abc + sub.l @(0x1234:16,r3.w),@(0xffff9abc:16,er2.l) ;01066f3c1234f2309abc + sub.l @(0x1234:16,r3.w),@(0x9abcdef0:32,r2l.b) ;01066f3c1234da309abcdef0 + sub.l @(0x1234:16,r3.w),@(0x9abcdef0:32,r2.w) ;01066f3c1234ea309abcdef0 + sub.l @(0x1234:16,r3.w),@(0x9abcdef0:32,er2.l) ;01066f3c1234fa309abcdef0 + sub.l @(0x1234:16,r3.w),@0xffff9abc:16 ;01066f3c123440309abc + sub.l @(0x1234:16,r3.w),@0x9abcdef0:32 ;01066f3c123448309abcdef0 + + sub.l @(0x1234:16,er3.l),@er1 ;01076f3c12340130 + sub.l @(0x1234:16,er3.l),@(0xc:2,er1) ;01076f3c12343130 + sub.l @(0x1234:16,er3.l),@-er1 ;01076f3c1234b130 + sub.l @(0x1234:16,er3.l),@er1+ ;01076f3c12348130 + sub.l @(0x1234:16,er3.l),@er1- ;01076f3c1234a130 + sub.l @(0x1234:16,er3.l),@+er1 ;01076f3c12349130 + sub.l @(0x1234:16,er3.l),@(0xffff9abc:16,er1) ;01076f3c1234c1309abc + sub.l @(0x1234:16,er3.l),@(0x9abcdef0:32,er1) ;01076f3c1234c9309abcdef0 + sub.l @(0x1234:16,er3.l),@(0xffff9abc:16,r2l.b) ;01076f3c1234d2309abc + sub.l @(0x1234:16,er3.l),@(0xffff9abc:16,r2.w) ;01076f3c1234e2309abc + sub.l @(0x1234:16,er3.l),@(0xffff9abc:16,er2.l) ;01076f3c1234f2309abc + sub.l @(0x1234:16,er3.l),@(0x9abcdef0:32,r2l.b) ;01076f3c1234da309abcdef0 + sub.l @(0x1234:16,er3.l),@(0x9abcdef0:32,r2.w) ;01076f3c1234ea309abcdef0 + sub.l @(0x1234:16,er3.l),@(0x9abcdef0:32,er2.l) ;01076f3c1234fa309abcdef0 + sub.l @(0x1234:16,er3.l),@0xffff9abc:16 ;01076f3c123440309abc + sub.l @(0x1234:16,er3.l),@0x9abcdef0:32 ;01076f3c123448309abcdef0 + + sub.l @(0x12345678:32,r3l.b),@er1 ;78b56b2c123456780130 + sub.l @(0x12345678:32,r3l.b),@(0xc:2,er1) ;78b56b2c123456783130 + sub.l @(0x12345678:32,r3l.b),@-er1 ;78b56b2c12345678b130 + sub.l @(0x12345678:32,r3l.b),@er1+ ;78b56b2c123456788130 + sub.l @(0x12345678:32,r3l.b),@er1- ;78b56b2c12345678a130 + sub.l @(0x12345678:32,r3l.b),@+er1 ;78b56b2c123456789130 + sub.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,er1) ;78b56b2c12345678c1309abc + sub.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1) ;78b56b2c12345678c9309abcdef0 + sub.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2l.b) ;78b56b2c12345678d2309abc + sub.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2.w) ;78b56b2c12345678e2309abc + sub.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,er2.l) ;78b56b2c12345678f2309abc + sub.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2l.b) ;78b56b2c12345678da309abcdef0 + sub.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2.w) ;78b56b2c12345678ea309abcdef0 + sub.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er2.l) ;78b56b2c12345678fa309abcdef0 + sub.l @(0x12345678:32,r3l.b),@0xffff9abc:16 ;78b56b2c1234567840309abc + sub.l @(0x12345678:32,r3l.b),@0x9abcdef0:32 ;78b56b2c1234567848309abcdef0 + + sub.l @(0x12345678:32,r3.w),@er1 ;78b66b2c123456780130 + sub.l @(0x12345678:32,r3.w),@(0xc:2,er1) ;78b66b2c123456783130 + sub.l @(0x12345678:32,r3.w),@-er1 ;78b66b2c12345678b130 + sub.l @(0x12345678:32,r3.w),@er1+ ;78b66b2c123456788130 + sub.l @(0x12345678:32,r3.w),@er1- ;78b66b2c12345678a130 + sub.l @(0x12345678:32,r3.w),@+er1 ;78b66b2c123456789130 + sub.l @(0x12345678:32,r3.w),@(0xffff9abc:16,er1) ;78b66b2c12345678c1309abc + sub.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1) ;78b66b2c12345678c9309abcdef0 + sub.l @(0x12345678:32,r3.w),@(0xffff9abc:16,r2l.b) ;78b66b2c12345678d2309abc + sub.l @(0x12345678:32,r3.w),@(0xffff9abc:16,r2.w) ;78b66b2c12345678e2309abc + sub.l @(0x12345678:32,r3.w),@(0xffff9abc:16,er2.l) ;78b66b2c12345678f2309abc + sub.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2l.b) ;78b66b2c12345678da309abcdef0 + sub.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2.w) ;78b66b2c12345678ea309abcdef0 + sub.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,er2.l) ;78b66b2c12345678fa309abcdef0 + sub.l @(0x12345678:32,r3.w),@0xffff9abc:16 ;78b66b2c1234567840309abc + sub.l @(0x12345678:32,r3.w),@0x9abcdef0:32 ;78b66b2c1234567848309abcdef0 + + sub.l @(0x12345678:32,er3.l),@er1 ;78b76b2c123456780130 + sub.l @(0x12345678:32,er3.l),@(0xc:2,er1) ;78b76b2c123456783130 + sub.l @(0x12345678:32,er3.l),@-er1 ;78b76b2c12345678b130 + sub.l @(0x12345678:32,er3.l),@er1+ ;78b76b2c123456788130 + sub.l @(0x12345678:32,er3.l),@er1- ;78b76b2c12345678a130 + sub.l @(0x12345678:32,er3.l),@+er1 ;78b76b2c123456789130 + sub.l @(0x12345678:32,er3.l),@(0xffff9abc:16,er1) ;78b76b2c12345678c1309abc + sub.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1) ;78b76b2c12345678c9309abcdef0 + sub.l @(0x12345678:32,er3.l),@(0xffff9abc:16,r2l.b) ;78b76b2c12345678d2309abc + sub.l @(0x12345678:32,er3.l),@(0xffff9abc:16,r2.w) ;78b76b2c12345678e2309abc + sub.l @(0x12345678:32,er3.l),@(0xffff9abc:16,er2.l) ;78b76b2c12345678f2309abc + sub.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2l.b) ;78b76b2c12345678da309abcdef0 + sub.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2.w) ;78b76b2c12345678ea309abcdef0 + sub.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,er2.l) ;78b76b2c12345678fa309abcdef0 + sub.l @(0x12345678:32,er3.l),@0xffff9abc:16 ;78b76b2c1234567840309abc + sub.l @(0x12345678:32,er3.l),@0x9abcdef0:32 ;78b76b2c1234567848309abcdef0 + + sub.l @0x1234:16,@er1 ;01046b0c12340130 + sub.l @0x1234:16,@(0xc:2,er1) ;01046b0c12343130 + sub.l @0x1234:16,@-er1 ;01046b0c1234b130 + sub.l @0x1234:16,@er1+ ;01046b0c12348130 + sub.l @0x1234:16,@er1- ;01046b0c1234a130 + sub.l @0x1234:16,@+er1 ;01046b0c12349130 + sub.l @0x1234:16,@(0xffff9abc:16,er1) ;01046b0c1234c1309abc + sub.l @0x1234:16,@(0x9abcdef0:32,er1) ;01046b0c1234c9309abcdef0 + sub.l @0x1234:16,@(0xffff9abc:16,r2l.b) ;01046b0c1234d2309abc + sub.l @0x1234:16,@(0xffff9abc:16,r2.w) ;01046b0c1234e2309abc + sub.l @0x1234:16,@(0xffff9abc:16,er2.l) ;01046b0c1234f2309abc + sub.l @0x1234:16,@(0x9abcdef0:32,r2l.b) ;01046b0c1234da309abcdef0 + sub.l @0x1234:16,@(0x9abcdef0:32,r2.w) ;01046b0c1234ea309abcdef0 + sub.l @0x1234:16,@(0x9abcdef0:32,er2.l) ;01046b0c1234fa309abcdef0 + sub.l @0x1234:16,@0xffff9abc:16 ;01046b0c123440309abc + sub.l @0x1234:16,@0x9abcdef0:32 ;01046b0c123448309abcdef0 + + sub.l @0x12345678:32,@er1 ;01046b2c123456780130 + sub.l @0x12345678:32,@(0xc:2,er1) ;01046b2c123456783130 + sub.l @0x12345678:32,@-er1 ;01046b2c12345678b130 + sub.l @0x12345678:32,@er1+ ;01046b2c123456788130 + sub.l @0x12345678:32,@er1- ;01046b2c12345678a130 + sub.l @0x12345678:32,@+er1 ;01046b2c123456789130 + sub.l @0x12345678:32,@(0xffff9abc:16,er1) ;01046b2c12345678c1309abc + sub.l @0x12345678:32,@(0x9abcdef0:32,er1) ;01046b2c12345678c9309abcdef0 + sub.l @0x12345678:32,@(0xffff9abc:16,r2l.b) ;01046b2c12345678d2309abc + sub.l @0x12345678:32,@(0xffff9abc:16,r2.w) ;01046b2c12345678e2309abc + sub.l @0x12345678:32,@(0xffff9abc:16,er2.l) ;01046b2c12345678f2309abc + sub.l @0x12345678:32,@(0x9abcdef0:32,r2l.b) ;01046b2c12345678da309abcdef0 + sub.l @0x12345678:32,@(0x9abcdef0:32,r2.w) ;01046b2c12345678ea309abcdef0 + sub.l @0x12345678:32,@(0x9abcdef0:32,er2.l) ;01046b2c12345678fa309abcdef0 + sub.l @0x12345678:32,@0xffff9abc:16 ;01046b2c1234567840309abc + sub.l @0x12345678:32,@0x9abcdef0:32 ;01046b2c1234567848309abcdef0 + + .end diff --git a/gdb/testsuite/gdb.disasm/t05_cmp.exp b/gdb/testsuite/gdb.disasm/t05_cmp.exp new file mode 100644 index 0000000..8578000 --- /dev/null +++ b/gdb/testsuite/gdb.disasm/t05_cmp.exp @@ -0,0 +1,1770 @@ +# Copyright (C) 2003 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# Please email any bugs, comments, and/or additions to this file to: +# bug-gdb@prep.ai.mit.edu + +# This file was written by Michael Snyder (msnyder@redhat.com) + +if $tracelevel then { + strace $tracelevel +} + +if ![istarget "h8300*-*-*"] { + verbose "Tests ignored for all but h8300s based targets." + return +} + +set prms_id 0 +set bug_id 0 + +set testfile "t05_cmp" +set srcfile ${srcdir}/${subdir}/${testfile}.s +set objfile ${objdir}/${subdir}/${testfile}.o +set binfile ${objdir}/${subdir}/${testfile}.x + +set asm-flags ""; +set link-flags "-m h8300sxelf"; + + +if {[target_assemble $srcfile $objfile "${asm-flags}"] != ""} then { + gdb_suppress_entire_file "Testcase assembly failed, so all tests in this file will automatically fail." +} + +if {[target_link $objfile $binfile "${link-flags}"] != ""} then { + gdb_suppress_entire_file "Testcase link failed, so all tests in this file will automatically fail." +} + +gdb_start +gdb_reinitialize_dir $srcdir/$subdir +gdb_load $binfile + +gdb_test "x /i _start" "cmp.b\t@er3,@er1" \ + "cmp.b @er3,@er1" +gdb_test "x" "cmp.b\t@er3,@\\(0x3(:2|),er1\\)" \ + "cmp.b @er3,@(0x3:2,er1)" +gdb_test "x" "cmp.b\t@er3,@-er1" \ + "cmp.b @er3,@-er1" +gdb_test "x" "cmp.b\t@er3,@er1\\+" \ + "cmp.b @er3,@er1+" +gdb_test "x" "cmp.b\t@er3,@er1-" \ + "cmp.b @er3,@er1-" +gdb_test "x" "cmp.b\t@er3,@\\+er1" \ + "cmp.b @er3,@+er1" +gdb_test "x" "cmp.b\t@er3,@\\(0x9abc(:16|),er1\\)" \ + "cmp.b @er3,@(0x9abc:16,er1)" +gdb_test "x" "cmp.b\t@er3,@\\(0x9abcdef0(:32|),er1\\)" \ + "cmp.b @er3,@(0x9abcdef0:32,er1)" +gdb_test "x" "cmp.b\t@er3,@\\(0x9abc(:16|),r2l.b\\)" \ + "cmp.b @er3,@(0x9abc:16,r2l.b)" +gdb_test "x" "cmp.b\t@er3,@\\(0x9abc(:16|),r2.w\\)" \ + "cmp.b @er3,@(0x9abc:16,r2.w)" +gdb_test "x" "cmp.b\t@er3,@\\(0x9abc(:16|),er2.l\\)" \ + "cmp.b @er3,@(0x9abc:16,er2.l)" +gdb_test "x" "cmp.b\t@er3,@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "cmp.b @er3,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "cmp.b\t@er3,@\\(0x9abcdef0(:32|),r2.w\\)" \ + "cmp.b @er3,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "cmp.b\t@er3,@\\(0x9abcdef0(:32|),er2.l\\)" \ + "cmp.b @er3,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "cmp.b\t@er3,@0x9abc(:16|)" \ + "cmp.b @er3,@0x9abc:16" +gdb_test "x" "cmp.b\t@er3,@0x9abcdef0(:32|)" \ + "cmp.b @er3,@0x9abcdef0:32" +gdb_test "x" "cmp.b\t@-er3,@er1" \ + "cmp.b @-er3,@er1" +gdb_test "x" "cmp.b\t@-er3,@\\(0x3(:2|),er1\\)" \ + "cmp.b @-er3,@(0x3:2,er1)" +gdb_test "x" "cmp.b\t@-er3,@-er1" \ + "cmp.b @-er3,@-er1" +gdb_test "x" "cmp.b\t@-er3,@er1\\+" \ + "cmp.b @-er3,@er1+" +gdb_test "x" "cmp.b\t@-er3,@er1-" \ + "cmp.b @-er3,@er1-" +gdb_test "x" "cmp.b\t@-er3,@\\+er1" \ + "cmp.b @-er3,@+er1" +gdb_test "x" "cmp.b\t@-er3,@\\(0x9abc(:16|),er1\\)" \ + "cmp.b @-er3,@(0x9abc:16,er1)" +gdb_test "x" "cmp.b\t@-er3,@\\(0x9abcdef0(:32|),er1\\)" \ + "cmp.b @-er3,@(0x9abcdef0:32,er1)" +gdb_test "x" "cmp.b\t@-er3,@\\(0x9abc(:16|),r2l.b\\)" \ + "cmp.b @-er3,@(0x9abc:16,r2l.b)" +gdb_test "x" "cmp.b\t@-er3,@\\(0x9abc(:16|),r2.w\\)" \ + "cmp.b @-er3,@(0x9abc:16,r2.w)" +gdb_test "x" "cmp.b\t@-er3,@\\(0x9abc(:16|),er2.l\\)" \ + "cmp.b @-er3,@(0x9abc:16,er2.l)" +gdb_test "x" "cmp.b\t@-er3,@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "cmp.b @-er3,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "cmp.b\t@-er3,@\\(0x9abcdef0(:32|),r2.w\\)" \ + "cmp.b @-er3,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "cmp.b\t@-er3,@\\(0x9abcdef0(:32|),er2.l\\)" \ + "cmp.b @-er3,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "cmp.b\t@-er3,@0x9abc(:16|)" \ + "cmp.b @-er3,@0x9abc:16" +gdb_test "x" "cmp.b\t@-er3,@0x9abcdef0(:32|)" \ + "cmp.b @-er3,@0x9abcdef0:32" +gdb_test "x" "cmp.b\t@er3\\+,@er1" \ + "cmp.b @er3+,@er1" +gdb_test "x" "cmp.b\t@er3\\+,@\\(0x3(:2|),er1\\)" \ + "cmp.b @er3+,@(0x3:2,er1)" +gdb_test "x" "cmp.b\t@er3\\+,@-er1" \ + "cmp.b @er3+,@-er1" +gdb_test "x" "cmp.b\t@er3\\+,@er1\\+" \ + "cmp.b @er3+,@er1+" +gdb_test "x" "cmp.b\t@er3\\+,@er1-" \ + "cmp.b @er3+,@er1-" +gdb_test "x" "cmp.b\t@er3\\+,@\\+er1" \ + "cmp.b @er3+,@+er1" +gdb_test "x" "cmp.b\t@er3\\+,@\\(0x9abc(:16|),er1\\)" \ + "cmp.b @er3+,@(0x9abc:16,er1)" +gdb_test "x" "cmp.b\t@er3\\+,@\\(0x9abcdef0(:32|),er1\\)" \ + "cmp.b @er3+,@(0x9abcdef0:32,er1)" +gdb_test "x" "cmp.b\t@er3\\+,@\\(0x9abc(:16|),r2l.b\\)" \ + "cmp.b @er3+,@(0x9abc:16,r2l.b)" +gdb_test "x" "cmp.b\t@er3\\+,@\\(0x9abc(:16|),r2.w\\)" \ + "cmp.b @er3+,@(0x9abc:16,r2.w)" +gdb_test "x" "cmp.b\t@er3\\+,@\\(0x9abc(:16|),er2.l\\)" \ + "cmp.b @er3+,@(0x9abc:16,er2.l)" +gdb_test "x" "cmp.b\t@er3\\+,@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "cmp.b @er3+,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "cmp.b\t@er3\\+,@\\(0x9abcdef0(:32|),r2.w\\)" \ + "cmp.b @er3+,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "cmp.b\t@er3\\+,@\\(0x9abcdef0(:32|),er2.l\\)" \ + "cmp.b @er3+,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "cmp.b\t@er3\\+,@0x9abc(:16|)" \ + "cmp.b @er3+,@0x9abc:16" +gdb_test "x" "cmp.b\t@er3\\+,@0x9abcdef0(:32|)" \ + "cmp.b @er3+,@0x9abcdef0:32" +gdb_test "x" "cmp.b\t@er3-,@er1" \ + "cmp.b @er3-,@er1" +gdb_test "x" "cmp.b\t@er3-,@\\(0x3(:2|),er1\\)" \ + "cmp.b @er3-,@(0x3:2,er1)" +gdb_test "x" "cmp.b\t@er3-,@-er1" \ + "cmp.b @er3-,@-er1" +gdb_test "x" "cmp.b\t@er3-,@er1\\+" \ + "cmp.b @er3-,@er1+" +gdb_test "x" "cmp.b\t@er3-,@er1-" \ + "cmp.b @er3-,@er1-" +gdb_test "x" "cmp.b\t@er3-,@\\+er1" \ + "cmp.b @er3-,@+er1" +gdb_test "x" "cmp.b\t@er3-,@\\(0x9abc(:16|),er1\\)" \ + "cmp.b @er3-,@(0x9abc:16,er1)" +gdb_test "x" "cmp.b\t@er3-,@\\(0x9abcdef0(:32|),er1\\)" \ + "cmp.b @er3-,@(0x9abcdef0:32,er1)" +gdb_test "x" "cmp.b\t@er3-,@\\(0x9abc(:16|),r2l.b\\)" \ + "cmp.b @er3-,@(0x9abc:16,r2l.b)" +gdb_test "x" "cmp.b\t@er3-,@\\(0x9abc(:16|),r2.w\\)" \ + "cmp.b @er3-,@(0x9abc:16,r2.w)" +gdb_test "x" "cmp.b\t@er3-,@\\(0x9abc(:16|),er2.l\\)" \ + "cmp.b @er3-,@(0x9abc:16,er2.l)" +gdb_test "x" "cmp.b\t@er3-,@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "cmp.b @er3-,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "cmp.b\t@er3-,@\\(0x9abcdef0(:32|),r2.w\\)" \ + "cmp.b @er3-,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "cmp.b\t@er3-,@\\(0x9abcdef0(:32|),er2.l\\)" \ + "cmp.b @er3-,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "cmp.b\t@er3-,@0x9abc(:16|)" \ + "cmp.b @er3-,@0x9abc:16" +gdb_test "x" "cmp.b\t@er3-,@0x9abcdef0(:32|)" \ + "cmp.b @er3-,@0x9abcdef0:32" +gdb_test "x" "cmp.b\t@\\+er3,@er1" \ + "cmp.b @+er3,@er1" +gdb_test "x" "cmp.b\t@\\+er3,@\\(0x3(:2|),er1\\)" \ + "cmp.b @+er3,@(0x3:2,er1)" +gdb_test "x" "cmp.b\t@\\+er3,@-er1" \ + "cmp.b @+er3,@-er1" +gdb_test "x" "cmp.b\t@\\+er3,@er1\\+" \ + "cmp.b @+er3,@er1+" +gdb_test "x" "cmp.b\t@\\+er3,@er1-" \ + "cmp.b @+er3,@er1-" +gdb_test "x" "cmp.b\t@\\+er3,@\\+er1" \ + "cmp.b @+er3,@+er1" +gdb_test "x" "cmp.b\t@\\+er3,@\\(0x9abc(:16|),er1\\)" \ + "cmp.b @+er3,@(0x9abc:16,er1)" +gdb_test "x" "cmp.b\t@\\+er3,@\\(0x9abcdef0(:32|),er1\\)" \ + "cmp.b @+er3,@(0x9abcdef0:32,er1)" +gdb_test "x" "cmp.b\t@\\+er3,@\\(0x9abc(:16|),r2l.b\\)" \ + "cmp.b @+er3,@(0x9abc:16,r2l.b)" +gdb_test "x" "cmp.b\t@\\+er3,@\\(0x9abc(:16|),r2.w\\)" \ + "cmp.b @+er3,@(0x9abc:16,r2.w)" +gdb_test "x" "cmp.b\t@\\+er3,@\\(0x9abc(:16|),er2.l\\)" \ + "cmp.b @+er3,@(0x9abc:16,er2.l)" +gdb_test "x" "cmp.b\t@\\+er3,@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "cmp.b @+er3,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "cmp.b\t@\\+er3,@\\(0x9abcdef0(:32|),r2.w\\)" \ + "cmp.b @+er3,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "cmp.b\t@\\+er3,@\\(0x9abcdef0(:32|),er2.l\\)" \ + "cmp.b @+er3,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "cmp.b\t@\\+er3,@0x9abc(:16|)" \ + "cmp.b @+er3,@0x9abc:16" +gdb_test "x" "cmp.b\t@\\+er3,@0x9abcdef0(:32|)" \ + "cmp.b @+er3,@0x9abcdef0:32" +gdb_test "x" "cmp.b\t@\\(0x1234(:16|),er3\\),@er1" \ + "cmp.b @(0x1234:16,er3),@er1" +gdb_test "x" "cmp.b\t@\\(0x1234(:16|),er3\\),@\\(0x3(:2|),er1\\)" \ + "cmp.b @(0x1234:16,er3),@(0x3:2,er1)" +gdb_test "x" "cmp.b\t@\\(0x1234(:16|),er3\\),@-er1" \ + "cmp.b @(0x1234:16,er3),@-er1" +gdb_test "x" "cmp.b\t@\\(0x1234(:16|),er3\\),@er1\\+" \ + "cmp.b @(0x1234:16,er3),@er1+" +gdb_test "x" "cmp.b\t@\\(0x1234(:16|),er3\\),@er1-" \ + "cmp.b @(0x1234:16,er3),@er1-" +gdb_test "x" "cmp.b\t@\\(0x1234(:16|),er3\\),@\\+er1" \ + "cmp.b @(0x1234:16,er3),@+er1" +gdb_test "x" "cmp.b\t@\\(0x1234(:16|),er3\\),@\\(0x9abc(:16|),er1\\)" \ + "cmp.b @(0x1234:16,er3),@(0x9abc:16,er1)" +gdb_test "x" "cmp.b\t@\\(0x1234(:16|),er3\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "cmp.b @(0x1234:16,er3),@(0x9abcdef0:32,er1)" +gdb_test "x" "cmp.b\t@\\(0x1234(:16|),er3\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "cmp.b @(0x1234:16,er3),@(0x9abc:16,r2l.b)" +gdb_test "x" "cmp.b\t@\\(0x1234(:16|),er3\\),@\\(0x9abc(:16|),r2.w\\)" \ + "cmp.b @(0x1234:16,er3),@(0x9abc:16,r2.w)" +gdb_test "x" "cmp.b\t@\\(0x1234(:16|),er3\\),@\\(0x9abc(:16|),er2.l\\)" \ + "cmp.b @(0x1234:16,er3),@(0x9abc:16,er2.l)" +gdb_test "x" "cmp.b\t@\\(0x1234(:16|),er3\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "cmp.b @(0x1234:16,er3),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "cmp.b\t@\\(0x1234(:16|),er3\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "cmp.b @(0x1234:16,er3),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "cmp.b\t@\\(0x1234(:16|),er3\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "cmp.b @(0x1234:16,er3),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "cmp.b\t@\\(0x1234(:16|),er3\\),@0x9abc(:16|)" \ + "cmp.b @(0x1234:16,er3),@0x9abc:16" +gdb_test "x" "cmp.b\t@\\(0x1234(:16|),er3\\),@0x9abcdef0(:32|)" \ + "cmp.b @(0x1234:16,er3),@0x9abcdef0:32" +gdb_test "x" "cmp.b\t@\\(0x12345678(:32|),er3\\),@er1" \ + "cmp.b @(0x12345678:32,er3),@er1" +gdb_test "x" "cmp.b\t@\\(0x12345678(:32|),er3\\),@\\(0x3(:2|),er1\\)" \ + "cmp.b @(0x12345678:32,er3),@(0x3:2,er1)" +gdb_test "x" "cmp.b\t@\\(0x12345678(:32|),er3\\),@-er1" \ + "cmp.b @(0x12345678:32,er3),@-er1" +gdb_test "x" "cmp.b\t@\\(0x12345678(:32|),er3\\),@er1\\+" \ + "cmp.b @(0x12345678:32,er3),@er1+" +gdb_test "x" "cmp.b\t@\\(0x12345678(:32|),er3\\),@er1-" \ + "cmp.b @(0x12345678:32,er3),@er1-" +gdb_test "x" "cmp.b\t@\\(0x12345678(:32|),er3\\),@\\+er1" \ + "cmp.b @(0x12345678:32,er3),@+er1" +gdb_test "x" "cmp.b\t@\\(0x12345678(:32|),er3\\),@\\(0x9abc(:16|),er1\\)" \ + "cmp.b @(0x12345678:32,er3),@(0x9abc:16,er1)" +gdb_test "x" "cmp.b\t@\\(0x12345678(:32|),er3\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "cmp.b @(0x12345678:32,er3),@(0x9abcdef0:32,er1)" +gdb_test "x" "cmp.b\t@\\(0x12345678(:32|),er3\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "cmp.b @(0x12345678:32,er3),@(0x9abc:16,r2l.b)" +gdb_test "x" "cmp.b\t@\\(0x12345678(:32|),er3\\),@\\(0x9abc(:16|),r2.w\\)" \ + "cmp.b @(0x12345678:32,er3),@(0x9abc:16,r2.w)" +gdb_test "x" "cmp.b\t@\\(0x12345678(:32|),er3\\),@\\(0x9abc(:16|),er2.l\\)" \ + "cmp.b @(0x12345678:32,er3),@(0x9abc:16,er2.l)" +gdb_test "x" "cmp.b\t@\\(0x12345678(:32|),er3\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "cmp.b @(0x12345678:32,er3),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "cmp.b\t@\\(0x12345678(:32|),er3\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "cmp.b @(0x12345678:32,er3),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "cmp.b\t@\\(0x12345678(:32|),er3\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "cmp.b @(0x12345678:32,er3),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "cmp.b\t@\\(0x12345678(:32|),er3\\),@0x9abc(:16|)" \ + "cmp.b @(0x12345678:32,er3),@0x9abc:16" +gdb_test "x" "cmp.b\t@\\(0x12345678(:32|),er3\\),@0x9abcdef0(:32|)" \ + "cmp.b @(0x12345678:32,er3),@0x9abcdef0:32" +gdb_test "x" "cmp.b\t@\\(0x1234(:16|),r3l.b\\),@er1" \ + "cmp.b @(0x1234:16,r3l.b),@er1" +gdb_test "x" "cmp.b\t@\\(0x1234(:16|),r3l.b\\),@\\(0x3(:2|),er1\\)" \ + "cmp.b @(0x1234:16,r3l.b),@(0x3:2,er1)" +gdb_test "x" "cmp.b\t@\\(0x1234(:16|),r3l.b\\),@-er1" \ + "cmp.b @(0x1234:16,r3l.b),@-er1" +gdb_test "x" "cmp.b\t@\\(0x1234(:16|),r3l.b\\),@er1\\+" \ + "cmp.b @(0x1234:16,r3l.b),@er1+" +gdb_test "x" "cmp.b\t@\\(0x1234(:16|),r3l.b\\),@er1-" \ + "cmp.b @(0x1234:16,r3l.b),@er1-" +gdb_test "x" "cmp.b\t@\\(0x1234(:16|),r3l.b\\),@\\+er1" \ + "cmp.b @(0x1234:16,r3l.b),@+er1" +gdb_test "x" "cmp.b\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abc(:16|),er1\\)" \ + "cmp.b @(0x1234:16,r3l.b),@(0x9abc:16,er1)" +gdb_test "x" "cmp.b\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "cmp.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1)" +gdb_test "x" "cmp.b\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "cmp.b @(0x1234:16,r3l.b),@(0x9abc:16,r2l.b)" +gdb_test "x" "cmp.b\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abc(:16|),r2.w\\)" \ + "cmp.b @(0x1234:16,r3l.b),@(0x9abc:16,r2.w)" +gdb_test "x" "cmp.b\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abc(:16|),er2.l\\)" \ + "cmp.b @(0x1234:16,r3l.b),@(0x9abc:16,er2.l)" +gdb_test "x" "cmp.b\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "cmp.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "cmp.b\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "cmp.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "cmp.b\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "cmp.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "cmp.b\t@\\(0x1234(:16|),r3l.b\\),@0x9abc(:16|)" \ + "cmp.b @(0x1234:16,r3l.b),@0x9abc:16" +gdb_test "x" "cmp.b\t@\\(0x1234(:16|),r3l.b\\),@0x9abcdef0(:32|)" \ + "cmp.b @(0x1234:16,r3l.b),@0x9abcdef0:32" +gdb_test "x" "cmp.b\t@\\(0x1234(:16|),r3.w\\),@er1" \ + "cmp.b @(0x1234:16,r3.w),@er1" +gdb_test "x" "cmp.b\t@\\(0x1234(:16|),r3.w\\),@\\(0x3(:2|),er1\\)" \ + "cmp.b @(0x1234:16,r3.w),@(0x3:2,er1)" +gdb_test "x" "cmp.b\t@\\(0x1234(:16|),r3.w\\),@-er1" \ + "cmp.b @(0x1234:16,r3.w),@-er1" +gdb_test "x" "cmp.b\t@\\(0x1234(:16|),r3.w\\),@er1\\+" \ + "cmp.b @(0x1234:16,r3.w),@er1+" +gdb_test "x" "cmp.b\t@\\(0x1234(:16|),r3.w\\),@er1-" \ + "cmp.b @(0x1234:16,r3.w),@er1-" +gdb_test "x" "cmp.b\t@\\(0x1234(:16|),r3.w\\),@\\+er1" \ + "cmp.b @(0x1234:16,r3.w),@+er1" +gdb_test "x" "cmp.b\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abc(:16|),er1\\)" \ + "cmp.b @(0x1234:16,r3.w),@(0x9abc:16,er1)" +gdb_test "x" "cmp.b\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "cmp.b @(0x1234:16,r3.w),@(0x9abcdef0:32,er1)" +gdb_test "x" "cmp.b\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "cmp.b @(0x1234:16,r3.w),@(0x9abc:16,r2l.b)" +gdb_test "x" "cmp.b\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abc(:16|),r2.w\\)" \ + "cmp.b @(0x1234:16,r3.w),@(0x9abc:16,r2.w)" +gdb_test "x" "cmp.b\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abc(:16|),er2.l\\)" \ + "cmp.b @(0x1234:16,r3.w),@(0x9abc:16,er2.l)" +gdb_test "x" "cmp.b\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "cmp.b @(0x1234:16,r3.w),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "cmp.b\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "cmp.b @(0x1234:16,r3.w),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "cmp.b\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "cmp.b @(0x1234:16,r3.w),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "cmp.b\t@\\(0x1234(:16|),r3.w\\),@0x9abc(:16|)" \ + "cmp.b @(0x1234:16,r3.w),@0x9abc:16" +gdb_test "x" "cmp.b\t@\\(0x1234(:16|),r3.w\\),@0x9abcdef0(:32|)" \ + "cmp.b @(0x1234:16,r3.w),@0x9abcdef0:32" +gdb_test "x" "cmp.b\t@\\(0x1234(:16|),er3.l\\),@er1" \ + "cmp.b @(0x1234:16,er3.l),@er1" +gdb_test "x" "cmp.b\t@\\(0x1234(:16|),er3.l\\),@\\(0x3(:2|),er1\\)" \ + "cmp.b @(0x1234:16,er3.l),@(0x3:2,er1)" +gdb_test "x" "cmp.b\t@\\(0x1234(:16|),er3.l\\),@-er1" \ + "cmp.b @(0x1234:16,er3.l),@-er1" +gdb_test "x" "cmp.b\t@\\(0x1234(:16|),er3.l\\),@er1\\+" \ + "cmp.b @(0x1234:16,er3.l),@er1+" +gdb_test "x" "cmp.b\t@\\(0x1234(:16|),er3.l\\),@er1-" \ + "cmp.b @(0x1234:16,er3.l),@er1-" +gdb_test "x" "cmp.b\t@\\(0x1234(:16|),er3.l\\),@\\+er1" \ + "cmp.b @(0x1234:16,er3.l),@+er1" +gdb_test "x" "cmp.b\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abc(:16|),er1\\)" \ + "cmp.b @(0x1234:16,er3.l),@(0x9abc:16,er1)" +gdb_test "x" "cmp.b\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "cmp.b @(0x1234:16,er3.l),@(0x9abcdef0:32,er1)" +gdb_test "x" "cmp.b\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "cmp.b @(0x1234:16,er3.l),@(0x9abc:16,r2l.b)" +gdb_test "x" "cmp.b\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abc(:16|),r2.w\\)" \ + "cmp.b @(0x1234:16,er3.l),@(0x9abc:16,r2.w)" +gdb_test "x" "cmp.b\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abc(:16|),er2.l\\)" \ + "cmp.b @(0x1234:16,er3.l),@(0x9abc:16,er2.l)" +gdb_test "x" "cmp.b\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "cmp.b @(0x1234:16,er3.l),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "cmp.b\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "cmp.b @(0x1234:16,er3.l),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "cmp.b\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "cmp.b @(0x1234:16,er3.l),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "cmp.b\t@\\(0x1234(:16|),er3.l\\),@0x9abc(:16|)" \ + "cmp.b @(0x1234:16,er3.l),@0x9abc:16" +gdb_test "x" "cmp.b\t@\\(0x1234(:16|),er3.l\\),@0x9abcdef0(:32|)" \ + "cmp.b @(0x1234:16,er3.l),@0x9abcdef0:32" +gdb_test "x" "cmp.b\t@\\(0x12345678(:32|),r3l.b\\),@er1" \ + "cmp.b @(0x12345678:32,r3l.b),@er1" +gdb_test "x" "cmp.b\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x3(:2|),er1\\)" \ + "cmp.b @(0x12345678:32,r3l.b),@(0x3:2,er1)" +gdb_test "x" "cmp.b\t@\\(0x12345678(:32|),r3l.b\\),@-er1" \ + "cmp.b @(0x12345678:32,r3l.b),@-er1" +gdb_test "x" "cmp.b\t@\\(0x12345678(:32|),r3l.b\\),@er1\\+" \ + "cmp.b @(0x12345678:32,r3l.b),@er1+" +gdb_test "x" "cmp.b\t@\\(0x12345678(:32|),r3l.b\\),@er1-" \ + "cmp.b @(0x12345678:32,r3l.b),@er1-" +gdb_test "x" "cmp.b\t@\\(0x12345678(:32|),r3l.b\\),@\\+er1" \ + "cmp.b @(0x12345678:32,r3l.b),@+er1" +gdb_test "x" "cmp.b\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abc(:16|),er1\\)" \ + "cmp.b @(0x12345678:32,r3l.b),@(0x9abc:16,er1)" +gdb_test "x" "cmp.b\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "cmp.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1)" +gdb_test "x" "cmp.b\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "cmp.b @(0x12345678:32,r3l.b),@(0x9abc:16,r2l.b)" +gdb_test "x" "cmp.b\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abc(:16|),r2.w\\)" \ + "cmp.b @(0x12345678:32,r3l.b),@(0x9abc:16,r2.w)" +gdb_test "x" "cmp.b\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abc(:16|),er2.l\\)" \ + "cmp.b @(0x12345678:32,r3l.b),@(0x9abc:16,er2.l)" +gdb_test "x" "cmp.b\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "cmp.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "cmp.b\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "cmp.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "cmp.b\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "cmp.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "cmp.b\t@\\(0x12345678(:32|),r3l.b\\),@0x9abc(:16|)" \ + "cmp.b @(0x12345678:32,r3l.b),@0x9abc:16" +gdb_test "x" "cmp.b\t@\\(0x12345678(:32|),r3l.b\\),@0x9abcdef0(:32|)" \ + "cmp.b @(0x12345678:32,r3l.b),@0x9abcdef0:32" +gdb_test "x" "cmp.b\t@\\(0x12345678(:32|),r3.w\\),@er1" \ + "cmp.b @(0x12345678:32,r3.w),@er1" +gdb_test "x" "cmp.b\t@\\(0x12345678(:32|),r3.w\\),@\\(0x3(:2|),er1\\)" \ + "cmp.b @(0x12345678:32,r3.w),@(0x3:2,er1)" +gdb_test "x" "cmp.b\t@\\(0x12345678(:32|),r3.w\\),@-er1" \ + "cmp.b @(0x12345678:32,r3.w),@-er1" +gdb_test "x" "cmp.b\t@\\(0x12345678(:32|),r3.w\\),@er1\\+" \ + "cmp.b @(0x12345678:32,r3.w),@er1+" +gdb_test "x" "cmp.b\t@\\(0x12345678(:32|),r3.w\\),@er1-" \ + "cmp.b @(0x12345678:32,r3.w),@er1-" +gdb_test "x" "cmp.b\t@\\(0x12345678(:32|),r3.w\\),@\\+er1" \ + "cmp.b @(0x12345678:32,r3.w),@+er1" +gdb_test "x" "cmp.b\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abc(:16|),er1\\)" \ + "cmp.b @(0x12345678:32,r3.w),@(0x9abc:16,er1)" +gdb_test "x" "cmp.b\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "cmp.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1)" +gdb_test "x" "cmp.b\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "cmp.b @(0x12345678:32,r3.w),@(0x9abc:16,r2l.b)" +gdb_test "x" "cmp.b\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abc(:16|),r2.w\\)" \ + "cmp.b @(0x12345678:32,r3.w),@(0x9abc:16,r2.w)" +gdb_test "x" "cmp.b\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abc(:16|),er2.l\\)" \ + "cmp.b @(0x12345678:32,r3.w),@(0x9abc:16,er2.l)" +gdb_test "x" "cmp.b\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "cmp.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "cmp.b\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "cmp.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "cmp.b\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "cmp.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "cmp.b\t@\\(0x12345678(:32|),r3.w\\),@0x9abc(:16|)" \ + "cmp.b @(0x12345678:32,r3.w),@0x9abc:16" +gdb_test "x" "cmp.b\t@\\(0x12345678(:32|),r3.w\\),@0x9abcdef0(:32|)" \ + "cmp.b @(0x12345678:32,r3.w),@0x9abcdef0:32" +gdb_test "x" "cmp.b\t@\\(0x12345678(:32|),er3.l\\),@er1" \ + "cmp.b @(0x12345678:32,er3.l),@er1" +gdb_test "x" "cmp.b\t@\\(0x12345678(:32|),er3.l\\),@\\(0x3(:2|),er1\\)" \ + "cmp.b @(0x12345678:32,er3.l),@(0x3:2,er1)" +gdb_test "x" "cmp.b\t@\\(0x12345678(:32|),er3.l\\),@-er1" \ + "cmp.b @(0x12345678:32,er3.l),@-er1" +gdb_test "x" "cmp.b\t@\\(0x12345678(:32|),er3.l\\),@er1\\+" \ + "cmp.b @(0x12345678:32,er3.l),@er1+" +gdb_test "x" "cmp.b\t@\\(0x12345678(:32|),er3.l\\),@er1-" \ + "cmp.b @(0x12345678:32,er3.l),@er1-" +gdb_test "x" "cmp.b\t@\\(0x12345678(:32|),er3.l\\),@\\+er1" \ + "cmp.b @(0x12345678:32,er3.l),@+er1" +gdb_test "x" "cmp.b\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abc(:16|),er1\\)" \ + "cmp.b @(0x12345678:32,er3.l),@(0x9abc:16,er1)" +gdb_test "x" "cmp.b\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "cmp.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1)" +gdb_test "x" "cmp.b\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "cmp.b @(0x12345678:32,er3.l),@(0x9abc:16,r2l.b)" +gdb_test "x" "cmp.b\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abc(:16|),r2.w\\)" \ + "cmp.b @(0x12345678:32,er3.l),@(0x9abc:16,r2.w)" +gdb_test "x" "cmp.b\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abc(:16|),er2.l\\)" \ + "cmp.b @(0x12345678:32,er3.l),@(0x9abc:16,er2.l)" +gdb_test "x" "cmp.b\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "cmp.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "cmp.b\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "cmp.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "cmp.b\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "cmp.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "cmp.b\t@\\(0x12345678(:32|),er3.l\\),@0x9abc(:16|)" \ + "cmp.b @(0x12345678:32,er3.l),@0x9abc:16" +gdb_test "x" "cmp.b\t@\\(0x12345678(:32|),er3.l\\),@0x9abcdef0(:32|)" \ + "cmp.b @(0x12345678:32,er3.l),@0x9abcdef0:32" +gdb_test "x" "cmp.b\t@0x1234(:16|),@er1" \ + "cmp.b @0x1234:16,@er1" +gdb_test "x" "cmp.b\t@0x1234(:16|),@\\(0x3(:2|),er1\\)" \ + "cmp.b @0x1234:16,@(0x3:2,er1)" +gdb_test "x" "cmp.b\t@0x1234(:16|),@-er1" \ + "cmp.b @0x1234:16,@-er1" +gdb_test "x" "cmp.b\t@0x1234(:16|),@er1\\+" \ + "cmp.b @0x1234:16,@er1+" +gdb_test "x" "cmp.b\t@0x1234(:16|),@er1-" \ + "cmp.b @0x1234:16,@er1-" +gdb_test "x" "cmp.b\t@0x1234(:16|),@\\+er1" \ + "cmp.b @0x1234:16,@+er1" +gdb_test "x" "cmp.b\t@0x1234(:16|),@\\(0x9abc(:16|),er1\\)" \ + "cmp.b @0x1234:16,@(0x9abc:16,er1)" +gdb_test "x" "cmp.b\t@0x1234(:16|),@\\(0x9abcdef0(:32|),er1\\)" \ + "cmp.b @0x1234:16,@(0x9abcdef0:32,er1)" +gdb_test "x" "cmp.b\t@0x1234(:16|),@\\(0x9abc(:16|),r2l.b\\)" \ + "cmp.b @0x1234:16,@(0x9abc:16,r2l.b)" +gdb_test "x" "cmp.b\t@0x1234(:16|),@\\(0x9abc(:16|),r2.w\\)" \ + "cmp.b @0x1234:16,@(0x9abc:16,r2.w)" +gdb_test "x" "cmp.b\t@0x1234(:16|),@\\(0x9abc(:16|),er2.l\\)" \ + "cmp.b @0x1234:16,@(0x9abc:16,er2.l)" +gdb_test "x" "cmp.b\t@0x1234(:16|),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "cmp.b @0x1234:16,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "cmp.b\t@0x1234(:16|),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "cmp.b @0x1234:16,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "cmp.b\t@0x1234(:16|),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "cmp.b @0x1234:16,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "cmp.b\t@0x1234(:16|),@0x9abc(:16|)" \ + "cmp.b @0x1234:16,@0x9abc:16" +gdb_test "x" "cmp.b\t@0x1234(:16|),@0x9abcdef0(:32|)" \ + "cmp.b @0x1234:16,@0x9abcdef0:32" +gdb_test "x" "cmp.b\t@0x12345678(:32|),@er1" \ + "cmp.b @0x12345678:32,@er1" +gdb_test "x" "cmp.b\t@0x12345678(:32|),@\\(0x3(:2|),er1\\)" \ + "cmp.b @0x12345678:32,@(0x3:2,er1)" +gdb_test "x" "cmp.b\t@0x12345678(:32|),@-er1" \ + "cmp.b @0x12345678:32,@-er1" +gdb_test "x" "cmp.b\t@0x12345678(:32|),@er1\\+" \ + "cmp.b @0x12345678:32,@er1+" +gdb_test "x" "cmp.b\t@0x12345678(:32|),@er1-" \ + "cmp.b @0x12345678:32,@er1-" +gdb_test "x" "cmp.b\t@0x12345678(:32|),@\\+er1" \ + "cmp.b @0x12345678:32,@+er1" +gdb_test "x" "cmp.b\t@0x12345678(:32|),@\\(0x9abc(:16|),er1\\)" \ + "cmp.b @0x12345678:32,@(0x9abc:16,er1)" +gdb_test "x" "cmp.b\t@0x12345678(:32|),@\\(0x9abcdef0(:32|),er1\\)" \ + "cmp.b @0x12345678:32,@(0x9abcdef0:32,er1)" +gdb_test "x" "cmp.b\t@0x12345678(:32|),@\\(0x9abc(:16|),r2l.b\\)" \ + "cmp.b @0x12345678:32,@(0x9abc:16,r2l.b)" +gdb_test "x" "cmp.b\t@0x12345678(:32|),@\\(0x9abc(:16|),r2.w\\)" \ + "cmp.b @0x12345678:32,@(0x9abc:16,r2.w)" +gdb_test "x" "cmp.b\t@0x12345678(:32|),@\\(0x9abc(:16|),er2.l\\)" \ + "cmp.b @0x12345678:32,@(0x9abc:16,er2.l)" +gdb_test "x" "cmp.b\t@0x12345678(:32|),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "cmp.b @0x12345678:32,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "cmp.b\t@0x12345678(:32|),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "cmp.b @0x12345678:32,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "cmp.b\t@0x12345678(:32|),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "cmp.b @0x12345678:32,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "cmp.b\t@0x12345678(:32|),@0x9abc(:16|)" \ + "cmp.b @0x12345678:32,@0x9abc:16" +gdb_test "x" "cmp.b\t@0x12345678(:32|),@0x9abcdef0(:32|)" \ + "cmp.b @0x12345678:32,@0x9abcdef0:32" +gdb_test "x" "cmp.w\t#0x1234(:16|),r1" \ + "cmp.w #0x1234:16,r1" +gdb_test "x" "cmp.w\t#0x7(:3|),r2" \ + "cmp.w #0x7:3,r2" +gdb_test "x" "cmp.w\t#0x1234(:16|),@er1" \ + "cmp.w #0x1234:16,@er1" +gdb_test "x" "cmp.w\t#0x1234(:16|),@\\(0x6(:2|),er1\\)" \ + "cmp.w #0x1234:16,@(0x6:2,er1)" +gdb_test "x" "cmp.w\t#0x1234(:16|),@er1\\+" \ + "cmp.w #0x1234:16,@er1+" +gdb_test "x" "cmp.w\t#0x1234(:16|),@-er1" \ + "cmp.w #0x1234:16,@-er1" +gdb_test "x" "cmp.w\t#0x1234(:16|),@\\+er1" \ + "cmp.w #0x1234:16,@+er1" +gdb_test "x" "cmp.w\t#0x1234(:16|),@er1-" \ + "cmp.w #0x1234:16,@er1-" +gdb_test "x" "cmp.w\t#0x1234(:16|),@\\(0x9abc(:16|),er1\\)" \ + "cmp.w #0x1234:16,@(0x9abc:16,er1)" +gdb_test "x" "cmp.w\t#0x1234(:16|),@\\(0x9abcdef0(:32|),er1\\)" \ + "cmp.w #0x1234:16,@(0x9abcdef0:32,er1)" +gdb_test "x" "cmp.w\t#0x1234(:16|),@\\(0x9abc(:16|),r2l.b\\)" \ + "cmp.w #0x1234:16,@(0x9abc:16,r2l.b)" +gdb_test "x" "cmp.w\t#0x1234(:16|),@\\(0x9abc(:16|),r2.w\\)" \ + "cmp.w #0x1234:16,@(0x9abc:16,r2.w)" +gdb_test "x" "cmp.w\t#0x1234(:16|),@\\(0x9abc(:16|),er2.l\\)" \ + "cmp.w #0x1234:16,@(0x9abc:16,er2.l)" +gdb_test "x" "cmp.w\t#0x1234(:16|),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "cmp.w #0x1234:16,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "cmp.w\t#0x1234(:16|),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "cmp.w #0x1234:16,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "cmp.w\t#0x1234(:16|),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "cmp.w #0x1234:16,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "cmp.w\t#0x1234(:16|),@0x9abc(:16|)" \ + "cmp.w #0x1234:16,@0x9abc:16" +gdb_test "x" "cmp.w\t#0x1234(:16|),@0x9abcdef0(:32|)" \ + "cmp.w #0x1234:16,@0x9abcdef0:32" +gdb_test "x" "cmp.w\t#0x7(:3|),@er1" \ + "cmp.w #0x7:3,@er1" +gdb_test "x" "cmp.w\t#0x7(:3|),@0x1234(:16|)" \ + "cmp.w #0x7:3,@0x1234:16" +gdb_test "x" "cmp.w\t#0x7(:3|),@0x12345678(:32|)" \ + "cmp.w #0x7:3,@0x12345678:32" +gdb_test "x" "cmp.w\tr3,r1" \ + "cmp.w r3,r1" +gdb_test "x" "cmp.w\tr3,@er1" \ + "cmp.w r3,@er1" +gdb_test "x" "cmp.w\tr3,@\\(0x6(:2|),er1\\)" \ + "cmp.w r3,@(0x6:2,er1)" +gdb_test "x" "cmp.w\tr3,@er1\\+" \ + "cmp.w r3,@er1+" +gdb_test "x" "cmp.w\tr3,@-er1" \ + "cmp.w r3,@-er1" +gdb_test "x" "cmp.w\tr3,@\\+er1" \ + "cmp.w r3,@+er1" +gdb_test "x" "cmp.w\tr3,@er1-" \ + "cmp.w r3,@er1-" +gdb_test "x" "cmp.w\tr3,@\\(0x1234(:16|),er1\\)" \ + "cmp.w r3,@(0x1234:16,er1)" +gdb_test "x" "cmp.w\tr3,@\\(0x12345678(:32|),er1\\)" \ + "cmp.w r3,@(0x12345678:32,er1)" +gdb_test "x" "cmp.w\tr3,@\\(0x1234(:16|),r2l.b\\)" \ + "cmp.w r3,@(0x1234:16,r2l.b)" +gdb_test "x" "cmp.w\tr3,@\\(0x1234(:16|),r2.w\\)" \ + "cmp.w r3,@(0x1234:16,r2.w)" +gdb_test "x" "cmp.w\tr3,@\\(0x1234(:16|),er2.l\\)" \ + "cmp.w r3,@(0x1234:16,er2.l)" +gdb_test "x" "cmp.w\tr3,@\\(0x12345678(:32|),r2l.b\\)" \ + "cmp.w r3,@(0x12345678:32,r2l.b)" +gdb_test "x" "cmp.w\tr3,@\\(0x12345678(:32|),r2.w\\)" \ + "cmp.w r3,@(0x12345678:32,r2.w)" +gdb_test "x" "cmp.w\tr3,@\\(0x12345678(:32|),er2.l\\)" \ + "cmp.w r3,@(0x12345678:32,er2.l)" +gdb_test "x" "cmp.w\tr3,@0x1234(:16|)" \ + "cmp.w r3,@0x1234:16" +gdb_test "x" "cmp.w\tr3,@0x12345678(:32|)" \ + "cmp.w r3,@0x12345678:32" +gdb_test "x" "cmp.w\t@er3,r1" \ + "cmp.w @er3,r1" +gdb_test "x" "cmp.w\t@\\(0x6(:2|),er3\\),r1" \ + "cmp.w @(0x6:2,er3),r1" +gdb_test "x" "cmp.w\t@er3\\+,r1" \ + "cmp.w @er3+,r1" +gdb_test "x" "cmp.w\t@-er3,r1" \ + "cmp.w @-er3,r1" +gdb_test "x" "cmp.w\t@\\+er3,r1" \ + "cmp.w @+er3,r1" +gdb_test "x" "cmp.w\t@er3-,r1" \ + "cmp.w @er3-,r1" +gdb_test "x" "cmp.w\t@\\(0x1234(:16|),er1\\),r1" \ + "cmp.w @(0x1234:16,er1),r1" +gdb_test "x" "cmp.w\t@\\(0x12345678(:32|),er1\\),r1" \ + "cmp.w @(0x12345678:32,er1),r1" +gdb_test "x" "cmp.w\t@\\(0x1234(:16|),r2l.b\\),r1" \ + "cmp.w @(0x1234:16,r2l.b),r1" +gdb_test "x" "cmp.w\t@\\(0x1234(:16|),r2.w\\),r1" \ + "cmp.w @(0x1234:16,r2.w),r1" +gdb_test "x" "cmp.w\t@\\(0x1234(:16|),er2.l\\),r1" \ + "cmp.w @(0x1234:16,er2.l),r1" +gdb_test "x" "cmp.w\t@\\(0x12345678(:32|),r2l.b\\),r1" \ + "cmp.w @(0x12345678:32,r2l.b),r1" +gdb_test "x" "cmp.w\t@\\(0x12345678(:32|),r2.w\\),r1" \ + "cmp.w @(0x12345678:32,r2.w),r1" +gdb_test "x" "cmp.w\t@\\(0x12345678(:32|),er2.l\\),r1" \ + "cmp.w @(0x12345678:32,er2.l),r1" +gdb_test "x" "cmp.w\t@0x1234(:16|),r1" \ + "cmp.w @0x1234:16,r1" +gdb_test "x" "cmp.w\t@0x12345678(:32|),r1" \ + "cmp.w @0x12345678:32,r1" +gdb_test "x" "cmp.w\t@er3,@er1" \ + "cmp.w @er3,@er1" +gdb_test "x" "cmp.w\t@er3,@\\(0x6(:2|),er1\\)" \ + "cmp.w @er3,@(0x6:2,er1)" +gdb_test "x" "cmp.w\t@er3,@-er1" \ + "cmp.w @er3,@-er1" +gdb_test "x" "cmp.w\t@er3,@er1\\+" \ + "cmp.w @er3,@er1+" +gdb_test "x" "cmp.w\t@er3,@er1-" \ + "cmp.w @er3,@er1-" +gdb_test "x" "cmp.w\t@er3,@\\+er1" \ + "cmp.w @er3,@+er1" +gdb_test "x" "cmp.w\t@er3,@\\(0x9abc(:16|),er1\\)" \ + "cmp.w @er3,@(0x9abc:16,er1)" +gdb_test "x" "cmp.w\t@er3,@\\(0x9abcdef0(:32|),er1\\)" \ + "cmp.w @er3,@(0x9abcdef0:32,er1)" +gdb_test "x" "cmp.w\t@er3,@\\(0x9abc(:16|),r2l.b\\)" \ + "cmp.w @er3,@(0x9abc:16,r2l.b)" +gdb_test "x" "cmp.w\t@er3,@\\(0x9abc(:16|),r2.w\\)" \ + "cmp.w @er3,@(0x9abc:16,r2.w)" +gdb_test "x" "cmp.w\t@er3,@\\(0x9abc(:16|),er2.l\\)" \ + "cmp.w @er3,@(0x9abc:16,er2.l)" +gdb_test "x" "cmp.w\t@er3,@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "cmp.w @er3,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "cmp.w\t@er3,@\\(0x9abcdef0(:32|),r2.w\\)" \ + "cmp.w @er3,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "cmp.w\t@er3,@\\(0x9abcdef0(:32|),er2.l\\)" \ + "cmp.w @er3,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "cmp.w\t@er3,@0x9abc(:16|)" \ + "cmp.w @er3,@0x9abc:16" +gdb_test "x" "cmp.w\t@er3,@0x9abcdef0(:32|)" \ + "cmp.w @er3,@0x9abcdef0:32" +gdb_test "x" "cmp.w\t@-er3,@er1" \ + "cmp.w @-er3,@er1" +gdb_test "x" "cmp.w\t@-er3,@\\(0x6(:2|),er1\\)" \ + "cmp.w @-er3,@(0x6:2,er1)" +gdb_test "x" "cmp.w\t@-er3,@-er1" \ + "cmp.w @-er3,@-er1" +gdb_test "x" "cmp.w\t@-er3,@er1\\+" \ + "cmp.w @-er3,@er1+" +gdb_test "x" "cmp.w\t@-er3,@er1-" \ + "cmp.w @-er3,@er1-" +gdb_test "x" "cmp.w\t@-er3,@\\+er1" \ + "cmp.w @-er3,@+er1" +gdb_test "x" "cmp.w\t@-er3,@\\(0x9abc(:16|),er1\\)" \ + "cmp.w @-er3,@(0x9abc:16,er1)" +gdb_test "x" "cmp.w\t@-er3,@\\(0x9abcdef0(:32|),er1\\)" \ + "cmp.w @-er3,@(0x9abcdef0:32,er1)" +gdb_test "x" "cmp.w\t@-er3,@\\(0x9abc(:16|),r2l.b\\)" \ + "cmp.w @-er3,@(0x9abc:16,r2l.b)" +gdb_test "x" "cmp.w\t@-er3,@\\(0x9abc(:16|),r2.w\\)" \ + "cmp.w @-er3,@(0x9abc:16,r2.w)" +gdb_test "x" "cmp.w\t@-er3,@\\(0x9abc(:16|),er2.l\\)" \ + "cmp.w @-er3,@(0x9abc:16,er2.l)" +gdb_test "x" "cmp.w\t@-er3,@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "cmp.w @-er3,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "cmp.w\t@-er3,@\\(0x9abcdef0(:32|),r2.w\\)" \ + "cmp.w @-er3,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "cmp.w\t@-er3,@\\(0x9abcdef0(:32|),er2.l\\)" \ + "cmp.w @-er3,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "cmp.w\t@-er3,@0x9abc(:16|)" \ + "cmp.w @-er3,@0x9abc:16" +gdb_test "x" "cmp.w\t@-er3,@0x9abcdef0(:32|)" \ + "cmp.w @-er3,@0x9abcdef0:32" +gdb_test "x" "cmp.w\t@er3\\+,@er1" \ + "cmp.w @er3+,@er1" +gdb_test "x" "cmp.w\t@er3\\+,@\\(0x6(:2|),er1\\)" \ + "cmp.w @er3+,@(0x6:2,er1)" +gdb_test "x" "cmp.w\t@er3\\+,@-er1" \ + "cmp.w @er3+,@-er1" +gdb_test "x" "cmp.w\t@er3\\+,@er1\\+" \ + "cmp.w @er3+,@er1+" +gdb_test "x" "cmp.w\t@er3\\+,@er1-" \ + "cmp.w @er3+,@er1-" +gdb_test "x" "cmp.w\t@er3\\+,@\\+er1" \ + "cmp.w @er3+,@+er1" +gdb_test "x" "cmp.w\t@er3\\+,@\\(0x9abc(:16|),er1\\)" \ + "cmp.w @er3+,@(0x9abc:16,er1)" +gdb_test "x" "cmp.w\t@er3\\+,@\\(0x9abcdef0(:32|),er1\\)" \ + "cmp.w @er3+,@(0x9abcdef0:32,er1)" +gdb_test "x" "cmp.w\t@er3\\+,@\\(0x9abc(:16|),r2l.b\\)" \ + "cmp.w @er3+,@(0x9abc:16,r2l.b)" +gdb_test "x" "cmp.w\t@er3\\+,@\\(0x9abc(:16|),r2.w\\)" \ + "cmp.w @er3+,@(0x9abc:16,r2.w)" +gdb_test "x" "cmp.w\t@er3\\+,@\\(0x9abc(:16|),er2.l\\)" \ + "cmp.w @er3+,@(0x9abc:16,er2.l)" +gdb_test "x" "cmp.w\t@er3\\+,@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "cmp.w @er3+,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "cmp.w\t@er3\\+,@\\(0x9abcdef0(:32|),r2.w\\)" \ + "cmp.w @er3+,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "cmp.w\t@er3\\+,@\\(0x9abcdef0(:32|),er2.l\\)" \ + "cmp.w @er3+,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "cmp.w\t@er3\\+,@0x9abc(:16|)" \ + "cmp.w @er3+,@0x9abc:16" +gdb_test "x" "cmp.w\t@er3\\+,@0x9abcdef0(:32|)" \ + "cmp.w @er3+,@0x9abcdef0:32" +gdb_test "x" "cmp.w\t@er3-,@er1" \ + "cmp.w @er3-,@er1" +gdb_test "x" "cmp.w\t@er3-,@\\(0x6(:2|),er1\\)" \ + "cmp.w @er3-,@(0x6:2,er1)" +gdb_test "x" "cmp.w\t@er3-,@-er1" \ + "cmp.w @er3-,@-er1" +gdb_test "x" "cmp.w\t@er3-,@er1\\+" \ + "cmp.w @er3-,@er1+" +gdb_test "x" "cmp.w\t@er3-,@er1-" \ + "cmp.w @er3-,@er1-" +gdb_test "x" "cmp.w\t@er3-,@\\+er1" \ + "cmp.w @er3-,@+er1" +gdb_test "x" "cmp.w\t@er3-,@\\(0x9abc(:16|),er1\\)" \ + "cmp.w @er3-,@(0x9abc:16,er1)" +gdb_test "x" "cmp.w\t@er3-,@\\(0x9abcdef0(:32|),er1\\)" \ + "cmp.w @er3-,@(0x9abcdef0:32,er1)" +gdb_test "x" "cmp.w\t@er3-,@\\(0x9abc(:16|),r2l.b\\)" \ + "cmp.w @er3-,@(0x9abc:16,r2l.b)" +gdb_test "x" "cmp.w\t@er3-,@\\(0x9abc(:16|),r2.w\\)" \ + "cmp.w @er3-,@(0x9abc:16,r2.w)" +gdb_test "x" "cmp.w\t@er3-,@\\(0x9abc(:16|),er2.l\\)" \ + "cmp.w @er3-,@(0x9abc:16,er2.l)" +gdb_test "x" "cmp.w\t@er3-,@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "cmp.w @er3-,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "cmp.w\t@er3-,@\\(0x9abcdef0(:32|),r2.w\\)" \ + "cmp.w @er3-,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "cmp.w\t@er3-,@\\(0x9abcdef0(:32|),er2.l\\)" \ + "cmp.w @er3-,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "cmp.w\t@er3-,@0x9abc(:16|)" \ + "cmp.w @er3-,@0x9abc:16" +gdb_test "x" "cmp.w\t@er3-,@0x9abcdef0(:32|)" \ + "cmp.w @er3-,@0x9abcdef0:32" +gdb_test "x" "cmp.w\t@\\+er3,@er1" \ + "cmp.w @+er3,@er1" +gdb_test "x" "cmp.w\t@\\+er3,@\\(0x6(:2|),er1\\)" \ + "cmp.w @+er3,@(0x6:2,er1)" +gdb_test "x" "cmp.w\t@\\+er3,@-er1" \ + "cmp.w @+er3,@-er1" +gdb_test "x" "cmp.w\t@\\+er3,@er1\\+" \ + "cmp.w @+er3,@er1+" +gdb_test "x" "cmp.w\t@\\+er3,@er1-" \ + "cmp.w @+er3,@er1-" +gdb_test "x" "cmp.w\t@\\+er3,@\\+er1" \ + "cmp.w @+er3,@+er1" +gdb_test "x" "cmp.w\t@\\+er3,@\\(0x9abc(:16|),er1\\)" \ + "cmp.w @+er3,@(0x9abc:16,er1)" +gdb_test "x" "cmp.w\t@\\+er3,@\\(0x9abcdef0(:32|),er1\\)" \ + "cmp.w @+er3,@(0x9abcdef0:32,er1)" +gdb_test "x" "cmp.w\t@\\+er3,@\\(0x9abc(:16|),r2l.b\\)" \ + "cmp.w @+er3,@(0x9abc:16,r2l.b)" +gdb_test "x" "cmp.w\t@\\+er3,@\\(0x9abc(:16|),r2.w\\)" \ + "cmp.w @+er3,@(0x9abc:16,r2.w)" +gdb_test "x" "cmp.w\t@\\+er3,@\\(0x9abc(:16|),er2.l\\)" \ + "cmp.w @+er3,@(0x9abc:16,er2.l)" +gdb_test "x" "cmp.w\t@\\+er3,@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "cmp.w @+er3,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "cmp.w\t@\\+er3,@\\(0x9abcdef0(:32|),r2.w\\)" \ + "cmp.w @+er3,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "cmp.w\t@\\+er3,@\\(0x9abcdef0(:32|),er2.l\\)" \ + "cmp.w @+er3,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "cmp.w\t@\\+er3,@0x9abc(:16|)" \ + "cmp.w @+er3,@0x9abc:16" +gdb_test "x" "cmp.w\t@\\+er3,@0x9abcdef0(:32|)" \ + "cmp.w @+er3,@0x9abcdef0:32" +gdb_test "x" "cmp.w\t@\\(0x1234(:16|),er3\\),@er1" \ + "cmp.w @(0x1234:16,er3),@er1" +gdb_test "x" "cmp.w\t@\\(0x1234(:16|),er3\\),@\\(0x6(:2|),er1\\)" \ + "cmp.w @(0x1234:16,er3),@(0x6:2,er1)" +gdb_test "x" "cmp.w\t@\\(0x1234(:16|),er3\\),@-er1" \ + "cmp.w @(0x1234:16,er3),@-er1" +gdb_test "x" "cmp.w\t@\\(0x1234(:16|),er3\\),@er1\\+" \ + "cmp.w @(0x1234:16,er3),@er1+" +gdb_test "x" "cmp.w\t@\\(0x1234(:16|),er3\\),@er1-" \ + "cmp.w @(0x1234:16,er3),@er1-" +gdb_test "x" "cmp.w\t@\\(0x1234(:16|),er3\\),@\\+er1" \ + "cmp.w @(0x1234:16,er3),@+er1" +gdb_test "x" "cmp.w\t@\\(0x1234(:16|),er3\\),@\\(0x9abc(:16|),er1\\)" \ + "cmp.w @(0x1234:16,er3),@(0x9abc:16,er1)" +gdb_test "x" "cmp.w\t@\\(0x1234(:16|),er3\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "cmp.w @(0x1234:16,er3),@(0x9abcdef0:32,er1)" +gdb_test "x" "cmp.w\t@\\(0x1234(:16|),er3\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "cmp.w @(0x1234:16,er3),@(0x9abc:16,r2l.b)" +gdb_test "x" "cmp.w\t@\\(0x1234(:16|),er3\\),@\\(0x9abc(:16|),r2.w\\)" \ + "cmp.w @(0x1234:16,er3),@(0x9abc:16,r2.w)" +gdb_test "x" "cmp.w\t@\\(0x1234(:16|),er3\\),@\\(0x9abc(:16|),er2.l\\)" \ + "cmp.w @(0x1234:16,er3),@(0x9abc:16,er2.l)" +gdb_test "x" "cmp.w\t@\\(0x1234(:16|),er3\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "cmp.w @(0x1234:16,er3),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "cmp.w\t@\\(0x1234(:16|),er3\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "cmp.w @(0x1234:16,er3),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "cmp.w\t@\\(0x1234(:16|),er3\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "cmp.w @(0x1234:16,er3),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "cmp.w\t@\\(0x1234(:16|),er3\\),@0x9abc(:16|)" \ + "cmp.w @(0x1234:16,er3),@0x9abc:16" +gdb_test "x" "cmp.w\t@\\(0x1234(:16|),er3\\),@0x9abcdef0(:32|)" \ + "cmp.w @(0x1234:16,er3),@0x9abcdef0:32" +gdb_test "x" "cmp.w\t@\\(0x12345678(:32|),er3\\),@er1" \ + "cmp.w @(0x12345678:32,er3),@er1" +gdb_test "x" "cmp.w\t@\\(0x12345678(:32|),er3\\),@\\(0x6(:2|),er1\\)" \ + "cmp.w @(0x12345678:32,er3),@(0x6:2,er1)" +gdb_test "x" "cmp.w\t@\\(0x12345678(:32|),er3\\),@-er1" \ + "cmp.w @(0x12345678:32,er3),@-er1" +gdb_test "x" "cmp.w\t@\\(0x12345678(:32|),er3\\),@er1\\+" \ + "cmp.w @(0x12345678:32,er3),@er1+" +gdb_test "x" "cmp.w\t@\\(0x12345678(:32|),er3\\),@er1-" \ + "cmp.w @(0x12345678:32,er3),@er1-" +gdb_test "x" "cmp.w\t@\\(0x12345678(:32|),er3\\),@\\+er1" \ + "cmp.w @(0x12345678:32,er3),@+er1" +gdb_test "x" "cmp.w\t@\\(0x12345678(:32|),er3\\),@\\(0x9abc(:16|),er1\\)" \ + "cmp.w @(0x12345678:32,er3),@(0x9abc:16,er1)" +gdb_test "x" "cmp.w\t@\\(0x12345678(:32|),er3\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "cmp.w @(0x12345678:32,er3),@(0x9abcdef0:32,er1)" +gdb_test "x" "cmp.w\t@\\(0x12345678(:32|),er3\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "cmp.w @(0x12345678:32,er3),@(0x9abc:16,r2l.b)" +gdb_test "x" "cmp.w\t@\\(0x12345678(:32|),er3\\),@\\(0x9abc(:16|),r2.w\\)" \ + "cmp.w @(0x12345678:32,er3),@(0x9abc:16,r2.w)" +gdb_test "x" "cmp.w\t@\\(0x12345678(:32|),er3\\),@\\(0x9abc(:16|),er2.l\\)" \ + "cmp.w @(0x12345678:32,er3),@(0x9abc:16,er2.l)" +gdb_test "x" "cmp.w\t@\\(0x12345678(:32|),er3\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "cmp.w @(0x12345678:32,er3),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "cmp.w\t@\\(0x12345678(:32|),er3\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "cmp.w @(0x12345678:32,er3),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "cmp.w\t@\\(0x12345678(:32|),er3\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "cmp.w @(0x12345678:32,er3),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "cmp.w\t@\\(0x12345678(:32|),er3\\),@0x9abc(:16|)" \ + "cmp.w @(0x12345678:32,er3),@0x9abc:16" +gdb_test "x" "cmp.w\t@\\(0x12345678(:32|),er3\\),@0x9abcdef0(:32|)" \ + "cmp.w @(0x12345678:32,er3),@0x9abcdef0:32" +gdb_test "x" "cmp.w\t@\\(0x1234(:16|),r3l.b\\),@er1" \ + "cmp.w @(0x1234:16,r3l.b),@er1" +gdb_test "x" "cmp.w\t@\\(0x1234(:16|),r3l.b\\),@\\(0x6(:2|),er1\\)" \ + "cmp.w @(0x1234:16,r3l.b),@(0x6:2,er1)" +gdb_test "x" "cmp.w\t@\\(0x1234(:16|),r3l.b\\),@-er1" \ + "cmp.w @(0x1234:16,r3l.b),@-er1" +gdb_test "x" "cmp.w\t@\\(0x1234(:16|),r3l.b\\),@er1\\+" \ + "cmp.w @(0x1234:16,r3l.b),@er1+" +gdb_test "x" "cmp.w\t@\\(0x1234(:16|),r3l.b\\),@er1-" \ + "cmp.w @(0x1234:16,r3l.b),@er1-" +gdb_test "x" "cmp.w\t@\\(0x1234(:16|),r3l.b\\),@\\+er1" \ + "cmp.w @(0x1234:16,r3l.b),@+er1" +gdb_test "x" "cmp.w\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abc(:16|),er1\\)" \ + "cmp.w @(0x1234:16,r3l.b),@(0x9abc:16,er1)" +gdb_test "x" "cmp.w\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "cmp.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1)" +gdb_test "x" "cmp.w\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "cmp.w @(0x1234:16,r3l.b),@(0x9abc:16,r2l.b)" +gdb_test "x" "cmp.w\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abc(:16|),r2.w\\)" \ + "cmp.w @(0x1234:16,r3l.b),@(0x9abc:16,r2.w)" +gdb_test "x" "cmp.w\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abc(:16|),er2.l\\)" \ + "cmp.w @(0x1234:16,r3l.b),@(0x9abc:16,er2.l)" +gdb_test "x" "cmp.w\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "cmp.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "cmp.w\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "cmp.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "cmp.w\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "cmp.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "cmp.w\t@\\(0x1234(:16|),r3l.b\\),@0x9abc(:16|)" \ + "cmp.w @(0x1234:16,r3l.b),@0x9abc:16" +gdb_test "x" "cmp.w\t@\\(0x1234(:16|),r3l.b\\),@0x9abcdef0(:32|)" \ + "cmp.w @(0x1234:16,r3l.b),@0x9abcdef0:32" +gdb_test "x" "cmp.w\t@\\(0x1234(:16|),r3.w\\),@er1" \ + "cmp.w @(0x1234:16,r3.w),@er1" +gdb_test "x" "cmp.w\t@\\(0x1234(:16|),r3.w\\),@\\(0x6(:2|),er1\\)" \ + "cmp.w @(0x1234:16,r3.w),@(0x6:2,er1)" +gdb_test "x" "cmp.w\t@\\(0x1234(:16|),r3.w\\),@-er1" \ + "cmp.w @(0x1234:16,r3.w),@-er1" +gdb_test "x" "cmp.w\t@\\(0x1234(:16|),r3.w\\),@er1\\+" \ + "cmp.w @(0x1234:16,r3.w),@er1+" +gdb_test "x" "cmp.w\t@\\(0x1234(:16|),r3.w\\),@er1-" \ + "cmp.w @(0x1234:16,r3.w),@er1-" +gdb_test "x" "cmp.w\t@\\(0x1234(:16|),r3.w\\),@\\+er1" \ + "cmp.w @(0x1234:16,r3.w),@+er1" +gdb_test "x" "cmp.w\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abc(:16|),er1\\)" \ + "cmp.w @(0x1234:16,r3.w),@(0x9abc:16,er1)" +gdb_test "x" "cmp.w\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "cmp.w @(0x1234:16,r3.w),@(0x9abcdef0:32,er1)" +gdb_test "x" "cmp.w\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "cmp.w @(0x1234:16,r3.w),@(0x9abc:16,r2l.b)" +gdb_test "x" "cmp.w\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abc(:16|),r2.w\\)" \ + "cmp.w @(0x1234:16,r3.w),@(0x9abc:16,r2.w)" +gdb_test "x" "cmp.w\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abc(:16|),er2.l\\)" \ + "cmp.w @(0x1234:16,r3.w),@(0x9abc:16,er2.l)" +gdb_test "x" "cmp.w\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "cmp.w @(0x1234:16,r3.w),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "cmp.w\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "cmp.w @(0x1234:16,r3.w),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "cmp.w\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "cmp.w @(0x1234:16,r3.w),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "cmp.w\t@\\(0x1234(:16|),r3.w\\),@0x9abc(:16|)" \ + "cmp.w @(0x1234:16,r3.w),@0x9abc:16" +gdb_test "x" "cmp.w\t@\\(0x1234(:16|),r3.w\\),@0x9abcdef0(:32|)" \ + "cmp.w @(0x1234:16,r3.w),@0x9abcdef0:32" +gdb_test "x" "cmp.w\t@\\(0x1234(:16|),er3.l\\),@er1" \ + "cmp.w @(0x1234:16,er3.l),@er1" +gdb_test "x" "cmp.w\t@\\(0x1234(:16|),er3.l\\),@\\(0x6(:2|),er1\\)" \ + "cmp.w @(0x1234:16,er3.l),@(0x6:2,er1)" +gdb_test "x" "cmp.w\t@\\(0x1234(:16|),er3.l\\),@-er1" \ + "cmp.w @(0x1234:16,er3.l),@-er1" +gdb_test "x" "cmp.w\t@\\(0x1234(:16|),er3.l\\),@er1\\+" \ + "cmp.w @(0x1234:16,er3.l),@er1+" +gdb_test "x" "cmp.w\t@\\(0x1234(:16|),er3.l\\),@er1-" \ + "cmp.w @(0x1234:16,er3.l),@er1-" +gdb_test "x" "cmp.w\t@\\(0x1234(:16|),er3.l\\),@\\+er1" \ + "cmp.w @(0x1234:16,er3.l),@+er1" +gdb_test "x" "cmp.w\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abc(:16|),er1\\)" \ + "cmp.w @(0x1234:16,er3.l),@(0x9abc:16,er1)" +gdb_test "x" "cmp.w\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "cmp.w @(0x1234:16,er3.l),@(0x9abcdef0:32,er1)" +gdb_test "x" "cmp.w\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "cmp.w @(0x1234:16,er3.l),@(0x9abc:16,r2l.b)" +gdb_test "x" "cmp.w\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abc(:16|),r2.w\\)" \ + "cmp.w @(0x1234:16,er3.l),@(0x9abc:16,r2.w)" +gdb_test "x" "cmp.w\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abc(:16|),er2.l\\)" \ + "cmp.w @(0x1234:16,er3.l),@(0x9abc:16,er2.l)" +gdb_test "x" "cmp.w\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "cmp.w @(0x1234:16,er3.l),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "cmp.w\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "cmp.w @(0x1234:16,er3.l),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "cmp.w\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "cmp.w @(0x1234:16,er3.l),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "cmp.w\t@\\(0x1234(:16|),er3.l\\),@0x9abc(:16|)" \ + "cmp.w @(0x1234:16,er3.l),@0x9abc:16" +gdb_test "x" "cmp.w\t@\\(0x1234(:16|),er3.l\\),@0x9abcdef0(:32|)" \ + "cmp.w @(0x1234:16,er3.l),@0x9abcdef0:32" +gdb_test "x" "cmp.w\t@\\(0x12345678(:32|),r3l.b\\),@er1" \ + "cmp.w @(0x12345678:32,r3l.b),@er1" +gdb_test "x" "cmp.w\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x6(:2|),er1\\)" \ + "cmp.w @(0x12345678:32,r3l.b),@(0x6:2,er1)" +gdb_test "x" "cmp.w\t@\\(0x12345678(:32|),r3l.b\\),@-er1" \ + "cmp.w @(0x12345678:32,r3l.b),@-er1" +gdb_test "x" "cmp.w\t@\\(0x12345678(:32|),r3l.b\\),@er1\\+" \ + "cmp.w @(0x12345678:32,r3l.b),@er1+" +gdb_test "x" "cmp.w\t@\\(0x12345678(:32|),r3l.b\\),@er1-" \ + "cmp.w @(0x12345678:32,r3l.b),@er1-" +gdb_test "x" "cmp.w\t@\\(0x12345678(:32|),r3l.b\\),@\\+er1" \ + "cmp.w @(0x12345678:32,r3l.b),@+er1" +gdb_test "x" "cmp.w\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abc(:16|),er1\\)" \ + "cmp.w @(0x12345678:32,r3l.b),@(0x9abc:16,er1)" +gdb_test "x" "cmp.w\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "cmp.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1)" +gdb_test "x" "cmp.w\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "cmp.w @(0x12345678:32,r3l.b),@(0x9abc:16,r2l.b)" +gdb_test "x" "cmp.w\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abc(:16|),r2.w\\)" \ + "cmp.w @(0x12345678:32,r3l.b),@(0x9abc:16,r2.w)" +gdb_test "x" "cmp.w\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abc(:16|),er2.l\\)" \ + "cmp.w @(0x12345678:32,r3l.b),@(0x9abc:16,er2.l)" +gdb_test "x" "cmp.w\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "cmp.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "cmp.w\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "cmp.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "cmp.w\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "cmp.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "cmp.w\t@\\(0x12345678(:32|),r3l.b\\),@0x9abc(:16|)" \ + "cmp.w @(0x12345678:32,r3l.b),@0x9abc:16" +gdb_test "x" "cmp.w\t@\\(0x12345678(:32|),r3l.b\\),@0x9abcdef0(:32|)" \ + "cmp.w @(0x12345678:32,r3l.b),@0x9abcdef0:32" +gdb_test "x" "cmp.w\t@\\(0x12345678(:32|),r3.w\\),@er1" \ + "cmp.w @(0x12345678:32,r3.w),@er1" +gdb_test "x" "cmp.w\t@\\(0x12345678(:32|),r3.w\\),@\\(0x6(:2|),er1\\)" \ + "cmp.w @(0x12345678:32,r3.w),@(0x6:2,er1)" +gdb_test "x" "cmp.w\t@\\(0x12345678(:32|),r3.w\\),@-er1" \ + "cmp.w @(0x12345678:32,r3.w),@-er1" +gdb_test "x" "cmp.w\t@\\(0x12345678(:32|),r3.w\\),@er1\\+" \ + "cmp.w @(0x12345678:32,r3.w),@er1+" +gdb_test "x" "cmp.w\t@\\(0x12345678(:32|),r3.w\\),@er1-" \ + "cmp.w @(0x12345678:32,r3.w),@er1-" +gdb_test "x" "cmp.w\t@\\(0x12345678(:32|),r3.w\\),@\\+er1" \ + "cmp.w @(0x12345678:32,r3.w),@+er1" +gdb_test "x" "cmp.w\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abc(:16|),er1\\)" \ + "cmp.w @(0x12345678:32,r3.w),@(0x9abc:16,er1)" +gdb_test "x" "cmp.w\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "cmp.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1)" +gdb_test "x" "cmp.w\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "cmp.w @(0x12345678:32,r3.w),@(0x9abc:16,r2l.b)" +gdb_test "x" "cmp.w\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abc(:16|),r2.w\\)" \ + "cmp.w @(0x12345678:32,r3.w),@(0x9abc:16,r2.w)" +gdb_test "x" "cmp.w\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abc(:16|),er2.l\\)" \ + "cmp.w @(0x12345678:32,r3.w),@(0x9abc:16,er2.l)" +gdb_test "x" "cmp.w\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "cmp.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "cmp.w\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "cmp.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "cmp.w\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "cmp.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "cmp.w\t@\\(0x12345678(:32|),r3.w\\),@0x9abc(:16|)" \ + "cmp.w @(0x12345678:32,r3.w),@0x9abc:16" +gdb_test "x" "cmp.w\t@\\(0x12345678(:32|),r3.w\\),@0x9abcdef0(:32|)" \ + "cmp.w @(0x12345678:32,r3.w),@0x9abcdef0:32" +gdb_test "x" "cmp.w\t@\\(0x12345678(:32|),er3.l\\),@er1" \ + "cmp.w @(0x12345678:32,er3.l),@er1" +gdb_test "x" "cmp.w\t@\\(0x12345678(:32|),er3.l\\),@\\(0x6(:2|),er1\\)" \ + "cmp.w @(0x12345678:32,er3.l),@(0x6:2,er1)" +gdb_test "x" "cmp.w\t@\\(0x12345678(:32|),er3.l\\),@-er1" \ + "cmp.w @(0x12345678:32,er3.l),@-er1" +gdb_test "x" "cmp.w\t@\\(0x12345678(:32|),er3.l\\),@er1\\+" \ + "cmp.w @(0x12345678:32,er3.l),@er1+" +gdb_test "x" "cmp.w\t@\\(0x12345678(:32|),er3.l\\),@er1-" \ + "cmp.w @(0x12345678:32,er3.l),@er1-" +gdb_test "x" "cmp.w\t@\\(0x12345678(:32|),er3.l\\),@\\+er1" \ + "cmp.w @(0x12345678:32,er3.l),@+er1" +gdb_test "x" "cmp.w\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abc(:16|),er1\\)" \ + "cmp.w @(0x12345678:32,er3.l),@(0x9abc:16,er1)" +gdb_test "x" "cmp.w\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "cmp.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1)" +gdb_test "x" "cmp.w\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "cmp.w @(0x12345678:32,er3.l),@(0x9abc:16,r2l.b)" +gdb_test "x" "cmp.w\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abc(:16|),r2.w\\)" \ + "cmp.w @(0x12345678:32,er3.l),@(0x9abc:16,r2.w)" +gdb_test "x" "cmp.w\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abc(:16|),er2.l\\)" \ + "cmp.w @(0x12345678:32,er3.l),@(0x9abc:16,er2.l)" +gdb_test "x" "cmp.w\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "cmp.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "cmp.w\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "cmp.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "cmp.w\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "cmp.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "cmp.w\t@\\(0x12345678(:32|),er3.l\\),@0x9abc(:16|)" \ + "cmp.w @(0x12345678:32,er3.l),@0x9abc:16" +gdb_test "x" "cmp.w\t@\\(0x12345678(:32|),er3.l\\),@0x9abcdef0(:32|)" \ + "cmp.w @(0x12345678:32,er3.l),@0x9abcdef0:32" +gdb_test "x" "cmp.w\t@0x1234(:16|),@er1" \ + "cmp.w @0x1234:16,@er1" +gdb_test "x" "cmp.w\t@0x1234(:16|),@\\(0x6(:2|),er1\\)" \ + "cmp.w @0x1234:16,@(0x6:2,er1)" +gdb_test "x" "cmp.w\t@0x1234(:16|),@-er1" \ + "cmp.w @0x1234:16,@-er1" +gdb_test "x" "cmp.w\t@0x1234(:16|),@er1\\+" \ + "cmp.w @0x1234:16,@er1+" +gdb_test "x" "cmp.w\t@0x1234(:16|),@er1-" \ + "cmp.w @0x1234:16,@er1-" +gdb_test "x" "cmp.w\t@0x1234(:16|),@\\+er1" \ + "cmp.w @0x1234:16,@+er1" +gdb_test "x" "cmp.w\t@0x1234(:16|),@\\(0x9abc(:16|),er1\\)" \ + "cmp.w @0x1234:16,@(0x9abc:16,er1)" +gdb_test "x" "cmp.w\t@0x1234(:16|),@\\(0x9abcdef0(:32|),er1\\)" \ + "cmp.w @0x1234:16,@(0x9abcdef0:32,er1)" +gdb_test "x" "cmp.w\t@0x1234(:16|),@\\(0x9abc(:16|),r2l.b\\)" \ + "cmp.w @0x1234:16,@(0x9abc:16,r2l.b)" +gdb_test "x" "cmp.w\t@0x1234(:16|),@\\(0x9abc(:16|),r2.w\\)" \ + "cmp.w @0x1234:16,@(0x9abc:16,r2.w)" +gdb_test "x" "cmp.w\t@0x1234(:16|),@\\(0x9abc(:16|),er2.l\\)" \ + "cmp.w @0x1234:16,@(0x9abc:16,er2.l)" +gdb_test "x" "cmp.w\t@0x1234(:16|),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "cmp.w @0x1234:16,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "cmp.w\t@0x1234(:16|),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "cmp.w @0x1234:16,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "cmp.w\t@0x1234(:16|),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "cmp.w @0x1234:16,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "cmp.w\t@0x1234(:16|),@0x9abc(:16|)" \ + "cmp.w @0x1234:16,@0x9abc:16" +gdb_test "x" "cmp.w\t@0x1234(:16|),@0x9abcdef0(:32|)" \ + "cmp.w @0x1234:16,@0x9abcdef0:32" +gdb_test "x" "cmp.w\t@0x12345678(:32|),@er1" \ + "cmp.w @0x12345678:32,@er1" +gdb_test "x" "cmp.w\t@0x12345678(:32|),@\\(0x6(:2|),er1\\)" \ + "cmp.w @0x12345678:32,@(0x6:2,er1)" +gdb_test "x" "cmp.w\t@0x12345678(:32|),@-er1" \ + "cmp.w @0x12345678:32,@-er1" +gdb_test "x" "cmp.w\t@0x12345678(:32|),@er1\\+" \ + "cmp.w @0x12345678:32,@er1+" +gdb_test "x" "cmp.w\t@0x12345678(:32|),@er1-" \ + "cmp.w @0x12345678:32,@er1-" +gdb_test "x" "cmp.w\t@0x12345678(:32|),@\\+er1" \ + "cmp.w @0x12345678:32,@+er1" +gdb_test "x" "cmp.w\t@0x12345678(:32|),@\\(0x9abc(:16|),er1\\)" \ + "cmp.w @0x12345678:32,@(0x9abc:16,er1)" +gdb_test "x" "cmp.w\t@0x12345678(:32|),@\\(0x9abcdef0(:32|),er1\\)" \ + "cmp.w @0x12345678:32,@(0x9abcdef0:32,er1)" +gdb_test "x" "cmp.w\t@0x12345678(:32|),@\\(0x9abc(:16|),r2l.b\\)" \ + "cmp.w @0x12345678:32,@(0x9abc:16,r2l.b)" +gdb_test "x" "cmp.w\t@0x12345678(:32|),@\\(0x9abc(:16|),r2.w\\)" \ + "cmp.w @0x12345678:32,@(0x9abc:16,r2.w)" +gdb_test "x" "cmp.w\t@0x12345678(:32|),@\\(0x9abc(:16|),er2.l\\)" \ + "cmp.w @0x12345678:32,@(0x9abc:16,er2.l)" +gdb_test "x" "cmp.w\t@0x12345678(:32|),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "cmp.w @0x12345678:32,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "cmp.w\t@0x12345678(:32|),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "cmp.w @0x12345678:32,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "cmp.w\t@0x12345678(:32|),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "cmp.w @0x12345678:32,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "cmp.w\t@0x12345678(:32|),@0x9abc(:16|)" \ + "cmp.w @0x12345678:32,@0x9abc:16" +gdb_test "x" "cmp.w\t@0x12345678(:32|),@0x9abcdef0(:32|)" \ + "cmp.w @0x12345678:32,@0x9abcdef0:32" +gdb_test "x" "cmp.l\t#0x12345678(:32|),er1" \ + "cmp.l #0x12345678:32,er1" +gdb_test "x" "cmp.l\t#0x1234(:16|),er1" \ + "cmp.l #0x1234:16,er1" +gdb_test "x" "cmp.l\t#0x7(:3|),er2" \ + "cmp.l #0x7:3,er2" +gdb_test "x" "cmp.l\t#0x12345678(:32|),@er1" \ + "cmp.l #0x12345678:32,@er1" +gdb_test "x" "cmp.l\t#0x12345678(:32|),@\\(0xc(:2|),er1\\)" \ + "cmp.l #0x12345678:32,@(0xc:2,er1)" +gdb_test "x" "cmp.l\t#0x12345678(:32|),@er1\\+" \ + "cmp.l #0x12345678:32,@er1+" +gdb_test "x" "cmp.l\t#0x12345678(:32|),@-er1" \ + "cmp.l #0x12345678:32,@-er1" +gdb_test "x" "cmp.l\t#0x12345678(:32|),@\\+er1" \ + "cmp.l #0x12345678:32,@+er1" +gdb_test "x" "cmp.l\t#0x12345678(:32|),@er1-" \ + "cmp.l #0x12345678:32,@er1-" +gdb_test "x" "cmp.l\t#0x12345678(:32|),@\\(0x9abc(:16|),er1\\)" \ + "cmp.l #0x12345678:32,@(0x9abc:16,er1)" +gdb_test "x" "cmp.l\t#0x12345678(:32|),@\\(0x9abcdef0(:32|),er1\\)" \ + "cmp.l #0x12345678:32,@(0x9abcdef0:32,er1)" +gdb_test "x" "cmp.l\t#0x12345678(:32|),@\\(0x9abc(:16|),r2l.b\\)" \ + "cmp.l #0x12345678:32,@(0x9abc:16,r2l.b)" +gdb_test "x" "cmp.l\t#0x12345678(:32|),@\\(0x9abc(:16|),r2.w\\)" \ + "cmp.l #0x12345678:32,@(0x9abc:16,r2.w)" +gdb_test "x" "cmp.l\t#0x12345678(:32|),@\\(0x9abc(:16|),er2.l\\)" \ + "cmp.l #0x12345678:32,@(0x9abc:16,er2.l)" +gdb_test "x" "cmp.l\t#0x12345678(:32|),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "cmp.l #0x12345678:32,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "cmp.l\t#0x12345678(:32|),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "cmp.l #0x12345678:32,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "cmp.l\t#0x12345678(:32|),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "cmp.l #0x12345678:32,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "cmp.l\t#0x12345678(:32|),@0x9abc(:16|)" \ + "cmp.l #0x12345678:32,@0x9abc:16" +gdb_test "x" "cmp.l\t#0x12345678(:32|),@0x9abcdef0(:32|)" \ + "cmp.l #0x12345678:32,@0x9abcdef0:32" +gdb_test "x" "cmp.l\t#0x1234(:16|),@er1" \ + "cmp.l #0x1234:16,@er1" +gdb_test "x" "cmp.l\t#0x1234(:16|),@\\(0xc(:2|),er1\\)" \ + "cmp.l #0x1234:16,@(0xc:2,er1)" +gdb_test "x" "cmp.l\t#0x1234(:16|),@er1\\+" \ + "cmp.l #0x1234:16,@er1+" +gdb_test "x" "cmp.l\t#0x1234(:16|),@-er1" \ + "cmp.l #0x1234:16,@-er1" +gdb_test "x" "cmp.l\t#0x1234(:16|),@\\+er1" \ + "cmp.l #0x1234:16,@+er1" +gdb_test "x" "cmp.l\t#0x1234(:16|),@er1-" \ + "cmp.l #0x1234:16,@er1-" +gdb_test "x" "cmp.l\t#0x1234(:16|),@\\(0x9abc(:16|),er1\\)" \ + "cmp.l #0x1234:16,@(0x9abc:16,er1)" +gdb_test "x" "cmp.l\t#0x1234(:16|),@\\(0x9abcdef0(:32|),er1\\)" \ + "cmp.l #0x1234:16,@(0x9abcdef0:32,er1)" +gdb_test "x" "cmp.l\t#0x1234(:16|),@\\(0x9abc(:16|),r2l.b\\)" \ + "cmp.l #0x1234:16,@(0x9abc:16,r2l.b)" +gdb_test "x" "cmp.l\t#0x1234(:16|),@\\(0x9abc(:16|),r2.w\\)" \ + "cmp.l #0x1234:16,@(0x9abc:16,r2.w)" +gdb_test "x" "cmp.l\t#0x1234(:16|),@\\(0x9abc(:16|),er2.l\\)" \ + "cmp.l #0x1234:16,@(0x9abc:16,er2.l)" +gdb_test "x" "cmp.l\t#0x1234(:16|),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "cmp.l #0x1234:16,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "cmp.l\t#0x1234(:16|),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "cmp.l #0x1234:16,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "cmp.l\t#0x1234(:16|),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "cmp.l #0x1234:16,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "cmp.l\t#0x1234(:16|),@0x9abc(:16|)" \ + "cmp.l #0x1234:16,@0x9abc:16" +gdb_test "x" "cmp.l\t#0x1234(:16|),@0x9abcdef0(:32|)" \ + "cmp.l #0x1234:16,@0x9abcdef0:32" +gdb_test "x" "cmp.l\ter3,er1" \ + "cmp.l er3,er1" +gdb_test "x" "cmp.l\ter3,@er1" \ + "cmp.l er3,@er1" +gdb_test "x" "cmp.l\ter3,@\\(0xc(:2|),er1\\)" \ + "cmp.l er3,@(0xc:2,er1)" +gdb_test "x" "cmp.l\ter3,@er1\\+" \ + "cmp.l er3,@er1+" +gdb_test "x" "cmp.l\ter3,@-er1" \ + "cmp.l er3,@-er1" +gdb_test "x" "cmp.l\ter3,@\\+er1" \ + "cmp.l er3,@+er1" +gdb_test "x" "cmp.l\ter3,@er1-" \ + "cmp.l er3,@er1-" +gdb_test "x" "cmp.l\ter3,@\\(0x1234(:16|),er1\\)" \ + "cmp.l er3,@(0x1234:16,er1)" +gdb_test "x" "cmp.l\ter3,@\\(0x12345678(:32|),er1\\)" \ + "cmp.l er3,@(0x12345678:32,er1)" +gdb_test "x" "cmp.l\ter3,@\\(0x1234(:16|),r2l.b\\)" \ + "cmp.l er3,@(0x1234:16,r2l.b)" +gdb_test "x" "cmp.l\ter3,@\\(0x1234(:16|),r2.w\\)" \ + "cmp.l er3,@(0x1234:16,r2.w)" +gdb_test "x" "cmp.l\ter3,@\\(0x1234(:16|),er2.l\\)" \ + "cmp.l er3,@(0x1234:16,er2.l)" +gdb_test "x" "cmp.l\ter3,@\\(0x12345678(:32|),r2l.b\\)" \ + "cmp.l er3,@(0x12345678:32,r2l.b)" +gdb_test "x" "cmp.l\ter3,@\\(0x12345678(:32|),r2.w\\)" \ + "cmp.l er3,@(0x12345678:32,r2.w)" +gdb_test "x" "cmp.l\ter3,@\\(0x12345678(:32|),er2.l\\)" \ + "cmp.l er3,@(0x12345678:32,er2.l)" +gdb_test "x" "cmp.l\ter3,@0x1234(:16|)" \ + "cmp.l er3,@0x1234:16" +gdb_test "x" "cmp.l\ter3,@0x12345678(:32|)" \ + "cmp.l er3,@0x12345678:32" +gdb_test "x" "cmp.l\t@er3,er1" \ + "cmp.l @er3,er1" +gdb_test "x" "cmp.l\t@\\(0xc(:2|),er3\\),er1" \ + "cmp.l @(0xc:2,er3),er1" +gdb_test "x" "cmp.l\t@er3\\+,er1" \ + "cmp.l @er3+,er1" +gdb_test "x" "cmp.l\t@-er3,er1" \ + "cmp.l @-er3,er1" +gdb_test "x" "cmp.l\t@\\+er3,er1" \ + "cmp.l @+er3,er1" +gdb_test "x" "cmp.l\t@er3-,er1" \ + "cmp.l @er3-,er1" +gdb_test "x" "cmp.l\t@\\(0x1234(:16|),er1\\),er1" \ + "cmp.l @(0x1234:16,er1),er1" +gdb_test "x" "cmp.l\t@\\(0x12345678(:32|),er1\\),er1" \ + "cmp.l @(0x12345678:32,er1),er1" +gdb_test "x" "cmp.l\t@\\(0x1234(:16|),r2l.b\\),er1" \ + "cmp.l @(0x1234:16,r2l.b),er1" +gdb_test "x" "cmp.l\t@\\(0x1234(:16|),r2.w\\),er1" \ + "cmp.l @(0x1234:16,r2.w),er1" +gdb_test "x" "cmp.l\t@\\(0x1234(:16|),er2.l\\),er1" \ + "cmp.l @(0x1234:16,er2.l),er1" +gdb_test "x" "cmp.l\t@\\(0x12345678(:32|),r2l.b\\),er1" \ + "cmp.l @(0x12345678:32,r2l.b),er1" +gdb_test "x" "cmp.l\t@\\(0x12345678(:32|),r2.w\\),er1" \ + "cmp.l @(0x12345678:32,r2.w),er1" +gdb_test "x" "cmp.l\t@\\(0x12345678(:32|),er2.l\\),er1" \ + "cmp.l @(0x12345678:32,er2.l),er1" +gdb_test "x" "cmp.l\t@0x1234(:16|),er1" \ + "cmp.l @0x1234:16,er1" +gdb_test "x" "cmp.l\t@0x12345678(:32|),er1" \ + "cmp.l @0x12345678:32,er1" +gdb_test "x" "cmp.l\t@er3,@er1" \ + "cmp.l @er3,@er1" +gdb_test "x" "cmp.l\t@er3,@\\(0xc(:2|),er1\\)" \ + "cmp.l @er3,@(0xc:2,er1)" +gdb_test "x" "cmp.l\t@er3,@-er1" \ + "cmp.l @er3,@-er1" +gdb_test "x" "cmp.l\t@er3,@er1\\+" \ + "cmp.l @er3,@er1+" +gdb_test "x" "cmp.l\t@er3,@er1-" \ + "cmp.l @er3,@er1-" +gdb_test "x" "cmp.l\t@er3,@\\+er1" \ + "cmp.l @er3,@+er1" +gdb_test "x" "cmp.l\t@er3,@\\(0x9abc(:16|),er1\\)" \ + "cmp.l @er3,@(0x9abc:16,er1)" +gdb_test "x" "cmp.l\t@er3,@\\(0x9abcdef0(:32|),er1\\)" \ + "cmp.l @er3,@(0x9abcdef0:32,er1)" +gdb_test "x" "cmp.l\t@er3,@\\(0x9abc(:16|),r2l.b\\)" \ + "cmp.l @er3,@(0x9abc:16,r2l.b)" +gdb_test "x" "cmp.l\t@er3,@\\(0x9abc(:16|),r2.w\\)" \ + "cmp.l @er3,@(0x9abc:16,r2.w)" +gdb_test "x" "cmp.l\t@er3,@\\(0x9abc(:16|),er2.l\\)" \ + "cmp.l @er3,@(0x9abc:16,er2.l)" +gdb_test "x" "cmp.l\t@er3,@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "cmp.l @er3,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "cmp.l\t@er3,@\\(0x9abcdef0(:32|),r2.w\\)" \ + "cmp.l @er3,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "cmp.l\t@er3,@\\(0x9abcdef0(:32|),er2.l\\)" \ + "cmp.l @er3,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "cmp.l\t@er3,@0x9abc(:16|)" \ + "cmp.l @er3,@0x9abc:16" +gdb_test "x" "cmp.l\t@er3,@0x9abcdef0(:32|)" \ + "cmp.l @er3,@0x9abcdef0:32" +gdb_test "x" "cmp.l\t@\\(0xc(:2|),er3\\),@er1" \ + "cmp.l @(0xc:2,er3),@er1" +gdb_test "x" "cmp.l\t@\\(0xc(:2|),er3\\),@\\(0xc(:2|),er1\\)" \ + "cmp.l @(0xc:2,er3),@(0xc:2,er1)" +gdb_test "x" "cmp.l\t@\\(0xc(:2|),er3\\),@-er1" \ + "cmp.l @(0xc:2,er3),@-er1" +gdb_test "x" "cmp.l\t@\\(0xc(:2|),er3\\),@er1\\+" \ + "cmp.l @(0xc:2,er3),@er1+" +gdb_test "x" "cmp.l\t@\\(0xc(:2|),er3\\),@er1-" \ + "cmp.l @(0xc:2,er3),@er1-" +gdb_test "x" "cmp.l\t@\\(0xc(:2|),er3\\),@\\+er1" \ + "cmp.l @(0xc:2,er3),@+er1" +gdb_test "x" "cmp.l\t@\\(0xc(:2|),er3\\),@\\(0x9abc(:16|),er1\\)" \ + "cmp.l @(0xc:2,er3),@(0x9abc:16,er1)" +gdb_test "x" "cmp.l\t@\\(0xc(:2|),er3\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "cmp.l @(0xc:2,er3),@(0x9abcdef0:32,er1)" +gdb_test "x" "cmp.l\t@\\(0xc(:2|),er3\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "cmp.l @(0xc:2,er3),@(0x9abc:16,r2l.b)" +gdb_test "x" "cmp.l\t@\\(0xc(:2|),er3\\),@\\(0x9abc(:16|),r2.w\\)" \ + "cmp.l @(0xc:2,er3),@(0x9abc:16,r2.w)" +gdb_test "x" "cmp.l\t@\\(0xc(:2|),er3\\),@\\(0x9abc(:16|),er2.l\\)" \ + "cmp.l @(0xc:2,er3),@(0x9abc:16,er2.l)" +gdb_test "x" "cmp.l\t@\\(0xc(:2|),er3\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "cmp.l @(0xc:2,er3),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "cmp.l\t@\\(0xc(:2|),er3\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "cmp.l @(0xc:2,er3),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "cmp.l\t@\\(0xc(:2|),er3\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "cmp.l @(0xc:2,er3),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "cmp.l\t@\\(0xc(:2|),er3\\),@0x9abc(:16|)" \ + "cmp.l @(0xc:2,er3),@0x9abc:16" +gdb_test "x" "cmp.l\t@\\(0xc(:2|),er3\\),@0x9abcdef0(:32|)" \ + "cmp.l @(0xc:2,er3),@0x9abcdef0:32" +gdb_test "x" "cmp.l\t@-er3,@er1" \ + "cmp.l @-er3,@er1" +gdb_test "x" "cmp.l\t@-er3,@\\(0xc(:2|),er1\\)" \ + "cmp.l @-er3,@(0xc:2,er1)" +gdb_test "x" "cmp.l\t@-er3,@-er1" \ + "cmp.l @-er3,@-er1" +gdb_test "x" "cmp.l\t@-er3,@er1\\+" \ + "cmp.l @-er3,@er1+" +gdb_test "x" "cmp.l\t@-er3,@er1-" \ + "cmp.l @-er3,@er1-" +gdb_test "x" "cmp.l\t@-er3,@\\+er1" \ + "cmp.l @-er3,@+er1" +gdb_test "x" "cmp.l\t@-er3,@\\(0x9abc(:16|),er1\\)" \ + "cmp.l @-er3,@(0x9abc:16,er1)" +gdb_test "x" "cmp.l\t@-er3,@\\(0x9abcdef0(:32|),er1\\)" \ + "cmp.l @-er3,@(0x9abcdef0:32,er1)" +gdb_test "x" "cmp.l\t@-er3,@\\(0x9abc(:16|),r2l.b\\)" \ + "cmp.l @-er3,@(0x9abc:16,r2l.b)" +gdb_test "x" "cmp.l\t@-er3,@\\(0x9abc(:16|),r2.w\\)" \ + "cmp.l @-er3,@(0x9abc:16,r2.w)" +gdb_test "x" "cmp.l\t@-er3,@\\(0x9abc(:16|),er2.l\\)" \ + "cmp.l @-er3,@(0x9abc:16,er2.l)" +gdb_test "x" "cmp.l\t@-er3,@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "cmp.l @-er3,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "cmp.l\t@-er3,@\\(0x9abcdef0(:32|),r2.w\\)" \ + "cmp.l @-er3,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "cmp.l\t@-er3,@\\(0x9abcdef0(:32|),er2.l\\)" \ + "cmp.l @-er3,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "cmp.l\t@-er3,@0x9abc(:16|)" \ + "cmp.l @-er3,@0x9abc:16" +gdb_test "x" "cmp.l\t@-er3,@0x9abcdef0(:32|)" \ + "cmp.l @-er3,@0x9abcdef0:32" +gdb_test "x" "cmp.l\t@er3\\+,@er1" \ + "cmp.l @er3+,@er1" +gdb_test "x" "cmp.l\t@er3\\+,@\\(0xc(:2|),er1\\)" \ + "cmp.l @er3+,@(0xc:2,er1)" +gdb_test "x" "cmp.l\t@er3\\+,@-er1" \ + "cmp.l @er3+,@-er1" +gdb_test "x" "cmp.l\t@er3\\+,@er1\\+" \ + "cmp.l @er3+,@er1+" +gdb_test "x" "cmp.l\t@er3\\+,@er1-" \ + "cmp.l @er3+,@er1-" +gdb_test "x" "cmp.l\t@er3\\+,@\\+er1" \ + "cmp.l @er3+,@+er1" +gdb_test "x" "cmp.l\t@er3\\+,@\\(0x9abc(:16|),er1\\)" \ + "cmp.l @er3+,@(0x9abc:16,er1)" +gdb_test "x" "cmp.l\t@er3\\+,@\\(0x9abcdef0(:32|),er1\\)" \ + "cmp.l @er3+,@(0x9abcdef0:32,er1)" +gdb_test "x" "cmp.l\t@er3\\+,@\\(0x9abc(:16|),r2l.b\\)" \ + "cmp.l @er3+,@(0x9abc:16,r2l.b)" +gdb_test "x" "cmp.l\t@er3\\+,@\\(0x9abc(:16|),r2.w\\)" \ + "cmp.l @er3+,@(0x9abc:16,r2.w)" +gdb_test "x" "cmp.l\t@er3\\+,@\\(0x9abc(:16|),er2.l\\)" \ + "cmp.l @er3+,@(0x9abc:16,er2.l)" +gdb_test "x" "cmp.l\t@er3\\+,@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "cmp.l @er3+,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "cmp.l\t@er3\\+,@\\(0x9abcdef0(:32|),r2.w\\)" \ + "cmp.l @er3+,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "cmp.l\t@er3\\+,@\\(0x9abcdef0(:32|),er2.l\\)" \ + "cmp.l @er3+,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "cmp.l\t@er3\\+,@0x9abc(:16|)" \ + "cmp.l @er3+,@0x9abc:16" +gdb_test "x" "cmp.l\t@er3\\+,@0x9abcdef0(:32|)" \ + "cmp.l @er3+,@0x9abcdef0:32" +gdb_test "x" "cmp.l\t@er3-,@er1" \ + "cmp.l @er3-,@er1" +gdb_test "x" "cmp.l\t@er3-,@\\(0xc(:2|),er1\\)" \ + "cmp.l @er3-,@(0xc:2,er1)" +gdb_test "x" "cmp.l\t@er3-,@-er1" \ + "cmp.l @er3-,@-er1" +gdb_test "x" "cmp.l\t@er3-,@er1\\+" \ + "cmp.l @er3-,@er1+" +gdb_test "x" "cmp.l\t@er3-,@er1-" \ + "cmp.l @er3-,@er1-" +gdb_test "x" "cmp.l\t@er3-,@\\+er1" \ + "cmp.l @er3-,@+er1" +gdb_test "x" "cmp.l\t@er3-,@\\(0x9abc(:16|),er1\\)" \ + "cmp.l @er3-,@(0x9abc:16,er1)" +gdb_test "x" "cmp.l\t@er3-,@\\(0x9abcdef0(:32|),er1\\)" \ + "cmp.l @er3-,@(0x9abcdef0:32,er1)" +gdb_test "x" "cmp.l\t@er3-,@\\(0x9abc(:16|),r2l.b\\)" \ + "cmp.l @er3-,@(0x9abc:16,r2l.b)" +gdb_test "x" "cmp.l\t@er3-,@\\(0x9abc(:16|),r2.w\\)" \ + "cmp.l @er3-,@(0x9abc:16,r2.w)" +gdb_test "x" "cmp.l\t@er3-,@\\(0x9abc(:16|),er2.l\\)" \ + "cmp.l @er3-,@(0x9abc:16,er2.l)" +gdb_test "x" "cmp.l\t@er3-,@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "cmp.l @er3-,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "cmp.l\t@er3-,@\\(0x9abcdef0(:32|),r2.w\\)" \ + "cmp.l @er3-,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "cmp.l\t@er3-,@\\(0x9abcdef0(:32|),er2.l\\)" \ + "cmp.l @er3-,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "cmp.l\t@er3-,@0x9abc(:16|)" \ + "cmp.l @er3-,@0x9abc:16" +gdb_test "x" "cmp.l\t@er3-,@0x9abcdef0(:32|)" \ + "cmp.l @er3-,@0x9abcdef0:32" +gdb_test "x" "cmp.l\t@\\+er3,@er1" \ + "cmp.l @+er3,@er1" +gdb_test "x" "cmp.l\t@\\+er3,@\\(0xc(:2|),er1\\)" \ + "cmp.l @+er3,@(0xc:2,er1)" +gdb_test "x" "cmp.l\t@\\+er3,@-er1" \ + "cmp.l @+er3,@-er1" +gdb_test "x" "cmp.l\t@\\+er3,@er1\\+" \ + "cmp.l @+er3,@er1+" +gdb_test "x" "cmp.l\t@\\+er3,@er1-" \ + "cmp.l @+er3,@er1-" +gdb_test "x" "cmp.l\t@\\+er3,@\\+er1" \ + "cmp.l @+er3,@+er1" +gdb_test "x" "cmp.l\t@\\+er3,@\\(0x9abc(:16|),er1\\)" \ + "cmp.l @+er3,@(0x9abc:16,er1)" +gdb_test "x" "cmp.l\t@\\+er3,@\\(0x9abcdef0(:32|),er1\\)" \ + "cmp.l @+er3,@(0x9abcdef0:32,er1)" +gdb_test "x" "cmp.l\t@\\+er3,@\\(0x9abc(:16|),r2l.b\\)" \ + "cmp.l @+er3,@(0x9abc:16,r2l.b)" +gdb_test "x" "cmp.l\t@\\+er3,@\\(0x9abc(:16|),r2.w\\)" \ + "cmp.l @+er3,@(0x9abc:16,r2.w)" +gdb_test "x" "cmp.l\t@\\+er3,@\\(0x9abc(:16|),er2.l\\)" \ + "cmp.l @+er3,@(0x9abc:16,er2.l)" +gdb_test "x" "cmp.l\t@\\+er3,@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "cmp.l @+er3,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "cmp.l\t@\\+er3,@\\(0x9abcdef0(:32|),r2.w\\)" \ + "cmp.l @+er3,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "cmp.l\t@\\+er3,@\\(0x9abcdef0(:32|),er2.l\\)" \ + "cmp.l @+er3,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "cmp.l\t@\\+er3,@0x9abc(:16|)" \ + "cmp.l @+er3,@0x9abc:16" +gdb_test "x" "cmp.l\t@\\+er3,@0x9abcdef0(:32|)" \ + "cmp.l @+er3,@0x9abcdef0:32" +gdb_test "x" "cmp.l\t@\\(0x1234(:16|),er3\\),@er1" \ + "cmp.l @(0x1234:16,er3),@er1" +gdb_test "x" "cmp.l\t@\\(0x1234(:16|),er3\\),@\\(0xc(:2|),er1\\)" \ + "cmp.l @(0x1234:16,er3),@(0xc:2,er1)" +gdb_test "x" "cmp.l\t@\\(0x1234(:16|),er3\\),@-er1" \ + "cmp.l @(0x1234:16,er3),@-er1" +gdb_test "x" "cmp.l\t@\\(0x1234(:16|),er3\\),@er1\\+" \ + "cmp.l @(0x1234:16,er3),@er1+" +gdb_test "x" "cmp.l\t@\\(0x1234(:16|),er3\\),@er1-" \ + "cmp.l @(0x1234:16,er3),@er1-" +gdb_test "x" "cmp.l\t@\\(0x1234(:16|),er3\\),@\\+er1" \ + "cmp.l @(0x1234:16,er3),@+er1" +gdb_test "x" "cmp.l\t@\\(0x1234(:16|),er3\\),@\\(0x9abc(:16|),er1\\)" \ + "cmp.l @(0x1234:16,er3),@(0x9abc:16,er1)" +gdb_test "x" "cmp.l\t@\\(0x1234(:16|),er3\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "cmp.l @(0x1234:16,er3),@(0x9abcdef0:32,er1)" +gdb_test "x" "cmp.l\t@\\(0x1234(:16|),er3\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "cmp.l @(0x1234:16,er3),@(0x9abc:16,r2l.b)" +gdb_test "x" "cmp.l\t@\\(0x1234(:16|),er3\\),@\\(0x9abc(:16|),r2.w\\)" \ + "cmp.l @(0x1234:16,er3),@(0x9abc:16,r2.w)" +gdb_test "x" "cmp.l\t@\\(0x1234(:16|),er3\\),@\\(0x9abc(:16|),er2.l\\)" \ + "cmp.l @(0x1234:16,er3),@(0x9abc:16,er2.l)" +gdb_test "x" "cmp.l\t@\\(0x1234(:16|),er3\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "cmp.l @(0x1234:16,er3),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "cmp.l\t@\\(0x1234(:16|),er3\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "cmp.l @(0x1234:16,er3),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "cmp.l\t@\\(0x1234(:16|),er3\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "cmp.l @(0x1234:16,er3),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "cmp.l\t@\\(0x1234(:16|),er3\\),@0x9abc(:16|)" \ + "cmp.l @(0x1234:16,er3),@0x9abc:16" +gdb_test "x" "cmp.l\t@\\(0x1234(:16|),er3\\),@0x9abcdef0(:32|)" \ + "cmp.l @(0x1234:16,er3),@0x9abcdef0:32" +gdb_test "x" "cmp.l\t@\\(0x12345678(:32|),er3\\),@er1" \ + "cmp.l @(0x12345678:32,er3),@er1" +gdb_test "x" "cmp.l\t@\\(0x12345678(:32|),er3\\),@\\(0xc(:2|),er1\\)" \ + "cmp.l @(0x12345678:32,er3),@(0xc:2,er1)" +gdb_test "x" "cmp.l\t@\\(0x12345678(:32|),er3\\),@-er1" \ + "cmp.l @(0x12345678:32,er3),@-er1" +gdb_test "x" "cmp.l\t@\\(0x12345678(:32|),er3\\),@er1\\+" \ + "cmp.l @(0x12345678:32,er3),@er1+" +gdb_test "x" "cmp.l\t@\\(0x12345678(:32|),er3\\),@er1-" \ + "cmp.l @(0x12345678:32,er3),@er1-" +gdb_test "x" "cmp.l\t@\\(0x12345678(:32|),er3\\),@\\+er1" \ + "cmp.l @(0x12345678:32,er3),@+er1" +gdb_test "x" "cmp.l\t@\\(0x12345678(:32|),er3\\),@\\(0x9abc(:16|),er1\\)" \ + "cmp.l @(0x12345678:32,er3),@(0x9abc:16,er1)" +gdb_test "x" "cmp.l\t@\\(0x12345678(:32|),er3\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "cmp.l @(0x12345678:32,er3),@(0x9abcdef0:32,er1)" +gdb_test "x" "cmp.l\t@\\(0x12345678(:32|),er3\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "cmp.l @(0x12345678:32,er3),@(0x9abc:16,r2l.b)" +gdb_test "x" "cmp.l\t@\\(0x12345678(:32|),er3\\),@\\(0x9abc(:16|),r2.w\\)" \ + "cmp.l @(0x12345678:32,er3),@(0x9abc:16,r2.w)" +gdb_test "x" "cmp.l\t@\\(0x12345678(:32|),er3\\),@\\(0x9abc(:16|),er2.l\\)" \ + "cmp.l @(0x12345678:32,er3),@(0x9abc:16,er2.l)" +gdb_test "x" "cmp.l\t@\\(0x12345678(:32|),er3\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "cmp.l @(0x12345678:32,er3),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "cmp.l\t@\\(0x12345678(:32|),er3\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "cmp.l @(0x12345678:32,er3),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "cmp.l\t@\\(0x12345678(:32|),er3\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "cmp.l @(0x12345678:32,er3),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "cmp.l\t@\\(0x12345678(:32|),er3\\),@0x9abc(:16|)" \ + "cmp.l @(0x12345678:32,er3),@0x9abc:16" +gdb_test "x" "cmp.l\t@\\(0x12345678(:32|),er3\\),@0x9abcdef0(:32|)" \ + "cmp.l @(0x12345678:32,er3),@0x9abcdef0:32" +gdb_test "x" "cmp.l\t@\\(0x1234(:16|),r3l.b\\),@er1" \ + "cmp.l @(0x1234:16,r3l.b),@er1" +gdb_test "x" "cmp.l\t@\\(0x1234(:16|),r3l.b\\),@\\(0xc(:2|),er1\\)" \ + "cmp.l @(0x1234:16,r3l.b),@(0xc:2,er1)" +gdb_test "x" "cmp.l\t@\\(0x1234(:16|),r3l.b\\),@-er1" \ + "cmp.l @(0x1234:16,r3l.b),@-er1" +gdb_test "x" "cmp.l\t@\\(0x1234(:16|),r3l.b\\),@er1\\+" \ + "cmp.l @(0x1234:16,r3l.b),@er1+" +gdb_test "x" "cmp.l\t@\\(0x1234(:16|),r3l.b\\),@er1-" \ + "cmp.l @(0x1234:16,r3l.b),@er1-" +gdb_test "x" "cmp.l\t@\\(0x1234(:16|),r3l.b\\),@\\+er1" \ + "cmp.l @(0x1234:16,r3l.b),@+er1" +gdb_test "x" "cmp.l\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abc(:16|),er1\\)" \ + "cmp.l @(0x1234:16,r3l.b),@(0x9abc:16,er1)" +gdb_test "x" "cmp.l\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "cmp.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1)" +gdb_test "x" "cmp.l\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "cmp.l @(0x1234:16,r3l.b),@(0x9abc:16,r2l.b)" +gdb_test "x" "cmp.l\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abc(:16|),r2.w\\)" \ + "cmp.l @(0x1234:16,r3l.b),@(0x9abc:16,r2.w)" +gdb_test "x" "cmp.l\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abc(:16|),er2.l\\)" \ + "cmp.l @(0x1234:16,r3l.b),@(0x9abc:16,er2.l)" +gdb_test "x" "cmp.l\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "cmp.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "cmp.l\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "cmp.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "cmp.l\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "cmp.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "cmp.l\t@\\(0x1234(:16|),r3l.b\\),@0x9abc(:16|)" \ + "cmp.l @(0x1234:16,r3l.b),@0x9abc:16" +gdb_test "x" "cmp.l\t@\\(0x1234(:16|),r3l.b\\),@0x9abcdef0(:32|)" \ + "cmp.l @(0x1234:16,r3l.b),@0x9abcdef0:32" +gdb_test "x" "cmp.l\t@\\(0x1234(:16|),r3.w\\),@er1" \ + "cmp.l @(0x1234:16,r3.w),@er1" +gdb_test "x" "cmp.l\t@\\(0x1234(:16|),r3.w\\),@\\(0xc(:2|),er1\\)" \ + "cmp.l @(0x1234:16,r3.w),@(0xc:2,er1)" +gdb_test "x" "cmp.l\t@\\(0x1234(:16|),r3.w\\),@-er1" \ + "cmp.l @(0x1234:16,r3.w),@-er1" +gdb_test "x" "cmp.l\t@\\(0x1234(:16|),r3.w\\),@er1\\+" \ + "cmp.l @(0x1234:16,r3.w),@er1+" +gdb_test "x" "cmp.l\t@\\(0x1234(:16|),r3.w\\),@er1-" \ + "cmp.l @(0x1234:16,r3.w),@er1-" +gdb_test "x" "cmp.l\t@\\(0x1234(:16|),r3.w\\),@\\+er1" \ + "cmp.l @(0x1234:16,r3.w),@+er1" +gdb_test "x" "cmp.l\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abc(:16|),er1\\)" \ + "cmp.l @(0x1234:16,r3.w),@(0x9abc:16,er1)" +gdb_test "x" "cmp.l\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "cmp.l @(0x1234:16,r3.w),@(0x9abcdef0:32,er1)" +gdb_test "x" "cmp.l\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "cmp.l @(0x1234:16,r3.w),@(0x9abc:16,r2l.b)" +gdb_test "x" "cmp.l\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abc(:16|),r2.w\\)" \ + "cmp.l @(0x1234:16,r3.w),@(0x9abc:16,r2.w)" +gdb_test "x" "cmp.l\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abc(:16|),er2.l\\)" \ + "cmp.l @(0x1234:16,r3.w),@(0x9abc:16,er2.l)" +gdb_test "x" "cmp.l\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "cmp.l @(0x1234:16,r3.w),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "cmp.l\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "cmp.l @(0x1234:16,r3.w),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "cmp.l\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "cmp.l @(0x1234:16,r3.w),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "cmp.l\t@\\(0x1234(:16|),r3.w\\),@0x9abc(:16|)" \ + "cmp.l @(0x1234:16,r3.w),@0x9abc:16" +gdb_test "x" "cmp.l\t@\\(0x1234(:16|),r3.w\\),@0x9abcdef0(:32|)" \ + "cmp.l @(0x1234:16,r3.w),@0x9abcdef0:32" +gdb_test "x" "cmp.l\t@\\(0x1234(:16|),er3.l\\),@er1" \ + "cmp.l @(0x1234:16,er3.l),@er1" +gdb_test "x" "cmp.l\t@\\(0x1234(:16|),er3.l\\),@\\(0xc(:2|),er1\\)" \ + "cmp.l @(0x1234:16,er3.l),@(0xc:2,er1)" +gdb_test "x" "cmp.l\t@\\(0x1234(:16|),er3.l\\),@-er1" \ + "cmp.l @(0x1234:16,er3.l),@-er1" +gdb_test "x" "cmp.l\t@\\(0x1234(:16|),er3.l\\),@er1\\+" \ + "cmp.l @(0x1234:16,er3.l),@er1+" +gdb_test "x" "cmp.l\t@\\(0x1234(:16|),er3.l\\),@er1-" \ + "cmp.l @(0x1234:16,er3.l),@er1-" +gdb_test "x" "cmp.l\t@\\(0x1234(:16|),er3.l\\),@\\+er1" \ + "cmp.l @(0x1234:16,er3.l),@+er1" +gdb_test "x" "cmp.l\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abc(:16|),er1\\)" \ + "cmp.l @(0x1234:16,er3.l),@(0x9abc:16,er1)" +gdb_test "x" "cmp.l\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "cmp.l @(0x1234:16,er3.l),@(0x9abcdef0:32,er1)" +gdb_test "x" "cmp.l\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "cmp.l @(0x1234:16,er3.l),@(0x9abc:16,r2l.b)" +gdb_test "x" "cmp.l\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abc(:16|),r2.w\\)" \ + "cmp.l @(0x1234:16,er3.l),@(0x9abc:16,r2.w)" +gdb_test "x" "cmp.l\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abc(:16|),er2.l\\)" \ + "cmp.l @(0x1234:16,er3.l),@(0x9abc:16,er2.l)" +gdb_test "x" "cmp.l\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "cmp.l @(0x1234:16,er3.l),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "cmp.l\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "cmp.l @(0x1234:16,er3.l),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "cmp.l\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "cmp.l @(0x1234:16,er3.l),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "cmp.l\t@\\(0x1234(:16|),er3.l\\),@0x9abc(:16|)" \ + "cmp.l @(0x1234:16,er3.l),@0x9abc:16" +gdb_test "x" "cmp.l\t@\\(0x1234(:16|),er3.l\\),@0x9abcdef0(:32|)" \ + "cmp.l @(0x1234:16,er3.l),@0x9abcdef0:32" +gdb_test "x" "cmp.l\t@\\(0x12345678(:32|),r3l.b\\),@er1" \ + "cmp.l @(0x12345678:32,r3l.b),@er1" +gdb_test "x" "cmp.l\t@\\(0x12345678(:32|),r3l.b\\),@\\(0xc(:2|),er1\\)" \ + "cmp.l @(0x12345678:32,r3l.b),@(0xc:2,er1)" +gdb_test "x" "cmp.l\t@\\(0x12345678(:32|),r3l.b\\),@-er1" \ + "cmp.l @(0x12345678:32,r3l.b),@-er1" +gdb_test "x" "cmp.l\t@\\(0x12345678(:32|),r3l.b\\),@er1\\+" \ + "cmp.l @(0x12345678:32,r3l.b),@er1+" +gdb_test "x" "cmp.l\t@\\(0x12345678(:32|),r3l.b\\),@er1-" \ + "cmp.l @(0x12345678:32,r3l.b),@er1-" +gdb_test "x" "cmp.l\t@\\(0x12345678(:32|),r3l.b\\),@\\+er1" \ + "cmp.l @(0x12345678:32,r3l.b),@+er1" +gdb_test "x" "cmp.l\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abc(:16|),er1\\)" \ + "cmp.l @(0x12345678:32,r3l.b),@(0x9abc:16,er1)" +gdb_test "x" "cmp.l\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "cmp.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1)" +gdb_test "x" "cmp.l\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "cmp.l @(0x12345678:32,r3l.b),@(0x9abc:16,r2l.b)" +gdb_test "x" "cmp.l\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abc(:16|),r2.w\\)" \ + "cmp.l @(0x12345678:32,r3l.b),@(0x9abc:16,r2.w)" +gdb_test "x" "cmp.l\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abc(:16|),er2.l\\)" \ + "cmp.l @(0x12345678:32,r3l.b),@(0x9abc:16,er2.l)" +gdb_test "x" "cmp.l\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "cmp.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "cmp.l\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "cmp.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "cmp.l\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "cmp.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "cmp.l\t@\\(0x12345678(:32|),r3l.b\\),@0x9abc(:16|)" \ + "cmp.l @(0x12345678:32,r3l.b),@0x9abc:16" +gdb_test "x" "cmp.l\t@\\(0x12345678(:32|),r3l.b\\),@0x9abcdef0(:32|)" \ + "cmp.l @(0x12345678:32,r3l.b),@0x9abcdef0:32" +gdb_test "x" "cmp.l\t@\\(0x12345678(:32|),r3.w\\),@er1" \ + "cmp.l @(0x12345678:32,r3.w),@er1" +gdb_test "x" "cmp.l\t@\\(0x12345678(:32|),r3.w\\),@\\(0xc(:2|),er1\\)" \ + "cmp.l @(0x12345678:32,r3.w),@(0xc:2,er1)" +gdb_test "x" "cmp.l\t@\\(0x12345678(:32|),r3.w\\),@-er1" \ + "cmp.l @(0x12345678:32,r3.w),@-er1" +gdb_test "x" "cmp.l\t@\\(0x12345678(:32|),r3.w\\),@er1\\+" \ + "cmp.l @(0x12345678:32,r3.w),@er1+" +gdb_test "x" "cmp.l\t@\\(0x12345678(:32|),r3.w\\),@er1-" \ + "cmp.l @(0x12345678:32,r3.w),@er1-" +gdb_test "x" "cmp.l\t@\\(0x12345678(:32|),r3.w\\),@\\+er1" \ + "cmp.l @(0x12345678:32,r3.w),@+er1" +gdb_test "x" "cmp.l\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abc(:16|),er1\\)" \ + "cmp.l @(0x12345678:32,r3.w),@(0x9abc:16,er1)" +gdb_test "x" "cmp.l\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "cmp.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1)" +gdb_test "x" "cmp.l\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "cmp.l @(0x12345678:32,r3.w),@(0x9abc:16,r2l.b)" +gdb_test "x" "cmp.l\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abc(:16|),r2.w\\)" \ + "cmp.l @(0x12345678:32,r3.w),@(0x9abc:16,r2.w)" +gdb_test "x" "cmp.l\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abc(:16|),er2.l\\)" \ + "cmp.l @(0x12345678:32,r3.w),@(0x9abc:16,er2.l)" +gdb_test "x" "cmp.l\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "cmp.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "cmp.l\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "cmp.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "cmp.l\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "cmp.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "cmp.l\t@\\(0x12345678(:32|),r3.w\\),@0x9abc(:16|)" \ + "cmp.l @(0x12345678:32,r3.w),@0x9abc:16" +gdb_test "x" "cmp.l\t@\\(0x12345678(:32|),r3.w\\),@0x9abcdef0(:32|)" \ + "cmp.l @(0x12345678:32,r3.w),@0x9abcdef0:32" +gdb_test "x" "cmp.l\t@\\(0x12345678(:32|),er3.l\\),@er1" \ + "cmp.l @(0x12345678:32,er3.l),@er1" +gdb_test "x" "cmp.l\t@\\(0x12345678(:32|),er3.l\\),@\\(0xc(:2|),er1\\)" \ + "cmp.l @(0x12345678:32,er3.l),@(0xc:2,er1)" +gdb_test "x" "cmp.l\t@\\(0x12345678(:32|),er3.l\\),@-er1" \ + "cmp.l @(0x12345678:32,er3.l),@-er1" +gdb_test "x" "cmp.l\t@\\(0x12345678(:32|),er3.l\\),@er1\\+" \ + "cmp.l @(0x12345678:32,er3.l),@er1+" +gdb_test "x" "cmp.l\t@\\(0x12345678(:32|),er3.l\\),@er1-" \ + "cmp.l @(0x12345678:32,er3.l),@er1-" +gdb_test "x" "cmp.l\t@\\(0x12345678(:32|),er3.l\\),@\\+er1" \ + "cmp.l @(0x12345678:32,er3.l),@+er1" +gdb_test "x" "cmp.l\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abc(:16|),er1\\)" \ + "cmp.l @(0x12345678:32,er3.l),@(0x9abc:16,er1)" +gdb_test "x" "cmp.l\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "cmp.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1)" +gdb_test "x" "cmp.l\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "cmp.l @(0x12345678:32,er3.l),@(0x9abc:16,r2l.b)" +gdb_test "x" "cmp.l\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abc(:16|),r2.w\\)" \ + "cmp.l @(0x12345678:32,er3.l),@(0x9abc:16,r2.w)" +gdb_test "x" "cmp.l\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abc(:16|),er2.l\\)" \ + "cmp.l @(0x12345678:32,er3.l),@(0x9abc:16,er2.l)" +gdb_test "x" "cmp.l\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "cmp.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "cmp.l\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "cmp.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "cmp.l\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "cmp.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "cmp.l\t@\\(0x12345678(:32|),er3.l\\),@0x9abc(:16|)" \ + "cmp.l @(0x12345678:32,er3.l),@0x9abc:16" +gdb_test "x" "cmp.l\t@\\(0x12345678(:32|),er3.l\\),@0x9abcdef0(:32|)" \ + "cmp.l @(0x12345678:32,er3.l),@0x9abcdef0:32" +gdb_test "x" "cmp.l\t@0x1234(:16|),@er1" \ + "cmp.l @0x1234:16,@er1" +gdb_test "x" "cmp.l\t@0x1234(:16|),@\\(0xc(:2|),er1\\)" \ + "cmp.l @0x1234:16,@(0xc:2,er1)" +gdb_test "x" "cmp.l\t@0x1234(:16|),@-er1" \ + "cmp.l @0x1234:16,@-er1" +gdb_test "x" "cmp.l\t@0x1234(:16|),@er1\\+" \ + "cmp.l @0x1234:16,@er1+" +gdb_test "x" "cmp.l\t@0x1234(:16|),@er1-" \ + "cmp.l @0x1234:16,@er1-" +gdb_test "x" "cmp.l\t@0x1234(:16|),@\\+er1" \ + "cmp.l @0x1234:16,@+er1" +gdb_test "x" "cmp.l\t@0x1234(:16|),@\\(0x9abc(:16|),er1\\)" \ + "cmp.l @0x1234:16,@(0x9abc:16,er1)" +gdb_test "x" "cmp.l\t@0x1234(:16|),@\\(0x9abcdef0(:32|),er1\\)" \ + "cmp.l @0x1234:16,@(0x9abcdef0:32,er1)" +gdb_test "x" "cmp.l\t@0x1234(:16|),@\\(0x9abc(:16|),r2l.b\\)" \ + "cmp.l @0x1234:16,@(0x9abc:16,r2l.b)" +gdb_test "x" "cmp.l\t@0x1234(:16|),@\\(0x9abc(:16|),r2.w\\)" \ + "cmp.l @0x1234:16,@(0x9abc:16,r2.w)" +gdb_test "x" "cmp.l\t@0x1234(:16|),@\\(0x9abc(:16|),er2.l\\)" \ + "cmp.l @0x1234:16,@(0x9abc:16,er2.l)" +gdb_test "x" "cmp.l\t@0x1234(:16|),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "cmp.l @0x1234:16,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "cmp.l\t@0x1234(:16|),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "cmp.l @0x1234:16,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "cmp.l\t@0x1234(:16|),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "cmp.l @0x1234:16,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "cmp.l\t@0x1234(:16|),@0x9abc(:16|)" \ + "cmp.l @0x1234:16,@0x9abc:16" +gdb_test "x" "cmp.l\t@0x1234(:16|),@0x9abcdef0(:32|)" \ + "cmp.l @0x1234:16,@0x9abcdef0:32" +gdb_test "x" "cmp.l\t@0x12345678(:32|),@er1" \ + "cmp.l @0x12345678:32,@er1" +gdb_test "x" "cmp.l\t@0x12345678(:32|),@\\(0xc(:2|),er1\\)" \ + "cmp.l @0x12345678:32,@(0xc:2,er1)" +gdb_test "x" "cmp.l\t@0x12345678(:32|),@-er1" \ + "cmp.l @0x12345678:32,@-er1" +gdb_test "x" "cmp.l\t@0x12345678(:32|),@er1\\+" \ + "cmp.l @0x12345678:32,@er1+" +gdb_test "x" "cmp.l\t@0x12345678(:32|),@er1-" \ + "cmp.l @0x12345678:32,@er1-" +gdb_test "x" "cmp.l\t@0x12345678(:32|),@\\+er1" \ + "cmp.l @0x12345678:32,@+er1" +gdb_test "x" "cmp.l\t@0x12345678(:32|),@\\(0x9abc(:16|),er1\\)" \ + "cmp.l @0x12345678:32,@(0x9abc:16,er1)" +gdb_test "x" "cmp.l\t@0x12345678(:32|),@\\(0x9abcdef0(:32|),er1\\)" \ + "cmp.l @0x12345678:32,@(0x9abcdef0:32,er1)" +gdb_test "x" "cmp.l\t@0x12345678(:32|),@\\(0x9abc(:16|),r2l.b\\)" \ + "cmp.l @0x12345678:32,@(0x9abc:16,r2l.b)" +gdb_test "x" "cmp.l\t@0x12345678(:32|),@\\(0x9abc(:16|),r2.w\\)" \ + "cmp.l @0x12345678:32,@(0x9abc:16,r2.w)" +gdb_test "x" "cmp.l\t@0x12345678(:32|),@\\(0x9abc(:16|),er2.l\\)" \ + "cmp.l @0x12345678:32,@(0x9abc:16,er2.l)" +gdb_test "x" "cmp.l\t@0x12345678(:32|),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "cmp.l @0x12345678:32,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "cmp.l\t@0x12345678(:32|),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "cmp.l @0x12345678:32,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "cmp.l\t@0x12345678(:32|),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "cmp.l @0x12345678:32,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "cmp.l\t@0x12345678(:32|),@0x9abc(:16|)" \ + "cmp.l @0x12345678:32,@0x9abc:16" +gdb_test "x" "cmp.l\t@0x12345678(:32|),@0x9abcdef0(:32|)" \ + "cmp.l @0x12345678:32,@0x9abcdef0:32" diff --git a/gdb/testsuite/gdb.disasm/t05_cmp.s b/gdb/testsuite/gdb.disasm/t05_cmp.s new file mode 100644 index 0000000..eef3359 --- /dev/null +++ b/gdb/testsuite/gdb.disasm/t05_cmp.s @@ -0,0 +1,921 @@ +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;arith_1 +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + .h8300sx + .text + .global _start +_start: + cmp.b @er3,@er1 ;7c350120 + cmp.b @er3,@(3:2,er1) ;7c353120 + cmp.b @er3,@-er1 ;7c35b120 + cmp.b @er3,@er1+ ;7c358120 + cmp.b @er3,@er1- ;7c35a120 + cmp.b @er3,@+er1 ;7c359120 + cmp.b @er3,@(0xffff9abc:16,er1) ;7c35c1209abc + cmp.b @er3,@(0x9abcdef0:32,er1) ;7c35c9209abcdef0 + cmp.b @er3,@(0xffff9abc:16,r2l.b) ;7c35d2209abc + cmp.b @er3,@(0xffff9abc:16,r2.w) ;7c35e2209abc + cmp.b @er3,@(0xffff9abc:16,er2.l) ;7c35f2209abc + cmp.b @er3,@(0x9abcdef0:32,r2l.b) ;7c35da209abcdef0 + cmp.b @er3,@(0x9abcdef0:32,r2.w) ;7c35ea209abcdef0 + cmp.b @er3,@(0x9abcdef0:32,er2.l) ;7c35fa209abcdef0 + cmp.b @er3,@0xffff9abc:16 ;7c3540209abc + cmp.b @er3,@0x9abcdef0:32 ;7c3548209abcdef0 + + cmp.b @-er3,@er1 ;01776c3c0120 + cmp.b @-er3,@(3:2,er1) ;01776c3c3120 + cmp.b @-er3,@-er1 ;01776c3cb120 + cmp.b @-er3,@er1+ ;01776c3c8120 + cmp.b @-er3,@er1- ;01776c3ca120 + cmp.b @-er3,@+er1 ;01776c3c9120 + cmp.b @-er3,@(0xffff9abc:16,er1) ;01776c3cc1209abc + cmp.b @-er3,@(0x9abcdef0:32,er1) ;01776c3cc9209abcdef0 + cmp.b @-er3,@(0xffff9abc:16,r2l.b) ;01776c3cd2209abc + cmp.b @-er3,@(0xffff9abc:16,r2.w) ;01776c3ce2209abc + cmp.b @-er3,@(0xffff9abc:16,er2.l) ;01776c3cf2209abc + cmp.b @-er3,@(0x9abcdef0:32,r2l.b) ;01776c3cda209abcdef0 + cmp.b @-er3,@(0x9abcdef0:32,r2.w) ;01776c3cea209abcdef0 + cmp.b @-er3,@(0x9abcdef0:32,er2.l) ;01776c3cfa209abcdef0 + cmp.b @-er3,@0xffff9abc:16 ;01776c3c40209abc + cmp.b @-er3,@0x9abcdef0:32 ;01776c3c48209abcdef0 + + cmp.b @er3+,@er1 ;01746c3c0120 + cmp.b @er3+,@(3:2,er1) ;01746c3c3120 + cmp.b @er3+,@-er1 ;01746c3cb120 + cmp.b @er3+,@er1+ ;01746c3c8120 + cmp.b @er3+,@er1- ;01746c3ca120 + cmp.b @er3+,@+er1 ;01746c3c9120 + cmp.b @er3+,@(0xffff9abc:16,er1) ;01746c3cc1209abc + cmp.b @er3+,@(0x9abcdef0:32,er1) ;01746c3cc9209abcdef0 + cmp.b @er3+,@(0xffff9abc:16,r2l.b) ;01746c3cd2209abc + cmp.b @er3+,@(0xffff9abc:16,r2.w) ;01746c3ce2209abc + cmp.b @er3+,@(0xffff9abc:16,er2.l) ;01746c3cf2209abc + cmp.b @er3+,@(0x9abcdef0:32,r2l.b) ;01746c3cda209abcdef0 + cmp.b @er3+,@(0x9abcdef0:32,r2.w) ;01746c3cea209abcdef0 + cmp.b @er3+,@(0x9abcdef0:32,er2.l) ;01746c3cfa209abcdef0 + cmp.b @er3+,@0xffff9abc:16 ;01746c3c40209abc + cmp.b @er3+,@0x9abcdef0:32 ;01746c3c48209abcdef0 + + cmp.b @er3-,@er1 ;01766c3c0120 + cmp.b @er3-,@(3:2,er1) ;01766c3c3120 + cmp.b @er3-,@-er1 ;01766c3cb120 + cmp.b @er3-,@er1+ ;01766c3c8120 + cmp.b @er3-,@er1- ;01766c3ca120 + cmp.b @er3-,@+er1 ;01766c3c9120 + cmp.b @er3-,@(0xffff9abc:16,er1) ;01766c3cc1209abc + cmp.b @er3-,@(0x9abcdef0:32,er1) ;01766c3cc9209abcdef0 + cmp.b @er3-,@(0xffff9abc:16,r2l.b) ;01766c3cd2209abc + cmp.b @er3-,@(0xffff9abc:16,r2.w) ;01766c3ce2209abc + cmp.b @er3-,@(0xffff9abc:16,er2.l) ;01766c3cf2209abc + cmp.b @er3-,@(0x9abcdef0:32,r2l.b) ;01766c3cda209abcdef0 + cmp.b @er3-,@(0x9abcdef0:32,r2.w) ;01766c3cea209abcdef0 + cmp.b @er3-,@(0x9abcdef0:32,er2.l) ;01766c3cfa209abcdef0 + cmp.b @er3-,@0xffff9abc:16 ;01766c3c40209abc + cmp.b @er3-,@0x9abcdef0:32 ;01766c3c48209abcdef0 + + cmp.b @+er3,@er1 ;01756c3c0120 + cmp.b @+er3,@(3:2,er1) ;01756c3c3120 + cmp.b @+er3,@-er1 ;01756c3cb120 + cmp.b @+er3,@er1+ ;01756c3c8120 + cmp.b @+er3,@er1- ;01756c3ca120 + cmp.b @+er3,@+er1 ;01756c3c9120 + cmp.b @+er3,@(0xffff9abc:16,er1) ;01756c3cc1209abc + cmp.b @+er3,@(0x9abcdef0:32,er1) ;01756c3cc9209abcdef0 + cmp.b @+er3,@(0xffff9abc:16,r2l.b) ;01756c3cd2209abc + cmp.b @+er3,@(0xffff9abc:16,r2.w) ;01756c3ce2209abc + cmp.b @+er3,@(0xffff9abc:16,er2.l) ;01756c3cf2209abc + cmp.b @+er3,@(0x9abcdef0:32,r2l.b) ;01756c3cda209abcdef0 + cmp.b @+er3,@(0x9abcdef0:32,r2.w) ;01756c3cea209abcdef0 + cmp.b @+er3,@(0x9abcdef0:32,er2.l) ;01756c3cfa209abcdef0 + cmp.b @+er3,@0xffff9abc:16 ;01756c3c40209abc + cmp.b @+er3,@0x9abcdef0:32 ;01756c3c48209abcdef0 + + cmp.b @(0x1234:16,er3),@er1 ;01746e3c12340120 + cmp.b @(0x1234:16,er3),@(3:2,er1) ;01746e3c12343120 + cmp.b @(0x1234:16,er3),@-er1 ;01746e3c1234b120 + cmp.b @(0x1234:16,er3),@er1+ ;01746e3c12348120 + cmp.b @(0x1234:16,er3),@er1- ;01746e3c1234a120 + cmp.b @(0x1234:16,er3),@+er1 ;01746e3c12349120 + cmp.b @(0x1234:16,er3),@(0xffff9abc:16,er1) ;01746e3c1234c1209abc + cmp.b @(0x1234:16,er3),@(0x9abcdef0:32,er1) ;01746e3c1234c9209abcdef0 + cmp.b @(0x1234:16,er3),@(0xffff9abc:16,r2l.b) ;01746e3c1234d2209abc + cmp.b @(0x1234:16,er3),@(0xffff9abc:16,r2.w) ;01746e3c1234e2209abc + cmp.b @(0x1234:16,er3),@(0xffff9abc:16,er2.l) ;01746e3c1234f2209abc + cmp.b @(0x1234:16,er3),@(0x9abcdef0:32,r2l.b) ;01746e3c1234da209abcdef0 + cmp.b @(0x1234:16,er3),@(0x9abcdef0:32,r2.w) ;01746e3c1234ea209abcdef0 + cmp.b @(0x1234:16,er3),@(0x9abcdef0:32,er2.l) ;01746e3c1234fa209abcdef0 + cmp.b @(0x1234:16,er3),@0xffff9abc:16 ;01746e3c123440209abc + cmp.b @(0x1234:16,er3),@0x9abcdef0:32 ;01746e3c123448209abcdef0 + + cmp.b @(0x12345678:32,er3),@er1 ;78346a2c123456780120 + cmp.b @(0x12345678:32,er3),@(3:2,er1) ;78346a2c123456783120 + cmp.b @(0x12345678:32,er3),@-er1 ;78346a2c12345678b120 + cmp.b @(0x12345678:32,er3),@er1+ ;78346a2c123456788120 + cmp.b @(0x12345678:32,er3),@er1- ;78346a2c12345678a120 + cmp.b @(0x12345678:32,er3),@+er1 ;78346a2c123456789120 + cmp.b @(0x12345678:32,er3),@(0xffff9abc:16,er1) ;78346a2c12345678c1209abc + cmp.b @(0x12345678:32,er3),@(0x9abcdef0:32,er1) ;78346a2c12345678c9209abcdef0 + cmp.b @(0x12345678:32,er3),@(0xffff9abc:16,r2l.b) ;78346a2c12345678d2209abc + cmp.b @(0x12345678:32,er3),@(0xffff9abc:16,r2.w) ;78346a2c12345678e2209abc + cmp.b @(0x12345678:32,er3),@(0xffff9abc:16,er2.l) ;78346a2c12345678f2209abc + cmp.b @(0x12345678:32,er3),@(0x9abcdef0:32,r2l.b) ;78346a2c12345678da209abcdef0 + cmp.b @(0x12345678:32,er3),@(0x9abcdef0:32,r2.w) ;78346a2c12345678ea209abcdef0 + cmp.b @(0x12345678:32,er3),@(0x9abcdef0:32,er2.l) ;78346a2c12345678fa209abcdef0 + cmp.b @(0x12345678:32,er3),@0xffff9abc:16 ;78346a2c1234567840209abc + cmp.b @(0x12345678:32,er3),@0x9abcdef0:32 ;78346a2c1234567848209abcdef0 + + cmp.b @(0x1234:16,r3l.b),@er1 ;01756e3c12340120 + cmp.b @(0x1234:16,r3l.b),@(3:2,er1) ;01756e3c12343120 + cmp.b @(0x1234:16,r3l.b),@-er1 ;01756e3c1234b120 + cmp.b @(0x1234:16,r3l.b),@er1+ ;01756e3c12348120 + cmp.b @(0x1234:16,r3l.b),@er1- ;01756e3c1234a120 + cmp.b @(0x1234:16,r3l.b),@+er1 ;01756e3c12349120 + cmp.b @(0x1234:16,r3l.b),@(0xffff9abc:16,er1) ;01756e3c1234c1209abc + cmp.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1) ;01756e3c1234c9209abcdef0 + cmp.b @(0x1234:16,r3l.b),@(0xffff9abc:16,r2l.b) ;01756e3c1234d2209abc + cmp.b @(0x1234:16,r3l.b),@(0xffff9abc:16,r2.w) ;01756e3c1234e2209abc + cmp.b @(0x1234:16,r3l.b),@(0xffff9abc:16,er2.l) ;01756e3c1234f2209abc + cmp.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2l.b) ;01756e3c1234da209abcdef0 + cmp.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2.w) ;01756e3c1234ea209abcdef0 + cmp.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,er2.l) ;01756e3c1234fa209abcdef0 + cmp.b @(0x1234:16,r3l.b),@0xffff9abc:16 ;01756e3c123440209abc + cmp.b @(0x1234:16,r3l.b),@0x9abcdef0:32 ;01756e3c123448209abcdef0 + + cmp.b @(0x1234:16,r3.w),@er1 ;01766e3c12340120 + cmp.b @(0x1234:16,r3.w),@(3:2,er1) ;01766e3c12343120 + cmp.b @(0x1234:16,r3.w),@-er1 ;01766e3c1234b120 + cmp.b @(0x1234:16,r3.w),@er1+ ;01766e3c12348120 + cmp.b @(0x1234:16,r3.w),@er1- ;01766e3c1234a120 + cmp.b @(0x1234:16,r3.w),@+er1 ;01766e3c12349120 + cmp.b @(0x1234:16,r3.w),@(0xffff9abc:16,er1) ;01766e3c1234c1209abc + cmp.b @(0x1234:16,r3.w),@(0x9abcdef0:32,er1) ;01766e3c1234c9209abcdef0 + cmp.b @(0x1234:16,r3.w),@(0xffff9abc:16,r2l.b) ;01766e3c1234d2209abc + cmp.b @(0x1234:16,r3.w),@(0xffff9abc:16,r2.w) ;01766e3c1234e2209abc + cmp.b @(0x1234:16,r3.w),@(0xffff9abc:16,er2.l) ;01766e3c1234f2209abc + cmp.b @(0x1234:16,r3.w),@(0x9abcdef0:32,r2l.b) ;01766e3c1234da209abcdef0 + cmp.b @(0x1234:16,r3.w),@(0x9abcdef0:32,r2.w) ;01766e3c1234ea209abcdef0 + cmp.b @(0x1234:16,r3.w),@(0x9abcdef0:32,er2.l) ;01766e3c1234fa209abcdef0 + cmp.b @(0x1234:16,r3.w),@0xffff9abc:16 ;01766e3c123440209abc + cmp.b @(0x1234:16,r3.w),@0x9abcdef0:32 ;01766e3c123448209abcdef0 + + cmp.b @(0x1234:16,er3.l),@er1 ;01776e3c12340120 + cmp.b @(0x1234:16,er3.l),@(3:2,er1) ;01776e3c12343120 + cmp.b @(0x1234:16,er3.l),@-er1 ;01776e3c1234b120 + cmp.b @(0x1234:16,er3.l),@er1+ ;01776e3c12348120 + cmp.b @(0x1234:16,er3.l),@er1- ;01776e3c1234a120 + cmp.b @(0x1234:16,er3.l),@+er1 ;01776e3c12349120 + cmp.b @(0x1234:16,er3.l),@(0xffff9abc:16,er1) ;01776e3c1234c1209abc + cmp.b @(0x1234:16,er3.l),@(0x9abcdef0:32,er1) ;01776e3c1234c9209abcdef0 + cmp.b @(0x1234:16,er3.l),@(0xffff9abc:16,r2l.b) ;01776e3c1234d2209abc + cmp.b @(0x1234:16,er3.l),@(0xffff9abc:16,r2.w) ;01776e3c1234e2209abc + cmp.b @(0x1234:16,er3.l),@(0xffff9abc:16,er2.l) ;01776e3c1234f2209abc + cmp.b @(0x1234:16,er3.l),@(0x9abcdef0:32,r2l.b) ;01776e3c1234da209abcdef0 + cmp.b @(0x1234:16,er3.l),@(0x9abcdef0:32,r2.w) ;01776e3c1234ea209abcdef0 + cmp.b @(0x1234:16,er3.l),@(0x9abcdef0:32,er2.l) ;01776e3c1234fa209abcdef0 + cmp.b @(0x1234:16,er3.l),@0xffff9abc:16 ;01776e3c123440209abc + cmp.b @(0x1234:16,er3.l),@0x9abcdef0:32 ;01776e3c123448209abcdef0 + + cmp.b @(0x12345678:32,r3l.b),@er1 ;78356a2c123456780120 + cmp.b @(0x12345678:32,r3l.b),@(3:2,er1) ;78356a2c123456783120 + cmp.b @(0x12345678:32,r3l.b),@-er1 ;78356a2c12345678b120 + cmp.b @(0x12345678:32,r3l.b),@er1+ ;78356a2c123456788120 + cmp.b @(0x12345678:32,r3l.b),@er1- ;78356a2c12345678a120 + cmp.b @(0x12345678:32,r3l.b),@+er1 ;78356a2c123456789120 + cmp.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,er1) ;78356a2c12345678c1209abc + cmp.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1) ;78356a2c12345678c9209abcdef0 + cmp.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2l.b) ;78356a2c12345678d2209abc + cmp.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2.w) ;78356a2c12345678e2209abc + cmp.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,er2.l) ;78356a2c12345678f2209abc + cmp.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2l.b) ;78356a2c12345678da209abcdef0 + cmp.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2.w) ;78356a2c12345678ea209abcdef0 + cmp.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er2.l) ;78356a2c12345678fa209abcdef0 + cmp.b @(0x12345678:32,r3l.b),@0xffff9abc:16 ;78356a2c1234567840209abc + cmp.b @(0x12345678:32,r3l.b),@0x9abcdef0:32 ;78356a2c1234567848209abcdef0 + + cmp.b @(0x12345678:32,r3.w),@er1 ;78366a2c123456780120 + cmp.b @(0x12345678:32,r3.w),@(3:2,er1) ;78366a2c123456783120 + cmp.b @(0x12345678:32,r3.w),@-er1 ;78366a2c12345678b120 + cmp.b @(0x12345678:32,r3.w),@er1+ ;78366a2c123456788120 + cmp.b @(0x12345678:32,r3.w),@er1- ;78366a2c12345678a120 + cmp.b @(0x12345678:32,r3.w),@+er1 ;78366a2c123456789120 + cmp.b @(0x12345678:32,r3.w),@(0xffff9abc:16,er1) ;78366a2c12345678c1209abc + cmp.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1) ;78366a2c12345678c9209abcdef0 + cmp.b @(0x12345678:32,r3.w),@(0xffff9abc:16,r2l.b) ;78366a2c12345678d2209abc + cmp.b @(0x12345678:32,r3.w),@(0xffff9abc:16,r2.w) ;78366a2c12345678e2209abc + cmp.b @(0x12345678:32,r3.w),@(0xffff9abc:16,er2.l) ;78366a2c12345678f2209abc + cmp.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2l.b) ;78366a2c12345678da209abcdef0 + cmp.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2.w) ;78366a2c12345678ea209abcdef0 + cmp.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,er2.l) ;78366a2c12345678fa209abcdef0 + cmp.b @(0x12345678:32,r3.w),@0xffff9abc:16 ;78366a2c1234567840209abc + cmp.b @(0x12345678:32,r3.w),@0x9abcdef0:32 ;78366a2c1234567848209abcdef0 + + cmp.b @(0x12345678:32,er3.l),@er1 ;78376a2c123456780120 + cmp.b @(0x12345678:32,er3.l),@(3:2,er1) ;78376a2c123456783120 + cmp.b @(0x12345678:32,er3.l),@-er1 ;78376a2c12345678b120 + cmp.b @(0x12345678:32,er3.l),@er1+ ;78376a2c123456788120 + cmp.b @(0x12345678:32,er3.l),@er1- ;78376a2c12345678a120 + cmp.b @(0x12345678:32,er3.l),@+er1 ;78376a2c123456789120 + cmp.b @(0x12345678:32,er3.l),@(0xffff9abc:16,er1) ;78376a2c12345678c1209abc + cmp.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1) ;78376a2c12345678c9209abcdef0 + cmp.b @(0x12345678:32,er3.l),@(0xffff9abc:16,r2l.b) ;78376a2c12345678d2209abc + cmp.b @(0x12345678:32,er3.l),@(0xffff9abc:16,r2.w) ;78376a2c12345678e2209abc + cmp.b @(0x12345678:32,er3.l),@(0xffff9abc:16,er2.l) ;78376a2c12345678f2209abc + cmp.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2l.b) ;78376a2c12345678da209abcdef0 + cmp.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2.w) ;78376a2c12345678ea209abcdef0 + cmp.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,er2.l) ;78376a2c12345678fa209abcdef0 + cmp.b @(0x12345678:32,er3.l),@0xffff9abc:16 ;78376a2c1234567840209abc + cmp.b @(0x12345678:32,er3.l),@0x9abcdef0:32 ;78376a2c1234567848209abcdef0 + + cmp.b @0x1234:16,@er1 ;6a1512340120 + cmp.b @0x1234:16,@(3:2,er1) ;6a1512343120 + cmp.b @0x1234:16,@-er1 ;6a151234b120 + cmp.b @0x1234:16,@er1+ ;6a1512348120 + cmp.b @0x1234:16,@er1- ;6a151234a120 + cmp.b @0x1234:16,@+er1 ;6a1512349120 + cmp.b @0x1234:16,@(0xffff9abc:16,er1) ;6a151234c1209abc + cmp.b @0x1234:16,@(0x9abcdef0:32,er1) ;6a151234c9209abcdef0 + cmp.b @0x1234:16,@(0xffff9abc:16,r2l.b) ;6a151234d2209abc + cmp.b @0x1234:16,@(0xffff9abc:16,r2.w) ;6a151234e2209abc + cmp.b @0x1234:16,@(0xffff9abc:16,er2.l) ;6a151234f2209abc + cmp.b @0x1234:16,@(0x9abcdef0:32,r2l.b) ;6a151234da209abcdef0 + cmp.b @0x1234:16,@(0x9abcdef0:32,r2.w) ;6a151234ea209abcdef0 + cmp.b @0x1234:16,@(0x9abcdef0:32,er2.l) ;6a151234fa209abcdef0 + cmp.b @0x1234:16,@0xffff9abc:16 ;6a15123440209abc + cmp.b @0x1234:16,@0x9abcdef0:32 ;6a15123448209abcdef0 + + cmp.b @0x12345678:32,@er1 ;6a35123456780120 + cmp.b @0x12345678:32,@(3:2,er1) ;6a35123456783120 + cmp.b @0x12345678:32,@-er1 ;6a3512345678b120 + cmp.b @0x12345678:32,@er1+ ;6a35123456788120 + cmp.b @0x12345678:32,@er1- ;6a3512345678a120 + cmp.b @0x12345678:32,@+er1 ;6a35123456789120 + cmp.b @0x12345678:32,@(0xffff9abc:16,er1) ;6a3512345678c1209abc + cmp.b @0x12345678:32,@(0x9abcdef0:32,er1) ;6a3512345678c9209abcdef0 + cmp.b @0x12345678:32,@(0xffff9abc:16,r2l.b) ;6a3512345678d2209abc + cmp.b @0x12345678:32,@(0xffff9abc:16,r2.w) ;6a3512345678e2209abc + cmp.b @0x12345678:32,@(0xffff9abc:16,er2.l) ;6a3512345678f2209abc + cmp.b @0x12345678:32,@(0x9abcdef0:32,r2l.b) ;6a3512345678da209abcdef0 + cmp.b @0x12345678:32,@(0x9abcdef0:32,r2.w) ;6a3512345678ea209abcdef0 + cmp.b @0x12345678:32,@(0x9abcdef0:32,er2.l) ;6a3512345678fa209abcdef0 + cmp.b @0x12345678:32,@0xffff9abc:16 ;6a351234567840209abc + cmp.b @0x12345678:32,@0x9abcdef0:32 ;6a351234567848209abcdef0 + + cmp.w #0x1234:16,r1 ;79211234 + cmp.w #0x7:3,r2 ;1f72 + cmp.w #0x1234:16,@er1 ;015e01201234 + cmp.w #0x1234:16,@(0x6:2,er1) ;015e31201234 + cmp.w #0x1234:16,@er1+ ;015e81201234 + cmp.w #0x1234:16,@-er1 ;015eb1201234 + cmp.w #0x1234:16,@+er1 ;015e91201234 + cmp.w #0x1234:16,@er1- ;015ea1201234 + cmp.w #0x1234:16,@(0xffff9abc:16,er1) ;015ec1209abc1234 + cmp.w #0x1234:16,@(0x9abcdef0:32,er1) ;015ec9209abcdef01234 + cmp.w #0x1234:16,@(0xffff9abc:16,r2l.b) ;015ed2209abc1234 + cmp.w #0x1234:16,@(0xffff9abc:16,r2.w) ;015ee2209abc1234 + cmp.w #0x1234:16,@(0xffff9abc:16,er2.l) ;015ef2209abc1234 + cmp.w #0x1234:16,@(0x9abcdef0:32,r2l.b) ;015eda209abcdef01234 + cmp.w #0x1234:16,@(0x9abcdef0:32,r2.w) ;015eea209abcdef01234 + cmp.w #0x1234:16,@(0x9abcdef0:32,er2.l) ;015efa209abcdef01234 + cmp.w #0x1234:16,@0xffff9abc:16 ;015e40209abc1234 + cmp.w #0x1234:16,@0x9abcdef0:32 ;015e48209abcdef01234 + + cmp.w #0x7:3,@er1 ;7d901f70 + cmp.w #0x7:3,@0x1234:16 ;6b1812341f70 + cmp.w #0x7:3,@0x12345678:32 ;6b38123456781f70 + + cmp.w r3,r1 ;1d31 + + cmp.w r3,@er1 ;7d901d30 + cmp.w r3,@(0x6:2,er1) ;01593123 + cmp.w r3,@er1+ ;01598123 + cmp.w r3,@-er1 ;0159b123 + cmp.w r3,@+er1 ;01599123 + cmp.w r3,@er1- ;0159a123 + cmp.w r3,@(0x1234:16,er1) ;0159c1231234 + cmp.w r3,@(0x12345678:32,er1) ;0159c92312345678 + cmp.w r3,@(0x1234:16,r2l.b) ;0159d2231234 + cmp.w r3,@(0x1234:16,r2.w) ;0159e2231234 + cmp.w r3,@(0x1234:16,er2.l) ;0159f2231234 + cmp.w r3,@(0x12345678:32,r2l.b) ;0159da2312345678 + cmp.w r3,@(0x12345678:32,r2.w) ;0159ea2312345678 + cmp.w r3,@(0x12345678:32,er2.l) ;0159fa2312345678 + cmp.w r3,@0x1234:16 ;6b1812341d30 + cmp.w r3,@0x12345678:32 ;6b38123456781d30 + + cmp.w @er3,r1 ;7cb01d01 + cmp.w @(0x6:2,er3),r1 ;015a3321 + cmp.w @er3+,r1 ;015a8321 + cmp.w @-er3,r1 ;015ab321 + cmp.w @+er3,r1 ;015a9321 + cmp.w @er3-,r1 ;015aa321 + cmp.w @(0x1234:16,er1),r1 ;015ac1211234 + cmp.w @(0x12345678:32,er1),r1 ;015ac92112345678 + cmp.w @(0x1234:16,r2l.b),r1 ;015ad2211234 + cmp.w @(0x1234:16,r2.w),r1 ;015ae2211234 + cmp.w @(0x1234:16,er2.l),r1 ;015af2211234 + cmp.w @(0x12345678:32,r2l.b),r1 ;015ada2112345678 + cmp.w @(0x12345678:32,r2.w),r1 ;015aea2112345678 + cmp.w @(0x12345678:32,er2.l),r1 ;015afa2112345678 + cmp.w @0x1234:16,r1 ;6b1012341d01 + cmp.w @0x12345678:32,r1 ;6b30123456781d01 + + cmp.w @er3,@er1 ;7cb50120 + cmp.w @er3,@(6:2,er1) ;7cb53120 + cmp.w @er3,@-er1 ;7cb5b120 + cmp.w @er3,@er1+ ;7cb58120 + cmp.w @er3,@er1- ;7cb5a120 + cmp.w @er3,@+er1 ;7cb59120 + cmp.w @er3,@(0xffff9abc:16,er1) ;7cb5c1209abc + cmp.w @er3,@(0x9abcdef0:32,er1) ;7cb5c9209abcdef0 + cmp.w @er3,@(0xffff9abc:16,r2l.b) ;7cb5d2209abc + cmp.w @er3,@(0xffff9abc:16,r2.w) ;7cb5e2209abc + cmp.w @er3,@(0xffff9abc:16,er2.l) ;7cb5f2209abc + cmp.w @er3,@(0x9abcdef0:32,r2l.b) ;7cb5da209abcdef0 + cmp.w @er3,@(0x9abcdef0:32,r2.w) ;7cb5ea209abcdef0 + cmp.w @er3,@(0x9abcdef0:32,er2.l) ;7cb5fa209abcdef0 + cmp.w @er3,@0xffff9abc:16 ;7cb540209abc + cmp.w @er3,@0x9abcdef0:32 ;7cb548209abcdef0 + + cmp.w @-er3,@er1 ;01576d3c0120 + cmp.w @-er3,@(6:2,er1) ;01576d3c3120 + cmp.w @-er3,@-er1 ;01576d3cb120 + cmp.w @-er3,@er1+ ;01576d3c8120 + cmp.w @-er3,@er1- ;01576d3ca120 + cmp.w @-er3,@+er1 ;01576d3c9120 + cmp.w @-er3,@(0xffff9abc:16,er1) ;01576d3cc1209abc + cmp.w @-er3,@(0x9abcdef0:32,er1) ;01576d3cc9209abcdef0 + cmp.w @-er3,@(0xffff9abc:16,r2l.b) ;01576d3cd2209abc + cmp.w @-er3,@(0xffff9abc:16,r2.w) ;01576d3ce2209abc + cmp.w @-er3,@(0xffff9abc:16,er2.l) ;01576d3cf2209abc + cmp.w @-er3,@(0x9abcdef0:32,r2l.b) ;01576d3cda209abcdef0 + cmp.w @-er3,@(0x9abcdef0:32,r2.w) ;01576d3cea209abcdef0 + cmp.w @-er3,@(0x9abcdef0:32,er2.l) ;01576d3cfa209abcdef0 + cmp.w @-er3,@0xffff9abc:16 ;01576d3c40209abc + cmp.w @-er3,@0x9abcdef0:32 ;01576d3c48209abcdef0 + + cmp.w @er3+,@er1 ;01546d3c0120 + cmp.w @er3+,@(6:2,er1) ;01546d3c3120 + cmp.w @er3+,@-er1 ;01546d3cb120 + cmp.w @er3+,@er1+ ;01546d3c8120 + cmp.w @er3+,@er1- ;01546d3ca120 + cmp.w @er3+,@+er1 ;01546d3c9120 + cmp.w @er3+,@(0xffff9abc:16,er1) ;01546d3cc1209abc + cmp.w @er3+,@(0x9abcdef0:32,er1) ;01546d3cc9209abcdef0 + cmp.w @er3+,@(0xffff9abc:16,r2l.b) ;01546d3cd2209abc + cmp.w @er3+,@(0xffff9abc:16,r2.w) ;01546d3ce2209abc + cmp.w @er3+,@(0xffff9abc:16,er2.l) ;01546d3cf2209abc + cmp.w @er3+,@(0x9abcdef0:32,r2l.b) ;01546d3cda209abcdef0 + cmp.w @er3+,@(0x9abcdef0:32,r2.w) ;01546d3cea209abcdef0 + cmp.w @er3+,@(0x9abcdef0:32,er2.l) ;01546d3cfa209abcdef0 + cmp.w @er3+,@0xffff9abc:16 ;01546d3c40209abc + cmp.w @er3+,@0x9abcdef0:32 ;01546d3c48209abcdef0 + + cmp.w @er3-,@er1 ;01566d3c0120 + cmp.w @er3-,@(6:2,er1) ;01566d3c3120 + cmp.w @er3-,@-er1 ;01566d3cb120 + cmp.w @er3-,@er1+ ;01566d3c8120 + cmp.w @er3-,@er1- ;01566d3ca120 + cmp.w @er3-,@+er1 ;01566d3c9120 + cmp.w @er3-,@(0xffff9abc:16,er1) ;01566d3cc1209abc + cmp.w @er3-,@(0x9abcdef0:32,er1) ;01566d3cc9209abcdef0 + cmp.w @er3-,@(0xffff9abc:16,r2l.b) ;01566d3cd2209abc + cmp.w @er3-,@(0xffff9abc:16,r2.w) ;01566d3ce2209abc + cmp.w @er3-,@(0xffff9abc:16,er2.l) ;01566d3cf2209abc + cmp.w @er3-,@(0x9abcdef0:32,r2l.b) ;01566d3cda209abcdef0 + cmp.w @er3-,@(0x9abcdef0:32,r2.w) ;01566d3cea209abcdef0 + cmp.w @er3-,@(0x9abcdef0:32,er2.l) ;01566d3cfa209abcdef0 + cmp.w @er3-,@0xffff9abc:16 ;01566d3c40209abc + cmp.w @er3-,@0x9abcdef0:32 ;01566d3c48209abcdef0 + + cmp.w @+er3,@er1 ;01556d3c0120 + cmp.w @+er3,@(6:2,er1) ;01556d3c3120 + cmp.w @+er3,@-er1 ;01556d3cb120 + cmp.w @+er3,@er1+ ;01556d3c8120 + cmp.w @+er3,@er1- ;01556d3ca120 + cmp.w @+er3,@+er1 ;01556d3c9120 + cmp.w @+er3,@(0xffff9abc:16,er1) ;01556d3cc1209abc + cmp.w @+er3,@(0x9abcdef0:32,er1) ;01556d3cc9209abcdef0 + cmp.w @+er3,@(0xffff9abc:16,r2l.b) ;01556d3cd2209abc + cmp.w @+er3,@(0xffff9abc:16,r2.w) ;01556d3ce2209abc + cmp.w @+er3,@(0xffff9abc:16,er2.l) ;01556d3cf2209abc + cmp.w @+er3,@(0x9abcdef0:32,r2l.b) ;01556d3cda209abcdef0 + cmp.w @+er3,@(0x9abcdef0:32,r2.w) ;01556d3cea209abcdef0 + cmp.w @+er3,@(0x9abcdef0:32,er2.l) ;01556d3cfa209abcdef0 + cmp.w @+er3,@0xffff9abc:16 ;01556d3c40209abc + cmp.w @+er3,@0x9abcdef0:32 ;01556d3c48209abcdef0 + + cmp.w @(0x1234:16,er3),@er1 ;01546f3c12340120 + cmp.w @(0x1234:16,er3),@(6:2,er1) ;01546f3c12343120 + cmp.w @(0x1234:16,er3),@-er1 ;01546f3c1234b120 + cmp.w @(0x1234:16,er3),@er1+ ;01546f3c12348120 + cmp.w @(0x1234:16,er3),@er1- ;01546f3c1234a120 + cmp.w @(0x1234:16,er3),@+er1 ;01546f3c12349120 + cmp.w @(0x1234:16,er3),@(0xffff9abc:16,er1) ;01546f3c1234c1209abc + cmp.w @(0x1234:16,er3),@(0x9abcdef0:32,er1) ;01546f3c1234c9209abcdef0 + cmp.w @(0x1234:16,er3),@(0xffff9abc:16,r2l.b) ;01546f3c1234d2209abc + cmp.w @(0x1234:16,er3),@(0xffff9abc:16,r2.w) ;01546f3c1234e2209abc + cmp.w @(0x1234:16,er3),@(0xffff9abc:16,er2.l) ;01546f3c1234f2209abc + cmp.w @(0x1234:16,er3),@(0x9abcdef0:32,r2l.b) ;01546f3c1234da209abcdef0 + cmp.w @(0x1234:16,er3),@(0x9abcdef0:32,r2.w) ;01546f3c1234ea209abcdef0 + cmp.w @(0x1234:16,er3),@(0x9abcdef0:32,er2.l) ;01546f3c1234fa209abcdef0 + cmp.w @(0x1234:16,er3),@0xffff9abc:16 ;01546f3c123440209abc + cmp.w @(0x1234:16,er3),@0x9abcdef0:32 ;01546f3c123448209abcdef0 + + cmp.w @(0x12345678:32,er3),@er1 ;78346b2c123456780120 + cmp.w @(0x12345678:32,er3),@(6:2,er1) ;78346b2c123456783120 + cmp.w @(0x12345678:32,er3),@-er1 ;78346b2c12345678b120 + cmp.w @(0x12345678:32,er3),@er1+ ;78346b2c123456788120 + cmp.w @(0x12345678:32,er3),@er1- ;78346b2c12345678a120 + cmp.w @(0x12345678:32,er3),@+er1 ;78346b2c123456789120 + cmp.w @(0x12345678:32,er3),@(0xffff9abc:16,er1) ;78346b2c12345678c1209abc + cmp.w @(0x12345678:32,er3),@(0x9abcdef0:32,er1) ;78346b2c12345678c9209abcdef0 + cmp.w @(0x12345678:32,er3),@(0xffff9abc:16,r2l.b) ;78346b2c12345678d2209abc + cmp.w @(0x12345678:32,er3),@(0xffff9abc:16,r2.w) ;78346b2c12345678e2209abc + cmp.w @(0x12345678:32,er3),@(0xffff9abc:16,er2.l) ;78346b2c12345678f2209abc + cmp.w @(0x12345678:32,er3),@(0x9abcdef0:32,r2l.b) ;78346b2c12345678da209abcdef0 + cmp.w @(0x12345678:32,er3),@(0x9abcdef0:32,r2.w) ;78346b2c12345678ea209abcdef0 + cmp.w @(0x12345678:32,er3),@(0x9abcdef0:32,er2.l) ;78346b2c12345678fa209abcdef0 + cmp.w @(0x12345678:32,er3),@0xffff9abc:16 ;78346b2c1234567840209abc + cmp.w @(0x12345678:32,er3),@0x9abcdef0:32 ;78346b2c1234567848209abcdef0 + + cmp.w @(0x1234:16,r3l.b),@er1 ;01556f3c12340120 + cmp.w @(0x1234:16,r3l.b),@(6:2,er1) ;01556f3c12343120 + cmp.w @(0x1234:16,r3l.b),@-er1 ;01556f3c1234b120 + cmp.w @(0x1234:16,r3l.b),@er1+ ;01556f3c12348120 + cmp.w @(0x1234:16,r3l.b),@er1- ;01556f3c1234a120 + cmp.w @(0x1234:16,r3l.b),@+er1 ;01556f3c12349120 + cmp.w @(0x1234:16,r3l.b),@(0xffff9abc:16,er1) ;01556f3c1234c1209abc + cmp.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1) ;01556f3c1234c9209abcdef0 + cmp.w @(0x1234:16,r3l.b),@(0xffff9abc:16,r2l.b) ;01556f3c1234d2209abc + cmp.w @(0x1234:16,r3l.b),@(0xffff9abc:16,r2.w) ;01556f3c1234e2209abc + cmp.w @(0x1234:16,r3l.b),@(0xffff9abc:16,er2.l) ;01556f3c1234f2209abc + cmp.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2l.b) ;01556f3c1234da209abcdef0 + cmp.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2.w) ;01556f3c1234ea209abcdef0 + cmp.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,er2.l) ;01556f3c1234fa209abcdef0 + cmp.w @(0x1234:16,r3l.b),@0xffff9abc:16 ;01556f3c123440209abc + cmp.w @(0x1234:16,r3l.b),@0x9abcdef0:32 ;01556f3c123448209abcdef0 + + cmp.w @(0x1234:16,r3.w),@er1 ;01566f3c12340120 + cmp.w @(0x1234:16,r3.w),@(6:2,er1) ;01566f3c12343120 + cmp.w @(0x1234:16,r3.w),@-er1 ;01566f3c1234b120 + cmp.w @(0x1234:16,r3.w),@er1+ ;01566f3c12348120 + cmp.w @(0x1234:16,r3.w),@er1- ;01566f3c1234a120 + cmp.w @(0x1234:16,r3.w),@+er1 ;01566f3c12349120 + cmp.w @(0x1234:16,r3.w),@(0xffff9abc:16,er1) ;01566f3c1234c1209abc + cmp.w @(0x1234:16,r3.w),@(0x9abcdef0:32,er1) ;01566f3c1234c9209abcdef0 + cmp.w @(0x1234:16,r3.w),@(0xffff9abc:16,r2l.b) ;01566f3c1234d2209abc + cmp.w @(0x1234:16,r3.w),@(0xffff9abc:16,r2.w) ;01566f3c1234e2209abc + cmp.w @(0x1234:16,r3.w),@(0xffff9abc:16,er2.l) ;01566f3c1234f2209abc + cmp.w @(0x1234:16,r3.w),@(0x9abcdef0:32,r2l.b) ;01566f3c1234da209abcdef0 + cmp.w @(0x1234:16,r3.w),@(0x9abcdef0:32,r2.w) ;01566f3c1234ea209abcdef0 + cmp.w @(0x1234:16,r3.w),@(0x9abcdef0:32,er2.l) ;01566f3c1234fa209abcdef0 + cmp.w @(0x1234:16,r3.w),@0xffff9abc:16 ;01566f3c123440209abc + cmp.w @(0x1234:16,r3.w),@0x9abcdef0:32 ;01566f3c123448209abcdef0 + + cmp.w @(0x1234:16,er3.l),@er1 ;01576f3c12340120 + cmp.w @(0x1234:16,er3.l),@(6:2,er1) ;01576f3c12343120 + cmp.w @(0x1234:16,er3.l),@-er1 ;01576f3c1234b120 + cmp.w @(0x1234:16,er3.l),@er1+ ;01576f3c12348120 + cmp.w @(0x1234:16,er3.l),@er1- ;01576f3c1234a120 + cmp.w @(0x1234:16,er3.l),@+er1 ;01576f3c12349120 + cmp.w @(0x1234:16,er3.l),@(0xffff9abc:16,er1) ;01576f3c1234c1209abc + cmp.w @(0x1234:16,er3.l),@(0x9abcdef0:32,er1) ;01576f3c1234c9209abcdef0 + cmp.w @(0x1234:16,er3.l),@(0xffff9abc:16,r2l.b) ;01576f3c1234d2209abc + cmp.w @(0x1234:16,er3.l),@(0xffff9abc:16,r2.w) ;01576f3c1234e2209abc + cmp.w @(0x1234:16,er3.l),@(0xffff9abc:16,er2.l) ;01576f3c1234f2209abc + cmp.w @(0x1234:16,er3.l),@(0x9abcdef0:32,r2l.b) ;01576f3c1234da209abcdef0 + cmp.w @(0x1234:16,er3.l),@(0x9abcdef0:32,r2.w) ;01576f3c1234ea209abcdef0 + cmp.w @(0x1234:16,er3.l),@(0x9abcdef0:32,er2.l) ;01576f3c1234fa209abcdef0 + cmp.w @(0x1234:16,er3.l),@0xffff9abc:16 ;01576f3c123440209abc + cmp.w @(0x1234:16,er3.l),@0x9abcdef0:32 ;01576f3c123448209abcdef0 + + cmp.w @(0x12345678:32,r3l.b),@er1 ;78356b2c123456780120 + cmp.w @(0x12345678:32,r3l.b),@(6:2,er1) ;78356b2c123456783120 + cmp.w @(0x12345678:32,r3l.b),@-er1 ;78356b2c12345678b120 + cmp.w @(0x12345678:32,r3l.b),@er1+ ;78356b2c123456788120 + cmp.w @(0x12345678:32,r3l.b),@er1- ;78356b2c12345678a120 + cmp.w @(0x12345678:32,r3l.b),@+er1 ;78356b2c123456789120 + cmp.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,er1) ;78356b2c12345678c1209abc + cmp.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1) ;78356b2c12345678c9209abcdef0 + cmp.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2l.b) ;78356b2c12345678d2209abc + cmp.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2.w) ;78356b2c12345678e2209abc + cmp.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,er2.l) ;78356b2c12345678f2209abc + cmp.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2l.b) ;78356b2c12345678da209abcdef0 + cmp.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2.w) ;78356b2c12345678ea209abcdef0 + cmp.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er2.l) ;78356b2c12345678fa209abcdef0 + cmp.w @(0x12345678:32,r3l.b),@0xffff9abc:16 ;78356b2c1234567840209abc + cmp.w @(0x12345678:32,r3l.b),@0x9abcdef0:32 ;78356b2c1234567848209abcdef0 + + cmp.w @(0x12345678:32,r3.w),@er1 ;78366b2c123456780120 + cmp.w @(0x12345678:32,r3.w),@(6:2,er1) ;78366b2c123456783120 + cmp.w @(0x12345678:32,r3.w),@-er1 ;78366b2c12345678b120 + cmp.w @(0x12345678:32,r3.w),@er1+ ;78366b2c123456788120 + cmp.w @(0x12345678:32,r3.w),@er1- ;78366b2c12345678a120 + cmp.w @(0x12345678:32,r3.w),@+er1 ;78366b2c123456789120 + cmp.w @(0x12345678:32,r3.w),@(0xffff9abc:16,er1) ;78366b2c12345678c1209abc + cmp.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1) ;78366b2c12345678c9209abcdef0 + cmp.w @(0x12345678:32,r3.w),@(0xffff9abc:16,r2l.b) ;78366b2c12345678d2209abc + cmp.w @(0x12345678:32,r3.w),@(0xffff9abc:16,r2.w) ;78366b2c12345678e2209abc + cmp.w @(0x12345678:32,r3.w),@(0xffff9abc:16,er2.l) ;78366b2c12345678f2209abc + cmp.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2l.b) ;78366b2c12345678da209abcdef0 + cmp.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2.w) ;78366b2c12345678ea209abcdef0 + cmp.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,er2.l) ;78366b2c12345678fa209abcdef0 + cmp.w @(0x12345678:32,r3.w),@0xffff9abc:16 ;78366b2c1234567840209abc + cmp.w @(0x12345678:32,r3.w),@0x9abcdef0:32 ;78366b2c1234567848209abcdef0 + + cmp.w @(0x12345678:32,er3.l),@er1 ;78376b2c123456780120 + cmp.w @(0x12345678:32,er3.l),@(6:2,er1) ;78376b2c123456783120 + cmp.w @(0x12345678:32,er3.l),@-er1 ;78376b2c12345678b120 + cmp.w @(0x12345678:32,er3.l),@er1+ ;78376b2c123456788120 + cmp.w @(0x12345678:32,er3.l),@er1- ;78376b2c12345678a120 + cmp.w @(0x12345678:32,er3.l),@+er1 ;78376b2c123456789120 + cmp.w @(0x12345678:32,er3.l),@(0xffff9abc:16,er1) ;78376b2c12345678c1209abc + cmp.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1) ;78376b2c12345678c9209abcdef0 + cmp.w @(0x12345678:32,er3.l),@(0xffff9abc:16,r2l.b) ;78376b2c12345678d2209abc + cmp.w @(0x12345678:32,er3.l),@(0xffff9abc:16,r2.w) ;78376b2c12345678e2209abc + cmp.w @(0x12345678:32,er3.l),@(0xffff9abc:16,er2.l) ;78376b2c12345678f2209abc + cmp.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2l.b) ;78376b2c12345678da209abcdef0 + cmp.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2.w) ;78376b2c12345678ea209abcdef0 + cmp.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,er2.l) ;78376b2c12345678fa209abcdef0 + cmp.w @(0x12345678:32,er3.l),@0xffff9abc:16 ;78376b2c1234567840209abc + cmp.w @(0x12345678:32,er3.l),@0x9abcdef0:32 ;78376b2c1234567848209abcdef0 + + cmp.w @0x1234:16,@er1 ;6b1512340120 + cmp.w @0x1234:16,@(6:2,er1) ;6b1512343120 + cmp.w @0x1234:16,@-er1 ;6b151234b120 + cmp.w @0x1234:16,@er1+ ;6b1512348120 + cmp.w @0x1234:16,@er1- ;6b151234a120 + cmp.w @0x1234:16,@+er1 ;6b1512349120 + cmp.w @0x1234:16,@(0xffff9abc:16,er1) ;6b151234c1209abc + cmp.w @0x1234:16,@(0x9abcdef0:32,er1) ;6b151234c9209abcdef0 + cmp.w @0x1234:16,@(0xffff9abc:16,r2l.b) ;6b151234d2209abc + cmp.w @0x1234:16,@(0xffff9abc:16,r2.w) ;6b151234e2209abc + cmp.w @0x1234:16,@(0xffff9abc:16,er2.l) ;6b151234f2209abc + cmp.w @0x1234:16,@(0x9abcdef0:32,r2l.b) ;6b151234da209abcdef0 + cmp.w @0x1234:16,@(0x9abcdef0:32,r2.w) ;6b151234ea209abcdef0 + cmp.w @0x1234:16,@(0x9abcdef0:32,er2.l) ;6b151234fa209abcdef0 + cmp.w @0x1234:16,@0xffff9abc:16 ;6b15123440209abc + cmp.w @0x1234:16,@0x9abcdef0:32 ;6b15123448209abcdef0 + + cmp.w @0x12345678:32,@er1 ;6b35123456780120 + cmp.w @0x12345678:32,@(6:2,er1) ;6b35123456783120 + cmp.w @0x12345678:32,@-er1 ;6b3512345678b120 + cmp.w @0x12345678:32,@er1+ ;6b35123456788120 + cmp.w @0x12345678:32,@er1- ;6b3512345678a120 + cmp.w @0x12345678:32,@+er1 ;6b35123456789120 + cmp.w @0x12345678:32,@(0xffff9abc:16,er1) ;6b3512345678c1209abc + cmp.w @0x12345678:32,@(0x9abcdef0:32,er1) ;6b3512345678c9209abcdef0 + cmp.w @0x12345678:32,@(0xffff9abc:16,r2l.b) ;6b3512345678d2209abc + cmp.w @0x12345678:32,@(0xffff9abc:16,r2.w) ;6b3512345678e2209abc + cmp.w @0x12345678:32,@(0xffff9abc:16,er2.l) ;6b3512345678f2209abc + cmp.w @0x12345678:32,@(0x9abcdef0:32,r2l.b) ;6b3512345678da209abcdef0 + cmp.w @0x12345678:32,@(0x9abcdef0:32,r2.w) ;6b3512345678ea209abcdef0 + cmp.w @0x12345678:32,@(0x9abcdef0:32,er2.l) ;6b3512345678fa209abcdef0 + cmp.w @0x12345678:32,@0xffff9abc:16 ;6b351234567840209abc + cmp.w @0x12345678:32,@0x9abcdef0:32 ;6b351234567848209abcdef0 + + cmp.l #0x12345678:32,er1 ;7a2112345678 + cmp.l #0x1234:16,er1 ;7a291234 + cmp.l #0x7:3,er2 ;1ffa + cmp.l #0x12345678:32,@er1 ;010e012812345678 + cmp.l #0x12345678:32,@(0xc:2,er1) ;010e312812345678 + cmp.l #0x12345678:32,@er1+ ;010e812812345678 + cmp.l #0x12345678:32,@-er1 ;010eb12812345678 + cmp.l #0x12345678:32,@+er1 ;010e912812345678 + cmp.l #0x12345678:32,@er1- ;010ea12812345678 + cmp.l #0x12345678:32,@(0xffff9abc:16,er1) ;010ec1289abc12345678 + cmp.l #0x12345678:32,@(0x9abcdef0:32,er1) ;010ec9289abcdef012345678 + cmp.l #0x12345678:32,@(0xffff9abc:16,r2l.b) ;010ed2289abc12345678 + cmp.l #0x12345678:32,@(0xffff9abc:16,r2.w) ;010ee2289abc12345678 + cmp.l #0x12345678:32,@(0xffff9abc:16,er2.l) ;010ef2289abc12345678 + cmp.l #0x12345678:32,@(0x9abcdef0:32,r2l.b) ;010eda289abcdef012345678 + cmp.l #0x12345678:32,@(0x9abcdef0:32,r2.w) ;010eea289abcdef012345678 + cmp.l #0x12345678:32,@(0x9abcdef0:32,er2.l) ;010efa289abcdef012345678 + cmp.l #0x12345678:32,@0xffff9abc:16 ;010e40289abc12345678 + cmp.l #0x12345678:32,@0x9abcdef0:32 ;010e48289abcdef012345678 + cmp.l #0x1234:16,@er1 ;010e01201234 + cmp.l #0x1234:16,@(0xc:2,er1) ;010e31201234 + cmp.l #0x1234:16,@er1+ ;010e81201234 + cmp.l #0x1234:16,@-er1 ;010eb1201234 + cmp.l #0x1234:16,@+er1 ;010e91201234 + cmp.l #0x1234:16,@er1- ;010ea1201234 + cmp.l #0x1234:16,@(0xffff9abc:16,er1) ;010ec1209abc1234 + cmp.l #0x1234:16,@(0x9abcdef0:32,er1) ;010ec9209abcdef01234 + cmp.l #0x1234:16,@(0xffff9abc:16,r2l.b) ;010ed2209abc1234 + cmp.l #0x1234:16,@(0xffff9abc:16,r2.w) ;010ee2209abc1234 + cmp.l #0x1234:16,@(0xffff9abc:16,er2.l) ;010ef2209abc1234 + cmp.l #0x1234:16,@(0x9abcdef0:32,r2l.b) ;010eda209abcdef01234 + cmp.l #0x1234:16,@(0x9abcdef0:32,r2.w) ;010eea209abcdef01234 + cmp.l #0x1234:16,@(0x9abcdef0:32,er2.l) ;010efa209abcdef01234 + cmp.l #0x1234:16,@0xffff9abc:16 ;010e40209abc1234 + cmp.l #0x1234:16,@0x9abcdef0:32 ;010e48209abcdef01234 + + cmp.l er3,er1 ;1fb1 + + cmp.l er3,@er1 ;01090123 + cmp.l er3,@(0xc:2,er1) ;01093123 + cmp.l er3,@er1+ ;01098123 + cmp.l er3,@-er1 ;0109b123 + cmp.l er3,@+er1 ;01099123 + cmp.l er3,@er1- ;0109a123 + cmp.l er3,@(0x1234:16,er1) ;0109c1231234 + cmp.l er3,@(0x12345678:32,er1) ;0109c92312345678 + cmp.l er3,@(0x1234:16,r2l.b) ;0109d2231234 + cmp.l er3,@(0x1234:16,r2.w) ;0109e2231234 + cmp.l er3,@(0x1234:16,er2.l) ;0109f2231234 + cmp.l er3,@(0x12345678:32,r2l.b) ;0109da2312345678 + cmp.l er3,@(0x12345678:32,r2.w) ;0109ea2312345678 + cmp.l er3,@(0x12345678:32,er2.l) ;0109fa2312345678 + cmp.l er3,@0x1234:16 ;010940231234 + cmp.l er3,@0x12345678:32 ;0109482312345678 + + cmp.l @er3,er1 ;010a0321 + cmp.l @(0xc:2,er3),er1 ;010a3321 + cmp.l @er3+,er1 ;010a8321 + cmp.l @-er3,er1 ;010ab321 + cmp.l @+er3,er1 ;010a9321 + cmp.l @er3-,er1 ;010aa321 + cmp.l @(0x1234:16,er1),er1 ;010ac1211234 + cmp.l @(0x12345678:32,er1),er1 ;010ac92112345678 + cmp.l @(0x1234:16,r2l.b),er1 ;010ad2211234 + cmp.l @(0x1234:16,r2.w),er1 ;010ae2211234 + cmp.l @(0x1234:16,er2.l),er1 ;010af2211234 + cmp.l @(0x12345678:32,r2l.b),er1 ;010ada2112345678 + cmp.l @(0x12345678:32,r2.w),er1 ;010aea2112345678 + cmp.l @(0x12345678:32,er2.l),er1 ;010afa2112345678 + cmp.l @0x1234:16,er1 ;010a40211234 + cmp.l @0x12345678:32,er1 ;010a482112345678 + + cmp.l @er3,@er1 ;0104693c0120 + cmp.l @er3,@(0xc:2,er1) ;0104693c3120 + cmp.l @er3,@-er1 ;0104693cb120 + cmp.l @er3,@er1+ ;0104693c8120 + cmp.l @er3,@er1- ;0104693ca120 + cmp.l @er3,@+er1 ;0104693c9120 + cmp.l @er3,@(0xffff9abc:16,er1) ;0104693cc1209abc + cmp.l @er3,@(0x9abcdef0:32,er1) ;0104693cc9209abcdef0 + cmp.l @er3,@(0xffff9abc:16,r2l.b) ;0104693cd2209abc + cmp.l @er3,@(0xffff9abc:16,r2.w) ;0104693ce2209abc + cmp.l @er3,@(0xffff9abc:16,er2.l) ;0104693cf2209abc + cmp.l @er3,@(0x9abcdef0:32,r2l.b) ;0104693cda209abcdef0 + cmp.l @er3,@(0x9abcdef0:32,r2.w) ;0104693cea209abcdef0 + cmp.l @er3,@(0x9abcdef0:32,er2.l) ;0104693cfa209abcdef0 + cmp.l @er3,@0xffff9abc:16 ;0104693c40209abc + cmp.l @er3,@0x9abcdef0:32 ;0104693c48209abcdef0 + + cmp.l @(0xc:2,er3),@er1 ;0107693c0120 + cmp.l @(0xc:2,er3),@(0xc:2,er1) ;0107693c3120 + cmp.l @(0xc:2,er3),@-er1 ;0107693cb120 + cmp.l @(0xc:2,er3),@er1+ ;0107693c8120 + cmp.l @(0xc:2,er3),@er1- ;0107693ca120 + cmp.l @(0xc:2,er3),@+er1 ;0107693c9120 + cmp.l @(0xc:2,er3),@(0xffff9abc:16,er1) ;0107693cc1209abc + cmp.l @(0xc:2,er3),@(0x9abcdef0:32,er1) ;0107693cc9209abcdef0 + cmp.l @(0xc:2,er3),@(0xffff9abc:16,r2l.b) ;0107693cd2209abc + cmp.l @(0xc:2,er3),@(0xffff9abc:16,r2.w) ;0107693ce2209abc + cmp.l @(0xc:2,er3),@(0xffff9abc:16,er2.l) ;0107693cf2209abc + cmp.l @(0xc:2,er3),@(0x9abcdef0:32,r2l.b) ;0107693cda209abcdef0 + cmp.l @(0xc:2,er3),@(0x9abcdef0:32,r2.w) ;0107693cea209abcdef0 + cmp.l @(0xc:2,er3),@(0x9abcdef0:32,er2.l) ;0107693cfa209abcdef0 + cmp.l @(0xc:2,er3),@0xffff9abc:16 ;0107693c40209abc + cmp.l @(0xc:2,er3),@0x9abcdef0:32 ;0107693c48209abcdef0 + + cmp.l @-er3,@er1 ;01076d3c0120 + cmp.l @-er3,@(0xc:2,er1) ;01076d3c3120 + cmp.l @-er3,@-er1 ;01076d3cb120 + cmp.l @-er3,@er1+ ;01076d3c8120 + cmp.l @-er3,@er1- ;01076d3ca120 + cmp.l @-er3,@+er1 ;01076d3c9120 + cmp.l @-er3,@(0xffff9abc:16,er1) ;01076d3cc1209abc + cmp.l @-er3,@(0x9abcdef0:32,er1) ;01076d3cc9209abcdef0 + cmp.l @-er3,@(0xffff9abc:16,r2l.b) ;01076d3cd2209abc + cmp.l @-er3,@(0xffff9abc:16,r2.w) ;01076d3ce2209abc + cmp.l @-er3,@(0xffff9abc:16,er2.l) ;01076d3cf2209abc + cmp.l @-er3,@(0x9abcdef0:32,r2l.b) ;01076d3cda209abcdef0 + cmp.l @-er3,@(0x9abcdef0:32,r2.w) ;01076d3cea209abcdef0 + cmp.l @-er3,@(0x9abcdef0:32,er2.l) ;01076d3cfa209abcdef0 + cmp.l @-er3,@0xffff9abc:16 ;01076d3c40209abc + cmp.l @-er3,@0x9abcdef0:32 ;01076d3c48209abcdef0 + + cmp.l @er3+,@er1 ;01046d3c0120 + cmp.l @er3+,@(0xc:2,er1) ;01046d3c3120 + cmp.l @er3+,@-er1 ;01046d3cb120 + cmp.l @er3+,@er1+ ;01046d3c8120 + cmp.l @er3+,@er1- ;01046d3ca120 + cmp.l @er3+,@+er1 ;01046d3c9120 + cmp.l @er3+,@(0xffff9abc:16,er1) ;01046d3cc1209abc + cmp.l @er3+,@(0x9abcdef0:32,er1) ;01046d3cc9209abcdef0 + cmp.l @er3+,@(0xffff9abc:16,r2l.b) ;01046d3cd2209abc + cmp.l @er3+,@(0xffff9abc:16,r2.w) ;01046d3ce2209abc + cmp.l @er3+,@(0xffff9abc:16,er2.l) ;01046d3cf2209abc + cmp.l @er3+,@(0x9abcdef0:32,r2l.b) ;01046d3cda209abcdef0 + cmp.l @er3+,@(0x9abcdef0:32,r2.w) ;01046d3cea209abcdef0 + cmp.l @er3+,@(0x9abcdef0:32,er2.l) ;01046d3cfa209abcdef0 + cmp.l @er3+,@0xffff9abc:16 ;01046d3c40209abc + cmp.l @er3+,@0x9abcdef0:32 ;01046d3c48209abcdef0 + + cmp.l @er3-,@er1 ;01066d3c0120 + cmp.l @er3-,@(0xc:2,er1) ;01066d3c3120 + cmp.l @er3-,@-er1 ;01066d3cb120 + cmp.l @er3-,@er1+ ;01066d3c8120 + cmp.l @er3-,@er1- ;01066d3ca120 + cmp.l @er3-,@+er1 ;01066d3c9120 + cmp.l @er3-,@(0xffff9abc:16,er1) ;01066d3cc1209abc + cmp.l @er3-,@(0x9abcdef0:32,er1) ;01066d3cc9209abcdef0 + cmp.l @er3-,@(0xffff9abc:16,r2l.b) ;01066d3cd2209abc + cmp.l @er3-,@(0xffff9abc:16,r2.w) ;01066d3ce2209abc + cmp.l @er3-,@(0xffff9abc:16,er2.l) ;01066d3cf2209abc + cmp.l @er3-,@(0x9abcdef0:32,r2l.b) ;01066d3cda209abcdef0 + cmp.l @er3-,@(0x9abcdef0:32,r2.w) ;01066d3cea209abcdef0 + cmp.l @er3-,@(0x9abcdef0:32,er2.l) ;01066d3cfa209abcdef0 + cmp.l @er3-,@0xffff9abc:16 ;01066d3c40209abc + cmp.l @er3-,@0x9abcdef0:32 ;01066d3c48209abcdef0 + + cmp.l @+er3,@er1 ;01056d3c0120 + cmp.l @+er3,@(0xc:2,er1) ;01056d3c3120 + cmp.l @+er3,@-er1 ;01056d3cb120 + cmp.l @+er3,@er1+ ;01056d3c8120 + cmp.l @+er3,@er1- ;01056d3ca120 + cmp.l @+er3,@+er1 ;01056d3c9120 + cmp.l @+er3,@(0xffff9abc:16,er1) ;01056d3cc1209abc + cmp.l @+er3,@(0x9abcdef0:32,er1) ;01056d3cc9209abcdef0 + cmp.l @+er3,@(0xffff9abc:16,r2l.b) ;01056d3cd2209abc + cmp.l @+er3,@(0xffff9abc:16,r2.w) ;01056d3ce2209abc + cmp.l @+er3,@(0xffff9abc:16,er2.l) ;01056d3cf2209abc + cmp.l @+er3,@(0x9abcdef0:32,r2l.b) ;01056d3cda209abcdef0 + cmp.l @+er3,@(0x9abcdef0:32,r2.w) ;01056d3cea209abcdef0 + cmp.l @+er3,@(0x9abcdef0:32,er2.l) ;01056d3cfa209abcdef0 + cmp.l @+er3,@0xffff9abc:16 ;01056d3c40209abc + cmp.l @+er3,@0x9abcdef0:32 ;01056d3c48209abcdef0 + + cmp.l @(0x1234:16,er3),@er1 ;01046f3c12340120 + cmp.l @(0x1234:16,er3),@(0xc:2,er1) ;01046f3c12343120 + cmp.l @(0x1234:16,er3),@-er1 ;01046f3c1234b120 + cmp.l @(0x1234:16,er3),@er1+ ;01046f3c12348120 + cmp.l @(0x1234:16,er3),@er1- ;01046f3c1234a120 + cmp.l @(0x1234:16,er3),@+er1 ;01046f3c12349120 + cmp.l @(0x1234:16,er3),@(0xffff9abc:16,er1) ;01046f3c1234c1209abc + cmp.l @(0x1234:16,er3),@(0x9abcdef0:32,er1) ;01046f3c1234c9209abcdef0 + cmp.l @(0x1234:16,er3),@(0xffff9abc:16,r2l.b) ;01046f3c1234d2209abc + cmp.l @(0x1234:16,er3),@(0xffff9abc:16,r2.w) ;01046f3c1234e2209abc + cmp.l @(0x1234:16,er3),@(0xffff9abc:16,er2.l) ;01046f3c1234f2209abc + cmp.l @(0x1234:16,er3),@(0x9abcdef0:32,r2l.b) ;01046f3c1234da209abcdef0 + cmp.l @(0x1234:16,er3),@(0x9abcdef0:32,r2.w) ;01046f3c1234ea209abcdef0 + cmp.l @(0x1234:16,er3),@(0x9abcdef0:32,er2.l) ;01046f3c1234fa209abcdef0 + cmp.l @(0x1234:16,er3),@0xffff9abc:16 ;01046f3c123440209abc + cmp.l @(0x1234:16,er3),@0x9abcdef0:32 ;01046f3c123448209abcdef0 + + cmp.l @(0x12345678:32,er3),@er1 ;78b46b2c123456780120 + cmp.l @(0x12345678:32,er3),@(0xc:2,er1) ;78b46b2c123456783120 + cmp.l @(0x12345678:32,er3),@-er1 ;78b46b2c12345678b120 + cmp.l @(0x12345678:32,er3),@er1+ ;78b46b2c123456788120 + cmp.l @(0x12345678:32,er3),@er1- ;78b46b2c12345678a120 + cmp.l @(0x12345678:32,er3),@+er1 ;78b46b2c123456789120 + cmp.l @(0x12345678:32,er3),@(0xffff9abc:16,er1) ;78b46b2c12345678c1209abc + cmp.l @(0x12345678:32,er3),@(0x9abcdef0:32,er1) ;78b46b2c12345678c9209abcdef0 + cmp.l @(0x12345678:32,er3),@(0xffff9abc:16,r2l.b) ;78b46b2c12345678d2209abc + cmp.l @(0x12345678:32,er3),@(0xffff9abc:16,r2.w) ;78b46b2c12345678e2209abc + cmp.l @(0x12345678:32,er3),@(0xffff9abc:16,er2.l) ;78b46b2c12345678f2209abc + cmp.l @(0x12345678:32,er3),@(0x9abcdef0:32,r2l.b) ;78b46b2c12345678da209abcdef0 + cmp.l @(0x12345678:32,er3),@(0x9abcdef0:32,r2.w) ;78b46b2c12345678ea209abcdef0 + cmp.l @(0x12345678:32,er3),@(0x9abcdef0:32,er2.l) ;78b46b2c12345678fa209abcdef0 + cmp.l @(0x12345678:32,er3),@0xffff9abc:16 ;78b46b2c1234567840209abc + cmp.l @(0x12345678:32,er3),@0x9abcdef0:32 ;78b46b2c1234567848209abcdef0 + + cmp.l @(0x1234:16,r3l.b),@er1 ;01056f3c12340120 + cmp.l @(0x1234:16,r3l.b),@(0xc:2,er1) ;01056f3c12343120 + cmp.l @(0x1234:16,r3l.b),@-er1 ;01056f3c1234b120 + cmp.l @(0x1234:16,r3l.b),@er1+ ;01056f3c12348120 + cmp.l @(0x1234:16,r3l.b),@er1- ;01056f3c1234a120 + cmp.l @(0x1234:16,r3l.b),@+er1 ;01056f3c12349120 + cmp.l @(0x1234:16,r3l.b),@(0xffff9abc:16,er1) ;01056f3c1234c1209abc + cmp.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1) ;01056f3c1234c9209abcdef0 + cmp.l @(0x1234:16,r3l.b),@(0xffff9abc:16,r2l.b) ;01056f3c1234d2209abc + cmp.l @(0x1234:16,r3l.b),@(0xffff9abc:16,r2.w) ;01056f3c1234e2209abc + cmp.l @(0x1234:16,r3l.b),@(0xffff9abc:16,er2.l) ;01056f3c1234f2209abc + cmp.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2l.b) ;01056f3c1234da209abcdef0 + cmp.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2.w) ;01056f3c1234ea209abcdef0 + cmp.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,er2.l) ;01056f3c1234fa209abcdef0 + cmp.l @(0x1234:16,r3l.b),@0xffff9abc:16 ;01056f3c123440209abc + cmp.l @(0x1234:16,r3l.b),@0x9abcdef0:32 ;01056f3c123448209abcdef0 + + cmp.l @(0x1234:16,r3.w),@er1 ;01066f3c12340120 + cmp.l @(0x1234:16,r3.w),@(0xc:2,er1) ;01066f3c12343120 + cmp.l @(0x1234:16,r3.w),@-er1 ;01066f3c1234b120 + cmp.l @(0x1234:16,r3.w),@er1+ ;01066f3c12348120 + cmp.l @(0x1234:16,r3.w),@er1- ;01066f3c1234a120 + cmp.l @(0x1234:16,r3.w),@+er1 ;01066f3c12349120 + cmp.l @(0x1234:16,r3.w),@(0xffff9abc:16,er1) ;01066f3c1234c1209abc + cmp.l @(0x1234:16,r3.w),@(0x9abcdef0:32,er1) ;01066f3c1234c9209abcdef0 + cmp.l @(0x1234:16,r3.w),@(0xffff9abc:16,r2l.b) ;01066f3c1234d2209abc + cmp.l @(0x1234:16,r3.w),@(0xffff9abc:16,r2.w) ;01066f3c1234e2209abc + cmp.l @(0x1234:16,r3.w),@(0xffff9abc:16,er2.l) ;01066f3c1234f2209abc + cmp.l @(0x1234:16,r3.w),@(0x9abcdef0:32,r2l.b) ;01066f3c1234da209abcdef0 + cmp.l @(0x1234:16,r3.w),@(0x9abcdef0:32,r2.w) ;01066f3c1234ea209abcdef0 + cmp.l @(0x1234:16,r3.w),@(0x9abcdef0:32,er2.l) ;01066f3c1234fa209abcdef0 + cmp.l @(0x1234:16,r3.w),@0xffff9abc:16 ;01066f3c123440209abc + cmp.l @(0x1234:16,r3.w),@0x9abcdef0:32 ;01066f3c123448209abcdef0 + + cmp.l @(0x1234:16,er3.l),@er1 ;01076f3c12340120 + cmp.l @(0x1234:16,er3.l),@(0xc:2,er1) ;01076f3c12343120 + cmp.l @(0x1234:16,er3.l),@-er1 ;01076f3c1234b120 + cmp.l @(0x1234:16,er3.l),@er1+ ;01076f3c12348120 + cmp.l @(0x1234:16,er3.l),@er1- ;01076f3c1234a120 + cmp.l @(0x1234:16,er3.l),@+er1 ;01076f3c12349120 + cmp.l @(0x1234:16,er3.l),@(0xffff9abc:16,er1) ;01076f3c1234c1209abc + cmp.l @(0x1234:16,er3.l),@(0x9abcdef0:32,er1) ;01076f3c1234c9209abcdef0 + cmp.l @(0x1234:16,er3.l),@(0xffff9abc:16,r2l.b) ;01076f3c1234d2209abc + cmp.l @(0x1234:16,er3.l),@(0xffff9abc:16,r2.w) ;01076f3c1234e2209abc + cmp.l @(0x1234:16,er3.l),@(0xffff9abc:16,er2.l) ;01076f3c1234f2209abc + cmp.l @(0x1234:16,er3.l),@(0x9abcdef0:32,r2l.b) ;01076f3c1234da209abcdef0 + cmp.l @(0x1234:16,er3.l),@(0x9abcdef0:32,r2.w) ;01076f3c1234ea209abcdef0 + cmp.l @(0x1234:16,er3.l),@(0x9abcdef0:32,er2.l) ;01076f3c1234fa209abcdef0 + cmp.l @(0x1234:16,er3.l),@0xffff9abc:16 ;01076f3c123440209abc + cmp.l @(0x1234:16,er3.l),@0x9abcdef0:32 ;01076f3c123448209abcdef0 + + cmp.l @(0x12345678:32,r3l.b),@er1 ;78b56b2c123456780120 + cmp.l @(0x12345678:32,r3l.b),@(0xc:2,er1) ;78b56b2c123456783120 + cmp.l @(0x12345678:32,r3l.b),@-er1 ;78b56b2c12345678b120 + cmp.l @(0x12345678:32,r3l.b),@er1+ ;78b56b2c123456788120 + cmp.l @(0x12345678:32,r3l.b),@er1- ;78b56b2c12345678a120 + cmp.l @(0x12345678:32,r3l.b),@+er1 ;78b56b2c123456789120 + cmp.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,er1) ;78b56b2c12345678c1209abc + cmp.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1) ;78b56b2c12345678c9209abcdef0 + cmp.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2l.b) ;78b56b2c12345678d2209abc + cmp.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2.w) ;78b56b2c12345678e2209abc + cmp.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,er2.l) ;78b56b2c12345678f2209abc + cmp.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2l.b) ;78b56b2c12345678da209abcdef0 + cmp.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2.w) ;78b56b2c12345678ea209abcdef0 + cmp.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er2.l) ;78b56b2c12345678fa209abcdef0 + cmp.l @(0x12345678:32,r3l.b),@0xffff9abc:16 ;78b56b2c1234567840209abc + cmp.l @(0x12345678:32,r3l.b),@0x9abcdef0:32 ;78b56b2c1234567848209abcdef0 + + cmp.l @(0x12345678:32,r3.w),@er1 ;78b66b2c123456780120 + cmp.l @(0x12345678:32,r3.w),@(0xc:2,er1) ;78b66b2c123456783120 + cmp.l @(0x12345678:32,r3.w),@-er1 ;78b66b2c12345678b120 + cmp.l @(0x12345678:32,r3.w),@er1+ ;78b66b2c123456788120 + cmp.l @(0x12345678:32,r3.w),@er1- ;78b66b2c12345678a120 + cmp.l @(0x12345678:32,r3.w),@+er1 ;78b66b2c123456789120 + cmp.l @(0x12345678:32,r3.w),@(0xffff9abc:16,er1) ;78b66b2c12345678c1209abc + cmp.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1) ;78b66b2c12345678c9209abcdef0 + cmp.l @(0x12345678:32,r3.w),@(0xffff9abc:16,r2l.b) ;78b66b2c12345678d2209abc + cmp.l @(0x12345678:32,r3.w),@(0xffff9abc:16,r2.w) ;78b66b2c12345678e2209abc + cmp.l @(0x12345678:32,r3.w),@(0xffff9abc:16,er2.l) ;78b66b2c12345678f2209abc + cmp.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2l.b) ;78b66b2c12345678da209abcdef0 + cmp.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2.w) ;78b66b2c12345678ea209abcdef0 + cmp.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,er2.l) ;78b66b2c12345678fa209abcdef0 + cmp.l @(0x12345678:32,r3.w),@0xffff9abc:16 ;78b66b2c1234567840209abc + cmp.l @(0x12345678:32,r3.w),@0x9abcdef0:32 ;78b66b2c1234567848209abcdef0 + + cmp.l @(0x12345678:32,er3.l),@er1 ;78b76b2c123456780120 + cmp.l @(0x12345678:32,er3.l),@(0xc:2,er1) ;78b76b2c123456783120 + cmp.l @(0x12345678:32,er3.l),@-er1 ;78b76b2c12345678b120 + cmp.l @(0x12345678:32,er3.l),@er1+ ;78b76b2c123456788120 + cmp.l @(0x12345678:32,er3.l),@er1- ;78b76b2c12345678a120 + cmp.l @(0x12345678:32,er3.l),@+er1 ;78b76b2c123456789120 + cmp.l @(0x12345678:32,er3.l),@(0xffff9abc:16,er1) ;78b76b2c12345678c1209abc + cmp.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1) ;78b76b2c12345678c9209abcdef0 + cmp.l @(0x12345678:32,er3.l),@(0xffff9abc:16,r2l.b) ;78b76b2c12345678d2209abc + cmp.l @(0x12345678:32,er3.l),@(0xffff9abc:16,r2.w) ;78b76b2c12345678e2209abc + cmp.l @(0x12345678:32,er3.l),@(0xffff9abc:16,er2.l) ;78b76b2c12345678f2209abc + cmp.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2l.b) ;78b76b2c12345678da209abcdef0 + cmp.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2.w) ;78b76b2c12345678ea209abcdef0 + cmp.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,er2.l) ;78b76b2c12345678fa209abcdef0 + cmp.l @(0x12345678:32,er3.l),@0xffff9abc:16 ;78b76b2c1234567840209abc + cmp.l @(0x12345678:32,er3.l),@0x9abcdef0:32 ;78b76b2c1234567848209abcdef0 + + cmp.l @0x1234:16,@er1 ;01046b0c12340120 + cmp.l @0x1234:16,@(0xc:2,er1) ;01046b0c12343120 + cmp.l @0x1234:16,@-er1 ;01046b0c1234b120 + cmp.l @0x1234:16,@er1+ ;01046b0c12348120 + cmp.l @0x1234:16,@er1- ;01046b0c1234a120 + cmp.l @0x1234:16,@+er1 ;01046b0c12349120 + cmp.l @0x1234:16,@(0xffff9abc:16,er1) ;01046b0c1234c1209abc + cmp.l @0x1234:16,@(0x9abcdef0:32,er1) ;01046b0c1234c9209abcdef0 + cmp.l @0x1234:16,@(0xffff9abc:16,r2l.b) ;01046b0c1234d2209abc + cmp.l @0x1234:16,@(0xffff9abc:16,r2.w) ;01046b0c1234e2209abc + cmp.l @0x1234:16,@(0xffff9abc:16,er2.l) ;01046b0c1234f2209abc + cmp.l @0x1234:16,@(0x9abcdef0:32,r2l.b) ;01046b0c1234da209abcdef0 + cmp.l @0x1234:16,@(0x9abcdef0:32,r2.w) ;01046b0c1234ea209abcdef0 + cmp.l @0x1234:16,@(0x9abcdef0:32,er2.l) ;01046b0c1234fa209abcdef0 + cmp.l @0x1234:16,@0xffff9abc:16 ;01046b0c123440209abc + cmp.l @0x1234:16,@0x9abcdef0:32 ;01046b0c123448209abcdef0 + + cmp.l @0x12345678:32,@er1 ;01046b2c123456780120 + cmp.l @0x12345678:32,@(0xc:2,er1) ;01046b2c123456783120 + cmp.l @0x12345678:32,@-er1 ;01046b2c12345678b120 + cmp.l @0x12345678:32,@er1+ ;01046b2c123456788120 + cmp.l @0x12345678:32,@er1- ;01046b2c12345678a120 + cmp.l @0x12345678:32,@+er1 ;01046b2c123456789120 + cmp.l @0x12345678:32,@(0xffff9abc:16,er1) ;01046b2c12345678c1209abc + cmp.l @0x12345678:32,@(0x9abcdef0:32,er1) ;01046b2c12345678c9209abcdef0 + cmp.l @0x12345678:32,@(0xffff9abc:16,r2l.b) ;01046b2c12345678d2209abc + cmp.l @0x12345678:32,@(0xffff9abc:16,r2.w) ;01046b2c12345678e2209abc + cmp.l @0x12345678:32,@(0xffff9abc:16,er2.l) ;01046b2c12345678f2209abc + cmp.l @0x12345678:32,@(0x9abcdef0:32,r2l.b) ;01046b2c12345678da209abcdef0 + cmp.l @0x12345678:32,@(0x9abcdef0:32,r2.w) ;01046b2c12345678ea209abcdef0 + cmp.l @0x12345678:32,@(0x9abcdef0:32,er2.l) ;01046b2c12345678fa209abcdef0 + cmp.l @0x12345678:32,@0xffff9abc:16 ;01046b2c1234567840209abc + cmp.l @0x12345678:32,@0x9abcdef0:32 ;01046b2c1234567848209abcdef0 + + .end diff --git a/gdb/testsuite/gdb.disasm/t06_ari2.exp b/gdb/testsuite/gdb.disasm/t06_ari2.exp new file mode 100644 index 0000000..99ad366 --- /dev/null +++ b/gdb/testsuite/gdb.disasm/t06_ari2.exp @@ -0,0 +1,282 @@ +# Copyright (C) 2003 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# Please email any bugs, comments, and/or additions to this file to: +# bug-gdb@prep.ai.mit.edu + +# This file was written by Michael Snyder (msnyder@redhat.com) + +if $tracelevel then { + strace $tracelevel +} + +if ![istarget "h8300*-*-*"] { + verbose "Tests ignored for all but h8300s based targets." + return +} + +set prms_id 0 +set bug_id 0 + +set testfile "t06_ari2" +set srcfile ${srcdir}/${subdir}/${testfile}.s +set objfile ${objdir}/${subdir}/${testfile}.o +set binfile ${objdir}/${subdir}/${testfile}.x + +set asm-flags ""; +set link-flags "-m h8300sxelf"; + + +if {[target_assemble $srcfile $objfile "${asm-flags}"] != ""} then { + gdb_suppress_entire_file "Testcase assembly failed, so all tests in this file will automatically fail." +} + +if {[target_link $objfile $binfile "${link-flags}"] != ""} then { + gdb_suppress_entire_file "Testcase link failed, so all tests in this file will automatically fail." +} + +gdb_start +gdb_reinitialize_dir $srcdir/$subdir +gdb_load $binfile + +gdb_test "x /i _start" "addx(.b|)\t#0x12(:8|),r1h" \ + "addx.b #0x12:8,r1h" +gdb_test "x" "addx(.b|)\t#0x12(:8|),@er1" \ + "addx.b #0x12:8,@er1" +gdb_test "x" "addx(.b|)\t#0x12(:8|),@er1-" \ + "addx.b #0x12:8,@er1-" +gdb_test "x" "addx(.b|)\tr3h,r1h" \ + "addx.b r3h,r1h" +gdb_test "x" "addx(.b|)\tr3h,@er1" \ + "addx.b r3h,@er1" +gdb_test "x" "addx(.b|)\tr3h,@er1-" \ + "addx.b r3h,@er1-" +gdb_test "x" "addx(.b|)\t@er3,r1h" \ + "addx.b @er3,r1h" +gdb_test "x" "addx(.b|)\t@er3,@er1" \ + "addx.b @er3,@er1" +gdb_test "x" "addx(.b|)\t@er3-,r1h" \ + "addx.b @er3-,r1h" +gdb_test "x" "addx(.b|)\t@er3-,@er1-" \ + "addx.b @er3-,@er1-" +gdb_test "x" "addx.w\t#0x1234(:16|),r1" \ + "addx.w #0x1234:16,r1" +gdb_test "x" "addx.w\t#0x1234(:16|),@er1" \ + "addx.w #0x1234:16,@er1" +gdb_test "x" "addx.w\t#0x1234(:16|),@er1-" \ + "addx.w #0x1234:16,@er1-" +gdb_test "x" "addx.w\tr3,r1" \ + "addx.w r3,r1" +gdb_test "x" "addx.w\tr3,@er1" \ + "addx.w r3,@er1" +gdb_test "x" "addx.w\tr3,@er1-" \ + "addx.w r3,@er1-" +gdb_test "x" "addx.w\t@er3,r1" \ + "addx.w @er3,r1" +gdb_test "x" "addx.w\t@er3,@er1" \ + "addx.w @er3,@er1" +gdb_test "x" "addx.w\t@er3-,r1" \ + "addx.w @er3-,r1" +gdb_test "x" "addx.w\t@er3-,@er1-" \ + "addx.w @er3-,@er1-" +gdb_test "x" "addx.l\t#0x12345678(:32|),er1" \ + "addx.l #0x12345678:32,er1" +gdb_test "x" "addx.l\t#0x12345678(:32|),@er1" \ + "addx.l #0x12345678:32,@er1" +gdb_test "x" "addx.l\t#0x12345678(:32|),@er1-" \ + "addx.l #0x12345678:32,@er1-" +gdb_test "x" "addx.l\ter3,er1" \ + "addx.l er3,er1" +gdb_test "x" "addx.l\ter3,@er1" \ + "addx.l er3,@er1" +gdb_test "x" "addx.l\ter3,@er1-" \ + "addx.l er3,@er1-" +gdb_test "x" "addx.l\t@er3,er1" \ + "addx.l @er3,er1" +gdb_test "x" "addx.l\t@er3,@er1" \ + "addx.l @er3,@er1" +gdb_test "x" "addx.l\t@er3-,er1" \ + "addx.l @er3-,er1" +gdb_test "x" "addx.l\t@er3-,@er1-" \ + "addx.l @er3-,@er1-" +gdb_test "x" "subx(.b|)\t#0x12(:8|),r1h" \ + "subx.b #0x12:8,r1h" +gdb_test "x" "subx(.b|)\t#0x12(:8|),@er1" \ + "subx.b #0x12:8,@er1" +gdb_test "x" "subx(.b|)\t#0x12(:8|),@er1-" \ + "subx.b #0x12:8,@er1-" +gdb_test "x" "subx(.b|)\tr3h,r1h" \ + "subx.b r3h,r1h" +gdb_test "x" "subx(.b|)\tr3h,@er1" \ + "subx.b r3h,@er1" +gdb_test "x" "subx(.b|)\tr3h,@er1-" \ + "subx.b r3h,@er1-" +gdb_test "x" "subx(.b|)\t@er3,r1h" \ + "subx.b @er3,r1h" +gdb_test "x" "subx(.b|)\t@er3,@er1" \ + "subx.b @er3,@er1" +gdb_test "x" "subx(.b|)\t@er3-,r1h" \ + "subx.b @er3-,r1h" +gdb_test "x" "subx(.b|)\t@er3-,@er1-" \ + "subx.b @er3-,@er1-" +gdb_test "x" "subx.w\t#0x1234(:16|),r1" \ + "subx.w #0x1234:16,r1" +gdb_test "x" "subx.w\t#0x1234(:16|),@er1" \ + "subx.w #0x1234:16,@er1" +gdb_test "x" "subx.w\t#0x1234(:16|),@er1-" \ + "subx.w #0x1234:16,@er1-" +gdb_test "x" "subx.w\tr3,r1" \ + "subx.w r3,r1" +gdb_test "x" "subx.w\tr3,@er1" \ + "subx.w r3,@er1" +gdb_test "x" "subx.w\tr3,@er1-" \ + "subx.w r3,@er1-" +gdb_test "x" "subx.w\t@er3,r1" \ + "subx.w @er3,r1" +gdb_test "x" "subx.w\t@er3,@er1" \ + "subx.w @er3,@er1" +gdb_test "x" "subx.w\t@er3-,r1" \ + "subx.w @er3-,r1" +gdb_test "x" "subx.w\t@er3-,@er1-" \ + "subx.w @er3-,@er1-" +gdb_test "x" "subx.l\t#0x12345678(:32|),er1" \ + "subx.l #0x12345678:32,er1" +gdb_test "x" "subx.l\t#0x12345678(:32|),@er1" \ + "subx.l #0x12345678:32,@er1" +gdb_test "x" "subx.l\t#0x12345678(:32|),@er1-" \ + "subx.l #0x12345678:32,@er1-" +gdb_test "x" "subx.l\ter3,er1" \ + "subx.l er3,er1" +gdb_test "x" "subx.l\ter3,@er1" \ + "subx.l er3,@er1" +gdb_test "x" "subx.l\ter3,@er1-" \ + "subx.l er3,@er1-" +gdb_test "x" "subx.l\t@er3,er1" \ + "subx.l @er3,er1" +gdb_test "x" "subx.l\t@er3,@er1" \ + "subx.l @er3,@er1" +gdb_test "x" "subx.l\t@er3-,er1" \ + "subx.l @er3-,er1" +gdb_test "x" "subx.l\t@er3-,@er1-" \ + "subx.l @er3-,@er1-" +gdb_test "x" "inc(.b|)\tr1h" \ + "inc.b r1h" +gdb_test "x" "inc(.w|)\t#1,r1" \ + "inc.w #1,r1" +gdb_test "x" "inc(.w|)\t#2,r1" \ + "inc.w #2,r1" +gdb_test "x" "inc(.l|)\t#1,er1" \ + "inc.l #1,er1" +gdb_test "x" "inc(.l|)\t#2,er1" \ + "inc.l #2,er1" +gdb_test "x" "dec(.b|)\tr1h" \ + "dec.b r1h" +gdb_test "x" "dec(.w|)\t#1,r1" \ + "dec.w #1,r1" +gdb_test "x" "dec(.w|)\t#2,r1" \ + "dec.w #2,r1" +gdb_test "x" "dec(.l|)\t#1,er1" \ + "dec.l #1,er1" +gdb_test "x" "dec(.l|)\t#2,er1" \ + "dec.l #2,er1" +gdb_test "x" "adds(.l|)\t#1,er1" \ + "adds.l #1,er1" +gdb_test "x" "adds(.l|)\t#2,er1" \ + "adds.l #2,er1" +gdb_test "x" "adds(.l|)\t#4,er1" \ + "adds.l #4,er1" +gdb_test "x" "subs(.l|)\t#1,er1" \ + "subs.l #1,er1" +gdb_test "x" "subs(.l|)\t#2,er1" \ + "subs.l #2,er1" +gdb_test "x" "subs(.l|)\t#4,er1" \ + "subs.l #4,er1" +gdb_test "x" "daa(.b|)\tr1h" \ + "daa.b r1h" +gdb_test "x" "das(.b|)\tr1h" \ + "das.b r1h" +gdb_test "x" "mulxu.b\t#0xf(:4|),r1" \ + "mulxu.b #0xf:4,r1" +gdb_test "x" "mulxu.b\tr3h,r1" \ + "mulxu.b r3h,r1" +gdb_test "x" "mulxu.w\t#0xf(:4|),er1" \ + "mulxu.w #0xf:4,er1" +gdb_test "x" "mulxu.w\tr3,er1" \ + "mulxu.w r3,er1" +gdb_test "x" "divxu.b\t#0xf(:4|),r1" \ + "divxu.b #0xf:4,r1" +gdb_test "x" "divxu.b\tr3h,r1" \ + "divxu.b r3h,r1" +gdb_test "x" "divxu.w\t#0xf(:4|),er1" \ + "divxu.w #0xf:4,er1" +gdb_test "x" "divxu.w\tr3,er1" \ + "divxu.w r3,er1" +gdb_test "x" "mulxs.b\t#0xf(:4|),r1" \ + "mulxs.b #0xf:4,r1" +gdb_test "x" "mulxs.b\tr3h,r1" \ + "mulxs.b r3h,r1" +gdb_test "x" "mulxs.w\t#0xf(:4|),er1" \ + "mulxs.w #0xf:4,er1" +gdb_test "x" "mulxs.w\tr3,er1" \ + "mulxs.w r3,er1" +gdb_test "x" "divxs.b\t#0xf(:4|),r1" \ + "divxs.b #0xf:4,r1" +gdb_test "x" "divxs.b\tr3h,r1" \ + "divxs.b r3h,r1" +gdb_test "x" "divxs.w\t#0xf(:4|),er1" \ + "divxs.w #0xf:4,er1" +gdb_test "x" "divxs.w\tr3,er1" \ + "divxs.w r3,er1" +gdb_test "x" "mulu.w\t#0xf(:4|),r1" \ + "mulu.w #0xf:4,r1" +gdb_test "x" "mulu.w\tr3,r1" \ + "mulu.w r3,r1" +gdb_test "x" "mulu.l\t#0xf(:4|),er1" \ + "mulu.l #0xf:4,er1" +gdb_test "x" "mulu.l\ter3,er1" \ + "mulu.l er3,er1" +gdb_test "x" "mulu/u.l\t#0xf(:4|),er1" \ + "mulu/u.l #0xf:4,er1" +gdb_test "x" "mulu/u.l\ter3,er1" \ + "mulu/u.l er3,er1" +gdb_test "x" "muls.w\t#0xf(:4|),r1" \ + "muls.w #0xf:4,r1" +gdb_test "x" "muls.w\tr3,r1" \ + "muls.w r3,r1" +gdb_test "x" "muls.l\t#0xf(:4|),er1" \ + "muls.l #0xf:4,er1" +gdb_test "x" "muls.l\ter3,er1" \ + "muls.l er3,er1" +gdb_test "x" "muls/u.l\t#0xf(:4|),er1" \ + "muls/u.l #0xf:4,er1" +gdb_test "x" "muls/u.l\ter3,er1" \ + "muls/u.l er3,er1" +gdb_test "x" "divu.w\t#0xf(:4|),r1" \ + "divu.w #0xf:4,r1" +gdb_test "x" "divu.w\tr3,r1" \ + "divu.w r3,r1" +gdb_test "x" "divu.l\t#0xf(:4|),er1" \ + "divu.l #0xf:4,er1" +gdb_test "x" "divu.l\ter3,er1" \ + "divu.l er3,er1" +gdb_test "x" "divs.w\t#0xf(:4|),r1" \ + "divs.w #0xf:4,r1" +gdb_test "x" "divs.w\tr3,r1" \ + "divs.w r3,r1" +gdb_test "x" "divs.l\t#0xf(:4|),er1" \ + "divs.l #0xf:4,er1" +gdb_test "x" "divs.l\ter3,er1" \ + "divs.l er3,er1" diff --git a/gdb/testsuite/gdb.disasm/t06_ari2.s b/gdb/testsuite/gdb.disasm/t06_ari2.s new file mode 100644 index 0000000..2c7c99f --- /dev/null +++ b/gdb/testsuite/gdb.disasm/t06_ari2.s @@ -0,0 +1,188 @@ +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;arith_2 +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + .h8300sx + .text + .global _start +_start: + addx.b #0x12:8,r1h ;9112 + addx.b #0x12:8,@er1 ;7d109012 + addx.b #0x12:8,@er1- ;01766c189012 + + addx.b r3h,r1h ;0e31 + addx.b r3h,@er1 ;7d100e30 + addx.b r3h,@er1- ;01766c180e30 + + addx.b @er3,r1h ;7c300e01 + addx.b @er3,@er1 ;0174683d0110 + + addx.b @er3-,r1h ;01766c300e01 + addx.b @er3-,@er1- ;01766c3da110 + + addx.w #0x1234:16,r1 ;015179111234 + addx.w #0x1234:16,@er1 ;7d9179101234 + addx.w #0x1234:16,@er1- ;01566d1979101234 + + addx.w r3,r1 ;01510931 + addx.w r3,@er1 ;7d910930 + addx.w r3,@er1- ;01566d190930 + + addx.w @er3,r1 ;7cb10901 + addx.w @er3,@er1 ;0154693d0110 + + addx.w @er3-,r1 ;01566d310901 + addx.w @er3-,@er1- ;01566d3da110 + + addx.l #0x12345678:32,er1 ;01017a1112345678 + addx.l #0x12345678:32,@er1 ;010469197a1012345678 + addx.l #0x12345678:32,@er1- ;01066d197a1012345678 + + addx.l er3,er1 ;01010ab1 + addx.l er3,@er1 ;010469190ab0 + addx.l er3,@er1- ;01066d190ab0 + + addx.l @er3,er1 ;010469310a81 + addx.l @er3,@er1 ;0104693d0110 + + addx.l @er3-,er1 ;01066d310a81 + addx.l @er3-,@er1- ;01066d3da110 + + subx.b #0x12:8,r1h ;b112 + subx.b #0x12:8,@er1 ;7d10b012 + subx.b #0x12:8,@er1- ;01766c18b012 + + subx.b r3h,r1h ;1e31 + subx.b r3h,@er1 ;7d101e30 + subx.b r3h,@er1- ;01766c181e30 + + subx.b @er3,r1h ;7c301e01 + subx.b @er3,@er1 ;0174683d0130 + + subx.b @er3-,r1h ;01766c301e01 + subx.b @er3-,@er1- ;01766c3da130 + + subx.w #0x1234:16,r1 ;015179311234 + subx.w #0x1234:16,@er1 ;7d9179301234 + subx.w #0x1234:16,@er1- ;01566d1979301234 + + subx.w r3,r1 ;01511931 + subx.w r3,@er1 ;7d911930 + subx.w r3,@er1- ;01566d191930 + + subx.w @er3,r1 ;7cb11901 + subx.w @er3,@er1 ;0154693d0130 + + subx.w @er3-,r1 ;01566d311901 + subx.w @er3-,@er1- ;01566d3da130 + + subx.l #0x12345678:32,er1 ;01017a3112345678 + subx.l #0x12345678:32,@er1 ;010469197a3012345678 + subx.l #0x12345678:32,@er1- ;01066d197a3012345678 + + subx.l er3,er1 ;01011ab1 + subx.l er3,@er1 ;010469191ab0 + subx.l er3,@er1- ;01066d191ab0 + + subx.l @er3,er1 ;010469311a81 + subx.l @er3,@er1 ;0104693d0130 + + subx.l @er3-,er1 ;01066d311a81 + subx.l @er3-,@er1- ;01066d3da130 + + inc.b r1h ;0a01 + inc.w #1,r1 ;0b51 + inc.w #2,r1 ;0bd1 + inc.l #1,er1 ;0b71 + inc.l #2,er1 ;0bf1 + + dec.b r1h ;1a01 + dec.w #1,r1 ;1b51 + dec.w #2,r1 ;1bd1 + dec.l #1,er1 ;1b71 + dec.l #2,er1 ;1bf1 + + adds.l #1,er1 ;0b01 + adds.l #2,er1 ;0b81 + adds.l #4,er1 ;0b91 + + subs.l #1,er1 ;1b01 + subs.l #2,er1 ;1b81 + subs.l #4,er1 ;1b91 + + daa.b r1h ;0f01 + + das.b r1h ;1f01 + + mulxu.b #0xf:4,r1 ;01cc50f1 + + mulxu.b r3h,r1 ;5031 + + mulxu.w #0xf:4,er1 ;01cc52f1 + + mulxu.w r3,er1 ;5231 + + divxu.b #0xf:4,r1 ;01dc51f1 + + divxu.b r3h,r1 ;5131 + + divxu.w #0xf:4,er1 ;01dc53f1 + + divxu.w r3,er1 ;5331 + + mulxs.b #0xf:4,r1 ;01c450f1 + + mulxs.b r3h,r1 ;01c05031 + + mulxs.w #0xf:4,er1 ;01c452f1 + + mulxs.w r3,er1 ;01c05231 + + divxs.b #0xf:4,r1 ;01d451f1 + + divxs.b r3h,r1 ;01d05131 + + divxs.w #0xf:4,er1 ;01d453f1 + + divxs.w r3,er1 ;01d05331 + + mulu.w #0xf:4,r1 ;01ce50f1 + + mulu.w r3,r1 ;01ca5031 + + mulu.l #0xf:4,er1 ;01ce52f1 + + mulu.l er3,er1 ;01ca5231 + + mulu/u.l #0xf:4,er1 ;01cf52f1 + + mulu/u.l er3,er1 ;01cb5231 + + muls.w #0xf:4,r1 ;01c650f1 + + muls.w r3,r1 ;01c25031 + + muls.l #0xf:4,er1 ;01c652f1 + + muls.l er3,er1 ;01c25231 + + muls/u.l #0xf:4,er1 ;01c752f1 + + muls/u.l er3,er1 ;01c35231 + + divu.w #0xf:4,r1 ;01de51f1 + + divu.w r3,r1 ;01da5131 + + divu.l #0xf:4,er1 ;01de53f1 + + divu.l er3,er1 ;01da5331 + + divs.w #0xf:4,r1 ;01d651f1 + + divs.w r3,r1 ;01d25131 + + divs.l #0xf:4,er1 ;01d653f1 + + divs.l er3,er1 ;01d25331 + + .end diff --git a/gdb/testsuite/gdb.disasm/t07_ari3.exp b/gdb/testsuite/gdb.disasm/t07_ari3.exp new file mode 100644 index 0000000..7084a95 --- /dev/null +++ b/gdb/testsuite/gdb.disasm/t07_ari3.exp @@ -0,0 +1,364 @@ +# Copyright (C) 2003 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# Please email any bugs, comments, and/or additions to this file to: +# bug-gdb@prep.ai.mit.edu + +# This file was written by Michael Snyder (msnyder@redhat.com) + +if $tracelevel then { + strace $tracelevel +} + +if ![istarget "h8300*-*-*"] { + verbose "Tests ignored for all but h8300s based targets." + return +} + +set prms_id 0 +set bug_id 0 + +set testfile "t07_ari3" +set srcfile ${srcdir}/${subdir}/${testfile}.s +set objfile ${objdir}/${subdir}/${testfile}.o +set binfile ${objdir}/${subdir}/${testfile}.x + +set asm-flags ""; +set link-flags "-m h8300sxelf"; + + +if {[target_assemble $srcfile $objfile "${asm-flags}"] != ""} then { + gdb_suppress_entire_file "Testcase assembly failed, so all tests in this file will automatically fail." +} + +if {[target_link $objfile $binfile "${link-flags}"] != ""} then { + gdb_suppress_entire_file "Testcase link failed, so all tests in this file will automatically fail." +} + +gdb_start +gdb_reinitialize_dir $srcdir/$subdir +gdb_load $binfile + +gdb_test "x /i _start" "neg.b\tr1h" \ + "neg.b r1h" +gdb_test "x" "neg.b\t@er1" \ + "neg.b @er1" +gdb_test "x" "neg.b\t@\\(0x3(:2|),er1\\)" \ + "neg.b @(0x3:2,er1)" +gdb_test "x" "neg.b\t@er1\\+" \ + "neg.b @er1+" +gdb_test "x" "neg.b\t@-er1" \ + "neg.b @-er1" +gdb_test "x" "neg.b\t@\\+er1" \ + "neg.b @+er1" +gdb_test "x" "neg.b\t@er1-" \ + "neg.b @er1-" +gdb_test "x" "neg.b\t@\\(0x1234(:16|),er1\\)" \ + "neg.b @(0x1234:16,er1)" +gdb_test "x" "neg.b\t@\\(0x12345678(:32|),er1\\)" \ + "neg.b @(0x12345678:32,er1)" +gdb_test "x" "neg.b\t@\\(0x1234(:16|),r2l.b\\)" \ + "neg.b @(0x1234:16,r2l.b)" +gdb_test "x" "neg.b\t@\\(0x1234(:16|),r2.w\\)" \ + "neg.b @(0x1234:16,r2.w)" +gdb_test "x" "neg.b\t@\\(0x1234(:16|),er2.l\\)" \ + "neg.b @(0x1234:16,er2.l)" +gdb_test "x" "neg.b\t@\\(0x12345678(:32|),r2l.b\\)" \ + "neg.b @(0x12345678:32,r2l.b)" +gdb_test "x" "neg.b\t@\\(0x12345678(:32|),r2.w\\)" \ + "neg.b @(0x12345678:32,r2.w)" +gdb_test "x" "neg.b\t@\\(0x12345678(:32|),er2.l\\)" \ + "neg.b @(0x12345678:32,er2.l)" +gdb_test "x" "neg.b\t@0x12(:8|)" \ + "neg.b @0x12:8" +gdb_test "x" "neg.b\t@0x1234(:16|)" \ + "neg.b @0x1234:16" +gdb_test "x" "neg.b\t@0x12345678(:32|)" \ + "neg.b @0x12345678:32" +gdb_test "x" "neg.w\tr1" \ + "neg.w r1" +gdb_test "x" "neg.w\t@er1" \ + "neg.w @er1" +gdb_test "x" "neg.w\t@\\(0x6(:2|),er1\\)" \ + "neg.w @(0x6:2,er1)" +gdb_test "x" "neg.w\t@er1\\+" \ + "neg.w @er1+" +gdb_test "x" "neg.w\t@-er1" \ + "neg.w @-er1" +gdb_test "x" "neg.w\t@\\+er1" \ + "neg.w @+er1" +gdb_test "x" "neg.w\t@er1-" \ + "neg.w @er1-" +gdb_test "x" "neg.w\t@\\(0x1234(:16|),er1\\)" \ + "neg.w @(0x1234:16,er1)" +gdb_test "x" "neg.w\t@\\(0x12345678(:32|),er1\\)" \ + "neg.w @(0x12345678:32,er1)" +gdb_test "x" "neg.w\t@\\(0x1234(:16|),r2l.b\\)" \ + "neg.w @(0x1234:16,r2l.b)" +gdb_test "x" "neg.w\t@\\(0x1234(:16|),r2.w\\)" \ + "neg.w @(0x1234:16,r2.w)" +gdb_test "x" "neg.w\t@\\(0x1234(:16|),er2.l\\)" \ + "neg.w @(0x1234:16,er2.l)" +gdb_test "x" "neg.w\t@\\(0x12345678(:32|),r2l.b\\)" \ + "neg.w @(0x12345678:32,r2l.b)" +gdb_test "x" "neg.w\t@\\(0x12345678(:32|),r2.w\\)" \ + "neg.w @(0x12345678:32,r2.w)" +gdb_test "x" "neg.w\t@\\(0x12345678(:32|),er2.l\\)" \ + "neg.w @(0x12345678:32,er2.l)" +gdb_test "x" "neg.w\t@0x1234(:16|)" \ + "neg.w @0x1234:16" +gdb_test "x" "neg.w\t@0x12345678(:32|)" \ + "neg.w @0x12345678:32" +gdb_test "x" "neg.l\ter1" \ + "neg.l er1" +gdb_test "x" "neg.l\t@er1" \ + "neg.l @er1" +gdb_test "x" "neg.l\t@\\(0xc(:2|),er1\\)" \ + "neg.l @(0xc:2,er1)" +gdb_test "x" "neg.l\t@er1\\+" \ + "neg.l @er1+" +gdb_test "x" "neg.l\t@-er1" \ + "neg.l @-er1" +gdb_test "x" "neg.l\t@\\+er1" \ + "neg.l @+er1" +gdb_test "x" "neg.l\t@er1-" \ + "neg.l @er1-" +gdb_test "x" "neg.l\t@\\(0x1234(:16|),er1\\)" \ + "neg.l @(0x1234:16,er1)" +gdb_test "x" "neg.l\t@\\(0x12345678(:32|),er1\\)" \ + "neg.l @(0x12345678:32,er1)" +gdb_test "x" "neg.l\t@\\(0x1234(:16|),r2l.b\\)" \ + "neg.l @(0x1234:16,r2l.b)" +gdb_test "x" "neg.l\t@\\(0x1234(:16|),r2.w\\)" \ + "neg.l @(0x1234:16,r2.w)" +gdb_test "x" "neg.l\t@\\(0x1234(:16|),er2.l\\)" \ + "neg.l @(0x1234:16,er2.l)" +gdb_test "x" "neg.l\t@\\(0x12345678(:32|),r2l.b\\)" \ + "neg.l @(0x12345678:32,r2l.b)" +gdb_test "x" "neg.l\t@\\(0x12345678(:32|),r2.w\\)" \ + "neg.l @(0x12345678:32,r2.w)" +gdb_test "x" "neg.l\t@\\(0x12345678(:32|),er2.l\\)" \ + "neg.l @(0x12345678:32,er2.l)" +gdb_test "x" "neg.l\t@0x1234(:16|)" \ + "neg.l @0x1234:16" +gdb_test "x" "neg.l\t@0x12345678(:32|)" \ + "neg.l @0x12345678:32" +gdb_test "x" "tas\t@er1" \ + "tas @er1" +gdb_test "x" "extu.w\tr1" \ + "extu.w r1" +gdb_test "x" "extu.w\t@er1" \ + "extu.w @er1" +gdb_test "x" "extu.w\t@\\(0x6(:2|),er1\\)" \ + "extu.w @(0x6:2,er1)" +gdb_test "x" "extu.w\t@er1\\+" \ + "extu.w @er1+" +gdb_test "x" "extu.w\t@-er1" \ + "extu.w @-er1" +gdb_test "x" "extu.w\t@\\+er1" \ + "extu.w @+er1" +gdb_test "x" "extu.w\t@er1-" \ + "extu.w @er1-" +gdb_test "x" "extu.w\t@\\(0x1234(:16|),er1\\)" \ + "extu.w @(0x1234:16,er1)" +gdb_test "x" "extu.w\t@\\(0x12345678(:32|),er1\\)" \ + "extu.w @(0x12345678:32,er1)" +gdb_test "x" "extu.w\t@\\(0x1234(:16|),r2l.b\\)" \ + "extu.w @(0x1234:16,r2l.b)" +gdb_test "x" "extu.w\t@\\(0x1234(:16|),r2.w\\)" \ + "extu.w @(0x1234:16,r2.w)" +gdb_test "x" "extu.w\t@\\(0x1234(:16|),er2.l\\)" \ + "extu.w @(0x1234:16,er2.l)" +gdb_test "x" "extu.w\t@\\(0x12345678(:32|),r2l.b\\)" \ + "extu.w @(0x12345678:32,r2l.b)" +gdb_test "x" "extu.w\t@\\(0x12345678(:32|),r2.w\\)" \ + "extu.w @(0x12345678:32,r2.w)" +gdb_test "x" "extu.w\t@\\(0x12345678(:32|),er2.l\\)" \ + "extu.w @(0x12345678:32,er2.l)" +gdb_test "x" "extu.w\t@0x1234(:16|)" \ + "extu.w @0x1234:16" +gdb_test "x" "extu.w\t@0x12345678(:32|)" \ + "extu.w @0x12345678:32" +gdb_test "x" "extu.l\ter1" \ + "extu.l er1" +gdb_test "x" "extu.l\t@er1" \ + "extu.l @er1" +gdb_test "x" "extu.l\t@\\(0xc(:2|),er1\\)" \ + "extu.l @(0xc:2,er1)" +gdb_test "x" "extu.l\t@er1\\+" \ + "extu.l @er1+" +gdb_test "x" "extu.l\t@-er1" \ + "extu.l @-er1" +gdb_test "x" "extu.l\t@\\+er1" \ + "extu.l @+er1" +gdb_test "x" "extu.l\t@er1-" \ + "extu.l @er1-" +gdb_test "x" "extu.l\t@\\(0x1234(:16|),er1\\)" \ + "extu.l @(0x1234:16,er1)" +gdb_test "x" "extu.l\t@\\(0x12345678(:32|),er1\\)" \ + "extu.l @(0x12345678:32,er1)" +gdb_test "x" "extu.l\t@\\(0x1234(:16|),r2l.b\\)" \ + "extu.l @(0x1234:16,r2l.b)" +gdb_test "x" "extu.l\t@\\(0x1234(:16|),r2.w\\)" \ + "extu.l @(0x1234:16,r2.w)" +gdb_test "x" "extu.l\t@\\(0x1234(:16|),er2.l\\)" \ + "extu.l @(0x1234:16,er2.l)" +gdb_test "x" "extu.l\t@\\(0x12345678(:32|),r2l.b\\)" \ + "extu.l @(0x12345678:32,r2l.b)" +gdb_test "x" "extu.l\t@\\(0x12345678(:32|),r2.w\\)" \ + "extu.l @(0x12345678:32,r2.w)" +gdb_test "x" "extu.l\t@\\(0x12345678(:32|),er2.l\\)" \ + "extu.l @(0x12345678:32,er2.l)" +gdb_test "x" "extu.l\t@0x1234(:16|)" \ + "extu.l @0x1234:16" +gdb_test "x" "extu.l\t@0x12345678(:32|)" \ + "extu.l @0x12345678:32" +gdb_test "x" "extu.l\t#2,er1" \ + "extu.l #2,er1" +gdb_test "x" "extu.l\t#2,@er1" \ + "extu.l #2,@er1" +gdb_test "x" "extu.l\t#2,@\\(0xc(:2|),er1\\)" \ + "extu.l #2,@(0xc:2,er1)" +gdb_test "x" "extu.l\t#2,@er1\\+" \ + "extu.l #2,@er1+" +gdb_test "x" "extu.l\t#2,@-er1" \ + "extu.l #2,@-er1" +gdb_test "x" "extu.l\t#2,@\\+er1" \ + "extu.l #2,@+er1" +gdb_test "x" "extu.l\t#2,@er1-" \ + "extu.l #2,@er1-" +gdb_test "x" "extu.l\t#2,@\\(0x1234(:16|),er1\\)" \ + "extu.l #2,@(0x1234:16,er1)" +gdb_test "x" "extu.l\t#2,@\\(0x12345678(:32|),er1\\)" \ + "extu.l #2,@(0x12345678:32,er1)" +gdb_test "x" "extu.l\t#2,@\\(0x1234(:16|),r2l.b\\)" \ + "extu.l #2,@(0x1234:16,r2l.b)" +gdb_test "x" "extu.l\t#2,@\\(0x1234(:16|),r2.w\\)" \ + "extu.l #2,@(0x1234:16,r2.w)" +gdb_test "x" "extu.l\t#2,@\\(0x1234(:16|),er2.l\\)" \ + "extu.l #2,@(0x1234:16,er2.l)" +gdb_test "x" "extu.l\t#2,@\\(0x12345678(:32|),r2l.b\\)" \ + "extu.l #2,@(0x12345678:32,r2l.b)" +gdb_test "x" "extu.l\t#2,@\\(0x12345678(:32|),r2.w\\)" \ + "extu.l #2,@(0x12345678:32,r2.w)" +gdb_test "x" "extu.l\t#2,@\\(0x12345678(:32|),er2.l\\)" \ + "extu.l #2,@(0x12345678:32,er2.l)" +gdb_test "x" "extu.l\t#2,@0x1234(:16|)" \ + "extu.l #2,@0x1234:16" +gdb_test "x" "extu.l\t#2,@0x12345678(:32|)" \ + "extu.l #2,@0x12345678:32" +gdb_test "x" "exts.w\tr1" \ + "exts.w r1" +gdb_test "x" "exts.w\t@er1" \ + "exts.w @er1" +gdb_test "x" "exts.w\t@\\(0x6(:2|),er1\\)" \ + "exts.w @(0x6:2,er1)" +gdb_test "x" "exts.w\t@er1\\+" \ + "exts.w @er1+" +gdb_test "x" "exts.w\t@-er1" \ + "exts.w @-er1" +gdb_test "x" "exts.w\t@\\+er1" \ + "exts.w @+er1" +gdb_test "x" "exts.w\t@er1-" \ + "exts.w @er1-" +gdb_test "x" "exts.w\t@\\(0x1234(:16|),er1\\)" \ + "exts.w @(0x1234:16,er1)" +gdb_test "x" "exts.w\t@\\(0x12345678(:32|),er1\\)" \ + "exts.w @(0x12345678:32,er1)" +gdb_test "x" "exts.w\t@\\(0x1234(:16|),r2l.b\\)" \ + "exts.w @(0x1234:16,r2l.b)" +gdb_test "x" "exts.w\t@\\(0x1234(:16|),r2.w\\)" \ + "exts.w @(0x1234:16,r2.w)" +gdb_test "x" "exts.w\t@\\(0x1234(:16|),er2.l\\)" \ + "exts.w @(0x1234:16,er2.l)" +gdb_test "x" "exts.w\t@\\(0x12345678(:32|),r2l.b\\)" \ + "exts.w @(0x12345678:32,r2l.b)" +gdb_test "x" "exts.w\t@\\(0x12345678(:32|),r2.w\\)" \ + "exts.w @(0x12345678:32,r2.w)" +gdb_test "x" "exts.w\t@\\(0x12345678(:32|),er2.l\\)" \ + "exts.w @(0x12345678:32,er2.l)" +gdb_test "x" "exts.w\t@0x1234(:16|)" \ + "exts.w @0x1234:16" +gdb_test "x" "exts.w\t@0x12345678(:32|)" \ + "exts.w @0x12345678:32" +gdb_test "x" "exts.l\ter1" \ + "exts.l er1" +gdb_test "x" "exts.l\t@er1" \ + "exts.l @er1" +gdb_test "x" "exts.l\t@\\(0xc(:2|),er1\\)" \ + "exts.l @(0xc:2,er1)" +gdb_test "x" "exts.l\t@er1\\+" \ + "exts.l @er1+" +gdb_test "x" "exts.l\t@-er1" \ + "exts.l @-er1" +gdb_test "x" "exts.l\t@\\+er1" \ + "exts.l @+er1" +gdb_test "x" "exts.l\t@er1-" \ + "exts.l @er1-" +gdb_test "x" "exts.l\t@\\(0x1234(:16|),er1\\)" \ + "exts.l @(0x1234:16,er1)" +gdb_test "x" "exts.l\t@\\(0x12345678(:32|),er1\\)" \ + "exts.l @(0x12345678:32,er1)" +gdb_test "x" "exts.l\t@\\(0x1234(:16|),r2l.b\\)" \ + "exts.l @(0x1234:16,r2l.b)" +gdb_test "x" "exts.l\t@\\(0x1234(:16|),r2.w\\)" \ + "exts.l @(0x1234:16,r2.w)" +gdb_test "x" "exts.l\t@\\(0x1234(:16|),er2.l\\)" \ + "exts.l @(0x1234:16,er2.l)" +gdb_test "x" "exts.l\t@\\(0x12345678(:32|),r2l.b\\)" \ + "exts.l @(0x12345678:32,r2l.b)" +gdb_test "x" "exts.l\t@\\(0x12345678(:32|),r2.w\\)" \ + "exts.l @(0x12345678:32,r2.w)" +gdb_test "x" "exts.l\t@\\(0x12345678(:32|),er2.l\\)" \ + "exts.l @(0x12345678:32,er2.l)" +gdb_test "x" "exts.l\t@0x1234(:16|)" \ + "exts.l @0x1234:16" +gdb_test "x" "exts.l\t@0x12345678(:32|)" \ + "exts.l @0x12345678:32" +gdb_test "x" "exts.l\t#2,er1" \ + "exts.l #2,er1" +gdb_test "x" "exts.l\t#2,@er1" \ + "exts.l #2,@er1" +gdb_test "x" "exts.l\t#2,@\\(0xc(:2|),er1\\)" \ + "exts.l #2,@(0xc:2,er1)" +gdb_test "x" "exts.l\t#2,@er1\\+" \ + "exts.l #2,@er1+" +gdb_test "x" "exts.l\t#2,@-er1" \ + "exts.l #2,@-er1" +gdb_test "x" "exts.l\t#2,@\\+er1" \ + "exts.l #2,@+er1" +gdb_test "x" "exts.l\t#2,@er1-" \ + "exts.l #2,@er1-" +gdb_test "x" "exts.l\t#2,@\\(0x1234(:16|),er1\\)" \ + "exts.l #2,@(0x1234:16,er1)" +gdb_test "x" "exts.l\t#2,@\\(0x12345678(:32|),er1\\)" \ + "exts.l #2,@(0x12345678:32,er1)" +gdb_test "x" "exts.l\t#2,@\\(0x1234(:16|),r2l.b\\)" \ + "exts.l #2,@(0x1234:16,r2l.b)" +gdb_test "x" "exts.l\t#2,@\\(0x1234(:16|),r2.w\\)" \ + "exts.l #2,@(0x1234:16,r2.w)" +gdb_test "x" "exts.l\t#2,@\\(0x1234(:16|),er2.l\\)" \ + "exts.l #2,@(0x1234:16,er2.l)" +gdb_test "x" "exts.l\t#2,@\\(0x12345678(:32|),r2l.b\\)" \ + "exts.l #2,@(0x12345678:32,r2l.b)" +gdb_test "x" "exts.l\t#2,@\\(0x12345678(:32|),r2.w\\)" \ + "exts.l #2,@(0x12345678:32,r2.w)" +gdb_test "x" "exts.l\t#2,@\\(0x12345678(:32|),er2.l\\)" \ + "exts.l #2,@(0x12345678:32,er2.l)" +gdb_test "x" "exts.l\t#2,@0x1234(:16|)" \ + "exts.l #2,@0x1234:16" +gdb_test "x" "exts.l\t#2,@0x12345678(:32|)" \ + "exts.l #2,@0x12345678:32" diff --git a/gdb/testsuite/gdb.disasm/t07_ari3.s b/gdb/testsuite/gdb.disasm/t07_ari3.s new file mode 100644 index 0000000..985c684 --- /dev/null +++ b/gdb/testsuite/gdb.disasm/t07_ari3.s @@ -0,0 +1,173 @@ +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;arith_3 +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + .h8300sx + .text + .global _start +_start: + neg.b r1h ;1781 + neg.b @er1 ;7d101780 + neg.b @(0x3:2,er1) ;017768181780 + neg.b @er1+ ;01746c181780 + neg.b @-er1 ;01776c181780 + neg.b @+er1 ;01756c181780 + neg.b @er1- ;01766c181780 + neg.b @(0x1234:16,er1) ;01746e1812341780 + neg.b @(0x12345678:32,er1) ;78146a28123456781780 + neg.b @(0x1234:16,r2l.b) ;01756e2812341780 + neg.b @(0x1234:16,r2.w) ;01766e2812341780 + neg.b @(0x1234:16,er2.l) ;01776e2812341780 + neg.b @(0x12345678:32,r2l.b) ;78256a28123456781780 + neg.b @(0x12345678:32,r2.w) ;78266a28123456781780 + neg.b @(0x12345678:32,er2.l) ;78276a28123456781780 + neg.b @0xffffff12:8 ;7f121780 + neg.b @0x1234:16 ;6a1812341780 + neg.b @0x12345678:32 ;6a38123456781780 + + neg.w r1 ;1791 + neg.w @er1 ;7d901790 + neg.w @(0x6:2,er1) ;015769181790 + neg.w @er1+ ;01546d181790 + neg.w @-er1 ;01576d181790 + neg.w @+er1 ;01556d181790 + neg.w @er1- ;01566d181790 + neg.w @(0x1234:16,er1) ;01546f1812341790 + neg.w @(0x12345678:32,er1) ;78146b28123456781790 + neg.w @(0x1234:16,r2l.b) ;01556f2812341790 + neg.w @(0x1234:16,r2.w) ;01566f2812341790 + neg.w @(0x1234:16,er2.l) ;01576f2812341790 + neg.w @(0x12345678:32,r2l.b) ;78256b28123456781790 + neg.w @(0x12345678:32,r2.w) ;78266b28123456781790 + neg.w @(0x12345678:32,er2.l) ;78276b28123456781790 + neg.w @0x1234:16 ;6b1812341790 + neg.w @0x12345678:32 ;6b38123456781790 + + neg.l er1 ;17b1 + neg.l @er1 ;0104691817b0 + neg.l @(0xc:2,er1) ;0107691817b0 + neg.l @er1+ ;01046d1817b0 + neg.l @-er1 ;01076d1817b0 + neg.l @+er1 ;01056d1817b0 + neg.l @er1- ;01066d1817b0 + neg.l @(0x1234:16,er1) ;01046f18123417b0 + neg.l @(0x12345678:32,er1) ;78946b281234567817b0 + neg.l @(0x1234:16,r2l.b) ;01056f28123417b0 + neg.l @(0x1234:16,r2.w) ;01066f28123417b0 + neg.l @(0x1234:16,er2.l) ;01076f28123417b0 + neg.l @(0x12345678:32,r2l.b) ;78a56b281234567817b0 + neg.l @(0x12345678:32,r2.w) ;78a66b281234567817b0 + neg.l @(0x12345678:32,er2.l) ;78a76b281234567817b0 + neg.l @0x1234:16 ;01046b08123417b0 + neg.l @0x12345678:32 ;01046b281234567817b0 + + tas @er1 ;01e07b1c + + extu.w r1 ;1751 + extu.w @er1 ;7d901750 + extu.w @(0x6:2,er1) ;015769181750 + extu.w @er1+ ;01546d181750 + extu.w @-er1 ;01576d181750 + extu.w @+er1 ;01556d181750 + extu.w @er1- ;01566d181750 + extu.w @(0x1234:16,er1) ;01546f1812341750 + extu.w @(0x12345678:32,er1) ;78146b28123456781750 + extu.w @(0x1234:16,r2l.b) ;01556f2812341750 + extu.w @(0x1234:16,r2.w) ;01566f2812341750 + extu.w @(0x1234:16,er2.l) ;01576f2812341750 + extu.w @(0x12345678:32,r2l.b) ;78256b28123456781750 + extu.w @(0x12345678:32,r2.w) ;78266b28123456781750 + extu.w @(0x12345678:32,er2.l) ;78276b28123456781750 + extu.w @0x1234:16 ;6b1812341750 + extu.w @0x12345678:32 ;6b38123456781750 + + extu.l er1 ;1771 + extu.l @er1 ;010469181770 + extu.l @(0xc:2,er1) ;010769181770 + extu.l @er1+ ;01046d181770 + extu.l @-er1 ;01076d181770 + extu.l @+er1 ;01056d181770 + extu.l @er1- ;01066d181770 + extu.l @(0x1234:16,er1) ;01046f1812341770 + extu.l @(0x12345678:32,er1) ;78946b28123456781770 + extu.l @(0x1234:16,r2l.b) ;01056f2812341770 + extu.l @(0x1234:16,r2.w) ;01066f2812341770 + extu.l @(0x1234:16,er2.l) ;01076f2812341770 + extu.l @(0x12345678:32,r2l.b) ;78a56b28123456781770 + extu.l @(0x12345678:32,r2.w) ;78a66b28123456781770 + extu.l @(0x12345678:32,er2.l) ;78a76b28123456781770 + extu.l @0x1234:16 ;01046b0812341770 + extu.l @0x12345678:32 ;01046b28123456781770 + + extu.l #2,er1 ;1761 + extu.l #2,@er1 ;010469181760 + extu.l #2,@(0xc:2,er1) ;010769181760 + extu.l #2,@er1+ ;01046d181760 + extu.l #2,@-er1 ;01076d181760 + extu.l #2,@+er1 ;01056d181760 + extu.l #2,@er1- ;01066d181760 + extu.l #2,@(0x1234:16,er1) ;01046f1812341760 + extu.l #2,@(0x12345678:32,er1) ;78946b28123456781760 + extu.l #2,@(0x1234:16,r2l.b) ;01056f2812341760 + extu.l #2,@(0x1234:16,r2.w) ;01066f2812341760 + extu.l #2,@(0x1234:16,er2.l) ;01076f2812341760 + extu.l #2,@(0x12345678:32,r2l.b) ;78a56b28123456781760 + extu.l #2,@(0x12345678:32,r2.w) ;78a66b28123456781760 + extu.l #2,@(0x12345678:32,er2.l) ;78a76b28123456781760 + extu.l #2,@0x1234:16 ;01046b0812341760 + extu.l #2,@0x12345678:32 ;01046b28123456781760 + + exts.w r1 ;17d1 + exts.w @er1 ;7d9017d0 + exts.w @(0x6:2,er1) ;0157691817d0 + exts.w @er1+ ;01546d1817d0 + exts.w @-er1 ;01576d1817d0 + exts.w @+er1 ;01556d1817d0 + exts.w @er1- ;01566d1817d0 + exts.w @(0x1234:16,er1) ;01546f18123417d0 + exts.w @(0x12345678:32,er1) ;78146b281234567817d0 + exts.w @(0x1234:16,r2l.b) ;01556f28123417d0 + exts.w @(0x1234:16,r2.w) ;01566f28123417d0 + exts.w @(0x1234:16,er2.l) ;01576f28123417d0 + exts.w @(0x12345678:32,r2l.b) ;78256b281234567817d0 + exts.w @(0x12345678:32,r2.w) ;78266b281234567817d0 + exts.w @(0x12345678:32,er2.l) ;78276b281234567817d0 + exts.w @0x1234:16 ;6b18123417d0 + exts.w @0x12345678:32 ;6b381234567817d0 + + exts.l er1 ;17f1 + exts.l @er1 ;0104691817f0 + exts.l @(0xc:2,er1) ;0107691817f0 + exts.l @er1+ ;01046d1817f0 + exts.l @-er1 ;01076d1817f0 + exts.l @+er1 ;01056d1817f0 + exts.l @er1- ;01066d1817f0 + exts.l @(0x1234:16,er1) ;01046f18123417f0 + exts.l @(0x12345678:32,er1) ;78946b281234567817f0 + exts.l @(0x1234:16,r2l.b) ;01056f28123417f0 + exts.l @(0x1234:16,r2.w) ;01066f28123417f0 + exts.l @(0x1234:16,er2.l) ;01076f28123417f0 + exts.l @(0x12345678:32,r2l.b) ;78a56b281234567817f0 + exts.l @(0x12345678:32,r2.w) ;78a66b281234567817f0 + exts.l @(0x12345678:32,er2.l) ;78a76b281234567817f0 + exts.l @0x1234:16 ;01046b08123417f0 + exts.l @0x12345678:32 ;01046b281234567817f0 + + exts.l #2,er1 ;17e1 + exts.l #2,@er1 ;0104691817e0 + exts.l #2,@(0xc:2,er1) ;0107691817e0 + exts.l #2,@er1+ ;01046d1817e0 + exts.l #2,@-er1 ;01076d1817e0 + exts.l #2,@+er1 ;01056d1817e0 + exts.l #2,@er1- ;01066d1817e0 + exts.l #2,@(0x1234:16,er1) ;01046f18123417e0 + exts.l #2,@(0x12345678:32,er1) ;78946b281234567817e0 + exts.l #2,@(0x1234:16,r2l.b) ;01056f28123417e0 + exts.l #2,@(0x1234:16,r2.w) ;01066f28123417e0 + exts.l #2,@(0x1234:16,er2.l) ;01076f28123417e0 + exts.l #2,@(0x12345678:32,r2l.b) ;78a56b281234567817e0 + exts.l #2,@(0x12345678:32,r2.w) ;78a66b281234567817e0 + exts.l #2,@(0x12345678:32,er2.l) ;78a76b281234567817e0 + exts.l #2,@0x1234:16 ;01046b08123417e0 + exts.l #2,@0x12345678:32 ;01046b281234567817e0 + + .end diff --git a/gdb/testsuite/gdb.disasm/t08_or.exp b/gdb/testsuite/gdb.disasm/t08_or.exp new file mode 100644 index 0000000..5652cf7 --- /dev/null +++ b/gdb/testsuite/gdb.disasm/t08_or.exp @@ -0,0 +1,1866 @@ +# Copyright (C) 2003 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# Please email any bugs, comments, and/or additions to this file to: +# bug-gdb@prep.ai.mit.edu + +# This file was written by Michael Snyder (msnyder@redhat.com) + +if $tracelevel then { + strace $tracelevel +} + +if ![istarget "h8300*-*-*"] { + verbose "Tests ignored for all but h8300s based targets." + return +} + +set prms_id 0 +set bug_id 0 + +set testfile "t08_or" +set srcfile ${srcdir}/${subdir}/${testfile}.s +set objfile ${objdir}/${subdir}/${testfile}.o +set binfile ${objdir}/${subdir}/${testfile}.x + +set asm-flags ""; +set link-flags "-m h8300sxelf"; + + +if {[target_assemble $srcfile $objfile "${asm-flags}"] != ""} then { + gdb_suppress_entire_file "Testcase assembly failed, so all tests in this file will automatically fail." +} + +if {[target_link $objfile $binfile "${link-flags}"] != ""} then { + gdb_suppress_entire_file "Testcase link failed, so all tests in this file will automatically fail." +} + +gdb_start +gdb_reinitialize_dir $srcdir/$subdir +gdb_load $binfile + +gdb_test "x /i _start" "or.b\t#0x12(:8|),r1h" \ + "or.b #0x12:8,r1h" +gdb_test "x" "or.b\t#0x12(:8|),@er1" \ + "or.b #0x12:8,@er1" +gdb_test "x" "or.b\t#0x12(:8|),@\\(0x3(:2|),er1\\)" \ + "or.b #0x12:8,@(0x3:2,er1)" +gdb_test "x" "or.b\t#0x12(:8|),@er1\\+" \ + "or.b #0x12:8,@er1+" +gdb_test "x" "or.b\t#0x12(:8|),@-er1" \ + "or.b #0x12:8,@-er1" +gdb_test "x" "or.b\t#0x12(:8|),@\\+er1" \ + "or.b #0x12:8,@+er1" +gdb_test "x" "or.b\t#0x12(:8|),@er1-" \ + "or.b #0x12:8,@er1-" +gdb_test "x" "or.b\t#0x12(:8|),@\\(0x1234(:16|),er1\\)" \ + "or.b #0x12:8,@(0x1234:16,er1)" +gdb_test "x" "or.b\t#0x12(:8|),@\\(0x12345678(:32|),er1\\)" \ + "or.b #0x12:8,@(0x12345678:32,er1)" +gdb_test "x" "or.b\t#0x12(:8|),@\\(0x1234(:16|),r2l.b\\)" \ + "or.b #0x12:8,@(0x1234:16,r2l.b)" +gdb_test "x" "or.b\t#0x12(:8|),@\\(0x1234(:16|),r2.w\\)" \ + "or.b #0x12:8,@(0x1234:16,r2.w)" +gdb_test "x" "or.b\t#0x12(:8|),@\\(0x1234(:16|),er2.l\\)" \ + "or.b #0x12:8,@(0x1234:16,er2.l)" +gdb_test "x" "or.b\t#0x12(:8|),@\\(0x12345678(:32|),r2l.b\\)" \ + "or.b #0x12:8,@(0x12345678:32,r2l.b)" +gdb_test "x" "or.b\t#0x12(:8|),@\\(0x12345678(:32|),r2.w\\)" \ + "or.b #0x12:8,@(0x12345678:32,r2.w)" +gdb_test "x" "or.b\t#0x12(:8|),@\\(0x12345678(:32|),er2.l\\)" \ + "or.b #0x12:8,@(0x12345678:32,er2.l)" +gdb_test "x" "or.b\t#0x12(:8|),@0x12(:8|)" \ + "or.b #0x12:8,@0x12:8" +gdb_test "x" "or.b\t#0x12(:8|),@0x1234(:16|)" \ + "or.b #0x12:8,@0x1234:16" +gdb_test "x" "or.b\t#0x12(:8|),@0x12345678(:32|)" \ + "or.b #0x12:8,@0x12345678:32" +gdb_test "x" "or.b\tr3h,r1h" \ + "or.b r3h,r1h" +gdb_test "x" "or.b\tr3h,@er1" \ + "or.b r3h,@er1" +gdb_test "x" "or.b\tr3h,@\\(0x3(:2|),er1\\)" \ + "or.b r3h,@(0x3:2,er1)" +gdb_test "x" "or.b\tr3h,@er1\\+" \ + "or.b r3h,@er1+" +gdb_test "x" "or.b\tr3h,@-er1" \ + "or.b r3h,@-er1" +gdb_test "x" "or.b\tr3h,@\\+er1" \ + "or.b r3h,@+er1" +gdb_test "x" "or.b\tr3h,@er1-" \ + "or.b r3h,@er1-" +gdb_test "x" "or.b\tr3h,@\\(0x1234(:16|),er1\\)" \ + "or.b r3h,@(0x1234:16,er1)" +gdb_test "x" "or.b\tr3h,@\\(0x12345678(:32|),er1\\)" \ + "or.b r3h,@(0x12345678:32,er1)" +gdb_test "x" "or.b\tr3h,@\\(0x1234(:16|),r2l.b\\)" \ + "or.b r3h,@(0x1234:16,r2l.b)" +gdb_test "x" "or.b\tr3h,@\\(0x1234(:16|),r2.w\\)" \ + "or.b r3h,@(0x1234:16,r2.w)" +gdb_test "x" "or.b\tr3h,@\\(0x1234(:16|),er2.l\\)" \ + "or.b r3h,@(0x1234:16,er2.l)" +gdb_test "x" "or.b\tr3h,@\\(0x12345678(:32|),r2l.b\\)" \ + "or.b r3h,@(0x12345678:32,r2l.b)" +gdb_test "x" "or.b\tr3h,@\\(0x12345678(:32|),r2.w\\)" \ + "or.b r3h,@(0x12345678:32,r2.w)" +gdb_test "x" "or.b\tr3h,@\\(0x12345678(:32|),er2.l\\)" \ + "or.b r3h,@(0x12345678:32,er2.l)" +gdb_test "x" "or.b\tr3h,@0x12(:8|)" \ + "or.b r3h,@0x12:8" +gdb_test "x" "or.b\tr3h,@0x1234(:16|)" \ + "or.b r3h,@0x1234:16" +gdb_test "x" "or.b\tr3h,@0x12345678(:32|)" \ + "or.b r3h,@0x12345678:32" +gdb_test "x" "or.b\t@er3,r1h" \ + "or.b @er3,r1h" +gdb_test "x" "or.b\t@\\(0x3(:2|),er3\\),r1h" \ + "or.b @(0x3:2,er3),r1h" +gdb_test "x" "or.b\t@er3\\+,r1h" \ + "or.b @er3+,r1h" +gdb_test "x" "or.b\t@-er3,r1h" \ + "or.b @-er3,r1h" +gdb_test "x" "or.b\t@\\+er3,r1h" \ + "or.b @+er3,r1h" +gdb_test "x" "or.b\t@er3-,r1h" \ + "or.b @er3-,r1h" +gdb_test "x" "or.b\t@\\(0x1234(:16|),er1\\),r1h" \ + "or.b @(0x1234:16,er1),r1h" +gdb_test "x" "or.b\t@\\(0x12345678(:32|),er1\\),r1h" \ + "or.b @(0x12345678:32,er1),r1h" +gdb_test "x" "or.b\t@\\(0x1234(:16|),r2l.b\\),r1h" \ + "or.b @(0x1234:16,r2l.b),r1h" +gdb_test "x" "or.b\t@\\(0x1234(:16|),r2.w\\),r1h" \ + "or.b @(0x1234:16,r2.w),r1h" +gdb_test "x" "or.b\t@\\(0x1234(:16|),er2.l\\),r1h" \ + "or.b @(0x1234:16,er2.l),r1h" +gdb_test "x" "or.b\t@\\(0x12345678(:32|),r2l.b\\),r1h" \ + "or.b @(0x12345678:32,r2l.b),r1h" +gdb_test "x" "or.b\t@\\(0x12345678(:32|),r2.w\\),r1h" \ + "or.b @(0x12345678:32,r2.w),r1h" +gdb_test "x" "or.b\t@\\(0x12345678(:32|),er2.l\\),r1h" \ + "or.b @(0x12345678:32,er2.l),r1h" +gdb_test "x" "or.b\t@0x12(:8|),r1h" \ + "or.b @0x12:8,r1h" +gdb_test "x" "or.b\t@0x1234(:16|),r1h" \ + "or.b @0x1234:16,r1h" +gdb_test "x" "or.b\t@0x12345678(:32|),r1h" \ + "or.b @0x12345678:32,r1h" +gdb_test "x" "or.b\t@er3,@er1" \ + "or.b @er3,@er1" +gdb_test "x" "or.b\t@er3,@\\(0x3(:2|),er1\\)" \ + "or.b @er3,@(0x3:2,er1)" +gdb_test "x" "or.b\t@er3,@-er1" \ + "or.b @er3,@-er1" +gdb_test "x" "or.b\t@er3,@er1\\+" \ + "or.b @er3,@er1+" +gdb_test "x" "or.b\t@er3,@er1-" \ + "or.b @er3,@er1-" +gdb_test "x" "or.b\t@er3,@\\+er1" \ + "or.b @er3,@+er1" +gdb_test "x" "or.b\t@er3,@\\(0x9abc(:16|),er1\\)" \ + "or.b @er3,@(0x9abc:16,er1)" +gdb_test "x" "or.b\t@er3,@\\(0x9abcdef0(:32|),er1\\)" \ + "or.b @er3,@(0x9abcdef0:32,er1)" +gdb_test "x" "or.b\t@er3,@\\(0x9abc(:16|),r2l.b\\)" \ + "or.b @er3,@(0x9abc:16,r2l.b)" +gdb_test "x" "or.b\t@er3,@\\(0x9abc(:16|),r2.w\\)" \ + "or.b @er3,@(0x9abc:16,r2.w)" +gdb_test "x" "or.b\t@er3,@\\(0x9abc(:16|),er2.l\\)" \ + "or.b @er3,@(0x9abc:16,er2.l)" +gdb_test "x" "or.b\t@er3,@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "or.b @er3,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "or.b\t@er3,@\\(0x9abcdef0(:32|),r2.w\\)" \ + "or.b @er3,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "or.b\t@er3,@\\(0x9abcdef0(:32|),er2.l\\)" \ + "or.b @er3,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "or.b\t@er3,@0x9abc(:16|)" \ + "or.b @er3,@0x9abc:16" +gdb_test "x" "or.b\t@er3,@0x9abcdef0(:32|)" \ + "or.b @er3,@0x9abcdef0:32" +gdb_test "x" "or.b\t@-er3,@er1" \ + "or.b @-er3,@er1" +gdb_test "x" "or.b\t@-er3,@\\(0x3(:2|),er1\\)" \ + "or.b @-er3,@(0x3:2,er1)" +gdb_test "x" "or.b\t@-er3,@-er1" \ + "or.b @-er3,@-er1" +gdb_test "x" "or.b\t@-er3,@er1\\+" \ + "or.b @-er3,@er1+" +gdb_test "x" "or.b\t@-er3,@er1-" \ + "or.b @-er3,@er1-" +gdb_test "x" "or.b\t@-er3,@\\+er1" \ + "or.b @-er3,@+er1" +gdb_test "x" "or.b\t@-er3,@\\(0x9abc(:16|),er1\\)" \ + "or.b @-er3,@(0x9abc:16,er1)" +gdb_test "x" "or.b\t@-er3,@\\(0x9abcdef0(:32|),er1\\)" \ + "or.b @-er3,@(0x9abcdef0:32,er1)" +gdb_test "x" "or.b\t@-er3,@\\(0x9abc(:16|),r2l.b\\)" \ + "or.b @-er3,@(0x9abc:16,r2l.b)" +gdb_test "x" "or.b\t@-er3,@\\(0x9abc(:16|),r2.w\\)" \ + "or.b @-er3,@(0x9abc:16,r2.w)" +gdb_test "x" "or.b\t@-er3,@\\(0x9abc(:16|),er2.l\\)" \ + "or.b @-er3,@(0x9abc:16,er2.l)" +gdb_test "x" "or.b\t@-er3,@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "or.b @-er3,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "or.b\t@-er3,@\\(0x9abcdef0(:32|),r2.w\\)" \ + "or.b @-er3,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "or.b\t@-er3,@\\(0x9abcdef0(:32|),er2.l\\)" \ + "or.b @-er3,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "or.b\t@-er3,@0x9abc(:16|)" \ + "or.b @-er3,@0x9abc:16" +gdb_test "x" "or.b\t@-er3,@0x9abcdef0(:32|)" \ + "or.b @-er3,@0x9abcdef0:32" +gdb_test "x" "or.b\t@er3\\+,@er1" \ + "or.b @er3+,@er1" +gdb_test "x" "or.b\t@er3\\+,@\\(0x3(:2|),er1\\)" \ + "or.b @er3+,@(0x3:2,er1)" +gdb_test "x" "or.b\t@er3\\+,@-er1" \ + "or.b @er3+,@-er1" +gdb_test "x" "or.b\t@er3\\+,@er1\\+" \ + "or.b @er3+,@er1+" +gdb_test "x" "or.b\t@er3\\+,@er1-" \ + "or.b @er3+,@er1-" +gdb_test "x" "or.b\t@er3\\+,@\\+er1" \ + "or.b @er3+,@+er1" +gdb_test "x" "or.b\t@er3\\+,@\\(0x9abc(:16|),er1\\)" \ + "or.b @er3+,@(0x9abc:16,er1)" +gdb_test "x" "or.b\t@er3\\+,@\\(0x9abcdef0(:32|),er1\\)" \ + "or.b @er3+,@(0x9abcdef0:32,er1)" +gdb_test "x" "or.b\t@er3\\+,@\\(0x9abc(:16|),r2l.b\\)" \ + "or.b @er3+,@(0x9abc:16,r2l.b)" +gdb_test "x" "or.b\t@er3\\+,@\\(0x9abc(:16|),r2.w\\)" \ + "or.b @er3+,@(0x9abc:16,r2.w)" +gdb_test "x" "or.b\t@er3\\+,@\\(0x9abc(:16|),er2.l\\)" \ + "or.b @er3+,@(0x9abc:16,er2.l)" +gdb_test "x" "or.b\t@er3\\+,@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "or.b @er3+,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "or.b\t@er3\\+,@\\(0x9abcdef0(:32|),r2.w\\)" \ + "or.b @er3+,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "or.b\t@er3\\+,@\\(0x9abcdef0(:32|),er2.l\\)" \ + "or.b @er3+,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "or.b\t@er3\\+,@0x9abc(:16|)" \ + "or.b @er3+,@0x9abc:16" +gdb_test "x" "or.b\t@er3\\+,@0x9abcdef0(:32|)" \ + "or.b @er3+,@0x9abcdef0:32" +gdb_test "x" "or.b\t@er3-,@er1" \ + "or.b @er3-,@er1" +gdb_test "x" "or.b\t@er3-,@\\(0x3(:2|),er1\\)" \ + "or.b @er3-,@(0x3:2,er1)" +gdb_test "x" "or.b\t@er3-,@-er1" \ + "or.b @er3-,@-er1" +gdb_test "x" "or.b\t@er3-,@er1\\+" \ + "or.b @er3-,@er1+" +gdb_test "x" "or.b\t@er3-,@er1-" \ + "or.b @er3-,@er1-" +gdb_test "x" "or.b\t@er3-,@\\+er1" \ + "or.b @er3-,@+er1" +gdb_test "x" "or.b\t@er3-,@\\(0x9abc(:16|),er1\\)" \ + "or.b @er3-,@(0x9abc:16,er1)" +gdb_test "x" "or.b\t@er3-,@\\(0x9abcdef0(:32|),er1\\)" \ + "or.b @er3-,@(0x9abcdef0:32,er1)" +gdb_test "x" "or.b\t@er3-,@\\(0x9abc(:16|),r2l.b\\)" \ + "or.b @er3-,@(0x9abc:16,r2l.b)" +gdb_test "x" "or.b\t@er3-,@\\(0x9abc(:16|),r2.w\\)" \ + "or.b @er3-,@(0x9abc:16,r2.w)" +gdb_test "x" "or.b\t@er3-,@\\(0x9abc(:16|),er2.l\\)" \ + "or.b @er3-,@(0x9abc:16,er2.l)" +gdb_test "x" "or.b\t@er3-,@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "or.b @er3-,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "or.b\t@er3-,@\\(0x9abcdef0(:32|),r2.w\\)" \ + "or.b @er3-,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "or.b\t@er3-,@\\(0x9abcdef0(:32|),er2.l\\)" \ + "or.b @er3-,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "or.b\t@er3-,@0x9abc(:16|)" \ + "or.b @er3-,@0x9abc:16" +gdb_test "x" "or.b\t@er3-,@0x9abcdef0(:32|)" \ + "or.b @er3-,@0x9abcdef0:32" +gdb_test "x" "or.b\t@\\+er3,@er1" \ + "or.b @+er3,@er1" +gdb_test "x" "or.b\t@\\+er3,@\\(0x3(:2|),er1\\)" \ + "or.b @+er3,@(0x3:2,er1)" +gdb_test "x" "or.b\t@\\+er3,@-er1" \ + "or.b @+er3,@-er1" +gdb_test "x" "or.b\t@\\+er3,@er1\\+" \ + "or.b @+er3,@er1+" +gdb_test "x" "or.b\t@\\+er3,@er1-" \ + "or.b @+er3,@er1-" +gdb_test "x" "or.b\t@\\+er3,@\\+er1" \ + "or.b @+er3,@+er1" +gdb_test "x" "or.b\t@\\+er3,@\\(0x9abc(:16|),er1\\)" \ + "or.b @+er3,@(0x9abc:16,er1)" +gdb_test "x" "or.b\t@\\+er3,@\\(0x9abcdef0(:32|),er1\\)" \ + "or.b @+er3,@(0x9abcdef0:32,er1)" +gdb_test "x" "or.b\t@\\+er3,@\\(0x9abc(:16|),r2l.b\\)" \ + "or.b @+er3,@(0x9abc:16,r2l.b)" +gdb_test "x" "or.b\t@\\+er3,@\\(0x9abc(:16|),r2.w\\)" \ + "or.b @+er3,@(0x9abc:16,r2.w)" +gdb_test "x" "or.b\t@\\+er3,@\\(0x9abc(:16|),er2.l\\)" \ + "or.b @+er3,@(0x9abc:16,er2.l)" +gdb_test "x" "or.b\t@\\+er3,@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "or.b @+er3,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "or.b\t@\\+er3,@\\(0x9abcdef0(:32|),r2.w\\)" \ + "or.b @+er3,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "or.b\t@\\+er3,@\\(0x9abcdef0(:32|),er2.l\\)" \ + "or.b @+er3,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "or.b\t@\\+er3,@0x9abc(:16|)" \ + "or.b @+er3,@0x9abc:16" +gdb_test "x" "or.b\t@\\+er3,@0x9abcdef0(:32|)" \ + "or.b @+er3,@0x9abcdef0:32" +gdb_test "x" "or.b\t@\\(0x1234(:16|),er3\\),@er1" \ + "or.b @(0x1234:16,er3),@er1" +gdb_test "x" "or.b\t@\\(0x1234(:16|),er3\\),@\\(0x3(:2|),er1\\)" \ + "or.b @(0x1234:16,er3),@(0x3:2,er1)" +gdb_test "x" "or.b\t@\\(0x1234(:16|),er3\\),@-er1" \ + "or.b @(0x1234:16,er3),@-er1" +gdb_test "x" "or.b\t@\\(0x1234(:16|),er3\\),@er1\\+" \ + "or.b @(0x1234:16,er3),@er1+" +gdb_test "x" "or.b\t@\\(0x1234(:16|),er3\\),@er1-" \ + "or.b @(0x1234:16,er3),@er1-" +gdb_test "x" "or.b\t@\\(0x1234(:16|),er3\\),@\\+er1" \ + "or.b @(0x1234:16,er3),@+er1" +gdb_test "x" "or.b\t@\\(0x1234(:16|),er3\\),@\\(0x9abc(:16|),er1\\)" \ + "or.b @(0x1234:16,er3),@(0x9abc:16,er1)" +gdb_test "x" "or.b\t@\\(0x1234(:16|),er3\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "or.b @(0x1234:16,er3),@(0x9abcdef0:32,er1)" +gdb_test "x" "or.b\t@\\(0x1234(:16|),er3\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "or.b @(0x1234:16,er3),@(0x9abc:16,r2l.b)" +gdb_test "x" "or.b\t@\\(0x1234(:16|),er3\\),@\\(0x9abc(:16|),r2.w\\)" \ + "or.b @(0x1234:16,er3),@(0x9abc:16,r2.w)" +gdb_test "x" "or.b\t@\\(0x1234(:16|),er3\\),@\\(0x9abc(:16|),er2.l\\)" \ + "or.b @(0x1234:16,er3),@(0x9abc:16,er2.l)" +gdb_test "x" "or.b\t@\\(0x1234(:16|),er3\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "or.b @(0x1234:16,er3),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "or.b\t@\\(0x1234(:16|),er3\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "or.b @(0x1234:16,er3),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "or.b\t@\\(0x1234(:16|),er3\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "or.b @(0x1234:16,er3),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "or.b\t@\\(0x1234(:16|),er3\\),@0x9abc(:16|)" \ + "or.b @(0x1234:16,er3),@0x9abc:16" +gdb_test "x" "or.b\t@\\(0x1234(:16|),er3\\),@0x9abcdef0(:32|)" \ + "or.b @(0x1234:16,er3),@0x9abcdef0:32" +gdb_test "x" "or.b\t@\\(0x12345678(:32|),er3\\),@er1" \ + "or.b @(0x12345678:32,er3),@er1" +gdb_test "x" "or.b\t@\\(0x12345678(:32|),er3\\),@\\(0x3(:2|),er1\\)" \ + "or.b @(0x12345678:32,er3),@(0x3:2,er1)" +gdb_test "x" "or.b\t@\\(0x12345678(:32|),er3\\),@-er1" \ + "or.b @(0x12345678:32,er3),@-er1" +gdb_test "x" "or.b\t@\\(0x12345678(:32|),er3\\),@er1\\+" \ + "or.b @(0x12345678:32,er3),@er1+" +gdb_test "x" "or.b\t@\\(0x12345678(:32|),er3\\),@er1-" \ + "or.b @(0x12345678:32,er3),@er1-" +gdb_test "x" "or.b\t@\\(0x12345678(:32|),er3\\),@\\+er1" \ + "or.b @(0x12345678:32,er3),@+er1" +gdb_test "x" "or.b\t@\\(0x12345678(:32|),er3\\),@\\(0x9abc(:16|),er1\\)" \ + "or.b @(0x12345678:32,er3),@(0x9abc:16,er1)" +gdb_test "x" "or.b\t@\\(0x12345678(:32|),er3\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "or.b @(0x12345678:32,er3),@(0x9abcdef0:32,er1)" +gdb_test "x" "or.b\t@\\(0x12345678(:32|),er3\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "or.b @(0x12345678:32,er3),@(0x9abc:16,r2l.b)" +gdb_test "x" "or.b\t@\\(0x12345678(:32|),er3\\),@\\(0x9abc(:16|),r2.w\\)" \ + "or.b @(0x12345678:32,er3),@(0x9abc:16,r2.w)" +gdb_test "x" "or.b\t@\\(0x12345678(:32|),er3\\),@\\(0x9abc(:16|),er2.l\\)" \ + "or.b @(0x12345678:32,er3),@(0x9abc:16,er2.l)" +gdb_test "x" "or.b\t@\\(0x12345678(:32|),er3\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "or.b @(0x12345678:32,er3),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "or.b\t@\\(0x12345678(:32|),er3\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "or.b @(0x12345678:32,er3),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "or.b\t@\\(0x12345678(:32|),er3\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "or.b @(0x12345678:32,er3),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "or.b\t@\\(0x12345678(:32|),er3\\),@0x9abc(:16|)" \ + "or.b @(0x12345678:32,er3),@0x9abc:16" +gdb_test "x" "or.b\t@\\(0x12345678(:32|),er3\\),@0x9abcdef0(:32|)" \ + "or.b @(0x12345678:32,er3),@0x9abcdef0:32" +gdb_test "x" "or.b\t@\\(0x1234(:16|),r3l.b\\),@er1" \ + "or.b @(0x1234:16,r3l.b),@er1" +gdb_test "x" "or.b\t@\\(0x1234(:16|),r3l.b\\),@\\(0x3(:2|),er1\\)" \ + "or.b @(0x1234:16,r3l.b),@(0x3:2,er1)" +gdb_test "x" "or.b\t@\\(0x1234(:16|),r3l.b\\),@-er1" \ + "or.b @(0x1234:16,r3l.b),@-er1" +gdb_test "x" "or.b\t@\\(0x1234(:16|),r3l.b\\),@er1\\+" \ + "or.b @(0x1234:16,r3l.b),@er1+" +gdb_test "x" "or.b\t@\\(0x1234(:16|),r3l.b\\),@er1-" \ + "or.b @(0x1234:16,r3l.b),@er1-" +gdb_test "x" "or.b\t@\\(0x1234(:16|),r3l.b\\),@\\+er1" \ + "or.b @(0x1234:16,r3l.b),@+er1" +gdb_test "x" "or.b\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abc(:16|),er1\\)" \ + "or.b @(0x1234:16,r3l.b),@(0x9abc:16,er1)" +gdb_test "x" "or.b\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "or.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1)" +gdb_test "x" "or.b\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "or.b @(0x1234:16,r3l.b),@(0x9abc:16,r2l.b)" +gdb_test "x" "or.b\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abc(:16|),r2.w\\)" \ + "or.b @(0x1234:16,r3l.b),@(0x9abc:16,r2.w)" +gdb_test "x" "or.b\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abc(:16|),er2.l\\)" \ + "or.b @(0x1234:16,r3l.b),@(0x9abc:16,er2.l)" +gdb_test "x" "or.b\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "or.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "or.b\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "or.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "or.b\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "or.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "or.b\t@\\(0x1234(:16|),r3l.b\\),@0x9abc(:16|)" \ + "or.b @(0x1234:16,r3l.b),@0x9abc:16" +gdb_test "x" "or.b\t@\\(0x1234(:16|),r3l.b\\),@0x9abcdef0(:32|)" \ + "or.b @(0x1234:16,r3l.b),@0x9abcdef0:32" +gdb_test "x" "or.b\t@\\(0x1234(:16|),r3.w\\),@er1" \ + "or.b @(0x1234:16,r3.w),@er1" +gdb_test "x" "or.b\t@\\(0x1234(:16|),r3.w\\),@\\(0x3(:2|),er1\\)" \ + "or.b @(0x1234:16,r3.w),@(0x3:2,er1)" +gdb_test "x" "or.b\t@\\(0x1234(:16|),r3.w\\),@-er1" \ + "or.b @(0x1234:16,r3.w),@-er1" +gdb_test "x" "or.b\t@\\(0x1234(:16|),r3.w\\),@er1\\+" \ + "or.b @(0x1234:16,r3.w),@er1+" +gdb_test "x" "or.b\t@\\(0x1234(:16|),r3.w\\),@er1-" \ + "or.b @(0x1234:16,r3.w),@er1-" +gdb_test "x" "or.b\t@\\(0x1234(:16|),r3.w\\),@\\+er1" \ + "or.b @(0x1234:16,r3.w),@+er1" +gdb_test "x" "or.b\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abc(:16|),er1\\)" \ + "or.b @(0x1234:16,r3.w),@(0x9abc:16,er1)" +gdb_test "x" "or.b\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "or.b @(0x1234:16,r3.w),@(0x9abcdef0:32,er1)" +gdb_test "x" "or.b\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "or.b @(0x1234:16,r3.w),@(0x9abc:16,r2l.b)" +gdb_test "x" "or.b\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abc(:16|),r2.w\\)" \ + "or.b @(0x1234:16,r3.w),@(0x9abc:16,r2.w)" +gdb_test "x" "or.b\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abc(:16|),er2.l\\)" \ + "or.b @(0x1234:16,r3.w),@(0x9abc:16,er2.l)" +gdb_test "x" "or.b\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "or.b @(0x1234:16,r3.w),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "or.b\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "or.b @(0x1234:16,r3.w),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "or.b\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "or.b @(0x1234:16,r3.w),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "or.b\t@\\(0x1234(:16|),r3.w\\),@0x9abc(:16|)" \ + "or.b @(0x1234:16,r3.w),@0x9abc:16" +gdb_test "x" "or.b\t@\\(0x1234(:16|),r3.w\\),@0x9abcdef0(:32|)" \ + "or.b @(0x1234:16,r3.w),@0x9abcdef0:32" +gdb_test "x" "or.b\t@\\(0x1234(:16|),er3.l\\),@er1" \ + "or.b @(0x1234:16,er3.l),@er1" +gdb_test "x" "or.b\t@\\(0x1234(:16|),er3.l\\),@\\(0x3(:2|),er1\\)" \ + "or.b @(0x1234:16,er3.l),@(0x3:2,er1)" +gdb_test "x" "or.b\t@\\(0x1234(:16|),er3.l\\),@-er1" \ + "or.b @(0x1234:16,er3.l),@-er1" +gdb_test "x" "or.b\t@\\(0x1234(:16|),er3.l\\),@er1\\+" \ + "or.b @(0x1234:16,er3.l),@er1+" +gdb_test "x" "or.b\t@\\(0x1234(:16|),er3.l\\),@er1-" \ + "or.b @(0x1234:16,er3.l),@er1-" +gdb_test "x" "or.b\t@\\(0x1234(:16|),er3.l\\),@\\+er1" \ + "or.b @(0x1234:16,er3.l),@+er1" +gdb_test "x" "or.b\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abc(:16|),er1\\)" \ + "or.b @(0x1234:16,er3.l),@(0x9abc:16,er1)" +gdb_test "x" "or.b\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "or.b @(0x1234:16,er3.l),@(0x9abcdef0:32,er1)" +gdb_test "x" "or.b\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "or.b @(0x1234:16,er3.l),@(0x9abc:16,r2l.b)" +gdb_test "x" "or.b\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abc(:16|),r2.w\\)" \ + "or.b @(0x1234:16,er3.l),@(0x9abc:16,r2.w)" +gdb_test "x" "or.b\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abc(:16|),er2.l\\)" \ + "or.b @(0x1234:16,er3.l),@(0x9abc:16,er2.l)" +gdb_test "x" "or.b\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "or.b @(0x1234:16,er3.l),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "or.b\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "or.b @(0x1234:16,er3.l),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "or.b\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "or.b @(0x1234:16,er3.l),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "or.b\t@\\(0x1234(:16|),er3.l\\),@0x9abc(:16|)" \ + "or.b @(0x1234:16,er3.l),@0x9abc:16" +gdb_test "x" "or.b\t@\\(0x1234(:16|),er3.l\\),@0x9abcdef0(:32|)" \ + "or.b @(0x1234:16,er3.l),@0x9abcdef0:32" +gdb_test "x" "or.b\t@\\(0x12345678(:32|),r3l.b\\),@er1" \ + "or.b @(0x12345678:32,r3l.b),@er1" +gdb_test "x" "or.b\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x3(:2|),er1\\)" \ + "or.b @(0x12345678:32,r3l.b),@(0x3:2,er1)" +gdb_test "x" "or.b\t@\\(0x12345678(:32|),r3l.b\\),@-er1" \ + "or.b @(0x12345678:32,r3l.b),@-er1" +gdb_test "x" "or.b\t@\\(0x12345678(:32|),r3l.b\\),@er1\\+" \ + "or.b @(0x12345678:32,r3l.b),@er1+" +gdb_test "x" "or.b\t@\\(0x12345678(:32|),r3l.b\\),@er1-" \ + "or.b @(0x12345678:32,r3l.b),@er1-" +gdb_test "x" "or.b\t@\\(0x12345678(:32|),r3l.b\\),@\\+er1" \ + "or.b @(0x12345678:32,r3l.b),@+er1" +gdb_test "x" "or.b\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abc(:16|),er1\\)" \ + "or.b @(0x12345678:32,r3l.b),@(0x9abc:16,er1)" +gdb_test "x" "or.b\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "or.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1)" +gdb_test "x" "or.b\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "or.b @(0x12345678:32,r3l.b),@(0x9abc:16,r2l.b)" +gdb_test "x" "or.b\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abc(:16|),r2.w\\)" \ + "or.b @(0x12345678:32,r3l.b),@(0x9abc:16,r2.w)" +gdb_test "x" "or.b\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abc(:16|),er2.l\\)" \ + "or.b @(0x12345678:32,r3l.b),@(0x9abc:16,er2.l)" +gdb_test "x" "or.b\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "or.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "or.b\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "or.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "or.b\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "or.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "or.b\t@\\(0x12345678(:32|),r3l.b\\),@0x9abc(:16|)" \ + "or.b @(0x12345678:32,r3l.b),@0x9abc:16" +gdb_test "x" "or.b\t@\\(0x12345678(:32|),r3l.b\\),@0x9abcdef0(:32|)" \ + "or.b @(0x12345678:32,r3l.b),@0x9abcdef0:32" +gdb_test "x" "or.b\t@\\(0x12345678(:32|),r3.w\\),@er1" \ + "or.b @(0x12345678:32,r3.w),@er1" +gdb_test "x" "or.b\t@\\(0x12345678(:32|),r3.w\\),@\\(0x3(:2|),er1\\)" \ + "or.b @(0x12345678:32,r3.w),@(0x3:2,er1)" +gdb_test "x" "or.b\t@\\(0x12345678(:32|),r3.w\\),@-er1" \ + "or.b @(0x12345678:32,r3.w),@-er1" +gdb_test "x" "or.b\t@\\(0x12345678(:32|),r3.w\\),@er1\\+" \ + "or.b @(0x12345678:32,r3.w),@er1+" +gdb_test "x" "or.b\t@\\(0x12345678(:32|),r3.w\\),@er1-" \ + "or.b @(0x12345678:32,r3.w),@er1-" +gdb_test "x" "or.b\t@\\(0x12345678(:32|),r3.w\\),@\\+er1" \ + "or.b @(0x12345678:32,r3.w),@+er1" +gdb_test "x" "or.b\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abc(:16|),er1\\)" \ + "or.b @(0x12345678:32,r3.w),@(0x9abc:16,er1)" +gdb_test "x" "or.b\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "or.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1)" +gdb_test "x" "or.b\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "or.b @(0x12345678:32,r3.w),@(0x9abc:16,r2l.b)" +gdb_test "x" "or.b\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abc(:16|),r2.w\\)" \ + "or.b @(0x12345678:32,r3.w),@(0x9abc:16,r2.w)" +gdb_test "x" "or.b\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abc(:16|),er2.l\\)" \ + "or.b @(0x12345678:32,r3.w),@(0x9abc:16,er2.l)" +gdb_test "x" "or.b\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "or.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "or.b\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "or.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "or.b\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "or.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "or.b\t@\\(0x12345678(:32|),r3.w\\),@0x9abc(:16|)" \ + "or.b @(0x12345678:32,r3.w),@0x9abc:16" +gdb_test "x" "or.b\t@\\(0x12345678(:32|),r3.w\\),@0x9abcdef0(:32|)" \ + "or.b @(0x12345678:32,r3.w),@0x9abcdef0:32" +gdb_test "x" "or.b\t@\\(0x12345678(:32|),er3.l\\),@er1" \ + "or.b @(0x12345678:32,er3.l),@er1" +gdb_test "x" "or.b\t@\\(0x12345678(:32|),er3.l\\),@\\(0x3(:2|),er1\\)" \ + "or.b @(0x12345678:32,er3.l),@(0x3:2,er1)" +gdb_test "x" "or.b\t@\\(0x12345678(:32|),er3.l\\),@-er1" \ + "or.b @(0x12345678:32,er3.l),@-er1" +gdb_test "x" "or.b\t@\\(0x12345678(:32|),er3.l\\),@er1\\+" \ + "or.b @(0x12345678:32,er3.l),@er1+" +gdb_test "x" "or.b\t@\\(0x12345678(:32|),er3.l\\),@er1-" \ + "or.b @(0x12345678:32,er3.l),@er1-" +gdb_test "x" "or.b\t@\\(0x12345678(:32|),er3.l\\),@\\+er1" \ + "or.b @(0x12345678:32,er3.l),@+er1" +gdb_test "x" "or.b\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abc(:16|),er1\\)" \ + "or.b @(0x12345678:32,er3.l),@(0x9abc:16,er1)" +gdb_test "x" "or.b\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "or.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1)" +gdb_test "x" "or.b\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "or.b @(0x12345678:32,er3.l),@(0x9abc:16,r2l.b)" +gdb_test "x" "or.b\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abc(:16|),r2.w\\)" \ + "or.b @(0x12345678:32,er3.l),@(0x9abc:16,r2.w)" +gdb_test "x" "or.b\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abc(:16|),er2.l\\)" \ + "or.b @(0x12345678:32,er3.l),@(0x9abc:16,er2.l)" +gdb_test "x" "or.b\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "or.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "or.b\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "or.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "or.b\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "or.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "or.b\t@\\(0x12345678(:32|),er3.l\\),@0x9abc(:16|)" \ + "or.b @(0x12345678:32,er3.l),@0x9abc:16" +gdb_test "x" "or.b\t@\\(0x12345678(:32|),er3.l\\),@0x9abcdef0(:32|)" \ + "or.b @(0x12345678:32,er3.l),@0x9abcdef0:32" +gdb_test "x" "or.b\t@0x1234(:16|),@er1" \ + "or.b @0x1234:16,@er1" +gdb_test "x" "or.b\t@0x1234(:16|),@\\(0x3(:2|),er1\\)" \ + "or.b @0x1234:16,@(0x3:2,er1)" +gdb_test "x" "or.b\t@0x1234(:16|),@-er1" \ + "or.b @0x1234:16,@-er1" +gdb_test "x" "or.b\t@0x1234(:16|),@er1\\+" \ + "or.b @0x1234:16,@er1+" +gdb_test "x" "or.b\t@0x1234(:16|),@er1-" \ + "or.b @0x1234:16,@er1-" +gdb_test "x" "or.b\t@0x1234(:16|),@\\+er1" \ + "or.b @0x1234:16,@+er1" +gdb_test "x" "or.b\t@0x1234(:16|),@\\(0x9abc(:16|),er1\\)" \ + "or.b @0x1234:16,@(0x9abc:16,er1)" +gdb_test "x" "or.b\t@0x1234(:16|),@\\(0x9abcdef0(:32|),er1\\)" \ + "or.b @0x1234:16,@(0x9abcdef0:32,er1)" +gdb_test "x" "or.b\t@0x1234(:16|),@\\(0x9abc(:16|),r2l.b\\)" \ + "or.b @0x1234:16,@(0x9abc:16,r2l.b)" +gdb_test "x" "or.b\t@0x1234(:16|),@\\(0x9abc(:16|),r2.w\\)" \ + "or.b @0x1234:16,@(0x9abc:16,r2.w)" +gdb_test "x" "or.b\t@0x1234(:16|),@\\(0x9abc(:16|),er2.l\\)" \ + "or.b @0x1234:16,@(0x9abc:16,er2.l)" +gdb_test "x" "or.b\t@0x1234(:16|),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "or.b @0x1234:16,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "or.b\t@0x1234(:16|),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "or.b @0x1234:16,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "or.b\t@0x1234(:16|),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "or.b @0x1234:16,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "or.b\t@0x1234(:16|),@0x9abc(:16|)" \ + "or.b @0x1234:16,@0x9abc:16" +gdb_test "x" "or.b\t@0x1234(:16|),@0x9abcdef0(:32|)" \ + "or.b @0x1234:16,@0x9abcdef0:32" +gdb_test "x" "or.b\t@0x12345678(:32|),@er1" \ + "or.b @0x12345678:32,@er1" +gdb_test "x" "or.b\t@0x12345678(:32|),@\\(0x3(:2|),er1\\)" \ + "or.b @0x12345678:32,@(0x3:2,er1)" +gdb_test "x" "or.b\t@0x12345678(:32|),@-er1" \ + "or.b @0x12345678:32,@-er1" +gdb_test "x" "or.b\t@0x12345678(:32|),@er1\\+" \ + "or.b @0x12345678:32,@er1+" +gdb_test "x" "or.b\t@0x12345678(:32|),@er1-" \ + "or.b @0x12345678:32,@er1-" +gdb_test "x" "or.b\t@0x12345678(:32|),@\\+er1" \ + "or.b @0x12345678:32,@+er1" +gdb_test "x" "or.b\t@0x12345678(:32|),@\\(0x9abc(:16|),er1\\)" \ + "or.b @0x12345678:32,@(0x9abc:16,er1)" +gdb_test "x" "or.b\t@0x12345678(:32|),@\\(0x9abcdef0(:32|),er1\\)" \ + "or.b @0x12345678:32,@(0x9abcdef0:32,er1)" +gdb_test "x" "or.b\t@0x12345678(:32|),@\\(0x9abc(:16|),r2l.b\\)" \ + "or.b @0x12345678:32,@(0x9abc:16,r2l.b)" +gdb_test "x" "or.b\t@0x12345678(:32|),@\\(0x9abc(:16|),r2.w\\)" \ + "or.b @0x12345678:32,@(0x9abc:16,r2.w)" +gdb_test "x" "or.b\t@0x12345678(:32|),@\\(0x9abc(:16|),er2.l\\)" \ + "or.b @0x12345678:32,@(0x9abc:16,er2.l)" +gdb_test "x" "or.b\t@0x12345678(:32|),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "or.b @0x12345678:32,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "or.b\t@0x12345678(:32|),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "or.b @0x12345678:32,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "or.b\t@0x12345678(:32|),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "or.b @0x12345678:32,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "or.b\t@0x12345678(:32|),@0x9abc(:16|)" \ + "or.b @0x12345678:32,@0x9abc:16" +gdb_test "x" "or.b\t@0x12345678(:32|),@0x9abcdef0(:32|)" \ + "or.b @0x12345678:32,@0x9abcdef0:32" +gdb_test "x" "or.w\t#0x1234(:16|),r1" \ + "or.w #0x1234:16,r1" +gdb_test "x" "or.w\t#0x1234(:16|),@er1" \ + "or.w #0x1234:16,@er1" +gdb_test "x" "or.w\t#0x1234(:16|),@\\(0x6(:2|),er1\\)" \ + "or.w #0x1234:16,@(0x6:2,er1)" +gdb_test "x" "or.w\t#0x1234(:16|),@er1\\+" \ + "or.w #0x1234:16,@er1+" +gdb_test "x" "or.w\t#0x1234(:16|),@-er1" \ + "or.w #0x1234:16,@-er1" +gdb_test "x" "or.w\t#0x1234(:16|),@\\+er1" \ + "or.w #0x1234:16,@+er1" +gdb_test "x" "or.w\t#0x1234(:16|),@er1-" \ + "or.w #0x1234:16,@er1-" +gdb_test "x" "or.w\t#0x1234(:16|),@\\(0x9abc(:16|),er1\\)" \ + "or.w #0x1234:16,@(0x9abc:16,er1)" +gdb_test "x" "or.w\t#0x1234(:16|),@\\(0x9abcdef0(:32|),er1\\)" \ + "or.w #0x1234:16,@(0x9abcdef0:32,er1)" +gdb_test "x" "or.w\t#0x1234(:16|),@\\(0x9abc(:16|),r2l.b\\)" \ + "or.w #0x1234:16,@(0x9abc:16,r2l.b)" +gdb_test "x" "or.w\t#0x1234(:16|),@\\(0x9abc(:16|),r2.w\\)" \ + "or.w #0x1234:16,@(0x9abc:16,r2.w)" +gdb_test "x" "or.w\t#0x1234(:16|),@\\(0x9abc(:16|),er2.l\\)" \ + "or.w #0x1234:16,@(0x9abc:16,er2.l)" +gdb_test "x" "or.w\t#0x1234(:16|),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "or.w #0x1234:16,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "or.w\t#0x1234(:16|),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "or.w #0x1234:16,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "or.w\t#0x1234(:16|),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "or.w #0x1234:16,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "or.w\t#0x1234(:16|),@0x9abc(:16|)" \ + "or.w #0x1234:16,@0x9abc:16" +gdb_test "x" "or.w\t#0x1234(:16|),@0x9abcdef0(:32|)" \ + "or.w #0x1234:16,@0x9abcdef0:32" +gdb_test "x" "or.w\tr3,r1" \ + "or.w r3,r1" +gdb_test "x" "or.w\tr3,@er1" \ + "or.w r3,@er1" +gdb_test "x" "or.w\tr3,@\\(0x6(:2|),er1\\)" \ + "or.w r3,@(0x6:2,er1)" +gdb_test "x" "or.w\tr3,@er1\\+" \ + "or.w r3,@er1+" +gdb_test "x" "or.w\tr3,@-er1" \ + "or.w r3,@-er1" +gdb_test "x" "or.w\tr3,@\\+er1" \ + "or.w r3,@+er1" +gdb_test "x" "or.w\tr3,@er1-" \ + "or.w r3,@er1-" +gdb_test "x" "or.w\tr3,@\\(0x1234(:16|),er1\\)" \ + "or.w r3,@(0x1234:16,er1)" +gdb_test "x" "or.w\tr3,@\\(0x12345678(:32|),er1\\)" \ + "or.w r3,@(0x12345678:32,er1)" +gdb_test "x" "or.w\tr3,@\\(0x1234(:16|),r2l.b\\)" \ + "or.w r3,@(0x1234:16,r2l.b)" +gdb_test "x" "or.w\tr3,@\\(0x1234(:16|),r2.w\\)" \ + "or.w r3,@(0x1234:16,r2.w)" +gdb_test "x" "or.w\tr3,@\\(0x1234(:16|),er2.l\\)" \ + "or.w r3,@(0x1234:16,er2.l)" +gdb_test "x" "or.w\tr3,@\\(0x12345678(:32|),r2l.b\\)" \ + "or.w r3,@(0x12345678:32,r2l.b)" +gdb_test "x" "or.w\tr3,@\\(0x12345678(:32|),r2.w\\)" \ + "or.w r3,@(0x12345678:32,r2.w)" +gdb_test "x" "or.w\tr3,@\\(0x12345678(:32|),er2.l\\)" \ + "or.w r3,@(0x12345678:32,er2.l)" +gdb_test "x" "or.w\tr3,@0x1234(:16|)" \ + "or.w r3,@0x1234:16" +gdb_test "x" "or.w\tr3,@0x12345678(:32|)" \ + "or.w r3,@0x12345678:32" +gdb_test "x" "or.w\t@er3,r1" \ + "or.w @er3,r1" +gdb_test "x" "or.w\t@\\(0x6(:2|),er3\\),r1" \ + "or.w @(0x6:2,er3),r1" +gdb_test "x" "or.w\t@er3\\+,r1" \ + "or.w @er3+,r1" +gdb_test "x" "or.w\t@-er3,r1" \ + "or.w @-er3,r1" +gdb_test "x" "or.w\t@\\+er3,r1" \ + "or.w @+er3,r1" +gdb_test "x" "or.w\t@er3-,r1" \ + "or.w @er3-,r1" +gdb_test "x" "or.w\t@\\(0x1234(:16|),er1\\),r1" \ + "or.w @(0x1234:16,er1),r1" +gdb_test "x" "or.w\t@\\(0x12345678(:32|),er1\\),r1" \ + "or.w @(0x12345678:32,er1),r1" +gdb_test "x" "or.w\t@\\(0x1234(:16|),r2l.b\\),r1" \ + "or.w @(0x1234:16,r2l.b),r1" +gdb_test "x" "or.w\t@\\(0x1234(:16|),r2.w\\),r1" \ + "or.w @(0x1234:16,r2.w),r1" +gdb_test "x" "or.w\t@\\(0x1234(:16|),er2.l\\),r1" \ + "or.w @(0x1234:16,er2.l),r1" +gdb_test "x" "or.w\t@\\(0x12345678(:32|),r2l.b\\),r1" \ + "or.w @(0x12345678:32,r2l.b),r1" +gdb_test "x" "or.w\t@\\(0x12345678(:32|),r2.w\\),r1" \ + "or.w @(0x12345678:32,r2.w),r1" +gdb_test "x" "or.w\t@\\(0x12345678(:32|),er2.l\\),r1" \ + "or.w @(0x12345678:32,er2.l),r1" +gdb_test "x" "or.w\t@0x1234(:16|),r1" \ + "or.w @0x1234:16,r1" +gdb_test "x" "or.w\t@0x12345678(:32|),r1" \ + "or.w @0x12345678:32,r1" +gdb_test "x" "or.w\t@er3,@er1" \ + "or.w @er3,@er1" +gdb_test "x" "or.w\t@er3,@\\(0x6(:2|),er1\\)" \ + "or.w @er3,@(0x6:2,er1)" +gdb_test "x" "or.w\t@er3,@-er1" \ + "or.w @er3,@-er1" +gdb_test "x" "or.w\t@er3,@er1\\+" \ + "or.w @er3,@er1+" +gdb_test "x" "or.w\t@er3,@er1-" \ + "or.w @er3,@er1-" +gdb_test "x" "or.w\t@er3,@\\+er1" \ + "or.w @er3,@+er1" +gdb_test "x" "or.w\t@er3,@\\(0x9abc(:16|),er1\\)" \ + "or.w @er3,@(0x9abc:16,er1)" +gdb_test "x" "or.w\t@er3,@\\(0x9abcdef0(:32|),er1\\)" \ + "or.w @er3,@(0x9abcdef0:32,er1)" +gdb_test "x" "or.w\t@er3,@\\(0x9abc(:16|),r2l.b\\)" \ + "or.w @er3,@(0x9abc:16,r2l.b)" +gdb_test "x" "or.w\t@er3,@\\(0x9abc(:16|),r2.w\\)" \ + "or.w @er3,@(0x9abc:16,r2.w)" +gdb_test "x" "or.w\t@er3,@\\(0x9abc(:16|),er2.l\\)" \ + "or.w @er3,@(0x9abc:16,er2.l)" +gdb_test "x" "or.w\t@er3,@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "or.w @er3,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "or.w\t@er3,@\\(0x9abcdef0(:32|),r2.w\\)" \ + "or.w @er3,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "or.w\t@er3,@\\(0x9abcdef0(:32|),er2.l\\)" \ + "or.w @er3,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "or.w\t@er3,@0x9abc(:16|)" \ + "or.w @er3,@0x9abc:16" +gdb_test "x" "or.w\t@er3,@0x9abcdef0(:32|)" \ + "or.w @er3,@0x9abcdef0:32" +gdb_test "x" "or.w\t@-er3,@er1" \ + "or.w @-er3,@er1" +gdb_test "x" "or.w\t@-er3,@\\(0x6(:2|),er1\\)" \ + "or.w @-er3,@(0x6:2,er1)" +gdb_test "x" "or.w\t@-er3,@-er1" \ + "or.w @-er3,@-er1" +gdb_test "x" "or.w\t@-er3,@er1\\+" \ + "or.w @-er3,@er1+" +gdb_test "x" "or.w\t@-er3,@er1-" \ + "or.w @-er3,@er1-" +gdb_test "x" "or.w\t@-er3,@\\+er1" \ + "or.w @-er3,@+er1" +gdb_test "x" "or.w\t@-er3,@\\(0x9abc(:16|),er1\\)" \ + "or.w @-er3,@(0x9abc:16,er1)" +gdb_test "x" "or.w\t@-er3,@\\(0x9abcdef0(:32|),er1\\)" \ + "or.w @-er3,@(0x9abcdef0:32,er1)" +gdb_test "x" "or.w\t@-er3,@\\(0x9abc(:16|),r2l.b\\)" \ + "or.w @-er3,@(0x9abc:16,r2l.b)" +gdb_test "x" "or.w\t@-er3,@\\(0x9abc(:16|),r2.w\\)" \ + "or.w @-er3,@(0x9abc:16,r2.w)" +gdb_test "x" "or.w\t@-er3,@\\(0x9abc(:16|),er2.l\\)" \ + "or.w @-er3,@(0x9abc:16,er2.l)" +gdb_test "x" "or.w\t@-er3,@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "or.w @-er3,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "or.w\t@-er3,@\\(0x9abcdef0(:32|),r2.w\\)" \ + "or.w @-er3,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "or.w\t@-er3,@\\(0x9abcdef0(:32|),er2.l\\)" \ + "or.w @-er3,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "or.w\t@-er3,@0x9abc(:16|)" \ + "or.w @-er3,@0x9abc:16" +gdb_test "x" "or.w\t@-er3,@0x9abcdef0(:32|)" \ + "or.w @-er3,@0x9abcdef0:32" +gdb_test "x" "or.w\t@er3\\+,@er1" \ + "or.w @er3+,@er1" +gdb_test "x" "or.w\t@er3\\+,@\\(0x6(:2|),er1\\)" \ + "or.w @er3+,@(0x6:2,er1)" +gdb_test "x" "or.w\t@er3\\+,@-er1" \ + "or.w @er3+,@-er1" +gdb_test "x" "or.w\t@er3\\+,@er1\\+" \ + "or.w @er3+,@er1+" +gdb_test "x" "or.w\t@er3\\+,@er1-" \ + "or.w @er3+,@er1-" +gdb_test "x" "or.w\t@er3\\+,@\\+er1" \ + "or.w @er3+,@+er1" +gdb_test "x" "or.w\t@er3\\+,@\\(0x9abc(:16|),er1\\)" \ + "or.w @er3+,@(0x9abc:16,er1)" +gdb_test "x" "or.w\t@er3\\+,@\\(0x9abcdef0(:32|),er1\\)" \ + "or.w @er3+,@(0x9abcdef0:32,er1)" +gdb_test "x" "or.w\t@er3\\+,@\\(0x9abc(:16|),r2l.b\\)" \ + "or.w @er3+,@(0x9abc:16,r2l.b)" +gdb_test "x" "or.w\t@er3\\+,@\\(0x9abc(:16|),r2.w\\)" \ + "or.w @er3+,@(0x9abc:16,r2.w)" +gdb_test "x" "or.w\t@er3\\+,@\\(0x9abc(:16|),er2.l\\)" \ + "or.w @er3+,@(0x9abc:16,er2.l)" +gdb_test "x" "or.w\t@er3\\+,@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "or.w @er3+,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "or.w\t@er3\\+,@\\(0x9abcdef0(:32|),r2.w\\)" \ + "or.w @er3+,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "or.w\t@er3\\+,@\\(0x9abcdef0(:32|),er2.l\\)" \ + "or.w @er3+,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "or.w\t@er3\\+,@0x9abc(:16|)" \ + "or.w @er3+,@0x9abc:16" +gdb_test "x" "or.w\t@er3\\+,@0x9abcdef0(:32|)" \ + "or.w @er3+,@0x9abcdef0:32" +gdb_test "x" "or.w\t@er3-,@er1" \ + "or.w @er3-,@er1" +gdb_test "x" "or.w\t@er3-,@\\(0x6(:2|),er1\\)" \ + "or.w @er3-,@(0x6:2,er1)" +gdb_test "x" "or.w\t@er3-,@-er1" \ + "or.w @er3-,@-er1" +gdb_test "x" "or.w\t@er3-,@er1\\+" \ + "or.w @er3-,@er1+" +gdb_test "x" "or.w\t@er3-,@er1-" \ + "or.w @er3-,@er1-" +gdb_test "x" "or.w\t@er3-,@\\+er1" \ + "or.w @er3-,@+er1" +gdb_test "x" "or.w\t@er3-,@\\(0x9abc(:16|),er1\\)" \ + "or.w @er3-,@(0x9abc:16,er1)" +gdb_test "x" "or.w\t@er3-,@\\(0x9abcdef0(:32|),er1\\)" \ + "or.w @er3-,@(0x9abcdef0:32,er1)" +gdb_test "x" "or.w\t@er3-,@\\(0x9abc(:16|),r2l.b\\)" \ + "or.w @er3-,@(0x9abc:16,r2l.b)" +gdb_test "x" "or.w\t@er3-,@\\(0x9abc(:16|),r2.w\\)" \ + "or.w @er3-,@(0x9abc:16,r2.w)" +gdb_test "x" "or.w\t@er3-,@\\(0x9abc(:16|),er2.l\\)" \ + "or.w @er3-,@(0x9abc:16,er2.l)" +gdb_test "x" "or.w\t@er3-,@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "or.w @er3-,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "or.w\t@er3-,@\\(0x9abcdef0(:32|),r2.w\\)" \ + "or.w @er3-,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "or.w\t@er3-,@\\(0x9abcdef0(:32|),er2.l\\)" \ + "or.w @er3-,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "or.w\t@er3-,@0x9abc(:16|)" \ + "or.w @er3-,@0x9abc:16" +gdb_test "x" "or.w\t@er3-,@0x9abcdef0(:32|)" \ + "or.w @er3-,@0x9abcdef0:32" +gdb_test "x" "or.w\t@\\+er3,@er1" \ + "or.w @+er3,@er1" +gdb_test "x" "or.w\t@\\+er3,@\\(0x6(:2|),er1\\)" \ + "or.w @+er3,@(0x6:2,er1)" +gdb_test "x" "or.w\t@\\+er3,@-er1" \ + "or.w @+er3,@-er1" +gdb_test "x" "or.w\t@\\+er3,@er1\\+" \ + "or.w @+er3,@er1+" +gdb_test "x" "or.w\t@\\+er3,@er1-" \ + "or.w @+er3,@er1-" +gdb_test "x" "or.w\t@\\+er3,@\\+er1" \ + "or.w @+er3,@+er1" +gdb_test "x" "or.w\t@\\+er3,@\\(0x9abc(:16|),er1\\)" \ + "or.w @+er3,@(0x9abc:16,er1)" +gdb_test "x" "or.w\t@\\+er3,@\\(0x9abcdef0(:32|),er1\\)" \ + "or.w @+er3,@(0x9abcdef0:32,er1)" +gdb_test "x" "or.w\t@\\+er3,@\\(0x9abc(:16|),r2l.b\\)" \ + "or.w @+er3,@(0x9abc:16,r2l.b)" +gdb_test "x" "or.w\t@\\+er3,@\\(0x9abc(:16|),r2.w\\)" \ + "or.w @+er3,@(0x9abc:16,r2.w)" +gdb_test "x" "or.w\t@\\+er3,@\\(0x9abc(:16|),er2.l\\)" \ + "or.w @+er3,@(0x9abc:16,er2.l)" +gdb_test "x" "or.w\t@\\+er3,@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "or.w @+er3,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "or.w\t@\\+er3,@\\(0x9abcdef0(:32|),r2.w\\)" \ + "or.w @+er3,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "or.w\t@\\+er3,@\\(0x9abcdef0(:32|),er2.l\\)" \ + "or.w @+er3,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "or.w\t@\\+er3,@0x9abc(:16|)" \ + "or.w @+er3,@0x9abc:16" +gdb_test "x" "or.w\t@\\+er3,@0x9abcdef0(:32|)" \ + "or.w @+er3,@0x9abcdef0:32" +gdb_test "x" "or.w\t@\\(0x1234(:16|),er3\\),@er1" \ + "or.w @(0x1234:16,er3),@er1" +gdb_test "x" "or.w\t@\\(0x1234(:16|),er3\\),@\\(0x6(:2|),er1\\)" \ + "or.w @(0x1234:16,er3),@(0x6:2,er1)" +gdb_test "x" "or.w\t@\\(0x1234(:16|),er3\\),@-er1" \ + "or.w @(0x1234:16,er3),@-er1" +gdb_test "x" "or.w\t@\\(0x1234(:16|),er3\\),@er1\\+" \ + "or.w @(0x1234:16,er3),@er1+" +gdb_test "x" "or.w\t@\\(0x1234(:16|),er3\\),@er1-" \ + "or.w @(0x1234:16,er3),@er1-" +gdb_test "x" "or.w\t@\\(0x1234(:16|),er3\\),@\\+er1" \ + "or.w @(0x1234:16,er3),@+er1" +gdb_test "x" "or.w\t@\\(0x1234(:16|),er3\\),@\\(0x9abc(:16|),er1\\)" \ + "or.w @(0x1234:16,er3),@(0x9abc:16,er1)" +gdb_test "x" "or.w\t@\\(0x1234(:16|),er3\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "or.w @(0x1234:16,er3),@(0x9abcdef0:32,er1)" +gdb_test "x" "or.w\t@\\(0x1234(:16|),er3\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "or.w @(0x1234:16,er3),@(0x9abc:16,r2l.b)" +gdb_test "x" "or.w\t@\\(0x1234(:16|),er3\\),@\\(0x9abc(:16|),r2.w\\)" \ + "or.w @(0x1234:16,er3),@(0x9abc:16,r2.w)" +gdb_test "x" "or.w\t@\\(0x1234(:16|),er3\\),@\\(0x9abc(:16|),er2.l\\)" \ + "or.w @(0x1234:16,er3),@(0x9abc:16,er2.l)" +gdb_test "x" "or.w\t@\\(0x1234(:16|),er3\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "or.w @(0x1234:16,er3),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "or.w\t@\\(0x1234(:16|),er3\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "or.w @(0x1234:16,er3),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "or.w\t@\\(0x1234(:16|),er3\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "or.w @(0x1234:16,er3),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "or.w\t@\\(0x1234(:16|),er3\\),@0x9abc(:16|)" \ + "or.w @(0x1234:16,er3),@0x9abc:16" +gdb_test "x" "or.w\t@\\(0x1234(:16|),er3\\),@0x9abcdef0(:32|)" \ + "or.w @(0x1234:16,er3),@0x9abcdef0:32" +gdb_test "x" "or.w\t@\\(0x12345678(:32|),er3\\),@er1" \ + "or.w @(0x12345678:32,er3),@er1" +gdb_test "x" "or.w\t@\\(0x12345678(:32|),er3\\),@\\(0x6(:2|),er1\\)" \ + "or.w @(0x12345678:32,er3),@(0x6:2,er1)" +gdb_test "x" "or.w\t@\\(0x12345678(:32|),er3\\),@-er1" \ + "or.w @(0x12345678:32,er3),@-er1" +gdb_test "x" "or.w\t@\\(0x12345678(:32|),er3\\),@er1\\+" \ + "or.w @(0x12345678:32,er3),@er1+" +gdb_test "x" "or.w\t@\\(0x12345678(:32|),er3\\),@er1-" \ + "or.w @(0x12345678:32,er3),@er1-" +gdb_test "x" "or.w\t@\\(0x12345678(:32|),er3\\),@\\+er1" \ + "or.w @(0x12345678:32,er3),@+er1" +gdb_test "x" "or.w\t@\\(0x12345678(:32|),er3\\),@\\(0x9abc(:16|),er1\\)" \ + "or.w @(0x12345678:32,er3),@(0x9abc:16,er1)" +gdb_test "x" "or.w\t@\\(0x12345678(:32|),er3\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "or.w @(0x12345678:32,er3),@(0x9abcdef0:32,er1)" +gdb_test "x" "or.w\t@\\(0x12345678(:32|),er3\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "or.w @(0x12345678:32,er3),@(0x9abc:16,r2l.b)" +gdb_test "x" "or.w\t@\\(0x12345678(:32|),er3\\),@\\(0x9abc(:16|),r2.w\\)" \ + "or.w @(0x12345678:32,er3),@(0x9abc:16,r2.w)" +gdb_test "x" "or.w\t@\\(0x12345678(:32|),er3\\),@\\(0x9abc(:16|),er2.l\\)" \ + "or.w @(0x12345678:32,er3),@(0x9abc:16,er2.l)" +gdb_test "x" "or.w\t@\\(0x12345678(:32|),er3\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "or.w @(0x12345678:32,er3),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "or.w\t@\\(0x12345678(:32|),er3\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "or.w @(0x12345678:32,er3),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "or.w\t@\\(0x12345678(:32|),er3\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "or.w @(0x12345678:32,er3),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "or.w\t@\\(0x12345678(:32|),er3\\),@0x9abc(:16|)" \ + "or.w @(0x12345678:32,er3),@0x9abc:16" +gdb_test "x" "or.w\t@\\(0x12345678(:32|),er3\\),@0x9abcdef0(:32|)" \ + "or.w @(0x12345678:32,er3),@0x9abcdef0:32" +gdb_test "x" "or.w\t@\\(0x1234(:16|),r3l.b\\),@er1" \ + "or.w @(0x1234:16,r3l.b),@er1" +gdb_test "x" "or.w\t@\\(0x1234(:16|),r3l.b\\),@\\(0x6(:2|),er1\\)" \ + "or.w @(0x1234:16,r3l.b),@(0x6:2,er1)" +gdb_test "x" "or.w\t@\\(0x1234(:16|),r3l.b\\),@-er1" \ + "or.w @(0x1234:16,r3l.b),@-er1" +gdb_test "x" "or.w\t@\\(0x1234(:16|),r3l.b\\),@er1\\+" \ + "or.w @(0x1234:16,r3l.b),@er1+" +gdb_test "x" "or.w\t@\\(0x1234(:16|),r3l.b\\),@er1-" \ + "or.w @(0x1234:16,r3l.b),@er1-" +gdb_test "x" "or.w\t@\\(0x1234(:16|),r3l.b\\),@\\+er1" \ + "or.w @(0x1234:16,r3l.b),@+er1" +gdb_test "x" "or.w\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abc(:16|),er1\\)" \ + "or.w @(0x1234:16,r3l.b),@(0x9abc:16,er1)" +gdb_test "x" "or.w\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "or.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1)" +gdb_test "x" "or.w\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "or.w @(0x1234:16,r3l.b),@(0x9abc:16,r2l.b)" +gdb_test "x" "or.w\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abc(:16|),r2.w\\)" \ + "or.w @(0x1234:16,r3l.b),@(0x9abc:16,r2.w)" +gdb_test "x" "or.w\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abc(:16|),er2.l\\)" \ + "or.w @(0x1234:16,r3l.b),@(0x9abc:16,er2.l)" +gdb_test "x" "or.w\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "or.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "or.w\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "or.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "or.w\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "or.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "or.w\t@\\(0x1234(:16|),r3l.b\\),@0x9abc(:16|)" \ + "or.w @(0x1234:16,r3l.b),@0x9abc:16" +gdb_test "x" "or.w\t@\\(0x1234(:16|),r3l.b\\),@0x9abcdef0(:32|)" \ + "or.w @(0x1234:16,r3l.b),@0x9abcdef0:32" +gdb_test "x" "or.w\t@\\(0x1234(:16|),r3.w\\),@er1" \ + "or.w @(0x1234:16,r3.w),@er1" +gdb_test "x" "or.w\t@\\(0x1234(:16|),r3.w\\),@\\(0x6(:2|),er1\\)" \ + "or.w @(0x1234:16,r3.w),@(0x6:2,er1)" +gdb_test "x" "or.w\t@\\(0x1234(:16|),r3.w\\),@-er1" \ + "or.w @(0x1234:16,r3.w),@-er1" +gdb_test "x" "or.w\t@\\(0x1234(:16|),r3.w\\),@er1\\+" \ + "or.w @(0x1234:16,r3.w),@er1+" +gdb_test "x" "or.w\t@\\(0x1234(:16|),r3.w\\),@er1-" \ + "or.w @(0x1234:16,r3.w),@er1-" +gdb_test "x" "or.w\t@\\(0x1234(:16|),r3.w\\),@\\+er1" \ + "or.w @(0x1234:16,r3.w),@+er1" +gdb_test "x" "or.w\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abc(:16|),er1\\)" \ + "or.w @(0x1234:16,r3.w),@(0x9abc:16,er1)" +gdb_test "x" "or.w\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "or.w @(0x1234:16,r3.w),@(0x9abcdef0:32,er1)" +gdb_test "x" "or.w\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "or.w @(0x1234:16,r3.w),@(0x9abc:16,r2l.b)" +gdb_test "x" "or.w\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abc(:16|),r2.w\\)" \ + "or.w @(0x1234:16,r3.w),@(0x9abc:16,r2.w)" +gdb_test "x" "or.w\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abc(:16|),er2.l\\)" \ + "or.w @(0x1234:16,r3.w),@(0x9abc:16,er2.l)" +gdb_test "x" "or.w\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "or.w @(0x1234:16,r3.w),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "or.w\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "or.w @(0x1234:16,r3.w),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "or.w\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "or.w @(0x1234:16,r3.w),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "or.w\t@\\(0x1234(:16|),r3.w\\),@0x9abc(:16|)" \ + "or.w @(0x1234:16,r3.w),@0x9abc:16" +gdb_test "x" "or.w\t@\\(0x1234(:16|),r3.w\\),@0x9abcdef0(:32|)" \ + "or.w @(0x1234:16,r3.w),@0x9abcdef0:32" +gdb_test "x" "or.w\t@\\(0x1234(:16|),er3.l\\),@er1" \ + "or.w @(0x1234:16,er3.l),@er1" +gdb_test "x" "or.w\t@\\(0x1234(:16|),er3.l\\),@\\(0x6(:2|),er1\\)" \ + "or.w @(0x1234:16,er3.l),@(0x6:2,er1)" +gdb_test "x" "or.w\t@\\(0x1234(:16|),er3.l\\),@-er1" \ + "or.w @(0x1234:16,er3.l),@-er1" +gdb_test "x" "or.w\t@\\(0x1234(:16|),er3.l\\),@er1\\+" \ + "or.w @(0x1234:16,er3.l),@er1+" +gdb_test "x" "or.w\t@\\(0x1234(:16|),er3.l\\),@er1-" \ + "or.w @(0x1234:16,er3.l),@er1-" +gdb_test "x" "or.w\t@\\(0x1234(:16|),er3.l\\),@\\+er1" \ + "or.w @(0x1234:16,er3.l),@+er1" +gdb_test "x" "or.w\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abc(:16|),er1\\)" \ + "or.w @(0x1234:16,er3.l),@(0x9abc:16,er1)" +gdb_test "x" "or.w\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "or.w @(0x1234:16,er3.l),@(0x9abcdef0:32,er1)" +gdb_test "x" "or.w\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "or.w @(0x1234:16,er3.l),@(0x9abc:16,r2l.b)" +gdb_test "x" "or.w\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abc(:16|),r2.w\\)" \ + "or.w @(0x1234:16,er3.l),@(0x9abc:16,r2.w)" +gdb_test "x" "or.w\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abc(:16|),er2.l\\)" \ + "or.w @(0x1234:16,er3.l),@(0x9abc:16,er2.l)" +gdb_test "x" "or.w\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "or.w @(0x1234:16,er3.l),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "or.w\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "or.w @(0x1234:16,er3.l),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "or.w\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "or.w @(0x1234:16,er3.l),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "or.w\t@\\(0x1234(:16|),er3.l\\),@0x9abc(:16|)" \ + "or.w @(0x1234:16,er3.l),@0x9abc:16" +gdb_test "x" "or.w\t@\\(0x1234(:16|),er3.l\\),@0x9abcdef0(:32|)" \ + "or.w @(0x1234:16,er3.l),@0x9abcdef0:32" +gdb_test "x" "or.w\t@\\(0x12345678(:32|),r3l.b\\),@er1" \ + "or.w @(0x12345678:32,r3l.b),@er1" +gdb_test "x" "or.w\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x6(:2|),er1\\)" \ + "or.w @(0x12345678:32,r3l.b),@(0x6:2,er1)" +gdb_test "x" "or.w\t@\\(0x12345678(:32|),r3l.b\\),@-er1" \ + "or.w @(0x12345678:32,r3l.b),@-er1" +gdb_test "x" "or.w\t@\\(0x12345678(:32|),r3l.b\\),@er1\\+" \ + "or.w @(0x12345678:32,r3l.b),@er1+" +gdb_test "x" "or.w\t@\\(0x12345678(:32|),r3l.b\\),@er1-" \ + "or.w @(0x12345678:32,r3l.b),@er1-" +gdb_test "x" "or.w\t@\\(0x12345678(:32|),r3l.b\\),@\\+er1" \ + "or.w @(0x12345678:32,r3l.b),@+er1" +gdb_test "x" "or.w\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abc(:16|),er1\\)" \ + "or.w @(0x12345678:32,r3l.b),@(0x9abc:16,er1)" +gdb_test "x" "or.w\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "or.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1)" +gdb_test "x" "or.w\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "or.w @(0x12345678:32,r3l.b),@(0x9abc:16,r2l.b)" +gdb_test "x" "or.w\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abc(:16|),r2.w\\)" \ + "or.w @(0x12345678:32,r3l.b),@(0x9abc:16,r2.w)" +gdb_test "x" "or.w\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abc(:16|),er2.l\\)" \ + "or.w @(0x12345678:32,r3l.b),@(0x9abc:16,er2.l)" +gdb_test "x" "or.w\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "or.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "or.w\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "or.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "or.w\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "or.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "or.w\t@\\(0x12345678(:32|),r3l.b\\),@0x9abc(:16|)" \ + "or.w @(0x12345678:32,r3l.b),@0x9abc:16" +gdb_test "x" "or.w\t@\\(0x12345678(:32|),r3l.b\\),@0x9abcdef0(:32|)" \ + "or.w @(0x12345678:32,r3l.b),@0x9abcdef0:32" +gdb_test "x" "or.w\t@\\(0x12345678(:32|),r3.w\\),@er1" \ + "or.w @(0x12345678:32,r3.w),@er1" +gdb_test "x" "or.w\t@\\(0x12345678(:32|),r3.w\\),@\\(0x6(:2|),er1\\)" \ + "or.w @(0x12345678:32,r3.w),@(0x6:2,er1)" +gdb_test "x" "or.w\t@\\(0x12345678(:32|),r3.w\\),@-er1" \ + "or.w @(0x12345678:32,r3.w),@-er1" +gdb_test "x" "or.w\t@\\(0x12345678(:32|),r3.w\\),@er1\\+" \ + "or.w @(0x12345678:32,r3.w),@er1+" +gdb_test "x" "or.w\t@\\(0x12345678(:32|),r3.w\\),@er1-" \ + "or.w @(0x12345678:32,r3.w),@er1-" +gdb_test "x" "or.w\t@\\(0x12345678(:32|),r3.w\\),@\\+er1" \ + "or.w @(0x12345678:32,r3.w),@+er1" +gdb_test "x" "or.w\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abc(:16|),er1\\)" \ + "or.w @(0x12345678:32,r3.w),@(0x9abc:16,er1)" +gdb_test "x" "or.w\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "or.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1)" +gdb_test "x" "or.w\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "or.w @(0x12345678:32,r3.w),@(0x9abc:16,r2l.b)" +gdb_test "x" "or.w\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abc(:16|),r2.w\\)" \ + "or.w @(0x12345678:32,r3.w),@(0x9abc:16,r2.w)" +gdb_test "x" "or.w\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abc(:16|),er2.l\\)" \ + "or.w @(0x12345678:32,r3.w),@(0x9abc:16,er2.l)" +gdb_test "x" "or.w\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "or.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "or.w\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "or.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "or.w\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "or.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "or.w\t@\\(0x12345678(:32|),r3.w\\),@0x9abc(:16|)" \ + "or.w @(0x12345678:32,r3.w),@0x9abc:16" +gdb_test "x" "or.w\t@\\(0x12345678(:32|),r3.w\\),@0x9abcdef0(:32|)" \ + "or.w @(0x12345678:32,r3.w),@0x9abcdef0:32" +gdb_test "x" "or.w\t@\\(0x12345678(:32|),er3.l\\),@er1" \ + "or.w @(0x12345678:32,er3.l),@er1" +gdb_test "x" "or.w\t@\\(0x12345678(:32|),er3.l\\),@\\(0x6(:2|),er1\\)" \ + "or.w @(0x12345678:32,er3.l),@(0x6:2,er1)" +gdb_test "x" "or.w\t@\\(0x12345678(:32|),er3.l\\),@-er1" \ + "or.w @(0x12345678:32,er3.l),@-er1" +gdb_test "x" "or.w\t@\\(0x12345678(:32|),er3.l\\),@er1\\+" \ + "or.w @(0x12345678:32,er3.l),@er1+" +gdb_test "x" "or.w\t@\\(0x12345678(:32|),er3.l\\),@er1-" \ + "or.w @(0x12345678:32,er3.l),@er1-" +gdb_test "x" "or.w\t@\\(0x12345678(:32|),er3.l\\),@\\+er1" \ + "or.w @(0x12345678:32,er3.l),@+er1" +gdb_test "x" "or.w\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abc(:16|),er1\\)" \ + "or.w @(0x12345678:32,er3.l),@(0x9abc:16,er1)" +gdb_test "x" "or.w\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "or.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1)" +gdb_test "x" "or.w\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "or.w @(0x12345678:32,er3.l),@(0x9abc:16,r2l.b)" +gdb_test "x" "or.w\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abc(:16|),r2.w\\)" \ + "or.w @(0x12345678:32,er3.l),@(0x9abc:16,r2.w)" +gdb_test "x" "or.w\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abc(:16|),er2.l\\)" \ + "or.w @(0x12345678:32,er3.l),@(0x9abc:16,er2.l)" +gdb_test "x" "or.w\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "or.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "or.w\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "or.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "or.w\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "or.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "or.w\t@\\(0x12345678(:32|),er3.l\\),@0x9abc(:16|)" \ + "or.w @(0x12345678:32,er3.l),@0x9abc:16" +gdb_test "x" "or.w\t@\\(0x12345678(:32|),er3.l\\),@0x9abcdef0(:32|)" \ + "or.w @(0x12345678:32,er3.l),@0x9abcdef0:32" +gdb_test "x" "or.w\t@0x1234(:16|),@er1" \ + "or.w @0x1234:16,@er1" +gdb_test "x" "or.w\t@0x1234(:16|),@\\(0x6(:2|),er1\\)" \ + "or.w @0x1234:16,@(0x6:2,er1)" +gdb_test "x" "or.w\t@0x1234(:16|),@-er1" \ + "or.w @0x1234:16,@-er1" +gdb_test "x" "or.w\t@0x1234(:16|),@er1\\+" \ + "or.w @0x1234:16,@er1+" +gdb_test "x" "or.w\t@0x1234(:16|),@er1-" \ + "or.w @0x1234:16,@er1-" +gdb_test "x" "or.w\t@0x1234(:16|),@\\+er1" \ + "or.w @0x1234:16,@+er1" +gdb_test "x" "or.w\t@0x1234(:16|),@\\(0x9abc(:16|),er1\\)" \ + "or.w @0x1234:16,@(0x9abc:16,er1)" +gdb_test "x" "or.w\t@0x1234(:16|),@\\(0x9abcdef0(:32|),er1\\)" \ + "or.w @0x1234:16,@(0x9abcdef0:32,er1)" +gdb_test "x" "or.w\t@0x1234(:16|),@\\(0x9abc(:16|),r2l.b\\)" \ + "or.w @0x1234:16,@(0x9abc:16,r2l.b)" +gdb_test "x" "or.w\t@0x1234(:16|),@\\(0x9abc(:16|),r2.w\\)" \ + "or.w @0x1234:16,@(0x9abc:16,r2.w)" +gdb_test "x" "or.w\t@0x1234(:16|),@\\(0x9abc(:16|),er2.l\\)" \ + "or.w @0x1234:16,@(0x9abc:16,er2.l)" +gdb_test "x" "or.w\t@0x1234(:16|),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "or.w @0x1234:16,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "or.w\t@0x1234(:16|),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "or.w @0x1234:16,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "or.w\t@0x1234(:16|),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "or.w @0x1234:16,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "or.w\t@0x1234(:16|),@0x9abc(:16|)" \ + "or.w @0x1234:16,@0x9abc:16" +gdb_test "x" "or.w\t@0x1234(:16|),@0x9abcdef0(:32|)" \ + "or.w @0x1234:16,@0x9abcdef0:32" +gdb_test "x" "or.w\t@0x12345678(:32|),@er1" \ + "or.w @0x12345678:32,@er1" +gdb_test "x" "or.w\t@0x12345678(:32|),@\\(0x6(:2|),er1\\)" \ + "or.w @0x12345678:32,@(0x6:2,er1)" +gdb_test "x" "or.w\t@0x12345678(:32|),@-er1" \ + "or.w @0x12345678:32,@-er1" +gdb_test "x" "or.w\t@0x12345678(:32|),@er1\\+" \ + "or.w @0x12345678:32,@er1+" +gdb_test "x" "or.w\t@0x12345678(:32|),@er1-" \ + "or.w @0x12345678:32,@er1-" +gdb_test "x" "or.w\t@0x12345678(:32|),@\\+er1" \ + "or.w @0x12345678:32,@+er1" +gdb_test "x" "or.w\t@0x12345678(:32|),@\\(0x9abc(:16|),er1\\)" \ + "or.w @0x12345678:32,@(0x9abc:16,er1)" +gdb_test "x" "or.w\t@0x12345678(:32|),@\\(0x9abcdef0(:32|),er1\\)" \ + "or.w @0x12345678:32,@(0x9abcdef0:32,er1)" +gdb_test "x" "or.w\t@0x12345678(:32|),@\\(0x9abc(:16|),r2l.b\\)" \ + "or.w @0x12345678:32,@(0x9abc:16,r2l.b)" +gdb_test "x" "or.w\t@0x12345678(:32|),@\\(0x9abc(:16|),r2.w\\)" \ + "or.w @0x12345678:32,@(0x9abc:16,r2.w)" +gdb_test "x" "or.w\t@0x12345678(:32|),@\\(0x9abc(:16|),er2.l\\)" \ + "or.w @0x12345678:32,@(0x9abc:16,er2.l)" +gdb_test "x" "or.w\t@0x12345678(:32|),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "or.w @0x12345678:32,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "or.w\t@0x12345678(:32|),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "or.w @0x12345678:32,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "or.w\t@0x12345678(:32|),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "or.w @0x12345678:32,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "or.w\t@0x12345678(:32|),@0x9abc(:16|)" \ + "or.w @0x12345678:32,@0x9abc:16" +gdb_test "x" "or.w\t@0x12345678(:32|),@0x9abcdef0(:32|)" \ + "or.w @0x12345678:32,@0x9abcdef0:32" +gdb_test "x" "or.l\t#0x12345678(:32|),er1" \ + "or.l #0x12345678:32,er1" +gdb_test "x" "or.l\t#0x1234(:16|),er1" \ + "or.l #0x1234:16,er1" +gdb_test "x" "or.l\t#0x12345678(:32|),@er1" \ + "or.l #0x12345678:32,@er1" +gdb_test "x" "or.l\t#0x12345678(:32|),@\\(0xc(:2|),er1\\)" \ + "or.l #0x12345678:32,@(0xc:2,er1)" +gdb_test "x" "or.l\t#0x12345678(:32|),@er1\\+" \ + "or.l #0x12345678:32,@er1+" +gdb_test "x" "or.l\t#0x12345678(:32|),@-er1" \ + "or.l #0x12345678:32,@-er1" +gdb_test "x" "or.l\t#0x12345678(:32|),@\\+er1" \ + "or.l #0x12345678:32,@+er1" +gdb_test "x" "or.l\t#0x12345678(:32|),@er1-" \ + "or.l #0x12345678:32,@er1-" +gdb_test "x" "or.l\t#0x12345678(:32|),@\\(0x9abc(:16|),er1\\)" \ + "or.l #0x12345678:32,@(0x9abc:16,er1)" +gdb_test "x" "or.l\t#0x12345678(:32|),@\\(0x9abcdef0(:32|),er1\\)" \ + "or.l #0x12345678:32,@(0x9abcdef0:32,er1)" +gdb_test "x" "or.l\t#0x12345678(:32|),@\\(0x9abc(:16|),r2l.b\\)" \ + "or.l #0x12345678:32,@(0x9abc:16,r2l.b)" +gdb_test "x" "or.l\t#0x12345678(:32|),@\\(0x9abc(:16|),r2.w\\)" \ + "or.l #0x12345678:32,@(0x9abc:16,r2.w)" +gdb_test "x" "or.l\t#0x12345678(:32|),@\\(0x9abc(:16|),er2.l\\)" \ + "or.l #0x12345678:32,@(0x9abc:16,er2.l)" +gdb_test "x" "or.l\t#0x12345678(:32|),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "or.l #0x12345678:32,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "or.l\t#0x12345678(:32|),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "or.l #0x12345678:32,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "or.l\t#0x12345678(:32|),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "or.l #0x12345678:32,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "or.l\t#0x12345678(:32|),@0x9abc(:16|)" \ + "or.l #0x12345678:32,@0x9abc:16" +gdb_test "x" "or.l\t#0x12345678(:32|),@0x9abcdef0(:32|)" \ + "or.l #0x12345678:32,@0x9abcdef0:32" +gdb_test "x" "or.l\t#0x1234(:16|),@er1" \ + "or.l #0x1234:16,@er1" +gdb_test "x" "or.l\t#0x1234(:16|),@\\(0xc(:2|),er1\\)" \ + "or.l #0x1234:16,@(0xc:2,er1)" +gdb_test "x" "or.l\t#0x1234(:16|),@er1\\+" \ + "or.l #0x1234:16,@er1+" +gdb_test "x" "or.l\t#0x1234(:16|),@-er1" \ + "or.l #0x1234:16,@-er1" +gdb_test "x" "or.l\t#0x1234(:16|),@\\+er1" \ + "or.l #0x1234:16,@+er1" +gdb_test "x" "or.l\t#0x1234(:16|),@er1-" \ + "or.l #0x1234:16,@er1-" +gdb_test "x" "or.l\t#0x1234(:16|),@\\(0x9abc(:16|),er1\\)" \ + "or.l #0x1234:16,@(0x9abc:16,er1)" +gdb_test "x" "or.l\t#0x1234(:16|),@\\(0x9abcdef0(:32|),er1\\)" \ + "or.l #0x1234:16,@(0x9abcdef0:32,er1)" +gdb_test "x" "or.l\t#0x1234(:16|),@\\(0x9abc(:16|),r2l.b\\)" \ + "or.l #0x1234:16,@(0x9abc:16,r2l.b)" +gdb_test "x" "or.l\t#0x1234(:16|),@\\(0x9abc(:16|),r2.w\\)" \ + "or.l #0x1234:16,@(0x9abc:16,r2.w)" +gdb_test "x" "or.l\t#0x1234(:16|),@\\(0x9abc(:16|),er2.l\\)" \ + "or.l #0x1234:16,@(0x9abc:16,er2.l)" +gdb_test "x" "or.l\t#0x1234(:16|),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "or.l #0x1234:16,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "or.l\t#0x1234(:16|),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "or.l #0x1234:16,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "or.l\t#0x1234(:16|),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "or.l #0x1234:16,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "or.l\t#0x1234(:16|),@0x9abc(:16|)" \ + "or.l #0x1234:16,@0x9abc:16" +gdb_test "x" "or.l\t#0x1234(:16|),@0x9abcdef0(:32|)" \ + "or.l #0x1234:16,@0x9abcdef0:32" +gdb_test "x" "or.l\ter3,er1" \ + "or.l er3,er1" +gdb_test "x" "or.l\ter3,@er1" \ + "or.l er3,@er1" +gdb_test "x" "or.l\ter3,@\\(0xc(:2|),er1\\)" \ + "or.l er3,@(0xc:2,er1)" +gdb_test "x" "or.l\ter3,@er1\\+" \ + "or.l er3,@er1+" +gdb_test "x" "or.l\ter3,@-er1" \ + "or.l er3,@-er1" +gdb_test "x" "or.l\ter3,@\\+er1" \ + "or.l er3,@+er1" +gdb_test "x" "or.l\ter3,@er1-" \ + "or.l er3,@er1-" +gdb_test "x" "or.l\ter3,@\\(0x1234(:16|),er1\\)" \ + "or.l er3,@(0x1234:16,er1)" +gdb_test "x" "or.l\ter3,@\\(0x12345678(:32|),er1\\)" \ + "or.l er3,@(0x12345678:32,er1)" +gdb_test "x" "or.l\ter3,@\\(0x1234(:16|),r2l.b\\)" \ + "or.l er3,@(0x1234:16,r2l.b)" +gdb_test "x" "or.l\ter3,@\\(0x1234(:16|),r2.w\\)" \ + "or.l er3,@(0x1234:16,r2.w)" +gdb_test "x" "or.l\ter3,@\\(0x1234(:16|),er2.l\\)" \ + "or.l er3,@(0x1234:16,er2.l)" +gdb_test "x" "or.l\ter3,@\\(0x12345678(:32|),r2l.b\\)" \ + "or.l er3,@(0x12345678:32,r2l.b)" +gdb_test "x" "or.l\ter3,@\\(0x12345678(:32|),r2.w\\)" \ + "or.l er3,@(0x12345678:32,r2.w)" +gdb_test "x" "or.l\ter3,@\\(0x12345678(:32|),er2.l\\)" \ + "or.l er3,@(0x12345678:32,er2.l)" +gdb_test "x" "or.l\ter3,@0x1234(:16|)" \ + "or.l er3,@0x1234:16" +gdb_test "x" "or.l\ter3,@0x12345678(:32|)" \ + "or.l er3,@0x12345678:32" +gdb_test "x" "or.l\t@er3,er1" \ + "or.l @er3,er1" +gdb_test "x" "or.l\t@\\(0xc(:2|),er3\\),er1" \ + "or.l @(0xc:2,er3),er1" +gdb_test "x" "or.l\t@er3\\+,er1" \ + "or.l @er3+,er1" +gdb_test "x" "or.l\t@-er3,er1" \ + "or.l @-er3,er1" +gdb_test "x" "or.l\t@\\+er3,er1" \ + "or.l @+er3,er1" +gdb_test "x" "or.l\t@er3-,er1" \ + "or.l @er3-,er1" +gdb_test "x" "or.l\t@\\(0x1234(:16|),er1\\),er1" \ + "or.l @(0x1234:16,er1),er1" +gdb_test "x" "or.l\t@\\(0x12345678(:32|),er1\\),er1" \ + "or.l @(0x12345678:32,er1),er1" +gdb_test "x" "or.l\t@\\(0x1234(:16|),r2l.b\\),er1" \ + "or.l @(0x1234:16,r2l.b),er1" +gdb_test "x" "or.l\t@\\(0x1234(:16|),r2.w\\),er1" \ + "or.l @(0x1234:16,r2.w),er1" +gdb_test "x" "or.l\t@\\(0x1234(:16|),er2.l\\),er1" \ + "or.l @(0x1234:16,er2.l),er1" +gdb_test "x" "or.l\t@\\(0x12345678(:32|),r2l.b\\),er1" \ + "or.l @(0x12345678:32,r2l.b),er1" +gdb_test "x" "or.l\t@\\(0x12345678(:32|),r2.w\\),er1" \ + "or.l @(0x12345678:32,r2.w),er1" +gdb_test "x" "or.l\t@\\(0x12345678(:32|),er2.l\\),er1" \ + "or.l @(0x12345678:32,er2.l),er1" +gdb_test "x" "or.l\t@0x1234(:16|),er1" \ + "or.l @0x1234:16,er1" +gdb_test "x" "or.l\t@0x12345678(:32|),er1" \ + "or.l @0x12345678:32,er1" +gdb_test "x" "or.l\t@er3,@er1" \ + "or.l @er3,@er1" +gdb_test "x" "or.l\t@er3,@\\(0xc(:2|),er1\\)" \ + "or.l @er3,@(0xc:2,er1)" +gdb_test "x" "or.l\t@er3,@-er1" \ + "or.l @er3,@-er1" +gdb_test "x" "or.l\t@er3,@er1\\+" \ + "or.l @er3,@er1+" +gdb_test "x" "or.l\t@er3,@er1-" \ + "or.l @er3,@er1-" +gdb_test "x" "or.l\t@er3,@\\+er1" \ + "or.l @er3,@+er1" +gdb_test "x" "or.l\t@er3,@\\(0x9abc(:16|),er1\\)" \ + "or.l @er3,@(0x9abc:16,er1)" +gdb_test "x" "or.l\t@er3,@\\(0x9abcdef0(:32|),er1\\)" \ + "or.l @er3,@(0x9abcdef0:32,er1)" +gdb_test "x" "or.l\t@er3,@\\(0x9abc(:16|),r2l.b\\)" \ + "or.l @er3,@(0x9abc:16,r2l.b)" +gdb_test "x" "or.l\t@er3,@\\(0x9abc(:16|),r2.w\\)" \ + "or.l @er3,@(0x9abc:16,r2.w)" +gdb_test "x" "or.l\t@er3,@\\(0x9abc(:16|),er2.l\\)" \ + "or.l @er3,@(0x9abc:16,er2.l)" +gdb_test "x" "or.l\t@er3,@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "or.l @er3,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "or.l\t@er3,@\\(0x9abcdef0(:32|),r2.w\\)" \ + "or.l @er3,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "or.l\t@er3,@\\(0x9abcdef0(:32|),er2.l\\)" \ + "or.l @er3,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "or.l\t@er3,@0x9abc(:16|)" \ + "or.l @er3,@0x9abc:16" +gdb_test "x" "or.l\t@er3,@0x9abcdef0(:32|)" \ + "or.l @er3,@0x9abcdef0:32" +gdb_test "x" "or.l\t@\\(0xc(:2|),er3\\),@er1" \ + "or.l @(0xc:2,er3),@er1" +gdb_test "x" "or.l\t@\\(0xc(:2|),er3\\),@\\(0xc(:2|),er1\\)" \ + "or.l @(0xc:2,er3),@(0xc:2,er1)" +gdb_test "x" "or.l\t@\\(0xc(:2|),er3\\),@-er1" \ + "or.l @(0xc:2,er3),@-er1" +gdb_test "x" "or.l\t@\\(0xc(:2|),er3\\),@er1\\+" \ + "or.l @(0xc:2,er3),@er1+" +gdb_test "x" "or.l\t@\\(0xc(:2|),er3\\),@er1-" \ + "or.l @(0xc:2,er3),@er1-" +gdb_test "x" "or.l\t@\\(0xc(:2|),er3\\),@\\+er1" \ + "or.l @(0xc:2,er3),@+er1" +gdb_test "x" "or.l\t@\\(0xc(:2|),er3\\),@\\(0x9abc(:16|),er1\\)" \ + "or.l @(0xc:2,er3),@(0x9abc:16,er1)" +gdb_test "x" "or.l\t@\\(0xc(:2|),er3\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "or.l @(0xc:2,er3),@(0x9abcdef0:32,er1)" +gdb_test "x" "or.l\t@\\(0xc(:2|),er3\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "or.l @(0xc:2,er3),@(0x9abc:16,r2l.b)" +gdb_test "x" "or.l\t@\\(0xc(:2|),er3\\),@\\(0x9abc(:16|),r2.w\\)" \ + "or.l @(0xc:2,er3),@(0x9abc:16,r2.w)" +gdb_test "x" "or.l\t@\\(0xc(:2|),er3\\),@\\(0x9abc(:16|),er2.l\\)" \ + "or.l @(0xc:2,er3),@(0x9abc:16,er2.l)" +gdb_test "x" "or.l\t@\\(0xc(:2|),er3\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "or.l @(0xc:2,er3),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "or.l\t@\\(0xc(:2|),er3\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "or.l @(0xc:2,er3),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "or.l\t@\\(0xc(:2|),er3\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "or.l @(0xc:2,er3),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "or.l\t@\\(0xc(:2|),er3\\),@0x9abc(:16|)" \ + "or.l @(0xc:2,er3),@0x9abc:16" +gdb_test "x" "or.l\t@\\(0xc(:2|),er3\\),@0x9abcdef0(:32|)" \ + "or.l @(0xc:2,er3),@0x9abcdef0:32" +gdb_test "x" "or.l\t@-er3,@er1" \ + "or.l @-er3,@er1" +gdb_test "x" "or.l\t@-er3,@\\(0xc(:2|),er1\\)" \ + "or.l @-er3,@(0xc:2,er1)" +gdb_test "x" "or.l\t@-er3,@-er1" \ + "or.l @-er3,@-er1" +gdb_test "x" "or.l\t@-er3,@er1\\+" \ + "or.l @-er3,@er1+" +gdb_test "x" "or.l\t@-er3,@er1-" \ + "or.l @-er3,@er1-" +gdb_test "x" "or.l\t@-er3,@\\+er1" \ + "or.l @-er3,@+er1" +gdb_test "x" "or.l\t@-er3,@\\(0x9abc(:16|),er1\\)" \ + "or.l @-er3,@(0x9abc:16,er1)" +gdb_test "x" "or.l\t@-er3,@\\(0x9abcdef0(:32|),er1\\)" \ + "or.l @-er3,@(0x9abcdef0:32,er1)" +gdb_test "x" "or.l\t@-er3,@\\(0x9abc(:16|),r2l.b\\)" \ + "or.l @-er3,@(0x9abc:16,r2l.b)" +gdb_test "x" "or.l\t@-er3,@\\(0x9abc(:16|),r2.w\\)" \ + "or.l @-er3,@(0x9abc:16,r2.w)" +gdb_test "x" "or.l\t@-er3,@\\(0x9abc(:16|),er2.l\\)" \ + "or.l @-er3,@(0x9abc:16,er2.l)" +gdb_test "x" "or.l\t@-er3,@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "or.l @-er3,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "or.l\t@-er3,@\\(0x9abcdef0(:32|),r2.w\\)" \ + "or.l @-er3,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "or.l\t@-er3,@\\(0x9abcdef0(:32|),er2.l\\)" \ + "or.l @-er3,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "or.l\t@-er3,@0x9abc(:16|)" \ + "or.l @-er3,@0x9abc:16" +gdb_test "x" "or.l\t@-er3,@0x9abcdef0(:32|)" \ + "or.l @-er3,@0x9abcdef0:32" +gdb_test "x" "or.l\t@er3\\+,@er1" \ + "or.l @er3+,@er1" +gdb_test "x" "or.l\t@er3\\+,@\\(0xc(:2|),er1\\)" \ + "or.l @er3+,@(0xc:2,er1)" +gdb_test "x" "or.l\t@er3\\+,@-er1" \ + "or.l @er3+,@-er1" +gdb_test "x" "or.l\t@er3\\+,@er1\\+" \ + "or.l @er3+,@er1+" +gdb_test "x" "or.l\t@er3\\+,@er1-" \ + "or.l @er3+,@er1-" +gdb_test "x" "or.l\t@er3\\+,@\\+er1" \ + "or.l @er3+,@+er1" +gdb_test "x" "or.l\t@er3\\+,@\\(0x9abc(:16|),er1\\)" \ + "or.l @er3+,@(0x9abc:16,er1)" +gdb_test "x" "or.l\t@er3\\+,@\\(0x9abcdef0(:32|),er1\\)" \ + "or.l @er3+,@(0x9abcdef0:32,er1)" +gdb_test "x" "or.l\t@er3\\+,@\\(0x9abc(:16|),r2l.b\\)" \ + "or.l @er3+,@(0x9abc:16,r2l.b)" +gdb_test "x" "or.l\t@er3\\+,@\\(0x9abc(:16|),r2.w\\)" \ + "or.l @er3+,@(0x9abc:16,r2.w)" +gdb_test "x" "or.l\t@er3\\+,@\\(0x9abc(:16|),er2.l\\)" \ + "or.l @er3+,@(0x9abc:16,er2.l)" +gdb_test "x" "or.l\t@er3\\+,@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "or.l @er3+,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "or.l\t@er3\\+,@\\(0x9abcdef0(:32|),r2.w\\)" \ + "or.l @er3+,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "or.l\t@er3\\+,@\\(0x9abcdef0(:32|),er2.l\\)" \ + "or.l @er3+,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "or.l\t@er3\\+,@0x9abc(:16|)" \ + "or.l @er3+,@0x9abc:16" +gdb_test "x" "or.l\t@er3\\+,@0x9abcdef0(:32|)" \ + "or.l @er3+,@0x9abcdef0:32" +gdb_test "x" "or.l\t@er3-,@er1" \ + "or.l @er3-,@er1" +gdb_test "x" "or.l\t@er3-,@\\(0xc(:2|),er1\\)" \ + "or.l @er3-,@(0xc:2,er1)" +gdb_test "x" "or.l\t@er3-,@-er1" \ + "or.l @er3-,@-er1" +gdb_test "x" "or.l\t@er3-,@er1\\+" \ + "or.l @er3-,@er1+" +gdb_test "x" "or.l\t@er3-,@er1-" \ + "or.l @er3-,@er1-" +gdb_test "x" "or.l\t@er3-,@\\+er1" \ + "or.l @er3-,@+er1" +gdb_test "x" "or.l\t@er3-,@\\(0x9abc(:16|),er1\\)" \ + "or.l @er3-,@(0x9abc:16,er1)" +gdb_test "x" "or.l\t@er3-,@\\(0x9abcdef0(:32|),er1\\)" \ + "or.l @er3-,@(0x9abcdef0:32,er1)" +gdb_test "x" "or.l\t@er3-,@\\(0x9abc(:16|),r2l.b\\)" \ + "or.l @er3-,@(0x9abc:16,r2l.b)" +gdb_test "x" "or.l\t@er3-,@\\(0x9abc(:16|),r2.w\\)" \ + "or.l @er3-,@(0x9abc:16,r2.w)" +gdb_test "x" "or.l\t@er3-,@\\(0x9abc(:16|),er2.l\\)" \ + "or.l @er3-,@(0x9abc:16,er2.l)" +gdb_test "x" "or.l\t@er3-,@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "or.l @er3-,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "or.l\t@er3-,@\\(0x9abcdef0(:32|),r2.w\\)" \ + "or.l @er3-,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "or.l\t@er3-,@\\(0x9abcdef0(:32|),er2.l\\)" \ + "or.l @er3-,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "or.l\t@er3-,@0x9abc(:16|)" \ + "or.l @er3-,@0x9abc:16" +gdb_test "x" "or.l\t@er3-,@0x9abcdef0(:32|)" \ + "or.l @er3-,@0x9abcdef0:32" +gdb_test "x" "or.l\t@\\+er3,@er1" \ + "or.l @+er3,@er1" +gdb_test "x" "or.l\t@\\+er3,@\\(0xc(:2|),er1\\)" \ + "or.l @+er3,@(0xc:2,er1)" +gdb_test "x" "or.l\t@\\+er3,@-er1" \ + "or.l @+er3,@-er1" +gdb_test "x" "or.l\t@\\+er3,@er1\\+" \ + "or.l @+er3,@er1+" +gdb_test "x" "or.l\t@\\+er3,@er1-" \ + "or.l @+er3,@er1-" +gdb_test "x" "or.l\t@\\+er3,@\\+er1" \ + "or.l @+er3,@+er1" +gdb_test "x" "or.l\t@\\+er3,@\\(0x9abc(:16|),er1\\)" \ + "or.l @+er3,@(0x9abc:16,er1)" +gdb_test "x" "or.l\t@\\+er3,@\\(0x9abcdef0(:32|),er1\\)" \ + "or.l @+er3,@(0x9abcdef0:32,er1)" +gdb_test "x" "or.l\t@\\+er3,@\\(0x9abc(:16|),r2l.b\\)" \ + "or.l @+er3,@(0x9abc:16,r2l.b)" +gdb_test "x" "or.l\t@\\+er3,@\\(0x9abc(:16|),r2.w\\)" \ + "or.l @+er3,@(0x9abc:16,r2.w)" +gdb_test "x" "or.l\t@\\+er3,@\\(0x9abc(:16|),er2.l\\)" \ + "or.l @+er3,@(0x9abc:16,er2.l)" +gdb_test "x" "or.l\t@\\+er3,@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "or.l @+er3,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "or.l\t@\\+er3,@\\(0x9abcdef0(:32|),r2.w\\)" \ + "or.l @+er3,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "or.l\t@\\+er3,@\\(0x9abcdef0(:32|),er2.l\\)" \ + "or.l @+er3,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "or.l\t@\\+er3,@0x9abc(:16|)" \ + "or.l @+er3,@0x9abc:16" +gdb_test "x" "or.l\t@\\+er3,@0x9abcdef0(:32|)" \ + "or.l @+er3,@0x9abcdef0:32" +gdb_test "x" "or.l\t@\\(0x1234(:16|),er3\\),@er1" \ + "or.l @(0x1234:16,er3),@er1" +gdb_test "x" "or.l\t@\\(0x1234(:16|),er3\\),@\\(0xc(:2|),er1\\)" \ + "or.l @(0x1234:16,er3),@(0xc:2,er1)" +gdb_test "x" "or.l\t@\\(0x1234(:16|),er3\\),@-er1" \ + "or.l @(0x1234:16,er3),@-er1" +gdb_test "x" "or.l\t@\\(0x1234(:16|),er3\\),@er1\\+" \ + "or.l @(0x1234:16,er3),@er1+" +gdb_test "x" "or.l\t@\\(0x1234(:16|),er3\\),@er1-" \ + "or.l @(0x1234:16,er3),@er1-" +gdb_test "x" "or.l\t@\\(0x1234(:16|),er3\\),@\\+er1" \ + "or.l @(0x1234:16,er3),@+er1" +gdb_test "x" "or.l\t@\\(0x1234(:16|),er3\\),@\\(0x9abc(:16|),er1\\)" \ + "or.l @(0x1234:16,er3),@(0x9abc:16,er1)" +gdb_test "x" "or.l\t@\\(0x1234(:16|),er3\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "or.l @(0x1234:16,er3),@(0x9abcdef0:32,er1)" +gdb_test "x" "or.l\t@\\(0x1234(:16|),er3\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "or.l @(0x1234:16,er3),@(0x9abc:16,r2l.b)" +gdb_test "x" "or.l\t@\\(0x1234(:16|),er3\\),@\\(0x9abc(:16|),r2.w\\)" \ + "or.l @(0x1234:16,er3),@(0x9abc:16,r2.w)" +gdb_test "x" "or.l\t@\\(0x1234(:16|),er3\\),@\\(0x9abc(:16|),er2.l\\)" \ + "or.l @(0x1234:16,er3),@(0x9abc:16,er2.l)" +gdb_test "x" "or.l\t@\\(0x1234(:16|),er3\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "or.l @(0x1234:16,er3),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "or.l\t@\\(0x1234(:16|),er3\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "or.l @(0x1234:16,er3),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "or.l\t@\\(0x1234(:16|),er3\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "or.l @(0x1234:16,er3),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "or.l\t@\\(0x1234(:16|),er3\\),@0x9abc(:16|)" \ + "or.l @(0x1234:16,er3),@0x9abc:16" +gdb_test "x" "or.l\t@\\(0x1234(:16|),er3\\),@0x9abcdef0(:32|)" \ + "or.l @(0x1234:16,er3),@0x9abcdef0:32" +gdb_test "x" "or.l\t@\\(0x12345678(:32|),er3\\),@er1" \ + "or.l @(0x12345678:32,er3),@er1" +gdb_test "x" "or.l\t@\\(0x12345678(:32|),er3\\),@\\(0xc(:2|),er1\\)" \ + "or.l @(0x12345678:32,er3),@(0xc:2,er1)" +gdb_test "x" "or.l\t@\\(0x12345678(:32|),er3\\),@-er1" \ + "or.l @(0x12345678:32,er3),@-er1" +gdb_test "x" "or.l\t@\\(0x12345678(:32|),er3\\),@er1\\+" \ + "or.l @(0x12345678:32,er3),@er1+" +gdb_test "x" "or.l\t@\\(0x12345678(:32|),er3\\),@er1-" \ + "or.l @(0x12345678:32,er3),@er1-" +gdb_test "x" "or.l\t@\\(0x12345678(:32|),er3\\),@\\+er1" \ + "or.l @(0x12345678:32,er3),@+er1" +gdb_test "x" "or.l\t@\\(0x12345678(:32|),er3\\),@\\(0x9abc(:16|),er1\\)" \ + "or.l @(0x12345678:32,er3),@(0x9abc:16,er1)" +gdb_test "x" "or.l\t@\\(0x12345678(:32|),er3\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "or.l @(0x12345678:32,er3),@(0x9abcdef0:32,er1)" +gdb_test "x" "or.l\t@\\(0x12345678(:32|),er3\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "or.l @(0x12345678:32,er3),@(0x9abc:16,r2l.b)" +gdb_test "x" "or.l\t@\\(0x12345678(:32|),er3\\),@\\(0x9abc(:16|),r2.w\\)" \ + "or.l @(0x12345678:32,er3),@(0x9abc:16,r2.w)" +gdb_test "x" "or.l\t@\\(0x12345678(:32|),er3\\),@\\(0x9abc(:16|),er2.l\\)" \ + "or.l @(0x12345678:32,er3),@(0x9abc:16,er2.l)" +gdb_test "x" "or.l\t@\\(0x12345678(:32|),er3\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "or.l @(0x12345678:32,er3),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "or.l\t@\\(0x12345678(:32|),er3\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "or.l @(0x12345678:32,er3),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "or.l\t@\\(0x12345678(:32|),er3\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "or.l @(0x12345678:32,er3),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "or.l\t@\\(0x12345678(:32|),er3\\),@0x9abc(:16|)" \ + "or.l @(0x12345678:32,er3),@0x9abc:16" +gdb_test "x" "or.l\t@\\(0x12345678(:32|),er3\\),@0x9abcdef0(:32|)" \ + "or.l @(0x12345678:32,er3),@0x9abcdef0:32" +gdb_test "x" "or.l\t@\\(0x1234(:16|),r3l.b\\),@er1" \ + "or.l @(0x1234:16,r3l.b),@er1" +gdb_test "x" "or.l\t@\\(0x1234(:16|),r3l.b\\),@\\(0xc(:2|),er1\\)" \ + "or.l @(0x1234:16,r3l.b),@(0xc:2,er1)" +gdb_test "x" "or.l\t@\\(0x1234(:16|),r3l.b\\),@-er1" \ + "or.l @(0x1234:16,r3l.b),@-er1" +gdb_test "x" "or.l\t@\\(0x1234(:16|),r3l.b\\),@er1\\+" \ + "or.l @(0x1234:16,r3l.b),@er1+" +gdb_test "x" "or.l\t@\\(0x1234(:16|),r3l.b\\),@er1-" \ + "or.l @(0x1234:16,r3l.b),@er1-" +gdb_test "x" "or.l\t@\\(0x1234(:16|),r3l.b\\),@\\+er1" \ + "or.l @(0x1234:16,r3l.b),@+er1" +gdb_test "x" "or.l\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abc(:16|),er1\\)" \ + "or.l @(0x1234:16,r3l.b),@(0x9abc:16,er1)" +gdb_test "x" "or.l\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "or.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1)" +gdb_test "x" "or.l\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "or.l @(0x1234:16,r3l.b),@(0x9abc:16,r2l.b)" +gdb_test "x" "or.l\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abc(:16|),r2.w\\)" \ + "or.l @(0x1234:16,r3l.b),@(0x9abc:16,r2.w)" +gdb_test "x" "or.l\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abc(:16|),er2.l\\)" \ + "or.l @(0x1234:16,r3l.b),@(0x9abc:16,er2.l)" +gdb_test "x" "or.l\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "or.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "or.l\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "or.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "or.l\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "or.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "or.l\t@\\(0x1234(:16|),r3l.b\\),@0x9abc(:16|)" \ + "or.l @(0x1234:16,r3l.b),@0x9abc:16" +gdb_test "x" "or.l\t@\\(0x1234(:16|),r3l.b\\),@0x9abcdef0(:32|)" \ + "or.l @(0x1234:16,r3l.b),@0x9abcdef0:32" +gdb_test "x" "or.l\t@\\(0x1234(:16|),r3.w\\),@er1" \ + "or.l @(0x1234:16,r3.w),@er1" +gdb_test "x" "or.l\t@\\(0x1234(:16|),r3.w\\),@\\(0xc(:2|),er1\\)" \ + "or.l @(0x1234:16,r3.w),@(0xc:2,er1)" +gdb_test "x" "or.l\t@\\(0x1234(:16|),r3.w\\),@-er1" \ + "or.l @(0x1234:16,r3.w),@-er1" +gdb_test "x" "or.l\t@\\(0x1234(:16|),r3.w\\),@er1\\+" \ + "or.l @(0x1234:16,r3.w),@er1+" +gdb_test "x" "or.l\t@\\(0x1234(:16|),r3.w\\),@er1-" \ + "or.l @(0x1234:16,r3.w),@er1-" +gdb_test "x" "or.l\t@\\(0x1234(:16|),r3.w\\),@\\+er1" \ + "or.l @(0x1234:16,r3.w),@+er1" +gdb_test "x" "or.l\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abc(:16|),er1\\)" \ + "or.l @(0x1234:16,r3.w),@(0x9abc:16,er1)" +gdb_test "x" "or.l\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "or.l @(0x1234:16,r3.w),@(0x9abcdef0:32,er1)" +gdb_test "x" "or.l\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "or.l @(0x1234:16,r3.w),@(0x9abc:16,r2l.b)" +gdb_test "x" "or.l\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abc(:16|),r2.w\\)" \ + "or.l @(0x1234:16,r3.w),@(0x9abc:16,r2.w)" +gdb_test "x" "or.l\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abc(:16|),er2.l\\)" \ + "or.l @(0x1234:16,r3.w),@(0x9abc:16,er2.l)" +gdb_test "x" "or.l\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "or.l @(0x1234:16,r3.w),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "or.l\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "or.l @(0x1234:16,r3.w),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "or.l\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "or.l @(0x1234:16,r3.w),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "or.l\t@\\(0x1234(:16|),r3.w\\),@0x9abc(:16|)" \ + "or.l @(0x1234:16,r3.w),@0x9abc:16" +gdb_test "x" "or.l\t@\\(0x1234(:16|),r3.w\\),@0x9abcdef0(:32|)" \ + "or.l @(0x1234:16,r3.w),@0x9abcdef0:32" +gdb_test "x" "or.l\t@\\(0x1234(:16|),er3.l\\),@er1" \ + "or.l @(0x1234:16,er3.l),@er1" +gdb_test "x" "or.l\t@\\(0x1234(:16|),er3.l\\),@\\(0xc(:2|),er1\\)" \ + "or.l @(0x1234:16,er3.l),@(0xc:2,er1)" +gdb_test "x" "or.l\t@\\(0x1234(:16|),er3.l\\),@-er1" \ + "or.l @(0x1234:16,er3.l),@-er1" +gdb_test "x" "or.l\t@\\(0x1234(:16|),er3.l\\),@er1\\+" \ + "or.l @(0x1234:16,er3.l),@er1+" +gdb_test "x" "or.l\t@\\(0x1234(:16|),er3.l\\),@er1-" \ + "or.l @(0x1234:16,er3.l),@er1-" +gdb_test "x" "or.l\t@\\(0x1234(:16|),er3.l\\),@\\+er1" \ + "or.l @(0x1234:16,er3.l),@+er1" +gdb_test "x" "or.l\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abc(:16|),er1\\)" \ + "or.l @(0x1234:16,er3.l),@(0x9abc:16,er1)" +gdb_test "x" "or.l\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "or.l @(0x1234:16,er3.l),@(0x9abcdef0:32,er1)" +gdb_test "x" "or.l\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "or.l @(0x1234:16,er3.l),@(0x9abc:16,r2l.b)" +gdb_test "x" "or.l\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abc(:16|),r2.w\\)" \ + "or.l @(0x1234:16,er3.l),@(0x9abc:16,r2.w)" +gdb_test "x" "or.l\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abc(:16|),er2.l\\)" \ + "or.l @(0x1234:16,er3.l),@(0x9abc:16,er2.l)" +gdb_test "x" "or.l\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "or.l @(0x1234:16,er3.l),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "or.l\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "or.l @(0x1234:16,er3.l),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "or.l\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "or.l @(0x1234:16,er3.l),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "or.l\t@\\(0x1234(:16|),er3.l\\),@0x9abc(:16|)" \ + "or.l @(0x1234:16,er3.l),@0x9abc:16" +gdb_test "x" "or.l\t@\\(0x1234(:16|),er3.l\\),@0x9abcdef0(:32|)" \ + "or.l @(0x1234:16,er3.l),@0x9abcdef0:32" +gdb_test "x" "or.l\t@\\(0x12345678(:32|),r3l.b\\),@er1" \ + "or.l @(0x12345678:32,r3l.b),@er1" +gdb_test "x" "or.l\t@\\(0x12345678(:32|),r3l.b\\),@\\(0xc(:2|),er1\\)" \ + "or.l @(0x12345678:32,r3l.b),@(0xc:2,er1)" +gdb_test "x" "or.l\t@\\(0x12345678(:32|),r3l.b\\),@-er1" \ + "or.l @(0x12345678:32,r3l.b),@-er1" +gdb_test "x" "or.l\t@\\(0x12345678(:32|),r3l.b\\),@er1\\+" \ + "or.l @(0x12345678:32,r3l.b),@er1+" +gdb_test "x" "or.l\t@\\(0x12345678(:32|),r3l.b\\),@er1-" \ + "or.l @(0x12345678:32,r3l.b),@er1-" +gdb_test "x" "or.l\t@\\(0x12345678(:32|),r3l.b\\),@\\+er1" \ + "or.l @(0x12345678:32,r3l.b),@+er1" +gdb_test "x" "or.l\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abc(:16|),er1\\)" \ + "or.l @(0x12345678:32,r3l.b),@(0x9abc:16,er1)" +gdb_test "x" "or.l\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "or.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1)" +gdb_test "x" "or.l\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "or.l @(0x12345678:32,r3l.b),@(0x9abc:16,r2l.b)" +gdb_test "x" "or.l\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abc(:16|),r2.w\\)" \ + "or.l @(0x12345678:32,r3l.b),@(0x9abc:16,r2.w)" +gdb_test "x" "or.l\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abc(:16|),er2.l\\)" \ + "or.l @(0x12345678:32,r3l.b),@(0x9abc:16,er2.l)" +gdb_test "x" "or.l\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "or.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "or.l\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "or.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "or.l\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "or.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "or.l\t@\\(0x12345678(:32|),r3l.b\\),@0x9abc(:16|)" \ + "or.l @(0x12345678:32,r3l.b),@0x9abc:16" +gdb_test "x" "or.l\t@\\(0x12345678(:32|),r3l.b\\),@0x9abcdef0(:32|)" \ + "or.l @(0x12345678:32,r3l.b),@0x9abcdef0:32" +gdb_test "x" "or.l\t@\\(0x12345678(:32|),r3.w\\),@er1" \ + "or.l @(0x12345678:32,r3.w),@er1" +gdb_test "x" "or.l\t@\\(0x12345678(:32|),r3.w\\),@\\(0xc(:2|),er1\\)" \ + "or.l @(0x12345678:32,r3.w),@(0xc:2,er1)" +gdb_test "x" "or.l\t@\\(0x12345678(:32|),r3.w\\),@-er1" \ + "or.l @(0x12345678:32,r3.w),@-er1" +gdb_test "x" "or.l\t@\\(0x12345678(:32|),r3.w\\),@er1\\+" \ + "or.l @(0x12345678:32,r3.w),@er1+" +gdb_test "x" "or.l\t@\\(0x12345678(:32|),r3.w\\),@er1-" \ + "or.l @(0x12345678:32,r3.w),@er1-" +gdb_test "x" "or.l\t@\\(0x12345678(:32|),r3.w\\),@\\+er1" \ + "or.l @(0x12345678:32,r3.w),@+er1" +gdb_test "x" "or.l\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abc(:16|),er1\\)" \ + "or.l @(0x12345678:32,r3.w),@(0x9abc:16,er1)" +gdb_test "x" "or.l\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "or.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1)" +gdb_test "x" "or.l\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "or.l @(0x12345678:32,r3.w),@(0x9abc:16,r2l.b)" +gdb_test "x" "or.l\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abc(:16|),r2.w\\)" \ + "or.l @(0x12345678:32,r3.w),@(0x9abc:16,r2.w)" +gdb_test "x" "or.l\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abc(:16|),er2.l\\)" \ + "or.l @(0x12345678:32,r3.w),@(0x9abc:16,er2.l)" +gdb_test "x" "or.l\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "or.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "or.l\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "or.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "or.l\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "or.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "or.l\t@\\(0x12345678(:32|),r3.w\\),@0x9abc(:16|)" \ + "or.l @(0x12345678:32,r3.w),@0x9abc:16" +gdb_test "x" "or.l\t@\\(0x12345678(:32|),r3.w\\),@0x9abcdef0(:32|)" \ + "or.l @(0x12345678:32,r3.w),@0x9abcdef0:32" +gdb_test "x" "or.l\t@\\(0x12345678(:32|),er3.l\\),@er1" \ + "or.l @(0x12345678:32,er3.l),@er1" +gdb_test "x" "or.l\t@\\(0x12345678(:32|),er3.l\\),@\\(0xc(:2|),er1\\)" \ + "or.l @(0x12345678:32,er3.l),@(0xc:2,er1)" +gdb_test "x" "or.l\t@\\(0x12345678(:32|),er3.l\\),@-er1" \ + "or.l @(0x12345678:32,er3.l),@-er1" +gdb_test "x" "or.l\t@\\(0x12345678(:32|),er3.l\\),@er1\\+" \ + "or.l @(0x12345678:32,er3.l),@er1+" +gdb_test "x" "or.l\t@\\(0x12345678(:32|),er3.l\\),@er1-" \ + "or.l @(0x12345678:32,er3.l),@er1-" +gdb_test "x" "or.l\t@\\(0x12345678(:32|),er3.l\\),@\\+er1" \ + "or.l @(0x12345678:32,er3.l),@+er1" +gdb_test "x" "or.l\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abc(:16|),er1\\)" \ + "or.l @(0x12345678:32,er3.l),@(0x9abc:16,er1)" +gdb_test "x" "or.l\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "or.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1)" +gdb_test "x" "or.l\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "or.l @(0x12345678:32,er3.l),@(0x9abc:16,r2l.b)" +gdb_test "x" "or.l\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abc(:16|),r2.w\\)" \ + "or.l @(0x12345678:32,er3.l),@(0x9abc:16,r2.w)" +gdb_test "x" "or.l\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abc(:16|),er2.l\\)" \ + "or.l @(0x12345678:32,er3.l),@(0x9abc:16,er2.l)" +gdb_test "x" "or.l\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "or.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "or.l\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "or.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "or.l\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "or.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "or.l\t@\\(0x12345678(:32|),er3.l\\),@0x9abc(:16|)" \ + "or.l @(0x12345678:32,er3.l),@0x9abc:16" +gdb_test "x" "or.l\t@\\(0x12345678(:32|),er3.l\\),@0x9abcdef0(:32|)" \ + "or.l @(0x12345678:32,er3.l),@0x9abcdef0:32" +gdb_test "x" "or.l\t@0x1234(:16|),@er1" \ + "or.l @0x1234:16,@er1" +gdb_test "x" "or.l\t@0x1234(:16|),@\\(0xc(:2|),er1\\)" \ + "or.l @0x1234:16,@(0xc:2,er1)" +gdb_test "x" "or.l\t@0x1234(:16|),@-er1" \ + "or.l @0x1234:16,@-er1" +gdb_test "x" "or.l\t@0x1234(:16|),@er1\\+" \ + "or.l @0x1234:16,@er1+" +gdb_test "x" "or.l\t@0x1234(:16|),@er1-" \ + "or.l @0x1234:16,@er1-" +gdb_test "x" "or.l\t@0x1234(:16|),@\\+er1" \ + "or.l @0x1234:16,@+er1" +gdb_test "x" "or.l\t@0x1234(:16|),@\\(0x9abc(:16|),er1\\)" \ + "or.l @0x1234:16,@(0x9abc:16,er1)" +gdb_test "x" "or.l\t@0x1234(:16|),@\\(0x9abcdef0(:32|),er1\\)" \ + "or.l @0x1234:16,@(0x9abcdef0:32,er1)" +gdb_test "x" "or.l\t@0x1234(:16|),@\\(0x9abc(:16|),r2l.b\\)" \ + "or.l @0x1234:16,@(0x9abc:16,r2l.b)" +gdb_test "x" "or.l\t@0x1234(:16|),@\\(0x9abc(:16|),r2.w\\)" \ + "or.l @0x1234:16,@(0x9abc:16,r2.w)" +gdb_test "x" "or.l\t@0x1234(:16|),@\\(0x9abc(:16|),er2.l\\)" \ + "or.l @0x1234:16,@(0x9abc:16,er2.l)" +gdb_test "x" "or.l\t@0x1234(:16|),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "or.l @0x1234:16,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "or.l\t@0x1234(:16|),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "or.l @0x1234:16,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "or.l\t@0x1234(:16|),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "or.l @0x1234:16,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "or.l\t@0x1234(:16|),@0x9abc(:16|)" \ + "or.l @0x1234:16,@0x9abc:16" +gdb_test "x" "or.l\t@0x1234(:16|),@0x9abcdef0(:32|)" \ + "or.l @0x1234:16,@0x9abcdef0:32" +gdb_test "x" "or.l\t@0x12345678(:32|),@er1" \ + "or.l @0x12345678:32,@er1" +gdb_test "x" "or.l\t@0x12345678(:32|),@\\(0xc(:2|),er1\\)" \ + "or.l @0x12345678:32,@(0xc:2,er1)" +gdb_test "x" "or.l\t@0x12345678(:32|),@-er1" \ + "or.l @0x12345678:32,@-er1" +gdb_test "x" "or.l\t@0x12345678(:32|),@er1\\+" \ + "or.l @0x12345678:32,@er1+" +gdb_test "x" "or.l\t@0x12345678(:32|),@er1-" \ + "or.l @0x12345678:32,@er1-" +gdb_test "x" "or.l\t@0x12345678(:32|),@\\+er1" \ + "or.l @0x12345678:32,@+er1" +gdb_test "x" "or.l\t@0x12345678(:32|),@\\(0x9abc(:16|),er1\\)" \ + "or.l @0x12345678:32,@(0x9abc:16,er1)" +gdb_test "x" "or.l\t@0x12345678(:32|),@\\(0x9abcdef0(:32|),er1\\)" \ + "or.l @0x12345678:32,@(0x9abcdef0:32,er1)" +gdb_test "x" "or.l\t@0x12345678(:32|),@\\(0x9abc(:16|),r2l.b\\)" \ + "or.l @0x12345678:32,@(0x9abc:16,r2l.b)" +gdb_test "x" "or.l\t@0x12345678(:32|),@\\(0x9abc(:16|),r2.w\\)" \ + "or.l @0x12345678:32,@(0x9abc:16,r2.w)" +gdb_test "x" "or.l\t@0x12345678(:32|),@\\(0x9abc(:16|),er2.l\\)" \ + "or.l @0x12345678:32,@(0x9abc:16,er2.l)" +gdb_test "x" "or.l\t@0x12345678(:32|),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "or.l @0x12345678:32,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "or.l\t@0x12345678(:32|),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "or.l @0x12345678:32,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "or.l\t@0x12345678(:32|),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "or.l @0x12345678:32,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "or.l\t@0x12345678(:32|),@0x9abc(:16|)" \ + "or.l @0x12345678:32,@0x9abc:16" +gdb_test "x" "or.l\t@0x12345678(:32|),@0x9abcdef0(:32|)" \ + "or.l @0x12345678:32,@0x9abcdef0:32" diff --git a/gdb/testsuite/gdb.disasm/t08_or.s b/gdb/testsuite/gdb.disasm/t08_or.s new file mode 100644 index 0000000..22d9f04 --- /dev/null +++ b/gdb/testsuite/gdb.disasm/t08_or.s @@ -0,0 +1,972 @@ +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;log_1 +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + .h8300sx + .text + .global _start +_start: + or.b #0x12:8,r1h ;c112 + or.b #0x12:8,@er1 ;7d10c012 + or.b #0x12:8,@(0x3:2,er1) ;01776818c012 + or.b #0x12:8,@er1+ ;01746c18c012 + or.b #0x12:8,@-er1 ;01776c18c012 + or.b #0x12:8,@+er1 ;01756c18c012 + or.b #0x12:8,@er1- ;01766c18c012 + or.b #0x12:8,@(0x1234:16,er1) ;01746e181234c012 + or.b #0x12:8,@(0x12345678:32,er1) ;78146a2812345678c012 + or.b #0x12:8,@(0x1234:16,r2l.b) ;01756e281234c012 + or.b #0x12:8,@(0x1234:16,r2.w) ;01766e281234c012 + or.b #0x12:8,@(0x1234:16,er2.l) ;01776e281234c012 + or.b #0x12:8,@(0x12345678:32,r2l.b) ;78256a2812345678c012 + or.b #0x12:8,@(0x12345678:32,r2.w) ;78266a2812345678c012 + or.b #0x12:8,@(0x12345678:32,er2.l) ;78276a2812345678c012 + or.b #0x12:8,@0xffffff12:8 ;7f12c012 + or.b #0x12:8,@0x1234:16 ;6a181234c012 + or.b #0x12:8,@0x12345678:32 ;6a3812345678c012 + + or.b r3h,r1h ;1431 + + or.b r3h,@er1 ;7d101430 + or.b r3h,@(0x3:2,er1) ;01793143 + or.b r3h,@er1+ ;01798143 + or.b r3h,@-er1 ;0179b143 + or.b r3h,@+er1 ;01799143 + or.b r3h,@er1- ;0179a143 + or.b r3h,@(0x1234:16,er1) ;0179c1431234 + or.b r3h,@(0x12345678:32,er1) ;0179c94312345678 + or.b r3h,@(0x1234:16,r2l.b) ;0179d2431234 + or.b r3h,@(0x1234:16,r2.w) ;0179e2431234 + or.b r3h,@(0x1234:16,er2.l) ;0179f2431234 + or.b r3h,@(0x12345678:32,r2l.b) ;0179da4312345678 + or.b r3h,@(0x12345678:32,r2.w) ;0179ea4312345678 + or.b r3h,@(0x12345678:32,er2.l) ;0179fa4312345678 + or.b r3h,@0xffffff12:8 ;7f121430 + or.b r3h,@0x1234:16 ;6a1812341430 + or.b r3h,@0x12345678:32 ;6a38123456781430 + + or.b @er3,r1h ;7c301401 + or.b @(0x3:2,er3),r1h ;017a3341 + or.b @er3+,r1h ;017a8341 + or.b @-er3,r1h ;017ab341 + or.b @+er3,r1h ;017a9341 + or.b @er3-,r1h ;017aa341 + or.b @(0x1234:16,er1),r1h ;017ac1411234 + or.b @(0x12345678:32,er1),r1h ;017ac94112345678 + or.b @(0x1234:16,r2l.b),r1h ;017ad2411234 + or.b @(0x1234:16,r2.w),r1h ;017ae2411234 + or.b @(0x1234:16,er2.l),r1h ;017af2411234 + or.b @(0x12345678:32,r2l.b),r1h ;017ada4112345678 + or.b @(0x12345678:32,r2.w),r1h ;017aea4112345678 + or.b @(0x12345678:32,er2.l),r1h ;017afa4112345678 + or.b @0xffffff12:8,r1h ;7e121401 + or.b @0x1234:16,r1h ;6a1012341401 + or.b @0x12345678:32,r1h ;6a30123456781401 + + or.b @er3,@er1 ;7c350140 + or.b @er3,@(3:2,er1) ;7c353140 + or.b @er3,@-er1 ;7c35b140 + or.b @er3,@er1+ ;7c358140 + or.b @er3,@er1- ;7c35a140 + or.b @er3,@+er1 ;7c359140 + or.b @er3,@(0xffff9abc:16,er1) ;7c35c1409abc + or.b @er3,@(0x9abcdef0:32,er1) ;7c35c9409abcdef0 + or.b @er3,@(0xffff9abc:16,r2l.b) ;7c35d2409abc + or.b @er3,@(0xffff9abc:16,r2.w) ;7c35e2409abc + or.b @er3,@(0xffff9abc:16,er2.l) ;7c35f2409abc + or.b @er3,@(0x9abcdef0:32,r2l.b) ;7c35da409abcdef0 + or.b @er3,@(0x9abcdef0:32,r2.w) ;7c35ea409abcdef0 + or.b @er3,@(0x9abcdef0:32,er2.l) ;7c35fa409abcdef0 + or.b @er3,@0xffff9abc:16 ;7c3540409abc + or.b @er3,@0x9abcdef0:32 ;7c3548409abcdef0 + + or.b @-er3,@er1 ;01776c3c0140 + or.b @-er3,@(3:2,er1) ;01776c3c3140 + or.b @-er3,@-er1 ;01776c3cb140 + or.b @-er3,@er1+ ;01776c3c8140 + or.b @-er3,@er1- ;01776c3ca140 + or.b @-er3,@+er1 ;01776c3c9140 + or.b @-er3,@(0xffff9abc:16,er1) ;01776c3cc1409abc + or.b @-er3,@(0x9abcdef0:32,er1) ;01776c3cc9409abcdef0 + or.b @-er3,@(0xffff9abc:16,r2l.b) ;01776c3cd2409abc + or.b @-er3,@(0xffff9abc:16,r2.w) ;01776c3ce2409abc + or.b @-er3,@(0xffff9abc:16,er2.l) ;01776c3cf2409abc + or.b @-er3,@(0x9abcdef0:32,r2l.b) ;01776c3cda409abcdef0 + or.b @-er3,@(0x9abcdef0:32,r2.w) ;01776c3cea409abcdef0 + or.b @-er3,@(0x9abcdef0:32,er2.l) ;01776c3cfa409abcdef0 + or.b @-er3,@0xffff9abc:16 ;01776c3c40409abc + or.b @-er3,@0x9abcdef0:32 ;01776c3c48409abcdef0 + + or.b @er3+,@er1 ;01746c3c0140 + or.b @er3+,@(3:2,er1) ;01746c3c3140 + or.b @er3+,@-er1 ;01746c3cb140 + or.b @er3+,@er1+ ;01746c3c8140 + or.b @er3+,@er1- ;01746c3ca140 + or.b @er3+,@+er1 ;01746c3c9140 + or.b @er3+,@(0xffff9abc:16,er1) ;01746c3cc1409abc + or.b @er3+,@(0x9abcdef0:32,er1) ;01746c3cc9409abcdef0 + or.b @er3+,@(0xffff9abc:16,r2l.b) ;01746c3cd2409abc + or.b @er3+,@(0xffff9abc:16,r2.w) ;01746c3ce2409abc + or.b @er3+,@(0xffff9abc:16,er2.l) ;01746c3cf2409abc + or.b @er3+,@(0x9abcdef0:32,r2l.b) ;01746c3cda409abcdef0 + or.b @er3+,@(0x9abcdef0:32,r2.w) ;01746c3cea409abcdef0 + or.b @er3+,@(0x9abcdef0:32,er2.l) ;01746c3cfa409abcdef0 + or.b @er3+,@0xffff9abc:16 ;01746c3c40409abc + or.b @er3+,@0x9abcdef0:32 ;01746c3c48409abcdef0 + + or.b @er3-,@er1 ;01766c3c0140 + or.b @er3-,@(3:2,er1) ;01766c3c3140 + or.b @er3-,@-er1 ;01766c3cb140 + or.b @er3-,@er1+ ;01766c3c8140 + or.b @er3-,@er1- ;01766c3ca140 + or.b @er3-,@+er1 ;01766c3c9140 + or.b @er3-,@(0xffff9abc:16,er1) ;01766c3cc1409abc + or.b @er3-,@(0x9abcdef0:32,er1) ;01766c3cc9409abcdef0 + or.b @er3-,@(0xffff9abc:16,r2l.b) ;01766c3cd2409abc + or.b @er3-,@(0xffff9abc:16,r2.w) ;01766c3ce2409abc + or.b @er3-,@(0xffff9abc:16,er2.l) ;01766c3cf2409abc + or.b @er3-,@(0x9abcdef0:32,r2l.b) ;01766c3cda409abcdef0 + or.b @er3-,@(0x9abcdef0:32,r2.w) ;01766c3cea409abcdef0 + or.b @er3-,@(0x9abcdef0:32,er2.l) ;01766c3cfa409abcdef0 + or.b @er3-,@0xffff9abc:16 ;01766c3c40409abc + or.b @er3-,@0x9abcdef0:32 ;01766c3c48409abcdef0 + + or.b @+er3,@er1 ;01756c3c0140 + or.b @+er3,@(3:2,er1) ;01756c3c3140 + or.b @+er3,@-er1 ;01756c3cb140 + or.b @+er3,@er1+ ;01756c3c8140 + or.b @+er3,@er1- ;01756c3ca140 + or.b @+er3,@+er1 ;01756c3c9140 + or.b @+er3,@(0xffff9abc:16,er1) ;01756c3cc1409abc + or.b @+er3,@(0x9abcdef0:32,er1) ;01756c3cc9409abcdef0 + or.b @+er3,@(0xffff9abc:16,r2l.b) ;01756c3cd2409abc + or.b @+er3,@(0xffff9abc:16,r2.w) ;01756c3ce2409abc + or.b @+er3,@(0xffff9abc:16,er2.l) ;01756c3cf2409abc + or.b @+er3,@(0x9abcdef0:32,r2l.b) ;01756c3cda409abcdef0 + or.b @+er3,@(0x9abcdef0:32,r2.w) ;01756c3cea409abcdef0 + or.b @+er3,@(0x9abcdef0:32,er2.l) ;01756c3cfa409abcdef0 + or.b @+er3,@0xffff9abc:16 ;01756c3c40409abc + or.b @+er3,@0x9abcdef0:32 ;01756c3c48409abcdef0 + + or.b @(0x1234:16,er3),@er1 ;01746e3c12340140 + or.b @(0x1234:16,er3),@(3:2,er1) ;01746e3c12343140 + or.b @(0x1234:16,er3),@-er1 ;01746e3c1234b140 + or.b @(0x1234:16,er3),@er1+ ;01746e3c12348140 + or.b @(0x1234:16,er3),@er1- ;01746e3c1234a140 + or.b @(0x1234:16,er3),@+er1 ;01746e3c12349140 + or.b @(0x1234:16,er3),@(0xffff9abc:16,er1) ;01746e3c1234c1409abc + or.b @(0x1234:16,er3),@(0x9abcdef0:32,er1) ;01746e3c1234c9409abcdef0 + or.b @(0x1234:16,er3),@(0xffff9abc:16,r2l.b) ;01746e3c1234d2409abc + or.b @(0x1234:16,er3),@(0xffff9abc:16,r2.w) ;01746e3c1234e2409abc + or.b @(0x1234:16,er3),@(0xffff9abc:16,er2.l) ;01746e3c1234f2409abc + or.b @(0x1234:16,er3),@(0x9abcdef0:32,r2l.b) ;01746e3c1234da409abcdef0 + or.b @(0x1234:16,er3),@(0x9abcdef0:32,r2.w) ;01746e3c1234ea409abcdef0 + or.b @(0x1234:16,er3),@(0x9abcdef0:32,er2.l) ;01746e3c1234fa409abcdef0 + or.b @(0x1234:16,er3),@0xffff9abc:16 ;01746e3c123440409abc + or.b @(0x1234:16,er3),@0x9abcdef0:32 ;01746e3c123448409abcdef0 + + or.b @(0x12345678:32,er3),@er1 ;78346a2c123456780140 + or.b @(0x12345678:32,er3),@(3:2,er1) ;78346a2c123456783140 + or.b @(0x12345678:32,er3),@-er1 ;78346a2c12345678b140 + or.b @(0x12345678:32,er3),@er1+ ;78346a2c123456788140 + or.b @(0x12345678:32,er3),@er1- ;78346a2c12345678a140 + or.b @(0x12345678:32,er3),@+er1 ;78346a2c123456789140 + or.b @(0x12345678:32,er3),@(0xffff9abc:16,er1) ;78346a2c12345678c1409abc + or.b @(0x12345678:32,er3),@(0x9abcdef0:32,er1) ;78346a2c12345678c9409abcdef0 + or.b @(0x12345678:32,er3),@(0xffff9abc:16,r2l.b) ;78346a2c12345678d2409abc + or.b @(0x12345678:32,er3),@(0xffff9abc:16,r2.w) ;78346a2c12345678e2409abc + or.b @(0x12345678:32,er3),@(0xffff9abc:16,er2.l) ;78346a2c12345678f2409abc + or.b @(0x12345678:32,er3),@(0x9abcdef0:32,r2l.b) ;78346a2c12345678da409abcdef0 + or.b @(0x12345678:32,er3),@(0x9abcdef0:32,r2.w) ;78346a2c12345678ea409abcdef0 + or.b @(0x12345678:32,er3),@(0x9abcdef0:32,er2.l) ;78346a2c12345678fa409abcdef0 + or.b @(0x12345678:32,er3),@0xffff9abc:16 ;78346a2c1234567840409abc + or.b @(0x12345678:32,er3),@0x9abcdef0:32 ;78346a2c1234567848409abcdef0 + + or.b @(0x1234:16,r3l.b),@er1 ;01756e3c12340140 + or.b @(0x1234:16,r3l.b),@(3:2,er1) ;01756e3c12343140 + or.b @(0x1234:16,r3l.b),@-er1 ;01756e3c1234b140 + or.b @(0x1234:16,r3l.b),@er1+ ;01756e3c12348140 + or.b @(0x1234:16,r3l.b),@er1- ;01756e3c1234a140 + or.b @(0x1234:16,r3l.b),@+er1 ;01756e3c12349140 + or.b @(0x1234:16,r3l.b),@(0xffff9abc:16,er1) ;01756e3c1234c1409abc + or.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1) ;01756e3c1234c9409abcdef0 + or.b @(0x1234:16,r3l.b),@(0xffff9abc:16,r2l.b) ;01756e3c1234d2409abc + or.b @(0x1234:16,r3l.b),@(0xffff9abc:16,r2.w) ;01756e3c1234e2409abc + or.b @(0x1234:16,r3l.b),@(0xffff9abc:16,er2.l) ;01756e3c1234f2409abc + or.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2l.b) ;01756e3c1234da409abcdef0 + or.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2.w) ;01756e3c1234ea409abcdef0 + or.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,er2.l) ;01756e3c1234fa409abcdef0 + or.b @(0x1234:16,r3l.b),@0xffff9abc:16 ;01756e3c123440409abc + or.b @(0x1234:16,r3l.b),@0x9abcdef0:32 ;01756e3c123448409abcdef0 + + or.b @(0x1234:16,r3.w),@er1 ;01766e3c12340140 + or.b @(0x1234:16,r3.w),@(3:2,er1) ;01766e3c12343140 + or.b @(0x1234:16,r3.w),@-er1 ;01766e3c1234b140 + or.b @(0x1234:16,r3.w),@er1+ ;01766e3c12348140 + or.b @(0x1234:16,r3.w),@er1- ;01766e3c1234a140 + or.b @(0x1234:16,r3.w),@+er1 ;01766e3c12349140 + or.b @(0x1234:16,r3.w),@(0xffff9abc:16,er1) ;01766e3c1234c1409abc + or.b @(0x1234:16,r3.w),@(0x9abcdef0:32,er1) ;01766e3c1234c9409abcdef0 + or.b @(0x1234:16,r3.w),@(0xffff9abc:16,r2l.b) ;01766e3c1234d2409abc + or.b @(0x1234:16,r3.w),@(0xffff9abc:16,r2.w) ;01766e3c1234e2409abc + or.b @(0x1234:16,r3.w),@(0xffff9abc:16,er2.l) ;01766e3c1234f2409abc + or.b @(0x1234:16,r3.w),@(0x9abcdef0:32,r2l.b) ;01766e3c1234da409abcdef0 + or.b @(0x1234:16,r3.w),@(0x9abcdef0:32,r2.w) ;01766e3c1234ea409abcdef0 + or.b @(0x1234:16,r3.w),@(0x9abcdef0:32,er2.l) ;01766e3c1234fa409abcdef0 + or.b @(0x1234:16,r3.w),@0xffff9abc:16 ;01766e3c123440409abc + or.b @(0x1234:16,r3.w),@0x9abcdef0:32 ;01766e3c123448409abcdef0 + + or.b @(0x1234:16,er3.l),@er1 ;01776e3c12340140 + or.b @(0x1234:16,er3.l),@(3:2,er1) ;01776e3c12343140 + or.b @(0x1234:16,er3.l),@-er1 ;01776e3c1234b140 + or.b @(0x1234:16,er3.l),@er1+ ;01776e3c12348140 + or.b @(0x1234:16,er3.l),@er1- ;01776e3c1234a140 + or.b @(0x1234:16,er3.l),@+er1 ;01776e3c12349140 + or.b @(0x1234:16,er3.l),@(0xffff9abc:16,er1) ;01776e3c1234c1409abc + or.b @(0x1234:16,er3.l),@(0x9abcdef0:32,er1) ;01776e3c1234c9409abcdef0 + or.b @(0x1234:16,er3.l),@(0xffff9abc:16,r2l.b) ;01776e3c1234d2409abc + or.b @(0x1234:16,er3.l),@(0xffff9abc:16,r2.w) ;01776e3c1234e2409abc + or.b @(0x1234:16,er3.l),@(0xffff9abc:16,er2.l) ;01776e3c1234f2409abc + or.b @(0x1234:16,er3.l),@(0x9abcdef0:32,r2l.b) ;01776e3c1234da409abcdef0 + or.b @(0x1234:16,er3.l),@(0x9abcdef0:32,r2.w) ;01776e3c1234ea409abcdef0 + or.b @(0x1234:16,er3.l),@(0x9abcdef0:32,er2.l) ;01776e3c1234fa409abcdef0 + or.b @(0x1234:16,er3.l),@0xffff9abc:16 ;01776e3c123440409abc + or.b @(0x1234:16,er3.l),@0x9abcdef0:32 ;01776e3c123448409abcdef0 + + or.b @(0x12345678:32,r3l.b),@er1 ;78356a2c123456780140 + or.b @(0x12345678:32,r3l.b),@(3:2,er1) ;78356a2c123456783140 + or.b @(0x12345678:32,r3l.b),@-er1 ;78356a2c12345678b140 + or.b @(0x12345678:32,r3l.b),@er1+ ;78356a2c123456788140 + or.b @(0x12345678:32,r3l.b),@er1- ;78356a2c12345678a140 + or.b @(0x12345678:32,r3l.b),@+er1 ;78356a2c123456789140 + or.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,er1) ;78356a2c12345678c1409abc + or.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1) ;78356a2c12345678c9409abcdef0 + or.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2l.b) ;78356a2c12345678d2409abc + or.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2.w) ;78356a2c12345678e2409abc + or.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,er2.l) ;78356a2c12345678f2409abc + or.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2l.b) ;78356a2c12345678da409abcdef0 + or.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2.w) ;78356a2c12345678ea409abcdef0 + or.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er2.l) ;78356a2c12345678fa409abcdef0 + or.b @(0x12345678:32,r3l.b),@0xffff9abc:16 ;78356a2c1234567840409abc + or.b @(0x12345678:32,r3l.b),@0x9abcdef0:32 ;78356a2c1234567848409abcdef0 + + or.b @(0x12345678:32,r3.w),@er1 ;78366a2c123456780140 + or.b @(0x12345678:32,r3.w),@(3:2,er1) ;78366a2c123456783140 + or.b @(0x12345678:32,r3.w),@-er1 ;78366a2c12345678b140 + or.b @(0x12345678:32,r3.w),@er1+ ;78366a2c123456788140 + or.b @(0x12345678:32,r3.w),@er1- ;78366a2c12345678a140 + or.b @(0x12345678:32,r3.w),@+er1 ;78366a2c123456789140 + or.b @(0x12345678:32,r3.w),@(0xffff9abc:16,er1) ;78366a2c12345678c1409abc + or.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1) ;78366a2c12345678c9409abcdef0 + or.b @(0x12345678:32,r3.w),@(0xffff9abc:16,r2l.b) ;78366a2c12345678d2409abc + or.b @(0x12345678:32,r3.w),@(0xffff9abc:16,r2.w) ;78366a2c12345678e2409abc + or.b @(0x12345678:32,r3.w),@(0xffff9abc:16,er2.l) ;78366a2c12345678f2409abc + or.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2l.b) ;78366a2c12345678da409abcdef0 + or.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2.w) ;78366a2c12345678ea409abcdef0 + or.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,er2.l) ;78366a2c12345678fa409abcdef0 + or.b @(0x12345678:32,r3.w),@0xffff9abc:16 ;78366a2c1234567840409abc + or.b @(0x12345678:32,r3.w),@0x9abcdef0:32 ;78366a2c1234567848409abcdef0 + + or.b @(0x12345678:32,er3.l),@er1 ;78376a2c123456780140 + or.b @(0x12345678:32,er3.l),@(3:2,er1) ;78376a2c123456783140 + or.b @(0x12345678:32,er3.l),@-er1 ;78376a2c12345678b140 + or.b @(0x12345678:32,er3.l),@er1+ ;78376a2c123456788140 + or.b @(0x12345678:32,er3.l),@er1- ;78376a2c12345678a140 + or.b @(0x12345678:32,er3.l),@+er1 ;78376a2c123456789140 + or.b @(0x12345678:32,er3.l),@(0xffff9abc:16,er1) ;78376a2c12345678c1409abc + or.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1) ;78376a2c12345678c9409abcdef0 + or.b @(0x12345678:32,er3.l),@(0xffff9abc:16,r2l.b) ;78376a2c12345678d2409abc + or.b @(0x12345678:32,er3.l),@(0xffff9abc:16,r2.w) ;78376a2c12345678e2409abc + or.b @(0x12345678:32,er3.l),@(0xffff9abc:16,er2.l) ;78376a2c12345678f2409abc + or.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2l.b) ;78376a2c12345678da409abcdef0 + or.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2.w) ;78376a2c12345678ea409abcdef0 + or.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,er2.l) ;78376a2c12345678fa409abcdef0 + or.b @(0x12345678:32,er3.l),@0xffff9abc:16 ;78376a2c1234567840409abc + or.b @(0x12345678:32,er3.l),@0x9abcdef0:32 ;78376a2c1234567848409abcdef0 + + or.b @0x1234:16,@er1 ;6a1512340140 + or.b @0x1234:16,@(3:2,er1) ;6a1512343140 + or.b @0x1234:16,@-er1 ;6a151234b140 + or.b @0x1234:16,@er1+ ;6a1512348140 + or.b @0x1234:16,@er1- ;6a151234a140 + or.b @0x1234:16,@+er1 ;6a1512349140 + or.b @0x1234:16,@(0xffff9abc:16,er1) ;6a151234c1409abc + or.b @0x1234:16,@(0x9abcdef0:32,er1) ;6a151234c9409abcdef0 + or.b @0x1234:16,@(0xffff9abc:16,r2l.b) ;6a151234d2409abc + or.b @0x1234:16,@(0xffff9abc:16,r2.w) ;6a151234e2409abc + or.b @0x1234:16,@(0xffff9abc:16,er2.l) ;6a151234f2409abc + or.b @0x1234:16,@(0x9abcdef0:32,r2l.b) ;6a151234da409abcdef0 + or.b @0x1234:16,@(0x9abcdef0:32,r2.w) ;6a151234ea409abcdef0 + or.b @0x1234:16,@(0x9abcdef0:32,er2.l) ;6a151234fa409abcdef0 + or.b @0x1234:16,@0xffff9abc:16 ;6a15123440409abc + or.b @0x1234:16,@0x9abcdef0:32 ;6a15123448409abcdef0 + + or.b @0x12345678:32,@er1 ;6a35123456780140 + or.b @0x12345678:32,@(3:2,er1) ;6a35123456783140 + or.b @0x12345678:32,@-er1 ;6a3512345678b140 + or.b @0x12345678:32,@er1+ ;6a35123456788140 + or.b @0x12345678:32,@er1- ;6a3512345678a140 + or.b @0x12345678:32,@+er1 ;6a35123456789140 + or.b @0x12345678:32,@(0xffff9abc:16,er1) ;6a3512345678c1409abc + or.b @0x12345678:32,@(0x9abcdef0:32,er1) ;6a3512345678c9409abcdef0 + or.b @0x12345678:32,@(0xffff9abc:16,r2l.b) ;6a3512345678d2409abc + or.b @0x12345678:32,@(0xffff9abc:16,r2.w) ;6a3512345678e2409abc + or.b @0x12345678:32,@(0xffff9abc:16,er2.l) ;6a3512345678f2409abc + or.b @0x12345678:32,@(0x9abcdef0:32,r2l.b) ;6a3512345678da409abcdef0 + or.b @0x12345678:32,@(0x9abcdef0:32,r2.w) ;6a3512345678ea409abcdef0 + or.b @0x12345678:32,@(0x9abcdef0:32,er2.l) ;6a3512345678fa409abcdef0 + or.b @0x12345678:32,@0xffff9abc:16 ;6a351234567840409abc + or.b @0x12345678:32,@0x9abcdef0:32 ;6a351234567848409abcdef0 + + or.w #0x1234:16,r1 ;79411234 + or.w #0x1234:16,@er1 ;015e01401234 + or.w #0x1234:16,@(0x6:2,er1) ;015e31401234 + or.w #0x1234:16,@er1+ ;015e81401234 + or.w #0x1234:16,@-er1 ;015eb1401234 + or.w #0x1234:16,@+er1 ;015e91401234 + or.w #0x1234:16,@er1- ;015ea1401234 + or.w #0x1234:16,@(0xffff9abc:16,er1) ;015ec1409abc1234 + or.w #0x1234:16,@(0x9abcdef0:32,er1) ;015ec9409abcdef01234 + or.w #0x1234:16,@(0xffff9abc:16,r2l.b) ;015ed2409abc1234 + or.w #0x1234:16,@(0xffff9abc:16,r2.w) ;015ee2409abc1234 + or.w #0x1234:16,@(0xffff9abc:16,er2.l) ;015ef2409abc1234 + or.w #0x1234:16,@(0x9abcdef0:32,r2l.b) ;015eda409abcdef01234 + or.w #0x1234:16,@(0x9abcdef0:32,r2.w) ;015eea409abcdef01234 + or.w #0x1234:16,@(0x9abcdef0:32,er2.l) ;015efa409abcdef01234 + or.w #0x1234:16,@0xffff9abc:16 ;015e40409abc1234 + or.w #0x1234:16,@0x9abcdef0:32 ;015e48409abcdef01234 + + or.w r3,r1 ;6431 + + or.w r3,@er1 ;7d906430 + or.w r3,@(0x6:2,er1) ;01593143 + or.w r3,@er1+ ;01598143 + or.w r3,@-er1 ;0159b143 + or.w r3,@+er1 ;01599143 + or.w r3,@er1- ;0159a143 + or.w r3,@(0x1234:16,er1) ;0159c1431234 + or.w r3,@(0x12345678:32,er1) ;0159c94312345678 + or.w r3,@(0x1234:16,r2l.b) ;0159d2431234 + or.w r3,@(0x1234:16,r2.w) ;0159e2431234 + or.w r3,@(0x1234:16,er2.l) ;0159f2431234 + or.w r3,@(0x12345678:32,r2l.b) ;0159da4312345678 + or.w r3,@(0x12345678:32,r2.w) ;0159ea4312345678 + or.w r3,@(0x12345678:32,er2.l) ;0159fa4312345678 + or.w r3,@0x1234:16 ;6b1812346430 + or.w r3,@0x12345678:32 ;6b38123456786430 + + or.w @er3,r1 ;7cb06401 + or.w @(0x6:2,er3),r1 ;015a3341 + or.w @er3+,r1 ;015a8341 + or.w @-er3,r1 ;015ab341 + or.w @+er3,r1 ;015a9341 + or.w @er3-,r1 ;015aa341 + or.w @(0x1234:16,er1),r1 ;015ac1411234 + or.w @(0x12345678:32,er1),r1 ;015ac94112345678 + or.w @(0x1234:16,r2l.b),r1 ;015ad2411234 + or.w @(0x1234:16,r2.w),r1 ;015ae2411234 + or.w @(0x1234:16,er2.l),r1 ;015af2411234 + or.w @(0x12345678:32,r2l.b),r1 ;015ada4112345678 + or.w @(0x12345678:32,r2.w),r1 ;015aea4112345678 + or.w @(0x12345678:32,er2.l),r1 ;015afa4112345678 + or.w @0x1234:16,r1 ;6b1012346401 + or.w @0x12345678:32,r1 ;6b30123456786401 + + or.w @er3,@er1 ;7cb50140 + or.w @er3,@(6:2,er1) ;7cb53140 + or.w @er3,@-er1 ;7cb5b140 + or.w @er3,@er1+ ;7cb58140 + or.w @er3,@er1- ;7cb5a140 + or.w @er3,@+er1 ;7cb59140 + or.w @er3,@(0xffff9abc:16,er1) ;7cb5c1409abc + or.w @er3,@(0x9abcdef0:32,er1) ;7cb5c9409abcdef0 + or.w @er3,@(0xffff9abc:16,r2l.b) ;7cb5d2409abc + or.w @er3,@(0xffff9abc:16,r2.w) ;7cb5e2409abc + or.w @er3,@(0xffff9abc:16,er2.l) ;7cb5f2409abc + or.w @er3,@(0x9abcdef0:32,r2l.b) ;7cb5da409abcdef0 + or.w @er3,@(0x9abcdef0:32,r2.w) ;7cb5ea409abcdef0 + or.w @er3,@(0x9abcdef0:32,er2.l) ;7cb5fa409abcdef0 + or.w @er3,@0xffff9abc:16 ;7cb540409abc + or.w @er3,@0x9abcdef0:32 ;7cb548409abcdef0 + + or.w @-er3,@er1 ;01576d3c0140 + or.w @-er3,@(6:2,er1) ;01576d3c3140 + or.w @-er3,@-er1 ;01576d3cb140 + or.w @-er3,@er1+ ;01576d3c8140 + or.w @-er3,@er1- ;01576d3ca140 + or.w @-er3,@+er1 ;01576d3c9140 + or.w @-er3,@(0xffff9abc:16,er1) ;01576d3cc1409abc + or.w @-er3,@(0x9abcdef0:32,er1) ;01576d3cc9409abcdef0 + or.w @-er3,@(0xffff9abc:16,r2l.b) ;01576d3cd2409abc + or.w @-er3,@(0xffff9abc:16,r2.w) ;01576d3ce2409abc + or.w @-er3,@(0xffff9abc:16,er2.l) ;01576d3cf2409abc + or.w @-er3,@(0x9abcdef0:32,r2l.b) ;01576d3cda409abcdef0 + or.w @-er3,@(0x9abcdef0:32,r2.w) ;01576d3cea409abcdef0 + or.w @-er3,@(0x9abcdef0:32,er2.l) ;01576d3cfa409abcdef0 + or.w @-er3,@0xffff9abc:16 ;01576d3c40409abc + or.w @-er3,@0x9abcdef0:32 ;01576d3c48409abcdef0 + + or.w @er3+,@er1 ;01546d3c0140 + or.w @er3+,@(6:2,er1) ;01546d3c3140 + or.w @er3+,@-er1 ;01546d3cb140 + or.w @er3+,@er1+ ;01546d3c8140 + or.w @er3+,@er1- ;01546d3ca140 + or.w @er3+,@+er1 ;01546d3c9140 + or.w @er3+,@(0xffff9abc:16,er1) ;01546d3cc1409abc + or.w @er3+,@(0x9abcdef0:32,er1) ;01546d3cc9409abcdef0 + or.w @er3+,@(0xffff9abc:16,r2l.b) ;01546d3cd2409abc + or.w @er3+,@(0xffff9abc:16,r2.w) ;01546d3ce2409abc + or.w @er3+,@(0xffff9abc:16,er2.l) ;01546d3cf2409abc + or.w @er3+,@(0x9abcdef0:32,r2l.b) ;01546d3cda409abcdef0 + or.w @er3+,@(0x9abcdef0:32,r2.w) ;01546d3cea409abcdef0 + or.w @er3+,@(0x9abcdef0:32,er2.l) ;01546d3cfa409abcdef0 + or.w @er3+,@0xffff9abc:16 ;01546d3c40409abc + or.w @er3+,@0x9abcdef0:32 ;01546d3c48409abcdef0 + + or.w @er3-,@er1 ;01566d3c0140 + or.w @er3-,@(6:2,er1) ;01566d3c3140 + or.w @er3-,@-er1 ;01566d3cb140 + or.w @er3-,@er1+ ;01566d3c8140 + or.w @er3-,@er1- ;01566d3ca140 + or.w @er3-,@+er1 ;01566d3c9140 + or.w @er3-,@(0xffff9abc:16,er1) ;01566d3cc1409abc + or.w @er3-,@(0x9abcdef0:32,er1) ;01566d3cc9409abcdef0 + or.w @er3-,@(0xffff9abc:16,r2l.b) ;01566d3cd2409abc + or.w @er3-,@(0xffff9abc:16,r2.w) ;01566d3ce2409abc + or.w @er3-,@(0xffff9abc:16,er2.l) ;01566d3cf2409abc + or.w @er3-,@(0x9abcdef0:32,r2l.b) ;01566d3cda409abcdef0 + or.w @er3-,@(0x9abcdef0:32,r2.w) ;01566d3cea409abcdef0 + or.w @er3-,@(0x9abcdef0:32,er2.l) ;01566d3cfa409abcdef0 + or.w @er3-,@0xffff9abc:16 ;01566d3c40409abc + or.w @er3-,@0x9abcdef0:32 ;01566d3c48409abcdef0 + + or.w @+er3,@er1 ;01556d3c0140 + or.w @+er3,@(6:2,er1) ;01556d3c3140 + or.w @+er3,@-er1 ;01556d3cb140 + or.w @+er3,@er1+ ;01556d3c8140 + or.w @+er3,@er1- ;01556d3ca140 + or.w @+er3,@+er1 ;01556d3c9140 + or.w @+er3,@(0xffff9abc:16,er1) ;01556d3cc1409abc + or.w @+er3,@(0x9abcdef0:32,er1) ;01556d3cc9409abcdef0 + or.w @+er3,@(0xffff9abc:16,r2l.b) ;01556d3cd2409abc + or.w @+er3,@(0xffff9abc:16,r2.w) ;01556d3ce2409abc + or.w @+er3,@(0xffff9abc:16,er2.l) ;01556d3cf2409abc + or.w @+er3,@(0x9abcdef0:32,r2l.b) ;01556d3cda409abcdef0 + or.w @+er3,@(0x9abcdef0:32,r2.w) ;01556d3cea409abcdef0 + or.w @+er3,@(0x9abcdef0:32,er2.l) ;01556d3cfa409abcdef0 + or.w @+er3,@0xffff9abc:16 ;01556d3c40409abc + or.w @+er3,@0x9abcdef0:32 ;01556d3c48409abcdef0 + + or.w @(0x1234:16,er3),@er1 ;01546f3c12340140 + or.w @(0x1234:16,er3),@(6:2,er1) ;01546f3c12343140 + or.w @(0x1234:16,er3),@-er1 ;01546f3c1234b140 + or.w @(0x1234:16,er3),@er1+ ;01546f3c12348140 + or.w @(0x1234:16,er3),@er1- ;01546f3c1234a140 + or.w @(0x1234:16,er3),@+er1 ;01546f3c12349140 + or.w @(0x1234:16,er3),@(0xffff9abc:16,er1) ;01546f3c1234c1409abc + or.w @(0x1234:16,er3),@(0x9abcdef0:32,er1) ;01546f3c1234c9409abcdef0 + or.w @(0x1234:16,er3),@(0xffff9abc:16,r2l.b) ;01546f3c1234d2409abc + or.w @(0x1234:16,er3),@(0xffff9abc:16,r2.w) ;01546f3c1234e2409abc + or.w @(0x1234:16,er3),@(0xffff9abc:16,er2.l) ;01546f3c1234f2409abc + or.w @(0x1234:16,er3),@(0x9abcdef0:32,r2l.b) ;01546f3c1234da409abcdef0 + or.w @(0x1234:16,er3),@(0x9abcdef0:32,r2.w) ;01546f3c1234ea409abcdef0 + or.w @(0x1234:16,er3),@(0x9abcdef0:32,er2.l) ;01546f3c1234fa409abcdef0 + or.w @(0x1234:16,er3),@0xffff9abc:16 ;01546f3c123440409abc + or.w @(0x1234:16,er3),@0x9abcdef0:32 ;01546f3c123448409abcdef0 + + or.w @(0x12345678:32,er3),@er1 ;78346b2c123456780140 + or.w @(0x12345678:32,er3),@(6:2,er1) ;78346b2c123456783140 + or.w @(0x12345678:32,er3),@-er1 ;78346b2c12345678b140 + or.w @(0x12345678:32,er3),@er1+ ;78346b2c123456788140 + or.w @(0x12345678:32,er3),@er1- ;78346b2c12345678a140 + or.w @(0x12345678:32,er3),@+er1 ;78346b2c123456789140 + or.w @(0x12345678:32,er3),@(0xffff9abc:16,er1) ;78346b2c12345678c1409abc + or.w @(0x12345678:32,er3),@(0x9abcdef0:32,er1) ;78346b2c12345678c9409abcdef0 + or.w @(0x12345678:32,er3),@(0xffff9abc:16,r2l.b) ;78346b2c12345678d2409abc + or.w @(0x12345678:32,er3),@(0xffff9abc:16,r2.w) ;78346b2c12345678e2409abc + or.w @(0x12345678:32,er3),@(0xffff9abc:16,er2.l) ;78346b2c12345678f2409abc + or.w @(0x12345678:32,er3),@(0x9abcdef0:32,r2l.b) ;78346b2c12345678da409abcdef0 + or.w @(0x12345678:32,er3),@(0x9abcdef0:32,r2.w) ;78346b2c12345678ea409abcdef0 + or.w @(0x12345678:32,er3),@(0x9abcdef0:32,er2.l) ;78346b2c12345678fa409abcdef0 + or.w @(0x12345678:32,er3),@0xffff9abc:16 ;78346b2c1234567840409abc + or.w @(0x12345678:32,er3),@0x9abcdef0:32 ;78346b2c1234567848409abcdef0 + + or.w @(0x1234:16,r3l.b),@er1 ;01556f3c12340140 + or.w @(0x1234:16,r3l.b),@(6:2,er1) ;01556f3c12343140 + or.w @(0x1234:16,r3l.b),@-er1 ;01556f3c1234b140 + or.w @(0x1234:16,r3l.b),@er1+ ;01556f3c12348140 + or.w @(0x1234:16,r3l.b),@er1- ;01556f3c1234a140 + or.w @(0x1234:16,r3l.b),@+er1 ;01556f3c12349140 + or.w @(0x1234:16,r3l.b),@(0xffff9abc:16,er1) ;01556f3c1234c1409abc + or.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1) ;01556f3c1234c9409abcdef0 + or.w @(0x1234:16,r3l.b),@(0xffff9abc:16,r2l.b) ;01556f3c1234d2409abc + or.w @(0x1234:16,r3l.b),@(0xffff9abc:16,r2.w) ;01556f3c1234e2409abc + or.w @(0x1234:16,r3l.b),@(0xffff9abc:16,er2.l) ;01556f3c1234f2409abc + or.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2l.b) ;01556f3c1234da409abcdef0 + or.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2.w) ;01556f3c1234ea409abcdef0 + or.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,er2.l) ;01556f3c1234fa409abcdef0 + or.w @(0x1234:16,r3l.b),@0xffff9abc:16 ;01556f3c123440409abc + or.w @(0x1234:16,r3l.b),@0x9abcdef0:32 ;01556f3c123448409abcdef0 + + or.w @(0x1234:16,r3.w),@er1 ;01566f3c12340140 + or.w @(0x1234:16,r3.w),@(6:2,er1) ;01566f3c12343140 + or.w @(0x1234:16,r3.w),@-er1 ;01566f3c1234b140 + or.w @(0x1234:16,r3.w),@er1+ ;01566f3c12348140 + or.w @(0x1234:16,r3.w),@er1- ;01566f3c1234a140 + or.w @(0x1234:16,r3.w),@+er1 ;01566f3c12349140 + or.w @(0x1234:16,r3.w),@(0xffff9abc:16,er1) ;01566f3c1234c1409abc + or.w @(0x1234:16,r3.w),@(0x9abcdef0:32,er1) ;01566f3c1234c9409abcdef0 + or.w @(0x1234:16,r3.w),@(0xffff9abc:16,r2l.b) ;01566f3c1234d2409abc + or.w @(0x1234:16,r3.w),@(0xffff9abc:16,r2.w) ;01566f3c1234e2409abc + or.w @(0x1234:16,r3.w),@(0xffff9abc:16,er2.l) ;01566f3c1234f2409abc + or.w @(0x1234:16,r3.w),@(0x9abcdef0:32,r2l.b) ;01566f3c1234da409abcdef0 + or.w @(0x1234:16,r3.w),@(0x9abcdef0:32,r2.w) ;01566f3c1234ea409abcdef0 + or.w @(0x1234:16,r3.w),@(0x9abcdef0:32,er2.l) ;01566f3c1234fa409abcdef0 + or.w @(0x1234:16,r3.w),@0xffff9abc:16 ;01566f3c123440409abc + or.w @(0x1234:16,r3.w),@0x9abcdef0:32 ;01566f3c123448409abcdef0 + + or.w @(0x1234:16,er3.l),@er1 ;01576f3c12340140 + or.w @(0x1234:16,er3.l),@(6:2,er1) ;01576f3c12343140 + or.w @(0x1234:16,er3.l),@-er1 ;01576f3c1234b140 + or.w @(0x1234:16,er3.l),@er1+ ;01576f3c12348140 + or.w @(0x1234:16,er3.l),@er1- ;01576f3c1234a140 + or.w @(0x1234:16,er3.l),@+er1 ;01576f3c12349140 + or.w @(0x1234:16,er3.l),@(0xffff9abc:16,er1) ;01576f3c1234c1409abc + or.w @(0x1234:16,er3.l),@(0x9abcdef0:32,er1) ;01576f3c1234c9409abcdef0 + or.w @(0x1234:16,er3.l),@(0xffff9abc:16,r2l.b) ;01576f3c1234d2409abc + or.w @(0x1234:16,er3.l),@(0xffff9abc:16,r2.w) ;01576f3c1234e2409abc + or.w @(0x1234:16,er3.l),@(0xffff9abc:16,er2.l) ;01576f3c1234f2409abc + or.w @(0x1234:16,er3.l),@(0x9abcdef0:32,r2l.b) ;01576f3c1234da409abcdef0 + or.w @(0x1234:16,er3.l),@(0x9abcdef0:32,r2.w) ;01576f3c1234ea409abcdef0 + or.w @(0x1234:16,er3.l),@(0x9abcdef0:32,er2.l) ;01576f3c1234fa409abcdef0 + or.w @(0x1234:16,er3.l),@0xffff9abc:16 ;01576f3c123440409abc + or.w @(0x1234:16,er3.l),@0x9abcdef0:32 ;01576f3c123448409abcdef0 + + or.w @(0x12345678:32,r3l.b),@er1 ;78356b2c123456780140 + or.w @(0x12345678:32,r3l.b),@(6:2,er1) ;78356b2c123456783140 + or.w @(0x12345678:32,r3l.b),@-er1 ;78356b2c12345678b140 + or.w @(0x12345678:32,r3l.b),@er1+ ;78356b2c123456788140 + or.w @(0x12345678:32,r3l.b),@er1- ;78356b2c12345678a140 + or.w @(0x12345678:32,r3l.b),@+er1 ;78356b2c123456789140 + or.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,er1) ;78356b2c12345678c1409abc + or.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1) ;78356b2c12345678c9409abcdef0 + or.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2l.b) ;78356b2c12345678d2409abc + or.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2.w) ;78356b2c12345678e2409abc + or.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,er2.l) ;78356b2c12345678f2409abc + or.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2l.b) ;78356b2c12345678da409abcdef0 + or.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2.w) ;78356b2c12345678ea409abcdef0 + or.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er2.l) ;78356b2c12345678fa409abcdef0 + or.w @(0x12345678:32,r3l.b),@0xffff9abc:16 ;78356b2c1234567840409abc + or.w @(0x12345678:32,r3l.b),@0x9abcdef0:32 ;78356b2c1234567848409abcdef0 + + or.w @(0x12345678:32,r3.w),@er1 ;78366b2c123456780140 + or.w @(0x12345678:32,r3.w),@(6:2,er1) ;78366b2c123456783140 + or.w @(0x12345678:32,r3.w),@-er1 ;78366b2c12345678b140 + or.w @(0x12345678:32,r3.w),@er1+ ;78366b2c123456788140 + or.w @(0x12345678:32,r3.w),@er1- ;78366b2c12345678a140 + or.w @(0x12345678:32,r3.w),@+er1 ;78366b2c123456789140 + or.w @(0x12345678:32,r3.w),@(0xffff9abc:16,er1) ;78366b2c12345678c1409abc + or.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1) ;78366b2c12345678c9409abcdef0 + or.w @(0x12345678:32,r3.w),@(0xffff9abc:16,r2l.b) ;78366b2c12345678d2409abc + or.w @(0x12345678:32,r3.w),@(0xffff9abc:16,r2.w) ;78366b2c12345678e2409abc + or.w @(0x12345678:32,r3.w),@(0xffff9abc:16,er2.l) ;78366b2c12345678f2409abc + or.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2l.b) ;78366b2c12345678da409abcdef0 + or.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2.w) ;78366b2c12345678ea409abcdef0 + or.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,er2.l) ;78366b2c12345678fa409abcdef0 + or.w @(0x12345678:32,r3.w),@0xffff9abc:16 ;78366b2c1234567840409abc + or.w @(0x12345678:32,r3.w),@0x9abcdef0:32 ;78366b2c1234567848409abcdef0 + + or.w @(0x12345678:32,er3.l),@er1 ;78376b2c123456780140 + or.w @(0x12345678:32,er3.l),@(6:2,er1) ;78376b2c123456783140 + or.w @(0x12345678:32,er3.l),@-er1 ;78376b2c12345678b140 + or.w @(0x12345678:32,er3.l),@er1+ ;78376b2c123456788140 + or.w @(0x12345678:32,er3.l),@er1- ;78376b2c12345678a140 + or.w @(0x12345678:32,er3.l),@+er1 ;78376b2c123456789140 + or.w @(0x12345678:32,er3.l),@(0xffff9abc:16,er1) ;78376b2c12345678c1409abc + or.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1) ;78376b2c12345678c9409abcdef0 + or.w @(0x12345678:32,er3.l),@(0xffff9abc:16,r2l.b) ;78376b2c12345678d2409abc + or.w @(0x12345678:32,er3.l),@(0xffff9abc:16,r2.w) ;78376b2c12345678e2409abc + or.w @(0x12345678:32,er3.l),@(0xffff9abc:16,er2.l) ;78376b2c12345678f2409abc + or.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2l.b) ;78376b2c12345678da409abcdef0 + or.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2.w) ;78376b2c12345678ea409abcdef0 + or.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,er2.l) ;78376b2c12345678fa409abcdef0 + or.w @(0x12345678:32,er3.l),@0xffff9abc:16 ;78376b2c1234567840409abc + or.w @(0x12345678:32,er3.l),@0x9abcdef0:32 ;78376b2c1234567848409abcdef0 + + or.w @0x1234:16,@er1 ;6b1512340140 + or.w @0x1234:16,@(6:2,er1) ;6b1512343140 + or.w @0x1234:16,@-er1 ;6b151234b140 + or.w @0x1234:16,@er1+ ;6b1512348140 + or.w @0x1234:16,@er1- ;6b151234a140 + or.w @0x1234:16,@+er1 ;6b1512349140 + or.w @0x1234:16,@(0xffff9abc:16,er1) ;6b151234c1409abc + or.w @0x1234:16,@(0x9abcdef0:32,er1) ;6b151234c9409abcdef0 + or.w @0x1234:16,@(0xffff9abc:16,r2l.b) ;6b151234d2409abc + or.w @0x1234:16,@(0xffff9abc:16,r2.w) ;6b151234e2409abc + or.w @0x1234:16,@(0xffff9abc:16,er2.l) ;6b151234f2409abc + or.w @0x1234:16,@(0x9abcdef0:32,r2l.b) ;6b151234da409abcdef0 + or.w @0x1234:16,@(0x9abcdef0:32,r2.w) ;6b151234ea409abcdef0 + or.w @0x1234:16,@(0x9abcdef0:32,er2.l) ;6b151234fa409abcdef0 + or.w @0x1234:16,@0xffff9abc:16 ;6b15123440409abc + or.w @0x1234:16,@0x9abcdef0:32 ;6b15123448409abcdef0 + + or.w @0x12345678:32,@er1 ;6b35123456780140 + or.w @0x12345678:32,@(6:2,er1) ;6b35123456783140 + or.w @0x12345678:32,@-er1 ;6b3512345678b140 + or.w @0x12345678:32,@er1+ ;6b35123456788140 + or.w @0x12345678:32,@er1- ;6b3512345678a140 + or.w @0x12345678:32,@+er1 ;6b35123456789140 + or.w @0x12345678:32,@(0xffff9abc:16,er1) ;6b3512345678c1409abc + or.w @0x12345678:32,@(0x9abcdef0:32,er1) ;6b3512345678c9409abcdef0 + or.w @0x12345678:32,@(0xffff9abc:16,r2l.b) ;6b3512345678d2409abc + or.w @0x12345678:32,@(0xffff9abc:16,r2.w) ;6b3512345678e2409abc + or.w @0x12345678:32,@(0xffff9abc:16,er2.l) ;6b3512345678f2409abc + or.w @0x12345678:32,@(0x9abcdef0:32,r2l.b) ;6b3512345678da409abcdef0 + or.w @0x12345678:32,@(0x9abcdef0:32,r2.w) ;6b3512345678ea409abcdef0 + or.w @0x12345678:32,@(0x9abcdef0:32,er2.l) ;6b3512345678fa409abcdef0 + or.w @0x12345678:32,@0xffff9abc:16 ;6b351234567840409abc + or.w @0x12345678:32,@0x9abcdef0:32 ;6b351234567848409abcdef0 + + or.l #0x12345678:32,er1 ;7a4112345678 + or.l #0x1234:16,er1 ;7a491234 + or.l #0x12345678:32,@er1 ;010e014812345678 + or.l #0x12345678:32,@(0xc:2,er1) ;010e314812345678 + or.l #0x12345678:32,@er1+ ;010e814812345678 + or.l #0x12345678:32,@-er1 ;010eb14812345678 + or.l #0x12345678:32,@+er1 ;010e914812345678 + or.l #0x12345678:32,@er1- ;010ea14812345678 + or.l #0x12345678:32,@(0xffff9abc:16,er1) ;010ec1489abc12345678 + or.l #0x12345678:32,@(0x9abcdef0:32,er1) ;010ec9489abcdef012345678 + or.l #0x12345678:32,@(0xffff9abc:16,r2l.b) ;010ed2489abc12345678 + or.l #0x12345678:32,@(0xffff9abc:16,r2.w) ;010ee2489abc12345678 + or.l #0x12345678:32,@(0xffff9abc:16,er2.l) ;010ef2489abc12345678 + or.l #0x12345678:32,@(0x9abcdef0:32,r2l.b) ;010eda489abcdef012345678 + or.l #0x12345678:32,@(0x9abcdef0:32,r2.w) ;010eea489abcdef012345678 + or.l #0x12345678:32,@(0x9abcdef0:32,er2.l) ;010efa489abcdef012345678 + or.l #0x12345678:32,@0xffff9abc:16 ;010e40489abc12345678 + or.l #0x12345678:32,@0x9abcdef0:32 ;010e48489abcdef012345678 + or.l #0x1234:16,@er1 ;010e01401234 + or.l #0x1234:16,@(0xc:2,er1) ;010e31401234 + or.l #0x1234:16,@er1+ ;010e81401234 + or.l #0x1234:16,@-er1 ;010eb1401234 + or.l #0x1234:16,@+er1 ;010e91401234 + or.l #0x1234:16,@er1- ;010ea1401234 + or.l #0x1234:16,@(0xffff9abc:16,er1) ;010ec1409abc1234 + or.l #0x1234:16,@(0x9abcdef0:32,er1) ;010ec9409abcdef01234 + or.l #0x1234:16,@(0xffff9abc:16,r2l.b) ;010ed2409abc1234 + or.l #0x1234:16,@(0xffff9abc:16,r2.w) ;010ee2409abc1234 + or.l #0x1234:16,@(0xffff9abc:16,er2.l) ;010ef2409abc1234 + or.l #0x1234:16,@(0x9abcdef0:32,r2l.b) ;010eda409abcdef01234 + or.l #0x1234:16,@(0x9abcdef0:32,r2.w) ;010eea409abcdef01234 + or.l #0x1234:16,@(0x9abcdef0:32,er2.l) ;010efa409abcdef01234 + or.l #0x1234:16,@0xffff9abc:16 ;010e40409abc1234 + or.l #0x1234:16,@0x9abcdef0:32 ;010e48409abcdef01234 + + or.l er3,er1 ;01f06431 + + or.l er3,@er1 ;01090143 + or.l er3,@(0xc:2,er1) ;01093143 + or.l er3,@er1+ ;01098143 + or.l er3,@-er1 ;0109b143 + or.l er3,@+er1 ;01099143 + or.l er3,@er1- ;0109a143 + or.l er3,@(0x1234:16,er1) ;0109c1431234 + or.l er3,@(0x12345678:32,er1) ;0109c94312345678 + or.l er3,@(0x1234:16,r2l.b) ;0109d2431234 + or.l er3,@(0x1234:16,r2.w) ;0109e2431234 + or.l er3,@(0x1234:16,er2.l) ;0109f2431234 + or.l er3,@(0x12345678:32,r2l.b) ;0109da4312345678 + or.l er3,@(0x12345678:32,r2.w) ;0109ea4312345678 + or.l er3,@(0x12345678:32,er2.l) ;0109fa4312345678 + or.l er3,@0x1234:16 ;010940431234 + or.l er3,@0x12345678:32 ;0109484312345678 + + or.l @er3,er1 ;010a0341 + or.l @(0xc:2,er3),er1 ;010a3341 + or.l @er3+,er1 ;010a8341 + or.l @-er3,er1 ;010ab341 + or.l @+er3,er1 ;010a9341 + or.l @er3-,er1 ;010aa341 + or.l @(0x1234:16,er1),er1 ;010ac1411234 + or.l @(0x12345678:32,er1),er1 ;010ac94112345678 + or.l @(0x1234:16,r2l.b),er1 ;010ad2411234 + or.l @(0x1234:16,r2.w),er1 ;010ae2411234 + or.l @(0x1234:16,er2.l),er1 ;010af2411234 + or.l @(0x12345678:32,r2l.b),er1 ;010ada4112345678 + or.l @(0x12345678:32,r2.w),er1 ;010aea4112345678 + or.l @(0x12345678:32,er2.l),er1 ;010afa4112345678 + or.l @0x1234:16,er1 ;010a40411234 + or.l @0x12345678:32,er1 ;010a484112345678 + + or.l @er3,@er1 ;0104693c0140 + or.l @er3,@(0xc:2,er1) ;0104693c3140 + or.l @er3,@-er1 ;0104693cb140 + or.l @er3,@er1+ ;0104693c8140 + or.l @er3,@er1- ;0104693ca140 + or.l @er3,@+er1 ;0104693c9140 + or.l @er3,@(0xffff9abc:16,er1) ;0104693cc1409abc + or.l @er3,@(0x9abcdef0:32,er1) ;0104693cc9409abcdef0 + or.l @er3,@(0xffff9abc:16,r2l.b) ;0104693cd2409abc + or.l @er3,@(0xffff9abc:16,r2.w) ;0104693ce2409abc + or.l @er3,@(0xffff9abc:16,er2.l) ;0104693cf2409abc + or.l @er3,@(0x9abcdef0:32,r2l.b) ;0104693cda409abcdef0 + or.l @er3,@(0x9abcdef0:32,r2.w) ;0104693cea409abcdef0 + or.l @er3,@(0x9abcdef0:32,er2.l) ;0104693cfa409abcdef0 + or.l @er3,@0xffff9abc:16 ;0104693c40409abc + or.l @er3,@0x9abcdef0:32 ;0104693c48409abcdef0 + + or.l @(0xc:2,er3),@er1 ;0107693c0140 + or.l @(0xc:2,er3),@(0xc:2,er1) ;0107693c3140 + or.l @(0xc:2,er3),@-er1 ;0107693cb140 + or.l @(0xc:2,er3),@er1+ ;0107693c8140 + or.l @(0xc:2,er3),@er1- ;0107693ca140 + or.l @(0xc:2,er3),@+er1 ;0107693c9140 + or.l @(0xc:2,er3),@(0xffff9abc:16,er1) ;0107693cc1409abc + or.l @(0xc:2,er3),@(0x9abcdef0:32,er1) ;0107693cc9409abcdef0 + or.l @(0xc:2,er3),@(0xffff9abc:16,r2l.b) ;0107693cd2409abc + or.l @(0xc:2,er3),@(0xffff9abc:16,r2.w) ;0107693ce2409abc + or.l @(0xc:2,er3),@(0xffff9abc:16,er2.l) ;0107693cf2409abc + or.l @(0xc:2,er3),@(0x9abcdef0:32,r2l.b) ;0107693cda409abcdef0 + or.l @(0xc:2,er3),@(0x9abcdef0:32,r2.w) ;0107693cea409abcdef0 + or.l @(0xc:2,er3),@(0x9abcdef0:32,er2.l) ;0107693cfa409abcdef0 + or.l @(0xc:2,er3),@0xffff9abc:16 ;0107693c40409abc + or.l @(0xc:2,er3),@0x9abcdef0:32 ;0107693c48409abcdef0 + + or.l @-er3,@er1 ;01076d3c0140 + or.l @-er3,@(0xc:2,er1) ;01076d3c3140 + or.l @-er3,@-er1 ;01076d3cb140 + or.l @-er3,@er1+ ;01076d3c8140 + or.l @-er3,@er1- ;01076d3ca140 + or.l @-er3,@+er1 ;01076d3c9140 + or.l @-er3,@(0xffff9abc:16,er1) ;01076d3cc1409abc + or.l @-er3,@(0x9abcdef0:32,er1) ;01076d3cc9409abcdef0 + or.l @-er3,@(0xffff9abc:16,r2l.b) ;01076d3cd2409abc + or.l @-er3,@(0xffff9abc:16,r2.w) ;01076d3ce2409abc + or.l @-er3,@(0xffff9abc:16,er2.l) ;01076d3cf2409abc + or.l @-er3,@(0x9abcdef0:32,r2l.b) ;01076d3cda409abcdef0 + or.l @-er3,@(0x9abcdef0:32,r2.w) ;01076d3cea409abcdef0 + or.l @-er3,@(0x9abcdef0:32,er2.l) ;01076d3cfa409abcdef0 + or.l @-er3,@0xffff9abc:16 ;01076d3c40409abc + or.l @-er3,@0x9abcdef0:32 ;01076d3c48409abcdef0 + + or.l @er3+,@er1 ;01046d3c0140 + or.l @er3+,@(0xc:2,er1) ;01046d3c3140 + or.l @er3+,@-er1 ;01046d3cb140 + or.l @er3+,@er1+ ;01046d3c8140 + or.l @er3+,@er1- ;01046d3ca140 + or.l @er3+,@+er1 ;01046d3c9140 + or.l @er3+,@(0xffff9abc:16,er1) ;01046d3cc1409abc + or.l @er3+,@(0x9abcdef0:32,er1) ;01046d3cc9409abcdef0 + or.l @er3+,@(0xffff9abc:16,r2l.b) ;01046d3cd2409abc + or.l @er3+,@(0xffff9abc:16,r2.w) ;01046d3ce2409abc + or.l @er3+,@(0xffff9abc:16,er2.l) ;01046d3cf2409abc + or.l @er3+,@(0x9abcdef0:32,r2l.b) ;01046d3cda409abcdef0 + or.l @er3+,@(0x9abcdef0:32,r2.w) ;01046d3cea409abcdef0 + or.l @er3+,@(0x9abcdef0:32,er2.l) ;01046d3cfa409abcdef0 + or.l @er3+,@0xffff9abc:16 ;01046d3c40409abc + or.l @er3+,@0x9abcdef0:32 ;01046d3c48409abcdef0 + + or.l @er3-,@er1 ;01066d3c0140 + or.l @er3-,@(0xc:2,er1) ;01066d3c3140 + or.l @er3-,@-er1 ;01066d3cb140 + or.l @er3-,@er1+ ;01066d3c8140 + or.l @er3-,@er1- ;01066d3ca140 + or.l @er3-,@+er1 ;01066d3c9140 + or.l @er3-,@(0xffff9abc:16,er1) ;01066d3cc1409abc + or.l @er3-,@(0x9abcdef0:32,er1) ;01066d3cc9409abcdef0 + or.l @er3-,@(0xffff9abc:16,r2l.b) ;01066d3cd2409abc + or.l @er3-,@(0xffff9abc:16,r2.w) ;01066d3ce2409abc + or.l @er3-,@(0xffff9abc:16,er2.l) ;01066d3cf2409abc + or.l @er3-,@(0x9abcdef0:32,r2l.b) ;01066d3cda409abcdef0 + or.l @er3-,@(0x9abcdef0:32,r2.w) ;01066d3cea409abcdef0 + or.l @er3-,@(0x9abcdef0:32,er2.l) ;01066d3cfa409abcdef0 + or.l @er3-,@0xffff9abc:16 ;01066d3c40409abc + or.l @er3-,@0x9abcdef0:32 ;01066d3c48409abcdef0 + + or.l @+er3,@er1 ;01056d3c0140 + or.l @+er3,@(0xc:2,er1) ;01056d3c3140 + or.l @+er3,@-er1 ;01056d3cb140 + or.l @+er3,@er1+ ;01056d3c8140 + or.l @+er3,@er1- ;01056d3ca140 + or.l @+er3,@+er1 ;01056d3c9140 + or.l @+er3,@(0xffff9abc:16,er1) ;01056d3cc1409abc + or.l @+er3,@(0x9abcdef0:32,er1) ;01056d3cc9409abcdef0 + or.l @+er3,@(0xffff9abc:16,r2l.b) ;01056d3cd2409abc + or.l @+er3,@(0xffff9abc:16,r2.w) ;01056d3ce2409abc + or.l @+er3,@(0xffff9abc:16,er2.l) ;01056d3cf2409abc + or.l @+er3,@(0x9abcdef0:32,r2l.b) ;01056d3cda409abcdef0 + or.l @+er3,@(0x9abcdef0:32,r2.w) ;01056d3cea409abcdef0 + or.l @+er3,@(0x9abcdef0:32,er2.l) ;01056d3cfa409abcdef0 + or.l @+er3,@0xffff9abc:16 ;01056d3c40409abc + or.l @+er3,@0x9abcdef0:32 ;01056d3c48409abcdef0 + + or.l @(0x1234:16,er3),@er1 ;01046f3c12340140 + or.l @(0x1234:16,er3),@(0xc:2,er1) ;01046f3c12343140 + or.l @(0x1234:16,er3),@-er1 ;01046f3c1234b140 + or.l @(0x1234:16,er3),@er1+ ;01046f3c12348140 + or.l @(0x1234:16,er3),@er1- ;01046f3c1234a140 + or.l @(0x1234:16,er3),@+er1 ;01046f3c12349140 + or.l @(0x1234:16,er3),@(0xffff9abc:16,er1) ;01046f3c1234c1409abc + or.l @(0x1234:16,er3),@(0x9abcdef0:32,er1) ;01046f3c1234c9409abcdef0 + or.l @(0x1234:16,er3),@(0xffff9abc:16,r2l.b) ;01046f3c1234d2409abc + or.l @(0x1234:16,er3),@(0xffff9abc:16,r2.w) ;01046f3c1234e2409abc + or.l @(0x1234:16,er3),@(0xffff9abc:16,er2.l) ;01046f3c1234f2409abc + or.l @(0x1234:16,er3),@(0x9abcdef0:32,r2l.b) ;01046f3c1234da409abcdef0 + or.l @(0x1234:16,er3),@(0x9abcdef0:32,r2.w) ;01046f3c1234ea409abcdef0 + or.l @(0x1234:16,er3),@(0x9abcdef0:32,er2.l) ;01046f3c1234fa409abcdef0 + or.l @(0x1234:16,er3),@0xffff9abc:16 ;01046f3c123440409abc + or.l @(0x1234:16,er3),@0x9abcdef0:32 ;01046f3c123448409abcdef0 + + or.l @(0x12345678:32,er3),@er1 ;78b46b2c123456780140 + or.l @(0x12345678:32,er3),@(0xc:2,er1) ;78b46b2c123456783140 + or.l @(0x12345678:32,er3),@-er1 ;78b46b2c12345678b140 + or.l @(0x12345678:32,er3),@er1+ ;78b46b2c123456788140 + or.l @(0x12345678:32,er3),@er1- ;78b46b2c12345678a140 + or.l @(0x12345678:32,er3),@+er1 ;78b46b2c123456789140 + or.l @(0x12345678:32,er3),@(0xffff9abc:16,er1) ;78b46b2c12345678c1409abc + or.l @(0x12345678:32,er3),@(0x9abcdef0:32,er1) ;78b46b2c12345678c9409abcdef0 + or.l @(0x12345678:32,er3),@(0xffff9abc:16,r2l.b) ;78b46b2c12345678d2409abc + or.l @(0x12345678:32,er3),@(0xffff9abc:16,r2.w) ;78b46b2c12345678e2409abc + or.l @(0x12345678:32,er3),@(0xffff9abc:16,er2.l) ;78b46b2c12345678f2409abc + or.l @(0x12345678:32,er3),@(0x9abcdef0:32,r2l.b) ;78b46b2c12345678da409abcdef0 + or.l @(0x12345678:32,er3),@(0x9abcdef0:32,r2.w) ;78b46b2c12345678ea409abcdef0 + or.l @(0x12345678:32,er3),@(0x9abcdef0:32,er2.l) ;78b46b2c12345678fa409abcdef0 + or.l @(0x12345678:32,er3),@0xffff9abc:16 ;78b46b2c1234567840409abc + or.l @(0x12345678:32,er3),@0x9abcdef0:32 ;78b46b2c1234567848409abcdef0 + + or.l @(0x1234:16,r3l.b),@er1 ;01056f3c12340140 + or.l @(0x1234:16,r3l.b),@(0xc:2,er1) ;01056f3c12343140 + or.l @(0x1234:16,r3l.b),@-er1 ;01056f3c1234b140 + or.l @(0x1234:16,r3l.b),@er1+ ;01056f3c12348140 + or.l @(0x1234:16,r3l.b),@er1- ;01056f3c1234a140 + or.l @(0x1234:16,r3l.b),@+er1 ;01056f3c12349140 + or.l @(0x1234:16,r3l.b),@(0xffff9abc:16,er1) ;01056f3c1234c1409abc + or.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1) ;01056f3c1234c9409abcdef0 + or.l @(0x1234:16,r3l.b),@(0xffff9abc:16,r2l.b) ;01056f3c1234d2409abc + or.l @(0x1234:16,r3l.b),@(0xffff9abc:16,r2.w) ;01056f3c1234e2409abc + or.l @(0x1234:16,r3l.b),@(0xffff9abc:16,er2.l) ;01056f3c1234f2409abc + or.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2l.b) ;01056f3c1234da409abcdef0 + or.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2.w) ;01056f3c1234ea409abcdef0 + or.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,er2.l) ;01056f3c1234fa409abcdef0 + or.l @(0x1234:16,r3l.b),@0xffff9abc:16 ;01056f3c123440409abc + or.l @(0x1234:16,r3l.b),@0x9abcdef0:32 ;01056f3c123448409abcdef0 + + or.l @(0x1234:16,r3.w),@er1 ;01066f3c12340140 + or.l @(0x1234:16,r3.w),@(0xc:2,er1) ;01066f3c12343140 + or.l @(0x1234:16,r3.w),@-er1 ;01066f3c1234b140 + or.l @(0x1234:16,r3.w),@er1+ ;01066f3c12348140 + or.l @(0x1234:16,r3.w),@er1- ;01066f3c1234a140 + or.l @(0x1234:16,r3.w),@+er1 ;01066f3c12349140 + or.l @(0x1234:16,r3.w),@(0xffff9abc:16,er1) ;01066f3c1234c1409abc + or.l @(0x1234:16,r3.w),@(0x9abcdef0:32,er1) ;01066f3c1234c9409abcdef0 + or.l @(0x1234:16,r3.w),@(0xffff9abc:16,r2l.b) ;01066f3c1234d2409abc + or.l @(0x1234:16,r3.w),@(0xffff9abc:16,r2.w) ;01066f3c1234e2409abc + or.l @(0x1234:16,r3.w),@(0xffff9abc:16,er2.l) ;01066f3c1234f2409abc + or.l @(0x1234:16,r3.w),@(0x9abcdef0:32,r2l.b) ;01066f3c1234da409abcdef0 + or.l @(0x1234:16,r3.w),@(0x9abcdef0:32,r2.w) ;01066f3c1234ea409abcdef0 + or.l @(0x1234:16,r3.w),@(0x9abcdef0:32,er2.l) ;01066f3c1234fa409abcdef0 + or.l @(0x1234:16,r3.w),@0xffff9abc:16 ;01066f3c123440409abc + or.l @(0x1234:16,r3.w),@0x9abcdef0:32 ;01066f3c123448409abcdef0 + + or.l @(0x1234:16,er3.l),@er1 ;01076f3c12340140 + or.l @(0x1234:16,er3.l),@(0xc:2,er1) ;01076f3c12343140 + or.l @(0x1234:16,er3.l),@-er1 ;01076f3c1234b140 + or.l @(0x1234:16,er3.l),@er1+ ;01076f3c12348140 + or.l @(0x1234:16,er3.l),@er1- ;01076f3c1234a140 + or.l @(0x1234:16,er3.l),@+er1 ;01076f3c12349140 + or.l @(0x1234:16,er3.l),@(0xffff9abc:16,er1) ;01076f3c1234c1409abc + or.l @(0x1234:16,er3.l),@(0x9abcdef0:32,er1) ;01076f3c1234c9409abcdef0 + or.l @(0x1234:16,er3.l),@(0xffff9abc:16,r2l.b) ;01076f3c1234d2409abc + or.l @(0x1234:16,er3.l),@(0xffff9abc:16,r2.w) ;01076f3c1234e2409abc + or.l @(0x1234:16,er3.l),@(0xffff9abc:16,er2.l) ;01076f3c1234f2409abc + or.l @(0x1234:16,er3.l),@(0x9abcdef0:32,r2l.b) ;01076f3c1234da409abcdef0 + or.l @(0x1234:16,er3.l),@(0x9abcdef0:32,r2.w) ;01076f3c1234ea409abcdef0 + or.l @(0x1234:16,er3.l),@(0x9abcdef0:32,er2.l) ;01076f3c1234fa409abcdef0 + or.l @(0x1234:16,er3.l),@0xffff9abc:16 ;01076f3c123440409abc + or.l @(0x1234:16,er3.l),@0x9abcdef0:32 ;01076f3c123448409abcdef0 + + or.l @(0x12345678:32,r3l.b),@er1 ;78b56b2c123456780140 + or.l @(0x12345678:32,r3l.b),@(0xc:2,er1) ;78b56b2c123456783140 + or.l @(0x12345678:32,r3l.b),@-er1 ;78b56b2c12345678b140 + or.l @(0x12345678:32,r3l.b),@er1+ ;78b56b2c123456788140 + or.l @(0x12345678:32,r3l.b),@er1- ;78b56b2c12345678a140 + or.l @(0x12345678:32,r3l.b),@+er1 ;78b56b2c123456789140 + or.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,er1) ;78b56b2c12345678c1409abc + or.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1) ;78b56b2c12345678c9409abcdef0 + or.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2l.b) ;78b56b2c12345678d2409abc + or.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2.w) ;78b56b2c12345678e2409abc + or.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,er2.l) ;78b56b2c12345678f2409abc + or.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2l.b) ;78b56b2c12345678da409abcdef0 + or.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2.w) ;78b56b2c12345678ea409abcdef0 + or.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er2.l) ;78b56b2c12345678fa409abcdef0 + or.l @(0x12345678:32,r3l.b),@0xffff9abc:16 ;78b56b2c1234567840409abc + or.l @(0x12345678:32,r3l.b),@0x9abcdef0:32 ;78b56b2c1234567848409abcdef0 + + or.l @(0x12345678:32,r3.w),@er1 ;78b66b2c123456780140 + or.l @(0x12345678:32,r3.w),@(0xc:2,er1) ;78b66b2c123456783140 + or.l @(0x12345678:32,r3.w),@-er1 ;78b66b2c12345678b140 + or.l @(0x12345678:32,r3.w),@er1+ ;78b66b2c123456788140 + or.l @(0x12345678:32,r3.w),@er1- ;78b66b2c12345678a140 + or.l @(0x12345678:32,r3.w),@+er1 ;78b66b2c123456789140 + or.l @(0x12345678:32,r3.w),@(0xffff9abc:16,er1) ;78b66b2c12345678c1409abc + or.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1) ;78b66b2c12345678c9409abcdef0 + or.l @(0x12345678:32,r3.w),@(0xffff9abc:16,r2l.b) ;78b66b2c12345678d2409abc + or.l @(0x12345678:32,r3.w),@(0xffff9abc:16,r2.w) ;78b66b2c12345678e2409abc + or.l @(0x12345678:32,r3.w),@(0xffff9abc:16,er2.l) ;78b66b2c12345678f2409abc + or.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2l.b) ;78b66b2c12345678da409abcdef0 + or.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2.w) ;78b66b2c12345678ea409abcdef0 + or.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,er2.l) ;78b66b2c12345678fa409abcdef0 + or.l @(0x12345678:32,r3.w),@0xffff9abc:16 ;78b66b2c1234567840409abc + or.l @(0x12345678:32,r3.w),@0x9abcdef0:32 ;78b66b2c1234567848409abcdef0 + + or.l @(0x12345678:32,er3.l),@er1 ;78b76b2c123456780140 + or.l @(0x12345678:32,er3.l),@(0xc:2,er1) ;78b76b2c123456783140 + or.l @(0x12345678:32,er3.l),@-er1 ;78b76b2c12345678b140 + or.l @(0x12345678:32,er3.l),@er1+ ;78b76b2c123456788140 + or.l @(0x12345678:32,er3.l),@er1- ;78b76b2c12345678a140 + or.l @(0x12345678:32,er3.l),@+er1 ;78b76b2c123456789140 + or.l @(0x12345678:32,er3.l),@(0xffff9abc:16,er1) ;78b76b2c12345678c1409abc + or.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1) ;78b76b2c12345678c9409abcdef0 + or.l @(0x12345678:32,er3.l),@(0xffff9abc:16,r2l.b) ;78b76b2c12345678d2409abc + or.l @(0x12345678:32,er3.l),@(0xffff9abc:16,r2.w) ;78b76b2c12345678e2409abc + or.l @(0x12345678:32,er3.l),@(0xffff9abc:16,er2.l) ;78b76b2c12345678f2409abc + or.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2l.b) ;78b76b2c12345678da409abcdef0 + or.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2.w) ;78b76b2c12345678ea409abcdef0 + or.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,er2.l) ;78b76b2c12345678fa409abcdef0 + or.l @(0x12345678:32,er3.l),@0xffff9abc:16 ;78b76b2c1234567840409abc + or.l @(0x12345678:32,er3.l),@0x9abcdef0:32 ;78b76b2c1234567848409abcdef0 + + or.l @0x1234:16,@er1 ;01046b0c12340140 + or.l @0x1234:16,@(0xc:2,er1) ;01046b0c12343140 + or.l @0x1234:16,@-er1 ;01046b0c1234b140 + or.l @0x1234:16,@er1+ ;01046b0c12348140 + or.l @0x1234:16,@er1- ;01046b0c1234a140 + or.l @0x1234:16,@+er1 ;01046b0c12349140 + or.l @0x1234:16,@(0xffff9abc:16,er1) ;01046b0c1234c1409abc + or.l @0x1234:16,@(0x9abcdef0:32,er1) ;01046b0c1234c9409abcdef0 + or.l @0x1234:16,@(0xffff9abc:16,r2l.b) ;01046b0c1234d2409abc + or.l @0x1234:16,@(0xffff9abc:16,r2.w) ;01046b0c1234e2409abc + or.l @0x1234:16,@(0xffff9abc:16,er2.l) ;01046b0c1234f2409abc + or.l @0x1234:16,@(0x9abcdef0:32,r2l.b) ;01046b0c1234da409abcdef0 + or.l @0x1234:16,@(0x9abcdef0:32,r2.w) ;01046b0c1234ea409abcdef0 + or.l @0x1234:16,@(0x9abcdef0:32,er2.l) ;01046b0c1234fa409abcdef0 + or.l @0x1234:16,@0xffff9abc:16 ;01046b0c123440409abc + or.l @0x1234:16,@0x9abcdef0:32 ;01046b0c123448409abcdef0 + + or.l @0x12345678:32,@er1 ;01046b2c123456780140 + or.l @0x12345678:32,@(0xc:2,er1) ;01046b2c123456783140 + or.l @0x12345678:32,@-er1 ;01046b2c12345678b140 + or.l @0x12345678:32,@er1+ ;01046b2c123456788140 + or.l @0x12345678:32,@er1- ;01046b2c12345678a140 + or.l @0x12345678:32,@+er1 ;01046b2c123456789140 + or.l @0x12345678:32,@(0xffff9abc:16,er1) ;01046b2c12345678c1409abc + or.l @0x12345678:32,@(0x9abcdef0:32,er1) ;01046b2c12345678c9409abcdef0 + or.l @0x12345678:32,@(0xffff9abc:16,r2l.b) ;01046b2c12345678d2409abc + or.l @0x12345678:32,@(0xffff9abc:16,r2.w) ;01046b2c12345678e2409abc + or.l @0x12345678:32,@(0xffff9abc:16,er2.l) ;01046b2c12345678f2409abc + or.l @0x12345678:32,@(0x9abcdef0:32,r2l.b) ;01046b2c12345678da409abcdef0 + or.l @0x12345678:32,@(0x9abcdef0:32,r2.w) ;01046b2c12345678ea409abcdef0 + or.l @0x12345678:32,@(0x9abcdef0:32,er2.l) ;01046b2c12345678fa409abcdef0 + or.l @0x12345678:32,@0xffff9abc:16 ;01046b2c1234567840409abc + or.l @0x12345678:32,@0x9abcdef0:32 ;01046b2c1234567848409abcdef0 + + .end diff --git a/gdb/testsuite/gdb.disasm/t09_xor.exp b/gdb/testsuite/gdb.disasm/t09_xor.exp new file mode 100644 index 0000000..0164b33 --- /dev/null +++ b/gdb/testsuite/gdb.disasm/t09_xor.exp @@ -0,0 +1,1866 @@ +# Copyright (C) 2003 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# Please email any bugs, comments, and/or additions to this file to: +# bug-gdb@prep.ai.mit.edu + +# This file was written by Michael Snyder (msnyder@redhat.com) + +if $tracelevel then { + strace $tracelevel +} + +if ![istarget "h8300*-*-*"] { + verbose "Tests ignored for all but h8300s based targets." + return +} + +set prms_id 0 +set bug_id 0 + +set testfile "t09_xor" +set srcfile ${srcdir}/${subdir}/${testfile}.s +set objfile ${objdir}/${subdir}/${testfile}.o +set binfile ${objdir}/${subdir}/${testfile}.x + +set asm-flags ""; +set link-flags "-m h8300sxelf"; + + +if {[target_assemble $srcfile $objfile "${asm-flags}"] != ""} then { + gdb_suppress_entire_file "Testcase assembly failed, so all tests in this file will automatically fail." +} + +if {[target_link $objfile $binfile "${link-flags}"] != ""} then { + gdb_suppress_entire_file "Testcase link failed, so all tests in this file will automatically fail." +} + +gdb_start +gdb_reinitialize_dir $srcdir/$subdir +gdb_load $binfile + +gdb_test "x /i _start" "xor.b\t#0x12(:8|),r1h" \ + "xor.b #0x12:8,r1h" +gdb_test "x" "xor.b\t#0x12(:8|),@er1" \ + "xor.b #0x12:8,@er1" +gdb_test "x" "xor.b\t#0x12(:8|),@\\(0x3(:2|),er1\\)" \ + "xor.b #0x12:8,@(0x3:2,er1)" +gdb_test "x" "xor.b\t#0x12(:8|),@er1\\+" \ + "xor.b #0x12:8,@er1+" +gdb_test "x" "xor.b\t#0x12(:8|),@-er1" \ + "xor.b #0x12:8,@-er1" +gdb_test "x" "xor.b\t#0x12(:8|),@\\+er1" \ + "xor.b #0x12:8,@+er1" +gdb_test "x" "xor.b\t#0x12(:8|),@er1-" \ + "xor.b #0x12:8,@er1-" +gdb_test "x" "xor.b\t#0x12(:8|),@\\(0x1234(:16|),er1\\)" \ + "xor.b #0x12:8,@(0x1234:16,er1)" +gdb_test "x" "xor.b\t#0x12(:8|),@\\(0x12345678(:32|),er1\\)" \ + "xor.b #0x12:8,@(0x12345678:32,er1)" +gdb_test "x" "xor.b\t#0x12(:8|),@\\(0x1234(:16|),r2l.b\\)" \ + "xor.b #0x12:8,@(0x1234:16,r2l.b)" +gdb_test "x" "xor.b\t#0x12(:8|),@\\(0x1234(:16|),r2.w\\)" \ + "xor.b #0x12:8,@(0x1234:16,r2.w)" +gdb_test "x" "xor.b\t#0x12(:8|),@\\(0x1234(:16|),er2.l\\)" \ + "xor.b #0x12:8,@(0x1234:16,er2.l)" +gdb_test "x" "xor.b\t#0x12(:8|),@\\(0x12345678(:32|),r2l.b\\)" \ + "xor.b #0x12:8,@(0x12345678:32,r2l.b)" +gdb_test "x" "xor.b\t#0x12(:8|),@\\(0x12345678(:32|),r2.w\\)" \ + "xor.b #0x12:8,@(0x12345678:32,r2.w)" +gdb_test "x" "xor.b\t#0x12(:8|),@\\(0x12345678(:32|),er2.l\\)" \ + "xor.b #0x12:8,@(0x12345678:32,er2.l)" +gdb_test "x" "xor.b\t#0x12(:8|),@0x12(:8|)" \ + "xor.b #0x12:8,@0x12:8" +gdb_test "x" "xor.b\t#0x12(:8|),@0x1234(:16|)" \ + "xor.b #0x12:8,@0x1234:16" +gdb_test "x" "xor.b\t#0x12(:8|),@0x12345678(:32|)" \ + "xor.b #0x12:8,@0x12345678:32" +gdb_test "x" "xor.b\tr3h,r1h" \ + "xor.b r3h,r1h" +gdb_test "x" "xor.b\tr3h,@er1" \ + "xor.b r3h,@er1" +gdb_test "x" "xor.b\tr3h,@\\(0x3(:2|),er1\\)" \ + "xor.b r3h,@(0x3:2,er1)" +gdb_test "x" "xor.b\tr3h,@er1\\+" \ + "xor.b r3h,@er1+" +gdb_test "x" "xor.b\tr3h,@-er1" \ + "xor.b r3h,@-er1" +gdb_test "x" "xor.b\tr3h,@\\+er1" \ + "xor.b r3h,@+er1" +gdb_test "x" "xor.b\tr3h,@er1-" \ + "xor.b r3h,@er1-" +gdb_test "x" "xor.b\tr3h,@\\(0x1234(:16|),er1\\)" \ + "xor.b r3h,@(0x1234:16,er1)" +gdb_test "x" "xor.b\tr3h,@\\(0x12345678(:32|),er1\\)" \ + "xor.b r3h,@(0x12345678:32,er1)" +gdb_test "x" "xor.b\tr3h,@\\(0x1234(:16|),r2l.b\\)" \ + "xor.b r3h,@(0x1234:16,r2l.b)" +gdb_test "x" "xor.b\tr3h,@\\(0x1234(:16|),r2.w\\)" \ + "xor.b r3h,@(0x1234:16,r2.w)" +gdb_test "x" "xor.b\tr3h,@\\(0x1234(:16|),er2.l\\)" \ + "xor.b r3h,@(0x1234:16,er2.l)" +gdb_test "x" "xor.b\tr3h,@\\(0x12345678(:32|),r2l.b\\)" \ + "xor.b r3h,@(0x12345678:32,r2l.b)" +gdb_test "x" "xor.b\tr3h,@\\(0x12345678(:32|),r2.w\\)" \ + "xor.b r3h,@(0x12345678:32,r2.w)" +gdb_test "x" "xor.b\tr3h,@\\(0x12345678(:32|),er2.l\\)" \ + "xor.b r3h,@(0x12345678:32,er2.l)" +gdb_test "x" "xor.b\tr3h,@0x12(:8|)" \ + "xor.b r3h,@0x12:8" +gdb_test "x" "xor.b\tr3h,@0x1234(:16|)" \ + "xor.b r3h,@0x1234:16" +gdb_test "x" "xor.b\tr3h,@0x12345678(:32|)" \ + "xor.b r3h,@0x12345678:32" +gdb_test "x" "xor.b\t@er3,r1h" \ + "xor.b @er3,r1h" +gdb_test "x" "xor.b\t@\\(0x3(:2|),er3\\),r1h" \ + "xor.b @(0x3:2,er3),r1h" +gdb_test "x" "xor.b\t@er3\\+,r1h" \ + "xor.b @er3+,r1h" +gdb_test "x" "xor.b\t@-er3,r1h" \ + "xor.b @-er3,r1h" +gdb_test "x" "xor.b\t@\\+er3,r1h" \ + "xor.b @+er3,r1h" +gdb_test "x" "xor.b\t@er3-,r1h" \ + "xor.b @er3-,r1h" +gdb_test "x" "xor.b\t@\\(0x1234(:16|),er1\\),r1h" \ + "xor.b @(0x1234:16,er1),r1h" +gdb_test "x" "xor.b\t@\\(0x12345678(:32|),er1\\),r1h" \ + "xor.b @(0x12345678:32,er1),r1h" +gdb_test "x" "xor.b\t@\\(0x1234(:16|),r2l.b\\),r1h" \ + "xor.b @(0x1234:16,r2l.b),r1h" +gdb_test "x" "xor.b\t@\\(0x1234(:16|),r2.w\\),r1h" \ + "xor.b @(0x1234:16,r2.w),r1h" +gdb_test "x" "xor.b\t@\\(0x1234(:16|),er2.l\\),r1h" \ + "xor.b @(0x1234:16,er2.l),r1h" +gdb_test "x" "xor.b\t@\\(0x12345678(:32|),r2l.b\\),r1h" \ + "xor.b @(0x12345678:32,r2l.b),r1h" +gdb_test "x" "xor.b\t@\\(0x12345678(:32|),r2.w\\),r1h" \ + "xor.b @(0x12345678:32,r2.w),r1h" +gdb_test "x" "xor.b\t@\\(0x12345678(:32|),er2.l\\),r1h" \ + "xor.b @(0x12345678:32,er2.l),r1h" +gdb_test "x" "xor.b\t@0x12(:8|),r1h" \ + "xor.b @0x12:8,r1h" +gdb_test "x" "xor.b\t@0x1234(:16|),r1h" \ + "xor.b @0x1234:16,r1h" +gdb_test "x" "xor.b\t@0x12345678(:32|),r1h" \ + "xor.b @0x12345678:32,r1h" +gdb_test "x" "xor.b\t@er3,@er1" \ + "xor.b @er3,@er1" +gdb_test "x" "xor.b\t@er3,@\\(0x3(:2|),er1\\)" \ + "xor.b @er3,@(0x3:2,er1)" +gdb_test "x" "xor.b\t@er3,@-er1" \ + "xor.b @er3,@-er1" +gdb_test "x" "xor.b\t@er3,@er1\\+" \ + "xor.b @er3,@er1+" +gdb_test "x" "xor.b\t@er3,@er1-" \ + "xor.b @er3,@er1-" +gdb_test "x" "xor.b\t@er3,@\\+er1" \ + "xor.b @er3,@+er1" +gdb_test "x" "xor.b\t@er3,@\\(0x9abc(:16|),er1\\)" \ + "xor.b @er3,@(0x9abc:16,er1)" +gdb_test "x" "xor.b\t@er3,@\\(0x9abcdef0(:32|),er1\\)" \ + "xor.b @er3,@(0x9abcdef0:32,er1)" +gdb_test "x" "xor.b\t@er3,@\\(0x9abc(:16|),r2l.b\\)" \ + "xor.b @er3,@(0x9abc:16,r2l.b)" +gdb_test "x" "xor.b\t@er3,@\\(0x9abc(:16|),r2.w\\)" \ + "xor.b @er3,@(0x9abc:16,r2.w)" +gdb_test "x" "xor.b\t@er3,@\\(0x9abc(:16|),er2.l\\)" \ + "xor.b @er3,@(0x9abc:16,er2.l)" +gdb_test "x" "xor.b\t@er3,@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "xor.b @er3,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "xor.b\t@er3,@\\(0x9abcdef0(:32|),r2.w\\)" \ + "xor.b @er3,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "xor.b\t@er3,@\\(0x9abcdef0(:32|),er2.l\\)" \ + "xor.b @er3,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "xor.b\t@er3,@0x9abc(:16|)" \ + "xor.b @er3,@0x9abc:16" +gdb_test "x" "xor.b\t@er3,@0x9abcdef0(:32|)" \ + "xor.b @er3,@0x9abcdef0:32" +gdb_test "x" "xor.b\t@-er3,@er1" \ + "xor.b @-er3,@er1" +gdb_test "x" "xor.b\t@-er3,@\\(0x3(:2|),er1\\)" \ + "xor.b @-er3,@(0x3:2,er1)" +gdb_test "x" "xor.b\t@-er3,@-er1" \ + "xor.b @-er3,@-er1" +gdb_test "x" "xor.b\t@-er3,@er1\\+" \ + "xor.b @-er3,@er1+" +gdb_test "x" "xor.b\t@-er3,@er1-" \ + "xor.b @-er3,@er1-" +gdb_test "x" "xor.b\t@-er3,@\\+er1" \ + "xor.b @-er3,@+er1" +gdb_test "x" "xor.b\t@-er3,@\\(0x9abc(:16|),er1\\)" \ + "xor.b @-er3,@(0x9abc:16,er1)" +gdb_test "x" "xor.b\t@-er3,@\\(0x9abcdef0(:32|),er1\\)" \ + "xor.b @-er3,@(0x9abcdef0:32,er1)" +gdb_test "x" "xor.b\t@-er3,@\\(0x9abc(:16|),r2l.b\\)" \ + "xor.b @-er3,@(0x9abc:16,r2l.b)" +gdb_test "x" "xor.b\t@-er3,@\\(0x9abc(:16|),r2.w\\)" \ + "xor.b @-er3,@(0x9abc:16,r2.w)" +gdb_test "x" "xor.b\t@-er3,@\\(0x9abc(:16|),er2.l\\)" \ + "xor.b @-er3,@(0x9abc:16,er2.l)" +gdb_test "x" "xor.b\t@-er3,@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "xor.b @-er3,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "xor.b\t@-er3,@\\(0x9abcdef0(:32|),r2.w\\)" \ + "xor.b @-er3,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "xor.b\t@-er3,@\\(0x9abcdef0(:32|),er2.l\\)" \ + "xor.b @-er3,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "xor.b\t@-er3,@0x9abc(:16|)" \ + "xor.b @-er3,@0x9abc:16" +gdb_test "x" "xor.b\t@-er3,@0x9abcdef0(:32|)" \ + "xor.b @-er3,@0x9abcdef0:32" +gdb_test "x" "xor.b\t@er3\\+,@er1" \ + "xor.b @er3+,@er1" +gdb_test "x" "xor.b\t@er3\\+,@\\(0x3(:2|),er1\\)" \ + "xor.b @er3+,@(0x3:2,er1)" +gdb_test "x" "xor.b\t@er3\\+,@-er1" \ + "xor.b @er3+,@-er1" +gdb_test "x" "xor.b\t@er3\\+,@er1\\+" \ + "xor.b @er3+,@er1+" +gdb_test "x" "xor.b\t@er3\\+,@er1-" \ + "xor.b @er3+,@er1-" +gdb_test "x" "xor.b\t@er3\\+,@\\+er1" \ + "xor.b @er3+,@+er1" +gdb_test "x" "xor.b\t@er3\\+,@\\(0x9abc(:16|),er1\\)" \ + "xor.b @er3+,@(0x9abc:16,er1)" +gdb_test "x" "xor.b\t@er3\\+,@\\(0x9abcdef0(:32|),er1\\)" \ + "xor.b @er3+,@(0x9abcdef0:32,er1)" +gdb_test "x" "xor.b\t@er3\\+,@\\(0x9abc(:16|),r2l.b\\)" \ + "xor.b @er3+,@(0x9abc:16,r2l.b)" +gdb_test "x" "xor.b\t@er3\\+,@\\(0x9abc(:16|),r2.w\\)" \ + "xor.b @er3+,@(0x9abc:16,r2.w)" +gdb_test "x" "xor.b\t@er3\\+,@\\(0x9abc(:16|),er2.l\\)" \ + "xor.b @er3+,@(0x9abc:16,er2.l)" +gdb_test "x" "xor.b\t@er3\\+,@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "xor.b @er3+,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "xor.b\t@er3\\+,@\\(0x9abcdef0(:32|),r2.w\\)" \ + "xor.b @er3+,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "xor.b\t@er3\\+,@\\(0x9abcdef0(:32|),er2.l\\)" \ + "xor.b @er3+,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "xor.b\t@er3\\+,@0x9abc(:16|)" \ + "xor.b @er3+,@0x9abc:16" +gdb_test "x" "xor.b\t@er3\\+,@0x9abcdef0(:32|)" \ + "xor.b @er3+,@0x9abcdef0:32" +gdb_test "x" "xor.b\t@er3-,@er1" \ + "xor.b @er3-,@er1" +gdb_test "x" "xor.b\t@er3-,@\\(0x3(:2|),er1\\)" \ + "xor.b @er3-,@(0x3:2,er1)" +gdb_test "x" "xor.b\t@er3-,@-er1" \ + "xor.b @er3-,@-er1" +gdb_test "x" "xor.b\t@er3-,@er1\\+" \ + "xor.b @er3-,@er1+" +gdb_test "x" "xor.b\t@er3-,@er1-" \ + "xor.b @er3-,@er1-" +gdb_test "x" "xor.b\t@er3-,@\\+er1" \ + "xor.b @er3-,@+er1" +gdb_test "x" "xor.b\t@er3-,@\\(0x9abc(:16|),er1\\)" \ + "xor.b @er3-,@(0x9abc:16,er1)" +gdb_test "x" "xor.b\t@er3-,@\\(0x9abcdef0(:32|),er1\\)" \ + "xor.b @er3-,@(0x9abcdef0:32,er1)" +gdb_test "x" "xor.b\t@er3-,@\\(0x9abc(:16|),r2l.b\\)" \ + "xor.b @er3-,@(0x9abc:16,r2l.b)" +gdb_test "x" "xor.b\t@er3-,@\\(0x9abc(:16|),r2.w\\)" \ + "xor.b @er3-,@(0x9abc:16,r2.w)" +gdb_test "x" "xor.b\t@er3-,@\\(0x9abc(:16|),er2.l\\)" \ + "xor.b @er3-,@(0x9abc:16,er2.l)" +gdb_test "x" "xor.b\t@er3-,@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "xor.b @er3-,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "xor.b\t@er3-,@\\(0x9abcdef0(:32|),r2.w\\)" \ + "xor.b @er3-,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "xor.b\t@er3-,@\\(0x9abcdef0(:32|),er2.l\\)" \ + "xor.b @er3-,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "xor.b\t@er3-,@0x9abc(:16|)" \ + "xor.b @er3-,@0x9abc:16" +gdb_test "x" "xor.b\t@er3-,@0x9abcdef0(:32|)" \ + "xor.b @er3-,@0x9abcdef0:32" +gdb_test "x" "xor.b\t@\\+er3,@er1" \ + "xor.b @+er3,@er1" +gdb_test "x" "xor.b\t@\\+er3,@\\(0x3(:2|),er1\\)" \ + "xor.b @+er3,@(0x3:2,er1)" +gdb_test "x" "xor.b\t@\\+er3,@-er1" \ + "xor.b @+er3,@-er1" +gdb_test "x" "xor.b\t@\\+er3,@er1\\+" \ + "xor.b @+er3,@er1+" +gdb_test "x" "xor.b\t@\\+er3,@er1-" \ + "xor.b @+er3,@er1-" +gdb_test "x" "xor.b\t@\\+er3,@\\+er1" \ + "xor.b @+er3,@+er1" +gdb_test "x" "xor.b\t@\\+er3,@\\(0x9abc(:16|),er1\\)" \ + "xor.b @+er3,@(0x9abc:16,er1)" +gdb_test "x" "xor.b\t@\\+er3,@\\(0x9abcdef0(:32|),er1\\)" \ + "xor.b @+er3,@(0x9abcdef0:32,er1)" +gdb_test "x" "xor.b\t@\\+er3,@\\(0x9abc(:16|),r2l.b\\)" \ + "xor.b @+er3,@(0x9abc:16,r2l.b)" +gdb_test "x" "xor.b\t@\\+er3,@\\(0x9abc(:16|),r2.w\\)" \ + "xor.b @+er3,@(0x9abc:16,r2.w)" +gdb_test "x" "xor.b\t@\\+er3,@\\(0x9abc(:16|),er2.l\\)" \ + "xor.b @+er3,@(0x9abc:16,er2.l)" +gdb_test "x" "xor.b\t@\\+er3,@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "xor.b @+er3,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "xor.b\t@\\+er3,@\\(0x9abcdef0(:32|),r2.w\\)" \ + "xor.b @+er3,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "xor.b\t@\\+er3,@\\(0x9abcdef0(:32|),er2.l\\)" \ + "xor.b @+er3,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "xor.b\t@\\+er3,@0x9abc(:16|)" \ + "xor.b @+er3,@0x9abc:16" +gdb_test "x" "xor.b\t@\\+er3,@0x9abcdef0(:32|)" \ + "xor.b @+er3,@0x9abcdef0:32" +gdb_test "x" "xor.b\t@\\(0x1234(:16|),er3\\),@er1" \ + "xor.b @(0x1234:16,er3),@er1" +gdb_test "x" "xor.b\t@\\(0x1234(:16|),er3\\),@\\(0x3(:2|),er1\\)" \ + "xor.b @(0x1234:16,er3),@(0x3:2,er1)" +gdb_test "x" "xor.b\t@\\(0x1234(:16|),er3\\),@-er1" \ + "xor.b @(0x1234:16,er3),@-er1" +gdb_test "x" "xor.b\t@\\(0x1234(:16|),er3\\),@er1\\+" \ + "xor.b @(0x1234:16,er3),@er1+" +gdb_test "x" "xor.b\t@\\(0x1234(:16|),er3\\),@er1-" \ + "xor.b @(0x1234:16,er3),@er1-" +gdb_test "x" "xor.b\t@\\(0x1234(:16|),er3\\),@\\+er1" \ + "xor.b @(0x1234:16,er3),@+er1" +gdb_test "x" "xor.b\t@\\(0x1234(:16|),er3\\),@\\(0x9abc(:16|),er1\\)" \ + "xor.b @(0x1234:16,er3),@(0x9abc:16,er1)" +gdb_test "x" "xor.b\t@\\(0x1234(:16|),er3\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "xor.b @(0x1234:16,er3),@(0x9abcdef0:32,er1)" +gdb_test "x" "xor.b\t@\\(0x1234(:16|),er3\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "xor.b @(0x1234:16,er3),@(0x9abc:16,r2l.b)" +gdb_test "x" "xor.b\t@\\(0x1234(:16|),er3\\),@\\(0x9abc(:16|),r2.w\\)" \ + "xor.b @(0x1234:16,er3),@(0x9abc:16,r2.w)" +gdb_test "x" "xor.b\t@\\(0x1234(:16|),er3\\),@\\(0x9abc(:16|),er2.l\\)" \ + "xor.b @(0x1234:16,er3),@(0x9abc:16,er2.l)" +gdb_test "x" "xor.b\t@\\(0x1234(:16|),er3\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "xor.b @(0x1234:16,er3),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "xor.b\t@\\(0x1234(:16|),er3\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "xor.b @(0x1234:16,er3),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "xor.b\t@\\(0x1234(:16|),er3\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "xor.b @(0x1234:16,er3),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "xor.b\t@\\(0x1234(:16|),er3\\),@0x9abc(:16|)" \ + "xor.b @(0x1234:16,er3),@0x9abc:16" +gdb_test "x" "xor.b\t@\\(0x1234(:16|),er3\\),@0x9abcdef0(:32|)" \ + "xor.b @(0x1234:16,er3),@0x9abcdef0:32" +gdb_test "x" "xor.b\t@\\(0x12345678(:32|),er3\\),@er1" \ + "xor.b @(0x12345678:32,er3),@er1" +gdb_test "x" "xor.b\t@\\(0x12345678(:32|),er3\\),@\\(0x3(:2|),er1\\)" \ + "xor.b @(0x12345678:32,er3),@(0x3:2,er1)" +gdb_test "x" "xor.b\t@\\(0x12345678(:32|),er3\\),@-er1" \ + "xor.b @(0x12345678:32,er3),@-er1" +gdb_test "x" "xor.b\t@\\(0x12345678(:32|),er3\\),@er1\\+" \ + "xor.b @(0x12345678:32,er3),@er1+" +gdb_test "x" "xor.b\t@\\(0x12345678(:32|),er3\\),@er1-" \ + "xor.b @(0x12345678:32,er3),@er1-" +gdb_test "x" "xor.b\t@\\(0x12345678(:32|),er3\\),@\\+er1" \ + "xor.b @(0x12345678:32,er3),@+er1" +gdb_test "x" "xor.b\t@\\(0x12345678(:32|),er3\\),@\\(0x9abc(:16|),er1\\)" \ + "xor.b @(0x12345678:32,er3),@(0x9abc:16,er1)" +gdb_test "x" "xor.b\t@\\(0x12345678(:32|),er3\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "xor.b @(0x12345678:32,er3),@(0x9abcdef0:32,er1)" +gdb_test "x" "xor.b\t@\\(0x12345678(:32|),er3\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "xor.b @(0x12345678:32,er3),@(0x9abc:16,r2l.b)" +gdb_test "x" "xor.b\t@\\(0x12345678(:32|),er3\\),@\\(0x9abc(:16|),r2.w\\)" \ + "xor.b @(0x12345678:32,er3),@(0x9abc:16,r2.w)" +gdb_test "x" "xor.b\t@\\(0x12345678(:32|),er3\\),@\\(0x9abc(:16|),er2.l\\)" \ + "xor.b @(0x12345678:32,er3),@(0x9abc:16,er2.l)" +gdb_test "x" "xor.b\t@\\(0x12345678(:32|),er3\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "xor.b @(0x12345678:32,er3),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "xor.b\t@\\(0x12345678(:32|),er3\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "xor.b @(0x12345678:32,er3),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "xor.b\t@\\(0x12345678(:32|),er3\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "xor.b @(0x12345678:32,er3),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "xor.b\t@\\(0x12345678(:32|),er3\\),@0x9abc(:16|)" \ + "xor.b @(0x12345678:32,er3),@0x9abc:16" +gdb_test "x" "xor.b\t@\\(0x12345678(:32|),er3\\),@0x9abcdef0(:32|)" \ + "xor.b @(0x12345678:32,er3),@0x9abcdef0:32" +gdb_test "x" "xor.b\t@\\(0x1234(:16|),r3l.b\\),@er1" \ + "xor.b @(0x1234:16,r3l.b),@er1" +gdb_test "x" "xor.b\t@\\(0x1234(:16|),r3l.b\\),@\\(0x3(:2|),er1\\)" \ + "xor.b @(0x1234:16,r3l.b),@(0x3:2,er1)" +gdb_test "x" "xor.b\t@\\(0x1234(:16|),r3l.b\\),@-er1" \ + "xor.b @(0x1234:16,r3l.b),@-er1" +gdb_test "x" "xor.b\t@\\(0x1234(:16|),r3l.b\\),@er1\\+" \ + "xor.b @(0x1234:16,r3l.b),@er1+" +gdb_test "x" "xor.b\t@\\(0x1234(:16|),r3l.b\\),@er1-" \ + "xor.b @(0x1234:16,r3l.b),@er1-" +gdb_test "x" "xor.b\t@\\(0x1234(:16|),r3l.b\\),@\\+er1" \ + "xor.b @(0x1234:16,r3l.b),@+er1" +gdb_test "x" "xor.b\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abc(:16|),er1\\)" \ + "xor.b @(0x1234:16,r3l.b),@(0x9abc:16,er1)" +gdb_test "x" "xor.b\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "xor.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1)" +gdb_test "x" "xor.b\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "xor.b @(0x1234:16,r3l.b),@(0x9abc:16,r2l.b)" +gdb_test "x" "xor.b\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abc(:16|),r2.w\\)" \ + "xor.b @(0x1234:16,r3l.b),@(0x9abc:16,r2.w)" +gdb_test "x" "xor.b\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abc(:16|),er2.l\\)" \ + "xor.b @(0x1234:16,r3l.b),@(0x9abc:16,er2.l)" +gdb_test "x" "xor.b\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "xor.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "xor.b\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "xor.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "xor.b\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "xor.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "xor.b\t@\\(0x1234(:16|),r3l.b\\),@0x9abc(:16|)" \ + "xor.b @(0x1234:16,r3l.b),@0x9abc:16" +gdb_test "x" "xor.b\t@\\(0x1234(:16|),r3l.b\\),@0x9abcdef0(:32|)" \ + "xor.b @(0x1234:16,r3l.b),@0x9abcdef0:32" +gdb_test "x" "xor.b\t@\\(0x1234(:16|),r3.w\\),@er1" \ + "xor.b @(0x1234:16,r3.w),@er1" +gdb_test "x" "xor.b\t@\\(0x1234(:16|),r3.w\\),@\\(0x3(:2|),er1\\)" \ + "xor.b @(0x1234:16,r3.w),@(0x3:2,er1)" +gdb_test "x" "xor.b\t@\\(0x1234(:16|),r3.w\\),@-er1" \ + "xor.b @(0x1234:16,r3.w),@-er1" +gdb_test "x" "xor.b\t@\\(0x1234(:16|),r3.w\\),@er1\\+" \ + "xor.b @(0x1234:16,r3.w),@er1+" +gdb_test "x" "xor.b\t@\\(0x1234(:16|),r3.w\\),@er1-" \ + "xor.b @(0x1234:16,r3.w),@er1-" +gdb_test "x" "xor.b\t@\\(0x1234(:16|),r3.w\\),@\\+er1" \ + "xor.b @(0x1234:16,r3.w),@+er1" +gdb_test "x" "xor.b\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abc(:16|),er1\\)" \ + "xor.b @(0x1234:16,r3.w),@(0x9abc:16,er1)" +gdb_test "x" "xor.b\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "xor.b @(0x1234:16,r3.w),@(0x9abcdef0:32,er1)" +gdb_test "x" "xor.b\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "xor.b @(0x1234:16,r3.w),@(0x9abc:16,r2l.b)" +gdb_test "x" "xor.b\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abc(:16|),r2.w\\)" \ + "xor.b @(0x1234:16,r3.w),@(0x9abc:16,r2.w)" +gdb_test "x" "xor.b\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abc(:16|),er2.l\\)" \ + "xor.b @(0x1234:16,r3.w),@(0x9abc:16,er2.l)" +gdb_test "x" "xor.b\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "xor.b @(0x1234:16,r3.w),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "xor.b\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "xor.b @(0x1234:16,r3.w),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "xor.b\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "xor.b @(0x1234:16,r3.w),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "xor.b\t@\\(0x1234(:16|),r3.w\\),@0x9abc(:16|)" \ + "xor.b @(0x1234:16,r3.w),@0x9abc:16" +gdb_test "x" "xor.b\t@\\(0x1234(:16|),r3.w\\),@0x9abcdef0(:32|)" \ + "xor.b @(0x1234:16,r3.w),@0x9abcdef0:32" +gdb_test "x" "xor.b\t@\\(0x1234(:16|),er3.l\\),@er1" \ + "xor.b @(0x1234:16,er3.l),@er1" +gdb_test "x" "xor.b\t@\\(0x1234(:16|),er3.l\\),@\\(0x3(:2|),er1\\)" \ + "xor.b @(0x1234:16,er3.l),@(0x3:2,er1)" +gdb_test "x" "xor.b\t@\\(0x1234(:16|),er3.l\\),@-er1" \ + "xor.b @(0x1234:16,er3.l),@-er1" +gdb_test "x" "xor.b\t@\\(0x1234(:16|),er3.l\\),@er1\\+" \ + "xor.b @(0x1234:16,er3.l),@er1+" +gdb_test "x" "xor.b\t@\\(0x1234(:16|),er3.l\\),@er1-" \ + "xor.b @(0x1234:16,er3.l),@er1-" +gdb_test "x" "xor.b\t@\\(0x1234(:16|),er3.l\\),@\\+er1" \ + "xor.b @(0x1234:16,er3.l),@+er1" +gdb_test "x" "xor.b\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abc(:16|),er1\\)" \ + "xor.b @(0x1234:16,er3.l),@(0x9abc:16,er1)" +gdb_test "x" "xor.b\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "xor.b @(0x1234:16,er3.l),@(0x9abcdef0:32,er1)" +gdb_test "x" "xor.b\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "xor.b @(0x1234:16,er3.l),@(0x9abc:16,r2l.b)" +gdb_test "x" "xor.b\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abc(:16|),r2.w\\)" \ + "xor.b @(0x1234:16,er3.l),@(0x9abc:16,r2.w)" +gdb_test "x" "xor.b\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abc(:16|),er2.l\\)" \ + "xor.b @(0x1234:16,er3.l),@(0x9abc:16,er2.l)" +gdb_test "x" "xor.b\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "xor.b @(0x1234:16,er3.l),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "xor.b\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "xor.b @(0x1234:16,er3.l),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "xor.b\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "xor.b @(0x1234:16,er3.l),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "xor.b\t@\\(0x1234(:16|),er3.l\\),@0x9abc(:16|)" \ + "xor.b @(0x1234:16,er3.l),@0x9abc:16" +gdb_test "x" "xor.b\t@\\(0x1234(:16|),er3.l\\),@0x9abcdef0(:32|)" \ + "xor.b @(0x1234:16,er3.l),@0x9abcdef0:32" +gdb_test "x" "xor.b\t@\\(0x12345678(:32|),r3l.b\\),@er1" \ + "xor.b @(0x12345678:32,r3l.b),@er1" +gdb_test "x" "xor.b\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x3(:2|),er1\\)" \ + "xor.b @(0x12345678:32,r3l.b),@(0x3:2,er1)" +gdb_test "x" "xor.b\t@\\(0x12345678(:32|),r3l.b\\),@-er1" \ + "xor.b @(0x12345678:32,r3l.b),@-er1" +gdb_test "x" "xor.b\t@\\(0x12345678(:32|),r3l.b\\),@er1\\+" \ + "xor.b @(0x12345678:32,r3l.b),@er1+" +gdb_test "x" "xor.b\t@\\(0x12345678(:32|),r3l.b\\),@er1-" \ + "xor.b @(0x12345678:32,r3l.b),@er1-" +gdb_test "x" "xor.b\t@\\(0x12345678(:32|),r3l.b\\),@\\+er1" \ + "xor.b @(0x12345678:32,r3l.b),@+er1" +gdb_test "x" "xor.b\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abc(:16|),er1\\)" \ + "xor.b @(0x12345678:32,r3l.b),@(0x9abc:16,er1)" +gdb_test "x" "xor.b\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "xor.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1)" +gdb_test "x" "xor.b\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "xor.b @(0x12345678:32,r3l.b),@(0x9abc:16,r2l.b)" +gdb_test "x" "xor.b\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abc(:16|),r2.w\\)" \ + "xor.b @(0x12345678:32,r3l.b),@(0x9abc:16,r2.w)" +gdb_test "x" "xor.b\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abc(:16|),er2.l\\)" \ + "xor.b @(0x12345678:32,r3l.b),@(0x9abc:16,er2.l)" +gdb_test "x" "xor.b\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "xor.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "xor.b\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "xor.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "xor.b\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "xor.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "xor.b\t@\\(0x12345678(:32|),r3l.b\\),@0x9abc(:16|)" \ + "xor.b @(0x12345678:32,r3l.b),@0x9abc:16" +gdb_test "x" "xor.b\t@\\(0x12345678(:32|),r3l.b\\),@0x9abcdef0(:32|)" \ + "xor.b @(0x12345678:32,r3l.b),@0x9abcdef0:32" +gdb_test "x" "xor.b\t@\\(0x12345678(:32|),r3.w\\),@er1" \ + "xor.b @(0x12345678:32,r3.w),@er1" +gdb_test "x" "xor.b\t@\\(0x12345678(:32|),r3.w\\),@\\(0x3(:2|),er1\\)" \ + "xor.b @(0x12345678:32,r3.w),@(0x3:2,er1)" +gdb_test "x" "xor.b\t@\\(0x12345678(:32|),r3.w\\),@-er1" \ + "xor.b @(0x12345678:32,r3.w),@-er1" +gdb_test "x" "xor.b\t@\\(0x12345678(:32|),r3.w\\),@er1\\+" \ + "xor.b @(0x12345678:32,r3.w),@er1+" +gdb_test "x" "xor.b\t@\\(0x12345678(:32|),r3.w\\),@er1-" \ + "xor.b @(0x12345678:32,r3.w),@er1-" +gdb_test "x" "xor.b\t@\\(0x12345678(:32|),r3.w\\),@\\+er1" \ + "xor.b @(0x12345678:32,r3.w),@+er1" +gdb_test "x" "xor.b\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abc(:16|),er1\\)" \ + "xor.b @(0x12345678:32,r3.w),@(0x9abc:16,er1)" +gdb_test "x" "xor.b\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "xor.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1)" +gdb_test "x" "xor.b\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "xor.b @(0x12345678:32,r3.w),@(0x9abc:16,r2l.b)" +gdb_test "x" "xor.b\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abc(:16|),r2.w\\)" \ + "xor.b @(0x12345678:32,r3.w),@(0x9abc:16,r2.w)" +gdb_test "x" "xor.b\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abc(:16|),er2.l\\)" \ + "xor.b @(0x12345678:32,r3.w),@(0x9abc:16,er2.l)" +gdb_test "x" "xor.b\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "xor.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "xor.b\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "xor.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "xor.b\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "xor.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "xor.b\t@\\(0x12345678(:32|),r3.w\\),@0x9abc(:16|)" \ + "xor.b @(0x12345678:32,r3.w),@0x9abc:16" +gdb_test "x" "xor.b\t@\\(0x12345678(:32|),r3.w\\),@0x9abcdef0(:32|)" \ + "xor.b @(0x12345678:32,r3.w),@0x9abcdef0:32" +gdb_test "x" "xor.b\t@\\(0x12345678(:32|),er3.l\\),@er1" \ + "xor.b @(0x12345678:32,er3.l),@er1" +gdb_test "x" "xor.b\t@\\(0x12345678(:32|),er3.l\\),@\\(0x3(:2|),er1\\)" \ + "xor.b @(0x12345678:32,er3.l),@(0x3:2,er1)" +gdb_test "x" "xor.b\t@\\(0x12345678(:32|),er3.l\\),@-er1" \ + "xor.b @(0x12345678:32,er3.l),@-er1" +gdb_test "x" "xor.b\t@\\(0x12345678(:32|),er3.l\\),@er1\\+" \ + "xor.b @(0x12345678:32,er3.l),@er1+" +gdb_test "x" "xor.b\t@\\(0x12345678(:32|),er3.l\\),@er1-" \ + "xor.b @(0x12345678:32,er3.l),@er1-" +gdb_test "x" "xor.b\t@\\(0x12345678(:32|),er3.l\\),@\\+er1" \ + "xor.b @(0x12345678:32,er3.l),@+er1" +gdb_test "x" "xor.b\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abc(:16|),er1\\)" \ + "xor.b @(0x12345678:32,er3.l),@(0x9abc:16,er1)" +gdb_test "x" "xor.b\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "xor.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1)" +gdb_test "x" "xor.b\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "xor.b @(0x12345678:32,er3.l),@(0x9abc:16,r2l.b)" +gdb_test "x" "xor.b\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abc(:16|),r2.w\\)" \ + "xor.b @(0x12345678:32,er3.l),@(0x9abc:16,r2.w)" +gdb_test "x" "xor.b\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abc(:16|),er2.l\\)" \ + "xor.b @(0x12345678:32,er3.l),@(0x9abc:16,er2.l)" +gdb_test "x" "xor.b\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "xor.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "xor.b\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "xor.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "xor.b\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "xor.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "xor.b\t@\\(0x12345678(:32|),er3.l\\),@0x9abc(:16|)" \ + "xor.b @(0x12345678:32,er3.l),@0x9abc:16" +gdb_test "x" "xor.b\t@\\(0x12345678(:32|),er3.l\\),@0x9abcdef0(:32|)" \ + "xor.b @(0x12345678:32,er3.l),@0x9abcdef0:32" +gdb_test "x" "xor.b\t@0x1234(:16|),@er1" \ + "xor.b @0x1234:16,@er1" +gdb_test "x" "xor.b\t@0x1234(:16|),@\\(0x3(:2|),er1\\)" \ + "xor.b @0x1234:16,@(0x3:2,er1)" +gdb_test "x" "xor.b\t@0x1234(:16|),@-er1" \ + "xor.b @0x1234:16,@-er1" +gdb_test "x" "xor.b\t@0x1234(:16|),@er1\\+" \ + "xor.b @0x1234:16,@er1+" +gdb_test "x" "xor.b\t@0x1234(:16|),@er1-" \ + "xor.b @0x1234:16,@er1-" +gdb_test "x" "xor.b\t@0x1234(:16|),@\\+er1" \ + "xor.b @0x1234:16,@+er1" +gdb_test "x" "xor.b\t@0x1234(:16|),@\\(0x9abc(:16|),er1\\)" \ + "xor.b @0x1234:16,@(0x9abc:16,er1)" +gdb_test "x" "xor.b\t@0x1234(:16|),@\\(0x9abcdef0(:32|),er1\\)" \ + "xor.b @0x1234:16,@(0x9abcdef0:32,er1)" +gdb_test "x" "xor.b\t@0x1234(:16|),@\\(0x9abc(:16|),r2l.b\\)" \ + "xor.b @0x1234:16,@(0x9abc:16,r2l.b)" +gdb_test "x" "xor.b\t@0x1234(:16|),@\\(0x9abc(:16|),r2.w\\)" \ + "xor.b @0x1234:16,@(0x9abc:16,r2.w)" +gdb_test "x" "xor.b\t@0x1234(:16|),@\\(0x9abc(:16|),er2.l\\)" \ + "xor.b @0x1234:16,@(0x9abc:16,er2.l)" +gdb_test "x" "xor.b\t@0x1234(:16|),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "xor.b @0x1234:16,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "xor.b\t@0x1234(:16|),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "xor.b @0x1234:16,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "xor.b\t@0x1234(:16|),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "xor.b @0x1234:16,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "xor.b\t@0x1234(:16|),@0x9abc(:16|)" \ + "xor.b @0x1234:16,@0x9abc:16" +gdb_test "x" "xor.b\t@0x1234(:16|),@0x9abcdef0(:32|)" \ + "xor.b @0x1234:16,@0x9abcdef0:32" +gdb_test "x" "xor.b\t@0x12345678(:32|),@er1" \ + "xor.b @0x12345678:32,@er1" +gdb_test "x" "xor.b\t@0x12345678(:32|),@\\(0x3(:2|),er1\\)" \ + "xor.b @0x12345678:32,@(0x3:2,er1)" +gdb_test "x" "xor.b\t@0x12345678(:32|),@-er1" \ + "xor.b @0x12345678:32,@-er1" +gdb_test "x" "xor.b\t@0x12345678(:32|),@er1\\+" \ + "xor.b @0x12345678:32,@er1+" +gdb_test "x" "xor.b\t@0x12345678(:32|),@er1-" \ + "xor.b @0x12345678:32,@er1-" +gdb_test "x" "xor.b\t@0x12345678(:32|),@\\+er1" \ + "xor.b @0x12345678:32,@+er1" +gdb_test "x" "xor.b\t@0x12345678(:32|),@\\(0x9abc(:16|),er1\\)" \ + "xor.b @0x12345678:32,@(0x9abc:16,er1)" +gdb_test "x" "xor.b\t@0x12345678(:32|),@\\(0x9abcdef0(:32|),er1\\)" \ + "xor.b @0x12345678:32,@(0x9abcdef0:32,er1)" +gdb_test "x" "xor.b\t@0x12345678(:32|),@\\(0x9abc(:16|),r2l.b\\)" \ + "xor.b @0x12345678:32,@(0x9abc:16,r2l.b)" +gdb_test "x" "xor.b\t@0x12345678(:32|),@\\(0x9abc(:16|),r2.w\\)" \ + "xor.b @0x12345678:32,@(0x9abc:16,r2.w)" +gdb_test "x" "xor.b\t@0x12345678(:32|),@\\(0x9abc(:16|),er2.l\\)" \ + "xor.b @0x12345678:32,@(0x9abc:16,er2.l)" +gdb_test "x" "xor.b\t@0x12345678(:32|),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "xor.b @0x12345678:32,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "xor.b\t@0x12345678(:32|),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "xor.b @0x12345678:32,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "xor.b\t@0x12345678(:32|),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "xor.b @0x12345678:32,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "xor.b\t@0x12345678(:32|),@0x9abc(:16|)" \ + "xor.b @0x12345678:32,@0x9abc:16" +gdb_test "x" "xor.b\t@0x12345678(:32|),@0x9abcdef0(:32|)" \ + "xor.b @0x12345678:32,@0x9abcdef0:32" +gdb_test "x" "xor.w\t#0x1234(:16|),r1" \ + "xor.w #0x1234:16,r1" +gdb_test "x" "xor.w\t#0x1234(:16|),@er1" \ + "xor.w #0x1234:16,@er1" +gdb_test "x" "xor.w\t#0x1234(:16|),@\\(0x6(:2|),er1\\)" \ + "xor.w #0x1234:16,@(0x6:2,er1)" +gdb_test "x" "xor.w\t#0x1234(:16|),@er1\\+" \ + "xor.w #0x1234:16,@er1+" +gdb_test "x" "xor.w\t#0x1234(:16|),@-er1" \ + "xor.w #0x1234:16,@-er1" +gdb_test "x" "xor.w\t#0x1234(:16|),@\\+er1" \ + "xor.w #0x1234:16,@+er1" +gdb_test "x" "xor.w\t#0x1234(:16|),@er1-" \ + "xor.w #0x1234:16,@er1-" +gdb_test "x" "xor.w\t#0x1234(:16|),@\\(0x9abc(:16|),er1\\)" \ + "xor.w #0x1234:16,@(0x9abc:16,er1)" +gdb_test "x" "xor.w\t#0x1234(:16|),@\\(0x9abcdef0(:32|),er1\\)" \ + "xor.w #0x1234:16,@(0x9abcdef0:32,er1)" +gdb_test "x" "xor.w\t#0x1234(:16|),@\\(0x9abc(:16|),r2l.b\\)" \ + "xor.w #0x1234:16,@(0x9abc:16,r2l.b)" +gdb_test "x" "xor.w\t#0x1234(:16|),@\\(0x9abc(:16|),r2.w\\)" \ + "xor.w #0x1234:16,@(0x9abc:16,r2.w)" +gdb_test "x" "xor.w\t#0x1234(:16|),@\\(0x9abc(:16|),er2.l\\)" \ + "xor.w #0x1234:16,@(0x9abc:16,er2.l)" +gdb_test "x" "xor.w\t#0x1234(:16|),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "xor.w #0x1234:16,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "xor.w\t#0x1234(:16|),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "xor.w #0x1234:16,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "xor.w\t#0x1234(:16|),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "xor.w #0x1234:16,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "xor.w\t#0x1234(:16|),@0x9abc(:16|)" \ + "xor.w #0x1234:16,@0x9abc:16" +gdb_test "x" "xor.w\t#0x1234(:16|),@0x9abcdef0(:32|)" \ + "xor.w #0x1234:16,@0x9abcdef0:32" +gdb_test "x" "xor.w\tr3,r1" \ + "xor.w r3,r1" +gdb_test "x" "xor.w\tr3,@er1" \ + "xor.w r3,@er1" +gdb_test "x" "xor.w\tr3,@\\(0x6(:2|),er1\\)" \ + "xor.w r3,@(0x6:2,er1)" +gdb_test "x" "xor.w\tr3,@-er1" \ + "xor.w r3,@-er1" +gdb_test "x" "xor.w\tr3,@er1\\+" \ + "xor.w r3,@er1+" +gdb_test "x" "xor.w\tr3,@er1-" \ + "xor.w r3,@er1-" +gdb_test "x" "xor.w\tr3,@\\+er1" \ + "xor.w r3,@+er1" +gdb_test "x" "xor.w\tr3,@\\(0x1234(:16|),er1\\)" \ + "xor.w r3,@(0x1234:16,er1)" +gdb_test "x" "xor.w\tr3,@\\(0x12345678(:32|),er1\\)" \ + "xor.w r3,@(0x12345678:32,er1)" +gdb_test "x" "xor.w\tr3,@\\(0x1234(:16|),r2l.b\\)" \ + "xor.w r3,@(0x1234:16,r2l.b)" +gdb_test "x" "xor.w\tr3,@\\(0x1234(:16|),r2.w\\)" \ + "xor.w r3,@(0x1234:16,r2.w)" +gdb_test "x" "xor.w\tr3,@\\(0x1234(:16|),er2.l\\)" \ + "xor.w r3,@(0x1234:16,er2.l)" +gdb_test "x" "xor.w\tr3,@\\(0x12345678(:32|),r2l.b\\)" \ + "xor.w r3,@(0x12345678:32,r2l.b)" +gdb_test "x" "xor.w\tr3,@\\(0x12345678(:32|),r2.w\\)" \ + "xor.w r3,@(0x12345678:32,r2.w)" +gdb_test "x" "xor.w\tr3,@\\(0x12345678(:32|),er2.l\\)" \ + "xor.w r3,@(0x12345678:32,er2.l)" +gdb_test "x" "xor.w\tr3,@0x1234(:16|)" \ + "xor.w r3,@0x1234:16" +gdb_test "x" "xor.w\tr3,@0x12345678(:32|)" \ + "xor.w r3,@0x12345678:32" +gdb_test "x" "xor.w\t@er3,r1" \ + "xor.w @er3,r1" +gdb_test "x" "xor.w\t@\\(0x6(:2|),er3\\),r1" \ + "xor.w @(0x6:2,er3),r1" +gdb_test "x" "xor.w\t@er3\\+,r1" \ + "xor.w @er3+,r1" +gdb_test "x" "xor.w\t@-er3,r1" \ + "xor.w @-er3,r1" +gdb_test "x" "xor.w\t@\\+er3,r1" \ + "xor.w @+er3,r1" +gdb_test "x" "xor.w\t@er3-,r1" \ + "xor.w @er3-,r1" +gdb_test "x" "xor.w\t@\\(0x1234(:16|),er1\\),r1" \ + "xor.w @(0x1234:16,er1),r1" +gdb_test "x" "xor.w\t@\\(0x12345678(:32|),er1\\),r1" \ + "xor.w @(0x12345678:32,er1),r1" +gdb_test "x" "xor.w\t@\\(0x1234(:16|),r2l.b\\),r1" \ + "xor.w @(0x1234:16,r2l.b),r1" +gdb_test "x" "xor.w\t@\\(0x1234(:16|),r2.w\\),r1" \ + "xor.w @(0x1234:16,r2.w),r1" +gdb_test "x" "xor.w\t@\\(0x1234(:16|),er2.l\\),r1" \ + "xor.w @(0x1234:16,er2.l),r1" +gdb_test "x" "xor.w\t@\\(0x12345678(:32|),r2l.b\\),r1" \ + "xor.w @(0x12345678:32,r2l.b),r1" +gdb_test "x" "xor.w\t@\\(0x12345678(:32|),r2.w\\),r1" \ + "xor.w @(0x12345678:32,r2.w),r1" +gdb_test "x" "xor.w\t@\\(0x12345678(:32|),er2.l\\),r1" \ + "xor.w @(0x12345678:32,er2.l),r1" +gdb_test "x" "xor.w\t@0x1234(:16|),r1" \ + "xor.w @0x1234:16,r1" +gdb_test "x" "xor.w\t@0x12345678(:32|),r1" \ + "xor.w @0x12345678:32,r1" +gdb_test "x" "xor.w\t@er3,@er1" \ + "xor.w @er3,@er1" +gdb_test "x" "xor.w\t@er3,@\\(0x6(:2|),er1\\)" \ + "xor.w @er3,@(0x6:2,er1)" +gdb_test "x" "xor.w\t@er3,@-er1" \ + "xor.w @er3,@-er1" +gdb_test "x" "xor.w\t@er3,@er1\\+" \ + "xor.w @er3,@er1+" +gdb_test "x" "xor.w\t@er3,@er1-" \ + "xor.w @er3,@er1-" +gdb_test "x" "xor.w\t@er3,@\\+er1" \ + "xor.w @er3,@+er1" +gdb_test "x" "xor.w\t@er3,@\\(0x9abc(:16|),er1\\)" \ + "xor.w @er3,@(0x9abc:16,er1)" +gdb_test "x" "xor.w\t@er3,@\\(0x9abcdef0(:32|),er1\\)" \ + "xor.w @er3,@(0x9abcdef0:32,er1)" +gdb_test "x" "xor.w\t@er3,@\\(0x9abc(:16|),r2l.b\\)" \ + "xor.w @er3,@(0x9abc:16,r2l.b)" +gdb_test "x" "xor.w\t@er3,@\\(0x9abc(:16|),r2.w\\)" \ + "xor.w @er3,@(0x9abc:16,r2.w)" +gdb_test "x" "xor.w\t@er3,@\\(0x9abc(:16|),er2.l\\)" \ + "xor.w @er3,@(0x9abc:16,er2.l)" +gdb_test "x" "xor.w\t@er3,@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "xor.w @er3,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "xor.w\t@er3,@\\(0x9abcdef0(:32|),r2.w\\)" \ + "xor.w @er3,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "xor.w\t@er3,@\\(0x9abcdef0(:32|),er2.l\\)" \ + "xor.w @er3,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "xor.w\t@er3,@0x9abc(:16|)" \ + "xor.w @er3,@0x9abc:16" +gdb_test "x" "xor.w\t@er3,@0x9abcdef0(:32|)" \ + "xor.w @er3,@0x9abcdef0:32" +gdb_test "x" "xor.w\t@-er3,@er1" \ + "xor.w @-er3,@er1" +gdb_test "x" "xor.w\t@-er3,@\\(0x6(:2|),er1\\)" \ + "xor.w @-er3,@(0x6:2,er1)" +gdb_test "x" "xor.w\t@-er3,@-er1" \ + "xor.w @-er3,@-er1" +gdb_test "x" "xor.w\t@-er3,@er1\\+" \ + "xor.w @-er3,@er1+" +gdb_test "x" "xor.w\t@-er3,@er1-" \ + "xor.w @-er3,@er1-" +gdb_test "x" "xor.w\t@-er3,@\\+er1" \ + "xor.w @-er3,@+er1" +gdb_test "x" "xor.w\t@-er3,@\\(0x9abc(:16|),er1\\)" \ + "xor.w @-er3,@(0x9abc:16,er1)" +gdb_test "x" "xor.w\t@-er3,@\\(0x9abcdef0(:32|),er1\\)" \ + "xor.w @-er3,@(0x9abcdef0:32,er1)" +gdb_test "x" "xor.w\t@-er3,@\\(0x9abc(:16|),r2l.b\\)" \ + "xor.w @-er3,@(0x9abc:16,r2l.b)" +gdb_test "x" "xor.w\t@-er3,@\\(0x9abc(:16|),r2.w\\)" \ + "xor.w @-er3,@(0x9abc:16,r2.w)" +gdb_test "x" "xor.w\t@-er3,@\\(0x9abc(:16|),er2.l\\)" \ + "xor.w @-er3,@(0x9abc:16,er2.l)" +gdb_test "x" "xor.w\t@-er3,@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "xor.w @-er3,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "xor.w\t@-er3,@\\(0x9abcdef0(:32|),r2.w\\)" \ + "xor.w @-er3,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "xor.w\t@-er3,@\\(0x9abcdef0(:32|),er2.l\\)" \ + "xor.w @-er3,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "xor.w\t@-er3,@0x9abc(:16|)" \ + "xor.w @-er3,@0x9abc:16" +gdb_test "x" "xor.w\t@-er3,@0x9abcdef0(:32|)" \ + "xor.w @-er3,@0x9abcdef0:32" +gdb_test "x" "xor.w\t@er3\\+,@er1" \ + "xor.w @er3+,@er1" +gdb_test "x" "xor.w\t@er3\\+,@\\(0x6(:2|),er1\\)" \ + "xor.w @er3+,@(0x6:2,er1)" +gdb_test "x" "xor.w\t@er3\\+,@-er1" \ + "xor.w @er3+,@-er1" +gdb_test "x" "xor.w\t@er3\\+,@er1\\+" \ + "xor.w @er3+,@er1+" +gdb_test "x" "xor.w\t@er3\\+,@er1-" \ + "xor.w @er3+,@er1-" +gdb_test "x" "xor.w\t@er3\\+,@\\+er1" \ + "xor.w @er3+,@+er1" +gdb_test "x" "xor.w\t@er3\\+,@\\(0x9abc(:16|),er1\\)" \ + "xor.w @er3+,@(0x9abc:16,er1)" +gdb_test "x" "xor.w\t@er3\\+,@\\(0x9abcdef0(:32|),er1\\)" \ + "xor.w @er3+,@(0x9abcdef0:32,er1)" +gdb_test "x" "xor.w\t@er3\\+,@\\(0x9abc(:16|),r2l.b\\)" \ + "xor.w @er3+,@(0x9abc:16,r2l.b)" +gdb_test "x" "xor.w\t@er3\\+,@\\(0x9abc(:16|),r2.w\\)" \ + "xor.w @er3+,@(0x9abc:16,r2.w)" +gdb_test "x" "xor.w\t@er3\\+,@\\(0x9abc(:16|),er2.l\\)" \ + "xor.w @er3+,@(0x9abc:16,er2.l)" +gdb_test "x" "xor.w\t@er3\\+,@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "xor.w @er3+,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "xor.w\t@er3\\+,@\\(0x9abcdef0(:32|),r2.w\\)" \ + "xor.w @er3+,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "xor.w\t@er3\\+,@\\(0x9abcdef0(:32|),er2.l\\)" \ + "xor.w @er3+,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "xor.w\t@er3\\+,@0x9abc(:16|)" \ + "xor.w @er3+,@0x9abc:16" +gdb_test "x" "xor.w\t@er3\\+,@0x9abcdef0(:32|)" \ + "xor.w @er3+,@0x9abcdef0:32" +gdb_test "x" "xor.w\t@er3-,@er1" \ + "xor.w @er3-,@er1" +gdb_test "x" "xor.w\t@er3-,@\\(0x6(:2|),er1\\)" \ + "xor.w @er3-,@(0x6:2,er1)" +gdb_test "x" "xor.w\t@er3-,@-er1" \ + "xor.w @er3-,@-er1" +gdb_test "x" "xor.w\t@er3-,@er1\\+" \ + "xor.w @er3-,@er1+" +gdb_test "x" "xor.w\t@er3-,@er1-" \ + "xor.w @er3-,@er1-" +gdb_test "x" "xor.w\t@er3-,@\\+er1" \ + "xor.w @er3-,@+er1" +gdb_test "x" "xor.w\t@er3-,@\\(0x9abc(:16|),er1\\)" \ + "xor.w @er3-,@(0x9abc:16,er1)" +gdb_test "x" "xor.w\t@er3-,@\\(0x9abcdef0(:32|),er1\\)" \ + "xor.w @er3-,@(0x9abcdef0:32,er1)" +gdb_test "x" "xor.w\t@er3-,@\\(0x9abc(:16|),r2l.b\\)" \ + "xor.w @er3-,@(0x9abc:16,r2l.b)" +gdb_test "x" "xor.w\t@er3-,@\\(0x9abc(:16|),r2.w\\)" \ + "xor.w @er3-,@(0x9abc:16,r2.w)" +gdb_test "x" "xor.w\t@er3-,@\\(0x9abc(:16|),er2.l\\)" \ + "xor.w @er3-,@(0x9abc:16,er2.l)" +gdb_test "x" "xor.w\t@er3-,@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "xor.w @er3-,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "xor.w\t@er3-,@\\(0x9abcdef0(:32|),r2.w\\)" \ + "xor.w @er3-,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "xor.w\t@er3-,@\\(0x9abcdef0(:32|),er2.l\\)" \ + "xor.w @er3-,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "xor.w\t@er3-,@0x9abc(:16|)" \ + "xor.w @er3-,@0x9abc:16" +gdb_test "x" "xor.w\t@er3-,@0x9abcdef0(:32|)" \ + "xor.w @er3-,@0x9abcdef0:32" +gdb_test "x" "xor.w\t@\\+er3,@er1" \ + "xor.w @+er3,@er1" +gdb_test "x" "xor.w\t@\\+er3,@\\(0x6(:2|),er1\\)" \ + "xor.w @+er3,@(0x6:2,er1)" +gdb_test "x" "xor.w\t@\\+er3,@-er1" \ + "xor.w @+er3,@-er1" +gdb_test "x" "xor.w\t@\\+er3,@er1\\+" \ + "xor.w @+er3,@er1+" +gdb_test "x" "xor.w\t@\\+er3,@er1-" \ + "xor.w @+er3,@er1-" +gdb_test "x" "xor.w\t@\\+er3,@\\+er1" \ + "xor.w @+er3,@+er1" +gdb_test "x" "xor.w\t@\\+er3,@\\(0x9abc(:16|),er1\\)" \ + "xor.w @+er3,@(0x9abc:16,er1)" +gdb_test "x" "xor.w\t@\\+er3,@\\(0x9abcdef0(:32|),er1\\)" \ + "xor.w @+er3,@(0x9abcdef0:32,er1)" +gdb_test "x" "xor.w\t@\\+er3,@\\(0x9abc(:16|),r2l.b\\)" \ + "xor.w @+er3,@(0x9abc:16,r2l.b)" +gdb_test "x" "xor.w\t@\\+er3,@\\(0x9abc(:16|),r2.w\\)" \ + "xor.w @+er3,@(0x9abc:16,r2.w)" +gdb_test "x" "xor.w\t@\\+er3,@\\(0x9abc(:16|),er2.l\\)" \ + "xor.w @+er3,@(0x9abc:16,er2.l)" +gdb_test "x" "xor.w\t@\\+er3,@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "xor.w @+er3,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "xor.w\t@\\+er3,@\\(0x9abcdef0(:32|),r2.w\\)" \ + "xor.w @+er3,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "xor.w\t@\\+er3,@\\(0x9abcdef0(:32|),er2.l\\)" \ + "xor.w @+er3,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "xor.w\t@\\+er3,@0x9abc(:16|)" \ + "xor.w @+er3,@0x9abc:16" +gdb_test "x" "xor.w\t@\\+er3,@0x9abcdef0(:32|)" \ + "xor.w @+er3,@0x9abcdef0:32" +gdb_test "x" "xor.w\t@\\(0x1234(:16|),er3\\),@er1" \ + "xor.w @(0x1234:16,er3),@er1" +gdb_test "x" "xor.w\t@\\(0x1234(:16|),er3\\),@\\(0x6(:2|),er1\\)" \ + "xor.w @(0x1234:16,er3),@(0x6:2,er1)" +gdb_test "x" "xor.w\t@\\(0x1234(:16|),er3\\),@-er1" \ + "xor.w @(0x1234:16,er3),@-er1" +gdb_test "x" "xor.w\t@\\(0x1234(:16|),er3\\),@er1\\+" \ + "xor.w @(0x1234:16,er3),@er1+" +gdb_test "x" "xor.w\t@\\(0x1234(:16|),er3\\),@er1-" \ + "xor.w @(0x1234:16,er3),@er1-" +gdb_test "x" "xor.w\t@\\(0x1234(:16|),er3\\),@\\+er1" \ + "xor.w @(0x1234:16,er3),@+er1" +gdb_test "x" "xor.w\t@\\(0x1234(:16|),er3\\),@\\(0x9abc(:16|),er1\\)" \ + "xor.w @(0x1234:16,er3),@(0x9abc:16,er1)" +gdb_test "x" "xor.w\t@\\(0x1234(:16|),er3\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "xor.w @(0x1234:16,er3),@(0x9abcdef0:32,er1)" +gdb_test "x" "xor.w\t@\\(0x1234(:16|),er3\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "xor.w @(0x1234:16,er3),@(0x9abc:16,r2l.b)" +gdb_test "x" "xor.w\t@\\(0x1234(:16|),er3\\),@\\(0x9abc(:16|),r2.w\\)" \ + "xor.w @(0x1234:16,er3),@(0x9abc:16,r2.w)" +gdb_test "x" "xor.w\t@\\(0x1234(:16|),er3\\),@\\(0x9abc(:16|),er2.l\\)" \ + "xor.w @(0x1234:16,er3),@(0x9abc:16,er2.l)" +gdb_test "x" "xor.w\t@\\(0x1234(:16|),er3\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "xor.w @(0x1234:16,er3),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "xor.w\t@\\(0x1234(:16|),er3\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "xor.w @(0x1234:16,er3),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "xor.w\t@\\(0x1234(:16|),er3\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "xor.w @(0x1234:16,er3),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "xor.w\t@\\(0x1234(:16|),er3\\),@0x9abc(:16|)" \ + "xor.w @(0x1234:16,er3),@0x9abc:16" +gdb_test "x" "xor.w\t@\\(0x1234(:16|),er3\\),@0x9abcdef0(:32|)" \ + "xor.w @(0x1234:16,er3),@0x9abcdef0:32" +gdb_test "x" "xor.w\t@\\(0x12345678(:32|),er3\\),@er1" \ + "xor.w @(0x12345678:32,er3),@er1" +gdb_test "x" "xor.w\t@\\(0x12345678(:32|),er3\\),@\\(0x6(:2|),er1\\)" \ + "xor.w @(0x12345678:32,er3),@(0x6:2,er1)" +gdb_test "x" "xor.w\t@\\(0x12345678(:32|),er3\\),@-er1" \ + "xor.w @(0x12345678:32,er3),@-er1" +gdb_test "x" "xor.w\t@\\(0x12345678(:32|),er3\\),@er1\\+" \ + "xor.w @(0x12345678:32,er3),@er1+" +gdb_test "x" "xor.w\t@\\(0x12345678(:32|),er3\\),@er1-" \ + "xor.w @(0x12345678:32,er3),@er1-" +gdb_test "x" "xor.w\t@\\(0x12345678(:32|),er3\\),@\\+er1" \ + "xor.w @(0x12345678:32,er3),@+er1" +gdb_test "x" "xor.w\t@\\(0x12345678(:32|),er3\\),@\\(0x9abc(:16|),er1\\)" \ + "xor.w @(0x12345678:32,er3),@(0x9abc:16,er1)" +gdb_test "x" "xor.w\t@\\(0x12345678(:32|),er3\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "xor.w @(0x12345678:32,er3),@(0x9abcdef0:32,er1)" +gdb_test "x" "xor.w\t@\\(0x12345678(:32|),er3\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "xor.w @(0x12345678:32,er3),@(0x9abc:16,r2l.b)" +gdb_test "x" "xor.w\t@\\(0x12345678(:32|),er3\\),@\\(0x9abc(:16|),r2.w\\)" \ + "xor.w @(0x12345678:32,er3),@(0x9abc:16,r2.w)" +gdb_test "x" "xor.w\t@\\(0x12345678(:32|),er3\\),@\\(0x9abc(:16|),er2.l\\)" \ + "xor.w @(0x12345678:32,er3),@(0x9abc:16,er2.l)" +gdb_test "x" "xor.w\t@\\(0x12345678(:32|),er3\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "xor.w @(0x12345678:32,er3),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "xor.w\t@\\(0x12345678(:32|),er3\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "xor.w @(0x12345678:32,er3),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "xor.w\t@\\(0x12345678(:32|),er3\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "xor.w @(0x12345678:32,er3),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "xor.w\t@\\(0x12345678(:32|),er3\\),@0x9abc(:16|)" \ + "xor.w @(0x12345678:32,er3),@0x9abc:16" +gdb_test "x" "xor.w\t@\\(0x12345678(:32|),er3\\),@0x9abcdef0(:32|)" \ + "xor.w @(0x12345678:32,er3),@0x9abcdef0:32" +gdb_test "x" "xor.w\t@\\(0x1234(:16|),r3l.b\\),@er1" \ + "xor.w @(0x1234:16,r3l.b),@er1" +gdb_test "x" "xor.w\t@\\(0x1234(:16|),r3l.b\\),@\\(0x6(:2|),er1\\)" \ + "xor.w @(0x1234:16,r3l.b),@(0x6:2,er1)" +gdb_test "x" "xor.w\t@\\(0x1234(:16|),r3l.b\\),@-er1" \ + "xor.w @(0x1234:16,r3l.b),@-er1" +gdb_test "x" "xor.w\t@\\(0x1234(:16|),r3l.b\\),@er1\\+" \ + "xor.w @(0x1234:16,r3l.b),@er1+" +gdb_test "x" "xor.w\t@\\(0x1234(:16|),r3l.b\\),@er1-" \ + "xor.w @(0x1234:16,r3l.b),@er1-" +gdb_test "x" "xor.w\t@\\(0x1234(:16|),r3l.b\\),@\\+er1" \ + "xor.w @(0x1234:16,r3l.b),@+er1" +gdb_test "x" "xor.w\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abc(:16|),er1\\)" \ + "xor.w @(0x1234:16,r3l.b),@(0x9abc:16,er1)" +gdb_test "x" "xor.w\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "xor.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1)" +gdb_test "x" "xor.w\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "xor.w @(0x1234:16,r3l.b),@(0x9abc:16,r2l.b)" +gdb_test "x" "xor.w\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abc(:16|),r2.w\\)" \ + "xor.w @(0x1234:16,r3l.b),@(0x9abc:16,r2.w)" +gdb_test "x" "xor.w\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abc(:16|),er2.l\\)" \ + "xor.w @(0x1234:16,r3l.b),@(0x9abc:16,er2.l)" +gdb_test "x" "xor.w\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "xor.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "xor.w\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "xor.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "xor.w\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "xor.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "xor.w\t@\\(0x1234(:16|),r3l.b\\),@0x9abc(:16|)" \ + "xor.w @(0x1234:16,r3l.b),@0x9abc:16" +gdb_test "x" "xor.w\t@\\(0x1234(:16|),r3l.b\\),@0x9abcdef0(:32|)" \ + "xor.w @(0x1234:16,r3l.b),@0x9abcdef0:32" +gdb_test "x" "xor.w\t@\\(0x1234(:16|),r3.w\\),@er1" \ + "xor.w @(0x1234:16,r3.w),@er1" +gdb_test "x" "xor.w\t@\\(0x1234(:16|),r3.w\\),@\\(0x6(:2|),er1\\)" \ + "xor.w @(0x1234:16,r3.w),@(0x6:2,er1)" +gdb_test "x" "xor.w\t@\\(0x1234(:16|),r3.w\\),@-er1" \ + "xor.w @(0x1234:16,r3.w),@-er1" +gdb_test "x" "xor.w\t@\\(0x1234(:16|),r3.w\\),@er1\\+" \ + "xor.w @(0x1234:16,r3.w),@er1+" +gdb_test "x" "xor.w\t@\\(0x1234(:16|),r3.w\\),@er1-" \ + "xor.w @(0x1234:16,r3.w),@er1-" +gdb_test "x" "xor.w\t@\\(0x1234(:16|),r3.w\\),@\\+er1" \ + "xor.w @(0x1234:16,r3.w),@+er1" +gdb_test "x" "xor.w\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abc(:16|),er1\\)" \ + "xor.w @(0x1234:16,r3.w),@(0x9abc:16,er1)" +gdb_test "x" "xor.w\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "xor.w @(0x1234:16,r3.w),@(0x9abcdef0:32,er1)" +gdb_test "x" "xor.w\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "xor.w @(0x1234:16,r3.w),@(0x9abc:16,r2l.b)" +gdb_test "x" "xor.w\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abc(:16|),r2.w\\)" \ + "xor.w @(0x1234:16,r3.w),@(0x9abc:16,r2.w)" +gdb_test "x" "xor.w\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abc(:16|),er2.l\\)" \ + "xor.w @(0x1234:16,r3.w),@(0x9abc:16,er2.l)" +gdb_test "x" "xor.w\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "xor.w @(0x1234:16,r3.w),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "xor.w\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "xor.w @(0x1234:16,r3.w),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "xor.w\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "xor.w @(0x1234:16,r3.w),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "xor.w\t@\\(0x1234(:16|),r3.w\\),@0x9abc(:16|)" \ + "xor.w @(0x1234:16,r3.w),@0x9abc:16" +gdb_test "x" "xor.w\t@\\(0x1234(:16|),r3.w\\),@0x9abcdef0(:32|)" \ + "xor.w @(0x1234:16,r3.w),@0x9abcdef0:32" +gdb_test "x" "xor.w\t@\\(0x1234(:16|),er3.l\\),@er1" \ + "xor.w @(0x1234:16,er3.l),@er1" +gdb_test "x" "xor.w\t@\\(0x1234(:16|),er3.l\\),@\\(0x6(:2|),er1\\)" \ + "xor.w @(0x1234:16,er3.l),@(0x6:2,er1)" +gdb_test "x" "xor.w\t@\\(0x1234(:16|),er3.l\\),@-er1" \ + "xor.w @(0x1234:16,er3.l),@-er1" +gdb_test "x" "xor.w\t@\\(0x1234(:16|),er3.l\\),@er1\\+" \ + "xor.w @(0x1234:16,er3.l),@er1+" +gdb_test "x" "xor.w\t@\\(0x1234(:16|),er3.l\\),@er1-" \ + "xor.w @(0x1234:16,er3.l),@er1-" +gdb_test "x" "xor.w\t@\\(0x1234(:16|),er3.l\\),@\\+er1" \ + "xor.w @(0x1234:16,er3.l),@+er1" +gdb_test "x" "xor.w\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abc(:16|),er1\\)" \ + "xor.w @(0x1234:16,er3.l),@(0x9abc:16,er1)" +gdb_test "x" "xor.w\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "xor.w @(0x1234:16,er3.l),@(0x9abcdef0:32,er1)" +gdb_test "x" "xor.w\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "xor.w @(0x1234:16,er3.l),@(0x9abc:16,r2l.b)" +gdb_test "x" "xor.w\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abc(:16|),r2.w\\)" \ + "xor.w @(0x1234:16,er3.l),@(0x9abc:16,r2.w)" +gdb_test "x" "xor.w\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abc(:16|),er2.l\\)" \ + "xor.w @(0x1234:16,er3.l),@(0x9abc:16,er2.l)" +gdb_test "x" "xor.w\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "xor.w @(0x1234:16,er3.l),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "xor.w\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "xor.w @(0x1234:16,er3.l),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "xor.w\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "xor.w @(0x1234:16,er3.l),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "xor.w\t@\\(0x1234(:16|),er3.l\\),@0x9abc(:16|)" \ + "xor.w @(0x1234:16,er3.l),@0x9abc:16" +gdb_test "x" "xor.w\t@\\(0x1234(:16|),er3.l\\),@0x9abcdef0(:32|)" \ + "xor.w @(0x1234:16,er3.l),@0x9abcdef0:32" +gdb_test "x" "xor.w\t@\\(0x12345678(:32|),r3l.b\\),@er1" \ + "xor.w @(0x12345678:32,r3l.b),@er1" +gdb_test "x" "xor.w\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x6(:2|),er1\\)" \ + "xor.w @(0x12345678:32,r3l.b),@(0x6:2,er1)" +gdb_test "x" "xor.w\t@\\(0x12345678(:32|),r3l.b\\),@-er1" \ + "xor.w @(0x12345678:32,r3l.b),@-er1" +gdb_test "x" "xor.w\t@\\(0x12345678(:32|),r3l.b\\),@er1\\+" \ + "xor.w @(0x12345678:32,r3l.b),@er1+" +gdb_test "x" "xor.w\t@\\(0x12345678(:32|),r3l.b\\),@er1-" \ + "xor.w @(0x12345678:32,r3l.b),@er1-" +gdb_test "x" "xor.w\t@\\(0x12345678(:32|),r3l.b\\),@\\+er1" \ + "xor.w @(0x12345678:32,r3l.b),@+er1" +gdb_test "x" "xor.w\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abc(:16|),er1\\)" \ + "xor.w @(0x12345678:32,r3l.b),@(0x9abc:16,er1)" +gdb_test "x" "xor.w\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "xor.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1)" +gdb_test "x" "xor.w\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "xor.w @(0x12345678:32,r3l.b),@(0x9abc:16,r2l.b)" +gdb_test "x" "xor.w\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abc(:16|),r2.w\\)" \ + "xor.w @(0x12345678:32,r3l.b),@(0x9abc:16,r2.w)" +gdb_test "x" "xor.w\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abc(:16|),er2.l\\)" \ + "xor.w @(0x12345678:32,r3l.b),@(0x9abc:16,er2.l)" +gdb_test "x" "xor.w\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "xor.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "xor.w\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "xor.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "xor.w\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "xor.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "xor.w\t@\\(0x12345678(:32|),r3l.b\\),@0x9abc(:16|)" \ + "xor.w @(0x12345678:32,r3l.b),@0x9abc:16" +gdb_test "x" "xor.w\t@\\(0x12345678(:32|),r3l.b\\),@0x9abcdef0(:32|)" \ + "xor.w @(0x12345678:32,r3l.b),@0x9abcdef0:32" +gdb_test "x" "xor.w\t@\\(0x12345678(:32|),r3.w\\),@er1" \ + "xor.w @(0x12345678:32,r3.w),@er1" +gdb_test "x" "xor.w\t@\\(0x12345678(:32|),r3.w\\),@\\(0x6(:2|),er1\\)" \ + "xor.w @(0x12345678:32,r3.w),@(0x6:2,er1)" +gdb_test "x" "xor.w\t@\\(0x12345678(:32|),r3.w\\),@-er1" \ + "xor.w @(0x12345678:32,r3.w),@-er1" +gdb_test "x" "xor.w\t@\\(0x12345678(:32|),r3.w\\),@er1\\+" \ + "xor.w @(0x12345678:32,r3.w),@er1+" +gdb_test "x" "xor.w\t@\\(0x12345678(:32|),r3.w\\),@er1-" \ + "xor.w @(0x12345678:32,r3.w),@er1-" +gdb_test "x" "xor.w\t@\\(0x12345678(:32|),r3.w\\),@\\+er1" \ + "xor.w @(0x12345678:32,r3.w),@+er1" +gdb_test "x" "xor.w\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abc(:16|),er1\\)" \ + "xor.w @(0x12345678:32,r3.w),@(0x9abc:16,er1)" +gdb_test "x" "xor.w\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "xor.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1)" +gdb_test "x" "xor.w\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "xor.w @(0x12345678:32,r3.w),@(0x9abc:16,r2l.b)" +gdb_test "x" "xor.w\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abc(:16|),r2.w\\)" \ + "xor.w @(0x12345678:32,r3.w),@(0x9abc:16,r2.w)" +gdb_test "x" "xor.w\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abc(:16|),er2.l\\)" \ + "xor.w @(0x12345678:32,r3.w),@(0x9abc:16,er2.l)" +gdb_test "x" "xor.w\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "xor.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "xor.w\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "xor.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "xor.w\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "xor.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "xor.w\t@\\(0x12345678(:32|),r3.w\\),@0x9abc(:16|)" \ + "xor.w @(0x12345678:32,r3.w),@0x9abc:16" +gdb_test "x" "xor.w\t@\\(0x12345678(:32|),r3.w\\),@0x9abcdef0(:32|)" \ + "xor.w @(0x12345678:32,r3.w),@0x9abcdef0:32" +gdb_test "x" "xor.w\t@\\(0x12345678(:32|),er3.l\\),@er1" \ + "xor.w @(0x12345678:32,er3.l),@er1" +gdb_test "x" "xor.w\t@\\(0x12345678(:32|),er3.l\\),@\\(0x6(:2|),er1\\)" \ + "xor.w @(0x12345678:32,er3.l),@(0x6:2,er1)" +gdb_test "x" "xor.w\t@\\(0x12345678(:32|),er3.l\\),@-er1" \ + "xor.w @(0x12345678:32,er3.l),@-er1" +gdb_test "x" "xor.w\t@\\(0x12345678(:32|),er3.l\\),@er1\\+" \ + "xor.w @(0x12345678:32,er3.l),@er1+" +gdb_test "x" "xor.w\t@\\(0x12345678(:32|),er3.l\\),@er1-" \ + "xor.w @(0x12345678:32,er3.l),@er1-" +gdb_test "x" "xor.w\t@\\(0x12345678(:32|),er3.l\\),@\\+er1" \ + "xor.w @(0x12345678:32,er3.l),@+er1" +gdb_test "x" "xor.w\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abc(:16|),er1\\)" \ + "xor.w @(0x12345678:32,er3.l),@(0x9abc:16,er1)" +gdb_test "x" "xor.w\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "xor.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1)" +gdb_test "x" "xor.w\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "xor.w @(0x12345678:32,er3.l),@(0x9abc:16,r2l.b)" +gdb_test "x" "xor.w\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abc(:16|),r2.w\\)" \ + "xor.w @(0x12345678:32,er3.l),@(0x9abc:16,r2.w)" +gdb_test "x" "xor.w\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abc(:16|),er2.l\\)" \ + "xor.w @(0x12345678:32,er3.l),@(0x9abc:16,er2.l)" +gdb_test "x" "xor.w\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "xor.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "xor.w\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "xor.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "xor.w\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "xor.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "xor.w\t@\\(0x12345678(:32|),er3.l\\),@0x9abc(:16|)" \ + "xor.w @(0x12345678:32,er3.l),@0x9abc:16" +gdb_test "x" "xor.w\t@\\(0x12345678(:32|),er3.l\\),@0x9abcdef0(:32|)" \ + "xor.w @(0x12345678:32,er3.l),@0x9abcdef0:32" +gdb_test "x" "xor.w\t@0x1234(:16|),@er1" \ + "xor.w @0x1234:16,@er1" +gdb_test "x" "xor.w\t@0x1234(:16|),@\\(0x6(:2|),er1\\)" \ + "xor.w @0x1234:16,@(0x6:2,er1)" +gdb_test "x" "xor.w\t@0x1234(:16|),@-er1" \ + "xor.w @0x1234:16,@-er1" +gdb_test "x" "xor.w\t@0x1234(:16|),@er1\\+" \ + "xor.w @0x1234:16,@er1+" +gdb_test "x" "xor.w\t@0x1234(:16|),@er1-" \ + "xor.w @0x1234:16,@er1-" +gdb_test "x" "xor.w\t@0x1234(:16|),@\\+er1" \ + "xor.w @0x1234:16,@+er1" +gdb_test "x" "xor.w\t@0x1234(:16|),@\\(0x9abc(:16|),er1\\)" \ + "xor.w @0x1234:16,@(0x9abc:16,er1)" +gdb_test "x" "xor.w\t@0x1234(:16|),@\\(0x9abcdef0(:32|),er1\\)" \ + "xor.w @0x1234:16,@(0x9abcdef0:32,er1)" +gdb_test "x" "xor.w\t@0x1234(:16|),@\\(0x9abc(:16|),r2l.b\\)" \ + "xor.w @0x1234:16,@(0x9abc:16,r2l.b)" +gdb_test "x" "xor.w\t@0x1234(:16|),@\\(0x9abc(:16|),r2.w\\)" \ + "xor.w @0x1234:16,@(0x9abc:16,r2.w)" +gdb_test "x" "xor.w\t@0x1234(:16|),@\\(0x9abc(:16|),er2.l\\)" \ + "xor.w @0x1234:16,@(0x9abc:16,er2.l)" +gdb_test "x" "xor.w\t@0x1234(:16|),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "xor.w @0x1234:16,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "xor.w\t@0x1234(:16|),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "xor.w @0x1234:16,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "xor.w\t@0x1234(:16|),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "xor.w @0x1234:16,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "xor.w\t@0x1234(:16|),@0x9abc(:16|)" \ + "xor.w @0x1234:16,@0x9abc:16" +gdb_test "x" "xor.w\t@0x1234(:16|),@0x9abcdef0(:32|)" \ + "xor.w @0x1234:16,@0x9abcdef0:32" +gdb_test "x" "xor.w\t@0x12345678(:32|),@er1" \ + "xor.w @0x12345678:32,@er1" +gdb_test "x" "xor.w\t@0x12345678(:32|),@\\(0x6(:2|),er1\\)" \ + "xor.w @0x12345678:32,@(0x6:2,er1)" +gdb_test "x" "xor.w\t@0x12345678(:32|),@-er1" \ + "xor.w @0x12345678:32,@-er1" +gdb_test "x" "xor.w\t@0x12345678(:32|),@er1\\+" \ + "xor.w @0x12345678:32,@er1+" +gdb_test "x" "xor.w\t@0x12345678(:32|),@er1-" \ + "xor.w @0x12345678:32,@er1-" +gdb_test "x" "xor.w\t@0x12345678(:32|),@\\+er1" \ + "xor.w @0x12345678:32,@+er1" +gdb_test "x" "xor.w\t@0x12345678(:32|),@\\(0x9abc(:16|),er1\\)" \ + "xor.w @0x12345678:32,@(0x9abc:16,er1)" +gdb_test "x" "xor.w\t@0x12345678(:32|),@\\(0x9abcdef0(:32|),er1\\)" \ + "xor.w @0x12345678:32,@(0x9abcdef0:32,er1)" +gdb_test "x" "xor.w\t@0x12345678(:32|),@\\(0x9abc(:16|),r2l.b\\)" \ + "xor.w @0x12345678:32,@(0x9abc:16,r2l.b)" +gdb_test "x" "xor.w\t@0x12345678(:32|),@\\(0x9abc(:16|),r2.w\\)" \ + "xor.w @0x12345678:32,@(0x9abc:16,r2.w)" +gdb_test "x" "xor.w\t@0x12345678(:32|),@\\(0x9abc(:16|),er2.l\\)" \ + "xor.w @0x12345678:32,@(0x9abc:16,er2.l)" +gdb_test "x" "xor.w\t@0x12345678(:32|),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "xor.w @0x12345678:32,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "xor.w\t@0x12345678(:32|),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "xor.w @0x12345678:32,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "xor.w\t@0x12345678(:32|),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "xor.w @0x12345678:32,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "xor.w\t@0x12345678(:32|),@0x9abc(:16|)" \ + "xor.w @0x12345678:32,@0x9abc:16" +gdb_test "x" "xor.w\t@0x12345678(:32|),@0x9abcdef0(:32|)" \ + "xor.w @0x12345678:32,@0x9abcdef0:32" +gdb_test "x" "xor.l\t#0x12345678(:32|),er1" \ + "xor.l #0x12345678:32,er1" +gdb_test "x" "xor.l\t#0x1234(:16|),er1" \ + "xor.l #0x1234:16,er1" +gdb_test "x" "xor.l\t#0x12345678(:32|),@er1" \ + "xor.l #0x12345678:32,@er1" +gdb_test "x" "xor.l\t#0x12345678(:32|),@\\(0xc(:2|),er1\\)" \ + "xor.l #0x12345678:32,@(0xc:2,er1)" +gdb_test "x" "xor.l\t#0x12345678(:32|),@er1\\+" \ + "xor.l #0x12345678:32,@er1+" +gdb_test "x" "xor.l\t#0x12345678(:32|),@-er1" \ + "xor.l #0x12345678:32,@-er1" +gdb_test "x" "xor.l\t#0x12345678(:32|),@\\+er1" \ + "xor.l #0x12345678:32,@+er1" +gdb_test "x" "xor.l\t#0x12345678(:32|),@er1-" \ + "xor.l #0x12345678:32,@er1-" +gdb_test "x" "xor.l\t#0x12345678(:32|),@\\(0x9abc(:16|),er1\\)" \ + "xor.l #0x12345678:32,@(0x9abc:16,er1)" +gdb_test "x" "xor.l\t#0x12345678(:32|),@\\(0x9abcdef0(:32|),er1\\)" \ + "xor.l #0x12345678:32,@(0x9abcdef0:32,er1)" +gdb_test "x" "xor.l\t#0x12345678(:32|),@\\(0x9abc(:16|),r2l.b\\)" \ + "xor.l #0x12345678:32,@(0x9abc:16,r2l.b)" +gdb_test "x" "xor.l\t#0x12345678(:32|),@\\(0x9abc(:16|),r2.w\\)" \ + "xor.l #0x12345678:32,@(0x9abc:16,r2.w)" +gdb_test "x" "xor.l\t#0x12345678(:32|),@\\(0x9abc(:16|),er2.l\\)" \ + "xor.l #0x12345678:32,@(0x9abc:16,er2.l)" +gdb_test "x" "xor.l\t#0x12345678(:32|),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "xor.l #0x12345678:32,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "xor.l\t#0x12345678(:32|),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "xor.l #0x12345678:32,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "xor.l\t#0x12345678(:32|),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "xor.l #0x12345678:32,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "xor.l\t#0x12345678(:32|),@0x9abc(:16|)" \ + "xor.l #0x12345678:32,@0x9abc:16" +gdb_test "x" "xor.l\t#0x12345678(:32|),@0x9abcdef0(:32|)" \ + "xor.l #0x12345678:32,@0x9abcdef0:32" +gdb_test "x" "xor.l\t#0x1234(:16|),@er1" \ + "xor.l #0x1234:16,@er1" +gdb_test "x" "xor.l\t#0x1234(:16|),@\\(0xc(:2|),er1\\)" \ + "xor.l #0x1234:16,@(0xc:2,er1)" +gdb_test "x" "xor.l\t#0x1234(:16|),@er1\\+" \ + "xor.l #0x1234:16,@er1+" +gdb_test "x" "xor.l\t#0x1234(:16|),@-er1" \ + "xor.l #0x1234:16,@-er1" +gdb_test "x" "xor.l\t#0x1234(:16|),@\\+er1" \ + "xor.l #0x1234:16,@+er1" +gdb_test "x" "xor.l\t#0x1234(:16|),@er1-" \ + "xor.l #0x1234:16,@er1-" +gdb_test "x" "xor.l\t#0x1234(:16|),@\\(0x9abc(:16|),er1\\)" \ + "xor.l #0x1234:16,@(0x9abc:16,er1)" +gdb_test "x" "xor.l\t#0x1234(:16|),@\\(0x9abcdef0(:32|),er1\\)" \ + "xor.l #0x1234:16,@(0x9abcdef0:32,er1)" +gdb_test "x" "xor.l\t#0x1234(:16|),@\\(0x9abc(:16|),r2l.b\\)" \ + "xor.l #0x1234:16,@(0x9abc:16,r2l.b)" +gdb_test "x" "xor.l\t#0x1234(:16|),@\\(0x9abc(:16|),r2.w\\)" \ + "xor.l #0x1234:16,@(0x9abc:16,r2.w)" +gdb_test "x" "xor.l\t#0x1234(:16|),@\\(0x9abc(:16|),er2.l\\)" \ + "xor.l #0x1234:16,@(0x9abc:16,er2.l)" +gdb_test "x" "xor.l\t#0x1234(:16|),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "xor.l #0x1234:16,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "xor.l\t#0x1234(:16|),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "xor.l #0x1234:16,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "xor.l\t#0x1234(:16|),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "xor.l #0x1234:16,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "xor.l\t#0x1234(:16|),@0x9abc(:16|)" \ + "xor.l #0x1234:16,@0x9abc:16" +gdb_test "x" "xor.l\t#0x1234(:16|),@0x9abcdef0(:32|)" \ + "xor.l #0x1234:16,@0x9abcdef0:32" +gdb_test "x" "xor.l\ter3,er1" \ + "xor.l er3,er1" +gdb_test "x" "xor.l\ter3,@er1" \ + "xor.l er3,@er1" +gdb_test "x" "xor.l\ter3,@\\(0xc(:2|),er1\\)" \ + "xor.l er3,@(0xc:2,er1)" +gdb_test "x" "xor.l\ter3,@er1\\+" \ + "xor.l er3,@er1+" +gdb_test "x" "xor.l\ter3,@-er1" \ + "xor.l er3,@-er1" +gdb_test "x" "xor.l\ter3,@\\+er1" \ + "xor.l er3,@+er1" +gdb_test "x" "xor.l\ter3,@er1-" \ + "xor.l er3,@er1-" +gdb_test "x" "xor.l\ter3,@\\(0x1234(:16|),er1\\)" \ + "xor.l er3,@(0x1234:16,er1)" +gdb_test "x" "xor.l\ter3,@\\(0x12345678(:32|),er1\\)" \ + "xor.l er3,@(0x12345678:32,er1)" +gdb_test "x" "xor.l\ter3,@\\(0x1234(:16|),r2l.b\\)" \ + "xor.l er3,@(0x1234:16,r2l.b)" +gdb_test "x" "xor.l\ter3,@\\(0x1234(:16|),r2.w\\)" \ + "xor.l er3,@(0x1234:16,r2.w)" +gdb_test "x" "xor.l\ter3,@\\(0x1234(:16|),er2.l\\)" \ + "xor.l er3,@(0x1234:16,er2.l)" +gdb_test "x" "xor.l\ter3,@\\(0x12345678(:32|),r2l.b\\)" \ + "xor.l er3,@(0x12345678:32,r2l.b)" +gdb_test "x" "xor.l\ter3,@\\(0x12345678(:32|),r2.w\\)" \ + "xor.l er3,@(0x12345678:32,r2.w)" +gdb_test "x" "xor.l\ter3,@\\(0x12345678(:32|),er2.l\\)" \ + "xor.l er3,@(0x12345678:32,er2.l)" +gdb_test "x" "xor.l\ter3,@0x1234(:16|)" \ + "xor.l er3,@0x1234:16" +gdb_test "x" "xor.l\ter3,@0x12345678(:32|)" \ + "xor.l er3,@0x12345678:32" +gdb_test "x" "xor.l\t@er3,er1" \ + "xor.l @er3,er1" +gdb_test "x" "xor.l\t@\\(0xc(:2|),er3\\),er1" \ + "xor.l @(0xc:2,er3),er1" +gdb_test "x" "xor.l\t@er3\\+,er1" \ + "xor.l @er3+,er1" +gdb_test "x" "xor.l\t@-er3,er1" \ + "xor.l @-er3,er1" +gdb_test "x" "xor.l\t@\\+er3,er1" \ + "xor.l @+er3,er1" +gdb_test "x" "xor.l\t@er3-,er1" \ + "xor.l @er3-,er1" +gdb_test "x" "xor.l\t@\\(0x1234(:16|),er1\\),er1" \ + "xor.l @(0x1234:16,er1),er1" +gdb_test "x" "xor.l\t@\\(0x12345678(:32|),er1\\),er1" \ + "xor.l @(0x12345678:32,er1),er1" +gdb_test "x" "xor.l\t@\\(0x1234(:16|),r2l.b\\),er1" \ + "xor.l @(0x1234:16,r2l.b),er1" +gdb_test "x" "xor.l\t@\\(0x1234(:16|),r2.w\\),er1" \ + "xor.l @(0x1234:16,r2.w),er1" +gdb_test "x" "xor.l\t@\\(0x1234(:16|),er2.l\\),er1" \ + "xor.l @(0x1234:16,er2.l),er1" +gdb_test "x" "xor.l\t@\\(0x12345678(:32|),r2l.b\\),er1" \ + "xor.l @(0x12345678:32,r2l.b),er1" +gdb_test "x" "xor.l\t@\\(0x12345678(:32|),r2.w\\),er1" \ + "xor.l @(0x12345678:32,r2.w),er1" +gdb_test "x" "xor.l\t@\\(0x12345678(:32|),er2.l\\),er1" \ + "xor.l @(0x12345678:32,er2.l),er1" +gdb_test "x" "xor.l\t@0x1234(:16|),er1" \ + "xor.l @0x1234:16,er1" +gdb_test "x" "xor.l\t@0x12345678(:32|),er1" \ + "xor.l @0x12345678:32,er1" +gdb_test "x" "xor.l\t@er3,@er1" \ + "xor.l @er3,@er1" +gdb_test "x" "xor.l\t@er3,@\\(0xc(:2|),er1\\)" \ + "xor.l @er3,@(0xc:2,er1)" +gdb_test "x" "xor.l\t@er3,@-er1" \ + "xor.l @er3,@-er1" +gdb_test "x" "xor.l\t@er3,@er1\\+" \ + "xor.l @er3,@er1+" +gdb_test "x" "xor.l\t@er3,@er1-" \ + "xor.l @er3,@er1-" +gdb_test "x" "xor.l\t@er3,@\\+er1" \ + "xor.l @er3,@+er1" +gdb_test "x" "xor.l\t@er3,@\\(0x9abc(:16|),er1\\)" \ + "xor.l @er3,@(0x9abc:16,er1)" +gdb_test "x" "xor.l\t@er3,@\\(0x9abcdef0(:32|),er1\\)" \ + "xor.l @er3,@(0x9abcdef0:32,er1)" +gdb_test "x" "xor.l\t@er3,@\\(0x9abc(:16|),r2l.b\\)" \ + "xor.l @er3,@(0x9abc:16,r2l.b)" +gdb_test "x" "xor.l\t@er3,@\\(0x9abc(:16|),r2.w\\)" \ + "xor.l @er3,@(0x9abc:16,r2.w)" +gdb_test "x" "xor.l\t@er3,@\\(0x9abc(:16|),er2.l\\)" \ + "xor.l @er3,@(0x9abc:16,er2.l)" +gdb_test "x" "xor.l\t@er3,@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "xor.l @er3,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "xor.l\t@er3,@\\(0x9abcdef0(:32|),r2.w\\)" \ + "xor.l @er3,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "xor.l\t@er3,@\\(0x9abcdef0(:32|),er2.l\\)" \ + "xor.l @er3,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "xor.l\t@er3,@0x9abc(:16|)" \ + "xor.l @er3,@0x9abc:16" +gdb_test "x" "xor.l\t@er3,@0x9abcdef0(:32|)" \ + "xor.l @er3,@0x9abcdef0:32" +gdb_test "x" "xor.l\t@\\(0xc(:2|),er3\\),@er1" \ + "xor.l @(0xc:2,er3),@er1" +gdb_test "x" "xor.l\t@\\(0xc(:2|),er3\\),@\\(0xc(:2|),er1\\)" \ + "xor.l @(0xc:2,er3),@(0xc:2,er1)" +gdb_test "x" "xor.l\t@\\(0xc(:2|),er3\\),@-er1" \ + "xor.l @(0xc:2,er3),@-er1" +gdb_test "x" "xor.l\t@\\(0xc(:2|),er3\\),@er1\\+" \ + "xor.l @(0xc:2,er3),@er1+" +gdb_test "x" "xor.l\t@\\(0xc(:2|),er3\\),@er1-" \ + "xor.l @(0xc:2,er3),@er1-" +gdb_test "x" "xor.l\t@\\(0xc(:2|),er3\\),@\\+er1" \ + "xor.l @(0xc:2,er3),@+er1" +gdb_test "x" "xor.l\t@\\(0xc(:2|),er3\\),@\\(0x9abc(:16|),er1\\)" \ + "xor.l @(0xc:2,er3),@(0x9abc:16,er1)" +gdb_test "x" "xor.l\t@\\(0xc(:2|),er3\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "xor.l @(0xc:2,er3),@(0x9abcdef0:32,er1)" +gdb_test "x" "xor.l\t@\\(0xc(:2|),er3\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "xor.l @(0xc:2,er3),@(0x9abc:16,r2l.b)" +gdb_test "x" "xor.l\t@\\(0xc(:2|),er3\\),@\\(0x9abc(:16|),r2.w\\)" \ + "xor.l @(0xc:2,er3),@(0x9abc:16,r2.w)" +gdb_test "x" "xor.l\t@\\(0xc(:2|),er3\\),@\\(0x9abc(:16|),er2.l\\)" \ + "xor.l @(0xc:2,er3),@(0x9abc:16,er2.l)" +gdb_test "x" "xor.l\t@\\(0xc(:2|),er3\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "xor.l @(0xc:2,er3),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "xor.l\t@\\(0xc(:2|),er3\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "xor.l @(0xc:2,er3),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "xor.l\t@\\(0xc(:2|),er3\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "xor.l @(0xc:2,er3),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "xor.l\t@\\(0xc(:2|),er3\\),@0x9abc(:16|)" \ + "xor.l @(0xc:2,er3),@0x9abc:16" +gdb_test "x" "xor.l\t@\\(0xc(:2|),er3\\),@0x9abcdef0(:32|)" \ + "xor.l @(0xc:2,er3),@0x9abcdef0:32" +gdb_test "x" "xor.l\t@-er3,@er1" \ + "xor.l @-er3,@er1" +gdb_test "x" "xor.l\t@-er3,@\\(0xc(:2|),er1\\)" \ + "xor.l @-er3,@(0xc:2,er1)" +gdb_test "x" "xor.l\t@-er3,@-er1" \ + "xor.l @-er3,@-er1" +gdb_test "x" "xor.l\t@-er3,@er1\\+" \ + "xor.l @-er3,@er1+" +gdb_test "x" "xor.l\t@-er3,@er1-" \ + "xor.l @-er3,@er1-" +gdb_test "x" "xor.l\t@-er3,@\\+er1" \ + "xor.l @-er3,@+er1" +gdb_test "x" "xor.l\t@-er3,@\\(0x9abc(:16|),er1\\)" \ + "xor.l @-er3,@(0x9abc:16,er1)" +gdb_test "x" "xor.l\t@-er3,@\\(0x9abcdef0(:32|),er1\\)" \ + "xor.l @-er3,@(0x9abcdef0:32,er1)" +gdb_test "x" "xor.l\t@-er3,@\\(0x9abc(:16|),r2l.b\\)" \ + "xor.l @-er3,@(0x9abc:16,r2l.b)" +gdb_test "x" "xor.l\t@-er3,@\\(0x9abc(:16|),r2.w\\)" \ + "xor.l @-er3,@(0x9abc:16,r2.w)" +gdb_test "x" "xor.l\t@-er3,@\\(0x9abc(:16|),er2.l\\)" \ + "xor.l @-er3,@(0x9abc:16,er2.l)" +gdb_test "x" "xor.l\t@-er3,@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "xor.l @-er3,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "xor.l\t@-er3,@\\(0x9abcdef0(:32|),r2.w\\)" \ + "xor.l @-er3,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "xor.l\t@-er3,@\\(0x9abcdef0(:32|),er2.l\\)" \ + "xor.l @-er3,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "xor.l\t@-er3,@0x9abc(:16|)" \ + "xor.l @-er3,@0x9abc:16" +gdb_test "x" "xor.l\t@-er3,@0x9abcdef0(:32|)" \ + "xor.l @-er3,@0x9abcdef0:32" +gdb_test "x" "xor.l\t@er3\\+,@er1" \ + "xor.l @er3+,@er1" +gdb_test "x" "xor.l\t@er3\\+,@\\(0xc(:2|),er1\\)" \ + "xor.l @er3+,@(0xc:2,er1)" +gdb_test "x" "xor.l\t@er3\\+,@-er1" \ + "xor.l @er3+,@-er1" +gdb_test "x" "xor.l\t@er3\\+,@er1\\+" \ + "xor.l @er3+,@er1+" +gdb_test "x" "xor.l\t@er3\\+,@er1-" \ + "xor.l @er3+,@er1-" +gdb_test "x" "xor.l\t@er3\\+,@\\+er1" \ + "xor.l @er3+,@+er1" +gdb_test "x" "xor.l\t@er3\\+,@\\(0x9abc(:16|),er1\\)" \ + "xor.l @er3+,@(0x9abc:16,er1)" +gdb_test "x" "xor.l\t@er3\\+,@\\(0x9abcdef0(:32|),er1\\)" \ + "xor.l @er3+,@(0x9abcdef0:32,er1)" +gdb_test "x" "xor.l\t@er3\\+,@\\(0x9abc(:16|),r2l.b\\)" \ + "xor.l @er3+,@(0x9abc:16,r2l.b)" +gdb_test "x" "xor.l\t@er3\\+,@\\(0x9abc(:16|),r2.w\\)" \ + "xor.l @er3+,@(0x9abc:16,r2.w)" +gdb_test "x" "xor.l\t@er3\\+,@\\(0x9abc(:16|),er2.l\\)" \ + "xor.l @er3+,@(0x9abc:16,er2.l)" +gdb_test "x" "xor.l\t@er3\\+,@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "xor.l @er3+,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "xor.l\t@er3\\+,@\\(0x9abcdef0(:32|),r2.w\\)" \ + "xor.l @er3+,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "xor.l\t@er3\\+,@\\(0x9abcdef0(:32|),er2.l\\)" \ + "xor.l @er3+,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "xor.l\t@er3\\+,@0x9abc(:16|)" \ + "xor.l @er3+,@0x9abc:16" +gdb_test "x" "xor.l\t@er3\\+,@0x9abcdef0(:32|)" \ + "xor.l @er3+,@0x9abcdef0:32" +gdb_test "x" "xor.l\t@er3-,@er1" \ + "xor.l @er3-,@er1" +gdb_test "x" "xor.l\t@er3-,@\\(0xc(:2|),er1\\)" \ + "xor.l @er3-,@(0xc:2,er1)" +gdb_test "x" "xor.l\t@er3-,@-er1" \ + "xor.l @er3-,@-er1" +gdb_test "x" "xor.l\t@er3-,@er1\\+" \ + "xor.l @er3-,@er1+" +gdb_test "x" "xor.l\t@er3-,@er1-" \ + "xor.l @er3-,@er1-" +gdb_test "x" "xor.l\t@er3-,@\\+er1" \ + "xor.l @er3-,@+er1" +gdb_test "x" "xor.l\t@er3-,@\\(0x9abc(:16|),er1\\)" \ + "xor.l @er3-,@(0x9abc:16,er1)" +gdb_test "x" "xor.l\t@er3-,@\\(0x9abcdef0(:32|),er1\\)" \ + "xor.l @er3-,@(0x9abcdef0:32,er1)" +gdb_test "x" "xor.l\t@er3-,@\\(0x9abc(:16|),r2l.b\\)" \ + "xor.l @er3-,@(0x9abc:16,r2l.b)" +gdb_test "x" "xor.l\t@er3-,@\\(0x9abc(:16|),r2.w\\)" \ + "xor.l @er3-,@(0x9abc:16,r2.w)" +gdb_test "x" "xor.l\t@er3-,@\\(0x9abc(:16|),er2.l\\)" \ + "xor.l @er3-,@(0x9abc:16,er2.l)" +gdb_test "x" "xor.l\t@er3-,@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "xor.l @er3-,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "xor.l\t@er3-,@\\(0x9abcdef0(:32|),r2.w\\)" \ + "xor.l @er3-,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "xor.l\t@er3-,@\\(0x9abcdef0(:32|),er2.l\\)" \ + "xor.l @er3-,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "xor.l\t@er3-,@0x9abc(:16|)" \ + "xor.l @er3-,@0x9abc:16" +gdb_test "x" "xor.l\t@er3-,@0x9abcdef0(:32|)" \ + "xor.l @er3-,@0x9abcdef0:32" +gdb_test "x" "xor.l\t@\\+er3,@er1" \ + "xor.l @+er3,@er1" +gdb_test "x" "xor.l\t@\\+er3,@\\(0xc(:2|),er1\\)" \ + "xor.l @+er3,@(0xc:2,er1)" +gdb_test "x" "xor.l\t@\\+er3,@-er1" \ + "xor.l @+er3,@-er1" +gdb_test "x" "xor.l\t@\\+er3,@er1\\+" \ + "xor.l @+er3,@er1+" +gdb_test "x" "xor.l\t@\\+er3,@er1-" \ + "xor.l @+er3,@er1-" +gdb_test "x" "xor.l\t@\\+er3,@\\+er1" \ + "xor.l @+er3,@+er1" +gdb_test "x" "xor.l\t@\\+er3,@\\(0x9abc(:16|),er1\\)" \ + "xor.l @+er3,@(0x9abc:16,er1)" +gdb_test "x" "xor.l\t@\\+er3,@\\(0x9abcdef0(:32|),er1\\)" \ + "xor.l @+er3,@(0x9abcdef0:32,er1)" +gdb_test "x" "xor.l\t@\\+er3,@\\(0x9abc(:16|),r2l.b\\)" \ + "xor.l @+er3,@(0x9abc:16,r2l.b)" +gdb_test "x" "xor.l\t@\\+er3,@\\(0x9abc(:16|),r2.w\\)" \ + "xor.l @+er3,@(0x9abc:16,r2.w)" +gdb_test "x" "xor.l\t@\\+er3,@\\(0x9abc(:16|),er2.l\\)" \ + "xor.l @+er3,@(0x9abc:16,er2.l)" +gdb_test "x" "xor.l\t@\\+er3,@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "xor.l @+er3,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "xor.l\t@\\+er3,@\\(0x9abcdef0(:32|),r2.w\\)" \ + "xor.l @+er3,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "xor.l\t@\\+er3,@\\(0x9abcdef0(:32|),er2.l\\)" \ + "xor.l @+er3,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "xor.l\t@\\+er3,@0x9abc(:16|)" \ + "xor.l @+er3,@0x9abc:16" +gdb_test "x" "xor.l\t@\\+er3,@0x9abcdef0(:32|)" \ + "xor.l @+er3,@0x9abcdef0:32" +gdb_test "x" "xor.l\t@\\(0x1234(:16|),er3\\),@er1" \ + "xor.l @(0x1234:16,er3),@er1" +gdb_test "x" "xor.l\t@\\(0x1234(:16|),er3\\),@\\(0xc(:2|),er1\\)" \ + "xor.l @(0x1234:16,er3),@(0xc:2,er1)" +gdb_test "x" "xor.l\t@\\(0x1234(:16|),er3\\),@-er1" \ + "xor.l @(0x1234:16,er3),@-er1" +gdb_test "x" "xor.l\t@\\(0x1234(:16|),er3\\),@er1\\+" \ + "xor.l @(0x1234:16,er3),@er1+" +gdb_test "x" "xor.l\t@\\(0x1234(:16|),er3\\),@er1-" \ + "xor.l @(0x1234:16,er3),@er1-" +gdb_test "x" "xor.l\t@\\(0x1234(:16|),er3\\),@\\+er1" \ + "xor.l @(0x1234:16,er3),@+er1" +gdb_test "x" "xor.l\t@\\(0x1234(:16|),er3\\),@\\(0x9abc(:16|),er1\\)" \ + "xor.l @(0x1234:16,er3),@(0x9abc:16,er1)" +gdb_test "x" "xor.l\t@\\(0x1234(:16|),er3\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "xor.l @(0x1234:16,er3),@(0x9abcdef0:32,er1)" +gdb_test "x" "xor.l\t@\\(0x1234(:16|),er3\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "xor.l @(0x1234:16,er3),@(0x9abc:16,r2l.b)" +gdb_test "x" "xor.l\t@\\(0x1234(:16|),er3\\),@\\(0x9abc(:16|),r2.w\\)" \ + "xor.l @(0x1234:16,er3),@(0x9abc:16,r2.w)" +gdb_test "x" "xor.l\t@\\(0x1234(:16|),er3\\),@\\(0x9abc(:16|),er2.l\\)" \ + "xor.l @(0x1234:16,er3),@(0x9abc:16,er2.l)" +gdb_test "x" "xor.l\t@\\(0x1234(:16|),er3\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "xor.l @(0x1234:16,er3),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "xor.l\t@\\(0x1234(:16|),er3\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "xor.l @(0x1234:16,er3),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "xor.l\t@\\(0x1234(:16|),er3\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "xor.l @(0x1234:16,er3),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "xor.l\t@\\(0x1234(:16|),er3\\),@0x9abc(:16|)" \ + "xor.l @(0x1234:16,er3),@0x9abc:16" +gdb_test "x" "xor.l\t@\\(0x1234(:16|),er3\\),@0x9abcdef0(:32|)" \ + "xor.l @(0x1234:16,er3),@0x9abcdef0:32" +gdb_test "x" "xor.l\t@\\(0x12345678(:32|),er3\\),@er1" \ + "xor.l @(0x12345678:32,er3),@er1" +gdb_test "x" "xor.l\t@\\(0x12345678(:32|),er3\\),@\\(0xc(:2|),er1\\)" \ + "xor.l @(0x12345678:32,er3),@(0xc:2,er1)" +gdb_test "x" "xor.l\t@\\(0x12345678(:32|),er3\\),@-er1" \ + "xor.l @(0x12345678:32,er3),@-er1" +gdb_test "x" "xor.l\t@\\(0x12345678(:32|),er3\\),@er1\\+" \ + "xor.l @(0x12345678:32,er3),@er1+" +gdb_test "x" "xor.l\t@\\(0x12345678(:32|),er3\\),@er1-" \ + "xor.l @(0x12345678:32,er3),@er1-" +gdb_test "x" "xor.l\t@\\(0x12345678(:32|),er3\\),@\\+er1" \ + "xor.l @(0x12345678:32,er3),@+er1" +gdb_test "x" "xor.l\t@\\(0x12345678(:32|),er3\\),@\\(0x9abc(:16|),er1\\)" \ + "xor.l @(0x12345678:32,er3),@(0x9abc:16,er1)" +gdb_test "x" "xor.l\t@\\(0x12345678(:32|),er3\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "xor.l @(0x12345678:32,er3),@(0x9abcdef0:32,er1)" +gdb_test "x" "xor.l\t@\\(0x12345678(:32|),er3\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "xor.l @(0x12345678:32,er3),@(0x9abc:16,r2l.b)" +gdb_test "x" "xor.l\t@\\(0x12345678(:32|),er3\\),@\\(0x9abc(:16|),r2.w\\)" \ + "xor.l @(0x12345678:32,er3),@(0x9abc:16,r2.w)" +gdb_test "x" "xor.l\t@\\(0x12345678(:32|),er3\\),@\\(0x9abc(:16|),er2.l\\)" \ + "xor.l @(0x12345678:32,er3),@(0x9abc:16,er2.l)" +gdb_test "x" "xor.l\t@\\(0x12345678(:32|),er3\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "xor.l @(0x12345678:32,er3),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "xor.l\t@\\(0x12345678(:32|),er3\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "xor.l @(0x12345678:32,er3),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "xor.l\t@\\(0x12345678(:32|),er3\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "xor.l @(0x12345678:32,er3),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "xor.l\t@\\(0x12345678(:32|),er3\\),@0x9abc(:16|)" \ + "xor.l @(0x12345678:32,er3),@0x9abc:16" +gdb_test "x" "xor.l\t@\\(0x12345678(:32|),er3\\),@0x9abcdef0(:32|)" \ + "xor.l @(0x12345678:32,er3),@0x9abcdef0:32" +gdb_test "x" "xor.l\t@\\(0x1234(:16|),r3l.b\\),@er1" \ + "xor.l @(0x1234:16,r3l.b),@er1" +gdb_test "x" "xor.l\t@\\(0x1234(:16|),r3l.b\\),@\\(0xc(:2|),er1\\)" \ + "xor.l @(0x1234:16,r3l.b),@(0xc:2,er1)" +gdb_test "x" "xor.l\t@\\(0x1234(:16|),r3l.b\\),@-er1" \ + "xor.l @(0x1234:16,r3l.b),@-er1" +gdb_test "x" "xor.l\t@\\(0x1234(:16|),r3l.b\\),@er1\\+" \ + "xor.l @(0x1234:16,r3l.b),@er1+" +gdb_test "x" "xor.l\t@\\(0x1234(:16|),r3l.b\\),@er1-" \ + "xor.l @(0x1234:16,r3l.b),@er1-" +gdb_test "x" "xor.l\t@\\(0x1234(:16|),r3l.b\\),@\\+er1" \ + "xor.l @(0x1234:16,r3l.b),@+er1" +gdb_test "x" "xor.l\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abc(:16|),er1\\)" \ + "xor.l @(0x1234:16,r3l.b),@(0x9abc:16,er1)" +gdb_test "x" "xor.l\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "xor.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1)" +gdb_test "x" "xor.l\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "xor.l @(0x1234:16,r3l.b),@(0x9abc:16,r2l.b)" +gdb_test "x" "xor.l\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abc(:16|),r2.w\\)" \ + "xor.l @(0x1234:16,r3l.b),@(0x9abc:16,r2.w)" +gdb_test "x" "xor.l\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abc(:16|),er2.l\\)" \ + "xor.l @(0x1234:16,r3l.b),@(0x9abc:16,er2.l)" +gdb_test "x" "xor.l\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "xor.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "xor.l\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "xor.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "xor.l\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "xor.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "xor.l\t@\\(0x1234(:16|),r3l.b\\),@0x9abc(:16|)" \ + "xor.l @(0x1234:16,r3l.b),@0x9abc:16" +gdb_test "x" "xor.l\t@\\(0x1234(:16|),r3l.b\\),@0x9abcdef0(:32|)" \ + "xor.l @(0x1234:16,r3l.b),@0x9abcdef0:32" +gdb_test "x" "xor.l\t@\\(0x1234(:16|),r3.w\\),@er1" \ + "xor.l @(0x1234:16,r3.w),@er1" +gdb_test "x" "xor.l\t@\\(0x1234(:16|),r3.w\\),@\\(0xc(:2|),er1\\)" \ + "xor.l @(0x1234:16,r3.w),@(0xc:2,er1)" +gdb_test "x" "xor.l\t@\\(0x1234(:16|),r3.w\\),@-er1" \ + "xor.l @(0x1234:16,r3.w),@-er1" +gdb_test "x" "xor.l\t@\\(0x1234(:16|),r3.w\\),@er1\\+" \ + "xor.l @(0x1234:16,r3.w),@er1+" +gdb_test "x" "xor.l\t@\\(0x1234(:16|),r3.w\\),@er1-" \ + "xor.l @(0x1234:16,r3.w),@er1-" +gdb_test "x" "xor.l\t@\\(0x1234(:16|),r3.w\\),@\\+er1" \ + "xor.l @(0x1234:16,r3.w),@+er1" +gdb_test "x" "xor.l\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abc(:16|),er1\\)" \ + "xor.l @(0x1234:16,r3.w),@(0x9abc:16,er1)" +gdb_test "x" "xor.l\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "xor.l @(0x1234:16,r3.w),@(0x9abcdef0:32,er1)" +gdb_test "x" "xor.l\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "xor.l @(0x1234:16,r3.w),@(0x9abc:16,r2l.b)" +gdb_test "x" "xor.l\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abc(:16|),r2.w\\)" \ + "xor.l @(0x1234:16,r3.w),@(0x9abc:16,r2.w)" +gdb_test "x" "xor.l\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abc(:16|),er2.l\\)" \ + "xor.l @(0x1234:16,r3.w),@(0x9abc:16,er2.l)" +gdb_test "x" "xor.l\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "xor.l @(0x1234:16,r3.w),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "xor.l\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "xor.l @(0x1234:16,r3.w),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "xor.l\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "xor.l @(0x1234:16,r3.w),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "xor.l\t@\\(0x1234(:16|),r3.w\\),@0x9abc(:16|)" \ + "xor.l @(0x1234:16,r3.w),@0x9abc:16" +gdb_test "x" "xor.l\t@\\(0x1234(:16|),r3.w\\),@0x9abcdef0(:32|)" \ + "xor.l @(0x1234:16,r3.w),@0x9abcdef0:32" +gdb_test "x" "xor.l\t@\\(0x1234(:16|),er3.l\\),@er1" \ + "xor.l @(0x1234:16,er3.l),@er1" +gdb_test "x" "xor.l\t@\\(0x1234(:16|),er3.l\\),@\\(0xc(:2|),er1\\)" \ + "xor.l @(0x1234:16,er3.l),@(0xc:2,er1)" +gdb_test "x" "xor.l\t@\\(0x1234(:16|),er3.l\\),@-er1" \ + "xor.l @(0x1234:16,er3.l),@-er1" +gdb_test "x" "xor.l\t@\\(0x1234(:16|),er3.l\\),@er1\\+" \ + "xor.l @(0x1234:16,er3.l),@er1+" +gdb_test "x" "xor.l\t@\\(0x1234(:16|),er3.l\\),@er1-" \ + "xor.l @(0x1234:16,er3.l),@er1-" +gdb_test "x" "xor.l\t@\\(0x1234(:16|),er3.l\\),@\\+er1" \ + "xor.l @(0x1234:16,er3.l),@+er1" +gdb_test "x" "xor.l\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abc(:16|),er1\\)" \ + "xor.l @(0x1234:16,er3.l),@(0x9abc:16,er1)" +gdb_test "x" "xor.l\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "xor.l @(0x1234:16,er3.l),@(0x9abcdef0:32,er1)" +gdb_test "x" "xor.l\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "xor.l @(0x1234:16,er3.l),@(0x9abc:16,r2l.b)" +gdb_test "x" "xor.l\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abc(:16|),r2.w\\)" \ + "xor.l @(0x1234:16,er3.l),@(0x9abc:16,r2.w)" +gdb_test "x" "xor.l\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abc(:16|),er2.l\\)" \ + "xor.l @(0x1234:16,er3.l),@(0x9abc:16,er2.l)" +gdb_test "x" "xor.l\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "xor.l @(0x1234:16,er3.l),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "xor.l\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "xor.l @(0x1234:16,er3.l),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "xor.l\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "xor.l @(0x1234:16,er3.l),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "xor.l\t@\\(0x1234(:16|),er3.l\\),@0x9abc(:16|)" \ + "xor.l @(0x1234:16,er3.l),@0x9abc:16" +gdb_test "x" "xor.l\t@\\(0x1234(:16|),er3.l\\),@0x9abcdef0(:32|)" \ + "xor.l @(0x1234:16,er3.l),@0x9abcdef0:32" +gdb_test "x" "xor.l\t@\\(0x12345678(:32|),r3l.b\\),@er1" \ + "xor.l @(0x12345678:32,r3l.b),@er1" +gdb_test "x" "xor.l\t@\\(0x12345678(:32|),r3l.b\\),@\\(0xc(:2|),er1\\)" \ + "xor.l @(0x12345678:32,r3l.b),@(0xc:2,er1)" +gdb_test "x" "xor.l\t@\\(0x12345678(:32|),r3l.b\\),@-er1" \ + "xor.l @(0x12345678:32,r3l.b),@-er1" +gdb_test "x" "xor.l\t@\\(0x12345678(:32|),r3l.b\\),@er1\\+" \ + "xor.l @(0x12345678:32,r3l.b),@er1+" +gdb_test "x" "xor.l\t@\\(0x12345678(:32|),r3l.b\\),@er1-" \ + "xor.l @(0x12345678:32,r3l.b),@er1-" +gdb_test "x" "xor.l\t@\\(0x12345678(:32|),r3l.b\\),@\\+er1" \ + "xor.l @(0x12345678:32,r3l.b),@+er1" +gdb_test "x" "xor.l\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abc(:16|),er1\\)" \ + "xor.l @(0x12345678:32,r3l.b),@(0x9abc:16,er1)" +gdb_test "x" "xor.l\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "xor.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1)" +gdb_test "x" "xor.l\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "xor.l @(0x12345678:32,r3l.b),@(0x9abc:16,r2l.b)" +gdb_test "x" "xor.l\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abc(:16|),r2.w\\)" \ + "xor.l @(0x12345678:32,r3l.b),@(0x9abc:16,r2.w)" +gdb_test "x" "xor.l\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abc(:16|),er2.l\\)" \ + "xor.l @(0x12345678:32,r3l.b),@(0x9abc:16,er2.l)" +gdb_test "x" "xor.l\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "xor.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "xor.l\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "xor.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "xor.l\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "xor.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "xor.l\t@\\(0x12345678(:32|),r3l.b\\),@0x9abc(:16|)" \ + "xor.l @(0x12345678:32,r3l.b),@0x9abc:16" +gdb_test "x" "xor.l\t@\\(0x12345678(:32|),r3l.b\\),@0x9abcdef0(:32|)" \ + "xor.l @(0x12345678:32,r3l.b),@0x9abcdef0:32" +gdb_test "x" "xor.l\t@\\(0x12345678(:32|),r3.w\\),@er1" \ + "xor.l @(0x12345678:32,r3.w),@er1" +gdb_test "x" "xor.l\t@\\(0x12345678(:32|),r3.w\\),@\\(0xc(:2|),er1\\)" \ + "xor.l @(0x12345678:32,r3.w),@(0xc:2,er1)" +gdb_test "x" "xor.l\t@\\(0x12345678(:32|),r3.w\\),@-er1" \ + "xor.l @(0x12345678:32,r3.w),@-er1" +gdb_test "x" "xor.l\t@\\(0x12345678(:32|),r3.w\\),@er1\\+" \ + "xor.l @(0x12345678:32,r3.w),@er1+" +gdb_test "x" "xor.l\t@\\(0x12345678(:32|),r3.w\\),@er1-" \ + "xor.l @(0x12345678:32,r3.w),@er1-" +gdb_test "x" "xor.l\t@\\(0x12345678(:32|),r3.w\\),@\\+er1" \ + "xor.l @(0x12345678:32,r3.w),@+er1" +gdb_test "x" "xor.l\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abc(:16|),er1\\)" \ + "xor.l @(0x12345678:32,r3.w),@(0x9abc:16,er1)" +gdb_test "x" "xor.l\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "xor.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1)" +gdb_test "x" "xor.l\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "xor.l @(0x12345678:32,r3.w),@(0x9abc:16,r2l.b)" +gdb_test "x" "xor.l\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abc(:16|),r2.w\\)" \ + "xor.l @(0x12345678:32,r3.w),@(0x9abc:16,r2.w)" +gdb_test "x" "xor.l\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abc(:16|),er2.l\\)" \ + "xor.l @(0x12345678:32,r3.w),@(0x9abc:16,er2.l)" +gdb_test "x" "xor.l\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "xor.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "xor.l\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "xor.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "xor.l\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "xor.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "xor.l\t@\\(0x12345678(:32|),r3.w\\),@0x9abc(:16|)" \ + "xor.l @(0x12345678:32,r3.w),@0x9abc:16" +gdb_test "x" "xor.l\t@\\(0x12345678(:32|),r3.w\\),@0x9abcdef0(:32|)" \ + "xor.l @(0x12345678:32,r3.w),@0x9abcdef0:32" +gdb_test "x" "xor.l\t@\\(0x12345678(:32|),er3.l\\),@er1" \ + "xor.l @(0x12345678:32,er3.l),@er1" +gdb_test "x" "xor.l\t@\\(0x12345678(:32|),er3.l\\),@\\(0xc(:2|),er1\\)" \ + "xor.l @(0x12345678:32,er3.l),@(0xc:2,er1)" +gdb_test "x" "xor.l\t@\\(0x12345678(:32|),er3.l\\),@-er1" \ + "xor.l @(0x12345678:32,er3.l),@-er1" +gdb_test "x" "xor.l\t@\\(0x12345678(:32|),er3.l\\),@er1\\+" \ + "xor.l @(0x12345678:32,er3.l),@er1+" +gdb_test "x" "xor.l\t@\\(0x12345678(:32|),er3.l\\),@er1-" \ + "xor.l @(0x12345678:32,er3.l),@er1-" +gdb_test "x" "xor.l\t@\\(0x12345678(:32|),er3.l\\),@\\+er1" \ + "xor.l @(0x12345678:32,er3.l),@+er1" +gdb_test "x" "xor.l\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abc(:16|),er1\\)" \ + "xor.l @(0x12345678:32,er3.l),@(0x9abc:16,er1)" +gdb_test "x" "xor.l\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "xor.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1)" +gdb_test "x" "xor.l\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "xor.l @(0x12345678:32,er3.l),@(0x9abc:16,r2l.b)" +gdb_test "x" "xor.l\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abc(:16|),r2.w\\)" \ + "xor.l @(0x12345678:32,er3.l),@(0x9abc:16,r2.w)" +gdb_test "x" "xor.l\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abc(:16|),er2.l\\)" \ + "xor.l @(0x12345678:32,er3.l),@(0x9abc:16,er2.l)" +gdb_test "x" "xor.l\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "xor.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "xor.l\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "xor.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "xor.l\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "xor.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "xor.l\t@\\(0x12345678(:32|),er3.l\\),@0x9abc(:16|)" \ + "xor.l @(0x12345678:32,er3.l),@0x9abc:16" +gdb_test "x" "xor.l\t@\\(0x12345678(:32|),er3.l\\),@0x9abcdef0(:32|)" \ + "xor.l @(0x12345678:32,er3.l),@0x9abcdef0:32" +gdb_test "x" "xor.l\t@0x1234(:16|),@er1" \ + "xor.l @0x1234:16,@er1" +gdb_test "x" "xor.l\t@0x1234(:16|),@\\(0xc(:2|),er1\\)" \ + "xor.l @0x1234:16,@(0xc:2,er1)" +gdb_test "x" "xor.l\t@0x1234(:16|),@-er1" \ + "xor.l @0x1234:16,@-er1" +gdb_test "x" "xor.l\t@0x1234(:16|),@er1\\+" \ + "xor.l @0x1234:16,@er1+" +gdb_test "x" "xor.l\t@0x1234(:16|),@er1-" \ + "xor.l @0x1234:16,@er1-" +gdb_test "x" "xor.l\t@0x1234(:16|),@\\+er1" \ + "xor.l @0x1234:16,@+er1" +gdb_test "x" "xor.l\t@0x1234(:16|),@\\(0x9abc(:16|),er1\\)" \ + "xor.l @0x1234:16,@(0x9abc:16,er1)" +gdb_test "x" "xor.l\t@0x1234(:16|),@\\(0x9abcdef0(:32|),er1\\)" \ + "xor.l @0x1234:16,@(0x9abcdef0:32,er1)" +gdb_test "x" "xor.l\t@0x1234(:16|),@\\(0x9abc(:16|),r2l.b\\)" \ + "xor.l @0x1234:16,@(0x9abc:16,r2l.b)" +gdb_test "x" "xor.l\t@0x1234(:16|),@\\(0x9abc(:16|),r2.w\\)" \ + "xor.l @0x1234:16,@(0x9abc:16,r2.w)" +gdb_test "x" "xor.l\t@0x1234(:16|),@\\(0x9abc(:16|),er2.l\\)" \ + "xor.l @0x1234:16,@(0x9abc:16,er2.l)" +gdb_test "x" "xor.l\t@0x1234(:16|),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "xor.l @0x1234:16,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "xor.l\t@0x1234(:16|),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "xor.l @0x1234:16,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "xor.l\t@0x1234(:16|),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "xor.l @0x1234:16,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "xor.l\t@0x1234(:16|),@0x9abc(:16|)" \ + "xor.l @0x1234:16,@0x9abc:16" +gdb_test "x" "xor.l\t@0x1234(:16|),@0x9abcdef0(:32|)" \ + "xor.l @0x1234:16,@0x9abcdef0:32" +gdb_test "x" "xor.l\t@0x12345678(:32|),@er1" \ + "xor.l @0x12345678:32,@er1" +gdb_test "x" "xor.l\t@0x12345678(:32|),@\\(0xc(:2|),er1\\)" \ + "xor.l @0x12345678:32,@(0xc:2,er1)" +gdb_test "x" "xor.l\t@0x12345678(:32|),@-er1" \ + "xor.l @0x12345678:32,@-er1" +gdb_test "x" "xor.l\t@0x12345678(:32|),@er1\\+" \ + "xor.l @0x12345678:32,@er1+" +gdb_test "x" "xor.l\t@0x12345678(:32|),@er1-" \ + "xor.l @0x12345678:32,@er1-" +gdb_test "x" "xor.l\t@0x12345678(:32|),@\\+er1" \ + "xor.l @0x12345678:32,@+er1" +gdb_test "x" "xor.l\t@0x12345678(:32|),@\\(0x9abc(:16|),er1\\)" \ + "xor.l @0x12345678:32,@(0x9abc:16,er1)" +gdb_test "x" "xor.l\t@0x12345678(:32|),@\\(0x9abcdef0(:32|),er1\\)" \ + "xor.l @0x12345678:32,@(0x9abcdef0:32,er1)" +gdb_test "x" "xor.l\t@0x12345678(:32|),@\\(0x9abc(:16|),r2l.b\\)" \ + "xor.l @0x12345678:32,@(0x9abc:16,r2l.b)" +gdb_test "x" "xor.l\t@0x12345678(:32|),@\\(0x9abc(:16|),r2.w\\)" \ + "xor.l @0x12345678:32,@(0x9abc:16,r2.w)" +gdb_test "x" "xor.l\t@0x12345678(:32|),@\\(0x9abc(:16|),er2.l\\)" \ + "xor.l @0x12345678:32,@(0x9abc:16,er2.l)" +gdb_test "x" "xor.l\t@0x12345678(:32|),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "xor.l @0x12345678:32,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "xor.l\t@0x12345678(:32|),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "xor.l @0x12345678:32,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "xor.l\t@0x12345678(:32|),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "xor.l @0x12345678:32,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "xor.l\t@0x12345678(:32|),@0x9abc(:16|)" \ + "xor.l @0x12345678:32,@0x9abc:16" +gdb_test "x" "xor.l\t@0x12345678(:32|),@0x9abcdef0(:32|)" \ + "xor.l @0x12345678:32,@0x9abcdef0:32" diff --git a/gdb/testsuite/gdb.disasm/t09_xor.s b/gdb/testsuite/gdb.disasm/t09_xor.s new file mode 100644 index 0000000..7b9e8c4 --- /dev/null +++ b/gdb/testsuite/gdb.disasm/t09_xor.s @@ -0,0 +1,972 @@ +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;log_1 +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + .h8300sx + .text + .global _start +_start: + xor.b #0x12:8,r1h ;d112 + xor.b #0x12:8,@er1 ;7d10d012 + xor.b #0x12:8,@(0x3:2,er1) ;01776818d012 + xor.b #0x12:8,@er1+ ;01746c18d012 + xor.b #0x12:8,@-er1 ;01776c18d012 + xor.b #0x12:8,@+er1 ;01756c18d012 + xor.b #0x12:8,@er1- ;01766c18d012 + xor.b #0x12:8,@(0x1234:16,er1) ;01746e181234d012 + xor.b #0x12:8,@(0x12345678:32,er1) ;78146a2812345678d012 + xor.b #0x12:8,@(0x1234:16,r2l.b) ;01756e281234d012 + xor.b #0x12:8,@(0x1234:16,r2.w) ;01766e281234d012 + xor.b #0x12:8,@(0x1234:16,er2.l) ;01776e281234d012 + xor.b #0x12:8,@(0x12345678:32,r2l.b) ;78256a2812345678d012 + xor.b #0x12:8,@(0x12345678:32,r2.w) ;78266a2812345678d012 + xor.b #0x12:8,@(0x12345678:32,er2.l) ;78276a2812345678d012 + xor.b #0x12:8,@0xffffff12:8 ;7f12d012 + xor.b #0x12:8,@0x1234:16 ;6a181234d012 + xor.b #0x12:8,@0x12345678:32 ;6a3812345678d012 + + xor.b r3h,r1h ;1531 + + xor.b r3h,@er1 ;7d101530 + xor.b r3h,@(0x3:2,er1) ;01793153 + xor.b r3h,@er1+ ;01798153 + xor.b r3h,@-er1 ;0179b153 + xor.b r3h,@+er1 ;01799153 + xor.b r3h,@er1- ;0179a153 + xor.b r3h,@(0x1234:16,er1) ;0179c1531234 + xor.b r3h,@(0x12345678:32,er1) ;0179c95312345678 + xor.b r3h,@(0x1234:16,r2l.b) ;0179d2531234 + xor.b r3h,@(0x1234:16,r2.w) ;0179e2531234 + xor.b r3h,@(0x1234:16,er2.l) ;0179f2531234 + xor.b r3h,@(0x12345678:32,r2l.b) ;0179da5312345678 + xor.b r3h,@(0x12345678:32,r2.w) ;0179ea5312345678 + xor.b r3h,@(0x12345678:32,er2.l) ;0179fa5312345678 + xor.b r3h,@0xffffff12:8 ;7f121530 + xor.b r3h,@0x1234:16 ;6a1812341530 + xor.b r3h,@0x12345678:32 ;6a38123456781530 + + xor.b @er3,r1h ;7c301501 + xor.b @(0x3:2,er3),r1h ;017a3351 + xor.b @er3+,r1h ;017a8351 + xor.b @-er3,r1h ;017ab351 + xor.b @+er3,r1h ;017a9351 + xor.b @er3-,r1h ;017aa351 + xor.b @(0x1234:16,er1),r1h ;017ac1511234 + xor.b @(0x12345678:32,er1),r1h ;017ac95112345678 + xor.b @(0x1234:16,r2l.b),r1h ;017ad2511234 + xor.b @(0x1234:16,r2.w),r1h ;017ae2511234 + xor.b @(0x1234:16,er2.l),r1h ;017af2511234 + xor.b @(0x12345678:32,r2l.b),r1h ;017ada5112345678 + xor.b @(0x12345678:32,r2.w),r1h ;017aea5112345678 + xor.b @(0x12345678:32,er2.l),r1h ;017afa5112345678 + xor.b @0xffffff12:8,r1h ;7e121501 + xor.b @0x1234:16,r1h ;6a1012341501 + xor.b @0x12345678:32,r1h ;6a30123456781501 + + xor.b @er3,@er1 ;7c350150 + xor.b @er3,@(3:2,er1) ;7c353150 + xor.b @er3,@-er1 ;7c35b150 + xor.b @er3,@er1+ ;7c358150 + xor.b @er3,@er1- ;7c35a150 + xor.b @er3,@+er1 ;7c359150 + xor.b @er3,@(0xffff9abc:16,er1) ;7c35c1509abc + xor.b @er3,@(0x9abcdef0:32,er1) ;7c35c9509abcdef0 + xor.b @er3,@(0xffff9abc:16,r2l.b) ;7c35d2509abc + xor.b @er3,@(0xffff9abc:16,r2.w) ;7c35e2509abc + xor.b @er3,@(0xffff9abc:16,er2.l) ;7c35f2509abc + xor.b @er3,@(0x9abcdef0:32,r2l.b) ;7c35da509abcdef0 + xor.b @er3,@(0x9abcdef0:32,r2.w) ;7c35ea509abcdef0 + xor.b @er3,@(0x9abcdef0:32,er2.l) ;7c35fa509abcdef0 + xor.b @er3,@0xffff9abc:16 ;7c3540509abc + xor.b @er3,@0x9abcdef0:32 ;7c3548509abcdef0 + + xor.b @-er3,@er1 ;01776c3c0150 + xor.b @-er3,@(3:2,er1) ;01776c3c3150 + xor.b @-er3,@-er1 ;01776c3cb150 + xor.b @-er3,@er1+ ;01776c3c8150 + xor.b @-er3,@er1- ;01776c3ca150 + xor.b @-er3,@+er1 ;01776c3c9150 + xor.b @-er3,@(0xffff9abc:16,er1) ;01776c3cc1509abc + xor.b @-er3,@(0x9abcdef0:32,er1) ;01776c3cc9509abcdef0 + xor.b @-er3,@(0xffff9abc:16,r2l.b) ;01776c3cd2509abc + xor.b @-er3,@(0xffff9abc:16,r2.w) ;01776c3ce2509abc + xor.b @-er3,@(0xffff9abc:16,er2.l) ;01776c3cf2509abc + xor.b @-er3,@(0x9abcdef0:32,r2l.b) ;01776c3cda509abcdef0 + xor.b @-er3,@(0x9abcdef0:32,r2.w) ;01776c3cea509abcdef0 + xor.b @-er3,@(0x9abcdef0:32,er2.l) ;01776c3cfa509abcdef0 + xor.b @-er3,@0xffff9abc:16 ;01776c3c40509abc + xor.b @-er3,@0x9abcdef0:32 ;01776c3c48509abcdef0 + + xor.b @er3+,@er1 ;01746c3c0150 + xor.b @er3+,@(3:2,er1) ;01746c3c3150 + xor.b @er3+,@-er1 ;01746c3cb150 + xor.b @er3+,@er1+ ;01746c3c8150 + xor.b @er3+,@er1- ;01746c3ca150 + xor.b @er3+,@+er1 ;01746c3c9150 + xor.b @er3+,@(0xffff9abc:16,er1) ;01746c3cc1509abc + xor.b @er3+,@(0x9abcdef0:32,er1) ;01746c3cc9509abcdef0 + xor.b @er3+,@(0xffff9abc:16,r2l.b) ;01746c3cd2509abc + xor.b @er3+,@(0xffff9abc:16,r2.w) ;01746c3ce2509abc + xor.b @er3+,@(0xffff9abc:16,er2.l) ;01746c3cf2509abc + xor.b @er3+,@(0x9abcdef0:32,r2l.b) ;01746c3cda509abcdef0 + xor.b @er3+,@(0x9abcdef0:32,r2.w) ;01746c3cea509abcdef0 + xor.b @er3+,@(0x9abcdef0:32,er2.l) ;01746c3cfa509abcdef0 + xor.b @er3+,@0xffff9abc:16 ;01746c3c40509abc + xor.b @er3+,@0x9abcdef0:32 ;01746c3c48509abcdef0 + + xor.b @er3-,@er1 ;01766c3c0150 + xor.b @er3-,@(3:2,er1) ;01766c3c3150 + xor.b @er3-,@-er1 ;01766c3cb150 + xor.b @er3-,@er1+ ;01766c3c8150 + xor.b @er3-,@er1- ;01766c3ca150 + xor.b @er3-,@+er1 ;01766c3c9150 + xor.b @er3-,@(0xffff9abc:16,er1) ;01766c3cc1509abc + xor.b @er3-,@(0x9abcdef0:32,er1) ;01766c3cc9509abcdef0 + xor.b @er3-,@(0xffff9abc:16,r2l.b) ;01766c3cd2509abc + xor.b @er3-,@(0xffff9abc:16,r2.w) ;01766c3ce2509abc + xor.b @er3-,@(0xffff9abc:16,er2.l) ;01766c3cf2509abc + xor.b @er3-,@(0x9abcdef0:32,r2l.b) ;01766c3cda509abcdef0 + xor.b @er3-,@(0x9abcdef0:32,r2.w) ;01766c3cea509abcdef0 + xor.b @er3-,@(0x9abcdef0:32,er2.l) ;01766c3cfa509abcdef0 + xor.b @er3-,@0xffff9abc:16 ;01766c3c40509abc + xor.b @er3-,@0x9abcdef0:32 ;01766c3c48509abcdef0 + + xor.b @+er3,@er1 ;01756c3c0150 + xor.b @+er3,@(3:2,er1) ;01756c3c3150 + xor.b @+er3,@-er1 ;01756c3cb150 + xor.b @+er3,@er1+ ;01756c3c8150 + xor.b @+er3,@er1- ;01756c3ca150 + xor.b @+er3,@+er1 ;01756c3c9150 + xor.b @+er3,@(0xffff9abc:16,er1) ;01756c3cc1509abc + xor.b @+er3,@(0x9abcdef0:32,er1) ;01756c3cc9509abcdef0 + xor.b @+er3,@(0xffff9abc:16,r2l.b) ;01756c3cd2509abc + xor.b @+er3,@(0xffff9abc:16,r2.w) ;01756c3ce2509abc + xor.b @+er3,@(0xffff9abc:16,er2.l) ;01756c3cf2509abc + xor.b @+er3,@(0x9abcdef0:32,r2l.b) ;01756c3cda509abcdef0 + xor.b @+er3,@(0x9abcdef0:32,r2.w) ;01756c3cea509abcdef0 + xor.b @+er3,@(0x9abcdef0:32,er2.l) ;01756c3cfa509abcdef0 + xor.b @+er3,@0xffff9abc:16 ;01756c3c40509abc + xor.b @+er3,@0x9abcdef0:32 ;01756c3c48509abcdef0 + + xor.b @(0x1234:16,er3),@er1 ;01746e3c12340150 + xor.b @(0x1234:16,er3),@(3:2,er1) ;01746e3c12343150 + xor.b @(0x1234:16,er3),@-er1 ;01746e3c1234b150 + xor.b @(0x1234:16,er3),@er1+ ;01746e3c12348150 + xor.b @(0x1234:16,er3),@er1- ;01746e3c1234a150 + xor.b @(0x1234:16,er3),@+er1 ;01746e3c12349150 + xor.b @(0x1234:16,er3),@(0xffff9abc:16,er1) ;01746e3c1234c1509abc + xor.b @(0x1234:16,er3),@(0x9abcdef0:32,er1) ;01746e3c1234c9509abcdef0 + xor.b @(0x1234:16,er3),@(0xffff9abc:16,r2l.b) ;01746e3c1234d2509abc + xor.b @(0x1234:16,er3),@(0xffff9abc:16,r2.w) ;01746e3c1234e2509abc + xor.b @(0x1234:16,er3),@(0xffff9abc:16,er2.l) ;01746e3c1234f2509abc + xor.b @(0x1234:16,er3),@(0x9abcdef0:32,r2l.b) ;01746e3c1234da509abcdef0 + xor.b @(0x1234:16,er3),@(0x9abcdef0:32,r2.w) ;01746e3c1234ea509abcdef0 + xor.b @(0x1234:16,er3),@(0x9abcdef0:32,er2.l) ;01746e3c1234fa509abcdef0 + xor.b @(0x1234:16,er3),@0xffff9abc:16 ;01746e3c123440509abc + xor.b @(0x1234:16,er3),@0x9abcdef0:32 ;01746e3c123448509abcdef0 + + xor.b @(0x12345678:32,er3),@er1 ;78346a2c123456780150 + xor.b @(0x12345678:32,er3),@(3:2,er1) ;78346a2c123456783150 + xor.b @(0x12345678:32,er3),@-er1 ;78346a2c12345678b150 + xor.b @(0x12345678:32,er3),@er1+ ;78346a2c123456788150 + xor.b @(0x12345678:32,er3),@er1- ;78346a2c12345678a150 + xor.b @(0x12345678:32,er3),@+er1 ;78346a2c123456789150 + xor.b @(0x12345678:32,er3),@(0xffff9abc:16,er1) ;78346a2c12345678c1509abc + xor.b @(0x12345678:32,er3),@(0x9abcdef0:32,er1) ;78346a2c12345678c9509abcdef0 + xor.b @(0x12345678:32,er3),@(0xffff9abc:16,r2l.b) ;78346a2c12345678d2509abc + xor.b @(0x12345678:32,er3),@(0xffff9abc:16,r2.w) ;78346a2c12345678e2509abc + xor.b @(0x12345678:32,er3),@(0xffff9abc:16,er2.l) ;78346a2c12345678f2509abc + xor.b @(0x12345678:32,er3),@(0x9abcdef0:32,r2l.b) ;78346a2c12345678da509abcdef0 + xor.b @(0x12345678:32,er3),@(0x9abcdef0:32,r2.w) ;78346a2c12345678ea509abcdef0 + xor.b @(0x12345678:32,er3),@(0x9abcdef0:32,er2.l) ;78346a2c12345678fa509abcdef0 + xor.b @(0x12345678:32,er3),@0xffff9abc:16 ;78346a2c1234567840509abc + xor.b @(0x12345678:32,er3),@0x9abcdef0:32 ;78346a2c1234567848509abcdef0 + + xor.b @(0x1234:16,r3l.b),@er1 ;01756e3c12340150 + xor.b @(0x1234:16,r3l.b),@(3:2,er1) ;01756e3c12343150 + xor.b @(0x1234:16,r3l.b),@-er1 ;01756e3c1234b150 + xor.b @(0x1234:16,r3l.b),@er1+ ;01756e3c12348150 + xor.b @(0x1234:16,r3l.b),@er1- ;01756e3c1234a150 + xor.b @(0x1234:16,r3l.b),@+er1 ;01756e3c12349150 + xor.b @(0x1234:16,r3l.b),@(0xffff9abc:16,er1) ;01756e3c1234c1509abc + xor.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1) ;01756e3c1234c9509abcdef0 + xor.b @(0x1234:16,r3l.b),@(0xffff9abc:16,r2l.b) ;01756e3c1234d2509abc + xor.b @(0x1234:16,r3l.b),@(0xffff9abc:16,r2.w) ;01756e3c1234e2509abc + xor.b @(0x1234:16,r3l.b),@(0xffff9abc:16,er2.l) ;01756e3c1234f2509abc + xor.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2l.b) ;01756e3c1234da509abcdef0 + xor.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2.w) ;01756e3c1234ea509abcdef0 + xor.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,er2.l) ;01756e3c1234fa509abcdef0 + xor.b @(0x1234:16,r3l.b),@0xffff9abc:16 ;01756e3c123440509abc + xor.b @(0x1234:16,r3l.b),@0x9abcdef0:32 ;01756e3c123448509abcdef0 + + xor.b @(0x1234:16,r3.w),@er1 ;01766e3c12340150 + xor.b @(0x1234:16,r3.w),@(3:2,er1) ;01766e3c12343150 + xor.b @(0x1234:16,r3.w),@-er1 ;01766e3c1234b150 + xor.b @(0x1234:16,r3.w),@er1+ ;01766e3c12348150 + xor.b @(0x1234:16,r3.w),@er1- ;01766e3c1234a150 + xor.b @(0x1234:16,r3.w),@+er1 ;01766e3c12349150 + xor.b @(0x1234:16,r3.w),@(0xffff9abc:16,er1) ;01766e3c1234c1509abc + xor.b @(0x1234:16,r3.w),@(0x9abcdef0:32,er1) ;01766e3c1234c9509abcdef0 + xor.b @(0x1234:16,r3.w),@(0xffff9abc:16,r2l.b) ;01766e3c1234d2509abc + xor.b @(0x1234:16,r3.w),@(0xffff9abc:16,r2.w) ;01766e3c1234e2509abc + xor.b @(0x1234:16,r3.w),@(0xffff9abc:16,er2.l) ;01766e3c1234f2509abc + xor.b @(0x1234:16,r3.w),@(0x9abcdef0:32,r2l.b) ;01766e3c1234da509abcdef0 + xor.b @(0x1234:16,r3.w),@(0x9abcdef0:32,r2.w) ;01766e3c1234ea509abcdef0 + xor.b @(0x1234:16,r3.w),@(0x9abcdef0:32,er2.l) ;01766e3c1234fa509abcdef0 + xor.b @(0x1234:16,r3.w),@0xffff9abc:16 ;01766e3c123440509abc + xor.b @(0x1234:16,r3.w),@0x9abcdef0:32 ;01766e3c123448509abcdef0 + + xor.b @(0x1234:16,er3.l),@er1 ;01776e3c12340150 + xor.b @(0x1234:16,er3.l),@(3:2,er1) ;01776e3c12343150 + xor.b @(0x1234:16,er3.l),@-er1 ;01776e3c1234b150 + xor.b @(0x1234:16,er3.l),@er1+ ;01776e3c12348150 + xor.b @(0x1234:16,er3.l),@er1- ;01776e3c1234a150 + xor.b @(0x1234:16,er3.l),@+er1 ;01776e3c12349150 + xor.b @(0x1234:16,er3.l),@(0xffff9abc:16,er1) ;01776e3c1234c1509abc + xor.b @(0x1234:16,er3.l),@(0x9abcdef0:32,er1) ;01776e3c1234c9509abcdef0 + xor.b @(0x1234:16,er3.l),@(0xffff9abc:16,r2l.b) ;01776e3c1234d2509abc + xor.b @(0x1234:16,er3.l),@(0xffff9abc:16,r2.w) ;01776e3c1234e2509abc + xor.b @(0x1234:16,er3.l),@(0xffff9abc:16,er2.l) ;01776e3c1234f2509abc + xor.b @(0x1234:16,er3.l),@(0x9abcdef0:32,r2l.b) ;01776e3c1234da509abcdef0 + xor.b @(0x1234:16,er3.l),@(0x9abcdef0:32,r2.w) ;01776e3c1234ea509abcdef0 + xor.b @(0x1234:16,er3.l),@(0x9abcdef0:32,er2.l) ;01776e3c1234fa509abcdef0 + xor.b @(0x1234:16,er3.l),@0xffff9abc:16 ;01776e3c123440509abc + xor.b @(0x1234:16,er3.l),@0x9abcdef0:32 ;01776e3c123448509abcdef0 + + xor.b @(0x12345678:32,r3l.b),@er1 ;78356a2c123456780150 + xor.b @(0x12345678:32,r3l.b),@(3:2,er1) ;78356a2c123456783150 + xor.b @(0x12345678:32,r3l.b),@-er1 ;78356a2c12345678b150 + xor.b @(0x12345678:32,r3l.b),@er1+ ;78356a2c123456788150 + xor.b @(0x12345678:32,r3l.b),@er1- ;78356a2c12345678a150 + xor.b @(0x12345678:32,r3l.b),@+er1 ;78356a2c123456789150 + xor.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,er1) ;78356a2c12345678c1509abc + xor.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1) ;78356a2c12345678c9509abcdef0 + xor.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2l.b) ;78356a2c12345678d2509abc + xor.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2.w) ;78356a2c12345678e2509abc + xor.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,er2.l) ;78356a2c12345678f2509abc + xor.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2l.b) ;78356a2c12345678da509abcdef0 + xor.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2.w) ;78356a2c12345678ea509abcdef0 + xor.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er2.l) ;78356a2c12345678fa509abcdef0 + xor.b @(0x12345678:32,r3l.b),@0xffff9abc:16 ;78356a2c1234567840509abc + xor.b @(0x12345678:32,r3l.b),@0x9abcdef0:32 ;78356a2c1234567848509abcdef0 + + xor.b @(0x12345678:32,r3.w),@er1 ;78366a2c123456780150 + xor.b @(0x12345678:32,r3.w),@(3:2,er1) ;78366a2c123456783150 + xor.b @(0x12345678:32,r3.w),@-er1 ;78366a2c12345678b150 + xor.b @(0x12345678:32,r3.w),@er1+ ;78366a2c123456788150 + xor.b @(0x12345678:32,r3.w),@er1- ;78366a2c12345678a150 + xor.b @(0x12345678:32,r3.w),@+er1 ;78366a2c123456789150 + xor.b @(0x12345678:32,r3.w),@(0xffff9abc:16,er1) ;78366a2c12345678c1509abc + xor.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1) ;78366a2c12345678c9509abcdef0 + xor.b @(0x12345678:32,r3.w),@(0xffff9abc:16,r2l.b) ;78366a2c12345678d2509abc + xor.b @(0x12345678:32,r3.w),@(0xffff9abc:16,r2.w) ;78366a2c12345678e2509abc + xor.b @(0x12345678:32,r3.w),@(0xffff9abc:16,er2.l) ;78366a2c12345678f2509abc + xor.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2l.b) ;78366a2c12345678da509abcdef0 + xor.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2.w) ;78366a2c12345678ea509abcdef0 + xor.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,er2.l) ;78366a2c12345678fa509abcdef0 + xor.b @(0x12345678:32,r3.w),@0xffff9abc:16 ;78366a2c1234567840509abc + xor.b @(0x12345678:32,r3.w),@0x9abcdef0:32 ;78366a2c1234567848509abcdef0 + + xor.b @(0x12345678:32,er3.l),@er1 ;78376a2c123456780150 + xor.b @(0x12345678:32,er3.l),@(3:2,er1) ;78376a2c123456783150 + xor.b @(0x12345678:32,er3.l),@-er1 ;78376a2c12345678b150 + xor.b @(0x12345678:32,er3.l),@er1+ ;78376a2c123456788150 + xor.b @(0x12345678:32,er3.l),@er1- ;78376a2c12345678a150 + xor.b @(0x12345678:32,er3.l),@+er1 ;78376a2c123456789150 + xor.b @(0x12345678:32,er3.l),@(0xffff9abc:16,er1) ;78376a2c12345678c1509abc + xor.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1) ;78376a2c12345678c9509abcdef0 + xor.b @(0x12345678:32,er3.l),@(0xffff9abc:16,r2l.b) ;78376a2c12345678d2509abc + xor.b @(0x12345678:32,er3.l),@(0xffff9abc:16,r2.w) ;78376a2c12345678e2509abc + xor.b @(0x12345678:32,er3.l),@(0xffff9abc:16,er2.l) ;78376a2c12345678f2509abc + xor.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2l.b) ;78376a2c12345678da509abcdef0 + xor.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2.w) ;78376a2c12345678ea509abcdef0 + xor.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,er2.l) ;78376a2c12345678fa509abcdef0 + xor.b @(0x12345678:32,er3.l),@0xffff9abc:16 ;78376a2c1234567840509abc + xor.b @(0x12345678:32,er3.l),@0x9abcdef0:32 ;78376a2c1234567848509abcdef0 + + xor.b @0x1234:16,@er1 ;6a1512340150 + xor.b @0x1234:16,@(3:2,er1) ;6a1512343150 + xor.b @0x1234:16,@-er1 ;6a151234b150 + xor.b @0x1234:16,@er1+ ;6a1512348150 + xor.b @0x1234:16,@er1- ;6a151234a150 + xor.b @0x1234:16,@+er1 ;6a1512349150 + xor.b @0x1234:16,@(0xffff9abc:16,er1) ;6a151234c1509abc + xor.b @0x1234:16,@(0x9abcdef0:32,er1) ;6a151234c9509abcdef0 + xor.b @0x1234:16,@(0xffff9abc:16,r2l.b) ;6a151234d2509abc + xor.b @0x1234:16,@(0xffff9abc:16,r2.w) ;6a151234e2509abc + xor.b @0x1234:16,@(0xffff9abc:16,er2.l) ;6a151234f2509abc + xor.b @0x1234:16,@(0x9abcdef0:32,r2l.b) ;6a151234da509abcdef0 + xor.b @0x1234:16,@(0x9abcdef0:32,r2.w) ;6a151234ea509abcdef0 + xor.b @0x1234:16,@(0x9abcdef0:32,er2.l) ;6a151234fa509abcdef0 + xor.b @0x1234:16,@0xffff9abc:16 ;6a15123440509abc + xor.b @0x1234:16,@0x9abcdef0:32 ;6a15123448509abcdef0 + + xor.b @0x12345678:32,@er1 ;6a35123456780150 + xor.b @0x12345678:32,@(3:2,er1) ;6a35123456783150 + xor.b @0x12345678:32,@-er1 ;6a3512345678b150 + xor.b @0x12345678:32,@er1+ ;6a35123456788150 + xor.b @0x12345678:32,@er1- ;6a3512345678a150 + xor.b @0x12345678:32,@+er1 ;6a35123456789150 + xor.b @0x12345678:32,@(0xffff9abc:16,er1) ;6a3512345678c1509abc + xor.b @0x12345678:32,@(0x9abcdef0:32,er1) ;6a3512345678c9509abcdef0 + xor.b @0x12345678:32,@(0xffff9abc:16,r2l.b) ;6a3512345678d2509abc + xor.b @0x12345678:32,@(0xffff9abc:16,r2.w) ;6a3512345678e2509abc + xor.b @0x12345678:32,@(0xffff9abc:16,er2.l) ;6a3512345678f2509abc + xor.b @0x12345678:32,@(0x9abcdef0:32,r2l.b) ;6a3512345678da509abcdef0 + xor.b @0x12345678:32,@(0x9abcdef0:32,r2.w) ;6a3512345678ea509abcdef0 + xor.b @0x12345678:32,@(0x9abcdef0:32,er2.l) ;6a3512345678fa509abcdef0 + xor.b @0x12345678:32,@0xffff9abc:16 ;6a351234567840509abc + xor.b @0x12345678:32,@0x9abcdef0:32 ;6a351234567848509abcdef0 + + xor.w #0x1234:16,r1 ;79511234 + xor.w #0x1234:16,@er1 ;015e01501234 + xor.w #0x1234:16,@(0x6:2,er1) ;015e31501234 + xor.w #0x1234:16,@er1+ ;015e81501234 + xor.w #0x1234:16,@-er1 ;015eb1501234 + xor.w #0x1234:16,@+er1 ;015e91501234 + xor.w #0x1234:16,@er1- ;015ea1501234 + xor.w #0x1234:16,@(0xffff9abc:16,er1) ;015ec1509abc1234 + xor.w #0x1234:16,@(0x9abcdef0:32,er1) ;015ec9509abcdef01234 + xor.w #0x1234:16,@(0xffff9abc:16,r2l.b) ;015ed2509abc1234 + xor.w #0x1234:16,@(0xffff9abc:16,r2.w) ;015ee2509abc1234 + xor.w #0x1234:16,@(0xffff9abc:16,er2.l) ;015ef2509abc1234 + xor.w #0x1234:16,@(0x9abcdef0:32,r2l.b) ;015eda509abcdef01234 + xor.w #0x1234:16,@(0x9abcdef0:32,r2.w) ;015eea509abcdef01234 + xor.w #0x1234:16,@(0x9abcdef0:32,er2.l) ;015efa509abcdef01234 + xor.w #0x1234:16,@0xffff9abc:16 ;015e40509abc1234 + xor.w #0x1234:16,@0x9abcdef0:32 ;015e48509abcdef01234 + + xor.w r3,r1 ;6531 + + xor.w r3,@er1 ;7d906530 + xor.w r3,@(0x6:2,er1) ;01593153 + xor.w r3,@-er1 ;0159b153 + xor.w r3,@er1+ ;01598153 + xor.w r3,@er1- ;0159a153 + xor.w r3,@+er1 ;01599153 + xor.w r3,@(0x1234:16,er1) ;0159c1531234 + xor.w r3,@(0x12345678:32,er1) ;0159c95312345678 + xor.w r3,@(0x1234:16,r2l.b) ;0159d2531234 + xor.w r3,@(0x1234:16,r2.w) ;0159e2531234 + xor.w r3,@(0x1234:16,er2.l) ;0159f2531234 + xor.w r3,@(0x12345678:32,r2l.b) ;0159da5312345678 + xor.w r3,@(0x12345678:32,r2.w) ;0159ea5312345678 + xor.w r3,@(0x12345678:32,er2.l) ;0159fa5312345678 + xor.w r3,@0x1234:16 ;6b1812346530 + xor.w r3,@0x12345678:32 ;6b38123456786530 + + xor.w @er3,r1 ;7cb06501 + xor.w @(0x6:2,er3),r1 ;015a3351 + xor.w @er3+,r1 ;015a8351 + xor.w @-er3,r1 ;015ab351 + xor.w @+er3,r1 ;015a9351 + xor.w @er3-,r1 ;015aa351 + xor.w @(0x1234:16,er1),r1 ;015ac1511234 + xor.w @(0x12345678:32,er1),r1 ;015ac95112345678 + xor.w @(0x1234:16,r2l.b),r1 ;015ad2511234 + xor.w @(0x1234:16,r2.w),r1 ;015ae2511234 + xor.w @(0x1234:16,er2.l),r1 ;015af2511234 + xor.w @(0x12345678:32,r2l.b),r1 ;015ada5112345678 + xor.w @(0x12345678:32,r2.w),r1 ;015aea5112345678 + xor.w @(0x12345678:32,er2.l),r1 ;015afa5112345678 + xor.w @0x1234:16,r1 ;6b1012346501 + xor.w @0x12345678:32,r1 ;6b30123456786501 + + xor.w @er3,@er1 ;7cb50150 + xor.w @er3,@(6:2,er1) ;7cb53150 + xor.w @er3,@-er1 ;7cb5b150 + xor.w @er3,@er1+ ;7cb58150 + xor.w @er3,@er1- ;7cb5a150 + xor.w @er3,@+er1 ;7cb59150 + xor.w @er3,@(0xffff9abc:16,er1) ;7cb5c1509abc + xor.w @er3,@(0x9abcdef0:32,er1) ;7cb5c9509abcdef0 + xor.w @er3,@(0xffff9abc:16,r2l.b) ;7cb5d2509abc + xor.w @er3,@(0xffff9abc:16,r2.w) ;7cb5e2509abc + xor.w @er3,@(0xffff9abc:16,er2.l) ;7cb5f2509abc + xor.w @er3,@(0x9abcdef0:32,r2l.b) ;7cb5da509abcdef0 + xor.w @er3,@(0x9abcdef0:32,r2.w) ;7cb5ea509abcdef0 + xor.w @er3,@(0x9abcdef0:32,er2.l) ;7cb5fa509abcdef0 + xor.w @er3,@0xffff9abc:16 ;7cb540509abc + xor.w @er3,@0x9abcdef0:32 ;7cb548509abcdef0 + + xor.w @-er3,@er1 ;01576d3c0150 + xor.w @-er3,@(6:2,er1) ;01576d3c3150 + xor.w @-er3,@-er1 ;01576d3cb150 + xor.w @-er3,@er1+ ;01576d3c8150 + xor.w @-er3,@er1- ;01576d3ca150 + xor.w @-er3,@+er1 ;01576d3c9150 + xor.w @-er3,@(0xffff9abc:16,er1) ;01576d3cc1509abc + xor.w @-er3,@(0x9abcdef0:32,er1) ;01576d3cc9509abcdef0 + xor.w @-er3,@(0xffff9abc:16,r2l.b) ;01576d3cd2509abc + xor.w @-er3,@(0xffff9abc:16,r2.w) ;01576d3ce2509abc + xor.w @-er3,@(0xffff9abc:16,er2.l) ;01576d3cf2509abc + xor.w @-er3,@(0x9abcdef0:32,r2l.b) ;01576d3cda509abcdef0 + xor.w @-er3,@(0x9abcdef0:32,r2.w) ;01576d3cea509abcdef0 + xor.w @-er3,@(0x9abcdef0:32,er2.l) ;01576d3cfa509abcdef0 + xor.w @-er3,@0xffff9abc:16 ;01576d3c40509abc + xor.w @-er3,@0x9abcdef0:32 ;01576d3c48509abcdef0 + + xor.w @er3+,@er1 ;01546d3c0150 + xor.w @er3+,@(6:2,er1) ;01546d3c3150 + xor.w @er3+,@-er1 ;01546d3cb150 + xor.w @er3+,@er1+ ;01546d3c8150 + xor.w @er3+,@er1- ;01546d3ca150 + xor.w @er3+,@+er1 ;01546d3c9150 + xor.w @er3+,@(0xffff9abc:16,er1) ;01546d3cc1509abc + xor.w @er3+,@(0x9abcdef0:32,er1) ;01546d3cc9509abcdef0 + xor.w @er3+,@(0xffff9abc:16,r2l.b) ;01546d3cd2509abc + xor.w @er3+,@(0xffff9abc:16,r2.w) ;01546d3ce2509abc + xor.w @er3+,@(0xffff9abc:16,er2.l) ;01546d3cf2509abc + xor.w @er3+,@(0x9abcdef0:32,r2l.b) ;01546d3cda509abcdef0 + xor.w @er3+,@(0x9abcdef0:32,r2.w) ;01546d3cea509abcdef0 + xor.w @er3+,@(0x9abcdef0:32,er2.l) ;01546d3cfa509abcdef0 + xor.w @er3+,@0xffff9abc:16 ;01546d3c40509abc + xor.w @er3+,@0x9abcdef0:32 ;01546d3c48509abcdef0 + + xor.w @er3-,@er1 ;01566d3c0150 + xor.w @er3-,@(6:2,er1) ;01566d3c3150 + xor.w @er3-,@-er1 ;01566d3cb150 + xor.w @er3-,@er1+ ;01566d3c8150 + xor.w @er3-,@er1- ;01566d3ca150 + xor.w @er3-,@+er1 ;01566d3c9150 + xor.w @er3-,@(0xffff9abc:16,er1) ;01566d3cc1509abc + xor.w @er3-,@(0x9abcdef0:32,er1) ;01566d3cc9509abcdef0 + xor.w @er3-,@(0xffff9abc:16,r2l.b) ;01566d3cd2509abc + xor.w @er3-,@(0xffff9abc:16,r2.w) ;01566d3ce2509abc + xor.w @er3-,@(0xffff9abc:16,er2.l) ;01566d3cf2509abc + xor.w @er3-,@(0x9abcdef0:32,r2l.b) ;01566d3cda509abcdef0 + xor.w @er3-,@(0x9abcdef0:32,r2.w) ;01566d3cea509abcdef0 + xor.w @er3-,@(0x9abcdef0:32,er2.l) ;01566d3cfa509abcdef0 + xor.w @er3-,@0xffff9abc:16 ;01566d3c40509abc + xor.w @er3-,@0x9abcdef0:32 ;01566d3c48509abcdef0 + + xor.w @+er3,@er1 ;01556d3c0150 + xor.w @+er3,@(6:2,er1) ;01556d3c3150 + xor.w @+er3,@-er1 ;01556d3cb150 + xor.w @+er3,@er1+ ;01556d3c8150 + xor.w @+er3,@er1- ;01556d3ca150 + xor.w @+er3,@+er1 ;01556d3c9150 + xor.w @+er3,@(0xffff9abc:16,er1) ;01556d3cc1509abc + xor.w @+er3,@(0x9abcdef0:32,er1) ;01556d3cc9509abcdef0 + xor.w @+er3,@(0xffff9abc:16,r2l.b) ;01556d3cd2509abc + xor.w @+er3,@(0xffff9abc:16,r2.w) ;01556d3ce2509abc + xor.w @+er3,@(0xffff9abc:16,er2.l) ;01556d3cf2509abc + xor.w @+er3,@(0x9abcdef0:32,r2l.b) ;01556d3cda509abcdef0 + xor.w @+er3,@(0x9abcdef0:32,r2.w) ;01556d3cea509abcdef0 + xor.w @+er3,@(0x9abcdef0:32,er2.l) ;01556d3cfa509abcdef0 + xor.w @+er3,@0xffff9abc:16 ;01556d3c40509abc + xor.w @+er3,@0x9abcdef0:32 ;01556d3c48509abcdef0 + + xor.w @(0x1234:16,er3),@er1 ;01546f3c12340150 + xor.w @(0x1234:16,er3),@(6:2,er1) ;01546f3c12343150 + xor.w @(0x1234:16,er3),@-er1 ;01546f3c1234b150 + xor.w @(0x1234:16,er3),@er1+ ;01546f3c12348150 + xor.w @(0x1234:16,er3),@er1- ;01546f3c1234a150 + xor.w @(0x1234:16,er3),@+er1 ;01546f3c12349150 + xor.w @(0x1234:16,er3),@(0xffff9abc:16,er1) ;01546f3c1234c1509abc + xor.w @(0x1234:16,er3),@(0x9abcdef0:32,er1) ;01546f3c1234c9509abcdef0 + xor.w @(0x1234:16,er3),@(0xffff9abc:16,r2l.b) ;01546f3c1234d2509abc + xor.w @(0x1234:16,er3),@(0xffff9abc:16,r2.w) ;01546f3c1234e2509abc + xor.w @(0x1234:16,er3),@(0xffff9abc:16,er2.l) ;01546f3c1234f2509abc + xor.w @(0x1234:16,er3),@(0x9abcdef0:32,r2l.b) ;01546f3c1234da509abcdef0 + xor.w @(0x1234:16,er3),@(0x9abcdef0:32,r2.w) ;01546f3c1234ea509abcdef0 + xor.w @(0x1234:16,er3),@(0x9abcdef0:32,er2.l) ;01546f3c1234fa509abcdef0 + xor.w @(0x1234:16,er3),@0xffff9abc:16 ;01546f3c123440509abc + xor.w @(0x1234:16,er3),@0x9abcdef0:32 ;01546f3c123448509abcdef0 + + xor.w @(0x12345678:32,er3),@er1 ;78346b2c123456780150 + xor.w @(0x12345678:32,er3),@(6:2,er1) ;78346b2c123456783150 + xor.w @(0x12345678:32,er3),@-er1 ;78346b2c12345678b150 + xor.w @(0x12345678:32,er3),@er1+ ;78346b2c123456788150 + xor.w @(0x12345678:32,er3),@er1- ;78346b2c12345678a150 + xor.w @(0x12345678:32,er3),@+er1 ;78346b2c123456789150 + xor.w @(0x12345678:32,er3),@(0xffff9abc:16,er1) ;78346b2c12345678c1509abc + xor.w @(0x12345678:32,er3),@(0x9abcdef0:32,er1) ;78346b2c12345678c9509abcdef0 + xor.w @(0x12345678:32,er3),@(0xffff9abc:16,r2l.b) ;78346b2c12345678d2509abc + xor.w @(0x12345678:32,er3),@(0xffff9abc:16,r2.w) ;78346b2c12345678e2509abc + xor.w @(0x12345678:32,er3),@(0xffff9abc:16,er2.l) ;78346b2c12345678f2509abc + xor.w @(0x12345678:32,er3),@(0x9abcdef0:32,r2l.b) ;78346b2c12345678da509abcdef0 + xor.w @(0x12345678:32,er3),@(0x9abcdef0:32,r2.w) ;78346b2c12345678ea509abcdef0 + xor.w @(0x12345678:32,er3),@(0x9abcdef0:32,er2.l) ;78346b2c12345678fa509abcdef0 + xor.w @(0x12345678:32,er3),@0xffff9abc:16 ;78346b2c1234567840509abc + xor.w @(0x12345678:32,er3),@0x9abcdef0:32 ;78346b2c1234567848509abcdef0 + + xor.w @(0x1234:16,r3l.b),@er1 ;01556f3c12340150 + xor.w @(0x1234:16,r3l.b),@(6:2,er1) ;01556f3c12343150 + xor.w @(0x1234:16,r3l.b),@-er1 ;01556f3c1234b150 + xor.w @(0x1234:16,r3l.b),@er1+ ;01556f3c12348150 + xor.w @(0x1234:16,r3l.b),@er1- ;01556f3c1234a150 + xor.w @(0x1234:16,r3l.b),@+er1 ;01556f3c12349150 + xor.w @(0x1234:16,r3l.b),@(0xffff9abc:16,er1) ;01556f3c1234c1509abc + xor.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1) ;01556f3c1234c9509abcdef0 + xor.w @(0x1234:16,r3l.b),@(0xffff9abc:16,r2l.b) ;01556f3c1234d2509abc + xor.w @(0x1234:16,r3l.b),@(0xffff9abc:16,r2.w) ;01556f3c1234e2509abc + xor.w @(0x1234:16,r3l.b),@(0xffff9abc:16,er2.l) ;01556f3c1234f2509abc + xor.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2l.b) ;01556f3c1234da509abcdef0 + xor.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2.w) ;01556f3c1234ea509abcdef0 + xor.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,er2.l) ;01556f3c1234fa509abcdef0 + xor.w @(0x1234:16,r3l.b),@0xffff9abc:16 ;01556f3c123440509abc + xor.w @(0x1234:16,r3l.b),@0x9abcdef0:32 ;01556f3c123448509abcdef0 + + xor.w @(0x1234:16,r3.w),@er1 ;01566f3c12340150 + xor.w @(0x1234:16,r3.w),@(6:2,er1) ;01566f3c12343150 + xor.w @(0x1234:16,r3.w),@-er1 ;01566f3c1234b150 + xor.w @(0x1234:16,r3.w),@er1+ ;01566f3c12348150 + xor.w @(0x1234:16,r3.w),@er1- ;01566f3c1234a150 + xor.w @(0x1234:16,r3.w),@+er1 ;01566f3c12349150 + xor.w @(0x1234:16,r3.w),@(0xffff9abc:16,er1) ;01566f3c1234c1509abc + xor.w @(0x1234:16,r3.w),@(0x9abcdef0:32,er1) ;01566f3c1234c9509abcdef0 + xor.w @(0x1234:16,r3.w),@(0xffff9abc:16,r2l.b) ;01566f3c1234d2509abc + xor.w @(0x1234:16,r3.w),@(0xffff9abc:16,r2.w) ;01566f3c1234e2509abc + xor.w @(0x1234:16,r3.w),@(0xffff9abc:16,er2.l) ;01566f3c1234f2509abc + xor.w @(0x1234:16,r3.w),@(0x9abcdef0:32,r2l.b) ;01566f3c1234da509abcdef0 + xor.w @(0x1234:16,r3.w),@(0x9abcdef0:32,r2.w) ;01566f3c1234ea509abcdef0 + xor.w @(0x1234:16,r3.w),@(0x9abcdef0:32,er2.l) ;01566f3c1234fa509abcdef0 + xor.w @(0x1234:16,r3.w),@0xffff9abc:16 ;01566f3c123440509abc + xor.w @(0x1234:16,r3.w),@0x9abcdef0:32 ;01566f3c123448509abcdef0 + + xor.w @(0x1234:16,er3.l),@er1 ;01576f3c12340150 + xor.w @(0x1234:16,er3.l),@(6:2,er1) ;01576f3c12343150 + xor.w @(0x1234:16,er3.l),@-er1 ;01576f3c1234b150 + xor.w @(0x1234:16,er3.l),@er1+ ;01576f3c12348150 + xor.w @(0x1234:16,er3.l),@er1- ;01576f3c1234a150 + xor.w @(0x1234:16,er3.l),@+er1 ;01576f3c12349150 + xor.w @(0x1234:16,er3.l),@(0xffff9abc:16,er1) ;01576f3c1234c1509abc + xor.w @(0x1234:16,er3.l),@(0x9abcdef0:32,er1) ;01576f3c1234c9509abcdef0 + xor.w @(0x1234:16,er3.l),@(0xffff9abc:16,r2l.b) ;01576f3c1234d2509abc + xor.w @(0x1234:16,er3.l),@(0xffff9abc:16,r2.w) ;01576f3c1234e2509abc + xor.w @(0x1234:16,er3.l),@(0xffff9abc:16,er2.l) ;01576f3c1234f2509abc + xor.w @(0x1234:16,er3.l),@(0x9abcdef0:32,r2l.b) ;01576f3c1234da509abcdef0 + xor.w @(0x1234:16,er3.l),@(0x9abcdef0:32,r2.w) ;01576f3c1234ea509abcdef0 + xor.w @(0x1234:16,er3.l),@(0x9abcdef0:32,er2.l) ;01576f3c1234fa509abcdef0 + xor.w @(0x1234:16,er3.l),@0xffff9abc:16 ;01576f3c123440509abc + xor.w @(0x1234:16,er3.l),@0x9abcdef0:32 ;01576f3c123448509abcdef0 + + xor.w @(0x12345678:32,r3l.b),@er1 ;78356b2c123456780150 + xor.w @(0x12345678:32,r3l.b),@(6:2,er1) ;78356b2c123456783150 + xor.w @(0x12345678:32,r3l.b),@-er1 ;78356b2c12345678b150 + xor.w @(0x12345678:32,r3l.b),@er1+ ;78356b2c123456788150 + xor.w @(0x12345678:32,r3l.b),@er1- ;78356b2c12345678a150 + xor.w @(0x12345678:32,r3l.b),@+er1 ;78356b2c123456789150 + xor.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,er1) ;78356b2c12345678c1509abc + xor.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1) ;78356b2c12345678c9509abcdef0 + xor.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2l.b) ;78356b2c12345678d2509abc + xor.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2.w) ;78356b2c12345678e2509abc + xor.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,er2.l) ;78356b2c12345678f2509abc + xor.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2l.b) ;78356b2c12345678da509abcdef0 + xor.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2.w) ;78356b2c12345678ea509abcdef0 + xor.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er2.l) ;78356b2c12345678fa509abcdef0 + xor.w @(0x12345678:32,r3l.b),@0xffff9abc:16 ;78356b2c1234567840509abc + xor.w @(0x12345678:32,r3l.b),@0x9abcdef0:32 ;78356b2c1234567848509abcdef0 + + xor.w @(0x12345678:32,r3.w),@er1 ;78366b2c123456780150 + xor.w @(0x12345678:32,r3.w),@(6:2,er1) ;78366b2c123456783150 + xor.w @(0x12345678:32,r3.w),@-er1 ;78366b2c12345678b150 + xor.w @(0x12345678:32,r3.w),@er1+ ;78366b2c123456788150 + xor.w @(0x12345678:32,r3.w),@er1- ;78366b2c12345678a150 + xor.w @(0x12345678:32,r3.w),@+er1 ;78366b2c123456789150 + xor.w @(0x12345678:32,r3.w),@(0xffff9abc:16,er1) ;78366b2c12345678c1509abc + xor.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1) ;78366b2c12345678c9509abcdef0 + xor.w @(0x12345678:32,r3.w),@(0xffff9abc:16,r2l.b) ;78366b2c12345678d2509abc + xor.w @(0x12345678:32,r3.w),@(0xffff9abc:16,r2.w) ;78366b2c12345678e2509abc + xor.w @(0x12345678:32,r3.w),@(0xffff9abc:16,er2.l) ;78366b2c12345678f2509abc + xor.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2l.b) ;78366b2c12345678da509abcdef0 + xor.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2.w) ;78366b2c12345678ea509abcdef0 + xor.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,er2.l) ;78366b2c12345678fa509abcdef0 + xor.w @(0x12345678:32,r3.w),@0xffff9abc:16 ;78366b2c1234567840509abc + xor.w @(0x12345678:32,r3.w),@0x9abcdef0:32 ;78366b2c1234567848509abcdef0 + + xor.w @(0x12345678:32,er3.l),@er1 ;78376b2c123456780150 + xor.w @(0x12345678:32,er3.l),@(6:2,er1) ;78376b2c123456783150 + xor.w @(0x12345678:32,er3.l),@-er1 ;78376b2c12345678b150 + xor.w @(0x12345678:32,er3.l),@er1+ ;78376b2c123456788150 + xor.w @(0x12345678:32,er3.l),@er1- ;78376b2c12345678a150 + xor.w @(0x12345678:32,er3.l),@+er1 ;78376b2c123456789150 + xor.w @(0x12345678:32,er3.l),@(0xffff9abc:16,er1) ;78376b2c12345678c1509abc + xor.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1) ;78376b2c12345678c9509abcdef0 + xor.w @(0x12345678:32,er3.l),@(0xffff9abc:16,r2l.b) ;78376b2c12345678d2509abc + xor.w @(0x12345678:32,er3.l),@(0xffff9abc:16,r2.w) ;78376b2c12345678e2509abc + xor.w @(0x12345678:32,er3.l),@(0xffff9abc:16,er2.l) ;78376b2c12345678f2509abc + xor.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2l.b) ;78376b2c12345678da509abcdef0 + xor.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2.w) ;78376b2c12345678ea509abcdef0 + xor.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,er2.l) ;78376b2c12345678fa509abcdef0 + xor.w @(0x12345678:32,er3.l),@0xffff9abc:16 ;78376b2c1234567840509abc + xor.w @(0x12345678:32,er3.l),@0x9abcdef0:32 ;78376b2c1234567848509abcdef0 + + xor.w @0x1234:16,@er1 ;6b1512340150 + xor.w @0x1234:16,@(6:2,er1) ;6b1512343150 + xor.w @0x1234:16,@-er1 ;6b151234b150 + xor.w @0x1234:16,@er1+ ;6b1512348150 + xor.w @0x1234:16,@er1- ;6b151234a150 + xor.w @0x1234:16,@+er1 ;6b1512349150 + xor.w @0x1234:16,@(0xffff9abc:16,er1) ;6b151234c1509abc + xor.w @0x1234:16,@(0x9abcdef0:32,er1) ;6b151234c9509abcdef0 + xor.w @0x1234:16,@(0xffff9abc:16,r2l.b) ;6b151234d2509abc + xor.w @0x1234:16,@(0xffff9abc:16,r2.w) ;6b151234e2509abc + xor.w @0x1234:16,@(0xffff9abc:16,er2.l) ;6b151234f2509abc + xor.w @0x1234:16,@(0x9abcdef0:32,r2l.b) ;6b151234da509abcdef0 + xor.w @0x1234:16,@(0x9abcdef0:32,r2.w) ;6b151234ea509abcdef0 + xor.w @0x1234:16,@(0x9abcdef0:32,er2.l) ;6b151234fa509abcdef0 + xor.w @0x1234:16,@0xffff9abc:16 ;6b15123440509abc + xor.w @0x1234:16,@0x9abcdef0:32 ;6b15123448509abcdef0 + + xor.w @0x12345678:32,@er1 ;6b35123456780150 + xor.w @0x12345678:32,@(6:2,er1) ;6b35123456783150 + xor.w @0x12345678:32,@-er1 ;6b3512345678b150 + xor.w @0x12345678:32,@er1+ ;6b35123456788150 + xor.w @0x12345678:32,@er1- ;6b3512345678a150 + xor.w @0x12345678:32,@+er1 ;6b35123456789150 + xor.w @0x12345678:32,@(0xffff9abc:16,er1) ;6b3512345678c1509abc + xor.w @0x12345678:32,@(0x9abcdef0:32,er1) ;6b3512345678c9509abcdef0 + xor.w @0x12345678:32,@(0xffff9abc:16,r2l.b) ;6b3512345678d2509abc + xor.w @0x12345678:32,@(0xffff9abc:16,r2.w) ;6b3512345678e2509abc + xor.w @0x12345678:32,@(0xffff9abc:16,er2.l) ;6b3512345678f2509abc + xor.w @0x12345678:32,@(0x9abcdef0:32,r2l.b) ;6b3512345678da509abcdef0 + xor.w @0x12345678:32,@(0x9abcdef0:32,r2.w) ;6b3512345678ea509abcdef0 + xor.w @0x12345678:32,@(0x9abcdef0:32,er2.l) ;6b3512345678fa509abcdef0 + xor.w @0x12345678:32,@0xffff9abc:16 ;6b351234567840509abc + xor.w @0x12345678:32,@0x9abcdef0:32 ;6b351234567848509abcdef0 + + xor.l #0x12345678:32,er1 ;7a5112345678 + xor.l #0x1234:16,er1 ;7a591234 + xor.l #0x12345678:32,@er1 ;010e015812345678 + xor.l #0x12345678:32,@(0xc:2,er1) ;010e315812345678 + xor.l #0x12345678:32,@er1+ ;010e815812345678 + xor.l #0x12345678:32,@-er1 ;010eb15812345678 + xor.l #0x12345678:32,@+er1 ;010e915812345678 + xor.l #0x12345678:32,@er1- ;010ea15812345678 + xor.l #0x12345678:32,@(0xffff9abc:16,er1) ;010ec1589abc12345678 + xor.l #0x12345678:32,@(0x9abcdef0:32,er1) ;010ec9589abcdef012345678 + xor.l #0x12345678:32,@(0xffff9abc:16,r2l.b) ;010ed2589abc12345678 + xor.l #0x12345678:32,@(0xffff9abc:16,r2.w) ;010ee2589abc12345678 + xor.l #0x12345678:32,@(0xffff9abc:16,er2.l) ;010ef2589abc12345678 + xor.l #0x12345678:32,@(0x9abcdef0:32,r2l.b) ;010eda589abcdef012345678 + xor.l #0x12345678:32,@(0x9abcdef0:32,r2.w) ;010eea589abcdef012345678 + xor.l #0x12345678:32,@(0x9abcdef0:32,er2.l) ;010efa589abcdef012345678 + xor.l #0x12345678:32,@0xffff9abc:16 ;010e40589abc12345678 + xor.l #0x12345678:32,@0x9abcdef0:32 ;010e48589abcdef012345678 + xor.l #0x1234:16,@er1 ;010e01501234 + xor.l #0x1234:16,@(0xc:2,er1) ;010e31501234 + xor.l #0x1234:16,@er1+ ;010e81501234 + xor.l #0x1234:16,@-er1 ;010eb1501234 + xor.l #0x1234:16,@+er1 ;010e91501234 + xor.l #0x1234:16,@er1- ;010ea1501234 + xor.l #0x1234:16,@(0xffff9abc:16,er1) ;010ec1509abc1234 + xor.l #0x1234:16,@(0x9abcdef0:32,er1) ;010ec9509abcdef01234 + xor.l #0x1234:16,@(0xffff9abc:16,r2l.b) ;010ed2509abc1234 + xor.l #0x1234:16,@(0xffff9abc:16,r2.w) ;010ee2509abc1234 + xor.l #0x1234:16,@(0xffff9abc:16,er2.l) ;010ef2509abc1234 + xor.l #0x1234:16,@(0x9abcdef0:32,r2l.b) ;010eda509abcdef01234 + xor.l #0x1234:16,@(0x9abcdef0:32,r2.w) ;010eea509abcdef01234 + xor.l #0x1234:16,@(0x9abcdef0:32,er2.l) ;010efa509abcdef01234 + xor.l #0x1234:16,@0xffff9abc:16 ;010e40509abc1234 + xor.l #0x1234:16,@0x9abcdef0:32 ;010e48509abcdef01234 + + xor.l er3,er1 ;01f06531 + + xor.l er3,@er1 ;01090153 + xor.l er3,@(0xc:2,er1) ;01093153 + xor.l er3,@er1+ ;01098153 + xor.l er3,@-er1 ;0109b153 + xor.l er3,@+er1 ;01099153 + xor.l er3,@er1- ;0109a153 + xor.l er3,@(0x1234:16,er1) ;0109c1531234 + xor.l er3,@(0x12345678:32,er1) ;0109c95312345678 + xor.l er3,@(0x1234:16,r2l.b) ;0109d2531234 + xor.l er3,@(0x1234:16,r2.w) ;0109e2531234 + xor.l er3,@(0x1234:16,er2.l) ;0109f2531234 + xor.l er3,@(0x12345678:32,r2l.b) ;0109da5312345678 + xor.l er3,@(0x12345678:32,r2.w) ;0109ea5312345678 + xor.l er3,@(0x12345678:32,er2.l) ;0109fa5312345678 + xor.l er3,@0x1234:16 ;010940531234 + xor.l er3,@0x12345678:32 ;0109485312345678 + + xor.l @er3,er1 ;010a0351 + xor.l @(0xc:2,er3),er1 ;010a3351 + xor.l @er3+,er1 ;010a8351 + xor.l @-er3,er1 ;010ab351 + xor.l @+er3,er1 ;010a9351 + xor.l @er3-,er1 ;010aa351 + xor.l @(0x1234:16,er1),er1 ;010ac1511234 + xor.l @(0x12345678:32,er1),er1 ;010ac95112345678 + xor.l @(0x1234:16,r2l.b),er1 ;010ad2511234 + xor.l @(0x1234:16,r2.w),er1 ;010ae2511234 + xor.l @(0x1234:16,er2.l),er1 ;010af2511234 + xor.l @(0x12345678:32,r2l.b),er1 ;010ada5112345678 + xor.l @(0x12345678:32,r2.w),er1 ;010aea5112345678 + xor.l @(0x12345678:32,er2.l),er1 ;010afa5112345678 + xor.l @0x1234:16,er1 ;010a40511234 + xor.l @0x12345678:32,er1 ;010a485112345678 + + xor.l @er3,@er1 ;0104693c0150 + xor.l @er3,@(0xc:2,er1) ;0104693c3150 + xor.l @er3,@-er1 ;0104693cb150 + xor.l @er3,@er1+ ;0104693c8150 + xor.l @er3,@er1- ;0104693ca150 + xor.l @er3,@+er1 ;0104693c9150 + xor.l @er3,@(0xffff9abc:16,er1) ;0104693cc1509abc + xor.l @er3,@(0x9abcdef0:32,er1) ;0104693cc9509abcdef0 + xor.l @er3,@(0xffff9abc:16,r2l.b) ;0104693cd2509abc + xor.l @er3,@(0xffff9abc:16,r2.w) ;0104693ce2509abc + xor.l @er3,@(0xffff9abc:16,er2.l) ;0104693cf2509abc + xor.l @er3,@(0x9abcdef0:32,r2l.b) ;0104693cda509abcdef0 + xor.l @er3,@(0x9abcdef0:32,r2.w) ;0104693cea509abcdef0 + xor.l @er3,@(0x9abcdef0:32,er2.l) ;0104693cfa509abcdef0 + xor.l @er3,@0xffff9abc:16 ;0104693c40509abc + xor.l @er3,@0x9abcdef0:32 ;0104693c48509abcdef0 + + xor.l @(0xc:2,er3),@er1 ;0107693c0150 + xor.l @(0xc:2,er3),@(0xc:2,er1) ;0107693c3150 + xor.l @(0xc:2,er3),@-er1 ;0107693cb150 + xor.l @(0xc:2,er3),@er1+ ;0107693c8150 + xor.l @(0xc:2,er3),@er1- ;0107693ca150 + xor.l @(0xc:2,er3),@+er1 ;0107693c9150 + xor.l @(0xc:2,er3),@(0xffff9abc:16,er1) ;0107693cc1509abc + xor.l @(0xc:2,er3),@(0x9abcdef0:32,er1) ;0107693cc9509abcdef0 + xor.l @(0xc:2,er3),@(0xffff9abc:16,r2l.b) ;0107693cd2509abc + xor.l @(0xc:2,er3),@(0xffff9abc:16,r2.w) ;0107693ce2509abc + xor.l @(0xc:2,er3),@(0xffff9abc:16,er2.l) ;0107693cf2509abc + xor.l @(0xc:2,er3),@(0x9abcdef0:32,r2l.b) ;0107693cda509abcdef0 + xor.l @(0xc:2,er3),@(0x9abcdef0:32,r2.w) ;0107693cea509abcdef0 + xor.l @(0xc:2,er3),@(0x9abcdef0:32,er2.l) ;0107693cfa509abcdef0 + xor.l @(0xc:2,er3),@0xffff9abc:16 ;0107693c40509abc + xor.l @(0xc:2,er3),@0x9abcdef0:32 ;0107693c48509abcdef0 + + xor.l @-er3,@er1 ;01076d3c0150 + xor.l @-er3,@(0xc:2,er1) ;01076d3c3150 + xor.l @-er3,@-er1 ;01076d3cb150 + xor.l @-er3,@er1+ ;01076d3c8150 + xor.l @-er3,@er1- ;01076d3ca150 + xor.l @-er3,@+er1 ;01076d3c9150 + xor.l @-er3,@(0xffff9abc:16,er1) ;01076d3cc1509abc + xor.l @-er3,@(0x9abcdef0:32,er1) ;01076d3cc9509abcdef0 + xor.l @-er3,@(0xffff9abc:16,r2l.b) ;01076d3cd2509abc + xor.l @-er3,@(0xffff9abc:16,r2.w) ;01076d3ce2509abc + xor.l @-er3,@(0xffff9abc:16,er2.l) ;01076d3cf2509abc + xor.l @-er3,@(0x9abcdef0:32,r2l.b) ;01076d3cda509abcdef0 + xor.l @-er3,@(0x9abcdef0:32,r2.w) ;01076d3cea509abcdef0 + xor.l @-er3,@(0x9abcdef0:32,er2.l) ;01076d3cfa509abcdef0 + xor.l @-er3,@0xffff9abc:16 ;01076d3c40509abc + xor.l @-er3,@0x9abcdef0:32 ;01076d3c48509abcdef0 + + xor.l @er3+,@er1 ;01046d3c0150 + xor.l @er3+,@(0xc:2,er1) ;01046d3c3150 + xor.l @er3+,@-er1 ;01046d3cb150 + xor.l @er3+,@er1+ ;01046d3c8150 + xor.l @er3+,@er1- ;01046d3ca150 + xor.l @er3+,@+er1 ;01046d3c9150 + xor.l @er3+,@(0xffff9abc:16,er1) ;01046d3cc1509abc + xor.l @er3+,@(0x9abcdef0:32,er1) ;01046d3cc9509abcdef0 + xor.l @er3+,@(0xffff9abc:16,r2l.b) ;01046d3cd2509abc + xor.l @er3+,@(0xffff9abc:16,r2.w) ;01046d3ce2509abc + xor.l @er3+,@(0xffff9abc:16,er2.l) ;01046d3cf2509abc + xor.l @er3+,@(0x9abcdef0:32,r2l.b) ;01046d3cda509abcdef0 + xor.l @er3+,@(0x9abcdef0:32,r2.w) ;01046d3cea509abcdef0 + xor.l @er3+,@(0x9abcdef0:32,er2.l) ;01046d3cfa509abcdef0 + xor.l @er3+,@0xffff9abc:16 ;01046d3c40509abc + xor.l @er3+,@0x9abcdef0:32 ;01046d3c48509abcdef0 + + xor.l @er3-,@er1 ;01066d3c0150 + xor.l @er3-,@(0xc:2,er1) ;01066d3c3150 + xor.l @er3-,@-er1 ;01066d3cb150 + xor.l @er3-,@er1+ ;01066d3c8150 + xor.l @er3-,@er1- ;01066d3ca150 + xor.l @er3-,@+er1 ;01066d3c9150 + xor.l @er3-,@(0xffff9abc:16,er1) ;01066d3cc1509abc + xor.l @er3-,@(0x9abcdef0:32,er1) ;01066d3cc9509abcdef0 + xor.l @er3-,@(0xffff9abc:16,r2l.b) ;01066d3cd2509abc + xor.l @er3-,@(0xffff9abc:16,r2.w) ;01066d3ce2509abc + xor.l @er3-,@(0xffff9abc:16,er2.l) ;01066d3cf2509abc + xor.l @er3-,@(0x9abcdef0:32,r2l.b) ;01066d3cda509abcdef0 + xor.l @er3-,@(0x9abcdef0:32,r2.w) ;01066d3cea509abcdef0 + xor.l @er3-,@(0x9abcdef0:32,er2.l) ;01066d3cfa509abcdef0 + xor.l @er3-,@0xffff9abc:16 ;01066d3c40509abc + xor.l @er3-,@0x9abcdef0:32 ;01066d3c48509abcdef0 + + xor.l @+er3,@er1 ;01056d3c0150 + xor.l @+er3,@(0xc:2,er1) ;01056d3c3150 + xor.l @+er3,@-er1 ;01056d3cb150 + xor.l @+er3,@er1+ ;01056d3c8150 + xor.l @+er3,@er1- ;01056d3ca150 + xor.l @+er3,@+er1 ;01056d3c9150 + xor.l @+er3,@(0xffff9abc:16,er1) ;01056d3cc1509abc + xor.l @+er3,@(0x9abcdef0:32,er1) ;01056d3cc9509abcdef0 + xor.l @+er3,@(0xffff9abc:16,r2l.b) ;01056d3cd2509abc + xor.l @+er3,@(0xffff9abc:16,r2.w) ;01056d3ce2509abc + xor.l @+er3,@(0xffff9abc:16,er2.l) ;01056d3cf2509abc + xor.l @+er3,@(0x9abcdef0:32,r2l.b) ;01056d3cda509abcdef0 + xor.l @+er3,@(0x9abcdef0:32,r2.w) ;01056d3cea509abcdef0 + xor.l @+er3,@(0x9abcdef0:32,er2.l) ;01056d3cfa509abcdef0 + xor.l @+er3,@0xffff9abc:16 ;01056d3c40509abc + xor.l @+er3,@0x9abcdef0:32 ;01056d3c48509abcdef0 + + xor.l @(0x1234:16,er3),@er1 ;01046f3c12340150 + xor.l @(0x1234:16,er3),@(0xc:2,er1) ;01046f3c12343150 + xor.l @(0x1234:16,er3),@-er1 ;01046f3c1234b150 + xor.l @(0x1234:16,er3),@er1+ ;01046f3c12348150 + xor.l @(0x1234:16,er3),@er1- ;01046f3c1234a150 + xor.l @(0x1234:16,er3),@+er1 ;01046f3c12349150 + xor.l @(0x1234:16,er3),@(0xffff9abc:16,er1) ;01046f3c1234c1509abc + xor.l @(0x1234:16,er3),@(0x9abcdef0:32,er1) ;01046f3c1234c9509abcdef0 + xor.l @(0x1234:16,er3),@(0xffff9abc:16,r2l.b) ;01046f3c1234d2509abc + xor.l @(0x1234:16,er3),@(0xffff9abc:16,r2.w) ;01046f3c1234e2509abc + xor.l @(0x1234:16,er3),@(0xffff9abc:16,er2.l) ;01046f3c1234f2509abc + xor.l @(0x1234:16,er3),@(0x9abcdef0:32,r2l.b) ;01046f3c1234da509abcdef0 + xor.l @(0x1234:16,er3),@(0x9abcdef0:32,r2.w) ;01046f3c1234ea509abcdef0 + xor.l @(0x1234:16,er3),@(0x9abcdef0:32,er2.l) ;01046f3c1234fa509abcdef0 + xor.l @(0x1234:16,er3),@0xffff9abc:16 ;01046f3c123440509abc + xor.l @(0x1234:16,er3),@0x9abcdef0:32 ;01046f3c123448509abcdef0 + + xor.l @(0x12345678:32,er3),@er1 ;78b46b2c123456780150 + xor.l @(0x12345678:32,er3),@(0xc:2,er1) ;78b46b2c123456783150 + xor.l @(0x12345678:32,er3),@-er1 ;78b46b2c12345678b150 + xor.l @(0x12345678:32,er3),@er1+ ;78b46b2c123456788150 + xor.l @(0x12345678:32,er3),@er1- ;78b46b2c12345678a150 + xor.l @(0x12345678:32,er3),@+er1 ;78b46b2c123456789150 + xor.l @(0x12345678:32,er3),@(0xffff9abc:16,er1) ;78b46b2c12345678c1509abc + xor.l @(0x12345678:32,er3),@(0x9abcdef0:32,er1) ;78b46b2c12345678c9509abcdef0 + xor.l @(0x12345678:32,er3),@(0xffff9abc:16,r2l.b) ;78b46b2c12345678d2509abc + xor.l @(0x12345678:32,er3),@(0xffff9abc:16,r2.w) ;78b46b2c12345678e2509abc + xor.l @(0x12345678:32,er3),@(0xffff9abc:16,er2.l) ;78b46b2c12345678f2509abc + xor.l @(0x12345678:32,er3),@(0x9abcdef0:32,r2l.b) ;78b46b2c12345678da509abcdef0 + xor.l @(0x12345678:32,er3),@(0x9abcdef0:32,r2.w) ;78b46b2c12345678ea509abcdef0 + xor.l @(0x12345678:32,er3),@(0x9abcdef0:32,er2.l) ;78b46b2c12345678fa509abcdef0 + xor.l @(0x12345678:32,er3),@0xffff9abc:16 ;78b46b2c1234567840509abc + xor.l @(0x12345678:32,er3),@0x9abcdef0:32 ;78b46b2c1234567848509abcdef0 + + xor.l @(0x1234:16,r3l.b),@er1 ;01056f3c12340150 + xor.l @(0x1234:16,r3l.b),@(0xc:2,er1) ;01056f3c12343150 + xor.l @(0x1234:16,r3l.b),@-er1 ;01056f3c1234b150 + xor.l @(0x1234:16,r3l.b),@er1+ ;01056f3c12348150 + xor.l @(0x1234:16,r3l.b),@er1- ;01056f3c1234a150 + xor.l @(0x1234:16,r3l.b),@+er1 ;01056f3c12349150 + xor.l @(0x1234:16,r3l.b),@(0xffff9abc:16,er1) ;01056f3c1234c1509abc + xor.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1) ;01056f3c1234c9509abcdef0 + xor.l @(0x1234:16,r3l.b),@(0xffff9abc:16,r2l.b) ;01056f3c1234d2509abc + xor.l @(0x1234:16,r3l.b),@(0xffff9abc:16,r2.w) ;01056f3c1234e2509abc + xor.l @(0x1234:16,r3l.b),@(0xffff9abc:16,er2.l) ;01056f3c1234f2509abc + xor.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2l.b) ;01056f3c1234da509abcdef0 + xor.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2.w) ;01056f3c1234ea509abcdef0 + xor.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,er2.l) ;01056f3c1234fa509abcdef0 + xor.l @(0x1234:16,r3l.b),@0xffff9abc:16 ;01056f3c123440509abc + xor.l @(0x1234:16,r3l.b),@0x9abcdef0:32 ;01056f3c123448509abcdef0 + + xor.l @(0x1234:16,r3.w),@er1 ;01066f3c12340150 + xor.l @(0x1234:16,r3.w),@(0xc:2,er1) ;01066f3c12343150 + xor.l @(0x1234:16,r3.w),@-er1 ;01066f3c1234b150 + xor.l @(0x1234:16,r3.w),@er1+ ;01066f3c12348150 + xor.l @(0x1234:16,r3.w),@er1- ;01066f3c1234a150 + xor.l @(0x1234:16,r3.w),@+er1 ;01066f3c12349150 + xor.l @(0x1234:16,r3.w),@(0xffff9abc:16,er1) ;01066f3c1234c1509abc + xor.l @(0x1234:16,r3.w),@(0x9abcdef0:32,er1) ;01066f3c1234c9509abcdef0 + xor.l @(0x1234:16,r3.w),@(0xffff9abc:16,r2l.b) ;01066f3c1234d2509abc + xor.l @(0x1234:16,r3.w),@(0xffff9abc:16,r2.w) ;01066f3c1234e2509abc + xor.l @(0x1234:16,r3.w),@(0xffff9abc:16,er2.l) ;01066f3c1234f2509abc + xor.l @(0x1234:16,r3.w),@(0x9abcdef0:32,r2l.b) ;01066f3c1234da509abcdef0 + xor.l @(0x1234:16,r3.w),@(0x9abcdef0:32,r2.w) ;01066f3c1234ea509abcdef0 + xor.l @(0x1234:16,r3.w),@(0x9abcdef0:32,er2.l) ;01066f3c1234fa509abcdef0 + xor.l @(0x1234:16,r3.w),@0xffff9abc:16 ;01066f3c123440509abc + xor.l @(0x1234:16,r3.w),@0x9abcdef0:32 ;01066f3c123448509abcdef0 + + xor.l @(0x1234:16,er3.l),@er1 ;01076f3c12340150 + xor.l @(0x1234:16,er3.l),@(0xc:2,er1) ;01076f3c12343150 + xor.l @(0x1234:16,er3.l),@-er1 ;01076f3c1234b150 + xor.l @(0x1234:16,er3.l),@er1+ ;01076f3c12348150 + xor.l @(0x1234:16,er3.l),@er1- ;01076f3c1234a150 + xor.l @(0x1234:16,er3.l),@+er1 ;01076f3c12349150 + xor.l @(0x1234:16,er3.l),@(0xffff9abc:16,er1) ;01076f3c1234c1509abc + xor.l @(0x1234:16,er3.l),@(0x9abcdef0:32,er1) ;01076f3c1234c9509abcdef0 + xor.l @(0x1234:16,er3.l),@(0xffff9abc:16,r2l.b) ;01076f3c1234d2509abc + xor.l @(0x1234:16,er3.l),@(0xffff9abc:16,r2.w) ;01076f3c1234e2509abc + xor.l @(0x1234:16,er3.l),@(0xffff9abc:16,er2.l) ;01076f3c1234f2509abc + xor.l @(0x1234:16,er3.l),@(0x9abcdef0:32,r2l.b) ;01076f3c1234da509abcdef0 + xor.l @(0x1234:16,er3.l),@(0x9abcdef0:32,r2.w) ;01076f3c1234ea509abcdef0 + xor.l @(0x1234:16,er3.l),@(0x9abcdef0:32,er2.l) ;01076f3c1234fa509abcdef0 + xor.l @(0x1234:16,er3.l),@0xffff9abc:16 ;01076f3c123440509abc + xor.l @(0x1234:16,er3.l),@0x9abcdef0:32 ;01076f3c123448509abcdef0 + + xor.l @(0x12345678:32,r3l.b),@er1 ;78b56b2c123456780150 + xor.l @(0x12345678:32,r3l.b),@(0xc:2,er1) ;78b56b2c123456783150 + xor.l @(0x12345678:32,r3l.b),@-er1 ;78b56b2c12345678b150 + xor.l @(0x12345678:32,r3l.b),@er1+ ;78b56b2c123456788150 + xor.l @(0x12345678:32,r3l.b),@er1- ;78b56b2c12345678a150 + xor.l @(0x12345678:32,r3l.b),@+er1 ;78b56b2c123456789150 + xor.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,er1) ;78b56b2c12345678c1509abc + xor.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1) ;78b56b2c12345678c9509abcdef0 + xor.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2l.b) ;78b56b2c12345678d2509abc + xor.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2.w) ;78b56b2c12345678e2509abc + xor.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,er2.l) ;78b56b2c12345678f2509abc + xor.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2l.b) ;78b56b2c12345678da509abcdef0 + xor.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2.w) ;78b56b2c12345678ea509abcdef0 + xor.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er2.l) ;78b56b2c12345678fa509abcdef0 + xor.l @(0x12345678:32,r3l.b),@0xffff9abc:16 ;78b56b2c1234567840509abc + xor.l @(0x12345678:32,r3l.b),@0x9abcdef0:32 ;78b56b2c1234567848509abcdef0 + + xor.l @(0x12345678:32,r3.w),@er1 ;78b66b2c123456780150 + xor.l @(0x12345678:32,r3.w),@(0xc:2,er1) ;78b66b2c123456783150 + xor.l @(0x12345678:32,r3.w),@-er1 ;78b66b2c12345678b150 + xor.l @(0x12345678:32,r3.w),@er1+ ;78b66b2c123456788150 + xor.l @(0x12345678:32,r3.w),@er1- ;78b66b2c12345678a150 + xor.l @(0x12345678:32,r3.w),@+er1 ;78b66b2c123456789150 + xor.l @(0x12345678:32,r3.w),@(0xffff9abc:16,er1) ;78b66b2c12345678c1509abc + xor.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1) ;78b66b2c12345678c9509abcdef0 + xor.l @(0x12345678:32,r3.w),@(0xffff9abc:16,r2l.b) ;78b66b2c12345678d2509abc + xor.l @(0x12345678:32,r3.w),@(0xffff9abc:16,r2.w) ;78b66b2c12345678e2509abc + xor.l @(0x12345678:32,r3.w),@(0xffff9abc:16,er2.l) ;78b66b2c12345678f2509abc + xor.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2l.b) ;78b66b2c12345678da509abcdef0 + xor.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2.w) ;78b66b2c12345678ea509abcdef0 + xor.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,er2.l) ;78b66b2c12345678fa509abcdef0 + xor.l @(0x12345678:32,r3.w),@0xffff9abc:16 ;78b66b2c1234567840509abc + xor.l @(0x12345678:32,r3.w),@0x9abcdef0:32 ;78b66b2c1234567848509abcdef0 + + xor.l @(0x12345678:32,er3.l),@er1 ;78b76b2c123456780150 + xor.l @(0x12345678:32,er3.l),@(0xc:2,er1) ;78b76b2c123456783150 + xor.l @(0x12345678:32,er3.l),@-er1 ;78b76b2c12345678b150 + xor.l @(0x12345678:32,er3.l),@er1+ ;78b76b2c123456788150 + xor.l @(0x12345678:32,er3.l),@er1- ;78b76b2c12345678a150 + xor.l @(0x12345678:32,er3.l),@+er1 ;78b76b2c123456789150 + xor.l @(0x12345678:32,er3.l),@(0xffff9abc:16,er1) ;78b76b2c12345678c1509abc + xor.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1) ;78b76b2c12345678c9509abcdef0 + xor.l @(0x12345678:32,er3.l),@(0xffff9abc:16,r2l.b) ;78b76b2c12345678d2509abc + xor.l @(0x12345678:32,er3.l),@(0xffff9abc:16,r2.w) ;78b76b2c12345678e2509abc + xor.l @(0x12345678:32,er3.l),@(0xffff9abc:16,er2.l) ;78b76b2c12345678f2509abc + xor.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2l.b) ;78b76b2c12345678da509abcdef0 + xor.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2.w) ;78b76b2c12345678ea509abcdef0 + xor.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,er2.l) ;78b76b2c12345678fa509abcdef0 + xor.l @(0x12345678:32,er3.l),@0xffff9abc:16 ;78b76b2c1234567840509abc + xor.l @(0x12345678:32,er3.l),@0x9abcdef0:32 ;78b76b2c1234567848509abcdef0 + + xor.l @0x1234:16,@er1 ;01046b0c12340150 + xor.l @0x1234:16,@(0xc:2,er1) ;01046b0c12343150 + xor.l @0x1234:16,@-er1 ;01046b0c1234b150 + xor.l @0x1234:16,@er1+ ;01046b0c12348150 + xor.l @0x1234:16,@er1- ;01046b0c1234a150 + xor.l @0x1234:16,@+er1 ;01046b0c12349150 + xor.l @0x1234:16,@(0xffff9abc:16,er1) ;01046b0c1234c1509abc + xor.l @0x1234:16,@(0x9abcdef0:32,er1) ;01046b0c1234c9509abcdef0 + xor.l @0x1234:16,@(0xffff9abc:16,r2l.b) ;01046b0c1234d2509abc + xor.l @0x1234:16,@(0xffff9abc:16,r2.w) ;01046b0c1234e2509abc + xor.l @0x1234:16,@(0xffff9abc:16,er2.l) ;01046b0c1234f2509abc + xor.l @0x1234:16,@(0x9abcdef0:32,r2l.b) ;01046b0c1234da509abcdef0 + xor.l @0x1234:16,@(0x9abcdef0:32,r2.w) ;01046b0c1234ea509abcdef0 + xor.l @0x1234:16,@(0x9abcdef0:32,er2.l) ;01046b0c1234fa509abcdef0 + xor.l @0x1234:16,@0xffff9abc:16 ;01046b0c123440509abc + xor.l @0x1234:16,@0x9abcdef0:32 ;01046b0c123448509abcdef0 + + xor.l @0x12345678:32,@er1 ;01046b2c123456780150 + xor.l @0x12345678:32,@(0xc:2,er1) ;01046b2c123456783150 + xor.l @0x12345678:32,@-er1 ;01046b2c12345678b150 + xor.l @0x12345678:32,@er1+ ;01046b2c123456788150 + xor.l @0x12345678:32,@er1- ;01046b2c12345678a150 + xor.l @0x12345678:32,@+er1 ;01046b2c123456789150 + xor.l @0x12345678:32,@(0xffff9abc:16,er1) ;01046b2c12345678c1509abc + xor.l @0x12345678:32,@(0x9abcdef0:32,er1) ;01046b2c12345678c9509abcdef0 + xor.l @0x12345678:32,@(0xffff9abc:16,r2l.b) ;01046b2c12345678d2509abc + xor.l @0x12345678:32,@(0xffff9abc:16,r2.w) ;01046b2c12345678e2509abc + xor.l @0x12345678:32,@(0xffff9abc:16,er2.l) ;01046b2c12345678f2509abc + xor.l @0x12345678:32,@(0x9abcdef0:32,r2l.b) ;01046b2c12345678da509abcdef0 + xor.l @0x12345678:32,@(0x9abcdef0:32,r2.w) ;01046b2c12345678ea509abcdef0 + xor.l @0x12345678:32,@(0x9abcdef0:32,er2.l) ;01046b2c12345678fa509abcdef0 + xor.l @0x12345678:32,@0xffff9abc:16 ;01046b2c1234567840509abc + xor.l @0x12345678:32,@0x9abcdef0:32 ;01046b2c1234567848509abcdef0 + + .end diff --git a/gdb/testsuite/gdb.disasm/t10_and.exp b/gdb/testsuite/gdb.disasm/t10_and.exp new file mode 100644 index 0000000..63ae907 --- /dev/null +++ b/gdb/testsuite/gdb.disasm/t10_and.exp @@ -0,0 +1,1866 @@ +# Copyright (C) 2003 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# Please email any bugs, comments, and/or additions to this file to: +# bug-gdb@prep.ai.mit.edu + +# This file was written by Michael Snyder (msnyder@redhat.com) + +if $tracelevel then { + strace $tracelevel +} + +if ![istarget "h8300*-*-*"] { + verbose "Tests ignored for all but h8300s based targets." + return +} + +set prms_id 0 +set bug_id 0 + +set testfile "t10_and" +set srcfile ${srcdir}/${subdir}/${testfile}.s +set objfile ${objdir}/${subdir}/${testfile}.o +set binfile ${objdir}/${subdir}/${testfile}.x + +set asm-flags ""; +set link-flags "-m h8300sxelf"; + + +if {[target_assemble $srcfile $objfile "${asm-flags}"] != ""} then { + gdb_suppress_entire_file "Testcase assembly failed, so all tests in this file will automatically fail." +} + +if {[target_link $objfile $binfile "${link-flags}"] != ""} then { + gdb_suppress_entire_file "Testcase link failed, so all tests in this file will automatically fail." +} + +gdb_start +gdb_reinitialize_dir $srcdir/$subdir +gdb_load $binfile + +gdb_test "x /i _start" "and.b\t#0x12(:8|),r1h" \ + "and.b #0x12:8,r1h" +gdb_test "x" "and.b\t#0x12(:8|),@er1" \ + "and.b #0x12:8,@er1" +gdb_test "x" "and.b\t#0x12(:8|),@\\(0x3(:2|),er1\\)" \ + "and.b #0x12:8,@(0x3:2,er1)" +gdb_test "x" "and.b\t#0x12(:8|),@er1\\+" \ + "and.b #0x12:8,@er1+" +gdb_test "x" "and.b\t#0x12(:8|),@-er1" \ + "and.b #0x12:8,@-er1" +gdb_test "x" "and.b\t#0x12(:8|),@\\+er1" \ + "and.b #0x12:8,@+er1" +gdb_test "x" "and.b\t#0x12(:8|),@er1-" \ + "and.b #0x12:8,@er1-" +gdb_test "x" "and.b\t#0x12(:8|),@\\(0x1234(:16|),er1\\)" \ + "and.b #0x12:8,@(0x1234:16,er1)" +gdb_test "x" "and.b\t#0x12(:8|),@\\(0x12345678(:32|),er1\\)" \ + "and.b #0x12:8,@(0x12345678:32,er1)" +gdb_test "x" "and.b\t#0x12(:8|),@\\(0x1234(:16|),r2l.b\\)" \ + "and.b #0x12:8,@(0x1234:16,r2l.b)" +gdb_test "x" "and.b\t#0x12(:8|),@\\(0x1234(:16|),r2.w\\)" \ + "and.b #0x12:8,@(0x1234:16,r2.w)" +gdb_test "x" "and.b\t#0x12(:8|),@\\(0x1234(:16|),er2.l\\)" \ + "and.b #0x12:8,@(0x1234:16,er2.l)" +gdb_test "x" "and.b\t#0x12(:8|),@\\(0x12345678(:32|),r2l.b\\)" \ + "and.b #0x12:8,@(0x12345678:32,r2l.b)" +gdb_test "x" "and.b\t#0x12(:8|),@\\(0x12345678(:32|),r2.w\\)" \ + "and.b #0x12:8,@(0x12345678:32,r2.w)" +gdb_test "x" "and.b\t#0x12(:8|),@\\(0x12345678(:32|),er2.l\\)" \ + "and.b #0x12:8,@(0x12345678:32,er2.l)" +gdb_test "x" "and.b\t#0x12(:8|),@0x12(:8|)" \ + "and.b #0x12:8,@0x12:8" +gdb_test "x" "and.b\t#0x12(:8|),@0x1234(:16|)" \ + "and.b #0x12:8,@0x1234:16" +gdb_test "x" "and.b\t#0x12(:8|),@0x12345678(:32|)" \ + "and.b #0x12:8,@0x12345678:32" +gdb_test "x" "and.b\tr3h,r1h" \ + "and.b r3h,r1h" +gdb_test "x" "and.b\tr3h,@er1" \ + "and.b r3h,@er1" +gdb_test "x" "and.b\tr3h,@\\(0x3(:2|),er1\\)" \ + "and.b r3h,@(0x3:2,er1)" +gdb_test "x" "and.b\tr3h,@er1\\+" \ + "and.b r3h,@er1+" +gdb_test "x" "and.b\tr3h,@-er1" \ + "and.b r3h,@-er1" +gdb_test "x" "and.b\tr3h,@\\+er1" \ + "and.b r3h,@+er1" +gdb_test "x" "and.b\tr3h,@er1-" \ + "and.b r3h,@er1-" +gdb_test "x" "and.b\tr3h,@\\(0x1234(:16|),er1\\)" \ + "and.b r3h,@(0x1234:16,er1)" +gdb_test "x" "and.b\tr3h,@\\(0x12345678(:32|),er1\\)" \ + "and.b r3h,@(0x12345678:32,er1)" +gdb_test "x" "and.b\tr3h,@\\(0x1234(:16|),r2l.b\\)" \ + "and.b r3h,@(0x1234:16,r2l.b)" +gdb_test "x" "and.b\tr3h,@\\(0x1234(:16|),r2.w\\)" \ + "and.b r3h,@(0x1234:16,r2.w)" +gdb_test "x" "and.b\tr3h,@\\(0x1234(:16|),er2.l\\)" \ + "and.b r3h,@(0x1234:16,er2.l)" +gdb_test "x" "and.b\tr3h,@\\(0x12345678(:32|),r2l.b\\)" \ + "and.b r3h,@(0x12345678:32,r2l.b)" +gdb_test "x" "and.b\tr3h,@\\(0x12345678(:32|),r2.w\\)" \ + "and.b r3h,@(0x12345678:32,r2.w)" +gdb_test "x" "and.b\tr3h,@\\(0x12345678(:32|),er2.l\\)" \ + "and.b r3h,@(0x12345678:32,er2.l)" +gdb_test "x" "and.b\tr3h,@0x12(:8|)" \ + "and.b r3h,@0x12:8" +gdb_test "x" "and.b\tr3h,@0x1234(:16|)" \ + "and.b r3h,@0x1234:16" +gdb_test "x" "and.b\tr3h,@0x12345678(:32|)" \ + "and.b r3h,@0x12345678:32" +gdb_test "x" "and.b\t@er3,r1h" \ + "and.b @er3,r1h" +gdb_test "x" "and.b\t@\\(0x3(:2|),er3\\),r1h" \ + "and.b @(0x3:2,er3),r1h" +gdb_test "x" "and.b\t@er3\\+,r1h" \ + "and.b @er3+,r1h" +gdb_test "x" "and.b\t@-er3,r1h" \ + "and.b @-er3,r1h" +gdb_test "x" "and.b\t@\\+er3,r1h" \ + "and.b @+er3,r1h" +gdb_test "x" "and.b\t@er3-,r1h" \ + "and.b @er3-,r1h" +gdb_test "x" "and.b\t@\\(0x1234(:16|),er1\\),r1h" \ + "and.b @(0x1234:16,er1),r1h" +gdb_test "x" "and.b\t@\\(0x12345678(:32|),er1\\),r1h" \ + "and.b @(0x12345678:32,er1),r1h" +gdb_test "x" "and.b\t@\\(0x1234(:16|),r2l.b\\),r1h" \ + "and.b @(0x1234:16,r2l.b),r1h" +gdb_test "x" "and.b\t@\\(0x1234(:16|),r2.w\\),r1h" \ + "and.b @(0x1234:16,r2.w),r1h" +gdb_test "x" "and.b\t@\\(0x1234(:16|),er2.l\\),r1h" \ + "and.b @(0x1234:16,er2.l),r1h" +gdb_test "x" "and.b\t@\\(0x12345678(:32|),r2l.b\\),r1h" \ + "and.b @(0x12345678:32,r2l.b),r1h" +gdb_test "x" "and.b\t@\\(0x12345678(:32|),r2.w\\),r1h" \ + "and.b @(0x12345678:32,r2.w),r1h" +gdb_test "x" "and.b\t@\\(0x12345678(:32|),er2.l\\),r1h" \ + "and.b @(0x12345678:32,er2.l),r1h" +gdb_test "x" "and.b\t@0x12(:8|),r1h" \ + "and.b @0x12:8,r1h" +gdb_test "x" "and.b\t@0x1234(:16|),r1h" \ + "and.b @0x1234:16,r1h" +gdb_test "x" "and.b\t@0x12345678(:32|),r1h" \ + "and.b @0x12345678:32,r1h" +gdb_test "x" "and.b\t@er3,@er1" \ + "and.b @er3,@er1" +gdb_test "x" "and.b\t@er3,@\\(0x3(:2|),er1\\)" \ + "and.b @er3,@(0x3:2,er1)" +gdb_test "x" "and.b\t@er3,@-er1" \ + "and.b @er3,@-er1" +gdb_test "x" "and.b\t@er3,@er1\\+" \ + "and.b @er3,@er1+" +gdb_test "x" "and.b\t@er3,@er1-" \ + "and.b @er3,@er1-" +gdb_test "x" "and.b\t@er3,@\\+er1" \ + "and.b @er3,@+er1" +gdb_test "x" "and.b\t@er3,@\\(0x9abc(:16|),er1\\)" \ + "and.b @er3,@(0x9abc:16,er1)" +gdb_test "x" "and.b\t@er3,@\\(0x9abcdef0(:32|),er1\\)" \ + "and.b @er3,@(0x9abcdef0:32,er1)" +gdb_test "x" "and.b\t@er3,@\\(0x9abc(:16|),r2l.b\\)" \ + "and.b @er3,@(0x9abc:16,r2l.b)" +gdb_test "x" "and.b\t@er3,@\\(0x9abc(:16|),r2.w\\)" \ + "and.b @er3,@(0x9abc:16,r2.w)" +gdb_test "x" "and.b\t@er3,@\\(0x9abc(:16|),er2.l\\)" \ + "and.b @er3,@(0x9abc:16,er2.l)" +gdb_test "x" "and.b\t@er3,@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "and.b @er3,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "and.b\t@er3,@\\(0x9abcdef0(:32|),r2.w\\)" \ + "and.b @er3,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "and.b\t@er3,@\\(0x9abcdef0(:32|),er2.l\\)" \ + "and.b @er3,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "and.b\t@er3,@0x9abc(:16|)" \ + "and.b @er3,@0x9abc:16" +gdb_test "x" "and.b\t@er3,@0x9abcdef0(:32|)" \ + "and.b @er3,@0x9abcdef0:32" +gdb_test "x" "and.b\t@-er3,@er1" \ + "and.b @-er3,@er1" +gdb_test "x" "and.b\t@-er3,@\\(0x3(:2|),er1\\)" \ + "and.b @-er3,@(0x3:2,er1)" +gdb_test "x" "and.b\t@-er3,@-er1" \ + "and.b @-er3,@-er1" +gdb_test "x" "and.b\t@-er3,@er1\\+" \ + "and.b @-er3,@er1+" +gdb_test "x" "and.b\t@-er3,@er1-" \ + "and.b @-er3,@er1-" +gdb_test "x" "and.b\t@-er3,@\\+er1" \ + "and.b @-er3,@+er1" +gdb_test "x" "and.b\t@-er3,@\\(0x9abc(:16|),er1\\)" \ + "and.b @-er3,@(0x9abc:16,er1)" +gdb_test "x" "and.b\t@-er3,@\\(0x9abcdef0(:32|),er1\\)" \ + "and.b @-er3,@(0x9abcdef0:32,er1)" +gdb_test "x" "and.b\t@-er3,@\\(0x9abc(:16|),r2l.b\\)" \ + "and.b @-er3,@(0x9abc:16,r2l.b)" +gdb_test "x" "and.b\t@-er3,@\\(0x9abc(:16|),r2.w\\)" \ + "and.b @-er3,@(0x9abc:16,r2.w)" +gdb_test "x" "and.b\t@-er3,@\\(0x9abc(:16|),er2.l\\)" \ + "and.b @-er3,@(0x9abc:16,er2.l)" +gdb_test "x" "and.b\t@-er3,@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "and.b @-er3,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "and.b\t@-er3,@\\(0x9abcdef0(:32|),r2.w\\)" \ + "and.b @-er3,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "and.b\t@-er3,@\\(0x9abcdef0(:32|),er2.l\\)" \ + "and.b @-er3,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "and.b\t@-er3,@0x9abc(:16|)" \ + "and.b @-er3,@0x9abc:16" +gdb_test "x" "and.b\t@-er3,@0x9abcdef0(:32|)" \ + "and.b @-er3,@0x9abcdef0:32" +gdb_test "x" "and.b\t@er3\\+,@er1" \ + "and.b @er3+,@er1" +gdb_test "x" "and.b\t@er3\\+,@\\(0x3(:2|),er1\\)" \ + "and.b @er3+,@(0x3:2,er1)" +gdb_test "x" "and.b\t@er3\\+,@-er1" \ + "and.b @er3+,@-er1" +gdb_test "x" "and.b\t@er3\\+,@er1\\+" \ + "and.b @er3+,@er1+" +gdb_test "x" "and.b\t@er3\\+,@er1-" \ + "and.b @er3+,@er1-" +gdb_test "x" "and.b\t@er3\\+,@\\+er1" \ + "and.b @er3+,@+er1" +gdb_test "x" "and.b\t@er3\\+,@\\(0x9abc(:16|),er1\\)" \ + "and.b @er3+,@(0x9abc:16,er1)" +gdb_test "x" "and.b\t@er3\\+,@\\(0x9abcdef0(:32|),er1\\)" \ + "and.b @er3+,@(0x9abcdef0:32,er1)" +gdb_test "x" "and.b\t@er3\\+,@\\(0x9abc(:16|),r2l.b\\)" \ + "and.b @er3+,@(0x9abc:16,r2l.b)" +gdb_test "x" "and.b\t@er3\\+,@\\(0x9abc(:16|),r2.w\\)" \ + "and.b @er3+,@(0x9abc:16,r2.w)" +gdb_test "x" "and.b\t@er3\\+,@\\(0x9abc(:16|),er2.l\\)" \ + "and.b @er3+,@(0x9abc:16,er2.l)" +gdb_test "x" "and.b\t@er3\\+,@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "and.b @er3+,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "and.b\t@er3\\+,@\\(0x9abcdef0(:32|),r2.w\\)" \ + "and.b @er3+,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "and.b\t@er3\\+,@\\(0x9abcdef0(:32|),er2.l\\)" \ + "and.b @er3+,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "and.b\t@er3\\+,@0x9abc(:16|)" \ + "and.b @er3+,@0x9abc:16" +gdb_test "x" "and.b\t@er3\\+,@0x9abcdef0(:32|)" \ + "and.b @er3+,@0x9abcdef0:32" +gdb_test "x" "and.b\t@er3-,@er1" \ + "and.b @er3-,@er1" +gdb_test "x" "and.b\t@er3-,@\\(0x3(:2|),er1\\)" \ + "and.b @er3-,@(0x3:2,er1)" +gdb_test "x" "and.b\t@er3-,@-er1" \ + "and.b @er3-,@-er1" +gdb_test "x" "and.b\t@er3-,@er1\\+" \ + "and.b @er3-,@er1+" +gdb_test "x" "and.b\t@er3-,@er1-" \ + "and.b @er3-,@er1-" +gdb_test "x" "and.b\t@er3-,@\\+er1" \ + "and.b @er3-,@+er1" +gdb_test "x" "and.b\t@er3-,@\\(0x9abc(:16|),er1\\)" \ + "and.b @er3-,@(0x9abc:16,er1)" +gdb_test "x" "and.b\t@er3-,@\\(0x9abcdef0(:32|),er1\\)" \ + "and.b @er3-,@(0x9abcdef0:32,er1)" +gdb_test "x" "and.b\t@er3-,@\\(0x9abc(:16|),r2l.b\\)" \ + "and.b @er3-,@(0x9abc:16,r2l.b)" +gdb_test "x" "and.b\t@er3-,@\\(0x9abc(:16|),r2.w\\)" \ + "and.b @er3-,@(0x9abc:16,r2.w)" +gdb_test "x" "and.b\t@er3-,@\\(0x9abc(:16|),er2.l\\)" \ + "and.b @er3-,@(0x9abc:16,er2.l)" +gdb_test "x" "and.b\t@er3-,@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "and.b @er3-,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "and.b\t@er3-,@\\(0x9abcdef0(:32|),r2.w\\)" \ + "and.b @er3-,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "and.b\t@er3-,@\\(0x9abcdef0(:32|),er2.l\\)" \ + "and.b @er3-,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "and.b\t@er3-,@0x9abc(:16|)" \ + "and.b @er3-,@0x9abc:16" +gdb_test "x" "and.b\t@er3-,@0x9abcdef0(:32|)" \ + "and.b @er3-,@0x9abcdef0:32" +gdb_test "x" "and.b\t@\\+er3,@er1" \ + "and.b @+er3,@er1" +gdb_test "x" "and.b\t@\\+er3,@\\(0x3(:2|),er1\\)" \ + "and.b @+er3,@(0x3:2,er1)" +gdb_test "x" "and.b\t@\\+er3,@-er1" \ + "and.b @+er3,@-er1" +gdb_test "x" "and.b\t@\\+er3,@er1\\+" \ + "and.b @+er3,@er1+" +gdb_test "x" "and.b\t@\\+er3,@er1-" \ + "and.b @+er3,@er1-" +gdb_test "x" "and.b\t@\\+er3,@\\+er1" \ + "and.b @+er3,@+er1" +gdb_test "x" "and.b\t@\\+er3,@\\(0x9abc(:16|),er1\\)" \ + "and.b @+er3,@(0x9abc:16,er1)" +gdb_test "x" "and.b\t@\\+er3,@\\(0x9abcdef0(:32|),er1\\)" \ + "and.b @+er3,@(0x9abcdef0:32,er1)" +gdb_test "x" "and.b\t@\\+er3,@\\(0x9abc(:16|),r2l.b\\)" \ + "and.b @+er3,@(0x9abc:16,r2l.b)" +gdb_test "x" "and.b\t@\\+er3,@\\(0x9abc(:16|),r2.w\\)" \ + "and.b @+er3,@(0x9abc:16,r2.w)" +gdb_test "x" "and.b\t@\\+er3,@\\(0x9abc(:16|),er2.l\\)" \ + "and.b @+er3,@(0x9abc:16,er2.l)" +gdb_test "x" "and.b\t@\\+er3,@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "and.b @+er3,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "and.b\t@\\+er3,@\\(0x9abcdef0(:32|),r2.w\\)" \ + "and.b @+er3,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "and.b\t@\\+er3,@\\(0x9abcdef0(:32|),er2.l\\)" \ + "and.b @+er3,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "and.b\t@\\+er3,@0x9abc(:16|)" \ + "and.b @+er3,@0x9abc:16" +gdb_test "x" "and.b\t@\\+er3,@0x9abcdef0(:32|)" \ + "and.b @+er3,@0x9abcdef0:32" +gdb_test "x" "and.b\t@\\(0x1234(:16|),er3\\),@er1" \ + "and.b @(0x1234:16,er3),@er1" +gdb_test "x" "and.b\t@\\(0x1234(:16|),er3\\),@\\(0x3(:2|),er1\\)" \ + "and.b @(0x1234:16,er3),@(0x3:2,er1)" +gdb_test "x" "and.b\t@\\(0x1234(:16|),er3\\),@-er1" \ + "and.b @(0x1234:16,er3),@-er1" +gdb_test "x" "and.b\t@\\(0x1234(:16|),er3\\),@er1\\+" \ + "and.b @(0x1234:16,er3),@er1+" +gdb_test "x" "and.b\t@\\(0x1234(:16|),er3\\),@er1-" \ + "and.b @(0x1234:16,er3),@er1-" +gdb_test "x" "and.b\t@\\(0x1234(:16|),er3\\),@\\+er1" \ + "and.b @(0x1234:16,er3),@+er1" +gdb_test "x" "and.b\t@\\(0x1234(:16|),er3\\),@\\(0x9abc(:16|),er1\\)" \ + "and.b @(0x1234:16,er3),@(0x9abc:16,er1)" +gdb_test "x" "and.b\t@\\(0x1234(:16|),er3\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "and.b @(0x1234:16,er3),@(0x9abcdef0:32,er1)" +gdb_test "x" "and.b\t@\\(0x1234(:16|),er3\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "and.b @(0x1234:16,er3),@(0x9abc:16,r2l.b)" +gdb_test "x" "and.b\t@\\(0x1234(:16|),er3\\),@\\(0x9abc(:16|),r2.w\\)" \ + "and.b @(0x1234:16,er3),@(0x9abc:16,r2.w)" +gdb_test "x" "and.b\t@\\(0x1234(:16|),er3\\),@\\(0x9abc(:16|),er2.l\\)" \ + "and.b @(0x1234:16,er3),@(0x9abc:16,er2.l)" +gdb_test "x" "and.b\t@\\(0x1234(:16|),er3\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "and.b @(0x1234:16,er3),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "and.b\t@\\(0x1234(:16|),er3\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "and.b @(0x1234:16,er3),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "and.b\t@\\(0x1234(:16|),er3\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "and.b @(0x1234:16,er3),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "and.b\t@\\(0x1234(:16|),er3\\),@0x9abc(:16|)" \ + "and.b @(0x1234:16,er3),@0x9abc:16" +gdb_test "x" "and.b\t@\\(0x1234(:16|),er3\\),@0x9abcdef0(:32|)" \ + "and.b @(0x1234:16,er3),@0x9abcdef0:32" +gdb_test "x" "and.b\t@\\(0x12345678(:32|),er3\\),@er1" \ + "and.b @(0x12345678:32,er3),@er1" +gdb_test "x" "and.b\t@\\(0x12345678(:32|),er3\\),@\\(0x3(:2|),er1\\)" \ + "and.b @(0x12345678:32,er3),@(0x3:2,er1)" +gdb_test "x" "and.b\t@\\(0x12345678(:32|),er3\\),@-er1" \ + "and.b @(0x12345678:32,er3),@-er1" +gdb_test "x" "and.b\t@\\(0x12345678(:32|),er3\\),@er1\\+" \ + "and.b @(0x12345678:32,er3),@er1+" +gdb_test "x" "and.b\t@\\(0x12345678(:32|),er3\\),@er1-" \ + "and.b @(0x12345678:32,er3),@er1-" +gdb_test "x" "and.b\t@\\(0x12345678(:32|),er3\\),@\\+er1" \ + "and.b @(0x12345678:32,er3),@+er1" +gdb_test "x" "and.b\t@\\(0x12345678(:32|),er3\\),@\\(0x9abc(:16|),er1\\)" \ + "and.b @(0x12345678:32,er3),@(0x9abc:16,er1)" +gdb_test "x" "and.b\t@\\(0x12345678(:32|),er3\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "and.b @(0x12345678:32,er3),@(0x9abcdef0:32,er1)" +gdb_test "x" "and.b\t@\\(0x12345678(:32|),er3\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "and.b @(0x12345678:32,er3),@(0x9abc:16,r2l.b)" +gdb_test "x" "and.b\t@\\(0x12345678(:32|),er3\\),@\\(0x9abc(:16|),r2.w\\)" \ + "and.b @(0x12345678:32,er3),@(0x9abc:16,r2.w)" +gdb_test "x" "and.b\t@\\(0x12345678(:32|),er3\\),@\\(0x9abc(:16|),er2.l\\)" \ + "and.b @(0x12345678:32,er3),@(0x9abc:16,er2.l)" +gdb_test "x" "and.b\t@\\(0x12345678(:32|),er3\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "and.b @(0x12345678:32,er3),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "and.b\t@\\(0x12345678(:32|),er3\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "and.b @(0x12345678:32,er3),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "and.b\t@\\(0x12345678(:32|),er3\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "and.b @(0x12345678:32,er3),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "and.b\t@\\(0x12345678(:32|),er3\\),@0x9abc(:16|)" \ + "and.b @(0x12345678:32,er3),@0x9abc:16" +gdb_test "x" "and.b\t@\\(0x12345678(:32|),er3\\),@0x9abcdef0(:32|)" \ + "and.b @(0x12345678:32,er3),@0x9abcdef0:32" +gdb_test "x" "and.b\t@\\(0x1234(:16|),r3l.b\\),@er1" \ + "and.b @(0x1234:16,r3l.b),@er1" +gdb_test "x" "and.b\t@\\(0x1234(:16|),r3l.b\\),@\\(0x3(:2|),er1\\)" \ + "and.b @(0x1234:16,r3l.b),@(0x3:2,er1)" +gdb_test "x" "and.b\t@\\(0x1234(:16|),r3l.b\\),@-er1" \ + "and.b @(0x1234:16,r3l.b),@-er1" +gdb_test "x" "and.b\t@\\(0x1234(:16|),r3l.b\\),@er1\\+" \ + "and.b @(0x1234:16,r3l.b),@er1+" +gdb_test "x" "and.b\t@\\(0x1234(:16|),r3l.b\\),@er1-" \ + "and.b @(0x1234:16,r3l.b),@er1-" +gdb_test "x" "and.b\t@\\(0x1234(:16|),r3l.b\\),@\\+er1" \ + "and.b @(0x1234:16,r3l.b),@+er1" +gdb_test "x" "and.b\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abc(:16|),er1\\)" \ + "and.b @(0x1234:16,r3l.b),@(0x9abc:16,er1)" +gdb_test "x" "and.b\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "and.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1)" +gdb_test "x" "and.b\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "and.b @(0x1234:16,r3l.b),@(0x9abc:16,r2l.b)" +gdb_test "x" "and.b\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abc(:16|),r2.w\\)" \ + "and.b @(0x1234:16,r3l.b),@(0x9abc:16,r2.w)" +gdb_test "x" "and.b\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abc(:16|),er2.l\\)" \ + "and.b @(0x1234:16,r3l.b),@(0x9abc:16,er2.l)" +gdb_test "x" "and.b\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "and.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "and.b\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "and.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "and.b\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "and.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "and.b\t@\\(0x1234(:16|),r3l.b\\),@0x9abc(:16|)" \ + "and.b @(0x1234:16,r3l.b),@0x9abc:16" +gdb_test "x" "and.b\t@\\(0x1234(:16|),r3l.b\\),@0x9abcdef0(:32|)" \ + "and.b @(0x1234:16,r3l.b),@0x9abcdef0:32" +gdb_test "x" "and.b\t@\\(0x1234(:16|),r3.w\\),@er1" \ + "and.b @(0x1234:16,r3.w),@er1" +gdb_test "x" "and.b\t@\\(0x1234(:16|),r3.w\\),@\\(0x3(:2|),er1\\)" \ + "and.b @(0x1234:16,r3.w),@(0x3:2,er1)" +gdb_test "x" "and.b\t@\\(0x1234(:16|),r3.w\\),@-er1" \ + "and.b @(0x1234:16,r3.w),@-er1" +gdb_test "x" "and.b\t@\\(0x1234(:16|),r3.w\\),@er1\\+" \ + "and.b @(0x1234:16,r3.w),@er1+" +gdb_test "x" "and.b\t@\\(0x1234(:16|),r3.w\\),@er1-" \ + "and.b @(0x1234:16,r3.w),@er1-" +gdb_test "x" "and.b\t@\\(0x1234(:16|),r3.w\\),@\\+er1" \ + "and.b @(0x1234:16,r3.w),@+er1" +gdb_test "x" "and.b\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abc(:16|),er1\\)" \ + "and.b @(0x1234:16,r3.w),@(0x9abc:16,er1)" +gdb_test "x" "and.b\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "and.b @(0x1234:16,r3.w),@(0x9abcdef0:32,er1)" +gdb_test "x" "and.b\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "and.b @(0x1234:16,r3.w),@(0x9abc:16,r2l.b)" +gdb_test "x" "and.b\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abc(:16|),r2.w\\)" \ + "and.b @(0x1234:16,r3.w),@(0x9abc:16,r2.w)" +gdb_test "x" "and.b\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abc(:16|),er2.l\\)" \ + "and.b @(0x1234:16,r3.w),@(0x9abc:16,er2.l)" +gdb_test "x" "and.b\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "and.b @(0x1234:16,r3.w),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "and.b\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "and.b @(0x1234:16,r3.w),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "and.b\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "and.b @(0x1234:16,r3.w),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "and.b\t@\\(0x1234(:16|),r3.w\\),@0x9abc(:16|)" \ + "and.b @(0x1234:16,r3.w),@0x9abc:16" +gdb_test "x" "and.b\t@\\(0x1234(:16|),r3.w\\),@0x9abcdef0(:32|)" \ + "and.b @(0x1234:16,r3.w),@0x9abcdef0:32" +gdb_test "x" "and.b\t@\\(0x1234(:16|),er3.l\\),@er1" \ + "and.b @(0x1234:16,er3.l),@er1" +gdb_test "x" "and.b\t@\\(0x1234(:16|),er3.l\\),@\\(0x3(:2|),er1\\)" \ + "and.b @(0x1234:16,er3.l),@(0x3:2,er1)" +gdb_test "x" "and.b\t@\\(0x1234(:16|),er3.l\\),@-er1" \ + "and.b @(0x1234:16,er3.l),@-er1" +gdb_test "x" "and.b\t@\\(0x1234(:16|),er3.l\\),@er1\\+" \ + "and.b @(0x1234:16,er3.l),@er1+" +gdb_test "x" "and.b\t@\\(0x1234(:16|),er3.l\\),@er1-" \ + "and.b @(0x1234:16,er3.l),@er1-" +gdb_test "x" "and.b\t@\\(0x1234(:16|),er3.l\\),@\\+er1" \ + "and.b @(0x1234:16,er3.l),@+er1" +gdb_test "x" "and.b\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abc(:16|),er1\\)" \ + "and.b @(0x1234:16,er3.l),@(0x9abc:16,er1)" +gdb_test "x" "and.b\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "and.b @(0x1234:16,er3.l),@(0x9abcdef0:32,er1)" +gdb_test "x" "and.b\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "and.b @(0x1234:16,er3.l),@(0x9abc:16,r2l.b)" +gdb_test "x" "and.b\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abc(:16|),r2.w\\)" \ + "and.b @(0x1234:16,er3.l),@(0x9abc:16,r2.w)" +gdb_test "x" "and.b\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abc(:16|),er2.l\\)" \ + "and.b @(0x1234:16,er3.l),@(0x9abc:16,er2.l)" +gdb_test "x" "and.b\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "and.b @(0x1234:16,er3.l),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "and.b\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "and.b @(0x1234:16,er3.l),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "and.b\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "and.b @(0x1234:16,er3.l),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "and.b\t@\\(0x1234(:16|),er3.l\\),@0x9abc(:16|)" \ + "and.b @(0x1234:16,er3.l),@0x9abc:16" +gdb_test "x" "and.b\t@\\(0x1234(:16|),er3.l\\),@0x9abcdef0(:32|)" \ + "and.b @(0x1234:16,er3.l),@0x9abcdef0:32" +gdb_test "x" "and.b\t@\\(0x12345678(:32|),r3l.b\\),@er1" \ + "and.b @(0x12345678:32,r3l.b),@er1" +gdb_test "x" "and.b\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x3(:2|),er1\\)" \ + "and.b @(0x12345678:32,r3l.b),@(0x3:2,er1)" +gdb_test "x" "and.b\t@\\(0x12345678(:32|),r3l.b\\),@-er1" \ + "and.b @(0x12345678:32,r3l.b),@-er1" +gdb_test "x" "and.b\t@\\(0x12345678(:32|),r3l.b\\),@er1\\+" \ + "and.b @(0x12345678:32,r3l.b),@er1+" +gdb_test "x" "and.b\t@\\(0x12345678(:32|),r3l.b\\),@er1-" \ + "and.b @(0x12345678:32,r3l.b),@er1-" +gdb_test "x" "and.b\t@\\(0x12345678(:32|),r3l.b\\),@\\+er1" \ + "and.b @(0x12345678:32,r3l.b),@+er1" +gdb_test "x" "and.b\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abc(:16|),er1\\)" \ + "and.b @(0x12345678:32,r3l.b),@(0x9abc:16,er1)" +gdb_test "x" "and.b\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "and.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1)" +gdb_test "x" "and.b\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "and.b @(0x12345678:32,r3l.b),@(0x9abc:16,r2l.b)" +gdb_test "x" "and.b\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abc(:16|),r2.w\\)" \ + "and.b @(0x12345678:32,r3l.b),@(0x9abc:16,r2.w)" +gdb_test "x" "and.b\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abc(:16|),er2.l\\)" \ + "and.b @(0x12345678:32,r3l.b),@(0x9abc:16,er2.l)" +gdb_test "x" "and.b\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "and.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "and.b\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "and.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "and.b\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "and.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "and.b\t@\\(0x12345678(:32|),r3l.b\\),@0x9abc(:16|)" \ + "and.b @(0x12345678:32,r3l.b),@0x9abc:16" +gdb_test "x" "and.b\t@\\(0x12345678(:32|),r3l.b\\),@0x9abcdef0(:32|)" \ + "and.b @(0x12345678:32,r3l.b),@0x9abcdef0:32" +gdb_test "x" "and.b\t@\\(0x12345678(:32|),r3.w\\),@er1" \ + "and.b @(0x12345678:32,r3.w),@er1" +gdb_test "x" "and.b\t@\\(0x12345678(:32|),r3.w\\),@\\(0x3(:2|),er1\\)" \ + "and.b @(0x12345678:32,r3.w),@(0x3:2,er1)" +gdb_test "x" "and.b\t@\\(0x12345678(:32|),r3.w\\),@-er1" \ + "and.b @(0x12345678:32,r3.w),@-er1" +gdb_test "x" "and.b\t@\\(0x12345678(:32|),r3.w\\),@er1\\+" \ + "and.b @(0x12345678:32,r3.w),@er1+" +gdb_test "x" "and.b\t@\\(0x12345678(:32|),r3.w\\),@er1-" \ + "and.b @(0x12345678:32,r3.w),@er1-" +gdb_test "x" "and.b\t@\\(0x12345678(:32|),r3.w\\),@\\+er1" \ + "and.b @(0x12345678:32,r3.w),@+er1" +gdb_test "x" "and.b\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abc(:16|),er1\\)" \ + "and.b @(0x12345678:32,r3.w),@(0x9abc:16,er1)" +gdb_test "x" "and.b\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "and.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1)" +gdb_test "x" "and.b\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "and.b @(0x12345678:32,r3.w),@(0x9abc:16,r2l.b)" +gdb_test "x" "and.b\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abc(:16|),r2.w\\)" \ + "and.b @(0x12345678:32,r3.w),@(0x9abc:16,r2.w)" +gdb_test "x" "and.b\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abc(:16|),er2.l\\)" \ + "and.b @(0x12345678:32,r3.w),@(0x9abc:16,er2.l)" +gdb_test "x" "and.b\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "and.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "and.b\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "and.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "and.b\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "and.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "and.b\t@\\(0x12345678(:32|),r3.w\\),@0x9abc(:16|)" \ + "and.b @(0x12345678:32,r3.w),@0x9abc:16" +gdb_test "x" "and.b\t@\\(0x12345678(:32|),r3.w\\),@0x9abcdef0(:32|)" \ + "and.b @(0x12345678:32,r3.w),@0x9abcdef0:32" +gdb_test "x" "and.b\t@\\(0x12345678(:32|),er3.l\\),@er1" \ + "and.b @(0x12345678:32,er3.l),@er1" +gdb_test "x" "and.b\t@\\(0x12345678(:32|),er3.l\\),@\\(0x3(:2|),er1\\)" \ + "and.b @(0x12345678:32,er3.l),@(0x3:2,er1)" +gdb_test "x" "and.b\t@\\(0x12345678(:32|),er3.l\\),@-er1" \ + "and.b @(0x12345678:32,er3.l),@-er1" +gdb_test "x" "and.b\t@\\(0x12345678(:32|),er3.l\\),@er1\\+" \ + "and.b @(0x12345678:32,er3.l),@er1+" +gdb_test "x" "and.b\t@\\(0x12345678(:32|),er3.l\\),@er1-" \ + "and.b @(0x12345678:32,er3.l),@er1-" +gdb_test "x" "and.b\t@\\(0x12345678(:32|),er3.l\\),@\\+er1" \ + "and.b @(0x12345678:32,er3.l),@+er1" +gdb_test "x" "and.b\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abc(:16|),er1\\)" \ + "and.b @(0x12345678:32,er3.l),@(0x9abc:16,er1)" +gdb_test "x" "and.b\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "and.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1)" +gdb_test "x" "and.b\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "and.b @(0x12345678:32,er3.l),@(0x9abc:16,r2l.b)" +gdb_test "x" "and.b\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abc(:16|),r2.w\\)" \ + "and.b @(0x12345678:32,er3.l),@(0x9abc:16,r2.w)" +gdb_test "x" "and.b\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abc(:16|),er2.l\\)" \ + "and.b @(0x12345678:32,er3.l),@(0x9abc:16,er2.l)" +gdb_test "x" "and.b\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "and.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "and.b\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "and.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "and.b\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "and.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "and.b\t@\\(0x12345678(:32|),er3.l\\),@0x9abc(:16|)" \ + "and.b @(0x12345678:32,er3.l),@0x9abc:16" +gdb_test "x" "and.b\t@\\(0x12345678(:32|),er3.l\\),@0x9abcdef0(:32|)" \ + "and.b @(0x12345678:32,er3.l),@0x9abcdef0:32" +gdb_test "x" "and.b\t@0x1234(:16|),@er1" \ + "and.b @0x1234:16,@er1" +gdb_test "x" "and.b\t@0x1234(:16|),@\\(0x3(:2|),er1\\)" \ + "and.b @0x1234:16,@(0x3:2,er1)" +gdb_test "x" "and.b\t@0x1234(:16|),@-er1" \ + "and.b @0x1234:16,@-er1" +gdb_test "x" "and.b\t@0x1234(:16|),@er1\\+" \ + "and.b @0x1234:16,@er1+" +gdb_test "x" "and.b\t@0x1234(:16|),@er1-" \ + "and.b @0x1234:16,@er1-" +gdb_test "x" "and.b\t@0x1234(:16|),@\\+er1" \ + "and.b @0x1234:16,@+er1" +gdb_test "x" "and.b\t@0x1234(:16|),@\\(0x9abc(:16|),er1\\)" \ + "and.b @0x1234:16,@(0x9abc:16,er1)" +gdb_test "x" "and.b\t@0x1234(:16|),@\\(0x9abcdef0(:32|),er1\\)" \ + "and.b @0x1234:16,@(0x9abcdef0:32,er1)" +gdb_test "x" "and.b\t@0x1234(:16|),@\\(0x9abc(:16|),r2l.b\\)" \ + "and.b @0x1234:16,@(0x9abc:16,r2l.b)" +gdb_test "x" "and.b\t@0x1234(:16|),@\\(0x9abc(:16|),r2.w\\)" \ + "and.b @0x1234:16,@(0x9abc:16,r2.w)" +gdb_test "x" "and.b\t@0x1234(:16|),@\\(0x9abc(:16|),er2.l\\)" \ + "and.b @0x1234:16,@(0x9abc:16,er2.l)" +gdb_test "x" "and.b\t@0x1234(:16|),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "and.b @0x1234:16,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "and.b\t@0x1234(:16|),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "and.b @0x1234:16,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "and.b\t@0x1234(:16|),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "and.b @0x1234:16,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "and.b\t@0x1234(:16|),@0x9abc(:16|)" \ + "and.b @0x1234:16,@0x9abc:16" +gdb_test "x" "and.b\t@0x1234(:16|),@0x9abcdef0(:32|)" \ + "and.b @0x1234:16,@0x9abcdef0:32" +gdb_test "x" "and.b\t@0x12345678(:32|),@er1" \ + "and.b @0x12345678:32,@er1" +gdb_test "x" "and.b\t@0x12345678(:32|),@\\(0x3(:2|),er1\\)" \ + "and.b @0x12345678:32,@(0x3:2,er1)" +gdb_test "x" "and.b\t@0x12345678(:32|),@-er1" \ + "and.b @0x12345678:32,@-er1" +gdb_test "x" "and.b\t@0x12345678(:32|),@er1\\+" \ + "and.b @0x12345678:32,@er1+" +gdb_test "x" "and.b\t@0x12345678(:32|),@er1-" \ + "and.b @0x12345678:32,@er1-" +gdb_test "x" "and.b\t@0x12345678(:32|),@\\+er1" \ + "and.b @0x12345678:32,@+er1" +gdb_test "x" "and.b\t@0x12345678(:32|),@\\(0x9abc(:16|),er1\\)" \ + "and.b @0x12345678:32,@(0x9abc:16,er1)" +gdb_test "x" "and.b\t@0x12345678(:32|),@\\(0x9abcdef0(:32|),er1\\)" \ + "and.b @0x12345678:32,@(0x9abcdef0:32,er1)" +gdb_test "x" "and.b\t@0x12345678(:32|),@\\(0x9abc(:16|),r2l.b\\)" \ + "and.b @0x12345678:32,@(0x9abc:16,r2l.b)" +gdb_test "x" "and.b\t@0x12345678(:32|),@\\(0x9abc(:16|),r2.w\\)" \ + "and.b @0x12345678:32,@(0x9abc:16,r2.w)" +gdb_test "x" "and.b\t@0x12345678(:32|),@\\(0x9abc(:16|),er2.l\\)" \ + "and.b @0x12345678:32,@(0x9abc:16,er2.l)" +gdb_test "x" "and.b\t@0x12345678(:32|),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "and.b @0x12345678:32,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "and.b\t@0x12345678(:32|),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "and.b @0x12345678:32,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "and.b\t@0x12345678(:32|),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "and.b @0x12345678:32,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "and.b\t@0x12345678(:32|),@0x9abc(:16|)" \ + "and.b @0x12345678:32,@0x9abc:16" +gdb_test "x" "and.b\t@0x12345678(:32|),@0x9abcdef0(:32|)" \ + "and.b @0x12345678:32,@0x9abcdef0:32" +gdb_test "x" "and.w\t#0x1234(:16|),r1" \ + "and.w #0x1234:16,r1" +gdb_test "x" "and.w\t#0x1234(:16|),@er1" \ + "and.w #0x1234:16,@er1" +gdb_test "x" "and.w\t#0x1234(:16|),@\\(0x6(:2|),er1\\)" \ + "and.w #0x1234:16,@(0x6:2,er1)" +gdb_test "x" "and.w\t#0x1234(:16|),@er1\\+" \ + "and.w #0x1234:16,@er1+" +gdb_test "x" "and.w\t#0x1234(:16|),@-er1" \ + "and.w #0x1234:16,@-er1" +gdb_test "x" "and.w\t#0x1234(:16|),@\\+er1" \ + "and.w #0x1234:16,@+er1" +gdb_test "x" "and.w\t#0x1234(:16|),@er1-" \ + "and.w #0x1234:16,@er1-" +gdb_test "x" "and.w\t#0x1234(:16|),@\\(0x9abc(:16|),er1\\)" \ + "and.w #0x1234:16,@(0x9abc:16,er1)" +gdb_test "x" "and.w\t#0x1234(:16|),@\\(0x9abcdef0(:32|),er1\\)" \ + "and.w #0x1234:16,@(0x9abcdef0:32,er1)" +gdb_test "x" "and.w\t#0x1234(:16|),@\\(0x9abc(:16|),r2l.b\\)" \ + "and.w #0x1234:16,@(0x9abc:16,r2l.b)" +gdb_test "x" "and.w\t#0x1234(:16|),@\\(0x9abc(:16|),r2.w\\)" \ + "and.w #0x1234:16,@(0x9abc:16,r2.w)" +gdb_test "x" "and.w\t#0x1234(:16|),@\\(0x9abc(:16|),er2.l\\)" \ + "and.w #0x1234:16,@(0x9abc:16,er2.l)" +gdb_test "x" "and.w\t#0x1234(:16|),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "and.w #0x1234:16,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "and.w\t#0x1234(:16|),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "and.w #0x1234:16,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "and.w\t#0x1234(:16|),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "and.w #0x1234:16,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "and.w\t#0x1234(:16|),@0x9abc(:16|)" \ + "and.w #0x1234:16,@0x9abc:16" +gdb_test "x" "and.w\t#0x1234(:16|),@0x9abcdef0(:32|)" \ + "and.w #0x1234:16,@0x9abcdef0:32" +gdb_test "x" "and.w\tr3,r1" \ + "and.w r3,r1" +gdb_test "x" "and.w\tr3,@er1" \ + "and.w r3,@er1" +gdb_test "x" "and.w\tr3,@\\(0x6(:2|),er1\\)" \ + "and.w r3,@(0x6:2,er1)" +gdb_test "x" "and.w\tr3,@er1\\+" \ + "and.w r3,@er1+" +gdb_test "x" "and.w\tr3,@-er1" \ + "and.w r3,@-er1" +gdb_test "x" "and.w\tr3,@\\+er1" \ + "and.w r3,@+er1" +gdb_test "x" "and.w\tr3,@er1-" \ + "and.w r3,@er1-" +gdb_test "x" "and.w\tr3,@\\(0x1234(:16|),er1\\)" \ + "and.w r3,@(0x1234:16,er1)" +gdb_test "x" "and.w\tr3,@\\(0x12345678(:32|),er1\\)" \ + "and.w r3,@(0x12345678:32,er1)" +gdb_test "x" "and.w\tr3,@\\(0x1234(:16|),r2l.b\\)" \ + "and.w r3,@(0x1234:16,r2l.b)" +gdb_test "x" "and.w\tr3,@\\(0x1234(:16|),r2.w\\)" \ + "and.w r3,@(0x1234:16,r2.w)" +gdb_test "x" "and.w\tr3,@\\(0x1234(:16|),er2.l\\)" \ + "and.w r3,@(0x1234:16,er2.l)" +gdb_test "x" "and.w\tr3,@\\(0x12345678(:32|),r2l.b\\)" \ + "and.w r3,@(0x12345678:32,r2l.b)" +gdb_test "x" "and.w\tr3,@\\(0x12345678(:32|),r2.w\\)" \ + "and.w r3,@(0x12345678:32,r2.w)" +gdb_test "x" "and.w\tr3,@\\(0x12345678(:32|),er2.l\\)" \ + "and.w r3,@(0x12345678:32,er2.l)" +gdb_test "x" "and.w\tr3,@0x1234(:16|)" \ + "and.w r3,@0x1234:16" +gdb_test "x" "and.w\tr3,@0x12345678(:32|)" \ + "and.w r3,@0x12345678:32" +gdb_test "x" "and.w\t@er3,r1" \ + "and.w @er3,r1" +gdb_test "x" "and.w\t@\\(0x6(:2|),er3\\),r1" \ + "and.w @(0x6:2,er3),r1" +gdb_test "x" "and.w\t@er3\\+,r1" \ + "and.w @er3+,r1" +gdb_test "x" "and.w\t@-er3,r1" \ + "and.w @-er3,r1" +gdb_test "x" "and.w\t@\\+er3,r1" \ + "and.w @+er3,r1" +gdb_test "x" "and.w\t@er3-,r1" \ + "and.w @er3-,r1" +gdb_test "x" "and.w\t@\\(0x1234(:16|),er1\\),r1" \ + "and.w @(0x1234:16,er1),r1" +gdb_test "x" "and.w\t@\\(0x12345678(:32|),er1\\),r1" \ + "and.w @(0x12345678:32,er1),r1" +gdb_test "x" "and.w\t@\\(0x1234(:16|),r2l.b\\),r1" \ + "and.w @(0x1234:16,r2l.b),r1" +gdb_test "x" "and.w\t@\\(0x1234(:16|),r2.w\\),r1" \ + "and.w @(0x1234:16,r2.w),r1" +gdb_test "x" "and.w\t@\\(0x1234(:16|),er2.l\\),r1" \ + "and.w @(0x1234:16,er2.l),r1" +gdb_test "x" "and.w\t@\\(0x12345678(:32|),r2l.b\\),r1" \ + "and.w @(0x12345678:32,r2l.b),r1" +gdb_test "x" "and.w\t@\\(0x12345678(:32|),r2.w\\),r1" \ + "and.w @(0x12345678:32,r2.w),r1" +gdb_test "x" "and.w\t@\\(0x12345678(:32|),er2.l\\),r1" \ + "and.w @(0x12345678:32,er2.l),r1" +gdb_test "x" "and.w\t@0x1234(:16|),r1" \ + "and.w @0x1234:16,r1" +gdb_test "x" "and.w\t@0x12345678(:32|),r1" \ + "and.w @0x12345678:32,r1" +gdb_test "x" "and.w\t@er3,@er1" \ + "and.w @er3,@er1" +gdb_test "x" "and.w\t@er3,@\\(0x6(:2|),er1\\)" \ + "and.w @er3,@(0x6:2,er1)" +gdb_test "x" "and.w\t@er3,@-er1" \ + "and.w @er3,@-er1" +gdb_test "x" "and.w\t@er3,@er1\\+" \ + "and.w @er3,@er1+" +gdb_test "x" "and.w\t@er3,@er1-" \ + "and.w @er3,@er1-" +gdb_test "x" "and.w\t@er3,@\\+er1" \ + "and.w @er3,@+er1" +gdb_test "x" "and.w\t@er3,@\\(0x9abc(:16|),er1\\)" \ + "and.w @er3,@(0x9abc:16,er1)" +gdb_test "x" "and.w\t@er3,@\\(0x9abcdef0(:32|),er1\\)" \ + "and.w @er3,@(0x9abcdef0:32,er1)" +gdb_test "x" "and.w\t@er3,@\\(0x9abc(:16|),r2l.b\\)" \ + "and.w @er3,@(0x9abc:16,r2l.b)" +gdb_test "x" "and.w\t@er3,@\\(0x9abc(:16|),r2.w\\)" \ + "and.w @er3,@(0x9abc:16,r2.w)" +gdb_test "x" "and.w\t@er3,@\\(0x9abc(:16|),er2.l\\)" \ + "and.w @er3,@(0x9abc:16,er2.l)" +gdb_test "x" "and.w\t@er3,@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "and.w @er3,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "and.w\t@er3,@\\(0x9abcdef0(:32|),r2.w\\)" \ + "and.w @er3,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "and.w\t@er3,@\\(0x9abcdef0(:32|),er2.l\\)" \ + "and.w @er3,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "and.w\t@er3,@0x9abc(:16|)" \ + "and.w @er3,@0x9abc:16" +gdb_test "x" "and.w\t@er3,@0x9abcdef0(:32|)" \ + "and.w @er3,@0x9abcdef0:32" +gdb_test "x" "and.w\t@-er3,@er1" \ + "and.w @-er3,@er1" +gdb_test "x" "and.w\t@-er3,@\\(0x6(:2|),er1\\)" \ + "and.w @-er3,@(0x6:2,er1)" +gdb_test "x" "and.w\t@-er3,@-er1" \ + "and.w @-er3,@-er1" +gdb_test "x" "and.w\t@-er3,@er1\\+" \ + "and.w @-er3,@er1+" +gdb_test "x" "and.w\t@-er3,@er1-" \ + "and.w @-er3,@er1-" +gdb_test "x" "and.w\t@-er3,@\\+er1" \ + "and.w @-er3,@+er1" +gdb_test "x" "and.w\t@-er3,@\\(0x9abc(:16|),er1\\)" \ + "and.w @-er3,@(0x9abc:16,er1)" +gdb_test "x" "and.w\t@-er3,@\\(0x9abcdef0(:32|),er1\\)" \ + "and.w @-er3,@(0x9abcdef0:32,er1)" +gdb_test "x" "and.w\t@-er3,@\\(0x9abc(:16|),r2l.b\\)" \ + "and.w @-er3,@(0x9abc:16,r2l.b)" +gdb_test "x" "and.w\t@-er3,@\\(0x9abc(:16|),r2.w\\)" \ + "and.w @-er3,@(0x9abc:16,r2.w)" +gdb_test "x" "and.w\t@-er3,@\\(0x9abc(:16|),er2.l\\)" \ + "and.w @-er3,@(0x9abc:16,er2.l)" +gdb_test "x" "and.w\t@-er3,@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "and.w @-er3,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "and.w\t@-er3,@\\(0x9abcdef0(:32|),r2.w\\)" \ + "and.w @-er3,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "and.w\t@-er3,@\\(0x9abcdef0(:32|),er2.l\\)" \ + "and.w @-er3,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "and.w\t@-er3,@0x9abc(:16|)" \ + "and.w @-er3,@0x9abc:16" +gdb_test "x" "and.w\t@-er3,@0x9abcdef0(:32|)" \ + "and.w @-er3,@0x9abcdef0:32" +gdb_test "x" "and.w\t@er3\\+,@er1" \ + "and.w @er3+,@er1" +gdb_test "x" "and.w\t@er3\\+,@\\(0x6(:2|),er1\\)" \ + "and.w @er3+,@(0x6:2,er1)" +gdb_test "x" "and.w\t@er3\\+,@-er1" \ + "and.w @er3+,@-er1" +gdb_test "x" "and.w\t@er3\\+,@er1\\+" \ + "and.w @er3+,@er1+" +gdb_test "x" "and.w\t@er3\\+,@er1-" \ + "and.w @er3+,@er1-" +gdb_test "x" "and.w\t@er3\\+,@\\+er1" \ + "and.w @er3+,@+er1" +gdb_test "x" "and.w\t@er3\\+,@\\(0x9abc(:16|),er1\\)" \ + "and.w @er3+,@(0x9abc:16,er1)" +gdb_test "x" "and.w\t@er3\\+,@\\(0x9abcdef0(:32|),er1\\)" \ + "and.w @er3+,@(0x9abcdef0:32,er1)" +gdb_test "x" "and.w\t@er3\\+,@\\(0x9abc(:16|),r2l.b\\)" \ + "and.w @er3+,@(0x9abc:16,r2l.b)" +gdb_test "x" "and.w\t@er3\\+,@\\(0x9abc(:16|),r2.w\\)" \ + "and.w @er3+,@(0x9abc:16,r2.w)" +gdb_test "x" "and.w\t@er3\\+,@\\(0x9abc(:16|),er2.l\\)" \ + "and.w @er3+,@(0x9abc:16,er2.l)" +gdb_test "x" "and.w\t@er3\\+,@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "and.w @er3+,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "and.w\t@er3\\+,@\\(0x9abcdef0(:32|),r2.w\\)" \ + "and.w @er3+,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "and.w\t@er3\\+,@\\(0x9abcdef0(:32|),er2.l\\)" \ + "and.w @er3+,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "and.w\t@er3\\+,@0x9abc(:16|)" \ + "and.w @er3+,@0x9abc:16" +gdb_test "x" "and.w\t@er3\\+,@0x9abcdef0(:32|)" \ + "and.w @er3+,@0x9abcdef0:32" +gdb_test "x" "and.w\t@er3-,@er1" \ + "and.w @er3-,@er1" +gdb_test "x" "and.w\t@er3-,@\\(0x6(:2|),er1\\)" \ + "and.w @er3-,@(0x6:2,er1)" +gdb_test "x" "and.w\t@er3-,@-er1" \ + "and.w @er3-,@-er1" +gdb_test "x" "and.w\t@er3-,@er1\\+" \ + "and.w @er3-,@er1+" +gdb_test "x" "and.w\t@er3-,@er1-" \ + "and.w @er3-,@er1-" +gdb_test "x" "and.w\t@er3-,@\\+er1" \ + "and.w @er3-,@+er1" +gdb_test "x" "and.w\t@er3-,@\\(0x9abc(:16|),er1\\)" \ + "and.w @er3-,@(0x9abc:16,er1)" +gdb_test "x" "and.w\t@er3-,@\\(0x9abcdef0(:32|),er1\\)" \ + "and.w @er3-,@(0x9abcdef0:32,er1)" +gdb_test "x" "and.w\t@er3-,@\\(0x9abc(:16|),r2l.b\\)" \ + "and.w @er3-,@(0x9abc:16,r2l.b)" +gdb_test "x" "and.w\t@er3-,@\\(0x9abc(:16|),r2.w\\)" \ + "and.w @er3-,@(0x9abc:16,r2.w)" +gdb_test "x" "and.w\t@er3-,@\\(0x9abc(:16|),er2.l\\)" \ + "and.w @er3-,@(0x9abc:16,er2.l)" +gdb_test "x" "and.w\t@er3-,@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "and.w @er3-,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "and.w\t@er3-,@\\(0x9abcdef0(:32|),r2.w\\)" \ + "and.w @er3-,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "and.w\t@er3-,@\\(0x9abcdef0(:32|),er2.l\\)" \ + "and.w @er3-,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "and.w\t@er3-,@0x9abc(:16|)" \ + "and.w @er3-,@0x9abc:16" +gdb_test "x" "and.w\t@er3-,@0x9abcdef0(:32|)" \ + "and.w @er3-,@0x9abcdef0:32" +gdb_test "x" "and.w\t@\\+er3,@er1" \ + "and.w @+er3,@er1" +gdb_test "x" "and.w\t@\\+er3,@\\(0x6(:2|),er1\\)" \ + "and.w @+er3,@(0x6:2,er1)" +gdb_test "x" "and.w\t@\\+er3,@-er1" \ + "and.w @+er3,@-er1" +gdb_test "x" "and.w\t@\\+er3,@er1\\+" \ + "and.w @+er3,@er1+" +gdb_test "x" "and.w\t@\\+er3,@er1-" \ + "and.w @+er3,@er1-" +gdb_test "x" "and.w\t@\\+er3,@\\+er1" \ + "and.w @+er3,@+er1" +gdb_test "x" "and.w\t@\\+er3,@\\(0x9abc(:16|),er1\\)" \ + "and.w @+er3,@(0x9abc:16,er1)" +gdb_test "x" "and.w\t@\\+er3,@\\(0x9abcdef0(:32|),er1\\)" \ + "and.w @+er3,@(0x9abcdef0:32,er1)" +gdb_test "x" "and.w\t@\\+er3,@\\(0x9abc(:16|),r2l.b\\)" \ + "and.w @+er3,@(0x9abc:16,r2l.b)" +gdb_test "x" "and.w\t@\\+er3,@\\(0x9abc(:16|),r2.w\\)" \ + "and.w @+er3,@(0x9abc:16,r2.w)" +gdb_test "x" "and.w\t@\\+er3,@\\(0x9abc(:16|),er2.l\\)" \ + "and.w @+er3,@(0x9abc:16,er2.l)" +gdb_test "x" "and.w\t@\\+er3,@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "and.w @+er3,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "and.w\t@\\+er3,@\\(0x9abcdef0(:32|),r2.w\\)" \ + "and.w @+er3,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "and.w\t@\\+er3,@\\(0x9abcdef0(:32|),er2.l\\)" \ + "and.w @+er3,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "and.w\t@\\+er3,@0x9abc(:16|)" \ + "and.w @+er3,@0x9abc:16" +gdb_test "x" "and.w\t@\\+er3,@0x9abcdef0(:32|)" \ + "and.w @+er3,@0x9abcdef0:32" +gdb_test "x" "and.w\t@\\(0x1234(:16|),er3\\),@er1" \ + "and.w @(0x1234:16,er3),@er1" +gdb_test "x" "and.w\t@\\(0x1234(:16|),er3\\),@\\(0x6(:2|),er1\\)" \ + "and.w @(0x1234:16,er3),@(0x6:2,er1)" +gdb_test "x" "and.w\t@\\(0x1234(:16|),er3\\),@-er1" \ + "and.w @(0x1234:16,er3),@-er1" +gdb_test "x" "and.w\t@\\(0x1234(:16|),er3\\),@er1\\+" \ + "and.w @(0x1234:16,er3),@er1+" +gdb_test "x" "and.w\t@\\(0x1234(:16|),er3\\),@er1-" \ + "and.w @(0x1234:16,er3),@er1-" +gdb_test "x" "and.w\t@\\(0x1234(:16|),er3\\),@\\+er1" \ + "and.w @(0x1234:16,er3),@+er1" +gdb_test "x" "and.w\t@\\(0x1234(:16|),er3\\),@\\(0x9abc(:16|),er1\\)" \ + "and.w @(0x1234:16,er3),@(0x9abc:16,er1)" +gdb_test "x" "and.w\t@\\(0x1234(:16|),er3\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "and.w @(0x1234:16,er3),@(0x9abcdef0:32,er1)" +gdb_test "x" "and.w\t@\\(0x1234(:16|),er3\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "and.w @(0x1234:16,er3),@(0x9abc:16,r2l.b)" +gdb_test "x" "and.w\t@\\(0x1234(:16|),er3\\),@\\(0x9abc(:16|),r2.w\\)" \ + "and.w @(0x1234:16,er3),@(0x9abc:16,r2.w)" +gdb_test "x" "and.w\t@\\(0x1234(:16|),er3\\),@\\(0x9abc(:16|),er2.l\\)" \ + "and.w @(0x1234:16,er3),@(0x9abc:16,er2.l)" +gdb_test "x" "and.w\t@\\(0x1234(:16|),er3\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "and.w @(0x1234:16,er3),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "and.w\t@\\(0x1234(:16|),er3\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "and.w @(0x1234:16,er3),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "and.w\t@\\(0x1234(:16|),er3\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "and.w @(0x1234:16,er3),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "and.w\t@\\(0x1234(:16|),er3\\),@0x9abc(:16|)" \ + "and.w @(0x1234:16,er3),@0x9abc:16" +gdb_test "x" "and.w\t@\\(0x1234(:16|),er3\\),@0x9abcdef0(:32|)" \ + "and.w @(0x1234:16,er3),@0x9abcdef0:32" +gdb_test "x" "and.w\t@\\(0x12345678(:32|),er3\\),@er1" \ + "and.w @(0x12345678:32,er3),@er1" +gdb_test "x" "and.w\t@\\(0x12345678(:32|),er3\\),@\\(0x6(:2|),er1\\)" \ + "and.w @(0x12345678:32,er3),@(0x6:2,er1)" +gdb_test "x" "and.w\t@\\(0x12345678(:32|),er3\\),@-er1" \ + "and.w @(0x12345678:32,er3),@-er1" +gdb_test "x" "and.w\t@\\(0x12345678(:32|),er3\\),@er1\\+" \ + "and.w @(0x12345678:32,er3),@er1+" +gdb_test "x" "and.w\t@\\(0x12345678(:32|),er3\\),@er1-" \ + "and.w @(0x12345678:32,er3),@er1-" +gdb_test "x" "and.w\t@\\(0x12345678(:32|),er3\\),@\\+er1" \ + "and.w @(0x12345678:32,er3),@+er1" +gdb_test "x" "and.w\t@\\(0x12345678(:32|),er3\\),@\\(0x9abc(:16|),er1\\)" \ + "and.w @(0x12345678:32,er3),@(0x9abc:16,er1)" +gdb_test "x" "and.w\t@\\(0x12345678(:32|),er3\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "and.w @(0x12345678:32,er3),@(0x9abcdef0:32,er1)" +gdb_test "x" "and.w\t@\\(0x12345678(:32|),er3\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "and.w @(0x12345678:32,er3),@(0x9abc:16,r2l.b)" +gdb_test "x" "and.w\t@\\(0x12345678(:32|),er3\\),@\\(0x9abc(:16|),r2.w\\)" \ + "and.w @(0x12345678:32,er3),@(0x9abc:16,r2.w)" +gdb_test "x" "and.w\t@\\(0x12345678(:32|),er3\\),@\\(0x9abc(:16|),er2.l\\)" \ + "and.w @(0x12345678:32,er3),@(0x9abc:16,er2.l)" +gdb_test "x" "and.w\t@\\(0x12345678(:32|),er3\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "and.w @(0x12345678:32,er3),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "and.w\t@\\(0x12345678(:32|),er3\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "and.w @(0x12345678:32,er3),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "and.w\t@\\(0x12345678(:32|),er3\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "and.w @(0x12345678:32,er3),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "and.w\t@\\(0x12345678(:32|),er3\\),@0x9abc(:16|)" \ + "and.w @(0x12345678:32,er3),@0x9abc:16" +gdb_test "x" "and.w\t@\\(0x12345678(:32|),er3\\),@0x9abcdef0(:32|)" \ + "and.w @(0x12345678:32,er3),@0x9abcdef0:32" +gdb_test "x" "and.w\t@\\(0x1234(:16|),r3l.b\\),@er1" \ + "and.w @(0x1234:16,r3l.b),@er1" +gdb_test "x" "and.w\t@\\(0x1234(:16|),r3l.b\\),@\\(0x6(:2|),er1\\)" \ + "and.w @(0x1234:16,r3l.b),@(0x6:2,er1)" +gdb_test "x" "and.w\t@\\(0x1234(:16|),r3l.b\\),@-er1" \ + "and.w @(0x1234:16,r3l.b),@-er1" +gdb_test "x" "and.w\t@\\(0x1234(:16|),r3l.b\\),@er1\\+" \ + "and.w @(0x1234:16,r3l.b),@er1+" +gdb_test "x" "and.w\t@\\(0x1234(:16|),r3l.b\\),@er1-" \ + "and.w @(0x1234:16,r3l.b),@er1-" +gdb_test "x" "and.w\t@\\(0x1234(:16|),r3l.b\\),@\\+er1" \ + "and.w @(0x1234:16,r3l.b),@+er1" +gdb_test "x" "and.w\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abc(:16|),er1\\)" \ + "and.w @(0x1234:16,r3l.b),@(0x9abc:16,er1)" +gdb_test "x" "and.w\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "and.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1)" +gdb_test "x" "and.w\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "and.w @(0x1234:16,r3l.b),@(0x9abc:16,r2l.b)" +gdb_test "x" "and.w\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abc(:16|),r2.w\\)" \ + "and.w @(0x1234:16,r3l.b),@(0x9abc:16,r2.w)" +gdb_test "x" "and.w\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abc(:16|),er2.l\\)" \ + "and.w @(0x1234:16,r3l.b),@(0x9abc:16,er2.l)" +gdb_test "x" "and.w\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "and.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "and.w\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "and.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "and.w\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "and.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "and.w\t@\\(0x1234(:16|),r3l.b\\),@0x9abc(:16|)" \ + "and.w @(0x1234:16,r3l.b),@0x9abc:16" +gdb_test "x" "and.w\t@\\(0x1234(:16|),r3l.b\\),@0x9abcdef0(:32|)" \ + "and.w @(0x1234:16,r3l.b),@0x9abcdef0:32" +gdb_test "x" "and.w\t@\\(0x1234(:16|),r3.w\\),@er1" \ + "and.w @(0x1234:16,r3.w),@er1" +gdb_test "x" "and.w\t@\\(0x1234(:16|),r3.w\\),@\\(0x6(:2|),er1\\)" \ + "and.w @(0x1234:16,r3.w),@(0x6:2,er1)" +gdb_test "x" "and.w\t@\\(0x1234(:16|),r3.w\\),@-er1" \ + "and.w @(0x1234:16,r3.w),@-er1" +gdb_test "x" "and.w\t@\\(0x1234(:16|),r3.w\\),@er1\\+" \ + "and.w @(0x1234:16,r3.w),@er1+" +gdb_test "x" "and.w\t@\\(0x1234(:16|),r3.w\\),@er1-" \ + "and.w @(0x1234:16,r3.w),@er1-" +gdb_test "x" "and.w\t@\\(0x1234(:16|),r3.w\\),@\\+er1" \ + "and.w @(0x1234:16,r3.w),@+er1" +gdb_test "x" "and.w\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abc(:16|),er1\\)" \ + "and.w @(0x1234:16,r3.w),@(0x9abc:16,er1)" +gdb_test "x" "and.w\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "and.w @(0x1234:16,r3.w),@(0x9abcdef0:32,er1)" +gdb_test "x" "and.w\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "and.w @(0x1234:16,r3.w),@(0x9abc:16,r2l.b)" +gdb_test "x" "and.w\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abc(:16|),r2.w\\)" \ + "and.w @(0x1234:16,r3.w),@(0x9abc:16,r2.w)" +gdb_test "x" "and.w\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abc(:16|),er2.l\\)" \ + "and.w @(0x1234:16,r3.w),@(0x9abc:16,er2.l)" +gdb_test "x" "and.w\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "and.w @(0x1234:16,r3.w),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "and.w\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "and.w @(0x1234:16,r3.w),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "and.w\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "and.w @(0x1234:16,r3.w),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "and.w\t@\\(0x1234(:16|),r3.w\\),@0x9abc(:16|)" \ + "and.w @(0x1234:16,r3.w),@0x9abc:16" +gdb_test "x" "and.w\t@\\(0x1234(:16|),r3.w\\),@0x9abcdef0(:32|)" \ + "and.w @(0x1234:16,r3.w),@0x9abcdef0:32" +gdb_test "x" "and.w\t@\\(0x1234(:16|),er3.l\\),@er1" \ + "and.w @(0x1234:16,er3.l),@er1" +gdb_test "x" "and.w\t@\\(0x1234(:16|),er3.l\\),@\\(0x6(:2|),er1\\)" \ + "and.w @(0x1234:16,er3.l),@(0x6:2,er1)" +gdb_test "x" "and.w\t@\\(0x1234(:16|),er3.l\\),@-er1" \ + "and.w @(0x1234:16,er3.l),@-er1" +gdb_test "x" "and.w\t@\\(0x1234(:16|),er3.l\\),@er1\\+" \ + "and.w @(0x1234:16,er3.l),@er1+" +gdb_test "x" "and.w\t@\\(0x1234(:16|),er3.l\\),@er1-" \ + "and.w @(0x1234:16,er3.l),@er1-" +gdb_test "x" "and.w\t@\\(0x1234(:16|),er3.l\\),@\\+er1" \ + "and.w @(0x1234:16,er3.l),@+er1" +gdb_test "x" "and.w\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abc(:16|),er1\\)" \ + "and.w @(0x1234:16,er3.l),@(0x9abc:16,er1)" +gdb_test "x" "and.w\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "and.w @(0x1234:16,er3.l),@(0x9abcdef0:32,er1)" +gdb_test "x" "and.w\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "and.w @(0x1234:16,er3.l),@(0x9abc:16,r2l.b)" +gdb_test "x" "and.w\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abc(:16|),r2.w\\)" \ + "and.w @(0x1234:16,er3.l),@(0x9abc:16,r2.w)" +gdb_test "x" "and.w\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abc(:16|),er2.l\\)" \ + "and.w @(0x1234:16,er3.l),@(0x9abc:16,er2.l)" +gdb_test "x" "and.w\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "and.w @(0x1234:16,er3.l),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "and.w\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "and.w @(0x1234:16,er3.l),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "and.w\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "and.w @(0x1234:16,er3.l),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "and.w\t@\\(0x1234(:16|),er3.l\\),@0x9abc(:16|)" \ + "and.w @(0x1234:16,er3.l),@0x9abc:16" +gdb_test "x" "and.w\t@\\(0x1234(:16|),er3.l\\),@0x9abcdef0(:32|)" \ + "and.w @(0x1234:16,er3.l),@0x9abcdef0:32" +gdb_test "x" "and.w\t@\\(0x12345678(:32|),r3l.b\\),@er1" \ + "and.w @(0x12345678:32,r3l.b),@er1" +gdb_test "x" "and.w\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x6(:2|),er1\\)" \ + "and.w @(0x12345678:32,r3l.b),@(0x6:2,er1)" +gdb_test "x" "and.w\t@\\(0x12345678(:32|),r3l.b\\),@-er1" \ + "and.w @(0x12345678:32,r3l.b),@-er1" +gdb_test "x" "and.w\t@\\(0x12345678(:32|),r3l.b\\),@er1\\+" \ + "and.w @(0x12345678:32,r3l.b),@er1+" +gdb_test "x" "and.w\t@\\(0x12345678(:32|),r3l.b\\),@er1-" \ + "and.w @(0x12345678:32,r3l.b),@er1-" +gdb_test "x" "and.w\t@\\(0x12345678(:32|),r3l.b\\),@\\+er1" \ + "and.w @(0x12345678:32,r3l.b),@+er1" +gdb_test "x" "and.w\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abc(:16|),er1\\)" \ + "and.w @(0x12345678:32,r3l.b),@(0x9abc:16,er1)" +gdb_test "x" "and.w\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "and.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1)" +gdb_test "x" "and.w\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "and.w @(0x12345678:32,r3l.b),@(0x9abc:16,r2l.b)" +gdb_test "x" "and.w\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abc(:16|),r2.w\\)" \ + "and.w @(0x12345678:32,r3l.b),@(0x9abc:16,r2.w)" +gdb_test "x" "and.w\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abc(:16|),er2.l\\)" \ + "and.w @(0x12345678:32,r3l.b),@(0x9abc:16,er2.l)" +gdb_test "x" "and.w\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "and.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "and.w\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "and.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "and.w\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "and.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "and.w\t@\\(0x12345678(:32|),r3l.b\\),@0x9abc(:16|)" \ + "and.w @(0x12345678:32,r3l.b),@0x9abc:16" +gdb_test "x" "and.w\t@\\(0x12345678(:32|),r3l.b\\),@0x9abcdef0(:32|)" \ + "and.w @(0x12345678:32,r3l.b),@0x9abcdef0:32" +gdb_test "x" "and.w\t@\\(0x12345678(:32|),r3.w\\),@er1" \ + "and.w @(0x12345678:32,r3.w),@er1" +gdb_test "x" "and.w\t@\\(0x12345678(:32|),r3.w\\),@\\(0x6(:2|),er1\\)" \ + "and.w @(0x12345678:32,r3.w),@(0x6:2,er1)" +gdb_test "x" "and.w\t@\\(0x12345678(:32|),r3.w\\),@-er1" \ + "and.w @(0x12345678:32,r3.w),@-er1" +gdb_test "x" "and.w\t@\\(0x12345678(:32|),r3.w\\),@er1\\+" \ + "and.w @(0x12345678:32,r3.w),@er1+" +gdb_test "x" "and.w\t@\\(0x12345678(:32|),r3.w\\),@er1-" \ + "and.w @(0x12345678:32,r3.w),@er1-" +gdb_test "x" "and.w\t@\\(0x12345678(:32|),r3.w\\),@\\+er1" \ + "and.w @(0x12345678:32,r3.w),@+er1" +gdb_test "x" "and.w\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abc(:16|),er1\\)" \ + "and.w @(0x12345678:32,r3.w),@(0x9abc:16,er1)" +gdb_test "x" "and.w\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "and.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1)" +gdb_test "x" "and.w\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "and.w @(0x12345678:32,r3.w),@(0x9abc:16,r2l.b)" +gdb_test "x" "and.w\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abc(:16|),r2.w\\)" \ + "and.w @(0x12345678:32,r3.w),@(0x9abc:16,r2.w)" +gdb_test "x" "and.w\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abc(:16|),er2.l\\)" \ + "and.w @(0x12345678:32,r3.w),@(0x9abc:16,er2.l)" +gdb_test "x" "and.w\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "and.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "and.w\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "and.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "and.w\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "and.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "and.w\t@\\(0x12345678(:32|),r3.w\\),@0x9abc(:16|)" \ + "and.w @(0x12345678:32,r3.w),@0x9abc:16" +gdb_test "x" "and.w\t@\\(0x12345678(:32|),r3.w\\),@0x9abcdef0(:32|)" \ + "and.w @(0x12345678:32,r3.w),@0x9abcdef0:32" +gdb_test "x" "and.w\t@\\(0x12345678(:32|),er3.l\\),@er1" \ + "and.w @(0x12345678:32,er3.l),@er1" +gdb_test "x" "and.w\t@\\(0x12345678(:32|),er3.l\\),@\\(0x6(:2|),er1\\)" \ + "and.w @(0x12345678:32,er3.l),@(0x6:2,er1)" +gdb_test "x" "and.w\t@\\(0x12345678(:32|),er3.l\\),@-er1" \ + "and.w @(0x12345678:32,er3.l),@-er1" +gdb_test "x" "and.w\t@\\(0x12345678(:32|),er3.l\\),@er1\\+" \ + "and.w @(0x12345678:32,er3.l),@er1+" +gdb_test "x" "and.w\t@\\(0x12345678(:32|),er3.l\\),@er1-" \ + "and.w @(0x12345678:32,er3.l),@er1-" +gdb_test "x" "and.w\t@\\(0x12345678(:32|),er3.l\\),@\\+er1" \ + "and.w @(0x12345678:32,er3.l),@+er1" +gdb_test "x" "and.w\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abc(:16|),er1\\)" \ + "and.w @(0x12345678:32,er3.l),@(0x9abc:16,er1)" +gdb_test "x" "and.w\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "and.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1)" +gdb_test "x" "and.w\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "and.w @(0x12345678:32,er3.l),@(0x9abc:16,r2l.b)" +gdb_test "x" "and.w\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abc(:16|),r2.w\\)" \ + "and.w @(0x12345678:32,er3.l),@(0x9abc:16,r2.w)" +gdb_test "x" "and.w\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abc(:16|),er2.l\\)" \ + "and.w @(0x12345678:32,er3.l),@(0x9abc:16,er2.l)" +gdb_test "x" "and.w\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "and.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "and.w\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "and.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "and.w\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "and.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "and.w\t@\\(0x12345678(:32|),er3.l\\),@0x9abc(:16|)" \ + "and.w @(0x12345678:32,er3.l),@0x9abc:16" +gdb_test "x" "and.w\t@\\(0x12345678(:32|),er3.l\\),@0x9abcdef0(:32|)" \ + "and.w @(0x12345678:32,er3.l),@0x9abcdef0:32" +gdb_test "x" "and.w\t@0x1234(:16|),@er1" \ + "and.w @0x1234:16,@er1" +gdb_test "x" "and.w\t@0x1234(:16|),@\\(0x6(:2|),er1\\)" \ + "and.w @0x1234:16,@(0x6:2,er1)" +gdb_test "x" "and.w\t@0x1234(:16|),@-er1" \ + "and.w @0x1234:16,@-er1" +gdb_test "x" "and.w\t@0x1234(:16|),@er1\\+" \ + "and.w @0x1234:16,@er1+" +gdb_test "x" "and.w\t@0x1234(:16|),@er1-" \ + "and.w @0x1234:16,@er1-" +gdb_test "x" "and.w\t@0x1234(:16|),@\\+er1" \ + "and.w @0x1234:16,@+er1" +gdb_test "x" "and.w\t@0x1234(:16|),@\\(0x9abc(:16|),er1\\)" \ + "and.w @0x1234:16,@(0x9abc:16,er1)" +gdb_test "x" "and.w\t@0x1234(:16|),@\\(0x9abcdef0(:32|),er1\\)" \ + "and.w @0x1234:16,@(0x9abcdef0:32,er1)" +gdb_test "x" "and.w\t@0x1234(:16|),@\\(0x9abc(:16|),r2l.b\\)" \ + "and.w @0x1234:16,@(0x9abc:16,r2l.b)" +gdb_test "x" "and.w\t@0x1234(:16|),@\\(0x9abc(:16|),r2.w\\)" \ + "and.w @0x1234:16,@(0x9abc:16,r2.w)" +gdb_test "x" "and.w\t@0x1234(:16|),@\\(0x9abc(:16|),er2.l\\)" \ + "and.w @0x1234:16,@(0x9abc:16,er2.l)" +gdb_test "x" "and.w\t@0x1234(:16|),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "and.w @0x1234:16,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "and.w\t@0x1234(:16|),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "and.w @0x1234:16,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "and.w\t@0x1234(:16|),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "and.w @0x1234:16,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "and.w\t@0x1234(:16|),@0x9abc(:16|)" \ + "and.w @0x1234:16,@0x9abc:16" +gdb_test "x" "and.w\t@0x1234(:16|),@0x9abcdef0(:32|)" \ + "and.w @0x1234:16,@0x9abcdef0:32" +gdb_test "x" "and.w\t@0x12345678(:32|),@er1" \ + "and.w @0x12345678:32,@er1" +gdb_test "x" "and.w\t@0x12345678(:32|),@\\(0x6(:2|),er1\\)" \ + "and.w @0x12345678:32,@(0x6:2,er1)" +gdb_test "x" "and.w\t@0x12345678(:32|),@-er1" \ + "and.w @0x12345678:32,@-er1" +gdb_test "x" "and.w\t@0x12345678(:32|),@er1\\+" \ + "and.w @0x12345678:32,@er1+" +gdb_test "x" "and.w\t@0x12345678(:32|),@er1-" \ + "and.w @0x12345678:32,@er1-" +gdb_test "x" "and.w\t@0x12345678(:32|),@\\+er1" \ + "and.w @0x12345678:32,@+er1" +gdb_test "x" "and.w\t@0x12345678(:32|),@\\(0x9abc(:16|),er1\\)" \ + "and.w @0x12345678:32,@(0x9abc:16,er1)" +gdb_test "x" "and.w\t@0x12345678(:32|),@\\(0x9abcdef0(:32|),er1\\)" \ + "and.w @0x12345678:32,@(0x9abcdef0:32,er1)" +gdb_test "x" "and.w\t@0x12345678(:32|),@\\(0x9abc(:16|),r2l.b\\)" \ + "and.w @0x12345678:32,@(0x9abc:16,r2l.b)" +gdb_test "x" "and.w\t@0x12345678(:32|),@\\(0x9abc(:16|),r2.w\\)" \ + "and.w @0x12345678:32,@(0x9abc:16,r2.w)" +gdb_test "x" "and.w\t@0x12345678(:32|),@\\(0x9abc(:16|),er2.l\\)" \ + "and.w @0x12345678:32,@(0x9abc:16,er2.l)" +gdb_test "x" "and.w\t@0x12345678(:32|),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "and.w @0x12345678:32,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "and.w\t@0x12345678(:32|),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "and.w @0x12345678:32,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "and.w\t@0x12345678(:32|),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "and.w @0x12345678:32,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "and.w\t@0x12345678(:32|),@0x9abc(:16|)" \ + "and.w @0x12345678:32,@0x9abc:16" +gdb_test "x" "and.w\t@0x12345678(:32|),@0x9abcdef0(:32|)" \ + "and.w @0x12345678:32,@0x9abcdef0:32" +gdb_test "x" "and.l\t#0x12345678(:32|),er1" \ + "and.l #0x12345678:32,er1" +gdb_test "x" "and.l\t#0x1234(:16|),er1" \ + "and.l #0x1234:16,er1" +gdb_test "x" "and.l\t#0x12345678(:32|),@er1" \ + "and.l #0x12345678:32,@er1" +gdb_test "x" "and.l\t#0x12345678(:32|),@\\(0xc(:2|),er1\\)" \ + "and.l #0x12345678:32,@(0xc:2,er1)" +gdb_test "x" "and.l\t#0x12345678(:32|),@er1\\+" \ + "and.l #0x12345678:32,@er1+" +gdb_test "x" "and.l\t#0x12345678(:32|),@-er1" \ + "and.l #0x12345678:32,@-er1" +gdb_test "x" "and.l\t#0x12345678(:32|),@\\+er1" \ + "and.l #0x12345678:32,@+er1" +gdb_test "x" "and.l\t#0x12345678(:32|),@er1-" \ + "and.l #0x12345678:32,@er1-" +gdb_test "x" "and.l\t#0x12345678(:32|),@\\(0x9abc(:16|),er1\\)" \ + "and.l #0x12345678:32,@(0x9abc:16,er1)" +gdb_test "x" "and.l\t#0x12345678(:32|),@\\(0x9abcdef0(:32|),er1\\)" \ + "and.l #0x12345678:32,@(0x9abcdef0:32,er1)" +gdb_test "x" "and.l\t#0x12345678(:32|),@\\(0x9abc(:16|),r2l.b\\)" \ + "and.l #0x12345678:32,@(0x9abc:16,r2l.b)" +gdb_test "x" "and.l\t#0x12345678(:32|),@\\(0x9abc(:16|),r2.w\\)" \ + "and.l #0x12345678:32,@(0x9abc:16,r2.w)" +gdb_test "x" "and.l\t#0x12345678(:32|),@\\(0x9abc(:16|),er2.l\\)" \ + "and.l #0x12345678:32,@(0x9abc:16,er2.l)" +gdb_test "x" "and.l\t#0x12345678(:32|),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "and.l #0x12345678:32,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "and.l\t#0x12345678(:32|),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "and.l #0x12345678:32,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "and.l\t#0x12345678(:32|),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "and.l #0x12345678:32,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "and.l\t#0x12345678(:32|),@0x9abc(:16|)" \ + "and.l #0x12345678:32,@0x9abc:16" +gdb_test "x" "and.l\t#0x12345678(:32|),@0x9abcdef0(:32|)" \ + "and.l #0x12345678:32,@0x9abcdef0:32" +gdb_test "x" "and.l\t#0x1234(:16|),@er1" \ + "and.l #0x1234:16,@er1" +gdb_test "x" "and.l\t#0x1234(:16|),@\\(0xc(:2|),er1\\)" \ + "and.l #0x1234:16,@(0xc:2,er1)" +gdb_test "x" "and.l\t#0x1234(:16|),@er1\\+" \ + "and.l #0x1234:16,@er1+" +gdb_test "x" "and.l\t#0x1234(:16|),@-er1" \ + "and.l #0x1234:16,@-er1" +gdb_test "x" "and.l\t#0x1234(:16|),@\\+er1" \ + "and.l #0x1234:16,@+er1" +gdb_test "x" "and.l\t#0x1234(:16|),@er1-" \ + "and.l #0x1234:16,@er1-" +gdb_test "x" "and.l\t#0x1234(:16|),@\\(0x9abc(:16|),er1\\)" \ + "and.l #0x1234:16,@(0x9abc:16,er1)" +gdb_test "x" "and.l\t#0x1234(:16|),@\\(0x9abcdef0(:32|),er1\\)" \ + "and.l #0x1234:16,@(0x9abcdef0:32,er1)" +gdb_test "x" "and.l\t#0x1234(:16|),@\\(0x9abc(:16|),r2l.b\\)" \ + "and.l #0x1234:16,@(0x9abc:16,r2l.b)" +gdb_test "x" "and.l\t#0x1234(:16|),@\\(0x9abc(:16|),r2.w\\)" \ + "and.l #0x1234:16,@(0x9abc:16,r2.w)" +gdb_test "x" "and.l\t#0x1234(:16|),@\\(0x9abc(:16|),er2.l\\)" \ + "and.l #0x1234:16,@(0x9abc:16,er2.l)" +gdb_test "x" "and.l\t#0x1234(:16|),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "and.l #0x1234:16,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "and.l\t#0x1234(:16|),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "and.l #0x1234:16,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "and.l\t#0x1234(:16|),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "and.l #0x1234:16,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "and.l\t#0x1234(:16|),@0x9abc(:16|)" \ + "and.l #0x1234:16,@0x9abc:16" +gdb_test "x" "and.l\t#0x1234(:16|),@0x9abcdef0(:32|)" \ + "and.l #0x1234:16,@0x9abcdef0:32" +gdb_test "x" "and.l\ter3,er1" \ + "and.l er3,er1" +gdb_test "x" "and.l\ter3,@er1" \ + "and.l er3,@er1" +gdb_test "x" "and.l\ter3,@\\(0xc(:2|),er1\\)" \ + "and.l er3,@(0xc:2,er1)" +gdb_test "x" "and.l\ter3,@er1\\+" \ + "and.l er3,@er1+" +gdb_test "x" "and.l\ter3,@-er1" \ + "and.l er3,@-er1" +gdb_test "x" "and.l\ter3,@\\+er1" \ + "and.l er3,@+er1" +gdb_test "x" "and.l\ter3,@er1-" \ + "and.l er3,@er1-" +gdb_test "x" "and.l\ter3,@\\(0x1234(:16|),er1\\)" \ + "and.l er3,@(0x1234:16,er1)" +gdb_test "x" "and.l\ter3,@\\(0x12345678(:32|),er1\\)" \ + "and.l er3,@(0x12345678:32,er1)" +gdb_test "x" "and.l\ter3,@\\(0x1234(:16|),r2l.b\\)" \ + "and.l er3,@(0x1234:16,r2l.b)" +gdb_test "x" "and.l\ter3,@\\(0x1234(:16|),r2.w\\)" \ + "and.l er3,@(0x1234:16,r2.w)" +gdb_test "x" "and.l\ter3,@\\(0x1234(:16|),er2.l\\)" \ + "and.l er3,@(0x1234:16,er2.l)" +gdb_test "x" "and.l\ter3,@\\(0x12345678(:32|),r2l.b\\)" \ + "and.l er3,@(0x12345678:32,r2l.b)" +gdb_test "x" "and.l\ter3,@\\(0x12345678(:32|),r2.w\\)" \ + "and.l er3,@(0x12345678:32,r2.w)" +gdb_test "x" "and.l\ter3,@\\(0x12345678(:32|),er2.l\\)" \ + "and.l er3,@(0x12345678:32,er2.l)" +gdb_test "x" "and.l\ter3,@0x1234(:16|)" \ + "and.l er3,@0x1234:16" +gdb_test "x" "and.l\ter3,@0x12345678(:32|)" \ + "and.l er3,@0x12345678:32" +gdb_test "x" "and.l\t@er3,er1" \ + "and.l @er3,er1" +gdb_test "x" "and.l\t@\\(0xc(:2|),er3\\),er1" \ + "and.l @(0xc:2,er3),er1" +gdb_test "x" "and.l\t@er3\\+,er1" \ + "and.l @er3+,er1" +gdb_test "x" "and.l\t@-er3,er1" \ + "and.l @-er3,er1" +gdb_test "x" "and.l\t@\\+er3,er1" \ + "and.l @+er3,er1" +gdb_test "x" "and.l\t@er3-,er1" \ + "and.l @er3-,er1" +gdb_test "x" "and.l\t@\\(0x1234(:16|),er1\\),er1" \ + "and.l @(0x1234:16,er1),er1" +gdb_test "x" "and.l\t@\\(0x12345678(:32|),er1\\),er1" \ + "and.l @(0x12345678:32,er1),er1" +gdb_test "x" "and.l\t@\\(0x1234(:16|),r2l.b\\),er1" \ + "and.l @(0x1234:16,r2l.b),er1" +gdb_test "x" "and.l\t@\\(0x1234(:16|),r2.w\\),er1" \ + "and.l @(0x1234:16,r2.w),er1" +gdb_test "x" "and.l\t@\\(0x1234(:16|),er2.l\\),er1" \ + "and.l @(0x1234:16,er2.l),er1" +gdb_test "x" "and.l\t@\\(0x12345678(:32|),r2l.b\\),er1" \ + "and.l @(0x12345678:32,r2l.b),er1" +gdb_test "x" "and.l\t@\\(0x12345678(:32|),r2.w\\),er1" \ + "and.l @(0x12345678:32,r2.w),er1" +gdb_test "x" "and.l\t@\\(0x12345678(:32|),er2.l\\),er1" \ + "and.l @(0x12345678:32,er2.l),er1" +gdb_test "x" "and.l\t@0x1234(:16|),er1" \ + "and.l @0x1234:16,er1" +gdb_test "x" "and.l\t@0x12345678(:32|),er1" \ + "and.l @0x12345678:32,er1" +gdb_test "x" "and.l\t@er3,@er1" \ + "and.l @er3,@er1" +gdb_test "x" "and.l\t@er3,@\\(0xc(:2|),er1\\)" \ + "and.l @er3,@(0xc:2,er1)" +gdb_test "x" "and.l\t@er3,@-er1" \ + "and.l @er3,@-er1" +gdb_test "x" "and.l\t@er3,@er1\\+" \ + "and.l @er3,@er1+" +gdb_test "x" "and.l\t@er3,@er1-" \ + "and.l @er3,@er1-" +gdb_test "x" "and.l\t@er3,@\\+er1" \ + "and.l @er3,@+er1" +gdb_test "x" "and.l\t@er3,@\\(0x9abc(:16|),er1\\)" \ + "and.l @er3,@(0x9abc:16,er1)" +gdb_test "x" "and.l\t@er3,@\\(0x9abcdef0(:32|),er1\\)" \ + "and.l @er3,@(0x9abcdef0:32,er1)" +gdb_test "x" "and.l\t@er3,@\\(0x9abc(:16|),r2l.b\\)" \ + "and.l @er3,@(0x9abc:16,r2l.b)" +gdb_test "x" "and.l\t@er3,@\\(0x9abc(:16|),r2.w\\)" \ + "and.l @er3,@(0x9abc:16,r2.w)" +gdb_test "x" "and.l\t@er3,@\\(0x9abc(:16|),er2.l\\)" \ + "and.l @er3,@(0x9abc:16,er2.l)" +gdb_test "x" "and.l\t@er3,@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "and.l @er3,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "and.l\t@er3,@\\(0x9abcdef0(:32|),r2.w\\)" \ + "and.l @er3,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "and.l\t@er3,@\\(0x9abcdef0(:32|),er2.l\\)" \ + "and.l @er3,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "and.l\t@er3,@0x9abc(:16|)" \ + "and.l @er3,@0x9abc:16" +gdb_test "x" "and.l\t@er3,@0x9abcdef0(:32|)" \ + "and.l @er3,@0x9abcdef0:32" +gdb_test "x" "and.l\t@\\(0xc(:2|),er3\\),@er1" \ + "and.l @(0xc:2,er3),@er1" +gdb_test "x" "and.l\t@\\(0xc(:2|),er3\\),@\\(0xc(:2|),er1\\)" \ + "and.l @(0xc:2,er3),@(0xc:2,er1)" +gdb_test "x" "and.l\t@\\(0xc(:2|),er3\\),@-er1" \ + "and.l @(0xc:2,er3),@-er1" +gdb_test "x" "and.l\t@\\(0xc(:2|),er3\\),@er1\\+" \ + "and.l @(0xc:2,er3),@er1+" +gdb_test "x" "and.l\t@\\(0xc(:2|),er3\\),@er1-" \ + "and.l @(0xc:2,er3),@er1-" +gdb_test "x" "and.l\t@\\(0xc(:2|),er3\\),@\\+er1" \ + "and.l @(0xc:2,er3),@+er1" +gdb_test "x" "and.l\t@\\(0xc(:2|),er3\\),@\\(0x9abc(:16|),er1\\)" \ + "and.l @(0xc:2,er3),@(0x9abc:16,er1)" +gdb_test "x" "and.l\t@\\(0xc(:2|),er3\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "and.l @(0xc:2,er3),@(0x9abcdef0:32,er1)" +gdb_test "x" "and.l\t@\\(0xc(:2|),er3\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "and.l @(0xc:2,er3),@(0x9abc:16,r2l.b)" +gdb_test "x" "and.l\t@\\(0xc(:2|),er3\\),@\\(0x9abc(:16|),r2.w\\)" \ + "and.l @(0xc:2,er3),@(0x9abc:16,r2.w)" +gdb_test "x" "and.l\t@\\(0xc(:2|),er3\\),@\\(0x9abc(:16|),er2.l\\)" \ + "and.l @(0xc:2,er3),@(0x9abc:16,er2.l)" +gdb_test "x" "and.l\t@\\(0xc(:2|),er3\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "and.l @(0xc:2,er3),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "and.l\t@\\(0xc(:2|),er3\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "and.l @(0xc:2,er3),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "and.l\t@\\(0xc(:2|),er3\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "and.l @(0xc:2,er3),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "and.l\t@\\(0xc(:2|),er3\\),@0x9abc(:16|)" \ + "and.l @(0xc:2,er3),@0x9abc:16" +gdb_test "x" "and.l\t@\\(0xc(:2|),er3\\),@0x9abcdef0(:32|)" \ + "and.l @(0xc:2,er3),@0x9abcdef0:32" +gdb_test "x" "and.l\t@-er3,@er1" \ + "and.l @-er3,@er1" +gdb_test "x" "and.l\t@-er3,@\\(0xc(:2|),er1\\)" \ + "and.l @-er3,@(0xc:2,er1)" +gdb_test "x" "and.l\t@-er3,@-er1" \ + "and.l @-er3,@-er1" +gdb_test "x" "and.l\t@-er3,@er1\\+" \ + "and.l @-er3,@er1+" +gdb_test "x" "and.l\t@-er3,@er1-" \ + "and.l @-er3,@er1-" +gdb_test "x" "and.l\t@-er3,@\\+er1" \ + "and.l @-er3,@+er1" +gdb_test "x" "and.l\t@-er3,@\\(0x9abc(:16|),er1\\)" \ + "and.l @-er3,@(0x9abc:16,er1)" +gdb_test "x" "and.l\t@-er3,@\\(0x9abcdef0(:32|),er1\\)" \ + "and.l @-er3,@(0x9abcdef0:32,er1)" +gdb_test "x" "and.l\t@-er3,@\\(0x9abc(:16|),r2l.b\\)" \ + "and.l @-er3,@(0x9abc:16,r2l.b)" +gdb_test "x" "and.l\t@-er3,@\\(0x9abc(:16|),r2.w\\)" \ + "and.l @-er3,@(0x9abc:16,r2.w)" +gdb_test "x" "and.l\t@-er3,@\\(0x9abc(:16|),er2.l\\)" \ + "and.l @-er3,@(0x9abc:16,er2.l)" +gdb_test "x" "and.l\t@-er3,@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "and.l @-er3,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "and.l\t@-er3,@\\(0x9abcdef0(:32|),r2.w\\)" \ + "and.l @-er3,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "and.l\t@-er3,@\\(0x9abcdef0(:32|),er2.l\\)" \ + "and.l @-er3,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "and.l\t@-er3,@0x9abc(:16|)" \ + "and.l @-er3,@0x9abc:16" +gdb_test "x" "and.l\t@-er3,@0x9abcdef0(:32|)" \ + "and.l @-er3,@0x9abcdef0:32" +gdb_test "x" "and.l\t@er3\\+,@er1" \ + "and.l @er3+,@er1" +gdb_test "x" "and.l\t@er3\\+,@\\(0xc(:2|),er1\\)" \ + "and.l @er3+,@(0xc:2,er1)" +gdb_test "x" "and.l\t@er3\\+,@-er1" \ + "and.l @er3+,@-er1" +gdb_test "x" "and.l\t@er3\\+,@er1\\+" \ + "and.l @er3+,@er1+" +gdb_test "x" "and.l\t@er3\\+,@er1-" \ + "and.l @er3+,@er1-" +gdb_test "x" "and.l\t@er3\\+,@\\+er1" \ + "and.l @er3+,@+er1" +gdb_test "x" "and.l\t@er3\\+,@\\(0x9abc(:16|),er1\\)" \ + "and.l @er3+,@(0x9abc:16,er1)" +gdb_test "x" "and.l\t@er3\\+,@\\(0x9abcdef0(:32|),er1\\)" \ + "and.l @er3+,@(0x9abcdef0:32,er1)" +gdb_test "x" "and.l\t@er3\\+,@\\(0x9abc(:16|),r2l.b\\)" \ + "and.l @er3+,@(0x9abc:16,r2l.b)" +gdb_test "x" "and.l\t@er3\\+,@\\(0x9abc(:16|),r2.w\\)" \ + "and.l @er3+,@(0x9abc:16,r2.w)" +gdb_test "x" "and.l\t@er3\\+,@\\(0x9abc(:16|),er2.l\\)" \ + "and.l @er3+,@(0x9abc:16,er2.l)" +gdb_test "x" "and.l\t@er3\\+,@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "and.l @er3+,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "and.l\t@er3\\+,@\\(0x9abcdef0(:32|),r2.w\\)" \ + "and.l @er3+,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "and.l\t@er3\\+,@\\(0x9abcdef0(:32|),er2.l\\)" \ + "and.l @er3+,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "and.l\t@er3\\+,@0x9abc(:16|)" \ + "and.l @er3+,@0x9abc:16" +gdb_test "x" "and.l\t@er3\\+,@0x9abcdef0(:32|)" \ + "and.l @er3+,@0x9abcdef0:32" +gdb_test "x" "and.l\t@er3-,@er1" \ + "and.l @er3-,@er1" +gdb_test "x" "and.l\t@er3-,@\\(0xc(:2|),er1\\)" \ + "and.l @er3-,@(0xc:2,er1)" +gdb_test "x" "and.l\t@er3-,@-er1" \ + "and.l @er3-,@-er1" +gdb_test "x" "and.l\t@er3-,@er1\\+" \ + "and.l @er3-,@er1+" +gdb_test "x" "and.l\t@er3-,@er1-" \ + "and.l @er3-,@er1-" +gdb_test "x" "and.l\t@er3-,@\\+er1" \ + "and.l @er3-,@+er1" +gdb_test "x" "and.l\t@er3-,@\\(0x9abc(:16|),er1\\)" \ + "and.l @er3-,@(0x9abc:16,er1)" +gdb_test "x" "and.l\t@er3-,@\\(0x9abcdef0(:32|),er1\\)" \ + "and.l @er3-,@(0x9abcdef0:32,er1)" +gdb_test "x" "and.l\t@er3-,@\\(0x9abc(:16|),r2l.b\\)" \ + "and.l @er3-,@(0x9abc:16,r2l.b)" +gdb_test "x" "and.l\t@er3-,@\\(0x9abc(:16|),r2.w\\)" \ + "and.l @er3-,@(0x9abc:16,r2.w)" +gdb_test "x" "and.l\t@er3-,@\\(0x9abc(:16|),er2.l\\)" \ + "and.l @er3-,@(0x9abc:16,er2.l)" +gdb_test "x" "and.l\t@er3-,@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "and.l @er3-,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "and.l\t@er3-,@\\(0x9abcdef0(:32|),r2.w\\)" \ + "and.l @er3-,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "and.l\t@er3-,@\\(0x9abcdef0(:32|),er2.l\\)" \ + "and.l @er3-,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "and.l\t@er3-,@0x9abc(:16|)" \ + "and.l @er3-,@0x9abc:16" +gdb_test "x" "and.l\t@er3-,@0x9abcdef0(:32|)" \ + "and.l @er3-,@0x9abcdef0:32" +gdb_test "x" "and.l\t@\\+er3,@er1" \ + "and.l @+er3,@er1" +gdb_test "x" "and.l\t@\\+er3,@\\(0xc(:2|),er1\\)" \ + "and.l @+er3,@(0xc:2,er1)" +gdb_test "x" "and.l\t@\\+er3,@-er1" \ + "and.l @+er3,@-er1" +gdb_test "x" "and.l\t@\\+er3,@er1\\+" \ + "and.l @+er3,@er1+" +gdb_test "x" "and.l\t@\\+er3,@er1-" \ + "and.l @+er3,@er1-" +gdb_test "x" "and.l\t@\\+er3,@\\+er1" \ + "and.l @+er3,@+er1" +gdb_test "x" "and.l\t@\\+er3,@\\(0x9abc(:16|),er1\\)" \ + "and.l @+er3,@(0x9abc:16,er1)" +gdb_test "x" "and.l\t@\\+er3,@\\(0x9abcdef0(:32|),er1\\)" \ + "and.l @+er3,@(0x9abcdef0:32,er1)" +gdb_test "x" "and.l\t@\\+er3,@\\(0x9abc(:16|),r2l.b\\)" \ + "and.l @+er3,@(0x9abc:16,r2l.b)" +gdb_test "x" "and.l\t@\\+er3,@\\(0x9abc(:16|),r2.w\\)" \ + "and.l @+er3,@(0x9abc:16,r2.w)" +gdb_test "x" "and.l\t@\\+er3,@\\(0x9abc(:16|),er2.l\\)" \ + "and.l @+er3,@(0x9abc:16,er2.l)" +gdb_test "x" "and.l\t@\\+er3,@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "and.l @+er3,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "and.l\t@\\+er3,@\\(0x9abcdef0(:32|),r2.w\\)" \ + "and.l @+er3,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "and.l\t@\\+er3,@\\(0x9abcdef0(:32|),er2.l\\)" \ + "and.l @+er3,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "and.l\t@\\+er3,@0x9abc(:16|)" \ + "and.l @+er3,@0x9abc:16" +gdb_test "x" "and.l\t@\\+er3,@0x9abcdef0(:32|)" \ + "and.l @+er3,@0x9abcdef0:32" +gdb_test "x" "and.l\t@\\(0x1234(:16|),er3\\),@er1" \ + "and.l @(0x1234:16,er3),@er1" +gdb_test "x" "and.l\t@\\(0x1234(:16|),er3\\),@\\(0xc(:2|),er1\\)" \ + "and.l @(0x1234:16,er3),@(0xc:2,er1)" +gdb_test "x" "and.l\t@\\(0x1234(:16|),er3\\),@-er1" \ + "and.l @(0x1234:16,er3),@-er1" +gdb_test "x" "and.l\t@\\(0x1234(:16|),er3\\),@er1\\+" \ + "and.l @(0x1234:16,er3),@er1+" +gdb_test "x" "and.l\t@\\(0x1234(:16|),er3\\),@er1-" \ + "and.l @(0x1234:16,er3),@er1-" +gdb_test "x" "and.l\t@\\(0x1234(:16|),er3\\),@\\+er1" \ + "and.l @(0x1234:16,er3),@+er1" +gdb_test "x" "and.l\t@\\(0x1234(:16|),er3\\),@\\(0x9abc(:16|),er1\\)" \ + "and.l @(0x1234:16,er3),@(0x9abc:16,er1)" +gdb_test "x" "and.l\t@\\(0x1234(:16|),er3\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "and.l @(0x1234:16,er3),@(0x9abcdef0:32,er1)" +gdb_test "x" "and.l\t@\\(0x1234(:16|),er3\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "and.l @(0x1234:16,er3),@(0x9abc:16,r2l.b)" +gdb_test "x" "and.l\t@\\(0x1234(:16|),er3\\),@\\(0x9abc(:16|),r2.w\\)" \ + "and.l @(0x1234:16,er3),@(0x9abc:16,r2.w)" +gdb_test "x" "and.l\t@\\(0x1234(:16|),er3\\),@\\(0x9abc(:16|),er2.l\\)" \ + "and.l @(0x1234:16,er3),@(0x9abc:16,er2.l)" +gdb_test "x" "and.l\t@\\(0x1234(:16|),er3\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "and.l @(0x1234:16,er3),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "and.l\t@\\(0x1234(:16|),er3\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "and.l @(0x1234:16,er3),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "and.l\t@\\(0x1234(:16|),er3\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "and.l @(0x1234:16,er3),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "and.l\t@\\(0x1234(:16|),er3\\),@0x9abc(:16|)" \ + "and.l @(0x1234:16,er3),@0x9abc:16" +gdb_test "x" "and.l\t@\\(0x1234(:16|),er3\\),@0x9abcdef0(:32|)" \ + "and.l @(0x1234:16,er3),@0x9abcdef0:32" +gdb_test "x" "and.l\t@\\(0x12345678(:32|),er3\\),@er1" \ + "and.l @(0x12345678:32,er3),@er1" +gdb_test "x" "and.l\t@\\(0x12345678(:32|),er3\\),@\\(0xc(:2|),er1\\)" \ + "and.l @(0x12345678:32,er3),@(0xc:2,er1)" +gdb_test "x" "and.l\t@\\(0x12345678(:32|),er3\\),@-er1" \ + "and.l @(0x12345678:32,er3),@-er1" +gdb_test "x" "and.l\t@\\(0x12345678(:32|),er3\\),@er1\\+" \ + "and.l @(0x12345678:32,er3),@er1+" +gdb_test "x" "and.l\t@\\(0x12345678(:32|),er3\\),@er1-" \ + "and.l @(0x12345678:32,er3),@er1-" +gdb_test "x" "and.l\t@\\(0x12345678(:32|),er3\\),@\\+er1" \ + "and.l @(0x12345678:32,er3),@+er1" +gdb_test "x" "and.l\t@\\(0x12345678(:32|),er3\\),@\\(0x9abc(:16|),er1\\)" \ + "and.l @(0x12345678:32,er3),@(0x9abc:16,er1)" +gdb_test "x" "and.l\t@\\(0x12345678(:32|),er3\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "and.l @(0x12345678:32,er3),@(0x9abcdef0:32,er1)" +gdb_test "x" "and.l\t@\\(0x12345678(:32|),er3\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "and.l @(0x12345678:32,er3),@(0x9abc:16,r2l.b)" +gdb_test "x" "and.l\t@\\(0x12345678(:32|),er3\\),@\\(0x9abc(:16|),r2.w\\)" \ + "and.l @(0x12345678:32,er3),@(0x9abc:16,r2.w)" +gdb_test "x" "and.l\t@\\(0x12345678(:32|),er3\\),@\\(0x9abc(:16|),er2.l\\)" \ + "and.l @(0x12345678:32,er3),@(0x9abc:16,er2.l)" +gdb_test "x" "and.l\t@\\(0x12345678(:32|),er3\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "and.l @(0x12345678:32,er3),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "and.l\t@\\(0x12345678(:32|),er3\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "and.l @(0x12345678:32,er3),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "and.l\t@\\(0x12345678(:32|),er3\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "and.l @(0x12345678:32,er3),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "and.l\t@\\(0x12345678(:32|),er3\\),@0x9abc(:16|)" \ + "and.l @(0x12345678:32,er3),@0x9abc:16" +gdb_test "x" "and.l\t@\\(0x12345678(:32|),er3\\),@0x9abcdef0(:32|)" \ + "and.l @(0x12345678:32,er3),@0x9abcdef0:32" +gdb_test "x" "and.l\t@\\(0x1234(:16|),r3l.b\\),@er1" \ + "and.l @(0x1234:16,r3l.b),@er1" +gdb_test "x" "and.l\t@\\(0x1234(:16|),r3l.b\\),@\\(0xc(:2|),er1\\)" \ + "and.l @(0x1234:16,r3l.b),@(0xc:2,er1)" +gdb_test "x" "and.l\t@\\(0x1234(:16|),r3l.b\\),@-er1" \ + "and.l @(0x1234:16,r3l.b),@-er1" +gdb_test "x" "and.l\t@\\(0x1234(:16|),r3l.b\\),@er1\\+" \ + "and.l @(0x1234:16,r3l.b),@er1+" +gdb_test "x" "and.l\t@\\(0x1234(:16|),r3l.b\\),@er1-" \ + "and.l @(0x1234:16,r3l.b),@er1-" +gdb_test "x" "and.l\t@\\(0x1234(:16|),r3l.b\\),@\\+er1" \ + "and.l @(0x1234:16,r3l.b),@+er1" +gdb_test "x" "and.l\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abc(:16|),er1\\)" \ + "and.l @(0x1234:16,r3l.b),@(0x9abc:16,er1)" +gdb_test "x" "and.l\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "and.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1)" +gdb_test "x" "and.l\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "and.l @(0x1234:16,r3l.b),@(0x9abc:16,r2l.b)" +gdb_test "x" "and.l\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abc(:16|),r2.w\\)" \ + "and.l @(0x1234:16,r3l.b),@(0x9abc:16,r2.w)" +gdb_test "x" "and.l\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abc(:16|),er2.l\\)" \ + "and.l @(0x1234:16,r3l.b),@(0x9abc:16,er2.l)" +gdb_test "x" "and.l\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "and.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "and.l\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "and.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "and.l\t@\\(0x1234(:16|),r3l.b\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "and.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "and.l\t@\\(0x1234(:16|),r3l.b\\),@0x9abc(:16|)" \ + "and.l @(0x1234:16,r3l.b),@0x9abc:16" +gdb_test "x" "and.l\t@\\(0x1234(:16|),r3l.b\\),@0x9abcdef0(:32|)" \ + "and.l @(0x1234:16,r3l.b),@0x9abcdef0:32" +gdb_test "x" "and.l\t@\\(0x1234(:16|),r3.w\\),@er1" \ + "and.l @(0x1234:16,r3.w),@er1" +gdb_test "x" "and.l\t@\\(0x1234(:16|),r3.w\\),@\\(0xc(:2|),er1\\)" \ + "and.l @(0x1234:16,r3.w),@(0xc:2,er1)" +gdb_test "x" "and.l\t@\\(0x1234(:16|),r3.w\\),@-er1" \ + "and.l @(0x1234:16,r3.w),@-er1" +gdb_test "x" "and.l\t@\\(0x1234(:16|),r3.w\\),@er1\\+" \ + "and.l @(0x1234:16,r3.w),@er1+" +gdb_test "x" "and.l\t@\\(0x1234(:16|),r3.w\\),@er1-" \ + "and.l @(0x1234:16,r3.w),@er1-" +gdb_test "x" "and.l\t@\\(0x1234(:16|),r3.w\\),@\\+er1" \ + "and.l @(0x1234:16,r3.w),@+er1" +gdb_test "x" "and.l\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abc(:16|),er1\\)" \ + "and.l @(0x1234:16,r3.w),@(0x9abc:16,er1)" +gdb_test "x" "and.l\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "and.l @(0x1234:16,r3.w),@(0x9abcdef0:32,er1)" +gdb_test "x" "and.l\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "and.l @(0x1234:16,r3.w),@(0x9abc:16,r2l.b)" +gdb_test "x" "and.l\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abc(:16|),r2.w\\)" \ + "and.l @(0x1234:16,r3.w),@(0x9abc:16,r2.w)" +gdb_test "x" "and.l\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abc(:16|),er2.l\\)" \ + "and.l @(0x1234:16,r3.w),@(0x9abc:16,er2.l)" +gdb_test "x" "and.l\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "and.l @(0x1234:16,r3.w),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "and.l\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "and.l @(0x1234:16,r3.w),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "and.l\t@\\(0x1234(:16|),r3.w\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "and.l @(0x1234:16,r3.w),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "and.l\t@\\(0x1234(:16|),r3.w\\),@0x9abc(:16|)" \ + "and.l @(0x1234:16,r3.w),@0x9abc:16" +gdb_test "x" "and.l\t@\\(0x1234(:16|),r3.w\\),@0x9abcdef0(:32|)" \ + "and.l @(0x1234:16,r3.w),@0x9abcdef0:32" +gdb_test "x" "and.l\t@\\(0x1234(:16|),er3.l\\),@er1" \ + "and.l @(0x1234:16,er3.l),@er1" +gdb_test "x" "and.l\t@\\(0x1234(:16|),er3.l\\),@\\(0xc(:2|),er1\\)" \ + "and.l @(0x1234:16,er3.l),@(0xc:2,er1)" +gdb_test "x" "and.l\t@\\(0x1234(:16|),er3.l\\),@-er1" \ + "and.l @(0x1234:16,er3.l),@-er1" +gdb_test "x" "and.l\t@\\(0x1234(:16|),er3.l\\),@er1\\+" \ + "and.l @(0x1234:16,er3.l),@er1+" +gdb_test "x" "and.l\t@\\(0x1234(:16|),er3.l\\),@er1-" \ + "and.l @(0x1234:16,er3.l),@er1-" +gdb_test "x" "and.l\t@\\(0x1234(:16|),er3.l\\),@\\+er1" \ + "and.l @(0x1234:16,er3.l),@+er1" +gdb_test "x" "and.l\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abc(:16|),er1\\)" \ + "and.l @(0x1234:16,er3.l),@(0x9abc:16,er1)" +gdb_test "x" "and.l\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "and.l @(0x1234:16,er3.l),@(0x9abcdef0:32,er1)" +gdb_test "x" "and.l\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "and.l @(0x1234:16,er3.l),@(0x9abc:16,r2l.b)" +gdb_test "x" "and.l\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abc(:16|),r2.w\\)" \ + "and.l @(0x1234:16,er3.l),@(0x9abc:16,r2.w)" +gdb_test "x" "and.l\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abc(:16|),er2.l\\)" \ + "and.l @(0x1234:16,er3.l),@(0x9abc:16,er2.l)" +gdb_test "x" "and.l\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "and.l @(0x1234:16,er3.l),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "and.l\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "and.l @(0x1234:16,er3.l),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "and.l\t@\\(0x1234(:16|),er3.l\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "and.l @(0x1234:16,er3.l),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "and.l\t@\\(0x1234(:16|),er3.l\\),@0x9abc(:16|)" \ + "and.l @(0x1234:16,er3.l),@0x9abc:16" +gdb_test "x" "and.l\t@\\(0x1234(:16|),er3.l\\),@0x9abcdef0(:32|)" \ + "and.l @(0x1234:16,er3.l),@0x9abcdef0:32" +gdb_test "x" "and.l\t@\\(0x12345678(:32|),r3l.b\\),@er1" \ + "and.l @(0x12345678:32,r3l.b),@er1" +gdb_test "x" "and.l\t@\\(0x12345678(:32|),r3l.b\\),@\\(0xc(:2|),er1\\)" \ + "and.l @(0x12345678:32,r3l.b),@(0xc:2,er1)" +gdb_test "x" "and.l\t@\\(0x12345678(:32|),r3l.b\\),@-er1" \ + "and.l @(0x12345678:32,r3l.b),@-er1" +gdb_test "x" "and.l\t@\\(0x12345678(:32|),r3l.b\\),@er1\\+" \ + "and.l @(0x12345678:32,r3l.b),@er1+" +gdb_test "x" "and.l\t@\\(0x12345678(:32|),r3l.b\\),@er1-" \ + "and.l @(0x12345678:32,r3l.b),@er1-" +gdb_test "x" "and.l\t@\\(0x12345678(:32|),r3l.b\\),@\\+er1" \ + "and.l @(0x12345678:32,r3l.b),@+er1" +gdb_test "x" "and.l\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abc(:16|),er1\\)" \ + "and.l @(0x12345678:32,r3l.b),@(0x9abc:16,er1)" +gdb_test "x" "and.l\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "and.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1)" +gdb_test "x" "and.l\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "and.l @(0x12345678:32,r3l.b),@(0x9abc:16,r2l.b)" +gdb_test "x" "and.l\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abc(:16|),r2.w\\)" \ + "and.l @(0x12345678:32,r3l.b),@(0x9abc:16,r2.w)" +gdb_test "x" "and.l\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abc(:16|),er2.l\\)" \ + "and.l @(0x12345678:32,r3l.b),@(0x9abc:16,er2.l)" +gdb_test "x" "and.l\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "and.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "and.l\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "and.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "and.l\t@\\(0x12345678(:32|),r3l.b\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "and.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "and.l\t@\\(0x12345678(:32|),r3l.b\\),@0x9abc(:16|)" \ + "and.l @(0x12345678:32,r3l.b),@0x9abc:16" +gdb_test "x" "and.l\t@\\(0x12345678(:32|),r3l.b\\),@0x9abcdef0(:32|)" \ + "and.l @(0x12345678:32,r3l.b),@0x9abcdef0:32" +gdb_test "x" "and.l\t@\\(0x12345678(:32|),r3.w\\),@er1" \ + "and.l @(0x12345678:32,r3.w),@er1" +gdb_test "x" "and.l\t@\\(0x12345678(:32|),r3.w\\),@\\(0xc(:2|),er1\\)" \ + "and.l @(0x12345678:32,r3.w),@(0xc:2,er1)" +gdb_test "x" "and.l\t@\\(0x12345678(:32|),r3.w\\),@-er1" \ + "and.l @(0x12345678:32,r3.w),@-er1" +gdb_test "x" "and.l\t@\\(0x12345678(:32|),r3.w\\),@er1\\+" \ + "and.l @(0x12345678:32,r3.w),@er1+" +gdb_test "x" "and.l\t@\\(0x12345678(:32|),r3.w\\),@er1-" \ + "and.l @(0x12345678:32,r3.w),@er1-" +gdb_test "x" "and.l\t@\\(0x12345678(:32|),r3.w\\),@\\+er1" \ + "and.l @(0x12345678:32,r3.w),@+er1" +gdb_test "x" "and.l\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abc(:16|),er1\\)" \ + "and.l @(0x12345678:32,r3.w),@(0x9abc:16,er1)" +gdb_test "x" "and.l\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "and.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1)" +gdb_test "x" "and.l\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "and.l @(0x12345678:32,r3.w),@(0x9abc:16,r2l.b)" +gdb_test "x" "and.l\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abc(:16|),r2.w\\)" \ + "and.l @(0x12345678:32,r3.w),@(0x9abc:16,r2.w)" +gdb_test "x" "and.l\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abc(:16|),er2.l\\)" \ + "and.l @(0x12345678:32,r3.w),@(0x9abc:16,er2.l)" +gdb_test "x" "and.l\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "and.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "and.l\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "and.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "and.l\t@\\(0x12345678(:32|),r3.w\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "and.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "and.l\t@\\(0x12345678(:32|),r3.w\\),@0x9abc(:16|)" \ + "and.l @(0x12345678:32,r3.w),@0x9abc:16" +gdb_test "x" "and.l\t@\\(0x12345678(:32|),r3.w\\),@0x9abcdef0(:32|)" \ + "and.l @(0x12345678:32,r3.w),@0x9abcdef0:32" +gdb_test "x" "and.l\t@\\(0x12345678(:32|),er3.l\\),@er1" \ + "and.l @(0x12345678:32,er3.l),@er1" +gdb_test "x" "and.l\t@\\(0x12345678(:32|),er3.l\\),@\\(0xc(:2|),er1\\)" \ + "and.l @(0x12345678:32,er3.l),@(0xc:2,er1)" +gdb_test "x" "and.l\t@\\(0x12345678(:32|),er3.l\\),@-er1" \ + "and.l @(0x12345678:32,er3.l),@-er1" +gdb_test "x" "and.l\t@\\(0x12345678(:32|),er3.l\\),@er1\\+" \ + "and.l @(0x12345678:32,er3.l),@er1+" +gdb_test "x" "and.l\t@\\(0x12345678(:32|),er3.l\\),@er1-" \ + "and.l @(0x12345678:32,er3.l),@er1-" +gdb_test "x" "and.l\t@\\(0x12345678(:32|),er3.l\\),@\\+er1" \ + "and.l @(0x12345678:32,er3.l),@+er1" +gdb_test "x" "and.l\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abc(:16|),er1\\)" \ + "and.l @(0x12345678:32,er3.l),@(0x9abc:16,er1)" +gdb_test "x" "and.l\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abcdef0(:32|),er1\\)" \ + "and.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1)" +gdb_test "x" "and.l\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abc(:16|),r2l.b\\)" \ + "and.l @(0x12345678:32,er3.l),@(0x9abc:16,r2l.b)" +gdb_test "x" "and.l\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abc(:16|),r2.w\\)" \ + "and.l @(0x12345678:32,er3.l),@(0x9abc:16,r2.w)" +gdb_test "x" "and.l\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abc(:16|),er2.l\\)" \ + "and.l @(0x12345678:32,er3.l),@(0x9abc:16,er2.l)" +gdb_test "x" "and.l\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "and.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "and.l\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "and.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2.w)" +gdb_test "x" "and.l\t@\\(0x12345678(:32|),er3.l\\),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "and.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,er2.l)" +gdb_test "x" "and.l\t@\\(0x12345678(:32|),er3.l\\),@0x9abc(:16|)" \ + "and.l @(0x12345678:32,er3.l),@0x9abc:16" +gdb_test "x" "and.l\t@\\(0x12345678(:32|),er3.l\\),@0x9abcdef0(:32|)" \ + "and.l @(0x12345678:32,er3.l),@0x9abcdef0:32" +gdb_test "x" "and.l\t@0x1234(:16|),@er1" \ + "and.l @0x1234:16,@er1" +gdb_test "x" "and.l\t@0x1234(:16|),@\\(0xc(:2|),er1\\)" \ + "and.l @0x1234:16,@(0xc:2,er1)" +gdb_test "x" "and.l\t@0x1234(:16|),@-er1" \ + "and.l @0x1234:16,@-er1" +gdb_test "x" "and.l\t@0x1234(:16|),@er1\\+" \ + "and.l @0x1234:16,@er1+" +gdb_test "x" "and.l\t@0x1234(:16|),@er1-" \ + "and.l @0x1234:16,@er1-" +gdb_test "x" "and.l\t@0x1234(:16|),@\\+er1" \ + "and.l @0x1234:16,@+er1" +gdb_test "x" "and.l\t@0x1234(:16|),@\\(0x9abc(:16|),er1\\)" \ + "and.l @0x1234:16,@(0x9abc:16,er1)" +gdb_test "x" "and.l\t@0x1234(:16|),@\\(0x9abcdef0(:32|),er1\\)" \ + "and.l @0x1234:16,@(0x9abcdef0:32,er1)" +gdb_test "x" "and.l\t@0x1234(:16|),@\\(0x9abc(:16|),r2l.b\\)" \ + "and.l @0x1234:16,@(0x9abc:16,r2l.b)" +gdb_test "x" "and.l\t@0x1234(:16|),@\\(0x9abc(:16|),r2.w\\)" \ + "and.l @0x1234:16,@(0x9abc:16,r2.w)" +gdb_test "x" "and.l\t@0x1234(:16|),@\\(0x9abc(:16|),er2.l\\)" \ + "and.l @0x1234:16,@(0x9abc:16,er2.l)" +gdb_test "x" "and.l\t@0x1234(:16|),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "and.l @0x1234:16,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "and.l\t@0x1234(:16|),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "and.l @0x1234:16,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "and.l\t@0x1234(:16|),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "and.l @0x1234:16,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "and.l\t@0x1234(:16|),@0x9abc(:16|)" \ + "and.l @0x1234:16,@0x9abc:16" +gdb_test "x" "and.l\t@0x1234(:16|),@0x9abcdef0(:32|)" \ + "and.l @0x1234:16,@0x9abcdef0:32" +gdb_test "x" "and.l\t@0x12345678(:32|),@er1" \ + "and.l @0x12345678:32,@er1" +gdb_test "x" "and.l\t@0x12345678(:32|),@\\(0xc(:2|),er1\\)" \ + "and.l @0x12345678:32,@(0xc:2,er1)" +gdb_test "x" "and.l\t@0x12345678(:32|),@-er1" \ + "and.l @0x12345678:32,@-er1" +gdb_test "x" "and.l\t@0x12345678(:32|),@er1\\+" \ + "and.l @0x12345678:32,@er1+" +gdb_test "x" "and.l\t@0x12345678(:32|),@er1-" \ + "and.l @0x12345678:32,@er1-" +gdb_test "x" "and.l\t@0x12345678(:32|),@\\+er1" \ + "and.l @0x12345678:32,@+er1" +gdb_test "x" "and.l\t@0x12345678(:32|),@\\(0x9abc(:16|),er1\\)" \ + "and.l @0x12345678:32,@(0x9abc:16,er1)" +gdb_test "x" "and.l\t@0x12345678(:32|),@\\(0x9abcdef0(:32|),er1\\)" \ + "and.l @0x12345678:32,@(0x9abcdef0:32,er1)" +gdb_test "x" "and.l\t@0x12345678(:32|),@\\(0x9abc(:16|),r2l.b\\)" \ + "and.l @0x12345678:32,@(0x9abc:16,r2l.b)" +gdb_test "x" "and.l\t@0x12345678(:32|),@\\(0x9abc(:16|),r2.w\\)" \ + "and.l @0x12345678:32,@(0x9abc:16,r2.w)" +gdb_test "x" "and.l\t@0x12345678(:32|),@\\(0x9abc(:16|),er2.l\\)" \ + "and.l @0x12345678:32,@(0x9abc:16,er2.l)" +gdb_test "x" "and.l\t@0x12345678(:32|),@\\(0x9abcdef0(:32|),r2l.b\\)" \ + "and.l @0x12345678:32,@(0x9abcdef0:32,r2l.b)" +gdb_test "x" "and.l\t@0x12345678(:32|),@\\(0x9abcdef0(:32|),r2.w\\)" \ + "and.l @0x12345678:32,@(0x9abcdef0:32,r2.w)" +gdb_test "x" "and.l\t@0x12345678(:32|),@\\(0x9abcdef0(:32|),er2.l\\)" \ + "and.l @0x12345678:32,@(0x9abcdef0:32,er2.l)" +gdb_test "x" "and.l\t@0x12345678(:32|),@0x9abc(:16|)" \ + "and.l @0x12345678:32,@0x9abc:16" +gdb_test "x" "and.l\t@0x12345678(:32|),@0x9abcdef0(:32|)" \ + "and.l @0x12345678:32,@0x9abcdef0:32" diff --git a/gdb/testsuite/gdb.disasm/t10_and.s b/gdb/testsuite/gdb.disasm/t10_and.s new file mode 100644 index 0000000..63ce383 --- /dev/null +++ b/gdb/testsuite/gdb.disasm/t10_and.s @@ -0,0 +1,972 @@ +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;log_1 +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + .h8300sx + .text + .global _start +_start: + and.b #0x12:8,r1h ;e112 + and.b #0x12:8,@er1 ;7d10e012 + and.b #0x12:8,@(0x3:2,er1) ;01776818e012 + and.b #0x12:8,@er1+ ;01746c18e012 + and.b #0x12:8,@-er1 ;01776c18e012 + and.b #0x12:8,@+er1 ;01756c18e012 + and.b #0x12:8,@er1- ;01766c18e012 + and.b #0x12:8,@(0x1234:16,er1) ;01746e181234e012 + and.b #0x12:8,@(0x12345678:32,er1) ;78146a2812345678e012 + and.b #0x12:8,@(0x1234:16,r2l.b) ;01756e281234e012 + and.b #0x12:8,@(0x1234:16,r2.w) ;01766e281234e012 + and.b #0x12:8,@(0x1234:16,er2.l) ;01776e281234e012 + and.b #0x12:8,@(0x12345678:32,r2l.b) ;78256a2812345678e012 + and.b #0x12:8,@(0x12345678:32,r2.w) ;78266a2812345678e012 + and.b #0x12:8,@(0x12345678:32,er2.l) ;78276a2812345678e012 + and.b #0x12:8,@0xffffff12:8 ;7f12e012 + and.b #0x12:8,@0x1234:16 ;6a181234e012 + and.b #0x12:8,@0x12345678:32 ;6a3812345678e012 + + and.b r3h,r1h ;1631 + + and.b r3h,@er1 ;7d101630 + and.b r3h,@(0x3:2,er1) ;01793163 + and.b r3h,@er1+ ;01798163 + and.b r3h,@-er1 ;0179b163 + and.b r3h,@+er1 ;01799163 + and.b r3h,@er1- ;0179a163 + and.b r3h,@(0x1234:16,er1) ;0179c1631234 + and.b r3h,@(0x12345678:32,er1) ;0179c96312345678 + and.b r3h,@(0x1234:16,r2l.b) ;0179d2631234 + and.b r3h,@(0x1234:16,r2.w) ;0179e2631234 + and.b r3h,@(0x1234:16,er2.l) ;0179f2631234 + and.b r3h,@(0x12345678:32,r2l.b) ;0179da6312345678 + and.b r3h,@(0x12345678:32,r2.w) ;0179ea6312345678 + and.b r3h,@(0x12345678:32,er2.l) ;0179fa6312345678 + and.b r3h,@0xffffff12:8 ;7f121630 + and.b r3h,@0x1234:16 ;6a1812341630 + and.b r3h,@0x12345678:32 ;6a38123456781630 + + and.b @er3,r1h ;7c301601 + and.b @(0x3:2,er3),r1h ;017a3361 + and.b @er3+,r1h ;017a8361 + and.b @-er3,r1h ;017ab361 + and.b @+er3,r1h ;017a9361 + and.b @er3-,r1h ;017aa361 + and.b @(0x1234:16,er1),r1h ;017ac1611234 + and.b @(0x12345678:32,er1),r1h ;017ac96112345678 + and.b @(0x1234:16,r2l.b),r1h ;017ad2611234 + and.b @(0x1234:16,r2.w),r1h ;017ae2611234 + and.b @(0x1234:16,er2.l),r1h ;017af2611234 + and.b @(0x12345678:32,r2l.b),r1h ;017ada6112345678 + and.b @(0x12345678:32,r2.w),r1h ;017aea6112345678 + and.b @(0x12345678:32,er2.l),r1h ;017afa6112345678 + and.b @0xffffff12:8,r1h ;7e121601 + and.b @0x1234:16,r1h ;6a1012341601 + and.b @0x12345678:32,r1h ;6a30123456781601 + + and.b @er3,@er1 ;7c350160 + and.b @er3,@(3:2,er1) ;7c353160 + and.b @er3,@-er1 ;7c35b160 + and.b @er3,@er1+ ;7c358160 + and.b @er3,@er1- ;7c35a160 + and.b @er3,@+er1 ;7c359160 + and.b @er3,@(0xffff9abc:16,er1) ;7c35c1609abc + and.b @er3,@(0x9abcdef0:32,er1) ;7c35c9609abcdef0 + and.b @er3,@(0xffff9abc:16,r2l.b) ;7c35d2609abc + and.b @er3,@(0xffff9abc:16,r2.w) ;7c35e2609abc + and.b @er3,@(0xffff9abc:16,er2.l) ;7c35f2609abc + and.b @er3,@(0x9abcdef0:32,r2l.b) ;7c35da609abcdef0 + and.b @er3,@(0x9abcdef0:32,r2.w) ;7c35ea609abcdef0 + and.b @er3,@(0x9abcdef0:32,er2.l) ;7c35fa609abcdef0 + and.b @er3,@0xffff9abc:16 ;7c3540609abc + and.b @er3,@0x9abcdef0:32 ;7c3548609abcdef0 + + and.b @-er3,@er1 ;01776c3c0160 + and.b @-er3,@(3:2,er1) ;01776c3c3160 + and.b @-er3,@-er1 ;01776c3cb160 + and.b @-er3,@er1+ ;01776c3c8160 + and.b @-er3,@er1- ;01776c3ca160 + and.b @-er3,@+er1 ;01776c3c9160 + and.b @-er3,@(0xffff9abc:16,er1) ;01776c3cc1609abc + and.b @-er3,@(0x9abcdef0:32,er1) ;01776c3cc9609abcdef0 + and.b @-er3,@(0xffff9abc:16,r2l.b) ;01776c3cd2609abc + and.b @-er3,@(0xffff9abc:16,r2.w) ;01776c3ce2609abc + and.b @-er3,@(0xffff9abc:16,er2.l) ;01776c3cf2609abc + and.b @-er3,@(0x9abcdef0:32,r2l.b) ;01776c3cda609abcdef0 + and.b @-er3,@(0x9abcdef0:32,r2.w) ;01776c3cea609abcdef0 + and.b @-er3,@(0x9abcdef0:32,er2.l) ;01776c3cfa609abcdef0 + and.b @-er3,@0xffff9abc:16 ;01776c3c40609abc + and.b @-er3,@0x9abcdef0:32 ;01776c3c48609abcdef0 + + and.b @er3+,@er1 ;01746c3c0160 + and.b @er3+,@(3:2,er1) ;01746c3c3160 + and.b @er3+,@-er1 ;01746c3cb160 + and.b @er3+,@er1+ ;01746c3c8160 + and.b @er3+,@er1- ;01746c3ca160 + and.b @er3+,@+er1 ;01746c3c9160 + and.b @er3+,@(0xffff9abc:16,er1) ;01746c3cc1609abc + and.b @er3+,@(0x9abcdef0:32,er1) ;01746c3cc9609abcdef0 + and.b @er3+,@(0xffff9abc:16,r2l.b) ;01746c3cd2609abc + and.b @er3+,@(0xffff9abc:16,r2.w) ;01746c3ce2609abc + and.b @er3+,@(0xffff9abc:16,er2.l) ;01746c3cf2609abc + and.b @er3+,@(0x9abcdef0:32,r2l.b) ;01746c3cda609abcdef0 + and.b @er3+,@(0x9abcdef0:32,r2.w) ;01746c3cea609abcdef0 + and.b @er3+,@(0x9abcdef0:32,er2.l) ;01746c3cfa609abcdef0 + and.b @er3+,@0xffff9abc:16 ;01746c3c40609abc + and.b @er3+,@0x9abcdef0:32 ;01746c3c48609abcdef0 + + and.b @er3-,@er1 ;01766c3c0160 + and.b @er3-,@(3:2,er1) ;01766c3c3160 + and.b @er3-,@-er1 ;01766c3cb160 + and.b @er3-,@er1+ ;01766c3c8160 + and.b @er3-,@er1- ;01766c3ca160 + and.b @er3-,@+er1 ;01766c3c9160 + and.b @er3-,@(0xffff9abc:16,er1) ;01766c3cc1609abc + and.b @er3-,@(0x9abcdef0:32,er1) ;01766c3cc9609abcdef0 + and.b @er3-,@(0xffff9abc:16,r2l.b) ;01766c3cd2609abc + and.b @er3-,@(0xffff9abc:16,r2.w) ;01766c3ce2609abc + and.b @er3-,@(0xffff9abc:16,er2.l) ;01766c3cf2609abc + and.b @er3-,@(0x9abcdef0:32,r2l.b) ;01766c3cda609abcdef0 + and.b @er3-,@(0x9abcdef0:32,r2.w) ;01766c3cea609abcdef0 + and.b @er3-,@(0x9abcdef0:32,er2.l) ;01766c3cfa609abcdef0 + and.b @er3-,@0xffff9abc:16 ;01766c3c40609abc + and.b @er3-,@0x9abcdef0:32 ;01766c3c48609abcdef0 + + and.b @+er3,@er1 ;01756c3c0160 + and.b @+er3,@(3:2,er1) ;01756c3c3160 + and.b @+er3,@-er1 ;01756c3cb160 + and.b @+er3,@er1+ ;01756c3c8160 + and.b @+er3,@er1- ;01756c3ca160 + and.b @+er3,@+er1 ;01756c3c9160 + and.b @+er3,@(0xffff9abc:16,er1) ;01756c3cc1609abc + and.b @+er3,@(0x9abcdef0:32,er1) ;01756c3cc9609abcdef0 + and.b @+er3,@(0xffff9abc:16,r2l.b) ;01756c3cd2609abc + and.b @+er3,@(0xffff9abc:16,r2.w) ;01756c3ce2609abc + and.b @+er3,@(0xffff9abc:16,er2.l) ;01756c3cf2609abc + and.b @+er3,@(0x9abcdef0:32,r2l.b) ;01756c3cda609abcdef0 + and.b @+er3,@(0x9abcdef0:32,r2.w) ;01756c3cea609abcdef0 + and.b @+er3,@(0x9abcdef0:32,er2.l) ;01756c3cfa609abcdef0 + and.b @+er3,@0xffff9abc:16 ;01756c3c40609abc + and.b @+er3,@0x9abcdef0:32 ;01756c3c48609abcdef0 + + and.b @(0x1234:16,er3),@er1 ;01746e3c12340160 + and.b @(0x1234:16,er3),@(3:2,er1) ;01746e3c12343160 + and.b @(0x1234:16,er3),@-er1 ;01746e3c1234b160 + and.b @(0x1234:16,er3),@er1+ ;01746e3c12348160 + and.b @(0x1234:16,er3),@er1- ;01746e3c1234a160 + and.b @(0x1234:16,er3),@+er1 ;01746e3c12349160 + and.b @(0x1234:16,er3),@(0xffff9abc:16,er1) ;01746e3c1234c1609abc + and.b @(0x1234:16,er3),@(0x9abcdef0:32,er1) ;01746e3c1234c9609abcdef0 + and.b @(0x1234:16,er3),@(0xffff9abc:16,r2l.b) ;01746e3c1234d2609abc + and.b @(0x1234:16,er3),@(0xffff9abc:16,r2.w) ;01746e3c1234e2609abc + and.b @(0x1234:16,er3),@(0xffff9abc:16,er2.l) ;01746e3c1234f2609abc + and.b @(0x1234:16,er3),@(0x9abcdef0:32,r2l.b) ;01746e3c1234da609abcdef0 + and.b @(0x1234:16,er3),@(0x9abcdef0:32,r2.w) ;01746e3c1234ea609abcdef0 + and.b @(0x1234:16,er3),@(0x9abcdef0:32,er2.l) ;01746e3c1234fa609abcdef0 + and.b @(0x1234:16,er3),@0xffff9abc:16 ;01746e3c123440609abc + and.b @(0x1234:16,er3),@0x9abcdef0:32 ;01746e3c123448609abcdef0 + + and.b @(0x12345678:32,er3),@er1 ;78346a2c123456780160 + and.b @(0x12345678:32,er3),@(3:2,er1) ;78346a2c123456783160 + and.b @(0x12345678:32,er3),@-er1 ;78346a2c12345678b160 + and.b @(0x12345678:32,er3),@er1+ ;78346a2c123456788160 + and.b @(0x12345678:32,er3),@er1- ;78346a2c12345678a160 + and.b @(0x12345678:32,er3),@+er1 ;78346a2c123456789160 + and.b @(0x12345678:32,er3),@(0xffff9abc:16,er1) ;78346a2c12345678c1609abc + and.b @(0x12345678:32,er3),@(0x9abcdef0:32,er1) ;78346a2c12345678c9609abcdef0 + and.b @(0x12345678:32,er3),@(0xffff9abc:16,r2l.b) ;78346a2c12345678d2609abc + and.b @(0x12345678:32,er3),@(0xffff9abc:16,r2.w) ;78346a2c12345678e2609abc + and.b @(0x12345678:32,er3),@(0xffff9abc:16,er2.l) ;78346a2c12345678f2609abc + and.b @(0x12345678:32,er3),@(0x9abcdef0:32,r2l.b) ;78346a2c12345678da609abcdef0 + and.b @(0x12345678:32,er3),@(0x9abcdef0:32,r2.w) ;78346a2c12345678ea609abcdef0 + and.b @(0x12345678:32,er3),@(0x9abcdef0:32,er2.l) ;78346a2c12345678fa609abcdef0 + and.b @(0x12345678:32,er3),@0xffff9abc:16 ;78346a2c1234567840609abc + and.b @(0x12345678:32,er3),@0x9abcdef0:32 ;78346a2c1234567848609abcdef0 + + and.b @(0x1234:16,r3l.b),@er1 ;01756e3c12340160 + and.b @(0x1234:16,r3l.b),@(3:2,er1) ;01756e3c12343160 + and.b @(0x1234:16,r3l.b),@-er1 ;01756e3c1234b160 + and.b @(0x1234:16,r3l.b),@er1+ ;01756e3c12348160 + and.b @(0x1234:16,r3l.b),@er1- ;01756e3c1234a160 + and.b @(0x1234:16,r3l.b),@+er1 ;01756e3c12349160 + and.b @(0x1234:16,r3l.b),@(0xffff9abc:16,er1) ;01756e3c1234c1609abc + and.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1) ;01756e3c1234c9609abcdef0 + and.b @(0x1234:16,r3l.b),@(0xffff9abc:16,r2l.b) ;01756e3c1234d2609abc + and.b @(0x1234:16,r3l.b),@(0xffff9abc:16,r2.w) ;01756e3c1234e2609abc + and.b @(0x1234:16,r3l.b),@(0xffff9abc:16,er2.l) ;01756e3c1234f2609abc + and.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2l.b) ;01756e3c1234da609abcdef0 + and.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2.w) ;01756e3c1234ea609abcdef0 + and.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,er2.l) ;01756e3c1234fa609abcdef0 + and.b @(0x1234:16,r3l.b),@0xffff9abc:16 ;01756e3c123440609abc + and.b @(0x1234:16,r3l.b),@0x9abcdef0:32 ;01756e3c123448609abcdef0 + + and.b @(0x1234:16,r3.w),@er1 ;01766e3c12340160 + and.b @(0x1234:16,r3.w),@(3:2,er1) ;01766e3c12343160 + and.b @(0x1234:16,r3.w),@-er1 ;01766e3c1234b160 + and.b @(0x1234:16,r3.w),@er1+ ;01766e3c12348160 + and.b @(0x1234:16,r3.w),@er1- ;01766e3c1234a160 + and.b @(0x1234:16,r3.w),@+er1 ;01766e3c12349160 + and.b @(0x1234:16,r3.w),@(0xffff9abc:16,er1) ;01766e3c1234c1609abc + and.b @(0x1234:16,r3.w),@(0x9abcdef0:32,er1) ;01766e3c1234c9609abcdef0 + and.b @(0x1234:16,r3.w),@(0xffff9abc:16,r2l.b) ;01766e3c1234d2609abc + and.b @(0x1234:16,r3.w),@(0xffff9abc:16,r2.w) ;01766e3c1234e2609abc + and.b @(0x1234:16,r3.w),@(0xffff9abc:16,er2.l) ;01766e3c1234f2609abc + and.b @(0x1234:16,r3.w),@(0x9abcdef0:32,r2l.b) ;01766e3c1234da609abcdef0 + and.b @(0x1234:16,r3.w),@(0x9abcdef0:32,r2.w) ;01766e3c1234ea609abcdef0 + and.b @(0x1234:16,r3.w),@(0x9abcdef0:32,er2.l) ;01766e3c1234fa609abcdef0 + and.b @(0x1234:16,r3.w),@0xffff9abc:16 ;01766e3c123440609abc + and.b @(0x1234:16,r3.w),@0x9abcdef0:32 ;01766e3c123448609abcdef0 + + and.b @(0x1234:16,er3.l),@er1 ;01776e3c12340160 + and.b @(0x1234:16,er3.l),@(3:2,er1) ;01776e3c12343160 + and.b @(0x1234:16,er3.l),@-er1 ;01776e3c1234b160 + and.b @(0x1234:16,er3.l),@er1+ ;01776e3c12348160 + and.b @(0x1234:16,er3.l),@er1- ;01776e3c1234a160 + and.b @(0x1234:16,er3.l),@+er1 ;01776e3c12349160 + and.b @(0x1234:16,er3.l),@(0xffff9abc:16,er1) ;01776e3c1234c1609abc + and.b @(0x1234:16,er3.l),@(0x9abcdef0:32,er1) ;01776e3c1234c9609abcdef0 + and.b @(0x1234:16,er3.l),@(0xffff9abc:16,r2l.b) ;01776e3c1234d2609abc + and.b @(0x1234:16,er3.l),@(0xffff9abc:16,r2.w) ;01776e3c1234e2609abc + and.b @(0x1234:16,er3.l),@(0xffff9abc:16,er2.l) ;01776e3c1234f2609abc + and.b @(0x1234:16,er3.l),@(0x9abcdef0:32,r2l.b) ;01776e3c1234da609abcdef0 + and.b @(0x1234:16,er3.l),@(0x9abcdef0:32,r2.w) ;01776e3c1234ea609abcdef0 + and.b @(0x1234:16,er3.l),@(0x9abcdef0:32,er2.l) ;01776e3c1234fa609abcdef0 + and.b @(0x1234:16,er3.l),@0xffff9abc:16 ;01776e3c123440609abc + and.b @(0x1234:16,er3.l),@0x9abcdef0:32 ;01776e3c123448609abcdef0 + + and.b @(0x12345678:32,r3l.b),@er1 ;78356a2c123456780160 + and.b @(0x12345678:32,r3l.b),@(3:2,er1) ;78356a2c123456783160 + and.b @(0x12345678:32,r3l.b),@-er1 ;78356a2c12345678b160 + and.b @(0x12345678:32,r3l.b),@er1+ ;78356a2c123456788160 + and.b @(0x12345678:32,r3l.b),@er1- ;78356a2c12345678a160 + and.b @(0x12345678:32,r3l.b),@+er1 ;78356a2c123456789160 + and.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,er1) ;78356a2c12345678c1609abc + and.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1) ;78356a2c12345678c9609abcdef0 + and.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2l.b) ;78356a2c12345678d2609abc + and.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2.w) ;78356a2c12345678e2609abc + and.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,er2.l) ;78356a2c12345678f2609abc + and.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2l.b) ;78356a2c12345678da609abcdef0 + and.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2.w) ;78356a2c12345678ea609abcdef0 + and.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er2.l) ;78356a2c12345678fa609abcdef0 + and.b @(0x12345678:32,r3l.b),@0xffff9abc:16 ;78356a2c1234567840609abc + and.b @(0x12345678:32,r3l.b),@0x9abcdef0:32 ;78356a2c1234567848609abcdef0 + + and.b @(0x12345678:32,r3.w),@er1 ;78366a2c123456780160 + and.b @(0x12345678:32,r3.w),@(3:2,er1) ;78366a2c123456783160 + and.b @(0x12345678:32,r3.w),@-er1 ;78366a2c12345678b160 + and.b @(0x12345678:32,r3.w),@er1+ ;78366a2c123456788160 + and.b @(0x12345678:32,r3.w),@er1- ;78366a2c12345678a160 + and.b @(0x12345678:32,r3.w),@+er1 ;78366a2c123456789160 + and.b @(0x12345678:32,r3.w),@(0xffff9abc:16,er1) ;78366a2c12345678c1609abc + and.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1) ;78366a2c12345678c9609abcdef0 + and.b @(0x12345678:32,r3.w),@(0xffff9abc:16,r2l.b) ;78366a2c12345678d2609abc + and.b @(0x12345678:32,r3.w),@(0xffff9abc:16,r2.w) ;78366a2c12345678e2609abc + and.b @(0x12345678:32,r3.w),@(0xffff9abc:16,er2.l) ;78366a2c12345678f2609abc + and.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2l.b) ;78366a2c12345678da609abcdef0 + and.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2.w) ;78366a2c12345678ea609abcdef0 + and.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,er2.l) ;78366a2c12345678fa609abcdef0 + and.b @(0x12345678:32,r3.w),@0xffff9abc:16 ;78366a2c1234567840609abc + and.b @(0x12345678:32,r3.w),@0x9abcdef0:32 ;78366a2c1234567848609abcdef0 + + and.b @(0x12345678:32,er3.l),@er1 ;78376a2c123456780160 + and.b @(0x12345678:32,er3.l),@(3:2,er1) ;78376a2c123456783160 + and.b @(0x12345678:32,er3.l),@-er1 ;78376a2c12345678b160 + and.b @(0x12345678:32,er3.l),@er1+ ;78376a2c123456788160 + and.b @(0x12345678:32,er3.l),@er1- ;78376a2c12345678a160 + and.b @(0x12345678:32,er3.l),@+er1 ;78376a2c123456789160 + and.b @(0x12345678:32,er3.l),@(0xffff9abc:16,er1) ;78376a2c12345678c1609abc + and.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1) ;78376a2c12345678c9609abcdef0 + and.b @(0x12345678:32,er3.l),@(0xffff9abc:16,r2l.b) ;78376a2c12345678d2609abc + and.b @(0x12345678:32,er3.l),@(0xffff9abc:16,r2.w) ;78376a2c12345678e2609abc + and.b @(0x12345678:32,er3.l),@(0xffff9abc:16,er2.l) ;78376a2c12345678f2609abc + and.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2l.b) ;78376a2c12345678da609abcdef0 + and.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2.w) ;78376a2c12345678ea609abcdef0 + and.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,er2.l) ;78376a2c12345678fa609abcdef0 + and.b @(0x12345678:32,er3.l),@0xffff9abc:16 ;78376a2c1234567840609abc + and.b @(0x12345678:32,er3.l),@0x9abcdef0:32 ;78376a2c1234567848609abcdef0 + + and.b @0x1234:16,@er1 ;6a1512340160 + and.b @0x1234:16,@(3:2,er1) ;6a1512343160 + and.b @0x1234:16,@-er1 ;6a151234b160 + and.b @0x1234:16,@er1+ ;6a1512348160 + and.b @0x1234:16,@er1- ;6a151234a160 + and.b @0x1234:16,@+er1 ;6a1512349160 + and.b @0x1234:16,@(0xffff9abc:16,er1) ;6a151234c1609abc + and.b @0x1234:16,@(0x9abcdef0:32,er1) ;6a151234c9609abcdef0 + and.b @0x1234:16,@(0xffff9abc:16,r2l.b) ;6a151234d2609abc + and.b @0x1234:16,@(0xffff9abc:16,r2.w) ;6a151234e2609abc + and.b @0x1234:16,@(0xffff9abc:16,er2.l) ;6a151234f2609abc + and.b @0x1234:16,@(0x9abcdef0:32,r2l.b) ;6a151234da609abcdef0 + and.b @0x1234:16,@(0x9abcdef0:32,r2.w) ;6a151234ea609abcdef0 + and.b @0x1234:16,@(0x9abcdef0:32,er2.l) ;6a151234fa609abcdef0 + and.b @0x1234:16,@0xffff9abc:16 ;6a15123440609abc + and.b @0x1234:16,@0x9abcdef0:32 ;6a15123448609abcdef0 + + and.b @0x12345678:32,@er1 ;6a35123456780160 + and.b @0x12345678:32,@(3:2,er1) ;6a35123456783160 + and.b @0x12345678:32,@-er1 ;6a3512345678b160 + and.b @0x12345678:32,@er1+ ;6a35123456788160 + and.b @0x12345678:32,@er1- ;6a3512345678a160 + and.b @0x12345678:32,@+er1 ;6a35123456789160 + and.b @0x12345678:32,@(0xffff9abc:16,er1) ;6a3512345678c1609abc + and.b @0x12345678:32,@(0x9abcdef0:32,er1) ;6a3512345678c9609abcdef0 + and.b @0x12345678:32,@(0xffff9abc:16,r2l.b) ;6a3512345678d2609abc + and.b @0x12345678:32,@(0xffff9abc:16,r2.w) ;6a3512345678e2609abc + and.b @0x12345678:32,@(0xffff9abc:16,er2.l) ;6a3512345678f2609abc + and.b @0x12345678:32,@(0x9abcdef0:32,r2l.b) ;6a3512345678da609abcdef0 + and.b @0x12345678:32,@(0x9abcdef0:32,r2.w) ;6a3512345678ea609abcdef0 + and.b @0x12345678:32,@(0x9abcdef0:32,er2.l) ;6a3512345678fa609abcdef0 + and.b @0x12345678:32,@0xffff9abc:16 ;6a351234567840609abc + and.b @0x12345678:32,@0x9abcdef0:32 ;6a351234567848609abcdef0 + + and.w #0x1234:16,r1 ;79611234 + and.w #0x1234:16,@er1 ;015e01601234 + and.w #0x1234:16,@(0x6:2,er1) ;015e31601234 + and.w #0x1234:16,@er1+ ;015e81601234 + and.w #0x1234:16,@-er1 ;015eb1601234 + and.w #0x1234:16,@+er1 ;015e91601234 + and.w #0x1234:16,@er1- ;015ea1601234 + and.w #0x1234:16,@(0xffff9abc:16,er1) ;015ec1609abc1234 + and.w #0x1234:16,@(0x9abcdef0:32,er1) ;015ec9609abcdef01234 + and.w #0x1234:16,@(0xffff9abc:16,r2l.b) ;015ed2609abc1234 + and.w #0x1234:16,@(0xffff9abc:16,r2.w) ;015ee2609abc1234 + and.w #0x1234:16,@(0xffff9abc:16,er2.l) ;015ef2609abc1234 + and.w #0x1234:16,@(0x9abcdef0:32,r2l.b) ;015eda609abcdef01234 + and.w #0x1234:16,@(0x9abcdef0:32,r2.w) ;015eea609abcdef01234 + and.w #0x1234:16,@(0x9abcdef0:32,er2.l) ;015efa609abcdef01234 + and.w #0x1234:16,@0xffff9abc:16 ;015e40609abc1234 + and.w #0x1234:16,@0x9abcdef0:32 ;015e48609abcdef01234 + + and.w r3,r1 ;6631 + + and.w r3,@er1 ;7d906630 + and.w r3,@(0x6:2,er1) ;01593163 + and.w r3,@er1+ ;01598163 + and.w r3,@-er1 ;0159b163 + and.w r3,@+er1 ;01599163 + and.w r3,@er1- ;0159a163 + and.w r3,@(0x1234:16,er1) ;0159c1631234 + and.w r3,@(0x12345678:32,er1) ;0159c96312345678 + and.w r3,@(0x1234:16,r2l.b) ;0159d2631234 + and.w r3,@(0x1234:16,r2.w) ;0159e2631234 + and.w r3,@(0x1234:16,er2.l) ;0159f2631234 + and.w r3,@(0x12345678:32,r2l.b) ;0159da6312345678 + and.w r3,@(0x12345678:32,r2.w) ;0159ea6312345678 + and.w r3,@(0x12345678:32,er2.l) ;0159fa6312345678 + and.w r3,@0x1234:16 ;6b1812346630 + and.w r3,@0x12345678:32 ;6b38123456786630 + + and.w @er3,r1 ;7cb06601 + and.w @(0x6:2,er3),r1 ;015a3361 + and.w @er3+,r1 ;015a8361 + and.w @-er3,r1 ;015ab361 + and.w @+er3,r1 ;015a9361 + and.w @er3-,r1 ;015aa361 + and.w @(0x1234:16,er1),r1 ;015ac1611234 + and.w @(0x12345678:32,er1),r1 ;015ac96112345678 + and.w @(0x1234:16,r2l.b),r1 ;015ad2611234 + and.w @(0x1234:16,r2.w),r1 ;015ae2611234 + and.w @(0x1234:16,er2.l),r1 ;015af2611234 + and.w @(0x12345678:32,r2l.b),r1 ;015ada6112345678 + and.w @(0x12345678:32,r2.w),r1 ;015aea6112345678 + and.w @(0x12345678:32,er2.l),r1 ;015afa6112345678 + and.w @0x1234:16,r1 ;6b1012346601 + and.w @0x12345678:32,r1 ;6b30123456786601 + + and.w @er3,@er1 ;7cb50160 + and.w @er3,@(6:2,er1) ;7cb53160 + and.w @er3,@-er1 ;7cb5b160 + and.w @er3,@er1+ ;7cb58160 + and.w @er3,@er1- ;7cb5a160 + and.w @er3,@+er1 ;7cb59160 + and.w @er3,@(0xffff9abc:16,er1) ;7cb5c1609abc + and.w @er3,@(0x9abcdef0:32,er1) ;7cb5c9609abcdef0 + and.w @er3,@(0xffff9abc:16,r2l.b) ;7cb5d2609abc + and.w @er3,@(0xffff9abc:16,r2.w) ;7cb5e2609abc + and.w @er3,@(0xffff9abc:16,er2.l) ;7cb5f2609abc + and.w @er3,@(0x9abcdef0:32,r2l.b) ;7cb5da609abcdef0 + and.w @er3,@(0x9abcdef0:32,r2.w) ;7cb5ea609abcdef0 + and.w @er3,@(0x9abcdef0:32,er2.l) ;7cb5fa609abcdef0 + and.w @er3,@0xffff9abc:16 ;7cb540609abc + and.w @er3,@0x9abcdef0:32 ;7cb548609abcdef0 + + and.w @-er3,@er1 ;01576d3c0160 + and.w @-er3,@(6:2,er1) ;01576d3c3160 + and.w @-er3,@-er1 ;01576d3cb160 + and.w @-er3,@er1+ ;01576d3c8160 + and.w @-er3,@er1- ;01576d3ca160 + and.w @-er3,@+er1 ;01576d3c9160 + and.w @-er3,@(0xffff9abc:16,er1) ;01576d3cc1609abc + and.w @-er3,@(0x9abcdef0:32,er1) ;01576d3cc9609abcdef0 + and.w @-er3,@(0xffff9abc:16,r2l.b) ;01576d3cd2609abc + and.w @-er3,@(0xffff9abc:16,r2.w) ;01576d3ce2609abc + and.w @-er3,@(0xffff9abc:16,er2.l) ;01576d3cf2609abc + and.w @-er3,@(0x9abcdef0:32,r2l.b) ;01576d3cda609abcdef0 + and.w @-er3,@(0x9abcdef0:32,r2.w) ;01576d3cea609abcdef0 + and.w @-er3,@(0x9abcdef0:32,er2.l) ;01576d3cfa609abcdef0 + and.w @-er3,@0xffff9abc:16 ;01576d3c40609abc + and.w @-er3,@0x9abcdef0:32 ;01576d3c48609abcdef0 + + and.w @er3+,@er1 ;01546d3c0160 + and.w @er3+,@(6:2,er1) ;01546d3c3160 + and.w @er3+,@-er1 ;01546d3cb160 + and.w @er3+,@er1+ ;01546d3c8160 + and.w @er3+,@er1- ;01546d3ca160 + and.w @er3+,@+er1 ;01546d3c9160 + and.w @er3+,@(0xffff9abc:16,er1) ;01546d3cc1609abc + and.w @er3+,@(0x9abcdef0:32,er1) ;01546d3cc9609abcdef0 + and.w @er3+,@(0xffff9abc:16,r2l.b) ;01546d3cd2609abc + and.w @er3+,@(0xffff9abc:16,r2.w) ;01546d3ce2609abc + and.w @er3+,@(0xffff9abc:16,er2.l) ;01546d3cf2609abc + and.w @er3+,@(0x9abcdef0:32,r2l.b) ;01546d3cda609abcdef0 + and.w @er3+,@(0x9abcdef0:32,r2.w) ;01546d3cea609abcdef0 + and.w @er3+,@(0x9abcdef0:32,er2.l) ;01546d3cfa609abcdef0 + and.w @er3+,@0xffff9abc:16 ;01546d3c40609abc + and.w @er3+,@0x9abcdef0:32 ;01546d3c48609abcdef0 + + and.w @er3-,@er1 ;01566d3c0160 + and.w @er3-,@(6:2,er1) ;01566d3c3160 + and.w @er3-,@-er1 ;01566d3cb160 + and.w @er3-,@er1+ ;01566d3c8160 + and.w @er3-,@er1- ;01566d3ca160 + and.w @er3-,@+er1 ;01566d3c9160 + and.w @er3-,@(0xffff9abc:16,er1) ;01566d3cc1609abc + and.w @er3-,@(0x9abcdef0:32,er1) ;01566d3cc9609abcdef0 + and.w @er3-,@(0xffff9abc:16,r2l.b) ;01566d3cd2609abc + and.w @er3-,@(0xffff9abc:16,r2.w) ;01566d3ce2609abc + and.w @er3-,@(0xffff9abc:16,er2.l) ;01566d3cf2609abc + and.w @er3-,@(0x9abcdef0:32,r2l.b) ;01566d3cda609abcdef0 + and.w @er3-,@(0x9abcdef0:32,r2.w) ;01566d3cea609abcdef0 + and.w @er3-,@(0x9abcdef0:32,er2.l) ;01566d3cfa609abcdef0 + and.w @er3-,@0xffff9abc:16 ;01566d3c40609abc + and.w @er3-,@0x9abcdef0:32 ;01566d3c48609abcdef0 + + and.w @+er3,@er1 ;01556d3c0160 + and.w @+er3,@(6:2,er1) ;01556d3c3160 + and.w @+er3,@-er1 ;01556d3cb160 + and.w @+er3,@er1+ ;01556d3c8160 + and.w @+er3,@er1- ;01556d3ca160 + and.w @+er3,@+er1 ;01556d3c9160 + and.w @+er3,@(0xffff9abc:16,er1) ;01556d3cc1609abc + and.w @+er3,@(0x9abcdef0:32,er1) ;01556d3cc9609abcdef0 + and.w @+er3,@(0xffff9abc:16,r2l.b) ;01556d3cd2609abc + and.w @+er3,@(0xffff9abc:16,r2.w) ;01556d3ce2609abc + and.w @+er3,@(0xffff9abc:16,er2.l) ;01556d3cf2609abc + and.w @+er3,@(0x9abcdef0:32,r2l.b) ;01556d3cda609abcdef0 + and.w @+er3,@(0x9abcdef0:32,r2.w) ;01556d3cea609abcdef0 + and.w @+er3,@(0x9abcdef0:32,er2.l) ;01556d3cfa609abcdef0 + and.w @+er3,@0xffff9abc:16 ;01556d3c40609abc + and.w @+er3,@0x9abcdef0:32 ;01556d3c48609abcdef0 + + and.w @(0x1234:16,er3),@er1 ;01546f3c12340160 + and.w @(0x1234:16,er3),@(6:2,er1) ;01546f3c12343160 + and.w @(0x1234:16,er3),@-er1 ;01546f3c1234b160 + and.w @(0x1234:16,er3),@er1+ ;01546f3c12348160 + and.w @(0x1234:16,er3),@er1- ;01546f3c1234a160 + and.w @(0x1234:16,er3),@+er1 ;01546f3c12349160 + and.w @(0x1234:16,er3),@(0xffff9abc:16,er1) ;01546f3c1234c1609abc + and.w @(0x1234:16,er3),@(0x9abcdef0:32,er1) ;01546f3c1234c9609abcdef0 + and.w @(0x1234:16,er3),@(0xffff9abc:16,r2l.b) ;01546f3c1234d2609abc + and.w @(0x1234:16,er3),@(0xffff9abc:16,r2.w) ;01546f3c1234e2609abc + and.w @(0x1234:16,er3),@(0xffff9abc:16,er2.l) ;01546f3c1234f2609abc + and.w @(0x1234:16,er3),@(0x9abcdef0:32,r2l.b) ;01546f3c1234da609abcdef0 + and.w @(0x1234:16,er3),@(0x9abcdef0:32,r2.w) ;01546f3c1234ea609abcdef0 + and.w @(0x1234:16,er3),@(0x9abcdef0:32,er2.l) ;01546f3c1234fa609abcdef0 + and.w @(0x1234:16,er3),@0xffff9abc:16 ;01546f3c123440609abc + and.w @(0x1234:16,er3),@0x9abcdef0:32 ;01546f3c123448609abcdef0 + + and.w @(0x12345678:32,er3),@er1 ;78346b2c123456780160 + and.w @(0x12345678:32,er3),@(6:2,er1) ;78346b2c123456783160 + and.w @(0x12345678:32,er3),@-er1 ;78346b2c12345678b160 + and.w @(0x12345678:32,er3),@er1+ ;78346b2c123456788160 + and.w @(0x12345678:32,er3),@er1- ;78346b2c12345678a160 + and.w @(0x12345678:32,er3),@+er1 ;78346b2c123456789160 + and.w @(0x12345678:32,er3),@(0xffff9abc:16,er1) ;78346b2c12345678c1609abc + and.w @(0x12345678:32,er3),@(0x9abcdef0:32,er1) ;78346b2c12345678c9609abcdef0 + and.w @(0x12345678:32,er3),@(0xffff9abc:16,r2l.b) ;78346b2c12345678d2609abc + and.w @(0x12345678:32,er3),@(0xffff9abc:16,r2.w) ;78346b2c12345678e2609abc + and.w @(0x12345678:32,er3),@(0xffff9abc:16,er2.l) ;78346b2c12345678f2609abc + and.w @(0x12345678:32,er3),@(0x9abcdef0:32,r2l.b) ;78346b2c12345678da609abcdef0 + and.w @(0x12345678:32,er3),@(0x9abcdef0:32,r2.w) ;78346b2c12345678ea609abcdef0 + and.w @(0x12345678:32,er3),@(0x9abcdef0:32,er2.l) ;78346b2c12345678fa609abcdef0 + and.w @(0x12345678:32,er3),@0xffff9abc:16 ;78346b2c1234567840609abc + and.w @(0x12345678:32,er3),@0x9abcdef0:32 ;78346b2c1234567848609abcdef0 + + and.w @(0x1234:16,r3l.b),@er1 ;01556f3c12340160 + and.w @(0x1234:16,r3l.b),@(6:2,er1) ;01556f3c12343160 + and.w @(0x1234:16,r3l.b),@-er1 ;01556f3c1234b160 + and.w @(0x1234:16,r3l.b),@er1+ ;01556f3c12348160 + and.w @(0x1234:16,r3l.b),@er1- ;01556f3c1234a160 + and.w @(0x1234:16,r3l.b),@+er1 ;01556f3c12349160 + and.w @(0x1234:16,r3l.b),@(0xffff9abc:16,er1) ;01556f3c1234c1609abc + and.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1) ;01556f3c1234c9609abcdef0 + and.w @(0x1234:16,r3l.b),@(0xffff9abc:16,r2l.b) ;01556f3c1234d2609abc + and.w @(0x1234:16,r3l.b),@(0xffff9abc:16,r2.w) ;01556f3c1234e2609abc + and.w @(0x1234:16,r3l.b),@(0xffff9abc:16,er2.l) ;01556f3c1234f2609abc + and.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2l.b) ;01556f3c1234da609abcdef0 + and.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2.w) ;01556f3c1234ea609abcdef0 + and.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,er2.l) ;01556f3c1234fa609abcdef0 + and.w @(0x1234:16,r3l.b),@0xffff9abc:16 ;01556f3c123440609abc + and.w @(0x1234:16,r3l.b),@0x9abcdef0:32 ;01556f3c123448609abcdef0 + + and.w @(0x1234:16,r3.w),@er1 ;01566f3c12340160 + and.w @(0x1234:16,r3.w),@(6:2,er1) ;01566f3c12343160 + and.w @(0x1234:16,r3.w),@-er1 ;01566f3c1234b160 + and.w @(0x1234:16,r3.w),@er1+ ;01566f3c12348160 + and.w @(0x1234:16,r3.w),@er1- ;01566f3c1234a160 + and.w @(0x1234:16,r3.w),@+er1 ;01566f3c12349160 + and.w @(0x1234:16,r3.w),@(0xffff9abc:16,er1) ;01566f3c1234c1609abc + and.w @(0x1234:16,r3.w),@(0x9abcdef0:32,er1) ;01566f3c1234c9609abcdef0 + and.w @(0x1234:16,r3.w),@(0xffff9abc:16,r2l.b) ;01566f3c1234d2609abc + and.w @(0x1234:16,r3.w),@(0xffff9abc:16,r2.w) ;01566f3c1234e2609abc + and.w @(0x1234:16,r3.w),@(0xffff9abc:16,er2.l) ;01566f3c1234f2609abc + and.w @(0x1234:16,r3.w),@(0x9abcdef0:32,r2l.b) ;01566f3c1234da609abcdef0 + and.w @(0x1234:16,r3.w),@(0x9abcdef0:32,r2.w) ;01566f3c1234ea609abcdef0 + and.w @(0x1234:16,r3.w),@(0x9abcdef0:32,er2.l) ;01566f3c1234fa609abcdef0 + and.w @(0x1234:16,r3.w),@0xffff9abc:16 ;01566f3c123440609abc + and.w @(0x1234:16,r3.w),@0x9abcdef0:32 ;01566f3c123448609abcdef0 + + and.w @(0x1234:16,er3.l),@er1 ;01576f3c12340160 + and.w @(0x1234:16,er3.l),@(6:2,er1) ;01576f3c12343160 + and.w @(0x1234:16,er3.l),@-er1 ;01576f3c1234b160 + and.w @(0x1234:16,er3.l),@er1+ ;01576f3c12348160 + and.w @(0x1234:16,er3.l),@er1- ;01576f3c1234a160 + and.w @(0x1234:16,er3.l),@+er1 ;01576f3c12349160 + and.w @(0x1234:16,er3.l),@(0xffff9abc:16,er1) ;01576f3c1234c1609abc + and.w @(0x1234:16,er3.l),@(0x9abcdef0:32,er1) ;01576f3c1234c9609abcdef0 + and.w @(0x1234:16,er3.l),@(0xffff9abc:16,r2l.b) ;01576f3c1234d2609abc + and.w @(0x1234:16,er3.l),@(0xffff9abc:16,r2.w) ;01576f3c1234e2609abc + and.w @(0x1234:16,er3.l),@(0xffff9abc:16,er2.l) ;01576f3c1234f2609abc + and.w @(0x1234:16,er3.l),@(0x9abcdef0:32,r2l.b) ;01576f3c1234da609abcdef0 + and.w @(0x1234:16,er3.l),@(0x9abcdef0:32,r2.w) ;01576f3c1234ea609abcdef0 + and.w @(0x1234:16,er3.l),@(0x9abcdef0:32,er2.l) ;01576f3c1234fa609abcdef0 + and.w @(0x1234:16,er3.l),@0xffff9abc:16 ;01576f3c123440609abc + and.w @(0x1234:16,er3.l),@0x9abcdef0:32 ;01576f3c123448609abcdef0 + + and.w @(0x12345678:32,r3l.b),@er1 ;78356b2c123456780160 + and.w @(0x12345678:32,r3l.b),@(6:2,er1) ;78356b2c123456783160 + and.w @(0x12345678:32,r3l.b),@-er1 ;78356b2c12345678b160 + and.w @(0x12345678:32,r3l.b),@er1+ ;78356b2c123456788160 + and.w @(0x12345678:32,r3l.b),@er1- ;78356b2c12345678a160 + and.w @(0x12345678:32,r3l.b),@+er1 ;78356b2c123456789160 + and.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,er1) ;78356b2c12345678c1609abc + and.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1) ;78356b2c12345678c9609abcdef0 + and.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2l.b) ;78356b2c12345678d2609abc + and.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2.w) ;78356b2c12345678e2609abc + and.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,er2.l) ;78356b2c12345678f2609abc + and.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2l.b) ;78356b2c12345678da609abcdef0 + and.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2.w) ;78356b2c12345678ea609abcdef0 + and.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er2.l) ;78356b2c12345678fa609abcdef0 + and.w @(0x12345678:32,r3l.b),@0xffff9abc:16 ;78356b2c1234567840609abc + and.w @(0x12345678:32,r3l.b),@0x9abcdef0:32 ;78356b2c1234567848609abcdef0 + + and.w @(0x12345678:32,r3.w),@er1 ;78366b2c123456780160 + and.w @(0x12345678:32,r3.w),@(6:2,er1) ;78366b2c123456783160 + and.w @(0x12345678:32,r3.w),@-er1 ;78366b2c12345678b160 + and.w @(0x12345678:32,r3.w),@er1+ ;78366b2c123456788160 + and.w @(0x12345678:32,r3.w),@er1- ;78366b2c12345678a160 + and.w @(0x12345678:32,r3.w),@+er1 ;78366b2c123456789160 + and.w @(0x12345678:32,r3.w),@(0xffff9abc:16,er1) ;78366b2c12345678c1609abc + and.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1) ;78366b2c12345678c9609abcdef0 + and.w @(0x12345678:32,r3.w),@(0xffff9abc:16,r2l.b) ;78366b2c12345678d2609abc + and.w @(0x12345678:32,r3.w),@(0xffff9abc:16,r2.w) ;78366b2c12345678e2609abc + and.w @(0x12345678:32,r3.w),@(0xffff9abc:16,er2.l) ;78366b2c12345678f2609abc + and.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2l.b) ;78366b2c12345678da609abcdef0 + and.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2.w) ;78366b2c12345678ea609abcdef0 + and.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,er2.l) ;78366b2c12345678fa609abcdef0 + and.w @(0x12345678:32,r3.w),@0xffff9abc:16 ;78366b2c1234567840609abc + and.w @(0x12345678:32,r3.w),@0x9abcdef0:32 ;78366b2c1234567848609abcdef0 + + and.w @(0x12345678:32,er3.l),@er1 ;78376b2c123456780160 + and.w @(0x12345678:32,er3.l),@(6:2,er1) ;78376b2c123456783160 + and.w @(0x12345678:32,er3.l),@-er1 ;78376b2c12345678b160 + and.w @(0x12345678:32,er3.l),@er1+ ;78376b2c123456788160 + and.w @(0x12345678:32,er3.l),@er1- ;78376b2c12345678a160 + and.w @(0x12345678:32,er3.l),@+er1 ;78376b2c123456789160 + and.w @(0x12345678:32,er3.l),@(0xffff9abc:16,er1) ;78376b2c12345678c1609abc + and.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1) ;78376b2c12345678c9609abcdef0 + and.w @(0x12345678:32,er3.l),@(0xffff9abc:16,r2l.b) ;78376b2c12345678d2609abc + and.w @(0x12345678:32,er3.l),@(0xffff9abc:16,r2.w) ;78376b2c12345678e2609abc + and.w @(0x12345678:32,er3.l),@(0xffff9abc:16,er2.l) ;78376b2c12345678f2609abc + and.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2l.b) ;78376b2c12345678da609abcdef0 + and.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2.w) ;78376b2c12345678ea609abcdef0 + and.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,er2.l) ;78376b2c12345678fa609abcdef0 + and.w @(0x12345678:32,er3.l),@0xffff9abc:16 ;78376b2c1234567840609abc + and.w @(0x12345678:32,er3.l),@0x9abcdef0:32 ;78376b2c1234567848609abcdef0 + + and.w @0x1234:16,@er1 ;6b1512340160 + and.w @0x1234:16,@(6:2,er1) ;6b1512343160 + and.w @0x1234:16,@-er1 ;6b151234b160 + and.w @0x1234:16,@er1+ ;6b1512348160 + and.w @0x1234:16,@er1- ;6b151234a160 + and.w @0x1234:16,@+er1 ;6b1512349160 + and.w @0x1234:16,@(0xffff9abc:16,er1) ;6b151234c1609abc + and.w @0x1234:16,@(0x9abcdef0:32,er1) ;6b151234c9609abcdef0 + and.w @0x1234:16,@(0xffff9abc:16,r2l.b) ;6b151234d2609abc + and.w @0x1234:16,@(0xffff9abc:16,r2.w) ;6b151234e2609abc + and.w @0x1234:16,@(0xffff9abc:16,er2.l) ;6b151234f2609abc + and.w @0x1234:16,@(0x9abcdef0:32,r2l.b) ;6b151234da609abcdef0 + and.w @0x1234:16,@(0x9abcdef0:32,r2.w) ;6b151234ea609abcdef0 + and.w @0x1234:16,@(0x9abcdef0:32,er2.l) ;6b151234fa609abcdef0 + and.w @0x1234:16,@0xffff9abc:16 ;6b15123440609abc + and.w @0x1234:16,@0x9abcdef0:32 ;6b15123448609abcdef0 + + and.w @0x12345678:32,@er1 ;6b35123456780160 + and.w @0x12345678:32,@(6:2,er1) ;6b35123456783160 + and.w @0x12345678:32,@-er1 ;6b3512345678b160 + and.w @0x12345678:32,@er1+ ;6b35123456788160 + and.w @0x12345678:32,@er1- ;6b3512345678a160 + and.w @0x12345678:32,@+er1 ;6b35123456789160 + and.w @0x12345678:32,@(0xffff9abc:16,er1) ;6b3512345678c1609abc + and.w @0x12345678:32,@(0x9abcdef0:32,er1) ;6b3512345678c9609abcdef0 + and.w @0x12345678:32,@(0xffff9abc:16,r2l.b) ;6b3512345678d2609abc + and.w @0x12345678:32,@(0xffff9abc:16,r2.w) ;6b3512345678e2609abc + and.w @0x12345678:32,@(0xffff9abc:16,er2.l) ;6b3512345678f2609abc + and.w @0x12345678:32,@(0x9abcdef0:32,r2l.b) ;6b3512345678da609abcdef0 + and.w @0x12345678:32,@(0x9abcdef0:32,r2.w) ;6b3512345678ea609abcdef0 + and.w @0x12345678:32,@(0x9abcdef0:32,er2.l) ;6b3512345678fa609abcdef0 + and.w @0x12345678:32,@0xffff9abc:16 ;6b351234567840609abc + and.w @0x12345678:32,@0x9abcdef0:32 ;6b351234567848609abcdef0 + + and.l #0x12345678:32,er1 ;7a6112345678 + and.l #0x1234:16,er1 ;7a691234 + and.l #0x12345678:32,@er1 ;010e016812345678 + and.l #0x12345678:32,@(0xc:2,er1) ;010e316812345678 + and.l #0x12345678:32,@er1+ ;010e816812345678 + and.l #0x12345678:32,@-er1 ;010eb16812345678 + and.l #0x12345678:32,@+er1 ;010e916812345678 + and.l #0x12345678:32,@er1- ;010ea16812345678 + and.l #0x12345678:32,@(0xffff9abc:16,er1) ;010ec1689abc12345678 + and.l #0x12345678:32,@(0x9abcdef0:32,er1) ;010ec9689abcdef012345678 + and.l #0x12345678:32,@(0xffff9abc:16,r2l.b) ;010ed2689abc12345678 + and.l #0x12345678:32,@(0xffff9abc:16,r2.w) ;010ee2689abc12345678 + and.l #0x12345678:32,@(0xffff9abc:16,er2.l) ;010ef2689abc12345678 + and.l #0x12345678:32,@(0x9abcdef0:32,r2l.b) ;010eda689abcdef012345678 + and.l #0x12345678:32,@(0x9abcdef0:32,r2.w) ;010eea689abcdef012345678 + and.l #0x12345678:32,@(0x9abcdef0:32,er2.l) ;010efa689abcdef012345678 + and.l #0x12345678:32,@0xffff9abc:16 ;010e40689abc12345678 + and.l #0x12345678:32,@0x9abcdef0:32 ;010e48689abcdef012345678 + and.l #0x1234:16,@er1 ;010e01601234 + and.l #0x1234:16,@(0xc:2,er1) ;010e31601234 + and.l #0x1234:16,@er1+ ;010e81601234 + and.l #0x1234:16,@-er1 ;010eb1601234 + and.l #0x1234:16,@+er1 ;010e91601234 + and.l #0x1234:16,@er1- ;010ea1601234 + and.l #0x1234:16,@(0xffff9abc:16,er1) ;010ec1609abc1234 + and.l #0x1234:16,@(0x9abcdef0:32,er1) ;010ec9609abcdef01234 + and.l #0x1234:16,@(0xffff9abc:16,r2l.b) ;010ed2609abc1234 + and.l #0x1234:16,@(0xffff9abc:16,r2.w) ;010ee2609abc1234 + and.l #0x1234:16,@(0xffff9abc:16,er2.l) ;010ef2609abc1234 + and.l #0x1234:16,@(0x9abcdef0:32,r2l.b) ;010eda609abcdef01234 + and.l #0x1234:16,@(0x9abcdef0:32,r2.w) ;010eea609abcdef01234 + and.l #0x1234:16,@(0x9abcdef0:32,er2.l) ;010efa609abcdef01234 + and.l #0x1234:16,@0xffff9abc:16 ;010e40609abc1234 + and.l #0x1234:16,@0x9abcdef0:32 ;010e48609abcdef01234 + + and.l er3,er1 ;01f06631 + + and.l er3,@er1 ;01090163 + and.l er3,@(0xc:2,er1) ;01093163 + and.l er3,@er1+ ;01098163 + and.l er3,@-er1 ;0109b163 + and.l er3,@+er1 ;01099163 + and.l er3,@er1- ;0109a163 + and.l er3,@(0x1234:16,er1) ;0109c1631234 + and.l er3,@(0x12345678:32,er1) ;0109c96312345678 + and.l er3,@(0x1234:16,r2l.b) ;0109d2631234 + and.l er3,@(0x1234:16,r2.w) ;0109e2631234 + and.l er3,@(0x1234:16,er2.l) ;0109f2631234 + and.l er3,@(0x12345678:32,r2l.b) ;0109da6312345678 + and.l er3,@(0x12345678:32,r2.w) ;0109ea6312345678 + and.l er3,@(0x12345678:32,er2.l) ;0109fa6312345678 + and.l er3,@0x1234:16 ;010940631234 + and.l er3,@0x12345678:32 ;0109486312345678 + + and.l @er3,er1 ;010a0361 + and.l @(0xc:2,er3),er1 ;010a3361 + and.l @er3+,er1 ;010a8361 + and.l @-er3,er1 ;010ab361 + and.l @+er3,er1 ;010a9361 + and.l @er3-,er1 ;010aa361 + and.l @(0x1234:16,er1),er1 ;010ac1611234 + and.l @(0x12345678:32,er1),er1 ;010ac96112345678 + and.l @(0x1234:16,r2l.b),er1 ;010ad2611234 + and.l @(0x1234:16,r2.w),er1 ;010ae2611234 + and.l @(0x1234:16,er2.l),er1 ;010af2611234 + and.l @(0x12345678:32,r2l.b),er1 ;010ada6112345678 + and.l @(0x12345678:32,r2.w),er1 ;010aea6112345678 + and.l @(0x12345678:32,er2.l),er1 ;010afa6112345678 + and.l @0x1234:16,er1 ;010a40611234 + and.l @0x12345678:32,er1 ;010a486112345678 + + and.l @er3,@er1 ;0104693c0160 + and.l @er3,@(0xc:2,er1) ;0104693c3160 + and.l @er3,@-er1 ;0104693cb160 + and.l @er3,@er1+ ;0104693c8160 + and.l @er3,@er1- ;0104693ca160 + and.l @er3,@+er1 ;0104693c9160 + and.l @er3,@(0xffff9abc:16,er1) ;0104693cc1609abc + and.l @er3,@(0x9abcdef0:32,er1) ;0104693cc9609abcdef0 + and.l @er3,@(0xffff9abc:16,r2l.b) ;0104693cd2609abc + and.l @er3,@(0xffff9abc:16,r2.w) ;0104693ce2609abc + and.l @er3,@(0xffff9abc:16,er2.l) ;0104693cf2609abc + and.l @er3,@(0x9abcdef0:32,r2l.b) ;0104693cda609abcdef0 + and.l @er3,@(0x9abcdef0:32,r2.w) ;0104693cea609abcdef0 + and.l @er3,@(0x9abcdef0:32,er2.l) ;0104693cfa609abcdef0 + and.l @er3,@0xffff9abc:16 ;0104693c40609abc + and.l @er3,@0x9abcdef0:32 ;0104693c48609abcdef0 + + and.l @(0xc:2,er3),@er1 ;0107693c0160 + and.l @(0xc:2,er3),@(0xc:2,er1) ;0107693c3160 + and.l @(0xc:2,er3),@-er1 ;0107693cb160 + and.l @(0xc:2,er3),@er1+ ;0107693c8160 + and.l @(0xc:2,er3),@er1- ;0107693ca160 + and.l @(0xc:2,er3),@+er1 ;0107693c9160 + and.l @(0xc:2,er3),@(0xffff9abc:16,er1) ;0107693cc1609abc + and.l @(0xc:2,er3),@(0x9abcdef0:32,er1) ;0107693cc9609abcdef0 + and.l @(0xc:2,er3),@(0xffff9abc:16,r2l.b) ;0107693cd2609abc + and.l @(0xc:2,er3),@(0xffff9abc:16,r2.w) ;0107693ce2609abc + and.l @(0xc:2,er3),@(0xffff9abc:16,er2.l) ;0107693cf2609abc + and.l @(0xc:2,er3),@(0x9abcdef0:32,r2l.b) ;0107693cda609abcdef0 + and.l @(0xc:2,er3),@(0x9abcdef0:32,r2.w) ;0107693cea609abcdef0 + and.l @(0xc:2,er3),@(0x9abcdef0:32,er2.l) ;0107693cfa609abcdef0 + and.l @(0xc:2,er3),@0xffff9abc:16 ;0107693c40609abc + and.l @(0xc:2,er3),@0x9abcdef0:32 ;0107693c48609abcdef0 + + and.l @-er3,@er1 ;01076d3c0160 + and.l @-er3,@(0xc:2,er1) ;01076d3c3160 + and.l @-er3,@-er1 ;01076d3cb160 + and.l @-er3,@er1+ ;01076d3c8160 + and.l @-er3,@er1- ;01076d3ca160 + and.l @-er3,@+er1 ;01076d3c9160 + and.l @-er3,@(0xffff9abc:16,er1) ;01076d3cc1609abc + and.l @-er3,@(0x9abcdef0:32,er1) ;01076d3cc9609abcdef0 + and.l @-er3,@(0xffff9abc:16,r2l.b) ;01076d3cd2609abc + and.l @-er3,@(0xffff9abc:16,r2.w) ;01076d3ce2609abc + and.l @-er3,@(0xffff9abc:16,er2.l) ;01076d3cf2609abc + and.l @-er3,@(0x9abcdef0:32,r2l.b) ;01076d3cda609abcdef0 + and.l @-er3,@(0x9abcdef0:32,r2.w) ;01076d3cea609abcdef0 + and.l @-er3,@(0x9abcdef0:32,er2.l) ;01076d3cfa609abcdef0 + and.l @-er3,@0xffff9abc:16 ;01076d3c40609abc + and.l @-er3,@0x9abcdef0:32 ;01076d3c48609abcdef0 + + and.l @er3+,@er1 ;01046d3c0160 + and.l @er3+,@(0xc:2,er1) ;01046d3c3160 + and.l @er3+,@-er1 ;01046d3cb160 + and.l @er3+,@er1+ ;01046d3c8160 + and.l @er3+,@er1- ;01046d3ca160 + and.l @er3+,@+er1 ;01046d3c9160 + and.l @er3+,@(0xffff9abc:16,er1) ;01046d3cc1609abc + and.l @er3+,@(0x9abcdef0:32,er1) ;01046d3cc9609abcdef0 + and.l @er3+,@(0xffff9abc:16,r2l.b) ;01046d3cd2609abc + and.l @er3+,@(0xffff9abc:16,r2.w) ;01046d3ce2609abc + and.l @er3+,@(0xffff9abc:16,er2.l) ;01046d3cf2609abc + and.l @er3+,@(0x9abcdef0:32,r2l.b) ;01046d3cda609abcdef0 + and.l @er3+,@(0x9abcdef0:32,r2.w) ;01046d3cea609abcdef0 + and.l @er3+,@(0x9abcdef0:32,er2.l) ;01046d3cfa609abcdef0 + and.l @er3+,@0xffff9abc:16 ;01046d3c40609abc + and.l @er3+,@0x9abcdef0:32 ;01046d3c48609abcdef0 + + and.l @er3-,@er1 ;01066d3c0160 + and.l @er3-,@(0xc:2,er1) ;01066d3c3160 + and.l @er3-,@-er1 ;01066d3cb160 + and.l @er3-,@er1+ ;01066d3c8160 + and.l @er3-,@er1- ;01066d3ca160 + and.l @er3-,@+er1 ;01066d3c9160 + and.l @er3-,@(0xffff9abc:16,er1) ;01066d3cc1609abc + and.l @er3-,@(0x9abcdef0:32,er1) ;01066d3cc9609abcdef0 + and.l @er3-,@(0xffff9abc:16,r2l.b) ;01066d3cd2609abc + and.l @er3-,@(0xffff9abc:16,r2.w) ;01066d3ce2609abc + and.l @er3-,@(0xffff9abc:16,er2.l) ;01066d3cf2609abc + and.l @er3-,@(0x9abcdef0:32,r2l.b) ;01066d3cda609abcdef0 + and.l @er3-,@(0x9abcdef0:32,r2.w) ;01066d3cea609abcdef0 + and.l @er3-,@(0x9abcdef0:32,er2.l) ;01066d3cfa609abcdef0 + and.l @er3-,@0xffff9abc:16 ;01066d3c40609abc + and.l @er3-,@0x9abcdef0:32 ;01066d3c48609abcdef0 + + and.l @+er3,@er1 ;01056d3c0160 + and.l @+er3,@(0xc:2,er1) ;01056d3c3160 + and.l @+er3,@-er1 ;01056d3cb160 + and.l @+er3,@er1+ ;01056d3c8160 + and.l @+er3,@er1- ;01056d3ca160 + and.l @+er3,@+er1 ;01056d3c9160 + and.l @+er3,@(0xffff9abc:16,er1) ;01056d3cc1609abc + and.l @+er3,@(0x9abcdef0:32,er1) ;01056d3cc9609abcdef0 + and.l @+er3,@(0xffff9abc:16,r2l.b) ;01056d3cd2609abc + and.l @+er3,@(0xffff9abc:16,r2.w) ;01056d3ce2609abc + and.l @+er3,@(0xffff9abc:16,er2.l) ;01056d3cf2609abc + and.l @+er3,@(0x9abcdef0:32,r2l.b) ;01056d3cda609abcdef0 + and.l @+er3,@(0x9abcdef0:32,r2.w) ;01056d3cea609abcdef0 + and.l @+er3,@(0x9abcdef0:32,er2.l) ;01056d3cfa609abcdef0 + and.l @+er3,@0xffff9abc:16 ;01056d3c40609abc + and.l @+er3,@0x9abcdef0:32 ;01056d3c48609abcdef0 + + and.l @(0x1234:16,er3),@er1 ;01046f3c12340160 + and.l @(0x1234:16,er3),@(0xc:2,er1) ;01046f3c12343160 + and.l @(0x1234:16,er3),@-er1 ;01046f3c1234b160 + and.l @(0x1234:16,er3),@er1+ ;01046f3c12348160 + and.l @(0x1234:16,er3),@er1- ;01046f3c1234a160 + and.l @(0x1234:16,er3),@+er1 ;01046f3c12349160 + and.l @(0x1234:16,er3),@(0xffff9abc:16,er1) ;01046f3c1234c1609abc + and.l @(0x1234:16,er3),@(0x9abcdef0:32,er1) ;01046f3c1234c9609abcdef0 + and.l @(0x1234:16,er3),@(0xffff9abc:16,r2l.b) ;01046f3c1234d2609abc + and.l @(0x1234:16,er3),@(0xffff9abc:16,r2.w) ;01046f3c1234e2609abc + and.l @(0x1234:16,er3),@(0xffff9abc:16,er2.l) ;01046f3c1234f2609abc + and.l @(0x1234:16,er3),@(0x9abcdef0:32,r2l.b) ;01046f3c1234da609abcdef0 + and.l @(0x1234:16,er3),@(0x9abcdef0:32,r2.w) ;01046f3c1234ea609abcdef0 + and.l @(0x1234:16,er3),@(0x9abcdef0:32,er2.l) ;01046f3c1234fa609abcdef0 + and.l @(0x1234:16,er3),@0xffff9abc:16 ;01046f3c123440609abc + and.l @(0x1234:16,er3),@0x9abcdef0:32 ;01046f3c123448609abcdef0 + + and.l @(0x12345678:32,er3),@er1 ;78b46b2c123456780160 + and.l @(0x12345678:32,er3),@(0xc:2,er1) ;78b46b2c123456783160 + and.l @(0x12345678:32,er3),@-er1 ;78b46b2c12345678b160 + and.l @(0x12345678:32,er3),@er1+ ;78b46b2c123456788160 + and.l @(0x12345678:32,er3),@er1- ;78b46b2c12345678a160 + and.l @(0x12345678:32,er3),@+er1 ;78b46b2c123456789160 + and.l @(0x12345678:32,er3),@(0xffff9abc:16,er1) ;78b46b2c12345678c1609abc + and.l @(0x12345678:32,er3),@(0x9abcdef0:32,er1) ;78b46b2c12345678c9609abcdef0 + and.l @(0x12345678:32,er3),@(0xffff9abc:16,r2l.b) ;78b46b2c12345678d2609abc + and.l @(0x12345678:32,er3),@(0xffff9abc:16,r2.w) ;78b46b2c12345678e2609abc + and.l @(0x12345678:32,er3),@(0xffff9abc:16,er2.l) ;78b46b2c12345678f2609abc + and.l @(0x12345678:32,er3),@(0x9abcdef0:32,r2l.b) ;78b46b2c12345678da609abcdef0 + and.l @(0x12345678:32,er3),@(0x9abcdef0:32,r2.w) ;78b46b2c12345678ea609abcdef0 + and.l @(0x12345678:32,er3),@(0x9abcdef0:32,er2.l) ;78b46b2c12345678fa609abcdef0 + and.l @(0x12345678:32,er3),@0xffff9abc:16 ;78b46b2c1234567840609abc + and.l @(0x12345678:32,er3),@0x9abcdef0:32 ;78b46b2c1234567848609abcdef0 + + and.l @(0x1234:16,r3l.b),@er1 ;01056f3c12340160 + and.l @(0x1234:16,r3l.b),@(0xc:2,er1) ;01056f3c12343160 + and.l @(0x1234:16,r3l.b),@-er1 ;01056f3c1234b160 + and.l @(0x1234:16,r3l.b),@er1+ ;01056f3c12348160 + and.l @(0x1234:16,r3l.b),@er1- ;01056f3c1234a160 + and.l @(0x1234:16,r3l.b),@+er1 ;01056f3c12349160 + and.l @(0x1234:16,r3l.b),@(0xffff9abc:16,er1) ;01056f3c1234c1609abc + and.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1) ;01056f3c1234c9609abcdef0 + and.l @(0x1234:16,r3l.b),@(0xffff9abc:16,r2l.b) ;01056f3c1234d2609abc + and.l @(0x1234:16,r3l.b),@(0xffff9abc:16,r2.w) ;01056f3c1234e2609abc + and.l @(0x1234:16,r3l.b),@(0xffff9abc:16,er2.l) ;01056f3c1234f2609abc + and.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2l.b) ;01056f3c1234da609abcdef0 + and.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2.w) ;01056f3c1234ea609abcdef0 + and.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,er2.l) ;01056f3c1234fa609abcdef0 + and.l @(0x1234:16,r3l.b),@0xffff9abc:16 ;01056f3c123440609abc + and.l @(0x1234:16,r3l.b),@0x9abcdef0:32 ;01056f3c123448609abcdef0 + + and.l @(0x1234:16,r3.w),@er1 ;01066f3c12340160 + and.l @(0x1234:16,r3.w),@(0xc:2,er1) ;01066f3c12343160 + and.l @(0x1234:16,r3.w),@-er1 ;01066f3c1234b160 + and.l @(0x1234:16,r3.w),@er1+ ;01066f3c12348160 + and.l @(0x1234:16,r3.w),@er1- ;01066f3c1234a160 + and.l @(0x1234:16,r3.w),@+er1 ;01066f3c12349160 + and.l @(0x1234:16,r3.w),@(0xffff9abc:16,er1) ;01066f3c1234c1609abc + and.l @(0x1234:16,r3.w),@(0x9abcdef0:32,er1) ;01066f3c1234c9609abcdef0 + and.l @(0x1234:16,r3.w),@(0xffff9abc:16,r2l.b) ;01066f3c1234d2609abc + and.l @(0x1234:16,r3.w),@(0xffff9abc:16,r2.w) ;01066f3c1234e2609abc + and.l @(0x1234:16,r3.w),@(0xffff9abc:16,er2.l) ;01066f3c1234f2609abc + and.l @(0x1234:16,r3.w),@(0x9abcdef0:32,r2l.b) ;01066f3c1234da609abcdef0 + and.l @(0x1234:16,r3.w),@(0x9abcdef0:32,r2.w) ;01066f3c1234ea609abcdef0 + and.l @(0x1234:16,r3.w),@(0x9abcdef0:32,er2.l) ;01066f3c1234fa609abcdef0 + and.l @(0x1234:16,r3.w),@0xffff9abc:16 ;01066f3c123440609abc + and.l @(0x1234:16,r3.w),@0x9abcdef0:32 ;01066f3c123448609abcdef0 + + and.l @(0x1234:16,er3.l),@er1 ;01076f3c12340160 + and.l @(0x1234:16,er3.l),@(0xc:2,er1) ;01076f3c12343160 + and.l @(0x1234:16,er3.l),@-er1 ;01076f3c1234b160 + and.l @(0x1234:16,er3.l),@er1+ ;01076f3c12348160 + and.l @(0x1234:16,er3.l),@er1- ;01076f3c1234a160 + and.l @(0x1234:16,er3.l),@+er1 ;01076f3c12349160 + and.l @(0x1234:16,er3.l),@(0xffff9abc:16,er1) ;01076f3c1234c1609abc + and.l @(0x1234:16,er3.l),@(0x9abcdef0:32,er1) ;01076f3c1234c9609abcdef0 + and.l @(0x1234:16,er3.l),@(0xffff9abc:16,r2l.b) ;01076f3c1234d2609abc + and.l @(0x1234:16,er3.l),@(0xffff9abc:16,r2.w) ;01076f3c1234e2609abc + and.l @(0x1234:16,er3.l),@(0xffff9abc:16,er2.l) ;01076f3c1234f2609abc + and.l @(0x1234:16,er3.l),@(0x9abcdef0:32,r2l.b) ;01076f3c1234da609abcdef0 + and.l @(0x1234:16,er3.l),@(0x9abcdef0:32,r2.w) ;01076f3c1234ea609abcdef0 + and.l @(0x1234:16,er3.l),@(0x9abcdef0:32,er2.l) ;01076f3c1234fa609abcdef0 + and.l @(0x1234:16,er3.l),@0xffff9abc:16 ;01076f3c123440609abc + and.l @(0x1234:16,er3.l),@0x9abcdef0:32 ;01076f3c123448609abcdef0 + + and.l @(0x12345678:32,r3l.b),@er1 ;78b56b2c123456780160 + and.l @(0x12345678:32,r3l.b),@(0xc:2,er1) ;78b56b2c123456783160 + and.l @(0x12345678:32,r3l.b),@-er1 ;78b56b2c12345678b160 + and.l @(0x12345678:32,r3l.b),@er1+ ;78b56b2c123456788160 + and.l @(0x12345678:32,r3l.b),@er1- ;78b56b2c12345678a160 + and.l @(0x12345678:32,r3l.b),@+er1 ;78b56b2c123456789160 + and.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,er1) ;78b56b2c12345678c1609abc + and.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1) ;78b56b2c12345678c9609abcdef0 + and.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2l.b) ;78b56b2c12345678d2609abc + and.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2.w) ;78b56b2c12345678e2609abc + and.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,er2.l) ;78b56b2c12345678f2609abc + and.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2l.b) ;78b56b2c12345678da609abcdef0 + and.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2.w) ;78b56b2c12345678ea609abcdef0 + and.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er2.l) ;78b56b2c12345678fa609abcdef0 + and.l @(0x12345678:32,r3l.b),@0xffff9abc:16 ;78b56b2c1234567840609abc + and.l @(0x12345678:32,r3l.b),@0x9abcdef0:32 ;78b56b2c1234567848609abcdef0 + + and.l @(0x12345678:32,r3.w),@er1 ;78b66b2c123456780160 + and.l @(0x12345678:32,r3.w),@(0xc:2,er1) ;78b66b2c123456783160 + and.l @(0x12345678:32,r3.w),@-er1 ;78b66b2c12345678b160 + and.l @(0x12345678:32,r3.w),@er1+ ;78b66b2c123456788160 + and.l @(0x12345678:32,r3.w),@er1- ;78b66b2c12345678a160 + and.l @(0x12345678:32,r3.w),@+er1 ;78b66b2c123456789160 + and.l @(0x12345678:32,r3.w),@(0xffff9abc:16,er1) ;78b66b2c12345678c1609abc + and.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1) ;78b66b2c12345678c9609abcdef0 + and.l @(0x12345678:32,r3.w),@(0xffff9abc:16,r2l.b) ;78b66b2c12345678d2609abc + and.l @(0x12345678:32,r3.w),@(0xffff9abc:16,r2.w) ;78b66b2c12345678e2609abc + and.l @(0x12345678:32,r3.w),@(0xffff9abc:16,er2.l) ;78b66b2c12345678f2609abc + and.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2l.b) ;78b66b2c12345678da609abcdef0 + and.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2.w) ;78b66b2c12345678ea609abcdef0 + and.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,er2.l) ;78b66b2c12345678fa609abcdef0 + and.l @(0x12345678:32,r3.w),@0xffff9abc:16 ;78b66b2c1234567840609abc + and.l @(0x12345678:32,r3.w),@0x9abcdef0:32 ;78b66b2c1234567848609abcdef0 + + and.l @(0x12345678:32,er3.l),@er1 ;78b76b2c123456780160 + and.l @(0x12345678:32,er3.l),@(0xc:2,er1) ;78b76b2c123456783160 + and.l @(0x12345678:32,er3.l),@-er1 ;78b76b2c12345678b160 + and.l @(0x12345678:32,er3.l),@er1+ ;78b76b2c123456788160 + and.l @(0x12345678:32,er3.l),@er1- ;78b76b2c12345678a160 + and.l @(0x12345678:32,er3.l),@+er1 ;78b76b2c123456789160 + and.l @(0x12345678:32,er3.l),@(0xffff9abc:16,er1) ;78b76b2c12345678c1609abc + and.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1) ;78b76b2c12345678c9609abcdef0 + and.l @(0x12345678:32,er3.l),@(0xffff9abc:16,r2l.b) ;78b76b2c12345678d2609abc + and.l @(0x12345678:32,er3.l),@(0xffff9abc:16,r2.w) ;78b76b2c12345678e2609abc + and.l @(0x12345678:32,er3.l),@(0xffff9abc:16,er2.l) ;78b76b2c12345678f2609abc + and.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2l.b) ;78b76b2c12345678da609abcdef0 + and.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2.w) ;78b76b2c12345678ea609abcdef0 + and.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,er2.l) ;78b76b2c12345678fa609abcdef0 + and.l @(0x12345678:32,er3.l),@0xffff9abc:16 ;78b76b2c1234567840609abc + and.l @(0x12345678:32,er3.l),@0x9abcdef0:32 ;78b76b2c1234567848609abcdef0 + + and.l @0x1234:16,@er1 ;01046b0c12340160 + and.l @0x1234:16,@(0xc:2,er1) ;01046b0c12343160 + and.l @0x1234:16,@-er1 ;01046b0c1234b160 + and.l @0x1234:16,@er1+ ;01046b0c12348160 + and.l @0x1234:16,@er1- ;01046b0c1234a160 + and.l @0x1234:16,@+er1 ;01046b0c12349160 + and.l @0x1234:16,@(0xffff9abc:16,er1) ;01046b0c1234c1609abc + and.l @0x1234:16,@(0x9abcdef0:32,er1) ;01046b0c1234c9609abcdef0 + and.l @0x1234:16,@(0xffff9abc:16,r2l.b) ;01046b0c1234d2609abc + and.l @0x1234:16,@(0xffff9abc:16,r2.w) ;01046b0c1234e2609abc + and.l @0x1234:16,@(0xffff9abc:16,er2.l) ;01046b0c1234f2609abc + and.l @0x1234:16,@(0x9abcdef0:32,r2l.b) ;01046b0c1234da609abcdef0 + and.l @0x1234:16,@(0x9abcdef0:32,r2.w) ;01046b0c1234ea609abcdef0 + and.l @0x1234:16,@(0x9abcdef0:32,er2.l) ;01046b0c1234fa609abcdef0 + and.l @0x1234:16,@0xffff9abc:16 ;01046b0c123440609abc + and.l @0x1234:16,@0x9abcdef0:32 ;01046b0c123448609abcdef0 + + and.l @0x12345678:32,@er1 ;01046b2c123456780160 + and.l @0x12345678:32,@(0xc:2,er1) ;01046b2c123456783160 + and.l @0x12345678:32,@-er1 ;01046b2c12345678b160 + and.l @0x12345678:32,@er1+ ;01046b2c123456788160 + and.l @0x12345678:32,@er1- ;01046b2c12345678a160 + and.l @0x12345678:32,@+er1 ;01046b2c123456789160 + and.l @0x12345678:32,@(0xffff9abc:16,er1) ;01046b2c12345678c1609abc + and.l @0x12345678:32,@(0x9abcdef0:32,er1) ;01046b2c12345678c9609abcdef0 + and.l @0x12345678:32,@(0xffff9abc:16,r2l.b) ;01046b2c12345678d2609abc + and.l @0x12345678:32,@(0xffff9abc:16,r2.w) ;01046b2c12345678e2609abc + and.l @0x12345678:32,@(0xffff9abc:16,er2.l) ;01046b2c12345678f2609abc + and.l @0x12345678:32,@(0x9abcdef0:32,r2l.b) ;01046b2c12345678da609abcdef0 + and.l @0x12345678:32,@(0x9abcdef0:32,r2.w) ;01046b2c12345678ea609abcdef0 + and.l @0x12345678:32,@(0x9abcdef0:32,er2.l) ;01046b2c12345678fa609abcdef0 + and.l @0x12345678:32,@0xffff9abc:16 ;01046b2c1234567840609abc + and.l @0x12345678:32,@0x9abcdef0:32 ;01046b2c1234567848609abcdef0 + + .end diff --git a/gdb/testsuite/gdb.disasm/t11_logs.exp b/gdb/testsuite/gdb.disasm/t11_logs.exp new file mode 100644 index 0000000..85b2a9e --- /dev/null +++ b/gdb/testsuite/gdb.disasm/t11_logs.exp @@ -0,0 +1,2258 @@ +# Copyright (C) 2003 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# Please email any bugs, comments, and/or additions to this file to: +# bug-gdb@prep.ai.mit.edu + +# This file was written by Michael Snyder (msnyder@redhat.com) + +if $tracelevel then { + strace $tracelevel +} + +if ![istarget "h8300*-*-*"] { + verbose "Tests ignored for all but h8300s based targets." + return +} + +set prms_id 0 +set bug_id 0 + +set testfile "t11_logs" +set srcfile ${srcdir}/${subdir}/${testfile}.s +set objfile ${objdir}/${subdir}/${testfile}.o +set binfile ${objdir}/${subdir}/${testfile}.x + +set asm-flags ""; +set link-flags "-m h8300sxelf"; + + +if {[target_assemble $srcfile $objfile "${asm-flags}"] != ""} then { + gdb_suppress_entire_file "Testcase assembly failed, so all tests in this file will automatically fail." +} + +if {[target_link $objfile $binfile "${link-flags}"] != ""} then { + gdb_suppress_entire_file "Testcase link failed, so all tests in this file will automatically fail." +} + +gdb_start +gdb_reinitialize_dir $srcdir/$subdir +gdb_load $binfile + +gdb_test "x /i _start" "not.b\tr1h" \ + "not.b r1h" +gdb_test "x" "not.b\t@er1" \ + "not.b @er1" +gdb_test "x" "not.b\t@\\(0x3(:2|),er1\\)" \ + "not.b @(0x3:2,er1)" +gdb_test "x" "not.b\t@er1\\+" \ + "not.b @er1+" +gdb_test "x" "not.b\t@-er1" \ + "not.b @-er1" +gdb_test "x" "not.b\t@\\+er1" \ + "not.b @+er1" +gdb_test "x" "not.b\t@er1-" \ + "not.b @er1-" +gdb_test "x" "not.b\t@\\(0x1234(:16|),er1\\)" \ + "not.b @(0x1234:16,er1)" +gdb_test "x" "not.b\t@\\(0x12345678(:32|),er1\\)" \ + "not.b @(0x12345678:32,er1)" +gdb_test "x" "not.b\t@\\(0x1234(:16|),r2l.b\\)" \ + "not.b @(0x1234:16,r2l.b)" +gdb_test "x" "not.b\t@\\(0x1234(:16|),r2.w\\)" \ + "not.b @(0x1234:16,r2.w)" +gdb_test "x" "not.b\t@\\(0x1234(:16|),er2.l\\)" \ + "not.b @(0x1234:16,er2.l)" +gdb_test "x" "not.b\t@\\(0x12345678(:32|),r2l.b\\)" \ + "not.b @(0x12345678:32,r2l.b)" +gdb_test "x" "not.b\t@\\(0x12345678(:32|),r2.w\\)" \ + "not.b @(0x12345678:32,r2.w)" +gdb_test "x" "not.b\t@\\(0x12345678(:32|),er2.l\\)" \ + "not.b @(0x12345678:32,er2.l)" +gdb_test "x" "not.b\t@0x12(:8|)" \ + "not.b @0x12:8" +gdb_test "x" "not.b\t@0x1234(:16|)" \ + "not.b @0x1234:16" +gdb_test "x" "not.b\t@0x12345678(:32|)" \ + "not.b @0x12345678:32" +gdb_test "x" "not.w\tr1" \ + "not.w r1" +gdb_test "x" "not.w\t@er1" \ + "not.w @er1" +gdb_test "x" "not.w\t@\\(0x6(:2|),er1\\)" \ + "not.w @(0x6:2,er1)" +gdb_test "x" "not.w\t@er1\\+" \ + "not.w @er1+" +gdb_test "x" "not.w\t@-er1" \ + "not.w @-er1" +gdb_test "x" "not.w\t@\\+er1" \ + "not.w @+er1" +gdb_test "x" "not.w\t@er1-" \ + "not.w @er1-" +gdb_test "x" "not.w\t@\\(0x1234(:16|),er1\\)" \ + "not.w @(0x1234:16,er1)" +gdb_test "x" "not.w\t@\\(0x12345678(:32|),er1\\)" \ + "not.w @(0x12345678:32,er1)" +gdb_test "x" "not.w\t@\\(0x1234(:16|),r2l.b\\)" \ + "not.w @(0x1234:16,r2l.b)" +gdb_test "x" "not.w\t@\\(0x1234(:16|),r2.w\\)" \ + "not.w @(0x1234:16,r2.w)" +gdb_test "x" "not.w\t@\\(0x1234(:16|),er2.l\\)" \ + "not.w @(0x1234:16,er2.l)" +gdb_test "x" "not.w\t@\\(0x12345678(:32|),r2l.b\\)" \ + "not.w @(0x12345678:32,r2l.b)" +gdb_test "x" "not.w\t@\\(0x12345678(:32|),r2.w\\)" \ + "not.w @(0x12345678:32,r2.w)" +gdb_test "x" "not.w\t@\\(0x12345678(:32|),er2.l\\)" \ + "not.w @(0x12345678:32,er2.l)" +gdb_test "x" "not.w\t@0x1234(:16|)" \ + "not.w @0x1234:16" +gdb_test "x" "not.w\t@0x12345678(:32|)" \ + "not.w @0x12345678:32" +gdb_test "x" "not.l\ter1" \ + "not.l er1" +gdb_test "x" "not.l\t@er1" \ + "not.l @er1" +gdb_test "x" "not.l\t@\\(0xc(:2|),er1\\)" \ + "not.l @(0xc:2,er1)" +gdb_test "x" "not.l\t@er1\\+" \ + "not.l @er1+" +gdb_test "x" "not.l\t@-er1" \ + "not.l @-er1" +gdb_test "x" "not.l\t@\\+er1" \ + "not.l @+er1" +gdb_test "x" "not.l\t@er1-" \ + "not.l @er1-" +gdb_test "x" "not.l\t@\\(0x1234(:16|),er1\\)" \ + "not.l @(0x1234:16,er1)" +gdb_test "x" "not.l\t@\\(0x12345678(:32|),er1\\)" \ + "not.l @(0x12345678:32,er1)" +gdb_test "x" "not.l\t@\\(0x1234(:16|),r2l.b\\)" \ + "not.l @(0x1234:16,r2l.b)" +gdb_test "x" "not.l\t@\\(0x1234(:16|),r2.w\\)" \ + "not.l @(0x1234:16,r2.w)" +gdb_test "x" "not.l\t@\\(0x1234(:16|),er2.l\\)" \ + "not.l @(0x1234:16,er2.l)" +gdb_test "x" "not.l\t@\\(0x12345678(:32|),r2l.b\\)" \ + "not.l @(0x12345678:32,r2l.b)" +gdb_test "x" "not.l\t@\\(0x12345678(:32|),r2.w\\)" \ + "not.l @(0x12345678:32,r2.w)" +gdb_test "x" "not.l\t@\\(0x12345678(:32|),er2.l\\)" \ + "not.l @(0x12345678:32,er2.l)" +gdb_test "x" "not.l\t@0x1234(:16|)" \ + "not.l @0x1234:16" +gdb_test "x" "not.l\t@0x12345678(:32|)" \ + "not.l @0x12345678:32" +gdb_test "x" "shll.b\tr1h" \ + "shll.b r1h" +gdb_test "x" "shll.b\t@er1" \ + "shll.b @er1" +gdb_test "x" "shll.b\t@\\(0x3(:2|),er1\\)" \ + "shll.b @(0x3:2,er1)" +gdb_test "x" "shll.b\t@er1\\+" \ + "shll.b @er1+" +gdb_test "x" "shll.b\t@-er1" \ + "shll.b @-er1" +gdb_test "x" "shll.b\t@\\+er1" \ + "shll.b @+er1" +gdb_test "x" "shll.b\t@er1-" \ + "shll.b @er1-" +gdb_test "x" "shll.b\t@\\(0x1234(:16|),er1\\)" \ + "shll.b @(0x1234:16,er1)" +gdb_test "x" "shll.b\t@\\(0x12345678(:32|),er1\\)" \ + "shll.b @(0x12345678:32,er1)" +gdb_test "x" "shll.b\t@\\(0x1234(:16|),r2l.b\\)" \ + "shll.b @(0x1234:16,r2l.b)" +gdb_test "x" "shll.b\t@\\(0x1234(:16|),r2.w\\)" \ + "shll.b @(0x1234:16,r2.w)" +gdb_test "x" "shll.b\t@\\(0x1234(:16|),er2.l\\)" \ + "shll.b @(0x1234:16,er2.l)" +gdb_test "x" "shll.b\t@\\(0x12345678(:32|),r2l.b\\)" \ + "shll.b @(0x12345678:32,r2l.b)" +gdb_test "x" "shll.b\t@\\(0x12345678(:32|),r2.w\\)" \ + "shll.b @(0x12345678:32,r2.w)" +gdb_test "x" "shll.b\t@\\(0x12345678(:32|),er2.l\\)" \ + "shll.b @(0x12345678:32,er2.l)" +gdb_test "x" "shll.b\t@0x12(:8|)" \ + "shll.b @0x12:8" +gdb_test "x" "shll.b\t@0x1234(:16|)" \ + "shll.b @0x1234:16" +gdb_test "x" "shll.b\t@0x12345678(:32|)" \ + "shll.b @0x12345678:32" +gdb_test "x" "shll.w\tr1" \ + "shll.w r1" +gdb_test "x" "shll.w\t@er1" \ + "shll.w @er1" +gdb_test "x" "shll.w\t@\\(0x6(:2|),er1\\)" \ + "shll.w @(0x6:2,er1)" +gdb_test "x" "shll.w\t@er1\\+" \ + "shll.w @er1+" +gdb_test "x" "shll.w\t@-er1" \ + "shll.w @-er1" +gdb_test "x" "shll.w\t@\\+er1" \ + "shll.w @+er1" +gdb_test "x" "shll.w\t@er1-" \ + "shll.w @er1-" +gdb_test "x" "shll.w\t@\\(0x1234(:16|),er1\\)" \ + "shll.w @(0x1234:16,er1)" +gdb_test "x" "shll.w\t@\\(0x12345678(:32|),er1\\)" \ + "shll.w @(0x12345678:32,er1)" +gdb_test "x" "shll.w\t@\\(0x1234(:16|),r2l.b\\)" \ + "shll.w @(0x1234:16,r2l.b)" +gdb_test "x" "shll.w\t@\\(0x1234(:16|),r2.w\\)" \ + "shll.w @(0x1234:16,r2.w)" +gdb_test "x" "shll.w\t@\\(0x1234(:16|),er2.l\\)" \ + "shll.w @(0x1234:16,er2.l)" +gdb_test "x" "shll.w\t@\\(0x12345678(:32|),r2l.b\\)" \ + "shll.w @(0x12345678:32,r2l.b)" +gdb_test "x" "shll.w\t@\\(0x12345678(:32|),r2.w\\)" \ + "shll.w @(0x12345678:32,r2.w)" +gdb_test "x" "shll.w\t@\\(0x12345678(:32|),er2.l\\)" \ + "shll.w @(0x12345678:32,er2.l)" +gdb_test "x" "shll.w\t@0x1234(:16|)" \ + "shll.w @0x1234:16" +gdb_test "x" "shll.w\t@0x12345678(:32|)" \ + "shll.w @0x12345678:32" +gdb_test "x" "shll.l\ter1" \ + "shll.l er1" +gdb_test "x" "shll.l\t@er1" \ + "shll.l @er1" +gdb_test "x" "shll.l\t@\\(0xc(:2|),er1\\)" \ + "shll.l @(0xc:2,er1)" +gdb_test "x" "shll.l\t@er1\\+" \ + "shll.l @er1+" +gdb_test "x" "shll.l\t@-er1" \ + "shll.l @-er1" +gdb_test "x" "shll.l\t@\\+er1" \ + "shll.l @+er1" +gdb_test "x" "shll.l\t@er1-" \ + "shll.l @er1-" +gdb_test "x" "shll.l\t@\\(0x1234(:16|),er1\\)" \ + "shll.l @(0x1234:16,er1)" +gdb_test "x" "shll.l\t@\\(0x12345678(:32|),er1\\)" \ + "shll.l @(0x12345678:32,er1)" +gdb_test "x" "shll.l\t@\\(0x1234(:16|),r2l.b\\)" \ + "shll.l @(0x1234:16,r2l.b)" +gdb_test "x" "shll.l\t@\\(0x1234(:16|),r2.w\\)" \ + "shll.l @(0x1234:16,r2.w)" +gdb_test "x" "shll.l\t@\\(0x1234(:16|),er2.l\\)" \ + "shll.l @(0x1234:16,er2.l)" +gdb_test "x" "shll.l\t@\\(0x12345678(:32|),r2l.b\\)" \ + "shll.l @(0x12345678:32,r2l.b)" +gdb_test "x" "shll.l\t@\\(0x12345678(:32|),r2.w\\)" \ + "shll.l @(0x12345678:32,r2.w)" +gdb_test "x" "shll.l\t@\\(0x12345678(:32|),er2.l\\)" \ + "shll.l @(0x12345678:32,er2.l)" +gdb_test "x" "shll.l\t@0x1234(:16|)" \ + "shll.l @0x1234:16" +gdb_test "x" "shll.l\t@0x12345678(:32|)" \ + "shll.l @0x12345678:32" +gdb_test "x" "shll.b\t#2,r1h" \ + "shll.b #2,r1h" +gdb_test "x" "shll.b\t#2,@er1" \ + "shll.b #2,@er1" +gdb_test "x" "shll.b\t#2,@\\(0x3(:2|),er1\\)" \ + "shll.b #2,@(0x3:2,er1)" +gdb_test "x" "shll.b\t#2,@er1\\+" \ + "shll.b #2,@er1+" +gdb_test "x" "shll.b\t#2,@-er1" \ + "shll.b #2,@-er1" +gdb_test "x" "shll.b\t#2,@\\+er1" \ + "shll.b #2,@+er1" +gdb_test "x" "shll.b\t#2,@er1-" \ + "shll.b #2,@er1-" +gdb_test "x" "shll.b\t#2,@\\(0x1234(:16|),er1\\)" \ + "shll.b #2,@(0x1234:16,er1)" +gdb_test "x" "shll.b\t#2,@\\(0x12345678(:32|),er1\\)" \ + "shll.b #2,@(0x12345678:32,er1)" +gdb_test "x" "shll.b\t#2,@\\(0x1234(:16|),r2l.b\\)" \ + "shll.b #2,@(0x1234:16,r2l.b)" +gdb_test "x" "shll.b\t#2,@\\(0x1234(:16|),r2.w\\)" \ + "shll.b #2,@(0x1234:16,r2.w)" +gdb_test "x" "shll.b\t#2,@\\(0x1234(:16|),er2.l\\)" \ + "shll.b #2,@(0x1234:16,er2.l)" +gdb_test "x" "shll.b\t#2,@\\(0x12345678(:32|),r2l.b\\)" \ + "shll.b #2,@(0x12345678:32,r2l.b)" +gdb_test "x" "shll.b\t#2,@\\(0x12345678(:32|),r2.w\\)" \ + "shll.b #2,@(0x12345678:32,r2.w)" +gdb_test "x" "shll.b\t#2,@\\(0x12345678(:32|),er2.l\\)" \ + "shll.b #2,@(0x12345678:32,er2.l)" +gdb_test "x" "shll.b\t#2,@0x12(:8|)" \ + "shll.b #2,@0x12:8" +gdb_test "x" "shll.b\t#2,@0x1234(:16|)" \ + "shll.b #2,@0x1234:16" +gdb_test "x" "shll.b\t#2,@0x12345678(:32|)" \ + "shll.b #2,@0x12345678:32" +gdb_test "x" "shll.w\t#2,r1" \ + "shll.w #2,r1" +gdb_test "x" "shll.w\t#2,@er1" \ + "shll.w #2,@er1" +gdb_test "x" "shll.w\t#2,@\\(0x6(:2|),er1\\)" \ + "shll.w #2,@(0x6:2,er1)" +gdb_test "x" "shll.w\t#2,@er1\\+" \ + "shll.w #2,@er1+" +gdb_test "x" "shll.w\t#2,@-er1" \ + "shll.w #2,@-er1" +gdb_test "x" "shll.w\t#2,@\\+er1" \ + "shll.w #2,@+er1" +gdb_test "x" "shll.w\t#2,@er1-" \ + "shll.w #2,@er1-" +gdb_test "x" "shll.w\t#2,@\\(0x1234(:16|),er1\\)" \ + "shll.w #2,@(0x1234:16,er1)" +gdb_test "x" "shll.w\t#2,@\\(0x12345678(:32|),er1\\)" \ + "shll.w #2,@(0x12345678:32,er1)" +gdb_test "x" "shll.w\t#2,@\\(0x1234(:16|),r2l.b\\)" \ + "shll.w #2,@(0x1234:16,r2l.b)" +gdb_test "x" "shll.w\t#2,@\\(0x1234(:16|),r2.w\\)" \ + "shll.w #2,@(0x1234:16,r2.w)" +gdb_test "x" "shll.w\t#2,@\\(0x1234(:16|),er2.l\\)" \ + "shll.w #2,@(0x1234:16,er2.l)" +gdb_test "x" "shll.w\t#2,@\\(0x12345678(:32|),r2l.b\\)" \ + "shll.w #2,@(0x12345678:32,r2l.b)" +gdb_test "x" "shll.w\t#2,@\\(0x12345678(:32|),r2.w\\)" \ + "shll.w #2,@(0x12345678:32,r2.w)" +gdb_test "x" "shll.w\t#2,@\\(0x12345678(:32|),er2.l\\)" \ + "shll.w #2,@(0x12345678:32,er2.l)" +gdb_test "x" "shll.w\t#2,@0x1234(:16|)" \ + "shll.w #2,@0x1234:16" +gdb_test "x" "shll.w\t#2,@0x12345678(:32|)" \ + "shll.w #2,@0x12345678:32" +gdb_test "x" "shll.l\t#2,er1" \ + "shll.l #2,er1" +gdb_test "x" "shll.l\t#2,@er1" \ + "shll.l #2,@er1" +gdb_test "x" "shll.l\t#2,@\\(0xc(:2|),er1\\)" \ + "shll.l #2,@(0xc:2,er1)" +gdb_test "x" "shll.l\t#2,@er1\\+" \ + "shll.l #2,@er1+" +gdb_test "x" "shll.l\t#2,@-er1" \ + "shll.l #2,@-er1" +gdb_test "x" "shll.l\t#2,@\\+er1" \ + "shll.l #2,@+er1" +gdb_test "x" "shll.l\t#2,@er1-" \ + "shll.l #2,@er1-" +gdb_test "x" "shll.l\t#2,@\\(0x1234(:16|),er1\\)" \ + "shll.l #2,@(0x1234:16,er1)" +gdb_test "x" "shll.l\t#2,@\\(0x12345678(:32|),er1\\)" \ + "shll.l #2,@(0x12345678:32,er1)" +gdb_test "x" "shll.l\t#2,@\\(0x1234(:16|),r2l.b\\)" \ + "shll.l #2,@(0x1234:16,r2l.b)" +gdb_test "x" "shll.l\t#2,@\\(0x1234(:16|),r2.w\\)" \ + "shll.l #2,@(0x1234:16,r2.w)" +gdb_test "x" "shll.l\t#2,@\\(0x1234(:16|),er2.l\\)" \ + "shll.l #2,@(0x1234:16,er2.l)" +gdb_test "x" "shll.l\t#2,@\\(0x12345678(:32|),r2l.b\\)" \ + "shll.l #2,@(0x12345678:32,r2l.b)" +gdb_test "x" "shll.l\t#2,@\\(0x12345678(:32|),r2.w\\)" \ + "shll.l #2,@(0x12345678:32,r2.w)" +gdb_test "x" "shll.l\t#2,@\\(0x12345678(:32|),er2.l\\)" \ + "shll.l #2,@(0x12345678:32,er2.l)" +gdb_test "x" "shll.l\t#2,@0x1234(:16|)" \ + "shll.l #2,@0x1234:16" +gdb_test "x" "shll.l\t#2,@0x12345678(:32|)" \ + "shll.l #2,@0x12345678:32" +gdb_test "x" "shll.b\t#4,r1h" \ + "shll.b #4,r1h" +gdb_test "x" "shll.b\t#4,@er1" \ + "shll.b #4,@er1" +gdb_test "x" "shll.b\t#4,@\\(0x3(:2|),er1\\)" \ + "shll.b #4,@(0x3:2,er1)" +gdb_test "x" "shll.b\t#4,@er1\\+" \ + "shll.b #4,@er1+" +gdb_test "x" "shll.b\t#4,@-er1" \ + "shll.b #4,@-er1" +gdb_test "x" "shll.b\t#4,@\\+er1" \ + "shll.b #4,@+er1" +gdb_test "x" "shll.b\t#4,@er1-" \ + "shll.b #4,@er1-" +gdb_test "x" "shll.b\t#4,@\\(0x1234(:16|),er1\\)" \ + "shll.b #4,@(0x1234:16,er1)" +gdb_test "x" "shll.b\t#4,@\\(0x12345678(:32|),er1\\)" \ + "shll.b #4,@(0x12345678:32,er1)" +gdb_test "x" "shll.b\t#4,@\\(0x1234(:16|),r2l.b\\)" \ + "shll.b #4,@(0x1234:16,r2l.b)" +gdb_test "x" "shll.b\t#4,@\\(0x1234(:16|),r2.w\\)" \ + "shll.b #4,@(0x1234:16,r2.w)" +gdb_test "x" "shll.b\t#4,@\\(0x1234(:16|),er2.l\\)" \ + "shll.b #4,@(0x1234:16,er2.l)" +gdb_test "x" "shll.b\t#4,@\\(0x12345678(:32|),r2l.b\\)" \ + "shll.b #4,@(0x12345678:32,r2l.b)" +gdb_test "x" "shll.b\t#4,@\\(0x12345678(:32|),r2.w\\)" \ + "shll.b #4,@(0x12345678:32,r2.w)" +gdb_test "x" "shll.b\t#4,@\\(0x12345678(:32|),er2.l\\)" \ + "shll.b #4,@(0x12345678:32,er2.l)" +gdb_test "x" "shll.b\t#4,@0x12(:8|)" \ + "shll.b #4,@0x12:8" +gdb_test "x" "shll.b\t#4,@0x1234(:16|)" \ + "shll.b #4,@0x1234:16" +gdb_test "x" "shll.b\t#4,@0x12345678(:32|)" \ + "shll.b #4,@0x12345678:32" +gdb_test "x" "shll.w\t#4,r1" \ + "shll.w #4,r1" +gdb_test "x" "shll.w\t#4,@er1" \ + "shll.w #4,@er1" +gdb_test "x" "shll.w\t#4,@\\(0x6(:2|),er1\\)" \ + "shll.w #4,@(0x6:2,er1)" +gdb_test "x" "shll.w\t#4,@er1\\+" \ + "shll.w #4,@er1+" +gdb_test "x" "shll.w\t#4,@-er1" \ + "shll.w #4,@-er1" +gdb_test "x" "shll.w\t#4,@\\+er1" \ + "shll.w #4,@+er1" +gdb_test "x" "shll.w\t#4,@er1-" \ + "shll.w #4,@er1-" +gdb_test "x" "shll.w\t#4,@\\(0x1234(:16|),er1\\)" \ + "shll.w #4,@(0x1234:16,er1)" +gdb_test "x" "shll.w\t#4,@\\(0x12345678(:32|),er1\\)" \ + "shll.w #4,@(0x12345678:32,er1)" +gdb_test "x" "shll.w\t#4,@\\(0x1234(:16|),r2l.b\\)" \ + "shll.w #4,@(0x1234:16,r2l.b)" +gdb_test "x" "shll.w\t#4,@\\(0x1234(:16|),r2.w\\)" \ + "shll.w #4,@(0x1234:16,r2.w)" +gdb_test "x" "shll.w\t#4,@\\(0x1234(:16|),er2.l\\)" \ + "shll.w #4,@(0x1234:16,er2.l)" +gdb_test "x" "shll.w\t#4,@\\(0x12345678(:32|),r2l.b\\)" \ + "shll.w #4,@(0x12345678:32,r2l.b)" +gdb_test "x" "shll.w\t#4,@\\(0x12345678(:32|),r2.w\\)" \ + "shll.w #4,@(0x12345678:32,r2.w)" +gdb_test "x" "shll.w\t#4,@\\(0x12345678(:32|),er2.l\\)" \ + "shll.w #4,@(0x12345678:32,er2.l)" +gdb_test "x" "shll.w\t#4,@0x1234(:16|)" \ + "shll.w #4,@0x1234:16" +gdb_test "x" "shll.w\t#4,@0x12345678(:32|)" \ + "shll.w #4,@0x12345678:32" +gdb_test "x" "shll.l\t#4,er1" \ + "shll.l #4,er1" +gdb_test "x" "shll.l\t#4,@er1" \ + "shll.l #4,@er1" +gdb_test "x" "shll.l\t#4,@\\(0xc(:2|),er1\\)" \ + "shll.l #4,@(0xc:2,er1)" +gdb_test "x" "shll.l\t#4,@er1\\+" \ + "shll.l #4,@er1+" +gdb_test "x" "shll.l\t#4,@-er1" \ + "shll.l #4,@-er1" +gdb_test "x" "shll.l\t#4,@\\+er1" \ + "shll.l #4,@+er1" +gdb_test "x" "shll.l\t#4,@er1-" \ + "shll.l #4,@er1-" +gdb_test "x" "shll.l\t#4,@\\(0x1234(:16|),er1\\)" \ + "shll.l #4,@(0x1234:16,er1)" +gdb_test "x" "shll.l\t#4,@\\(0x12345678(:32|),er1\\)" \ + "shll.l #4,@(0x12345678:32,er1)" +gdb_test "x" "shll.l\t#4,@\\(0x1234(:16|),r2l.b\\)" \ + "shll.l #4,@(0x1234:16,r2l.b)" +gdb_test "x" "shll.l\t#4,@\\(0x1234(:16|),r2.w\\)" \ + "shll.l #4,@(0x1234:16,r2.w)" +gdb_test "x" "shll.l\t#4,@\\(0x1234(:16|),er2.l\\)" \ + "shll.l #4,@(0x1234:16,er2.l)" +gdb_test "x" "shll.l\t#4,@\\(0x12345678(:32|),r2l.b\\)" \ + "shll.l #4,@(0x12345678:32,r2l.b)" +gdb_test "x" "shll.l\t#4,@\\(0x12345678(:32|),r2.w\\)" \ + "shll.l #4,@(0x12345678:32,r2.w)" +gdb_test "x" "shll.l\t#4,@\\(0x12345678(:32|),er2.l\\)" \ + "shll.l #4,@(0x12345678:32,er2.l)" +gdb_test "x" "shll.l\t#4,@0x1234(:16|)" \ + "shll.l #4,@0x1234:16" +gdb_test "x" "shll.l\t#4,@0x12345678(:32|)" \ + "shll.l #4,@0x12345678:32" +gdb_test "x" "shll.w\t#8,r1" \ + "shll.w #8,r1" +gdb_test "x" "shll.w\t#8,@er1" \ + "shll.w #8,@er1" +gdb_test "x" "shll.w\t#8,@\\(0x6(:2|),er1\\)" \ + "shll.w #8,@(0x6:2,er1)" +gdb_test "x" "shll.w\t#8,@er1\\+" \ + "shll.w #8,@er1+" +gdb_test "x" "shll.w\t#8,@-er1" \ + "shll.w #8,@-er1" +gdb_test "x" "shll.w\t#8,@\\+er1" \ + "shll.w #8,@+er1" +gdb_test "x" "shll.w\t#8,@er1-" \ + "shll.w #8,@er1-" +gdb_test "x" "shll.w\t#8,@\\(0x1234(:16|),er1\\)" \ + "shll.w #8,@(0x1234:16,er1)" +gdb_test "x" "shll.w\t#8,@\\(0x12345678(:32|),er1\\)" \ + "shll.w #8,@(0x12345678:32,er1)" +gdb_test "x" "shll.w\t#8,@\\(0x1234(:16|),r2l.b\\)" \ + "shll.w #8,@(0x1234:16,r2l.b)" +gdb_test "x" "shll.w\t#8,@\\(0x1234(:16|),r2.w\\)" \ + "shll.w #8,@(0x1234:16,r2.w)" +gdb_test "x" "shll.w\t#8,@\\(0x1234(:16|),er2.l\\)" \ + "shll.w #8,@(0x1234:16,er2.l)" +gdb_test "x" "shll.w\t#8,@\\(0x12345678(:32|),r2l.b\\)" \ + "shll.w #8,@(0x12345678:32,r2l.b)" +gdb_test "x" "shll.w\t#8,@\\(0x12345678(:32|),r2.w\\)" \ + "shll.w #8,@(0x12345678:32,r2.w)" +gdb_test "x" "shll.w\t#8,@\\(0x12345678(:32|),er2.l\\)" \ + "shll.w #8,@(0x12345678:32,er2.l)" +gdb_test "x" "shll.w\t#8,@0x1234(:16|)" \ + "shll.w #8,@0x1234:16" +gdb_test "x" "shll.w\t#8,@0x12345678(:32|)" \ + "shll.w #8,@0x12345678:32" +gdb_test "x" "shll.l\t#8,er1" \ + "shll.l #8,er1" +gdb_test "x" "shll.l\t#8,@er1" \ + "shll.l #8,@er1" +gdb_test "x" "shll.l\t#8,@\\(0xc(:2|),er1\\)" \ + "shll.l #8,@(0xc:2,er1)" +gdb_test "x" "shll.l\t#8,@er1\\+" \ + "shll.l #8,@er1+" +gdb_test "x" "shll.l\t#8,@-er1" \ + "shll.l #8,@-er1" +gdb_test "x" "shll.l\t#8,@\\+er1" \ + "shll.l #8,@+er1" +gdb_test "x" "shll.l\t#8,@er1-" \ + "shll.l #8,@er1-" +gdb_test "x" "shll.l\t#8,@\\(0x1234(:16|),er1\\)" \ + "shll.l #8,@(0x1234:16,er1)" +gdb_test "x" "shll.l\t#8,@\\(0x12345678(:32|),er1\\)" \ + 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@(0x12345678:32,r2l.b)" +gdb_test "x" "shal.b\t@\\(0x12345678(:32|),r2.w\\)" \ + "shal.b @(0x12345678:32,r2.w)" +gdb_test "x" "shal.b\t@\\(0x12345678(:32|),er2.l\\)" \ + "shal.b @(0x12345678:32,er2.l)" +gdb_test "x" "shal.b\t@0x12(:8|)" \ + "shal.b @0x12:8" +gdb_test "x" "shal.b\t@0x1234(:16|)" \ + "shal.b @0x1234:16" +gdb_test "x" "shal.b\t@0x12345678(:32|)" \ + "shal.b @0x12345678:32" +gdb_test "x" "shal.w\tr1" \ + "shal.w r1" +gdb_test "x" "shal.w\t@er1" \ + "shal.w @er1" +gdb_test "x" "shal.w\t@\\(0x6(:2|),er1\\)" \ + "shal.w @(0x6:2,er1)" +gdb_test "x" "shal.w\t@er1\\+" \ + "shal.w @er1+" +gdb_test "x" "shal.w\t@-er1" \ + "shal.w @-er1" +gdb_test "x" "shal.w\t@\\+er1" \ + "shal.w @+er1" +gdb_test "x" "shal.w\t@er1-" \ + "shal.w @er1-" +gdb_test "x" "shal.w\t@\\(0x1234(:16|),er1\\)" \ + "shal.w @(0x1234:16,er1)" +gdb_test "x" "shal.w\t@\\(0x12345678(:32|),er1\\)" \ + "shal.w @(0x12345678:32,er1)" +gdb_test "x" "shal.w\t@\\(0x1234(:16|),r2l.b\\)" \ + "shal.w @(0x1234:16,r2l.b)" +gdb_test "x" "shal.w\t@\\(0x1234(:16|),r2.w\\)" \ + "shal.w @(0x1234:16,r2.w)" +gdb_test "x" "shal.w\t@\\(0x1234(:16|),er2.l\\)" \ + "shal.w @(0x1234:16,er2.l)" +gdb_test "x" "shal.w\t@\\(0x12345678(:32|),r2l.b\\)" \ + "shal.w @(0x12345678:32,r2l.b)" +gdb_test "x" "shal.w\t@\\(0x12345678(:32|),r2.w\\)" \ + "shal.w @(0x12345678:32,r2.w)" +gdb_test "x" "shal.w\t@\\(0x12345678(:32|),er2.l\\)" \ + "shal.w @(0x12345678:32,er2.l)" +gdb_test "x" "shal.w\t@0x1234(:16|)" \ + "shal.w @0x1234:16" +gdb_test "x" "shal.w\t@0x12345678(:32|)" \ + "shal.w @0x12345678:32" +gdb_test "x" "shal.l\ter1" \ + "shal.l er1" +gdb_test "x" "shal.l\t@er1" \ + "shal.l @er1" +gdb_test "x" "shal.l\t@\\(0xc(:2|),er1\\)" \ + "shal.l @(0xc:2,er1)" +gdb_test "x" "shal.l\t@er1\\+" \ + "shal.l @er1+" +gdb_test "x" "shal.l\t@-er1" \ + "shal.l @-er1" +gdb_test "x" "shal.l\t@\\+er1" \ + "shal.l @+er1" +gdb_test "x" "shal.l\t@er1-" \ + "shal.l @er1-" +gdb_test "x" "shal.l\t@\\(0x1234(:16|),er1\\)" \ + "shal.l @(0x1234:16,er1)" +gdb_test "x" "shal.l\t@\\(0x12345678(:32|),er1\\)" \ + "shal.l @(0x12345678:32,er1)" +gdb_test "x" "shal.l\t@\\(0x1234(:16|),r2l.b\\)" \ + "shal.l @(0x1234:16,r2l.b)" +gdb_test "x" "shal.l\t@\\(0x1234(:16|),r2.w\\)" \ + "shal.l @(0x1234:16,r2.w)" +gdb_test "x" "shal.l\t@\\(0x1234(:16|),er2.l\\)" \ + "shal.l @(0x1234:16,er2.l)" +gdb_test "x" "shal.l\t@\\(0x12345678(:32|),r2l.b\\)" \ + "shal.l @(0x12345678:32,r2l.b)" +gdb_test "x" "shal.l\t@\\(0x12345678(:32|),r2.w\\)" \ + "shal.l @(0x12345678:32,r2.w)" +gdb_test "x" "shal.l\t@\\(0x12345678(:32|),er2.l\\)" \ + "shal.l @(0x12345678:32,er2.l)" +gdb_test "x" "shal.l\t@0x1234(:16|)" \ + "shal.l @0x1234:16" +gdb_test "x" "shal.l\t@0x12345678(:32|)" \ + "shal.l @0x12345678:32" +gdb_test "x" "shal.b\t#2,r1h" \ + "shal.b #2,r1h" +gdb_test "x" "shal.b\t#2,@er1" \ + "shal.b #2,@er1" +gdb_test "x" "shal.b\t#2,@\\(0x3(:2|),er1\\)" \ + "shal.b #2,@(0x3:2,er1)" +gdb_test "x" "shal.b\t#2,@er1\\+" \ + "shal.b #2,@er1+" +gdb_test "x" "shal.b\t#2,@-er1" \ + "shal.b #2,@-er1" +gdb_test "x" "shal.b\t#2,@\\+er1" \ + "shal.b #2,@+er1" +gdb_test "x" "shal.b\t#2,@er1-" \ + "shal.b #2,@er1-" +gdb_test "x" "shal.b\t#2,@\\(0x1234(:16|),er1\\)" \ + "shal.b #2,@(0x1234:16,er1)" +gdb_test "x" "shal.b\t#2,@\\(0x12345678(:32|),er1\\)" \ + "shal.b #2,@(0x12345678:32,er1)" +gdb_test "x" "shal.b\t#2,@\\(0x1234(:16|),r2l.b\\)" \ + "shal.b #2,@(0x1234:16,r2l.b)" +gdb_test "x" "shal.b\t#2,@\\(0x1234(:16|),r2.w\\)" \ + "shal.b #2,@(0x1234:16,r2.w)" +gdb_test "x" "shal.b\t#2,@\\(0x1234(:16|),er2.l\\)" \ + "shal.b #2,@(0x1234:16,er2.l)" +gdb_test "x" "shal.b\t#2,@\\(0x12345678(:32|),r2l.b\\)" \ + "shal.b #2,@(0x12345678:32,r2l.b)" +gdb_test "x" "shal.b\t#2,@\\(0x12345678(:32|),r2.w\\)" \ + "shal.b #2,@(0x12345678:32,r2.w)" +gdb_test "x" "shal.b\t#2,@\\(0x12345678(:32|),er2.l\\)" \ + "shal.b #2,@(0x12345678:32,er2.l)" +gdb_test "x" "shal.b\t#2,@0x12(:8|)" \ + "shal.b #2,@0x12:8" +gdb_test "x" "shal.b\t#2,@0x1234(:16|)" \ + "shal.b #2,@0x1234:16" +gdb_test "x" "shal.b\t#2,@0x12345678(:32|)" \ + "shal.b #2,@0x12345678:32" +gdb_test "x" "shal.w\t#2,r1" \ + "shal.w #2,r1" +gdb_test "x" "shal.w\t#2,@er1" \ + "shal.w #2,@er1" +gdb_test "x" "shal.w\t#2,@\\(0x6(:2|),er1\\)" \ + "shal.w #2,@(0x6:2,er1)" +gdb_test "x" "shal.w\t#2,@er1\\+" \ + "shal.w #2,@er1+" +gdb_test "x" "shal.w\t#2,@-er1" \ + "shal.w #2,@-er1" +gdb_test "x" "shal.w\t#2,@\\+er1" \ + "shal.w #2,@+er1" +gdb_test "x" "shal.w\t#2,@er1-" \ + "shal.w #2,@er1-" +gdb_test "x" "shal.w\t#2,@\\(0x1234(:16|),er1\\)" \ + "shal.w #2,@(0x1234:16,er1)" +gdb_test "x" "shal.w\t#2,@\\(0x12345678(:32|),er1\\)" \ + "shal.w #2,@(0x12345678:32,er1)" +gdb_test "x" "shal.w\t#2,@\\(0x1234(:16|),r2l.b\\)" \ + "shal.w #2,@(0x1234:16,r2l.b)" +gdb_test "x" "shal.w\t#2,@\\(0x1234(:16|),r2.w\\)" \ + "shal.w #2,@(0x1234:16,r2.w)" +gdb_test "x" "shal.w\t#2,@\\(0x1234(:16|),er2.l\\)" \ + "shal.w #2,@(0x1234:16,er2.l)" +gdb_test "x" "shal.w\t#2,@\\(0x12345678(:32|),r2l.b\\)" \ + "shal.w #2,@(0x12345678:32,r2l.b)" +gdb_test "x" "shal.w\t#2,@\\(0x12345678(:32|),r2.w\\)" \ + "shal.w #2,@(0x12345678:32,r2.w)" +gdb_test "x" "shal.w\t#2,@\\(0x12345678(:32|),er2.l\\)" \ + "shal.w #2,@(0x12345678:32,er2.l)" +gdb_test "x" "shal.w\t#2,@0x1234(:16|)" \ + "shal.w #2,@0x1234:16" +gdb_test "x" "shal.w\t#2,@0x12345678(:32|)" \ + "shal.w #2,@0x12345678:32" +gdb_test "x" "shal.l\t#2,er1" \ + "shal.l #2,er1" +gdb_test "x" "shal.l\t#2,@er1" \ + "shal.l #2,@er1" +gdb_test "x" "shal.l\t#2,@\\(0xc(:2|),er1\\)" \ + "shal.l #2,@(0xc:2,er1)" +gdb_test "x" "shal.l\t#2,@er1\\+" \ + "shal.l #2,@er1+" +gdb_test "x" "shal.l\t#2,@-er1" \ + "shal.l #2,@-er1" +gdb_test "x" "shal.l\t#2,@\\+er1" \ + "shal.l #2,@+er1" +gdb_test "x" "shal.l\t#2,@er1-" \ + "shal.l #2,@er1-" +gdb_test "x" "shal.l\t#2,@\\(0x1234(:16|),er1\\)" \ + "shal.l #2,@(0x1234:16,er1)" +gdb_test "x" "shal.l\t#2,@\\(0x12345678(:32|),er1\\)" \ + "shal.l #2,@(0x12345678:32,er1)" +gdb_test "x" "shal.l\t#2,@\\(0x1234(:16|),r2l.b\\)" \ + "shal.l #2,@(0x1234:16,r2l.b)" +gdb_test "x" "shal.l\t#2,@\\(0x1234(:16|),r2.w\\)" \ + "shal.l #2,@(0x1234:16,r2.w)" +gdb_test "x" "shal.l\t#2,@\\(0x1234(:16|),er2.l\\)" \ + "shal.l #2,@(0x1234:16,er2.l)" +gdb_test "x" "shal.l\t#2,@\\(0x12345678(:32|),r2l.b\\)" \ + "shal.l #2,@(0x12345678:32,r2l.b)" +gdb_test "x" "shal.l\t#2,@\\(0x12345678(:32|),r2.w\\)" \ + "shal.l #2,@(0x12345678:32,r2.w)" +gdb_test "x" "shal.l\t#2,@\\(0x12345678(:32|),er2.l\\)" \ + "shal.l #2,@(0x12345678:32,er2.l)" +gdb_test "x" "shal.l\t#2,@0x1234(:16|)" \ + "shal.l #2,@0x1234:16" +gdb_test "x" "shal.l\t#2,@0x12345678(:32|)" \ + "shal.l #2,@0x12345678:32" +gdb_test "x" "shar.b\tr1h" \ + "shar.b r1h" +gdb_test "x" "shar.b\t@er1" \ + "shar.b @er1" +gdb_test "x" "shar.b\t@\\(0x3(:2|),er1\\)" \ + "shar.b @(0x3:2,er1)" +gdb_test "x" "shar.b\t@er1\\+" \ + "shar.b @er1+" +gdb_test "x" "shar.b\t@-er1" \ + "shar.b @-er1" +gdb_test "x" "shar.b\t@\\+er1" \ + "shar.b @+er1" +gdb_test "x" "shar.b\t@er1-" \ + "shar.b @er1-" +gdb_test "x" "shar.b\t@\\(0x1234(:16|),er1\\)" \ + "shar.b @(0x1234:16,er1)" +gdb_test "x" "shar.b\t@\\(0x12345678(:32|),er1\\)" \ + "shar.b @(0x12345678:32,er1)" +gdb_test "x" "shar.b\t@\\(0x1234(:16|),r2l.b\\)" \ + "shar.b @(0x1234:16,r2l.b)" +gdb_test "x" "shar.b\t@\\(0x1234(:16|),r2.w\\)" \ + "shar.b @(0x1234:16,r2.w)" +gdb_test "x" "shar.b\t@\\(0x1234(:16|),er2.l\\)" \ + "shar.b @(0x1234:16,er2.l)" +gdb_test "x" "shar.b\t@\\(0x12345678(:32|),r2l.b\\)" \ + "shar.b @(0x12345678:32,r2l.b)" +gdb_test "x" "shar.b\t@\\(0x12345678(:32|),r2.w\\)" \ + "shar.b @(0x12345678:32,r2.w)" +gdb_test "x" "shar.b\t@\\(0x12345678(:32|),er2.l\\)" \ + "shar.b @(0x12345678:32,er2.l)" +gdb_test "x" "shar.b\t@0x12(:8|)" \ + "shar.b @0x12:8" +gdb_test "x" "shar.b\t@0x1234(:16|)" \ + "shar.b @0x1234:16" +gdb_test "x" "shar.b\t@0x12345678(:32|)" \ + "shar.b @0x12345678:32" +gdb_test "x" "shar.w\tr1" \ + "shar.w r1" +gdb_test "x" "shar.w\t@er1" \ + "shar.w @er1" +gdb_test "x" "shar.w\t@\\(0x6(:2|),er1\\)" \ + "shar.w @(0x6:2,er1)" +gdb_test "x" "shar.w\t@er1\\+" \ + "shar.w @er1+" +gdb_test "x" "shar.w\t@-er1" \ + "shar.w @-er1" +gdb_test "x" "shar.w\t@\\+er1" \ + "shar.w @+er1" +gdb_test "x" "shar.w\t@er1-" \ + "shar.w @er1-" +gdb_test "x" "shar.w\t@\\(0x1234(:16|),er1\\)" \ + "shar.w @(0x1234:16,er1)" +gdb_test "x" "shar.w\t@\\(0x12345678(:32|),er1\\)" \ + "shar.w @(0x12345678:32,er1)" +gdb_test "x" "shar.w\t@\\(0x1234(:16|),r2l.b\\)" \ + "shar.w @(0x1234:16,r2l.b)" +gdb_test "x" "shar.w\t@\\(0x1234(:16|),r2.w\\)" \ + "shar.w @(0x1234:16,r2.w)" +gdb_test "x" "shar.w\t@\\(0x1234(:16|),er2.l\\)" \ + "shar.w @(0x1234:16,er2.l)" +gdb_test "x" "shar.w\t@\\(0x12345678(:32|),r2l.b\\)" \ + "shar.w @(0x12345678:32,r2l.b)" +gdb_test "x" "shar.w\t@\\(0x12345678(:32|),r2.w\\)" \ + "shar.w @(0x12345678:32,r2.w)" +gdb_test "x" "shar.w\t@\\(0x12345678(:32|),er2.l\\)" \ + "shar.w @(0x12345678:32,er2.l)" +gdb_test "x" "shar.w\t@0x1234(:16|)" \ + "shar.w @0x1234:16" +gdb_test "x" "shar.w\t@0x12345678(:32|)" \ + "shar.w @0x12345678:32" +gdb_test "x" "shar.l\ter1" \ + "shar.l er1" +gdb_test "x" "shar.l\t@er1" \ + "shar.l @er1" +gdb_test "x" "shar.l\t@\\(0xc(:2|),er1\\)" \ + "shar.l @(0xc:2,er1)" +gdb_test "x" "shar.l\t@er1\\+" \ + "shar.l @er1+" +gdb_test "x" "shar.l\t@-er1" \ + "shar.l @-er1" +gdb_test "x" "shar.l\t@\\+er1" \ + "shar.l @+er1" +gdb_test "x" "shar.l\t@er1-" \ + "shar.l @er1-" +gdb_test "x" "shar.l\t@\\(0x1234(:16|),er1\\)" \ + "shar.l @(0x1234:16,er1)" +gdb_test "x" "shar.l\t@\\(0x12345678(:32|),er1\\)" \ + "shar.l @(0x12345678:32,er1)" +gdb_test "x" "shar.l\t@\\(0x1234(:16|),r2l.b\\)" \ + "shar.l @(0x1234:16,r2l.b)" +gdb_test "x" "shar.l\t@\\(0x1234(:16|),r2.w\\)" \ + "shar.l @(0x1234:16,r2.w)" +gdb_test "x" "shar.l\t@\\(0x1234(:16|),er2.l\\)" \ + "shar.l @(0x1234:16,er2.l)" +gdb_test "x" "shar.l\t@\\(0x12345678(:32|),r2l.b\\)" \ + "shar.l @(0x12345678:32,r2l.b)" +gdb_test "x" "shar.l\t@\\(0x12345678(:32|),r2.w\\)" \ + "shar.l @(0x12345678:32,r2.w)" +gdb_test "x" "shar.l\t@\\(0x12345678(:32|),er2.l\\)" \ + "shar.l @(0x12345678:32,er2.l)" +gdb_test "x" "shar.l\t@0x1234(:16|)" \ + "shar.l @0x1234:16" +gdb_test "x" "shar.l\t@0x12345678(:32|)" \ + "shar.l @0x12345678:32" +gdb_test "x" "shar.b\t#2,r1h" \ + "shar.b #2,r1h" +gdb_test "x" "shar.b\t#2,@er1" \ + "shar.b #2,@er1" +gdb_test "x" "shar.b\t#2,@\\(0x3(:2|),er1\\)" \ + "shar.b #2,@(0x3:2,er1)" +gdb_test "x" "shar.b\t#2,@er1\\+" \ + "shar.b #2,@er1+" +gdb_test "x" "shar.b\t#2,@-er1" \ + "shar.b #2,@-er1" +gdb_test "x" "shar.b\t#2,@\\+er1" \ + "shar.b #2,@+er1" +gdb_test "x" "shar.b\t#2,@er1-" \ + "shar.b #2,@er1-" +gdb_test "x" "shar.b\t#2,@\\(0x1234(:16|),er1\\)" \ + "shar.b #2,@(0x1234:16,er1)" +gdb_test "x" "shar.b\t#2,@\\(0x12345678(:32|),er1\\)" \ + "shar.b #2,@(0x12345678:32,er1)" +gdb_test "x" "shar.b\t#2,@\\(0x1234(:16|),r2l.b\\)" \ + "shar.b #2,@(0x1234:16,r2l.b)" +gdb_test "x" "shar.b\t#2,@\\(0x1234(:16|),r2.w\\)" \ + "shar.b #2,@(0x1234:16,r2.w)" +gdb_test "x" "shar.b\t#2,@\\(0x1234(:16|),er2.l\\)" \ + "shar.b #2,@(0x1234:16,er2.l)" +gdb_test "x" "shar.b\t#2,@\\(0x12345678(:32|),r2l.b\\)" \ + "shar.b #2,@(0x12345678:32,r2l.b)" +gdb_test "x" "shar.b\t#2,@\\(0x12345678(:32|),r2.w\\)" \ + "shar.b #2,@(0x12345678:32,r2.w)" +gdb_test "x" "shar.b\t#2,@\\(0x12345678(:32|),er2.l\\)" \ + "shar.b #2,@(0x12345678:32,er2.l)" +gdb_test "x" "shar.b\t#2,@0x12(:8|)" \ + "shar.b #2,@0x12:8" +gdb_test "x" "shar.b\t#2,@0x1234(:16|)" \ + "shar.b #2,@0x1234:16" +gdb_test "x" "shar.b\t#2,@0x12345678(:32|)" \ + "shar.b #2,@0x12345678:32" +gdb_test "x" "shar.w\t#2,r1" \ + "shar.w #2,r1" +gdb_test "x" "shar.w\t#2,@er1" \ + "shar.w #2,@er1" +gdb_test "x" "shar.w\t#2,@\\(0x6(:2|),er1\\)" \ + "shar.w #2,@(0x6:2,er1)" +gdb_test "x" "shar.w\t#2,@er1\\+" \ + "shar.w #2,@er1+" +gdb_test "x" "shar.w\t#2,@-er1" \ + "shar.w #2,@-er1" +gdb_test "x" "shar.w\t#2,@\\+er1" \ + "shar.w #2,@+er1" +gdb_test "x" "shar.w\t#2,@er1-" \ + "shar.w #2,@er1-" +gdb_test "x" "shar.w\t#2,@\\(0x1234(:16|),er1\\)" \ + "shar.w #2,@(0x1234:16,er1)" +gdb_test "x" "shar.w\t#2,@\\(0x12345678(:32|),er1\\)" \ + "shar.w #2,@(0x12345678:32,er1)" +gdb_test "x" "shar.w\t#2,@\\(0x1234(:16|),r2l.b\\)" \ + "shar.w #2,@(0x1234:16,r2l.b)" +gdb_test "x" "shar.w\t#2,@\\(0x1234(:16|),r2.w\\)" \ + "shar.w #2,@(0x1234:16,r2.w)" +gdb_test "x" "shar.w\t#2,@\\(0x1234(:16|),er2.l\\)" \ + "shar.w #2,@(0x1234:16,er2.l)" +gdb_test "x" "shar.w\t#2,@\\(0x12345678(:32|),r2l.b\\)" \ + "shar.w #2,@(0x12345678:32,r2l.b)" +gdb_test "x" "shar.w\t#2,@\\(0x12345678(:32|),r2.w\\)" \ + "shar.w #2,@(0x12345678:32,r2.w)" +gdb_test "x" "shar.w\t#2,@\\(0x12345678(:32|),er2.l\\)" \ + "shar.w #2,@(0x12345678:32,er2.l)" +gdb_test "x" "shar.w\t#2,@0x1234(:16|)" \ + "shar.w #2,@0x1234:16" +gdb_test "x" "shar.w\t#2,@0x12345678(:32|)" \ + "shar.w #2,@0x12345678:32" +gdb_test "x" "shar.l\t#2,er1" \ + "shar.l #2,er1" +gdb_test "x" "shar.l\t#2,@er1" \ + "shar.l #2,@er1" +gdb_test "x" "shar.l\t#2,@\\(0xc(:2|),er1\\)" \ + "shar.l #2,@(0xc:2,er1)" +gdb_test "x" "shar.l\t#2,@er1\\+" \ + "shar.l #2,@er1+" +gdb_test "x" "shar.l\t#2,@-er1" \ + "shar.l #2,@-er1" +gdb_test "x" "shar.l\t#2,@\\+er1" \ + "shar.l #2,@+er1" +gdb_test "x" "shar.l\t#2,@er1-" \ + "shar.l #2,@er1-" +gdb_test "x" "shar.l\t#2,@\\(0x1234(:16|),er1\\)" \ + "shar.l #2,@(0x1234:16,er1)" +gdb_test "x" "shar.l\t#2,@\\(0x12345678(:32|),er1\\)" \ + "shar.l #2,@(0x12345678:32,er1)" +gdb_test "x" "shar.l\t#2,@\\(0x1234(:16|),r2l.b\\)" \ + "shar.l #2,@(0x1234:16,r2l.b)" +gdb_test "x" "shar.l\t#2,@\\(0x1234(:16|),r2.w\\)" \ + "shar.l #2,@(0x1234:16,r2.w)" +gdb_test "x" "shar.l\t#2,@\\(0x1234(:16|),er2.l\\)" \ + "shar.l #2,@(0x1234:16,er2.l)" +gdb_test "x" "shar.l\t#2,@\\(0x12345678(:32|),r2l.b\\)" \ + "shar.l #2,@(0x12345678:32,r2l.b)" +gdb_test "x" "shar.l\t#2,@\\(0x12345678(:32|),r2.w\\)" \ + "shar.l #2,@(0x12345678:32,r2.w)" +gdb_test "x" "shar.l\t#2,@\\(0x12345678(:32|),er2.l\\)" \ + "shar.l #2,@(0x12345678:32,er2.l)" +gdb_test "x" "shar.l\t#2,@0x1234(:16|)" \ + "shar.l #2,@0x1234:16" +gdb_test "x" "shar.l\t#2,@0x12345678(:32|)" \ + "shar.l #2,@0x12345678:32" +gdb_test "x" "rotxl.b\tr1h" \ + "rotxl.b r1h" +gdb_test "x" "rotxl.b\t@er1" \ + "rotxl.b @er1" +gdb_test "x" "rotxl.b\t@\\(0x3(:2|),er1\\)" \ + "rotxl.b @(0x3:2,er1)" +gdb_test "x" "rotxl.b\t@er1\\+" \ + "rotxl.b @er1+" +gdb_test "x" "rotxl.b\t@-er1" \ + "rotxl.b @-er1" +gdb_test "x" "rotxl.b\t@\\+er1" \ + "rotxl.b @+er1" +gdb_test "x" "rotxl.b\t@er1-" \ + "rotxl.b @er1-" +gdb_test "x" "rotxl.b\t@\\(0x1234(:16|),er1\\)" \ + "rotxl.b @(0x1234:16,er1)" +gdb_test "x" "rotxl.b\t@\\(0x12345678(:32|),er1\\)" \ + "rotxl.b @(0x12345678:32,er1)" +gdb_test "x" "rotxl.b\t@\\(0x1234(:16|),r2l.b\\)" \ + "rotxl.b @(0x1234:16,r2l.b)" +gdb_test "x" "rotxl.b\t@\\(0x1234(:16|),r2.w\\)" \ + "rotxl.b @(0x1234:16,r2.w)" +gdb_test "x" "rotxl.b\t@\\(0x1234(:16|),er2.l\\)" \ + "rotxl.b @(0x1234:16,er2.l)" +gdb_test "x" "rotxl.b\t@\\(0x12345678(:32|),r2l.b\\)" \ + "rotxl.b @(0x12345678:32,r2l.b)" +gdb_test "x" "rotxl.b\t@\\(0x12345678(:32|),r2.w\\)" \ + "rotxl.b @(0x12345678:32,r2.w)" +gdb_test "x" "rotxl.b\t@\\(0x12345678(:32|),er2.l\\)" \ + "rotxl.b @(0x12345678:32,er2.l)" +gdb_test "x" "rotxl.b\t@0x12(:8|)" \ + "rotxl.b @0x12:8" +gdb_test "x" "rotxl.b\t@0x1234(:16|)" \ + "rotxl.b @0x1234:16" +gdb_test "x" "rotxl.b\t@0x12345678(:32|)" \ + "rotxl.b @0x12345678:32" +gdb_test "x" "rotxl.w\tr1" \ + "rotxl.w r1" +gdb_test "x" "rotxl.w\t@er1" \ + "rotxl.w @er1" +gdb_test "x" "rotxl.w\t@\\(0x6(:2|),er1\\)" \ + "rotxl.w @(0x6:2,er1)" +gdb_test "x" "rotxl.w\t@er1\\+" \ + "rotxl.w @er1+" +gdb_test "x" "rotxl.w\t@-er1" \ + "rotxl.w @-er1" +gdb_test "x" "rotxl.w\t@\\+er1" \ + "rotxl.w @+er1" +gdb_test "x" "rotxl.w\t@er1-" \ + "rotxl.w @er1-" +gdb_test "x" "rotxl.w\t@\\(0x1234(:16|),er1\\)" \ + "rotxl.w @(0x1234:16,er1)" +gdb_test "x" "rotxl.w\t@\\(0x12345678(:32|),er1\\)" \ + "rotxl.w @(0x12345678:32,er1)" +gdb_test "x" "rotxl.w\t@\\(0x1234(:16|),r2l.b\\)" \ + "rotxl.w @(0x1234:16,r2l.b)" +gdb_test "x" "rotxl.w\t@\\(0x1234(:16|),r2.w\\)" \ + "rotxl.w @(0x1234:16,r2.w)" +gdb_test "x" "rotxl.w\t@\\(0x1234(:16|),er2.l\\)" \ + "rotxl.w @(0x1234:16,er2.l)" +gdb_test "x" "rotxl.w\t@\\(0x12345678(:32|),r2l.b\\)" \ + "rotxl.w @(0x12345678:32,r2l.b)" +gdb_test "x" "rotxl.w\t@\\(0x12345678(:32|),r2.w\\)" \ + "rotxl.w @(0x12345678:32,r2.w)" +gdb_test "x" "rotxl.w\t@\\(0x12345678(:32|),er2.l\\)" \ + "rotxl.w @(0x12345678:32,er2.l)" +gdb_test "x" "rotxl.w\t@0x1234(:16|)" \ + "rotxl.w @0x1234:16" +gdb_test "x" "rotxl.w\t@0x12345678(:32|)" \ + "rotxl.w @0x12345678:32" +gdb_test "x" "rotxl.l\ter1" \ + "rotxl.l er1" +gdb_test "x" "rotxl.l\t@er1" \ + "rotxl.l @er1" +gdb_test "x" "rotxl.l\t@\\(0xc(:2|),er1\\)" \ + "rotxl.l @(0xc:2,er1)" +gdb_test "x" "rotxl.l\t@er1\\+" \ + "rotxl.l @er1+" +gdb_test "x" "rotxl.l\t@-er1" \ + "rotxl.l @-er1" +gdb_test "x" "rotxl.l\t@\\+er1" \ + "rotxl.l @+er1" +gdb_test "x" "rotxl.l\t@er1-" \ + "rotxl.l @er1-" +gdb_test "x" "rotxl.l\t@\\(0x1234(:16|),er1\\)" \ + "rotxl.l @(0x1234:16,er1)" +gdb_test "x" "rotxl.l\t@\\(0x12345678(:32|),er1\\)" \ + "rotxl.l @(0x12345678:32,er1)" +gdb_test "x" "rotxl.l\t@\\(0x1234(:16|),r2l.b\\)" \ + "rotxl.l @(0x1234:16,r2l.b)" +gdb_test "x" "rotxl.l\t@\\(0x1234(:16|),r2.w\\)" \ + "rotxl.l @(0x1234:16,r2.w)" +gdb_test "x" "rotxl.l\t@\\(0x1234(:16|),er2.l\\)" \ + "rotxl.l @(0x1234:16,er2.l)" +gdb_test "x" "rotxl.l\t@\\(0x12345678(:32|),r2l.b\\)" \ + "rotxl.l @(0x12345678:32,r2l.b)" +gdb_test "x" "rotxl.l\t@\\(0x12345678(:32|),r2.w\\)" \ + "rotxl.l @(0x12345678:32,r2.w)" +gdb_test "x" "rotxl.l\t@\\(0x12345678(:32|),er2.l\\)" \ + "rotxl.l @(0x12345678:32,er2.l)" +gdb_test "x" "rotxl.l\t@0x1234(:16|)" \ + "rotxl.l @0x1234:16" +gdb_test "x" "rotxl.l\t@0x12345678(:32|)" \ + "rotxl.l @0x12345678:32" +gdb_test "x" "rotxl.b\t#2,r1h" \ + "rotxl.b #2,r1h" +gdb_test "x" "rotxl.b\t#2,@er1" \ + "rotxl.b #2,@er1" +gdb_test "x" "rotxl.b\t#2,@\\(0x3(:2|),er1\\)" \ + "rotxl.b #2,@(0x3:2,er1)" +gdb_test "x" "rotxl.b\t#2,@er1\\+" \ + "rotxl.b #2,@er1+" +gdb_test "x" "rotxl.b\t#2,@-er1" \ + "rotxl.b #2,@-er1" +gdb_test "x" "rotxl.b\t#2,@\\+er1" \ + "rotxl.b #2,@+er1" +gdb_test "x" "rotxl.b\t#2,@er1-" \ + "rotxl.b #2,@er1-" +gdb_test "x" "rotxl.b\t#2,@\\(0x1234(:16|),er1\\)" \ + "rotxl.b #2,@(0x1234:16,er1)" +gdb_test "x" "rotxl.b\t#2,@\\(0x12345678(:32|),er1\\)" \ + "rotxl.b #2,@(0x12345678:32,er1)" +gdb_test "x" "rotxl.b\t#2,@\\(0x1234(:16|),r2l.b\\)" \ + "rotxl.b #2,@(0x1234:16,r2l.b)" +gdb_test "x" "rotxl.b\t#2,@\\(0x1234(:16|),r2.w\\)" \ + "rotxl.b #2,@(0x1234:16,r2.w)" +gdb_test "x" "rotxl.b\t#2,@\\(0x1234(:16|),er2.l\\)" \ + "rotxl.b #2,@(0x1234:16,er2.l)" +gdb_test "x" "rotxl.b\t#2,@\\(0x12345678(:32|),r2l.b\\)" \ + "rotxl.b #2,@(0x12345678:32,r2l.b)" +gdb_test "x" "rotxl.b\t#2,@\\(0x12345678(:32|),r2.w\\)" \ + "rotxl.b #2,@(0x12345678:32,r2.w)" +gdb_test "x" "rotxl.b\t#2,@\\(0x12345678(:32|),er2.l\\)" \ + "rotxl.b #2,@(0x12345678:32,er2.l)" +gdb_test "x" "rotxl.b\t#2,@0x12(:8|)" \ + "rotxl.b #2,@0x12:8" +gdb_test "x" "rotxl.b\t#2,@0x1234(:16|)" \ + "rotxl.b #2,@0x1234:16" +gdb_test "x" "rotxl.b\t#2,@0x12345678(:32|)" \ + "rotxl.b #2,@0x12345678:32" +gdb_test "x" "rotxl.w\t#2,r1" \ + "rotxl.w #2,r1" +gdb_test "x" "rotxl.w\t#2,@er1" \ + "rotxl.w #2,@er1" +gdb_test "x" "rotxl.w\t#2,@\\(0x6(:2|),er1\\)" \ + "rotxl.w #2,@(0x6:2,er1)" +gdb_test "x" "rotxl.w\t#2,@er1\\+" \ + "rotxl.w #2,@er1+" +gdb_test "x" "rotxl.w\t#2,@-er1" \ + "rotxl.w #2,@-er1" +gdb_test "x" "rotxl.w\t#2,@\\+er1" \ + "rotxl.w #2,@+er1" +gdb_test "x" "rotxl.w\t#2,@er1-" \ + "rotxl.w #2,@er1-" +gdb_test "x" "rotxl.w\t#2,@\\(0x1234(:16|),er1\\)" \ + "rotxl.w #2,@(0x1234:16,er1)" +gdb_test "x" "rotxl.w\t#2,@\\(0x12345678(:32|),er1\\)" \ + "rotxl.w #2,@(0x12345678:32,er1)" +gdb_test "x" "rotxl.w\t#2,@\\(0x1234(:16|),r2l.b\\)" \ + "rotxl.w #2,@(0x1234:16,r2l.b)" +gdb_test "x" "rotxl.w\t#2,@\\(0x1234(:16|),r2.w\\)" \ + "rotxl.w #2,@(0x1234:16,r2.w)" +gdb_test "x" "rotxl.w\t#2,@\\(0x1234(:16|),er2.l\\)" \ + "rotxl.w #2,@(0x1234:16,er2.l)" +gdb_test "x" "rotxl.w\t#2,@\\(0x12345678(:32|),r2l.b\\)" \ + "rotxl.w #2,@(0x12345678:32,r2l.b)" +gdb_test "x" "rotxl.w\t#2,@\\(0x12345678(:32|),r2.w\\)" \ + "rotxl.w #2,@(0x12345678:32,r2.w)" +gdb_test "x" "rotxl.w\t#2,@\\(0x12345678(:32|),er2.l\\)" \ + "rotxl.w #2,@(0x12345678:32,er2.l)" +gdb_test "x" "rotxl.w\t#2,@0x1234(:16|)" \ + "rotxl.w #2,@0x1234:16" +gdb_test "x" "rotxl.w\t#2,@0x12345678(:32|)" \ + "rotxl.w #2,@0x12345678:32" +gdb_test "x" "rotxl.l\t#2,er1" \ + "rotxl.l #2,er1" +gdb_test "x" "rotxl.l\t#2,@er1" \ + "rotxl.l #2,@er1" +gdb_test "x" "rotxl.l\t#2,@\\(0xc(:2|),er1\\)" \ + "rotxl.l #2,@(0xc:2,er1)" +gdb_test "x" "rotxl.l\t#2,@er1\\+" \ + "rotxl.l #2,@er1+" +gdb_test "x" "rotxl.l\t#2,@-er1" \ + "rotxl.l #2,@-er1" +gdb_test "x" "rotxl.l\t#2,@\\+er1" \ + "rotxl.l #2,@+er1" +gdb_test "x" "rotxl.l\t#2,@er1-" \ + "rotxl.l #2,@er1-" +gdb_test "x" "rotxl.l\t#2,@\\(0x1234(:16|),er1\\)" \ + "rotxl.l #2,@(0x1234:16,er1)" +gdb_test "x" "rotxl.l\t#2,@\\(0x12345678(:32|),er1\\)" \ + "rotxl.l #2,@(0x12345678:32,er1)" +gdb_test "x" "rotxl.l\t#2,@\\(0x1234(:16|),r2l.b\\)" \ + "rotxl.l #2,@(0x1234:16,r2l.b)" +gdb_test "x" "rotxl.l\t#2,@\\(0x1234(:16|),r2.w\\)" \ + "rotxl.l #2,@(0x1234:16,r2.w)" +gdb_test "x" "rotxl.l\t#2,@\\(0x1234(:16|),er2.l\\)" \ + "rotxl.l #2,@(0x1234:16,er2.l)" +gdb_test "x" "rotxl.l\t#2,@\\(0x12345678(:32|),r2l.b\\)" \ + "rotxl.l #2,@(0x12345678:32,r2l.b)" +gdb_test "x" "rotxl.l\t#2,@\\(0x12345678(:32|),r2.w\\)" \ + "rotxl.l #2,@(0x12345678:32,r2.w)" +gdb_test "x" "rotxl.l\t#2,@\\(0x12345678(:32|),er2.l\\)" \ + "rotxl.l #2,@(0x12345678:32,er2.l)" +gdb_test "x" "rotxl.l\t#2,@0x1234(:16|)" \ + "rotxl.l #2,@0x1234:16" +gdb_test "x" "rotxl.l\t#2,@0x12345678(:32|)" \ + "rotxl.l #2,@0x12345678:32" +gdb_test "x" "rotxr.b\tr1h" \ + "rotxr.b r1h" +gdb_test "x" "rotxr.b\t@er1" \ + "rotxr.b @er1" +gdb_test "x" "rotxr.b\t@\\(0x3(:2|),er1\\)" \ + "rotxr.b @(0x3:2,er1)" +gdb_test "x" "rotxr.b\t@er1\\+" \ + "rotxr.b @er1+" +gdb_test "x" "rotxr.b\t@-er1" \ + "rotxr.b @-er1" +gdb_test "x" "rotxr.b\t@\\+er1" \ + "rotxr.b @+er1" +gdb_test "x" "rotxr.b\t@er1-" \ + "rotxr.b @er1-" +gdb_test "x" "rotxr.b\t@\\(0x1234(:16|),er1\\)" \ + "rotxr.b @(0x1234:16,er1)" +gdb_test "x" "rotxr.b\t@\\(0x12345678(:32|),er1\\)" \ + "rotxr.b @(0x12345678:32,er1)" +gdb_test "x" "rotxr.b\t@\\(0x1234(:16|),r2l.b\\)" \ + "rotxr.b @(0x1234:16,r2l.b)" +gdb_test "x" "rotxr.b\t@\\(0x1234(:16|),r2.w\\)" \ + "rotxr.b @(0x1234:16,r2.w)" +gdb_test "x" "rotxr.b\t@\\(0x1234(:16|),er2.l\\)" \ + "rotxr.b @(0x1234:16,er2.l)" +gdb_test "x" "rotxr.b\t@\\(0x12345678(:32|),r2l.b\\)" \ + "rotxr.b @(0x12345678:32,r2l.b)" +gdb_test "x" "rotxr.b\t@\\(0x12345678(:32|),r2.w\\)" \ + "rotxr.b @(0x12345678:32,r2.w)" +gdb_test "x" "rotxr.b\t@\\(0x12345678(:32|),er2.l\\)" \ + "rotxr.b @(0x12345678:32,er2.l)" +gdb_test "x" "rotxr.b\t@0x12(:8|)" \ + "rotxr.b @0x12:8" +gdb_test "x" "rotxr.b\t@0x1234(:16|)" \ + "rotxr.b @0x1234:16" +gdb_test "x" "rotxr.b\t@0x12345678(:32|)" \ + "rotxr.b @0x12345678:32" +gdb_test "x" "rotxr.w\tr1" \ + "rotxr.w r1" +gdb_test "x" "rotxr.w\t@er1" \ + "rotxr.w @er1" +gdb_test "x" "rotxr.w\t@\\(0x6(:2|),er1\\)" \ + "rotxr.w @(0x6:2,er1)" +gdb_test "x" "rotxr.w\t@er1\\+" \ + "rotxr.w @er1+" +gdb_test "x" "rotxr.w\t@-er1" \ + "rotxr.w @-er1" +gdb_test "x" "rotxr.w\t@\\+er1" \ + "rotxr.w @+er1" +gdb_test "x" "rotxr.w\t@er1-" \ + "rotxr.w @er1-" +gdb_test "x" "rotxr.w\t@\\(0x1234(:16|),er1\\)" \ + "rotxr.w @(0x1234:16,er1)" +gdb_test "x" "rotxr.w\t@\\(0x12345678(:32|),er1\\)" \ + "rotxr.w @(0x12345678:32,er1)" +gdb_test "x" "rotxr.w\t@\\(0x1234(:16|),r2l.b\\)" \ + "rotxr.w @(0x1234:16,r2l.b)" +gdb_test "x" "rotxr.w\t@\\(0x1234(:16|),r2.w\\)" \ + "rotxr.w @(0x1234:16,r2.w)" +gdb_test "x" "rotxr.w\t@\\(0x1234(:16|),er2.l\\)" \ + "rotxr.w @(0x1234:16,er2.l)" +gdb_test "x" "rotxr.w\t@\\(0x12345678(:32|),r2l.b\\)" \ + "rotxr.w @(0x12345678:32,r2l.b)" +gdb_test "x" "rotxr.w\t@\\(0x12345678(:32|),r2.w\\)" \ + "rotxr.w @(0x12345678:32,r2.w)" +gdb_test "x" "rotxr.w\t@\\(0x12345678(:32|),er2.l\\)" \ + "rotxr.w @(0x12345678:32,er2.l)" +gdb_test "x" "rotxr.w\t@0x1234(:16|)" \ + "rotxr.w @0x1234:16" +gdb_test "x" "rotxr.w\t@0x12345678(:32|)" \ + "rotxr.w @0x12345678:32" +gdb_test "x" "rotxr.l\ter1" \ + "rotxr.l er1" +gdb_test "x" "rotxr.l\t@er1" \ + "rotxr.l @er1" +gdb_test "x" "rotxr.l\t@\\(0xc(:2|),er1\\)" \ + "rotxr.l @(0xc:2,er1)" +gdb_test "x" "rotxr.l\t@er1\\+" \ + "rotxr.l @er1+" +gdb_test "x" "rotxr.l\t@-er1" \ + "rotxr.l @-er1" +gdb_test "x" "rotxr.l\t@\\+er1" \ + "rotxr.l @+er1" +gdb_test "x" "rotxr.l\t@er1-" \ + "rotxr.l @er1-" +gdb_test "x" "rotxr.l\t@\\(0x1234(:16|),er1\\)" \ + "rotxr.l @(0x1234:16,er1)" +gdb_test "x" "rotxr.l\t@\\(0x12345678(:32|),er1\\)" \ + "rotxr.l @(0x12345678:32,er1)" +gdb_test "x" "rotxr.l\t@\\(0x1234(:16|),r2l.b\\)" \ + "rotxr.l @(0x1234:16,r2l.b)" +gdb_test "x" "rotxr.l\t@\\(0x1234(:16|),r2.w\\)" \ + "rotxr.l @(0x1234:16,r2.w)" +gdb_test "x" "rotxr.l\t@\\(0x1234(:16|),er2.l\\)" \ + "rotxr.l @(0x1234:16,er2.l)" +gdb_test "x" "rotxr.l\t@\\(0x12345678(:32|),r2l.b\\)" \ + "rotxr.l @(0x12345678:32,r2l.b)" +gdb_test "x" "rotxr.l\t@\\(0x12345678(:32|),r2.w\\)" \ + "rotxr.l @(0x12345678:32,r2.w)" +gdb_test "x" "rotxr.l\t@\\(0x12345678(:32|),er2.l\\)" \ + "rotxr.l @(0x12345678:32,er2.l)" +gdb_test "x" "rotxr.l\t@0x1234(:16|)" \ + "rotxr.l @0x1234:16" +gdb_test "x" "rotxr.l\t@0x12345678(:32|)" \ + "rotxr.l @0x12345678:32" +gdb_test "x" "rotxr.b\t#2,r1h" \ + "rotxr.b #2,r1h" +gdb_test "x" "rotxr.b\t#2,@er1" \ + "rotxr.b #2,@er1" +gdb_test "x" "rotxr.b\t#2,@\\(0x3(:2|),er1\\)" \ + "rotxr.b #2,@(0x3:2,er1)" +gdb_test "x" "rotxr.b\t#2,@er1\\+" \ + "rotxr.b #2,@er1+" +gdb_test "x" "rotxr.b\t#2,@-er1" \ + "rotxr.b #2,@-er1" +gdb_test "x" "rotxr.b\t#2,@\\+er1" \ + "rotxr.b #2,@+er1" +gdb_test "x" "rotxr.b\t#2,@er1-" \ + "rotxr.b #2,@er1-" +gdb_test "x" "rotxr.b\t#2,@\\(0x1234(:16|),er1\\)" \ + "rotxr.b #2,@(0x1234:16,er1)" +gdb_test "x" "rotxr.b\t#2,@\\(0x12345678(:32|),er1\\)" \ + "rotxr.b #2,@(0x12345678:32,er1)" +gdb_test "x" "rotxr.b\t#2,@\\(0x1234(:16|),r2l.b\\)" \ + "rotxr.b #2,@(0x1234:16,r2l.b)" +gdb_test "x" "rotxr.b\t#2,@\\(0x1234(:16|),r2.w\\)" \ + "rotxr.b #2,@(0x1234:16,r2.w)" +gdb_test "x" "rotxr.b\t#2,@\\(0x1234(:16|),er2.l\\)" \ + "rotxr.b #2,@(0x1234:16,er2.l)" +gdb_test "x" "rotxr.b\t#2,@\\(0x12345678(:32|),r2l.b\\)" \ + "rotxr.b #2,@(0x12345678:32,r2l.b)" +gdb_test "x" "rotxr.b\t#2,@\\(0x12345678(:32|),r2.w\\)" \ + "rotxr.b #2,@(0x12345678:32,r2.w)" +gdb_test "x" "rotxr.b\t#2,@\\(0x12345678(:32|),er2.l\\)" \ + "rotxr.b #2,@(0x12345678:32,er2.l)" +gdb_test "x" "rotxr.b\t#2,@0x12(:8|)" \ + "rotxr.b #2,@0x12:8" +gdb_test "x" "rotxr.b\t#2,@0x1234(:16|)" \ + "rotxr.b #2,@0x1234:16" +gdb_test "x" "rotxr.b\t#2,@0x12345678(:32|)" \ + "rotxr.b #2,@0x12345678:32" +gdb_test "x" "rotxr.w\t#2,r1" \ + "rotxr.w #2,r1" +gdb_test "x" "rotxr.w\t#2,@er1" \ + "rotxr.w #2,@er1" +gdb_test "x" "rotxr.w\t#2,@\\(0x6(:2|),er1\\)" \ + "rotxr.w #2,@(0x6:2,er1)" +gdb_test "x" "rotxr.w\t#2,@er1\\+" \ + "rotxr.w #2,@er1+" +gdb_test "x" "rotxr.w\t#2,@-er1" \ + "rotxr.w #2,@-er1" +gdb_test "x" "rotxr.w\t#2,@\\+er1" \ + "rotxr.w #2,@+er1" +gdb_test "x" "rotxr.w\t#2,@er1-" \ + "rotxr.w #2,@er1-" +gdb_test "x" "rotxr.w\t#2,@\\(0x1234(:16|),er1\\)" \ + "rotxr.w #2,@(0x1234:16,er1)" +gdb_test "x" "rotxr.w\t#2,@\\(0x12345678(:32|),er1\\)" \ + "rotxr.w #2,@(0x12345678:32,er1)" +gdb_test "x" "rotxr.w\t#2,@\\(0x1234(:16|),r2l.b\\)" \ + "rotxr.w #2,@(0x1234:16,r2l.b)" +gdb_test "x" "rotxr.w\t#2,@\\(0x1234(:16|),r2.w\\)" \ + "rotxr.w #2,@(0x1234:16,r2.w)" +gdb_test "x" "rotxr.w\t#2,@\\(0x1234(:16|),er2.l\\)" \ + "rotxr.w #2,@(0x1234:16,er2.l)" +gdb_test "x" "rotxr.w\t#2,@\\(0x12345678(:32|),r2l.b\\)" \ + "rotxr.w #2,@(0x12345678:32,r2l.b)" +gdb_test "x" "rotxr.w\t#2,@\\(0x12345678(:32|),r2.w\\)" \ + "rotxr.w #2,@(0x12345678:32,r2.w)" +gdb_test "x" "rotxr.w\t#2,@\\(0x12345678(:32|),er2.l\\)" \ + "rotxr.w #2,@(0x12345678:32,er2.l)" +gdb_test "x" "rotxr.w\t#2,@0x1234(:16|)" \ + "rotxr.w #2,@0x1234:16" +gdb_test "x" "rotxr.w\t#2,@0x12345678(:32|)" \ + "rotxr.w #2,@0x12345678:32" +gdb_test "x" "rotxr.l\t#2,er1" \ + "rotxr.l #2,er1" +gdb_test "x" "rotxr.l\t#2,@er1" \ + "rotxr.l #2,@er1" +gdb_test "x" "rotxr.l\t#2,@\\(0xc(:2|),er1\\)" \ + "rotxr.l #2,@(0xc:2,er1)" +gdb_test "x" "rotxr.l\t#2,@er1\\+" \ + "rotxr.l #2,@er1+" +gdb_test "x" "rotxr.l\t#2,@-er1" \ + "rotxr.l #2,@-er1" +gdb_test "x" "rotxr.l\t#2,@\\+er1" \ + "rotxr.l #2,@+er1" +gdb_test "x" "rotxr.l\t#2,@er1-" \ + "rotxr.l #2,@er1-" +gdb_test "x" "rotxr.l\t#2,@\\(0x1234(:16|),er1\\)" \ + "rotxr.l #2,@(0x1234:16,er1)" +gdb_test "x" "rotxr.l\t#2,@\\(0x12345678(:32|),er1\\)" \ + "rotxr.l #2,@(0x12345678:32,er1)" +gdb_test "x" "rotxr.l\t#2,@\\(0x1234(:16|),r2l.b\\)" \ + "rotxr.l #2,@(0x1234:16,r2l.b)" +gdb_test "x" "rotxr.l\t#2,@\\(0x1234(:16|),r2.w\\)" \ + "rotxr.l #2,@(0x1234:16,r2.w)" +gdb_test "x" "rotxr.l\t#2,@\\(0x1234(:16|),er2.l\\)" \ + "rotxr.l #2,@(0x1234:16,er2.l)" +gdb_test "x" "rotxr.l\t#2,@\\(0x12345678(:32|),r2l.b\\)" \ + "rotxr.l #2,@(0x12345678:32,r2l.b)" +gdb_test "x" "rotxr.l\t#2,@\\(0x12345678(:32|),r2.w\\)" \ + "rotxr.l #2,@(0x12345678:32,r2.w)" +gdb_test "x" "rotxr.l\t#2,@\\(0x12345678(:32|),er2.l\\)" \ + "rotxr.l #2,@(0x12345678:32,er2.l)" +gdb_test "x" "rotxr.l\t#2,@0x1234(:16|)" \ + "rotxr.l #2,@0x1234:16" +gdb_test "x" "rotxr.l\t#2,@0x12345678(:32|)" \ + "rotxr.l #2,@0x12345678:32" +gdb_test "x" "rotl.b\tr1h" \ + "rotl.b r1h" +gdb_test "x" "rotl.b\t@er1" \ + "rotl.b @er1" +gdb_test "x" "rotl.b\t@\\(0x3(:2|),er1\\)" \ + "rotl.b @(0x3:2,er1)" +gdb_test "x" "rotl.b\t@er1\\+" \ + "rotl.b @er1+" +gdb_test "x" "rotl.b\t@-er1" \ + "rotl.b @-er1" +gdb_test "x" "rotl.b\t@\\+er1" \ + "rotl.b @+er1" +gdb_test "x" "rotl.b\t@er1-" \ + "rotl.b @er1-" +gdb_test "x" "rotl.b\t@\\(0x1234(:16|),er1\\)" \ + "rotl.b @(0x1234:16,er1)" +gdb_test "x" "rotl.b\t@\\(0x12345678(:32|),er1\\)" \ + "rotl.b @(0x12345678:32,er1)" +gdb_test "x" "rotl.b\t@\\(0x1234(:16|),r2l.b\\)" \ + "rotl.b @(0x1234:16,r2l.b)" +gdb_test "x" "rotl.b\t@\\(0x1234(:16|),r2.w\\)" \ + "rotl.b @(0x1234:16,r2.w)" +gdb_test "x" "rotl.b\t@\\(0x1234(:16|),er2.l\\)" \ + "rotl.b @(0x1234:16,er2.l)" +gdb_test "x" "rotl.b\t@\\(0x12345678(:32|),r2l.b\\)" \ + "rotl.b @(0x12345678:32,r2l.b)" +gdb_test "x" "rotl.b\t@\\(0x12345678(:32|),r2.w\\)" \ + "rotl.b @(0x12345678:32,r2.w)" +gdb_test "x" "rotl.b\t@\\(0x12345678(:32|),er2.l\\)" \ + "rotl.b @(0x12345678:32,er2.l)" +gdb_test "x" "rotl.b\t@0x12(:8|)" \ + "rotl.b @0x12:8" +gdb_test "x" "rotl.b\t@0x1234(:16|)" \ + "rotl.b @0x1234:16" +gdb_test "x" "rotl.b\t@0x12345678(:32|)" \ + "rotl.b @0x12345678:32" +gdb_test "x" "rotl.w\tr1" \ + "rotl.w r1" +gdb_test "x" "rotl.w\t@er1" \ + "rotl.w @er1" +gdb_test "x" "rotl.w\t@\\(0x6(:2|),er1\\)" \ + "rotl.w @(0x6:2,er1)" +gdb_test "x" "rotl.w\t@-er1" \ + "rotl.w @-er1" +gdb_test "x" "rotl.w\t@er1\\+" \ + "rotl.w @er1+" +gdb_test "x" "rotl.w\t@er1-" \ + "rotl.w @er1-" +gdb_test "x" "rotl.w\t@\\+er1" \ + "rotl.w @+er1" +gdb_test "x" "rotl.w\t@\\(0x1234(:16|),er1\\)" \ + "rotl.w @(0x1234:16,er1)" +gdb_test "x" "rotl.w\t@\\(0x12345678(:32|),er1\\)" \ + "rotl.w @(0x12345678:32,er1)" +gdb_test "x" "rotl.w\t@\\(0x1234(:16|),r2l.b\\)" \ + "rotl.w @(0x1234:16,r2l.b)" +gdb_test "x" "rotl.w\t@\\(0x1234(:16|),r2.w\\)" \ + "rotl.w @(0x1234:16,r2.w)" +gdb_test "x" "rotl.w\t@\\(0x1234(:16|),er2.l\\)" \ + "rotl.w @(0x1234:16,er2.l)" +gdb_test "x" "rotl.w\t@\\(0x12345678(:32|),r2l.b\\)" \ + "rotl.w @(0x12345678:32,r2l.b)" +gdb_test "x" "rotl.w\t@\\(0x12345678(:32|),r2.w\\)" \ + "rotl.w @(0x12345678:32,r2.w)" +gdb_test "x" "rotl.w\t@\\(0x12345678(:32|),er2.l\\)" \ + "rotl.w @(0x12345678:32,er2.l)" +gdb_test "x" "rotl.w\t@0x1234(:16|)" \ + "rotl.w @0x1234:16" +gdb_test "x" "rotl.w\t@0x12345678(:32|)" \ + "rotl.w @0x12345678:32" +gdb_test "x" "rotl.l\ter1" \ + "rotl.l er1" +gdb_test "x" "rotl.l\t@er1" \ + "rotl.l @er1" +gdb_test "x" "rotl.l\t@\\(0xc(:2|),er1\\)" \ + "rotl.l @(0xc:2,er1)" +gdb_test "x" "rotl.l\t@er1\\+" \ + "rotl.l @er1+" +gdb_test "x" "rotl.l\t@-er1" \ + "rotl.l @-er1" +gdb_test "x" "rotl.l\t@\\+er1" \ + "rotl.l @+er1" +gdb_test "x" "rotl.l\t@er1-" \ + "rotl.l @er1-" +gdb_test "x" "rotl.l\t@\\(0x1234(:16|),er1\\)" \ + "rotl.l @(0x1234:16,er1)" +gdb_test "x" "rotl.l\t@\\(0x12345678(:32|),er1\\)" \ + "rotl.l @(0x12345678:32,er1)" +gdb_test "x" "rotl.l\t@\\(0x1234(:16|),r2l.b\\)" \ + "rotl.l @(0x1234:16,r2l.b)" +gdb_test "x" "rotl.l\t@\\(0x1234(:16|),r2.w\\)" \ + "rotl.l @(0x1234:16,r2.w)" +gdb_test "x" "rotl.l\t@\\(0x1234(:16|),er2.l\\)" \ + "rotl.l @(0x1234:16,er2.l)" +gdb_test "x" "rotl.l\t@\\(0x12345678(:32|),r2l.b\\)" \ + "rotl.l @(0x12345678:32,r2l.b)" +gdb_test "x" "rotl.l\t@\\(0x12345678(:32|),r2.w\\)" \ + "rotl.l @(0x12345678:32,r2.w)" +gdb_test "x" "rotl.l\t@\\(0x12345678(:32|),er2.l\\)" \ + "rotl.l @(0x12345678:32,er2.l)" +gdb_test "x" "rotl.l\t@0x1234(:16|)" \ + "rotl.l @0x1234:16" +gdb_test "x" "rotl.l\t@0x12345678(:32|)" \ + "rotl.l @0x12345678:32" +gdb_test "x" "rotl.b\t#2,r1h" \ + "rotl.b #2,r1h" +gdb_test "x" "rotl.b\t#2,@er1" \ + "rotl.b #2,@er1" +gdb_test "x" "rotl.b\t#2,@\\(0x3(:2|),er1\\)" \ + "rotl.b #2,@(0x3:2,er1)" +gdb_test "x" "rotl.b\t#2,@er1\\+" \ + "rotl.b #2,@er1+" +gdb_test "x" "rotl.b\t#2,@-er1" \ + "rotl.b #2,@-er1" +gdb_test "x" "rotl.b\t#2,@\\+er1" \ + "rotl.b #2,@+er1" +gdb_test "x" "rotl.b\t#2,@er1-" \ + "rotl.b #2,@er1-" +gdb_test "x" "rotl.b\t#2,@\\(0x1234(:16|),er1\\)" \ + "rotl.b #2,@(0x1234:16,er1)" +gdb_test "x" "rotl.b\t#2,@\\(0x12345678(:32|),er1\\)" \ + "rotl.b #2,@(0x12345678:32,er1)" +gdb_test "x" "rotl.b\t#2,@\\(0x1234(:16|),r2l.b\\)" \ + "rotl.b #2,@(0x1234:16,r2l.b)" +gdb_test "x" "rotl.b\t#2,@\\(0x1234(:16|),r2.w\\)" \ + "rotl.b #2,@(0x1234:16,r2.w)" +gdb_test "x" "rotl.b\t#2,@\\(0x1234(:16|),er2.l\\)" \ + "rotl.b #2,@(0x1234:16,er2.l)" +gdb_test "x" "rotl.b\t#2,@\\(0x12345678(:32|),r2l.b\\)" \ + "rotl.b #2,@(0x12345678:32,r2l.b)" +gdb_test "x" "rotl.b\t#2,@\\(0x12345678(:32|),r2.w\\)" \ + "rotl.b #2,@(0x12345678:32,r2.w)" +gdb_test "x" "rotl.b\t#2,@\\(0x12345678(:32|),er2.l\\)" \ + "rotl.b #2,@(0x12345678:32,er2.l)" +gdb_test "x" "rotl.b\t#2,@0x12(:8|)" \ + "rotl.b #2,@0x12:8" +gdb_test "x" "rotl.b\t#2,@0x1234(:16|)" \ + "rotl.b #2,@0x1234:16" +gdb_test "x" "rotl.b\t#2,@0x12345678(:32|)" \ + "rotl.b #2,@0x12345678:32" +gdb_test "x" "rotl.w\t#2,r1" \ + "rotl.w #2,r1" +gdb_test "x" "rotl.w\t#2,@er1" \ + "rotl.w #2,@er1" +gdb_test "x" "rotl.w\t#2,@\\(0x6(:2|),er1\\)" \ + "rotl.w #2,@(0x6:2,er1)" +gdb_test "x" "rotl.w\t#2,@er1\\+" \ + "rotl.w #2,@er1+" +gdb_test "x" "rotl.w\t#2,@-er1" \ + "rotl.w #2,@-er1" +gdb_test "x" "rotl.w\t#2,@\\+er1" \ + "rotl.w #2,@+er1" +gdb_test "x" "rotl.w\t#2,@er1-" \ + "rotl.w #2,@er1-" +gdb_test "x" "rotl.w\t#2,@\\(0x1234(:16|),er1\\)" \ + "rotl.w #2,@(0x1234:16,er1)" +gdb_test "x" "rotl.w\t#2,@\\(0x12345678(:32|),er1\\)" \ + "rotl.w #2,@(0x12345678:32,er1)" +gdb_test "x" "rotl.w\t#2,@\\(0x1234(:16|),r2l.b\\)" \ + "rotl.w #2,@(0x1234:16,r2l.b)" +gdb_test "x" "rotl.w\t#2,@\\(0x1234(:16|),r2.w\\)" \ + "rotl.w #2,@(0x1234:16,r2.w)" +gdb_test "x" "rotl.w\t#2,@\\(0x1234(:16|),er2.l\\)" \ + "rotl.w #2,@(0x1234:16,er2.l)" +gdb_test "x" "rotl.w\t#2,@\\(0x12345678(:32|),r2l.b\\)" \ + "rotl.w #2,@(0x12345678:32,r2l.b)" +gdb_test "x" "rotl.w\t#2,@\\(0x12345678(:32|),r2.w\\)" \ + "rotl.w #2,@(0x12345678:32,r2.w)" +gdb_test "x" "rotl.w\t#2,@\\(0x12345678(:32|),er2.l\\)" \ + "rotl.w #2,@(0x12345678:32,er2.l)" +gdb_test "x" "rotl.w\t#2,@0x1234(:16|)" \ + "rotl.w #2,@0x1234:16" +gdb_test "x" "rotl.w\t#2,@0x12345678(:32|)" \ + "rotl.w #2,@0x12345678:32" +gdb_test "x" "rotl.l\t#2,er1" \ + "rotl.l #2,er1" +gdb_test "x" "rotl.l\t#2,@er1" \ + "rotl.l #2,@er1" +gdb_test "x" "rotl.l\t#2,@\\(0xc(:2|),er1\\)" \ + "rotl.l #2,@(0xc:2,er1)" +gdb_test "x" "rotl.l\t#2,@er1\\+" \ + "rotl.l #2,@er1+" +gdb_test "x" "rotl.l\t#2,@-er1" \ + "rotl.l #2,@-er1" +gdb_test "x" "rotl.l\t#2,@\\+er1" \ + "rotl.l #2,@+er1" +gdb_test "x" "rotl.l\t#2,@er1-" \ + "rotl.l #2,@er1-" +gdb_test "x" "rotl.l\t#2,@\\(0x1234(:16|),er1\\)" \ + "rotl.l #2,@(0x1234:16,er1)" +gdb_test "x" "rotl.l\t#2,@\\(0x12345678(:32|),er1\\)" \ + "rotl.l #2,@(0x12345678:32,er1)" +gdb_test "x" "rotl.l\t#2,@\\(0x1234(:16|),r2l.b\\)" \ + "rotl.l #2,@(0x1234:16,r2l.b)" +gdb_test "x" "rotl.l\t#2,@\\(0x1234(:16|),r2.w\\)" \ + "rotl.l #2,@(0x1234:16,r2.w)" +gdb_test "x" "rotl.l\t#2,@\\(0x1234(:16|),er2.l\\)" \ + "rotl.l #2,@(0x1234:16,er2.l)" +gdb_test "x" "rotl.l\t#2,@\\(0x12345678(:32|),r2l.b\\)" \ + "rotl.l #2,@(0x12345678:32,r2l.b)" +gdb_test "x" "rotl.l\t#2,@\\(0x12345678(:32|),r2.w\\)" \ + "rotl.l #2,@(0x12345678:32,r2.w)" +gdb_test "x" "rotl.l\t#2,@\\(0x12345678(:32|),er2.l\\)" \ + "rotl.l #2,@(0x12345678:32,er2.l)" +gdb_test "x" "rotl.l\t#2,@0x1234(:16|)" \ + "rotl.l #2,@0x1234:16" +gdb_test "x" "rotl.l\t#2,@0x12345678(:32|)" \ + "rotl.l #2,@0x12345678:32" +gdb_test "x" "rotr.b\tr1h" \ + "rotr.b r1h" +gdb_test "x" "rotr.b\t@er1" \ + "rotr.b @er1" +gdb_test "x" "rotr.b\t@\\(0x3(:2|),er1\\)" \ + "rotr.b @(0x3:2,er1)" +gdb_test "x" "rotr.b\t@er1\\+" \ + "rotr.b @er1+" +gdb_test "x" "rotr.b\t@-er1" \ + "rotr.b @-er1" +gdb_test "x" "rotr.b\t@\\+er1" \ + "rotr.b @+er1" +gdb_test "x" "rotr.b\t@er1-" \ + "rotr.b @er1-" +gdb_test "x" "rotr.b\t@\\(0x1234(:16|),er1\\)" \ + "rotr.b @(0x1234:16,er1)" +gdb_test "x" "rotr.b\t@\\(0x12345678(:32|),er1\\)" \ + "rotr.b @(0x12345678:32,er1)" +gdb_test "x" "rotr.b\t@\\(0x1234(:16|),r2l.b\\)" \ + "rotr.b @(0x1234:16,r2l.b)" +gdb_test "x" "rotr.b\t@\\(0x1234(:16|),r2.w\\)" \ + "rotr.b @(0x1234:16,r2.w)" +gdb_test "x" "rotr.b\t@\\(0x1234(:16|),er2.l\\)" \ + "rotr.b @(0x1234:16,er2.l)" +gdb_test "x" "rotr.b\t@\\(0x12345678(:32|),r2l.b\\)" \ + "rotr.b @(0x12345678:32,r2l.b)" +gdb_test "x" "rotr.b\t@\\(0x12345678(:32|),r2.w\\)" \ + "rotr.b @(0x12345678:32,r2.w)" +gdb_test "x" "rotr.b\t@\\(0x12345678(:32|),er2.l\\)" \ + "rotr.b @(0x12345678:32,er2.l)" +gdb_test "x" "rotr.b\t@0x12(:8|)" \ + "rotr.b @0x12:8" +gdb_test "x" "rotr.b\t@0x1234(:16|)" \ + "rotr.b @0x1234:16" +gdb_test "x" "rotr.b\t@0x12345678(:32|)" \ + "rotr.b @0x12345678:32" +gdb_test "x" "rotr.w\tr1" \ + "rotr.w r1" +gdb_test "x" "rotr.w\t@er1" \ + "rotr.w @er1" +gdb_test "x" "rotr.w\t@\\(0x6(:2|),er1\\)" \ + "rotr.w @(0x6:2,er1)" +gdb_test "x" "rotr.w\t@-er1" \ + "rotr.w @-er1" +gdb_test "x" "rotr.w\t@er1\\+" \ + "rotr.w @er1+" +gdb_test "x" "rotr.w\t@er1-" \ + "rotr.w @er1-" +gdb_test "x" "rotr.w\t@\\+er1" \ + "rotr.w @+er1" +gdb_test "x" "rotr.w\t@\\(0x1234(:16|),er1\\)" \ + "rotr.w @(0x1234:16,er1)" +gdb_test "x" "rotr.w\t@\\(0x12345678(:32|),er1\\)" \ + "rotr.w @(0x12345678:32,er1)" +gdb_test "x" "rotr.w\t@\\(0x1234(:16|),r2l.b\\)" \ + "rotr.w @(0x1234:16,r2l.b)" +gdb_test "x" "rotr.w\t@\\(0x1234(:16|),r2.w\\)" \ + "rotr.w @(0x1234:16,r2.w)" +gdb_test "x" "rotr.w\t@\\(0x1234(:16|),er2.l\\)" \ + "rotr.w @(0x1234:16,er2.l)" +gdb_test "x" "rotr.w\t@\\(0x12345678(:32|),r2l.b\\)" \ + "rotr.w @(0x12345678:32,r2l.b)" +gdb_test "x" "rotr.w\t@\\(0x12345678(:32|),r2.w\\)" \ + "rotr.w @(0x12345678:32,r2.w)" +gdb_test "x" "rotr.w\t@\\(0x12345678(:32|),er2.l\\)" \ + "rotr.w @(0x12345678:32,er2.l)" +gdb_test "x" "rotr.w\t@0x1234(:16|)" \ + "rotr.w @0x1234:16" +gdb_test "x" "rotr.w\t@0x12345678(:32|)" \ + "rotr.w @0x12345678:32" +gdb_test "x" "rotr.l\ter1" \ + "rotr.l er1" +gdb_test "x" "rotr.l\t@er1" \ + "rotr.l @er1" +gdb_test "x" "rotr.l\t@\\(0xc(:2|),er1\\)" \ + "rotr.l @(0xc:2,er1)" +gdb_test "x" "rotr.l\t@er1\\+" \ + "rotr.l @er1+" +gdb_test "x" "rotr.l\t@-er1" \ + "rotr.l @-er1" +gdb_test "x" "rotr.l\t@\\+er1" \ + "rotr.l @+er1" +gdb_test "x" "rotr.l\t@er1-" \ + "rotr.l @er1-" +gdb_test "x" "rotr.l\t@\\(0x1234(:16|),er1\\)" \ + "rotr.l @(0x1234:16,er1)" +gdb_test "x" "rotr.l\t@\\(0x12345678(:32|),er1\\)" \ + "rotr.l @(0x12345678:32,er1)" +gdb_test "x" "rotr.l\t@\\(0x1234(:16|),r2l.b\\)" \ + "rotr.l @(0x1234:16,r2l.b)" +gdb_test "x" "rotr.l\t@\\(0x1234(:16|),r2.w\\)" \ + "rotr.l @(0x1234:16,r2.w)" +gdb_test "x" "rotr.l\t@\\(0x1234(:16|),er2.l\\)" \ + "rotr.l @(0x1234:16,er2.l)" +gdb_test "x" "rotr.l\t@\\(0x12345678(:32|),r2l.b\\)" \ + "rotr.l @(0x12345678:32,r2l.b)" +gdb_test "x" "rotr.l\t@\\(0x12345678(:32|),r2.w\\)" \ + "rotr.l @(0x12345678:32,r2.w)" +gdb_test "x" "rotr.l\t@\\(0x12345678(:32|),er2.l\\)" \ + "rotr.l @(0x12345678:32,er2.l)" +gdb_test "x" "rotr.l\t@0x1234(:16|)" \ + "rotr.l @0x1234:16" +gdb_test "x" "rotr.l\t@0x12345678(:32|)" \ + "rotr.l @0x12345678:32" +gdb_test "x" "rotr.b\t#2,r1h" \ + "rotr.b #2,r1h" +gdb_test "x" "rotr.b\t#2,@er1" \ + "rotr.b #2,@er1" +gdb_test "x" "rotr.b\t#2,@\\(0x3(:2|),er1\\)" \ + "rotr.b #2,@(0x3:2,er1)" +gdb_test "x" "rotr.b\t#2,@er1\\+" \ + "rotr.b #2,@er1+" +gdb_test "x" "rotr.b\t#2,@-er1" \ + "rotr.b #2,@-er1" +gdb_test "x" "rotr.b\t#2,@\\+er1" \ + "rotr.b #2,@+er1" +gdb_test "x" "rotr.b\t#2,@er1-" \ + "rotr.b #2,@er1-" +gdb_test "x" "rotr.b\t#2,@\\(0x1234(:16|),er1\\)" \ + "rotr.b #2,@(0x1234:16,er1)" +gdb_test "x" "rotr.b\t#2,@\\(0x12345678(:32|),er1\\)" \ + "rotr.b #2,@(0x12345678:32,er1)" +gdb_test "x" "rotr.b\t#2,@\\(0x1234(:16|),r2l.b\\)" \ + "rotr.b #2,@(0x1234:16,r2l.b)" +gdb_test "x" "rotr.b\t#2,@\\(0x1234(:16|),r2.w\\)" \ + "rotr.b #2,@(0x1234:16,r2.w)" +gdb_test "x" "rotr.b\t#2,@\\(0x1234(:16|),er2.l\\)" \ + "rotr.b #2,@(0x1234:16,er2.l)" +gdb_test "x" "rotr.b\t#2,@\\(0x12345678(:32|),r2l.b\\)" \ + "rotr.b #2,@(0x12345678:32,r2l.b)" +gdb_test "x" "rotr.b\t#2,@\\(0x12345678(:32|),r2.w\\)" \ + "rotr.b #2,@(0x12345678:32,r2.w)" +gdb_test "x" "rotr.b\t#2,@\\(0x12345678(:32|),er2.l\\)" \ + "rotr.b #2,@(0x12345678:32,er2.l)" +gdb_test "x" "rotr.b\t#2,@0x12(:8|)" \ + "rotr.b #2,@0x12:8" +gdb_test "x" "rotr.b\t#2,@0x1234(:16|)" \ + "rotr.b #2,@0x1234:16" +gdb_test "x" "rotr.b\t#2,@0x12345678(:32|)" \ + "rotr.b #2,@0x12345678:32" +gdb_test "x" "rotr.w\t#2,r1" \ + "rotr.w #2,r1" +gdb_test "x" "rotr.w\t#2,@er1" \ + "rotr.w #2,@er1" +gdb_test "x" "rotr.w\t#2,@\\(0x6(:2|),er1\\)" \ + "rotr.w #2,@(0x6:2,er1)" +gdb_test "x" "rotr.w\t#2,@er1\\+" \ + "rotr.w #2,@er1+" +gdb_test "x" "rotr.w\t#2,@-er1" \ + "rotr.w #2,@-er1" +gdb_test "x" "rotr.w\t#2,@\\+er1" \ + "rotr.w #2,@+er1" +gdb_test "x" "rotr.w\t#2,@er1-" \ + "rotr.w #2,@er1-" +gdb_test "x" "rotr.w\t#2,@\\(0x1234(:16|),er1\\)" \ + "rotr.w #2,@(0x1234:16,er1)" +gdb_test "x" "rotr.w\t#2,@\\(0x12345678(:32|),er1\\)" \ + "rotr.w #2,@(0x12345678:32,er1)" +gdb_test "x" "rotr.w\t#2,@\\(0x1234(:16|),r2l.b\\)" \ + "rotr.w #2,@(0x1234:16,r2l.b)" +gdb_test "x" "rotr.w\t#2,@\\(0x1234(:16|),r2.w\\)" \ + "rotr.w #2,@(0x1234:16,r2.w)" +gdb_test "x" "rotr.w\t#2,@\\(0x1234(:16|),er2.l\\)" \ + "rotr.w #2,@(0x1234:16,er2.l)" +gdb_test "x" "rotr.w\t#2,@\\(0x12345678(:32|),r2l.b\\)" \ + "rotr.w #2,@(0x12345678:32,r2l.b)" +gdb_test "x" "rotr.w\t#2,@\\(0x12345678(:32|),r2.w\\)" \ + "rotr.w #2,@(0x12345678:32,r2.w)" +gdb_test "x" "rotr.w\t#2,@\\(0x12345678(:32|),er2.l\\)" \ + "rotr.w #2,@(0x12345678:32,er2.l)" +gdb_test "x" "rotr.w\t#2,@0x1234(:16|)" \ + "rotr.w #2,@0x1234:16" +gdb_test "x" "rotr.w\t#2,@0x12345678(:32|)" \ + "rotr.w #2,@0x12345678:32" +gdb_test "x" "rotr.l\t#2,er1" \ + "rotr.l #2,er1" +gdb_test "x" "rotr.l\t#2,@er1" \ + "rotr.l #2,@er1" +gdb_test "x" "rotr.l\t#2,@\\(0xc(:2|),er1\\)" \ + "rotr.l #2,@(0xc:2,er1)" +gdb_test "x" "rotr.l\t#2,@er1\\+" \ + "rotr.l #2,@er1+" +gdb_test "x" "rotr.l\t#2,@-er1" \ + "rotr.l #2,@-er1" +gdb_test "x" "rotr.l\t#2,@\\+er1" \ + "rotr.l #2,@+er1" +gdb_test "x" "rotr.l\t#2,@er1-" \ + "rotr.l #2,@er1-" +gdb_test "x" "rotr.l\t#2,@\\(0x1234(:16|),er1\\)" \ + "rotr.l #2,@(0x1234:16,er1)" +gdb_test "x" "rotr.l\t#2,@\\(0x12345678(:32|),er1\\)" \ + "rotr.l #2,@(0x12345678:32,er1)" +gdb_test "x" "rotr.l\t#2,@\\(0x1234(:16|),r2l.b\\)" \ + "rotr.l #2,@(0x1234:16,r2l.b)" +gdb_test "x" "rotr.l\t#2,@\\(0x1234(:16|),r2.w\\)" \ + "rotr.l #2,@(0x1234:16,r2.w)" +gdb_test "x" "rotr.l\t#2,@\\(0x1234(:16|),er2.l\\)" \ + "rotr.l #2,@(0x1234:16,er2.l)" +gdb_test "x" "rotr.l\t#2,@\\(0x12345678(:32|),r2l.b\\)" \ + "rotr.l #2,@(0x12345678:32,r2l.b)" +gdb_test "x" "rotr.l\t#2,@\\(0x12345678(:32|),r2.w\\)" \ + "rotr.l #2,@(0x12345678:32,r2.w)" +gdb_test "x" "rotr.l\t#2,@\\(0x12345678(:32|),er2.l\\)" \ + "rotr.l #2,@(0x12345678:32,er2.l)" +gdb_test "x" "rotr.l\t#2,@0x1234(:16|)" \ + "rotr.l #2,@0x1234:16" +gdb_test "x" "rotr.l\t#2,@0x12345678(:32|)" \ + "rotr.l #2,@0x12345678:32" diff --git a/gdb/testsuite/gdb.disasm/t11_logs.s b/gdb/testsuite/gdb.disasm/t11_logs.s new file mode 100644 index 0000000..7782754 --- /dev/null +++ b/gdb/testsuite/gdb.disasm/t11_logs.s @@ -0,0 +1,1177 @@ +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;log_sft +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + .h8300sx + .text + .global _start +_start: + not.b r1h ;1701 + not.b @er1 ;7d101700 + not.b @(0x3:2,er1) ;017768181700 + not.b @er1+ ;01746c181700 + not.b @-er1 ;01776c181700 + not.b @+er1 ;01756c181700 + not.b @er1- ;01766c181700 + not.b @(0x1234:16,er1) ;01746e1812341700 + not.b @(0x12345678:32,er1) ;78146a28123456781700 + not.b @(0x1234:16,r2l.b) ;01756e2812341700 + not.b @(0x1234:16,r2.w) ;01766e2812341700 + not.b @(0x1234:16,er2.l) ;01776e2812341700 + not.b @(0x12345678:32,r2l.b) ;78256a28123456781700 + not.b @(0x12345678:32,r2.w) ;78266a28123456781700 + not.b @(0x12345678:32,er2.l) ;78276a28123456781700 + not.b @0xffffff12:8 ;7f121700 + not.b @0x1234:16 ;6a1812341700 + not.b @0x12345678:32 ;6a38123456781700 + + not.w r1 ;1711 + not.w @er1 ;7d901710 + not.w @(0x6:2,er1) ;015769181710 + not.w @er1+ ;01546d181710 + not.w @-er1 ;01576d181710 + not.w @+er1 ;01556d181710 + not.w @er1- ;01566d181710 + not.w @(0x1234:16,er1) ;01546f1812341710 + not.w @(0x12345678:32,er1) ;78146b28123456781710 + not.w @(0x1234:16,r2l.b) ;01556f2812341710 + not.w @(0x1234:16,r2.w) ;01566f2812341710 + not.w @(0x1234:16,er2.l) ;01576f2812341710 + not.w @(0x12345678:32,r2l.b) ;78256b28123456781710 + not.w @(0x12345678:32,r2.w) ;78266b28123456781710 + not.w @(0x12345678:32,er2.l) ;78276b28123456781710 + not.w @0x1234:16 ;6b1812341710 + not.w @0x12345678:32 ;6b38123456781710 + + not.l er1 ;1731 + not.l @er1 ;010469181730 + not.l @(0xc:2,er1) ;010769181730 + not.l @er1+ ;01046d181730 + not.l @-er1 ;01076d181730 + not.l @+er1 ;01056d181730 + not.l @er1- ;01066d181730 + not.l @(0x1234:16,er1) ;01046f1812341730 + not.l @(0x12345678:32,er1) ;78946b28123456781730 + not.l @(0x1234:16,r2l.b) ;01056f2812341730 + not.l @(0x1234:16,r2.w) ;01066f2812341730 + not.l @(0x1234:16,er2.l) ;01076f2812341730 + not.l @(0x12345678:32,r2l.b) ;78a56b28123456781730 + not.l @(0x12345678:32,r2.w) ;78a66b28123456781730 + not.l @(0x12345678:32,er2.l) ;78a76b28123456781730 + not.l @0x1234:16 ;01046b0812341730 + not.l @0x12345678:32 ;01046b28123456781730 + + shll.b r1h ;1001 + shll.b @er1 ;7d101000 + shll.b @(0x3:2,er1) ;017768181000 + shll.b @er1+ ;01746c181000 + shll.b @-er1 ;01776c181000 + shll.b @+er1 ;01756c181000 + shll.b @er1- ;01766c181000 + shll.b @(0x1234:16,er1) ;01746e1812341000 + shll.b @(0x12345678:32,er1) ;78146a28123456781000 + shll.b @(0x1234:16,r2l.b) ;01756e2812341000 + shll.b @(0x1234:16,r2.w) ;01766e2812341000 + shll.b @(0x1234:16,er2.l) ;01776e2812341000 + shll.b @(0x12345678:32,r2l.b) ;78256a28123456781000 + shll.b @(0x12345678:32,r2.w) ;78266a28123456781000 + shll.b @(0x12345678:32,er2.l) ;78276a28123456781000 + shll.b @0xffffff12:8 ;7f121000 + shll.b @0x1234:16 ;6a1812341000 + shll.b @0x12345678:32 ;6a38123456781000 + + shll.w r1 ;1011 + shll.w @er1 ;7d901010 + shll.w @(0x6:2,er1) ;015769181010 + shll.w @er1+ ;01546d181010 + shll.w @-er1 ;01576d181010 + shll.w @+er1 ;01556d181010 + shll.w @er1- ;01566d181010 + shll.w @(0x1234:16,er1) ;01546f1812341010 + shll.w @(0x12345678:32,er1) ;78146b28123456781010 + shll.w @(0x1234:16,r2l.b) ;01556f2812341010 + shll.w @(0x1234:16,r2.w) ;01566f2812341010 + shll.w @(0x1234:16,er2.l) ;01576f2812341010 + shll.w @(0x12345678:32,r2l.b) ;78256b28123456781010 + shll.w @(0x12345678:32,r2.w) ;78266b28123456781010 + shll.w @(0x12345678:32,er2.l) ;78276b28123456781010 + shll.w @0x1234:16 ;6b1812341010 + shll.w @0x12345678:32 ;6b38123456781010 + + shll.l er1 ;1031 + shll.l @er1 ;010469181030 + shll.l @(0xc:2,er1) ;010769181030 + shll.l @er1+ ;01046d181030 + shll.l @-er1 ;01076d181030 + shll.l @+er1 ;01056d181030 + shll.l @er1- ;01066d181030 + shll.l @(0x1234:16,er1) ;01046f1812341030 + shll.l @(0x12345678:32,er1) ;78946b28123456781030 + shll.l @(0x1234:16,r2l.b) ;01056f2812341030 + shll.l @(0x1234:16,r2.w) ;01066f2812341030 + shll.l @(0x1234:16,er2.l) ;01076f2812341030 + shll.l @(0x12345678:32,r2l.b) ;78a56b28123456781030 + shll.l @(0x12345678:32,r2.w) ;78a66b28123456781030 + shll.l @(0x12345678:32,er2.l) ;78a76b28123456781030 + shll.l @0x1234:16 ;01046b0812341030 + shll.l @0x12345678:32 ;01046b28123456781030 + + shll.b #2,r1h ;1041 + shll.b #2,@er1 ;7d101040 + shll.b #2,@(0x3:2,er1) ;017768181040 + shll.b #2,@er1+ ;01746c181040 + shll.b #2,@-er1 ;01776c181040 + shll.b #2,@+er1 ;01756c181040 + shll.b #2,@er1- ;01766c181040 + shll.b #2,@(0x1234:16,er1) ;01746e1812341040 + shll.b #2,@(0x12345678:32,er1) ;78146a28123456781040 + shll.b #2,@(0x1234:16,r2l.b) ;01756e2812341040 + shll.b #2,@(0x1234:16,r2.w) ;01766e2812341040 + shll.b #2,@(0x1234:16,er2.l) ;01776e2812341040 + shll.b #2,@(0x12345678:32,r2l.b) ;78256a28123456781040 + shll.b #2,@(0x12345678:32,r2.w) ;78266a28123456781040 + shll.b #2,@(0x12345678:32,er2.l) ;78276a28123456781040 + shll.b #2,@0xffffff12:8 ;7f121040 + shll.b #2,@0x1234:16 ;6a1812341040 + shll.b #2,@0x12345678:32 ;6a38123456781040 + + shll.w #2,r1 ;1051 + shll.w #2,@er1 ;7d901050 + shll.w #2,@(0x6:2,er1) ;015769181050 + shll.w #2,@er1+ ;01546d181050 + shll.w #2,@-er1 ;01576d181050 + shll.w #2,@+er1 ;01556d181050 + shll.w #2,@er1- ;01566d181050 + shll.w #2,@(0x1234:16,er1) ;01546f1812341050 + shll.w #2,@(0x12345678:32,er1) ;78146b28123456781050 + shll.w #2,@(0x1234:16,r2l.b) ;01556f2812341050 + shll.w #2,@(0x1234:16,r2.w) ;01566f2812341050 + shll.w #2,@(0x1234:16,er2.l) ;01576f2812341050 + shll.w #2,@(0x12345678:32,r2l.b) ;78256b28123456781050 + shll.w #2,@(0x12345678:32,r2.w) ;78266b28123456781050 + shll.w #2,@(0x12345678:32,er2.l) ;78276b28123456781050 + shll.w #2,@0x1234:16 ;6b1812341050 + shll.w #2,@0x12345678:32 ;6b38123456781050 + + shll.l #2,er1 ;1071 + shll.l #2,@er1 ;010469181070 + shll.l #2,@(0xc:2,er1) ;010769181070 + shll.l #2,@er1+ ;01046d181070 + shll.l #2,@-er1 ;01076d181070 + shll.l #2,@+er1 ;01056d181070 + shll.l #2,@er1- ;01066d181070 + shll.l #2,@(0x1234:16,er1) ;01046f1812341070 + shll.l #2,@(0x12345678:32,er1) ;78946b28123456781070 + shll.l #2,@(0x1234:16,r2l.b) ;01056f2812341070 + shll.l #2,@(0x1234:16,r2.w) ;01066f2812341070 + shll.l #2,@(0x1234:16,er2.l) ;01076f2812341070 + shll.l #2,@(0x12345678:32,r2l.b) ;78a56b28123456781070 + shll.l #2,@(0x12345678:32,r2.w) ;78a66b28123456781070 + shll.l #2,@(0x12345678:32,er2.l) ;78a76b28123456781070 + shll.l #2,@0x1234:16 ;01046b0812341070 + shll.l #2,@0x12345678:32 ;01046b28123456781070 + + shll.b #4,r1h ;10a1 + shll.b #4,@er1 ;7d1010a0 + shll.b #4,@(0x3:2,er1) ;0177681810a0 + shll.b #4,@er1+ ;01746c1810a0 + shll.b #4,@-er1 ;01776c1810a0 + shll.b #4,@+er1 ;01756c1810a0 + shll.b #4,@er1- ;01766c1810a0 + shll.b #4,@(0x1234:16,er1) ;01746e18123410a0 + shll.b #4,@(0x12345678:32,er1) ;78146a281234567810a0 + shll.b #4,@(0x1234:16,r2l.b) ;01756e28123410a0 + shll.b #4,@(0x1234:16,r2.w) ;01766e28123410a0 + shll.b #4,@(0x1234:16,er2.l) ;01776e28123410a0 + shll.b #4,@(0x12345678:32,r2l.b) ;78256a281234567810a0 + shll.b #4,@(0x12345678:32,r2.w) ;78266a281234567810a0 + shll.b #4,@(0x12345678:32,er2.l) ;78276a281234567810a0 + shll.b #4,@0xffffff12:8 ;7f1210a0 + shll.b #4,@0x1234:16 ;6a18123410a0 + shll.b #4,@0x12345678:32 ;6a381234567810a0 + + shll.w #4,r1 ;1021 + shll.w #4,@er1 ;7d901020 + shll.w #4,@(0x6:2,er1) ;015769181020 + shll.w #4,@er1+ ;01546d181020 + shll.w #4,@-er1 ;01576d181020 + shll.w #4,@+er1 ;01556d181020 + shll.w #4,@er1- ;01566d181020 + shll.w #4,@(0x1234:16,er1) ;01546f1812341020 + shll.w #4,@(0x12345678:32,er1) ;78146b28123456781020 + shll.w #4,@(0x1234:16,r2l.b) ;01556f2812341020 + shll.w #4,@(0x1234:16,r2.w) ;01566f2812341020 + shll.w #4,@(0x1234:16,er2.l) ;01576f2812341020 + shll.w #4,@(0x12345678:32,r2l.b) ;78256b28123456781020 + shll.w #4,@(0x12345678:32,r2.w) ;78266b28123456781020 + shll.w #4,@(0x12345678:32,er2.l) ;78276b28123456781020 + shll.w #4,@0x1234:16 ;6b1812341020 + shll.w #4,@0x12345678:32 ;6b38123456781020 + + shll.l #4,er1 ;1039 + shll.l #4,@er1 ;010469181038 + shll.l #4,@(0xc:2,er1) ;010769181038 + shll.l #4,@er1+ ;01046d181038 + shll.l #4,@-er1 ;01076d181038 + shll.l #4,@+er1 ;01056d181038 + shll.l #4,@er1- ;01066d181038 + shll.l #4,@(0x1234:16,er1) ;01046f1812341038 + shll.l #4,@(0x12345678:32,er1) ;78946b28123456781038 + shll.l #4,@(0x1234:16,r2l.b) ;01056f2812341038 + shll.l #4,@(0x1234:16,r2.w) ;01066f2812341038 + shll.l #4,@(0x1234:16,er2.l) ;01076f2812341038 + shll.l #4,@(0x12345678:32,r2l.b) ;78a56b28123456781038 + shll.l #4,@(0x12345678:32,r2.w) ;78a66b28123456781038 + shll.l #4,@(0x12345678:32,er2.l) ;78a76b28123456781038 + shll.l #4,@0x1234:16 ;01046b0812341038 + shll.l #4,@0x12345678:32 ;01046b28123456781038 + + shll.w #8,r1 ;1061 + shll.w #8,@er1 ;7d901060 + shll.w #8,@(0x6:2,er1) ;015769181060 + shll.w #8,@er1+ ;01546d181060 + shll.w #8,@-er1 ;01576d181060 + shll.w #8,@+er1 ;01556d181060 + shll.w #8,@er1- ;01566d181060 + shll.w #8,@(0x1234:16,er1) ;01546f1812341060 + shll.w #8,@(0x12345678:32,er1) ;78146b28123456781060 + shll.w #8,@(0x1234:16,r2l.b) ;01556f2812341060 + shll.w #8,@(0x1234:16,r2.w) ;01566f2812341060 + shll.w #8,@(0x1234:16,er2.l) ;01576f2812341060 + shll.w #8,@(0x12345678:32,r2l.b) ;78256b28123456781060 + shll.w #8,@(0x12345678:32,r2.w) ;78266b28123456781060 + shll.w #8,@(0x12345678:32,er2.l) ;78276b28123456781060 + shll.w #8,@0x1234:16 ;6b1812341060 + shll.w #8,@0x12345678:32 ;6b38123456781060 + + shll.l #8,er1 ;1079 + shll.l #8,@er1 ;010469181078 + shll.l #8,@(0xc:2,er1) ;010769181078 + shll.l #8,@er1+ ;01046d181078 + shll.l #8,@-er1 ;01076d181078 + shll.l #8,@+er1 ;01056d181078 + shll.l #8,@er1- ;01066d181078 + shll.l #8,@(0x1234:16,er1) ;01046f1812341078 + shll.l #8,@(0x12345678:32,er1) ;78946b28123456781078 + shll.l #8,@(0x1234:16,r2l.b) ;01056f2812341078 + shll.l #8,@(0x1234:16,r2.w) ;01066f2812341078 + shll.l #8,@(0x1234:16,er2.l) ;01076f2812341078 + shll.l #8,@(0x12345678:32,r2l.b) ;78a56b28123456781078 + shll.l #8,@(0x12345678:32,r2.w) ;78a66b28123456781078 + shll.l #8,@(0x12345678:32,er2.l) ;78a76b28123456781078 + shll.l #8,@0x1234:16 ;01046b0812341078 + shll.l #8,@0x12345678:32 ;01046b28123456781078 + + shll.l #16,er1 ;10f9 + shll.l #16,@er1 ;0104691810f8 + shll.l #16,@(0xc:2,er1) ;0107691810f8 + shll.l #16,@er1+ ;01046d1810f8 + shll.l #16,@-er1 ;01076d1810f8 + shll.l #16,@+er1 ;01056d1810f8 + shll.l #16,@er1- ;01066d1810f8 + shll.l #16,@(0x1234:16,er1) ;01046f18123410f8 + shll.l #16,@(0x12345678:32,er1) ;78946b281234567810f8 + shll.l #16,@(0x1234:16,r2l.b) ;01056f28123410f8 + shll.l #16,@(0x1234:16,r2.w) ;01066f28123410f8 + shll.l #16,@(0x1234:16,er2.l) ;01076f28123410f8 + shll.l #16,@(0x12345678:32,r2l.b) ;78a56b281234567810f8 + shll.l #16,@(0x12345678:32,r2.w) ;78a66b281234567810f8 + shll.l #16,@(0x12345678:32,er2.l) ;78a76b281234567810f8 + shll.l #16,@0x1234:16 ;01046b08123410f8 + shll.l #16,@0x12345678:32 ;01046b281234567810f8 + + shll.b #0x7:5,r1h ;03871001 + shll.w #0xf:5,r1 ;038f1011 + shll.l #0x1f:5,er1 ;039f1031 + + shll.b r3h,r1h ;78381001 + shll.w r3h,r1 ;78381011 + shll.l r3h,er1 ;78381031 + + shlr.b r1h ;1101 + shlr.b @er1 ;7d101100 + shlr.b @(0x3:2,er1) ;017768181100 + shlr.b @er1+ ;01746c181100 + shlr.b @-er1 ;01776c181100 + shlr.b @+er1 ;01756c181100 + shlr.b @er1- ;01766c181100 + shlr.b @(0x1234:16,er1) ;01746e1812341100 + shlr.b @(0x12345678:32,er1) ;78146a28123456781100 + shlr.b @(0x1234:16,r2l.b) ;01756e2812341100 + shlr.b @(0x1234:16,r2.w) ;01766e2812341100 + shlr.b @(0x1234:16,er2.l) ;01776e2812341100 + shlr.b @(0x12345678:32,r2l.b) ;78256a28123456781100 + shlr.b @(0x12345678:32,r2.w) ;78266a28123456781100 + shlr.b @(0x12345678:32,er2.l) ;78276a28123456781100 + shlr.b @0xffffff12:8 ;7f121100 + shlr.b @0x1234:16 ;6a1812341100 + shlr.b @0x12345678:32 ;6a38123456781100 + + shlr.w r1 ;1111 + shlr.w @er1 ;7d901110 + shlr.w @(0x6:2,er1) ;015769181110 + shlr.w @er1+ ;01546d181110 + shlr.w @-er1 ;01576d181110 + shlr.w @+er1 ;01556d181110 + shlr.w @er1- ;01566d181110 + shlr.w @(0x1234:16,er1) ;01546f1812341110 + shlr.w @(0x12345678:32,er1) ;78146b28123456781110 + shlr.w @(0x1234:16,r2l.b) ;01556f2812341110 + shlr.w @(0x1234:16,r2.w) ;01566f2812341110 + shlr.w @(0x1234:16,er2.l) ;01576f2812341110 + shlr.w @(0x12345678:32,r2l.b) ;78256b28123456781110 + shlr.w @(0x12345678:32,r2.w) ;78266b28123456781110 + shlr.w @(0x12345678:32,er2.l) ;78276b28123456781110 + shlr.w @0x1234:16 ;6b1812341110 + shlr.w @0x12345678:32 ;6b38123456781110 + + shlr.l er1 ;1131 + shlr.l @er1 ;010469181130 + shlr.l @(0xc:2,er1) ;010769181130 + shlr.l @er1+ ;01046d181130 + shlr.l @-er1 ;01076d181130 + shlr.l @+er1 ;01056d181130 + shlr.l @er1- ;01066d181130 + shlr.l @(0x1234:16,er1) ;01046f1812341130 + shlr.l @(0x12345678:32,er1) ;78946b28123456781130 + shlr.l @(0x1234:16,r2l.b) ;01056f2812341130 + shlr.l @(0x1234:16,r2.w) ;01066f2812341130 + shlr.l @(0x1234:16,er2.l) ;01076f2812341130 + shlr.l @(0x12345678:32,r2l.b) ;78a56b28123456781130 + shlr.l @(0x12345678:32,r2.w) ;78a66b28123456781130 + shlr.l @(0x12345678:32,er2.l) ;78a76b28123456781130 + shlr.l @0x1234:16 ;01046b0812341130 + shlr.l @0x12345678:32 ;01046b28123456781130 + + shlr.b #2,r1h ;1141 + shlr.b #2,@er1 ;7d101140 + shlr.b #2,@(0x3:2,er1) ;017768181140 + shlr.b #2,@er1+ ;01746c181140 + shlr.b #2,@-er1 ;01776c181140 + shlr.b #2,@+er1 ;01756c181140 + shlr.b #2,@er1- ;01766c181140 + shlr.b #2,@(0x1234:16,er1) ;01746e1812341140 + shlr.b #2,@(0x12345678:32,er1) ;78146a28123456781140 + shlr.b #2,@(0x1234:16,r2l.b) ;01756e2812341140 + shlr.b #2,@(0x1234:16,r2.w) ;01766e2812341140 + shlr.b #2,@(0x1234:16,er2.l) ;01776e2812341140 + shlr.b #2,@(0x12345678:32,r2l.b) ;78256a28123456781140 + shlr.b #2,@(0x12345678:32,r2.w) ;78266a28123456781140 + shlr.b #2,@(0x12345678:32,er2.l) ;78276a28123456781140 + shlr.b #2,@0xffffff12:8 ;7f121140 + shlr.b #2,@0x1234:16 ;6a1812341140 + shlr.b #2,@0x12345678:32 ;6a38123456781140 + + shlr.w #2,r1 ;1151 + shlr.w #2,@er1 ;7d901150 + shlr.w #2,@(0x6:2,er1) ;015769181150 + shlr.w #2,@er1+ ;01546d181150 + shlr.w #2,@-er1 ;01576d181150 + shlr.w #2,@+er1 ;01556d181150 + shlr.w #2,@er1- ;01566d181150 + shlr.w #2,@(0x1234:16,er1) ;01546f1812341150 + shlr.w #2,@(0x12345678:32,er1) ;78146b28123456781150 + shlr.w #2,@(0x1234:16,r2l.b) ;01556f2812341150 + shlr.w #2,@(0x1234:16,r2.w) ;01566f2812341150 + shlr.w #2,@(0x1234:16,er2.l) ;01576f2812341150 + shlr.w #2,@(0x12345678:32,r2l.b) ;78256b28123456781150 + shlr.w #2,@(0x12345678:32,r2.w) ;78266b28123456781150 + shlr.w #2,@(0x12345678:32,er2.l) ;78276b28123456781150 + shlr.w #2,@0x1234:16 ;6b1812341150 + shlr.w #2,@0x12345678:32 ;6b38123456781150 + + shlr.l #2,er1 ;1171 + shlr.l #2,@er1 ;010469181170 + shlr.l #2,@(0xc:2,er1) ;010769181170 + shlr.l #2,@er1+ ;01046d181170 + shlr.l #2,@-er1 ;01076d181170 + shlr.l #2,@+er1 ;01056d181170 + shlr.l #2,@er1- ;01066d181170 + shlr.l #2,@(0x1234:16,er1) ;01046f1812341170 + shlr.l #2,@(0x12345678:32,er1) ;78946b28123456781170 + shlr.l #2,@(0x1234:16,r2l.b) ;01056f2812341170 + shlr.l #2,@(0x1234:16,r2.w) ;01066f2812341170 + shlr.l #2,@(0x1234:16,er2.l) ;01076f2812341170 + shlr.l #2,@(0x12345678:32,r2l.b) ;78a56b28123456781170 + shlr.l #2,@(0x12345678:32,r2.w) ;78a66b28123456781170 + shlr.l #2,@(0x12345678:32,er2.l) ;78a76b28123456781170 + shlr.l #2,@0x1234:16 ;01046b0812341170 + shlr.l #2,@0x12345678:32 ;01046b28123456781170 + + shlr.b #4,r1h ;11a1 + shlr.b #4,@er1 ;7d1011a0 + shlr.b #4,@(0x3:2,er1) ;0177681811a0 + shlr.b #4,@er1+ ;01746c1811a0 + shlr.b #4,@-er1 ;01776c1811a0 + shlr.b #4,@+er1 ;01756c1811a0 + shlr.b #4,@er1- ;01766c1811a0 + shlr.b #4,@(0x1234:16,er1) ;01746e18123411a0 + shlr.b #4,@(0x12345678:32,er1) ;78146a281234567811a0 + shlr.b #4,@(0x1234:16,r2l.b) ;01756e28123411a0 + shlr.b #4,@(0x1234:16,r2.w) ;01766e28123411a0 + shlr.b #4,@(0x1234:16,er2.l) ;01776e28123411a0 + shlr.b #4,@(0x12345678:32,r2l.b) ;78256a281234567811a0 + shlr.b #4,@(0x12345678:32,r2.w) ;78266a281234567811a0 + shlr.b #4,@(0x12345678:32,er2.l) ;78276a281234567811a0 + shlr.b #4,@0xffffff12:8 ;7f1211a0 + shlr.b #4,@0x1234:16 ;6a18123411a0 + shlr.b #4,@0x12345678:32 ;6a381234567811a0 + + shlr.w #4,r1 ;1121 + shlr.w #4,@er1 ;7d901120 + shlr.w #4,@(0x6:2,er1) ;015769181120 + shlr.w #4,@er1+ ;01546d181120 + shlr.w #4,@-er1 ;01576d181120 + shlr.w #4,@+er1 ;01556d181120 + shlr.w #4,@er1- ;01566d181120 + shlr.w #4,@(0x1234:16,er1) ;01546f1812341120 + shlr.w #4,@(0x12345678:32,er1) ;78146b28123456781120 + shlr.w #4,@(0x1234:16,r2l.b) ;01556f2812341120 + shlr.w #4,@(0x1234:16,r2.w) ;01566f2812341120 + shlr.w #4,@(0x1234:16,er2.l) ;01576f2812341120 + shlr.w #4,@(0x12345678:32,r2l.b) ;78256b28123456781120 + shlr.w #4,@(0x12345678:32,r2.w) ;78266b28123456781120 + shlr.w #4,@(0x12345678:32,er2.l) ;78276b28123456781120 + shlr.w #4,@0x1234:16 ;6b1812341120 + shlr.w #4,@0x12345678:32 ;6b38123456781120 + + shlr.l #4,er1 ;1139 + shlr.l #4,@er1 ;010469181138 + shlr.l #4,@(0xc:2,er1) ;010769181138 + shlr.l #4,@er1+ ;01046d181138 + shlr.l #4,@-er1 ;01076d181138 + shlr.l #4,@+er1 ;01056d181138 + shlr.l #4,@er1- ;01066d181138 + shlr.l #4,@(0x1234:16,er1) ;01046f1812341138 + shlr.l #4,@(0x12345678:32,er1) ;78946b28123456781138 + shlr.l #4,@(0x1234:16,r2l.b) ;01056f2812341138 + shlr.l #4,@(0x1234:16,r2.w) ;01066f2812341138 + shlr.l #4,@(0x1234:16,er2.l) ;01076f2812341138 + shlr.l #4,@(0x12345678:32,r2l.b) ;78a56b28123456781138 + shlr.l #4,@(0x12345678:32,r2.w) ;78a66b28123456781138 + shlr.l #4,@(0x12345678:32,er2.l) ;78a76b28123456781138 + shlr.l #4,@0x1234:16 ;01046b0812341138 + shlr.l #4,@0x12345678:32 ;01046b28123456781138 + + shlr.w #8,r1 ;1161 + shlr.w #8,@er1 ;7d901160 + shlr.w #8,@(0x6:2,er1) ;015769181160 + shlr.w #8,@er1+ ;01546d181160 + shlr.w #8,@-er1 ;01576d181160 + shlr.w #8,@+er1 ;01556d181160 + shlr.w #8,@er1- ;01566d181160 + shlr.w #8,@(0x1234:16,er1) ;01546f1812341160 + shlr.w #8,@(0x12345678:32,er1) ;78146b28123456781160 + shlr.w #8,@(0x1234:16,r2l.b) ;01556f2812341160 + shlr.w #8,@(0x1234:16,r2.w) ;01566f2812341160 + shlr.w #8,@(0x1234:16,er2.l) ;01576f2812341160 + shlr.w #8,@(0x12345678:32,r2l.b) ;78256b28123456781160 + shlr.w #8,@(0x12345678:32,r2.w) ;78266b28123456781160 + shlr.w #8,@(0x12345678:32,er2.l) ;78276b28123456781160 + shlr.w #8,@0x1234:16 ;6b1812341160 + shlr.w #8,@0x12345678:32 ;6b38123456781160 + + shlr.l #8,er1 ;1179 + shlr.l #8,@er1 ;010469181178 + shlr.l #8,@(0xc:2,er1) ;010769181178 + shlr.l #8,@er1+ ;01046d181178 + shlr.l #8,@-er1 ;01076d181178 + shlr.l #8,@+er1 ;01056d181178 + shlr.l #8,@er1- ;01066d181178 + shlr.l #8,@(0x1234:16,er1) ;01046f1812341178 + shlr.l #8,@(0x12345678:32,er1) ;78946b28123456781178 + shlr.l #8,@(0x1234:16,r2l.b) ;01056f2812341178 + shlr.l #8,@(0x1234:16,r2.w) ;01066f2812341178 + shlr.l #8,@(0x1234:16,er2.l) ;01076f2812341178 + shlr.l #8,@(0x12345678:32,r2l.b) ;78a56b28123456781178 + shlr.l #8,@(0x12345678:32,r2.w) ;78a66b28123456781178 + shlr.l #8,@(0x12345678:32,er2.l) ;78a76b28123456781178 + shlr.l #8,@0x1234:16 ;01046b0812341178 + shlr.l #8,@0x12345678:32 ;01046b28123456781178 + + shlr.l #16,er1 ;11f9 + shlr.l #16,@er1 ;0104691811f8 + shlr.l #16,@(0xc:2,er1) ;0107691811f8 + shlr.l #16,@er1+ ;01046d1811f8 + shlr.l #16,@-er1 ;01076d1811f8 + shlr.l #16,@+er1 ;01056d1811f8 + shlr.l #16,@er1- ;01066d1811f8 + shlr.l #16,@(0x1234:16,er1) ;01046f18123411f8 + shlr.l #16,@(0x12345678:32,er1) ;78946b281234567811f8 + shlr.l #16,@(0x1234:16,r2l.b) ;01056f28123411f8 + shlr.l #16,@(0x1234:16,r2.w) ;01066f28123411f8 + shlr.l #16,@(0x1234:16,er2.l) ;01076f28123411f8 + shlr.l #16,@(0x12345678:32,r2l.b) ;78a56b281234567811f8 + shlr.l #16,@(0x12345678:32,r2.w) ;78a66b281234567811f8 + shlr.l #16,@(0x12345678:32,er2.l) ;78a76b281234567811f8 + shlr.l #16,@0x1234:16 ;01046b08123411f8 + shlr.l #16,@0x12345678:32 ;01046b281234567811f8 + + shlr.b #0x7:5,r1h ;03871101 + shlr.w #0xf:5,r1 ;038f1111 + shlr.l #0x1f:5,er1 ;039f1131 + + shlr.b r3h,r1h ;78381101 + shlr.w r3h,r1 ;78381111 + shlr.l r3h,er1 ;78381131 + + shal.b r1h ;1081 + shal.b @er1 ;7d101080 + shal.b @(0x3:2,er1) ;017768181080 + shal.b @er1+ ;01746c181080 + shal.b @-er1 ;01776c181080 + shal.b @+er1 ;01756c181080 + shal.b @er1- ;01766c181080 + shal.b @(0x1234:16,er1) ;01746e1812341080 + shal.b @(0x12345678:32,er1) ;78146a28123456781080 + shal.b @(0x1234:16,r2l.b) ;01756e2812341080 + shal.b @(0x1234:16,r2.w) ;01766e2812341080 + shal.b @(0x1234:16,er2.l) ;01776e2812341080 + shal.b @(0x12345678:32,r2l.b) ;78256a28123456781080 + shal.b @(0x12345678:32,r2.w) ;78266a28123456781080 + shal.b @(0x12345678:32,er2.l) ;78276a28123456781080 + shal.b @0xffffff12:8 ;7f121080 + shal.b @0x1234:16 ;6a1812341080 + shal.b @0x12345678:32 ;6a38123456781080 + + shal.w r1 ;1091 + shal.w @er1 ;7d901090 + shal.w @(0x6:2,er1) ;015769181090 + shal.w @er1+ ;01546d181090 + shal.w @-er1 ;01576d181090 + shal.w @+er1 ;01556d181090 + shal.w @er1- ;01566d181090 + shal.w @(0x1234:16,er1) ;01546f1812341090 + shal.w @(0x12345678:32,er1) ;78146b28123456781090 + shal.w @(0x1234:16,r2l.b) ;01556f2812341090 + shal.w @(0x1234:16,r2.w) ;01566f2812341090 + shal.w @(0x1234:16,er2.l) ;01576f2812341090 + shal.w @(0x12345678:32,r2l.b) ;78256b28123456781090 + shal.w @(0x12345678:32,r2.w) ;78266b28123456781090 + shal.w @(0x12345678:32,er2.l) ;78276b28123456781090 + shal.w @0x1234:16 ;6b1812341090 + shal.w @0x12345678:32 ;6b38123456781090 + + shal.l er1 ;10b1 + shal.l @er1 ;0104691810b0 + shal.l @(0xc:2,er1) ;0107691810b0 + shal.l @er1+ ;01046d1810b0 + shal.l @-er1 ;01076d1810b0 + shal.l @+er1 ;01056d1810b0 + shal.l @er1- ;01066d1810b0 + shal.l @(0x1234:16,er1) ;01046f18123410b0 + shal.l @(0x12345678:32,er1) ;78946b281234567810b0 + shal.l @(0x1234:16,r2l.b) ;01056f28123410b0 + shal.l @(0x1234:16,r2.w) ;01066f28123410b0 + shal.l @(0x1234:16,er2.l) ;01076f28123410b0 + shal.l @(0x12345678:32,r2l.b) ;78a56b281234567810b0 + shal.l @(0x12345678:32,r2.w) ;78a66b281234567810b0 + shal.l @(0x12345678:32,er2.l) ;78a76b281234567810b0 + shal.l @0x1234:16 ;01046b08123410b0 + shal.l @0x12345678:32 ;01046b281234567810b0 + + shal.b #2,r1h ;10c1 + shal.b #2,@er1 ;7d1010c0 + shal.b #2,@(0x3:2,er1) ;0177681810c0 + shal.b #2,@er1+ ;01746c1810c0 + shal.b #2,@-er1 ;01776c1810c0 + shal.b #2,@+er1 ;01756c1810c0 + shal.b #2,@er1- ;01766c1810c0 + shal.b #2,@(0x1234:16,er1) ;01746e18123410c0 + shal.b #2,@(0x12345678:32,er1) ;78146a281234567810c0 + shal.b #2,@(0x1234:16,r2l.b) ;01756e28123410c0 + shal.b #2,@(0x1234:16,r2.w) ;01766e28123410c0 + shal.b #2,@(0x1234:16,er2.l) ;01776e28123410c0 + shal.b #2,@(0x12345678:32,r2l.b) ;78256a281234567810c0 + shal.b #2,@(0x12345678:32,r2.w) ;78266a281234567810c0 + shal.b #2,@(0x12345678:32,er2.l) ;78276a281234567810c0 + shal.b #2,@0xffffff12:8 ;7f1210c0 + shal.b #2,@0x1234:16 ;6a18123410c0 + shal.b #2,@0x12345678:32 ;6a381234567810c0 + + shal.w #2,r1 ;10d1 + shal.w #2,@er1 ;7d9010d0 + shal.w #2,@(0x6:2,er1) ;0157691810d0 + shal.w #2,@er1+ ;01546d1810d0 + shal.w #2,@-er1 ;01576d1810d0 + shal.w #2,@+er1 ;01556d1810d0 + shal.w #2,@er1- ;01566d1810d0 + shal.w #2,@(0x1234:16,er1) ;01546f18123410d0 + shal.w #2,@(0x12345678:32,er1) ;78146b281234567810d0 + shal.w #2,@(0x1234:16,r2l.b) ;01556f28123410d0 + shal.w #2,@(0x1234:16,r2.w) ;01566f28123410d0 + shal.w #2,@(0x1234:16,er2.l) ;01576f28123410d0 + shal.w #2,@(0x12345678:32,r2l.b) ;78256b281234567810d0 + shal.w #2,@(0x12345678:32,r2.w) ;78266b281234567810d0 + shal.w #2,@(0x12345678:32,er2.l) ;78276b281234567810d0 + shal.w #2,@0x1234:16 ;6b18123410d0 + shal.w #2,@0x12345678:32 ;6b381234567810d0 + + shal.l #2,er1 ;10f1 + shal.l #2,@er1 ;0104691810f0 + shal.l #2,@(0xc:2,er1) ;0107691810f0 + shal.l #2,@er1+ ;01046d1810f0 + shal.l #2,@-er1 ;01076d1810f0 + shal.l #2,@+er1 ;01056d1810f0 + shal.l #2,@er1- ;01066d1810f0 + shal.l #2,@(0x1234:16,er1) ;01046f18123410f0 + shal.l #2,@(0x12345678:32,er1) ;78946b281234567810f0 + shal.l #2,@(0x1234:16,r2l.b) ;01056f28123410f0 + shal.l #2,@(0x1234:16,r2.w) ;01066f28123410f0 + shal.l #2,@(0x1234:16,er2.l) ;01076f28123410f0 + shal.l #2,@(0x12345678:32,r2l.b) ;78a56b281234567810f0 + shal.l #2,@(0x12345678:32,r2.w) ;78a66b281234567810f0 + shal.l #2,@(0x12345678:32,er2.l) ;78a76b281234567810f0 + shal.l #2,@0x1234:16 ;01046b08123410f0 + shal.l #2,@0x12345678:32 ;01046b281234567810f0 + + shar.b r1h ;1181 + shar.b @er1 ;7d101180 + shar.b @(0x3:2,er1) ;017768181180 + shar.b @er1+ ;01746c181180 + shar.b @-er1 ;01776c181180 + shar.b @+er1 ;01756c181180 + shar.b @er1- ;01766c181180 + shar.b @(0x1234:16,er1) ;01746e1812341180 + shar.b @(0x12345678:32,er1) ;78146a28123456781180 + shar.b @(0x1234:16,r2l.b) ;01756e2812341180 + shar.b @(0x1234:16,r2.w) ;01766e2812341180 + shar.b @(0x1234:16,er2.l) ;01776e2812341180 + shar.b @(0x12345678:32,r2l.b) ;78256a28123456781180 + shar.b @(0x12345678:32,r2.w) ;78266a28123456781180 + shar.b @(0x12345678:32,er2.l) ;78276a28123456781180 + shar.b @0xffffff12:8 ;7f121180 + shar.b @0x1234:16 ;6a1812341180 + shar.b @0x12345678:32 ;6a38123456781180 + + shar.w r1 ;1191 + shar.w @er1 ;7d901190 + shar.w @(0x6:2,er1) ;015769181190 + shar.w @er1+ ;01546d181190 + shar.w @-er1 ;01576d181190 + shar.w @+er1 ;01556d181190 + shar.w @er1- ;01566d181190 + shar.w @(0x1234:16,er1) ;01546f1812341190 + shar.w @(0x12345678:32,er1) ;78146b28123456781190 + shar.w @(0x1234:16,r2l.b) ;01556f2812341190 + shar.w @(0x1234:16,r2.w) ;01566f2812341190 + shar.w @(0x1234:16,er2.l) ;01576f2812341190 + shar.w @(0x12345678:32,r2l.b) ;78256b28123456781190 + shar.w @(0x12345678:32,r2.w) ;78266b28123456781190 + shar.w @(0x12345678:32,er2.l) ;78276b28123456781190 + shar.w @0x1234:16 ;6b1812341190 + shar.w @0x12345678:32 ;6b38123456781190 + + shar.l er1 ;11b1 + shar.l @er1 ;0104691811b0 + shar.l @(0xc:2,er1) ;0107691811b0 + shar.l @er1+ ;01046d1811b0 + shar.l @-er1 ;01076d1811b0 + shar.l @+er1 ;01056d1811b0 + shar.l @er1- ;01066d1811b0 + shar.l @(0x1234:16,er1) ;01046f18123411b0 + shar.l @(0x12345678:32,er1) ;78946b281234567811b0 + shar.l @(0x1234:16,r2l.b) ;01056f28123411b0 + shar.l @(0x1234:16,r2.w) ;01066f28123411b0 + shar.l @(0x1234:16,er2.l) ;01076f28123411b0 + shar.l @(0x12345678:32,r2l.b) ;78a56b281234567811b0 + shar.l @(0x12345678:32,r2.w) ;78a66b281234567811b0 + shar.l @(0x12345678:32,er2.l) ;78a76b281234567811b0 + shar.l @0x1234:16 ;01046b08123411b0 + shar.l @0x12345678:32 ;01046b281234567811b0 + + shar.b #2,r1h ;11c1 + shar.b #2,@er1 ;7d1011c0 + shar.b #2,@(0x3:2,er1) ;0177681811c0 + shar.b #2,@er1+ ;01746c1811c0 + shar.b #2,@-er1 ;01776c1811c0 + shar.b #2,@+er1 ;01756c1811c0 + shar.b #2,@er1- ;01766c1811c0 + shar.b #2,@(0x1234:16,er1) ;01746e18123411c0 + shar.b #2,@(0x12345678:32,er1) ;78146a281234567811c0 + shar.b #2,@(0x1234:16,r2l.b) ;01756e28123411c0 + shar.b #2,@(0x1234:16,r2.w) ;01766e28123411c0 + shar.b #2,@(0x1234:16,er2.l) ;01776e28123411c0 + shar.b #2,@(0x12345678:32,r2l.b) ;78256a281234567811c0 + shar.b #2,@(0x12345678:32,r2.w) ;78266a281234567811c0 + shar.b #2,@(0x12345678:32,er2.l) ;78276a281234567811c0 + shar.b #2,@0xffffff12:8 ;7f1211c0 + shar.b #2,@0x1234:16 ;6a18123411c0 + shar.b #2,@0x12345678:32 ;6a381234567811c0 + + shar.w #2,r1 ;11d1 + shar.w #2,@er1 ;7d9011d0 + shar.w #2,@(0x6:2,er1) ;0157691811d0 + shar.w #2,@er1+ ;01546d1811d0 + shar.w #2,@-er1 ;01576d1811d0 + shar.w #2,@+er1 ;01556d1811d0 + shar.w #2,@er1- ;01566d1811d0 + shar.w #2,@(0x1234:16,er1) ;01546f18123411d0 + shar.w #2,@(0x12345678:32,er1) ;78146b281234567811d0 + shar.w #2,@(0x1234:16,r2l.b) ;01556f28123411d0 + shar.w #2,@(0x1234:16,r2.w) ;01566f28123411d0 + shar.w #2,@(0x1234:16,er2.l) ;01576f28123411d0 + shar.w #2,@(0x12345678:32,r2l.b) ;78256b281234567811d0 + shar.w #2,@(0x12345678:32,r2.w) ;78266b281234567811d0 + shar.w #2,@(0x12345678:32,er2.l) ;78276b281234567811d0 + shar.w #2,@0x1234:16 ;6b18123411d0 + shar.w #2,@0x12345678:32 ;6b381234567811d0 + + shar.l #2,er1 ;11f1 + shar.l #2,@er1 ;0104691811f0 + shar.l #2,@(0xc:2,er1) ;0107691811f0 + shar.l #2,@er1+ ;01046d1811f0 + shar.l #2,@-er1 ;01076d1811f0 + shar.l #2,@+er1 ;01056d1811f0 + shar.l #2,@er1- ;01066d1811f0 + shar.l #2,@(0x1234:16,er1) ;01046f18123411f0 + shar.l #2,@(0x12345678:32,er1) ;78946b281234567811f0 + shar.l #2,@(0x1234:16,r2l.b) ;01056f28123411f0 + shar.l #2,@(0x1234:16,r2.w) ;01066f28123411f0 + shar.l #2,@(0x1234:16,er2.l) ;01076f28123411f0 + shar.l #2,@(0x12345678:32,r2l.b) ;78a56b281234567811f0 + shar.l #2,@(0x12345678:32,r2.w) ;78a66b281234567811f0 + shar.l #2,@(0x12345678:32,er2.l) ;78a76b281234567811f0 + shar.l #2,@0x1234:16 ;01046b08123411f0 + shar.l #2,@0x12345678:32 ;01046b281234567811f0 + + rotxl.b r1h ;1201 + rotxl.b @er1 ;7d101200 + rotxl.b @(0x3:2,er1) ;017768181200 + rotxl.b @er1+ ;01746c181200 + rotxl.b @-er1 ;01776c181200 + rotxl.b @+er1 ;01756c181200 + rotxl.b @er1- ;01766c181200 + rotxl.b @(0x1234:16,er1) ;01746e1812341200 + rotxl.b @(0x12345678:32,er1) ;78146a28123456781200 + rotxl.b @(0x1234:16,r2l.b) ;01756e2812341200 + rotxl.b @(0x1234:16,r2.w) ;01766e2812341200 + rotxl.b @(0x1234:16,er2.l) ;01776e2812341200 + rotxl.b @(0x12345678:32,r2l.b) ;78256a28123456781200 + rotxl.b @(0x12345678:32,r2.w) ;78266a28123456781200 + rotxl.b @(0x12345678:32,er2.l) ;78276a28123456781200 + rotxl.b @0xffffff12:8 ;7f121200 + rotxl.b @0x1234:16 ;6a1812341200 + rotxl.b @0x12345678:32 ;6a38123456781200 + + rotxl.w r1 ;1211 + rotxl.w @er1 ;7d901210 + rotxl.w @(0x6:2,er1) ;015769181210 + rotxl.w @er1+ ;01546d181210 + rotxl.w @-er1 ;01576d181210 + rotxl.w @+er1 ;01556d181210 + rotxl.w @er1- ;01566d181210 + rotxl.w @(0x1234:16,er1) ;01546f1812341210 + rotxl.w @(0x12345678:32,er1) ;78146b28123456781210 + rotxl.w @(0x1234:16,r2l.b) ;01556f2812341210 + rotxl.w @(0x1234:16,r2.w) ;01566f2812341210 + rotxl.w @(0x1234:16,er2.l) ;01576f2812341210 + rotxl.w @(0x12345678:32,r2l.b) ;78256b28123456781210 + rotxl.w @(0x12345678:32,r2.w) ;78266b28123456781210 + rotxl.w @(0x12345678:32,er2.l) ;78276b28123456781210 + rotxl.w @0x1234:16 ;6b1812341210 + rotxl.w @0x12345678:32 ;6b38123456781210 + + rotxl.l er1 ;1231 + rotxl.l @er1 ;010469181230 + rotxl.l @(0xc:2,er1) ;010769181230 + rotxl.l @er1+ ;01046d181230 + rotxl.l @-er1 ;01076d181230 + rotxl.l @+er1 ;01056d181230 + rotxl.l @er1- ;01066d181230 + rotxl.l @(0x1234:16,er1) ;01046f1812341230 + rotxl.l @(0x12345678:32,er1) ;78946b28123456781230 + rotxl.l @(0x1234:16,r2l.b) ;01056f2812341230 + rotxl.l @(0x1234:16,r2.w) ;01066f2812341230 + rotxl.l @(0x1234:16,er2.l) ;01076f2812341230 + rotxl.l @(0x12345678:32,r2l.b) ;78a56b28123456781230 + rotxl.l @(0x12345678:32,r2.w) ;78a66b28123456781230 + rotxl.l @(0x12345678:32,er2.l) ;78a76b28123456781230 + rotxl.l @0x1234:16 ;01046b0812341230 + rotxl.l @0x12345678:32 ;01046b28123456781230 + + rotxl.b #2,r1h ;1241 + rotxl.b #2,@er1 ;7d101240 + rotxl.b #2,@(0x3:2,er1) ;017768181240 + rotxl.b #2,@er1+ ;01746c181240 + rotxl.b #2,@-er1 ;01776c181240 + rotxl.b #2,@+er1 ;01756c181240 + rotxl.b #2,@er1- ;01766c181240 + rotxl.b #2,@(0x1234:16,er1) ;01746e1812341240 + rotxl.b #2,@(0x12345678:32,er1) ;78146a28123456781240 + rotxl.b #2,@(0x1234:16,r2l.b) ;01756e2812341240 + rotxl.b #2,@(0x1234:16,r2.w) ;01766e2812341240 + rotxl.b #2,@(0x1234:16,er2.l) ;01776e2812341240 + rotxl.b #2,@(0x12345678:32,r2l.b) ;78256a28123456781240 + rotxl.b #2,@(0x12345678:32,r2.w) ;78266a28123456781240 + rotxl.b #2,@(0x12345678:32,er2.l) ;78276a28123456781240 + rotxl.b #2,@0xffffff12:8 ;7f121240 + rotxl.b #2,@0x1234:16 ;6a1812341240 + rotxl.b #2,@0x12345678:32 ;6a38123456781240 + + rotxl.w #2,r1 ;1251 + rotxl.w #2,@er1 ;7d901250 + rotxl.w #2,@(0x6:2,er1) ;015769181250 + rotxl.w #2,@er1+ ;01546d181250 + rotxl.w #2,@-er1 ;01576d181250 + rotxl.w #2,@+er1 ;01556d181250 + rotxl.w #2,@er1- ;01566d181250 + rotxl.w #2,@(0x1234:16,er1) ;01546f1812341250 + rotxl.w #2,@(0x12345678:32,er1) ;78146b28123456781250 + rotxl.w #2,@(0x1234:16,r2l.b) ;01556f2812341250 + rotxl.w #2,@(0x1234:16,r2.w) ;01566f2812341250 + rotxl.w #2,@(0x1234:16,er2.l) ;01576f2812341250 + rotxl.w #2,@(0x12345678:32,r2l.b) ;78256b28123456781250 + rotxl.w #2,@(0x12345678:32,r2.w) ;78266b28123456781250 + rotxl.w #2,@(0x12345678:32,er2.l) ;78276b28123456781250 + rotxl.w #2,@0x1234:16 ;6b1812341250 + rotxl.w #2,@0x12345678:32 ;6b38123456781250 + + rotxl.l #2,er1 ;1271 + rotxl.l #2,@er1 ;010469181270 + rotxl.l #2,@(0xc:2,er1) ;010769181270 + rotxl.l #2,@er1+ ;01046d181270 + rotxl.l #2,@-er1 ;01076d181270 + rotxl.l #2,@+er1 ;01056d181270 + rotxl.l #2,@er1- ;01066d181270 + rotxl.l #2,@(0x1234:16,er1) ;01046f1812341270 + rotxl.l #2,@(0x12345678:32,er1) ;78946b28123456781270 + rotxl.l #2,@(0x1234:16,r2l.b) ;01056f2812341270 + rotxl.l #2,@(0x1234:16,r2.w) ;01066f2812341270 + rotxl.l #2,@(0x1234:16,er2.l) ;01076f2812341270 + rotxl.l #2,@(0x12345678:32,r2l.b) ;78a56b28123456781270 + rotxl.l #2,@(0x12345678:32,r2.w) ;78a66b28123456781270 + rotxl.l #2,@(0x12345678:32,er2.l) ;78a76b28123456781270 + rotxl.l #2,@0x1234:16 ;01046b0812341270 + rotxl.l #2,@0x12345678:32 ;01046b28123456781270 + + rotxr.b r1h ;1301 + rotxr.b @er1 ;7d101300 + rotxr.b @(0x3:2,er1) ;017768181300 + rotxr.b @er1+ ;01746c181300 + rotxr.b @-er1 ;01776c181300 + rotxr.b @+er1 ;01756c181300 + rotxr.b @er1- ;01766c181300 + rotxr.b @(0x1234:16,er1) ;01746e1812341300 + rotxr.b @(0x12345678:32,er1) ;78146a28123456781300 + rotxr.b @(0x1234:16,r2l.b) ;01756e2812341300 + rotxr.b @(0x1234:16,r2.w) ;01766e2812341300 + rotxr.b @(0x1234:16,er2.l) ;01776e2812341300 + rotxr.b @(0x12345678:32,r2l.b) ;78256a28123456781300 + rotxr.b @(0x12345678:32,r2.w) ;78266a28123456781300 + rotxr.b @(0x12345678:32,er2.l) ;78276a28123456781300 + rotxr.b @0xffffff12:8 ;7f121300 + rotxr.b @0x1234:16 ;6a1812341300 + rotxr.b @0x12345678:32 ;6a38123456781300 + + rotxr.w r1 ;1311 + rotxr.w @er1 ;7d901310 + rotxr.w @(0x6:2,er1) ;015769181310 + rotxr.w @er1+ ;01546d181310 + rotxr.w @-er1 ;01576d181310 + rotxr.w @+er1 ;01556d181310 + rotxr.w @er1- ;01566d181310 + rotxr.w @(0x1234:16,er1) ;01546f1812341310 + rotxr.w @(0x12345678:32,er1) ;78146b28123456781310 + rotxr.w @(0x1234:16,r2l.b) ;01556f2812341310 + rotxr.w @(0x1234:16,r2.w) ;01566f2812341310 + rotxr.w @(0x1234:16,er2.l) ;01576f2812341310 + rotxr.w @(0x12345678:32,r2l.b) ;78256b28123456781310 + rotxr.w @(0x12345678:32,r2.w) ;78266b28123456781310 + rotxr.w @(0x12345678:32,er2.l) ;78276b28123456781310 + rotxr.w @0x1234:16 ;6b1812341310 + rotxr.w @0x12345678:32 ;6b38123456781310 + + rotxr.l er1 ;1331 + rotxr.l @er1 ;010469181330 + rotxr.l @(0xc:2,er1) ;010769181330 + rotxr.l @er1+ ;01046d181330 + rotxr.l @-er1 ;01076d181330 + rotxr.l @+er1 ;01056d181330 + rotxr.l @er1- ;01066d181330 + rotxr.l @(0x1234:16,er1) ;01046f1812341330 + rotxr.l @(0x12345678:32,er1) ;78946b28123456781330 + rotxr.l @(0x1234:16,r2l.b) ;01056f2812341330 + rotxr.l @(0x1234:16,r2.w) ;01066f2812341330 + rotxr.l @(0x1234:16,er2.l) ;01076f2812341330 + rotxr.l @(0x12345678:32,r2l.b) ;78a56b28123456781330 + rotxr.l @(0x12345678:32,r2.w) ;78a66b28123456781330 + rotxr.l @(0x12345678:32,er2.l) ;78a76b28123456781330 + rotxr.l @0x1234:16 ;01046b0812341330 + rotxr.l @0x12345678:32 ;01046b28123456781330 + + rotxr.b #2,r1h ;1341 + rotxr.b #2,@er1 ;7d101340 + rotxr.b #2,@(0x3:2,er1) ;017768181340 + rotxr.b #2,@er1+ ;01746c181340 + rotxr.b #2,@-er1 ;01776c181340 + rotxr.b #2,@+er1 ;01756c181340 + rotxr.b #2,@er1- ;01766c181340 + rotxr.b #2,@(0x1234:16,er1) ;01746e1812341340 + rotxr.b #2,@(0x12345678:32,er1) ;78146a28123456781340 + rotxr.b #2,@(0x1234:16,r2l.b) ;01756e2812341340 + rotxr.b #2,@(0x1234:16,r2.w) ;01766e2812341340 + rotxr.b #2,@(0x1234:16,er2.l) ;01776e2812341340 + rotxr.b #2,@(0x12345678:32,r2l.b) ;78256a28123456781340 + rotxr.b #2,@(0x12345678:32,r2.w) ;78266a28123456781340 + rotxr.b #2,@(0x12345678:32,er2.l) ;78276a28123456781340 + rotxr.b #2,@0xffffff12:8 ;7f121340 + rotxr.b #2,@0x1234:16 ;6a1812341340 + rotxr.b #2,@0x12345678:32 ;6a38123456781340 + + rotxr.w #2,r1 ;1351 + rotxr.w #2,@er1 ;7d901350 + rotxr.w #2,@(0x6:2,er1) ;015769181350 + rotxr.w #2,@er1+ ;01546d181350 + rotxr.w #2,@-er1 ;01576d181350 + rotxr.w #2,@+er1 ;01556d181350 + rotxr.w #2,@er1- ;01566d181350 + rotxr.w #2,@(0x1234:16,er1) ;01546f1812341350 + rotxr.w #2,@(0x12345678:32,er1) ;78146b28123456781350 + rotxr.w #2,@(0x1234:16,r2l.b) ;01556f2812341350 + rotxr.w #2,@(0x1234:16,r2.w) ;01566f2812341350 + rotxr.w #2,@(0x1234:16,er2.l) ;01576f2812341350 + rotxr.w #2,@(0x12345678:32,r2l.b) ;78256b28123456781350 + rotxr.w #2,@(0x12345678:32,r2.w) ;78266b28123456781350 + rotxr.w #2,@(0x12345678:32,er2.l) ;78276b28123456781350 + rotxr.w #2,@0x1234:16 ;6b1812341350 + rotxr.w #2,@0x12345678:32 ;6b38123456781350 + + rotxr.l #2,er1 ;1371 + rotxr.l #2,@er1 ;010469181370 + rotxr.l #2,@(0xc:2,er1) ;010769181370 + rotxr.l #2,@er1+ ;01046d181370 + rotxr.l #2,@-er1 ;01076d181370 + rotxr.l #2,@+er1 ;01056d181370 + rotxr.l #2,@er1- ;01066d181370 + rotxr.l #2,@(0x1234:16,er1) ;01046f1812341370 + rotxr.l #2,@(0x12345678:32,er1) ;78946b28123456781370 + rotxr.l #2,@(0x1234:16,r2l.b) ;01056f2812341370 + rotxr.l #2,@(0x1234:16,r2.w) ;01066f2812341370 + rotxr.l #2,@(0x1234:16,er2.l) ;01076f2812341370 + rotxr.l #2,@(0x12345678:32,r2l.b) ;78a56b28123456781370 + rotxr.l #2,@(0x12345678:32,r2.w) ;78a66b28123456781370 + rotxr.l #2,@(0x12345678:32,er2.l) ;78a76b28123456781370 + rotxr.l #2,@0x1234:16 ;01046b0812341370 + rotxr.l #2,@0x12345678:32 ;01046b28123456781370 + + rotl.b r1h ;1281 + rotl.b @er1 ;7d101280 + rotl.b @(0x3:2,er1) ;017768181280 + rotl.b @er1+ ;01746c181280 + rotl.b @-er1 ;01776c181280 + rotl.b @+er1 ;01756c181280 + rotl.b @er1- ;01766c181280 + rotl.b @(0x1234:16,er1) ;01746e1812341280 + rotl.b @(0x12345678:32,er1) ;78146a28123456781280 + rotl.b @(0x1234:16,r2l.b) ;01756e2812341280 + rotl.b @(0x1234:16,r2.w) ;01766e2812341280 + rotl.b @(0x1234:16,er2.l) ;01776e2812341280 + rotl.b @(0x12345678:32,r2l.b) ;78256a28123456781280 + rotl.b @(0x12345678:32,r2.w) ;78266a28123456781280 + rotl.b @(0x12345678:32,er2.l) ;78276a28123456781280 + rotl.b @0xffffff12:8 ;7f121280 + rotl.b @0x1234:16 ;6a1812341280 + rotl.b @0x12345678:32 ;6a38123456781280 + + rotl.w r1 ;1291 + rotl.w @er1 ;7d901290 + rotl.w @(0x6:2,er1) ;015769181290 + rotl.w @-er1 ;01576d181290 + rotl.w @er1+ ;01546d181290 + rotl.w @er1- ;01566d181290 + rotl.w @+er1 ;01556d181290 + rotl.w @(0x1234:16,er1) ;01546f1812341290 + rotl.w @(0x12345678:32,er1) ;78146b28123456781290 + rotl.w @(0x1234:16,r2l.b) ;01556f2812341290 + rotl.w @(0x1234:16,r2.w) ;01566f2812341290 + rotl.w @(0x1234:16,er2.l) ;01576f2812341290 + rotl.w @(0x12345678:32,r2l.b) ;78256b28123456781290 + rotl.w @(0x12345678:32,r2.w) ;78266b28123456781290 + rotl.w @(0x12345678:32,er2.l) ;78276b28123456781290 + rotl.w @0x1234:16 ;6b1812341290 + rotl.w @0x12345678:32 ;6b38123456781290 + + rotl.l er1 ;12b1 + rotl.l @er1 ;0104691812b0 + rotl.l @(0xc:2,er1) ;0107691812b0 + rotl.l @er1+ ;01046d1812b0 + rotl.l @-er1 ;01076d1812b0 + rotl.l @+er1 ;01056d1812b0 + rotl.l @er1- ;01066d1812b0 + rotl.l @(0x1234:16,er1) ;01046f18123412b0 + rotl.l @(0x12345678:32,er1) ;78946b281234567812b0 + rotl.l @(0x1234:16,r2l.b) ;01056f28123412b0 + rotl.l @(0x1234:16,r2.w) ;01066f28123412b0 + rotl.l @(0x1234:16,er2.l) ;01076f28123412b0 + rotl.l @(0x12345678:32,r2l.b) ;78a56b281234567812b0 + rotl.l @(0x12345678:32,r2.w) ;78a66b281234567812b0 + rotl.l @(0x12345678:32,er2.l) ;78a76b281234567812b0 + rotl.l @0x1234:16 ;01046b08123412b0 + rotl.l @0x12345678:32 ;01046b281234567812b0 + + rotl.b #2,r1h ;12c1 + rotl.b #2,@er1 ;7d1012c0 + rotl.b #2,@(0x3:2,er1) ;0177681812c0 + rotl.b #2,@er1+ ;01746c1812c0 + rotl.b #2,@-er1 ;01776c1812c0 + rotl.b #2,@+er1 ;01756c1812c0 + rotl.b #2,@er1- ;01766c1812c0 + rotl.b #2,@(0x1234:16,er1) ;01746e18123412c0 + rotl.b #2,@(0x12345678:32,er1) ;78146a281234567812c0 + rotl.b #2,@(0x1234:16,r2l.b) ;01756e28123412c0 + rotl.b #2,@(0x1234:16,r2.w) ;01766e28123412c0 + rotl.b #2,@(0x1234:16,er2.l) ;01776e28123412c0 + rotl.b #2,@(0x12345678:32,r2l.b) ;78256a281234567812c0 + rotl.b #2,@(0x12345678:32,r2.w) ;78266a281234567812c0 + rotl.b #2,@(0x12345678:32,er2.l) ;78276a281234567812c0 + rotl.b #2,@0xffffff12:8 ;7f1212c0 + rotl.b #2,@0x1234:16 ;6a18123412c0 + rotl.b #2,@0x12345678:32 ;6a381234567812c0 + + rotl.w #2,r1 ;12d1 + rotl.w #2,@er1 ;7d9012d0 + rotl.w #2,@(0x6:2,er1) ;0157691812d0 + rotl.w #2,@er1+ ;01546d1812d0 + rotl.w #2,@-er1 ;01576d1812d0 + rotl.w #2,@+er1 ;01556d1812d0 + rotl.w #2,@er1- ;01566d1812d0 + rotl.w #2,@(0x1234:16,er1) ;01546f18123412d0 + rotl.w #2,@(0x12345678:32,er1) ;78146b281234567812d0 + rotl.w #2,@(0x1234:16,r2l.b) ;01556f28123412d0 + rotl.w #2,@(0x1234:16,r2.w) ;01566f28123412d0 + rotl.w #2,@(0x1234:16,er2.l) ;01576f28123412d0 + rotl.w #2,@(0x12345678:32,r2l.b) ;78256b281234567812d0 + rotl.w #2,@(0x12345678:32,r2.w) ;78266b281234567812d0 + rotl.w #2,@(0x12345678:32,er2.l) ;78276b281234567812d0 + rotl.w #2,@0x1234:16 ;6b18123412d0 + rotl.w #2,@0x12345678:32 ;6b381234567812d0 + + rotl.l #2,er1 ;12f1 + rotl.l #2,@er1 ;0104691812f0 + rotl.l #2,@(0xc:2,er1) ;0107691812f0 + rotl.l #2,@er1+ ;01046d1812f0 + rotl.l #2,@-er1 ;01076d1812f0 + rotl.l #2,@+er1 ;01056d1812f0 + rotl.l #2,@er1- ;01066d1812f0 + rotl.l #2,@(0x1234:16,er1) ;01046f18123412f0 + rotl.l #2,@(0x12345678:32,er1) ;78946b281234567812f0 + rotl.l #2,@(0x1234:16,r2l.b) ;01056f28123412f0 + rotl.l #2,@(0x1234:16,r2.w) ;01066f28123412f0 + rotl.l #2,@(0x1234:16,er2.l) ;01076f28123412f0 + rotl.l #2,@(0x12345678:32,r2l.b) ;78a56b281234567812f0 + rotl.l #2,@(0x12345678:32,r2.w) ;78a66b281234567812f0 + rotl.l #2,@(0x12345678:32,er2.l) ;78a76b281234567812f0 + rotl.l #2,@0x1234:16 ;01046b08123412f0 + rotl.l #2,@0x12345678:32 ;01046b281234567812f0 + + rotr.b r1h ;1381 + rotr.b @er1 ;7d101380 + rotr.b @(0x3:2,er1) ;017768181380 + rotr.b @er1+ ;01746c181380 + rotr.b @-er1 ;01776c181380 + rotr.b @+er1 ;01756c181380 + rotr.b @er1- ;01766c181380 + rotr.b @(0x1234:16,er1) ;01746e1812341380 + rotr.b @(0x12345678:32,er1) ;78146a28123456781380 + rotr.b @(0x1234:16,r2l.b) ;01756e2812341380 + rotr.b @(0x1234:16,r2.w) ;01766e2812341380 + rotr.b @(0x1234:16,er2.l) ;01776e2812341380 + rotr.b @(0x12345678:32,r2l.b) ;78256a28123456781380 + rotr.b @(0x12345678:32,r2.w) ;78266a28123456781380 + rotr.b @(0x12345678:32,er2.l) ;78276a28123456781380 + rotr.b @0xffffff12:8 ;7f121380 + rotr.b @0x1234:16 ;6a1812341380 + rotr.b @0x12345678:32 ;6a38123456781380 + + rotr.w r1 ;1391 + rotr.w @er1 ;7d901390 + rotr.w @(0x6:2,er1) ;015769181390 + rotr.w @-er1 ;01576d181390 + rotr.w @er1+ ;01546d181390 + rotr.w @er1- ;01566d181390 + rotr.w @+er1 ;01556d181390 + rotr.w @(0x1234:16,er1) ;01546f1812341390 + rotr.w @(0x12345678:32,er1) ;78146b28123456781390 + rotr.w @(0x1234:16,r2l.b) ;01556f2812341390 + rotr.w @(0x1234:16,r2.w) ;01566f2812341390 + rotr.w @(0x1234:16,er2.l) ;01576f2812341390 + rotr.w @(0x12345678:32,r2l.b) ;78256b28123456781390 + rotr.w @(0x12345678:32,r2.w) ;78266b28123456781390 + rotr.w @(0x12345678:32,er2.l) ;78276b28123456781390 + rotr.w @0x1234:16 ;6b1812341390 + rotr.w @0x12345678:32 ;6b38123456781390 + + rotr.l er1 ;13b1 + rotr.l @er1 ;0104691813b0 + rotr.l @(0xc:2,er1) ;0107691813b0 + rotr.l @er1+ ;01046d1813b0 + rotr.l @-er1 ;01076d1813b0 + rotr.l @+er1 ;01056d1813b0 + rotr.l @er1- ;01066d1813b0 + rotr.l @(0x1234:16,er1) ;01046f18123413b0 + rotr.l @(0x12345678:32,er1) ;78946b281234567813b0 + rotr.l @(0x1234:16,r2l.b) ;01056f28123413b0 + rotr.l @(0x1234:16,r2.w) ;01066f28123413b0 + rotr.l @(0x1234:16,er2.l) ;01076f28123413b0 + rotr.l @(0x12345678:32,r2l.b) ;78a56b281234567813b0 + rotr.l @(0x12345678:32,r2.w) ;78a66b281234567813b0 + rotr.l @(0x12345678:32,er2.l) ;78a76b281234567813b0 + rotr.l @0x1234:16 ;01046b08123413b0 + rotr.l @0x12345678:32 ;01046b281234567813b0 + + rotr.b #2,r1h ;13c1 + rotr.b #2,@er1 ;7d1013c0 + rotr.b #2,@(0x3:2,er1) ;0177681813c0 + rotr.b #2,@er1+ ;01746c1813c0 + rotr.b #2,@-er1 ;01776c1813c0 + rotr.b #2,@+er1 ;01756c1813c0 + rotr.b #2,@er1- ;01766c1813c0 + rotr.b #2,@(0x1234:16,er1) ;01746e18123413c0 + rotr.b #2,@(0x12345678:32,er1) ;78146a281234567813c0 + rotr.b #2,@(0x1234:16,r2l.b) ;01756e28123413c0 + rotr.b #2,@(0x1234:16,r2.w) ;01766e28123413c0 + rotr.b #2,@(0x1234:16,er2.l) ;01776e28123413c0 + rotr.b #2,@(0x12345678:32,r2l.b) ;78256a281234567813c0 + rotr.b #2,@(0x12345678:32,r2.w) ;78266a281234567813c0 + rotr.b #2,@(0x12345678:32,er2.l) ;78276a281234567813c0 + rotr.b #2,@0xffffff12:8 ;7f1213c0 + rotr.b #2,@0x1234:16 ;6a18123413c0 + rotr.b #2,@0x12345678:32 ;6a381234567813c0 + + rotr.w #2,r1 ;13d1 + rotr.w #2,@er1 ;7d9013d0 + rotr.w #2,@(0x6:2,er1) ;0157691813d0 + rotr.w #2,@er1+ ;01546d1813d0 + rotr.w #2,@-er1 ;01576d1813d0 + rotr.w #2,@+er1 ;01556d1813d0 + rotr.w #2,@er1- ;01566d1813d0 + rotr.w #2,@(0x1234:16,er1) ;01546f18123413d0 + rotr.w #2,@(0x12345678:32,er1) ;78146b281234567813d0 + rotr.w #2,@(0x1234:16,r2l.b) ;01556f28123413d0 + rotr.w #2,@(0x1234:16,r2.w) ;01566f28123413d0 + rotr.w #2,@(0x1234:16,er2.l) ;01576f28123413d0 + rotr.w #2,@(0x12345678:32,r2l.b) ;78256b281234567813d0 + rotr.w #2,@(0x12345678:32,r2.w) ;78266b281234567813d0 + rotr.w #2,@(0x12345678:32,er2.l) ;78276b281234567813d0 + rotr.w #2,@0x1234:16 ;6b18123413d0 + rotr.w #2,@0x12345678:32 ;6b381234567813d0 + + rotr.l #2,er1 ;13f1 + rotr.l #2,@er1 ;0104691813f0 + rotr.l #2,@(0xc:2,er1) ;0107691813f0 + rotr.l #2,@er1+ ;01046d1813f0 + rotr.l #2,@-er1 ;01076d1813f0 + rotr.l #2,@+er1 ;01056d1813f0 + rotr.l #2,@er1- ;01066d1813f0 + rotr.l #2,@(0x1234:16,er1) ;01046f18123413f0 + rotr.l #2,@(0x12345678:32,er1) ;78946b281234567813f0 + rotr.l #2,@(0x1234:16,r2l.b) ;01056f28123413f0 + rotr.l #2,@(0x1234:16,r2.w) ;01066f28123413f0 + rotr.l #2,@(0x1234:16,er2.l) ;01076f28123413f0 + rotr.l #2,@(0x12345678:32,r2l.b) ;78a56b281234567813f0 + rotr.l #2,@(0x12345678:32,r2.w) ;78a66b281234567813f0 + rotr.l #2,@(0x12345678:32,er2.l) ;78a76b281234567813f0 + rotr.l #2,@0x1234:16 ;01046b08123413f0 + rotr.l #2,@0x12345678:32 ;01046b281234567813f0 + + .end diff --git a/gdb/testsuite/gdb.disasm/t12_bit.exp b/gdb/testsuite/gdb.disasm/t12_bit.exp new file mode 100644 index 0000000..c59cdc8 --- /dev/null +++ b/gdb/testsuite/gdb.disasm/t12_bit.exp @@ -0,0 +1,330 @@ +# Copyright (C) 2003 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# Please email any bugs, comments, and/or additions to this file to: +# bug-gdb@prep.ai.mit.edu + +# This file was written by Michael Snyder (msnyder@redhat.com) + +if $tracelevel then { + strace $tracelevel +} + +if ![istarget "h8300*-*-*"] { + verbose "Tests ignored for all but h8300s based targets." + return +} + +set prms_id 0 +set bug_id 0 + +set testfile "t12_bit" +set srcfile ${srcdir}/${subdir}/${testfile}.s +set objfile ${objdir}/${subdir}/${testfile}.o +set binfile ${objdir}/${subdir}/${testfile}.x + +set asm-flags ""; +set link-flags "-m h8300sxelf"; + + +if {[target_assemble $srcfile $objfile "${asm-flags}"] != ""} then { + gdb_suppress_entire_file "Testcase assembly failed, so all tests in this file will automatically fail." +} + +if {[target_link $objfile $binfile "${link-flags}"] != ""} then { + gdb_suppress_entire_file "Testcase link failed, so all tests in this file will automatically fail." +} + +gdb_start +gdb_reinitialize_dir $srcdir/$subdir +gdb_load $binfile + +gdb_test "x /i _start" "bset\t#0x7,r1h" \ + "bset #0x7,r1h" +gdb_test "x" "bset\t#0x7,@er1" \ + "bset #0x7,@er1" +gdb_test "x" "bset\t#0x7,@0x12(:8|)" \ + "bset #0x7,@0x12:8" +gdb_test "x" "bset\t#0x7,@0x1234(:16|)" \ + "bset #0x7,@0x1234:16" +gdb_test "x" "bset\t#0x7,@0x12345678(:32|)" \ + "bset #0x7,@0x12345678:32" +gdb_test "x" "bset\tr3h,r1h" \ + "bset r3h,r1h" +gdb_test "x" "bset\tr3h,@er1" \ + "bset r3h,@er1" +gdb_test "x" "bset\tr3h,@0x12(:8|)" \ + "bset r3h,@0x12:8" +gdb_test "x" "bset\tr3h,@0x1234(:16|)" \ + "bset r3h,@0x1234:16" +gdb_test "x" "bset\tr3h,@0x12345678(:32|)" \ + "bset r3h,@0x12345678:32" +gdb_test "x" "bset/eq\t#0x7,@er1" \ + "bset/eq #0x7,@er1" +gdb_test "x" "bset/eq\t#0x7,@0x12(:8|)" \ + "bset/eq #0x7,@0x12:8" +gdb_test "x" "bset/eq\t#0x7,@0x1234(:16|)" \ + "bset/eq #0x7,@0x1234:16" +gdb_test "x" "bset/eq\t#0x7,@0x12345678(:32|)" \ + "bset/eq #0x7,@0x12345678:32" +gdb_test "x" "bset/eq\tr3h,@er1" \ + "bset/eq r3h,@er1" +gdb_test "x" "bset/eq\tr3h,@0x12(:8|)" \ + "bset/eq r3h,@0x12:8" +gdb_test "x" "bset/eq\tr3h,@0x1234(:16|)" \ + "bset/eq r3h,@0x1234:16" +gdb_test "x" "bset/eq\tr3h,@0x12345678(:32|)" \ + "bset/eq r3h,@0x12345678:32" +gdb_test "x" "bset/ne\t#0x7,@er1" \ + "bset/ne #0x7,@er1" +gdb_test "x" "bset/ne\t#0x7,@0x12(:8|)" \ + "bset/ne #0x7,@0x12:8" +gdb_test "x" "bset/ne\t#0x7,@0x1234(:16|)" \ + "bset/ne #0x7,@0x1234:16" +gdb_test "x" "bset/ne\t#0x7,@0x12345678(:32|)" \ + "bset/ne #0x7,@0x12345678:32" +gdb_test "x" "bset/ne\tr3h,@er1" \ + "bset/ne r3h,@er1" +gdb_test "x" "bset/ne\tr3h,@0x12(:8|)" \ + "bset/ne r3h,@0x12:8" +gdb_test "x" "bset/ne\tr3h,@0x1234(:16|)" \ + "bset/ne r3h,@0x1234:16" +gdb_test "x" "bset/ne\tr3h,@0x12345678(:32|)" \ + "bset/ne r3h,@0x12345678:32" +gdb_test "x" "bnot\t#0x7,r1h" \ + "bnot #0x7,r1h" +gdb_test "x" "bnot\t#0x7,@er1" \ + "bnot #0x7,@er1" +gdb_test "x" "bnot\t#0x7,@0x12(:8|)" \ + "bnot #0x7,@0x12:8" +gdb_test "x" "bnot\t#0x7,@0x1234(:16|)" \ + "bnot #0x7,@0x1234:16" +gdb_test "x" "bnot\t#0x7,@0x12345678(:32|)" \ + "bnot #0x7,@0x12345678:32" +gdb_test "x" "bnot\tr3h,r1h" \ + "bnot r3h,r1h" +gdb_test "x" "bnot\tr3h,@er1" \ + "bnot r3h,@er1" +gdb_test "x" "bnot\tr3h,@0x12(:8|)" \ + "bnot r3h,@0x12:8" +gdb_test "x" "bnot\tr3h,@0x1234(:16|)" \ + "bnot r3h,@0x1234:16" +gdb_test "x" "bnot\tr3h,@0x12345678(:32|)" \ + "bnot r3h,@0x12345678:32" +gdb_test "x" "bclr\t#0x7,r1h" \ + "bclr #0x7,r1h" +gdb_test "x" "bclr\t#0x7,@er1" \ + "bclr #0x7,@er1" +gdb_test "x" "bclr\t#0x7,@0x12(:8|)" \ + "bclr #0x7,@0x12:8" +gdb_test "x" "bclr\t#0x7,@0x1234(:16|)" \ + "bclr #0x7,@0x1234:16" +gdb_test "x" "bclr\t#0x7,@0x12345678(:32|)" \ + "bclr #0x7,@0x12345678:32" +gdb_test "x" "bclr\tr3h,r1h" \ + "bclr r3h,r1h" +gdb_test "x" "bclr\tr3h,@er1" \ + "bclr r3h,@er1" +gdb_test "x" "bclr\tr3h,@0x12(:8|)" \ + "bclr r3h,@0x12:8" +gdb_test "x" "bclr\tr3h,@0x1234(:16|)" \ + "bclr r3h,@0x1234:16" +gdb_test "x" "bclr\tr3h,@0x12345678(:32|)" \ + "bclr r3h,@0x12345678:32" +gdb_test "x" "bclr/eq\t#0x7,@er1" \ + "bclr/eq #0x7,@er1" +gdb_test "x" "bclr/eq\t#0x7,@0x12(:8|)" \ + "bclr/eq #0x7,@0x12:8" +gdb_test "x" "bclr/eq\t#0x7,@0x1234(:16|)" \ + "bclr/eq #0x7,@0x1234:16" +gdb_test "x" "bclr/eq\t#0x7,@0x12345678(:32|)" \ + "bclr/eq #0x7,@0x12345678:32" +gdb_test "x" "bclr/eq\tr3h,@er1" \ + "bclr/eq r3h,@er1" +gdb_test "x" "bclr/eq\tr3h,@0x12(:8|)" \ + "bclr/eq r3h,@0x12:8" +gdb_test "x" "bclr/eq\tr3h,@0x1234(:16|)" \ + "bclr/eq r3h,@0x1234:16" +gdb_test "x" "bclr/eq\tr3h,@0x12345678(:32|)" \ + "bclr/eq r3h,@0x12345678:32" +gdb_test "x" "bclr/ne\t#0x7,@er1" \ + "bclr/ne #0x7,@er1" +gdb_test "x" "bclr/ne\t#0x7,@0x12(:8|)" \ + "bclr/ne #0x7,@0x12:8" +gdb_test "x" "bclr/ne\t#0x7,@0x1234(:16|)" \ + "bclr/ne #0x7,@0x1234:16" +gdb_test "x" "bclr/ne\t#0x7,@0x12345678(:32|)" \ + "bclr/ne #0x7,@0x12345678:32" +gdb_test "x" "bclr/ne\tr3h,@er1" \ + "bclr/ne r3h,@er1" +gdb_test "x" "bclr/ne\tr3h,@0x12(:8|)" \ + "bclr/ne r3h,@0x12:8" +gdb_test "x" "bclr/ne\tr3h,@0x1234(:16|)" \ + "bclr/ne r3h,@0x1234:16" +gdb_test "x" "bclr/ne\tr3h,@0x12345678(:32|)" \ + "bclr/ne r3h,@0x12345678:32" +gdb_test "x" "btst\t#0x7,r1h" \ + "btst #0x7,r1h" +gdb_test "x" "btst\t#0x7,@er1" \ + "btst #0x7,@er1" +gdb_test "x" "btst\t#0x7,@0x12(:8|)" \ + "btst #0x7,@0x12:8" +gdb_test "x" "btst\t#0x7,@0x1234(:16|)" \ + "btst #0x7,@0x1234:16" +gdb_test "x" "btst\t#0x7,@0x12345678(:32|)" \ + "btst #0x7,@0x12345678:32" +gdb_test "x" "btst\tr3h,r1h" \ + "btst r3h,r1h" +gdb_test "x" "btst\tr3h,@er1" \ + "btst r3h,@er1" +gdb_test "x" "btst\tr3h,@0x12(:8|)" \ + "btst r3h,@0x12:8" +gdb_test "x" "btst\tr3h,@0x1234(:16|)" \ + "btst r3h,@0x1234:16" +gdb_test "x" "btst\tr3h,@0x12345678(:32|)" \ + "btst r3h,@0x12345678:32" +gdb_test "x" "bor\t#0x7,r1h" \ + "bor #0x7,r1h" +gdb_test "x" "bor\t#0x7,@er1" \ + "bor #0x7,@er1" +gdb_test "x" "bor\t#0x7,@0x12(:8|)" \ + "bor #0x7,@0x12:8" +gdb_test "x" "bor\t#0x7,@0x1234(:16|)" \ + "bor #0x7,@0x1234:16" +gdb_test "x" "bor\t#0x7,@0x12345678(:32|)" \ + "bor #0x7,@0x12345678:32" +gdb_test "x" "bior\t#0x7,r1h" \ + "bior #0x7,r1h" +gdb_test "x" "bior\t#0x7,@er1" \ + "bior #0x7,@er1" +gdb_test "x" "bior\t#0x7,@0x12(:8|)" \ + "bior #0x7,@0x12:8" +gdb_test "x" "bior\t#0x7,@0x1234(:16|)" \ + "bior #0x7,@0x1234:16" +gdb_test "x" "bior\t#0x7,@0x12345678(:32|)" \ + "bior #0x7,@0x12345678:32" +gdb_test "x" "bxor\t#0x7,r1h" \ + "bxor #0x7,r1h" +gdb_test "x" "bxor\t#0x7,@er1" \ + "bxor #0x7,@er1" +gdb_test "x" "bxor\t#0x7,@0x12(:8|)" \ + "bxor #0x7,@0x12:8" +gdb_test "x" "bxor\t#0x7,@0x1234(:16|)" \ + "bxor #0x7,@0x1234:16" +gdb_test "x" "bxor\t#0x7,@0x12345678(:32|)" \ + "bxor #0x7,@0x12345678:32" +gdb_test "x" "bixor\t#0x7,r1h" \ + "bixor #0x7,r1h" +gdb_test "x" "bixor\t#0x7,@er1" \ + "bixor #0x7,@er1" +gdb_test "x" "bixor\t#0x7,@0x12(:8|)" \ + "bixor #0x7,@0x12:8" +gdb_test "x" "bixor\t#0x7,@0x1234(:16|)" \ + "bixor #0x7,@0x1234:16" +gdb_test "x" "bixor\t#0x7,@0x12345678(:32|)" \ + "bixor #0x7,@0x12345678:32" +gdb_test "x" "band\t#0x7,r1h" \ + "band #0x7,r1h" +gdb_test "x" "band\t#0x7,@er1" \ + "band #0x7,@er1" +gdb_test "x" "band\t#0x7,@0x12(:8|)" \ + "band #0x7,@0x12:8" +gdb_test "x" "band\t#0x7,@0x1234(:16|)" \ + "band #0x7,@0x1234:16" +gdb_test "x" "band\t#0x7,@0x12345678(:32|)" \ + "band #0x7,@0x12345678:32" +gdb_test "x" "biand\t#0x7,r1h" \ + "biand #0x7,r1h" +gdb_test "x" "biand\t#0x7,@er1" \ + "biand #0x7,@er1" +gdb_test "x" "biand\t#0x7,@0x12(:8|)" \ + "biand #0x7,@0x12:8" +gdb_test "x" "biand\t#0x7,@0x1234(:16|)" \ + "biand #0x7,@0x1234:16" +gdb_test "x" "biand\t#0x7,@0x12345678(:32|)" \ + "biand #0x7,@0x12345678:32" +gdb_test "x" "bld\t#0x7,r1h" \ + "bld #0x7,r1h" +gdb_test "x" "bld\t#0x7,@er1" \ + "bld #0x7,@er1" +gdb_test "x" "bld\t#0x7,@0x12(:8|)" \ + "bld #0x7,@0x12:8" +gdb_test "x" "bld\t#0x7,@0x1234(:16|)" \ + "bld #0x7,@0x1234:16" +gdb_test "x" "bld\t#0x7,@0x12345678(:32|)" \ + "bld #0x7,@0x12345678:32" +gdb_test "x" "bild\t#0x7,r1h" \ + "bild #0x7,r1h" +gdb_test "x" "bild\t#0x7,@er1" \ + "bild #0x7,@er1" +gdb_test "x" "bild\t#0x7,@0x12(:8|)" \ + "bild #0x7,@0x12:8" +gdb_test "x" "bild\t#0x7,@0x1234(:16|)" \ + "bild #0x7,@0x1234:16" +gdb_test "x" "bild\t#0x7,@0x12345678(:32|)" \ + "bild #0x7,@0x12345678:32" +gdb_test "x" "bst\t#0x7,r1h" \ + "bst #0x7,r1h" +gdb_test "x" "bst\t#0x7,@er1" \ + "bst #0x7,@er1" +gdb_test "x" "bst\t#0x7,@0x12(:8|)" \ + "bst #0x7,@0x12:8" +gdb_test "x" "bst\t#0x7,@0x1234(:16|)" \ + "bst #0x7,@0x1234:16" +gdb_test "x" "bst\t#0x7,@0x12345678(:32|)" \ + "bst #0x7,@0x12345678:32" +gdb_test "x" "bstz\t#0x7,@er1" \ + "bstz #0x7,@er1" +gdb_test "x" "bstz\t#0x7,@0x12(:8|)" \ + "bstz #0x7,@0x12:8" +gdb_test "x" "bstz\t#0x7,@0x1234(:16|)" \ + "bstz #0x7,@0x1234:16" +gdb_test "x" "bstz\t#0x7,@0x12345678(:32|)" \ + "bstz #0x7,@0x12345678:32" +gdb_test "x" "bist\t#0x7,r1h" \ + "bist #0x7,r1h" +gdb_test "x" "bist\t#0x7,@er1" \ + "bist #0x7,@er1" +gdb_test "x" "bist\t#0x7,@0x12(:8|)" \ + "bist #0x7,@0x12:8" +gdb_test "x" "bist\t#0x7,@0x1234(:16|)" \ + "bist #0x7,@0x1234:16" +gdb_test "x" "bist\t#0x7,@0x12345678(:32|)" \ + "bist #0x7,@0x12345678:32" +gdb_test "x" "bistz\t#0x7,@er1" \ + "bistz #0x7,@er1" +gdb_test "x" "bistz\t#0x7,@0x12(:8|)" \ + "bistz #0x7,@0x12:8" +gdb_test "x" "bistz\t#0x7,@0x1234(:16|)" \ + "bistz #0x7,@0x1234:16" +gdb_test "x" "bistz\t#0x7,@0x12345678(:32|)" \ + "bistz #0x7,@0x12345678:32" +gdb_test "x" "bfld\t#0x34(:8|),@er1,r3h" \ + "bfld #0x34:8,@er1,r3h" +gdb_test "x" "bfld\t#0x34(:8|),@0x12(:8|),r3h" \ + "bfld #0x34:8,@0x12:8,r3h" +gdb_test "x" "bfld\t#0x34(:8|),@0x1234(:16|),r3h" \ + "bfld #0x34:8,@0x1234:16,r3h" +gdb_test "x" "bfld\t#0x34(:8|),@0x12345678(:32|),r3h" \ + "bfld #0x34:8,@0x12345678:32,r3h" +gdb_test "x" "bfst\tr3h,#0x34(:8|),@er1" \ + "bfst r3h,#0x34:8,@er1" +gdb_test "x" "bfst\tr3h,#0x34(:8|),@0x12(:8|)" \ + "bfst r3h,#0x34:8,@0x12:8" +gdb_test "x" "bfst\tr3h,#0x34(:8|),@0x1234(:16|)" \ + "bfst r3h,#0x34:8,@0x1234:16" +gdb_test "x" "bfst\tr3h,#0x34(:8|),@0x12345678(:32|)" \ + "bfst r3h,#0x34:8,@0x12345678:32" diff --git a/gdb/testsuite/gdb.disasm/t12_bit.s b/gdb/testsuite/gdb.disasm/t12_bit.s new file mode 100644 index 0000000..cd22f2f --- /dev/null +++ b/gdb/testsuite/gdb.disasm/t12_bit.s @@ -0,0 +1,176 @@ +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;bit +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + .h8300sx + .text + .global _start +_start: + bset #0x7,r1h ;7071 + bset #0x7,@er1 ;7d107070 + bset #0x7,@0xffffff12:8 ;7f127070 + bset #0x7,@0x1234:16 ;6a1812347070 + bset #0x7,@0x12345678:32 ;6a38123456787070 + + bset r3h,r1h ;6031 + bset r3h,@er1 ;7d106030 + bset r3h,@0xffffff12:8 ;7f126030 + bset r3h,@0x1234:16 ;6a1812346030 + bset r3h,@0x12345678:32 ;6a38123456786030 + + bset/eq #0x7,@er1 ;7d107077 + bset/eq #0x7,@0xffffff12:8 ;7f127077 + bset/eq #0x7,@0x1234:16 ;6a1812347077 + bset/eq #0x7,@0x12345678:32 ;6a38123456787077 + + bset/eq r3h,@er1 ;7d106037 + bset/eq r3h,@0xffffff12:8 ;7f126037 + bset/eq r3h,@0x1234:16 ;6a1812346037 + bset/eq r3h,@0x12345678:32 ;6a38123456786037 + + bset/ne #0x7,@er1 ;7d107076 + bset/ne #0x7,@0xffffff12:8 ;7f127076 + bset/ne #0x7,@0x1234:16 ;6a1812347076 + bset/ne #0x7,@0x12345678:32 ;6a38123456787076 + + bset/ne r3h,@er1 ;7d106036 + bset/ne r3h,@0xffffff12:8 ;7f126036 + bset/ne r3h,@0x1234:16 ;6a1812346036 + bset/ne r3h,@0x12345678:32 ;6a38123456786036 + + bnot #0x7,r1h ;7171 + bnot #0x7,@er1 ;7d107170 + bnot #0x7,@0xffffff12:8 ;7f127170 + bnot #0x7,@0x1234:16 ;6a1812347170 + bnot #0x7,@0x12345678:32 ;6a38123456787170 + + bnot r3h,r1h ;6131 + bnot r3h,@er1 ;7d106130 + bnot r3h,@0xffffff12:8 ;7f126130 + bnot r3h,@0x1234:16 ;6a1812346130 + bnot r3h,@0x12345678:32 ;6a38123456786130 + + bclr #0x7,r1h ;7271 + bclr #0x7,@er1 ;7d107270 + bclr #0x7,@0xffffff12:8 ;7f127270 + bclr #0x7,@0x1234:16 ;6a1812347270 + bclr #0x7,@0x12345678:32 ;6a38123456787270 + + bclr r3h,r1h ;6231 + bclr r3h,@er1 ;7d106230 + bclr r3h,@0xffffff12:8 ;7f126230 + bclr r3h,@0x1234:16 ;6a1812346230 + bclr r3h,@0x12345678:32 ;6a38123456786230 + + bclr/eq #0x7,@er1 ;7d107277 + bclr/eq #0x7,@0xffffff12:8 ;7f127277 + bclr/eq #0x7,@0x1234:16 ;6a1812347277 + bclr/eq #0x7,@0x12345678:32 ;6a38123456787277 + + bclr/eq r3h,@er1 ;7d106237 + bclr/eq r3h,@0xffffff12:8 ;7f126237 + bclr/eq r3h,@0x1234:16 ;6a1812346237 + bclr/eq r3h,@0x12345678:32 ;6a38123456786237 + + bclr/ne #0x7,@er1 ;7d107276 + bclr/ne #0x7,@0xffffff12:8 ;7f127276 + bclr/ne #0x7,@0x1234:16 ;6a1812347276 + bclr/ne #0x7,@0x12345678:32 ;6a38123456787276 + + bclr/ne r3h,@er1 ;7d106236 + bclr/ne r3h,@0xffffff12:8 ;7f126236 + bclr/ne r3h,@0x1234:16 ;6a1812346236 + bclr/ne r3h,@0x12345678:32 ;6a38123456786236 + + btst #0x7,r1h ;7371 + btst #0x7,@er1 ;7c107370 + btst #0x7,@0xffffff12:8 ;7e127370 + btst #0x7,@0x1234:16 ;6a1012347370 + btst #0x7,@0x12345678:32 ;6a30123456787370 + + btst r3h,r1h ;6331 + btst r3h,@er1 ;7c106330 + btst r3h,@0xffffff12:8 ;7e126330 + btst r3h,@0x1234:16 ;6a1012346330 + btst r3h,@0x12345678:32 ;6a30123456786330 + + bor #0x7,r1h ;7471 + bor #0x7,@er1 ;7c107470 + bor #0x7,@0xffffff12:8 ;7e127470 + bor #0x7,@0x1234:16 ;6a1012347470 + bor #0x7,@0x12345678:32 ;6a30123456787470 + + bior #0x7,r1h ;74f1 + bior #0x7,@er1 ;7c1074f0 + bior #0x7,@0xffffff12:8 ;7e1274f0 + bior #0x7,@0x1234:16 ;6a10123474f0 + bior #0x7,@0x12345678:32 ;6a301234567874f0 + + bxor #0x7,r1h ;7571 + bxor #0x7,@er1 ;7c107570 + bxor #0x7,@0xffffff12:8 ;7e127570 + bxor #0x7,@0x1234:16 ;6a1012347570 + bxor #0x7,@0x12345678:32 ;6a30123456787570 + + bixor #0x7,r1h ;75f1 + bixor #0x7,@er1 ;7c1075f0 + bixor #0x7,@0xffffff12:8 ;7e1275f0 + bixor #0x7,@0x1234:16 ;6a10123475f0 + bixor #0x7,@0x12345678:32 ;6a301234567875f0 + + band #0x7,r1h ;7671 + band #0x7,@er1 ;7c107670 + band #0x7,@0xffffff12:8 ;7e127670 + band #0x7,@0x1234:16 ;6a1012347670 + band #0x7,@0x12345678:32 ;6a30123456787670 + + biand #0x7,r1h ;76f1 + biand #0x7,@er1 ;7c1076f0 + biand #0x7,@0xffffff12:8 ;7e1276f0 + biand #0x7,@0x1234:16 ;6a10123476f0 + biand #0x7,@0x12345678:32 ;6a301234567876f0 + + bld #0x7,r1h ;7771 + bld #0x7,@er1 ;7c107770 + bld #0x7,@0xffffff12:8 ;7e127770 + bld #0x7,@0x1234:16 ;6a1012347770 + bld #0x7,@0x12345678:32 ;6a30123456787770 + + bild #0x7,r1h ;77f1 + bild #0x7,@er1 ;7c1077f0 + bild #0x7,@0xffffff12:8 ;7e1277f0 + bild #0x7,@0x1234:16 ;6a10123477f0 + bild #0x7,@0x12345678:32 ;6a301234567877f0 + + bst #0x7,r1h ;6771 + bst #0x7,@er1 ;7d106770 + bst #0x7,@0xffffff12:8 ;7f126770 + bst #0x7,@0x1234:16 ;6a1812346770 + bst #0x7,@0x12345678:32 ;6a38123456786770 + + bstz #0x7,@er1 ;7d106777 + bstz #0x7,@0xffffff12:8 ;7f126777 + bstz #0x7,@0x1234:16 ;6a1812346777 + bstz #0x7,@0x12345678:32 ;6a38123456786777 + + bist #0x7,r1h ;67f1 + bist #0x7,@er1 ;7d1067f0 + bist #0x7,@0xffffff12:8 ;7f1267f0 + bist #0x7,@0x1234:16 ;6a18123467f0 + bist #0x7,@0x12345678:32 ;6a381234567867f0 + + bistz #0x7,@er1 ;7d1067f7 + bistz #0x7,@0xffffff12:8 ;7f1267f7 + bistz #0x7,@0x1234:16 ;6a18123467f7 + bistz #0x7,@0x12345678:32 ;6a381234567867f7 + + bfld #0x34:8,@er1,r3h ;7c10f334 + bfld #0x34:8,@0xffffff12:8,r3h ;7e12f334 + bfld #0x34:8,@0x1234:16,r3h ;6a101234f334 + bfld #0x34:8,@0x12345678:32,r3h ;6a3012345678f334 + + bfst r3h,#0x34:8,@er1 ;7d10f334 + bfst r3h,#0x34:8,@0xffffff12:8 ;7f12f334 + bfst r3h,#0x34:8,@0x1234:16 ;6a181234f334 + bfst r3h,#0x34:8,@0x12345678:32 ;6a3812345678f334 + + .end diff --git a/gdb/testsuite/gdb.disasm/t13_otr.exp b/gdb/testsuite/gdb.disasm/t13_otr.exp new file mode 100644 index 0000000..5c01842 --- /dev/null +++ b/gdb/testsuite/gdb.disasm/t13_otr.exp @@ -0,0 +1,306 @@ +# Copyright (C) 2003 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# Please email any bugs, comments, and/or additions to this file to: +# bug-gdb@prep.ai.mit.edu + +# This file was written by Michael Snyder (msnyder@redhat.com) + +if $tracelevel then { + strace $tracelevel +} + +if ![istarget "h8300*-*-*"] { + verbose "Tests ignored for all but h8300s based targets." + return +} + +set prms_id 0 +set bug_id 0 + +set testfile "t13_otr" +set srcfile ${srcdir}/${subdir}/${testfile}.s +set objfile ${objdir}/${subdir}/${testfile}.o +set binfile ${objdir}/${subdir}/${testfile}.x + +set asm-flags ""; +set link-flags "-m h8300sxelf"; + + +if {[target_assemble $srcfile $objfile "${asm-flags}"] != ""} then { + gdb_suppress_entire_file "Testcase assembly failed, so all tests in this file will automatically fail." +} + +if {[target_link $objfile $binfile "${link-flags}"] != ""} then { + gdb_suppress_entire_file "Testcase link failed, so all tests in this file will automatically fail." +} + +gdb_start +gdb_reinitialize_dir $srcdir/$subdir +gdb_load $binfile + +global hex + +gdb_test "x /i _start" "bra\t.\\+18 \\($hex\\)" \ + "bra .+18" +gdb_test "x" "brn\t.\\+18 \\($hex\\)" \ + "brn .+18" +gdb_test "x" "bhi\t.\\+18 \\($hex\\)" \ + "bhi .+18" +gdb_test "x" "bls\t.\\+18 \\($hex\\)" \ + "bls .+18" +gdb_test "x" "bcc\t.\\+18 \\($hex\\)" \ + "bcc .+18" +gdb_test "x" "bcs\t.\\+18 \\($hex\\)" \ + "bcs .+18" +gdb_test "x" "bne\t.\\+18 \\($hex\\)" \ + "bne .+18" +gdb_test "x" "beq\t.\\+18 \\($hex\\)" \ + "beq .+18" +gdb_test "x" "bvc\t.\\+18 \\($hex\\)" \ + "bvc .+18" +gdb_test "x" "bvs\t.\\+18 \\($hex\\)" \ + "bvs .+18" +gdb_test "x" "bpl\t.\\+18 \\($hex\\)" \ + "bpl .+18" +gdb_test "x" "bmi\t.\\+18 \\($hex\\)" \ + "bmi .+18" +gdb_test "x" "bge\t.\\+18 \\($hex\\)" \ + "bge .+18" +gdb_test "x" "blt\t.\\+18 \\($hex\\)" \ + "blt .+18" +gdb_test "x" "bgt\t.\\+18 \\($hex\\)" \ + "bgt .+18" +gdb_test "x" "ble\t.\\+18 \\($hex\\)" \ + "ble .+18" +gdb_test "x" "bra\t.\\+4660 \\($hex\\)" \ + "bra .+4660" +gdb_test "x" "brn\t.\\+4660 \\($hex\\)" \ + "brn .+4660" +gdb_test "x" "bhi\t.\\+4660 \\($hex\\)" \ + "bhi .+4660" +gdb_test "x" "bls\t.\\+4660 \\($hex\\)" \ + "bls .+4660" +gdb_test "x" "bcc\t.\\+4660 \\($hex\\)" \ + "bcc .+4660" +gdb_test "x" "bcs\t.\\+4660 \\($hex\\)" \ + "bcs .+4660" +gdb_test "x" "bne\t.\\+4660 \\($hex\\)" \ + "bne .+4660" +gdb_test "x" "beq\t.\\+4660 \\($hex\\)" \ + "beq .+4660" +gdb_test "x" "bvc\t.\\+4660 \\($hex\\)" \ + "bvc .+4660" +gdb_test "x" "bvs\t.\\+4660 \\($hex\\)" \ + "bvs .+4660" +gdb_test "x" "bpl\t.\\+4660 \\($hex\\)" \ + "bpl .+4660" +gdb_test "x" "bmi\t.\\+4660 \\($hex\\)" \ + "bmi .+4660" +gdb_test "x" "bge\t.\\+4660 \\($hex\\)" \ + "bge .+4660" +gdb_test "x" "blt\t.\\+4660 \\($hex\\)" \ + "blt .+4660" +gdb_test "x" "bgt\t.\\+4660 \\($hex\\)" \ + "bgt .+4660" +gdb_test "x" "ble\t.\\+4660 \\($hex\\)" \ + "ble .+4660" +gdb_test "x" "bra/s\t.\\+18 \\($hex\\)" \ + "bra/s .+18" +gdb_test "x" "nop\[ \t\]*" \ + "nop" +gdb_test "x" "bra/bc\t#0x7,@er2,.\\+18 \\($hex\\)" \ + "bra/bc #0x7,@er2,.+18" +gdb_test "x" "bra/bc\t#0x7,@0x9a(:8|),.\\+18 \\($hex\\)" \ + "bra/bc #0x7,@0x9a:8,.+18" +gdb_test "x" "bra/bc\t#0x7,@0x1234(:16|),.\\+18 \\($hex\\)" \ + "bra/bc #0x7,@0x1234:16,.+18" +gdb_test "x" "bra/bc\t#0x7,@0x12345678(:32|),.\\+18 \\($hex\\)" \ + "bra/bc #0x7,@0x12345678:32,.+18" +gdb_test "x" "bra/bc\t#0x7,@er2,.\\+4660 \\($hex\\)" \ + "bra/bc #0x7,@er2,.+4660" +gdb_test "x" "bra/bc\t#0x7,@0x12(:8|),.\\+4660 \\($hex\\)" \ + "bra/bc #0x7,@0x12:8,.+4660" +gdb_test "x" "bra/bc\t#0x7,@0x9abc(:16|),.\\+4660 \\($hex\\)" \ + "bra/bc #0x7,@0x9abc:16,.+4660" +gdb_test "x" "bra/bc\t#0x7,@0x12345678(:32|),.\\+4660 \\($hex\\)" \ + "bra/bc #0x7,@0x12345678:32,.+4660" +gdb_test "x" "bra/bs\t#0x7,@er2,.\\+18 \\($hex\\)" \ + "bra/bs #0x7,@er2,.+18" +gdb_test "x" "bra/bs\t#0x7,@0x9a(:8|),.\\+18 \\($hex\\)" \ + "bra/bs #0x7,@0x9a:8,.+18" +gdb_test "x" "bra/bs\t#0x7,@0x1234(:16|),.\\+18 \\($hex\\)" \ + "bra/bs #0x7,@0x1234:16,.+18" +gdb_test "x" "bra/bs\t#0x7,@0x12345678(:32|),.\\+18 \\($hex\\)" \ + "bra/bs #0x7,@0x12345678:32,.+18" +gdb_test "x" "bra/bs\t#0x7,@er2,.\\+4660 \\($hex\\)" \ + "bra/bs #0x7,@er2,.+4660" +gdb_test "x" "bra/bs\t#0x7,@0x12(:8|),.\\+4660 \\($hex\\)" \ + "bra/bs #0x7,@0x12:8,.+4660" +gdb_test "x" "bra/bs\t#0x7,@0x9abc(:16|),.\\+4660 \\($hex\\)" \ + "bra/bs #0x7,@0x9abc:16,.+4660" +gdb_test "x" "bra/bs\t#0x7,@0x12345678(:32|),.\\+4660 \\($hex\\)" \ + "bra/bs #0x7,@0x12345678:32,.+4660" +gdb_test "x" "bsr/bc\t#0x7,@er2,.\\+4660 \\($hex\\)" \ + "bsr/bc #0x7,@er2,.+4660" +gdb_test "x" "bsr/bc\t#0x7,@0x12(:8|),.\\+4660 \\($hex\\)" \ + "bsr/bc #0x7,@0x12:8,.+4660" +gdb_test "x" "bsr/bc\t#0x7,@0x9abc(:16|),.\\+4660 \\($hex\\)" \ + "bsr/bc #0x7,@0x9abc:16,.+4660" +gdb_test "x" "bsr/bc\t#0x7,@0x12345678(:32|),.\\+4660 \\($hex\\)" \ + "bsr/bc #0x7,@0x12345678:32,.+4660" +gdb_test "x" "bsr/bs\t#0x7,@er2,.\\+4660 \\($hex\\)" \ + "bsr/bs #0x7,@er2,.+4660" +gdb_test "x" "bsr/bs\t#0x7,@0x12(:8|),.\\+4660 \\($hex\\)" \ + "bsr/bs #0x7,@0x12:8,.+4660" +gdb_test "x" "bsr/bs\t#0x7,@0x9abc(:16|),.\\+4660 \\($hex\\)" \ + "bsr/bs #0x7,@0x9abc:16,.+4660" +gdb_test "x" "bsr/bs\t#0x7,@0x12345678(:32|),.\\+4660 \\($hex\\)" \ + "bsr/bs #0x7,@0x12345678:32,.+4660" +gdb_test "x" "bra\tr2l.b" \ + "bra r2l.b" +gdb_test "x" "bra\tr2.w" \ + "bra r2.w" +gdb_test "x" "bra\ter2(.l|)" \ + "bra er2.l" +gdb_test "x" "bsr\t.\\+18 \\($hex\\)" \ + "bsr .+18" +gdb_test "x" "bsr\t.\\+4660 \\($hex\\)" \ + "bsr .+4660" +gdb_test "x" "bsr\tr2l.b" \ + "bsr r2l.b" +gdb_test "x" "bsr\tr2.w" \ + "bsr r2.w" +gdb_test "x" "bsr\ter2(.l|)" \ + "bsr er2.l" +gdb_test "x" "jmp\t@er2" \ + "jmp @er2" +gdb_test "x" "jmp\t@0x123456(:24|)" \ + "jmp @0x123456:24" +gdb_test "x" "jmp\t@0x12345678(:32|)" \ + "jmp @0x12345678:32" +gdb_test "x" "jmp\t@@18 \\(0x12\\)" \ + "jmp @@18 (0x12)" +gdb_test "x" "jmp\t@@564 \\(0x234\\)" \ + "jmp @@564 (0x234)" +gdb_test "x" "jsr\t@er2" \ + "jsr @er2" +gdb_test "x" "jsr\t@0x123456(:24|)" \ + "jsr @0x123456:24" +gdb_test "x" "jsr\t@0x12345678(:32|)" \ + "jsr @0x12345678:32" +gdb_test "x" "jsr\t@@18 \\(0x12\\)" \ + "jsr @@18 (0x12)" +gdb_test "x" "jsr\t@@564 \\(0x234\\)" \ + "jsr @@564 (0x234)" +gdb_test "x" "rts\[ \t\]*" \ + "rts" +gdb_test "x" "rts/l\ter3" \ + "rts/l er3" +gdb_test "x" "rts/l\ter1-er2" \ + "rts/l er1-er2" +gdb_test "x" "rts/l\ter2-er4" \ + "rts/l er2-er4" +gdb_test "x" "rts/l\ter3-er6" \ + "rts/l er3-er6" +gdb_test "x" "trapa\t#0x3" \ + "trapa #0x3" +gdb_test "x" "rte\[ \t\]*" \ + "rte" +gdb_test "x" "rte/l\ter3" \ + "rte/l er3" +gdb_test "x" "rte/l\ter1-er2" \ + "rte/l er1-er2" +gdb_test "x" "rte/l\ter2-er4" \ + "rte/l er2-er4" +gdb_test "x" "rte/l\ter3-er6" \ + "rte/l er3-er6" +gdb_test "x" "ldc(.b|)\t#0x12(:8|),ccr" \ + "ldc.b #0x12:8,ccr" +gdb_test "x" "ldc(.b|)\tr3h,ccr" \ + "ldc.b r3h,ccr" +gdb_test "x" "ldc(.w|)\t@er3,ccr" \ + "ldc.w @er3,ccr" +gdb_test "x" "ldc(.w|)\t@er3\\+,ccr" \ + "ldc.w @er3+,ccr" +gdb_test "x" "ldc(.w|)\t@\\(0x1234(:16|),er3\\),ccr" \ + "ldc.w @(0x1234:16,er3),ccr" +gdb_test "x" "ldc(.w|)\t@\\(0x12345678(:32|),er3\\),ccr" \ + "ldc.w @(0x12345678:32,er3),ccr" +gdb_test "x" "ldc(.w|)\t@0x1234(:16|),ccr" \ + "ldc.w @0x1234:16,ccr" +gdb_test "x" "ldc(.w|)\t@0x12345678(:32|),ccr" \ + "ldc.w @0x12345678:32,ccr" +gdb_test "x" "ldc(.b|)\t#0x12(:8|),exr" \ + "ldc.b #0x12:8,exr" +gdb_test "x" "ldc(.b|)\tr3h,exr" \ + "ldc.b r3h,exr" +gdb_test "x" "ldc(.w|)\t@er3,exr" \ + "ldc.w @er3,exr" +gdb_test "x" "ldc(.w|)\t@er3\\+,exr" \ + "ldc.w @er3+,exr" +gdb_test "x" "ldc(.w|)\t@\\(0x1234(:16|),er3\\),exr" \ + "ldc.w @(0x1234:16,er3),exr" +gdb_test "x" "ldc(.w|)\t@\\(0x12345678(:32|),er3\\),exr" \ + "ldc.w @(0x12345678:32,er3),exr" +gdb_test "x" "ldc(.w|)\t@0x1234(:16|),exr" \ + "ldc.w @0x1234:16,exr" +gdb_test "x" "ldc(.w|)\t@0x12345678(:32|),exr" \ + "ldc.w @0x12345678:32,exr" +gdb_test "x" "stc(.b|)\tccr,r1h" \ + "stc.b ccr,r1h" +gdb_test "x" "stc(.w|)\tccr,@er1" \ + "stc.w ccr,@er1" +gdb_test "x" "stc(.w|)\tccr,@-er1" \ + "stc.w ccr,@-er1" +gdb_test "x" "stc(.w|)\tccr,@\\(0x1234(:16|),er1\\)" \ + "stc.w ccr,@(0x1234:16,er1)" +gdb_test "x" "stc(.w|)\tccr,@\\(0x12345678(:32|),er1\\)" \ + "stc.w ccr,@(0x12345678:32,er1)" +gdb_test "x" "stc(.w|)\tccr,@0x1234(:16|)" \ + "stc.w ccr,@0x1234:16" +gdb_test "x" "stc(.w|)\tccr,@0x12345678(:32|)" \ + "stc.w ccr,@0x12345678:32" +gdb_test "x" "stc(.b|)\texr,r1h" \ + "stc.b exr,r1h" +gdb_test "x" "stc(.w|)\texr,@er1" \ + "stc.w exr,@er1" +gdb_test "x" "stc(.w|)\texr,@-er1" \ + "stc.w exr,@-er1" +gdb_test "x" "stc(.w|)\texr,@\\(0x1234(:16|),er1\\)" \ + "stc.w exr,@(0x1234:16,er1)" +gdb_test "x" "stc(.w|)\texr,@\\(0x12345678(:32|),er1\\)" \ + "stc.w exr,@(0x12345678:32,er1)" +gdb_test "x" "stc(.w|)\texr,@0x1234(:16|)" \ + "stc.w exr,@0x1234:16" +gdb_test "x" "stc(.w|)\texr,@0x12345678(:32|)" \ + "stc.w exr,@0x12345678:32" +gdb_test "x" "orc(.b|)\t#0x12(:8|),ccr" \ + "orc.b #0x12:8,ccr" +gdb_test "x" "orc(.b|)\t#0x12(:8|),exr" \ + "orc.b #0x12:8,exr" +gdb_test "x" "xorc(.b|)\t#0x12(:8|),ccr" \ + "xorc.b #0x12:8,ccr" +gdb_test "x" "xorc(.b|)\t#0x12(:8|),exr" \ + "xorc.b #0x12:8,exr" +gdb_test "x" "andc(.b|)\t#0x12(:8|),ccr" \ + "andc.b #0x12:8,ccr" +gdb_test "x" "andc(.b|)\t#0x12(:8|),exr" \ + "andc.b #0x12:8,exr" +gdb_test "x" "sleep\[ \t\]*" \ + "sleep" +gdb_test "x" "nop\[ \t\]*" \ + "nop" diff --git a/gdb/testsuite/gdb.disasm/t13_otr.s b/gdb/testsuite/gdb.disasm/t13_otr.s new file mode 100644 index 0000000..6e0f887 --- /dev/null +++ b/gdb/testsuite/gdb.disasm/t13_otr.s @@ -0,0 +1,159 @@ +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;others +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + .h8300sx + .text + .org 0x12 +lab_12: + .org 0x1234 + .global _start +_start: + bra 0x12+.+2 ;4012 + brn 0x12+.+2 ;4112 + bhi 0x12+.+2 ;4212 + bls 0x12+.+2 ;4312 + bcc 0x12+.+2 ;4412 + bcs 0x12+.+2 ;4512 + bne 0x12+.+2 ;4612 + beq 0x12+.+2 ;4712 + bvc 0x12+.+2 ;4812 + bvs 0x12+.+2 ;4912 + bpl 0x12+.+2 ;4a12 + bmi 0x12+.+2 ;4b12 + bge 0x12+.+2 ;4c12 + blt 0x12+.+2 ;4d12 + bgt 0x12+.+2 ;4e12 + ble 0x12+.+2 ;4f12 + + bra 0x1234+.+4 ;58001234 + brn 0x1234+.+4 ;58101234 + bhi 0x1234+.+4 ;58201234 + bls 0x1234+.+4 ;58301234 + bcc 0x1234+.+4 ;58401234 + bcs 0x1234+.+4 ;58501234 + bne 0x1234+.+4 ;58601234 + beq 0x1234+.+4 ;58701234 + bvc 0x1234+.+4 ;58801234 + bvs 0x1234+.+4 ;58901234 + bpl 0x1234+.+4 ;58a01234 + bmi 0x1234+.+4 ;58b01234 + bge 0x1234+.+4 ;58c01234 + blt 0x1234+.+4 ;58d01234 + bgt 0x1234+.+4 ;58e01234 + ble 0x1234+.+4 ;58f01234 + + bra/s 0x12+.+2 ;4013 + nop ;0000 + + bra/bc #0x7,@er2,0x12+.+4 ;7c204712 + bra/bc #0x7,@0xffffff9a:8,0x12+.+4 ;7e9a4712 + bra/bc #0x7,@0x1234:16,0x12+.+6 ;6a1012344712 + bra/bc #0x7,@0x12345678:32,0x12+.+8 ;6a30123456784712 + bra/bc #0x7,@er2,0x1234+.+6 ;7c2058701234 + bra/bc #0x7,@0xffffff12:8,0x1234+.+6 ;7e1258701234 + bra/bc #0x7,@0xffff9abc:16,0x1234+.+8 ;6a109abc58701234 + bra/bc #0x7,@0x12345678:32,0x1234+.+0xa ;6a301234567858701234 + + bra/bs #0x7,@er2,0x12+.+4 ;7c204f12 + bra/bs #0x7,@0xffffff9a:8,0x12+.+4 ;7e9a4f12 + bra/bs #0x7,@0x1234:16,0x12+.+6 ;6a1012344f12 + bra/bs #0x7,@0x12345678:32,0x12+.+8 ;6a30123456784f12 + bra/bs #0x7,@er2,0x1234+.+6 ;7c2058f01234 + bra/bs #0x7,@0xffffff12:8,0x1234+.+6 ;7e1258f01234 + bra/bs #0x7,@0xffff9abc:16,0x1234+.+8 ;6a109abc58f01234 + bra/bs #0x7,@0x12345678:32,0x1234+.+0xa ;6a301234567858f01234 + + bsr/bc #0x7,@er2,0x1234+.+6 ;7c205c701234 + bsr/bc #0x7,@0xffffff12:8,0x1234+.+6 ;7e125c701234 + bsr/bc #0x7,@0xffff9abc:16,0x1234+.+8 ;6a109abc5c701234 + bsr/bc #0x7,@0x12345678:32,0x1234+.+0xa ;6a30123456785c701234 + + bsr/bs #0x7,@er2,0x1234+.+6 ;7c205cf01234 + bsr/bs #0x7,@0xffffff12:8,0x1234+.+6 ;7e125cf01234 + bsr/bs #0x7,@0xffff9abc:16,0x1234+.+8 ;6a109abc5cf01234 + bsr/bs #0x7,@0x12345678:32,0x1234+.+0xa ;6a30123456785cf01234 + + bra r2l.b ;5925 + bra r2.w ;5926 + bra er2.l ;5927 + + bsr 0x12+.+2 ;5512 + bsr 0x1234+.+4 ;5c001234 + bsr r2l.b ;5d25 + bsr r2.w ;5d26 + bsr er2.l ;5d27 + + jmp @er2 ;5920 + jmp @0x123456:24 ;5a123456 + jmp @0x12345678:32 ;590812345678 + jmp @@0x12 ;5b12 + jmp @@0x234 ;598d + + jsr @er2 ;5d20 + jsr @0x123456:24 ;5e123456 + jsr @0x12345678:32 ;5d0812345678 + jsr @@0x12 ;5f12 + jsr @@0x234 ;5d8d + + rts ;5470 + rts/l er3 ;5403 + rts/l er1-er2 ;5412 + rts/l er2-er4 ;5424 + rts/l er3-er6 ;5436 + + trapa #0x3 ;5730 + + rte ;5670 + rte/l er3 ;5603 + rte/l er1-er2 ;5612 + rte/l er2-er4 ;5624 + rte/l er3-er6 ;5636 + + ldc.b #0x12:8,ccr ;0712 + ldc.b r3h,ccr ;0303 + ldc.w @er3,ccr ;01406930 + ldc.w @er3+,ccr ;01406d30 + ldc.w @(0x1234:16,er3),ccr ;01406f301234 + ldc.w @(0x12345678:32,er3),ccr ;014078306b2012345678 + ldc.w @0x1234:16,ccr ;01406b001234 + ldc.w @0x12345678:32,ccr ;01406b2012345678 + + ldc.b #0x12:8,exr ;01410712 + ldc.b r3h,exr ;0313 + ldc.w @er3,exr ;01416930 + ldc.w @er3+,exr ;01416d30 + ldc.w @(0x1234:16,er3),exr ;01416f301234 + ldc.w @(0x12345678:32,er3),exr ;014178306b2012345678 + ldc.w @0x1234:16,exr ;01416b001234 + ldc.w @0x12345678:32,exr ;01416b2012345678 + + stc.b ccr,r1h ;0201 + stc.w ccr,@er1 ;01406990 + stc.w ccr,@-er1 ;01406d90 + stc.w ccr,@(0x1234:16,er1) ;01406f901234 + stc.w ccr,@(0x12345678:32,er1) ;014078106ba012345678 + stc.w ccr,@0x1234:16 ;01406b801234 + stc.w ccr,@0x12345678:32 ;01406ba012345678 + + stc.b exr,r1h ;0211 + stc.w exr,@er1 ;01416990 + stc.w exr,@-er1 ;01416d90 + stc.w exr,@(0x1234:16,er1) ;01416f901234 + stc.w exr,@(0x12345678:32,er1) ;014178106ba012345678 + stc.w exr,@0x1234:16 ;01416b801234 + stc.w exr,@0x12345678:32 ;01416ba012345678 + + orc.b #0x12:8,ccr ;0412 + orc.b #0x12:8,exr ;01410412 + + xorc.b #0x12:8,ccr ;0512 + xorc.b #0x12:8,exr ;01410512 + + andc.b #0x12:8,ccr ;0612 + andc.b #0x12:8,exr ;01410612 + + sleep ;0180 + + nop ;0000 + + .end diff --git a/gdb/testsuite/gdb.gdb/observer.exp b/gdb/testsuite/gdb.gdb/observer.exp new file mode 100644 index 0000000..80ab29a --- /dev/null +++ b/gdb/testsuite/gdb.gdb/observer.exp @@ -0,0 +1,265 @@ +# Copyright 2003 +# Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# Please email any bugs, comments, and/or additions to this file to: +# bug-gdb@prep.ai.mit.edu + +# This file was written by Joel Brobecker (brobecker@gnat.com), derived +# from xfullpath.exp. + +if $tracelevel then { + strace $tracelevel +} + +set prms_id 0 +set bug_id 0 + +# are we on a target board +if [is_remote target] { + return +} + +proc setup_test { executable } { + global gdb_prompt + global timeout + + # load yourself into the debugger + # This can take a relatively long time, particularly for testing where + # the executable is being accessed over a network, or where gdb does not + # support partial symbols for a particular target and has to load the + # entire symbol table. Set the timeout to 10 minutes, which should be + # adequate for most environments (it *has* timed out with 5 min on a + # SPARCstation SLC under moderate load, so this isn't unreasonable). + # After gdb is started, set the timeout to 30 seconds for the duration + # of this test, and then back to the original value. + + set oldtimeout $timeout + set timeout 600 + verbose "Timeout is now $timeout seconds" 2 + if {[gdb_load $executable] <0} then { + set timeout $oldtimeout + verbose "Timeout is now $timeout seconds" 2 + return -1 + } + set timeout $oldtimeout + verbose "Timeout is now $timeout seconds" 2 + + # Set a breakpoint at main + gdb_test "break captured_main" \ + "Breakpoint.*at.* file.*, line.*" \ + "breakpoint in captured_main" + + # run yourself + # It may take a very long time for the inferior gdb to start (lynx), + # so we bump it back up for the duration of this command. + set timeout 600 + + set description "run until breakpoint at captured_main" + send_gdb "run -nw\n" + gdb_expect { + -re "Starting program.*Breakpoint \[0-9\]+,.*captured_main .data.* at .*main.c:.*$gdb_prompt $" { + pass "$description" + } + -re "Starting program.*Breakpoint \[0-9\]+,.*captured_main .data.*$gdb_prompt $" { + xfail "$description (line numbers scrambled?)" + } + -re "vfork: No more processes.*$gdb_prompt $" { + fail "$description (out of virtual memory)" + set timeout $oldtimeout + verbose "Timeout is now $timeout seconds" 2 + return -1 + } + -re ".*$gdb_prompt $" { + fail "$description" + set timeout $oldtimeout + verbose "Timeout is now $timeout seconds" 2 + return -1 + } + timeout { + fail "$description (timeout)" + } + } + + set timeout $oldtimeout + verbose "Timeout is now $timeout seconds" 2 + + return 0 +} + +proc attach_first_observer { } { + gdb_test "set \$first_obs = observer_attach_normal_stop (&observer_test_first_notification_function)" \ + "" "attach first observer" +} + +proc attach_second_observer { } { + gdb_test "set \$second_obs = observer_attach_normal_stop (&observer_test_second_notification_function)" \ + "" "attach second observer" +} + +proc attach_third_observer { } { + gdb_test "set \$third_obs = observer_attach_normal_stop (&observer_test_third_notification_function)" \ + "" "attach third observer" +} + +proc detach_first_observer { } { + gdb_test "call observer_detach_normal_stop (\$first_obs)" \ + "" "detach first observer" +} + +proc detach_second_observer { } { + gdb_test "call observer_detach_normal_stop (\$second_obs)" \ + "" "detach second observer" +} + +proc detach_third_observer { } { + gdb_test "call observer_detach_normal_stop (\$third_obs)" \ + "" "detach third observer" +} + +proc check_counters { first second third message } { + gdb_test "print observer_test_first_observer" \ + ".\[0-9\]+ =.*$first" \ + "check first observer counter value ($message)" + gdb_test "print observer_test_second_observer" \ + ".\[0-9\]+ =.*$second" \ + "check second observer counter value ($message)" + gdb_test "print observer_test_third_observer" \ + ".\[0-9\]+ =.*$third" \ + "check third observer counter value ($message)" +} + +proc reset_counters { } { + gdb_test "set variable observer_test_first_observer = 0" "" \ + "reset first observer counter" + gdb_test "set variable observer_test_second_observer = 0" "" \ + "reset second observer counter" + gdb_test "set variable observer_test_third_observer = 0" "" \ + "reset third observer counter" +} + +proc test_normal_stop_notifications { first second third message } { + reset_counters + gdb_test "call observer_notify_normal_stop ()" "" \ + "sending notification ($message)" + check_counters $first $second $third $message +} + +proc test_observer_normal_stop { executable } { + + set setup_result [setup_test $executable] + if {$setup_result <0} then { + return -1 + } + + # First, try sending a notification without any observer attached. + test_normal_stop_notifications 0 0 0 "no observer" + + # Now, attach one observer, and send a notification. + attach_second_observer + test_normal_stop_notifications 0 1 0 "one observer" + + # Remove the observer, and send a notification. + detach_second_observer + test_normal_stop_notifications 0 0 0 "no observer" + + # With a new observer. + attach_first_observer + test_normal_stop_notifications 1 0 0 "a new observer" + + # With 2 observers. + attach_second_observer + test_normal_stop_notifications 1 1 0 "2 observers" + + # With 3 observers. + attach_third_observer + test_normal_stop_notifications 1 1 1 "3 observers" + + # Remove middle observer. + detach_second_observer + test_normal_stop_notifications 1 0 1 "middle observer removed" + + # Remove first observer. + detach_first_observer + test_normal_stop_notifications 0 0 1 "first observer removed" + + # Remove last observer. + detach_third_observer + test_normal_stop_notifications 0 0 0 "last observer removed" + + # Go back to 3 observers, and remove them in a different order... + attach_first_observer + attach_second_observer + attach_third_observer + test_normal_stop_notifications 1 1 1 "3 observers again" + + # Remove the third observer. + detach_third_observer + test_normal_stop_notifications 1 1 0 "third observer removed" + + # Remove the second observer. + detach_second_observer + test_normal_stop_notifications 1 0 0 "second observer removed" + + # Remove the first observer, no more observers. + detach_first_observer + test_normal_stop_notifications 0 0 0 "last observer removed" + + return 0 +} + +# Find a pathname to a file that we would execute if the shell was asked +# to run $arg using the current PATH. + +proc find_gdb { arg } { + + # If the arg directly specifies an existing executable file, then + # simply use it. + + if [file executable $arg] then { + return $arg + } + + set result [which $arg] + if [string match "/" [ string range $result 0 0 ]] then { + return $result + } + + # If everything fails, just return the unqualified pathname as default + # and hope for best. + + return $arg +} + +# Run the test with self. +# Copy the file executable file in case this OS doesn't like to edit its own +# text space. + +set GDB_FULLPATH [find_gdb $GDB] + +# Remove any old copy lying around. +remote_file host delete x$tool + +gdb_start +set file [remote_download host $GDB_FULLPATH x$tool] +set result [test_observer_normal_stop $file]; +gdb_exit; +catch "remote_file host delete $file"; + +if {$result <0} then { + warning "Couldn't test self" + return -1 +} diff --git a/gdb/testsuite/gdb.mi/gdb792.cc b/gdb/testsuite/gdb.mi/gdb792.cc new file mode 100644 index 0000000..a698a12 --- /dev/null +++ b/gdb/testsuite/gdb.mi/gdb792.cc @@ -0,0 +1,59 @@ +#include +#include + +class Q +{ + int v; + protected: + int qx; + int qy; + int w; +}; + +class B +{ + int k; + public: + int bx; + int by; +}; + +class A +{ + int u; + + public: + A() + { + }; + int x; + char buffer[10]; + + protected: + int y; + B b; + + private: + float z; +}; + +class C : public A +{ + public: + C() + { + }; + int zzzz; + private: + int ssss; +}; + +int main() +{ + A a; + C c; + Q q; + strcpy( a.buffer, "test" ); + printf ( "%.10s\n", a.buffer ); + return 0; +} diff --git a/gdb/testsuite/gdb.mi/gdb792.exp b/gdb/testsuite/gdb.mi/gdb792.exp new file mode 100644 index 0000000..8196464 --- /dev/null +++ b/gdb/testsuite/gdb.mi/gdb792.exp @@ -0,0 +1,92 @@ +# Copyright 2002 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# Please email any bugs, comments, and/or additions to this file to: +# bug-gdb@prep.ai.mit.edu + +# +# test gdb/792 +# + +if { [skip_cplus_tests] } { continue } + +load_lib mi-support.exp +set MIFLAGS "-i=mi" + +gdb_exit +if [mi_gdb_start] { + continue +} + +set testfile gdb792 +set srcfile "$testfile.cc" +set binfile $objdir/$subdir/$testfile + +if [get_compiler_info ${binfile} "c++"] { + return -1; +} + +if {[gdb_compile $srcdir/$subdir/$srcfile $binfile executable {debug c++}] != ""} { + gdb_suppress_entire_file "Testcase compile failed, so all test in this file will automatically fail." +} + +# Test that children of classes are properly reported + +# Run to main +mi_run_to_main + +mi_gdb_test "-var-create - * a" \ + "(&\".*\"\r\n)*\\^done,name=\"var1\",numchild=\"3\",type=\"A\"" \ + "create var for class A" + +mi_gdb_test "-var-list-children var1" \ + "(&\".*\"\r\n)*\\^done,numchild=\"3\",children=\\\[child=\{name=\"var1\.public\",exp=\"public\",numchild=\"2\"\},child=\{name=\"var1\.private\",exp=\"private\",numchild=\"2\"\},child=\{name=\"var1\.protected\",exp=\"protected\",numchild=\"2\"\}\\\]" \ + "list children of class A" + +mi_gdb_test "-var-list-children var1.public" \ + "(&\".*\"\r\n)*\\^done,numchild=\"2\",children=\\\[child=\{name=\"var1\.public\.x\",exp=\"x\",numchild=\"0\",type=\"int\"\},child=\{name=\"var1\.public\.buffer\",exp=\"buffer\",numchild=\"10\",type=\"char \\\[10\\\]\"\}\\\]" \ + "list children of A.public" + +mi_gdb_test "-var-list-children var1.private" \ + "(&\".*\"\r\n)*\\^done,numchild=\"2\",children=\\\[child=\{name=\"var1\.private\.u\",exp=\"u\",numchild=\"0\",type=\"int\"\},child=\{name=\"var1\.private\.z\",exp=\"z\",numchild=\"0\",type=\"float\"\}\\\]" \ + "list children of A.private" + +mi_gdb_test "-var-list-children var1.protected" \ + "(&\".*\"\r\n)*\\^done,numchild=\"2\",children=\\\[child=\{name=\"var1\.protected\.y\",exp=\"y\",numchild=\"0\",type=\"int\"\},child=\{name=\"var1\.protected\.b\",exp=\"b\",numchild=\"2\",type=\"B\"\}\\\]" \ + "list children of A.protected" + +mi_gdb_test "-var-list-children var1.protected.b" \ + "(&\".*\"\r\n)*\\^done,numchild=\"2\",children=\\\[child=\{name=\"var1\.protected\.b\.public\",exp=\"public\",numchild=\"2\"\},child=\{name=\"var1\.protected\.b\.private\",exp=\"private\",numchild=\"1\"\}\\\]" \ + "list children of A.protected.b" + +mi_gdb_test "-var-list-children var1.protected.b.public" \ + "(&\".*\"\r\n)*\\^done,numchild=\"2\",children=\\\[child=\{name=\"var1\.protected\.b\.public\.bx\",exp=\"bx\",numchild=\"0\",type=\"int\"\},child=\{name=\"var1\.protected\.b\.public\.by\",exp=\"by\",numchild=\"0\",type=\"int\"\}\\\]" \ + "list children of A.protected.b.public" + +mi_gdb_test "-var-list-children var1.protected.b.private" \ + "(&\".*\"\r\n)*\\^done,numchild=\"1\",children=\\\[child=\{name=\"var1\.protected\.b\.private\.k\",exp=\"k\",numchild=\"0\",type=\"int\"\}\\\]" \ + "list children of A.protected.b.private" + +mi_gdb_test "-var-create - * c" \ + "(&\".*\"\r\n)*\\^done,name=\"var2\",numchild=\"3\",type=\"C\"" \ + "create var for class C which has baseclass A" + +mi_gdb_test "-var-list-children var2" \ + "(&\".*\"\r\n)*\\^done,numchild=\"3\",children=\\\[child=\{name=\"var2\.A\",exp=\"A\",numchild=\"3\",type=\"A\"\},child=\{name=\"var2\.public\",exp=\"public\",numchild=\"1\"\},child=\{name=\"var2\.private\",exp=\"private\",numchild=\"1\"\}\\\]" \ + "list children of class C" + +mi_gdb_exit +return 0 diff --git a/gdb/testsuite/gdb.mi/mi-cli.exp b/gdb/testsuite/gdb.mi/mi-cli.exp new file mode 100644 index 0000000..62501e0 --- /dev/null +++ b/gdb/testsuite/gdb.mi/mi-cli.exp @@ -0,0 +1,208 @@ +# Copyright 2002, 2003 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# Please email any bugs, comments, and/or additions to this file to: +# bug-gdb@prep.ai.mit.edu + +# This file tests that GDB's console can be accessed via the MI. +# Specifically, we are testing the "interpreter-exec" command and that +# the commands that are executed via this command are properly executed. +# Console commands executed via MI should use MI output wrappers, MI event +# handlers, etc. + +load_lib mi-support.exp +set MIFLAGS "-i=mi" + +gdb_exit +if [mi_gdb_start] { + continue +} + +set testfile "basics" +set srcfile ${testfile}.c +set binfile ${objdir}/${subdir}/${testfile} +if { [gdb_compile "${srcdir}/${subdir}/${srcfile}" "${binfile}" executable {debug additional_flags=-DFAKEARGV}] != "" } { + gdb_suppress_entire_file "Testcase compile failed, so all tests in this file will automatically fail." +} + +mi_gdb_reinitialize_dir $srcdir/$subdir + +mi_gdb_test "-interpreter-exec" \ + {\^error,msg="mi_cmd_interpreter_exec: Usage: -interpreter-exec interp command"} \ + "-interpreter-exec with no arguments" + +mi_gdb_test "-interpreter-exec console" \ + {\^error,msg="mi_cmd_interpreter_exec: Usage: -interpreter-exec interp command"} \ + "-interpreter-exec with one argument" + +mi_gdb_test "-interpreter-exec bogus command" \ + {\^error,msg="mi_cmd_interpreter_exec: could not find interpreter \\\"bogus\\\""} \ + "-interpreter-exec with bogus interpreter" + +set msg {Undefined command: \\\"bogus\\\"\. Try \\\"help\\\"\.} +mi_gdb_test "-interpreter-exec console bogus" \ + "&\\\"$msg\\\\n\\\".*\\^error,msg=\\\"$msg\\\".*" \ + "-interpreter-exec console bogus" + +# NOTE: cagney/2003-02-03: Not yet. +# mi_gdb_test "-interpreter-exec console \"file $binfile\"" \ +# {(=.*)+\^done} \ +# "-interpreter-exec console \"file \$binfile\"" +mi_gdb_test "-interpreter-exec console \"file $binfile\"" \ + {\^done} \ + "-interpreter-exec console \"file \$binfile\"" + +mi_run_to_main + +mi_gdb_test "-interpreter-exec console \"set args foobar\"" \ + {\^done} \ + "-interpreter-exec console \"set args foobar\"" + +mi_gdb_test "-interpreter-exec console \"show args\"" \ + {\~"Argument list to give program being debugged when it is started is \\\"foobar\\\"\.\\n".*\^done} \ + "-interpreter-exec console \"show args\"" + +# NOTE: cagney/2003-02-03: Not yet. +# mi_gdb_test "-interpreter-exec console \"break callee4\"" \ +# {(&.*)*.*~"Breakpoint 2 at.*\\n".*=breakpoint-create,number="2".*\^done} \ +# "-interpreter-exec console \"break callee4\"" +mi_gdb_test "-interpreter-exec console \"break callee4\"" \ + {(&.*)*.*~"Breakpoint 2 at.*\\n".*\^done} \ + "-interpreter-exec console \"break callee4\"" + +mi_gdb_test "-interpreter-exec console \"info break\"" \ + {\~"Num[ \t]*Type[ \t]*Disp[ \t]*Enb[ \t]*Address[ \t]*What\\n".*~"2[ \t]*breakpoint[ \t]*keep[ \t]*y[ \t]*0x[0-9A-Fa-f]+[ \t]*in callee4 at .*basics.c:[0-9]+\\n".*\^done} \ + "-interpreter-exec console \"info break\"" + +mi_gdb_test "-interpreter-exec console \"set listsize 1\"" \ + {\^done} \ + "-interpreter-exec console \"set listsize 1\"" + +mi_gdb_test "-interpreter-exec console \"list\"" \ + {.*\~"32[ \t(\\t)]*callee1.*\\n".*\^done} \ + "-interpreter-exec console \"list\"" + +# # NOTE: cagney/2003-02-03: Not yet. +# mi_gdb_test "-exec-continue" \ +# {.*\*stopped,reason="breakpoint-hit",.*func="callee4".*file=".*basics.c",line="8"\}} \ +# "-interpreter-exec console \"continue to callee4\"" +send_gdb "999-exec-continue\n" +gdb_expect { + -re "999\\^running\[\r\n\]+$mi_gdb_prompt.*999\\*stopped,reason=.breakpoint-hit.*$mi_gdb_prompt$" { + pass "continue to callee4" + } + timeout { + fail "continue to callee4 (timeout)" + } +} + +# NOTE: cagney/2003-02-03: Not yet. +# mi_gdb_test "100-interpreter-exec console \"delete 2\"" \ +# {.*=breakpoint-delete,number=\"2\".*\^done} \ +# "-interpreter-exec console \"delete 2\"" +mi_gdb_test "100-interpreter-exec console \"delete 2\"" \ + {100\^done} \ + "-interpreter-exec console \"delete 2\"" + +# NOTE: cagney/2003-02-03: Not yet. +# mi_gdb_test "200-interpreter-exec console \"up\"" \ +# {.*=selected-frame-level-changed,level="1".*\^done} \ +# "-interpreter-exec console \"up\"" +mi_gdb_test "200-interpreter-exec console \"up\"" \ + {200\^done} \ + "-interpreter-exec console \"up\"" + +# NOTE: cagney/2003-02-03: Not yet. +# mi_gdb_test "300-interpreter-exec console \"down\"" \ +# {.*=selected-frame-level-changed,level="0".*\^done} \ +# "-interpreter-exec console \"down\"" +mi_gdb_test "300-interpreter-exec console \"down\"" \ + {300\^done} \ + "-interpreter-exec console \"down\"" + +# NOTE: cagney/2003-02-03: Not yet. +# mi_gdb_test "-interpreter-exec console \"frame 2\"" \ +# {.*=selected-frame-level-changed,level="2".*\^done} \ +# "-interpreter-exec console \"frame 2\"" +mi_gdb_test "400-interpreter-exec console \"frame 2\"" \ + {400\^done} \ + "-interpreter-exec console \"frame 2\"" + +# NOTE: cagney/2003-02-03: Not yet. +# mi_gdb_test "-stack-select-frame 0" \ +# {.*=selected-frame-level-changed,level="0".*\^done} \ +# "-stack-select-frame 0" +mi_gdb_test "500-stack-select-frame 0" \ + {500\^done} \ + "-stack-select-frame 0" + +# NOTE: cagney/2003-02-03: Not yet. +# mi_gdb_test "-break-insert -t basics.c:35" \ +# {.*=breakpoint-create,number="3".*\^done} \ +# "-break-insert -t basics.c:35" +mi_gdb_test "600-break-insert -t basics.c:35" \ + {600\^done,bkpt=.number="3",type="breakpoint".*\}} \ + "-break-insert -t basics.c:35" + +# mi_gdb_test "-exec-continue" \ +# {.*\*stopped.*,file=".*basics.c",line="35"\}} \ +# "-exec-continue to line 35" +send_gdb "700-exec-continue\n" +gdb_expect { + -re "700\\^running\[\r\n\]+$mi_gdb_prompt.*\\*stopped.*,file=.*basics.c.,line=.35.*$mi_gdb_prompt$" { + pass "-exec-continue to line 35" + } + timeout { + fail "-exec-continue to line 35" + } +} + +# NOTE: cagney/2003-02-03: Not yet. +# mi_gdb_test "-exec-next" \ +# {.*\*stopped,reason="end-stepping-range",.*,file=".*basics.c",line="37"\}} \ +# "-exec-next to line 37" +send_gdb "800-exec-next\n" +gdb_expect { + -re "800\\^running\[\r\n\]+$mi_gdb_prompt.*\\*stopped,reason=.end-stepping-range.*,file=.*basics.c.,line=.37.*$mi_gdb_prompt$" { + pass "-exec-next to line 37" + } + timeout { + fail "-exec-next to line 37" + } +} + +mi_gdb_test "-interpreter-exec console \"list\"" \ + {\~"37[ \t(\\t)]*return 0;\\n".*\^done} \ + "-interpreter-exec console \"list\" at basics.c:37" + +mi_gdb_test "-interpreter-exec console \"help set args\"" \ + {\~"Set argument list to give program being debugged when it is started\.\\nFollow this command with any number of args, to be passed to the program\.".*\^done} \ + "-interpreter-exec console \"help set args\"" + +# NOTE: cagney/2003-02-03: Not yet. +# mi_gdb_test "-interpreter-exec console \"set \$pc=0x0\"" \ +# {.*=target-changed.*\^done} \ +# "-interpreter-exec console \"set \$pc=0x0\"" +mi_gdb_test "888-interpreter-exec console \"set \$pc=0x0\"" \ + {888\^done} \ + "-interpreter-exec console \"set \$pc=0x0\"" + +#mi_gdb_test "-interpreter-exec console \"\"" \ + {} \ + "-interpreter-exec console \"\"" + +mi_gdb_exit +return 0 diff --git a/gdb/testsuite/gdb.mi/mi-file.exp b/gdb/testsuite/gdb.mi/mi-file.exp new file mode 100644 index 0000000..2ffdcbf --- /dev/null +++ b/gdb/testsuite/gdb.mi/mi-file.exp @@ -0,0 +1,65 @@ +# Copyright 1999 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# Please email any bugs, comments, and/or additions to this file to: +# bug-gdb@prep.ai.mit.edu + +# +# Test essential Machine interface (MI) operations +# +# Verify that, using the MI, we can run a simple program and perform basic +# debugging activities like: insert breakpoints, run the program, +# step, next, continue until it ends and, last but not least, quit. +# +# The goal is not to test gdb functionality, which is done by other tests, +# but to verify the correct output response to MI operations. +# + +load_lib mi-support.exp +set MIFLAGS "-i=mi" + +gdb_exit +if [mi_gdb_start] { + continue +} + +set testfile "basics" +set srcfile ${testfile}.c +set binfile ${objdir}/${subdir}/${testfile} +if { [gdb_compile "${srcdir}/${subdir}/${srcfile}" "${binfile}" executable {debug additional_flags=-DFAKEARGV}] != "" } { + gdb_suppress_entire_file "Testcase compile failed, so all tests in this file will automatically fail." +} + +mi_delete_breakpoints +mi_gdb_reinitialize_dir $srcdir/$subdir +mi_gdb_load ${binfile} + +proc test_tbreak_creation_and_listing {} { + global srcfile + global srcdir + global subdir + set srcfilepath [string_to_regexp ${srcdir}/${subdir}/${srcfile}] + + # get the path and absolute path to the current executable + mi_gdb_test "111-file-list-exec-source-file" \ + "111\\\^done,line=\"23\",file=\"${srcfilepath}\",fullname=\"/.*/${srcfile}\"" \ + "request path info of current source file (${srcfile})" +} + +test_tbreak_creation_and_listing + +mi_gdb_exit +return 0 diff --git a/gdb/testsuite/gdb.mi/mi-syn-frame.c b/gdb/testsuite/gdb.mi/mi-syn-frame.c new file mode 100644 index 0000000..580b534 --- /dev/null +++ b/gdb/testsuite/gdb.mi/mi-syn-frame.c @@ -0,0 +1,66 @@ +#include +#include +#include + +void foo (void); +void bar (void); + +void subroutine (int); +void handler (int); +void have_a_very_merry_interrupt (void); + +main () +{ + puts ("Starting up"); + + foo (); /* Put a breakpoint on foo() and call it to see a dummy frame */ + + + have_a_very_merry_interrupt (); + + puts ("Shutting down"); +} + +void +foo (void) +{ + puts ("hi in foo"); +} + +void +bar (void) +{ + char *nuller = 0; + + puts ("hi in bar"); + + *nuller = 'a'; /* try to cause a segfault */ +} + +void +handler (int sig) +{ + subroutine (sig); +} + +/* The first statement in subroutine () is a place for a breakpoint. + Without it, the breakpoint is put on the while comparison and will + be hit at each iteration. */ + +void +subroutine (int in) +{ + int count = in; + while (count < 100) + count++; +} + +void +have_a_very_merry_interrupt (void) +{ + puts ("Waiting to get a signal"); + signal (SIGALRM, handler); + alarm (1); + sleep (2); /* We'll receive that signal while sleeping */ +} + diff --git a/gdb/testsuite/gdb.mi/mi-syn-frame.exp b/gdb/testsuite/gdb.mi/mi-syn-frame.exp new file mode 100644 index 0000000..44ce845 --- /dev/null +++ b/gdb/testsuite/gdb.mi/mi-syn-frame.exp @@ -0,0 +1,111 @@ +# Copyright 2002, 2003 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# Please email any bugs, comments, and/or additions to this file to: +# bug-gdb@prep.ai.mit.edu + +# Test MI output with synthetic frames on the stack (call dummies, +# signal handlers). + +if [target_info exists gdb,nosignals] { + verbose "Skipping mi-syn-frame.exp because of nosignals." + continue +} + +load_lib mi-support.exp +set MIFLAGS "-i=mi" + +set testfile "mi-syn-frame" +set srcfile ${testfile}.c +set binfile ${objdir}/${subdir}/${testfile} +if { [gdb_compile "${srcdir}/${subdir}/${srcfile}" "${binfile}" executable {debug additional_flags=-DFAKEARGV}] != "" } { + gdb_suppress_entire_file "Testcase compile failed, so all tests in this file will automatically fail." +} + +set my_mi_gdb_prompt "\\(gdb\\)\[ \]*\[\r\n\]*" + +mi_gdb_exit +mi_gdb_start +mi_delete_breakpoints +mi_gdb_reinitialize_dir $srcdir/$subdir +mi_gdb_load ${binfile} +mi_run_to_main + +mi_gdb_test "400-break-insert foo" "400\\^done,bkpt=\{number=\"2\",type=\"breakpoint\",disp=\"keep\",enabled=\"y\",addr=\"$hex\",func=\"foo\",file=\".*mi-syn-frame.c\",line=\"$decimal\",times=\"0\"\}" + + +# +# Call foo() by hand, where we'll hit a breakpoint. +# + +mi_gdb_test "401-data-evaluate-expression foo()" "\\&\"The program being debugged stopped while in a function called from GDB.\\\\n\"\[\r\n\]+\\&\"When the function \\(foo\\) is done executing, GDB will silently\\\\n\"\[\r\n\]+\\&\"stop \\(instead of continuing to evaluate the expression containing\\\\n\"\[\r\n\]+\\&\"the function call\\).\\\\n\"\[\r\n\]+401\\^error,msg=\"The program being debugged stopped while in a function called from GDB.*\"" "call inferior's function with a breakpoint set in it" + +mi_gdb_test "402-stack-list-frames" "402\\^done,reason=\"breakpoint-hit\",bkptno=\"2\",thread-id=\"$decimal\",frame=\{addr=\"$hex\",func=\"foo\",args=\\\[\\\],file=\".*mi-syn-frame.c\",line=\"$decimal\"\},stack=\\\[frame=\{level=\"0\",addr=\"$hex\",func=\"foo\",file=\".*mi-syn-frame.c\",line=\"$decimal\"\},frame=\{level=\"1\",addr=\"$hex\",func=\"\"\},frame=\{level=\"2\",addr=\"$hex\",func=\"main\",file=\".*mi-syn-frame.c\",line=\"$decimal\"\}.*\\\]" "backtrace from inferior function stopped at bp, showing gdb dummy frame" + +# +# Continue back to main() +# + +send_gdb "403-exec-continue\n" +gdb_expect { + -re "403\\^running\[\r\n\]+${my_mi_gdb_prompt}hi in foo\[\r\n\]+403\\\*stopped\[\r\n\]+${my_mi_gdb_prompt}$" { + pass "403-exec-continue" + } + timeout { + fail "403-exec-continue" + } +} + +mi_gdb_test "404-stack-list-frames 0 0" "404\\^done,stack=\\\[frame=\{level=\"0\",addr=\"$hex\",func=\"main\",file=\".*mi-syn-frame.c\",line=\"$decimal\"\}.*\\\]" + + +# +# Call have_a_very_merry_interrupt() which will eventually raise a signal +# that's caught by handler() which calls subroutine(). + +mi_gdb_test "405-break-insert subroutine" "405\\^done,bkpt=\{number=\"3\",type=\"breakpoint\",disp=\"keep\",enabled=\"y\",addr=\"$hex\",func=\"subroutine\",file=\".*mi-syn-frame.c\",line=\"$decimal\",times=\"0\"\}" + +mi_gdb_test "406-data-evaluate-expression have_a_very_merry_interrupt()" "Waiting to get a signal\[\r\n\]+\\&\"The program being debugged stopped while in a function called from GDB.\\\\n\"\[\r\n\]+\\&\"When the function \\(have_a_very_merry_interrupt\\) is done executing, GDB will silently\\\\n\"\[\r\n\]+\\&\"stop \\(instead of continuing to evaluate the expression containing\\\\n\"\[\r\n\]+\\&\"the function call\\).\\\\n\"\[\r\n\]+406\\^error,msg=\"The program being debugged stopped while in a function called from GDB.\\\\nWhen the function \\(have_a_very_merry_interrupt\\) is done executing, GDB will silently\\\\nstop \\(instead of continuing to evaluate the expression containing\\\\nthe function call\\).\"" + +# We should have both a signal handler and a call dummy frame +# in this next output. + +mi_gdb_test "407-stack-list-frames" "407\\^done,reason=\"breakpoint-hit\",bkptno=\"3\",thread-id=\"$decimal\",frame=\{addr=\"$hex\",func=\"subroutine\",args=\\\[\{name=\"in\",value=\"$decimal\"\}\\\],file=\".*mi-syn-frame.c\",line=\"$decimal\"\},stack=\\\[frame=\{level=\"0\",addr=\"$hex\",func=\"subroutine\",file=\".*mi-syn-frame.c\",line=\"$decimal\"\},frame=\{level=\"1\",addr=\"$hex\",func=\"handler\",file=\".*mi-syn-frame.c\",line=\"$decimal\"\},frame=\{level=\"2\",addr=\"$hex\",func=\"\"\},.*frame=\{level=\"$decimal\",addr=\"$hex\",func=\"have_a_very_merry_interrupt\",file=\".*mi-syn-frame.c\",line=\"$decimal\"\},frame=\{level=\"$decimal\",addr=\"$hex\",func=\"\"\},frame=\{level=\"$decimal\",addr=\"$hex\",func=\"main\",file=\".*mi-syn-frame.c\",line=\"$decimal\"\}.*\\\]" + + +send_gdb "408-exec-continue\n" +gdb_expect { + -re "408\\^running\[\r\n\]+${my_mi_gdb_prompt}408\\\*stopped\[\r\n\]+${my_mi_gdb_prompt}$" { + pass "408-exec-continue" + } + timeout { + fail "408-exec-continue" + } +} + +mi_gdb_test "409-stack-list-frames 0 0" "409\\^done,stack=\\\[frame=\{level=\"0\",addr=\"$hex\",func=\"main\",file=\".*mi-syn-frame.c\",line=\"$decimal\"\}.*\\\]" + +# +# Call bar() by hand, which should get an exception while running. +# + +mi_gdb_test "410-data-evaluate-expression bar()" "hi in bar\[\r\n\]+\\&\"The program being debugged was signaled while in a function called from GDB.\\\\n\"\[\r\n\]+\\&\"GDB remains in the frame where the signal was received.\\\\n\"\[\r\n\]+\\&\"To change this behavior use \\\\\"set unwindonsignal on\\\\\"\\\\n\"\[\r\n\]+\\&\"Evaluation of the expression containing the function \\(bar\\) will be abandoned.\\\\n\"\[\r\n\]+410\\^error,msg=\"The program being debugged was signaled while in a function called from GDB.\\\\nGDB remains in the frame where the signal was received.\\\\nTo change this behavior use \\\\\"set unwindonsignal on\\\\\"\\\\nEvaluation of the expression containing the function \\(bar\\) will be abandoned.\"" "call inferior function which raises exception" + +mi_gdb_test "411-stack-list-frames" "411\\^done,reason=\"signal-received\",signal-name=\".*\",signal-meaning=\".*\",thread-id=\"$decimal\",frame=\{addr=\"$hex\",func=\"bar\",args=\\\[\\\],file=\".*mi-syn-frame.c\",line=\"$decimal\"\},stack=\\\[frame=\{level=\"0\",addr=\"$hex\",func=\"bar\",file=\".*mi-syn-frame.c\",line=\"$decimal\"},frame=\{level=\"1\",addr=\"$hex\",func=\"\"\},frame=\{level=\"2\",addr=\"$hex\",func=\"main\",file=\".*mi-syn-frame.c\",line=\"$decimal\"}.*\\\]" "backtrace from inferior function at exception" + +mi_gdb_exit + +return 0 diff --git a/gdb/testsuite/gdb.mi/mi1-symbol.exp b/gdb/testsuite/gdb.mi/mi1-symbol.exp new file mode 100644 index 0000000..f0da197 --- /dev/null +++ b/gdb/testsuite/gdb.mi/mi1-symbol.exp @@ -0,0 +1,61 @@ +# Copyright 2003 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# Please email any bugs, comments, and/or additions to this file to: +# bug-gdb@prep.ai.mit.edu + +# +# The goal is not to test gdb functionality, which is done by other tests, +# but to verify the correct output response to MI operations. +# + +load_lib mi-support.exp +set MIFLAGS "-i=mi1" + +gdb_exit +if [mi_gdb_start] { + continue +} + +set testfile "basics" +set srcfile ${testfile}.c +set binfile ${objdir}/${subdir}/${testfile} +if { [gdb_compile "${srcdir}/${subdir}/${srcfile}" "${binfile}" executable {debug additional_flags=-DFAKEARGV}] != "" } { + gdb_suppress_entire_file "Testcase compile failed, so all tests in this file will automatically fail." +} + +mi_run_to_main + +proc test_list_lines {} { + global mi_gdb_prompt + global hex + global decimal + global srcfile + + # Test list-lines. + # Tests: + # -symbol-list-lines ${srcfile} + + mi_gdb_test "-symbol-list-lines ${srcfile}" \ + "\\^done,lines=\[\{pc=\"$hex\",line=\"$decimal\"\}.*\]" \ + "symbol-list-lines for source file ${srcfile}" + +} + +test_list_lines + +mi_gdb_exit +return 0 diff --git a/gdb/testsuite/gdb.mi/mi2-basics.exp b/gdb/testsuite/gdb.mi/mi2-basics.exp new file mode 100644 index 0000000..44d2e4b --- /dev/null +++ b/gdb/testsuite/gdb.mi/mi2-basics.exp @@ -0,0 +1,246 @@ +# Copyright 1999, 2000 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# Please email any bugs, comments, and/or additions to this file to: +# bug-gdb@prep.ai.mit.edu + +# +# test basic Machine interface (MI) operations +# +# Verify that, using the MI, we can load a program and do +# other basic things that are used by all test files through mi_gdb_exit, +# mi_gdb_start, mi_delete_breakpoints, mi_gdb_reinitialize_dir and +# mi_gdb_load, so we can safely use those. +# +# The goal is not to test gdb functionality, which is done by other tests, +# but the command syntax and correct output response to MI operations. +# + +load_lib mi-support.exp +set MIFLAGS "-i=mi2" + +gdb_exit +if [mi_gdb_start] { + continue +} + +set testfile "basics" +set srcfile ${testfile}.c +set binfile ${objdir}/${subdir}/${testfile} +if { [gdb_compile "${srcdir}/${subdir}/${srcfile}" "${binfile}" executable {debug additional_flags=-DFAKEARGV}] != "" } { + gdb_suppress_entire_file "Testcase compile failed, so all tests in this file will automatically fail." +} + +# In this file we want to test if the operations needed by the following +# procedures work, so it makes no sense using them here. + +# mi_delete_breakpoints +# mi_gdb_reinitialize_dir $srcdir/$subdir +# mi_gdb_load ${binfile} + +# Test if the MI interpreter has been configured + +proc test_mi_interpreter_selection {} { + global mi_gdb_prompt + global gdb_prompt + + # All this test expects is to get the prompt back + # with no syntax error message + send_gdb "-gdb-version\n" + gdb_expect { + -re "GNU gdb .*\r\n$mi_gdb_prompt$" \ + { pass "acceptance of MI operations" + return 1} + -re ".*\r\n$mi_gdb_prompt$" \ + { fail "acceptance of MI operations" + note "Skipping all other MI tests." } + -re "Undefined command.*$gdb_prompt $" \ + { fail "acceptance of MI operations" + note "Skipping all other MI tests." } + -re ".*$gdb_prompt $" \ + { fail "acceptance of MI operations" + note "Skipping all other MI tests." } + timeout { fail "acceptance of MI operations (timeout)" + note "Skipping all other MI tests." } + } + return 0 +} + +proc test_exec_and_symbol_mi_operatons {} { + global mi_gdb_prompt + global binfile + + # Load symbols and specify executable on a single operation + # Tests: + # -file-exec-and-symbols + + # Can't use mi_gdb_test as if this doesn't work, + # we must give up on the whole test file + send_gdb "-file-exec-and-symbols ${binfile}\n" + gdb_expect { + -re "\[\r\n\]*\\\^done\r\n$mi_gdb_prompt$" \ + { pass "file-exec-and-symbols operation" } + timeout { fail "file-exec-and-symbols operation (timeout)" + note "Skipping all other MI tests." + return 0} + } + + # The following is not used by mi-support.exp, but we test here so + # we get done with loading a program basics. + + # Do it again, but now load symbols and specify executable with + # two separate operations + # Tests: + # -file-clear + # -file-exec-file + # -file-symbol-file + + # FIXME: file-clear is not implemented yet. +# mi_gdb_test "-file-clear" \ +# "\\\^done" \ +# "file-clear operation" + + mi_gdb_test "-file-exec-file ${binfile}" \ + "\\\^done" \ + "file-exec-file operation" + + mi_gdb_test "-file-symbol-file ${binfile}" \ + "\\\^done" \ + "file-symbol-file operation" + + # FIXME: if we cannot load we have to skip all other tests. +} + +proc test_breakpoints_deletion {} { + global mi_gdb_prompt + global srcfile + + # Clear all breakpoints and list to confirm + # Tests: + # -break-delete (all) + # -break-list + + # The all parameter is actually no parameter. + mi_gdb_test "200-break-delete" \ + "\\\^done" \ + "break-delete (all) operation" + + mi_gdb_test "201-break-list" \ + ".*\\\^done,BreakpointTable=\\\{.*,body=\\\[\\\]\\\}" \ + "all breakpoints removed" +} + +proc test_dir_specification {} { + global mi_gdb_prompt + global srcdir + global subdir + + # Add to the search directories, display, then reset back to default + # Tests: + # -environment-directory arg + # -environment-directory + # -environment-directory -r + +#exp_internal 1 + mi_gdb_test "202-environment-directory ${srcdir}/${subdir}" \ + "\\\^done,source-path=\"${srcdir}/${subdir}.\\\$cdir.\\\$cwd\"" \ + "environment-directory arg operation" + + mi_gdb_test "203-environment-directory" \ + "\\\^done,source-path=\"${srcdir}/${subdir}.\\\$cdir.\\\$cwd\"" \ + "environment-directory empty-string operation" + + mi_gdb_test "204-environment-directory -r" \ + "\\\^done,source-path=\"\\\$cdir.\\\$cwd\"" \ + "environment-directory operation" + +#exp_internal 0 +} + +proc test_cwd_specification {} { + global mi_gdb_prompt + global objdir + global subdir + + # Change the working directory, then print the current working directory + # Tests: + # -environment-cd ${objdir} + # -environment-pwd + + mi_gdb_test "205-environment-cd ${objdir}" \ + "\\\^done" \ + "environment-cd arg operation" + + mi_gdb_test "206-environment-pwd" \ + "\\\^done,cwd=\"${objdir}\"" \ + "environment-pwd operation" +} + +proc test_path_specification {} { + global mi_gdb_prompt + global orig_path + global objdir + global srcdir + + # Add to the path, display, then reset + # Tests: + # -environment-path + # -environment-path dir1 dir2 + # -environment-path -r dir + # -environment-path -r + +#exp_internal 1 + + send_gdb "-environment-path\n" + gdb_expect 20 { + -re "\\\^done,path=\"\(.*\)\"\r\n$mi_gdb_prompt" { + set orig_path $expect_out(1,string); + } + timeout { + perror "-environment-path (timeout)" ; + return + } + } + + mi_gdb_test "207-environment-path" \ + "\\\^done,path=\"$orig_path\"" \ + "environment-path no-args operation" + + mi_gdb_test "208-environment-path $srcdir $objdir" \ + "\\\^done,path=\"$srcdir.$objdir.$orig_path\"" \ + "environment-path dir1 dir2 operation" + + mi_gdb_test "209-environment-path -r $objdir" \ + "\\\^done,path=\"$objdir.$orig_path\"" \ + "environment-path -r dir operation" + + mi_gdb_test "210-environment-path -r" \ + "\\\^done,path=\"$orig_path\"" \ + "environment-path -r operation" + +#exp_internal 0 +} + +if [test_mi_interpreter_selection] { + test_exec_and_symbol_mi_operatons + test_breakpoints_deletion + test_dir_specification + test_cwd_specification + test_path_specification +} + +mi_gdb_exit +return 0 diff --git a/gdb/testsuite/gdb.mi/mi2-break.exp b/gdb/testsuite/gdb.mi/mi2-break.exp new file mode 100644 index 0000000..11cb0d9 --- /dev/null +++ b/gdb/testsuite/gdb.mi/mi2-break.exp @@ -0,0 +1,138 @@ +# Copyright 1999 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# Please email any bugs, comments, and/or additions to this file to: +# bug-gdb@prep.ai.mit.edu + +# +# Test essential Machine interface (MI) operations +# +# Verify that, using the MI, we can run a simple program and perform basic +# debugging activities like: insert breakpoints, run the program, +# step, next, continue until it ends and, last but not least, quit. +# +# The goal is not to test gdb functionality, which is done by other tests, +# but to verify the correct output response to MI operations. +# + +load_lib mi-support.exp +set MIFLAGS "-i=mi2" + +gdb_exit +if [mi_gdb_start] { + continue +} + +set testfile "basics" +set srcfile ${testfile}.c +set binfile ${objdir}/${subdir}/${testfile} +if { [gdb_compile "${srcdir}/${subdir}/${srcfile}" "${binfile}" executable {debug additional_flags=-DFAKEARGV}] != "" } { + gdb_suppress_entire_file "Testcase compile failed, so all tests in this file will automatically fail." +} + +mi_delete_breakpoints +mi_gdb_reinitialize_dir $srcdir/$subdir +mi_gdb_load ${binfile} + +proc test_tbreak_creation_and_listing {} { + global mi_gdb_prompt + global srcfile + global hex + + # Insert some breakpoints and list them + # Also, disable some so they do not interfere with other tests + # Tests: + # -break-insert -t main + # -break-insert -t basics.c:callee2 + # -break-insert -t basics.c:15 + # -break-insert -t srcfile:6 + # -break-list + + mi_gdb_test "222-break-insert -t main" \ + "222\\^done,bkpt=\{number=\"1\",type=\"breakpoint\",disp=\"del\",enabled=\"y\",addr=\"$hex\",func=\"main\",file=\".*basics.c\",line=\"32\",times=\"0\"\}" \ + "break-insert -t operation" + + mi_gdb_test "333-break-insert -t basics.c:callee2" \ + "333\\^done,bkpt=\{number=\"2\",type=\"breakpoint\",disp=\"del\",enabled=\"y\",addr=\"$hex\",func=\"callee2\",file=\".*basics.c\",line=\"22\",times=\"0\"\}" \ + "insert temp breakpoint at basics.c:callee2" + + mi_gdb_test "444-break-insert -t basics.c:15" \ + "444\\^done,bkpt=\{number=\"3\",type=\"breakpoint\",disp=\"del\",enabled=\"y\",addr=\"$hex\",func=\"callee3\",file=\".*basics.c\",line=\"15\",times=\"0\"\}" \ + "insert temp breakpoint at basics.c:15 (callee3)" + + # Getting the quoting right is tricky. That is "\"\":6" + mi_gdb_test "555-break-insert -t \"\\\"${srcfile}\\\":6\"" \ + "555\\^done,bkpt=\{number=\"4\",type=\"breakpoint\",disp=\"del\",enabled=\"y\",addr=\"$hex\",func=\"callee4\",file=\".*basics.c\",line=\"6\",times=\"0\"\}" \ + "insert temp breakpoint at \"\":6 (callee4)" + + mi_gdb_test "666-break-list" \ + "666\\\^done,BreakpointTable=\{nr_rows=\".\",nr_cols=\".\",hdr=\\\[\{width=\".*\",alignment=\".*\",col_name=\"number\",colhdr=\"Num\"\}.*colhdr=\"Type\".*colhdr=\"Disp\".*colhdr=\"Enb\".*colhdr=\"Address\".*colhdr=\"What\".*\\\],body=\\\[bkpt=\{number=\"1\",type=\"breakpoint\",disp=\"del\",enabled=\"y\",addr=\"$hex\",func=\"main\",file=\".*basics.c\",line=\"32\",times=\"0\"\}.*\\\]\}" \ + "list of breakpoints" + + mi_gdb_test "777-break-delete" \ + "777\\^done" \ + "delete temp breakpoints" +} + +proc test_rbreak_creation_and_listing {} { + global mi_gdb_prompt + global srcfile + global hex + + # Insert some breakpoints and list them + # Also, disable some so they do not interfere with other tests + # Tests: + # -break-insert -r main + # -break-insert -r callee2 + # -break-insert -r callee + # -break-insert -r .*llee + # -break-list + + setup_xfail "*-*-*" + mi_gdb_test "122-break-insert -r main" \ + "122\\^done,bkpt=\{number=\"5\",addr=\"$hex\",file=\".*basics.c\",line=\"32\"\}" \ + "break-insert -r operation" + + setup_xfail "*-*-*" + mi_gdb_test "133-break-insert -r callee2" \ + "133\\^done,bkpt=\{number=\"6\",addr=\"$hex\",file=\".*basics.c\",line=\"22\"\}" \ + "insert breakpoint with regexp callee2" + + setup_xfail "*-*-*" + mi_gdb_test "144-break-insert -r callee" \ + "144\\^done,bkpt=\{number=\"7\",addr=\"$hex\",file=\".*basics.c\",line=\"27\"\},bkpt=\{number=\"8\",addr=\"$hex\",file=\".*basics.c\",line=\"22\"\},bkpt=\{number=\"9\",addr=\"$hex\",file=\".*basics.c\",line=\"17\"\},bkpt=\{number=\"10\",addr=\"$hex\",file=\".*basics.c\",line=\"8\"\}" \ + "insert breakpoint with regexp callee" + + setup_xfail "*-*-*" + mi_gdb_test "155-break-insert -r \.\*llee" \ + "155\\^done,bkpt=\{number=\"11\",addr=\"$hex\",file=\".*basics.c\",line=\"27\"\},bkpt=\{number=\"12\",addr=\"$hex\",file=\".*basics.c\",line=\"22\"\},bkpt=\{number=\"13\",addr=\"$hex\",file=\".*basics.c\",line=\"17\"\},bkpt=\{number=\"14\",addr=\"$hex\",file=\".*basics.c\",line=\"8\"\}" \ + "insert breakpoint with regexp .*llee" + + setup_xfail "*-*-*" + mi_gdb_test "166-break-list" \ + "1\\\^done,BreakpointTable=\{nr_rows=\".\",nr_cols=\".\",hdr=\\\[\{width=\".*\",alignment=\".*\",col_name=\"number\",colhdr=\"Num\"\}.*colhdr=\"Type\".*colhdr=\"Disp\".*colhdr=\"Enb\".*colhdr=\"Address\".*colhdr=\"What\".*\\\],body=\\\[bkpt=\{number=\"5\",type=\"breakpoint\",disp=\"keep\",enabled=\"y\",addr=\"$hex\",func=\"main\",file=\".*basics.c\",line=\"32\",times=\"0\"\},.*\}\\\]\}" \ + "list of breakpoints" + + mi_gdb_test "177-break-delete" \ + "177\\^done" \ + "delete temp breakpoints" +} + +test_tbreak_creation_and_listing +test_rbreak_creation_and_listing + +mi_gdb_exit +return 0 diff --git a/gdb/testsuite/gdb.mi/mi2-cli.exp b/gdb/testsuite/gdb.mi/mi2-cli.exp new file mode 100644 index 0000000..10295a9 --- /dev/null +++ b/gdb/testsuite/gdb.mi/mi2-cli.exp @@ -0,0 +1,208 @@ +# Copyright 2002, 2003 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# Please email any bugs, comments, and/or additions to this file to: +# bug-gdb@prep.ai.mit.edu + +# This file tests that GDB's console can be accessed via the MI. +# Specifically, we are testing the "interpreter-exec" command and that +# the commands that are executed via this command are properly executed. +# Console commands executed via MI should use MI output wrappers, MI event +# handlers, etc. + +load_lib mi-support.exp +set MIFLAGS "-i=mi2" + +gdb_exit +if [mi_gdb_start] { + continue +} + +set testfile "basics" +set srcfile ${testfile}.c +set binfile ${objdir}/${subdir}/${testfile} +if { [gdb_compile "${srcdir}/${subdir}/${srcfile}" "${binfile}" executable {debug additional_flags=-DFAKEARGV}] != "" } { + gdb_suppress_entire_file "Testcase compile failed, so all tests in this file will automatically fail." +} + +mi_gdb_reinitialize_dir $srcdir/$subdir + +mi_gdb_test "-interpreter-exec" \ + {\^error,msg="mi_cmd_interpreter_exec: Usage: -interpreter-exec interp command"} \ + "-interpreter-exec with no arguments" + +mi_gdb_test "-interpreter-exec console" \ + {\^error,msg="mi_cmd_interpreter_exec: Usage: -interpreter-exec interp command"} \ + "-interpreter-exec with one argument" + +mi_gdb_test "-interpreter-exec bogus command" \ + {\^error,msg="mi_cmd_interpreter_exec: could not find interpreter \\\"bogus\\\""} \ + "-interpreter-exec with bogus interpreter" + +set msg {Undefined command: \\\"bogus\\\"\. Try \\\"help\\\"\.} +mi_gdb_test "-interpreter-exec console bogus" \ + "&\\\"$msg\\\\n\\\".*\\^error,msg=\\\"$msg\\\".*" \ + "-interpreter-exec console bogus" + +# NOTE: cagney/2003-02-03: Not yet. +# mi_gdb_test "-interpreter-exec console \"file $binfile\"" \ +# {(=.*)+\^done} \ +# "-interpreter-exec console \"file \$binfile\"" +mi_gdb_test "-interpreter-exec console \"file $binfile\"" \ + {\^done} \ + "-interpreter-exec console \"file \$binfile\"" + +mi_run_to_main + +mi_gdb_test "-interpreter-exec console \"set args foobar\"" \ + {\^done} \ + "-interpreter-exec console \"set args foobar\"" + +mi_gdb_test "-interpreter-exec console \"show args\"" \ + {\~"Argument list to give program being debugged when it is started is \\\"foobar\\\"\.\\n".*\^done} \ + "-interpreter-exec console \"show args\"" + +# NOTE: cagney/2003-02-03: Not yet. +# mi_gdb_test "-interpreter-exec console \"break callee4\"" \ +# {(&.*)*.*~"Breakpoint 2 at.*\\n".*=breakpoint-create,number="2".*\^done} \ +# "-interpreter-exec console \"break callee4\"" +mi_gdb_test "-interpreter-exec console \"break callee4\"" \ + {(&.*)*.*~"Breakpoint 2 at.*\\n".*\^done} \ + "-interpreter-exec console \"break callee4\"" + +mi_gdb_test "-interpreter-exec console \"info break\"" \ + {\~"Num[ \t]*Type[ \t]*Disp[ \t]*Enb[ \t]*Address[ \t]*What\\n".*~"2[ \t]*breakpoint[ \t]*keep[ \t]*y[ \t]*0x[0-9A-Fa-f]+[ \t]*in callee4 at .*basics.c:[0-9]+\\n".*\^done} \ + "-interpreter-exec console \"info break\"" + +mi_gdb_test "-interpreter-exec console \"set listsize 1\"" \ + {\^done} \ + "-interpreter-exec console \"set listsize 1\"" + +mi_gdb_test "-interpreter-exec console \"list\"" \ + {.*\~"32[ \t(\\t)]*callee1.*\\n".*\^done} \ + "-interpreter-exec console \"list\"" + +# # NOTE: cagney/2003-02-03: Not yet. +# mi_gdb_test "-exec-continue" \ +# {.*\*stopped,reason="breakpoint-hit",.*func="callee4".*file=".*basics.c",line="8"\}} \ +# "-interpreter-exec console \"continue to callee4\"" +send_gdb "999-exec-continue\n" +gdb_expect { + -re "999\\^running\[\r\n\]+$mi_gdb_prompt.*999\\*stopped,reason=.breakpoint-hit.*$mi_gdb_prompt$" { + pass "continue to callee4" + } + timeout { + fail "continue to callee4 (timeout)" + } +} + +# NOTE: cagney/2003-02-03: Not yet. +# mi_gdb_test "100-interpreter-exec console \"delete 2\"" \ +# {.*=breakpoint-delete,number=\"2\".*\^done} \ +# "-interpreter-exec console \"delete 2\"" +mi_gdb_test "100-interpreter-exec console \"delete 2\"" \ + {100\^done} \ + "-interpreter-exec console \"delete 2\"" + +# NOTE: cagney/2003-02-03: Not yet. +# mi_gdb_test "200-interpreter-exec console \"up\"" \ +# {.*=selected-frame-level-changed,level="1".*\^done} \ +# "-interpreter-exec console \"up\"" +mi_gdb_test "200-interpreter-exec console \"up\"" \ + {200\^done} \ + "-interpreter-exec console \"up\"" + +# NOTE: cagney/2003-02-03: Not yet. +# mi_gdb_test "300-interpreter-exec console \"down\"" \ +# {.*=selected-frame-level-changed,level="0".*\^done} \ +# "-interpreter-exec console \"down\"" +mi_gdb_test "300-interpreter-exec console \"down\"" \ + {300\^done} \ + "-interpreter-exec console \"down\"" + +# NOTE: cagney/2003-02-03: Not yet. +# mi_gdb_test "-interpreter-exec console \"frame 2\"" \ +# {.*=selected-frame-level-changed,level="2".*\^done} \ +# "-interpreter-exec console \"frame 2\"" +mi_gdb_test "400-interpreter-exec console \"frame 2\"" \ + {400\^done} \ + "-interpreter-exec console \"frame 2\"" + +# NOTE: cagney/2003-02-03: Not yet. +# mi_gdb_test "-stack-select-frame 0" \ +# {.*=selected-frame-level-changed,level="0".*\^done} \ +# "-stack-select-frame 0" +mi_gdb_test "500-stack-select-frame 0" \ + {500\^done} \ + "-stack-select-frame 0" + +# NOTE: cagney/2003-02-03: Not yet. +# mi_gdb_test "-break-insert -t basics.c:35" \ +# {.*=breakpoint-create,number="3".*\^done} \ +# "-break-insert -t basics.c:35" +mi_gdb_test "600-break-insert -t basics.c:35" \ + {600\^done,bkpt=.number="3",type="breakpoint".*\}} \ + "-break-insert -t basics.c:35" + +# mi_gdb_test "-exec-continue" \ +# {.*\*stopped.*,file=".*basics.c",line="35"\}} \ +# "-exec-continue to line 35" +send_gdb "700-exec-continue\n" +gdb_expect { + -re "700\\^running\[\r\n\]+$mi_gdb_prompt.*\\*stopped.*,file=.*basics.c.,line=.35.*$mi_gdb_prompt$" { + pass "-exec-continue to line 35" + } + timeout { + fail "-exec-continue to line 35" + } +} + +# NOTE: cagney/2003-02-03: Not yet. +# mi_gdb_test "-exec-next" \ +# {.*\*stopped,reason="end-stepping-range",.*,file=".*basics.c",line="37"\}} \ +# "-exec-next to line 37" +send_gdb "800-exec-next\n" +gdb_expect { + -re "800\\^running\[\r\n\]+$mi_gdb_prompt.*\\*stopped,reason=.end-stepping-range.*,file=.*basics.c.,line=.37.*$mi_gdb_prompt$" { + pass "-exec-next to line 37" + } + timeout { + fail "-exec-next to line 37" + } +} + +mi_gdb_test "-interpreter-exec console \"list\"" \ + {\~"37[ \t(\\t)]*return 0;\\n".*\^done} \ + "-interpreter-exec console \"list\" at basics.c:37" + +mi_gdb_test "-interpreter-exec console \"help set args\"" \ + {\~"Set argument list to give program being debugged when it is started\.\\nFollow this command with any number of args, to be passed to the program\.".*\^done} \ + "-interpreter-exec console \"help set args\"" + +# NOTE: cagney/2003-02-03: Not yet. +# mi_gdb_test "-interpreter-exec console \"set \$pc=0x0\"" \ +# {.*=target-changed.*\^done} \ +# "-interpreter-exec console \"set \$pc=0x0\"" +mi_gdb_test "888-interpreter-exec console \"set \$pc=0x0\"" \ + {888\^done} \ + "-interpreter-exec console \"set \$pc=0x0\"" + +#mi_gdb_test "-interpreter-exec console \"\"" \ + {} \ + "-interpreter-exec console \"\"" + +mi_gdb_exit +return 0 diff --git a/gdb/testsuite/gdb.mi/mi2-console.exp b/gdb/testsuite/gdb.mi/mi2-console.exp new file mode 100644 index 0000000..5e307b9 --- /dev/null +++ b/gdb/testsuite/gdb.mi/mi2-console.exp @@ -0,0 +1,97 @@ +# Copyright 1999, 2000, 2001, 2002 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# Please email any bugs, comments, and/or additions to this file to: +# bug-gdb@prep.ai.mit.edu + +# +# Test essential Machine interface (MI) operations +# +# Verify that, using the MI, we can run a simple program and perform basic +# debugging activities like: insert breakpoints, run the program, +# step, next, continue until it ends and, last but not least, quit. +# +# The goal is not to test gdb functionality, which is done by other tests, +# but to verify the correct output response to MI operations. +# + +# This test only works when talking to a target that routes its output +# through GDB. Check that we're either talking to a simulator or a +# remote target. + +load_lib mi-support.exp +set MIFLAGS "-i=mi2" + +gdb_exit +if [mi_gdb_start] { + continue +} + +set testfile "mi-console" +set srcfile ${testfile}.c +set binfile ${objdir}/${subdir}/${testfile} +if { [gdb_compile "${srcdir}/${subdir}/${srcfile}" "${binfile}" executable {debug additional_flags=-DFAKEARGV}] != "" } { + gdb_suppress_entire_file "Testcase compile failed, so all tests in this file will automatically fail." +} + +mi_delete_breakpoints +mi_gdb_reinitialize_dir $srcdir/$subdir +mi_gdb_load ${binfile} + +mi_run_to_main + +# Next over the hello() call which will produce lots of output +send_gdb "47-exec-next\n" +gdb_expect { + -re "47\\^running\r\n$mi_gdb_prompt" { + pass "Started step over hello" + } + timeout { + fail "Started step over hello (timeout)" + } +} + +gdb_expect { + -re "@\"H\"\r\n.*@\"e\"\r\n.*@\"l\"\r\n.*@\"l\"\r\n.*@\"o\"\r\n.*@\" \"\r\n.*@\"\\\\\\\\\"\r\n.*@\"\\\\\"\"\r\n.*@\"!\"\r\n.*@\"\\\\r\"\r\n.*@\"\\\\n\"\r\n" { + pass "Hello message" + } + -re "Hello" { + + # Probably a native system where GDB doesn't have direct + # control over the inferior console. + # For this to work, GDB would need to run the inferior process + # under a PTY and then use the even-loops ability to wait on + # multiple event sources to channel the output back through the + # MI. + + kfail "gdb/623" "Hello message" + } + timeout { + fail "Hello message (timeout)" + } +} + +gdb_expect { + -re "47\\*stopped.*$mi_gdb_prompt$" { + pass "Finished step over hello" + } + timeout { + fail "Finished step over hello (timeout)" + } +} + +mi_gdb_exit +return 0 diff --git a/gdb/testsuite/gdb.mi/mi2-disassemble.exp b/gdb/testsuite/gdb.mi/mi2-disassemble.exp new file mode 100644 index 0000000..8cd76f9 --- /dev/null +++ b/gdb/testsuite/gdb.mi/mi2-disassemble.exp @@ -0,0 +1,178 @@ +# Copyright 1999, 2000, 2002 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# Please email any bugs, comments, and/or additions to this file to: +# bug-gdb@prep.ai.mit.edu + +# +# Test Machine interface (MI) operations for disassembly. +# +# The goal is not to test gdb functionality, which is done by other tests, +# but to verify the correct output response to MI operations. +# + +load_lib mi-support.exp +set MIFLAGS "-i=mi2" + +gdb_exit +if [mi_gdb_start] { + continue +} + +set testfile "basics" +set srcfile ${testfile}.c +set binfile ${objdir}/${subdir}/${testfile} +if { [gdb_compile "${srcdir}/${subdir}/${srcfile}" "${binfile}" executable {debug additional_flags=-DFAKEARGV}] != "" } { + gdb_suppress_entire_file "Testcase compile failed, so all tests in this file will automatically fail." +} + +mi_delete_breakpoints +mi_gdb_reinitialize_dir $srcdir/$subdir +mi_gdb_load ${binfile} + +proc test_disassembly_only {} { + global mi_gdb_prompt + global hex + global decimal + + # Test disassembly more only for the current function. + # Tests: + # -data-disassemble -s $pc -e "$pc+8" -- 0 + # -data-disassembly -f basics.c -l 32 -- 0 + + mi_gdb_test "print/x \$pc" "" "" + mi_gdb_test "111-data-disassemble -s \$pc -e \"\$pc + 12\" -- 0" \ + "111\\^done,asm_insns=\\\[\{address=\"$hex\",func-name=\"main\",offset=\"$decimal\",inst=\".*\"\},\{address=\"$hex\",func-name=\"main\",offset=\"$decimal\",inst=\".*\"\}.*\]" \ + "data-disassemble from pc to pc+12 assembly only" + + mi_gdb_test "222-data-disassemble -f basics.c -l 32 -- 0" \ + "222\\^done,asm_insns=\\\[\{address=\"$hex\",func-name=\"main\",offset=\"0\",inst=\".*\"\},.*,\{address=\"$hex\",func-name=\"main\",offset=\"$decimal\",inst=\".*\"\}\\\]" \ + "data-disassemble file & line, assembly only" +} + +proc test_disassembly_lines_limit {} { + global mi_gdb_prompt + global hex + global decimal + + # Test disassembly more only for the current function. + # Tests: + # -data-disassembly -f basics.c -l 32 -n 20 -- 0 + # -data-disassembly -f basics.c -l 32 -n 0 -- 0 + # -data-disassembly -f basics.c -l 32 -n 50 -- 0 + + mi_gdb_test "print/x \$pc" "" "" + mi_gdb_test "222-data-disassemble -f basics.c -l 32 -n 20 -- 0" \ + "222\\^done,asm_insns=\\\[\{address=\"$hex\",func-name=\"main\",offset=\"0\",inst=\".*\"\},.*,\{address=\"$hex\",func-name=\"main\",offset=\"$decimal\",inst=\".*\"\}\\\]" \ + "data-disassemble file, line, number assembly only" + + mi_gdb_test "222-data-disassemble -f basics.c -l 32 -n 0 -- 0" \ + "222\\^done,asm_insns=\\\[\\\]" \ + "data-disassemble file, line, number (zero lines) assembly only" + + mi_gdb_test "222-data-disassemble -f basics.c -l 32 -n 50 -- 0" \ + "222\\^done,asm_insns=\\\[\{address=\"$hex\",func-name=\"main\",offset=\"0\",inst=\".*\"\},.*,\{address=\"$hex\",func-name=\"main\",offset=\"$decimal\",inst=\".*\"\}\\\]" \ + "data-disassemble file, line, number (more than main lines) assembly only" +} + + +proc test_disassembly_mixed {} { + global mi_gdb_prompt + global hex + global decimal + + # Test disassembly more only for the current function. + # Tests: + # -data-disassembly -f basics.c -l 21 -- 1 + # -data-disassembly -s $pc -e "$pc+8" -- 1 + + mi_gdb_test "002-data-disassemble -f basics.c -l 21 -- 1" \ + "002\\^done,asm_insns=\\\[src_and_asm_line=\{line=\"21\",file=\".*basics.c\",line_asm_insn=\\\[\{address=\"$hex\",func-name=\"callee2\",offset=\"0\",inst=\".*\"\}.*\\\]\}.*,src_and_asm_line=\{line=\"$decimal\",file=\".*basics.c\",line_asm_insn=\\\[.*\{address=\"$hex\",func-name=\"callee2\",offset=\"$decimal\",inst=\".*\"\}\\\]\}\\\]" \ + "data-disassemble file, line assembly mixed" + + # + # In mixed mode, the lowest level of granularity is the source line. + # So we are going to get the disassembly for the source line at + # which we are now, even if we have specified that the range is only 2 insns. + # + mi_gdb_test "003-data-disassemble -s \$pc -e \"\$pc+4\" -- 1" \ + "003\\^done,asm_insns=\\\[src_and_asm_line=\{line=\"$decimal\",file=\".*basics.c\",line_asm_insn=\\\[\{address=\"$hex\",func-name=\"main\",offset=\"$decimal\",inst=\".*\"\}.*\{address=\"$hex\",func-name=\"main\",offset=\"$decimal\",inst=\".*\"\}\\\]\}\\\]" \ + "data-disassemble range assembly mixed" +} + +proc test_disassembly_mixed_lines_limit {} { + global mi_gdb_prompt + global hex + global decimal + + # Test disassembly more only for the current function. + # Tests: + # -data-disassembly -f basics.c -l 32 -n 20 -- 1 + # -data-disassembly -f basics.c -l 32 -n 0 -- 1 + # -data-disassembly -f basics.c -l 32 -n 50 -- 1 + + mi_gdb_test "print/x \$pc" "" "" + mi_gdb_test "222-data-disassemble -f basics.c -l 32 -n 20 -- 1" \ + "222\\^done,asm_insns=\\\[src_and_asm_line=\{line=\"$decimal\",file=\".*basics.c\",line_asm_insn=\\\[\{address=\"$hex\",func-name=\"main\",offset=\"0\",inst=\".*\"\},.*,\{address=\"$hex\",func-name=\"main\",offset=\"$decimal\",inst=\".*\"\}\\\]\}\]" \ + "data-disassemble file, line, number assembly mixed" + + mi_gdb_test "222-data-disassemble -f basics.c -l 32 -n 0 -- 1" \ + "222\\^done,asm_insns=\\\[src_and_asm_line=\{line=\"31\",file=\".*basics.c\",line_asm_insn=\\\[\\\]\}\\\]" \ + "data-disassemble file, line, number (zero lines) assembly mixed" + + mi_gdb_test "222-data-disassemble -f basics.c -l 32 -n 50 -- 1" \ + "222\\^done,asm_insns=\\\[src_and_asm_line=\{line=\"$decimal\",file=\".*basics.c\",line_asm_insn=\\\[\{address=\"$hex\",func-name=\"main\",offset=\"0\",inst=\".*\"\}.*,\{address=\"$hex\",func-name=\"main\",offset=\"$decimal\",inst=\".*\"\}\\\]\}\]" \ + "data-disassemble file, line, number (more than main lines) assembly mixed" +} + +proc test_disassembly_bogus_args {} { + global mi_gdb_prompt + global hex + + # Test that bogus input to disassembly command is rejected. + # Tests: + # -data-disassembly -f foo -l abc -n 0 -- 0 + # -data-disassembly -s foo -e bar -- 0 + # -data-disassembly -s $pc -f basics.c -- 0 + # -data-disassembly -f basics.c -l 32 -- 9 + + mi_gdb_test "123-data-disassemble -f foo -l abc -n 0 -- 0" \ + ".*123\\^error,msg=\"mi_cmd_disassemble: Invalid filename.\"" \ + "data-disassemble bogus filename" + + mi_gdb_test "321-data-disassemble -s foo -e bar -- 0" \ + "321\\^error,msg=\"No symbol \\\\\"foo\\\\\" in current context.\"" \ + "data-disassemble bogus address" + + mi_gdb_test "456-data-disassemble -s \$pc -f basics.c -- 0" \ + "456\\^error,msg=\"mi_cmd_disassemble: Usage: \\( .-f filename -l linenum .-n howmany.. | .-s startaddr -e endaddr.\\) .--. mixed_mode.\"" \ + "data-disassemble mix different args" + + mi_gdb_test "789-data-disassemble -f basics.c -l 32 -- 9" \ + "789\\^error,msg=\"mi_cmd_disassemble: Mixed_mode argument must be 0 or 1.\"" \ + "data-disassemble wrong mode arg" + +} + +mi_run_to_main +test_disassembly_only +test_disassembly_mixed +test_disassembly_bogus_args +test_disassembly_lines_limit +test_disassembly_mixed_lines_limit + +mi_gdb_exit +return 0 diff --git a/gdb/testsuite/gdb.mi/mi2-eval.exp b/gdb/testsuite/gdb.mi/mi2-eval.exp new file mode 100644 index 0000000..85fd991 --- /dev/null +++ b/gdb/testsuite/gdb.mi/mi2-eval.exp @@ -0,0 +1,62 @@ +# Copyright 1999, 2000, 2002 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# Please email any bugs, comments, and/or additions to this file to: +# bug-gdb@prep.ai.mit.edu + +# +# Test essential Machine interface (MI) operations +# +# Verify -data-evaluate-expression. There are really minimal tests. + +# The goal is not to test gdb functionality, which is done by other tests, +# but to verify the correct output response to MI operations. +# + +load_lib mi-support.exp +set MIFLAGS "-i=mi2" + +gdb_exit +if [mi_gdb_start] { + continue +} + +set testfile "basics" +set srcfile ${testfile}.c +set binfile ${objdir}/${subdir}/${testfile} +if { [gdb_compile "${srcdir}/${subdir}/${srcfile}" "${binfile}" executable {debug additional_flags=-DFAKEARGV}] != "" } { + gdb_suppress_entire_file "Testcase compile failed, so all tests in this file will automatically fail." +} + +mi_delete_breakpoints +mi_gdb_reinitialize_dir $srcdir/$subdir +mi_gdb_reinitialize_dir $srcdir/$subdir +mi_gdb_load ${binfile} + +mi_runto callee4 +mi_next_to "callee4" "" "basics.c" "9" "next at callee4" + +mi_gdb_test "211-data-evaluate-expression A" "211\\^done,value=\"1\"" "eval A" + +mi_gdb_test "311-data-evaluate-expression &A" "311\\^done,value=\"$hex\"" "eval &A" + +mi_gdb_test "411-data-evaluate-expression A+3" "411\\^done,value=\"4\"" "eval A+3" + +mi_gdb_test "511-data-evaluate-expression \"A + 3\"" "511\\^done,value=\"4\"" "eval A + 3" + + +mi_gdb_exit +return 0 diff --git a/gdb/testsuite/gdb.mi/mi2-file.exp b/gdb/testsuite/gdb.mi/mi2-file.exp new file mode 100644 index 0000000..fe75a93 --- /dev/null +++ b/gdb/testsuite/gdb.mi/mi2-file.exp @@ -0,0 +1,65 @@ +# Copyright 1999 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# Please email any bugs, comments, and/or additions to this file to: +# bug-gdb@prep.ai.mit.edu + +# +# Test essential Machine interface (MI) operations +# +# Verify that, using the MI, we can run a simple program and perform basic +# debugging activities like: insert breakpoints, run the program, +# step, next, continue until it ends and, last but not least, quit. +# +# The goal is not to test gdb functionality, which is done by other tests, +# but to verify the correct output response to MI operations. +# + +load_lib mi-support.exp +set MIFLAGS "-i=mi2" + +gdb_exit +if [mi_gdb_start] { + continue +} + +set testfile "basics" +set srcfile ${testfile}.c +set binfile ${objdir}/${subdir}/${testfile} +if { [gdb_compile "${srcdir}/${subdir}/${srcfile}" "${binfile}" executable {debug additional_flags=-DFAKEARGV}] != "" } { + gdb_suppress_entire_file "Testcase compile failed, so all tests in this file will automatically fail." +} + +mi_delete_breakpoints +mi_gdb_reinitialize_dir $srcdir/$subdir +mi_gdb_load ${binfile} + +proc test_tbreak_creation_and_listing {} { + global srcfile + global srcdir + global subdir + set srcfilepath [string_to_regexp ${srcdir}/${subdir}/${srcfile}] + + # get the path and absolute path to the current executable + mi_gdb_test "111-file-list-exec-source-file" \ + "111\\\^done,line=\"23\",file=\"${srcfilepath}\",fullname=\"/.*/${srcfile}\"" \ + "request path info of current source file (${srcfile})" +} + +test_tbreak_creation_and_listing + +mi_gdb_exit +return 0 diff --git a/gdb/testsuite/gdb.mi/mi2-hack-cli.exp b/gdb/testsuite/gdb.mi/mi2-hack-cli.exp new file mode 100644 index 0000000..066eea2 --- /dev/null +++ b/gdb/testsuite/gdb.mi/mi2-hack-cli.exp @@ -0,0 +1,40 @@ +# Copyright 1999 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# Please email any bugs, comments, and/or additions to this file to: +# bug-gdb@prep.ai.mit.edu + + +# Some basic checks for the CLI. + +load_lib mi-support.exp +set MIFLAGS "-i=mi2" + +gdb_exit +if [mi_gdb_start] { + continue +} + +mi_gdb_test "show architecture" \ + "&\"show architecture\\\\n\"\r\n~\"The target architecture.*\"\r\n\\^done" \ + "show architecture" + +mi_gdb_test "47show architecture" \ + "&\"show architecture\\\\n\"\r\n~\"The target architecture.*\"\r\n47\\^done" \ + "47show architecture" + +mi_gdb_exit +return 0 diff --git a/gdb/testsuite/gdb.mi/mi2-pthreads.exp b/gdb/testsuite/gdb.mi/mi2-pthreads.exp new file mode 100644 index 0000000..fe007e5 --- /dev/null +++ b/gdb/testsuite/gdb.mi/mi2-pthreads.exp @@ -0,0 +1,221 @@ +# Copyright 2002, 2003 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# Please email any bugs, comments, and/or additions to this file to: +# bug-gdb@prep.ai.mit.edu + +# This file tests MI thread commands. +# Specifically, we are testing the MI command set and the console (in MI) +# command set ("interpreter-exec") and that the commands that are executed +# via these command pathways are properly executed. Console commands +# executed via MI should use MI output wrappers, MI event handlers, etc. + +# This only works with native configurations +if {![isnative]} { + return +} + +load_lib mi-support.exp +set MIFLAGS "-i=mi2" + +gdb_exit +if {[mi_gdb_start]} { + continue +} + +# The procs below dealing with parsing cli/mi output for the threadlist +# is duplicated in gdb669.exp. Any changes here will probably need to +# be made there as well. + +proc get_mi_thread_list {name} { + global expect_out + + # MI will return a list of thread ids: + # + # -thread-list-ids + # ^done,thread-ids=[thread-id="1",thread-id="2",...],number-of-threads="N" + # (gdb) + mi_gdb_test "-thread-list-ids" \ + {\^done,thread-ids={(thread-id="[0-9]+"(,)?)+},number-of-threads="[0-9]+"} \ + "-thread_list_ids ($name)" + + set output {} + if {[info exists expect_out(buffer)]} { + set output $expect_out(buffer) + } + + set thread_list {} + if {![regexp {thread-ids=\{(thread-id="[0-9]+"(,)?)*\}} $output threads]} { + fail "finding threads in MI output ($name)" + } else { + pass "finding threads in MI output ($name)" + + # Make list of console threads + set start [expr {[string first \{ $threads] + 1}] + set end [expr {[string first \} $threads] - 1}] + set threads [string range $threads $start $end] + foreach thread [split $threads ,] { + if {[scan $thread {thread-id="%d"} num]} { + lappend thread_list $num + } + } + } + + return $thread_list +} + +# Check that MI and the console know of the same threads. +# Appends NAME to all test names. +proc check_mi_and_console_threads {name} { + global expect_out + + mi_gdb_test "-thread-list-ids" \ + {\^done,thread-ids={(thread-id="[0-9]+"(,)*)+},number-of-threads="[0-9]+"} \ + "-thread-list-ids ($name)" + set mi_output {} + if {[info exists expect_out(buffer)]} { + set mi_output $expect_out(buffer) + } + + # GDB will return a list of thread ids and some more info: + # + # (gdb) + # -interpreter-exec console "info threads" + # ~" 4 Thread 2051 (LWP 7734) 0x401166b1 in __libc_nanosleep () at __libc_nanosleep:-1" + # ~" 3 Thread 1026 (LWP 7733) () at __libc_nanosleep:-1" + # ~" 2 Thread 2049 (LWP 7732) 0x401411f8 in __poll (fds=0x804bb24, nfds=1, timeout=2000) at ../sysdeps/unix/sysv/linux/poll.c:63" + # ~"* 1 Thread 1024 (LWP 7731) main (argc=1, argv=0xbfffdd94) at ../../../src/gdb/testsuite/gdb.mi/pthreads.c:160" + # FIXME: kseitz/2002-09-05: Don't use the hack-cli method. + mi_gdb_test "info threads" \ + {.*(~".*"[\r\n]*)+.*} \ + "info threads ($name)" + set console_output {} + if {[info exists $expect_out(buffer)]} { + set console_output $expect_out(buffer) + } + + # Make a list of all known threads to console (gdb's thread IDs) + set console_thread_list {} + foreach line [split $console_output \n] { + if {[string index $line 0] == "~"} { + # This is a line from the console; trim off "~", " ", "*", and "\"" + set line [string trim $line ~\ \"\*] + if {[scan $line "%d" id] == 1} { + lappend console_thread_list $id + } + } + } + + # Now find the result string from MI + set mi_result "" + foreach line [split $mi_output \n] { + if {[string range $line 0 4] == "^done"} { + set mi_result $line + } + } + if {$mi_result == ""} { + fail "finding MI result string ($name)" + } else { + pass "finding MI result string ($name)" + } + + # Finally, extract the thread ids and compare them to the console + set num_mi_threads_str "" + if {![regexp {number-of-threads="[0-9]+"} $mi_result num_mi_threads_str]} { + fail "finding number of threads in MI output ($name)" + } else { + pass "finding number of threads in MI output ($name)" + + # Extract the number of threads from the MI result + if {![scan $num_mi_threads_str {number-of-threads="%d"} num_mi_threads]} { + fail "got number of threads from MI ($name)" + } else { + pass "got number of threads from MI ($name)" + + # Check if MI and console have same number of threads + if {$num_mi_threads != [llength $console_thread_list]} { + fail "console and MI have same number of threads ($name)" + } else { + pass "console and MI have same number of threads ($name)" + + # Get MI thread list + set mi_thread_list [get_mi_thread_list $name] + + # Check if MI and console have the same threads + set fails 0 + foreach ct [lsort $console_thread_list] mt [lsort $mi_thread_list] { + if {$ct != $mt} { + incr fails + } + } + if {$fails > 0} { + fail "MI and console have same threads ($name)" + + # Send a list of failures to the log + send_log "Console has thread ids: $console_thread_list\n" + send_log "MI has thread ids: $mi_thread_list\n" + } else { + pass "MI and console have same threads ($name)" + } + } + } + } +} + +# This procedure tests the various thread commands in MI. +proc check_mi_thread_command_set {} { + + mi_runto done_making_threads + + set thread_list [get_mi_thread_list "in check_mi_thread_command_set"] + + mi_gdb_test "-thread-select" \ + {\^error,msg="mi_cmd_thread_select: USAGE: threadnum."} \ + "check_mi_thread_command_set: -thread-select" + + mi_gdb_test "-thread-select 123456789" \ + {\^error,msg="Thread ID 123456789 not known\."} \ + "check_mi_thread_command_set: -thread-select 123456789" + + foreach thread $thread_list { + # line and file are optional. + # many of the threads are blocked in libc calls, + # and many people have libc's with no symbols. + mi_gdb_test "-thread-select $thread" \ + "\\^done,new-thread-id=\"$thread\",frame={.*}(,line=\"(-)?\[0-9\]+\",file=\".*\")?" \ + "check_mi_thread_command_set: -thread-select $thread" + } +} + +# +# Start here +# +set testfile "pthreads" +set srcfile "$testfile.c" +set binfile "$objdir/$subdir/$testfile" + +set options [list debug incdir=$objdir] +if {[gdb_compile_pthreads "$srcdir/$subdir/$srcfile" $binfile executable $options] != "" } { + return -1 +} + +mi_gdb_reinitialize_dir $srcdir/$subdir +mi_gdb_load $binfile + +check_mi_thread_command_set + +mi_gdb_exit + diff --git a/gdb/testsuite/gdb.mi/mi2-read-memory.exp b/gdb/testsuite/gdb.mi/mi2-read-memory.exp new file mode 100644 index 0000000..eee36a7 --- /dev/null +++ b/gdb/testsuite/gdb.mi/mi2-read-memory.exp @@ -0,0 +1,86 @@ +# Copyright 1999, 2000, 2002 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# Please email any bugs, comments, and/or additions to this file to: +# bug-gdb@prep.ai.mit.edu + +# +# test basic Machine interface (MI) operations +# +# Verify that, using the MI, we can load a program and do +# other basic things that are used by all test files through mi_gdb_exit, +# mi_gdb_start, mi_delete_breakpoints, mi_gdb_reinitialize_dir and +# mi_gdb_load, so we can safely use those. +# +# The goal is not to test gdb functionality, which is done by other tests, +# but the command syntax and correct output response to MI operations. +# + +load_lib mi-support.exp +set MIFLAGS "-i=mi2" + +gdb_exit +if [mi_gdb_start] { + continue +} + +set testfile "mi-read-memory" +set srcfile ${testfile}.c +set binfile ${objdir}/${subdir}/${testfile} +if { [gdb_compile "${srcdir}/${subdir}/${srcfile}" "${binfile}" executable {debug additional_flags=-DFAKEARGV}] != "" } { + gdb_suppress_entire_file "Testcase compile failed, so all tests in this file will automatically fail." +} + + +mi_run_to_main +mi_next_to "main" "" "mi-read-memory.c" "20" "next at main" + +mi_gdb_test "1-data-read-memory" \ + "1\\^error,msg=\".*\"" \ + "no arguments" + + +mi_gdb_test "2-data-read-memory bytes x 1 3 2" \ + "2\\^done,addr=\"$hex\",nr-bytes=\"6\",total-bytes=\"6\",next-row=\"$hex\",prev-row=\"$hex\",next-page=\"$hex\",prev-page=\"$hex\",memory=\\\[{addr=\"$hex\",data=\\\[\"0x00\",\"0x01\"\\\]},{addr=\"$hex\",data=\\\[\"0x02\",\"0x03\"\\\]},{addr=\"$hex\",data=\\\[\"0x04\",\"0x05\"\\\]}\\\]" \ + "3x2, one byte" + + +mi_gdb_test "9-data-read-memory -o -6 -- -0+bytes+6 x 1 3 2" \ + "9\\^done,addr=\"$hex\",nr-bytes=\"6\",total-bytes=\"6\",next-row=\"$hex\",prev-row=\"$hex\",next-page=\"$hex\",prev-page=\"$hex\",memory=\\\[{addr=\"$hex\",data=\\\[\"0x00\",\"0x01\"\\\]},{addr=\"$hex\",data=\\\[\"0x02\",\"0x03\"\\\]},{addr=\"$hex\",data=\\\[\"0x04\",\"0x05\"\\\]}\\\]" \ + "3x2, one byte offset by -6" + + +mi_gdb_test "3-data-read-memory \"(shorts + 128)\" x 2 1 2" \ + "3\\^done,addr=\"$hex\",nr-bytes=\"4\",total-bytes=\"4\",next-row=\"$hex\",prev-row=\"$hex\",next-page=\"$hex\",prev-page=\"$hex\",memory=\\\[{addr=\"$hex\",data=\\\[\"0x0100\",\"0x0102\"\\\]}\\\]" \ + "expression in quotes" + + +mi_gdb_test "4-data-read-memory bytes+16 x 1 8 4 x" \ + "4\\^done,addr=\"$hex\",nr-bytes=\"32\",total-bytes=\"32\",next-row=\"$hex\",prev-row=\"$hex\",next-page=\"$hex\",prev-page=\"$hex\",memory=\\\[{addr=\"$hex\",data=\\\[\"0x10\",\"0x11\",\"0x12\",\"0x13\"\\\],ascii=\"xxxx\"},{addr=\"$hex\",data=\\\[\"0x14\",\"0x15\",\"0x16\",\"0x17\"\\\],ascii=\"xxxx\"},{addr=\"$hex\",data=\\\[\"0x18\",\"0x19\",\"0x1a\",\"0x1b\"\\\],ascii=\"xxxx\"},{addr=\"$hex\",data=\\\[\"0x1c\",\"0x1d\",\"0x1e\",\"0x1f\"\\\],ascii=\"xxxx\"},{addr=\"$hex\",data=\\\[\"0x20\",\"0x21\",\"0x22\",\"0x23\"\\\],ascii=\" !\\\\\"#\"},{addr=\"$hex\",data=\\\[\"0x24\",\"0x25\",\"0x26\",\"0x27\"\\\],ascii=\"\\$%&'\"},{addr=\"$hex\",data=\\\[\"0x28\",\"0x29\",\"0x2a\",\"0x2b\"\\\],ascii=\"().+\"},{addr=\"$hex\",data=\\\[\"0x2c\",\"0x2d\",\"0x2e\",\"0x2f\"\\\],ascii=\",-\./\"}\\\]" \ + "ascii and data" + + +mi_gdb_test "5-data-read-memory shorts+64 d 2 1 1" \ + "5\\^done,addr=\"$hex\",nr-bytes=\"2\",total-bytes=\"2\",next-row=\"$hex\",prev-row=\"$hex\",next-page=\"$hex\",prev-page=\"$hex\",memory=\\\[{addr=\"$hex\",data=\\\[\"128\"\\\]}\\\]" \ + "decimal" + +mi_gdb_test "6-data-read-memory shorts+64 o 2 1 1" \ + "6\\^done,addr=\"$hex\",nr-bytes=\"2\",total-bytes=\"2\",next-row=\"$hex\",prev-row=\"$hex\",next-page=\"$hex\",prev-page=\"$hex\",memory=\\\[{addr=\"$hex\",data=\\\[\"0200\"\\\]}\\\]" \ + "octal" + + +mi_gdb_exit +return 0 diff --git a/gdb/testsuite/gdb.mi/mi2-regs.exp b/gdb/testsuite/gdb.mi/mi2-regs.exp new file mode 100644 index 0000000..a14b241 --- /dev/null +++ b/gdb/testsuite/gdb.mi/mi2-regs.exp @@ -0,0 +1,129 @@ +# Copyright 1999, 2000, 2002 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# Please email any bugs, comments, and/or additions to this file to: +# bug-gdb@prep.ai.mit.edu +# +# Test essential Machine interface (MI) operations +# +# Verify that, using the MI, we can run a simple program and look at registers. +# +# The goal is not to test gdb functionality, which is done by other tests, +# but to verify the correct output response to MI operations. +# + + +load_lib mi-support.exp +set MIFLAGS "-i=mi2" + +gdb_exit +if [mi_gdb_start] { + continue +} + +set testfile "basics" +set srcfile ${testfile}.c +set binfile ${objdir}/${subdir}/${testfile} +if { [gdb_compile "${srcdir}/${subdir}/${srcfile}" "${binfile}" executable {debug additional_flags=-DFAKEARGV}] != "" } { + gdb_suppress_entire_file "Testcase compile failed, so all tests in this file will automatically fail." +} + +mi_delete_breakpoints +mi_gdb_reinitialize_dir $srcdir/$subdir +mi_gdb_load ${binfile} + +proc sparc_register_tests_no_exec { } { + # Test the generic IDT chip. + mi_gdb_test "111-data-list-register-values" \ + ".*111\\^error,msg=\"mi_cmd_data_list_register_values: Usage: -data-list-register-values \\\[...\\\]\"" \ + "wrong arguments" + + mi_gdb_test "111-data-list-register-values x" \ + ".*111\\^error,msg=\"mi_cmd_data_list_register_values: No registers\.\"" \ + "no executable" +} + +# These tests exercise IDT-specific MIPS registers for several +# different processor models. + +# This should detect the actual processor in use and change +# the expected results appropriately. FIXME + +proc sparc_register_tests { } { + global hex + global decimal + set octal "\[0-7\]+" + set binary "\[0-1\]+" + set float "\\-?((\[0-9\]+(\\.\[0-9\]+)?(e\[-+\]\[0-9\]+)?)|(nan\\($hex\\)))" + set float2 "\\-?\[0-9\]+" + + mi_gdb_test "111-data-list-register-names" \ + "111\\^done,register-names=\\\[\"g0\",\"g1\",\"g2\",\"g3\",\"g4\",\"g5\",\"g6\",\"g7\",\"o0\",\"o1\",\"o2\",\"o3\",\"o4\",\"o5\",\"sp\",\"o7\",\"l0\",\"l1\",\"l2\",\"l3\",\"l4\",\"l5\",\"l6\",\"l7\",\"i0\",\"i1\",\"i2\",\"i3\",\"i4\",\"i5\",\"fp\",\"i7\",\"f0\",\"f1\",\"f2\",\"f3\",\"f4\",\"f5\",\"f6\",\"f7\",\"f8\",\"f9\",\"f10\",\"f11\",\"f12\",\"f13\",\"f14\",\"f15\",\"f16\",\"f17\",\"f18\",\"f19\",\"f20\",\"f21\",\"f22\",\"f23\",\"f24\",\"f25\",\"f26\",\"f27\",\"f28\",\"f29\",\"f30\",\"f31\",\"y\",\"psr\",\"wim\",\"tbr\",\"pc\",\"npc\",\"fpsr\",\"cpsr\"\\\]" \ + "list register names" + + mi_gdb_test "222-data-list-register-values x" \ + "222\\^done,register-values=\\\[\{number=\"0\",value=\"$hex\"\}.*\{number=\"71\",value=\"$hex\"\}\\\]" \ + "register values x" + + mi_gdb_test "333-data-list-register-values f" \ + "333\\^done,register-values=\\\[\{number=\"0\",value=\"$float\"\},\{number=\"1\",value=\"$float\"\},.*\{number=\"71\",value=\"$float\"\}\\\]" \ + "register values f" + + mi_gdb_test "444-data-list-register-values d" \ + "444\\^done,register-values=\\\[\{number=\"0\",value=\"$decimal\"\}.*\{number=\"71\",value=\"$decimal\"\}\\\]" \ + "register values d" + + mi_gdb_test "555-data-list-register-values o" \ + "555\\^done,register-values=\\\[\{number=\"0\",value=\"$octal\"\}.*\{number=\"71\",value=\"$octal\"\}\\\]" \ + "register values o" + + mi_gdb_test "666-data-list-register-values t" \ + "666\\^done,register-values=\\\[\{number=\"0\",value=\"$binary\"\}.*\{number=\"71\",value=\"$binary\"\}\\\]" \ + "register values t" + + # On the sparc, registers 0-31 are int, 32-63 float, 64-71 int + + mi_gdb_test "777-data-list-register-values N" \ + "777\\^done,register-values=\\\[\{number=\"0\",value=\"$decimal\"\}.*\{number=\"31\",value=\"$decimal\"\},\{number=\"32\",value=\"$float\"\}.*\{number=\"63\",value=\"$float\"\},\{number=\"64\",value=\"$decimal\"\}.*\{number=\"71\",value=\"$decimal\"\}\\\]" \ + "register values N" + + mi_gdb_test "888-data-list-register-values r" \ + "888\\^done,register-values=\\\[\{number=\"0\",value=\"$hex\"\}.*\{number=\"71\",value=\"$hex\"\}\\\]" \ + "register values r" + + mi_gdb_test "999-data-list-register-names 68 69 70 71" \ + "999\\^done,register-names=\\\[\"pc\",\"npc\",\"fpsr\",\"cpsr\"\\\]" \ + "list names of some regs" + + mi_gdb_test "001-data-list-register-values x 68 69 70 71" \ + "001\\^done,register-values=\\\[\{number=\"68\",value=\"$hex\"\},\{number=\"69\",value=\"$hex\"\},\{number=\"70\",value=\"$hex\"\},\{number=\"71\",value=\"$hex\"\}\\\]" \ + "list values of some regs" + + mi_gdb_test "002-data-list-changed-registers" \ + "002\\^done,changed-registers=\\\[(\"${decimal}\"(,\"${decimal}\")*)?\\\]" \ + "list changed registers" +} + +if [istarget "sparc-*-*"] then { + sparc_register_tests_no_exec + mi_run_to_main + sparc_register_tests +} else { + verbose "mi-regs.exp tests ignored for this target" +} + +mi_gdb_exit +return 0 diff --git a/gdb/testsuite/gdb.mi/mi2-return.exp b/gdb/testsuite/gdb.mi/mi2-return.exp new file mode 100644 index 0000000..b54f15a --- /dev/null +++ b/gdb/testsuite/gdb.mi/mi2-return.exp @@ -0,0 +1,72 @@ +# Copyright 1999, 2000, 2002 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# Please email any bugs, comments, and/or additions to this file to: +# bug-gdb@prep.ai.mit.edu + +# Test Machine interface (MI) operations +# Verify that, using the MI, we can run a simple program and perform +# exec-return. + +# The goal is not to +# test gdb functionality, which is done by other tests, but to verify +# the correct output response to MI operations. +# + +load_lib mi-support.exp +set MIFLAGS "-i=mi2" + +gdb_exit +if [mi_gdb_start] { + continue +} + +set testfile "basics" +set srcfile ${testfile}.c +set binfile ${objdir}/${subdir}/${testfile} +if { [gdb_compile "${srcdir}/${subdir}/${srcfile}" "${binfile}" executable {debug additional_flags=-DFAKEARGV}] != "" } { + gdb_suppress_entire_file "Testcase compile failed, so all tests in this file will automatically fail." +} + +mi_delete_breakpoints +mi_gdb_reinitialize_dir $srcdir/$subdir +mi_gdb_reinitialize_dir $srcdir/$subdir +mi_gdb_load ${binfile} + + +proc test_return_simple {} { + global mi_gdb_prompt + global hex + + send_gdb "111-exec-return\n" + gdb_expect { + -re "111\\^done,frame=\{level=\"0\",addr=\"$hex\",func=\"callee3\",args=\\\[.*\\\],file=\".*basics.c\",line=\"18\"\}\r\n$mi_gdb_prompt$" {pass "return from callee4 now"} + -re ".*\r\n$mi_gdb_prompt$" { fail "return from callee4 now" } + timeout { fail "return from callee4 now (timeout)" + } + } +} + +mi_runto callee4 + +mi_gdb_test "205-break-delete" \ + "205\\^done.*" \ + "delete all breakpoints" + +test_return_simple + +mi_gdb_exit +return 0 diff --git a/gdb/testsuite/gdb.mi/mi2-simplerun.exp b/gdb/testsuite/gdb.mi/mi2-simplerun.exp new file mode 100644 index 0000000..93d4426 --- /dev/null +++ b/gdb/testsuite/gdb.mi/mi2-simplerun.exp @@ -0,0 +1,199 @@ +# Copyright 1999, 2000 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# Please email any bugs, comments, and/or additions to this file to: +# bug-gdb@prep.ai.mit.edu + +# +# Test essential Machine interface (MI) operations +# +# Verify that, using the MI, we can run a simple program and perform basic +# debugging activities like: insert breakpoints, run the program, +# step, next, continue until it ends and, last but not least, quit. +# +# The goal is not to test gdb functionality, which is done by other tests, +# but to verify the correct output response to MI operations. +# + +load_lib mi-support.exp +set MIFLAGS "-i=mi2" + +gdb_exit +if [mi_gdb_start] { + continue +} + +set testfile "basics" +set srcfile ${testfile}.c +set binfile ${objdir}/${subdir}/${testfile} +if { [gdb_compile "${srcdir}/${subdir}/${srcfile}" "${binfile}" executable {debug additional_flags=-DFAKEARGV}] != "" } { + gdb_suppress_entire_file "Testcase compile failed, so all tests in this file will automatically fail." +} + +mi_delete_breakpoints +mi_gdb_reinitialize_dir $srcdir/$subdir +mi_gdb_reinitialize_dir $srcdir/$subdir +mi_gdb_load ${binfile} + +proc test_breakpoints_creation_and_listing {} { + global mi_gdb_prompt + global srcfile + global hex + + # Insert some breakpoints and list them + # Also, disable some so they do not interfere with other tests + # Tests: + # -break-insert + # -break-list + # -break-disable + # -break-info + + mi_gdb_test "200-break-insert main" \ + "200\\^done,bkpt=\{number=\"1\",type=\"breakpoint\",disp=\"keep\",enabled=\"y\",addr=\"$hex\",func=\"main\",file=\".*basics.c\",line=\"32\",times=\"0\"\}" \ + "break-insert operation" + + mi_gdb_test "201-break-insert basics.c:callee2" \ + "201\\^done,bkpt=\{number=\"2\",type=\"breakpoint\",disp=\"keep\",enabled=\"y\",addr=\"$hex\",func=\"callee2\",file=\".*basics.c\",line=\"22\",times=\"0\"\}" \ + "insert breakpoint at basics.c:callee2" + + mi_gdb_test "202-break-insert basics.c:15" \ + "202\\^done,bkpt=\{number=\"3\",type=\"breakpoint\",disp=\"keep\",enabled=\"y\",addr=\"$hex\",func=\"callee3\",file=\".*basics.c\",line=\"15\",times=\"0\"\}" \ + "insert breakpoint at basics.c:15 (callee3)" + + mi_gdb_test "203-break-insert \"\\\"${srcfile}\\\":6\"" \ + "203\\^done,bkpt=\{number=\"4\",type=\"breakpoint\",disp=\"keep\",enabled=\"y\",addr=\"$hex\",func=\"callee4\",file=\".*basics.c\",line=\"6\",times=\"0\"\}" \ + "insert breakpoint at \"\":6 (callee4)" + + mi_gdb_test "204-break-list" \ + "204\\^done,BreakpointTable=\{.*,hdr=\\\[.*\\\],body=\\\[bkpt=\{number=\"1\",type=\"breakpoint\",disp=\"keep\",enabled=\"y\",addr=\"$hex\",func=\"main\",file=\".*basics.c\",line=\"32\",times=\"0\"\},.*\}\\\]\}" \ + "list of breakpoints" + + mi_gdb_test "205-break-disable 2 3 4" \ + "205\\^done.*" \ + "disabling of breakpoints" + + mi_gdb_test "206-break-info 2" \ + "206\\^done,BreakpointTable=\{.*,hdr=\\\[.*\\\],body=\\\[bkpt=\{number=\"2\",.*,enabled=\"n\",.*\}\\\]\}" \ + "list of breakpoints, 16 disabled" +} + +proc test_running_the_program {} { + global mi_gdb_prompt + global hex + + # Run the program without args, then specify srgs and rerun the program + # Tests: + # -exec-run + # -gdb-set + + # mi_gdb_test cannot be used for asynchronous commands because there are + # two prompts involved and this can lead to a race condition. + # The following is equivalent to a send_gdb "000-exec-run\n" + mi_run_cmd + gdb_expect { + -re "000\\*stopped,reason=\"breakpoint-hit\",bkptno=\"1\",thread-id=\"\[01\]\",frame=\{addr=\"$hex\",func=\"main\",args=\\\[\\\],file=\".*basics.c\",line=\"32\"\}\r\n$mi_gdb_prompt$" { + pass "run to main" + } + -re ".*$mi_gdb_prompt$" { + fail "run to main (2)" + } + timeout { + fail "run to main (timeout)" + } + } +} + +proc test_controlled_execution {} { + global mi_gdb_prompt + global hex + + # Continue execution until a breakpoint is reached, step into calls, verifying + # if the arguments are correctly shown, continue to the end of a called + # function, step over a call (next). + # Tests: + # -exec-continue + # -exec-next + # -exec-step + # -exec-finish + + mi_next_to "main" "" "basics.c" "33" "next at main" + + # FIXME: A string argument is not printed right; should be fixed and + # we should look for the right thing here. + # NOTE: The ``\\\\\"'' is for \". + mi_step_to "callee1" \ + "\{name=\"intarg\",value=\"2\"\},\{name=\"strarg\",value=\"$hex \\\\\"A string argument\.\\\\\"\"\},\{name=\"fltarg\",value=\"3.5\"\}" \ + "basics.c" "27" "step at main" + + # FIXME: A string argument is not printed right; should be fixed and + # we should look for the right thing here. + mi_execute_to "exec-step 3" "end-stepping-range" "callee4" "" \ + "basics.c" "8" "" "step to callee4" + + # FIXME: A string argument is not printed right; should be fixed and + # we should look for the right thing here. + # NOTE: The ``.'' is part of ``gdb-result-var="$1"'' + mi_finish_to "callee3" ".*" "basics.c" "18" ".1" "0" "exec-finish" +} + +proc test_controlling_breakpoints {} { + global mi_gdb_prompt + + # Enable, delete, set ignore counts in breakpoints + # (disable was already tested above) + # Tests: + # -break-delete + # -break-enable + # -break-after + # -break-condition + +} + +proc test_program_termination {} { + global mi_gdb_prompt + + # Run to completion: normal and forced + # Tests: + # -exec-abort + # (normal termination of inferior) + + # FIXME: "stopped" doesn't seem appropriate. + # mi_gdb_test cannot be used for asynchronous commands because there are + # two prompts involved and this can lead to a race condition. + send_gdb "999-exec-continue\n" + gdb_expect { + -re "999\\^running\r\n$mi_gdb_prompt" { + gdb_expect { + -re "999\\*stopped,reason=\"exited-normally\"\r\n$mi_gdb_prompt$" { + pass "continue to end" + } + -re ".*$mi_gdb_prompt$" {fail "continue to end (2)"} + timeout {fail "continue to end (timeout 2)"} + } + } + -re ".*$mi_gdb_prompt$" {fail "continue to end (1)"} + timeout {fail "continue to end (timeout 1)"} + } +} + +test_breakpoints_creation_and_listing +test_running_the_program +test_controlled_execution +test_controlling_breakpoints +test_program_termination + +mi_gdb_exit +return 0 diff --git a/gdb/testsuite/gdb.mi/mi2-stack.exp b/gdb/testsuite/gdb.mi/mi2-stack.exp new file mode 100644 index 0000000..f0a4a61 --- /dev/null +++ b/gdb/testsuite/gdb.mi/mi2-stack.exp @@ -0,0 +1,203 @@ +# Copyright 2000, 2002 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# Please email any bugs, comments, and/or additions to this file to: +# bug-gdb@prep.ai.mit.edu + +# +# Test essential Machine interface (MI) operations +# +# Verify that stack commands work. + +# The goal is not to test gdb functionality, which is done by other tests, +# but to verify the correct output response to MI operations. +# + +load_lib mi-support.exp +set MIFLAGS "-i=mi2" + +gdb_exit +if [mi_gdb_start] { + continue +} + +set testfile "basics" +set srcfile ${testfile}.c +set binfile ${objdir}/${subdir}/${testfile} +if { [gdb_compile "${srcdir}/${subdir}/${srcfile}" "${binfile}" executable {debug additional_flags=-DFAKEARGV}] != "" } { + gdb_suppress_entire_file "Testcase compile failed, so all tests in this file will automatically fail." +} + +mi_delete_breakpoints +mi_gdb_reinitialize_dir $srcdir/$subdir +mi_gdb_reinitialize_dir $srcdir/$subdir +mi_gdb_load ${binfile} + +proc test_stack_frame_listing {} { + global mi_gdb_prompt + global hex + + # Obtain a stack trace + # Tests: + # -stack-list-frames + # -stack-list-frames 1 1 + # -stack-list-frames 1 3 + + mi_gdb_test "231-stack-list-frames" \ + "231\\^done,stack=\\\[frame=\{level=\"0\",addr=\"$hex\",func=\"callee4\",file=\".*basics.c\",line=\"8\"\},frame=\{level=\"1\",addr=\"$hex\",func=\"callee3\",.*\},frame=\{level=\"2\",addr=\"$hex\",func=\"callee2\",.*\},frame=\{level=\"3\",addr=\"$hex\",func=\"callee1\",.*\},frame=\{level=\"4\",addr=\"$hex\",func=\"main\",.*\}\\\]" \ + "stack frame listing" + mi_gdb_test "232-stack-list-frames 1 1" \ + "232\\^done,stack=\\\[frame=\{level=\"1\",addr=\"$hex\",func=\"callee3\",.*\}\\\]" \ + "stack frame listing 1 1" + mi_gdb_test "233-stack-list-frames 1 3" \ + "233\\^done,stack=\\\[frame=\{level=\"1\",addr=\"$hex\",func=\"callee3\",.*\},frame=\{level=\"2\",addr=\"$hex\",func=\"callee2\",.*\},frame=\{level=\"3\",addr=\"$hex\",func=\"callee1\",.*\}\\\]" \ + "stack frame listing 1 3" + + mi_gdb_test "234-stack-list-frames 1" \ + "234\\^error,msg=\"mi_cmd_stack_list_frames: Usage.*FRAME_LOW FRAME_HIGH.*\"" \ + "stack frame listing wrong" +} + +proc test_stack_args_listing {} { + global mi_gdb_prompt + global hex + + # Obtain lists for args for the stack frames + # Tests: + # -stack-list-arguments 0 + # -stack-list-arguments 0 1 1 + # -stack-list-arguments 0 1 3 + # -stack-list-arguments 1 + # -stack-list-arguments 1 1 1 + # -stack-list-arguments 1 1 3 + # -stack-list-arguments + + mi_gdb_test "231-stack-list-arguments 0" \ + "231\\^done,stack-args=\\\[frame=\{level=\"0\",args=\\\[\\\]\},frame=\{level=\"1\",args=\\\[name=\"strarg\"\\\]\},frame=\{level=\"2\",args=\\\[name=\"intarg\",name=\"strarg\"\\\]\},frame=\{level=\"3\",args=\\\[name=\"intarg\",name=\"strarg\",name=\"fltarg\"\\\]\},frame=\{level=\"4\",args=\\\[\\\]\}\\\]" \ + "stack args listing 0" + + mi_gdb_test "232-stack-list-arguments 0 1 1" \ + "232\\^done,stack-args=\\\[frame=\{level=\"1\",args=\\\[name=\"strarg\"\\\]\}\\\]" \ + "stack args listing 0 1 1" + + mi_gdb_test "233-stack-list-arguments 0 1 3" \ + "233\\^done,stack-args=\\\[frame=\{level=\"1\",args=\\\[name=\"strarg\"\\\]\},frame=\{level=\"2\",args=\\\[name=\"intarg\",name=\"strarg\"\\\]\},frame=\{level=\"3\",args=\\\[name=\"intarg\",name=\"strarg\",name=\"fltarg\"\\\]\}\\\]" \ + "stack args listing 0 1 3" + + mi_gdb_test "231-stack-list-arguments 1" \ + "231\\^done,stack-args=\\\[frame=\{level=\"0\",args=\\\[\\\]\},frame=\{level=\"1\",args=\\\[\{name=\"strarg\",value=\"$hex \\\\\"A string argument.\\\\\"\"\}\\\]\},frame=\{level=\"2\",args=\\\[\{name=\"intarg\",value=\"2\"\},\{name=\"strarg\",value=\"$hex \\\\\"A string argument.\\\\\"\"\}\\\]\},frame=\{level=\"3\",args=\\\[\{name=\"intarg\",value=\"2\"\},\{name=\"strarg\",value=\"$hex \\\\\"A string argument.\\\\\"\"\},\{name=\"fltarg\",value=\"3.5\"\}\\\]\},frame=\{level=\"4\",args=\\\[\\\]\}\\\]" \ + "stack args listing 1" + + mi_gdb_test "232-stack-list-arguments 1 1 1" \ + "232\\^done,stack-args=\\\[frame=\{level=\"1\",args=\\\[\{name=\"strarg\",value=\"$hex \\\\\"A string argument.\\\\\"\"\}\\\]\}\\\]" \ + "stack args listing 1 1 1" + + mi_gdb_test "233-stack-list-arguments 1 1 3" \ + "233\\^done,stack-args=\\\[frame=\{level=\"1\",args=\\\[\{name=\"strarg\",value=\"$hex \\\\\"A string argument.\\\\\"\"\}\\\]\},frame=\{level=\"2\",args=\\\[\{name=\"intarg\",value=\"2\"\},\{name=\"strarg\",value=\"$hex \\\\\"A string argument.\\\\\"\"\}\\\]\},frame=\{level=\"3\",args=\\\[\{name=\"intarg\",value=\"2\"\},\{name=\"strarg\",value=\"$hex \\\\\"A string argument.\\\\\"\"\},\{name=\"fltarg\",value=\"3.5\"\}\\\]\}\\\]" \ + "stack args listing 1 1 3" + + mi_gdb_test "234-stack-list-arguments" \ + "234\\^error,msg=\"mi_cmd_stack_list_args: Usage.*PRINT_VALUES.*FRAME_LOW FRAME_HIGH.*\"" \ + "stack args listing wrong" +} + +proc test_stack_info_depth {} { + global mi_gdb_prompt + global hex + + # Obtain depth of stack + # Tests: + # -stack-info-depth + # -stack-info-depth 3 + # -stack-info-depth 99 + + mi_gdb_test "231-stack-info-depth" \ + "231\\^done,depth=\"5\"" \ + "stack info-depth" + + mi_gdb_test "231-stack-info-depth 3" \ + "231\\^done,depth=\"3\"" \ + "stack info-depth 3" + + mi_gdb_test "231-stack-info-depth 99" \ + "231\\^done,depth=\"5\"" \ + "stack info-depth 99" + + mi_gdb_test "231-stack-info-depth 99 99" \ + "231\\^error,msg=\"mi_cmd_stack_info_depth: Usage: .MAX_DEPTH.\"" \ + "stack info-depth wrong usage" +} + +proc test_stack_locals_listing {} { + global mi_gdb_prompt + global hex + + # Obtain lists for locals for the stack frames + # Tests: + # -stack-list-locals 0 + # -stack-list-locals 1 + # -stack-list-arguments + + mi_gdb_test "232-stack-list-locals 0" \ + "232\\^done,locals=\\\[name=\"A\",name=\"B\",name=\"C\"\\\]" \ + "stack locals listing 0" + +# step until A, B, C, have some reasonable values. +send_gdb "-exec-next 3\n" +gdb_expect { + -re "\\^running\r\n${mi_gdb_prompt}\\*stopped,reason=\"end-stepping-range\",thread-id=\"\[01\]\",frame=\{addr=\"$hex\",func=\"callee4\",args=\\\[\\\],file=\".*basics.c\",line=\"13\"\}\r\n$mi_gdb_prompt$" { + pass "next's in callee4" + } + timeout { fail "next in callee4 (timeout)" } +} + + mi_gdb_test "232-stack-list-locals 1" \ + "232\\^done,locals=\\\[\{name=\"A\",value=\"1\"\},\{name=\"B\",value=\"2\"\},\{name=\"C\",value=\"3\"\}\\\]" \ + "stack locals listing 1" + + mi_gdb_test "234-stack-list-locals" \ + "234\\^error,msg=\"mi_cmd_stack_list_locals: Usage.*PRINT_VALUES.*\"" \ + "stack locals listing wrong" + + mi_gdb_test "232-stack-select-frame 1" \ + "232\\^done" \ + "stack select frame 1" + + mi_gdb_test "232-stack-list-locals 1" \ + "232\\^done,locals=\\\[\\\]" \ + "stack locals listing for new frame" + +# this should be a no-op + + mi_gdb_test "232-stack-select-frame" \ + "232\\^done" \ + "stack select same frame" + + mi_gdb_test "232-stack-list-locals 1" \ + "232\\^done,locals=\\\[\\\]" \ + "stack locals for same frame (level 1)" + +} + +mi_runto callee4 +test_stack_frame_listing +test_stack_args_listing +test_stack_locals_listing +test_stack_info_depth + + +mi_gdb_exit +return 0 diff --git a/gdb/testsuite/gdb.mi/mi2-stepi.exp b/gdb/testsuite/gdb.mi/mi2-stepi.exp new file mode 100644 index 0000000..208b9e2 --- /dev/null +++ b/gdb/testsuite/gdb.mi/mi2-stepi.exp @@ -0,0 +1,86 @@ +# Copyright 1999, 2000, 2002 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# Please email any bugs, comments, and/or additions to this file to: +# bug-gdb@prep.ai.mit.edu + +# Test Machine interface (MI) operations +# Verify that, using the MI, we can run a simple program and perform +# exec-step-instruction and exec-next-instruction. + +# The goal is not to +# test gdb functionality, which is done by other tests, but to verify +# the correct output response to MI operations. +# + +load_lib mi-support.exp +set MIFLAGS "-i=mi2" + +gdb_exit +if [mi_gdb_start] { + continue +} + +set testfile "basics" +set srcfile ${testfile}.c +set binfile ${objdir}/${subdir}/${testfile} +if { [gdb_compile "${srcdir}/${subdir}/${srcfile}" "${binfile}" executable {debug additional_flags=-DFAKEARGV}] != "" } { + gdb_suppress_entire_file "Testcase compile failed, so all tests in this file will automatically fail." +} + +mi_delete_breakpoints +mi_gdb_reinitialize_dir $srcdir/$subdir +mi_gdb_reinitialize_dir $srcdir/$subdir +mi_gdb_load ${binfile} + +proc test_stepi_nexti {} { + global mi_gdb_prompt + global hex + + send_gdb "111-exec-step-instruction\n" + gdb_expect { + -re "111\\^running\r\n${mi_gdb_prompt}111\\*stopped,reason=\"end-stepping-range\",thread-id=\"\[01\]\",frame=\{addr=\"$hex\",func=\"main\",args=\\\[\\\],file=\".*basics.c\",line=\"3.\"\}\r\n$mi_gdb_prompt$" { + pass "step-instruction at main" + } + timeout { + fail "step-instruction at main (timeout)" + } + } + send_gdb "222-exec-next-instruction\n" + gdb_expect { + -re "222\\^running\r\n${mi_gdb_prompt}222\\*stopped,reason=\"end-stepping-range\",thread-id=\"\[01\]\",frame=\{addr=\"$hex\",func=\"main\",args=\\\[\\\],file=\".*basics.c\",line=\"3.\"\}\r\n$mi_gdb_prompt$" { + pass "next-instruction at main" + } + timeout { + fail "next-instruction at main (timeout)" + } + } + send_gdb "333-exec-next-instruction\n" + gdb_expect { + -re "333\\^running\r\n${mi_gdb_prompt}333\\*stopped,reason=\"end-stepping-range\",thread-id=\"\[01\]\",frame=\{addr=\"$hex\",func=\"main\",args=\\\[\\\],file=\".*basics.c\",line=\"3.\"\}\r\n$mi_gdb_prompt$" { + pass "next-instruction at main" + } + timeout { + fail "next-instruction at main (timeout)" + } + } +} + +mi_run_to_main +test_stepi_nexti + +mi_gdb_exit +return 0 diff --git a/gdb/testsuite/gdb.mi/mi2-syn-frame.exp b/gdb/testsuite/gdb.mi/mi2-syn-frame.exp new file mode 100644 index 0000000..263bb39 --- /dev/null +++ b/gdb/testsuite/gdb.mi/mi2-syn-frame.exp @@ -0,0 +1,111 @@ +# Copyright 2002, 2003 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# Please email any bugs, comments, and/or additions to this file to: +# bug-gdb@prep.ai.mit.edu + +# Test MI output with synthetic frames on the stack (call dummies, +# signal handlers). + +if [target_info exists gdb,nosignals] { + verbose "Skipping mi-syn-frame.exp because of nosignals." + continue +} + +load_lib mi-support.exp +set MIFLAGS "-i=mi2" + +set testfile "mi-syn-frame" +set srcfile ${testfile}.c +set binfile ${objdir}/${subdir}/${testfile} +if { [gdb_compile "${srcdir}/${subdir}/${srcfile}" "${binfile}" executable {debug additional_flags=-DFAKEARGV}] != "" } { + gdb_suppress_entire_file "Testcase compile failed, so all tests in this file will automatically fail." +} + +set my_mi_gdb_prompt "\\(gdb\\)\[ \]*\[\r\n\]*" + +mi_gdb_exit +mi_gdb_start +mi_delete_breakpoints +mi_gdb_reinitialize_dir $srcdir/$subdir +mi_gdb_load ${binfile} +mi_run_to_main + +mi_gdb_test "400-break-insert foo" "400\\^done,bkpt=\{number=\"2\",type=\"breakpoint\",disp=\"keep\",enabled=\"y\",addr=\"$hex\",func=\"foo\",file=\".*mi-syn-frame.c\",line=\"$decimal\",times=\"0\"\}" + + +# +# Call foo() by hand, where we'll hit a breakpoint. +# + +mi_gdb_test "401-data-evaluate-expression foo()" "\\&\"The program being debugged stopped while in a function called from GDB.\\\\n\"\[\r\n\]+\\&\"When the function \\(foo\\) is done executing, GDB will silently\\\\n\"\[\r\n\]+\\&\"stop \\(instead of continuing to evaluate the expression containing\\\\n\"\[\r\n\]+\\&\"the function call\\).\\\\n\"\[\r\n\]+401\\^error,msg=\"The program being debugged stopped while in a function called from GDB.*\"" "call inferior's function with a breakpoint set in it" + +mi_gdb_test "402-stack-list-frames" "402\\^done,reason=\"breakpoint-hit\",bkptno=\"2\",thread-id=\"$decimal\",frame=\{addr=\"$hex\",func=\"foo\",args=\\\[\\\],file=\".*mi-syn-frame.c\",line=\"$decimal\"\},stack=\\\[frame=\{level=\"0\",addr=\"$hex\",func=\"foo\",file=\".*mi-syn-frame.c\",line=\"$decimal\"\},frame=\{level=\"1\",addr=\"$hex\",func=\"\"\},frame=\{level=\"2\",addr=\"$hex\",func=\"main\",file=\".*mi-syn-frame.c\",line=\"$decimal\"\}.*\\\]" "backtrace from inferior function stopped at bp, showing gdb dummy frame" + +# +# Continue back to main() +# + +send_gdb "403-exec-continue\n" +gdb_expect { + -re "403\\^running\[\r\n\]+${my_mi_gdb_prompt}hi in foo\[\r\n\]+403\\\*stopped\[\r\n\]+${my_mi_gdb_prompt}$" { + pass "403-exec-continue" + } + timeout { + fail "403-exec-continue" + } +} + +mi_gdb_test "404-stack-list-frames 0 0" "404\\^done,stack=\\\[frame=\{level=\"0\",addr=\"$hex\",func=\"main\",file=\".*mi-syn-frame.c\",line=\"$decimal\"\}.*\\\]" + + +# +# Call have_a_very_merry_interrupt() which will eventually raise a signal +# that's caught by handler() which calls subroutine(). + +mi_gdb_test "405-break-insert subroutine" "405\\^done,bkpt=\{number=\"3\",type=\"breakpoint\",disp=\"keep\",enabled=\"y\",addr=\"$hex\",func=\"subroutine\",file=\".*mi-syn-frame.c\",line=\"$decimal\",times=\"0\"\}" + +mi_gdb_test "406-data-evaluate-expression have_a_very_merry_interrupt()" "Waiting to get a signal\[\r\n\]+\\&\"The program being debugged stopped while in a function called from GDB.\\\\n\"\[\r\n\]+\\&\"When the function \\(have_a_very_merry_interrupt\\) is done executing, GDB will silently\\\\n\"\[\r\n\]+\\&\"stop \\(instead of continuing to evaluate the expression containing\\\\n\"\[\r\n\]+\\&\"the function call\\).\\\\n\"\[\r\n\]+406\\^error,msg=\"The program being debugged stopped while in a function called from GDB.\\\\nWhen the function \\(have_a_very_merry_interrupt\\) is done executing, GDB will silently\\\\nstop \\(instead of continuing to evaluate the expression containing\\\\nthe function call\\).\"" + +# We should have both a signal handler and a call dummy frame +# in this next output. + +mi_gdb_test "407-stack-list-frames" "407\\^done,reason=\"breakpoint-hit\",bkptno=\"3\",thread-id=\"$decimal\",frame=\{addr=\"$hex\",func=\"subroutine\",args=\\\[\{name=\"in\",value=\"$decimal\"\}\\\],file=\".*mi-syn-frame.c\",line=\"$decimal\"\},stack=\\\[frame=\{level=\"0\",addr=\"$hex\",func=\"subroutine\",file=\".*mi-syn-frame.c\",line=\"$decimal\"\},frame=\{level=\"1\",addr=\"$hex\",func=\"handler\",file=\".*mi-syn-frame.c\",line=\"$decimal\"\},frame=\{level=\"2\",addr=\"$hex\",func=\"\"\},.*frame=\{level=\"$decimal\",addr=\"$hex\",func=\"have_a_very_merry_interrupt\",file=\".*mi-syn-frame.c\",line=\"$decimal\"\},frame=\{level=\"$decimal\",addr=\"$hex\",func=\"\"\},frame=\{level=\"$decimal\",addr=\"$hex\",func=\"main\",file=\".*mi-syn-frame.c\",line=\"$decimal\"\}.*\\\]" + + +send_gdb "408-exec-continue\n" +gdb_expect { + -re "408\\^running\[\r\n\]+${my_mi_gdb_prompt}408\\\*stopped\[\r\n\]+${my_mi_gdb_prompt}$" { + pass "408-exec-continue" + } + timeout { + fail "408-exec-continue" + } +} + +mi_gdb_test "409-stack-list-frames 0 0" "409\\^done,stack=\\\[frame=\{level=\"0\",addr=\"$hex\",func=\"main\",file=\".*mi-syn-frame.c\",line=\"$decimal\"\}.*\\\]" + +# +# Call bar() by hand, which should get an exception while running. +# + +mi_gdb_test "410-data-evaluate-expression bar()" "hi in bar\[\r\n\]+\\&\"The program being debugged was signaled while in a function called from GDB.\\\\n\"\[\r\n\]+\\&\"GDB remains in the frame where the signal was received.\\\\n\"\[\r\n\]+\\&\"To change this behavior use \\\\\"set unwindonsignal on\\\\\"\\\\n\"\[\r\n\]+\\&\"Evaluation of the expression containing the function \\(bar\\) will be abandoned.\\\\n\"\[\r\n\]+410\\^error,msg=\"The program being debugged was signaled while in a function called from GDB.\\\\nGDB remains in the frame where the signal was received.\\\\nTo change this behavior use \\\\\"set unwindonsignal on\\\\\"\\\\nEvaluation of the expression containing the function \\(bar\\) will be abandoned.\"" "call inferior function which raises exception" + +mi_gdb_test "411-stack-list-frames" "411\\^done,reason=\"signal-received\",signal-name=\".*\",signal-meaning=\".*\",thread-id=\"$decimal\",frame=\{addr=\"$hex\",func=\"bar\",args=\\\[\\\],file=\".*mi-syn-frame.c\",line=\"$decimal\"\},stack=\\\[frame=\{level=\"0\",addr=\"$hex\",func=\"bar\",file=\".*mi-syn-frame.c\",line=\"$decimal\"},frame=\{level=\"1\",addr=\"$hex\",func=\"\"\},frame=\{level=\"2\",addr=\"$hex\",func=\"main\",file=\".*mi-syn-frame.c\",line=\"$decimal\"}.*\\\]" "backtrace from inferior function at exception" + +mi_gdb_exit + +return 0 diff --git a/gdb/testsuite/gdb.mi/mi2-until.exp b/gdb/testsuite/gdb.mi/mi2-until.exp new file mode 100644 index 0000000..4ef296c --- /dev/null +++ b/gdb/testsuite/gdb.mi/mi2-until.exp @@ -0,0 +1,127 @@ +# Copyright 1999, 2000 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# Please email any bugs, comments, and/or additions to this file to: +# bug-gdb@prep.ai.mit.edu + +# Test Machine interface (MI) operations +# Verify that, using the MI, we can run a simple program and perform +# exec-until. + +# The goal is not to +# test gdb functionality, which is done by other tests, but to verify +# the correct output response to MI operations. +# + +load_lib mi-support.exp +set MIFLAGS "-i=mi2" + +gdb_exit +if [mi_gdb_start] { + continue +} + +set testfile "until" +set srcfile ${testfile}.c +set binfile ${objdir}/${subdir}/${testfile} +if { [gdb_compile "${srcdir}/${subdir}/${srcfile}" "${binfile}" executable {debug additional_flags=-DFAKEARGV}] != "" } { + gdb_suppress_entire_file "Testcase compile failed, so all tests in this file will automatically fail." +} + +mi_delete_breakpoints +mi_gdb_reinitialize_dir $srcdir/$subdir +mi_gdb_reinitialize_dir $srcdir/$subdir +mi_gdb_load ${binfile} + +proc test_running_to_foo {} { + global mi_gdb_prompt + global hex + + mi_gdb_test "200-break-insert 10" \ + "200\\^done,bkpt=\{number=\"1\",type=\"breakpoint\",disp=\"keep\",enabled=\"y\",addr=\"$hex\",func=\"foo\",file=\".*until.c\",line=\"10\",times=\"0\"\}" \ + "break-insert operation" + + mi_run_cmd + + gdb_expect { + -re "000\\*stopped,reason=\"breakpoint-hit\",bkptno=\"1\",thread-id=\"\[01\]\",frame=\{addr=\"$hex\",func=\"foo\",args=\\\[\\\],file=\".*until.c\",line=\"10\"\}\r\n$mi_gdb_prompt$" { + pass "run to main" + } + -re ".*$mi_gdb_prompt$" { + fail "run to main (2)" + } + timeout { + fail "run to main (timeout)" + } + } + + mi_gdb_test "100-break-delete 1" "100\\^done" "break-delete 1" + +} + +proc test_until {} { + global mi_gdb_prompt + global hex + + send_gdb "111-exec-until\n" + gdb_expect { + -re "111\\^running\r\n${mi_gdb_prompt}111\\*stopped,reason=\"end-stepping-range\",thread-id=\"\[01\]\",frame=\{addr=\"$hex\",func=\"foo\",args=\\\[\\\],file=\".*until.c\",line=\"12\"\}\r\n$mi_gdb_prompt$" { + pass "until after while loop" + } + timeout { + fail "until after while loop (timeout)" + } + } + + send_gdb "222-exec-until 15\n" + gdb_expect { + -re "222\\^running\r\n${mi_gdb_prompt}222\\*stopped,reason=\"location-reached\",thread-id=\"\[01\]\",frame=\{addr=\"$hex\",func=\"foo\",args=\\\[\\\],file=\".*until.c\",line=\"15\"\}\r\n$mi_gdb_prompt$" { + pass "until line number" + } + timeout { + fail "until line number (timeout)" + } + } + + send_gdb "333-exec-until until.c:17\n" + gdb_expect { + -re "333\\^running\r\n${mi_gdb_prompt}333\\*stopped,reason=\"location-reached\",thread-id=\"\[01\]\",frame=\{addr=\"$hex\",func=\"foo\",args=\\\[\\\],file=\".*until.c\",line=\"17\"\}\r\n$mi_gdb_prompt$" { + pass "until line number:file" + } + timeout { + fail "until line number:file (timeout)" + } + } + + # This is supposed to NOT stop at line 25. It stops right after foo is over. + + send_gdb "444-exec-until until.c:25\n" + gdb_expect { + -re "444\\^running\r\n${mi_gdb_prompt}444\\*stopped,reason=\"location-reached\",thread-id=\"\[01\]\",frame=\{addr=\"$hex\",func=\"main\",args=\\\[\\\],file=\".*until.c\",line=\"24\"\}\r\n$mi_gdb_prompt$" { + pass "until after current function" + } + timeout { + fail "until after current function (timeout)" + } + } + +} + +test_running_to_foo +test_until + +mi_gdb_exit +return 0 diff --git a/gdb/testsuite/gdb.mi/mi2-var-block.exp b/gdb/testsuite/gdb.mi/mi2-var-block.exp new file mode 100644 index 0000000..84bc1ff --- /dev/null +++ b/gdb/testsuite/gdb.mi/mi2-var-block.exp @@ -0,0 +1,173 @@ +# Copyright (C) 1999, 2000, 2002 Free Software Foundation, Inc. +# +# This Program Is Free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# Please email any bugs, comments, and/or additions to this file to: +# bug-gdb@prep.ai.mit.edu + +# Test essential Machine interface (MI) operations +# +# Verify that, using the MI, we can create, update, delete variables. +# + + +load_lib mi-support.exp +set MIFLAGS "-i=mi2" + +gdb_exit +if [mi_gdb_start] { + continue +} + +set testfile "var-cmd" +set srcfile ${testfile}.c +set binfile ${objdir}/${subdir}/${testfile} +if { [gdb_compile "${srcdir}/${subdir}/${srcfile}" "${binfile}" executable {debug additional_flags=-DFAKEARGV}] != "" } { + gdb_suppress_entire_file "Testcase compile failed, so all tests in this file will automatically fail." +} + +mi_delete_breakpoints +mi_gdb_reinitialize_dir $srcdir/$subdir +mi_gdb_load ${binfile} + +mi_runto do_block_tests + +# Test: c_variable-3.2 +# Desc: create cb and foo +mi_gdb_test "-var-create cb * cb" \ + "\\^done,name=\"cb\",numchild=\"0\",type=\"int\"" \ + "create local variable cb" + +mi_gdb_test "-var-create foo * foo" \ + "&\"mi_cmd_var_create: unable to create variable object\\\\n\".*\\^error,msg=\"mi_cmd_var_create: unable to create variable object\"" \ + "create local variable foo" + +# step to "foo = 123;" +mi_step_to "do_block_tests" "" "var-cmd.c" "158" "step at do_block_test" + + +# Be paranoid and assume 3.2 created foo +mi_gdb_test "-var-delete foo" \ + "&\"Variable object not found\\\\n\".*\\^error,msg=\"Variable object not found\"" \ + "delete var foo" + + +# Test: c_variable-3.3 +# Desc: create foo +mi_gdb_test "-var-create foo * foo" \ + "\\^done,name=\"foo\",numchild=\"0\",type=\"int\"" \ + "create local variable foo" + +# step to "foo2 = 123;" +mi_step_to "do_block_tests" "" "var-cmd.c" "161" "step at do_block_test" + +# Test: c_variable-3.4 +# Desc: check foo, cb changed +mi_gdb_test "-var-update *" \ + "\\^done,changelist=\\\[\{name=\"foo\",in_scope=\"true\",type_changed=\"false\"\},\{name=\"cb\",in_scope=\"true\",type_changed=\"false\"\}\\\]" \ + "update all vars: cb foo changed" + +# step to "foo = 321;" +mi_step_to "do_block_tests" "" "var-cmd.c" "164" "step at do_block_test" + +# Test: c_variable-3.5 +# Desc: create inner block foo +mi_gdb_test "-var-create inner_foo * foo" \ + "\\^done,name=\"inner_foo\",numchild=\"0\",type=\"int\"" \ + "create local variable inner_foo" + +# step to "foo2 = 0;" +mi_step_to "do_block_tests" "" "var-cmd.c" "166" "step at do_block_test" + +# Test: c_variable-3.6 +# Desc: create foo2 +mi_gdb_test "-var-create foo2 * foo2" \ + "\\^done,name=\"foo2\",numchild=\"0\",type=\"int\"" \ + "create local variable foo2" + +# Test: c_variable-3.7 +# Desc: check that outer foo in scope and inner foo out of scope +# Note: also a known gdb problem +setup_xfail *-*-* +mi_gdb_test "-var-update inner_foo" \ + "\\^done,changelist=\{FIXME\}" \ + "update inner_foo: should be out of scope: KNOWN PROBLEM" +clear_xfail *-*-* + +setup_xfail *-*-* +mi_gdb_test "-var-evaluate-expression inner_foo" \ + "\\^done,value=\{FIXME\}" \ + "evaluate inner_foo: should be out of scope: KNOWN PROBLEM" +clear_xfail *-*-* + +mi_gdb_test "-var-update foo" \ + "\\^done,changelist=\\\[\\\]" \ + "update foo: did not change" + +mi_gdb_test "-var-delete inner_foo" \ + "\\^done,ndeleted=\"1\"" \ + "delete var inner_foo" + +# step to "foo = 0;" +mi_step_to "do_block_tests" "" "var-cmd.c" "168" "step at do_block_test" + +# Test: c_variable-3.8 +# Desc: check that foo2 out of scope (known gdb problem) +setup_xfail *-*-* +mi_gdb_test "-var-update foo2" \ + "\\^done,changelist=\{FIXME\}" \ + "update foo2: should be out of scope: KNOWN PROBLEM" +clear_xfail *-*-* + +# step to "cb = 21;" +mi_step_to "do_block_tests" "" "var-cmd.c" "171" "step at do_block_test" + +# Test: c_variable-3.9 +# Desc: check that only cb is in scope (known gdb problem) +setup_xfail *-*-* +mi_gdb_test "-var-update foo2" \ + "\\^done,changelist=\\\[FIXME\\\]" \ + "update foo2 should be out of scope: KNOWN PROBLEM" +clear_xfail *-*-* +setup_xfail *-*-* +mi_gdb_test "-var-update foo" \ + "\\^done,changelist=\{FIXME\}" \ + "update foo should be out of scope: KNOWN PROBLEM" +clear_xfail *-*-* +mi_gdb_test "-var-update cb" \ + "\\^done,changelist=\\\[\\\]" \ + "update cb" + +# Test: c_variable-3.10 +# Desc: names of editable variables +#gdbtk_test c_variable-3.10 {names of editable variables} { +# editable_variables +#} {{foo cb foo2} {}} + +# Done with block tests +mi_gdb_test "-var-delete foo" \ + "\\^done,ndeleted=\"1\"" \ + "delete var foo" + +mi_gdb_test "-var-delete foo2" \ + "\\^done,ndeleted=\"1\"" \ + "delete var foo2" + +mi_gdb_test "-var-delete cb" \ + "\\^done,ndeleted=\"1\"" \ + "delete var cb" + +mi_gdb_exit +return 0 diff --git a/gdb/testsuite/gdb.mi/mi2-var-child.exp b/gdb/testsuite/gdb.mi/mi2-var-child.exp new file mode 100644 index 0000000..3f6a3fd --- /dev/null +++ b/gdb/testsuite/gdb.mi/mi2-var-child.exp @@ -0,0 +1,1203 @@ +# Copyright (C) 1999, 2000, 2002 Free Software Foundation + +# This Program Is Free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# Please email any bugs, comments, and/or additions to this file to: +# bug-gdb@prep.ai.mit.edu + +# Test essential Machine interface (MI) operations +# +# Verify that, using the MI, we can create, update, delete variables. +# + + +load_lib mi-support.exp +set MIFLAGS "-i=mi2" + +gdb_exit +if [mi_gdb_start] { + continue +} + +set testfile "var-cmd" +set srcfile ${testfile}.c +set binfile ${objdir}/${subdir}/${testfile} +if { [gdb_compile "${srcdir}/${subdir}/${srcfile}" "${binfile}" executable {debug additional_flags=-DFAKEARGV}] != "" } { + gdb_suppress_entire_file "Testcase compile failed, so all tests in this file will automatically fail." +} + +mi_delete_breakpoints +mi_gdb_reinitialize_dir $srcdir/$subdir +mi_gdb_load ${binfile} + +mi_runto do_children_tests + +##### ##### +# # +# children tests # +# # +##### ##### + + +# Test: c_variable-4.2 +# Desc: create variable "struct_declarations" +mi_gdb_test "-var-create struct_declarations * struct_declarations" \ + "\\^done,name=\"struct_declarations\",numchild=\"11\",type=\"struct _struct_decl\"" \ + "create local variable struct_declarations" + +# Test: c_variable-4.3 +# Desc: children of struct_declarations +# STABS doesn't give us argument types for the func ptr structs, but +# Dwarf 2 does. +mi_gdb_test "-var-list-children struct_declarations" \ + "\\^done,numchild=\"11\",children=\\\[child=\{name=\"struct_declarations.integer\",exp=\"integer\",numchild=\"0\",type=\"int\"\},child=\{name=\"struct_declarations.character\",exp=\"character\",numchild=\"0\",type=\"char\"\},child={name=\"struct_declarations.char_ptr\",exp=\"char_ptr\",numchild=\"1\",type=\"char \\*\"\},child=\{name=\"struct_declarations.long_int\",exp=\"long_int\",numchild=\"0\",type=\"long int\"\},child=\{name=\"struct_declarations.int_ptr_ptr\",exp=\"int_ptr_ptr\",numchild=\"1\",type=\"int \\*\\*\"\},child=\{name=\"struct_declarations.long_array\",exp=\"long_array\",numchild=\"10\",type=\"long int \\\[10\\\]\"\},child=\{name=\"struct_declarations.func_ptr\",exp=\"func_ptr\",numchild=\"0\",type=\"void \\(\\*\\)\\((void)?\\)\"\},child=\{name=\"struct_declarations.func_ptr_struct\",exp=\"func_ptr_struct\",numchild=\"0\",type=\"struct _struct_decl \\(\\*\\)\\((int, char \\*, long int)?\\)\"\},child=\{name=\"struct_declarations.func_ptr_ptr\",exp=\"func_ptr_ptr\",numchild=\"0\",type=\"struct _struct_decl \\*\\(\\*\\)\\((int, char \\*, long int)?\\)\"\},child=\{name=\"struct_declarations.u1\",exp=\"u1\",numchild=\"4\",type=\"union \{\\.\\.\\.\}\"\},child=\{name=\"struct_declarations.s2\",exp=\"s2\",numchild=\"4\",type=\"struct \{\\.\\.\\.\}\"\}\\\]" \ + "get children of struct_declarations" + +#gdbtk_test c_variable-4.3 {children of struct_declarations} { +# get_children struct_declarations +#} {integer character char_ptr long_int int_ptr_ptr long_array func_ptr func_ptr_struct func_ptr_ptr u1 s2} + +# Test: c_variable-4.4 +# Desc: number of children of struct_declarations +mi_gdb_test "-var-info-num-children struct_declarations" \ + "\\^done,numchild=\"11\"" \ + "get number of children of struct_declarations" + +# Test: c_variable-4.5 +# Desc: children of struct_declarations.integer +mi_gdb_test "-var-list-children struct_declarations.integer" \ + "\\^done,numchild=\"0\"" \ + "get children of struct_declarations.integer" + +# Test: c_variable-4.6 +# Desc: number of children of struct_declarations.integer +mi_gdb_test "-var-info-num-children struct_declarations.integer" \ + "\\^done,numchild=\"0\"" \ + "get number of children of struct_declarations.integer" + +# Test: c_variable-4.7 +# Desc: children of struct_declarations.character +mi_gdb_test "-var-list-children struct_declarations.character" \ + "\\^done,numchild=\"0\"" \ + "get children of struct_declarations.character" + +# Test: c_variable-4.8 +# Desc: number of children of struct_declarations.character +mi_gdb_test "-var-info-num-children struct_declarations.character" \ + "\\^done,numchild=\"0\"" \ + "get number of children of struct_declarations.character" + +# Test: c_variable-4.9 +# Desc: children of struct_declarations.char_ptr +mi_gdb_test "-var-list-children struct_declarations.char_ptr" \ + "\\^done,numchild=\"1\",children=\\\[child=\{name=\"struct_declarations.char_ptr.\\*char_ptr\",exp=\"\\*char_ptr\",numchild=\"0\",type=\"char\"\}\\\]" \ + "get children of struct_declarations.char_ptr" + +# Test: c_variable-4.10 +# Desc: number of children of struct_declarations.char_ptr +mi_gdb_test "-var-info-num-children struct_declarations.char_ptr" \ + "\\^done,numchild=\"1\"" \ + "get number of children of struct_declarations.char_ptr" + +# Test: c_variable-4.11 +# Desc: children of struct_declarations.long_int +mi_gdb_test "-var-list-children struct_declarations.long_int" \ + "\\^done,numchild=\"0\"" \ + "get children of struct_declarations.long_int" + +# Test: c_variable-4.12 +# Desc: number of children of struct_declarations.long_int +mi_gdb_test "-var-info-num-children struct_declarations.long_int" \ + "\\^done,numchild=\"0\"" \ + "get number of children of struct_declarations.long_int" + +# Test: c_variable-4.13 +# Desc: children of int_ptr_ptr +mi_gdb_test "-var-list-children struct_declarations.int_ptr_ptr" \ + "\\^done,numchild=\"1\",children=\\\[child=\{name=\"struct_declarations.int_ptr_ptr.\\*int_ptr_ptr\",exp=\"\\*int_ptr_ptr\",numchild=\"1\",type=\"int \\*\"\}\\\]" \ + "get children of struct_declarations.int_ptr_ptr" + +#gdbtk_test c_variable-4.13 {children of int_ptr_ptr} { +# get_children struct_declarations.int_ptr_ptr +#} {*int_ptr_ptr} + +# Test: c_variable-4.14 +# Desc: number of children of int_ptr_ptr +mi_gdb_test "-var-info-num-children struct_declarations.int_ptr_ptr" \ + "\\^done,numchild=\"1\"" \ + "get number of children of struct_declarations.int_ptr_ptr" + + +# Test: c_variable-4.15 +# Desc: children of struct_declarations.long_array +mi_gdb_test "-var-list-children struct_declarations.long_array" \ + "\\^done,numchild=\"10\",children=\\\[child=\{name=\"struct_declarations.long_array.0\",exp=\"0\",numchild=\"0\",type=\"long int\"\},child=\{name=\"struct_declarations.long_array.1\",exp=\"1\",numchild=\"0\",type=\"long int\"\},child=\{name=\"struct_declarations.long_array.2\",exp=\"2\",numchild=\"0\",type=\"long int\"\},child=\{name=\"struct_declarations.long_array.3\",exp=\"3\",numchild=\"0\",type=\"long int\"\},child=\{name=\"struct_declarations.long_array.4\",exp=\"4\",numchild=\"0\",type=\"long int\"\},child=\{name=\"struct_declarations.long_array.5\",exp=\"5\",numchild=\"0\",type=\"long int\"\},child=\{name=\"struct_declarations.long_array.6\",exp=\"6\",numchild=\"0\",type=\"long int\"\},child=\{name=\"struct_declarations.long_array.7\",exp=\"7\",numchild=\"0\",type=\"long int\"\},child=\{name=\"struct_declarations.long_array.8\",exp=\"8\",numchild=\"0\",type=\"long int\"\},child=\{name=\"struct_declarations.long_array.9\",exp=\"9\",numchild=\"0\",type=\"long int\"\}\\\]" \ + "get children of struct_declarations.long_array" + +# Test: c_variable-4.16 +# Desc: number of children of struct_declarations.long_array +mi_gdb_test "-var-info-num-children struct_declarations.long_array" \ + "\\^done,numchild=\"10\"" \ + "get number of children of struct_declarations.long_array" + +# Test: c_variable-4.17 +# Desc: children of struct_declarations.func_ptr +mi_gdb_test "-var-list-children struct_declarations.func_ptr" \ + "\\^done,numchild=\"0\"" \ + "get children of struct_declarations.func_ptr" + + +# Test: c_variable-4.18 +# Desc: number of children of struct_declarations.func_ptr +mi_gdb_test "-var-info-num-children struct_declarations.func_ptr" \ + "\\^done,numchild=\"0\"" \ + "get number of children of struct_declarations.func_ptr" + + +# Test: c_variable-4.19 +# Desc: children of struct_declarations.func_ptr_struct +mi_gdb_test "-var-list-children struct_declarations.func_ptr_struct" \ + "\\^done,numchild=\"0\"" \ + "get children of struct_declarations.func_ptr_struct" + +# Test: c_variable-4.20 +# Desc: number of children of struct_declarations.func_ptr_struct +mi_gdb_test "-var-info-num-children struct_declarations.func_ptr_struct" \ + "\\^done,numchild=\"0\"" \ + "get number of children of struct_declarations.func_ptr_struct" + + +# Test: c_variable-4.21 +# Desc: children of struct_declarations.func_ptr_ptr +mi_gdb_test "-var-list-children struct_declarations.func_ptr_ptr" \ + "\\^done,numchild=\"0\"" \ + "get children of struct_declarations.func_ptr_ptr" + +# Test: c_variable-4.22 +# Desc: number of children of struct_declarations.func_ptr_ptr +mi_gdb_test "-var-info-num-children struct_declarations.func_ptr_ptr" \ + "\\^done,numchild=\"0\"" \ + "get number of children of struct_declarations.func_ptr_ptr" + + +# Test: c_variable-4.23 +# Desc: children of struct_declarations.u1 +mi_gdb_test "-var-list-children struct_declarations.u1" \ + "\\^done,numchild=\"4\",children=\\\[child=\{name=\"struct_declarations.u1.a\",exp=\"a\",numchild=\"0\",type=\"int\"\},child=\{name=\"struct_declarations.u1.b\",exp=\"b\",numchild=\"1\",type=\"char \\*\"\},child=\{name=\"struct_declarations.u1.c\",exp=\"c\",numchild=\"0\",type=\"long int\"\},child=\{name=\"struct_declarations.u1.d\",exp=\"d\",numchild=\"0\",type=\"enum foo\"\}\\\]" \ + "get children of struct_declarations.u1" + +# Test: c_variable-4.24 +# Desc: number of children of struct_declarations.u1 +mi_gdb_test "-var-info-num-children struct_declarations.u1" \ + "\\^done,numchild=\"4\"" \ + "get number of children of struct_declarations.u1" + +# Test: c_variable-4.25 +# Desc: children of struct_declarations.s2 +mi_gdb_test "-var-list-children struct_declarations.s2" \ + "\\^done,numchild=\"4\",children=\\\[child=\{name=\"struct_declarations.s2.u2\",exp=\"u2\",numchild=\"3\",type=\"union \{\\.\\.\\.\}\"\},child=\{name=\"struct_declarations.s2.g\",exp=\"g\",numchild=\"0\",type=\"int\"\},child=\{name=\"struct_declarations.s2.h\",exp=\"h\",numchild=\"0\",type=\"char\"\},child=\{name=\"struct_declarations.s2.i\",exp=\"i\",numchild=\"10\",type=\"long int \\\[10\\\]\"\}\\\]" \ + "get children of struct_declarations.s2" +#gdbtk_test c_variable-4.25 {children of struct_declarations.s2} { +# get_children struct_declarations.s2 +#} {u2 g h i} + +# Test: c_variable-4.26 +# Desc: number of children of struct_declarations.s2 +mi_gdb_test "-var-info-num-children struct_declarations.s2" \ + "\\^done,numchild=\"4\"" \ + "get number of children of struct_declarations.s2" + + +# Test: c_variable-4.27 +# Desc: children of struct_declarations.long_array.1 +mi_gdb_test "-var-list-children struct_declarations.long_array.1" \ + "\\^done,numchild=\"0\"" \ + "get children of struct_declarations.long_array.1" + +# Test: c_variable-4.28 +# Desc: number of children of struct_declarations.long_array.1 +mi_gdb_test "-var-info-num-children struct_declarations.long_array.1" \ + "\\^done,numchild=\"0\"" \ + "get number of children of struct_declarations.long_array.1" + +# Test: c_variable-4.29 +# Desc: children of struct_declarations.long_array.2 +mi_gdb_test "-var-list-children struct_declarations.long_array.2" \ + "\\^done,numchild=\"0\"" \ + "get children of struct_declarations.long_array.2" + +# Test: c_variable-4.30 +# Desc: number of children of struct_declarations.long_array.2 +mi_gdb_test "-var-info-num-children struct_declarations.long_array.2" \ + "\\^done,numchild=\"0\"" \ + "get number of children of struct_declarations.long_array.2" + +# Test: c_variable-4.31 +# Desc: children of struct_declarations.long_array.3 +mi_gdb_test "-var-list-children struct_declarations.long_array.3" \ + "\\^done,numchild=\"0\"" \ + "get children of struct_declarations.long_array.3" + +# Test: c_variable-4.32 +# Desc: number of children of struct_declarations.long_array.3 +mi_gdb_test "-var-info-num-children struct_declarations.long_array.3" \ + "\\^done,numchild=\"0\"" \ + "get number of children of struct_declarations.long_array.3" + +# Test: c_variable-4.33 +# Desc: children of struct_declarations.long_array.4 +mi_gdb_test "-var-list-children struct_declarations.long_array.4" \ + "\\^done,numchild=\"0\"" \ + "get children of struct_declarations.long_array.4" + +# Test: c_variable-4.34 +# Desc: number of children of struct_declarations.long_array.4 +mi_gdb_test "-var-info-num-children struct_declarations.long_array.4" \ + "\\^done,numchild=\"0\"" \ + "get number of children of struct_declarations.long_array.4" + +# Test: c_variable-4.35 +# Desc: children of struct_declarations.long_array.5 +mi_gdb_test "-var-list-children struct_declarations.long_array.5" \ + "\\^done,numchild=\"0\"" \ + "get children of struct_declarations.long_array.5" + +# Test: c_variable-4.36 +# Desc: number of children of struct_declarations.long_array.5 +mi_gdb_test "-var-info-num-children struct_declarations.long_array.5" \ + "\\^done,numchild=\"0\"" \ + "get number of children of struct_declarations.long_array.5" + +# Test: c_variable-4.37 +# Desc: children of struct_declarations.long_array.6 +mi_gdb_test "-var-list-children struct_declarations.long_array.6" \ + "\\^done,numchild=\"0\"" \ + "get children of struct_declarations.long_array.6" + +# Test: c_variable-4.38 +# Desc: number of children of struct_declarations.long_array.6 +mi_gdb_test "-var-info-num-children struct_declarations.long_array.6" \ + "\\^done,numchild=\"0\"" \ + "get number of children of struct_declarations.long_array.6" + +# Test: c_variable-4.39 +# Desc: children of struct_declarations.long_array.7 +mi_gdb_test "-var-list-children struct_declarations.long_array.7" \ + "\\^done,numchild=\"0\"" \ + "get children of struct_declarations.long_array.7" + +# Test: c_variable-4.40 +# Desc: number of children of struct_declarations.long_array.7 +mi_gdb_test "-var-info-num-children struct_declarations.long_array.7" \ + "\\^done,numchild=\"0\"" \ + "get number of children of struct_declarations.long_array.7" + +# Test: c_variable-4.41 +# Desc: children of struct_declarations.long_array.8 +mi_gdb_test "-var-list-children struct_declarations.long_array.8" \ + "\\^done,numchild=\"0\"" \ + "get children of struct_declarations.long_array.8" + +# Test: c_variable-4.42 +# Desc: number of children of struct_declarations.long_array.8 +mi_gdb_test "-var-info-num-children struct_declarations.long_array.8" \ + "\\^done,numchild=\"0\"" \ + "get number of children of struct_declarations.long_array.8" + + +# Test: c_variable-4.43 +# Desc: children of struct_declarations.long_array.9 +mi_gdb_test "-var-list-children struct_declarations.long_array.9" \ + "\\^done,numchild=\"0\"" \ + "get children of struct_declarations.long_array.9" + +# Test: c_variable-4.44 +# Desc: number of children of struct_declarations.long_array.9 +mi_gdb_test "-var-info-num-children struct_declarations.long_array.9" \ + "\\^done,numchild=\"0\"" \ + "get number of children of struct_declarations.long_array.9" + +# Test: c_variable-4.45 +# Desc: children of struct_declarations.u1.a +mi_gdb_test "-var-list-children struct_declarations.u1.a" \ + "\\^done,numchild=\"0\"" \ + "get children of struct_declarations.u1.a" + +# Test: c_variable-4.46 +# Desc: number of children of struct_declarations.u1.a +mi_gdb_test "-var-info-num-children struct_declarations.u1.a" \ + "\\^done,numchild=\"0\"" \ + "get number of children of struct_declarations.u1.a" + +# Test: c_variable-4.47 +# Desc: children of struct_declarations.u1.b +mi_gdb_test "-var-list-children struct_declarations.u1.b" \ + "\\^done,numchild=\"1\",children=\\\[child=\{name=\"struct_declarations.u1.b.\\*b\",exp=\"\\*b\",numchild=\"0\",type=\"char\"\}\\\]" \ + "get children of struct_declarations.u1.b" + +# Test: c_variable-4.48 +# Desc: number of children of struct_declarations.u1.b +mi_gdb_test "-var-info-num-children struct_declarations.u1.b" \ + "\\^done,numchild=\"1\"" \ + "get number of children of struct_declarations.u1.b" + +# Test: c_variable-4.49 +# Desc: children of struct_declarations.u1.c +mi_gdb_test "-var-list-children struct_declarations.u1.c" \ + "\\^done,numchild=\"0\"" \ + "get children of struct_declarations.u1.c" + +# Test: c_variable-4.50 +# Desc: number of children of struct_declarations.u1.c +mi_gdb_test "-var-info-num-children struct_declarations.u1.c" \ + "\\^done,numchild=\"0\"" \ + "get number of children of struct_declarations.u1.c" + +# Test: c_variable-4.51 +# Desc: children of struct_declarations.u1.d +mi_gdb_test "-var-list-children struct_declarations.u1.d" \ + "\\^done,numchild=\"0\"" \ + "get children of struct_declarations.u1.d" + + +# Test: c_variable-4.52 +# Desc: number of children of struct_declarations.u1.d +mi_gdb_test "-var-info-num-children struct_declarations.u1.d" \ + "\\^done,numchild=\"0\"" \ + "get number of children of struct_declarations.u1.d" + + +# Test: c_variable-4.53 +# Desc: children of struct_declarations.s2.u2 +mi_gdb_test "-var-list-children struct_declarations.s2.u2" \ + "\\^done,numchild=\"3\",children=\\\[child=\{name=\"struct_declarations.s2.u2.u1s1\",exp=\"u1s1\",numchild=\"4\",type=\"struct \{\\.\\.\\.\}\"\},child=\{name=\"struct_declarations.s2.u2.f\",exp=\"f\",numchild=\"0\",type=\"long int\"\},child=\{name=\"struct_declarations.s2.u2.u1s2\",exp=\"u1s2\",numchild=\"2\",type=\"struct \{\\.\\.\\.\}\"\}\\\]" \ + "get children of struct_declarations.s2.u2" + +# Test: c_variable-4.54 +# Desc: number of children of struct_declarations.s2.u2 +mi_gdb_test "-var-info-num-children struct_declarations.s2.u2" \ + "\\^done,numchild=\"3\"" \ + "get number of children of struct_declarations.s2.u2" + +# Test: c_variable-4.55 +# Desc: children of struct_declarations.s2.g +mi_gdb_test "-var-list-children struct_declarations.s2.g" \ + "\\^done,numchild=\"0\"" \ + "get children of struct_declarations.s2.g" + +# Test: c_variable-4.56 +# Desc: number of children of struct_declarations.s2.g +mi_gdb_test "-var-info-num-children struct_declarations.s2.g" \ + "\\^done,numchild=\"0\"" \ + "get number of children of struct_declarations.s2.g" + + +# Test: c_variable-4.57 +# Desc: children of struct_declarations.s2.h +mi_gdb_test "-var-list-children struct_declarations.s2.h" \ + "\\^done,numchild=\"0\"" \ + "get children of struct_declarations.s2.h" + +# Test: c_variable-4.58 +# Desc: number of children of struct_declarations.s2.h +mi_gdb_test "-var-info-num-children struct_declarations.s2.h" \ + "\\^done,numchild=\"0\"" \ + "get number of children of struct_declarations.s2.h" + + +# Test: c_variable-4.59 +# Desc: children of struct_declarations.s2.i +mi_gdb_test "-var-list-children struct_declarations.s2.i" \ + "\\^done,numchild=\"10\",children=\\\[child=\{name=\"struct_declarations.s2.i.0\",exp=\"0\",numchild=\"0\",type=\"long int\"\},child=\{name=\"struct_declarations.s2.i.1\",exp=\"1\",numchild=\"0\",type=\"long int\"\},child=\{name=\"struct_declarations.s2.i.2\",exp=\"2\",numchild=\"0\",type=\"long int\"\},child=\{name=\"struct_declarations.s2.i.3\",exp=\"3\",numchild=\"0\",type=\"long int\"\},child=\{name=\"struct_declarations.s2.i.4\",exp=\"4\",numchild=\"0\",type=\"long int\"\},child=\{name=\"struct_declarations.s2.i.5\",exp=\"5\",numchild=\"0\",type=\"long int\"\},child=\{name=\"struct_declarations.s2.i.6\",exp=\"6\",numchild=\"0\",type=\"long int\"\},child=\{name=\"struct_declarations.s2.i.7\",exp=\"7\",numchild=\"0\",type=\"long int\"\},child=\{name=\"struct_declarations.s2.i.8\",exp=\"8\",numchild=\"0\",type=\"long int\"\},child=\{name=\"struct_declarations.s2.i.9\",exp=\"9\",numchild=\"0\",type=\"long int\"\}\\\]" \ + "get children of struct_declarations.s2.i" + +# Test: c_variable-4.60 +# Desc: number of children of struct_declarations.s2.i +mi_gdb_test "-var-info-num-children struct_declarations.s2.i" \ + "\\^done,numchild=\"10\"" \ + "get number of children of struct_declarations.s2.i" + +# Test: c_variable-4.61 +# Desc: children of struct_declarations.s2.u2.u1s1 +mi_gdb_test "-var-list-children struct_declarations.s2.u2.u1s1" \ + "\\^done,numchild=\"4\",children=\\\[child=\{name=\"struct_declarations.s2.u2.u1s1.d\",exp=\"d\",numchild=\"0\",type=\"int\"\},child=\{name=\"struct_declarations.s2.u2.u1s1.e\",exp=\"e\",numchild=\"10\",type=\"char \\\[10\\\]\"\},child=\{name=\"struct_declarations.s2.u2.u1s1.func\",exp=\"func\",numchild=\"0\",type=\"int \\*\\(\\*\\)\\((void)?\\)\"\},child=\{name=\"struct_declarations.s2.u2.u1s1.foo\",exp=\"foo\",numchild=\"0\",type=\"efoo\"\}\\\]" \ + "get children of struct_declarations.s2.u2.u1s1" + +# Test: c_variable-4.62 +# Desc: number of children of struct_declarations.s2.u2.u1s1 +mi_gdb_test "-var-info-num-children struct_declarations.s2.u2.u1s1" \ + "\\^done,numchild=\"4\"" \ + "get number of children of struct_declarations.s2.u2.u1s1" + +# Test: c_variable-4.63 +# Desc: children of struct_declarations.s2.u2.f +mi_gdb_test "-var-list-children struct_declarations.s2.u2.f" \ + "\\^done,numchild=\"0\"" \ + "get children of struct_declarations.s2.u2.f" + +# Test: c_variable-4.64 +# Desc: number of children of struct_declarations.s2.u2.f +mi_gdb_test "-var-info-num-children struct_declarations.s2.u2.f" \ + "\\^done,numchild=\"0\"" \ + "get number of children of struct_declarations.s2.u2.f" + +# Test: c_variable-4.65 +# Desc: children of struct_declarations.s2.u2.u1s2 +mi_gdb_test "-var-list-children struct_declarations.s2.u2.u1s2" \ + "\\^done,numchild=\"2\",children=\\\[child=\{name=\"struct_declarations.s2.u2.u1s2.array_ptr\",exp=\"array_ptr\",numchild=\"2\",type=\"char \\\[2\\\]\"\},child=\{name=\"struct_declarations.s2.u2.u1s2.func\",exp=\"func\",numchild=\"0\",type=\"int \\(\\*\\)\\((int, char \\*)?\\)\"\}\\\]" \ + "get children of struct_declarations.s2.u2.u1s2" + +# Test: c_variable-4.66 +# Desc: number of children of struct_declarations.s2.u2.u1s2 +mi_gdb_test "-var-info-num-children struct_declarations.s2.u2.u1s2" \ + "\\^done,numchild=\"2\"" \ + "get number of children of struct_declarations.s2.u2.u1s2" + +# Test: c_variable-4.67 +# Desc: children of struct_declarations.s2.u2.u1s1.d +mi_gdb_test "-var-list-children struct_declarations.s2.u2.u1s1.d" \ + "\\^done,numchild=\"0\"" \ + "get children of struct_declarations.s2.u2.u1s1.d" + +# Test: c_variable-4.68 +# Desc: number of children of struct_declarations.s2.u2.u1s1.d +mi_gdb_test "-var-info-num-children struct_declarations.s2.u2.u1s1.d" \ + "\\^done,numchild=\"0\"" \ + "get number of children of struct_declarations.s2.u2.u1s1.d" + +# Test: c_variable-4.69 +# Desc: children of struct_declarations.s2.u2.u1s1.e +mi_gdb_test "-var-list-children struct_declarations.s2.u2.u1s1.e" \ + "\\^done,numchild=\"10\",children=\\\[child=\{name=\"struct_declarations.s2.u2.u1s1.e.0\",exp=\"0\",numchild=\"0\",type=\"char\"\},child=\{name=\"struct_declarations.s2.u2.u1s1.e.1\",exp=\"1\",numchild=\"0\",type=\"char\"\},child=\{name=\"struct_declarations.s2.u2.u1s1.e.2\",exp=\"2\",numchild=\"0\",type=\"char\"\},child={name=\"struct_declarations.s2.u2.u1s1.e.3\",exp=\"3\",numchild=\"0\",type=\"char\"\},child=\{name=\"struct_declarations.s2.u2.u1s1.e.4\",exp=\"4\",numchild=\"0\",type=\"char\"\},child=\{name=\"struct_declarations.s2.u2.u1s1.e.5\",exp=\"5\",numchild=\"0\",type=\"char\"\},child=\{name=\"struct_declarations.s2.u2.u1s1.e.6\",exp=\"6\",numchild=\"0\",type=\"char\"\},child=\{name=\"struct_declarations.s2.u2.u1s1.e.7\",exp=\"7\",numchild=\"0\",type=\"char\"\},child=\{name=\"struct_declarations.s2.u2.u1s1.e.8\",exp=\"8\",numchild=\"0\",type=\"char\"\},child=\{name=\"struct_declarations.s2.u2.u1s1.e.9\",exp=\"9\",numchild=\"0\",type=\"char\"\}\\\]" \ + "get children of struct_declarations.s2.u2.u1s1.e" + +# Test: c_variable-4.70 +# Desc: number of children of struct_declarations.s2.u2.u1s1.e +mi_gdb_test "-var-info-num-children struct_declarations.s2.u2.u1s1.e" \ + "\\^done,numchild=\"10\"" \ + "get number of children of struct_declarations.s2.u2.u1s1.e" + + +# Test: c_variable-4.71 +# Desc: children of struct_declarations.s2.u2.u1s1.func +mi_gdb_test "-var-list-children struct_declarations.s2.u2.u1s1.func" \ + "\\^done,numchild=\"0\"" \ + "get children of struct_declarations.s2.u2.u1s1.func" + +# Test: c_variable-4.72 +# Desc: number of children of struct_declarations.s2.u2.u1s1.func +mi_gdb_test "-var-info-num-children struct_declarations.s2.u2.u1s1.func" \ + "\\^done,numchild=\"0\"" \ + "get number of children of struct_declarations.s2.u2.u1s1.func" + + +# Test: c_variable-4.73 +# Desc: children of struct_declarations.s2.u2.u1s1.foo +mi_gdb_test "-var-list-children struct_declarations.s2.u2.u1s1.foo" \ + "\\^done,numchild=\"0\"" \ + "get children of struct_declarations.s2.u2.u1s1.foo" + +# Test: c_variable-4.74 +# Desc: number of children of struct_declarations.s2.u2.u1s1.foo +mi_gdb_test "-var-info-num-children struct_declarations.s2.u2.u1s1.foo" \ + "\\^done,numchild=\"0\"" \ + "get number of children of struct_declarations.s2.u2.u1s1.foo" + + +# Test: c_variable-4.75 +# Desc: children of struct_declarations.s2.u2.u1s2.array_ptr +mi_gdb_test "-var-list-children struct_declarations.s2.u2.u1s2.array_ptr" \ + "\\^done,numchild=\"2\",children=\\\[child=\{name=\"struct_declarations.s2.u2.u1s2.array_ptr.0\",exp=\"0\",numchild=\"0\",type=\"char\"\},child={name=\"struct_declarations.s2.u2.u1s2.array_ptr.1\",exp=\"1\",numchild=\"0\",type=\"char\"\}\\\]" \ + "get children of struct_declarations.s2.u2.u1s2.array_ptr" + +# Test: c_variable-4.76 +# Desc: number of children of struct_declarations.s2.u2.u1s2.array_ptr +mi_gdb_test "-var-info-num-children struct_declarations.s2.u2.u1s2.array_ptr" \ + "\\^done,numchild=\"2\"" \ + "get number of children of struct_declarations.s2.u2.u1s2.array_ptr" + +# Test: c_variable-4.77 +# Desc: children of struct_declarations.s2.u2.u1s2.func +mi_gdb_test "-var-list-children struct_declarations.s2.u2.u1s2.func" \ + "\\^done,numchild=\"0\"" \ + "get children of struct_declarations.s2.u2.u1s2.func" + +# Test: c_variable-4.78 +# Desc: number of children of struct_declarations.s2.u2.u1s2.func +mi_gdb_test "-var-info-num-children struct_declarations.s2.u2.u1s2.func" \ + "\\^done,numchild=\"0\"" \ + "get number of children of struct_declarations.s2.u2.u1s2.func" + +# Test: c_variable-4.79 +# Desc: children of struct_declarations.int_ptr_ptr.*int_ptr_ptr +mi_gdb_test "-var-list-children struct_declarations.int_ptr_ptr.*int_ptr_ptr" \ + "\\^done,numchild=\"1\",children=\\\[child=\{name=\"struct_declarations.int_ptr_ptr.\\*int_ptr_ptr.\\*\\*int_ptr_ptr\",exp=\"\\*\\*int_ptr_ptr\",numchild=\"0\",type=\"int\"\}\\\]" \ + "get children of struct_declarations.int_ptr_ptr.*int_ptr_ptr" +#} {**int_ptr_ptr} + +# Test: c_variable-4.80 +# Desc: Number of children of struct_declarations.int_ptr_ptr.*int_ptr_ptr +mi_gdb_test "-var-info-num-children struct_declarations.int_ptr_ptr.*int_ptr_ptr" \ + "\\^done,numchild=\"1\"" \ + "get number of children of struct_declarations.int_ptr_ptr.*int_ptr_ptr" + + +# Step to "struct_declarations.integer = 123;" +set line 192 +mi_step_to do_children_tests {} {.*var-cmd.c} $line "step to line $line" + +# Test: c_variable-4.81 +# Desc: create local variable "weird" +mi_gdb_test "-var-create weird * weird" \ + "\\^done,name=\"weird\",numchild=\"11\",type=\"weird_struct \\*\"" \ + "create local variable weird" + +# Test: c_variable-4.82 +# Desc: children of weird +mi_gdb_test "-var-list-children weird" \ + "\\^done,numchild=\"11\",children=\\\[child=\{name=\"weird.integer\",exp=\"integer\",numchild=\"0\",type=\"int\"\},child=\{name=\"weird.character\",exp=\"character\",numchild=\"0\",type=\"char\"\},child=\{name=\"weird.char_ptr\",exp=\"char_ptr\",numchild=\"1\",type=\"char \\*\"\},child=\{name=\"weird.long_int\",exp=\"long_int\",numchild=\"0\",type=\"long int\"\},child=\{name=\"weird.int_ptr_ptr\",exp=\"int_ptr_ptr\",numchild=\"1\",type=\"int \\*\\*\"\},child=\{name=\"weird.long_array\",exp=\"long_array\",numchild=\"10\",type=\"long int \\\[10\\\]\"\},child=\{name=\"weird.func_ptr\",exp=\"func_ptr\",numchild=\"0\",type=\"void \\(\\*\\)\\((void)?\\)\"\},child=\{name=\"weird.func_ptr_struct\",exp=\"func_ptr_struct\",numchild=\"0\",type=\"struct _struct_decl \\(\\*\\)\\((int, char \\*, long int)?\\)\"\},child=\{name=\"weird.func_ptr_ptr\",exp=\"func_ptr_ptr\",numchild=\"0\",type=\"struct _struct_decl \\*\\(\\*\\)\\((int, char \\*, long int)?\\)\"\},child=\{name=\"weird.u1\",exp=\"u1\",numchild=\"4\",type=\"union \{\\.\\.\\.\}\"\},child=\{name=\"weird.s2\",exp=\"s2\",numchild=\"4\",type=\"struct \{\\.\\.\\.\}\"\}\\\]" \ + "get children of weird" + +# Test: c_variable-4.83 +# Desc: number of children of weird +mi_gdb_test "-var-info-num-children weird" \ + "\\^done,numchild=\"11\"" \ + "get number of children of weird" + + +# Test: c_variable-4.84 +# Desc: children of weird->long_array +mi_gdb_test "-var-list-children weird.long_array" \ + "\\^done,numchild=\"10\",children=\\\[child=\{name=\"weird.long_array.0\",exp=\"0\",numchild=\"0\",type=\"long int\"\},child=\{name=\"weird.long_array.1\",exp=\"1\",numchild=\"0\",type=\"long int\"\},child=\{name=\"weird.long_array.2\",exp=\"2\",numchild=\"0\",type=\"long int\"\},child=\{name=\"weird.long_array.3\",exp=\"3\",numchild=\"0\",type=\"long int\"\},child=\{name=\"weird.long_array.4\",exp=\"4\",numchild=\"0\",type=\"long int\"\},child=\{name=\"weird.long_array.5\",exp=\"5\",numchild=\"0\",type=\"long int\"\},child=\{name=\"weird.long_array.6\",exp=\"6\",numchild=\"0\",type=\"long int\"\},child=\{name=\"weird.long_array.7\",exp=\"7\",numchild=\"0\",type=\"long int\"\},child=\{name=\"weird.long_array.8\",exp=\"8\",numchild=\"0\",type=\"long int\"\},child=\{name=\"weird.long_array.9\",exp=\"9\",numchild=\"0\",type=\"long int\"\}\\\]" \ + "get children of weird.long_array" +#gdbtk_test c_variable-4.84 {children of weird->long_array} { +# get_children weird.long_array +#} {0 1 2 3 4 5 6 7 8 9} + +# Test: c_variable-4.85 +# Desc: number of children of weird.long_array +mi_gdb_test "-var-info-num-children weird.long_array" \ + "\\^done,numchild=\"10\"" \ + "get number of children of weird.long_array" + +# Test: c_variable-4.86 +# Desc: children of weird.int_ptr_ptr +mi_gdb_test "-var-list-children weird.int_ptr_ptr" \ + "\\^done,numchild=\"1\",children=\\\[child=\{name=\"weird.int_ptr_ptr.\\*int_ptr_ptr\",exp=\"\\*int_ptr_ptr\",numchild=\"1\",type=\"int \\*\"\}\\\]" \ + "get children of weird.int_ptr_ptr" +#gdbtk_test c_variable-4.86 {children of weird->int_ptr_ptr} { +# get_children weird.int_ptr_ptr +#} {*int_ptr_ptr} + +# Test: c_variable-4.87 +# Desc: number of children of weird.int_ptr_ptr +mi_gdb_test "-var-info-num-children weird.int_ptr_ptr" \ + "\\^done,numchild=\"1\"" \ + "get number of children of weird.int_ptr_ptr" + +# Test: c_variable-4.88 +# Desc: children of *weird->int_ptr_ptr +mi_gdb_test "-var-list-children weird.int_ptr_ptr.*int_ptr_ptr" \ + "\\^done,numchild=\"1\",children=\\\[child=\{name=\"weird.int_ptr_ptr.\\*int_ptr_ptr.\\*\\*int_ptr_ptr\",exp=\"\\*\\*int_ptr_ptr\",numchild=\"0\",type=\"int\"\}\\\]" \ + "get children of weird.int_ptr_ptr.*int_ptr_ptr" +#gdbtk_test c_variable-4.88 {children of *weird->int_ptr_ptr} { +# get_children weird.int_ptr_ptr.*int_ptr_ptr +#} {**int_ptr_ptr} + +# Test: c_variable-4.89 +# Desc: number of children *weird->int_ptr_ptr +mi_gdb_test "-var-info-num-children weird.int_ptr_ptr.*int_ptr_ptr" \ + "\\^done,numchild=\"1\"" \ + "get number of children of weird.int_ptr_ptr.*int_ptr_ptr" + +# Test: c_variable-4.90 +# Desc: create weird->int_ptr_ptr +mi_gdb_test "-var-create weird->int_ptr_ptr * weird->int_ptr_ptr" \ + "\\^done,name=\"weird->int_ptr_ptr\",numchild=\"1\",type=\"int \\*\\*\"" \ + "create local variable weird->int_ptr_ptr" + +# Test: c_variable-4.91 +# Desc: children of weird->int_ptr_ptr +mi_gdb_test "-var-list-children weird->int_ptr_ptr" \ + "\\^done,numchild=\"1\",children=\\\[child=\{name=\"weird->int_ptr_ptr.\\*weird->int_ptr_ptr\",exp=\"\\*weird->int_ptr_ptr\",numchild=\"1\",type=\"int \\*\"\}\\\]" \ + "get children of weird->int_ptr_ptr" + + +# Test: c_variable-4.92 +# Desc: number of children of (weird->int_ptr_ptr) +mi_gdb_test "-var-info-num-children weird->int_ptr_ptr" \ + "\\^done,numchild=\"1\"" \ + "get number of children of weird->int_ptr_ptr" + +# Test: c_variable-4.93 +# Desc: children of *(weird->int_ptr_ptr) +mi_gdb_test "-var-list-children weird->int_ptr_ptr.*weird->int_ptr_ptr" \ + "\\^done,numchild=\"1\",children=\\\[child=\{name=\"weird->int_ptr_ptr.\\*weird->int_ptr_ptr.\\*\\*weird->int_ptr_ptr\",exp=\"\\*\\*weird->int_ptr_ptr\",numchild=\"0\",type=\"int\"\}\\\]" \ + "get children of weird->int_ptr_ptr.*weird->int_ptr_ptr" + +# Test: c_variable-4.94 +# Desc: number of children of *(weird->int_ptr_ptr) +mi_gdb_test "-var-info-num-children weird->int_ptr_ptr.*weird->int_ptr_ptr" \ + "\\^done,numchild=\"1\"" \ + "get number of children of weird->int_ptr_ptr.*weird->int_ptr_ptr" + +# Test: c_variable-4.95 +# Desc: children of *(*(weird->int_ptr_ptr)) +mi_gdb_test "-var-list-children weird->int_ptr_ptr.*weird->int_ptr_ptr.**weird->int_ptr_ptr" \ + "\\^done,numchild=\"0\"" \ + "get children of weird->int_ptr_ptr.*weird->int_ptr_ptr.**weird->int_ptr_ptr" + +# Test: c_variable-4.96 +# Desc: number of children of *(*(weird->int_ptr_ptr)) +mi_gdb_test "-var-info-num-children weird->int_ptr_ptr.*weird->int_ptr_ptr.**weird->int_ptr_ptr" \ + "\\^done,numchild=\"0\"" \ + "get number of children of weird->int_ptr_ptr.*weird->int_ptr_ptr.**weird->int_ptr_ptr" + +# Test: c_variable-4.97 +# Desc: is weird editable +mi_gdb_test "-var-show-attributes weird" \ + "\\^done,attr=\"editable\"" \ + "is weird editable" + +# Test: c_variable-4.98 +# Desc: is weird->int_ptr_ptr editable +mi_gdb_test "-var-show-attributes weird->int_ptr_ptr" \ + "\\^done,attr=\"editable\"" \ + "is weird->int_ptr_ptr editable" + +# Test: c_variable-4.99 +# Desc: is *(weird->int_ptr_ptr) editable +mi_gdb_test "-var-show-attributes weird.int_ptr_ptr.*int_ptr_ptr" \ + "\\^done,attr=\"editable\"" \ + "is weird.int_ptr_ptr.*int_ptr_ptr editable" + +# Test: c_variable-4.100 +# Desc: is *(*(weird->int_ptr_ptr)) editable +mi_gdb_test "-var-show-attributes weird.int_ptr_ptr.*int_ptr_ptr.**int_ptr_ptr" \ + "\\^done,attr=\"editable\"" \ + "is weird.int_ptr_ptr.*int_ptr_ptr.**int_ptr_ptr editable" + +# Test: c_variable-4.101 +# Desc: is weird->u1 editable +mi_gdb_test "-var-show-attributes weird.u1" \ + "\\^done,attr=\"noneditable\"" \ + "is weird.u1 editable" + +# Test: c_variable-4.102 +# Desc: is weird->s2 editable +mi_gdb_test "-var-show-attributes weird.s2" \ + "\\^done,attr=\"noneditable\"" \ + "is weird.s2 editable" + +# Test: c_variable-4.103 +# Desc: is struct_declarations.u1.a editable +mi_gdb_test "-var-show-attributes struct_declarations.u1.a" \ + "\\^done,attr=\"editable\"" \ + "is struct_declarations.u1.a editable" + +# Test: c_variable-4.104 +# Desc: is struct_declarations.u1.b editable +mi_gdb_test "-var-show-attributes struct_declarations.u1.b" \ + "\\^done,attr=\"editable\"" \ + "is struct_declarations.u1.b editable" + +# Test: c_variable-4.105 +# Desc: is struct_declarations.u1.c editable +mi_gdb_test "-var-show-attributes struct_declarations.u1.c" \ + "\\^done,attr=\"editable\"" \ + "is struct_declarations.u1.c editable" + +# Test: c_variable-4.106 +# Desc: is struct_declarations.long_array editable +mi_gdb_test "-var-show-attributes struct_declarations.long_array" \ + "\\^done,attr=\"noneditable\"" \ + "is struct_declarations.long_array editable" + +# Test: c_variable-4.107 +# Desc: is struct_declarations.long_array[0] editable +mi_gdb_test "-var-show-attributes struct_declarations.long_array.0" \ + "\\^done,attr=\"editable\"" \ + "is struct_declarations.long_array.0 editable" + +# Test: c_variable-4.108 +# Desc: is struct_declarations editable +mi_gdb_test "-var-show-attributes struct_declarations" \ + "\\^done,attr=\"noneditable\"" \ + "is struct_declarations editable" + +mi_gdb_test "-var-delete weird" \ + "\\^done,ndeleted=\"24\"" \ + "delete var weird" + +##### ##### +# # +# children and update tests # +# # +##### ##### + +# Test: c_variable-5.1 +# Desc: check that nothing changed +mi_gdb_test "-var-update *" \ + "\\^done,changelist=\\\[\\\]" \ + "update all vars. None changed" + +# Step over "struct_declarations.integer = 123;" +set line 193 +mi_step_to do_children_tests {} {.*var-cmd.c} $line "step $line" + +# Test: c_variable-5.2 +# Desc: check that integer changed +mi_gdb_test "-var-update *" \ + "\\^done,changelist=\\\[\{name=\"struct_declarations.integer\",in_scope=\"true\",type_changed=\"false\"\}\\\]" \ + "update all vars struct_declarations.integer" + +# Step over: +# weird->char_ptr = "hello"; +# bar = 2121; +# foo = &bar; +set line 196 +mi_execute_to "exec-step 3" "end-stepping-range" do_children_tests {} {.*var-cmd.c} $line {} "step $line" + +# Test: c_variable-5.3 +# Desc: check that char_ptr changed +mi_gdb_test "-var-update *" \ + "\\^done,changelist=\\\[\{name=\"struct_declarations.char_ptr\",in_scope=\"true\",type_changed=\"false\"\},\{name=\"struct_declarations.char_ptr.\\*char_ptr\",in_scope=\"true\",type_changed=\"false\"\}\\\]" \ + "update all vars struct_declarations.char_ptr" + +# Step over "struct_declarations.int_ptr_ptr = &foo;" +set line 197 +mi_step_to do_children_tests {} {.*var-cmd.c} $line "step $line" + +# Test: c_variable-5.4 +# Desc: check that int_ptr_ptr and children changed +mi_gdb_test "-var-update *" \ + "\\^done,changelist=\\\[\{name=\"weird->int_ptr_ptr\",in_scope=\"true\",type_changed=\"false\"\},\{name=\"weird->int_ptr_ptr.\\*weird->int_ptr_ptr\",in_scope=\"true\",type_changed=\"false\"\},\{name=\"weird->int_ptr_ptr.\\*weird->int_ptr_ptr.\\*\\*weird->int_ptr_ptr\",in_scope=\"true\",type_changed=\"false\"\},\{name=\"struct_declarations.int_ptr_ptr\",in_scope=\"true\",type_changed=\"false\"\},\{name=\"struct_declarations.int_ptr_ptr.\\*int_ptr_ptr\",in_scope=\"true\",type_changed=\"false\"\},\{name=\"struct_declarations.int_ptr_ptr.\\*int_ptr_ptr.\\*\\*int_ptr_ptr\",in_scope=\"true\",type_changed=\"false\"\}\\\]" \ + "update all vars int_ptr_ptr and children changed" + +# Step over "weird->long_array[0] = 1234;" +set line 198 +mi_step_to do_children_tests {} {.*var-cmd.c} $line "step $line" + +# Test: c_variable-5.5 +# Desc: check that long_array[0] changed +mi_gdb_test "-var-update *" \ + "\\^done,changelist=\\\[\{name=\"struct_declarations.long_array.0\",in_scope=\"true\",type_changed=\"false\"\}\\\]" \ + "update all vars struct_declarations.long_array.0 changed" + +# Step over "struct_declarations.long_array[1] = 2345;" +set line 199 +mi_step_to do_children_tests {} {.*var-cmd.c} $line "step $line" + +# Test: c_variable-5.6 +# Desc: check that long_array[1] changed +mi_gdb_test "-var-update *" \ + "\\^done,changelist=\\\[\{name=\"struct_declarations.long_array.1\",in_scope=\"true\",type_changed=\"false\"\}\\\]" \ + "update all vars struct_declarations.long_array.1 changed" + +# Step over "weird->long_array[2] = 3456;" +set line 200 +mi_step_to do_children_tests {} {.*var-cmd.c} $line "step $line" + +# Test: c_variable-5.7 +# Desc: check that long_array[2] changed +mi_gdb_test "-var-update *" \ + "\\^done,changelist=\\\[\{name=\"struct_declarations.long_array.2\",in_scope=\"true\",type_changed=\"false\"\}\\\]" \ + "update all vars struct_declarations.long_array.2 changed" + +# Step over: +# struct_declarations.long_array[3] = 4567; +# weird->long_array[4] = 5678; +# struct_declarations.long_array[5] = 6789; +# weird->long_array[6] = 7890; +# struct_declarations.long_array[7] = 8901; +# weird->long_array[8] = 9012; +# struct_declarations.long_array[9] = 1234; +set line 208 +mi_execute_to "exec-step 7" "end-stepping-range" do_children_tests {} {.*var-cmd.c} $line {} "step $line" + +# Test: c_variable-5.8 +# Desc: check that long_array[3-9] changed +mi_gdb_test "-var-update *" \ + "\\^done,changelist=\\\[\{name=\"struct_declarations.long_array.3\",in_scope=\"true\",type_changed=\"false\"\},\{name=\"struct_declarations.long_array.4\",in_scope=\"true\",type_changed=\"false\"\},\{name=\"struct_declarations.long_array.5\",in_scope=\"true\",type_changed=\"false\"\},\{name=\"struct_declarations.long_array.6\",in_scope=\"true\",type_changed=\"false\"\},\{name=\"struct_declarations.long_array.7\",in_scope=\"true\",type_changed=\"false\"\},\{name=\"struct_declarations.long_array.8\",in_scope=\"true\",type_changed=\"false\"\},\{name=\"struct_declarations.long_array.9\",in_scope=\"true\",type_changed=\"false\"\}\\\]" \ + "update all vars struct_declarations.long_array.3-9 changed" + + +# Step over "weird->func_ptr = nothing;" +set line 211 +mi_step_to do_children_tests {} {.*var-cmd.c} $line "step $line" + +# Test: c_variable-5.9 +# Desc: check that func_ptr changed +mi_gdb_test "-var-update *" \ + "\\^done,changelist=\\\[\{name=\"struct_declarations.func_ptr\",in_scope=\"true\",type_changed=\"false\"\}\\\]" \ + "update all vars struct_declarations.func_ptr changed" + +# Delete all variables +mi_gdb_test "-var-delete struct_declarations" \ + "\\^done,ndeleted=\"65\"" \ + "delete var struct_declarations" + +mi_gdb_test "-var-delete weird->int_ptr_ptr" \ + "\\^done,ndeleted=\"3\"" \ + "delete var weird->int_ptr_ptr" + +# Step over all lines: +# ... +# psnp = &snp0; +set line 254 +mi_execute_to "exec-step 43" "end-stepping-range" do_children_tests {} {.*var-cmd.c} $line {} "step $line" + +# Test: c_variable-5.10 +# Desc: create psnp->char_ptr +mi_gdb_test "-var-create psnp->char_ptr * psnp->char_ptr" \ + "\\^done,name=\"psnp->char_ptr\",numchild=\"1\",type=\"char \\*\\*\\*\\*\"" \ + "create local variable psnp->char_ptr" + +# Test: c_variable-5.11 +# Desc: children of psnp->char_ptr +mi_gdb_test "-var-list-children psnp->char_ptr" \ + "\\^done,numchild=\"1\",children=\\\[child=\{name=\"psnp->char_ptr.\\*psnp->char_ptr\",exp=\"\\*psnp->char_ptr\",numchild=\"1\",type=\"char \\*\\*\\*\"\}\\\]" \ + "get children of psnp->char_ptr" + +# Test: c_variable-5.12 +# Desc: number of children of psnp->char_ptr +mi_gdb_test "-var-info-num-children psnp->char_ptr" \ + "\\^done,numchild=\"1\"" \ + "get number of children of psnp->char_ptr" + +# Test: c_variable-5.13 +# Desc: children of *(psnp->char_ptr) +mi_gdb_test "-var-list-children psnp->char_ptr.*psnp->char_ptr" \ + "\\^done,numchild=\"1\",children=\\\[child=\{name=\"psnp->char_ptr.\\*psnp->char_ptr.\\*\\*psnp->char_ptr\",exp=\"\\*\\*psnp->char_ptr\",numchild=\"1\",type=\"char \\*\\*\"\}\\\]" \ + "get children of psnp->char_ptr.*psnp->char_ptr" + +# Test: c_variable-5.14 +# Desc: number of children of *(psnp->char_ptr) +mi_gdb_test "-var-info-num-children psnp->char_ptr.*psnp->char_ptr" \ + "\\^done,numchild=\"1\"" \ + "get number of children of psnp->char_ptr.*psnp->char_ptr" + +# Test: c_variable-5.15 +# Desc: children of *(*(psnp->char_ptr)) +mi_gdb_test "-var-list-children psnp->char_ptr.*psnp->char_ptr.**psnp->char_ptr" \ + "\\^done,numchild=\"1\",children=\\\[child=\{name=\"psnp->char_ptr.\\*psnp->char_ptr.\\*\\*psnp->char_ptr.\\*\\*\\*psnp->char_ptr\",exp=\"\\*\\*\\*psnp->char_ptr\",numchild=\"1\",type=\"char \\*\"\}\\\]" \ + "get children of psnp->char_ptr.*psnp->char_ptr.**psnp->char_ptr" + +# Test: c_variable-5.15B +# Desc: children of *(*(*(psnp->char_ptr))) +mi_gdb_test "-var-list-children psnp->char_ptr.*psnp->char_ptr.**psnp->char_ptr.***psnp->char_ptr" \ + "\\^done,numchild=\"1\",children=\\\[child=\{name=\"psnp->char_ptr.\\*psnp->char_ptr.\\*\\*psnp->char_ptr.\\*\\*\\*psnp->char_ptr.\\*\\*\\*\\*psnp->char_ptr\",exp=\"\\*\\*\\*\\*psnp->char_ptr\",numchild=\"0\",type=\"char\"\}\\\]" \ + "get children of psnp->char_ptr.*psnp->char_ptr.**psnp->char_ptr" + +# Test: c_variable-5.16 +# Desc: number of children of *(*(psnp->char_ptr)) +mi_gdb_test "-var-info-num-children psnp->char_ptr.*psnp->char_ptr.**psnp->char_ptr" \ + "\\^done,numchild=\"1\"" \ + "get number of children of psnp->char_ptr.*psnp->char_ptr.**psnp->char_ptr" + +# Test: c_variable-5.17 +# Desc: children of *(*(*(psnp->char_ptr))) +mi_gdb_test "-var-list-children psnp->char_ptr.*psnp->char_ptr.**psnp->char_ptr.***psnp->char_ptr" \ + "\\^done,numchild=\"1\",children=\\\[child=\{name=\"psnp->char_ptr.\\*psnp->char_ptr.\\*\\*psnp->char_ptr.\\*\\*\\*psnp->char_ptr.\\*\\*\\*\\*psnp->char_ptr\",exp=\"\\*\\*\\*\\*psnp->char_ptr\",numchild=\"0\",type=\"char\"\}\\\]" \ + "get children of psnp->char_ptr.*psnp->char_ptr.**psnp->char_ptr.***psnp->char_ptr" + +# Test: c_variable-5.18 +# Desc: number of children of *(*(*(psnp->char_ptr))) +mi_gdb_test "-var-info-num-children psnp->char_ptr.*psnp->char_ptr.**psnp->char_ptr.***psnp->char_ptr" \ + "\\^done,numchild=\"1\"" \ + "get number of children of psnp->char_ptr.*psnp->char_ptr.**psnp->char_ptr.***psnp->char_ptr" + +# Test: c_variable-5.17B +# Desc: children of *(*(*(*(psnp->char_ptr)))) +mi_gdb_test "-var-list-children psnp->char_ptr.*psnp->char_ptr.**psnp->char_ptr.***psnp->char_ptr.****psnp->char_ptr" \ + "\\^done,numchild=\"0\"" \ + "get children of psnp->char_ptr.*psnp->char_ptr.**psnp->char_ptr.***psnp->char_ptr.****psnp->char_ptr" + +# Test: c_variable-5.18B +# Desc: number of children of *(*(*(*(psnp->char_ptr)))) +mi_gdb_test "-var-info-num-children psnp->char_ptr.*psnp->char_ptr.**psnp->char_ptr.***psnp->char_ptr.****psnp->char_ptr" \ + "\\^done,numchild=\"0\"" \ + "get number of children of psnp->char_ptr.*psnp->char_ptr.**psnp->char_ptr.***psnp->char_ptr.****psnp->char_ptr" + + +# Test: c_variable-5.19 +# Desc: create psnp->long_ptr +mi_gdb_test "-var-create psnp->long_ptr * psnp->long_ptr" \ + "\\^done,name=\"psnp->long_ptr\",numchild=\"1\",type=\"long int \\*\\*\\*\\*\"" \ + "create local variable psnp->long_ptr" + +# Test: c_variable-5.20 +# Desc: children of psnp->long_ptr +mi_gdb_test "-var-list-children psnp->long_ptr" \ + "\\^done,numchild=\"1\",children=\\\[child=\{name=\"psnp->long_ptr.\\*psnp->long_ptr\",exp=\"\\*psnp->long_ptr\",numchild=\"1\",type=\"long int \\*\\*\\*\"\}\\\]" \ + "get children of psnp->long_ptr" + +# Test: c_variable-5.21 +# Desc: number of children of psnp->long_ptr +mi_gdb_test "-var-info-num-children psnp->long_ptr" \ + "\\^done,numchild=\"1\"" \ + "get number of children of psnp->long_ptr" + +# Test: c_variable-5.22 +# Desc: children of *(psnp->long_ptr) +mi_gdb_test "-var-list-children psnp->long_ptr.*psnp->long_ptr" \ + "\\^done,numchild=\"1\",children=\\\[child=\{name=\"psnp->long_ptr.\\*psnp->long_ptr.\\*\\*psnp->long_ptr\",exp=\"\\*\\*psnp->long_ptr\",numchild=\"1\",type=\"long int \\*\\*\"\}\\\]" \ + "get children of psnp->long_ptr.*psnp->long_ptr" + + +# Test: c_variable-5.23 +# Desc: number of children of *(psnp->long_ptr) +mi_gdb_test "-var-info-num-children psnp->long_ptr.*psnp->long_ptr" \ + "\\^done,numchild=\"1\"" \ + "get number of children of psnp->long_ptr.*psnp->long_ptr" + +# Test: c_variable-5.24 +# Desc: children of *(*(psnp->long_ptr)) +mi_gdb_test "-var-list-children psnp->long_ptr.*psnp->long_ptr.**psnp->long_ptr" \ + "\\^done,numchild=\"1\",children=\\\[child=\{name=\"psnp->long_ptr.\\*psnp->long_ptr.\\*\\*psnp->long_ptr.\\*\\*\\*psnp->long_ptr\",exp=\"\\*\\*\\*psnp->long_ptr\",numchild=\"1\",type=\"long int \\*\"\}\\\]" \ + "get children of psnp->long_ptr.*psnp->long_ptr.**psnp->long_ptr" + +# Test: c_variable-5.25 +# Desc: number of children of *(*(psnp->long_ptr)) +mi_gdb_test "-var-info-num-children psnp->long_ptr.*psnp->long_ptr.**psnp->long_ptr" \ + "\\^done,numchild=\"1\"" \ + "get number of children of psnp->long_ptr.*psnp->long_ptr.**psnp->long_ptr" + +# Test: c_variable-5.26 +# Desc: children of *(*(*(psnp->long_ptr))) +mi_gdb_test "-var-list-children psnp->long_ptr.*psnp->long_ptr.**psnp->long_ptr.***psnp->long_ptr" \ + "\\^done,numchild=\"1\",children=\\\[child=\{name=\"psnp->long_ptr.\\*psnp->long_ptr.\\*\\*psnp->long_ptr.\\*\\*\\*psnp->long_ptr.\\*\\*\\*\\*psnp->long_ptr\",exp=\"\\*\\*\\*\\*psnp->long_ptr\",numchild=\"0\",type=\"long int\"\}\\\]" \ + "get children of psnp->long_ptr.*psnp->long_ptr.**psnp->long_ptr.***psnp->long_ptr" + +# Test: c_variable-5.27 +# Desc: number of children of *(*(*(psnp->long_ptr))) +mi_gdb_test "-var-info-num-children psnp->long_ptr.*psnp->long_ptr.**psnp->long_ptr.***psnp->long_ptr" \ + "\\^done,numchild=\"1\"" \ + "get number of children of psnp->long_ptr.*psnp->long_ptr.**psnp->long_ptr.***psnp->long_ptr" + +# Test: c_variable-5.28 +# Desc: children of *(*(*(*(psnp->long_ptr)))) +mi_gdb_test "-var-list-children psnp->long_ptr.*psnp->long_ptr.**psnp->long_ptr.***psnp->long_ptr.****psnp->long_ptr" \ + "\\^done,numchild=\"0\"" \ + "get children of psnp->long_ptr.*psnp->long_ptr.**psnp->long_ptr.***psnp->long_ptr.****psnp->long_ptr" + +# Test: c_variable-5.29 +# Desc: number of children of *(*(*(*(psnp->long_ptr)))) +mi_gdb_test "-var-info-num-children psnp->long_ptr.*psnp->long_ptr.**psnp->long_ptr.***psnp->long_ptr.****psnp->long_ptr" \ + "\\^done,numchild=\"0\"" \ + "get number of children of psnp->long_ptr.*psnp->long_ptr.**psnp->long_ptr.***psnp->long_ptr.****psnp->long_ptr" + +# Test: c_variable-5.30 +# Desc: create psnp->ptrs +mi_gdb_test "-var-create psnp->ptrs * psnp->ptrs" \ + "\\^done,name=\"psnp->ptrs\",numchild=\"3\",type=\"struct _struct_n_pointer \\*\\\[3\\\]\"" \ + "create local variable psnp->ptrs" + +# Test: c_variable-5.31 +# Desc: children of psnp->ptrs +mi_gdb_test "-var-list-children psnp->ptrs" \ + "\\^done,numchild=\"3\",children=\\\[child=\{name=\"psnp->ptrs.0\",exp=\"0\",numchild=\"4\",type=\"struct _struct_n_pointer \\*\"\},child=\{name=\"psnp->ptrs.1\",exp=\"1\",numchild=\"4\",type=\"struct _struct_n_pointer \\*\"\},child=\{name=\"psnp->ptrs.2\",exp=\"2\",numchild=\"4\",type=\"struct _struct_n_pointer \\*\"\}\\\]" \ + "get children of psnp->ptrs" + +# Test: c_variable-5.32 +# Desc: number of children of psnp->ptrs +mi_gdb_test "-var-info-num-children psnp->ptrs" \ + "\\^done,numchild=\"3\"" \ + "get number of children of psnp->ptrs" + +# Test: c_variable-5.33 +# Desc: children of psnp->ptrs[0] +mi_gdb_test "-var-list-children psnp->ptrs.0" \ + "\\^done,numchild=\"4\",children=\\\[child=\{name=\"psnp->ptrs.0.char_ptr\",exp=\"char_ptr\",numchild=\"1\",type=\"char \\*\\*\\*\\*\"\},child=\{name=\"psnp->ptrs.0.long_ptr\",exp=\"long_ptr\",numchild=\"1\",type=\"long int \\*\\*\\*\\*\"\},child=\{name=\"psnp->ptrs.0.ptrs\",exp=\"ptrs\",numchild=\"3\",type=\"struct _struct_n_pointer \\*\\\[3\\\]\"\},child=\{name=\"psnp->ptrs.0.next\",exp=\"next\",numchild=\"4\",type=\"struct _struct_n_pointer \\*\"\}\\\]" \ + "get children of psnp->ptrs.0" + +# Test: c_variable-5.34 +# Desc: number of children of psnp->ptrs[0] +mi_gdb_test "-var-info-num-children psnp->ptrs.0" \ + "\\^done,numchild=\"4\"" \ + "get number of children of psnp->ptrs.0" + +# Test: c_variable-5.35 +# Desc: children of psnp->ptrs[0]->next +mi_gdb_test "-var-list-children psnp->ptrs.0.next" \ + "\\^done,numchild=\"4\",children=\\\[child=\{name=\"psnp->ptrs.0.next.char_ptr\",exp=\"char_ptr\",numchild=\"1\",type=\"char \\*\\*\\*\\*\"\},child=\{name=\"psnp->ptrs.0.next.long_ptr\",exp=\"long_ptr\",numchild=\"1\",type=\"long int \\*\\*\\*\\*\"\},child=\{name=\"psnp->ptrs.0.next.ptrs\",exp=\"ptrs\",numchild=\"3\",type=\"struct _struct_n_pointer \\*\\\[3\\\]\"\},child=\{name=\"psnp->ptrs.0.next.next\",exp=\"next\",numchild=\"4\",type=\"struct _struct_n_pointer \\*\"\}\\\]" \ + "get children of psnp->ptrs.0.next" + +#} {char_ptr long_ptr ptrs next} + +# Test: c_variable-5.36 +# Desc: number of children of psnp->ptrs[0]->next +mi_gdb_test "-var-info-num-children psnp->ptrs.0.next" \ + "\\^done,numchild=\"4\"" \ + "get number of children of psnp->ptrs.0.next" + + +# Test: c_variable-5.37 +# Desc: children of psnp->ptrs[0]->next->char_ptr +mi_gdb_test "-var-list-children psnp->ptrs.0.next.char_ptr" \ + "\\^done,numchild=\"1\",children=\\\[child=\{name=\"psnp->ptrs.0.next.char_ptr.\\*char_ptr\",exp=\"\\*char_ptr\",numchild=\"1\",type=\"char \\*\\*\\*\"\}\\\]" \ + "get children of psnp->ptrs.0.next.char_ptr" + +#gdbtk_test c_variable-5.37 {children of psnp->ptrs[0]->next->char_ptr} { +# get_children psnp->ptrs.0.next.char_ptr +#} {*char_ptr} + +# Test: c_variable-5.38 +# Desc: number of children of psnp->ptrs[0]->next->char_ptr +mi_gdb_test "-var-info-num-children psnp->ptrs.0.next.char_ptr" \ + "\\^done,numchild=\"1\"" \ + "get number of children of psnp->ptrs.0.next.char_ptr" + +# Test: c_variable-5.39 +# Desc: children of *psnp->ptrs[0]->next->char_ptr +mi_gdb_test "-var-list-children psnp->ptrs.0.next.char_ptr.*char_ptr" \ + "\\^done,numchild=\"1\",children=\\\[child=\{name=\"psnp->ptrs.0.next.char_ptr.\\*char_ptr.\\*\\*char_ptr\",exp=\"\\*\\*char_ptr\",numchild=\"1\",type=\"char \\*\\*\"\}\\\]" \ + "get children of psnp->ptrs.0.next.char_ptr.*char_ptr" + +# Test: c_variable-5.40 +# Desc: number of children of *psnp->ptrs[0]->next->char_ptr +mi_gdb_test "-var-info-num-children psnp->ptrs.0.next.char_ptr.*char_ptr" \ + "\\^done,numchild=\"1\"" \ + "get number of children of psnp->ptrs.0.next.char_ptr.*char_ptr" + +# Test: c_variable-5.41 +# Desc: children of **psnp->ptrs[0]->next->char_ptr +mi_gdb_test "-var-list-children psnp->ptrs.0.next.char_ptr.*char_ptr.**char_ptr" \ + "\\^done,numchild=\"1\",children=\\\[child=\{name=\"psnp->ptrs.0.next.char_ptr.\\*char_ptr.\\*\\*char_ptr.\\*\\*\\*char_ptr\",exp=\"\\*\\*\\*char_ptr\",numchild=\"1\",type=\"char \\*\"\}\\\]" \ + "get children of psnp->ptrs.0.next.char_ptr.*char_ptr.**char_ptr" + +# Test: c_variable-5.41B +# Desc: children of ***psnp->ptrs[0]->next->char_ptr +mi_gdb_test "-var-list-children psnp->ptrs.0.next.char_ptr.*char_ptr.**char_ptr.***char_ptr" \ + "\\^done,numchild=\"1\",children=\\\[child=\{name=\"psnp->ptrs.0.next.char_ptr.\\*char_ptr.\\*\\*char_ptr.\\*\\*\\*char_ptr.\\*\\*\\*\\*char_ptr\",exp=\"\\*\\*\\*\\*char_ptr\",numchild=\"0\",type=\"char\"\}\\\]" \ + "get children of psnp->ptrs.0.next.char_ptr.*char_ptr.**char_ptr" + +# Test: c_variable-5.42 +# Desc: number of children of **psnp->ptrs[0]->next->char_ptr +mi_gdb_test "-var-info-num-children psnp->ptrs.0.next.char_ptr.*char_ptr.**char_ptr" \ + "\\^done,numchild=\"1\"" \ + "get number of children of psnp->ptrs.0.next.char_ptr.*char_ptr.**char_ptr" + +# Test: c_variable-5.43 +# Desc: children of ***psnp->ptrs[0]->next->char_ptr +mi_gdb_test "-var-list-children psnp->ptrs.0.next.char_ptr.*char_ptr.**char_ptr.***char_ptr" \ + "\\^done,numchild=\"1\",children=\\\[child=\{name=\"psnp->ptrs.0.next.char_ptr.\\*char_ptr.\\*\\*char_ptr.\\*\\*\\*char_ptr.\\*\\*\\*\\*char_ptr\",exp=\"\\*\\*\\*\\*char_ptr\",numchild=\"0\",type=\"char\"\}\\\]" \ + "get children of psnp->ptrs.0.next.char_ptr.*char_ptr.**char_ptr.***char_ptr" + +# Test: c_variable-5.44 +# Desc: number of children of ***psnp->ptrs[0]->next->char_ptr +mi_gdb_test "-var-info-num-children psnp->ptrs.0.next.char_ptr.*char_ptr.**char_ptr.***char_ptr" \ + "\\^done,numchild=\"1\"" \ + "get number of children of psnp->ptrs.0.next.char_ptr.*char_ptr.**char_ptr.***char_ptr" + +# Test: c_variable-5.43B +# Desc: children of ****psnp->ptrs[0]->next->char_ptr +mi_gdb_test "-var-list-children psnp->ptrs.0.next.char_ptr.*char_ptr.**char_ptr.***char_ptr.****char_ptr" \ + "\\^done,numchild=\"0\"" \ + "get children of psnp->ptrs.0.next.char_ptr.*char_ptr.**char_ptr.***char_ptr" + +# Test: c_variable-5.44B +# Desc: number of children of ****psnp->ptrs[0]->next->char_ptr +mi_gdb_test "-var-info-num-children psnp->ptrs.0.next.char_ptr.*char_ptr.**char_ptr.***char_ptr.****char_ptr" \ + "\\^done,numchild=\"0\"" \ + "get number of children of psnp->ptrs.0.next.char_ptr.*char_ptr.**char_ptr.***char_ptr" + +# Test: c_variable-5.45 +# Desc: children of psnp->ptrs[0]->next->next +mi_gdb_test "-var-list-children psnp->ptrs.0.next.next" \ + "\\^done,numchild=\"4\",children=\\\[child=\{name=\"psnp->ptrs.0.next.next.char_ptr\",exp=\"char_ptr\",numchild=\"1\",type=\"char \\*\\*\\*\\*\"\},child=\{name=\"psnp->ptrs.0.next.next.long_ptr\",exp=\"long_ptr\",numchild=\"1\",type=\"long int \\*\\*\\*\\*\"\},child=\{name=\"psnp->ptrs.0.next.next.ptrs\",exp=\"ptrs\",numchild=\"3\",type=\"struct _struct_n_pointer \\*\\\[3\\\]\"\},child=\{name=\"psnp->ptrs.0.next.next.next\",exp=\"next\",numchild=\"4\",type=\"struct _struct_n_pointer \\*\"\}\\\]" \ + "get children of psnp->ptrs.0.next.next" + +# Test: c_variable-5.46 +# Desc: children of psnp->ptrs[0]->next->next->ptrs +mi_gdb_test "-var-list-children psnp->ptrs.0.next.next.ptrs" \ + "\\^done,numchild=\"3\",children=\\\[child=\{name=\"psnp->ptrs.0.next.next.ptrs.0\",exp=\"0\",numchild=\"4\",type=\"struct _struct_n_pointer \\*\"\},child=\{name=\"psnp->ptrs.0.next.next.ptrs.1\",exp=\"1\",numchild=\"4\",type=\"struct _struct_n_pointer \\*\"\},child=\{name=\"psnp->ptrs.0.next.next.ptrs.2\",exp=\"2\",numchild=\"4\",type=\"struct _struct_n_pointer \\*\"\}\\\]" \ + "get children of psnp->ptrs.0.next.next.ptrs" + +# Step over "snp0.char_ptr = &b3;" +set line 255 +mi_step_to do_children_tests {} {.*var-cmd.c} $line "step $line" + +# Test: c_variable-5.47 +# Desc: check that psnp->char_ptr (and [0].char_ptr) changed +mi_gdb_test "-var-update *" \ + "\\^done,changelist=\\\[\{name=\"psnp->ptrs.0.char_ptr\",in_scope=\"true\",type_changed=\"false\"\},\{name=\"psnp->char_ptr\",in_scope=\"true\",type_changed=\"false\"\},\{name=\"psnp->char_ptr.\\*psnp->char_ptr\",in_scope=\"true\",type_changed=\"false\"\},\{name=\"psnp->char_ptr.\\*psnp->char_ptr.\\*\\*psnp->char_ptr\",in_scope=\"true\",type_changed=\"false\"\},\{name=\"psnp->char_ptr.\\*psnp->char_ptr.\\*\\*psnp->char_ptr.\\*\\*\\*psnp->char_ptr\",in_scope=\"true\",type_changed=\"false\"\},\{name=\"psnp->char_ptr.\\*psnp->char_ptr.\\*\\*psnp->char_ptr.\\*\\*\\*psnp->char_ptr.\\*\\*\\*\\*psnp->char_ptr\",in_scope=\"true\",type_changed=\"false\"\}\\\]" \ + "update all vars psnp->char_ptr (and 0.char_ptr) changed" + +# Step over "snp1.char_ptr = &c3;" +set line 256 +mi_step_to do_children_tests {} {.*var-cmd.c} $line "step $line" + +# Test: c_variable-5.48 +# Desc: check that psnp->next->char_ptr (and [1].char_ptr) changed +mi_gdb_test "-var-update *" \ + "\\^done,changelist=\\\[\{name=\"psnp->ptrs.0.next.char_ptr\",in_scope=\"true\",type_changed=\"false\"\},\{name=\"psnp->ptrs.0.next.char_ptr.\\*char_ptr\",in_scope=\"true\",type_changed=\"false\"\},\{name=\"psnp->ptrs.0.next.char_ptr.\\*char_ptr.\\*\\*char_ptr\",in_scope=\"true\",type_changed=\"false\"\},\{name=\"psnp->ptrs.0.next.char_ptr.\\*char_ptr.\\*\\*char_ptr.\\*\\*\\*char_ptr\",in_scope=\"true\",type_changed=\"false\"\},\{name=\"psnp->ptrs.0.next.char_ptr.\\*char_ptr.\\*\\*char_ptr.\\*\\*\\*char_ptr.\\*\\*\\*\\*char_ptr\",in_scope=\"true\",type_changed=\"false\"\}\\\]" \ + "update all vars psnp->next->char_ptr (and 1.char_ptr) changed" + + +# Step over "snp2.char_ptr = &a3;" +set line 257 +mi_step_to do_children_tests {} {.*var-cmd.c} $line "step $line" + +# Test: c_variable-5.49 +# Desc: check that psnp->next->next->char_ptr (and [2].char_ptr) changed +mi_gdb_test "-var-update *" \ + "\\^done,changelist=\\\[\{name=\"psnp->ptrs.0.next.next.char_ptr\",in_scope=\"true\",type_changed=\"false\"\}\\\]" \ + "update all vars psnp->next->next->char_ptr (and 2.char_ptr) changed" + + +# Step over "snp0.long_ptr = &y3;" +set line 258 +mi_step_to do_children_tests {} {.*var-cmd.c} $line "step $line" + +# Test: c_variable-5.50 +# Desc: check that psnp->long_ptr (and [0].long_ptr) changed +mi_gdb_test "-var-update *" \ + "\\^done,changelist=\\\[\{name=\"psnp->ptrs.0.long_ptr\",in_scope=\"true\",type_changed=\"false\"\},\{name=\"psnp->long_ptr\",in_scope=\"true\",type_changed=\"false\"\},\{name=\"psnp->long_ptr.\\*psnp->long_ptr\",in_scope=\"true\",type_changed=\"false\"\},\{name=\"psnp->long_ptr.\\*psnp->long_ptr.\\*\\*psnp->long_ptr\",in_scope=\"true\",type_changed=\"false\"\},\{name=\"psnp->long_ptr.\\*psnp->long_ptr.\\*\\*psnp->long_ptr.\\*\\*\\*psnp->long_ptr\",in_scope=\"true\",type_changed=\"false\"\},\{name=\"psnp->long_ptr.\\*psnp->long_ptr.\\*\\*psnp->long_ptr.\\*\\*\\*psnp->long_ptr.\\*\\*\\*\\*psnp->long_ptr\",in_scope=\"true\",type_changed=\"false\"\}\\\]" \ + "update all vars psnp->long_ptr (and 0.long_ptr) changed" + + +# Step over "snp1.long_ptr = &x3;" +set line 259 +mi_step_to do_children_tests {} {.*var-cmd.c} $line "step $line" + +# Test: c_variable-5.51 +# Desc: check that psnp->next->long_ptr (and [1].long_ptr) changed +# Why does this have a FIXME? +setup_xfail *-*-* +mi_gdb_test "-var-update *" \ + "FIXME\\^done,changelist=\\\[\{name=\"psnp->ptrs.0.next.long_ptr\",in_scope=\"true\",type_changed=\"false\"\}\\\]" \ + "update all vars psnp->next->long_ptr (and 1.long_ptr) changed" +clear_xfail *-*-* + +# This command produces this error message: +# &"warning: varobj_list: assertion failed - mycount <> 0\n" +# + +# Step over "snp2.long_ptr = &z3;" +set line 260 +mi_step_to do_children_tests {} {.*var-cmd.c} $line "step $line" + +# Test: c_variable-5.52 +# Desc: check that psnp->next->next->long_ptr (and [2].long_ptr) changed +mi_gdb_test "-var-update *" \ + "\\^done,changelist=\\\[\{name=\"psnp->ptrs.0.next.next.long_ptr\",in_scope=\"true\",type_changed=\"false\"\}\\\]" \ + "update all vars psnp->next->next->long_ptr (and 2.long_ptr) changed" + + + + +mi_gdb_exit +return 0 diff --git a/gdb/testsuite/gdb.mi/mi2-var-cmd.exp b/gdb/testsuite/gdb.mi/mi2-var-cmd.exp new file mode 100644 index 0000000..25326df --- /dev/null +++ b/gdb/testsuite/gdb.mi/mi2-var-cmd.exp @@ -0,0 +1,560 @@ +# Copyright (C) 1999, 2000, 2002 Free Software Foundation, Inc. +# +# This Program Is Free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# Please email any bugs, comments, and/or additions to this file to: +# bug-gdb@prep.ai.mit.edu + +# Test essential Machine interface (MI) operations +# +# Verify that, using the MI, we can create, update, delete variables. +# + + +load_lib mi-support.exp +set MIFLAGS "-i=mi2" + +gdb_exit +if [mi_gdb_start] { + continue +} + +set testfile "var-cmd" +set srcfile ${testfile}.c +set binfile ${objdir}/${subdir}/${testfile} +if { [gdb_compile "${srcdir}/${subdir}/${srcfile}" "${binfile}" executable {debug additional_flags=-DFAKEARGV}] != "" } { + gdb_suppress_entire_file "Testcase compile failed, so all tests in this file will automatically fail." +} + +mi_delete_breakpoints +mi_gdb_reinitialize_dir $srcdir/$subdir +mi_gdb_load ${binfile} + + +##### ##### +# # +# Variable Creation tests # +# # +##### ##### + +# Test: c_variable-1.1 +# Desc: Create global variable + +mi_gdb_test "111-var-create global_simple * global_simple" \ + "111\\^done,name=\"global_simple\",numchild=\"6\",type=\"simpleton\"" \ + "create global variable" + +# Test: c_variable-1.2 +# Desc: Create non-existent variable + +mi_gdb_test "112-var-create bogus_unknown_variable * bogus_unknown_variable" \ + "&\"mi_cmd_var_create: unable to create variable object\\\\n\".*112\\^error,msg=\"mi_cmd_var_create: unable to create variable object\"" \ + "create non-existent variable" + +# Test: c_variable-1.3 +# Desc: Create out of scope variable + +mi_gdb_test "113-var-create argc * argc" \ + "&\"mi_cmd_var_create: unable to create variable object\\\\n\".*113\\^error,msg=\"mi_cmd_var_create: unable to create variable object\"" \ + "create out of scope variable" + +mi_runto do_locals_tests + +# Test: c_variable-1.4 +# Desc: create local variables + +mi_gdb_test "-var-create linteger * linteger" \ + "\\^done,name=\"linteger\",numchild=\"0\",type=\"int\"" \ + "create local variable linteger" + +mi_gdb_test "-var-create lpinteger * lpinteger" \ + "\\^done,name=\"lpinteger\",numchild=\"1\",type=\"int \\*\"" \ + "create local variable lpinteger" + +mi_gdb_test "-var-create lcharacter * lcharacter" \ + "\\^done,name=\"lcharacter\",numchild=\"0\",type=\"char\"" \ + "create local variablelcharacter " + +mi_gdb_test "-var-create lpcharacter * lpcharacter" \ + "\\^done,name=\"lpcharacter\",numchild=\"1\",type=\"char \\*\"" \ + "create local variable lpcharacter" + +mi_gdb_test "-var-create llong * llong" \ + "\\^done,name=\"llong\",numchild=\"0\",type=\"long int\"" \ + "create local variable llong" + +mi_gdb_test "-var-create lplong * lplong" \ + "\\^done,name=\"lplong\",numchild=\"1\",type=\"long int \\*\"" \ + "create local variable lplong" + +mi_gdb_test "-var-create lfloat * lfloat" \ + "\\^done,name=\"lfloat\",numchild=\"0\",type=\"float\"" \ + "create local variable lfloat" + +mi_gdb_test "-var-create lpfloat * lpfloat" \ + "\\^done,name=\"lpfloat\",numchild=\"1\",type=\"float \\*\"" \ + "create local variable lpfloat" + +mi_gdb_test "-var-create ldouble * ldouble" \ + "\\^done,name=\"ldouble\",numchild=\"0\",type=\"double\"" \ + "create local variable ldouble" + +mi_gdb_test "-var-create lpdouble * lpdouble" \ + "\\^done,name=\"lpdouble\",numchild=\"1\",type=\"double \\*\"" \ + "create local variable lpdouble" + +mi_gdb_test "-var-create lsimple * lsimple" \ + "\\^done,name=\"lsimple\",numchild=\"6\",type=\"struct _simple_struct\"" \ + "create local variable lsimple" + +mi_gdb_test "-var-create lpsimple * lpsimple" \ + "\\^done,name=\"lpsimple\",numchild=\"6\",type=\"struct _simple_struct \\*\"" \ + "create local variable lpsimple" + +mi_gdb_test "-var-create func * func" \ + "\\^done,name=\"func\",numchild=\"0\",type=\"void \\(\\*\\)\\((void|)\\)\"" \ + "create local variable func" + +# Test: c_variable-1.5 +# Desc: create lsimple.character +mi_gdb_test "-var-create lsimple.character * lsimple.character" \ + "\\^done,name=\"lsimple.character\",numchild=\"0\",type=\"char\"" \ + "create lsimple.character" + +# Test: c_variable-1.6 +# Desc: create lpsimple->integer +mi_gdb_test "-var-create lsimple->integer * lsimple->integer" \ + "\\^done,name=\"lsimple->integer\",numchild=\"0\",type=\"int\"" \ + "create lsimple->integer" + +# Test: c_variable-1.7 +# Desc: ceate lsimple.integer +mi_gdb_test "-var-create lsimple.integer * lsimple.integer" \ + "\\^done,name=\"lsimple.integer\",numchild=\"0\",type=\"int\"" \ + "create lsimple->integer" + + +# Test: c_variable-1.9 +# Desc: create type name +# Type names (like int, long, etc..) are all proper expressions to gdb. +# make sure variable code does not allow users to create variables, though. +mi_gdb_test "-var-create int * int" \ + "&\"Attempt to use a type name as an expression.mi_cmd_var_create: unable to create variable object\\\\n\".*\\^error,msg=\"mi_cmd_var_create: unable to create variable object\"" \ + "create int" + + +##### ##### +# # +# Value changed tests # +# # +##### ##### + +# Test: c_variable-2.1 +# Desc: check whether values changed at do_block_tests +mi_gdb_test "-var-update *" \ + "\\^done,changelist=\\\[\\\]" \ + "update all vars" + +# Step over "linteger = 1234;" +mi_step_to "do_locals_tests" "" "var-cmd.c" "107" "step at do_locals_test" + +# Test: c_variable-2.2 +# Desc: check whether only linteger changed values +mi_gdb_test "-var-update *" \ + "\\^done,changelist=\\\[\{name=\"linteger\",in_scope=\"true\",type_changed=\"false\"\}\\\]" \ + "update all vars: linteger changed" + +# Step over "lpinteger = &linteger;" +mi_step_to "do_locals_tests" "" "var-cmd.c" 108 "step at do_locals_tests (2)" + +# Test: c_variable-2.3 +# Desc: check whether only lpinteger changed +mi_gdb_test "-var-update *" \ + "\\^done,changelist=\\\[\{name=\"lpinteger\",in_scope=\"true\",type_changed=\"false\"\}\\\]" \ + "update all vars: lpinteger changed" + +# Step over "lcharacter = 'a';" +mi_step_to "do_locals_tests" "" "var-cmd.c" "109" "step at do_locals_tests (3)" + +# Test: c_variable-2.4 +# Desc: check whether only lcharacter changed +mi_gdb_test "-var-update *" \ + "\\^done,changelist=\\\[\{name=\"lcharacter\",in_scope=\"true\",type_changed=\"false\"\}\\\]" \ + "update all vars: lcharacter changed" + +# Step over "lpcharacter = &lcharacter;" +mi_step_to "do_locals_tests" "" "var-cmd.c" "110" "step at do_locals_tests (4)" + +# Test: c_variable-2.5 +# Desc: check whether only lpcharacter changed +mi_gdb_test "-var-update *" \ + "\\^done,changelist=\\\[\{name=\"lpcharacter\",in_scope=\"true\",type_changed=\"false\"\}\\\]" \ + "update all vars: lpcharacter changed" + + +# Step over: +# llong = 2121L; +# lplong = &llong; +# lfloat = 2.1; +# lpfloat = &lfloat; +# ldouble = 2.718281828459045; +# lpdouble = &ldouble; +# lsimple.integer = 1234; +# lsimple.unsigned_integer = 255; +# lsimple.character = 'a'; + +mi_execute_to "exec-step 9" "end-stepping-range" "do_locals_tests" "" \ + "var-cmd.c" "119" "" "step at do_locals_tests (5)" + +# Test: c_variable-2.6 +# Desc: check whether llong, lplong, lfloat, lpfloat, ldouble, lpdouble, lsimple.integer, +# lsimple.unsigned_character lsimple.integer lsimple.character changed +mi_gdb_test "-var-update *" \ + "\\^done,changelist=\\\[\{name=\"lsimple.integer\",in_scope=\"true\",type_changed=\"false\"\},\{name=\"lsimple->integer\",in_scope=\"true\",type_changed=\"false\"\},\{name=\"lsimple.character\",in_scope=\"true\",type_changed=\"false\"\},\{name=\"lpdouble\",in_scope=\"true\",type_changed=\"false\"\},\{name=\"ldouble\",in_scope=\"true\",type_changed=\"false\"\},\{name=\"lpfloat\",in_scope=\"true\",type_changed=\"false\"\},\{name=\"lfloat\",in_scope=\"true\",type_changed=\"false\"\},\{name=\"lplong\",in_scope=\"true\",type_changed=\"false\"\},\{name=\"llong\",in_scope=\"true\",type_changed=\"false\"\}\\\]" \ + "update all vars: many changed" + +# Step over: +# lsimple.signed_character = 21; +# lsimple.char_ptr = &lcharacter; +# lpsimple = &lsimple; +# func = nothing; + +mi_execute_to "exec-step 4" "end-stepping-range" "do_locals_tests" "" \ + "var-cmd.c" "125" "" "step at do_locals_tests (6)" + +# Test: c_variable-2.7 +# Desc: check whether (lsimple.signed_character, lsimple.char_ptr) lpsimple, func changed +mi_gdb_test "-var-update *" \ + "\\^done,changelist=\\\[\{name=\"func\",in_scope=\"true\",type_changed=\"false\"\},\{name=\"lpsimple\",in_scope=\"true\",type_changed=\"false\"\}\\\]" \ + "update all vars: func and lpsimple changed" + +# Step over +# linteger = 4321; +# lcharacter = 'b'; +# llong = 1212L; +# lfloat = 1.2; +# ldouble = 5.498548281828172; +# lsimple.integer = 255; +# lsimple.unsigned_integer = 4321; +# lsimple.character = 'b'; + +mi_execute_to "exec-step 8" "end-stepping-range" "do_locals_tests" "" \ + "var-cmd.c" "133" "" "step at do_locals_tests (7)" + +# Test: c_variable-2.8 +# Desc: check whether linteger, lcharacter, llong, lfoat, ldouble, lsimple.integer, +# lpsimple.integer lsimple.character changed +# Note: this test also checks that lpsimple->integer and lsimple.integer have +# changed (they are the same) +mi_gdb_test "-var-update *" \ + "\\^done,changelist=\\\[\{name=\"lsimple.integer\",in_scope=\"true\",type_changed=\"false\"\},\{name=\"lsimple->integer\",in_scope=\"true\",type_changed=\"false\"\},\{name=\"lsimple.character\",in_scope=\"true\",type_changed=\"false\"\},\{name=\"ldouble\",in_scope=\"true\",type_changed=\"false\"\},\{name=\"lfloat\",in_scope=\"true\",type_changed=\"false\"\},\{name=\"llong\",in_scope=\"true\",type_changed=\"false\"\},\{name=\"lcharacter\",in_scope=\"true\",type_changed=\"false\"\},\{name=\"linteger\",in_scope=\"true\",type_changed=\"false\"\}\\\]" \ + "update all vars: func and lpsimple changed" + + +### +# +# Test assignment to variables. More tests on assignment are in other files. +# +### +mi_gdb_test "-var-assign global_simple 0" \ + "&\"mi_cmd_var_assign: Variable object is not editable\\\\n\".*\\^error,msg=\"mi_cmd_var_assign: Variable object is not editable\"" \ + "assign to global_simple" + +mi_gdb_test "-var-assign linteger 3333" \ + "\\^done,value=\"3333\"" \ + "assign to linteger" + +mi_gdb_test "-var-update *" \ + "\\^done,changelist=\\\[\{name=\"linteger\",in_scope=\"true\",type_changed=\"false\"\}\\\]" \ + "update all vars: linteger changed after assign" + +mi_gdb_test "-var-assign linteger 3333" \ + "\\^done,value=\"3333\"" \ + "assign to linteger again, same value" + +mi_gdb_test "-var-update *" \ + "\\^done,changelist=\\\[\\\]" \ + "update all vars: linteger not changed after same assign" + +mi_gdb_test "-var-evaluate-expression linteger" \ + "\\^done,value=\"3333\"" \ + "eval linteger" + +mi_gdb_test "-var-assign lpinteger \"&linteger + 3\"" \ + "\\^done,value=\"$hex\"" \ + "assign to lpinteger" + +mi_gdb_test "-var-update *" \ + "\\^done,changelist=\\\[\{name=\"lpinteger\",in_scope=\"true\",type_changed=\"false\"\}\\\]" \ + "update all vars: lpinteger changed after assign" + +mi_gdb_test "-var-update *" \ + "\\^done,changelist=\\\[\\\]" \ + "update all vars: no changes on second update" + +mi_gdb_test "-var-evaluate-expression lpinteger" \ + "\\^done,value=\"$hex\"" \ + "eval lpinteger" + +# reset the values to the original ones so that the rest of the file doesn't suffer. + +mi_gdb_test "-var-assign linteger 4321" \ + "\\^done,value=\"4321\"" \ + "assign to linteger" + +mi_gdb_test "-var-assign lpinteger &linteger" \ + "\\^done,value=\"$hex\"" \ + "assign to lpinteger" + +mi_gdb_test "-var-assign lcharacter 'z'" \ + "\\^done,value=\"122 'z'\"" \ + "assign to lcharacter" + +mi_gdb_test "-var-evaluate-expression lcharacter" \ + "\\^done,value=\"122 'z'\"" \ + "eval lcharacter" + +mi_gdb_test "-var-assign llong 1313L" \ + "\\^done,value=\"1313\"" \ + "assign to llong" +mi_gdb_test "-var-evaluate-expression llong" \ + "\\^done,value=\"1313\"" \ + "eval llong" +mi_gdb_test "-var-assign llong 1212L" \ + "\\^done,value=\"1212\"" \ + "assign to llong" + +mi_gdb_test "-var-assign lplong &llong+4" \ + "\\^done,value=\"$hex\"" \ + "assign to lplong" +mi_gdb_test "-var-evaluate-expression lplong" \ + "\\^done,value=\"$hex\"" \ + "eval lplong" +mi_gdb_test "-var-assign lplong &llong" \ + "\\^done,value=\"$hex\"" \ + "assign to lplong" + +mi_gdb_test "-var-assign lfloat 3.4567" \ + "\\^done,value=\"3.45.*\"" \ + "assign to lfloat" +mi_gdb_test "-var-evaluate-expression lfloat" \ + "\\^done,value=\"3.45.*\"" \ + "eval lfloat" +mi_gdb_test "-var-assign lfloat 1.2345" \ + "\\^done,value=\"1.23.*\"" \ + "assign to lfloat" + +mi_gdb_test "-var-assign lpfloat &lfloat+4" \ + "\\^done,value=\"$hex\"" \ + "assign to lpfloat" + +mi_gdb_test "-var-assign ldouble 5.333318284590435" \ + "\\^done,value=\"5.333318284590435\"" \ + "assign to ldouble" + +mi_gdb_test "-var-assign func do_block_tests" \ + "\\^done,value=\"$hex \"" \ + "assign to func" + +mi_gdb_test "-var-assign lsimple.character 'd'" \ + "\\^done,value=\"100 'd'\"" \ + "assign to lsimple.character" + +mi_gdb_test "-var-assign lsimple->integer 222" \ + "\\^done,value=\"222\"" \ + "assign to lsimple->integer" + +mi_gdb_test "-var-assign lsimple.integer 333" \ + "\\^done,value=\"333\"" \ + "assign to lsimple.integer" + +###### +# End of assign tests +##### + +mi_gdb_test "-break-insert subroutine1" \ + "\\^done,bkpt=\{number=\"2\",type=\"breakpoint\",disp=\"keep\",enabled=\"y\",addr=\"$hex\",func=\"subroutine1\",file=\".*var-cmd.c\",line=\"146\",times=\"0\"\}" \ + "break-insert subroutine1" +mi_continue_to "2" "subroutine1" \ + "\{name=\"i\",value=\"4321\"\},\{name=\"l\",value=\"$hex\"\}" \ + "var-cmd.c" "146" "continue to subroutine1" + +# Test: c_variable-2.10 +# Desc: create variable for locals i,l in subroutine1 +mi_gdb_test "-var-create i * i" \ + "\\^done,name=\"i\",numchild=\"0\",type=\"int\"" \ + "create i" + +mi_gdb_test "-var-create l * l" \ + "\\^done,name=\"l\",numchild=\"1\",type=\"long int \\*\"" \ + "create l" + +# Test: c_variable-2.11 +# Desc: create do_locals_tests local in subroutine1 +mi_gdb_test "-var-create linteger * linteger" \ + "&\"mi_cmd_var_create: unable to create variable object\\\\n\".*\\^error,msg=\"mi_cmd_var_create: unable to create variable object\"" \ + "create linteger" + +mi_step_to "subroutine1" "\{name=\"i\",value=\".*\"\},\{name=\"l\",value=\".*\"\}" \ + "var-cmd.c" "147" "step at subroutine1" + +# Test: c_variable-2.12 +# Desc: change global_simple.integer +# Note: This also tests whether we are reporting changes in structs properly. +# gdb normally would say that global_simple has changed, but we +# special case that, since it is not what a human expects to +# see. + +setup_xfail *-*-* +mi_gdb_test "-var-update *" \ + "\\^done,changelist=\{FIXME: WHAT IS CORRECT HERE\}" \ + "update all vars: changed FIXME" +clear_xfail *-*-* + +mi_step_to "subroutine1" "\{name=\"i\",value=\".*\"\},\{name=\"l\",value=\".*\"\}" \ + "var-cmd.c" "148" "step at subroutine1 (2)" + +# Test: c_variable-2.13 +# Desc: change subroutine1 local i +mi_gdb_test "-var-update *" \ + "\\^done,changelist=\\\[\{name=\"i\",in_scope=\"true\",type_changed=\"false\"\}\\\]" \ + "update all vars: i changed" + +mi_step_to "subroutine1" "\{name=\"i\",value=\".*\"\},\{name=\"l\",value=\".*\"\}" \ + "var-cmd.c" "149" "step at subroutine1 (3)" + +# Test: c_variable-2.14 +# Desc: change do_locals_tests local llong +mi_gdb_test "-var-update *" \ + "\\^done,changelist=\\\[\{name=\"llong\",in_scope=\"true\",type_changed=\"false\"\}\\\]" \ + "update all vars: llong changed" + +mi_next_to "do_locals_tests" "" "var-cmd.c" "136" "next out of subroutine1" + +# Test: c_variable-2.15 +# Desc: check for out of scope subroutine1 locals +mi_gdb_test "-var-update *" \ + "\\^done,changelist=\\\[\{name=\"l\",in_scope=\"false\"\},\{name=\"i\",in_scope=\"false\"\}\\\]" \ + "update all vars: all now out of scope" + +# Done with locals/globals tests. Erase all variables +#delete_all_variables +mi_gdb_test "-var-delete global_simple" \ + "\\^done,ndeleted=\"1\"" \ + "delete var" + +mi_gdb_test "-var-delete linteger" \ + "\\^done,ndeleted=\"1\"" \ + "delete var linteger" + +mi_gdb_test "-var-delete lpinteger" \ + "\\^done,ndeleted=\"1\"" \ + "delete var lpinteger" + +mi_gdb_test "-var-delete lcharacter" \ + "\\^done,ndeleted=\"1\"" \ + "delete var lcharacter" + +mi_gdb_test "-var-delete lpcharacter" \ + "\\^done,ndeleted=\"1\"" \ + "delete var lpcharacter" + +mi_gdb_test "-var-delete llong" \ + "\\^done,ndeleted=\"1\"" \ + "delete var llong" + +mi_gdb_test "-var-delete lplong" \ + "\\^done,ndeleted=\"1\"" \ + "delete var lplong" + +mi_gdb_test "-var-delete lfloat" \ + "\\^done,ndeleted=\"1\"" \ + "delete var lfloat" + +mi_gdb_test "-var-delete lpfloat" \ + "\\^done,ndeleted=\"1\"" \ + "delete var lpfloat" + +mi_gdb_test "-var-delete ldouble" \ + "\\^done,ndeleted=\"1\"" \ + "delete var ldouble" + +mi_gdb_test "-var-delete lpdouble" \ + "\\^done,ndeleted=\"1\"" \ + "delete var lpdouble" + +mi_gdb_test "-var-delete lsimple" \ + "\\^done,ndeleted=\"1\"" \ + "delete var lsimple" + +mi_gdb_test "-var-delete lpsimple" \ + "\\^done,ndeleted=\"1\"" \ + "delete var lpsimple" + +mi_gdb_test "-var-delete func" \ + "\\^done,ndeleted=\"1\"" \ + "delete var func" + +mi_gdb_test "-var-delete lsimple.character" \ + "\\^done,ndeleted=\"1\"" \ + "delete var lsimple.character" + +mi_gdb_test "-var-delete lsimple->integer" \ + "\\^done,ndeleted=\"1\"" \ + "delete var lsimple->integer" + +mi_gdb_test "-var-delete lsimple.integer" \ + "\\^done,ndeleted=\"1\"" \ + "delete var lsimple.integer" + +mi_gdb_test "-var-delete i" \ + "\\^done,ndeleted=\"1\"" \ + "delete var i" + +mi_gdb_test "-var-delete l" \ + "\\^done,ndeleted=\"1\"" \ + "delete var l" + +# Test whether we can follow the name of a variable through multiple +# stack frames. +mi_gdb_test "-break-insert do_special_tests" \ + {\^done,bkpt=.*} \ + "set breakpoint at do_special_tests" + +mi_continue_to {.*} do_special_tests {.*} {.*var-cmd.c} {.*} {stop in do_special_tests} + +mi_gdb_test "-var-create selected_a @ a" \ + {\^done,name="selected_a",numchild="0",type="int"} \ + "create selected_a" + +mi_gdb_test "-break-insert incr_a" \ + {\^done,bkpt=.*} \ + "set breakpoint at incr_a" + +mi_continue_to {.*} incr_a {.*} {.*var-cmd.c} {.*} {stop in incr_a} + +mi_gdb_test "-var-update selected_a" \ + "\\^done,changelist=\\\[\{name=\"selected_a\",in_scope=\"true\",new_type=\"char\",new_num_children=\"0\"\}\\\]" \ + "update selected_a in incr_a" + +mi_next "step a line in incr_a" +mi_next "return from incr_a to do_special_tests" + +mi_gdb_test "-var-update selected_a" \ + "\\^done,changelist=\\\[\{name=\"selected_a\",in_scope=\"true\",new_type=\"int\",new_num_children=\"0\"\}\\\]" \ + "update selected_a in do_special_tests" + +mi_gdb_exit +return 0 diff --git a/gdb/testsuite/gdb.mi/mi2-var-display.exp b/gdb/testsuite/gdb.mi/mi2-var-display.exp new file mode 100644 index 0000000..3b0990d --- /dev/null +++ b/gdb/testsuite/gdb.mi/mi2-var-display.exp @@ -0,0 +1,627 @@ +# Copyright (C) 1999, 2000, 2002 Free Software Foundation, Inc. +# +# This Program Is Free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# Please email any bugs, comments, and/or additions to this file to: +# bug-gdb@prep.ai.mit.edu + +# Test essential Machine interface (MI) operations +# +# Verify that, using the MI, we can create, update, delete variables. +# + + +load_lib mi-support.exp +set MIFLAGS "-i=mi2" + +gdb_exit +if [mi_gdb_start] { + continue +} + +set testfile "var-cmd" +set srcfile ${testfile}.c +set binfile ${objdir}/${subdir}/${testfile} +if { [gdb_compile "${srcdir}/${subdir}/${srcfile}" "${binfile}" executable {debug additional_flags=-DFAKEARGV}] != "" } { + gdb_suppress_entire_file "Testcase compile failed, so all tests in this file will automatically fail." +} + +mi_delete_breakpoints +mi_gdb_reinitialize_dir $srcdir/$subdir +mi_gdb_load ${binfile} + +mi_gdb_test "200-break-insert 260" \ + "200\\^done,bkpt=\{number=\"1\",type=\"breakpoint\",disp=\"keep\",enabled=\"y\",addr=\"$hex\",func=\"do_children_tests\",file=\".*var-cmd.c\",line=\"260\",times=\"0\"\}" \ + "break-insert operation" + +mi_run_cmd +# The running part has been checked already by mi_run_cmd +gdb_expect { + -re "\[\r\n\]*000\\*stopped,reason=\"breakpoint-hit\",bkptno=\"1\",thread-id=\"\[01\]\",frame=\{addr=\"$hex\",func=\"do_children_tests\",args=\\\[\\\],file=\".*var-cmd.c\",line=\"260\"\}\r\n$mi_gdb_prompt$" { + pass "run to do_children_tests" + } + -re ".*$mi_gdb_prompt$" {fail "run to do_children_tests (2)"} + timeout {fail "run to do_children_tests (timeout 2)"} +} + +##### ##### +# # +# Display tests # +# # +##### ##### + +# Test: c_variable-6.1 +# Desc: create variable bar +mi_gdb_test "-var-create bar * bar" \ + "\\^done,name=\"bar\",numchild=\"0\",type=\"int\"" \ + "create local variable bar" + +# Test: c_variable-6.2 +# Desc: type of variable bar +mi_gdb_test "-var-info-type bar" \ + "\\^done,type=\"int\"" \ + "info type variable bar" + +# Test: c_variable-6.3 +# Desc: format of variable bar +mi_gdb_test "-var-show-format bar" \ + "\\^done,format=\"natural\"" \ + "show format variable bar" + +# Test: c_variable-6.4 +# Desc: value of variable bar +mi_gdb_test "-var-evaluate-expression bar" \ + "\\^done,value=\"2121\"" \ + "eval variable bar" + +# Test: c_variable-6.5 +# Desc: change format of bar to hex +mi_gdb_test "-var-set-format bar hexadecimal" \ + "\\^done,format=\"hexadecimal\"" \ + "set format variable bar" + +# Test: c_variable-6.6 +# Desc: value of bar with new format +mi_gdb_test "-var-evaluate-expression bar" \ + "\\^done,value=\"0x849\"" \ + "eval variable bar with new format" + +# Test: c_variable-6.7 +# Desc: change value of bar +mi_gdb_test "-var-assign bar 3" \ + "\\^done,value=\"0x3\"" \ + "assing to variable bar" + +mi_gdb_test "-var-set-format bar decimal" \ + "\\^done,format=\"decimal\"" \ + "set format variable bar" + +mi_gdb_test "-var-evaluate-expression bar" \ + "\\^done,value=\"3\"" \ + "eval variable bar with new value" + +mi_gdb_test "-var-delete bar" \ + "\\^done,ndeleted=\"1\"" \ + "delete var bar" + +# Test: c_variable-6.11 +# Desc: create variable foo +mi_gdb_test "-var-create foo * foo" \ + "\\^done,name=\"foo\",numchild=\"1\",type=\"int \\*\"" \ + "create local variable foo" + +# Test: c_variable-6.12 +# Desc: type of variable foo +mi_gdb_test "-var-info-type foo" \ + "\\^done,type=\"int \\*\"" \ + "info type variable foo" + +# Test: c_variable-6.13 +# Desc: format of variable foo +mi_gdb_test "-var-show-format foo" \ + "\\^done,format=\"natural\"" \ + "show format variable foo" + +# Test: c_variable-6.14 +# Desc: value of variable foo +mi_gdb_test "-var-evaluate-expression foo" \ + "\\^done,value=\"$hex\"" \ + "eval variable foo" + +# Test: c_variable-6.15 +# Desc: change format of var to octal +mi_gdb_test "-var-set-format foo octal" \ + "\\^done,format=\"octal\"" \ + "set format variable foo" + +mi_gdb_test "-var-show-format foo" \ + "\\^done,format=\"octal\"" \ + "show format variable foo" + +# Test: c_variable-6.16 +# Desc: value of foo with new format +mi_gdb_test "-var-evaluate-expression foo" \ + "\\^done,value=\"\[0-7\]+\"" \ + "eval variable foo" + +# Test: c_variable-6.17 +# Desc: change value of foo +mi_gdb_test "-var-assign foo 3" \ + "\\^done,value=\"03\"" \ + "assing to variable foo" + +mi_gdb_test "-var-set-format foo decimal" \ + "\\^done,format=\"decimal\"" \ + "set format variable foo" + +# Test: c_variable-6.18 +# Desc: check new value of foo +mi_gdb_test "-var-evaluate-expression foo" \ + "\\^done,value=\"3\"" \ + "eval variable foo" + +mi_gdb_test "-var-delete foo" \ + "\\^done,ndeleted=\"1\"" \ + "delete var foo" + +# Test: c_variable-6.21 +# Desc: create variable weird and children +mi_gdb_test "-var-create weird * weird" \ + "\\^done,name=\"weird\",numchild=\"11\",type=\"weird_struct \\*\"" \ + "create local variable weird" + +mi_gdb_test "-var-list-children weird" \ + "\\^done,numchild=\"11\",children=\\\[child=\{name=\"weird.integer\",exp=\"integer\",numchild=\"0\",type=\"int\"\},child=\{name=\"weird.character\",exp=\"character\",numchild=\"0\",type=\"char\"\},child={name=\"weird.char_ptr\",exp=\"char_ptr\",numchild=\"1\",type=\"char \\*\"\},child=\{name=\"weird.long_int\",exp=\"long_int\",numchild=\"0\",type=\"long int\"\},child=\{name=\"weird.int_ptr_ptr\",exp=\"int_ptr_ptr\",numchild=\"1\",type=\"int \\*\\*\"\},child=\{name=\"weird.long_array\",exp=\"long_array\",numchild=\"10\",type=\"long int \\\[10\\\]\"\},child=\{name=\"weird.func_ptr\",exp=\"func_ptr\",numchild=\"0\",type=\"void \\(\\*\\)\\((void|)\\)\"\},child=\{name=\"weird.func_ptr_struct\",exp=\"func_ptr_struct\",numchild=\"0\",type=\"struct _struct_decl \\(\\*\\)\\((int, char \\*, long int|)\\)\"\},child=\{name=\"weird.func_ptr_ptr\",exp=\"func_ptr_ptr\",numchild=\"0\",type=\"struct _struct_decl \\*\\(\\*\\)\\((int, char \\*, long int|)\\)\"\},child=\{name=\"weird.u1\",exp=\"u1\",numchild=\"4\",type=\"union \{\\.\\.\\.\}\"\},child=\{name=\"weird.s2\",exp=\"s2\",numchild=\"4\",type=\"struct \{\\.\\.\\.\}\"\}\\\]" \ + "get children local variable weird" + + +# Test: c_variable-6.23 +# Desc: change format of weird.func_ptr and weird.func_ptr_ptr +mi_gdb_test "-var-set-format weird.func_ptr hexadecimal" \ + "\\^done,format=\"hexadecimal\"" \ + "set format variable weird.func_ptr" + +mi_gdb_test "-var-show-format weird.func_ptr" \ + "\\^done,format=\"hexadecimal\"" \ + "show format variable weird.func_ptr" + +mi_gdb_test "-var-set-format weird.func_ptr_ptr hexadecimal" \ + "\\^done,format=\"hexadecimal\"" \ + "set format variable weird.func_ptr_ptr" + +mi_gdb_test "-var-show-format weird.func_ptr_ptr" \ + "\\^done,format=\"hexadecimal\"" \ + "show format variable weird.func_ptr_ptr" + +# Test: c_variable-6.24 +# Desc: format of weird and children +mi_gdb_test "-var-set-format weird natural" \ + "\\^done,format=\"natural\"" \ + "set format variable weird" + +mi_gdb_test "-var-set-format weird.integer natural" \ + "\\^done,format=\"natural\"" \ + "set format variable weird.integer" + +mi_gdb_test "-var-set-format weird.character natural" \ + "\\^done,format=\"natural\"" \ + "set format variable weird.character" + +mi_gdb_test "-var-set-format weird.char_ptr natural" \ + "\\^done,format=\"natural\"" \ + "set format variable weird.char_ptr" + +mi_gdb_test "-var-set-format weird.long_int natural" \ + "\\^done,format=\"natural\"" \ + "set format variable weird.long_int" + +mi_gdb_test "-var-set-format weird.int_ptr_ptr natural" \ + "\\^done,format=\"natural\"" \ + "set format variable weird.int_ptr_ptr" + +mi_gdb_test "-var-set-format weird.long_array natural" \ + "\\^done,format=\"natural\"" \ + "set format variable weird.long_array" + +mi_gdb_test "-var-set-format weird.func_ptr hexadecimal" \ + "\\^done,format=\"hexadecimal\"" \ + "set format variable weird.func_ptr" + +mi_gdb_test "-var-set-format weird.func_ptr_struct hexadecimal" \ + "\\^done,format=\"hexadecimal\"" \ + "set format variable weird.func_ptr_struct" + +mi_gdb_test "-var-set-format weird.func_ptr_ptr natural" \ + "\\^done,format=\"natural\"" \ + "set format variable weird.func_ptr_ptr" + +mi_gdb_test "-var-set-format weird.u1 natural" \ + "\\^done,format=\"natural\"" \ + "set format variable weird.u1" + +mi_gdb_test "-var-set-format weird.s2 natural" \ + "\\^done,format=\"natural\"" \ + "set format variable weird.s2" + +# Test: c_variable-6.25 +# Desc: value of weird and children +#gdbtk_test c_variable-6.25 {value of weird and children} { +# set values {} +# foreach v [lsort [array names var]] f [list x "" "" x x x x d d d d d] { +# lappend values [value $v $f] +# } + +# set values +#} {ok ok ok ok ok ok ok ok weird.long_array ok weird.s2 weird.u1} + +# Test: c_variable-6.26 +# Desc: change format of weird and children to octal +#gdbtk_test c_variable-6.26 {change format of weird and children to octal} { +# set formats {} +# foreach v [lsort [array names var]] { +# $var($v) format octal +# lappend formats [$var($v) format] +# } + +# set formats +#} {octal octal octal octal octal octal octal octal octal octal octal octal} + +# Test: c_variable-6.27 +# Desc: value of weird and children with new format +#gdbtk_test c_variable-6.27 {value of foo with new format} { +# set values {} +# foreach v [lsort [array names var]] { +# lappend values [value $v o] +# } + +# set values +#} {ok ok ok ok ok ok ok ok weird.long_array ok weird.s2 weird.u1} + +# Test: c_variable-6.30 +# Desc: create more children of weird +#gdbtk_test c_variable-6.30 {create more children of weird} { +# foreach v [array names var] { +# get_children $v +# } + +# # Do it twice to get more children +# foreach v [array names var] { +# get_children $v +# } + +# lsort [array names var] +#} {weird weird.char_ptr weird.character weird.func_ptr weird.func_ptr_ptr weird.func_ptr_struct weird.int_ptr_ptr weird.int_ptr_ptr.*int_ptr_ptr weird.int_ptr_ptr.*int_ptr_ptr.**int_ptr_ptr weird.integer weird.long_array weird.long_array.0 weird.long_array.1 weird.long_array.2 weird.long_array.3 weird.long_array.4 weird.long_array.5 weird.long_array.6 weird.long_array.7 weird.long_array.8 weird.long_array.9 weird.long_int weird.s2 weird.s2.g weird.s2.h weird.s2.i weird.s2.i.0 weird.s2.i.1 weird.s2.i.2 weird.s2.i.3 weird.s2.i.4 weird.s2.i.5 weird.s2.i.6 weird.s2.i.7 weird.s2.i.8 weird.s2.i.9 weird.s2.u2 weird.s2.u2.f weird.s2.u2.u1s1 weird.s2.u2.u1s2 weird.u1 weird.u1.a weird.u1.b weird.u1.c weird.u1.d} + +# Test: c_variable-6.31 +# Desc: check that all children of weird change +# Ok, obviously things like weird.s2 and weird.u1 will not change! +#gdbtk_test *c_variable-6.31 {check that all children of weird change (ops, we are now reporting array names as changed in this case - seems harmless though)} { +# $var(weird) value 0x2121 +# check_update +#} {{weird.integer weird.character weird.char_ptr weird.long_int weird.int_ptr_ptr weird.int_ptr_ptr.*int_ptr_ptr weird.int_ptr_ptr.*int_ptr_ptr.**int_ptr_ptr weird.long_array.0 weird.long_array.1 weird.long_array.2 weird.long_array.3 weird.long_array.4 weird.long_array.5 weird.long_array.6 weird.long_array.7 weird.long_array.8 weird.long_array.9 weird.func_ptr weird.func_ptr_struct weird.func_ptr_ptr weird.u1.a weird.u1.b weird.u1.c weird.u1.d weird.s2.u2.f weird.s2.g weird.s2.h weird.s2.i.0 weird.s2.i.1 weird.s2.i.2 weird.s2.i.3 weird.s2.i.4 weird.s2.i.5 weird.s2.i.6 weird.s2.i.7 weird.s2.i.8 weird.s2.i.9} {weird.s2.i weird.s2.u2 weird weird.s2.u2.u1s1 weird.s2.u2.u1s2 weird.s2 weird.long_array weird.u1} {}} + +mi_gdb_test "-var-delete weird" \ + "\\^done,ndeleted=\"12\"" \ + "delete var weird" + + +##### ##### +# # +# Special Display Tests # +# # +##### ##### + +# Stop in "do_special_tests" +mi_gdb_test "200-break-insert do_special_tests" \ + "200\\^done,bkpt=\{number=\"2\",type=\"breakpoint\",disp=\"keep\",enabled=\"y\",addr=\"$hex\",func=\"do_special_tests\",file=\".*var-cmd.c\",line=\"282\",times=\"0\"\}" \ + "break-insert operation" + +send_gdb "-exec-continue\n" +gdb_expect { + -re "\\^running\r\n${mi_gdb_prompt}\\*stopped,reason=\"breakpoint-hit\",bkptno=\"2\",thread-id=\"\[01\]\",frame=\{addr=\"$hex\",func=\"do_special_tests\",args=\\\[\\\],file=\".*var-cmd.c\",line=\"282\"\}\r\n$mi_gdb_prompt$" { + pass "continue to do_special_tests" + } + timeout { + fail "continue to do_special_tests (timeout)" + } +} + +# Test: c_variable-7.10 +# Desc: create union u +mi_gdb_test "-var-create u * u" \ + "\\^done,name=\"u\",numchild=\"2\",type=\"union named_union\"" \ + "create local variable u" + +# Test: c_variable-7.11 +# Desc: value of u +mi_gdb_test "-var-evaluate-expression u" \ + "\\^done,value=\"\{\\.\\.\\.\}\"" \ + "eval variable u" + +# Test: c_variable-7.12 +# Desc: type of u +mi_gdb_test "-var-info-type u" \ + "\\^done,type=\"union named_union\"" \ + "info type variable u" + +# Test: c_variable-7.13 +# Desc: is u editable +mi_gdb_test "-var-show-attributes u" \ + "\\^done,attr=\"noneditable\"" \ + "is u editable" + +# Test: c_variable-7.14 +# Desc: number of children of u +mi_gdb_test "-var-info-num-children u" \ + "\\^done,numchild=\"2\"" \ + "get number of children of u" + +# Test: c_variable-7.15 +# Desc: children of u +mi_gdb_test "-var-list-children u" \ + "\\^done,numchild=\"2\",children=\\\[child=\{name=\"u.integer\",exp=\"integer\",numchild=\"0\",type=\"int\"\},child=\{name=\"u.char_ptr\",exp=\"char_ptr\",numchild=\"1\",type=\"char \\*\"\}\\\]" \ + "get children of u" + +# Test: c_variable-7.20 +# Desc: create anonu +mi_gdb_test "-var-create anonu * anonu" \ + "\\^done,name=\"anonu\",numchild=\"3\",type=\"union \{\\.\\.\\.\}\"" \ + "create local variable anonu" + +# Test: c_variable-7.21 +# Desc: value of anonu +mi_gdb_test "-var-evaluate-expression anonu" \ + "\\^done,value=\"\{\\.\\.\\.\}\"" \ + "eval variable anonu" + +# Test: c_variable-7.22 +# Desc: type of anonu +mi_gdb_test "-var-info-type anonu" \ + "\\^done,type=\"union \{\\.\\.\\.\}\"" \ + "info type variable anonu" + +# Test: c_variable-7.23 +# Desc: is anonu editable +mi_gdb_test "-var-show-attributes anonu" \ + "\\^done,attr=\"noneditable\"" \ + "is anonu editable" + +# Test: c_variable-7.24 +# Desc: number of children of anonu +mi_gdb_test "-var-info-num-children anonu" \ + "\\^done,numchild=\"3\"" \ + "get number of children of anonu" + +# Test: c_variable-7.25 +# Desc: children of anonu +mi_gdb_test "-var-list-children anonu" \ + "\\^done,numchild=\"3\",children=\\\[child=\{name=\"anonu.a\",exp=\"a\",numchild=\"0\",type=\"int\"\},child=\{name=\"anonu.b\",exp=\"b\",numchild=\"0\",type=\"char\"\},child=\{name=\"anonu.c\",exp=\"c\",numchild=\"0\",type=\"long int\"\}\\\]" \ + "get children of anonu" + +# Test: c_variable-7.30 +# Desc: create struct s +mi_gdb_test "-var-create s * s" \ + "\\^done,name=\"s\",numchild=\"6\",type=\"struct _simple_struct\"" \ + "create local variable s" + + +# Test: c_variable-7.31 +# Desc: value of s +mi_gdb_test "-var-evaluate-expression s" \ + "\\^done,value=\"\{\\.\\.\\.\}\"" \ + "eval variable s" + +# Test: c_variable-7.32 +# Desc: type of s +mi_gdb_test "-var-info-type s" \ + "\\^done,type=\"struct _simple_struct\"" \ + "info type variable s" + +# Test: c_variable-7.33 +# Desc: is s editable +mi_gdb_test "-var-show-attributes s" \ + "\\^done,attr=\"noneditable\"" \ + "is s editable" + +# Test: c_variable-7.34 +# Desc: number of children of s +mi_gdb_test "-var-info-num-children s" \ + "\\^done,numchild=\"6\"" \ + "get number of children of s" + +# Test: c_variable-7.35 +# Desc: children of s +mi_gdb_test "-var-list-children s" \ + "\\^done,numchild=\"6\",children=\\\[child=\{name=\"s.integer\",exp=\"integer\",numchild=\"0\",type=\"int\"\},child=\{name=\"s.unsigned_integer\",exp=\"unsigned_integer\",numchild=\"0\",type=\"unsigned int\"\},child=\{name=\"s.character\",exp=\"character\",numchild=\"0\",type=\"char\"\},child=\{name=\"s.signed_character\",exp=\"signed_character\",numchild=\"0\",type=\"signed char\"\},child=\{name=\"s.char_ptr\",exp=\"char_ptr\",numchild=\"1\",type=\"char \\*\"\},child=\{name=\"s.array_of_10\",exp=\"array_of_10\",numchild=\"10\",type=\"int \\\[10\\\]\"\}\\\]" \ + "get children of s" +#} {integer unsigned_integer character signed_character char_ptr array_of_10} + +# Test: c_variable-7.40 +# Desc: create anons +mi_gdb_test "-var-create anons * anons" \ + "\\^done,name=\"anons\",numchild=\"3\",type=\"struct \{\\.\\.\\.\}\"" \ + "create local variable anons" + +# Test: c_variable-7.41 +# Desc: value of anons +mi_gdb_test "-var-evaluate-expression anons" \ + "\\^done,value=\"\{\\.\\.\\.\}\"" \ + "eval variable anons" + +# Test: c_variable-7.42 +# Desc: type of anons +mi_gdb_test "-var-info-type anons" \ + "\\^done,type=\"struct \{\\.\\.\\.\}\"" \ + "info type variable anons" + +# Test: c_variable-7.43 +# Desc: is anons editable +mi_gdb_test "-var-show-attributes anons" \ + "\\^done,attr=\"noneditable\"" \ + "is anons editable" + +# Test: c_variable-7.44 +# Desc: number of children of anons +mi_gdb_test "-var-info-num-children anons" \ + "\\^done,numchild=\"3\"" \ + "get number of children of anons" + +# Test: c_variable-7.45 +# Desc: children of anons +mi_gdb_test "-var-list-children anons" \ + "\\^done,numchild=\"3\",children=\\\[child=\{name=\"anons.a\",exp=\"a\",numchild=\"0\",type=\"int\"\},child=\{name=\"anons.b\",exp=\"b\",numchild=\"0\",type=\"char\"\},child=\{name=\"anons.c\",exp=\"c\",numchild=\"0\",type=\"long int\"\}\\\]" \ + "get children of anons" + + +# Test: c_variable-7.50 +# Desc: create enum e +mi_gdb_test "-var-create e * e" \ + "\\^done,name=\"e\",numchild=\"0\",type=\"enum foo\"" \ + "create local variable e" + +setup_xfail "*-*-*" +# Test: c_variable-7.51 +# Desc: value of e +mi_gdb_test "-var-evaluate-expression e" \ + "\\^done,value=\"FIXME\"" \ + "eval variable e" +clear_xfail "*-*-*" + +# Test: c_variable-7.52 +# Desc: type of e +mi_gdb_test "-var-info-type e" \ + "\\^done,type=\"enum foo\"" \ + "info type variable e" + +# Test: c_variable-7.53 +# Desc: is e editable +mi_gdb_test "-var-show-attributes e" \ + "\\^done,attr=\"editable\"" \ + "is e editable" + +# Test: c_variable-7.54 +# Desc: number of children of e +mi_gdb_test "-var-info-num-children e" \ + "\\^done,numchild=\"0\"" \ + "get number of children of e" + +# Test: c_variable-7.55 +# Desc: children of e +mi_gdb_test "-var-list-children e" \ + "\\^done,numchild=\"0\"" \ + "get children of e" + +# Test: c_variable-7.60 +# Desc: create anone +mi_gdb_test "-var-create anone * anone" \ + "\\^done,name=\"anone\",numchild=\"0\",type=\"enum \{\\.\\.\\.\}\"" \ + "create local variable anone" + +setup_xfail "*-*-*" +# Test: c_variable-7.61 +# Desc: value of anone +mi_gdb_test "-var-evaluate-expression anone" \ + "\\^done,value=\"A\"" \ + "eval variable anone" +clear_xfail "*-*-*" + + +# Test: c_variable-7.70 +# Desc: create anone +mi_gdb_test "-var-create anone * anone" \ + "&\"Duplicate variable object name\\\\n\".*\\^error,msg=\"Duplicate variable object name\"" \ + "create duplicate local variable anone" + + +# Test: c_variable-7.72 +# Desc: type of anone +mi_gdb_test "-var-info-type anone" \ + "\\^done,type=\"enum \{\\.\\.\\.\}\"" \ + "info type variable anone" + + +# Test: c_variable-7.73 +# Desc: is anone editable +mi_gdb_test "-var-show-attributes anone" \ + "\\^done,attr=\"editable\"" \ + "is anone editable" + +# Test: c_variable-7.74 +# Desc: number of children of anone +mi_gdb_test "-var-info-num-children anone" \ + "\\^done,numchild=\"0\"" \ + "get number of children of anone" + +# Test: c_variable-7.75 +# Desc: children of anone +mi_gdb_test "-var-list-children anone" \ + "\\^done,numchild=\"0\"" \ + "get children of anone" + + +# Record fp + +send_gdb "p/x \$fp\n" +gdb_expect { + -re ".*($hex).*\\^done\r\n$mi_gdb_prompt$" { + pass "print FP register" + set fp $expect_out(1,string) + } +# -re ".*" { fail "print FP register"} + timeout { fail "print FP register (timeout)"} +} + +mi_gdb_test "200-break-insert incr_a" \ + "200\\^done,bkpt=\{number=\"3\",type=\"breakpoint\",disp=\"keep\",enabled=\"y\",addr=\"$hex\",func=\"incr_a\",file=\".*var-cmd.c\",line=\"85\",times=\"0\"\}" \ + "break-insert operation" +send_gdb "-exec-continue\n" +gdb_expect { + -re "\\^running\r\n${mi_gdb_prompt}\\*stopped,reason=\"breakpoint-hit\",bkptno=\"3\",thread-id=\"\[01\]\",frame=\{addr=\"$hex\",func=\"incr_a\",args=\\\[\{name=\"a\",value=\"2\.*\"\}\\\],file=\".*var-cmd.c\",line=\"85\"\}\r\n$mi_gdb_prompt$" { + pass "continue to incr_a" + } + -re "\\^running\r\n${mi_gdb_prompt}\\*stopped,reason=\"breakpoint-hit\",bkptno=\"3\",thread-id=\"\[01\]\",frame=\{addr=\"$hex\",func=\"incr_a\",args=\\\[\{name=\"a\",value=\"\.*\"\}\\\],file=\".*var-cmd.c\",line=\"8\[345\]\"\}\r\n$mi_gdb_prompt$" { + fail "continue to incr_a (compiler debug info incorrect)" + } + -re "\\^running\r\n${mi_gdb_prompt}.*\r\n$mi_gdb_prompt$" { + fail "continue to incr_a (unknown output)" + } + timeout { + fail "continue to incr_a (timeout)" + } +} + +# Test: c_variable-7.81 +# Desc: Create variables in different scopes +mi_gdb_test "-var-create a1 * a" \ + "\\^done,name=\"a1\",numchild=\"0\",type=\"char\"" \ + "create local variable a1" + +mi_gdb_test "-var-create a2 $fp a" \ + "\\^done,name=\"a2\",numchild=\"0\",type=\"int\"" \ + "create variable a2 in different scope" + +#gdbtk_test c_variable-7.81 {create variables in different scopes} { +# set a1 [gdb_variable create -expr a] +# set a2 [gdb_variable create -expr a -frame $fp] + +# set vals {} +# lappend vals [$a1 value] +# lappend vals [$a2 value] +# set vals +#} {2 1} + + +mi_gdb_exit +return 0 diff --git a/gdb/testsuite/gdb.mi/mi2-watch.exp b/gdb/testsuite/gdb.mi/mi2-watch.exp new file mode 100644 index 0000000..ba7df2b --- /dev/null +++ b/gdb/testsuite/gdb.mi/mi2-watch.exp @@ -0,0 +1,166 @@ +# Copyright 1999, 2000, 2002 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# Please email any bugs, comments, and/or additions to this file to: +# bug-gdb@prep.ai.mit.edu + +# +# Test essential Machine interface (MI) operations +# +# Verify that, using the MI, we can run a simple program and perform basic +# debugging activities like: insert breakpoints, run the program, +# step, next, continue until it ends and, last but not least, quit. +# +# The goal is not to test gdb functionality, which is done by other tests, +# but to verify the correct output response to MI operations. +# + +load_lib mi-support.exp +set MIFLAGS "-i=mi2" + +gdb_exit +if [mi_gdb_start] { + continue +} + +set testfile "basics" +set srcfile ${testfile}.c +set binfile ${objdir}/${subdir}/${testfile} +if { [gdb_compile "${srcdir}/${subdir}/${srcfile}" "${binfile}" executable {debug additional_flags=-DFAKEARGV}] != "" } { + gdb_suppress_entire_file "Testcase compile failed, so all tests in this file will automatically fail." +} + +mi_delete_breakpoints +mi_gdb_reinitialize_dir $srcdir/$subdir +mi_gdb_load ${binfile} + +proc test_watchpoint_creation_and_listing {} { + global mi_gdb_prompt + global srcfile + global hex + + # Insert a watchpoint and list + # Tests: + # -break-watch C + # -break-list + + mi_gdb_test "111-break-watch C" \ + "111\\^done,wpt=\{number=\"2\",exp=\"C\"\}" \ + "break-watch operation" + + mi_gdb_test "222-break-list" \ + "222\\\^done,BreakpointTable=\{nr_rows=\".\",nr_cols=\".\",hdr=\\\[\{width=\".*\",alignment=\".*\",col_name=\"number\",colhdr=\"Num\"\}.*colhdr=\"Type\".*colhdr=\"Disp\".*colhdr=\"Enb\".*colhdr=\"Address\".*colhdr=\"What\".*\\\],body=\\\[bkpt=\{number=\"1\",type=\"breakpoint\",disp=\"keep\",enabled=\"y\",addr=\"$hex\",func=\"callee4\",file=\".*basics.c\",line=\"8\",times=\"1\"\},bkpt=\{number=\"2\",type=\".*watchpoint\",disp=\"keep\",enabled=\"y\",addr=\"\",what=\"C\",times=\"0\"\}\\\]\}" \ + "list of watchpoints" + +} + +# UNUSED at the time +proc test_awatch_creation_and_listing {} { + global mi_gdb_prompt + global srcfile + global hex + + # Insert an access watchpoint and list it + # Tests: + # -break-watch -a A + # -break-list + + mi_gdb_test "333-break-watch -a A" \ + "333\\^done,bkpt=\{number=\"1\",addr=\"$hex\",file=\".*basics.c\",line=\"32\"\}" \ + "break-watch -a operation" + + mi_gdb_test "444-break-list" \ + "444\\^done,BreakpointTable=\{.*,hdr=\\\[.*\\\],body=\\\[bkpt=\{number=\"3\",type=\"watchpoint\",disp=\"del\",enabled=\"y\",addr=\"$hex\",func=\"main\",file=\".*basics.c\",line=\"32\",times=\"0\"\},.*\}\\\]\}" \ + "list of watchpoints awatch" + + mi_gdb_test "777-break-delete 3" \ + "777\\^done" \ + "delete access watchpoint" +} + +# UNUSED at the time +proc test_rwatch_creation_and_listing {} { + global mi_gdb_prompt + global srcfile + global hex + + # Insert a read watchpoint and list it. + # Tests: + # -break-insert -r B + # -break-list + + mi_gdb_test "200-break-watch -r C" \ + "200\\^done,bkpt=\{number=\"5\",type=\"breakpoint\",disp=\"keep\",enabled=\"y\",addr=\"$hex\",func=\"callee4\",file=\".*basics.c\",line=\"32\",times=\"0\"\}" \ + "break-insert -r operation" + + mi_gdb_test "300-break-list" \ + "300\\^done,BreakpointTable=\{.*,hdr=\\\[.*\\\],body=\\\[bkpt=\{number=\"5\",type=\"breakpoint\",disp=\"keep\",enabled=\"y\",addr=\"$hex\",func=\"main\",file=\".*basics.c\",line=\"32\",times=\"0\"\},.*\}\\\}\}" \ + "list of breakpoints" + + mi_gdb_test "177-break-delete 4" \ + "177\\^done" \ + "delete read watchpoint" +} + +proc test_watchpoint_triggering {} { + global mi_gdb_prompt + global hex + + # Continue execution until the watchpoint is reached, continue again, + # to see the watchpoint go out of scope. + # Does: + # -exec-continue (Here wp triggers) + # -exec-continue (Here wp goes out of scope) + + send_gdb "222-exec-continue\n" + gdb_expect { + -re "222\\^running\r\n$mi_gdb_prompt" { + gdb_expect { + -re "222\\*stopped,reason=\"watchpoint-trigger\",wpt=\{number=\"2\",exp=\"C\"\},value=\{old=\".*\",new=\"3\"\},thread-id=\"\[01\]\",frame=\{addr=\"$hex\",func=\"callee4\",args=\\\[\\\],file=\".*basics.c\",line=\"13\"\}\r\n$mi_gdb_prompt$" { + pass "watchpoint trigger" + } + -re ".*$mi_gdb_prompt$" {fail "watchpoint trigger (2)"} + timeout {fail "watchpoint trigger (timeout 2)"} + } + } + -re ".*$mi_gdb_prompt$" {fail "watchpoint trigger (1)"} + timeout {fail "watchpoint trigger (timeout 1)"} + } + + send_gdb "223-exec-continue\n" + gdb_expect { + -re "223\\^running\r\n$mi_gdb_prompt" { + gdb_expect { + -re "\[\r\n\]*223\\*stopped,reason=\"watchpoint-scope\",wpnum=\"2\",thread-id=\"\[01\]\",frame=\{addr=\"$hex\",func=\"callee3\",args=\\\[.*\\\],file=\".*basics.c\",line=\"18\"\}\r\n$mi_gdb_prompt$" { + pass "wp out of scope" + } + -re ".*$mi_gdb_prompt$" {fail "wp out of scope (2)"} + timeout {fail "wp out of scope (timeout 2)"} + } + } + -re ".*$mi_gdb_prompt$" {fail "wp out of scope (1)"} + timeout {fail "wp out of scope (timeout 1)"} + } +} + +mi_runto callee4 +test_watchpoint_creation_and_listing +#test_rwatch_creation_and_listing +#test_awatch_creation_and_listing +test_watchpoint_triggering + +mi_gdb_exit +return 0 diff --git a/gdb/testsuite/gdb.objc/Makefile.in b/gdb/testsuite/gdb.objc/Makefile.in new file mode 100644 index 0000000..381e48a --- /dev/null +++ b/gdb/testsuite/gdb.objc/Makefile.in @@ -0,0 +1,22 @@ +VPATH = @srcdir@ +srcdir = @srcdir@ + +EXECUTABLES = basicclass + +all: + @echo "Nothing to be done for all..." + +info: +install-info: +dvi: +install: +uninstall: force +installcheck: +check: + +clean mostlyclean: + -rm -f *~ *.o *.ci + -rm -f core ${EXECUTABLES} + +distclean maintainer-clean realclean: clean + -rm -f Makefile config.status config.log diff --git a/gdb/testsuite/gdb.objc/basicclass.exp b/gdb/testsuite/gdb.objc/basicclass.exp new file mode 100644 index 0000000..39cf296 --- /dev/null +++ b/gdb/testsuite/gdb.objc/basicclass.exp @@ -0,0 +1,199 @@ +# Copyright 2003 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# This file was written by Adam Fedor (fedor@gnu.org) + +if $tracelevel then { + strace $tracelevel +} + +set testfile "basicclass" +set srcfile ${testfile}.m +set binfile ${objdir}/${subdir}/${testfile} + +# +# Objective-C program compilation isn't standard. We need to figure out +# which libraries to link in. Most of the time it uses pthread +# +if {[gdb_compile_objc "${srcdir}/${subdir}/${srcfile}" "${binfile}" executable [list debug ]] != "" } { + return -1 +} + +# +# Deduce language of main() +# + +proc deduce_language_of_main {} { + global gdb_prompt + + # See what language gdb thinks main() is, prior to reading full symbols. + # I think this fails for COFF targets. + send_gdb "show language\n" + gdb_expect { + -re ".* source language is \"auto; currently objective-c\".*$gdb_prompt $" { + pass "deduced language is Objective-C, before full symbols" + } + -re ".*$gdb_prompt $" { + fail "source language not correct for Objective-C (psymtabs only)" + return + } + timeout { + fail "can't show language (timeout)" + return + } + } + + runto_main + + # See if our idea of the language has changed. + + send_gdb "show language\n" + gdb_expect { + -re ".* source language is \"auto; currently objective-c\".*$gdb_prompt $" { + pass "deduced language is Objective-C, after full symbols" + } + -re ".*$gdb_prompt $" { + fail "source language not correct for Objective-C (full symbols)" + return + } + timeout { + fail "can't show language (timeout)" + return + } + } +} + +proc do_objc_tests {} { + global prms_id + global bug_id + global subdir + global objdir + global srcdir + global binfile + global gdb_prompt + + set prms_id 0 + set bug_id 0 + + # Start with a fresh gdb. + + gdb_exit + gdb_start + gdb_reinitialize_dir $srcdir/$subdir + gdb_load $binfile + + deduce_language_of_main +} + +do_objc_tests + +# +# Breakpoint tests +# +gdb_test "break doIt" \ + "Breakpoint.*at.* file .*$srcfile, line.29.*" \ + "breakpoint method" + +gdb_test "break takeArg:" \ + "Breakpoint.*at.* file .*$srcfile, line.34.*" \ + "breakpoint method with colon" + +gdb_test "break newWithArg:" \ + "Breakpoint.*at.* file .*$srcfile, line.22.*" \ + "breakpoint class method with colon" + +# +# Continue until breakpoint (test re-setting breakpoint) +# +gdb_test continue \ + "Continuing\\..*Breakpoint \[0-9\]+, -.BasicClass takeArg:. \\(self=.*, _cmd=.*, arg=.*\\) at .*$srcfile:34.*" \ + "continue until method breakpoint" + +# +# Test resetting breakpoints when re-running program +# +send_gdb "run\n" +gdb_expect { + -re "The program .* has been started already.*y or n. $" { + send_gdb "y\n" + exp_continue + } + -re "Starting program.*Breakpoint \[0-9\]+,.*main .*argc.*argv.* at .*$srcfile:.*$gdb_prompt $"\ + { pass "resetting breakpoints when rerunning" } + -re ".*$gdb_prompt $" { fail "resetting breakpoints when rerunning" } + timeout { fail "resetting breakpoints when rerunning" } +} + +# +# Continue until breakpoint (test re-setting breakpoint) +# +gdb_test continue \ + "Continuing\\..*Breakpoint \[0-9\]+, -.BasicClass takeArg:. \\(self=.*, _cmd=.*, arg=.*\\) at .*$srcfile:34.*" \ + "continue until method breakpoint" + +# +# Test printing objects +# +gdb_test "print object" \ + "\\$\[0-9\] = .*0x0" \ + " print an ivar of self" + +gdb_test "print self" \ + "\\$\[0-9\] = \\(.*BasicClass \\*\\) 0x\[0-9a-f\]+" \ + " print self" + +gdb_test "print \*self" \ + "\\$\[0-9\] = \{isa = 0x\[0-9a-f\]+, object = 0x0\}" \ + " print contents of self" + +# +# Break in a category +# +gdb_test "break hiddenMethod" \ + "Breakpoint.*at.* file .*$srcfile, line.61." \ + "breakpoint in category method" + + +# +# Continue until breakpoint (test re-setting category breakpoint) +# +gdb_test continue \ + "Continuing\\..*Breakpoint \[0-9\]+, -.BasicClass\\(Private\\) hiddenMethod. \\(self=.*, _cmd=.*\\) at .*$srcfile:61.*" \ + "continue until category method" + +# +# Test calling Objective-C methods +# +gdb_test "print \[self printHi\]" \ + "Hi.*\\$\[0-9\] = -?\[0-9\]+" \ + "Call an Objective-C method with no arguments" + +gdb_test "print \[self printNumber: 42\]" \ + "42.*\\$\[0-9\] = 43" \ + "Call an Objective-C method with one argument" + +# +# Test printing the object description +# +gdb_test "print-object object" \ + "BasicClass gdb test object" \ + "Use of the print-object command" + +gdb_test "po self" \ + "BasicClass gdb test object" \ + "Use of the po (print-object) command" + + diff --git a/gdb/testsuite/gdb.objc/basicclass.m b/gdb/testsuite/gdb.objc/basicclass.m new file mode 100644 index 0000000..0de12db --- /dev/null +++ b/gdb/testsuite/gdb.objc/basicclass.m @@ -0,0 +1,81 @@ +#include + +@interface BasicClass: Object +{ + id object; +} ++ newWithArg: arg; +- doIt; +- takeArg: arg; +- printHi; +- (int) printNumber: (int)number; +- (const char *) myDescription; +@end + +@interface BasicClass (Private) +- hiddenMethod; +@end + +@implementation BasicClass ++ newWithArg: arg +{ + id obj = [self new]; + [obj takeArg: arg]; + return obj; +} + +- doIt +{ + return self; +} + +- takeArg: arg +{ + object = arg; + [self hiddenMethod]; + return self; +} + +- printHi +{ + printf("Hi\n"); + return self; +} + +- (int) printNumber: (int)number +{ + printf("%d\n", number); + return number+1; +} + +- (const char *) myDescription +{ + return "BasicClass gdb test object"; +} + +@end + +@implementation BasicClass (Private) +- hiddenMethod +{ + return self; +} +@end + +int main (int argc, const char *argv[]) +{ + id obj; + obj = [BasicClass new]; + [obj takeArg: obj]; + return 0; +} + +const char *_NSPrintForDebugger(id object) +{ + /* This is not really what _NSPrintForDebugger should do, but it + is a simple test if gdb can call this function */ + if (object && [object respondsTo: @selector(myDescription)]) + return [object myDescription]; + + return NULL; +} diff --git a/gdb/testsuite/gdb.objc/nondebug.exp b/gdb/testsuite/gdb.objc/nondebug.exp new file mode 100644 index 0000000..9c7a744 --- /dev/null +++ b/gdb/testsuite/gdb.objc/nondebug.exp @@ -0,0 +1,77 @@ +# Copyright 2003 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# This file tests decoding non-debuggable Objective-C symbols + +# This file was written by Adam Fedor (fedor@gnu.org) + +if $tracelevel then { + strace $tracelevel +} + +set testfile "nondebug" +set srcfile ${testfile}.m +set binfile ${objdir}/${subdir}/${testfile} + +# +# Objective-C program compilation isn't standard. We need to figure out +# which libraries to link in. Most of the time it uses pthread +# +if {[gdb_compile_objc "${srcdir}/${subdir}/${srcfile}" "${binfile}" executable [list ] ] != "" } { + return -1 +} + +proc do_objc_tests {} { + global prms_id + global bug_id + global subdir + global objdir + global srcdir + global binfile + global gdb_prompt + + set prms_id 0 + set bug_id 0 + + # Start with a fresh gdb. + + gdb_exit + gdb_start + gdb_reinitialize_dir $srcdir/$subdir + gdb_load $binfile + +} + +do_objc_tests + +# +# Break on multiply defined non-debuggable symbol (PR objc/1236) +# +set name "break on non-debuggable method" +gdb_test_multiple "break someMethod" $name \ +{ + -re "\\\[0\\\] cancel\r\n\\\[1\\\] all\r\n\\\[2\\\]\[ \]+-.NonDebug someMethod.*\\\[3\\\]\[ \]+-.NonDebug2 someMethod.*" { + send_gdb "2\n" + exp_continue + } + -re "\\\[0\\\] cancel\r\n\\\[1\\\] all\r\n> " { + gdb_test "0" "" "" + kfail "gdb/1236" $name + } + -re "Breakpoint \[0-9\]+ at 0x\[0-9a-f\]+.*$gdb_prompt $" { pass $name } + -re ".*$gdb_prompt $" { kfail "gdb/1236" $name } +} + diff --git a/gdb/testsuite/gdb.objc/nondebug.m b/gdb/testsuite/gdb.objc/nondebug.m new file mode 100644 index 0000000..dcbdde9 --- /dev/null +++ b/gdb/testsuite/gdb.objc/nondebug.m @@ -0,0 +1,38 @@ +#include + +@interface NonDebug: Object +{ +} +@end +@interface NonDebug2: Object +{ +} +@end + +@implementation NonDebug + +- someMethod +{ + printf("method someMethod\n"); + return self; +} + +@end +@implementation NonDebug2 + +- someMethod +{ + printf("method2 someMethod\n"); + return self; +} + +@end + + +int main (int argc, const char *argv[]) +{ + id obj; + obj = [NonDebug new]; + [obj someMethod]; + return 0; +} diff --git a/gdb/testsuite/gdb.objc/objcdecode.exp b/gdb/testsuite/gdb.objc/objcdecode.exp new file mode 100644 index 0000000..e00bffe --- /dev/null +++ b/gdb/testsuite/gdb.objc/objcdecode.exp @@ -0,0 +1,86 @@ +# Copyright 2003 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# This file tests decoding of Objective-C symbols + +# This file was written by Adam Fedor (fedor@gnu.org) + +if $tracelevel then { + strace $tracelevel +} + +set testfile "objcdecode" +set srcfile ${testfile}.m +set binfile ${objdir}/${subdir}/${testfile} + +# +# Objective-C program compilation isn't standard. We need to figure out +# which libraries to link in. Most of the time it uses pthread +# +if {[gdb_compile_objc "${srcdir}/${subdir}/${srcfile}" "${binfile}" executable [list debug ]] != "" } { + return -1 +} + +proc do_objc_tests {} { + global prms_id + global bug_id + global subdir + global objdir + global srcdir + global binfile + global gdb_prompt + + set prms_id 0 + set bug_id 0 + + # Start with a fresh gdb. + + gdb_exit + gdb_start + gdb_reinitialize_dir $srcdir/$subdir + gdb_load $binfile + +} + +do_objc_tests + +# +# Break on multiply defined method (PR objc/1236) +# +set name "break on multiply defined method" +gdb_test_multiple "break multipleDef" $name \ +{ + -re "\\\[0\\\] cancel\r\n\\\[1\\\] all\r\n\\\[2\\\] -.Decode multipleDef. at .*\r\n\\\[3\\\] multipleDef at .*\r\n> $" { + send_gdb "3\n" + exp_continue + } + -re "Breakpoint \[0-9\]+ at 0x\[0-9a-f\]+: file .*\r\n$gdb_prompt $" { pass $name } + -re ".*$gdb_prompt $" { kfail "gdb/1236" $name } +} + +set name "continue after break on multiply defined symbol" +gdb_test_multiple "run" $name \ +{ + -re "Starting program.*Breakpoint \[0-9\]+, multipleDef \\\(\\\) at .*\r\n$gdb_prompt $" { + pass $name + } + -re "Starting program.*\\\[0\\\] cancel\r\n\\\[1\\\] all\r\n\\\[2\\\] -.Decode multipleDef. at .*\r\n\\\[3\\\] multipleDef at .*\r\n> $" { + send_gdb "0\n" + kfail "gdb/1238" $name + # gdb is in a bad state here. + # It would be difficult to do any more tests after this. + } +} diff --git a/gdb/testsuite/gdb.objc/objcdecode.m b/gdb/testsuite/gdb.objc/objcdecode.m new file mode 100644 index 0000000..5e99618 --- /dev/null +++ b/gdb/testsuite/gdb.objc/objcdecode.m @@ -0,0 +1,49 @@ +#include + +@interface Decode: Object +{ +} +- multipleDef; +- (const char *) myDescription; +@end + +@implementation Decode + +- multipleDef +{ + printf("method multipleDef\n"); + return self; +} + +- (const char *) myDescription +{ + return "Decode gdb test object"; +} + +@end + +int +multipleDef() +{ + printf("function multipleDef\n"); + return 0; +} + +int main (int argc, const char *argv[]) +{ + id obj; + obj = [Decode new]; + multipleDef(); + [obj multipleDef]; + return 0; +} + +const char *_NSPrintForDebugger(id object) +{ + /* This is not really what _NSPrintForDebugger should do, but it + is a simple test if gdb can call this function */ + if (object && [object respondsTo: @selector(myDescription)]) + return [object myDescription]; + + return NULL; +} diff --git a/gdb/testsuite/gdb.threads/switch-threads.c b/gdb/testsuite/gdb.threads/switch-threads.c new file mode 100644 index 0000000..3e5a825 --- /dev/null +++ b/gdb/testsuite/gdb.threads/switch-threads.c @@ -0,0 +1,47 @@ +/* A minimal multi-threaded test case. + + Copyright 2003 + Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#include + +void foo (void) +{ +} + +void *thread_func (void *arg) +{ + int x; + for (x = 0; x < 10; x++) + foo (); + return 0; +} + +int main() +{ + pthread_t thr; + void *ret; + int x; + + pthread_create (&thr, NULL, thread_func, NULL); + pthread_join (thr, &ret); + for (x = 0; x < 10; x++) + foo (); +} diff --git a/gdb/testsuite/gdb.threads/switch-threads.exp b/gdb/testsuite/gdb.threads/switch-threads.exp new file mode 100644 index 0000000..d5608cf --- /dev/null +++ b/gdb/testsuite/gdb.threads/switch-threads.exp @@ -0,0 +1,52 @@ +# Copyright (C) 2003 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# Please email any bugs, comments, and/or additions to this file to: +# bug-gdb@prep.ai.mit.edu + +# This file was written by Daniel Jacobowitz . +# +# It tests that the correct thread is single-stepped. Prior to the +# introduction of vCont, we didn't pass enough information to remote +# multi-threaded stubs to reliably get this correct; gdbserver defaulted +# to the first thread. + +# TODO: we should also test explicitly changing threads with the "thread" +# command. + +if $tracelevel then { + strace $tracelevel +} + +set testfile "switch-threads" +set srcfile ${testfile}.c +set binfile ${objdir}/${subdir}/${testfile} + +if {[gdb_compile_pthreads "${srcdir}/${subdir}/${srcfile}" "${binfile}" executable [list debug "incdir=${objdir}"]] != "" } { + return -1 +} + +gdb_exit +gdb_start +gdb_reinitialize_dir $srcdir/$subdir +gdb_load ${binfile} + +runto_main + +gdb_breakpoint thread_func +gdb_continue_to_breakpoint "continue to thread_func" +gdb_test "next" ".*foo \\(\\);" + diff --git a/gdb/testsuite/gdb.threads/tls-main.c b/gdb/testsuite/gdb.threads/tls-main.c new file mode 100644 index 0000000..eec5d50 --- /dev/null +++ b/gdb/testsuite/gdb.threads/tls-main.c @@ -0,0 +1,9 @@ +__thread int i_tls = 2; +int main () +{ + int result; + result = foo (); /* Call to foo should return 2, not 1. */ + result ++; + return 0; /* break here to check result */ +} + diff --git a/gdb/testsuite/gdb.threads/tls-shared.c b/gdb/testsuite/gdb.threads/tls-shared.c new file mode 100644 index 0000000..d4f8e5c --- /dev/null +++ b/gdb/testsuite/gdb.threads/tls-shared.c @@ -0,0 +1,6 @@ +__thread int i_tls = 1; +int foo () +{ + return i_tls; +} + diff --git a/gdb/testsuite/gdb.threads/tls-shared.exp b/gdb/testsuite/gdb.threads/tls-shared.exp new file mode 100644 index 0000000..fc5c086 --- /dev/null +++ b/gdb/testsuite/gdb.threads/tls-shared.exp @@ -0,0 +1,115 @@ +# Copyright 2003 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +# Please email any bugs, comments, and/or additions to this file to: +# bug-gdb@prep.ai.mit.edu + +# tls-shared.exp -- Expect script to test thread local storage in gdb, with +# shared libraries. + +if $tracelevel then { + strace $tracelevel +} + +set testfile tls-main +set libfile tls-shared +set srcfile ${testfile}.c +set binfile ${objdir}/${subdir}/${testfile} + +remote_exec build "rm -f ${binfile}" + +# get the value of gcc_compiled +if [get_compiler_info ${binfile}] { + return -1 +} + +if { [gdb_compile_pthreads "${srcdir}/${subdir}/${srcfile}" "${binfile}.o" object {debug}] != "" } { + return -1 +} + +# Build the shared libraries this test case needs. +# + +if {$gcc_compiled == 0} { + if [istarget "hppa*-hp-hpux*"] then { + set additional_flags "additional_flags=+z" + } elseif { [istarget "mips-sgi-irix*"] } { + # Disable SGI compiler's implicit -Dsgi + set additional_flags "additional_flags=-Usgi" + } else { + # don't know what the compiler is... + set additional_flags "" + } +} else { + if { ([istarget "powerpc*-*-aix*"] + || [istarget "rs6000*-*-aix*"]) } { + set additional_flags "" + } else { + set additional_flags "additional_flags=-fpic" + } +} + +set additional_flags "$additional_flags -shared" +if {[gdb_compile_pthreads "${srcdir}/${subdir}/${libfile}.c" "${objdir}/${subdir}/${libfile}.so" executable [list debug $additional_flags "incdir=${objdir}"]] != ""} { + return -1 +} + +if { ($gcc_compiled +&& ([istarget "powerpc*-*-aix*"] +|| [istarget "rs6000*-*-aix*"] )) } { + set additional_flags "additional_flags=-L${objdir}/${subdir}" +} elseif { [istarget "mips-sgi-irix*"] } { + set additional_flags "additional_flags=-rpath ${objdir}/${subdir}" +} else { + set additional_flags "" +} + +if {[gdb_compile_pthreads "${objdir}/${subdir}/${testfile}.o ${objdir}/${subdir}/${libfile}.so" "${binfile}" executable [list debug $additional_flags]] != ""} { + return -1 +} + + +gdb_exit +gdb_start +gdb_reinitialize_dir $srcdir/$subdir +gdb_load ${binfile} + +if ![runto_main] then { + fail "Can't run to main" + return 0 +} + +gdb_test "print i_tls" "2" "print thread local storage variable" + +gdb_test "ptype i_tls" "int" "ptype of thread local storage variable" + +gdb_test "info address i_tls" \ + "Symbol \\\"i_tls\\\" is a thread-local variable at offset 0 in the thread-local storage for .*tls-main.." \ + "print storage info for thread local storage variable" + +set line_number [gdb_get_line_number "break here to check result"] + +gdb_test "break $line_number" \ + "Breakpoint.*at.*file.*tls-main.c.*line ${line_number}." \ + "break at and of main" +gdb_test "continue" \ + "main .* at .*:.*return 0.*break here to check result.*" \ + "continue to break" +# This is more of a gcc/glibc test, really. +# +gdb_test "print result" "3" "print result" + + diff --git a/gdb/testsuite/gdb.threads/tls.c b/gdb/testsuite/gdb.threads/tls.c new file mode 100644 index 0000000..9b2145e --- /dev/null +++ b/gdb/testsuite/gdb.threads/tls.c @@ -0,0 +1,221 @@ +/* BeginSourceFile tls.c + + This file creates and deletes threads. It uses thread local storage + variables too. */ + +#include +#include +#include +#include +#include +#include +#include + +#define N_THREADS 3 + +/* Uncomment to turn on debugging output */ +/*#define START_DEBUG*/ + +/* Thread-local storage. */ +__thread int a_thread_local; +__thread int another_thread_local; + +/* Global variable just for info addr in gdb. */ +int a_global; + +/* Print the results of thread-local storage. */ +int thread_local_val[ N_THREADS ]; +int another_thread_local_val[ N_THREADS ]; + +/* Semaphores to make sure the threads are alive when we print the TLS + variables from gdb. */ +sem_t tell_main, tell_thread; + + +void print_error () +{ + switch (errno) + { + case EAGAIN: + fprintf (stderr, "EAGAIN\n"); + break; + case EINTR: + fprintf (stderr, "EINTR\n"); + break; + case EINVAL: + fprintf (stderr, "EINVAL\n"); + break; + case ENOSYS: + fprintf (stderr, "ENOSYS\n"); + break; + case ENOENT: + fprintf (stderr, "ENOENT\n"); + break; + case EDEADLK: + fprintf (stderr, "EDEADLK\n"); + break; + default: + fprintf (stderr, "Unknown error\n"); + break; + } +} + +/* Routine for each thread to run, does nothing. */ +void *spin( vp ) + void * vp; +{ + int me = (long) vp; + int i; + + /* Use a_global. */ + a_global++; + + a_thread_local = 0; + another_thread_local = me; + for( i = 0; i <= me; i++ ) { + a_thread_local += i; + } + + another_thread_local_val[me] = another_thread_local; + thread_local_val[ me ] = a_thread_local; /* here we know tls value */ + + if (sem_post (&tell_main) == -1) + { + fprintf (stderr, "th %d post on sem tell_main failed\n", me); + print_error (); + return; + } +#ifdef START_DEBUG + fprintf (stderr, "th %d post on tell main\n", me); +#endif + + while (1) + { +#ifdef START_DEBUG + fprintf (stderr, "th %d start wait on tell_thread\n", me); +#endif + if (sem_wait (&tell_thread) == 0) + break; + + if (errno == EINTR) + { +#ifdef START_DEBUG + fprintf (stderr, "th %d wait tell_thread got EINTR, rewaiting\n", me); +#endif + continue; + } + else + { + fprintf (stderr, "th %d wait on sem tell_thread failed\n", me); + print_error (); + return; + } + } + +#ifdef START_DEBUG + fprintf (stderr, "th %d Wait on tell_thread\n", me); +#endif + +} + +void +do_pass() +{ + int i; + pthread_t t[ N_THREADS ]; + int err; + + for( i = 0; i < N_THREADS; i++) + { + thread_local_val[i] = 0; + another_thread_local_val[i] = 0; + } + + if (sem_init (&tell_main, 0, 0) == -1) + { + fprintf (stderr, "tell_main semaphore init failed\n"); + return; + } + + if (sem_init (&tell_thread, 0, 0) == -1) + { + fprintf (stderr, "tell_thread semaphore init failed\n"); + return; + } + + /* Start N_THREADS threads, then join them so that they are terminated. */ + for( i = 0; i < N_THREADS; i++ ) + { + err = pthread_create( &t[i], NULL, spin, (void *) (long) i ); + if( err != 0 ) { + fprintf(stderr, "Error in thread %d create\n", i ); + } + } + + for( i = 0; i < N_THREADS; i++ ) + { + while (1) + { +#ifdef START_DEBUG + fprintf (stderr, "main %d start wait on tell_main\n", i); +#endif + if (sem_wait (&tell_main) == 0) + break; + + if (errno == EINTR) + { +#ifdef START_DEBUG + fprintf (stderr, "main %d wait tell_main got EINTR, rewaiting\n", i); +#endif + continue; + } + else + { + fprintf (stderr, "main %d wait on sem tell_main failed\n", i); + print_error (); + return; + } + } + } + +#ifdef START_DEBUG + fprintf (stderr, "main done waiting on tell_main\n"); +#endif + + i = 10; /* Here all threads should be still alive. */ + + for( i = 0; i < N_THREADS; i++ ) + { + if (sem_post (&tell_thread) == -1) + { + fprintf (stderr, "main %d post on sem tell_thread failed\n", i); + print_error (); + return; + } +#ifdef START_DEBUG + fprintf (stderr, "main %d post on tell_thread\n", i); +#endif + } + + for( i = 0; i < N_THREADS; i++ ) + { + err = pthread_join(t[i], NULL ); + if( err != 0 ) + { + fprintf (stderr, "error in thread %d join\n", i ); + } + } + + i = 10; /* Null line for setting bpts on. */ + +} + +int +main() +{ + do_pass (); + + return 0; /* Set breakpoint here before exit. */ +} + +/* EndSourceFile */ diff --git a/gdb/testsuite/gdb.threads/tls.exp b/gdb/testsuite/gdb.threads/tls.exp new file mode 100644 index 0000000..3f74993 --- /dev/null +++ b/gdb/testsuite/gdb.threads/tls.exp @@ -0,0 +1,291 @@ +# tls.exp -- Expect script to test thread-local storage +# Copyright (C) 1992, 2003 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +# Please email any bugs, comments, and/or additions to this file to: +# bug-gdb@prep.ai.mit.edu + +set testfile tls +set srcfile ${testfile}.c +set binfile ${objdir}/${subdir}/${testfile} + +if [istarget "*-*-linux"] then { + set target_cflags "-D_MIT_POSIX_THREADS" +} else { + set target_cflags "" +} + +if {[gdb_compile_pthreads "${srcdir}/${subdir}/${srcfile}" "${binfile}" executable [list debug "incdir=${objdir}"]] != "" } { + return -1 +} + +### Compute the value of the a_thread_local variable. +proc compute_expected_value {value} { + set expected_value 0 + set i 0 + while { $i <= $value} { + incr expected_value $i + incr i + } + return $expected_value +} + +### Get the value of the variable 'me' for the current thread. +proc get_me_variable {tnum} { + global expect_out + global gdb_prompt + global decimal + + set value_of_me -1 + send_gdb "print me\n" + gdb_expect { + -re ".*= ($decimal).*\r\n$gdb_prompt $" { + set value_of_me $expect_out(1,string) + pass "$tnum thread print me" + } + -re "$gdb_prompt $" { + fail "$tnum thread print me" + } + timeout { + fail "$tnum thread print me (timeout)" + } + } + return ${value_of_me} +} + +### Check the values of the thread local variables in the thread. +### Also check that info address print the right things. +proc check_thread_local {number} { + set me_variable [get_me_variable $number] + set expected_value [compute_expected_value ${me_variable}] + + gdb_test "p a_thread_local" \ + "= $expected_value" \ + "${number} thread local storage" + + gdb_test "p another_thread_local" \ + "= $me_variable" \ + "${number} another thread local storage" + + gdb_test "info address a_thread_local" \ + ".*a_thread_local.*a thread-local variable at offset.*" \ + "${number} info address a_thread_local" + + gdb_test "info address another_thread_local" \ + ".*another_thread_local.*a thread-local variable at offset.*" \ + "${number} info address another_thread_local" +} + +### Select a particular thread. +proc select_thread {thread} { + global gdb_prompt + + send_gdb "thread $thread\n" + gdb_expect { + -re "\\\[Switching to thread .*\\\].*\r\n$gdb_prompt $" { + pass "selected thread: $thread" + } + -re "$gdb_prompt $" { + fail "selected thread: $thread" + } + timeout { + fail "selected thread: $thread (timeout)" + } + } +} + +### Do a backtrace for the current thread, and check that the 'spin' routine +### is in it. This means we have one of the threads we created, rather +### than the main thread. Record the thread in the spin_threads +### array. Also remember the level of the 'spin' routine in the backtrace, for +### later use. +proc check_thread_stack {number spin_threads spin_threads_level} { + global gdb_prompt + global expect_out + global decimal + global hex + upvar $spin_threads tarr + upvar $spin_threads_level tarrl + + select_thread $number + send_gdb "where\n" + gdb_expect { + -re ".*(\[0-9\]+)\[ \t\]+$hex in spin \\(vp=(0x\[0-9a-f\]+).*\r\n$gdb_prompt $" { + if {[info exists tarr($number)]} { + fail "backtrace of thread number $number in spin" + } else { + pass "backtrace of thread number $number in spin" + set level $expect_out(1,string) + set tarrl($number) $level + set tarr($number) 1 + } + } + -re ".*$gdb_prompt $" { + set tarr($number) 0 + set tarrl($number) 0 + pass "backtrace of thread number $number not relevant" + } + timeout { + fail "backtrace of thread number $number (timeout)" + } + } +} + +gdb_exit +gdb_start +gdb_reinitialize_dir $srcdir/$subdir + +gdb_load ${binfile} +if ![runto_main] then { + fail "Can't run to main" + return 0 +} + +# Set a breakpoint at the "spin" routine to +# test the thread local's value. +# +gdb_test "b [gdb_get_line_number "here we know tls value"]" \ + ".*Breakpoint 2.*tls.*" "set breakpoint at all threads" + +# Set a bp at a point where we know all threads are alive. +# +gdb_test "b [gdb_get_line_number "still alive"]" \ + ".*Breakpoint 3.*tls.*" "set breakpoint at synch point" + +# Set a bp at the end to see if all threads are finished. +# +gdb_test "b [gdb_get_line_number "before exit"]" \ + ".*Breakpoint 4.*tls.*" "set breakpoint at exit" + +send_gdb "continue\n" +gdb_expect { + -re ".*Program received signal SIGSEGV.*a_thread_local = 0;.*$gdb_prompt $" { + # This is the first symptom if the gcc and binutils versions + # in use support TLS, but the system glibc does not. + unsupported "continue to first thread: system does not support TLS" + return -1 + } + -re ".*Program exited normally.*$gdb_prompt $" { + fail "continue to first thread: program runaway" + } + -re ".*Pass 0 done.*Pass 1 done.*$gdb_prompt $" { + fail "continue to first thread: program runaway 2" + } + -re ".*Breakpoint 2.*tls value.*$gdb_prompt $" { + pass "continue to first thread: get to thread" + } + -re ".*$gdb_prompt $" { + fail "continue to first thread: no progress?" + } + timeout { fail "continue to first thread (timeout)" } +} + +gdb_test "info thread" ".*Thread.*spin.*" \ + "at least one th in spin while stopped at first th" + +check_thread_local "first" + +gdb_test "continue" ".*Breakpoint 2.*tls value.*" "continue to second thread" +gdb_test "info thread" "Thread.*spin.*" \ + "at least one th in spin while stopped at second th" + +check_thread_local "second" + +gdb_test "continue" ".*Breakpoint 2.*tls value.*" "continue to third thread" +gdb_test "info thread" ".*Thread.*spin.*" \ + "at least one th in spin while stopped at third th" + +check_thread_local "third" + +gdb_test "continue" ".*Breakpoint 3.*still alive.*" "continue to synch point" + +set no_of_threads 0 +send_gdb "info thread\n" +gdb_expect { + -re "^info thread\[ \t\r\n\]+(\[0-9\]+) Thread.*$gdb_prompt $" { + set no_of_threads $expect_out(1,string) + pass "get number of threads" + } + -re "$gdb_prompt $" { + fail "get number of threads" + } + timeout { + fail "get number of threads (timeout)" + } +} + +array set spin_threads {} +unset spin_threads +array set spin_threads_level {} +unset spin_threads_level + +# For each thread check its backtrace to see if it is stopped at the +# spin routine. +for {set i 1} {$i <= $no_of_threads} {incr i} { + check_thread_stack $i spin_threads spin_threads_level +} + +### Loop through the threads and check the values of the tls variables. +### keep track of how many threads we find in the spin routine. +set thrs_in_spin 0 +foreach i [array names spin_threads] { + if {$spin_threads($i) == 1} { + incr thrs_in_spin + select_thread $i + set level $spin_threads_level($i) + gdb_test "up $level" ".*spin.*sem_wait.*" "thread $i up" + check_thread_local $i + } +} + +if {$thrs_in_spin == 0} { + fail "No thread backtrace reported spin (vsyscall kernel problem?)" +} + +gdb_test "continue" ".*Breakpoint 4.*before exit.*" "threads exited" + +send_gdb "info thread\n" +gdb_expect { + -re ".* 1 Thread.*2 Thread.*$gdb_prompt $" { + fail "Too many threads left at end" + } + -re ".*\\\* 1 Thread.*main.*$gdb_prompt $" { + pass "Expect only base thread at end" + } + -re ".*No stack.*$gdb_prompt $" { + fail "runaway at end" + } + -re ".*$gdb_prompt $" { + fail "mess at end" + } + timeout { fail "at end (timeout)" } +} + +# Start over and do some "info address" stuff +# +runto spin + +gdb_test "info address a_global" \ + ".*a_global.*static storage at address.*" "info address a_global" + +setup_kfail "gdb/1294" "*-*-*" +gdb_test "info address me" ".*me.*is a variable at offset.*" "info address me" + +# Done! +# +gdb_exit + +return 0 diff --git a/gdb/trad-frame.c b/gdb/trad-frame.c new file mode 100644 index 0000000..f397f5d --- /dev/null +++ b/gdb/trad-frame.c @@ -0,0 +1,134 @@ +/* Traditional frame unwind support, for GDB the GNU Debugger. + + Copyright 2003 Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#include "defs.h" +#include "frame.h" +#include "trad-frame.h" +#include "regcache.h" + +/* A traditional frame is unwound by analysing the function prologue + and using the information gathered to track registers. For + non-optimized frames, the technique is reliable (just need to check + for all potential instruction sequences). */ + +struct trad_frame_saved_reg * +trad_frame_alloc_saved_regs (struct frame_info *next_frame) +{ + int regnum; + struct gdbarch *gdbarch = get_frame_arch (next_frame); + int numregs = NUM_REGS + NUM_PSEUDO_REGS; + struct trad_frame_saved_reg *this_saved_regs + = FRAME_OBSTACK_CALLOC (numregs, struct trad_frame_saved_reg); + for (regnum = 0; regnum < numregs; regnum++) + { + this_saved_regs[regnum].realreg = regnum; + this_saved_regs[regnum].addr = -1; + } + return this_saved_regs; +} + +enum { REG_VALUE = -1, REG_UNKNOWN = -2 }; + +int +trad_frame_value_p (struct trad_frame_saved_reg this_saved_regs[], int regnum) +{ + return (this_saved_regs[regnum].realreg == REG_VALUE); +} + +int +trad_frame_addr_p (struct trad_frame_saved_reg this_saved_regs[], int regnum) +{ + return (this_saved_regs[regnum].realreg >= 0 + && this_saved_regs[regnum].addr != -1); +} + +int +trad_frame_realreg_p (struct trad_frame_saved_reg this_saved_regs[], + int regnum) +{ + return (this_saved_regs[regnum].realreg >= 0 + && this_saved_regs[regnum].addr == -1); +} + +void +trad_frame_set_value (struct trad_frame_saved_reg this_saved_regs[], + int regnum, LONGEST val) +{ + /* Make the REALREG invalid, indicating that the ADDR contains the + register's value. */ + this_saved_regs[regnum].realreg = REG_VALUE; + this_saved_regs[regnum].addr = val; +} + +void +trad_frame_set_unknown (struct trad_frame_saved_reg this_saved_regs[], + int regnum) +{ + /* Make the REALREG invalid, indicating that the value is not known. */ + this_saved_regs[regnum].realreg = REG_UNKNOWN; + this_saved_regs[regnum].addr = -1; +} + +void +trad_frame_prev_register (struct frame_info *next_frame, + struct trad_frame_saved_reg this_saved_regs[], + int regnum, int *optimizedp, + enum lval_type *lvalp, CORE_ADDR *addrp, + int *realregp, void *bufferp) +{ + struct gdbarch *gdbarch = get_frame_arch (next_frame); + if (trad_frame_addr_p (this_saved_regs, regnum)) + { + /* The register was saved in memory. */ + *optimizedp = 0; + *lvalp = lval_memory; + *addrp = this_saved_regs[regnum].addr; + *realregp = -1; + if (bufferp != NULL) + { + /* Read the value in from memory. */ + get_frame_memory (next_frame, this_saved_regs[regnum].addr, bufferp, + register_size (gdbarch, regnum)); + } + } + else if (trad_frame_realreg_p (this_saved_regs, regnum)) + { + /* Ask the next frame to return the value of the register. */ + frame_register_unwind (next_frame, this_saved_regs[regnum].realreg, + optimizedp, lvalp, addrp, realregp, bufferp); + } + else if (trad_frame_value_p (this_saved_regs, regnum)) + { + /* The register's value is available. */ + *optimizedp = 0; + *lvalp = not_lval; + *addrp = 0; + *realregp = -1; + if (bufferp != NULL) + store_unsigned_integer (bufferp, register_size (gdbarch, regnum), + this_saved_regs[regnum].addr); + } + else + { + error ("Register %s not available", + gdbarch_register_name (gdbarch, regnum)); + } +} diff --git a/gdb/trad-frame.h b/gdb/trad-frame.h new file mode 100644 index 0000000..55720c7 --- /dev/null +++ b/gdb/trad-frame.h @@ -0,0 +1,88 @@ +/* Traditional frame unwind support, for GDB the GNU Debugger. + + Copyright 2003 Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#ifndef TRAD_FRAME_H +#define TRAD_FRAME_H + +struct frame_info; + +/* A traditional saved regs table, indexed by REGNUM, encoding where + the value of REGNUM for the previous frame can be found in this + frame. + + The table is initialized with an identity encoding (ADDR == -1, + REALREG == REGNUM) indicating that the value of REGNUM in the + previous frame can be found in register REGNUM (== REALREG) in this + frame. + + The initial encoding can then be changed: + + Modify ADDR (REALREG >= 0, ADDR != -1) to indicate that the value + of register REGNUM in the previous frame can be found in memory at + ADDR in this frame (addr_p, !realreg_p, !value_p). + + Modify REALREG (REALREG >= 0, ADDR == -1) to indicate that the + value of register REGNUM in the previous frame is found in register + REALREG in this frame (!addr_p, realreg_p, !value_p). + + Call trad_frame_set_value (REALREG == -1) to indicate that the + value of register REGNUM in the previous frame is found in ADDR + (!addr_p, !realreg_p, value_p). + + Call trad_frame_set_unknown (REALREG == -2) to indicate that the + register's value is not known. */ + +struct trad_frame_saved_reg +{ + LONGEST addr; /* A CORE_ADDR fits in a longest. */ + int realreg; +}; + +/* Encode REGNUM value in the trad-frame. */ +void trad_frame_set_value (struct trad_frame_saved_reg this_saved_regs[], + int regnum, LONGEST val); + +/* Mark REGNUM as unknown. */ +void trad_frame_set_unknown (struct trad_frame_saved_reg this_saved_regs[], + int regnum); + +/* Convenience functions, return non-zero if the register has been + encoded as specified. */ +int trad_frame_value_p (struct trad_frame_saved_reg this_saved_regs[], + int regnum); +int trad_frame_addr_p (struct trad_frame_saved_reg this_saved_regs[], + int regnum); +int trad_frame_realreg_p (struct trad_frame_saved_reg this_saved_regs[], + int regnum); + + +/* Return a freshly allocated (and initialized) trad_frame array. */ +struct trad_frame_saved_reg *trad_frame_alloc_saved_regs (struct frame_info *next_frame); + +/* Given the trad_frame info, return the location of the specified + register. */ +void trad_frame_prev_register (struct frame_info *next_frame, + struct trad_frame_saved_reg this_saved_regs[], + int regnum, int *optimizedp, + enum lval_type *lvalp, CORE_ADDR *addrp, + int *realregp, void *bufferp); + +#endif diff --git a/gdb/tui/tui-interp.c b/gdb/tui/tui-interp.c new file mode 100644 index 0000000..986ebb3 --- /dev/null +++ b/gdb/tui/tui-interp.c @@ -0,0 +1,210 @@ +/* TUI Interpreter definitions for GDB, the GNU debugger. + + Copyright 2003 Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#include "defs.h" +#include "interps.h" +#include "top.h" +#include "event-top.h" +#include "event-loop.h" +#include "ui-out.h" +#include "cli-out.h" +#include "tui/tuiData.h" +#include "readline/readline.h" +#include "tui/tuiWin.h" +#include "tui/tui.h" +#include "tui/tuiIO.h" + +/* Set to 1 when the TUI mode must be activated when we first start gdb. */ +static int tui_start_enabled = 0; + +/* Cleanup the tui before exiting. */ + +static void +tui_exit (void) +{ + /* Disable the tui. Curses mode is left leaving the screen + in a clean state (see endwin()). */ + tui_disable (); +} + +/* These implement the TUI interpreter. */ + +static void * +tui_init (void) +{ + /* Install exit handler to leave the screen in a good shape. */ + atexit (tui_exit); + + initializeStaticData (); + + tui_initialize_io (); + tui_initialize_readline (); + + return NULL; +} + +static int +tui_resume (void *data) +{ + struct ui_file *stream; + + /* gdb_setup_readline will change gdb_stdout. If the TUI was previously + writing to gdb_stdout, then set it to the new gdb_stdout afterwards. */ + + stream = cli_out_set_stream (tui_old_uiout, gdb_stdout); + if (stream != gdb_stdout) + { + cli_out_set_stream (tui_old_uiout, stream); + stream = NULL; + } + + gdb_setup_readline (); + + if (stream != NULL) + cli_out_set_stream (tui_old_uiout, gdb_stdout); + + if (tui_start_enabled) + tui_enable (); + return 1; +} + +static int +tui_suspend (void *data) +{ + tui_start_enabled = tui_active; + tui_disable (); + return 1; +} + +/* Display the prompt if we are silent. */ + +static int +tui_display_prompt_p (void *data) +{ + if (interp_quiet_p (NULL)) + return 0; + else + return 1; +} + +static int +tui_exec (void *data, const char *command_str) +{ + internal_error (__FILE__, __LINE__, "tui_exec called"); +} + + +/* Initialize all the necessary variables, start the event loop, + register readline, and stdin, start the loop. */ + +static void +tui_command_loop (void *data) +{ + int length; + char *a_prompt; + char *gdb_prompt = get_prompt (); + + /* If we are using readline, set things up and display the first + prompt, otherwise just print the prompt. */ + if (async_command_editing_p) + { + /* Tell readline what the prompt to display is and what function + it will need to call after a whole line is read. This also + displays the first prompt. */ + length = strlen (PREFIX (0)) + strlen (gdb_prompt) + strlen (SUFFIX (0)) + 1; + a_prompt = (char *) xmalloc (length); + strcpy (a_prompt, PREFIX (0)); + strcat (a_prompt, gdb_prompt); + strcat (a_prompt, SUFFIX (0)); + rl_callback_handler_install (a_prompt, input_handler); + } + else + display_gdb_prompt (0); + + /* Loop until there is nothing to do. This is the entry point to the + event loop engine. gdb_do_one_event, called via catch_errors() + will process one event for each invocation. It blocks waits for + an event and then processes it. >0 when an event is processed, 0 + when catch_errors() caught an error and <0 when there are no + longer any event sources registered. */ + while (1) + { + int result = catch_errors (gdb_do_one_event, 0, "", RETURN_MASK_ALL); + if (result < 0) + break; + + /* Update gdb output according to TUI mode. Since catch_errors + preserves the uiout from changing, this must be done at top + level of event loop. */ + if (tui_active) + uiout = tui_out; + else + uiout = tui_old_uiout; + + if (result == 0) + { + /* FIXME: this should really be a call to a hook that is + interface specific, because interfaces can display the + prompt in their own way. */ + display_gdb_prompt (0); + /* This call looks bizarre, but it is required. If the user + entered a command that caused an error, + after_char_processing_hook won't be called from + rl_callback_read_char_wrapper. Using a cleanup there + won't work, since we want this function to be called + after a new prompt is printed. */ + if (after_char_processing_hook) + (*after_char_processing_hook) (); + /* Maybe better to set a flag to be checked somewhere as to + whether display the prompt or not. */ + } + } + + /* We are done with the event loop. There are no more event sources + to listen to. So we exit GDB. */ + return; +} + +void +_initialize_tui_interp (void) +{ + static const struct interp_procs procs = { + tui_init, + tui_resume, + tui_suspend, + tui_exec, + tui_display_prompt_p, + tui_command_loop, + }; + struct interp *tui_interp; + + /* Create a default uiout builder for the TUI. */ + tui_out = tui_out_new (gdb_stdout); + interp_add (interp_new ("tui", NULL, tui_out, &procs)); + if (interpreter_p && strcmp (interpreter_p, "tui") == 0) + tui_start_enabled = 1; + + if (interpreter_p && strcmp (interpreter_p, INTERP_CONSOLE) == 0) + { + xfree (interpreter_p); + interpreter_p = xstrdup ("tui"); + } +} diff --git a/gdb/user-regs.c b/gdb/user-regs.c new file mode 100644 index 0000000..470a518 --- /dev/null +++ b/gdb/user-regs.c @@ -0,0 +1,205 @@ +/* User visible, per-frame registers, for GDB, the GNU debugger. + + Copyright 2002 Free Software Foundation, Inc. + + Contributed by Red Hat. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#include "defs.h" +#include "user-regs.h" +#include "gdbtypes.h" +#include "gdb_string.h" +#include "gdb_assert.h" +#include "frame.h" + +/* A table of user registers. + + User registers have regnum's that live above of the range [0 + .. NUM_REGS + NUM_PSEUDO_REGS) (which is controlled by the target). + The target should never see a user register's regnum value. + + Always append, never delete. By doing this, the relative regnum + (offset from NUM_REGS + NUM_PSEUDO_REGS) assigned to each user + register never changes. */ + +struct user_reg +{ + const char *name; + struct value *(*read) (struct frame_info * frame); + struct user_reg *next; +}; + +struct user_regs +{ + struct user_reg *first; + struct user_reg **last; +}; + +static void +append_user_reg (struct user_regs *regs, const char *name, + user_reg_read_ftype *read, struct user_reg *reg) +{ + /* The caller is responsible for allocating memory needed to store + the register. By doing this, the function can operate on a + register list stored in the common heap or a specific obstack. */ + gdb_assert (reg != NULL); + reg->name = name; + reg->read = read; + reg->next = NULL; + (*regs->last) = reg; + regs->last = &(*regs->last)->next; +} + +/* An array of the builtin user registers. */ + +static struct user_regs builtin_user_regs = { NULL, &builtin_user_regs.first }; + +void +user_reg_add_builtin (const char *name, user_reg_read_ftype *read) +{ + append_user_reg (&builtin_user_regs, name, read, + XMALLOC (struct user_reg)); +} + +/* Per-architecture user registers. Start with the builtin user + registers and then, again, append. */ + +static struct gdbarch_data *user_regs_data; + +static void * +user_regs_init (struct gdbarch *gdbarch) +{ + struct user_reg *reg; + struct user_regs *regs = GDBARCH_OBSTACK_ZALLOC (gdbarch, struct user_regs); + regs->last = ®s->first; + for (reg = builtin_user_regs.first; reg != NULL; reg = reg->next) + append_user_reg (regs, reg->name, reg->read, + GDBARCH_OBSTACK_ZALLOC (gdbarch, struct user_reg)); + return regs; +} + +void +user_reg_add (struct gdbarch *gdbarch, const char *name, + user_reg_read_ftype *read) +{ + struct user_regs *regs = gdbarch_data (gdbarch, user_regs_data); + if (regs == NULL) + { + /* ULGH, called during architecture initialization. Patch + things up. */ + regs = user_regs_init (gdbarch); + set_gdbarch_data (gdbarch, user_regs_data, regs); + } + append_user_reg (regs, name, read, + GDBARCH_OBSTACK_ZALLOC (gdbarch, struct user_reg)); +} + +int +user_reg_map_name_to_regnum (struct gdbarch *gdbarch, const char *name, + int len) +{ + /* Make life easy, set the len to something reasonable. */ + if (len < 0) + len = strlen (name); + + /* Search register name space first - always let an architecture + specific register override the user registers. */ + { + int i; + int maxregs = (gdbarch_num_regs (gdbarch) + + gdbarch_num_pseudo_regs (gdbarch)); + for (i = 0; i < maxregs; i++) + { + const char *regname = gdbarch_register_name (gdbarch, i); + if (regname != NULL && len == strlen (regname) + && strncmp (regname, name, len) == 0) + { + return i; + } + } + } + + /* Search the user name space. */ + { + struct user_regs *regs = gdbarch_data (gdbarch, user_regs_data); + struct user_reg *reg; + int nr; + for (nr = 0, reg = regs->first; reg != NULL; reg = reg->next, nr++) + { + if ((len < 0 && strcmp (reg->name, name)) + || (len == strlen (reg->name) + && strncmp (reg->name, name, len) == 0)) + return NUM_REGS + NUM_PSEUDO_REGS + nr; + } + } + + return -1; +} + +static struct user_reg * +usernum_to_user_reg (struct gdbarch *gdbarch, int usernum) +{ + struct user_regs *regs = gdbarch_data (gdbarch, user_regs_data); + struct user_reg *reg; + for (reg = regs->first; reg != NULL; reg = reg->next) + { + if (usernum == 0) + return reg; + usernum--; + } + return NULL; +} + +const char * +user_reg_map_regnum_to_name (struct gdbarch *gdbarch, int regnum) +{ + int maxregs = (gdbarch_num_regs (gdbarch) + + gdbarch_num_pseudo_regs (gdbarch)); + if (regnum < 0) + return NULL; + else if (regnum < maxregs) + return gdbarch_register_name (gdbarch, regnum); + else + { + struct user_reg *reg = usernum_to_user_reg (gdbarch, regnum - maxregs); + if (reg == NULL) + return NULL; + else + return reg->name; + } +} + +struct value * +value_of_user_reg (int regnum, struct frame_info *frame) +{ + struct gdbarch *gdbarch = get_frame_arch (frame); + int maxregs = (gdbarch_num_regs (gdbarch) + + gdbarch_num_pseudo_regs (gdbarch)); + struct user_reg *reg = usernum_to_user_reg (gdbarch, regnum - maxregs); + gdb_assert (reg != NULL); + return reg->read (frame); +} + +extern initialize_file_ftype _initialize_user_regs; /* -Wmissing-prototypes */ + +void +_initialize_user_regs (void) +{ + user_regs_data = register_gdbarch_data (user_regs_init); +} diff --git a/gdb/user-regs.h b/gdb/user-regs.h new file mode 100644 index 0000000..d845c8a --- /dev/null +++ b/gdb/user-regs.h @@ -0,0 +1,71 @@ +/* Per-frame user registers, for GDB, the GNU debugger. + + Copyright 2002, 2003 Free Software Foundation, Inc. + + Contributed by Red Hat. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#ifndef USER_REGS_H +#define USER_REGS_H + +/* Implement both builtin, and architecture specific, per-frame user + visible registers. + + Builtin registers apply to all architectures, where as architecture + specific registers are present when the architecture is selected. + + These registers are assigned register numbers outside the + architecture's register range [0 .. NUM_REGS + NUM_PSEUDO_REGS). + Their values should be constructed using per-frame information. */ + +/* TODO: cagney/2003-06-27: Need to think more about how these + registers are added, read, and modified. At present they are kind + of assumed to be read-only. Should it, for instance, return a + register descriptor that contains all the relvent access methods. */ + +struct frame_info; +struct gdbarch; + +/* Given an architecture, map a user visible register name onto its + index. */ + +extern int user_reg_map_name_to_regnum (struct gdbarch *gdbarch, + const char *str, int len); + +extern const char *user_reg_map_regnum_to_name (struct gdbarch *gdbarch, + int regnum); + +/* Return the value of the frame register in the specified frame. + + Note; These methods return a "struct value" instead of the raw + bytes as, at the time the register is being added, the type needed + to describe the register has not bee initialized. */ + +typedef struct value *(user_reg_read_ftype) (struct frame_info *frame); +extern struct value *value_of_user_reg (int regnum, struct frame_info *frame); + +/* Add a builtin register (present in all architectures). */ +extern void user_reg_add_builtin (const char *name, + user_reg_read_ftype *read); + +/* Add a per-architecture frame register. */ +extern void user_reg_add (struct gdbarch *gdbarch, const char *name, + user_reg_read_ftype *read); + +#endif diff --git a/gdb/x86-64-linux-tdep.h b/gdb/x86-64-linux-tdep.h new file mode 100644 index 0000000..a135cfa --- /dev/null +++ b/gdb/x86-64-linux-tdep.h @@ -0,0 +1,39 @@ +/* Target-dependent code for the x86-64. + + Copyright 2003 + Free Software Foundation, Inc. + + Contributed by Michal Ludvig, SuSE AG. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#ifndef X86_64_LINUX_TDEP_H +#define X86_64_LINUX_TDEP_H + +/* Fill GDB's register array with the general-purpose register values + in *GREGSETP. */ + +void x86_64_linux_supply_gregset (char *regp); + +/* Fill register REGNO (if it is a general-purpose register) in + *GREGSETPS with the value in GDB's register array. If REGNO is -1, + do this for all registers. */ + +void x86_64_linux_fill_gregset (char *regp, int regno); + +#endif /* x86-64-linux-tdep.h */ diff --git a/include/elf/iq2000.h b/include/elf/iq2000.h new file mode 100644 index 0000000..83c690c --- /dev/null +++ b/include/elf/iq2000.h @@ -0,0 +1,58 @@ +/* IQ2000 ELF support for BFD. + Copyright (C) 2002 Free Software Foundation, Inc. + +This file is part of BFD, the Binary File Descriptor library. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef _ELF_IQ2000_H +#define _ELF_IQ2000_H + +#include "elf/reloc-macros.h" + +/* Relocations. */ +START_RELOC_NUMBERS (elf_iq2000_reloc_type) + RELOC_NUMBER (R_IQ2000_NONE, 0) + RELOC_NUMBER (R_IQ2000_16, 1) + RELOC_NUMBER (R_IQ2000_32, 2) + RELOC_NUMBER (R_IQ2000_26, 3) + RELOC_NUMBER (R_IQ2000_PC16, 4) + RELOC_NUMBER (R_IQ2000_HI16, 5) + RELOC_NUMBER (R_IQ2000_LO16, 6) + RELOC_NUMBER (R_IQ2000_OFFSET_16, 7) + RELOC_NUMBER (R_IQ2000_OFFSET_21, 8) + RELOC_NUMBER (R_IQ2000_UHI16, 9) + RELOC_NUMBER (R_IQ2000_32_DEBUG, 10) + RELOC_NUMBER (R_IQ2000_GNU_VTINHERIT, 200) + RELOC_NUMBER (R_IQ2000_GNU_VTENTRY, 201) +END_RELOC_NUMBERS(R_IQ2000_max) + +#define EF_IQ2000_CPU_IQ2000 0x00000001 /* default */ +#define EF_IQ2000_CPU_IQ10 0x00000002 /* IQ10 */ +#define EF_IQ2000_CPU_MASK 0x00000003 /* specific cpu bits */ +#define EF_IQ2000_ALL_FLAGS (EF_IQ2000_CPU_MASK) + +/* Define the data & instruction memory discriminator. In a linked + executable, an symbol should be deemed to point to an instruction + if ((address & IQ2000_INSN_MASK) == IQ2000_INSN_VALUE), and similarly + for the data space. */ + +#define IQ2000_DATA_MASK 0x80000000 +#define IQ2000_DATA_VALUE 0x00000000 +#define IQ2000_INSN_MASK 0x80000000 +#define IQ2000_INSN_VALUE 0x80000000 + + +#endif /* _ELF_IQ2000_H */ diff --git a/include/elf/msp430.h b/include/elf/msp430.h new file mode 100644 index 0000000..912ded7 --- /dev/null +++ b/include/elf/msp430.h @@ -0,0 +1,56 @@ +/* MSP430 ELF support for BFD. + Copyright (C) 2002 Free Software Foundation, Inc. + Contributed by Dmitry Diky + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, Inc., + 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef _ELF_MSP430_H +#define _ELF_MSP430_H + +#include "elf/reloc-macros.h" + +/* Processor specific flags for the ELF header e_flags field. */ +#define EF_MSP430_MACH 0xff + +#define E_MSP430_MACH_MSP430x11 11 +#define E_MSP430_MACH_MSP430x11x1 110 +#define E_MSP430_MACH_MSP430x12 12 +#define E_MSP430_MACH_MSP430x13 13 +#define E_MSP430_MACH_MSP430x14 14 +#define E_MSP430_MACH_MSP430x15 15 +#define E_MSP430_MACH_MSP430x16 16 +#define E_MSP430_MACH_MSP430x31 31 +#define E_MSP430_MACH_MSP430x32 32 +#define E_MSP430_MACH_MSP430x33 33 +#define E_MSP430_MACH_MSP430x41 41 +#define E_MSP430_MACH_MSP430x42 42 +#define E_MSP430_MACH_MSP430x43 43 +#define E_MSP430_MACH_MSP430x44 44 + +/* Relocations. */ +START_RELOC_NUMBERS (elf_msp430_reloc_type) + RELOC_NUMBER (R_MSP430_NONE, 0) + RELOC_NUMBER (R_MSP430_32, 1) + RELOC_NUMBER (R_MSP430_10_PCREL, 2) + RELOC_NUMBER (R_MSP430_16, 3) + RELOC_NUMBER (R_MSP430_16_PCREL, 4) + RELOC_NUMBER (R_MSP430_16_BYTE, 5) + RELOC_NUMBER (R_MSP430_16_PCREL_BYTE, 6) + +END_RELOC_NUMBERS (R_MSP430_max) + +#endif /* _ELF_MSP430_H */ diff --git a/include/elf/ppc64.h b/include/elf/ppc64.h new file mode 100644 index 0000000..ee2b0ea --- /dev/null +++ b/include/elf/ppc64.h @@ -0,0 +1,156 @@ +/* PPC64 ELF support for BFD. + Copyright 2003 Free Software Foundation, Inc. + +This file is part of BFD, the Binary File Descriptor library. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef _ELF_PPC64_H +#define _ELF_PPC64_H + +#include "elf/reloc-macros.h" + +/* Relocations. */ +START_RELOC_NUMBERS (elf_ppc64_reloc_type) + RELOC_NUMBER (R_PPC64_NONE, 0) + RELOC_NUMBER (R_PPC64_ADDR32, 1) + RELOC_NUMBER (R_PPC64_ADDR24, 2) + RELOC_NUMBER (R_PPC64_ADDR16, 3) + RELOC_NUMBER (R_PPC64_ADDR16_LO, 4) + RELOC_NUMBER (R_PPC64_ADDR16_HI, 5) + RELOC_NUMBER (R_PPC64_ADDR16_HA, 6) + RELOC_NUMBER (R_PPC64_ADDR14, 7) + RELOC_NUMBER (R_PPC64_ADDR14_BRTAKEN, 8) + RELOC_NUMBER (R_PPC64_ADDR14_BRNTAKEN, 9) + RELOC_NUMBER (R_PPC64_REL24, 10) + RELOC_NUMBER (R_PPC64_REL14, 11) + RELOC_NUMBER (R_PPC64_REL14_BRTAKEN, 12) + RELOC_NUMBER (R_PPC64_REL14_BRNTAKEN, 13) + RELOC_NUMBER (R_PPC64_GOT16, 14) + RELOC_NUMBER (R_PPC64_GOT16_LO, 15) + RELOC_NUMBER (R_PPC64_GOT16_HI, 16) + RELOC_NUMBER (R_PPC64_GOT16_HA, 17) + /* 18 unused. 32-bit reloc is R_PPC_PLTREL24. */ + RELOC_NUMBER (R_PPC64_COPY, 19) + RELOC_NUMBER (R_PPC64_GLOB_DAT, 20) + RELOC_NUMBER (R_PPC64_JMP_SLOT, 21) + RELOC_NUMBER (R_PPC64_RELATIVE, 22) + /* 23 unused. 32-bit reloc is R_PPC_LOCAL24PC. */ + RELOC_NUMBER (R_PPC64_UADDR32, 24) + RELOC_NUMBER (R_PPC64_UADDR16, 25) + RELOC_NUMBER (R_PPC64_REL32, 26) + RELOC_NUMBER (R_PPC64_PLT32, 27) + RELOC_NUMBER (R_PPC64_PLTREL32, 28) + RELOC_NUMBER (R_PPC64_PLT16_LO, 29) + RELOC_NUMBER (R_PPC64_PLT16_HI, 30) + RELOC_NUMBER (R_PPC64_PLT16_HA, 31) + /* 32 unused. 32-bit reloc is R_PPC_SDAREL16. */ + RELOC_NUMBER (R_PPC64_SECTOFF, 33) + RELOC_NUMBER (R_PPC64_SECTOFF_LO, 34) + RELOC_NUMBER (R_PPC64_SECTOFF_HI, 35) + RELOC_NUMBER (R_PPC64_SECTOFF_HA, 36) + RELOC_NUMBER (R_PPC64_REL30, 37) + RELOC_NUMBER (R_PPC64_ADDR64, 38) + RELOC_NUMBER (R_PPC64_ADDR16_HIGHER, 39) + RELOC_NUMBER (R_PPC64_ADDR16_HIGHERA, 40) + RELOC_NUMBER (R_PPC64_ADDR16_HIGHEST, 41) + RELOC_NUMBER (R_PPC64_ADDR16_HIGHESTA, 42) + RELOC_NUMBER (R_PPC64_UADDR64, 43) + RELOC_NUMBER (R_PPC64_REL64, 44) + RELOC_NUMBER (R_PPC64_PLT64, 45) + RELOC_NUMBER (R_PPC64_PLTREL64, 46) + RELOC_NUMBER (R_PPC64_TOC16, 47) + RELOC_NUMBER (R_PPC64_TOC16_LO, 48) + RELOC_NUMBER (R_PPC64_TOC16_HI, 49) + RELOC_NUMBER (R_PPC64_TOC16_HA, 50) + RELOC_NUMBER (R_PPC64_TOC, 51) + RELOC_NUMBER (R_PPC64_PLTGOT16, 52) + RELOC_NUMBER (R_PPC64_PLTGOT16_LO, 53) + RELOC_NUMBER (R_PPC64_PLTGOT16_HI, 54) + RELOC_NUMBER (R_PPC64_PLTGOT16_HA, 55) + + /* The following relocs were added in the 64-bit PowerPC ELF ABI + revision 1.2. */ + RELOC_NUMBER (R_PPC64_ADDR16_DS, 56) + RELOC_NUMBER (R_PPC64_ADDR16_LO_DS, 57) + RELOC_NUMBER (R_PPC64_GOT16_DS, 58) + RELOC_NUMBER (R_PPC64_GOT16_LO_DS, 59) + RELOC_NUMBER (R_PPC64_PLT16_LO_DS, 60) + RELOC_NUMBER (R_PPC64_SECTOFF_DS, 61) + RELOC_NUMBER (R_PPC64_SECTOFF_LO_DS, 62) + RELOC_NUMBER (R_PPC64_TOC16_DS, 63) + RELOC_NUMBER (R_PPC64_TOC16_LO_DS, 64) + RELOC_NUMBER (R_PPC64_PLTGOT16_DS, 65) + RELOC_NUMBER (R_PPC64_PLTGOT16_LO_DS, 66) + + /* Relocs added to support TLS. PowerPC64 ELF ABI revision 1.5. */ + RELOC_NUMBER (R_PPC64_TLS, 67) + RELOC_NUMBER (R_PPC64_DTPMOD64, 68) + RELOC_NUMBER (R_PPC64_TPREL16, 69) + RELOC_NUMBER (R_PPC64_TPREL16_LO, 70) + RELOC_NUMBER (R_PPC64_TPREL16_HI, 71) + RELOC_NUMBER (R_PPC64_TPREL16_HA, 72) + RELOC_NUMBER (R_PPC64_TPREL64, 73) + RELOC_NUMBER (R_PPC64_DTPREL16, 74) + RELOC_NUMBER (R_PPC64_DTPREL16_LO, 75) + RELOC_NUMBER (R_PPC64_DTPREL16_HI, 76) + RELOC_NUMBER (R_PPC64_DTPREL16_HA, 77) + RELOC_NUMBER (R_PPC64_DTPREL64, 78) + RELOC_NUMBER (R_PPC64_GOT_TLSGD16, 79) + RELOC_NUMBER (R_PPC64_GOT_TLSGD16_LO, 80) + RELOC_NUMBER (R_PPC64_GOT_TLSGD16_HI, 81) + RELOC_NUMBER (R_PPC64_GOT_TLSGD16_HA, 82) + RELOC_NUMBER (R_PPC64_GOT_TLSLD16, 83) + RELOC_NUMBER (R_PPC64_GOT_TLSLD16_LO, 84) + RELOC_NUMBER (R_PPC64_GOT_TLSLD16_HI, 85) + RELOC_NUMBER (R_PPC64_GOT_TLSLD16_HA, 86) + RELOC_NUMBER (R_PPC64_GOT_TPREL16_DS, 87) + RELOC_NUMBER (R_PPC64_GOT_TPREL16_LO_DS, 88) + RELOC_NUMBER (R_PPC64_GOT_TPREL16_HI, 89) + RELOC_NUMBER (R_PPC64_GOT_TPREL16_HA, 90) + RELOC_NUMBER (R_PPC64_GOT_DTPREL16_DS, 91) + RELOC_NUMBER (R_PPC64_GOT_DTPREL16_LO_DS, 92) + RELOC_NUMBER (R_PPC64_GOT_DTPREL16_HI, 93) + RELOC_NUMBER (R_PPC64_GOT_DTPREL16_HA, 94) + RELOC_NUMBER (R_PPC64_TPREL16_DS, 95) + RELOC_NUMBER (R_PPC64_TPREL16_LO_DS, 96) + RELOC_NUMBER (R_PPC64_TPREL16_HIGHER, 97) + RELOC_NUMBER (R_PPC64_TPREL16_HIGHERA, 98) + RELOC_NUMBER (R_PPC64_TPREL16_HIGHEST, 99) + RELOC_NUMBER (R_PPC64_TPREL16_HIGHESTA, 100) + RELOC_NUMBER (R_PPC64_DTPREL16_DS, 101) + RELOC_NUMBER (R_PPC64_DTPREL16_LO_DS, 102) + RELOC_NUMBER (R_PPC64_DTPREL16_HIGHER, 103) + RELOC_NUMBER (R_PPC64_DTPREL16_HIGHERA, 104) + RELOC_NUMBER (R_PPC64_DTPREL16_HIGHEST, 105) + RELOC_NUMBER (R_PPC64_DTPREL16_HIGHESTA, 106) + + /* These are GNU extensions to enable C++ vtable garbage collection. */ + RELOC_NUMBER (R_PPC64_GNU_VTINHERIT, 253) + RELOC_NUMBER (R_PPC64_GNU_VTENTRY, 254) + +END_RELOC_NUMBERS (R_PPC64_max) + +#define IS_PPC64_TLS_RELOC(R) \ + ((R) >= R_PPC64_TLS && (R) <= R_PPC64_DTPREL16_HIGHESTA) + +/* Specify the start of the .glink section. */ +#define DT_PPC64_GLINK DT_LOPROC + +/* Specify the start and size of the .opd section. */ +#define DT_PPC64_OPD (DT_LOPROC + 1) +#define DT_PPC64_OPDSZ (DT_LOPROC + 2) + +#endif /* _ELF_PPC64_H */ diff --git a/include/elf/xtensa.h b/include/elf/xtensa.h new file mode 100644 index 0000000..6c584c7 --- /dev/null +++ b/include/elf/xtensa.h @@ -0,0 +1,88 @@ +/* Xtensa ELF support for BFD. + Copyright 2003 Free Software Foundation, Inc. + Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, + USA. */ + +/* This file holds definitions specific to the Xtensa ELF ABI. */ + +#ifndef _ELF_XTENSA_H +#define _ELF_XTENSA_H + +#include "elf/reloc-macros.h" + +/* Relocations. */ +START_RELOC_NUMBERS (elf_xtensa_reloc_type) + RELOC_NUMBER (R_XTENSA_NONE, 0) + RELOC_NUMBER (R_XTENSA_32, 1) + RELOC_NUMBER (R_XTENSA_RTLD, 2) + RELOC_NUMBER (R_XTENSA_GLOB_DAT, 3) + RELOC_NUMBER (R_XTENSA_JMP_SLOT, 4) + RELOC_NUMBER (R_XTENSA_RELATIVE, 5) + RELOC_NUMBER (R_XTENSA_PLT, 6) + RELOC_NUMBER (R_XTENSA_OP0, 8) + RELOC_NUMBER (R_XTENSA_OP1, 9) + RELOC_NUMBER (R_XTENSA_OP2, 10) + RELOC_NUMBER (R_XTENSA_ASM_EXPAND, 11) + RELOC_NUMBER (R_XTENSA_ASM_SIMPLIFY, 12) + RELOC_NUMBER (R_XTENSA_GNU_VTINHERIT, 15) + RELOC_NUMBER (R_XTENSA_GNU_VTENTRY, 16) +END_RELOC_NUMBERS (R_XTENSA_max) + +/* Processor-specific flags for the ELF header e_flags field. */ + +/* Four-bit Xtensa machine type field. */ +#define EF_XTENSA_MACH 0x0000000f + +/* Various CPU types. */ +#define E_XTENSA_MACH 0x00000000 + +/* Leave bits 0xf0 alone in case we ever have more than 16 cpu types. + Highly unlikely, but what the heck. */ + +#define EF_XTENSA_XT_INSN 0x00000100 +#define EF_XTENSA_XT_LIT 0x00000200 + + +/* Processor-specific dynamic array tags. */ + +/* Offset of the table that records the GOT location(s). */ +#define DT_XTENSA_GOT_LOC_OFF 0x70000000 + +/* Number of entries in the GOT location table. */ +#define DT_XTENSA_GOT_LOC_SZ 0x70000001 + + +/* Definitions for instruction and literal property tables. The + tables for ".gnu.linkonce.*" sections are placed in the following + sections: + + instruction tables: .gnu.linkonce.x.* + literal tables: .gnu.linkonce.p.* +*/ + +#define XTENSA_INSN_SEC_NAME ".xt.insn" +#define XTENSA_LIT_SEC_NAME ".xt.lit" + +typedef struct property_table_entry_t +{ + bfd_vma address; + bfd_vma size; +} property_table_entry; + +#endif /* _ELF_XTENSA_H */ diff --git a/include/gdb/fileio.h b/include/gdb/fileio.h new file mode 100644 index 0000000..d844781 --- /dev/null +++ b/include/gdb/fileio.h @@ -0,0 +1,146 @@ +/* Hosted File I/O interface definitions, for GDB, the GNU Debugger. + + Copyright 2003 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA + 02111-1307, USA. */ + +#ifndef GDB_FILEIO_H_ +#define GDB_FILEIO_H_ + +/* The following flags are defined to be independent of the host + as well as the target side implementation of these constants. + All constants are defined with a leading FILEIO_ in the name + to allow the usage of these constants together with the + corresponding implementation dependent constants in one module. */ + +/* open(2) flags */ +#define FILEIO_O_RDONLY 0x0 +#define FILEIO_O_WRONLY 0x1 +#define FILEIO_O_RDWR 0x2 +#define FILEIO_O_APPEND 0x8 +#define FILEIO_O_CREAT 0x200 +#define FILEIO_O_TRUNC 0x400 +#define FILEIO_O_EXCL 0x800 +#define FILEIO_O_SUPPORTED (FILEIO_O_RDONLY | FILEIO_O_WRONLY| \ + FILEIO_O_RDWR | FILEIO_O_APPEND| \ + FILEIO_O_CREAT | FILEIO_O_TRUNC| \ + FILEIO_O_EXCL) + +/* mode_t bits */ +#define FILEIO_S_IFREG 0100000 +#define FILEIO_S_IFDIR 040000 +#define FILEIO_S_IFCHR 020000 +#define FILEIO_S_IRUSR 0400 +#define FILEIO_S_IWUSR 0200 +#define FILEIO_S_IXUSR 0100 +#define FILEIO_S_IRWXU 0700 +#define FILEIO_S_IRGRP 040 +#define FILEIO_S_IWGRP 020 +#define FILEIO_S_IXGRP 010 +#define FILEIO_S_IRWXG 070 +#define FILEIO_S_IROTH 04 +#define FILEIO_S_IWOTH 02 +#define FILEIO_S_IXOTH 01 +#define FILEIO_S_IRWXO 07 +#define FILEIO_S_SUPPORTED (FILEIO_S_IFREG|FILEIO_S_IFDIR| \ + FILEIO_S_IRWXU|FILEIO_S_IRWXG| \ + FILEIO_S_IRWXO) + +/* lseek(2) flags */ +#define FILEIO_SEEK_SET 0 +#define FILEIO_SEEK_CUR 1 +#define FILEIO_SEEK_END 2 + +/* errno values */ +#define FILEIO_EPERM 1 +#define FILEIO_ENOENT 2 +#define FILEIO_EINTR 4 +#define FILEIO_EIO 5 +#define FILEIO_EBADF 9 +#define FILEIO_EACCES 13 +#define FILEIO_EFAULT 14 +#define FILEIO_EBUSY 16 +#define FILEIO_EEXIST 17 +#define FILEIO_ENODEV 19 +#define FILEIO_ENOTDIR 20 +#define FILEIO_EISDIR 21 +#define FILEIO_EINVAL 22 +#define FILEIO_ENFILE 23 +#define FILEIO_EMFILE 24 +#define FILEIO_EFBIG 27 +#define FILEIO_ENOSPC 28 +#define FILEIO_ESPIPE 29 +#define FILEIO_EROFS 30 +#define FILEIO_ENOSYS 88 +#define FILEIO_ENAMETOOLONG 91 +#define FILEIO_EUNKNOWN 9999 + +/* limits */ +#define FILEIO_INT_MIN -2147483648L +#define FILEIO_INT_MAX 2147483647L +#define FILEIO_UINT_MAX 4294967295UL +#define FILEIO_LONG_MIN -9223372036854775808LL +#define FILEIO_LONG_MAX 9223372036854775807LL +#define FILEIO_ULONG_MAX 18446744073709551615ULL + +/* Integral types as used in protocol. */ +#if 0 +typedef __int32_t fio_int_t; +typedef __uint32_t fio_uint_t, fio_mode_t, fio_time_t; +typedef __int64_t fio_long_t; +typedef __uint64_t fio_ulong_t; +#endif + +#define FIO_INT_LEN 4 +#define FIO_UINT_LEN 4 +#define FIO_MODE_LEN 4 +#define FIO_TIME_LEN 4 +#define FIO_LONG_LEN 8 +#define FIO_ULONG_LEN 8 + +typedef char fio_int_t[FIO_INT_LEN]; +typedef char fio_uint_t[FIO_UINT_LEN]; +typedef char fio_mode_t[FIO_MODE_LEN]; +typedef char fio_time_t[FIO_TIME_LEN]; +typedef char fio_long_t[FIO_LONG_LEN]; +typedef char fio_ulong_t[FIO_ULONG_LEN]; + +/* Struct stat as used in protocol. For complete independence + of host/target systems, it's defined as an array with offsets + to the members. */ + +struct fio_stat { + fio_uint_t fst_dev; + fio_uint_t fst_ino; + fio_mode_t fst_mode; + fio_uint_t fst_nlink; + fio_uint_t fst_uid; + fio_uint_t fst_gid; + fio_uint_t fst_rdev; + fio_ulong_t fst_size; + fio_ulong_t fst_blksize; + fio_ulong_t fst_blocks; + fio_time_t fst_atime; + fio_time_t fst_mtime; + fio_time_t fst_ctime; +}; + +struct fio_timeval { + fio_time_t ftv_sec; + fio_long_t ftv_usec; +}; + +#endif /* GDB_FILEIO_H_ */ diff --git a/include/gdb/sim-frv.h b/include/gdb/sim-frv.h new file mode 100644 index 0000000..0a1e021 --- /dev/null +++ b/include/gdb/sim-frv.h @@ -0,0 +1,53 @@ +/* This file defines the interface between the FR-V simulator and GDB. + + Copyright 2003 Free Software Foundation, Inc. + + Contributed by Red Hat. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA + 02111-1307, USA. */ + +#if !defined (SIM_FRV_H) +#define SIM_FRV_H + +#ifdef __cplusplus +extern "C" { // } +#endif + +enum sim_frv_regs +{ + SIM_FRV_GR0_REGNUM = 0, + SIM_FRV_GR63_REGNUM = 63, + SIM_FRV_FR0_REGNUM = 64, + SIM_FRV_FR63_REGNUM = 127, + SIM_FRV_PC_REGNUM = 128, + + /* An FR-V architecture may have up to 4096 special purpose registers + (SPRs). In order to determine a specific constant used to access + a particular SPR, one of the H_SPR_ prefixed offsets defined in + opcodes/frv-desc.h should be added to SIM_FRV_SPR0_REGNUM. So, + for example, the number that GDB uses to fetch the link register + from the simulator is (SIM_FRV_SPR0_REGNUM + H_SPR_LR). */ + SIM_FRV_SPR0_REGNUM = 129, + SIM_FRV_SPR4095_REGNUM = SIM_FRV_SPR0_REGNUM + 4095 +}; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/include/opcode/msp430.h b/include/opcode/msp430.h new file mode 100644 index 0000000..1970225 --- /dev/null +++ b/include/opcode/msp430.h @@ -0,0 +1,111 @@ +/* Opcode table for the TI MSP430 microcontrollers + + Copyright 2002 Free Software Foundation, Inc. + Contributed by Dmitry Diky + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef __MSP430_H_ +#define __MSP430_H_ + +struct msp430_operand_s +{ + int ol; /* Operand length words. */ + int am; /* Addr mode. */ + int reg; /* Register. */ + int mode; /* Pperand mode. */ +#define OP_REG 0 +#define OP_EXP 1 +#ifndef DASM_SECTION + expressionS exp; +#endif +}; + +#define BYTE_OPERATION (1 << 6) /* Byte operation flag for all instructions. */ + +struct msp430_opcode_s +{ + char *name; + int fmt; + int insn_opnumb; + int bin_opcode; + int bin_mask; +}; + +#define MSP_INSN(name, size, numb, bin, mask) { #name, size, numb, bin, mask } + +static struct msp430_opcode_s msp430_opcodes[] = +{ + MSP_INSN (and, 1, 2, 0xf000, 0xf000), + MSP_INSN (inv, 0, 1, 0xe330, 0xfff0), + MSP_INSN (xor, 1, 2, 0xe000, 0xf000), + MSP_INSN (setz, 0, 0, 0xd322, 0xffff), + MSP_INSN (setc, 0, 0, 0xd312, 0xffff), + MSP_INSN (eint, 0, 0, 0xd232, 0xffff), + MSP_INSN (setn, 0, 0, 0xd222, 0xffff), + MSP_INSN (bis, 1, 2, 0xd000, 0xf000), + MSP_INSN (clrz, 0, 0, 0xc322, 0xffff), + MSP_INSN (clrc, 0, 0, 0xc312, 0xffff), + MSP_INSN (dint, 0, 0, 0xc232, 0xffff), + MSP_INSN (clrn, 0, 0, 0xc222, 0xffff), + MSP_INSN (bic, 1, 2, 0xc000, 0xf000), + MSP_INSN (bit, 1, 2, 0xb000, 0xf000), + MSP_INSN (dadc, 0, 1, 0xa300, 0xff30), + MSP_INSN (dadd, 1, 2, 0xa000, 0xf000), + MSP_INSN (tst, 0, 1, 0x9300, 0xff30), + MSP_INSN (cmp, 1, 2, 0x9000, 0xf000), + MSP_INSN (decd, 0, 1, 0x8320, 0xff30), + MSP_INSN (dec, 0, 1, 0x8310, 0xff30), + MSP_INSN (sub, 1, 2, 0x8000, 0xf000), + MSP_INSN (sbc, 0, 1, 0x7300, 0xff30), + MSP_INSN (subc, 1, 2, 0x7000, 0xf000), + MSP_INSN (adc, 0, 1, 0x6300, 0xff30), + MSP_INSN (rlc, 0, 2, 0x6000, 0xf000), + MSP_INSN (addc, 1, 2, 0x6000, 0xf000), + MSP_INSN (incd, 0, 1, 0x5320, 0xff30), + MSP_INSN (inc, 0, 1, 0x5310, 0xff30), + MSP_INSN (rla, 0, 2, 0x5000, 0xf000), + MSP_INSN (add, 1, 2, 0x5000, 0xf000), + MSP_INSN (nop, 0, 0, 0x4303, 0xffff), + MSP_INSN (clr, 0, 1, 0x4300, 0xff30), + MSP_INSN (ret, 0, 0, 0x4130, 0xff30), + MSP_INSN (pop, 0, 1, 0x4130, 0xff30), + MSP_INSN (br, 0, 3, 0x4000, 0xf000), + MSP_INSN (mov, 1, 2, 0x4000, 0xf000), + MSP_INSN (jmp, 3, 1, 0x3c00, 0xfc00), + MSP_INSN (jl, 3, 1, 0x3800, 0xfc00), + MSP_INSN (jge, 3, 1, 0x3400, 0xfc00), + MSP_INSN (jn, 3, 1, 0x3000, 0xfc00), + MSP_INSN (jc, 3, 1, 0x2c00, 0xfc00), + MSP_INSN (jhs, 3, 1, 0x2c00, 0xfc00), + MSP_INSN (jnc, 3, 1, 0x2800, 0xfc00), + MSP_INSN (jlo, 3, 1, 0x2800, 0xfc00), + MSP_INSN (jz, 3, 1, 0x2400, 0xfc00), + MSP_INSN (jeq, 3, 1, 0x2400, 0xfc00), + MSP_INSN (jnz, 3, 1, 0x2000, 0xfc00), + MSP_INSN (jne, 3, 1, 0x2000, 0xfc00), + MSP_INSN (reti, 2, 0, 0x1300, 0xffc0), + MSP_INSN (call, 2, 1, 0x1280, 0xffc0), + MSP_INSN (push, 2, 1, 0x1200, 0xff80), + MSP_INSN (sxt, 2, 1, 0x1180, 0xffc0), + MSP_INSN (rra, 2, 1, 0x1100, 0xff80), + MSP_INSN (swpb, 2, 1, 0x1080, 0xffc0), + MSP_INSN (rrc, 2, 1, 0x1000, 0xff80), + + /* End of instruction set. */ + { NULL, 0, 0, 0, 0 } +}; + +#endif diff --git a/include/xtensa-config.h b/include/xtensa-config.h new file mode 100644 index 0000000..4191c36 --- /dev/null +++ b/include/xtensa-config.h @@ -0,0 +1,139 @@ +/* Xtensa configuration settings. + Copyright (C) 2001,2002,2003 Free Software Foundation, Inc. + Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef XTENSA_CONFIG_H +#define XTENSA_CONFIG_H + +/* The macros defined here match those with the same names in the Xtensa + compile-time HAL (Hardware Abstraction Layer). Please refer to the + Xtensa System Software Reference Manual for documentation of these + macros. */ + +#undef XCHAL_HAVE_BE +#define XCHAL_HAVE_BE 1 + +#undef XCHAL_HAVE_DENSITY +#define XCHAL_HAVE_DENSITY 1 + +#undef XCHAL_HAVE_CONST16 +#define XCHAL_HAVE_CONST16 0 + +#undef XCHAL_HAVE_ABS +#define XCHAL_HAVE_ABS 1 + +#undef XCHAL_HAVE_ADDX +#define XCHAL_HAVE_ADDX 1 + +#undef XCHAL_HAVE_L32R +#define XCHAL_HAVE_L32R 1 + +#undef XCHAL_HAVE_MAC16 +#define XCHAL_HAVE_MAC16 0 + +#undef XCHAL_HAVE_MUL16 +#define XCHAL_HAVE_MUL16 0 + +#undef XCHAL_HAVE_MUL32 +#define XCHAL_HAVE_MUL32 0 + +#undef XCHAL_HAVE_DIV32 +#define XCHAL_HAVE_DIV32 0 + +#undef XCHAL_HAVE_NSA +#define XCHAL_HAVE_NSA 1 + +#undef XCHAL_HAVE_MINMAX +#define XCHAL_HAVE_MINMAX 0 + +#undef XCHAL_HAVE_SEXT +#define XCHAL_HAVE_SEXT 0 + +#undef XCHAL_HAVE_LOOPS +#define XCHAL_HAVE_LOOPS 1 + +#undef XCHAL_HAVE_BOOLEANS +#define XCHAL_HAVE_BOOLEANS 0 + +#undef XCHAL_HAVE_FP +#define XCHAL_HAVE_FP 0 + +#undef XCHAL_HAVE_FP_DIV +#define XCHAL_HAVE_FP_DIV 0 + +#undef XCHAL_HAVE_FP_RECIP +#define XCHAL_HAVE_FP_RECIP 0 + +#undef XCHAL_HAVE_FP_SQRT +#define XCHAL_HAVE_FP_SQRT 0 + +#undef XCHAL_HAVE_FP_RSQRT +#define XCHAL_HAVE_FP_RSQRT 0 + +#undef XCHAL_HAVE_WINDOWED +#define XCHAL_HAVE_WINDOWED 1 + + +#undef XCHAL_ICACHE_SIZE +#define XCHAL_ICACHE_SIZE 8192 + +#undef XCHAL_DCACHE_SIZE +#define XCHAL_DCACHE_SIZE 8192 + +#undef XCHAL_ICACHE_LINESIZE +#define XCHAL_ICACHE_LINESIZE 16 + +#undef XCHAL_DCACHE_LINESIZE +#define XCHAL_DCACHE_LINESIZE 16 + +#undef XCHAL_ICACHE_LINEWIDTH +#define XCHAL_ICACHE_LINEWIDTH 4 + +#undef XCHAL_DCACHE_LINEWIDTH +#define XCHAL_DCACHE_LINEWIDTH 4 + +#undef XCHAL_DCACHE_IS_WRITEBACK +#define XCHAL_DCACHE_IS_WRITEBACK 0 + + +#undef XCHAL_HAVE_MMU +#define XCHAL_HAVE_MMU 1 + +#undef XCHAL_MMU_MIN_PTE_PAGE_SIZE +#define XCHAL_MMU_MIN_PTE_PAGE_SIZE 12 + + +#undef XCHAL_HAVE_DEBUG +#define XCHAL_HAVE_DEBUG 1 + +#undef XCHAL_NUM_IBREAK +#define XCHAL_NUM_IBREAK 2 + +#undef XCHAL_NUM_DBREAK +#define XCHAL_NUM_DBREAK 2 + +#undef XCHAL_DEBUGLEVEL +#define XCHAL_DEBUGLEVEL 4 + + +#undef XCHAL_EXTRA_SA_SIZE +#define XCHAL_EXTRA_SA_SIZE 0 + +#undef XCHAL_EXTRA_SA_ALIGN +#define XCHAL_EXTRA_SA_ALIGN 1 + +#endif /* !XTENSA_CONFIG_H */ diff --git a/include/xtensa-isa-internal.h b/include/xtensa-isa-internal.h new file mode 100644 index 0000000..7f221ea --- /dev/null +++ b/include/xtensa-isa-internal.h @@ -0,0 +1,114 @@ +/* Internal definitions for configurable Xtensa ISA support. + Copyright 2003 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* Use the statically-linked version for the GNU tools. */ +#define STATIC_LIBISA 1 + +#define ISA_INTERFACE_VERSION 3 + +struct config_struct +{ + char *param_name; + char *param_value; +}; + +/* Encode/decode function types for immediate operands. */ +typedef uint32 (*xtensa_immed_decode_fn) (uint32); +typedef xtensa_encode_result (*xtensa_immed_encode_fn) (uint32 *); + +/* Field accessor function types. */ +typedef uint32 (*xtensa_get_field_fn) (const xtensa_insnbuf); +typedef void (*xtensa_set_field_fn) (xtensa_insnbuf, uint32); + +/* PC-relative relocation function types. */ +typedef uint32 (*xtensa_do_reloc_fn) (uint32, uint32); +typedef uint32 (*xtensa_undo_reloc_fn) (uint32, uint32); + +/* Instruction decode function type. */ +typedef int (*xtensa_insn_decode_fn) (const xtensa_insnbuf); + +/* Instruction encoding template function type (each of these functions + returns a constant template; they exist only to make it easier for the + TIE compiler to generate endian-independent DLLs). */ +typedef xtensa_insnbuf (*xtensa_encoding_template_fn) (void); + + +typedef struct xtensa_operand_internal_struct +{ + char *operand_kind; /* e.g., "a", "f", "i", "l".... */ + char inout; /* '<', '>', or '='. */ + char isPCRelative; /* Is this a PC-relative offset? */ + xtensa_get_field_fn get_field; /* Get encoded value of the field. */ + xtensa_set_field_fn set_field; /* Set field with an encoded value. */ + xtensa_immed_encode_fn encode; /* Encode the operand value. */ + xtensa_immed_decode_fn decode; /* Decode the value from the field. */ + xtensa_do_reloc_fn do_reloc; /* Perform a PC-relative relocation. */ + xtensa_undo_reloc_fn undo_reloc; /* Undo a PC-relative relocation. */ +} xtensa_operand_internal; + + +typedef struct xtensa_iclass_internal_struct +{ + int num_operands; /* Size of "operands" array. */ + xtensa_operand_internal **operands; /* Array of operand structures. */ +} xtensa_iclass_internal; + + +typedef struct xtensa_opcode_internal_struct +{ + const char *name; /* Opcode mnemonic. */ + int length; /* Length in bytes of the insn. */ + xtensa_encoding_template_fn template; /* Fn returning encoding template. */ + xtensa_iclass_internal *iclass; /* Iclass for this opcode. */ +} xtensa_opcode_internal; + + +typedef struct opname_lookup_entry_struct +{ + const char *key; /* Opcode mnemonic. */ + xtensa_opcode opcode; /* Internal opcode number. */ +} opname_lookup_entry; + + +typedef struct xtensa_isa_internal_struct +{ + int is_big_endian; /* Endianness. */ + int insn_size; /* Maximum length in bytes. */ + int insnbuf_size; /* Number of insnbuf_words. */ + int num_opcodes; /* Total number for all modules. */ + xtensa_opcode_internal **opcode_table;/* Indexed by internal opcode #. */ + int num_modules; /* Number of modules (DLLs) loaded. */ + int *module_opcode_base; /* Starting opcode # for each module. */ + xtensa_insn_decode_fn *module_decode_fn; /* Decode fn for each module. */ + opname_lookup_entry *opname_lookup_table; /* Lookup table for each module. */ + struct config_struct *config; /* Table of configuration parameters. */ + int has_density; /* Is density option available? */ +} xtensa_isa_internal; + + +typedef struct xtensa_isa_module_struct +{ + int (*get_num_opcodes_fn) (void); + xtensa_opcode_internal **(*get_opcodes_fn) (void); + int (*decode_insn_fn) (const xtensa_insnbuf); + struct config_struct *(*get_config_table_fn) (void); +} xtensa_isa_module; + +extern xtensa_isa_module xtensa_isa_modules[]; + diff --git a/include/xtensa-isa.h b/include/xtensa-isa.h new file mode 100644 index 0000000..54f750c --- /dev/null +++ b/include/xtensa-isa.h @@ -0,0 +1,230 @@ +/* Interface definition for configurable Xtensa ISA support. + Copyright 2003 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef XTENSA_LIBISA_H +#define XTENSA_LIBISA_H + +/* Use the statically-linked version for the GNU tools. */ +#define STATIC_LIBISA 1 + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef uint32 +#define uint32 unsigned int +#endif + +/* This file defines the interface to the Xtensa ISA library. This library + contains most of the ISA-specific information for a particular Xtensa + processor. For example, the set of valid instructions, their opcode + encodings and operand fields are all included here. To support Xtensa's + configurability and user-defined instruction extensions (i.e., TIE), the + library is initialized by loading one or more dynamic libraries; only a + small set of interface code is present in the statically-linked portion + of the library. + + This interface basically defines four abstract data types. + + . an instruction buffer - for holding the raw instruction bits + . ISA info - information about the ISA as a whole + . opcode info - information about individual instructions + . operand info - information about specific instruction operands + + It would be nice to implement these as classes in C++, but the library is + implemented in C to match the expectations of the GNU tools. + Instead, the interface defines a set of functions to access each data + type. With the exception of the instruction buffer, the internal + representations of the data structures are hidden. All accesses must be + made through the functions defined here. */ + +typedef void* xtensa_isa; +typedef void* xtensa_operand; + + +/* Opcodes are represented here using sequential integers beginning with 0. + The specific value used for a particular opcode is only fixed for a + particular instantiation of an xtensa_isa structure, so these values + should only be used internally. */ +typedef int xtensa_opcode; + +/* Define a unique value for undefined opcodes ("static const int" doesn't + seem to work for this because EGCS 1.0.3 on i686-Linux without -O won't + allow it to be used as an initializer). */ +#define XTENSA_UNDEFINED -1 + + +typedef int libisa_module_specifier; + +extern xtensa_isa xtensa_isa_init (void); + + +/* Instruction buffers. */ + +typedef uint32 xtensa_insnbuf_word; +typedef xtensa_insnbuf_word *xtensa_insnbuf; + +/* Get the size in words of the xtensa_insnbuf array. */ +extern int xtensa_insnbuf_size (xtensa_isa); + +/* Allocate (with malloc) an xtensa_insnbuf of the right size. */ +extern xtensa_insnbuf xtensa_insnbuf_alloc (xtensa_isa); + +/* Release (with free) an xtensa_insnbuf of the right size. */ +extern void xtensa_insnbuf_free (xtensa_insnbuf); + +/* Inward and outward conversion from memory images (byte streams) to our + internal instruction representation. */ +extern void xtensa_insnbuf_to_chars (xtensa_isa, const xtensa_insnbuf, + char *); + +extern void xtensa_insnbuf_from_chars (xtensa_isa, xtensa_insnbuf, + const char *); + + +/* ISA information. */ + +/* Load the ISA information from a shared library. If successful, this returns + a value which identifies the ISA for use in subsequent calls to the ISA + library; otherwise, it returns NULL. Multiple ISAs can be loaded to support + heterogeneous multiprocessor systems. */ +extern xtensa_isa xtensa_load_isa (libisa_module_specifier); + +/* Extend an existing set of ISA information by loading an additional shared + library of ISA information. This is primarily intended for loading TIE + extensions. If successful, the return value is non-zero. */ +extern int xtensa_extend_isa (xtensa_isa, libisa_module_specifier); + +/* The default ISA. This variable is set automatically to the ISA most + recently loaded and is provided as a convenience. An exception is the GNU + opcodes library, where there is a fixed interface that does not allow + passing the ISA as a parameter and the ISA must be taken from this global + variable. (Note: Since this variable is just a convenience, it is not + exported when libisa is built as a DLL, due to the hassle of dealing with + declspecs.) */ +extern xtensa_isa xtensa_default_isa; + + +/* Deallocate an xtensa_isa structure. */ +extern void xtensa_isa_free (xtensa_isa); + +/* Get the maximum instruction size in bytes. */ +extern int xtensa_insn_maxlength (xtensa_isa); + +/* Get the total number of opcodes for this processor. */ +extern int xtensa_num_opcodes (xtensa_isa); + +/* Translate a mnemonic name to an opcode. Returns XTENSA_UNDEFINED if + the name is not a valid opcode mnemonic. */ +extern xtensa_opcode xtensa_opcode_lookup (xtensa_isa, const char *); + +/* Decode a binary instruction buffer. Returns the opcode or + XTENSA_UNDEFINED if the instruction is illegal. */ +extern xtensa_opcode xtensa_decode_insn (xtensa_isa, const xtensa_insnbuf); + + +/* Opcode information. */ + +/* Set the opcode field(s) in a binary instruction buffer. The operand + fields are set to zero. */ +extern void xtensa_encode_insn (xtensa_isa, xtensa_opcode, xtensa_insnbuf); + +/* Get the mnemonic name for an opcode. */ +extern const char * xtensa_opcode_name (xtensa_isa, xtensa_opcode); + +/* Find the length (in bytes) of an instruction. */ +extern int xtensa_insn_length (xtensa_isa, xtensa_opcode); + +/* Find the length of an instruction by looking only at the first byte. */ +extern int xtensa_insn_length_from_first_byte (xtensa_isa, char); + +/* Find the number of operands for an instruction. */ +extern int xtensa_num_operands (xtensa_isa, xtensa_opcode); + +/* Get the information about operand number "opnd" of a particular opcode. */ +extern xtensa_operand xtensa_get_operand (xtensa_isa, xtensa_opcode, int); + +/* Operand information. */ + +/* Find the kind of operand. There are three possibilities: + 1) PC-relative immediates (e.g., "l", "L"). These can be identified with + the xtensa_operand_isPCRelative function. + 2) non-PC-relative immediates ("i"). + 3) register-file short names (e.g., "a", "b", "m" and others defined + via TIE). */ +extern char * xtensa_operand_kind (xtensa_operand); + +/* Check if an operand is an input ('<'), output ('>'), or inout ('=') + operand. Note: The output operand of a conditional assignment + (e.g., movnez) appears here as an inout ('=') even if it is declared + in the TIE code as an output ('>'); this allows the compiler to + properly handle register allocation for conditional assignments. */ +extern char xtensa_operand_inout (xtensa_operand); + +/* Get and set the raw (encoded) value of the field for the specified + operand. The "set" function does not check if the value fits in the + field; that is done by the "encode" function below. */ +extern uint32 xtensa_operand_get_field (xtensa_operand, const xtensa_insnbuf); + +extern void xtensa_operand_set_field (xtensa_operand, xtensa_insnbuf, uint32); + + +/* Encode and decode operands. The raw bits in the operand field + may be encoded in a variety of different ways. These functions hide the + details of that encoding. The encode function has a special return type + (xtensa_encode_result) to indicate success or the reason for failure; the + encoded value is returned through the argument pointer. The decode function + has no possibility of failure and returns the decoded value. */ + +typedef enum +{ + xtensa_encode_result_ok, + xtensa_encode_result_align, + xtensa_encode_result_not_in_table, + xtensa_encode_result_too_low, + xtensa_encode_result_too_high, + xtensa_encode_result_not_ok, + xtensa_encode_result_max = xtensa_encode_result_not_ok +} xtensa_encode_result; + +extern xtensa_encode_result xtensa_operand_encode (xtensa_operand, uint32 *); + +extern uint32 xtensa_operand_decode (xtensa_operand, uint32); + + +/* For PC-relative offset operands, the interpretation of the offset may vary + between opcodes, e.g., is it relative to the current PC or that of the next + instruction? The following functions are defined to perform PC-relative + relocations and to undo them (as in the disassembler). The first function + takes the desired address and the PC of the current instruction and returns + the unencoded value to be stored in the offset field. The second function + takes the unencoded offset value and the current PC and returns the address. + Note that these functions do not replace the encode/decode functions; the + operands must be encoded/decoded separately. */ + +extern int xtensa_operand_isPCRelative (xtensa_operand); + +extern uint32 xtensa_operand_do_reloc (xtensa_operand, uint32, uint32); + +extern uint32 xtensa_operand_undo_reloc (xtensa_operand, uint32, uint32); + +#ifdef __cplusplus +} +#endif +#endif /* XTENSA_LIBISA_H */ diff --git a/libiberty/acconfig.h b/libiberty/acconfig.h new file mode 100644 index 0000000..364cb41 --- /dev/null +++ b/libiberty/acconfig.h @@ -0,0 +1,3 @@ +/* Define to `unsigned long' if doesn't define. */ +#undef uintptr_t + diff --git a/libiberty/lrealpath.c b/libiberty/lrealpath.c new file mode 100644 index 0000000..b001b38 --- /dev/null +++ b/libiberty/lrealpath.c @@ -0,0 +1,128 @@ +/* Libiberty realpath. Like realpath, but more consistent behavior. + Based on gdb_realpath from GDB. + + Copyright 2003 Free Software Foundation, Inc. + + This file is part of the libiberty library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +/* + +@deftypefn Replacement {const char*} lrealpath (const char *@var{name}) + +Given a pointer to a string containing a pathname, returns a canonical +version of the filename. Symlinks will be resolved, and ``.'' and ``..'' +components will be simplified. The returned value will be allocated using +@code{malloc}, or @code{NULL} will be returned on a memory allocation error. + +@end deftypefn + +*/ + +#include "config.h" +#include "ansidecl.h" +#include "libiberty.h" + +#ifdef HAVE_LIMITS_H +#include +#endif +#ifdef HAVE_STDLIB_H +#include +#endif +#ifdef HAVE_UNISTD_H +#include +#endif +#ifdef HAVE_STRING_H +#include +#endif + +/* On GNU libc systems the declaration is only visible with _GNU_SOURCE. */ +#if defined(HAVE_CANONICALIZE_FILE_NAME) \ + && defined(NEED_DECLARATION_CANONICALIZE_FILE_NAME) +extern char *canonicalize_file_name (const char *); +#endif + +#if defined(HAVE_REALPATH) +# if defined (PATH_MAX) +# define REALPATH_LIMIT PATH_MAX +# else +# if defined (MAXPATHLEN) +# define REALPATH_LIMIT MAXPATHLEN +# endif +# endif +#endif + +char * +lrealpath (filename) + const char *filename; +{ + /* Method 1: The system has a compile time upper bound on a filename + path. Use that and realpath() to canonicalize the name. This is + the most common case. Note that, if there isn't a compile time + upper bound, you want to avoid realpath() at all costs. */ +#if defined(REALPATH_LIMIT) + { + char buf[REALPATH_LIMIT]; + const char *rp = realpath (filename, buf); + if (rp == NULL) + rp = filename; + return strdup (rp); + } +#endif /* REALPATH_LIMIT */ + + /* Method 2: The host system (i.e., GNU) has the function + canonicalize_file_name() which malloc's a chunk of memory and + returns that, use that. */ +#if defined(HAVE_CANONICALIZE_FILE_NAME) + { + char *rp = canonicalize_file_name (filename); + if (rp == NULL) + return strdup (filename); + else + return rp; + } +#endif + + /* Method 3: Now we're getting desperate! The system doesn't have a + compile time buffer size and no alternative function. Query the + OS, using pathconf(), for the buffer limit. Care is needed + though, some systems do not limit PATH_MAX (return -1 for + pathconf()) making it impossible to pass a correctly sized buffer + to realpath() (it could always overflow). On those systems, we + skip this. */ +#if defined (HAVE_REALPATH) && defined (HAVE_UNISTD_H) + { + /* Find out the max path size. */ + long path_max = pathconf ("/", _PC_PATH_MAX); + if (path_max > 0) + { + /* PATH_MAX is bounded. */ + char *buf, *rp, *ret; + buf = malloc (path_max); + if (buf == NULL) + return NULL; + rp = realpath (filename, buf); + ret = strdup (rp ? rp : filename); + free (buf); + return ret; + } + } +#endif + + /* This system is a lost cause, just duplicate the filename. */ + return strdup (filename); +} diff --git a/libiberty/make-relative-prefix.c b/libiberty/make-relative-prefix.c new file mode 100644 index 0000000..dc4f8d5 --- /dev/null +++ b/libiberty/make-relative-prefix.c @@ -0,0 +1,396 @@ +/* Relative (relocatable) prefix support. + Copyright (C) 1987, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998, + 1999, 2000, 2001, 2002 Free Software Foundation, Inc. + +This file is part of libiberty. + +GCC is free software; you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free +Software Foundation; either version 2, or (at your option) any later +version. + +GCC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +You should have received a copy of the GNU General Public License +along with GCC; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ + +/* + +@deftypefn Extension {const char*} make_relative_prefix (const char *@var{progname}, const char *@var{bin_prefix}, const char *@var{prefix}) + +Given three paths @var{progname}, @var{bin_prefix}, @var{prefix}, +return the path that is in the same position relative to +@var{progname}'s directory as @var{prefix} is relative to +@var{bin_prefix}. That is, a string starting with the directory +portion of @var{progname}, followed by a relative pathname of the +difference between @var{bin_prefix} and @var{prefix}. + +If @var{progname} does not contain any directory separators, +@code{make_relative_prefix} will search @env{PATH} to find a program +named @var{progname}. Also, if @var{progname} is a symbolic link, +the symbolic link will be resolved. + +For example, if @var{bin_prefix} is @code{/alpha/beta/gamma/gcc/delta}, +@var{prefix} is @code{/alpha/beta/gamma/omega/}, and @var{progname} is +@code{/red/green/blue/gcc}, then this function will return +@code{/red/green/blue/../../omega/}. + +The return value is normally allocated via @code{malloc}. If no +relative prefix can be found, return @code{NULL}. + +@end deftypefn + +*/ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#ifdef HAVE_STDLIB_H +#include +#endif +#ifdef HAVE_UNISTD_H +#include +#endif + +#include + +#include "ansidecl.h" +#include "libiberty.h" + +#ifndef R_OK +#define R_OK 4 +#define W_OK 2 +#define X_OK 1 +#endif + +#ifndef DIR_SEPARATOR +# define DIR_SEPARATOR '/' +#endif + +#if defined (_WIN32) || defined (__MSDOS__) \ + || defined (__DJGPP__) || defined (__OS2__) +# define HAVE_DOS_BASED_FILE_SYSTEM +# define HAVE_HOST_EXECUTABLE_SUFFIX +# define HOST_EXECUTABLE_SUFFIX ".exe" +# ifndef DIR_SEPARATOR_2 +# define DIR_SEPARATOR_2 '\\' +# endif +# define PATH_SEPARATOR ';' +#else +# define PATH_SEPARATOR ':' +#endif + +#ifndef DIR_SEPARATOR_2 +# define IS_DIR_SEPARATOR(ch) ((ch) == DIR_SEPARATOR) +#else +# define IS_DIR_SEPARATOR(ch) \ + (((ch) == DIR_SEPARATOR) || ((ch) == DIR_SEPARATOR_2)) +#endif + +#define DIR_UP ".." + +static char *save_string PARAMS ((const char *, int)); +static char **split_directories PARAMS ((const char *, int *)); +static void free_split_directories PARAMS ((char **)); + +static char * +save_string (s, len) + const char *s; + int len; +{ + char *result = malloc (len + 1); + + memcpy (result, s, len); + result[len] = 0; + return result; +} + +/* Split a filename into component directories. */ + +static char ** +split_directories (name, ptr_num_dirs) + const char *name; + int *ptr_num_dirs; +{ + int num_dirs = 0; + char **dirs; + const char *p, *q; + int ch; + + /* Count the number of directories. Special case MSDOS disk names as part + of the initial directory. */ + p = name; +#ifdef HAVE_DOS_BASED_FILE_SYSTEM + if (name[1] == ':' && IS_DIR_SEPARATOR (name[2])) + { + p += 3; + num_dirs++; + } +#endif /* HAVE_DOS_BASED_FILE_SYSTEM */ + + while ((ch = *p++) != '\0') + { + if (IS_DIR_SEPARATOR (ch)) + { + num_dirs++; + while (IS_DIR_SEPARATOR (*p)) + p++; + } + } + + dirs = (char **) malloc (sizeof (char *) * (num_dirs + 2)); + if (dirs == NULL) + return NULL; + + /* Now copy the directory parts. */ + num_dirs = 0; + p = name; +#ifdef HAVE_DOS_BASED_FILE_SYSTEM + if (name[1] == ':' && IS_DIR_SEPARATOR (name[2])) + { + dirs[num_dirs++] = save_string (p, 3); + if (dirs[num_dirs - 1] == NULL) + { + free (dirs); + return NULL; + } + p += 3; + } +#endif /* HAVE_DOS_BASED_FILE_SYSTEM */ + + q = p; + while ((ch = *p++) != '\0') + { + if (IS_DIR_SEPARATOR (ch)) + { + while (IS_DIR_SEPARATOR (*p)) + p++; + + dirs[num_dirs++] = save_string (q, p - q); + if (dirs[num_dirs - 1] == NULL) + { + dirs[num_dirs] = NULL; + free_split_directories (dirs); + return NULL; + } + q = p; + } + } + + if (p - 1 - q > 0) + dirs[num_dirs++] = save_string (q, p - 1 - q); + dirs[num_dirs] = NULL; + + if (dirs[num_dirs - 1] == NULL) + { + free_split_directories (dirs); + return NULL; + } + + if (ptr_num_dirs) + *ptr_num_dirs = num_dirs; + return dirs; +} + +/* Release storage held by split directories. */ + +static void +free_split_directories (dirs) + char **dirs; +{ + int i = 0; + + while (dirs[i] != NULL) + free (dirs[i++]); + + free ((char *) dirs); +} + +/* Given three strings PROGNAME, BIN_PREFIX, PREFIX, return a string that gets + to PREFIX starting with the directory portion of PROGNAME and a relative + pathname of the difference between BIN_PREFIX and PREFIX. + + For example, if BIN_PREFIX is /alpha/beta/gamma/gcc/delta, PREFIX is + /alpha/beta/gamma/omega/, and PROGNAME is /red/green/blue/gcc, then this + function will return /red/green/blue/../../omega/. + + If no relative prefix can be found, return NULL. */ + +char * +make_relative_prefix (progname, bin_prefix, prefix) + const char *progname; + const char *bin_prefix; + const char *prefix; +{ + char **prog_dirs, **bin_dirs, **prefix_dirs; + int prog_num, bin_num, prefix_num; + int i, n, common; + int needed_len; + char *ret, *ptr, *full_progname = NULL; + + if (progname == NULL || bin_prefix == NULL || prefix == NULL) + return NULL; + + /* If there is no full pathname, try to find the program by checking in each + of the directories specified in the PATH environment variable. */ + if (lbasename (progname) == progname) + { + char *temp; + + temp = getenv ("PATH"); + if (temp) + { + char *startp, *endp, *nstore; + size_t prefixlen = strlen (temp) + 1; + if (prefixlen < 2) + prefixlen = 2; + + nstore = (char *) alloca (prefixlen + strlen (progname) + 1); + + startp = endp = temp; + while (1) + { + if (*endp == PATH_SEPARATOR || *endp == 0) + { + if (endp == startp) + { + nstore[0] = '.'; + nstore[1] = DIR_SEPARATOR; + nstore[2] = '\0'; + } + else + { + strncpy (nstore, startp, endp - startp); + if (! IS_DIR_SEPARATOR (endp[-1])) + { + nstore[endp - startp] = DIR_SEPARATOR; + nstore[endp - startp + 1] = 0; + } + else + nstore[endp - startp] = 0; + } + strcat (nstore, progname); + if (! access (nstore, X_OK) +#ifdef HAVE_HOST_EXECUTABLE_SUFFIX + || ! access (strcat (nstore, HOST_EXECUTABLE_SUFFIX), X_OK) +#endif + ) + { + progname = nstore; + break; + } + + if (*endp == 0) + break; + endp = startp = endp + 1; + } + else + endp++; + } + } + } + + full_progname = lrealpath (progname); + if (full_progname == NULL) + return NULL; + + prog_dirs = split_directories (full_progname, &prog_num); + bin_dirs = split_directories (bin_prefix, &bin_num); + free (full_progname); + if (bin_dirs == NULL || prog_dirs == NULL) + return NULL; + + /* Remove the program name from comparison of directory names. */ + prog_num--; + + /* If we are still installed in the standard location, we don't need to + specify relative directories. Also, if argv[0] still doesn't contain + any directory specifiers after the search above, then there is not much + we can do. */ + if (prog_num == bin_num) + { + for (i = 0; i < bin_num; i++) + { + if (strcmp (prog_dirs[i], bin_dirs[i]) != 0) + break; + } + + if (prog_num <= 0 || i == bin_num) + { + free_split_directories (prog_dirs); + free_split_directories (bin_dirs); + prog_dirs = bin_dirs = (char **) 0; + return NULL; + } + } + + prefix_dirs = split_directories (prefix, &prefix_num); + if (prefix_dirs == NULL) + { + free_split_directories (prog_dirs); + free_split_directories (bin_dirs); + return NULL; + } + + /* Find how many directories are in common between bin_prefix & prefix. */ + n = (prefix_num < bin_num) ? prefix_num : bin_num; + for (common = 0; common < n; common++) + { + if (strcmp (bin_dirs[common], prefix_dirs[common]) != 0) + break; + } + + /* If there are no common directories, there can be no relative prefix. */ + if (common == 0) + { + free_split_directories (prog_dirs); + free_split_directories (bin_dirs); + free_split_directories (prefix_dirs); + return NULL; + } + + /* Two passes: first figure out the size of the result string, and + then construct it. */ + needed_len = 0; + for (i = 0; i < prog_num; i++) + needed_len += strlen (prog_dirs[i]); + needed_len += sizeof (DIR_UP) * (bin_num - common); + for (i = common; i < prefix_num; i++) + needed_len += strlen (prefix_dirs[i]); + needed_len += 1; /* Trailing NUL. */ + + ret = (char *) malloc (needed_len); + if (ret == NULL) + return NULL; + + /* Build up the pathnames in argv[0]. */ + *ret = '\0'; + for (i = 0; i < prog_num; i++) + strcat (ret, prog_dirs[i]); + + /* Now build up the ..'s. */ + ptr = ret + strlen(ret); + for (i = common; i < bin_num; i++) + { + strcpy (ptr, DIR_UP); + ptr += sizeof (DIR_UP) - 1; + *(ptr++) = DIR_SEPARATOR; + } + *ptr = '\0'; + + /* Put in directories to move over to prefix. */ + for (i = common; i < prefix_num; i++) + strcat (ret, prefix_dirs[i]); + + free_split_directories (prog_dirs); + free_split_directories (bin_dirs); + free_split_directories (prefix_dirs); + + return ret; +} diff --git a/libiberty/mempcpy.c b/libiberty/mempcpy.c new file mode 100644 index 0000000..b0dccfa --- /dev/null +++ b/libiberty/mempcpy.c @@ -0,0 +1,48 @@ +/* Implement the mempcpy function. + Copyright (C) 2003 Free Software Foundation, Inc. + Written by Kaveh R. Ghazi . + +This file is part of the libiberty library. +Libiberty is free software; you can redistribute it and/or +modify it under the terms of the GNU Library General Public +License as published by the Free Software Foundation; either +version 2 of the License, or (at your option) any later version. + +Libiberty is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +Library General Public License for more details. + +You should have received a copy of the GNU Library General Public +License along with libiberty; see the file COPYING.LIB. If +not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* + +@deftypefn Supplemental void* mempcpy (void *@var{out}, const void *@var{in}, size_t @var{length}) + +Copies @var{length} bytes from memory region @var{in} to region +@var{out}. Returns a pointer to @var{out} + @var{length}. + +@end deftypefn + +*/ + +#include +#ifdef ANSI_PROTOTYPES +#include +#else +#define size_t unsigned long +#endif + +extern PTR memcpy PARAMS ((PTR, const PTR, size_t)); + +PTR +mempcpy (dst, src, len) + PTR dst; + const PTR src; + size_t len; +{ + return (char *) memcpy (dst, src, len) + len; +} diff --git a/libiberty/pex-common.h b/libiberty/pex-common.h new file mode 100644 index 0000000..da2f71e --- /dev/null +++ b/libiberty/pex-common.h @@ -0,0 +1,42 @@ +/* Utilities to execute a program in a subprocess (possibly linked by pipes + with other subprocesses), and wait for it. Shared logic. + Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2003 + Free Software Foundation, Inc. + +This file is part of the libiberty library. +Libiberty is free software; you can redistribute it and/or +modify it under the terms of the GNU Library General Public +License as published by the Free Software Foundation; either +version 2 of the License, or (at your option) any later version. + +Libiberty is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +Library General Public License for more details. + +You should have received a copy of the GNU Library General Public +License along with libiberty; see the file COPYING.LIB. If not, +write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#ifndef PEX_COMMON_H +#define PEX_COMMON_H + +#include "config.h" +#include "libiberty.h" + +#define install_error_msg "installation problem, cannot exec `%s'" + +/* stdin file number. */ +#define STDIN_FILE_NO 0 + +/* stdout file number. */ +#define STDOUT_FILE_NO 1 + +/* value of `pipe': port index for reading. */ +#define READ_PORT 0 + +/* value of `pipe': port index for writing. */ +#define WRITE_PORT 1 + +#endif diff --git a/libiberty/pex-djgpp.c b/libiberty/pex-djgpp.c new file mode 100644 index 0000000..968e784 --- /dev/null +++ b/libiberty/pex-djgpp.c @@ -0,0 +1,103 @@ +/* Utilities to execute a program in a subprocess (possibly linked by pipes + with other subprocesses), and wait for it. DJGPP specialization. + Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2003 + Free Software Foundation, Inc. + +This file is part of the libiberty library. +Libiberty is free software; you can redistribute it and/or +modify it under the terms of the GNU Library General Public +License as published by the Free Software Foundation; either +version 2 of the License, or (at your option) any later version. + +Libiberty is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +Library General Public License for more details. + +You should have received a copy of the GNU Library General Public +License along with libiberty; see the file COPYING.LIB. If not, +write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#include "pex-common.h" + +#include +#include +#ifdef NEED_DECLARATION_ERRNO +extern int errno; +#endif +#ifdef HAVE_STDLIB_H +#include +#endif +#include + +/* Use ECHILD if available, otherwise use EINVAL. */ +#ifdef ECHILD +#define PWAIT_ERROR ECHILD +#else +#define PWAIT_ERROR EINVAL +#endif + +/* MSDOS doesn't multitask, but for the sake of a consistent interface + the code behaves like it does. pexecute runs the program, tucks the + exit code away, and returns a "pid". pwait must be called to fetch the + exit code. */ + +/* For communicating information from pexecute to pwait. */ +static int last_pid = 0; +static int last_status = 0; +static int last_reaped = 0; + +int +pexecute (program, argv, this_pname, temp_base, errmsg_fmt, errmsg_arg, flags) + const char *program; + char * const *argv; + const char *this_pname; + const char *temp_base; + char **errmsg_fmt, **errmsg_arg; + int flags; +{ + int rc; + + last_pid++; + if (last_pid < 0) + last_pid = 1; + + if ((flags & PEXECUTE_ONE) != PEXECUTE_ONE) + abort (); + + /* ??? What are the possible return values from spawnv? */ + rc = (flags & PEXECUTE_SEARCH ? spawnvp : spawnv) (P_WAIT, program, argv); + + if (rc == -1) + { + *errmsg_fmt = install_error_msg; + *errmsg_arg = (char *)program; + return -1; + } + + /* Tuck the status away for pwait, and return a "pid". */ + last_status = rc << 8; + return last_pid; +} + +int +pwait (pid, status, flags) + int pid; + int *status; + int flags; +{ + /* On MSDOS each pexecute must be followed by its associated pwait. */ + if (pid != last_pid + /* Called twice for the same child? */ + || pid == last_reaped) + { + errno = PWAIT_ERROR; + return -1; + } + /* ??? Here's an opportunity to canonicalize the values in STATUS. + Needed? */ + *status = (last_status >> 8); + last_reaped = last_pid; + return last_pid; +} diff --git a/libiberty/pex-mpw.c b/libiberty/pex-mpw.c new file mode 100644 index 0000000..9a8879c --- /dev/null +++ b/libiberty/pex-mpw.c @@ -0,0 +1,161 @@ +/* Utilities to execute a program in a subprocess (possibly linked by pipes + with other subprocesses), and wait for it. MPW specialization. + Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2003 + Free Software Foundation, Inc. + +This file is part of the libiberty library. +Libiberty is free software; you can redistribute it and/or +modify it under the terms of the GNU Library General Public +License as published by the Free Software Foundation; either +version 2 of the License, or (at your option) any later version. + +Libiberty is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +Library General Public License for more details. + +You should have received a copy of the GNU Library General Public +License along with libiberty; see the file COPYING.LIB. If not, +write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#include "pex-common.h" + +#include +#ifdef HAVE_STRING_H +#include +#endif + +/* MPW pexecute doesn't actually run anything; instead, it writes out + script commands that, when run, will do the actual executing. + + For example, in GCC's case, GCC will write out several script commands: + + cpp ... + cc1 ... + as ... + ld ... + + and then exit. None of the above programs will have run yet. The task + that called GCC will then execute the script and cause cpp,etc. to run. + The caller must invoke pfinish before calling exit. This adds + the finishing touches to the generated script. */ + +static int first_time = 1; + +extern void mpwify_filename PARAMS ((const char *, char *)); + +int +pexecute (program, argv, this_pname, temp_base, errmsg_fmt, errmsg_arg, flags) + const char *program; + char * const *argv; + const char *this_pname; + const char *temp_base; + char **errmsg_fmt, **errmsg_arg; + int flags; +{ + char tmpprogram[255]; + char *cp, *tmpname; + int i; + + mpwify_filename (program, tmpprogram); + if (first_time) + { + printf ("Set Failed 0\n"); + first_time = 0; + } + + fputs ("If {Failed} == 0\n", stdout); + /* If being verbose, output a copy of the command. It should be + accurate enough and escaped enough to be "clickable". */ + if (flags & PEXECUTE_VERBOSE) + { + fputs ("\tEcho ", stdout); + fputc ('\'', stdout); + fputs (tmpprogram, stdout); + fputc ('\'', stdout); + fputc (' ', stdout); + for (i=1; argv[i]; i++) + { + fputc ('\'', stdout); + /* See if we have an argument that needs fixing. */ + if (strchr(argv[i], '/')) + { + tmpname = (char *) xmalloc (256); + mpwify_filename (argv[i], tmpname); + argv[i] = tmpname; + } + for (cp = argv[i]; *cp; cp++) + { + /* Write an Option-d escape char in front of special chars. */ + if (strchr("'+", *cp)) + fputc ('\266', stdout); + fputc (*cp, stdout); + } + fputc ('\'', stdout); + fputc (' ', stdout); + } + fputs ("\n", stdout); + } + fputs ("\t", stdout); + fputs (tmpprogram, stdout); + fputc (' ', stdout); + + for (i=1; argv[i]; i++) + { + /* See if we have an argument that needs fixing. */ + if (strchr(argv[i], '/')) + { + tmpname = (char *) xmalloc (256); + mpwify_filename (argv[i], tmpname); + argv[i] = tmpname; + } + if (strchr (argv[i], ' ')) + fputc ('\'', stdout); + for (cp = argv[i]; *cp; cp++) + { + /* Write an Option-d escape char in front of special chars. */ + if (strchr("'+", *cp)) + fputc ('\266', stdout); + fputc (*cp, stdout); + } + if (strchr (argv[i], ' ')) + fputc ('\'', stdout); + fputc (' ', stdout); + } + + fputs ("\n", stdout); + + /* Output commands that arrange to clean up and exit if a failure occurs. + We have to be careful to collect the status from the program that was + run, rather than some other script command. Also, we don't exit + immediately, since necessary cleanups are at the end of the script. */ + fputs ("\tSet TmpStatus {Status}\n", stdout); + fputs ("\tIf {TmpStatus} != 0\n", stdout); + fputs ("\t\tSet Failed {TmpStatus}\n", stdout); + fputs ("\tEnd\n", stdout); + fputs ("End\n", stdout); + + /* We're just composing a script, can't fail here. */ + return 0; +} + +int +pwait (pid, status, flags) + int pid; + int *status; + int flags; +{ + *status = 0; + return 0; +} + +/* Write out commands that will exit with the correct error code + if something in the script failed. */ + +void +pfinish () +{ + printf ("\tExit \"{Failed}\"\n"); +} + diff --git a/libiberty/pex-msdos.c b/libiberty/pex-msdos.c new file mode 100644 index 0000000..d61c129 --- /dev/null +++ b/libiberty/pex-msdos.c @@ -0,0 +1,147 @@ +/* Utilities to execute a program in a subprocess (possibly linked by pipes + with other subprocesses), and wait for it. Generic MSDOS specialization. + Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2003 + Free Software Foundation, Inc. + +This file is part of the libiberty library. +Libiberty is free software; you can redistribute it and/or +modify it under the terms of the GNU Library General Public +License as published by the Free Software Foundation; either +version 2 of the License, or (at your option) any later version. + +Libiberty is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +Library General Public License for more details. + +You should have received a copy of the GNU Library General Public +License along with libiberty; see the file COPYING.LIB. If not, +write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#include "pex-common.h" + +#include +#include +#ifdef NEED_DECLARATION_ERRNO +extern int errno; +#endif +#ifdef HAVE_STRING_H +#include +#endif +#ifdef HAVE_STDLIB_H +#include +#endif + +#include "safe-ctype.h" +#include + +/* MSDOS doesn't multitask, but for the sake of a consistent interface + the code behaves like it does. pexecute runs the program, tucks the + exit code away, and returns a "pid". pwait must be called to fetch the + exit code. */ + +/* For communicating information from pexecute to pwait. */ +static int last_pid = 0; +static int last_status = 0; +static int last_reaped = 0; + +int +pexecute (program, argv, this_pname, temp_base, errmsg_fmt, errmsg_arg, flags) + const char *program; + char * const *argv; + const char *this_pname; + const char *temp_base; + char **errmsg_fmt, **errmsg_arg; + int flags; +{ + int rc; + char *scmd, *rf; + FILE *argfile; + int i, el = flags & PEXECUTE_SEARCH ? 4 : 0; + + last_pid++; + if (last_pid < 0) + last_pid = 1; + + if ((flags & PEXECUTE_ONE) != PEXECUTE_ONE) + abort (); + + if (temp_base == 0) + temp_base = choose_temp_base (); + scmd = (char *) xmalloc (strlen (program) + strlen (temp_base) + 6 + el); + rf = scmd + strlen(program) + 2 + el; + sprintf (scmd, "%s%s @%s.gp", program, + (flags & PEXECUTE_SEARCH ? ".exe" : ""), temp_base); + argfile = fopen (rf, "w"); + if (argfile == 0) + { + int errno_save = errno; + free (scmd); + errno = errno_save; + *errmsg_fmt = "cannot open `%s.gp'"; + *errmsg_arg = temp_base; + return -1; + } + + for (i=1; argv[i]; i++) + { + char *cp; + for (cp = argv[i]; *cp; cp++) + { + if (*cp == '"' || *cp == '\'' || *cp == '\\' || ISSPACE (*cp)) + fputc ('\\', argfile); + fputc (*cp, argfile); + } + fputc ('\n', argfile); + } + fclose (argfile); + + rc = system (scmd); + + { + int errno_save = errno; + remove (rf); + free (scmd); + errno = errno_save; + } + + if (rc == -1) + { + *errmsg_fmt = install_error_msg; + *errmsg_arg = (char *)program; + return -1; + } + + /* Tuck the status away for pwait, and return a "pid". */ + last_status = rc << 8; + return last_pid; +} + +/* Use ECHILD if available, otherwise use EINVAL. */ +#ifdef ECHILD +#define PWAIT_ERROR ECHILD +#else +#define PWAIT_ERROR EINVAL +#endif + +int +pwait (pid, status, flags) + int pid; + int *status; + int flags; +{ + /* On MSDOS each pexecute must be followed by its associated pwait. */ + if (pid != last_pid + /* Called twice for the same child? */ + || pid == last_reaped) + { + errno = PWAIT_ERROR; + return -1; + } + /* ??? Here's an opportunity to canonicalize the values in STATUS. + Needed? */ + *status = last_status; + last_reaped = last_pid; + return last_pid; +} diff --git a/libiberty/pex-os2.c b/libiberty/pex-os2.c new file mode 100644 index 0000000..d9eacf1 --- /dev/null +++ b/libiberty/pex-os2.c @@ -0,0 +1,72 @@ +/* Utilities to execute a program in a subprocess (possibly linked by pipes + with other subprocesses), and wait for it. OS/2 specialization. + Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2003 + Free Software Foundation, Inc. + +This file is part of the libiberty library. +Libiberty is free software; you can redistribute it and/or +modify it under the terms of the GNU Library General Public +License as published by the Free Software Foundation; either +version 2 of the License, or (at your option) any later version. + +Libiberty is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +Library General Public License for more details. + +You should have received a copy of the GNU Library General Public +License along with libiberty; see the file COPYING.LIB. If not, +write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#include "pex-common.h" + +#ifdef HAVE_UNISTD_H +#include +#endif +#ifdef HAVE_STDLIB_H +#include +#endif +#ifdef HAVE_SYS_WAIT_H +#include +#endif + +/* ??? Does OS2 have process.h? */ +extern int spawnv (); +extern int spawnvp (); + +int +pexecute (program, argv, this_pname, temp_base, errmsg_fmt, errmsg_arg, flags) + const char *program; + char * const *argv; + const char *this_pname; + const char *temp_base; + char **errmsg_fmt, **errmsg_arg; + int flags; +{ + int pid; + + if ((flags & PEXECUTE_ONE) != PEXECUTE_ONE) + abort (); + /* ??? Presumably 1 == _P_NOWAIT. */ + pid = (flags & PEXECUTE_SEARCH ? spawnvp : spawnv) (1, program, argv); + if (pid == -1) + { + *errmsg_fmt = install_error_msg; + *errmsg_arg = program; + return -1; + } + return pid; +} + +int +pwait (pid, status, flags) + int pid; + int *status; + int flags; +{ + /* ??? Here's an opportunity to canonicalize the values in STATUS. + Needed? */ + int pid = wait (status); + return pid; +} diff --git a/libiberty/pex-unix.c b/libiberty/pex-unix.c new file mode 100644 index 0000000..14fe71e --- /dev/null +++ b/libiberty/pex-unix.c @@ -0,0 +1,166 @@ +/* Utilities to execute a program in a subprocess (possibly linked by pipes + with other subprocesses), and wait for it. Generic Unix version + (also used for UWIN and VMS). + Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2003 + Free Software Foundation, Inc. + +This file is part of the libiberty library. +Libiberty is free software; you can redistribute it and/or +modify it under the terms of the GNU Library General Public +License as published by the Free Software Foundation; either +version 2 of the License, or (at your option) any later version. + +Libiberty is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +Library General Public License for more details. + +You should have received a copy of the GNU Library General Public +License along with libiberty; see the file COPYING.LIB. If not, +write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#include "pex-common.h" + +#include +#include +#ifdef NEED_DECLARATION_ERRNO +extern int errno; +#endif +#ifdef HAVE_STRING_H +#include +#endif +#ifdef HAVE_UNISTD_H +#include +#endif +#ifdef HAVE_STDLIB_H +#include +#endif +#ifdef HAVE_SYS_WAIT_H +#include +#endif + +#ifndef HAVE_WAITPID +#define waitpid(pid, status, flags) wait(status) +#endif + +extern int execv (); +extern int execvp (); + +int +pexecute (program, argv, this_pname, temp_base, errmsg_fmt, errmsg_arg, flags) + const char *program; + char * const *argv; + const char *this_pname; + const char *temp_base ATTRIBUTE_UNUSED; + char **errmsg_fmt, **errmsg_arg; + int flags; +{ + int (*func)() = (flags & PEXECUTE_SEARCH ? execvp : execv); + int pid; + int pdes[2]; + int input_desc, output_desc; + int retries, sleep_interval; + /* Pipe waiting from last process, to be used as input for the next one. + Value is STDIN_FILE_NO if no pipe is waiting + (i.e. the next command is the first of a group). */ + static int last_pipe_input; + + /* If this is the first process, initialize. */ + if (flags & PEXECUTE_FIRST) + last_pipe_input = STDIN_FILE_NO; + + input_desc = last_pipe_input; + + /* If this isn't the last process, make a pipe for its output, + and record it as waiting to be the input to the next process. */ + if (! (flags & PEXECUTE_LAST)) + { + if (pipe (pdes) < 0) + { + *errmsg_fmt = "pipe"; + *errmsg_arg = NULL; + return -1; + } + output_desc = pdes[WRITE_PORT]; + last_pipe_input = pdes[READ_PORT]; + } + else + { + /* Last process. */ + output_desc = STDOUT_FILE_NO; + last_pipe_input = STDIN_FILE_NO; + } + + /* Fork a subprocess; wait and retry if it fails. */ + sleep_interval = 1; + pid = -1; + for (retries = 0; retries < 4; retries++) + { + pid = fork (); + if (pid >= 0) + break; + sleep (sleep_interval); + sleep_interval *= 2; + } + + switch (pid) + { + case -1: + *errmsg_fmt = "fork"; + *errmsg_arg = NULL; + return -1; + + case 0: /* child */ + /* Move the input and output pipes into place, if necessary. */ + if (input_desc != STDIN_FILE_NO) + { + close (STDIN_FILE_NO); + dup (input_desc); + close (input_desc); + } + if (output_desc != STDOUT_FILE_NO) + { + close (STDOUT_FILE_NO); + dup (output_desc); + close (output_desc); + } + + /* Close the parent's descs that aren't wanted here. */ + if (last_pipe_input != STDIN_FILE_NO) + close (last_pipe_input); + + /* Exec the program. */ + (*func) (program, argv); + + fprintf (stderr, "%s: ", this_pname); + fprintf (stderr, install_error_msg, program); + fprintf (stderr, ": %s\n", xstrerror (errno)); + exit (-1); + /* NOTREACHED */ + return 0; + + default: + /* In the parent, after forking. + Close the descriptors that we made for this child. */ + if (input_desc != STDIN_FILE_NO) + close (input_desc); + if (output_desc != STDOUT_FILE_NO) + close (output_desc); + + /* Return child's process number. */ + return pid; + } +} + +int +pwait (pid, status, flags) + int pid; + int *status; + int flags ATTRIBUTE_UNUSED; +{ + /* ??? Here's an opportunity to canonicalize the values in STATUS. + Needed? */ + pid = waitpid (pid, status, 0); + return pid; +} diff --git a/libiberty/pex-win32.c b/libiberty/pex-win32.c new file mode 100644 index 0000000..27a5bb4 --- /dev/null +++ b/libiberty/pex-win32.c @@ -0,0 +1,250 @@ +/* Utilities to execute a program in a subprocess (possibly linked by pipes + with other subprocesses), and wait for it. Generic Win32 specialization. + Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2003 + Free Software Foundation, Inc. + +This file is part of the libiberty library. +Libiberty is free software; you can redistribute it and/or +modify it under the terms of the GNU Library General Public +License as published by the Free Software Foundation; either +version 2 of the License, or (at your option) any later version. + +Libiberty is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +Library General Public License for more details. + +You should have received a copy of the GNU Library General Public +License along with libiberty; see the file COPYING.LIB. If not, +write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#include "pex-common.h" + +#ifdef HAVE_STRING_H +#include +#endif +#ifdef HAVE_UNISTD_H +#include +#endif +#ifdef HAVE_SYS_WAIT_H +#include +#endif + +#include +#include +#include +#include + +/* mingw32 headers may not define the following. */ + +#ifndef _P_WAIT +# define _P_WAIT 0 +# define _P_NOWAIT 1 +# define _P_OVERLAY 2 +# define _P_NOWAITO 3 +# define _P_DETACH 4 + +# define WAIT_CHILD 0 +# define WAIT_GRANDCHILD 1 +#endif + +/* This is a kludge to get around the Microsoft C spawn functions' propensity + to remove the outermost set of double quotes from all arguments. */ + +static const char * const * +fix_argv (argvec) + char **argvec; +{ + int i; + char * command0 = argvec[0]; + + /* Ensure that the executable pathname uses Win32 backslashes. */ + for (; *command0 != '\0'; command0++) + if (*command0 == '/') + *command0 = '\\'; + + for (i = 1; argvec[i] != 0; i++) + { + int len, j; + char *temp, *newtemp; + + temp = argvec[i]; + len = strlen (temp); + for (j = 0; j < len; j++) + { + if (temp[j] == '"') + { + newtemp = xmalloc (len + 2); + strncpy (newtemp, temp, j); + newtemp [j] = '\\'; + strncpy (&newtemp [j+1], &temp [j], len-j); + newtemp [len+1] = 0; + temp = newtemp; + len++; + j++; + } + } + + argvec[i] = temp; + } + + for (i = 0; argvec[i] != 0; i++) + { + if (strpbrk (argvec[i], " \t")) + { + int len, trailing_backslash; + char *temp; + + len = strlen (argvec[i]); + trailing_backslash = 0; + + /* There is an added complication when an arg with embedded white + space ends in a backslash (such as in the case of -iprefix arg + passed to cpp). The resulting quoted strings gets misinterpreted + by the command interpreter -- it thinks that the ending quote + is escaped by the trailing backslash and things get confused. + We handle this case by escaping the trailing backslash, provided + it was not escaped in the first place. */ + if (len > 1 + && argvec[i][len-1] == '\\' + && argvec[i][len-2] != '\\') + { + trailing_backslash = 1; + ++len; /* to escape the final backslash. */ + } + + len += 2; /* and for the enclosing quotes. */ + + temp = xmalloc (len + 1); + temp[0] = '"'; + strcpy (temp + 1, argvec[i]); + if (trailing_backslash) + temp[len-2] = '\\'; + temp[len-1] = '"'; + temp[len] = '\0'; + + argvec[i] = temp; + } + } + + return (const char * const *) argvec; +} + +/* Win32 supports pipes */ +int +pexecute (program, argv, this_pname, temp_base, errmsg_fmt, errmsg_arg, flags) + const char *program; + char * const *argv; + const char *this_pname ATTRIBUTE_UNUSED; + const char *temp_base ATTRIBUTE_UNUSED; + char **errmsg_fmt, **errmsg_arg; + int flags; +{ + int pid; + int pdes[2]; + int org_stdin = -1; + int org_stdout = -1; + int input_desc, output_desc; + + /* Pipe waiting from last process, to be used as input for the next one. + Value is STDIN_FILE_NO if no pipe is waiting + (i.e. the next command is the first of a group). */ + static int last_pipe_input; + + /* If this is the first process, initialize. */ + if (flags & PEXECUTE_FIRST) + last_pipe_input = STDIN_FILE_NO; + + input_desc = last_pipe_input; + + /* If this isn't the last process, make a pipe for its output, + and record it as waiting to be the input to the next process. */ + if (! (flags & PEXECUTE_LAST)) + { + if (_pipe (pdes, 256, O_BINARY) < 0) + { + *errmsg_fmt = "pipe"; + *errmsg_arg = NULL; + return -1; + } + output_desc = pdes[WRITE_PORT]; + last_pipe_input = pdes[READ_PORT]; + } + else + { + /* Last process. */ + output_desc = STDOUT_FILE_NO; + last_pipe_input = STDIN_FILE_NO; + } + + if (input_desc != STDIN_FILE_NO) + { + org_stdin = dup (STDIN_FILE_NO); + dup2 (input_desc, STDIN_FILE_NO); + close (input_desc); + } + + if (output_desc != STDOUT_FILE_NO) + { + org_stdout = dup (STDOUT_FILE_NO); + dup2 (output_desc, STDOUT_FILE_NO); + close (output_desc); + } + + pid = (flags & PEXECUTE_SEARCH ? _spawnvp : _spawnv) + (_P_NOWAIT, program, fix_argv(argv)); + + if (input_desc != STDIN_FILE_NO) + { + dup2 (org_stdin, STDIN_FILE_NO); + close (org_stdin); + } + + if (output_desc != STDOUT_FILE_NO) + { + dup2 (org_stdout, STDOUT_FILE_NO); + close (org_stdout); + } + + if (pid == -1) + { + *errmsg_fmt = install_error_msg; + *errmsg_arg = (char*) program; + return -1; + } + + return pid; +} + +/* MS CRTDLL doesn't return enough information in status to decide if the + child exited due to a signal or not, rather it simply returns an + integer with the exit code of the child; eg., if the child exited with + an abort() call and didn't have a handler for SIGABRT, it simply returns + with status = 3. We fix the status code to conform to the usual WIF* + macros. Note that WIFSIGNALED will never be true under CRTDLL. */ + +int +pwait (pid, status, flags) + int pid; + int *status; + int flags ATTRIBUTE_UNUSED; +{ + int termstat; + + pid = _cwait (&termstat, pid, WAIT_CHILD); + + /* ??? Here's an opportunity to canonicalize the values in STATUS. + Needed? */ + + /* cwait returns the child process exit code in termstat. + A value of 3 indicates that the child caught a signal, but not + which one. Since only SIGABRT, SIGFPE and SIGINT do anything, we + report SIGABRT. */ + if (termstat == 3) + *status = SIGABRT; + else + *status = (((termstat) & 0xff) << 8); + + return pid; +} diff --git a/libiberty/pexecute.txh b/libiberty/pexecute.txh new file mode 100644 index 0000000..269f031 --- /dev/null +++ b/libiberty/pexecute.txh @@ -0,0 +1,63 @@ +@deftypefn Extension int pexecute (const char *@var{program}, char * const *@var{argv}, const char *@var{this_pname}, const char *@var{temp_base}, char **@var{errmsg_fmt}, char **@var{errmsg_arg}, int flags) + +Executes a program. + +@var{program} and @var{argv} are the arguments to +@code{execv}/@code{execvp}. + +@var{this_pname} is name of the calling program (i.e., @code{argv[0]}). + +@var{temp_base} is the path name, sans suffix, of a temporary file to +use if needed. This is currently only needed for MS-DOS ports that +don't use @code{go32} (do any still exist?). Ports that don't need it +can pass @code{NULL}. + +(@code{@var{flags} & PEXECUTE_SEARCH}) is non-zero if @env{PATH} +should be searched (??? It's not clear that GCC passes this flag +correctly). (@code{@var{flags} & PEXECUTE_FIRST}) is nonzero for the +first process in chain. (@code{@var{flags} & PEXECUTE_FIRST}) is +nonzero for the last process in chain. The first/last flags could be +simplified to only mark the last of a chain of processes but that +requires the caller to always mark the last one (and not give up +early if some error occurs). It's more robust to require the caller +to mark both ends of the chain. + +The result is the pid on systems like Unix where we +@code{fork}/@code{exec} and on systems like WIN32 and OS/2 where we +use @code{spawn}. It is up to the caller to wait for the child. + +The result is the @code{WEXITSTATUS} on systems like MS-DOS where we +@code{spawn} and wait for the child here. + +Upon failure, @var{errmsg_fmt} and @var{errmsg_arg} are set to the +text of the error message with an optional argument (if not needed, +@var{errmsg_arg} is set to @code{NULL}), and @minus{}1 is returned. +@code{errno} is available to the caller to use. + +@end deftypefn + +@deftypefn Extension int pwait (int @var{pid}, int *@var{status}, int @var{flags}) + +Waits for a program started by @code{pexecute} to finish. + +@var{pid} is the process id of the task to wait for. @var{status} is +the `status' argument to wait. @var{flags} is currently unused +(allows future enhancement without breaking upward compatibility). +Pass 0 for now. + +The result is the pid of the child reaped, or -1 for failure +(@code{errno} says why). + +On systems that don't support waiting for a particular child, +@var{pid} is ignored. On systems like MS-DOS that don't really +multitask @code{pwait} is just a mechanism to provide a consistent +interface for the caller. + +@end deftypefn + +@undocumented pfinish + +pfinish: finish generation of script + +pfinish is necessary for systems like MPW where a script is generated +that runs the requested programs. diff --git a/libiberty/physmem.c b/libiberty/physmem.c new file mode 100644 index 0000000..f64e07c --- /dev/null +++ b/libiberty/physmem.c @@ -0,0 +1,305 @@ +/* Calculate the size of physical memory. + Copyright 2000, 2001, 2003 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* Written by Paul Eggert. */ + +#if HAVE_CONFIG_H +# include +#endif + +#if HAVE_UNISTD_H +# include +#endif + +#if HAVE_SYS_PSTAT_H +# include +#endif + +#if HAVE_SYS_SYSMP_H +# include +#endif + +#if HAVE_SYS_SYSINFO_H && HAVE_MACHINE_HAL_SYSINFO_H +# include +# include +#endif + +#if HAVE_SYS_TABLE_H +# include +#endif + +#include + +#if HAVE_SYS_PARAM_H +# include +#endif + +#if HAVE_SYS_SYSCTL_H +# include +#endif + +#if HAVE_SYS_SYSTEMCFG_H +# include +#endif + +#ifdef _WIN32 +# define WIN32_LEAN_AND_MEAN +# include +/* MEMORYSTATUSEX is missing from older windows headers, so define + a local replacement. */ +typedef struct +{ + DWORD dwLength; + DWORD dwMemoryLoad; + DWORDLONG ullTotalPhys; + DWORDLONG ullAvailPhys; + DWORDLONG ullTotalPageFile; + DWORDLONG ullAvailPageFile; + DWORDLONG ullTotalVirtual; + DWORDLONG ullAvailVirtual; + DWORDLONG ullAvailExtendedVirtual; +} lMEMORYSTATUSEX; +typedef WINBOOL (WINAPI *PFN_MS_EX) (lMEMORYSTATUSEX*); +#endif + +#include "libiberty.h" + +/* Return the total amount of physical memory. */ +double +physmem_total () +{ +#if defined _SC_PHYS_PAGES && defined _SC_PAGESIZE + { /* This works on linux-gnu, solaris2 and cygwin. */ + double pages = sysconf (_SC_PHYS_PAGES); + double pagesize = sysconf (_SC_PAGESIZE); + if (0 <= pages && 0 <= pagesize) + return pages * pagesize; + } +#endif + +#if HAVE_PSTAT_GETSTATIC + { /* This works on hpux11. */ + struct pst_static pss; + if (0 <= pstat_getstatic (&pss, sizeof pss, 1, 0)) + { + double pages = pss.physical_memory; + double pagesize = pss.page_size; + if (0 <= pages && 0 <= pagesize) + return pages * pagesize; + } + } +#endif + +#if HAVE_SYSMP && defined MP_SAGET && defined MPSA_RMINFO && defined _SC_PAGESIZE + { /* This works on irix6. */ + struct rminfo realmem; + if (sysmp (MP_SAGET, MPSA_RMINFO, &realmem, sizeof realmem) == 0) + { + double pagesize = sysconf (_SC_PAGESIZE); + double pages = realmem.physmem; + if (0 <= pages && 0 <= pagesize) + return pages * pagesize; + } + } +#endif + +#if HAVE_GETSYSINFO && defined GSI_PHYSMEM + { /* This works on Tru64 UNIX V4/5. */ + int physmem; + + if (getsysinfo (GSI_PHYSMEM, (caddr_t) &physmem, sizeof (physmem), + NULL, NULL, NULL) == 1) + { + double kbytes = physmem; + + if (0 <= kbytes) + return kbytes * 1024.0; + } + } +#endif + +#if HAVE_SYSCTL && defined HW_PHYSMEM + { /* This works on *bsd and darwin. */ + unsigned int physmem; + size_t len = sizeof physmem; + static int mib[2] = { CTL_HW, HW_PHYSMEM }; + + if (sysctl (mib, ARRAY_SIZE (mib), &physmem, &len, NULL, 0) == 0 + && len == sizeof (physmem)) + return (double) physmem; + } +#endif + +#if HAVE__SYSTEM_CONFIGURATION + /* This works on AIX 4.3.3+. */ + return _system_configuration.physmem; +#endif + +#if defined _WIN32 + { /* this works on windows */ + PFN_MS_EX pfnex; + HMODULE h = GetModuleHandle ("kernel32.dll"); + + if (!h) + return 0.0; + + /* Use GlobalMemoryStatusEx if available. */ + if ((pfnex = (PFN_MS_EX) GetProcAddress (h, "GlobalMemoryStatusEx"))) + { + lMEMORYSTATUSEX lms_ex; + lms_ex.dwLength = sizeof lms_ex; + if (!pfnex (&lms_ex)) + return 0.0; + return (double) lms_ex.ullTotalPhys; + } + + /* Fall back to GlobalMemoryStatus which is always available. + but returns wrong results for physical memory > 4GB. */ + else + { + MEMORYSTATUS ms; + GlobalMemoryStatus (&ms); + return (double) ms.dwTotalPhys; + } + } +#endif + + /* Return 0 if we can't determine the value. */ + return 0; +} + +/* Return the amount of physical memory available. */ +double +physmem_available () +{ +#if defined _SC_AVPHYS_PAGES && defined _SC_PAGESIZE + { /* This works on linux-gnu, solaris2 and cygwin. */ + double pages = sysconf (_SC_AVPHYS_PAGES); + double pagesize = sysconf (_SC_PAGESIZE); + if (0 <= pages && 0 <= pagesize) + return pages * pagesize; + } +#endif + +#if HAVE_PSTAT_GETSTATIC && HAVE_PSTAT_GETDYNAMIC + { /* This works on hpux11. */ + struct pst_static pss; + struct pst_dynamic psd; + if (0 <= pstat_getstatic (&pss, sizeof pss, 1, 0) + && 0 <= pstat_getdynamic (&psd, sizeof psd, 1, 0)) + { + double pages = psd.psd_free; + double pagesize = pss.page_size; + if (0 <= pages && 0 <= pagesize) + return pages * pagesize; + } + } +#endif + +#if HAVE_SYSMP && defined MP_SAGET && defined MPSA_RMINFO && defined _SC_PAGESIZE + { /* This works on irix6. */ + struct rminfo realmem; + if (sysmp (MP_SAGET, MPSA_RMINFO, &realmem, sizeof realmem) == 0) + { + double pagesize = sysconf (_SC_PAGESIZE); + double pages = realmem.availrmem; + if (0 <= pages && 0 <= pagesize) + return pages * pagesize; + } + } +#endif + +#if HAVE_TABLE && defined TBL_VMSTATS + { /* This works on Tru64 UNIX V4/5. */ + struct tbl_vmstats vmstats; + + if (table (TBL_VMSTATS, 0, &vmstats, 1, sizeof (vmstats)) == 1) + { + double pages = vmstats.free_count; + double pagesize = vmstats.pagesize; + + if (0 <= pages && 0 <= pagesize) + return pages * pagesize; + } + } +#endif + +#if HAVE_SYSCTL && defined HW_USERMEM + { /* This works on *bsd and darwin. */ + unsigned int usermem; + size_t len = sizeof usermem; + static int mib[2] = { CTL_HW, HW_USERMEM }; + + if (sysctl (mib, ARRAY_SIZE (mib), &usermem, &len, NULL, 0) == 0 + && len == sizeof (usermem)) + return (double) usermem; + } +#endif + +#if defined _WIN32 + { /* this works on windows */ + PFN_MS_EX pfnex; + HMODULE h = GetModuleHandle ("kernel32.dll"); + + if (!h) + return 0.0; + + /* Use GlobalMemoryStatusEx if available. */ + if ((pfnex = (PFN_MS_EX) GetProcAddress (h, "GlobalMemoryStatusEx"))) + { + lMEMORYSTATUSEX lms_ex; + lms_ex.dwLength = sizeof lms_ex; + if (!pfnex (&lms_ex)) + return 0.0; + return (double) lms_ex.ullAvailPhys; + } + + /* Fall back to GlobalMemoryStatus which is always available. + but returns wrong results for physical memory > 4GB */ + else + { + MEMORYSTATUS ms; + GlobalMemoryStatus (&ms); + return (double) ms.dwAvailPhys; + } + } +#endif + + /* Guess 25% of physical memory. */ + return physmem_total () / 4; +} + + +#if DEBUG + +# include +# include + +int +main () +{ + printf ("%12.f %12.f\n", physmem_total (), physmem_available ()); + exit (0); +} + +#endif /* DEBUG */ + +/* +Local Variables: +compile-command: "gcc -DDEBUG -DHAVE_CONFIG_H -I.. -g -O -Wall -W physmem.c" +End: +*/ diff --git a/libiberty/snprintf.c b/libiberty/snprintf.c new file mode 100644 index 0000000..8916469 --- /dev/null +++ b/libiberty/snprintf.c @@ -0,0 +1,65 @@ +/* Implement the snprintf function. + Copyright (C) 2003 Free Software Foundation, Inc. + Written by Kaveh R. Ghazi . + +This file is part of the libiberty library. This library is free +software; you can redistribute it and/or modify it under the +terms of the GNU General Public License as published by the +Free Software Foundation; either version 2, or (at your option) +any later version. + +This library is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +As a special exception, if you link this library with files +compiled with a GNU compiler to produce an executable, this does not cause +the resulting executable to be covered by the GNU General Public License. +This exception does not however invalidate any other reasons why +the executable file might be covered by the GNU General Public License. */ + +/* + +@deftypefn Supplemental int snprintf (char *@var{buf}, size_t @var{n}, const char *@var{format}, ...) + +This function is similar to sprintf, but it will print at most @var{n} +characters. On error the return value is -1, otherwise it returns the +number of characters that would have been printed had @var{n} been +sufficiently large, regardless of the actual value of @var{n}. Note +some pre-C99 system libraries do not implement this correctly so users +cannot generally rely on the return value if the system version of +this function is used. + +@end deftypefn + +*/ + +#include "ansidecl.h" + +#ifdef ANSI_PROTOTYPES +#include +#include +#else +#include +#define size_t unsigned long +#endif + +int vsnprintf PARAMS ((char *, size_t, const char *, va_list)); + +int +snprintf VPARAMS ((char *s, size_t n, const char *format, ...)) +{ + int result; + VA_OPEN (ap, format); + VA_FIXEDARG (ap, char *, s); + VA_FIXEDARG (ap, size_t, n); + VA_FIXEDARG (ap, const char *, format); + result = vsnprintf (s, n, format, ap); + VA_CLOSE (ap); + return result; +} diff --git a/libiberty/stpcpy.c b/libiberty/stpcpy.c new file mode 100644 index 0000000..a589642 --- /dev/null +++ b/libiberty/stpcpy.c @@ -0,0 +1,49 @@ +/* Implement the stpcpy function. + Copyright (C) 2003 Free Software Foundation, Inc. + Written by Kaveh R. Ghazi . + +This file is part of the libiberty library. +Libiberty is free software; you can redistribute it and/or +modify it under the terms of the GNU Library General Public +License as published by the Free Software Foundation; either +version 2 of the License, or (at your option) any later version. + +Libiberty is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +Library General Public License for more details. + +You should have received a copy of the GNU Library General Public +License along with libiberty; see the file COPYING.LIB. If +not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* + +@deftypefn Supplemental char* stpcpy (char *@var{dst}, const char *@var{src}) + +Copies the string @var{src} into @var{dst}. Returns a pointer to +@var{dst} + strlen(@var{src}). + +@end deftypefn + +*/ + +#include +#ifdef ANSI_PROTOTYPES +#include +#else +#define size_t unsigned long +#endif + +extern size_t strlen PARAMS ((const char *)); +extern PTR memcpy PARAMS ((PTR, const PTR, size_t)); + +char * +stpcpy (dst, src) + char *dst; + const char *src; +{ + const size_t len = strlen (src); + return (char *) memcpy (dst, src, len + 1) + len; +} diff --git a/libiberty/stpncpy.c b/libiberty/stpncpy.c new file mode 100644 index 0000000..cb67b4d --- /dev/null +++ b/libiberty/stpncpy.c @@ -0,0 +1,54 @@ +/* Implement the stpncpy function. + Copyright (C) 2003 Free Software Foundation, Inc. + Written by Kaveh R. Ghazi . + +This file is part of the libiberty library. +Libiberty is free software; you can redistribute it and/or +modify it under the terms of the GNU Library General Public +License as published by the Free Software Foundation; either +version 2 of the License, or (at your option) any later version. + +Libiberty is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +Library General Public License for more details. + +You should have received a copy of the GNU Library General Public +License along with libiberty; see the file COPYING.LIB. If +not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* + +@deftypefn Supplemental char* stpncpy (char *@var{dst}, const char *@var{src}, size_t @var{len}) + +Copies the string @var{src} into @var{dst}, copying exactly @var{len} +and padding with zeros if necessary. If @var{len} < strlen(@var{src}) +then return @var{dst} + @var{len}, otherwise returns @var{dst} + +strlen(@var{src}). + +@end deftypefn + +*/ + +#include +#ifdef ANSI_PROTOTYPES +#include +#else +#define size_t unsigned long +#endif + +extern size_t strlen PARAMS ((const char *)); +extern char *strncpy PARAMS ((char *, const char *, size_t)); + +char * +stpncpy (dst, src, len) + char *dst; + const char *src; + size_t len; +{ + size_t n = strlen (src); + if (n > len) + n = len; + return strncpy (dst, src, len) + n; +} diff --git a/libiberty/vsnprintf.c b/libiberty/vsnprintf.c new file mode 100644 index 0000000..fd3dd18 --- /dev/null +++ b/libiberty/vsnprintf.c @@ -0,0 +1,153 @@ +/* Implement the vsnprintf function. + Copyright (C) 2003 Free Software Foundation, Inc. + Written by Kaveh R. Ghazi . + +This file is part of the libiberty library. This library is free +software; you can redistribute it and/or modify it under the +terms of the GNU General Public License as published by the +Free Software Foundation; either version 2, or (at your option) +any later version. + +This library is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +As a special exception, if you link this library with files +compiled with a GNU compiler to produce an executable, this does not cause +the resulting executable to be covered by the GNU General Public License. +This exception does not however invalidate any other reasons why +the executable file might be covered by the GNU General Public License. */ + +/* + +@deftypefn Supplemental int vsnprintf (char *@var{buf}, size_t @var{n}, const char *@var{format}, va_list @var{ap}) + +This function is similar to vsprintf, but it will print at most +@var{n} characters. On error the return value is -1, otherwise it +returns the number of characters that would have been printed had +@var{n} been sufficiently large, regardless of the actual value of +@var{n}. Note some pre-C99 system libraries do not implement this +correctly so users cannot generally rely on the return value if the +system version of this function is used. + +@end deftypefn + +*/ + +#include "config.h" +#include "ansidecl.h" + +#ifdef ANSI_PROTOTYPES +#include +#else +#include +#endif +#ifdef HAVE_STRING_H +#include +#endif +#ifdef HAVE_STDLIB_H +#include +#endif + +#include "libiberty.h" + +/* This implementation relies on a working vasprintf. */ +int +vsnprintf (s, n, format, ap) + char * s; + size_t n; + const char *format; + va_list ap; +{ + char *buf = 0; + int result = vasprintf (&buf, format, ap); + + if (!buf) + return -1; + if (result < 0) + { + free (buf); + return -1; + } + + result = strlen (buf); + if (n > 0) + { + if ((long) n > result) + memcpy (s, buf, result+1); + else + { + memcpy (s, buf, n-1); + s[n - 1] = 0; + } + } + free (buf); + return result; +} + +#ifdef TEST +/* Set the buffer to a known state. */ +#define CLEAR(BUF) do { memset ((BUF), 'X', sizeof (BUF)); (BUF)[14] = '\0'; } while (0) +/* For assertions. */ +#define VERIFY(P) do { if (!(P)) abort(); } while (0) + +static int ATTRIBUTE_PRINTF_3 +checkit VPARAMS ((char *s, size_t n, const char *format, ...)) +{ + int result; + VA_OPEN (ap, format); + VA_FIXEDARG (ap, char *, s); + VA_FIXEDARG (ap, size_t, n); + VA_FIXEDARG (ap, const char *, format); + result = vsnprintf (s, n, format, ap); + VA_CLOSE (ap); + return result; +} + +extern int main PARAMS ((void)); +int +main () +{ + char buf[128]; + int status; + + CLEAR (buf); + status = checkit (buf, 10, "%s:%d", "foobar", 9); + VERIFY (status==8 && memcmp (buf, "foobar:9\0XXXXX\0", 15) == 0); + + CLEAR (buf); + status = checkit (buf, 9, "%s:%d", "foobar", 9); + VERIFY (status==8 && memcmp (buf, "foobar:9\0XXXXX\0", 15) == 0); + + CLEAR (buf); + status = checkit (buf, 8, "%s:%d", "foobar", 9); + VERIFY (status==8 && memcmp (buf, "foobar:\0XXXXXX\0", 15) == 0); + + CLEAR (buf); + status = checkit (buf, 7, "%s:%d", "foobar", 9); + VERIFY (status==8 && memcmp (buf, "foobar\0XXXXXXX\0", 15) == 0); + + CLEAR (buf); + status = checkit (buf, 6, "%s:%d", "foobar", 9); + VERIFY (status==8 && memcmp (buf, "fooba\0XXXXXXXX\0", 15) == 0); + + CLEAR (buf); + status = checkit (buf, 2, "%s:%d", "foobar", 9); + VERIFY (status==8 && memcmp (buf, "f\0XXXXXXXXXXXX\0", 15) == 0); + + CLEAR (buf); + status = checkit (buf, 1, "%s:%d", "foobar", 9); + VERIFY (status==8 && memcmp (buf, "\0XXXXXXXXXXXXX\0", 15) == 0); + + CLEAR (buf); + status = checkit (buf, 0, "%s:%d", "foobar", 9); + VERIFY (status==8 && memcmp (buf, "XXXXXXXXXXXXXX\0", 15) == 0); + + return 0; +} +#endif /* TEST */ diff --git a/opcodes/dis-init.c b/opcodes/dis-init.c new file mode 100644 index 0000000..35a5ee7 --- /dev/null +++ b/opcodes/dis-init.c @@ -0,0 +1,43 @@ +/* Initialize "struct disassemble_info". + + Copyright 2003 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA + 02111-1307, USA. */ + +#include "sysdep.h" +#include "dis-asm.h" +#include "bfd.h" + +void +init_disassemble_info (struct disassemble_info *info, void *stream, + fprintf_ftype fprintf_func) +{ + memset (info, 0, sizeof (*info)); + + info->flavour = bfd_target_unknown_flavour; + info->arch = bfd_arch_unknown; + info->endian = BFD_ENDIAN_UNKNOWN; + info->octets_per_byte = 1; + info->fprintf_func = fprintf_func; + info->stream = stream; + info->read_memory_func = buffer_read_memory; + info->memory_error_func = perror_memory; + info->print_address_func = generic_print_address; + info->symbol_at_address_func = generic_symbol_at_address; + info->symbol_is_valid = generic_symbol_is_valid; + info->display_endian = BFD_ENDIAN_UNKNOWN; +} + diff --git a/opcodes/iq2000-asm.c b/opcodes/iq2000-asm.c new file mode 100644 index 0000000..62d03f8 --- /dev/null +++ b/opcodes/iq2000-asm.c @@ -0,0 +1,883 @@ +/* Assembler interface for targets using CGEN. -*- C -*- + CGEN: Cpu tools GENerator + +THIS FILE IS MACHINE GENERATED WITH CGEN. +- the resultant file is machine generated, cgen-asm.in isn't + +Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* ??? Eventually more and more of this stuff can go to cpu-independent files. + Keep that in mind. */ + +#include "sysdep.h" +#include +#include "ansidecl.h" +#include "bfd.h" +#include "symcat.h" +#include "iq2000-desc.h" +#include "iq2000-opc.h" +#include "opintl.h" +#include "xregex.h" +#include "libiberty.h" +#include "safe-ctype.h" + +#undef min +#define min(a,b) ((a) < (b) ? (a) : (b)) +#undef max +#define max(a,b) ((a) > (b) ? (a) : (b)) + +static const char * parse_insn_normal + (CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *); + +/* -- assembler routines inserted here. */ + +/* -- asm.c */ +static const char * parse_mimm PARAMS ((CGEN_CPU_DESC, const char **, int, long *)); +static const char * parse_imm PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *)); +static const char * parse_hi16 PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *)); +static const char * parse_lo16 PARAMS ((CGEN_CPU_DESC, const char **, int, long *)); + +/* Special check to ensure that instruction exists for given machine */ +int +iq2000_cgen_insn_supported (cd, insn) + CGEN_CPU_DESC cd; + CGEN_INSN *insn; +{ + int machs = cd->machs; + + return ((CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_MACH) & machs) != 0); +} + +static int iq2000_cgen_isa_register (strp) + const char **strp; +{ + int len; + int ch1, ch2; + if (**strp == 'r' || **strp == 'R') + { + len = strlen (*strp); + if (len == 2) + { + ch1 = (*strp)[1]; + if ('0' <= ch1 && ch1 <= '9') + return 1; + } + else if (len == 3) + { + ch1 = (*strp)[1]; + ch2 = (*strp)[2]; + if (('1' <= ch1 && ch1 <= '2') && ('0' <= ch2 && ch2 <= '9')) + return 1; + if ('3' == ch1 && (ch2 == '0' || ch2 == '1')) + return 1; + } + } + if (**strp == '%' && tolower((*strp)[1]) != 'l' && tolower((*strp)[1]) != 'h') + return 1; + return 0; +} + +/* Handle negated literal. */ + +static const char * +parse_mimm (cd, strp, opindex, valuep) + CGEN_CPU_DESC cd; + const char **strp; + int opindex; + long *valuep; +{ + const char *errmsg; + long value; + + /* Verify this isn't a register */ + if (iq2000_cgen_isa_register (strp)) + errmsg = _("immediate value cannot be register"); + else + { + long value; + + errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value); + if (errmsg == NULL) + { + long x = (-value) & 0xFFFF0000; + if (x != 0 && x != 0xFFFF0000) + errmsg = _("immediate value out of range"); + else + *valuep = (-value & 0xFFFF); + } + } + return errmsg; +} + +/* Handle signed/unsigned literal. */ + +static const char * +parse_imm (cd, strp, opindex, valuep) + CGEN_CPU_DESC cd; + const char **strp; + int opindex; + unsigned long *valuep; +{ + const char *errmsg; + long value; + + if (iq2000_cgen_isa_register (strp)) + errmsg = _("immediate value cannot be register"); + else + { + long value; + + errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value); + if (errmsg == NULL) + { + long x = value & 0xFFFF0000; + if (x != 0 && x != 0xFFFF0000) + errmsg = _("immediate value out of range"); + else + *valuep = (value & 0xFFFF); + } + } + return errmsg; +} + +/* Handle iq10 21-bit jmp offset. */ + +static const char * +parse_jtargq10 (cd, strp, opindex, reloc, type_addr, valuep) + CGEN_CPU_DESC cd; + const char **strp; + int opindex; + int reloc; + enum cgen_parse_operand_result *type_addr; + unsigned long *valuep; +{ + const char *errmsg; + bfd_vma value; + enum cgen_parse_operand_result result_type = CGEN_PARSE_OPERAND_RESULT_NUMBER; + + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_IQ2000_OFFSET_21, + &result_type, &value); + if (errmsg == NULL && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) + { + /* check value is within 23-bits (remembering that 2-bit shift right will occur) */ + if (value > 0x7fffff) + return _("21-bit offset out of range"); + } + *valuep = (value & 0x7FFFFF); + return errmsg; +} + +/* Handle high(). */ + +static const char * +parse_hi16 (cd, strp, opindex, valuep) + CGEN_CPU_DESC cd; + const char **strp; + int opindex; + unsigned long *valuep; +{ + if (strncasecmp (*strp, "%hi(", 4) == 0) + { + enum cgen_parse_operand_result result_type; + bfd_vma value; + const char *errmsg; + + *strp += 4; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_HI16, + &result_type, &value); + if (**strp != ')') + return _("missing `)'"); + + ++*strp; + if (errmsg == NULL + && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) + { + /* if value has top-bit of %lo on, then it will + sign-propagate and so we compensate by adding + 1 to the resultant %hi value */ + if (value & 0x8000) + value += 0x10000; + value >>= 16; + } + *valuep = value; + + return errmsg; + } + + /* we add %uhi in case a user just wants the high 16-bits or is using + an insn like ori for %lo which does not sign-propagate */ + if (strncasecmp (*strp, "%uhi(", 5) == 0) + { + enum cgen_parse_operand_result result_type; + bfd_vma value; + const char *errmsg; + + *strp += 5; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_IQ2000_UHI16, + &result_type, &value); + if (**strp != ')') + return _("missing `)'"); + + ++*strp; + if (errmsg == NULL + && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) + { + value >>= 16; + } + *valuep = value; + + return errmsg; + } + + return parse_imm (cd, strp, opindex, valuep); +} + +/* Handle %lo in a signed context. + The signedness of the value doesn't matter to %lo(), but this also + handles the case where %lo() isn't present. */ + +static const char * +parse_lo16 (cd, strp, opindex, valuep) + CGEN_CPU_DESC cd; + const char **strp; + int opindex; + long *valuep; +{ + if (strncasecmp (*strp, "%lo(", 4) == 0) + { + const char *errmsg; + enum cgen_parse_operand_result result_type; + bfd_vma value; + + *strp += 4; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_LO16, + &result_type, &value); + if (**strp != ')') + return _("missing `)'"); + ++*strp; + if (errmsg == NULL + && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) + value &= 0xffff; + *valuep = value; + return errmsg; + } + + return parse_imm (cd, strp, opindex, valuep); +} + +/* Handle %lo in a negated signed context. + The signedness of the value doesn't matter to %lo(), but this also + handles the case where %lo() isn't present. */ + +static const char * +parse_mlo16 (cd, strp, opindex, valuep) + CGEN_CPU_DESC cd; + const char **strp; + int opindex; + long *valuep; +{ + if (strncasecmp (*strp, "%lo(", 4) == 0) + { + const char *errmsg; + enum cgen_parse_operand_result result_type; + bfd_vma value; + + *strp += 4; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_LO16, + &result_type, &value); + if (**strp != ')') + return _("missing `)'"); + ++*strp; + if (errmsg == NULL + && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) + value = (-value) & 0xffff; + *valuep = value; + return errmsg; + } + + return parse_mimm (cd, strp, opindex, valuep); +} + +/* -- */ + +const char * iq2000_cgen_parse_operand + PARAMS ((CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *)); + +/* Main entry point for operand parsing. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `parse_insn_normal', but keeping it + separate makes clear the interface between `parse_insn_normal' and each of + the handlers. */ + +const char * +iq2000_cgen_parse_operand (cd, opindex, strp, fields) + CGEN_CPU_DESC cd; + int opindex; + const char ** strp; + CGEN_FIELDS * fields; +{ + const char * errmsg = NULL; + /* Used by scalar operands that still need to be parsed. */ + long junk ATTRIBUTE_UNUSED; + + switch (opindex) + { + case IQ2000_OPERAND_BASE : + errmsg = cgen_parse_keyword (cd, strp, & iq2000_cgen_opval_gr_names, & fields->f_rs); + break; + case IQ2000_OPERAND_BASEOFF : + { + bfd_vma value; + errmsg = cgen_parse_address (cd, strp, IQ2000_OPERAND_BASEOFF, 0, NULL, & value); + fields->f_imm = value; + } + break; + case IQ2000_OPERAND_BITNUM : + errmsg = cgen_parse_unsigned_integer (cd, strp, IQ2000_OPERAND_BITNUM, &fields->f_rt); + break; + case IQ2000_OPERAND_BYTECOUNT : + errmsg = cgen_parse_unsigned_integer (cd, strp, IQ2000_OPERAND_BYTECOUNT, &fields->f_bytecount); + break; + case IQ2000_OPERAND_CAM_Y : + errmsg = cgen_parse_unsigned_integer (cd, strp, IQ2000_OPERAND_CAM_Y, &fields->f_cam_y); + break; + case IQ2000_OPERAND_CAM_Z : + errmsg = cgen_parse_unsigned_integer (cd, strp, IQ2000_OPERAND_CAM_Z, &fields->f_cam_z); + break; + case IQ2000_OPERAND_CM_3FUNC : + errmsg = cgen_parse_unsigned_integer (cd, strp, IQ2000_OPERAND_CM_3FUNC, &fields->f_cm_3func); + break; + case IQ2000_OPERAND_CM_3Z : + errmsg = cgen_parse_unsigned_integer (cd, strp, IQ2000_OPERAND_CM_3Z, &fields->f_cm_3z); + break; + case IQ2000_OPERAND_CM_4FUNC : + errmsg = cgen_parse_unsigned_integer (cd, strp, IQ2000_OPERAND_CM_4FUNC, &fields->f_cm_4func); + break; + case IQ2000_OPERAND_CM_4Z : + errmsg = cgen_parse_unsigned_integer (cd, strp, IQ2000_OPERAND_CM_4Z, &fields->f_cm_4z); + break; + case IQ2000_OPERAND_COUNT : + errmsg = cgen_parse_unsigned_integer (cd, strp, IQ2000_OPERAND_COUNT, &fields->f_count); + break; + case IQ2000_OPERAND_EXECODE : + errmsg = cgen_parse_unsigned_integer (cd, strp, IQ2000_OPERAND_EXECODE, &fields->f_excode); + break; + case IQ2000_OPERAND_F_INDEX : + errmsg = cgen_parse_unsigned_integer (cd, strp, IQ2000_OPERAND_F_INDEX, &fields->f_index); + break; + case IQ2000_OPERAND_HI16 : + errmsg = parse_hi16 (cd, strp, IQ2000_OPERAND_HI16, &fields->f_imm); + break; + case IQ2000_OPERAND_IMM : + errmsg = parse_imm (cd, strp, IQ2000_OPERAND_IMM, &fields->f_imm); + break; + case IQ2000_OPERAND_JMPTARG : + { + bfd_vma value; + errmsg = cgen_parse_address (cd, strp, IQ2000_OPERAND_JMPTARG, 0, NULL, & value); + fields->f_jtarg = value; + } + break; + case IQ2000_OPERAND_JMPTARGQ10 : + { + bfd_vma value; + errmsg = parse_jtargq10 (cd, strp, IQ2000_OPERAND_JMPTARGQ10, 0, NULL, & value); + fields->f_jtargq10 = value; + } + break; + case IQ2000_OPERAND_LO16 : + errmsg = parse_lo16 (cd, strp, IQ2000_OPERAND_LO16, &fields->f_imm); + break; + case IQ2000_OPERAND_MASK : + errmsg = cgen_parse_unsigned_integer (cd, strp, IQ2000_OPERAND_MASK, &fields->f_mask); + break; + case IQ2000_OPERAND_MASKL : + errmsg = cgen_parse_unsigned_integer (cd, strp, IQ2000_OPERAND_MASKL, &fields->f_maskl); + break; + case IQ2000_OPERAND_MASKQ10 : + errmsg = cgen_parse_unsigned_integer (cd, strp, IQ2000_OPERAND_MASKQ10, &fields->f_maskq10); + break; + case IQ2000_OPERAND_MASKR : + errmsg = cgen_parse_unsigned_integer (cd, strp, IQ2000_OPERAND_MASKR, &fields->f_rs); + break; + case IQ2000_OPERAND_MLO16 : + errmsg = parse_mlo16 (cd, strp, IQ2000_OPERAND_MLO16, &fields->f_imm); + break; + case IQ2000_OPERAND_OFFSET : + { + bfd_vma value; + errmsg = cgen_parse_address (cd, strp, IQ2000_OPERAND_OFFSET, 0, NULL, & value); + fields->f_offset = value; + } + break; + case IQ2000_OPERAND_RD : + errmsg = cgen_parse_keyword (cd, strp, & iq2000_cgen_opval_gr_names, & fields->f_rd); + break; + case IQ2000_OPERAND_RD_RS : + errmsg = cgen_parse_keyword (cd, strp, & iq2000_cgen_opval_gr_names, & fields->f_rd_rs); + break; + case IQ2000_OPERAND_RD_RT : + errmsg = cgen_parse_keyword (cd, strp, & iq2000_cgen_opval_gr_names, & fields->f_rd_rt); + break; + case IQ2000_OPERAND_RS : + errmsg = cgen_parse_keyword (cd, strp, & iq2000_cgen_opval_gr_names, & fields->f_rs); + break; + case IQ2000_OPERAND_RT : + errmsg = cgen_parse_keyword (cd, strp, & iq2000_cgen_opval_gr_names, & fields->f_rt); + break; + case IQ2000_OPERAND_RT_RS : + errmsg = cgen_parse_keyword (cd, strp, & iq2000_cgen_opval_gr_names, & fields->f_rt_rs); + break; + case IQ2000_OPERAND_SHAMT : + errmsg = cgen_parse_unsigned_integer (cd, strp, IQ2000_OPERAND_SHAMT, &fields->f_shamt); + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while parsing.\n"), opindex); + abort (); + } + + return errmsg; +} + +cgen_parse_fn * const iq2000_cgen_parse_handlers[] = +{ + parse_insn_normal, +}; + +void +iq2000_cgen_init_asm (cd) + CGEN_CPU_DESC cd; +{ + iq2000_cgen_init_opcode_table (cd); + iq2000_cgen_init_ibld_table (cd); + cd->parse_handlers = & iq2000_cgen_parse_handlers[0]; + cd->parse_operand = iq2000_cgen_parse_operand; +} + + + +/* Regex construction routine. + + This translates an opcode syntax string into a regex string, + by replacing any non-character syntax element (such as an + opcode) with the pattern '.*' + + It then compiles the regex and stores it in the opcode, for + later use by iq2000_cgen_assemble_insn + + Returns NULL for success, an error message for failure. */ + +char * +iq2000_cgen_build_insn_regex (CGEN_INSN *insn) +{ + CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn); + const char *mnem = CGEN_INSN_MNEMONIC (insn); + char rxbuf[CGEN_MAX_RX_ELEMENTS]; + char *rx = rxbuf; + const CGEN_SYNTAX_CHAR_TYPE *syn; + int reg_err; + + syn = CGEN_SYNTAX_STRING (CGEN_OPCODE_SYNTAX (opc)); + + /* Mnemonics come first in the syntax string. */ + if (! CGEN_SYNTAX_MNEMONIC_P (* syn)) + return _("missing mnemonic in syntax string"); + ++syn; + + /* Generate a case sensitive regular expression that emulates case + insensitive matching in the "C" locale. We cannot generate a case + insensitive regular expression because in Turkish locales, 'i' and 'I' + are not equal modulo case conversion. */ + + /* Copy the literal mnemonic out of the insn. */ + for (; *mnem; mnem++) + { + char c = *mnem; + + if (ISALPHA (c)) + { + *rx++ = '['; + *rx++ = TOLOWER (c); + *rx++ = TOUPPER (c); + *rx++ = ']'; + } + else + *rx++ = c; + } + + /* Copy any remaining literals from the syntax string into the rx. */ + for(; * syn != 0 && rx <= rxbuf + (CGEN_MAX_RX_ELEMENTS - 7 - 4); ++syn) + { + if (CGEN_SYNTAX_CHAR_P (* syn)) + { + char c = CGEN_SYNTAX_CHAR (* syn); + + switch (c) + { + /* Escape any regex metacharacters in the syntax. */ + case '.': case '[': case '\\': + case '*': case '^': case '$': + +#ifdef CGEN_ESCAPE_EXTENDED_REGEX + case '?': case '{': case '}': + case '(': case ')': case '*': + case '|': case '+': case ']': +#endif + *rx++ = '\\'; + *rx++ = c; + break; + + default: + if (ISALPHA (c)) + { + *rx++ = '['; + *rx++ = TOLOWER (c); + *rx++ = TOUPPER (c); + *rx++ = ']'; + } + else + *rx++ = c; + break; + } + } + else + { + /* Replace non-syntax fields with globs. */ + *rx++ = '.'; + *rx++ = '*'; + } + } + + /* Trailing whitespace ok. */ + * rx++ = '['; + * rx++ = ' '; + * rx++ = '\t'; + * rx++ = ']'; + * rx++ = '*'; + + /* But anchor it after that. */ + * rx++ = '$'; + * rx = '\0'; + + CGEN_INSN_RX (insn) = xmalloc (sizeof (regex_t)); + reg_err = regcomp ((regex_t *) CGEN_INSN_RX (insn), rxbuf, REG_NOSUB); + + if (reg_err == 0) + return NULL; + else + { + static char msg[80]; + + regerror (reg_err, (regex_t *) CGEN_INSN_RX (insn), msg, 80); + regfree ((regex_t *) CGEN_INSN_RX (insn)); + free (CGEN_INSN_RX (insn)); + (CGEN_INSN_RX (insn)) = NULL; + return msg; + } +} + + +/* Default insn parser. + + The syntax string is scanned and operands are parsed and stored in FIELDS. + Relocs are queued as we go via other callbacks. + + ??? Note that this is currently an all-or-nothing parser. If we fail to + parse the instruction, we return 0 and the caller will start over from + the beginning. Backtracking will be necessary in parsing subexpressions, + but that can be handled there. Not handling backtracking here may get + expensive in the case of the m68k. Deal with later. + + Returns NULL for success, an error message for failure. */ + +static const char * +parse_insn_normal (CGEN_CPU_DESC cd, + const CGEN_INSN *insn, + const char **strp, + CGEN_FIELDS *fields) +{ + /* ??? Runtime added insns not handled yet. */ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + const char *str = *strp; + const char *errmsg; + const char *p; + const CGEN_SYNTAX_CHAR_TYPE * syn; +#ifdef CGEN_MNEMONIC_OPERANDS + /* FIXME: wip */ + int past_opcode_p; +#endif + + /* For now we assume the mnemonic is first (there are no leading operands). + We can parse it without needing to set up operand parsing. + GAS's input scrubber will ensure mnemonics are lowercase, but we may + not be called from GAS. */ + p = CGEN_INSN_MNEMONIC (insn); + while (*p && TOLOWER (*p) == TOLOWER (*str)) + ++p, ++str; + + if (* p) + return _("unrecognized instruction"); + +#ifndef CGEN_MNEMONIC_OPERANDS + if (* str && ! ISSPACE (* str)) + return _("unrecognized instruction"); +#endif + + CGEN_INIT_PARSE (cd); + cgen_init_parse_operand (cd); +#ifdef CGEN_MNEMONIC_OPERANDS + past_opcode_p = 0; +#endif + + /* We don't check for (*str != '\0') here because we want to parse + any trailing fake arguments in the syntax string. */ + syn = CGEN_SYNTAX_STRING (syntax); + + /* Mnemonics come first for now, ensure valid string. */ + if (! CGEN_SYNTAX_MNEMONIC_P (* syn)) + abort (); + + ++syn; + + while (* syn != 0) + { + /* Non operand chars must match exactly. */ + if (CGEN_SYNTAX_CHAR_P (* syn)) + { + /* FIXME: While we allow for non-GAS callers above, we assume the + first char after the mnemonic part is a space. */ + /* FIXME: We also take inappropriate advantage of the fact that + GAS's input scrubber will remove extraneous blanks. */ + if (TOLOWER (*str) == TOLOWER (CGEN_SYNTAX_CHAR (* syn))) + { +#ifdef CGEN_MNEMONIC_OPERANDS + if (CGEN_SYNTAX_CHAR(* syn) == ' ') + past_opcode_p = 1; +#endif + ++ syn; + ++ str; + } + else if (*str) + { + /* Syntax char didn't match. Can't be this insn. */ + static char msg [80]; + + /* xgettext:c-format */ + sprintf (msg, _("syntax error (expected char `%c', found `%c')"), + CGEN_SYNTAX_CHAR(*syn), *str); + return msg; + } + else + { + /* Ran out of input. */ + static char msg [80]; + + /* xgettext:c-format */ + sprintf (msg, _("syntax error (expected char `%c', found end of instruction)"), + CGEN_SYNTAX_CHAR(*syn)); + return msg; + } + continue; + } + + /* We have an operand of some sort. */ + errmsg = cd->parse_operand (cd, CGEN_SYNTAX_FIELD (*syn), + &str, fields); + if (errmsg) + return errmsg; + + /* Done with this operand, continue with next one. */ + ++ syn; + } + + /* If we're at the end of the syntax string, we're done. */ + if (* syn == 0) + { + /* FIXME: For the moment we assume a valid `str' can only contain + blanks now. IE: We needn't try again with a longer version of + the insn and it is assumed that longer versions of insns appear + before shorter ones (eg: lsr r2,r3,1 vs lsr r2,r3). */ + while (ISSPACE (* str)) + ++ str; + + if (* str != '\0') + return _("junk at end of line"); /* FIXME: would like to include `str' */ + + return NULL; + } + + /* We couldn't parse it. */ + return _("unrecognized instruction"); +} + +/* Main entry point. + This routine is called for each instruction to be assembled. + STR points to the insn to be assembled. + We assume all necessary tables have been initialized. + The assembled instruction, less any fixups, is stored in BUF. + Remember that if CGEN_INT_INSN_P then BUF is an int and thus the value + still needs to be converted to target byte order, otherwise BUF is an array + of bytes in target byte order. + The result is a pointer to the insn's entry in the opcode table, + or NULL if an error occured (an error message will have already been + printed). + + Note that when processing (non-alias) macro-insns, + this function recurses. + + ??? It's possible to make this cpu-independent. + One would have to deal with a few minor things. + At this point in time doing so would be more of a curiosity than useful + [for example this file isn't _that_ big], but keeping the possibility in + mind helps keep the design clean. */ + +const CGEN_INSN * +iq2000_cgen_assemble_insn (CGEN_CPU_DESC cd, + const char *str, + CGEN_FIELDS *fields, + CGEN_INSN_BYTES_PTR buf, + char **errmsg) +{ + const char *start; + CGEN_INSN_LIST *ilist; + const char *parse_errmsg = NULL; + const char *insert_errmsg = NULL; + int recognized_mnemonic = 0; + + /* Skip leading white space. */ + while (ISSPACE (* str)) + ++ str; + + /* The instructions are stored in hashed lists. + Get the first in the list. */ + ilist = CGEN_ASM_LOOKUP_INSN (cd, str); + + /* Keep looking until we find a match. */ + start = str; + for ( ; ilist != NULL ; ilist = CGEN_ASM_NEXT_INSN (ilist)) + { + const CGEN_INSN *insn = ilist->insn; + recognized_mnemonic = 1; + +#ifdef CGEN_VALIDATE_INSN_SUPPORTED + /* Not usually needed as unsupported opcodes + shouldn't be in the hash lists. */ + /* Is this insn supported by the selected cpu? */ + if (! iq2000_cgen_insn_supported (cd, insn)) + continue; +#endif + /* If the RELAXED attribute is set, this is an insn that shouldn't be + chosen immediately. Instead, it is used during assembler/linker + relaxation if possible. */ + if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAXED) != 0) + continue; + + str = start; + + /* Skip this insn if str doesn't look right lexically. */ + if (CGEN_INSN_RX (insn) != NULL && + regexec ((regex_t *) CGEN_INSN_RX (insn), str, 0, NULL, 0) == REG_NOMATCH) + continue; + + /* Allow parse/insert handlers to obtain length of insn. */ + CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); + + parse_errmsg = CGEN_PARSE_FN (cd, insn) (cd, insn, & str, fields); + if (parse_errmsg != NULL) + continue; + + /* ??? 0 is passed for `pc'. */ + insert_errmsg = CGEN_INSERT_FN (cd, insn) (cd, insn, fields, buf, + (bfd_vma) 0); + if (insert_errmsg != NULL) + continue; + + /* It is up to the caller to actually output the insn and any + queued relocs. */ + return insn; + } + + { + static char errbuf[150]; +#ifdef CGEN_VERBOSE_ASSEMBLER_ERRORS + const char *tmp_errmsg; + + /* If requesting verbose error messages, use insert_errmsg. + Failing that, use parse_errmsg. */ + tmp_errmsg = (insert_errmsg ? insert_errmsg : + parse_errmsg ? parse_errmsg : + recognized_mnemonic ? + _("unrecognized form of instruction") : + _("unrecognized instruction")); + + if (strlen (start) > 50) + /* xgettext:c-format */ + sprintf (errbuf, "%s `%.50s...'", tmp_errmsg, start); + else + /* xgettext:c-format */ + sprintf (errbuf, "%s `%.50s'", tmp_errmsg, start); +#else + if (strlen (start) > 50) + /* xgettext:c-format */ + sprintf (errbuf, _("bad instruction `%.50s...'"), start); + else + /* xgettext:c-format */ + sprintf (errbuf, _("bad instruction `%.50s'"), start); +#endif + + *errmsg = errbuf; + return NULL; + } +} + +#if 0 /* This calls back to GAS which we can't do without care. */ + +/* Record each member of OPVALS in the assembler's symbol table. + This lets GAS parse registers for us. + ??? Interesting idea but not currently used. */ + +/* Record each member of OPVALS in the assembler's symbol table. + FIXME: Not currently used. */ + +void +iq2000_cgen_asm_hash_keywords (CGEN_CPU_DESC cd, CGEN_KEYWORD *opvals) +{ + CGEN_KEYWORD_SEARCH search = cgen_keyword_search_init (opvals, NULL); + const CGEN_KEYWORD_ENTRY * ke; + + while ((ke = cgen_keyword_search_next (& search)) != NULL) + { +#if 0 /* Unnecessary, should be done in the search routine. */ + if (! iq2000_cgen_opval_supported (ke)) + continue; +#endif + cgen_asm_record_register (cd, ke->name, ke->value); + } +} + +#endif /* 0 */ diff --git a/opcodes/iq2000-desc.c b/opcodes/iq2000-desc.c new file mode 100644 index 0000000..6c7f3b0 --- /dev/null +++ b/opcodes/iq2000-desc.c @@ -0,0 +1,2228 @@ +/* CPU data for iq2000. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +*/ + +#include "sysdep.h" +#include +#include +#include "ansidecl.h" +#include "bfd.h" +#include "symcat.h" +#include "iq2000-desc.h" +#include "iq2000-opc.h" +#include "opintl.h" +#include "libiberty.h" +#include "xregex.h" + +/* Attributes. */ + +static const CGEN_ATTR_ENTRY bool_attr[] = +{ + { "#f", 0 }, + { "#t", 1 }, + { 0, 0 } +}; + +static const CGEN_ATTR_ENTRY MACH_attr[] = +{ + { "base", MACH_BASE }, + { "iq2000", MACH_IQ2000 }, + { "iq10", MACH_IQ10 }, + { "max", MACH_MAX }, + { 0, 0 } +}; + +static const CGEN_ATTR_ENTRY ISA_attr[] = +{ + { "iq2000", ISA_IQ2000 }, + { "max", ISA_MAX }, + { 0, 0 } +}; + +const CGEN_ATTR_TABLE iq2000_cgen_ifield_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, + { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, + { "RESERVED", &bool_attr[0], &bool_attr[0] }, + { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, + { "SIGNED", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +const CGEN_ATTR_TABLE iq2000_cgen_hardware_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] }, + { "PC", &bool_attr[0], &bool_attr[0] }, + { "PROFILE", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +const CGEN_ATTR_TABLE iq2000_cgen_operand_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, + { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, + { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, + { "SIGNED", &bool_attr[0], &bool_attr[0] }, + { "NEGATIVE", &bool_attr[0], &bool_attr[0] }, + { "RELAX", &bool_attr[0], &bool_attr[0] }, + { "SEM-ONLY", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +const CGEN_ATTR_TABLE iq2000_cgen_insn_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "ALIAS", &bool_attr[0], &bool_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] }, + { "COND-CTI", &bool_attr[0], &bool_attr[0] }, + { "SKIP-CTI", &bool_attr[0], &bool_attr[0] }, + { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] }, + { "RELAXABLE", &bool_attr[0], &bool_attr[0] }, + { "RELAXED", &bool_attr[0], &bool_attr[0] }, + { "NO-DIS", &bool_attr[0], &bool_attr[0] }, + { "PBB", &bool_attr[0], &bool_attr[0] }, + { "YIELD-INSN", &bool_attr[0], &bool_attr[0] }, + { "LOAD-DELAY", &bool_attr[0], &bool_attr[0] }, + { "EVEN-REG-NUM", &bool_attr[0], &bool_attr[0] }, + { "UNSUPPORTED", &bool_attr[0], &bool_attr[0] }, + { "USES-RD", &bool_attr[0], &bool_attr[0] }, + { "USES-RS", &bool_attr[0], &bool_attr[0] }, + { "USES-RT", &bool_attr[0], &bool_attr[0] }, + { "USES-R31", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +/* Instruction set variants. */ + +static const CGEN_ISA iq2000_cgen_isa_table[] = { + { "iq2000", 32, 32, 23, 32 }, + { 0, 0, 0, 0, 0 } +}; + +/* Machine variants. */ + +static const CGEN_MACH iq2000_cgen_mach_table[] = { + { "iq2000", "iq2000", MACH_IQ2000, 0 }, + { "iq10", "iq10", MACH_IQ10, 0 }, + { 0, 0, 0, 0 } +}; + +static CGEN_KEYWORD_ENTRY iq2000_cgen_opval_gr_names_entries[] = +{ + { "r0", 0, {0, {0}}, 0, 0 }, + { "%0", 0, {0, {0}}, 0, 0 }, + { "r1", 1, {0, {0}}, 0, 0 }, + { "%1", 1, {0, {0}}, 0, 0 }, + { "r2", 2, {0, {0}}, 0, 0 }, + { "%2", 2, {0, {0}}, 0, 0 }, + { "r3", 3, {0, {0}}, 0, 0 }, + { "%3", 3, {0, {0}}, 0, 0 }, + { "r4", 4, {0, {0}}, 0, 0 }, + { "%4", 4, {0, {0}}, 0, 0 }, + { "r5", 5, {0, {0}}, 0, 0 }, + { "%5", 5, {0, {0}}, 0, 0 }, + { "r6", 6, {0, {0}}, 0, 0 }, + { "%6", 6, {0, {0}}, 0, 0 }, + { "r7", 7, {0, {0}}, 0, 0 }, + { "%7", 7, {0, {0}}, 0, 0 }, + { "r8", 8, {0, {0}}, 0, 0 }, + { "%8", 8, {0, {0}}, 0, 0 }, + { "r9", 9, {0, {0}}, 0, 0 }, + { "%9", 9, {0, {0}}, 0, 0 }, + { "r10", 10, {0, {0}}, 0, 0 }, + { "%10", 10, {0, {0}}, 0, 0 }, + { "r11", 11, {0, {0}}, 0, 0 }, + { "%11", 11, {0, {0}}, 0, 0 }, + { "r12", 12, {0, {0}}, 0, 0 }, + { "%12", 12, {0, {0}}, 0, 0 }, + { "r13", 13, {0, {0}}, 0, 0 }, + { "%13", 13, {0, {0}}, 0, 0 }, + { "r14", 14, {0, {0}}, 0, 0 }, + { "%14", 14, {0, {0}}, 0, 0 }, + { "r15", 15, {0, {0}}, 0, 0 }, + { "%15", 15, {0, {0}}, 0, 0 }, + { "r16", 16, {0, {0}}, 0, 0 }, + { "%16", 16, {0, {0}}, 0, 0 }, + { "r17", 17, {0, {0}}, 0, 0 }, + { "%17", 17, {0, {0}}, 0, 0 }, + { "r18", 18, {0, {0}}, 0, 0 }, + { "%18", 18, {0, {0}}, 0, 0 }, + { "r19", 19, {0, {0}}, 0, 0 }, + { "%19", 19, {0, {0}}, 0, 0 }, + { "r20", 20, {0, {0}}, 0, 0 }, + { "%20", 20, {0, {0}}, 0, 0 }, + { "r21", 21, {0, {0}}, 0, 0 }, + { "%21", 21, {0, {0}}, 0, 0 }, + { "r22", 22, {0, {0}}, 0, 0 }, + { "%22", 22, {0, {0}}, 0, 0 }, + { "r23", 23, {0, {0}}, 0, 0 }, + { "%23", 23, {0, {0}}, 0, 0 }, + { "r24", 24, {0, {0}}, 0, 0 }, + { "%24", 24, {0, {0}}, 0, 0 }, + { "r25", 25, {0, {0}}, 0, 0 }, + { "%25", 25, {0, {0}}, 0, 0 }, + { "r26", 26, {0, {0}}, 0, 0 }, + { "%26", 26, {0, {0}}, 0, 0 }, + { "r27", 27, {0, {0}}, 0, 0 }, + { "%27", 27, {0, {0}}, 0, 0 }, + { "r28", 28, {0, {0}}, 0, 0 }, + { "%28", 28, {0, {0}}, 0, 0 }, + { "r29", 29, {0, {0}}, 0, 0 }, + { "%29", 29, {0, {0}}, 0, 0 }, + { "r30", 30, {0, {0}}, 0, 0 }, + { "%30", 30, {0, {0}}, 0, 0 }, + { "r31", 31, {0, {0}}, 0, 0 }, + { "%31", 31, {0, {0}}, 0, 0 } +}; + +CGEN_KEYWORD iq2000_cgen_opval_gr_names = +{ + & iq2000_cgen_opval_gr_names_entries[0], + 64, + 0, 0, 0, 0, "" +}; + + +/* The hardware table. */ + +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define A(a) (1 << CGEN_HW_##a) +#else +#define A(a) (1 << CGEN_HW_/**/a) +#endif + +const CGEN_HW_ENTRY iq2000_cgen_hw_table[] = +{ + { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { (1<name) + { + if (strcmp (name, table->bfd_name) == 0) + return table; + ++table; + } + abort (); +} + +/* Subroutine of iq2000_cgen_cpu_open to build the hardware table. */ + +static void +build_hw_table (cd) + CGEN_CPU_TABLE *cd; +{ + int i; + int machs = cd->machs; + const CGEN_HW_ENTRY *init = & iq2000_cgen_hw_table[0]; + /* MAX_HW is only an upper bound on the number of selected entries. + However each entry is indexed by it's enum so there can be holes in + the table. */ + const CGEN_HW_ENTRY **selected = + (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *)); + + cd->hw_table.init_entries = init; + cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY); + memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *)); + /* ??? For now we just use machs to determine which ones we want. */ + for (i = 0; init[i].name != NULL; ++i) + if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH) + & machs) + selected[init[i].type] = &init[i]; + cd->hw_table.entries = selected; + cd->hw_table.num_entries = MAX_HW; +} + +/* Subroutine of iq2000_cgen_cpu_open to build the hardware table. */ + +static void +build_ifield_table (cd) + CGEN_CPU_TABLE *cd; +{ + cd->ifld_table = & iq2000_cgen_ifld_table[0]; +} + +/* Subroutine of iq2000_cgen_cpu_open to build the hardware table. */ + +static void +build_operand_table (cd) + CGEN_CPU_TABLE *cd; +{ + int i; + int machs = cd->machs; + const CGEN_OPERAND *init = & iq2000_cgen_operand_table[0]; + /* MAX_OPERANDS is only an upper bound on the number of selected entries. + However each entry is indexed by it's enum so there can be holes in + the table. */ + const CGEN_OPERAND **selected = + (const CGEN_OPERAND **) xmalloc (MAX_OPERANDS * sizeof (CGEN_OPERAND *)); + + cd->operand_table.init_entries = init; + cd->operand_table.entry_size = sizeof (CGEN_OPERAND); + memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *)); + /* ??? For now we just use mach to determine which ones we want. */ + for (i = 0; init[i].name != NULL; ++i) + if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH) + & machs) + selected[init[i].type] = &init[i]; + cd->operand_table.entries = selected; + cd->operand_table.num_entries = MAX_OPERANDS; +} + +/* Subroutine of iq2000_cgen_cpu_open to build the hardware table. + ??? This could leave out insns not supported by the specified mach/isa, + but that would cause errors like "foo only supported by bar" to become + "unknown insn", so for now we include all insns and require the app to + do the checking later. + ??? On the other hand, parsing of such insns may require their hardware or + operand elements to be in the table [which they mightn't be]. */ + +static void +build_insn_table (cd) + CGEN_CPU_TABLE *cd; +{ + int i; + const CGEN_IBASE *ib = & iq2000_cgen_insn_table[0]; + CGEN_INSN *insns = (CGEN_INSN *) xmalloc (MAX_INSNS * sizeof (CGEN_INSN)); + + memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN)); + for (i = 0; i < MAX_INSNS; ++i) + insns[i].base = &ib[i]; + cd->insn_table.init_entries = insns; + cd->insn_table.entry_size = sizeof (CGEN_IBASE); + cd->insn_table.num_init_entries = MAX_INSNS; +} + +/* Subroutine of iq2000_cgen_cpu_open to rebuild the tables. */ + +static void +iq2000_cgen_rebuild_tables (cd) + CGEN_CPU_TABLE *cd; +{ + int i; + unsigned int isas = cd->isas; + unsigned int machs = cd->machs; + + cd->int_insn_p = CGEN_INT_INSN_P; + + /* Data derived from the isa spec. */ +#define UNSET (CGEN_SIZE_UNKNOWN + 1) + cd->default_insn_bitsize = UNSET; + cd->base_insn_bitsize = UNSET; + cd->min_insn_bitsize = 65535; /* some ridiculously big number */ + cd->max_insn_bitsize = 0; + for (i = 0; i < MAX_ISAS; ++i) + if (((1 << i) & isas) != 0) + { + const CGEN_ISA *isa = & iq2000_cgen_isa_table[i]; + + /* Default insn sizes of all selected isas must be + equal or we set the result to 0, meaning "unknown". */ + if (cd->default_insn_bitsize == UNSET) + cd->default_insn_bitsize = isa->default_insn_bitsize; + else if (isa->default_insn_bitsize == cd->default_insn_bitsize) + ; /* this is ok */ + else + cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN; + + /* Base insn sizes of all selected isas must be equal + or we set the result to 0, meaning "unknown". */ + if (cd->base_insn_bitsize == UNSET) + cd->base_insn_bitsize = isa->base_insn_bitsize; + else if (isa->base_insn_bitsize == cd->base_insn_bitsize) + ; /* this is ok */ + else + cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN; + + /* Set min,max insn sizes. */ + if (isa->min_insn_bitsize < cd->min_insn_bitsize) + cd->min_insn_bitsize = isa->min_insn_bitsize; + if (isa->max_insn_bitsize > cd->max_insn_bitsize) + cd->max_insn_bitsize = isa->max_insn_bitsize; + } + + /* Data derived from the mach spec. */ + for (i = 0; i < MAX_MACHS; ++i) + if (((1 << i) & machs) != 0) + { + const CGEN_MACH *mach = & iq2000_cgen_mach_table[i]; + + if (mach->insn_chunk_bitsize != 0) + { + if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize) + { + fprintf (stderr, "iq2000_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n", + cd->insn_chunk_bitsize, mach->insn_chunk_bitsize); + abort (); + } + + cd->insn_chunk_bitsize = mach->insn_chunk_bitsize; + } + } + + /* Determine which hw elements are used by MACH. */ + build_hw_table (cd); + + /* Build the ifield table. */ + build_ifield_table (cd); + + /* Determine which operands are used by MACH/ISA. */ + build_operand_table (cd); + + /* Build the instruction table. */ + build_insn_table (cd); +} + +/* Initialize a cpu table and return a descriptor. + It's much like opening a file, and must be the first function called. + The arguments are a set of (type/value) pairs, terminated with + CGEN_CPU_OPEN_END. + + Currently supported values: + CGEN_CPU_OPEN_ISAS: bitmap of values in enum isa_attr + CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr + CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name + CGEN_CPU_OPEN_ENDIAN: specify endian choice + CGEN_CPU_OPEN_END: terminates arguments + + ??? Simultaneous multiple isas might not make sense, but it's not (yet) + precluded. + + ??? We only support ISO C stdargs here, not K&R. + Laziness, plus experiment to see if anything requires K&R - eventually + K&R will no longer be supported - e.g. GDB is currently trying this. */ + +CGEN_CPU_DESC +iq2000_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) +{ + CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE)); + static int init_p; + unsigned int isas = 0; /* 0 = "unspecified" */ + unsigned int machs = 0; /* 0 = "unspecified" */ + enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN; + va_list ap; + + if (! init_p) + { + init_tables (); + init_p = 1; + } + + memset (cd, 0, sizeof (*cd)); + + va_start (ap, arg_type); + while (arg_type != CGEN_CPU_OPEN_END) + { + switch (arg_type) + { + case CGEN_CPU_OPEN_ISAS : + isas = va_arg (ap, unsigned int); + break; + case CGEN_CPU_OPEN_MACHS : + machs = va_arg (ap, unsigned int); + break; + case CGEN_CPU_OPEN_BFDMACH : + { + const char *name = va_arg (ap, const char *); + const CGEN_MACH *mach = + lookup_mach_via_bfd_name (iq2000_cgen_mach_table, name); + + machs |= 1 << mach->num; + break; + } + case CGEN_CPU_OPEN_ENDIAN : + endian = va_arg (ap, enum cgen_endian); + break; + default : + fprintf (stderr, "iq2000_cgen_cpu_open: unsupported argument `%d'\n", + arg_type); + abort (); /* ??? return NULL? */ + } + arg_type = va_arg (ap, enum cgen_cpu_open_arg); + } + va_end (ap); + + /* mach unspecified means "all" */ + if (machs == 0) + machs = (1 << MAX_MACHS) - 1; + /* base mach is always selected */ + machs |= 1; + /* isa unspecified means "all" */ + if (isas == 0) + isas = (1 << MAX_ISAS) - 1; + if (endian == CGEN_ENDIAN_UNKNOWN) + { + /* ??? If target has only one, could have a default. */ + fprintf (stderr, "iq2000_cgen_cpu_open: no endianness specified\n"); + abort (); + } + + cd->isas = isas; + cd->machs = machs; + cd->endian = endian; + /* FIXME: for the sparc case we can determine insn-endianness statically. + The worry here is where both data and insn endian can be independently + chosen, in which case this function will need another argument. + Actually, will want to allow for more arguments in the future anyway. */ + cd->insn_endian = endian; + + /* Table (re)builder. */ + cd->rebuild_tables = iq2000_cgen_rebuild_tables; + iq2000_cgen_rebuild_tables (cd); + + /* Default to not allowing signed overflow. */ + cd->signed_overflow_ok_p = 0; + + return (CGEN_CPU_DESC) cd; +} + +/* Cover fn to iq2000_cgen_cpu_open to handle the simple case of 1 isa, 1 mach. + MACH_NAME is the bfd name of the mach. */ + +CGEN_CPU_DESC +iq2000_cgen_cpu_open_1 (mach_name, endian) + const char *mach_name; + enum cgen_endian endian; +{ + return iq2000_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name, + CGEN_CPU_OPEN_ENDIAN, endian, + CGEN_CPU_OPEN_END); +} + +/* Close a cpu table. + ??? This can live in a machine independent file, but there's currently + no place to put this file (there's no libcgen). libopcodes is the wrong + place as some simulator ports use this but they don't use libopcodes. */ + +void +iq2000_cgen_cpu_close (cd) + CGEN_CPU_DESC cd; +{ + unsigned int i; + const CGEN_INSN *insns; + + if (cd->macro_insn_table.init_entries) + { + insns = cd->macro_insn_table.init_entries; + for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns) + { + if (CGEN_INSN_RX ((insns))) + regfree (CGEN_INSN_RX (insns)); + } + } + + if (cd->insn_table.init_entries) + { + insns = cd->insn_table.init_entries; + for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns) + { + if (CGEN_INSN_RX (insns)) + regfree (CGEN_INSN_RX (insns)); + } + } + + + + if (cd->macro_insn_table.init_entries) + free ((CGEN_INSN *) cd->macro_insn_table.init_entries); + + if (cd->insn_table.init_entries) + free ((CGEN_INSN *) cd->insn_table.init_entries); + + if (cd->hw_table.entries) + free ((CGEN_HW_ENTRY *) cd->hw_table.entries); + + if (cd->operand_table.entries) + free ((CGEN_HW_ENTRY *) cd->operand_table.entries); + + free (cd); +} + diff --git a/opcodes/iq2000-desc.h b/opcodes/iq2000-desc.h new file mode 100644 index 0000000..13b4f56 --- /dev/null +++ b/opcodes/iq2000-desc.h @@ -0,0 +1,302 @@ +/* CPU data header for iq2000. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +*/ + +#ifndef IQ2000_CPU_H +#define IQ2000_CPU_H + +#define CGEN_ARCH iq2000 + +/* Given symbol S, return iq2000_cgen_. */ +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define CGEN_SYM(s) iq2000##_cgen_##s +#else +#define CGEN_SYM(s) iq2000/**/_cgen_/**/s +#endif + + +/* Selected cpu families. */ +#define HAVE_CPU_IQ2000BF +#define HAVE_CPU_IQ10BF + +#define CGEN_INSN_LSB0_P 1 + +/* Minimum size of any insn (in bytes). */ +#define CGEN_MIN_INSN_SIZE 3 + +/* Maximum size of any insn (in bytes). */ +#define CGEN_MAX_INSN_SIZE 4 + +#define CGEN_INT_INSN_P 1 + +/* Maximum number of syntax elements in an instruction. */ +#define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 19 + +/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands. + e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands + we can't hash on everything up to the space. */ +#define CGEN_MNEMONIC_OPERANDS + +/* Maximum number of fields in an instruction. */ +#define CGEN_ACTUAL_MAX_IFMT_OPERANDS 8 + +/* Enums. */ + +/* Enum declaration for . */ +typedef enum gr_names { + H_GR_R0 = 0, H_GR__0 = 0, H_GR_R1 = 1, H_GR__1 = 1 + , H_GR_R2 = 2, H_GR__2 = 2, H_GR_R3 = 3, H_GR__3 = 3 + , H_GR_R4 = 4, H_GR__4 = 4, H_GR_R5 = 5, H_GR__5 = 5 + , H_GR_R6 = 6, H_GR__6 = 6, H_GR_R7 = 7, H_GR__7 = 7 + , H_GR_R8 = 8, H_GR__8 = 8, H_GR_R9 = 9, H_GR__9 = 9 + , H_GR_R10 = 10, H_GR__10 = 10, H_GR_R11 = 11, H_GR__11 = 11 + , H_GR_R12 = 12, H_GR__12 = 12, H_GR_R13 = 13, H_GR__13 = 13 + , H_GR_R14 = 14, H_GR__14 = 14, H_GR_R15 = 15, H_GR__15 = 15 + , H_GR_R16 = 16, H_GR__16 = 16, H_GR_R17 = 17, H_GR__17 = 17 + , H_GR_R18 = 18, H_GR__18 = 18, H_GR_R19 = 19, H_GR__19 = 19 + , H_GR_R20 = 20, H_GR__20 = 20, H_GR_R21 = 21, H_GR__21 = 21 + , H_GR_R22 = 22, H_GR__22 = 22, H_GR_R23 = 23, H_GR__23 = 23 + , H_GR_R24 = 24, H_GR__24 = 24, H_GR_R25 = 25, H_GR__25 = 25 + , H_GR_R26 = 26, H_GR__26 = 26, H_GR_R27 = 27, H_GR__27 = 27 + , H_GR_R28 = 28, H_GR__28 = 28, H_GR_R29 = 29, H_GR__29 = 29 + , H_GR_R30 = 30, H_GR__30 = 30, H_GR_R31 = 31, H_GR__31 = 31 +} GR_NAMES; + +/* Enum declaration for primary opcodes. */ +typedef enum opcodes { + OP_SPECIAL = 0, OP_REGIMM = 1, OP_J = 2, OP_JAL = 3 + , OP_BEQ = 4, OP_BNE = 5, OP_BLEZ = 6, OP_BGTZ = 7 + , OP_ADDI = 8, OP_ADDIU = 9, OP_SLTI = 10, OP_SLTIU = 11 + , OP_ANDI = 12, OP_ORI = 13, OP_XORI = 14, OP_LUI = 15 + , OP_COP0 = 16, OP_COP1 = 17, OP_COP2 = 18, OP_COP3 = 19 + , OP_BEQL = 20, OP_BNEL = 21, OP_BLEZL = 22, OP_BGTZL = 23 + , OP_BMB0 = 24, OP_BMB1 = 25, OP_BMB2 = 26, OP_BMB3 = 27 + , OP_BBI = 28, OP_BBV = 29, OP_BBIN = 30, OP_BBVN = 31 + , OP_LB = 32, OP_LH = 33, OP_LW = 35, OP_LBU = 36 + , OP_LHU = 37, OP_RAM = 39, OP_SB = 40, OP_SH = 41 + , OP_SW = 43, OP_ANDOI = 44, OP_BMB = 45, OP_ORUI = 47 + , OP_LDW = 48, OP_SDW = 56, OP_ANDOUI = 63 +} OPCODES; + +/* Enum declaration for iq10-only primary opcodes. */ +typedef enum q10_opcodes { + OP10_BMB = 6, OP10_ORUI = 15, OP10_BMBL = 22, OP10_ANDOUI = 47 + , OP10_BBIL = 60, OP10_BBVL = 61, OP10_BBINL = 62, OP10_BBVNL = 63 +} Q10_OPCODES; + +/* Enum declaration for branch sub-opcodes. */ +typedef enum regimm_functions { + FUNC_BLTZ = 0, FUNC_BGEZ = 1, FUNC_BLTZL = 2, FUNC_BGEZL = 3 + , FUNC_BLEZ = 4, FUNC_BGTZ = 5, FUNC_BLEZL = 6, FUNC_BGTZL = 7 + , FUNC_BRI = 8, FUNC_BRV = 9, FUNC_BCTX = 12, FUNC_BLTZAL = 16 + , FUNC_BGEZAL = 17, FUNC_BLTZALL = 18, FUNC_BGEZALL = 19, FUNC_BLEZAL = 20 + , FUNC_BGTZAL = 21, FUNC_BLEZALL = 22, FUNC_BGTZALL = 23 +} REGIMM_FUNCTIONS; + +/* Enum declaration for function sub-opcodes. */ +typedef enum functions { + FUNC_SLL = 0, FUNC_SLMV = 1, FUNC_SRL = 2, FUNC_SRA = 3 + , FUNC_SLLV = 4, FUNC_SRMV = 5, FUNC_SRLV = 6, FUNC_SRAV = 7 + , FUNC_JR = 8, FUNC_JALR = 9, FUNC_JCR = 10, FUNC_SYSCALL = 12 + , FUNC_BREAK = 13, FUNC_SLEEP = 14, FUNC_ADD = 32, FUNC_ADDU = 33 + , FUNC_SUB = 34, FUNC_SUBU = 35, FUNC_AND = 36, FUNC_OR = 37 + , FUNC_XOR = 38, FUNC_NOR = 39, FUNC_ADO16 = 41, FUNC_SLT = 42 + , FUNC_SLTU = 43, FUNC_MRGB = 45 +} FUNCTIONS; + +/* Enum declaration for iq10-only special function sub-opcodes. */ +typedef enum q10s_functions { + FUNC10_YIELD = 14, FUNC10_CNT1S = 46 +} Q10S_FUNCTIONS; + +/* Enum declaration for iq10 function sub-opcodes. */ +typedef enum cop_functions { + FUNC10_CFC = 0, FUNC10_LOCK = 1, FUNC10_CTC = 2, FUNC10_UNLK = 3 + , FUNC10_SWRD = 4, FUNC10_SWRDL = 5, FUNC10_SWWR = 6, FUNC10_SWWRU = 7 + , FUNC10_RBA = 8, FUNC10_RBAL = 9, FUNC10_RBAR = 10, FUNC10_DWRD = 12 + , FUNC10_DWRDL = 13, FUNC10_WBA = 16, FUNC10_WBAU = 17, FUNC10_WBAC = 18 + , FUNC10_CRC32 = 20, FUNC10_CRC32B = 21, FUNC10_MCID = 32, FUNC10_DBD = 33 + , FUNC10_DBA = 34, FUNC10_DPWT = 35, FUNC10_AVAIL = 36, FUNC10_FREE = 37 + , FUNC10_CHKHDR = 38, FUNC10_TSTOD = 39, FUNC10_PKRLA = 40, FUNC10_PKRLAU = 41 + , FUNC10_PKRLAH = 42, FUNC10_PKRLAC = 43, FUNC10_CMPHDR = 44, FUNC10_CM64RS = 0 + , FUNC10_CM64RD = 1, FUNC10_CM64RI = 4, FUNC10_CM64CLR = 5, FUNC10_CM64SS = 8 + , FUNC10_CM64SD = 9, FUNC10_CM64SI = 12, FUNC10_CM64RA = 16, FUNC10_CM64RIA2 = 20 + , FUNC10_CM128RIA2 = 21, FUNC10_CM64SA = 24, FUNC10_CM64SIA2 = 28, FUNC10_CM128SIA2 = 29 + , FUNC10_CM32RS = 32, FUNC10_CM32RD = 33, FUNC10_CM32XOR = 34, FUNC10_CM32ANDN = 35 + , FUNC10_CM32RI = 36, FUNC10_CM128VSA = 38, FUNC10_CM32SS = 40, FUNC10_CM32SD = 41 + , FUNC10_CM32OR = 42, FUNC10_CM32AND = 43, FUNC10_CM32SI = 44, FUNC10_CM32RA = 48 + , FUNC10_CM32SA = 56 +} COP_FUNCTIONS; + +/* Enum declaration for iq10 function sub-opcodes. */ +typedef enum cop_cm128_4functions { + FUNC10_CM128RIA3 = 4, FUNC10_CM128SIA3 = 6 +} COP_CM128_4FUNCTIONS; + +/* Enum declaration for iq10 function sub-opcodes. */ +typedef enum cop_cm128_3functions { + FUNC10_CM128RIA4 = 6, FUNC10_CM128SIA4 = 7 +} COP_CM128_3FUNCTIONS; + +/* Enum declaration for iq10 coprocessor sub-opcodes. */ +typedef enum cop2_functions { + FUNC10_PKRLI = 0, FUNC10_PKRLIU = 1, FUNC10_PKRLIH = 2, FUNC10_PKRLIC = 3 + , FUNC10_RBIR = 1, FUNC10_RBI = 2, FUNC10_RBIL = 3, FUNC10_WBIC = 5 + , FUNC10_WBI = 6, FUNC10_WBIU = 7 +} COP2_FUNCTIONS; + +/* Enum declaration for iq10 coprocessor cam sub-opcodes. */ +typedef enum cop3_cam_functions { + FUNC10_CAM36 = 16, FUNC10_CAM72 = 17, FUNC10_CAM144 = 18, FUNC10_CAM288 = 19 +} COP3_CAM_FUNCTIONS; + +/* Attributes. */ + +/* Enum declaration for machine type selection. */ +typedef enum mach_attr { + MACH_BASE, MACH_IQ2000, MACH_IQ10, MACH_MAX +} MACH_ATTR; + +/* Enum declaration for instruction set selection. */ +typedef enum isa_attr { + ISA_IQ2000, ISA_MAX +} ISA_ATTR; + +/* Number of architecture variants. */ +#define MAX_ISAS 1 +#define MAX_MACHS ((int) MACH_MAX) + +/* Ifield support. */ + +extern const struct cgen_ifld iq2000_cgen_ifld_table[]; + +/* Ifield attribute indices. */ + +/* Enum declaration for cgen_ifld attrs. */ +typedef enum cgen_ifld_attr { + CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED + , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31 + , CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS +} CGEN_IFLD_ATTR; + +/* Number of non-boolean elements in cgen_ifld_attr. */ +#define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1) + +/* Enum declaration for iq2000 ifield types. */ +typedef enum ifield_type { + IQ2000_F_NIL, IQ2000_F_ANYOF, IQ2000_F_OPCODE, IQ2000_F_RS + , IQ2000_F_RT, IQ2000_F_RD, IQ2000_F_SHAMT, IQ2000_F_CP_OP + , IQ2000_F_CP_OP_10, IQ2000_F_CP_GRP, IQ2000_F_FUNC, IQ2000_F_IMM + , IQ2000_F_RD_RS, IQ2000_F_RD_RT, IQ2000_F_RT_RS, IQ2000_F_JTARG + , IQ2000_F_JTARGQ10, IQ2000_F_OFFSET, IQ2000_F_COUNT, IQ2000_F_BYTECOUNT + , IQ2000_F_INDEX, IQ2000_F_MASK, IQ2000_F_MASKQ10, IQ2000_F_MASKL + , IQ2000_F_EXCODE, IQ2000_F_RSRVD, IQ2000_F_10_11, IQ2000_F_24_19 + , IQ2000_F_5, IQ2000_F_10, IQ2000_F_25, IQ2000_F_CAM_Z + , IQ2000_F_CAM_Y, IQ2000_F_CM_3FUNC, IQ2000_F_CM_4FUNC, IQ2000_F_CM_3Z + , IQ2000_F_CM_4Z, IQ2000_F_MAX +} IFIELD_TYPE; + +#define MAX_IFLD ((int) IQ2000_F_MAX) + +/* Hardware attribute indices. */ + +/* Enum declaration for cgen_hw attrs. */ +typedef enum cgen_hw_attr { + CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE + , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS +} CGEN_HW_ATTR; + +/* Number of non-boolean elements in cgen_hw_attr. */ +#define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1) + +/* Enum declaration for iq2000 hardware types. */ +typedef enum cgen_hw_type { + HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR + , HW_H_IADDR, HW_H_PC, HW_H_GR, HW_MAX +} CGEN_HW_TYPE; + +#define MAX_HW ((int) HW_MAX) + +/* Operand attribute indices. */ + +/* Enum declaration for cgen_operand attrs. */ +typedef enum cgen_operand_attr { + CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT + , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY + , CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH, CGEN_OPERAND_END_NBOOLS +} CGEN_OPERAND_ATTR; + +/* Number of non-boolean elements in cgen_operand_attr. */ +#define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1) + +/* Enum declaration for iq2000 operand types. */ +typedef enum cgen_operand_type { + IQ2000_OPERAND_PC, IQ2000_OPERAND_RS, IQ2000_OPERAND_RT, IQ2000_OPERAND_RD + , IQ2000_OPERAND_RD_RS, IQ2000_OPERAND_RD_RT, IQ2000_OPERAND_RT_RS, IQ2000_OPERAND_SHAMT + , IQ2000_OPERAND_IMM, IQ2000_OPERAND_OFFSET, IQ2000_OPERAND_BASEOFF, IQ2000_OPERAND_JMPTARG + , IQ2000_OPERAND_MASK, IQ2000_OPERAND_MASKQ10, IQ2000_OPERAND_MASKL, IQ2000_OPERAND_COUNT + , IQ2000_OPERAND_F_INDEX, IQ2000_OPERAND_EXECODE, IQ2000_OPERAND_BYTECOUNT, IQ2000_OPERAND_CAM_Y + , IQ2000_OPERAND_CAM_Z, IQ2000_OPERAND_CM_3FUNC, IQ2000_OPERAND_CM_4FUNC, IQ2000_OPERAND_CM_3Z + , IQ2000_OPERAND_CM_4Z, IQ2000_OPERAND_BASE, IQ2000_OPERAND_MASKR, IQ2000_OPERAND_BITNUM + , IQ2000_OPERAND_HI16, IQ2000_OPERAND_LO16, IQ2000_OPERAND_MLO16, IQ2000_OPERAND_JMPTARGQ10 + , IQ2000_OPERAND_MAX +} CGEN_OPERAND_TYPE; + +/* Number of operands types. */ +#define MAX_OPERANDS 32 + +/* Maximum number of operands referenced by any insn. */ +#define MAX_OPERAND_INSTANCES 8 + +/* Insn attribute indices. */ + +/* Enum declaration for cgen_insn attrs. */ +typedef enum cgen_insn_attr { + CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI + , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED + , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_YIELD_INSN, CGEN_INSN_LOAD_DELAY + , CGEN_INSN_EVEN_REG_NUM, CGEN_INSN_UNSUPPORTED, CGEN_INSN_USES_RD, CGEN_INSN_USES_RS + , CGEN_INSN_USES_RT, CGEN_INSN_USES_R31, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31 + , CGEN_INSN_MACH, CGEN_INSN_END_NBOOLS +} CGEN_INSN_ATTR; + +/* Number of non-boolean elements in cgen_insn_attr. */ +#define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1) + +/* cgen.h uses things we just defined. */ +#include "opcode/cgen.h" + +/* Attributes. */ +extern const CGEN_ATTR_TABLE iq2000_cgen_hardware_attr_table[]; +extern const CGEN_ATTR_TABLE iq2000_cgen_ifield_attr_table[]; +extern const CGEN_ATTR_TABLE iq2000_cgen_operand_attr_table[]; +extern const CGEN_ATTR_TABLE iq2000_cgen_insn_attr_table[]; + +/* Hardware decls. */ + +extern CGEN_KEYWORD iq2000_cgen_opval_gr_names; + + + + +#endif /* IQ2000_CPU_H */ diff --git a/opcodes/iq2000-dis.c b/opcodes/iq2000-dis.c new file mode 100644 index 0000000..c20e978 --- /dev/null +++ b/opcodes/iq2000-dis.c @@ -0,0 +1,609 @@ +/* Disassembler interface for targets using CGEN. -*- C -*- + CGEN: Cpu tools GENerator + +THIS FILE IS MACHINE GENERATED WITH CGEN. +- the resultant file is machine generated, cgen-dis.in isn't + +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 +Free Software Foundation, Inc. + +This file is part of the GNU Binutils and GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* ??? Eventually more and more of this stuff can go to cpu-independent files. + Keep that in mind. */ + +#include "sysdep.h" +#include +#include "ansidecl.h" +#include "dis-asm.h" +#include "bfd.h" +#include "symcat.h" +#include "libiberty.h" +#include "iq2000-desc.h" +#include "iq2000-opc.h" +#include "opintl.h" + +/* Default text to print if an instruction isn't recognized. */ +#define UNKNOWN_INSN_MSG _("*unknown*") + +static void print_normal + (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int); +static void print_address + (CGEN_CPU_DESC, void *, bfd_vma, unsigned int, bfd_vma, int); +static void print_keyword + (CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int); +static void print_insn_normal + (CGEN_CPU_DESC, void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int); +static int print_insn + (CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, unsigned); +static int default_print_insn + (CGEN_CPU_DESC, bfd_vma, disassemble_info *); +static int read_insn + (CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, int, CGEN_EXTRACT_INFO *, + unsigned long *); + +/* -- disassembler routines inserted here */ + + +void iq2000_cgen_print_operand + PARAMS ((CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, + void const *, bfd_vma, int)); + +/* Main entry point for printing operands. + XINFO is a `void *' and not a `disassemble_info *' to not put a requirement + of dis-asm.h on cgen.h. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `print_insn_normal', but keeping it + separate makes clear the interface between `print_insn_normal' and each of + the handlers. */ + +void +iq2000_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length) + CGEN_CPU_DESC cd; + int opindex; + PTR xinfo; + CGEN_FIELDS *fields; + void const *attrs ATTRIBUTE_UNUSED; + bfd_vma pc; + int length; +{ + disassemble_info *info = (disassemble_info *) xinfo; + + switch (opindex) + { + case IQ2000_OPERAND_BASE : + print_keyword (cd, info, & iq2000_cgen_opval_gr_names, fields->f_rs, 0); + break; + case IQ2000_OPERAND_BASEOFF : + print_address (cd, info, fields->f_imm, 0, pc, length); + break; + case IQ2000_OPERAND_BITNUM : + print_normal (cd, info, fields->f_rt, 0, pc, length); + break; + case IQ2000_OPERAND_BYTECOUNT : + print_normal (cd, info, fields->f_bytecount, 0, pc, length); + break; + case IQ2000_OPERAND_CAM_Y : + print_normal (cd, info, fields->f_cam_y, 0, pc, length); + break; + case IQ2000_OPERAND_CAM_Z : + print_normal (cd, info, fields->f_cam_z, 0, pc, length); + break; + case IQ2000_OPERAND_CM_3FUNC : + print_normal (cd, info, fields->f_cm_3func, 0, pc, length); + break; + case IQ2000_OPERAND_CM_3Z : + print_normal (cd, info, fields->f_cm_3z, 0, pc, length); + break; + case IQ2000_OPERAND_CM_4FUNC : + print_normal (cd, info, fields->f_cm_4func, 0, pc, length); + break; + case IQ2000_OPERAND_CM_4Z : + print_normal (cd, info, fields->f_cm_4z, 0, pc, length); + break; + case IQ2000_OPERAND_COUNT : + print_normal (cd, info, fields->f_count, 0, pc, length); + break; + case IQ2000_OPERAND_EXECODE : + print_normal (cd, info, fields->f_excode, 0, pc, length); + break; + case IQ2000_OPERAND_F_INDEX : + print_normal (cd, info, fields->f_index, 0, pc, length); + break; + case IQ2000_OPERAND_HI16 : + print_normal (cd, info, fields->f_imm, 0, pc, length); + break; + case IQ2000_OPERAND_IMM : + print_normal (cd, info, fields->f_imm, 0, pc, length); + break; + case IQ2000_OPERAND_JMPTARG : + print_address (cd, info, fields->f_jtarg, 0|(1<f_jtargq10, 0|(1<f_imm, 0, pc, length); + break; + case IQ2000_OPERAND_MASK : + print_normal (cd, info, fields->f_mask, 0, pc, length); + break; + case IQ2000_OPERAND_MASKL : + print_normal (cd, info, fields->f_maskl, 0, pc, length); + break; + case IQ2000_OPERAND_MASKQ10 : + print_normal (cd, info, fields->f_maskq10, 0, pc, length); + break; + case IQ2000_OPERAND_MASKR : + print_normal (cd, info, fields->f_rs, 0, pc, length); + break; + case IQ2000_OPERAND_MLO16 : + print_normal (cd, info, fields->f_imm, 0, pc, length); + break; + case IQ2000_OPERAND_OFFSET : + print_address (cd, info, fields->f_offset, 0|(1<f_rd, 0); + break; + case IQ2000_OPERAND_RD_RS : + print_keyword (cd, info, & iq2000_cgen_opval_gr_names, fields->f_rd_rs, 0|(1<f_rd_rt, 0|(1<f_rs, 0); + break; + case IQ2000_OPERAND_RT : + print_keyword (cd, info, & iq2000_cgen_opval_gr_names, fields->f_rt, 0); + break; + case IQ2000_OPERAND_RT_RS : + print_keyword (cd, info, & iq2000_cgen_opval_gr_names, fields->f_rt_rs, 0|(1<f_shamt, 0, pc, length); + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while printing insn.\n"), + opindex); + abort (); + } +} + +cgen_print_fn * const iq2000_cgen_print_handlers[] = +{ + print_insn_normal, +}; + + +void +iq2000_cgen_init_dis (cd) + CGEN_CPU_DESC cd; +{ + iq2000_cgen_init_opcode_table (cd); + iq2000_cgen_init_ibld_table (cd); + cd->print_handlers = & iq2000_cgen_print_handlers[0]; + cd->print_operand = iq2000_cgen_print_operand; +} + + +/* Default print handler. */ + +static void +print_normal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void *dis_info, + long value, + unsigned int attrs, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + disassemble_info *info = (disassemble_info *) dis_info; + +#ifdef CGEN_PRINT_NORMAL + CGEN_PRINT_NORMAL (cd, info, value, attrs, pc, length); +#endif + + /* Print the operand as directed by the attributes. */ + if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) + ; /* nothing to do */ + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) + (*info->fprintf_func) (info->stream, "%ld", value); + else + (*info->fprintf_func) (info->stream, "0x%lx", value); +} + +/* Default address handler. */ + +static void +print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void *dis_info, + bfd_vma value, + unsigned int attrs, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + disassemble_info *info = (disassemble_info *) dis_info; + +#ifdef CGEN_PRINT_ADDRESS + CGEN_PRINT_ADDRESS (cd, info, value, attrs, pc, length); +#endif + + /* Print the operand as directed by the attributes. */ + if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) + ; /* nothing to do */ + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR)) + (*info->print_address_func) (value, info); + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR)) + (*info->print_address_func) (value, info); + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) + (*info->fprintf_func) (info->stream, "%ld", (long) value); + else + (*info->fprintf_func) (info->stream, "0x%lx", (long) value); +} + +/* Keyword print handler. */ + +static void +print_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void *dis_info, + CGEN_KEYWORD *keyword_table, + long value, + unsigned int attrs ATTRIBUTE_UNUSED) +{ + disassemble_info *info = (disassemble_info *) dis_info; + const CGEN_KEYWORD_ENTRY *ke; + + ke = cgen_keyword_lookup_value (keyword_table, value); + if (ke != NULL) + (*info->fprintf_func) (info->stream, "%s", ke->name); + else + (*info->fprintf_func) (info->stream, "???"); +} + +/* Default insn printer. + + DIS_INFO is defined as `void *' so the disassembler needn't know anything + about disassemble_info. */ + +static void +print_insn_normal (CGEN_CPU_DESC cd, + void *dis_info, + const CGEN_INSN *insn, + CGEN_FIELDS *fields, + bfd_vma pc, + int length) +{ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + disassemble_info *info = (disassemble_info *) dis_info; + const CGEN_SYNTAX_CHAR_TYPE *syn; + + CGEN_INIT_PRINT (cd); + + for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) + { + if (CGEN_SYNTAX_MNEMONIC_P (*syn)) + { + (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn)); + continue; + } + if (CGEN_SYNTAX_CHAR_P (*syn)) + { + (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn)); + continue; + } + + /* We have an operand. */ + iq2000_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info, + fields, CGEN_INSN_ATTRS (insn), pc, length); + } +} + +/* Subroutine of print_insn. Reads an insn into the given buffers and updates + the extract info. + Returns 0 if all is well, non-zero otherwise. */ + +static int +read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + bfd_vma pc, + disassemble_info *info, + char *buf, + int buflen, + CGEN_EXTRACT_INFO *ex_info, + unsigned long *insn_value) +{ + int status = (*info->read_memory_func) (pc, buf, buflen, info); + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return -1; + } + + ex_info->dis_info = info; + ex_info->valid = (1 << buflen) - 1; + ex_info->insn_bytes = buf; + + *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG); + return 0; +} + +/* Utility to print an insn. + BUF is the base part of the insn, target byte order, BUFLEN bytes long. + The result is the size of the insn in bytes or zero for an unknown insn + or -1 if an error occurs fetching data (memory_error_func will have + been called). */ + +static int +print_insn (CGEN_CPU_DESC cd, + bfd_vma pc, + disassemble_info *info, + char *buf, + unsigned int buflen) +{ + CGEN_INSN_INT insn_value; + const CGEN_INSN_LIST *insn_list; + CGEN_EXTRACT_INFO ex_info; + int basesize; + + /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */ + basesize = cd->base_insn_bitsize < buflen * 8 ? + cd->base_insn_bitsize : buflen * 8; + insn_value = cgen_get_insn_value (cd, buf, basesize); + + + /* Fill in ex_info fields like read_insn would. Don't actually call + read_insn, since the incoming buffer is already read (and possibly + modified a la m32r). */ + ex_info.valid = (1 << buflen) - 1; + ex_info.dis_info = info; + ex_info.insn_bytes = buf; + + /* The instructions are stored in hash lists. + Pick the first one and keep trying until we find the right one. */ + + insn_list = CGEN_DIS_LOOKUP_INSN (cd, buf, insn_value); + while (insn_list != NULL) + { + const CGEN_INSN *insn = insn_list->insn; + CGEN_FIELDS fields; + int length; + unsigned long insn_value_cropped; + +#ifdef CGEN_VALIDATE_INSN_SUPPORTED + /* Not needed as insn shouldn't be in hash lists if not supported. */ + /* Supported by this cpu? */ + if (! iq2000_cgen_insn_supported (cd, insn)) + { + insn_list = CGEN_DIS_NEXT_INSN (insn_list); + continue; + } +#endif + + /* Basic bit mask must be correct. */ + /* ??? May wish to allow target to defer this check until the extract + handler. */ + + /* Base size may exceed this instruction's size. Extract the + relevant part from the buffer. */ + if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen && + (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) + insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn), + info->endian == BFD_ENDIAN_BIG); + else + insn_value_cropped = insn_value; + + if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn)) + == CGEN_INSN_BASE_VALUE (insn)) + { + /* Printing is handled in two passes. The first pass parses the + machine insn and extracts the fields. The second pass prints + them. */ + + /* Make sure the entire insn is loaded into insn_value, if it + can fit. */ + if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) && + (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) + { + unsigned long full_insn_value; + int rc = read_insn (cd, pc, info, buf, + CGEN_INSN_BITSIZE (insn) / 8, + & ex_info, & full_insn_value); + if (rc != 0) + return rc; + length = CGEN_EXTRACT_FN (cd, insn) + (cd, insn, &ex_info, full_insn_value, &fields, pc); + } + else + length = CGEN_EXTRACT_FN (cd, insn) + (cd, insn, &ex_info, insn_value_cropped, &fields, pc); + + /* length < 0 -> error */ + if (length < 0) + return length; + if (length > 0) + { + CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length); + /* length is in bits, result is in bytes */ + return length / 8; + } + } + + insn_list = CGEN_DIS_NEXT_INSN (insn_list); + } + + return 0; +} + +/* Default value for CGEN_PRINT_INSN. + The result is the size of the insn in bytes or zero for an unknown insn + or -1 if an error occured fetching bytes. */ + +#ifndef CGEN_PRINT_INSN +#define CGEN_PRINT_INSN default_print_insn +#endif + +static int +default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) +{ + char buf[CGEN_MAX_INSN_SIZE]; + int buflen; + int status; + + /* Attempt to read the base part of the insn. */ + buflen = cd->base_insn_bitsize / 8; + status = (*info->read_memory_func) (pc, buf, buflen, info); + + /* Try again with the minimum part, if min < base. */ + if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize)) + { + buflen = cd->min_insn_bitsize / 8; + status = (*info->read_memory_func) (pc, buf, buflen, info); + } + + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return -1; + } + + return print_insn (cd, pc, info, buf, buflen); +} + +/* Main entry point. + Print one instruction from PC on INFO->STREAM. + Return the size of the instruction (in bytes). */ + +typedef struct cpu_desc_list { + struct cpu_desc_list *next; + int isa; + int mach; + int endian; + CGEN_CPU_DESC cd; +} cpu_desc_list; + +int +print_insn_iq2000 (bfd_vma pc, disassemble_info *info) +{ + static cpu_desc_list *cd_list = 0; + cpu_desc_list *cl = 0; + static CGEN_CPU_DESC cd = 0; + static int prev_isa; + static int prev_mach; + static int prev_endian; + int length; + int isa,mach; + int endian = (info->endian == BFD_ENDIAN_BIG + ? CGEN_ENDIAN_BIG + : CGEN_ENDIAN_LITTLE); + enum bfd_architecture arch; + + /* ??? gdb will set mach but leave the architecture as "unknown" */ +#ifndef CGEN_BFD_ARCH +#define CGEN_BFD_ARCH bfd_arch_iq2000 +#endif + arch = info->arch; + if (arch == bfd_arch_unknown) + arch = CGEN_BFD_ARCH; + + /* There's no standard way to compute the machine or isa number + so we leave it to the target. */ +#ifdef CGEN_COMPUTE_MACH + mach = CGEN_COMPUTE_MACH (info); +#else + mach = info->mach; +#endif + +#ifdef CGEN_COMPUTE_ISA + isa = CGEN_COMPUTE_ISA (info); +#else + isa = info->insn_sets; +#endif + + /* If we've switched cpu's, try to find a handle we've used before */ + if (cd + && (isa != prev_isa + || mach != prev_mach + || endian != prev_endian)) + { + cd = 0; + for (cl = cd_list; cl; cl = cl->next) + { + if (cl->isa == isa && + cl->mach == mach && + cl->endian == endian) + { + cd = cl->cd; + break; + } + } + } + + /* If we haven't initialized yet, initialize the opcode table. */ + if (! cd) + { + const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach); + const char *mach_name; + + if (!arch_type) + abort (); + mach_name = arch_type->printable_name; + + prev_isa = isa; + prev_mach = mach; + prev_endian = endian; + cd = iq2000_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa, + CGEN_CPU_OPEN_BFDMACH, mach_name, + CGEN_CPU_OPEN_ENDIAN, prev_endian, + CGEN_CPU_OPEN_END); + if (!cd) + abort (); + + /* save this away for future reference */ + cl = xmalloc (sizeof (struct cpu_desc_list)); + cl->cd = cd; + cl->isa = isa; + cl->mach = mach; + cl->endian = endian; + cl->next = cd_list; + cd_list = cl; + + iq2000_cgen_init_dis (cd); + } + + /* We try to have as much common code as possible. + But at this point some targets need to take over. */ + /* ??? Some targets may need a hook elsewhere. Try to avoid this, + but if not possible try to move this hook elsewhere rather than + have two hooks. */ + length = CGEN_PRINT_INSN (cd, pc, info); + if (length > 0) + return length; + if (length < 0) + return -1; + + (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); + return cd->default_insn_bitsize / 8; +} diff --git a/opcodes/iq2000-ibld.c b/opcodes/iq2000-ibld.c new file mode 100644 index 0000000..f0640f0 --- /dev/null +++ b/opcodes/iq2000-ibld.c @@ -0,0 +1,1396 @@ +/* Instruction building/extraction support for iq2000. -*- C -*- + +THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator. +- the resultant file is machine generated, cgen-ibld.in isn't + +Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* ??? Eventually more and more of this stuff can go to cpu-independent files. + Keep that in mind. */ + +#include "sysdep.h" +#include +#include "ansidecl.h" +#include "dis-asm.h" +#include "bfd.h" +#include "symcat.h" +#include "iq2000-desc.h" +#include "iq2000-opc.h" +#include "opintl.h" +#include "safe-ctype.h" + +#undef min +#define min(a,b) ((a) < (b) ? (a) : (b)) +#undef max +#define max(a,b) ((a) > (b) ? (a) : (b)) + +/* Used by the ifield rtx function. */ +#define FLD(f) (fields->f) + +static const char * insert_normal + (CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int, + unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR); +static const char * insert_insn_normal + (CGEN_CPU_DESC, const CGEN_INSN *, + CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma); +static int extract_normal + (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, + unsigned int, unsigned int, unsigned int, unsigned int, + unsigned int, unsigned int, bfd_vma, long *); +static int extract_insn_normal + (CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *, + CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma); +#if CGEN_INT_INSN_P +static void put_insn_int_value + (CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT); +#endif +#if ! CGEN_INT_INSN_P +static CGEN_INLINE void insert_1 + (CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *); +static CGEN_INLINE int fill_cache + (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, bfd_vma); +static CGEN_INLINE long extract_1 + (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, unsigned char *, bfd_vma); +#endif + +/* Operand insertion. */ + +#if ! CGEN_INT_INSN_P + +/* Subroutine of insert_normal. */ + +static CGEN_INLINE void +insert_1 (CGEN_CPU_DESC cd, + unsigned long value, + int start, + int length, + int word_length, + unsigned char *bufp) +{ + unsigned long x,mask; + int shift; + + x = cgen_get_insn_value (cd, bufp, word_length); + + /* Written this way to avoid undefined behaviour. */ + mask = (((1L << (length - 1)) - 1) << 1) | 1; + if (CGEN_INSN_LSB0_P) + shift = (start + 1) - length; + else + shift = (word_length - (start + length)); + x = (x & ~(mask << shift)) | ((value & mask) << shift); + + cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x); +} + +#endif /* ! CGEN_INT_INSN_P */ + +/* Default insertion routine. + + ATTRS is a mask of the boolean attributes. + WORD_OFFSET is the offset in bits from the start of the insn of the value. + WORD_LENGTH is the length of the word in bits in which the value resides. + START is the starting bit number in the word, architecture origin. + LENGTH is the length of VALUE in bits. + TOTAL_LENGTH is the total length of the insn in bits. + + The result is an error message or NULL if success. */ + +/* ??? This duplicates functionality with bfd's howto table and + bfd_install_relocation. */ +/* ??? This doesn't handle bfd_vma's. Create another function when + necessary. */ + +static const char * +insert_normal (CGEN_CPU_DESC cd, + long value, + unsigned int attrs, + unsigned int word_offset, + unsigned int start, + unsigned int length, + unsigned int word_length, + unsigned int total_length, + CGEN_INSN_BYTES_PTR buffer) +{ + static char errbuf[100]; + /* Written this way to avoid undefined behaviour. */ + unsigned long mask = (((1L << (length - 1)) - 1) << 1) | 1; + + /* If LENGTH is zero, this operand doesn't contribute to the value. */ + if (length == 0) + return NULL; + +#if 0 + if (CGEN_INT_INSN_P + && word_offset != 0) + abort (); +#endif + + if (word_length > 32) + abort (); + + /* For architectures with insns smaller than the base-insn-bitsize, + word_length may be too big. */ + if (cd->min_insn_bitsize < cd->base_insn_bitsize) + { + if (word_offset == 0 + && word_length > total_length) + word_length = total_length; + } + + /* Ensure VALUE will fit. */ + if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGN_OPT)) + { + long minval = - (1L << (length - 1)); + unsigned long maxval = mask; + + if ((value > 0 && (unsigned long) value > maxval) + || value < minval) + { + /* xgettext:c-format */ + sprintf (errbuf, + _("operand out of range (%ld not between %ld and %lu)"), + value, minval, maxval); + return errbuf; + } + } + else if (! CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED)) + { + unsigned long maxval = mask; + + if ((unsigned long) value > maxval) + { + /* xgettext:c-format */ + sprintf (errbuf, + _("operand out of range (%lu not between 0 and %lu)"), + value, maxval); + return errbuf; + } + } + else + { + if (! cgen_signed_overflow_ok_p (cd)) + { + long minval = - (1L << (length - 1)); + long maxval = (1L << (length - 1)) - 1; + + if (value < minval || value > maxval) + { + sprintf + /* xgettext:c-format */ + (errbuf, _("operand out of range (%ld not between %ld and %ld)"), + value, minval, maxval); + return errbuf; + } + } + } + +#if CGEN_INT_INSN_P + + { + int shift; + + if (CGEN_INSN_LSB0_P) + shift = (word_offset + start + 1) - length; + else + shift = total_length - (word_offset + start + length); + *buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift); + } + +#else /* ! CGEN_INT_INSN_P */ + + { + unsigned char *bufp = (unsigned char *) buffer + word_offset / 8; + + insert_1 (cd, value, start, length, word_length, bufp); + } + +#endif /* ! CGEN_INT_INSN_P */ + + return NULL; +} + +/* Default insn builder (insert handler). + The instruction is recorded in CGEN_INT_INSN_P byte order (meaning + that if CGEN_INSN_BYTES_PTR is an int * and thus, the value is + recorded in host byte order, otherwise BUFFER is an array of bytes + and the value is recorded in target byte order). + The result is an error message or NULL if success. */ + +static const char * +insert_insn_normal (CGEN_CPU_DESC cd, + const CGEN_INSN * insn, + CGEN_FIELDS * fields, + CGEN_INSN_BYTES_PTR buffer, + bfd_vma pc) +{ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + unsigned long value; + const CGEN_SYNTAX_CHAR_TYPE * syn; + + CGEN_INIT_INSERT (cd); + value = CGEN_INSN_BASE_VALUE (insn); + + /* If we're recording insns as numbers (rather than a string of bytes), + target byte order handling is deferred until later. */ + +#if CGEN_INT_INSN_P + + put_insn_int_value (cd, buffer, cd->base_insn_bitsize, + CGEN_FIELDS_BITSIZE (fields), value); + +#else + + cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize, + (unsigned) CGEN_FIELDS_BITSIZE (fields)), + value); + +#endif /* ! CGEN_INT_INSN_P */ + + /* ??? It would be better to scan the format's fields. + Still need to be able to insert a value based on the operand though; + e.g. storing a branch displacement that got resolved later. + Needs more thought first. */ + + for (syn = CGEN_SYNTAX_STRING (syntax); * syn; ++ syn) + { + const char *errmsg; + + if (CGEN_SYNTAX_CHAR_P (* syn)) + continue; + + errmsg = (* cd->insert_operand) (cd, CGEN_SYNTAX_FIELD (*syn), + fields, buffer, pc); + if (errmsg) + return errmsg; + } + + return NULL; +} + +#if CGEN_INT_INSN_P +/* Cover function to store an insn value into an integral insn. Must go here + because it needs -desc.h for CGEN_INT_INSN_P. */ + +static void +put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + CGEN_INSN_BYTES_PTR buf, + int length, + int insn_length, + CGEN_INSN_INT value) +{ + /* For architectures with insns smaller than the base-insn-bitsize, + length may be too big. */ + if (length > insn_length) + *buf = value; + else + { + int shift = insn_length - length; + /* Written this way to avoid undefined behaviour. */ + CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1; + *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift); + } +} +#endif + +/* Operand extraction. */ + +#if ! CGEN_INT_INSN_P + +/* Subroutine of extract_normal. + Ensure sufficient bytes are cached in EX_INFO. + OFFSET is the offset in bytes from the start of the insn of the value. + BYTES is the length of the needed value. + Returns 1 for success, 0 for failure. */ + +static CGEN_INLINE int +fill_cache (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + CGEN_EXTRACT_INFO *ex_info, + int offset, + int bytes, + bfd_vma pc) +{ + /* It's doubtful that the middle part has already been fetched so + we don't optimize that case. kiss. */ + unsigned int mask; + disassemble_info *info = (disassemble_info *) ex_info->dis_info; + + /* First do a quick check. */ + mask = (1 << bytes) - 1; + if (((ex_info->valid >> offset) & mask) == mask) + return 1; + + /* Search for the first byte we need to read. */ + for (mask = 1 << offset; bytes > 0; --bytes, ++offset, mask <<= 1) + if (! (mask & ex_info->valid)) + break; + + if (bytes) + { + int status; + + pc += offset; + status = (*info->read_memory_func) + (pc, ex_info->insn_bytes + offset, bytes, info); + + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return 0; + } + + ex_info->valid |= ((1 << bytes) - 1) << offset; + } + + return 1; +} + +/* Subroutine of extract_normal. */ + +static CGEN_INLINE long +extract_1 (CGEN_CPU_DESC cd, + CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED, + int start, + int length, + int word_length, + unsigned char *bufp, + bfd_vma pc ATTRIBUTE_UNUSED) +{ + unsigned long x; + int shift; +#if 0 + int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG; +#endif + x = cgen_get_insn_value (cd, bufp, word_length); + + if (CGEN_INSN_LSB0_P) + shift = (start + 1) - length; + else + shift = (word_length - (start + length)); + return x >> shift; +} + +#endif /* ! CGEN_INT_INSN_P */ + +/* Default extraction routine. + + INSN_VALUE is the first base_insn_bitsize bits of the insn in host order, + or sometimes less for cases like the m32r where the base insn size is 32 + but some insns are 16 bits. + ATTRS is a mask of the boolean attributes. We only need `SIGNED', + but for generality we take a bitmask of all of them. + WORD_OFFSET is the offset in bits from the start of the insn of the value. + WORD_LENGTH is the length of the word in bits in which the value resides. + START is the starting bit number in the word, architecture origin. + LENGTH is the length of VALUE in bits. + TOTAL_LENGTH is the total length of the insn in bits. + + Returns 1 for success, 0 for failure. */ + +/* ??? The return code isn't properly used. wip. */ + +/* ??? This doesn't handle bfd_vma's. Create another function when + necessary. */ + +static int +extract_normal (CGEN_CPU_DESC cd, +#if ! CGEN_INT_INSN_P + CGEN_EXTRACT_INFO *ex_info, +#else + CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED, +#endif + CGEN_INSN_INT insn_value, + unsigned int attrs, + unsigned int word_offset, + unsigned int start, + unsigned int length, + unsigned int word_length, + unsigned int total_length, +#if ! CGEN_INT_INSN_P + bfd_vma pc, +#else + bfd_vma pc ATTRIBUTE_UNUSED, +#endif + long *valuep) +{ + long value, mask; + + /* If LENGTH is zero, this operand doesn't contribute to the value + so give it a standard value of zero. */ + if (length == 0) + { + *valuep = 0; + return 1; + } + +#if 0 + if (CGEN_INT_INSN_P + && word_offset != 0) + abort (); +#endif + + if (word_length > 32) + abort (); + + /* For architectures with insns smaller than the insn-base-bitsize, + word_length may be too big. */ + if (cd->min_insn_bitsize < cd->base_insn_bitsize) + { + if (word_offset == 0 + && word_length > total_length) + word_length = total_length; + } + + /* Does the value reside in INSN_VALUE, and at the right alignment? */ + + if (CGEN_INT_INSN_P || (word_offset == 0 && word_length == total_length)) + { + if (CGEN_INSN_LSB0_P) + value = insn_value >> ((word_offset + start + 1) - length); + else + value = insn_value >> (total_length - ( word_offset + start + length)); + } + +#if ! CGEN_INT_INSN_P + + else + { + unsigned char *bufp = ex_info->insn_bytes + word_offset / 8; + + if (word_length > 32) + abort (); + + if (fill_cache (cd, ex_info, word_offset / 8, word_length / 8, pc) == 0) + return 0; + + value = extract_1 (cd, ex_info, start, length, word_length, bufp, pc); + } + +#endif /* ! CGEN_INT_INSN_P */ + + /* Written this way to avoid undefined behaviour. */ + mask = (((1L << (length - 1)) - 1) << 1) | 1; + + value &= mask; + /* sign extend? */ + if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED) + && (value & (1L << (length - 1)))) + value |= ~mask; + + *valuep = value; + + return 1; +} + +/* Default insn extractor. + + INSN_VALUE is the first base_insn_bitsize bits, translated to host order. + The extracted fields are stored in FIELDS. + EX_INFO is used to handle reading variable length insns. + Return the length of the insn in bits, or 0 if no match, + or -1 if an error occurs fetching data (memory_error_func will have + been called). */ + +static int +extract_insn_normal (CGEN_CPU_DESC cd, + const CGEN_INSN *insn, + CGEN_EXTRACT_INFO *ex_info, + CGEN_INSN_INT insn_value, + CGEN_FIELDS *fields, + bfd_vma pc) +{ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + const CGEN_SYNTAX_CHAR_TYPE *syn; + + CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); + + CGEN_INIT_EXTRACT (cd); + + for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) + { + int length; + + if (CGEN_SYNTAX_CHAR_P (*syn)) + continue; + + length = (* cd->extract_operand) (cd, CGEN_SYNTAX_FIELD (*syn), + ex_info, insn_value, fields, pc); + if (length <= 0) + return length; + } + + /* We recognized and successfully extracted this insn. */ + return CGEN_INSN_BITSIZE (insn); +} + +/* machine generated code added here */ + +const char * iq2000_cgen_insert_operand + PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma)); + +/* Main entry point for operand insertion. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `parse_insn_normal', but keeping it + separate makes clear the interface between `parse_insn_normal' and each of + the handlers. It's also needed by GAS to insert operands that couldn't be + resolved during parsing. */ + +const char * +iq2000_cgen_insert_operand (cd, opindex, fields, buffer, pc) + CGEN_CPU_DESC cd; + int opindex; + CGEN_FIELDS * fields; + CGEN_INSN_BYTES_PTR buffer; + bfd_vma pc ATTRIBUTE_UNUSED; +{ + const char * errmsg = NULL; + unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); + + switch (opindex) + { + case IQ2000_OPERAND_BASE : + errmsg = insert_normal (cd, fields->f_rs, 0, 0, 25, 5, 32, total_length, buffer); + break; + case IQ2000_OPERAND_BASEOFF : + errmsg = insert_normal (cd, fields->f_imm, 0, 0, 15, 16, 32, total_length, buffer); + break; + case IQ2000_OPERAND_BITNUM : + errmsg = insert_normal (cd, fields->f_rt, 0, 0, 20, 5, 32, total_length, buffer); + break; + case IQ2000_OPERAND_BYTECOUNT : + errmsg = insert_normal (cd, fields->f_bytecount, 0, 0, 7, 8, 32, total_length, buffer); + break; + case IQ2000_OPERAND_CAM_Y : + errmsg = insert_normal (cd, fields->f_cam_y, 0, 0, 2, 3, 32, total_length, buffer); + break; + case IQ2000_OPERAND_CAM_Z : + errmsg = insert_normal (cd, fields->f_cam_z, 0, 0, 5, 3, 32, total_length, buffer); + break; + case IQ2000_OPERAND_CM_3FUNC : + errmsg = insert_normal (cd, fields->f_cm_3func, 0, 0, 5, 3, 32, total_length, buffer); + break; + case IQ2000_OPERAND_CM_3Z : + errmsg = insert_normal (cd, fields->f_cm_3z, 0, 0, 1, 2, 32, total_length, buffer); + break; + case IQ2000_OPERAND_CM_4FUNC : + errmsg = insert_normal (cd, fields->f_cm_4func, 0, 0, 5, 4, 32, total_length, buffer); + break; + case IQ2000_OPERAND_CM_4Z : + errmsg = insert_normal (cd, fields->f_cm_4z, 0, 0, 2, 3, 32, total_length, buffer); + break; + case IQ2000_OPERAND_COUNT : + errmsg = insert_normal (cd, fields->f_count, 0, 0, 15, 7, 32, total_length, buffer); + break; + case IQ2000_OPERAND_EXECODE : + errmsg = insert_normal (cd, fields->f_excode, 0, 0, 25, 20, 32, total_length, buffer); + break; + case IQ2000_OPERAND_F_INDEX : + errmsg = insert_normal (cd, fields->f_index, 0, 0, 8, 9, 32, total_length, buffer); + break; + case IQ2000_OPERAND_HI16 : + errmsg = insert_normal (cd, fields->f_imm, 0, 0, 15, 16, 32, total_length, buffer); + break; + case IQ2000_OPERAND_IMM : + errmsg = insert_normal (cd, fields->f_imm, 0, 0, 15, 16, 32, total_length, buffer); + break; + case IQ2000_OPERAND_JMPTARG : + { + long value = fields->f_jtarg; + value = ((unsigned int) (((value) & (262143))) >> (2)); + errmsg = insert_normal (cd, value, 0|(1<f_jtargq10; + value = ((unsigned int) (((value) & (8388607))) >> (2)); + errmsg = insert_normal (cd, value, 0|(1<f_imm, 0, 0, 15, 16, 32, total_length, buffer); + break; + case IQ2000_OPERAND_MASK : + errmsg = insert_normal (cd, fields->f_mask, 0, 0, 9, 4, 32, total_length, buffer); + break; + case IQ2000_OPERAND_MASKL : + errmsg = insert_normal (cd, fields->f_maskl, 0, 0, 4, 5, 32, total_length, buffer); + break; + case IQ2000_OPERAND_MASKQ10 : + errmsg = insert_normal (cd, fields->f_maskq10, 0, 0, 10, 5, 32, total_length, buffer); + break; + case IQ2000_OPERAND_MASKR : + errmsg = insert_normal (cd, fields->f_rs, 0, 0, 25, 5, 32, total_length, buffer); + break; + case IQ2000_OPERAND_MLO16 : + errmsg = insert_normal (cd, fields->f_imm, 0, 0, 15, 16, 32, total_length, buffer); + break; + case IQ2000_OPERAND_OFFSET : + { + long value = fields->f_offset; + value = ((int) (((value) - (pc))) >> (2)); + errmsg = insert_normal (cd, value, 0|(1<f_rd, 0, 0, 15, 5, 32, total_length, buffer); + break; + case IQ2000_OPERAND_RD_RS : + { +{ + FLD (f_rd) = FLD (f_rd_rs); + FLD (f_rs) = FLD (f_rd_rs); +} + errmsg = insert_normal (cd, fields->f_rd, 0, 0, 15, 5, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_rs, 0, 0, 25, 5, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case IQ2000_OPERAND_RD_RT : + { +{ + FLD (f_rd) = FLD (f_rd_rt); + FLD (f_rt) = FLD (f_rd_rt); +} + errmsg = insert_normal (cd, fields->f_rd, 0, 0, 15, 5, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_rt, 0, 0, 20, 5, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case IQ2000_OPERAND_RS : + errmsg = insert_normal (cd, fields->f_rs, 0, 0, 25, 5, 32, total_length, buffer); + break; + case IQ2000_OPERAND_RT : + errmsg = insert_normal (cd, fields->f_rt, 0, 0, 20, 5, 32, total_length, buffer); + break; + case IQ2000_OPERAND_RT_RS : + { +{ + FLD (f_rt) = FLD (f_rt_rs); + FLD (f_rs) = FLD (f_rt_rs); +} + errmsg = insert_normal (cd, fields->f_rt, 0, 0, 20, 5, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_rs, 0, 0, 25, 5, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case IQ2000_OPERAND_SHAMT : + errmsg = insert_normal (cd, fields->f_shamt, 0, 0, 10, 5, 32, total_length, buffer); + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while building insn.\n"), + opindex); + abort (); + } + + return errmsg; +} + +int iq2000_cgen_extract_operand + PARAMS ((CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, + CGEN_FIELDS *, bfd_vma)); + +/* Main entry point for operand extraction. + The result is <= 0 for error, >0 for success. + ??? Actual values aren't well defined right now. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `print_insn_normal', but keeping it + separate makes clear the interface between `print_insn_normal' and each of + the handlers. */ + +int +iq2000_cgen_extract_operand (cd, opindex, ex_info, insn_value, fields, pc) + CGEN_CPU_DESC cd; + int opindex; + CGEN_EXTRACT_INFO *ex_info; + CGEN_INSN_INT insn_value; + CGEN_FIELDS * fields; + bfd_vma pc; +{ + /* Assume success (for those operands that are nops). */ + int length = 1; + unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); + + switch (opindex) + { + case IQ2000_OPERAND_BASE : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_rs); + break; + case IQ2000_OPERAND_BASEOFF : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 16, 32, total_length, pc, & fields->f_imm); + break; + case IQ2000_OPERAND_BITNUM : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 5, 32, total_length, pc, & fields->f_rt); + break; + case IQ2000_OPERAND_BYTECOUNT : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 7, 8, 32, total_length, pc, & fields->f_bytecount); + break; + case IQ2000_OPERAND_CAM_Y : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 2, 3, 32, total_length, pc, & fields->f_cam_y); + break; + case IQ2000_OPERAND_CAM_Z : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 3, 32, total_length, pc, & fields->f_cam_z); + break; + case IQ2000_OPERAND_CM_3FUNC : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 3, 32, total_length, pc, & fields->f_cm_3func); + break; + case IQ2000_OPERAND_CM_3Z : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 1, 2, 32, total_length, pc, & fields->f_cm_3z); + break; + case IQ2000_OPERAND_CM_4FUNC : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 4, 32, total_length, pc, & fields->f_cm_4func); + break; + case IQ2000_OPERAND_CM_4Z : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 2, 3, 32, total_length, pc, & fields->f_cm_4z); + break; + case IQ2000_OPERAND_COUNT : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 7, 32, total_length, pc, & fields->f_count); + break; + case IQ2000_OPERAND_EXECODE : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 20, 32, total_length, pc, & fields->f_excode); + break; + case IQ2000_OPERAND_F_INDEX : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 9, 32, total_length, pc, & fields->f_index); + break; + case IQ2000_OPERAND_HI16 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 16, 32, total_length, pc, & fields->f_imm); + break; + case IQ2000_OPERAND_IMM : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 16, 32, total_length, pc, & fields->f_imm); + break; + case IQ2000_OPERAND_JMPTARG : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_jtarg = value; + } + break; + case IQ2000_OPERAND_JMPTARGQ10 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_jtargq10 = value; + } + break; + case IQ2000_OPERAND_LO16 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 16, 32, total_length, pc, & fields->f_imm); + break; + case IQ2000_OPERAND_MASK : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 4, 32, total_length, pc, & fields->f_mask); + break; + case IQ2000_OPERAND_MASKL : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 5, 32, total_length, pc, & fields->f_maskl); + break; + case IQ2000_OPERAND_MASKQ10 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 10, 5, 32, total_length, pc, & fields->f_maskq10); + break; + case IQ2000_OPERAND_MASKR : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_rs); + break; + case IQ2000_OPERAND_MLO16 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 16, 32, total_length, pc, & fields->f_imm); + break; + case IQ2000_OPERAND_OFFSET : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_offset = value; + } + break; + case IQ2000_OPERAND_RD : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 5, 32, total_length, pc, & fields->f_rd); + break; + case IQ2000_OPERAND_RD_RS : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 5, 32, total_length, pc, & fields->f_rd); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_rs); + if (length <= 0) break; +{ + FLD (f_rd_rs) = FLD (f_rs); +} + } + break; + case IQ2000_OPERAND_RD_RT : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 5, 32, total_length, pc, & fields->f_rd); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 5, 32, total_length, pc, & fields->f_rt); + if (length <= 0) break; +{ + FLD (f_rd_rt) = FLD (f_rt); +} + } + break; + case IQ2000_OPERAND_RS : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_rs); + break; + case IQ2000_OPERAND_RT : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 5, 32, total_length, pc, & fields->f_rt); + break; + case IQ2000_OPERAND_RT_RS : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 5, 32, total_length, pc, & fields->f_rt); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_rs); + if (length <= 0) break; +{ + FLD (f_rd_rs) = FLD (f_rs); +} + } + break; + case IQ2000_OPERAND_SHAMT : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 10, 5, 32, total_length, pc, & fields->f_shamt); + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while decoding insn.\n"), + opindex); + abort (); + } + + return length; +} + +cgen_insert_fn * const iq2000_cgen_insert_handlers[] = +{ + insert_insn_normal, +}; + +cgen_extract_fn * const iq2000_cgen_extract_handlers[] = +{ + extract_insn_normal, +}; + +int iq2000_cgen_get_int_operand + PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *)); +bfd_vma iq2000_cgen_get_vma_operand + PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *)); + +/* Getting values from cgen_fields is handled by a collection of functions. + They are distinguished by the type of the VALUE argument they return. + TODO: floating point, inlining support, remove cases where result type + not appropriate. */ + +int +iq2000_cgen_get_int_operand (cd, opindex, fields) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + int opindex; + const CGEN_FIELDS * fields; +{ + int value; + + switch (opindex) + { + case IQ2000_OPERAND_BASE : + value = fields->f_rs; + break; + case IQ2000_OPERAND_BASEOFF : + value = fields->f_imm; + break; + case IQ2000_OPERAND_BITNUM : + value = fields->f_rt; + break; + case IQ2000_OPERAND_BYTECOUNT : + value = fields->f_bytecount; + break; + case IQ2000_OPERAND_CAM_Y : + value = fields->f_cam_y; + break; + case IQ2000_OPERAND_CAM_Z : + value = fields->f_cam_z; + break; + case IQ2000_OPERAND_CM_3FUNC : + value = fields->f_cm_3func; + break; + case IQ2000_OPERAND_CM_3Z : + value = fields->f_cm_3z; + break; + case IQ2000_OPERAND_CM_4FUNC : + value = fields->f_cm_4func; + break; + case IQ2000_OPERAND_CM_4Z : + value = fields->f_cm_4z; + break; + case IQ2000_OPERAND_COUNT : + value = fields->f_count; + break; + case IQ2000_OPERAND_EXECODE : + value = fields->f_excode; + break; + case IQ2000_OPERAND_F_INDEX : + value = fields->f_index; + break; + case IQ2000_OPERAND_HI16 : + value = fields->f_imm; + break; + case IQ2000_OPERAND_IMM : + value = fields->f_imm; + break; + case IQ2000_OPERAND_JMPTARG : + value = fields->f_jtarg; + break; + case IQ2000_OPERAND_JMPTARGQ10 : + value = fields->f_jtargq10; + break; + case IQ2000_OPERAND_LO16 : + value = fields->f_imm; + break; + case IQ2000_OPERAND_MASK : + value = fields->f_mask; + break; + case IQ2000_OPERAND_MASKL : + value = fields->f_maskl; + break; + case IQ2000_OPERAND_MASKQ10 : + value = fields->f_maskq10; + break; + case IQ2000_OPERAND_MASKR : + value = fields->f_rs; + break; + case IQ2000_OPERAND_MLO16 : + value = fields->f_imm; + break; + case IQ2000_OPERAND_OFFSET : + value = fields->f_offset; + break; + case IQ2000_OPERAND_RD : + value = fields->f_rd; + break; + case IQ2000_OPERAND_RD_RS : + value = fields->f_rd_rs; + break; + case IQ2000_OPERAND_RD_RT : + value = fields->f_rd_rt; + break; + case IQ2000_OPERAND_RS : + value = fields->f_rs; + break; + case IQ2000_OPERAND_RT : + value = fields->f_rt; + break; + case IQ2000_OPERAND_RT_RS : + value = fields->f_rt_rs; + break; + case IQ2000_OPERAND_SHAMT : + value = fields->f_shamt; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"), + opindex); + abort (); + } + + return value; +} + +bfd_vma +iq2000_cgen_get_vma_operand (cd, opindex, fields) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + int opindex; + const CGEN_FIELDS * fields; +{ + bfd_vma value; + + switch (opindex) + { + case IQ2000_OPERAND_BASE : + value = fields->f_rs; + break; + case IQ2000_OPERAND_BASEOFF : + value = fields->f_imm; + break; + case IQ2000_OPERAND_BITNUM : + value = fields->f_rt; + break; + case IQ2000_OPERAND_BYTECOUNT : + value = fields->f_bytecount; + break; + case IQ2000_OPERAND_CAM_Y : + value = fields->f_cam_y; + break; + case IQ2000_OPERAND_CAM_Z : + value = fields->f_cam_z; + break; + case IQ2000_OPERAND_CM_3FUNC : + value = fields->f_cm_3func; + break; + case IQ2000_OPERAND_CM_3Z : + value = fields->f_cm_3z; + break; + case IQ2000_OPERAND_CM_4FUNC : + value = fields->f_cm_4func; + break; + case IQ2000_OPERAND_CM_4Z : + value = fields->f_cm_4z; + break; + case IQ2000_OPERAND_COUNT : + value = fields->f_count; + break; + case IQ2000_OPERAND_EXECODE : + value = fields->f_excode; + break; + case IQ2000_OPERAND_F_INDEX : + value = fields->f_index; + break; + case IQ2000_OPERAND_HI16 : + value = fields->f_imm; + break; + case IQ2000_OPERAND_IMM : + value = fields->f_imm; + break; + case IQ2000_OPERAND_JMPTARG : + value = fields->f_jtarg; + break; + case IQ2000_OPERAND_JMPTARGQ10 : + value = fields->f_jtargq10; + break; + case IQ2000_OPERAND_LO16 : + value = fields->f_imm; + break; + case IQ2000_OPERAND_MASK : + value = fields->f_mask; + break; + case IQ2000_OPERAND_MASKL : + value = fields->f_maskl; + break; + case IQ2000_OPERAND_MASKQ10 : + value = fields->f_maskq10; + break; + case IQ2000_OPERAND_MASKR : + value = fields->f_rs; + break; + case IQ2000_OPERAND_MLO16 : + value = fields->f_imm; + break; + case IQ2000_OPERAND_OFFSET : + value = fields->f_offset; + break; + case IQ2000_OPERAND_RD : + value = fields->f_rd; + break; + case IQ2000_OPERAND_RD_RS : + value = fields->f_rd_rs; + break; + case IQ2000_OPERAND_RD_RT : + value = fields->f_rd_rt; + break; + case IQ2000_OPERAND_RS : + value = fields->f_rs; + break; + case IQ2000_OPERAND_RT : + value = fields->f_rt; + break; + case IQ2000_OPERAND_RT_RS : + value = fields->f_rt_rs; + break; + case IQ2000_OPERAND_SHAMT : + value = fields->f_shamt; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"), + opindex); + abort (); + } + + return value; +} + +void iq2000_cgen_set_int_operand + PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, int)); +void iq2000_cgen_set_vma_operand + PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma)); + +/* Stuffing values in cgen_fields is handled by a collection of functions. + They are distinguished by the type of the VALUE argument they accept. + TODO: floating point, inlining support, remove cases where argument type + not appropriate. */ + +void +iq2000_cgen_set_int_operand (cd, opindex, fields, value) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + int opindex; + CGEN_FIELDS * fields; + int value; +{ + switch (opindex) + { + case IQ2000_OPERAND_BASE : + fields->f_rs = value; + break; + case IQ2000_OPERAND_BASEOFF : + fields->f_imm = value; + break; + case IQ2000_OPERAND_BITNUM : + fields->f_rt = value; + break; + case IQ2000_OPERAND_BYTECOUNT : + fields->f_bytecount = value; + break; + case IQ2000_OPERAND_CAM_Y : + fields->f_cam_y = value; + break; + case IQ2000_OPERAND_CAM_Z : + fields->f_cam_z = value; + break; + case IQ2000_OPERAND_CM_3FUNC : + fields->f_cm_3func = value; + break; + case IQ2000_OPERAND_CM_3Z : + fields->f_cm_3z = value; + break; + case IQ2000_OPERAND_CM_4FUNC : + fields->f_cm_4func = value; + break; + case IQ2000_OPERAND_CM_4Z : + fields->f_cm_4z = value; + break; + case IQ2000_OPERAND_COUNT : + fields->f_count = value; + break; + case IQ2000_OPERAND_EXECODE : + fields->f_excode = value; + break; + case IQ2000_OPERAND_F_INDEX : + fields->f_index = value; + break; + case IQ2000_OPERAND_HI16 : + fields->f_imm = value; + break; + case IQ2000_OPERAND_IMM : + fields->f_imm = value; + break; + case IQ2000_OPERAND_JMPTARG : + fields->f_jtarg = value; + break; + case IQ2000_OPERAND_JMPTARGQ10 : + fields->f_jtargq10 = value; + break; + case IQ2000_OPERAND_LO16 : + fields->f_imm = value; + break; + case IQ2000_OPERAND_MASK : + fields->f_mask = value; + break; + case IQ2000_OPERAND_MASKL : + fields->f_maskl = value; + break; + case IQ2000_OPERAND_MASKQ10 : + fields->f_maskq10 = value; + break; + case IQ2000_OPERAND_MASKR : + fields->f_rs = value; + break; + case IQ2000_OPERAND_MLO16 : + fields->f_imm = value; + break; + case IQ2000_OPERAND_OFFSET : + fields->f_offset = value; + break; + case IQ2000_OPERAND_RD : + fields->f_rd = value; + break; + case IQ2000_OPERAND_RD_RS : + fields->f_rd_rs = value; + break; + case IQ2000_OPERAND_RD_RT : + fields->f_rd_rt = value; + break; + case IQ2000_OPERAND_RS : + fields->f_rs = value; + break; + case IQ2000_OPERAND_RT : + fields->f_rt = value; + break; + case IQ2000_OPERAND_RT_RS : + fields->f_rt_rs = value; + break; + case IQ2000_OPERAND_SHAMT : + fields->f_shamt = value; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"), + opindex); + abort (); + } +} + +void +iq2000_cgen_set_vma_operand (cd, opindex, fields, value) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + int opindex; + CGEN_FIELDS * fields; + bfd_vma value; +{ + switch (opindex) + { + case IQ2000_OPERAND_BASE : + fields->f_rs = value; + break; + case IQ2000_OPERAND_BASEOFF : + fields->f_imm = value; + break; + case IQ2000_OPERAND_BITNUM : + fields->f_rt = value; + break; + case IQ2000_OPERAND_BYTECOUNT : + fields->f_bytecount = value; + break; + case IQ2000_OPERAND_CAM_Y : + fields->f_cam_y = value; + break; + case IQ2000_OPERAND_CAM_Z : + fields->f_cam_z = value; + break; + case IQ2000_OPERAND_CM_3FUNC : + fields->f_cm_3func = value; + break; + case IQ2000_OPERAND_CM_3Z : + fields->f_cm_3z = value; + break; + case IQ2000_OPERAND_CM_4FUNC : + fields->f_cm_4func = value; + break; + case IQ2000_OPERAND_CM_4Z : + fields->f_cm_4z = value; + break; + case IQ2000_OPERAND_COUNT : + fields->f_count = value; + break; + case IQ2000_OPERAND_EXECODE : + fields->f_excode = value; + break; + case IQ2000_OPERAND_F_INDEX : + fields->f_index = value; + break; + case IQ2000_OPERAND_HI16 : + fields->f_imm = value; + break; + case IQ2000_OPERAND_IMM : + fields->f_imm = value; + break; + case IQ2000_OPERAND_JMPTARG : + fields->f_jtarg = value; + break; + case IQ2000_OPERAND_JMPTARGQ10 : + fields->f_jtargq10 = value; + break; + case IQ2000_OPERAND_LO16 : + fields->f_imm = value; + break; + case IQ2000_OPERAND_MASK : + fields->f_mask = value; + break; + case IQ2000_OPERAND_MASKL : + fields->f_maskl = value; + break; + case IQ2000_OPERAND_MASKQ10 : + fields->f_maskq10 = value; + break; + case IQ2000_OPERAND_MASKR : + fields->f_rs = value; + break; + case IQ2000_OPERAND_MLO16 : + fields->f_imm = value; + break; + case IQ2000_OPERAND_OFFSET : + fields->f_offset = value; + break; + case IQ2000_OPERAND_RD : + fields->f_rd = value; + break; + case IQ2000_OPERAND_RD_RS : + fields->f_rd_rs = value; + break; + case IQ2000_OPERAND_RD_RT : + fields->f_rd_rt = value; + break; + case IQ2000_OPERAND_RS : + fields->f_rs = value; + break; + case IQ2000_OPERAND_RT : + fields->f_rt = value; + break; + case IQ2000_OPERAND_RT_RS : + fields->f_rt_rs = value; + break; + case IQ2000_OPERAND_SHAMT : + fields->f_shamt = value; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"), + opindex); + abort (); + } +} + +/* Function to call before using the instruction builder tables. */ + +void +iq2000_cgen_init_ibld_table (cd) + CGEN_CPU_DESC cd; +{ + cd->insert_handlers = & iq2000_cgen_insert_handlers[0]; + cd->extract_handlers = & iq2000_cgen_extract_handlers[0]; + + cd->insert_operand = iq2000_cgen_insert_operand; + cd->extract_operand = iq2000_cgen_extract_operand; + + cd->get_int_operand = iq2000_cgen_get_int_operand; + cd->set_int_operand = iq2000_cgen_set_int_operand; + cd->get_vma_operand = iq2000_cgen_get_vma_operand; + cd->set_vma_operand = iq2000_cgen_set_vma_operand; +} diff --git a/opcodes/iq2000-opc.c b/opcodes/iq2000-opc.c new file mode 100644 index 0000000..35ffdf0 --- /dev/null +++ b/opcodes/iq2000-opc.c @@ -0,0 +1,3482 @@ +/* Instruction opcode table for iq2000. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +*/ + +#include "sysdep.h" +#include "ansidecl.h" +#include "bfd.h" +#include "symcat.h" +#include "iq2000-desc.h" +#include "iq2000-opc.h" +#include "libiberty.h" + +/* The hash functions are recorded here to help keep assembler code out of + the disassembler and vice versa. */ + +static int asm_hash_insn_p PARAMS ((const CGEN_INSN *)); +static unsigned int asm_hash_insn PARAMS ((const char *)); +static int dis_hash_insn_p PARAMS ((const CGEN_INSN *)); +static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT)); + +/* Instruction formats. */ + +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define F(f) & iq2000_cgen_ifld_table[IQ2000_##f] +#else +#define F(f) & iq2000_cgen_ifld_table[IQ2000_/**/f] +#endif +static const CGEN_IFMT ifmt_empty = { + 0, 0, 0x0, { { 0 } } +}; + +static const CGEN_IFMT ifmt_add2 = { + 32, 32, 0xfc0007ff, { { F (F_OPCODE) }, { F (F_RT) }, { F (F_RD_RS) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_add = { + 32, 32, 0xfc0007ff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_addi2 = { + 32, 32, 0xfc000000, { { F (F_OPCODE) }, { F (F_RT_RS) }, { F (F_IMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_addi = { + 32, 32, 0xfc000000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_IMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ram = { + 32, 32, 0xfc000020, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_5) }, { F (F_MASKL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sll = { + 32, 32, 0xffe0003f, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sllv2 = { + 32, 32, 0xfc0007ff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RD_RT) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_slmv2 = { + 32, 32, 0xfc00003f, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RD_RT) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_slmv = { + 32, 32, 0xfc00003f, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_slti2 = { + 32, 32, 0xfc000000, { { F (F_OPCODE) }, { F (F_RT_RS) }, { F (F_IMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_slti = { + 32, 32, 0xfc000000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_IMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sra2 = { + 32, 32, 0xffe0003f, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RD_RT) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bbi = { + 32, 32, 0xfc000000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_OFFSET) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bbv = { + 32, 32, 0xfc000000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_OFFSET) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bgez = { + 32, 32, 0xfc1f0000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_OFFSET) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_jalr = { + 32, 32, 0xfc1f07ff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_jr = { + 32, 32, 0xfc1fffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_lb = { + 32, 32, 0xfc000000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_IMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_lui = { + 32, 32, 0xffe00000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_IMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_break = { + 32, 32, 0xffffffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_syscall = { + 32, 32, 0xfc00003f, { { F (F_OPCODE) }, { F (F_EXCODE) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_andoui = { + 32, 32, 0xfc000000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_IMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_andoui2 = { + 32, 32, 0xfc000000, { { F (F_OPCODE) }, { F (F_RT_RS) }, { F (F_IMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mrgb = { + 32, 32, 0xfc00043f, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_10) }, { F (F_MASK) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mrgb2 = { + 32, 32, 0xfc00043f, { { F (F_OPCODE) }, { F (F_RT) }, { F (F_RD_RS) }, { F (F_10) }, { F (F_MASK) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bc0f = { + 32, 32, 0xffff0000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_OFFSET) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cfc0 = { + 32, 32, 0xffe007ff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_10_11) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_chkhdr = { + 32, 32, 0xffe007ff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_lulck = { + 32, 32, 0xffe0ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_pkrlr1 = { + 23, 23, 0xffe00000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_COUNT) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_rfe = { + 32, 32, 0xffffffff, { { F (F_OPCODE) }, { F (F_25) }, { F (F_24_19) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_j = { + 32, 32, 0xffff0000, { { F (F_OPCODE) }, { F (F_RSRVD) }, { F (F_JTARG) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mrgbq10 = { + 32, 32, 0xfc00003f, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_MASKQ10) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mrgbq102 = { + 32, 32, 0xfc00003f, { { F (F_OPCODE) }, { F (F_RT) }, { F (F_RD_RS) }, { F (F_MASKQ10) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_jq10 = { + 32, 32, 0xffff0000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_JTARG) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_jalq10 = { + 32, 32, 0xffe00000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_JTARG) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_avail = { + 32, 32, 0xffff07ff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_rbi = { + 32, 32, 0xfc000700, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_BYTECOUNT) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cam36 = { + 32, 32, 0xffe007c0, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP_10) }, { F (F_CAM_Z) }, { F (F_CAM_Y) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cm32and = { + 32, 32, 0xfc0007ff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cm32rd = { + 32, 32, 0xffe007ff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cm128ria3 = { + 32, 32, 0xfc0007fc, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_CM_4FUNC) }, { F (F_CM_3Z) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cm128ria4 = { + 32, 32, 0xfc0007f8, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_CM_3FUNC) }, { F (F_CM_4Z) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ctc = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +#undef F + +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define A(a) (1 << CGEN_INSN_##a) +#else +#define A(a) (1 << CGEN_INSN_/**/a) +#endif +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define OPERAND(op) IQ2000_OPERAND_##op +#else +#define OPERAND(op) IQ2000_OPERAND_/**/op +#endif +#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */ +#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) + +/* The instruction table. */ + +static const CGEN_OPCODE iq2000_cgen_insn_opcode_table[MAX_INSNS] = +{ + /* Special null first entry. + A `num' value of zero is thus invalid. + Also, the special `invalid' insn resides here. */ + { { 0, 0, 0, 0 }, {{0}}, 0, {0}}, +/* add ${rd-rs},$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD_RS), ',', OP (RT), 0 } }, + & ifmt_add2, { 0x20 } + }, +/* add $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_add, { 0x20 } + }, +/* addi ${rt-rs},$lo16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT_RS), ',', OP (LO16), 0 } }, + & ifmt_addi2, { 0x20000000 } + }, +/* addi $rt,$rs,$lo16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RS), ',', OP (LO16), 0 } }, + & ifmt_addi, { 0x20000000 } + }, +/* addiu ${rt-rs},$lo16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT_RS), ',', OP (LO16), 0 } }, + & ifmt_addi2, { 0x24000000 } + }, +/* addiu $rt,$rs,$lo16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RS), ',', OP (LO16), 0 } }, + & ifmt_addi, { 0x24000000 } + }, +/* addu ${rd-rs},$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD_RS), ',', OP (RT), 0 } }, + & ifmt_add2, { 0x21 } + }, +/* addu $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_add, { 0x21 } + }, +/* ado16 ${rd-rs},$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD_RS), ',', OP (RT), 0 } }, + & ifmt_add2, { 0x29 } + }, +/* ado16 $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_add, { 0x29 } + }, +/* and ${rd-rs},$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD_RS), ',', OP (RT), 0 } }, + & ifmt_add2, { 0x24 } + }, +/* and $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_add, { 0x24 } + }, +/* andi ${rt-rs},$lo16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT_RS), ',', OP (LO16), 0 } }, + & ifmt_addi2, { 0x30000000 } + }, +/* andi $rt,$rs,$lo16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RS), ',', OP (LO16), 0 } }, + & ifmt_addi, { 0x30000000 } + }, +/* andoi ${rt-rs},$lo16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT_RS), ',', OP (LO16), 0 } }, + & ifmt_addi2, { 0xb0000000 } + }, +/* andoi $rt,$rs,$lo16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RS), ',', OP (LO16), 0 } }, + & ifmt_addi, { 0xb0000000 } + }, +/* nor ${rd-rs},$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD_RS), ',', OP (RT), 0 } }, + & ifmt_add2, { 0x27 } + }, +/* nor $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_add, { 0x27 } + }, +/* or ${rd-rs},$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD_RS), ',', OP (RT), 0 } }, + & ifmt_add2, { 0x25 } + }, +/* or $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_add, { 0x25 } + }, +/* ori ${rt-rs},$lo16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT_RS), ',', OP (LO16), 0 } }, + & ifmt_addi2, { 0x34000000 } + }, +/* ori $rt,$rs,$lo16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RS), ',', OP (LO16), 0 } }, + & ifmt_addi, { 0x34000000 } + }, +/* ram $rd,$rt,$shamt,$maskl,$maskr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), ',', OP (SHAMT), ',', OP (MASKL), ',', OP (MASKR), 0 } }, + & ifmt_ram, { 0x9c000000 } + }, +/* sll $rd,$rt,$shamt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), ',', OP (SHAMT), 0 } }, + & ifmt_sll, { 0x0 } + }, +/* sllv ${rd-rt},$rs */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD_RT), ',', OP (RS), 0 } }, + & ifmt_sllv2, { 0x4 } + }, +/* sllv $rd,$rt,$rs */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), ',', OP (RS), 0 } }, + & ifmt_add, { 0x4 } + }, +/* slmv ${rd-rt},$rs,$shamt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD_RT), ',', OP (RS), ',', OP (SHAMT), 0 } }, + & ifmt_slmv2, { 0x1 } + }, +/* slmv $rd,$rt,$rs,$shamt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), ',', OP (RS), ',', OP (SHAMT), 0 } }, + & ifmt_slmv, { 0x1 } + }, +/* slt ${rd-rs},$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD_RS), ',', OP (RT), 0 } }, + & ifmt_add2, { 0x2a } + }, +/* slt $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_add, { 0x2a } + }, +/* slti ${rt-rs},$imm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT_RS), ',', OP (IMM), 0 } }, + & ifmt_slti2, { 0x28000000 } + }, +/* slti $rt,$rs,$imm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RS), ',', OP (IMM), 0 } }, + & ifmt_slti, { 0x28000000 } + }, +/* sltiu ${rt-rs},$imm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT_RS), ',', OP (IMM), 0 } }, + & ifmt_slti2, { 0x2c000000 } + }, +/* sltiu $rt,$rs,$imm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RS), ',', OP (IMM), 0 } }, + & ifmt_slti, { 0x2c000000 } + }, +/* sltu ${rd-rs},$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD_RS), ',', OP (RT), 0 } }, + & ifmt_add2, { 0x2b } + }, +/* sltu $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_add, { 0x2b } + }, +/* sra ${rd-rt},$shamt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD_RT), ',', OP (SHAMT), 0 } }, + & ifmt_sra2, { 0x3 } + }, +/* sra $rd,$rt,$shamt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), ',', OP (SHAMT), 0 } }, + & ifmt_sll, { 0x3 } + }, +/* srav ${rd-rt},$rs */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD_RT), ',', OP (RS), 0 } }, + & ifmt_sllv2, { 0x7 } + }, +/* srav $rd,$rt,$rs */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), ',', OP (RS), 0 } }, + & ifmt_add, { 0x7 } + }, +/* srl $rd,$rt,$shamt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), ',', OP (SHAMT), 0 } }, + & ifmt_sll, { 0x2 } + }, +/* srlv ${rd-rt},$rs */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD_RT), ',', OP (RS), 0 } }, + & ifmt_sllv2, { 0x6 } + }, +/* srlv $rd,$rt,$rs */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), ',', OP (RS), 0 } }, + & ifmt_add, { 0x6 } + }, +/* srmv ${rd-rt},$rs,$shamt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD_RT), ',', OP (RS), ',', OP (SHAMT), 0 } }, + & ifmt_slmv2, { 0x5 } + }, +/* srmv $rd,$rt,$rs,$shamt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), ',', OP (RS), ',', OP (SHAMT), 0 } }, + & ifmt_slmv, { 0x5 } + }, +/* sub ${rd-rs},$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD_RS), ',', OP (RT), 0 } }, + & ifmt_add2, { 0x22 } + }, +/* sub $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_add, { 0x22 } + }, +/* subu ${rd-rs},$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD_RS), ',', OP (RT), 0 } }, + & ifmt_add2, { 0x23 } + }, +/* subu $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_add, { 0x23 } + }, +/* xor ${rd-rs},$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD_RS), ',', OP (RT), 0 } }, + & ifmt_add2, { 0x26 } + }, +/* xor $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_add, { 0x26 } + }, +/* xori ${rt-rs},$lo16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT_RS), ',', OP (LO16), 0 } }, + & ifmt_addi2, { 0x38000000 } + }, +/* xori $rt,$rs,$lo16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RS), ',', OP (LO16), 0 } }, + & ifmt_addi, { 0x38000000 } + }, +/* bbi $rs($bitnum),$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), '(', OP (BITNUM), ')', ',', OP (OFFSET), 0 } }, + & ifmt_bbi, { 0x70000000 } + }, +/* bbin $rs($bitnum),$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), '(', OP (BITNUM), ')', ',', OP (OFFSET), 0 } }, + & ifmt_bbi, { 0x78000000 } + }, +/* bbv $rs,$rt,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (RT), ',', OP (OFFSET), 0 } }, + & ifmt_bbv, { 0x74000000 } + }, +/* bbvn $rs,$rt,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (RT), ',', OP (OFFSET), 0 } }, + & ifmt_bbv, { 0x7c000000 } + }, +/* beq $rs,$rt,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (RT), ',', OP (OFFSET), 0 } }, + & ifmt_bbv, { 0x10000000 } + }, +/* beql $rs,$rt,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (RT), ',', OP (OFFSET), 0 } }, + & ifmt_bbv, { 0x50000000 } + }, +/* bgez $rs,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (OFFSET), 0 } }, + & ifmt_bgez, { 0x4010000 } + }, +/* bgezal $rs,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (OFFSET), 0 } }, + & ifmt_bgez, { 0x4110000 } + }, +/* bgezall $rs,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (OFFSET), 0 } }, + & ifmt_bgez, { 0x4130000 } + }, +/* bgezl $rs,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (OFFSET), 0 } }, + & ifmt_bgez, { 0x4030000 } + }, +/* bltz $rs,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (OFFSET), 0 } }, + & ifmt_bgez, { 0x4000000 } + }, +/* bltzl $rs,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (OFFSET), 0 } }, + & ifmt_bgez, { 0x4020000 } + }, +/* bltzal $rs,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (OFFSET), 0 } }, + & ifmt_bgez, { 0x4100000 } + }, +/* bltzall $rs,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (OFFSET), 0 } }, + & ifmt_bgez, { 0x4120000 } + }, +/* bmb0 $rs,$rt,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (RT), ',', OP (OFFSET), 0 } }, + & ifmt_bbv, { 0x60000000 } + }, +/* bmb1 $rs,$rt,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (RT), ',', OP (OFFSET), 0 } }, + & ifmt_bbv, { 0x64000000 } + }, +/* bmb2 $rs,$rt,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (RT), ',', OP (OFFSET), 0 } }, + & ifmt_bbv, { 0x68000000 } + }, +/* bmb3 $rs,$rt,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (RT), ',', OP (OFFSET), 0 } }, + & ifmt_bbv, { 0x6c000000 } + }, +/* bne $rs,$rt,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (RT), ',', OP (OFFSET), 0 } }, + & ifmt_bbv, { 0x14000000 } + }, +/* bnel $rs,$rt,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (RT), ',', OP (OFFSET), 0 } }, + & ifmt_bbv, { 0x54000000 } + }, +/* jalr $rd,$rs */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), 0 } }, + & ifmt_jalr, { 0x9 } + }, +/* jr $rs */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), 0 } }, + & ifmt_jr, { 0x8 } + }, +/* lb $rt,$lo16($base) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (LO16), '(', OP (BASE), ')', 0 } }, + & ifmt_lb, { 0x80000000 } + }, +/* lbu $rt,$lo16($base) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (LO16), '(', OP (BASE), ')', 0 } }, + & ifmt_lb, { 0x90000000 } + }, +/* lh $rt,$lo16($base) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (LO16), '(', OP (BASE), ')', 0 } }, + & ifmt_lb, { 0x84000000 } + }, +/* lhu $rt,$lo16($base) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (LO16), '(', OP (BASE), ')', 0 } }, + & ifmt_lb, { 0x94000000 } + }, +/* lui $rt,$hi16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (HI16), 0 } }, + & ifmt_lui, { 0x3c000000 } + }, +/* lw $rt,$lo16($base) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (LO16), '(', OP (BASE), ')', 0 } }, + & ifmt_lb, { 0x8c000000 } + }, +/* sb $rt,$lo16($base) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (LO16), '(', OP (BASE), ')', 0 } }, + & ifmt_lb, { 0xa0000000 } + }, +/* sh $rt,$lo16($base) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (LO16), '(', OP (BASE), ')', 0 } }, + & ifmt_lb, { 0xa4000000 } + }, +/* sw $rt,$lo16($base) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (LO16), '(', OP (BASE), ')', 0 } }, + & ifmt_lb, { 0xac000000 } + }, +/* break */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_break, { 0xd } + }, +/* syscall */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_syscall, { 0xc } + }, +/* andoui $rt,$rs,$hi16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RS), ',', OP (HI16), 0 } }, + & ifmt_andoui, { 0xfc000000 } + }, +/* andoui ${rt-rs},$hi16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT_RS), ',', OP (HI16), 0 } }, + & ifmt_andoui2, { 0xfc000000 } + }, +/* orui ${rt-rs},$hi16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT_RS), ',', OP (HI16), 0 } }, + & ifmt_andoui2, { 0xbc000000 } + }, +/* orui $rt,$rs,$hi16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RS), ',', OP (HI16), 0 } }, + & ifmt_andoui, { 0xbc000000 } + }, +/* bgtz $rs,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (OFFSET), 0 } }, + & ifmt_bgez, { 0x1c000000 } + }, +/* bgtzl $rs,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (OFFSET), 0 } }, + & ifmt_bgez, { 0x5c000000 } + }, +/* blez $rs,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (OFFSET), 0 } }, + & ifmt_bgez, { 0x18000000 } + }, +/* blezl $rs,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (OFFSET), 0 } }, + & ifmt_bgez, { 0x58000000 } + }, +/* mrgb $rd,$rs,$rt,$mask */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), ',', OP (MASK), 0 } }, + & ifmt_mrgb, { 0x2d } + }, +/* mrgb ${rd-rs},$rt,$mask */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD_RS), ',', OP (RT), ',', OP (MASK), 0 } }, + & ifmt_mrgb2, { 0x2d } + }, +/* bctxt $rs,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (OFFSET), 0 } }, + & ifmt_bgez, { 0x4060000 } + }, +/* bc0f $offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (OFFSET), 0 } }, + & ifmt_bc0f, { 0x41000000 } + }, +/* bc0fl $offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (OFFSET), 0 } }, + & ifmt_bc0f, { 0x41020000 } + }, +/* bc3f $offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (OFFSET), 0 } }, + & ifmt_bc0f, { 0x4d000000 } + }, +/* bc3fl $offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (OFFSET), 0 } }, + & ifmt_bc0f, { 0x4d020000 } + }, +/* bc0t $offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (OFFSET), 0 } }, + & ifmt_bc0f, { 0x41010000 } + }, +/* bc0tl $offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (OFFSET), 0 } }, + & ifmt_bc0f, { 0x41030000 } + }, +/* bc3t $offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (OFFSET), 0 } }, + & ifmt_bc0f, { 0x4d010000 } + }, +/* bc3tl $offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (OFFSET), 0 } }, + & ifmt_bc0f, { 0x4d030000 } + }, +/* cfc0 $rt,$rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RD), 0 } }, + & ifmt_cfc0, { 0x40400000 } + }, +/* cfc1 $rt,$rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RD), 0 } }, + & ifmt_cfc0, { 0x44400000 } + }, +/* cfc2 $rt,$rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RD), 0 } }, + & ifmt_cfc0, { 0x48400000 } + }, +/* cfc3 $rt,$rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RD), 0 } }, + & ifmt_cfc0, { 0x4c400000 } + }, +/* chkhdr $rd,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), 0 } }, + & ifmt_chkhdr, { 0x4d200000 } + }, +/* ctc0 $rt,$rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RD), 0 } }, + & ifmt_cfc0, { 0x40c00000 } + }, +/* ctc1 $rt,$rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RD), 0 } }, + & ifmt_cfc0, { 0x44c00000 } + }, +/* ctc2 $rt,$rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RD), 0 } }, + & ifmt_cfc0, { 0x48c00000 } + }, +/* ctc3 $rt,$rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RD), 0 } }, + & ifmt_cfc0, { 0x4cc00000 } + }, +/* jcr $rs */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), 0 } }, + & ifmt_jr, { 0xa } + }, +/* luc32 $rt,$rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RD), 0 } }, + & ifmt_chkhdr, { 0x48200003 } + }, +/* luc32l $rt,$rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RD), 0 } }, + & ifmt_chkhdr, { 0x48200007 } + }, +/* luc64 $rt,$rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RD), 0 } }, + & ifmt_chkhdr, { 0x4820000b } + }, +/* luc64l $rt,$rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RD), 0 } }, + & ifmt_chkhdr, { 0x4820000f } + }, +/* luk $rt,$rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RD), 0 } }, + & ifmt_chkhdr, { 0x48200008 } + }, +/* lulck $rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), 0 } }, + & ifmt_lulck, { 0x48200004 } + }, +/* lum32 $rt,$rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RD), 0 } }, + & ifmt_chkhdr, { 0x48200002 } + }, +/* lum32l $rt,$rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RD), 0 } }, + & ifmt_chkhdr, { 0x48200006 } + }, +/* lum64 $rt,$rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RD), 0 } }, + & ifmt_chkhdr, { 0x4820000a } + }, +/* lum64l $rt,$rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RD), 0 } }, + & ifmt_chkhdr, { 0x4820000e } + }, +/* lur $rt,$rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RD), 0 } }, + & ifmt_chkhdr, { 0x48200001 } + }, +/* lurl $rt,$rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RD), 0 } }, + & ifmt_chkhdr, { 0x48200005 } + }, +/* luulck $rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), 0 } }, + & ifmt_lulck, { 0x48200000 } + }, +/* mfc0 $rt,$rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RD), 0 } }, + & ifmt_cfc0, { 0x40000000 } + }, +/* mfc1 $rt,$rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RD), 0 } }, + & ifmt_cfc0, { 0x44000000 } + }, +/* mfc2 $rt,$rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RD), 0 } }, + & ifmt_cfc0, { 0x48000000 } + }, +/* mfc3 $rt,$rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RD), 0 } }, + & ifmt_cfc0, { 0x4c000000 } + }, +/* mtc0 $rt,$rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RD), 0 } }, + & ifmt_cfc0, { 0x40800000 } + }, +/* mtc1 $rt,$rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RD), 0 } }, + & ifmt_cfc0, { 0x44800000 } + }, +/* mtc2 $rt,$rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RD), 0 } }, + & ifmt_cfc0, { 0x48800000 } + }, +/* mtc3 $rt,$rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RD), 0 } }, + & ifmt_cfc0, { 0x4c800000 } + }, +/* pkrl $rd,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), 0 } }, + & ifmt_chkhdr, { 0x4c200007 } + }, +/* pkrlr1 $rt,$count */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (COUNT), 0 } }, + & ifmt_pkrlr1, { 0x4fa00000 } + }, +/* pkrlr30 $rt,$count */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (COUNT), 0 } }, + & ifmt_pkrlr1, { 0x4fe00000 } + }, +/* rb $rd,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), 0 } }, + & ifmt_chkhdr, { 0x4c200004 } + }, +/* rbr1 $rt,$count */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (COUNT), 0 } }, + & ifmt_pkrlr1, { 0x4f000000 } + }, +/* rbr30 $rt,$count */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (COUNT), 0 } }, + & ifmt_pkrlr1, { 0x4f400000 } + }, +/* rfe */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_rfe, { 0x42000010 } + }, +/* rx $rd,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), 0 } }, + & ifmt_chkhdr, { 0x4c200006 } + }, +/* rxr1 $rt,$count */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (COUNT), 0 } }, + & ifmt_pkrlr1, { 0x4f800000 } + }, +/* rxr30 $rt,$count */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (COUNT), 0 } }, + & ifmt_pkrlr1, { 0x4fc00000 } + }, +/* sleep */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_syscall, { 0xe } + }, +/* srrd $rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), 0 } }, + & ifmt_lulck, { 0x48200010 } + }, +/* srrdl $rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), 0 } }, + & ifmt_lulck, { 0x48200014 } + }, +/* srulck $rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), 0 } }, + & ifmt_lulck, { 0x48200016 } + }, +/* srwr $rt,$rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RD), 0 } }, + & ifmt_chkhdr, { 0x48200011 } + }, +/* srwru $rt,$rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RD), 0 } }, + & ifmt_chkhdr, { 0x48200015 } + }, +/* trapqfl */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_break, { 0x4c200008 } + }, +/* trapqne */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_break, { 0x4c200009 } + }, +/* traprel $rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), 0 } }, + & ifmt_lulck, { 0x4c20000a } + }, +/* wb $rd,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), 0 } }, + & ifmt_chkhdr, { 0x4c200000 } + }, +/* wbu $rd,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), 0 } }, + & ifmt_chkhdr, { 0x4c200001 } + }, +/* wbr1 $rt,$count */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (COUNT), 0 } }, + & ifmt_pkrlr1, { 0x4e000000 } + }, +/* wbr1u $rt,$count */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (COUNT), 0 } }, + & ifmt_pkrlr1, { 0x4e200000 } + }, +/* wbr30 $rt,$count */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (COUNT), 0 } }, + & ifmt_pkrlr1, { 0x4e400000 } + }, +/* wbr30u $rt,$count */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (COUNT), 0 } }, + & ifmt_pkrlr1, { 0x4e600000 } + }, +/* wx $rd,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), 0 } }, + & ifmt_chkhdr, { 0x4c200002 } + }, +/* wxu $rd,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), 0 } }, + & ifmt_chkhdr, { 0x4c200003 } + }, +/* wxr1 $rt,$count */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (COUNT), 0 } }, + & ifmt_pkrlr1, { 0x4e800000 } + }, +/* wxr1u $rt,$count */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (COUNT), 0 } }, + & ifmt_pkrlr1, { 0x4ea00000 } + }, +/* wxr30 $rt,$count */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (COUNT), 0 } }, + & ifmt_pkrlr1, { 0x4ec00000 } + }, +/* wxr30u $rt,$count */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (COUNT), 0 } }, + & ifmt_pkrlr1, { 0x4ee00000 } + }, +/* ldw $rt,$lo16($base) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (LO16), '(', OP (BASE), ')', 0 } }, + & ifmt_lb, { 0xc0000000 } + }, +/* sdw $rt,$lo16($base) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (LO16), '(', OP (BASE), ')', 0 } }, + & ifmt_lb, { 0xe0000000 } + }, +/* j $jmptarg */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (JMPTARG), 0 } }, + & ifmt_j, { 0x8000000 } + }, +/* jal $jmptarg */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (JMPTARG), 0 } }, + & ifmt_j, { 0xc000000 } + }, +/* bmb $rs,$rt,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (RT), ',', OP (OFFSET), 0 } }, + & ifmt_bbv, { 0xb4000000 } + }, +/* andoui $rt,$rs,$hi16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RS), ',', OP (HI16), 0 } }, + & ifmt_andoui, { 0xbc000000 } + }, +/* andoui ${rt-rs},$hi16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT_RS), ',', OP (HI16), 0 } }, + & ifmt_andoui2, { 0xbc000000 } + }, +/* orui $rt,$rs,$hi16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RS), ',', OP (HI16), 0 } }, + & ifmt_andoui, { 0x3c000000 } + }, +/* orui ${rt-rs},$hi16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT_RS), ',', OP (HI16), 0 } }, + & ifmt_andoui2, { 0x3c000000 } + }, +/* mrgb $rd,$rs,$rt,$maskq10 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), ',', OP (MASKQ10), 0 } }, + & ifmt_mrgbq10, { 0x2d } + }, +/* mrgb ${rd-rs},$rt,$maskq10 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD_RS), ',', OP (RT), ',', OP (MASKQ10), 0 } }, + & ifmt_mrgbq102, { 0x2d } + }, +/* j $jmptarg */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (JMPTARG), 0 } }, + & ifmt_jq10, { 0x8000000 } + }, +/* jal $rt,$jmptarg */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (JMPTARG), 0 } }, + & ifmt_jalq10, { 0xc000000 } + }, +/* jal $jmptarg */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (JMPTARG), 0 } }, + & ifmt_jq10, { 0xc1f0000 } + }, +/* bbil $rs($bitnum),$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), '(', OP (BITNUM), ')', ',', OP (OFFSET), 0 } }, + & ifmt_bbi, { 0xf0000000 } + }, +/* bbinl $rs($bitnum),$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), '(', OP (BITNUM), ')', ',', OP (OFFSET), 0 } }, + & ifmt_bbi, { 0xf8000000 } + }, +/* bbvl $rs,$rt,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (RT), ',', OP (OFFSET), 0 } }, + & ifmt_bbv, { 0xf4000000 } + }, +/* bbvnl $rs,$rt,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (RT), ',', OP (OFFSET), 0 } }, + & ifmt_bbv, { 0xfc000000 } + }, +/* bgtzal $rs,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (OFFSET), 0 } }, + & ifmt_bgez, { 0x4150000 } + }, +/* bgtzall $rs,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (OFFSET), 0 } }, + & ifmt_bgez, { 0x4170000 } + }, +/* blezal $rs,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (OFFSET), 0 } }, + & ifmt_bgez, { 0x4140000 } + }, +/* blezall $rs,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (OFFSET), 0 } }, + & ifmt_bgez, { 0x4160000 } + }, +/* bgtz $rs,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (OFFSET), 0 } }, + & ifmt_bgez, { 0x4050000 } + }, +/* bgtzl $rs,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (OFFSET), 0 } }, + & ifmt_bgez, { 0x4070000 } + }, +/* blez $rs,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (OFFSET), 0 } }, + & ifmt_bgez, { 0x4040000 } + }, +/* blezl $rs,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (OFFSET), 0 } }, + & ifmt_bgez, { 0x4060000 } + }, +/* bmb $rs,$rt,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (RT), ',', OP (OFFSET), 0 } }, + & ifmt_bbv, { 0x18000000 } + }, +/* bmbl $rs,$rt,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (RT), ',', OP (OFFSET), 0 } }, + & ifmt_bbv, { 0x58000000 } + }, +/* bri $rs,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (OFFSET), 0 } }, + & ifmt_bgez, { 0x4080000 } + }, +/* brv $rs,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (OFFSET), 0 } }, + & ifmt_bgez, { 0x4090000 } + }, +/* bctx $rs,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (OFFSET), 0 } }, + & ifmt_bgez, { 0x40c0000 } + }, +/* yield */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_break, { 0xe } + }, +/* crc32 $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_add, { 0x4c000014 } + }, +/* crc32b $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_add, { 0x4c000015 } + }, +/* cnt1s $rd,$rs */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), 0 } }, + & ifmt_add, { 0x2e } + }, +/* avail $rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), 0 } }, + & ifmt_avail, { 0x4c000024 } + }, +/* free $rd,$rs */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), 0 } }, + & ifmt_jalr, { 0x4c000025 } + }, +/* tstod $rd,$rs */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), 0 } }, + & ifmt_jalr, { 0x4c000027 } + }, +/* cmphdr $rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), 0 } }, + & ifmt_avail, { 0x4c00002c } + }, +/* mcid $rd,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), 0 } }, + & ifmt_chkhdr, { 0x4c000020 } + }, +/* dba $rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), 0 } }, + & ifmt_avail, { 0x4c000022 } + }, +/* dbd $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_add, { 0x4c000021 } + }, +/* dpwt $rd,$rs */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), 0 } }, + & ifmt_jalr, { 0x4c000023 } + }, +/* chkhdr $rd,$rs */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), 0 } }, + & ifmt_jalr, { 0x4c000026 } + }, +/* rba $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_add, { 0x4c000008 } + }, +/* rbal $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_add, { 0x4c000009 } + }, +/* rbar $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_add, { 0x4c00000a } + }, +/* wba $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_add, { 0x4c000010 } + }, +/* wbau $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_add, { 0x4c000011 } + }, +/* wbac $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_add, { 0x4c000012 } + }, +/* rbi $rd,$rs,$rt,$bytecount */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), ',', OP (BYTECOUNT), 0 } }, + & ifmt_rbi, { 0x4c000200 } + }, +/* rbil $rd,$rs,$rt,$bytecount */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), ',', OP (BYTECOUNT), 0 } }, + & ifmt_rbi, { 0x4c000300 } + }, +/* rbir $rd,$rs,$rt,$bytecount */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), ',', OP (BYTECOUNT), 0 } }, + & ifmt_rbi, { 0x4c000100 } + }, +/* wbi $rd,$rs,$rt,$bytecount */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), ',', OP (BYTECOUNT), 0 } }, + & ifmt_rbi, { 0x4c000600 } + }, +/* wbic $rd,$rs,$rt,$bytecount */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), ',', OP (BYTECOUNT), 0 } }, + & ifmt_rbi, { 0x4c000500 } + }, +/* wbiu $rd,$rs,$rt,$bytecount */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), ',', OP (BYTECOUNT), 0 } }, + & ifmt_rbi, { 0x4c000700 } + }, +/* pkrli $rd,$rs,$rt,$bytecount */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), ',', OP (BYTECOUNT), 0 } }, + & ifmt_rbi, { 0x48000000 } + }, +/* pkrlih $rd,$rs,$rt,$bytecount */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), ',', OP (BYTECOUNT), 0 } }, + & ifmt_rbi, { 0x48000200 } + }, +/* pkrliu $rd,$rs,$rt,$bytecount */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), ',', OP (BYTECOUNT), 0 } }, + & ifmt_rbi, { 0x48000100 } + }, +/* pkrlic $rd,$rs,$rt,$bytecount */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), ',', OP (BYTECOUNT), 0 } }, + & ifmt_rbi, { 0x48000300 } + }, +/* pkrla $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_add, { 0x4c000028 } + }, +/* pkrlau $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_add, { 0x4c000029 } + }, +/* pkrlah $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_add, { 0x4c00002a } + }, +/* pkrlac $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_add, { 0x4c00002b } + }, +/* lock $rd,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), 0 } }, + & ifmt_chkhdr, { 0x4c000001 } + }, +/* unlk $rd,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), 0 } }, + & ifmt_chkhdr, { 0x4c000003 } + }, +/* swrd $rd,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), 0 } }, + & ifmt_chkhdr, { 0x4c000004 } + }, +/* swrdl $rd,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), 0 } }, + & ifmt_chkhdr, { 0x4c000005 } + }, +/* swwr $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_add, { 0x4c000006 } + }, +/* swwru $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_add, { 0x4c000007 } + }, +/* dwrd $rd,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), 0 } }, + & ifmt_chkhdr, { 0x4c00000c } + }, +/* dwrdl $rd,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), 0 } }, + & ifmt_chkhdr, { 0x4c00000d } + }, +/* cam36 $rd,$rt,${cam-z},${cam-y} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), ',', OP (CAM_Z), ',', OP (CAM_Y), 0 } }, + & ifmt_cam36, { 0x4c000400 } + }, +/* cam72 $rd,$rt,${cam-y},${cam-z} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), ',', OP (CAM_Y), ',', OP (CAM_Z), 0 } }, + & ifmt_cam36, { 0x4c000440 } + }, +/* cam144 $rd,$rt,${cam-y},${cam-z} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), ',', OP (CAM_Y), ',', OP (CAM_Z), 0 } }, + & ifmt_cam36, { 0x4c000480 } + }, +/* cam288 $rd,$rt,${cam-y},${cam-z} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), ',', OP (CAM_Y), ',', OP (CAM_Z), 0 } }, + & ifmt_cam36, { 0x4c0004c0 } + }, +/* cm32and $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_cm32and, { 0x4c0000ab } + }, +/* cm32andn $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_cm32and, { 0x4c0000a3 } + }, +/* cm32or $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_cm32and, { 0x4c0000aa } + }, +/* cm32ra $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_add, { 0x4c0000b0 } + }, +/* cm32rd $rd,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), 0 } }, + & ifmt_cm32rd, { 0x4c0000a1 } + }, +/* cm32ri $rd,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), 0 } }, + & ifmt_cm32rd, { 0x4c0000a4 } + }, +/* cm32rs $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_add, { 0x4c0000a0 } + }, +/* cm32sa $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_cm32and, { 0x4c0000b8 } + }, +/* cm32sd $rd,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), 0 } }, + & ifmt_cm32rd, { 0x4c0000a9 } + }, +/* cm32si $rd,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), 0 } }, + & ifmt_cm32rd, { 0x4c0000ac } + }, +/* cm32ss $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_cm32and, { 0x4c0000a8 } + }, +/* cm32xor $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_cm32and, { 0x4c0000a2 } + }, +/* cm64clr $rd,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), 0 } }, + & ifmt_cm32rd, { 0x4c000085 } + }, +/* cm64ra $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_cm32and, { 0x4c000090 } + }, +/* cm64rd $rd,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), 0 } }, + & ifmt_cm32rd, { 0x4c000081 } + }, +/* cm64ri $rd,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), 0 } }, + & ifmt_cm32rd, { 0x4c000084 } + }, +/* cm64ria2 $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_cm32and, { 0x4c000094 } + }, +/* cm64rs $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_cm32and, { 0x4c000080 } + }, +/* cm64sa $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_cm32and, { 0x4c000098 } + }, +/* cm64sd $rd,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), 0 } }, + & ifmt_cm32rd, { 0x4c000089 } + }, +/* cm64si $rd,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), 0 } }, + & ifmt_cm32rd, { 0x4c00008c } + }, +/* cm64sia2 $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_cm32and, { 0x4c00009c } + }, +/* cm64ss $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_cm32and, { 0x4c000088 } + }, +/* cm128ria2 $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_cm32and, { 0x4c000095 } + }, +/* cm128ria3 $rd,$rs,$rt,${cm-3z} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), ',', OP (CM_3Z), 0 } }, + & ifmt_cm128ria3, { 0x4c000090 } + }, +/* cm128ria4 $rd,$rs,$rt,${cm-4z} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), ',', OP (CM_4Z), 0 } }, + & ifmt_cm128ria4, { 0x4c0000b0 } + }, +/* cm128sia2 $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_cm32and, { 0x4c00009d } + }, +/* cm128sia3 $rd,$rs,$rt,${cm-3z} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), ',', OP (CM_3Z), 0 } }, + & ifmt_cm128ria3, { 0x4c000098 } + }, +/* cm128sia4 $rd,$rs,$rt,${cm-4z} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), ',', OP (CM_4Z), 0 } }, + & ifmt_cm128ria4, { 0x4c0000b8 } + }, +/* cm128vsa $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_cm32and, { 0x4c0000a6 } + }, +/* cfc $rd,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), 0 } }, + & ifmt_chkhdr, { 0x4c000000 } + }, +/* ctc $rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (RT), 0 } }, + & ifmt_ctc, { 0x4c000002 } + }, +}; + +#undef A +#undef OPERAND +#undef MNEM +#undef OP + +/* Formats for ALIAS macro-insns. */ + +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define F(f) & iq2000_cgen_ifld_table[IQ2000_##f] +#else +#define F(f) & iq2000_cgen_ifld_table[IQ2000_/**/f] +#endif +static const CGEN_IFMT ifmt_nop = { + 32, 32, 0xffffffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_li = { + 32, 32, 0xfc1f0000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_IMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_move = { + 32, 32, 0xffe007ff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_lb_base_0 = { + 32, 32, 0xffe00000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_IMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_lbu_base_0 = { + 32, 32, 0xffe00000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_IMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_lh_base_0 = { + 32, 32, 0xffe00000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_IMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_lw_base_0 = { + 32, 32, 0xffe00000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_IMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_add = { + 32, 32, 0xfc000000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_IMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_addu = { + 32, 32, 0xfc000000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_IMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_and = { + 32, 32, 0xfc000000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_IMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_j = { + 32, 32, 0xfc1fffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_or = { + 32, 32, 0xfc000000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_IMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_sll = { + 32, 32, 0xfc0007ff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_slt = { + 32, 32, 0xfc000000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_IMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_sltu = { + 32, 32, 0xfc000000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_IMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_sra = { + 32, 32, 0xfc0007ff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_srl = { + 32, 32, 0xfc0007ff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_not = { + 32, 32, 0xffe007ff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subi = { + 32, 32, 0xfc000000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_IMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_sub = { + 32, 32, 0xfc000000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_IMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_subu = { + 32, 32, 0xfc000000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_IMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sb_base_0 = { + 32, 32, 0xffe00000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_IMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sh_base_0 = { + 32, 32, 0xffe00000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_IMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sw_base_0 = { + 32, 32, 0xffe00000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_IMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_xor = { + 32, 32, 0xfc000000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_IMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldw_base_0 = { + 32, 32, 0xffe00000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_IMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sdw_base_0 = { + 32, 32, 0xffe00000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_IMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_avail = { + 32, 32, 0xffffffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cam36 = { + 32, 32, 0xffe007c7, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP_10) }, { F (F_CAM_Z) }, { F (F_CAM_Y) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cam72 = { + 32, 32, 0xffe007c7, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP_10) }, { F (F_CAM_Z) }, { F (F_CAM_Y) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cam144 = { + 32, 32, 0xffe007c7, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP_10) }, { F (F_CAM_Z) }, { F (F_CAM_Y) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cam288 = { + 32, 32, 0xffe007c7, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP_10) }, { F (F_CAM_Z) }, { F (F_CAM_Y) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm32read = { + 32, 32, 0xffe007ff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm64read = { + 32, 32, 0xffe007ff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm32mlog = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm32and = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm32andn = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm32or = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm32ra = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm32rd = { + 32, 32, 0xffe0ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm32ri = { + 32, 32, 0xffe0ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm32rs = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm32sa = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm32sd = { + 32, 32, 0xffe0ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm32si = { + 32, 32, 0xffe0ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm32ss = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm32xor = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm64clr = { + 32, 32, 0xffe0ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm64ra = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm64rd = { + 32, 32, 0xffe0ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm64ri = { + 32, 32, 0xffe0ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm64ria2 = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm64rs = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm64sa = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm64sd = { + 32, 32, 0xffe0ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm64si = { + 32, 32, 0xffe0ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm64sia2 = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm64ss = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm128ria2 = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm128ria3 = { + 32, 32, 0xfc00fffc, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_CM_4FUNC) }, { F (F_CM_3Z) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm128ria4 = { + 32, 32, 0xfc00fff8, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_CM_3FUNC) }, { F (F_CM_4Z) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm128sia2 = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm128sia3 = { + 32, 32, 0xfc00fffc, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_CM_4FUNC) }, { F (F_CM_3Z) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm128sia4 = { + 32, 32, 0xfc00fff8, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_CM_3FUNC) }, { F (F_CM_4Z) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cmphdr = { + 32, 32, 0xffffffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_dbd = { + 32, 32, 0xffe007ff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m2_dbd = { + 32, 32, 0xffe0ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_dpwt = { + 32, 32, 0xfc1fffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_free = { + 32, 32, 0xfc1fffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_lock = { + 32, 32, 0xffe0ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_pkrla = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_pkrlac = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_pkrlah = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_pkrlau = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_pkrli = { + 32, 32, 0xfc00ff00, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_BYTECOUNT) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_pkrlic = { + 32, 32, 0xfc00ff00, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_BYTECOUNT) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_pkrlih = { + 32, 32, 0xfc00ff00, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_BYTECOUNT) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_pkrliu = { + 32, 32, 0xfc00ff00, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_BYTECOUNT) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_rba = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_rbal = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_rbar = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_rbi = { + 32, 32, 0xfc00ff00, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_BYTECOUNT) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_rbil = { + 32, 32, 0xfc00ff00, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_BYTECOUNT) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_rbir = { + 32, 32, 0xfc00ff00, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_BYTECOUNT) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_swwr = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_swwru = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_tstod = { + 32, 32, 0xfc1fffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_unlk = { + 32, 32, 0xffe0ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_wba = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_wbac = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_wbau = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_wbi = { + 32, 32, 0xfc00ff00, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_BYTECOUNT) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_wbic = { + 32, 32, 0xfc00ff00, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_BYTECOUNT) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_wbiu = { + 32, 32, 0xfc00ff00, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_BYTECOUNT) }, { 0 } } +}; + +#undef F + +/* Each non-simple macro entry points to an array of expansion possibilities. */ + +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define A(a) (1 << CGEN_INSN_##a) +#else +#define A(a) (1 << CGEN_INSN_/**/a) +#endif +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define OPERAND(op) IQ2000_OPERAND_##op +#else +#define OPERAND(op) IQ2000_OPERAND_/**/op +#endif +#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */ +#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) + +/* The macro instruction table. */ + +static const CGEN_IBASE iq2000_cgen_macro_insn_table[] = +{ +/* nop */ + { + -1, "nop", "nop", 32, + { 0|A(ALIAS), { (1<macro_insn_table.init_entries = insns; + cd->macro_insn_table.entry_size = sizeof (CGEN_IBASE); + cd->macro_insn_table.num_init_entries = num_macros; + + oc = & iq2000_cgen_insn_opcode_table[0]; + insns = (CGEN_INSN *) cd->insn_table.init_entries; + for (i = 0; i < MAX_INSNS; ++i) + { + insns[i].opcode = &oc[i]; + iq2000_cgen_build_insn_regex (& insns[i]); + } + + cd->sizeof_fields = sizeof (CGEN_FIELDS); + cd->set_fields_bitsize = set_fields_bitsize; + + cd->asm_hash_p = asm_hash_insn_p; + cd->asm_hash = asm_hash_insn; + cd->asm_hash_size = CGEN_ASM_HASH_SIZE; + + cd->dis_hash_p = dis_hash_insn_p; + cd->dis_hash = dis_hash_insn; + cd->dis_hash_size = CGEN_DIS_HASH_SIZE; +} diff --git a/opcodes/iq2000-opc.h b/opcodes/iq2000-opc.h new file mode 100644 index 0000000..1242cea --- /dev/null +++ b/opcodes/iq2000-opc.h @@ -0,0 +1,181 @@ +/* Instruction opcode header for iq2000. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +*/ + +#ifndef IQ2000_OPC_H +#define IQ2000_OPC_H + +/* -- opc.h */ + +/* Allows reason codes to be output when assembler errors occur. */ +#define CGEN_VERBOSE_ASSEMBLER_ERRORS + +/* Override disassembly hashing - there are variable bits in the top + byte of these instructions. */ +#define CGEN_DIS_HASH_SIZE 8 +#define CGEN_DIS_HASH(buf,value) (((* (unsigned char*) (buf)) >> 6) % CGEN_DIS_HASH_SIZE) + +/* following activates check beyond hashing since some iq2000 and iq10 + instructions have same mnemonics but different functionality. */ +#define CGEN_VALIDATE_INSN_SUPPORTED + +extern int iq2000_cgen_insn_supported (CGEN_CPU_DESC cd, CGEN_INSN *insn); + +/* -- asm.c */ +/* Enum declaration for iq2000 instruction types. */ +typedef enum cgen_insn_type { + IQ2000_INSN_INVALID, IQ2000_INSN_ADD2, IQ2000_INSN_ADD, IQ2000_INSN_ADDI2 + , IQ2000_INSN_ADDI, IQ2000_INSN_ADDIU2, IQ2000_INSN_ADDIU, IQ2000_INSN_ADDU2 + , IQ2000_INSN_ADDU, IQ2000_INSN_ADO162, IQ2000_INSN_ADO16, IQ2000_INSN_AND2 + , IQ2000_INSN_AND, IQ2000_INSN_ANDI2, IQ2000_INSN_ANDI, IQ2000_INSN_ANDOI2 + , IQ2000_INSN_ANDOI, IQ2000_INSN_NOR2, IQ2000_INSN_NOR, IQ2000_INSN_OR2 + , IQ2000_INSN_OR, IQ2000_INSN_ORI2, IQ2000_INSN_ORI, IQ2000_INSN_RAM + , IQ2000_INSN_SLL, IQ2000_INSN_SLLV2, IQ2000_INSN_SLLV, IQ2000_INSN_SLMV2 + , IQ2000_INSN_SLMV, IQ2000_INSN_SLT2, IQ2000_INSN_SLT, IQ2000_INSN_SLTI2 + , IQ2000_INSN_SLTI, IQ2000_INSN_SLTIU2, IQ2000_INSN_SLTIU, IQ2000_INSN_SLTU2 + , IQ2000_INSN_SLTU, IQ2000_INSN_SRA2, IQ2000_INSN_SRA, IQ2000_INSN_SRAV2 + , IQ2000_INSN_SRAV, IQ2000_INSN_SRL, IQ2000_INSN_SRLV2, IQ2000_INSN_SRLV + , IQ2000_INSN_SRMV2, IQ2000_INSN_SRMV, IQ2000_INSN_SUB2, IQ2000_INSN_SUB + , IQ2000_INSN_SUBU2, IQ2000_INSN_SUBU, IQ2000_INSN_XOR2, IQ2000_INSN_XOR + , IQ2000_INSN_XORI2, IQ2000_INSN_XORI, IQ2000_INSN_BBI, IQ2000_INSN_BBIN + , IQ2000_INSN_BBV, IQ2000_INSN_BBVN, IQ2000_INSN_BEQ, IQ2000_INSN_BEQL + , IQ2000_INSN_BGEZ, IQ2000_INSN_BGEZAL, IQ2000_INSN_BGEZALL, IQ2000_INSN_BGEZL + , IQ2000_INSN_BLTZ, IQ2000_INSN_BLTZL, IQ2000_INSN_BLTZAL, IQ2000_INSN_BLTZALL + , IQ2000_INSN_BMB0, IQ2000_INSN_BMB1, IQ2000_INSN_BMB2, IQ2000_INSN_BMB3 + , IQ2000_INSN_BNE, IQ2000_INSN_BNEL, IQ2000_INSN_JALR, IQ2000_INSN_JR + , IQ2000_INSN_LB, IQ2000_INSN_LBU, IQ2000_INSN_LH, IQ2000_INSN_LHU + , IQ2000_INSN_LUI, IQ2000_INSN_LW, IQ2000_INSN_SB, IQ2000_INSN_SH + , IQ2000_INSN_SW, IQ2000_INSN_BREAK, IQ2000_INSN_SYSCALL, IQ2000_INSN_ANDOUI + , IQ2000_INSN_ANDOUI2, IQ2000_INSN_ORUI2, IQ2000_INSN_ORUI, IQ2000_INSN_BGTZ + , IQ2000_INSN_BGTZL, IQ2000_INSN_BLEZ, IQ2000_INSN_BLEZL, IQ2000_INSN_MRGB + , IQ2000_INSN_MRGB2, IQ2000_INSN_BCTXT, IQ2000_INSN_BC0F, IQ2000_INSN_BC0FL + , IQ2000_INSN_BC3F, IQ2000_INSN_BC3FL, IQ2000_INSN_BC0T, IQ2000_INSN_BC0TL + , IQ2000_INSN_BC3T, IQ2000_INSN_BC3TL, IQ2000_INSN_CFC0, IQ2000_INSN_CFC1 + , IQ2000_INSN_CFC2, IQ2000_INSN_CFC3, IQ2000_INSN_CHKHDR, IQ2000_INSN_CTC0 + , IQ2000_INSN_CTC1, IQ2000_INSN_CTC2, IQ2000_INSN_CTC3, IQ2000_INSN_JCR + , IQ2000_INSN_LUC32, IQ2000_INSN_LUC32L, IQ2000_INSN_LUC64, IQ2000_INSN_LUC64L + , IQ2000_INSN_LUK, IQ2000_INSN_LULCK, IQ2000_INSN_LUM32, IQ2000_INSN_LUM32L + , IQ2000_INSN_LUM64, IQ2000_INSN_LUM64L, IQ2000_INSN_LUR, IQ2000_INSN_LURL + , IQ2000_INSN_LUULCK, IQ2000_INSN_MFC0, IQ2000_INSN_MFC1, IQ2000_INSN_MFC2 + , IQ2000_INSN_MFC3, IQ2000_INSN_MTC0, IQ2000_INSN_MTC1, IQ2000_INSN_MTC2 + , IQ2000_INSN_MTC3, IQ2000_INSN_PKRL, IQ2000_INSN_PKRLR1, IQ2000_INSN_PKRLR30 + , IQ2000_INSN_RB, IQ2000_INSN_RBR1, IQ2000_INSN_RBR30, IQ2000_INSN_RFE + , IQ2000_INSN_RX, IQ2000_INSN_RXR1, IQ2000_INSN_RXR30, IQ2000_INSN_SLEEP + , IQ2000_INSN_SRRD, IQ2000_INSN_SRRDL, IQ2000_INSN_SRULCK, IQ2000_INSN_SRWR + , IQ2000_INSN_SRWRU, IQ2000_INSN_TRAPQFL, IQ2000_INSN_TRAPQNE, IQ2000_INSN_TRAPREL + , IQ2000_INSN_WB, IQ2000_INSN_WBU, IQ2000_INSN_WBR1, IQ2000_INSN_WBR1U + , IQ2000_INSN_WBR30, IQ2000_INSN_WBR30U, IQ2000_INSN_WX, IQ2000_INSN_WXU + , IQ2000_INSN_WXR1, IQ2000_INSN_WXR1U, IQ2000_INSN_WXR30, IQ2000_INSN_WXR30U + , IQ2000_INSN_LDW, IQ2000_INSN_SDW, IQ2000_INSN_J, IQ2000_INSN_JAL + , IQ2000_INSN_BMB, IQ2000_INSN_ANDOUI_Q10, IQ2000_INSN_ANDOUI2_Q10, IQ2000_INSN_ORUI_Q10 + , IQ2000_INSN_ORUI2_Q10, IQ2000_INSN_MRGBQ10, IQ2000_INSN_MRGBQ102, IQ2000_INSN_JQ10 + , IQ2000_INSN_JALQ10, IQ2000_INSN_JALQ10_2, IQ2000_INSN_BBIL, IQ2000_INSN_BBINL + , IQ2000_INSN_BBVL, IQ2000_INSN_BBVNL, IQ2000_INSN_BGTZAL, IQ2000_INSN_BGTZALL + , IQ2000_INSN_BLEZAL, IQ2000_INSN_BLEZALL, IQ2000_INSN_BGTZ_Q10, IQ2000_INSN_BGTZL_Q10 + , IQ2000_INSN_BLEZ_Q10, IQ2000_INSN_BLEZL_Q10, IQ2000_INSN_BMB_Q10, IQ2000_INSN_BMBL + , IQ2000_INSN_BRI, IQ2000_INSN_BRV, IQ2000_INSN_BCTX, IQ2000_INSN_YIELD + , IQ2000_INSN_CRC32, IQ2000_INSN_CRC32B, IQ2000_INSN_CNT1S, IQ2000_INSN_AVAIL + , IQ2000_INSN_FREE, IQ2000_INSN_TSTOD, IQ2000_INSN_CMPHDR, IQ2000_INSN_MCID + , IQ2000_INSN_DBA, IQ2000_INSN_DBD, IQ2000_INSN_DPWT, IQ2000_INSN_CHKHDRQ10 + , IQ2000_INSN_RBA, IQ2000_INSN_RBAL, IQ2000_INSN_RBAR, IQ2000_INSN_WBA + , IQ2000_INSN_WBAU, IQ2000_INSN_WBAC, IQ2000_INSN_RBI, IQ2000_INSN_RBIL + , IQ2000_INSN_RBIR, IQ2000_INSN_WBI, IQ2000_INSN_WBIC, IQ2000_INSN_WBIU + , IQ2000_INSN_PKRLI, IQ2000_INSN_PKRLIH, IQ2000_INSN_PKRLIU, IQ2000_INSN_PKRLIC + , IQ2000_INSN_PKRLA, IQ2000_INSN_PKRLAU, IQ2000_INSN_PKRLAH, IQ2000_INSN_PKRLAC + , IQ2000_INSN_LOCK, IQ2000_INSN_UNLK, IQ2000_INSN_SWRD, IQ2000_INSN_SWRDL + , IQ2000_INSN_SWWR, IQ2000_INSN_SWWRU, IQ2000_INSN_DWRD, IQ2000_INSN_DWRDL + , IQ2000_INSN_CAM36, IQ2000_INSN_CAM72, IQ2000_INSN_CAM144, IQ2000_INSN_CAM288 + , IQ2000_INSN_CM32AND, IQ2000_INSN_CM32ANDN, IQ2000_INSN_CM32OR, IQ2000_INSN_CM32RA + , IQ2000_INSN_CM32RD, IQ2000_INSN_CM32RI, IQ2000_INSN_CM32RS, IQ2000_INSN_CM32SA + , IQ2000_INSN_CM32SD, IQ2000_INSN_CM32SI, IQ2000_INSN_CM32SS, IQ2000_INSN_CM32XOR + , IQ2000_INSN_CM64CLR, IQ2000_INSN_CM64RA, IQ2000_INSN_CM64RD, IQ2000_INSN_CM64RI + , IQ2000_INSN_CM64RIA2, IQ2000_INSN_CM64RS, IQ2000_INSN_CM64SA, IQ2000_INSN_CM64SD + , IQ2000_INSN_CM64SI, IQ2000_INSN_CM64SIA2, IQ2000_INSN_CM64SS, IQ2000_INSN_CM128RIA2 + , IQ2000_INSN_CM128RIA3, IQ2000_INSN_CM128RIA4, IQ2000_INSN_CM128SIA2, IQ2000_INSN_CM128SIA3 + , IQ2000_INSN_CM128SIA4, IQ2000_INSN_CM128VSA, IQ2000_INSN_CFC, IQ2000_INSN_CTC +} CGEN_INSN_TYPE; + +/* Index of `invalid' insn place holder. */ +#define CGEN_INSN_INVALID IQ2000_INSN_INVALID + +/* Total number of insns in table. */ +#define MAX_INSNS ((int) IQ2000_INSN_CTC + 1) + +/* This struct records data prior to insertion or after extraction. */ +struct cgen_fields +{ + int length; + long f_nil; + long f_anyof; + long f_opcode; + long f_rs; + long f_rt; + long f_rd; + long f_shamt; + long f_cp_op; + long f_cp_op_10; + long f_cp_grp; + long f_func; + long f_imm; + long f_rd_rs; + long f_rd_rt; + long f_rt_rs; + long f_jtarg; + long f_jtargq10; + long f_offset; + long f_count; + long f_bytecount; + long f_index; + long f_mask; + long f_maskq10; + long f_maskl; + long f_excode; + long f_rsrvd; + long f_10_11; + long f_24_19; + long f_5; + long f_10; + long f_25; + long f_cam_z; + long f_cam_y; + long f_cm_3func; + long f_cm_4func; + long f_cm_3z; + long f_cm_4z; +}; + +#define CGEN_INIT_PARSE(od) \ +{\ +} +#define CGEN_INIT_INSERT(od) \ +{\ +} +#define CGEN_INIT_EXTRACT(od) \ +{\ +} +#define CGEN_INIT_PRINT(od) \ +{\ +} + + +#endif /* IQ2000_OPC_H */ diff --git a/opcodes/msp430-dis.c b/opcodes/msp430-dis.c new file mode 100644 index 0000000..767ffa4 --- /dev/null +++ b/opcodes/msp430-dis.c @@ -0,0 +1,805 @@ +/* Disassemble MSP430 instructions. + Copyright (C) 2002 Free Software Foundation, Inc. + + Contributed by Dmitry Diky + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include +#include +#include +#include + +#include "dis-asm.h" +#include "opintl.h" +#include "libiberty.h" + +#define DASM_SECTION +#include "opcode/msp430.h" +#undef DASM_SECTION + + +static unsigned short msp430dis_opcode + PARAMS ((bfd_vma, disassemble_info *)); +int print_insn_msp430 + PARAMS ((bfd_vma, disassemble_info *)); +int msp430_nooperands + PARAMS ((struct msp430_opcode_s *, bfd_vma, unsigned short, char *, int *)); +int msp430_singleoperand + PARAMS ((disassemble_info *, struct msp430_opcode_s *, bfd_vma, unsigned short, + char *, char *, int *)); +int msp430_doubleoperand + PARAMS ((disassemble_info *, struct msp430_opcode_s *, bfd_vma, unsigned short, + char *, char *, char *, char *, int *)); +int msp430_branchinstr + PARAMS ((disassemble_info *, struct msp430_opcode_s *, bfd_vma, unsigned short, + char *, char *, int *)); + +#define PS(x) (0xffff & (x)) + +static unsigned short +msp430dis_opcode (addr, info) + bfd_vma addr; + disassemble_info *info; +{ + bfd_byte buffer[2]; + int status; + + status = info->read_memory_func (addr, buffer, 2, info); + if (status != 0) + { + info->memory_error_func (status, addr, info); + return -1; + } + return bfd_getl16 (buffer); +} + +int +print_insn_msp430 (addr, info) + bfd_vma addr; + disassemble_info *info; +{ + void *stream = info->stream; + fprintf_ftype prin = info->fprintf_func; + struct msp430_opcode_s *opcode; + char op1[32], op2[32], comm1[64], comm2[64]; + int cmd_len = 0; + unsigned short insn; + int cycles = 0; + char *bc = ""; + char dinfo[32]; /* Debug purposes. */ + + insn = msp430dis_opcode (addr, info); + sprintf (dinfo, "0x%04x", insn); + + if (((int) addr & 0xffff) > 0xffdf) + { + (*prin) (stream, "interrupt service routine at 0x%04x", 0xffff & insn); + return 2; + } + + *comm1 = 0; + *comm2 = 0; + + for (opcode = msp430_opcodes; opcode->name; opcode++) + { + if ((insn & opcode->bin_mask) == opcode->bin_opcode + && opcode->bin_opcode != 0x9300) + { + *op1 = 0; + *op2 = 0; + *comm1 = 0; + *comm2 = 0; + + /* r0 as destination. Ad should be zero. */ + if (opcode->insn_opnumb == 3 && (insn & 0x000f) == 0 + && (0x0080 & insn) == 0) + { + cmd_len = + msp430_branchinstr (info, opcode, addr, insn, op1, comm1, + &cycles); + if (cmd_len) + break; + } + + switch (opcode->insn_opnumb) + { + case 0: + cmd_len = msp430_nooperands (opcode, addr, insn, comm1, &cycles); + break; + case 2: + cmd_len = + msp430_doubleoperand (info, opcode, addr, insn, op1, op2, + comm1, comm2, &cycles); + if (insn & BYTE_OPERATION) + bc = ".b"; + break; + case 1: + cmd_len = + msp430_singleoperand (info, opcode, addr, insn, op1, comm1, + &cycles); + if (insn & BYTE_OPERATION && opcode->fmt != 3) + bc = ".b"; + break; + default: + break; + } + } + + if (cmd_len) + break; + } + + dinfo[5] = 0; + + if (cmd_len < 1) + { + /* Unknown opcode, or invalid combination of operands. */ + (*prin) (stream, ".word 0x%04x; ????", PS (insn)); + return 2; + } + + (*prin) (stream, "%s%s", opcode->name, bc); + + if (*op1) + (*prin) (stream, "\t%s", op1); + if (*op2) + (*prin) (stream, ","); + + if (strlen (op1) < 7) + (*prin) (stream, "\t"); + if (!strlen (op1)) + (*prin) (stream, "\t"); + + if (*op2) + (*prin) (stream, "%s", op2); + if (strlen (op2) < 8) + (*prin) (stream, "\t"); + + if (*comm1 || *comm2) + (*prin) (stream, ";"); + else if (cycles) + { + if (*op2) + (*prin) (stream, ";"); + else + { + if (strlen (op1) < 7) + (*prin) (stream, ";"); + else + (*prin) (stream, "\t;"); + } + } + if (*comm1) + (*prin) (stream, "%s", comm1); + if (*comm1 && *comm2) + (*prin) (stream, ","); + if (*comm2) + (*prin) (stream, " %s", comm2); + return cmd_len; +} + +int +msp430_nooperands (opcode, addr, insn, comm, cycles) + struct msp430_opcode_s *opcode; + bfd_vma addr ATTRIBUTE_UNUSED; + unsigned short insn ATTRIBUTE_UNUSED; + char *comm; + int *cycles; +{ + /* Pop with constant. */ + if (insn == 0x43b2) + return 0; + if (insn == opcode->bin_opcode) + return 2; + + if (opcode->fmt == 0) + { + if ((insn & 0x0f00) != 3 || (insn & 0x0f00) != 2) + return 0; + + strcpy (comm, "emulated..."); + *cycles = 1; + } + else + { + strcpy (comm, "return from interupt"); + *cycles = 5; + } + + return 2; +} + + +int +msp430_singleoperand (info, opcode, addr, insn, op, comm, cycles) + disassemble_info *info; + struct msp430_opcode_s *opcode; + bfd_vma addr; + unsigned short insn; + char *op; + char *comm; + int *cycles; +{ + int regs = 0, regd = 0; + int ad = 0, as = 0; + int where = 0; + int cmd_len = 2; + short dst = 0; + + regd = insn & 0x0f; + regs = (insn & 0x0f00) >> 8; + as = (insn & 0x0030) >> 4; + ad = (insn & 0x0080) >> 7; + + switch (opcode->fmt) + { + case 0: /* Emulated work with dst register. */ + if (regs != 2 && regs != 3 && regs != 1) + return 0; + + /* Check if not clr insn. */ + if (opcode->bin_opcode == 0x4300 && (ad || as)) + return 0; + + /* Check if really inc, incd insns. */ + if ((opcode->bin_opcode & 0xff00) == 0x5300 && as == 3) + return 0; + + if (ad == 0) + { + *cycles = 1; + + /* Register. */ + if (regd == 0) + { + *cycles += 1; + sprintf (op, "r0"); + } + else if (regd == 1) + sprintf (op, "r1"); + + else if (regd == 2) + sprintf (op, "r2"); + + else + sprintf (op, "r%d", regd); + } + else /* ad == 1 msp430dis_opcode. */ + { + if (regd == 0) + { + /* PC relative. */ + dst = msp430dis_opcode (addr + 2, info); + cmd_len += 2; + *cycles = 4; + sprintf (op, "0x%04x", dst); + sprintf (comm, "PC rel. abs addr 0x%04x", + PS ((short) (addr + 2) + dst)); + } + else if (regd == 2) + { + /* Absolute. */ + dst = msp430dis_opcode (addr + 2, info); + cmd_len += 2; + *cycles = 4; + sprintf (op, "&0x%04x", PS (dst)); + } + else + { + dst = msp430dis_opcode (addr + 2, info); + cmd_len += 2; + *cycles = 4; + sprintf (op, "%d(r%d)", dst, regd); + } + } + break; + + case 2: /* rrc, push, call, swpb, rra, sxt, push, call, reti etc... */ + + if (as == 0) + { + if (regd == 3) + { + /* Constsnts. */ + sprintf (op, "#0"); + sprintf (comm, "r3 As==00"); + } + else + { + /* Register. */ + sprintf (op, "r%d", regd); + } + *cycles = 1; + } + else if (as == 2) + { + *cycles = 1; + if (regd == 2) + { + sprintf (op, "#4"); + sprintf (comm, "r2 As==10"); + } + else if (regd == 3) + { + sprintf (op, "#2"); + sprintf (comm, "r3 As==10"); + } + else + { + *cycles = 3; + /* Indexed register mode @Rn. */ + sprintf (op, "@r%d", regd); + } + } + else if (as == 3) + { + *cycles = 1; + if (regd == 2) + { + sprintf (op, "#8"); + sprintf (comm, "r2 As==11"); + } + else if (regd == 3) + { + sprintf (op, "#-1"); + sprintf (comm, "r3 As==11"); + } + else if (regd == 0) + { + *cycles = 3; + /* absolute. @pc+ */ + dst = msp430dis_opcode (addr + 2, info); + cmd_len += 2; + sprintf (op, "#%d", dst); + sprintf (comm, "#0x%04x", PS (dst)); + } + else + { + *cycles = 3; + sprintf (op, "@r%d+", regd); + } + } + else if (as == 1) + { + *cycles = 4; + if (regd == 0) + { + /* PC relative. */ + dst = msp430dis_opcode (addr + 2, info); + cmd_len += 2; + sprintf (op, "0x%04x", PS (dst)); + sprintf (comm, "PC rel. 0x%04x", + PS ((short) addr + 2 + dst)); + } + else if (regd == 2) + { + /* Absolute. */ + dst = msp430dis_opcode (addr + 2, info); + cmd_len += 2; + sprintf (op, "&0x%04x", PS (dst)); + } + else if (regd == 3) + { + *cycles = 1; + sprintf (op, "#1"); + sprintf (comm, "r3 As==01"); + } + else + { + /* Indexd. */ + dst = msp430dis_opcode (addr + 2, info); + cmd_len += 2; + sprintf (op, "%d(r%d)", dst, regd); + } + } + break; + + case 3: /* Jumps. */ + where = insn & 0x03ff; + if (where & 0x200) + where |= ~0x03ff; + if (where > 512 || where < -511) + return 0; + + where *= 2; + sprintf (op, "$%+-8d", where + 2); + sprintf (comm, "abs 0x%x", PS ((short) (addr) + 2 + where)); + *cycles = 2; + return 2; + break; + default: + cmd_len = 0; + } + + return cmd_len; +} + +int +msp430_doubleoperand (info, opcode, addr, insn, op1, op2, comm1, comm2, cycles) + disassemble_info *info; + struct msp430_opcode_s *opcode; + bfd_vma addr; + unsigned short insn; + char *op1, *op2; + char *comm1, *comm2; + int *cycles; +{ + int regs = 0, regd = 0; + int ad = 0, as = 0; + int cmd_len = 2; + short dst = 0; + + regd = insn & 0x0f; + regs = (insn & 0x0f00) >> 8; + as = (insn & 0x0030) >> 4; + ad = (insn & 0x0080) >> 7; + + if (opcode->fmt == 0) + { + /* Special case: rla and rlc are the only 2 emulated instructions that + fall into two operand instructions. */ + /* With dst, there are only: + Rm Register, + x(Rm) Indexed, + 0xXXXX Relative, + &0xXXXX Absolute + emulated_ins dst + basic_ins dst, dst. */ + + if (regd != regs || as != ad) + return 0; /* May be 'data' section. */ + + if (ad == 0) + { + /* Register mode. */ + if (regd == 3) + { + strcpy (comm1, "Illegal as emulation instr"); + return -1; + } + + sprintf (op1, "r%d", regd); + *cycles = 1; + } + else /* ad == 1 */ + { + if (regd == 0) + { + /* PC relative, Symbolic. */ + dst = msp430dis_opcode (addr + 2, info); + cmd_len += 4; + *cycles = 6; + sprintf (op1, "0x%04x", PS (dst)); + sprintf (comm1, "PC rel. 0x%04x", + PS ((short) addr + 2 + dst)); + + } + else if (regd == 2) + { + /* Absolute. */ + dst = msp430dis_opcode (addr + 2, info); + cmd_len += 4; + *cycles = 6; + sprintf (op1, "&0x%04x", PS (dst)); + } + else + { + /* Indexed. */ + dst = msp430dis_opcode (addr + 2, info); + cmd_len += 4; + *cycles = 6; + sprintf (op1, "%d(r%d)", dst, regd); + } + } + + *op2 = 0; + *comm2 = 0; + return cmd_len; + } + + /* Two operands exactly. */ + if (ad == 0 && regd == 3) + { + /* R2/R3 are illegal as dest: may be data section. */ + strcpy (comm1, "Illegal as 2-op instr"); + return -1; + } + + /* Source. */ + if (as == 0) + { + *cycles = 1; + if (regs == 3) + { + /* Constsnts. */ + sprintf (op1, "#0"); + sprintf (comm1, "r3 As==00"); + } + else + { + /* Register. */ + sprintf (op1, "r%d", regs); + } + } + else if (as == 2) + { + *cycles = 1; + + if (regs == 2) + { + sprintf (op1, "#4"); + sprintf (comm1, "r2 As==10"); + } + else if (regs == 3) + { + sprintf (op1, "#2"); + sprintf (comm1, "r3 As==10"); + } + else + { + *cycles = 2; + + /* Indexed register mode @Rn. */ + sprintf (op1, "@r%d", regs); + } + if (!regs) + *cycles = 3; + } + else if (as == 3) + { + if (regs == 2) + { + sprintf (op1, "#8"); + sprintf (comm1, "r2 As==11"); + *cycles = 1; + } + else if (regs == 3) + { + sprintf (op1, "#-1"); + sprintf (comm1, "r3 As==11"); + *cycles = 1; + } + else if (regs == 0) + { + *cycles = 3; + /* Absolute. @pc+ */ + dst = msp430dis_opcode (addr + 2, info); + cmd_len += 2; + sprintf (op1, "#%d", dst); + sprintf (comm1, "#0x%04x", PS (dst)); + } + else + { + *cycles = 2; + sprintf (op1, "@r%d+", regs); + } + } + else if (as == 1) + { + if (regs == 0) + { + *cycles = 4; + /* PC relative. */ + dst = msp430dis_opcode (addr + 2, info); + cmd_len += 2; + sprintf (op1, "0x%04x", PS (dst)); + sprintf (comm1, "PC rel. 0x%04x", + PS ((short) addr + 2 + dst)); + } + else if (regs == 2) + { + *cycles = 2; + /* Absolute. */ + dst = msp430dis_opcode (addr + 2, info); + cmd_len += 2; + sprintf (op1, "&0x%04x", PS (dst)); + sprintf (comm1, "0x%04x", PS (dst)); + } + else if (regs == 3) + { + *cycles = 1; + sprintf (op1, "#1"); + sprintf (comm1, "r3 As==01"); + } + else + { + *cycles = 3; + /* Indexed. */ + dst = msp430dis_opcode (addr + 2, info); + cmd_len += 2; + sprintf (op1, "%d(r%d)", dst, regs); + } + } + + /* Destination. Special care needed on addr + XXXX. */ + + if (ad == 0) + { + /* Register. */ + if (regd == 0) + { + *cycles += 1; + sprintf (op2, "r0"); + } + else if (regd == 1) + sprintf (op2, "r1"); + + else if (regd == 2) + sprintf (op2, "r2"); + + else + sprintf (op2, "r%d", regd); + } + else /* ad == 1. */ + { + * cycles += 3; + + if (regd == 0) + { + /* PC relative. */ + *cycles += 1; + dst = msp430dis_opcode (addr + cmd_len, info); + sprintf (op2, "0x%04x", PS (dst)); + sprintf (comm2, "PC rel. 0x%04x", + PS ((short) addr + cmd_len + dst)); + cmd_len += 2; + } + else if (regd == 2) + { + /* Absolute. */ + dst = msp430dis_opcode (addr + cmd_len, info); + cmd_len += 2; + sprintf (op2, "&0x%04x", PS (dst)); + } + else + { + dst = msp430dis_opcode (addr + cmd_len, info); + cmd_len += 2; + sprintf (op2, "%d(r%d)", dst, regd); + } + } + + return cmd_len; +} + + +int +msp430_branchinstr (info, opcode, addr, insn, op1, comm1, cycles) + disassemble_info *info; + struct msp430_opcode_s *opcode ATTRIBUTE_UNUSED; + bfd_vma addr ATTRIBUTE_UNUSED; + unsigned short insn; + char *op1; + char *comm1; + int *cycles; +{ + int regs = 0, regd = 0; + int ad = 0, as = 0; + int cmd_len = 2; + short dst = 0; + + regd = insn & 0x0f; + regs = (insn & 0x0f00) >> 8; + as = (insn & 0x0030) >> 4; + ad = (insn & 0x0080) >> 7; + + if (regd != 0) /* Destination register is not a PC. */ + return 0; + + /* dst is a source register. */ + if (as == 0) + { + /* Constants. */ + if (regs == 3) + { + *cycles = 1; + sprintf (op1, "#0"); + sprintf (comm1, "r3 As==00"); + } + else + { + /* Register. */ + *cycles = 1; + sprintf (op1, "r%d", regs); + } + } + else if (as == 2) + { + if (regs == 2) + { + *cycles = 2; + sprintf (op1, "#4"); + sprintf (comm1, "r2 As==10"); + } + else if (regs == 3) + { + *cycles = 1; + sprintf (op1, "#2"); + sprintf (comm1, "r3 As==10"); + } + else + { + /* Indexed register mode @Rn. */ + *cycles = 2; + sprintf (op1, "@r%d", regs); + } + } + else if (as == 3) + { + if (regs == 2) + { + *cycles = 1; + sprintf (op1, "#8"); + sprintf (comm1, "r2 As==11"); + } + else if (regs == 3) + { + *cycles = 1; + sprintf (op1, "#-1"); + sprintf (comm1, "r3 As==11"); + } + else if (regs == 0) + { + /* Absolute. @pc+ */ + *cycles = 3; + dst = msp430dis_opcode (addr + 2, info); + cmd_len += 2; + sprintf (op1, "#0x%04x", PS (dst)); + } + else + { + *cycles = 2; + sprintf (op1, "@r%d+", regs); + } + } + else if (as == 1) + { + * cycles = 3; + + if (regs == 0) + { + /* PC relative. */ + dst = msp430dis_opcode (addr + 2, info); + cmd_len += 2; + (*cycles)++; + sprintf (op1, "0x%04x", PS (dst)); + sprintf (comm1, "PC rel. 0x%04x", + PS ((short) addr + 2 + dst)); + } + else if (regs == 2) + { + /* Absolute. */ + dst = msp430dis_opcode (addr + 2, info); + cmd_len += 2; + sprintf (op1, "&0x%04x", PS (dst)); + } + else if (regs == 3) + { + (*cycles)--; + sprintf (op1, "#1"); + sprintf (comm1, "r3 As==01"); + } + else + { + /* Indexd. */ + dst = msp430dis_opcode (addr + 2, info); + cmd_len += 2; + sprintf (op1, "%d(r%d)", dst, regs); + } + } + + return cmd_len; +} diff --git a/opcodes/po/nl.po b/opcodes/po/nl.po new file mode 100644 index 0000000..d4247c1 --- /dev/null +++ b/opcodes/po/nl.po @@ -0,0 +1,809 @@ +# Dutch messages for the Opcodes Library. +# Copyright (C) 1999, 2002, 2003 Free Software Foundation, Inc. +# This file is distributed under the same license as the Opcodes package. +# Tim Van Holder , 1999, 2002, 2003. +# +msgid "" +msgstr "" +"Project-Id-Version: opcodes 2.14rel030712\n" +"POT-Creation-Date: 2003-07-11 13:56+0930\n" +"PO-Revision-Date: 2003-07-18 17:17+0200\n" +"Last-Translator: Tim Van Holder \n" +"Language-Team: Dutch \n" +"MIME-Version: 1.0\n" +"Content-Type: text/plain; charset=iso-8859-1\n" +"Content-Transfer-Encoding: 8-bit\n" +"Plural-Forms: nplurals=2; plural=(n != 1);\n" + +# misschien 'branch' vertalen (vertakking?) +# en unaligned vertalen als 'niet uitgelijnd'? +#: alpha-opc.c:335 +msgid "branch operand unaligned" +msgstr "branch-operand niet uitgelijnd" + +#: alpha-opc.c:358 alpha-opc.c:380 +msgid "jump hint unaligned" +msgstr "jump-hint niet uitgelijnd" + +#: arc-dis.c:52 +msgid "Illegal limm reference in last instruction!\n" +msgstr "Ongeldige limm-verwijzing in de laatste instructie!\n" + +#: arm-dis.c:554 +msgid "" +msgstr "" + +# Hoort set bij 'name', of bij 'register name'? +#: arm-dis.c:1162 +#, c-format +msgid "Unrecognised register name set: %s\n" +msgstr "Registernaam-verzameling niet herkend: %s\n" + +#: arm-dis.c:1169 +#, c-format +msgid "Unrecognised disassembler option: %s\n" +msgstr "Disassembler-optie niet herkend: %s\n" + +#: arm-dis.c:1343 +msgid "" +"\n" +"The following ARM specific disassembler options are supported for use with\n" +"the -M switch:\n" +msgstr "" +"\n" +"De volgende ARM-specifieke disassembler-opties worden ondersteund voor gebruik\n" +"via de -M optie:\n" + +#: avr-dis.c:117 avr-dis.c:127 +msgid "undefined" +msgstr "niet gedefinieerd" + +#: avr-dis.c:179 +msgid "Internal disassembler error" +msgstr "Interne fout in de disassembler" + +# Vertaling voor constraint? 'begrenzing' misschien? +#: avr-dis.c:227 +#, c-format +msgid "unknown constraint `%c'" +msgstr "onbekende constraint `%c'" + +#: cgen-asm.c:348 fr30-ibld.c:195 frv-ibld.c:195 ip2k-ibld.c:195 +#: iq2000-ibld.c:195 m32r-ibld.c:195 openrisc-ibld.c:195 xstormy16-ibld.c:195 +#, c-format +msgid "operand out of range (%ld not between %ld and %ld)" +msgstr "operand buiten bereik (%ld niet tussen %ld en %ld)" + +#: cgen-asm.c:369 +#, c-format +msgid "operand out of range (%lu not between %lu and %lu)" +msgstr "operand buiten bereik (%lu niet tussen %lu en %lu)" + +#: d30v-dis.c:312 +#, c-format +msgid "" +msgstr "" + +#. Can't happen. +#: dis-buf.c:57 +#, c-format +msgid "Unknown error %d\n" +msgstr "Onbekende fout %d\n" + +# Slecht vertaald. Wat is de geijkte vertaling voor 'out of bounds'? +#: dis-buf.c:62 +#, c-format +msgid "Address 0x%x is out of bounds.\n" +msgstr "Adres 0x%x is buiten de perken.\n" + +# Betere vertaling voor 'parsing'? +#: fr30-asm.c:323 frv-asm.c:626 ip2k-asm.c:574 iq2000-asm.c:460 m32r-asm.c:325 +#: openrisc-asm.c:261 xstormy16-asm.c:284 +#, c-format +msgid "Unrecognized field %d while parsing.\n" +msgstr "Veld %d niet herkend tijdens parsen.\n" + +#: fr30-asm.c:373 frv-asm.c:676 ip2k-asm.c:624 iq2000-asm.c:510 m32r-asm.c:375 +#: openrisc-asm.c:311 xstormy16-asm.c:334 +msgid "missing mnemonic in syntax string" +msgstr "mnemonic ontbreekt in syntaxstring" + +#. We couldn't parse it. +#: fr30-asm.c:509 fr30-asm.c:513 fr30-asm.c:600 fr30-asm.c:702 frv-asm.c:812 +#: frv-asm.c:816 frv-asm.c:903 frv-asm.c:1005 ip2k-asm.c:760 ip2k-asm.c:764 +#: ip2k-asm.c:851 ip2k-asm.c:953 iq2000-asm.c:646 iq2000-asm.c:650 +#: iq2000-asm.c:737 iq2000-asm.c:839 m32r-asm.c:511 m32r-asm.c:515 +#: m32r-asm.c:602 m32r-asm.c:704 openrisc-asm.c:447 openrisc-asm.c:451 +#: openrisc-asm.c:538 openrisc-asm.c:640 xstormy16-asm.c:470 +#: xstormy16-asm.c:474 xstormy16-asm.c:561 xstormy16-asm.c:663 +msgid "unrecognized instruction" +msgstr "instructie niet herkend" + +#: fr30-asm.c:556 frv-asm.c:859 ip2k-asm.c:807 iq2000-asm.c:693 m32r-asm.c:558 +#: openrisc-asm.c:494 xstormy16-asm.c:517 +#, c-format +msgid "syntax error (expected char `%c', found `%c')" +msgstr "syntaxfout (verwachtte character `%c', maar vond `%c')" + +#: fr30-asm.c:566 frv-asm.c:869 ip2k-asm.c:817 iq2000-asm.c:703 m32r-asm.c:568 +#: openrisc-asm.c:504 xstormy16-asm.c:527 +#, c-format +msgid "syntax error (expected char `%c', found end of instruction)" +msgstr "syntaxfout (verwachtte character `%c', maar vond het einde van de instructie)" + +# Betere (niet-Vlaamse) vertaling voor 'junk'? +#: fr30-asm.c:594 frv-asm.c:897 ip2k-asm.c:845 iq2000-asm.c:731 m32r-asm.c:596 +#: openrisc-asm.c:532 xstormy16-asm.c:555 +msgid "junk at end of line" +msgstr "brol aan einde van lijn" + +#: fr30-asm.c:701 frv-asm.c:1004 ip2k-asm.c:952 iq2000-asm.c:838 +#: m32r-asm.c:703 openrisc-asm.c:639 xstormy16-asm.c:662 +msgid "unrecognized form of instruction" +msgstr "instructievorm niet herkend" + +#: fr30-asm.c:713 frv-asm.c:1016 ip2k-asm.c:964 iq2000-asm.c:850 +#: m32r-asm.c:715 openrisc-asm.c:651 xstormy16-asm.c:674 +#, c-format +msgid "bad instruction `%.50s...'" +msgstr "slechte instructie `%s.50s...'" + +#: fr30-asm.c:716 frv-asm.c:1019 ip2k-asm.c:967 iq2000-asm.c:853 +#: m32r-asm.c:718 openrisc-asm.c:654 xstormy16-asm.c:677 +#, c-format +msgid "bad instruction `%.50s'" +msgstr "slechte instructie `%s.50s'" + +#. Default text to print if an instruction isn't recognized. +#: fr30-dis.c:41 frv-dis.c:41 ip2k-dis.c:41 iq2000-dis.c:41 m32r-dis.c:41 +#: mmix-dis.c:284 openrisc-dis.c:41 xstormy16-dis.c:41 +msgid "*unknown*" +msgstr "*onbekend*" + +#: fr30-dis.c:320 frv-dis.c:371 ip2k-dis.c:329 iq2000-dis.c:192 m32r-dis.c:251 +#: openrisc-dis.c:138 xstormy16-dis.c:171 +#, c-format +msgid "Unrecognized field %d while printing insn.\n" +msgstr "Veld %d niet herkend bij het afdrukken van een insn.\n" + +#: fr30-ibld.c:166 frv-ibld.c:166 ip2k-ibld.c:166 iq2000-ibld.c:166 +#: m32r-ibld.c:166 openrisc-ibld.c:166 xstormy16-ibld.c:166 +#, c-format +msgid "operand out of range (%ld not between %ld and %lu)" +msgstr "operand buiten bereik (%ld niet tussen %ld en %lu)" + +#: fr30-ibld.c:179 frv-ibld.c:179 ip2k-ibld.c:179 iq2000-ibld.c:179 +#: m32r-ibld.c:179 openrisc-ibld.c:179 xstormy16-ibld.c:179 +#, c-format +msgid "operand out of range (%lu not between 0 and %lu)" +msgstr "operand buiten bereik (%lu niet tussen 0 en %lu)" + +#: fr30-ibld.c:730 frv-ibld.c:829 ip2k-ibld.c:607 iq2000-ibld.c:713 +#: m32r-ibld.c:659 openrisc-ibld.c:633 xstormy16-ibld.c:678 +#, c-format +msgid "Unrecognized field %d while building insn.\n" +msgstr "Veld %d niet herkend bij het opbouwen van een insn.\n" + +#: fr30-ibld.c:937 frv-ibld.c:1121 ip2k-ibld.c:684 iq2000-ibld.c:890 +#: m32r-ibld.c:792 openrisc-ibld.c:735 xstormy16-ibld.c:826 +#, c-format +msgid "Unrecognized field %d while decoding insn.\n" +msgstr "Veld %d niet herkend bij het decoderen van een insn.\n" + +#: fr30-ibld.c:1086 frv-ibld.c:1375 ip2k-ibld.c:761 iq2000-ibld.c:1024 +#: m32r-ibld.c:902 openrisc-ibld.c:815 xstormy16-ibld.c:939 +#, c-format +msgid "Unrecognized field %d while getting int operand.\n" +msgstr "Veld %d niet herkend bij het ophalen van een int-operand.\n" + +#: fr30-ibld.c:1215 frv-ibld.c:1609 ip2k-ibld.c:818 iq2000-ibld.c:1138 +#: m32r-ibld.c:992 openrisc-ibld.c:875 xstormy16-ibld.c:1032 +#, c-format +msgid "Unrecognized field %d while getting vma operand.\n" +msgstr "Veld %d niet herkend bij het ophalen van een vma-operand.\n" + +#: fr30-ibld.c:1349 frv-ibld.c:1852 ip2k-ibld.c:880 iq2000-ibld.c:1261 +#: m32r-ibld.c:1090 openrisc-ibld.c:944 xstormy16-ibld.c:1134 +#, c-format +msgid "Unrecognized field %d while setting int operand.\n" +msgstr "Veld %d niet herkend bij het instellen van een int-operand.\n" + +#: fr30-ibld.c:1471 frv-ibld.c:2083 ip2k-ibld.c:930 iq2000-ibld.c:1372 +#: m32r-ibld.c:1176 openrisc-ibld.c:1001 xstormy16-ibld.c:1224 +#, c-format +msgid "Unrecognized field %d while setting vma operand.\n" +msgstr "Veld %d niet herkend bij het instellen van een vma-operand.\n" + +#: frv-asm.c:365 +msgid "register number must be even" +msgstr "registernummer moet paar zijn" + +#: h8300-dis.c:377 +#, c-format +msgid "Hmmmm 0x%x" +msgstr "Hmmmm 0x%x" + +#: h8300-dis.c:760 +#, c-format +msgid "Don't understand 0x%x \n" +msgstr "Ik begrijp 0x%x niet\n" + +#: h8500-dis.c:143 +#, c-format +msgid "can't cope with insert %d\n" +msgstr "kan niet omgaan met insert %d\n" + +#. Couldn't understand anything. +#: h8500-dis.c:350 +#, c-format +msgid "%02x\t\t*unknown*" +msgstr "%02x\t\t*onbekend*" + +#: i386-dis.c:1699 +msgid "" +msgstr "" + +#: ia64-gen.c:295 +#, c-format +msgid "%s: Error: " +msgstr "%s: Fout: " + +#: ia64-gen.c:308 +#, c-format +msgid "%s: Warning: " +msgstr "%s: Let Op: " + +#: ia64-gen.c:494 ia64-gen.c:728 +#, c-format +msgid "multiple note %s not handled\n" +msgstr "meervoudige noot %s wordt niet opgevangen\n" + +#: ia64-gen.c:605 +msgid "can't find ia64-ic.tbl for reading\n" +msgstr "kan invoerbestand ia64-ic.tbl niet vinden\n" + +#: ia64-gen.c:810 +#, c-format +msgid "can't find %s for reading\n" +msgstr "kan invoerbestand %s niet vinden\n" + +#: ia64-gen.c:1034 +#, c-format +msgid "" +"most recent format '%s'\n" +"appears more restrictive than '%s'\n" +msgstr "" +"het meest recente formaat '%s'\n" +"lijkt meer beperkend dan '%s'\n" + +#: ia64-gen.c:1045 +#, c-format +msgid "overlapping field %s->%s\n" +msgstr "overlappend veld %s->%s\n" + +#: ia64-gen.c:1236 +#, c-format +msgid "overwriting note %d with note %d (IC:%s)\n" +msgstr "noot %d wordt overschreven door noot %d (IC:%s)\n" + +#: ia64-gen.c:1435 +#, c-format +msgid "don't know how to specify %% dependency %s\n" +msgstr "ik weet niet hoe ik de %%-dependency %s moet opgeven\n" + +#: ia64-gen.c:1457 +#, c-format +msgid "Don't know how to specify # dependency %s\n" +msgstr "Ik weet niet hoe ik de #-dependency %s moet opgeven\n" + +#: ia64-gen.c:1496 +#, c-format +msgid "IC:%s [%s] has no terminals or sub-classes\n" +msgstr "IC:%s [%s] heeft geen eindsymbolen of subklassen\n" + +#: ia64-gen.c:1499 +#, c-format +msgid "IC:%s has no terminals or sub-classes\n" +msgstr "IC:%s heeft geen eindsymbolen of subklassen\n" + +#: ia64-gen.c:1508 +#, c-format +msgid "no insns mapped directly to terminal IC %s [%s]" +msgstr "er zijn geen insns die rechtstreeks naar eindsymbool IC %s [%s] vertaald worden" + +#: ia64-gen.c:1511 +#, c-format +msgid "no insns mapped directly to terminal IC %s\n" +msgstr "er zijn geen insns die rechtstreeks naar eindsymbool IC %s vertaald worden\n" + +#: ia64-gen.c:1522 +#, c-format +msgid "class %s is defined but not used\n" +msgstr "klasse %s is gedefinieerd maar wordt niet gebruikt\n" + +#: ia64-gen.c:1533 +#, c-format +msgid "Warning: rsrc %s (%s) has no chks%s\n" +msgstr "Let Op: rsrc %s (%s) heeft geen chks%s\n" + +#: ia64-gen.c:1537 +#, c-format +msgid "rsrc %s (%s) has no regs\n" +msgstr "rsrc %s (%s) heeft geen regs\n" + +#: ia64-gen.c:2436 +#, c-format +msgid "IC note %d in opcode %s (IC:%s) conflicts with resource %s note %d\n" +msgstr "IC noot %d in opcode %s (IC:%s) geeft een conflict met resource %s noot %d\n" + +#: ia64-gen.c:2464 +#, c-format +msgid "IC note %d for opcode %s (IC:%s) conflicts with resource %s note %d\n" +msgstr "IC noot %d voor opcode %s (IC:%s) geeft een conflict met resource %s noot %d\n" + +#: ia64-gen.c:2478 +#, c-format +msgid "opcode %s has no class (ops %d %d %d)\n" +msgstr "opcode %s heeft geen klasse (ops %d %d %d)\n" + +#: ia64-gen.c:2789 +#, c-format +msgid "unable to change directory to \"%s\", errno = %s\n" +msgstr "kan niet naar directory \"%s\" gaan, errno = %s\n" + +#. We've been passed a w. Return with an error message so that +#. cgen will try the next parsing option. +#: ip2k-asm.c:92 +msgid "W keyword invalid in FR operand slot." +msgstr "keyword W is ongeldig in operand-slot FR" + +#. Invalid offset present. +#: ip2k-asm.c:122 +msgid "offset(IP) is not a valid form" +msgstr "offset(IP) is geen geldige vorm" + +#. Found something there in front of (DP) but it's out +#. of range. +#: ip2k-asm.c:175 +msgid "(DP) offset out of range." +msgstr "(DP) offset buiten bereik" + +#. Found something there in front of (SP) but it's out +#. of range. +#: ip2k-asm.c:221 +msgid "(SP) offset out of range." +msgstr "(SP) offset buiten bereik" + +#: ip2k-asm.c:241 +msgid "illegal use of parentheses" +msgstr "ongeldig gebruik van haakjes" + +#: ip2k-asm.c:248 +msgid "operand out of range (not between 1 and 255)" +msgstr "operand buiten bereik (niet tussen 1 en 255)" + +#. Something is very wrong. opindex has to be one of the above. +#: ip2k-asm.c:273 +msgid "parse_addr16: invalid opindex." +msgstr "parse_addr16: ongeldige opindex." + +#: ip2k-asm.c:353 +msgid "Byte address required. - must be even." +msgstr "Byte-adres vereist. - moet paar zijn." + +#: ip2k-asm.c:362 +msgid "cgen_parse_address returned a symbol. Literal required." +msgstr "cgen_parse_address gaf een symbool terug terwijl een letterlijke waarde vereist is." + +#: ip2k-asm.c:420 +#, c-format +msgid "%operator operand is not a symbol" +msgstr "operand van %operator is geen symbool" + +#: ip2k-asm.c:474 +msgid "Attempt to find bit index of 0" +msgstr "Poging tot vinden van bit-index van 0" + +#: iq2000-asm.c:110 iq2000-asm.c:141 +msgid "immediate value cannot be register" +msgstr "onmiddellijke waarde kan geen register zijn" + +# of moet 'immediate' behouden worden? +#: iq2000-asm.c:120 iq2000-asm.c:151 +msgid "immediate value out of range" +msgstr "onmiddellijke waarde is buiten bereik" + +#: iq2000-asm.c:180 +msgid "21-bit offset out of range" +msgstr "21-bit offset is buiten bereik" + +#: iq2000-asm.c:205 iq2000-asm.c:235 iq2000-asm.c:272 iq2000-asm.c:305 +#: openrisc-asm.c:96 openrisc-asm.c:155 +msgid "missing `)'" +msgstr "`)' ontbreekt" + +#: m10200-dis.c:199 +#, c-format +msgid "unknown\t0x%02x" +msgstr "onbekend\t0x%02x" + +#: m10200-dis.c:339 +#, c-format +msgid "unknown\t0x%04lx" +msgstr "onbekend\t0x%04lx" + +#: m10300-dis.c:766 +#, c-format +msgid "unknown\t0x%04x" +msgstr "onbekend\t0x%04x" + +#: m68k-dis.c:429 +#, c-format +msgid "\n" +msgstr "\n" + +#: m68k-dis.c:1007 +#, c-format +msgid "" +msgstr "" + +#: m88k-dis.c:746 +#, c-format +msgid "# " +msgstr "# " + +#: mips-dis.c:699 +msgid "# internal error, incomplete extension sequence (+)" +msgstr "# interne fout, onvolledige extension sequence (+)" + +#: mips-dis.c:742 +#, c-format +msgid "# internal error, undefined extension sequence (+%c)" +msgstr "# interne fout, extension sequence (+%c) niet gedefinieerd" + +#: mips-dis.c:1000 +#, c-format +msgid "# internal error, undefined modifier(%c)" +msgstr "# interne fout, modifier(%c) niet gedefinieerd" + +#: mips-dis.c:1751 +#, c-format +msgid "# internal disassembler error, unrecognised modifier (%c)" +msgstr "# interne fout in disassembler, modifier(%c) niet herkend" + +#: mips-dis.c:1763 +msgid "" +"\n" +"The following MIPS specific disassembler options are supported for use\n" +"with the -M switch (multiple options should be separated by commas):\n" +msgstr "" +"\n" +"De volgende MIPS-specifieke disassembler-opties worden ondersteund voor gebruik\n" +"via de -M optie (meerdere opties moeten door komma's gescheiden worden):\n" + +#: mips-dis.c:1767 +msgid "" +"\n" +" gpr-names=ABI Print GPR names according to specified ABI.\n" +" Default: based on binary being disassembled.\n" +msgstr "" +"\n" +" gpr-names=ABI Druk GPR-namen af volgens de opgegeven ABI.\n" +" Standaard: gebaseerd op het binair bestand dat\n" +" gedesassembleerd wordt.\n" + +#: mips-dis.c:1771 +msgid "" +"\n" +" fpr-names=ABI Print FPR names according to specified ABI.\n" +" Default: numeric.\n" +msgstr "" +"\n" +" fpr-names=ABI Druk FPR-namen af volgens de opgegeven ABI.\n" +" Standaard: numeriek.\n" + +#: mips-dis.c:1775 +msgid "" +"\n" +" cp0-names=ARCH Print CP0 register names according to\n" +" specified architecture.\n" +" Default: based on binary being disassembled.\n" +msgstr "" +"\n" +" cp0-names=ARCH Druk CP0 registernamen af volgens de opgegeven\n" +" architectuur.\n" +" Standaard: gebaseerd op het binair bestand dat\n" +" gedesassembleerd wordt.\n" + +#: mips-dis.c:1780 +msgid "" +"\n" +" hwr-names=ARCH Print HWR names according to specified \n" +"\t\t\t architecture.\n" +" Default: based on binary being disassembled.\n" +msgstr "" +"\n" +" hwr-names=ARCH Druk HWR-namen af volgens de opgegeven architectuur.\n" +" Standaard: gebaseerd op het binair bestand dat\n" +" gedesassembleerd wordt.\n" +"\n" + +#: mips-dis.c:1785 +msgid "" +"\n" +" reg-names=ABI Print GPR and FPR names according to\n" +" specified ABI.\n" +msgstr "" +"\n" +" reg-names=ABI Druk GPR- en FPR-namen af volgens de opgegeven ABI.\n" + +#: mips-dis.c:1789 +msgid "" +"\n" +" reg-names=ARCH Print CP0 register and HWR names according to\n" +" specified architecture.\n" +msgstr "" +"\n" +" reg-names=ARCH Druk CP0 registernamen en HWR-namen af volgens de\n" +" opgegeven architectuur.\n" + +#: mips-dis.c:1793 +msgid "" +"\n" +" For the options above, the following values are supported for \"ABI\":\n" +" " +msgstr "" +"\n" +" Voor de bovenstaande opties zijn dit de ondersteunde waarden voor \"ABI\":\n" +" " + +#: mips-dis.c:1798 mips-dis.c:1806 mips-dis.c:1808 +msgid "\n" +msgstr "\n" + +#: mips-dis.c:1800 +msgid "" +"\n" +" For the options above, The following values are supported for \"ARCH\":\n" +" " +msgstr "" +"\n" +" Voor de bovenstaande opties zijn dit de ondersteunde waarden voor \"ARCH\":\n" +" " + +#: mmix-dis.c:34 +#, c-format +msgid "Bad case %d (%s) in %s:%d\n" +msgstr "Ongeldige case %d (%s) in %s:%d\n" + +#: mmix-dis.c:44 +#, c-format +msgid "Internal: Non-debugged code (test-case missing): %s:%d" +msgstr "Intern: Code niet gedebugd (test-case ontbreekt): %s:%d" + +#: mmix-dis.c:53 +msgid "(unknown)" +msgstr "(onbekend)" + +#: mmix-dis.c:519 +#, c-format +msgid "*unknown operands type: %d*" +msgstr "onbekend type operanden: %d" + +#. I and Z are output operands and can`t be immediate +#. * A is an address and we can`t have the address of +#. * an immediate either. We don't know how much to increase +#. * aoffsetp by since whatever generated this is broken +#. * anyway! +#. +#: ns32k-dis.c:631 +msgid "$" +msgstr "$" + +#: ppc-opc.c:781 ppc-opc.c:809 +msgid "invalid conditional option" +msgstr "ongeldige voorwaardelijke optie" + +# Dit kan waarschijnlijk beter +#: ppc-opc.c:811 +msgid "attempt to set y bit when using + or - modifier" +msgstr "poging om y bit in te stellen wanneer + of - modifier gebruikt wordt" + +#: ppc-opc.c:840 +msgid "offset not a multiple of 16" +msgstr "offset is geen veelvoud van 16" + +#: ppc-opc.c:860 +msgid "offset not a multiple of 2" +msgstr "offset is geen veelvoud van 2" + +#: ppc-opc.c:862 +msgid "offset greater than 62" +msgstr "offset is groter dan 62" + +#: ppc-opc.c:881 ppc-opc.c:927 ppc-opc.c:975 +msgid "offset not a multiple of 4" +msgstr "offset is geen veelvoud van 4" + +#: ppc-opc.c:883 +msgid "offset greater than 124" +msgstr "offset is groter dan 124" + +#: ppc-opc.c:902 +msgid "offset not a multiple of 8" +msgstr "offset is geen veelvoud van 8" + +#: ppc-opc.c:904 +msgid "offset greater than 248" +msgstr "offset is groter dan 248" + +#: ppc-opc.c:950 +msgid "offset not between -2048 and 2047" +msgstr "offset ligt niet tussen -2048 en 2047" + +#: ppc-opc.c:973 +msgid "offset not between -8192 and 8191" +msgstr "offset ligt niet tussen -8192 en 8191" + +#: ppc-opc.c:1011 +msgid "ignoring invalid mfcr mask" +msgstr "ongeldig mfcr-masker wordt genegeerd" + +#: ppc-opc.c:1059 +msgid "ignoring least significant bits in branch offset" +msgstr "minst significante bits worden genegeerd in branch offset" + +#: ppc-opc.c:1090 ppc-opc.c:1125 +msgid "illegal bitmask" +msgstr "illegaal bitmasker" + +#: ppc-opc.c:1192 +msgid "value out of range" +msgstr "waarde buiten bereik" + +# of is laadbereik beter? +#: ppc-opc.c:1262 +msgid "index register in load range" +msgstr "indexregister in load-bereik" + +#: ppc-opc.c:1279 +msgid "source and target register operands must be different" +msgstr "bron- en doel-registeroperanden moeten verschillen" + +#: ppc-opc.c:1294 +msgid "invalid register operand when updating" +msgstr "ongeldige register-operand bij update" + +#: ppc-opc.c:1335 +msgid "target register operand must be even" +msgstr "doel-registeroperand moet paar zijn" + +#: ppc-opc.c:1350 +msgid "source register operand must be even" +msgstr "bron-registeroperand moet paar zijn" + +#. Mark as non-valid instruction. +#: sparc-dis.c:760 +msgid "unknown" +msgstr "onbekend" + +# Looks like this is a typo (two spaces after the ':') +#: sparc-dis.c:835 +#, c-format +msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" +msgstr "Interne fout: sparch-opcode.h is verkeerd: \"%s\", %#.8lx, %#.8lx\n" + +#: sparc-dis.c:846 +#, c-format +msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" +msgstr "Interne fout: sparch-opcode.h is verkeerd: \"%s\", %#.8lx, %#.8lx\n" + +#: sparc-dis.c:895 +#, c-format +msgid "Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n" +msgstr "Interne fout: sparch-opcode.h is verkeerd: \"%s\" == \"%s\"\n" + +#: v850-dis.c:221 +#, c-format +msgid "unknown operand shift: %x\n" +msgstr "onbekende operand-shift: %x\n" + +#: v850-dis.c:233 +#, c-format +msgid "unknown pop reg: %d\n" +msgstr "onbekend pop reg: %d\n" + +# Wat is een goede vertaling voor 'displacement'? +#. The functions used to insert and extract complicated operands. +#. Note: There is a conspiracy between these functions and +#. v850_insert_operand() in gas/config/tc-v850.c. Error messages +#. containing the string 'out of range' will be ignored unless a +#. specific command line option is given to GAS. +#: v850-opc.c:68 +msgid "displacement value is not in range and is not aligned" +msgstr "displacement-waarde is niet in bereik en is niet uitgelijnd" + +#: v850-opc.c:69 +msgid "displacement value is out of range" +msgstr "displacement-waarde is buiten bereik" + +#: v850-opc.c:70 +msgid "displacement value is not aligned" +msgstr "displacement-waarde is niet uitgelijnd" + +# of moet 'immediate' behouden worden? +#: v850-opc.c:72 +msgid "immediate value is out of range" +msgstr "onmiddellijke waarde is buiten bereik" + +# Repeated message..., use 'to an odd...' to merge it +#: v850-opc.c:83 +msgid "branch value not in range and to odd offset" +msgstr "branch-waarde niet in bereik en naar onpare offset" + +#: v850-opc.c:85 v850-opc.c:117 +msgid "branch value out of range" +msgstr "branch-waarde buiten bereik" + +#: v850-opc.c:88 v850-opc.c:120 +msgid "branch to odd offset" +msgstr "branch naar onpare offset" + +#: v850-opc.c:115 +msgid "branch value not in range and to an odd offset" +msgstr "branch-waarde niet in bereik en naar een onpare offset" + +#: v850-opc.c:346 +msgid "invalid register for stack adjustment" +msgstr "ongeldig register voor stack-aanpassing" + +#: v850-opc.c:370 +msgid "immediate value not in range and not even" +msgstr "onmiddellijke waarde niet in bereik en niet paar" + +#: v850-opc.c:375 +msgid "immediate value must be even" +msgstr "onmiddellijke waarde moet paar zijn" + +# of is laadbereik beter? +#: xstormy16-asm.c:76 +msgid "Bad register in preincrement" +msgstr "Ongeldig register in preincrement" + +#: xstormy16-asm.c:81 +msgid "Bad register in postincrement" +msgstr "Ongeldig register in postincrement" + +# of is laadbereik beter? +#: xstormy16-asm.c:83 +msgid "Bad register name" +msgstr "Ongeldige registernaam" + +#: xstormy16-asm.c:87 +msgid "Label conflicts with register name" +msgstr "Label geeft conflict met registernaam" + +#: xstormy16-asm.c:91 +msgid "Label conflicts with `Rx'" +msgstr "Label geeft conflict met `Rx'" + +#: xstormy16-asm.c:93 +msgid "Bad immediate expression" +msgstr "Slechte onmiddelijke expressie" + +# immediate what? 'value' assumed +#: xstormy16-asm.c:115 +msgid "No relocation for small immediate" +msgstr "Geen relocatie voor kleine onmiddelijke waarde" + +#: xstormy16-asm.c:125 +msgid "Small operand was not an immediate number" +msgstr "Kleine operand was geen onmiddellijk getal" + +#: xstormy16-asm.c:164 +msgid "Operand is not a symbol" +msgstr "Operand is geen symbool" + +#: xstormy16-asm.c:172 +msgid "Syntax error: No trailing ')'" +msgstr "Syntaxfout: Geen sluithaakje" diff --git a/opcodes/po/ro.po b/opcodes/po/ro.po new file mode 100644 index 0000000..ca0b870 --- /dev/null +++ b/opcodes/po/ro.po @@ -0,0 +1,788 @@ +# Mesajele în limba românã pentru pachetul opcodes +# Copyright (C) 2003 Free Software Foundation, Inc. +# Eugen Hoanca , 2003 +# +msgid "" +msgstr "" +"Project-Id-Version: opcodes 2.14rel030712\n" +"POT-Creation-Date: 2003-07-11 13:56+0930\n" +"PO-Revision-Date: 2003-07-21 16:53+0300\n" +"Last-Translator: Eugen Hoanca \n" +"Language-Team: Romanian \n" +"MIME-Version: 1.0\n" +"Content-Type: text/plain; charset=ISO-8859-2\n" +"Content-Transfer-Encoding: 8bit\n" + +#: alpha-opc.c:335 +msgid "branch operand unaligned" +msgstr "ramurã operand nealiniatã" + +#: alpha-opc.c:358 alpha-opc.c:380 +msgid "jump hint unaligned" +msgstr "sugestie salt(jump) nealiniat" + +#: arc-dis.c:52 +msgid "Illegal limm reference in last instruction!\n" +msgstr "referinþã limm ilegalã în ultima instrucþiune!\n" + +#: arm-dis.c:554 +msgid "" +msgstr "" + +#: arm-dis.c:1162 +#, c-format +msgid "Unrecognised register name set: %s\n" +msgstr "Setare nume registru necunoscutã: %s\n" + +#: arm-dis.c:1169 +#, c-format +msgid "Unrecognised disassembler option: %s\n" +msgstr "Opþiune dezasamblor necunsocutã: %s\n" + +#: arm-dis.c:1343 +msgid "" +"\n" +"The following ARM specific disassembler options are supported for use with\n" +"the -M switch:\n" +msgstr "" +"\n" +"Opþiunile ARM de dezasamblor specifice urmãtoare sunt permise cu folosirea\n" +"switch-ului -M:\n" + +#: avr-dis.c:117 avr-dis.c:127 +msgid "undefined" +msgstr "nedefinit(ã)" + +#: avr-dis.c:179 +msgid "Internal disassembler error" +msgstr "Eroare internã de dezasamblor" + +#: avr-dis.c:227 +#, c-format +msgid "unknown constraint `%c'" +msgstr "constrângere necunoscutã `%c'" + +#: cgen-asm.c:348 fr30-ibld.c:195 frv-ibld.c:195 ip2k-ibld.c:195 +#: iq2000-ibld.c:195 m32r-ibld.c:195 openrisc-ibld.c:195 xstormy16-ibld.c:195 +#, c-format +msgid "operand out of range (%ld not between %ld and %ld)" +msgstr "operand în afara intervalului (%ld nu este între %ld ºi %ld)" + +#: cgen-asm.c:369 +#, c-format +msgid "operand out of range (%lu not between %lu and %lu)" +msgstr "operand în afara intervalului (%lu nu este între %lu ºi %lu)" + +#: d30v-dis.c:312 +#, c-format +msgid "" +msgstr "" + +#. Can't happen. +#: dis-buf.c:57 +#, c-format +msgid "Unknown error %d\n" +msgstr "Eroare necunoscutã %d\n" + +#: dis-buf.c:62 +#, c-format +msgid "Address 0x%x is out of bounds.\n" +msgstr "Adresa 0x%x este peste limite (out of bounds).\n" + +#: fr30-asm.c:323 frv-asm.c:626 ip2k-asm.c:574 iq2000-asm.c:460 m32r-asm.c:325 +#: openrisc-asm.c:261 xstormy16-asm.c:284 +#, c-format +msgid "Unrecognized field %d while parsing.\n" +msgstr "Câmp necunoscut %d în analizã(parsing).\n" + +#: fr30-asm.c:373 frv-asm.c:676 ip2k-asm.c:624 iq2000-asm.c:510 m32r-asm.c:375 +#: openrisc-asm.c:311 xstormy16-asm.c:334 +msgid "missing mnemonic in syntax string" +msgstr "mnemonicã lipsã în sintaxã" + +#. We couldn't parse it. +#: fr30-asm.c:509 fr30-asm.c:513 fr30-asm.c:600 fr30-asm.c:702 frv-asm.c:812 +#: frv-asm.c:816 frv-asm.c:903 frv-asm.c:1005 ip2k-asm.c:760 ip2k-asm.c:764 +#: ip2k-asm.c:851 ip2k-asm.c:953 iq2000-asm.c:646 iq2000-asm.c:650 +#: iq2000-asm.c:737 iq2000-asm.c:839 m32r-asm.c:511 m32r-asm.c:515 +#: m32r-asm.c:602 m32r-asm.c:704 openrisc-asm.c:447 openrisc-asm.c:451 +#: openrisc-asm.c:538 openrisc-asm.c:640 xstormy16-asm.c:470 +#: xstormy16-asm.c:474 xstormy16-asm.c:561 xstormy16-asm.c:663 +msgid "unrecognized instruction" +msgstr "instrucþiune necunoscutã" + +#: fr30-asm.c:556 frv-asm.c:859 ip2k-asm.c:807 iq2000-asm.c:693 m32r-asm.c:558 +#: openrisc-asm.c:494 xstormy16-asm.c:517 +#, c-format +msgid "syntax error (expected char `%c', found `%c')" +msgstr "eroare de sintaxã ( se aºtepta %c', s-a primit `%c')" + +#: fr30-asm.c:566 frv-asm.c:869 ip2k-asm.c:817 iq2000-asm.c:703 m32r-asm.c:568 +#: openrisc-asm.c:504 xstormy16-asm.c:527 +#, c-format +msgid "syntax error (expected char `%c', found end of instruction)" +msgstr "eroare de sintaxã (s-a aºteptat char `%c' s-a primit sfârºit de instrucþiune)" + +#: fr30-asm.c:594 frv-asm.c:897 ip2k-asm.c:845 iq2000-asm.c:731 m32r-asm.c:596 +#: openrisc-asm.c:532 xstormy16-asm.c:555 +msgid "junk at end of line" +msgstr "resturi(junk) la sfârºit de linie" + +#: fr30-asm.c:701 frv-asm.c:1004 ip2k-asm.c:952 iq2000-asm.c:838 +#: m32r-asm.c:703 openrisc-asm.c:639 xstormy16-asm.c:662 +msgid "unrecognized form of instruction" +msgstr "formã de instrucþiune necunoscutã" + +#: fr30-asm.c:713 frv-asm.c:1016 ip2k-asm.c:964 iq2000-asm.c:850 +#: m32r-asm.c:715 openrisc-asm.c:651 xstormy16-asm.c:674 +#, c-format +msgid "bad instruction `%.50s...'" +msgstr "instrucþiune greºitã ``%.50s...'" + +#: fr30-asm.c:716 frv-asm.c:1019 ip2k-asm.c:967 iq2000-asm.c:853 +#: m32r-asm.c:718 openrisc-asm.c:654 xstormy16-asm.c:677 +#, c-format +msgid "bad instruction `%.50s'" +msgstr "instrucþiune greºitã `%.50s'" + +#. Default text to print if an instruction isn't recognized. +#: fr30-dis.c:41 frv-dis.c:41 ip2k-dis.c:41 iq2000-dis.c:41 m32r-dis.c:41 +#: mmix-dis.c:284 openrisc-dis.c:41 xstormy16-dis.c:41 +msgid "*unknown*" +msgstr "*necunoscut(ã)*" + +#: fr30-dis.c:320 frv-dis.c:371 ip2k-dis.c:329 iq2000-dis.c:192 m32r-dis.c:251 +#: openrisc-dis.c:138 xstormy16-dis.c:171 +#, c-format +msgid "Unrecognized field %d while printing insn.\n" +msgstr "Câmp necunoscut %d în tipãrire insn.\n" + +#: fr30-ibld.c:166 frv-ibld.c:166 ip2k-ibld.c:166 iq2000-ibld.c:166 +#: m32r-ibld.c:166 openrisc-ibld.c:166 xstormy16-ibld.c:166 +#, c-format +msgid "operand out of range (%ld not between %ld and %lu)" +msgstr "operand în afara limitelor (%ld nu este între %ld ºi %lu)" + +#: fr30-ibld.c:179 frv-ibld.c:179 ip2k-ibld.c:179 iq2000-ibld.c:179 +#: m32r-ibld.c:179 openrisc-ibld.c:179 xstormy16-ibld.c:179 +#, c-format +msgid "operand out of range (%lu not between 0 and %lu)" +msgstr "operand în afara limitelor (%lu nu este între 0 ºi %lu)" + +#: fr30-ibld.c:730 frv-ibld.c:829 ip2k-ibld.c:607 iq2000-ibld.c:713 +#: m32r-ibld.c:659 openrisc-ibld.c:633 xstormy16-ibld.c:678 +#, c-format +msgid "Unrecognized field %d while building insn.\n" +msgstr "Câmp necunoscut %d în construire(building) insn.\n" + +#: fr30-ibld.c:937 frv-ibld.c:1121 ip2k-ibld.c:684 iq2000-ibld.c:890 +#: m32r-ibld.c:792 openrisc-ibld.c:735 xstormy16-ibld.c:826 +#, c-format +msgid "Unrecognized field %d while decoding insn.\n" +msgstr "Câmp necunoscut %d în decodare insn.\n" + +#: fr30-ibld.c:1086 frv-ibld.c:1375 ip2k-ibld.c:761 iq2000-ibld.c:1024 +#: m32r-ibld.c:902 openrisc-ibld.c:815 xstormy16-ibld.c:939 +#, c-format +msgid "Unrecognized field %d while getting int operand.\n" +msgstr "Câmp necunoscut %d în preluare operand int.\n" + +#: fr30-ibld.c:1215 frv-ibld.c:1609 ip2k-ibld.c:818 iq2000-ibld.c:1138 +#: m32r-ibld.c:992 openrisc-ibld.c:875 xstormy16-ibld.c:1032 +#, c-format +msgid "Unrecognized field %d while getting vma operand.\n" +msgstr "Câmp necunoscut %d în preluare operand vma.\n" + +#: fr30-ibld.c:1349 frv-ibld.c:1852 ip2k-ibld.c:880 iq2000-ibld.c:1261 +#: m32r-ibld.c:1090 openrisc-ibld.c:944 xstormy16-ibld.c:1134 +#, c-format +msgid "Unrecognized field %d while setting int operand.\n" +msgstr "Câmp necunoscut %d în setare operand int.\n" + +#: fr30-ibld.c:1471 frv-ibld.c:2083 ip2k-ibld.c:930 iq2000-ibld.c:1372 +#: m32r-ibld.c:1176 openrisc-ibld.c:1001 xstormy16-ibld.c:1224 +#, c-format +msgid "Unrecognized field %d while setting vma operand.\n" +msgstr "Câmp necunoscut %d în setare operand vma.\n" + +#: frv-asm.c:365 +msgid "register number must be even" +msgstr "numãrul registrului trebuie sã fie par" + +#: h8300-dis.c:377 +#, c-format +msgid "Hmmmm 0x%x" +msgstr "Hmmmm 0x%x" + +#: h8300-dis.c:760 +#, c-format +msgid "Don't understand 0x%x \n" +msgstr "Nu înþeleg 0x%x \n" + +#: h8500-dis.c:143 +#, c-format +msgid "can't cope with insert %d\n" +msgstr "nu fac faþã la inserarea %d\n" + +#. Couldn't understand anything. +#: h8500-dis.c:350 +#, c-format +msgid "%02x\t\t*unknown*" +msgstr "%02x\t\t*necunoscut(ã)*" + +#: i386-dis.c:1699 +msgid "" +msgstr "" + +#: ia64-gen.c:295 +#, c-format +msgid "%s: Error: " +msgstr "%s: Eroare: " + +#: ia64-gen.c:308 +#, c-format +msgid "%s: Warning: " +msgstr "%s: Avertisment: " + +#: ia64-gen.c:494 ia64-gen.c:728 +#, c-format +msgid "multiple note %s not handled\n" +msgstr "notele multiple %s nerezolvabile(handled)\n" + +#: ia64-gen.c:605 +msgid "can't find ia64-ic.tbl for reading\n" +msgstr "nu pot gãsi ia64-ic.tbl pentru citire\n" + +#: ia64-gen.c:810 +#, c-format +msgid "can't find %s for reading\n" +msgstr "nu pot gãsi %s pentru citire\n" + +#: ia64-gen.c:1034 +#, c-format +msgid "" +"most recent format '%s'\n" +"appears more restrictive than '%s'\n" +msgstr "" +"cel mai recent format %s \n" +"pare mai restrictiv decât '%s'\n" + +#: ia64-gen.c:1045 +#, c-format +msgid "overlapping field %s->%s\n" +msgstr "câmp suprapus %s -> %s\n" + +#: ia64-gen.c:1236 +#, c-format +msgid "overwriting note %d with note %d (IC:%s)\n" +msgstr "suprascriere nota %d cu nota %d (IC:%s)\n" + +#: ia64-gen.c:1435 +#, c-format +msgid "don't know how to specify %% dependency %s\n" +msgstr "nu ºtiu cum se specificã dependinþele %% %s\n" + +#: ia64-gen.c:1457 +#, c-format +msgid "Don't know how to specify # dependency %s\n" +msgstr "nu ºtiu cum se specificã dependinþele # %s\n" + +#: ia64-gen.c:1496 +#, c-format +msgid "IC:%s [%s] has no terminals or sub-classes\n" +msgstr "IC:%s [%s] nu are terminale sau sublclase\n" + +#: ia64-gen.c:1499 +#, c-format +msgid "IC:%s has no terminals or sub-classes\n" +msgstr "IC:%s nu are terminale sau subclase\n" + +#: ia64-gen.c:1508 +#, c-format +msgid "no insns mapped directly to terminal IC %s [%s]" +msgstr "nici un insns mapat direct la terminalul IC %s [%s]" + +#: ia64-gen.c:1511 +#, c-format +msgid "no insns mapped directly to terminal IC %s\n" +msgstr "nici un insns mapat direct la terminalul IC %s\n" + +#: ia64-gen.c:1522 +#, c-format +msgid "class %s is defined but not used\n" +msgstr "clasa %s este definitã dar nefolositã\n" + +#: ia64-gen.c:1533 +#, c-format +msgid "Warning: rsrc %s (%s) has no chks%s\n" +msgstr "Avertisment: rsrc %s (%s) nu are chks%s\n" + +#: ia64-gen.c:1537 +#, c-format +msgid "rsrc %s (%s) has no regs\n" +msgstr "rsrc %s (%s) nu areo regs\n" + +#: ia64-gen.c:2436 +#, c-format +msgid "IC note %d in opcode %s (IC:%s) conflicts with resource %s note %d\n" +msgstr "Nota IC %d din opcode %s (IC:%s) e în conflict cu resursa %s nota %d\n" + +#: ia64-gen.c:2464 +#, c-format +msgid "IC note %d for opcode %s (IC:%s) conflicts with resource %s note %d\n" +msgstr "Nota IC %d pentru opcode %s (IC:%s) e în conflict cu resursa %s nota %d\n" + +#: ia64-gen.c:2478 +#, c-format +msgid "opcode %s has no class (ops %d %d %d)\n" +msgstr "opcode %s nu are clasã (ops %d %d %d)\n" + +#: ia64-gen.c:2789 +#, c-format +msgid "unable to change directory to \"%s\", errno = %s\n" +msgstr "nu am putut schimba directorul în \"%s\", errno = %s\n" + +#. We've been passed a w. Return with an error message so that +#. cgen will try the next parsing option. +#: ip2k-asm.c:92 +msgid "W keyword invalid in FR operand slot." +msgstr "Cuvânt cheie W invalidv în slotul operand FR." + +#. Invalid offset present. +#: ip2k-asm.c:122 +msgid "offset(IP) is not a valid form" +msgstr "offsetul(IP) nu are formã validã" + +#. Found something there in front of (DP) but it's out +#. of range. +#: ip2k-asm.c:175 +msgid "(DP) offset out of range." +msgstr "(DP) offset în afara intervalului" + +#. Found something there in front of (SP) but it's out +#. of range. +#: ip2k-asm.c:221 +msgid "(SP) offset out of range." +msgstr "(SP) offset în afara intervalului" + +#: ip2k-asm.c:241 +msgid "illegal use of parentheses" +msgstr "Folosire ilegalã de paranteze" + +#: ip2k-asm.c:248 +msgid "operand out of range (not between 1 and 255)" +msgstr "operand în afara limitelor (nu este între 0 ºi 255)" + +#. Something is very wrong. opindex has to be one of the above. +#: ip2k-asm.c:273 +msgid "parse_addr16: invalid opindex." +msgstr "parse_addr16: opindex invalid." + +#: ip2k-asm.c:353 +msgid "Byte address required. - must be even." +msgstr "Se necesitã adresã byte. -trebuie sã fie parã (even)." + +#: ip2k-asm.c:362 +msgid "cgen_parse_address returned a symbol. Literal required." +msgstr "cgen_parse_address a returnat un simbol. Se necesitã literal." + +#: ip2k-asm.c:420 +#, c-format +msgid "%operator operand is not a symbol" +msgstr "%operator operandulk nu este un simbol" + +#: ip2k-asm.c:474 +msgid "Attempt to find bit index of 0" +msgstr "Se încearcã gãsirea bitului index de 0" + +#: iq2000-asm.c:110 iq2000-asm.c:141 +msgid "immediate value cannot be register" +msgstr "valoarea directã(immediate) nu poate fi înregistratã" + +#: iq2000-asm.c:120 iq2000-asm.c:151 +msgid "immediate value out of range" +msgstr "valoare directã(immediate) în afara intervalului" + +#: iq2000-asm.c:180 +msgid "21-bit offset out of range" +msgstr "offsetul 21 bit în afara intervalului" + +#: iq2000-asm.c:205 iq2000-asm.c:235 iq2000-asm.c:272 iq2000-asm.c:305 +#: openrisc-asm.c:96 openrisc-asm.c:155 +msgid "missing `)'" +msgstr "`)' lipsã" + +#: m10200-dis.c:199 +#, c-format +msgid "unknown\t0x%02x" +msgstr "necunoscut(ã)\t0x%02x" + +#: m10200-dis.c:339 +#, c-format +msgid "unknown\t0x%04lx" +msgstr "necunoscut(ã)\t0x%04lx" + +#: m10300-dis.c:766 +#, c-format +msgid "unknown\t0x%04x" +msgstr "necunoscut(ã)\t0x%04x" + +#: m68k-dis.c:429 +#, c-format +msgid "\n" +msgstr "\n" + +#: m68k-dis.c:1007 +#, c-format +msgid "" +msgstr "" + +#: m88k-dis.c:746 +#, c-format +msgid "# " +msgstr "# " + +#: mips-dis.c:699 +msgid "# internal error, incomplete extension sequence (+)" +msgstr "# eroare internã, secvenþã incompletã de extensie (+)" + +#: mips-dis.c:742 +#, c-format +msgid "# internal error, undefined extension sequence (+%c)" +msgstr "# eroare internã, secvenþã de extensie nedefinitã (+%c)" + +#: mips-dis.c:1000 +#, c-format +msgid "# internal error, undefined modifier(%c)" +msgstr "# eroare internã, modificator nedefinit(%c)" + +#: mips-dis.c:1751 +#, c-format +msgid "# internal disassembler error, unrecognised modifier (%c)" +msgstr "# eroare internã de dezasamblor, modificator necunoscut (%c)" + +#: mips-dis.c:1763 +msgid "" +"\n" +"The following MIPS specific disassembler options are supported for use\n" +"with the -M switch (multiple options should be separated by commas):\n" +msgstr "" +"\n" +"Opþiunile MIPS de dezasamblor specifice urmãtoare sunt permise cu folosirea\n" +"switch-ului -M (opþiunile multiple trebuie separate prin virgulã:\n" + +#: mips-dis.c:1767 +msgid "" +"\n" +" gpr-names=ABI Print GPR names according to specified ABI.\n" +" Default: based on binary being disassembled.\n" +msgstr "" +"\n" +" gpr-names=ABI Afiºeazã numele GPR potrivit ABI specificat.\n" +" Implicit: bazat pe binar ce este dezasamblat.\n" + +#: mips-dis.c:1771 +msgid "" +"\n" +" fpr-names=ABI Print FPR names according to specified ABI.\n" +" Default: numeric.\n" +msgstr "" +"\n" +" fpr-names=ABI Afiºeazã numele FPR potrivit ABI specificat.\n" +" Implicit: numeric.\n" + +#: mips-dis.c:1775 +msgid "" +"\n" +" cp0-names=ARCH Print CP0 register names according to\n" +" specified architecture.\n" +" Default: based on binary being disassembled.\n" +msgstr "" +"\n" +" cp0-names=ARCH Afiºeazã numele de regiºtri CP0 potrivit\n" +" arhitecturii specifice.\n" +" Implicit: bazat pe binar în dezasamblare.\n" + +#: mips-dis.c:1780 +msgid "" +"\n" +" hwr-names=ARCH Print HWR names according to specified \n" +"\t\t\t architecture.\n" +" Default: based on binary being disassembled.\n" +msgstr "" +"\n" +" hwr-names=ARCH Afiºeazã numele HWR potrivit arhitecturii \n" +"\t\t\t specifice.\n" +" Implicit: bazat pe binar în dezasamblare.\n" + +#: mips-dis.c:1785 +msgid "" +"\n" +" reg-names=ABI Print GPR and FPR names according to\n" +" specified ABI.\n" +msgstr "" +"\n" +" reg-names=ABI Afiºeazã numele GPR ºi FPR potriviti\n" +" ABI specificat.\n" + +#: mips-dis.c:1789 +msgid "" +"\n" +" reg-names=ARCH Print CP0 register and HWR names according to\n" +" specified architecture.\n" +msgstr "" +"\n" +" reg-names=ARCH Afiºeazã regiºtrii CP0 ºi numele HWR potrivit\n" +" arhitecturii specifice.\n" + +#: mips-dis.c:1793 +msgid "" +"\n" +" For the options above, the following values are supported for \"ABI\":\n" +" " +msgstr "" +"\n" +" Pentru opþiunile de mai sus, urmatoarele valori sunt suportate pentru \"ABI\":\n" +" " + +#: mips-dis.c:1798 mips-dis.c:1806 mips-dis.c:1808 +msgid "\n" +msgstr "\n" + +#: mips-dis.c:1800 +msgid "" +"\n" +" For the options above, The following values are supported for \"ARCH\":\n" +" " +msgstr "" +"\n" +" Pentru opþiunile de mai sus, urmatoarele valori sunt suportate pentru \"ARCH\":\n" +" " + +#: mmix-dis.c:34 +#, c-format +msgid "Bad case %d (%s) in %s:%d\n" +msgstr "Caz greºit %d (%s) in %s: %d\n" + +#: mmix-dis.c:44 +#, c-format +msgid "Internal: Non-debugged code (test-case missing): %s:%d" +msgstr "Intern: cod non debugged (caz test lipsã) %s:%d" + +#: mmix-dis.c:53 +msgid "(unknown)" +msgstr "(necunoscut)" + +#: mmix-dis.c:519 +#, c-format +msgid "*unknown operands type: %d*" +msgstr "*tip necunoscut de operanzi: %d*" + +#. I and Z are output operands and can`t be immediate +#. * A is an address and we can`t have the address of +#. * an immediate either. We don't know how much to increase +#. * aoffsetp by since whatever generated this is broken +#. * anyway! +#. +#: ns32k-dis.c:631 +msgid "$" +msgstr "$" + +#: ppc-opc.c:781 ppc-opc.c:809 +msgid "invalid conditional option" +msgstr "opþiune condiþionalã invalidã" + +#: ppc-opc.c:811 +msgid "attempt to set y bit when using + or - modifier" +msgstr "se încearcã setarea bitului y în folosirea modificatorilor + sau -" + +#: ppc-opc.c:840 +msgid "offset not a multiple of 16" +msgstr "offsetul nu este multiplu de 16" + +#: ppc-opc.c:860 +msgid "offset not a multiple of 2" +msgstr "offsetul nu este multiplu de 2" + +#: ppc-opc.c:862 +msgid "offset greater than 62" +msgstr "offset mai mare decât 62" + +#: ppc-opc.c:881 ppc-opc.c:927 ppc-opc.c:975 +msgid "offset not a multiple of 4" +msgstr "offsetul nu este multiplu de 4" + +#: ppc-opc.c:883 +msgid "offset greater than 124" +msgstr "offset mai mare decât 124" + +#: ppc-opc.c:902 +msgid "offset not a multiple of 8" +msgstr "offsetul nu este multiplu de 8" + +#: ppc-opc.c:904 +msgid "offset greater than 248" +msgstr "offset mai mare de 248" + +#: ppc-opc.c:950 +msgid "offset not between -2048 and 2047" +msgstr "offsetul nu este între -2048 ºi 2047" + +#: ppc-opc.c:973 +msgid "offset not between -8192 and 8191" +msgstr "offsetul nu este între -8192 ºi 8191" + +#: ppc-opc.c:1011 +msgid "ignoring invalid mfcr mask" +msgstr "se ignorã mascã mfcr invalidã" + +#: ppc-opc.c:1059 +msgid "ignoring least significant bits in branch offset" +msgstr "se ignorã cei mai puþin semnificanþi biþi în offsetul ramurii(branch)" + +#: ppc-opc.c:1090 ppc-opc.c:1125 +msgid "illegal bitmask" +msgstr "bitmask ilegal" + +#: ppc-opc.c:1192 +msgid "value out of range" +msgstr "valoare în afara intervalului" + +#: ppc-opc.c:1262 +msgid "index register in load range" +msgstr "registru index în interval de încãrcare" + +#: ppc-opc.c:1279 +msgid "source and target register operands must be different" +msgstr "operanzii regiºtri sursã ºi destinaþie trebuie sã fie diferiþi" + +#: ppc-opc.c:1294 +msgid "invalid register operand when updating" +msgstr "registru de operand invalid în updatare" + +#: ppc-opc.c:1335 +msgid "target register operand must be even" +msgstr "operandul registru destinaþie trebuie sã fie par" + +#: ppc-opc.c:1350 +msgid "source register operand must be even" +msgstr "operandul registru sursã trebuie sã fie par" + +#. Mark as non-valid instruction. +#: sparc-dis.c:760 +msgid "unknown" +msgstr "necunoscut(ã)" + +#: sparc-dis.c:835 +#, c-format +msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" +msgstr "Eroare internã: opcode.h sparc greºit: \"%s\", %#.8lx, %#.8lx\n" + +#: sparc-dis.c:846 +#, c-format +msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" +msgstr "Eroare internã: opcode.h sparc greºit: \"%s\", %#.8lx, %#.8lx\n" + +#: sparc-dis.c:895 +#, c-format +msgid "Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n" +msgstr "Eroare internã: opcode.h sparc greºit: \"%s\" == \"%s\"\n" + +#: v850-dis.c:221 +#, c-format +msgid "unknown operand shift: %x\n" +msgstr "schimbare(shift) de oberand necunoscutã: %x\n" + +#: v850-dis.c:233 +#, c-format +msgid "unknown pop reg: %d\n" +msgstr "pop reg necunoscut: %d\n" + +#. The functions used to insert and extract complicated operands. +#. Note: There is a conspiracy between these functions and +#. v850_insert_operand() in gas/config/tc-v850.c. Error messages +#. containing the string 'out of range' will be ignored unless a +#. specific command line option is given to GAS. +#: v850-opc.c:68 +msgid "displacement value is not in range and is not aligned" +msgstr "valoarea deplasãrii în afara intervalului ºi nealiniatã" + +#: v850-opc.c:69 +msgid "displacement value is out of range" +msgstr "deplasare" + +#: v850-opc.c:70 +msgid "displacement value is not aligned" +msgstr "valoarea deplasãrii nu este aliniatã" + +#: v850-opc.c:72 +msgid "immediate value is out of range" +msgstr "valoare directã(immediate) în afara intervalului" + +#: v850-opc.c:83 +msgid "branch value not in range and to odd offset" +msgstr "valoare ramurã(branch) în afara intervalului ºi la offset impar" + +#: v850-opc.c:85 v850-opc.c:117 +msgid "branch value out of range" +msgstr "valoare ramurã(branch) în afara intervalului" + +#: v850-opc.c:88 v850-opc.c:120 +msgid "branch to odd offset" +msgstr "ramurã(branch) la offset impar" + +#: v850-opc.c:115 +msgid "branch value not in range and to an odd offset" +msgstr "valoare ramurã(branch) în afara intervalului ºi la offset impar" + +#: v850-opc.c:346 +msgid "invalid register for stack adjustment" +msgstr "registru invalid pentru modificare stivã" + +#: v850-opc.c:370 +msgid "immediate value not in range and not even" +msgstr "valoare directã(immediate) în afara intervalului ºi imparã" + +#: v850-opc.c:375 +msgid "immediate value must be even" +msgstr "valoarea directã(immediate) trebuie sã fie parã" + +#: xstormy16-asm.c:76 +msgid "Bad register in preincrement" +msgstr "Registru greºit în preincrementare" + +#: xstormy16-asm.c:81 +msgid "Bad register in postincrement" +msgstr "Registru greºit în postincrementare" + +#: xstormy16-asm.c:83 +msgid "Bad register name" +msgstr "Nume registru greºit" + +#: xstormy16-asm.c:87 +msgid "Label conflicts with register name" +msgstr "Eticheta(label) se aflã în conflict cu numele de registru" + +#: xstormy16-asm.c:91 +msgid "Label conflicts with `Rx'" +msgstr "Eticheta(label) se aflã în conflict cu `Rx'" + +#: xstormy16-asm.c:93 +msgid "Bad immediate expression" +msgstr "Expresie directã(immediate) greºitã" + +#: xstormy16-asm.c:115 +msgid "No relocation for small immediate" +msgstr "Nici o relocare pentru mai mic directã(immediate)" + +#: xstormy16-asm.c:125 +msgid "Small operand was not an immediate number" +msgstr "Operandul redus nu a fost un numãr direct(immediate)" + +#: xstormy16-asm.c:164 +msgid "Operand is not a symbol" +msgstr "Operandul nu este simbol" + +#: xstormy16-asm.c:172 +msgid "Syntax error: No trailing ')'" +msgstr "Eroare de sintaxã:Nu existã ')'" diff --git a/opcodes/xtensa-dis.c b/opcodes/xtensa-dis.c new file mode 100644 index 0000000..8c31085 --- /dev/null +++ b/opcodes/xtensa-dis.c @@ -0,0 +1,524 @@ +/* xtensa-dis.c. Disassembly functions for Xtensa. + Copyright 2003 Free Software Foundation, Inc. + Contributed by Bob Wilson at Tensilica, Inc. (bwilson@tensilica.com) + + This file is part of GDB, GAS, and the GNU binutils. + + GDB, GAS, and the GNU binutils are free software; you can redistribute + them and/or modify them under the terms of the GNU General Public + License as published by the Free Software Foundation; either version 2, + or (at your option) any later version. + + GDB, GAS, and the GNU binutils are distributed in the hope that they + will be useful, but WITHOUT ANY WARRANTY; without even the implied + warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See + the GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this file; see the file COPYING. If not, write to the Free + Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, + USA. */ + +#include +#include +#include +#include +#include "xtensa-isa.h" +#include "ansidecl.h" +#include "sysdep.h" +#include "dis-asm.h" + +#include + +#ifndef MAX +#define MAX(a,b) (a > b ? a : b) +#endif + +static char* state_names[256] = +{ + "lbeg", /* 0 */ + "lend", /* 1 */ + "lcount", /* 2 */ + "sar", /* 3 */ + "br", /* 4 */ + + "reserved_5", /* 5 */ + "reserved_6", /* 6 */ + "reserved_7", /* 7 */ + + "av", /* 8 */ + "avh", /* 9 */ + "bv", /* 10 */ + "sav", /* 11 */ + "scompare1", /* 12 */ + + "reserved_13", /* 13 */ + "reserved_14", /* 14 */ + "reserved_15", /* 15 */ + + "acclo", /* 16 */ + "acchi", /* 17 */ + + "reserved_18", /* 18 */ + "reserved_19", /* 19 */ + "reserved_20", /* 20 */ + "reserved_21", /* 21 */ + "reserved_22", /* 22 */ + "reserved_23", /* 23 */ + "reserved_24", /* 24 */ + "reserved_25", /* 25 */ + "reserved_26", /* 26 */ + "reserved_27", /* 27 */ + "reserved_28", /* 28 */ + "reserved_29", /* 29 */ + "reserved_30", /* 30 */ + "reserved_31", /* 31 */ + + "mr0", /* 32 */ + "mr1", /* 33 */ + "mr2", /* 34 */ + "mr3", /* 35 */ + + "reserved_36", /* 36 */ + "reserved_37", /* 37 */ + "reserved_38", /* 38 */ + "reserved_39", /* 39 */ + "reserved_40", /* 40 */ + "reserved_41", /* 41 */ + "reserved_42", /* 42 */ + "reserved_43", /* 43 */ + "reserved_44", /* 44 */ + "reserved_45", /* 45 */ + "reserved_46", /* 46 */ + "reserved_47", /* 47 */ + "reserved_48", /* 48 */ + "reserved_49", /* 49 */ + "reserved_50", /* 50 */ + "reserved_51", /* 51 */ + "reserved_52", /* 52 */ + "reserved_53", /* 53 */ + "reserved_54", /* 54 */ + "reserved_55", /* 55 */ + "reserved_56", /* 56 */ + "reserved_57", /* 57 */ + "reserved_58", /* 58 */ + "reserved_59", /* 59 */ + "reserved_60", /* 60 */ + "reserved_61", /* 61 */ + "reserved_62", /* 62 */ + "reserved_63", /* 63 */ + + "reserved_64", /* 64 */ + "reserved_65", /* 65 */ + "reserved_66", /* 66 */ + "reserved_67", /* 67 */ + "reserved_68", /* 68 */ + "reserved_69", /* 69 */ + "reserved_70", /* 70 */ + "reserved_71", /* 71 */ + + "wb", /* 72 */ + "ws", /* 73 */ + + "reserved_74", /* 74 */ + "reserved_75", /* 75 */ + "reserved_76", /* 76 */ + "reserved_77", /* 77 */ + "reserved_78", /* 78 */ + "reserved_79", /* 79 */ + "reserved_80", /* 80 */ + "reserved_81", /* 81 */ + "reserved_82", /* 82 */ + + "ptevaddr", /* 83 */ + + "reserved_84", /* 84 */ + "reserved_85", /* 85 */ + "reserved_86", /* 86 */ + "reserved_87", /* 87 */ + "reserved_88", /* 88 */ + "reserved_89", /* 89 */ + + "rasid", /* 90 */ + "itlbcfg", /* 91 */ + "dtlbcfg", /* 92 */ + + "reserved_93", /* 93 */ + "reserved_94", /* 94 */ + "reserved_95", /* 95 */ + + "ibreakenable", /* 96 */ + + "reserved_97", /* 97 */ + + "cacheattr", /* 98 */ + + "reserved_99", /* 99 */ + "reserved_100", /* 100 */ + "reserved_101", /* 101 */ + "reserved_102", /* 102 */ + "reserved_103", /* 103 */ + + "ddr", /* 104 */ + + "reserved_105", /* 105 */ + "reserved_106", /* 106 */ + "reserved_107", /* 107 */ + "reserved_108", /* 108 */ + "reserved_109", /* 109 */ + "reserved_110", /* 110 */ + "reserved_111", /* 111 */ + "reserved_112", /* 112 */ + "reserved_113", /* 113 */ + "reserved_114", /* 114 */ + "reserved_115", /* 115 */ + "reserved_116", /* 116 */ + "reserved_117", /* 117 */ + "reserved_118", /* 118 */ + "reserved_119", /* 119 */ + "reserved_120", /* 120 */ + "reserved_121", /* 121 */ + "reserved_122", /* 122 */ + "reserved_123", /* 123 */ + "reserved_124", /* 124 */ + "reserved_125", /* 125 */ + "reserved_126", /* 126 */ + "reserved_127", /* 127 */ + + "ibreaka0", /* 128 */ + "ibreaka1", /* 129 */ + "ibreaka2", /* 130 */ + "ibreaka3", /* 131 */ + "ibreaka4", /* 132 */ + "ibreaka5", /* 133 */ + "ibreaka6", /* 134 */ + "ibreaka7", /* 135 */ + "ibreaka8", /* 136 */ + "ibreaka9", /* 137 */ + "ibreaka10", /* 138 */ + "ibreaka11", /* 139 */ + "ibreaka12", /* 140 */ + "ibreaka13", /* 141 */ + "ibreaka14", /* 142 */ + "ibreaka15", /* 143 */ + + "dbreaka0", /* 144 */ + "dbreaka1", /* 145 */ + "dbreaka2", /* 146 */ + "dbreaka3", /* 147 */ + "dbreaka4", /* 148 */ + "dbreaka5", /* 149 */ + "dbreaka6", /* 150 */ + "dbreaka7", /* 151 */ + "dbreaka8", /* 152 */ + "dbreaka9", /* 153 */ + "dbreaka10", /* 154 */ + "dbreaka11", /* 155 */ + "dbreaka12", /* 156 */ + "dbreaka13", /* 157 */ + "dbreaka14", /* 158 */ + "dbreaka15", /* 159 */ + + "dbreakc0", /* 160 */ + "dbreakc1", /* 161 */ + "dbreakc2", /* 162 */ + "dbreakc3", /* 163 */ + "dbreakc4", /* 164 */ + "dbreakc5", /* 165 */ + "dbreakc6", /* 166 */ + "dbreakc7", /* 167 */ + "dbreakc8", /* 168 */ + "dbreakc9", /* 169 */ + "dbreakc10", /* 170 */ + "dbreakc11", /* 171 */ + "dbreakc12", /* 172 */ + "dbreakc13", /* 173 */ + "dbreakc14", /* 174 */ + "dbreakc15", /* 175 */ + + "reserved_176", /* 176 */ + + "epc1", /* 177 */ + "epc2", /* 178 */ + "epc3", /* 179 */ + "epc4", /* 180 */ + "epc5", /* 181 */ + "epc6", /* 182 */ + "epc7", /* 183 */ + "epc8", /* 184 */ + "epc9", /* 185 */ + "epc10", /* 186 */ + "epc11", /* 187 */ + "epc12", /* 188 */ + "epc13", /* 189 */ + "epc14", /* 190 */ + "epc15", /* 191 */ + "depc", /* 192 */ + + "reserved_193", /* 193 */ + + "eps2", /* 194 */ + "eps3", /* 195 */ + "eps4", /* 196 */ + "eps5", /* 197 */ + "eps6", /* 198 */ + "eps7", /* 199 */ + "eps8", /* 200 */ + "eps9", /* 201 */ + "eps10", /* 202 */ + "eps11", /* 203 */ + "eps12", /* 204 */ + "eps13", /* 205 */ + "eps14", /* 206 */ + "eps15", /* 207 */ + + "reserved_208", /* 208 */ + + "excsave1", /* 209 */ + "excsave2", /* 210 */ + "excsave3", /* 211 */ + "excsave4", /* 212 */ + "excsave5", /* 213 */ + "excsave6", /* 214 */ + "excsave7", /* 215 */ + "excsave8", /* 216 */ + "excsave9", /* 217 */ + "excsave10", /* 218 */ + "excsave11", /* 219 */ + "excsave12", /* 220 */ + "excsave13", /* 221 */ + "excsave14", /* 222 */ + "excsave15", /* 223 */ + "cpenable", /* 224 */ + + "reserved_225", /* 225 */ + + "interrupt", /* 226 */ + "interrupt2", /* 227 */ + "intenable", /* 228 */ + + "reserved_229", /* 229 */ + + "ps", /* 230 */ + + "reserved_231", /* 231 */ + + "exccause", /* 232 */ + "debugcause", /* 233 */ + "ccount", /* 234 */ + "prid", /* 235 */ + "icount", /* 236 */ + "icountlvl", /* 237 */ + "excvaddr", /* 238 */ + + "reserved_239", /* 239 */ + + "ccompare0", /* 240 */ + "ccompare1", /* 241 */ + "ccompare2", /* 242 */ + "ccompare3", /* 243 */ + + "misc0", /* 244 */ + "misc1", /* 245 */ + "misc2", /* 246 */ + "misc3", /* 247 */ + + "reserved_248", /* 248 */ + "reserved_249", /* 249 */ + "reserved_250", /* 250 */ + "reserved_251", /* 251 */ + "reserved_252", /* 252 */ + "reserved_253", /* 253 */ + "reserved_254", /* 254 */ + "reserved_255", /* 255 */ +}; + + +int show_raw_fields; + +static int fetch_data + PARAMS ((struct disassemble_info *info, bfd_vma memaddr)); +static void print_xtensa_operand + PARAMS ((bfd_vma, struct disassemble_info *, xtensa_operand, + unsigned operand_val, int print_sr_name)); + +struct dis_private { + bfd_byte *byte_buf; + jmp_buf bailout; +}; + +static int +fetch_data (info, memaddr) + struct disassemble_info *info; + bfd_vma memaddr; +{ + int length, status = 0; + struct dis_private *priv = (struct dis_private *) info->private_data; + int insn_size = xtensa_insn_maxlength (xtensa_default_isa); + + /* Read the maximum instruction size, padding with zeros if we go past + the end of the text section. This code will automatically adjust + length when we hit the end of the buffer. */ + + memset (priv->byte_buf, 0, insn_size); + for (length = insn_size; length > 0; length--) + { + status = (*info->read_memory_func) (memaddr, priv->byte_buf, length, + info); + if (status == 0) + return length; + } + (*info->memory_error_func) (status, memaddr, info); + longjmp (priv->bailout, 1); + /*NOTREACHED*/ +} + + +static void +print_xtensa_operand (memaddr, info, opnd, operand_val, print_sr_name) + bfd_vma memaddr; + struct disassemble_info *info; + xtensa_operand opnd; + unsigned operand_val; + int print_sr_name; +{ + char *kind = xtensa_operand_kind (opnd); + int signed_operand_val; + + if (show_raw_fields) + { + if (operand_val < 0xa) + (*info->fprintf_func) (info->stream, "%u", operand_val); + else + (*info->fprintf_func) (info->stream, "0x%x", operand_val); + return; + } + + operand_val = xtensa_operand_decode (opnd, operand_val); + signed_operand_val = (int) operand_val; + + if (xtensa_operand_isPCRelative (opnd)) + { + operand_val = xtensa_operand_undo_reloc (opnd, operand_val, memaddr); + info->target = operand_val; + (*info->print_address_func) (info->target, info); + } + else if (!strcmp (kind, "i")) + { + if (print_sr_name + && signed_operand_val >= 0 + && signed_operand_val <= 255) + (*info->fprintf_func) (info->stream, "%s", + state_names[signed_operand_val]); + else if ((signed_operand_val > -256) && (signed_operand_val < 256)) + (*info->fprintf_func) (info->stream, "%d", signed_operand_val); + else + (*info->fprintf_func) (info->stream, "0x%x",signed_operand_val); + } + else + (*info->fprintf_func) (info->stream, "%s%u", kind, operand_val); +} + + +/* Print the Xtensa instruction at address MEMADDR on info->stream. + Returns length of the instruction in bytes. */ + +int +print_insn_xtensa (memaddr, info) + bfd_vma memaddr; + struct disassemble_info *info; +{ + unsigned operand_val; + int bytes_fetched, size, maxsize, i, noperands; + xtensa_isa isa; + xtensa_opcode opc; + char *op_name; + int print_sr_name; + struct dis_private priv; + static bfd_byte *byte_buf = NULL; + static xtensa_insnbuf insn_buffer = NULL; + + if (!xtensa_default_isa) + (void) xtensa_isa_init (); + + info->target = 0; + maxsize = xtensa_insn_maxlength (xtensa_default_isa); + + /* Set bytes_per_line to control the amount of whitespace between the hex + values and the opcode. For Xtensa, we always print one "chunk" and we + vary bytes_per_chunk to determine how many bytes to print. (objdump + would apparently prefer that we set bytes_per_chunk to 1 and vary + bytes_per_line but that makes it hard to fit 64-bit instructions on + an 80-column screen.) The value of bytes_per_line here is not exactly + right, because objdump adds an extra space for each chunk so that the + amount of whitespace depends on the chunk size. Oh well, it's good + enough.... Note that we set the minimum size to 4 to accomodate + literal pools. */ + info->bytes_per_line = MAX (maxsize, 4); + + /* Allocate buffers the first time through. */ + if (!insn_buffer) + insn_buffer = xtensa_insnbuf_alloc (xtensa_default_isa); + if (!byte_buf) + byte_buf = (bfd_byte *) malloc (MAX (maxsize, 4)); + + priv.byte_buf = byte_buf; + + info->private_data = (PTR) &priv; + if (setjmp (priv.bailout) != 0) + /* Error return. */ + return -1; + + /* Don't set "isa" before the setjmp to keep the compiler from griping. */ + isa = xtensa_default_isa; + + /* Fetch the maximum size instruction. */ + bytes_fetched = fetch_data (info, memaddr); + + /* Copy the bytes into the decode buffer. */ + memset (insn_buffer, 0, (xtensa_insnbuf_size (isa) * + sizeof (xtensa_insnbuf_word))); + xtensa_insnbuf_from_chars (isa, insn_buffer, priv.byte_buf); + + opc = xtensa_decode_insn (isa, insn_buffer); + if (opc == XTENSA_UNDEFINED + || ((size = xtensa_insn_length (isa, opc)) > bytes_fetched)) + { + (*info->fprintf_func) (info->stream, ".byte %#02x", priv.byte_buf[0]); + return 1; + } + + op_name = (char *) xtensa_opcode_name (isa, opc); + (*info->fprintf_func) (info->stream, "%s", op_name); + + print_sr_name = (!strcasecmp (op_name, "wsr") + || !strcasecmp (op_name, "xsr") + || !strcasecmp (op_name, "rsr")); + + /* Print the operands (if any). */ + noperands = xtensa_num_operands (isa, opc); + if (noperands > 0) + { + int first = 1; + + (*info->fprintf_func) (info->stream, "\t"); + for (i = 0; i < noperands; i++) + { + xtensa_operand opnd = xtensa_get_operand (isa, opc, i); + + if (first) + first = 0; + else + (*info->fprintf_func) (info->stream, ", "); + operand_val = xtensa_operand_get_field (opnd, insn_buffer); + print_xtensa_operand (memaddr, info, opnd, operand_val, + print_sr_name); + } + } + + info->bytes_per_chunk = size; + info->display_endian = info->endian; + + return size; +} + diff --git a/readline/compat.c b/readline/compat.c new file mode 100644 index 0000000..a66d210 --- /dev/null +++ b/readline/compat.c @@ -0,0 +1,113 @@ +/* compat.c -- backwards compatibility functions. */ + +/* Copyright (C) 2000 Free Software Foundation, Inc. + + This file is part of the GNU Readline Library, a library for + reading lines of text with interactive input and history editing. + + The GNU Readline Library is free software; you can redistribute it + and/or modify it under the terms of the GNU General Public License + as published by the Free Software Foundation; either version 2, or + (at your option) any later version. + + The GNU Readline Library is distributed in the hope that it will be + useful, but WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + The GNU General Public License is often shipped with GNU software, and + is generally kept in a file called COPYING or LICENSE. If you do not + have a copy of the license, write to the Free Software Foundation, + 59 Temple Place, Suite 330, Boston, MA 02111 USA. */ +#define READLINE_LIBRARY + +#if defined (HAVE_CONFIG_H) +# include +#endif + +#include + +#include "rlstdc.h" +#include "rltypedefs.h" + +extern void rl_free_undo_list PARAMS((void)); +extern int rl_maybe_save_line PARAMS((void)); +extern int rl_maybe_unsave_line PARAMS((void)); +extern int rl_maybe_replace_line PARAMS((void)); + +extern int rl_crlf PARAMS((void)); +extern int rl_ding PARAMS((void)); +extern int rl_alphabetic PARAMS((int)); + +extern char **rl_completion_matches PARAMS((const char *, rl_compentry_func_t *)); +extern char *rl_username_completion_function PARAMS((const char *, int)); +extern char *rl_filename_completion_function PARAMS((const char *, int)); + +/* Provide backwards-compatible entry points for old function names. */ + +void +free_undo_list () +{ + rl_free_undo_list (); +} + +int +maybe_replace_line () +{ + return rl_maybe_replace_line (); +} + +int +maybe_save_line () +{ + return rl_maybe_save_line (); +} + +int +maybe_unsave_line () +{ + return rl_maybe_unsave_line (); +} + +int +ding () +{ + return rl_ding (); +} + +int +crlf () +{ + return rl_crlf (); +} + +int +alphabetic (c) + int c; +{ + return rl_alphabetic (c); +} + +char ** +completion_matches (s, f) + const char *s; + rl_compentry_func_t *f; +{ + return rl_completion_matches (s, f); +} + +char * +username_completion_function (s, i) + const char *s; + int i; +{ + return rl_username_completion_function (s, i); +} + +char * +filename_completion_function (s, i) + const char *s; + int i; +{ + return rl_filename_completion_function (s, i); +} diff --git a/readline/doc/history.3 b/readline/doc/history.3 new file mode 100644 index 0000000..ed0cb9f --- /dev/null +++ b/readline/doc/history.3 @@ -0,0 +1,640 @@ +.\" +.\" MAN PAGE COMMENTS to +.\" +.\" Chet Ramey +.\" Information Network Services +.\" Case Western Reserve University +.\" chet@ins.CWRU.Edu +.\" +.\" Last Change: Thu Jan 31 16:08:07 EST 2002 +.\" +.TH HISTORY 3 "2002 January 31" "GNU History 4.3" +.\" +.\" File Name macro. This used to be `.PN', for Path Name, +.\" but Sun doesn't seem to like that very much. +.\" +.de FN +\fI\|\\$1\|\fP +.. +.ds lp \fR\|(\fP +.ds rp \fR\|)\fP +.\" FnN return-value fun-name N arguments +.de Fn1 +\fI\\$1\fP \fB\\$2\fP \\*(lp\fI\\$3\fP\\*(rp +.br +.. +.de Fn2 +.if t \fI\\$1\fP \fB\\$2\fP \\*(lp\fI\\$3,\|\\$4\fP\\*(rp +.if n \fI\\$1\fP \fB\\$2\fP \\*(lp\fI\\$3, \\$4\fP\\*(rp +.br +.. +.de Fn3 +.if t \fI\\$1\fP \fB\\$2\fP \\*(lp\fI\\$3,\|\\$4,\|\\$5\fP\|\\*(rp +.if n \fI\\$1\fP \fB\\$2\fP \\*(lp\fI\\$3, \\$4, \\$5\fP\\*(rp +.br +.. +.de Vb +\fI\\$1\fP \fB\\$2\fP +.br +.. +.SH NAME +history \- GNU History Library +.SH COPYRIGHT +.if t The GNU History Library is Copyright \(co 1989-2002 by the Free Software Foundation, Inc. +.if n The GNU History Library is Copyright (C) 1989-2002 by the Free Software Foundation, Inc. +.SH DESCRIPTION +Many programs read input from the user a line at a time. The GNU +History library is able to keep track of those lines, associate arbitrary +data with each line, and utilize information from previous lines in +composing new ones. +.PP +.SH "HISTORY EXPANSION" +.PP +The history library supports a history expansion feature that +is identical to the history expansion in +.BR bash. +This section describes what syntax features are available. +.PP +History expansions introduce words from the history list into +the input stream, making it easy to repeat commands, insert the +arguments to a previous command into the current input line, or +fix errors in previous commands quickly. +.PP +History expansion is usually performed immediately after a complete line +is read. +It takes place in two parts. +The first is to determine which line from the history list +to use during substitution. +The second is to select portions of that line for inclusion into +the current one. +The line selected from the history is the \fIevent\fP, +and the portions of that line that are acted upon are \fIwords\fP. +Various \fImodifiers\fP are available to manipulate the selected words. +The line is broken into words in the same fashion as \fBbash\fP +does when reading input, +so that several words that would otherwise be separated +are considered one word when surrounded by quotes (see the +description of \fBhistory_tokenize()\fP below). +History expansions are introduced by the appearance of the +history expansion character, which is \^\fB!\fP\^ by default. +Only backslash (\^\fB\e\fP\^) and single quotes can quote +the history expansion character. +.SS Event Designators +.PP +An event designator is a reference to a command line entry in the +history list. +.PP +.PD 0 +.TP +.B ! +Start a history substitution, except when followed by a +.BR blank , +newline, = or (. +.TP +.B !\fIn\fR +Refer to command line +.IR n . +.TP +.B !\-\fIn\fR +Refer to the current command line minus +.IR n . +.TP +.B !! +Refer to the previous command. This is a synonym for `!\-1'. +.TP +.B !\fIstring\fR +Refer to the most recent command starting with +.IR string . +.TP +.B !?\fIstring\fR\fB[?]\fR +Refer to the most recent command containing +.IR string . +The trailing \fB?\fP may be omitted if +.I string +is followed immediately by a newline. +.TP +.B \d\s+2^\s-2\u\fIstring1\fP\d\s+2^\s-2\u\fIstring2\fP\d\s+2^\s-2\u +Quick substitution. Repeat the last command, replacing +.I string1 +with +.IR string2 . +Equivalent to +``!!:s/\fIstring1\fP/\fIstring2\fP/'' +(see \fBModifiers\fP below). +.TP +.B !# +The entire command line typed so far. +.PD +.SS Word Designators +.PP +Word designators are used to select desired words from the event. +A +.B : +separates the event specification from the word designator. +It may be omitted if the word designator begins with a +.BR ^ , +.BR $ , +.BR * , +.BR \- , +or +.BR % . +Words are numbered from the beginning of the line, +with the first word being denoted by 0 (zero). +Words are inserted into the current line separated by single spaces. +.PP +.PD 0 +.TP +.B 0 (zero) +The zeroth word. For the shell, this is the command +word. +.TP +.I n +The \fIn\fRth word. +.TP +.B ^ +The first argument. That is, word 1. +.TP +.B $ +The last argument. +.TP +.B % +The word matched by the most recent `?\fIstring\fR?' search. +.TP +.I x\fB\-\fPy +A range of words; `\-\fIy\fR' abbreviates `0\-\fIy\fR'. +.TP +.B * +All of the words but the zeroth. This is a synonym +for `\fI1\-$\fP'. It is not an error to use +.B * +if there is just one +word in the event; the empty string is returned in that case. +.TP +.B x* +Abbreviates \fIx\-$\fP. +.TP +.B x\- +Abbreviates \fIx\-$\fP like \fBx*\fP, but omits the last word. +.PD +.PP +If a word designator is supplied without an event specification, the +previous command is used as the event. +.SS Modifiers +.PP +After the optional word designator, there may appear a sequence of +one or more of the following modifiers, each preceded by a `:'. +.PP +.PD 0 +.PP +.TP +.B h +Remove a trailing file name component, leaving only the head. +.TP +.B t +Remove all leading file name components, leaving the tail. +.TP +.B r +Remove a trailing suffix of the form \fI.xxx\fP, leaving the +basename. +.TP +.B e +Remove all but the trailing suffix. +.TP +.B p +Print the new command but do not execute it. +.TP +.B q +Quote the substituted words, escaping further substitutions. +.TP +.B x +Quote the substituted words as with +.BR q , +but break into words at +.B blanks +and newlines. +.TP +.B s/\fIold\fP/\fInew\fP/ +Substitute +.I new +for the first occurrence of +.I old +in the event line. Any delimiter can be used in place of /. The +final delimiter is optional if it is the last character of the +event line. The delimiter may be quoted in +.I old +and +.I new +with a single backslash. If & appears in +.IR new , +it is replaced by +.IR old . +A single backslash will quote the &. If +.I old +is null, it is set to the last +.I old +substituted, or, if no previous history substitutions took place, +the last +.I string +in a +.B !?\fIstring\fR\fB[?]\fR +search. +.TP +.B & +Repeat the previous substitution. +.TP +.B g +Cause changes to be applied over the entire event line. This is +used in conjunction with `\fB:s\fP' (e.g., `\fB:gs/\fIold\fP/\fInew\fP/\fR') +or `\fB:&\fP'. If used with +`\fB:s\fP', any delimiter can be used +in place of /, and the final delimiter is optional +if it is the last character of the event line. +.PD +.SH "PROGRAMMING WITH HISTORY FUNCTIONS" +This section describes how to use the History library in other programs. +.SS Introduction to History +.PP +The programmer using the History library has available functions +for remembering lines on a history list, associating arbitrary data +with a line, removing lines from the list, searching through the list +for a line containing an arbitrary text string, and referencing any line +in the list directly. In addition, a history \fIexpansion\fP function +is available which provides for a consistent user interface across +different programs. +.PP +The user using programs written with the History library has the +benefit of a consistent user interface with a set of well-known +commands for manipulating the text of previous lines and using that text +in new commands. The basic history manipulation commands are +identical to +the history substitution provided by \fBbash\fP. +.PP +If the programmer desires, he can use the Readline library, which +includes some history manipulation by default, and has the added +advantage of command line editing. +.PP +Before declaring any functions using any functionality the History +library provides in other code, an application writer should include +the file +.FN +in any file that uses the +History library's features. It supplies extern declarations for all +of the library's public functions and variables, and declares all of +the public data structures. + +.SS History Storage +.PP +The history list is an array of history entries. A history entry is +declared as follows: +.PP +.Vb "typedef void *" histdata_t; +.PP +.nf +typedef struct _hist_entry { + char *line; + histdata_t data; +} HIST_ENTRY; +.fi +.PP +The history list itself might therefore be declared as +.PP +.Vb "HIST_ENTRY **" the_history_list; +.PP +The state of the History library is encapsulated into a single structure: +.PP +.nf +/* + * A structure used to pass around the current state of the history. + */ +typedef struct _hist_state { + HIST_ENTRY **entries; /* Pointer to the entries themselves. */ + int offset; /* The location pointer within this array. */ + int length; /* Number of elements within this array. */ + int size; /* Number of slots allocated to this array. */ + int flags; +} HISTORY_STATE; +.fi +.PP +If the flags member includes \fBHS_STIFLED\fP, the history has been +stifled. +.SH "History Functions" +.PP +This section describes the calling sequence for the various functions +exported by the GNU History library. +.SS Initializing History and State Management +This section describes functions used to initialize and manage +the state of the History library when you want to use the history +functions in your program. + +.Fn1 void using_history void +Begin a session in which the history functions might be used. This +initializes the interactive variables. + +.Fn1 "HISTORY_STATE *" history_get_history_state void +Return a structure describing the current state of the input history. + +.Fn1 void history_set_history_state "HISTORY_STATE *state" +Set the state of the history list according to \fIstate\fP. + +.SS History List Management + +These functions manage individual entries on the history list, or set +parameters managing the list itself. + +.Fn1 void add_history "const char *string" +Place \fIstring\fP at the end of the history list. The associated data +field (if any) is set to \fBNULL\fP. + +.Fn1 "HIST_ENTRY *" remove_history "int which" +Remove history entry at offset \fIwhich\fP from the history. The +removed element is returned so you can free the line, data, +and containing structure. + +.Fn3 "HIST_ENTRY *" replace_history_entry "int which" "const char *line" "histdata_t data" +Make the history entry at offset \fIwhich\fP have \fIline\fP and \fIdata\fP. +This returns the old entry so you can dispose of the data. In the case +of an invalid \fIwhich\fP, a \fBNULL\fP pointer is returned. + +.Fn1 void clear_history "void" +Clear the history list by deleting all the entries. + +.Fn1 void stifle_history "int max" +Stifle the history list, remembering only the last \fImax\fP entries. + +.Fn1 int unstifle_history "void" +Stop stifling the history. This returns the previously-set +maximum number of history entries (as set by \fBstifle_history()\fP). +history was stifled. The value is positive if the history was +stifled, negative if it wasn't. + +.Fn1 int history_is_stifled "void" +Returns non-zero if the history is stifled, zero if it is not. + +.SS Information About the History List + +These functions return information about the entire history list or +individual list entries. + +.Fn1 "HIST_ENTRY **" history_list "void" +Return a \fBNULL\fP terminated array of \fIHIST_ENTRY *\fP which is the +current input history. Element 0 of this list is the beginning of time. +If there is no history, return \fBNULL\fP. + +.Fn1 int where_history "void" +Returns the offset of the current history element. + +.Fn1 "HIST_ENTRY *" current_history "void" +Return the history entry at the current position, as determined by +\fBwhere_history()\fP. If there is no entry there, return a \fBNULL\fP +pointer. + +.Fn1 "HIST_ENTRY *" history_get "int offset" +Return the history entry at position \fIoffset\fP, starting from +\fBhistory_base\fP. +If there is no entry there, or if \fIoffset\fP +is greater than the history length, return a \fBNULL\fP pointer. + +.Fn1 int history_total_bytes "void" +Return the number of bytes that the primary history entries are using. +This function returns the sum of the lengths of all the lines in the +history. + +.SS Moving Around the History List + +These functions allow the current index into the history list to be +set or changed. + +.Fn1 int history_set_pos "int pos" +Set the current history offset to \fIpos\fP, an absolute index +into the list. +Returns 1 on success, 0 if \fIpos\fP is less than zero or greater +than the number of history entries. + +.Fn1 "HIST_ENTRY *" previous_history "void" +Back up the current history offset to the previous history entry, and +return a pointer to that entry. If there is no previous entry, return +a \fBNULL\fP pointer. + +.Fn1 "HIST_ENTRY *" next_history "void" +Move the current history offset forward to the next history entry, and +return the a pointer to that entry. If there is no next entry, return +a \fBNULL\fP pointer. + +.SS Searching the History List + +These functions allow searching of the history list for entries containing +a specific string. Searching may be performed both forward and backward +from the current history position. The search may be \fIanchored\fP, +meaning that the string must match at the beginning of the history entry. + +.Fn2 int history_search "const char *string" "int direction" +Search the history for \fIstring\fP, starting at the current history offset. +If \fIdirection\fP is less than 0, then the search is through +previous entries, otherwise through subsequent entries. +If \fIstring\fP is found, then +the current history index is set to that history entry, and the value +returned is the offset in the line of the entry where +\fIstring\fP was found. Otherwise, nothing is changed, and a -1 is +returned. + +.Fn2 int history_search_prefix "const char *string" "int direction" +Search the history for \fIstring\fP, starting at the current history +offset. The search is anchored: matching lines must begin with +\fIstring\fP. If \fIdirection\fP is less than 0, then the search is +through previous entries, otherwise through subsequent entries. +If \fIstring\fP is found, then the +current history index is set to that entry, and the return value is 0. +Otherwise, nothing is changed, and a -1 is returned. + +.Fn3 int history_search_pos "const char *string" "int direction" "int pos" +Search for \fIstring\fP in the history list, starting at \fIpos\fP, an +absolute index into the list. If \fIdirection\fP is negative, the search +proceeds backward from \fIpos\fP, otherwise forward. Returns the absolute +index of the history element where \fIstring\fP was found, or -1 otherwise. + +.SS Managing the History File +The History library can read the history from and write it to a file. +This section documents the functions for managing a history file. + +.Fn1 int read_history "const char *filename" +Add the contents of \fIfilename\fP to the history list, a line at a time. +If \fIfilename\fP is \fBNULL\fP, then read from \fI~/.history\fP. +Returns 0 if successful, or \fBerrno\fP if not. + +.Fn3 int read_history_range "const char *filename" "int from" "int to" +Read a range of lines from \fIfilename\fP, adding them to the history list. +Start reading at line \fIfrom\fP and end at \fIto\fP. +If \fIfrom\fP is zero, start at the beginning. If \fIto\fP is less than +\fIfrom\fP, then read until the end of the file. If \fIfilename\fP is +\fBNULL\fP, then read from \fI~/.history\fP. Returns 0 if successful, +or \fBerrno\fP if not. + +.Fn1 int write_history "const char *filename" +Write the current history to \fIfilename\fP, overwriting \fIfilename\fP +if necessary. +If \fIfilename\fP is \fBNULL\fP, then write the history list to \fI~/.history\fP. +Returns 0 on success, or \fBerrno\fP on a read or write error. + + +.Fn2 int append_history "int nelements" "const char *filename" +Append the last \fInelements\fP of the history list to \fIfilename\fP. +If \fIfilename\fP is \fBNULL\fP, then append to \fI~/.history\fP. +Returns 0 on success, or \fBerrno\fP on a read or write error. + +.Fn2 int history_truncate_file "const char *filename" "int nlines" +Truncate the history file \fIfilename\fP, leaving only the last +\fInlines\fP lines. +If \fIfilename\fP is \fBNULL\fP, then \fI~/.history\fP is truncated. +Returns 0 on success, or \fBerrno\fP on failure. + +.SS History Expansion + +These functions implement history expansion. + +.Fn2 int history_expand "char *string" "char **output" +Expand \fIstring\fP, placing the result into \fIoutput\fP, a pointer +to a string. Returns: +.RS +.PD 0 +.TP +0 +If no expansions took place (or, if the only change in +the text was the removal of escape characters preceding the history expansion +character); +.TP +1 +if expansions did take place; +.TP +-1 +if there was an error in expansion; +.TP +2 +if the returned line should be displayed, but not executed, +as with the \fB:p\fP modifier. +.PD +.RE +If an error ocurred in expansion, then \fIoutput\fP contains a descriptive +error message. + +.Fn3 "char *" get_history_event "const char *string" "int *cindex" "int qchar" +Returns the text of the history event beginning at \fIstring\fP + +\fI*cindex\fP. \fI*cindex\fP is modified to point to after the event +specifier. At function entry, \fIcindex\fP points to the index into +\fIstring\fP where the history event specification begins. \fIqchar\fP +is a character that is allowed to end the event specification in addition +to the ``normal'' terminating characters. + +.Fn1 "char **" history_tokenize "const char *string" +Return an array of tokens parsed out of \fIstring\fP, much as the +shell might. +The tokens are split on the characters in the +\fBhistory_word_delimiters\fP variable, +and shell quoting conventions are obeyed. + +.Fn3 "char *" history_arg_extract "int first" "int last" "const char *string" +Extract a string segment consisting of the \fIfirst\fP through \fIlast\fP +arguments present in \fIstring\fP. Arguments are split using +\fBhistory_tokenize()\fP. + +.SS History Variables + +This section describes the externally-visible variables exported by +the GNU History Library. + +.Vb int history_base +The logical offset of the first entry in the history list. + +.Vb int history_length +The number of entries currently stored in the history list. + +.Vb int history_max_entries +The maximum number of history entries. This must be changed using +\fBstifle_history()\fP. + +.Vb char history_expansion_char +The character that introduces a history event. The default is \fB!\fP. +Setting this to 0 inhibits history expansion. + +.Vb char history_subst_char +The character that invokes word substitution if found at the start of +a line. The default is \fB^\fP. + +.Vb char history_comment_char +During tokenization, if this character is seen as the first character +of a word, then it and all subsequent characters up to a newline are +ignored, suppressing history expansion for the remainder of the line. +This is disabled by default. + +.Vb "char *" history_word_delimiters +The characters that separate tokens for \fBhistory_tokenize()\fP. +The default value is \fB"\ \et\en()<>;&|"\fP. + +.Vb "char *" history_no_expand_chars +The list of characters which inhibit history expansion if found immediately +following \fBhistory_expansion_char\fP. The default is space, tab, newline, +\fB\er\fP, and \fB=\fP. + +.Vb "char *" history_search_delimiter_chars +The list of additional characters which can delimit a history search +string, in addition to space, tab, \fI:\fP and \fI?\fP in the case of +a substring search. The default is empty. + +.Vb int history_quotes_inhibit_expansion +If non-zero, single-quoted words are not scanned for the history expansion +character. The default value is 0. + +.Vb "rl_linebuf_func_t *" history_inhibit_expansion_function +This should be set to the address of a function that takes two arguments: +a \fBchar *\fP (\fIstring\fP) +and an \fBint\fP index into that string (\fIi\fP). +It should return a non-zero value if the history expansion starting at +\fIstring[i]\fP should not be performed; zero if the expansion should +be done. +It is intended for use by applications like \fBbash\fP that use the history +expansion character for additional purposes. +By default, this variable is set to \fBNULL\fP. +.SH FILES +.PD 0 +.TP +.FN ~/.history +Default filename for reading and writing saved history +.PD +.SH "SEE ALSO" +.PD 0 +.TP +\fIThe Gnu Readline Library\fP, Brian Fox and Chet Ramey +.TP +\fIThe Gnu History Library\fP, Brian Fox and Chet Ramey +.TP +\fIbash\fP(1) +.TP +\fIreadline\fP(3) +.PD +.SH AUTHORS +Brian Fox, Free Software Foundation +.br +bfox@gnu.org +.PP +Chet Ramey, Case Western Reserve University +.br +chet@ins.CWRU.Edu +.SH BUG REPORTS +If you find a bug in the +.B history +library, you should report it. But first, you should +make sure that it really is a bug, and that it appears in the latest +version of the +.B history +library that you have. +.PP +Once you have determined that a bug actually exists, mail a +bug report to \fIbug\-readline\fP@\fIgnu.org\fP. +If you have a fix, you are welcome to mail that +as well! Suggestions and `philosophical' bug reports may be mailed +to \fPbug-readline\fP@\fIgnu.org\fP or posted to the Usenet +newsgroup +.BR gnu.bash.bug . +.PP +Comments and bug reports concerning +this manual page should be directed to +.IR chet@ins.CWRU.Edu . diff --git a/readline/examples/readlinebuf.h b/readline/examples/readlinebuf.h new file mode 100644 index 0000000..91ef4d6 --- /dev/null +++ b/readline/examples/readlinebuf.h @@ -0,0 +1,139 @@ +/******************************************************************************* + * $Revision$ + * $Date$ + * $Author$ + * + * Contents: A streambuf which uses the GNU readline library for line I/O + * (c) 2001 by Dimitris Vyzovitis [vyzo@media.mit.edu] + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this program; if not, write to the Free + * Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + ******************************************************************************/ + +#ifndef _READLINEBUF_H_ +#define _READLINEBUF_H_ + +#include +#include +#include +#include +#include + +#include +#include + +#if (defined __GNUC__) && (__GNUC__ < 3) +#include +#else +#include +using std::streamsize; +using std::streambuf; +#endif + +class readlinebuf : public streambuf { +public: +#if (defined __GNUC__) && (__GNUC__ < 3) + typedef char char_type; + typedef int int_type; + typedef streampos pos_type; + typedef streamoff off_type; +#endif + static const int_type eof = EOF; // this is -1 + static const int_type not_eof = 0; + +private: + const char* prompt_; + bool history_; + char* line_; + int low_; + int high_; + +protected: + + virtual int_type showmanyc() const { return high_ - low_; } + + virtual streamsize xsgetn( char_type* buf, streamsize n ) { + int rd = n > (high_ - low_)? (high_ - low_) : n; + memcpy( buf, line_, rd ); + low_ += rd; + + if ( rd < n ) { + low_ = high_ = 0; + free( line_ ); // free( NULL ) is a noop + line_ = readline( prompt_ ); + if ( line_ ) { + high_ = strlen( line_ ); + if ( history_ && high_ ) add_history( line_ ); + rd += xsgetn( buf + rd, n - rd ); + } + } + + return rd; + } + + virtual int_type underflow() { + if ( high_ == low_ ) { + low_ = high_ = 0; + free( line_ ); // free( NULL ) is a noop + line_ = readline( prompt_ ); + if ( line_ ) { + high_ = strlen( line_ ); + if ( history_ && high_ ) add_history( line_ ); + } + } + + if ( low_ < high_ ) return line_[low_]; + else return eof; + } + + virtual int_type uflow() { + int_type c = underflow(); + if ( c != eof ) ++low_; + return c; + } + + virtual int_type pbackfail( int_type c = eof ) { + if ( low_ > 0 ) --low_; + else if ( c != eof ) { + if ( high_ > 0 ) { + char* nl = (char*)realloc( line_, high_ + 1 ); + if ( nl ) { + line_ = (char*)memcpy( nl + 1, line_, high_ ); + high_ += 1; + line_[0] = char( c ); + } else return eof; + } else { + assert( !line_ ); + line_ = (char*)malloc( sizeof( char ) ); + *line_ = char( c ); + high_ = 1; + } + } else return eof; + + return not_eof; + } + +public: + readlinebuf( const char* prompt = NULL, bool history = true ) + : prompt_( prompt ), history_( history ), + line_( NULL ), low_( 0 ), high_( 0 ) { + setbuf( 0, 0 ); + } + + +}; + +#endif diff --git a/readline/examples/rlcat.c b/readline/examples/rlcat.c new file mode 100644 index 0000000..176b9f4 --- /dev/null +++ b/readline/examples/rlcat.c @@ -0,0 +1,174 @@ +/* + * rlcat - cat(1) using readline + * + * usage: rlcat + */ + +/* Copyright (C) 1987-2002 Free Software Foundation, Inc. + + This file is part of the GNU Readline Library, a library for + reading lines of text with interactive input and history editing. + + The GNU Readline Library is free software; you can redistribute it + and/or modify it under the terms of the GNU General Public License + as published by the Free Software Foundation; either version 2, or + (at your option) any later version. + + The GNU Readline Library is distributed in the hope that it will be + useful, but WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + The GNU General Public License is often shipped with GNU software, and + is generally kept in a file called COPYING or LICENSE. If you do not + have a copy of the license, write to the Free Software Foundation, + 59 Temple Place, Suite 330, Boston, MA 02111 USA. */ + +#if defined (HAVE_CONFIG_H) +# include +#endif + +#ifdef HAVE_UNISTD_H +# include +#endif + +#include +#include "posixstat.h" + +#include +#include +#include +#include + +#ifndef errno +extern int errno; +#endif + +#if defined (READLINE_LIBRARY) +# include "readline.h" +# include "history.h" +#else +# include +# include +#endif + +extern int optind; +extern char *optarg; + +static int stdcat(); + +static char *progname; +static int vflag; + +static void +usage() +{ + fprintf (stderr, "%s: usage: %s [-vEVN] [filename]\n", progname, progname); +} + +int +main (argc, argv) + int argc; + char **argv; +{ + char *temp; + int opt, Vflag, Nflag; + + progname = strrchr(argv[0], '/'); + if (progname == 0) + progname = argv[0]; + else + progname++; + + vflag = Vflag = Nflag = 0; + while ((opt = getopt(argc, argv, "vEVN")) != EOF) + { + switch (opt) + { + case 'v': + vflag = 1; + break; + case 'V': + Vflag = 1; + break; + case 'E': + Vflag = 0; + break; + case 'N': + Nflag = 1; + break; + default: + usage (); + exit (2); + } + } + + argc -= optind; + argv += optind; + + if (isatty(0) == 0 || argc || Nflag) + return stdcat(argc, argv); + + rl_variable_bind ("editing-mode", Vflag ? "vi" : "emacs"); + while (temp = readline ("")) + { + if (*temp) + add_history (temp); + printf ("%s\n", temp); + } + + return (ferror (stdout)); +} + +static int +fcopy(fp) + FILE *fp; +{ + int c; + char *x; + + while ((c = getc(fp)) != EOF) + { + if (vflag && isascii ((unsigned char)c) && isprint((unsigned char)c) == 0) + { + x = rl_untranslate_keyseq (c); + if (fputs (x, stdout) != 0) + return 1; + } + else if (putchar (c) == EOF) + return 1; + } + return (ferror (stdout)); +} + +int +stdcat (argc, argv) + int argc; + char **argv; +{ + int i, fd, r; + char *s; + FILE *fp; + + if (argc == 0) + return (fcopy(stdin)); + + for (i = 0, r = 1; i < argc; i++) + { + if (*argv[i] == '-' && argv[i][1] == 0) + fp = stdin; + else + { + fp = fopen (argv[i], "r"); + if (fp == 0) + { + fprintf (stderr, "%s: %s: cannot open: %s\n", progname, argv[i], strerror(errno)); + continue; + } + } + r = fcopy (fp); + if (fp != stdin) + fclose(fp); + } + return r; +} diff --git a/readline/mbutil.c b/readline/mbutil.c new file mode 100644 index 0000000..50302f0 --- /dev/null +++ b/readline/mbutil.c @@ -0,0 +1,337 @@ +/* mbutil.c -- readline multibyte character utility functions */ + +/* Copyright (C) 2001 Free Software Foundation, Inc. + + This file is part of the GNU Readline Library, a library for + reading lines of text with interactive input and history editing. + + The GNU Readline Library is free software; you can redistribute it + and/or modify it under the terms of the GNU General Public License + as published by the Free Software Foundation; either version 2, or + (at your option) any later version. + + The GNU Readline Library is distributed in the hope that it will be + useful, but WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + The GNU General Public License is often shipped with GNU software, and + is generally kept in a file called COPYING or LICENSE. If you do not + have a copy of the license, write to the Free Software Foundation, + 59 Temple Place, Suite 330, Boston, MA 02111 USA. */ +#define READLINE_LIBRARY + +#if defined (HAVE_CONFIG_H) +# include +#endif + +#include +#include +#include "posixjmp.h" + +#if defined (HAVE_UNISTD_H) +# include /* for _POSIX_VERSION */ +#endif /* HAVE_UNISTD_H */ + +#if defined (HAVE_STDLIB_H) +# include +#else +# include "ansi_stdlib.h" +#endif /* HAVE_STDLIB_H */ + +#include +#include + +/* System-specific feature definitions and include files. */ +#include "rldefs.h" +#include "rlmbutil.h" + +#if defined (TIOCSTAT_IN_SYS_IOCTL) +# include +#endif /* TIOCSTAT_IN_SYS_IOCTL */ + +/* Some standard library routines. */ +#include "readline.h" + +#include "rlprivate.h" +#include "xmalloc.h" + +/* Declared here so it can be shared between the readline and history + libraries. */ +#if defined (HANDLE_MULTIBYTE) +int rl_byte_oriented = 0; +#else +int rl_byte_oriented = 1; +#endif + +/* **************************************************************** */ +/* */ +/* Multibyte Character Utility Functions */ +/* */ +/* **************************************************************** */ + +#if defined(HANDLE_MULTIBYTE) + +static int +_rl_find_next_mbchar_internal (string, seed, count, find_non_zero) + char *string; + int seed, count, find_non_zero; +{ + size_t tmp = 0; + mbstate_t ps; + int point = 0; + wchar_t wc; + + memset(&ps, 0, sizeof (mbstate_t)); + if (seed < 0) + seed = 0; + if (count <= 0) + return seed; + + point = seed + _rl_adjust_point(string, seed, &ps); + /* if this is true, means that seed was not pointed character + started byte. So correct the point and consume count */ + if (seed < point) + count --; + + while (count > 0) + { + tmp = mbrtowc (&wc, string+point, strlen(string + point), &ps); + if ((size_t)(tmp) == (size_t)-1 || (size_t)(tmp) == (size_t)-2) + { + /* invalid bytes. asume a byte represents a character */ + point++; + count--; + /* reset states. */ + memset(&ps, 0, sizeof(mbstate_t)); + } + else if (tmp == (size_t)0) + /* found '\0' char */ + break; + else + { + /* valid bytes */ + point += tmp; + if (find_non_zero) + { + if (wcwidth (wc) == 0) + continue; + else + count--; + } + else + count--; + } + } + + if (find_non_zero) + { + tmp = mbrtowc (&wc, string + point, strlen (string + point), &ps); + while (wcwidth (wc) == 0) + { + point += tmp; + tmp = mbrtowc (&wc, string + point, strlen (string + point), &ps); + if (tmp == (size_t)(0) || tmp == (size_t)(-1) || tmp == (size_t)(-2)) + break; + } + } + return point; +} + +static int +_rl_find_prev_mbchar_internal (string, seed, find_non_zero) + char *string; + int seed, find_non_zero; +{ + mbstate_t ps; + int prev, non_zero_prev, point, length; + size_t tmp; + wchar_t wc; + + memset(&ps, 0, sizeof(mbstate_t)); + length = strlen(string); + + if (seed < 0) + return 0; + else if (length < seed) + return length; + + prev = non_zero_prev = point = 0; + while (point < seed) + { + tmp = mbrtowc (&wc, string + point, length - point, &ps); + if ((size_t)(tmp) == (size_t)-1 || (size_t)(tmp) == (size_t)-2) + { + /* in this case, bytes are invalid or shorted to compose + multibyte char, so assume that the first byte represents + a single character anyway. */ + tmp = 1; + /* clear the state of the byte sequence, because + in this case effect of mbstate is undefined */ + memset(&ps, 0, sizeof (mbstate_t)); + } + else if (tmp == 0) + break; /* Found '\0' char. Can this happen? */ + else + { + if (find_non_zero) + { + if (wcwidth (wc) != 0) + prev = point; + } + else + prev = point; + } + + point += tmp; + } + + return prev; +} + +/* return the number of bytes parsed from the multibyte sequence starting + at src, if a non-L'\0' wide character was recognized. It returns 0, + if a L'\0' wide character was recognized. It returns (size_t)(-1), + if an invalid multibyte sequence was encountered. It returns (size_t)(-2) + if it couldn't parse a complete multibyte character. */ +int +_rl_get_char_len (src, ps) + char *src; + mbstate_t *ps; +{ + size_t tmp; + + tmp = mbrlen((const char *)src, (size_t)strlen (src), ps); + if (tmp == (size_t)(-2)) + { + /* shorted to compose multibyte char */ + memset (ps, 0, sizeof(mbstate_t)); + return -2; + } + else if (tmp == (size_t)(-1)) + { + /* invalid to compose multibyte char */ + /* initialize the conversion state */ + memset (ps, 0, sizeof(mbstate_t)); + return -1; + } + else if (tmp == (size_t)0) + return 0; + else + return (int)tmp; +} + +/* compare the specified two characters. If the characters matched, + return 1. Otherwise return 0. */ +int +_rl_compare_chars (buf1, pos1, ps1, buf2, pos2, ps2) + char *buf1, *buf2; + mbstate_t *ps1, *ps2; + int pos1, pos2; +{ + int i, w1, w2; + + if ((w1 = _rl_get_char_len (&buf1[pos1], ps1)) <= 0 || + (w2 = _rl_get_char_len (&buf2[pos2], ps2)) <= 0 || + (w1 != w2) || + (buf1[pos1] != buf2[pos2])) + return 0; + + for (i = 1; i < w1; i++) + if (buf1[pos1+i] != buf2[pos2+i]) + return 0; + + return 1; +} + +/* adjust pointed byte and find mbstate of the point of string. + adjusted point will be point <= adjusted_point, and returns + differences of the byte(adjusted_point - point). + if point is invalied (point < 0 || more than string length), + it returns -1 */ +int +_rl_adjust_point(string, point, ps) + char *string; + int point; + mbstate_t *ps; +{ + size_t tmp = 0; + int length; + int pos = 0; + + length = strlen(string); + if (point < 0) + return -1; + if (length < point) + return -1; + + while (pos < point) + { + tmp = mbrlen (string + pos, length - pos, ps); + if((size_t)(tmp) == (size_t)-1 || (size_t)(tmp) == (size_t)-2) + { + /* in this case, bytes are invalid or shorted to compose + multibyte char, so assume that the first byte represents + a single character anyway. */ + pos++; + /* clear the state of the byte sequence, because + in this case effect of mbstate is undefined */ + memset (ps, 0, sizeof (mbstate_t)); + } + else + pos += tmp; + } + + return (pos - point); +} + +int +_rl_is_mbchar_matched (string, seed, end, mbchar, length) + char *string; + int seed, end; + char *mbchar; + int length; +{ + int i; + + if ((end - seed) < length) + return 0; + + for (i = 0; i < length; i++) + if (string[seed + i] != mbchar[i]) + return 0; + return 1; +} +#endif /* HANDLE_MULTIBYTE */ + +/* Find next `count' characters started byte point of the specified seed. + If flags is MB_FIND_NONZERO, we look for non-zero-width multibyte + characters. */ +#undef _rl_find_next_mbchar +int +_rl_find_next_mbchar (string, seed, count, flags) + char *string; + int seed, count, flags; +{ +#if defined (HANDLE_MULTIBYTE) + return _rl_find_next_mbchar_internal (string, seed, count, flags); +#else + return (seed + count); +#endif +} + +/* Find previous character started byte point of the specified seed. + Returned point will be point <= seed. If flags is MB_FIND_NONZERO, + we look for non-zero-width multibyte characters. */ +#undef _rl_find_prev_mbchar +int +_rl_find_prev_mbchar (string, seed, flags) + char *string; + int seed, flags; +{ +#if defined (HANDLE_MULTIBYTE) + return _rl_find_prev_mbchar_internal (string, seed, flags); +#else + return ((seed == 0) ? seed : seed - 1); +#endif +} diff --git a/readline/misc.c b/readline/misc.c new file mode 100644 index 0000000..f3775d3 --- /dev/null +++ b/readline/misc.c @@ -0,0 +1,496 @@ +/* misc.c -- miscellaneous bindable readline functions. */ + +/* Copyright (C) 1987-2002 Free Software Foundation, Inc. + + This file is part of the GNU Readline Library, a library for + reading lines of text with interactive input and history editing. + + The GNU Readline Library is free software; you can redistribute it + and/or modify it under the terms of the GNU General Public License + as published by the Free Software Foundation; either version 2, or + (at your option) any later version. + + The GNU Readline Library is distributed in the hope that it will be + useful, but WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + The GNU General Public License is often shipped with GNU software, and + is generally kept in a file called COPYING or LICENSE. If you do not + have a copy of the license, write to the Free Software Foundation, + 59 Temple Place, Suite 330, Boston, MA 02111 USA. */ +#define READLINE_LIBRARY + +#if defined (HAVE_CONFIG_H) +# include +#endif + +#if defined (HAVE_UNISTD_H) +# include +#endif /* HAVE_UNISTD_H */ + +#if defined (HAVE_STDLIB_H) +# include +#else +# include "ansi_stdlib.h" +#endif /* HAVE_STDLIB_H */ + +#if defined (HAVE_LOCALE_H) +# include +#endif + +#include + +/* System-specific feature definitions and include files. */ +#include "rldefs.h" +#include "rlmbutil.h" + +/* Some standard library routines. */ +#include "readline.h" +#include "history.h" + +#include "rlprivate.h" +#include "rlshell.h" +#include "xmalloc.h" + +static int rl_digit_loop PARAMS((void)); +static void _rl_history_set_point PARAMS((void)); + +/* Forward declarations used in this file */ +void _rl_free_history_entry PARAMS((HIST_ENTRY *)); + +/* If non-zero, rl_get_previous_history and rl_get_next_history attempt + to preserve the value of rl_point from line to line. */ +int _rl_history_preserve_point = 0; + +/* Saved target point for when _rl_history_preserve_point is set. Special + value of -1 means that point is at the end of the line. */ +int _rl_history_saved_point = -1; + +/* **************************************************************** */ +/* */ +/* Numeric Arguments */ +/* */ +/* **************************************************************** */ + +/* Handle C-u style numeric args, as well as M--, and M-digits. */ +static int +rl_digit_loop () +{ + int key, c, sawminus, sawdigits; + + rl_save_prompt (); + + RL_SETSTATE(RL_STATE_NUMERICARG); + sawminus = sawdigits = 0; + while (1) + { + if (rl_numeric_arg > 1000000) + { + sawdigits = rl_explicit_arg = rl_numeric_arg = 0; + rl_ding (); + rl_restore_prompt (); + rl_clear_message (); + RL_UNSETSTATE(RL_STATE_NUMERICARG); + return 1; + } + rl_message ("(arg: %d) ", rl_arg_sign * rl_numeric_arg); + RL_SETSTATE(RL_STATE_MOREINPUT); + key = c = rl_read_key (); + RL_UNSETSTATE(RL_STATE_MOREINPUT); + + if (c < 0) + { + _rl_abort_internal (); + return -1; + } + + /* If we see a key bound to `universal-argument' after seeing digits, + it ends the argument but is otherwise ignored. */ + if (_rl_keymap[c].type == ISFUNC && + _rl_keymap[c].function == rl_universal_argument) + { + if (sawdigits == 0) + { + rl_numeric_arg *= 4; + continue; + } + else + { + RL_SETSTATE(RL_STATE_MOREINPUT); + key = rl_read_key (); + RL_UNSETSTATE(RL_STATE_MOREINPUT); + rl_restore_prompt (); + rl_clear_message (); + RL_UNSETSTATE(RL_STATE_NUMERICARG); + return (_rl_dispatch (key, _rl_keymap)); + } + } + + c = UNMETA (c); + + if (_rl_digit_p (c)) + { + rl_numeric_arg = rl_explicit_arg ? (rl_numeric_arg * 10) + c - '0' : c - '0'; + sawdigits = rl_explicit_arg = 1; + } + else if (c == '-' && rl_explicit_arg == 0) + { + rl_numeric_arg = sawminus = 1; + rl_arg_sign = -1; + } + else + { + /* Make M-- command equivalent to M--1 command. */ + if (sawminus && rl_numeric_arg == 1 && rl_explicit_arg == 0) + rl_explicit_arg = 1; + rl_restore_prompt (); + rl_clear_message (); + RL_UNSETSTATE(RL_STATE_NUMERICARG); + return (_rl_dispatch (key, _rl_keymap)); + } + } + + /*NOTREACHED*/ +} + +/* Add the current digit to the argument in progress. */ +int +rl_digit_argument (ignore, key) + int ignore, key; +{ + rl_execute_next (key); + return (rl_digit_loop ()); +} + +/* What to do when you abort reading an argument. */ +int +rl_discard_argument () +{ + rl_ding (); + rl_clear_message (); + _rl_init_argument (); + return 0; +} + +/* Create a default argument. */ +int +_rl_init_argument () +{ + rl_numeric_arg = rl_arg_sign = 1; + rl_explicit_arg = 0; + return 0; +} + +/* C-u, universal argument. Multiply the current argument by 4. + Read a key. If the key has nothing to do with arguments, then + dispatch on it. If the key is the abort character then abort. */ +int +rl_universal_argument (count, key) + int count, key; +{ + rl_numeric_arg *= 4; + return (rl_digit_loop ()); +} + +/* **************************************************************** */ +/* */ +/* History Utilities */ +/* */ +/* **************************************************************** */ + +/* We already have a history library, and that is what we use to control + the history features of readline. This is our local interface to + the history mechanism. */ + +/* While we are editing the history, this is the saved + version of the original line. */ +HIST_ENTRY *_rl_saved_line_for_history = (HIST_ENTRY *)NULL; + +/* Set the history pointer back to the last entry in the history. */ +void +_rl_start_using_history () +{ + using_history (); + if (_rl_saved_line_for_history) + _rl_free_history_entry (_rl_saved_line_for_history); + + _rl_saved_line_for_history = (HIST_ENTRY *)NULL; +} + +/* Free the contents (and containing structure) of a HIST_ENTRY. */ +void +_rl_free_history_entry (entry) + HIST_ENTRY *entry; +{ + if (entry == 0) + return; + if (entry->line) + free (entry->line); + free (entry); +} + +/* Perhaps put back the current line if it has changed. */ +int +rl_maybe_replace_line () +{ + HIST_ENTRY *temp; + + temp = current_history (); + /* If the current line has changed, save the changes. */ + if (temp && ((UNDO_LIST *)(temp->data) != rl_undo_list)) + { + temp = replace_history_entry (where_history (), rl_line_buffer, (histdata_t)rl_undo_list); + free (temp->line); + free (temp); + } + return 0; +} + +/* Restore the _rl_saved_line_for_history if there is one. */ +int +rl_maybe_unsave_line () +{ + if (_rl_saved_line_for_history) + { + rl_replace_line (_rl_saved_line_for_history->line, 0); + rl_undo_list = (UNDO_LIST *)_rl_saved_line_for_history->data; + _rl_free_history_entry (_rl_saved_line_for_history); + _rl_saved_line_for_history = (HIST_ENTRY *)NULL; + rl_point = rl_end; /* rl_replace_line sets rl_end */ + } + else + rl_ding (); + return 0; +} + +/* Save the current line in _rl_saved_line_for_history. */ +int +rl_maybe_save_line () +{ + if (_rl_saved_line_for_history == 0) + { + _rl_saved_line_for_history = (HIST_ENTRY *)xmalloc (sizeof (HIST_ENTRY)); + _rl_saved_line_for_history->line = savestring (rl_line_buffer); + _rl_saved_line_for_history->data = (char *)rl_undo_list; + } + return 0; +} + +int +_rl_free_saved_history_line () +{ + if (_rl_saved_line_for_history) + { + _rl_free_history_entry (_rl_saved_line_for_history); + _rl_saved_line_for_history = (HIST_ENTRY *)NULL; + } + return 0; +} + +static void +_rl_history_set_point () +{ + rl_point = (_rl_history_preserve_point && _rl_history_saved_point != -1) + ? _rl_history_saved_point + : rl_end; + if (rl_point > rl_end) + rl_point = rl_end; + +#if defined (VI_MODE) + if (rl_editing_mode == vi_mode) + rl_point = 0; +#endif /* VI_MODE */ + + if (rl_editing_mode == emacs_mode) + rl_mark = (rl_point == rl_end ? 0 : rl_end); +} + +void +rl_replace_from_history (entry, flags) + HIST_ENTRY *entry; + int flags; /* currently unused */ +{ + rl_replace_line (entry->line, 0); + rl_undo_list = (UNDO_LIST *)entry->data; + rl_point = rl_end; + rl_mark = 0; + +#if defined (VI_MODE) + if (rl_editing_mode == vi_mode) + { + rl_point = 0; + rl_mark = rl_end; + } +#endif +} + +/* **************************************************************** */ +/* */ +/* History Commands */ +/* */ +/* **************************************************************** */ + +/* Meta-< goes to the start of the history. */ +int +rl_beginning_of_history (count, key) + int count, key; +{ + return (rl_get_previous_history (1 + where_history (), key)); +} + +/* Meta-> goes to the end of the history. (The current line). */ +int +rl_end_of_history (count, key) + int count, key; +{ + rl_maybe_replace_line (); + using_history (); + rl_maybe_unsave_line (); + return 0; +} + +/* Move down to the next history line. */ +int +rl_get_next_history (count, key) + int count, key; +{ + HIST_ENTRY *temp; + + if (count < 0) + return (rl_get_previous_history (-count, key)); + + if (count == 0) + return 0; + + rl_maybe_replace_line (); + + /* either not saved by rl_newline or at end of line, so set appropriately. */ + if (_rl_history_saved_point == -1 && (rl_point || rl_end)) + _rl_history_saved_point = (rl_point == rl_end) ? -1 : rl_point; + + temp = (HIST_ENTRY *)NULL; + while (count) + { + temp = next_history (); + if (!temp) + break; + --count; + } + + if (temp == 0) + rl_maybe_unsave_line (); + else + { + rl_replace_from_history (temp, 0); + _rl_history_set_point (); + } + return 0; +} + +/* Get the previous item out of our interactive history, making it the current + line. If there is no previous history, just ding. */ +int +rl_get_previous_history (count, key) + int count, key; +{ + HIST_ENTRY *old_temp, *temp; + + if (count < 0) + return (rl_get_next_history (-count, key)); + + if (count == 0) + return 0; + + /* either not saved by rl_newline or at end of line, so set appropriately. */ + if (_rl_history_saved_point == -1 && (rl_point || rl_end)) + _rl_history_saved_point = (rl_point == rl_end) ? -1 : rl_point; + + /* If we don't have a line saved, then save this one. */ + rl_maybe_save_line (); + + /* If the current line has changed, save the changes. */ + rl_maybe_replace_line (); + + temp = old_temp = (HIST_ENTRY *)NULL; + while (count) + { + temp = previous_history (); + if (temp == 0) + break; + + old_temp = temp; + --count; + } + + /* If there was a large argument, and we moved back to the start of the + history, that is not an error. So use the last value found. */ + if (!temp && old_temp) + temp = old_temp; + + if (temp == 0) + rl_ding (); + else + { + rl_replace_from_history (temp, 0); + _rl_history_set_point (); + } + return 0; +} + +/* **************************************************************** */ +/* */ +/* Editing Modes */ +/* */ +/* **************************************************************** */ +/* How to toggle back and forth between editing modes. */ +int +rl_vi_editing_mode (count, key) + int count, key; +{ +#if defined (VI_MODE) + _rl_set_insert_mode (RL_IM_INSERT, 1); /* vi mode ignores insert mode */ + rl_editing_mode = vi_mode; + rl_vi_insertion_mode (1, key); +#endif /* VI_MODE */ + + return 0; +} + +int +rl_emacs_editing_mode (count, key) + int count, key; +{ + rl_editing_mode = emacs_mode; + _rl_set_insert_mode (RL_IM_INSERT, 1); /* emacs mode default is insert mode */ + _rl_keymap = emacs_standard_keymap; + return 0; +} + +/* Function for the rest of the library to use to set insert/overwrite mode. */ +void +_rl_set_insert_mode (im, force) + int im, force; +{ +#ifdef CURSOR_MODE + _rl_set_cursor (im, force); +#endif + + rl_insert_mode = im; +} + +/* Toggle overwrite mode. A positive explicit argument selects overwrite + mode. A negative or zero explicit argument selects insert mode. */ +int +rl_overwrite_mode (count, key) + int count, key; +{ + if (rl_explicit_arg == 0) + _rl_set_insert_mode (rl_insert_mode ^ 1, 0); + else if (count > 0) + _rl_set_insert_mode (RL_IM_OVERWRITE, 0); + else + _rl_set_insert_mode (RL_IM_INSERT, 0); + + return 0; +} diff --git a/readline/rlmbutil.h b/readline/rlmbutil.h new file mode 100644 index 0000000..9b8464a --- /dev/null +++ b/readline/rlmbutil.h @@ -0,0 +1,109 @@ +/* rlmbutil.h -- utility functions for multibyte characters. */ + +/* Copyright (C) 2001 Free Software Foundation, Inc. + + This file is part of the GNU Readline Library, a library for + reading lines of text with interactive input and history editing. + + The GNU Readline Library is free software; you can redistribute it + and/or modify it under the terms of the GNU General Public License + as published by the Free Software Foundation; either version 2, or + (at your option) any later version. + + The GNU Readline Library is distributed in the hope that it will be + useful, but WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + The GNU General Public License is often shipped with GNU software, and + is generally kept in a file called COPYING or LICENSE. If you do not + have a copy of the license, write to the Free Software Foundation, + 59 Temple Place, Suite 330, Boston, MA 02111 USA. */ + +#if !defined (_RL_MBUTIL_H_) +#define _RL_MBUTIL_H_ + +#include "rlstdc.h" + +/************************************************/ +/* check multibyte capability for I18N code */ +/************************************************/ + +/* For platforms which support the ISO C amendement 1 functionality we + support user defined character classes. */ + /* Solaris 2.5 has a bug: must be included before . */ +#if defined (HAVE_WCTYPE_H) && defined (HAVE_WCHAR_H) +# include +# include +# if defined (HAVE_MBRTOWC) && defined (HAVE_MBSRTOWCS) + /* system is supposed to support XPG5 */ +# define HANDLE_MULTIBYTE 1 +# endif +#endif + +/* Some systems, like BeOS, have multibyte encodings but lack mbstate_t. */ +#if HANDLE_MULTIBYTE && !defined (HAVE_MBSTATE_T) +# define wcsrtombs(dest, src, len, ps) (wcsrtombs) (dest, src, len, 0) +# define mbsrtowcs(dest, src, len, ps) (mbsrtowcs) (dest, src, len, 0) +# define wcrtomb(s, wc, ps) (wcrtomb) (s, wc, 0) +# define mbrtowc(pwc, s, n, ps) (mbrtowc) (pwc, s, n, 0) +# define mbrlen(s, n, ps) (mbrlen) (s, n, 0) +# define mbstate_t int +#endif + +/* Make sure MB_LEN_MAX is at least 16 on systems that claim to be able to + handle multibyte chars (some systems define MB_LEN_MAX as 1) */ +#ifdef HANDLE_MULTIBYTE +# include +# if defined(MB_LEN_MAX) && (MB_LEN_MAX < 16) +# undef MB_LEN_MAX +# endif +# if !defined (MB_LEN_MAX) +# define MB_LEN_MAX 16 +# endif +#endif + +/************************************************/ +/* end of multibyte capability checks for I18N */ +/************************************************/ + +/* + * Flags for _rl_find_prev_mbchar and _rl_find_next_mbchar: + * + * MB_FIND_ANY find any multibyte character + * MB_FIND_NONZERO find a non-zero-width multibyte character + */ + +#define MB_FIND_ANY 0x00 +#define MB_FIND_NONZERO 0x01 + +extern int _rl_find_prev_mbchar PARAMS((char *, int, int)); +extern int _rl_find_next_mbchar PARAMS((char *, int, int, int)); + +#ifdef HANDLE_MULTIBYTE + +extern int _rl_compare_chars PARAMS((char *, int, mbstate_t *, char *, int, mbstate_t *)); +extern int _rl_get_char_len PARAMS((char *, mbstate_t *)); +extern int _rl_adjust_point PARAMS((char *, int, mbstate_t *)); + +extern int _rl_read_mbchar PARAMS((char *, int)); +extern int _rl_read_mbstring PARAMS((int, char *, int)); + +extern int _rl_is_mbchar_matched PARAMS((char *, int, int, char *, int)); + +#else /* !HANDLE_MULTIBYTE */ + +#undef MB_LEN_MAX +#undef MB_CUR_MAX + +#define MB_LEN_MAX 1 +#define MB_CUR_MAX 1 + +#define _rl_find_prev_mbchar(b, i, f) (((i) == 0) ? (i) : ((i) - 1)) +#define _rl_find_next_mbchar(b, i1, i2, f) ((i1) + (i2)) + +#endif /* !HANDLE_MULTIBYTE */ + +extern int rl_byte_oriented; + +#endif /* _RL_MBUTIL_H_ */ diff --git a/readline/rltypedefs.h b/readline/rltypedefs.h new file mode 100644 index 0000000..f3280e9 --- /dev/null +++ b/readline/rltypedefs.h @@ -0,0 +1,88 @@ +/* rltypedefs.h -- Type declarations for readline functions. */ + +/* Copyright (C) 2000 Free Software Foundation, Inc. + + This file is part of the GNU Readline Library, a library for + reading lines of text with interactive input and history editing. + + The GNU Readline Library is free software; you can redistribute it + and/or modify it under the terms of the GNU General Public License + as published by the Free Software Foundation; either version 2, or + (at your option) any later version. + + The GNU Readline Library is distributed in the hope that it will be + useful, but WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + The GNU General Public License is often shipped with GNU software, and + is generally kept in a file called COPYING or LICENSE. If you do not + have a copy of the license, write to the Free Software Foundation, + 59 Temple Place, Suite 330, Boston, MA 02111 USA. */ + +#ifndef _RL_TYPEDEFS_H_ +#define _RL_TYPEDEFS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Old-style */ + +#if !defined (_FUNCTION_DEF) +# define _FUNCTION_DEF + +typedef int Function (); +typedef void VFunction (); +typedef char *CPFunction (); +typedef char **CPPFunction (); + +#endif /* _FUNCTION_DEF */ + +/* New style. */ + +#if !defined (_RL_FUNCTION_TYPEDEF) +# define _RL_FUNCTION_TYPEDEF + +/* Bindable functions */ +typedef int rl_command_func_t PARAMS((int, int)); + +/* Typedefs for the completion system */ +typedef char *rl_compentry_func_t PARAMS((const char *, int)); +typedef char **rl_completion_func_t PARAMS((const char *, int, int)); + +typedef char *rl_quote_func_t PARAMS((char *, int, char *)); +typedef char *rl_dequote_func_t PARAMS((char *, int)); + +typedef int rl_compignore_func_t PARAMS((char **)); + +typedef void rl_compdisp_func_t PARAMS((char **, int, int)); + +/* Type for input and pre-read hook functions like rl_event_hook */ +typedef int rl_hook_func_t PARAMS((void)); + +/* Input function type */ +typedef int rl_getc_func_t PARAMS((FILE *)); + +/* Generic function that takes a character buffer (which could be the readline + line buffer) and an index into it (which could be rl_point) and returns + an int. */ +typedef int rl_linebuf_func_t PARAMS((char *, int)); + +/* `Generic' function pointer typedefs */ +typedef int rl_intfunc_t PARAMS((int)); +#define rl_ivoidfunc_t rl_hook_func_t +typedef int rl_icpfunc_t PARAMS((char *)); +typedef int rl_icppfunc_t PARAMS((char **)); + +typedef void rl_voidfunc_t PARAMS((void)); +typedef void rl_vintfunc_t PARAMS((int)); +typedef void rl_vcpfunc_t PARAMS((char *)); +typedef void rl_vcppfunc_t PARAMS((char **)); +#endif /* _RL_FUNCTION_TYPEDEF */ + +#ifdef __cplusplus +} +#endif + +#endif /* _RL_TYPEDEFS_H_ */ diff --git a/readline/support/wcwidth.c b/readline/support/wcwidth.c new file mode 100644 index 0000000..ace9a3a --- /dev/null +++ b/readline/support/wcwidth.c @@ -0,0 +1,236 @@ +/* + * This is an implementation of wcwidth() and wcswidth() as defined in + * "The Single UNIX Specification, Version 2, The Open Group, 1997" + * + * + * Markus Kuhn -- 2001-09-08 -- public domain + */ + +#include + +struct interval { + unsigned short first; + unsigned short last; +}; + +/* auxiliary function for binary search in interval table */ +static int bisearch(wchar_t ucs, const struct interval *table, int max) { + int min = 0; + int mid; + + if (ucs < table[0].first || ucs > table[max].last) + return 0; + while (max >= min) { + mid = (min + max) / 2; + if (ucs > table[mid].last) + min = mid + 1; + else if (ucs < table[mid].first) + max = mid - 1; + else + return 1; + } + + return 0; +} + + +/* The following functions define the column width of an ISO 10646 + * character as follows: + * + * - The null character (U+0000) has a column width of 0. + * + * - Other C0/C1 control characters and DEL will lead to a return + * value of -1. + * + * - Non-spacing and enclosing combining characters (general + * category code Mn or Me in the Unicode database) have a + * column width of 0. + * + * - Other format characters (general category code Cf in the Unicode + * database) and ZERO WIDTH SPACE (U+200B) have a column width of 0. + * + * - Hangul Jamo medial vowels and final consonants (U+1160-U+11FF) + * have a column width of 0. + * + * - Spacing characters in the East Asian Wide (W) or East Asian + * FullWidth (F) category as defined in Unicode Technical + * Report #11 have a column width of 2. + * + * - All remaining characters (including all printable + * ISO 8859-1 and WGL4 characters, Unicode control characters, + * etc.) have a column width of 1. + * + * This implementation assumes that wchar_t characters are encoded + * in ISO 10646. + */ + +int wcwidth(wchar_t ucs) +{ + /* sorted list of non-overlapping intervals of non-spacing characters */ + static const struct interval combining[] = { + { 0x0300, 0x034E }, { 0x0360, 0x0362 }, { 0x0483, 0x0486 }, + { 0x0488, 0x0489 }, { 0x0591, 0x05A1 }, { 0x05A3, 0x05B9 }, + { 0x05BB, 0x05BD }, { 0x05BF, 0x05BF }, { 0x05C1, 0x05C2 }, + { 0x05C4, 0x05C4 }, { 0x064B, 0x0655 }, { 0x0670, 0x0670 }, + { 0x06D6, 0x06E4 }, { 0x06E7, 0x06E8 }, { 0x06EA, 0x06ED }, + { 0x070F, 0x070F }, { 0x0711, 0x0711 }, { 0x0730, 0x074A }, + { 0x07A6, 0x07B0 }, { 0x0901, 0x0902 }, { 0x093C, 0x093C }, + { 0x0941, 0x0948 }, { 0x094D, 0x094D }, { 0x0951, 0x0954 }, + { 0x0962, 0x0963 }, { 0x0981, 0x0981 }, { 0x09BC, 0x09BC }, + { 0x09C1, 0x09C4 }, { 0x09CD, 0x09CD }, { 0x09E2, 0x09E3 }, + { 0x0A02, 0x0A02 }, { 0x0A3C, 0x0A3C }, { 0x0A41, 0x0A42 }, + { 0x0A47, 0x0A48 }, { 0x0A4B, 0x0A4D }, { 0x0A70, 0x0A71 }, + { 0x0A81, 0x0A82 }, { 0x0ABC, 0x0ABC }, { 0x0AC1, 0x0AC5 }, + { 0x0AC7, 0x0AC8 }, { 0x0ACD, 0x0ACD }, { 0x0B01, 0x0B01 }, + { 0x0B3C, 0x0B3C }, { 0x0B3F, 0x0B3F }, { 0x0B41, 0x0B43 }, + { 0x0B4D, 0x0B4D }, { 0x0B56, 0x0B56 }, { 0x0B82, 0x0B82 }, + { 0x0BC0, 0x0BC0 }, { 0x0BCD, 0x0BCD }, { 0x0C3E, 0x0C40 }, + { 0x0C46, 0x0C48 }, { 0x0C4A, 0x0C4D }, { 0x0C55, 0x0C56 }, + { 0x0CBF, 0x0CBF }, { 0x0CC6, 0x0CC6 }, { 0x0CCC, 0x0CCD }, + { 0x0D41, 0x0D43 }, { 0x0D4D, 0x0D4D }, { 0x0DCA, 0x0DCA }, + { 0x0DD2, 0x0DD4 }, { 0x0DD6, 0x0DD6 }, { 0x0E31, 0x0E31 }, + { 0x0E34, 0x0E3A }, { 0x0E47, 0x0E4E }, { 0x0EB1, 0x0EB1 }, + { 0x0EB4, 0x0EB9 }, { 0x0EBB, 0x0EBC }, { 0x0EC8, 0x0ECD }, + { 0x0F18, 0x0F19 }, { 0x0F35, 0x0F35 }, { 0x0F37, 0x0F37 }, + { 0x0F39, 0x0F39 }, { 0x0F71, 0x0F7E }, { 0x0F80, 0x0F84 }, + { 0x0F86, 0x0F87 }, { 0x0F90, 0x0F97 }, { 0x0F99, 0x0FBC }, + { 0x0FC6, 0x0FC6 }, { 0x102D, 0x1030 }, { 0x1032, 0x1032 }, + { 0x1036, 0x1037 }, { 0x1039, 0x1039 }, { 0x1058, 0x1059 }, + { 0x1160, 0x11FF }, { 0x17B7, 0x17BD }, { 0x17C6, 0x17C6 }, + { 0x17C9, 0x17D3 }, { 0x180B, 0x180E }, { 0x18A9, 0x18A9 }, + { 0x200B, 0x200F }, { 0x202A, 0x202E }, { 0x206A, 0x206F }, + { 0x20D0, 0x20E3 }, { 0x302A, 0x302F }, { 0x3099, 0x309A }, + { 0xFB1E, 0xFB1E }, { 0xFE20, 0xFE23 }, { 0xFEFF, 0xFEFF }, + { 0xFFF9, 0xFFFB } + }; + + /* test for 8-bit control characters */ + if (ucs == 0) + return 0; + if (ucs < 32 || (ucs >= 0x7f && ucs < 0xa0)) + return -1; + + /* binary search in table of non-spacing characters */ + if (bisearch(ucs, combining, + sizeof(combining) / sizeof(struct interval) - 1)) + return 0; + + /* if we arrive here, ucs is not a combining or C0/C1 control character */ + + return 1 + + (ucs >= 0x1100 && + (ucs <= 0x115f || /* Hangul Jamo init. consonants */ + (ucs >= 0x2e80 && ucs <= 0xa4cf && (ucs & ~0x0011) != 0x300a && + ucs != 0x303f) || /* CJK ... Yi */ + (ucs >= 0xac00 && ucs <= 0xd7a3) || /* Hangul Syllables */ + (ucs >= 0xf900 && ucs <= 0xfaff) || /* CJK Compatibility Ideographs */ + (ucs >= 0xfe30 && ucs <= 0xfe6f) || /* CJK Compatibility Forms */ + (ucs >= 0xff00 && ucs <= 0xff5f) || /* Fullwidth Forms */ + (ucs >= 0xffe0 && ucs <= 0xffe6) || + (ucs >= 0x20000 && ucs <= 0x2ffff))); +} + + +int wcswidth(const wchar_t *pwcs, size_t n) +{ + int w, width = 0; + + for (;*pwcs && n-- > 0; pwcs++) + if ((w = wcwidth(*pwcs)) < 0) + return -1; + else + width += w; + + return width; +} + + +/* + * The following function is the same as wcwidth(), except that + * spacing characters in the East Asian Ambiguous (A) category as + * defined in Unicode Technical Report #11 have a column width of 2. + * This experimental variant might be useful for users of CJK legacy + * encodings who want to migrate to UCS. It is not otherwise + * recommended for general use. + */ +static int wcwidth_cjk(wchar_t ucs) +{ + /* sorted list of non-overlapping intervals of East Asian Ambiguous + * characters */ + static const struct interval ambiguous[] = { + { 0x00A1, 0x00A1 }, { 0x00A4, 0x00A4 }, { 0x00A7, 0x00A8 }, + { 0x00AA, 0x00AA }, { 0x00AD, 0x00AE }, { 0x00B0, 0x00B4 }, + { 0x00B6, 0x00BA }, { 0x00BC, 0x00BF }, { 0x00C6, 0x00C6 }, + { 0x00D0, 0x00D0 }, { 0x00D7, 0x00D8 }, { 0x00DE, 0x00E1 }, + { 0x00E6, 0x00E6 }, { 0x00E8, 0x00EA }, { 0x00EC, 0x00ED }, + { 0x00F0, 0x00F0 }, { 0x00F2, 0x00F3 }, { 0x00F7, 0x00FA }, + { 0x00FC, 0x00FC }, { 0x00FE, 0x00FE }, { 0x0101, 0x0101 }, + { 0x0111, 0x0111 }, { 0x0113, 0x0113 }, { 0x011B, 0x011B }, + { 0x0126, 0x0127 }, { 0x012B, 0x012B }, { 0x0131, 0x0133 }, + { 0x0138, 0x0138 }, { 0x013F, 0x0142 }, { 0x0144, 0x0144 }, + { 0x0148, 0x014B }, { 0x014D, 0x014D }, { 0x0152, 0x0153 }, + { 0x0166, 0x0167 }, { 0x016B, 0x016B }, { 0x01CE, 0x01CE }, + { 0x01D0, 0x01D0 }, { 0x01D2, 0x01D2 }, { 0x01D4, 0x01D4 }, + { 0x01D6, 0x01D6 }, { 0x01D8, 0x01D8 }, { 0x01DA, 0x01DA }, + { 0x01DC, 0x01DC }, { 0x0251, 0x0251 }, { 0x0261, 0x0261 }, + { 0x02C4, 0x02C4 }, { 0x02C7, 0x02C7 }, { 0x02C9, 0x02CB }, + { 0x02CD, 0x02CD }, { 0x02D0, 0x02D0 }, { 0x02D8, 0x02DB }, + { 0x02DD, 0x02DD }, { 0x02DF, 0x02DF }, { 0x0300, 0x034E }, + { 0x0360, 0x0362 }, { 0x0391, 0x03A1 }, { 0x03A3, 0x03A9 }, + { 0x03B1, 0x03C1 }, { 0x03C3, 0x03C9 }, { 0x0401, 0x0401 }, + { 0x0410, 0x044F }, { 0x0451, 0x0451 }, { 0x2010, 0x2010 }, + { 0x2013, 0x2016 }, { 0x2018, 0x2019 }, { 0x201C, 0x201D }, + { 0x2020, 0x2022 }, { 0x2024, 0x2027 }, { 0x2030, 0x2030 }, + { 0x2032, 0x2033 }, { 0x2035, 0x2035 }, { 0x203B, 0x203B }, + { 0x203E, 0x203E }, { 0x2074, 0x2074 }, { 0x207F, 0x207F }, + { 0x2081, 0x2084 }, { 0x20AC, 0x20AC }, { 0x2103, 0x2103 }, + { 0x2105, 0x2105 }, { 0x2109, 0x2109 }, { 0x2113, 0x2113 }, + { 0x2116, 0x2116 }, { 0x2121, 0x2122 }, { 0x2126, 0x2126 }, + { 0x212B, 0x212B }, { 0x2153, 0x2155 }, { 0x215B, 0x215E }, + { 0x2160, 0x216B }, { 0x2170, 0x2179 }, { 0x2190, 0x2199 }, + { 0x21B8, 0x21B9 }, { 0x21D2, 0x21D2 }, { 0x21D4, 0x21D4 }, + { 0x21E7, 0x21E7 }, { 0x2200, 0x2200 }, { 0x2202, 0x2203 }, + { 0x2207, 0x2208 }, { 0x220B, 0x220B }, { 0x220F, 0x220F }, + { 0x2211, 0x2211 }, { 0x2215, 0x2215 }, { 0x221A, 0x221A }, + { 0x221D, 0x2220 }, { 0x2223, 0x2223 }, { 0x2225, 0x2225 }, + { 0x2227, 0x222C }, { 0x222E, 0x222E }, { 0x2234, 0x2237 }, + { 0x223C, 0x223D }, { 0x2248, 0x2248 }, { 0x224C, 0x224C }, + { 0x2252, 0x2252 }, { 0x2260, 0x2261 }, { 0x2264, 0x2267 }, + { 0x226A, 0x226B }, { 0x226E, 0x226F }, { 0x2282, 0x2283 }, + { 0x2286, 0x2287 }, { 0x2295, 0x2295 }, { 0x2299, 0x2299 }, + { 0x22A5, 0x22A5 }, { 0x22BF, 0x22BF }, { 0x2312, 0x2312 }, + { 0x2329, 0x232A }, { 0x2460, 0x24BF }, { 0x24D0, 0x24E9 }, + { 0x2500, 0x254B }, { 0x2550, 0x2574 }, { 0x2580, 0x258F }, + { 0x2592, 0x2595 }, { 0x25A0, 0x25A1 }, { 0x25A3, 0x25A9 }, + { 0x25B2, 0x25B3 }, { 0x25B6, 0x25B7 }, { 0x25BC, 0x25BD }, + { 0x25C0, 0x25C1 }, { 0x25C6, 0x25C8 }, { 0x25CB, 0x25CB }, + { 0x25CE, 0x25D1 }, { 0x25E2, 0x25E5 }, { 0x25EF, 0x25EF }, + { 0x2605, 0x2606 }, { 0x2609, 0x2609 }, { 0x260E, 0x260F }, + { 0x261C, 0x261C }, { 0x261E, 0x261E }, { 0x2640, 0x2640 }, + { 0x2642, 0x2642 }, { 0x2660, 0x2661 }, { 0x2663, 0x2665 }, + { 0x2667, 0x266A }, { 0x266C, 0x266D }, { 0x266F, 0x266F }, + { 0x273D, 0x273D }, { 0x3008, 0x300B }, { 0x3014, 0x3015 }, + { 0x3018, 0x301B }, { 0xFFFD, 0xFFFD } + }; + + /* binary search in table of non-spacing characters */ + if (bisearch(ucs, ambiguous, + sizeof(ambiguous) / sizeof(struct interval) - 1)) + return 2; + + return wcwidth(ucs); +} + + +int wcswidth_cjk(const wchar_t *pwcs, size_t n) +{ + int w, width = 0; + + for (;*pwcs && n-- > 0; pwcs++) + if ((w = wcwidth_cjk(*pwcs)) < 0) + return -1; + else + width += w; + + return width; +} diff --git a/readline/text.c b/readline/text.c new file mode 100644 index 0000000..2a7b724 --- /dev/null +++ b/readline/text.c @@ -0,0 +1,1540 @@ +/* text.c -- text handling commands for readline. */ + +/* Copyright (C) 1987-2002 Free Software Foundation, Inc. + + This file is part of the GNU Readline Library, a library for + reading lines of text with interactive input and history editing. + + The GNU Readline Library is free software; you can redistribute it + and/or modify it under the terms of the GNU General Public License + as published by the Free Software Foundation; either version 2, or + (at your option) any later version. + + The GNU Readline Library is distributed in the hope that it will be + useful, but WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + The GNU General Public License is often shipped with GNU software, and + is generally kept in a file called COPYING or LICENSE. If you do not + have a copy of the license, write to the Free Software Foundation, + 59 Temple Place, Suite 330, Boston, MA 02111 USA. */ +#define READLINE_LIBRARY + +#if defined (HAVE_CONFIG_H) +# include +#endif + +#if defined (HAVE_UNISTD_H) +# include +#endif /* HAVE_UNISTD_H */ + +#if defined (HAVE_STDLIB_H) +# include +#else +# include "ansi_stdlib.h" +#endif /* HAVE_STDLIB_H */ + +#if defined (HAVE_LOCALE_H) +# include +#endif + +#include + +/* System-specific feature definitions and include files. */ +#include "rldefs.h" +#include "rlmbutil.h" + +#if defined (__EMX__) +# define INCL_DOSPROCESS +# include +#endif /* __EMX__ */ + +/* Some standard library routines. */ +#include "readline.h" +#include "history.h" + +#include "rlprivate.h" +#include "rlshell.h" +#include "xmalloc.h" + +/* Forward declarations. */ +static int rl_change_case PARAMS((int, int)); +static int _rl_char_search PARAMS((int, int, int)); + +/* **************************************************************** */ +/* */ +/* Insert and Delete */ +/* */ +/* **************************************************************** */ + +/* Insert a string of text into the line at point. This is the only + way that you should do insertion. _rl_insert_char () calls this + function. Returns the number of characters inserted. */ +int +rl_insert_text (string) + const char *string; +{ + register int i, l; + + l = (string && *string) ? strlen (string) : 0; + if (l == 0) + return 0; + + if (rl_end + l >= rl_line_buffer_len) + rl_extend_line_buffer (rl_end + l); + + for (i = rl_end; i >= rl_point; i--) + rl_line_buffer[i + l] = rl_line_buffer[i]; + strncpy (rl_line_buffer + rl_point, string, l); + + /* Remember how to undo this if we aren't undoing something. */ + if (_rl_doing_an_undo == 0) + { + /* If possible and desirable, concatenate the undos. */ + if ((l == 1) && + rl_undo_list && + (rl_undo_list->what == UNDO_INSERT) && + (rl_undo_list->end == rl_point) && + (rl_undo_list->end - rl_undo_list->start < 20)) + rl_undo_list->end++; + else + rl_add_undo (UNDO_INSERT, rl_point, rl_point + l, (char *)NULL); + } + rl_point += l; + rl_end += l; + rl_line_buffer[rl_end] = '\0'; + return l; +} + +/* Delete the string between FROM and TO. FROM is inclusive, TO is not. + Returns the number of characters deleted. */ +int +rl_delete_text (from, to) + int from, to; +{ + register char *text; + register int diff, i; + + /* Fix it if the caller is confused. */ + if (from > to) + SWAP (from, to); + + /* fix boundaries */ + if (to > rl_end) + { + to = rl_end; + if (from > to) + from = to; + } + if (from < 0) + from = 0; + + text = rl_copy_text (from, to); + + /* Some versions of strncpy() can't handle overlapping arguments. */ + diff = to - from; + for (i = from; i < rl_end - diff; i++) + rl_line_buffer[i] = rl_line_buffer[i + diff]; + + /* Remember how to undo this delete. */ + if (_rl_doing_an_undo == 0) + rl_add_undo (UNDO_DELETE, from, to, text); + else + free (text); + + rl_end -= diff; + rl_line_buffer[rl_end] = '\0'; + return (diff); +} + +/* Fix up point so that it is within the line boundaries after killing + text. If FIX_MARK_TOO is non-zero, the mark is forced within line + boundaries also. */ + +#define _RL_FIX_POINT(x) \ + do { \ + if (x > rl_end) \ + x = rl_end; \ + else if (x < 0) \ + x = 0; \ + } while (0) + +void +_rl_fix_point (fix_mark_too) + int fix_mark_too; +{ + _RL_FIX_POINT (rl_point); + if (fix_mark_too) + _RL_FIX_POINT (rl_mark); +} +#undef _RL_FIX_POINT + +int +_rl_replace_text (text, start, end) + const char *text; + int start, end; +{ + int n; + + rl_begin_undo_group (); + rl_delete_text (start, end + 1); + rl_point = start; + n = rl_insert_text (text); + rl_end_undo_group (); + + return n; +} + +/* Replace the current line buffer contents with TEXT. If CLEAR_UNDO is + non-zero, we free the current undo list. */ +void +rl_replace_line (text, clear_undo) + const char *text; + int clear_undo; +{ + int len; + + len = strlen (text); + if (len >= rl_line_buffer_len) + rl_extend_line_buffer (len); + strcpy (rl_line_buffer, text); + rl_end = len; + + if (clear_undo) + rl_free_undo_list (); + + _rl_fix_point (1); +} + +/* **************************************************************** */ +/* */ +/* Readline character functions */ +/* */ +/* **************************************************************** */ + +/* This is not a gap editor, just a stupid line input routine. No hair + is involved in writing any of the functions, and none should be. */ + +/* Note that: + + rl_end is the place in the string that we would place '\0'; + i.e., it is always safe to place '\0' there. + + rl_point is the place in the string where the cursor is. Sometimes + this is the same as rl_end. + + Any command that is called interactively receives two arguments. + The first is a count: the numeric arg pased to this command. + The second is the key which invoked this command. +*/ + +/* **************************************************************** */ +/* */ +/* Movement Commands */ +/* */ +/* **************************************************************** */ + +/* Note that if you `optimize' the display for these functions, you cannot + use said functions in other functions which do not do optimizing display. + I.e., you will have to update the data base for rl_redisplay, and you + might as well let rl_redisplay do that job. */ + +/* Move forward COUNT bytes. */ +int +rl_forward_byte (count, key) + int count, key; +{ + if (count < 0) + return (rl_backward_byte (-count, key)); + + if (count > 0) + { + int end = rl_point + count; +#if defined (VI_MODE) + int lend = rl_end > 0 ? rl_end - (rl_editing_mode == vi_mode) : rl_end; +#else + int lend = rl_end; +#endif + + if (end > lend) + { + rl_point = lend; + rl_ding (); + } + else + rl_point = end; + } + + if (rl_end < 0) + rl_end = 0; + + return 0; +} + +#if defined (HANDLE_MULTIBYTE) +/* Move forward COUNT characters. */ +int +rl_forward_char (count, key) + int count, key; +{ + int point; + + if (MB_CUR_MAX == 1 || rl_byte_oriented) + return (rl_forward_byte (count, key)); + + if (count < 0) + return (rl_backward_char (-count, key)); + + if (count > 0) + { + point = _rl_find_next_mbchar (rl_line_buffer, rl_point, count, MB_FIND_NONZERO); + +#if defined (VI_MODE) + if (rl_end <= point && rl_editing_mode == vi_mode) + point = _rl_find_prev_mbchar (rl_line_buffer, rl_end, MB_FIND_NONZERO); +#endif + + if (rl_point == point) + rl_ding (); + + rl_point = point; + + if (rl_end < 0) + rl_end = 0; + } + + return 0; +} +#else /* !HANDLE_MULTIBYTE */ +int +rl_forward_char (count, key) + int count, key; +{ + return (rl_forward_byte (count, key)); +} +#endif /* !HANDLE_MULTIBYTE */ + +/* Backwards compatibility. */ +int +rl_forward (count, key) + int count, key; +{ + return (rl_forward_char (count, key)); +} + +/* Move backward COUNT bytes. */ +int +rl_backward_byte (count, key) + int count, key; +{ + if (count < 0) + return (rl_forward_byte (-count, key)); + + if (count > 0) + { + if (rl_point < count) + { + rl_point = 0; + rl_ding (); + } + else + rl_point -= count; + } + + if (rl_point < 0) + rl_point = 0; + + return 0; +} + +#if defined (HANDLE_MULTIBYTE) +/* Move backward COUNT characters. */ +int +rl_backward_char (count, key) + int count, key; +{ + int point; + + if (MB_CUR_MAX == 1 || rl_byte_oriented) + return (rl_backward_byte (count, key)); + + if (count < 0) + return (rl_forward_char (-count, key)); + + if (count > 0) + { + point = rl_point; + + while (count > 0 && point > 0) + { + point = _rl_find_prev_mbchar (rl_line_buffer, point, MB_FIND_NONZERO); + count--; + } + if (count > 0) + { + rl_point = 0; + rl_ding (); + } + else + rl_point = point; + } + + return 0; +} +#else +int +rl_backward_char (count, key) + int count, key; +{ + return (rl_backward_byte (count, key)); +} +#endif + +/* Backwards compatibility. */ +int +rl_backward (count, key) + int count, key; +{ + return (rl_backward_char (count, key)); +} + +/* Move to the beginning of the line. */ +int +rl_beg_of_line (count, key) + int count, key; +{ + rl_point = 0; + return 0; +} + +/* Move to the end of the line. */ +int +rl_end_of_line (count, key) + int count, key; +{ + rl_point = rl_end; + return 0; +} + +/* XXX - these might need changes for multibyte characters */ +/* Move forward a word. We do what Emacs does. */ +int +rl_forward_word (count, key) + int count, key; +{ + int c; + + if (count < 0) + return (rl_backward_word (-count, key)); + + while (count) + { + if (rl_point == rl_end) + return 0; + + /* If we are not in a word, move forward until we are in one. + Then, move forward until we hit a non-alphabetic character. */ + c = rl_line_buffer[rl_point]; + if (rl_alphabetic (c) == 0) + { + while (++rl_point < rl_end) + { + c = rl_line_buffer[rl_point]; + if (rl_alphabetic (c)) + break; + } + } + + if (rl_point == rl_end) + return 0; + + while (++rl_point < rl_end) + { + c = rl_line_buffer[rl_point]; + if (rl_alphabetic (c) == 0) + break; + } + --count; + } + + return 0; +} + +/* Move backward a word. We do what Emacs does. */ +int +rl_backward_word (count, key) + int count, key; +{ + int c; + + if (count < 0) + return (rl_forward_word (-count, key)); + + while (count) + { + if (!rl_point) + return 0; + + /* Like rl_forward_word (), except that we look at the characters + just before point. */ + + c = rl_line_buffer[rl_point - 1]; + if (rl_alphabetic (c) == 0) + { + while (--rl_point) + { + c = rl_line_buffer[rl_point - 1]; + if (rl_alphabetic (c)) + break; + } + } + + while (rl_point) + { + c = rl_line_buffer[rl_point - 1]; + if (rl_alphabetic (c) == 0) + break; + else + --rl_point; + } + + --count; + } + + return 0; +} + +/* Clear the current line. Numeric argument to C-l does this. */ +int +rl_refresh_line (ignore1, ignore2) + int ignore1, ignore2; +{ + int curr_line; + + curr_line = _rl_current_display_line (); + + _rl_move_vert (curr_line); + _rl_move_cursor_relative (0, rl_line_buffer); /* XXX is this right */ + + _rl_clear_to_eol (0); /* arg of 0 means to not use spaces */ + + rl_forced_update_display (); + rl_display_fixed = 1; + + return 0; +} + +/* C-l typed to a line without quoting clears the screen, and then reprints + the prompt and the current input line. Given a numeric arg, redraw only + the current line. */ +int +rl_clear_screen (count, key) + int count, key; +{ + if (rl_explicit_arg) + { + rl_refresh_line (count, key); + return 0; + } + + _rl_clear_screen (); /* calls termcap function to clear screen */ + rl_forced_update_display (); + rl_display_fixed = 1; + + return 0; +} + +int +rl_arrow_keys (count, c) + int count, c; +{ + int ch; + + RL_SETSTATE(RL_STATE_MOREINPUT); + ch = rl_read_key (); + RL_UNSETSTATE(RL_STATE_MOREINPUT); + + switch (_rl_to_upper (ch)) + { + case 'A': + rl_get_previous_history (count, ch); + break; + + case 'B': + rl_get_next_history (count, ch); + break; + + case 'C': + if (MB_CUR_MAX > 1 && rl_byte_oriented == 0) + rl_forward_char (count, ch); + else + rl_forward_byte (count, ch); + break; + + case 'D': + if (MB_CUR_MAX > 1 && rl_byte_oriented == 0) + rl_backward_char (count, ch); + else + rl_backward_byte (count, ch); + break; + + default: + rl_ding (); + } + + return 0; +} + +/* **************************************************************** */ +/* */ +/* Text commands */ +/* */ +/* **************************************************************** */ + +#ifdef HANDLE_MULTIBYTE +static char pending_bytes[MB_LEN_MAX]; +static int pending_bytes_length = 0; +static mbstate_t ps = {0}; +#endif + +/* Insert the character C at the current location, moving point forward. + If C introduces a multibyte sequence, we read the whole sequence and + then insert the multibyte char into the line buffer. */ +int +_rl_insert_char (count, c) + int count, c; +{ + register int i; + char *string; +#ifdef HANDLE_MULTIBYTE + int string_size; + char incoming[MB_LEN_MAX + 1]; + int incoming_length = 0; + mbstate_t ps_back; + static int stored_count = 0; +#endif + + if (count <= 0) + return 0; + +#if defined (HANDLE_MULTIBYTE) + if (MB_CUR_MAX == 1 || rl_byte_oriented) + { + incoming[0] = c; + incoming[1] = '\0'; + incoming_length = 1; + } + else + { + wchar_t wc; + size_t ret; + + if (stored_count <= 0) + stored_count = count; + else + count = stored_count; + + ps_back = ps; + pending_bytes[pending_bytes_length++] = c; + ret = mbrtowc (&wc, pending_bytes, pending_bytes_length, &ps); + + if (ret == (size_t)-2) + { + /* Bytes too short to compose character, try to wait for next byte. + Restore the state of the byte sequence, because in this case the + effect of mbstate is undefined. */ + ps = ps_back; + return 1; + } + else if (ret == (size_t)-1) + { + /* Invalid byte sequence for the current locale. Treat first byte + as a single character. */ + incoming[0] = pending_bytes[0]; + incoming[1] = '\0'; + incoming_length = 1; + pending_bytes_length--; + memmove (pending_bytes, pending_bytes + 1, pending_bytes_length); + /* Clear the state of the byte sequence, because in this case the + effect of mbstate is undefined. */ + memset (&ps, 0, sizeof (mbstate_t)); + } + else if (ret == (size_t)0) + { + incoming[0] = '\0'; + incoming_length = 0; + pending_bytes_length--; + /* Clear the state of the byte sequence, because in this case the + effect of mbstate is undefined. */ + memset (&ps, 0, sizeof (mbstate_t)); + } + else + { + /* We successfully read a single multibyte character. */ + memcpy (incoming, pending_bytes, pending_bytes_length); + incoming[pending_bytes_length] = '\0'; + incoming_length = pending_bytes_length; + pending_bytes_length = 0; + } + } +#endif /* HANDLE_MULTIBYTE */ + + /* If we can optimize, then do it. But don't let people crash + readline because of extra large arguments. */ + if (count > 1 && count <= 1024) + { +#if defined (HANDLE_MULTIBYTE) + string_size = count * incoming_length; + string = (char *)xmalloc (1 + string_size); + + i = 0; + while (i < string_size) + { + strncpy (string + i, incoming, incoming_length); + i += incoming_length; + } + incoming_length = 0; + stored_count = 0; +#else /* !HANDLE_MULTIBYTE */ + string = (char *)xmalloc (1 + count); + + for (i = 0; i < count; i++) + string[i] = c; +#endif /* !HANDLE_MULTIBYTE */ + + string[i] = '\0'; + rl_insert_text (string); + free (string); + + return 0; + } + + if (count > 1024) + { + int decreaser; +#if defined (HANDLE_MULTIBYTE) + string_size = incoming_length * 1024; + string = (char *)xmalloc (1 + string_size); + + i = 0; + while (i < string_size) + { + strncpy (string + i, incoming, incoming_length); + i += incoming_length; + } + + while (count) + { + decreaser = (count > 1024) ? 1024 : count; + string[decreaser*incoming_length] = '\0'; + rl_insert_text (string); + count -= decreaser; + } + + free (string); + incoming_length = 0; + stored_count = 0; +#else /* !HANDLE_MULTIBYTE */ + char str[1024+1]; + + for (i = 0; i < 1024; i++) + str[i] = c; + + while (count) + { + decreaser = (count > 1024 ? 1024 : count); + str[decreaser] = '\0'; + rl_insert_text (str); + count -= decreaser; + } +#endif /* !HANDLE_MULTIBYTE */ + + return 0; + } + +#if defined (HANDLE_MULTIBYTE) + if (MB_CUR_MAX == 1 || rl_byte_oriented) + { +#endif + /* We are inserting a single character. + If there is pending input, then make a string of all of the + pending characters that are bound to rl_insert, and insert + them all. */ + if (_rl_any_typein ()) + _rl_insert_typein (c); + else + { + /* Inserting a single character. */ + char str[2]; + + str[1] = '\0'; + str[0] = c; + rl_insert_text (str); + } +#if defined (HANDLE_MULTIBYTE) + } + else + { + rl_insert_text (incoming); + stored_count = 0; + } +#endif + + return 0; +} + +/* Overwrite the character at point (or next COUNT characters) with C. + If C introduces a multibyte character sequence, read the entire sequence + before starting the overwrite loop. */ +int +_rl_overwrite_char (count, c) + int count, c; +{ + int i; +#if defined (HANDLE_MULTIBYTE) + char mbkey[MB_LEN_MAX]; + int k; + + /* Read an entire multibyte character sequence to insert COUNT times. */ + if (count > 0 && MB_CUR_MAX > 1 && rl_byte_oriented == 0) + k = _rl_read_mbstring (c, mbkey, MB_LEN_MAX); +#endif + + for (i = 0; i < count; i++) + { + rl_begin_undo_group (); + + if (rl_point < rl_end) + rl_delete (1, c); + +#if defined (HANDLE_MULTIBYTE) + if (MB_CUR_MAX > 1 && rl_byte_oriented == 0) + rl_insert_text (mbkey); + else +#endif + _rl_insert_char (1, c); + + rl_end_undo_group (); + } + + return 0; +} + +int +rl_insert (count, c) + int count, c; +{ + return (rl_insert_mode == RL_IM_INSERT ? _rl_insert_char (count, c) + : _rl_overwrite_char (count, c)); +} + +/* Insert the next typed character verbatim. */ +int +rl_quoted_insert (count, key) + int count, key; +{ + int c; + +#if defined (HANDLE_SIGNALS) + _rl_disable_tty_signals (); +#endif + + RL_SETSTATE(RL_STATE_MOREINPUT); + c = rl_read_key (); + RL_UNSETSTATE(RL_STATE_MOREINPUT); + +#if defined (HANDLE_SIGNALS) + _rl_restore_tty_signals (); +#endif + + return (_rl_insert_char (count, c)); +} + +/* Insert a tab character. */ +int +rl_tab_insert (count, key) + int count, key; +{ + return (_rl_insert_char (count, '\t')); +} + +/* What to do when a NEWLINE is pressed. We accept the whole line. + KEY is the key that invoked this command. I guess it could have + meaning in the future. */ +int +rl_newline (count, key) + int count, key; +{ + rl_done = 1; + + if (_rl_history_preserve_point) + _rl_history_saved_point = (rl_point == rl_end) ? -1 : rl_point; + + RL_SETSTATE(RL_STATE_DONE); + +#if defined (VI_MODE) + if (rl_editing_mode == vi_mode) + { + _rl_vi_done_inserting (); + _rl_vi_reset_last (); + } +#endif /* VI_MODE */ + + /* If we've been asked to erase empty lines, suppress the final update, + since _rl_update_final calls rl_crlf(). */ + if (rl_erase_empty_line && rl_point == 0 && rl_end == 0) + return 0; + + if (readline_echoing_p) + _rl_update_final (); + return 0; +} + +/* What to do for some uppercase characters, like meta characters, + and some characters appearing in emacs_ctlx_keymap. This function + is just a stub, you bind keys to it and the code in _rl_dispatch () + is special cased. */ +int +rl_do_lowercase_version (ignore1, ignore2) + int ignore1, ignore2; +{ + return 0; +} + +/* This is different from what vi does, so the code's not shared. Emacs + rubout in overwrite mode has one oddity: it replaces a control + character that's displayed as two characters (^X) with two spaces. */ +int +_rl_overwrite_rubout (count, key) + int count, key; +{ + int opoint; + int i, l; + + if (rl_point == 0) + { + rl_ding (); + return 1; + } + + opoint = rl_point; + + /* L == number of spaces to insert */ + for (i = l = 0; i < count; i++) + { + rl_backward_char (1, key); + l += rl_character_len (rl_line_buffer[rl_point], rl_point); /* not exactly right */ + } + + rl_begin_undo_group (); + + if (count > 1 || rl_explicit_arg) + rl_kill_text (opoint, rl_point); + else + rl_delete_text (opoint, rl_point); + + /* Emacs puts point at the beginning of the sequence of spaces. */ + opoint = rl_point; + _rl_insert_char (l, ' '); + rl_point = opoint; + + rl_end_undo_group (); + + return 0; +} + +/* Rubout the character behind point. */ +int +rl_rubout (count, key) + int count, key; +{ + if (count < 0) + return (rl_delete (-count, key)); + + if (!rl_point) + { + rl_ding (); + return -1; + } + + if (rl_insert_mode == RL_IM_OVERWRITE) + return (_rl_overwrite_rubout (count, key)); + + return (_rl_rubout_char (count, key)); +} + +int +_rl_rubout_char (count, key) + int count, key; +{ + int orig_point; + unsigned char c; + + /* Duplicated code because this is called from other parts of the library. */ + if (count < 0) + return (rl_delete (-count, key)); + + if (rl_point == 0) + { + rl_ding (); + return -1; + } + + if (count > 1 || rl_explicit_arg) + { + orig_point = rl_point; +#if defined (HANDLE_MULTIBYTE) + if (MB_CUR_MAX > 1 && rl_byte_oriented == 0) + rl_backward_char (count, key); + else +#endif + rl_backward_byte (count, key); + rl_kill_text (orig_point, rl_point); + } + else + { +#if defined (HANDLE_MULTIBYTE) + if (MB_CUR_MAX == 1 || rl_byte_oriented) + { +#endif + c = rl_line_buffer[--rl_point]; + rl_delete_text (rl_point, rl_point + 1); +#if defined (HANDLE_MULTIBYTE) + } + else + { + int orig_point; + + orig_point = rl_point; + rl_point = _rl_find_prev_mbchar (rl_line_buffer, rl_point, MB_FIND_NONZERO); + c = rl_line_buffer[rl_point]; + rl_delete_text (rl_point, orig_point); + } +#endif /* HANDLE_MULTIBYTE */ + + /* I don't think that the hack for end of line is needed for + multibyte chars. */ +#if defined (HANDLE_MULTIBYTE) + if (MB_CUR_MAX == 1 || rl_byte_oriented) +#endif + if (rl_point == rl_end && ISPRINT (c) && _rl_last_c_pos) + { + int l; + l = rl_character_len (c, rl_point); + _rl_erase_at_end_of_line (l); + } + } + + return 0; +} + +/* Delete the character under the cursor. Given a numeric argument, + kill that many characters instead. */ +int +rl_delete (count, key) + int count, key; +{ + int r; + + if (count < 0) + return (_rl_rubout_char (-count, key)); + + if (rl_point == rl_end) + { + rl_ding (); + return -1; + } + + if (count > 1 || rl_explicit_arg) + { + int orig_point = rl_point; +#if defined (HANDLE_MULTIBYTE) + if (MB_CUR_MAX > 1 && rl_byte_oriented == 0) + rl_forward_char (count, key); + else +#endif + rl_forward_byte (count, key); + + r = rl_kill_text (orig_point, rl_point); + rl_point = orig_point; + return r; + } + else + { + int new_point; + if (MB_CUR_MAX > 1 && rl_byte_oriented == 0) + new_point = _rl_find_next_mbchar (rl_line_buffer, rl_point, 1, MB_FIND_NONZERO); + else + new_point = rl_point + 1; + + return (rl_delete_text (rl_point, new_point)); + } +} + +/* Delete the character under the cursor, unless the insertion + point is at the end of the line, in which case the character + behind the cursor is deleted. COUNT is obeyed and may be used + to delete forward or backward that many characters. */ +int +rl_rubout_or_delete (count, key) + int count, key; +{ + if (rl_end != 0 && rl_point == rl_end) + return (_rl_rubout_char (count, key)); + else + return (rl_delete (count, key)); +} + +/* Delete all spaces and tabs around point. */ +int +rl_delete_horizontal_space (count, ignore) + int count, ignore; +{ + int start = rl_point; + + while (rl_point && whitespace (rl_line_buffer[rl_point - 1])) + rl_point--; + + start = rl_point; + + while (rl_point < rl_end && whitespace (rl_line_buffer[rl_point])) + rl_point++; + + if (start != rl_point) + { + rl_delete_text (start, rl_point); + rl_point = start; + } + return 0; +} + +/* Like the tcsh editing function delete-char-or-list. The eof character + is caught before this is invoked, so this really does the same thing as + delete-char-or-list-or-eof, as long as it's bound to the eof character. */ +int +rl_delete_or_show_completions (count, key) + int count, key; +{ + if (rl_end != 0 && rl_point == rl_end) + return (rl_possible_completions (count, key)); + else + return (rl_delete (count, key)); +} + +#ifndef RL_COMMENT_BEGIN_DEFAULT +#define RL_COMMENT_BEGIN_DEFAULT "#" +#endif + +/* Turn the current line into a comment in shell history. + A K*rn shell style function. */ +int +rl_insert_comment (count, key) + int count, key; +{ + char *rl_comment_text; + int rl_comment_len; + + rl_beg_of_line (1, key); + rl_comment_text = _rl_comment_begin ? _rl_comment_begin : RL_COMMENT_BEGIN_DEFAULT; + + if (rl_explicit_arg == 0) + rl_insert_text (rl_comment_text); + else + { + rl_comment_len = strlen (rl_comment_text); + if (STREQN (rl_comment_text, rl_line_buffer, rl_comment_len)) + rl_delete_text (rl_point, rl_point + rl_comment_len); + else + rl_insert_text (rl_comment_text); + } + + (*rl_redisplay_function) (); + rl_newline (1, '\n'); + + return (0); +} + +/* **************************************************************** */ +/* */ +/* Changing Case */ +/* */ +/* **************************************************************** */ + +/* The three kinds of things that we know how to do. */ +#define UpCase 1 +#define DownCase 2 +#define CapCase 3 + +/* Uppercase the word at point. */ +int +rl_upcase_word (count, key) + int count, key; +{ + return (rl_change_case (count, UpCase)); +} + +/* Lowercase the word at point. */ +int +rl_downcase_word (count, key) + int count, key; +{ + return (rl_change_case (count, DownCase)); +} + +/* Upcase the first letter, downcase the rest. */ +int +rl_capitalize_word (count, key) + int count, key; +{ + return (rl_change_case (count, CapCase)); +} + +/* The meaty function. + Change the case of COUNT words, performing OP on them. + OP is one of UpCase, DownCase, or CapCase. + If a negative argument is given, leave point where it started, + otherwise, leave it where it moves to. */ +static int +rl_change_case (count, op) + int count, op; +{ + register int start, end; + int inword, c; + + start = rl_point; + rl_forward_word (count, 0); + end = rl_point; + + if (count < 0) + SWAP (start, end); + + /* We are going to modify some text, so let's prepare to undo it. */ + rl_modifying (start, end); + + for (inword = 0; start < end; start++) + { + c = rl_line_buffer[start]; + switch (op) + { + case UpCase: + rl_line_buffer[start] = _rl_to_upper (c); + break; + + case DownCase: + rl_line_buffer[start] = _rl_to_lower (c); + break; + + case CapCase: + rl_line_buffer[start] = (inword == 0) ? _rl_to_upper (c) : _rl_to_lower (c); + inword = rl_alphabetic (rl_line_buffer[start]); + break; + + default: + rl_ding (); + return -1; + } + } + rl_point = end; + return 0; +} + +/* **************************************************************** */ +/* */ +/* Transposition */ +/* */ +/* **************************************************************** */ + +/* Transpose the words at point. If point is at the end of the line, + transpose the two words before point. */ +int +rl_transpose_words (count, key) + int count, key; +{ + char *word1, *word2; + int w1_beg, w1_end, w2_beg, w2_end; + int orig_point = rl_point; + + if (!count) + return 0; + + /* Find the two words. */ + rl_forward_word (count, key); + w2_end = rl_point; + rl_backward_word (1, key); + w2_beg = rl_point; + rl_backward_word (count, key); + w1_beg = rl_point; + rl_forward_word (1, key); + w1_end = rl_point; + + /* Do some check to make sure that there really are two words. */ + if ((w1_beg == w2_beg) || (w2_beg < w1_end)) + { + rl_ding (); + rl_point = orig_point; + return -1; + } + + /* Get the text of the words. */ + word1 = rl_copy_text (w1_beg, w1_end); + word2 = rl_copy_text (w2_beg, w2_end); + + /* We are about to do many insertions and deletions. Remember them + as one operation. */ + rl_begin_undo_group (); + + /* Do the stuff at word2 first, so that we don't have to worry + about word1 moving. */ + rl_point = w2_beg; + rl_delete_text (w2_beg, w2_end); + rl_insert_text (word1); + + rl_point = w1_beg; + rl_delete_text (w1_beg, w1_end); + rl_insert_text (word2); + + /* This is exactly correct since the text before this point has not + changed in length. */ + rl_point = w2_end; + + /* I think that does it. */ + rl_end_undo_group (); + free (word1); + free (word2); + + return 0; +} + +/* Transpose the characters at point. If point is at the end of the line, + then transpose the characters before point. */ +int +rl_transpose_chars (count, key) + int count, key; +{ +#if defined (HANDLE_MULTIBYTE) + char *dummy; + int i, prev_point; +#else + char dummy[2]; +#endif + int char_length; + + if (count == 0) + return 0; + + if (!rl_point || rl_end < 2) + { + rl_ding (); + return -1; + } + + rl_begin_undo_group (); + + if (rl_point == rl_end) + { + if (MB_CUR_MAX > 1 && rl_byte_oriented == 0) + rl_point = _rl_find_prev_mbchar (rl_line_buffer, rl_point, MB_FIND_NONZERO); + else + --rl_point; + count = 1; + } + +#if defined (HANDLE_MULTIBYTE) + prev_point = rl_point; + if (MB_CUR_MAX > 1 && rl_byte_oriented == 0) + rl_point = _rl_find_prev_mbchar (rl_line_buffer, rl_point, MB_FIND_NONZERO); + else +#endif + rl_point--; + +#if defined (HANDLE_MULTIBYTE) + char_length = prev_point - rl_point; + dummy = (char *)xmalloc (char_length + 1); + for (i = 0; i < char_length; i++) + dummy[i] = rl_line_buffer[rl_point + i]; + dummy[i] = '\0'; +#else + dummy[0] = rl_line_buffer[rl_point]; + dummy[char_length = 1] = '\0'; +#endif + + rl_delete_text (rl_point, rl_point + char_length); + + rl_point = _rl_find_next_mbchar (rl_line_buffer, rl_point, count, MB_FIND_NONZERO); + + _rl_fix_point (0); + rl_insert_text (dummy); + rl_end_undo_group (); + +#if defined (HANDLE_MULTIBYTE) + free (dummy); +#endif + + return 0; +} + +/* **************************************************************** */ +/* */ +/* Character Searching */ +/* */ +/* **************************************************************** */ + +int +#if defined (HANDLE_MULTIBYTE) +_rl_char_search_internal (count, dir, smbchar, len) + int count, dir; + char *smbchar; + int len; +#else +_rl_char_search_internal (count, dir, schar) + int count, dir, schar; +#endif +{ + int pos, inc; +#if defined (HANDLE_MULTIBYTE) + int prepos; +#endif + + pos = rl_point; + inc = (dir < 0) ? -1 : 1; + while (count) + { + if ((dir < 0 && pos <= 0) || (dir > 0 && pos >= rl_end)) + { + rl_ding (); + return -1; + } + +#if defined (HANDLE_MULTIBYTE) + pos = (inc > 0) ? _rl_find_next_mbchar (rl_line_buffer, pos, 1, MB_FIND_ANY) + : _rl_find_prev_mbchar (rl_line_buffer, pos, MB_FIND_ANY); +#else + pos += inc; +#endif + do + { +#if defined (HANDLE_MULTIBYTE) + if (_rl_is_mbchar_matched (rl_line_buffer, pos, rl_end, smbchar, len)) +#else + if (rl_line_buffer[pos] == schar) +#endif + { + count--; + if (dir < 0) + rl_point = (dir == BTO) ? _rl_find_next_mbchar (rl_line_buffer, pos, 1, MB_FIND_ANY) + : pos; + else + rl_point = (dir == FTO) ? _rl_find_prev_mbchar (rl_line_buffer, pos, MB_FIND_ANY) + : pos; + break; + } +#if defined (HANDLE_MULTIBYTE) + prepos = pos; +#endif + } +#if defined (HANDLE_MULTIBYTE) + while ((dir < 0) ? (pos = _rl_find_prev_mbchar (rl_line_buffer, pos, MB_FIND_ANY)) != prepos + : (pos = _rl_find_next_mbchar (rl_line_buffer, pos, 1, MB_FIND_ANY)) != prepos); +#else + while ((dir < 0) ? pos-- : ++pos < rl_end); +#endif + } + return (0); +} + +/* Search COUNT times for a character read from the current input stream. + FDIR is the direction to search if COUNT is non-negative; otherwise + the search goes in BDIR. So much is dependent on HANDLE_MULTIBYTE + that there are two separate versions of this function. */ +#if defined (HANDLE_MULTIBYTE) +static int +_rl_char_search (count, fdir, bdir) + int count, fdir, bdir; +{ + char mbchar[MB_LEN_MAX]; + int mb_len; + + mb_len = _rl_read_mbchar (mbchar, MB_LEN_MAX); + + if (count < 0) + return (_rl_char_search_internal (-count, bdir, mbchar, mb_len)); + else + return (_rl_char_search_internal (count, fdir, mbchar, mb_len)); +} +#else /* !HANDLE_MULTIBYTE */ +static int +_rl_char_search (count, fdir, bdir) + int count, fdir, bdir; +{ + int c; + + RL_SETSTATE(RL_STATE_MOREINPUT); + c = rl_read_key (); + RL_UNSETSTATE(RL_STATE_MOREINPUT); + + if (count < 0) + return (_rl_char_search_internal (-count, bdir, c)); + else + return (_rl_char_search_internal (count, fdir, c)); +} +#endif /* !HANDLE_MULTIBYTE */ + +int +rl_char_search (count, key) + int count, key; +{ + return (_rl_char_search (count, FFIND, BFIND)); +} + +int +rl_backward_char_search (count, key) + int count, key; +{ + return (_rl_char_search (count, BFIND, FFIND)); +} + +/* **************************************************************** */ +/* */ +/* The Mark and the Region. */ +/* */ +/* **************************************************************** */ + +/* Set the mark at POSITION. */ +int +_rl_set_mark_at_pos (position) + int position; +{ + if (position > rl_end) + return -1; + + rl_mark = position; + return 0; +} + +/* A bindable command to set the mark. */ +int +rl_set_mark (count, key) + int count, key; +{ + return (_rl_set_mark_at_pos (rl_explicit_arg ? count : rl_point)); +} + +/* Exchange the position of mark and point. */ +int +rl_exchange_point_and_mark (count, key) + int count, key; +{ + if (rl_mark > rl_end) + rl_mark = -1; + + if (rl_mark == -1) + { + rl_ding (); + return -1; + } + else + SWAP (rl_point, rl_mark); + + return 0; +} diff --git a/sim/arm/README b/sim/arm/README new file mode 100644 index 0000000..adfb766 --- /dev/null +++ b/sim/arm/README @@ -0,0 +1,27 @@ + +This directory contains the standard release of the ARMulator from +Advanced RISC Machines, and was ftp'd from. + +ftp.cl.cam.ac.uk:/arm/gnu + +It likes to use TCP/IP between the simulator and the host, which is +nice, but is a pain to use under anything non-unix. + +I've added created a new Makefile.in (the original in Makefile.orig) +to build a version of the simulator without the TCP/IP stuff, and a +wrapper.c to link directly into gdb and the run command. + +It should be possible (barring major changes in the layout of +the armulator) to upgrade the simulator by copying all the files +out of a release into this directory and renaming the Makefile. + +(Except that I changed armos.c to work more simply with our +simulator rigs) + +Steve + +sac@cygnus.com + +Mon May 15 12:03:28 PDT 1995 + + diff --git a/sim/arm/iwmmxt.c b/sim/arm/iwmmxt.c new file mode 100644 index 0000000..72444f6 --- /dev/null +++ b/sim/arm/iwmmxt.c @@ -0,0 +1,3730 @@ +/* iwmmxt.c -- Intel(r) Wireless MMX(tm) technology co-processor interface. + Copyright (C) 2002 Free Software Foundation, Inc. + Contributed by matthew green (mrg@redhat.com). + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include "armdefs.h" +#include "armos.h" +#include "armemu.h" +#include "ansidecl.h" +#include "iwmmxt.h" + +/* #define DEBUG 1 */ + +/* Intel(r) Wireless MMX(tm) technology co-processor. + It uses co-processor numbers (0 and 1). There are 16 vector registers wRx + and 16 control registers wCx. Co-processors 0 and 1 are used in MCR/MRC + to access wRx and wCx respectively. */ + +static ARMdword wR[16]; +static ARMword wC[16] = { 0x69051010 }; + +#define SUBSTR(w,t,m,n) ((t)(w << ((sizeof (t) * 8 - 1) - (n))) \ + >> (((sizeof (t) * 8 - 1) - (n)) + (m))) +#define wCBITS(w,x,y) SUBSTR (wC[w], ARMword, x, y) +#define wRBITS(w,x,y) SUBSTR (wR[w], ARMdword, x, y) +#define wCID 0 +#define wCon 1 +#define wCSSF 2 +#define wCASF 3 +#define wCGR0 8 +#define wCGR1 9 +#define wCGR2 10 +#define wCGR3 11 + +/* Bits in the wCon register. */ +#define WCON_CUP (1 << 0) +#define WCON_MUP (1 << 1) + +/* Set the SIMD wCASF flags for 8, 16, 32 or 64-bit operations. */ +#define SIMD8_SET(x, v, n, b) (x) |= ((v != 0) << ((((b) + 1) * 4) + (n))) +#define SIMD16_SET(x, v, n, h) (x) |= ((v != 0) << ((((h) + 1) * 8) + (n))) +#define SIMD32_SET(x, v, n, w) (x) |= ((v != 0) << ((((w) + 1) * 16) + (n))) +#define SIMD64_SET(x, v, n) (x) |= ((v != 0) << (32 + (n))) + +/* Flags to pass as "n" above. */ +#define SIMD_NBIT -1 +#define SIMD_ZBIT -2 +#define SIMD_CBIT -3 +#define SIMD_VBIT -4 + +/* Various status bit macros. */ +#define NBIT8(x) ((x) & 0x80) +#define NBIT16(x) ((x) & 0x8000) +#define NBIT32(x) ((x) & 0x80000000) +#define NBIT64(x) ((x) & 0x8000000000000000ULL) +#define ZBIT8(x) (((x) & 0xff) == 0) +#define ZBIT16(x) (((x) & 0xffff) == 0) +#define ZBIT32(x) (((x) & 0xffffffff) == 0) +#define ZBIT64(x) (x == 0) + +/* Access byte/half/word "n" of register "x". */ +#define wRBYTE(x,n) wRBITS ((x), (n) * 8, (n) * 8 + 7) +#define wRHALF(x,n) wRBITS ((x), (n) * 16, (n) * 16 + 15) +#define wRWORD(x,n) wRBITS ((x), (n) * 32, (n) * 32 + 31) + +/* Macro to handle how the G bit selects wCGR registers. */ +#define DECODE_G_BIT(state, instr, shift) \ +{ \ + unsigned int reg; \ + \ + reg = BITS (0, 3); \ + \ + if (BIT (8)) /* G */ \ + { \ + if (reg < wCGR0 || reg > wCGR3) \ + { \ + ARMul_UndefInstr (state, instr); \ + return ARMul_DONE; \ + } \ + shift = wC [reg]; \ + } \ + else \ + shift = wR [reg]; \ + \ + shift &= 0xff; \ +} + +/* Index calculations for the satrv[] array. */ +#define BITIDX8(x) (x) +#define BITIDX16(x) (((x) + 1) * 2 - 1) +#define BITIDX32(x) (((x) + 1) * 4 - 1) + +/* Sign extension macros. */ +#define EXTEND8(a) ((a) & 0x80 ? ((a) | 0xffffff00) : (a)) +#define EXTEND16(a) ((a) & 0x8000 ? ((a) | 0xffff0000) : (a)) +#define EXTEND32(a) ((a) & 0x80000000ULL ? ((a) | 0xffffffff00000000ULL) : (a)) + +/* Set the wCSSF from 8 values. */ +#define SET_wCSSF(a,b,c,d,e,f,g,h) \ + wC[wCSSF] = (((h) != 0) << 7) | (((g) != 0) << 6) \ + | (((f) != 0) << 5) | (((e) != 0) << 4) \ + | (((d) != 0) << 3) | (((c) != 0) << 2) \ + | (((b) != 0) << 1) | (((a) != 0) << 0); + +/* Set the wCSSR from an array with 8 values. */ +#define SET_wCSSFvec(v) \ + SET_wCSSF((v)[0],(v)[1],(v)[2],(v)[3],(v)[4],(v)[5],(v)[6],(v)[7]) + +/* Size qualifiers for vector operations. */ +#define Bqual 0 +#define Hqual 1 +#define Wqual 2 +#define Dqual 3 + +/* Saturation qualifiers for vector operations. */ +#define NoSaturation 0 +#define UnsignedSaturation 1 +#define SignedSaturation 3 + + +/* Prototypes. */ +static ARMword Add32 (ARMword, ARMword, int *, int *, ARMword); +static ARMdword AddS32 (ARMdword, ARMdword, int *, int *); +static ARMdword AddU32 (ARMdword, ARMdword, int *, int *); +static ARMword AddS16 (ARMword, ARMword, int *, int *); +static ARMword AddU16 (ARMword, ARMword, int *, int *); +static ARMword AddS8 (ARMword, ARMword, int *, int *); +static ARMword AddU8 (ARMword, ARMword, int *, int *); +static ARMword Sub32 (ARMword, ARMword, int *, int *, ARMword); +static ARMdword SubS32 (ARMdword, ARMdword, int *, int *); +static ARMdword SubU32 (ARMdword, ARMdword, int *, int *); +static ARMword SubS16 (ARMword, ARMword, int *, int *); +static ARMword SubS8 (ARMword, ARMword, int *, int *); +static ARMword SubU16 (ARMword, ARMword, int *, int *); +static ARMword SubU8 (ARMword, ARMword, int *, int *); +static unsigned char IwmmxtSaturateU8 (signed short, int *); +static signed char IwmmxtSaturateS8 (signed short, int *); +static unsigned short IwmmxtSaturateU16 (signed int, int *); +static signed short IwmmxtSaturateS16 (signed int, int *); +static unsigned long IwmmxtSaturateU32 (signed long long, int *); +static signed long IwmmxtSaturateS32 (signed long long, int *); +static ARMword Compute_Iwmmxt_Address (ARMul_State *, ARMword, int *); +static ARMdword Iwmmxt_Load_Double_Word (ARMul_State *, ARMword); +static ARMword Iwmmxt_Load_Word (ARMul_State *, ARMword); +static ARMword Iwmmxt_Load_Half_Word (ARMul_State *, ARMword); +static ARMword Iwmmxt_Load_Byte (ARMul_State *, ARMword); +static void Iwmmxt_Store_Double_Word (ARMul_State *, ARMword, ARMdword); +static void Iwmmxt_Store_Word (ARMul_State *, ARMword, ARMword); +static void Iwmmxt_Store_Half_Word (ARMul_State *, ARMword, ARMword); +static void Iwmmxt_Store_Byte (ARMul_State *, ARMword, ARMword); +static int Process_Instruction (ARMul_State *, ARMword); + +static int TANDC (ARMul_State *, ARMword); +static int TBCST (ARMul_State *, ARMword); +static int TEXTRC (ARMul_State *, ARMword); +static int TEXTRM (ARMul_State *, ARMword); +static int TINSR (ARMul_State *, ARMword); +static int TMCR (ARMul_State *, ARMword); +static int TMCRR (ARMul_State *, ARMword); +static int TMIA (ARMul_State *, ARMword); +static int TMIAPH (ARMul_State *, ARMword); +static int TMIAxy (ARMul_State *, ARMword); +static int TMOVMSK (ARMul_State *, ARMword); +static int TMRC (ARMul_State *, ARMword); +static int TMRRC (ARMul_State *, ARMword); +static int TORC (ARMul_State *, ARMword); +static int WACC (ARMul_State *, ARMword); +static int WADD (ARMul_State *, ARMword); +static int WALIGNI (ARMword); +static int WALIGNR (ARMul_State *, ARMword); +static int WAND (ARMword); +static int WANDN (ARMword); +static int WAVG2 (ARMword); +static int WCMPEQ (ARMul_State *, ARMword); +static int WCMPGT (ARMul_State *, ARMword); +static int WLDR (ARMul_State *, ARMword); +static int WMAC (ARMword); +static int WMADD (ARMword); +static int WMAX (ARMul_State *, ARMword); +static int WMIN (ARMul_State *, ARMword); +static int WMUL (ARMword); +static int WOR (ARMword); +static int WPACK (ARMul_State *, ARMword); +static int WROR (ARMul_State *, ARMword); +static int WSAD (ARMword); +static int WSHUFH (ARMword); +static int WSLL (ARMul_State *, ARMword); +static int WSRA (ARMul_State *, ARMword); +static int WSRL (ARMul_State *, ARMword); +static int WSTR (ARMul_State *, ARMword); +static int WSUB (ARMul_State *, ARMword); +static int WUNPCKEH (ARMul_State *, ARMword); +static int WUNPCKEL (ARMul_State *, ARMword); +static int WUNPCKIH (ARMul_State *, ARMword); +static int WUNPCKIL (ARMul_State *, ARMword); +static int WXOR (ARMword); + +/* This function does the work of adding two 32bit values + together, and calculating if a carry has occurred. */ + +static ARMword +Add32 (ARMword a1, + ARMword a2, + int * carry_ptr, + int * overflow_ptr, + ARMword sign_mask) +{ + ARMword result = (a1 + a2); + unsigned int uresult = (unsigned int) result; + unsigned int ua1 = (unsigned int) a1; + + /* If (result == a1) and (a2 == 0), + or (result > a2) then we have no carry. */ + * carry_ptr = ((uresult == ua1) ? (a2 != 0) : (uresult < ua1)); + + /* Overflow occurs when both arguments are the + same sign, but the result is a different sign. */ + * overflow_ptr = ( ( (result & sign_mask) && !(a1 & sign_mask) && !(a2 & sign_mask)) + || (!(result & sign_mask) && (a1 & sign_mask) && (a2 & sign_mask))); + + return result; +} + +static ARMdword +AddS32 (ARMdword a1, ARMdword a2, int * carry_ptr, int * overflow_ptr) +{ + ARMdword result; + unsigned int uresult; + unsigned int ua1; + + a1 = EXTEND32 (a1); + a2 = EXTEND32 (a2); + + result = a1 + a2; + uresult = (unsigned int) result; + ua1 = (unsigned int) a1; + + * carry_ptr = ((uresult == a1) ? (a2 != 0) : (uresult < ua1)); + + * overflow_ptr = ( ( (result & 0x80000000ULL) && !(a1 & 0x80000000ULL) && !(a2 & 0x80000000ULL)) + || (!(result & 0x80000000ULL) && (a1 & 0x80000000ULL) && (a2 & 0x80000000ULL))); + + return result; +} + +static ARMdword +AddU32 (ARMdword a1, ARMdword a2, int * carry_ptr, int * overflow_ptr) +{ + ARMdword result; + unsigned int uresult; + unsigned int ua1; + + a1 &= 0xffffffff; + a2 &= 0xffffffff; + + result = a1 + a2; + uresult = (unsigned int) result; + ua1 = (unsigned int) a1; + + * carry_ptr = ((uresult == a1) ? (a2 != 0) : (uresult < ua1)); + + * overflow_ptr = ( ( (result & 0x80000000ULL) && !(a1 & 0x80000000ULL) && !(a2 & 0x80000000ULL)) + || (!(result & 0x80000000ULL) && (a1 & 0x80000000ULL) && (a2 & 0x80000000ULL))); + + return result; +} + +static ARMword +AddS16 (ARMword a1, ARMword a2, int * carry_ptr, int * overflow_ptr) +{ + a1 = EXTEND16 (a1); + a2 = EXTEND16 (a2); + + return Add32 (a1, a2, carry_ptr, overflow_ptr, 0x8000); +} + +static ARMword +AddU16 (ARMword a1, ARMword a2, int * carry_ptr, int * overflow_ptr) +{ + a1 &= 0xffff; + a2 &= 0xffff; + + return Add32 (a1, a2, carry_ptr, overflow_ptr, 0x8000); +} + +static ARMword +AddS8 (ARMword a1, ARMword a2, int * carry_ptr, int * overflow_ptr) +{ + a1 = EXTEND8 (a1); + a2 = EXTEND8 (a2); + + return Add32 (a1, a2, carry_ptr, overflow_ptr, 0x80); +} + +static ARMword +AddU8 (ARMword a1, ARMword a2, int * carry_ptr, int * overflow_ptr) +{ + a1 &= 0xff; + a2 &= 0xff; + + return Add32 (a1, a2, carry_ptr, overflow_ptr, 0x80); +} + +static ARMword +Sub32 (ARMword a1, + ARMword a2, + int * borrow_ptr, + int * overflow_ptr, + ARMword sign_mask) +{ + ARMword result = (a1 - a2); + unsigned int ua1 = (unsigned int) a1; + unsigned int ua2 = (unsigned int) a2; + + /* A borrow occurs if a2 is (unsigned) larger than a1. + However the carry flag is *cleared* if a borrow occurs. */ + * borrow_ptr = ! (ua2 > ua1); + + /* Overflow occurs when a negative number is subtracted from a + positive number and the result is negative or a positive + number is subtracted from a negative number and the result is + positive. */ + * overflow_ptr = ( (! (a1 & sign_mask) && (a2 & sign_mask) && (result & sign_mask)) + || ((a1 & sign_mask) && ! (a2 & sign_mask) && ! (result & sign_mask))); + + return result; +} + +static ARMdword +SubS32 (ARMdword a1, ARMdword a2, int * borrow_ptr, int * overflow_ptr) +{ + ARMdword result; + unsigned int ua1; + unsigned int ua2; + + a1 = EXTEND32 (a1); + a2 = EXTEND32 (a2); + + result = a1 - a2; + ua1 = (unsigned int) a1; + ua2 = (unsigned int) a2; + + * borrow_ptr = ! (ua2 > ua1); + + * overflow_ptr = ( (! (a1 & 0x80000000ULL) && (a2 & 0x80000000ULL) && (result & 0x80000000ULL)) + || ((a1 & 0x80000000ULL) && ! (a2 & 0x80000000ULL) && ! (result & 0x80000000ULL))); + + return result; +} + +static ARMword +SubS16 (ARMword a1, ARMword a2, int * carry_ptr, int * overflow_ptr) +{ + a1 = EXTEND16 (a1); + a2 = EXTEND16 (a2); + + return Sub32 (a1, a2, carry_ptr, overflow_ptr, 0x8000); +} + +static ARMword +SubS8 (ARMword a1, ARMword a2, int * carry_ptr, int * overflow_ptr) +{ + a1 = EXTEND8 (a1); + a2 = EXTEND8 (a2); + + return Sub32 (a1, a2, carry_ptr, overflow_ptr, 0x80); +} + +static ARMword +SubU16 (ARMword a1, ARMword a2, int * carry_ptr, int * overflow_ptr) +{ + a1 &= 0xffff; + a2 &= 0xffff; + + return Sub32 (a1, a2, carry_ptr, overflow_ptr, 0x8000); +} + +static ARMword +SubU8 (ARMword a1, ARMword a2, int * carry_ptr, int * overflow_ptr) +{ + a1 &= 0xff; + a2 &= 0xff; + + return Sub32 (a1, a2, carry_ptr, overflow_ptr, 0x80); +} + +static ARMdword +SubU32 (ARMdword a1, ARMdword a2, int * borrow_ptr, int * overflow_ptr) +{ + ARMdword result; + unsigned int ua1; + unsigned int ua2; + + a1 &= 0xffffffff; + a2 &= 0xffffffff; + + result = a1 - a2; + ua1 = (unsigned int) a1; + ua2 = (unsigned int) a2; + + * borrow_ptr = ! (ua2 > ua1); + + * overflow_ptr = ( (! (a1 & 0x80000000ULL) && (a2 & 0x80000000ULL) && (result & 0x80000000ULL)) + || ((a1 & 0x80000000ULL) && ! (a2 & 0x80000000ULL) && ! (result & 0x80000000ULL))); + + return result; +} + +/* For the saturation. */ + +static unsigned char +IwmmxtSaturateU8 (signed short val, int * sat) +{ + unsigned char rv; + + if (val < 0) + { + rv = 0; + *sat = 1; + } + else if (val > 0xff) + { + rv = 0xff; + *sat = 1; + } + else + { + rv = val & 0xff; + *sat = 0; + } + return rv; +} + +static signed char +IwmmxtSaturateS8 (signed short val, int * sat) +{ + signed char rv; + + if (val < -0x80) + { + rv = -0x80; + *sat = 1; + } + else if (val > 0x7f) + { + rv = 0x7f; + *sat = 1; + } + else + { + rv = val & 0xff; + *sat = 0; + } + return rv; +} + +static unsigned short +IwmmxtSaturateU16 (signed int val, int * sat) +{ + unsigned short rv; + + if (val < 0) + { + rv = 0; + *sat = 1; + } + else if (val > 0xffff) + { + rv = 0xffff; + *sat = 1; + } + else + { + rv = val & 0xffff; + *sat = 0; + } + return rv; +} + +static signed short +IwmmxtSaturateS16 (signed int val, int * sat) +{ + signed short rv; + + if (val < -0x8000) + { + rv = - 0x8000; + *sat = 1; + } + else if (val > 0x7fff) + { + rv = 0x7fff; + *sat = 1; + } + else + { + rv = val & 0xffff; + *sat = 0; + } + return rv; +} + +static unsigned long +IwmmxtSaturateU32 (signed long long val, int * sat) +{ + unsigned long rv; + + if (val < 0) + { + rv = 0; + *sat = 1; + } + else if (val > 0xffffffff) + { + rv = 0xffffffff; + *sat = 1; + } + else + { + rv = val & 0xffffffff; + *sat = 0; + } + return rv; +} + +static signed long +IwmmxtSaturateS32 (signed long long val, int * sat) +{ + signed long rv; + + if (val < -0x80000000LL) + { + rv = -0x80000000; + *sat = 1; + } + else if (val > 0x7fffffff) + { + rv = 0x7fffffff; + *sat = 1; + } + else + { + rv = val & 0xffffffff; + *sat = 0; + } + return rv; +} + +/* Intel(r) Wireless MMX(tm) technology Acessor functions. */ + +unsigned +IwmmxtLDC (ARMul_State * state ATTRIBUTE_UNUSED, + unsigned type ATTRIBUTE_UNUSED, + ARMword instr, + ARMword data) +{ + return ARMul_CANT; +} + +unsigned +IwmmxtSTC (ARMul_State * state ATTRIBUTE_UNUSED, + unsigned type ATTRIBUTE_UNUSED, + ARMword instr, + ARMword * data) +{ + return ARMul_CANT; +} + +unsigned +IwmmxtMRC (ARMul_State * state ATTRIBUTE_UNUSED, + unsigned type ATTRIBUTE_UNUSED, + ARMword instr, + ARMword * value) +{ + return ARMul_CANT; +} + +unsigned +IwmmxtMCR (ARMul_State * state ATTRIBUTE_UNUSED, + unsigned type ATTRIBUTE_UNUSED, + ARMword instr, + ARMword value) +{ + return ARMul_CANT; +} + +unsigned +IwmmxtCDP (ARMul_State * state, unsigned type, ARMword instr) +{ + return ARMul_CANT; +} + +/* Intel(r) Wireless MMX(tm) technology instruction implementations. */ + +static int +TANDC (ARMul_State * state, ARMword instr) +{ + ARMword cpsr; + + if ((read_cp15_reg (15, 0, 1) & 3) != 3) + return ARMul_CANT; + +#ifdef DEBUG + fprintf (stderr, "tandc\n"); +#endif + + /* The Rd field must be r15. */ + if (BITS (12, 15) != 15) + return ARMul_CANT; + + /* The CRn field must be r3. */ + if (BITS (16, 19) != 3) + return ARMul_CANT; + + /* The CRm field must be r0. */ + if (BITS (0, 3) != 0) + return ARMul_CANT; + + cpsr = ARMul_GetCPSR (state) & 0x0fffffff; + + switch (BITS (22, 23)) + { + case Bqual: + cpsr |= ( (wCBITS (wCASF, 28, 31) & wCBITS (wCASF, 24, 27) + & wCBITS (wCASF, 20, 23) & wCBITS (wCASF, 16, 19) + & wCBITS (wCASF, 12, 15) & wCBITS (wCASF, 8, 11) + & wCBITS (wCASF, 4, 7) & wCBITS (wCASF, 0, 3)) << 28); + break; + + case Hqual: + cpsr |= ( (wCBITS (wCASF, 28, 31) & wCBITS (wCASF, 20, 23) + & wCBITS (wCASF, 12, 15) & wCBITS (wCASF, 4, 7)) << 28); + break; + + case Wqual: + cpsr |= ((wCBITS (wCASF, 28, 31) & wCBITS (wCASF, 12, 15)) << 28); + break; + + default: + ARMul_UndefInstr (state, instr); + return ARMul_DONE; + } + + ARMul_SetCPSR (state, cpsr); + + return ARMul_DONE; +} + +static int +TBCST (ARMul_State * state, ARMword instr) +{ + ARMdword Rn; + int wRd; + + if ((read_cp15_reg (15, 0, 1) & 3) != 3) + return ARMul_CANT; + +#ifdef DEBUG + fprintf (stderr, "tbcst\n"); +#endif + + Rn = state->Reg [BITS (12, 15)]; + if (BITS (12, 15) == 15) + Rn &= 0xfffffffc; + + wRd = BITS (16, 19); + + switch (BITS (6, 7)) + { + case Bqual: + Rn &= 0xff; + wR [wRd] = (Rn << 56) | (Rn << 48) | (Rn << 40) | (Rn << 32) + | (Rn << 24) | (Rn << 16) | (Rn << 8) | Rn; + break; + + case Hqual: + Rn &= 0xffff; + wR [wRd] = (Rn << 48) | (Rn << 32) | (Rn << 16) | Rn; + break; + + case Wqual: + Rn &= 0xffffffff; + wR [wRd] = (Rn << 32) | Rn; + break; + + default: + ARMul_UndefInstr (state, instr); + break; + } + + wC [wCon] |= WCON_MUP; + return ARMul_DONE; +} + +static int +TEXTRC (ARMul_State * state, ARMword instr) +{ + ARMword cpsr; + ARMword selector; + + if ((read_cp15_reg (15, 0, 1) & 3) != 3) + return ARMul_CANT; + +#ifdef DEBUG + fprintf (stderr, "textrc\n"); +#endif + + /* The Rd field must be r15. */ + if (BITS (12, 15) != 15) + return ARMul_CANT; + + /* The CRn field must be r3. */ + if (BITS (16, 19) != 3) + return ARMul_CANT; + + /* The CRm field must be 0xxx. */ + if (BIT (3) != 0) + return ARMul_CANT; + + selector = BITS (0, 2); + cpsr = ARMul_GetCPSR (state) & 0x0fffffff; + + switch (BITS (22, 23)) + { + case Bqual: selector *= 4; break; + case Hqual: selector = ((selector & 3) * 8) + 4; break; + case Wqual: selector = ((selector & 1) * 16) + 12; break; + + default: + ARMul_UndefInstr (state, instr); + return ARMul_DONE; + } + + cpsr |= wCBITS (wCASF, selector, selector + 3) << 28; + ARMul_SetCPSR (state, cpsr); + + return ARMul_DONE; +} + +static int +TEXTRM (ARMul_State * state, ARMword instr) +{ + ARMword Rd; + int offset; + int wRn; + int sign; + + if ((read_cp15_reg (15, 0, 1) & 3) != 3) + return ARMul_CANT; + +#ifdef DEBUG + fprintf (stderr, "textrm\n"); +#endif + + wRn = BITS (16, 19); + sign = BIT (3); + offset = BITS (0, 2); + + switch (BITS (22, 23)) + { + case Bqual: + offset *= 8; + Rd = wRBITS (wRn, offset, offset + 7); + if (sign) + Rd = EXTEND8 (Rd); + break; + + case Hqual: + offset = (offset & 3) * 16; + Rd = wRBITS (wRn, offset, offset + 15); + if (sign) + Rd = EXTEND16 (Rd); + break; + + case Wqual: + offset = (offset & 1) * 32; + Rd = wRBITS (wRn, offset, offset + 31); + break; + + default: + ARMul_UndefInstr (state, instr); + return ARMul_DONE; + } + + if (BITS (12, 15) == 15) + ARMul_UndefInstr (state, instr); + else + state->Reg [BITS (12, 15)] = Rd; + + return ARMul_DONE; +} + +static int +TINSR (ARMul_State * state, ARMword instr) +{ + ARMdword data; + ARMword offset; + int wRd; + + if ((read_cp15_reg (15, 0, 1) & 3) != 3) + return ARMul_CANT; + +#ifdef DEBUG + fprintf (stderr, "tinsr\n"); +#endif + + wRd = BITS (16, 19); + data = state->Reg [BITS (12, 15)]; + offset = BITS (0, 2); + + switch (BITS (6, 7)) + { + case Bqual: + data &= 0xff; + switch (offset) + { + case 0: wR [wRd] = data | (wRBITS (wRd, 8, 63) << 8); break; + case 1: wR [wRd] = wRBITS (wRd, 0, 7) | (data << 8) | (wRBITS (wRd, 16, 63) << 16); break; + case 2: wR [wRd] = wRBITS (wRd, 0, 15) | (data << 16) | (wRBITS (wRd, 24, 63) << 24); break; + case 3: wR [wRd] = wRBITS (wRd, 0, 23) | (data << 24) | (wRBITS (wRd, 32, 63) << 32); break; + case 4: wR [wRd] = wRBITS (wRd, 0, 31) | (data << 32) | (wRBITS (wRd, 40, 63) << 40); break; + case 5: wR [wRd] = wRBITS (wRd, 0, 39) | (data << 40) | (wRBITS (wRd, 48, 63) << 48); break; + case 6: wR [wRd] = wRBITS (wRd, 0, 47) | (data << 48) | (wRBITS (wRd, 56, 63) << 56); break; + case 7: wR [wRd] = wRBITS (wRd, 0, 55) | (data << 56); break; + } + break; + + case Hqual: + data &= 0xffff; + + switch (offset & 3) + { + case 0: wR [wRd] = data | (wRBITS (wRd, 16, 63) << 16); break; + case 1: wR [wRd] = wRBITS (wRd, 0, 15) | (data << 16) | (wRBITS (wRd, 32, 63) << 32); break; + case 2: wR [wRd] = wRBITS (wRd, 0, 31) | (data << 32) | (wRBITS (wRd, 48, 63) << 48); break; + case 3: wR [wRd] = wRBITS (wRd, 0, 47) | (data << 48); break; + } + break; + + case Wqual: + if (offset & 1) + wR [wRd] = wRBITS (wRd, 0, 31) | (data << 32); + else + wR [wRd] = (wRBITS (wRd, 32, 63) << 32) | data; + break; + + default: + ARMul_UndefInstr (state, instr); + break; + } + + wC [wCon] |= WCON_MUP; + return ARMul_DONE; +} + +static int +TMCR (ARMul_State * state, ARMword instr) +{ + ARMword val; + int wCreg; + + if ((read_cp15_reg (15, 0, 1) & 3) != 3) + return ARMul_CANT; + +#ifdef DEBUG + fprintf (stderr, "tmcr\n"); +#endif + + if (BITS (0, 3) != 0) + return ARMul_CANT; + + val = state->Reg [BITS (12, 15)]; + if (BITS (12, 15) == 15) + val &= 0xfffffffc; + + wCreg = BITS (16, 19); + + switch (wCreg) + { + case wCID: + /* The wCID register is read only. */ + break; + + case wCon: + /* Writing to the MUP or CUP bits clears them. */ + wC [wCon] &= ~ (val & 0x3); + break; + + case wCSSF: + /* Only the bottom 8 bits can be written to. + The higher bits write as zero. */ + wC [wCSSF] = (val & 0xff); + wC [wCon] |= WCON_CUP; + break; + + default: + wC [wCreg] = val; + wC [wCon] |= WCON_CUP; + break; + } + + return ARMul_DONE; +} + +static int +TMCRR (ARMul_State * state, ARMword instr) +{ + ARMdword RdHi = state->Reg [BITS (16, 19)]; + ARMword RdLo = state->Reg [BITS (12, 15)]; + + if ((read_cp15_reg (15, 0, 1) & 3) != 3) + return ARMul_CANT; + +#ifdef DEBUG + fprintf (stderr, "tmcrr\n"); +#endif + + if ((BITS (16, 19) == 15) || (BITS (12, 15) == 15)) + return ARMul_CANT; + + wR [BITS (0, 3)] = (RdHi << 32) | RdLo; + + wC [wCon] |= WCON_MUP; + + return ARMul_DONE; +} + +static int +TMIA (ARMul_State * state, ARMword instr) +{ + signed long long a, b; + + if ((read_cp15_reg (15, 0, 1) & 3) != 3) + return ARMul_CANT; + +#ifdef DEBUG + fprintf (stderr, "tmia\n"); +#endif + + if ((BITS (0, 3) == 15) || (BITS (12, 15) == 15)) + { + ARMul_UndefInstr (state, instr); + return ARMul_DONE; + } + + a = state->Reg [BITS (0, 3)]; + b = state->Reg [BITS (12, 15)]; + + a = EXTEND32 (a); + b = EXTEND32 (b); + + wR [BITS (5, 8)] += a * b; + wC [wCon] |= WCON_MUP; + + return ARMul_DONE; +} + +static int +TMIAPH (ARMul_State * state, ARMword instr) +{ + signed long a, b, result; + signed long long r; + ARMword Rm = state->Reg [BITS (0, 3)]; + ARMword Rs = state->Reg [BITS (12, 15)]; + + if ((read_cp15_reg (15, 0, 1) & 3) != 3) + return ARMul_CANT; + +#ifdef DEBUG + fprintf (stderr, "tmiaph\n"); +#endif + + if (BITS (0, 3) == 15 || BITS (12, 15) == 15) + { + ARMul_UndefInstr (state, instr); + return ARMul_DONE; + } + + a = SUBSTR (Rs, ARMword, 16, 31); + b = SUBSTR (Rm, ARMword, 16, 31); + + a = EXTEND16 (a); + b = EXTEND16 (b); + + result = a * b; + + r = result; + r = EXTEND32 (r); + + wR [BITS (5, 8)] += r; + + a = SUBSTR (Rs, ARMword, 0, 15); + b = SUBSTR (Rm, ARMword, 0, 15); + + a = EXTEND16 (a); + b = EXTEND16 (b); + + result = a * b; + + r = result; + r = EXTEND32 (r); + + wR [BITS (5, 8)] += r; + wC [wCon] |= WCON_MUP; + + return ARMul_DONE; +} + +static int +TMIAxy (ARMul_State * state, ARMword instr) +{ + ARMword Rm; + ARMword Rs; + long long temp; + + if ((read_cp15_reg (15, 0, 1) & 3) != 3) + return ARMul_CANT; + +#ifdef DEBUG + fprintf (stderr, "tmiaxy\n"); +#endif + + if (BITS (0, 3) == 15 || BITS (12, 15) == 15) + { + ARMul_UndefInstr (state, instr); + return ARMul_DONE; + } + + Rm = state->Reg [BITS (0, 3)]; + if (BIT (17)) + Rm >>= 16; + else + Rm &= 0xffff; + + Rs = state->Reg [BITS (12, 15)]; + if (BIT (16)) + Rs >>= 16; + else + Rs &= 0xffff; + + if (Rm & (1 << 15)) + Rm -= 1 << 16; + + if (Rs & (1 << 15)) + Rs -= 1 << 16; + + Rm *= Rs; + temp = Rm; + + if (temp & (1 << 31)) + temp -= 1ULL << 32; + + wR [BITS (5, 8)] += temp; + wC [wCon] |= WCON_MUP; + + return ARMul_DONE; +} + +static int +TMOVMSK (ARMul_State * state, ARMword instr) +{ + ARMdword result; + int wRn; + + if ((read_cp15_reg (15, 0, 1) & 3) != 3) + return ARMul_CANT; + +#ifdef DEBUG + fprintf (stderr, "tmovmsk\n"); +#endif + + /* The CRm field must be r0. */ + if (BITS (0, 3) != 0) + return ARMul_CANT; + + wRn = BITS (16, 19); + + switch (BITS (22, 23)) + { + case Bqual: + result = ( (wRBITS (wRn, 63, 63) << 7) + | (wRBITS (wRn, 55, 55) << 6) + | (wRBITS (wRn, 47, 47) << 5) + | (wRBITS (wRn, 39, 39) << 4) + | (wRBITS (wRn, 31, 31) << 3) + | (wRBITS (wRn, 23, 23) << 2) + | (wRBITS (wRn, 15, 15) << 1) + | (wRBITS (wRn, 7, 7) << 0)); + break; + + case Hqual: + result = ( (wRBITS (wRn, 63, 63) << 3) + | (wRBITS (wRn, 47, 47) << 2) + | (wRBITS (wRn, 31, 31) << 1) + | (wRBITS (wRn, 15, 15) << 0)); + break; + + case Wqual: + result = (wRBITS (wRn, 63, 63) << 1) | wRBITS (wRn, 31, 31); + break; + + default: + ARMul_UndefInstr (state, instr); + return ARMul_DONE; + } + + state->Reg [BITS (12, 15)] = result; + + return ARMul_DONE; +} + +static int +TMRC (ARMul_State * state, ARMword instr) +{ + int reg = BITS (12, 15); + + if ((read_cp15_reg (15, 0, 1) & 3) != 3) + return ARMul_CANT; + +#ifdef DEBUG + fprintf (stderr, "tmrc\n"); +#endif + + if (BITS (0, 3) != 0) + return ARMul_CANT; + + if (reg == 15) + ARMul_UndefInstr (state, instr); + else + state->Reg [reg] = wC [BITS (16, 19)]; + + return ARMul_DONE; +} + +static int +TMRRC (ARMul_State * state, ARMword instr) +{ + if ((read_cp15_reg (15, 0, 1) & 3) != 3) + return ARMul_CANT; + +#ifdef DEBUG + fprintf (stderr, "tmrrc\n"); +#endif + + if ((BITS (16, 19) == 15) || (BITS (12, 15) == 15) || (BITS (4, 11) != 0)) + ARMul_UndefInstr (state, instr); + else + { + state->Reg [BITS (16, 19)] = wRBITS (BITS (0, 3), 32, 63); + state->Reg [BITS (12, 15)] = wRBITS (BITS (0, 3), 0, 31); + } + + return ARMul_DONE; +} + +static int +TORC (ARMul_State * state, ARMword instr) +{ + ARMword cpsr = ARMul_GetCPSR (state); + + if ((read_cp15_reg (15, 0, 1) & 3) != 3) + return ARMul_CANT; + +#ifdef DEBUG + fprintf (stderr, "torc\n"); +#endif + + /* The Rd field must be r15. */ + if (BITS (12, 15) != 15) + return ARMul_CANT; + + /* The CRn field must be r3. */ + if (BITS (16, 19) != 3) + return ARMul_CANT; + + /* The CRm field must be r0. */ + if (BITS (0, 3) != 0) + return ARMul_CANT; + + cpsr &= 0x0fffffff; + + switch (BITS (22, 23)) + { + case Bqual: + cpsr |= ( (wCBITS (wCASF, 28, 31) | wCBITS (wCASF, 24, 27) + | wCBITS (wCASF, 20, 23) | wCBITS (wCASF, 16, 19) + | wCBITS (wCASF, 12, 15) | wCBITS (wCASF, 8, 11) + | wCBITS (wCASF, 4, 7) | wCBITS (wCASF, 0, 3)) << 28); + break; + + case Hqual: + cpsr |= ( (wCBITS (wCASF, 28, 31) | wCBITS (wCASF, 20, 23) + | wCBITS (wCASF, 12, 15) | wCBITS (wCASF, 4, 7)) << 28); + break; + + case Wqual: + cpsr |= ((wCBITS (wCASF, 28, 31) | wCBITS (wCASF, 12, 15)) << 28); + break; + + default: + ARMul_UndefInstr (state, instr); + return ARMul_DONE; + } + + ARMul_SetCPSR (state, cpsr); + + return ARMul_DONE; +} + +static int +WACC (ARMul_State * state, ARMword instr) +{ + int wRn; + + if ((read_cp15_reg (15, 0, 1) & 3) != 3) + return ARMul_CANT; + +#ifdef DEBUG + fprintf (stderr, "wacc\n"); +#endif + + wRn = BITS (16, 19); + + switch (BITS (22, 23)) + { + case Bqual: + wR [BITS (12, 15)] = + wRBITS (wRn, 56, 63) + wRBITS (wRn, 48, 55) + + wRBITS (wRn, 40, 47) + wRBITS (wRn, 32, 39) + + wRBITS (wRn, 24, 31) + wRBITS (wRn, 16, 23) + + wRBITS (wRn, 8, 15) + wRBITS (wRn, 0, 7); + break; + + case Hqual: + wR [BITS (12, 15)] = + wRBITS (wRn, 48, 63) + wRBITS (wRn, 32, 47) + + wRBITS (wRn, 16, 31) + wRBITS (wRn, 0, 15); + break; + + case Wqual: + wR [BITS (12, 15)] = wRBITS (wRn, 32, 63) + wRBITS (wRn, 0, 31); + break; + + default: + ARMul_UndefInstr (state, instr); + break; + } + + wC [wCon] |= WCON_MUP; + return ARMul_DONE; +} + +static int +WADD (ARMul_State * state, ARMword instr) +{ + ARMdword r = 0; + ARMdword x; + ARMdword s; + ARMword psr = 0; + int i; + int carry; + int overflow; + int satrv[8]; + + if ((read_cp15_reg (15, 0, 1) & 3) != 3) + return ARMul_CANT; + +#ifdef DEBUG + fprintf (stderr, "wadd\n"); +#endif + + /* Add two numbers using the specified function, + leaving setting the carry bit as required. */ +#define ADDx(x, y, m, f) \ + (*f) (wRBITS (BITS (16, 19), (x), (y)) & (m), \ + wRBITS (BITS ( 0, 3), (x), (y)) & (m), \ + & carry, & overflow) + + switch (BITS (22, 23)) + { + case Bqual: + for (i = 0; i < 8; i++) + { + switch (BITS (20, 21)) + { + case NoSaturation: + s = ADDx ((i * 8), (i * 8) + 7, 0xff, AddS8); + satrv [BITIDX8 (i)] = 0; + r |= (s & 0xff) << (i * 8); + SIMD8_SET (psr, NBIT8 (s), SIMD_NBIT, i); + SIMD8_SET (psr, ZBIT8 (s), SIMD_ZBIT, i); + SIMD8_SET (psr, carry, SIMD_CBIT, i); + SIMD8_SET (psr, overflow, SIMD_VBIT, i); + break; + + case UnsignedSaturation: + s = ADDx ((i * 8), (i * 8) + 7, 0xff, AddU8); + x = IwmmxtSaturateU8 (s, satrv + BITIDX8 (i)); + r |= (x & 0xff) << (i * 8); + SIMD8_SET (psr, NBIT8 (x), SIMD_NBIT, i); + SIMD8_SET (psr, ZBIT8 (x), SIMD_ZBIT, i); + if (! satrv [BITIDX8 (i)]) + { + SIMD8_SET (psr, carry, SIMD_CBIT, i); + SIMD8_SET (psr, overflow, SIMD_VBIT, i); + } + break; + + case SignedSaturation: + s = ADDx ((i * 8), (i * 8) + 7, 0xff, AddS8); + x = IwmmxtSaturateS8 (s, satrv + BITIDX8 (i)); + r |= (x & 0xff) << (i * 8); + SIMD8_SET (psr, NBIT8 (x), SIMD_NBIT, i); + SIMD8_SET (psr, ZBIT8 (x), SIMD_ZBIT, i); + if (! satrv [BITIDX8 (i)]) + { + SIMD8_SET (psr, carry, SIMD_CBIT, i); + SIMD8_SET (psr, overflow, SIMD_VBIT, i); + } + break; + + default: + ARMul_UndefInstr (state, instr); + return ARMul_DONE; + } + } + break; + + case Hqual: + satrv[0] = satrv[2] = satrv[4] = satrv[6] = 0; + + for (i = 0; i < 4; i++) + { + switch (BITS (20, 21)) + { + case NoSaturation: + s = ADDx ((i * 16), (i * 16) + 15, 0xffff, AddS16); + satrv [BITIDX16 (i)] = 0; + r |= (s & 0xffff) << (i * 16); + SIMD16_SET (psr, NBIT16 (s), SIMD_NBIT, i); + SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i); + SIMD16_SET (psr, carry, SIMD_CBIT, i); + SIMD16_SET (psr, overflow, SIMD_VBIT, i); + break; + + case UnsignedSaturation: + s = ADDx ((i * 16), (i * 16) + 15, 0xffff, AddU16); + x = IwmmxtSaturateU16 (s, satrv + BITIDX16 (i)); + r |= (x & 0xffff) << (i * 16); + SIMD16_SET (psr, NBIT16 (x), SIMD_NBIT, i); + SIMD16_SET (psr, ZBIT16 (x), SIMD_ZBIT, i); + if (! satrv [BITIDX16 (i)]) + { + SIMD16_SET (psr, carry, SIMD_CBIT, i); + SIMD16_SET (psr, overflow, SIMD_VBIT, i); + } + break; + + case SignedSaturation: + s = ADDx ((i * 16), (i * 16) + 15, 0xffff, AddS16); + x = IwmmxtSaturateS16 (s, satrv + BITIDX16 (i)); + r |= (x & 0xffff) << (i * 16); + SIMD16_SET (psr, NBIT16 (x), SIMD_NBIT, i); + SIMD16_SET (psr, ZBIT16 (x), SIMD_ZBIT, i); + if (! satrv [BITIDX16 (i)]) + { + SIMD16_SET (psr, carry, SIMD_CBIT, i); + SIMD16_SET (psr, overflow, SIMD_VBIT, i); + } + break; + + default: + ARMul_UndefInstr (state, instr); + return ARMul_DONE; + } + } + break; + + case Wqual: + satrv[0] = satrv[1] = satrv[2] = satrv[4] = satrv[5] = satrv[6] = 0; + + for (i = 0; i < 2; i++) + { + switch (BITS (20, 21)) + { + case NoSaturation: + s = ADDx ((i * 32), (i * 32) + 31, 0xffffffff, AddS32); + satrv [BITIDX32 (i)] = 0; + r |= (s & 0xffffffff) << (i * 32); + SIMD32_SET (psr, NBIT32 (s), SIMD_NBIT, i); + SIMD32_SET (psr, ZBIT32 (s), SIMD_ZBIT, i); + SIMD32_SET (psr, carry, SIMD_CBIT, i); + SIMD32_SET (psr, overflow, SIMD_VBIT, i); + break; + + case UnsignedSaturation: + s = ADDx ((i * 32), (i * 32) + 31, 0xffffffff, AddU32); + x = IwmmxtSaturateU32 (s, satrv + BITIDX32 (i)); + r |= (x & 0xffffffff) << (i * 32); + SIMD32_SET (psr, NBIT32 (x), SIMD_NBIT, i); + SIMD32_SET (psr, ZBIT32 (x), SIMD_ZBIT, i); + if (! satrv [BITIDX32 (i)]) + { + SIMD32_SET (psr, carry, SIMD_CBIT, i); + SIMD32_SET (psr, overflow, SIMD_VBIT, i); + } + break; + + case SignedSaturation: + s = ADDx ((i * 32), (i * 32) + 31, 0xffffffff, AddS32); + x = IwmmxtSaturateS32 (s, satrv + BITIDX32 (i)); + r |= (x & 0xffffffff) << (i * 32); + SIMD32_SET (psr, NBIT32 (x), SIMD_NBIT, i); + SIMD32_SET (psr, ZBIT32 (x), SIMD_ZBIT, i); + if (! satrv [BITIDX32 (i)]) + { + SIMD32_SET (psr, carry, SIMD_CBIT, i); + SIMD32_SET (psr, overflow, SIMD_VBIT, i); + } + break; + + default: + ARMul_UndefInstr (state, instr); + return ARMul_DONE; + } + } + break; + + default: + ARMul_UndefInstr (state, instr); + return ARMul_DONE; + } + + wC [wCASF] = psr; + wR [BITS (12, 15)] = r; + wC [wCon] |= (WCON_MUP | WCON_CUP); + + SET_wCSSFvec (satrv); + +#undef ADDx + + return ARMul_DONE; +} + +static int +WALIGNI (ARMword instr) +{ + int shift = BITS (20, 22) * 8; + + if ((read_cp15_reg (15, 0, 1) & 3) != 3) + return ARMul_CANT; + +#ifdef DEBUG + fprintf (stderr, "waligni\n"); +#endif + + if (shift) + wR [BITS (12, 15)] = + wRBITS (BITS (16, 19), shift, 63) + | (wRBITS (BITS (0, 3), 0, shift) << ((64 - shift))); + else + wR [BITS (12, 15)] = wR [BITS (16, 19)]; + + wC [wCon] |= WCON_MUP; + return ARMul_DONE; +} + +static int +WALIGNR (ARMul_State * state, ARMword instr) +{ + int shift = (wC [BITS (20, 21) + 8] & 0x7) * 8; + + if ((read_cp15_reg (15, 0, 1) & 3) != 3) + return ARMul_CANT; + +#ifdef DEBUG + fprintf (stderr, "walignr\n"); +#endif + + if (shift) + wR [BITS (12, 15)] = + wRBITS (BITS (16, 19), shift, 63) + | (wRBITS (BITS (0, 3), 0, shift) << ((64 - shift))); + else + wR [BITS (12, 15)] = wR [BITS (16, 19)]; + + wC [wCon] |= WCON_MUP; + return ARMul_DONE; +} + +static int +WAND (ARMword instr) +{ + ARMdword result; + ARMword psr = 0; + + if ((read_cp15_reg (15, 0, 1) & 3) != 3) + return ARMul_CANT; + +#ifdef DEBUG + fprintf (stderr, "wand\n"); +#endif + + result = wR [BITS (16, 19)] & wR [BITS (0, 3)]; + wR [BITS (12, 15)] = result; + + SIMD64_SET (psr, (result == 0), SIMD_ZBIT); + SIMD64_SET (psr, (result & (1ULL << 63)), SIMD_NBIT); + + wC [wCASF] = psr; + wC [wCon] |= (WCON_CUP | WCON_MUP); + + return ARMul_DONE; +} + +static int +WANDN (ARMword instr) +{ + ARMdword result; + ARMword psr = 0; + + if ((read_cp15_reg (15, 0, 1) & 3) != 3) + return ARMul_CANT; + +#ifdef DEBUG + fprintf (stderr, "wandn\n"); +#endif + + result = wR [BITS (16, 19)] & ~ wR [BITS (0, 3)]; + wR [BITS (12, 15)] = result; + + SIMD64_SET (psr, (result == 0), SIMD_ZBIT); + SIMD64_SET (psr, (result & (1ULL << 63)), SIMD_NBIT); + + wC [wCASF] = psr; + wC [wCon] |= (WCON_CUP | WCON_MUP); + + return ARMul_DONE; +} + +static int +WAVG2 (ARMword instr) +{ + ARMdword r = 0; + ARMword psr = 0; + ARMdword s; + int i; + int round = BIT (20) ? 1 : 0; + + if ((read_cp15_reg (15, 0, 1) & 3) != 3) + return ARMul_CANT; + +#ifdef DEBUG + fprintf (stderr, "wavg2\n"); +#endif + +#define AVG2x(x, y, m) (((wRBITS (BITS (16, 19), (x), (y)) & (m)) \ + + (wRBITS (BITS ( 0, 3), (x), (y)) & (m)) \ + + round) / 2) + + if (BIT (22)) + { + for (i = 0; i < 4; i++) + { + s = AVG2x ((i * 16), (i * 16) + 15, 0xffff) & 0xffff; + SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i); + r |= s << (i * 16); + } + } + else + { + for (i = 0; i < 8; i++) + { + s = AVG2x ((i * 8), (i * 8) + 7, 0xff) & 0xff; + SIMD8_SET (psr, ZBIT8 (s), SIMD_ZBIT, i); + r |= s << (i * 8); + } + } + + wR [BITS (12, 15)] = r; + wC [wCASF] = psr; + wC [wCon] |= (WCON_CUP | WCON_MUP); + + return ARMul_DONE; +} + +static int +WCMPEQ (ARMul_State * state, ARMword instr) +{ + ARMdword r = 0; + ARMword psr = 0; + ARMdword s; + int i; + + if ((read_cp15_reg (15, 0, 1) & 3) != 3) + return ARMul_CANT; + +#ifdef DEBUG + fprintf (stderr, "wcmpeq\n"); +#endif + + switch (BITS (22, 23)) + { + case Bqual: + for (i = 0; i < 8; i++) + { + s = wRBYTE (BITS (16, 19), i) == wRBYTE (BITS (0, 3), i) ? 0xff : 0; + r |= s << (i * 8); + SIMD8_SET (psr, NBIT8 (s), SIMD_NBIT, i); + SIMD8_SET (psr, ZBIT8 (s), SIMD_ZBIT, i); + } + break; + + case Hqual: + for (i = 0; i < 4; i++) + { + s = wRHALF (BITS (16, 19), i) == wRHALF (BITS (0, 3), i) ? 0xffff : 0; + r |= s << (i * 16); + SIMD16_SET (psr, NBIT16 (s), SIMD_NBIT, i); + SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i); + } + break; + + case Wqual: + for (i = 0; i < 2; i++) + { + s = wRWORD (BITS (16, 19), i) == wRWORD (BITS (0, 3), i) ? 0xffffffff : 0; + r |= s << (i * 32); + SIMD32_SET (psr, NBIT32 (s), SIMD_NBIT, i); + SIMD32_SET (psr, ZBIT32 (s), SIMD_ZBIT, i); + } + break; + + default: + ARMul_UndefInstr (state, instr); + return ARMul_DONE; + } + + wC [wCASF] = psr; + wR [BITS (12, 15)] = r; + wC [wCon] |= (WCON_CUP | WCON_MUP); + + return ARMul_DONE; +} + +static int +WCMPGT (ARMul_State * state, ARMword instr) +{ + ARMdword r = 0; + ARMword psr = 0; + ARMdword s; + int i; + + if ((read_cp15_reg (15, 0, 1) & 3) != 3) + return ARMul_CANT; + +#ifdef DEBUG + fprintf (stderr, "wcmpgt\n"); +#endif + + switch (BITS (22, 23)) + { + case Bqual: + if (BIT (21)) + { + /* Use a signed comparison. */ + for (i = 0; i < 8; i++) + { + signed char a, b; + + a = wRBYTE (BITS (16, 19), i); + b = wRBYTE (BITS (0, 3), i); + + s = (a > b) ? 0xff : 0; + r |= s << (i * 8); + SIMD8_SET (psr, NBIT8 (s), SIMD_NBIT, i); + SIMD8_SET (psr, ZBIT8 (s), SIMD_ZBIT, i); + } + } + else + { + for (i = 0; i < 8; i++) + { + s = (wRBYTE (BITS (16, 19), i) > wRBYTE (BITS (0, 3), i)) + ? 0xff : 0; + r |= s << (i * 8); + SIMD8_SET (psr, NBIT8 (s), SIMD_NBIT, i); + SIMD8_SET (psr, ZBIT8 (s), SIMD_ZBIT, i); + } + } + break; + + case Hqual: + if (BIT (21)) + { + for (i = 0; i < 4; i++) + { + signed int a, b; + + a = wRHALF (BITS (16, 19), i); + a = EXTEND16 (a); + + b = wRHALF (BITS (0, 3), i); + b = EXTEND16 (b); + + s = (a > b) ? 0xffff : 0; + r |= s << (i * 16); + SIMD16_SET (psr, NBIT16 (s), SIMD_NBIT, i); + SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i); + } + } + else + { + for (i = 0; i < 4; i++) + { + s = (wRHALF (BITS (16, 19), i) > wRHALF (BITS (0, 3), i)) + ? 0xffff : 0; + r |= s << (i * 16); + SIMD16_SET (psr, NBIT16 (s), SIMD_NBIT, i); + SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i); + } + } + break; + + case Wqual: + if (BIT (21)) + { + for (i = 0; i < 2; i++) + { + signed long a, b; + + a = wRWORD (BITS (16, 19), i); + b = wRWORD (BITS (0, 3), i); + + s = (a > b) ? 0xffffffff : 0; + r |= s << (i * 32); + SIMD32_SET (psr, NBIT32 (s), SIMD_NBIT, i); + SIMD32_SET (psr, ZBIT32 (s), SIMD_ZBIT, i); + } + } + else + { + for (i = 0; i < 2; i++) + { + s = (wRWORD (BITS (16, 19), i) > wRWORD (BITS (0, 3), i)) + ? 0xffffffff : 0; + r |= s << (i * 32); + SIMD32_SET (psr, NBIT32 (s), SIMD_NBIT, i); + SIMD32_SET (psr, ZBIT32 (s), SIMD_ZBIT, i); + } + } + break; + + default: + ARMul_UndefInstr (state, instr); + return ARMul_DONE; + } + + wC [wCASF] = psr; + wR [BITS (12, 15)] = r; + wC [wCon] |= (WCON_CUP | WCON_MUP); + + return ARMul_DONE; +} + +static ARMword +Compute_Iwmmxt_Address (ARMul_State * state, ARMword instr, int * pFailed) +{ + ARMword Rn; + ARMword addr; + ARMword offset; + ARMword multiplier; + + * pFailed = 0; + Rn = BITS (16, 19); + addr = state->Reg [Rn]; + offset = BITS (0, 7); + multiplier = BIT (8) ? 4 : 1; + + if (BIT (24)) /* P */ + { + /* Pre Indexed Addressing. */ + if (BIT (23)) + addr += offset * multiplier; + else + addr -= offset * multiplier; + + /* Immediate Pre-Indexed. */ + if (BIT (21)) /* W */ + { + if (Rn == 15) + { + /* Writeback into R15 is UNPREDICTABLE. */ +#ifdef DEBUG + fprintf (stderr, "iWMMXt: writeback into r15\n"); +#endif + * pFailed = 1; + } + else + state->Reg [Rn] = addr; + } + } + else + { + /* Post Indexed Addressing. */ + if (BIT (21)) /* W */ + { + /* Handle the write back of the final address. */ + if (Rn == 15) + { + /* Writeback into R15 is UNPREDICTABLE. */ +#ifdef DEBUG + fprintf (stderr, "iWMMXt: writeback into r15\n"); +#endif + * pFailed = 1; + } + else + { + ARMword increment; + + if (BIT (23)) + increment = offset * multiplier; + else + increment = - (offset * multiplier); + + state->Reg [Rn] = addr + increment; + } + } + else + { + /* P == 0, W == 0, U == 0 is UNPREDICTABLE. */ + if (BIT (23) == 0) + { +#ifdef DEBUG + fprintf (stderr, "iWMMXt: undefined addressing mode\n"); +#endif + * pFailed = 1; + } + } + } + + return addr; +} + +static ARMdword +Iwmmxt_Load_Double_Word (ARMul_State * state, ARMword address) +{ + ARMdword value; + + /* The address must be aligned on a 8 byte boundary. */ + if (address & 0x7) + { + fprintf (stderr, "iWMMXt: At addr 0x%x: Unaligned double word load from 0x%x\n", + (state->Reg[15] - 8) & ~0x3, address); +#ifdef DEBUG +#endif + /* No need to check for alignment traps. An unaligned + double word load with alignment trapping disabled is + UNPREDICTABLE. */ + ARMul_Abort (state, ARMul_DataAbortV); + } + + /* Load the words. */ + if (! state->bigendSig) + { + value = ARMul_LoadWordN (state, address + 4); + value <<= 32; + value |= ARMul_LoadWordN (state, address); + } + else + { + value = ARMul_LoadWordN (state, address); + value <<= 32; + value |= ARMul_LoadWordN (state, address + 4); + } + + /* Check for data aborts. */ + if (state->Aborted) + ARMul_Abort (state, ARMul_DataAbortV); + else + ARMul_Icycles (state, 2, 0L); + + return value; +} + +static ARMword +Iwmmxt_Load_Word (ARMul_State * state, ARMword address) +{ + ARMword value; + + /* Check for a misaligned address. */ + if (address & 3) + { + if ((read_cp15_reg (1, 0, 0) & ARMul_CP15_R1_ALIGN)) + ARMul_Abort (state, ARMul_DataAbortV); + else + address &= ~ 3; + } + + value = ARMul_LoadWordN (state, address); + + if (state->Aborted) + ARMul_Abort (state, ARMul_DataAbortV); + else + ARMul_Icycles (state, 1, 0L); + + return value; +} + +static ARMword +Iwmmxt_Load_Half_Word (ARMul_State * state, ARMword address) +{ + ARMword value; + + /* Check for a misaligned address. */ + if (address & 1) + { + if ((read_cp15_reg (1, 0, 0) & ARMul_CP15_R1_ALIGN)) + ARMul_Abort (state, ARMul_DataAbortV); + else + address &= ~ 1; + } + + value = ARMul_LoadHalfWord (state, address); + + if (state->Aborted) + ARMul_Abort (state, ARMul_DataAbortV); + else + ARMul_Icycles (state, 1, 0L); + + return value; +} + +static ARMword +Iwmmxt_Load_Byte (ARMul_State * state, ARMword address) +{ + ARMword value; + + value = ARMul_LoadByte (state, address); + + if (state->Aborted) + ARMul_Abort (state, ARMul_DataAbortV); + else + ARMul_Icycles (state, 1, 0L); + + return value; +} + +static void +Iwmmxt_Store_Double_Word (ARMul_State * state, ARMword address, ARMdword value) +{ + /* The address must be aligned on a 8 byte boundary. */ + if (address & 0x7) + { + fprintf (stderr, "iWMMXt: At addr 0x%x: Unaligned double word store to 0x%x\n", + (state->Reg[15] - 8) & ~0x3, address); +#ifdef DEBUG +#endif + /* No need to check for alignment traps. An unaligned + double word store with alignment trapping disabled is + UNPREDICTABLE. */ + ARMul_Abort (state, ARMul_DataAbortV); + } + + /* Store the words. */ + if (! state->bigendSig) + { + ARMul_StoreWordN (state, address, value); + ARMul_StoreWordN (state, address + 4, value >> 32); + } + else + { + ARMul_StoreWordN (state, address + 4, value); + ARMul_StoreWordN (state, address, value >> 32); + } + + /* Check for data aborts. */ + if (state->Aborted) + ARMul_Abort (state, ARMul_DataAbortV); + else + ARMul_Icycles (state, 2, 0L); +} + +static void +Iwmmxt_Store_Word (ARMul_State * state, ARMword address, ARMword value) +{ + /* Check for a misaligned address. */ + if (address & 3) + { + if ((read_cp15_reg (1, 0, 0) & ARMul_CP15_R1_ALIGN)) + ARMul_Abort (state, ARMul_DataAbortV); + else + address &= ~ 3; + } + + ARMul_StoreWordN (state, address, value); + + if (state->Aborted) + ARMul_Abort (state, ARMul_DataAbortV); +} + +static void +Iwmmxt_Store_Half_Word (ARMul_State * state, ARMword address, ARMword value) +{ + /* Check for a misaligned address. */ + if (address & 1) + { + if ((read_cp15_reg (1, 0, 0) & ARMul_CP15_R1_ALIGN)) + ARMul_Abort (state, ARMul_DataAbortV); + else + address &= ~ 1; + } + + ARMul_StoreHalfWord (state, address, value); + + if (state->Aborted) + ARMul_Abort (state, ARMul_DataAbortV); +} + +static void +Iwmmxt_Store_Byte (ARMul_State * state, ARMword address, ARMword value) +{ + ARMul_StoreByte (state, address, value); + + if (state->Aborted) + ARMul_Abort (state, ARMul_DataAbortV); +} + +static int +WLDR (ARMul_State * state, ARMword instr) +{ + ARMword address; + int failed; + + if ((read_cp15_reg (15, 0, 1) & 3) != 3) + return ARMul_CANT; + +#ifdef DEBUG + fprintf (stderr, "wldr\n"); +#endif + + address = Compute_Iwmmxt_Address (state, instr, & failed); + if (failed) + return ARMul_CANT; + + if (BITS (28, 31) == 0xf) + { + /* WLDRW wCx */ + wC [BITS (12, 15)] = Iwmmxt_Load_Word (state, address); + } + else if (BIT (8) == 0) + { + if (BIT (22) == 0) + /* WLDRB */ + wR [BITS (12, 15)] = Iwmmxt_Load_Byte (state, address); + else + /* WLDRH */ + wR [BITS (12, 15)] = Iwmmxt_Load_Half_Word (state, address); + } + else + { + if (BIT (22) == 0) + /* WLDRW wRd */ + wR [BITS (12, 15)] = Iwmmxt_Load_Word (state, address); + else + /* WLDRD */ + wR [BITS (12, 15)] = Iwmmxt_Load_Double_Word (state, address); + } + + wC [wCon] |= WCON_MUP; + + return ARMul_DONE; +} + +static int +WMAC (ARMword instr) +{ + int i; + ARMdword t = 0; + ARMword a, b; + + if ((read_cp15_reg (15, 0, 1) & 3) != 3) + return ARMul_CANT; + +#ifdef DEBUG + fprintf (stderr, "wmac\n"); +#endif + + for (i = 0; i < 4; i++) + { + if (BIT (21)) + { + /* Signed. */ + signed long s; + + a = wRHALF (BITS (16, 19), i); + a = EXTEND16 (a); + + b = wRHALF (BITS (0, 3), i); + b = EXTEND16 (b); + + s = (signed long) a * (signed long) b; + + (signed long long) t += s; + } + else + { + /* Unsigned. */ + a = wRHALF (BITS (16, 19), i); + b = wRHALF (BITS ( 0, 3), i); + + t += a * b; + } + } + + if (BIT (20)) + wR [BITS (12, 15)] = 0; + + if (BIT (21)) /* Signed. */ + (signed long long) wR[BITS (12, 15)] += (signed long long) t; + else + wR [BITS (12, 15)] += t; + + wC [wCon] |= WCON_MUP; + + return ARMul_DONE; +} + +static int +WMADD (ARMword instr) +{ + ARMdword r = 0; + int i; + + if ((read_cp15_reg (15, 0, 1) & 3) != 3) + return ARMul_CANT; + +#ifdef DEBUG + fprintf (stderr, "wmadd\n"); +#endif + + for (i = 0; i < 2; i++) + { + ARMdword s1, s2; + + if (BIT (21)) /* Signed. */ + { + signed long a, b; + + a = wRHALF (BITS (16, 19), i * 2); + a = EXTEND16 (a); + + b = wRHALF (BITS (0, 3), i * 2); + b = EXTEND16 (b); + + (signed long) s1 = a * b; + + a = wRHALF (BITS (16, 19), i * 2 + 1); + a = EXTEND16 (a); + + b = wRHALF (BITS (0, 3), i * 2 + 1); + b = EXTEND16 (b); + + (signed long) s2 = a * b; + } + else /* Unsigned. */ + { + unsigned long a, b; + + a = wRHALF (BITS (16, 19), i * 2); + b = wRHALF (BITS ( 0, 3), i * 2); + + (unsigned long) s1 = a * b; + + a = wRHALF (BITS (16, 19), i * 2 + 1); + b = wRHALF (BITS ( 0, 3), i * 2 + 1); + + (signed long) s2 = a * b; + } + + r |= (ARMdword) ((s1 + s2) & 0xffffffff) << (i ? 32 : 0); + } + + wR [BITS (12, 15)] = r; + wC [wCon] |= WCON_MUP; + + return ARMul_DONE; +} + +static int +WMAX (ARMul_State * state, ARMword instr) +{ + ARMdword r = 0; + ARMdword s; + int i; + + if ((read_cp15_reg (15, 0, 1) & 3) != 3) + return ARMul_CANT; + +#ifdef DEBUG + fprintf (stderr, "wmax\n"); +#endif + + switch (BITS (22, 23)) + { + case Bqual: + for (i = 0; i < 8; i++) + if (BIT (21)) /* Signed. */ + { + int a, b; + + a = wRBYTE (BITS (16, 19), i); + a = EXTEND8 (a); + + b = wRBYTE (BITS (0, 3), i); + b = EXTEND8 (b); + + if (a > b) + s = a; + else + s = b; + + r |= (s & 0xff) << (i * 8); + } + else /* Unsigned. */ + { + unsigned int a, b; + + a = wRBYTE (BITS (16, 19), i); + b = wRBYTE (BITS (0, 3), i); + + if (a > b) + s = a; + else + s = b; + + r |= (s & 0xff) << (i * 8); + } + break; + + case Hqual: + for (i = 0; i < 4; i++) + if (BIT (21)) /* Signed. */ + { + int a, b; + + a = wRHALF (BITS (16, 19), i); + a = EXTEND16 (a); + + b = wRHALF (BITS (0, 3), i); + b = EXTEND16 (b); + + if (a > b) + s = a; + else + s = b; + + r |= (s & 0xffff) << (i * 16); + } + else /* Unsigned. */ + { + unsigned int a, b; + + a = wRHALF (BITS (16, 19), i); + b = wRHALF (BITS (0, 3), i); + + if (a > b) + s = a; + else + s = b; + + r |= (s & 0xffff) << (i * 16); + } + break; + + case Wqual: + for (i = 0; i < 2; i++) + if (BIT (21)) /* Signed. */ + { + int a, b; + + a = wRWORD (BITS (16, 19), i); + b = wRWORD (BITS (0, 3), i); + + if (a > b) + s = a; + else + s = b; + + r |= (s & 0xffffffff) << (i * 32); + } + else + { + unsigned int a, b; + + a = wRWORD (BITS (16, 19), i); + b = wRWORD (BITS (0, 3), i); + + if (a > b) + s = a; + else + s = b; + + r |= (s & 0xffffffff) << (i * 32); + } + break; + + default: + ARMul_UndefInstr (state, instr); + return ARMul_DONE; + } + + wR [BITS (12, 15)] = r; + wC [wCon] |= WCON_MUP; + + return ARMul_DONE; +} + +static int +WMIN (ARMul_State * state, ARMword instr) +{ + ARMdword r = 0; + ARMdword s; + int i; + + if ((read_cp15_reg (15, 0, 1) & 3) != 3) + return ARMul_CANT; + +#ifdef DEBUG + fprintf (stderr, "wmin\n"); +#endif + + switch (BITS (22, 23)) + { + case Bqual: + for (i = 0; i < 8; i++) + if (BIT (21)) /* Signed. */ + { + int a, b; + + a = wRBYTE (BITS (16, 19), i); + a = EXTEND8 (a); + + b = wRBYTE (BITS (0, 3), i); + b = EXTEND8 (b); + + if (a < b) + s = a; + else + s = b; + + r |= (s & 0xff) << (i * 8); + } + else /* Unsigned. */ + { + unsigned int a, b; + + a = wRBYTE (BITS (16, 19), i); + b = wRBYTE (BITS (0, 3), i); + + if (a < b) + s = a; + else + s = b; + + r |= (s & 0xff) << (i * 8); + } + break; + + case Hqual: + for (i = 0; i < 4; i++) + if (BIT (21)) /* Signed. */ + { + int a, b; + + a = wRHALF (BITS (16, 19), i); + a = EXTEND16 (a); + + b = wRHALF (BITS (0, 3), i); + b = EXTEND16 (b); + + if (a < b) + s = a; + else + s = b; + + r |= (s & 0xffff) << (i * 16); + } + else + { + /* Unsigned. */ + unsigned int a, b; + + a = wRHALF (BITS (16, 19), i); + b = wRHALF (BITS ( 0, 3), i); + + if (a < b) + s = a; + else + s = b; + + r |= (s & 0xffff) << (i * 16); + } + break; + + case Wqual: + for (i = 0; i < 2; i++) + if (BIT (21)) /* Signed. */ + { + int a, b; + + a = wRWORD (BITS (16, 19), i); + b = wRWORD (BITS ( 0, 3), i); + + if (a < b) + s = a; + else + s = b; + + r |= (s & 0xffffffff) << (i * 32); + } + else + { + unsigned int a, b; + + a = wRWORD (BITS (16, 19), i); + b = wRWORD (BITS (0, 3), i); + + if (a < b) + s = a; + else + s = b; + + r |= (s & 0xffffffff) << (i * 32); + } + break; + + default: + ARMul_UndefInstr (state, instr); + return ARMul_DONE; + } + + wR [BITS (12, 15)] = r; + wC [wCon] |= WCON_MUP; + + return ARMul_DONE; +} + +static int +WMUL (ARMword instr) +{ + ARMdword r = 0; + ARMdword s; + int i; + + if ((read_cp15_reg (15, 0, 1) & 3) != 3) + return ARMul_CANT; + +#ifdef DEBUG + fprintf (stderr, "wmul\n"); +#endif + + for (i = 0; i < 4; i++) + if (BIT (21)) /* Signed. */ + { + long a, b; + + a = wRHALF (BITS (16, 19), i); + a = EXTEND16 (a); + + b = wRHALF (BITS (0, 3), i); + b = EXTEND16 (b); + + s = a * b; + + if (BIT (20)) + r |= ((s >> 16) & 0xffff) << (i * 16); + else + r |= (s & 0xffff) << (i * 16); + } + else /* Unsigned. */ + { + unsigned long a, b; + + a = wRHALF (BITS (16, 19), i); + b = wRHALF (BITS (0, 3), i); + + s = a * b; + + if (BIT (20)) + r |= ((s >> 16) & 0xffff) << (i * 16); + else + r |= (s & 0xffff) << (i * 16); + } + + wR [BITS (12, 15)] = r; + wC [wCon] |= WCON_MUP; + + return ARMul_DONE; +} + +static int +WOR (ARMword instr) +{ + ARMword psr = 0; + ARMdword result; + + if ((read_cp15_reg (15, 0, 1) & 3) != 3) + return ARMul_CANT; + +#ifdef DEBUG + fprintf (stderr, "wor\n"); +#endif + + result = wR [BITS (16, 19)] | wR [BITS (0, 3)]; + wR [BITS (12, 15)] = result; + + SIMD64_SET (psr, (result == 0), SIMD_ZBIT); + SIMD64_SET (psr, (result & (1ULL << 63)), SIMD_NBIT); + + wC [wCASF] = psr; + wC [wCon] |= (WCON_CUP | WCON_MUP); + + return ARMul_DONE; +} + +static int +WPACK (ARMul_State * state, ARMword instr) +{ + ARMdword r = 0; + ARMword psr = 0; + ARMdword x; + ARMdword s; + int i; + int satrv[8]; + + if ((read_cp15_reg (15, 0, 1) & 3) != 3) + return ARMul_CANT; + +#ifdef DEBUG + fprintf (stderr, "wpack\n"); +#endif + + switch (BITS (22, 23)) + { + case Hqual: + for (i = 0; i < 8; i++) + { + x = wRHALF (i < 4 ? BITS (16, 19) : BITS (0, 3), i & 3); + + switch (BITS (20, 21)) + { + case UnsignedSaturation: + s = IwmmxtSaturateU8 (x, satrv + BITIDX8 (i)); + break; + + case SignedSaturation: + s = IwmmxtSaturateS8 (x, satrv + BITIDX8 (i)); + break; + + default: + ARMul_UndefInstr (state, instr); + return ARMul_DONE; + } + + r |= (s & 0xff) << (i * 8); + SIMD8_SET (psr, NBIT8 (s), SIMD_NBIT, i); + SIMD8_SET (psr, ZBIT8 (s), SIMD_ZBIT, i); + } + break; + + case Wqual: + satrv[0] = satrv[2] = satrv[4] = satrv[6] = 0; + + for (i = 0; i < 4; i++) + { + x = wRWORD (i < 2 ? BITS (16, 19) : BITS (0, 3), i & 1); + + switch (BITS (20, 21)) + { + case UnsignedSaturation: + s = IwmmxtSaturateU16 (x, satrv + BITIDX16 (i)); + break; + + case SignedSaturation: + s = IwmmxtSaturateS16 (x, satrv + BITIDX16 (i)); + break; + + default: + ARMul_UndefInstr (state, instr); + return ARMul_DONE; + } + + r |= (s & 0xffff) << (i * 16); + SIMD16_SET (psr, NBIT16 (s), SIMD_NBIT, i); + SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i); + } + break; + + case Dqual: + satrv[0] = satrv[1] = satrv[2] = satrv[4] = satrv[5] = satrv[6] = 0; + + for (i = 0; i < 2; i++) + { + x = wR [i ? BITS (0, 3) : BITS (16, 19)]; + + switch (BITS (20, 21)) + { + case UnsignedSaturation: + s = IwmmxtSaturateU32 (x, satrv + BITIDX32 (i)); + break; + + case SignedSaturation: + s = IwmmxtSaturateS32 (x, satrv + BITIDX32 (i)); + break; + + default: + ARMul_UndefInstr (state, instr); + return ARMul_DONE; + } + + r |= (s & 0xffffffff) << (i * 32); + SIMD32_SET (psr, NBIT32 (s), SIMD_NBIT, i); + SIMD32_SET (psr, ZBIT32 (s), SIMD_ZBIT, i); + } + break; + + default: + ARMul_UndefInstr (state, instr); + return ARMul_DONE; + } + + wC [wCASF] = psr; + wR [BITS (12, 15)] = r; + SET_wCSSFvec (satrv); + wC [wCon] |= (WCON_CUP | WCON_MUP); + + return ARMul_DONE; +} + +static int +WROR (ARMul_State * state, ARMword instr) +{ + ARMdword r = 0; + ARMdword s; + ARMword psr = 0; + int i; + int shift; + + if ((read_cp15_reg (15, 0, 1) & 3) != 3) + return ARMul_CANT; + +#ifdef DEBUG + fprintf (stderr, "wror\n"); +#endif + + DECODE_G_BIT (state, instr, shift); + + switch (BITS (22, 23)) + { + case Hqual: + shift &= 0xf; + for (i = 0; i < 4; i++) + { + s = ((wRHALF (BITS (16, 19), i) & 0xffff) << (16 - shift)) + | ((wRHALF (BITS (16, 19), i) & 0xffff) >> shift); + r |= (s & 0xffff) << (i * 16); + SIMD16_SET (psr, NBIT16 (s), SIMD_NBIT, i); + SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i); + } + break; + + case Wqual: + shift &= 0x1f; + for (i = 0; i < 2; i++) + { + s = ((wRWORD (BITS (16, 19), i) & 0xffffffff) << (32 - shift)) + | ((wRWORD (BITS (16, 19), i) & 0xffffffff) >> shift); + r |= (s & 0xffffffff) << (i * 32); + SIMD32_SET (psr, NBIT32 (s), SIMD_NBIT, i); + SIMD32_SET (psr, ZBIT32 (s), SIMD_ZBIT, i); + } + break; + + case Dqual: + shift &= 0x3f; + r = (wR [BITS (16, 19)] >> shift) + | (wR [BITS (16, 19)] << (64 - shift)); + + SIMD64_SET (psr, NBIT64 (r), SIMD_NBIT); + SIMD64_SET (psr, ZBIT64 (r), SIMD_ZBIT); + break; + + default: + ARMul_UndefInstr (state, instr); + return ARMul_DONE; + } + + wC [wCASF] = psr; + wR [BITS (12, 15)] = r; + wC [wCon] |= (WCON_CUP | WCON_MUP); + + return ARMul_DONE; +} + +static int +WSAD (ARMword instr) +{ + ARMdword r; + int s; + int i; + + if ((read_cp15_reg (15, 0, 1) & 3) != 3) + return ARMul_CANT; + +#ifdef DEBUG + fprintf (stderr, "wsad\n"); +#endif + + /* Z bit. */ + r = BIT (20) ? 0 : (wR [BITS (12, 15)] & 0xffffffff); + + if (BIT (22)) + /* Half. */ + for (i = 0; i < 4; i++) + { + s = (wRHALF (BITS (16, 19), i) - wRHALF (BITS (0, 3), i)); + r += abs (s); + } + else + /* Byte. */ + for (i = 0; i < 8; i++) + { + s = (wRBYTE (BITS (16, 19), i) - wRBYTE (BITS (0, 3), i)); + r += abs (s); + } + + wR [BITS (12, 15)] = r; + wC [wCon] |= WCON_MUP; + + return ARMul_DONE; +} + +static int +WSHUFH (ARMword instr) +{ + ARMdword r = 0; + ARMword psr = 0; + ARMdword s; + int i; + int imm8; + + if ((read_cp15_reg (15, 0, 1) & 3) != 3) + return ARMul_CANT; + +#ifdef DEBUG + fprintf (stderr, "wshufh\n"); +#endif + + imm8 = (BITS (20, 23) << 4) | BITS (0, 3); + + for (i = 0; i < 4; i++) + { + s = wRHALF (BITS (16, 19), ((imm8 >> (i * 2) & 3)) & 0xff); + r |= (s & 0xffff) << (i * 16); + SIMD16_SET (psr, NBIT16 (s), SIMD_NBIT, i); + SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i); + } + + wC [wCASF] = psr; + wR [BITS (12, 15)] = r; + wC [wCon] |= (WCON_CUP | WCON_MUP); + + return ARMul_DONE; +} + +static int +WSLL (ARMul_State * state, ARMword instr) +{ + ARMdword r = 0; + ARMdword s; + ARMword psr = 0; + int i; + unsigned shift; + + if ((read_cp15_reg (15, 0, 1) & 3) != 3) + return ARMul_CANT; + +#ifdef DEBUG + fprintf (stderr, "wsll\n"); +#endif + + DECODE_G_BIT (state, instr, shift); + + switch (BITS (22, 23)) + { + case Hqual: + for (i = 0; i < 4; i++) + { + if (shift > 15) + s = 0; + else + s = ((wRHALF (BITS (16, 19), i) & 0xffff) << shift); + r |= (s & 0xffff) << (i * 16); + SIMD16_SET (psr, NBIT16 (s), SIMD_NBIT, i); + SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i); + } + break; + + case Wqual: + for (i = 0; i < 2; i++) + { + if (shift > 31) + s = 0; + else + s = ((wRWORD (BITS (16, 19), i) & 0xffffffff) << shift); + r |= (s & 0xffffffff) << (i * 32); + SIMD32_SET (psr, NBIT32 (s), SIMD_NBIT, i); + SIMD32_SET (psr, ZBIT32 (s), SIMD_ZBIT, i); + } + break; + + case Dqual: + if (shift > 63) + r = 0; + else + r = ((wR[BITS (16, 19)] & 0xffffffffffffffff) << shift); + + SIMD64_SET (psr, NBIT64 (r), SIMD_NBIT); + SIMD64_SET (psr, ZBIT64 (r), SIMD_ZBIT); + break; + + default: + ARMul_UndefInstr (state, instr); + return ARMul_DONE; + } + + wC [wCASF] = psr; + wR [BITS (12, 15)] = r; + wC [wCon] |= (WCON_CUP | WCON_MUP); + + return ARMul_DONE; +} + +static int +WSRA (ARMul_State * state, ARMword instr) +{ + ARMdword r = 0; + ARMdword s; + ARMword psr = 0; + int i; + unsigned shift; + signed long t; + + if ((read_cp15_reg (15, 0, 1) & 3) != 3) + return ARMul_CANT; + +#ifdef DEBUG + fprintf (stderr, "wsra\n"); +#endif + + DECODE_G_BIT (state, instr, shift); + + switch (BITS (22, 23)) + { + case Hqual: + for (i = 0; i < 4; i++) + { + if (shift > 15) + t = (wRHALF (BITS (16, 19), i) & 0x8000) ? 0xffff : 0; + else + { + t = wRHALF (BITS (16, 19), i); + t = EXTEND16 (t); + t >>= shift; + } + + s = t; + r |= (s & 0xffff) << (i * 16); + SIMD16_SET (psr, NBIT16 (s), SIMD_NBIT, i); + SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i); + } + break; + + case Wqual: + for (i = 0; i < 2; i++) + { + if (shift > 31) + t = (wRWORD (BITS (16, 19), i) & 0x80000000) ? 0xffffffff : 0; + else + { + t = wRWORD (BITS (16, 19), i); + t >>= shift; + } + s = t; + r |= (s & 0xffffffff) << (i * 32); + SIMD32_SET (psr, NBIT32 (s), SIMD_NBIT, i); + SIMD32_SET (psr, ZBIT32 (s), SIMD_ZBIT, i); + } + break; + + case Dqual: + if (shift > 63) + r = (wR [BITS (16, 19)] & 0x8000000000000000) ? 0xffffffffffffffff : 0; + else + r = ((signed long long) (wR[BITS (16, 19)] & 0xffffffffffffffff) >> shift); + SIMD64_SET (psr, NBIT64 (r), SIMD_NBIT); + SIMD64_SET (psr, ZBIT64 (r), SIMD_ZBIT); + break; + + default: + ARMul_UndefInstr (state, instr); + return ARMul_DONE; + } + + wC [wCASF] = psr; + wR [BITS (12, 15)] = r; + wC [wCon] |= (WCON_CUP | WCON_MUP); + + return ARMul_DONE; +} + +static int +WSRL (ARMul_State * state, ARMword instr) +{ + ARMdword r = 0; + ARMdword s; + ARMword psr = 0; + int i; + unsigned int shift; + + if ((read_cp15_reg (15, 0, 1) & 3) != 3) + return ARMul_CANT; + +#ifdef DEBUG + fprintf (stderr, "wsrl\n"); +#endif + + DECODE_G_BIT (state, instr, shift); + + switch (BITS (22, 23)) + { + case Hqual: + for (i = 0; i < 4; i++) + { + if (shift > 15) + s = 0; + else + s = ((unsigned) (wRHALF (BITS (16, 19), i) & 0xffff) >> shift); + + r |= (s & 0xffff) << (i * 16); + SIMD16_SET (psr, NBIT16 (s), SIMD_NBIT, i); + SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i); + } + break; + + case Wqual: + for (i = 0; i < 2; i++) + { + if (shift > 31) + s = 0; + else + s = ((unsigned long) (wRWORD (BITS (16, 19), i) & 0xffffffff) >> shift); + + r |= (s & 0xffffffff) << (i * 32); + SIMD32_SET (psr, NBIT32 (s), SIMD_NBIT, i); + SIMD32_SET (psr, ZBIT32 (s), SIMD_ZBIT, i); + } + break; + + case Dqual: + if (shift > 63) + r = 0; + else + r = (wR [BITS (16, 19)] & 0xffffffffffffffff) >> shift; + + SIMD64_SET (psr, NBIT64 (r), SIMD_NBIT); + SIMD64_SET (psr, ZBIT64 (r), SIMD_ZBIT); + break; + + default: + ARMul_UndefInstr (state, instr); + return ARMul_DONE; + } + + wC [wCASF] = psr; + wR [BITS (12, 15)] = r; + wC [wCon] |= (WCON_CUP | WCON_MUP); + + return ARMul_DONE; +} + +static int +WSTR (ARMul_State * state, ARMword instr) +{ + ARMword address; + int failed; + + + if ((read_cp15_reg (15, 0, 1) & 3) != 3) + return ARMul_CANT; + +#ifdef DEBUG + fprintf (stderr, "wstr\n"); +#endif + + address = Compute_Iwmmxt_Address (state, instr, & failed); + if (failed) + return ARMul_CANT; + + if (BITS (28, 31) == 0xf) + { + /* WSTRW wCx */ + Iwmmxt_Store_Word (state, address, wC [BITS (12, 15)]); + } + else if (BIT (8) == 0) + { + if (BIT (22) == 0) + /* WSTRB */ + Iwmmxt_Store_Byte (state, address, wR [BITS (12, 15)]); + else + /* WSTRH */ + Iwmmxt_Store_Half_Word (state, address, wR [BITS (12, 15)]); + } + else + { + if (BIT (22) == 0) + /* WSTRW wRd */ + Iwmmxt_Store_Word (state, address, wR [BITS (12, 15)]); + else + /* WSTRD */ + Iwmmxt_Store_Double_Word (state, address, wR [BITS (12, 15)]); + } + + return ARMul_DONE; +} + +static int +WSUB (ARMul_State * state, ARMword instr) +{ + ARMdword r = 0; + ARMword psr = 0; + ARMdword x; + ARMdword s; + int i; + int carry; + int overflow; + int satrv[8]; + + if ((read_cp15_reg (15, 0, 1) & 3) != 3) + return ARMul_CANT; + +#ifdef DEBUG + fprintf (stderr, "wsub\n"); +#endif + +/* Subtract two numbers using the specified function, + leaving setting the carry bit as required. */ +#define SUBx(x, y, m, f) \ + (*f) (wRBITS (BITS (16, 19), (x), (y)) & (m), \ + wRBITS (BITS ( 0, 3), (x), (y)) & (m), & carry, & overflow) + + switch (BITS (22, 23)) + { + case Bqual: + for (i = 0; i < 8; i++) + { + switch (BITS (20, 21)) + { + case NoSaturation: + s = SUBx ((i * 8), (i * 8) + 7, 0xff, SubS8); + satrv [BITIDX8 (i)] = 0; + r |= (s & 0xff) << (i * 8); + SIMD8_SET (psr, NBIT8 (s), SIMD_NBIT, i); + SIMD8_SET (psr, ZBIT8 (s), SIMD_ZBIT, i); + SIMD8_SET (psr, carry, SIMD_CBIT, i); + SIMD8_SET (psr, overflow, SIMD_VBIT, i); + break; + + case UnsignedSaturation: + s = SUBx ((i * 8), (i * 8) + 7, 0xff, SubU8); + x = IwmmxtSaturateU8 (s, satrv + BITIDX8 (i)); + r |= (x & 0xff) << (i * 8); + SIMD8_SET (psr, NBIT8 (x), SIMD_NBIT, i); + SIMD8_SET (psr, ZBIT8 (x), SIMD_ZBIT, i); + if (! satrv [BITIDX8 (i)]) + { + SIMD8_SET (psr, carry, SIMD_CBIT, i); + SIMD8_SET (psr, overflow, SIMD_VBIT, i); + } + break; + + case SignedSaturation: + s = SUBx ((i * 8), (i * 8) + 7, 0xff, SubS8); + x = IwmmxtSaturateS8 (s, satrv + BITIDX8 (i)); + r |= (x & 0xff) << (i * 8); + SIMD8_SET (psr, NBIT8 (x), SIMD_NBIT, i); + SIMD8_SET (psr, ZBIT8 (x), SIMD_ZBIT, i); + if (! satrv [BITIDX8 (i)]) + { + SIMD8_SET (psr, carry, SIMD_CBIT, i); + SIMD8_SET (psr, overflow, SIMD_VBIT, i); + } + break; + + default: + ARMul_UndefInstr (state, instr); + return ARMul_DONE; + } + } + break; + + case Hqual: + satrv[0] = satrv[2] = satrv[4] = satrv[6] = 0; + + for (i = 0; i < 4; i++) + { + switch (BITS (20, 21)) + { + case NoSaturation: + s = SUBx ((i * 16), (i * 16) + 15, 0xffff, SubU16); + satrv [BITIDX16 (i)] = 0; + r |= (s & 0xffff) << (i * 16); + SIMD16_SET (psr, NBIT16 (s), SIMD_NBIT, i); + SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i); + SIMD16_SET (psr, carry, SIMD_CBIT, i); + SIMD16_SET (psr, overflow, SIMD_VBIT, i); + break; + + case UnsignedSaturation: + s = SUBx ((i * 16), (i * 16) + 15, 0xffff, SubU16); + x = IwmmxtSaturateU16 (s, satrv + BITIDX16 (i)); + r |= (x & 0xffff) << (i * 16); + SIMD16_SET (psr, NBIT16 (x & 0xffff), SIMD_NBIT, i); + SIMD16_SET (psr, ZBIT16 (x), SIMD_ZBIT, i); + if (! satrv [BITIDX16 (i)]) + { + SIMD16_SET (psr, carry, SIMD_CBIT, i); + SIMD16_SET (psr, overflow, SIMD_VBIT, i); + } + break; + + case SignedSaturation: + s = SUBx ((i * 16), (i * 16) + 15, 0xffff, SubS16); + x = IwmmxtSaturateS16 (s, satrv + BITIDX16 (i)); + r |= (x & 0xffff) << (i * 16); + SIMD16_SET (psr, NBIT16 (x), SIMD_NBIT, i); + SIMD16_SET (psr, ZBIT16 (x), SIMD_ZBIT, i); + if (! satrv [BITIDX16 (i)]) + { + SIMD16_SET (psr, carry, SIMD_CBIT, i); + SIMD16_SET (psr, overflow, SIMD_VBIT, i); + } + break; + + default: + ARMul_UndefInstr (state, instr); + return ARMul_DONE; + } + } + break; + + case Wqual: + satrv[0] = satrv[1] = satrv[2] = satrv[4] = satrv[5] = satrv[6] = 0; + + for (i = 0; i < 2; i++) + { + switch (BITS (20, 21)) + { + case NoSaturation: + s = SUBx ((i * 32), (i * 32) + 31, 0xffffffff, SubU32); + satrv[BITIDX32 (i)] = 0; + r |= (s & 0xffffffff) << (i * 32); + SIMD32_SET (psr, NBIT32 (s), SIMD_NBIT, i); + SIMD32_SET (psr, ZBIT32 (s), SIMD_ZBIT, i); + SIMD32_SET (psr, carry, SIMD_CBIT, i); + SIMD32_SET (psr, overflow, SIMD_VBIT, i); + break; + + case UnsignedSaturation: + s = SUBx ((i * 32), (i * 32) + 31, 0xffffffff, SubU32); + x = IwmmxtSaturateU32 (s, satrv + BITIDX32 (i)); + r |= (x & 0xffffffff) << (i * 32); + SIMD32_SET (psr, NBIT32 (x), SIMD_NBIT, i); + SIMD32_SET (psr, ZBIT32 (x), SIMD_ZBIT, i); + if (! satrv [BITIDX32 (i)]) + { + SIMD32_SET (psr, carry, SIMD_CBIT, i); + SIMD32_SET (psr, overflow, SIMD_VBIT, i); + } + break; + + case SignedSaturation: + s = SUBx ((i * 32), (i * 32) + 31, 0xffffffff, SubS32); + x = IwmmxtSaturateS32 (s, satrv + BITIDX32 (i)); + r |= (x & 0xffffffff) << (i * 32); + SIMD32_SET (psr, NBIT32 (x), SIMD_NBIT, i); + SIMD32_SET (psr, ZBIT32 (x), SIMD_ZBIT, i); + if (! satrv [BITIDX32 (i)]) + { + SIMD32_SET (psr, carry, SIMD_CBIT, i); + SIMD32_SET (psr, overflow, SIMD_VBIT, i); + } + break; + + default: + ARMul_UndefInstr (state, instr); + return ARMul_DONE; + } + } + break; + + default: + ARMul_UndefInstr (state, instr); + return ARMul_DONE; + } + + wR [BITS (12, 15)] = r; + wC [wCASF] = psr; + SET_wCSSFvec (satrv); + wC [wCon] |= (WCON_CUP | WCON_MUP); + +#undef SUBx + + return ARMul_DONE; +} + +static int +WUNPCKEH (ARMul_State * state, ARMword instr) +{ + ARMdword r = 0; + ARMword psr = 0; + ARMdword s; + int i; + + if ((read_cp15_reg (15, 0, 1) & 3) != 3) + return ARMul_CANT; + +#ifdef DEBUG + fprintf (stderr, "wunpckeh\n"); +#endif + + switch (BITS (22, 23)) + { + case Bqual: + for (i = 0; i < 4; i++) + { + s = wRBYTE (BITS (16, 19), i + 4); + + if (BIT (21) && NBIT8 (s)) + s |= 0xff00; + + r |= (s & 0xffff) << (i * 16); + SIMD16_SET (psr, NBIT16 (s), SIMD_NBIT, i); + SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i); + } + break; + + case Hqual: + for (i = 0; i < 2; i++) + { + s = wRHALF (BITS (16, 19), i + 2); + + if (BIT (21) && NBIT16 (s)) + s |= 0xffff0000; + + r |= (s & 0xffffffff) << (i * 32); + SIMD32_SET (psr, NBIT32 (s), SIMD_NBIT, i); + SIMD32_SET (psr, ZBIT32 (s), SIMD_ZBIT, i); + } + break; + + case Wqual: + r = wRWORD (BITS (16, 19), 1); + + if (BIT (21) && NBIT32 (r)) + r |= 0xffffffff00000000; + + SIMD64_SET (psr, NBIT64 (r), SIMD_NBIT); + SIMD64_SET (psr, ZBIT64 (r), SIMD_ZBIT); + break; + + default: + ARMul_UndefInstr (state, instr); + return ARMul_DONE; + } + + wC [wCASF] = psr; + wR [BITS (12, 15)] = r; + wC [wCon] |= (WCON_CUP | WCON_MUP); + + return ARMul_DONE; +} + +static int +WUNPCKEL (ARMul_State * state, ARMword instr) +{ + ARMdword r = 0; + ARMword psr = 0; + ARMdword s; + int i; + + if ((read_cp15_reg (15, 0, 1) & 3) != 3) + return ARMul_CANT; + +#ifdef DEBUG + fprintf (stderr, "wunpckel\n"); +#endif + + switch (BITS (22, 23)) + { + case Bqual: + for (i = 0; i < 4; i++) + { + s = wRBYTE (BITS (16, 19), i); + + if (BIT (21) && NBIT8 (s)) + s |= 0xff00; + + r |= (s & 0xffff) << (i * 16); + SIMD16_SET (psr, NBIT16 (s), SIMD_NBIT, i); + SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i); + } + break; + + case Hqual: + for (i = 0; i < 2; i++) + { + s = wRHALF (BITS (16, 19), i); + + if (BIT (21) && NBIT16 (s)) + s |= 0xffff0000; + + r |= (s & 0xffffffff) << (i * 32); + SIMD32_SET (psr, NBIT32 (s), SIMD_NBIT, i); + SIMD32_SET (psr, ZBIT32 (s), SIMD_ZBIT, i); + } + break; + + case Wqual: + r = wRWORD (BITS (16, 19), 0); + + if (BIT (21) && NBIT32 (r)) + r |= 0xffffffff00000000; + + SIMD64_SET (psr, NBIT64 (r), SIMD_NBIT); + SIMD64_SET (psr, ZBIT64 (r), SIMD_ZBIT); + break; + + default: + ARMul_UndefInstr (state, instr); + return ARMul_DONE; + } + + wC [wCASF] = psr; + wR [BITS (12, 15)] = r; + wC [wCon] |= (WCON_CUP | WCON_MUP); + + return ARMul_DONE; +} + +static int +WUNPCKIH (ARMul_State * state, ARMword instr) +{ + ARMword a, b; + ARMdword r = 0; + ARMword psr = 0; + ARMdword s; + int i; + + if ((read_cp15_reg (15, 0, 1) & 3) != 3) + return ARMul_CANT; + +#ifdef DEBUG + fprintf (stderr, "wunpckih\n"); +#endif + + switch (BITS (22, 23)) + { + case Bqual: + for (i = 0; i < 4; i++) + { + a = wRBYTE (BITS (16, 19), i + 4); + b = wRBYTE (BITS ( 0, 3), i + 4); + s = a | (b << 8); + r |= (s & 0xffff) << (i * 16); + SIMD8_SET (psr, NBIT8 (a), SIMD_NBIT, i * 2); + SIMD8_SET (psr, ZBIT8 (a), SIMD_ZBIT, i * 2); + SIMD8_SET (psr, NBIT8 (b), SIMD_NBIT, (i * 2) + 1); + SIMD8_SET (psr, ZBIT8 (b), SIMD_ZBIT, (i * 2) + 1); + } + break; + + case Hqual: + for (i = 0; i < 2; i++) + { + a = wRHALF (BITS (16, 19), i + 2); + b = wRHALF (BITS ( 0, 3), i + 2); + s = a | (b << 16); + r |= (s & 0xffffffff) << (i * 32); + SIMD16_SET (psr, NBIT16 (a), SIMD_NBIT, (i * 2)); + SIMD16_SET (psr, ZBIT16 (a), SIMD_ZBIT, (i * 2)); + SIMD16_SET (psr, NBIT16 (b), SIMD_NBIT, (i * 2) + 1); + SIMD16_SET (psr, ZBIT16 (b), SIMD_ZBIT, (i * 2) + 1); + } + break; + + case Wqual: + a = wRWORD (BITS (16, 19), 1); + s = wRWORD (BITS ( 0, 3), 1); + r = a | (s << 32); + + SIMD32_SET (psr, NBIT32 (a), SIMD_NBIT, 0); + SIMD32_SET (psr, ZBIT32 (a), SIMD_ZBIT, 0); + SIMD32_SET (psr, NBIT32 (s), SIMD_NBIT, 1); + SIMD32_SET (psr, ZBIT32 (s), SIMD_ZBIT, 1); + break; + + default: + ARMul_UndefInstr (state, instr); + return ARMul_DONE; + } + + wC [wCASF] = psr; + wR [BITS (12, 15)] = r; + wC [wCon] |= (WCON_CUP | WCON_MUP); + + return ARMul_DONE; +} + +static int +WUNPCKIL (ARMul_State * state, ARMword instr) +{ + ARMword a, b; + ARMdword r = 0; + ARMword psr = 0; + ARMdword s; + int i; + + if ((read_cp15_reg (15, 0, 1) & 3) != 3) + return ARMul_CANT; + +#ifdef DEBUG + fprintf (stderr, "wunpckil\n"); +#endif + + switch (BITS (22, 23)) + { + case Bqual: + for (i = 0; i < 4; i++) + { + a = wRBYTE (BITS (16, 19), i); + b = wRBYTE (BITS ( 0, 3), i); + s = a | (b << 8); + r |= (s & 0xffff) << (i * 16); + SIMD8_SET (psr, NBIT8 (a), SIMD_NBIT, i * 2); + SIMD8_SET (psr, ZBIT8 (a), SIMD_ZBIT, i * 2); + SIMD8_SET (psr, NBIT8 (b), SIMD_NBIT, (i * 2) + 1); + SIMD8_SET (psr, ZBIT8 (b), SIMD_ZBIT, (i * 2) + 1); + } + break; + + case Hqual: + for (i = 0; i < 2; i++) + { + a = wRHALF (BITS (16, 19), i); + b = wRHALF (BITS ( 0, 3), i); + s = a | (b << 16); + r |= (s & 0xffffffff) << (i * 32); + SIMD16_SET (psr, NBIT16 (a), SIMD_NBIT, (i * 2)); + SIMD16_SET (psr, ZBIT16 (a), SIMD_ZBIT, (i * 2)); + SIMD16_SET (psr, NBIT16 (b), SIMD_NBIT, (i * 2) + 1); + SIMD16_SET (psr, ZBIT16 (b), SIMD_ZBIT, (i * 2) + 1); + } + break; + + case Wqual: + a = wRWORD (BITS (16, 19), 0); + s = wRWORD (BITS ( 0, 3), 0); + r = a | (s << 32); + + SIMD32_SET (psr, NBIT32 (a), SIMD_NBIT, 0); + SIMD32_SET (psr, ZBIT32 (a), SIMD_ZBIT, 0); + SIMD32_SET (psr, NBIT32 (s), SIMD_NBIT, 1); + SIMD32_SET (psr, ZBIT32 (s), SIMD_ZBIT, 1); + break; + + default: + ARMul_UndefInstr (state, instr); + return ARMul_DONE; + } + + wC [wCASF] = psr; + wR [BITS (12, 15)] = r; + wC [wCon] |= (WCON_CUP | WCON_MUP); + + return ARMul_DONE; +} + +static int +WXOR (ARMword instr) +{ + ARMword psr = 0; + ARMdword result; + + if ((read_cp15_reg (15, 0, 1) & 3) != 3) + return ARMul_CANT; + +#ifdef DEBUG + fprintf (stderr, "wxor\n"); +#endif + + result = wR [BITS (16, 19)] ^ wR [BITS (0, 3)]; + wR [BITS (12, 15)] = result; + + SIMD64_SET (psr, (result == 0), SIMD_ZBIT); + SIMD64_SET (psr, (result & (1ULL << 63)), SIMD_NBIT); + + wC [wCASF] = psr; + wC [wCon] |= (WCON_CUP | WCON_MUP); + + return ARMul_DONE; +} + +/* This switch table is moved to a seperate function in order + to work around a compiler bug in the host compiler... */ + +static int +Process_Instruction (ARMul_State * state, ARMword instr) +{ + int status = ARMul_BUSY; + + switch ((BITS (20, 23) << 8) | BITS (4, 11)) + { + case 0x000: status = WOR (instr); break; + case 0x011: status = TMCR (state, instr); break; + case 0x100: status = WXOR (instr); break; + case 0x111: status = TMRC (state, instr); break; + case 0x300: status = WANDN (instr); break; + case 0x200: status = WAND (instr); break; + + case 0x810: case 0xa10: + status = WMADD (instr); break; + + case 0x10e: case 0x50e: case 0x90e: case 0xd0e: + status = WUNPCKIL (state, instr); break; + case 0x10c: case 0x50c: case 0x90c: case 0xd0c: + status = WUNPCKIH (state, instr); break; + case 0x012: case 0x112: case 0x412: case 0x512: + status = WSAD (instr); break; + case 0x010: case 0x110: case 0x210: case 0x310: + status = WMUL (instr); break; + case 0x410: case 0x510: case 0x610: case 0x710: + status = WMAC (instr); break; + case 0x006: case 0x406: case 0x806: case 0xc06: + status = WCMPEQ (state, instr); break; + case 0x800: case 0x900: case 0xc00: case 0xd00: + status = WAVG2 (instr); break; + case 0x802: case 0x902: case 0xa02: case 0xb02: + status = WALIGNR (state, instr); break; + case 0x601: case 0x605: case 0x609: case 0x60d: + status = TINSR (state, instr); break; + case 0x107: case 0x507: case 0x907: case 0xd07: + status = TEXTRM (state, instr); break; + case 0x117: case 0x517: case 0x917: case 0xd17: + status = TEXTRC (state, instr); break; + case 0x401: case 0x405: case 0x409: case 0x40d: + status = TBCST (state, instr); break; + case 0x113: case 0x513: case 0x913: case 0xd13: + status = TANDC (state, instr); break; + case 0x01c: case 0x41c: case 0x81c: case 0xc1c: + status = WACC (state, instr); break; + case 0x115: case 0x515: case 0x915: case 0xd15: + status = TORC (state, instr); break; + case 0x103: case 0x503: case 0x903: case 0xd03: + status = TMOVMSK (state, instr); break; + case 0x106: case 0x306: case 0x506: case 0x706: + case 0x906: case 0xb06: case 0xd06: case 0xf06: + status = WCMPGT (state, instr); break; + case 0x00e: case 0x20e: case 0x40e: case 0x60e: + case 0x80e: case 0xa0e: case 0xc0e: case 0xe0e: + status = WUNPCKEL (state, instr); break; + case 0x00c: case 0x20c: case 0x40c: case 0x60c: + case 0x80c: case 0xa0c: case 0xc0c: case 0xe0c: + status = WUNPCKEH (state, instr); break; + case 0x204: case 0x604: case 0xa04: case 0xe04: + case 0x214: case 0x614: case 0xa14: case 0xe14: + status = WSRL (state, instr); break; + case 0x004: case 0x404: case 0x804: case 0xc04: + case 0x014: case 0x414: case 0x814: case 0xc14: + status = WSRA (state, instr); break; + case 0x104: case 0x504: case 0x904: case 0xd04: + case 0x114: case 0x514: case 0x914: case 0xd14: + status = WSLL (state, instr); break; + case 0x304: case 0x704: case 0xb04: case 0xf04: + case 0x314: case 0x714: case 0xb14: case 0xf14: + status = WROR (state, instr); break; + case 0x116: case 0x316: case 0x516: case 0x716: + case 0x916: case 0xb16: case 0xd16: case 0xf16: + status = WMIN (state, instr); break; + case 0x016: case 0x216: case 0x416: case 0x616: + case 0x816: case 0xa16: case 0xc16: case 0xe16: + status = WMAX (state, instr); break; + case 0x002: case 0x102: case 0x202: case 0x302: + case 0x402: case 0x502: case 0x602: case 0x702: + status = WALIGNI (instr); break; + case 0x01a: case 0x11a: case 0x21a: case 0x31a: + case 0x41a: case 0x51a: case 0x61a: case 0x71a: + case 0x81a: case 0x91a: case 0xa1a: case 0xb1a: + case 0xc1a: case 0xd1a: case 0xe1a: case 0xf1a: + status = WSUB (state, instr); break; + case 0x01e: case 0x11e: case 0x21e: case 0x31e: + case 0x41e: case 0x51e: case 0x61e: case 0x71e: + case 0x81e: case 0x91e: case 0xa1e: case 0xb1e: + case 0xc1e: case 0xd1e: case 0xe1e: case 0xf1e: + status = WSHUFH (instr); break; + case 0x018: case 0x118: case 0x218: case 0x318: + case 0x418: case 0x518: case 0x618: case 0x718: + case 0x818: case 0x918: case 0xa18: case 0xb18: + case 0xc18: case 0xd18: case 0xe18: case 0xf18: + status = WADD (state, instr); break; + case 0x008: case 0x108: case 0x208: case 0x308: + case 0x408: case 0x508: case 0x608: case 0x708: + case 0x808: case 0x908: case 0xa08: case 0xb08: + case 0xc08: case 0xd08: case 0xe08: case 0xf08: + status = WPACK (state, instr); break; + case 0x201: case 0x203: case 0x205: case 0x207: + case 0x209: case 0x20b: case 0x20d: case 0x20f: + case 0x211: case 0x213: case 0x215: case 0x217: + case 0x219: case 0x21b: case 0x21d: case 0x21f: + switch (BITS (16, 19)) + { + case 0x0: status = TMIA (state, instr); break; + case 0x8: status = TMIAPH (state, instr); break; + case 0xc: + case 0xd: + case 0xe: + case 0xf: status = TMIAxy (state, instr); break; + default: break; + } + break; + default: + break; + } + return status; +} + +/* Process a possibly Intel(r) Wireless MMX(tm) technology instruction. + Return true if the instruction was handled. */ + +int +ARMul_HandleIwmmxt (ARMul_State * state, ARMword instr) +{ + int status = ARMul_BUSY; + + if (BITS (24, 27) == 0xe) + { + status = Process_Instruction (state, instr); + } + else if (BITS (25, 27) == 0x6) + { + if (BITS (4, 11) == 0x0 && BITS (20, 24) == 0x4) + status = TMCRR (state, instr); + else if (BITS (9, 11) == 0x0) + { + if (BIT (20) == 0x0) + status = WSTR (state, instr); + else if (BITS (20, 24) == 0x5) + status = TMRRC (state, instr); + else + status = WLDR (state, instr); + } + } + + if (status == ARMul_CANT) + { + /* If the instruction was a recognised but illegal, + perform the abort here rather than returning false. + If we return false then ARMul_MRC may be called which + will still abort, but which also perform the register + transfer... */ + ARMul_Abort (state, ARMul_UndefinedInstrV); + status = ARMul_DONE; + } + + return status == ARMul_DONE; +} + +int +Fetch_Iwmmxt_Register (unsigned int regnum, unsigned char * memory) +{ + if (regnum >= 16) + { + memcpy (memory, wC + (regnum - 16), sizeof wC [0]); + return sizeof wC [0]; + } + else + { + memcpy (memory, wR + regnum, sizeof wR [0]); + return sizeof wR [0]; + } +} + +int +Store_Iwmmxt_Register (unsigned int regnum, unsigned char * memory) +{ + if (regnum >= 16) + { + memcpy (wC + (regnum - 16), memory, sizeof wC [0]); + return sizeof wC [0]; + } + else + { + memcpy (wR + regnum, memory, sizeof wR [0]); + return sizeof wR [0]; + } +} diff --git a/sim/arm/iwmmxt.h b/sim/arm/iwmmxt.h new file mode 100644 index 0000000..e25feab --- /dev/null +++ b/sim/arm/iwmmxt.h @@ -0,0 +1,28 @@ +/* iwmmxt.h -- Intel(r) Wireless MMX(tm) technology co-processor interface. + Copyright (C) 2002 Free Software Foundation, Inc. + Contributed by matthew green (mrg@redhat.com). + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +extern unsigned IwmmxtLDC (ARMul_State *, unsigned, ARMword, ARMword); +extern unsigned IwmmxtSTC (ARMul_State *, unsigned, ARMword, ARMword *); +extern unsigned IwmmxtMCR (ARMul_State *, unsigned, ARMword, ARMword); +extern unsigned IwmmxtMRC (ARMul_State *, unsigned, ARMword, ARMword *); +extern unsigned IwmmxtCDP (ARMul_State *, unsigned, ARMword); + +extern int ARMul_HandleIwmmxt (ARMul_State *, ARMword); + +extern int Fetch_Iwmmxt_Register (unsigned int, unsigned char *); +extern int Store_Iwmmxt_Register (unsigned int, unsigned char *); diff --git a/sim/arm/maverick.c b/sim/arm/maverick.c new file mode 100644 index 0000000..82871f9 --- /dev/null +++ b/sim/arm/maverick.c @@ -0,0 +1,1291 @@ +/* maverick.c -- Cirrus/DSP co-processor interface. + Copyright (C) 2003 Free Software Foundation, Inc. + Contributed by Aldy Hernandez (aldyh@redhat.com). + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include +#include "armdefs.h" +#include "ansidecl.h" +#include "armemu.h" + +/*#define CIRRUS_DEBUG 1 /**/ +#if CIRRUS_DEBUG +# define printfdbg printf +#else +# define printfdbg printf_nothing +#endif + +#define POS64(i) ( (~(i)) >> 63 ) +#define NEG64(i) ( (i) >> 63 ) + +/* Define Co-Processor instruction handlers here. */ + +/* Here's ARMulator's DSP definition. A few things to note: + 1) it has 16 64-bit registers and 4 72-bit accumulators + 2) you can only access its registers with MCR and MRC. */ + +/* We can't define these in here because this file might not be linked + unless the target is arm9e-*. They are defined in wrapper.c. + Eventually the simulator should be made to handle any coprocessor + at run time. */ +struct maverick_regs +{ + union + { + int i; + float f; + } upper; + + union + { + int i; + float f; + } lower; +}; + +union maverick_acc_regs +{ + long double ld; /* Acc registers are 72-bits. */ +}; + +struct maverick_regs DSPregs[16]; +union maverick_acc_regs DSPacc[4]; +ARMword DSPsc; + +#define DEST_REG (BITS (12, 15)) +#define SRC1_REG (BITS (16, 19)) +#define SRC2_REG (BITS (0, 3)) + +static int lsw_int_index, msw_int_index; +static int lsw_float_index, msw_float_index; + +static double mv_getRegDouble (int); +static long long mv_getReg64int (int); +static void mv_setRegDouble (int, double val); +static void mv_setReg64int (int, long long val); + +static union +{ + double d; + long long ll; + int ints[2]; +} reg_conv; + +static void +printf_nothing (void * foo, ...) +{ +} + +static void +cirrus_not_implemented (char * insn) +{ + fprintf (stderr, "Cirrus instruction '%s' not implemented.\n", insn); + fprintf (stderr, "aborting!\n"); + + exit (1); +} + +static unsigned +DSPInit (ARMul_State * state) +{ + ARMul_ConsolePrint (state, ", DSP present"); + return TRUE; +} + +unsigned +DSPMRC4 (ARMul_State * state ATTRIBUTE_UNUSED, + unsigned type ATTRIBUTE_UNUSED, + ARMword instr, + ARMword * value) +{ + switch (BITS (5, 7)) + { + case 0: /* cfmvrdl */ + /* Move lower half of a DF stored in a DSP reg into an Arm reg. */ + printfdbg ("cfmvrdl\n"); + printfdbg ("\tlower half=0x%x\n", DSPregs[SRC1_REG].lower.i); + printfdbg ("\tentire thing=%g\n", mv_getRegDouble (SRC1_REG)); + + *value = (ARMword) DSPregs[SRC1_REG].lower.i; + break; + + case 1: /* cfmvrdh */ + /* Move upper half of a DF stored in a DSP reg into an Arm reg. */ + printfdbg ("cfmvrdh\n"); + printfdbg ("\tupper half=0x%x\n", DSPregs[SRC1_REG].upper.i); + printfdbg ("\tentire thing=%g\n", mv_getRegDouble (SRC1_REG)); + + *value = (ARMword) DSPregs[SRC1_REG].upper.i; + break; + + case 2: /* cfmvrs */ + /* Move SF from upper half of a DSP register to an Arm register. */ + *value = (ARMword) DSPregs[SRC1_REG].upper.i; + printfdbg ("cfmvrs = mvf%d <-- %f\n", + SRC1_REG, + DSPregs[SRC1_REG].upper.f); + break; + +#ifdef doesnt_work + case 4: /* cfcmps */ + { + float a, b; + int n, z, c, v; + + a = DSPregs[SRC1_REG].upper.f; + b = DSPregs[SRC2_REG].upper.f; + + printfdbg ("cfcmps\n"); + printfdbg ("\tcomparing %f and %f\n", a, b); + + z = a == b; /* zero */ + n = a != b; /* negative */ + v = a > b; /* overflow */ + c = 0; /* carry */ + *value = (n << 31) | (z << 30) | (c << 29) | (v << 28); + break; + } + + case 5: /* cfcmpd */ + { + double a, b; + int n, z, c, v; + + a = mv_getRegDouble (SRC1_REG); + b = mv_getRegDouble (SRC2_REG); + + printfdbg ("cfcmpd\n"); + printfdbg ("\tcomparing %g and %g\n", a, b); + + z = a == b; /* zero */ + n = a != b; /* negative */ + v = a > b; /* overflow */ + c = 0; /* carry */ + *value = (n << 31) | (z << 30) | (c << 29) | (v << 28); + break; + } +#else + case 4: /* cfcmps */ + { + float a, b; + int n, z, c, v; + + a = DSPregs[SRC1_REG].upper.f; + b = DSPregs[SRC2_REG].upper.f; + + printfdbg ("cfcmps\n"); + printfdbg ("\tcomparing %f and %f\n", a, b); + + z = a == b; /* zero */ + n = a < b; /* negative */ + c = a > b; /* carry */ + v = 0; /* fixme */ + printfdbg ("\tz = %d, n = %d\n", z, n); + *value = (n << 31) | (z << 30) | (c << 29) | (v << 28); + break; + } + + case 5: /* cfcmpd */ + { + double a, b; + int n, z, c, v; + + a = mv_getRegDouble (SRC1_REG); + b = mv_getRegDouble (SRC2_REG); + + printfdbg ("cfcmpd\n"); + printfdbg ("\tcomparing %g and %g\n", a, b); + + z = a == b; /* zero */ + n = a < b; /* negative */ + c = a > b; /* carry */ + v = 0; /* fixme */ + *value = (n << 31) | (z << 30) | (c << 29) | (v << 28); + break; + } +#endif + default: + fprintf (stderr, "unknown opcode in DSPMRC4 0x%x\n", instr); + cirrus_not_implemented ("unknown"); + break; + } + + return ARMul_DONE; +} + +unsigned +DSPMRC5 (ARMul_State * state ATTRIBUTE_UNUSED, + unsigned type ATTRIBUTE_UNUSED, + ARMword instr, + ARMword * value) +{ + switch (BITS (5, 7)) + { + case 0: /* cfmvr64l */ + /* Move lower half of 64bit int from Cirrus to Arm. */ + *value = (ARMword) DSPregs[SRC1_REG].lower.i; + printfdbg ("cfmvr64l ARM_REG = mvfx%d <-- %d\n", + DEST_REG, + (int) *value); + break; + + case 1: /* cfmvr64h */ + /* Move upper half of 64bit int from Cirrus to Arm. */ + *value = (ARMword) DSPregs[SRC1_REG].upper.i; + printfdbg ("cfmvr64h <-- %d\n", (int) *value); + break; + + case 4: /* cfcmp32 */ + { + int res; + int n, z, c, v; + unsigned int a, b; + + printfdbg ("cfcmp32 mvfx%d - mvfx%d\n", + SRC1_REG, + SRC2_REG); + + /* FIXME: see comment for cfcmps. */ + a = DSPregs[SRC1_REG].lower.i; + b = DSPregs[SRC2_REG].lower.i; + + res = DSPregs[SRC1_REG].lower.i - DSPregs[SRC2_REG].lower.i; + /* zero */ + z = res == 0; + /* negative */ + n = res < 0; + /* overflow */ + v = SubOverflow (DSPregs[SRC1_REG].lower.i, DSPregs[SRC2_REG].lower.i, + res); + /* carry */ + c = (NEG (a) && POS (b) || + (NEG (a) && POS (res)) || (POS (b) && POS (res))); + + *value = (n << 31) | (z << 30) | (c << 29) | (v << 28); + break; + } + + case 5: /* cfcmp64 */ + { + long long res; + int n, z, c, v; + unsigned long long a, b; + + printfdbg ("cfcmp64 mvdx%d - mvdx%d\n", + SRC1_REG, + SRC2_REG); + + /* fixme: see comment for cfcmps. */ + + a = mv_getReg64int (SRC1_REG); + b = mv_getReg64int (SRC2_REG); + + res = mv_getReg64int (SRC1_REG) - mv_getReg64int (SRC2_REG); + /* zero */ + z = res == 0; + /* negative */ + n = res < 0; + /* overflow */ + v = ((NEG64 (a) && POS64 (b) && POS64 (res)) + || (POS64 (a) && NEG64 (b) && NEG64 (res))); + /* carry */ + c = (NEG64 (a) && POS64 (b) || + (NEG64 (a) && POS64 (res)) || (POS64 (b) && POS64 (res))); + + *value = (n << 31) | (z << 30) | (c << 29) | (v << 28); + break; + } + + default: + fprintf (stderr, "unknown opcode in DSPMRC5 0x%x\n", instr); + cirrus_not_implemented ("unknown"); + break; + } + + return ARMul_DONE; +} + +unsigned +DSPMRC6 (ARMul_State * state ATTRIBUTE_UNUSED, + unsigned type ATTRIBUTE_UNUSED, + ARMword instr, + ARMword * value) +{ + switch (BITS (5, 7)) + { + case 0: /* cfmval32 */ + cirrus_not_implemented ("cfmval32"); + break; + + case 1: /* cfmvam32 */ + cirrus_not_implemented ("cfmvam32"); + break; + + case 2: /* cfmvah32 */ + cirrus_not_implemented ("cfmvah32"); + break; + + case 3: /* cfmva32 */ + cirrus_not_implemented ("cfmva32"); + break; + + case 4: /* cfmva64 */ + cirrus_not_implemented ("cfmva64"); + break; + + case 5: /* cfmvsc32 */ + cirrus_not_implemented ("cfmvsc32"); + break; + + default: + fprintf (stderr, "unknown opcode in DSPMRC6 0x%x\n", instr); + cirrus_not_implemented ("unknown"); + break; + } + + return ARMul_DONE; +} + +unsigned +DSPMCR4 (ARMul_State * state, + unsigned type ATTRIBUTE_UNUSED, + ARMword instr, + ARMword value) +{ + switch (BITS (5, 7)) + { + case 0: /* cfmvdlr */ + /* Move the lower half of a DF value from an Arm register into + the lower half of a Cirrus register. */ + printfdbg ("cfmvdlr <-- 0x%x\n", (int) value); + DSPregs[SRC1_REG].lower.i = (int) value; + break; + + case 1: /* cfmvdhr */ + /* Move the upper half of a DF value from an Arm register into + the upper half of a Cirrus register. */ + printfdbg ("cfmvdhr <-- 0x%x\n", (int) value); + DSPregs[SRC1_REG].upper.i = (int) value; + break; + + case 2: /* cfmvsr */ + /* Move SF from Arm register into upper half of Cirrus register. */ + printfdbg ("cfmvsr <-- 0x%x\n", (int) value); + DSPregs[SRC1_REG].upper.i = (int) value; + break; + + default: + fprintf (stderr, "unknown opcode in DSPMCR4 0x%x\n", instr); + cirrus_not_implemented ("unknown"); + break; + } + + return ARMul_DONE; +} + +unsigned +DSPMCR5 (ARMul_State * state, + unsigned type ATTRIBUTE_UNUSED, + ARMword instr, + ARMword value) +{ + union + { + int s; + unsigned int us; + } val; + + switch (BITS (5, 7)) + { + case 0: /* cfmv64lr */ + /* Move lower half of a 64bit int from an ARM register into the + lower half of a DSP register and sign extend it. */ + printfdbg ("cfmv64lr mvdx%d <-- 0x%x\n", SRC1_REG, (int) value); + DSPregs[SRC1_REG].lower.i = (int) value; + break; + + case 1: /* cfmv64hr */ + /* Move upper half of a 64bit int from an ARM register into the + upper half of a DSP register. */ + printfdbg ("cfmv64hr ARM_REG = mvfx%d <-- 0x%x\n", + SRC1_REG, + (int) value); + DSPregs[SRC1_REG].upper.i = (int) value; + break; + + case 2: /* cfrshl32 */ + printfdbg ("cfrshl32\n"); + val.us = value; + if (val.s > 0) + DSPregs[SRC2_REG].lower.i = DSPregs[SRC1_REG].lower.i << value; + else + DSPregs[SRC2_REG].lower.i = DSPregs[SRC1_REG].lower.i >> -value; + break; + + case 3: /* cfrshl64 */ + printfdbg ("cfrshl64\n"); + val.us = value; + if (val.s > 0) + mv_setReg64int (SRC2_REG, mv_getReg64int (SRC1_REG) << value); + else + mv_setReg64int (SRC2_REG, mv_getReg64int (SRC1_REG) >> -value); + break; + + default: + fprintf (stderr, "unknown opcode in DSPMCR5 0x%x\n", instr); + cirrus_not_implemented ("unknown"); + break; + } + + return ARMul_DONE; +} + +unsigned +DSPMCR6 (ARMul_State * state, + unsigned type ATTRIBUTE_UNUSED, + ARMword instr, + ARMword value) +{ + switch (BITS (5, 7)) + { + case 0: /* cfmv32al */ + cirrus_not_implemented ("cfmv32al"); + break; + + case 1: /* cfmv32am */ + cirrus_not_implemented ("cfmv32am"); + break; + + case 2: /* cfmv32ah */ + cirrus_not_implemented ("cfmv32ah"); + break; + + case 3: /* cfmv32a */ + cirrus_not_implemented ("cfmv32a"); + break; + + case 4: /* cfmv64a */ + cirrus_not_implemented ("cfmv64a"); + break; + + case 5: /* cfmv32sc */ + cirrus_not_implemented ("cfmv32sc"); + break; + + default: + fprintf (stderr, "unknown opcode in DSPMCR6 0x%x\n", instr); + cirrus_not_implemented ("unknown"); + break; + } + + return ARMul_DONE; +} + +unsigned +DSPLDC4 (ARMul_State * state ATTRIBUTE_UNUSED, + unsigned type, + ARMword instr, + ARMword data) +{ + static unsigned words; + + if (type != ARMul_DATA) + { + words = 0; + return ARMul_DONE; + } + + if (BIT (22)) + { /* it's a long access, get two words */ + /* cfldrd */ + + printfdbg ("cfldrd: %x (words = %d) (bigend = %d) DESTREG = %d\n", + data, words, state->bigendSig, DEST_REG); + + if (words == 0) + { + if (state->bigendSig) + DSPregs[DEST_REG].upper.i = (int) data; + else + DSPregs[DEST_REG].lower.i = (int) data; + } + else + { + if (state->bigendSig) + DSPregs[DEST_REG].lower.i = (int) data; + else + DSPregs[DEST_REG].upper.i = (int) data; + } + + ++ words; + + if (words == 2) + { + printfdbg ("\tmvd%d <-- mem = %g\n", DEST_REG, + mv_getRegDouble (DEST_REG)); + + return ARMul_DONE; + } + else + return ARMul_INC; + } + else + { + /* Get just one word. */ + + /* cfldrs */ + printfdbg ("cfldrs\n"); + + DSPregs[DEST_REG].upper.i = (int) data; + + printfdbg ("\tmvf%d <-- mem = %f\n", DEST_REG, + DSPregs[DEST_REG].upper.f); + + return ARMul_DONE; + } +} + +unsigned +DSPLDC5 (ARMul_State * state ATTRIBUTE_UNUSED, + unsigned type, + ARMword instr, + ARMword data) +{ + static unsigned words; + + if (type != ARMul_DATA) + { + words = 0; + return ARMul_DONE; + } + + if (BIT (22)) + { + /* It's a long access, get two words. */ + + /* cfldr64 */ + printfdbg ("cfldr64: %d\n", data); + + if (words == 0) + { + if (state->bigendSig) + DSPregs[DEST_REG].upper.i = (int) data; + else + DSPregs[DEST_REG].lower.i = (int) data; + } + else + { + if (state->bigendSig) + DSPregs[DEST_REG].lower.i = (int) data; + else + DSPregs[DEST_REG].upper.i = (int) data; + } + + ++ words; + + if (words == 2) + { + printfdbg ("\tmvdx%d <-- mem = %lld\n", DEST_REG, + mv_getReg64int (DEST_REG)); + + return ARMul_DONE; + } + else + return ARMul_INC; + } + else + { + /* Get just one word. */ + + /* cfldr32 */ + printfdbg ("cfldr32 mvfx%d <-- %d\n", DEST_REG, (int) data); + + /* 32bit ints should be sign extended to 64bits when loaded. */ + mv_setReg64int (DEST_REG, (long long) data); + + return ARMul_DONE; + } +} + +unsigned +DSPSTC4 (ARMul_State * state ATTRIBUTE_UNUSED, + unsigned type, + ARMword instr, + ARMword * data) +{ + static unsigned words; + + if (type != ARMul_DATA) + { + words = 0; + return ARMul_DONE; + } + + if (BIT (22)) + { + /* It's a long access, get two words. */ + /* cfstrd */ + printfdbg ("cfstrd\n"); + + if (words == 0) + { + if (state->bigendSig) + *data = (ARMword) DSPregs[DEST_REG].upper.i; + else + *data = (ARMword) DSPregs[DEST_REG].lower.i; + } + else + { + if (state->bigendSig) + *data = (ARMword) DSPregs[DEST_REG].lower.i; + else + *data = (ARMword) DSPregs[DEST_REG].upper.i; + } + + ++ words; + + if (words == 2) + { + printfdbg ("\tmem = mvd%d = %g\n", DEST_REG, + mv_getRegDouble (DEST_REG)); + + return ARMul_DONE; + } + else + return ARMul_INC; + } + else + { + /* Get just one word. */ + /* cfstrs */ + printfdbg ("cfstrs mvf%d <-- %f\n", DEST_REG, + DSPregs[DEST_REG].upper.f); + + *data = (ARMword) DSPregs[DEST_REG].upper.i; + + return ARMul_DONE; + } +} + +unsigned +DSPSTC5 (ARMul_State * state ATTRIBUTE_UNUSED, + unsigned type, + ARMword instr, + ARMword * data) +{ + static unsigned words; + + if (type != ARMul_DATA) + { + words = 0; + return ARMul_DONE; + } + + if (BIT (22)) + { + /* It's a long access, store two words. */ + /* cfstr64 */ + printfdbg ("cfstr64\n"); + + if (words == 0) + { + if (state->bigendSig) + *data = (ARMword) DSPregs[DEST_REG].upper.i; + else + *data = (ARMword) DSPregs[DEST_REG].lower.i; + } + else + { + if (state->bigendSig) + *data = (ARMword) DSPregs[DEST_REG].lower.i; + else + *data = (ARMword) DSPregs[DEST_REG].upper.i; + } + + ++ words; + + if (words == 2) + { + printfdbg ("\tmem = mvd%d = %lld\n", DEST_REG, + mv_getReg64int (DEST_REG)); + + return ARMul_DONE; + } + else + return ARMul_INC; + } + else + { + /* Store just one word. */ + /* cfstr32 */ + *data = (ARMword) DSPregs[DEST_REG].lower.i; + + printfdbg ("cfstr32 MEM = %d\n", (int) *data); + + return ARMul_DONE; + } +} + +unsigned +DSPCDP4 (ARMul_State * state, + unsigned type, + ARMword instr) +{ + int opcode2; + + opcode2 = BITS (5,7); + + switch (BITS (20,21)) + { + case 0: + switch (opcode2) + { + case 0: /* cfcpys */ + printfdbg ("cfcpys mvf%d = mvf%d = %f\n", + DEST_REG, + SRC1_REG, + DSPregs[SRC1_REG].upper.f); + DSPregs[DEST_REG].upper.f = DSPregs[SRC1_REG].upper.f; + break; + + case 1: /* cfcpyd */ + printfdbg ("cfcpyd mvd%d = mvd%d = %g\n", + DEST_REG, + SRC1_REG, + mv_getRegDouble (SRC1_REG)); + mv_setRegDouble (DEST_REG, mv_getRegDouble (SRC1_REG)); + break; + + case 2: /* cfcvtds */ + printfdbg ("cfcvtds mvf%d = (float) mvd%d = %f\n", + DEST_REG, + SRC1_REG, + (float) mv_getRegDouble (SRC1_REG)); + DSPregs[DEST_REG].upper.f = (float) mv_getRegDouble (SRC1_REG); + break; + + case 3: /* cfcvtsd */ + printfdbg ("cfcvtsd mvd%d = mvf%d = %g\n", + DEST_REG, + SRC1_REG, + (double) DSPregs[SRC1_REG].upper.f); + mv_setRegDouble (DEST_REG, (double) DSPregs[SRC1_REG].upper.f); + break; + + case 4: /* cfcvt32s */ + printfdbg ("cfcvt32s mvf%d = mvfx%d = %f\n", + DEST_REG, + SRC1_REG, + (float) DSPregs[SRC1_REG].lower.i); + DSPregs[DEST_REG].upper.f = (float) DSPregs[SRC1_REG].lower.i; + break; + + case 5: /* cfcvt32d */ + printfdbg ("cfcvt32d mvd%d = mvfx%d = %g\n", + DEST_REG, + SRC1_REG, + (double) DSPregs[SRC1_REG].lower.i); + mv_setRegDouble (DEST_REG, (double) DSPregs[SRC1_REG].lower.i); + break; + + case 6: /* cfcvt64s */ + printfdbg ("cfcvt64s mvf%d = mvdx%d = %f\n", + DEST_REG, + SRC1_REG, + (float) mv_getReg64int (SRC1_REG)); + DSPregs[DEST_REG].upper.f = (float) mv_getReg64int (SRC1_REG); + break; + + case 7: /* cfcvt64d */ + printfdbg ("cfcvt64d mvd%d = mvdx%d = %g\n", + DEST_REG, + SRC1_REG, + (double) mv_getReg64int (SRC1_REG)); + mv_setRegDouble (DEST_REG, (double) mv_getReg64int (SRC1_REG)); + break; + } + break; + + case 1: + switch (opcode2) + { + case 0: /* cfmuls */ + printfdbg ("cfmuls mvf%d = mvf%d = %f\n", + DEST_REG, + SRC1_REG, + DSPregs[SRC1_REG].upper.f * DSPregs[SRC2_REG].upper.f); + + DSPregs[DEST_REG].upper.f = DSPregs[SRC1_REG].upper.f + * DSPregs[SRC2_REG].upper.f; + break; + + case 1: /* cfmuld */ + printfdbg ("cfmuld mvd%d = mvd%d = %g\n", + DEST_REG, + SRC1_REG, + mv_getRegDouble (SRC1_REG) * mv_getRegDouble (SRC2_REG)); + + mv_setRegDouble (DEST_REG, + mv_getRegDouble (SRC1_REG) + * mv_getRegDouble (SRC2_REG)); + break; + + default: + fprintf (stderr, "unknown opcode in DSPCDP4 0x%x\n", instr); + cirrus_not_implemented ("unknown"); + break; + } + break; + + case 3: + switch (opcode2) + { + case 0: /* cfabss */ + DSPregs[DEST_REG].upper.f = (DSPregs[SRC1_REG].upper.f < 0.0F ? + -DSPregs[SRC1_REG].upper.f + : DSPregs[SRC1_REG].upper.f); + printfdbg ("cfabss mvf%d = |mvf%d| = %f\n", + DEST_REG, + SRC1_REG, + DSPregs[DEST_REG].upper.f); + break; + + case 1: /* cfabsd */ + mv_setRegDouble (DEST_REG, + (mv_getRegDouble (SRC1_REG) < 0.0 ? + -mv_getRegDouble (SRC1_REG) + : mv_getRegDouble (SRC1_REG))); + printfdbg ("cfabsd mvd%d = |mvd%d| = %g\n", + DEST_REG, + SRC1_REG, + mv_getRegDouble (DEST_REG)); + break; + + case 2: /* cfnegs */ + DSPregs[DEST_REG].upper.f = -DSPregs[SRC1_REG].upper.f; + printfdbg ("cfnegs mvf%d = -mvf%d = %f\n", + DEST_REG, + SRC1_REG, + DSPregs[DEST_REG].upper.f); + break; + + case 3: /* cfnegd */ + mv_setRegDouble (DEST_REG, + -mv_getRegDouble (SRC1_REG)); + printfdbg ("cfnegd mvd%d = -mvd%d = %g\n", + DEST_REG, + mv_getRegDouble (DEST_REG)); + break; + + case 4: /* cfadds */ + DSPregs[DEST_REG].upper.f = DSPregs[SRC1_REG].upper.f + + DSPregs[SRC2_REG].upper.f; + printfdbg ("cfadds mvf%d = mvf%d + mvf%d = %f\n", + DEST_REG, + SRC1_REG, + SRC2_REG, + DSPregs[DEST_REG].upper.f); + break; + + case 5: /* cfaddd */ + mv_setRegDouble (DEST_REG, + mv_getRegDouble (SRC1_REG) + + mv_getRegDouble (SRC2_REG)); + printfdbg ("cfaddd: mvd%d = mvd%d + mvd%d = %g\n", + DEST_REG, + SRC1_REG, + SRC2_REG, + mv_getRegDouble (DEST_REG)); + break; + + case 6: /* cfsubs */ + DSPregs[DEST_REG].upper.f = DSPregs[SRC1_REG].upper.f + - DSPregs[SRC2_REG].upper.f; + printfdbg ("cfsubs: mvf%d = mvf%d - mvf%d = %f\n", + DEST_REG, + SRC1_REG, + SRC2_REG, + DSPregs[DEST_REG].upper.f); + break; + + case 7: /* cfsubd */ + mv_setRegDouble (DEST_REG, + mv_getRegDouble (SRC1_REG) + - mv_getRegDouble (SRC2_REG)); + printfdbg ("cfsubd: mvd%d = mvd%d - mvd%d = %g\n", + DEST_REG, + SRC1_REG, + SRC2_REG, + mv_getRegDouble (DEST_REG)); + break; + } + break; + + default: + fprintf (stderr, "unknown opcode in DSPCDP4 0x%x\n", instr); + cirrus_not_implemented ("unknown"); + break; + } + + return ARMul_DONE; +} + +unsigned +DSPCDP5 (ARMul_State * state, + unsigned type, + ARMword instr) +{ + int opcode2; + char shift; + + opcode2 = BITS (5,7); + + /* Shift constants are 7bit signed numbers in bits 0..3|5..7. */ + shift = BITS (0, 3) | (BITS (5, 7)) << 4; + if (shift & 0x40) + shift |= 0xc0; + + switch (BITS (20,21)) + { + case 0: + /* cfsh32 */ + printfdbg ("cfsh32 %s amount=%d\n", shift < 0 ? "right" : "left", + shift); + if (shift < 0) + /* Negative shift is a right shift. */ + DSPregs[DEST_REG].lower.i = DSPregs[SRC1_REG].lower.i >> -shift; + else + /* Positive shift is a left shift. */ + DSPregs[DEST_REG].lower.i = DSPregs[SRC1_REG].lower.i << shift; + break; + + case 1: + switch (opcode2) + { + case 0: /* cfmul32 */ + DSPregs[DEST_REG].lower.i = DSPregs[SRC1_REG].lower.i + * DSPregs[SRC2_REG].lower.i; + printfdbg ("cfmul32 mvfx%d = mvfx%d * mvfx%d = %d\n", + DEST_REG, + SRC1_REG, + SRC2_REG, + DSPregs[DEST_REG].lower.i); + break; + + case 1: /* cfmul64 */ + mv_setReg64int (DEST_REG, + mv_getReg64int (SRC1_REG) + * mv_getReg64int (SRC2_REG)); + printfdbg ("cfmul64 mvdx%d = mvdx%d * mvdx%d = %lld\n", + DEST_REG, + SRC1_REG, + SRC2_REG, + mv_getReg64int (DEST_REG)); + break; + + case 2: /* cfmac32 */ + DSPregs[DEST_REG].lower.i + += DSPregs[SRC1_REG].lower.i * DSPregs[SRC2_REG].lower.i; + printfdbg ("cfmac32 mvfx%d += mvfx%d * mvfx%d = %d\n", + DEST_REG, + SRC1_REG, + SRC2_REG, + DSPregs[DEST_REG].lower.i); + break; + + case 3: /* cfmsc32 */ + DSPregs[DEST_REG].lower.i + -= DSPregs[SRC1_REG].lower.i * DSPregs[SRC2_REG].lower.i; + printfdbg ("cfmsc32 mvfx%d -= mvfx%d * mvfx%d = %d\n", + DEST_REG, + SRC1_REG, + SRC2_REG, + DSPregs[DEST_REG].lower.i); + break; + + case 4: /* cfcvts32 */ + /* fixme: this should round */ + DSPregs[DEST_REG].lower.i = (int) DSPregs[SRC1_REG].upper.f; + printfdbg ("cfcvts32 mvfx%d = mvf%d = %d\n", + DEST_REG, + SRC1_REG, + DSPregs[DEST_REG].lower.i); + break; + + case 5: /* cfcvtd32 */ + /* fixme: this should round */ + DSPregs[DEST_REG].lower.i = (int) mv_getRegDouble (SRC1_REG); + printfdbg ("cfcvtd32 mvdx%d = mvd%d = %d\n", + DEST_REG, + SRC1_REG, + DSPregs[DEST_REG].lower.i); + break; + + case 6: /* cftruncs32 */ + DSPregs[DEST_REG].lower.i = (int) DSPregs[SRC1_REG].upper.f; + printfdbg ("cftruncs32 mvfx%d = mvf%d = %d\n", + DEST_REG, + SRC1_REG, + DSPregs[DEST_REG].lower.i); + break; + + case 7: /* cftruncd32 */ + DSPregs[DEST_REG].lower.i = (int) mv_getRegDouble (SRC1_REG); + printfdbg ("cftruncd32 mvfx%d = mvd%d = %d\n", + DEST_REG, + SRC1_REG, + DSPregs[DEST_REG].lower.i); + break; + } + break; + + case 2: + /* cfsh64 */ + printfdbg ("cfsh64\n"); + + if (shift < 0) + /* Negative shift is a right shift. */ + mv_setReg64int (DEST_REG, + mv_getReg64int (SRC1_REG) >> -shift); + else + /* Positive shift is a left shift. */ + mv_setReg64int (DEST_REG, + mv_getReg64int (SRC1_REG) << shift); + printfdbg ("\t%llx\n", mv_getReg64int(DEST_REG)); + break; + + case 3: + switch (opcode2) + { + case 0: /* cfabs32 */ + DSPregs[DEST_REG].lower.i = (DSPregs[SRC1_REG].lower.i < 0 + ? -DSPregs[SRC1_REG].lower.i : DSPregs[SRC1_REG].lower.i); + printfdbg ("cfabs32 mvfx%d = |mvfx%d| = %d\n", + DEST_REG, + SRC1_REG, + SRC2_REG, + DSPregs[DEST_REG].lower.i); + break; + + case 1: /* cfabs64 */ + mv_setReg64int (DEST_REG, + (mv_getReg64int (SRC1_REG) < 0 + ? -mv_getReg64int (SRC1_REG) + : mv_getReg64int (SRC1_REG))); + printfdbg ("cfabs64 mvdx%d = |mvdx%d| = %lld\n", + DEST_REG, + SRC1_REG, + SRC2_REG, + mv_getReg64int (DEST_REG)); + break; + + case 2: /* cfneg32 */ + DSPregs[DEST_REG].lower.i = -DSPregs[SRC1_REG].lower.i; + printfdbg ("cfneg32 mvfx%d = -mvfx%d = %d\n", + DEST_REG, + SRC1_REG, + SRC2_REG, + DSPregs[DEST_REG].lower.i); + break; + + case 3: /* cfneg64 */ + mv_setReg64int (DEST_REG, -mv_getReg64int (SRC1_REG)); + printfdbg ("cfneg64 mvdx%d = -mvdx%d = %lld\n", + DEST_REG, + SRC1_REG, + SRC2_REG, + mv_getReg64int (DEST_REG)); + break; + + case 4: /* cfadd32 */ + DSPregs[DEST_REG].lower.i = DSPregs[SRC1_REG].lower.i + + DSPregs[SRC2_REG].lower.i; + printfdbg ("cfadd32 mvfx%d = mvfx%d + mvfx%d = %d\n", + DEST_REG, + SRC1_REG, + SRC2_REG, + DSPregs[DEST_REG].lower.i); + break; + + case 5: /* cfadd64 */ + mv_setReg64int (DEST_REG, + mv_getReg64int (SRC1_REG) + + mv_getReg64int (SRC2_REG)); + printfdbg ("cfadd64 mvdx%d = mvdx%d + mvdx%d = %lld\n", + DEST_REG, + SRC1_REG, + SRC2_REG, + mv_getReg64int (DEST_REG)); + break; + + case 6: /* cfsub32 */ + DSPregs[DEST_REG].lower.i = DSPregs[SRC1_REG].lower.i + - DSPregs[SRC2_REG].lower.i; + printfdbg ("cfsub32 mvfx%d = mvfx%d - mvfx%d = %d\n", + DEST_REG, + SRC1_REG, + SRC2_REG, + DSPregs[DEST_REG].lower.i); + break; + + case 7: /* cfsub64 */ + mv_setReg64int (DEST_REG, + mv_getReg64int (SRC1_REG) + - mv_getReg64int (SRC2_REG)); + printfdbg ("cfsub64 mvdx%d = mvdx%d - mvdx%d = %d\n", + DEST_REG, + SRC1_REG, + SRC2_REG, + mv_getReg64int (DEST_REG)); + break; + } + break; + + default: + fprintf (stderr, "unknown opcode in DSPCDP5 0x%x\n", instr); + cirrus_not_implemented ("unknown"); + break; + } + + return ARMul_DONE; +} + +unsigned +DSPCDP6 (ARMul_State * state, + unsigned type, + ARMword instr) +{ + int opcode2; + + opcode2 = BITS (5,7); + + switch (BITS (20,21)) + { + case 0: + /* cfmadd32 */ + cirrus_not_implemented ("cfmadd32"); + break; + + case 1: + /* cfmsub32 */ + cirrus_not_implemented ("cfmsub32"); + break; + + case 2: + /* cfmadda32 */ + cirrus_not_implemented ("cfmadda32"); + break; + + case 3: + /* cfmsuba32 */ + cirrus_not_implemented ("cfmsuba32"); + break; + + default: + fprintf (stderr, "unknown opcode in DSPCDP6 0x%x\n", instr); + } + + return ARMul_DONE; +} + +/* Conversion functions. + + 32-bit integers are stored in the LOWER half of a 64-bit physical + register. + + Single precision floats are stored in the UPPER half of a 64-bit + physical register. */ + +static double +mv_getRegDouble (int regnum) +{ + reg_conv.ints[lsw_float_index] = DSPregs[regnum].upper.i; + reg_conv.ints[msw_float_index] = DSPregs[regnum].lower.i; + return reg_conv.d; +} + +static void +mv_setRegDouble (int regnum, double val) +{ + reg_conv.d = val; + DSPregs[regnum].upper.i = reg_conv.ints[lsw_float_index]; + DSPregs[regnum].lower.i = reg_conv.ints[msw_float_index]; +} + +static long long +mv_getReg64int (int regnum) +{ + reg_conv.ints[lsw_int_index] = DSPregs[regnum].lower.i; + reg_conv.ints[msw_int_index] = DSPregs[regnum].upper.i; + return reg_conv.ll; +} + +static void +mv_setReg64int (int regnum, long long val) +{ + reg_conv.ll = val; + DSPregs[regnum].lower.i = reg_conv.ints[lsw_int_index]; + DSPregs[regnum].upper.i = reg_conv.ints[msw_int_index]; +} + +/* Compute LSW in a double and a long long. */ + +void +mv_compute_host_endianness (ARMul_State * state) +{ + static union + { + long long ll; + long ints[2]; + long i; + double d; + float floats[2]; + float f; + } conv; + + /* Calculate where's the LSW in a 64bit int. */ + conv.ll = 45; + + if (conv.ints[0] == 0) + { + msw_int_index = 0; + lsw_int_index = 1; + } + else + { + assert (conv.ints[1] == 0); + msw_int_index = 1; + lsw_int_index = 0; + } + + /* Calculate where's the LSW in a double. */ + conv.d = 3.0; + + if (conv.ints[0] == 0) + { + msw_float_index = 0; + lsw_float_index = 1; + } + else + { + assert (conv.ints[1] == 0); + msw_float_index = 1; + lsw_float_index = 0; + } + + printfdbg ("lsw_int_index %d\n", lsw_int_index); + printfdbg ("lsw_float_index %d\n", lsw_float_index); +} diff --git a/sim/frv/ChangeLog b/sim/frv/ChangeLog new file mode 100644 index 0000000..68b33ec --- /dev/null +++ b/sim/frv/ChangeLog @@ -0,0 +1,2493 @@ +2003-11-24 Kevin Buettner + + * frv-sim.h (GR_REGNUM_MAX, FR_REGNUM_MAX, PC_REGNUM, SPR_REGNUM_MIN) + (SPR_REGNUM_MAX): Delete. + * frv.c (gdb/sim-frv.h): Include. + (frvbf_fetch_register, frvbf_store_register): Use register number + constants from gdb/sim-frv.h. Check availability of general + purpose and float registers. + +2003-11-03 Dave Brolley + + * cache.c (address_interference): Check for higher priority requests + in the same pipeline. + +2003-10-31 Dave Brolley + + * frv-sim.h (LR_REGNUM): Removed. + (SPR_REGNUM_MIN,SPR_REGNUM_MAX): New macros. + * frv.c (frvbf_fetch_register): Fetch SPR registers based on + SPR_REGNUM_MIN and SPR_REGNUM_MAX. Check whether SPRs are implemented. + Return 0 for an unimplemented register. Return the length of the data + for an implemented register. + (frvbf_store_register): Ditto. + +2003-10-30 Andrew Cagney + + * traps.c: Replace "struct symbol_cache_entry" with "struct + bfd_symbol". + +2003-10-10 Dave Brolley + + * cpu.h, sem.c: Regenerate. + +2003-10-06 Dave Brolley + + * profile-fr550.[ch]: New files. + * configure.in: Move frv handling to alphabetically correct placement. + * Makefile.in: Add fr550 support. + * frv-sim.h,frv.c,interrups.c,memory.c,mloop.in,pipeline.c, + profile.[ch],registers.c,traps.c: Add fr550 support. + * arch.c,arch.h,cpu.c,cpu.h,cpuall.h,model.h,decode.c,decode.h,sem.c: + Regenerate. + +2003-09-25 Dave Brolley + + * reset.c (frv_initialize): Call frv_register_control_init first. + +2003-09-24 Dave Brolley + + * profile.h (update_FR_ptime): New prototype. + (update_FRdouble_ptime): Ditto. + (update_SPR_ptime): Ditto. + (increase_ACC_busy): Ditto. + (enforce_full_acc_latency): Ditto. + (post_wait_for_SPR): Ditto. + * profile.c (update_FR_ptime): Moved here from profile-fr500.c. + (update_FRdouble_ptime): Ditto. + (update_SPR_ptime): New function. + (increase_ACC_busy): Ditto. + (enforce_full_acc_latency): Ditto. + (vliw_wait_for_fdiv_resource): Correct resource name. + (vliw_wait_for_fsqrt_resource): Ditto. + (post_wait_for_SPR): New function. + * profile-fr500.c (frvbf_model_fr500_u_commit): New function. + (frvbf_model_fr500_u_gr2fr): Pass out_FRk as output register to + adjust_float_register_busy. + (frvbf_model_fr500_u_gr_load): Record latency of SPR registers. + (frvbf_model_fr500_u_fr_load): Wait for and record latency of SPR + registers. + (frvbf_model_fr500_u_float_arith): Ditto. + (frvbf_model_fr500_u_float_dual_arith): Ditto. + (frvbf_model_fr500_u_float_div): Ditto. + (frvbf_model_fr500_u_float_sqrt): Ditto. + (frvbf_model_fr500_u_float_convert): Ditto. + (update_FR_ptime): Moved to profile.c + (update_FRdouble_ptime): Moved to profile.c + * profile-fr400.c (update_FR_ptime): Removed. Identical to functions + for other machines. + (update_FRdouble_ptime): Ditto. + * arch.h,cpu.h,sem.c,decode.[ch],model.c,sem.c: Regenerated. + +2003-09-12 Dave Brolley + + * registers.c (frv_check_spr_read_access): Check for access to + ACC4-ACC63 and ACCG4-ACCG63. + * profile.h (frv-desc.h): #include it. + (spr_busy): New member of FRV_PROFILE_STATE. + (spr_latency): Ditto. + (GNER_FOR_GR): New macro. + (FNER_FOR_FR): New maccro. + (update_SPR_latency): New function. + (vliw_wait_for_SPR): New function. + * profile.c (update_latencies): Update SPR latencies. + (update_target_latencies): Ditto. + (update_SPR_latency): New function. + (vliw_wait_for_SPR): New function. + * profile-fr500.c (frvbf_model_fr500_u_idiv): Record GNER latency. + (frvbf_model_fr500_u_trap): Removed unused variable, ps. + (frvbf_model_fr500_u_check): Ditto. + (frvbf_model_fr500_u_clrgr): New unit modeller for fr500. + (frvbf_model_fr500_u_clrfr): Ditto. + (frvbf_model_fr500_u_spr2gr): Wait for SPR. + (frvbf_model_fr500_u_gr2spr): Ditto. + * frv-sim.h (H_SPR_ACC4): New macro. + (H_SPR_ACCG4): New macro; + (H_SPR_ACC0): Removed. + (H_SPR_ACCG0): Removed. + * arch.h,model.c,sem[ch],decode.[ch]: Regenerated. + +2003-09-10 Dave Brolley + + * profile.c (slot_names): FM1 was listed twice. Changed first + instance to FM0. Added IALL, FMALL and FMLOW. + (print_parallel): Don't examine slots with no insns. + +2003-09-09 Dave Brolley + + * frv.c (do_media_average): Select machine using a switch. + +2003-09-08 Dave Brolley + + On behalf of Doug Evans + * Makefile.in (stamp-arch,stamp-cpu): Pass archfile to cgen. + Remove copying of .cpu file to cgen/cpu, no longer needed. + +2003-09-03 Dave Brolley + + * cpu.h, model.c, sem.c, decode.h, decode.c: Regenerated. + +2003-08-29 Dave Brolley + + * Makefile.in (stamp-arch): Copy frv.cpu from $(srcdir)../../cpu + temporarily when regenerating files. + (stamp-cpu): Ditto. + +2003-08-20 Micheal Snyder + + * All generated files: Regenerate. + +2001-10-11 Dave Brolley + + * cpu.h,decode.c,decode.h,sem.c: Regenerate. + +2001-10-09 Dave Brolley + + * traps.c (frv_rett): Halt if PSR.S and PSR.ET are both set or both + not set. + * reset.c (frv_hardware_reset): Invalidate both caches. + * registers.c: Update init, reset and read-only masks for all registers + on all machines. + * profile.h (cur_gr_complex): New field of FRV_PROFILE_STATE + (prev_gr_complex): New field of FRV_PROFILE_STATE + (set_use_is_gr_complex): New function. + (set_use_not_gr_complex): New function. + (use_is_gr_complex): New function. + (decrease_GR_busy): New function. + * profile.c (reset_gr_flags): New function. + (reset_cc_flags): New function. + (set_use_is_gr_complex): New function. + (set_use_not_gr_complex): New function. + (use_is_gr_complex): New function. + (update_latencies): Reset gr and cc flags when latency reaches 0. + (decrease_GR_busy): New function. + * profile-fr400.h (fr500_reset_acc_flags): Removed. + (fr500_reset_cc_flags): New function. + * profile-fr500.c (frvbf_model_fr400_u_*): Reflect latencies from fr500 + LSI version 1.41. + * profile-fr400.h (fr400_reset_gr_flags): New function. + (fr400_reset_fr_flags): New function. + (fr400_reset_acc_flags): New function. + * profile-fr400.c (set_use_not_media_p4): New function. + (set_use_not_media_p6): New function. + (set_acc_use_not_media_p2): New function. + (set_acc_use_not_media_p4): New function. + (fr400_reset_gr_flags): New function. + (fr400_reset_fr_flags): New function. + (fr400_reset_acc_flags): New function. + (frvbf_model_fr400_u_*): Reflect latencies from fr400 LSI version 1.1. + (frvbf_model_fr400_u_media_hilo): New function. + * pipeline.c (frv_vliw_setup_insn): Don't clear MSR0.MTT. + * memory.c (fr400_check_data_read_address): Check address range only + for double word loads. Don't check alignment here. + (fr400_check_readwrite_address): New function. + (fr500_check_readwrite_address): New function. + (check_readwrite_address): New function. + (fr500_check_insn_read_address): Correct address ranges. + (frvbf_read_mem_*): Check address range here. + (frv_address_forbidden): Removed. + (fr400_check_write_address): New function. + (check_write_address): New function. + (frvbf_write_mem_*): Don't check address range here. + (frvbf_mem_set_*): Check address range here. + * interrupts.c (frv_queue_data_access_error_interrupt): Now takes an + address as second argument. + (frv_queue_data_access_exception_interrupt): New function. + (frv_queue_illegal_instruction_interrupt): Generate fp_exception for + media insns on fr400. + (frv_queue_non_implemented_instruction_interrupt): Generate mp_exception + for media insns on fr400. + (frv_detect_insn_access_interrupts): Don't check for illegal addresses + of insns here. Check for MTRAP insn if PSR.EM is not set. + (frv_set_mp_exception_registers): Only set MSR0.MTT if it is not already + set. + (set_exception_status_registers): Do not always set EPCR. Set EAR for + data_acess_error only if not fr400. + * frv.c (do_media_average): New function. + (frvbf_media_average): New function. + (frvbf_insn_cache_invalidate): Check for illegal invocation. + (frvbf_data_cache_invalidate): Ditto. + (frvbf_data_cache_flush): Ditto. + * frv-sim.h (GET_FSR_QNE): New macro. + (frv_msr_mtt): Remove MTT_SEQUENCE_ERROR. + (GET_MSR_SRDAV): New macro. + (GET_MSR_RDAV): New macro. + (GET_MSR_RD): New macro. + (frv_queue_data_access_error_interrupt): Now takes an address as second + argument. + (frv_address_forbidden): Removed. + * cache.c (non_cache_access): Correct address ranges. Now takes cache + as first argument. + * arch.h,cpu.h,decode.c,decode.h,model.c,sem.c: Regenerate. + +2001-08-20 Dave Brolley + + * sim-main.h (_sim_cpu): New field 'elf_flags'. + * sim-if.c (sim_open): Extract the elf_flags from the input file and + save them with each cpu. + * mloop.in (main loop): Pass elf flags to frv_vliw_reset. Set + last_insn_p before executing the insn. + * cache.c (frv_cache_invalidate): Flush scache if this is the cpu's + insn cache. + (frv_cache_invalidate_all): Ditto. + +2001-08-20 Richard Sandiford + + * traps.c (syscall_read_mem): Flush the data cache before reading. + (syscall_write_mem): Flush the data cache before writing. + Invalidate both caches. + +2001-07-05 Ben Elliston + + * Makefile.in (stamp-arch): Use $(CGEN_CPU_DIR). + (stamp-cpu): Likewise. + +2001-05-23 Dave Brolley + + * profile-fr400.c (acc_use_is_media_p2): New function. + (frvbf_model_fr400_u_media_2): Account for latency of output + accumulators. + (frvbf_model_fr400_u_media_2_quad): Ditto. + (frvbf_model_fr400_u_media_2_acc): New function. + (frvbf_model_fr400_u_media_2_acc_dual): New function. + (frvbf_model_fr400_u_media_2_add_sub): New function. + (frvbf_model_fr400_u_media_2_add_sub_dual): New function. + (frvbf_model_fr400_u_media_3_dual): New function. + (frvbf_model_fr400_u_media_4_acc_dual): New function. + * arch.h,cpu.h,decode.c,decode.h,model.c,sem.c: Regenerate. + +2001-05-15 Dave Brolley + + * registers.c (fr400_spr): Enable write access to HSR0.CBM. + * profile.h (FRV_PROFILE_STATE): New field 'all_cache_entries'. + * profile.c (CACHE_QUEUE_ELEMENT): New 'all' field. + (request_cache_flush): Save 'all' argument. + (request_cache_invalidate): Save all_cache_entries from profile state + to 'all' field of the request. + (submit_cache_request): Pass the 'all' field of the request to + frv_cache_request_invalidate. + * frv.c (frv_insn_cache_invalidate): Add new 'all' parameter. Perform + operation even if HSR0.ICE is not set. + (frv_data_cache_invalidate): Add new 'all' parameter. Perform + operation even if HSR0.DCE is not set. + (frv_data_cache_flush): Ditto. + * frv-sim.h (frv_insn_cache_invalidate): Add new 'all' parameter. + (frv_data_cache_invalidate): Add new 'all' parameter. + (frv_data_cache_flush): Add new 'all' parameter. + * cache.h (FRV_CACHE_INVALIDATE_REQUEST): Add new 'all' field. + (frv_cache_request_invalidate): Add new 'all' parameter. + * cache.c (frv_cache_request_invalidate): Add new 'all' parameter. Save + its value in the invalidate request. + (address_interference): Accept the value '-1' for the address argument + to mean 'any address'. + (handle_req_invalidate): Handle request to invalidate all cache lines. + * cpu.h,decode.c,decode.h,model.c,sem.c: Regenerate. + +2001-05-14 Dave Brolley + + * profile.h (past_first_p): New field of profiling state. + (branch_penalty): Ditto. + (branch_hint): Ditto. + (update_branch_penalty): New function. + * profile.c (frvbf_model_insn_after): Reset past_first_p and + branch_address fields of the profiling state. + (frvbf_model_branch): New function. + (update_branch_penalty): New function. + * profile-fr500.c (frvbf_model_fr500_u_branch): Remove ICCi_3 and + FCCi_3 inputs. + (frvbf_model_fr500_u_trap): New function. + (frvbf_model_fr500_u_check): New function. + (frvbf_model_fr500_u_media_dual_htob): post-processing latency is 3 + cycles. + * profile-fr400.c (frvbf_model_fr400_u_branch): Set branch penalties + as documented in the fr400 LSI. Remove ICCi_3 and FCCi_3 inputs. + (frvbf_model_fr400_u_media_dual_expand): Check resource usage as + documented in teh fr400 LSI. + (frvbf_model_fr400_u_media_dual_htob): Ditto. + (frvbf_model_fr400_u_media_dual_unpack): Removed. + (frvbf_model_fr500_u_trap): New function. + (frvbf_model_fr500_u_check): New function. + * mloop.in (simulate_dual_insn_prefetch): New function. + (@cpu@_simulate_insn_prefetch): Call simulate_dual_insn_prefetch with + arguments for each machine type. + * arch.h,cpu.h,decode.c,decode.h,model.c,sem.c: Regenerate. + +2001-05-09 Dave Brolley + + * Makefile.in (profile.o): Add profile-fr400.h as a dependency. + (profile-fr400.o): New target. + * profile.c: New file. + * profile.h: New file. + * profile-fr400.c: New file. + * profile-fr400.h: New file. + * profile-fr500.c: New file. + * profile-fr500.h: New file. + * arch.h,cpu.h,decode.c,decode.h,model.c,sem.c: Regenerate. + +2001-05-02 Dave Brolley + + * sim-main.h (profile.h): #include it. + (CPU_PROFILE_STATE): New macro. + (profile_state): New frv specific cpu field. + * reset.c (frv_initialize): insn_fetch_address and branch_address now + part of global profiling state. + * Makefile.in (SIM_OBJS): Add profile.o and profile-fr500.o. + (SIM_EXTRA_DEPS): Add profile.h. + (registers.o): Correct name of source file. + (profile.o): New target. + (profile-fr500.o): New target. + * frv-sim.h: Move profile related data structures to profile.h. + * frv.c: Move fr500 specific functions to profile-fr500.c. + * cpu.h: Regenerated. + +2001-04-27 Dave Brolley + + * sim-main.h (CPU_PIPELINE): Renamed to CPU_VLIW. + * interrupts.c: Rename FRV_PIPELINE to FRV_VLIW. + Rename pipeline to vliw. Rename CPU_PIPELINE to CPU_VLIW. + Rename PIPE_* to UNIT_*. + (frv_queue_illegal_instruction_interrupt): Use + frv_is_float_insn and frv_is_media_insn. + (frv_queue_non_implemented_instruction_interrupt): Ditto. + (frv_detect_insn_access_interrupts): Ditto. + * frv.c: Rename FRV_PIPELINE to FRV_VLIW. Rename pipeline to vliw. + Rename CPU_PIPELINE to CPU_VLIW. Rename PIPE_* to UNIT_*. + * memory.c: Ditto. + * pipeline.c: Ditto. + * mloop.in: Ditto. + * frv-sim.h (frv_pipeline_setup_insn): Renamed to frv_vliw_setup_insn. + * cache.c: Rename PIPE_* to UNIT_*. + +2001-04-24 Dave Brolley + + * frv.c (frvbf_load_quad_GR): Delete have_data and hsr0. + (frvbf_load_quad_FRint): Ditto. + (frvbf_load_quad_CPR): Ditto. + * cache.c (frv_cache_init): Initialize cache for fr400 vs other + machines. + (bfd.h): #include it. + (non_cache_access): Update for revised fr500 and for fr400. + * registers.c (frv_spr): Don't reset PSR.PS. + (fr500_spr): Ditto. + (frv_reset_spr): Set PSR.PS to the former value of PSR.S. + +2001-04-23 Dave Brolley + + * traps.c (frv_core_signal): On fr400, generate data_access_error. + (frvbf_media_cr_not_aligned): On fr400, generate illegal_instruction. + (frvbf_media_acc_not_aligned): Ditto. + (frvbf_media_register_not_aligned): Ditto. + (frvbf_division_exception): Use GET_ISR_EDE. + * registers.c (frv_check_spr_read_access): New function. + (frv_check_spr_write_access): New function. + (frv_check_spr_access): Deleted. + (frv_check_register_access): On fr400, generate illegal_instruction. + * memory.c (fr400_check_data_read_address): New function. + (fr500_check_data_read_address): Ditto. + (check_data_read_address): Ditto. + (fr400_check_insn_read_address): Ditto. + (fr500_check_insn_read_address): Ditto. + (check_insn_read_address): Ditto. + (frvbf_read_mem_QI): Call check_data_read_access. + (frvbf_read_mem_UQI): Ditto. + (frvbf_read_mem_HI): Ditto. + (frvbf_read_mem_UHI): Ditto. + (frvbf_read_mem_SI): Ditto. + (frvbf_read_mem_DI): Ditto. + (frvbf_read_mem_DF): Ditto. + (frvbf_read_imem_USI): Call check_insn_read_access. + (frv_address_forbidden): Now takes cpu as first argument. Check based + on machine type. + (fr400_mem_address_unaligned): New function. + (fr500_mem_address_unaligned): Ditto. + (check_write_address): Ditto. + (frvbf_mem_set_QI): Call check_write_address. + (frvbf_mem_set_HI): Ditto. + (frvbf_mem_set_SI): Ditto. + (frvbf_mem_set_DI): Ditto. + (frvbf_mem_set_DF): Ditto. + (frvbf_mem_set_XI): Ditto. + * interrupts.c (bfd.h): #include it. + (frv_queue_data_access_error_interrupt): New function. + (frv_queue_instruction_access_error_interrupt): New function. + (frv_queue_instruction_access_exception_interrupt): New function. + (frv_queue_illegal_instruction_interrupt): No fp_exception on fr400. + (frv_queue_non_implemented_instruction_interrupt): Ditto. + (frv_detect_insn_access_interrupts): Reorder tests to match priority + from the LSI manual. + (set_isr_exception_fields): Accumulate dtt bits. + * frv.c (check_register_alignment): New function. + (check_fr_register_alignment): New function. + (check_memory_alignment): New function. + (frvbf_h_gr_double_get_handler): Call check_register_alignment. + (frvbf_h_gr_double_set_handler): Ditto. + (frvbf_h_cpr_double_get_handler): Ditto. + (frvbf_h_cpr_double_set_handler): Ditto. + (frvbf_h_gr_quad_set_handler): Ditto. + (frvbf_h_cpr_quad_set_handler): Ditto. + (frvbf_h_fr_double_get_handler): Call check_fr_register_alignment. + (frvbf_h_fr_double_set_handler): Ditto. + (frvbf_h_fr_quad_set_handler): Ditto. + (frvbf_h_spr_get_handler): Call frv_check_spr_read_access. + (frvbf_h_spr_set_handler): Call frv_check_spr_write_access. + (frvbf_load_quad_GR): Call check_memory_aligment. + (frvbf_load_quad_FRint): Ditto. + (frvbf_load_quad_CPR): Ditto. + (frvbf_store_quad_GR): Call check_memory_aligment and + check_register_alignment. + (frvbf_store_quad_FRint): Ditto. + (frvbf_store_quad_CPR): Ditto. + (frvbf_signed_integer_divide: Use GET_ISR_EDEM. + * frv-sim.h (H_SPR_ACC0): New macro. + (H_SPR_ACC63): New macro. + (H_SPR_ACCG0): New macro. + (H_SPR_ACCG63): New macro. + (frv_dtt): New enumerator. + (GET_ISR_EDE): Renamed from GET_ISR_EDEM. + (GET_ISR_DTT): New macro. + (frv_queue_data_access_error_interrupt): New function. + (frv_queue_instruction_access_error_interrupt): New function. + (frv_queue_instruction_access_exception_interrupt): New function. + (frv_address_forbidden): Now takes cpu as first argument. + * cpu.h: Regenerate. + +2001-04-10 Dave Brolley + + * registers.c (fr500_spr): Add new fields to fr500 PSR register. + (fr500_spr): Add STBAR and MMCR unimplemented registers for fr500. + (fr400_spr): Implement SPR registers for fr400. + (frv_register_control_init): Handle bfd_mach_fr400 properly. + * frv.c (spr_bpsr_get_handler): Mask field before shifting. + (spr_psr_get_handler): Ditto. + (spr_ccr_get_handler): Ditto. + (spr_cccr_get_handler): Ditto. + (frvbf_clear_accumulators): Only 4 accumulators on fr400. + * frv-sim.h: Update comment about MCCR_* macros. + * cpu.c,cpu.h: Regenerate. + +2001-04-05 Dave Brolley + + * cpu.h,decode.c,model.c,sem.c: Regenerate. + +2001-04-05 Dave Brolley + + * reset.c: Update copyright. + * registers.c (frv_register_control_init): Handle bfd_mach_fr400. + * frv.c (frvbf_model_fr400_u_exec): New function. + * Makefile.in (stamp-cpu): Add fr400 to list of machines. + * arch.c,arch.h,cpu.c,cpu.h,cpuall.h,model.h,decode.c,decode.h,sem.c: + Regenerate. + +2000-11-22 Dave Brolley + + * arch.c,arch.h,cpu.c,cpu.h,cpuall.h,model.h,decode.c,decode.h,sem.c: + Regenerate. + +2000-11-10 Dave Brolley + + * decode.c: Regenerate. + +2000-09-12 Dave Brolley + + * traps.c (frv_sim_engine_halt_hook): New function. + (frv_itrap): Caches now invalidated in sim_engine_halt via + SIM_ENGINE_HALT_HOOK. + (frv_break): Ditto. + * sim-main.h (frv_sim_engine_halt_hook): New function. + (SIM_ENGINE_HALT_HOOK): New macro. + (SIM_ENGINE_RESTART_HOOK): New macro. + * interrupts.c: Call to frv_term now done within sim_engine_halt via + SIM_ENGINE_HALT_HOOK. + +2000-09-08 Dave Brolley + + * traps.c (frv_itrap): Invalidate and flush the data and insn caches + respectively when stopping for a breakpoint. + (frv_break): Ditto. + * cache.h (frv_cache_invalidate_all): New function. + * cache.c (frv_cache_invalidate_all): New function. + +2000-09-05 Dave Brolley + + * traps.c (frv_break): If SIM_HAVE_BREAKPOINTS, call + sim_handle_breakpoint. Otherwise if environment != operating call + sim_engine_halt. Otherwise handle normally. + * interrupts.c (frv_queue_break_interrupt): Don't handle debugger + breakpoints here. Moved to frv_break in traps.c. + + * sem.c: Regenerate. + +2000-09-01 Dave Brolley + + * interrupts.c (frv_queue_break_interrupt): Call sim_handle_breakpoint + before queuing an interrupt in order to allow 'break' to be used as + the breakpoint insn. + +2000-08-29 Dave Brolley + + * traps.c (frv_itrap): Invalidate the insn cache at a breakpoint. + +2000-07-27 Dave Brolley + + * cpu.h,decode.c: Rebuild. + +2000-07-26 Dave Brolley + + * frv.c (spr_cccr_get_handler): Change CRx to CCx. + (spr_cccr_set_handler): Change CRx to CCx. + * cpu.h,decode.c,decode.h,model.c,sem.c: Rebuild. + +2000-07-24 Dave Brolley + + * sem.c: Regenerate. + * frv.c (frvbf_unsigned_integer_divide): Queue a write for the result. + Don't write it directly. + +Thu Jul 6 13:51:12 2000 Dave Brolley + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +2000-07-05 Ben Elliston + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +2000-06-28 Dave Brolley + + * cpu.h,decode.c,decode.h,model.c,sem.c: Rebuild. + +2000-06-21 Dave Brolley + + * pipeline.c: All code except frv_pipeline_setup_insn moved to + frv.opc. + * mloop.in (main loop): frv_pipeline_add_insn broken up into + frv_pipeline_add_insn and frv_pipeline_setup_insn. + * frv-sim.h: Move pipeline status code to frv.opc. + * model.c: Regenerate. + +2000-06-12 Dave Brolley + + * options.c (frv_option_handler): --profile-parallel implies + --profile-model. + * mloop.in (fetch_buffer): Removed. + (@cpu@_simulate_insn_prefetch): Monitoring of fetch buffer moved to + run_caches. Use cache directly if not counting cycles. Don't use + cache at all if not counting cycles and cache not enabled. + * frv.c (frv_insn_fetch_buffer): New global variable. + (run_caches): Monitor the status of insn prefetch requests. + * frv-sim.h (FRV_INSN_FETCH_BUFFER): New struct type. + (frv_insn_fetch_buffer): New global variable. + +2000-06-12 Dave Brolley + + * mloop.in (fetch_buffer): New static struct. + (@cpu@_simulate_insn_prefetch): Rewritten. + * cache.c (frv_cache_request_invalidate): Don't invalidate return + buffer. + (address_interference): Defer to any WAR request in either pipeline. + +2000-06-09 Dave Brolley + + * pipeline.c (insns_in_slot): New Array. + (frv_pipeline_add_insn): Call COUNT_INSNS_IN_SLOT. + * options.c (frv_options): Remove 'NONBLOCK' argument from data-cache + option. + (parse_cache_option): New function. + (frv_option_handler): Call parse_cache_option. + * frv.c (vliw_branch_taken): New variable. + (vliw_load_stall): New variable. + (handle_resource_wait): Update vliw_load_stall. + (frvbf_model_insn_before): Initialize vliw_branch_taken and + vliw_load_stall. + (frvbf_model_insn_after): Increment PROFILE_MODEL_LOAD_STALL_CYCLES. + (load_wait_for_FR): Update vliw_load_stall. + (load_wait_for_GR): Update vliw_load_stall. + (load_wait_for_FRdouble): Update vliw_load_stall. + (load_wait_for_GRdouble): Update vliw_load_stall. + (frvbf_model_fr500_u_branch): Count branches taken and not taken. + (slot_names): New static array. + (print_parallel): Now takes second argument 'verbose'. Print cycles per + VLIW insn and instructions per cycle. Also tabulate the number of insns + in each type of VLIW slot. + (frv_profile_info): Call print_parallel with new second argument. + * frv-sim.h (insn_in_slot): New array. + (COUNT_INSNS_IN_SLOT): New macro. + (INSNS_IN_SLOT): New macro. + * cache.c: Remove references to non_blocking_count. Remove references to + last_was_hit. Remove references to req_none. + (handle_req_store): Adjust statistics before requeuing the store + request. + (handle_req_WAR): Don't let the WAR request affect the cache statistics. + * cache.h: Remove references to non_blocking_count. Remove references to + last_was_hit. Remove references to req_none. + * model.c: Regenerate. + +2000-06-08 Dave Brolley + + * frv.c (request_complete): Copy load data from the correct return + buffer. + +2000-06-07 Dave Brolley + + * traps.c (frv_core_signal): Call frv_term before exiting. + (frv_itrap): Call frv_term before exiting. + (next_available_nesr): Make sure NECR is implemented before reading it. + (next_valid_nesr): Ditto. + (frvbf_check_non_excepting_load): Ditto. + (frvbf_clear_ne_flags): Ditto. + (frvbf_commit): Ditto. + (frvbf_check_recovering_store): Delay cache operation if 'model_insn'. + * sim-main.h (_sim_cpu): Add load_address, load_length, load_flag and + store_flag members. + (CPU_LOAD_ADDRESS): New macro. + (CPU_LOAD_LENGTH): New macro. + (CPU_LOAD_SIGNED): New macro. + (CPU_LOAD_LOCK): New macro. + * reset.c (frv_term): New function. + (frv_power_on_reset): Use SETMEMSI if the cache is not enabled. + (frv_hardware_reset): Use SETMEMSI if the cache is not enabled. + (frv_software_reset): Use SETMEMSI if the cache is not enabled. + * mloop.in (execute): Call FRV_COUNT_CYCLES to decide whether to model + the insn. Model the insn in two passes. One before and one after + execution. + (cache_reqno): new static variable. + (@cpu@_simulate_insn_prefetch): Model fetch latency by waiting for the + cache rather than assuming a fixed latency. + (xinit): Turn on PROFILE_MODEL_P before each vliw insn if the timer is + enabled so that modeling data is collected by cgen during execution. + (full-exec): Restore PROFILE_MODEL_P after each vliw insn. + * memory.c (data_non_cache_access): Removed. + (insn_non_cache_access): Removed. + (frvbf_read_mem_QI): Delay read operation if 'model_insn'. + (frvbf_read_mem_UQI): Delay read operation if 'model_insn'. + (frvbf_read_mem_HI): Delay read operation if 'model_insn'. + (frvbf_read_mem_UHI): Delay read operation if 'model_insn'. + (frvbf_read_mem_SI): Delay read operation if 'model_insn'. + (frvbf_read_mem_DI): Delay read operation if 'model_insn'. + (frvbf_read_mem_DF): Delay read operation if 'model_insn'. + (frvbf_read_imem_USI): Read the cache or ememory passively. + (frvbf_write_mem_QI): Don't check for non-cache access here. + (frvbf_write_mem_UQI): Call frvbf_write_mem_QI. + (frvbf_write_mem_HI): Don't check for non-cache access here. + (frvbf_write_mem_UHI): Call frvbf_write_mem_QI. + (frvbf_write_mem_SI): Don't check for non-cache access here. + (frvbf_write_mem_DI): Don't check for non-cache access here. + (frvbf_write_mem_DF): Don't check for non-cache access here. + (frvbf_mem_set_QI): Use cycle-accurate cache write if 'model_insn'. + (frvbf_mem_set_HI): Use cycle-accurate cache write if 'model_insn'. + (frvbf_mem_set_SI): Use cycle-accurate cache write if 'model_insn'. + (frvbf_mem_set_DI): Use cycle-accurate cache write if 'model_insn'. + (frvbf_mem_set_DF): Use cycle-accurate cache write if 'model_insn'. + (frvbf_mem_set_XI): Use cycle-accurate cache write if 'model_insn'. + * interrupts.c (check_reset): Read the cache and memory passively. + (frv_program_or_software_interrupt): Call frv_term before calling + sim_engine_halt. + * frv.c (all modeling functions): Break into two passes. One before + execuetion and one after. call load_wait_for_* for all GR and FR + registers. + (frvbf_load_quad_GR): Delay performing the load if 'model_insn'. + (frvbf_load_quad_FRint): Delay performing the load if 'model_insn'. + (frvbf_load_quad_CPR): Delay performing the load if 'model_insn'. + (frvbf_insn_cache_preload): Delay cache operation if 'model_insn'. + (frvbf_data_cache_preload): Delay cache operation if 'model_insn'. + (frvbf_insn_cache_unlock): Delay cache operation if 'model_insn'. + (frvbf_data_cache_unlock): Delay cache operation if 'model_insn'. + (frvbf_insn_cache_invalidate): Delay cache operation if 'model_insn'. + (frvbf_data_cache_invalidate): Delay cache operation if 'model_insn'. + (frvbf_data_cache_flush): Delay cache operation if 'model_insn'. + (model_insn): New global variable. + (fr_ptime): New array. + (cache_request): New enumeration. + (CACHE_QUEUE_ELEMENT): New struct type. + (CACHE_QUEUE_SIZE): New macro. + (cache_queue): New static struct. + (request_cache_load): New function. + (request_cache_flush): New function. + (request_cache_invalidate): New function. + (request_cache_preload): New function. + (request_cache_unlock): New function. + (submit_cache_request): New function. + (activate_cache_requests): New function. + (load_pending_for_register): New function. + (flush_pending_for_address): New function. + (remove_cache_queue_element): New function. + (copy_load_data): New function. + (request_complete): New function. + (run_caches): New function. + (frv_model_trace_wait_cycles): New function. + (wait_for_flush): New function. + (frvbf_model_insn_before): Insn prefect wait now modeled in + frvbf_simulate_insn_prefetch. Incremement vliw_insns here. Call + wait_for_flush. + (frvbf_model_insn_after): Call activate_cache_requests. Don't increment + vliw_insns here anymore. + (update_FR_latency_for_load): New function. + (update_FRdouble_latency_for_load): New function. + (update_FR_ptime): New function. + (update_FRdouble_ptime): New function. + (update_GR_latency_for_swap): New function. + (load_wait_for_GR): New function. + (load_wait_for_FR): New function. + (load_wait_for_GRdouble): New function. + (load_wait_for_FRdouble): New function. + (frvbf_model_fr500_u_ici): New function. + (frvbf_model_fr500_u_dci): New function. + (frvbf_model_fr500_u_dcf): New function. + (frvbf_model_fr500_u_icpl): New function. + (frvbf_model_fr500_u_dcpl): New function. + (frvbf_model_fr500_u_icul): New function. + (frvbf_model_fr500_u_dcul): New function. + * frv-sim.h (frv_term): New function. + (insn_non_cache_access): Removed. + (FRV_COUNT_CYCLES): New macro. + (frv_save_peofile_model_p): New global variable. + (model_insn): New enumerated global variable. + (frv_model_advance_cycles): New function. + (frv_model_trace_wait_cycles): New function. + * cache.h (FRV_CACHE_REQUEST_KIND): New enumeration. + (FRV_CACHE_WAR_REQUEST): New struct type. + (FRV_CACHE_STORE_REQUEST): New struct type. + (FRV_CACHE_INVALIDATE_REQUEST): New struct type. + (FRV_CACHE_PRELOAD_REQUEST): New struct type. + (FRV_CACHE_REQUEST): New struct type. + (FRV_CACHE_RETURN_BUFFER): New struct type. + (FRV_CACHE_FLUSH_STATUS): New struct type. + (FRV_CACHE_STATUS): New struct type. + (FRV_CACHE_STAGE): New struct type. + (FRV_CACHE_STAGES): New enumeration. + (FRV_CACHE_WAR): New struct type. + (FRV_CACHE_PIPELINE): New struct type. + (FRV_CACHE_ARS): New struct type. + (FRV_CACHE_STATISTICS): New struct type. + (FRV_CACHE): Add pipeline, statistics, BARS and NARS. + (CACHE_RETURN_DATA): 'return_buffer' is now within 'status'. + (CACHE_RETURN_DATA_ADDRESS): New macro. + (frv_cache_read): Now takes pipe index as second argument. + (frv_cache_enabled): New function. + (frv_cache_request_load): New function. + (frv_cache_request_store): New function. + (frv_cache_request_invalidate): New function. + (frv_cache_request_preload): New function. + (frv_cache_request_unlock): New function. + (frv_cache_run): New function. + (frv_cache_read_passive_SI): New function. + (frv_cache_data_in_buffer): New function. + (frv_cache_data_flushed): New function. + * cache.c (frv_cache_init): Initialize pipelines and xARS registers. + (frv_cache_enabled): New function. + (non_cache_access): New function. + (write_data_to_memory): Count write accesses for each mode. Write to + memory using sim_core_write_unaligned_1; + (read_data_from_memory): New function. + (fill_line_from_memory): Use read_data_from_memory. + (copy_line_to_return_buffer): New function. + (copy_memory_to_return_buffer): New function. + (set_return_buffer_reqno): New function. + (frv_cache_read): Now takes pipe index as second argument. Check for + non-cache access. + (frv_cache_preload): Check for non-cache access. + (frv_cache_unlock): Check for non-cache access. + (invalidate_return_buffer): New function. + (frv_cache_invalidate): Check for non-cache access. + (convert_slot_to_index): New function. + (FREE_CHAIN_SIZE): New macro. + (frv_cache_request_free_chain): New static variable. + (frv_store_request_free_chain): New static variable. + (allocate_new_cache_requests): New function. + (new_cache_request): New function. + (free_cache_request): New function. + (new_store_request): New function. + (pipeline_remove_request): New function. + (pipeline_add_request): New function. + (pipeline_requeue_request): New function. + (next_priority): New function. + (add_WAR_request): New function. + (pipeline_next_request): New function. + (pipeline_stage_request): New function. + (advance_pipelines): New function. + (frv_cache_request_load): New function. + (frv_cache_request_store): New function. + (frv_cache_request_invalidate): New function. + (frv_cache_request_preload): New function. + (frv_cache_request_unlock): New function. + (address_interference): New function. + (wait_for_WAR): New function. + (wait_in_WAR): New function. + (handle_req_load): New function. + (handle_req_preload): New function. + (handle_req_store): New function. + (handle_req_invalidate): New function. + (handle_req_unlock): New function. + (handle_req_WAR): New function. + (arbitrate_requests): New function. + (move_ARS_to_WAR): New function. + (decrease_latencies): New function. + (frv_cache_run): New function. + (frv_cache_read_passive_SI): New function. + (frv_cache_data_in_buffer): New function. + (frv_cache_data_flushed): New function. + * arch.h,decode.c,decode.h,model.c,sem.c: Rebuild. + +Wed May 24 14:40:34 2000 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +2000-05-19 Dave Brolley + + * traps.c (frv_rett): Check for exceptions in the order specified in the + architecture spec. Allow privileged_instruction interrrupt to be handled + normally. + * registers.c (frv_register_control_init): Handle bfd_mach_frvtomcat. + * frv.c (frvbf_signed_integer_divide): Use updated dtt to decide whether + to clear the NE flag. + (frvbf_model_tomcat_u_exec): New function. + * frv-sim.h (frvbf_division_exception): Now returns updated dtt. + * Makefile.in (stamp-cpu): Add 'tomcat' to 'mach' value. + * arch.c,arch.h,cpu.h,cpuall.h,model.h,decode.c,sem.c: Regenerate. + +2000-05-18 Dave Brolley + + * sim-if.c (elf-bfd.h): #include it. + (sim_open): Set machine amd architecture based on elf flags. + +2000-04-04 Dave Brolley + + * frv-sim.h (frv_h_psr_esr_set_handler): Removed. + Delete '#if 0' blocks. + * frv.c: Delete '#if 0' blocks. + (spr_psr_set_handler): Remove special handling for circular referencing of handlers for + PSR.S and PSR.ESR. + (frv_h_psr_esr_set_handler): Removed. + * interrupts.c: Delete '#if 0' blocks. + * memory.c: Delete '#if 0' blocks. + * cpu.c,cpu.h: Regenerate. + +2000-04-03 Dave Brolley + + * traps.c (frvbf_check_recovering_store): Invalidate data cache line + containing the target address. + (clear_nesr_neear): No longer takes hi_available and lo_available. + Remove bogus check for available GR registers. + (frvbf_clear_ne_flags): Update call to clear_nesr_neear. + (frvbf_commit): Update call to clear_nesr_neear. + * interrupts.c (next_available_esr): Removed. + (next_available_edr): Removed. + (next_available_fq): Removed. + * frv.c (frvbf_fetch_register): Remove "FIXME" comment. + (frvbf_store_register): Remove "FIXME" comment. + * frv-sim.h (UART_INCHAR_ADDR): Removed. + (UART_OUTCHAR_ADDR): Removed. + (UART_STATUS_ADDR): Removed. + (UART_INPUT_READY): Removed. + (UART_OUTPUT_READY): Removed. + (FRV_DEVICE_ADDR): Removed. + (FRV_DEVICE_LEN): Removed. + (SET_NESR): Call frvbf_force_update. + (SET_NEEAR): Call frvbf_force_update. + (SET_NE_FLAGS): Call frvbf_force_update. + +2000-03-30 Dave Brolley + + * configure: Regenerated. + +2000-03-30 Dave Brolley + + * registers.c (fr500_spr): Define ESR14-15 and EPCSR14-15 for fr500. + * memory.c (frvbf_write_mem_*): Save slot containing the insn + performing the write. + (frvbf_mem_set_*): Overwrite the slot information of the interrupt + queue element with the information in the interrupt state. + * interrupts.c (frv_queue_interrupt): Call frv_set_interrupt_queue_slot. + (frv_queue_fp_exception_interrupt): Initialize 'new_element'. + (frv_set_interrupt_queue_slot): New function. + (esr_for_data_access_exception): New function. + (set_edr_register): edr_index is now passed in. + (fq_for_exception): New function. + (set_fp_exception_registers): Call fq_for_exception. Interrupt queue + element now passed in. + (set_exception_status_registers): Obtain slot from interrupt queue + element. Call esr_for_data_access_exception. Use ESR14 + for data_store_error. Use ESR15 for data_access_error. Use EDR0. + (frv_save_data_written_for_interrupts): Save slot containing the insn + performing the write. + * frv-sim.h (struct frv_fp_exception_info): Use frv_fsr_traps and + frv_fsr_ftt. + (struct frv_interrupt_state): Add 'slot' field. + (frv_set_interrupt_queue_slot): New function. + (frv_set_write_queue_slot): New function. + +2000-03-24 Dave Brolley + + * mloop.in (_parallel_write_init): Initialize + frv_interrupt_state.imprecise_interrupt. + (_parallel_write_queued): After an imprecise interrupt, only perform + forced writes and floating point writes (for certain exceptions). + * interrupts.c (handle_interrupt): Set + frv_interrupt_state.imprecise_interrupt for writeback after an imprecise + interrupt. + (frv_process_interrupts): No need to clear f_ne_flags. + * frv.c (frvbf_signed_integer_divide): Queue writes to GR registers and + force them to happen even if there is an overflow exception. + (frvbf_force_update): New function. + * frv-sim.h (frvbf_force_update): New function. + (struct frv_interrupt_state): Add imprecise_interrupt. + (FRV_WRITE_QUEUE_FORCE_WRITE): New macro. + * sem.c: Regenerate. + +2000-03-23 Dave Brolley + + * traps.c (frv_rett): Queue FRV_ILLEGAL_INSTRUCTION directly. + * registers.c (frv_spr): MCIRL -> MCILR. + * interrupts.c (frv_queue_non_implemented_instruction_interrupt): + New function. + (frv_detect_insn_access_interrupts): + Call frv_queue_non_implemented_instruction_interrupt. + (frv_process_interrupts): Clear accumulated NE flags. + * frv.c (frvbf_media_cop): New function. + (frvbf_set_ne_index): Now takes (SIM_CPU *) as first argument. Clear + the NE flag of the given target register. + (frvbf_model_fr500_u_float_arith): Account for FRdouble registers. + (frvbf_model_fr500_u_float_dual_arith): Account for FRdouble registers. + (frvbf_model_fr500_u_float_dual_sqrt): New function. + (frvbf_model_fr500_u_float_convert): Account for FRdouble registers. + (frvbf_model_fr500_u_float_dual_convert): New function. + * frv-sim.h (frvbf_media_cop): New function. + (GET_FQ): Use H_SPR_FQST0. + (SET_FQ): Use H_SPR_FQST0. + (SET_FQ_OPC): Use J_SPR_FQOP0. + (GET_MSR_EMCI): New macro. + (frv_queue_non_implemented_instruction_interrupt): New function. + * arch.h,cpu.h,decode.c,decode.h,model.c,sem.c: Regenerate. + +2000-03-08 Dave Brolley + + * traps.c (frv_rett): Align new_pc. + * memory.c (frvbf_read_mem_HI): Align address. + (frvbf_read_mem_UHI): Align address. + (frvbf_read_mem_SI): Align address. + (frvbf_read_mem_DI): Align address. + (frvbf_read_mem_DF): Align address. + (frvbf_read_imem_USI): Align address. + (frvbf_mem_set_HI): Align address. + (frvbf_mem_set_SI): Align address. + (frvbf_mem_set_DI): Align address. + (frvbf_mem_set_DF): Align address. + (frvbf_mem_set_XI): Align address. + * registers.c (frv_spr): Initialize FSR0.NS to 1. + (fr500_spr): Initialize FSR0.NS to 1. + * interrupts.c (frv_queue_mem_address_not_aligned_interrupt): Check + whether the exception is masked. + * frv.c (frvbf_load_quad_GR): Align address. + (frvbf_store_quad_GR): Align address. + (frvbf_load_quad_FRint): Align address. + (frvbf_store_quad_FRint): Align address. + (frvbf_load_quad_CPR): Align address. + (frvbf_store_quad_CPR): Align address. + * frv-sim.h (GET_ISR_EMAM): New macro. + +2000-03-08 Dave Brolley + + * traps.c (frvbf_division_exception): Check for masked overflow and + set NE flags, if necessary. + (frvbf_check_recovering_store): Queue writes to the hardware. + (check_registers_available): Removed. + (which_registers_available): Call frv_{fr,gr}_registers_available. + (frvbf_clear_ne_flags): Call check_register_access. + (frvbf_commit): Call check_register_access. + * registers.h (frv_fr_registers_available): New function. + (frv_gr_registers_available): New function. + (frv_check_register_access): New function. + (frv_check_gr_access): New function. + (frv_check_fr_access): New function. + * registers.c (frv_spr): Correct initial value of ISR. + (fr500_spr): Correct initial value of ISR. + (frv_fr_registers_available): New function. + (frv_gr_registers_available): New function. + (frv_check_register_access): New function. + (frv_check_gr_access): New function. + (frv_check_fr_access): New function. + * interrupts.c (frv_queue_division_exception_interrupt): New function. + (set_isr_exception_fields): New function. + (set_exception_status_registers): Set ISR fields for division exception. + (frv_save_data_written_for_interrupts): Handle CGEN_FN_SF_WRITE. + * frv.c (frvbf_h_gr_get_handler): New function. + (frvbf_h_gr_set_handler): New function. + (frvbf_h_fr_get_handler): New function. + (frvbf_h_fr_set_handler): New function. + (frvbf_h_spr_get_handler): Remove special handling for ISR. + (frvbf_h_spr_set_handler): Remove special handling for ISR. + (spr_isr_get_handler): Removed. + (spr_isr_set_handler): Removed. + (frvbf_signed_integer_divide): New funciton. + (frvbf_unsigned_integer_divide): New funciton. + * frv-sim.h (frvbf_h_gr_get_handler): New function. + (frvbf_h_gr_set_handler): New function. + (frvbf_h_fr_get_handler): New function. + (frvbf_h_fr_set_handler): New function. + (frvbf_signed_integer_divide): New funciton. + (frvbf_unsigned_integer_divide): New funciton. + (frv_dtt): New enumeration. + (struct frv_interrupt_queue_element): Add dtt member. + (GET_ISR): New macro. + (SET_ISR): New macro. + (GET_ISR_EDEM): New macro. + (SET_ISR_DTT): New macro. + (SET_ISR_AEXC): New macro. + (frvbf_division_exception): Add 2 'int' arguments. + (frvbf_check_non_excepting_divide): Removed. + * cpu.c,cpu.h,decode.c,decode.h,model.c,sem.c: Regenerate. + +2000-02-29 Dave Brolley + + * traps.c (frv_itrap): Use GET_H_GR, SET_H_GR, GET_H_FR. + (frv_rett): Use hardware access macros. Write PSR as a whole. + (next_available_nesr): Check that NECR is valid. + (next_valid_nesr): Check that NECR is valid. + (frvbf_check_non_excepting_load): User new NECR access macros. Don't + call hardware access functions. Use cover macros. + (check_registers_available): New function. + (clear_nesr_near): Check register availability. + (clear_ne_flags): Check register availability. + (frvbf_clear_ne_flags): Check register availability. + (frvbf_commit): Check register availability. + (which_registers_available): New function. + * sim-main.h (registers.h): #include it. + (register_control): New cpu field. + (CPU_REGISTER_CONTROL): New macro. + * reset.c (frv_initialize): Set HSR0 fields for cache here. + (frv_power_on_reset): Initialize SPR registers and RSTR. + (frv_hardware_reset): Initialize SPR registers and RSTR. + (frv_software_reset): Reset SPR registers and RSTR. + * options.c (frv_option_handler): Don't set HSR0 fields for cache here. + Call frv_cache_init. + * mloop.in (main loop): Check for insn access interrupts before + executing the insn. + * interrupts.c (frv_queue_external_interrupt): Use GET_H_PSR_ET. + (frv_detect_insn_access_interrupts): Don't call hardware access + functions directly. Use cover macros. + (check_reset): Don't reset RSTR here. + (next_available_esr): ESFR -> ESFR_FLAG. + (next_available_edr): ESFR -> ESFR_FLAG. + (clear_exception_status_registers): Use GET_ESFR and SET_ESFR. + ESFR -> ESFR_FLAG. + (frv_break_interrupt): Don't call hardware access functions directly. + Use cover macros. + (frv_program_or_software_interrupt): Ditto. + (frv_external_interrupt): Ditto. + * frv.c (frvbf_fetch_register): Don't call 'get' functions directly. + (frvbf_store_register): Don't call 'set' functions directly. + (frvbf_h_gr_double_get_handler): Use GET_H_GR. + (frvbf_h_gr_double_set_handler): Use SET_H_GR. + (frvbf_h_fr_double_get_handler): Use GET_H_FR. + (frvbf_h_fr_double_set_handler): Use SET_H_FR. + (frvbf_h_fr_int_get_handler): Use GET_H_FR. + (frvbf_h_fr_int_set_handler): Use SET_H_FR. + (frvbf_h_cpr_double_get_handler): Use GET_H_CPR. + (frvbf_h_cpr_double_set_handler): Use SET_H_CPR. + (frvbf_h_gr_quad_set_handler): Use SET_H_GR. + (frvbf_h_fr_quad_set_handler): Use SET_H_FR. + (frvbf_h_spr_get_handler): Check SPR access. Call renamed functions. + Support shadow registers. + (frvbf_h_spr_set_handler): Check SPR access. Call renamed functions. + Support shadow registers. + (spr_psr_get_handler): Renamed from frvbf_h_psr_get_handler. + (spr_psr_set_handler): Renamed from frvbf_h_psr_set_handler. + (spr_tbr_get_handler): Renamed from frvbf_h_tbr_get_handler. + (spr_tbr_set_handler): Renamed from frvbf_h_tbr_set_handler. + (spr_bpsr_get_handler): Renamed from frvbf_h_bpsr_get_handler. + (spr_bpsr_set_handler): Renamed from frvbf_h_bpsr_set_handler. + (spr_ccr_get_handler): Renamed from frvbf_h_ccr_get_handler. + (spr_ccr_set_handler): Renamed from frvbf_h_ccr_set_handler. + (spr_lr_get_handler): Renamed from frvbf_h_lr_get_handler. + (spr_lr_set_handler): Renamed from frvbf_h_lr_set_handler. + (spr_cccr_get_handler): Renamed from frvbf_h_cccr_get_handler. + (spr_cccr_set_handler): Renamed from frvbf_h_cccr_set_handler. + (spr_isr_get_handler): Renamed from frvbf_h_isr_get_handler. + (spr_isr_set_handler): Renamed from frvbf_h_isr_set_handler. + (spr_sr_get_handler): Renamed from frvbf_h_sr_get_handler. + (spr_sr_set_handler): Renamed from frvbf_h_sr_set_handler. + (frvbf_h_psr_esr_set_handler): Update to conform to FRV architecture + version 1.3a. + (spr_ccr_get_handler): Don't reference the hardware directly. + (spr_ccr_set_handler): Don't reference the hardware directly. + (spr_cccr_get_handler): Don't reference the hardware directly. + (spr_cccr_set_handler): Don't reference the hardware directly. + (spr_sr_get_handler): New function. + (spr_sr_set_handler): New function. + (frvbf_switch_supervisor_user_context): Temporarily switch to + supervisor mode. + (frvbf_store_quad_GR): Don't call handler directly. + (frvbf_store_quad_FRint): Don't call handler directly. + (frvbf_store_quad_CPR): Don't call handler directly. + (frvbf_clear_all_accumulators): Removed. + (frvbf_clear_accumulators): New function. + (frvbf_model_fr500_u_media): Expand busy_adjustment to 8 members. + Account for in_ACCGi and out_ACCGk. + * frv-sim.h (RSTR_HARDWARE_RESET): New macro. + (RSTR_SOFTWARE_RESET): New macro. + (spr_psr_get_handler): Renamed from frvbf_h_psr_get_handler. + (spr_psr_set_handler): Renamed from frvbf_h_psr_set_handler. + (spr_tbr_get_handler): Renamed from frvbf_h_tbr_get_handler. + (spr_tbr_set_handler): Renamed from frvbf_h_tbr_set_handler. + (spr_bpsr_get_handler): Renamed from frvbf_h_bpsr_get_handler. + (spr_bpsr_set_handler): Renamed from frvbf_h_bpsr_set_handler. + (spr_ccr_get_handler): Renamed from frvbf_h_ccr_get_handler. + (spr_ccr_set_handler): Renamed from frvbf_h_ccr_set_handler. + (spr_lr_get_handler): Renamed from frvbf_h_lr_get_handler. + (spr_lr_set_handler): Renamed from frvbf_h_lr_set_handler. + (spr_cccr_get_handler): Renamed from frvbf_h_cccr_get_handler. + (spr_cccr_set_handler): Renamed from frvbf_h_cccr_set_handler. + (spr_isr_get_handler): Renamed from frvbf_h_isr_get_handler. + (spr_isr_set_handler): Renamed from frvbf_h_isr_set_handler. + (spr_sr_get_handler): Renamed from frvbf_h_sr_get_handler. + (spr_sr_set_handler): Renamed from frvbf_h_sr_set_handler. + (frvbf_clear_all_accumulators): Removed. + (frvbf_clear_accumulators): New function. + (GET_HSR0): Use GET_H_SPR. + (SET_HSR0): Use SET_H_SPR. + (CLEAR_HSR0_ICE): New macro. + (CLEAR_HSR0_DCE): New macro. + (GET_IHSR8): Use GET_H_SPR. + (GET_PSR): New macro. + (SET_PSR_ET): New macro. + (GET_PSR_PS): New macro. + (SET_PSR_S): New macro. + (GET_ESFR): Changed to reference entire register. + (SET_ESFR): Changed to reference entire register. + (GET_ESFR_FLAG): New macro. + (SET_ESFR_FLAG): New macro. + (NECR_ELOS): Removed. + (NECR_NEN): Removed. + (NECR_VALID): Removed. + (GET_NECR): New macro. + (GET_NECR_ELOS): New macro. + (GET_NECR_NEN): New macro. + (GET_NECR_VALID): New macro. + (NESR_RANGE): Removed. + (GET_NESR): Use GET_H_SPR. + (GET_NE_FLAGS): Use GET_H_SPR. + * cache.h (CACHE_INITIALIZED): New macro. + * Makefile.in (SIM_OBJS): Add registers.o. + (SIM_EXTRA_DEPS): Add registers.h. + (registers.o): New target. + * cpu.c,cpu.h,decode.c,decode.h,model.c,sem.c: Regenerate. + +2000-02-17 Dave Brolley + + * interrupts.c (frv_interrupt_table): Update priority order and handler + offsets to conform to the architecture version 1.3a. + * frv-sim.h (frv_interrupt_kind): Update priority order to conform + to the architecture version 1.3a. + +2000-02-17 Dave Brolley + + * interrupts.c (frv_interrupt_table): Update priority order and handler + offsets to conform to the latest specifications. + (frv_queue_interrupt): Correct comment. Identical interrupts can be + queued. New variable 'iclass' used to test for external interrupts. + * frv-sim.h (frv_interrupt_kind): Update priority order to conform + to the latest specifications. + +2000-01-20 Dave Brolley + + * sim-if.c (sim_open): Move frv-specific initialization to + frv_initialize in reset.c. + * interrupts.c (check_reset): Use RSTR_ADDRESS. Check and reset RSTR + status bits for hardware vs software reset. + * reset.c: New file. + * frv-sim.h (frv_initialize): New function. + (frv_power_on_reset): New function. + (frv_hardware_reset): New function. + (frv_software_reset): New function. + (RSTR_ADDRESS): New macro. + (RSTR_INITIAL_VALUE): New macro. + (GET_RSTR_HR): New macro. + (GET_RSTR_SR): New macro. + (SET_RSTR_H): New macro. + (SET_RSTR_S): New macro. + (CLEAR_RSTR_P): New macro. + (CLEAR_RSTR_H): New macro. + (CLEAR_RSTR_S): New macro. + (CLEAR_RSTR_HR): New macro. + (CLEAR_RSTR_SR): New macro. + +2000-01-03 Dave Brolley + + * mloop.in (execute): Only call modeling function if the pointer is not + NULL. + * frv.c (frvbf_model_insn_after): Only access FR500_MODEL_DATA for + fr500. + +2000-01-03 Dave Brolley + + * options.c (OPTION_FRV_MEMORY_LATENCY): New enumerator. + (frv_options): Add --memory-latency. + (frv_option_handler): Handle FRV_OPTION_MEMORY_LATENCY. + * mloop.in (@cpu@_simulate_insn_prefetch): Use cache memory_latency. + * frv.c (SET_ACC_USE_IS_MEDIA_P1): operate on d->curr_acc_p1 + (SET_ACC_USE_NOT_MEDIA_P1): operate on d->curr_acc_p1 + (SET_ACC_USE_IS_MEDIA_P2): operate on d->curr_acc_p1 + (SET_ACC_USE_NOT_MEDIA_P2): operate on d->curr_acc_p1 + (update_latencies): Only clear usage flags if the register has no + target latency. + (frvbf_model_insn_before): Update cur_acc_p1 and cur_acc_p2. Use | (or) + not |= (or assgnment). + (frvbf_model_insn_after): Print post processing wait for all insns. + Update prev_acc_p1 and prev_acc_p2. + (frvbf_model_fr500_u_gr_load_store): Use cache memory_latency. + (frvbf_model_fr500_u_fr_load_store): Use cache memory_latency. + (frvbf_model_fr500_u_swap): Use cache memory_latency. + (frvbf_model_fr500_u_media): Use busy_adjustment[4] for out_ACC40Sk. + (frvbf_model_fr500_u_media): Use busy_adjustment[5] for out_ACC40Uk. + (frvbf_model_fr500_u_media_quad_arith): New function. + (frvbf_model_fr500_u_media_dual_mul): New function. + (frvbf_model_fr500_u_media_quad_mul): New function. + (frvbf_model_fr500_u_media_quad_complex): New function. + (frvbf_model_fr500_u_media_dual_expand): New function. + (frvbf_model_fr500_u_media_dual_unpack): New function. + (frvbf_model_fr500_u_media_dual_btoh): New function. + (frvbf_model_fr500_u_media_dual_htob): New function. + (frvbf_model_fr500_u_media_dual_btohe): New function. + (frv_ref_SI): New function. + * cache.h (FRV_CACHE): Add memory_latency field. + * cache.c (frv_cache_init): Initialize memory_latency. + * arch.h,cpu.h,decode.c,decode.h,model.c,sem.c: Regenerate. + +1999-12-17 Dave Brolley + + * sim-if.c (sim_open): Initialize insn prefetch and reset register. + * options.c (OPTIONS_FRV_PROFILE_CACHE): New enumeration. + (OPTIONS_FRV_PROFILE_PARALLEL): New enumeration. + (OPTIONS_FRV_TIMER): New enumeration. + (frv_options): Add --profile-cache, --profile-parallel, --timer. + (frv_option_handler): Override common implementation of -p. Handle + --profile-cache, --profile-parallel, --timer. + * mloop.in (execute): Call profiling functions if the timer interrupt + is enabled. + (@cpu@_simulate_insn_prefetch): New function. + (main loop): Call @cpu@_simulate_insn_prefetch. + * interrupts.c (frv_queue_interrupt): Don't queue two external + interrupts of the same priority. + (frv_queue_external_interrupt): New function. + (frv_external_interrupt): New function. + (handle_interrupt): Handle external interrupts. + (check_reset): New function. + (frv_process_interrupts): Call check_reset. + * frv.c: Include "bfd.h" + (frvbf_h_psr_get_handler): Set the PIL field. + (frvbf_h_psr_set_handler): Get the PIL field. + (DUAL_REG): New macro. + (DUAL_DOUBLE): New macro. + (SET_USE_IS_FPOP): New macro. + (SET_USE_NOT_FPOP): New macro. + (USE_IS_FPOP): New macro. + (SET_USE_IS_MEDIA): New macro. + (SET_USE_NOT_MEDIA): New macro. + (USE_IS_MEDIA_P1): New macro. + (SET_USE_IS_MEDIA_P1): New macro. + (SET_USE_NOT_MEDIA_P1): New macro. + (SET_USE_IS_MEDIA_P2): New macro. + (SET_USE_NOT_MEDIA_P2): New macro. + (USE_IS_MEDIA_P2): New macro. + (SET_ACC_USE_IS_MEDIA_P1): New macro. + (SET_ACC_USE_NOT_MEDIA_P1): New macro. + (ACC_USE_IS_MEDIA_P1): New macro. + (SET_ACC_USE_IS_MEDIA_P2): New macro. + (SET_ACC_USE_NOT_MEDIA_P2): New macro. + (ACC_USE_IS_MEDIA_P2): New macro. + (RESOURCE_IDIV): New macro. + (RESOURCE_FDIV): New macro. + (RESOURCE_SQRT): New macro. + (fr_busy_adjust): New array. + (acc_busy_adjust): New array. + (apply_latency_adjustments): New function. + (update_latencies): New function. + (handle_wait_cycles): New function. + (handle_resource_wait): New function. + (update_target_latencies): New function. + (frvbf_model_insn_before): Add resource latency to cycle counts. + (frvbf_model_insn_after): Add resource latency to cycle counts. + (update_GR_latency): New function. + (update_GRdouble_latency): New function. + (update_FR_latency): New function. + (update_FRdouble_latency): New function. + (decrease_ACC_busy): New function. + (decrease_FR_busy): New function. + (increase_FR_busy): New function. + (update_ACC_latency): New function. + (update_CCR_latency): New function. + (update_idiv_resource_latency): New function. + (update_fdiv_resource_latency): New function. + (update_fsqrt_resource_latency): New function. + (vliw_wait_for_GR): New function. + (vliw_wait_for_GRdouble): New function. + (vliw_wait_for_FR): New function. + (vliw_wait_for_FRdouble): New function. + (vliw_wait_for_CCR): New function. + (vliw_wait_for_ACC): New function. + (vliw_wait_for_idiv_resource): New function. + (vliw_wait_for_fdiv_resource): New function. + (vliw_wait_for_fsqrt_resource): New function. + (enforce_full_fr_latency): New function. + (frvbf_model_fr500_u_exec): New function. + (frvbf_model_fr500_u_integer): New function. + (frvbf_model_fr500_u_imul): New function. + (frvbf_model_fr500_u_idiv): New function. + (frvbf_model_fr500_u_branch): New function. + (frvbf_model_fr500_u_set_hilo): New function. + (frvbf_model_fr500_u_gr_load_store): New function. + (frvbf_model_fr500_u_fr_load_store): New function. + (frvbf_model_fr500_u_swap): New function. + (frvbf_model_fr500_u_fr2fr): New function. + (frvbf_model_fr500_u_fr2gr): New function. + (frvbf_model_fr500_u_spr2gr): New function. + (frvbf_model_fr500_u_gr2fr): New function. + (frvbf_model_fr500_u_gr2spr): New function. + (post_wait_for_FR): New function. + (post_wait_for_FRdouble): New function. + (post_wait_for_ACC): New function. + (post_wait_for_CCR): New function. + (post_wait_for_fdiv): New function. + (post_wait_for_fsqrt): New function. + (adjust_float_register_busy): New function. + (adjust_double_register_busy): New function. + (restore_float_register_busy): New function. + (restore_double_register_busy): New function. + (frvbf_model_fr500_u_float_arith): New function. + (frvbf_model_fr500_u_float_dual_arith): New function. + (frvbf_model_fr500_u_float_div): New function. + (frvbf_model_fr500_u_float_sqrt): New function. + (frvbf_model_fr500_u_float_compare): New function. + (frvbf_model_fr500_u_float_dual_compare): New function. + (frvbf_model_fr500_u_float_convert): New function. + (frvbf_model_fr500_u_media): New function. + (frvbf_model_fr500_u_barrier): New function. + (frvbf_model_fr500_u_membar): New function. + * frv-sim.h (LEUINT): New macro. + (GET_HSR0_SA): New macro. + (struct frv_interrupt_timer): New struct. + (struct frv_interrupt_state): Add timer fiield. + (frv_queue_external_interrupt): New function. + (frv_external_interrupt): New function. + (frv_profile_info): New function. + (PROFILE_CACHE_IDX): New enumerator. + (PROFILE_PARALLEL_IDX): New enumerator. + (PROFILE_cache): New macro. + (PROFILE_parallel): New macro. + (WITH_PROFILE_CACHE_P): New macro. + (WITH_PROFILE_PARALLEL_P): New macro. + * cache.h (FRV_CACHE): Add last_was_hit field. + * cache.c (get_tag): Use new last_was_hit field. + (frv_cache_read): Ditto. + (frv_cache_write): Ditto. + * arch.h,cpu.c,cpu.h,decode.c,decode.h,model.c,sem.c: Regenerate. + +1999-12-13 Dave Brolley + + * frv.c (frvbf_h_spr_set_handler): Handle accumulator guards. + (frvbf_clear_all_accumulators): Pass frvbf_h_acc40S_set to + sim_queue_fn_di_write. + (frvbf_media_cut_ss): New function. + * frv-sim.h (frvbf_media_cut_ss): New function. + * cpu.c,cpu.h,decode.c,decode.h,model.c,sem.c: Regenerate. + +1999-12-13 Dave Brolley + + * pipeline.c (check_insn_major_constraints): F-4, F-8 and M-8 have + no constraints. + * interrupts.c (frv_queue_illegal_instruction_interrupt): Use + FRV_IS_FLOAT_INSN and FRV_IS_MEDIA_INSN. + (frv_detect_insn_access_interrupts): Use FRV_IS_FLOAT_INSN and + FRV_IS_MEDIA_INSN. + * frv.c (frvbf_model_simple_u_exec): New function. + * frv-sim.h (FRV_IS_FLOAT_INSN): Range includes F-8. + (FRV_IS_MEDIA_INSN): Range includes M-8. + + * Makefile.in (stamp-cpu): add 'simple' to the list of machines. + * arch.c,arch.h,cpu.h,cpuall.h,decode.c,decode.h,model.c,sem.c: + Regenerate. + +1999-12-10 Dave Brolley + + * traps.c (check_registers_available): New function. + (clear_ne_flags): Generate register_exception if register(s) not + available. + (frvbf_commit): Generate register_exception if register(s) not + available. + * interrupts.c (frv_program_or_software_interrupt): No need to copy + GR4-GR7 to SR0-SR4. + * frv.c (frvbf_h_psr_set_handler): Special handling for PSR.S and + PSR.ESR. + (frvbf_h_psr_s_set_handler): New function. + (frvbf_h_psr_esr_set_handler): New function. + (frvbf_switch_supervisor_user_context): New function. + (frvbf_scan_result): Reflect latest ISA. + * frv-sim.h (frvbf_h_psr_s_set_handler): New function. + (frvbf_h_psr_esr_set_handler): New function. + (frvbf_switch_supervisor_user_context): New function. + (GET_HSR0_FRN): New Macro. + (GET_HSR0_GRN): New Macro. + (GET_HSR0_FRHE): New Macro. + (GET_HSR0_FRLE): New Macro. + (GET_HSR0_GRHE): New Macro. + (GET_HSR0_GRLE): New Macro. + (frv_ec): New value for FRV_EC_COMMIT_EXCEPTION. + (GET_ESFR): New bit ordering. + (SET_ESFR): New bit ordering. + * cpu.c,cpu.h,decode.c,decode.h,model.c,sem.c: Regenerate. + +1999-12-10 Michael Meissner + + * Makefile.in (sim-if.o): Add eng.h dependency. + +1999-12-09 Dave Brolley + + * mloop.in (execute): Pass sc->first_insn_p to @cpu@_model_insn_before. + Pass sc->last_insn_p to @cpu@_model_insn_before. + (main loop): Compute sc->first_insn_p. + * frv.c (frvbf_model_insn_before): Set state variables. + (frvbf_model_insn_after): Count basic cycles. Set state variables. + (frvbf_model_fr500_u_integer): Remove. + * arch.h,cpu.h,decode.h,model.c: Regenerate. + +1999-12-07 Dave Brolley + + * sim-main.h (cache.h): Include it. + (insn_cache): New member. + (data_cache): New member. + (CPU_INSN_CACHE): New macro. + (CPU_DATA_CACHE): New macro. + * sim-if.c (WANT_CPU): New macro. + (WANT_CPU_FRVBF): New macro. + (sim_open): Call sim_add_option_table. Call frv_cache_init for the + data and insn caches for each cpu. + (sim_close): Call frv_cache_term for the insn and data caches of each + cpu. + * mloop.in (extract): Read insn from the cache. + (main loop): Access the insn cache in order to maintain stats. + * memory.c (data_non_cache_access): New function. + (insn_non_cache_access): New function. + (frvbf_read_mem_QI): Attempt to read from the cache first. + (frvbf_read_mem_UQI): Ditto. + (frvbf_read_mem_HI): Ditto. + (frvbf_read_mem_UHI): Ditto. + (frvbf_read_mem_SI): Ditto. + (frvbf_read_mem_DI): Ditto. + (frvbf_read_mem_DF): Ditto. + (frvbf_read_imem_USI): New function. + (frvbf_write_mem_QI): Write through the cache is it is enabled. + (frvbf_write_mem_UQI): Ditto. + (frvbf_write_mem_HI): Ditto. + (frvbf_write_mem_UHI): Ditto. + (frvbf_write_mem_SI): Ditto. + (frvbf_write_mem_DI): Ditto. + (frvbf_write_mem_DF): Ditto. + (frvbf_mem_set_QI): New function. + (frvbf_mem_set_HI): New function. + (frvbf_mem_set_SI): New function. + (frvbf_mem_set_DI): New function. + (frvbf_mem_set_DF): New function. + (frvbf_mem_set_XI): New function. + * interrupts.c (frv_save_data_written_for_interrupts): Handle + CGEN_FN_MEM_QI_WRITE, + CGEN_FN_MEM_HI_WRITE, CGEN_FN_MEM_SI_WRITE, CGEN_FN_MEM_DI_WRITE, + CGEN_FN_MEM_DF_WRITE, CGEN_FN_MEM_XI_WRITE. + * frv.c (frvbf_load_quad_GR): Call frvbf_read_mem_SI. + Call sim_queue_fn_mem_xi_write. + (frvbf_load_quad_FRint): Call frvbf_read_mem_SI. + Call sim_queue_fn_mem_xi_write. + (frvbf_load_quad_CPR): Call frvbf_read_mem_SI. + Call sim_queue_fn_mem_xi_write. + (frvbf_insn_cache_preload): New function. + (frvbf_data_cache_preload): New function. + (frvbf_insn_cache_unlock): New function. + (frvbf_data_cache_unlock): New function. + (frvbf_insn_cache_invalidate): New function. + (frvbf_data_cache_invalidate): New function. + (frvbf_data_cache_flush): New function. + * frv-sim.h (sim-options.h): Include it. + (GET_HSR0): New macro. + (SET_HSR0): New macro. + (GET_HSR0_ICE): New macro. + (SET_HSR0_ICE): New macro. + (GET_HSR0_DCE): New macro. + (SET_HSR0_DCE): New macro. + (GET_HSR0_CBM): New macro. + (GET_HSR0_RME): New macro. + (GET_IHSR8): New macro. + (GET_IHSR8_NBC): New macro. + (frvbf_insn_cache_preload): New function. + (frvbf_data_cache_preload): New function. + (frvbf_insn_cache_unlock): New function. + (frvbf_data_cache_unlock): New function. + (frvbf_insn_cache_invalidate): New function. + (frvbf_data_cache_invalidate): New function. + (frvbf_data_cache_flush): New function. + (insn_non_cache_access): New function. + (frvbf_read_imem_USI): New function. + (frvbf_mem_set_QI): New function. + (frvbf_mem_set_HI): New function. + (frvbf_mem_set_SI): New function. + (frvbf_mem_set_DI): New function. + (frvbf_mem_set_DF): New function. + (frvbf_mem_set_XI): New function. + (frv_options): FRV specific command line options. + * Makefile.in (SIM_OBJS): Add options.o and cache.o. + (SIM_EXTRA_DEPS): Add $(sim-options_h). + (cache.o): New target. + (options.o): New target. + * cpu.h,decode.c,decode.h,model.c,sem.c: Regenerate. + * cache.h: New file. + * cache.c: New file. + * options.c: New file. + +1999-11-29 Dave Brolley + + * traps.c (frvbf_check_non_excepting_load): Use new NE_FLAG macros. + (frvbf_check_non_excepting_divide): Ditto. + (clear_ne_flags): Ditto + (frvbf_commit): Ditto. + * pipeline.c (frv_pipeline_add_insn): Clear the NE index for all insns. + * mloop.in (_parallel_write_init): Clear NE flags here. + * interrupts.c (frv_queue_fp_exception_interrupt): Set NE flags here + for non excepting insns. Also check for masked interrupts here. + (frv_process_interrupts): Write NE flags here. + (set_fp_exception_registers): No longer check for masked interrupts + here. + (check_for_compound_interrupt): No need to worry about masked + interrupts. + * frv-sim.h (frv_interrupt_state): Add f_ne_flags member. + (GET_NE_FLAGS): New macro. + (SET_NE_FLAGS): New macro. + (GET_NE_FLAG): Operate on accumulated argument. + (SET_NE_FLAG): Operate on accumulated argument. + (CLEAR_NE_FLAG): Operate on accumulated argument. + * Makefile.in (FRVBF_INCLUDE_DEPS): Add $(SIM_EXTRA_DEPS) + (frv.o): Correct dependencies. + (traps.o): Ditto. + (pipeline.o): Ditto. + (interrupts.o): Ditto. + (memory.o): Ditto. + * sem.c: Regenerate. + +1999-11-26 Dave Brolley + + * traps.c (frvbf_fpu_error): Only call frv_queue_fp_exception if + there is an exception indicated in the mask. + * pipeline.c (frv_pipeline_add_insn): Clear ne_index in the interrupt + state when adding a floating point insn to the pipeline. + * interrupts.c (set_fp_exception_registers): Set NE flag for + non-excepting insns. + * frv-sim.h (frvbf_h_fr_double_get_handler): Mode of data is DF. + (frvbf_h_fr_double_set_handler): Mode of data is DF. + (frvbf_h_fr_int_get_handler): New function. + (frvbf_h_fr_int_set_handler): New function. + (frvbf_set_ne_index): New function. + (NE_NOFLAG): New macro. + (frv_interrupt_state): Add ne_index member. + * frv.c (frvbf_h_fr_double_get_handler): Mode of data is DF. + (frvbf_h_fr_double_set_handler): Mode of data is DF. + (frvbf_h_fr_int_get_handler): New function. + (frvbf_h_fr_int_set_handler): New function. + (frvbf_set_ne_index): New function. + * cpu.c,cpu.h,decode.c,decode.h,model.c,sem.c: Regenerate. + +1999-11-24 Dave Brolley + + * cpu.h,decode.c,decode.h,model.c,sem.c: Regenerate. + +1999-11-23 Dave Brolley + + * frv-sim.h (frvbf_media_cut): New function. + * frv.c (frvbf_media_cut): New function. + * cpu.h,decode.c,decode.h,model.c,sem.c: Regenerate. + +1999-11-22 Dave Brolley + + * frv-sim.h (frvbf_clear_all_accumulators): New function. + * frv.c.h (frvbf_clear_all_accumulators): New function. + * cpu.c,cpu.h,decode.c,decode.h,model.c,sem.c: Regenerate. + +1999-11-18 Dave Brolley + + * pipeline.c (frv_pipeline_add_insn): Only clear MSR0 and FSR0 fields + if this is the first insn of its class in the pipeline. + * frv-sim.h (frvbf_media_register_not_aligned): New function. + * traps.c (frvbf_media_register_not_aligned): New function. + * cpu.h,decode.c,decode.h,model.c,sem.c: Regenerate. + +1999-11-17 Dave Brolley + + * pipeline.c (frv_pipeline_add_insn): Clear MSRx.SIE fields. + * frv-sim.h (OR_MSR_SIE): New macro. + (CLEAR_MSR_SIE): New macro. + (frvbf_media_overflow): Now takes sie argument. + (frv_set_mp_exception_registers): Now takes sie argument. + * interrupts.c (frv_set_mp_exception_registers): Now takes sie argument. + Set MSRx.SIE field. + * cpu.h,decode.c,decode.h,model.c,sem.c: Regenerate. + +1999-11-15 Dave Brolley + + * traps.c (frv_mtrap): New function. + (frvbf_media_cr_not_aligned): New function. + (frvbf_media_acc_not_aligned): New function. + (frvbf_media_overflow): New function. + * pipeline.c (frv_pipeline_add_insn): Clear MSR fields. + * interrupts.c: Call frv_set_mp_exception_registers. + (frv_set_mp_exception_registers): New function. + * frv-sim.h (frv_msr_mtt): New enumeration. + (GET_MSR): New macro. + (SET_MSR): New macro. + (GET_MSR_AOVF): New macro. + (SET_MSR_AOVF): New macro. + (GET_MSR_OVF): New macro. + (SET_MSR_OVF): New macro. + (CLEAR_MSR_OVF): New macro. + (GET_MSR_MTT): New macro. + (SET_MSR_MTT): New macro. + (frv_set_mp_exception_registers): New function. + (frv_mtrap): New function. + (FRV_IS_MEDIA_INSN): New macro. + * cpu.c,cpu.h,decode.c,decode.h,model.c,sem.c: Regenerate. + +1999-11-10 Dave Brolley + + * sim-main.h (_sim_cpu): Add debug_state member. + * mloop.in (_parallel_write_queued): Clear data_written.length. + * interrupts.c (frv_interrupt_table): Offset of BREAK_EXCEPTION + handler is 0xff. + (frv_queue_break_interrupt): New function. + (frv_break_interrupt): New function. + (handle_interrupt): Handle break_interrupt. + (frv_non_operating_interrupt): Now takes interrupt_kind. + * frv-sim.h (frv_queue_break_interrupt): New function. + (frv_break_interrupt): New function. + (frv_break): New function. + (frv_non_operating_interrupt): Now takes interrupt_kind. + * cpu.h,decode.c,decode.h,model.c,sem.c: Regenerate. + +1999-11-09 Dave Brolley + + * pipeline.c (frv_pipeline_add_insn): Clear FSR0.FTT when adding + a floating point insn. + * traps.c (frvbf_fpu_error): Map fpu status to frv interrupts. + * interrupts.c (frv_queue_illegal_instruction_interrupt): Call + frv_queue_fp_exception_interrupt. + (frv_queue_fp_exception_interrupt): New function. + (next_available_fq): New function. + (set_fp_exception_registers): New function. + (set_exception_status_registers): Now returns 1 if interrupt not masked. + (check_for_compound_interrupt): Now returns NULL if interrupt masked. + (frv_program_interrupt): Don't process interrupt if it is masked. + * frv.c (frvbf_h_fr_double_get_handler): Call + frv_queue_fp_exception_interrupt. + (frvbf_h_fr_double_set_handler): Call frv_queue_fp_exception_interrupt. + (frvbf_h_fr_quad_set_handler): Call frv_queue_fp_exception_interrupt. + (frvbf_store_quad_FRint): Call frv_queue_fp_exception_interrupt. + * frv-sim.h: Get/set hardware directly in GET/SET macros. + (frv_fp_exception_info): New struct type. + (frv_interrupt_queue_element): Add fp_info member. + (frv_fsr_traps): New enumeration. + (frv_fsr_ftt): New enumeration. + (frv_sie): New enumeration. + (frv_miv): New enumeration. + (GET_FSR): New macro. + (SET_FSR): New macro. + (GET_FSR_TEM): New macro. + (SET_FSR_QNE): New macro. + (SET_FSR_FTT): New macro. + (GET_FSR_AEXC): New macro. + (SET_FSR_AEXC): New macro. + (GET_FQ): New macro. + (SET_FQ): New macro. + (SET_FQ_OPC): New macro. + (SET_FQ_MIV): New macro. + (SET_FQ_SIE): New macro. + (SET_FQ_FTT): New macro. + (SET_FQ_CEXC): New macro. + (GET_FQ_VALID): New macro. + (SET_FQ_VALID): New macro. + (frv_queue_fp_exception_interrupt): New function. + (FRV_IS_FLOAT_INSN): New macro. + +1999-11-04 Dave Brolley + + * traps.c (frvbf_fpu_error): No floating point errors need to be + detected. + * interrupts.c (clear_exception_status_registers): Clear 'valid' fields + of the ESR registers too. + (set_exception_status_registers): Don't set EAR for any precise + interrupts. Register index should be 1 for insns in PIPE_I1. Clear + ESR.EAV and ESR.EDV if not setting them. Set ESR.VALID. + (non_operating_interrupt): No need for return code. + (frv_program_or_software_interrupt): Process interrupt regardless + of operating mode. If PSR.ET was not set at the start of processing, + then stop the simulation with a message. + (frv_save_data_written_for_interrupts): Handle CGEN_FN_XI_WRITE and + CGEN_MEM_XI_WRITE. + * frv.c (frvbf_h_gr_quad_set_handler): New function. + (frvbf_h_fr_quad_set_handler): New function. + (frvbf_h_cpr_quad_set_handler): New function. + (frvbf_load_quad_GR): Renamed from frvbf_load_multiple_GR. Use new + sim_queue_fn_xi_write. + (frvbf_load_quad_FRint): Renamed from frvbf_load_multiple_GR. Use new + sim_queue_fn_xi_write. + (frvbf_load_quad_CPR): Renamed from frvbf_load_multiple_GR. Use new + sim_queue_fn_xi_write. + (frvbf_store_quad_GR): Renamed from frvbf_store_multiple_GR. Use new + sim_queue_mem_xi_write. + (frvbf_store_quad_FRint): Renamed from frvbf_store_multiple_GR. Use new + sim_queue_mem_xi_write. + (frvbf_store_quad_CPR): Renamed from frvbf_store_multiple_GR. Use new + sim_queue_mem_xi_write. + * frv-sim.h (frvbf_h_gr_quad_set_handler): New function. + (frvbf_h_fr_quad_set_handler): New function. + (frvbf_h_cpr_quad_set_handler): New function. + (SET_ESR_VALID): New macro. + (CLEAR_ESR_VALID): New macro. + (CLEAR_ESR_EAV): New macro. + (CLEAR_ESR_EDV): New macro. + * sem.c: Regenerate. + +1999-11-02 Dave Brolley + + * traps.c (frv_core_signal): Call + frv_queue_mem_address_not_aligned_interrupt. + * mloop.in (_parallel_write_queued): Call + frv_save_data_written_for_interrupts. + * frv.c (frvbf_h_gr_double_get_handler): Call + frv_queue_register_exception_interrupt. + (frvbf_h_cpr_double_get_handler): Call + frv_queue_register_exception_interrupt. + (frvbf_h_cpr_double_set_handler): Call + frv_queue_register_exception_interrupt. + (frvbf_load_multiple_GR): Call + frv_queue_register_exception_interrupt. + (frvbf_store_multiple_GR): Call + frv_queue_register_exception_interrupt. + (frvbf_load_multiple_CPR): Call + frv_queue_register_exception_interrupt. + (frvbf_store_multiple_CPR): Call + frv_queue_register_exception_interrupt. + (frvbf_h_tbr_get_handler): Fix TBR.TBA mask. + * interrupts.c (frv_queue_software_interrupt): Now returns interrupt + queue element. + (frv_queue_program_interrupt): Now returns interrupt queue element. + (frv_queue_illegal_instruction_interrupt): Now returns interrupt queue + element. + (frv_queue_interrupt): Now returns interrupt queue element. + (frv_queue_register_exception_interrupt): New function. + (frv_queue_mem_address_not_aligned_interrupt): New function. + (frv_save_data_written_for_interrupts): New function. + (next_available_edr): EDR registers available in blocks of 4. + (clear_exception_status_registers): New function. + (set_exception_status_registers): Pass esr to SET_ESR* macros. + + * frv-sim.h (struct frv_data_written): New struct type. + (frv_interrupt_queue_element): Add data_written member. + (frv_queue_software_interrupt): Now returns interrupt queue element. + (frv_queue_program_interrupt): Now returns interrupt queue element. + (frv_queue_illegal_instruction_interrupt): Now returns interrupt queue + element. + (frv_queue_interrupt): Now returns interrupt queue element. + (frv_queue_register_exception_interrupt): New function. + (frv_queue_mem_address_not_aligned_interrupt): New function. + (frv_save_data_written_for_interrupts): New function. + +1999-10-27 Dave Brolley + + * interrupts.c (ITABLE_ENTRY): New macro. + (frv_interrupt_table): Add exception codes. + (next_available_esr): New function. + (next_available_edr): New function. + (set_edr_register): New function. + (set_exception_status_registers): New function. + (check_for_compound_interrupt): Record information on all interrupts + found. + (frv_program_interrupt): Always call check_for_compound_interrupt. + * frv.c (frvbf_h_pc_set_handler): Removed. + (frvbf_h_spr_get_handler): Handle LR register. + (frvbf_h_spr_set_handler): Handle LR register. + (frvbf_h_lr_get_handler): New function. + (frvbf_h_lr_set_handler): New function. + * frv-sim.h (frvbf_h_lr_get_handler): New function. + (frvbf_h_lr_set_handler): New function. + (frv_ec): New enumeration. + (frv_interrupt): Add frv_ec field. + (frv_rec): New enumeration. + (frv_daec): New enumeration. + (frv_interrupt_queue_element): Add eaddress, rec, iaec, daec fields. + (SET_ESR_EC): New macro. + (SET_ESR_REC): New macro. + (SET_ESR_IAEC): New macro. + (SET_ESR_DAEC): New macro. + (SET_ESR_EAV): New macro. + (GET_ESR_EDV): New macro. + (SET_ESR_EDV): New macro. + (GET_ESR_EDN): New macro. + (SET_ESR_EDN): New macro. + (GET_ESR): New macro. + (SET_ESR): New macro. + (SET_EPCR): New macro. + (SET_EAR): New macro. + (SET_EDR): New macro. + (GET_ESFR): New macro. + (SET_ESFR): New macro. + * cpu.c,cpu.h,sem.c: Rebuild. + +1999-10-26 Dave Brolley + + * traps.c (frvbf_check_non_excepting_load): Only set NESR, NECR, NEEAR + if mach is frv. + (clear_nesr_neear): Only execute if mach is frv. + +1999-10-22 Dave Brolley + + * sim-main.h (sim_cpu): Add pipeline. + (CPU_PIPELINE): New macro. + * mloop.in (_parallel_write_queued): Maintain pc in cpu during writes. + (main loop): Maintain pc in cpu. + * frv-sim.h (frv_queue_software_interrupt): New interface. + (frv_queue_program_interrupt): New interface. + (frv_queue_illegal_instruction_interrupt: New interface. + (frv_queue_interrupt): New interface. + (frv_detect_insn_access_interrupts): New interface. + (frv_process_interrupts): New interface. + (frv_program_interrupt): New interface. + (frv_software_interrupt): New interface. + (frv_program_or_software_interrupt): New interface. + (FRV_PIPELINE): Moved from pipline.c. + (frv_pipeline_reset): New interface. + (frv_pipeline_add_insn): New interface. + * interrupts.c (frv_queue_software_interrupt): New interface. + (frv_queue_program_interrupt): New interface. + (frv_queue_illegal_instruction_interrupt: New interface. + (frv_queue_interrupt): New interface. + (frv_detect_insn_access_interrupts): New interface. + (frv_process_interrupts): New interface. + (frv_program_interrupt): New interface. + (frv_software_interrupt): New interface. + (frv_program_or_software_interrupt): New interface. + * frv.c: Use new interfaces. + * pipeline.c: Use new interfaces. + * traps.c: Use new interfaces. + * memory.c: Use new interfaces. + (frv_address_forbidden): No longer static. + +1999-10-19 Dave Brolley + + * traps.c (frvbf_check_non_excepting_load): Set NESR.DAEC, NESR.REC and + NESR.EC. + * mloop.in (_parallel_write_queued): Handle CGEN_FN_PC_WRITE. + * frv.c (frvbf_h_pc_set_handler): New function. + * interrupts.c (frv_detect_data_interrupt): Removed. + (address_forbidden): Removed. + * frv-sim.h (frv_detect_data_interrupt): Removed. + (NESR_MEM_ADDRESS_NOT_ALIGNED): New macro. + (NESR_REGISTER_NOT_ALIGNED): New macro. + (NESR_UQI_SIZE): New macro. + (NESR_QI_SIZE): New macro. + (NESR_UHI_SIZE): New macro. + (NESR_HI_SIZE): New macro. + (NESR_SI_SIZE): New macro. + (NESR_DI_SIZE): New macro. + (NESR_XI_SIZE): New macro. + (GET_NESR_DAEC): New macro. + (SET_NESR_DAEC): New macro. + (GET_NESR_REC): New macro. + (SET_NESR_REC): New macro. + (GET_NESR_EC): New macro. + (SET_NESR_EC): New macro. + (frvbf_read_mem_QI): New function. + (frvbf_read_mem_UQI): New function. + (frvbf_read_mem_HI): New function. + (frvbf_read_mem_UHI): New function. + (frvbf_read_mem_SI): New function. + (frvbf_read_mem_WI): New function. + (frvbf_read_mem_DI): New function. + (frvbf_read_mem_DF): New function. + (frvbf_write_mem_QI): New function. + (frvbf_write_mem_UQI): New function. + (frvbf_write_mem_HI): New function. + (frvbf_write_mem_UHI): New function. + (frvbf_write_mem_SI): New function. + (frvbf_write_mem_WI): New function. + (frvbf_write_mem_DI): New function. + (frvbf_write_mem_DF): New function. + * Makefile.in (SIM_OBJS): Add memory.o. + * cpu.c,cpu.h,sem.c: Rebuild. + +1999-10-18 Dave Brolley + + * sim-if.c (sim_open): Use a real fpu error function. + * pipeline.c (frv_pipeline_add_insn): Don't add invalid insns. + * mloop.in (_parallel_write_queued): Clear queue after writing. + * interrupts.c (check_for_compound_interrupt): New function. + (non_operating_interrupt): New function. + * frv-sim.h (frvbf_h_gr_double_get_handler): New function. + (frvbf_h_gr_double_set_handler): New function. + (frvbf_h_fr_double_get_handler): New function. + (frvbf_h_fr_double_set_handler): New function. + (frvbf_h_cpr_double_get_handler): New function. + (frvbf_h_cpr_double_set_handler): New function. + (frv_interrupt_queue_element): New struct type. + (frv_queue_program_interrupt): Now takes pc. + (frv_queue_illegal_instruction_interrupt): Now takes pc. + (frv_queue_interrupt): Now takes pc. + (frv_program_interrupt): Now takes frv_interrupt_queue_element. + (frv_software_interrupt): Now takes frv_interrupt_queue_element. + (frvbf_division_exception): New function. + (frvbf_fpu_error): New function. + (frvbf_load_multiple_GR): New function. + (frvbf_load_multiple_FR): New function. + (frvbf_load_multiple_CPR): New function. + * frv.c (frvbf_h_gr_double_get_handler): New function. + (frvbf_h_gr_double_set_handler): New function. + (frvbf_h_fr_double_get_handler): New function. + (frvbf_h_fr_double_set_handler): New function. + (frvbf_h_cpr_double_get_handler): New function. + (frvbf_h_cpr_double_set_handler): New function. + (frv_interrupt_queue_element): New struct type. + (frv_queue_program_interrupt): Now takes pc. + (frv_queue_illegal_instruction_interrupt): Now takes pc. + (frv_queue_interrupt): Now takes pc. + (frv_program_interrupt): Now takes frv_interrupt_queue_element. + (frv_software_interrupt): Now takes frv_interrupt_queue_element. + (frvbf_fpu_error): New function. + (frvbf_load_multiple_GR): New function. + (frvbf_load_multiple_FR): New function. + (frvbf_load_multiple_CPR): New function. + * traps.c (frvbf_division_exception): New function. + * cpu.c,cpu.h,decode.c,decode.h,model.c,sem.c: Rebuild. + +1999-10-12 Dave Brolley + + * mloop.in (new_vpc): New variable. + (main loop): Call frv_detect_insn_access_interrupts. Call + frv_detect_data_interrupts. + * interrupts.c (access_queued_to): New function. + (frv_detect_data_interrupts): New function. + (frv_detect_insn_access_interrupts): New function. + (frv_program_or_software_interrupt): Set PSR.S. + * frv-sim.h (frv_detect_data_interrupts): New function. + (frv_detect_insn_interrupts): New function. + +1999-10-07 Dave Brolley + + * frv-sim.h (frvbf_h_gr_hi_get_handler): New function. + (frvbf_h_gr_hi_set_handler): New function. + (frvbf_h_gr_lo_get_handler): New function. + (frvbf_h_gr_lo.set_handler): New function. + * frv.c (frvbf_h_gr_hi_get_handler): New function. + (frvbf_h_gr_hi_set_handler): New function. + (frvbf_h_gr_lo_get_handler): New function. + (frvbf_h_gr_lo.set_handler): New function. + (frvbf_model_fr500_u_integer): New function. + * arch.h,cpu.h,cpu.c,decode.h,decode.c,model.c,sem.c: Rebuild. + +1999-10-04 Dave Brolley + + * traps.c: Use sim_engine_abort. + * pipeline.c (frv_pipeline): Add field for insn major. + (add_next_to_pipe): Return address of matching pipeline. + (find_major_in_pipeline): New function. + (check_insn_major_constraints: New function. + (frv_pipeline_add_insn): Add checks for insn major constraints. + * interrupts.c (frv_process_interrupts): Use sim_engine_abort. + * frv.c (frvbf_h_spr_get_handler): No need to abort. + +Thu Sep 30 18:10:25 1999 Dave Brolley + + * pipeline.c: New file. + * mloop.in (main loop): Call frv_pipeline_reset. + Call frv_pipeline_add_insn. + * frv-sim.h (frv_pipeline_reset): New function. + (frv_pipeline_add_insn): New function. + * Makefile.in (SIM_OBJS): Add pipeline.o + +1999-09-29 Doug Evans + + * sem.c: Rebuild. + * traps.c (sim_engine_invalid_insn): New arg `vpc'. Change type of + result to SEM_PC. Return vpc. + +Wed Sep 29 16:01:52 1999 Dave Brolley + + * interrupts.c (frv_interrupt_table): DATA_STORE_ERROR is imprecise. + (frv_queue_interrupt): Don't detect identical interrupts here. + +Wed Sep 29 14:49:52 1999 Dave Brolley + + * interrupts.c: New file. + * traps.c (sim_engine_invalid_insn): Return PC of next insn. + (frv_software_interrupt): Moved to interrupts.c. + (frv_itrap): New interface. Call frv_queue_software_interrupt. + * mloop.in (@cpu@_parallel_write_init): set previous_vliw_pc. + (@cpu@_perform_writeback): New function. + (main loop): Call frv_process_interrupts. + * frv-sim.h (frvbf_write_next_vliw_addr_to_PCSR): Removed. + (frv_itrap): New interface. + (frv_interrupt_class): New enumeration. + (frv_interrupt_kind): New enumeration. + (struct frv_interrupt): New struct type. + (frv_interrupt_table): New table of interrupt information. + (FRV_INTERRUPT_QUEUE_SIZE): New macro. + (struct frv_interrupt_state): New struct type. + (frv_interrupt_state): New global variable. + (previous_vliw_pc): New global variable. + (frv_queue_software_interrupt): New function. + (frv_queue_program_interrupt): New function. + (frv_queue_interrupt): New function. + (frv_process_interrupts): New function. + (frv_program_interrupt): New function. + (frv_software_interrupt): New function. + (frv_program_or_software_interrupt): New function. + (frv_clear_interrupt_classes): New function. + * frv.c (frvbf_write_next_vliw_addr_to_PCSR): Removed. + * Makefile.in (SIM_OBJS): Add interrupts.o + * sem.c: Rebuild. + +1999-09-25 Doug Evans + + * cpu.h,cpuall.h,decode.c,sem.c: Rebuild. + +Tue Sep 21 17:16:47 1999 Dave Brolley + + * mloop.in (main loop): Determine last insn from scache entry. + * cpu.h: Rebuild. + * cpuall.h: Rebuild. + +Tue Sep 14 14:21:31 1999 Dave Brolley + + * frv-sim.h (frvbf_write_next_vliw_addr_to_PCSR): New flag. + (NECR_ELOS): Define as unshifted value. + (NECR_NEN): Define as unshifted value. + (NECR_VALID): Define as unshifted value. + (SET_NESR): Rewite to use post-write queue. + (SET_NESR_VALID): Rewite to operate on argument. + (SET_NESR_EAV): Rewite to operate on argument. + (SET_NESR_FR): Rewite to operate on argument. + (CLEAR_NESR_FR): Rewite to operate on argument. + (SET_NESR_DRN): Rewite to operate on argument. + (SET_NESR_SIZE): Rewite to operate on argument. + (SET_NESR_NEAN): Rewite to operate on argument. + (SET_NEEAR): Rewite to use post-write queue. + (SET_NE_FLAG): Rewite to use post-write queue. + (CLEAR_NE_FLAG): Rewite to use post-write queue. + * traps.c (frv_software_interrupt): Rewite to use post-write queue. + (frv_rett): Rewite to use post-write queue. + (next_available_nesr): Rewrite to use new macro interfaces. + (next_valid_nesr): Ditto. + (frvbf_check_non_excepting_load): Ditto. + (frvbf_check_recovering_store): Ditto. + (clear_nesr_neear): Ditto. + (clear_ne_flags): Ditto. + * mloop.in (main loop): Update PCSR with address of next VLIW insn + when flag is set. + * frv.c (frvbf_h_spr_get_handler): Shift register fields here now. + (frvbf_store_multiple_GR): Rewite to use post-write queue. + (frvbf_store_multiple_FRint): Rewite to use post-write queue. + (frvbf_store_multiple_CPR): Rewite to use post-write queue. + * Makefile.in (frv.o): Depend on cgen-par.h. + +Fri Sep 10 17:03:15 1999 Dave Brolley + + * frv-sim.h (frvbf_set_write_next_vliw_addr_to_LR): New function. + (frvbf_write_next_vliw_addr_to_LR): New flag. + * frv.c (frvbf_set_write_next_vliw_addr_to_LR): New function. + * mloop.in: Only take the first branch in a VLIW insn. Set LR to the + address of the next VLIW insn if flag is set. + * cpu.h,decode.c,sem.c: Rebuild. + +Tue Sep 7 13:44:23 1999 Dave Brolley + + * mloop.in: Limit parallel insns to MAX_PARALLEL_INSNS. + * sem.c: Rebuild. + +1999-09-02 Doug Evans + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +1999-09-01 Doug Evans + + * decode.c: Rebuild. + +Mon Aug 30 17:54:57 1999 Dave Brolley + + * traps.c (frv_rett): New function. + * frv.c (frvbf_h_spr_get_handler): Handle bpsr. + (frvbf_h_spr_set_handler): Handle bpsr. + (frvbf_h_bpsr_get_handler): New function. + (frvbf_h_bpsr_set_handler): New function. + * frv-sim.h (frv_rett): New function. + (frvbf_h_bpsr_get_handler): New function. + (frvbf_h_bpsr_set_handler): New function. + * mloop.in: Read actual packing bit. + * cpu.c,cpu.h,decode.c,decode.h,model.c,sem.c: Rebuild. + +Tue Aug 31 16:04:37 1999 Dave Brolley + + * traps.c (WANT_CPU): New macro. + (WANT_CPU_FRVBF): New macro. + (frvbf_check_recovering_store): Use registers for source and queue + writes. + * mloop.in: New main loop for parallel support. + (@cpu@_parallel_write_init): New function. + (@cpu@_parallel_write_queued): New function. + * frv-sim.h (set_icc_for_shift_left): New interface. + (set_icc_for_shift_right): New interface. + (frvbf_check_recovering_store): New interface. + * frv.c (set_icc_for_shift_left): Pass and return icc value. + (set_icc_for_shift_right): Pass and return icc value. + (frvbf_check_recovering_store): New interface. + * Makefile.in (FRV_OBJS): Add cgen-par.o. + (stamp-mloop): Add cgen parallel options. + (stamp-arch): Remove with-profile option. + (stamp-cpu): Add cgen parallel options. + * arch.h,cpu.h,decode.c,decode.h,model.c,sem.c: Rebuild. + +1999-08-28 Doug Evans + + * cpu.h,decode.c,sem.c: Rebuild. + +Wed Aug 25 12:25:04 1999 Dave Brolley + + * arch.h,cpu.h,decode.h,model.c,sem.c: Rebuild. + +Thu Aug 19 17:59:00 1999 Dave Brolley + + * configure.in: fr500 now the default model. + * configure: Regenerate. + * frv.c: Change frv-1 to frv-gen. + (frvbf_model_fr500_u_exec): New function. + * Makefile.in (stamp-cpu): Use 'mach=frv,fr500' to build decoder. + * mloop.in: Fix typos in comments. + * arch.c,arch.h,cpu.h,cpuall.h,decode.h,model.c,sem.c: Rebuild. + +1999-08-17 Dave Brolley + + * cpu.h,decode.c,decode.h,model.c,sem.c: Rebuild. + +1999-08-09 Doug Evans + + * cpu.h,decode.c,decode.h,model.c,sem.c: Rebuild. + +1999-08-04 Doug Evans + + * cpu.h,cpuall.h,decode.c,model.c,sem.c: Rebuild. + +Fri Jul 16 14:50:15 1999 Dave Brolley + + * frv.c (frvbf_fetch_register): Use GDB register number macros. + (frvbf_store_register): Use GDB register number macros. + (frvbf_cut): New function. + * frv-sim.h (GR_REGNUM_MAX): New macro. + (FR_REGNUM_MAX): New macro. + (PC_REGNUM): New macro. + (LR_REGNUM): New macro. + (frvbf_cut): New function. + * cpu.h,decode.c,decode.h,model.c,sem.c: Regenerate. + +1999-07-15 Stan Shebs + + * frv.c (frvbf_fetch_register): Add ability to get LR register, + add default for unhandled registers. + (frvbf_store_register): Add ability to set LR register. + +1999-07-14 Stan Shebs + + * frv.c (frvbf_fetch_register, frvbf_store_register): Fill in. + (decode_gdb_dr_regnum): Remove, not used. + +1999-07-13 Michael Meissner + + * Makefile.in (SIM_EXTRA_FLAGS): Incorporate @sim_trapdump@. + + * configure.in (--enable-sim-trapdump): New switch to make unknown + traps dump the register contents, instead of doing the trap thing. + * configure: Regenerate. + + * frv-sim.h (TRAP_BREAKPOINT): Define as 81, so it can be used. + (TRAP_REGDUMP{1,2}): Define to provide register dumping support + temporarily. + + * traps.h (toplevel): Include bfd.h, libiberity.h. + (frv_itrap): Add support for --enable-sim-trapdump and traps 2,3 + dumping the registers. + +Thu Jul 8 10:57:39 1999 Dave Brolley + + * Makefile.in (SIM_EXTRA_LIBS): Removed. libm no longer needed. + +Wed Jul 7 17:01:12 1999 Dave Brolley + + * cpu.c,cpu.h,decode.c,model.c,sem.c: Rebuild. + +Tue Jul 6 16:12:18 1999 Dave Brolley + + * frv.c (frvbf_square_root_SF): Removed. + (frvbf_square_root_DF): Removed. + (frvbf_h_fr_double_get_handler): Removed. + (frvbf_h_fr_double_set_handler): Removed. + (frvbf_h_fr_int_get_handler): Removed. + (frvbf_h_fr_int_set_handler): Removed. + * frv-sim.h (frvbf_square_root_SF): Removed. + (frvbf_square_root_DF): Removed. + (frvbf_h_fr_double_get_handler): Removed. + (frvbf_h_fr_double_set_handler): Removed. + (frvbf_h_fr_int_get_handler): Removed. + (frvbf_h_fr_int_set_handler): Removed. + * decode.c,decode.h,model.c,sem.c: Rebuild. + +1999-07-05 Doug Evans + + * Makefile.in (SIM_OBJS): Add cgen-fpu.o, cgen-accfp.o. + * cpu.c,cpu.h,decode.c,decode.h,model.c,sem.c: Rebuild. + * sim-if.c (sim_open): Initialize fpu. + * frv-sim.h (SETMEMSF,SETMEMDF): Delete. + * frv.c (frvbf_store_multiple_FRint): Replace frvbf_h_fr_int_get + with frvbf_h_fr_get. + +Wed Jun 30 15:56:56 1999 Dave Brolley + + * frv-sim.h (NESR_RANGE): New macro. + (NO_NESR): New macro. + (GET_NESR_VALID): New macro. + (next_ne_index): Removed. + * traps.c (next_available_nesr): New function. + (next_valid_nesr): New function. + (frvbf_check_non_excepting_load): Use next_available_nesr. + (frvbf_check_recovering_store): Use next_available_nesr and + next_valid_nesr. + (clear_nesr_neear): Use next_available_nesr and next_valid_nesr. + (frvbf_check_recovering_store): Only consider one matching register. + * sem.c: Rebuild. + +Tue Jun 29 16:54:32 1999 Dave Brolley + + * frv.c (frvbf_square_root_SF): New function. + (frvbf_square_root_DF): New function. + (frvbf_h_fr_double_get_handler): New function. + (frvbf_h_fr_double_set_handler): New function. + * frv-sim.h (frvbf_square_root_SF): New function. + (frvbf_square_root_DF): New function. + (frvbf_h_fr_double_get_handler): New function. + (frvbf_h_fr_double_set_handler): New function. + * cpu.h,cpu.c,decode.c,decode.h,model.c,sem.c: Rebuild. + +1999-06-28 Dave Brolley + + * decode.c,decode.h,model.c,sem.c: Regenerate. + +Thu Jun 24 17:26:32 1999 Dave Brolley + + * Makefile.in (SIM_EXTRA_LIBS): Add -lm. + * frv-sim.h (frvbf_h_fr_int_get_handler): New function. + (frvbf_h_fr_int_set_handler): New function. + (frvbf_store_multiple_FRint): New function. + (frvbf_square_root_SF): New function. + * frv.c (frvbf_h_fr_int_get_handler): New function. + (frvbf_h_fr_int_set_handler): New function. + (frvbf_store_multiple_FRint): New function. + (frvbf_square_root_SF): New function. + * cpu.h,cpu.c,decode.c,decode.h,model.c,sem.c,sem-switch.c: Regenerate. + +1999-06-23 Doug Evans + + * Makefile.in (stamp-mloop): Delete -fast -pbb -switch args + to genmloop.sh. Pass -scache instead. + (mloop.o): Delete sem-switch.c dependency. + (sem-switch.c): Delete rule. + (stamp-cpu): Don't build sem-switch.c. + * sem-switch.c: Delete. + * mloop.in (xfull-exec-*): Fix call to execute. + * tconfig.in (WITH_SCACHE_PBB): Define as 0. + + * cpu.h,decode.c,model.c,sem-switch.c,sem.c: Rebuild. + +Tue Jun 22 16:23:57 1999 Dave Brolley + + * cpu.h,decode.c,sem.c,sem-switch.c: Regenerate. + +Mon Jun 21 17:34:10 1999 Dave Brolley + + * mloop.in (execute): Force gr0 to zero before each insn. + * cpu.h,cpu.c,decode.c,sem.c,sem-switch.c: Regenerate. + +1999-06-18 Doug Evans + + * cpu.h,decode.c,model.c,sem-switch.c,sem.c: Rebuild. + +Fri Jun 18 17:49:23 1999 Dave Brolley + + * frv.c (frvbf_h_gr_get_handler): New function. + (frvbf_h_gr_set_handler): New function: + (frvbf_store-multiple_GR): New function: + (frvbf_store-multiple_FR): New function: + (frvbf_store-multiple_CPR): New function: + * frv-sim.h (frvbf_h_gr_get_handler): New function. + (frvbf_h_gr_set_handler): New function: + (frvbf_store-multiple_GR): New function: + (frvbf_store-multiple_FR): New function: + (frvbf_store-multiple_CPR): New function: + * traps.c (frv_itrap): Implement proper syscalls interface. + * cpu.h,cpu.c,decode.c,decode.h,model.c,sem.c,sem-switch.c: Regenerate. + +Fri Jun 18 14:36:23 1999 Dave Brolley + + * traps.c (frvbf_check_non_excepting_divide): New function. + (frvbf_check_recovering_store): New function. + (clear_nesr_neear): New function. + (clear_ne_flags): New function. + (frvbf_commit): New function. + + * frv-sim.h (frvbf_check_non_excepting_divide): New function. + (frvbf_check_recovering_store): New function. + (clear_nesr_neear): New function. + (clear_ne_flags): New function. + (frvbf_commit): New function. + * cpu.h,decode.c,decode.h,model.c,sem.c,sem-switch.c: Regenerate. + +1999-06-16 Dave Brolley + + * frv.c (frvbf_h_spr_get_handler): Handle SPR_NECR. + (frvbf_h_spr_set_handler): Handle SPR_NECR. + * traps.c (next_ne_index): New variable. + (frvbf_check_non_excepting_load): New function. + * frv-sim.h (NECR_ELOS): New macro. + (NECR_NEN): New macro. + (NECR_VALID): New macro. + (SET_NESR_VALID): New macro. + (SET_NESR_EAV): New macro. + (SET_NESR_FR): New macro. + (CLEAR_NESR_FR): New macro. + (SET_NESR_DRN): New macro. + (SET_NESR_SIZE): New macro. + (SET_NESR_NEAN): New macro. + (SET_NEEAR): New macro. + (GET_NE_FLAG): New macro. + (SET_NE_FLAG): New macro. + (CLEAR_NE_FLAG): New macro. + (frvbf_check_non_excepting_load): New function: + * cpu.h,decode.c,decode.h,model.c,sem.c,sem-switch.c: Regenerate. + +Wed Jun 9 18:12:49 1999 Dave Brolley + + * cpu.h,decode.c,model.c,sem.c,sem-switch.c: Regenerate. + +Tue Jun 8 18:13:51 1999 Dave Brolley + + * frv.c (cr_logic): Correct andcr, nandcr, andncr and nandncr. + * cpu.h,decode.c,decode.h,model.c,sem.c,sem-switch.c: Regenerate. + +Mon Jun 7 17:09:15 1999 Dave Brolley + + * cpu.h,decode.c,decode.h,model.c,sem.c,sem-switch.c: Regenerate. + +1999-06-07 Dave Brolley + + * cpu.h,decode.c,decode.h,model.c,sem.c,sem-switch.c: Regenerate. + +Thu Jun 3 17:33:31 1999 Dave Brolley + + * cpu.h,decode.c,decode.h,model.c,sem.c,sem-switch.c: Regenerate. + +Wed Jun 2 17:50:21 1999 Dave Brolley + + * cpu.h,decode.c,decode.h,model.c,sem.c,sem-switch.c: Regenerate. + +Tue Jun 1 17:58:53 1999 Dave Brolley + + * cpu.h,decode.c,model.c,sem.c,sem-switch.c: Regenerate. + +Mon May 31 17:57:25 1999 Dave Brolley + + * traps.c (frv_software_interrupt): Pass current_cpu to + frvbf_h_psr_esr_get. + (frv_software_interrupt): Calculate the new PC based on TBR. + * cpu.h,decode.c,model.c,sem.c,sem-switch.c: Regenerate. + +1999-05-31 Dave Brolley + + * cpu.h,decode.c,model.c,sem.c,sem-switch.c: Regenerate. + +Thu May 27 17:42:00 1999 Dave Brolley + + * frv-sim.h (frvbf_h_cccr_get_handler): New function. + (frvbf_h_cccr_set_handler): New function. + (frvbf_scan_result): New function. + (frvbf_cr_logic): New function. + * frv.c (frvbf_h_cccr_get_handler): New function. + (frvbf_h_cccr_set_handler): New function. + (frvbf_scan_result): New function. + (frvbf_cr_logic): New function. + (cr_ops,cr_result,cr_logic): New table. + * cpu.h,decode.c,model.c,sem.c,sem-switch.c: Regenerate. + +1999-05-25 Dave Brolley + + * frv.c (frvbf_h_spr_get_handler): Add support for TBR and PSR. + (frvbf_h_spr_set_handler): Add support for TBR and PSR. + (frv_psr_get_handler): New function. + (frv_psr_set_handler): New function. + (frv_tbr_get_handler): New function. + (frv_tbr_set_handler): New function. + (frvbf_h_ccr_get_handler): Add support for fCC. + (frvbf_h_ccr_set_handler): Add support for fCC. + * frv-sim.h (frv_psr_get_handler): New function. + (frv_psr_set_handler): New function. + (frv_tbr_get_handler): New function. + (frv_tbr_set_handler): New function. + * traps.c (frv_software_interrupt): Implement. + * cpu.h,cpu.c,decode.c,decode.h,model.c,sem.c,sem-switch.c: Regenerate. + +Thu May 20 16:39:27 1999 Dave Brolley + + * cpu.h,cpu.c,decode.c,decode.h,model.c,sem.c,sem-switch.c: Regenerate. + +1999-05-18 Dave Brolley + + * frv.c: (frvbf_set_icc_for_shift_left): New function. + (frvbf_set_icc_for_shift_right): New function. + * frv-sim.h (frvbf_set_icc_for_shift_left): New function. + (frvbf_set_icc_for_shift_right): New function. + (SETMEMSF): New Macro. + (SETMEMDF): New Macro. + * cpu.h,decode.c,decode.h,model.c,sem.c,sem-switch.c: Regenerate. + +Thu May 13 17:14:49 1999 Dave Brolley + + * frv.c (frvbf_h_ccr_get_handler): New function. + (frvbf_h_ccr_set_handler): New function. + * cpu.h,cpu.c,decode.c,decode.h,model.c,sem.c,sem-switch.c: Regenerate. + +Tue May 11 16:13:15 1999 Dave Brolley + + * frv-sim.h (frvbf_h_spr_get_handler,frvbf_h_spr_set_handler, + frvbf_h_isr_get_handler, frvbf_h_isr_set_handler): New functions. + * frv.c: Likewise. + * cpu.h,cpu.c,decode.c,decode.h,model.c,sem.c,sem-switch.c: Regenerate. + +1999-05-10 Dave Brolley + + * cpu.h,cpu.c,decode.c,model.c,sem.c,sem-switch.c: Regenerate. + +Thu May 6 16:48:21 1999 Dave Brolley + + * cpu.h,decode.c,sem.c,sem-switch.c: Regenerate. + * frv-sim.h (TRAP_SYSCALL): Define as 0x80. + +Wed May 5 11:52:24 1999 Dave Brolley + + * traps.c (frv_software_interrupt): New function. + (frv_itrap): New function. + * frv-sim.h (TRAP_SYSCALL): define as 0. + * cpu.h,decode.c,decode.h,model.c,sem.c,sem-switch.c: Regenerate. + +Mon May 3 13:49:21 1999 Dave Brolley + + * cpu.h,decode.c,decode.h,model.c,sem.c,sem-switch.c: Regenerate. + +Thu Apr 29 17:37:06 1999 Dave Brolley + + * Directory created. diff --git a/sim/frv/Makefile.in b/sim/frv/Makefile.in new file mode 100644 index 0000000..adc11ca --- /dev/null +++ b/sim/frv/Makefile.in @@ -0,0 +1,130 @@ +# Makefile template for Configure for the frv simulator +# Copyright (C) 1998, 1999, 2000, 2001, 2003 Free Software Foundation, Inc. +# Contributed by Red Hat. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License along +# with this program; if not, write to the Free Software Foundation, Inc., +# 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +## COMMON_PRE_CONFIG_FRAG + +FRV_OBJS = frv.o cpu.o decode.o sem.o model.o mloop.o cgen-par.o + +CONFIG_DEVICES = dv-sockser.o +CONFIG_DEVICES = + +SIM_OBJS = \ + $(SIM_NEW_COMMON_OBJS) \ + sim-cpu.o \ + sim-hload.o \ + sim-hrw.o \ + sim-model.o \ + sim-reg.o \ + cgen-utils.o cgen-trace.o cgen-scache.o cgen-fpu.o cgen-accfp.o \ + cgen-run.o sim-reason.o sim-engine.o sim-stop.o \ + sim-if.o arch.o \ + $(FRV_OBJS) \ + traps.o interrupts.o memory.o cache.o pipeline.o \ + profile.o profile-fr400.o profile-fr500.o profile-fr550.o options.o \ + devices.o reset.o registers.o \ + $(CONFIG_DEVICES) + +# Extra headers included by sim-main.h. +SIM_EXTRA_DEPS = \ + $(CGEN_INCLUDE_DEPS) \ + arch.h cpuall.h frv-sim.h $(srcdir)/../../opcodes/frv-desc.h cache.h \ + registers.h profile.h \ + $(sim-options_h) + +SIM_EXTRA_CFLAGS = @sim_trapdump@ + +SIM_RUN_OBJS = nrun.o +SIM_EXTRA_CLEAN = frv-clean + +# This selects the frv newlib/libgloss syscall definitions. +NL_TARGET = -DNL_TARGET_frv + +## COMMON_POST_CONFIG_FRAG + +arch = frv + +arch.o: arch.c $(SIM_MAIN_DEPS) + +devices.o: devices.c $(SIM_MAIN_DEPS) + +# FRV objs + +FRVBF_INCLUDE_DEPS = \ + $(CGEN_MAIN_CPU_DEPS) \ + $(SIM_EXTRA_DEPS) \ + cpu.h decode.h eng.h + +frv.o: frv.c $(FRVBF_INCLUDE_DEPS) +traps.o: traps.c $(FRVBF_INCLUDE_DEPS) +pipeline.o: pipeline.c $(FRVBF_INCLUDE_DEPS) +interrupts.o: interrupts.c $(FRVBF_INCLUDE_DEPS) +memory.o: memory.c $(FRVBF_INCLUDE_DEPS) +cache.o: cache.c $(FRVBF_INCLUDE_DEPS) +options.o: options.c $(FRVBF_INCLUDE_DEPS) +reset.o: reset.c $(FRVBF_INCLUDE_DEPS) +registers.o: registers.c $(FRVBF_INCLUDE_DEPS) +profile.o: profile.c profile-fr400.h profile-fr500.h profile-fr550.h $(FRVBF_INCLUDE_DEPS) +profile-fr400.o: profile-fr400.c profile-fr400.h $(FRVBF_INCLUDE_DEPS) +profile-fr500.o: profile-fr500.c profile-fr500.h $(FRVBF_INCLUDE_DEPS) +profile-fr550.o: profile-fr550.c profile-fr550.h $(FRVBF_INCLUDE_DEPS) +sim-if.o: sim-if.c $(FRVBF_INCLUDE_DEPS) $(srcdir)/../common/sim-core.h eng.h + + +# FIXME: Use of `mono' is wip. +mloop.c eng.h: stamp-mloop +stamp-mloop: $(srcdir)/../common/genmloop.sh mloop.in Makefile + $(SHELL) $(srccom)/genmloop.sh \ + -mono -scache -parallel-generic-write -parallel-only \ + -cpu frvbf -infile $(srcdir)/mloop.in + $(SHELL) $(srcroot)/move-if-change eng.hin eng.h + $(SHELL) $(srcroot)/move-if-change mloop.cin mloop.c + touch stamp-mloop +mloop.o: mloop.c $(FRVBF_INCLUDE_DEPS) + +cpu.o: cpu.c $(FRVBF_INCLUDE_DEPS) +decode.o: decode.c $(FRVBF_INCLUDE_DEPS) +sem.o: sem.c $(FRVBF_INCLUDE_DEPS) +model.o: model.c $(FRVBF_INCLUDE_DEPS) + +frv-clean: + rm -f mloop.c eng.h stamp-mloop + rm -f tmp-* + rm -f stamp-arch stamp-cpu + +# cgen support, enable with --enable-cgen-maint +CGEN_MAINT = ; @true +# The following line is commented in or out depending upon --enable-cgen-maint. +@CGEN_MAINT@CGEN_MAINT = + +stamp-arch: $(CGEN_READ_SCM) $(CGEN_ARCH_SCM) $(srcdir)/../../cpu/frv.cpu + $(MAKE) cgen-arch $(CGEN_FLAGS_TO_PASS) mach=all \ + archfile=$(srcdir)/../../cpu/frv.cpu \ + FLAGS="with-scache" + touch stamp-arch +arch.h arch.c cpuall.h: $(CGEN_MAINT) stamp-arch +# @true + +stamp-cpu: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(srcdir)/../../cpu/frv.cpu + $(MAKE) cgen-cpu-decode $(CGEN_FLAGS_TO_PASS) \ + cpu=frvbf mach=frv,fr550,fr500,fr400,tomcat,simple SUFFIX= \ + archfile=$(srcdir)/../../cpu/frv.cpu \ + FLAGS="with-scache with-profile=fn with-generic-write with-parallel-only" \ + EXTRAFILES="$(CGEN_CPU_SEM)" + touch stamp-cpu +cpu.h sem.c model.c decode.c decode.h: $(CGEN_MAINT) stamp-cpu +# @true diff --git a/sim/frv/README b/sim/frv/README new file mode 100644 index 0000000..a88ea19 --- /dev/null +++ b/sim/frv/README @@ -0,0 +1,10 @@ +This is the frv simulator directory. + +It is still work-in-progress. The current sources are +well tested and lots of features are in. + +There are lots of machine generated files in the source directory! +They are only generated if you configure with --enable-cgen-maint, +similar in behaviour to Makefile.in, configure under automake/autoconf. + +For details on the generator, see ../../cgen. diff --git a/sim/frv/TODO b/sim/frv/TODO new file mode 100644 index 0000000..6aa400b --- /dev/null +++ b/sim/frv/TODO @@ -0,0 +1,8 @@ +- header file dependencies revisit +- hooks cleanup +- testsuites +- FIXME's +- memory accesses still test if profiling is on even in fast mode +- have semantic code use G/SET_H_FOO if not default [incl fun-access] +- have G/SET_H_FOO macros call function if fun-access +- --> can always use G/S_H_FOO macros diff --git a/sim/frv/arch.c b/sim/frv/arch.c new file mode 100644 index 0000000..d0ac82f --- /dev/null +++ b/sim/frv/arch.c @@ -0,0 +1,50 @@ +/* Simulator support for frv. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. + +This file is part of the GNU simulators. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +*/ + +#include "sim-main.h" +#include "bfd.h" + +const MACH *sim_machs[] = +{ +#ifdef HAVE_CPU_FRVBF + & frv_mach, +#endif +#ifdef HAVE_CPU_FRVBF + & fr550_mach, +#endif +#ifdef HAVE_CPU_FRVBF + & fr500_mach, +#endif +#ifdef HAVE_CPU_FRVBF + & tomcat_mach, +#endif +#ifdef HAVE_CPU_FRVBF + & fr400_mach, +#endif +#ifdef HAVE_CPU_FRVBF + & simple_mach, +#endif + 0 +}; + diff --git a/sim/frv/arch.h b/sim/frv/arch.h new file mode 100644 index 0000000..6f26965 --- /dev/null +++ b/sim/frv/arch.h @@ -0,0 +1,82 @@ +/* Simulator header for frv. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. + +This file is part of the GNU simulators. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +*/ + +#ifndef FRV_ARCH_H +#define FRV_ARCH_H + +#define TARGET_BIG_ENDIAN 1 + +/* Enum declaration for model types. */ +typedef enum model_type { + MODEL_FRV, MODEL_FR550, MODEL_FR500, MODEL_TOMCAT + , MODEL_FR400, MODEL_SIMPLE, MODEL_MAX +} MODEL_TYPE; + +#define MAX_MODELS ((int) MODEL_MAX) + +/* Enum declaration for unit types. */ +typedef enum unit_type { + UNIT_NONE, UNIT_FRV_U_EXEC, UNIT_FR550_U_MEDIA_4_QUAD, UNIT_FR550_U_MEDIA_4_ADD_SUB_DUAL + , UNIT_FR550_U_MEDIA_4_ADD_SUB, UNIT_FR550_U_MEDIA_4_ACC_DUAL, UNIT_FR550_U_MEDIA_4_ACC, UNIT_FR550_U_MEDIA_4 + , UNIT_FR550_U_MEDIA_SET, UNIT_FR550_U_MEDIA_3_MCLRACC, UNIT_FR550_U_MEDIA_3_WTACC, UNIT_FR550_U_MEDIA_3_ACC_DUAL + , UNIT_FR550_U_MEDIA_3_ACC, UNIT_FR550_U_MEDIA_3_DUAL, UNIT_FR550_U_MEDIA_DUAL_EXPAND, UNIT_FR550_U_MEDIA_QUAD + , UNIT_FR550_U_MEDIA, UNIT_FR550_U_FLOAT_CONVERT, UNIT_FR550_U_COMMIT, UNIT_FR550_U_DCUL + , UNIT_FR550_U_ICUL, UNIT_FR550_U_DCPL, UNIT_FR550_U_ICPL, UNIT_FR550_U_DCF + , UNIT_FR550_U_DCI, UNIT_FR550_U_ICI, UNIT_FR550_U_CLRFR, UNIT_FR550_U_CLRGR + , UNIT_FR550_U_FR2FR, UNIT_FR550_U_SWAP, UNIT_FR550_U_FR_STORE, UNIT_FR550_U_FR_LOAD + , UNIT_FR550_U_GR_STORE, UNIT_FR550_U_GR_LOAD, UNIT_FR550_U_SET_HILO, UNIT_FR550_U_GR2SPR + , UNIT_FR550_U_SPR2GR, UNIT_FR550_U_GR2FR, UNIT_FR550_U_FR2GR, UNIT_FR550_U_FLOAT_DUAL_COMPARE + , UNIT_FR550_U_FLOAT_COMPARE, UNIT_FR550_U_FLOAT_SQRT, UNIT_FR550_U_FLOAT_DIV, UNIT_FR550_U_FLOAT_DUAL_ARITH + , UNIT_FR550_U_FLOAT_ARITH, UNIT_FR550_U_CHECK, UNIT_FR550_U_TRAP, UNIT_FR550_U_BRANCH + , UNIT_FR550_U_IDIV, UNIT_FR550_U_IMUL, UNIT_FR550_U_INTEGER, UNIT_FR550_U_EXEC + , UNIT_FR500_U_COMMIT, UNIT_FR500_U_DCUL, UNIT_FR500_U_ICUL, UNIT_FR500_U_DCPL + , UNIT_FR500_U_ICPL, UNIT_FR500_U_DCF, UNIT_FR500_U_DCI, UNIT_FR500_U_ICI + , UNIT_FR500_U_MEMBAR, UNIT_FR500_U_BARRIER, UNIT_FR500_U_MEDIA_DUAL_BTOHE, UNIT_FR500_U_MEDIA_DUAL_HTOB + , UNIT_FR500_U_MEDIA_DUAL_BTOH, UNIT_FR500_U_MEDIA_DUAL_UNPACK, UNIT_FR500_U_MEDIA_DUAL_EXPAND, UNIT_FR500_U_MEDIA_QUAD_COMPLEX + , UNIT_FR500_U_MEDIA_QUAD_MUL, UNIT_FR500_U_MEDIA_DUAL_MUL, UNIT_FR500_U_MEDIA_QUAD_ARITH, UNIT_FR500_U_MEDIA + , UNIT_FR500_U_FLOAT_DUAL_CONVERT, UNIT_FR500_U_FLOAT_CONVERT, UNIT_FR500_U_FLOAT_DUAL_COMPARE, UNIT_FR500_U_FLOAT_COMPARE + , UNIT_FR500_U_FLOAT_DUAL_SQRT, UNIT_FR500_U_FLOAT_SQRT, UNIT_FR500_U_FLOAT_DIV, UNIT_FR500_U_FLOAT_DUAL_ARITH + , UNIT_FR500_U_FLOAT_ARITH, UNIT_FR500_U_GR2SPR, UNIT_FR500_U_GR2FR, UNIT_FR500_U_SPR2GR + , UNIT_FR500_U_FR2GR, UNIT_FR500_U_FR2FR, UNIT_FR500_U_SWAP, UNIT_FR500_U_FR_R_STORE + , UNIT_FR500_U_FR_STORE, UNIT_FR500_U_FR_LOAD, UNIT_FR500_U_GR_R_STORE, UNIT_FR500_U_GR_STORE + , UNIT_FR500_U_GR_LOAD, UNIT_FR500_U_SET_HILO, UNIT_FR500_U_CLRFR, UNIT_FR500_U_CLRGR + , UNIT_FR500_U_CHECK, UNIT_FR500_U_TRAP, UNIT_FR500_U_BRANCH, UNIT_FR500_U_IDIV + , UNIT_FR500_U_IMUL, UNIT_FR500_U_INTEGER, UNIT_FR500_U_EXEC, UNIT_TOMCAT_U_EXEC + , UNIT_FR400_U_DCUL, UNIT_FR400_U_ICUL, UNIT_FR400_U_DCPL, UNIT_FR400_U_ICPL + , UNIT_FR400_U_DCF, UNIT_FR400_U_DCI, UNIT_FR400_U_ICI, UNIT_FR400_U_MEMBAR + , UNIT_FR400_U_BARRIER, UNIT_FR400_U_MEDIA_DUAL_HTOB, UNIT_FR400_U_MEDIA_DUAL_EXPAND, UNIT_FR400_U_MEDIA_7 + , UNIT_FR400_U_MEDIA_6, UNIT_FR400_U_MEDIA_4_ACC_DUAL, UNIT_FR400_U_MEDIA_4_ACCG, UNIT_FR400_U_MEDIA_4 + , UNIT_FR400_U_MEDIA_3_QUAD, UNIT_FR400_U_MEDIA_3_DUAL, UNIT_FR400_U_MEDIA_3, UNIT_FR400_U_MEDIA_2_ADD_SUB_DUAL + , UNIT_FR400_U_MEDIA_2_ADD_SUB, UNIT_FR400_U_MEDIA_2_ACC_DUAL, UNIT_FR400_U_MEDIA_2_ACC, UNIT_FR400_U_MEDIA_2_QUAD + , UNIT_FR400_U_MEDIA_2, UNIT_FR400_U_MEDIA_HILO, UNIT_FR400_U_MEDIA_1_QUAD, UNIT_FR400_U_MEDIA_1 + , UNIT_FR400_U_GR2SPR, UNIT_FR400_U_GR2FR, UNIT_FR400_U_SPR2GR, UNIT_FR400_U_FR2GR + , UNIT_FR400_U_SWAP, UNIT_FR400_U_FR_STORE, UNIT_FR400_U_FR_LOAD, UNIT_FR400_U_GR_STORE + , UNIT_FR400_U_GR_LOAD, UNIT_FR400_U_SET_HILO, UNIT_FR400_U_CHECK, UNIT_FR400_U_TRAP + , UNIT_FR400_U_BRANCH, UNIT_FR400_U_IDIV, UNIT_FR400_U_IMUL, UNIT_FR400_U_INTEGER + , UNIT_FR400_U_EXEC, UNIT_SIMPLE_U_EXEC, UNIT_MAX +} UNIT_TYPE; + +#define MAX_UNITS (1) + +#endif /* FRV_ARCH_H */ diff --git a/sim/frv/cache.c b/sim/frv/cache.c new file mode 100644 index 0000000..7b2635b --- /dev/null +++ b/sim/frv/cache.c @@ -0,0 +1,1664 @@ +/* frv cache model. + Copyright (C) 1999, 2000, 2001, 2003 Free Software Foundation, Inc. + Contributed by Red Hat. + +This file is part of the GNU simulators. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#define WANT_CPU frvbf +#define WANT_CPU_FRVBF + +#include "libiberty.h" +#include "sim-main.h" +#include "cache.h" +#include "bfd.h" + +void +frv_cache_init (SIM_CPU *cpu, FRV_CACHE *cache) +{ + int elements; + int i, j; + SIM_DESC sd; + + /* Set defaults for fields which are not initialized. */ + sd = CPU_STATE (cpu); + switch (STATE_ARCHITECTURE (sd)->mach) + { + case bfd_mach_fr400: + if (cache->configured_sets == 0) + cache->configured_sets = 128; + if (cache->configured_ways == 0) + cache->configured_ways = 2; + if (cache->line_size == 0) + cache->line_size = 32; + if (cache->memory_latency == 0) + cache->memory_latency = 20; + break; + case bfd_mach_fr550: + if (cache->configured_sets == 0) + cache->configured_sets = 128; + if (cache->configured_ways == 0) + cache->configured_ways = 4; + if (cache->line_size == 0) + cache->line_size = 64; + if (cache->memory_latency == 0) + cache->memory_latency = 20; + break; + default: + if (cache->configured_sets == 0) + cache->configured_sets = 64; + if (cache->configured_ways == 0) + cache->configured_ways = 4; + if (cache->line_size == 0) + cache->line_size = 64; + if (cache->memory_latency == 0) + cache->memory_latency = 20; + break; + } + + frv_cache_reconfigure (cpu, cache); + + /* First allocate the cache storage based on the given dimensions. */ + elements = cache->sets * cache->ways; + cache->tag_storage = (FRV_CACHE_TAG *) + zalloc (elements * sizeof (*cache->tag_storage)); + cache->data_storage = (char *) xmalloc (elements * cache->line_size); + + /* Initialize the pipelines and status buffers. */ + for (i = LS; i < FRV_CACHE_PIPELINES; ++i) + { + cache->pipeline[i].requests = NULL; + cache->pipeline[i].status.flush.valid = 0; + cache->pipeline[i].status.return_buffer.valid = 0; + cache->pipeline[i].status.return_buffer.data + = (char *) xmalloc (cache->line_size); + for (j = FIRST_STAGE; j < FRV_CACHE_STAGES; ++j) + cache->pipeline[i].stages[j].request = NULL; + } + cache->BARS.valid = 0; + cache->NARS.valid = 0; + + /* Now set the cache state. */ + cache->cpu = cpu; + cache->statistics.accesses = 0; + cache->statistics.hits = 0; +} + +void +frv_cache_term (FRV_CACHE *cache) +{ + /* Free the cache storage. */ + free (cache->tag_storage); + free (cache->data_storage); + free (cache->pipeline[LS].status.return_buffer.data); + free (cache->pipeline[LD].status.return_buffer.data); +} + +/* Reset the cache configuration based on registers in the cpu. */ +void +frv_cache_reconfigure (SIM_CPU *current_cpu, FRV_CACHE *cache) +{ + int ihsr8; + int icdm; + SIM_DESC sd; + + /* Set defaults for fields which are not initialized. */ + sd = CPU_STATE (current_cpu); + switch (STATE_ARCHITECTURE (sd)->mach) + { + case bfd_mach_fr550: + if (cache == CPU_INSN_CACHE (current_cpu)) + { + ihsr8 = GET_IHSR8 (); + icdm = GET_IHSR8_ICDM (ihsr8); + /* If IHSR8.ICDM is set, then the cache becomes a one way cache. */ + if (icdm) + { + cache->sets = cache->sets * cache->ways; + cache->ways = 1; + break; + } + } + /* fall through */ + default: + /* Set the cache to its original settings. */ + cache->sets = cache->configured_sets; + cache->ways = cache->configured_ways; + break; + } +} + +/* Determine whether the given cache is enabled. */ +int +frv_cache_enabled (FRV_CACHE *cache) +{ + SIM_CPU *current_cpu = cache->cpu; + int hsr0 = GET_HSR0 (); + if (GET_HSR0_ICE (hsr0) && cache == CPU_INSN_CACHE (current_cpu)) + return 1; + if (GET_HSR0_DCE (hsr0) && cache == CPU_DATA_CACHE (current_cpu)) + return 1; + return 0; +} + +/* Determine whether the given address is RAM access, assuming that HSR0.RME + is set. */ +static int +ram_access (FRV_CACHE *cache, USI address) +{ + int ihsr8; + int cwe; + USI start, end, way_size; + SIM_CPU *current_cpu = cache->cpu; + SIM_DESC sd = CPU_STATE (current_cpu); + + switch (STATE_ARCHITECTURE (sd)->mach) + { + case bfd_mach_fr550: + /* IHSR8.DCWE or IHSR8.ICWE deternines which ways get RAM access. */ + ihsr8 = GET_IHSR8 (); + if (cache == CPU_INSN_CACHE (current_cpu)) + { + start = 0xfe000000; + end = 0xfe008000; + cwe = GET_IHSR8_ICWE (ihsr8); + } + else + { + start = 0xfe400000; + end = 0xfe408000; + cwe = GET_IHSR8_DCWE (ihsr8); + } + way_size = (end - start) / 4; + end -= way_size * cwe; + return address >= start && address < end; + default: + break; + } + + return 1; /* RAM access */ +} + +/* Determine whether the given address should be accessed without using + the cache. */ +static int +non_cache_access (FRV_CACHE *cache, USI address) +{ + int hsr0; + SIM_DESC sd; + SIM_CPU *current_cpu = cache->cpu; + + sd = CPU_STATE (current_cpu); + switch (STATE_ARCHITECTURE (sd)->mach) + { + case bfd_mach_fr400: + if (address >= 0xff000000 + || address >= 0xfe000000 && address <= 0xfeffffff) + return 1; /* non-cache access */ + case bfd_mach_fr550: + if (address >= 0xff000000 + || address >= 0xfeff0000 && address <= 0xfeffffff) + return 1; /* non-cache access */ + if (cache == CPU_INSN_CACHE (current_cpu)) + { + if (address >= 0xfe000000 && address <= 0xfe007fff) + return 1; /* non-cache access */ + } + else if (address >= 0xfe400000 && address <= 0xfe407fff) + return 1; /* non-cache access */ + default: + if (address >= 0xff000000 + || address >= 0xfeff0000 && address <= 0xfeffffff) + return 1; /* non-cache access */ + if (cache == CPU_INSN_CACHE (current_cpu)) + { + if (address >= 0xfe000000 && address <= 0xfe003fff) + return 1; /* non-cache access */ + } + else if (address >= 0xfe400000 && address <= 0xfe403fff) + return 1; /* non-cache access */ + } + + hsr0 = GET_HSR0 (); + if (GET_HSR0_RME (hsr0)) + return ram_access (cache, address); + + return 0; /* cache-access */ +} + +/* Find the cache line corresponding to the given address. + If it is found then 'return_tag' is set to point to the tag for that line + and 1 is returned. + If it is not found, 'return_tag' is set to point to the tag for the least + recently used line and 0 is returned. +*/ +static int +get_tag (FRV_CACHE *cache, SI address, FRV_CACHE_TAG **return_tag) +{ + int set; + int way; + int bits; + USI tag; + FRV_CACHE_TAG *found; + FRV_CACHE_TAG *available; + + ++cache->statistics.accesses; + + /* First calculate which set this address will fall into. Do this by + shifting out the bits representing the offset within the line and + then keeping enough bits to index the set. */ + set = address & ~(cache->line_size - 1); + for (bits = cache->line_size - 1; bits != 0; bits >>= 1) + set >>= 1; + set &= (cache->sets - 1); + + /* Now search the set for a valid tag which matches this address. At the + same time make note of the least recently used tag, which we will return + if no match is found. */ + available = NULL; + tag = CACHE_ADDRESS_TAG (cache, address); + for (way = 0; way < cache->ways; ++way) + { + found = CACHE_TAG (cache, set, way); + /* This tag is available as the least recently used if it is the + least recently used seen so far and it is not locked. */ + if (! found->locked && (available == NULL || available->lru > found->lru)) + available = found; + if (found->valid && found->tag == tag) + { + *return_tag = found; + ++cache->statistics.hits; + return 1; /* found it */ + } + } + + *return_tag = available; + return 0; /* not found */ +} + +/* Write the given data out to memory. */ +static void +write_data_to_memory (FRV_CACHE *cache, SI address, char *data, int length) +{ + SIM_CPU *cpu = cache->cpu; + IADDR pc = CPU_PC_GET (cpu); + int write_index = 0; + + switch (length) + { + case 1: + default: + PROFILE_COUNT_WRITE (cpu, address, MODE_QI); + break; + case 2: + PROFILE_COUNT_WRITE (cpu, address, MODE_HI); + break; + case 4: + PROFILE_COUNT_WRITE (cpu, address, MODE_SI); + break; + case 8: + PROFILE_COUNT_WRITE (cpu, address, MODE_DI); + break; + } + + for (write_index = 0; write_index < length; ++write_index) + { + /* TODO: Better way to copy memory than a byte at a time? */ + sim_core_write_unaligned_1 (cpu, pc, write_map, address + write_index, + data[write_index]); + } +} + +/* Write a cache line out to memory. */ +static void +write_line_to_memory (FRV_CACHE *cache, FRV_CACHE_TAG *tag) +{ + SI address = tag->tag; + int set = CACHE_TAG_SET_NUMBER (cache, tag); + int bits; + for (bits = cache->line_size - 1; bits != 0; bits >>= 1) + set <<= 1; + address |= set; + write_data_to_memory (cache, address, tag->line, cache->line_size); +} + +static void +read_data_from_memory (SIM_CPU *current_cpu, SI address, char *buffer, + int length) +{ + PCADDR pc = CPU_PC_GET (current_cpu); + int i; + PROFILE_COUNT_READ (current_cpu, address, MODE_QI); + for (i = 0; i < length; ++i) + { + /* TODO: Better way to copy memory than a byte at a time? */ + buffer[i] = sim_core_read_unaligned_1 (current_cpu, pc, read_map, + address + i); + } +} + +/* Fill the given cache line from memory. */ +static void +fill_line_from_memory (FRV_CACHE *cache, FRV_CACHE_TAG *tag, SI address) +{ + PCADDR pc; + int line_alignment; + SI read_address; + SIM_CPU *current_cpu = cache->cpu; + + /* If this line is already valid and the cache is in copy-back mode, then + write this line to memory before refilling it. + Check the dirty bit first, since it is less likely to be set. */ + if (tag->dirty && tag->valid) + { + int hsr0 = GET_HSR0 (); + if (GET_HSR0_CBM (hsr0)) + write_line_to_memory (cache, tag); + } + else if (tag->line == NULL) + { + int line_index = tag - cache->tag_storage; + tag->line = cache->data_storage + (line_index * cache->line_size); + } + + pc = CPU_PC_GET (current_cpu); + line_alignment = cache->line_size - 1; + read_address = address & ~line_alignment; + read_data_from_memory (current_cpu, read_address, tag->line, + cache->line_size); + tag->tag = CACHE_ADDRESS_TAG (cache, address); + tag->valid = 1; +} + +/* Update the LRU information for the tags in the same set as the given tag. */ +static void +set_most_recently_used (FRV_CACHE *cache, FRV_CACHE_TAG *tag) +{ + /* All tags in the same set are contiguous, so find the beginning of the + set by aligning to the size of a set. */ + FRV_CACHE_TAG *item = cache->tag_storage + CACHE_TAG_SET_START (cache, tag); + FRV_CACHE_TAG *limit = item + cache->ways; + + while (item < limit) + { + if (item->lru > tag->lru) + --item->lru; + ++item; + } + tag->lru = cache->ways; /* Mark as most recently used. */ +} + +/* Update the LRU information for the tags in the same set as the given tag. */ +static void +set_least_recently_used (FRV_CACHE *cache, FRV_CACHE_TAG *tag) +{ + /* All tags in the same set are contiguous, so find the beginning of the + set by aligning to the size of a set. */ + FRV_CACHE_TAG *item = cache->tag_storage + CACHE_TAG_SET_START (cache, tag); + FRV_CACHE_TAG *limit = item + cache->ways; + + while (item < limit) + { + if (item->lru != 0 && item->lru < tag->lru) + ++item->lru; + ++item; + } + tag->lru = 0; /* Mark as least recently used. */ +} + +/* Find the line containing the given address and load it if it is not + already loaded. + Returns the tag of the requested line. */ +static FRV_CACHE_TAG * +find_or_retrieve_cache_line (FRV_CACHE *cache, SI address) +{ + /* See if this data is already in the cache. */ + FRV_CACHE_TAG *tag; + int found = get_tag (cache, address, &tag); + + /* Fill the line from memory, if it is not valid. */ + if (! found) + { + /* The tag could be NULL is all ways in the set were used and locked. */ + if (tag == NULL) + return tag; + + fill_line_from_memory (cache, tag, address); + tag->dirty = 0; + } + + /* Update the LRU information for the tags in this set. */ + set_most_recently_used (cache, tag); + + return tag; +} + +static void +copy_line_to_return_buffer (FRV_CACHE *cache, int pipe, FRV_CACHE_TAG *tag, + SI address) +{ + /* A cache line was available for the data. + Copy the data from the cache line to the output buffer. */ + memcpy (cache->pipeline[pipe].status.return_buffer.data, + tag->line, cache->line_size); + cache->pipeline[pipe].status.return_buffer.address + = address & ~(cache->line_size - 1); + cache->pipeline[pipe].status.return_buffer.valid = 1; +} + +static void +copy_memory_to_return_buffer (FRV_CACHE *cache, int pipe, SI address) +{ + address &= ~(cache->line_size - 1); + read_data_from_memory (cache->cpu, address, + cache->pipeline[pipe].status.return_buffer.data, + cache->line_size); + cache->pipeline[pipe].status.return_buffer.address = address; + cache->pipeline[pipe].status.return_buffer.valid = 1; +} + +static void +set_return_buffer_reqno (FRV_CACHE *cache, int pipe, unsigned reqno) +{ + cache->pipeline[pipe].status.return_buffer.reqno = reqno; +} + +/* Read data from the given cache. + Returns the number of cycles required to obtain the data. */ +int +frv_cache_read (FRV_CACHE *cache, int pipe, SI address) +{ + FRV_CACHE_TAG *tag; + + if (non_cache_access (cache, address)) + { + copy_memory_to_return_buffer (cache, pipe, address); + return 1; + } + + tag = find_or_retrieve_cache_line (cache, address); + + if (tag == NULL) + return 0; /* Indicate non-cache-access. */ + + /* A cache line was available for the data. + Copy the data from the cache line to the output buffer. */ + copy_line_to_return_buffer (cache, pipe, tag, address); + + return 1; /* TODO - number of cycles unknown */ +} + +/* Writes data through the given cache. + The data is assumed to be in target endian order. + Returns the number of cycles required to write the data. */ +int +frv_cache_write (FRV_CACHE *cache, SI address, char *data, unsigned length) +{ + int copy_back; + + /* See if this data is already in the cache. */ + SIM_CPU *current_cpu = cache->cpu; + USI hsr0 = GET_HSR0 (); + FRV_CACHE_TAG *tag; + int found; + + if (non_cache_access (cache, address)) + { + write_data_to_memory (cache, address, data, length); + return 1; + } + + found = get_tag (cache, address, &tag); + + /* Write the data to the cache line if one was available and if it is + either a hit or a miss in copy-back mode. + The tag may be NULL if all ways were in use and locked on a miss. + */ + copy_back = GET_HSR0_CBM (GET_HSR0 ()); + if (tag != NULL && (found || copy_back)) + { + int line_offset; + /* Load the line from memory first, if it was a miss. */ + if (! found) + fill_line_from_memory (cache, tag, address); + line_offset = address & (cache->line_size - 1); + memcpy (tag->line + line_offset, data, length); + tag->dirty = 1; + + /* Update the LRU information for the tags in this set. */ + set_most_recently_used (cache, tag); + } + + /* Write the data to memory if there was no line available or we are in + write-through (not copy-back mode). */ + if (tag == NULL || ! copy_back) + { + write_data_to_memory (cache, address, data, length); + if (tag != NULL) + tag->dirty = 0; + } + + return 1; /* TODO - number of cycles unknown */ +} + +/* Preload the cache line containing the given address. Lock the + data if requested. + Returns the number of cycles required to write the data. */ +int +frv_cache_preload (FRV_CACHE *cache, SI address, USI length, int lock) +{ + int offset; + int lines; + + if (non_cache_access (cache, address)) + return 1; + + /* preload at least 1 line. */ + if (length == 0) + length = 1; + + offset = address & (cache->line_size - 1); + lines = 1 + (offset + length - 1) / cache->line_size; + + /* Careful with this loop -- length is unsigned. */ + for (/**/; lines > 0; --lines) + { + FRV_CACHE_TAG *tag = find_or_retrieve_cache_line (cache, address); + if (lock && tag != NULL) + tag->locked = 1; + address += cache->line_size; + } + + return 1; /* TODO - number of cycles unknown */ +} + +/* Unlock the cache line containing the given address. + Returns the number of cycles required to unlock the line. */ +int +frv_cache_unlock (FRV_CACHE *cache, SI address) +{ + FRV_CACHE_TAG *tag; + int found; + + if (non_cache_access (cache, address)) + return 1; + + found = get_tag (cache, address, &tag); + + if (found) + tag->locked = 0; + + return 1; /* TODO - number of cycles unknown */ +} + +static void +invalidate_return_buffer (FRV_CACHE *cache, SI address) +{ + /* If this address is in one of the return buffers, then invalidate that + return buffer. */ + address &= ~(cache->line_size - 1); + if (address == cache->pipeline[LS].status.return_buffer.address) + cache->pipeline[LS].status.return_buffer.valid = 0; + if (address == cache->pipeline[LD].status.return_buffer.address) + cache->pipeline[LD].status.return_buffer.valid = 0; +} + +/* Invalidate the cache line containing the given address. Flush the + data if requested. + Returns the number of cycles required to write the data. */ +int +frv_cache_invalidate (FRV_CACHE *cache, SI address, int flush) +{ + /* See if this data is already in the cache. */ + FRV_CACHE_TAG *tag; + int found; + + /* Check for non-cache access. This operation is still perfromed even if + the cache is not currently enabled. */ + if (non_cache_access (cache, address)) + return 1; + + /* If the line is found, invalidate it. If a flush is requested, then flush + it if it is dirty. */ + found = get_tag (cache, address, &tag); + if (found) + { + SIM_CPU *cpu; + /* If a flush is requested, then flush it if it is dirty. */ + if (tag->dirty && flush) + write_line_to_memory (cache, tag); + set_least_recently_used (cache, tag); + tag->valid = 0; + tag->locked = 0; + + /* If this is the insn cache, then flush the cpu's scache as well. */ + cpu = cache->cpu; + if (cache == CPU_INSN_CACHE (cpu)) + scache_flush_cpu (cpu); + } + + invalidate_return_buffer (cache, address); + + return 1; /* TODO - number of cycles unknown */ +} + +/* Invalidate the entire cache. Flush the data if requested. */ +int +frv_cache_invalidate_all (FRV_CACHE *cache, int flush) +{ + /* See if this data is already in the cache. */ + int elements = cache->sets * cache->ways; + FRV_CACHE_TAG *tag = cache->tag_storage; + SIM_CPU *cpu; + int i; + + for(i = 0; i < elements; ++i, ++tag) + { + /* If a flush is requested, then flush it if it is dirty. */ + if (tag->valid && tag->dirty && flush) + write_line_to_memory (cache, tag); + tag->valid = 0; + tag->locked = 0; + } + + + /* If this is the insn cache, then flush the cpu's scache as well. */ + cpu = cache->cpu; + if (cache == CPU_INSN_CACHE (cpu)) + scache_flush_cpu (cpu); + + /* Invalidate both return buffers. */ + cache->pipeline[LS].status.return_buffer.valid = 0; + cache->pipeline[LD].status.return_buffer.valid = 0; + + return 1; /* TODO - number of cycles unknown */ +} + +/* --------------------------------------------------------------------------- + Functions for operating the cache in cycle accurate mode. + ------------------------------------------------------------------------- */ +/* Convert a VLIW slot to a cache pipeline index. */ +static int +convert_slot_to_index (int slot) +{ + switch (slot) + { + case UNIT_I0: + case UNIT_C: + return LS; + case UNIT_I1: + return LD; + default: + abort (); + } + return 0; +} + +/* Allocate free chains of cache requests. */ +#define FREE_CHAIN_SIZE 16 +static FRV_CACHE_REQUEST *frv_cache_request_free_chain = NULL; +static FRV_CACHE_REQUEST *frv_store_request_free_chain = NULL; + +static void +allocate_new_cache_requests (void) +{ + int i; + frv_cache_request_free_chain = xmalloc (FREE_CHAIN_SIZE + * sizeof (FRV_CACHE_REQUEST)); + for (i = 0; i < FREE_CHAIN_SIZE - 1; ++i) + { + frv_cache_request_free_chain[i].next + = & frv_cache_request_free_chain[i + 1]; + } + + frv_cache_request_free_chain[FREE_CHAIN_SIZE - 1].next = NULL; +} + +/* Return the next free request in the queue for the given cache pipeline. */ +static FRV_CACHE_REQUEST * +new_cache_request (void) +{ + FRV_CACHE_REQUEST *req; + + /* Allocate new elements for the free chain if necessary. */ + if (frv_cache_request_free_chain == NULL) + allocate_new_cache_requests (); + + req = frv_cache_request_free_chain; + frv_cache_request_free_chain = req->next; + + return req; +} + +/* Return the given cache request to the free chain. */ +static void +free_cache_request (FRV_CACHE_REQUEST *req) +{ + if (req->kind == req_store) + { + req->next = frv_store_request_free_chain; + frv_store_request_free_chain = req; + } + else + { + req->next = frv_cache_request_free_chain; + frv_cache_request_free_chain = req; + } +} + +/* Search the free chain for an existing store request with a buffer that's + large enough. */ +static FRV_CACHE_REQUEST * +new_store_request (int length) +{ + FRV_CACHE_REQUEST *prev = NULL; + FRV_CACHE_REQUEST *req; + for (req = frv_store_request_free_chain; req != NULL; req = req->next) + { + if (req->u.store.length == length) + break; + prev = req; + } + if (req != NULL) + { + if (prev == NULL) + frv_store_request_free_chain = req->next; + else + prev->next = req->next; + return req; + } + + /* No existing request buffer was found, so make a new one. */ + req = new_cache_request (); + req->kind = req_store; + req->u.store.data = xmalloc (length); + req->u.store.length = length; + return req; +} + +/* Remove the given request from the given pipeline. */ +static void +pipeline_remove_request (FRV_CACHE_PIPELINE *p, FRV_CACHE_REQUEST *request) +{ + FRV_CACHE_REQUEST *next = request->next; + FRV_CACHE_REQUEST *prev = request->prev; + + if (prev == NULL) + p->requests = next; + else + prev->next = next; + + if (next != NULL) + next->prev = prev; +} + +/* Add the given request to the given pipeline. */ +static void +pipeline_add_request (FRV_CACHE_PIPELINE *p, FRV_CACHE_REQUEST *request) +{ + FRV_CACHE_REQUEST *prev = NULL; + FRV_CACHE_REQUEST *item; + + /* Add the request in priority order. 0 is the highest priority. */ + for (item = p->requests; item != NULL; item = item->next) + { + if (item->priority > request->priority) + break; + prev = item; + } + + request->next = item; + request->prev = prev; + if (prev == NULL) + p->requests = request; + else + prev->next = request; + if (item != NULL) + item->prev = request; +} + +/* Requeu the given request from the last of the given pipeline. */ +static void +pipeline_requeue_request (FRV_CACHE_PIPELINE *p) +{ + FRV_CACHE_STAGE *stage = & p->stages[LAST_STAGE]; + FRV_CACHE_REQUEST *req = stage->request; + stage->request = NULL; + pipeline_add_request (p, req); +} + +/* Return the priority lower than the lowest one in this cache pipeline. + 0 is the highest priority. */ +static int +next_priority (FRV_CACHE *cache, FRV_CACHE_PIPELINE *pipeline) +{ + int i, j; + int pipe; + int lowest = 0; + FRV_CACHE_REQUEST *req; + + /* Check the priorities of any queued items. */ + for (req = pipeline->requests; req != NULL; req = req->next) + if (req->priority > lowest) + lowest = req->priority; + + /* Check the priorities of items in the pipeline stages. */ + for (i = FIRST_STAGE; i < FRV_CACHE_STAGES; ++i) + { + FRV_CACHE_STAGE *stage = & pipeline->stages[i]; + if (stage->request != NULL && stage->request->priority > lowest) + lowest = stage->request->priority; + } + + /* Check the priorities of load requests waiting in WAR. These are one + higher than the request that spawned them. */ + for (i = 0; i < NUM_WARS; ++i) + { + FRV_CACHE_WAR *war = & pipeline->WAR[i]; + if (war->valid && war->priority > lowest) + lowest = war->priority + 1; + } + + /* Check the priorities of any BARS or NARS associated with this pipeline. + These are one higher than the request that spawned them. */ + pipe = pipeline - cache->pipeline; + if (cache->BARS.valid && cache->BARS.pipe == pipe + && cache->BARS.priority > lowest) + lowest = cache->BARS.priority + 1; + if (cache->NARS.valid && cache->NARS.pipe == pipe + && cache->NARS.priority > lowest) + lowest = cache->NARS.priority + 1; + + /* Return a priority 2 lower than the lowest found. This allows a WAR + request to be generated with a priority greater than this but less than + the next higher priority request. */ + return lowest + 2; +} + +static void +add_WAR_request (FRV_CACHE_PIPELINE* pipeline, FRV_CACHE_WAR *war) +{ + /* Add the load request to the indexed pipeline. */ + FRV_CACHE_REQUEST *req = new_cache_request (); + req->kind = req_WAR; + req->reqno = war->reqno; + req->priority = war->priority; + req->address = war->address; + req->u.WAR.preload = war->preload; + req->u.WAR.lock = war->lock; + pipeline_add_request (pipeline, req); +} + +/* Remove the next request from the given pipeline and return it. */ +static FRV_CACHE_REQUEST * +pipeline_next_request (FRV_CACHE_PIPELINE *p) +{ + FRV_CACHE_REQUEST *first = p->requests; + if (first != NULL) + pipeline_remove_request (p, first); + return first; +} + +/* Return the request which is at the given stage of the given pipeline. */ +static FRV_CACHE_REQUEST * +pipeline_stage_request (FRV_CACHE_PIPELINE *p, int stage) +{ + return p->stages[stage].request; +} + +static void +advance_pipelines (FRV_CACHE *cache) +{ + int stage; + int pipe; + FRV_CACHE_PIPELINE *pipelines = cache->pipeline; + + /* Free the final stage requests. */ + for (pipe = 0; pipe < FRV_CACHE_PIPELINES; ++pipe) + { + FRV_CACHE_REQUEST *req = pipelines[pipe].stages[LAST_STAGE].request; + if (req != NULL) + free_cache_request (req); + } + + /* Shuffle the requests along the pipeline. */ + for (stage = LAST_STAGE; stage > FIRST_STAGE; --stage) + { + for (pipe = 0; pipe < FRV_CACHE_PIPELINES; ++pipe) + pipelines[pipe].stages[stage] = pipelines[pipe].stages[stage - 1]; + } + + /* Add a new request to the pipeline. */ + for (pipe = 0; pipe < FRV_CACHE_PIPELINES; ++pipe) + pipelines[pipe].stages[FIRST_STAGE].request + = pipeline_next_request (& pipelines[pipe]); +} + +/* Handle a request for a load from the given address. */ +void +frv_cache_request_load (FRV_CACHE *cache, unsigned reqno, SI address, int slot) +{ + FRV_CACHE_REQUEST *req; + + /* slot is a UNIT_*. Convert it to a cache pipeline index. */ + int pipe = convert_slot_to_index (slot); + FRV_CACHE_PIPELINE *pipeline = & cache->pipeline[pipe]; + + /* Add the load request to the indexed pipeline. */ + req = new_cache_request (); + req->kind = req_load; + req->reqno = reqno; + req->priority = next_priority (cache, pipeline); + req->address = address; + + pipeline_add_request (pipeline, req); +} + +void +frv_cache_request_store (FRV_CACHE *cache, SI address, + int slot, char *data, unsigned length) +{ + FRV_CACHE_REQUEST *req; + + /* slot is a UNIT_*. Convert it to a cache pipeline index. */ + int pipe = convert_slot_to_index (slot); + FRV_CACHE_PIPELINE *pipeline = & cache->pipeline[pipe]; + + /* Add the load request to the indexed pipeline. */ + req = new_store_request (length); + req->kind = req_store; + req->reqno = NO_REQNO; + req->priority = next_priority (cache, pipeline); + req->address = address; + req->u.store.length = length; + memcpy (req->u.store.data, data, length); + + pipeline_add_request (pipeline, req); + invalidate_return_buffer (cache, address); +} + +/* Handle a request to invalidate the cache line containing the given address. + Flush the data if requested. */ +void +frv_cache_request_invalidate (FRV_CACHE *cache, unsigned reqno, SI address, + int slot, int all, int flush) +{ + FRV_CACHE_REQUEST *req; + + /* slot is a UNIT_*. Convert it to a cache pipeline index. */ + int pipe = convert_slot_to_index (slot); + FRV_CACHE_PIPELINE *pipeline = & cache->pipeline[pipe]; + + /* Add the load request to the indexed pipeline. */ + req = new_cache_request (); + req->kind = req_invalidate; + req->reqno = reqno; + req->priority = next_priority (cache, pipeline); + req->address = address; + req->u.invalidate.all = all; + req->u.invalidate.flush = flush; + + pipeline_add_request (pipeline, req); +} + +/* Handle a request to preload the cache line containing the given address. */ +void +frv_cache_request_preload (FRV_CACHE *cache, SI address, + int slot, int length, int lock) +{ + FRV_CACHE_REQUEST *req; + + /* slot is a UNIT_*. Convert it to a cache pipeline index. */ + int pipe = convert_slot_to_index (slot); + FRV_CACHE_PIPELINE *pipeline = & cache->pipeline[pipe]; + + /* Add the load request to the indexed pipeline. */ + req = new_cache_request (); + req->kind = req_preload; + req->reqno = NO_REQNO; + req->priority = next_priority (cache, pipeline); + req->address = address; + req->u.preload.length = length; + req->u.preload.lock = lock; + + pipeline_add_request (pipeline, req); + invalidate_return_buffer (cache, address); +} + +/* Handle a request to unlock the cache line containing the given address. */ +void +frv_cache_request_unlock (FRV_CACHE *cache, SI address, int slot) +{ + FRV_CACHE_REQUEST *req; + + /* slot is a UNIT_*. Convert it to a cache pipeline index. */ + int pipe = convert_slot_to_index (slot); + FRV_CACHE_PIPELINE *pipeline = & cache->pipeline[pipe]; + + /* Add the load request to the indexed pipeline. */ + req = new_cache_request (); + req->kind = req_unlock; + req->reqno = NO_REQNO; + req->priority = next_priority (cache, pipeline); + req->address = address; + + pipeline_add_request (pipeline, req); +} + +/* Check whether this address interferes with a pending request of + higher priority. */ +static int +address_interference (FRV_CACHE *cache, SI address, FRV_CACHE_REQUEST *req, + int pipe) +{ + int i, j; + int line_mask = ~(cache->line_size - 1); + int other_pipe; + int priority = req->priority; + FRV_CACHE_REQUEST *other_req; + SI other_address; + SI all_address; + + address &= line_mask; + all_address = -1 & line_mask; + + /* Check for collisions in the queue for this pipeline. */ + for (other_req = cache->pipeline[pipe].requests; + other_req != NULL; + other_req = other_req->next) + { + other_address = other_req->address & line_mask; + if ((address == other_address || address == all_address) + && priority > other_req->priority) + return 1; + } + + /* Check for a collision in the the other pipeline. */ + other_pipe = pipe ^ 1; + other_req = cache->pipeline[other_pipe].stages[LAST_STAGE].request; + if (other_req != NULL) + { + other_address = other_req->address & line_mask; + if (address == other_address || address == all_address) + return 1; + } + + /* Check for a collision with load requests waiting in WAR. */ + for (i = LS; i < FRV_CACHE_PIPELINES; ++i) + { + for (j = 0; j < NUM_WARS; ++j) + { + FRV_CACHE_WAR *war = & cache->pipeline[i].WAR[j]; + if (war->valid + && (address == (war->address & line_mask) + || address == all_address) + && priority > war->priority) + return 1; + } + /* If this is not a WAR request, then yield to any WAR requests in + either pipeline or to a higher priority request in the same pipeline. + */ + if (req->kind != req_WAR) + { + for (j = FIRST_STAGE; j < FRV_CACHE_STAGES; ++j) + { + other_req = cache->pipeline[i].stages[j].request; + if (other_req != NULL) + { + if (other_req->kind == req_WAR) + return 1; + if (i == pipe + && (address == (other_req->address & line_mask) + || address == all_address) + && priority > other_req->priority) + return 1; + } + } + } + } + + /* Check for a collision with load requests waiting in ARS. */ + if (cache->BARS.valid + && (address == (cache->BARS.address & line_mask) + || address == all_address) + && priority > cache->BARS.priority) + return 1; + if (cache->NARS.valid + && (address == (cache->NARS.address & line_mask) + || address == all_address) + && priority > cache->NARS.priority) + return 1; + + return 0; +} + +/* Wait for a free WAR register in BARS or NARS. */ +static void +wait_for_WAR (FRV_CACHE* cache, int pipe, FRV_CACHE_REQUEST *req) +{ + FRV_CACHE_WAR war; + FRV_CACHE_PIPELINE *pipeline = & cache->pipeline[pipe]; + + if (! cache->BARS.valid) + { + cache->BARS.pipe = pipe; + cache->BARS.reqno = req->reqno; + cache->BARS.address = req->address; + cache->BARS.priority = req->priority - 1; + switch (req->kind) + { + case req_load: + cache->BARS.preload = 0; + cache->BARS.lock = 0; + break; + case req_store: + cache->BARS.preload = 1; + cache->BARS.lock = 0; + break; + case req_preload: + cache->BARS.preload = 1; + cache->BARS.lock = req->u.preload.lock; + break; + } + cache->BARS.valid = 1; + return; + } + if (! cache->NARS.valid) + { + cache->NARS.pipe = pipe; + cache->NARS.reqno = req->reqno; + cache->NARS.address = req->address; + cache->NARS.priority = req->priority - 1; + switch (req->kind) + { + case req_load: + cache->NARS.preload = 0; + cache->NARS.lock = 0; + break; + case req_store: + cache->NARS.preload = 1; + cache->NARS.lock = 0; + break; + case req_preload: + cache->NARS.preload = 1; + cache->NARS.lock = req->u.preload.lock; + break; + } + cache->NARS.valid = 1; + return; + } + /* All wait registers are busy, so resubmit this request. */ + pipeline_requeue_request (pipeline); +} + +/* Find a free WAR register and wait for memory to fetch the data. */ +static void +wait_in_WAR (FRV_CACHE* cache, int pipe, FRV_CACHE_REQUEST *req) +{ + int war; + FRV_CACHE_PIPELINE *pipeline = & cache->pipeline[pipe]; + + /* Find a valid WAR to hold this request. */ + for (war = 0; war < NUM_WARS; ++war) + if (! pipeline->WAR[war].valid) + break; + if (war >= NUM_WARS) + { + wait_for_WAR (cache, pipe, req); + return; + } + + pipeline->WAR[war].address = req->address; + pipeline->WAR[war].reqno = req->reqno; + pipeline->WAR[war].priority = req->priority - 1; + pipeline->WAR[war].latency = cache->memory_latency + 1; + switch (req->kind) + { + case req_load: + pipeline->WAR[war].preload = 0; + pipeline->WAR[war].lock = 0; + break; + case req_store: + pipeline->WAR[war].preload = 1; + pipeline->WAR[war].lock = 0; + break; + case req_preload: + pipeline->WAR[war].preload = 1; + pipeline->WAR[war].lock = req->u.preload.lock; + break; + } + pipeline->WAR[war].valid = 1; +} + +static void +handle_req_load (FRV_CACHE *cache, int pipe, FRV_CACHE_REQUEST *req) +{ + FRV_CACHE_TAG *tag; + SI address = req->address; + + /* If this address interferes with an existing request, then requeue it. */ + if (address_interference (cache, address, req, pipe)) + { + pipeline_requeue_request (& cache->pipeline[pipe]); + return; + } + + if (frv_cache_enabled (cache) && ! non_cache_access (cache, address)) + { + int found = get_tag (cache, address, &tag); + + /* If the data was found, return it to the caller. */ + if (found) + { + set_most_recently_used (cache, tag); + copy_line_to_return_buffer (cache, pipe, tag, address); + set_return_buffer_reqno (cache, pipe, req->reqno); + return; + } + } + + /* The data is not in the cache or this is a non-cache access. We need to + wait for the memory unit to fetch it. Store this request in the WAR in + the meantime. */ + wait_in_WAR (cache, pipe, req); +} + +static void +handle_req_preload (FRV_CACHE *cache, int pipe, FRV_CACHE_REQUEST *req) +{ + int found; + FRV_CACHE_WAR war; + FRV_CACHE_TAG *tag; + int length; + int lock; + int offset; + int lines; + int line; + SI address = req->address; + SI cur_address; + + if (! frv_cache_enabled (cache) || non_cache_access (cache, address)) + return; + + /* preload at least 1 line. */ + length = req->u.preload.length; + if (length == 0) + length = 1; + + /* Make sure that this request does not interfere with a pending request. */ + offset = address & (cache->line_size - 1); + lines = 1 + (offset + length - 1) / cache->line_size; + cur_address = address & ~(cache->line_size - 1); + for (line = 0; line < lines; ++line) + { + /* If this address interferes with an existing request, + then requeue it. */ + if (address_interference (cache, cur_address, req, pipe)) + { + pipeline_requeue_request (& cache->pipeline[pipe]); + return; + } + cur_address += cache->line_size; + } + + /* Now process each cache line. */ + /* Careful with this loop -- length is unsigned. */ + lock = req->u.preload.lock; + cur_address = address & ~(cache->line_size - 1); + for (line = 0; line < lines; ++line) + { + /* If the data was found, then lock it if requested. */ + found = get_tag (cache, cur_address, &tag); + if (found) + { + if (lock) + tag->locked = 1; + } + else + { + /* The data is not in the cache. We need to wait for the memory + unit to fetch it. Store this request in the WAR in the meantime. + */ + wait_in_WAR (cache, pipe, req); + } + cur_address += cache->line_size; + } +} + +static void +handle_req_store (FRV_CACHE *cache, int pipe, FRV_CACHE_REQUEST *req) +{ + SIM_CPU *current_cpu; + FRV_CACHE_TAG *tag; + int found; + int copy_back; + SI address = req->address; + char *data = req->u.store.data; + int length = req->u.store.length; + + /* If this address interferes with an existing request, then requeue it. */ + if (address_interference (cache, address, req, pipe)) + { + pipeline_requeue_request (& cache->pipeline[pipe]); + return; + } + + /* Non-cache access. Write the data directly to memory. */ + if (! frv_cache_enabled (cache) || non_cache_access (cache, address)) + { + write_data_to_memory (cache, address, data, length); + return; + } + + /* See if the data is in the cache. */ + found = get_tag (cache, address, &tag); + + /* Write the data to the cache line if one was available and if it is + either a hit or a miss in copy-back mode. + The tag may be NULL if all ways were in use and locked on a miss. + */ + current_cpu = cache->cpu; + copy_back = GET_HSR0_CBM (GET_HSR0 ()); + if (tag != NULL && (found || copy_back)) + { + int line_offset; + /* Load the line from memory first, if it was a miss. */ + if (! found) + { + /* We need to wait for the memory unit to fetch the data. + Store this request in the WAR and requeue the store request. */ + wait_in_WAR (cache, pipe, req); + pipeline_requeue_request (& cache->pipeline[pipe]); + /* Decrement the counts of accesses and hits because when the requeued + request is processed again, it will appear to be a new access and + a hit. */ + --cache->statistics.accesses; + --cache->statistics.hits; + return; + } + line_offset = address & (cache->line_size - 1); + memcpy (tag->line + line_offset, data, length); + invalidate_return_buffer (cache, address); + tag->dirty = 1; + + /* Update the LRU information for the tags in this set. */ + set_most_recently_used (cache, tag); + } + + /* Write the data to memory if there was no line available or we are in + write-through (not copy-back mode). */ + if (tag == NULL || ! copy_back) + { + write_data_to_memory (cache, address, data, length); + if (tag != NULL) + tag->dirty = 0; + } +} + +static void +handle_req_invalidate (FRV_CACHE *cache, int pipe, FRV_CACHE_REQUEST *req) +{ + FRV_CACHE_PIPELINE *pipeline = & cache->pipeline[pipe]; + SI address = req->address; + SI interfere_address = req->u.invalidate.all ? -1 : address; + + /* If this address interferes with an existing request, then requeue it. */ + if (address_interference (cache, interfere_address, req, pipe)) + { + pipeline_requeue_request (pipeline); + return; + } + + /* Invalidate the cache line now. This function already checks for + non-cache access. */ + if (req->u.invalidate.all) + frv_cache_invalidate_all (cache, req->u.invalidate.flush); + else + frv_cache_invalidate (cache, address, req->u.invalidate.flush); + if (req->u.invalidate.flush) + { + pipeline->status.flush.reqno = req->reqno; + pipeline->status.flush.address = address; + pipeline->status.flush.valid = 1; + } +} + +static void +handle_req_unlock (FRV_CACHE *cache, int pipe, FRV_CACHE_REQUEST *req) +{ + FRV_CACHE_PIPELINE *pipeline = & cache->pipeline[pipe]; + SI address = req->address; + + /* If this address interferes with an existing request, then requeue it. */ + if (address_interference (cache, address, req, pipe)) + { + pipeline_requeue_request (pipeline); + return; + } + + /* Unlock the cache line. This function checks for non-cache access. */ + frv_cache_unlock (cache, address); +} + +static void +handle_req_WAR (FRV_CACHE *cache, int pipe, FRV_CACHE_REQUEST *req) +{ + char *buffer; + FRV_CACHE_TAG *tag; + SI address = req->address; + + if (frv_cache_enabled (cache) && ! non_cache_access (cache, address)) + { + /* Look for the data in the cache. The statistics of cache hit or + miss have already been recorded, so save and restore the stats before + and after obtaining the cache line. */ + FRV_CACHE_STATISTICS save_stats = cache->statistics; + tag = find_or_retrieve_cache_line (cache, address); + cache->statistics = save_stats; + if (tag != NULL) + { + if (! req->u.WAR.preload) + { + copy_line_to_return_buffer (cache, pipe, tag, address); + set_return_buffer_reqno (cache, pipe, req->reqno); + } + else + { + invalidate_return_buffer (cache, address); + if (req->u.WAR.lock) + tag->locked = 1; + } + return; + } + } + + /* All cache lines in the set were locked, so just copy the data to the + return buffer directly. */ + if (! req->u.WAR.preload) + { + copy_memory_to_return_buffer (cache, pipe, address); + set_return_buffer_reqno (cache, pipe, req->reqno); + } +} + +/* Resolve any conflicts and/or execute the given requests. */ +static void +arbitrate_requests (FRV_CACHE *cache) +{ + int pipe; + /* Simply execute the requests in the final pipeline stages. */ + for (pipe = LS; pipe < FRV_CACHE_PIPELINES; ++pipe) + { + FRV_CACHE_REQUEST *req + = pipeline_stage_request (& cache->pipeline[pipe], LAST_STAGE); + /* Make sure that there is a request to handle. */ + if (req == NULL) + continue; + + /* Handle the request. */ + switch (req->kind) + { + case req_load: + handle_req_load (cache, pipe, req); + break; + case req_store: + handle_req_store (cache, pipe, req); + break; + case req_invalidate: + handle_req_invalidate (cache, pipe, req); + break; + case req_preload: + handle_req_preload (cache, pipe, req); + break; + case req_unlock: + handle_req_unlock (cache, pipe, req); + break; + case req_WAR: + handle_req_WAR (cache, pipe, req); + break; + default: + abort (); + } + } +} + +/* Move a waiting ARS register to a free WAR register. */ +static void +move_ARS_to_WAR (FRV_CACHE *cache, int pipe, FRV_CACHE_WAR *war) +{ + /* If BARS is valid for this pipe, then move it to the given WAR. Move + NARS to BARS if it is valid. */ + if (cache->BARS.valid && cache->BARS.pipe == pipe) + { + war->address = cache->BARS.address; + war->reqno = cache->BARS.reqno; + war->priority = cache->BARS.priority; + war->preload = cache->BARS.preload; + war->lock = cache->BARS.lock; + war->latency = cache->memory_latency + 1; + war->valid = 1; + if (cache->NARS.valid) + { + cache->BARS = cache->NARS; + cache->NARS.valid = 0; + } + else + cache->BARS.valid = 0; + return; + } + /* If NARS is valid for this pipe, then move it to the given WAR. */ + if (cache->NARS.valid && cache->NARS.pipe == pipe) + { + war->address = cache->NARS.address; + war->reqno = cache->NARS.reqno; + war->priority = cache->NARS.priority; + war->preload = cache->NARS.preload; + war->lock = cache->NARS.lock; + war->latency = cache->memory_latency + 1; + war->valid = 1; + cache->NARS.valid = 0; + } +} + +/* Decrease the latencies of the various states in the cache. */ +static void +decrease_latencies (FRV_CACHE *cache) +{ + int pipe, j; + /* Check the WAR registers. */ + for (pipe = LS; pipe < FRV_CACHE_PIPELINES; ++pipe) + { + FRV_CACHE_PIPELINE *pipeline = & cache->pipeline[pipe]; + for (j = 0; j < NUM_WARS; ++j) + { + FRV_CACHE_WAR *war = & pipeline->WAR[j]; + if (war->valid) + { + --war->latency; + /* If the latency has expired, then submit a WAR request to the + pipeline. */ + if (war->latency <= 0) + { + add_WAR_request (pipeline, war); + war->valid = 0; + move_ARS_to_WAR (cache, pipe, war); + } + } + } + } +} + +/* Run the cache for the given number of cycles. */ +void +frv_cache_run (FRV_CACHE *cache, int cycles) +{ + int i; + for (i = 0; i < cycles; ++i) + { + advance_pipelines (cache); + arbitrate_requests (cache); + decrease_latencies (cache); + } +} + +int +frv_cache_read_passive_SI (FRV_CACHE *cache, SI address, SI *value) +{ + SI offset; + FRV_CACHE_TAG *tag; + + if (non_cache_access (cache, address)) + return 0; + + { + FRV_CACHE_STATISTICS save_stats = cache->statistics; + int found = get_tag (cache, address, &tag); + cache->statistics = save_stats; + + if (! found) + return 0; /* Indicate non-cache-access. */ + } + + /* A cache line was available for the data. + Extract the target data from the line. */ + offset = address & (cache->line_size - 1); + *value = T2H_4 (*(SI *)(tag->line + offset)); + return 1; +} + +/* Check the return buffers of the data cache to see if the requested data is + available. */ +int +frv_cache_data_in_buffer (FRV_CACHE* cache, int pipe, SI address, + unsigned reqno) +{ + return cache->pipeline[pipe].status.return_buffer.valid + && cache->pipeline[pipe].status.return_buffer.reqno == reqno + && cache->pipeline[pipe].status.return_buffer.address <= address + && cache->pipeline[pipe].status.return_buffer.address + cache->line_size + > address; +} + +/* Check to see if the requested data has been flushed. */ +int +frv_cache_data_flushed (FRV_CACHE* cache, int pipe, SI address, unsigned reqno) +{ + return cache->pipeline[pipe].status.flush.valid + && cache->pipeline[pipe].status.flush.reqno == reqno + && cache->pipeline[pipe].status.flush.address <= address + && cache->pipeline[pipe].status.flush.address + cache->line_size + > address; +} diff --git a/sim/frv/cache.h b/sim/frv/cache.h new file mode 100644 index 0000000..2d17514 --- /dev/null +++ b/sim/frv/cache.h @@ -0,0 +1,267 @@ +/* Cache support for the FRV simulator + Copyright (C) 1999, 2000, 2003 Free Software Foundation, Inc. + Contributed by Red Hat. + +This file is part of the GNU Simulators. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef CACHE_H +#define CACHE_H + +/* A representation of a set-associative cache with LRU replacement, + cache line locking, non-blocking support and multiple read ports. */ + +/* An enumeration of cache pipeline request kinds. */ +typedef enum +{ + req_load, + req_store, + req_invalidate, + req_flush, + req_preload, + req_unlock, + req_WAR +} FRV_CACHE_REQUEST_KIND; + +/* The cache pipeline requests. */ +typedef struct { + int preload; + int lock; +} FRV_CACHE_WAR_REQUEST; + +typedef struct { + char *data; + int length; +} FRV_CACHE_STORE_REQUEST; + +typedef struct { + int flush; + int all; +} FRV_CACHE_INVALIDATE_REQUEST; + +typedef struct { + int lock; + int length; +} FRV_CACHE_PRELOAD_REQUEST; + +/* A cache pipeline request. */ +typedef struct frv_cache_request +{ + struct frv_cache_request *next; + struct frv_cache_request *prev; + FRV_CACHE_REQUEST_KIND kind; + unsigned reqno; + unsigned priority; + SI address; + union { + FRV_CACHE_STORE_REQUEST store; + FRV_CACHE_INVALIDATE_REQUEST invalidate; + FRV_CACHE_PRELOAD_REQUEST preload; + FRV_CACHE_WAR_REQUEST WAR; + } u; +} FRV_CACHE_REQUEST; + +/* The buffer for returning data to the caller. */ +typedef struct { + unsigned reqno; + SI address; + char *data; + int valid; +} FRV_CACHE_RETURN_BUFFER; + +/* The status of flush requests. */ +typedef struct { + unsigned reqno; + SI address; + int valid; +} FRV_CACHE_FLUSH_STATUS; + +/* Communicate status of requests to the caller. */ +typedef struct { + FRV_CACHE_FLUSH_STATUS flush; + FRV_CACHE_RETURN_BUFFER return_buffer; +} FRV_CACHE_STATUS; + +/* A cache pipeline stage. */ +typedef struct { + FRV_CACHE_REQUEST *request; +} FRV_CACHE_STAGE; + +enum { + FIRST_STAGE, + A_STAGE = FIRST_STAGE, /* Addressing stage */ + I_STAGE, /* Interference stage */ + LAST_STAGE = I_STAGE, + FRV_CACHE_STAGES +}; + +/* Representation of the WAR register. */ +typedef struct { + unsigned reqno; + unsigned priority; + SI address; + int preload; + int lock; + int latency; + int valid; +} FRV_CACHE_WAR; + +/* A cache pipeline. */ +#define NUM_WARS 2 +typedef struct { + FRV_CACHE_REQUEST *requests; + FRV_CACHE_STAGE stages[FRV_CACHE_STAGES]; + FRV_CACHE_WAR WAR[NUM_WARS]; + FRV_CACHE_STATUS status; +} FRV_CACHE_PIPELINE; + +enum {LS, LD, FRV_CACHE_PIPELINES}; + +/* Representation of the xARS registers. */ +typedef struct { + int pipe; + unsigned reqno; + unsigned priority; + SI address; + int preload; + int lock; + int valid; +} FRV_CACHE_ARS; + +/* A cache tag. */ +typedef struct { + USI tag; /* Address tag. */ + int lru; /* Lower values indicates less recently used. */ + char *line; /* Points to storage for line in data_storage. */ + char dirty; /* line has been written to since last stored? */ + char locked; /* line is locked? */ + char valid; /* tag is valid? */ +} FRV_CACHE_TAG; + +/* Cache statistics. */ +typedef struct { + unsigned long accesses; /* number of cache accesses. */ + unsigned long hits; /* number of cache hits. */ +} FRV_CACHE_STATISTICS; + +/* The cache itself. + Notes: + - line_size must be a power of 2 + - sets must be a power of 2 + - ways must be a power of 2 +*/ +typedef struct { + SIM_CPU *cpu; + unsigned configured_ways; /* Number of ways configured in each set. */ + unsigned configured_sets; /* Number of sets configured in the cache. */ + unsigned ways; /* Number of ways in each set. */ + unsigned sets; /* Number of sets in the cache. */ + unsigned line_size; /* Size of each cache line. */ + unsigned memory_latency; /* Latency of main memory in cycles. */ + FRV_CACHE_TAG *tag_storage; /* Storage for tags. */ + char *data_storage; /* Storage for data (cache lines). */ + FRV_CACHE_PIPELINE pipeline[2]; /* Cache pipelines. */ + FRV_CACHE_ARS BARS; /* BARS register. */ + FRV_CACHE_ARS NARS; /* BARS register. */ + FRV_CACHE_STATISTICS statistics; /* Operation statistics. */ +} FRV_CACHE; + +/* The tags are stored by ways within sets in order to make computations + easier. */ +#define CACHE_TAG(cache, set, way) ( \ + & ((cache)->tag_storage[(set) * (cache)->ways + (way)]) \ +) + +/* Compute the address tag corresponding to the given address. */ +#define CACHE_ADDRESS_TAG(cache, address) ( \ + (address) & ~(((cache)->line_size * (cache)->sets) - 1) \ +) + +/* Determine the index at which the set containing this tag starts. */ +#define CACHE_TAG_SET_START(cache, tag) ( \ + ((tag) - (cache)->tag_storage) & ~((cache)->ways - 1) \ +) + +/* Determine the number of the set which this cache tag is in. */ +#define CACHE_TAG_SET_NUMBER(cache, tag) ( \ + CACHE_TAG_SET_START ((cache), (tag)) / (cache)->ways \ +) + +#define CACHE_RETURN_DATA(cache, slot, address, mode, N) ( \ + T2H_##N (*(mode *)(& (cache)->pipeline[slot].status.return_buffer.data \ + [((address) & ((cache)->line_size - 1))])) \ +) +#define CACHE_RETURN_DATA_ADDRESS(cache, slot, address, N) ( \ + ((void *)& (cache)->pipeline[slot].status.return_buffer.data[(address) \ + & ((cache)->line_size - 1)]) \ +) + +#define DATA_CROSSES_CACHE_LINE(cache, address, size) ( \ + ((address) & ((cache)->line_size - 1)) + (size) > (cache)->line_size \ +) + +#define CACHE_INITIALIZED(cache) ((cache)->data_storage != NULL) + +/* These functions are used to initialize and terminate a cache. */ +void +frv_cache_init (SIM_CPU *, FRV_CACHE *); +void +frv_cache_term (FRV_CACHE *); +void +frv_cache_reconfigure (SIM_CPU *, FRV_CACHE *); +int +frv_cache_enabled (FRV_CACHE *); + +/* These functions are used to operate the cache in non-cycle-accurate mode. + Each request is handled individually and immediately using the current + cache internal state. */ +int +frv_cache_read (FRV_CACHE *, int, SI); +int +frv_cache_write (FRV_CACHE *, SI, char *, unsigned); +int +frv_cache_preload (FRV_CACHE *, SI, USI, int); +int +frv_cache_invalidate (FRV_CACHE *, SI, int); +int +frv_cache_invalidate_all (FRV_CACHE *, int); + +/* These functions are used to operate the cache in cycle-accurate mode. + The internal operation of the cache is simulated down to the cycle level. */ +#define NO_REQNO 0xffffffff +void +frv_cache_request_load (FRV_CACHE *, unsigned, SI, int); +void +frv_cache_request_store (FRV_CACHE *, SI, int, char *, unsigned); +void +frv_cache_request_invalidate (FRV_CACHE *, unsigned, SI, int, int, int); +void +frv_cache_request_preload (FRV_CACHE *, SI, int, int, int); +void +frv_cache_request_unlock (FRV_CACHE *, SI, int); + +void +frv_cache_run (FRV_CACHE *, int); + +int +frv_cache_data_in_buffer (FRV_CACHE*, int, SI, unsigned); +int +frv_cache_data_flushed (FRV_CACHE*, int, SI, unsigned); + +int +frv_cache_read_passive_SI (FRV_CACHE *, SI, SI *); + +#endif /* CACHE_H */ diff --git a/sim/frv/config.in b/sim/frv/config.in new file mode 100644 index 0000000..9723b86 --- /dev/null +++ b/sim/frv/config.in @@ -0,0 +1,162 @@ +/* config.in. Generated automatically from configure.in by autoheader. */ + +/* Define if using alloca.c. */ +#undef C_ALLOCA + +/* Define to empty if the keyword does not work. */ +#undef const + +/* Define to one of _getb67, GETB67, getb67 for Cray-2 and Cray-YMP systems. + This function is required for alloca.c support on those systems. */ +#undef CRAY_STACKSEG_END + +/* Define if you have alloca, as a function or macro. */ +#undef HAVE_ALLOCA + +/* Define if you have and it should be used (not on Ultrix). */ +#undef HAVE_ALLOCA_H + +/* Define if you have a working `mmap' system call. */ +#undef HAVE_MMAP + +/* Define as __inline if that's what the C compiler calls it. */ +#undef inline + +/* Define to `long' if doesn't define. */ +#undef off_t + +/* Define if you need to in order for stat and other things to work. */ +#undef _POSIX_SOURCE + +/* Define as the return type of signal handlers (int or void). */ +#undef RETSIGTYPE + +/* Define to `unsigned' if doesn't define. */ +#undef size_t + +/* If using the C implementation of alloca, define if you know the + direction of stack growth for your system; otherwise it will be + automatically deduced at run-time. + STACK_DIRECTION > 0 => grows toward higher addresses + STACK_DIRECTION < 0 => grows toward lower addresses + STACK_DIRECTION = 0 => direction of growth unknown + */ +#undef STACK_DIRECTION + +/* Define if you have the ANSI C header files. */ +#undef STDC_HEADERS + +/* Define if your processor stores words with the most significant + byte first (like Motorola and SPARC, unlike Intel and VAX). */ +#undef WORDS_BIGENDIAN + +/* Define to 1 if NLS is requested. */ +#undef ENABLE_NLS + +/* Define as 1 if you have gettext and don't want to use GNU gettext. */ +#undef HAVE_GETTEXT + +/* Define as 1 if you have the stpcpy function. */ +#undef HAVE_STPCPY + +/* Define if your locale.h file contains LC_MESSAGES. */ +#undef HAVE_LC_MESSAGES + +/* Define if you have the __argz_count function. */ +#undef HAVE___ARGZ_COUNT + +/* Define if you have the __argz_next function. */ +#undef HAVE___ARGZ_NEXT + +/* Define if you have the __argz_stringify function. */ +#undef HAVE___ARGZ_STRINGIFY + +/* Define if you have the __setfpucw function. */ +#undef HAVE___SETFPUCW + +/* Define if you have the dcgettext function. */ +#undef HAVE_DCGETTEXT + +/* Define if you have the getcwd function. */ +#undef HAVE_GETCWD + +/* Define if you have the getpagesize function. */ +#undef HAVE_GETPAGESIZE + +/* Define if you have the getrusage function. */ +#undef HAVE_GETRUSAGE + +/* Define if you have the munmap function. */ +#undef HAVE_MUNMAP + +/* Define if you have the putenv function. */ +#undef HAVE_PUTENV + +/* Define if you have the setenv function. */ +#undef HAVE_SETENV + +/* Define if you have the setlocale function. */ +#undef HAVE_SETLOCALE + +/* Define if you have the sigaction function. */ +#undef HAVE_SIGACTION + +/* Define if you have the stpcpy function. */ +#undef HAVE_STPCPY + +/* Define if you have the strcasecmp function. */ +#undef HAVE_STRCASECMP + +/* Define if you have the strchr function. */ +#undef HAVE_STRCHR + +/* Define if you have the time function. */ +#undef HAVE_TIME + +/* Define if you have the header file. */ +#undef HAVE_ARGZ_H + +/* Define if you have the header file. */ +#undef HAVE_FCNTL_H + +/* Define if you have the header file. */ +#undef HAVE_FPU_CONTROL_H + +/* Define if you have the header file. */ +#undef HAVE_LIMITS_H + +/* Define if you have the header file. */ +#undef HAVE_LOCALE_H + +/* Define if you have the header file. */ +#undef HAVE_MALLOC_H + +/* Define if you have the header file. */ +#undef HAVE_NL_TYPES_H + +/* Define if you have the header file. */ +#undef HAVE_STDLIB_H + +/* Define if you have the header file. */ +#undef HAVE_STRING_H + +/* Define if you have the header file. */ +#undef HAVE_STRINGS_H + +/* Define if you have the header file. */ +#undef HAVE_SYS_PARAM_H + +/* Define if you have the header file. */ +#undef HAVE_SYS_RESOURCE_H + +/* Define if you have the header file. */ +#undef HAVE_SYS_TIME_H + +/* Define if you have the header file. */ +#undef HAVE_TIME_H + +/* Define if you have the header file. */ +#undef HAVE_UNISTD_H + +/* Define if you have the header file. */ +#undef HAVE_VALUES_H diff --git a/sim/frv/configure b/sim/frv/configure new file mode 100755 index 0000000..38b2b7d --- /dev/null +++ b/sim/frv/configure @@ -0,0 +1,4315 @@ +#! /bin/sh + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +sim_inline="-DDEFAULT_INLINE=0" + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +# This file is derived from `gettext.m4'. The difference is that the +# included macros assume Cygnus-style source and build trees. + +# Macro to add for using GNU gettext. +# Ulrich Drepper , 1995. +# +# This file file be copied and used freely without restrictions. It can +# be used in projects which are not available under the GNU Public License +# but which still want to provide support for the GNU gettext functionality. +# Please note that the actual code is *not* freely available. + +# serial 3 + + + + + +# Search path for a program which passes the given test. +# Ulrich Drepper , 1996. +# +# This file file be copied and used freely without restrictions. It can +# be used in projects which are not available under the GNU Public License +# but which still want to provide support for the GNU gettext functionality. +# Please note that the actual code is *not* freely available. + +# serial 1 + + + +# Check whether LC_MESSAGES is available in . +# Ulrich Drepper , 1995. +# +# This file file be copied and used freely without restrictions. It can +# be used in projects which are not available under the GNU Public License +# but which still want to provide support for the GNU gettext functionality. +# Please note that the actual code is *not* freely available. + +# serial 1 + + + + + + +# Guess values for system-dependent variables and create Makefiles. +# Generated automatically using autoconf version 2.13 +# Copyright (C) 1992, 93, 94, 95, 96 Free Software Foundation, Inc. +# +# This configure script is free software; the Free Software Foundation +# gives unlimited permission to copy, distribute and modify it. + +# Defaults: +ac_help= +ac_default_prefix=/usr/local +# Any additions from configure.in: +ac_help="$ac_help + --disable-nls do not use Native Language Support" +ac_help="$ac_help + --with-included-gettext use the GNU gettext library included here" +ac_help="$ac_help + --enable-maintainer-mode Enable developer functionality." +ac_help="$ac_help + --enable-sim-bswap Use Host specific BSWAP instruction." +ac_help="$ac_help + --enable-sim-cflags=opts Extra CFLAGS for use in building simulator" +ac_help="$ac_help + --enable-sim-debug=opts Enable debugging flags" +ac_help="$ac_help + --enable-sim-stdio Specify whether to use stdio for console input/output." +ac_help="$ac_help + --enable-sim-trace=opts Enable tracing flags" +ac_help="$ac_help + --enable-sim-profile=opts Enable profiling flags" +ac_help="$ac_help + --enable-sim-endian=endian Specify target byte endian orientation." +ac_help="$ac_help + --enable-sim-alignment=align Specify strict, nonstrict or forced alignment of memory accesses." +ac_help="$ac_help + --enable-sim-hostendian=end Specify host byte endian orientation." +ac_help="$ac_help + --enable-sim-scache=size Specify simulator execution cache size." +ac_help="$ac_help + --enable-sim-default-model=model Specify default model to simulate." +ac_help="$ac_help + --enable-sim-environment=environment Specify mixed, user, virtual or operating environment." +ac_help="$ac_help + --enable-cgen-maint[=DIR] build cgen generated files" +ac_help="$ac_help + --enable-sim-trapdump Make unknown traps dump the registers" + +# Initialize some variables set by options. +# The variables have the same names as the options, with +# dashes changed to underlines. +build=NONE +cache_file=./config.cache +exec_prefix=NONE +host=NONE +no_create= +nonopt=NONE +no_recursion= +prefix=NONE +program_prefix=NONE +program_suffix=NONE +program_transform_name=s,x,x, +silent= +site= +sitefile= +srcdir= +target=NONE +verbose= +x_includes=NONE +x_libraries=NONE +bindir='${exec_prefix}/bin' +sbindir='${exec_prefix}/sbin' +libexecdir='${exec_prefix}/libexec' +datadir='${prefix}/share' +sysconfdir='${prefix}/etc' +sharedstatedir='${prefix}/com' +localstatedir='${prefix}/var' +libdir='${exec_prefix}/lib' +includedir='${prefix}/include' +oldincludedir='/usr/include' +infodir='${prefix}/info' +mandir='${prefix}/man' + +# Initialize some other variables. +subdirs= +MFLAGS= MAKEFLAGS= +SHELL=${CONFIG_SHELL-/bin/sh} +# Maximum number of lines to put in a shell here document. +ac_max_here_lines=12 + +ac_prev= +for ac_option +do + + # If the previous option needs an argument, assign it. + if test -n "$ac_prev"; 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+ + -program-transform-name | --program-transform-name \ + | --program-transform-nam | --program-transform-na \ + | --program-transform-n | --program-transform- \ + | --program-transform | --program-transfor \ + | --program-transfo | --program-transf \ + | --program-trans | --program-tran \ + | --progr-tra | --program-tr | --program-t) + ac_prev=program_transform_name ;; + -program-transform-name=* | --program-transform-name=* \ + | --program-transform-nam=* | --program-transform-na=* \ + | --program-transform-n=* | --program-transform-=* \ + | --program-transform=* | --program-transfor=* \ + | --program-transfo=* | --program-transf=* \ + | --program-trans=* | --program-tran=* \ + | --progr-tra=* | --program-tr=* | --program-t=*) + program_transform_name="$ac_optarg" ;; + + -q | -quiet | --quiet | --quie | --qui | --qu | --q \ + | -silent | --silent | --silen | --sile | --sil) + silent=yes ;; + + -sbindir | --sbindir | --sbindi | --sbind | --sbin | --sbi | --sb) + ac_prev=sbindir ;; + -sbindir=* | --sbindir=* | --sbindi=* | --sbind=* | --sbin=* \ + | --sbi=* | --sb=*) + sbindir="$ac_optarg" ;; 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+ -sysconfdir=* | --sysconfdir=* | --sysconfdi=* | --sysconfd=* | --sysconf=* \ + | --syscon=* | --sysco=* | --sysc=* | --sys=* | --sy=*) + sysconfdir="$ac_optarg" ;; + + -target | --target | --targe | --targ | --tar | --ta | --t) + ac_prev=target ;; + -target=* | --target=* | --targe=* | --targ=* | --tar=* | --ta=* | --t=*) + target="$ac_optarg" ;; + + -v | -verbose | --verbose | --verbos | --verbo | --verb) + verbose=yes ;; + + -version | --version | --versio | --versi | --vers) + echo "configure generated by autoconf version 2.13" + exit 0 ;; + + -with-* | --with-*) + ac_package=`echo $ac_option|sed -e 's/-*with-//' -e 's/=.*//'` + # Reject names that are not valid shell variable names. + if test -n "`echo $ac_package| sed 's/[-_a-zA-Z0-9]//g'`"; then + { echo "configure: error: $ac_package: invalid package name" 1>&2; exit 1; } + fi + ac_package=`echo $ac_package| sed 's/-/_/g'` + case "$ac_option" in + *=*) ;; + *) ac_optarg=yes ;; + esac + eval "with_${ac_package}='$ac_optarg'" ;; + + -without-* | --without-*) + ac_package=`echo $ac_option|sed -e 's/-*without-//'` + # Reject names that are not valid shell variable names. + if test -n "`echo $ac_package| sed 's/[-a-zA-Z0-9_]//g'`"; then + { echo "configure: error: $ac_package: invalid package name" 1>&2; exit 1; } + fi + ac_package=`echo $ac_package| sed 's/-/_/g'` + eval "with_${ac_package}=no" ;; + + --x) + # Obsolete; use --with-x. + with_x=yes ;; + + -x-includes | --x-includes | --x-include | --x-includ | --x-inclu \ + | --x-incl | --x-inc | --x-in | --x-i) + ac_prev=x_includes ;; + -x-includes=* | --x-includes=* | --x-include=* | --x-includ=* | --x-inclu=* \ + | --x-incl=* | --x-inc=* | --x-in=* | --x-i=*) + x_includes="$ac_optarg" ;; + + -x-libraries | --x-libraries | --x-librarie | --x-librari \ + | --x-librar | --x-libra | --x-libr | --x-lib | --x-li | --x-l) + ac_prev=x_libraries ;; + -x-libraries=* | --x-libraries=* | --x-librarie=* | --x-librari=* \ + | --x-librar=* | --x-libra=* | --x-libr=* | --x-lib=* | --x-li=* | --x-l=*) + x_libraries="$ac_optarg" ;; + + -*) { echo "configure: error: $ac_option: invalid option; use --help to show usage" 1>&2; exit 1; } + ;; + + *) + if test -n "`echo $ac_option| sed 's/[-a-z0-9.]//g'`"; then + echo "configure: warning: $ac_option: invalid host type" 1>&2 + fi + if test "x$nonopt" != xNONE; then + { echo "configure: error: can only configure for one host and one target at a time" 1>&2; exit 1; } + fi + nonopt="$ac_option" + ;; + + esac +done + +if test -n "$ac_prev"; then + { echo "configure: error: missing argument to --`echo $ac_prev | sed 's/_/-/g'`" 1>&2; exit 1; } +fi + +trap 'rm -fr conftest* confdefs* core core.* *.core $ac_clean_files; exit 1' 1 2 15 + +# File descriptor usage: +# 0 standard input +# 1 file creation +# 2 errors and warnings +# 3 some systems may open it to /dev/tty +# 4 used on the Kubota Titan +# 6 checking for... messages and results +# 5 compiler messages saved in config.log +if test "$silent" = yes; then + exec 6>/dev/null +else + exec 6>&1 +fi +exec 5>./config.log + +echo "\ +This file contains any messages produced by compilers while +running configure, to aid debugging if configure makes a mistake. +" 1>&5 + +# Strip out --no-create and --no-recursion so they do not pile up. +# Also quote any args containing shell metacharacters. +ac_configure_args= +for ac_arg +do + case "$ac_arg" in + -no-create | --no-create | --no-creat | --no-crea | --no-cre \ + | --no-cr | --no-c) ;; + -no-recursion | --no-recursion | --no-recursio | --no-recursi \ + | --no-recurs | --no-recur | --no-recu | --no-rec | --no-re | --no-r) ;; + *" "*|*" "*|*[\[\]\~\#\$\^\&\*\(\)\{\}\\\|\;\<\>\?]*) + ac_configure_args="$ac_configure_args '$ac_arg'" ;; + *) ac_configure_args="$ac_configure_args $ac_arg" ;; + esac +done + +# NLS nuisances. +# Only set these to C if already set. These must not be set unconditionally +# because not all systems understand e.g. LANG=C (notably SCO). +# Fixing LC_MESSAGES prevents Solaris sh from translating var values in `set'! +# Non-C LC_CTYPE values break the ctype check. +if test "${LANG+set}" = set; then LANG=C; export LANG; fi +if test "${LC_ALL+set}" = set; then LC_ALL=C; export LC_ALL; fi +if test "${LC_MESSAGES+set}" = set; then LC_MESSAGES=C; export LC_MESSAGES; fi +if test "${LC_CTYPE+set}" = set; then LC_CTYPE=C; export LC_CTYPE; fi + +# confdefs.h avoids OS command line length limits that DEFS can exceed. +rm -rf conftest* confdefs.h +# AIX cpp loses on an empty file, so make sure it contains at least a newline. +echo > confdefs.h + +# A filename unique to this package, relative to the directory that +# configure is in, which we can look for to find out if srcdir is correct. +ac_unique_file=Makefile.in + +# Find the source files, if location was not specified. +if test -z "$srcdir"; then + ac_srcdir_defaulted=yes + # Try the directory containing this script, then its parent. + ac_prog=$0 + ac_confdir=`echo $ac_prog|sed 's%/[^/][^/]*$%%'` + test "x$ac_confdir" = "x$ac_prog" && ac_confdir=. + srcdir=$ac_confdir + if test ! -r $srcdir/$ac_unique_file; then + srcdir=.. + fi +else + ac_srcdir_defaulted=no +fi +if test ! -r $srcdir/$ac_unique_file; then + if test "$ac_srcdir_defaulted" = yes; then + { echo "configure: error: can not find sources in $ac_confdir or .." 1>&2; exit 1; } + else + { echo "configure: error: can not find sources in $srcdir" 1>&2; exit 1; } + fi +fi +srcdir=`echo "${srcdir}" | sed 's%\([^/]\)/*$%\1%'` + +# Prefer explicitly selected file to automatically selected ones. +if test -z "$sitefile"; then + if test -z "$CONFIG_SITE"; then + if test "x$prefix" != xNONE; then + CONFIG_SITE="$prefix/share/config.site $prefix/etc/config.site" + else + CONFIG_SITE="$ac_default_prefix/share/config.site $ac_default_prefix/etc/config.site" + fi + fi +else + CONFIG_SITE="$sitefile" +fi +for ac_site_file in $CONFIG_SITE; do + if test -r "$ac_site_file"; then + echo "loading site script $ac_site_file" + . "$ac_site_file" + fi +done + +if test -r "$cache_file"; then + echo "loading cache $cache_file" + . $cache_file +else + echo "creating cache $cache_file" + > $cache_file +fi + +ac_ext=c +# CFLAGS is not in ac_cpp because -g, -O, etc. are not valid cpp options. +ac_cpp='$CPP $CPPFLAGS' +ac_compile='${CC-cc} -c $CFLAGS $CPPFLAGS conftest.$ac_ext 1>&5' +ac_link='${CC-cc} -o conftest${ac_exeext} $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS 1>&5' +cross_compiling=$ac_cv_prog_cc_cross + +ac_exeext= +ac_objext=o +if (echo "testing\c"; echo 1,2,3) | grep c >/dev/null; then + # Stardent Vistra SVR4 grep lacks -e, says ghazi@caip.rutgers.edu. + if (echo -n testing; echo 1,2,3) | sed s/-n/xn/ | grep xn >/dev/null; then + ac_n= ac_c=' +' ac_t=' ' + else + ac_n=-n ac_c= ac_t= + fi +else + ac_n= ac_c='\c' ac_t= +fi + + + +echo $ac_n "checking how to run the C preprocessor""... $ac_c" 1>&6 +echo "configure:695: checking how to run the C preprocessor" >&5 +# On Suns, sometimes $CPP names a directory. +if test -n "$CPP" && test -d "$CPP"; then + CPP= +fi +if test -z "$CPP"; then +if eval "test \"`echo '$''{'ac_cv_prog_CPP'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + # This must be in double quotes, not single quotes, because CPP may get + # substituted into the Makefile and "${CC-cc}" will confuse make. + CPP="${CC-cc} -E" + # On the NeXT, cc -E runs the code through the compiler's parser, + # not just through cpp. + cat > conftest.$ac_ext < +Syntax Error +EOF +ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" +{ (eval echo configure:716: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` +if test -z "$ac_err"; then + : +else + echo "$ac_err" >&5 + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + CPP="${CC-cc} -E -traditional-cpp" + cat > conftest.$ac_ext < +Syntax Error +EOF +ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" +{ (eval echo configure:733: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` +if test -z "$ac_err"; then + : +else + echo "$ac_err" >&5 + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + CPP="${CC-cc} -nologo -E" + cat > conftest.$ac_ext < +Syntax Error +EOF +ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" +{ (eval echo configure:750: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` +if test -z "$ac_err"; then + : +else + echo "$ac_err" >&5 + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + CPP=/lib/cpp +fi +rm -f conftest* +fi +rm -f conftest* +fi +rm -f conftest* + ac_cv_prog_CPP="$CPP" +fi + CPP="$ac_cv_prog_CPP" +else + ac_cv_prog_CPP="$CPP" +fi +echo "$ac_t""$CPP" 1>&6 + +echo $ac_n "checking whether ${MAKE-make} sets \${MAKE}""... $ac_c" 1>&6 +echo "configure:775: checking whether ${MAKE-make} sets \${MAKE}" >&5 +set dummy ${MAKE-make}; ac_make=`echo "$2" | sed 'y%./+-%__p_%'` +if eval "test \"`echo '$''{'ac_cv_prog_make_${ac_make}_set'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftestmake <<\EOF +all: + @echo 'ac_maketemp="${MAKE}"' +EOF +# GNU make sometimes prints "make[1]: Entering...", which would confuse us. +eval `${MAKE-make} -f conftestmake 2>/dev/null | grep temp=` +if test -n "$ac_maketemp"; then + eval ac_cv_prog_make_${ac_make}_set=yes +else + eval ac_cv_prog_make_${ac_make}_set=no +fi +rm -f conftestmake +fi +if eval "test \"`echo '$ac_cv_prog_make_'${ac_make}_set`\" = yes"; then + echo "$ac_t""yes" 1>&6 + SET_MAKE= +else + echo "$ac_t""no" 1>&6 + SET_MAKE="MAKE=${MAKE-make}" +fi + +echo $ac_n "checking for POSIXized ISC""... $ac_c" 1>&6 +echo "configure:802: checking for POSIXized ISC" >&5 +if test -d /etc/conf/kconfig.d && + grep _POSIX_VERSION /usr/include/sys/unistd.h >/dev/null 2>&1 +then + echo "$ac_t""yes" 1>&6 + ISC=yes # If later tests want to check for ISC. + cat >> confdefs.h <<\EOF +#define _POSIX_SOURCE 1 +EOF + + if test "$GCC" = yes; then + CC="$CC -posix" + else + CC="$CC -Xp" + fi +else + echo "$ac_t""no" 1>&6 + ISC= +fi + +echo $ac_n "checking for ANSI C header files""... $ac_c" 1>&6 +echo "configure:823: checking for ANSI C header files" >&5 +if eval "test \"`echo '$''{'ac_cv_header_stdc'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext < +#include +#include +#include +EOF +ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" +{ (eval echo configure:836: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` +if test -z "$ac_err"; then + rm -rf conftest* + ac_cv_header_stdc=yes +else + echo "$ac_err" >&5 + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + ac_cv_header_stdc=no +fi +rm -f conftest* + +if test $ac_cv_header_stdc = yes; then + # SunOS 4.x string.h does not declare mem*, contrary to ANSI. +cat > conftest.$ac_ext < +EOF +if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | + egrep "memchr" >/dev/null 2>&1; then + : +else + rm -rf conftest* + ac_cv_header_stdc=no +fi +rm -f conftest* + +fi + +if test $ac_cv_header_stdc = yes; then + # ISC 2.0.2 stdlib.h does not declare free, contrary to ANSI. +cat > conftest.$ac_ext < +EOF +if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | + egrep "free" >/dev/null 2>&1; then + : +else + rm -rf conftest* + ac_cv_header_stdc=no +fi +rm -f conftest* + +fi + +if test $ac_cv_header_stdc = yes; then + # /bin/cc in Irix-4.0.5 gets non-ANSI ctype macros unless using -ansi. +if test "$cross_compiling" = yes; then + : +else + cat > conftest.$ac_ext < +#define ISLOWER(c) ('a' <= (c) && (c) <= 'z') +#define TOUPPER(c) (ISLOWER(c) ? 'A' + ((c) - 'a') : (c)) +#define XOR(e, f) (((e) && !(f)) || (!(e) && (f))) +int main () { int i; for (i = 0; i < 256; i++) +if (XOR (islower (i), ISLOWER (i)) || toupper (i) != TOUPPER (i)) exit(2); +exit (0); } + +EOF +if { (eval echo configure:903: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null +then + : +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -fr conftest* + ac_cv_header_stdc=no +fi +rm -fr conftest* +fi + +fi +fi + +echo "$ac_t""$ac_cv_header_stdc" 1>&6 +if test $ac_cv_header_stdc = yes; then + cat >> confdefs.h <<\EOF +#define STDC_HEADERS 1 +EOF + +fi + +echo $ac_n "checking for working const""... $ac_c" 1>&6 +echo "configure:927: checking for working const" >&5 +if eval "test \"`echo '$''{'ac_cv_c_const'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext <j = 5; +} +{ /* ULTRIX-32 V3.1 (Rev 9) vcc rejects this */ + const int foo = 10; +} + +; return 0; } +EOF +if { (eval echo configure:981: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then + rm -rf conftest* + ac_cv_c_const=yes +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + ac_cv_c_const=no +fi +rm -f conftest* +fi + +echo "$ac_t""$ac_cv_c_const" 1>&6 +if test $ac_cv_c_const = no; then + cat >> confdefs.h <<\EOF +#define const +EOF + +fi + +echo $ac_n "checking for inline""... $ac_c" 1>&6 +echo "configure:1002: checking for inline" >&5 +if eval "test \"`echo '$''{'ac_cv_c_inline'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + ac_cv_c_inline=no +for ac_kw in inline __inline__ __inline; do + cat > conftest.$ac_ext <&5; (eval $ac_compile) 2>&5; }; then + rm -rf conftest* + ac_cv_c_inline=$ac_kw; break +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 +fi +rm -f conftest* +done + +fi + +echo "$ac_t""$ac_cv_c_inline" 1>&6 +case "$ac_cv_c_inline" in + inline | yes) ;; + no) cat >> confdefs.h <<\EOF +#define inline +EOF + ;; + *) cat >> confdefs.h <&6 +echo "configure:1042: checking for off_t" >&5 +if eval "test \"`echo '$''{'ac_cv_type_off_t'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext < +#if STDC_HEADERS +#include +#include +#endif +EOF +if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | + egrep "(^|[^a-zA-Z_0-9])off_t[^a-zA-Z_0-9]" >/dev/null 2>&1; then + rm -rf conftest* + ac_cv_type_off_t=yes +else + rm -rf conftest* + ac_cv_type_off_t=no +fi +rm -f conftest* + +fi +echo "$ac_t""$ac_cv_type_off_t" 1>&6 +if test $ac_cv_type_off_t = no; then + cat >> confdefs.h <<\EOF +#define off_t long +EOF + +fi + +echo $ac_n "checking for size_t""... $ac_c" 1>&6 +echo "configure:1075: checking for size_t" >&5 +if eval "test \"`echo '$''{'ac_cv_type_size_t'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext < +#if STDC_HEADERS +#include +#include +#endif +EOF +if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | + egrep "(^|[^a-zA-Z_0-9])size_t[^a-zA-Z_0-9]" >/dev/null 2>&1; then + rm -rf conftest* + ac_cv_type_size_t=yes +else + rm -rf conftest* + ac_cv_type_size_t=no +fi +rm -f conftest* + +fi +echo "$ac_t""$ac_cv_type_size_t" 1>&6 +if test $ac_cv_type_size_t = no; then + cat >> confdefs.h <<\EOF +#define size_t unsigned +EOF + +fi + +# The Ultrix 4.2 mips builtin alloca declared by alloca.h only works +# for constant arguments. Useless! +echo $ac_n "checking for working alloca.h""... $ac_c" 1>&6 +echo "configure:1110: checking for working alloca.h" >&5 +if eval "test \"`echo '$''{'ac_cv_header_alloca_h'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext < +int main() { +char *p = alloca(2 * sizeof(int)); +; return 0; } +EOF +if { (eval echo configure:1122: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then + rm -rf conftest* + ac_cv_header_alloca_h=yes +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + ac_cv_header_alloca_h=no +fi +rm -f conftest* +fi + +echo "$ac_t""$ac_cv_header_alloca_h" 1>&6 +if test $ac_cv_header_alloca_h = yes; then + cat >> confdefs.h <<\EOF +#define HAVE_ALLOCA_H 1 +EOF + +fi + +echo $ac_n "checking for alloca""... $ac_c" 1>&6 +echo "configure:1143: checking for alloca" >&5 +if eval "test \"`echo '$''{'ac_cv_func_alloca_works'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext < +# define alloca _alloca +# else +# if HAVE_ALLOCA_H +# include +# else +# ifdef _AIX + #pragma alloca +# else +# ifndef alloca /* predefined by HP cc +Olibcalls */ +char *alloca (); +# endif +# endif +# endif +# endif +#endif + +int main() { +char *p = (char *) alloca(1); +; return 0; } +EOF +if { (eval echo configure:1176: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then + rm -rf conftest* + ac_cv_func_alloca_works=yes +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + ac_cv_func_alloca_works=no +fi +rm -f conftest* +fi + +echo "$ac_t""$ac_cv_func_alloca_works" 1>&6 +if test $ac_cv_func_alloca_works = yes; then + cat >> confdefs.h <<\EOF +#define HAVE_ALLOCA 1 +EOF + +fi + +if test $ac_cv_func_alloca_works = no; then + # The SVR3 libPW and SVR4 libucb both contain incompatible functions + # that cause trouble. Some versions do not even contain alloca or + # contain a buggy version. If you still want to use their alloca, + # use ar to extract alloca.o from them instead of compiling alloca.c. + ALLOCA=alloca.${ac_objext} + cat >> confdefs.h <<\EOF +#define C_ALLOCA 1 +EOF + + +echo $ac_n "checking whether alloca needs Cray hooks""... $ac_c" 1>&6 +echo "configure:1208: checking whether alloca needs Cray hooks" >&5 +if eval "test \"`echo '$''{'ac_cv_os_cray'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext <&5 | + egrep "webecray" >/dev/null 2>&1; then + rm -rf conftest* + ac_cv_os_cray=yes +else + rm -rf conftest* + ac_cv_os_cray=no +fi +rm -f conftest* + +fi + +echo "$ac_t""$ac_cv_os_cray" 1>&6 +if test $ac_cv_os_cray = yes; then +for ac_func in _getb67 GETB67 getb67; do + echo $ac_n "checking for $ac_func""... $ac_c" 1>&6 +echo "configure:1238: checking for $ac_func" >&5 +if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext < +/* Override any gcc2 internal prototype to avoid an error. */ +/* We use char because int might match the return type of a gcc2 + builtin and then its argument prototype would still apply. */ +char $ac_func(); + +int main() { + +/* The GNU C library defines this for functions which it implements + to always fail with ENOSYS. Some functions are actually named + something starting with __ and the normal name is an alias. */ +#if defined (__stub_$ac_func) || defined (__stub___$ac_func) +choke me +#else +$ac_func(); +#endif + +; return 0; } +EOF +if { (eval echo configure:1266: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then + rm -rf conftest* + eval "ac_cv_func_$ac_func=yes" +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + eval "ac_cv_func_$ac_func=no" +fi +rm -f conftest* +fi + +if eval "test \"`echo '$ac_cv_func_'$ac_func`\" = yes"; then + echo "$ac_t""yes" 1>&6 + cat >> confdefs.h <&6 +fi + +done +fi + +echo $ac_n "checking stack direction for C alloca""... $ac_c" 1>&6 +echo "configure:1293: checking stack direction for C alloca" >&5 +if eval "test \"`echo '$''{'ac_cv_c_stack_direction'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + if test "$cross_compiling" = yes; then + ac_cv_c_stack_direction=0 +else + cat > conftest.$ac_ext < addr) ? 1 : -1; +} +main () +{ + exit (find_stack_direction() < 0); +} +EOF +if { (eval echo configure:1320: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null +then + ac_cv_c_stack_direction=1 +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -fr conftest* + ac_cv_c_stack_direction=-1 +fi +rm -fr conftest* +fi + +fi + +echo "$ac_t""$ac_cv_c_stack_direction" 1>&6 +cat >> confdefs.h <&6 +echo "configure:1345: checking for $ac_hdr" >&5 +if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext < +EOF +ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" +{ (eval echo configure:1355: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` +if test -z "$ac_err"; then + rm -rf conftest* + eval "ac_cv_header_$ac_safe=yes" +else + echo "$ac_err" >&5 + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + eval "ac_cv_header_$ac_safe=no" +fi +rm -f conftest* +fi +if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then + echo "$ac_t""yes" 1>&6 + ac_tr_hdr=HAVE_`echo $ac_hdr | sed 'y%abcdefghijklmnopqrstuvwxyz./-%ABCDEFGHIJKLMNOPQRSTUVWXYZ___%'` + cat >> confdefs.h <&6 +fi +done + +for ac_func in getpagesize +do +echo $ac_n "checking for $ac_func""... $ac_c" 1>&6 +echo "configure:1384: checking for $ac_func" >&5 +if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext < +/* Override any gcc2 internal prototype to avoid an error. */ +/* We use char because int might match the return type of a gcc2 + builtin and then its argument prototype would still apply. */ +char $ac_func(); + +int main() { + +/* The GNU C library defines this for functions which it implements + to always fail with ENOSYS. Some functions are actually named + something starting with __ and the normal name is an alias. */ +#if defined (__stub_$ac_func) || defined (__stub___$ac_func) +choke me +#else +$ac_func(); +#endif + +; return 0; } +EOF +if { (eval echo configure:1412: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then + rm -rf conftest* + eval "ac_cv_func_$ac_func=yes" +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + eval "ac_cv_func_$ac_func=no" +fi +rm -f conftest* +fi + +if eval "test \"`echo '$ac_cv_func_'$ac_func`\" = yes"; then + echo "$ac_t""yes" 1>&6 + ac_tr_func=HAVE_`echo $ac_func | tr 'abcdefghijklmnopqrstuvwxyz' 'ABCDEFGHIJKLMNOPQRSTUVWXYZ'` + cat >> confdefs.h <&6 +fi +done + +echo $ac_n "checking for working mmap""... $ac_c" 1>&6 +echo "configure:1437: checking for working mmap" >&5 +if eval "test \"`echo '$''{'ac_cv_func_mmap_fixed_mapped'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + if test "$cross_compiling" = yes; then + ac_cv_func_mmap_fixed_mapped=no +else + cat > conftest.$ac_ext < +#include +#include + +/* This mess was copied from the GNU getpagesize.h. */ +#ifndef HAVE_GETPAGESIZE +# ifdef HAVE_UNISTD_H +# include +# endif + +/* Assume that all systems that can run configure have sys/param.h. */ +# ifndef HAVE_SYS_PARAM_H +# define HAVE_SYS_PARAM_H 1 +# endif + +# ifdef _SC_PAGESIZE +# define getpagesize() sysconf(_SC_PAGESIZE) +# else /* no _SC_PAGESIZE */ +# ifdef HAVE_SYS_PARAM_H +# include +# ifdef EXEC_PAGESIZE +# define getpagesize() EXEC_PAGESIZE +# else /* no EXEC_PAGESIZE */ +# ifdef NBPG +# define getpagesize() NBPG * CLSIZE +# ifndef CLSIZE +# define CLSIZE 1 +# endif /* no CLSIZE */ +# else /* no NBPG */ +# ifdef NBPC +# define getpagesize() NBPC +# else /* no NBPC */ +# ifdef PAGESIZE +# define getpagesize() PAGESIZE +# endif /* PAGESIZE */ +# endif /* no NBPC */ +# endif /* no NBPG */ +# endif /* no EXEC_PAGESIZE */ +# else /* no HAVE_SYS_PARAM_H */ +# define getpagesize() 8192 /* punt totally */ +# endif /* no HAVE_SYS_PARAM_H */ +# endif /* no _SC_PAGESIZE */ + +#endif /* no HAVE_GETPAGESIZE */ + +#ifdef __cplusplus +extern "C" { void *malloc(unsigned); } +#else +char *malloc(); +#endif + +int +main() +{ + char *data, *data2, *data3; + int i, pagesize; + int fd; + + pagesize = getpagesize(); + + /* + * First, make a file with some known garbage in it. + */ + data = malloc(pagesize); + if (!data) + exit(1); + for (i = 0; i < pagesize; ++i) + *(data + i) = rand(); + umask(0); + fd = creat("conftestmmap", 0600); + if (fd < 0) + exit(1); + if (write(fd, data, pagesize) != pagesize) + exit(1); + close(fd); + + /* + * Next, try to mmap the file at a fixed address which + * already has something else allocated at it. If we can, + * also make sure that we see the same garbage. + */ + fd = open("conftestmmap", O_RDWR); + if (fd < 0) + exit(1); + data2 = malloc(2 * pagesize); + if (!data2) + exit(1); + data2 += (pagesize - ((int) data2 & (pagesize - 1))) & (pagesize - 1); + if (data2 != mmap(data2, pagesize, PROT_READ | PROT_WRITE, + MAP_PRIVATE | MAP_FIXED, fd, 0L)) + exit(1); + for (i = 0; i < pagesize; ++i) + if (*(data + i) != *(data2 + i)) + exit(1); + + /* + * Finally, make sure that changes to the mapped area + * do not percolate back to the file as seen by read(). + * (This is a bug on some variants of i386 svr4.0.) + */ + for (i = 0; i < pagesize; ++i) + *(data2 + i) = *(data2 + i) + 1; + data3 = malloc(pagesize); + if (!data3) + exit(1); + if (read(fd, data3, pagesize) != pagesize) + exit(1); + for (i = 0; i < pagesize; ++i) + if (*(data + i) != *(data3 + i)) + exit(1); + close(fd); + unlink("conftestmmap"); + exit(0); +} + +EOF +if { (eval echo configure:1585: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null +then + ac_cv_func_mmap_fixed_mapped=yes +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -fr conftest* + ac_cv_func_mmap_fixed_mapped=no +fi +rm -fr conftest* +fi + +fi + +echo "$ac_t""$ac_cv_func_mmap_fixed_mapped" 1>&6 +if test $ac_cv_func_mmap_fixed_mapped = yes; then + cat >> confdefs.h <<\EOF +#define HAVE_MMAP 1 +EOF + +fi + +echo $ac_n "checking for Cygwin environment""... $ac_c" 1>&6 +echo "configure:1608: checking for Cygwin environment" >&5 +if eval "test \"`echo '$''{'ac_cv_cygwin'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext <&5; (eval $ac_compile) 2>&5; }; then + rm -rf conftest* + ac_cv_cygwin=yes +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + ac_cv_cygwin=no +fi +rm -f conftest* +rm -f conftest* +fi + +echo "$ac_t""$ac_cv_cygwin" 1>&6 +CYGWIN= +test "$ac_cv_cygwin" = yes && CYGWIN=yes +echo $ac_n "checking for mingw32 environment""... $ac_c" 1>&6 +echo "configure:1641: checking for mingw32 environment" >&5 +if eval "test \"`echo '$''{'ac_cv_mingw32'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext <&5; (eval $ac_compile) 2>&5; }; then + rm -rf conftest* + ac_cv_mingw32=yes +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + ac_cv_mingw32=no +fi +rm -f conftest* +rm -f conftest* +fi + +echo "$ac_t""$ac_cv_mingw32" 1>&6 +MINGW32= +test "$ac_cv_mingw32" = yes && MINGW32=yes + +# autoconf.info says this should be called right after AC_INIT. + + +ac_aux_dir= +for ac_dir in `cd $srcdir;pwd`/../.. $srcdir/`cd $srcdir;pwd`/../..; do + if test -f $ac_dir/install-sh; then + ac_aux_dir=$ac_dir + ac_install_sh="$ac_aux_dir/install-sh -c" + break + elif test -f $ac_dir/install.sh; then + ac_aux_dir=$ac_dir + ac_install_sh="$ac_aux_dir/install.sh -c" + break + fi +done +if test -z "$ac_aux_dir"; then + { echo "configure: error: can not find install-sh or install.sh in `cd $srcdir;pwd`/../.. $srcdir/`cd $srcdir;pwd`/../.." 1>&2; exit 1; } +fi +ac_config_guess=$ac_aux_dir/config.guess +ac_config_sub=$ac_aux_dir/config.sub +ac_configure=$ac_aux_dir/configure # This should be Cygnus configure. + + +# Do some error checking and defaulting for the host and target type. +# The inputs are: +# configure --host=HOST --target=TARGET --build=BUILD NONOPT +# +# The rules are: +# 1. You are not allowed to specify --host, --target, and nonopt at the +# same time. +# 2. Host defaults to nonopt. +# 3. If nonopt is not specified, then host defaults to the current host, +# as determined by config.guess. +# 4. Target and build default to nonopt. +# 5. If nonopt is not specified, then target and build default to host. + +# The aliases save the names the user supplied, while $host etc. +# will get canonicalized. +case $host---$target---$nonopt in +NONE---*---* | *---NONE---* | *---*---NONE) ;; +*) { echo "configure: error: can only configure for one host and one target at a time" 1>&2; exit 1; } ;; +esac + + +# Make sure we can run config.sub. +if ${CONFIG_SHELL-/bin/sh} $ac_config_sub sun4 >/dev/null 2>&1; then : +else { echo "configure: error: can not run $ac_config_sub" 1>&2; exit 1; } +fi + +echo $ac_n "checking host system type""... $ac_c" 1>&6 +echo "configure:1720: checking host system type" >&5 + +host_alias=$host +case "$host_alias" in +NONE) + case $nonopt in + NONE) + if host_alias=`${CONFIG_SHELL-/bin/sh} $ac_config_guess`; then : + else { echo "configure: error: can not guess host type; you must specify one" 1>&2; exit 1; } + fi ;; + *) host_alias=$nonopt ;; + esac ;; +esac + +host=`${CONFIG_SHELL-/bin/sh} $ac_config_sub $host_alias` +host_cpu=`echo $host | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\1/'` +host_vendor=`echo $host | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\2/'` +host_os=`echo $host | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\3/'` +echo "$ac_t""$host" 1>&6 + +echo $ac_n "checking target system type""... $ac_c" 1>&6 +echo "configure:1741: checking target system type" >&5 + +target_alias=$target +case "$target_alias" in +NONE) + case $nonopt in + NONE) target_alias=$host_alias ;; + *) target_alias=$nonopt ;; + esac ;; +esac + +target=`${CONFIG_SHELL-/bin/sh} $ac_config_sub $target_alias` +target_cpu=`echo $target | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\1/'` +target_vendor=`echo $target | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\2/'` +target_os=`echo $target | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\3/'` +echo "$ac_t""$target" 1>&6 + +echo $ac_n "checking build system type""... $ac_c" 1>&6 +echo "configure:1759: checking build system type" >&5 + +build_alias=$build +case "$build_alias" in +NONE) + case $nonopt in + NONE) build_alias=$host_alias ;; + *) build_alias=$nonopt ;; + esac ;; +esac + +build=`${CONFIG_SHELL-/bin/sh} $ac_config_sub $build_alias` +build_cpu=`echo $build | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\1/'` +build_vendor=`echo $build | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\2/'` +build_os=`echo $build | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\3/'` +echo "$ac_t""$build" 1>&6 + +test "$host_alias" != "$target_alias" && + test "$program_prefix$program_suffix$program_transform_name" = \ + NONENONEs,x,x, && + program_prefix=${target_alias}- + +if test "$program_transform_name" = s,x,x,; then + program_transform_name= +else + # Double any \ or $. echo might interpret backslashes. + cat <<\EOF_SED > conftestsed +s,\\,\\\\,g; s,\$,$$,g +EOF_SED + program_transform_name="`echo $program_transform_name|sed -f conftestsed`" + rm -f conftestsed +fi +test "$program_prefix" != NONE && + program_transform_name="s,^,${program_prefix},; $program_transform_name" +# Use a double $ so make ignores it. +test "$program_suffix" != NONE && + program_transform_name="s,\$\$,${program_suffix},; $program_transform_name" + +# sed with no file args requires a program. +test "$program_transform_name" = "" && program_transform_name="s,x,x," + +# Extract the first word of "gcc", so it can be a program name with args. +set dummy gcc; ac_word=$2 +echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 +echo "configure:1803: checking for $ac_word" >&5 +if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else + IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS=":" + ac_dummy="$PATH" + for ac_dir in $ac_dummy; do + test -z "$ac_dir" && ac_dir=. + if test -f $ac_dir/$ac_word; then + ac_cv_prog_CC="gcc" + break + fi + done + IFS="$ac_save_ifs" +fi +fi +CC="$ac_cv_prog_CC" +if test -n "$CC"; then + echo "$ac_t""$CC" 1>&6 +else + echo "$ac_t""no" 1>&6 +fi + +if test -z "$CC"; then + # Extract the first word of "cc", so it can be a program name with args. +set dummy cc; ac_word=$2 +echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 +echo "configure:1833: checking for $ac_word" >&5 +if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else + IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS=":" + ac_prog_rejected=no + ac_dummy="$PATH" + for ac_dir in $ac_dummy; do + test -z "$ac_dir" && ac_dir=. + if test -f $ac_dir/$ac_word; then + if test "$ac_dir/$ac_word" = "/usr/ucb/cc"; then + ac_prog_rejected=yes + continue + fi + ac_cv_prog_CC="cc" + break + fi + done + IFS="$ac_save_ifs" +if test $ac_prog_rejected = yes; then + # We found a bogon in the path, so make sure we never use it. + set dummy $ac_cv_prog_CC + shift + if test $# -gt 0; then + # We chose a different compiler from the bogus one. + # However, it has the same basename, so the bogon will be chosen + # first if we set CC to just the basename; use the full file name. + shift + set dummy "$ac_dir/$ac_word" "$@" + shift + ac_cv_prog_CC="$@" + fi +fi +fi +fi +CC="$ac_cv_prog_CC" +if test -n "$CC"; then + echo "$ac_t""$CC" 1>&6 +else + echo "$ac_t""no" 1>&6 +fi + + if test -z "$CC"; then + case "`uname -s`" in + *win32* | *WIN32*) + # Extract the first word of "cl", so it can be a program name with args. +set dummy cl; ac_word=$2 +echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 +echo "configure:1884: checking for $ac_word" >&5 +if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else + IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS=":" + ac_dummy="$PATH" + for ac_dir in $ac_dummy; do + test -z "$ac_dir" && ac_dir=. + if test -f $ac_dir/$ac_word; then + ac_cv_prog_CC="cl" + break + fi + done + IFS="$ac_save_ifs" +fi +fi +CC="$ac_cv_prog_CC" +if test -n "$CC"; then + echo "$ac_t""$CC" 1>&6 +else + echo "$ac_t""no" 1>&6 +fi + ;; + esac + fi + test -z "$CC" && { echo "configure: error: no acceptable cc found in \$PATH" 1>&2; exit 1; } +fi + +echo $ac_n "checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works""... $ac_c" 1>&6 +echo "configure:1916: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works" >&5 + +ac_ext=c +# CFLAGS is not in ac_cpp because -g, -O, etc. are not valid cpp options. +ac_cpp='$CPP $CPPFLAGS' +ac_compile='${CC-cc} -c $CFLAGS $CPPFLAGS conftest.$ac_ext 1>&5' +ac_link='${CC-cc} -o conftest${ac_exeext} $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS 1>&5' +cross_compiling=$ac_cv_prog_cc_cross + +cat > conftest.$ac_ext << EOF + +#line 1927 "configure" +#include "confdefs.h" + +main(){return(0);} +EOF +if { (eval echo configure:1932: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then + ac_cv_prog_cc_works=yes + # If we can't run a trivial program, we are probably using a cross compiler. + if (./conftest; exit) 2>/dev/null; then + ac_cv_prog_cc_cross=no + else + ac_cv_prog_cc_cross=yes + fi +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + ac_cv_prog_cc_works=no +fi +rm -fr conftest* +ac_ext=c +# CFLAGS is not in ac_cpp because -g, -O, etc. are not valid cpp options. +ac_cpp='$CPP $CPPFLAGS' +ac_compile='${CC-cc} -c $CFLAGS $CPPFLAGS conftest.$ac_ext 1>&5' +ac_link='${CC-cc} -o conftest${ac_exeext} $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS 1>&5' +cross_compiling=$ac_cv_prog_cc_cross + +echo "$ac_t""$ac_cv_prog_cc_works" 1>&6 +if test $ac_cv_prog_cc_works = no; then + { echo "configure: error: installation or configuration problem: C compiler cannot create executables." 1>&2; exit 1; } +fi +echo $ac_n "checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler""... $ac_c" 1>&6 +echo "configure:1958: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler" >&5 +echo "$ac_t""$ac_cv_prog_cc_cross" 1>&6 +cross_compiling=$ac_cv_prog_cc_cross + +echo $ac_n "checking whether we are using GNU C""... $ac_c" 1>&6 +echo "configure:1963: checking whether we are using GNU C" >&5 +if eval "test \"`echo '$''{'ac_cv_prog_gcc'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.c <&5; (eval $ac_try) 2>&5; }; } | egrep yes >/dev/null 2>&1; then + ac_cv_prog_gcc=yes +else + ac_cv_prog_gcc=no +fi +fi + +echo "$ac_t""$ac_cv_prog_gcc" 1>&6 + +if test $ac_cv_prog_gcc = yes; then + GCC=yes +else + GCC= +fi + +ac_test_CFLAGS="${CFLAGS+set}" +ac_save_CFLAGS="$CFLAGS" +CFLAGS= +echo $ac_n "checking whether ${CC-cc} accepts -g""... $ac_c" 1>&6 +echo "configure:1991: checking whether ${CC-cc} accepts -g" >&5 +if eval "test \"`echo '$''{'ac_cv_prog_cc_g'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + echo 'void f(){}' > conftest.c +if test -z "`${CC-cc} -g -c conftest.c 2>&1`"; then + ac_cv_prog_cc_g=yes +else + ac_cv_prog_cc_g=no +fi +rm -f conftest* + +fi + +echo "$ac_t""$ac_cv_prog_cc_g" 1>&6 +if test "$ac_test_CFLAGS" = set; then + CFLAGS="$ac_save_CFLAGS" +elif test $ac_cv_prog_cc_g = yes; then + if test "$GCC" = yes; then + CFLAGS="-g -O2" + else + CFLAGS="-g" + fi +else + if test "$GCC" = yes; then + CFLAGS="-O2" + else + CFLAGS= + fi +fi + +# Find a good install program. We prefer a C program (faster), +# so one script is as good as another. But avoid the broken or +# incompatible versions: +# SysV /etc/install, /usr/sbin/install +# SunOS /usr/etc/install +# IRIX /sbin/install +# AIX /bin/install +# AIX 4 /usr/bin/installbsd, which doesn't work without a -g flag +# AFS /usr/afsws/bin/install, which mishandles nonexistent args +# SVR4 /usr/ucb/install, which tries to use the nonexistent group "staff" +# ./install, which can be erroneously created by make from ./install.sh. +echo $ac_n "checking for a BSD compatible install""... $ac_c" 1>&6 +echo "configure:2034: checking for a BSD compatible install" >&5 +if test -z "$INSTALL"; then +if eval "test \"`echo '$''{'ac_cv_path_install'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + IFS="${IFS= }"; ac_save_IFS="$IFS"; IFS=":" + for ac_dir in $PATH; do + # Account for people who put trailing slashes in PATH elements. + case "$ac_dir/" in + /|./|.//|/etc/*|/usr/sbin/*|/usr/etc/*|/sbin/*|/usr/afsws/bin/*|/usr/ucb/*) ;; + *) + # OSF1 and SCO ODT 3.0 have their own names for install. + # Don't use installbsd from OSF since it installs stuff as root + # by default. + for ac_prog in ginstall scoinst install; do + if test -f $ac_dir/$ac_prog; then + if test $ac_prog = install && + grep dspmsg $ac_dir/$ac_prog >/dev/null 2>&1; then + # AIX install. It has an incompatible calling convention. + : + else + ac_cv_path_install="$ac_dir/$ac_prog -c" + break 2 + fi + fi + done + ;; + esac + done + IFS="$ac_save_IFS" + +fi + if test "${ac_cv_path_install+set}" = set; then + INSTALL="$ac_cv_path_install" + else + # As a last resort, use the slow shell script. We don't cache a + # path for INSTALL within a source directory, because that will + # break other packages using the cache if that directory is + # removed, or if the path is relative. + INSTALL="$ac_install_sh" + fi +fi +echo "$ac_t""$INSTALL" 1>&6 + +# Use test -z because SunOS4 sh mishandles braces in ${var-val}. +# It thinks the first close brace ends the variable substitution. +test -z "$INSTALL_PROGRAM" && INSTALL_PROGRAM='${INSTALL}' + +test -z "$INSTALL_SCRIPT" && INSTALL_SCRIPT='${INSTALL_PROGRAM}' + +test -z "$INSTALL_DATA" && INSTALL_DATA='${INSTALL} -m 644' + + +# Put a plausible default for CC_FOR_BUILD in Makefile. +if test "x$cross_compiling" = "xno"; then + CC_FOR_BUILD='$(CC)' +else + CC_FOR_BUILD=gcc +fi + + + + +AR=${AR-ar} + +# Extract the first word of "ranlib", so it can be a program name with args. +set dummy ranlib; ac_word=$2 +echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 +echo "configure:2102: checking for $ac_word" >&5 +if eval "test \"`echo '$''{'ac_cv_prog_RANLIB'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + if test -n "$RANLIB"; then + ac_cv_prog_RANLIB="$RANLIB" # Let the user override the test. +else + IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS=":" + ac_dummy="$PATH" + for ac_dir in $ac_dummy; do + test -z "$ac_dir" && ac_dir=. + if test -f $ac_dir/$ac_word; then + ac_cv_prog_RANLIB="ranlib" + break + fi + done + IFS="$ac_save_ifs" + test -z "$ac_cv_prog_RANLIB" && ac_cv_prog_RANLIB=":" +fi +fi +RANLIB="$ac_cv_prog_RANLIB" +if test -n "$RANLIB"; then + echo "$ac_t""$RANLIB" 1>&6 +else + echo "$ac_t""no" 1>&6 +fi + + +ALL_LINGUAS= + + for ac_hdr in argz.h limits.h locale.h nl_types.h malloc.h string.h \ +unistd.h values.h sys/param.h +do +ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'` +echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6 +echo "configure:2137: checking for $ac_hdr" >&5 +if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext < +EOF +ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" +{ (eval echo configure:2147: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` +if test -z "$ac_err"; then + rm -rf conftest* + eval "ac_cv_header_$ac_safe=yes" +else + echo "$ac_err" >&5 + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + eval "ac_cv_header_$ac_safe=no" +fi +rm -f conftest* +fi +if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then + echo "$ac_t""yes" 1>&6 + ac_tr_hdr=HAVE_`echo $ac_hdr | sed 'y%abcdefghijklmnopqrstuvwxyz./-%ABCDEFGHIJKLMNOPQRSTUVWXYZ___%'` + cat >> confdefs.h <&6 +fi +done + + for ac_func in getcwd munmap putenv setenv setlocale strchr strcasecmp \ +__argz_count __argz_stringify __argz_next +do +echo $ac_n "checking for $ac_func""... $ac_c" 1>&6 +echo "configure:2177: checking for $ac_func" >&5 +if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext < +/* Override any gcc2 internal prototype to avoid an error. */ +/* We use char because int might match the return type of a gcc2 + builtin and then its argument prototype would still apply. */ +char $ac_func(); + +int main() { + +/* The GNU C library defines this for functions which it implements + to always fail with ENOSYS. Some functions are actually named + something starting with __ and the normal name is an alias. */ +#if defined (__stub_$ac_func) || defined (__stub___$ac_func) +choke me +#else +$ac_func(); +#endif + +; return 0; } +EOF +if { (eval echo configure:2205: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then + rm -rf conftest* + eval "ac_cv_func_$ac_func=yes" +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + eval "ac_cv_func_$ac_func=no" +fi +rm -f conftest* +fi + +if eval "test \"`echo '$ac_cv_func_'$ac_func`\" = yes"; then + echo "$ac_t""yes" 1>&6 + ac_tr_func=HAVE_`echo $ac_func | tr 'abcdefghijklmnopqrstuvwxyz' 'ABCDEFGHIJKLMNOPQRSTUVWXYZ'` + cat >> confdefs.h <&6 +fi +done + + + if test "${ac_cv_func_stpcpy+set}" != "set"; then + for ac_func in stpcpy +do +echo $ac_n "checking for $ac_func""... $ac_c" 1>&6 +echo "configure:2234: checking for $ac_func" >&5 +if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext < +/* Override any gcc2 internal prototype to avoid an error. */ +/* We use char because int might match the return type of a gcc2 + builtin and then its argument prototype would still apply. */ +char $ac_func(); + +int main() { + +/* The GNU C library defines this for functions which it implements + to always fail with ENOSYS. Some functions are actually named + something starting with __ and the normal name is an alias. */ +#if defined (__stub_$ac_func) || defined (__stub___$ac_func) +choke me +#else +$ac_func(); +#endif + +; return 0; } +EOF +if { (eval echo configure:2262: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then + rm -rf conftest* + eval "ac_cv_func_$ac_func=yes" +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + eval "ac_cv_func_$ac_func=no" +fi +rm -f conftest* +fi + +if eval "test \"`echo '$ac_cv_func_'$ac_func`\" = yes"; then + echo "$ac_t""yes" 1>&6 + ac_tr_func=HAVE_`echo $ac_func | tr 'abcdefghijklmnopqrstuvwxyz' 'ABCDEFGHIJKLMNOPQRSTUVWXYZ'` + cat >> confdefs.h <&6 +fi +done + + fi + if test "${ac_cv_func_stpcpy}" = "yes"; then + cat >> confdefs.h <<\EOF +#define HAVE_STPCPY 1 +EOF + + fi + + if test $ac_cv_header_locale_h = yes; then + echo $ac_n "checking for LC_MESSAGES""... $ac_c" 1>&6 +echo "configure:2296: checking for LC_MESSAGES" >&5 +if eval "test \"`echo '$''{'am_cv_val_LC_MESSAGES'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext < +int main() { +return LC_MESSAGES +; return 0; } +EOF +if { (eval echo configure:2308: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then + rm -rf conftest* + am_cv_val_LC_MESSAGES=yes +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + am_cv_val_LC_MESSAGES=no +fi +rm -f conftest* +fi + +echo "$ac_t""$am_cv_val_LC_MESSAGES" 1>&6 + if test $am_cv_val_LC_MESSAGES = yes; then + cat >> confdefs.h <<\EOF +#define HAVE_LC_MESSAGES 1 +EOF + + fi + fi + echo $ac_n "checking whether NLS is requested""... $ac_c" 1>&6 +echo "configure:2329: checking whether NLS is requested" >&5 + # Check whether --enable-nls or --disable-nls was given. +if test "${enable_nls+set}" = set; then + enableval="$enable_nls" + USE_NLS=$enableval +else + USE_NLS=yes +fi + + echo "$ac_t""$USE_NLS" 1>&6 + + + USE_INCLUDED_LIBINTL=no + + if test "$USE_NLS" = "yes"; then + cat >> confdefs.h <<\EOF +#define ENABLE_NLS 1 +EOF + + echo $ac_n "checking whether included gettext is requested""... $ac_c" 1>&6 +echo "configure:2349: checking whether included gettext is requested" >&5 + # Check whether --with-included-gettext or --without-included-gettext was given. +if test "${with_included_gettext+set}" = set; then + withval="$with_included_gettext" + nls_cv_force_use_gnu_gettext=$withval +else + nls_cv_force_use_gnu_gettext=no +fi + + echo "$ac_t""$nls_cv_force_use_gnu_gettext" 1>&6 + + nls_cv_use_gnu_gettext="$nls_cv_force_use_gnu_gettext" + if test "$nls_cv_force_use_gnu_gettext" != "yes"; then + nls_cv_header_intl= + nls_cv_header_libgt= + CATOBJEXT=NONE + + ac_safe=`echo "libintl.h" | sed 'y%./+-%__p_%'` +echo $ac_n "checking for libintl.h""... $ac_c" 1>&6 +echo "configure:2368: checking for libintl.h" >&5 +if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext < +EOF +ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" +{ (eval echo configure:2378: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` +if test -z "$ac_err"; then + rm -rf conftest* + eval "ac_cv_header_$ac_safe=yes" +else + echo "$ac_err" >&5 + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + eval "ac_cv_header_$ac_safe=no" +fi +rm -f conftest* +fi +if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then + echo "$ac_t""yes" 1>&6 + echo $ac_n "checking for gettext in libc""... $ac_c" 1>&6 +echo "configure:2395: checking for gettext in libc" >&5 +if eval "test \"`echo '$''{'gt_cv_func_gettext_libc'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext < +int main() { +return (int) gettext ("") +; return 0; } +EOF +if { (eval echo configure:2407: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then + rm -rf conftest* + gt_cv_func_gettext_libc=yes +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + gt_cv_func_gettext_libc=no +fi +rm -f conftest* +fi + +echo "$ac_t""$gt_cv_func_gettext_libc" 1>&6 + + if test "$gt_cv_func_gettext_libc" != "yes"; then + echo $ac_n "checking for bindtextdomain in -lintl""... $ac_c" 1>&6 +echo "configure:2423: checking for bindtextdomain in -lintl" >&5 +ac_lib_var=`echo intl'_'bindtextdomain | sed 'y%./+-%__p_%'` +if eval "test \"`echo '$''{'ac_cv_lib_$ac_lib_var'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + ac_save_LIBS="$LIBS" +LIBS="-lintl $LIBS" +cat > conftest.$ac_ext <&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then + rm -rf conftest* + eval "ac_cv_lib_$ac_lib_var=yes" +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + eval "ac_cv_lib_$ac_lib_var=no" +fi +rm -f conftest* +LIBS="$ac_save_LIBS" + +fi +if eval "test \"`echo '$ac_cv_lib_'$ac_lib_var`\" = yes"; then + echo "$ac_t""yes" 1>&6 + echo $ac_n "checking for gettext in libintl""... $ac_c" 1>&6 +echo "configure:2458: checking for gettext in libintl" >&5 +if eval "test \"`echo '$''{'gt_cv_func_gettext_libintl'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext <&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then + rm -rf conftest* + gt_cv_func_gettext_libintl=yes +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + gt_cv_func_gettext_libintl=no +fi +rm -f conftest* +fi + +echo "$ac_t""$gt_cv_func_gettext_libintl" 1>&6 +else + echo "$ac_t""no" 1>&6 +fi + + fi + + if test "$gt_cv_func_gettext_libc" = "yes" \ + || test "$gt_cv_func_gettext_libintl" = "yes"; then + cat >> confdefs.h <<\EOF +#define HAVE_GETTEXT 1 +EOF + + # Extract the first word of "msgfmt", so it can be a program name with args. +set dummy msgfmt; ac_word=$2 +echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 +echo "configure:2498: checking for $ac_word" >&5 +if eval "test \"`echo '$''{'ac_cv_path_MSGFMT'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + case "$MSGFMT" in + /*) + ac_cv_path_MSGFMT="$MSGFMT" # Let the user override the test with a path. + ;; + *) + IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS="${IFS}:" + for ac_dir in $PATH; do + test -z "$ac_dir" && ac_dir=. + if test -f $ac_dir/$ac_word; then + if test -z "`$ac_dir/$ac_word -h 2>&1 | grep 'dv '`"; then + ac_cv_path_MSGFMT="$ac_dir/$ac_word" + break + fi + fi + done + IFS="$ac_save_ifs" + test -z "$ac_cv_path_MSGFMT" && ac_cv_path_MSGFMT="no" + ;; +esac +fi +MSGFMT="$ac_cv_path_MSGFMT" +if test -n "$MSGFMT"; then + echo "$ac_t""$MSGFMT" 1>&6 +else + echo "$ac_t""no" 1>&6 +fi + if test "$MSGFMT" != "no"; then + for ac_func in dcgettext +do +echo $ac_n "checking for $ac_func""... $ac_c" 1>&6 +echo "configure:2532: checking for $ac_func" >&5 +if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext < +/* Override any gcc2 internal prototype to avoid an error. */ +/* We use char because int might match the return type of a gcc2 + builtin and then its argument prototype would still apply. */ +char $ac_func(); + +int main() { + +/* The GNU C library defines this for functions which it implements + to always fail with ENOSYS. Some functions are actually named + something starting with __ and the normal name is an alias. */ +#if defined (__stub_$ac_func) || defined (__stub___$ac_func) +choke me +#else +$ac_func(); +#endif + +; return 0; } +EOF +if { (eval echo configure:2560: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then + rm -rf conftest* + eval "ac_cv_func_$ac_func=yes" +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + eval "ac_cv_func_$ac_func=no" +fi +rm -f conftest* +fi + +if eval "test \"`echo '$ac_cv_func_'$ac_func`\" = yes"; then + echo "$ac_t""yes" 1>&6 + ac_tr_func=HAVE_`echo $ac_func | tr 'abcdefghijklmnopqrstuvwxyz' 'ABCDEFGHIJKLMNOPQRSTUVWXYZ'` + cat >> confdefs.h <&6 +fi +done + + # Extract the first word of "gmsgfmt", so it can be a program name with args. +set dummy gmsgfmt; ac_word=$2 +echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 +echo "configure:2587: checking for $ac_word" >&5 +if eval "test \"`echo '$''{'ac_cv_path_GMSGFMT'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + case "$GMSGFMT" in + /*) + ac_cv_path_GMSGFMT="$GMSGFMT" # Let the user override the test with a path. + ;; + ?:/*) + ac_cv_path_GMSGFMT="$GMSGFMT" # Let the user override the test with a dos path. + ;; + *) + IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS=":" + ac_dummy="$PATH" + for ac_dir in $ac_dummy; do + test -z "$ac_dir" && ac_dir=. + if test -f $ac_dir/$ac_word; then + ac_cv_path_GMSGFMT="$ac_dir/$ac_word" + break + fi + done + IFS="$ac_save_ifs" + test -z "$ac_cv_path_GMSGFMT" && ac_cv_path_GMSGFMT="$MSGFMT" + ;; +esac +fi +GMSGFMT="$ac_cv_path_GMSGFMT" +if test -n "$GMSGFMT"; then + echo "$ac_t""$GMSGFMT" 1>&6 +else + echo "$ac_t""no" 1>&6 +fi + + # Extract the first word of "xgettext", so it can be a program name with args. +set dummy xgettext; ac_word=$2 +echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 +echo "configure:2623: checking for $ac_word" >&5 +if eval "test \"`echo '$''{'ac_cv_path_XGETTEXT'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + case "$XGETTEXT" in + /*) + ac_cv_path_XGETTEXT="$XGETTEXT" # Let the user override the test with a path. + ;; + *) + IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS="${IFS}:" + for ac_dir in $PATH; do + test -z "$ac_dir" && ac_dir=. + if test -f $ac_dir/$ac_word; then + if test -z "`$ac_dir/$ac_word -h 2>&1 | grep '(HELP)'`"; then + ac_cv_path_XGETTEXT="$ac_dir/$ac_word" + break + fi + fi + done + IFS="$ac_save_ifs" + test -z "$ac_cv_path_XGETTEXT" && ac_cv_path_XGETTEXT=":" + ;; +esac +fi +XGETTEXT="$ac_cv_path_XGETTEXT" +if test -n "$XGETTEXT"; then + echo "$ac_t""$XGETTEXT" 1>&6 +else + echo "$ac_t""no" 1>&6 +fi + + cat > conftest.$ac_ext <&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then + rm -rf conftest* + CATOBJEXT=.gmo + DATADIRNAME=share +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + CATOBJEXT=.mo + DATADIRNAME=lib +fi +rm -f conftest* + INSTOBJEXT=.mo + fi + fi + +else + echo "$ac_t""no" 1>&6 +fi + + + + if test "$CATOBJEXT" = "NONE"; then + nls_cv_use_gnu_gettext=yes + fi + fi + + if test "$nls_cv_use_gnu_gettext" = "yes"; then + INTLOBJS="\$(GETTOBJS)" + # Extract the first word of "msgfmt", so it can be a program name with args. +set dummy msgfmt; ac_word=$2 +echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 +echo "configure:2695: checking for $ac_word" >&5 +if eval "test \"`echo '$''{'ac_cv_path_MSGFMT'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + case "$MSGFMT" in + /*) + ac_cv_path_MSGFMT="$MSGFMT" # Let the user override the test with a path. + ;; + *) + IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS="${IFS}:" + for ac_dir in $PATH; do + test -z "$ac_dir" && ac_dir=. + if test -f $ac_dir/$ac_word; then + if test -z "`$ac_dir/$ac_word -h 2>&1 | grep 'dv '`"; then + ac_cv_path_MSGFMT="$ac_dir/$ac_word" + break + fi + fi + done + IFS="$ac_save_ifs" + test -z "$ac_cv_path_MSGFMT" && ac_cv_path_MSGFMT="msgfmt" + ;; +esac +fi +MSGFMT="$ac_cv_path_MSGFMT" +if test -n "$MSGFMT"; then + echo "$ac_t""$MSGFMT" 1>&6 +else + echo "$ac_t""no" 1>&6 +fi + + # Extract the first word of "gmsgfmt", so it can be a program name with args. +set dummy gmsgfmt; ac_word=$2 +echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 +echo "configure:2729: checking for $ac_word" >&5 +if eval "test \"`echo '$''{'ac_cv_path_GMSGFMT'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + case "$GMSGFMT" in + /*) + ac_cv_path_GMSGFMT="$GMSGFMT" # Let the user override the test with a path. + ;; + ?:/*) + ac_cv_path_GMSGFMT="$GMSGFMT" # Let the user override the test with a dos path. + ;; + *) + IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS=":" + ac_dummy="$PATH" + for ac_dir in $ac_dummy; do + test -z "$ac_dir" && ac_dir=. + if test -f $ac_dir/$ac_word; then + ac_cv_path_GMSGFMT="$ac_dir/$ac_word" + break + fi + done + IFS="$ac_save_ifs" + test -z "$ac_cv_path_GMSGFMT" && ac_cv_path_GMSGFMT="$MSGFMT" + ;; +esac +fi +GMSGFMT="$ac_cv_path_GMSGFMT" +if test -n "$GMSGFMT"; then + echo "$ac_t""$GMSGFMT" 1>&6 +else + echo "$ac_t""no" 1>&6 +fi + + # Extract the first word of "xgettext", so it can be a program name with args. +set dummy xgettext; ac_word=$2 +echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 +echo "configure:2765: checking for $ac_word" >&5 +if eval "test \"`echo '$''{'ac_cv_path_XGETTEXT'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + case "$XGETTEXT" in + /*) + ac_cv_path_XGETTEXT="$XGETTEXT" # Let the user override the test with a path. + ;; + *) + IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS="${IFS}:" + for ac_dir in $PATH; do + test -z "$ac_dir" && ac_dir=. + if test -f $ac_dir/$ac_word; then + if test -z "`$ac_dir/$ac_word -h 2>&1 | grep '(HELP)'`"; then + ac_cv_path_XGETTEXT="$ac_dir/$ac_word" + break + fi + fi + done + IFS="$ac_save_ifs" + test -z "$ac_cv_path_XGETTEXT" && ac_cv_path_XGETTEXT=":" + ;; +esac +fi +XGETTEXT="$ac_cv_path_XGETTEXT" +if test -n "$XGETTEXT"; then + echo "$ac_t""$XGETTEXT" 1>&6 +else + echo "$ac_t""no" 1>&6 +fi + + + USE_INCLUDED_LIBINTL=yes + CATOBJEXT=.gmo + INSTOBJEXT=.mo + DATADIRNAME=share + INTLDEPS='$(top_builddir)/../intl/libintl.a' + INTLLIBS=$INTLDEPS + LIBS=`echo $LIBS | sed -e 's/-lintl//'` + nls_cv_header_intl=libintl.h + nls_cv_header_libgt=libgettext.h + fi + + if test "$XGETTEXT" != ":"; then + if $XGETTEXT --omit-header /dev/null 2> /dev/null; then + : ; + else + echo "$ac_t""found xgettext programs is not GNU xgettext; ignore it" 1>&6 + XGETTEXT=":" + fi + fi + + # We need to process the po/ directory. + POSUB=po + else + DATADIRNAME=share + nls_cv_header_intl=libintl.h + nls_cv_header_libgt=libgettext.h + fi + + # If this is used in GNU gettext we have to set USE_NLS to `yes' + # because some of the sources are only built for this goal. + if test "$PACKAGE" = gettext; then + USE_NLS=yes + USE_INCLUDED_LIBINTL=yes + fi + + for lang in $ALL_LINGUAS; do + GMOFILES="$GMOFILES $lang.gmo" + POFILES="$POFILES $lang.po" + done + + + + + + + + + + + + + + + if test "x$CATOBJEXT" != "x"; then + if test "x$ALL_LINGUAS" = "x"; then + LINGUAS= + else + echo $ac_n "checking for catalogs to be installed""... $ac_c" 1>&6 +echo "configure:2855: checking for catalogs to be installed" >&5 + NEW_LINGUAS= + for lang in ${LINGUAS=$ALL_LINGUAS}; do + case "$ALL_LINGUAS" in + *$lang*) NEW_LINGUAS="$NEW_LINGUAS $lang" ;; + esac + done + LINGUAS=$NEW_LINGUAS + echo "$ac_t""$LINGUAS" 1>&6 + fi + + if test -n "$LINGUAS"; then + for lang in $LINGUAS; do CATALOGS="$CATALOGS $lang$CATOBJEXT"; done + fi + fi + + if test $ac_cv_header_locale_h = yes; then + INCLUDE_LOCALE_H="#include " + else + INCLUDE_LOCALE_H="\ +/* The system does not provide the header . Take care yourself. */" + fi + + + if test -f $srcdir/po2tbl.sed.in; then + if test "$CATOBJEXT" = ".cat"; then + ac_safe=`echo "linux/version.h" | sed 'y%./+-%__p_%'` +echo $ac_n "checking for linux/version.h""... $ac_c" 1>&6 +echo "configure:2883: checking for linux/version.h" >&5 +if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext < +EOF +ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" +{ (eval echo configure:2893: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` +if test -z "$ac_err"; then + rm -rf conftest* + eval "ac_cv_header_$ac_safe=yes" +else + echo "$ac_err" >&5 + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + eval "ac_cv_header_$ac_safe=no" +fi +rm -f conftest* +fi +if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then + echo "$ac_t""yes" 1>&6 + msgformat=linux +else + echo "$ac_t""no" 1>&6 +msgformat=xopen +fi + + + sed -e '/^#/d' $srcdir/$msgformat-msg.sed > po2msg.sed + fi + sed -e '/^#.*[^\\]$/d' -e '/^#$/d' \ + $srcdir/po2tbl.sed.in > po2tbl.sed + fi + + if test "$PACKAGE" = "gettext"; then + GT_NO="#NO#" + GT_YES= + else + GT_NO= + GT_YES="#YES#" + fi + + + + MKINSTALLDIRS="\$(srcdir)/../../mkinstalldirs" + + + l= + + + if test -d $srcdir/po; then + test -d po || mkdir po + if test "x$srcdir" != "x."; then + if test "x`echo $srcdir | sed 's@/.*@@'`" = "x"; then + posrcprefix="$srcdir/" + else + posrcprefix="../$srcdir/" + fi + else + posrcprefix="../" + fi + rm -f po/POTFILES + sed -e "/^#/d" -e "/^\$/d" -e "s,.*, $posrcprefix& \\\\," -e "\$s/\(.*\) \\\\/\1/" \ + < $srcdir/po/POTFILES.in > po/POTFILES + fi + + +# Check for common headers. +# FIXME: Seems to me this can cause problems for i386-windows hosts. +# At one point there were hardcoded AC_DEFINE's if ${host} = i386-*-windows*. +for ac_hdr in stdlib.h string.h strings.h unistd.h time.h +do +ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'` +echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6 +echo "configure:2962: checking for $ac_hdr" >&5 +if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext < +EOF +ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" +{ (eval echo configure:2972: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` +if test -z "$ac_err"; then + rm -rf conftest* + eval "ac_cv_header_$ac_safe=yes" +else + echo "$ac_err" >&5 + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + eval "ac_cv_header_$ac_safe=no" +fi +rm -f conftest* +fi +if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then + echo "$ac_t""yes" 1>&6 + ac_tr_hdr=HAVE_`echo $ac_hdr | sed 'y%abcdefghijklmnopqrstuvwxyz./-%ABCDEFGHIJKLMNOPQRSTUVWXYZ___%'` + cat >> confdefs.h <&6 +fi +done + +for ac_hdr in sys/time.h sys/resource.h +do +ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'` +echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6 +echo "configure:3002: checking for $ac_hdr" >&5 +if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext < +EOF +ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" +{ (eval echo configure:3012: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` +if test -z "$ac_err"; then + rm -rf conftest* + eval "ac_cv_header_$ac_safe=yes" +else + echo "$ac_err" >&5 + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + eval "ac_cv_header_$ac_safe=no" +fi +rm -f conftest* +fi +if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then + echo "$ac_t""yes" 1>&6 + ac_tr_hdr=HAVE_`echo $ac_hdr | sed 'y%abcdefghijklmnopqrstuvwxyz./-%ABCDEFGHIJKLMNOPQRSTUVWXYZ___%'` + cat >> confdefs.h <&6 +fi +done + +for ac_hdr in fcntl.h fpu_control.h +do +ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'` +echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6 +echo "configure:3042: checking for $ac_hdr" >&5 +if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext < +EOF +ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" +{ (eval echo configure:3052: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` +if test -z "$ac_err"; then + rm -rf conftest* + eval "ac_cv_header_$ac_safe=yes" +else + echo "$ac_err" >&5 + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + eval "ac_cv_header_$ac_safe=no" +fi +rm -f conftest* +fi +if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then + echo "$ac_t""yes" 1>&6 + ac_tr_hdr=HAVE_`echo $ac_hdr | sed 'y%abcdefghijklmnopqrstuvwxyz./-%ABCDEFGHIJKLMNOPQRSTUVWXYZ___%'` + cat >> confdefs.h <&6 +fi +done + +for ac_hdr in dlfcn.h errno.h sys/stat.h +do +ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'` +echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6 +echo "configure:3082: checking for $ac_hdr" >&5 +if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext < +EOF +ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" +{ (eval echo configure:3092: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` +if test -z "$ac_err"; then + rm -rf conftest* + eval "ac_cv_header_$ac_safe=yes" +else + echo "$ac_err" >&5 + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + eval "ac_cv_header_$ac_safe=no" +fi +rm -f conftest* +fi +if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then + echo "$ac_t""yes" 1>&6 + ac_tr_hdr=HAVE_`echo $ac_hdr | sed 'y%abcdefghijklmnopqrstuvwxyz./-%ABCDEFGHIJKLMNOPQRSTUVWXYZ___%'` + cat >> confdefs.h <&6 +fi +done + +for ac_func in getrusage time sigaction __setfpucw +do +echo $ac_n "checking for $ac_func""... $ac_c" 1>&6 +echo "configure:3121: checking for $ac_func" >&5 +if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext < +/* Override any gcc2 internal prototype to avoid an error. */ +/* We use char because int might match the return type of a gcc2 + builtin and then its argument prototype would still apply. */ +char $ac_func(); + +int main() { + +/* The GNU C library defines this for functions which it implements + to always fail with ENOSYS. Some functions are actually named + something starting with __ and the normal name is an alias. */ +#if defined (__stub_$ac_func) || defined (__stub___$ac_func) +choke me +#else +$ac_func(); +#endif + +; return 0; } +EOF +if { (eval echo configure:3149: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then + rm -rf conftest* + eval "ac_cv_func_$ac_func=yes" +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + eval "ac_cv_func_$ac_func=no" +fi +rm -f conftest* +fi + +if eval "test \"`echo '$ac_cv_func_'$ac_func`\" = yes"; then + echo "$ac_t""yes" 1>&6 + ac_tr_func=HAVE_`echo $ac_func | tr 'abcdefghijklmnopqrstuvwxyz' 'ABCDEFGHIJKLMNOPQRSTUVWXYZ'` + cat >> confdefs.h <&6 +fi +done + + +# Check for socket libraries +echo $ac_n "checking for bind in -lsocket""... $ac_c" 1>&6 +echo "configure:3176: checking for bind in -lsocket" >&5 +ac_lib_var=`echo socket'_'bind | sed 'y%./+-%__p_%'` +if eval "test \"`echo '$''{'ac_cv_lib_$ac_lib_var'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + ac_save_LIBS="$LIBS" +LIBS="-lsocket $LIBS" +cat > conftest.$ac_ext <&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then + rm -rf conftest* + eval "ac_cv_lib_$ac_lib_var=yes" +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + eval "ac_cv_lib_$ac_lib_var=no" +fi +rm -f conftest* +LIBS="$ac_save_LIBS" + +fi +if eval "test \"`echo '$ac_cv_lib_'$ac_lib_var`\" = yes"; then + echo "$ac_t""yes" 1>&6 + ac_tr_lib=HAVE_LIB`echo socket | sed -e 's/[^a-zA-Z0-9_]/_/g' \ + -e 'y/abcdefghijklmnopqrstuvwxyz/ABCDEFGHIJKLMNOPQRSTUVWXYZ/'` + cat >> confdefs.h <&6 +fi + +echo $ac_n "checking for gethostbyname in -lnsl""... $ac_c" 1>&6 +echo "configure:3223: checking for gethostbyname in -lnsl" >&5 +ac_lib_var=`echo nsl'_'gethostbyname | sed 'y%./+-%__p_%'` +if eval "test \"`echo '$''{'ac_cv_lib_$ac_lib_var'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + ac_save_LIBS="$LIBS" +LIBS="-lnsl $LIBS" +cat > conftest.$ac_ext <&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then + rm -rf conftest* + eval "ac_cv_lib_$ac_lib_var=yes" +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + eval "ac_cv_lib_$ac_lib_var=no" +fi +rm -f conftest* +LIBS="$ac_save_LIBS" + +fi +if eval "test \"`echo '$ac_cv_lib_'$ac_lib_var`\" = yes"; then + echo "$ac_t""yes" 1>&6 + ac_tr_lib=HAVE_LIB`echo nsl | sed -e 's/[^a-zA-Z0-9_]/_/g' \ + -e 'y/abcdefghijklmnopqrstuvwxyz/ABCDEFGHIJKLMNOPQRSTUVWXYZ/'` + cat >> confdefs.h <&6 +fi + + +. ${srcdir}/../../bfd/configure.host + + + +USE_MAINTAINER_MODE=no +# Check whether --enable-maintainer-mode or --disable-maintainer-mode was given. +if test "${enable_maintainer_mode+set}" = set; then + enableval="$enable_maintainer_mode" + case "${enableval}" in + yes) MAINT="" USE_MAINTAINER_MODE=yes ;; + no) MAINT="#" ;; + *) { echo "configure: error: "--enable-maintainer-mode does not take a value"" 1>&2; exit 1; }; MAINT="#" ;; +esac +if test x"$silent" != x"yes" && test x"$MAINT" = x""; then + echo "Setting maintainer mode" 6>&1 +fi +else + MAINT="#" +fi + + + +# Check whether --enable-sim-bswap or --disable-sim-bswap was given. +if test "${enable_sim_bswap+set}" = set; then + enableval="$enable_sim_bswap" + case "${enableval}" in + yes) sim_bswap="-DWITH_BSWAP=1 -DUSE_BSWAP=1";; + no) sim_bswap="-DWITH_BSWAP=0";; + *) { echo "configure: error: "--enable-sim-bswap does not take a value"" 1>&2; exit 1; }; sim_bswap="";; +esac +if test x"$silent" != x"yes" && test x"$sim_bswap" != x""; then + echo "Setting bswap flags = $sim_bswap" 6>&1 +fi +else + sim_bswap="" +fi + + + +# Check whether --enable-sim-cflags or --disable-sim-cflags was given. +if test "${enable_sim_cflags+set}" = set; then + enableval="$enable_sim_cflags" + case "${enableval}" in + yes) sim_cflags="-O2 -fomit-frame-pointer";; + trace) { echo "configure: error: "Please use --enable-sim-debug instead."" 1>&2; exit 1; }; sim_cflags="";; + no) sim_cflags="";; + *) sim_cflags=`echo "${enableval}" | sed -e "s/,/ /g"`;; +esac +if test x"$silent" != x"yes" && test x"$sim_cflags" != x""; then + echo "Setting sim cflags = $sim_cflags" 6>&1 +fi +else + sim_cflags="" +fi + + + +# Check whether --enable-sim-debug or --disable-sim-debug was given. +if test "${enable_sim_debug+set}" = set; then + enableval="$enable_sim_debug" + case "${enableval}" in + yes) sim_debug="-DDEBUG=7 -DWITH_DEBUG=7";; + no) sim_debug="-DDEBUG=0 -DWITH_DEBUG=0";; + *) sim_debug="-DDEBUG='(${enableval})' -DWITH_DEBUG='(${enableval})'";; +esac +if test x"$silent" != x"yes" && test x"$sim_debug" != x""; then + echo "Setting sim debug = $sim_debug" 6>&1 +fi +else + sim_debug="" +fi + + + +# Check whether --enable-sim-stdio or --disable-sim-stdio was given. +if test "${enable_sim_stdio+set}" = set; then + enableval="$enable_sim_stdio" + case "${enableval}" in + yes) sim_stdio="-DWITH_STDIO=DO_USE_STDIO";; + no) sim_stdio="-DWITH_STDIO=DONT_USE_STDIO";; + *) { echo "configure: error: "Unknown value $enableval passed to --enable-sim-stdio"" 1>&2; exit 1; }; sim_stdio="";; +esac +if test x"$silent" != x"yes" && test x"$sim_stdio" != x""; then + echo "Setting stdio flags = $sim_stdio" 6>&1 +fi +else + sim_stdio="" +fi + + + +# Check whether --enable-sim-trace or --disable-sim-trace was given. +if test "${enable_sim_trace+set}" = set; then + enableval="$enable_sim_trace" + case "${enableval}" in + yes) sim_trace="-DTRACE=1 -DWITH_TRACE=-1";; + no) sim_trace="-DTRACE=0 -DWITH_TRACE=0";; + [-0-9]*) + sim_trace="-DTRACE='(${enableval})' -DWITH_TRACE='(${enableval})'";; + [a-z]*) + sim_trace="" + for x in `echo "$enableval" | sed -e "s/,/ /g"`; do + if test x"$sim_trace" = x; then + sim_trace="-DWITH_TRACE='(TRACE_$x" + else + sim_trace="${sim_trace}|TRACE_$x" + fi + done + sim_trace="$sim_trace)'" ;; +esac +if test x"$silent" != x"yes" && test x"$sim_trace" != x""; then + echo "Setting sim trace = $sim_trace" 6>&1 +fi +else + sim_trace="" +fi + + + +# Check whether --enable-sim-profile or --disable-sim-profile was given. +if test "${enable_sim_profile+set}" = set; then + enableval="$enable_sim_profile" + case "${enableval}" in + yes) sim_profile="-DPROFILE=1 -DWITH_PROFILE=-1";; + no) sim_profile="-DPROFILE=0 -DWITH_PROFILE=0";; + [-0-9]*) + sim_profile="-DPROFILE='(${enableval})' -DWITH_PROFILE='(${enableval})'";; + [a-z]*) + sim_profile="" + for x in `echo "$enableval" | sed -e "s/,/ /g"`; do + if test x"$sim_profile" = x; then + sim_profile="-DWITH_PROFILE='(PROFILE_$x" + else + sim_profile="${sim_profile}|PROFILE_$x" + fi + done + sim_profile="$sim_profile)'" ;; +esac +if test x"$silent" != x"yes" && test x"$sim_profile" != x""; then + echo "Setting sim profile = $sim_profile" 6>&1 +fi +else + sim_profile="-DPROFILE=1 -DWITH_PROFILE=-1" +fi + + + +echo $ac_n "checking return type of signal handlers""... $ac_c" 1>&6 +echo "configure:3418: checking return type of signal handlers" >&5 +if eval "test \"`echo '$''{'ac_cv_type_signal'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext < +#include +#ifdef signal +#undef signal +#endif +#ifdef __cplusplus +extern "C" void (*signal (int, void (*)(int)))(int); +#else +void (*signal ()) (); +#endif + +int main() { +int i; +; return 0; } +EOF +if { (eval echo configure:3440: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then + rm -rf conftest* + ac_cv_type_signal=void +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + ac_cv_type_signal=int +fi +rm -f conftest* +fi + +echo "$ac_t""$ac_cv_type_signal" 1>&6 +cat >> confdefs.h <&6 +echo "configure:3462: checking for executable suffix" >&5 +if eval "test \"`echo '$''{'ac_cv_exeext'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + if test "$CYGWIN" = yes || test "$MINGW32" = yes; then + ac_cv_exeext=.exe +else + rm -f conftest* + echo 'int main () { return 0; }' > conftest.$ac_ext + ac_cv_exeext= + if { (eval echo configure:3472: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; }; then + for file in conftest.*; do + case $file in + *.c | *.o | *.obj | *.ilk | *.pdb) ;; + *) ac_cv_exeext=`echo $file | sed -e s/conftest//` ;; + esac + done + else + { echo "configure: error: installation or configuration problem: compiler cannot create executables." 1>&2; exit 1; } + fi + rm -f conftest* + test x"${ac_cv_exeext}" = x && ac_cv_exeext=no +fi +fi + +EXEEXT="" +test x"${ac_cv_exeext}" != xno && EXEEXT=${ac_cv_exeext} +echo "$ac_t""${ac_cv_exeext}" 1>&6 +ac_exeext=$EXEEXT + + +sim_link_files= +sim_link_links= + +sim_link_links=tconfig.h +if test -f ${srcdir}/tconfig.in +then + sim_link_files=tconfig.in +else + sim_link_files=../common/tconfig.in +fi + +# targ-vals.def points to the libc macro description file. +case "${target}" in +*-*-*) TARG_VALS_DEF=../common/nltvals.def ;; +esac +sim_link_files="${sim_link_files} ${TARG_VALS_DEF}" +sim_link_links="${sim_link_links} targ-vals.def" + + + + +wire_endian="BIG_ENDIAN" +default_endian="" +# Check whether --enable-sim-endian or --disable-sim-endian was given. +if test "${enable_sim_endian+set}" = set; then + enableval="$enable_sim_endian" + case "${enableval}" in + b*|B*) sim_endian="-DWITH_TARGET_BYTE_ORDER=BIG_ENDIAN";; + l*|L*) sim_endian="-DWITH_TARGET_BYTE_ORDER=LITTLE_ENDIAN";; + yes) if test x"$wire_endian" != x; then + sim_endian="-DWITH_TARGET_BYTE_ORDER=${wire_endian}" + else + if test x"$default_endian" != x; then + sim_endian="-DWITH_TARGET_BYTE_ORDER=${default_endian}" + else + echo "No hard-wired endian for target $target" 1>&6 + sim_endian="-DWITH_TARGET_BYTE_ORDER=0" + fi + fi;; + no) if test x"$default_endian" != x; then + sim_endian="-DWITH_DEFAULT_TARGET_BYTE_ORDER=${default_endian}" + else + if test x"$wire_endian" != x; then + sim_endian="-DWITH_DEFAULT_TARGET_BYTE_ORDER=${wire_endian}" + else + echo "No default endian for target $target" 1>&6 + sim_endian="-DWITH_DEFAULT_TARGET_BYTE_ORDER=0" + fi + fi;; + *) { echo "configure: error: "Unknown value $enableval for --enable-sim-endian"" 1>&2; exit 1; }; sim_endian="";; +esac +if test x"$silent" != x"yes" && test x"$sim_endian" != x""; then + echo "Setting endian flags = $sim_endian" 6>&1 +fi +else + if test x"$default_endian" != x; then + sim_endian="-DWITH_DEFAULT_TARGET_BYTE_ORDER=${default_endian}" +else + if test x"$wire_endian" != x; then + sim_endian="-DWITH_TARGET_BYTE_ORDER=${wire_endian}" + else + sim_endian= + fi +fi +fi + +wire_alignment="STRICT_ALIGNMENT" +default_alignment="" + +# Check whether --enable-sim-alignment or --disable-sim-alignment was given. +if test "${enable_sim_alignment+set}" = set; then + enableval="$enable_sim_alignment" + case "${enableval}" in + strict | STRICT) sim_alignment="-DWITH_ALIGNMENT=STRICT_ALIGNMENT";; + nonstrict | NONSTRICT) sim_alignment="-DWITH_ALIGNMENT=NONSTRICT_ALIGNMENT";; + forced | FORCED) sim_alignment="-DWITH_ALIGNMENT=FORCED_ALIGNMENT";; + yes) if test x"$wire_alignment" != x; then + sim_alignment="-DWITH_ALIGNMENT=${wire_alignment}" + else + if test x"$default_alignment" != x; then + sim_alignment="-DWITH_ALIGNMENT=${default_alignment}" + else + echo "No hard-wired alignment for target $target" 1>&6 + sim_alignment="-DWITH_ALIGNMENT=0" + fi + fi;; + no) if test x"$default_alignment" != x; then + sim_alignment="-DWITH_DEFAULT_ALIGNMENT=${default_alignment}" + else + if test x"$wire_alignment" != x; then + sim_alignment="-DWITH_DEFAULT_ALIGNMENT=${wire_alignment}" + else + echo "No default alignment for target $target" 1>&6 + sim_alignment="-DWITH_DEFAULT_ALIGNMENT=0" + fi + fi;; + *) { echo "configure: error: "Unknown value $enableval passed to --enable-sim-alignment"" 1>&2; exit 1; }; sim_alignment="";; +esac +if test x"$silent" != x"yes" && test x"$sim_alignment" != x""; then + echo "Setting alignment flags = $sim_alignment" 6>&1 +fi +else + if test x"$default_alignment" != x; then + sim_alignment="-DWITH_DEFAULT_ALIGNMENT=${default_alignment}" +else + if test x"$wire_alignment" != x; then + sim_alignment="-DWITH_ALIGNMENT=${wire_alignment}" + else + sim_alignment= + fi +fi +fi + + +# Check whether --enable-sim-hostendian or --disable-sim-hostendian was given. +if test "${enable_sim_hostendian+set}" = set; then + enableval="$enable_sim_hostendian" + case "${enableval}" in + no) sim_hostendian="-DWITH_HOST_BYTE_ORDER=0";; + b*|B*) sim_hostendian="-DWITH_HOST_BYTE_ORDER=BIG_ENDIAN";; + l*|L*) sim_hostendian="-DWITH_HOST_BYTE_ORDER=LITTLE_ENDIAN";; + *) { echo "configure: error: "Unknown value $enableval for --enable-sim-hostendian"" 1>&2; exit 1; }; sim_hostendian="";; +esac +if test x"$silent" != x"yes" && test x"$sim_hostendian" != x""; then + echo "Setting hostendian flags = $sim_hostendian" 6>&1 +fi +else + +if test "x$cross_compiling" = "xno"; then + echo $ac_n "checking whether byte ordering is bigendian""... $ac_c" 1>&6 +echo "configure:3623: checking whether byte ordering is bigendian" >&5 +if eval "test \"`echo '$''{'ac_cv_c_bigendian'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + ac_cv_c_bigendian=unknown +# See if sys/param.h defines the BYTE_ORDER macro. +cat > conftest.$ac_ext < +#include +int main() { + +#if !BYTE_ORDER || !BIG_ENDIAN || !LITTLE_ENDIAN + bogus endian macros +#endif +; return 0; } +EOF +if { (eval echo configure:3641: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then + rm -rf conftest* + # It does; now see whether it defined to BIG_ENDIAN or not. +cat > conftest.$ac_ext < +#include +int main() { + +#if BYTE_ORDER != BIG_ENDIAN + not big endian +#endif +; return 0; } +EOF +if { (eval echo configure:3656: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then + rm -rf conftest* + ac_cv_c_bigendian=yes +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + ac_cv_c_bigendian=no +fi +rm -f conftest* +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 +fi +rm -f conftest* +if test $ac_cv_c_bigendian = unknown; then +if test "$cross_compiling" = yes; then + { echo "configure: error: can not run test program while cross compiling" 1>&2; exit 1; } +else + cat > conftest.$ac_ext <&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null +then + ac_cv_c_bigendian=no +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -fr conftest* + ac_cv_c_bigendian=yes +fi +rm -fr conftest* +fi + +fi +fi + +echo "$ac_t""$ac_cv_c_bigendian" 1>&6 +if test $ac_cv_c_bigendian = yes; then + cat >> confdefs.h <<\EOF +#define WORDS_BIGENDIAN 1 +EOF + +fi + + if test $ac_cv_c_bigendian = yes; then + sim_hostendian="-DWITH_HOST_BYTE_ORDER=BIG_ENDIAN" + else + sim_hostendian="-DWITH_HOST_BYTE_ORDER=LITTLE_ENDIAN" + fi +else + sim_hostendian="-DWITH_HOST_BYTE_ORDER=0" +fi +fi + + +default_sim_scache="16384" +# Check whether --enable-sim-scache or --disable-sim-scache was given. +if test "${enable_sim_scache+set}" = set; then + enableval="$enable_sim_scache" + case "${enableval}" in + yes) sim_scache="-DWITH_SCACHE=${default_sim_scache}";; + no) sim_scache="-DWITH_SCACHE=0" ;; + [0-9]*) sim_cache=${enableval};; + *) { echo "configure: error: "Bad value $enableval passed to --enable-sim-scache"" 1>&2; exit 1; }; + sim_scache="";; +esac +if test x"$silent" != x"yes" && test x"$sim_scache" != x""; then + echo "Setting scache size = $sim_scache" 6>&1 +fi +else + sim_scache="-DWITH_SCACHE=${default_sim_scache}" +fi + + + +default_sim_default_model="fr500" +# Check whether --enable-sim-default-model or --disable-sim-default-model was given. +if test "${enable_sim_default_model+set}" = set; then + enableval="$enable_sim_default_model" + case "${enableval}" in + yes|no) { echo "configure: error: "Missing argument to --enable-sim-default-model"" 1>&2; exit 1; };; + *) sim_default_model="-DWITH_DEFAULT_MODEL='\"${enableval}\"'";; +esac +if test x"$silent" != x"yes" && test x"$sim_default_model" != x""; then + echo "Setting default model = $sim_default_model" 6>&1 +fi +else + sim_default_model="-DWITH_DEFAULT_MODEL='\"${default_sim_default_model}\"'" +fi + + + +# Check whether --enable-sim-environment or --disable-sim-environment was given. +if test "${enable_sim_environment+set}" = set; then + enableval="$enable_sim_environment" + case "${enableval}" in + all | ALL) sim_environment="-DWITH_ENVIRONMENT=ALL_ENVIRONMENT";; + user | USER) sim_environment="-DWITH_ENVIRONMENT=USER_ENVIRONMENT";; + virtual | VIRTUAL) sim_environment="-DWITH_ENVIRONMENT=VIRTUAL_ENVIRONMENT";; + operating | OPERATING) sim_environment="-DWITH_ENVIRONMENT=OPERATING_ENVIRONMENT";; + *) { echo "configure: error: "Unknown value $enableval passed to --enable-sim-environment"" 1>&2; exit 1; }; + sim_environment="";; +esac +if test x"$silent" != x"yes" && test x"$sim_environment" != x""; then + echo "Setting sim environment = $sim_environment" 6>&1 +fi +else + sim_environment="-DWITH_ENVIRONMENT=ALL_ENVIRONMENT" +fi + + +cgen_maint=no +cgendir='$(srcdir)/../../cgen' + +# Check whether --enable-cgen-maint or --disable-cgen-maint was given. +if test "${enable_cgen_maint+set}" = set; then + enableval="$enable_cgen_maint" + case "${enableval}" in + yes) cgen_maint=yes ;; + no) cgen_maint=no ;; + *) + # argument is cgen install directory (not implemented yet). + # Having a `share' directory might be more appropriate for the .scm, + # .cpu, etc. files. + cgendir=${cgen_maint}/lib/cgen + ;; +esac +fi +if test x${cgen_maint} != xno ; then + CGEN_MAINT='' +else + CGEN_MAINT='#' +fi + + + + + +# +# Enable making unknown traps dump out registers +# +# Check whether --enable-sim-trapdump or --disable-sim-trapdump was given. +if test "${enable_sim_trapdump+set}" = set; then + enableval="$enable_sim_trapdump" + case "${enableval}" in + yes) sim_trapdump="-DTRAPDUMP=1";; + no) sim_trapdump="-DTRAPDUMP=0";; + *) { echo "configure: error: "Unknown value $enableval passed to --enable-sim-trapdump"" 1>&2; exit 1; }; sim_trapdump="";; +esac +if test x"$silent" != x"yes" && test x"$sim_trapdump" != x""; then + echo "Setting sim_trapdump = $sim_trapdump" 6>&1 +fi +else + sim_trapdump="" +fi + + + + +trap '' 1 2 15 +cat > confcache <<\EOF +# This file is a shell script that caches the results of configure +# tests run on this system so they can be shared between configure +# scripts and configure runs. It is not useful on other systems. +# If it contains results you don't want to keep, you may remove or edit it. +# +# By default, configure uses ./config.cache as the cache file, +# creating it if it does not exist already. You can give configure +# the --cache-file=FILE option to use a different cache file; that is +# what configure does when it calls configure scripts in +# subdirectories, so they share the cache. +# Giving --cache-file=/dev/null disables caching, for debugging configure. +# config.status only pays attention to the cache file if you give it the +# --recheck option to rerun configure. +# +EOF +# The following way of writing the cache mishandles newlines in values, +# but we know of no workaround that is simple, portable, and efficient. +# So, don't put newlines in cache variables' values. +# Ultrix sh set writes to stderr and can't be redirected directly, +# and sets the high bit in the cache file unless we assign to the vars. +(set) 2>&1 | + case `(ac_space=' '; set | grep ac_space) 2>&1` in + *ac_space=\ *) + # `set' does not quote correctly, so add quotes (double-quote substitution + # turns \\\\ into \\, and sed turns \\ into \). + sed -n \ + -e "s/'/'\\\\''/g" \ + -e "s/^\\([a-zA-Z0-9_]*_cv_[a-zA-Z0-9_]*\\)=\\(.*\\)/\\1=\${\\1='\\2'}/p" + ;; + *) + # `set' quotes correctly as required by POSIX, so do not add quotes. + sed -n -e 's/^\([a-zA-Z0-9_]*_cv_[a-zA-Z0-9_]*\)=\(.*\)/\1=${\1=\2}/p' + ;; + esac >> confcache +if cmp -s $cache_file confcache; then + : +else + if test -w $cache_file; then + echo "updating cache $cache_file" + cat confcache > $cache_file + else + echo "not updating unwritable cache $cache_file" + fi +fi +rm -f confcache + +trap 'rm -fr conftest* confdefs* core core.* *.core $ac_clean_files; exit 1' 1 2 15 + +test "x$prefix" = xNONE && prefix=$ac_default_prefix +# Let make expand exec_prefix. +test "x$exec_prefix" = xNONE && exec_prefix='${prefix}' + +# Any assignment to VPATH causes Sun make to only execute +# the first set of double-colon rules, so remove it if not needed. +# If there is a colon in the path, we need to keep it. +if test "x$srcdir" = x.; then + ac_vpsub='/^[ ]*VPATH[ ]*=[^:]*$/d' +fi + +trap 'rm -f $CONFIG_STATUS conftest*; exit 1' 1 2 15 + +DEFS=-DHAVE_CONFIG_H + +# Without the "./", some shells look in PATH for config.status. +: ${CONFIG_STATUS=./config.status} + +echo creating $CONFIG_STATUS +rm -f $CONFIG_STATUS +cat > $CONFIG_STATUS </dev/null | sed 1q`: +# +# $0 $ac_configure_args +# +# Compiler output produced by configure, useful for debugging +# configure, is in ./config.log if it exists. + +ac_cs_usage="Usage: $CONFIG_STATUS [--recheck] [--version] [--help]" +for ac_option +do + case "\$ac_option" in + -recheck | --recheck | --rechec | --reche | --rech | --rec | --re | --r) + echo "running \${CONFIG_SHELL-/bin/sh} $0 $ac_configure_args --no-create --no-recursion" + exec \${CONFIG_SHELL-/bin/sh} $0 $ac_configure_args --no-create --no-recursion ;; + -version | --version | --versio | --versi | --vers | --ver | --ve | --v) + echo "$CONFIG_STATUS generated by autoconf version 2.13" + exit 0 ;; + -help | --help | --hel | --he | --h) + echo "\$ac_cs_usage"; exit 0 ;; + *) echo "\$ac_cs_usage"; exit 1 ;; + esac +done + +ac_given_srcdir=$srcdir +ac_given_INSTALL="$INSTALL" + +trap 'rm -fr `echo "Makefile.sim:Makefile.in Make-common.sim:../common/Make-common.in .gdbinit:../common/gdbinit.in config.h:config.in" | sed "s/:[^ ]*//g"` conftest*; exit 1' 1 2 15 +EOF +cat >> $CONFIG_STATUS < conftest.subs <<\\CEOF +$ac_vpsub +$extrasub +s%@sim_environment@%$sim_environment%g +s%@sim_alignment@%$sim_alignment%g +s%@sim_assert@%$sim_assert%g +s%@sim_bitsize@%$sim_bitsize%g +s%@sim_endian@%$sim_endian%g +s%@sim_hostendian@%$sim_hostendian%g +s%@sim_float@%$sim_float%g +s%@sim_scache@%$sim_scache%g +s%@sim_default_model@%$sim_default_model%g +s%@sim_hw_cflags@%$sim_hw_cflags%g +s%@sim_hw_objs@%$sim_hw_objs%g +s%@sim_hw@%$sim_hw%g +s%@sim_inline@%$sim_inline%g +s%@sim_packages@%$sim_packages%g +s%@sim_regparm@%$sim_regparm%g +s%@sim_reserved_bits@%$sim_reserved_bits%g +s%@sim_smp@%$sim_smp%g +s%@sim_stdcall@%$sim_stdcall%g +s%@sim_xor_endian@%$sim_xor_endian%g +s%@WARN_CFLAGS@%$WARN_CFLAGS%g +s%@WERROR_CFLAGS@%$WERROR_CFLAGS%g +s%@SHELL@%$SHELL%g +s%@CFLAGS@%$CFLAGS%g +s%@CPPFLAGS@%$CPPFLAGS%g +s%@CXXFLAGS@%$CXXFLAGS%g +s%@FFLAGS@%$FFLAGS%g +s%@DEFS@%$DEFS%g +s%@LDFLAGS@%$LDFLAGS%g +s%@LIBS@%$LIBS%g +s%@exec_prefix@%$exec_prefix%g +s%@prefix@%$prefix%g +s%@program_transform_name@%$program_transform_name%g +s%@bindir@%$bindir%g +s%@sbindir@%$sbindir%g +s%@libexecdir@%$libexecdir%g +s%@datadir@%$datadir%g +s%@sysconfdir@%$sysconfdir%g +s%@sharedstatedir@%$sharedstatedir%g +s%@localstatedir@%$localstatedir%g +s%@libdir@%$libdir%g +s%@includedir@%$includedir%g +s%@oldincludedir@%$oldincludedir%g +s%@infodir@%$infodir%g +s%@mandir@%$mandir%g +s%@host@%$host%g +s%@host_alias@%$host_alias%g +s%@host_cpu@%$host_cpu%g +s%@host_vendor@%$host_vendor%g +s%@host_os@%$host_os%g +s%@target@%$target%g +s%@target_alias@%$target_alias%g +s%@target_cpu@%$target_cpu%g +s%@target_vendor@%$target_vendor%g +s%@target_os@%$target_os%g +s%@build@%$build%g +s%@build_alias@%$build_alias%g +s%@build_cpu@%$build_cpu%g +s%@build_vendor@%$build_vendor%g +s%@build_os@%$build_os%g +s%@CC@%$CC%g +s%@INSTALL_PROGRAM@%$INSTALL_PROGRAM%g +s%@INSTALL_SCRIPT@%$INSTALL_SCRIPT%g +s%@INSTALL_DATA@%$INSTALL_DATA%g +s%@CC_FOR_BUILD@%$CC_FOR_BUILD%g +s%@HDEFINES@%$HDEFINES%g +s%@AR@%$AR%g +s%@RANLIB@%$RANLIB%g +s%@SET_MAKE@%$SET_MAKE%g +s%@CPP@%$CPP%g +s%@ALLOCA@%$ALLOCA%g +s%@USE_NLS@%$USE_NLS%g +s%@MSGFMT@%$MSGFMT%g +s%@GMSGFMT@%$GMSGFMT%g +s%@XGETTEXT@%$XGETTEXT%g +s%@USE_INCLUDED_LIBINTL@%$USE_INCLUDED_LIBINTL%g +s%@CATALOGS@%$CATALOGS%g +s%@CATOBJEXT@%$CATOBJEXT%g +s%@DATADIRNAME@%$DATADIRNAME%g +s%@GMOFILES@%$GMOFILES%g +s%@INSTOBJEXT@%$INSTOBJEXT%g +s%@INTLDEPS@%$INTLDEPS%g +s%@INTLLIBS@%$INTLLIBS%g +s%@INTLOBJS@%$INTLOBJS%g +s%@POFILES@%$POFILES%g +s%@POSUB@%$POSUB%g +s%@INCLUDE_LOCALE_H@%$INCLUDE_LOCALE_H%g +s%@GT_NO@%$GT_NO%g +s%@GT_YES@%$GT_YES%g +s%@MKINSTALLDIRS@%$MKINSTALLDIRS%g +s%@l@%$l%g +s%@MAINT@%$MAINT%g +s%@sim_bswap@%$sim_bswap%g +s%@sim_cflags@%$sim_cflags%g +s%@sim_debug@%$sim_debug%g +s%@sim_stdio@%$sim_stdio%g +s%@sim_trace@%$sim_trace%g +s%@sim_profile@%$sim_profile%g +s%@EXEEXT@%$EXEEXT%g +s%@CGEN_MAINT@%$CGEN_MAINT%g +s%@cgendir@%$cgendir%g +s%@cgen@%$cgen%g +s%@sim_trapdump@%$sim_trapdump%g + +CEOF +EOF + +cat >> $CONFIG_STATUS <<\EOF + +# Split the substitutions into bite-sized pieces for seds with +# small command number limits, like on Digital OSF/1 and HP-UX. +ac_max_sed_cmds=90 # Maximum number of lines to put in a sed script. +ac_file=1 # Number of current file. +ac_beg=1 # First line for current file. +ac_end=$ac_max_sed_cmds # Line after last line for current file. +ac_more_lines=: +ac_sed_cmds="" +while $ac_more_lines; do + if test $ac_beg -gt 1; then + sed "1,${ac_beg}d; ${ac_end}q" conftest.subs > conftest.s$ac_file + else + sed "${ac_end}q" conftest.subs > conftest.s$ac_file + fi + if test ! -s conftest.s$ac_file; then + ac_more_lines=false + rm -f conftest.s$ac_file + else + if test -z "$ac_sed_cmds"; then + ac_sed_cmds="sed -f conftest.s$ac_file" + else + ac_sed_cmds="$ac_sed_cmds | sed -f conftest.s$ac_file" + fi + ac_file=`expr $ac_file + 1` + ac_beg=$ac_end + ac_end=`expr $ac_end + $ac_max_sed_cmds` + fi +done +if test -z "$ac_sed_cmds"; then + ac_sed_cmds=cat +fi +EOF + +cat >> $CONFIG_STATUS <> $CONFIG_STATUS <<\EOF +for ac_file in .. $CONFIG_FILES; do if test "x$ac_file" != x..; then + # Support "outfile[:infile[:infile...]]", defaulting infile="outfile.in". + case "$ac_file" in + *:*) ac_file_in=`echo "$ac_file"|sed 's%[^:]*:%%'` + ac_file=`echo "$ac_file"|sed 's%:.*%%'` ;; + *) ac_file_in="${ac_file}.in" ;; + esac + + # Adjust a relative srcdir, top_srcdir, and INSTALL for subdirectories. + + # Remove last slash and all that follows it. Not all systems have dirname. + ac_dir=`echo $ac_file|sed 's%/[^/][^/]*$%%'` + if test "$ac_dir" != "$ac_file" && test "$ac_dir" != .; then + # The file is in a subdirectory. + test ! -d "$ac_dir" && mkdir "$ac_dir" + ac_dir_suffix="/`echo $ac_dir|sed 's%^\./%%'`" + # A "../" for each directory in $ac_dir_suffix. + ac_dots=`echo $ac_dir_suffix|sed 's%/[^/]*%../%g'` + else + ac_dir_suffix= ac_dots= + fi + + case "$ac_given_srcdir" in + .) srcdir=. + if test -z "$ac_dots"; then top_srcdir=. + else top_srcdir=`echo $ac_dots|sed 's%/$%%'`; fi ;; + /*) srcdir="$ac_given_srcdir$ac_dir_suffix"; top_srcdir="$ac_given_srcdir" ;; + *) # Relative path. + srcdir="$ac_dots$ac_given_srcdir$ac_dir_suffix" + top_srcdir="$ac_dots$ac_given_srcdir" ;; + esac + + case "$ac_given_INSTALL" in + [/$]*) INSTALL="$ac_given_INSTALL" ;; + *) INSTALL="$ac_dots$ac_given_INSTALL" ;; + esac + + echo creating "$ac_file" + rm -f "$ac_file" + configure_input="Generated automatically from `echo $ac_file_in|sed 's%.*/%%'` by configure." + case "$ac_file" in + *Makefile*) ac_comsub="1i\\ +# $configure_input" ;; + *) ac_comsub= ;; + esac + + ac_file_inputs=`echo $ac_file_in|sed -e "s%^%$ac_given_srcdir/%" -e "s%:% $ac_given_srcdir/%g"` + sed -e "$ac_comsub +s%@configure_input@%$configure_input%g +s%@srcdir@%$srcdir%g +s%@top_srcdir@%$top_srcdir%g +s%@INSTALL@%$INSTALL%g +" $ac_file_inputs | (eval "$ac_sed_cmds") > $ac_file +fi; done +rm -f conftest.s* + +# These sed commands are passed to sed as "A NAME B NAME C VALUE D", where +# NAME is the cpp macro being defined and VALUE is the value it is being given. +# +# ac_d sets the value in "#define NAME VALUE" lines. +ac_dA='s%^\([ ]*\)#\([ ]*define[ ][ ]*\)' +ac_dB='\([ ][ ]*\)[^ ]*%\1#\2' +ac_dC='\3' +ac_dD='%g' +# ac_u turns "#undef NAME" with trailing blanks into "#define NAME VALUE". +ac_uA='s%^\([ ]*\)#\([ ]*\)undef\([ ][ ]*\)' +ac_uB='\([ ]\)%\1#\2define\3' +ac_uC=' ' +ac_uD='\4%g' +# ac_e turns "#undef NAME" without trailing blanks into "#define NAME VALUE". +ac_eA='s%^\([ ]*\)#\([ ]*\)undef\([ ][ ]*\)' +ac_eB='$%\1#\2define\3' +ac_eC=' ' +ac_eD='%g' + +if test "${CONFIG_HEADERS+set}" != set; then +EOF +cat >> $CONFIG_STATUS <> $CONFIG_STATUS <<\EOF +fi +for ac_file in .. $CONFIG_HEADERS; do if test "x$ac_file" != x..; then + # Support "outfile[:infile[:infile...]]", defaulting infile="outfile.in". + case "$ac_file" in + *:*) ac_file_in=`echo "$ac_file"|sed 's%[^:]*:%%'` + ac_file=`echo "$ac_file"|sed 's%:.*%%'` ;; + *) ac_file_in="${ac_file}.in" ;; + esac + + echo creating $ac_file + + rm -f conftest.frag conftest.in conftest.out + ac_file_inputs=`echo $ac_file_in|sed -e "s%^%$ac_given_srcdir/%" -e "s%:% $ac_given_srcdir/%g"` + cat $ac_file_inputs > conftest.in + +EOF + +# Transform confdefs.h into a sed script conftest.vals that substitutes +# the proper values into config.h.in to produce config.h. And first: +# Protect against being on the right side of a sed subst in config.status. +# Protect against being in an unquoted here document in config.status. +rm -f conftest.vals +cat > conftest.hdr <<\EOF +s/[\\&%]/\\&/g +s%[\\$`]%\\&%g +s%#define \([A-Za-z_][A-Za-z0-9_]*\) *\(.*\)%${ac_dA}\1${ac_dB}\1${ac_dC}\2${ac_dD}%gp +s%ac_d%ac_u%gp +s%ac_u%ac_e%gp +EOF +sed -n -f conftest.hdr confdefs.h > conftest.vals +rm -f conftest.hdr + +# This sed command replaces #undef with comments. This is necessary, for +# example, in the case of _POSIX_SOURCE, which is predefined and required +# on some systems where configure will not decide to define it. +cat >> conftest.vals <<\EOF +s%^[ ]*#[ ]*undef[ ][ ]*[a-zA-Z_][a-zA-Z_0-9]*%/* & */% +EOF + +# Break up conftest.vals because some shells have a limit on +# the size of here documents, and old seds have small limits too. + +rm -f conftest.tail +while : +do + ac_lines=`grep -c . conftest.vals` + # grep -c gives empty output for an empty file on some AIX systems. + if test -z "$ac_lines" || test "$ac_lines" -eq 0; then break; fi + # Write a limited-size here document to conftest.frag. + echo ' cat > conftest.frag <> $CONFIG_STATUS + sed ${ac_max_here_lines}q conftest.vals >> $CONFIG_STATUS + echo 'CEOF + sed -f conftest.frag conftest.in > conftest.out + rm -f conftest.in + mv conftest.out conftest.in +' >> $CONFIG_STATUS + sed 1,${ac_max_here_lines}d conftest.vals > conftest.tail + rm -f conftest.vals + mv conftest.tail conftest.vals +done +rm -f conftest.vals + +cat >> $CONFIG_STATUS <<\EOF + rm -f conftest.frag conftest.h + echo "/* $ac_file. Generated automatically by configure. */" > conftest.h + cat conftest.in >> conftest.h + rm -f conftest.in + if cmp -s $ac_file conftest.h 2>/dev/null; then + echo "$ac_file is unchanged" + rm -f conftest.h + else + # Remove last slash and all that follows it. Not all systems have dirname. + ac_dir=`echo $ac_file|sed 's%/[^/][^/]*$%%'` + if test "$ac_dir" != "$ac_file" && test "$ac_dir" != .; then + # The file is in a subdirectory. + test ! -d "$ac_dir" && mkdir "$ac_dir" + fi + rm -f $ac_file + mv conftest.h $ac_file + fi +fi; done + +EOF + +cat >> $CONFIG_STATUS <> $CONFIG_STATUS <<\EOF +srcdir=$ac_given_srcdir +while test -n "$ac_sources"; do + set $ac_dests; ac_dest=$1; shift; ac_dests=$* + set $ac_sources; ac_source=$1; shift; ac_sources=$* + + echo "linking $srcdir/$ac_source to $ac_dest" + + if test ! -r $srcdir/$ac_source; then + { echo "configure: error: $srcdir/$ac_source: File not found" 1>&2; exit 1; } + fi + rm -f $ac_dest + + # Make relative symlinks. + # Remove last slash and all that follows it. Not all systems have dirname. + ac_dest_dir=`echo $ac_dest|sed 's%/[^/][^/]*$%%'` + if test "$ac_dest_dir" != "$ac_dest" && test "$ac_dest_dir" != .; then + # The dest file is in a subdirectory. + test ! -d "$ac_dest_dir" && mkdir "$ac_dest_dir" + ac_dest_dir_suffix="/`echo $ac_dest_dir|sed 's%^\./%%'`" + # A "../" for each directory in $ac_dest_dir_suffix. + ac_dots=`echo $ac_dest_dir_suffix|sed 's%/[^/]*%../%g'` + else + ac_dest_dir_suffix= ac_dots= + fi + + case "$srcdir" in + [/$]*) ac_rel_source="$srcdir/$ac_source" ;; + *) ac_rel_source="$ac_dots$srcdir/$ac_source" ;; + esac + + # Make a symlink if possible; otherwise try a hard link. + if ln -s $ac_rel_source $ac_dest 2>/dev/null || + ln $srcdir/$ac_source $ac_dest; then : + else + { echo "configure: error: can not link $ac_dest to $srcdir/$ac_source" 1>&2; exit 1; } + fi +done +EOF +cat >> $CONFIG_STATUS <> $CONFIG_STATUS <<\EOF +case "x$CONFIG_FILES" in + xMakefile*) + echo "Merging Makefile.sim+Make-common.sim into Makefile ..." + rm -f Makesim1.tmp Makesim2.tmp Makefile + sed -n -e '/^## COMMON_PRE_/,/^## End COMMON_PRE_/ p' Makesim1.tmp + sed -n -e '/^## COMMON_POST_/,/^## End COMMON_POST_/ p' Makesim2.tmp + sed -e '/^## COMMON_PRE_/ r Makesim1.tmp' \ + -e '/^## COMMON_POST_/ r Makesim2.tmp' \ + Makefile + rm -f Makefile.sim Make-common.sim Makesim1.tmp Makesim2.tmp + ;; + esac + case "x$CONFIG_HEADERS" in xconfig.h:config.in) echo > stamp-h ;; esac + +exit 0 +EOF +chmod +x $CONFIG_STATUS +rm -fr confdefs* $ac_clean_files +test "$no_create" = yes || ${CONFIG_SHELL-/bin/sh} $CONFIG_STATUS || exit 1 + + diff --git a/sim/frv/configure.in b/sim/frv/configure.in new file mode 100644 index 0000000..62ff5af --- /dev/null +++ b/sim/frv/configure.in @@ -0,0 +1,31 @@ +dnl Process this file with autoconf to produce a configure script. +sinclude(../common/aclocal.m4) +AC_PREREQ(2.5)dnl +AC_INIT(Makefile.in) + +SIM_AC_COMMON + +SIM_AC_OPTION_ENDIAN(BIG_ENDIAN) +SIM_AC_OPTION_ALIGNMENT(STRICT_ALIGNMENT) +SIM_AC_OPTION_HOSTENDIAN +SIM_AC_OPTION_SCACHE(16384) +SIM_AC_OPTION_DEFAULT_MODEL(fr500) +SIM_AC_OPTION_ENVIRONMENT +SIM_AC_OPTION_CGEN_MAINT + +# +# Enable making unknown traps dump out registers +# +AC_ARG_ENABLE(sim-trapdump, +[ --enable-sim-trapdump Make unknown traps dump the registers], +[case "${enableval}" in + yes) sim_trapdump="-DTRAPDUMP=1";; + no) sim_trapdump="-DTRAPDUMP=0";; + *) AC_MSG_ERROR("Unknown value $enableval passed to --enable-sim-trapdump"); sim_trapdump="";; +esac +if test x"$silent" != x"yes" && test x"$sim_trapdump" != x""; then + echo "Setting sim_trapdump = $sim_trapdump" 6>&1 +fi],[sim_trapdump=""])dnl +AC_SUBST(sim_trapdump) + +SIM_AC_OUTPUT diff --git a/sim/frv/cpu.c b/sim/frv/cpu.c new file mode 100644 index 0000000..1b4b4a1 --- /dev/null +++ b/sim/frv/cpu.c @@ -0,0 +1,693 @@ +/* Misc. support for CPU family frvbf. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. + +This file is part of the GNU simulators. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +*/ + +#define WANT_CPU frvbf +#define WANT_CPU_FRVBF + +#include "sim-main.h" +#include "cgen-ops.h" + +/* Get the value of h-pc. */ + +USI +frvbf_h_pc_get (SIM_CPU *current_cpu) +{ + return CPU (h_pc); +} + +/* Set a value for h-pc. */ + +void +frvbf_h_pc_set (SIM_CPU *current_cpu, USI newval) +{ + CPU (h_pc) = newval; +} + +/* Get the value of h-psr_imple. */ + +UQI +frvbf_h_psr_imple_get (SIM_CPU *current_cpu) +{ + return CPU (h_psr_imple); +} + +/* Set a value for h-psr_imple. */ + +void +frvbf_h_psr_imple_set (SIM_CPU *current_cpu, UQI newval) +{ + CPU (h_psr_imple) = newval; +} + +/* Get the value of h-psr_ver. */ + +UQI +frvbf_h_psr_ver_get (SIM_CPU *current_cpu) +{ + return CPU (h_psr_ver); +} + +/* Set a value for h-psr_ver. */ + +void +frvbf_h_psr_ver_set (SIM_CPU *current_cpu, UQI newval) +{ + CPU (h_psr_ver) = newval; +} + +/* Get the value of h-psr_ice. */ + +BI +frvbf_h_psr_ice_get (SIM_CPU *current_cpu) +{ + return CPU (h_psr_ice); +} + +/* Set a value for h-psr_ice. */ + +void +frvbf_h_psr_ice_set (SIM_CPU *current_cpu, BI newval) +{ + CPU (h_psr_ice) = newval; +} + +/* Get the value of h-psr_nem. */ + +BI +frvbf_h_psr_nem_get (SIM_CPU *current_cpu) +{ + return CPU (h_psr_nem); +} + +/* Set a value for h-psr_nem. */ + +void +frvbf_h_psr_nem_set (SIM_CPU *current_cpu, BI newval) +{ + CPU (h_psr_nem) = newval; +} + +/* Get the value of h-psr_cm. */ + +BI +frvbf_h_psr_cm_get (SIM_CPU *current_cpu) +{ + return CPU (h_psr_cm); +} + +/* Set a value for h-psr_cm. */ + +void +frvbf_h_psr_cm_set (SIM_CPU *current_cpu, BI newval) +{ + CPU (h_psr_cm) = newval; +} + +/* Get the value of h-psr_be. */ + +BI +frvbf_h_psr_be_get (SIM_CPU *current_cpu) +{ + return CPU (h_psr_be); +} + +/* Set a value for h-psr_be. */ + +void +frvbf_h_psr_be_set (SIM_CPU *current_cpu, BI newval) +{ + CPU (h_psr_be) = newval; +} + +/* Get the value of h-psr_esr. */ + +BI +frvbf_h_psr_esr_get (SIM_CPU *current_cpu) +{ + return CPU (h_psr_esr); +} + +/* Set a value for h-psr_esr. */ + +void +frvbf_h_psr_esr_set (SIM_CPU *current_cpu, BI newval) +{ + CPU (h_psr_esr) = newval; +} + +/* Get the value of h-psr_ef. */ + +BI +frvbf_h_psr_ef_get (SIM_CPU *current_cpu) +{ + return CPU (h_psr_ef); +} + +/* Set a value for h-psr_ef. */ + +void +frvbf_h_psr_ef_set (SIM_CPU *current_cpu, BI newval) +{ + CPU (h_psr_ef) = newval; +} + +/* Get the value of h-psr_em. */ + +BI +frvbf_h_psr_em_get (SIM_CPU *current_cpu) +{ + return CPU (h_psr_em); +} + +/* Set a value for h-psr_em. */ + +void +frvbf_h_psr_em_set (SIM_CPU *current_cpu, BI newval) +{ + CPU (h_psr_em) = newval; +} + +/* Get the value of h-psr_pil. */ + +UQI +frvbf_h_psr_pil_get (SIM_CPU *current_cpu) +{ + return CPU (h_psr_pil); +} + +/* Set a value for h-psr_pil. */ + +void +frvbf_h_psr_pil_set (SIM_CPU *current_cpu, UQI newval) +{ + CPU (h_psr_pil) = newval; +} + +/* Get the value of h-psr_ps. */ + +BI +frvbf_h_psr_ps_get (SIM_CPU *current_cpu) +{ + return CPU (h_psr_ps); +} + +/* Set a value for h-psr_ps. */ + +void +frvbf_h_psr_ps_set (SIM_CPU *current_cpu, BI newval) +{ + CPU (h_psr_ps) = newval; +} + +/* Get the value of h-psr_et. */ + +BI +frvbf_h_psr_et_get (SIM_CPU *current_cpu) +{ + return CPU (h_psr_et); +} + +/* Set a value for h-psr_et. */ + +void +frvbf_h_psr_et_set (SIM_CPU *current_cpu, BI newval) +{ + CPU (h_psr_et) = newval; +} + +/* Get the value of h-psr_s. */ + +BI +frvbf_h_psr_s_get (SIM_CPU *current_cpu) +{ + return CPU (h_psr_s); +} + +/* Set a value for h-psr_s. */ + +void +frvbf_h_psr_s_set (SIM_CPU *current_cpu, BI newval) +{ + SET_H_PSR_S (newval); +} + +/* Get the value of h-tbr_tba. */ + +USI +frvbf_h_tbr_tba_get (SIM_CPU *current_cpu) +{ + return CPU (h_tbr_tba); +} + +/* Set a value for h-tbr_tba. */ + +void +frvbf_h_tbr_tba_set (SIM_CPU *current_cpu, USI newval) +{ + CPU (h_tbr_tba) = newval; +} + +/* Get the value of h-tbr_tt. */ + +UQI +frvbf_h_tbr_tt_get (SIM_CPU *current_cpu) +{ + return CPU (h_tbr_tt); +} + +/* Set a value for h-tbr_tt. */ + +void +frvbf_h_tbr_tt_set (SIM_CPU *current_cpu, UQI newval) +{ + CPU (h_tbr_tt) = newval; +} + +/* Get the value of h-bpsr_bs. */ + +BI +frvbf_h_bpsr_bs_get (SIM_CPU *current_cpu) +{ + return CPU (h_bpsr_bs); +} + +/* Set a value for h-bpsr_bs. */ + +void +frvbf_h_bpsr_bs_set (SIM_CPU *current_cpu, BI newval) +{ + CPU (h_bpsr_bs) = newval; +} + +/* Get the value of h-bpsr_bet. */ + +BI +frvbf_h_bpsr_bet_get (SIM_CPU *current_cpu) +{ + return CPU (h_bpsr_bet); +} + +/* Set a value for h-bpsr_bet. */ + +void +frvbf_h_bpsr_bet_set (SIM_CPU *current_cpu, BI newval) +{ + CPU (h_bpsr_bet) = newval; +} + +/* Get the value of h-gr. */ + +USI +frvbf_h_gr_get (SIM_CPU *current_cpu, UINT regno) +{ + return GET_H_GR (regno); +} + +/* Set a value for h-gr. */ + +void +frvbf_h_gr_set (SIM_CPU *current_cpu, UINT regno, USI newval) +{ + SET_H_GR (regno, newval); +} + +/* Get the value of h-gr_double. */ + +DI +frvbf_h_gr_double_get (SIM_CPU *current_cpu, UINT regno) +{ + return GET_H_GR_DOUBLE (regno); +} + +/* Set a value for h-gr_double. */ + +void +frvbf_h_gr_double_set (SIM_CPU *current_cpu, UINT regno, DI newval) +{ + SET_H_GR_DOUBLE (regno, newval); +} + +/* Get the value of h-gr_hi. */ + +UHI +frvbf_h_gr_hi_get (SIM_CPU *current_cpu, UINT regno) +{ + return GET_H_GR_HI (regno); +} + +/* Set a value for h-gr_hi. */ + +void +frvbf_h_gr_hi_set (SIM_CPU *current_cpu, UINT regno, UHI newval) +{ + SET_H_GR_HI (regno, newval); +} + +/* Get the value of h-gr_lo. */ + +UHI +frvbf_h_gr_lo_get (SIM_CPU *current_cpu, UINT regno) +{ + return GET_H_GR_LO (regno); +} + +/* Set a value for h-gr_lo. */ + +void +frvbf_h_gr_lo_set (SIM_CPU *current_cpu, UINT regno, UHI newval) +{ + SET_H_GR_LO (regno, newval); +} + +/* Get the value of h-fr. */ + +SF +frvbf_h_fr_get (SIM_CPU *current_cpu, UINT regno) +{ + return GET_H_FR (regno); +} + +/* Set a value for h-fr. */ + +void +frvbf_h_fr_set (SIM_CPU *current_cpu, UINT regno, SF newval) +{ + SET_H_FR (regno, newval); +} + +/* Get the value of h-fr_double. */ + +DF +frvbf_h_fr_double_get (SIM_CPU *current_cpu, UINT regno) +{ + return GET_H_FR_DOUBLE (regno); +} + +/* Set a value for h-fr_double. */ + +void +frvbf_h_fr_double_set (SIM_CPU *current_cpu, UINT regno, DF newval) +{ + SET_H_FR_DOUBLE (regno, newval); +} + +/* Get the value of h-fr_int. */ + +USI +frvbf_h_fr_int_get (SIM_CPU *current_cpu, UINT regno) +{ + return GET_H_FR_INT (regno); +} + +/* Set a value for h-fr_int. */ + +void +frvbf_h_fr_int_set (SIM_CPU *current_cpu, UINT regno, USI newval) +{ + SET_H_FR_INT (regno, newval); +} + +/* Get the value of h-fr_hi. */ + +UHI +frvbf_h_fr_hi_get (SIM_CPU *current_cpu, UINT regno) +{ + return GET_H_FR_HI (regno); +} + +/* Set a value for h-fr_hi. */ + +void +frvbf_h_fr_hi_set (SIM_CPU *current_cpu, UINT regno, UHI newval) +{ + SET_H_FR_HI (regno, newval); +} + +/* Get the value of h-fr_lo. */ + +UHI +frvbf_h_fr_lo_get (SIM_CPU *current_cpu, UINT regno) +{ + return GET_H_FR_LO (regno); +} + +/* Set a value for h-fr_lo. */ + +void +frvbf_h_fr_lo_set (SIM_CPU *current_cpu, UINT regno, UHI newval) +{ + SET_H_FR_LO (regno, newval); +} + +/* Get the value of h-fr_0. */ + +UHI +frvbf_h_fr_0_get (SIM_CPU *current_cpu, UINT regno) +{ + return GET_H_FR_0 (regno); +} + +/* Set a value for h-fr_0. */ + +void +frvbf_h_fr_0_set (SIM_CPU *current_cpu, UINT regno, UHI newval) +{ + SET_H_FR_0 (regno, newval); +} + +/* Get the value of h-fr_1. */ + +UHI +frvbf_h_fr_1_get (SIM_CPU *current_cpu, UINT regno) +{ + return GET_H_FR_1 (regno); +} + +/* Set a value for h-fr_1. */ + +void +frvbf_h_fr_1_set (SIM_CPU *current_cpu, UINT regno, UHI newval) +{ + SET_H_FR_1 (regno, newval); +} + +/* Get the value of h-fr_2. */ + +UHI +frvbf_h_fr_2_get (SIM_CPU *current_cpu, UINT regno) +{ + return GET_H_FR_2 (regno); +} + +/* Set a value for h-fr_2. */ + +void +frvbf_h_fr_2_set (SIM_CPU *current_cpu, UINT regno, UHI newval) +{ + SET_H_FR_2 (regno, newval); +} + +/* Get the value of h-fr_3. */ + +UHI +frvbf_h_fr_3_get (SIM_CPU *current_cpu, UINT regno) +{ + return GET_H_FR_3 (regno); +} + +/* Set a value for h-fr_3. */ + +void +frvbf_h_fr_3_set (SIM_CPU *current_cpu, UINT regno, UHI newval) +{ + SET_H_FR_3 (regno, newval); +} + +/* Get the value of h-cpr. */ + +SI +frvbf_h_cpr_get (SIM_CPU *current_cpu, UINT regno) +{ + return CPU (h_cpr[regno]); +} + +/* Set a value for h-cpr. */ + +void +frvbf_h_cpr_set (SIM_CPU *current_cpu, UINT regno, SI newval) +{ + CPU (h_cpr[regno]) = newval; +} + +/* Get the value of h-cpr_double. */ + +DI +frvbf_h_cpr_double_get (SIM_CPU *current_cpu, UINT regno) +{ + return GET_H_CPR_DOUBLE (regno); +} + +/* Set a value for h-cpr_double. */ + +void +frvbf_h_cpr_double_set (SIM_CPU *current_cpu, UINT regno, DI newval) +{ + SET_H_CPR_DOUBLE (regno, newval); +} + +/* Get the value of h-spr. */ + +USI +frvbf_h_spr_get (SIM_CPU *current_cpu, UINT regno) +{ + return GET_H_SPR (regno); +} + +/* Set a value for h-spr. */ + +void +frvbf_h_spr_set (SIM_CPU *current_cpu, UINT regno, USI newval) +{ + SET_H_SPR (regno, newval); +} + +/* Get the value of h-accg. */ + +USI +frvbf_h_accg_get (SIM_CPU *current_cpu, UINT regno) +{ + return GET_H_ACCG (regno); +} + +/* Set a value for h-accg. */ + +void +frvbf_h_accg_set (SIM_CPU *current_cpu, UINT regno, USI newval) +{ + SET_H_ACCG (regno, newval); +} + +/* Get the value of h-acc40S. */ + +DI +frvbf_h_acc40S_get (SIM_CPU *current_cpu, UINT regno) +{ + return GET_H_ACC40S (regno); +} + +/* Set a value for h-acc40S. */ + +void +frvbf_h_acc40S_set (SIM_CPU *current_cpu, UINT regno, DI newval) +{ + SET_H_ACC40S (regno, newval); +} + +/* Get the value of h-acc40U. */ + +UDI +frvbf_h_acc40U_get (SIM_CPU *current_cpu, UINT regno) +{ + return GET_H_ACC40U (regno); +} + +/* Set a value for h-acc40U. */ + +void +frvbf_h_acc40U_set (SIM_CPU *current_cpu, UINT regno, UDI newval) +{ + SET_H_ACC40U (regno, newval); +} + +/* Get the value of h-iacc0. */ + +DI +frvbf_h_iacc0_get (SIM_CPU *current_cpu, UINT regno) +{ + return GET_H_IACC0 (regno); +} + +/* Set a value for h-iacc0. */ + +void +frvbf_h_iacc0_set (SIM_CPU *current_cpu, UINT regno, DI newval) +{ + SET_H_IACC0 (regno, newval); +} + +/* Get the value of h-iccr. */ + +UQI +frvbf_h_iccr_get (SIM_CPU *current_cpu, UINT regno) +{ + return CPU (h_iccr[regno]); +} + +/* Set a value for h-iccr. */ + +void +frvbf_h_iccr_set (SIM_CPU *current_cpu, UINT regno, UQI newval) +{ + CPU (h_iccr[regno]) = newval; +} + +/* Get the value of h-fccr. */ + +UQI +frvbf_h_fccr_get (SIM_CPU *current_cpu, UINT regno) +{ + return CPU (h_fccr[regno]); +} + +/* Set a value for h-fccr. */ + +void +frvbf_h_fccr_set (SIM_CPU *current_cpu, UINT regno, UQI newval) +{ + CPU (h_fccr[regno]) = newval; +} + +/* Get the value of h-cccr. */ + +UQI +frvbf_h_cccr_get (SIM_CPU *current_cpu, UINT regno) +{ + return CPU (h_cccr[regno]); +} + +/* Set a value for h-cccr. */ + +void +frvbf_h_cccr_set (SIM_CPU *current_cpu, UINT regno, UQI newval) +{ + CPU (h_cccr[regno]) = newval; +} + +/* Record trace results for INSN. */ + +void +frvbf_record_trace_results (SIM_CPU *current_cpu, CGEN_INSN *insn, + int *indices, TRACE_RECORD *tr) +{ +} diff --git a/sim/frv/cpu.h b/sim/frv/cpu.h new file mode 100644 index 0000000..6325368 --- /dev/null +++ b/sim/frv/cpu.h @@ -0,0 +1,4328 @@ +/* CPU family header for frvbf. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. + +This file is part of the GNU simulators. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +*/ + +#ifndef CPU_FRVBF_H +#define CPU_FRVBF_H + +/* Maximum number of instructions that are fetched at a time. + This is for LIW type instructions sets (e.g. m32r). */ +#define MAX_LIW_INSNS 1 + +/* Maximum number of instructions that can be executed in parallel. */ +#define MAX_PARALLEL_INSNS 8 + +/* CPU state information. */ +typedef struct { + /* Hardware elements. */ + struct { + /* program counter */ + USI h_pc; +#define GET_H_PC() CPU (h_pc) +#define SET_H_PC(x) (CPU (h_pc) = (x)) + /* PSR.IMPLE */ + UQI h_psr_imple; +#define GET_H_PSR_IMPLE() CPU (h_psr_imple) +#define SET_H_PSR_IMPLE(x) (CPU (h_psr_imple) = (x)) + /* PSR.VER */ + UQI h_psr_ver; +#define GET_H_PSR_VER() CPU (h_psr_ver) +#define SET_H_PSR_VER(x) (CPU (h_psr_ver) = (x)) + /* PSR.ICE bit */ + BI h_psr_ice; +#define GET_H_PSR_ICE() CPU (h_psr_ice) +#define SET_H_PSR_ICE(x) (CPU (h_psr_ice) = (x)) + /* PSR.NEM bit */ + BI h_psr_nem; +#define GET_H_PSR_NEM() CPU (h_psr_nem) +#define SET_H_PSR_NEM(x) (CPU (h_psr_nem) = (x)) + /* PSR.CM bit */ + BI h_psr_cm; +#define GET_H_PSR_CM() CPU (h_psr_cm) +#define SET_H_PSR_CM(x) (CPU (h_psr_cm) = (x)) + /* PSR.BE bit */ + BI h_psr_be; +#define GET_H_PSR_BE() CPU (h_psr_be) +#define SET_H_PSR_BE(x) (CPU (h_psr_be) = (x)) + /* PSR.ESR bit */ + BI h_psr_esr; +#define GET_H_PSR_ESR() CPU (h_psr_esr) +#define SET_H_PSR_ESR(x) (CPU (h_psr_esr) = (x)) + /* PSR.EF bit */ + BI h_psr_ef; +#define GET_H_PSR_EF() CPU (h_psr_ef) +#define SET_H_PSR_EF(x) (CPU (h_psr_ef) = (x)) + /* PSR.EM bit */ + BI h_psr_em; +#define GET_H_PSR_EM() CPU (h_psr_em) +#define SET_H_PSR_EM(x) (CPU (h_psr_em) = (x)) + /* PSR.PIL */ + UQI h_psr_pil; +#define GET_H_PSR_PIL() CPU (h_psr_pil) +#define SET_H_PSR_PIL(x) (CPU (h_psr_pil) = (x)) + /* PSR.PS bit */ + BI h_psr_ps; +#define GET_H_PSR_PS() CPU (h_psr_ps) +#define SET_H_PSR_PS(x) (CPU (h_psr_ps) = (x)) + /* PSR.ET bit */ + BI h_psr_et; +#define GET_H_PSR_ET() CPU (h_psr_et) +#define SET_H_PSR_ET(x) (CPU (h_psr_et) = (x)) + /* PSR.S bit */ + BI h_psr_s; +#define GET_H_PSR_S() CPU (h_psr_s) +#define SET_H_PSR_S(x) \ +do { \ +frvbf_h_psr_s_set_handler (current_cpu, (x));\ +;} while (0) + /* TBR.TBA */ + USI h_tbr_tba; +#define GET_H_TBR_TBA() CPU (h_tbr_tba) +#define SET_H_TBR_TBA(x) (CPU (h_tbr_tba) = (x)) + /* TBR.TT */ + UQI h_tbr_tt; +#define GET_H_TBR_TT() CPU (h_tbr_tt) +#define SET_H_TBR_TT(x) (CPU (h_tbr_tt) = (x)) + /* PSR.S bit */ + BI h_bpsr_bs; +#define GET_H_BPSR_BS() CPU (h_bpsr_bs) +#define SET_H_BPSR_BS(x) (CPU (h_bpsr_bs) = (x)) + /* PSR.ET bit */ + BI h_bpsr_bet; +#define GET_H_BPSR_BET() CPU (h_bpsr_bet) +#define SET_H_BPSR_BET(x) (CPU (h_bpsr_bet) = (x)) + /* general registers */ + USI h_gr[64]; +#define GET_H_GR(index) frvbf_h_gr_get_handler (current_cpu, index) +#define SET_H_GR(index, x) \ +do { \ +frvbf_h_gr_set_handler (current_cpu, (index), (x));\ +;} while (0) + /* floating point registers */ + SF h_fr[64]; +#define GET_H_FR(index) frvbf_h_fr_get_handler (current_cpu, index) +#define SET_H_FR(index, x) \ +do { \ +frvbf_h_fr_set_handler (current_cpu, (index), (x));\ +;} while (0) + /* coprocessor registers */ + SI h_cpr[64]; +#define GET_H_CPR(a1) CPU (h_cpr)[a1] +#define SET_H_CPR(a1, x) (CPU (h_cpr)[a1] = (x)) + /* special purpose registers */ + USI h_spr[4096]; +#define GET_H_SPR(index) frvbf_h_spr_get_handler (current_cpu, index) +#define SET_H_SPR(index, x) \ +do { \ +frvbf_h_spr_set_handler (current_cpu, (index), (x));\ +;} while (0) + /* Integer condition code registers */ + UQI h_iccr[4]; +#define GET_H_ICCR(a1) CPU (h_iccr)[a1] +#define SET_H_ICCR(a1, x) (CPU (h_iccr)[a1] = (x)) + /* Floating point condition code registers */ + UQI h_fccr[4]; +#define GET_H_FCCR(a1) CPU (h_fccr)[a1] +#define SET_H_FCCR(a1, x) (CPU (h_fccr)[a1] = (x)) + /* Condition code registers */ + UQI h_cccr[8]; +#define GET_H_CCCR(a1) CPU (h_cccr)[a1] +#define SET_H_CCCR(a1, x) (CPU (h_cccr)[a1] = (x)) + } hardware; +#define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware) +} FRVBF_CPU_DATA; + +/* Virtual regs. */ + +#define GET_H_GR_DOUBLE(index) frvbf_h_gr_double_get_handler (current_cpu, index) +#define SET_H_GR_DOUBLE(index, x) \ +do { \ +frvbf_h_gr_double_set_handler (current_cpu, (index), (x));\ +;} while (0) +#define GET_H_GR_HI(index) frvbf_h_gr_hi_get_handler (current_cpu, index) +#define SET_H_GR_HI(index, x) \ +do { \ +frvbf_h_gr_hi_set_handler (current_cpu, (index), (x));\ +;} while (0) +#define GET_H_GR_LO(index) frvbf_h_gr_lo_get_handler (current_cpu, index) +#define SET_H_GR_LO(index, x) \ +do { \ +frvbf_h_gr_lo_set_handler (current_cpu, (index), (x));\ +;} while (0) +#define GET_H_FR_DOUBLE(index) frvbf_h_fr_double_get_handler (current_cpu, index) +#define SET_H_FR_DOUBLE(index, x) \ +do { \ +frvbf_h_fr_double_set_handler (current_cpu, (index), (x));\ +;} while (0) +#define GET_H_FR_INT(index) frvbf_h_fr_int_get_handler (current_cpu, index) +#define SET_H_FR_INT(index, x) \ +do { \ +frvbf_h_fr_int_set_handler (current_cpu, (index), (x));\ +;} while (0) +#define GET_H_FR_HI(index) SRLSI (GET_H_FR_INT (index), 16) +#define SET_H_FR_HI(index, x) \ +do { \ +SET_H_FR_INT ((index), ORSI (ANDSI (GET_H_FR_INT ((index)), 65535), SLLHI ((x), 16)));\ +;} while (0) +#define GET_H_FR_LO(index) ANDSI (GET_H_FR_INT (index), 65535) +#define SET_H_FR_LO(index, x) \ +do { \ +SET_H_FR_INT ((index), ORSI (ANDSI (GET_H_FR_INT ((index)), 0xffff0000), ANDHI ((x), 65535)));\ +;} while (0) +#define GET_H_FR_0(index) ANDSI (GET_H_FR_INT (index), 255) +#define SET_H_FR_0(index, x) \ +do { \ +{\ +if (GTSI ((x), 255)) {\ + (x) = 255;\ +}\ +SET_H_FR_INT ((index), ORSI (ANDSI (GET_H_FR_INT ((index)), 0xffffff00), (x)));\ +}\ +;} while (0) +#define GET_H_FR_1(index) ANDSI (SRLSI (GET_H_FR_INT (index), 8), 255) +#define SET_H_FR_1(index, x) \ +do { \ +{\ +if (GTSI ((x), 255)) {\ + (x) = 255;\ +}\ +SET_H_FR_INT ((index), ORSI (ANDSI (GET_H_FR_INT ((index)), 0xffff00ff), SLLHI ((x), 8)));\ +}\ +;} while (0) +#define GET_H_FR_2(index) ANDSI (SRLSI (GET_H_FR_INT (index), 16), 255) +#define SET_H_FR_2(index, x) \ +do { \ +{\ +if (GTSI ((x), 255)) {\ + (x) = 255;\ +}\ +SET_H_FR_INT ((index), ORSI (ANDSI (GET_H_FR_INT ((index)), 0xff00ffff), SLLHI ((x), 16)));\ +}\ +;} while (0) +#define GET_H_FR_3(index) ANDSI (SRLSI (GET_H_FR_INT (index), 24), 255) +#define SET_H_FR_3(index, x) \ +do { \ +{\ +if (GTSI ((x), 255)) {\ + (x) = 255;\ +}\ +SET_H_FR_INT ((index), ORSI (ANDSI (GET_H_FR_INT ((index)), 16777215), SLLHI ((x), 24)));\ +}\ +;} while (0) +#define GET_H_CPR_DOUBLE(index) frvbf_h_cpr_double_get_handler (current_cpu, index) +#define SET_H_CPR_DOUBLE(index, x) \ +do { \ +frvbf_h_cpr_double_set_handler (current_cpu, (index), (x));\ +;} while (0) +#define GET_H_ACCG(index) ANDSI (GET_H_SPR (((index) + (1472))), 255) +#define SET_H_ACCG(index, x) \ +do { \ +CPU (h_spr[(((index)) + (1472))]) = ANDSI ((x), 255);\ +;} while (0) +#define GET_H_ACC40S(index) ORDI (SLLDI (EXTQIDI (TRUNCSIQI (GET_H_SPR (((index) + (1472))))), 32), ZEXTSIDI (GET_H_SPR (((index) + (1408))))) +#define SET_H_ACC40S(index, x) \ +do { \ +{\ +frv_check_spr_write_access (current_cpu, (((index)) + (1408)));\ +CPU (h_spr[(((index)) + (1472))]) = ANDDI (SRLDI ((x), 32), 255);\ +CPU (h_spr[(((index)) + (1408))]) = TRUNCDISI ((x));\ +}\ +;} while (0) +#define GET_H_ACC40U(index) ORDI (SLLDI (ZEXTSIDI (GET_H_SPR (((index) + (1472)))), 32), ZEXTSIDI (GET_H_SPR (((index) + (1408))))) +#define SET_H_ACC40U(index, x) \ +do { \ +{\ +frv_check_spr_write_access (current_cpu, (((index)) + (1408)));\ +CPU (h_spr[(((index)) + (1472))]) = ANDDI (SRLDI ((x), 32), 255);\ +CPU (h_spr[(((index)) + (1408))]) = TRUNCDISI ((x));\ +}\ +;} while (0) +#define GET_H_IACC0(index) ORDI (SLLDI (EXTSIDI (GET_H_SPR (((UINT) 280))), 32), ZEXTSIDI (GET_H_SPR (((UINT) 281)))) +#define SET_H_IACC0(index, x) \ +do { \ +{\ +SET_H_SPR (((UINT) 280), TRUNCDISI (SRLDI ((x), 32)));\ +SET_H_SPR (((UINT) 281), TRUNCDISI ((x)));\ +}\ +;} while (0) + +/* Cover fns for register access. */ +USI frvbf_h_pc_get (SIM_CPU *); +void frvbf_h_pc_set (SIM_CPU *, USI); +UQI frvbf_h_psr_imple_get (SIM_CPU *); +void frvbf_h_psr_imple_set (SIM_CPU *, UQI); +UQI frvbf_h_psr_ver_get (SIM_CPU *); +void frvbf_h_psr_ver_set (SIM_CPU *, UQI); +BI frvbf_h_psr_ice_get (SIM_CPU *); +void frvbf_h_psr_ice_set (SIM_CPU *, BI); +BI frvbf_h_psr_nem_get (SIM_CPU *); +void frvbf_h_psr_nem_set (SIM_CPU *, BI); +BI frvbf_h_psr_cm_get (SIM_CPU *); +void frvbf_h_psr_cm_set (SIM_CPU *, BI); +BI frvbf_h_psr_be_get (SIM_CPU *); +void frvbf_h_psr_be_set (SIM_CPU *, BI); +BI frvbf_h_psr_esr_get (SIM_CPU *); +void frvbf_h_psr_esr_set (SIM_CPU *, BI); +BI frvbf_h_psr_ef_get (SIM_CPU *); +void frvbf_h_psr_ef_set (SIM_CPU *, BI); +BI frvbf_h_psr_em_get (SIM_CPU *); +void frvbf_h_psr_em_set (SIM_CPU *, BI); +UQI frvbf_h_psr_pil_get (SIM_CPU *); +void frvbf_h_psr_pil_set (SIM_CPU *, UQI); +BI frvbf_h_psr_ps_get (SIM_CPU *); +void frvbf_h_psr_ps_set (SIM_CPU *, BI); +BI frvbf_h_psr_et_get (SIM_CPU *); +void frvbf_h_psr_et_set (SIM_CPU *, BI); +BI frvbf_h_psr_s_get (SIM_CPU *); +void frvbf_h_psr_s_set (SIM_CPU *, BI); +USI frvbf_h_tbr_tba_get (SIM_CPU *); +void frvbf_h_tbr_tba_set (SIM_CPU *, USI); +UQI frvbf_h_tbr_tt_get (SIM_CPU *); +void frvbf_h_tbr_tt_set (SIM_CPU *, UQI); +BI frvbf_h_bpsr_bs_get (SIM_CPU *); +void frvbf_h_bpsr_bs_set (SIM_CPU *, BI); +BI frvbf_h_bpsr_bet_get (SIM_CPU *); +void frvbf_h_bpsr_bet_set (SIM_CPU *, BI); +USI frvbf_h_gr_get (SIM_CPU *, UINT); +void frvbf_h_gr_set (SIM_CPU *, UINT, USI); +DI frvbf_h_gr_double_get (SIM_CPU *, UINT); +void frvbf_h_gr_double_set (SIM_CPU *, UINT, DI); +UHI frvbf_h_gr_hi_get (SIM_CPU *, UINT); +void frvbf_h_gr_hi_set (SIM_CPU *, UINT, UHI); +UHI frvbf_h_gr_lo_get (SIM_CPU *, UINT); +void frvbf_h_gr_lo_set (SIM_CPU *, UINT, UHI); +SF frvbf_h_fr_get (SIM_CPU *, UINT); +void frvbf_h_fr_set (SIM_CPU *, UINT, SF); +DF frvbf_h_fr_double_get (SIM_CPU *, UINT); +void frvbf_h_fr_double_set (SIM_CPU *, UINT, DF); +USI frvbf_h_fr_int_get (SIM_CPU *, UINT); +void frvbf_h_fr_int_set (SIM_CPU *, UINT, USI); +UHI frvbf_h_fr_hi_get (SIM_CPU *, UINT); +void frvbf_h_fr_hi_set (SIM_CPU *, UINT, UHI); +UHI frvbf_h_fr_lo_get (SIM_CPU *, UINT); +void frvbf_h_fr_lo_set (SIM_CPU *, UINT, UHI); +UHI frvbf_h_fr_0_get (SIM_CPU *, UINT); +void frvbf_h_fr_0_set (SIM_CPU *, UINT, UHI); +UHI frvbf_h_fr_1_get (SIM_CPU *, UINT); +void frvbf_h_fr_1_set (SIM_CPU *, UINT, UHI); +UHI frvbf_h_fr_2_get (SIM_CPU *, UINT); +void frvbf_h_fr_2_set (SIM_CPU *, UINT, UHI); +UHI frvbf_h_fr_3_get (SIM_CPU *, UINT); +void frvbf_h_fr_3_set (SIM_CPU *, UINT, UHI); +SI frvbf_h_cpr_get (SIM_CPU *, UINT); +void frvbf_h_cpr_set (SIM_CPU *, UINT, SI); +DI frvbf_h_cpr_double_get (SIM_CPU *, UINT); +void frvbf_h_cpr_double_set (SIM_CPU *, UINT, DI); +USI frvbf_h_spr_get (SIM_CPU *, UINT); +void frvbf_h_spr_set (SIM_CPU *, UINT, USI); +USI frvbf_h_accg_get (SIM_CPU *, UINT); +void frvbf_h_accg_set (SIM_CPU *, UINT, USI); +DI frvbf_h_acc40S_get (SIM_CPU *, UINT); +void frvbf_h_acc40S_set (SIM_CPU *, UINT, DI); +UDI frvbf_h_acc40U_get (SIM_CPU *, UINT); +void frvbf_h_acc40U_set (SIM_CPU *, UINT, UDI); +DI frvbf_h_iacc0_get (SIM_CPU *, UINT); +void frvbf_h_iacc0_set (SIM_CPU *, UINT, DI); +UQI frvbf_h_iccr_get (SIM_CPU *, UINT); +void frvbf_h_iccr_set (SIM_CPU *, UINT, UQI); +UQI frvbf_h_fccr_get (SIM_CPU *, UINT); +void frvbf_h_fccr_set (SIM_CPU *, UINT, UQI); +UQI frvbf_h_cccr_get (SIM_CPU *, UINT); +void frvbf_h_cccr_set (SIM_CPU *, UINT, UQI); + +/* These must be hand-written. */ +extern CPUREG_FETCH_FN frvbf_fetch_register; +extern CPUREG_STORE_FN frvbf_store_register; + +typedef struct { + int empty; +} MODEL_FRV_DATA; + +typedef struct { + DI prev_fr_load; + DI prev_fr_complex_1; + DI prev_fr_complex_2; + DI prev_ccr_complex; + DI prev_acc_mmac; + DI cur_fr_load; + DI cur_fr_complex_1; + DI cur_fr_complex_2; + SI cur_ccr_complex; + DI cur_acc_mmac; +} MODEL_FR550_DATA; + +typedef struct { + DI prev_fpop; + DI prev_media; + DI prev_cc_complex; + DI cur_fpop; + DI cur_media; + DI cur_cc_complex; +} MODEL_FR500_DATA; + +typedef struct { + int empty; +} MODEL_TOMCAT_DATA; + +typedef struct { + DI prev_fp_load; + DI prev_fr_p4; + DI prev_fr_p6; + DI prev_acc_p2; + DI prev_acc_p4; + DI cur_fp_load; + DI cur_fr_p4; + DI cur_fr_p6; + DI cur_acc_p2; + DI cur_acc_p4; +} MODEL_FR400_DATA; + +typedef struct { + int empty; +} MODEL_SIMPLE_DATA; + +/* Instruction argument buffer. */ + +union sem_fields { + struct { /* no operands */ + int empty; + } fmt_empty; + struct { /* */ + unsigned short out_h_spr_USI_2; + } sfmt_break; + struct { /* */ + UINT f_debug; + } sfmt_rett; + struct { /* */ + IADDR i_label24; + } sfmt_call; + struct { /* */ + INT f_u12; + UINT f_FRk; + unsigned char out_FRkhi; + } sfmt_mhsethis; + struct { /* */ + INT f_u12; + UINT f_FRk; + unsigned char out_FRklo; + } sfmt_mhsetlos; + struct { /* */ + INT f_s16; + UINT f_GRk; + unsigned char out_GRk; + } sfmt_setlos; + struct { /* */ + UINT f_GRk; + UINT f_u16; + unsigned char out_GRkhi; + } sfmt_sethi; + struct { /* */ + UINT f_GRk; + UINT f_u16; + unsigned char out_GRklo; + } sfmt_setlo; + struct { /* */ + UINT f_ACCGi; + UINT f_FRk; + unsigned char in_ACCGi; + unsigned char out_FRintk; + } sfmt_mrdaccg; + struct { /* */ + INT f_s5; + UINT f_FRk; + unsigned char in_FRkhi; + unsigned char out_FRkhi; + } sfmt_mhsethih; + struct { /* */ + INT f_s5; + UINT f_FRk; + unsigned char in_FRklo; + unsigned char out_FRklo; + } sfmt_mhsetloh; + struct { /* */ + UINT f_FRj; + UINT f_FRk; + unsigned char in_FRdoublej; + unsigned char out_FRintk; + } sfmt_fdtoi; + struct { /* */ + UINT f_FRj; + UINT f_FRk; + unsigned char in_FRintj; + unsigned char out_FRdoublek; + } sfmt_fitod; + struct { /* */ + INT f_d12; + UINT f_GRi; + UINT f_LI; + unsigned char in_GRi; + } sfmt_jmpil; + struct { /* */ + IADDR i_label16; + UINT f_FCCi_2; + UINT f_hint; + unsigned char in_FCCi_2; + } sfmt_fbne; + struct { /* */ + IADDR i_label16; + UINT f_ICCi_2; + UINT f_hint; + unsigned char in_ICCi_2; + } sfmt_beq; + struct { /* */ + UINT f_GRj; + UINT f_spr; + unsigned short in_spr; + unsigned char out_GRj; + } sfmt_movsg; + struct { /* */ + UINT f_GRj; + UINT f_spr; + unsigned short out_spr; + unsigned char in_GRj; + } sfmt_movgs; + struct { /* */ + UINT f_ACCGk; + UINT f_FRi; + unsigned char in_ACCGk; + unsigned char in_FRinti; + unsigned char out_ACCGk; + } sfmt_mwtaccg; + struct { /* */ + INT f_s6; + UINT f_ACC40Si; + UINT f_FRk; + unsigned char in_ACC40Si; + unsigned char out_FRintk; + } sfmt_mcuti; + struct { /* */ + UINT f_GRi; + UINT f_GRj; + UINT f_lock; + unsigned char in_GRi; + unsigned char in_GRj; + } sfmt_icpl; + struct { /* */ + UINT f_GRi; + UINT f_GRj; + UINT f_ae; + unsigned char in_GRi; + unsigned char in_GRj; + } sfmt_icei; + struct { /* */ + INT f_d12; + UINT f_FRk; + UINT f_GRi; + unsigned char in_FRdoublek; + unsigned char in_GRi; + } sfmt_stdfi; + struct { /* */ + INT f_d12; + UINT f_GRi; + UINT f_GRk; + unsigned char in_GRdoublek; + unsigned char in_GRi; + } sfmt_stdi; + struct { /* */ + INT f_d12; + UINT f_FRk; + UINT f_GRi; + unsigned char in_FRintk; + unsigned char in_GRi; + } sfmt_stbfi; + struct { /* */ + INT f_d12; + UINT f_FRk; + UINT f_GRi; + unsigned char in_GRi; + unsigned char out_FRdoublek; + } sfmt_lddfi; + struct { /* */ + INT f_d12; + UINT f_FRk; + UINT f_GRi; + unsigned char in_GRi; + unsigned char out_FRintk; + } sfmt_ldbfi; + struct { /* */ + INT f_d12; + UINT f_GRi; + UINT f_GRk; + unsigned char in_GRi; + unsigned char out_GRdoublek; + } sfmt_smuli; + struct { /* */ + UINT f_GRj; + UINT f_GRk; + unsigned char in_GRj; + unsigned char in_h_iacc0_DI_0; + unsigned char out_GRk; + } sfmt_scutss; + struct { /* */ + UINT f_ACC40Si; + UINT f_FRj; + UINT f_FRk; + unsigned char in_ACC40Si; + unsigned char in_FRintj; + unsigned char out_FRintk; + } sfmt_mcut; + struct { /* */ + UINT f_FRi; + UINT f_FRk; + UINT f_u6; + unsigned char in_FRinti; + unsigned char in_h_fr_int_USI_add__DFLT_index_of__DFLT_FRinti_1; + unsigned char out_FRintk; + } sfmt_mwcuti; + struct { /* */ + INT f_u12; + UINT f_FRk; + unsigned char in_FRintk; + unsigned char out_FRintk; + unsigned char out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintk_0; + unsigned char out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintk_0; + } sfmt_mhdsets; + struct { /* */ + UINT f_FCCi_2; + UINT f_FRi; + UINT f_FRj; + unsigned char in_FRdoublei; + unsigned char in_FRdoublej; + unsigned char out_FCCi_2; + } sfmt_fcmpd; + struct { /* */ + UINT f_FRj; + UINT f_FRk; + unsigned char in_FRj; + unsigned char in_h_fr_SF_add__DFLT_index_of__DFLT_FRj_1; + unsigned char out_FRintk; + unsigned char out_h_fr_int_USI_add__DFLT_index_of__DFLT_FRintk_1; + } sfmt_fdstoi; + struct { /* */ + UINT f_FRj; + UINT f_FRk; + unsigned char in_FRintj; + unsigned char in_h_fr_int_USI_add__DFLT_index_of__DFLT_FRintj_1; + unsigned char out_FRk; + unsigned char out_h_fr_SF_add__DFLT_index_of__DFLT_FRk_1; + } sfmt_fditos; + struct { /* */ + UINT f_CRi; + UINT f_CRj; + UINT f_CRk; + unsigned char in_CRi; + unsigned char in_CRj; + unsigned char out_CRk; + } sfmt_andcr; + struct { /* */ + INT f_d12; + UINT f_GRi; + UINT f_GRk; + unsigned char in_GRi; + unsigned char in_GRk; + unsigned char out_GRk; + } sfmt_swapi; + struct { /* */ + UINT f_GRi; + UINT f_GRj; + unsigned char in_GRi; + unsigned char in_GRj; + unsigned char in_h_iacc0_DI_0; + unsigned char out_h_iacc0_DI_0; + } sfmt_smass; + struct { /* */ + INT f_s6; + UINT f_FRi; + UINT f_FRk; + unsigned char in_FRintieven; + unsigned char in_h_fr_int_USI_add__DFLT_index_of__DFLT_FRintieven_1; + unsigned char out_FRintkeven; + unsigned char out_h_fr_int_USI_add__DFLT_index_of__DFLT_FRintkeven_1; + } sfmt_mdrotli; + struct { /* */ + INT f_s6; + UINT f_ACC40Si; + UINT f_FRk; + unsigned char in_ACC40Si; + unsigned char in_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Si_1; + unsigned char out_FRintkeven; + unsigned char out_h_fr_int_USI_add__DFLT_index_of__DFLT_FRintkeven_1; + } sfmt_mdcutssi; + struct { /* */ + UINT f_FRi; + UINT f_FRj; + UINT f_FRk; + unsigned char in_FRinti; + unsigned char in_FRintj; + unsigned char in_h_fr_int_USI_add__DFLT_index_of__DFLT_FRinti_1; + unsigned char out_FRintk; + } sfmt_mwcut; + struct { /* */ + UINT f_FRi; + UINT f_FRj; + UINT f_FRk; + unsigned char in_FRdoublei; + unsigned char in_FRdoublej; + unsigned char in_FRdoublek; + unsigned char out_FRdoublek; + } sfmt_fmaddd; + struct { /* */ + UINT f_CCi; + UINT f_FRj; + UINT f_FRk; + UINT f_cond; + unsigned char in_CCi; + unsigned char in_FRj; + unsigned char out_FRintk; + } sfmt_cfstoi; + struct { /* */ + UINT f_CCi; + UINT f_FRj; + UINT f_FRk; + UINT f_cond; + unsigned char in_CCi; + unsigned char in_FRintj; + unsigned char out_FRk; + } sfmt_cfitos; + struct { /* */ + UINT f_CCi; + UINT f_CRj_float; + UINT f_FCCi_3; + UINT f_cond; + unsigned char in_CCi; + unsigned char in_FCCi_3; + unsigned char out_CRj_float; + } sfmt_cfckne; + struct { /* */ + SI f_CRj_int; + UINT f_CCi; + UINT f_ICCi_3; + UINT f_cond; + unsigned char in_CCi; + unsigned char in_ICCi_3; + unsigned char out_CRj_int; + } sfmt_cckeq; + struct { /* */ + UINT f_FCCi_2; + UINT f_ccond; + UINT f_hint; + unsigned short in_h_spr_USI_272; + unsigned short in_h_spr_USI_273; + unsigned short out_h_spr_USI_273; + unsigned char in_FCCi_2; + } sfmt_fcbeqlr; + struct { /* */ + UINT f_ICCi_2; + UINT f_ccond; + UINT f_hint; + unsigned short in_h_spr_USI_272; + unsigned short in_h_spr_USI_273; + unsigned short out_h_spr_USI_273; + unsigned char in_ICCi_2; + } sfmt_bceqlr; + struct { /* */ + UINT f_CPRk; + UINT f_GRi; + UINT f_GRj; + unsigned char in_CPRdoublek; + unsigned char in_GRi; + unsigned char in_GRj; + unsigned char out_GRi; + } sfmt_stdcu; + struct { /* */ + UINT f_CPRk; + UINT f_GRi; + UINT f_GRj; + unsigned char in_CPRk; + unsigned char in_GRi; + unsigned char in_GRj; + unsigned char out_GRi; + } sfmt_stcu; + struct { /* */ + UINT f_CPRk; + UINT f_GRi; + UINT f_GRj; + unsigned char in_GRi; + unsigned char in_GRj; + unsigned char out_CPRdoublek; + unsigned char out_GRi; + } sfmt_lddcu; + struct { /* */ + UINT f_CPRk; + UINT f_GRi; + UINT f_GRj; + unsigned char in_GRi; + unsigned char in_GRj; + unsigned char out_CPRk; + unsigned char out_GRi; + } sfmt_ldcu; + struct { /* */ + INT f_s5; + UINT f_FRk; + unsigned char in_FRintk; + unsigned char in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintk_0; + unsigned char in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintk_0; + unsigned char out_FRintk; + unsigned char out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintk_0; + unsigned char out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintk_0; + } sfmt_mhdseth; + struct { /* */ + UINT f_CCi; + UINT f_GRi; + UINT f_GRj; + UINT f_LI; + UINT f_cond; + unsigned char in_CCi; + unsigned char in_GRi; + unsigned char in_GRj; + } sfmt_cjmpl; + struct { /* */ + INT f_s10; + UINT f_GRi; + UINT f_GRk; + UINT f_ICCi_1; + unsigned char in_GRi; + unsigned char in_ICCi_1; + unsigned char out_GRdoublek; + unsigned char out_ICCi_1; + } sfmt_smulicc; + struct { /* */ + INT f_s10; + UINT f_GRi; + UINT f_GRk; + UINT f_ICCi_1; + unsigned char in_GRi; + unsigned char in_ICCi_1; + unsigned char out_GRk; + unsigned char out_ICCi_1; + } sfmt_addicc; + struct { /* */ + UINT f_CCi; + UINT f_FRi; + UINT f_FRj; + UINT f_FRk; + UINT f_cond; + unsigned char in_CCi; + unsigned char in_FRinti; + unsigned char in_FRintj; + unsigned char out_FRintk; + } sfmt_cmand; + struct { /* */ + UINT f_CCi; + UINT f_FCCi_2; + UINT f_FRi; + UINT f_FRj; + UINT f_cond; + unsigned char in_CCi; + unsigned char in_FRi; + unsigned char in_FRj; + unsigned char out_FCCi_2; + } sfmt_cfcmps; + struct { /* */ + UINT f_CCi; + UINT f_FRk; + UINT f_GRj; + UINT f_cond; + unsigned char in_CCi; + unsigned char in_FRintk; + unsigned char in_h_fr_int_USI_add__DFLT_index_of__DFLT_FRintk_1; + unsigned char out_GRj; + unsigned char out_h_gr_USI_add__DFLT_index_of__DFLT_GRj_1; + } sfmt_cmovfgd; + struct { /* */ + UINT f_CCi; + UINT f_FRk; + UINT f_GRj; + UINT f_cond; + unsigned char in_CCi; + unsigned char in_GRj; + unsigned char in_h_gr_USI_add__DFLT_index_of__DFLT_GRj_1; + unsigned char out_FRintk; + unsigned char out_h_fr_int_USI_add__DFLT_index_of__DFLT_FRintk_1; + } sfmt_cmovgfd; + struct { /* */ + UINT f_GRi; + UINT f_GRj; + UINT f_GRk; + UINT f_ICCi_1; + unsigned char in_GRi; + unsigned char in_GRj; + unsigned char in_ICCi_1; + unsigned char out_GRdoublek; + unsigned char out_ICCi_1; + } sfmt_smulcc; + struct { /* */ + UINT f_GRi; + UINT f_GRj; + UINT f_GRk; + UINT f_ICCi_1; + unsigned char in_GRi; + unsigned char in_GRj; + unsigned char in_ICCi_1; + unsigned char out_GRk; + unsigned char out_ICCi_1; + } sfmt_addcc; + struct { /* */ + UINT f_CCi; + UINT f_FRi; + UINT f_FRk; + UINT f_cond; + UINT f_u6; + unsigned char in_CCi; + unsigned char in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRinti_0; + unsigned char in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRinti_0; + unsigned char out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintk_0; + unsigned char out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintk_0; + } sfmt_cmexpdhw; + struct { /* */ + UINT f_ACC40Si; + UINT f_ACC40Sk; + unsigned char in_ACC40Si; + unsigned char in_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Si_1; + unsigned char in_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Si_2; + unsigned char in_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Si_3; + unsigned char out_ACC40Sk; + unsigned char out_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Sk_1; + unsigned char out_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Sk_2; + unsigned char out_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Sk_3; + } sfmt_mdasaccs; + struct { /* */ + UINT f_FRj; + UINT f_FRk; + unsigned char in_FRintj; + unsigned char in_FRintk; + unsigned char in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintj_0; + unsigned char in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintj_0; + unsigned char out_FRintj; + unsigned char out_FRintk; + unsigned char out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintk_0; + unsigned char out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintk_0; + } sfmt_mabshs; + struct { /* */ + UINT f_FRi; + UINT f_FRk; + UINT f_u6; + unsigned char in_FRinti; + unsigned char in_FRintk; + unsigned char in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRinti_0; + unsigned char in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRinti_1; + unsigned char out_FRinti; + unsigned char out_FRintk; + unsigned char out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintk_0; + } sfmt_mcplhi; + struct { /* */ + UINT f_FCCi_2; + UINT f_FRi; + UINT f_FRj; + UINT f_FRk; + unsigned char in_FRi; + unsigned char in_FRj; + unsigned char in_h_fr_SF_add__DFLT_index_of__DFLT_FRi_1; + unsigned char in_h_fr_SF_add__DFLT_index_of__DFLT_FRj_1; + unsigned char out_FCCi_2; + unsigned char out_h_fccr_UQI_add__DFLT_index_of__DFLT_FCCi_2_1; + } sfmt_nfdcmps; + struct { /* */ + UINT f_CCi; + UINT f_FRi; + UINT f_FRj; + UINT f_FRk; + UINT f_cond; + unsigned char in_CCi; + unsigned char in_FRi; + unsigned char in_FRj; + unsigned char in_FRk; + unsigned char out_FRk; + } sfmt_cfmadds; + struct { /* */ + INT f_d12; + UINT f_FCCi_2; + UINT f_GRi; + unsigned short out_h_spr_USI_1; + unsigned short out_h_spr_USI_768; + unsigned short out_h_spr_USI_769; + unsigned short out_h_spr_USI_770; + unsigned short out_h_spr_USI_771; + unsigned char in_FCCi_2; + unsigned char in_GRi; + } sfmt_ftine; + struct { /* */ + INT f_d12; + UINT f_GRi; + UINT f_ICCi_2; + unsigned short out_h_spr_USI_1; + unsigned short out_h_spr_USI_768; + unsigned short out_h_spr_USI_769; + unsigned short out_h_spr_USI_770; + unsigned short out_h_spr_USI_771; + unsigned char in_GRi; + unsigned char in_ICCi_2; + } sfmt_tieq; + struct { /* */ + UINT f_FRk; + UINT f_GRj; + unsigned char in_FRintk; + unsigned char in_h_fr_int_USI_add__DFLT_index_of__DFLT_FRintk_1; + unsigned char in_h_fr_int_USI_add__DFLT_index_of__DFLT_FRintk_2; + unsigned char in_h_fr_int_USI_add__DFLT_index_of__DFLT_FRintk_3; + unsigned char out_GRj; + unsigned char out_h_gr_USI_add__DFLT_index_of__DFLT_GRj_1; + unsigned char out_h_gr_USI_add__DFLT_index_of__DFLT_GRj_2; + unsigned char out_h_gr_USI_add__DFLT_index_of__DFLT_GRj_3; + } sfmt_movfgq; + struct { /* */ + UINT f_FRk; + UINT f_GRj; + unsigned char in_GRj; + unsigned char in_h_gr_USI_add__DFLT_index_of__DFLT_GRj_1; + unsigned char in_h_gr_USI_add__DFLT_index_of__DFLT_GRj_2; + unsigned char in_h_gr_USI_add__DFLT_index_of__DFLT_GRj_3; + unsigned char out_FRintk; + unsigned char out_h_fr_int_USI_add__DFLT_index_of__DFLT_FRintk_1; + unsigned char out_h_fr_int_USI_add__DFLT_index_of__DFLT_FRintk_2; + unsigned char out_h_fr_int_USI_add__DFLT_index_of__DFLT_FRintk_3; + } sfmt_movgfq; + struct { /* */ + UINT f_CCi; + UINT f_GRi; + UINT f_GRj; + UINT f_GRk; + UINT f_cond; + unsigned char in_CCi; + unsigned char in_GRi; + unsigned char in_GRj; + unsigned char in_GRk; + unsigned char out_GRk; + } sfmt_cswap; + struct { /* */ + UINT f_CCi; + UINT f_FRk; + UINT f_GRi; + UINT f_GRj; + UINT f_cond; + unsigned char in_CCi; + unsigned char in_FRdoublek; + unsigned char in_GRi; + unsigned char in_GRj; + unsigned char out_GRi; + } sfmt_cstdfu; + struct { /* */ + UINT f_CCi; + UINT f_GRi; + UINT f_GRj; + UINT f_GRk; + UINT f_cond; + unsigned char in_CCi; + unsigned char in_GRdoublek; + unsigned char in_GRi; + unsigned char in_GRj; + unsigned char out_GRi; + } sfmt_cstdu; + struct { /* */ + UINT f_CCi; + UINT f_FRk; + UINT f_GRi; + UINT f_GRj; + UINT f_cond; + unsigned char in_CCi; + unsigned char in_FRintk; + unsigned char in_GRi; + unsigned char in_GRj; + unsigned char out_GRi; + } sfmt_cstbfu; + struct { /* */ + UINT f_CCi; + UINT f_GRi; + UINT f_GRj; + UINT f_GRk; + UINT f_cond; + unsigned char in_CCi; + unsigned char in_GRi; + unsigned char in_GRj; + unsigned char in_GRk; + unsigned char out_GRi; + } sfmt_cstbu; + struct { /* */ + UINT f_CCi; + UINT f_FRk; + UINT f_GRi; + UINT f_GRj; + UINT f_cond; + unsigned char in_CCi; + unsigned char in_GRi; + unsigned char in_GRj; + unsigned char out_FRdoublek; + unsigned char out_GRi; + } sfmt_clddfu; + struct { /* */ + UINT f_CCi; + UINT f_GRi; + UINT f_GRj; + UINT f_GRk; + UINT f_cond; + unsigned char in_CCi; + unsigned char in_GRi; + unsigned char in_GRj; + unsigned char out_GRdoublek; + unsigned char out_GRi; + } sfmt_clddu; + struct { /* */ + UINT f_CCi; + UINT f_FRk; + UINT f_GRi; + UINT f_GRj; + UINT f_cond; + unsigned char in_CCi; + unsigned char in_GRi; + unsigned char in_GRj; + unsigned char out_FRintk; + unsigned char out_GRi; + } sfmt_cldbfu; + struct { /* */ + UINT f_CCi; + UINT f_GRi; + UINT f_GRj; + UINT f_GRk; + UINT f_cond; + unsigned char in_CCi; + unsigned char in_GRi; + unsigned char in_GRj; + unsigned char out_GRi; + unsigned char out_GRk; + } sfmt_cldsbu; + struct { /* */ + UINT f_FCCk; + UINT f_FRi; + UINT f_FRj; + unsigned char in_FRinti; + unsigned char in_FRintj; + unsigned char in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRinti_0; + unsigned char in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintj_0; + unsigned char in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRinti_0; + unsigned char in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintj_0; + unsigned char out_FCCk; + unsigned char out_h_fccr_UQI_add__DFLT_index_of__DFLT_FCCk_1; + } sfmt_mcmpsh; + struct { /* */ + UINT f_FRi; + UINT f_FRk; + UINT f_u6; + unsigned char in_FRinti; + unsigned char in_FRintk; + unsigned char in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRinti_0; + unsigned char in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRinti_0; + unsigned char out_FRinti; + unsigned char out_FRintk; + unsigned char out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintk_0; + unsigned char out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintk_0; + } sfmt_msllhi; + struct { /* */ + UINT f_FRi; + UINT f_FRj; + UINT f_FRk; + unsigned char in_FRi; + unsigned char in_FRj; + unsigned char in_FRk; + unsigned char in_h_fr_SF_add__DFLT_index_of__DFLT_FRi_1; + unsigned char in_h_fr_SF_add__DFLT_index_of__DFLT_FRj_1; + unsigned char in_h_fr_SF_add__DFLT_index_of__DFLT_FRk_1; + unsigned char out_FRk; + unsigned char out_h_fr_SF_add__DFLT_index_of__DFLT_FRk_1; + } sfmt_fdmadds; + struct { /* */ + UINT f_FCCi_2; + UINT f_GRi; + UINT f_GRj; + unsigned short out_h_spr_USI_1; + unsigned short out_h_spr_USI_768; + unsigned short out_h_spr_USI_769; + unsigned short out_h_spr_USI_770; + unsigned short out_h_spr_USI_771; + unsigned char in_FCCi_2; + unsigned char in_GRi; + unsigned char in_GRj; + } sfmt_ftne; + struct { /* */ + UINT f_GRi; + UINT f_GRj; + UINT f_ICCi_2; + unsigned short out_h_spr_USI_1; + unsigned short out_h_spr_USI_768; + unsigned short out_h_spr_USI_769; + unsigned short out_h_spr_USI_770; + unsigned short out_h_spr_USI_771; + unsigned char in_GRi; + unsigned char in_GRj; + unsigned char in_ICCi_2; + } sfmt_teq; + struct { /* */ + UINT f_CCi; + UINT f_GRi; + UINT f_GRj; + UINT f_GRk; + UINT f_cond; + unsigned char in_CCi; + unsigned char in_GRi; + unsigned char in_GRj; + unsigned char in_h_iccr_UQI_and__DFLT_index_of__DFLT_CCi_3; + unsigned char out_GRdoublek; + unsigned char out_h_iccr_UQI_and__DFLT_index_of__DFLT_CCi_3; + } sfmt_csmulcc; + struct { /* */ + UINT f_CCi; + UINT f_GRi; + UINT f_GRj; + UINT f_GRk; + UINT f_cond; + unsigned char in_CCi; + unsigned char in_GRi; + unsigned char in_GRj; + unsigned char in_h_iccr_UQI_and__DFLT_index_of__DFLT_CCi_3; + unsigned char out_GRk; + unsigned char out_h_iccr_UQI_and__DFLT_index_of__DFLT_CCi_3; + } sfmt_caddcc; + struct { /* */ + UINT f_FRi; + UINT f_FRk; + unsigned char in_FRinti; + unsigned char in_FRintkeven; + unsigned char in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRinti_0; + unsigned char in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRinti_0; + unsigned char out_FRinti; + unsigned char out_FRintkeven; + unsigned char out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintkeven_0; + unsigned char out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintkeven_add__DFLT_0_1; + unsigned char out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintkeven_0; + unsigned char out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintkeven_add__DFLT_0_1; + } sfmt_munpackh; + struct { /* */ + UINT f_CCi; + UINT f_FRi; + UINT f_FRj; + UINT f_FRk; + UINT f_cond; + unsigned char in_CCi; + unsigned char in_FRi; + unsigned char in_FRj; + unsigned char in_h_fr_SF_add__DFLT_index_of__DFLT_FRi_1; + unsigned char in_h_fr_SF_add__DFLT_index_of__DFLT_FRj_1; + unsigned char out_FRk; + unsigned char out_h_fr_SF_add__DFLT_index_of__DFLT_FRk_1; + } sfmt_cfmas; + struct { /* */ + UINT f_CCi; + UINT f_FRi; + UINT f_FRk; + UINT f_cond; + UINT f_u6; + unsigned char in_CCi; + unsigned char in_FRintkeven; + unsigned char in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRinti_0; + unsigned char in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRinti_0; + unsigned char out_FRintkeven; + unsigned char out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintkeven_0; + unsigned char out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintkeven_1; + unsigned char out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintkeven_0; + unsigned char out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintkeven_1; + } sfmt_cmexpdhd; + struct { /* */ + UINT f_CCi; + UINT f_FRi; + UINT f_FRj; + UINT f_FRk; + UINT f_cond; + unsigned char in_CCi; + unsigned char in_FRinti; + unsigned char in_FRintj; + unsigned char in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRinti_0; + unsigned char in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintj_0; + unsigned char in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRinti_0; + unsigned char in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintj_0; + unsigned char out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintk_0; + unsigned char out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintk_0; + } sfmt_cmaddhss; + struct { /* */ + UINT f_FRi; + UINT f_FRj; + UINT f_FRk; + unsigned char in_FRi; + unsigned char in_FRj; + unsigned char in_h_fr_SF_add__DFLT_index_of__DFLT_FRi_1; + unsigned char in_h_fr_SF_add__DFLT_index_of__DFLT_FRi_2; + unsigned char in_h_fr_SF_add__DFLT_index_of__DFLT_FRi_3; + unsigned char in_h_fr_SF_add__DFLT_index_of__DFLT_FRj_1; + unsigned char in_h_fr_SF_add__DFLT_index_of__DFLT_FRj_2; + unsigned char in_h_fr_SF_add__DFLT_index_of__DFLT_FRj_3; + unsigned char out_FRk; + unsigned char out_h_fr_SF_add__DFLT_index_of__DFLT_FRk_1; + unsigned char out_h_fr_SF_add__DFLT_index_of__DFLT_FRk_2; + unsigned char out_h_fr_SF_add__DFLT_index_of__DFLT_FRk_3; + } sfmt_fdmas; + struct { /* */ + UINT f_ACC40Uk; + UINT f_CCi; + UINT f_FRi; + UINT f_FRj; + UINT f_cond; + unsigned char in_ACC40Uk; + unsigned char in_CCi; + unsigned char in_FRinti; + unsigned char in_FRintj; + unsigned char in_h_acc40U_UDI_add__DFLT_index_of__DFLT_ACC40Uk_1; + unsigned char in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRinti_0; + unsigned char in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintj_0; + unsigned char in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRinti_0; + unsigned char in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintj_0; + unsigned char out_ACC40Uk; + unsigned char out_h_acc40U_UDI_add__DFLT_index_of__DFLT_ACC40Uk_1; + } sfmt_cmmachu; + struct { /* */ + UINT f_ACC40Sk; + UINT f_CCi; + UINT f_FRi; + UINT f_FRj; + UINT f_cond; + unsigned char in_ACC40Sk; + unsigned char in_CCi; + unsigned char in_FRinti; + unsigned char in_FRintj; + unsigned char in_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Sk_1; + unsigned char in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRinti_0; + unsigned char in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintj_0; + unsigned char in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRinti_0; + unsigned char in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintj_0; + unsigned char out_ACC40Sk; + unsigned char out_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Sk_1; + } sfmt_cmmachs; + struct { /* */ + UINT f_CCi; + UINT f_FRj; + UINT f_FRk; + UINT f_cond; + unsigned char in_CCi; + unsigned char in_FRintjeven; + unsigned char in_FRintk; + unsigned char in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintjeven_0; + unsigned char in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintjeven_1; + unsigned char in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintjeven_0; + unsigned char in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintjeven_1; + unsigned char out_FRintjeven; + unsigned char out_FRintk; + unsigned char out_h_fr_0_UHI_add__DFLT_index_of__DFLT_FRintk_0; + unsigned char out_h_fr_1_UHI_add__DFLT_index_of__DFLT_FRintk_0; + unsigned char out_h_fr_2_UHI_add__DFLT_index_of__DFLT_FRintk_0; + unsigned char out_h_fr_3_UHI_add__DFLT_index_of__DFLT_FRintk_0; + } sfmt_cmhtob; + struct { /* */ + UINT f_CCi; + UINT f_FRj; + UINT f_FRk; + UINT f_cond; + unsigned char in_CCi; + unsigned char in_FRintj; + unsigned char in_FRintkeven; + unsigned char in_h_fr_0_UHI_add__DFLT_index_of__DFLT_FRintj_0; + unsigned char in_h_fr_1_UHI_add__DFLT_index_of__DFLT_FRintj_0; + unsigned char in_h_fr_2_UHI_add__DFLT_index_of__DFLT_FRintj_0; + unsigned char in_h_fr_3_UHI_add__DFLT_index_of__DFLT_FRintj_0; + unsigned char out_FRintj; + unsigned char out_FRintkeven; + unsigned char out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintkeven_0; + unsigned char out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintkeven_1; + unsigned char out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintkeven_0; + unsigned char out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintkeven_1; + } sfmt_cmbtoh; + struct { /* */ + UINT f_FRi; + UINT f_FRj; + UINT f_FRk; + unsigned char in_FRintieven; + unsigned char in_FRintjeven; + unsigned char in_FRintkeven; + unsigned char in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintieven_0; + unsigned char in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintieven_1; + unsigned char in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintjeven_0; + unsigned char in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintjeven_1; + unsigned char out_FRintieven; + unsigned char out_FRintjeven; + unsigned char out_FRintkeven; + unsigned char out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintkeven_0; + unsigned char out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintkeven_1; + unsigned char out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintkeven_0; + unsigned char out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintkeven_1; + } sfmt_mdpackh; + struct { /* */ + UINT f_FRi; + UINT f_FRk; + unsigned char in_FRintieven; + unsigned char in_FRintk; + unsigned char in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintieven_0; + unsigned char in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintieven_1; + unsigned char in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintieven_0; + unsigned char in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintieven_1; + unsigned char out_FRintieven; + unsigned char out_FRintk; + unsigned char out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintk_0; + unsigned char out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintk_2; + unsigned char out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintk_add__DFLT_0_1; + unsigned char out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintk_add__DFLT_2_1; + unsigned char out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintk_0; + unsigned char out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintk_2; + unsigned char out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintk_add__DFLT_0_1; + unsigned char out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintk_add__DFLT_2_1; + } sfmt_mdunpackh; + struct { /* */ + UINT f_CCi; + UINT f_FRj; + UINT f_FRk; + UINT f_cond; + unsigned char in_CCi; + unsigned char in_FRintj; + unsigned char in_FRintk; + unsigned char in_h_fr_0_UHI_add__DFLT_index_of__DFLT_FRintj_0; + unsigned char in_h_fr_1_UHI_add__DFLT_index_of__DFLT_FRintj_0; + unsigned char in_h_fr_2_UHI_add__DFLT_index_of__DFLT_FRintj_0; + unsigned char in_h_fr_3_UHI_add__DFLT_index_of__DFLT_FRintj_0; + unsigned char out_FRintj; + unsigned char out_FRintk; + unsigned char out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintk_0; + unsigned char out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintk_1; + unsigned char out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintk_2; + unsigned char out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintk_3; + unsigned char out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintk_0; + unsigned char out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintk_1; + unsigned char out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintk_2; + unsigned char out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintk_3; + } sfmt_cmbtohe; + struct { /* */ + UINT f_CCi; + UINT f_FRi; + UINT f_FRj; + UINT f_FRk; + UINT f_cond; + unsigned char in_CCi; + unsigned char in_FRintieven; + unsigned char in_FRintjeven; + unsigned char in_FRintkeven; + unsigned char in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintieven_0; + unsigned char in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintieven_1; + unsigned char in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintjeven_0; + unsigned char in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintjeven_1; + unsigned char in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintieven_0; + unsigned char in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintieven_1; + unsigned char in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintjeven_0; + unsigned char in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintjeven_1; + unsigned char out_FRintkeven; + unsigned char out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintkeven_0; + unsigned char out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintkeven_1; + unsigned char out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintkeven_0; + unsigned char out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintkeven_1; + } sfmt_cmqaddhss; + struct { /* */ + UINT f_ACC40Uk; + UINT f_CCi; + UINT f_FRi; + UINT f_FRj; + UINT f_cond; + unsigned char in_ACC40Uk; + unsigned char in_CCi; + unsigned char in_FRintieven; + unsigned char in_FRintjeven; + unsigned char in_h_acc40U_UDI_add__DFLT_index_of__DFLT_ACC40Uk_1; + unsigned char in_h_acc40U_UDI_add__DFLT_index_of__DFLT_ACC40Uk_2; + unsigned char in_h_acc40U_UDI_add__DFLT_index_of__DFLT_ACC40Uk_3; + unsigned char in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintieven_0; + unsigned char in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintieven_1; + unsigned char in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintjeven_0; + unsigned char in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintjeven_1; + unsigned char in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintieven_0; + unsigned char in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintieven_1; + unsigned char in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintjeven_0; + unsigned char in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintjeven_1; + unsigned char out_ACC40Uk; + unsigned char out_h_acc40U_UDI_add__DFLT_index_of__DFLT_ACC40Uk_1; + unsigned char out_h_acc40U_UDI_add__DFLT_index_of__DFLT_ACC40Uk_2; + unsigned char out_h_acc40U_UDI_add__DFLT_index_of__DFLT_ACC40Uk_3; + } sfmt_cmqmachu; + struct { /* */ + UINT f_ACC40Sk; + UINT f_CCi; + UINT f_FRi; + UINT f_FRj; + UINT f_cond; + unsigned char in_ACC40Sk; + unsigned char in_CCi; + unsigned char in_FRintieven; + unsigned char in_FRintjeven; + unsigned char in_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Sk_1; + unsigned char in_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Sk_2; + unsigned char in_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Sk_3; + unsigned char in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintieven_0; + unsigned char in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintieven_1; + unsigned char in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintjeven_0; + unsigned char in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintjeven_1; + unsigned char in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintieven_0; + unsigned char in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintieven_1; + unsigned char in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintjeven_0; + unsigned char in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintjeven_1; + unsigned char out_ACC40Sk; + unsigned char out_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Sk_1; + unsigned char out_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Sk_2; + unsigned char out_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Sk_3; + } sfmt_cmqmachs; +#if WITH_SCACHE_PBB + /* Writeback handler. */ + struct { + /* Pointer to argbuf entry for insn whose results need writing back. */ + const struct argbuf *abuf; + } write; + /* x-before handler */ + struct { + /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/ + int first_p; + } before; + /* x-after handler */ + struct { + int empty; + } after; + /* This entry is used to terminate each pbb. */ + struct { + /* Number of insns in pbb. */ + int insn_count; + /* Next pbb to execute. */ + SCACHE *next; + SCACHE *branch_target; + } chain; +#endif +}; + +/* The ARGBUF struct. */ +struct argbuf { + /* These are the baseclass definitions. */ + IADDR addr; + const IDESC *idesc; + char trace_p; + char profile_p; + /* ??? Temporary hack for skip insns. */ + char skip_count; + char unused; + /* cpu specific data follows */ + union sem semantic; + int written; + union sem_fields fields; +}; + +/* A cached insn. + + ??? SCACHE used to contain more than just argbuf. We could delete the + type entirely and always just use ARGBUF, but for future concerns and as + a level of abstraction it is left in. */ + +struct scache { + struct argbuf argbuf; + int first_insn_p; + int last_insn_p; +}; + +/* Macros to simplify extraction, reading and semantic code. + These define and assign the local vars that contain the insn's fields. */ + +#define EXTRACT_IFMT_EMPTY_VARS \ + unsigned int length; +#define EXTRACT_IFMT_EMPTY_CODE \ + length = 0; \ + +#define EXTRACT_IFMT_ADD_VARS \ + UINT f_pack; \ + UINT f_GRk; \ + UINT f_op; \ + UINT f_GRi; \ + UINT f_ICCi_1_null; \ + UINT f_ope2; \ + UINT f_GRj; \ + unsigned int length; +#define EXTRACT_IFMT_ADD_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_ICCi_1_null = EXTRACT_LSB0_UINT (insn, 32, 11, 2); \ + f_ope2 = EXTRACT_LSB0_UINT (insn, 32, 9, 4); \ + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_NOT_VARS \ + UINT f_pack; \ + UINT f_GRk; \ + UINT f_op; \ + UINT f_rs_null; \ + UINT f_ICCi_1_null; \ + UINT f_ope2; \ + UINT f_GRj; \ + unsigned int length; +#define EXTRACT_IFMT_NOT_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_rs_null = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_ICCi_1_null = EXTRACT_LSB0_UINT (insn, 32, 11, 2); \ + f_ope2 = EXTRACT_LSB0_UINT (insn, 32, 9, 4); \ + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_SMUL_VARS \ + UINT f_pack; \ + UINT f_GRk; \ + UINT f_op; \ + UINT f_GRi; \ + UINT f_ICCi_1_null; \ + UINT f_ope2; \ + UINT f_GRj; \ + unsigned int length; +#define EXTRACT_IFMT_SMUL_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_ICCi_1_null = EXTRACT_LSB0_UINT (insn, 32, 11, 2); \ + f_ope2 = EXTRACT_LSB0_UINT (insn, 32, 9, 4); \ + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_SMU_VARS \ + UINT f_pack; \ + UINT f_rd_null; \ + UINT f_op; \ + UINT f_GRi; \ + UINT f_ope1; \ + UINT f_GRj; \ + unsigned int length; +#define EXTRACT_IFMT_SMU_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_rd_null = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \ + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_SLASS_VARS \ + UINT f_pack; \ + UINT f_GRk; \ + UINT f_op; \ + UINT f_GRi; \ + UINT f_ope1; \ + UINT f_GRj; \ + unsigned int length; +#define EXTRACT_IFMT_SLASS_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \ + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_SCUTSS_VARS \ + UINT f_pack; \ + UINT f_GRk; \ + UINT f_op; \ + UINT f_rs_null; \ + UINT f_ope1; \ + UINT f_GRj; \ + unsigned int length; +#define EXTRACT_IFMT_SCUTSS_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_rs_null = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \ + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_CADD_VARS \ + UINT f_pack; \ + UINT f_GRk; \ + UINT f_op; \ + UINT f_GRi; \ + UINT f_CCi; \ + UINT f_cond; \ + UINT f_ope4; \ + UINT f_GRj; \ + unsigned int length; +#define EXTRACT_IFMT_CADD_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); \ + f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); \ + f_ope4 = EXTRACT_LSB0_UINT (insn, 32, 7, 2); \ + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_CNOT_VARS \ + UINT f_pack; \ + UINT f_GRk; \ + UINT f_op; \ + UINT f_rs_null; \ + UINT f_CCi; \ + UINT f_cond; \ + UINT f_ope4; \ + UINT f_GRj; \ + unsigned int length; +#define EXTRACT_IFMT_CNOT_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_rs_null = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); \ + f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); \ + f_ope4 = EXTRACT_LSB0_UINT (insn, 32, 7, 2); \ + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_CSMUL_VARS \ + UINT f_pack; \ + UINT f_GRk; \ + UINT f_op; \ + UINT f_GRi; \ + UINT f_CCi; \ + UINT f_cond; \ + UINT f_ope4; \ + UINT f_GRj; \ + unsigned int length; +#define EXTRACT_IFMT_CSMUL_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); \ + f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); \ + f_ope4 = EXTRACT_LSB0_UINT (insn, 32, 7, 2); \ + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_ADDCC_VARS \ + UINT f_pack; \ + UINT f_GRk; \ + UINT f_op; \ + UINT f_GRi; \ + UINT f_ICCi_1; \ + UINT f_ope2; \ + UINT f_GRj; \ + unsigned int length; +#define EXTRACT_IFMT_ADDCC_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_ICCi_1 = EXTRACT_LSB0_UINT (insn, 32, 11, 2); \ + f_ope2 = EXTRACT_LSB0_UINT (insn, 32, 9, 4); \ + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_SMULCC_VARS \ + UINT f_pack; \ + UINT f_GRk; \ + UINT f_op; \ + UINT f_GRi; \ + UINT f_ICCi_1; \ + UINT f_ope2; \ + UINT f_GRj; \ + unsigned int length; +#define EXTRACT_IFMT_SMULCC_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_ICCi_1 = EXTRACT_LSB0_UINT (insn, 32, 11, 2); \ + f_ope2 = EXTRACT_LSB0_UINT (insn, 32, 9, 4); \ + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_ADDI_VARS \ + UINT f_pack; \ + UINT f_GRk; \ + UINT f_op; \ + UINT f_GRi; \ + INT f_d12; \ + unsigned int length; +#define EXTRACT_IFMT_ADDI_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_d12 = EXTRACT_LSB0_INT (insn, 32, 11, 12); \ + +#define EXTRACT_IFMT_SMULI_VARS \ + UINT f_pack; \ + UINT f_GRk; \ + UINT f_op; \ + UINT f_GRi; \ + INT f_d12; \ + unsigned int length; +#define EXTRACT_IFMT_SMULI_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_d12 = EXTRACT_LSB0_INT (insn, 32, 11, 12); \ + +#define EXTRACT_IFMT_ADDICC_VARS \ + UINT f_pack; \ + UINT f_GRk; \ + UINT f_op; \ + UINT f_GRi; \ + UINT f_ICCi_1; \ + INT f_s10; \ + unsigned int length; +#define EXTRACT_IFMT_ADDICC_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_ICCi_1 = EXTRACT_LSB0_UINT (insn, 32, 11, 2); \ + f_s10 = EXTRACT_LSB0_INT (insn, 32, 9, 10); \ + +#define EXTRACT_IFMT_SMULICC_VARS \ + UINT f_pack; \ + UINT f_GRk; \ + UINT f_op; \ + UINT f_GRi; \ + UINT f_ICCi_1; \ + INT f_s10; \ + unsigned int length; +#define EXTRACT_IFMT_SMULICC_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_ICCi_1 = EXTRACT_LSB0_UINT (insn, 32, 11, 2); \ + f_s10 = EXTRACT_LSB0_INT (insn, 32, 9, 10); \ + +#define EXTRACT_IFMT_CMPB_VARS \ + UINT f_pack; \ + UINT f_GRk_null; \ + UINT f_op; \ + UINT f_GRi; \ + UINT f_ICCi_1; \ + UINT f_ope2; \ + UINT f_GRj; \ + unsigned int length; +#define EXTRACT_IFMT_CMPB_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_GRk_null = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_ICCi_1 = EXTRACT_LSB0_UINT (insn, 32, 11, 2); \ + f_ope2 = EXTRACT_LSB0_UINT (insn, 32, 9, 4); \ + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_SETLO_VARS \ + UINT f_pack; \ + UINT f_GRk; \ + UINT f_op; \ + UINT f_misc_null_4; \ + UINT f_u16; \ + unsigned int length; +#define EXTRACT_IFMT_SETLO_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_misc_null_4 = EXTRACT_LSB0_UINT (insn, 32, 17, 2); \ + f_u16 = EXTRACT_LSB0_UINT (insn, 32, 15, 16); \ + +#define EXTRACT_IFMT_SETHI_VARS \ + UINT f_pack; \ + UINT f_GRk; \ + UINT f_op; \ + UINT f_misc_null_4; \ + UINT f_u16; \ + unsigned int length; +#define EXTRACT_IFMT_SETHI_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_misc_null_4 = EXTRACT_LSB0_UINT (insn, 32, 17, 2); \ + f_u16 = EXTRACT_LSB0_UINT (insn, 32, 15, 16); \ + +#define EXTRACT_IFMT_SETLOS_VARS \ + UINT f_pack; \ + UINT f_GRk; \ + UINT f_op; \ + UINT f_misc_null_4; \ + INT f_s16; \ + unsigned int length; +#define EXTRACT_IFMT_SETLOS_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_misc_null_4 = EXTRACT_LSB0_UINT (insn, 32, 17, 2); \ + f_s16 = EXTRACT_LSB0_INT (insn, 32, 15, 16); \ + +#define EXTRACT_IFMT_LDBF_VARS \ + UINT f_pack; \ + UINT f_FRk; \ + UINT f_op; \ + UINT f_GRi; \ + UINT f_ope1; \ + UINT f_GRj; \ + unsigned int length; +#define EXTRACT_IFMT_LDBF_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \ + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_LDC_VARS \ + UINT f_pack; \ + UINT f_CPRk; \ + UINT f_op; \ + UINT f_GRi; \ + UINT f_ope1; \ + UINT f_GRj; \ + unsigned int length; +#define EXTRACT_IFMT_LDC_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_CPRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \ + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_LDD_VARS \ + UINT f_pack; \ + UINT f_GRk; \ + UINT f_op; \ + UINT f_GRi; \ + UINT f_ope1; \ + UINT f_GRj; \ + unsigned int length; +#define EXTRACT_IFMT_LDD_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \ + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_LDDF_VARS \ + UINT f_pack; \ + UINT f_FRk; \ + UINT f_op; \ + UINT f_GRi; \ + UINT f_ope1; \ + UINT f_GRj; \ + unsigned int length; +#define EXTRACT_IFMT_LDDF_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \ + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_LDDC_VARS \ + UINT f_pack; \ + UINT f_CPRk; \ + UINT f_op; \ + UINT f_GRi; \ + UINT f_ope1; \ + UINT f_GRj; \ + unsigned int length; +#define EXTRACT_IFMT_LDDC_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_CPRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \ + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_LDSBI_VARS \ + UINT f_pack; \ + UINT f_GRk; \ + UINT f_op; \ + UINT f_GRi; \ + INT f_d12; \ + unsigned int length; +#define EXTRACT_IFMT_LDSBI_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_d12 = EXTRACT_LSB0_INT (insn, 32, 11, 12); \ + +#define EXTRACT_IFMT_LDBFI_VARS \ + UINT f_pack; \ + UINT f_FRk; \ + UINT f_op; \ + UINT f_GRi; \ + INT f_d12; \ + unsigned int length; +#define EXTRACT_IFMT_LDBFI_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_d12 = EXTRACT_LSB0_INT (insn, 32, 11, 12); \ + +#define EXTRACT_IFMT_LDDI_VARS \ + UINT f_pack; \ + UINT f_GRk; \ + UINT f_op; \ + UINT f_GRi; \ + INT f_d12; \ + unsigned int length; +#define EXTRACT_IFMT_LDDI_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_d12 = EXTRACT_LSB0_INT (insn, 32, 11, 12); \ + +#define EXTRACT_IFMT_LDDFI_VARS \ + UINT f_pack; \ + UINT f_FRk; \ + UINT f_op; \ + UINT f_GRi; \ + INT f_d12; \ + unsigned int length; +#define EXTRACT_IFMT_LDDFI_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_d12 = EXTRACT_LSB0_INT (insn, 32, 11, 12); \ + +#define EXTRACT_IFMT_CLDBF_VARS \ + UINT f_pack; \ + UINT f_FRk; \ + UINT f_op; \ + UINT f_GRi; \ + UINT f_CCi; \ + UINT f_cond; \ + UINT f_ope4; \ + UINT f_GRj; \ + unsigned int length; +#define EXTRACT_IFMT_CLDBF_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); \ + f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); \ + f_ope4 = EXTRACT_LSB0_UINT (insn, 32, 7, 2); \ + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_CLDDF_VARS \ + UINT f_pack; \ + UINT f_FRk; \ + UINT f_op; \ + UINT f_GRi; \ + UINT f_CCi; \ + UINT f_cond; \ + UINT f_ope4; \ + UINT f_GRj; \ + unsigned int length; +#define EXTRACT_IFMT_CLDDF_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); \ + f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); \ + f_ope4 = EXTRACT_LSB0_UINT (insn, 32, 7, 2); \ + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_MOVGF_VARS \ + UINT f_pack; \ + UINT f_FRk; \ + UINT f_op; \ + UINT f_rs_null; \ + UINT f_ope1; \ + UINT f_GRj; \ + unsigned int length; +#define EXTRACT_IFMT_MOVGF_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_rs_null = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \ + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_CMOVGF_VARS \ + UINT f_pack; \ + UINT f_FRk; \ + UINT f_op; \ + UINT f_rs_null; \ + UINT f_CCi; \ + UINT f_cond; \ + UINT f_ope4; \ + UINT f_GRj; \ + unsigned int length; +#define EXTRACT_IFMT_CMOVGF_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_rs_null = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); \ + f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); \ + f_ope4 = EXTRACT_LSB0_UINT (insn, 32, 7, 2); \ + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_MOVGS_VARS \ + UINT f_pack; \ + UINT f_op; \ + UINT f_spr_h; \ + UINT f_spr_l; \ + UINT f_spr; \ + UINT f_ope1; \ + UINT f_GRj; \ + unsigned int length; +#define EXTRACT_IFMT_MOVGS_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_spr_h = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_spr_l = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ +{\ + f_spr = ((((f_spr_h) << (6))) | (f_spr_l));\ +}\ + f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \ + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_BRA_VARS \ + UINT f_pack; \ + UINT f_int_cc; \ + UINT f_ICCi_2_null; \ + UINT f_op; \ + UINT f_hint; \ + SI f_label16; \ + unsigned int length; +#define EXTRACT_IFMT_BRA_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_int_cc = EXTRACT_LSB0_UINT (insn, 32, 30, 4); \ + f_ICCi_2_null = EXTRACT_LSB0_UINT (insn, 32, 26, 2); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_hint = EXTRACT_LSB0_UINT (insn, 32, 17, 2); \ + f_label16 = ((((EXTRACT_LSB0_INT (insn, 32, 15, 16)) << (2))) + (pc)); \ + +#define EXTRACT_IFMT_BNO_VARS \ + UINT f_pack; \ + UINT f_int_cc; \ + UINT f_ICCi_2_null; \ + UINT f_op; \ + UINT f_hint; \ + UINT f_label16_null; \ + unsigned int length; +#define EXTRACT_IFMT_BNO_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_int_cc = EXTRACT_LSB0_UINT (insn, 32, 30, 4); \ + f_ICCi_2_null = EXTRACT_LSB0_UINT (insn, 32, 26, 2); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_hint = EXTRACT_LSB0_UINT (insn, 32, 17, 2); \ + f_label16_null = EXTRACT_LSB0_UINT (insn, 32, 15, 16); \ + +#define EXTRACT_IFMT_BEQ_VARS \ + UINT f_pack; \ + UINT f_int_cc; \ + UINT f_ICCi_2; \ + UINT f_op; \ + UINT f_hint; \ + SI f_label16; \ + unsigned int length; +#define EXTRACT_IFMT_BEQ_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_int_cc = EXTRACT_LSB0_UINT (insn, 32, 30, 4); \ + f_ICCi_2 = EXTRACT_LSB0_UINT (insn, 32, 26, 2); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_hint = EXTRACT_LSB0_UINT (insn, 32, 17, 2); \ + f_label16 = ((((EXTRACT_LSB0_INT (insn, 32, 15, 16)) << (2))) + (pc)); \ + +#define EXTRACT_IFMT_FBRA_VARS \ + UINT f_pack; \ + UINT f_flt_cc; \ + UINT f_FCCi_2_null; \ + UINT f_op; \ + UINT f_hint; \ + SI f_label16; \ + unsigned int length; +#define EXTRACT_IFMT_FBRA_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_flt_cc = EXTRACT_LSB0_UINT (insn, 32, 30, 4); \ + f_FCCi_2_null = EXTRACT_LSB0_UINT (insn, 32, 26, 2); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_hint = EXTRACT_LSB0_UINT (insn, 32, 17, 2); \ + f_label16 = ((((EXTRACT_LSB0_INT (insn, 32, 15, 16)) << (2))) + (pc)); \ + +#define EXTRACT_IFMT_FBNO_VARS \ + UINT f_pack; \ + UINT f_flt_cc; \ + UINT f_FCCi_2_null; \ + UINT f_op; \ + UINT f_hint; \ + UINT f_label16_null; \ + unsigned int length; +#define EXTRACT_IFMT_FBNO_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_flt_cc = EXTRACT_LSB0_UINT (insn, 32, 30, 4); \ + f_FCCi_2_null = EXTRACT_LSB0_UINT (insn, 32, 26, 2); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_hint = EXTRACT_LSB0_UINT (insn, 32, 17, 2); \ + f_label16_null = EXTRACT_LSB0_UINT (insn, 32, 15, 16); \ + +#define EXTRACT_IFMT_FBNE_VARS \ + UINT f_pack; \ + UINT f_flt_cc; \ + UINT f_FCCi_2; \ + UINT f_op; \ + UINT f_hint; \ + SI f_label16; \ + unsigned int length; +#define EXTRACT_IFMT_FBNE_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_flt_cc = EXTRACT_LSB0_UINT (insn, 32, 30, 4); \ + f_FCCi_2 = EXTRACT_LSB0_UINT (insn, 32, 26, 2); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_hint = EXTRACT_LSB0_UINT (insn, 32, 17, 2); \ + f_label16 = ((((EXTRACT_LSB0_INT (insn, 32, 15, 16)) << (2))) + (pc)); \ + +#define EXTRACT_IFMT_BCTRLR_VARS \ + UINT f_pack; \ + UINT f_cond_null; \ + UINT f_ICCi_2_null; \ + UINT f_op; \ + UINT f_hint; \ + UINT f_ope3; \ + UINT f_ccond; \ + UINT f_s12_null; \ + unsigned int length; +#define EXTRACT_IFMT_BCTRLR_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_cond_null = EXTRACT_LSB0_UINT (insn, 32, 30, 4); \ + f_ICCi_2_null = EXTRACT_LSB0_UINT (insn, 32, 26, 2); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_hint = EXTRACT_LSB0_UINT (insn, 32, 17, 2); \ + f_ope3 = EXTRACT_LSB0_UINT (insn, 32, 15, 3); \ + f_ccond = EXTRACT_LSB0_UINT (insn, 32, 12, 1); \ + f_s12_null = EXTRACT_LSB0_UINT (insn, 32, 11, 12); \ + +#define EXTRACT_IFMT_BRALR_VARS \ + UINT f_pack; \ + UINT f_int_cc; \ + UINT f_ICCi_2_null; \ + UINT f_op; \ + UINT f_hint; \ + UINT f_ope3; \ + UINT f_ccond_null; \ + UINT f_s12_null; \ + unsigned int length; +#define EXTRACT_IFMT_BRALR_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_int_cc = EXTRACT_LSB0_UINT (insn, 32, 30, 4); \ + f_ICCi_2_null = EXTRACT_LSB0_UINT (insn, 32, 26, 2); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_hint = EXTRACT_LSB0_UINT (insn, 32, 17, 2); \ + f_ope3 = EXTRACT_LSB0_UINT (insn, 32, 15, 3); \ + f_ccond_null = EXTRACT_LSB0_UINT (insn, 32, 12, 1); \ + f_s12_null = EXTRACT_LSB0_UINT (insn, 32, 11, 12); \ + +#define EXTRACT_IFMT_BNOLR_VARS \ + UINT f_pack; \ + UINT f_int_cc; \ + UINT f_ICCi_2_null; \ + UINT f_op; \ + UINT f_hint; \ + UINT f_ope3; \ + UINT f_ccond_null; \ + UINT f_s12_null; \ + unsigned int length; +#define EXTRACT_IFMT_BNOLR_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_int_cc = EXTRACT_LSB0_UINT (insn, 32, 30, 4); \ + f_ICCi_2_null = EXTRACT_LSB0_UINT (insn, 32, 26, 2); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_hint = EXTRACT_LSB0_UINT (insn, 32, 17, 2); \ + f_ope3 = EXTRACT_LSB0_UINT (insn, 32, 15, 3); \ + f_ccond_null = EXTRACT_LSB0_UINT (insn, 32, 12, 1); \ + f_s12_null = EXTRACT_LSB0_UINT (insn, 32, 11, 12); \ + +#define EXTRACT_IFMT_BEQLR_VARS \ + UINT f_pack; \ + UINT f_int_cc; \ + UINT f_ICCi_2; \ + UINT f_op; \ + UINT f_hint; \ + UINT f_ope3; \ + UINT f_ccond_null; \ + UINT f_s12_null; \ + unsigned int length; +#define EXTRACT_IFMT_BEQLR_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_int_cc = EXTRACT_LSB0_UINT (insn, 32, 30, 4); \ + f_ICCi_2 = EXTRACT_LSB0_UINT (insn, 32, 26, 2); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_hint = EXTRACT_LSB0_UINT (insn, 32, 17, 2); \ + f_ope3 = EXTRACT_LSB0_UINT (insn, 32, 15, 3); \ + f_ccond_null = EXTRACT_LSB0_UINT (insn, 32, 12, 1); \ + f_s12_null = EXTRACT_LSB0_UINT (insn, 32, 11, 12); \ + +#define EXTRACT_IFMT_FBRALR_VARS \ + UINT f_pack; \ + UINT f_flt_cc; \ + UINT f_FCCi_2_null; \ + UINT f_op; \ + UINT f_hint; \ + UINT f_ope3; \ + UINT f_ccond_null; \ + UINT f_s12_null; \ + unsigned int length; +#define EXTRACT_IFMT_FBRALR_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_flt_cc = EXTRACT_LSB0_UINT (insn, 32, 30, 4); \ + f_FCCi_2_null = EXTRACT_LSB0_UINT (insn, 32, 26, 2); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_hint = EXTRACT_LSB0_UINT (insn, 32, 17, 2); \ + f_ope3 = EXTRACT_LSB0_UINT (insn, 32, 15, 3); \ + f_ccond_null = EXTRACT_LSB0_UINT (insn, 32, 12, 1); \ + f_s12_null = EXTRACT_LSB0_UINT (insn, 32, 11, 12); \ + +#define EXTRACT_IFMT_FBNOLR_VARS \ + UINT f_pack; \ + UINT f_flt_cc; \ + UINT f_FCCi_2_null; \ + UINT f_op; \ + UINT f_hint; \ + UINT f_ope3; \ + UINT f_ccond_null; \ + UINT f_s12_null; \ + unsigned int length; +#define EXTRACT_IFMT_FBNOLR_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_flt_cc = EXTRACT_LSB0_UINT (insn, 32, 30, 4); \ + f_FCCi_2_null = EXTRACT_LSB0_UINT (insn, 32, 26, 2); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_hint = EXTRACT_LSB0_UINT (insn, 32, 17, 2); \ + f_ope3 = EXTRACT_LSB0_UINT (insn, 32, 15, 3); \ + f_ccond_null = EXTRACT_LSB0_UINT (insn, 32, 12, 1); \ + f_s12_null = EXTRACT_LSB0_UINT (insn, 32, 11, 12); \ + +#define EXTRACT_IFMT_FBEQLR_VARS \ + UINT f_pack; \ + UINT f_flt_cc; \ + UINT f_FCCi_2; \ + UINT f_op; \ + UINT f_hint; \ + UINT f_ope3; \ + UINT f_ccond_null; \ + UINT f_s12_null; \ + unsigned int length; +#define EXTRACT_IFMT_FBEQLR_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_flt_cc = EXTRACT_LSB0_UINT (insn, 32, 30, 4); \ + f_FCCi_2 = EXTRACT_LSB0_UINT (insn, 32, 26, 2); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_hint = EXTRACT_LSB0_UINT (insn, 32, 17, 2); \ + f_ope3 = EXTRACT_LSB0_UINT (insn, 32, 15, 3); \ + f_ccond_null = EXTRACT_LSB0_UINT (insn, 32, 12, 1); \ + f_s12_null = EXTRACT_LSB0_UINT (insn, 32, 11, 12); \ + +#define EXTRACT_IFMT_BCRALR_VARS \ + UINT f_pack; \ + UINT f_int_cc; \ + UINT f_ICCi_2_null; \ + UINT f_op; \ + UINT f_hint; \ + UINT f_ope3; \ + UINT f_ccond; \ + UINT f_s12_null; \ + unsigned int length; +#define EXTRACT_IFMT_BCRALR_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_int_cc = EXTRACT_LSB0_UINT (insn, 32, 30, 4); \ + f_ICCi_2_null = EXTRACT_LSB0_UINT (insn, 32, 26, 2); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_hint = EXTRACT_LSB0_UINT (insn, 32, 17, 2); \ + f_ope3 = EXTRACT_LSB0_UINT (insn, 32, 15, 3); \ + f_ccond = EXTRACT_LSB0_UINT (insn, 32, 12, 1); \ + f_s12_null = EXTRACT_LSB0_UINT (insn, 32, 11, 12); \ + +#define EXTRACT_IFMT_BCEQLR_VARS \ + UINT f_pack; \ + UINT f_int_cc; \ + UINT f_ICCi_2; \ + UINT f_op; \ + UINT f_hint; \ + UINT f_ope3; \ + UINT f_ccond; \ + UINT f_s12_null; \ + unsigned int length; +#define EXTRACT_IFMT_BCEQLR_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_int_cc = EXTRACT_LSB0_UINT (insn, 32, 30, 4); \ + f_ICCi_2 = EXTRACT_LSB0_UINT (insn, 32, 26, 2); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_hint = EXTRACT_LSB0_UINT (insn, 32, 17, 2); \ + f_ope3 = EXTRACT_LSB0_UINT (insn, 32, 15, 3); \ + f_ccond = EXTRACT_LSB0_UINT (insn, 32, 12, 1); \ + f_s12_null = EXTRACT_LSB0_UINT (insn, 32, 11, 12); \ + +#define EXTRACT_IFMT_FCBRALR_VARS \ + UINT f_pack; \ + UINT f_flt_cc; \ + UINT f_FCCi_2_null; \ + UINT f_op; \ + UINT f_hint; \ + UINT f_ope3; \ + UINT f_ccond; \ + UINT f_s12_null; \ + unsigned int length; +#define EXTRACT_IFMT_FCBRALR_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_flt_cc = EXTRACT_LSB0_UINT (insn, 32, 30, 4); \ + f_FCCi_2_null = EXTRACT_LSB0_UINT (insn, 32, 26, 2); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_hint = EXTRACT_LSB0_UINT (insn, 32, 17, 2); \ + f_ope3 = EXTRACT_LSB0_UINT (insn, 32, 15, 3); \ + f_ccond = EXTRACT_LSB0_UINT (insn, 32, 12, 1); \ + f_s12_null = EXTRACT_LSB0_UINT (insn, 32, 11, 12); \ + +#define EXTRACT_IFMT_FCBEQLR_VARS \ + UINT f_pack; \ + UINT f_flt_cc; \ + UINT f_FCCi_2; \ + UINT f_op; \ + UINT f_hint; \ + UINT f_ope3; \ + UINT f_ccond; \ + UINT f_s12_null; \ + unsigned int length; +#define EXTRACT_IFMT_FCBEQLR_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_flt_cc = EXTRACT_LSB0_UINT (insn, 32, 30, 4); \ + f_FCCi_2 = EXTRACT_LSB0_UINT (insn, 32, 26, 2); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_hint = EXTRACT_LSB0_UINT (insn, 32, 17, 2); \ + f_ope3 = EXTRACT_LSB0_UINT (insn, 32, 15, 3); \ + f_ccond = EXTRACT_LSB0_UINT (insn, 32, 12, 1); \ + f_s12_null = EXTRACT_LSB0_UINT (insn, 32, 11, 12); \ + +#define EXTRACT_IFMT_JMPL_VARS \ + UINT f_pack; \ + UINT f_misc_null_1; \ + UINT f_LI_off; \ + UINT f_op; \ + UINT f_GRi; \ + UINT f_misc_null_2; \ + UINT f_GRj; \ + unsigned int length; +#define EXTRACT_IFMT_JMPL_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_misc_null_1 = EXTRACT_LSB0_UINT (insn, 32, 30, 5); \ + f_LI_off = EXTRACT_LSB0_UINT (insn, 32, 25, 1); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_misc_null_2 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \ + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_CALLL_VARS \ + UINT f_pack; \ + UINT f_misc_null_1; \ + UINT f_LI_on; \ + UINT f_op; \ + UINT f_GRi; \ + UINT f_misc_null_2; \ + UINT f_GRj; \ + unsigned int length; +#define EXTRACT_IFMT_CALLL_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_misc_null_1 = EXTRACT_LSB0_UINT (insn, 32, 30, 5); \ + f_LI_on = EXTRACT_LSB0_UINT (insn, 32, 25, 1); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_misc_null_2 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \ + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_JMPIL_VARS \ + UINT f_pack; \ + UINT f_misc_null_1; \ + UINT f_LI_off; \ + UINT f_op; \ + UINT f_GRi; \ + INT f_d12; \ + unsigned int length; +#define EXTRACT_IFMT_JMPIL_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_misc_null_1 = EXTRACT_LSB0_UINT (insn, 32, 30, 5); \ + f_LI_off = EXTRACT_LSB0_UINT (insn, 32, 25, 1); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_d12 = EXTRACT_LSB0_INT (insn, 32, 11, 12); \ + +#define EXTRACT_IFMT_CALLIL_VARS \ + UINT f_pack; \ + UINT f_misc_null_1; \ + UINT f_LI_on; \ + UINT f_op; \ + UINT f_GRi; \ + INT f_d12; \ + unsigned int length; +#define EXTRACT_IFMT_CALLIL_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_misc_null_1 = EXTRACT_LSB0_UINT (insn, 32, 30, 5); \ + f_LI_on = EXTRACT_LSB0_UINT (insn, 32, 25, 1); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_d12 = EXTRACT_LSB0_INT (insn, 32, 11, 12); \ + +#define EXTRACT_IFMT_CALL_VARS \ + UINT f_pack; \ + UINT f_op; \ + INT f_labelH6; \ + UINT f_labelL18; \ + INT f_label24; \ + unsigned int length; +#define EXTRACT_IFMT_CALL_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_labelH6 = EXTRACT_LSB0_INT (insn, 32, 30, 6); \ + f_labelL18 = EXTRACT_LSB0_UINT (insn, 32, 17, 18); \ +{\ + f_label24 = ((((((((f_labelH6) << (18))) | (f_labelL18))) << (2))) + (pc));\ +}\ + +#define EXTRACT_IFMT_RETT_VARS \ + UINT f_pack; \ + UINT f_misc_null_1; \ + UINT f_debug; \ + UINT f_op; \ + UINT f_rs_null; \ + UINT f_s12_null; \ + unsigned int length; +#define EXTRACT_IFMT_RETT_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_misc_null_1 = EXTRACT_LSB0_UINT (insn, 32, 30, 5); \ + f_debug = EXTRACT_LSB0_UINT (insn, 32, 25, 1); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_rs_null = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_s12_null = EXTRACT_LSB0_UINT (insn, 32, 11, 12); \ + +#define EXTRACT_IFMT_REI_VARS \ + UINT f_pack; \ + UINT f_rd_null; \ + UINT f_op; \ + UINT f_eir; \ + UINT f_s12_null; \ + unsigned int length; +#define EXTRACT_IFMT_REI_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_rd_null = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_eir = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_s12_null = EXTRACT_LSB0_UINT (insn, 32, 11, 12); \ + +#define EXTRACT_IFMT_TRA_VARS \ + UINT f_pack; \ + UINT f_int_cc; \ + UINT f_ICCi_2_null; \ + UINT f_op; \ + UINT f_GRi; \ + UINT f_misc_null_3; \ + UINT f_ope4; \ + UINT f_GRj; \ + unsigned int length; +#define EXTRACT_IFMT_TRA_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_int_cc = EXTRACT_LSB0_UINT (insn, 32, 30, 4); \ + f_ICCi_2_null = EXTRACT_LSB0_UINT (insn, 32, 26, 2); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_misc_null_3 = EXTRACT_LSB0_UINT (insn, 32, 11, 4); \ + f_ope4 = EXTRACT_LSB0_UINT (insn, 32, 7, 2); \ + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_TNO_VARS \ + UINT f_pack; \ + UINT f_int_cc; \ + UINT f_ICCi_2_null; \ + UINT f_op; \ + UINT f_GRi_null; \ + UINT f_misc_null_3; \ + UINT f_ope4; \ + UINT f_GRj_null; \ + unsigned int length; +#define EXTRACT_IFMT_TNO_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_int_cc = EXTRACT_LSB0_UINT (insn, 32, 30, 4); \ + f_ICCi_2_null = EXTRACT_LSB0_UINT (insn, 32, 26, 2); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_GRi_null = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_misc_null_3 = EXTRACT_LSB0_UINT (insn, 32, 11, 4); \ + f_ope4 = EXTRACT_LSB0_UINT (insn, 32, 7, 2); \ + f_GRj_null = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_TEQ_VARS \ + UINT f_pack; \ + UINT f_int_cc; \ + UINT f_ICCi_2; \ + UINT f_op; \ + UINT f_GRi; \ + UINT f_misc_null_3; \ + UINT f_ope4; \ + UINT f_GRj; \ + unsigned int length; +#define EXTRACT_IFMT_TEQ_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_int_cc = EXTRACT_LSB0_UINT (insn, 32, 30, 4); \ + f_ICCi_2 = EXTRACT_LSB0_UINT (insn, 32, 26, 2); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_misc_null_3 = EXTRACT_LSB0_UINT (insn, 32, 11, 4); \ + f_ope4 = EXTRACT_LSB0_UINT (insn, 32, 7, 2); \ + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_FTRA_VARS \ + UINT f_pack; \ + UINT f_flt_cc; \ + UINT f_FCCi_2_null; \ + UINT f_op; \ + UINT f_GRi; \ + UINT f_misc_null_3; \ + UINT f_ope4; \ + UINT f_GRj; \ + unsigned int length; +#define EXTRACT_IFMT_FTRA_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_flt_cc = EXTRACT_LSB0_UINT (insn, 32, 30, 4); \ + f_FCCi_2_null = EXTRACT_LSB0_UINT (insn, 32, 26, 2); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_misc_null_3 = EXTRACT_LSB0_UINT (insn, 32, 11, 4); \ + f_ope4 = EXTRACT_LSB0_UINT (insn, 32, 7, 2); \ + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_FTNO_VARS \ + UINT f_pack; \ + UINT f_flt_cc; \ + UINT f_FCCi_2_null; \ + UINT f_op; \ + UINT f_GRi_null; \ + UINT f_misc_null_3; \ + UINT f_ope4; \ + UINT f_GRj_null; \ + unsigned int length; +#define EXTRACT_IFMT_FTNO_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_flt_cc = EXTRACT_LSB0_UINT (insn, 32, 30, 4); \ + f_FCCi_2_null = EXTRACT_LSB0_UINT (insn, 32, 26, 2); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_GRi_null = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_misc_null_3 = EXTRACT_LSB0_UINT (insn, 32, 11, 4); \ + f_ope4 = EXTRACT_LSB0_UINT (insn, 32, 7, 2); \ + f_GRj_null = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_FTNE_VARS \ + UINT f_pack; \ + UINT f_flt_cc; \ + UINT f_FCCi_2; \ + UINT f_op; \ + UINT f_GRi; \ + UINT f_misc_null_3; \ + UINT f_ope4; \ + UINT f_GRj; \ + unsigned int length; +#define EXTRACT_IFMT_FTNE_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_flt_cc = EXTRACT_LSB0_UINT (insn, 32, 30, 4); \ + f_FCCi_2 = EXTRACT_LSB0_UINT (insn, 32, 26, 2); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_misc_null_3 = EXTRACT_LSB0_UINT (insn, 32, 11, 4); \ + f_ope4 = EXTRACT_LSB0_UINT (insn, 32, 7, 2); \ + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_TIRA_VARS \ + UINT f_pack; \ + UINT f_int_cc; \ + UINT f_ICCi_2_null; \ + UINT f_op; \ + UINT f_GRi; \ + INT f_d12; \ + unsigned int length; +#define EXTRACT_IFMT_TIRA_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_int_cc = EXTRACT_LSB0_UINT (insn, 32, 30, 4); \ + f_ICCi_2_null = EXTRACT_LSB0_UINT (insn, 32, 26, 2); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_d12 = EXTRACT_LSB0_INT (insn, 32, 11, 12); \ + +#define EXTRACT_IFMT_TINO_VARS \ + UINT f_pack; \ + UINT f_int_cc; \ + UINT f_ICCi_2_null; \ + UINT f_op; \ + UINT f_GRi_null; \ + UINT f_s12_null; \ + unsigned int length; +#define EXTRACT_IFMT_TINO_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_int_cc = EXTRACT_LSB0_UINT (insn, 32, 30, 4); \ + f_ICCi_2_null = EXTRACT_LSB0_UINT (insn, 32, 26, 2); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_GRi_null = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_s12_null = EXTRACT_LSB0_UINT (insn, 32, 11, 12); \ + +#define EXTRACT_IFMT_TIEQ_VARS \ + UINT f_pack; \ + UINT f_int_cc; \ + UINT f_ICCi_2; \ + UINT f_op; \ + UINT f_GRi; \ + INT f_d12; \ + unsigned int length; +#define EXTRACT_IFMT_TIEQ_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_int_cc = EXTRACT_LSB0_UINT (insn, 32, 30, 4); \ + f_ICCi_2 = EXTRACT_LSB0_UINT (insn, 32, 26, 2); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_d12 = EXTRACT_LSB0_INT (insn, 32, 11, 12); \ + +#define EXTRACT_IFMT_FTIRA_VARS \ + UINT f_pack; \ + UINT f_flt_cc; \ + UINT f_ICCi_2_null; \ + UINT f_op; \ + UINT f_GRi; \ + INT f_d12; \ + unsigned int length; +#define EXTRACT_IFMT_FTIRA_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_flt_cc = EXTRACT_LSB0_UINT (insn, 32, 30, 4); \ + f_ICCi_2_null = EXTRACT_LSB0_UINT (insn, 32, 26, 2); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_d12 = EXTRACT_LSB0_INT (insn, 32, 11, 12); \ + +#define EXTRACT_IFMT_FTINO_VARS \ + UINT f_pack; \ + UINT f_flt_cc; \ + UINT f_FCCi_2_null; \ + UINT f_op; \ + UINT f_GRi_null; \ + UINT f_s12_null; \ + unsigned int length; +#define EXTRACT_IFMT_FTINO_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_flt_cc = EXTRACT_LSB0_UINT (insn, 32, 30, 4); \ + f_FCCi_2_null = EXTRACT_LSB0_UINT (insn, 32, 26, 2); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_GRi_null = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_s12_null = EXTRACT_LSB0_UINT (insn, 32, 11, 12); \ + +#define EXTRACT_IFMT_FTINE_VARS \ + UINT f_pack; \ + UINT f_flt_cc; \ + UINT f_FCCi_2; \ + UINT f_op; \ + UINT f_GRi; \ + INT f_d12; \ + unsigned int length; +#define EXTRACT_IFMT_FTINE_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_flt_cc = EXTRACT_LSB0_UINT (insn, 32, 30, 4); \ + f_FCCi_2 = EXTRACT_LSB0_UINT (insn, 32, 26, 2); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_d12 = EXTRACT_LSB0_INT (insn, 32, 11, 12); \ + +#define EXTRACT_IFMT_BREAK_VARS \ + UINT f_pack; \ + UINT f_rd_null; \ + UINT f_op; \ + UINT f_rs_null; \ + UINT f_misc_null_3; \ + UINT f_ope4; \ + UINT f_GRj_null; \ + unsigned int length; +#define EXTRACT_IFMT_BREAK_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_rd_null = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_rs_null = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_misc_null_3 = EXTRACT_LSB0_UINT (insn, 32, 11, 4); \ + f_ope4 = EXTRACT_LSB0_UINT (insn, 32, 7, 2); \ + f_GRj_null = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_ANDCR_VARS \ + UINT f_pack; \ + UINT f_misc_null_6; \ + UINT f_CRk; \ + UINT f_op; \ + UINT f_misc_null_7; \ + UINT f_CRi; \ + UINT f_ope1; \ + UINT f_misc_null_8; \ + UINT f_CRj; \ + unsigned int length; +#define EXTRACT_IFMT_ANDCR_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_misc_null_6 = EXTRACT_LSB0_UINT (insn, 32, 30, 3); \ + f_CRk = EXTRACT_LSB0_UINT (insn, 32, 27, 3); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_misc_null_7 = EXTRACT_LSB0_UINT (insn, 32, 17, 3); \ + f_CRi = EXTRACT_LSB0_UINT (insn, 32, 14, 3); \ + f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \ + f_misc_null_8 = EXTRACT_LSB0_UINT (insn, 32, 5, 3); \ + f_CRj = EXTRACT_LSB0_UINT (insn, 32, 2, 3); \ + +#define EXTRACT_IFMT_NOTCR_VARS \ + UINT f_pack; \ + UINT f_misc_null_6; \ + UINT f_CRk; \ + UINT f_op; \ + UINT f_rs_null; \ + UINT f_ope1; \ + UINT f_misc_null_8; \ + UINT f_CRj; \ + unsigned int length; +#define EXTRACT_IFMT_NOTCR_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_misc_null_6 = EXTRACT_LSB0_UINT (insn, 32, 30, 3); \ + f_CRk = EXTRACT_LSB0_UINT (insn, 32, 27, 3); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_rs_null = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \ + f_misc_null_8 = EXTRACT_LSB0_UINT (insn, 32, 5, 3); \ + f_CRj = EXTRACT_LSB0_UINT (insn, 32, 2, 3); \ + +#define EXTRACT_IFMT_CKRA_VARS \ + UINT f_pack; \ + UINT f_int_cc; \ + SI f_CRj_int; \ + UINT f_op; \ + UINT f_misc_null_5; \ + UINT f_ICCi_3_null; \ + unsigned int length; +#define EXTRACT_IFMT_CKRA_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_int_cc = EXTRACT_LSB0_UINT (insn, 32, 30, 4); \ + f_CRj_int = ((EXTRACT_LSB0_UINT (insn, 32, 26, 2)) + (4)); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_misc_null_5 = EXTRACT_LSB0_UINT (insn, 32, 17, 16); \ + f_ICCi_3_null = EXTRACT_LSB0_UINT (insn, 32, 1, 2); \ + +#define EXTRACT_IFMT_CKEQ_VARS \ + UINT f_pack; \ + UINT f_int_cc; \ + SI f_CRj_int; \ + UINT f_op; \ + UINT f_misc_null_5; \ + UINT f_ICCi_3; \ + unsigned int length; +#define EXTRACT_IFMT_CKEQ_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_int_cc = EXTRACT_LSB0_UINT (insn, 32, 30, 4); \ + f_CRj_int = ((EXTRACT_LSB0_UINT (insn, 32, 26, 2)) + (4)); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_misc_null_5 = EXTRACT_LSB0_UINT (insn, 32, 17, 16); \ + f_ICCi_3 = EXTRACT_LSB0_UINT (insn, 32, 1, 2); \ + +#define EXTRACT_IFMT_FCKRA_VARS \ + UINT f_pack; \ + UINT f_flt_cc; \ + UINT f_CRj_float; \ + UINT f_op; \ + UINT f_misc_null_5; \ + UINT f_FCCi_3; \ + unsigned int length; +#define EXTRACT_IFMT_FCKRA_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_flt_cc = EXTRACT_LSB0_UINT (insn, 32, 30, 4); \ + f_CRj_float = EXTRACT_LSB0_UINT (insn, 32, 26, 2); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_misc_null_5 = EXTRACT_LSB0_UINT (insn, 32, 17, 16); \ + f_FCCi_3 = EXTRACT_LSB0_UINT (insn, 32, 1, 2); \ + +#define EXTRACT_IFMT_CCKRA_VARS \ + UINT f_pack; \ + UINT f_int_cc; \ + SI f_CRj_int; \ + UINT f_op; \ + UINT f_rs_null; \ + UINT f_CCi; \ + UINT f_cond; \ + UINT f_ope4; \ + UINT f_misc_null_9; \ + UINT f_ICCi_3_null; \ + unsigned int length; +#define EXTRACT_IFMT_CCKRA_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_int_cc = EXTRACT_LSB0_UINT (insn, 32, 30, 4); \ + f_CRj_int = ((EXTRACT_LSB0_UINT (insn, 32, 26, 2)) + (4)); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_rs_null = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); \ + f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); \ + f_ope4 = EXTRACT_LSB0_UINT (insn, 32, 7, 2); \ + f_misc_null_9 = EXTRACT_LSB0_UINT (insn, 32, 5, 4); \ + f_ICCi_3_null = EXTRACT_LSB0_UINT (insn, 32, 1, 2); \ + +#define EXTRACT_IFMT_CCKEQ_VARS \ + UINT f_pack; \ + UINT f_int_cc; \ + SI f_CRj_int; \ + UINT f_op; \ + UINT f_rs_null; \ + UINT f_CCi; \ + UINT f_cond; \ + UINT f_ope4; \ + UINT f_misc_null_9; \ + UINT f_ICCi_3; \ + unsigned int length; +#define EXTRACT_IFMT_CCKEQ_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_int_cc = EXTRACT_LSB0_UINT (insn, 32, 30, 4); \ + f_CRj_int = ((EXTRACT_LSB0_UINT (insn, 32, 26, 2)) + (4)); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_rs_null = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); \ + f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); \ + f_ope4 = EXTRACT_LSB0_UINT (insn, 32, 7, 2); \ + f_misc_null_9 = EXTRACT_LSB0_UINT (insn, 32, 5, 4); \ + f_ICCi_3 = EXTRACT_LSB0_UINT (insn, 32, 1, 2); \ + +#define EXTRACT_IFMT_CFCKRA_VARS \ + UINT f_pack; \ + UINT f_flt_cc; \ + UINT f_CRj_float; \ + UINT f_op; \ + UINT f_rs_null; \ + UINT f_CCi; \ + UINT f_cond; \ + UINT f_ope4; \ + UINT f_misc_null_9; \ + UINT f_FCCi_3_null; \ + unsigned int length; +#define EXTRACT_IFMT_CFCKRA_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_flt_cc = EXTRACT_LSB0_UINT (insn, 32, 30, 4); \ + f_CRj_float = EXTRACT_LSB0_UINT (insn, 32, 26, 2); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_rs_null = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); \ + f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); \ + f_ope4 = EXTRACT_LSB0_UINT (insn, 32, 7, 2); \ + f_misc_null_9 = EXTRACT_LSB0_UINT (insn, 32, 5, 4); \ + f_FCCi_3_null = EXTRACT_LSB0_UINT (insn, 32, 1, 2); \ + +#define EXTRACT_IFMT_CFCKNE_VARS \ + UINT f_pack; \ + UINT f_flt_cc; \ + UINT f_CRj_float; \ + UINT f_op; \ + UINT f_rs_null; \ + UINT f_CCi; \ + UINT f_cond; \ + UINT f_ope4; \ + UINT f_misc_null_9; \ + UINT f_FCCi_3; \ + unsigned int length; +#define EXTRACT_IFMT_CFCKNE_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_flt_cc = EXTRACT_LSB0_UINT (insn, 32, 30, 4); \ + f_CRj_float = EXTRACT_LSB0_UINT (insn, 32, 26, 2); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_rs_null = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); \ + f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); \ + f_ope4 = EXTRACT_LSB0_UINT (insn, 32, 7, 2); \ + f_misc_null_9 = EXTRACT_LSB0_UINT (insn, 32, 5, 4); \ + f_FCCi_3 = EXTRACT_LSB0_UINT (insn, 32, 1, 2); \ + +#define EXTRACT_IFMT_CJMPL_VARS \ + UINT f_pack; \ + UINT f_misc_null_1; \ + UINT f_LI_off; \ + UINT f_op; \ + UINT f_GRi; \ + UINT f_CCi; \ + UINT f_cond; \ + UINT f_ope4; \ + UINT f_GRj; \ + unsigned int length; +#define EXTRACT_IFMT_CJMPL_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_misc_null_1 = EXTRACT_LSB0_UINT (insn, 32, 30, 5); \ + f_LI_off = EXTRACT_LSB0_UINT (insn, 32, 25, 1); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); \ + f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); \ + f_ope4 = EXTRACT_LSB0_UINT (insn, 32, 7, 2); \ + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_CCALLL_VARS \ + UINT f_pack; \ + UINT f_misc_null_1; \ + UINT f_LI_on; \ + UINT f_op; \ + UINT f_GRi; \ + UINT f_CCi; \ + UINT f_cond; \ + UINT f_ope4; \ + UINT f_GRj; \ + unsigned int length; +#define EXTRACT_IFMT_CCALLL_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_misc_null_1 = EXTRACT_LSB0_UINT (insn, 32, 30, 5); \ + f_LI_on = EXTRACT_LSB0_UINT (insn, 32, 25, 1); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); \ + f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); \ + f_ope4 = EXTRACT_LSB0_UINT (insn, 32, 7, 2); \ + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_ICEI_VARS \ + UINT f_pack; \ + UINT f_misc_null_1; \ + UINT f_ae; \ + UINT f_op; \ + UINT f_GRi; \ + UINT f_ope1; \ + UINT f_GRj; \ + unsigned int length; +#define EXTRACT_IFMT_ICEI_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_misc_null_1 = EXTRACT_LSB0_UINT (insn, 32, 30, 5); \ + f_ae = EXTRACT_LSB0_UINT (insn, 32, 25, 1); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \ + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_ICPL_VARS \ + UINT f_pack; \ + UINT f_misc_null_1; \ + UINT f_lock; \ + UINT f_op; \ + UINT f_GRi; \ + UINT f_ope1; \ + UINT f_GRj; \ + unsigned int length; +#define EXTRACT_IFMT_ICPL_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_misc_null_1 = EXTRACT_LSB0_UINT (insn, 32, 30, 5); \ + f_lock = EXTRACT_LSB0_UINT (insn, 32, 25, 1); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \ + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_ICUL_VARS \ + UINT f_pack; \ + UINT f_rd_null; \ + UINT f_op; \ + UINT f_GRi; \ + UINT f_ope1; \ + UINT f_GRj_null; \ + unsigned int length; +#define EXTRACT_IFMT_ICUL_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_rd_null = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \ + f_GRj_null = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_BAR_VARS \ + UINT f_pack; \ + UINT f_rd_null; \ + UINT f_op; \ + UINT f_rs_null; \ + UINT f_ope1; \ + UINT f_GRj_null; \ + unsigned int length; +#define EXTRACT_IFMT_BAR_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_rd_null = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_rs_null = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \ + f_GRj_null = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_COP1_VARS \ + UINT f_pack; \ + UINT f_CPRk; \ + UINT f_op; \ + UINT f_CPRi; \ + INT f_s6_1; \ + UINT f_CPRj; \ + unsigned int length; +#define EXTRACT_IFMT_COP1_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_CPRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_CPRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_s6_1 = EXTRACT_LSB0_INT (insn, 32, 11, 6); \ + f_CPRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_CLRGR_VARS \ + UINT f_pack; \ + UINT f_GRk; \ + UINT f_op; \ + UINT f_rs_null; \ + UINT f_ope1; \ + UINT f_GRj_null; \ + unsigned int length; +#define EXTRACT_IFMT_CLRGR_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_rs_null = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \ + f_GRj_null = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_CLRFR_VARS \ + UINT f_pack; \ + UINT f_FRk; \ + UINT f_op; \ + UINT f_rs_null; \ + UINT f_ope1; \ + UINT f_GRj_null; \ + unsigned int length; +#define EXTRACT_IFMT_CLRFR_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_rs_null = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \ + f_GRj_null = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_FITOS_VARS \ + UINT f_pack; \ + UINT f_FRk; \ + UINT f_op; \ + UINT f_rs_null; \ + UINT f_ope1; \ + UINT f_FRj; \ + unsigned int length; +#define EXTRACT_IFMT_FITOS_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_rs_null = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \ + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_FSTOI_VARS \ + UINT f_pack; \ + UINT f_FRk; \ + UINT f_op; \ + UINT f_rs_null; \ + UINT f_ope1; \ + UINT f_FRj; \ + unsigned int length; +#define EXTRACT_IFMT_FSTOI_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_rs_null = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \ + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_FITOD_VARS \ + UINT f_pack; \ + UINT f_FRk; \ + UINT f_op; \ + UINT f_rs_null; \ + UINT f_ope1; \ + UINT f_FRj; \ + unsigned int length; +#define EXTRACT_IFMT_FITOD_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_rs_null = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \ + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_FDTOI_VARS \ + UINT f_pack; \ + UINT f_FRk; \ + UINT f_op; \ + UINT f_rs_null; \ + UINT f_ope1; \ + UINT f_FRj; \ + unsigned int length; +#define EXTRACT_IFMT_FDTOI_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_rs_null = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \ + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_CFITOS_VARS \ + UINT f_pack; \ + UINT f_FRk; \ + UINT f_op; \ + UINT f_rs_null; \ + UINT f_CCi; \ + UINT f_cond; \ + UINT f_ope4; \ + UINT f_FRj; \ + unsigned int length; +#define EXTRACT_IFMT_CFITOS_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_rs_null = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); \ + f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); \ + f_ope4 = EXTRACT_LSB0_UINT (insn, 32, 7, 2); \ + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_CFSTOI_VARS \ + UINT f_pack; \ + UINT f_FRk; \ + UINT f_op; \ + UINT f_rs_null; \ + UINT f_CCi; \ + UINT f_cond; \ + UINT f_ope4; \ + UINT f_FRj; \ + unsigned int length; +#define EXTRACT_IFMT_CFSTOI_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_rs_null = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); \ + f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); \ + f_ope4 = EXTRACT_LSB0_UINT (insn, 32, 7, 2); \ + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_FMOVS_VARS \ + UINT f_pack; \ + UINT f_FRk; \ + UINT f_op; \ + UINT f_rs_null; \ + UINT f_ope1; \ + UINT f_FRj; \ + unsigned int length; +#define EXTRACT_IFMT_FMOVS_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_rs_null = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \ + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_FMOVD_VARS \ + UINT f_pack; \ + UINT f_FRk; \ + UINT f_op; \ + UINT f_rs_null; \ + UINT f_ope1; \ + UINT f_FRj; \ + unsigned int length; +#define EXTRACT_IFMT_FMOVD_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_rs_null = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \ + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_CFMOVS_VARS \ + UINT f_pack; \ + UINT f_FRk; \ + UINT f_op; \ + UINT f_rs_null; \ + UINT f_CCi; \ + UINT f_cond; \ + UINT f_ope4; \ + UINT f_FRj; \ + unsigned int length; +#define EXTRACT_IFMT_CFMOVS_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_rs_null = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); \ + f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); \ + f_ope4 = EXTRACT_LSB0_UINT (insn, 32, 7, 2); \ + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_FADDS_VARS \ + UINT f_pack; \ + UINT f_FRk; \ + UINT f_op; \ + UINT f_FRi; \ + UINT f_ope1; \ + UINT f_FRj; \ + unsigned int length; +#define EXTRACT_IFMT_FADDS_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \ + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_FADDD_VARS \ + UINT f_pack; \ + UINT f_FRk; \ + UINT f_op; \ + UINT f_FRi; \ + UINT f_ope1; \ + UINT f_FRj; \ + unsigned int length; +#define EXTRACT_IFMT_FADDD_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \ + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_CFADDS_VARS \ + UINT f_pack; \ + UINT f_FRk; \ + UINT f_op; \ + UINT f_FRi; \ + UINT f_CCi; \ + UINT f_cond; \ + UINT f_ope4; \ + UINT f_FRj; \ + unsigned int length; +#define EXTRACT_IFMT_CFADDS_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); \ + f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); \ + f_ope4 = EXTRACT_LSB0_UINT (insn, 32, 7, 2); \ + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_FCMPS_VARS \ + UINT f_pack; \ + UINT f_cond_null; \ + UINT f_FCCi_2; \ + UINT f_op; \ + UINT f_FRi; \ + UINT f_ope1; \ + UINT f_FRj; \ + unsigned int length; +#define EXTRACT_IFMT_FCMPS_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_cond_null = EXTRACT_LSB0_UINT (insn, 32, 30, 4); \ + f_FCCi_2 = EXTRACT_LSB0_UINT (insn, 32, 26, 2); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \ + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_FCMPD_VARS \ + UINT f_pack; \ + UINT f_cond_null; \ + UINT f_FCCi_2; \ + UINT f_op; \ + UINT f_FRi; \ + UINT f_ope1; \ + UINT f_FRj; \ + unsigned int length; +#define EXTRACT_IFMT_FCMPD_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_cond_null = EXTRACT_LSB0_UINT (insn, 32, 30, 4); \ + f_FCCi_2 = EXTRACT_LSB0_UINT (insn, 32, 26, 2); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \ + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_CFCMPS_VARS \ + UINT f_pack; \ + UINT f_cond_null; \ + UINT f_FCCi_2; \ + UINT f_op; \ + UINT f_FRi; \ + UINT f_CCi; \ + UINT f_cond; \ + UINT f_ope4; \ + UINT f_FRj; \ + unsigned int length; +#define EXTRACT_IFMT_CFCMPS_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_cond_null = EXTRACT_LSB0_UINT (insn, 32, 30, 4); \ + f_FCCi_2 = EXTRACT_LSB0_UINT (insn, 32, 26, 2); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); \ + f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); \ + f_ope4 = EXTRACT_LSB0_UINT (insn, 32, 7, 2); \ + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_MHSETLOS_VARS \ + UINT f_pack; \ + UINT f_FRk; \ + UINT f_op; \ + UINT f_ope1; \ + INT f_u12_h; \ + UINT f_u12_l; \ + INT f_u12; \ + unsigned int length; +#define EXTRACT_IFMT_MHSETLOS_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \ + f_u12_h = EXTRACT_LSB0_INT (insn, 32, 17, 6); \ + f_u12_l = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ +{\ + f_u12 = ((((f_u12_h) << (6))) | (f_u12_l));\ +}\ + +#define EXTRACT_IFMT_MHSETHIS_VARS \ + UINT f_pack; \ + UINT f_FRk; \ + UINT f_op; \ + UINT f_ope1; \ + INT f_u12_h; \ + UINT f_u12_l; \ + INT f_u12; \ + unsigned int length; +#define EXTRACT_IFMT_MHSETHIS_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \ + f_u12_h = EXTRACT_LSB0_INT (insn, 32, 17, 6); \ + f_u12_l = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ +{\ + f_u12 = ((((f_u12_h) << (6))) | (f_u12_l));\ +}\ + +#define EXTRACT_IFMT_MHDSETS_VARS \ + UINT f_pack; \ + UINT f_FRk; \ + UINT f_op; \ + UINT f_ope1; \ + INT f_u12_h; \ + UINT f_u12_l; \ + INT f_u12; \ + unsigned int length; +#define EXTRACT_IFMT_MHDSETS_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \ + f_u12_h = EXTRACT_LSB0_INT (insn, 32, 17, 6); \ + f_u12_l = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ +{\ + f_u12 = ((((f_u12_h) << (6))) | (f_u12_l));\ +}\ + +#define EXTRACT_IFMT_MHSETLOH_VARS \ + UINT f_pack; \ + UINT f_FRk; \ + UINT f_op; \ + UINT f_FRi_null; \ + UINT f_ope1; \ + UINT f_misc_null_11; \ + INT f_s5; \ + unsigned int length; +#define EXTRACT_IFMT_MHSETLOH_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_FRi_null = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \ + f_misc_null_11 = EXTRACT_LSB0_UINT (insn, 32, 5, 1); \ + f_s5 = EXTRACT_LSB0_INT (insn, 32, 4, 5); \ + +#define EXTRACT_IFMT_MHSETHIH_VARS \ + UINT f_pack; \ + UINT f_FRk; \ + UINT f_op; \ + UINT f_FRi_null; \ + UINT f_ope1; \ + UINT f_misc_null_11; \ + INT f_s5; \ + unsigned int length; +#define EXTRACT_IFMT_MHSETHIH_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_FRi_null = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \ + f_misc_null_11 = EXTRACT_LSB0_UINT (insn, 32, 5, 1); \ + f_s5 = EXTRACT_LSB0_INT (insn, 32, 4, 5); \ + +#define EXTRACT_IFMT_MHDSETH_VARS \ + UINT f_pack; \ + UINT f_FRk; \ + UINT f_op; \ + UINT f_FRi_null; \ + UINT f_ope1; \ + UINT f_misc_null_11; \ + INT f_s5; \ + unsigned int length; +#define EXTRACT_IFMT_MHDSETH_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_FRi_null = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \ + f_misc_null_11 = EXTRACT_LSB0_UINT (insn, 32, 5, 1); \ + f_s5 = EXTRACT_LSB0_INT (insn, 32, 4, 5); \ + +#define EXTRACT_IFMT_MAND_VARS \ + UINT f_pack; \ + UINT f_FRk; \ + UINT f_op; \ + UINT f_FRi; \ + UINT f_ope1; \ + UINT f_FRj; \ + unsigned int length; +#define EXTRACT_IFMT_MAND_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \ + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_CMAND_VARS \ + UINT f_pack; \ + UINT f_FRk; \ + UINT f_op; \ + UINT f_FRi; \ + UINT f_CCi; \ + UINT f_cond; \ + UINT f_ope4; \ + UINT f_FRj; \ + unsigned int length; +#define EXTRACT_IFMT_CMAND_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); \ + f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); \ + f_ope4 = EXTRACT_LSB0_UINT (insn, 32, 7, 2); \ + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_MNOT_VARS \ + UINT f_pack; \ + UINT f_FRk; \ + UINT f_op; \ + UINT f_rs_null; \ + UINT f_ope1; \ + UINT f_FRj; \ + unsigned int length; +#define EXTRACT_IFMT_MNOT_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_rs_null = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \ + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_CMNOT_VARS \ + UINT f_pack; \ + UINT f_FRk; \ + UINT f_op; \ + UINT f_rs_null; \ + UINT f_CCi; \ + UINT f_cond; \ + UINT f_ope4; \ + UINT f_FRj; \ + unsigned int length; +#define EXTRACT_IFMT_CMNOT_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_rs_null = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); \ + f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); \ + f_ope4 = EXTRACT_LSB0_UINT (insn, 32, 7, 2); \ + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_MROTLI_VARS \ + UINT f_pack; \ + UINT f_FRk; \ + UINT f_op; \ + UINT f_FRi; \ + UINT f_ope1; \ + UINT f_u6; \ + unsigned int length; +#define EXTRACT_IFMT_MROTLI_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \ + f_u6 = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_MCUT_VARS \ + UINT f_pack; \ + UINT f_FRk; \ + UINT f_op; \ + UINT f_ACC40Si; \ + UINT f_ope1; \ + UINT f_FRj; \ + unsigned int length; +#define EXTRACT_IFMT_MCUT_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_ACC40Si = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \ + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_MCUTI_VARS \ + UINT f_pack; \ + UINT f_FRk; \ + UINT f_op; \ + UINT f_ACC40Si; \ + UINT f_ope1; \ + INT f_s6; \ + unsigned int length; +#define EXTRACT_IFMT_MCUTI_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_ACC40Si = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \ + f_s6 = EXTRACT_LSB0_INT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_MDCUTSSI_VARS \ + UINT f_pack; \ + UINT f_FRk; \ + UINT f_op; \ + UINT f_ACC40Si; \ + UINT f_ope1; \ + INT f_s6; \ + unsigned int length; +#define EXTRACT_IFMT_MDCUTSSI_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_ACC40Si = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \ + f_s6 = EXTRACT_LSB0_INT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_MDROTLI_VARS \ + UINT f_pack; \ + UINT f_FRk; \ + UINT f_op; \ + UINT f_FRi; \ + UINT f_ope1; \ + INT f_s6; \ + unsigned int length; +#define EXTRACT_IFMT_MDROTLI_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \ + f_s6 = EXTRACT_LSB0_INT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_MQSATHS_VARS \ + UINT f_pack; \ + UINT f_FRk; \ + UINT f_op; \ + UINT f_FRi; \ + UINT f_ope1; \ + UINT f_FRj; \ + unsigned int length; +#define EXTRACT_IFMT_MQSATHS_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \ + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_MCMPSH_VARS \ + UINT f_pack; \ + UINT f_cond_null; \ + UINT f_FCCk; \ + UINT f_op; \ + UINT f_FRi; \ + UINT f_ope1; \ + UINT f_FRj; \ + unsigned int length; +#define EXTRACT_IFMT_MCMPSH_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_cond_null = EXTRACT_LSB0_UINT (insn, 32, 30, 4); \ + f_FCCk = EXTRACT_LSB0_UINT (insn, 32, 26, 2); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \ + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_MABSHS_VARS \ + UINT f_pack; \ + UINT f_FRk; \ + UINT f_op; \ + UINT f_FRi_null; \ + UINT f_ope1; \ + UINT f_FRj; \ + unsigned int length; +#define EXTRACT_IFMT_MABSHS_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_FRi_null = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \ + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_CMQADDHSS_VARS \ + UINT f_pack; \ + UINT f_FRk; \ + UINT f_op; \ + UINT f_FRi; \ + UINT f_CCi; \ + UINT f_cond; \ + UINT f_ope4; \ + UINT f_FRj; \ + unsigned int length; +#define EXTRACT_IFMT_CMQADDHSS_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); \ + f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); \ + f_ope4 = EXTRACT_LSB0_UINT (insn, 32, 7, 2); \ + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_MADDACCS_VARS \ + UINT f_pack; \ + UINT f_ACC40Sk; \ + UINT f_op; \ + UINT f_ACC40Si; \ + UINT f_ope1; \ + UINT f_ACCj_null; \ + unsigned int length; +#define EXTRACT_IFMT_MADDACCS_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_ACC40Sk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_ACC40Si = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \ + f_ACCj_null = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_MMULHS_VARS \ + UINT f_pack; \ + UINT f_ACC40Sk; \ + UINT f_op; \ + UINT f_FRi; \ + UINT f_ope1; \ + UINT f_FRj; \ + unsigned int length; +#define EXTRACT_IFMT_MMULHS_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_ACC40Sk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \ + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_CMMULHS_VARS \ + UINT f_pack; \ + UINT f_ACC40Sk; \ + UINT f_op; \ + UINT f_FRi; \ + UINT f_CCi; \ + UINT f_cond; \ + UINT f_ope4; \ + UINT f_FRj; \ + unsigned int length; +#define EXTRACT_IFMT_CMMULHS_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_ACC40Sk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); \ + f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); \ + f_ope4 = EXTRACT_LSB0_UINT (insn, 32, 7, 2); \ + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_MQMULHS_VARS \ + UINT f_pack; \ + UINT f_ACC40Sk; \ + UINT f_op; \ + UINT f_FRi; \ + UINT f_ope1; \ + UINT f_FRj; \ + unsigned int length; +#define EXTRACT_IFMT_MQMULHS_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_ACC40Sk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \ + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_CMQMULHS_VARS \ + UINT f_pack; \ + UINT f_ACC40Sk; \ + UINT f_op; \ + UINT f_FRi; \ + UINT f_CCi; \ + UINT f_cond; \ + UINT f_ope4; \ + UINT f_FRj; \ + unsigned int length; +#define EXTRACT_IFMT_CMQMULHS_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_ACC40Sk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); \ + f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); \ + f_ope4 = EXTRACT_LSB0_UINT (insn, 32, 7, 2); \ + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_MMACHU_VARS \ + UINT f_pack; \ + UINT f_ACC40Uk; \ + UINT f_op; \ + UINT f_FRi; \ + UINT f_ope1; \ + UINT f_FRj; \ + unsigned int length; +#define EXTRACT_IFMT_MMACHU_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_ACC40Uk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \ + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_CMMACHU_VARS \ + UINT f_pack; \ + UINT f_ACC40Uk; \ + UINT f_op; \ + UINT f_FRi; \ + UINT f_CCi; \ + UINT f_cond; \ + UINT f_ope4; \ + UINT f_FRj; \ + unsigned int length; +#define EXTRACT_IFMT_CMMACHU_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_ACC40Uk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); \ + f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); \ + f_ope4 = EXTRACT_LSB0_UINT (insn, 32, 7, 2); \ + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_MQMACHU_VARS \ + UINT f_pack; \ + UINT f_ACC40Uk; \ + UINT f_op; \ + UINT f_FRi; \ + UINT f_ope1; \ + UINT f_FRj; \ + unsigned int length; +#define EXTRACT_IFMT_MQMACHU_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_ACC40Uk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \ + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_CMQMACHU_VARS \ + UINT f_pack; \ + UINT f_ACC40Uk; \ + UINT f_op; \ + UINT f_FRi; \ + UINT f_CCi; \ + UINT f_cond; \ + UINT f_ope4; \ + UINT f_FRj; \ + unsigned int length; +#define EXTRACT_IFMT_CMQMACHU_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_ACC40Uk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); \ + f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); \ + f_ope4 = EXTRACT_LSB0_UINT (insn, 32, 7, 2); \ + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_CMEXPDHW_VARS \ + UINT f_pack; \ + UINT f_FRk; \ + UINT f_op; \ + UINT f_FRi; \ + UINT f_CCi; \ + UINT f_cond; \ + UINT f_ope4; \ + UINT f_u6; \ + unsigned int length; +#define EXTRACT_IFMT_CMEXPDHW_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); \ + f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); \ + f_ope4 = EXTRACT_LSB0_UINT (insn, 32, 7, 2); \ + f_u6 = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_MEXPDHD_VARS \ + UINT f_pack; \ + UINT f_FRk; \ + UINT f_op; \ + UINT f_FRi; \ + UINT f_ope1; \ + UINT f_u6; \ + unsigned int length; +#define EXTRACT_IFMT_MEXPDHD_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \ + f_u6 = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_CMEXPDHD_VARS \ + UINT f_pack; \ + UINT f_FRk; \ + UINT f_op; \ + UINT f_FRi; \ + UINT f_CCi; \ + UINT f_cond; \ + UINT f_ope4; \ + UINT f_u6; \ + unsigned int length; +#define EXTRACT_IFMT_CMEXPDHD_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); \ + f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); \ + f_ope4 = EXTRACT_LSB0_UINT (insn, 32, 7, 2); \ + f_u6 = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_MUNPACKH_VARS \ + UINT f_pack; \ + UINT f_FRk; \ + UINT f_op; \ + UINT f_FRi; \ + UINT f_ope1; \ + UINT f_FRj_null; \ + unsigned int length; +#define EXTRACT_IFMT_MUNPACKH_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \ + f_FRj_null = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_MDUNPACKH_VARS \ + UINT f_pack; \ + UINT f_FRk; \ + UINT f_op; \ + UINT f_FRi; \ + UINT f_ope1; \ + UINT f_FRj_null; \ + unsigned int length; +#define EXTRACT_IFMT_MDUNPACKH_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \ + f_FRj_null = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_MBTOH_VARS \ + UINT f_pack; \ + UINT f_FRk; \ + UINT f_op; \ + UINT f_FRi_null; \ + UINT f_ope1; \ + UINT f_FRj; \ + unsigned int length; +#define EXTRACT_IFMT_MBTOH_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_FRi_null = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \ + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_CMBTOH_VARS \ + UINT f_pack; \ + UINT f_FRk; \ + UINT f_op; \ + UINT f_FRi_null; \ + UINT f_CCi; \ + UINT f_cond; \ + UINT f_ope4; \ + UINT f_FRj; \ + unsigned int length; +#define EXTRACT_IFMT_CMBTOH_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_FRi_null = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); \ + f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); \ + f_ope4 = EXTRACT_LSB0_UINT (insn, 32, 7, 2); \ + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_MHTOB_VARS \ + UINT f_pack; \ + UINT f_FRk; \ + UINT f_op; \ + UINT f_FRi_null; \ + UINT f_ope1; \ + UINT f_FRj; \ + unsigned int length; +#define EXTRACT_IFMT_MHTOB_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_FRi_null = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \ + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_CMHTOB_VARS \ + UINT f_pack; \ + UINT f_FRk; \ + UINT f_op; \ + UINT f_FRi_null; \ + UINT f_CCi; \ + UINT f_cond; \ + UINT f_ope4; \ + UINT f_FRj; \ + unsigned int length; +#define EXTRACT_IFMT_CMHTOB_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_FRi_null = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); \ + f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); \ + f_ope4 = EXTRACT_LSB0_UINT (insn, 32, 7, 2); \ + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_CMBTOHE_VARS \ + UINT f_pack; \ + UINT f_FRk; \ + UINT f_op; \ + UINT f_FRi_null; \ + UINT f_CCi; \ + UINT f_cond; \ + UINT f_ope4; \ + UINT f_FRj; \ + unsigned int length; +#define EXTRACT_IFMT_CMBTOHE_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_FRi_null = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); \ + f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); \ + f_ope4 = EXTRACT_LSB0_UINT (insn, 32, 7, 2); \ + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_MNOP_VARS \ + UINT f_pack; \ + UINT f_ACC40Sk; \ + UINT f_op; \ + UINT f_A; \ + UINT f_misc_null_10; \ + UINT f_ope1; \ + UINT f_FRj_null; \ + unsigned int length; +#define EXTRACT_IFMT_MNOP_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_ACC40Sk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_A = EXTRACT_LSB0_UINT (insn, 32, 17, 1); \ + f_misc_null_10 = EXTRACT_LSB0_UINT (insn, 32, 16, 5); \ + f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \ + f_FRj_null = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_MCLRACC_0_VARS \ + UINT f_pack; \ + UINT f_ACC40Sk; \ + UINT f_op; \ + UINT f_A; \ + UINT f_misc_null_10; \ + UINT f_ope1; \ + UINT f_FRj_null; \ + unsigned int length; +#define EXTRACT_IFMT_MCLRACC_0_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_ACC40Sk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_A = EXTRACT_LSB0_UINT (insn, 32, 17, 1); \ + f_misc_null_10 = EXTRACT_LSB0_UINT (insn, 32, 16, 5); \ + f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \ + f_FRj_null = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_MRDACC_VARS \ + UINT f_pack; \ + UINT f_FRk; \ + UINT f_op; \ + UINT f_ACC40Si; \ + UINT f_ope1; \ + UINT f_FRj_null; \ + unsigned int length; +#define EXTRACT_IFMT_MRDACC_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_ACC40Si = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \ + f_FRj_null = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_MRDACCG_VARS \ + UINT f_pack; \ + UINT f_FRk; \ + UINT f_op; \ + UINT f_ACCGi; \ + UINT f_ope1; \ + UINT f_FRj_null; \ + unsigned int length; +#define EXTRACT_IFMT_MRDACCG_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_ACCGi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \ + f_FRj_null = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_MWTACC_VARS \ + UINT f_pack; \ + UINT f_ACC40Sk; \ + UINT f_op; \ + UINT f_FRi; \ + UINT f_ope1; \ + UINT f_FRj_null; \ + unsigned int length; +#define EXTRACT_IFMT_MWTACC_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_ACC40Sk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \ + f_FRj_null = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_MWTACCG_VARS \ + UINT f_pack; \ + UINT f_ACCGk; \ + UINT f_op; \ + UINT f_FRi; \ + UINT f_ope1; \ + UINT f_FRj_null; \ + unsigned int length; +#define EXTRACT_IFMT_MWTACCG_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_ACCGk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \ + f_FRj_null = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_FNOP_VARS \ + UINT f_pack; \ + UINT f_rd_null; \ + UINT f_op; \ + UINT f_FRi_null; \ + UINT f_ope1; \ + UINT f_FRj_null; \ + unsigned int length; +#define EXTRACT_IFMT_FNOP_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_rd_null = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_FRi_null = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \ + f_FRj_null = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +/* Collection of various things for the trace handler to use. */ + +typedef struct trace_record { + IADDR pc; + /* FIXME:wip */ +} TRACE_RECORD; + +#endif /* CPU_FRVBF_H */ diff --git a/sim/frv/cpuall.h b/sim/frv/cpuall.h new file mode 100644 index 0000000..4d1cb68 --- /dev/null +++ b/sim/frv/cpuall.h @@ -0,0 +1,71 @@ +/* Simulator CPU header for frv. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. + +This file is part of the GNU simulators. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +*/ + +#ifndef FRV_CPUALL_H +#define FRV_CPUALL_H + +/* Include files for each cpu family. */ + +#ifdef WANT_CPU_FRVBF +#include "eng.h" +#include "cgen-engine.h" +#include "cpu.h" +#include "decode.h" +#endif + +extern const MACH frv_mach; +extern const MACH fr550_mach; +extern const MACH fr500_mach; +extern const MACH tomcat_mach; +extern const MACH fr400_mach; +extern const MACH simple_mach; + +#ifndef WANT_CPU +/* The ARGBUF struct. */ +struct argbuf { + /* These are the baseclass definitions. */ + IADDR addr; + const IDESC *idesc; + char trace_p; + char profile_p; + /* ??? Temporary hack for skip insns. */ + char skip_count; + char unused; + /* cpu specific data follows */ +}; +#endif + +#ifndef WANT_CPU +/* A cached insn. + + ??? SCACHE used to contain more than just argbuf. We could delete the + type entirely and always just use ARGBUF, but for future concerns and as + a level of abstraction it is left in. */ + +struct scache { + struct argbuf argbuf; +}; +#endif + +#endif /* FRV_CPUALL_H */ diff --git a/sim/frv/decode.c b/sim/frv/decode.c new file mode 100644 index 0000000..ef6be5a --- /dev/null +++ b/sim/frv/decode.c @@ -0,0 +1,11097 @@ +/* Simulator instruction decoder for frvbf. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. + +This file is part of the GNU simulators. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +*/ + +#define WANT_CPU frvbf +#define WANT_CPU_FRVBF + +#include "sim-main.h" +#include "sim-assert.h" + +/* The instruction descriptor array. + This is computed at runtime. Space for it is not malloc'd to save a + teensy bit of cpu in the decoder. Moving it to malloc space is trivial + but won't be done until necessary (we don't currently support the runtime + addition of instructions nor an SMP machine with different cpus). */ +static IDESC frvbf_insn_data[FRVBF_INSN__MAX]; + +/* Commas between elements are contained in the macros. + Some of these are conditionally compiled out. */ + +static const struct insn_sem frvbf_insn_sem[] = +{ + { VIRTUAL_INSN_X_INVALID, FRVBF_INSN_X_INVALID, FRVBF_SFMT_EMPTY }, + { VIRTUAL_INSN_X_AFTER, FRVBF_INSN_X_AFTER, FRVBF_SFMT_EMPTY }, + { VIRTUAL_INSN_X_BEFORE, FRVBF_INSN_X_BEFORE, FRVBF_SFMT_EMPTY }, + { VIRTUAL_INSN_X_CTI_CHAIN, FRVBF_INSN_X_CTI_CHAIN, FRVBF_SFMT_EMPTY }, + { VIRTUAL_INSN_X_CHAIN, FRVBF_INSN_X_CHAIN, FRVBF_SFMT_EMPTY }, + { VIRTUAL_INSN_X_BEGIN, FRVBF_INSN_X_BEGIN, FRVBF_SFMT_EMPTY }, + { FRV_INSN_ADD, FRVBF_INSN_ADD, FRVBF_SFMT_ADD }, + { FRV_INSN_SUB, FRVBF_INSN_SUB, FRVBF_SFMT_ADD }, + { FRV_INSN_AND, FRVBF_INSN_AND, FRVBF_SFMT_ADD }, + { FRV_INSN_OR, FRVBF_INSN_OR, FRVBF_SFMT_ADD }, + { FRV_INSN_XOR, FRVBF_INSN_XOR, FRVBF_SFMT_ADD }, + { FRV_INSN_NOT, FRVBF_INSN_NOT, FRVBF_SFMT_NOT }, + { FRV_INSN_SDIV, FRVBF_INSN_SDIV, FRVBF_SFMT_SDIV }, + { FRV_INSN_NSDIV, FRVBF_INSN_NSDIV, FRVBF_SFMT_SDIV }, + { FRV_INSN_UDIV, FRVBF_INSN_UDIV, FRVBF_SFMT_SDIV }, + { FRV_INSN_NUDIV, FRVBF_INSN_NUDIV, FRVBF_SFMT_SDIV }, + { FRV_INSN_SMUL, FRVBF_INSN_SMUL, FRVBF_SFMT_SMUL }, + { FRV_INSN_UMUL, FRVBF_INSN_UMUL, FRVBF_SFMT_SMUL }, + { FRV_INSN_SMU, FRVBF_INSN_SMU, FRVBF_SFMT_SMU }, + { FRV_INSN_SMASS, FRVBF_INSN_SMASS, FRVBF_SFMT_SMASS }, + { FRV_INSN_SMSSS, FRVBF_INSN_SMSSS, FRVBF_SFMT_SMASS }, + { FRV_INSN_SLL, FRVBF_INSN_SLL, FRVBF_SFMT_ADD }, + { FRV_INSN_SRL, FRVBF_INSN_SRL, FRVBF_SFMT_ADD }, + { FRV_INSN_SRA, FRVBF_INSN_SRA, FRVBF_SFMT_ADD }, + { FRV_INSN_SLASS, FRVBF_INSN_SLASS, FRVBF_SFMT_ADD }, + { FRV_INSN_SCUTSS, FRVBF_INSN_SCUTSS, FRVBF_SFMT_SCUTSS }, + { FRV_INSN_SCAN, FRVBF_INSN_SCAN, FRVBF_SFMT_ADD }, + { FRV_INSN_CADD, FRVBF_INSN_CADD, FRVBF_SFMT_CADD }, + { FRV_INSN_CSUB, FRVBF_INSN_CSUB, FRVBF_SFMT_CADD }, + { FRV_INSN_CAND, FRVBF_INSN_CAND, FRVBF_SFMT_CADD }, + { FRV_INSN_COR, FRVBF_INSN_COR, FRVBF_SFMT_CADD }, + { FRV_INSN_CXOR, FRVBF_INSN_CXOR, FRVBF_SFMT_CADD }, + { FRV_INSN_CNOT, FRVBF_INSN_CNOT, FRVBF_SFMT_CNOT }, + { FRV_INSN_CSMUL, FRVBF_INSN_CSMUL, FRVBF_SFMT_CSMUL }, + { FRV_INSN_CSDIV, FRVBF_INSN_CSDIV, FRVBF_SFMT_CSDIV }, + { FRV_INSN_CUDIV, FRVBF_INSN_CUDIV, FRVBF_SFMT_CSDIV }, + { FRV_INSN_CSLL, FRVBF_INSN_CSLL, FRVBF_SFMT_CADD }, + { FRV_INSN_CSRL, FRVBF_INSN_CSRL, FRVBF_SFMT_CADD }, + { FRV_INSN_CSRA, FRVBF_INSN_CSRA, FRVBF_SFMT_CADD }, + { FRV_INSN_CSCAN, FRVBF_INSN_CSCAN, FRVBF_SFMT_CADD }, + { FRV_INSN_ADDCC, FRVBF_INSN_ADDCC, FRVBF_SFMT_ADDCC }, + { FRV_INSN_SUBCC, FRVBF_INSN_SUBCC, FRVBF_SFMT_ADDCC }, + { FRV_INSN_ANDCC, FRVBF_INSN_ANDCC, FRVBF_SFMT_ANDCC }, + { FRV_INSN_ORCC, FRVBF_INSN_ORCC, FRVBF_SFMT_ANDCC }, + { FRV_INSN_XORCC, FRVBF_INSN_XORCC, FRVBF_SFMT_ANDCC }, + { FRV_INSN_SLLCC, FRVBF_INSN_SLLCC, FRVBF_SFMT_ADDCC }, + { FRV_INSN_SRLCC, FRVBF_INSN_SRLCC, FRVBF_SFMT_ADDCC }, + { FRV_INSN_SRACC, FRVBF_INSN_SRACC, FRVBF_SFMT_ADDCC }, + { FRV_INSN_SMULCC, FRVBF_INSN_SMULCC, FRVBF_SFMT_SMULCC }, + { FRV_INSN_UMULCC, FRVBF_INSN_UMULCC, FRVBF_SFMT_SMULCC }, + { FRV_INSN_CADDCC, FRVBF_INSN_CADDCC, FRVBF_SFMT_CADDCC }, + { FRV_INSN_CSUBCC, FRVBF_INSN_CSUBCC, FRVBF_SFMT_CADDCC }, + { FRV_INSN_CSMULCC, FRVBF_INSN_CSMULCC, FRVBF_SFMT_CSMULCC }, + { FRV_INSN_CANDCC, FRVBF_INSN_CANDCC, FRVBF_SFMT_CADDCC }, + { FRV_INSN_CORCC, FRVBF_INSN_CORCC, FRVBF_SFMT_CADDCC }, + { FRV_INSN_CXORCC, FRVBF_INSN_CXORCC, FRVBF_SFMT_CADDCC }, + { FRV_INSN_CSLLCC, FRVBF_INSN_CSLLCC, FRVBF_SFMT_CADDCC }, + { FRV_INSN_CSRLCC, FRVBF_INSN_CSRLCC, FRVBF_SFMT_CADDCC }, + { FRV_INSN_CSRACC, FRVBF_INSN_CSRACC, FRVBF_SFMT_CADDCC }, + { FRV_INSN_ADDX, FRVBF_INSN_ADDX, FRVBF_SFMT_ADDX }, + { FRV_INSN_SUBX, FRVBF_INSN_SUBX, FRVBF_SFMT_ADDX }, + { FRV_INSN_ADDXCC, FRVBF_INSN_ADDXCC, FRVBF_SFMT_ADDCC }, + { FRV_INSN_SUBXCC, FRVBF_INSN_SUBXCC, FRVBF_SFMT_ADDCC }, + { FRV_INSN_ADDSS, FRVBF_INSN_ADDSS, FRVBF_SFMT_ADD }, + { FRV_INSN_SUBSS, FRVBF_INSN_SUBSS, FRVBF_SFMT_ADD }, + { FRV_INSN_ADDI, FRVBF_INSN_ADDI, FRVBF_SFMT_ADDI }, + { FRV_INSN_SUBI, FRVBF_INSN_SUBI, FRVBF_SFMT_ADDI }, + { FRV_INSN_ANDI, FRVBF_INSN_ANDI, FRVBF_SFMT_ADDI }, + { FRV_INSN_ORI, FRVBF_INSN_ORI, FRVBF_SFMT_ADDI }, + { FRV_INSN_XORI, FRVBF_INSN_XORI, FRVBF_SFMT_ADDI }, + { FRV_INSN_SDIVI, FRVBF_INSN_SDIVI, FRVBF_SFMT_SDIVI }, + { FRV_INSN_NSDIVI, FRVBF_INSN_NSDIVI, FRVBF_SFMT_SDIVI }, + { FRV_INSN_UDIVI, FRVBF_INSN_UDIVI, FRVBF_SFMT_SDIVI }, + { FRV_INSN_NUDIVI, FRVBF_INSN_NUDIVI, FRVBF_SFMT_SDIVI }, + { FRV_INSN_SMULI, FRVBF_INSN_SMULI, FRVBF_SFMT_SMULI }, + { FRV_INSN_UMULI, FRVBF_INSN_UMULI, FRVBF_SFMT_SMULI }, + { FRV_INSN_SLLI, FRVBF_INSN_SLLI, FRVBF_SFMT_ADDI }, + { FRV_INSN_SRLI, FRVBF_INSN_SRLI, FRVBF_SFMT_ADDI }, + { FRV_INSN_SRAI, FRVBF_INSN_SRAI, FRVBF_SFMT_ADDI }, + { FRV_INSN_SCANI, FRVBF_INSN_SCANI, FRVBF_SFMT_ADDI }, + { FRV_INSN_ADDICC, FRVBF_INSN_ADDICC, FRVBF_SFMT_ADDICC }, + { FRV_INSN_SUBICC, FRVBF_INSN_SUBICC, FRVBF_SFMT_ADDICC }, + { FRV_INSN_ANDICC, FRVBF_INSN_ANDICC, FRVBF_SFMT_ANDICC }, + { FRV_INSN_ORICC, FRVBF_INSN_ORICC, FRVBF_SFMT_ANDICC }, + { FRV_INSN_XORICC, FRVBF_INSN_XORICC, FRVBF_SFMT_ANDICC }, + { FRV_INSN_SMULICC, FRVBF_INSN_SMULICC, FRVBF_SFMT_SMULICC }, + { FRV_INSN_UMULICC, FRVBF_INSN_UMULICC, FRVBF_SFMT_SMULICC }, + { FRV_INSN_SLLICC, FRVBF_INSN_SLLICC, FRVBF_SFMT_ADDICC }, + { FRV_INSN_SRLICC, FRVBF_INSN_SRLICC, FRVBF_SFMT_ADDICC }, + { FRV_INSN_SRAICC, FRVBF_INSN_SRAICC, FRVBF_SFMT_ADDICC }, + { FRV_INSN_ADDXI, FRVBF_INSN_ADDXI, FRVBF_SFMT_ADDXI }, + { FRV_INSN_SUBXI, FRVBF_INSN_SUBXI, FRVBF_SFMT_ADDXI }, + { FRV_INSN_ADDXICC, FRVBF_INSN_ADDXICC, FRVBF_SFMT_ADDICC }, + { FRV_INSN_SUBXICC, FRVBF_INSN_SUBXICC, FRVBF_SFMT_ADDICC }, + { FRV_INSN_CMPB, FRVBF_INSN_CMPB, FRVBF_SFMT_CMPB }, + { FRV_INSN_CMPBA, FRVBF_INSN_CMPBA, FRVBF_SFMT_CMPB }, + { FRV_INSN_SETLO, FRVBF_INSN_SETLO, FRVBF_SFMT_SETLO }, + { FRV_INSN_SETHI, FRVBF_INSN_SETHI, FRVBF_SFMT_SETHI }, + { FRV_INSN_SETLOS, FRVBF_INSN_SETLOS, FRVBF_SFMT_SETLOS }, + { FRV_INSN_LDSB, FRVBF_INSN_LDSB, FRVBF_SFMT_LDSB }, + { FRV_INSN_LDUB, FRVBF_INSN_LDUB, FRVBF_SFMT_LDSB }, + { FRV_INSN_LDSH, FRVBF_INSN_LDSH, FRVBF_SFMT_LDSB }, + { FRV_INSN_LDUH, FRVBF_INSN_LDUH, FRVBF_SFMT_LDSB }, + { FRV_INSN_LD, FRVBF_INSN_LD, FRVBF_SFMT_LDSB }, + { FRV_INSN_LDBF, FRVBF_INSN_LDBF, FRVBF_SFMT_LDBF }, + { FRV_INSN_LDHF, FRVBF_INSN_LDHF, FRVBF_SFMT_LDBF }, + { FRV_INSN_LDF, FRVBF_INSN_LDF, FRVBF_SFMT_LDBF }, + { FRV_INSN_LDC, FRVBF_INSN_LDC, FRVBF_SFMT_LDC }, + { FRV_INSN_NLDSB, FRVBF_INSN_NLDSB, FRVBF_SFMT_NLDSB }, + { FRV_INSN_NLDUB, FRVBF_INSN_NLDUB, FRVBF_SFMT_NLDSB }, + { FRV_INSN_NLDSH, FRVBF_INSN_NLDSH, FRVBF_SFMT_NLDSB }, + { FRV_INSN_NLDUH, FRVBF_INSN_NLDUH, FRVBF_SFMT_NLDSB }, + { FRV_INSN_NLD, FRVBF_INSN_NLD, FRVBF_SFMT_NLDSB }, + { FRV_INSN_NLDBF, FRVBF_INSN_NLDBF, FRVBF_SFMT_NLDBF }, + { FRV_INSN_NLDHF, FRVBF_INSN_NLDHF, FRVBF_SFMT_NLDBF }, + { FRV_INSN_NLDF, FRVBF_INSN_NLDF, FRVBF_SFMT_NLDBF }, + { FRV_INSN_LDD, FRVBF_INSN_LDD, FRVBF_SFMT_LDD }, + { FRV_INSN_LDDF, FRVBF_INSN_LDDF, FRVBF_SFMT_LDDF }, + { FRV_INSN_LDDC, FRVBF_INSN_LDDC, FRVBF_SFMT_LDDC }, + { FRV_INSN_NLDD, FRVBF_INSN_NLDD, FRVBF_SFMT_NLDD }, + { FRV_INSN_NLDDF, FRVBF_INSN_NLDDF, FRVBF_SFMT_NLDDF }, + { FRV_INSN_LDQ, FRVBF_INSN_LDQ, FRVBF_SFMT_LDQ }, + { FRV_INSN_LDQF, FRVBF_INSN_LDQF, FRVBF_SFMT_LDQF }, + { FRV_INSN_LDQC, FRVBF_INSN_LDQC, FRVBF_SFMT_LDQC }, + { FRV_INSN_NLDQ, FRVBF_INSN_NLDQ, FRVBF_SFMT_NLDQ }, + { FRV_INSN_NLDQF, FRVBF_INSN_NLDQF, FRVBF_SFMT_NLDQF }, + { FRV_INSN_LDSBU, FRVBF_INSN_LDSBU, FRVBF_SFMT_LDSBU }, + { FRV_INSN_LDUBU, FRVBF_INSN_LDUBU, FRVBF_SFMT_LDSBU }, + { FRV_INSN_LDSHU, FRVBF_INSN_LDSHU, FRVBF_SFMT_LDSBU }, + { FRV_INSN_LDUHU, FRVBF_INSN_LDUHU, FRVBF_SFMT_LDSBU }, + { FRV_INSN_LDU, FRVBF_INSN_LDU, FRVBF_SFMT_LDSBU }, + { FRV_INSN_NLDSBU, FRVBF_INSN_NLDSBU, FRVBF_SFMT_NLDSBU }, + { FRV_INSN_NLDUBU, FRVBF_INSN_NLDUBU, FRVBF_SFMT_NLDSBU }, + { FRV_INSN_NLDSHU, FRVBF_INSN_NLDSHU, FRVBF_SFMT_NLDSBU }, + { FRV_INSN_NLDUHU, FRVBF_INSN_NLDUHU, FRVBF_SFMT_NLDSBU }, + { FRV_INSN_NLDU, FRVBF_INSN_NLDU, FRVBF_SFMT_NLDSBU }, + { FRV_INSN_LDBFU, FRVBF_INSN_LDBFU, FRVBF_SFMT_LDBFU }, + { FRV_INSN_LDHFU, FRVBF_INSN_LDHFU, FRVBF_SFMT_LDBFU }, + { FRV_INSN_LDFU, FRVBF_INSN_LDFU, FRVBF_SFMT_LDBFU }, + { FRV_INSN_LDCU, FRVBF_INSN_LDCU, FRVBF_SFMT_LDCU }, + { FRV_INSN_NLDBFU, FRVBF_INSN_NLDBFU, FRVBF_SFMT_NLDBFU }, + { FRV_INSN_NLDHFU, FRVBF_INSN_NLDHFU, FRVBF_SFMT_NLDBFU }, + { FRV_INSN_NLDFU, FRVBF_INSN_NLDFU, FRVBF_SFMT_NLDBFU }, + { FRV_INSN_LDDU, FRVBF_INSN_LDDU, FRVBF_SFMT_LDDU }, + { FRV_INSN_NLDDU, FRVBF_INSN_NLDDU, FRVBF_SFMT_NLDDU }, + { FRV_INSN_LDDFU, FRVBF_INSN_LDDFU, FRVBF_SFMT_LDDFU }, + { FRV_INSN_LDDCU, FRVBF_INSN_LDDCU, FRVBF_SFMT_LDDCU }, + { FRV_INSN_NLDDFU, FRVBF_INSN_NLDDFU, FRVBF_SFMT_NLDDFU }, + { FRV_INSN_LDQU, FRVBF_INSN_LDQU, FRVBF_SFMT_LDQU }, + { FRV_INSN_NLDQU, FRVBF_INSN_NLDQU, FRVBF_SFMT_NLDQU }, + { FRV_INSN_LDQFU, FRVBF_INSN_LDQFU, FRVBF_SFMT_LDQFU }, + { FRV_INSN_LDQCU, FRVBF_INSN_LDQCU, FRVBF_SFMT_LDQCU }, + { FRV_INSN_NLDQFU, FRVBF_INSN_NLDQFU, FRVBF_SFMT_NLDQFU }, + { FRV_INSN_LDSBI, FRVBF_INSN_LDSBI, FRVBF_SFMT_LDSBI }, + { FRV_INSN_LDSHI, FRVBF_INSN_LDSHI, FRVBF_SFMT_LDSBI }, + { FRV_INSN_LDI, FRVBF_INSN_LDI, FRVBF_SFMT_LDSBI }, + { FRV_INSN_LDUBI, FRVBF_INSN_LDUBI, FRVBF_SFMT_LDSBI }, + { FRV_INSN_LDUHI, FRVBF_INSN_LDUHI, FRVBF_SFMT_LDSBI }, + { FRV_INSN_LDBFI, FRVBF_INSN_LDBFI, FRVBF_SFMT_LDBFI }, + { FRV_INSN_LDHFI, FRVBF_INSN_LDHFI, FRVBF_SFMT_LDBFI }, + { FRV_INSN_LDFI, FRVBF_INSN_LDFI, FRVBF_SFMT_LDBFI }, + { FRV_INSN_NLDSBI, FRVBF_INSN_NLDSBI, FRVBF_SFMT_NLDSBI }, + { FRV_INSN_NLDUBI, FRVBF_INSN_NLDUBI, FRVBF_SFMT_NLDSBI }, + { FRV_INSN_NLDSHI, FRVBF_INSN_NLDSHI, FRVBF_SFMT_NLDSBI }, + { FRV_INSN_NLDUHI, FRVBF_INSN_NLDUHI, FRVBF_SFMT_NLDSBI }, + { FRV_INSN_NLDI, FRVBF_INSN_NLDI, FRVBF_SFMT_NLDSBI }, + { FRV_INSN_NLDBFI, FRVBF_INSN_NLDBFI, FRVBF_SFMT_NLDBFI }, + { FRV_INSN_NLDHFI, FRVBF_INSN_NLDHFI, FRVBF_SFMT_NLDBFI }, + { FRV_INSN_NLDFI, FRVBF_INSN_NLDFI, FRVBF_SFMT_NLDBFI }, + { FRV_INSN_LDDI, FRVBF_INSN_LDDI, FRVBF_SFMT_LDDI }, + { FRV_INSN_LDDFI, FRVBF_INSN_LDDFI, FRVBF_SFMT_LDDFI }, + { FRV_INSN_NLDDI, FRVBF_INSN_NLDDI, FRVBF_SFMT_NLDDI }, + { FRV_INSN_NLDDFI, FRVBF_INSN_NLDDFI, FRVBF_SFMT_NLDDFI }, + { FRV_INSN_LDQI, FRVBF_INSN_LDQI, FRVBF_SFMT_LDQI }, + { FRV_INSN_LDQFI, FRVBF_INSN_LDQFI, FRVBF_SFMT_LDQFI }, + { FRV_INSN_NLDQFI, FRVBF_INSN_NLDQFI, FRVBF_SFMT_NLDQFI }, + { FRV_INSN_STB, FRVBF_INSN_STB, FRVBF_SFMT_STB }, + { FRV_INSN_STH, FRVBF_INSN_STH, FRVBF_SFMT_STB }, + { FRV_INSN_ST, FRVBF_INSN_ST, FRVBF_SFMT_STB }, + { FRV_INSN_STBF, FRVBF_INSN_STBF, FRVBF_SFMT_STBF }, + { FRV_INSN_STHF, FRVBF_INSN_STHF, FRVBF_SFMT_STBF }, + { FRV_INSN_STF, FRVBF_INSN_STF, FRVBF_SFMT_STBF }, + { FRV_INSN_STC, FRVBF_INSN_STC, FRVBF_SFMT_STC }, + { FRV_INSN_RSTB, FRVBF_INSN_RSTB, FRVBF_SFMT_RSTB }, + { FRV_INSN_RSTH, FRVBF_INSN_RSTH, FRVBF_SFMT_RSTB }, + { FRV_INSN_RST, FRVBF_INSN_RST, FRVBF_SFMT_RSTB }, + { FRV_INSN_RSTBF, FRVBF_INSN_RSTBF, FRVBF_SFMT_RSTBF }, + { FRV_INSN_RSTHF, FRVBF_INSN_RSTHF, FRVBF_SFMT_RSTBF }, + { FRV_INSN_RSTF, FRVBF_INSN_RSTF, FRVBF_SFMT_RSTBF }, + { FRV_INSN_STD, FRVBF_INSN_STD, FRVBF_SFMT_STD }, + { FRV_INSN_STDF, FRVBF_INSN_STDF, FRVBF_SFMT_STDF }, + { FRV_INSN_STDC, FRVBF_INSN_STDC, FRVBF_SFMT_STDC }, + { FRV_INSN_RSTD, FRVBF_INSN_RSTD, FRVBF_SFMT_RSTD }, + { FRV_INSN_RSTDF, FRVBF_INSN_RSTDF, FRVBF_SFMT_RSTDF }, + { FRV_INSN_STQ, FRVBF_INSN_STQ, FRVBF_SFMT_LDQ }, + { FRV_INSN_STQF, FRVBF_INSN_STQF, FRVBF_SFMT_LDQF }, + { FRV_INSN_STQC, FRVBF_INSN_STQC, FRVBF_SFMT_LDQC }, + { FRV_INSN_RSTQ, FRVBF_INSN_RSTQ, FRVBF_SFMT_LDQ }, + { FRV_INSN_RSTQF, FRVBF_INSN_RSTQF, FRVBF_SFMT_LDQF }, + { FRV_INSN_STBU, FRVBF_INSN_STBU, FRVBF_SFMT_STBU }, + { FRV_INSN_STHU, FRVBF_INSN_STHU, FRVBF_SFMT_STBU }, + { FRV_INSN_STU, FRVBF_INSN_STU, FRVBF_SFMT_STBU }, + { FRV_INSN_STBFU, FRVBF_INSN_STBFU, FRVBF_SFMT_STBFU }, + { FRV_INSN_STHFU, FRVBF_INSN_STHFU, FRVBF_SFMT_STBFU }, + { FRV_INSN_STFU, FRVBF_INSN_STFU, FRVBF_SFMT_STBFU }, + { FRV_INSN_STCU, FRVBF_INSN_STCU, FRVBF_SFMT_STCU }, + { FRV_INSN_STDU, FRVBF_INSN_STDU, FRVBF_SFMT_STDU }, + { FRV_INSN_STDFU, FRVBF_INSN_STDFU, FRVBF_SFMT_STDFU }, + { FRV_INSN_STDCU, FRVBF_INSN_STDCU, FRVBF_SFMT_STDCU }, + { FRV_INSN_STQU, FRVBF_INSN_STQU, FRVBF_SFMT_STQU }, + { FRV_INSN_STQFU, FRVBF_INSN_STQFU, FRVBF_SFMT_LDQFU }, + { FRV_INSN_STQCU, FRVBF_INSN_STQCU, FRVBF_SFMT_LDQCU }, + { FRV_INSN_CLDSB, FRVBF_INSN_CLDSB, FRVBF_SFMT_CLDSB }, + { FRV_INSN_CLDUB, FRVBF_INSN_CLDUB, FRVBF_SFMT_CLDSB }, + { FRV_INSN_CLDSH, FRVBF_INSN_CLDSH, FRVBF_SFMT_CLDSB }, + { FRV_INSN_CLDUH, FRVBF_INSN_CLDUH, FRVBF_SFMT_CLDSB }, + { FRV_INSN_CLD, FRVBF_INSN_CLD, FRVBF_SFMT_CLDSB }, + { FRV_INSN_CLDBF, FRVBF_INSN_CLDBF, FRVBF_SFMT_CLDBF }, + { FRV_INSN_CLDHF, FRVBF_INSN_CLDHF, FRVBF_SFMT_CLDBF }, + { FRV_INSN_CLDF, FRVBF_INSN_CLDF, FRVBF_SFMT_CLDBF }, + { FRV_INSN_CLDD, FRVBF_INSN_CLDD, FRVBF_SFMT_CLDD }, + { FRV_INSN_CLDDF, FRVBF_INSN_CLDDF, FRVBF_SFMT_CLDDF }, + { FRV_INSN_CLDQ, FRVBF_INSN_CLDQ, FRVBF_SFMT_CLDQ }, + { FRV_INSN_CLDSBU, FRVBF_INSN_CLDSBU, FRVBF_SFMT_CLDSBU }, + { FRV_INSN_CLDUBU, FRVBF_INSN_CLDUBU, FRVBF_SFMT_CLDSBU }, + { FRV_INSN_CLDSHU, FRVBF_INSN_CLDSHU, FRVBF_SFMT_CLDSBU }, + { FRV_INSN_CLDUHU, FRVBF_INSN_CLDUHU, FRVBF_SFMT_CLDSBU }, + { FRV_INSN_CLDU, FRVBF_INSN_CLDU, FRVBF_SFMT_CLDSBU }, + { FRV_INSN_CLDBFU, FRVBF_INSN_CLDBFU, FRVBF_SFMT_CLDBFU }, + { FRV_INSN_CLDHFU, FRVBF_INSN_CLDHFU, FRVBF_SFMT_CLDBFU }, + { FRV_INSN_CLDFU, FRVBF_INSN_CLDFU, FRVBF_SFMT_CLDBFU }, + { FRV_INSN_CLDDU, FRVBF_INSN_CLDDU, FRVBF_SFMT_CLDDU }, + { FRV_INSN_CLDDFU, FRVBF_INSN_CLDDFU, FRVBF_SFMT_CLDDFU }, + { FRV_INSN_CLDQU, FRVBF_INSN_CLDQU, FRVBF_SFMT_CLDQU }, + { FRV_INSN_CSTB, FRVBF_INSN_CSTB, FRVBF_SFMT_CSTB }, + { FRV_INSN_CSTH, FRVBF_INSN_CSTH, FRVBF_SFMT_CSTB }, + { FRV_INSN_CST, FRVBF_INSN_CST, FRVBF_SFMT_CSTB }, + { FRV_INSN_CSTBF, FRVBF_INSN_CSTBF, FRVBF_SFMT_CSTBF }, + { FRV_INSN_CSTHF, FRVBF_INSN_CSTHF, FRVBF_SFMT_CSTBF }, + { FRV_INSN_CSTF, FRVBF_INSN_CSTF, FRVBF_SFMT_CSTBF }, + { FRV_INSN_CSTD, FRVBF_INSN_CSTD, FRVBF_SFMT_CSTD }, + { FRV_INSN_CSTDF, FRVBF_INSN_CSTDF, FRVBF_SFMT_CSTDF }, + { FRV_INSN_CSTQ, FRVBF_INSN_CSTQ, FRVBF_SFMT_CLDQ }, + { FRV_INSN_CSTBU, FRVBF_INSN_CSTBU, FRVBF_SFMT_CSTBU }, + { FRV_INSN_CSTHU, FRVBF_INSN_CSTHU, FRVBF_SFMT_CSTBU }, + { FRV_INSN_CSTU, FRVBF_INSN_CSTU, FRVBF_SFMT_CSTBU }, + { FRV_INSN_CSTBFU, FRVBF_INSN_CSTBFU, FRVBF_SFMT_CSTBFU }, + { FRV_INSN_CSTHFU, FRVBF_INSN_CSTHFU, FRVBF_SFMT_CSTBFU }, + { FRV_INSN_CSTFU, FRVBF_INSN_CSTFU, FRVBF_SFMT_CSTBFU }, + { FRV_INSN_CSTDU, FRVBF_INSN_CSTDU, FRVBF_SFMT_CSTDU }, + { FRV_INSN_CSTDFU, FRVBF_INSN_CSTDFU, FRVBF_SFMT_CSTDFU }, + { FRV_INSN_STBI, FRVBF_INSN_STBI, FRVBF_SFMT_STBI }, + { FRV_INSN_STHI, FRVBF_INSN_STHI, FRVBF_SFMT_STBI }, + { FRV_INSN_STI, FRVBF_INSN_STI, FRVBF_SFMT_STBI }, + { FRV_INSN_STBFI, FRVBF_INSN_STBFI, FRVBF_SFMT_STBFI }, + { FRV_INSN_STHFI, FRVBF_INSN_STHFI, FRVBF_SFMT_STBFI }, + { FRV_INSN_STFI, FRVBF_INSN_STFI, FRVBF_SFMT_STBFI }, + { FRV_INSN_STDI, FRVBF_INSN_STDI, FRVBF_SFMT_STDI }, + { FRV_INSN_STDFI, FRVBF_INSN_STDFI, FRVBF_SFMT_STDFI }, + { FRV_INSN_STQI, FRVBF_INSN_STQI, FRVBF_SFMT_LDQI }, + { FRV_INSN_STQFI, FRVBF_INSN_STQFI, FRVBF_SFMT_LDQFI }, + { FRV_INSN_SWAP, FRVBF_INSN_SWAP, FRVBF_SFMT_SWAP }, + { FRV_INSN_SWAPI, FRVBF_INSN_SWAPI, FRVBF_SFMT_SWAPI }, + { FRV_INSN_CSWAP, FRVBF_INSN_CSWAP, FRVBF_SFMT_CSWAP }, + { FRV_INSN_MOVGF, FRVBF_INSN_MOVGF, FRVBF_SFMT_MOVGF }, + { FRV_INSN_MOVFG, FRVBF_INSN_MOVFG, FRVBF_SFMT_MOVFG }, + { FRV_INSN_MOVGFD, FRVBF_INSN_MOVGFD, FRVBF_SFMT_MOVGFD }, + { FRV_INSN_MOVFGD, FRVBF_INSN_MOVFGD, FRVBF_SFMT_MOVFGD }, + { FRV_INSN_MOVGFQ, FRVBF_INSN_MOVGFQ, FRVBF_SFMT_MOVGFQ }, + { FRV_INSN_MOVFGQ, FRVBF_INSN_MOVFGQ, FRVBF_SFMT_MOVFGQ }, + { FRV_INSN_CMOVGF, FRVBF_INSN_CMOVGF, FRVBF_SFMT_CMOVGF }, + { FRV_INSN_CMOVFG, FRVBF_INSN_CMOVFG, FRVBF_SFMT_CMOVFG }, + { FRV_INSN_CMOVGFD, FRVBF_INSN_CMOVGFD, FRVBF_SFMT_CMOVGFD }, + { FRV_INSN_CMOVFGD, FRVBF_INSN_CMOVFGD, FRVBF_SFMT_CMOVFGD }, + { FRV_INSN_MOVGS, FRVBF_INSN_MOVGS, FRVBF_SFMT_MOVGS }, + { FRV_INSN_MOVSG, FRVBF_INSN_MOVSG, FRVBF_SFMT_MOVSG }, + { FRV_INSN_BRA, FRVBF_INSN_BRA, FRVBF_SFMT_BRA }, + { FRV_INSN_BNO, FRVBF_INSN_BNO, FRVBF_SFMT_BNO }, + { FRV_INSN_BEQ, FRVBF_INSN_BEQ, FRVBF_SFMT_BEQ }, + { FRV_INSN_BNE, FRVBF_INSN_BNE, FRVBF_SFMT_BEQ }, + { FRV_INSN_BLE, FRVBF_INSN_BLE, FRVBF_SFMT_BEQ }, + { FRV_INSN_BGT, FRVBF_INSN_BGT, FRVBF_SFMT_BEQ }, + { FRV_INSN_BLT, FRVBF_INSN_BLT, FRVBF_SFMT_BEQ }, + { FRV_INSN_BGE, FRVBF_INSN_BGE, FRVBF_SFMT_BEQ }, + { FRV_INSN_BLS, FRVBF_INSN_BLS, FRVBF_SFMT_BEQ }, + { FRV_INSN_BHI, FRVBF_INSN_BHI, FRVBF_SFMT_BEQ }, + { FRV_INSN_BC, FRVBF_INSN_BC, FRVBF_SFMT_BEQ }, + { FRV_INSN_BNC, FRVBF_INSN_BNC, FRVBF_SFMT_BEQ }, + { FRV_INSN_BN, FRVBF_INSN_BN, FRVBF_SFMT_BEQ }, + { FRV_INSN_BP, FRVBF_INSN_BP, FRVBF_SFMT_BEQ }, + { FRV_INSN_BV, FRVBF_INSN_BV, FRVBF_SFMT_BEQ }, + { FRV_INSN_BNV, FRVBF_INSN_BNV, FRVBF_SFMT_BEQ }, + { FRV_INSN_FBRA, FRVBF_INSN_FBRA, FRVBF_SFMT_BRA }, + { FRV_INSN_FBNO, FRVBF_INSN_FBNO, FRVBF_SFMT_BNO }, + { FRV_INSN_FBNE, FRVBF_INSN_FBNE, FRVBF_SFMT_FBNE }, + { FRV_INSN_FBEQ, FRVBF_INSN_FBEQ, FRVBF_SFMT_FBNE }, + { FRV_INSN_FBLG, FRVBF_INSN_FBLG, FRVBF_SFMT_FBNE }, + { FRV_INSN_FBUE, FRVBF_INSN_FBUE, FRVBF_SFMT_FBNE }, + { FRV_INSN_FBUL, FRVBF_INSN_FBUL, FRVBF_SFMT_FBNE }, + { FRV_INSN_FBGE, FRVBF_INSN_FBGE, FRVBF_SFMT_FBNE }, + { FRV_INSN_FBLT, FRVBF_INSN_FBLT, FRVBF_SFMT_FBNE }, + { FRV_INSN_FBUGE, FRVBF_INSN_FBUGE, FRVBF_SFMT_FBNE }, + { FRV_INSN_FBUG, FRVBF_INSN_FBUG, FRVBF_SFMT_FBNE }, + { FRV_INSN_FBLE, FRVBF_INSN_FBLE, FRVBF_SFMT_FBNE }, + { FRV_INSN_FBGT, FRVBF_INSN_FBGT, FRVBF_SFMT_FBNE }, + { FRV_INSN_FBULE, FRVBF_INSN_FBULE, FRVBF_SFMT_FBNE }, + { FRV_INSN_FBU, FRVBF_INSN_FBU, FRVBF_SFMT_FBNE }, + { FRV_INSN_FBO, FRVBF_INSN_FBO, FRVBF_SFMT_FBNE }, + { FRV_INSN_BCTRLR, FRVBF_INSN_BCTRLR, FRVBF_SFMT_BCTRLR }, + { FRV_INSN_BRALR, FRVBF_INSN_BRALR, FRVBF_SFMT_BRALR }, + { FRV_INSN_BNOLR, FRVBF_INSN_BNOLR, FRVBF_SFMT_BNOLR }, + { FRV_INSN_BEQLR, FRVBF_INSN_BEQLR, FRVBF_SFMT_BEQLR }, + { FRV_INSN_BNELR, FRVBF_INSN_BNELR, FRVBF_SFMT_BEQLR }, + { FRV_INSN_BLELR, FRVBF_INSN_BLELR, FRVBF_SFMT_BEQLR }, + { FRV_INSN_BGTLR, FRVBF_INSN_BGTLR, FRVBF_SFMT_BEQLR }, + { FRV_INSN_BLTLR, FRVBF_INSN_BLTLR, FRVBF_SFMT_BEQLR }, + { FRV_INSN_BGELR, FRVBF_INSN_BGELR, FRVBF_SFMT_BEQLR }, + { FRV_INSN_BLSLR, FRVBF_INSN_BLSLR, FRVBF_SFMT_BEQLR }, + { FRV_INSN_BHILR, FRVBF_INSN_BHILR, FRVBF_SFMT_BEQLR }, + { FRV_INSN_BCLR, FRVBF_INSN_BCLR, FRVBF_SFMT_BEQLR }, + { FRV_INSN_BNCLR, FRVBF_INSN_BNCLR, FRVBF_SFMT_BEQLR }, + { FRV_INSN_BNLR, FRVBF_INSN_BNLR, FRVBF_SFMT_BEQLR }, + { FRV_INSN_BPLR, FRVBF_INSN_BPLR, FRVBF_SFMT_BEQLR }, + { FRV_INSN_BVLR, FRVBF_INSN_BVLR, FRVBF_SFMT_BEQLR }, + { FRV_INSN_BNVLR, FRVBF_INSN_BNVLR, FRVBF_SFMT_BEQLR }, + { FRV_INSN_FBRALR, FRVBF_INSN_FBRALR, FRVBF_SFMT_BRALR }, + { FRV_INSN_FBNOLR, FRVBF_INSN_FBNOLR, FRVBF_SFMT_BNOLR }, + { FRV_INSN_FBEQLR, FRVBF_INSN_FBEQLR, FRVBF_SFMT_FBEQLR }, + { FRV_INSN_FBNELR, FRVBF_INSN_FBNELR, FRVBF_SFMT_FBEQLR }, + { FRV_INSN_FBLGLR, FRVBF_INSN_FBLGLR, FRVBF_SFMT_FBEQLR }, + { FRV_INSN_FBUELR, FRVBF_INSN_FBUELR, FRVBF_SFMT_FBEQLR }, + { FRV_INSN_FBULLR, FRVBF_INSN_FBULLR, FRVBF_SFMT_FBEQLR }, + { FRV_INSN_FBGELR, FRVBF_INSN_FBGELR, FRVBF_SFMT_FBEQLR }, + { FRV_INSN_FBLTLR, FRVBF_INSN_FBLTLR, FRVBF_SFMT_FBEQLR }, + { FRV_INSN_FBUGELR, FRVBF_INSN_FBUGELR, FRVBF_SFMT_FBEQLR }, + { FRV_INSN_FBUGLR, FRVBF_INSN_FBUGLR, FRVBF_SFMT_FBEQLR }, + { FRV_INSN_FBLELR, FRVBF_INSN_FBLELR, FRVBF_SFMT_FBEQLR }, + { FRV_INSN_FBGTLR, FRVBF_INSN_FBGTLR, FRVBF_SFMT_FBEQLR }, + { FRV_INSN_FBULELR, FRVBF_INSN_FBULELR, FRVBF_SFMT_FBEQLR }, + { FRV_INSN_FBULR, FRVBF_INSN_FBULR, FRVBF_SFMT_FBEQLR }, + { FRV_INSN_FBOLR, FRVBF_INSN_FBOLR, FRVBF_SFMT_FBEQLR }, + { FRV_INSN_BCRALR, FRVBF_INSN_BCRALR, FRVBF_SFMT_BCRALR }, + { FRV_INSN_BCNOLR, FRVBF_INSN_BCNOLR, FRVBF_SFMT_BCNOLR }, + { FRV_INSN_BCEQLR, FRVBF_INSN_BCEQLR, FRVBF_SFMT_BCEQLR }, + { FRV_INSN_BCNELR, FRVBF_INSN_BCNELR, FRVBF_SFMT_BCEQLR }, + { FRV_INSN_BCLELR, FRVBF_INSN_BCLELR, FRVBF_SFMT_BCEQLR }, + { FRV_INSN_BCGTLR, FRVBF_INSN_BCGTLR, FRVBF_SFMT_BCEQLR }, + { FRV_INSN_BCLTLR, FRVBF_INSN_BCLTLR, FRVBF_SFMT_BCEQLR }, + { FRV_INSN_BCGELR, FRVBF_INSN_BCGELR, FRVBF_SFMT_BCEQLR }, + { FRV_INSN_BCLSLR, FRVBF_INSN_BCLSLR, FRVBF_SFMT_BCEQLR }, + { FRV_INSN_BCHILR, FRVBF_INSN_BCHILR, FRVBF_SFMT_BCEQLR }, + { FRV_INSN_BCCLR, FRVBF_INSN_BCCLR, FRVBF_SFMT_BCEQLR }, + { FRV_INSN_BCNCLR, FRVBF_INSN_BCNCLR, FRVBF_SFMT_BCEQLR }, + { FRV_INSN_BCNLR, FRVBF_INSN_BCNLR, FRVBF_SFMT_BCEQLR }, + { FRV_INSN_BCPLR, FRVBF_INSN_BCPLR, FRVBF_SFMT_BCEQLR }, + { FRV_INSN_BCVLR, FRVBF_INSN_BCVLR, FRVBF_SFMT_BCEQLR }, + { FRV_INSN_BCNVLR, FRVBF_INSN_BCNVLR, FRVBF_SFMT_BCEQLR }, + { FRV_INSN_FCBRALR, FRVBF_INSN_FCBRALR, FRVBF_SFMT_BCRALR }, + { FRV_INSN_FCBNOLR, FRVBF_INSN_FCBNOLR, FRVBF_SFMT_BCNOLR }, + { FRV_INSN_FCBEQLR, FRVBF_INSN_FCBEQLR, FRVBF_SFMT_FCBEQLR }, + { FRV_INSN_FCBNELR, FRVBF_INSN_FCBNELR, FRVBF_SFMT_FCBEQLR }, + { FRV_INSN_FCBLGLR, FRVBF_INSN_FCBLGLR, FRVBF_SFMT_FCBEQLR }, + { FRV_INSN_FCBUELR, FRVBF_INSN_FCBUELR, FRVBF_SFMT_FCBEQLR }, + { FRV_INSN_FCBULLR, FRVBF_INSN_FCBULLR, FRVBF_SFMT_FCBEQLR }, + { FRV_INSN_FCBGELR, FRVBF_INSN_FCBGELR, FRVBF_SFMT_FCBEQLR }, + { FRV_INSN_FCBLTLR, FRVBF_INSN_FCBLTLR, FRVBF_SFMT_FCBEQLR }, + { FRV_INSN_FCBUGELR, FRVBF_INSN_FCBUGELR, FRVBF_SFMT_FCBEQLR }, + { FRV_INSN_FCBUGLR, FRVBF_INSN_FCBUGLR, FRVBF_SFMT_FCBEQLR }, + { FRV_INSN_FCBLELR, FRVBF_INSN_FCBLELR, FRVBF_SFMT_FCBEQLR }, + { FRV_INSN_FCBGTLR, FRVBF_INSN_FCBGTLR, FRVBF_SFMT_FCBEQLR }, + { FRV_INSN_FCBULELR, FRVBF_INSN_FCBULELR, FRVBF_SFMT_FCBEQLR }, + { FRV_INSN_FCBULR, FRVBF_INSN_FCBULR, FRVBF_SFMT_FCBEQLR }, + { FRV_INSN_FCBOLR, FRVBF_INSN_FCBOLR, FRVBF_SFMT_FCBEQLR }, + { FRV_INSN_JMPL, FRVBF_INSN_JMPL, FRVBF_SFMT_JMPL }, + { FRV_INSN_CALLL, FRVBF_INSN_CALLL, FRVBF_SFMT_JMPL }, + { FRV_INSN_JMPIL, FRVBF_INSN_JMPIL, FRVBF_SFMT_JMPIL }, + { FRV_INSN_CALLIL, FRVBF_INSN_CALLIL, FRVBF_SFMT_JMPIL }, + { FRV_INSN_CALL, FRVBF_INSN_CALL, FRVBF_SFMT_CALL }, + { FRV_INSN_RETT, FRVBF_INSN_RETT, FRVBF_SFMT_RETT }, + { FRV_INSN_REI, FRVBF_INSN_REI, FRVBF_SFMT_REI }, + { FRV_INSN_TRA, FRVBF_INSN_TRA, FRVBF_SFMT_TRA }, + { FRV_INSN_TNO, FRVBF_INSN_TNO, FRVBF_SFMT_REI }, + { FRV_INSN_TEQ, FRVBF_INSN_TEQ, FRVBF_SFMT_TEQ }, + { FRV_INSN_TNE, FRVBF_INSN_TNE, FRVBF_SFMT_TEQ }, + { FRV_INSN_TLE, FRVBF_INSN_TLE, FRVBF_SFMT_TEQ }, + { FRV_INSN_TGT, FRVBF_INSN_TGT, FRVBF_SFMT_TEQ }, + { FRV_INSN_TLT, FRVBF_INSN_TLT, FRVBF_SFMT_TEQ }, + { FRV_INSN_TGE, FRVBF_INSN_TGE, FRVBF_SFMT_TEQ }, + { FRV_INSN_TLS, FRVBF_INSN_TLS, FRVBF_SFMT_TEQ }, + { FRV_INSN_THI, FRVBF_INSN_THI, FRVBF_SFMT_TEQ }, + { FRV_INSN_TC, FRVBF_INSN_TC, FRVBF_SFMT_TEQ }, + { FRV_INSN_TNC, FRVBF_INSN_TNC, FRVBF_SFMT_TEQ }, + { FRV_INSN_TN, FRVBF_INSN_TN, FRVBF_SFMT_TEQ }, + { FRV_INSN_TP, FRVBF_INSN_TP, FRVBF_SFMT_TEQ }, + { FRV_INSN_TV, FRVBF_INSN_TV, FRVBF_SFMT_TEQ }, + { FRV_INSN_TNV, FRVBF_INSN_TNV, FRVBF_SFMT_TEQ }, + { FRV_INSN_FTRA, FRVBF_INSN_FTRA, FRVBF_SFMT_TRA }, + { FRV_INSN_FTNO, FRVBF_INSN_FTNO, FRVBF_SFMT_REI }, + { FRV_INSN_FTNE, FRVBF_INSN_FTNE, FRVBF_SFMT_FTNE }, + { FRV_INSN_FTEQ, FRVBF_INSN_FTEQ, FRVBF_SFMT_FTNE }, + { FRV_INSN_FTLG, FRVBF_INSN_FTLG, FRVBF_SFMT_FTNE }, + { FRV_INSN_FTUE, FRVBF_INSN_FTUE, FRVBF_SFMT_FTNE }, + { FRV_INSN_FTUL, FRVBF_INSN_FTUL, FRVBF_SFMT_FTNE }, + { FRV_INSN_FTGE, FRVBF_INSN_FTGE, FRVBF_SFMT_FTNE }, + { FRV_INSN_FTLT, FRVBF_INSN_FTLT, FRVBF_SFMT_FTNE }, + { FRV_INSN_FTUGE, FRVBF_INSN_FTUGE, FRVBF_SFMT_FTNE }, + { FRV_INSN_FTUG, FRVBF_INSN_FTUG, FRVBF_SFMT_FTNE }, + { FRV_INSN_FTLE, FRVBF_INSN_FTLE, FRVBF_SFMT_FTNE }, + { FRV_INSN_FTGT, FRVBF_INSN_FTGT, FRVBF_SFMT_FTNE }, + { FRV_INSN_FTULE, FRVBF_INSN_FTULE, FRVBF_SFMT_FTNE }, + { FRV_INSN_FTU, FRVBF_INSN_FTU, FRVBF_SFMT_FTNE }, + { FRV_INSN_FTO, FRVBF_INSN_FTO, FRVBF_SFMT_FTNE }, + { FRV_INSN_TIRA, FRVBF_INSN_TIRA, FRVBF_SFMT_TIRA }, + { FRV_INSN_TINO, FRVBF_INSN_TINO, FRVBF_SFMT_REI }, + { FRV_INSN_TIEQ, FRVBF_INSN_TIEQ, FRVBF_SFMT_TIEQ }, + { FRV_INSN_TINE, FRVBF_INSN_TINE, FRVBF_SFMT_TIEQ }, + { FRV_INSN_TILE, FRVBF_INSN_TILE, FRVBF_SFMT_TIEQ }, + { FRV_INSN_TIGT, FRVBF_INSN_TIGT, FRVBF_SFMT_TIEQ }, + { FRV_INSN_TILT, FRVBF_INSN_TILT, FRVBF_SFMT_TIEQ }, + { FRV_INSN_TIGE, FRVBF_INSN_TIGE, FRVBF_SFMT_TIEQ }, + { FRV_INSN_TILS, FRVBF_INSN_TILS, FRVBF_SFMT_TIEQ }, + { FRV_INSN_TIHI, FRVBF_INSN_TIHI, FRVBF_SFMT_TIEQ }, + { FRV_INSN_TIC, FRVBF_INSN_TIC, FRVBF_SFMT_TIEQ }, + { FRV_INSN_TINC, FRVBF_INSN_TINC, FRVBF_SFMT_TIEQ }, + { FRV_INSN_TIN, FRVBF_INSN_TIN, FRVBF_SFMT_TIEQ }, + { FRV_INSN_TIP, FRVBF_INSN_TIP, FRVBF_SFMT_TIEQ }, + { FRV_INSN_TIV, FRVBF_INSN_TIV, FRVBF_SFMT_TIEQ }, + { FRV_INSN_TINV, FRVBF_INSN_TINV, FRVBF_SFMT_TIEQ }, + { FRV_INSN_FTIRA, FRVBF_INSN_FTIRA, FRVBF_SFMT_TIRA }, + { FRV_INSN_FTINO, FRVBF_INSN_FTINO, FRVBF_SFMT_REI }, + { FRV_INSN_FTINE, FRVBF_INSN_FTINE, FRVBF_SFMT_FTINE }, + { FRV_INSN_FTIEQ, FRVBF_INSN_FTIEQ, FRVBF_SFMT_FTINE }, + { FRV_INSN_FTILG, FRVBF_INSN_FTILG, FRVBF_SFMT_FTINE }, + { FRV_INSN_FTIUE, FRVBF_INSN_FTIUE, FRVBF_SFMT_FTINE }, + { FRV_INSN_FTIUL, FRVBF_INSN_FTIUL, FRVBF_SFMT_FTINE }, + { FRV_INSN_FTIGE, FRVBF_INSN_FTIGE, FRVBF_SFMT_FTINE }, + { FRV_INSN_FTILT, FRVBF_INSN_FTILT, FRVBF_SFMT_FTINE }, + { FRV_INSN_FTIUGE, FRVBF_INSN_FTIUGE, FRVBF_SFMT_FTINE }, + { FRV_INSN_FTIUG, FRVBF_INSN_FTIUG, FRVBF_SFMT_FTINE }, + { FRV_INSN_FTILE, FRVBF_INSN_FTILE, FRVBF_SFMT_FTINE }, + { FRV_INSN_FTIGT, FRVBF_INSN_FTIGT, FRVBF_SFMT_FTINE }, + { FRV_INSN_FTIULE, FRVBF_INSN_FTIULE, FRVBF_SFMT_FTINE }, + { FRV_INSN_FTIU, FRVBF_INSN_FTIU, FRVBF_SFMT_FTINE }, + { FRV_INSN_FTIO, FRVBF_INSN_FTIO, FRVBF_SFMT_FTINE }, + { FRV_INSN_BREAK, FRVBF_INSN_BREAK, FRVBF_SFMT_BREAK }, + { FRV_INSN_MTRAP, FRVBF_INSN_MTRAP, FRVBF_SFMT_REI }, + { FRV_INSN_ANDCR, FRVBF_INSN_ANDCR, FRVBF_SFMT_ANDCR }, + { FRV_INSN_ORCR, FRVBF_INSN_ORCR, FRVBF_SFMT_ANDCR }, + { FRV_INSN_XORCR, FRVBF_INSN_XORCR, FRVBF_SFMT_ANDCR }, + { FRV_INSN_NANDCR, FRVBF_INSN_NANDCR, FRVBF_SFMT_ANDCR }, + { FRV_INSN_NORCR, FRVBF_INSN_NORCR, FRVBF_SFMT_ANDCR }, + { FRV_INSN_ANDNCR, FRVBF_INSN_ANDNCR, FRVBF_SFMT_ANDCR }, + { FRV_INSN_ORNCR, FRVBF_INSN_ORNCR, FRVBF_SFMT_ANDCR }, + { FRV_INSN_NANDNCR, FRVBF_INSN_NANDNCR, FRVBF_SFMT_ANDCR }, + { FRV_INSN_NORNCR, FRVBF_INSN_NORNCR, FRVBF_SFMT_ANDCR }, + { FRV_INSN_NOTCR, FRVBF_INSN_NOTCR, FRVBF_SFMT_NOTCR }, + { FRV_INSN_CKRA, FRVBF_INSN_CKRA, FRVBF_SFMT_CKRA }, + { FRV_INSN_CKNO, FRVBF_INSN_CKNO, FRVBF_SFMT_CKRA }, + { FRV_INSN_CKEQ, FRVBF_INSN_CKEQ, FRVBF_SFMT_CKEQ }, + { FRV_INSN_CKNE, FRVBF_INSN_CKNE, FRVBF_SFMT_CKEQ }, + { FRV_INSN_CKLE, FRVBF_INSN_CKLE, FRVBF_SFMT_CKEQ }, + { FRV_INSN_CKGT, FRVBF_INSN_CKGT, FRVBF_SFMT_CKEQ }, + { FRV_INSN_CKLT, FRVBF_INSN_CKLT, FRVBF_SFMT_CKEQ }, + { FRV_INSN_CKGE, FRVBF_INSN_CKGE, FRVBF_SFMT_CKEQ }, + { FRV_INSN_CKLS, FRVBF_INSN_CKLS, FRVBF_SFMT_CKEQ }, + { FRV_INSN_CKHI, FRVBF_INSN_CKHI, FRVBF_SFMT_CKEQ }, + { FRV_INSN_CKC, FRVBF_INSN_CKC, FRVBF_SFMT_CKEQ }, + { FRV_INSN_CKNC, FRVBF_INSN_CKNC, FRVBF_SFMT_CKEQ }, + { FRV_INSN_CKN, FRVBF_INSN_CKN, FRVBF_SFMT_CKEQ }, + { FRV_INSN_CKP, FRVBF_INSN_CKP, FRVBF_SFMT_CKEQ }, + { FRV_INSN_CKV, FRVBF_INSN_CKV, FRVBF_SFMT_CKEQ }, + { FRV_INSN_CKNV, FRVBF_INSN_CKNV, FRVBF_SFMT_CKEQ }, + { FRV_INSN_FCKRA, FRVBF_INSN_FCKRA, FRVBF_SFMT_FCKRA }, + { FRV_INSN_FCKNO, FRVBF_INSN_FCKNO, FRVBF_SFMT_FCKRA }, + { FRV_INSN_FCKNE, FRVBF_INSN_FCKNE, FRVBF_SFMT_FCKNE }, + { FRV_INSN_FCKEQ, FRVBF_INSN_FCKEQ, FRVBF_SFMT_FCKNE }, + { FRV_INSN_FCKLG, FRVBF_INSN_FCKLG, FRVBF_SFMT_FCKNE }, + { FRV_INSN_FCKUE, FRVBF_INSN_FCKUE, FRVBF_SFMT_FCKNE }, + { FRV_INSN_FCKUL, FRVBF_INSN_FCKUL, FRVBF_SFMT_FCKNE }, + { FRV_INSN_FCKGE, FRVBF_INSN_FCKGE, FRVBF_SFMT_FCKNE }, + { FRV_INSN_FCKLT, FRVBF_INSN_FCKLT, FRVBF_SFMT_FCKNE }, + { FRV_INSN_FCKUGE, FRVBF_INSN_FCKUGE, FRVBF_SFMT_FCKNE }, + { FRV_INSN_FCKUG, FRVBF_INSN_FCKUG, FRVBF_SFMT_FCKNE }, + { FRV_INSN_FCKLE, FRVBF_INSN_FCKLE, FRVBF_SFMT_FCKNE }, + { FRV_INSN_FCKGT, FRVBF_INSN_FCKGT, FRVBF_SFMT_FCKNE }, + { FRV_INSN_FCKULE, FRVBF_INSN_FCKULE, FRVBF_SFMT_FCKNE }, + { FRV_INSN_FCKU, FRVBF_INSN_FCKU, FRVBF_SFMT_FCKNE }, + { FRV_INSN_FCKO, FRVBF_INSN_FCKO, FRVBF_SFMT_FCKNE }, + { FRV_INSN_CCKRA, FRVBF_INSN_CCKRA, FRVBF_SFMT_CCKRA }, + { FRV_INSN_CCKNO, FRVBF_INSN_CCKNO, FRVBF_SFMT_CCKRA }, + { FRV_INSN_CCKEQ, FRVBF_INSN_CCKEQ, FRVBF_SFMT_CCKEQ }, + { FRV_INSN_CCKNE, FRVBF_INSN_CCKNE, FRVBF_SFMT_CCKEQ }, + { FRV_INSN_CCKLE, FRVBF_INSN_CCKLE, FRVBF_SFMT_CCKEQ }, + { FRV_INSN_CCKGT, FRVBF_INSN_CCKGT, FRVBF_SFMT_CCKEQ }, + { FRV_INSN_CCKLT, FRVBF_INSN_CCKLT, FRVBF_SFMT_CCKEQ }, + { FRV_INSN_CCKGE, FRVBF_INSN_CCKGE, FRVBF_SFMT_CCKEQ }, + { FRV_INSN_CCKLS, FRVBF_INSN_CCKLS, FRVBF_SFMT_CCKEQ }, + { FRV_INSN_CCKHI, FRVBF_INSN_CCKHI, FRVBF_SFMT_CCKEQ }, + { FRV_INSN_CCKC, FRVBF_INSN_CCKC, FRVBF_SFMT_CCKEQ }, + { FRV_INSN_CCKNC, FRVBF_INSN_CCKNC, FRVBF_SFMT_CCKEQ }, + { FRV_INSN_CCKN, FRVBF_INSN_CCKN, FRVBF_SFMT_CCKEQ }, + { FRV_INSN_CCKP, FRVBF_INSN_CCKP, FRVBF_SFMT_CCKEQ }, + { FRV_INSN_CCKV, FRVBF_INSN_CCKV, FRVBF_SFMT_CCKEQ }, + { FRV_INSN_CCKNV, FRVBF_INSN_CCKNV, FRVBF_SFMT_CCKEQ }, + { FRV_INSN_CFCKRA, FRVBF_INSN_CFCKRA, FRVBF_SFMT_CFCKRA }, + { FRV_INSN_CFCKNO, FRVBF_INSN_CFCKNO, FRVBF_SFMT_CFCKRA }, + { FRV_INSN_CFCKNE, FRVBF_INSN_CFCKNE, FRVBF_SFMT_CFCKNE }, + { FRV_INSN_CFCKEQ, FRVBF_INSN_CFCKEQ, FRVBF_SFMT_CFCKNE }, + { FRV_INSN_CFCKLG, FRVBF_INSN_CFCKLG, FRVBF_SFMT_CFCKNE }, + { FRV_INSN_CFCKUE, FRVBF_INSN_CFCKUE, FRVBF_SFMT_CFCKNE }, + { FRV_INSN_CFCKUL, FRVBF_INSN_CFCKUL, FRVBF_SFMT_CFCKNE }, + { FRV_INSN_CFCKGE, FRVBF_INSN_CFCKGE, FRVBF_SFMT_CFCKNE }, + { FRV_INSN_CFCKLT, FRVBF_INSN_CFCKLT, FRVBF_SFMT_CFCKNE }, + { FRV_INSN_CFCKUGE, FRVBF_INSN_CFCKUGE, FRVBF_SFMT_CFCKNE }, + { FRV_INSN_CFCKUG, FRVBF_INSN_CFCKUG, FRVBF_SFMT_CFCKNE }, + { FRV_INSN_CFCKLE, FRVBF_INSN_CFCKLE, FRVBF_SFMT_CFCKNE }, + { FRV_INSN_CFCKGT, FRVBF_INSN_CFCKGT, FRVBF_SFMT_CFCKNE }, + { FRV_INSN_CFCKULE, FRVBF_INSN_CFCKULE, FRVBF_SFMT_CFCKNE }, + { FRV_INSN_CFCKU, FRVBF_INSN_CFCKU, FRVBF_SFMT_CFCKNE }, + { FRV_INSN_CFCKO, FRVBF_INSN_CFCKO, FRVBF_SFMT_CFCKNE }, + { FRV_INSN_CJMPL, FRVBF_INSN_CJMPL, FRVBF_SFMT_CJMPL }, + { FRV_INSN_CCALLL, FRVBF_INSN_CCALLL, FRVBF_SFMT_CJMPL }, + { FRV_INSN_ICI, FRVBF_INSN_ICI, FRVBF_SFMT_ICI }, + { FRV_INSN_DCI, FRVBF_INSN_DCI, FRVBF_SFMT_ICI }, + { FRV_INSN_ICEI, FRVBF_INSN_ICEI, FRVBF_SFMT_ICEI }, + { FRV_INSN_DCEI, FRVBF_INSN_DCEI, FRVBF_SFMT_ICEI }, + { FRV_INSN_DCF, FRVBF_INSN_DCF, FRVBF_SFMT_ICI }, + { FRV_INSN_DCEF, FRVBF_INSN_DCEF, FRVBF_SFMT_ICEI }, + { FRV_INSN_WITLB, FRVBF_INSN_WITLB, FRVBF_SFMT_REI }, + { FRV_INSN_WDTLB, FRVBF_INSN_WDTLB, FRVBF_SFMT_REI }, + { FRV_INSN_ITLBI, FRVBF_INSN_ITLBI, FRVBF_SFMT_REI }, + { FRV_INSN_DTLBI, FRVBF_INSN_DTLBI, FRVBF_SFMT_REI }, + { FRV_INSN_ICPL, FRVBF_INSN_ICPL, FRVBF_SFMT_ICPL }, + { FRV_INSN_DCPL, FRVBF_INSN_DCPL, FRVBF_SFMT_ICPL }, + { FRV_INSN_ICUL, FRVBF_INSN_ICUL, FRVBF_SFMT_ICUL }, + { FRV_INSN_DCUL, FRVBF_INSN_DCUL, FRVBF_SFMT_ICUL }, + { FRV_INSN_BAR, FRVBF_INSN_BAR, FRVBF_SFMT_REI }, + { FRV_INSN_MEMBAR, FRVBF_INSN_MEMBAR, FRVBF_SFMT_REI }, + { FRV_INSN_COP1, FRVBF_INSN_COP1, FRVBF_SFMT_REI }, + { FRV_INSN_COP2, FRVBF_INSN_COP2, FRVBF_SFMT_REI }, + { FRV_INSN_CLRGR, FRVBF_INSN_CLRGR, FRVBF_SFMT_CLRGR }, + { FRV_INSN_CLRFR, FRVBF_INSN_CLRFR, FRVBF_SFMT_CLRFR }, + { FRV_INSN_CLRGA, FRVBF_INSN_CLRGA, FRVBF_SFMT_REI }, + { FRV_INSN_CLRFA, FRVBF_INSN_CLRFA, FRVBF_SFMT_REI }, + { FRV_INSN_COMMITGR, FRVBF_INSN_COMMITGR, FRVBF_SFMT_COMMITGR }, + { FRV_INSN_COMMITFR, FRVBF_INSN_COMMITFR, FRVBF_SFMT_COMMITFR }, + { FRV_INSN_COMMITGA, FRVBF_INSN_COMMITGA, FRVBF_SFMT_REI }, + { FRV_INSN_COMMITFA, FRVBF_INSN_COMMITFA, FRVBF_SFMT_REI }, + { FRV_INSN_FITOS, FRVBF_INSN_FITOS, FRVBF_SFMT_FITOS }, + { FRV_INSN_FSTOI, FRVBF_INSN_FSTOI, FRVBF_SFMT_FSTOI }, + { FRV_INSN_FITOD, FRVBF_INSN_FITOD, FRVBF_SFMT_FITOD }, + { FRV_INSN_FDTOI, FRVBF_INSN_FDTOI, FRVBF_SFMT_FDTOI }, + { FRV_INSN_FDITOS, FRVBF_INSN_FDITOS, FRVBF_SFMT_FDITOS }, + { FRV_INSN_FDSTOI, FRVBF_INSN_FDSTOI, FRVBF_SFMT_FDSTOI }, + { FRV_INSN_NFDITOS, FRVBF_INSN_NFDITOS, FRVBF_SFMT_FDITOS }, + { FRV_INSN_NFDSTOI, FRVBF_INSN_NFDSTOI, FRVBF_SFMT_FDSTOI }, + { FRV_INSN_CFITOS, FRVBF_INSN_CFITOS, FRVBF_SFMT_CFITOS }, + { FRV_INSN_CFSTOI, FRVBF_INSN_CFSTOI, FRVBF_SFMT_CFSTOI }, + { FRV_INSN_NFITOS, FRVBF_INSN_NFITOS, FRVBF_SFMT_NFITOS }, + { FRV_INSN_NFSTOI, FRVBF_INSN_NFSTOI, FRVBF_SFMT_NFSTOI }, + { FRV_INSN_FMOVS, FRVBF_INSN_FMOVS, FRVBF_SFMT_FMOVS }, + { FRV_INSN_FMOVD, FRVBF_INSN_FMOVD, FRVBF_SFMT_FMOVD }, + { FRV_INSN_FDMOVS, FRVBF_INSN_FDMOVS, FRVBF_SFMT_FDMOVS }, + { FRV_INSN_CFMOVS, FRVBF_INSN_CFMOVS, FRVBF_SFMT_CFMOVS }, + { FRV_INSN_FNEGS, FRVBF_INSN_FNEGS, FRVBF_SFMT_FMOVS }, + { FRV_INSN_FNEGD, FRVBF_INSN_FNEGD, FRVBF_SFMT_FMOVD }, + { FRV_INSN_FDNEGS, FRVBF_INSN_FDNEGS, FRVBF_SFMT_FDMOVS }, + { FRV_INSN_CFNEGS, FRVBF_INSN_CFNEGS, FRVBF_SFMT_CFMOVS }, + { FRV_INSN_FABSS, FRVBF_INSN_FABSS, FRVBF_SFMT_FMOVS }, + { FRV_INSN_FABSD, FRVBF_INSN_FABSD, FRVBF_SFMT_FMOVD }, + { FRV_INSN_FDABSS, FRVBF_INSN_FDABSS, FRVBF_SFMT_FDMOVS }, + { FRV_INSN_CFABSS, FRVBF_INSN_CFABSS, FRVBF_SFMT_CFMOVS }, + { FRV_INSN_FSQRTS, FRVBF_INSN_FSQRTS, FRVBF_SFMT_FMOVS }, + { FRV_INSN_FDSQRTS, FRVBF_INSN_FDSQRTS, FRVBF_SFMT_FDMOVS }, + { FRV_INSN_NFDSQRTS, FRVBF_INSN_NFDSQRTS, FRVBF_SFMT_FDMOVS }, + { FRV_INSN_FSQRTD, FRVBF_INSN_FSQRTD, FRVBF_SFMT_FMOVD }, + { FRV_INSN_CFSQRTS, FRVBF_INSN_CFSQRTS, FRVBF_SFMT_CFMOVS }, + { FRV_INSN_NFSQRTS, FRVBF_INSN_NFSQRTS, FRVBF_SFMT_NFSQRTS }, + { FRV_INSN_FADDS, FRVBF_INSN_FADDS, FRVBF_SFMT_FADDS }, + { FRV_INSN_FSUBS, FRVBF_INSN_FSUBS, FRVBF_SFMT_FADDS }, + { FRV_INSN_FMULS, FRVBF_INSN_FMULS, FRVBF_SFMT_FADDS }, + { FRV_INSN_FDIVS, FRVBF_INSN_FDIVS, FRVBF_SFMT_FADDS }, + { FRV_INSN_FADDD, FRVBF_INSN_FADDD, FRVBF_SFMT_FADDD }, + { FRV_INSN_FSUBD, FRVBF_INSN_FSUBD, FRVBF_SFMT_FADDD }, + { FRV_INSN_FMULD, FRVBF_INSN_FMULD, FRVBF_SFMT_FADDD }, + { FRV_INSN_FDIVD, FRVBF_INSN_FDIVD, FRVBF_SFMT_FADDD }, + { FRV_INSN_CFADDS, FRVBF_INSN_CFADDS, FRVBF_SFMT_CFADDS }, + { FRV_INSN_CFSUBS, FRVBF_INSN_CFSUBS, FRVBF_SFMT_CFADDS }, + { FRV_INSN_CFMULS, FRVBF_INSN_CFMULS, FRVBF_SFMT_CFADDS }, + { FRV_INSN_CFDIVS, FRVBF_INSN_CFDIVS, FRVBF_SFMT_CFADDS }, + { FRV_INSN_NFADDS, FRVBF_INSN_NFADDS, FRVBF_SFMT_NFADDS }, + { FRV_INSN_NFSUBS, FRVBF_INSN_NFSUBS, FRVBF_SFMT_NFADDS }, + { FRV_INSN_NFMULS, FRVBF_INSN_NFMULS, FRVBF_SFMT_NFADDS }, + { FRV_INSN_NFDIVS, FRVBF_INSN_NFDIVS, FRVBF_SFMT_NFADDS }, + { FRV_INSN_FCMPS, FRVBF_INSN_FCMPS, FRVBF_SFMT_FCMPS }, + { FRV_INSN_FCMPD, FRVBF_INSN_FCMPD, FRVBF_SFMT_FCMPD }, + { FRV_INSN_CFCMPS, FRVBF_INSN_CFCMPS, FRVBF_SFMT_CFCMPS }, + { FRV_INSN_FDCMPS, FRVBF_INSN_FDCMPS, FRVBF_SFMT_FDCMPS }, + { FRV_INSN_FMADDS, FRVBF_INSN_FMADDS, FRVBF_SFMT_FMADDS }, + { FRV_INSN_FMSUBS, FRVBF_INSN_FMSUBS, FRVBF_SFMT_FMADDS }, + { FRV_INSN_FMADDD, FRVBF_INSN_FMADDD, FRVBF_SFMT_FMADDD }, + { FRV_INSN_FMSUBD, FRVBF_INSN_FMSUBD, FRVBF_SFMT_FMADDD }, + { FRV_INSN_FDMADDS, FRVBF_INSN_FDMADDS, FRVBF_SFMT_FDMADDS }, + { FRV_INSN_NFDMADDS, FRVBF_INSN_NFDMADDS, FRVBF_SFMT_FDMADDS }, + { FRV_INSN_CFMADDS, FRVBF_INSN_CFMADDS, FRVBF_SFMT_CFMADDS }, + { FRV_INSN_CFMSUBS, FRVBF_INSN_CFMSUBS, FRVBF_SFMT_CFMADDS }, + { FRV_INSN_NFMADDS, FRVBF_INSN_NFMADDS, FRVBF_SFMT_NFMADDS }, + { FRV_INSN_NFMSUBS, FRVBF_INSN_NFMSUBS, FRVBF_SFMT_NFMADDS }, + { FRV_INSN_FMAS, FRVBF_INSN_FMAS, FRVBF_SFMT_FMAS }, + { FRV_INSN_FMSS, FRVBF_INSN_FMSS, FRVBF_SFMT_FMAS }, + { FRV_INSN_FDMAS, FRVBF_INSN_FDMAS, FRVBF_SFMT_FDMAS }, + { FRV_INSN_FDMSS, FRVBF_INSN_FDMSS, FRVBF_SFMT_FDMAS }, + { FRV_INSN_NFDMAS, FRVBF_INSN_NFDMAS, FRVBF_SFMT_FDMAS }, + { FRV_INSN_NFDMSS, FRVBF_INSN_NFDMSS, FRVBF_SFMT_FDMAS }, + { FRV_INSN_CFMAS, FRVBF_INSN_CFMAS, FRVBF_SFMT_CFMAS }, + { FRV_INSN_CFMSS, FRVBF_INSN_CFMSS, FRVBF_SFMT_CFMAS }, + { FRV_INSN_FMAD, FRVBF_INSN_FMAD, FRVBF_SFMT_FMAS }, + { FRV_INSN_FMSD, FRVBF_INSN_FMSD, FRVBF_SFMT_FMAS }, + { FRV_INSN_NFMAS, FRVBF_INSN_NFMAS, FRVBF_SFMT_FMAS }, + { FRV_INSN_NFMSS, FRVBF_INSN_NFMSS, FRVBF_SFMT_FMAS }, + { FRV_INSN_FDADDS, FRVBF_INSN_FDADDS, FRVBF_SFMT_FMAS }, + { FRV_INSN_FDSUBS, FRVBF_INSN_FDSUBS, FRVBF_SFMT_FMAS }, + { FRV_INSN_FDMULS, FRVBF_INSN_FDMULS, FRVBF_SFMT_FMAS }, + { FRV_INSN_FDDIVS, FRVBF_INSN_FDDIVS, FRVBF_SFMT_FMAS }, + { FRV_INSN_FDSADS, FRVBF_INSN_FDSADS, FRVBF_SFMT_FMAS }, + { FRV_INSN_FDMULCS, FRVBF_INSN_FDMULCS, FRVBF_SFMT_FMAS }, + { FRV_INSN_NFDMULCS, FRVBF_INSN_NFDMULCS, FRVBF_SFMT_FMAS }, + { FRV_INSN_NFDADDS, FRVBF_INSN_NFDADDS, FRVBF_SFMT_FMAS }, + { FRV_INSN_NFDSUBS, FRVBF_INSN_NFDSUBS, FRVBF_SFMT_FMAS }, + { FRV_INSN_NFDMULS, FRVBF_INSN_NFDMULS, FRVBF_SFMT_FMAS }, + { FRV_INSN_NFDDIVS, FRVBF_INSN_NFDDIVS, FRVBF_SFMT_FMAS }, + { FRV_INSN_NFDSADS, FRVBF_INSN_NFDSADS, FRVBF_SFMT_FMAS }, + { FRV_INSN_NFDCMPS, FRVBF_INSN_NFDCMPS, FRVBF_SFMT_NFDCMPS }, + { FRV_INSN_MHSETLOS, FRVBF_INSN_MHSETLOS, FRVBF_SFMT_MHSETLOS }, + { FRV_INSN_MHSETHIS, FRVBF_INSN_MHSETHIS, FRVBF_SFMT_MHSETHIS }, + { FRV_INSN_MHDSETS, FRVBF_INSN_MHDSETS, FRVBF_SFMT_MHDSETS }, + { FRV_INSN_MHSETLOH, FRVBF_INSN_MHSETLOH, FRVBF_SFMT_MHSETLOH }, + { FRV_INSN_MHSETHIH, FRVBF_INSN_MHSETHIH, FRVBF_SFMT_MHSETHIH }, + { FRV_INSN_MHDSETH, FRVBF_INSN_MHDSETH, FRVBF_SFMT_MHDSETH }, + { FRV_INSN_MAND, FRVBF_INSN_MAND, FRVBF_SFMT_MAND }, + { FRV_INSN_MOR, FRVBF_INSN_MOR, FRVBF_SFMT_MAND }, + { FRV_INSN_MXOR, FRVBF_INSN_MXOR, FRVBF_SFMT_MAND }, + { FRV_INSN_CMAND, FRVBF_INSN_CMAND, FRVBF_SFMT_CMAND }, + { FRV_INSN_CMOR, FRVBF_INSN_CMOR, FRVBF_SFMT_CMAND }, + { FRV_INSN_CMXOR, FRVBF_INSN_CMXOR, FRVBF_SFMT_CMAND }, + { FRV_INSN_MNOT, FRVBF_INSN_MNOT, FRVBF_SFMT_MNOT }, + { FRV_INSN_CMNOT, FRVBF_INSN_CMNOT, FRVBF_SFMT_CMNOT }, + { FRV_INSN_MROTLI, FRVBF_INSN_MROTLI, FRVBF_SFMT_MROTLI }, + { FRV_INSN_MROTRI, FRVBF_INSN_MROTRI, FRVBF_SFMT_MROTLI }, + { FRV_INSN_MWCUT, FRVBF_INSN_MWCUT, FRVBF_SFMT_MWCUT }, + { FRV_INSN_MWCUTI, FRVBF_INSN_MWCUTI, FRVBF_SFMT_MWCUTI }, + { FRV_INSN_MCUT, FRVBF_INSN_MCUT, FRVBF_SFMT_MCUT }, + { FRV_INSN_MCUTI, FRVBF_INSN_MCUTI, FRVBF_SFMT_MCUTI }, + { FRV_INSN_MCUTSS, FRVBF_INSN_MCUTSS, FRVBF_SFMT_MCUT }, + { FRV_INSN_MCUTSSI, FRVBF_INSN_MCUTSSI, FRVBF_SFMT_MCUTI }, + { FRV_INSN_MDCUTSSI, FRVBF_INSN_MDCUTSSI, FRVBF_SFMT_MDCUTSSI }, + { FRV_INSN_MAVEH, FRVBF_INSN_MAVEH, FRVBF_SFMT_MAND }, + { FRV_INSN_MSLLHI, FRVBF_INSN_MSLLHI, FRVBF_SFMT_MSLLHI }, + { FRV_INSN_MSRLHI, FRVBF_INSN_MSRLHI, FRVBF_SFMT_MSLLHI }, + { FRV_INSN_MSRAHI, FRVBF_INSN_MSRAHI, FRVBF_SFMT_MSLLHI }, + { FRV_INSN_MDROTLI, FRVBF_INSN_MDROTLI, FRVBF_SFMT_MDROTLI }, + { FRV_INSN_MCPLHI, FRVBF_INSN_MCPLHI, FRVBF_SFMT_MCPLHI }, + { FRV_INSN_MCPLI, FRVBF_INSN_MCPLI, FRVBF_SFMT_MCPLI }, + { FRV_INSN_MSATHS, FRVBF_INSN_MSATHS, FRVBF_SFMT_MSATHS }, + { FRV_INSN_MQSATHS, FRVBF_INSN_MQSATHS, FRVBF_SFMT_MQSATHS }, + { FRV_INSN_MSATHU, FRVBF_INSN_MSATHU, FRVBF_SFMT_MSATHS }, + { FRV_INSN_MCMPSH, FRVBF_INSN_MCMPSH, FRVBF_SFMT_MCMPSH }, + { FRV_INSN_MCMPUH, FRVBF_INSN_MCMPUH, FRVBF_SFMT_MCMPSH }, + { FRV_INSN_MABSHS, FRVBF_INSN_MABSHS, FRVBF_SFMT_MABSHS }, + { FRV_INSN_MADDHSS, FRVBF_INSN_MADDHSS, FRVBF_SFMT_MSATHS }, + { FRV_INSN_MADDHUS, FRVBF_INSN_MADDHUS, FRVBF_SFMT_MSATHS }, + { FRV_INSN_MSUBHSS, FRVBF_INSN_MSUBHSS, FRVBF_SFMT_MSATHS }, + { FRV_INSN_MSUBHUS, FRVBF_INSN_MSUBHUS, FRVBF_SFMT_MSATHS }, + { FRV_INSN_CMADDHSS, FRVBF_INSN_CMADDHSS, FRVBF_SFMT_CMADDHSS }, + { FRV_INSN_CMADDHUS, FRVBF_INSN_CMADDHUS, FRVBF_SFMT_CMADDHSS }, + { FRV_INSN_CMSUBHSS, FRVBF_INSN_CMSUBHSS, FRVBF_SFMT_CMADDHSS }, + { FRV_INSN_CMSUBHUS, FRVBF_INSN_CMSUBHUS, FRVBF_SFMT_CMADDHSS }, + { FRV_INSN_MQADDHSS, FRVBF_INSN_MQADDHSS, FRVBF_SFMT_MQSATHS }, + { FRV_INSN_MQADDHUS, FRVBF_INSN_MQADDHUS, FRVBF_SFMT_MQSATHS }, + { FRV_INSN_MQSUBHSS, FRVBF_INSN_MQSUBHSS, FRVBF_SFMT_MQSATHS }, + { FRV_INSN_MQSUBHUS, FRVBF_INSN_MQSUBHUS, FRVBF_SFMT_MQSATHS }, + { FRV_INSN_CMQADDHSS, FRVBF_INSN_CMQADDHSS, FRVBF_SFMT_CMQADDHSS }, + { FRV_INSN_CMQADDHUS, FRVBF_INSN_CMQADDHUS, FRVBF_SFMT_CMQADDHSS }, + { FRV_INSN_CMQSUBHSS, FRVBF_INSN_CMQSUBHSS, FRVBF_SFMT_CMQADDHSS }, + { FRV_INSN_CMQSUBHUS, FRVBF_INSN_CMQSUBHUS, FRVBF_SFMT_CMQADDHSS }, + { FRV_INSN_MADDACCS, FRVBF_INSN_MADDACCS, FRVBF_SFMT_MADDACCS }, + { FRV_INSN_MSUBACCS, FRVBF_INSN_MSUBACCS, FRVBF_SFMT_MADDACCS }, + { FRV_INSN_MDADDACCS, FRVBF_INSN_MDADDACCS, FRVBF_SFMT_MDADDACCS }, + { FRV_INSN_MDSUBACCS, FRVBF_INSN_MDSUBACCS, FRVBF_SFMT_MDADDACCS }, + { FRV_INSN_MASACCS, FRVBF_INSN_MASACCS, FRVBF_SFMT_MASACCS }, + { FRV_INSN_MDASACCS, FRVBF_INSN_MDASACCS, FRVBF_SFMT_MDASACCS }, + { FRV_INSN_MMULHS, FRVBF_INSN_MMULHS, FRVBF_SFMT_MMULHS }, + { FRV_INSN_MMULHU, FRVBF_INSN_MMULHU, FRVBF_SFMT_MMULHS }, + { FRV_INSN_MMULXHS, FRVBF_INSN_MMULXHS, FRVBF_SFMT_MMULHS }, + { FRV_INSN_MMULXHU, FRVBF_INSN_MMULXHU, FRVBF_SFMT_MMULHS }, + { FRV_INSN_CMMULHS, FRVBF_INSN_CMMULHS, FRVBF_SFMT_CMMULHS }, + { FRV_INSN_CMMULHU, FRVBF_INSN_CMMULHU, FRVBF_SFMT_CMMULHS }, + { FRV_INSN_MQMULHS, FRVBF_INSN_MQMULHS, FRVBF_SFMT_MQMULHS }, + { FRV_INSN_MQMULHU, FRVBF_INSN_MQMULHU, FRVBF_SFMT_MQMULHS }, + { FRV_INSN_MQMULXHS, FRVBF_INSN_MQMULXHS, FRVBF_SFMT_MQMULHS }, + { FRV_INSN_MQMULXHU, FRVBF_INSN_MQMULXHU, FRVBF_SFMT_MQMULHS }, + { FRV_INSN_CMQMULHS, FRVBF_INSN_CMQMULHS, FRVBF_SFMT_CMQMULHS }, + { FRV_INSN_CMQMULHU, FRVBF_INSN_CMQMULHU, FRVBF_SFMT_CMQMULHS }, + { FRV_INSN_MMACHS, FRVBF_INSN_MMACHS, FRVBF_SFMT_MMACHS }, + { FRV_INSN_MMACHU, FRVBF_INSN_MMACHU, FRVBF_SFMT_MMACHU }, + { FRV_INSN_MMRDHS, FRVBF_INSN_MMRDHS, FRVBF_SFMT_MMACHS }, + { FRV_INSN_MMRDHU, FRVBF_INSN_MMRDHU, FRVBF_SFMT_MMACHU }, + { FRV_INSN_CMMACHS, FRVBF_INSN_CMMACHS, FRVBF_SFMT_CMMACHS }, + { FRV_INSN_CMMACHU, FRVBF_INSN_CMMACHU, FRVBF_SFMT_CMMACHU }, + { FRV_INSN_MQMACHS, FRVBF_INSN_MQMACHS, FRVBF_SFMT_MQMACHS }, + { FRV_INSN_MQMACHU, FRVBF_INSN_MQMACHU, FRVBF_SFMT_MQMACHU }, + { FRV_INSN_CMQMACHS, FRVBF_INSN_CMQMACHS, FRVBF_SFMT_CMQMACHS }, + { FRV_INSN_CMQMACHU, FRVBF_INSN_CMQMACHU, FRVBF_SFMT_CMQMACHU }, + { FRV_INSN_MQXMACHS, FRVBF_INSN_MQXMACHS, FRVBF_SFMT_MQMACHS }, + { FRV_INSN_MQXMACXHS, FRVBF_INSN_MQXMACXHS, FRVBF_SFMT_MQMACHS }, + { FRV_INSN_MQMACXHS, FRVBF_INSN_MQMACXHS, FRVBF_SFMT_MQMACHS }, + { FRV_INSN_MCPXRS, FRVBF_INSN_MCPXRS, FRVBF_SFMT_MCPXRS }, + { FRV_INSN_MCPXRU, FRVBF_INSN_MCPXRU, FRVBF_SFMT_MCPXRS }, + { FRV_INSN_MCPXIS, FRVBF_INSN_MCPXIS, FRVBF_SFMT_MCPXRS }, + { FRV_INSN_MCPXIU, FRVBF_INSN_MCPXIU, FRVBF_SFMT_MCPXRS }, + { FRV_INSN_CMCPXRS, FRVBF_INSN_CMCPXRS, FRVBF_SFMT_CMCPXRS }, + { FRV_INSN_CMCPXRU, FRVBF_INSN_CMCPXRU, FRVBF_SFMT_CMCPXRS }, + { FRV_INSN_CMCPXIS, FRVBF_INSN_CMCPXIS, FRVBF_SFMT_CMCPXRS }, + { FRV_INSN_CMCPXIU, FRVBF_INSN_CMCPXIU, FRVBF_SFMT_CMCPXRS }, + { FRV_INSN_MQCPXRS, FRVBF_INSN_MQCPXRS, FRVBF_SFMT_MQCPXRS }, + { FRV_INSN_MQCPXRU, FRVBF_INSN_MQCPXRU, FRVBF_SFMT_MQCPXRS }, + { FRV_INSN_MQCPXIS, FRVBF_INSN_MQCPXIS, FRVBF_SFMT_MQCPXRS }, + { FRV_INSN_MQCPXIU, FRVBF_INSN_MQCPXIU, FRVBF_SFMT_MQCPXRS }, + { FRV_INSN_MEXPDHW, FRVBF_INSN_MEXPDHW, FRVBF_SFMT_MEXPDHW }, + { FRV_INSN_CMEXPDHW, FRVBF_INSN_CMEXPDHW, FRVBF_SFMT_CMEXPDHW }, + { FRV_INSN_MEXPDHD, FRVBF_INSN_MEXPDHD, FRVBF_SFMT_MEXPDHD }, + { FRV_INSN_CMEXPDHD, FRVBF_INSN_CMEXPDHD, FRVBF_SFMT_CMEXPDHD }, + { FRV_INSN_MPACKH, FRVBF_INSN_MPACKH, FRVBF_SFMT_MPACKH }, + { FRV_INSN_MDPACKH, FRVBF_INSN_MDPACKH, FRVBF_SFMT_MDPACKH }, + { FRV_INSN_MUNPACKH, FRVBF_INSN_MUNPACKH, FRVBF_SFMT_MUNPACKH }, + { FRV_INSN_MDUNPACKH, FRVBF_INSN_MDUNPACKH, FRVBF_SFMT_MDUNPACKH }, + { FRV_INSN_MBTOH, FRVBF_INSN_MBTOH, FRVBF_SFMT_MBTOH }, + { FRV_INSN_CMBTOH, FRVBF_INSN_CMBTOH, FRVBF_SFMT_CMBTOH }, + { FRV_INSN_MHTOB, FRVBF_INSN_MHTOB, FRVBF_SFMT_MHTOB }, + { FRV_INSN_CMHTOB, FRVBF_INSN_CMHTOB, FRVBF_SFMT_CMHTOB }, + { FRV_INSN_MBTOHE, FRVBF_INSN_MBTOHE, FRVBF_SFMT_MBTOHE }, + { FRV_INSN_CMBTOHE, FRVBF_INSN_CMBTOHE, FRVBF_SFMT_CMBTOHE }, + { FRV_INSN_MNOP, FRVBF_INSN_MNOP, FRVBF_SFMT_REI }, + { FRV_INSN_MCLRACC_0, FRVBF_INSN_MCLRACC_0, FRVBF_SFMT_MCLRACC_0 }, + { FRV_INSN_MCLRACC_1, FRVBF_INSN_MCLRACC_1, FRVBF_SFMT_MCLRACC_0 }, + { FRV_INSN_MRDACC, FRVBF_INSN_MRDACC, FRVBF_SFMT_MRDACC }, + { FRV_INSN_MRDACCG, FRVBF_INSN_MRDACCG, FRVBF_SFMT_MRDACCG }, + { FRV_INSN_MWTACC, FRVBF_INSN_MWTACC, FRVBF_SFMT_MWTACC }, + { FRV_INSN_MWTACCG, FRVBF_INSN_MWTACCG, FRVBF_SFMT_MWTACCG }, + { FRV_INSN_MCOP1, FRVBF_INSN_MCOP1, FRVBF_SFMT_REI }, + { FRV_INSN_MCOP2, FRVBF_INSN_MCOP2, FRVBF_SFMT_REI }, + { FRV_INSN_FNOP, FRVBF_INSN_FNOP, FRVBF_SFMT_REI }, +}; + +static const struct insn_sem frvbf_insn_sem_invalid = { + VIRTUAL_INSN_X_INVALID, FRVBF_INSN_X_INVALID, FRVBF_SFMT_EMPTY +}; + +/* Initialize an IDESC from the compile-time computable parts. */ + +static INLINE void +init_idesc (SIM_CPU *cpu, IDESC *id, const struct insn_sem *t) +{ + const CGEN_INSN *insn_table = CGEN_CPU_INSN_TABLE (CPU_CPU_DESC (cpu))->init_entries; + + id->num = t->index; + id->sfmt = t->sfmt; + if ((int) t->type <= 0) + id->idata = & cgen_virtual_insn_table[- (int) t->type]; + else + id->idata = & insn_table[t->type]; + id->attrs = CGEN_INSN_ATTRS (id->idata); + /* Oh my god, a magic number. */ + id->length = CGEN_INSN_BITSIZE (id->idata) / 8; + +#if WITH_PROFILE_MODEL_P + id->timing = & MODEL_TIMING (CPU_MODEL (cpu)) [t->index]; + { + SIM_DESC sd = CPU_STATE (cpu); + SIM_ASSERT (t->index == id->timing->num); + } +#endif + + /* Semantic pointers are initialized elsewhere. */ +} + +/* Initialize the instruction descriptor table. */ + +void +frvbf_init_idesc_table (SIM_CPU *cpu) +{ + IDESC *id,*tabend; + const struct insn_sem *t,*tend; + int tabsize = FRVBF_INSN__MAX; + IDESC *table = frvbf_insn_data; + + memset (table, 0, tabsize * sizeof (IDESC)); + + /* First set all entries to the `invalid insn'. */ + t = & frvbf_insn_sem_invalid; + for (id = table, tabend = table + tabsize; id < tabend; ++id) + init_idesc (cpu, id, t); + + /* Now fill in the values for the chosen cpu. */ + for (t = frvbf_insn_sem, tend = t + sizeof (frvbf_insn_sem) / sizeof (*t); + t != tend; ++t) + { + init_idesc (cpu, & table[t->index], t); + } + + /* Link the IDESC table into the cpu. */ + CPU_IDESC (cpu) = table; +} + +/* Given an instruction, return a pointer to its IDESC entry. */ + +const IDESC * +frvbf_decode (SIM_CPU *current_cpu, IADDR pc, + CGEN_INSN_INT base_insn, CGEN_INSN_INT entire_insn, + ARGBUF *abuf) +{ + /* Result of decoder. */ + FRVBF_INSN_TYPE itype; + + { + CGEN_INSN_INT insn = base_insn; + + { + unsigned int val = (((insn >> 18) & (127 << 0))); + switch (val) + { + case 0 : + { + unsigned int val = (((insn >> 6) & (15 << 0))); + switch (val) + { + case 0 : itype = FRVBF_INSN_ADD; goto extract_sfmt_add; + case 1 : itype = FRVBF_INSN_ADDCC; goto extract_sfmt_addcc; + case 2 : itype = FRVBF_INSN_ADDX; goto extract_sfmt_addx; + case 3 : itype = FRVBF_INSN_ADDXCC; goto extract_sfmt_addcc; + case 4 : itype = FRVBF_INSN_SUB; goto extract_sfmt_add; + case 5 : itype = FRVBF_INSN_SUBCC; goto extract_sfmt_addcc; + case 6 : itype = FRVBF_INSN_SUBX; goto extract_sfmt_addx; + case 7 : itype = FRVBF_INSN_SUBXCC; goto extract_sfmt_addcc; + case 8 : itype = FRVBF_INSN_SMUL; goto extract_sfmt_smul; + case 9 : itype = FRVBF_INSN_SMULCC; goto extract_sfmt_smulcc; + case 10 : itype = FRVBF_INSN_UMUL; goto extract_sfmt_smul; + case 11 : itype = FRVBF_INSN_UMULCC; goto extract_sfmt_smulcc; + case 12 : itype = FRVBF_INSN_CMPB; goto extract_sfmt_cmpb; + case 13 : itype = FRVBF_INSN_CMPBA; goto extract_sfmt_cmpb; + case 14 : itype = FRVBF_INSN_SDIV; goto extract_sfmt_sdiv; + case 15 : itype = FRVBF_INSN_UDIV; goto extract_sfmt_sdiv; + default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 1 : + { + unsigned int val = (((insn >> 6) & (15 << 0))); + switch (val) + { + case 0 : itype = FRVBF_INSN_AND; goto extract_sfmt_add; + case 1 : itype = FRVBF_INSN_ANDCC; goto extract_sfmt_andcc; + case 2 : itype = FRVBF_INSN_OR; goto extract_sfmt_add; + case 3 : itype = FRVBF_INSN_ORCC; goto extract_sfmt_andcc; + case 4 : itype = FRVBF_INSN_XOR; goto extract_sfmt_add; + case 5 : itype = FRVBF_INSN_XORCC; goto extract_sfmt_andcc; + case 6 : itype = FRVBF_INSN_NOT; goto extract_sfmt_not; + case 8 : itype = FRVBF_INSN_SLL; goto extract_sfmt_add; + case 9 : itype = FRVBF_INSN_SLLCC; goto extract_sfmt_addcc; + case 10 : itype = FRVBF_INSN_SRL; goto extract_sfmt_add; + case 11 : itype = FRVBF_INSN_SRLCC; goto extract_sfmt_addcc; + case 12 : itype = FRVBF_INSN_SRA; goto extract_sfmt_add; + case 13 : itype = FRVBF_INSN_SRACC; goto extract_sfmt_addcc; + case 14 : itype = FRVBF_INSN_NSDIV; goto extract_sfmt_sdiv; + case 15 : itype = FRVBF_INSN_NUDIV; goto extract_sfmt_sdiv; + default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 2 : + { + unsigned int val = (((insn >> 6) & (63 << 0))); + switch (val) + { + case 0 : itype = FRVBF_INSN_LDSB; goto extract_sfmt_ldsb; + case 1 : itype = FRVBF_INSN_LDUB; goto extract_sfmt_ldsb; + case 2 : itype = FRVBF_INSN_LDSH; goto extract_sfmt_ldsb; + case 3 : itype = FRVBF_INSN_LDUH; goto extract_sfmt_ldsb; + case 4 : itype = FRVBF_INSN_LD; goto extract_sfmt_ldsb; + case 5 : itype = FRVBF_INSN_LDD; goto extract_sfmt_ldd; + case 6 : itype = FRVBF_INSN_LDQ; goto extract_sfmt_ldq; + case 8 : itype = FRVBF_INSN_LDBF; goto extract_sfmt_ldbf; + case 9 : itype = FRVBF_INSN_LDHF; goto extract_sfmt_ldbf; + case 10 : itype = FRVBF_INSN_LDF; goto extract_sfmt_ldbf; + case 11 : itype = FRVBF_INSN_LDDF; goto extract_sfmt_lddf; + case 12 : itype = FRVBF_INSN_LDQF; goto extract_sfmt_ldqf; + case 13 : itype = FRVBF_INSN_LDC; goto extract_sfmt_ldc; + case 14 : itype = FRVBF_INSN_LDDC; goto extract_sfmt_lddc; + case 15 : itype = FRVBF_INSN_LDQC; goto extract_sfmt_ldqc; + case 16 : itype = FRVBF_INSN_LDSBU; goto extract_sfmt_ldsbu; + case 17 : itype = FRVBF_INSN_LDUBU; goto extract_sfmt_ldsbu; + case 18 : itype = FRVBF_INSN_LDSHU; goto extract_sfmt_ldsbu; + case 19 : itype = FRVBF_INSN_LDUHU; goto extract_sfmt_ldsbu; + case 20 : itype = FRVBF_INSN_LDU; goto extract_sfmt_ldsbu; + case 21 : itype = FRVBF_INSN_LDDU; goto extract_sfmt_lddu; + case 22 : itype = FRVBF_INSN_LDQU; goto extract_sfmt_ldqu; + case 24 : itype = FRVBF_INSN_LDBFU; goto extract_sfmt_ldbfu; + case 25 : itype = FRVBF_INSN_LDHFU; goto extract_sfmt_ldbfu; + case 26 : itype = FRVBF_INSN_LDFU; goto extract_sfmt_ldbfu; + case 27 : itype = FRVBF_INSN_LDDFU; goto extract_sfmt_lddfu; + case 28 : itype = FRVBF_INSN_LDQFU; goto extract_sfmt_ldqfu; + case 29 : itype = FRVBF_INSN_LDCU; goto extract_sfmt_ldcu; + case 30 : itype = FRVBF_INSN_LDDCU; goto extract_sfmt_lddcu; + case 31 : itype = FRVBF_INSN_LDQCU; goto extract_sfmt_ldqcu; + case 32 : itype = FRVBF_INSN_NLDSB; goto extract_sfmt_nldsb; + case 33 : itype = FRVBF_INSN_NLDUB; goto extract_sfmt_nldsb; + case 34 : itype = FRVBF_INSN_NLDSH; goto extract_sfmt_nldsb; + case 35 : itype = FRVBF_INSN_NLDUH; goto extract_sfmt_nldsb; + case 36 : itype = FRVBF_INSN_NLD; goto extract_sfmt_nldsb; + case 37 : itype = FRVBF_INSN_NLDD; goto extract_sfmt_nldd; + case 38 : itype = FRVBF_INSN_NLDQ; goto extract_sfmt_nldq; + case 40 : itype = FRVBF_INSN_NLDBF; goto extract_sfmt_nldbf; + case 41 : itype = FRVBF_INSN_NLDHF; goto extract_sfmt_nldbf; + case 42 : itype = FRVBF_INSN_NLDF; goto extract_sfmt_nldbf; + case 43 : itype = FRVBF_INSN_NLDDF; goto extract_sfmt_nlddf; + case 44 : itype = FRVBF_INSN_NLDQF; goto extract_sfmt_nldqf; + case 48 : itype = FRVBF_INSN_NLDSBU; goto extract_sfmt_nldsbu; + case 49 : itype = FRVBF_INSN_NLDUBU; goto extract_sfmt_nldsbu; + case 50 : itype = FRVBF_INSN_NLDSHU; goto extract_sfmt_nldsbu; + case 51 : itype = FRVBF_INSN_NLDUHU; goto extract_sfmt_nldsbu; + case 52 : itype = FRVBF_INSN_NLDU; goto extract_sfmt_nldsbu; + case 53 : itype = FRVBF_INSN_NLDDU; goto extract_sfmt_nlddu; + case 54 : itype = FRVBF_INSN_NLDQU; goto extract_sfmt_nldqu; + case 56 : itype = FRVBF_INSN_NLDBFU; goto extract_sfmt_nldbfu; + case 57 : itype = FRVBF_INSN_NLDHFU; goto extract_sfmt_nldbfu; + case 58 : itype = FRVBF_INSN_NLDFU; goto extract_sfmt_nldbfu; + case 59 : itype = FRVBF_INSN_NLDDFU; goto extract_sfmt_nlddfu; + case 60 : itype = FRVBF_INSN_NLDQFU; goto extract_sfmt_nldqfu; + default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 3 : + { + unsigned int val = (((insn >> 6) & (63 << 0))); + switch (val) + { + case 0 : itype = FRVBF_INSN_STB; goto extract_sfmt_stb; + case 1 : itype = FRVBF_INSN_STH; goto extract_sfmt_stb; + case 2 : itype = FRVBF_INSN_ST; goto extract_sfmt_stb; + case 3 : itype = FRVBF_INSN_STD; goto extract_sfmt_std; + case 4 : itype = FRVBF_INSN_STQ; goto extract_sfmt_ldq; + case 5 : itype = FRVBF_INSN_SWAP; goto extract_sfmt_swap; + case 6 : itype = FRVBF_INSN_MOVGS; goto extract_sfmt_movgs; + case 7 : itype = FRVBF_INSN_MOVSG; goto extract_sfmt_movsg; + case 8 : itype = FRVBF_INSN_STBF; goto extract_sfmt_stbf; + case 9 : itype = FRVBF_INSN_STHF; goto extract_sfmt_stbf; + case 10 : itype = FRVBF_INSN_STF; goto extract_sfmt_stbf; + case 11 : itype = FRVBF_INSN_STDF; goto extract_sfmt_stdf; + case 12 : itype = FRVBF_INSN_STQF; goto extract_sfmt_ldqf; + case 13 : itype = FRVBF_INSN_MOVFG; goto extract_sfmt_movfg; + case 14 : itype = FRVBF_INSN_MOVFGD; goto extract_sfmt_movfgd; + case 15 : itype = FRVBF_INSN_MOVFGQ; goto extract_sfmt_movfgq; + case 16 : itype = FRVBF_INSN_STBU; goto extract_sfmt_stbu; + case 17 : itype = FRVBF_INSN_STHU; goto extract_sfmt_stbu; + case 18 : itype = FRVBF_INSN_STU; goto extract_sfmt_stbu; + case 19 : itype = FRVBF_INSN_STDU; goto extract_sfmt_stdu; + case 20 : itype = FRVBF_INSN_STQU; goto extract_sfmt_stqu; + case 21 : itype = FRVBF_INSN_MOVGF; goto extract_sfmt_movgf; + case 22 : itype = FRVBF_INSN_MOVGFD; goto extract_sfmt_movgfd; + case 23 : itype = FRVBF_INSN_MOVGFQ; goto extract_sfmt_movgfq; + case 24 : itype = FRVBF_INSN_STBFU; goto extract_sfmt_stbfu; + case 25 : itype = FRVBF_INSN_STHFU; goto extract_sfmt_stbfu; + case 26 : itype = FRVBF_INSN_STFU; goto extract_sfmt_stbfu; + case 27 : itype = FRVBF_INSN_STDFU; goto extract_sfmt_stdfu; + case 28 : itype = FRVBF_INSN_STQFU; goto extract_sfmt_ldqfu; + case 32 : itype = FRVBF_INSN_RSTB; goto extract_sfmt_rstb; + case 33 : itype = FRVBF_INSN_RSTH; goto extract_sfmt_rstb; + case 34 : itype = FRVBF_INSN_RST; goto extract_sfmt_rstb; + case 35 : itype = FRVBF_INSN_RSTD; goto extract_sfmt_rstd; + case 36 : itype = FRVBF_INSN_RSTQ; goto extract_sfmt_ldq; + case 37 : itype = FRVBF_INSN_STC; goto extract_sfmt_stc; + case 38 : itype = FRVBF_INSN_STDC; goto extract_sfmt_stdc; + case 39 : itype = FRVBF_INSN_STQC; goto extract_sfmt_ldqc; + case 40 : itype = FRVBF_INSN_RSTBF; goto extract_sfmt_rstbf; + case 41 : itype = FRVBF_INSN_RSTHF; goto extract_sfmt_rstbf; + case 42 : itype = FRVBF_INSN_RSTF; goto extract_sfmt_rstbf; + case 43 : itype = FRVBF_INSN_RSTDF; goto extract_sfmt_rstdf; + case 44 : itype = FRVBF_INSN_RSTQF; goto extract_sfmt_ldqf; + case 45 : itype = FRVBF_INSN_STCU; goto extract_sfmt_stcu; + case 46 : itype = FRVBF_INSN_STDCU; goto extract_sfmt_stdcu; + case 47 : itype = FRVBF_INSN_STQCU; goto extract_sfmt_ldqcu; + case 48 : itype = FRVBF_INSN_ICPL; goto extract_sfmt_icpl; + case 49 : itype = FRVBF_INSN_ICUL; goto extract_sfmt_icul; + case 50 : itype = FRVBF_INSN_WITLB; goto extract_sfmt_rei; + case 51 : itype = FRVBF_INSN_ITLBI; goto extract_sfmt_rei; + case 52 : itype = FRVBF_INSN_DCPL; goto extract_sfmt_icpl; + case 53 : itype = FRVBF_INSN_DCUL; goto extract_sfmt_icul; + case 54 : itype = FRVBF_INSN_WDTLB; goto extract_sfmt_rei; + case 55 : itype = FRVBF_INSN_DTLBI; goto extract_sfmt_rei; + case 56 : itype = FRVBF_INSN_ICI; goto extract_sfmt_ici; + case 57 : itype = FRVBF_INSN_ICEI; goto extract_sfmt_icei; + case 58 : itype = FRVBF_INSN_DCEI; goto extract_sfmt_icei; + case 59 : itype = FRVBF_INSN_DCEF; goto extract_sfmt_icei; + case 60 : itype = FRVBF_INSN_DCI; goto extract_sfmt_ici; + case 61 : itype = FRVBF_INSN_DCF; goto extract_sfmt_ici; + case 62 : itype = FRVBF_INSN_BAR; goto extract_sfmt_rei; + case 63 : itype = FRVBF_INSN_MEMBAR; goto extract_sfmt_rei; + default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 4 : + { + unsigned int val = (((insn >> 25) & (15 << 2)) | ((insn >> 6) & (3 << 0))); + switch (val) + { + case 0 : itype = FRVBF_INSN_TNO; goto extract_sfmt_rei; + case 1 : itype = FRVBF_INSN_FTNO; goto extract_sfmt_rei; + case 2 : itype = FRVBF_INSN_MTRAP; goto extract_sfmt_rei; + case 3 : itype = FRVBF_INSN_BREAK; goto extract_sfmt_break; + case 4 : itype = FRVBF_INSN_TC; goto extract_sfmt_teq; + case 5 : itype = FRVBF_INSN_FTU; goto extract_sfmt_ftne; + case 8 : itype = FRVBF_INSN_TV; goto extract_sfmt_teq; + case 9 : itype = FRVBF_INSN_FTGT; goto extract_sfmt_ftne; + case 12 : itype = FRVBF_INSN_TLT; goto extract_sfmt_teq; + case 13 : itype = FRVBF_INSN_FTUG; goto extract_sfmt_ftne; + case 16 : itype = FRVBF_INSN_TEQ; goto extract_sfmt_teq; + case 17 : itype = FRVBF_INSN_FTLT; goto extract_sfmt_ftne; + case 20 : itype = FRVBF_INSN_TLS; goto extract_sfmt_teq; + case 21 : itype = FRVBF_INSN_FTUL; goto extract_sfmt_ftne; + case 24 : itype = FRVBF_INSN_TN; goto extract_sfmt_teq; + case 25 : itype = FRVBF_INSN_FTLG; goto extract_sfmt_ftne; + case 28 : itype = FRVBF_INSN_TLE; goto extract_sfmt_teq; + case 29 : itype = FRVBF_INSN_FTNE; goto extract_sfmt_ftne; + case 32 : itype = FRVBF_INSN_TRA; goto extract_sfmt_tra; + case 33 : itype = FRVBF_INSN_FTEQ; goto extract_sfmt_ftne; + case 36 : itype = FRVBF_INSN_TNC; goto extract_sfmt_teq; + case 37 : itype = FRVBF_INSN_FTUE; goto extract_sfmt_ftne; + case 40 : itype = FRVBF_INSN_TNV; goto extract_sfmt_teq; + case 41 : itype = FRVBF_INSN_FTGE; goto extract_sfmt_ftne; + case 44 : itype = FRVBF_INSN_TGE; goto extract_sfmt_teq; + case 45 : itype = FRVBF_INSN_FTUGE; goto extract_sfmt_ftne; + case 48 : itype = FRVBF_INSN_TNE; goto extract_sfmt_teq; + case 49 : itype = FRVBF_INSN_FTLE; goto extract_sfmt_ftne; + case 52 : itype = FRVBF_INSN_THI; goto extract_sfmt_teq; + case 53 : itype = FRVBF_INSN_FTULE; goto extract_sfmt_ftne; + case 56 : itype = FRVBF_INSN_TP; goto extract_sfmt_teq; + case 57 : itype = FRVBF_INSN_FTO; goto extract_sfmt_ftne; + case 60 : itype = FRVBF_INSN_TGT; goto extract_sfmt_teq; + case 61 : itype = FRVBF_INSN_FTRA; goto extract_sfmt_tra; + default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 5 : itype = FRVBF_INSN_RETT; goto extract_sfmt_rett; + case 6 : + { + unsigned int val = (((insn >> 27) & (15 << 0))); + switch (val) + { + case 0 : itype = FRVBF_INSN_BNO; goto extract_sfmt_bno; + case 1 : itype = FRVBF_INSN_BC; goto extract_sfmt_beq; + case 2 : itype = FRVBF_INSN_BV; goto extract_sfmt_beq; + case 3 : itype = FRVBF_INSN_BLT; goto extract_sfmt_beq; + case 4 : itype = FRVBF_INSN_BEQ; goto extract_sfmt_beq; + case 5 : itype = FRVBF_INSN_BLS; goto extract_sfmt_beq; + case 6 : itype = FRVBF_INSN_BN; goto extract_sfmt_beq; + case 7 : itype = FRVBF_INSN_BLE; goto extract_sfmt_beq; + case 8 : itype = FRVBF_INSN_BRA; goto extract_sfmt_bra; + case 9 : itype = FRVBF_INSN_BNC; goto extract_sfmt_beq; + case 10 : itype = FRVBF_INSN_BNV; goto extract_sfmt_beq; + case 11 : itype = FRVBF_INSN_BGE; goto extract_sfmt_beq; + case 12 : itype = FRVBF_INSN_BNE; goto extract_sfmt_beq; + case 13 : itype = FRVBF_INSN_BHI; goto extract_sfmt_beq; + case 14 : itype = FRVBF_INSN_BP; goto extract_sfmt_beq; + case 15 : itype = FRVBF_INSN_BGT; goto extract_sfmt_beq; + default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 7 : + { + unsigned int val = (((insn >> 27) & (15 << 0))); + switch (val) + { + case 0 : itype = FRVBF_INSN_FBNO; goto extract_sfmt_bno; + case 1 : itype = FRVBF_INSN_FBU; goto extract_sfmt_fbne; + case 2 : itype = FRVBF_INSN_FBGT; goto extract_sfmt_fbne; + case 3 : itype = FRVBF_INSN_FBUG; goto extract_sfmt_fbne; + case 4 : itype = FRVBF_INSN_FBLT; goto extract_sfmt_fbne; + case 5 : itype = FRVBF_INSN_FBUL; goto extract_sfmt_fbne; + case 6 : itype = FRVBF_INSN_FBLG; goto extract_sfmt_fbne; + case 7 : itype = FRVBF_INSN_FBNE; goto extract_sfmt_fbne; + case 8 : itype = FRVBF_INSN_FBEQ; goto extract_sfmt_fbne; + case 9 : itype = FRVBF_INSN_FBUE; goto extract_sfmt_fbne; + case 10 : itype = FRVBF_INSN_FBGE; goto extract_sfmt_fbne; + case 11 : itype = FRVBF_INSN_FBUGE; goto extract_sfmt_fbne; + case 12 : itype = FRVBF_INSN_FBLE; goto extract_sfmt_fbne; + case 13 : itype = FRVBF_INSN_FBULE; goto extract_sfmt_fbne; + case 14 : itype = FRVBF_INSN_FBO; goto extract_sfmt_fbne; + case 15 : itype = FRVBF_INSN_FBRA; goto extract_sfmt_bra; + default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 8 : + { + unsigned int val = (((insn >> 27) & (15 << 0))); + switch (val) + { + case 0 : itype = FRVBF_INSN_CKNO; goto extract_sfmt_ckra; + case 1 : itype = FRVBF_INSN_CKC; goto extract_sfmt_ckeq; + case 2 : itype = FRVBF_INSN_CKV; goto extract_sfmt_ckeq; + case 3 : itype = FRVBF_INSN_CKLT; goto extract_sfmt_ckeq; + case 4 : itype = FRVBF_INSN_CKEQ; goto extract_sfmt_ckeq; + case 5 : itype = FRVBF_INSN_CKLS; goto extract_sfmt_ckeq; + case 6 : itype = FRVBF_INSN_CKN; goto extract_sfmt_ckeq; + case 7 : itype = FRVBF_INSN_CKLE; goto extract_sfmt_ckeq; + case 8 : itype = FRVBF_INSN_CKRA; goto extract_sfmt_ckra; + case 9 : itype = FRVBF_INSN_CKNC; goto extract_sfmt_ckeq; + case 10 : itype = FRVBF_INSN_CKNV; goto extract_sfmt_ckeq; + case 11 : itype = FRVBF_INSN_CKGE; goto extract_sfmt_ckeq; + case 12 : itype = FRVBF_INSN_CKNE; goto extract_sfmt_ckeq; + case 13 : itype = FRVBF_INSN_CKHI; goto extract_sfmt_ckeq; + case 14 : itype = FRVBF_INSN_CKP; goto extract_sfmt_ckeq; + case 15 : itype = FRVBF_INSN_CKGT; goto extract_sfmt_ckeq; + default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 9 : + { + unsigned int val = (((insn >> 27) & (15 << 0))); + switch (val) + { + case 0 : itype = FRVBF_INSN_FCKNO; goto extract_sfmt_fckra; + case 1 : itype = FRVBF_INSN_FCKU; goto extract_sfmt_fckne; + case 2 : itype = FRVBF_INSN_FCKGT; goto extract_sfmt_fckne; + case 3 : itype = FRVBF_INSN_FCKUG; goto extract_sfmt_fckne; + case 4 : itype = FRVBF_INSN_FCKLT; goto extract_sfmt_fckne; + case 5 : itype = FRVBF_INSN_FCKUL; goto extract_sfmt_fckne; + case 6 : itype = FRVBF_INSN_FCKLG; goto extract_sfmt_fckne; + case 7 : itype = FRVBF_INSN_FCKNE; goto extract_sfmt_fckne; + case 8 : itype = FRVBF_INSN_FCKEQ; goto extract_sfmt_fckne; + case 9 : itype = FRVBF_INSN_FCKUE; goto extract_sfmt_fckne; + case 10 : itype = FRVBF_INSN_FCKGE; goto extract_sfmt_fckne; + case 11 : itype = FRVBF_INSN_FCKUGE; goto extract_sfmt_fckne; + case 12 : itype = FRVBF_INSN_FCKLE; goto extract_sfmt_fckne; + case 13 : itype = FRVBF_INSN_FCKULE; goto extract_sfmt_fckne; + case 14 : itype = FRVBF_INSN_FCKO; goto extract_sfmt_fckne; + case 15 : itype = FRVBF_INSN_FCKRA; goto extract_sfmt_fckra; + default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 10 : + { + unsigned int val = (((insn >> 6) & (31 << 0))); + switch (val) + { + case 0 : itype = FRVBF_INSN_CLRGR; goto extract_sfmt_clrgr; + case 1 : itype = FRVBF_INSN_CLRGA; goto extract_sfmt_rei; + case 2 : itype = FRVBF_INSN_CLRFR; goto extract_sfmt_clrfr; + case 3 : itype = FRVBF_INSN_CLRFA; goto extract_sfmt_rei; + case 4 : itype = FRVBF_INSN_COMMITGR; goto extract_sfmt_commitgr; + case 5 : itype = FRVBF_INSN_COMMITGA; goto extract_sfmt_rei; + case 6 : itype = FRVBF_INSN_COMMITFR; goto extract_sfmt_commitfr; + case 7 : itype = FRVBF_INSN_COMMITFA; goto extract_sfmt_rei; + case 8 : itype = FRVBF_INSN_ANDCR; goto extract_sfmt_andcr; + case 9 : itype = FRVBF_INSN_ORCR; goto extract_sfmt_andcr; + case 10 : itype = FRVBF_INSN_XORCR; goto extract_sfmt_andcr; + case 11 : itype = FRVBF_INSN_NOTCR; goto extract_sfmt_notcr; + case 12 : itype = FRVBF_INSN_NANDCR; goto extract_sfmt_andcr; + case 13 : itype = FRVBF_INSN_NORCR; goto extract_sfmt_andcr; + case 16 : itype = FRVBF_INSN_ANDNCR; goto extract_sfmt_andcr; + case 17 : itype = FRVBF_INSN_ORNCR; goto extract_sfmt_andcr; + case 20 : itype = FRVBF_INSN_NANDNCR; goto extract_sfmt_andcr; + case 21 : itype = FRVBF_INSN_NORNCR; goto extract_sfmt_andcr; + default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 11 : itype = FRVBF_INSN_SCAN; goto extract_sfmt_add; + case 12 : + { + unsigned int val = (((insn >> 25) & (1 << 0))); + switch (val) + { + case 0 : itype = FRVBF_INSN_JMPL; goto extract_sfmt_jmpl; + case 1 : itype = FRVBF_INSN_CALLL; goto extract_sfmt_jmpl; + default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 13 : + { + unsigned int val = (((insn >> 25) & (1 << 0))); + switch (val) + { + case 0 : itype = FRVBF_INSN_JMPIL; goto extract_sfmt_jmpil; + case 1 : itype = FRVBF_INSN_CALLIL; goto extract_sfmt_jmpil; + default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 14 : + { + unsigned int val = (((insn >> 25) & (15 << 2)) | ((insn >> 14) & (1 << 1)) | ((insn >> 13) & (1 << 0))); + switch (val) + { + case 0 : itype = FRVBF_INSN_BNOLR; goto extract_sfmt_bnolr; + case 1 : + { + unsigned int val = (((insn >> 14) & (1 << 0))); + switch (val) + { + case 0 : itype = FRVBF_INSN_BCTRLR; goto extract_sfmt_bctrlr; + case 1 : itype = FRVBF_INSN_BCNOLR; goto extract_sfmt_bcnolr; + default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 2 : itype = FRVBF_INSN_FBNOLR; goto extract_sfmt_bnolr; + case 3 : itype = FRVBF_INSN_FCBNOLR; goto extract_sfmt_bcnolr; + case 4 : itype = FRVBF_INSN_BCLR; goto extract_sfmt_beqlr; + case 5 : itype = FRVBF_INSN_BCCLR; goto extract_sfmt_bceqlr; + case 6 : itype = FRVBF_INSN_FBULR; goto extract_sfmt_fbeqlr; + case 7 : itype = FRVBF_INSN_FCBULR; goto extract_sfmt_fcbeqlr; + case 8 : itype = FRVBF_INSN_BVLR; goto extract_sfmt_beqlr; + case 9 : itype = FRVBF_INSN_BCVLR; goto extract_sfmt_bceqlr; + case 10 : itype = FRVBF_INSN_FBGTLR; goto extract_sfmt_fbeqlr; + case 11 : itype = FRVBF_INSN_FCBGTLR; goto extract_sfmt_fcbeqlr; + case 12 : itype = FRVBF_INSN_BLTLR; goto extract_sfmt_beqlr; + case 13 : itype = FRVBF_INSN_BCLTLR; goto extract_sfmt_bceqlr; + case 14 : itype = FRVBF_INSN_FBUGLR; goto extract_sfmt_fbeqlr; + case 15 : itype = FRVBF_INSN_FCBUGLR; goto extract_sfmt_fcbeqlr; + case 16 : itype = FRVBF_INSN_BEQLR; goto extract_sfmt_beqlr; + case 17 : itype = FRVBF_INSN_BCEQLR; goto extract_sfmt_bceqlr; + case 18 : itype = FRVBF_INSN_FBLTLR; goto extract_sfmt_fbeqlr; + case 19 : itype = FRVBF_INSN_FCBLTLR; goto extract_sfmt_fcbeqlr; + case 20 : itype = FRVBF_INSN_BLSLR; goto extract_sfmt_beqlr; + case 21 : itype = FRVBF_INSN_BCLSLR; goto extract_sfmt_bceqlr; + case 22 : itype = FRVBF_INSN_FBULLR; goto extract_sfmt_fbeqlr; + case 23 : itype = FRVBF_INSN_FCBULLR; goto extract_sfmt_fcbeqlr; + case 24 : itype = FRVBF_INSN_BNLR; goto extract_sfmt_beqlr; + case 25 : itype = FRVBF_INSN_BCNLR; goto extract_sfmt_bceqlr; + case 26 : itype = FRVBF_INSN_FBLGLR; goto extract_sfmt_fbeqlr; + case 27 : itype = FRVBF_INSN_FCBLGLR; goto extract_sfmt_fcbeqlr; + case 28 : itype = FRVBF_INSN_BLELR; goto extract_sfmt_beqlr; + case 29 : itype = FRVBF_INSN_BCLELR; goto extract_sfmt_bceqlr; + case 30 : itype = FRVBF_INSN_FBNELR; goto extract_sfmt_fbeqlr; + case 31 : itype = FRVBF_INSN_FCBNELR; goto extract_sfmt_fcbeqlr; + case 32 : itype = FRVBF_INSN_BRALR; goto extract_sfmt_bralr; + case 33 : itype = FRVBF_INSN_BCRALR; goto extract_sfmt_bcralr; + case 34 : itype = FRVBF_INSN_FBEQLR; goto extract_sfmt_fbeqlr; + case 35 : itype = FRVBF_INSN_FCBEQLR; goto extract_sfmt_fcbeqlr; + case 36 : itype = FRVBF_INSN_BNCLR; goto extract_sfmt_beqlr; + case 37 : itype = FRVBF_INSN_BCNCLR; goto extract_sfmt_bceqlr; + case 38 : itype = FRVBF_INSN_FBUELR; goto extract_sfmt_fbeqlr; + case 39 : itype = FRVBF_INSN_FCBUELR; goto extract_sfmt_fcbeqlr; + case 40 : itype = FRVBF_INSN_BNVLR; goto extract_sfmt_beqlr; + case 41 : itype = FRVBF_INSN_BCNVLR; goto extract_sfmt_bceqlr; + case 42 : itype = FRVBF_INSN_FBGELR; goto extract_sfmt_fbeqlr; + case 43 : itype = FRVBF_INSN_FCBGELR; goto extract_sfmt_fcbeqlr; + case 44 : itype = FRVBF_INSN_BGELR; goto extract_sfmt_beqlr; + case 45 : itype = FRVBF_INSN_BCGELR; goto extract_sfmt_bceqlr; + case 46 : itype = FRVBF_INSN_FBUGELR; goto extract_sfmt_fbeqlr; + case 47 : itype = FRVBF_INSN_FCBUGELR; goto extract_sfmt_fcbeqlr; + case 48 : itype = FRVBF_INSN_BNELR; goto extract_sfmt_beqlr; + case 49 : itype = FRVBF_INSN_BCNELR; goto extract_sfmt_bceqlr; + case 50 : itype = FRVBF_INSN_FBLELR; goto extract_sfmt_fbeqlr; + case 51 : itype = FRVBF_INSN_FCBLELR; goto extract_sfmt_fcbeqlr; + case 52 : itype = FRVBF_INSN_BHILR; goto extract_sfmt_beqlr; + case 53 : itype = FRVBF_INSN_BCHILR; goto extract_sfmt_bceqlr; + case 54 : itype = FRVBF_INSN_FBULELR; goto extract_sfmt_fbeqlr; + case 55 : itype = FRVBF_INSN_FCBULELR; goto extract_sfmt_fcbeqlr; + case 56 : itype = FRVBF_INSN_BPLR; goto extract_sfmt_beqlr; + case 57 : itype = FRVBF_INSN_BCPLR; goto extract_sfmt_bceqlr; + case 58 : itype = FRVBF_INSN_FBOLR; goto extract_sfmt_fbeqlr; + case 59 : itype = FRVBF_INSN_FCBOLR; goto extract_sfmt_fcbeqlr; + case 60 : itype = FRVBF_INSN_BGTLR; goto extract_sfmt_beqlr; + case 61 : itype = FRVBF_INSN_BCGTLR; goto extract_sfmt_bceqlr; + case 62 : itype = FRVBF_INSN_FBRALR; goto extract_sfmt_bralr; + case 63 : itype = FRVBF_INSN_FCBRALR; goto extract_sfmt_bcralr; + default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 15 : itype = FRVBF_INSN_CALL; goto extract_sfmt_call; + case 16 : itype = FRVBF_INSN_ADDI; goto extract_sfmt_addi; + case 17 : itype = FRVBF_INSN_ADDICC; goto extract_sfmt_addicc; + case 18 : itype = FRVBF_INSN_ADDXI; goto extract_sfmt_addxi; + case 19 : itype = FRVBF_INSN_ADDXICC; goto extract_sfmt_addicc; + case 20 : itype = FRVBF_INSN_SUBI; goto extract_sfmt_addi; + case 21 : itype = FRVBF_INSN_SUBICC; goto extract_sfmt_addicc; + case 22 : itype = FRVBF_INSN_SUBXI; goto extract_sfmt_addxi; + case 23 : itype = FRVBF_INSN_SUBXICC; goto extract_sfmt_addicc; + case 24 : itype = FRVBF_INSN_SMULI; goto extract_sfmt_smuli; + case 25 : itype = FRVBF_INSN_SMULICC; goto extract_sfmt_smulicc; + case 26 : itype = FRVBF_INSN_UMULI; goto extract_sfmt_smuli; + case 27 : itype = FRVBF_INSN_UMULICC; goto extract_sfmt_smulicc; + case 28 : + { + unsigned int val = (((insn >> 27) & (15 << 0))); + switch (val) + { + case 0 : itype = FRVBF_INSN_TINO; goto extract_sfmt_rei; + case 1 : itype = FRVBF_INSN_TIC; goto extract_sfmt_tieq; + case 2 : itype = FRVBF_INSN_TIV; goto extract_sfmt_tieq; + case 3 : itype = FRVBF_INSN_TILT; goto extract_sfmt_tieq; + case 4 : itype = FRVBF_INSN_TIEQ; goto extract_sfmt_tieq; + case 5 : itype = FRVBF_INSN_TILS; goto extract_sfmt_tieq; + case 6 : itype = FRVBF_INSN_TIN; goto extract_sfmt_tieq; + case 7 : itype = FRVBF_INSN_TILE; goto extract_sfmt_tieq; + case 8 : itype = FRVBF_INSN_TIRA; goto extract_sfmt_tira; + case 9 : itype = FRVBF_INSN_TINC; goto extract_sfmt_tieq; + case 10 : itype = FRVBF_INSN_TINV; goto extract_sfmt_tieq; + case 11 : itype = FRVBF_INSN_TIGE; goto extract_sfmt_tieq; + case 12 : itype = FRVBF_INSN_TINE; goto extract_sfmt_tieq; + case 13 : itype = FRVBF_INSN_TIHI; goto extract_sfmt_tieq; + case 14 : itype = FRVBF_INSN_TIP; goto extract_sfmt_tieq; + case 15 : itype = FRVBF_INSN_TIGT; goto extract_sfmt_tieq; + default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 29 : + { + unsigned int val = (((insn >> 27) & (15 << 0))); + switch (val) + { + case 0 : itype = FRVBF_INSN_FTINO; goto extract_sfmt_rei; + case 1 : itype = FRVBF_INSN_FTIU; goto extract_sfmt_ftine; + case 2 : itype = FRVBF_INSN_FTIGT; goto extract_sfmt_ftine; + case 3 : itype = FRVBF_INSN_FTIUG; goto extract_sfmt_ftine; + case 4 : itype = FRVBF_INSN_FTILT; goto extract_sfmt_ftine; + case 5 : itype = FRVBF_INSN_FTIUL; goto extract_sfmt_ftine; + case 6 : itype = FRVBF_INSN_FTILG; goto extract_sfmt_ftine; + case 7 : itype = FRVBF_INSN_FTINE; goto extract_sfmt_ftine; + case 8 : itype = FRVBF_INSN_FTIEQ; goto extract_sfmt_ftine; + case 9 : itype = FRVBF_INSN_FTIUE; goto extract_sfmt_ftine; + case 10 : itype = FRVBF_INSN_FTIGE; goto extract_sfmt_ftine; + case 11 : itype = FRVBF_INSN_FTIUGE; goto extract_sfmt_ftine; + case 12 : itype = FRVBF_INSN_FTILE; goto extract_sfmt_ftine; + case 13 : itype = FRVBF_INSN_FTIULE; goto extract_sfmt_ftine; + case 14 : itype = FRVBF_INSN_FTIO; goto extract_sfmt_ftine; + case 15 : itype = FRVBF_INSN_FTIRA; goto extract_sfmt_tira; + default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 30 : itype = FRVBF_INSN_SDIVI; goto extract_sfmt_sdivi; + case 31 : itype = FRVBF_INSN_UDIVI; goto extract_sfmt_sdivi; + case 32 : itype = FRVBF_INSN_ANDI; goto extract_sfmt_addi; + case 33 : itype = FRVBF_INSN_ANDICC; goto extract_sfmt_andicc; + case 34 : itype = FRVBF_INSN_ORI; goto extract_sfmt_addi; + case 35 : itype = FRVBF_INSN_ORICC; goto extract_sfmt_andicc; + case 36 : itype = FRVBF_INSN_XORI; goto extract_sfmt_addi; + case 37 : itype = FRVBF_INSN_XORICC; goto extract_sfmt_andicc; + case 40 : itype = FRVBF_INSN_SLLI; goto extract_sfmt_addi; + case 41 : itype = FRVBF_INSN_SLLICC; goto extract_sfmt_addicc; + case 42 : itype = FRVBF_INSN_SRLI; goto extract_sfmt_addi; + case 43 : itype = FRVBF_INSN_SRLICC; goto extract_sfmt_addicc; + case 44 : itype = FRVBF_INSN_SRAI; goto extract_sfmt_addi; + case 45 : itype = FRVBF_INSN_SRAICC; goto extract_sfmt_addicc; + case 46 : itype = FRVBF_INSN_NSDIVI; goto extract_sfmt_sdivi; + case 47 : itype = FRVBF_INSN_NUDIVI; goto extract_sfmt_sdivi; + case 48 : itype = FRVBF_INSN_LDSBI; goto extract_sfmt_ldsbi; + case 49 : itype = FRVBF_INSN_LDSHI; goto extract_sfmt_ldsbi; + case 50 : itype = FRVBF_INSN_LDI; goto extract_sfmt_ldsbi; + case 51 : itype = FRVBF_INSN_LDDI; goto extract_sfmt_lddi; + case 52 : itype = FRVBF_INSN_LDQI; goto extract_sfmt_ldqi; + case 53 : itype = FRVBF_INSN_LDUBI; goto extract_sfmt_ldsbi; + case 54 : itype = FRVBF_INSN_LDUHI; goto extract_sfmt_ldsbi; + case 55 : itype = FRVBF_INSN_REI; goto extract_sfmt_rei; + case 56 : itype = FRVBF_INSN_LDBFI; goto extract_sfmt_ldbfi; + case 57 : itype = FRVBF_INSN_LDHFI; goto extract_sfmt_ldbfi; + case 58 : itype = FRVBF_INSN_LDFI; goto extract_sfmt_ldbfi; + case 59 : itype = FRVBF_INSN_LDDFI; goto extract_sfmt_lddfi; + case 60 : itype = FRVBF_INSN_LDQFI; goto extract_sfmt_ldqfi; + case 61 : itype = FRVBF_INSN_SETLO; goto extract_sfmt_setlo; + case 62 : itype = FRVBF_INSN_SETHI; goto extract_sfmt_sethi; + case 63 : itype = FRVBF_INSN_SETLOS; goto extract_sfmt_setlos; + case 64 : itype = FRVBF_INSN_NLDSBI; goto extract_sfmt_nldsbi; + case 65 : itype = FRVBF_INSN_NLDUBI; goto extract_sfmt_nldsbi; + case 66 : itype = FRVBF_INSN_NLDSHI; goto extract_sfmt_nldsbi; + case 67 : itype = FRVBF_INSN_NLDUHI; goto extract_sfmt_nldsbi; + case 68 : itype = FRVBF_INSN_NLDI; goto extract_sfmt_nldsbi; + case 69 : itype = FRVBF_INSN_NLDDI; goto extract_sfmt_nlddi; + case 70 : + { + unsigned int val = (((insn >> 6) & (7 << 0))); + switch (val) + { + case 0 : itype = FRVBF_INSN_ADDSS; goto extract_sfmt_add; + case 1 : itype = FRVBF_INSN_SUBSS; goto extract_sfmt_add; + case 2 : itype = FRVBF_INSN_SLASS; goto extract_sfmt_add; + case 4 : itype = FRVBF_INSN_SCUTSS; goto extract_sfmt_scutss; + case 5 : itype = FRVBF_INSN_SMU; goto extract_sfmt_smu; + case 6 : itype = FRVBF_INSN_SMASS; goto extract_sfmt_smass; + case 7 : itype = FRVBF_INSN_SMSSS; goto extract_sfmt_smass; + default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 71 : itype = FRVBF_INSN_SCANI; goto extract_sfmt_addi; + case 72 : itype = FRVBF_INSN_NLDBFI; goto extract_sfmt_nldbfi; + case 73 : itype = FRVBF_INSN_NLDHFI; goto extract_sfmt_nldbfi; + case 74 : itype = FRVBF_INSN_NLDFI; goto extract_sfmt_nldbfi; + case 75 : itype = FRVBF_INSN_NLDDFI; goto extract_sfmt_nlddfi; + case 76 : itype = FRVBF_INSN_NLDQFI; goto extract_sfmt_nldqfi; + case 77 : itype = FRVBF_INSN_SWAPI; goto extract_sfmt_swapi; + case 78 : itype = FRVBF_INSN_STBFI; goto extract_sfmt_stbfi; + case 79 : itype = FRVBF_INSN_STHFI; goto extract_sfmt_stbfi; + case 80 : itype = FRVBF_INSN_STBI; goto extract_sfmt_stbi; + case 81 : itype = FRVBF_INSN_STHI; goto extract_sfmt_stbi; + case 82 : itype = FRVBF_INSN_STI; goto extract_sfmt_stbi; + case 83 : itype = FRVBF_INSN_STDI; goto extract_sfmt_stdi; + case 84 : itype = FRVBF_INSN_STQI; goto extract_sfmt_ldqi; + case 85 : itype = FRVBF_INSN_STFI; goto extract_sfmt_stbfi; + case 86 : itype = FRVBF_INSN_STDFI; goto extract_sfmt_stdfi; + case 87 : itype = FRVBF_INSN_STQFI; goto extract_sfmt_ldqfi; + case 88 : + { + unsigned int val = (((insn >> 6) & (3 << 0))); + switch (val) + { + case 0 : itype = FRVBF_INSN_CADD; goto extract_sfmt_cadd; + case 1 : itype = FRVBF_INSN_CSUB; goto extract_sfmt_cadd; + case 2 : itype = FRVBF_INSN_CSMUL; goto extract_sfmt_csmul; + case 3 : itype = FRVBF_INSN_CSDIV; goto extract_sfmt_csdiv; + default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 89 : + { + unsigned int val = (((insn >> 6) & (3 << 0))); + switch (val) + { + case 0 : itype = FRVBF_INSN_CADDCC; goto extract_sfmt_caddcc; + case 1 : itype = FRVBF_INSN_CSUBCC; goto extract_sfmt_caddcc; + case 2 : itype = FRVBF_INSN_CSMULCC; goto extract_sfmt_csmulcc; + case 3 : itype = FRVBF_INSN_CUDIV; goto extract_sfmt_csdiv; + default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 90 : + { + unsigned int val = (((insn >> 6) & (3 << 0))); + switch (val) + { + case 0 : itype = FRVBF_INSN_CAND; goto extract_sfmt_cadd; + case 1 : itype = FRVBF_INSN_COR; goto extract_sfmt_cadd; + case 2 : itype = FRVBF_INSN_CXOR; goto extract_sfmt_cadd; + case 3 : itype = FRVBF_INSN_CNOT; goto extract_sfmt_cnot; + default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 91 : + { + unsigned int val = (((insn >> 6) & (3 << 0))); + switch (val) + { + case 0 : itype = FRVBF_INSN_CANDCC; goto extract_sfmt_caddcc; + case 1 : itype = FRVBF_INSN_CORCC; goto extract_sfmt_caddcc; + case 2 : itype = FRVBF_INSN_CXORCC; goto extract_sfmt_caddcc; + default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 92 : + { + unsigned int val = (((insn >> 6) & (3 << 0))); + switch (val) + { + case 0 : itype = FRVBF_INSN_CSLL; goto extract_sfmt_cadd; + case 1 : itype = FRVBF_INSN_CSRL; goto extract_sfmt_cadd; + case 2 : itype = FRVBF_INSN_CSRA; goto extract_sfmt_cadd; + default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 93 : + { + unsigned int val = (((insn >> 6) & (3 << 0))); + switch (val) + { + case 0 : itype = FRVBF_INSN_CSLLCC; goto extract_sfmt_caddcc; + case 1 : itype = FRVBF_INSN_CSRLCC; goto extract_sfmt_caddcc; + case 2 : itype = FRVBF_INSN_CSRACC; goto extract_sfmt_caddcc; + default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 94 : + { + unsigned int val = (((insn >> 6) & (3 << 0))); + switch (val) + { + case 0 : itype = FRVBF_INSN_CLDSB; goto extract_sfmt_cldsb; + case 1 : itype = FRVBF_INSN_CLDUB; goto extract_sfmt_cldsb; + case 2 : itype = FRVBF_INSN_CLDSH; goto extract_sfmt_cldsb; + case 3 : itype = FRVBF_INSN_CLDUH; goto extract_sfmt_cldsb; + default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 95 : + { + unsigned int val = (((insn >> 6) & (3 << 0))); + switch (val) + { + case 0 : itype = FRVBF_INSN_CLD; goto extract_sfmt_cldsb; + case 1 : itype = FRVBF_INSN_CLDD; goto extract_sfmt_cldd; + case 2 : itype = FRVBF_INSN_CLDQ; goto extract_sfmt_cldq; + default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 96 : + { + unsigned int val = (((insn >> 6) & (3 << 0))); + switch (val) + { + case 0 : itype = FRVBF_INSN_CLDBF; goto extract_sfmt_cldbf; + case 1 : itype = FRVBF_INSN_CLDHF; goto extract_sfmt_cldbf; + case 2 : itype = FRVBF_INSN_CLDF; goto extract_sfmt_cldbf; + case 3 : itype = FRVBF_INSN_CLDDF; goto extract_sfmt_clddf; + default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 97 : + { + unsigned int val = (((insn >> 6) & (3 << 0))); + switch (val) + { + case 0 : itype = FRVBF_INSN_CLDSBU; goto extract_sfmt_cldsbu; + case 1 : itype = FRVBF_INSN_CLDUBU; goto extract_sfmt_cldsbu; + case 2 : itype = FRVBF_INSN_CLDSHU; goto extract_sfmt_cldsbu; + case 3 : itype = FRVBF_INSN_CLDUHU; goto extract_sfmt_cldsbu; + default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 98 : + { + unsigned int val = (((insn >> 6) & (3 << 0))); + switch (val) + { + case 0 : itype = FRVBF_INSN_CLDU; goto extract_sfmt_cldsbu; + case 1 : itype = FRVBF_INSN_CLDDU; goto extract_sfmt_clddu; + case 2 : itype = FRVBF_INSN_CLDQU; goto extract_sfmt_cldqu; + default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 99 : + { + unsigned int val = (((insn >> 6) & (3 << 0))); + switch (val) + { + case 0 : itype = FRVBF_INSN_CLDBFU; goto extract_sfmt_cldbfu; + case 1 : itype = FRVBF_INSN_CLDHFU; goto extract_sfmt_cldbfu; + case 2 : itype = FRVBF_INSN_CLDFU; goto extract_sfmt_cldbfu; + case 3 : itype = FRVBF_INSN_CLDDFU; goto extract_sfmt_clddfu; + default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 100 : + { + unsigned int val = (((insn >> 6) & (3 << 0))); + switch (val) + { + case 0 : itype = FRVBF_INSN_CSTB; goto extract_sfmt_cstb; + case 1 : itype = FRVBF_INSN_CSTH; goto extract_sfmt_cstb; + case 2 : itype = FRVBF_INSN_CST; goto extract_sfmt_cstb; + case 3 : itype = FRVBF_INSN_CSTD; goto extract_sfmt_cstd; + default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 101 : + { + unsigned int val = (((insn >> 6) & (3 << 0))); + switch (val) + { + case 0 : itype = FRVBF_INSN_CSTQ; goto extract_sfmt_cldq; + case 2 : itype = FRVBF_INSN_CSWAP; goto extract_sfmt_cswap; + case 3 : itype = FRVBF_INSN_CSCAN; goto extract_sfmt_cadd; + default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 102 : + { + unsigned int val = (((insn >> 6) & (3 << 0))); + switch (val) + { + case 0 : itype = FRVBF_INSN_CSTBF; goto extract_sfmt_cstbf; + case 1 : itype = FRVBF_INSN_CSTHF; goto extract_sfmt_cstbf; + case 2 : itype = FRVBF_INSN_CSTF; goto extract_sfmt_cstbf; + case 3 : itype = FRVBF_INSN_CSTDF; goto extract_sfmt_cstdf; + default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 103 : + { + unsigned int val = (((insn >> 6) & (3 << 0))); + switch (val) + { + case 0 : itype = FRVBF_INSN_CSTBU; goto extract_sfmt_cstbu; + case 1 : itype = FRVBF_INSN_CSTHU; goto extract_sfmt_cstbu; + case 2 : itype = FRVBF_INSN_CSTU; goto extract_sfmt_cstbu; + case 3 : itype = FRVBF_INSN_CSTDU; goto extract_sfmt_cstdu; + default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 104 : + { + unsigned int val = (((insn >> 6) & (3 << 0))); + switch (val) + { + case 0 : itype = FRVBF_INSN_CSTBFU; goto extract_sfmt_cstbfu; + case 1 : itype = FRVBF_INSN_CSTHFU; goto extract_sfmt_cstbfu; + case 2 : itype = FRVBF_INSN_CSTFU; goto extract_sfmt_cstbfu; + case 3 : itype = FRVBF_INSN_CSTDFU; goto extract_sfmt_cstdfu; + default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 105 : + { + unsigned int val = (((insn >> 6) & (3 << 0))); + switch (val) + { + case 0 : itype = FRVBF_INSN_CMOVGF; goto extract_sfmt_cmovgf; + case 1 : itype = FRVBF_INSN_CMOVGFD; goto extract_sfmt_cmovgfd; + case 2 : itype = FRVBF_INSN_CMOVFG; goto extract_sfmt_cmovfg; + case 3 : itype = FRVBF_INSN_CMOVFGD; goto extract_sfmt_cmovfgd; + default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 106 : + { + unsigned int val = (((insn >> 26) & (15 << 1)) | ((insn >> 6) & (1 << 0))); + switch (val) + { + case 0 : + { + unsigned int val = (((insn >> 24) & (1 << 1)) | ((insn >> 7) & (1 << 0))); + switch (val) + { + case 0 : /* fall through */ + case 2 : itype = FRVBF_INSN_CCKNO; goto extract_sfmt_cckra; + case 1 : itype = FRVBF_INSN_CJMPL; goto extract_sfmt_cjmpl; + case 3 : itype = FRVBF_INSN_CCALLL; goto extract_sfmt_cjmpl; + default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 1 : itype = FRVBF_INSN_CFCKNO; goto extract_sfmt_cfckra; + case 2 : itype = FRVBF_INSN_CCKC; goto extract_sfmt_cckeq; + case 3 : itype = FRVBF_INSN_CFCKU; goto extract_sfmt_cfckne; + case 4 : itype = FRVBF_INSN_CCKV; goto extract_sfmt_cckeq; + case 5 : itype = FRVBF_INSN_CFCKGT; goto extract_sfmt_cfckne; + case 6 : itype = FRVBF_INSN_CCKLT; goto extract_sfmt_cckeq; + case 7 : itype = FRVBF_INSN_CFCKUG; goto extract_sfmt_cfckne; + case 8 : itype = FRVBF_INSN_CCKEQ; goto extract_sfmt_cckeq; + case 9 : itype = FRVBF_INSN_CFCKLT; goto extract_sfmt_cfckne; + case 10 : itype = FRVBF_INSN_CCKLS; goto extract_sfmt_cckeq; + case 11 : itype = FRVBF_INSN_CFCKUL; goto extract_sfmt_cfckne; + case 12 : itype = FRVBF_INSN_CCKN; goto extract_sfmt_cckeq; + case 13 : itype = FRVBF_INSN_CFCKLG; goto extract_sfmt_cfckne; + case 14 : itype = FRVBF_INSN_CCKLE; goto extract_sfmt_cckeq; + case 15 : itype = FRVBF_INSN_CFCKNE; goto extract_sfmt_cfckne; + case 16 : itype = FRVBF_INSN_CCKRA; goto extract_sfmt_cckra; + case 17 : itype = FRVBF_INSN_CFCKEQ; goto extract_sfmt_cfckne; + case 18 : itype = FRVBF_INSN_CCKNC; goto extract_sfmt_cckeq; + case 19 : itype = FRVBF_INSN_CFCKUE; goto extract_sfmt_cfckne; + case 20 : itype = FRVBF_INSN_CCKNV; goto extract_sfmt_cckeq; + case 21 : itype = FRVBF_INSN_CFCKGE; goto extract_sfmt_cfckne; + case 22 : itype = FRVBF_INSN_CCKGE; goto extract_sfmt_cckeq; + case 23 : itype = FRVBF_INSN_CFCKUGE; goto extract_sfmt_cfckne; + case 24 : itype = FRVBF_INSN_CCKNE; goto extract_sfmt_cckeq; + case 25 : itype = FRVBF_INSN_CFCKLE; goto extract_sfmt_cfckne; + case 26 : itype = FRVBF_INSN_CCKHI; goto extract_sfmt_cckeq; + case 27 : itype = FRVBF_INSN_CFCKULE; goto extract_sfmt_cfckne; + case 28 : itype = FRVBF_INSN_CCKP; goto extract_sfmt_cckeq; + case 29 : itype = FRVBF_INSN_CFCKO; goto extract_sfmt_cfckne; + case 30 : itype = FRVBF_INSN_CCKGT; goto extract_sfmt_cckeq; + case 31 : itype = FRVBF_INSN_CFCKRA; goto extract_sfmt_cfckra; + default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 107 : + { + unsigned int val = (((insn >> 6) & (1 << 0))); + switch (val) + { + case 0 : itype = FRVBF_INSN_CFITOS; goto extract_sfmt_cfitos; + case 1 : itype = FRVBF_INSN_CFSTOI; goto extract_sfmt_cfstoi; + default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 108 : + { + unsigned int val = (((insn >> 6) & (3 << 0))); + switch (val) + { + case 0 : itype = FRVBF_INSN_CFMOVS; goto extract_sfmt_cfmovs; + case 1 : itype = FRVBF_INSN_CFNEGS; goto extract_sfmt_cfmovs; + case 2 : itype = FRVBF_INSN_CFABSS; goto extract_sfmt_cfmovs; + default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 109 : + { + unsigned int val = (((insn >> 6) & (3 << 0))); + switch (val) + { + case 0 : itype = FRVBF_INSN_CFADDS; goto extract_sfmt_cfadds; + case 1 : itype = FRVBF_INSN_CFSUBS; goto extract_sfmt_cfadds; + case 2 : itype = FRVBF_INSN_CFCMPS; goto extract_sfmt_cfcmps; + default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 110 : + { + unsigned int val = (((insn >> 6) & (3 << 0))); + switch (val) + { + case 0 : itype = FRVBF_INSN_CFMULS; goto extract_sfmt_cfadds; + case 1 : itype = FRVBF_INSN_CFDIVS; goto extract_sfmt_cfadds; + case 2 : itype = FRVBF_INSN_CFSQRTS; goto extract_sfmt_cfmovs; + default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 111 : + { + unsigned int val = (((insn >> 6) & (3 << 0))); + switch (val) + { + case 0 : itype = FRVBF_INSN_CFMADDS; goto extract_sfmt_cfmadds; + case 1 : itype = FRVBF_INSN_CFMSUBS; goto extract_sfmt_cfmadds; + case 2 : itype = FRVBF_INSN_CFMAS; goto extract_sfmt_cfmas; + case 3 : itype = FRVBF_INSN_CFMSS; goto extract_sfmt_cfmas; + default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 112 : + { + unsigned int val = (((insn >> 6) & (3 << 0))); + switch (val) + { + case 0 : itype = FRVBF_INSN_CMAND; goto extract_sfmt_cmand; + case 1 : itype = FRVBF_INSN_CMOR; goto extract_sfmt_cmand; + case 2 : itype = FRVBF_INSN_CMXOR; goto extract_sfmt_cmand; + case 3 : itype = FRVBF_INSN_CMNOT; goto extract_sfmt_cmnot; + default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 113 : + { + unsigned int val = (((insn >> 6) & (3 << 0))); + switch (val) + { + case 0 : itype = FRVBF_INSN_CMADDHSS; goto extract_sfmt_cmaddhss; + case 1 : itype = FRVBF_INSN_CMADDHUS; goto extract_sfmt_cmaddhss; + case 2 : itype = FRVBF_INSN_CMSUBHSS; goto extract_sfmt_cmaddhss; + case 3 : itype = FRVBF_INSN_CMSUBHUS; goto extract_sfmt_cmaddhss; + default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 114 : + { + unsigned int val = (((insn >> 6) & (3 << 0))); + switch (val) + { + case 0 : itype = FRVBF_INSN_CMMULHS; goto extract_sfmt_cmmulhs; + case 1 : itype = FRVBF_INSN_CMMULHU; goto extract_sfmt_cmmulhs; + case 2 : itype = FRVBF_INSN_CMMACHS; goto extract_sfmt_cmmachs; + case 3 : itype = FRVBF_INSN_CMMACHU; goto extract_sfmt_cmmachu; + default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 115 : + { + unsigned int val = (((insn >> 6) & (3 << 0))); + switch (val) + { + case 0 : itype = FRVBF_INSN_CMQADDHSS; goto extract_sfmt_cmqaddhss; + case 1 : itype = FRVBF_INSN_CMQADDHUS; goto extract_sfmt_cmqaddhss; + case 2 : itype = FRVBF_INSN_CMQSUBHSS; goto extract_sfmt_cmqaddhss; + case 3 : itype = FRVBF_INSN_CMQSUBHUS; goto extract_sfmt_cmqaddhss; + default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 116 : + { + unsigned int val = (((insn >> 6) & (3 << 0))); + switch (val) + { + case 0 : itype = FRVBF_INSN_CMQMULHS; goto extract_sfmt_cmqmulhs; + case 1 : itype = FRVBF_INSN_CMQMULHU; goto extract_sfmt_cmqmulhs; + case 2 : itype = FRVBF_INSN_CMQMACHS; goto extract_sfmt_cmqmachs; + case 3 : itype = FRVBF_INSN_CMQMACHU; goto extract_sfmt_cmqmachu; + default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 117 : + { + unsigned int val = (((insn >> 6) & (3 << 0))); + switch (val) + { + case 0 : itype = FRVBF_INSN_CMCPXRS; goto extract_sfmt_cmcpxrs; + case 1 : itype = FRVBF_INSN_CMCPXRU; goto extract_sfmt_cmcpxrs; + case 2 : itype = FRVBF_INSN_CMCPXIS; goto extract_sfmt_cmcpxrs; + case 3 : itype = FRVBF_INSN_CMCPXIU; goto extract_sfmt_cmcpxrs; + default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 118 : + { + unsigned int val = (((insn >> 6) & (1 << 0))); + switch (val) + { + case 0 : itype = FRVBF_INSN_CMEXPDHW; goto extract_sfmt_cmexpdhw; + case 1 : itype = FRVBF_INSN_CMEXPDHD; goto extract_sfmt_cmexpdhd; + default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 119 : + { + unsigned int val = (((insn >> 6) & (3 << 0))); + switch (val) + { + case 0 : itype = FRVBF_INSN_CMBTOH; goto extract_sfmt_cmbtoh; + case 1 : itype = FRVBF_INSN_CMHTOB; goto extract_sfmt_cmhtob; + case 2 : itype = FRVBF_INSN_CMBTOHE; goto extract_sfmt_cmbtohe; + default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 120 : + { + unsigned int val = (((insn >> 7) & (1 << 4)) | ((insn >> 6) & (15 << 0))); + switch (val) + { + case 0 : itype = FRVBF_INSN_MQXMACHS; goto extract_sfmt_mqmachs; + case 1 : itype = FRVBF_INSN_MQXMACXHS; goto extract_sfmt_mqmachs; + case 2 : itype = FRVBF_INSN_MQMACXHS; goto extract_sfmt_mqmachs; + case 4 : itype = FRVBF_INSN_MADDACCS; goto extract_sfmt_maddaccs; + case 5 : itype = FRVBF_INSN_MSUBACCS; goto extract_sfmt_maddaccs; + case 6 : itype = FRVBF_INSN_MDADDACCS; goto extract_sfmt_mdaddaccs; + case 7 : itype = FRVBF_INSN_MDSUBACCS; goto extract_sfmt_mdaddaccs; + case 8 : itype = FRVBF_INSN_MASACCS; goto extract_sfmt_masaccs; + case 9 : itype = FRVBF_INSN_MDASACCS; goto extract_sfmt_mdasaccs; + case 10 : itype = FRVBF_INSN_MABSHS; goto extract_sfmt_mabshs; + case 11 : itype = FRVBF_INSN_MDROTLI; goto extract_sfmt_mdrotli; + case 12 : itype = FRVBF_INSN_MCPLHI; goto extract_sfmt_mcplhi; + case 13 : itype = FRVBF_INSN_MCPLI; goto extract_sfmt_mcpli; + case 14 : itype = FRVBF_INSN_MDCUTSSI; goto extract_sfmt_mdcutssi; + case 15 : itype = FRVBF_INSN_MQSATHS; goto extract_sfmt_mqsaths; + case 16 : itype = FRVBF_INSN_MHSETLOS; goto extract_sfmt_mhsetlos; + case 17 : itype = FRVBF_INSN_MHSETLOH; goto extract_sfmt_mhsetloh; + case 18 : itype = FRVBF_INSN_MHSETHIS; goto extract_sfmt_mhsethis; + case 19 : itype = FRVBF_INSN_MHSETHIH; goto extract_sfmt_mhsethih; + case 20 : itype = FRVBF_INSN_MHDSETS; goto extract_sfmt_mhdsets; + case 21 : itype = FRVBF_INSN_MHDSETH; goto extract_sfmt_mhdseth; + default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 121 : + { + unsigned int val = (((insn >> 7) & (1 << 3)) | ((insn >> 6) & (7 << 0))); + switch (val) + { + case 0 : + { + unsigned int val = (((insn >> 10) & (1 << 1)) | ((insn >> 9) & (1 << 0))); + switch (val) + { + case 0 : itype = FRVBF_INSN_FITOS; goto extract_sfmt_fitos; + case 1 : itype = FRVBF_INSN_FMULS; goto extract_sfmt_fadds; + case 2 : itype = FRVBF_INSN_NFITOS; goto extract_sfmt_nfitos; + case 3 : itype = FRVBF_INSN_NFMULS; goto extract_sfmt_nfadds; + default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 1 : + { + unsigned int val = (((insn >> 10) & (1 << 1)) | ((insn >> 9) & (1 << 0))); + switch (val) + { + case 0 : itype = FRVBF_INSN_FSTOI; goto extract_sfmt_fstoi; + case 1 : itype = FRVBF_INSN_FDIVS; goto extract_sfmt_fadds; + case 2 : itype = FRVBF_INSN_NFSTOI; goto extract_sfmt_nfstoi; + case 3 : itype = FRVBF_INSN_NFDIVS; goto extract_sfmt_nfadds; + default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 2 : + { + unsigned int val = (((insn >> 9) & (1 << 0))); + switch (val) + { + case 0 : itype = FRVBF_INSN_FMOVS; goto extract_sfmt_fmovs; + case 1 : itype = FRVBF_INSN_FCMPS; goto extract_sfmt_fcmps; + default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 3 : + { + unsigned int val = (((insn >> 10) & (1 << 1)) | ((insn >> 9) & (1 << 0))); + switch (val) + { + case 0 : itype = FRVBF_INSN_FNEGS; goto extract_sfmt_fmovs; + case 1 : itype = FRVBF_INSN_FMADDS; goto extract_sfmt_fmadds; + case 3 : itype = FRVBF_INSN_NFMADDS; goto extract_sfmt_nfmadds; + default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 4 : + { + unsigned int val = (((insn >> 10) & (1 << 1)) | ((insn >> 9) & (1 << 0))); + switch (val) + { + case 0 : itype = FRVBF_INSN_FABSS; goto extract_sfmt_fmovs; + case 1 : itype = FRVBF_INSN_FMSUBS; goto extract_sfmt_fmadds; + case 3 : itype = FRVBF_INSN_NFMSUBS; goto extract_sfmt_nfmadds; + default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 5 : + { + unsigned int val = (((insn >> 10) & (1 << 1)) | ((insn >> 9) & (1 << 0))); + switch (val) + { + case 0 : itype = FRVBF_INSN_FSQRTS; goto extract_sfmt_fmovs; + case 1 : itype = FRVBF_INSN_FNOP; goto extract_sfmt_rei; + case 2 : itype = FRVBF_INSN_NFSQRTS; goto extract_sfmt_nfsqrts; + default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 6 : + { + unsigned int val = (((insn >> 10) & (1 << 1)) | ((insn >> 9) & (1 << 0))); + switch (val) + { + case 0 : itype = FRVBF_INSN_FADDS; goto extract_sfmt_fadds; + case 1 : itype = FRVBF_INSN_FMAS; goto extract_sfmt_fmas; + case 2 : itype = FRVBF_INSN_NFADDS; goto extract_sfmt_nfadds; + case 3 : itype = FRVBF_INSN_NFMAS; goto extract_sfmt_fmas; + default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 7 : + { + unsigned int val = (((insn >> 10) & (1 << 1)) | ((insn >> 9) & (1 << 0))); + switch (val) + { + case 0 : itype = FRVBF_INSN_FSUBS; goto extract_sfmt_fadds; + case 1 : itype = FRVBF_INSN_FMSS; goto extract_sfmt_fmas; + case 2 : itype = FRVBF_INSN_NFSUBS; goto extract_sfmt_nfadds; + case 3 : itype = FRVBF_INSN_NFMSS; goto extract_sfmt_fmas; + default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 8 : + { + unsigned int val = (((insn >> 10) & (1 << 1)) | ((insn >> 9) & (1 << 0))); + switch (val) + { + case 0 : itype = FRVBF_INSN_FDITOS; goto extract_sfmt_fditos; + case 1 : itype = FRVBF_INSN_FDMULS; goto extract_sfmt_fmas; + case 2 : itype = FRVBF_INSN_NFDITOS; goto extract_sfmt_fditos; + case 3 : itype = FRVBF_INSN_NFDMULS; goto extract_sfmt_fmas; + default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 9 : + { + unsigned int val = (((insn >> 10) & (1 << 1)) | ((insn >> 9) & (1 << 0))); + switch (val) + { + case 0 : itype = FRVBF_INSN_FDSTOI; goto extract_sfmt_fdstoi; + case 1 : itype = FRVBF_INSN_FDDIVS; goto extract_sfmt_fmas; + case 2 : itype = FRVBF_INSN_NFDSTOI; goto extract_sfmt_fdstoi; + case 3 : itype = FRVBF_INSN_NFDDIVS; goto extract_sfmt_fmas; + default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 10 : + { + unsigned int val = (((insn >> 10) & (1 << 1)) | ((insn >> 9) & (1 << 0))); + switch (val) + { + case 0 : itype = FRVBF_INSN_FDMOVS; goto extract_sfmt_fdmovs; + case 1 : itype = FRVBF_INSN_FDCMPS; goto extract_sfmt_fdcmps; + case 3 : itype = FRVBF_INSN_NFDCMPS; goto extract_sfmt_nfdcmps; + default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 11 : + { + unsigned int val = (((insn >> 10) & (1 << 1)) | ((insn >> 9) & (1 << 0))); + switch (val) + { + case 0 : itype = FRVBF_INSN_FDNEGS; goto extract_sfmt_fdmovs; + case 1 : itype = FRVBF_INSN_FDMADDS; goto extract_sfmt_fdmadds; + case 3 : itype = FRVBF_INSN_NFDMADDS; goto extract_sfmt_fdmadds; + default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 12 : + { + unsigned int val = (((insn >> 10) & (1 << 1)) | ((insn >> 9) & (1 << 0))); + switch (val) + { + case 0 : itype = FRVBF_INSN_FDABSS; goto extract_sfmt_fdmovs; + case 1 : itype = FRVBF_INSN_FDMAS; goto extract_sfmt_fdmas; + case 3 : itype = FRVBF_INSN_NFDMAS; goto extract_sfmt_fdmas; + default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 13 : + { + unsigned int val = (((insn >> 10) & (1 << 1)) | ((insn >> 9) & (1 << 0))); + switch (val) + { + case 0 : itype = FRVBF_INSN_FDSQRTS; goto extract_sfmt_fdmovs; + case 1 : itype = FRVBF_INSN_FDMSS; goto extract_sfmt_fdmas; + case 2 : itype = FRVBF_INSN_NFDSQRTS; goto extract_sfmt_fdmovs; + case 3 : itype = FRVBF_INSN_NFDMSS; goto extract_sfmt_fdmas; + default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 14 : + { + unsigned int val = (((insn >> 10) & (1 << 1)) | ((insn >> 9) & (1 << 0))); + switch (val) + { + case 0 : itype = FRVBF_INSN_FDADDS; goto extract_sfmt_fmas; + case 1 : itype = FRVBF_INSN_FDSADS; goto extract_sfmt_fmas; + case 2 : itype = FRVBF_INSN_NFDADDS; goto extract_sfmt_fmas; + case 3 : itype = FRVBF_INSN_NFDSADS; goto extract_sfmt_fmas; + default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 15 : + { + unsigned int val = (((insn >> 10) & (1 << 1)) | ((insn >> 9) & (1 << 0))); + switch (val) + { + case 0 : itype = FRVBF_INSN_FDSUBS; goto extract_sfmt_fmas; + case 1 : itype = FRVBF_INSN_FDMULCS; goto extract_sfmt_fmas; + case 2 : itype = FRVBF_INSN_NFDSUBS; goto extract_sfmt_fmas; + case 3 : itype = FRVBF_INSN_NFDMULCS; goto extract_sfmt_fmas; + default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 122 : + { + unsigned int val = (((insn >> 6) & (15 << 0))); + switch (val) + { + case 0 : itype = FRVBF_INSN_FITOD; goto extract_sfmt_fitod; + case 1 : itype = FRVBF_INSN_FDTOI; goto extract_sfmt_fdtoi; + case 2 : itype = FRVBF_INSN_FMOVD; goto extract_sfmt_fmovd; + case 3 : itype = FRVBF_INSN_FNEGD; goto extract_sfmt_fmovd; + case 4 : itype = FRVBF_INSN_FABSD; goto extract_sfmt_fmovd; + case 5 : itype = FRVBF_INSN_FSQRTD; goto extract_sfmt_fmovd; + case 6 : itype = FRVBF_INSN_FADDD; goto extract_sfmt_faddd; + case 7 : itype = FRVBF_INSN_FSUBD; goto extract_sfmt_faddd; + case 8 : itype = FRVBF_INSN_FMULD; goto extract_sfmt_faddd; + case 9 : itype = FRVBF_INSN_FDIVD; goto extract_sfmt_faddd; + case 10 : itype = FRVBF_INSN_FCMPD; goto extract_sfmt_fcmpd; + case 11 : itype = FRVBF_INSN_FMADDD; goto extract_sfmt_fmaddd; + case 12 : itype = FRVBF_INSN_FMSUBD; goto extract_sfmt_fmaddd; + case 14 : itype = FRVBF_INSN_FMAD; goto extract_sfmt_fmas; + case 15 : itype = FRVBF_INSN_FMSD; goto extract_sfmt_fmas; + default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 123 : + { + unsigned int val = (((insn >> 6) & (63 << 0))); + switch (val) + { + case 0 : itype = FRVBF_INSN_MAND; goto extract_sfmt_mand; + case 1 : itype = FRVBF_INSN_MOR; goto extract_sfmt_mand; + case 2 : itype = FRVBF_INSN_MXOR; goto extract_sfmt_mand; + case 3 : itype = FRVBF_INSN_MNOT; goto extract_sfmt_mnot; + case 4 : itype = FRVBF_INSN_MROTLI; goto extract_sfmt_mrotli; + case 5 : itype = FRVBF_INSN_MROTRI; goto extract_sfmt_mrotli; + case 6 : itype = FRVBF_INSN_MWCUT; goto extract_sfmt_mwcut; + case 7 : itype = FRVBF_INSN_MWCUTI; goto extract_sfmt_mwcuti; + case 8 : itype = FRVBF_INSN_MAVEH; goto extract_sfmt_mand; + case 9 : itype = FRVBF_INSN_MSLLHI; goto extract_sfmt_msllhi; + case 10 : itype = FRVBF_INSN_MSRLHI; goto extract_sfmt_msllhi; + case 11 : itype = FRVBF_INSN_MSRAHI; goto extract_sfmt_msllhi; + case 12 : itype = FRVBF_INSN_MSATHS; goto extract_sfmt_msaths; + case 13 : itype = FRVBF_INSN_MSATHU; goto extract_sfmt_msaths; + case 14 : itype = FRVBF_INSN_MCMPSH; goto extract_sfmt_mcmpsh; + case 15 : itype = FRVBF_INSN_MCMPUH; goto extract_sfmt_mcmpsh; + case 16 : itype = FRVBF_INSN_MADDHSS; goto extract_sfmt_msaths; + case 17 : itype = FRVBF_INSN_MADDHUS; goto extract_sfmt_msaths; + case 18 : itype = FRVBF_INSN_MSUBHSS; goto extract_sfmt_msaths; + case 19 : itype = FRVBF_INSN_MSUBHUS; goto extract_sfmt_msaths; + case 20 : itype = FRVBF_INSN_MMULHS; goto extract_sfmt_mmulhs; + case 21 : itype = FRVBF_INSN_MMULHU; goto extract_sfmt_mmulhs; + case 22 : itype = FRVBF_INSN_MMACHS; goto extract_sfmt_mmachs; + case 23 : itype = FRVBF_INSN_MMACHU; goto extract_sfmt_mmachu; + case 24 : itype = FRVBF_INSN_MQADDHSS; goto extract_sfmt_mqsaths; + case 25 : itype = FRVBF_INSN_MQADDHUS; goto extract_sfmt_mqsaths; + case 26 : itype = FRVBF_INSN_MQSUBHSS; goto extract_sfmt_mqsaths; + case 27 : itype = FRVBF_INSN_MQSUBHUS; goto extract_sfmt_mqsaths; + case 28 : itype = FRVBF_INSN_MQMULHS; goto extract_sfmt_mqmulhs; + case 29 : itype = FRVBF_INSN_MQMULHU; goto extract_sfmt_mqmulhs; + case 30 : itype = FRVBF_INSN_MQMACHS; goto extract_sfmt_mqmachs; + case 31 : itype = FRVBF_INSN_MQMACHU; goto extract_sfmt_mqmachu; + case 32 : itype = FRVBF_INSN_MCPXRS; goto extract_sfmt_mcpxrs; + case 33 : itype = FRVBF_INSN_MCPXRU; goto extract_sfmt_mcpxrs; + case 34 : itype = FRVBF_INSN_MCPXIS; goto extract_sfmt_mcpxrs; + case 35 : itype = FRVBF_INSN_MCPXIU; goto extract_sfmt_mcpxrs; + case 36 : itype = FRVBF_INSN_MQCPXRS; goto extract_sfmt_mqcpxrs; + case 37 : itype = FRVBF_INSN_MQCPXRU; goto extract_sfmt_mqcpxrs; + case 38 : itype = FRVBF_INSN_MQCPXIS; goto extract_sfmt_mqcpxrs; + case 39 : itype = FRVBF_INSN_MQCPXIU; goto extract_sfmt_mqcpxrs; + case 40 : itype = FRVBF_INSN_MMULXHS; goto extract_sfmt_mmulhs; + case 41 : itype = FRVBF_INSN_MMULXHU; goto extract_sfmt_mmulhs; + case 42 : itype = FRVBF_INSN_MQMULXHS; goto extract_sfmt_mqmulhs; + case 43 : itype = FRVBF_INSN_MQMULXHU; goto extract_sfmt_mqmulhs; + case 44 : itype = FRVBF_INSN_MCUT; goto extract_sfmt_mcut; + case 45 : itype = FRVBF_INSN_MCUTSS; goto extract_sfmt_mcut; + case 46 : itype = FRVBF_INSN_MCUTI; goto extract_sfmt_mcuti; + case 47 : itype = FRVBF_INSN_MCUTSSI; goto extract_sfmt_mcuti; + case 48 : itype = FRVBF_INSN_MMRDHS; goto extract_sfmt_mmachs; + case 49 : itype = FRVBF_INSN_MMRDHU; goto extract_sfmt_mmachu; + case 50 : itype = FRVBF_INSN_MEXPDHW; goto extract_sfmt_mexpdhw; + case 51 : itype = FRVBF_INSN_MEXPDHD; goto extract_sfmt_mexpdhd; + case 52 : itype = FRVBF_INSN_MPACKH; goto extract_sfmt_mpackh; + case 53 : itype = FRVBF_INSN_MUNPACKH; goto extract_sfmt_munpackh; + case 54 : itype = FRVBF_INSN_MDPACKH; goto extract_sfmt_mdpackh; + case 55 : itype = FRVBF_INSN_MDUNPACKH; goto extract_sfmt_mdunpackh; + case 56 : itype = FRVBF_INSN_MBTOH; goto extract_sfmt_mbtoh; + case 57 : itype = FRVBF_INSN_MHTOB; goto extract_sfmt_mhtob; + case 58 : itype = FRVBF_INSN_MBTOHE; goto extract_sfmt_mbtohe; + case 59 : + { + unsigned int val = (((insn >> 17) & (1 << 0))); + switch (val) + { + case 0 : itype = FRVBF_INSN_MCLRACC_0; goto extract_sfmt_mclracc_0; + case 1 : + { + unsigned int val = (((insn >> 25) & (63 << 0))); + switch (val) + { + case 0 : /* fall through */ + case 1 : /* fall through */ + case 2 : /* fall through */ + case 3 : /* fall through */ + case 4 : /* fall through */ + case 5 : /* fall through */ + case 6 : /* fall through */ + case 7 : /* fall through */ + case 8 : /* fall through */ + case 9 : /* fall through */ + case 10 : /* fall through */ + case 11 : /* fall through */ + case 12 : /* fall through */ + case 13 : /* fall through */ + case 14 : /* fall through */ + case 15 : /* fall through */ + case 16 : /* fall through */ + case 17 : /* fall through */ + case 18 : /* fall through */ + case 19 : /* fall through */ + case 20 : /* fall through */ + case 21 : /* fall through */ + case 22 : /* fall through */ + case 23 : /* fall through */ + case 24 : /* fall through */ + case 25 : /* fall through */ + case 26 : /* fall through */ + case 27 : /* fall through */ + case 28 : /* fall through */ + case 29 : /* fall through */ + case 30 : /* fall through */ + case 31 : /* fall through */ + case 32 : /* fall through */ + case 33 : /* fall through */ + case 34 : /* fall through */ + case 35 : /* fall through */ + case 36 : /* fall through */ + case 37 : /* fall through */ + case 38 : /* fall through */ + case 39 : /* fall through */ + case 40 : /* fall through */ + case 41 : /* fall through */ + case 42 : /* fall through */ + case 43 : /* fall through */ + case 44 : /* fall through */ + case 45 : /* fall through */ + case 46 : /* fall through */ + case 47 : /* fall through */ + case 48 : /* fall through */ + case 49 : /* fall through */ + case 50 : /* fall through */ + case 51 : /* fall through */ + case 52 : /* fall through */ + case 53 : /* fall through */ + case 54 : /* fall through */ + case 55 : /* fall through */ + case 56 : /* fall through */ + case 57 : /* fall through */ + case 58 : /* fall through */ + case 59 : /* fall through */ + case 60 : /* fall through */ + case 61 : /* fall through */ + case 62 : itype = FRVBF_INSN_MCLRACC_1; goto extract_sfmt_mclracc_0; + case 63 : itype = FRVBF_INSN_MNOP; goto extract_sfmt_rei; + default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 60 : itype = FRVBF_INSN_MRDACC; goto extract_sfmt_mrdacc; + case 61 : itype = FRVBF_INSN_MWTACC; goto extract_sfmt_mwtacc; + case 62 : itype = FRVBF_INSN_MRDACCG; goto extract_sfmt_mrdaccg; + case 63 : itype = FRVBF_INSN_MWTACCG; goto extract_sfmt_mwtaccg; + default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 124 : itype = FRVBF_INSN_MCOP1; goto extract_sfmt_rei; + case 125 : itype = FRVBF_INSN_MCOP2; goto extract_sfmt_rei; + case 126 : itype = FRVBF_INSN_COP1; goto extract_sfmt_rei; + case 127 : itype = FRVBF_INSN_COP2; goto extract_sfmt_rei; + default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + } + + /* The instruction has been decoded, now extract the fields. */ + + extract_sfmt_empty: + { + const IDESC *idesc = &frvbf_insn_data[itype]; +#define FLD(f) abuf->fields.fmt_empty.f + + + /* Record the fields for the semantic handler. */ + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_empty", (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_add: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_addcc.f + UINT f_GRk; + UINT f_GRi; + UINT f_GRj; + + f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_GRi) = f_GRi; + FLD (f_GRj) = f_GRj; + FLD (f_GRk) = f_GRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_GRk 0x%x", 'x', f_GRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_GRi) = f_GRi; + FLD (in_GRj) = f_GRj; + FLD (out_GRk) = f_GRk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_not: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_scutss.f + UINT f_GRk; + UINT f_GRj; + + f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_GRj) = f_GRj; + FLD (f_GRk) = f_GRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_not", "f_GRj 0x%x", 'x', f_GRj, "f_GRk 0x%x", 'x', f_GRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_GRj) = f_GRj; + FLD (out_GRk) = f_GRk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_sdiv: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_addcc.f + UINT f_GRk; + UINT f_GRi; + UINT f_GRj; + + f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_GRi) = f_GRi; + FLD (f_GRj) = f_GRj; + FLD (f_GRk) = f_GRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sdiv", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_GRk 0x%x", 'x', f_GRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_GRi) = f_GRi; + FLD (in_GRj) = f_GRj; + FLD (out_GRk) = f_GRk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_smul: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_smulcc.f + UINT f_GRk; + UINT f_GRi; + UINT f_GRj; + + f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_GRi) = f_GRi; + FLD (f_GRj) = f_GRj; + FLD (f_GRk) = f_GRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_smul", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_GRk 0x%x", 'x', f_GRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_GRi) = f_GRi; + FLD (in_GRj) = f_GRj; + FLD (out_GRdoublek) = f_GRk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_smu: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_smass.f + UINT f_GRi; + UINT f_GRj; + + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_GRi) = f_GRi; + FLD (f_GRj) = f_GRj; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_smu", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_GRi) = f_GRi; + FLD (in_GRj) = f_GRj; + FLD (out_h_iacc0_DI_0) = 0; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_smass: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_smass.f + UINT f_GRi; + UINT f_GRj; + + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_GRi) = f_GRi; + FLD (f_GRj) = f_GRj; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_smass", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_GRi) = f_GRi; + FLD (in_GRj) = f_GRj; + FLD (in_h_iacc0_DI_0) = 0; + FLD (out_h_iacc0_DI_0) = 0; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_scutss: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_scutss.f + UINT f_GRk; + UINT f_GRj; + + f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_GRj) = f_GRj; + FLD (f_GRk) = f_GRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_scutss", "f_GRj 0x%x", 'x', f_GRj, "f_GRk 0x%x", 'x', f_GRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_GRj) = f_GRj; + FLD (in_h_iacc0_DI_0) = 0; + FLD (out_GRk) = f_GRk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_cadd: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cswap.f + UINT f_GRk; + UINT f_GRi; + UINT f_CCi; + UINT f_cond; + UINT f_GRj; + + f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); + f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_CCi) = f_CCi; + FLD (f_GRi) = f_GRi; + FLD (f_GRj) = f_GRj; + FLD (f_cond) = f_cond; + FLD (f_GRk) = f_GRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cadd", "f_CCi 0x%x", 'x', f_CCi, "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_cond 0x%x", 'x', f_cond, "f_GRk 0x%x", 'x', f_GRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_CCi) = f_CCi; + FLD (in_GRi) = f_GRi; + FLD (in_GRj) = f_GRj; + FLD (out_GRk) = f_GRk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_cnot: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cswap.f + UINT f_GRk; + UINT f_CCi; + UINT f_cond; + UINT f_GRj; + + f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); + f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_CCi) = f_CCi; + FLD (f_GRj) = f_GRj; + FLD (f_cond) = f_cond; + FLD (f_GRk) = f_GRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cnot", "f_CCi 0x%x", 'x', f_CCi, "f_GRj 0x%x", 'x', f_GRj, "f_cond 0x%x", 'x', f_cond, "f_GRk 0x%x", 'x', f_GRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_CCi) = f_CCi; + FLD (in_GRj) = f_GRj; + FLD (out_GRk) = f_GRk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_csmul: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_clddu.f + UINT f_GRk; + UINT f_GRi; + UINT f_CCi; + UINT f_cond; + UINT f_GRj; + + f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); + f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_CCi) = f_CCi; + FLD (f_GRi) = f_GRi; + FLD (f_GRj) = f_GRj; + FLD (f_cond) = f_cond; + FLD (f_GRk) = f_GRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_csmul", "f_CCi 0x%x", 'x', f_CCi, "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_cond 0x%x", 'x', f_cond, "f_GRk 0x%x", 'x', f_GRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_CCi) = f_CCi; + FLD (in_GRi) = f_GRi; + FLD (in_GRj) = f_GRj; + FLD (out_GRdoublek) = f_GRk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_csdiv: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cswap.f + UINT f_GRk; + UINT f_GRi; + UINT f_CCi; + UINT f_cond; + UINT f_GRj; + + f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); + f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_CCi) = f_CCi; + FLD (f_GRi) = f_GRi; + FLD (f_GRj) = f_GRj; + FLD (f_cond) = f_cond; + FLD (f_GRk) = f_GRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_csdiv", "f_CCi 0x%x", 'x', f_CCi, "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_cond 0x%x", 'x', f_cond, "f_GRk 0x%x", 'x', f_GRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_CCi) = f_CCi; + FLD (in_GRi) = f_GRi; + FLD (in_GRj) = f_GRj; + FLD (out_GRk) = f_GRk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_addcc: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_addcc.f + UINT f_GRk; + UINT f_GRi; + UINT f_ICCi_1; + UINT f_GRj; + + f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_ICCi_1 = EXTRACT_LSB0_UINT (insn, 32, 11, 2); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_GRi) = f_GRi; + FLD (f_GRj) = f_GRj; + FLD (f_ICCi_1) = f_ICCi_1; + FLD (f_GRk) = f_GRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addcc", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_ICCi_1 0x%x", 'x', f_ICCi_1, "f_GRk 0x%x", 'x', f_GRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_GRi) = f_GRi; + FLD (in_GRj) = f_GRj; + FLD (in_ICCi_1) = f_ICCi_1; + FLD (out_GRk) = f_GRk; + FLD (out_ICCi_1) = f_ICCi_1; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_andcc: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_addcc.f + UINT f_GRk; + UINT f_GRi; + UINT f_ICCi_1; + UINT f_GRj; + + f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_ICCi_1 = EXTRACT_LSB0_UINT (insn, 32, 11, 2); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_GRi) = f_GRi; + FLD (f_GRj) = f_GRj; + FLD (f_ICCi_1) = f_ICCi_1; + FLD (f_GRk) = f_GRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_andcc", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_ICCi_1 0x%x", 'x', f_ICCi_1, "f_GRk 0x%x", 'x', f_GRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_GRi) = f_GRi; + FLD (in_GRj) = f_GRj; + FLD (in_ICCi_1) = f_ICCi_1; + FLD (out_GRk) = f_GRk; + FLD (out_ICCi_1) = f_ICCi_1; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_smulcc: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_smulcc.f + UINT f_GRk; + UINT f_GRi; + UINT f_ICCi_1; + UINT f_GRj; + + f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_ICCi_1 = EXTRACT_LSB0_UINT (insn, 32, 11, 2); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_GRi) = f_GRi; + FLD (f_GRj) = f_GRj; + FLD (f_ICCi_1) = f_ICCi_1; + FLD (f_GRk) = f_GRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_smulcc", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_ICCi_1 0x%x", 'x', f_ICCi_1, "f_GRk 0x%x", 'x', f_GRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_GRi) = f_GRi; + FLD (in_GRj) = f_GRj; + FLD (in_ICCi_1) = f_ICCi_1; + FLD (out_GRdoublek) = f_GRk; + FLD (out_ICCi_1) = f_ICCi_1; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_caddcc: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_caddcc.f + UINT f_GRk; + UINT f_GRi; + UINT f_CCi; + UINT f_cond; + UINT f_GRj; + + f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); + f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_CCi) = f_CCi; + FLD (f_GRi) = f_GRi; + FLD (f_GRj) = f_GRj; + FLD (f_cond) = f_cond; + FLD (f_GRk) = f_GRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_caddcc", "f_CCi 0x%x", 'x', f_CCi, "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_cond 0x%x", 'x', f_cond, "f_GRk 0x%x", 'x', f_GRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_CCi) = f_CCi; + FLD (in_GRi) = f_GRi; + FLD (in_GRj) = f_GRj; + FLD (in_h_iccr_UQI_and__DFLT_index_of__DFLT_CCi_3) = ((FLD (f_CCi)) & (3)); + FLD (out_GRk) = f_GRk; + FLD (out_h_iccr_UQI_and__DFLT_index_of__DFLT_CCi_3) = ((FLD (f_CCi)) & (3)); + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_csmulcc: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_csmulcc.f + UINT f_GRk; + UINT f_GRi; + UINT f_CCi; + UINT f_cond; + UINT f_GRj; + + f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); + f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_CCi) = f_CCi; + FLD (f_GRi) = f_GRi; + FLD (f_GRj) = f_GRj; + FLD (f_cond) = f_cond; + FLD (f_GRk) = f_GRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_csmulcc", "f_CCi 0x%x", 'x', f_CCi, "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_cond 0x%x", 'x', f_cond, "f_GRk 0x%x", 'x', f_GRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_CCi) = f_CCi; + FLD (in_GRi) = f_GRi; + FLD (in_GRj) = f_GRj; + FLD (in_h_iccr_UQI_and__DFLT_index_of__DFLT_CCi_3) = ((FLD (f_CCi)) & (3)); + FLD (out_GRdoublek) = f_GRk; + FLD (out_h_iccr_UQI_and__DFLT_index_of__DFLT_CCi_3) = ((FLD (f_CCi)) & (3)); + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_addx: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_addcc.f + UINT f_GRk; + UINT f_GRi; + UINT f_ICCi_1; + UINT f_GRj; + + f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_ICCi_1 = EXTRACT_LSB0_UINT (insn, 32, 11, 2); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_GRi) = f_GRi; + FLD (f_GRj) = f_GRj; + FLD (f_ICCi_1) = f_ICCi_1; + FLD (f_GRk) = f_GRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addx", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_ICCi_1 0x%x", 'x', f_ICCi_1, "f_GRk 0x%x", 'x', f_GRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_GRi) = f_GRi; + FLD (in_GRj) = f_GRj; + FLD (in_ICCi_1) = f_ICCi_1; + FLD (out_GRk) = f_GRk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_addi: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_swapi.f + UINT f_GRk; + UINT f_GRi; + INT f_d12; + + f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_d12 = EXTRACT_LSB0_INT (insn, 32, 11, 12); + + /* Record the fields for the semantic handler. */ + FLD (f_GRi) = f_GRi; + FLD (f_d12) = f_d12; + FLD (f_GRk) = f_GRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addi", "f_GRi 0x%x", 'x', f_GRi, "f_d12 0x%x", 'x', f_d12, "f_GRk 0x%x", 'x', f_GRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_GRi) = f_GRi; + FLD (out_GRk) = f_GRk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_sdivi: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_swapi.f + UINT f_GRk; + UINT f_GRi; + INT f_d12; + + f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_d12 = EXTRACT_LSB0_INT (insn, 32, 11, 12); + + /* Record the fields for the semantic handler. */ + FLD (f_GRi) = f_GRi; + FLD (f_GRk) = f_GRk; + FLD (f_d12) = f_d12; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sdivi", "f_GRi 0x%x", 'x', f_GRi, "f_GRk 0x%x", 'x', f_GRk, "f_d12 0x%x", 'x', f_d12, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_GRi) = f_GRi; + FLD (out_GRk) = f_GRk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_smuli: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_smuli.f + UINT f_GRk; + UINT f_GRi; + INT f_d12; + + f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_d12 = EXTRACT_LSB0_INT (insn, 32, 11, 12); + + /* Record the fields for the semantic handler. */ + FLD (f_GRi) = f_GRi; + FLD (f_d12) = f_d12; + FLD (f_GRk) = f_GRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_smuli", "f_GRi 0x%x", 'x', f_GRi, "f_d12 0x%x", 'x', f_d12, "f_GRk 0x%x", 'x', f_GRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_GRi) = f_GRi; + FLD (out_GRdoublek) = f_GRk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_addicc: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_addicc.f + UINT f_GRk; + UINT f_GRi; + UINT f_ICCi_1; + INT f_s10; + + f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_ICCi_1 = EXTRACT_LSB0_UINT (insn, 32, 11, 2); + f_s10 = EXTRACT_LSB0_INT (insn, 32, 9, 10); + + /* Record the fields for the semantic handler. */ + FLD (f_GRi) = f_GRi; + FLD (f_ICCi_1) = f_ICCi_1; + FLD (f_s10) = f_s10; + FLD (f_GRk) = f_GRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addicc", "f_GRi 0x%x", 'x', f_GRi, "f_ICCi_1 0x%x", 'x', f_ICCi_1, "f_s10 0x%x", 'x', f_s10, "f_GRk 0x%x", 'x', f_GRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_GRi) = f_GRi; + FLD (in_ICCi_1) = f_ICCi_1; + FLD (out_GRk) = f_GRk; + FLD (out_ICCi_1) = f_ICCi_1; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_andicc: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_addicc.f + UINT f_GRk; + UINT f_GRi; + UINT f_ICCi_1; + INT f_s10; + + f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_ICCi_1 = EXTRACT_LSB0_UINT (insn, 32, 11, 2); + f_s10 = EXTRACT_LSB0_INT (insn, 32, 9, 10); + + /* Record the fields for the semantic handler. */ + FLD (f_GRi) = f_GRi; + FLD (f_ICCi_1) = f_ICCi_1; + FLD (f_s10) = f_s10; + FLD (f_GRk) = f_GRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_andicc", "f_GRi 0x%x", 'x', f_GRi, "f_ICCi_1 0x%x", 'x', f_ICCi_1, "f_s10 0x%x", 'x', f_s10, "f_GRk 0x%x", 'x', f_GRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_GRi) = f_GRi; + FLD (in_ICCi_1) = f_ICCi_1; + FLD (out_GRk) = f_GRk; + FLD (out_ICCi_1) = f_ICCi_1; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_smulicc: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_smulicc.f + UINT f_GRk; + UINT f_GRi; + UINT f_ICCi_1; + INT f_s10; + + f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_ICCi_1 = EXTRACT_LSB0_UINT (insn, 32, 11, 2); + f_s10 = EXTRACT_LSB0_INT (insn, 32, 9, 10); + + /* Record the fields for the semantic handler. */ + FLD (f_GRi) = f_GRi; + FLD (f_ICCi_1) = f_ICCi_1; + FLD (f_s10) = f_s10; + FLD (f_GRk) = f_GRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_smulicc", "f_GRi 0x%x", 'x', f_GRi, "f_ICCi_1 0x%x", 'x', f_ICCi_1, "f_s10 0x%x", 'x', f_s10, "f_GRk 0x%x", 'x', f_GRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_GRi) = f_GRi; + FLD (in_ICCi_1) = f_ICCi_1; + FLD (out_GRdoublek) = f_GRk; + FLD (out_ICCi_1) = f_ICCi_1; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_addxi: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_addicc.f + UINT f_GRk; + UINT f_GRi; + UINT f_ICCi_1; + INT f_s10; + + f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_ICCi_1 = EXTRACT_LSB0_UINT (insn, 32, 11, 2); + f_s10 = EXTRACT_LSB0_INT (insn, 32, 9, 10); + + /* Record the fields for the semantic handler. */ + FLD (f_GRi) = f_GRi; + FLD (f_ICCi_1) = f_ICCi_1; + FLD (f_s10) = f_s10; + FLD (f_GRk) = f_GRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addxi", "f_GRi 0x%x", 'x', f_GRi, "f_ICCi_1 0x%x", 'x', f_ICCi_1, "f_s10 0x%x", 'x', f_s10, "f_GRk 0x%x", 'x', f_GRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_GRi) = f_GRi; + FLD (in_ICCi_1) = f_ICCi_1; + FLD (out_GRk) = f_GRk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_cmpb: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_smulcc.f + UINT f_GRi; + UINT f_ICCi_1; + UINT f_GRj; + + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_ICCi_1 = EXTRACT_LSB0_UINT (insn, 32, 11, 2); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_GRi) = f_GRi; + FLD (f_GRj) = f_GRj; + FLD (f_ICCi_1) = f_ICCi_1; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmpb", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_ICCi_1 0x%x", 'x', f_ICCi_1, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_GRi) = f_GRi; + FLD (in_GRj) = f_GRj; + FLD (out_ICCi_1) = f_ICCi_1; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_setlo: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_setlo.f + UINT f_GRk; + UINT f_u16; + + f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_u16 = EXTRACT_LSB0_UINT (insn, 32, 15, 16); + + /* Record the fields for the semantic handler. */ + FLD (f_u16) = f_u16; + FLD (f_GRk) = f_GRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_setlo", "f_u16 0x%x", 'x', f_u16, "f_GRk 0x%x", 'x', f_GRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (out_GRklo) = f_GRk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_sethi: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_sethi.f + UINT f_GRk; + UINT f_u16; + + f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_u16 = EXTRACT_LSB0_UINT (insn, 32, 15, 16); + + /* Record the fields for the semantic handler. */ + FLD (f_u16) = f_u16; + FLD (f_GRk) = f_GRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sethi", "f_u16 0x%x", 'x', f_u16, "f_GRk 0x%x", 'x', f_GRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (out_GRkhi) = f_GRk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_setlos: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_setlos.f + UINT f_GRk; + INT f_s16; + + f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_s16 = EXTRACT_LSB0_INT (insn, 32, 15, 16); + + /* Record the fields for the semantic handler. */ + FLD (f_s16) = f_s16; + FLD (f_GRk) = f_GRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_setlos", "f_s16 0x%x", 'x', f_s16, "f_GRk 0x%x", 'x', f_GRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (out_GRk) = f_GRk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_ldsb: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_addcc.f + UINT f_GRk; + UINT f_GRi; + UINT f_GRj; + + f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_GRi) = f_GRi; + FLD (f_GRj) = f_GRj; + FLD (f_GRk) = f_GRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldsb", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_GRk 0x%x", 'x', f_GRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_GRi) = f_GRi; + FLD (in_GRj) = f_GRj; + FLD (out_GRk) = f_GRk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_ldbf: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cldbfu.f + UINT f_FRk; + UINT f_GRi; + UINT f_GRj; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_GRi) = f_GRi; + FLD (f_GRj) = f_GRj; + FLD (f_FRk) = f_FRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldbf", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_GRi) = f_GRi; + FLD (in_GRj) = f_GRj; + FLD (out_FRintk) = f_FRk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_ldc: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_ldcu.f + UINT f_CPRk; + UINT f_GRi; + UINT f_GRj; + + f_CPRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_GRi) = f_GRi; + FLD (f_GRj) = f_GRj; + FLD (f_CPRk) = f_CPRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldc", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_CPRk 0x%x", 'x', f_CPRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_GRi) = f_GRi; + FLD (in_GRj) = f_GRj; + FLD (out_CPRk) = f_CPRk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_nldsb: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_addcc.f + UINT f_GRk; + UINT f_GRi; + UINT f_GRj; + + f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_GRi) = f_GRi; + FLD (f_GRj) = f_GRj; + FLD (f_GRk) = f_GRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_nldsb", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_GRk 0x%x", 'x', f_GRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_GRi) = f_GRi; + FLD (in_GRj) = f_GRj; + FLD (out_GRk) = f_GRk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_nldbf: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cldbfu.f + UINT f_FRk; + UINT f_GRi; + UINT f_GRj; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_GRi) = f_GRi; + FLD (f_GRj) = f_GRj; + FLD (f_FRk) = f_FRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_nldbf", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_GRi) = f_GRi; + FLD (in_GRj) = f_GRj; + FLD (out_FRintk) = f_FRk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_ldd: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_smulcc.f + UINT f_GRk; + UINT f_GRi; + UINT f_GRj; + + f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_GRi) = f_GRi; + FLD (f_GRj) = f_GRj; + FLD (f_GRk) = f_GRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldd", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_GRk 0x%x", 'x', f_GRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_GRi) = f_GRi; + FLD (in_GRj) = f_GRj; + FLD (out_GRdoublek) = f_GRk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_lddf: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_clddfu.f + UINT f_FRk; + UINT f_GRi; + UINT f_GRj; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_GRi) = f_GRi; + FLD (f_GRj) = f_GRj; + FLD (f_FRk) = f_FRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lddf", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_GRi) = f_GRi; + FLD (in_GRj) = f_GRj; + FLD (out_FRdoublek) = f_FRk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_lddc: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_lddcu.f + UINT f_CPRk; + UINT f_GRi; + UINT f_GRj; + + f_CPRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_GRi) = f_GRi; + FLD (f_GRj) = f_GRj; + FLD (f_CPRk) = f_CPRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lddc", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_CPRk 0x%x", 'x', f_CPRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_GRi) = f_GRi; + FLD (in_GRj) = f_GRj; + FLD (out_CPRdoublek) = f_CPRk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_nldd: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_smulcc.f + UINT f_GRk; + UINT f_GRi; + UINT f_GRj; + + f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_GRi) = f_GRi; + FLD (f_GRj) = f_GRj; + FLD (f_GRk) = f_GRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_nldd", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_GRk 0x%x", 'x', f_GRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_GRi) = f_GRi; + FLD (in_GRj) = f_GRj; + FLD (out_GRdoublek) = f_GRk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_nlddf: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_clddfu.f + UINT f_FRk; + UINT f_GRi; + UINT f_GRj; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_GRi) = f_GRi; + FLD (f_GRj) = f_GRj; + FLD (f_FRk) = f_FRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_nlddf", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_GRi) = f_GRi; + FLD (in_GRj) = f_GRj; + FLD (out_FRdoublek) = f_FRk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_ldq: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_smulcc.f + UINT f_GRk; + UINT f_GRi; + UINT f_GRj; + + f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_GRi) = f_GRi; + FLD (f_GRj) = f_GRj; + FLD (f_GRk) = f_GRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldq", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_GRk 0x%x", 'x', f_GRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_GRi) = f_GRi; + FLD (in_GRj) = f_GRj; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_ldqf: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cstdfu.f + UINT f_FRk; + UINT f_GRi; + UINT f_GRj; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_GRi) = f_GRi; + FLD (f_GRj) = f_GRj; + FLD (f_FRk) = f_FRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldqf", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_GRi) = f_GRi; + FLD (in_GRj) = f_GRj; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_ldqc: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_stdcu.f + UINT f_CPRk; + UINT f_GRi; + UINT f_GRj; + + f_CPRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_GRi) = f_GRi; + FLD (f_GRj) = f_GRj; + FLD (f_CPRk) = f_CPRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldqc", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_CPRk 0x%x", 'x', f_CPRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_GRi) = f_GRi; + FLD (in_GRj) = f_GRj; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_nldq: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_smulcc.f + UINT f_GRk; + UINT f_GRi; + UINT f_GRj; + + f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_GRi) = f_GRi; + FLD (f_GRj) = f_GRj; + FLD (f_GRk) = f_GRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_nldq", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_GRk 0x%x", 'x', f_GRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_GRi) = f_GRi; + FLD (in_GRj) = f_GRj; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_nldqf: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cstdfu.f + UINT f_FRk; + UINT f_GRi; + UINT f_GRj; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_GRi) = f_GRi; + FLD (f_GRj) = f_GRj; + FLD (f_FRk) = f_FRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_nldqf", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_GRi) = f_GRi; + FLD (in_GRj) = f_GRj; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_ldsbu: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cldsbu.f + UINT f_GRk; + UINT f_GRi; + UINT f_GRj; + + f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_GRi) = f_GRi; + FLD (f_GRj) = f_GRj; + FLD (f_GRk) = f_GRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldsbu", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_GRk 0x%x", 'x', f_GRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_GRi) = f_GRi; + FLD (in_GRj) = f_GRj; + FLD (out_GRi) = f_GRi; + FLD (out_GRk) = f_GRk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_nldsbu: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cldsbu.f + UINT f_GRk; + UINT f_GRi; + UINT f_GRj; + + f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_GRi) = f_GRi; + FLD (f_GRj) = f_GRj; + FLD (f_GRk) = f_GRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_nldsbu", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_GRk 0x%x", 'x', f_GRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_GRi) = f_GRi; + FLD (in_GRj) = f_GRj; + FLD (out_GRi) = f_GRi; + FLD (out_GRk) = f_GRk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_ldbfu: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cldbfu.f + UINT f_FRk; + UINT f_GRi; + UINT f_GRj; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_GRi) = f_GRi; + FLD (f_GRj) = f_GRj; + FLD (f_FRk) = f_FRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldbfu", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_GRi) = f_GRi; + FLD (in_GRj) = f_GRj; + FLD (out_FRintk) = f_FRk; + FLD (out_GRi) = f_GRi; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_ldcu: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_ldcu.f + UINT f_CPRk; + UINT f_GRi; + UINT f_GRj; + + f_CPRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_GRi) = f_GRi; + FLD (f_GRj) = f_GRj; + FLD (f_CPRk) = f_CPRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldcu", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_CPRk 0x%x", 'x', f_CPRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_GRi) = f_GRi; + FLD (in_GRj) = f_GRj; + FLD (out_CPRk) = f_CPRk; + FLD (out_GRi) = f_GRi; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_nldbfu: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cldbfu.f + UINT f_FRk; + UINT f_GRi; + UINT f_GRj; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_GRi) = f_GRi; + FLD (f_GRj) = f_GRj; + FLD (f_FRk) = f_FRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_nldbfu", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_GRi) = f_GRi; + FLD (in_GRj) = f_GRj; + FLD (out_FRintk) = f_FRk; + FLD (out_GRi) = f_GRi; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_lddu: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_clddu.f + UINT f_GRk; + UINT f_GRi; + UINT f_GRj; + + f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_GRi) = f_GRi; + FLD (f_GRj) = f_GRj; + FLD (f_GRk) = f_GRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lddu", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_GRk 0x%x", 'x', f_GRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_GRi) = f_GRi; + FLD (in_GRj) = f_GRj; + FLD (out_GRdoublek) = f_GRk; + FLD (out_GRi) = f_GRi; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_nlddu: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_clddu.f + UINT f_GRk; + UINT f_GRi; + UINT f_GRj; + + f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_GRi) = f_GRi; + FLD (f_GRj) = f_GRj; + FLD (f_GRk) = f_GRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_nlddu", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_GRk 0x%x", 'x', f_GRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_GRi) = f_GRi; + FLD (in_GRj) = f_GRj; + FLD (out_GRdoublek) = f_GRk; + FLD (out_GRi) = f_GRi; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_lddfu: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_clddfu.f + UINT f_FRk; + UINT f_GRi; + UINT f_GRj; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_GRi) = f_GRi; + FLD (f_GRj) = f_GRj; + FLD (f_FRk) = f_FRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lddfu", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_GRi) = f_GRi; + FLD (in_GRj) = f_GRj; + FLD (out_FRdoublek) = f_FRk; + FLD (out_GRi) = f_GRi; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_lddcu: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_lddcu.f + UINT f_CPRk; + UINT f_GRi; + UINT f_GRj; + + f_CPRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_GRi) = f_GRi; + FLD (f_GRj) = f_GRj; + FLD (f_CPRk) = f_CPRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lddcu", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_CPRk 0x%x", 'x', f_CPRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_GRi) = f_GRi; + FLD (in_GRj) = f_GRj; + FLD (out_CPRdoublek) = f_CPRk; + FLD (out_GRi) = f_GRi; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_nlddfu: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_clddfu.f + UINT f_FRk; + UINT f_GRi; + UINT f_GRj; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_GRi) = f_GRi; + FLD (f_GRj) = f_GRj; + FLD (f_FRk) = f_FRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_nlddfu", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_GRi) = f_GRi; + FLD (in_GRj) = f_GRj; + FLD (out_FRdoublek) = f_FRk; + FLD (out_GRi) = f_GRi; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_ldqu: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cstdu.f + UINT f_GRk; + UINT f_GRi; + UINT f_GRj; + + f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_GRi) = f_GRi; + FLD (f_GRj) = f_GRj; + FLD (f_GRk) = f_GRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldqu", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_GRk 0x%x", 'x', f_GRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_GRi) = f_GRi; + FLD (in_GRj) = f_GRj; + FLD (out_GRi) = f_GRi; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_nldqu: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cstdu.f + UINT f_GRk; + UINT f_GRi; + UINT f_GRj; + + f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_GRi) = f_GRi; + FLD (f_GRj) = f_GRj; + FLD (f_GRk) = f_GRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_nldqu", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_GRk 0x%x", 'x', f_GRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_GRi) = f_GRi; + FLD (in_GRj) = f_GRj; + FLD (out_GRi) = f_GRi; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_ldqfu: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cstdfu.f + UINT f_FRk; + UINT f_GRi; + UINT f_GRj; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_GRi) = f_GRi; + FLD (f_GRj) = f_GRj; + FLD (f_FRk) = f_FRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldqfu", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_GRi) = f_GRi; + FLD (in_GRj) = f_GRj; + FLD (out_GRi) = f_GRi; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_ldqcu: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_stdcu.f + UINT f_CPRk; + UINT f_GRi; + UINT f_GRj; + + f_CPRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_GRi) = f_GRi; + FLD (f_GRj) = f_GRj; + FLD (f_CPRk) = f_CPRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldqcu", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_CPRk 0x%x", 'x', f_CPRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_GRi) = f_GRi; + FLD (in_GRj) = f_GRj; + FLD (out_GRi) = f_GRi; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_nldqfu: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cstdfu.f + UINT f_FRk; + UINT f_GRi; + UINT f_GRj; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_GRi) = f_GRi; + FLD (f_GRj) = f_GRj; + FLD (f_FRk) = f_FRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_nldqfu", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_GRi) = f_GRi; + FLD (in_GRj) = f_GRj; + FLD (out_GRi) = f_GRi; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_ldsbi: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_swapi.f + UINT f_GRk; + UINT f_GRi; + INT f_d12; + + f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_d12 = EXTRACT_LSB0_INT (insn, 32, 11, 12); + + /* Record the fields for the semantic handler. */ + FLD (f_GRi) = f_GRi; + FLD (f_d12) = f_d12; + FLD (f_GRk) = f_GRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldsbi", "f_GRi 0x%x", 'x', f_GRi, "f_d12 0x%x", 'x', f_d12, "f_GRk 0x%x", 'x', f_GRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_GRi) = f_GRi; + FLD (out_GRk) = f_GRk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_ldbfi: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_ldbfi.f + UINT f_FRk; + UINT f_GRi; + INT f_d12; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_d12 = EXTRACT_LSB0_INT (insn, 32, 11, 12); + + /* Record the fields for the semantic handler. */ + FLD (f_GRi) = f_GRi; + FLD (f_d12) = f_d12; + FLD (f_FRk) = f_FRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldbfi", "f_GRi 0x%x", 'x', f_GRi, "f_d12 0x%x", 'x', f_d12, "f_FRk 0x%x", 'x', f_FRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_GRi) = f_GRi; + FLD (out_FRintk) = f_FRk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_nldsbi: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_swapi.f + UINT f_GRk; + UINT f_GRi; + INT f_d12; + + f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_d12 = EXTRACT_LSB0_INT (insn, 32, 11, 12); + + /* Record the fields for the semantic handler. */ + FLD (f_GRi) = f_GRi; + FLD (f_d12) = f_d12; + FLD (f_GRk) = f_GRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_nldsbi", "f_GRi 0x%x", 'x', f_GRi, "f_d12 0x%x", 'x', f_d12, "f_GRk 0x%x", 'x', f_GRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_GRi) = f_GRi; + FLD (out_GRk) = f_GRk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_nldbfi: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_ldbfi.f + UINT f_FRk; + UINT f_GRi; + INT f_d12; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_d12 = EXTRACT_LSB0_INT (insn, 32, 11, 12); + + /* Record the fields for the semantic handler. */ + FLD (f_GRi) = f_GRi; + FLD (f_d12) = f_d12; + FLD (f_FRk) = f_FRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_nldbfi", "f_GRi 0x%x", 'x', f_GRi, "f_d12 0x%x", 'x', f_d12, "f_FRk 0x%x", 'x', f_FRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_GRi) = f_GRi; + FLD (out_FRintk) = f_FRk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_lddi: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_smuli.f + UINT f_GRk; + UINT f_GRi; + INT f_d12; + + f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_d12 = EXTRACT_LSB0_INT (insn, 32, 11, 12); + + /* Record the fields for the semantic handler. */ + FLD (f_GRi) = f_GRi; + FLD (f_d12) = f_d12; + FLD (f_GRk) = f_GRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lddi", "f_GRi 0x%x", 'x', f_GRi, "f_d12 0x%x", 'x', f_d12, "f_GRk 0x%x", 'x', f_GRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_GRi) = f_GRi; + FLD (out_GRdoublek) = f_GRk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_lddfi: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_lddfi.f + UINT f_FRk; + UINT f_GRi; + INT f_d12; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_d12 = EXTRACT_LSB0_INT (insn, 32, 11, 12); + + /* Record the fields for the semantic handler. */ + FLD (f_GRi) = f_GRi; + FLD (f_d12) = f_d12; + FLD (f_FRk) = f_FRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lddfi", "f_GRi 0x%x", 'x', f_GRi, "f_d12 0x%x", 'x', f_d12, "f_FRk 0x%x", 'x', f_FRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_GRi) = f_GRi; + FLD (out_FRdoublek) = f_FRk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_nlddi: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_smuli.f + UINT f_GRk; + UINT f_GRi; + INT f_d12; + + f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_d12 = EXTRACT_LSB0_INT (insn, 32, 11, 12); + + /* Record the fields for the semantic handler. */ + FLD (f_GRi) = f_GRi; + FLD (f_d12) = f_d12; + FLD (f_GRk) = f_GRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_nlddi", "f_GRi 0x%x", 'x', f_GRi, "f_d12 0x%x", 'x', f_d12, "f_GRk 0x%x", 'x', f_GRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_GRi) = f_GRi; + FLD (out_GRdoublek) = f_GRk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_nlddfi: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_lddfi.f + UINT f_FRk; + UINT f_GRi; + INT f_d12; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_d12 = EXTRACT_LSB0_INT (insn, 32, 11, 12); + + /* Record the fields for the semantic handler. */ + FLD (f_GRi) = f_GRi; + FLD (f_d12) = f_d12; + FLD (f_FRk) = f_FRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_nlddfi", "f_GRi 0x%x", 'x', f_GRi, "f_d12 0x%x", 'x', f_d12, "f_FRk 0x%x", 'x', f_FRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_GRi) = f_GRi; + FLD (out_FRdoublek) = f_FRk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_ldqi: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_stdi.f + UINT f_GRk; + UINT f_GRi; + INT f_d12; + + f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_d12 = EXTRACT_LSB0_INT (insn, 32, 11, 12); + + /* Record the fields for the semantic handler. */ + FLD (f_GRi) = f_GRi; + FLD (f_d12) = f_d12; + FLD (f_GRk) = f_GRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldqi", "f_GRi 0x%x", 'x', f_GRi, "f_d12 0x%x", 'x', f_d12, "f_GRk 0x%x", 'x', f_GRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_GRi) = f_GRi; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_ldqfi: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_stdfi.f + UINT f_FRk; + UINT f_GRi; + INT f_d12; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_d12 = EXTRACT_LSB0_INT (insn, 32, 11, 12); + + /* Record the fields for the semantic handler. */ + FLD (f_GRi) = f_GRi; + FLD (f_d12) = f_d12; + FLD (f_FRk) = f_FRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldqfi", "f_GRi 0x%x", 'x', f_GRi, "f_d12 0x%x", 'x', f_d12, "f_FRk 0x%x", 'x', f_FRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_GRi) = f_GRi; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_nldqfi: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_stdfi.f + UINT f_FRk; + UINT f_GRi; + INT f_d12; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_d12 = EXTRACT_LSB0_INT (insn, 32, 11, 12); + + /* Record the fields for the semantic handler. */ + FLD (f_GRi) = f_GRi; + FLD (f_d12) = f_d12; + FLD (f_FRk) = f_FRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_nldqfi", "f_GRi 0x%x", 'x', f_GRi, "f_d12 0x%x", 'x', f_d12, "f_FRk 0x%x", 'x', f_FRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_GRi) = f_GRi; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_stb: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cswap.f + UINT f_GRk; + UINT f_GRi; + UINT f_GRj; + + f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_GRi) = f_GRi; + FLD (f_GRj) = f_GRj; + FLD (f_GRk) = f_GRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_GRk 0x%x", 'x', f_GRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_GRi) = f_GRi; + FLD (in_GRj) = f_GRj; + FLD (in_GRk) = f_GRk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_stbf: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cstbfu.f + UINT f_FRk; + UINT f_GRi; + UINT f_GRj; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_FRk) = f_FRk; + FLD (f_GRi) = f_GRi; + FLD (f_GRj) = f_GRj; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stbf", "f_FRk 0x%x", 'x', f_FRk, "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_FRintk) = f_FRk; + FLD (in_GRi) = f_GRi; + FLD (in_GRj) = f_GRj; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_stc: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_stcu.f + UINT f_CPRk; + UINT f_GRi; + UINT f_GRj; + + f_CPRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_CPRk) = f_CPRk; + FLD (f_GRi) = f_GRi; + FLD (f_GRj) = f_GRj; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stc", "f_CPRk 0x%x", 'x', f_CPRk, "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_CPRk) = f_CPRk; + FLD (in_GRi) = f_GRi; + FLD (in_GRj) = f_GRj; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_rstb: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cswap.f + UINT f_GRk; + UINT f_GRi; + UINT f_GRj; + + f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_GRi) = f_GRi; + FLD (f_GRj) = f_GRj; + FLD (f_GRk) = f_GRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rstb", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_GRk 0x%x", 'x', f_GRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_GRi) = f_GRi; + FLD (in_GRj) = f_GRj; + FLD (in_GRk) = f_GRk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_rstbf: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cstbfu.f + UINT f_FRk; + UINT f_GRi; + UINT f_GRj; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_FRk) = f_FRk; + FLD (f_GRi) = f_GRi; + FLD (f_GRj) = f_GRj; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rstbf", "f_FRk 0x%x", 'x', f_FRk, "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_FRintk) = f_FRk; + FLD (in_GRi) = f_GRi; + FLD (in_GRj) = f_GRj; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_std: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cstdu.f + UINT f_GRk; + UINT f_GRi; + UINT f_GRj; + + f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_GRk) = f_GRk; + FLD (f_GRi) = f_GRi; + FLD (f_GRj) = f_GRj; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_std", "f_GRk 0x%x", 'x', f_GRk, "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_GRdoublek) = f_GRk; + FLD (in_GRi) = f_GRi; + FLD (in_GRj) = f_GRj; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_stdf: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cstdfu.f + UINT f_FRk; + UINT f_GRi; + UINT f_GRj; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_FRk) = f_FRk; + FLD (f_GRi) = f_GRi; + FLD (f_GRj) = f_GRj; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stdf", "f_FRk 0x%x", 'x', f_FRk, "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_FRdoublek) = f_FRk; + FLD (in_GRi) = f_GRi; + FLD (in_GRj) = f_GRj; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_stdc: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_stdcu.f + UINT f_CPRk; + UINT f_GRi; + UINT f_GRj; + + f_CPRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_CPRk) = f_CPRk; + FLD (f_GRi) = f_GRi; + FLD (f_GRj) = f_GRj; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stdc", "f_CPRk 0x%x", 'x', f_CPRk, "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_CPRdoublek) = f_CPRk; + FLD (in_GRi) = f_GRi; + FLD (in_GRj) = f_GRj; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_rstd: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cstdu.f + UINT f_GRk; + UINT f_GRi; + UINT f_GRj; + + f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_GRk) = f_GRk; + FLD (f_GRi) = f_GRi; + FLD (f_GRj) = f_GRj; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rstd", "f_GRk 0x%x", 'x', f_GRk, "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_GRdoublek) = f_GRk; + FLD (in_GRi) = f_GRi; + FLD (in_GRj) = f_GRj; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_rstdf: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cstdfu.f + UINT f_FRk; + UINT f_GRi; + UINT f_GRj; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_FRk) = f_FRk; + FLD (f_GRi) = f_GRi; + FLD (f_GRj) = f_GRj; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rstdf", "f_FRk 0x%x", 'x', f_FRk, "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_FRdoublek) = f_FRk; + FLD (in_GRi) = f_GRi; + FLD (in_GRj) = f_GRj; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_stbu: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cstbu.f + UINT f_GRk; + UINT f_GRi; + UINT f_GRj; + + f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_GRi) = f_GRi; + FLD (f_GRj) = f_GRj; + FLD (f_GRk) = f_GRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stbu", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_GRk 0x%x", 'x', f_GRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_GRi) = f_GRi; + FLD (in_GRj) = f_GRj; + FLD (in_GRk) = f_GRk; + FLD (out_GRi) = f_GRi; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_stbfu: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cstbfu.f + UINT f_FRk; + UINT f_GRi; + UINT f_GRj; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_FRk) = f_FRk; + FLD (f_GRi) = f_GRi; + FLD (f_GRj) = f_GRj; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stbfu", "f_FRk 0x%x", 'x', f_FRk, "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_FRintk) = f_FRk; + FLD (in_GRi) = f_GRi; + FLD (in_GRj) = f_GRj; + FLD (out_GRi) = f_GRi; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_stcu: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_stcu.f + UINT f_CPRk; + UINT f_GRi; + UINT f_GRj; + + f_CPRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_CPRk) = f_CPRk; + FLD (f_GRi) = f_GRi; + FLD (f_GRj) = f_GRj; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stcu", "f_CPRk 0x%x", 'x', f_CPRk, "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_CPRk) = f_CPRk; + FLD (in_GRi) = f_GRi; + FLD (in_GRj) = f_GRj; + FLD (out_GRi) = f_GRi; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_stdu: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cstdu.f + UINT f_GRk; + UINT f_GRi; + UINT f_GRj; + + f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_GRk) = f_GRk; + FLD (f_GRi) = f_GRi; + FLD (f_GRj) = f_GRj; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stdu", "f_GRk 0x%x", 'x', f_GRk, "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_GRdoublek) = f_GRk; + FLD (in_GRi) = f_GRi; + FLD (in_GRj) = f_GRj; + FLD (out_GRi) = f_GRi; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_stdfu: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cstdfu.f + UINT f_FRk; + UINT f_GRi; + UINT f_GRj; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_FRk) = f_FRk; + FLD (f_GRi) = f_GRi; + FLD (f_GRj) = f_GRj; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stdfu", "f_FRk 0x%x", 'x', f_FRk, "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_FRdoublek) = f_FRk; + FLD (in_GRi) = f_GRi; + FLD (in_GRj) = f_GRj; + FLD (out_GRi) = f_GRi; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_stdcu: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_stdcu.f + UINT f_CPRk; + UINT f_GRi; + UINT f_GRj; + + f_CPRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_CPRk) = f_CPRk; + FLD (f_GRi) = f_GRi; + FLD (f_GRj) = f_GRj; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stdcu", "f_CPRk 0x%x", 'x', f_CPRk, "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_CPRdoublek) = f_CPRk; + FLD (in_GRi) = f_GRi; + FLD (in_GRj) = f_GRj; + FLD (out_GRi) = f_GRi; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_stqu: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cstdu.f + UINT f_GRk; + UINT f_GRi; + UINT f_GRj; + + f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_GRi) = f_GRi; + FLD (f_GRj) = f_GRj; + FLD (f_GRk) = f_GRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stqu", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_GRk 0x%x", 'x', f_GRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_GRi) = f_GRi; + FLD (in_GRj) = f_GRj; + FLD (out_GRi) = f_GRi; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_cldsb: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cswap.f + UINT f_GRk; + UINT f_GRi; + UINT f_CCi; + UINT f_cond; + UINT f_GRj; + + f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); + f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_CCi) = f_CCi; + FLD (f_GRi) = f_GRi; + FLD (f_GRj) = f_GRj; + FLD (f_cond) = f_cond; + FLD (f_GRk) = f_GRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cldsb", "f_CCi 0x%x", 'x', f_CCi, "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_cond 0x%x", 'x', f_cond, "f_GRk 0x%x", 'x', f_GRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_CCi) = f_CCi; + FLD (in_GRi) = f_GRi; + FLD (in_GRj) = f_GRj; + FLD (out_GRk) = f_GRk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_cldbf: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cldbfu.f + UINT f_FRk; + UINT f_GRi; + UINT f_CCi; + UINT f_cond; + UINT f_GRj; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); + f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_CCi) = f_CCi; + FLD (f_GRi) = f_GRi; + FLD (f_GRj) = f_GRj; + FLD (f_cond) = f_cond; + FLD (f_FRk) = f_FRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cldbf", "f_CCi 0x%x", 'x', f_CCi, "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_cond 0x%x", 'x', f_cond, "f_FRk 0x%x", 'x', f_FRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_CCi) = f_CCi; + FLD (in_GRi) = f_GRi; + FLD (in_GRj) = f_GRj; + FLD (out_FRintk) = f_FRk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_cldd: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_clddu.f + UINT f_GRk; + UINT f_GRi; + UINT f_CCi; + UINT f_cond; + UINT f_GRj; + + f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); + f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_CCi) = f_CCi; + FLD (f_GRi) = f_GRi; + FLD (f_GRj) = f_GRj; + FLD (f_cond) = f_cond; + FLD (f_GRk) = f_GRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cldd", "f_CCi 0x%x", 'x', f_CCi, "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_cond 0x%x", 'x', f_cond, "f_GRk 0x%x", 'x', f_GRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_CCi) = f_CCi; + FLD (in_GRi) = f_GRi; + FLD (in_GRj) = f_GRj; + FLD (out_GRdoublek) = f_GRk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_clddf: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_clddfu.f + UINT f_FRk; + UINT f_GRi; + UINT f_CCi; + UINT f_cond; + UINT f_GRj; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); + f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_CCi) = f_CCi; + FLD (f_GRi) = f_GRi; + FLD (f_GRj) = f_GRj; + FLD (f_cond) = f_cond; + FLD (f_FRk) = f_FRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_clddf", "f_CCi 0x%x", 'x', f_CCi, "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_cond 0x%x", 'x', f_cond, "f_FRk 0x%x", 'x', f_FRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_CCi) = f_CCi; + FLD (in_GRi) = f_GRi; + FLD (in_GRj) = f_GRj; + FLD (out_FRdoublek) = f_FRk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_cldq: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cswap.f + UINT f_GRk; + UINT f_GRi; + UINT f_CCi; + UINT f_cond; + UINT f_GRj; + + f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); + f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_CCi) = f_CCi; + FLD (f_GRi) = f_GRi; + FLD (f_GRj) = f_GRj; + FLD (f_cond) = f_cond; + FLD (f_GRk) = f_GRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cldq", "f_CCi 0x%x", 'x', f_CCi, "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_cond 0x%x", 'x', f_cond, "f_GRk 0x%x", 'x', f_GRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_CCi) = f_CCi; + FLD (in_GRi) = f_GRi; + FLD (in_GRj) = f_GRj; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_cldsbu: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cldsbu.f + UINT f_GRk; + UINT f_GRi; + UINT f_CCi; + UINT f_cond; + UINT f_GRj; + + f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); + f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_CCi) = f_CCi; + FLD (f_GRi) = f_GRi; + FLD (f_GRj) = f_GRj; + FLD (f_cond) = f_cond; + FLD (f_GRk) = f_GRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cldsbu", "f_CCi 0x%x", 'x', f_CCi, "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_cond 0x%x", 'x', f_cond, "f_GRk 0x%x", 'x', f_GRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_CCi) = f_CCi; + FLD (in_GRi) = f_GRi; + FLD (in_GRj) = f_GRj; + FLD (out_GRi) = f_GRi; + FLD (out_GRk) = f_GRk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_cldbfu: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cldbfu.f + UINT f_FRk; + UINT f_GRi; + UINT f_CCi; + UINT f_cond; + UINT f_GRj; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); + f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_CCi) = f_CCi; + FLD (f_GRi) = f_GRi; + FLD (f_GRj) = f_GRj; + FLD (f_cond) = f_cond; + FLD (f_FRk) = f_FRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cldbfu", "f_CCi 0x%x", 'x', f_CCi, "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_cond 0x%x", 'x', f_cond, "f_FRk 0x%x", 'x', f_FRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_CCi) = f_CCi; + FLD (in_GRi) = f_GRi; + FLD (in_GRj) = f_GRj; + FLD (out_FRintk) = f_FRk; + FLD (out_GRi) = f_GRi; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_clddu: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_clddu.f + UINT f_GRk; + UINT f_GRi; + UINT f_CCi; + UINT f_cond; + UINT f_GRj; + + f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); + f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_CCi) = f_CCi; + FLD (f_GRi) = f_GRi; + FLD (f_GRj) = f_GRj; + FLD (f_cond) = f_cond; + FLD (f_GRk) = f_GRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_clddu", "f_CCi 0x%x", 'x', f_CCi, "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_cond 0x%x", 'x', f_cond, "f_GRk 0x%x", 'x', f_GRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_CCi) = f_CCi; + FLD (in_GRi) = f_GRi; + FLD (in_GRj) = f_GRj; + FLD (out_GRdoublek) = f_GRk; + FLD (out_GRi) = f_GRi; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_clddfu: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_clddfu.f + UINT f_FRk; + UINT f_GRi; + UINT f_CCi; + UINT f_cond; + UINT f_GRj; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); + f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_CCi) = f_CCi; + FLD (f_GRi) = f_GRi; + FLD (f_GRj) = f_GRj; + FLD (f_cond) = f_cond; + FLD (f_FRk) = f_FRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_clddfu", "f_CCi 0x%x", 'x', f_CCi, "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_cond 0x%x", 'x', f_cond, "f_FRk 0x%x", 'x', f_FRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_CCi) = f_CCi; + FLD (in_GRi) = f_GRi; + FLD (in_GRj) = f_GRj; + FLD (out_FRdoublek) = f_FRk; + FLD (out_GRi) = f_GRi; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_cldqu: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cstdu.f + UINT f_GRk; + UINT f_GRi; + UINT f_CCi; + UINT f_cond; + UINT f_GRj; + + f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); + f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_CCi) = f_CCi; + FLD (f_GRi) = f_GRi; + FLD (f_GRj) = f_GRj; + FLD (f_cond) = f_cond; + FLD (f_GRk) = f_GRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cldqu", "f_CCi 0x%x", 'x', f_CCi, "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_cond 0x%x", 'x', f_cond, "f_GRk 0x%x", 'x', f_GRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_CCi) = f_CCi; + FLD (in_GRi) = f_GRi; + FLD (in_GRj) = f_GRj; + FLD (out_GRi) = f_GRi; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_cstb: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cswap.f + UINT f_GRk; + UINT f_GRi; + UINT f_CCi; + UINT f_cond; + UINT f_GRj; + + f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); + f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_CCi) = f_CCi; + FLD (f_GRi) = f_GRi; + FLD (f_GRj) = f_GRj; + FLD (f_GRk) = f_GRk; + FLD (f_cond) = f_cond; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cstb", "f_CCi 0x%x", 'x', f_CCi, "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_GRk 0x%x", 'x', f_GRk, "f_cond 0x%x", 'x', f_cond, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_CCi) = f_CCi; + FLD (in_GRi) = f_GRi; + FLD (in_GRj) = f_GRj; + FLD (in_GRk) = f_GRk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_cstbf: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cstbfu.f + UINT f_FRk; + UINT f_GRi; + UINT f_CCi; + UINT f_cond; + UINT f_GRj; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); + f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_CCi) = f_CCi; + FLD (f_FRk) = f_FRk; + FLD (f_GRi) = f_GRi; + FLD (f_GRj) = f_GRj; + FLD (f_cond) = f_cond; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cstbf", "f_CCi 0x%x", 'x', f_CCi, "f_FRk 0x%x", 'x', f_FRk, "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_cond 0x%x", 'x', f_cond, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_CCi) = f_CCi; + FLD (in_FRintk) = f_FRk; + FLD (in_GRi) = f_GRi; + FLD (in_GRj) = f_GRj; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_cstd: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cstdu.f + UINT f_GRk; + UINT f_GRi; + UINT f_CCi; + UINT f_cond; + UINT f_GRj; + + f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); + f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_CCi) = f_CCi; + FLD (f_GRk) = f_GRk; + FLD (f_GRi) = f_GRi; + FLD (f_GRj) = f_GRj; + FLD (f_cond) = f_cond; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cstd", "f_CCi 0x%x", 'x', f_CCi, "f_GRk 0x%x", 'x', f_GRk, "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_cond 0x%x", 'x', f_cond, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_CCi) = f_CCi; + FLD (in_GRdoublek) = f_GRk; + FLD (in_GRi) = f_GRi; + FLD (in_GRj) = f_GRj; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_cstdf: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cstdfu.f + UINT f_FRk; + UINT f_GRi; + UINT f_CCi; + UINT f_cond; + UINT f_GRj; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); + f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_CCi) = f_CCi; + FLD (f_FRk) = f_FRk; + FLD (f_GRi) = f_GRi; + FLD (f_GRj) = f_GRj; + FLD (f_cond) = f_cond; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cstdf", "f_CCi 0x%x", 'x', f_CCi, "f_FRk 0x%x", 'x', f_FRk, "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_cond 0x%x", 'x', f_cond, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_CCi) = f_CCi; + FLD (in_FRdoublek) = f_FRk; + FLD (in_GRi) = f_GRi; + FLD (in_GRj) = f_GRj; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_cstbu: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cstbu.f + UINT f_GRk; + UINT f_GRi; + UINT f_CCi; + UINT f_cond; + UINT f_GRj; + + f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); + f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_CCi) = f_CCi; + FLD (f_GRi) = f_GRi; + FLD (f_GRj) = f_GRj; + FLD (f_GRk) = f_GRk; + FLD (f_cond) = f_cond; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cstbu", "f_CCi 0x%x", 'x', f_CCi, "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_GRk 0x%x", 'x', f_GRk, "f_cond 0x%x", 'x', f_cond, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_CCi) = f_CCi; + FLD (in_GRi) = f_GRi; + FLD (in_GRj) = f_GRj; + FLD (in_GRk) = f_GRk; + FLD (out_GRi) = f_GRi; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_cstbfu: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cstbfu.f + UINT f_FRk; + UINT f_GRi; + UINT f_CCi; + UINT f_cond; + UINT f_GRj; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); + f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_CCi) = f_CCi; + FLD (f_FRk) = f_FRk; + FLD (f_GRi) = f_GRi; + FLD (f_GRj) = f_GRj; + FLD (f_cond) = f_cond; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cstbfu", "f_CCi 0x%x", 'x', f_CCi, "f_FRk 0x%x", 'x', f_FRk, "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_cond 0x%x", 'x', f_cond, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_CCi) = f_CCi; + FLD (in_FRintk) = f_FRk; + FLD (in_GRi) = f_GRi; + FLD (in_GRj) = f_GRj; + FLD (out_GRi) = f_GRi; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_cstdu: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cstdu.f + UINT f_GRk; + UINT f_GRi; + UINT f_CCi; + UINT f_cond; + UINT f_GRj; + + f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); + f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_CCi) = f_CCi; + FLD (f_GRk) = f_GRk; + FLD (f_GRi) = f_GRi; + FLD (f_GRj) = f_GRj; + FLD (f_cond) = f_cond; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cstdu", "f_CCi 0x%x", 'x', f_CCi, "f_GRk 0x%x", 'x', f_GRk, "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_cond 0x%x", 'x', f_cond, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_CCi) = f_CCi; + FLD (in_GRdoublek) = f_GRk; + FLD (in_GRi) = f_GRi; + FLD (in_GRj) = f_GRj; + FLD (out_GRi) = f_GRi; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_cstdfu: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cstdfu.f + UINT f_FRk; + UINT f_GRi; + UINT f_CCi; + UINT f_cond; + UINT f_GRj; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); + f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_CCi) = f_CCi; + FLD (f_FRk) = f_FRk; + FLD (f_GRi) = f_GRi; + FLD (f_GRj) = f_GRj; + FLD (f_cond) = f_cond; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cstdfu", "f_CCi 0x%x", 'x', f_CCi, "f_FRk 0x%x", 'x', f_FRk, "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_cond 0x%x", 'x', f_cond, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_CCi) = f_CCi; + FLD (in_FRdoublek) = f_FRk; + FLD (in_GRi) = f_GRi; + FLD (in_GRj) = f_GRj; + FLD (out_GRi) = f_GRi; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_stbi: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_swapi.f + UINT f_GRk; + UINT f_GRi; + INT f_d12; + + f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_d12 = EXTRACT_LSB0_INT (insn, 32, 11, 12); + + /* Record the fields for the semantic handler. */ + FLD (f_GRi) = f_GRi; + FLD (f_GRk) = f_GRk; + FLD (f_d12) = f_d12; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stbi", "f_GRi 0x%x", 'x', f_GRi, "f_GRk 0x%x", 'x', f_GRk, "f_d12 0x%x", 'x', f_d12, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_GRi) = f_GRi; + FLD (in_GRk) = f_GRk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_stbfi: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_stbfi.f + UINT f_FRk; + UINT f_GRi; + INT f_d12; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_d12 = EXTRACT_LSB0_INT (insn, 32, 11, 12); + + /* Record the fields for the semantic handler. */ + FLD (f_FRk) = f_FRk; + FLD (f_GRi) = f_GRi; + FLD (f_d12) = f_d12; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stbfi", "f_FRk 0x%x", 'x', f_FRk, "f_GRi 0x%x", 'x', f_GRi, "f_d12 0x%x", 'x', f_d12, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_FRintk) = f_FRk; + FLD (in_GRi) = f_GRi; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_stdi: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_stdi.f + UINT f_GRk; + UINT f_GRi; + INT f_d12; + + f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_d12 = EXTRACT_LSB0_INT (insn, 32, 11, 12); + + /* Record the fields for the semantic handler. */ + FLD (f_GRk) = f_GRk; + FLD (f_GRi) = f_GRi; + FLD (f_d12) = f_d12; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stdi", "f_GRk 0x%x", 'x', f_GRk, "f_GRi 0x%x", 'x', f_GRi, "f_d12 0x%x", 'x', f_d12, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_GRdoublek) = f_GRk; + FLD (in_GRi) = f_GRi; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_stdfi: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_stdfi.f + UINT f_FRk; + UINT f_GRi; + INT f_d12; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_d12 = EXTRACT_LSB0_INT (insn, 32, 11, 12); + + /* Record the fields for the semantic handler. */ + FLD (f_FRk) = f_FRk; + FLD (f_GRi) = f_GRi; + FLD (f_d12) = f_d12; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stdfi", "f_FRk 0x%x", 'x', f_FRk, "f_GRi 0x%x", 'x', f_GRi, "f_d12 0x%x", 'x', f_d12, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_FRdoublek) = f_FRk; + FLD (in_GRi) = f_GRi; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_swap: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cswap.f + UINT f_GRk; + UINT f_GRi; + UINT f_GRj; + + f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_GRi) = f_GRi; + FLD (f_GRj) = f_GRj; + FLD (f_GRk) = f_GRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_swap", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_GRk 0x%x", 'x', f_GRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_GRi) = f_GRi; + FLD (in_GRj) = f_GRj; + FLD (in_GRk) = f_GRk; + FLD (out_GRk) = f_GRk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_swapi: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_swapi.f + UINT f_GRk; + UINT f_GRi; + INT f_d12; + + f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_d12 = EXTRACT_LSB0_INT (insn, 32, 11, 12); + + /* Record the fields for the semantic handler. */ + FLD (f_GRi) = f_GRi; + FLD (f_GRk) = f_GRk; + FLD (f_d12) = f_d12; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_swapi", "f_GRi 0x%x", 'x', f_GRi, "f_GRk 0x%x", 'x', f_GRk, "f_d12 0x%x", 'x', f_d12, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_GRi) = f_GRi; + FLD (in_GRk) = f_GRk; + FLD (out_GRk) = f_GRk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_cswap: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cswap.f + UINT f_GRk; + UINT f_GRi; + UINT f_CCi; + UINT f_cond; + UINT f_GRj; + + f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); + f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_CCi) = f_CCi; + FLD (f_GRi) = f_GRi; + FLD (f_GRj) = f_GRj; + FLD (f_GRk) = f_GRk; + FLD (f_cond) = f_cond; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cswap", "f_CCi 0x%x", 'x', f_CCi, "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_GRk 0x%x", 'x', f_GRk, "f_cond 0x%x", 'x', f_cond, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_CCi) = f_CCi; + FLD (in_GRi) = f_GRi; + FLD (in_GRj) = f_GRj; + FLD (in_GRk) = f_GRk; + FLD (out_GRk) = f_GRk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_movgf: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cmovgfd.f + UINT f_FRk; + UINT f_GRj; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_GRj) = f_GRj; + FLD (f_FRk) = f_FRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movgf", "f_GRj 0x%x", 'x', f_GRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_GRj) = f_GRj; + FLD (out_FRintk) = f_FRk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_movfg: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cmovfgd.f + UINT f_FRk; + UINT f_GRj; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_FRk) = f_FRk; + FLD (f_GRj) = f_GRj; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movfg", "f_FRk 0x%x", 'x', f_FRk, "f_GRj 0x%x", 'x', f_GRj, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_FRintk) = f_FRk; + FLD (out_GRj) = f_GRj; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_movgfd: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cmovgfd.f + UINT f_FRk; + UINT f_GRj; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_GRj) = f_GRj; + FLD (f_FRk) = f_FRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movgfd", "f_GRj 0x%x", 'x', f_GRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_GRj) = f_GRj; + FLD (in_h_gr_USI_add__DFLT_index_of__DFLT_GRj_1) = ((FLD (f_GRj)) + (1)); + FLD (out_FRintk) = f_FRk; + FLD (out_h_fr_int_USI_add__DFLT_index_of__DFLT_FRintk_1) = ((FLD (f_FRk)) + (1)); + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_movfgd: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cmovfgd.f + UINT f_FRk; + UINT f_GRj; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_FRk) = f_FRk; + FLD (f_GRj) = f_GRj; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movfgd", "f_FRk 0x%x", 'x', f_FRk, "f_GRj 0x%x", 'x', f_GRj, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_FRintk) = f_FRk; + FLD (in_h_fr_int_USI_add__DFLT_index_of__DFLT_FRintk_1) = ((FLD (f_FRk)) + (1)); + FLD (out_GRj) = f_GRj; + FLD (out_h_gr_USI_add__DFLT_index_of__DFLT_GRj_1) = ((FLD (f_GRj)) + (1)); + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_movgfq: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_movgfq.f + UINT f_FRk; + UINT f_GRj; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_GRj) = f_GRj; + FLD (f_FRk) = f_FRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movgfq", "f_GRj 0x%x", 'x', f_GRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_GRj) = f_GRj; + FLD (in_h_gr_USI_add__DFLT_index_of__DFLT_GRj_1) = ((FLD (f_GRj)) + (1)); + FLD (in_h_gr_USI_add__DFLT_index_of__DFLT_GRj_2) = ((FLD (f_GRj)) + (2)); + FLD (in_h_gr_USI_add__DFLT_index_of__DFLT_GRj_3) = ((FLD (f_GRj)) + (3)); + FLD (out_FRintk) = f_FRk; + FLD (out_h_fr_int_USI_add__DFLT_index_of__DFLT_FRintk_1) = ((FLD (f_FRk)) + (1)); + FLD (out_h_fr_int_USI_add__DFLT_index_of__DFLT_FRintk_2) = ((FLD (f_FRk)) + (2)); + FLD (out_h_fr_int_USI_add__DFLT_index_of__DFLT_FRintk_3) = ((FLD (f_FRk)) + (3)); + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_movfgq: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_movfgq.f + UINT f_FRk; + UINT f_GRj; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_FRk) = f_FRk; + FLD (f_GRj) = f_GRj; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movfgq", "f_FRk 0x%x", 'x', f_FRk, "f_GRj 0x%x", 'x', f_GRj, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_FRintk) = f_FRk; + FLD (in_h_fr_int_USI_add__DFLT_index_of__DFLT_FRintk_1) = ((FLD (f_FRk)) + (1)); + FLD (in_h_fr_int_USI_add__DFLT_index_of__DFLT_FRintk_2) = ((FLD (f_FRk)) + (2)); + FLD (in_h_fr_int_USI_add__DFLT_index_of__DFLT_FRintk_3) = ((FLD (f_FRk)) + (3)); + FLD (out_GRj) = f_GRj; + FLD (out_h_gr_USI_add__DFLT_index_of__DFLT_GRj_1) = ((FLD (f_GRj)) + (1)); + FLD (out_h_gr_USI_add__DFLT_index_of__DFLT_GRj_2) = ((FLD (f_GRj)) + (2)); + FLD (out_h_gr_USI_add__DFLT_index_of__DFLT_GRj_3) = ((FLD (f_GRj)) + (3)); + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_cmovgf: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cmovgfd.f + UINT f_FRk; + UINT f_CCi; + UINT f_cond; + UINT f_GRj; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); + f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_CCi) = f_CCi; + FLD (f_GRj) = f_GRj; + FLD (f_cond) = f_cond; + FLD (f_FRk) = f_FRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmovgf", "f_CCi 0x%x", 'x', f_CCi, "f_GRj 0x%x", 'x', f_GRj, "f_cond 0x%x", 'x', f_cond, "f_FRk 0x%x", 'x', f_FRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_CCi) = f_CCi; + FLD (in_GRj) = f_GRj; + FLD (out_FRintk) = f_FRk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_cmovfg: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cmovfgd.f + UINT f_FRk; + UINT f_CCi; + UINT f_cond; + UINT f_GRj; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); + f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_CCi) = f_CCi; + FLD (f_FRk) = f_FRk; + FLD (f_cond) = f_cond; + FLD (f_GRj) = f_GRj; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmovfg", "f_CCi 0x%x", 'x', f_CCi, "f_FRk 0x%x", 'x', f_FRk, "f_cond 0x%x", 'x', f_cond, "f_GRj 0x%x", 'x', f_GRj, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_CCi) = f_CCi; + FLD (in_FRintk) = f_FRk; + FLD (out_GRj) = f_GRj; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_cmovgfd: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cmovgfd.f + UINT f_FRk; + UINT f_CCi; + UINT f_cond; + UINT f_GRj; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); + f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_CCi) = f_CCi; + FLD (f_GRj) = f_GRj; + FLD (f_cond) = f_cond; + FLD (f_FRk) = f_FRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmovgfd", "f_CCi 0x%x", 'x', f_CCi, "f_GRj 0x%x", 'x', f_GRj, "f_cond 0x%x", 'x', f_cond, "f_FRk 0x%x", 'x', f_FRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_CCi) = f_CCi; + FLD (in_GRj) = f_GRj; + FLD (in_h_gr_USI_add__DFLT_index_of__DFLT_GRj_1) = ((FLD (f_GRj)) + (1)); + FLD (out_FRintk) = f_FRk; + FLD (out_h_fr_int_USI_add__DFLT_index_of__DFLT_FRintk_1) = ((FLD (f_FRk)) + (1)); + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_cmovfgd: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cmovfgd.f + UINT f_FRk; + UINT f_CCi; + UINT f_cond; + UINT f_GRj; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); + f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_CCi) = f_CCi; + FLD (f_FRk) = f_FRk; + FLD (f_cond) = f_cond; + FLD (f_GRj) = f_GRj; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmovfgd", "f_CCi 0x%x", 'x', f_CCi, "f_FRk 0x%x", 'x', f_FRk, "f_cond 0x%x", 'x', f_cond, "f_GRj 0x%x", 'x', f_GRj, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_CCi) = f_CCi; + FLD (in_FRintk) = f_FRk; + FLD (in_h_fr_int_USI_add__DFLT_index_of__DFLT_FRintk_1) = ((FLD (f_FRk)) + (1)); + FLD (out_GRj) = f_GRj; + FLD (out_h_gr_USI_add__DFLT_index_of__DFLT_GRj_1) = ((FLD (f_GRj)) + (1)); + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_movgs: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_movgs.f + UINT f_spr_h; + UINT f_spr_l; + UINT f_GRj; + UINT f_spr; + + f_spr_h = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_spr_l = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); +{ + f_spr = ((((f_spr_h) << (6))) | (f_spr_l)); +} + + /* Record the fields for the semantic handler. */ + FLD (f_GRj) = f_GRj; + FLD (f_spr) = f_spr; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movgs", "f_GRj 0x%x", 'x', f_GRj, "f_spr 0x%x", 'x', f_spr, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_GRj) = f_GRj; + FLD (out_spr) = f_spr; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_movsg: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_movsg.f + UINT f_spr_h; + UINT f_spr_l; + UINT f_GRj; + UINT f_spr; + + f_spr_h = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_spr_l = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); +{ + f_spr = ((((f_spr_h) << (6))) | (f_spr_l)); +} + + /* Record the fields for the semantic handler. */ + FLD (f_spr) = f_spr; + FLD (f_GRj) = f_GRj; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movsg", "f_spr 0x%x", 'x', f_spr, "f_GRj 0x%x", 'x', f_GRj, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_spr) = f_spr; + FLD (out_GRj) = f_GRj; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_bra: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_fbne.f + UINT f_hint; + SI f_label16; + + f_hint = EXTRACT_LSB0_UINT (insn, 32, 17, 2); + f_label16 = ((((EXTRACT_LSB0_INT (insn, 32, 15, 16)) << (2))) + (pc)); + + /* Record the fields for the semantic handler. */ + FLD (f_hint) = f_hint; + FLD (i_label16) = f_label16; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bra", "f_hint 0x%x", 'x', f_hint, "label16 0x%x", 'x', f_label16, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_bno: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_fbne.f + UINT f_hint; + SI f_label16; + + f_hint = EXTRACT_LSB0_UINT (insn, 32, 17, 2); + f_label16 = ((((EXTRACT_LSB0_INT (insn, 32, 15, 16)) << (2))) + (pc)); + + /* Record the fields for the semantic handler. */ + FLD (f_hint) = f_hint; + FLD (i_label16) = f_label16; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bno", "f_hint 0x%x", 'x', f_hint, "label16 0x%x", 'x', f_label16, (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_beq: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_beq.f + UINT f_ICCi_2; + UINT f_hint; + SI f_label16; + + f_ICCi_2 = EXTRACT_LSB0_UINT (insn, 32, 26, 2); + f_hint = EXTRACT_LSB0_UINT (insn, 32, 17, 2); + f_label16 = ((((EXTRACT_LSB0_INT (insn, 32, 15, 16)) << (2))) + (pc)); + + /* Record the fields for the semantic handler. */ + FLD (f_ICCi_2) = f_ICCi_2; + FLD (f_hint) = f_hint; + FLD (i_label16) = f_label16; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_beq", "f_ICCi_2 0x%x", 'x', f_ICCi_2, "f_hint 0x%x", 'x', f_hint, "label16 0x%x", 'x', f_label16, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_ICCi_2) = f_ICCi_2; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_fbne: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_fbne.f + UINT f_FCCi_2; + UINT f_hint; + SI f_label16; + + f_FCCi_2 = EXTRACT_LSB0_UINT (insn, 32, 26, 2); + f_hint = EXTRACT_LSB0_UINT (insn, 32, 17, 2); + f_label16 = ((((EXTRACT_LSB0_INT (insn, 32, 15, 16)) << (2))) + (pc)); + + /* Record the fields for the semantic handler. */ + FLD (f_FCCi_2) = f_FCCi_2; + FLD (f_hint) = f_hint; + FLD (i_label16) = f_label16; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fbne", "f_FCCi_2 0x%x", 'x', f_FCCi_2, "f_hint 0x%x", 'x', f_hint, "label16 0x%x", 'x', f_label16, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_FCCi_2) = f_FCCi_2; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_bctrlr: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + UINT f_hint; + UINT f_ccond; + + f_hint = EXTRACT_LSB0_UINT (insn, 32, 17, 2); + f_ccond = EXTRACT_LSB0_UINT (insn, 32, 12, 1); + + /* Record the fields for the semantic handler. */ + FLD (f_ccond) = f_ccond; + FLD (f_hint) = f_hint; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bctrlr", "f_ccond 0x%x", 'x', f_ccond, "f_hint 0x%x", 'x', f_hint, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_h_spr_USI_272) = 272; + FLD (in_h_spr_USI_273) = 273; + FLD (out_h_spr_USI_273) = 273; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_bralr: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + UINT f_hint; + + f_hint = EXTRACT_LSB0_UINT (insn, 32, 17, 2); + + /* Record the fields for the semantic handler. */ + FLD (f_hint) = f_hint; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bralr", "f_hint 0x%x", 'x', f_hint, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_h_spr_USI_272) = 272; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_bnolr: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + UINT f_hint; + + f_hint = EXTRACT_LSB0_UINT (insn, 32, 17, 2); + + /* Record the fields for the semantic handler. */ + FLD (f_hint) = f_hint; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bnolr", "f_hint 0x%x", 'x', f_hint, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_h_spr_USI_272) = 272; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_beqlr: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_bceqlr.f + UINT f_ICCi_2; + UINT f_hint; + + f_ICCi_2 = EXTRACT_LSB0_UINT (insn, 32, 26, 2); + f_hint = EXTRACT_LSB0_UINT (insn, 32, 17, 2); + + /* Record the fields for the semantic handler. */ + FLD (f_ICCi_2) = f_ICCi_2; + FLD (f_hint) = f_hint; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_beqlr", "f_ICCi_2 0x%x", 'x', f_ICCi_2, "f_hint 0x%x", 'x', f_hint, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_ICCi_2) = f_ICCi_2; + FLD (in_h_spr_USI_272) = 272; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_fbeqlr: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + UINT f_FCCi_2; + UINT f_hint; + + f_FCCi_2 = EXTRACT_LSB0_UINT (insn, 32, 26, 2); + f_hint = EXTRACT_LSB0_UINT (insn, 32, 17, 2); + + /* Record the fields for the semantic handler. */ + FLD (f_FCCi_2) = f_FCCi_2; + FLD (f_hint) = f_hint; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fbeqlr", "f_FCCi_2 0x%x", 'x', f_FCCi_2, "f_hint 0x%x", 'x', f_hint, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_FCCi_2) = f_FCCi_2; + FLD (in_h_spr_USI_272) = 272; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_bcralr: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + UINT f_hint; + UINT f_ccond; + + f_hint = EXTRACT_LSB0_UINT (insn, 32, 17, 2); + f_ccond = EXTRACT_LSB0_UINT (insn, 32, 12, 1); + + /* Record the fields for the semantic handler. */ + FLD (f_ccond) = f_ccond; + FLD (f_hint) = f_hint; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bcralr", "f_ccond 0x%x", 'x', f_ccond, "f_hint 0x%x", 'x', f_hint, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_h_spr_USI_272) = 272; + FLD (in_h_spr_USI_273) = 273; + FLD (out_h_spr_USI_273) = 273; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_bcnolr: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + UINT f_hint; + + f_hint = EXTRACT_LSB0_UINT (insn, 32, 17, 2); + + /* Record the fields for the semantic handler. */ + FLD (f_hint) = f_hint; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bcnolr", "f_hint 0x%x", 'x', f_hint, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_h_spr_USI_272) = 272; + FLD (in_h_spr_USI_273) = 273; + FLD (out_h_spr_USI_273) = 273; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_bceqlr: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_bceqlr.f + UINT f_ICCi_2; + UINT f_hint; + UINT f_ccond; + + f_ICCi_2 = EXTRACT_LSB0_UINT (insn, 32, 26, 2); + f_hint = EXTRACT_LSB0_UINT (insn, 32, 17, 2); + f_ccond = EXTRACT_LSB0_UINT (insn, 32, 12, 1); + + /* Record the fields for the semantic handler. */ + FLD (f_ICCi_2) = f_ICCi_2; + FLD (f_ccond) = f_ccond; + FLD (f_hint) = f_hint; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bceqlr", "f_ICCi_2 0x%x", 'x', f_ICCi_2, "f_ccond 0x%x", 'x', f_ccond, "f_hint 0x%x", 'x', f_hint, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_ICCi_2) = f_ICCi_2; + FLD (in_h_spr_USI_272) = 272; + FLD (in_h_spr_USI_273) = 273; + FLD (out_h_spr_USI_273) = 273; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_fcbeqlr: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + UINT f_FCCi_2; + UINT f_hint; + UINT f_ccond; + + f_FCCi_2 = EXTRACT_LSB0_UINT (insn, 32, 26, 2); + f_hint = EXTRACT_LSB0_UINT (insn, 32, 17, 2); + f_ccond = EXTRACT_LSB0_UINT (insn, 32, 12, 1); + + /* Record the fields for the semantic handler. */ + FLD (f_FCCi_2) = f_FCCi_2; + FLD (f_ccond) = f_ccond; + FLD (f_hint) = f_hint; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fcbeqlr", "f_FCCi_2 0x%x", 'x', f_FCCi_2, "f_ccond 0x%x", 'x', f_ccond, "f_hint 0x%x", 'x', f_hint, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_FCCi_2) = f_FCCi_2; + FLD (in_h_spr_USI_272) = 272; + FLD (in_h_spr_USI_273) = 273; + FLD (out_h_spr_USI_273) = 273; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_jmpl: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cjmpl.f + UINT f_LI; + UINT f_GRi; + UINT f_GRj; + + f_LI = EXTRACT_LSB0_UINT (insn, 32, 25, 1); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_GRi) = f_GRi; + FLD (f_GRj) = f_GRj; + FLD (f_LI) = f_LI; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jmpl", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_LI 0x%x", 'x', f_LI, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_GRi) = f_GRi; + FLD (in_GRj) = f_GRj; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_jmpil: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_jmpil.f + UINT f_LI; + UINT f_GRi; + INT f_d12; + + f_LI = EXTRACT_LSB0_UINT (insn, 32, 25, 1); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_d12 = EXTRACT_LSB0_INT (insn, 32, 11, 12); + + /* Record the fields for the semantic handler. */ + FLD (f_GRi) = f_GRi; + FLD (f_LI) = f_LI; + FLD (f_d12) = f_d12; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jmpil", "f_GRi 0x%x", 'x', f_GRi, "f_LI 0x%x", 'x', f_LI, "f_d12 0x%x", 'x', f_d12, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_GRi) = f_GRi; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_call: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_call.f + INT f_labelH6; + UINT f_labelL18; + INT f_label24; + + f_labelH6 = EXTRACT_LSB0_INT (insn, 32, 30, 6); + f_labelL18 = EXTRACT_LSB0_UINT (insn, 32, 17, 18); +{ + f_label24 = ((((((((f_labelH6) << (18))) | (f_labelL18))) << (2))) + (pc)); +} + + /* Record the fields for the semantic handler. */ + FLD (i_label24) = f_label24; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_call", "label24 0x%x", 'x', f_label24, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_rett: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_rett.f + UINT f_debug; + + f_debug = EXTRACT_LSB0_UINT (insn, 32, 25, 1); + + /* Record the fields for the semantic handler. */ + FLD (f_debug) = f_debug; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rett", "f_debug 0x%x", 'x', f_debug, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_rei: + { + const IDESC *idesc = &frvbf_insn_data[itype]; +#define FLD(f) abuf->fields.fmt_empty.f + + + /* Record the fields for the semantic handler. */ + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rei", (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_tra: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_ftne.f + UINT f_GRi; + UINT f_GRj; + + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_GRi) = f_GRi; + FLD (f_GRj) = f_GRj; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_tra", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_GRi) = f_GRi; + FLD (in_GRj) = f_GRj; + FLD (out_h_spr_USI_1) = 1; + FLD (out_h_spr_USI_768) = 768; + FLD (out_h_spr_USI_769) = 769; + FLD (out_h_spr_USI_770) = 770; + FLD (out_h_spr_USI_771) = 771; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_teq: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_teq.f + UINT f_ICCi_2; + UINT f_GRi; + UINT f_GRj; + + f_ICCi_2 = EXTRACT_LSB0_UINT (insn, 32, 26, 2); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_GRi) = f_GRi; + FLD (f_GRj) = f_GRj; + FLD (f_ICCi_2) = f_ICCi_2; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_teq", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_ICCi_2 0x%x", 'x', f_ICCi_2, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_GRi) = f_GRi; + FLD (in_GRj) = f_GRj; + FLD (in_ICCi_2) = f_ICCi_2; + FLD (out_h_spr_USI_1) = 1; + FLD (out_h_spr_USI_768) = 768; + FLD (out_h_spr_USI_769) = 769; + FLD (out_h_spr_USI_770) = 770; + FLD (out_h_spr_USI_771) = 771; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_ftne: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_ftne.f + UINT f_FCCi_2; + UINT f_GRi; + UINT f_GRj; + + f_FCCi_2 = EXTRACT_LSB0_UINT (insn, 32, 26, 2); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_FCCi_2) = f_FCCi_2; + FLD (f_GRi) = f_GRi; + FLD (f_GRj) = f_GRj; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ftne", "f_FCCi_2 0x%x", 'x', f_FCCi_2, "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_FCCi_2) = f_FCCi_2; + FLD (in_GRi) = f_GRi; + FLD (in_GRj) = f_GRj; + FLD (out_h_spr_USI_1) = 1; + FLD (out_h_spr_USI_768) = 768; + FLD (out_h_spr_USI_769) = 769; + FLD (out_h_spr_USI_770) = 770; + FLD (out_h_spr_USI_771) = 771; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_tira: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_ftine.f + UINT f_GRi; + INT f_d12; + + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_d12 = EXTRACT_LSB0_INT (insn, 32, 11, 12); + + /* Record the fields for the semantic handler. */ + FLD (f_GRi) = f_GRi; + FLD (f_d12) = f_d12; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_tira", "f_GRi 0x%x", 'x', f_GRi, "f_d12 0x%x", 'x', f_d12, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_GRi) = f_GRi; + FLD (out_h_spr_USI_1) = 1; + FLD (out_h_spr_USI_768) = 768; + FLD (out_h_spr_USI_769) = 769; + FLD (out_h_spr_USI_770) = 770; + FLD (out_h_spr_USI_771) = 771; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_tieq: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_tieq.f + UINT f_ICCi_2; + UINT f_GRi; + INT f_d12; + + f_ICCi_2 = EXTRACT_LSB0_UINT (insn, 32, 26, 2); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_d12 = EXTRACT_LSB0_INT (insn, 32, 11, 12); + + /* Record the fields for the semantic handler. */ + FLD (f_GRi) = f_GRi; + FLD (f_ICCi_2) = f_ICCi_2; + FLD (f_d12) = f_d12; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_tieq", "f_GRi 0x%x", 'x', f_GRi, "f_ICCi_2 0x%x", 'x', f_ICCi_2, "f_d12 0x%x", 'x', f_d12, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_GRi) = f_GRi; + FLD (in_ICCi_2) = f_ICCi_2; + FLD (out_h_spr_USI_1) = 1; + FLD (out_h_spr_USI_768) = 768; + FLD (out_h_spr_USI_769) = 769; + FLD (out_h_spr_USI_770) = 770; + FLD (out_h_spr_USI_771) = 771; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_ftine: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_ftine.f + UINT f_FCCi_2; + UINT f_GRi; + INT f_d12; + + f_FCCi_2 = EXTRACT_LSB0_UINT (insn, 32, 26, 2); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_d12 = EXTRACT_LSB0_INT (insn, 32, 11, 12); + + /* Record the fields for the semantic handler. */ + FLD (f_FCCi_2) = f_FCCi_2; + FLD (f_GRi) = f_GRi; + FLD (f_d12) = f_d12; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ftine", "f_FCCi_2 0x%x", 'x', f_FCCi_2, "f_GRi 0x%x", 'x', f_GRi, "f_d12 0x%x", 'x', f_d12, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_FCCi_2) = f_FCCi_2; + FLD (in_GRi) = f_GRi; + FLD (out_h_spr_USI_1) = 1; + FLD (out_h_spr_USI_768) = 768; + FLD (out_h_spr_USI_769) = 769; + FLD (out_h_spr_USI_770) = 770; + FLD (out_h_spr_USI_771) = 771; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_break: + { + const IDESC *idesc = &frvbf_insn_data[itype]; +#define FLD(f) abuf->fields.sfmt_break.f + + + /* Record the fields for the semantic handler. */ + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_break", (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (out_h_spr_USI_2) = 2; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_andcr: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_andcr.f + UINT f_CRk; + UINT f_CRi; + UINT f_CRj; + + f_CRk = EXTRACT_LSB0_UINT (insn, 32, 27, 3); + f_CRi = EXTRACT_LSB0_UINT (insn, 32, 14, 3); + f_CRj = EXTRACT_LSB0_UINT (insn, 32, 2, 3); + + /* Record the fields for the semantic handler. */ + FLD (f_CRi) = f_CRi; + FLD (f_CRj) = f_CRj; + FLD (f_CRk) = f_CRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_andcr", "f_CRi 0x%x", 'x', f_CRi, "f_CRj 0x%x", 'x', f_CRj, "f_CRk 0x%x", 'x', f_CRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_CRi) = f_CRi; + FLD (in_CRj) = f_CRj; + FLD (out_CRk) = f_CRk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_notcr: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_andcr.f + UINT f_CRk; + UINT f_CRj; + + f_CRk = EXTRACT_LSB0_UINT (insn, 32, 27, 3); + f_CRj = EXTRACT_LSB0_UINT (insn, 32, 2, 3); + + /* Record the fields for the semantic handler. */ + FLD (f_CRj) = f_CRj; + FLD (f_CRk) = f_CRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_notcr", "f_CRj 0x%x", 'x', f_CRj, "f_CRk 0x%x", 'x', f_CRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_CRj) = f_CRj; + FLD (out_CRk) = f_CRk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_ckra: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cckeq.f + SI f_CRj_int; + + f_CRj_int = ((EXTRACT_LSB0_UINT (insn, 32, 26, 2)) + (4)); + + /* Record the fields for the semantic handler. */ + FLD (f_CRj_int) = f_CRj_int; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ckra", "f_CRj_int 0x%x", 'x', f_CRj_int, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (out_CRj_int) = f_CRj_int; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_ckeq: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cckeq.f + SI f_CRj_int; + UINT f_ICCi_3; + + f_CRj_int = ((EXTRACT_LSB0_UINT (insn, 32, 26, 2)) + (4)); + f_ICCi_3 = EXTRACT_LSB0_UINT (insn, 32, 1, 2); + + /* Record the fields for the semantic handler. */ + FLD (f_ICCi_3) = f_ICCi_3; + FLD (f_CRj_int) = f_CRj_int; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ckeq", "f_ICCi_3 0x%x", 'x', f_ICCi_3, "f_CRj_int 0x%x", 'x', f_CRj_int, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_ICCi_3) = f_ICCi_3; + FLD (out_CRj_int) = f_CRj_int; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_fckra: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cfckne.f + UINT f_CRj_float; + + f_CRj_float = EXTRACT_LSB0_UINT (insn, 32, 26, 2); + + /* Record the fields for the semantic handler. */ + FLD (f_CRj_float) = f_CRj_float; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fckra", "f_CRj_float 0x%x", 'x', f_CRj_float, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (out_CRj_float) = f_CRj_float; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_fckne: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cfckne.f + UINT f_CRj_float; + UINT f_FCCi_3; + + f_CRj_float = EXTRACT_LSB0_UINT (insn, 32, 26, 2); + f_FCCi_3 = EXTRACT_LSB0_UINT (insn, 32, 1, 2); + + /* Record the fields for the semantic handler. */ + FLD (f_FCCi_3) = f_FCCi_3; + FLD (f_CRj_float) = f_CRj_float; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fckne", "f_FCCi_3 0x%x", 'x', f_FCCi_3, "f_CRj_float 0x%x", 'x', f_CRj_float, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_FCCi_3) = f_FCCi_3; + FLD (out_CRj_float) = f_CRj_float; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_cckra: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cckeq.f + SI f_CRj_int; + UINT f_CCi; + UINT f_cond; + + f_CRj_int = ((EXTRACT_LSB0_UINT (insn, 32, 26, 2)) + (4)); + f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); + f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); + + /* Record the fields for the semantic handler. */ + FLD (f_CCi) = f_CCi; + FLD (f_cond) = f_cond; + FLD (f_CRj_int) = f_CRj_int; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cckra", "f_CCi 0x%x", 'x', f_CCi, "f_cond 0x%x", 'x', f_cond, "f_CRj_int 0x%x", 'x', f_CRj_int, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_CCi) = f_CCi; + FLD (out_CRj_int) = f_CRj_int; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_cckeq: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cckeq.f + SI f_CRj_int; + UINT f_CCi; + UINT f_cond; + UINT f_ICCi_3; + + f_CRj_int = ((EXTRACT_LSB0_UINT (insn, 32, 26, 2)) + (4)); + f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); + f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); + f_ICCi_3 = EXTRACT_LSB0_UINT (insn, 32, 1, 2); + + /* Record the fields for the semantic handler. */ + FLD (f_CCi) = f_CCi; + FLD (f_ICCi_3) = f_ICCi_3; + FLD (f_cond) = f_cond; + FLD (f_CRj_int) = f_CRj_int; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cckeq", "f_CCi 0x%x", 'x', f_CCi, "f_ICCi_3 0x%x", 'x', f_ICCi_3, "f_cond 0x%x", 'x', f_cond, "f_CRj_int 0x%x", 'x', f_CRj_int, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_CCi) = f_CCi; + FLD (in_ICCi_3) = f_ICCi_3; + FLD (out_CRj_int) = f_CRj_int; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_cfckra: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cfckne.f + UINT f_CRj_float; + UINT f_CCi; + UINT f_cond; + + f_CRj_float = EXTRACT_LSB0_UINT (insn, 32, 26, 2); + f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); + f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); + + /* Record the fields for the semantic handler. */ + FLD (f_CCi) = f_CCi; + FLD (f_cond) = f_cond; + FLD (f_CRj_float) = f_CRj_float; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cfckra", "f_CCi 0x%x", 'x', f_CCi, "f_cond 0x%x", 'x', f_cond, "f_CRj_float 0x%x", 'x', f_CRj_float, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_CCi) = f_CCi; + FLD (out_CRj_float) = f_CRj_float; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_cfckne: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cfckne.f + UINT f_CRj_float; + UINT f_CCi; + UINT f_cond; + UINT f_FCCi_3; + + f_CRj_float = EXTRACT_LSB0_UINT (insn, 32, 26, 2); + f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); + f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); + f_FCCi_3 = EXTRACT_LSB0_UINT (insn, 32, 1, 2); + + /* Record the fields for the semantic handler. */ + FLD (f_CCi) = f_CCi; + FLD (f_FCCi_3) = f_FCCi_3; + FLD (f_cond) = f_cond; + FLD (f_CRj_float) = f_CRj_float; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cfckne", "f_CCi 0x%x", 'x', f_CCi, "f_FCCi_3 0x%x", 'x', f_FCCi_3, "f_cond 0x%x", 'x', f_cond, "f_CRj_float 0x%x", 'x', f_CRj_float, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_CCi) = f_CCi; + FLD (in_FCCi_3) = f_FCCi_3; + FLD (out_CRj_float) = f_CRj_float; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_cjmpl: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cjmpl.f + UINT f_LI; + UINT f_GRi; + UINT f_CCi; + UINT f_cond; + UINT f_GRj; + + f_LI = EXTRACT_LSB0_UINT (insn, 32, 25, 1); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); + f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_CCi) = f_CCi; + FLD (f_GRi) = f_GRi; + FLD (f_GRj) = f_GRj; + FLD (f_LI) = f_LI; + FLD (f_cond) = f_cond; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cjmpl", "f_CCi 0x%x", 'x', f_CCi, "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_LI 0x%x", 'x', f_LI, "f_cond 0x%x", 'x', f_cond, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_CCi) = f_CCi; + FLD (in_GRi) = f_GRi; + FLD (in_GRj) = f_GRj; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_ici: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_icpl.f + UINT f_GRi; + UINT f_GRj; + + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_GRi) = f_GRi; + FLD (f_GRj) = f_GRj; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ici", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_GRi) = f_GRi; + FLD (in_GRj) = f_GRj; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_icei: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_icei.f + UINT f_ae; + UINT f_GRi; + UINT f_GRj; + + f_ae = EXTRACT_LSB0_UINT (insn, 32, 25, 1); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_GRi) = f_GRi; + FLD (f_GRj) = f_GRj; + FLD (f_ae) = f_ae; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_icei", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_ae 0x%x", 'x', f_ae, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_GRi) = f_GRi; + FLD (in_GRj) = f_GRj; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_icpl: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_icpl.f + UINT f_lock; + UINT f_GRi; + UINT f_GRj; + + f_lock = EXTRACT_LSB0_UINT (insn, 32, 25, 1); + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_GRi) = f_GRi; + FLD (f_GRj) = f_GRj; + FLD (f_lock) = f_lock; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_icpl", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_lock 0x%x", 'x', f_lock, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_GRi) = f_GRi; + FLD (in_GRj) = f_GRj; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_icul: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_jmpil.f + UINT f_GRi; + + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_GRi) = f_GRi; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_icul", "f_GRi 0x%x", 'x', f_GRi, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_GRi) = f_GRi; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_clrgr: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_swapi.f + UINT f_GRk; + + f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_GRk) = f_GRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_clrgr", "f_GRk 0x%x", 'x', f_GRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_GRk) = f_GRk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_clrfr: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cfmadds.f + UINT f_FRk; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_FRk) = f_FRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_clrfr", "f_FRk 0x%x", 'x', f_FRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_FRk) = f_FRk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_commitgr: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_setlos.f + UINT f_GRk; + + f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_GRk) = f_GRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_commitgr", "f_GRk 0x%x", 'x', f_GRk, (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_commitfr: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_mhsethis.f + UINT f_FRk; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_FRk) = f_FRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_commitfr", "f_FRk 0x%x", 'x', f_FRk, (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_fitos: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_fditos.f + UINT f_FRk; + UINT f_FRj; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_FRj) = f_FRj; + FLD (f_FRk) = f_FRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fitos", "f_FRj 0x%x", 'x', f_FRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_FRintj) = f_FRj; + FLD (out_FRk) = f_FRk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_fstoi: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_fdstoi.f + UINT f_FRk; + UINT f_FRj; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_FRj) = f_FRj; + FLD (f_FRk) = f_FRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fstoi", "f_FRj 0x%x", 'x', f_FRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_FRj) = f_FRj; + FLD (out_FRintk) = f_FRk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_fitod: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_fitod.f + UINT f_FRk; + UINT f_FRj; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_FRj) = f_FRj; + FLD (f_FRk) = f_FRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fitod", "f_FRj 0x%x", 'x', f_FRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_FRintj) = f_FRj; + FLD (out_FRdoublek) = f_FRk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_fdtoi: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_fdtoi.f + UINT f_FRk; + UINT f_FRj; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_FRj) = f_FRj; + FLD (f_FRk) = f_FRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fdtoi", "f_FRj 0x%x", 'x', f_FRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_FRdoublej) = f_FRj; + FLD (out_FRintk) = f_FRk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_fditos: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_fditos.f + UINT f_FRk; + UINT f_FRj; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_FRj) = f_FRj; + FLD (f_FRk) = f_FRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fditos", "f_FRj 0x%x", 'x', f_FRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_FRintj) = f_FRj; + FLD (in_h_fr_int_USI_add__DFLT_index_of__DFLT_FRintj_1) = ((FLD (f_FRj)) + (1)); + FLD (out_FRk) = f_FRk; + FLD (out_h_fr_SF_add__DFLT_index_of__DFLT_FRk_1) = ((FLD (f_FRk)) + (1)); + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_fdstoi: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_fdstoi.f + UINT f_FRk; + UINT f_FRj; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_FRj) = f_FRj; + FLD (f_FRk) = f_FRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fdstoi", "f_FRj 0x%x", 'x', f_FRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_FRj) = f_FRj; + FLD (in_h_fr_SF_add__DFLT_index_of__DFLT_FRj_1) = ((FLD (f_FRj)) + (1)); + FLD (out_FRintk) = f_FRk; + FLD (out_h_fr_int_USI_add__DFLT_index_of__DFLT_FRintk_1) = ((FLD (f_FRk)) + (1)); + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_cfitos: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cfitos.f + UINT f_FRk; + UINT f_CCi; + UINT f_cond; + UINT f_FRj; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); + f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_CCi) = f_CCi; + FLD (f_FRj) = f_FRj; + FLD (f_cond) = f_cond; + FLD (f_FRk) = f_FRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cfitos", "f_CCi 0x%x", 'x', f_CCi, "f_FRj 0x%x", 'x', f_FRj, "f_cond 0x%x", 'x', f_cond, "f_FRk 0x%x", 'x', f_FRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_CCi) = f_CCi; + FLD (in_FRintj) = f_FRj; + FLD (out_FRk) = f_FRk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_cfstoi: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cfstoi.f + UINT f_FRk; + UINT f_CCi; + UINT f_cond; + UINT f_FRj; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); + f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_CCi) = f_CCi; + FLD (f_FRj) = f_FRj; + FLD (f_cond) = f_cond; + FLD (f_FRk) = f_FRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cfstoi", "f_CCi 0x%x", 'x', f_CCi, "f_FRj 0x%x", 'x', f_FRj, "f_cond 0x%x", 'x', f_cond, "f_FRk 0x%x", 'x', f_FRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_CCi) = f_CCi; + FLD (in_FRj) = f_FRj; + FLD (out_FRintk) = f_FRk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_nfitos: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_fditos.f + UINT f_FRk; + UINT f_FRj; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_FRj) = f_FRj; + FLD (f_FRk) = f_FRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_nfitos", "f_FRj 0x%x", 'x', f_FRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_FRintj) = f_FRj; + FLD (out_FRk) = f_FRk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_nfstoi: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_fdstoi.f + UINT f_FRk; + UINT f_FRj; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_FRj) = f_FRj; + FLD (f_FRk) = f_FRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_nfstoi", "f_FRj 0x%x", 'x', f_FRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_FRj) = f_FRj; + FLD (out_FRintk) = f_FRk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_fmovs: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cfmadds.f + UINT f_FRk; + UINT f_FRj; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_FRj) = f_FRj; + FLD (f_FRk) = f_FRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fmovs", "f_FRj 0x%x", 'x', f_FRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_FRj) = f_FRj; + FLD (out_FRk) = f_FRk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_fmovd: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_fmaddd.f + UINT f_FRk; + UINT f_FRj; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_FRj) = f_FRj; + FLD (f_FRk) = f_FRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fmovd", "f_FRj 0x%x", 'x', f_FRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_FRdoublej) = f_FRj; + FLD (out_FRdoublek) = f_FRk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_fdmovs: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_fdmadds.f + UINT f_FRk; + UINT f_FRj; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_FRj) = f_FRj; + FLD (f_FRk) = f_FRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fdmovs", "f_FRj 0x%x", 'x', f_FRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_FRj) = f_FRj; + FLD (in_h_fr_SF_add__DFLT_index_of__DFLT_FRj_1) = ((FLD (f_FRj)) + (1)); + FLD (out_FRk) = f_FRk; + FLD (out_h_fr_SF_add__DFLT_index_of__DFLT_FRk_1) = ((FLD (f_FRk)) + (1)); + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_cfmovs: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cfmadds.f + UINT f_FRk; + UINT f_CCi; + UINT f_cond; + UINT f_FRj; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); + f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_CCi) = f_CCi; + FLD (f_FRj) = f_FRj; + FLD (f_cond) = f_cond; + FLD (f_FRk) = f_FRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cfmovs", "f_CCi 0x%x", 'x', f_CCi, "f_FRj 0x%x", 'x', f_FRj, "f_cond 0x%x", 'x', f_cond, "f_FRk 0x%x", 'x', f_FRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_CCi) = f_CCi; + FLD (in_FRj) = f_FRj; + FLD (out_FRk) = f_FRk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_nfsqrts: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cfmadds.f + UINT f_FRk; + UINT f_FRj; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_FRj) = f_FRj; + FLD (f_FRk) = f_FRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_nfsqrts", "f_FRj 0x%x", 'x', f_FRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_FRj) = f_FRj; + FLD (out_FRk) = f_FRk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_fadds: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cfmadds.f + UINT f_FRk; + UINT f_FRi; + UINT f_FRj; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_FRi) = f_FRi; + FLD (f_FRj) = f_FRj; + FLD (f_FRk) = f_FRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fadds", "f_FRi 0x%x", 'x', f_FRi, "f_FRj 0x%x", 'x', f_FRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_FRi) = f_FRi; + FLD (in_FRj) = f_FRj; + FLD (out_FRk) = f_FRk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_faddd: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_fmaddd.f + UINT f_FRk; + UINT f_FRi; + UINT f_FRj; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_FRi) = f_FRi; + FLD (f_FRj) = f_FRj; + FLD (f_FRk) = f_FRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_faddd", "f_FRi 0x%x", 'x', f_FRi, "f_FRj 0x%x", 'x', f_FRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_FRdoublei) = f_FRi; + FLD (in_FRdoublej) = f_FRj; + FLD (out_FRdoublek) = f_FRk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_cfadds: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cfmadds.f + UINT f_FRk; + UINT f_FRi; + UINT f_CCi; + UINT f_cond; + UINT f_FRj; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); + f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_CCi) = f_CCi; + FLD (f_FRi) = f_FRi; + FLD (f_FRj) = f_FRj; + FLD (f_cond) = f_cond; + FLD (f_FRk) = f_FRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cfadds", "f_CCi 0x%x", 'x', f_CCi, "f_FRi 0x%x", 'x', f_FRi, "f_FRj 0x%x", 'x', f_FRj, "f_cond 0x%x", 'x', f_cond, "f_FRk 0x%x", 'x', f_FRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_CCi) = f_CCi; + FLD (in_FRi) = f_FRi; + FLD (in_FRj) = f_FRj; + FLD (out_FRk) = f_FRk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_nfadds: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cfmadds.f + UINT f_FRk; + UINT f_FRi; + UINT f_FRj; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_FRi) = f_FRi; + FLD (f_FRj) = f_FRj; + FLD (f_FRk) = f_FRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_nfadds", "f_FRi 0x%x", 'x', f_FRi, "f_FRj 0x%x", 'x', f_FRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_FRi) = f_FRi; + FLD (in_FRj) = f_FRj; + FLD (out_FRk) = f_FRk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_fcmps: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cfcmps.f + UINT f_FCCi_2; + UINT f_FRi; + UINT f_FRj; + + f_FCCi_2 = EXTRACT_LSB0_UINT (insn, 32, 26, 2); + f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_FRi) = f_FRi; + FLD (f_FRj) = f_FRj; + FLD (f_FCCi_2) = f_FCCi_2; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fcmps", "f_FRi 0x%x", 'x', f_FRi, "f_FRj 0x%x", 'x', f_FRj, "f_FCCi_2 0x%x", 'x', f_FCCi_2, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_FRi) = f_FRi; + FLD (in_FRj) = f_FRj; + FLD (out_FCCi_2) = f_FCCi_2; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_fcmpd: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_fcmpd.f + UINT f_FCCi_2; + UINT f_FRi; + UINT f_FRj; + + f_FCCi_2 = EXTRACT_LSB0_UINT (insn, 32, 26, 2); + f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_FRi) = f_FRi; + FLD (f_FRj) = f_FRj; + FLD (f_FCCi_2) = f_FCCi_2; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fcmpd", "f_FRi 0x%x", 'x', f_FRi, "f_FRj 0x%x", 'x', f_FRj, "f_FCCi_2 0x%x", 'x', f_FCCi_2, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_FRdoublei) = f_FRi; + FLD (in_FRdoublej) = f_FRj; + FLD (out_FCCi_2) = f_FCCi_2; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_cfcmps: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cfcmps.f + UINT f_FCCi_2; + UINT f_FRi; + UINT f_CCi; + UINT f_cond; + UINT f_FRj; + + f_FCCi_2 = EXTRACT_LSB0_UINT (insn, 32, 26, 2); + f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); + f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_CCi) = f_CCi; + FLD (f_FRi) = f_FRi; + FLD (f_FRj) = f_FRj; + FLD (f_cond) = f_cond; + FLD (f_FCCi_2) = f_FCCi_2; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cfcmps", "f_CCi 0x%x", 'x', f_CCi, "f_FRi 0x%x", 'x', f_FRi, "f_FRj 0x%x", 'x', f_FRj, "f_cond 0x%x", 'x', f_cond, "f_FCCi_2 0x%x", 'x', f_FCCi_2, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_CCi) = f_CCi; + FLD (in_FRi) = f_FRi; + FLD (in_FRj) = f_FRj; + FLD (out_FCCi_2) = f_FCCi_2; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_fdcmps: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_nfdcmps.f + UINT f_FCCi_2; + UINT f_FRi; + UINT f_FRj; + + f_FCCi_2 = EXTRACT_LSB0_UINT (insn, 32, 26, 2); + f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_FRi) = f_FRi; + FLD (f_FRj) = f_FRj; + FLD (f_FCCi_2) = f_FCCi_2; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fdcmps", "f_FRi 0x%x", 'x', f_FRi, "f_FRj 0x%x", 'x', f_FRj, "f_FCCi_2 0x%x", 'x', f_FCCi_2, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_FRi) = f_FRi; + FLD (in_FRj) = f_FRj; + FLD (in_h_fr_SF_add__DFLT_index_of__DFLT_FRi_1) = ((FLD (f_FRi)) + (1)); + FLD (in_h_fr_SF_add__DFLT_index_of__DFLT_FRj_1) = ((FLD (f_FRj)) + (1)); + FLD (out_FCCi_2) = f_FCCi_2; + FLD (out_h_fccr_UQI_add__DFLT_index_of__DFLT_FCCi_2_1) = ((FLD (f_FCCi_2)) + (1)); + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_fmadds: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cfmadds.f + UINT f_FRk; + UINT f_FRi; + UINT f_FRj; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_FRi) = f_FRi; + FLD (f_FRj) = f_FRj; + FLD (f_FRk) = f_FRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fmadds", "f_FRi 0x%x", 'x', f_FRi, "f_FRj 0x%x", 'x', f_FRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_FRi) = f_FRi; + FLD (in_FRj) = f_FRj; + FLD (in_FRk) = f_FRk; + FLD (out_FRk) = f_FRk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_fmaddd: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_fmaddd.f + UINT f_FRk; + UINT f_FRi; + UINT f_FRj; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_FRi) = f_FRi; + FLD (f_FRj) = f_FRj; + FLD (f_FRk) = f_FRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fmaddd", "f_FRi 0x%x", 'x', f_FRi, "f_FRj 0x%x", 'x', f_FRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_FRdoublei) = f_FRi; + FLD (in_FRdoublej) = f_FRj; + FLD (in_FRdoublek) = f_FRk; + FLD (out_FRdoublek) = f_FRk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_fdmadds: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_fdmadds.f + UINT f_FRk; + UINT f_FRi; + UINT f_FRj; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_FRi) = f_FRi; + FLD (f_FRj) = f_FRj; + FLD (f_FRk) = f_FRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fdmadds", "f_FRi 0x%x", 'x', f_FRi, "f_FRj 0x%x", 'x', f_FRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_FRi) = f_FRi; + FLD (in_FRj) = f_FRj; + FLD (in_FRk) = f_FRk; + FLD (in_h_fr_SF_add__DFLT_index_of__DFLT_FRi_1) = ((FLD (f_FRi)) + (1)); + FLD (in_h_fr_SF_add__DFLT_index_of__DFLT_FRj_1) = ((FLD (f_FRj)) + (1)); + FLD (in_h_fr_SF_add__DFLT_index_of__DFLT_FRk_1) = ((FLD (f_FRk)) + (1)); + FLD (out_FRk) = f_FRk; + FLD (out_h_fr_SF_add__DFLT_index_of__DFLT_FRk_1) = ((FLD (f_FRk)) + (1)); + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_cfmadds: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cfmadds.f + UINT f_FRk; + UINT f_FRi; + UINT f_CCi; + UINT f_cond; + UINT f_FRj; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); + f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_CCi) = f_CCi; + FLD (f_FRi) = f_FRi; + FLD (f_FRj) = f_FRj; + FLD (f_FRk) = f_FRk; + FLD (f_cond) = f_cond; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cfmadds", "f_CCi 0x%x", 'x', f_CCi, "f_FRi 0x%x", 'x', f_FRi, "f_FRj 0x%x", 'x', f_FRj, "f_FRk 0x%x", 'x', f_FRk, "f_cond 0x%x", 'x', f_cond, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_CCi) = f_CCi; + FLD (in_FRi) = f_FRi; + FLD (in_FRj) = f_FRj; + FLD (in_FRk) = f_FRk; + FLD (out_FRk) = f_FRk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_nfmadds: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cfmadds.f + UINT f_FRk; + UINT f_FRi; + UINT f_FRj; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_FRi) = f_FRi; + FLD (f_FRj) = f_FRj; + FLD (f_FRk) = f_FRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_nfmadds", "f_FRi 0x%x", 'x', f_FRi, "f_FRj 0x%x", 'x', f_FRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_FRi) = f_FRi; + FLD (in_FRj) = f_FRj; + FLD (in_FRk) = f_FRk; + FLD (out_FRk) = f_FRk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_fmas: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_fdmadds.f + UINT f_FRk; + UINT f_FRi; + UINT f_FRj; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_FRi) = f_FRi; + FLD (f_FRj) = f_FRj; + FLD (f_FRk) = f_FRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fmas", "f_FRi 0x%x", 'x', f_FRi, "f_FRj 0x%x", 'x', f_FRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_FRi) = f_FRi; + FLD (in_FRj) = f_FRj; + FLD (in_h_fr_SF_add__DFLT_index_of__DFLT_FRi_1) = ((FLD (f_FRi)) + (1)); + FLD (in_h_fr_SF_add__DFLT_index_of__DFLT_FRj_1) = ((FLD (f_FRj)) + (1)); + FLD (out_FRk) = f_FRk; + FLD (out_h_fr_SF_add__DFLT_index_of__DFLT_FRk_1) = ((FLD (f_FRk)) + (1)); + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_fdmas: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_fdmas.f + UINT f_FRk; + UINT f_FRi; + UINT f_FRj; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_FRi) = f_FRi; + FLD (f_FRj) = f_FRj; + FLD (f_FRk) = f_FRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fdmas", "f_FRi 0x%x", 'x', f_FRi, "f_FRj 0x%x", 'x', f_FRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_FRi) = f_FRi; + FLD (in_FRj) = f_FRj; + FLD (in_h_fr_SF_add__DFLT_index_of__DFLT_FRi_1) = ((FLD (f_FRi)) + (1)); + FLD (in_h_fr_SF_add__DFLT_index_of__DFLT_FRi_2) = ((FLD (f_FRi)) + (2)); + FLD (in_h_fr_SF_add__DFLT_index_of__DFLT_FRi_3) = ((FLD (f_FRi)) + (3)); + FLD (in_h_fr_SF_add__DFLT_index_of__DFLT_FRj_1) = ((FLD (f_FRj)) + (1)); + FLD (in_h_fr_SF_add__DFLT_index_of__DFLT_FRj_2) = ((FLD (f_FRj)) + (2)); + FLD (in_h_fr_SF_add__DFLT_index_of__DFLT_FRj_3) = ((FLD (f_FRj)) + (3)); + FLD (out_FRk) = f_FRk; + FLD (out_h_fr_SF_add__DFLT_index_of__DFLT_FRk_1) = ((FLD (f_FRk)) + (1)); + FLD (out_h_fr_SF_add__DFLT_index_of__DFLT_FRk_2) = ((FLD (f_FRk)) + (2)); + FLD (out_h_fr_SF_add__DFLT_index_of__DFLT_FRk_3) = ((FLD (f_FRk)) + (3)); + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_cfmas: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cfmas.f + UINT f_FRk; + UINT f_FRi; + UINT f_CCi; + UINT f_cond; + UINT f_FRj; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); + f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_CCi) = f_CCi; + FLD (f_FRi) = f_FRi; + FLD (f_FRj) = f_FRj; + FLD (f_cond) = f_cond; + FLD (f_FRk) = f_FRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cfmas", "f_CCi 0x%x", 'x', f_CCi, "f_FRi 0x%x", 'x', f_FRi, "f_FRj 0x%x", 'x', f_FRj, "f_cond 0x%x", 'x', f_cond, "f_FRk 0x%x", 'x', f_FRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_CCi) = f_CCi; + FLD (in_FRi) = f_FRi; + FLD (in_FRj) = f_FRj; + FLD (in_h_fr_SF_add__DFLT_index_of__DFLT_FRi_1) = ((FLD (f_FRi)) + (1)); + FLD (in_h_fr_SF_add__DFLT_index_of__DFLT_FRj_1) = ((FLD (f_FRj)) + (1)); + FLD (out_FRk) = f_FRk; + FLD (out_h_fr_SF_add__DFLT_index_of__DFLT_FRk_1) = ((FLD (f_FRk)) + (1)); + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_nfdcmps: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_nfdcmps.f + UINT f_FRk; + UINT f_FCCi_2; + UINT f_FRi; + UINT f_FRj; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_FCCi_2 = EXTRACT_LSB0_UINT (insn, 32, 26, 2); + f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_FRi) = f_FRi; + FLD (f_FRj) = f_FRj; + FLD (f_FCCi_2) = f_FCCi_2; + FLD (f_FRk) = f_FRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_nfdcmps", "f_FRi 0x%x", 'x', f_FRi, "f_FRj 0x%x", 'x', f_FRj, "f_FCCi_2 0x%x", 'x', f_FCCi_2, "f_FRk 0x%x", 'x', f_FRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_FRi) = f_FRi; + FLD (in_FRj) = f_FRj; + FLD (in_h_fr_SF_add__DFLT_index_of__DFLT_FRi_1) = ((FLD (f_FRi)) + (1)); + FLD (in_h_fr_SF_add__DFLT_index_of__DFLT_FRj_1) = ((FLD (f_FRj)) + (1)); + FLD (out_FCCi_2) = f_FCCi_2; + FLD (out_h_fccr_UQI_add__DFLT_index_of__DFLT_FCCi_2_1) = ((FLD (f_FCCi_2)) + (1)); + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_mhsetlos: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_mhsetlos.f + UINT f_FRk; + INT f_u12_h; + UINT f_u12_l; + INT f_u12; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_u12_h = EXTRACT_LSB0_INT (insn, 32, 17, 6); + f_u12_l = EXTRACT_LSB0_UINT (insn, 32, 5, 6); +{ + f_u12 = ((((f_u12_h) << (6))) | (f_u12_l)); +} + + /* Record the fields for the semantic handler. */ + FLD (f_u12) = f_u12; + FLD (f_FRk) = f_FRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mhsetlos", "f_u12 0x%x", 'x', f_u12, "f_FRk 0x%x", 'x', f_FRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (out_FRklo) = f_FRk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_mhsethis: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_mhsethis.f + UINT f_FRk; + INT f_u12_h; + UINT f_u12_l; + INT f_u12; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_u12_h = EXTRACT_LSB0_INT (insn, 32, 17, 6); + f_u12_l = EXTRACT_LSB0_UINT (insn, 32, 5, 6); +{ + f_u12 = ((((f_u12_h) << (6))) | (f_u12_l)); +} + + /* Record the fields for the semantic handler. */ + FLD (f_u12) = f_u12; + FLD (f_FRk) = f_FRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mhsethis", "f_u12 0x%x", 'x', f_u12, "f_FRk 0x%x", 'x', f_FRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (out_FRkhi) = f_FRk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_mhdsets: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_mhdsets.f + UINT f_FRk; + INT f_u12_h; + UINT f_u12_l; + INT f_u12; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_u12_h = EXTRACT_LSB0_INT (insn, 32, 17, 6); + f_u12_l = EXTRACT_LSB0_UINT (insn, 32, 5, 6); +{ + f_u12 = ((((f_u12_h) << (6))) | (f_u12_l)); +} + + /* Record the fields for the semantic handler. */ + FLD (f_FRk) = f_FRk; + FLD (f_u12) = f_u12; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mhdsets", "f_FRk 0x%x", 'x', f_FRk, "f_u12 0x%x", 'x', f_u12, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_FRintk) = f_FRk; + FLD (out_FRintk) = f_FRk; + FLD (out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintk_0) = ((FLD (f_FRk)) + (0)); + FLD (out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintk_0) = ((FLD (f_FRk)) + (0)); + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_mhsetloh: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_mhsetloh.f + UINT f_FRk; + INT f_s5; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_s5 = EXTRACT_LSB0_INT (insn, 32, 4, 5); + + /* Record the fields for the semantic handler. */ + FLD (f_FRk) = f_FRk; + FLD (f_s5) = f_s5; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mhsetloh", "f_FRk 0x%x", 'x', f_FRk, "f_s5 0x%x", 'x', f_s5, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_FRklo) = f_FRk; + FLD (out_FRklo) = f_FRk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_mhsethih: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_mhsethih.f + UINT f_FRk; + INT f_s5; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_s5 = EXTRACT_LSB0_INT (insn, 32, 4, 5); + + /* Record the fields for the semantic handler. */ + FLD (f_FRk) = f_FRk; + FLD (f_s5) = f_s5; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mhsethih", "f_FRk 0x%x", 'x', f_FRk, "f_s5 0x%x", 'x', f_s5, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_FRkhi) = f_FRk; + FLD (out_FRkhi) = f_FRk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_mhdseth: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_mhdseth.f + UINT f_FRk; + INT f_s5; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_s5 = EXTRACT_LSB0_INT (insn, 32, 4, 5); + + /* Record the fields for the semantic handler. */ + FLD (f_FRk) = f_FRk; + FLD (f_s5) = f_s5; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mhdseth", "f_FRk 0x%x", 'x', f_FRk, "f_s5 0x%x", 'x', f_s5, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_FRintk) = f_FRk; + FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintk_0) = ((FLD (f_FRk)) + (0)); + FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintk_0) = ((FLD (f_FRk)) + (0)); + FLD (out_FRintk) = f_FRk; + FLD (out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintk_0) = ((FLD (f_FRk)) + (0)); + FLD (out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintk_0) = ((FLD (f_FRk)) + (0)); + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_mand: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_mwcut.f + UINT f_FRk; + UINT f_FRi; + UINT f_FRj; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_FRi) = f_FRi; + FLD (f_FRj) = f_FRj; + FLD (f_FRk) = f_FRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mand", "f_FRi 0x%x", 'x', f_FRi, "f_FRj 0x%x", 'x', f_FRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_FRinti) = f_FRi; + FLD (in_FRintj) = f_FRj; + FLD (out_FRintk) = f_FRk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_cmand: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cmand.f + UINT f_FRk; + UINT f_FRi; + UINT f_CCi; + UINT f_cond; + UINT f_FRj; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); + f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_CCi) = f_CCi; + FLD (f_FRi) = f_FRi; + FLD (f_FRj) = f_FRj; + FLD (f_cond) = f_cond; + FLD (f_FRk) = f_FRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmand", "f_CCi 0x%x", 'x', f_CCi, "f_FRi 0x%x", 'x', f_FRi, "f_FRj 0x%x", 'x', f_FRj, "f_cond 0x%x", 'x', f_cond, "f_FRk 0x%x", 'x', f_FRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_CCi) = f_CCi; + FLD (in_FRinti) = f_FRi; + FLD (in_FRintj) = f_FRj; + FLD (out_FRintk) = f_FRk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_mnot: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_mcut.f + UINT f_FRk; + UINT f_FRj; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_FRj) = f_FRj; + FLD (f_FRk) = f_FRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mnot", "f_FRj 0x%x", 'x', f_FRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_FRintj) = f_FRj; + FLD (out_FRintk) = f_FRk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_cmnot: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cmand.f + UINT f_FRk; + UINT f_CCi; + UINT f_cond; + UINT f_FRj; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); + f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_CCi) = f_CCi; + FLD (f_FRj) = f_FRj; + FLD (f_cond) = f_cond; + FLD (f_FRk) = f_FRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmnot", "f_CCi 0x%x", 'x', f_CCi, "f_FRj 0x%x", 'x', f_FRj, "f_cond 0x%x", 'x', f_cond, "f_FRk 0x%x", 'x', f_FRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_CCi) = f_CCi; + FLD (in_FRintj) = f_FRj; + FLD (out_FRintk) = f_FRk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_mrotli: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_mwcuti.f + UINT f_FRk; + UINT f_FRi; + UINT f_u6; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_u6 = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_FRi) = f_FRi; + FLD (f_u6) = f_u6; + FLD (f_FRk) = f_FRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mrotli", "f_FRi 0x%x", 'x', f_FRi, "f_u6 0x%x", 'x', f_u6, "f_FRk 0x%x", 'x', f_FRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_FRinti) = f_FRi; + FLD (out_FRintk) = f_FRk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_mwcut: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_mwcut.f + UINT f_FRk; + UINT f_FRi; + UINT f_FRj; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_FRi) = f_FRi; + FLD (f_FRj) = f_FRj; + FLD (f_FRk) = f_FRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mwcut", "f_FRi 0x%x", 'x', f_FRi, "f_FRj 0x%x", 'x', f_FRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_FRinti) = f_FRi; + FLD (in_FRintj) = f_FRj; + FLD (in_h_fr_int_USI_add__DFLT_index_of__DFLT_FRinti_1) = ((FLD (f_FRi)) + (1)); + FLD (out_FRintk) = f_FRk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_mwcuti: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_mwcuti.f + UINT f_FRk; + UINT f_FRi; + UINT f_u6; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_u6 = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_FRi) = f_FRi; + FLD (f_u6) = f_u6; + FLD (f_FRk) = f_FRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mwcuti", "f_FRi 0x%x", 'x', f_FRi, "f_u6 0x%x", 'x', f_u6, "f_FRk 0x%x", 'x', f_FRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_FRinti) = f_FRi; + FLD (in_h_fr_int_USI_add__DFLT_index_of__DFLT_FRinti_1) = ((FLD (f_FRi)) + (1)); + FLD (out_FRintk) = f_FRk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_mcut: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_mcut.f + UINT f_FRk; + UINT f_ACC40Si; + UINT f_FRj; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_ACC40Si = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_ACC40Si) = f_ACC40Si; + FLD (f_FRj) = f_FRj; + FLD (f_FRk) = f_FRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mcut", "f_ACC40Si 0x%x", 'x', f_ACC40Si, "f_FRj 0x%x", 'x', f_FRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_ACC40Si) = f_ACC40Si; + FLD (in_FRintj) = f_FRj; + FLD (out_FRintk) = f_FRk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_mcuti: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_mcuti.f + UINT f_FRk; + UINT f_ACC40Si; + INT f_s6; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_ACC40Si = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_s6 = EXTRACT_LSB0_INT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_ACC40Si) = f_ACC40Si; + FLD (f_s6) = f_s6; + FLD (f_FRk) = f_FRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mcuti", "f_ACC40Si 0x%x", 'x', f_ACC40Si, "f_s6 0x%x", 'x', f_s6, "f_FRk 0x%x", 'x', f_FRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_ACC40Si) = f_ACC40Si; + FLD (out_FRintk) = f_FRk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_mdcutssi: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_mdcutssi.f + UINT f_FRk; + UINT f_ACC40Si; + INT f_s6; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_ACC40Si = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_s6 = EXTRACT_LSB0_INT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_ACC40Si) = f_ACC40Si; + FLD (f_FRk) = f_FRk; + FLD (f_s6) = f_s6; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mdcutssi", "f_ACC40Si 0x%x", 'x', f_ACC40Si, "f_FRk 0x%x", 'x', f_FRk, "f_s6 0x%x", 'x', f_s6, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_ACC40Si) = f_ACC40Si; + FLD (in_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Si_1) = ((FLD (f_ACC40Si)) + (1)); + FLD (out_FRintkeven) = f_FRk; + FLD (out_h_fr_int_USI_add__DFLT_index_of__DFLT_FRintkeven_1) = ((FLD (f_FRk)) + (1)); + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_msllhi: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_msllhi.f + UINT f_FRk; + UINT f_FRi; + UINT f_u6; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_u6 = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_FRi) = f_FRi; + FLD (f_FRk) = f_FRk; + FLD (f_u6) = f_u6; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_msllhi", "f_FRi 0x%x", 'x', f_FRi, "f_FRk 0x%x", 'x', f_FRk, "f_u6 0x%x", 'x', f_u6, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_FRinti) = f_FRi; + FLD (in_FRintk) = f_FRk; + FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRinti_0) = ((FLD (f_FRi)) + (0)); + FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRinti_0) = ((FLD (f_FRi)) + (0)); + FLD (out_FRinti) = f_FRi; + FLD (out_FRintk) = f_FRk; + FLD (out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintk_0) = ((FLD (f_FRk)) + (0)); + FLD (out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintk_0) = ((FLD (f_FRk)) + (0)); + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_mdrotli: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_mdrotli.f + UINT f_FRk; + UINT f_FRi; + INT f_s6; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_s6 = EXTRACT_LSB0_INT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_FRi) = f_FRi; + FLD (f_FRk) = f_FRk; + FLD (f_s6) = f_s6; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mdrotli", "f_FRi 0x%x", 'x', f_FRi, "f_FRk 0x%x", 'x', f_FRk, "f_s6 0x%x", 'x', f_s6, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_FRintieven) = f_FRi; + FLD (in_h_fr_int_USI_add__DFLT_index_of__DFLT_FRintieven_1) = ((FLD (f_FRi)) + (1)); + FLD (out_FRintkeven) = f_FRk; + FLD (out_h_fr_int_USI_add__DFLT_index_of__DFLT_FRintkeven_1) = ((FLD (f_FRk)) + (1)); + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_mcplhi: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_mcplhi.f + UINT f_FRk; + UINT f_FRi; + UINT f_u6; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_u6 = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_FRi) = f_FRi; + FLD (f_FRk) = f_FRk; + FLD (f_u6) = f_u6; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mcplhi", "f_FRi 0x%x", 'x', f_FRi, "f_FRk 0x%x", 'x', f_FRk, "f_u6 0x%x", 'x', f_u6, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_FRinti) = f_FRi; + FLD (in_FRintk) = f_FRk; + FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRinti_0) = ((FLD (f_FRi)) + (0)); + FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRinti_1) = ((FLD (f_FRi)) + (1)); + FLD (out_FRinti) = f_FRi; + FLD (out_FRintk) = f_FRk; + FLD (out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintk_0) = ((FLD (f_FRk)) + (0)); + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_mcpli: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_mwcuti.f + UINT f_FRk; + UINT f_FRi; + UINT f_u6; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_u6 = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_FRi) = f_FRi; + FLD (f_u6) = f_u6; + FLD (f_FRk) = f_FRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mcpli", "f_FRi 0x%x", 'x', f_FRi, "f_u6 0x%x", 'x', f_u6, "f_FRk 0x%x", 'x', f_FRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_FRinti) = f_FRi; + FLD (in_h_fr_int_USI_add__DFLT_index_of__DFLT_FRinti_1) = ((FLD (f_FRi)) + (1)); + FLD (out_FRintk) = f_FRk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_msaths: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + UINT f_FRk; + UINT f_FRi; + UINT f_FRj; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_FRi) = f_FRi; + FLD (f_FRj) = f_FRj; + FLD (f_FRk) = f_FRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_msaths", "f_FRi 0x%x", 'x', f_FRi, "f_FRj 0x%x", 'x', f_FRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_FRinti) = f_FRi; + FLD (in_FRintj) = f_FRj; + FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRinti_0) = ((FLD (f_FRi)) + (0)); + FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintj_0) = ((FLD (f_FRj)) + (0)); + FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRinti_0) = ((FLD (f_FRi)) + (0)); + FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintj_0) = ((FLD (f_FRj)) + (0)); + FLD (out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintk_0) = ((FLD (f_FRk)) + (0)); + FLD (out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintk_0) = ((FLD (f_FRk)) + (0)); + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_mqsaths: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + UINT f_FRk; + UINT f_FRi; + UINT f_FRj; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_FRi) = f_FRi; + FLD (f_FRj) = f_FRj; + FLD (f_FRk) = f_FRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mqsaths", "f_FRi 0x%x", 'x', f_FRi, "f_FRj 0x%x", 'x', f_FRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_FRintieven) = f_FRi; + FLD (in_FRintjeven) = f_FRj; + FLD (in_FRintkeven) = f_FRk; + FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintieven_0) = ((FLD (f_FRi)) + (0)); + FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintieven_1) = ((FLD (f_FRi)) + (1)); + FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintjeven_0) = ((FLD (f_FRj)) + (0)); + FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintjeven_1) = ((FLD (f_FRj)) + (1)); + FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintieven_0) = ((FLD (f_FRi)) + (0)); + FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintieven_1) = ((FLD (f_FRi)) + (1)); + FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintjeven_0) = ((FLD (f_FRj)) + (0)); + FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintjeven_1) = ((FLD (f_FRj)) + (1)); + FLD (out_FRintkeven) = f_FRk; + FLD (out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintkeven_0) = ((FLD (f_FRk)) + (0)); + FLD (out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintkeven_1) = ((FLD (f_FRk)) + (1)); + FLD (out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintkeven_0) = ((FLD (f_FRk)) + (0)); + FLD (out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintkeven_1) = ((FLD (f_FRk)) + (1)); + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_mcmpsh: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_mcmpsh.f + UINT f_FCCk; + UINT f_FRi; + UINT f_FRj; + + f_FCCk = EXTRACT_LSB0_UINT (insn, 32, 26, 2); + f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_FRi) = f_FRi; + FLD (f_FRj) = f_FRj; + FLD (f_FCCk) = f_FCCk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mcmpsh", "f_FRi 0x%x", 'x', f_FRi, "f_FRj 0x%x", 'x', f_FRj, "f_FCCk 0x%x", 'x', f_FCCk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_FRinti) = f_FRi; + FLD (in_FRintj) = f_FRj; + FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRinti_0) = ((FLD (f_FRi)) + (0)); + FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintj_0) = ((FLD (f_FRj)) + (0)); + FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRinti_0) = ((FLD (f_FRi)) + (0)); + FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintj_0) = ((FLD (f_FRj)) + (0)); + FLD (out_FCCk) = f_FCCk; + FLD (out_h_fccr_UQI_add__DFLT_index_of__DFLT_FCCk_1) = ((FLD (f_FCCk)) + (1)); + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_mabshs: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_mabshs.f + UINT f_FRk; + UINT f_FRj; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_FRj) = f_FRj; + FLD (f_FRk) = f_FRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mabshs", "f_FRj 0x%x", 'x', f_FRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_FRintj) = f_FRj; + FLD (in_FRintk) = f_FRk; + FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintj_0) = ((FLD (f_FRj)) + (0)); + FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintj_0) = ((FLD (f_FRj)) + (0)); + FLD (out_FRintj) = f_FRj; + FLD (out_FRintk) = f_FRk; + FLD (out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintk_0) = ((FLD (f_FRk)) + (0)); + FLD (out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintk_0) = ((FLD (f_FRk)) + (0)); + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_cmaddhss: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + UINT f_FRk; + UINT f_FRi; + UINT f_CCi; + UINT f_cond; + UINT f_FRj; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); + f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_CCi) = f_CCi; + FLD (f_FRi) = f_FRi; + FLD (f_FRj) = f_FRj; + FLD (f_cond) = f_cond; + FLD (f_FRk) = f_FRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmaddhss", "f_CCi 0x%x", 'x', f_CCi, "f_FRi 0x%x", 'x', f_FRi, "f_FRj 0x%x", 'x', f_FRj, "f_cond 0x%x", 'x', f_cond, "f_FRk 0x%x", 'x', f_FRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_CCi) = f_CCi; + FLD (in_FRinti) = f_FRi; + FLD (in_FRintj) = f_FRj; + FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRinti_0) = ((FLD (f_FRi)) + (0)); + FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintj_0) = ((FLD (f_FRj)) + (0)); + FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRinti_0) = ((FLD (f_FRi)) + (0)); + FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintj_0) = ((FLD (f_FRj)) + (0)); + FLD (out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintk_0) = ((FLD (f_FRk)) + (0)); + FLD (out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintk_0) = ((FLD (f_FRk)) + (0)); + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_cmqaddhss: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + UINT f_FRk; + UINT f_FRi; + UINT f_CCi; + UINT f_cond; + UINT f_FRj; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); + f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_CCi) = f_CCi; + FLD (f_FRi) = f_FRi; + FLD (f_FRj) = f_FRj; + FLD (f_FRk) = f_FRk; + FLD (f_cond) = f_cond; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmqaddhss", "f_CCi 0x%x", 'x', f_CCi, "f_FRi 0x%x", 'x', f_FRi, "f_FRj 0x%x", 'x', f_FRj, "f_FRk 0x%x", 'x', f_FRk, "f_cond 0x%x", 'x', f_cond, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_CCi) = f_CCi; + FLD (in_FRintieven) = f_FRi; + FLD (in_FRintjeven) = f_FRj; + FLD (in_FRintkeven) = f_FRk; + FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintieven_0) = ((FLD (f_FRi)) + (0)); + FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintieven_1) = ((FLD (f_FRi)) + (1)); + FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintjeven_0) = ((FLD (f_FRj)) + (0)); + FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintjeven_1) = ((FLD (f_FRj)) + (1)); + FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintieven_0) = ((FLD (f_FRi)) + (0)); + FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintieven_1) = ((FLD (f_FRi)) + (1)); + FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintjeven_0) = ((FLD (f_FRj)) + (0)); + FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintjeven_1) = ((FLD (f_FRj)) + (1)); + FLD (out_FRintkeven) = f_FRk; + FLD (out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintkeven_0) = ((FLD (f_FRk)) + (0)); + FLD (out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintkeven_1) = ((FLD (f_FRk)) + (1)); + FLD (out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintkeven_0) = ((FLD (f_FRk)) + (0)); + FLD (out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintkeven_1) = ((FLD (f_FRk)) + (1)); + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_maddaccs: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_mdasaccs.f + UINT f_ACC40Sk; + UINT f_ACC40Si; + + f_ACC40Sk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_ACC40Si = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_ACC40Si) = f_ACC40Si; + FLD (f_ACC40Sk) = f_ACC40Sk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_maddaccs", "f_ACC40Si 0x%x", 'x', f_ACC40Si, "f_ACC40Sk 0x%x", 'x', f_ACC40Sk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_ACC40Si) = f_ACC40Si; + FLD (in_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Si_1) = ((FLD (f_ACC40Si)) + (1)); + FLD (out_ACC40Sk) = f_ACC40Sk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_mdaddaccs: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_mdasaccs.f + UINT f_ACC40Sk; + UINT f_ACC40Si; + + f_ACC40Sk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_ACC40Si = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_ACC40Si) = f_ACC40Si; + FLD (f_ACC40Sk) = f_ACC40Sk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mdaddaccs", "f_ACC40Si 0x%x", 'x', f_ACC40Si, "f_ACC40Sk 0x%x", 'x', f_ACC40Sk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_ACC40Si) = f_ACC40Si; + FLD (in_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Si_1) = ((FLD (f_ACC40Si)) + (1)); + FLD (in_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Si_2) = ((FLD (f_ACC40Si)) + (2)); + FLD (in_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Si_3) = ((FLD (f_ACC40Si)) + (3)); + FLD (out_ACC40Sk) = f_ACC40Sk; + FLD (out_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Sk_1) = ((FLD (f_ACC40Sk)) + (1)); + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_masaccs: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_mdasaccs.f + UINT f_ACC40Sk; + UINT f_ACC40Si; + + f_ACC40Sk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_ACC40Si = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_ACC40Si) = f_ACC40Si; + FLD (f_ACC40Sk) = f_ACC40Sk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_masaccs", "f_ACC40Si 0x%x", 'x', f_ACC40Si, "f_ACC40Sk 0x%x", 'x', f_ACC40Sk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_ACC40Si) = f_ACC40Si; + FLD (in_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Si_1) = ((FLD (f_ACC40Si)) + (1)); + FLD (out_ACC40Sk) = f_ACC40Sk; + FLD (out_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Sk_1) = ((FLD (f_ACC40Sk)) + (1)); + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_mdasaccs: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_mdasaccs.f + UINT f_ACC40Sk; + UINT f_ACC40Si; + + f_ACC40Sk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_ACC40Si = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_ACC40Si) = f_ACC40Si; + FLD (f_ACC40Sk) = f_ACC40Sk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mdasaccs", "f_ACC40Si 0x%x", 'x', f_ACC40Si, "f_ACC40Sk 0x%x", 'x', f_ACC40Sk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_ACC40Si) = f_ACC40Si; + FLD (in_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Si_1) = ((FLD (f_ACC40Si)) + (1)); + FLD (in_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Si_2) = ((FLD (f_ACC40Si)) + (2)); + FLD (in_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Si_3) = ((FLD (f_ACC40Si)) + (3)); + FLD (out_ACC40Sk) = f_ACC40Sk; + FLD (out_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Sk_1) = ((FLD (f_ACC40Sk)) + (1)); + FLD (out_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Sk_2) = ((FLD (f_ACC40Sk)) + (2)); + FLD (out_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Sk_3) = ((FLD (f_ACC40Sk)) + (3)); + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_mmulhs: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cmmachs.f + UINT f_ACC40Sk; + UINT f_FRi; + UINT f_FRj; + + f_ACC40Sk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_FRi) = f_FRi; + FLD (f_FRj) = f_FRj; + FLD (f_ACC40Sk) = f_ACC40Sk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mmulhs", "f_FRi 0x%x", 'x', f_FRi, "f_FRj 0x%x", 'x', f_FRj, "f_ACC40Sk 0x%x", 'x', f_ACC40Sk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_FRinti) = f_FRi; + FLD (in_FRintj) = f_FRj; + FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRinti_0) = ((FLD (f_FRi)) + (0)); + FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintj_0) = ((FLD (f_FRj)) + (0)); + FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRinti_0) = ((FLD (f_FRi)) + (0)); + FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintj_0) = ((FLD (f_FRj)) + (0)); + FLD (out_ACC40Sk) = f_ACC40Sk; + FLD (out_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Sk_1) = ((FLD (f_ACC40Sk)) + (1)); + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_cmmulhs: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cmmachs.f + UINT f_ACC40Sk; + UINT f_FRi; + UINT f_CCi; + UINT f_cond; + UINT f_FRj; + + f_ACC40Sk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); + f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_CCi) = f_CCi; + FLD (f_FRi) = f_FRi; + FLD (f_FRj) = f_FRj; + FLD (f_cond) = f_cond; + FLD (f_ACC40Sk) = f_ACC40Sk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmmulhs", "f_CCi 0x%x", 'x', f_CCi, "f_FRi 0x%x", 'x', f_FRi, "f_FRj 0x%x", 'x', f_FRj, "f_cond 0x%x", 'x', f_cond, "f_ACC40Sk 0x%x", 'x', f_ACC40Sk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_CCi) = f_CCi; + FLD (in_FRinti) = f_FRi; + FLD (in_FRintj) = f_FRj; + FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRinti_0) = ((FLD (f_FRi)) + (0)); + FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintj_0) = ((FLD (f_FRj)) + (0)); + FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRinti_0) = ((FLD (f_FRi)) + (0)); + FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintj_0) = ((FLD (f_FRj)) + (0)); + FLD (out_ACC40Sk) = f_ACC40Sk; + FLD (out_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Sk_1) = ((FLD (f_ACC40Sk)) + (1)); + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_mqmulhs: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + UINT f_ACC40Sk; + UINT f_FRi; + UINT f_FRj; + + f_ACC40Sk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_FRi) = f_FRi; + FLD (f_FRj) = f_FRj; + FLD (f_ACC40Sk) = f_ACC40Sk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mqmulhs", "f_FRi 0x%x", 'x', f_FRi, "f_FRj 0x%x", 'x', f_FRj, "f_ACC40Sk 0x%x", 'x', f_ACC40Sk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_FRintieven) = f_FRi; + FLD (in_FRintjeven) = f_FRj; + FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintieven_0) = ((FLD (f_FRi)) + (0)); + FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintieven_1) = ((FLD (f_FRi)) + (1)); + FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintjeven_0) = ((FLD (f_FRj)) + (0)); + FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintjeven_1) = ((FLD (f_FRj)) + (1)); + FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintieven_0) = ((FLD (f_FRi)) + (0)); + FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintieven_1) = ((FLD (f_FRi)) + (1)); + FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintjeven_0) = ((FLD (f_FRj)) + (0)); + FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintjeven_1) = ((FLD (f_FRj)) + (1)); + FLD (out_ACC40Sk) = f_ACC40Sk; + FLD (out_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Sk_1) = ((FLD (f_ACC40Sk)) + (1)); + FLD (out_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Sk_2) = ((FLD (f_ACC40Sk)) + (2)); + FLD (out_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Sk_3) = ((FLD (f_ACC40Sk)) + (3)); + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_cmqmulhs: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + UINT f_ACC40Sk; + UINT f_FRi; + UINT f_CCi; + UINT f_cond; + UINT f_FRj; + + f_ACC40Sk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); + f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_CCi) = f_CCi; + FLD (f_FRi) = f_FRi; + FLD (f_FRj) = f_FRj; + FLD (f_cond) = f_cond; + FLD (f_ACC40Sk) = f_ACC40Sk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmqmulhs", "f_CCi 0x%x", 'x', f_CCi, "f_FRi 0x%x", 'x', f_FRi, "f_FRj 0x%x", 'x', f_FRj, "f_cond 0x%x", 'x', f_cond, "f_ACC40Sk 0x%x", 'x', f_ACC40Sk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_CCi) = f_CCi; + FLD (in_FRintieven) = f_FRi; + FLD (in_FRintjeven) = f_FRj; + FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintieven_0) = ((FLD (f_FRi)) + (0)); + FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintieven_1) = ((FLD (f_FRi)) + (1)); + FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintjeven_0) = ((FLD (f_FRj)) + (0)); + FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintjeven_1) = ((FLD (f_FRj)) + (1)); + FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintieven_0) = ((FLD (f_FRi)) + (0)); + FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintieven_1) = ((FLD (f_FRi)) + (1)); + FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintjeven_0) = ((FLD (f_FRj)) + (0)); + FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintjeven_1) = ((FLD (f_FRj)) + (1)); + FLD (out_ACC40Sk) = f_ACC40Sk; + FLD (out_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Sk_1) = ((FLD (f_ACC40Sk)) + (1)); + FLD (out_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Sk_2) = ((FLD (f_ACC40Sk)) + (2)); + FLD (out_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Sk_3) = ((FLD (f_ACC40Sk)) + (3)); + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_mmachs: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cmmachs.f + UINT f_ACC40Sk; + UINT f_FRi; + UINT f_FRj; + + f_ACC40Sk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_ACC40Sk) = f_ACC40Sk; + FLD (f_FRi) = f_FRi; + FLD (f_FRj) = f_FRj; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mmachs", "f_ACC40Sk 0x%x", 'x', f_ACC40Sk, "f_FRi 0x%x", 'x', f_FRi, "f_FRj 0x%x", 'x', f_FRj, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_ACC40Sk) = f_ACC40Sk; + FLD (in_FRinti) = f_FRi; + FLD (in_FRintj) = f_FRj; + FLD (in_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Sk_1) = ((FLD (f_ACC40Sk)) + (1)); + FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRinti_0) = ((FLD (f_FRi)) + (0)); + FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintj_0) = ((FLD (f_FRj)) + (0)); + FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRinti_0) = ((FLD (f_FRi)) + (0)); + FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintj_0) = ((FLD (f_FRj)) + (0)); + FLD (out_ACC40Sk) = f_ACC40Sk; + FLD (out_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Sk_1) = ((FLD (f_ACC40Sk)) + (1)); + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_mmachu: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cmmachu.f + UINT f_ACC40Uk; + UINT f_FRi; + UINT f_FRj; + + f_ACC40Uk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_ACC40Uk) = f_ACC40Uk; + FLD (f_FRi) = f_FRi; + FLD (f_FRj) = f_FRj; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mmachu", "f_ACC40Uk 0x%x", 'x', f_ACC40Uk, "f_FRi 0x%x", 'x', f_FRi, "f_FRj 0x%x", 'x', f_FRj, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_ACC40Uk) = f_ACC40Uk; + FLD (in_FRinti) = f_FRi; + FLD (in_FRintj) = f_FRj; + FLD (in_h_acc40U_UDI_add__DFLT_index_of__DFLT_ACC40Uk_1) = ((FLD (f_ACC40Uk)) + (1)); + FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRinti_0) = ((FLD (f_FRi)) + (0)); + FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintj_0) = ((FLD (f_FRj)) + (0)); + FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRinti_0) = ((FLD (f_FRi)) + (0)); + FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintj_0) = ((FLD (f_FRj)) + (0)); + FLD (out_ACC40Uk) = f_ACC40Uk; + FLD (out_h_acc40U_UDI_add__DFLT_index_of__DFLT_ACC40Uk_1) = ((FLD (f_ACC40Uk)) + (1)); + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_cmmachs: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cmmachs.f + UINT f_ACC40Sk; + UINT f_FRi; + UINT f_CCi; + UINT f_cond; + UINT f_FRj; + + f_ACC40Sk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); + f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_ACC40Sk) = f_ACC40Sk; + FLD (f_CCi) = f_CCi; + FLD (f_FRi) = f_FRi; + FLD (f_FRj) = f_FRj; + FLD (f_cond) = f_cond; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmmachs", "f_ACC40Sk 0x%x", 'x', f_ACC40Sk, "f_CCi 0x%x", 'x', f_CCi, "f_FRi 0x%x", 'x', f_FRi, "f_FRj 0x%x", 'x', f_FRj, "f_cond 0x%x", 'x', f_cond, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_ACC40Sk) = f_ACC40Sk; + FLD (in_CCi) = f_CCi; + FLD (in_FRinti) = f_FRi; + FLD (in_FRintj) = f_FRj; + FLD (in_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Sk_1) = ((FLD (f_ACC40Sk)) + (1)); + FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRinti_0) = ((FLD (f_FRi)) + (0)); + FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintj_0) = ((FLD (f_FRj)) + (0)); + FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRinti_0) = ((FLD (f_FRi)) + (0)); + FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintj_0) = ((FLD (f_FRj)) + (0)); + FLD (out_ACC40Sk) = f_ACC40Sk; + FLD (out_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Sk_1) = ((FLD (f_ACC40Sk)) + (1)); + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_cmmachu: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cmmachu.f + UINT f_ACC40Uk; + UINT f_FRi; + UINT f_CCi; + UINT f_cond; + UINT f_FRj; + + f_ACC40Uk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); + f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_ACC40Uk) = f_ACC40Uk; + FLD (f_CCi) = f_CCi; + FLD (f_FRi) = f_FRi; + FLD (f_FRj) = f_FRj; + FLD (f_cond) = f_cond; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmmachu", "f_ACC40Uk 0x%x", 'x', f_ACC40Uk, "f_CCi 0x%x", 'x', f_CCi, "f_FRi 0x%x", 'x', f_FRi, "f_FRj 0x%x", 'x', f_FRj, "f_cond 0x%x", 'x', f_cond, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_ACC40Uk) = f_ACC40Uk; + FLD (in_CCi) = f_CCi; + FLD (in_FRinti) = f_FRi; + FLD (in_FRintj) = f_FRj; + FLD (in_h_acc40U_UDI_add__DFLT_index_of__DFLT_ACC40Uk_1) = ((FLD (f_ACC40Uk)) + (1)); + FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRinti_0) = ((FLD (f_FRi)) + (0)); + FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintj_0) = ((FLD (f_FRj)) + (0)); + FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRinti_0) = ((FLD (f_FRi)) + (0)); + FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintj_0) = ((FLD (f_FRj)) + (0)); + FLD (out_ACC40Uk) = f_ACC40Uk; + FLD (out_h_acc40U_UDI_add__DFLT_index_of__DFLT_ACC40Uk_1) = ((FLD (f_ACC40Uk)) + (1)); + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_mqmachs: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + UINT f_ACC40Sk; + UINT f_FRi; + UINT f_FRj; + + f_ACC40Sk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_ACC40Sk) = f_ACC40Sk; + FLD (f_FRi) = f_FRi; + FLD (f_FRj) = f_FRj; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mqmachs", "f_ACC40Sk 0x%x", 'x', f_ACC40Sk, "f_FRi 0x%x", 'x', f_FRi, "f_FRj 0x%x", 'x', f_FRj, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_ACC40Sk) = f_ACC40Sk; + FLD (in_FRintieven) = f_FRi; + FLD (in_FRintjeven) = f_FRj; + FLD (in_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Sk_1) = ((FLD (f_ACC40Sk)) + (1)); + FLD (in_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Sk_2) = ((FLD (f_ACC40Sk)) + (2)); + FLD (in_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Sk_3) = ((FLD (f_ACC40Sk)) + (3)); + FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintieven_0) = ((FLD (f_FRi)) + (0)); + FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintieven_1) = ((FLD (f_FRi)) + (1)); + FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintjeven_0) = ((FLD (f_FRj)) + (0)); + FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintjeven_1) = ((FLD (f_FRj)) + (1)); + FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintieven_0) = ((FLD (f_FRi)) + (0)); + FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintieven_1) = ((FLD (f_FRi)) + (1)); + FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintjeven_0) = ((FLD (f_FRj)) + (0)); + FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintjeven_1) = ((FLD (f_FRj)) + (1)); + FLD (out_ACC40Sk) = f_ACC40Sk; + FLD (out_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Sk_1) = ((FLD (f_ACC40Sk)) + (1)); + FLD (out_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Sk_2) = ((FLD (f_ACC40Sk)) + (2)); + FLD (out_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Sk_3) = ((FLD (f_ACC40Sk)) + (3)); + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_mqmachu: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cmqmachu.f + UINT f_ACC40Uk; + UINT f_FRi; + UINT f_FRj; + + f_ACC40Uk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_ACC40Uk) = f_ACC40Uk; + FLD (f_FRi) = f_FRi; + FLD (f_FRj) = f_FRj; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mqmachu", "f_ACC40Uk 0x%x", 'x', f_ACC40Uk, "f_FRi 0x%x", 'x', f_FRi, "f_FRj 0x%x", 'x', f_FRj, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_ACC40Uk) = f_ACC40Uk; + FLD (in_FRintieven) = f_FRi; + FLD (in_FRintjeven) = f_FRj; + FLD (in_h_acc40U_UDI_add__DFLT_index_of__DFLT_ACC40Uk_1) = ((FLD (f_ACC40Uk)) + (1)); + FLD (in_h_acc40U_UDI_add__DFLT_index_of__DFLT_ACC40Uk_2) = ((FLD (f_ACC40Uk)) + (2)); + FLD (in_h_acc40U_UDI_add__DFLT_index_of__DFLT_ACC40Uk_3) = ((FLD (f_ACC40Uk)) + (3)); + FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintieven_0) = ((FLD (f_FRi)) + (0)); + FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintieven_1) = ((FLD (f_FRi)) + (1)); + FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintjeven_0) = ((FLD (f_FRj)) + (0)); + FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintjeven_1) = ((FLD (f_FRj)) + (1)); + FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintieven_0) = ((FLD (f_FRi)) + (0)); + FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintieven_1) = ((FLD (f_FRi)) + (1)); + FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintjeven_0) = ((FLD (f_FRj)) + (0)); + FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintjeven_1) = ((FLD (f_FRj)) + (1)); + FLD (out_ACC40Uk) = f_ACC40Uk; + FLD (out_h_acc40U_UDI_add__DFLT_index_of__DFLT_ACC40Uk_1) = ((FLD (f_ACC40Uk)) + (1)); + FLD (out_h_acc40U_UDI_add__DFLT_index_of__DFLT_ACC40Uk_2) = ((FLD (f_ACC40Uk)) + (2)); + FLD (out_h_acc40U_UDI_add__DFLT_index_of__DFLT_ACC40Uk_3) = ((FLD (f_ACC40Uk)) + (3)); + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_cmqmachs: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + UINT f_ACC40Sk; + UINT f_FRi; + UINT f_CCi; + UINT f_cond; + UINT f_FRj; + + f_ACC40Sk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); + f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_ACC40Sk) = f_ACC40Sk; + FLD (f_CCi) = f_CCi; + FLD (f_FRi) = f_FRi; + FLD (f_FRj) = f_FRj; + FLD (f_cond) = f_cond; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmqmachs", "f_ACC40Sk 0x%x", 'x', f_ACC40Sk, "f_CCi 0x%x", 'x', f_CCi, "f_FRi 0x%x", 'x', f_FRi, "f_FRj 0x%x", 'x', f_FRj, "f_cond 0x%x", 'x', f_cond, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_ACC40Sk) = f_ACC40Sk; + FLD (in_CCi) = f_CCi; + FLD (in_FRintieven) = f_FRi; + FLD (in_FRintjeven) = f_FRj; + FLD (in_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Sk_1) = ((FLD (f_ACC40Sk)) + (1)); + FLD (in_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Sk_2) = ((FLD (f_ACC40Sk)) + (2)); + FLD (in_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Sk_3) = ((FLD (f_ACC40Sk)) + (3)); + FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintieven_0) = ((FLD (f_FRi)) + (0)); + FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintieven_1) = ((FLD (f_FRi)) + (1)); + FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintjeven_0) = ((FLD (f_FRj)) + (0)); + FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintjeven_1) = ((FLD (f_FRj)) + (1)); + FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintieven_0) = ((FLD (f_FRi)) + (0)); + FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintieven_1) = ((FLD (f_FRi)) + (1)); + FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintjeven_0) = ((FLD (f_FRj)) + (0)); + FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintjeven_1) = ((FLD (f_FRj)) + (1)); + FLD (out_ACC40Sk) = f_ACC40Sk; + FLD (out_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Sk_1) = ((FLD (f_ACC40Sk)) + (1)); + FLD (out_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Sk_2) = ((FLD (f_ACC40Sk)) + (2)); + FLD (out_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Sk_3) = ((FLD (f_ACC40Sk)) + (3)); + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_cmqmachu: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cmqmachu.f + UINT f_ACC40Uk; + UINT f_FRi; + UINT f_CCi; + UINT f_cond; + UINT f_FRj; + + f_ACC40Uk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); + f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_ACC40Uk) = f_ACC40Uk; + FLD (f_CCi) = f_CCi; + FLD (f_FRi) = f_FRi; + FLD (f_FRj) = f_FRj; + FLD (f_cond) = f_cond; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmqmachu", "f_ACC40Uk 0x%x", 'x', f_ACC40Uk, "f_CCi 0x%x", 'x', f_CCi, "f_FRi 0x%x", 'x', f_FRi, "f_FRj 0x%x", 'x', f_FRj, "f_cond 0x%x", 'x', f_cond, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_ACC40Uk) = f_ACC40Uk; + FLD (in_CCi) = f_CCi; + FLD (in_FRintieven) = f_FRi; + FLD (in_FRintjeven) = f_FRj; + FLD (in_h_acc40U_UDI_add__DFLT_index_of__DFLT_ACC40Uk_1) = ((FLD (f_ACC40Uk)) + (1)); + FLD (in_h_acc40U_UDI_add__DFLT_index_of__DFLT_ACC40Uk_2) = ((FLD (f_ACC40Uk)) + (2)); + FLD (in_h_acc40U_UDI_add__DFLT_index_of__DFLT_ACC40Uk_3) = ((FLD (f_ACC40Uk)) + (3)); + FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintieven_0) = ((FLD (f_FRi)) + (0)); + FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintieven_1) = ((FLD (f_FRi)) + (1)); + FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintjeven_0) = ((FLD (f_FRj)) + (0)); + FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintjeven_1) = ((FLD (f_FRj)) + (1)); + FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintieven_0) = ((FLD (f_FRi)) + (0)); + FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintieven_1) = ((FLD (f_FRi)) + (1)); + FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintjeven_0) = ((FLD (f_FRj)) + (0)); + FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintjeven_1) = ((FLD (f_FRj)) + (1)); + FLD (out_ACC40Uk) = f_ACC40Uk; + FLD (out_h_acc40U_UDI_add__DFLT_index_of__DFLT_ACC40Uk_1) = ((FLD (f_ACC40Uk)) + (1)); + FLD (out_h_acc40U_UDI_add__DFLT_index_of__DFLT_ACC40Uk_2) = ((FLD (f_ACC40Uk)) + (2)); + FLD (out_h_acc40U_UDI_add__DFLT_index_of__DFLT_ACC40Uk_3) = ((FLD (f_ACC40Uk)) + (3)); + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_mcpxrs: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cmmachs.f + UINT f_ACC40Sk; + UINT f_FRi; + UINT f_FRj; + + f_ACC40Sk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_FRi) = f_FRi; + FLD (f_FRj) = f_FRj; + FLD (f_ACC40Sk) = f_ACC40Sk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mcpxrs", "f_FRi 0x%x", 'x', f_FRi, "f_FRj 0x%x", 'x', f_FRj, "f_ACC40Sk 0x%x", 'x', f_ACC40Sk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_FRinti) = f_FRi; + FLD (in_FRintj) = f_FRj; + FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRinti_0) = ((FLD (f_FRi)) + (0)); + FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintj_0) = ((FLD (f_FRj)) + (0)); + FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRinti_0) = ((FLD (f_FRi)) + (0)); + FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintj_0) = ((FLD (f_FRj)) + (0)); + FLD (out_ACC40Sk) = f_ACC40Sk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_cmcpxrs: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cmmachs.f + UINT f_ACC40Sk; + UINT f_FRi; + UINT f_CCi; + UINT f_cond; + UINT f_FRj; + + f_ACC40Sk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); + f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_CCi) = f_CCi; + FLD (f_FRi) = f_FRi; + FLD (f_FRj) = f_FRj; + FLD (f_cond) = f_cond; + FLD (f_ACC40Sk) = f_ACC40Sk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmcpxrs", "f_CCi 0x%x", 'x', f_CCi, "f_FRi 0x%x", 'x', f_FRi, "f_FRj 0x%x", 'x', f_FRj, "f_cond 0x%x", 'x', f_cond, "f_ACC40Sk 0x%x", 'x', f_ACC40Sk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_CCi) = f_CCi; + FLD (in_FRinti) = f_FRi; + FLD (in_FRintj) = f_FRj; + FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRinti_0) = ((FLD (f_FRi)) + (0)); + FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintj_0) = ((FLD (f_FRj)) + (0)); + FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRinti_0) = ((FLD (f_FRi)) + (0)); + FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintj_0) = ((FLD (f_FRj)) + (0)); + FLD (out_ACC40Sk) = f_ACC40Sk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_mqcpxrs: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + UINT f_ACC40Sk; + UINT f_FRi; + UINT f_FRj; + + f_ACC40Sk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_FRi) = f_FRi; + FLD (f_FRj) = f_FRj; + FLD (f_ACC40Sk) = f_ACC40Sk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mqcpxrs", "f_FRi 0x%x", 'x', f_FRi, "f_FRj 0x%x", 'x', f_FRj, "f_ACC40Sk 0x%x", 'x', f_ACC40Sk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_FRintieven) = f_FRi; + FLD (in_FRintjeven) = f_FRj; + FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintieven_0) = ((FLD (f_FRi)) + (0)); + FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintieven_1) = ((FLD (f_FRi)) + (1)); + FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintjeven_0) = ((FLD (f_FRj)) + (0)); + FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintjeven_1) = ((FLD (f_FRj)) + (1)); + FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintieven_0) = ((FLD (f_FRi)) + (0)); + FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintieven_1) = ((FLD (f_FRi)) + (1)); + FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintjeven_0) = ((FLD (f_FRj)) + (0)); + FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintjeven_1) = ((FLD (f_FRj)) + (1)); + FLD (out_ACC40Sk) = f_ACC40Sk; + FLD (out_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Sk_1) = ((FLD (f_ACC40Sk)) + (1)); + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_mexpdhw: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cmexpdhw.f + UINT f_FRk; + UINT f_FRi; + UINT f_u6; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_u6 = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_FRi) = f_FRi; + FLD (f_FRk) = f_FRk; + FLD (f_u6) = f_u6; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mexpdhw", "f_FRi 0x%x", 'x', f_FRi, "f_FRk 0x%x", 'x', f_FRk, "f_u6 0x%x", 'x', f_u6, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRinti_0) = ((FLD (f_FRi)) + (0)); + FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRinti_0) = ((FLD (f_FRi)) + (0)); + FLD (out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintk_0) = ((FLD (f_FRk)) + (0)); + FLD (out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintk_0) = ((FLD (f_FRk)) + (0)); + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_cmexpdhw: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cmexpdhw.f + UINT f_FRk; + UINT f_FRi; + UINT f_CCi; + UINT f_cond; + UINT f_u6; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); + f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); + f_u6 = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_CCi) = f_CCi; + FLD (f_cond) = f_cond; + FLD (f_FRi) = f_FRi; + FLD (f_FRk) = f_FRk; + FLD (f_u6) = f_u6; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmexpdhw", "f_CCi 0x%x", 'x', f_CCi, "f_cond 0x%x", 'x', f_cond, "f_FRi 0x%x", 'x', f_FRi, "f_FRk 0x%x", 'x', f_FRk, "f_u6 0x%x", 'x', f_u6, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_CCi) = f_CCi; + FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRinti_0) = ((FLD (f_FRi)) + (0)); + FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRinti_0) = ((FLD (f_FRi)) + (0)); + FLD (out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintk_0) = ((FLD (f_FRk)) + (0)); + FLD (out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintk_0) = ((FLD (f_FRk)) + (0)); + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_mexpdhd: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cmexpdhd.f + UINT f_FRk; + UINT f_FRi; + UINT f_u6; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_u6 = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_FRk) = f_FRk; + FLD (f_FRi) = f_FRi; + FLD (f_u6) = f_u6; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mexpdhd", "f_FRk 0x%x", 'x', f_FRk, "f_FRi 0x%x", 'x', f_FRi, "f_u6 0x%x", 'x', f_u6, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_FRintkeven) = f_FRk; + FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRinti_0) = ((FLD (f_FRi)) + (0)); + FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRinti_0) = ((FLD (f_FRi)) + (0)); + FLD (out_FRintkeven) = f_FRk; + FLD (out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintkeven_0) = ((FLD (f_FRk)) + (0)); + FLD (out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintkeven_1) = ((FLD (f_FRk)) + (1)); + FLD (out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintkeven_0) = ((FLD (f_FRk)) + (0)); + FLD (out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintkeven_1) = ((FLD (f_FRk)) + (1)); + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_cmexpdhd: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cmexpdhd.f + UINT f_FRk; + UINT f_FRi; + UINT f_CCi; + UINT f_cond; + UINT f_u6; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); + f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); + f_u6 = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_CCi) = f_CCi; + FLD (f_FRk) = f_FRk; + FLD (f_cond) = f_cond; + FLD (f_FRi) = f_FRi; + FLD (f_u6) = f_u6; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmexpdhd", "f_CCi 0x%x", 'x', f_CCi, "f_FRk 0x%x", 'x', f_FRk, "f_cond 0x%x", 'x', f_cond, "f_FRi 0x%x", 'x', f_FRi, "f_u6 0x%x", 'x', f_u6, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_CCi) = f_CCi; + FLD (in_FRintkeven) = f_FRk; + FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRinti_0) = ((FLD (f_FRi)) + (0)); + FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRinti_0) = ((FLD (f_FRi)) + (0)); + FLD (out_FRintkeven) = f_FRk; + FLD (out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintkeven_0) = ((FLD (f_FRk)) + (0)); + FLD (out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintkeven_1) = ((FLD (f_FRk)) + (1)); + FLD (out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintkeven_0) = ((FLD (f_FRk)) + (0)); + FLD (out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintkeven_1) = ((FLD (f_FRk)) + (1)); + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_mpackh: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + UINT f_FRk; + UINT f_FRi; + UINT f_FRj; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_FRi) = f_FRi; + FLD (f_FRj) = f_FRj; + FLD (f_FRk) = f_FRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mpackh", "f_FRi 0x%x", 'x', f_FRi, "f_FRj 0x%x", 'x', f_FRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRinti_0) = ((FLD (f_FRi)) + (0)); + FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintj_0) = ((FLD (f_FRj)) + (0)); + FLD (out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintk_0) = ((FLD (f_FRk)) + (0)); + FLD (out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintk_0) = ((FLD (f_FRk)) + (0)); + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_mdpackh: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_mdpackh.f + UINT f_FRk; + UINT f_FRi; + UINT f_FRj; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_FRi) = f_FRi; + FLD (f_FRj) = f_FRj; + FLD (f_FRk) = f_FRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mdpackh", "f_FRi 0x%x", 'x', f_FRi, "f_FRj 0x%x", 'x', f_FRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_FRintieven) = f_FRi; + FLD (in_FRintjeven) = f_FRj; + FLD (in_FRintkeven) = f_FRk; + FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintieven_0) = ((FLD (f_FRi)) + (0)); + FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintieven_1) = ((FLD (f_FRi)) + (1)); + FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintjeven_0) = ((FLD (f_FRj)) + (0)); + FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintjeven_1) = ((FLD (f_FRj)) + (1)); + FLD (out_FRintieven) = f_FRi; + FLD (out_FRintjeven) = f_FRj; + FLD (out_FRintkeven) = f_FRk; + FLD (out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintkeven_0) = ((FLD (f_FRk)) + (0)); + FLD (out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintkeven_1) = ((FLD (f_FRk)) + (1)); + FLD (out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintkeven_0) = ((FLD (f_FRk)) + (0)); + FLD (out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintkeven_1) = ((FLD (f_FRk)) + (1)); + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_munpackh: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_munpackh.f + UINT f_FRk; + UINT f_FRi; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_FRi) = f_FRi; + FLD (f_FRk) = f_FRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_munpackh", "f_FRi 0x%x", 'x', f_FRi, "f_FRk 0x%x", 'x', f_FRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_FRinti) = f_FRi; + FLD (in_FRintkeven) = f_FRk; + FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRinti_0) = ((FLD (f_FRi)) + (0)); + FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRinti_0) = ((FLD (f_FRi)) + (0)); + FLD (out_FRinti) = f_FRi; + FLD (out_FRintkeven) = f_FRk; + FLD (out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintkeven_0) = ((FLD (f_FRk)) + (0)); + FLD (out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintkeven_add__DFLT_0_1) = ((FLD (f_FRk)) + (((0) + (1)))); + FLD (out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintkeven_0) = ((FLD (f_FRk)) + (0)); + FLD (out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintkeven_add__DFLT_0_1) = ((FLD (f_FRk)) + (((0) + (1)))); + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_mdunpackh: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_mdunpackh.f + UINT f_FRk; + UINT f_FRi; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_FRi) = f_FRi; + FLD (f_FRk) = f_FRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mdunpackh", "f_FRi 0x%x", 'x', f_FRi, "f_FRk 0x%x", 'x', f_FRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_FRintieven) = f_FRi; + FLD (in_FRintk) = f_FRk; + FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintieven_0) = ((FLD (f_FRi)) + (0)); + FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintieven_1) = ((FLD (f_FRi)) + (1)); + FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintieven_0) = ((FLD (f_FRi)) + (0)); + FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintieven_1) = ((FLD (f_FRi)) + (1)); + FLD (out_FRintieven) = f_FRi; + FLD (out_FRintk) = f_FRk; + FLD (out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintk_0) = ((FLD (f_FRk)) + (0)); + FLD (out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintk_2) = ((FLD (f_FRk)) + (2)); + FLD (out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintk_add__DFLT_0_1) = ((FLD (f_FRk)) + (((0) + (1)))); + FLD (out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintk_add__DFLT_2_1) = ((FLD (f_FRk)) + (((2) + (1)))); + FLD (out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintk_0) = ((FLD (f_FRk)) + (0)); + FLD (out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintk_2) = ((FLD (f_FRk)) + (2)); + FLD (out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintk_add__DFLT_0_1) = ((FLD (f_FRk)) + (((0) + (1)))); + FLD (out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintk_add__DFLT_2_1) = ((FLD (f_FRk)) + (((2) + (1)))); + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_mbtoh: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cmbtoh.f + UINT f_FRk; + UINT f_FRj; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_FRj) = f_FRj; + FLD (f_FRk) = f_FRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mbtoh", "f_FRj 0x%x", 'x', f_FRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_FRintj) = f_FRj; + FLD (in_FRintkeven) = f_FRk; + FLD (in_h_fr_0_UHI_add__DFLT_index_of__DFLT_FRintj_0) = ((FLD (f_FRj)) + (0)); + FLD (in_h_fr_1_UHI_add__DFLT_index_of__DFLT_FRintj_0) = ((FLD (f_FRj)) + (0)); + FLD (in_h_fr_2_UHI_add__DFLT_index_of__DFLT_FRintj_0) = ((FLD (f_FRj)) + (0)); + FLD (in_h_fr_3_UHI_add__DFLT_index_of__DFLT_FRintj_0) = ((FLD (f_FRj)) + (0)); + FLD (out_FRintj) = f_FRj; + FLD (out_FRintkeven) = f_FRk; + FLD (out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintkeven_0) = ((FLD (f_FRk)) + (0)); + FLD (out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintkeven_1) = ((FLD (f_FRk)) + (1)); + FLD (out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintkeven_0) = ((FLD (f_FRk)) + (0)); + FLD (out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintkeven_1) = ((FLD (f_FRk)) + (1)); + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_cmbtoh: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cmbtoh.f + UINT f_FRk; + UINT f_CCi; + UINT f_cond; + UINT f_FRj; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); + f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_CCi) = f_CCi; + FLD (f_FRj) = f_FRj; + FLD (f_FRk) = f_FRk; + FLD (f_cond) = f_cond; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmbtoh", "f_CCi 0x%x", 'x', f_CCi, "f_FRj 0x%x", 'x', f_FRj, "f_FRk 0x%x", 'x', f_FRk, "f_cond 0x%x", 'x', f_cond, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_CCi) = f_CCi; + FLD (in_FRintj) = f_FRj; + FLD (in_FRintkeven) = f_FRk; + FLD (in_h_fr_0_UHI_add__DFLT_index_of__DFLT_FRintj_0) = ((FLD (f_FRj)) + (0)); + FLD (in_h_fr_1_UHI_add__DFLT_index_of__DFLT_FRintj_0) = ((FLD (f_FRj)) + (0)); + FLD (in_h_fr_2_UHI_add__DFLT_index_of__DFLT_FRintj_0) = ((FLD (f_FRj)) + (0)); + FLD (in_h_fr_3_UHI_add__DFLT_index_of__DFLT_FRintj_0) = ((FLD (f_FRj)) + (0)); + FLD (out_FRintj) = f_FRj; + FLD (out_FRintkeven) = f_FRk; + FLD (out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintkeven_0) = ((FLD (f_FRk)) + (0)); + FLD (out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintkeven_1) = ((FLD (f_FRk)) + (1)); + FLD (out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintkeven_0) = ((FLD (f_FRk)) + (0)); + FLD (out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintkeven_1) = ((FLD (f_FRk)) + (1)); + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_mhtob: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cmhtob.f + UINT f_FRk; + UINT f_FRj; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_FRj) = f_FRj; + FLD (f_FRk) = f_FRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mhtob", "f_FRj 0x%x", 'x', f_FRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_FRintjeven) = f_FRj; + FLD (in_FRintk) = f_FRk; + FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintjeven_0) = ((FLD (f_FRj)) + (0)); + FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintjeven_1) = ((FLD (f_FRj)) + (1)); + FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintjeven_0) = ((FLD (f_FRj)) + (0)); + FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintjeven_1) = ((FLD (f_FRj)) + (1)); + FLD (out_FRintjeven) = f_FRj; + FLD (out_FRintk) = f_FRk; + FLD (out_h_fr_0_UHI_add__DFLT_index_of__DFLT_FRintk_0) = ((FLD (f_FRk)) + (0)); + FLD (out_h_fr_1_UHI_add__DFLT_index_of__DFLT_FRintk_0) = ((FLD (f_FRk)) + (0)); + FLD (out_h_fr_2_UHI_add__DFLT_index_of__DFLT_FRintk_0) = ((FLD (f_FRk)) + (0)); + FLD (out_h_fr_3_UHI_add__DFLT_index_of__DFLT_FRintk_0) = ((FLD (f_FRk)) + (0)); + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_cmhtob: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cmhtob.f + UINT f_FRk; + UINT f_CCi; + UINT f_cond; + UINT f_FRj; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); + f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_CCi) = f_CCi; + FLD (f_FRj) = f_FRj; + FLD (f_FRk) = f_FRk; + FLD (f_cond) = f_cond; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmhtob", "f_CCi 0x%x", 'x', f_CCi, "f_FRj 0x%x", 'x', f_FRj, "f_FRk 0x%x", 'x', f_FRk, "f_cond 0x%x", 'x', f_cond, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_CCi) = f_CCi; + FLD (in_FRintjeven) = f_FRj; + FLD (in_FRintk) = f_FRk; + FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintjeven_0) = ((FLD (f_FRj)) + (0)); + FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintjeven_1) = ((FLD (f_FRj)) + (1)); + FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintjeven_0) = ((FLD (f_FRj)) + (0)); + FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintjeven_1) = ((FLD (f_FRj)) + (1)); + FLD (out_FRintjeven) = f_FRj; + FLD (out_FRintk) = f_FRk; + FLD (out_h_fr_0_UHI_add__DFLT_index_of__DFLT_FRintk_0) = ((FLD (f_FRk)) + (0)); + FLD (out_h_fr_1_UHI_add__DFLT_index_of__DFLT_FRintk_0) = ((FLD (f_FRk)) + (0)); + FLD (out_h_fr_2_UHI_add__DFLT_index_of__DFLT_FRintk_0) = ((FLD (f_FRk)) + (0)); + FLD (out_h_fr_3_UHI_add__DFLT_index_of__DFLT_FRintk_0) = ((FLD (f_FRk)) + (0)); + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_mbtohe: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cmbtohe.f + UINT f_FRk; + UINT f_FRj; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_FRj) = f_FRj; + FLD (f_FRk) = f_FRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mbtohe", "f_FRj 0x%x", 'x', f_FRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_FRintj) = f_FRj; + FLD (in_FRintk) = f_FRk; + FLD (in_h_fr_0_UHI_add__DFLT_index_of__DFLT_FRintj_0) = ((FLD (f_FRj)) + (0)); + FLD (in_h_fr_1_UHI_add__DFLT_index_of__DFLT_FRintj_0) = ((FLD (f_FRj)) + (0)); + FLD (in_h_fr_2_UHI_add__DFLT_index_of__DFLT_FRintj_0) = ((FLD (f_FRj)) + (0)); + FLD (in_h_fr_3_UHI_add__DFLT_index_of__DFLT_FRintj_0) = ((FLD (f_FRj)) + (0)); + FLD (out_FRintj) = f_FRj; + FLD (out_FRintk) = f_FRk; + FLD (out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintk_0) = ((FLD (f_FRk)) + (0)); + FLD (out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintk_1) = ((FLD (f_FRk)) + (1)); + FLD (out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintk_2) = ((FLD (f_FRk)) + (2)); + FLD (out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintk_3) = ((FLD (f_FRk)) + (3)); + FLD (out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintk_0) = ((FLD (f_FRk)) + (0)); + FLD (out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintk_1) = ((FLD (f_FRk)) + (1)); + FLD (out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintk_2) = ((FLD (f_FRk)) + (2)); + FLD (out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintk_3) = ((FLD (f_FRk)) + (3)); + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_cmbtohe: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cmbtohe.f + UINT f_FRk; + UINT f_CCi; + UINT f_cond; + UINT f_FRj; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); + f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); + f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_CCi) = f_CCi; + FLD (f_FRj) = f_FRj; + FLD (f_FRk) = f_FRk; + FLD (f_cond) = f_cond; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmbtohe", "f_CCi 0x%x", 'x', f_CCi, "f_FRj 0x%x", 'x', f_FRj, "f_FRk 0x%x", 'x', f_FRk, "f_cond 0x%x", 'x', f_cond, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_CCi) = f_CCi; + FLD (in_FRintj) = f_FRj; + FLD (in_FRintk) = f_FRk; + FLD (in_h_fr_0_UHI_add__DFLT_index_of__DFLT_FRintj_0) = ((FLD (f_FRj)) + (0)); + FLD (in_h_fr_1_UHI_add__DFLT_index_of__DFLT_FRintj_0) = ((FLD (f_FRj)) + (0)); + FLD (in_h_fr_2_UHI_add__DFLT_index_of__DFLT_FRintj_0) = ((FLD (f_FRj)) + (0)); + FLD (in_h_fr_3_UHI_add__DFLT_index_of__DFLT_FRintj_0) = ((FLD (f_FRj)) + (0)); + FLD (out_FRintj) = f_FRj; + FLD (out_FRintk) = f_FRk; + FLD (out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintk_0) = ((FLD (f_FRk)) + (0)); + FLD (out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintk_1) = ((FLD (f_FRk)) + (1)); + FLD (out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintk_2) = ((FLD (f_FRk)) + (2)); + FLD (out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintk_3) = ((FLD (f_FRk)) + (3)); + FLD (out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintk_0) = ((FLD (f_FRk)) + (0)); + FLD (out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintk_1) = ((FLD (f_FRk)) + (1)); + FLD (out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintk_2) = ((FLD (f_FRk)) + (2)); + FLD (out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintk_3) = ((FLD (f_FRk)) + (3)); + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_mclracc_0: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_mdasaccs.f + UINT f_ACC40Sk; + + f_ACC40Sk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_ACC40Sk) = f_ACC40Sk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mclracc_0", "f_ACC40Sk 0x%x", 'x', f_ACC40Sk, (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_mrdacc: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_mcuti.f + UINT f_FRk; + UINT f_ACC40Si; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_ACC40Si = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_ACC40Si) = f_ACC40Si; + FLD (f_FRk) = f_FRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mrdacc", "f_ACC40Si 0x%x", 'x', f_ACC40Si, "f_FRk 0x%x", 'x', f_FRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_ACC40Si) = f_ACC40Si; + FLD (out_FRintk) = f_FRk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_mrdaccg: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_mrdaccg.f + UINT f_FRk; + UINT f_ACCGi; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_ACCGi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_ACCGi) = f_ACCGi; + FLD (f_FRk) = f_FRk; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mrdaccg", "f_ACCGi 0x%x", 'x', f_ACCGi, "f_FRk 0x%x", 'x', f_FRk, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_ACCGi) = f_ACCGi; + FLD (out_FRintk) = f_FRk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_mwtacc: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_cmmachs.f + UINT f_ACC40Sk; + UINT f_FRi; + + f_ACC40Sk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_ACC40Sk) = f_ACC40Sk; + FLD (f_FRi) = f_FRi; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mwtacc", "f_ACC40Sk 0x%x", 'x', f_ACC40Sk, "f_FRi 0x%x", 'x', f_FRi, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_ACC40Sk) = f_ACC40Sk; + FLD (in_FRinti) = f_FRi; + FLD (out_ACC40Sk) = f_ACC40Sk; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_mwtaccg: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_mwtaccg.f + UINT f_ACCGk; + UINT f_FRi; + + f_ACCGk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_ACCGk) = f_ACCGk; + FLD (f_FRi) = f_FRi; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mwtaccg", "f_ACCGk 0x%x", 'x', f_ACCGk, "f_FRi 0x%x", 'x', f_FRi, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_ACCGk) = f_ACCGk; + FLD (in_FRinti) = f_FRi; + FLD (out_ACCGk) = f_ACCGk; + } +#endif +#undef FLD + return idesc; + } + +} diff --git a/sim/frv/decode.h b/sim/frv/decode.h new file mode 100644 index 0000000..9741d36 --- /dev/null +++ b/sim/frv/decode.h @@ -0,0 +1,455 @@ +/* Decode header for frvbf. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. + +This file is part of the GNU simulators. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +*/ + +#ifndef FRVBF_DECODE_H +#define FRVBF_DECODE_H + +extern const IDESC *frvbf_decode (SIM_CPU *, IADDR, + CGEN_INSN_INT, CGEN_INSN_INT, + ARGBUF *); +extern void frvbf_init_idesc_table (SIM_CPU *); +extern void frvbf_sem_init_idesc_table (SIM_CPU *); +extern void frvbf_semf_init_idesc_table (SIM_CPU *); + +/* Enum declaration for instructions in cpu family frvbf. */ +typedef enum frvbf_insn_type { + FRVBF_INSN_X_INVALID, FRVBF_INSN_X_AFTER, FRVBF_INSN_X_BEFORE, FRVBF_INSN_X_CTI_CHAIN + , FRVBF_INSN_X_CHAIN, FRVBF_INSN_X_BEGIN, FRVBF_INSN_ADD, FRVBF_INSN_SUB + , FRVBF_INSN_AND, FRVBF_INSN_OR, FRVBF_INSN_XOR, FRVBF_INSN_NOT + , FRVBF_INSN_SDIV, FRVBF_INSN_NSDIV, FRVBF_INSN_UDIV, FRVBF_INSN_NUDIV + , FRVBF_INSN_SMUL, FRVBF_INSN_UMUL, FRVBF_INSN_SMU, FRVBF_INSN_SMASS + , FRVBF_INSN_SMSSS, FRVBF_INSN_SLL, FRVBF_INSN_SRL, FRVBF_INSN_SRA + , FRVBF_INSN_SLASS, FRVBF_INSN_SCUTSS, FRVBF_INSN_SCAN, FRVBF_INSN_CADD + , FRVBF_INSN_CSUB, FRVBF_INSN_CAND, FRVBF_INSN_COR, FRVBF_INSN_CXOR + , FRVBF_INSN_CNOT, FRVBF_INSN_CSMUL, FRVBF_INSN_CSDIV, FRVBF_INSN_CUDIV + , FRVBF_INSN_CSLL, FRVBF_INSN_CSRL, FRVBF_INSN_CSRA, FRVBF_INSN_CSCAN + , FRVBF_INSN_ADDCC, FRVBF_INSN_SUBCC, FRVBF_INSN_ANDCC, FRVBF_INSN_ORCC + , FRVBF_INSN_XORCC, FRVBF_INSN_SLLCC, FRVBF_INSN_SRLCC, FRVBF_INSN_SRACC + , FRVBF_INSN_SMULCC, FRVBF_INSN_UMULCC, FRVBF_INSN_CADDCC, FRVBF_INSN_CSUBCC + , FRVBF_INSN_CSMULCC, FRVBF_INSN_CANDCC, FRVBF_INSN_CORCC, FRVBF_INSN_CXORCC + , FRVBF_INSN_CSLLCC, FRVBF_INSN_CSRLCC, FRVBF_INSN_CSRACC, FRVBF_INSN_ADDX + , FRVBF_INSN_SUBX, FRVBF_INSN_ADDXCC, FRVBF_INSN_SUBXCC, FRVBF_INSN_ADDSS + , FRVBF_INSN_SUBSS, FRVBF_INSN_ADDI, FRVBF_INSN_SUBI, FRVBF_INSN_ANDI + , FRVBF_INSN_ORI, FRVBF_INSN_XORI, FRVBF_INSN_SDIVI, FRVBF_INSN_NSDIVI + , FRVBF_INSN_UDIVI, FRVBF_INSN_NUDIVI, FRVBF_INSN_SMULI, FRVBF_INSN_UMULI + , FRVBF_INSN_SLLI, FRVBF_INSN_SRLI, FRVBF_INSN_SRAI, FRVBF_INSN_SCANI + , FRVBF_INSN_ADDICC, FRVBF_INSN_SUBICC, FRVBF_INSN_ANDICC, FRVBF_INSN_ORICC + , FRVBF_INSN_XORICC, FRVBF_INSN_SMULICC, FRVBF_INSN_UMULICC, FRVBF_INSN_SLLICC + , FRVBF_INSN_SRLICC, FRVBF_INSN_SRAICC, FRVBF_INSN_ADDXI, FRVBF_INSN_SUBXI + , FRVBF_INSN_ADDXICC, FRVBF_INSN_SUBXICC, FRVBF_INSN_CMPB, FRVBF_INSN_CMPBA + , FRVBF_INSN_SETLO, FRVBF_INSN_SETHI, FRVBF_INSN_SETLOS, FRVBF_INSN_LDSB + , FRVBF_INSN_LDUB, FRVBF_INSN_LDSH, FRVBF_INSN_LDUH, FRVBF_INSN_LD + , FRVBF_INSN_LDBF, FRVBF_INSN_LDHF, FRVBF_INSN_LDF, FRVBF_INSN_LDC + , FRVBF_INSN_NLDSB, FRVBF_INSN_NLDUB, FRVBF_INSN_NLDSH, FRVBF_INSN_NLDUH + , FRVBF_INSN_NLD, FRVBF_INSN_NLDBF, FRVBF_INSN_NLDHF, FRVBF_INSN_NLDF + , FRVBF_INSN_LDD, FRVBF_INSN_LDDF, FRVBF_INSN_LDDC, FRVBF_INSN_NLDD + , FRVBF_INSN_NLDDF, FRVBF_INSN_LDQ, FRVBF_INSN_LDQF, FRVBF_INSN_LDQC + , FRVBF_INSN_NLDQ, FRVBF_INSN_NLDQF, FRVBF_INSN_LDSBU, FRVBF_INSN_LDUBU + , FRVBF_INSN_LDSHU, FRVBF_INSN_LDUHU, FRVBF_INSN_LDU, FRVBF_INSN_NLDSBU + , FRVBF_INSN_NLDUBU, FRVBF_INSN_NLDSHU, FRVBF_INSN_NLDUHU, FRVBF_INSN_NLDU + , FRVBF_INSN_LDBFU, FRVBF_INSN_LDHFU, FRVBF_INSN_LDFU, FRVBF_INSN_LDCU + , FRVBF_INSN_NLDBFU, FRVBF_INSN_NLDHFU, FRVBF_INSN_NLDFU, FRVBF_INSN_LDDU + , FRVBF_INSN_NLDDU, FRVBF_INSN_LDDFU, FRVBF_INSN_LDDCU, FRVBF_INSN_NLDDFU + , FRVBF_INSN_LDQU, FRVBF_INSN_NLDQU, FRVBF_INSN_LDQFU, FRVBF_INSN_LDQCU + , FRVBF_INSN_NLDQFU, FRVBF_INSN_LDSBI, FRVBF_INSN_LDSHI, FRVBF_INSN_LDI + , FRVBF_INSN_LDUBI, FRVBF_INSN_LDUHI, FRVBF_INSN_LDBFI, FRVBF_INSN_LDHFI + , FRVBF_INSN_LDFI, FRVBF_INSN_NLDSBI, FRVBF_INSN_NLDUBI, FRVBF_INSN_NLDSHI + , FRVBF_INSN_NLDUHI, FRVBF_INSN_NLDI, FRVBF_INSN_NLDBFI, FRVBF_INSN_NLDHFI + , FRVBF_INSN_NLDFI, FRVBF_INSN_LDDI, FRVBF_INSN_LDDFI, FRVBF_INSN_NLDDI + , FRVBF_INSN_NLDDFI, FRVBF_INSN_LDQI, FRVBF_INSN_LDQFI, FRVBF_INSN_NLDQFI + , FRVBF_INSN_STB, FRVBF_INSN_STH, FRVBF_INSN_ST, FRVBF_INSN_STBF + , FRVBF_INSN_STHF, FRVBF_INSN_STF, FRVBF_INSN_STC, FRVBF_INSN_RSTB + , FRVBF_INSN_RSTH, FRVBF_INSN_RST, FRVBF_INSN_RSTBF, FRVBF_INSN_RSTHF + , FRVBF_INSN_RSTF, FRVBF_INSN_STD, FRVBF_INSN_STDF, FRVBF_INSN_STDC + , FRVBF_INSN_RSTD, FRVBF_INSN_RSTDF, FRVBF_INSN_STQ, FRVBF_INSN_STQF + , FRVBF_INSN_STQC, FRVBF_INSN_RSTQ, FRVBF_INSN_RSTQF, FRVBF_INSN_STBU + , FRVBF_INSN_STHU, FRVBF_INSN_STU, FRVBF_INSN_STBFU, FRVBF_INSN_STHFU + , FRVBF_INSN_STFU, FRVBF_INSN_STCU, FRVBF_INSN_STDU, FRVBF_INSN_STDFU + , FRVBF_INSN_STDCU, FRVBF_INSN_STQU, FRVBF_INSN_STQFU, FRVBF_INSN_STQCU + , FRVBF_INSN_CLDSB, FRVBF_INSN_CLDUB, FRVBF_INSN_CLDSH, FRVBF_INSN_CLDUH + , FRVBF_INSN_CLD, FRVBF_INSN_CLDBF, FRVBF_INSN_CLDHF, FRVBF_INSN_CLDF + , FRVBF_INSN_CLDD, FRVBF_INSN_CLDDF, FRVBF_INSN_CLDQ, FRVBF_INSN_CLDSBU + , FRVBF_INSN_CLDUBU, FRVBF_INSN_CLDSHU, FRVBF_INSN_CLDUHU, FRVBF_INSN_CLDU + , FRVBF_INSN_CLDBFU, FRVBF_INSN_CLDHFU, FRVBF_INSN_CLDFU, FRVBF_INSN_CLDDU + , FRVBF_INSN_CLDDFU, FRVBF_INSN_CLDQU, FRVBF_INSN_CSTB, FRVBF_INSN_CSTH + , FRVBF_INSN_CST, FRVBF_INSN_CSTBF, FRVBF_INSN_CSTHF, FRVBF_INSN_CSTF + , FRVBF_INSN_CSTD, FRVBF_INSN_CSTDF, FRVBF_INSN_CSTQ, FRVBF_INSN_CSTBU + , FRVBF_INSN_CSTHU, FRVBF_INSN_CSTU, FRVBF_INSN_CSTBFU, FRVBF_INSN_CSTHFU + , FRVBF_INSN_CSTFU, FRVBF_INSN_CSTDU, FRVBF_INSN_CSTDFU, FRVBF_INSN_STBI + , FRVBF_INSN_STHI, FRVBF_INSN_STI, FRVBF_INSN_STBFI, FRVBF_INSN_STHFI + , FRVBF_INSN_STFI, FRVBF_INSN_STDI, FRVBF_INSN_STDFI, FRVBF_INSN_STQI + , FRVBF_INSN_STQFI, FRVBF_INSN_SWAP, FRVBF_INSN_SWAPI, FRVBF_INSN_CSWAP + , FRVBF_INSN_MOVGF, FRVBF_INSN_MOVFG, FRVBF_INSN_MOVGFD, FRVBF_INSN_MOVFGD + , FRVBF_INSN_MOVGFQ, FRVBF_INSN_MOVFGQ, FRVBF_INSN_CMOVGF, FRVBF_INSN_CMOVFG + , FRVBF_INSN_CMOVGFD, FRVBF_INSN_CMOVFGD, FRVBF_INSN_MOVGS, FRVBF_INSN_MOVSG + , FRVBF_INSN_BRA, FRVBF_INSN_BNO, FRVBF_INSN_BEQ, FRVBF_INSN_BNE + , FRVBF_INSN_BLE, FRVBF_INSN_BGT, FRVBF_INSN_BLT, FRVBF_INSN_BGE + , FRVBF_INSN_BLS, FRVBF_INSN_BHI, FRVBF_INSN_BC, FRVBF_INSN_BNC + , FRVBF_INSN_BN, FRVBF_INSN_BP, FRVBF_INSN_BV, FRVBF_INSN_BNV + , FRVBF_INSN_FBRA, FRVBF_INSN_FBNO, FRVBF_INSN_FBNE, FRVBF_INSN_FBEQ + , FRVBF_INSN_FBLG, FRVBF_INSN_FBUE, FRVBF_INSN_FBUL, FRVBF_INSN_FBGE + , FRVBF_INSN_FBLT, FRVBF_INSN_FBUGE, FRVBF_INSN_FBUG, FRVBF_INSN_FBLE + , FRVBF_INSN_FBGT, FRVBF_INSN_FBULE, FRVBF_INSN_FBU, FRVBF_INSN_FBO + , FRVBF_INSN_BCTRLR, FRVBF_INSN_BRALR, FRVBF_INSN_BNOLR, FRVBF_INSN_BEQLR + , FRVBF_INSN_BNELR, FRVBF_INSN_BLELR, FRVBF_INSN_BGTLR, FRVBF_INSN_BLTLR + , FRVBF_INSN_BGELR, FRVBF_INSN_BLSLR, FRVBF_INSN_BHILR, FRVBF_INSN_BCLR + , FRVBF_INSN_BNCLR, FRVBF_INSN_BNLR, FRVBF_INSN_BPLR, FRVBF_INSN_BVLR + , FRVBF_INSN_BNVLR, FRVBF_INSN_FBRALR, FRVBF_INSN_FBNOLR, FRVBF_INSN_FBEQLR + , FRVBF_INSN_FBNELR, FRVBF_INSN_FBLGLR, FRVBF_INSN_FBUELR, FRVBF_INSN_FBULLR + , FRVBF_INSN_FBGELR, FRVBF_INSN_FBLTLR, FRVBF_INSN_FBUGELR, FRVBF_INSN_FBUGLR + , FRVBF_INSN_FBLELR, FRVBF_INSN_FBGTLR, FRVBF_INSN_FBULELR, FRVBF_INSN_FBULR + , FRVBF_INSN_FBOLR, FRVBF_INSN_BCRALR, FRVBF_INSN_BCNOLR, FRVBF_INSN_BCEQLR + , FRVBF_INSN_BCNELR, FRVBF_INSN_BCLELR, FRVBF_INSN_BCGTLR, FRVBF_INSN_BCLTLR + , FRVBF_INSN_BCGELR, FRVBF_INSN_BCLSLR, FRVBF_INSN_BCHILR, FRVBF_INSN_BCCLR + , FRVBF_INSN_BCNCLR, FRVBF_INSN_BCNLR, FRVBF_INSN_BCPLR, FRVBF_INSN_BCVLR + , FRVBF_INSN_BCNVLR, FRVBF_INSN_FCBRALR, FRVBF_INSN_FCBNOLR, FRVBF_INSN_FCBEQLR + , FRVBF_INSN_FCBNELR, FRVBF_INSN_FCBLGLR, FRVBF_INSN_FCBUELR, FRVBF_INSN_FCBULLR + , FRVBF_INSN_FCBGELR, FRVBF_INSN_FCBLTLR, FRVBF_INSN_FCBUGELR, FRVBF_INSN_FCBUGLR + , FRVBF_INSN_FCBLELR, FRVBF_INSN_FCBGTLR, FRVBF_INSN_FCBULELR, FRVBF_INSN_FCBULR + , FRVBF_INSN_FCBOLR, FRVBF_INSN_JMPL, FRVBF_INSN_CALLL, FRVBF_INSN_JMPIL + , FRVBF_INSN_CALLIL, FRVBF_INSN_CALL, FRVBF_INSN_RETT, FRVBF_INSN_REI + , FRVBF_INSN_TRA, FRVBF_INSN_TNO, FRVBF_INSN_TEQ, FRVBF_INSN_TNE + , FRVBF_INSN_TLE, FRVBF_INSN_TGT, FRVBF_INSN_TLT, FRVBF_INSN_TGE + , FRVBF_INSN_TLS, FRVBF_INSN_THI, FRVBF_INSN_TC, FRVBF_INSN_TNC + , FRVBF_INSN_TN, FRVBF_INSN_TP, FRVBF_INSN_TV, FRVBF_INSN_TNV + , FRVBF_INSN_FTRA, FRVBF_INSN_FTNO, FRVBF_INSN_FTNE, FRVBF_INSN_FTEQ + , FRVBF_INSN_FTLG, FRVBF_INSN_FTUE, FRVBF_INSN_FTUL, FRVBF_INSN_FTGE + , FRVBF_INSN_FTLT, FRVBF_INSN_FTUGE, FRVBF_INSN_FTUG, FRVBF_INSN_FTLE + , FRVBF_INSN_FTGT, FRVBF_INSN_FTULE, FRVBF_INSN_FTU, FRVBF_INSN_FTO + , FRVBF_INSN_TIRA, FRVBF_INSN_TINO, FRVBF_INSN_TIEQ, FRVBF_INSN_TINE + , FRVBF_INSN_TILE, FRVBF_INSN_TIGT, FRVBF_INSN_TILT, FRVBF_INSN_TIGE + , FRVBF_INSN_TILS, FRVBF_INSN_TIHI, FRVBF_INSN_TIC, FRVBF_INSN_TINC + , FRVBF_INSN_TIN, FRVBF_INSN_TIP, FRVBF_INSN_TIV, FRVBF_INSN_TINV + , FRVBF_INSN_FTIRA, FRVBF_INSN_FTINO, FRVBF_INSN_FTINE, FRVBF_INSN_FTIEQ + , FRVBF_INSN_FTILG, FRVBF_INSN_FTIUE, FRVBF_INSN_FTIUL, FRVBF_INSN_FTIGE + , FRVBF_INSN_FTILT, FRVBF_INSN_FTIUGE, FRVBF_INSN_FTIUG, FRVBF_INSN_FTILE + , FRVBF_INSN_FTIGT, FRVBF_INSN_FTIULE, FRVBF_INSN_FTIU, FRVBF_INSN_FTIO + , FRVBF_INSN_BREAK, FRVBF_INSN_MTRAP, FRVBF_INSN_ANDCR, FRVBF_INSN_ORCR + , FRVBF_INSN_XORCR, FRVBF_INSN_NANDCR, FRVBF_INSN_NORCR, FRVBF_INSN_ANDNCR + , FRVBF_INSN_ORNCR, FRVBF_INSN_NANDNCR, FRVBF_INSN_NORNCR, FRVBF_INSN_NOTCR + , FRVBF_INSN_CKRA, FRVBF_INSN_CKNO, FRVBF_INSN_CKEQ, FRVBF_INSN_CKNE + , FRVBF_INSN_CKLE, FRVBF_INSN_CKGT, FRVBF_INSN_CKLT, FRVBF_INSN_CKGE + , FRVBF_INSN_CKLS, FRVBF_INSN_CKHI, FRVBF_INSN_CKC, FRVBF_INSN_CKNC + , FRVBF_INSN_CKN, FRVBF_INSN_CKP, FRVBF_INSN_CKV, FRVBF_INSN_CKNV + , FRVBF_INSN_FCKRA, FRVBF_INSN_FCKNO, FRVBF_INSN_FCKNE, FRVBF_INSN_FCKEQ + , FRVBF_INSN_FCKLG, FRVBF_INSN_FCKUE, FRVBF_INSN_FCKUL, FRVBF_INSN_FCKGE + , FRVBF_INSN_FCKLT, FRVBF_INSN_FCKUGE, FRVBF_INSN_FCKUG, FRVBF_INSN_FCKLE + , FRVBF_INSN_FCKGT, FRVBF_INSN_FCKULE, FRVBF_INSN_FCKU, FRVBF_INSN_FCKO + , FRVBF_INSN_CCKRA, FRVBF_INSN_CCKNO, FRVBF_INSN_CCKEQ, FRVBF_INSN_CCKNE + , FRVBF_INSN_CCKLE, FRVBF_INSN_CCKGT, FRVBF_INSN_CCKLT, FRVBF_INSN_CCKGE + , FRVBF_INSN_CCKLS, FRVBF_INSN_CCKHI, FRVBF_INSN_CCKC, FRVBF_INSN_CCKNC + , FRVBF_INSN_CCKN, FRVBF_INSN_CCKP, FRVBF_INSN_CCKV, FRVBF_INSN_CCKNV + , FRVBF_INSN_CFCKRA, FRVBF_INSN_CFCKNO, FRVBF_INSN_CFCKNE, FRVBF_INSN_CFCKEQ + , FRVBF_INSN_CFCKLG, FRVBF_INSN_CFCKUE, FRVBF_INSN_CFCKUL, FRVBF_INSN_CFCKGE + , FRVBF_INSN_CFCKLT, FRVBF_INSN_CFCKUGE, FRVBF_INSN_CFCKUG, FRVBF_INSN_CFCKLE + , FRVBF_INSN_CFCKGT, FRVBF_INSN_CFCKULE, FRVBF_INSN_CFCKU, FRVBF_INSN_CFCKO + , FRVBF_INSN_CJMPL, FRVBF_INSN_CCALLL, FRVBF_INSN_ICI, FRVBF_INSN_DCI + , FRVBF_INSN_ICEI, FRVBF_INSN_DCEI, FRVBF_INSN_DCF, FRVBF_INSN_DCEF + , FRVBF_INSN_WITLB, FRVBF_INSN_WDTLB, FRVBF_INSN_ITLBI, FRVBF_INSN_DTLBI + , FRVBF_INSN_ICPL, FRVBF_INSN_DCPL, FRVBF_INSN_ICUL, FRVBF_INSN_DCUL + , FRVBF_INSN_BAR, FRVBF_INSN_MEMBAR, FRVBF_INSN_COP1, FRVBF_INSN_COP2 + , FRVBF_INSN_CLRGR, FRVBF_INSN_CLRFR, FRVBF_INSN_CLRGA, FRVBF_INSN_CLRFA + , FRVBF_INSN_COMMITGR, FRVBF_INSN_COMMITFR, FRVBF_INSN_COMMITGA, FRVBF_INSN_COMMITFA + , FRVBF_INSN_FITOS, FRVBF_INSN_FSTOI, FRVBF_INSN_FITOD, FRVBF_INSN_FDTOI + , FRVBF_INSN_FDITOS, FRVBF_INSN_FDSTOI, FRVBF_INSN_NFDITOS, FRVBF_INSN_NFDSTOI + , FRVBF_INSN_CFITOS, FRVBF_INSN_CFSTOI, FRVBF_INSN_NFITOS, FRVBF_INSN_NFSTOI + , FRVBF_INSN_FMOVS, FRVBF_INSN_FMOVD, FRVBF_INSN_FDMOVS, FRVBF_INSN_CFMOVS + , FRVBF_INSN_FNEGS, FRVBF_INSN_FNEGD, FRVBF_INSN_FDNEGS, FRVBF_INSN_CFNEGS + , FRVBF_INSN_FABSS, FRVBF_INSN_FABSD, FRVBF_INSN_FDABSS, FRVBF_INSN_CFABSS + , FRVBF_INSN_FSQRTS, FRVBF_INSN_FDSQRTS, FRVBF_INSN_NFDSQRTS, FRVBF_INSN_FSQRTD + , FRVBF_INSN_CFSQRTS, FRVBF_INSN_NFSQRTS, FRVBF_INSN_FADDS, FRVBF_INSN_FSUBS + , FRVBF_INSN_FMULS, FRVBF_INSN_FDIVS, FRVBF_INSN_FADDD, FRVBF_INSN_FSUBD + , FRVBF_INSN_FMULD, FRVBF_INSN_FDIVD, FRVBF_INSN_CFADDS, FRVBF_INSN_CFSUBS + , FRVBF_INSN_CFMULS, FRVBF_INSN_CFDIVS, FRVBF_INSN_NFADDS, FRVBF_INSN_NFSUBS + , FRVBF_INSN_NFMULS, FRVBF_INSN_NFDIVS, FRVBF_INSN_FCMPS, FRVBF_INSN_FCMPD + , FRVBF_INSN_CFCMPS, FRVBF_INSN_FDCMPS, FRVBF_INSN_FMADDS, FRVBF_INSN_FMSUBS + , FRVBF_INSN_FMADDD, FRVBF_INSN_FMSUBD, FRVBF_INSN_FDMADDS, FRVBF_INSN_NFDMADDS + , FRVBF_INSN_CFMADDS, FRVBF_INSN_CFMSUBS, FRVBF_INSN_NFMADDS, FRVBF_INSN_NFMSUBS + , FRVBF_INSN_FMAS, FRVBF_INSN_FMSS, FRVBF_INSN_FDMAS, FRVBF_INSN_FDMSS + , FRVBF_INSN_NFDMAS, FRVBF_INSN_NFDMSS, FRVBF_INSN_CFMAS, FRVBF_INSN_CFMSS + , FRVBF_INSN_FMAD, FRVBF_INSN_FMSD, FRVBF_INSN_NFMAS, FRVBF_INSN_NFMSS + , FRVBF_INSN_FDADDS, FRVBF_INSN_FDSUBS, FRVBF_INSN_FDMULS, FRVBF_INSN_FDDIVS + , FRVBF_INSN_FDSADS, FRVBF_INSN_FDMULCS, FRVBF_INSN_NFDMULCS, FRVBF_INSN_NFDADDS + , FRVBF_INSN_NFDSUBS, FRVBF_INSN_NFDMULS, FRVBF_INSN_NFDDIVS, FRVBF_INSN_NFDSADS + , FRVBF_INSN_NFDCMPS, FRVBF_INSN_MHSETLOS, FRVBF_INSN_MHSETHIS, FRVBF_INSN_MHDSETS + , FRVBF_INSN_MHSETLOH, FRVBF_INSN_MHSETHIH, FRVBF_INSN_MHDSETH, FRVBF_INSN_MAND + , FRVBF_INSN_MOR, FRVBF_INSN_MXOR, FRVBF_INSN_CMAND, FRVBF_INSN_CMOR + , FRVBF_INSN_CMXOR, FRVBF_INSN_MNOT, FRVBF_INSN_CMNOT, FRVBF_INSN_MROTLI + , FRVBF_INSN_MROTRI, FRVBF_INSN_MWCUT, FRVBF_INSN_MWCUTI, FRVBF_INSN_MCUT + , FRVBF_INSN_MCUTI, FRVBF_INSN_MCUTSS, FRVBF_INSN_MCUTSSI, FRVBF_INSN_MDCUTSSI + , FRVBF_INSN_MAVEH, FRVBF_INSN_MSLLHI, FRVBF_INSN_MSRLHI, FRVBF_INSN_MSRAHI + , FRVBF_INSN_MDROTLI, FRVBF_INSN_MCPLHI, FRVBF_INSN_MCPLI, FRVBF_INSN_MSATHS + , FRVBF_INSN_MQSATHS, FRVBF_INSN_MSATHU, FRVBF_INSN_MCMPSH, FRVBF_INSN_MCMPUH + , FRVBF_INSN_MABSHS, FRVBF_INSN_MADDHSS, FRVBF_INSN_MADDHUS, FRVBF_INSN_MSUBHSS + , FRVBF_INSN_MSUBHUS, FRVBF_INSN_CMADDHSS, FRVBF_INSN_CMADDHUS, FRVBF_INSN_CMSUBHSS + , FRVBF_INSN_CMSUBHUS, FRVBF_INSN_MQADDHSS, FRVBF_INSN_MQADDHUS, FRVBF_INSN_MQSUBHSS + , FRVBF_INSN_MQSUBHUS, FRVBF_INSN_CMQADDHSS, FRVBF_INSN_CMQADDHUS, FRVBF_INSN_CMQSUBHSS + , FRVBF_INSN_CMQSUBHUS, FRVBF_INSN_MADDACCS, FRVBF_INSN_MSUBACCS, FRVBF_INSN_MDADDACCS + , FRVBF_INSN_MDSUBACCS, FRVBF_INSN_MASACCS, FRVBF_INSN_MDASACCS, FRVBF_INSN_MMULHS + , FRVBF_INSN_MMULHU, FRVBF_INSN_MMULXHS, FRVBF_INSN_MMULXHU, FRVBF_INSN_CMMULHS + , FRVBF_INSN_CMMULHU, FRVBF_INSN_MQMULHS, FRVBF_INSN_MQMULHU, FRVBF_INSN_MQMULXHS + , FRVBF_INSN_MQMULXHU, FRVBF_INSN_CMQMULHS, FRVBF_INSN_CMQMULHU, FRVBF_INSN_MMACHS + , FRVBF_INSN_MMACHU, FRVBF_INSN_MMRDHS, FRVBF_INSN_MMRDHU, FRVBF_INSN_CMMACHS + , FRVBF_INSN_CMMACHU, FRVBF_INSN_MQMACHS, FRVBF_INSN_MQMACHU, FRVBF_INSN_CMQMACHS + , FRVBF_INSN_CMQMACHU, FRVBF_INSN_MQXMACHS, FRVBF_INSN_MQXMACXHS, FRVBF_INSN_MQMACXHS + , FRVBF_INSN_MCPXRS, FRVBF_INSN_MCPXRU, FRVBF_INSN_MCPXIS, FRVBF_INSN_MCPXIU + , FRVBF_INSN_CMCPXRS, FRVBF_INSN_CMCPXRU, FRVBF_INSN_CMCPXIS, FRVBF_INSN_CMCPXIU + , FRVBF_INSN_MQCPXRS, FRVBF_INSN_MQCPXRU, FRVBF_INSN_MQCPXIS, FRVBF_INSN_MQCPXIU + , FRVBF_INSN_MEXPDHW, FRVBF_INSN_CMEXPDHW, FRVBF_INSN_MEXPDHD, FRVBF_INSN_CMEXPDHD + , FRVBF_INSN_MPACKH, FRVBF_INSN_MDPACKH, FRVBF_INSN_MUNPACKH, FRVBF_INSN_MDUNPACKH + , FRVBF_INSN_MBTOH, FRVBF_INSN_CMBTOH, FRVBF_INSN_MHTOB, FRVBF_INSN_CMHTOB + , FRVBF_INSN_MBTOHE, FRVBF_INSN_CMBTOHE, FRVBF_INSN_MNOP, FRVBF_INSN_MCLRACC_0 + , FRVBF_INSN_MCLRACC_1, FRVBF_INSN_MRDACC, FRVBF_INSN_MRDACCG, FRVBF_INSN_MWTACC + , FRVBF_INSN_MWTACCG, FRVBF_INSN_MCOP1, FRVBF_INSN_MCOP2, FRVBF_INSN_FNOP + , FRVBF_INSN__MAX +} FRVBF_INSN_TYPE; + +/* Enum declaration for semantic formats in cpu family frvbf. */ +typedef enum frvbf_sfmt_type { + FRVBF_SFMT_EMPTY, FRVBF_SFMT_ADD, FRVBF_SFMT_NOT, FRVBF_SFMT_SDIV + , FRVBF_SFMT_SMUL, FRVBF_SFMT_SMU, FRVBF_SFMT_SMASS, FRVBF_SFMT_SCUTSS + , FRVBF_SFMT_CADD, FRVBF_SFMT_CNOT, FRVBF_SFMT_CSMUL, FRVBF_SFMT_CSDIV + , FRVBF_SFMT_ADDCC, FRVBF_SFMT_ANDCC, FRVBF_SFMT_SMULCC, FRVBF_SFMT_CADDCC + , FRVBF_SFMT_CSMULCC, FRVBF_SFMT_ADDX, FRVBF_SFMT_ADDI, FRVBF_SFMT_SDIVI + , FRVBF_SFMT_SMULI, FRVBF_SFMT_ADDICC, FRVBF_SFMT_ANDICC, FRVBF_SFMT_SMULICC + , FRVBF_SFMT_ADDXI, FRVBF_SFMT_CMPB, FRVBF_SFMT_SETLO, FRVBF_SFMT_SETHI + , FRVBF_SFMT_SETLOS, FRVBF_SFMT_LDSB, FRVBF_SFMT_LDBF, FRVBF_SFMT_LDC + , FRVBF_SFMT_NLDSB, FRVBF_SFMT_NLDBF, FRVBF_SFMT_LDD, FRVBF_SFMT_LDDF + , FRVBF_SFMT_LDDC, FRVBF_SFMT_NLDD, FRVBF_SFMT_NLDDF, FRVBF_SFMT_LDQ + , FRVBF_SFMT_LDQF, FRVBF_SFMT_LDQC, FRVBF_SFMT_NLDQ, FRVBF_SFMT_NLDQF + , FRVBF_SFMT_LDSBU, FRVBF_SFMT_NLDSBU, FRVBF_SFMT_LDBFU, FRVBF_SFMT_LDCU + , FRVBF_SFMT_NLDBFU, FRVBF_SFMT_LDDU, FRVBF_SFMT_NLDDU, FRVBF_SFMT_LDDFU + , FRVBF_SFMT_LDDCU, FRVBF_SFMT_NLDDFU, FRVBF_SFMT_LDQU, FRVBF_SFMT_NLDQU + , FRVBF_SFMT_LDQFU, FRVBF_SFMT_LDQCU, FRVBF_SFMT_NLDQFU, FRVBF_SFMT_LDSBI + , FRVBF_SFMT_LDBFI, FRVBF_SFMT_NLDSBI, FRVBF_SFMT_NLDBFI, FRVBF_SFMT_LDDI + , FRVBF_SFMT_LDDFI, FRVBF_SFMT_NLDDI, FRVBF_SFMT_NLDDFI, FRVBF_SFMT_LDQI + , FRVBF_SFMT_LDQFI, FRVBF_SFMT_NLDQFI, FRVBF_SFMT_STB, FRVBF_SFMT_STBF + , FRVBF_SFMT_STC, FRVBF_SFMT_RSTB, FRVBF_SFMT_RSTBF, FRVBF_SFMT_STD + , FRVBF_SFMT_STDF, FRVBF_SFMT_STDC, FRVBF_SFMT_RSTD, FRVBF_SFMT_RSTDF + , FRVBF_SFMT_STBU, FRVBF_SFMT_STBFU, FRVBF_SFMT_STCU, FRVBF_SFMT_STDU + , FRVBF_SFMT_STDFU, FRVBF_SFMT_STDCU, FRVBF_SFMT_STQU, FRVBF_SFMT_CLDSB + , FRVBF_SFMT_CLDBF, FRVBF_SFMT_CLDD, FRVBF_SFMT_CLDDF, FRVBF_SFMT_CLDQ + , FRVBF_SFMT_CLDSBU, FRVBF_SFMT_CLDBFU, FRVBF_SFMT_CLDDU, FRVBF_SFMT_CLDDFU + , FRVBF_SFMT_CLDQU, FRVBF_SFMT_CSTB, FRVBF_SFMT_CSTBF, FRVBF_SFMT_CSTD + , FRVBF_SFMT_CSTDF, FRVBF_SFMT_CSTBU, FRVBF_SFMT_CSTBFU, FRVBF_SFMT_CSTDU + , FRVBF_SFMT_CSTDFU, FRVBF_SFMT_STBI, FRVBF_SFMT_STBFI, FRVBF_SFMT_STDI + , FRVBF_SFMT_STDFI, FRVBF_SFMT_SWAP, FRVBF_SFMT_SWAPI, FRVBF_SFMT_CSWAP + , FRVBF_SFMT_MOVGF, FRVBF_SFMT_MOVFG, FRVBF_SFMT_MOVGFD, FRVBF_SFMT_MOVFGD + , FRVBF_SFMT_MOVGFQ, FRVBF_SFMT_MOVFGQ, FRVBF_SFMT_CMOVGF, FRVBF_SFMT_CMOVFG + , FRVBF_SFMT_CMOVGFD, FRVBF_SFMT_CMOVFGD, FRVBF_SFMT_MOVGS, FRVBF_SFMT_MOVSG + , FRVBF_SFMT_BRA, FRVBF_SFMT_BNO, FRVBF_SFMT_BEQ, FRVBF_SFMT_FBNE + , FRVBF_SFMT_BCTRLR, FRVBF_SFMT_BRALR, FRVBF_SFMT_BNOLR, FRVBF_SFMT_BEQLR + , FRVBF_SFMT_FBEQLR, FRVBF_SFMT_BCRALR, FRVBF_SFMT_BCNOLR, FRVBF_SFMT_BCEQLR + , FRVBF_SFMT_FCBEQLR, FRVBF_SFMT_JMPL, FRVBF_SFMT_JMPIL, FRVBF_SFMT_CALL + , FRVBF_SFMT_RETT, FRVBF_SFMT_REI, FRVBF_SFMT_TRA, FRVBF_SFMT_TEQ + , FRVBF_SFMT_FTNE, FRVBF_SFMT_TIRA, FRVBF_SFMT_TIEQ, FRVBF_SFMT_FTINE + , FRVBF_SFMT_BREAK, FRVBF_SFMT_ANDCR, FRVBF_SFMT_NOTCR, FRVBF_SFMT_CKRA + , FRVBF_SFMT_CKEQ, FRVBF_SFMT_FCKRA, FRVBF_SFMT_FCKNE, FRVBF_SFMT_CCKRA + , FRVBF_SFMT_CCKEQ, FRVBF_SFMT_CFCKRA, FRVBF_SFMT_CFCKNE, FRVBF_SFMT_CJMPL + , FRVBF_SFMT_ICI, FRVBF_SFMT_ICEI, FRVBF_SFMT_ICPL, FRVBF_SFMT_ICUL + , FRVBF_SFMT_CLRGR, FRVBF_SFMT_CLRFR, FRVBF_SFMT_COMMITGR, FRVBF_SFMT_COMMITFR + , FRVBF_SFMT_FITOS, FRVBF_SFMT_FSTOI, FRVBF_SFMT_FITOD, FRVBF_SFMT_FDTOI + , FRVBF_SFMT_FDITOS, FRVBF_SFMT_FDSTOI, FRVBF_SFMT_CFITOS, FRVBF_SFMT_CFSTOI + , FRVBF_SFMT_NFITOS, FRVBF_SFMT_NFSTOI, FRVBF_SFMT_FMOVS, FRVBF_SFMT_FMOVD + , FRVBF_SFMT_FDMOVS, FRVBF_SFMT_CFMOVS, FRVBF_SFMT_NFSQRTS, FRVBF_SFMT_FADDS + , FRVBF_SFMT_FADDD, FRVBF_SFMT_CFADDS, FRVBF_SFMT_NFADDS, FRVBF_SFMT_FCMPS + , FRVBF_SFMT_FCMPD, FRVBF_SFMT_CFCMPS, FRVBF_SFMT_FDCMPS, FRVBF_SFMT_FMADDS + , FRVBF_SFMT_FMADDD, FRVBF_SFMT_FDMADDS, FRVBF_SFMT_CFMADDS, FRVBF_SFMT_NFMADDS + , FRVBF_SFMT_FMAS, FRVBF_SFMT_FDMAS, FRVBF_SFMT_CFMAS, FRVBF_SFMT_NFDCMPS + , FRVBF_SFMT_MHSETLOS, FRVBF_SFMT_MHSETHIS, FRVBF_SFMT_MHDSETS, FRVBF_SFMT_MHSETLOH + , FRVBF_SFMT_MHSETHIH, FRVBF_SFMT_MHDSETH, FRVBF_SFMT_MAND, FRVBF_SFMT_CMAND + , FRVBF_SFMT_MNOT, FRVBF_SFMT_CMNOT, FRVBF_SFMT_MROTLI, FRVBF_SFMT_MWCUT + , FRVBF_SFMT_MWCUTI, FRVBF_SFMT_MCUT, FRVBF_SFMT_MCUTI, FRVBF_SFMT_MDCUTSSI + , FRVBF_SFMT_MSLLHI, FRVBF_SFMT_MDROTLI, FRVBF_SFMT_MCPLHI, FRVBF_SFMT_MCPLI + , FRVBF_SFMT_MSATHS, FRVBF_SFMT_MQSATHS, FRVBF_SFMT_MCMPSH, FRVBF_SFMT_MABSHS + , FRVBF_SFMT_CMADDHSS, FRVBF_SFMT_CMQADDHSS, FRVBF_SFMT_MADDACCS, FRVBF_SFMT_MDADDACCS + , FRVBF_SFMT_MASACCS, FRVBF_SFMT_MDASACCS, FRVBF_SFMT_MMULHS, FRVBF_SFMT_CMMULHS + , FRVBF_SFMT_MQMULHS, FRVBF_SFMT_CMQMULHS, FRVBF_SFMT_MMACHS, FRVBF_SFMT_MMACHU + , FRVBF_SFMT_CMMACHS, FRVBF_SFMT_CMMACHU, FRVBF_SFMT_MQMACHS, FRVBF_SFMT_MQMACHU + , FRVBF_SFMT_CMQMACHS, FRVBF_SFMT_CMQMACHU, FRVBF_SFMT_MCPXRS, FRVBF_SFMT_CMCPXRS + , FRVBF_SFMT_MQCPXRS, FRVBF_SFMT_MEXPDHW, FRVBF_SFMT_CMEXPDHW, FRVBF_SFMT_MEXPDHD + , FRVBF_SFMT_CMEXPDHD, FRVBF_SFMT_MPACKH, FRVBF_SFMT_MDPACKH, FRVBF_SFMT_MUNPACKH + , FRVBF_SFMT_MDUNPACKH, FRVBF_SFMT_MBTOH, FRVBF_SFMT_CMBTOH, FRVBF_SFMT_MHTOB + , FRVBF_SFMT_CMHTOB, FRVBF_SFMT_MBTOHE, FRVBF_SFMT_CMBTOHE, FRVBF_SFMT_MCLRACC_0 + , FRVBF_SFMT_MRDACC, FRVBF_SFMT_MRDACCG, FRVBF_SFMT_MWTACC, FRVBF_SFMT_MWTACCG +} FRVBF_SFMT_TYPE; + +/* Function unit handlers (user written). */ + +extern int frvbf_model_frv_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int frvbf_model_fr550_u_media_4_quad (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRintieven*/, INT /*FRintjeven*/, INT /*ACC40Sk*/, INT /*ACC40Uk*/); +extern int frvbf_model_fr550_u_media_4_add_sub_dual (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*ACC40Si*/, INT /*ACC40Sk*/); +extern int frvbf_model_fr550_u_media_4_add_sub (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*ACC40Si*/, INT /*ACC40Sk*/); +extern int frvbf_model_fr550_u_media_4_acc_dual (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*ACC40Si*/, INT /*ACC40Sk*/); +extern int frvbf_model_fr550_u_media_4_acc (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*ACC40Si*/, INT /*ACC40Sk*/); +extern int frvbf_model_fr550_u_media_4 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRinti*/, INT /*FRintj*/, INT /*ACC40Sk*/, INT /*ACC40Uk*/); +extern int frvbf_model_fr550_u_media_set (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRintk*/); +extern int frvbf_model_fr550_u_media_3_mclracc (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int frvbf_model_fr550_u_media_3_wtacc (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRinti*/, INT /*ACC40Sk*/); +extern int frvbf_model_fr550_u_media_3_acc_dual (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*ACC40Si*/, INT /*FRintkeven*/); +extern int frvbf_model_fr550_u_media_3_acc (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRintj*/, INT /*ACC40Si*/, INT /*FRintk*/); +extern int frvbf_model_fr550_u_media_3_dual (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRinti*/, INT /*FRintk*/); +extern int frvbf_model_fr550_u_media_dual_expand (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRinti*/, INT /*FRintkeven*/); +extern int frvbf_model_fr550_u_media_quad (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRintieven*/, INT /*FRintjeven*/, INT /*FRintkeven*/); +extern int frvbf_model_fr550_u_media (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRinti*/, INT /*FRintj*/, INT /*FRintk*/); +extern int frvbf_model_fr550_u_float_convert (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRj*/, INT /*FRintj*/, INT /*FRdoublej*/, INT /*FRk*/, INT /*FRintk*/, INT /*FRdoublek*/); +extern int frvbf_model_fr550_u_commit (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRk*/, INT /*FRk*/); +extern int frvbf_model_fr550_u_dcul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/); +extern int frvbf_model_fr550_u_icul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/); +extern int frvbf_model_fr550_u_dcpl (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/); +extern int frvbf_model_fr550_u_icpl (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/); +extern int frvbf_model_fr550_u_dcf (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/); +extern int frvbf_model_fr550_u_dci (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/); +extern int frvbf_model_fr550_u_ici (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/); +extern int frvbf_model_fr550_u_clrfr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRk*/); +extern int frvbf_model_fr550_u_clrgr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRk*/); +extern int frvbf_model_fr550_u_fr2fr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRi*/, INT /*FRk*/); +extern int frvbf_model_fr550_u_swap (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*GRk*/); +extern int frvbf_model_fr550_u_fr_store (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*FRintk*/, INT /*FRdoublek*/); +extern int frvbf_model_fr550_u_fr_load (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*FRintk*/, INT /*FRdoublek*/); +extern int frvbf_model_fr550_u_gr_store (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*GRk*/, INT /*GRdoublek*/); +extern int frvbf_model_fr550_u_gr_load (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*GRk*/, INT /*GRdoublek*/); +extern int frvbf_model_fr550_u_set_hilo (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRkhi*/, INT /*GRklo*/); +extern int frvbf_model_fr550_u_gr2spr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRj*/, INT /*spr*/); +extern int frvbf_model_fr550_u_spr2gr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*spr*/, INT /*GRj*/); +extern int frvbf_model_fr550_u_gr2fr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRj*/, INT /*FRintk*/); +extern int frvbf_model_fr550_u_fr2gr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRintk*/, INT /*GRj*/); +extern int frvbf_model_fr550_u_float_dual_compare (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRi*/, INT /*FRj*/, INT /*FCCi_2*/); +extern int frvbf_model_fr550_u_float_compare (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRi*/, INT /*FRj*/, INT /*FRdoublei*/, INT /*FRdoublej*/, INT /*FCCi_2*/); +extern int frvbf_model_fr550_u_float_sqrt (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRj*/, INT /*FRdoublej*/, INT /*FRk*/, INT /*FRdoublek*/); +extern int frvbf_model_fr550_u_float_div (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRi*/, INT /*FRj*/, INT /*FRk*/); +extern int frvbf_model_fr550_u_float_dual_arith (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRi*/, INT /*FRj*/, INT /*FRdoublei*/, INT /*FRdoublej*/, INT /*FRk*/, INT /*FRdoublek*/); +extern int frvbf_model_fr550_u_float_arith (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRi*/, INT /*FRj*/, INT /*FRdoublei*/, INT /*FRdoublej*/, INT /*FRk*/, INT /*FRdoublek*/); +extern int frvbf_model_fr550_u_check (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*ICCi_3*/, INT /*FCCi_3*/); +extern int frvbf_model_fr550_u_trap (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*ICCi_2*/, INT /*FCCi_2*/); +extern int frvbf_model_fr550_u_branch (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*ICCi_2*/, INT /*FCCi_2*/); +extern int frvbf_model_fr550_u_idiv (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*GRk*/, INT /*ICCi_1*/); +extern int frvbf_model_fr550_u_imul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*GRdoublek*/, INT /*ICCi_1*/); +extern int frvbf_model_fr550_u_integer (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*GRk*/, INT /*ICCi_1*/); +extern int frvbf_model_fr550_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int frvbf_model_fr500_u_commit (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRk*/, INT /*FRk*/); +extern int frvbf_model_fr500_u_dcul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/); +extern int frvbf_model_fr500_u_icul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/); +extern int frvbf_model_fr500_u_dcpl (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/); +extern int frvbf_model_fr500_u_icpl (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/); +extern int frvbf_model_fr500_u_dcf (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/); +extern int frvbf_model_fr500_u_dci (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/); +extern int frvbf_model_fr500_u_ici (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/); +extern int frvbf_model_fr500_u_membar (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int frvbf_model_fr500_u_barrier (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int frvbf_model_fr500_u_media_dual_btohe (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRintj*/, INT /*FRintk*/); +extern int frvbf_model_fr500_u_media_dual_htob (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRintj*/, INT /*FRintk*/); +extern int frvbf_model_fr500_u_media_dual_btoh (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRintj*/, INT /*FRintk*/); +extern int frvbf_model_fr500_u_media_dual_unpack (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRinti*/, INT /*FRintk*/); +extern int frvbf_model_fr500_u_media_dual_expand (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRinti*/, INT /*FRintk*/); +extern int frvbf_model_fr500_u_media_quad_complex (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRinti*/, INT /*FRintj*/, INT /*ACC40Sk*/); +extern int frvbf_model_fr500_u_media_quad_mul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRinti*/, INT /*FRintj*/, INT /*ACC40Sk*/, INT /*ACC40Uk*/); +extern int frvbf_model_fr500_u_media_dual_mul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRinti*/, INT /*FRintj*/, INT /*ACC40Sk*/, INT /*ACC40Uk*/); +extern int frvbf_model_fr500_u_media_quad_arith (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRinti*/, INT /*FRintj*/, INT /*FRintk*/); +extern int frvbf_model_fr500_u_media (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRinti*/, INT /*FRintj*/, INT /*ACC40Si*/, INT /*ACCGi*/, INT /*FRintk*/, INT /*ACC40Sk*/, INT /*ACC40Uk*/, INT /*ACCGk*/); +extern int frvbf_model_fr500_u_float_dual_convert (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRj*/, INT /*FRintj*/, INT /*FRk*/, INT /*FRintk*/); +extern int frvbf_model_fr500_u_float_convert (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRj*/, INT /*FRintj*/, INT /*FRdoublej*/, INT /*FRk*/, INT /*FRintk*/, INT /*FRdoublek*/); +extern int frvbf_model_fr500_u_float_dual_compare (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRi*/, INT /*FRj*/, INT /*FCCi_2*/); +extern int frvbf_model_fr500_u_float_compare (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRi*/, INT /*FRj*/, INT /*FRdoublei*/, INT /*FRdoublej*/, INT /*FCCi_2*/); +extern int frvbf_model_fr500_u_float_dual_sqrt (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRj*/, INT /*FRk*/); +extern int frvbf_model_fr500_u_float_sqrt (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRj*/, INT /*FRdoublej*/, INT /*FRk*/, INT /*FRdoublek*/); +extern int frvbf_model_fr500_u_float_div (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRi*/, INT /*FRj*/, INT /*FRk*/); +extern int frvbf_model_fr500_u_float_dual_arith (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRi*/, INT /*FRj*/, INT /*FRdoublei*/, INT /*FRdoublej*/, INT /*FRk*/, INT /*FRdoublek*/); +extern int frvbf_model_fr500_u_float_arith (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRi*/, INT /*FRj*/, INT /*FRdoublei*/, INT /*FRdoublej*/, INT /*FRk*/, INT /*FRdoublek*/); +extern int frvbf_model_fr500_u_gr2spr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRj*/, INT /*spr*/); +extern int frvbf_model_fr500_u_gr2fr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRj*/, INT /*FRintk*/); +extern int frvbf_model_fr500_u_spr2gr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*spr*/, INT /*GRj*/); +extern int frvbf_model_fr500_u_fr2gr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRintk*/, INT /*GRj*/); +extern int frvbf_model_fr500_u_fr2fr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRi*/, INT /*FRk*/); +extern int frvbf_model_fr500_u_swap (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*GRk*/); +extern int frvbf_model_fr500_u_fr_r_store (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*FRintk*/, INT /*FRdoublek*/); +extern int frvbf_model_fr500_u_fr_store (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*FRintk*/, INT /*FRdoublek*/); +extern int frvbf_model_fr500_u_fr_load (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*FRintk*/, INT /*FRdoublek*/); +extern int frvbf_model_fr500_u_gr_r_store (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*GRk*/, INT /*GRdoublek*/); +extern int frvbf_model_fr500_u_gr_store (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*GRk*/, INT /*GRdoublek*/); +extern int frvbf_model_fr500_u_gr_load (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*GRk*/, INT /*GRdoublek*/); +extern int frvbf_model_fr500_u_set_hilo (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRkhi*/, INT /*GRklo*/); +extern int frvbf_model_fr500_u_clrfr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRk*/); +extern int frvbf_model_fr500_u_clrgr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRk*/); +extern int frvbf_model_fr500_u_check (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*ICCi_3*/, INT /*FCCi_3*/); +extern int frvbf_model_fr500_u_trap (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*ICCi_2*/, INT /*FCCi_2*/); +extern int frvbf_model_fr500_u_branch (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*ICCi_2*/, INT /*FCCi_2*/); +extern int frvbf_model_fr500_u_idiv (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*GRk*/, INT /*ICCi_1*/); +extern int frvbf_model_fr500_u_imul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*GRdoublek*/, INT /*ICCi_1*/); +extern int frvbf_model_fr500_u_integer (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*GRk*/, INT /*ICCi_1*/); +extern int frvbf_model_fr500_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int frvbf_model_tomcat_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int frvbf_model_fr400_u_dcul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/); +extern int frvbf_model_fr400_u_icul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/); +extern int frvbf_model_fr400_u_dcpl (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/); +extern int frvbf_model_fr400_u_icpl (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/); +extern int frvbf_model_fr400_u_dcf (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/); +extern int frvbf_model_fr400_u_dci (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/); +extern int frvbf_model_fr400_u_ici (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/); +extern int frvbf_model_fr400_u_membar (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int frvbf_model_fr400_u_barrier (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int frvbf_model_fr400_u_media_dual_htob (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRintj*/, INT /*FRintk*/); +extern int frvbf_model_fr400_u_media_dual_expand (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRinti*/, INT /*FRintk*/); +extern int frvbf_model_fr400_u_media_7 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRinti*/, INT /*FRintj*/, INT /*FCCk*/); +extern int frvbf_model_fr400_u_media_6 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRinti*/, INT /*FRintk*/); +extern int frvbf_model_fr400_u_media_4_acc_dual (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*ACC40Si*/, INT /*FRintk*/); +extern int frvbf_model_fr400_u_media_4_accg (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*ACCGi*/, INT /*FRinti*/, INT /*ACCGk*/, INT /*FRintk*/); +extern int frvbf_model_fr400_u_media_4 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*ACC40Si*/, INT /*FRintj*/, INT /*ACC40Sk*/, INT /*FRintk*/); +extern int frvbf_model_fr400_u_media_3_quad (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRinti*/, INT /*FRintj*/, INT /*FRintk*/); +extern int frvbf_model_fr400_u_media_3_dual (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRinti*/, INT /*FRintk*/); +extern int frvbf_model_fr400_u_media_3 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRinti*/, INT /*FRintj*/, INT /*FRintk*/); +extern int frvbf_model_fr400_u_media_2_add_sub_dual (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*ACC40Si*/, INT /*ACC40Sk*/); +extern int frvbf_model_fr400_u_media_2_add_sub (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*ACC40Si*/, INT /*ACC40Sk*/); +extern int frvbf_model_fr400_u_media_2_acc_dual (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*ACC40Si*/, INT /*ACC40Sk*/); +extern int frvbf_model_fr400_u_media_2_acc (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*ACC40Si*/, INT /*ACC40Sk*/); +extern int frvbf_model_fr400_u_media_2_quad (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRinti*/, INT /*FRintj*/, INT /*ACC40Sk*/, INT /*ACC40Uk*/); +extern int frvbf_model_fr400_u_media_2 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRinti*/, INT /*FRintj*/, INT /*ACC40Sk*/, INT /*ACC40Uk*/); +extern int frvbf_model_fr400_u_media_hilo (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRkhi*/, INT /*FRklo*/); +extern int frvbf_model_fr400_u_media_1_quad (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRinti*/, INT /*FRintj*/, INT /*FRintk*/); +extern int frvbf_model_fr400_u_media_1 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRinti*/, INT /*FRintj*/, INT /*FRintk*/); +extern int frvbf_model_fr400_u_gr2spr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRj*/, INT /*spr*/); +extern int frvbf_model_fr400_u_gr2fr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRj*/, INT /*FRintk*/); +extern int frvbf_model_fr400_u_spr2gr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*spr*/, INT /*GRj*/); +extern int frvbf_model_fr400_u_fr2gr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRintk*/, INT /*GRj*/); +extern int frvbf_model_fr400_u_swap (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*GRk*/); +extern int frvbf_model_fr400_u_fr_store (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*FRintk*/, INT /*FRdoublek*/); +extern int frvbf_model_fr400_u_fr_load (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*FRintk*/, INT /*FRdoublek*/); +extern int frvbf_model_fr400_u_gr_store (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*GRk*/, INT /*GRdoublek*/); +extern int frvbf_model_fr400_u_gr_load (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*GRk*/, INT /*GRdoublek*/); +extern int frvbf_model_fr400_u_set_hilo (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRkhi*/, INT /*GRklo*/); +extern int frvbf_model_fr400_u_check (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*ICCi_3*/, INT /*FCCi_3*/); +extern int frvbf_model_fr400_u_trap (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*ICCi_2*/, INT /*FCCi_2*/); +extern int frvbf_model_fr400_u_branch (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*ICCi_2*/, INT /*FCCi_2*/); +extern int frvbf_model_fr400_u_idiv (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*GRk*/, INT /*ICCi_1*/); +extern int frvbf_model_fr400_u_imul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*GRdoublek*/, INT /*ICCi_1*/); +extern int frvbf_model_fr400_u_integer (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*GRk*/, INT /*ICCi_1*/); +extern int frvbf_model_fr400_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int frvbf_model_simple_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); + +/* Profiling before/after handlers (user written) */ + +extern void frvbf_model_insn_before (SIM_CPU *, int /*first_p*/); +extern void frvbf_model_insn_after (SIM_CPU *, int /*last_p*/, int /*cycles*/); + +#endif /* FRVBF_DECODE_H */ diff --git a/sim/frv/devices.c b/sim/frv/devices.c new file mode 100644 index 0000000..3c1dedb --- /dev/null +++ b/sim/frv/devices.c @@ -0,0 +1,96 @@ +/* frv device support + Copyright (C) 1998, 1999 Free Software Foundation, Inc. + Contributed by Red Hat. + +This file is part of the GNU simulators. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* ??? All of this is just to get something going. wip! */ + +#include "sim-main.h" + +#ifdef HAVE_DV_SOCKSER +#include "dv-sockser.h" +#endif + +device frv_devices; + +int +device_io_read_buffer (device *me, void *source, int space, + address_word addr, unsigned nr_bytes, + SIM_DESC sd, SIM_CPU *cpu, sim_cia cia) +{ + if (STATE_ENVIRONMENT (sd) != OPERATING_ENVIRONMENT) + return nr_bytes; + +#ifdef HAVE_DV_SOCKSER + if (addr == UART_INCHAR_ADDR) + { + int c = dv_sockser_read (sd); + if (c == -1) + return 0; + *(char *) source = c; + return 1; + } + if (addr == UART_STATUS_ADDR) + { + int status = dv_sockser_status (sd); + unsigned char *p = source; + p[0] = 0; + p[1] = (((status & DV_SOCKSER_INPUT_EMPTY) +#ifdef UART_INPUT_READY0 + ? UART_INPUT_READY : 0) +#else + ? 0 : UART_INPUT_READY) +#endif + + ((status & DV_SOCKSER_OUTPUT_EMPTY) ? UART_OUTPUT_READY : 0)); + return 2; + } +#endif + + return nr_bytes; +} + +int +device_io_write_buffer (device *me, const void *source, int space, + address_word addr, unsigned nr_bytes, + SIM_DESC sd, SIM_CPU *cpu, sim_cia cia) +{ + +#if WITH_SCACHE + if (addr == MCCR_ADDR) + { + if ((*(const char *) source & MCCR_CP) != 0) + scache_flush (sd); + return nr_bytes; + } +#endif + + if (STATE_ENVIRONMENT (sd) != OPERATING_ENVIRONMENT) + return nr_bytes; + +#if HAVE_DV_SOCKSER + if (addr == UART_OUTCHAR_ADDR) + { + int rc = dv_sockser_write (sd, *(char *) source); + return rc == 1; + } +#endif + + return nr_bytes; +} + +void device_error (device *me, char* message, ...) {} diff --git a/sim/frv/frv-sim.h b/sim/frv/frv-sim.h new file mode 100644 index 0000000..39da19c --- /dev/null +++ b/sim/frv/frv-sim.h @@ -0,0 +1,929 @@ +/* collection of junk waiting time to sort out + Copyright (C) 1998, 1999, 2000, 2001, 2003 Free Software Foundation, Inc. + Contributed by Red Hat + +This file is part of the GNU Simulators. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef FRV_SIM_H +#define FRV_SIM_H + +#include "sim-options.h" + +/* Not defined in the cgen cpu file for access restriction purposes. */ +#define H_SPR_ACC4 1412 +#define H_SPR_ACC63 1471 +#define H_SPR_ACCG4 1476 +#define H_SPR_ACCG63 1535 + +/* Initialization of the frv cpu. */ +void frv_initialize (SIM_CPU *, SIM_DESC); +void frv_term (SIM_DESC); +void frv_power_on_reset (SIM_CPU *); +void frv_hardware_reset (SIM_CPU *); +void frv_software_reset (SIM_CPU *); + +/* The reset register. See FRV LSI section 10.3.1 */ +#define RSTR_ADDRESS 0xfeff0500 +#define RSTR_INITIAL_VALUE 0x00000400 +#define RSTR_HARDWARE_RESET 0x00000200 +#define RSTR_SOFTWARE_RESET 0x00000100 + +#define GET_RSTR_HR(rstr) (((rstr) >> 1) & 1) +#define GET_RSTR_SR(rstr) (((rstr) ) & 1) + +#define SET_RSTR_H(rstr) ((rstr) |= (1 << 9)) +#define SET_RSTR_S(rstr) ((rstr) |= (1 << 8)) + +#define CLEAR_RSTR_P(rstr) ((rstr) &= ~(1 << 10)) +#define CLEAR_RSTR_H(rstr) ((rstr) &= ~(1 << 9)) +#define CLEAR_RSTR_S(rstr) ((rstr) &= ~(1 << 8)) +#define CLEAR_RSTR_HR(rstr) ((rstr) &= ~(1 << 1)) +#define CLEAR_RSTR_SR(rstr) ((rstr) &= ~1) + +/* Cutomized hardware get/set functions. */ +extern USI frvbf_h_spr_get_handler (SIM_CPU *, UINT); +extern void frvbf_h_spr_set_handler (SIM_CPU *, UINT, USI); +extern USI frvbf_h_gr_get_handler (SIM_CPU *, UINT); +extern void frvbf_h_gr_set_handler (SIM_CPU *, UINT, USI); +extern UHI frvbf_h_gr_hi_get_handler (SIM_CPU *, UINT); +extern void frvbf_h_gr_hi_set_handler (SIM_CPU *, UINT, UHI); +extern UHI frvbf_h_gr_lo_get_handler (SIM_CPU *, UINT); +extern void frvbf_h_gr_lo_set_handler (SIM_CPU *, UINT, UHI); +extern DI frvbf_h_gr_double_get_handler (SIM_CPU *, UINT); +extern void frvbf_h_gr_double_set_handler (SIM_CPU *, UINT, DI); +extern SF frvbf_h_fr_get_handler (SIM_CPU *, UINT); +extern void frvbf_h_fr_set_handler (SIM_CPU *, UINT, SF); +extern DF frvbf_h_fr_double_get_handler (SIM_CPU *, UINT); +extern void frvbf_h_fr_double_set_handler (SIM_CPU *, UINT, DF); +extern USI frvbf_h_fr_int_get_handler (SIM_CPU *, UINT); +extern void frvbf_h_fr_int_set_handler (SIM_CPU *, UINT, USI); +extern DI frvbf_h_cpr_double_get_handler (SIM_CPU *, UINT); +extern void frvbf_h_cpr_double_set_handler (SIM_CPU *, UINT, DI); +extern void frvbf_h_gr_quad_set_handler (SIM_CPU *, UINT, SI *); +extern void frvbf_h_fr_quad_set_handler (SIM_CPU *, UINT, SI *); +extern void frvbf_h_cpr_quad_set_handler (SIM_CPU *, UINT, SI *); +extern void frvbf_h_psr_s_set_handler (SIM_CPU *, BI); + +extern USI spr_psr_get_handler (SIM_CPU *); +extern void spr_psr_set_handler (SIM_CPU *, USI); +extern USI spr_tbr_get_handler (SIM_CPU *); +extern void spr_tbr_set_handler (SIM_CPU *, USI); +extern USI spr_bpsr_get_handler (SIM_CPU *); +extern void spr_bpsr_set_handler (SIM_CPU *, USI); +extern USI spr_ccr_get_handler (SIM_CPU *); +extern void spr_ccr_set_handler (SIM_CPU *, USI); +extern void spr_cccr_set_handler (SIM_CPU *, USI); +extern USI spr_cccr_get_handler (SIM_CPU *); +extern USI spr_isr_get_handler (SIM_CPU *); +extern void spr_isr_set_handler (SIM_CPU *, USI); +extern USI spr_sr_get_handler (SIM_CPU *, UINT); +extern void spr_sr_set_handler (SIM_CPU *, UINT, USI); + +extern void frvbf_switch_supervisor_user_context (SIM_CPU *); + +extern QI frvbf_set_icc_for_shift_left (SIM_CPU *, SI, SI, QI); +extern QI frvbf_set_icc_for_shift_right (SIM_CPU *, SI, SI, QI); + +/* Insn semantics. */ +extern void frvbf_signed_integer_divide (SIM_CPU *, SI, SI, int, int); +extern void frvbf_unsigned_integer_divide (SIM_CPU *, USI, USI, int, int); +extern SI frvbf_shift_left_arith_saturate (SIM_CPU *, SI, SI); +extern SI frvbf_iacc_cut (SIM_CPU *, DI, SI); + +extern void frvbf_clear_accumulators (SIM_CPU *, SI, int); + +extern SI frvbf_scan_result (SIM_CPU *, SI); +extern SI frvbf_cut (SIM_CPU *, SI, SI, SI); +extern SI frvbf_media_cut (SIM_CPU *, DI, SI); +extern SI frvbf_media_cut_ss (SIM_CPU *, DI, SI); +extern void frvbf_media_cop (SIM_CPU *, int); +extern UQI frvbf_cr_logic (SIM_CPU *, SI, UQI, UQI); + +extern void frvbf_set_write_next_vliw_addr_to_LR (SIM_CPU *, int); +extern int frvbf_write_next_vliw_addr_to_LR; + +extern void frvbf_set_ne_index (SIM_CPU *, int); +extern void frvbf_force_update (SIM_CPU *); + +#define GETTWI GETTSI +#define SETTWI SETTSI +#define LEUINT LEUSI + +/* Hardware/device support. + ??? Will eventually want to move device stuff to config files. */ + +/* Support for the MCCR register (Cache Control Register) is needed in order + for overlays to work correctly with the scache: cached instructions need + to be flushed when the instruction space is changed at runtime. */ + +/* These were just copied from another port and are necessary to build, but + but don't appear to be used. */ +#define MCCR_ADDR 0xffffffff +#define MCCR_CP 0x80 +/* not supported */ +#define MCCR_CM0 2 +#define MCCR_CM1 1 + +/* sim_core_attach device argument. */ +extern device frv_devices; + +/* FIXME: Temporary, until device support ready. */ +struct _device { int foo; }; + +/* maintain the address of the start of the previous VLIW insn sequence. */ +extern IADDR previous_vliw_pc; +extern CGEN_ATTR_VALUE_TYPE frv_current_fm_slot; + +/* Hardware status. */ +#define GET_HSR0() GET_H_SPR (H_SPR_HSR0) +#define SET_HSR0(hsr0) SET_H_SPR (H_SPR_HSR0, (hsr0)) + +#define GET_HSR0_ICE(hsr0) (((hsr0) >> 31) & 1) +#define SET_HSR0_ICE(hsr0) ((hsr0) |= (1 << 31)) +#define CLEAR_HSR0_ICE(hsr0) ((hsr0) &= ~(1 << 31)) + +#define GET_HSR0_DCE(hsr0) (((hsr0) >> 30) & 1) +#define SET_HSR0_DCE(hsr0) ((hsr0) |= (1 << 30)) +#define CLEAR_HSR0_DCE(hsr0) ((hsr0) &= ~(1 << 30)) + +#define GET_HSR0_CBM(hsr0) (((hsr0) >> 27) & 1) +#define GET_HSR0_RME(hsr0) (((hsr0) >> 22) & 1) +#define GET_HSR0_SA(hsr0) (((hsr0) >> 12) & 1) +#define GET_HSR0_FRN(hsr0) (((hsr0) >> 11) & 1) +#define GET_HSR0_GRN(hsr0) (((hsr0) >> 10) & 1) +#define GET_HSR0_FRHE(hsr0) (((hsr0) >> 9) & 1) +#define GET_HSR0_FRLE(hsr0) (((hsr0) >> 8) & 1) +#define GET_HSR0_GRHE(hsr0) (((hsr0) >> 7) & 1) +#define GET_HSR0_GRLE(hsr0) (((hsr0) >> 6) & 1) + +#define GET_IHSR8() GET_H_SPR (H_SPR_IHSR8) +#define GET_IHSR8_NBC(ihsr8) ((ihsr8) & 1) +#define GET_IHSR8_ICDM(ihsr8) (((ihsr8) >> 1) & 1) +#define GET_IHSR8_ICWE(ihsr8) (((ihsr8) >> 8) & 7) +#define GET_IHSR8_DCWE(ihsr8) (((ihsr8) >> 12) & 7) + +void frvbf_insn_cache_preload (SIM_CPU *, SI, USI, int); +void frvbf_data_cache_preload (SIM_CPU *, SI, USI, int); +void frvbf_insn_cache_unlock (SIM_CPU *, SI); +void frvbf_data_cache_unlock (SIM_CPU *, SI); +void frvbf_insn_cache_invalidate (SIM_CPU *, SI, int); +void frvbf_data_cache_invalidate (SIM_CPU *, SI, int); +void frvbf_data_cache_flush (SIM_CPU *, SI, int); + +/* FR-V Interrupt classes. + These are declared in order of increasing priority. */ +enum frv_interrupt_class +{ + FRV_EXTERNAL_INTERRUPT, + FRV_SOFTWARE_INTERRUPT, + FRV_PROGRAM_INTERRUPT, + FRV_BREAK_INTERRUPT, + FRV_RESET_INTERRUPT, + NUM_FRV_INTERRUPT_CLASSES +}; + +/* FR-V Interrupt kinds. + These are declared in order of increasing priority. */ +enum frv_interrupt_kind +{ + /* External interrupts */ + FRV_INTERRUPT_LEVEL_1, + FRV_INTERRUPT_LEVEL_2, + FRV_INTERRUPT_LEVEL_3, + FRV_INTERRUPT_LEVEL_4, + FRV_INTERRUPT_LEVEL_5, + FRV_INTERRUPT_LEVEL_6, + FRV_INTERRUPT_LEVEL_7, + FRV_INTERRUPT_LEVEL_8, + FRV_INTERRUPT_LEVEL_9, + FRV_INTERRUPT_LEVEL_10, + FRV_INTERRUPT_LEVEL_11, + FRV_INTERRUPT_LEVEL_12, + FRV_INTERRUPT_LEVEL_13, + FRV_INTERRUPT_LEVEL_14, + FRV_INTERRUPT_LEVEL_15, + /* Software interrupt */ + FRV_TRAP_INSTRUCTION, + /* Program interrupts */ + FRV_COMMIT_EXCEPTION, + FRV_DIVISION_EXCEPTION, + FRV_DATA_STORE_ERROR, + FRV_DATA_ACCESS_EXCEPTION, + FRV_DATA_ACCESS_MMU_MISS, + FRV_DATA_ACCESS_ERROR, + FRV_MP_EXCEPTION, + FRV_FP_EXCEPTION, + FRV_MEM_ADDRESS_NOT_ALIGNED, + FRV_REGISTER_EXCEPTION, + FRV_MP_DISABLED, + FRV_FP_DISABLED, + FRV_PRIVILEGED_INSTRUCTION, + FRV_ILLEGAL_INSTRUCTION, + FRV_INSTRUCTION_ACCESS_EXCEPTION, + FRV_INSTRUCTION_ACCESS_ERROR, + FRV_INSTRUCTION_ACCESS_MMU_MISS, + FRV_COMPOUND_EXCEPTION, + /* Break interrupt */ + FRV_BREAK_EXCEPTION, + /* Reset interrupt */ + FRV_RESET, + NUM_FRV_INTERRUPT_KINDS +}; + +/* FRV interrupt exception codes */ +enum frv_ec +{ + FRV_EC_DATA_STORE_ERROR = 0x00, + FRV_EC_INSTRUCTION_ACCESS_MMU_MISS = 0x01, + FRV_EC_INSTRUCTION_ACCESS_ERROR = 0x02, + FRV_EC_INSTRUCTION_ACCESS_EXCEPTION = 0x03, + FRV_EC_PRIVILEGED_INSTRUCTION = 0x04, + FRV_EC_ILLEGAL_INSTRUCTION = 0x05, + FRV_EC_FP_DISABLED = 0x06, + FRV_EC_MP_DISABLED = 0x07, + FRV_EC_MEM_ADDRESS_NOT_ALIGNED = 0x0b, + FRV_EC_REGISTER_EXCEPTION = 0x0c, + FRV_EC_FP_EXCEPTION = 0x0d, + FRV_EC_MP_EXCEPTION = 0x0e, + FRV_EC_DATA_ACCESS_ERROR = 0x10, + FRV_EC_DATA_ACCESS_MMU_MISS = 0x11, + FRV_EC_DATA_ACCESS_EXCEPTION = 0x12, + FRV_EC_DIVISION_EXCEPTION = 0x13, + FRV_EC_COMMIT_EXCEPTION = 0x14, + FRV_EC_NOT_EXECUTED = 0x1f, + FRV_EC_INTERRUPT_LEVEL_1 = FRV_EC_NOT_EXECUTED, + FRV_EC_INTERRUPT_LEVEL_2 = FRV_EC_NOT_EXECUTED, + FRV_EC_INTERRUPT_LEVEL_3 = FRV_EC_NOT_EXECUTED, + FRV_EC_INTERRUPT_LEVEL_4 = FRV_EC_NOT_EXECUTED, + FRV_EC_INTERRUPT_LEVEL_5 = FRV_EC_NOT_EXECUTED, + FRV_EC_INTERRUPT_LEVEL_6 = FRV_EC_NOT_EXECUTED, + FRV_EC_INTERRUPT_LEVEL_7 = FRV_EC_NOT_EXECUTED, + FRV_EC_INTERRUPT_LEVEL_8 = FRV_EC_NOT_EXECUTED, + FRV_EC_INTERRUPT_LEVEL_9 = FRV_EC_NOT_EXECUTED, + FRV_EC_INTERRUPT_LEVEL_10 = FRV_EC_NOT_EXECUTED, + FRV_EC_INTERRUPT_LEVEL_11 = FRV_EC_NOT_EXECUTED, + FRV_EC_INTERRUPT_LEVEL_12 = FRV_EC_NOT_EXECUTED, + FRV_EC_INTERRUPT_LEVEL_13 = FRV_EC_NOT_EXECUTED, + FRV_EC_INTERRUPT_LEVEL_14 = FRV_EC_NOT_EXECUTED, + FRV_EC_INTERRUPT_LEVEL_15 = FRV_EC_NOT_EXECUTED, + FRV_EC_TRAP_INSTRUCTION = FRV_EC_NOT_EXECUTED, + FRV_EC_COMPOUND_EXCEPTION = FRV_EC_NOT_EXECUTED, + FRV_EC_BREAK_EXCEPTION = FRV_EC_NOT_EXECUTED, + FRV_EC_RESET = FRV_EC_NOT_EXECUTED +}; + +/* FR-V Interrupt. + This struct contains enough information to describe a particular interrupt + occurance. */ +struct frv_interrupt +{ + enum frv_interrupt_kind kind; + enum frv_ec ec; + enum frv_interrupt_class iclass; + unsigned char deferred; + unsigned char precise; + unsigned char handler_offset; +}; + +/* FR-V Interrupt table. + Describes the interrupts supported by the FR-V. */ +extern struct frv_interrupt frv_interrupt_table[]; + +/* FR-V Interrupt State. + Interrupts are queued during execution of parallel insns and the interupt(s) + to be handled determined by analysing the queue after each VLIW insn. */ +#define FRV_INTERRUPT_QUEUE_SIZE (4 * 4) /* 4 interrupts x 4 insns for now. */ + +/* register_exception codes */ +enum frv_rec +{ + FRV_REC_UNIMPLEMENTED = 0, + FRV_REC_UNALIGNED = 1 +}; + +/* instruction_access_exception codes */ +enum frv_iaec +{ + FRV_IAEC_PROTECT_VIOLATION = 1 +}; + +/* data_access_exception codes */ +enum frv_daec +{ + FRV_DAEC_PROTECT_VIOLATION = 1 +}; + +/* division_exception ISR codes */ +enum frv_dtt +{ + FRV_DTT_NO_EXCEPTION = 0, + FRV_DTT_DIVISION_BY_ZERO = 1, + FRV_DTT_OVERFLOW = 2, + FRV_DTT_BOTH = 3 +}; + +/* data written during an insn causing an interrupt */ +struct frv_data_written +{ + USI words[4]; /* Actual data in words */ + int length; /* length of data written */ +}; + +/* fp_exception info */ +/* Trap codes for FSR0 and FQ registers. */ +enum frv_fsr_traps +{ + FSR_INVALID_OPERATION = 0x20, + FSR_OVERFLOW = 0x10, + FSR_UNDERFLOW = 0x08, + FSR_DIVISION_BY_ZERO = 0x04, + FSR_INEXACT = 0x02, + FSR_DENORMAL_INPUT = 0x01, + FSR_NO_EXCEPTION = 0 +}; + +/* Floating point trap types for FSR. */ +enum frv_fsr_ftt +{ + FTT_NONE = 0, + FTT_IEEE_754_EXCEPTION = 1, + FTT_UNIMPLEMENTED_FPOP = 3, + FTT_SEQUENCE_ERROR = 4, + FTT_INVALID_FR = 6, + FTT_DENORMAL_INPUT = 7 +}; + +struct frv_fp_exception_info +{ + enum frv_fsr_traps fsr_mask; /* interrupt code for FSR */ + enum frv_fsr_ftt ftt; /* floating point trap type */ +}; + +struct frv_interrupt_queue_element +{ + enum frv_interrupt_kind kind; /* kind of interrupt */ + IADDR vpc; /* address of insn causing interrupt */ + int slot; /* VLIW slot containing the insn. */ + USI eaddress; /* address of data access */ + union { + enum frv_rec rec; /* register exception code */ + enum frv_iaec iaec; /* insn access exception code */ + enum frv_daec daec; /* data access exception code */ + enum frv_dtt dtt; /* division exception code */ + struct frv_fp_exception_info fp_info; + struct frv_data_written data_written; + } u; +}; + +struct frv_interrupt_timer +{ + int enabled; + unsigned value; + unsigned current; + enum frv_interrupt_kind interrupt; +}; + +struct frv_interrupt_state +{ + /* The interrupt queue */ + struct frv_interrupt_queue_element queue[FRV_INTERRUPT_QUEUE_SIZE]; + int queue_index; + + /* interrupt queue element causing imprecise interrupt. */ + struct frv_interrupt_queue_element *imprecise_interrupt; + + /* interrupt timer. */ + struct frv_interrupt_timer timer; + + /* The last data written stored as an array of words. */ + struct frv_data_written data_written; + + /* The vliw slot of the insn causing the interrupt. */ + int slot; + + /* target register index for non excepting insns. */ +#define NE_NOFLAG (-1) + int ne_index; + + /* Accumulated NE flags for non excepting floating point insns. */ + SI f_ne_flags[2]; +}; + +extern struct frv_interrupt_state frv_interrupt_state; + +/* Macros to manipulate the PSR. */ +#define GET_PSR() GET_H_SPR (H_SPR_PSR) + +#define SET_PSR_ET(psr, et) ( \ + (psr) = ((psr) & ~0x1) | ((et) & 0x1) \ +) + +#define GET_PSR_PS(psr) (((psr) >> 1) & 1) + +#define SET_PSR_S(psr, s) ( \ + (psr) = ((psr) & ~(0x1 << 2)) | (((s) & 0x1) << 2) \ +) + +/* Macros to handle the ISR register. */ +#define GET_ISR() GET_H_SPR (H_SPR_ISR) +#define SET_ISR(isr) SET_H_SPR (H_SPR_ISR, (isr)) + +#define GET_ISR_EDE(isr) (((isr) >> 5) & 1) + +#define GET_ISR_DTT(isr) (((isr) >> 3) & 3) +#define SET_ISR_DTT(isr, dtt) ( \ + (isr) = ((isr) & ~(0x3 << 3)) | (((dtt) & 0x3) << 3) \ +) + +#define SET_ISR_AEXC(isr) ((isr) |= (1 << 2)) + +#define GET_ISR_EMAM(isr) ((isr) & 1) + +/* Macros to handle exception status registers. + Get and set the hardware directly, since we may be getting/setting fields + which are not accessible to the user. */ +#define GET_ESR(index) \ + (CPU (h_spr[H_SPR_ESR0 + (index)])) +#define SET_ESR(index, esr) \ + (CPU (h_spr[H_SPR_ESR0 + (index)]) = (esr)) + +#define SET_ESR_VALID(esr) ((esr) |= 1) +#define CLEAR_ESR_VALID(esr) ((esr) &= ~1) + +#define SET_ESR_EC(esr, ec) ( \ + (esr) = ((esr) & ~(0x1f << 1)) | (((ec) & 0x1f) << 1) \ +) + +#define SET_ESR_REC(esr, rec) ( \ + (esr) = ((esr) & ~(0x3 << 6)) | (((rec) & 0x3) << 6) \ +) + +#define SET_ESR_IAEC(esr, iaec) ( \ + (esr) = ((esr) & ~(0x1 << 8)) | (((iaec) & 0x1) << 8) \ +) + +#define SET_ESR_DAEC(esr, daec) ( \ + (esr) = ((esr) & ~(0x1 << 9)) | (((daec) & 0x1) << 9) \ +) + +#define SET_ESR_EAV(esr) ((esr) |= (1 << 11)) +#define CLEAR_ESR_EAV(esr) ((esr) &= ~(1 << 11)) + +#define GET_ESR_EDV(esr) (((esr) >> 12) & 1) +#define SET_ESR_EDV(esr) ((esr) |= (1 << 12)) +#define CLEAR_ESR_EDV(esr) ((esr) &= ~(1 << 12)) + +#define GET_ESR_EDN(esr) ( \ + ((esr) >> 13) & 0xf \ +) +#define SET_ESR_EDN(esr, edn) ( \ + (esr) = ((esr) & ~(0xf << 13)) | (((edn) & 0xf) << 13) \ +) + +#define SET_EPCR(index, address) \ + (CPU (h_spr[H_SPR_EPCR0 + (index)]) = (address)) + +#define SET_EAR(index, address) \ + (CPU (h_spr[H_SPR_EAR0 + (index)]) = (address)) + +#define SET_EDR(index, edr) \ + (CPU (h_spr[H_SPR_EDR0 + (index)]) = (edr)) + +#define GET_ESFR(index) \ + (CPU (h_spr[H_SPR_ESFR0 + (index)])) +#define SET_ESFR(index, esfr) \ + (CPU (h_spr[H_SPR_ESFR0 + (index)]) = (esfr)) + +#define GET_ESFR_FLAG(findex) ( \ + (findex) > 31 ? \ + ((CPU (h_spr[H_SPR_ESFR0]) >> ((findex)-32)) & 1) \ + : \ + ((CPU (h_spr[H_SPR_ESFR1]) >> (findex)) & 1) \ +) +#define SET_ESFR_FLAG(findex) ( \ + (findex) > 31 ? \ + (CPU (h_spr[H_SPR_ESFR0]) = \ + (CPU (h_spr[H_SPR_ESFR0]) | (1 << ((findex)-32))) \ + ) : \ + (CPU (h_spr[H_SPR_ESFR1]) = \ + (CPU (h_spr[H_SPR_ESFR1]) | (1 << (findex))) \ + ) \ +) + +/* The FSR registers. + Get and set the hardware directly, since we may be getting/setting fields + which are not accessible to the user. */ +#define GET_FSR(index) \ + (CPU (h_spr[H_SPR_FSR0 + (index)])) +#define SET_FSR(index, fsr) \ + (CPU (h_spr[H_SPR_FSR0 + (index)]) = (fsr)) + +#define GET_FSR_TEM(fsr) ( \ + ((fsr) >> 24) & 0x3f \ +) + +#define SET_FSR_QNE(fsr) ((fsr) |= (1 << 20)) +#define GET_FSR_QNE(fsr) (((fsr) >> 20) & 1) + +#define SET_FSR_FTT(fsr, ftt) ( \ + (fsr) = ((fsr) & ~(0x7 << 17)) | (((ftt) & 0x7) << 17) \ +) + +#define GET_FSR_AEXC(fsr) ( \ + ((fsr) >> 10) & 0x3f \ +) +#define SET_FSR_AEXC(fsr, aexc) ( \ + (fsr) = ((fsr) & ~(0x3f << 10)) | (((aexc) & 0x3f) << 10) \ +) + +/* SIMD instruction exception codes for FQ. */ +enum frv_sie +{ + SIE_NIL = 0, + SIE_FRi = 1, + SIE_FRi_1 = 2 +}; + +/* MIV field of FQ. */ +enum frv_miv +{ + MIV_FLOAT = 0, + MIV_MEDIA = 1 +}; + +/* The FQ registers are 64 bits wide and are implemented as 32 bit pairs. The + index here refers to the low order 32 bit element. + Get and set the hardware directly, since we may be getting/setting fields + which are not accessible to the user. */ +#define GET_FQ(index) \ + (CPU (h_spr[H_SPR_FQST0 + 2 * (index)])) +#define SET_FQ(index, fq) \ + (CPU (h_spr[H_SPR_FQST0 + 2 * (index)]) = (fq)) + +#define SET_FQ_MIV(fq, miv) ( \ + (fq) = ((fq) & ~(0x1 << 31)) | (((miv) & 0x1) << 31) \ +) + +#define SET_FQ_SIE(fq, sie) ( \ + (fq) = ((fq) & ~(0x3 << 15)) | (((sie) & 0x3) << 15) \ +) + +#define SET_FQ_FTT(fq, ftt) ( \ + (fq) = ((fq) & ~(0x7 << 7)) | (((ftt) & 0x7) << 7) \ +) + +#define SET_FQ_CEXC(fq, cexc) ( \ + (fq) = ((fq) & ~(0x3f << 1)) | (((cexc) & 0x3f) << 1) \ +) + +#define GET_FQ_VALID(fq) ((fq) & 1) +#define SET_FQ_VALID(fq) ((fq) |= 1) + +#define SET_FQ_OPC(index, insn) \ + (CPU (h_spr[H_SPR_FQOP0 + 2 * (index)]) = (insn)) + +/* mp_exception support. */ +/* Media trap types for MSR. */ +enum frv_msr_mtt +{ + MTT_NONE = 0, + MTT_OVERFLOW = 1, + MTT_ACC_NOT_ALIGNED = 2, + MTT_ACC_NOT_IMPLEMENTED = 2, /* Yes -- same value as MTT_ACC_NOT_ALIGNED. */ + MTT_CR_NOT_ALIGNED = 3, + MTT_UNIMPLEMENTED_MPOP = 5, + MTT_INVALID_FR = 6 +}; + +/* Media status registers. + Get and set the hardware directly, since we may be getting/setting fields + which are not accessible to the user. */ +#define GET_MSR(index) \ + (CPU (h_spr[H_SPR_MSR0 + (index)])) +#define SET_MSR(index, msr) \ + (CPU (h_spr[H_SPR_MSR0 + (index)]) = (msr)) + +#define GET_MSR_AOVF(msr) ((msr) & 1) +#define SET_MSR_AOVF(msr) ((msr) |= 1) + +#define GET_MSR_OVF(msr) ( \ + ((msr) >> 1) & 0x1 \ +) +#define SET_MSR_OVF(msr) ( \ + (msr) |= (1 << 1) \ +) +#define CLEAR_MSR_OVF(msr) ( \ + (msr) &= ~(1 << 1) \ +) + +#define OR_MSR_SIE(msr, sie) ( \ + (msr) |= (((sie) & 0xf) << 2) \ +) +#define CLEAR_MSR_SIE(msr) ( \ + (msr) &= ~(0xf << 2) \ +) + +#define GET_MSR_MTT(msr) ( \ + ((msr) >> 12) & 0x7 \ +) +#define SET_MSR_MTT(msr, mtt) ( \ + (msr) = ((msr) & ~(0x7 << 12)) | (((mtt) & 0x7) << 12) \ +) +#define GET_MSR_EMCI(msr) ( \ + ((msr) >> 24) & 0x1 \ +) +#define GET_MSR_MPEM(msr) ( \ + ((msr) >> 27) & 0x1 \ +) +#define GET_MSR_SRDAV(msr) ( \ + ((msr) >> 28) & 0x1 \ +) +#define GET_MSR_RDAV(msr) ( \ + ((msr) >> 29) & 0x1 \ +) +#define GET_MSR_RD(msr) ( \ + ((msr) >> 30) & 0x3 \ +) + +void frvbf_media_register_not_aligned (SIM_CPU *); +void frvbf_media_acc_not_aligned (SIM_CPU *); +void frvbf_media_cr_not_aligned (SIM_CPU *); +void frvbf_media_overflow (SIM_CPU *, int); + +/* Functions for queuing and processing interrupts. */ +struct frv_interrupt_queue_element * +frv_queue_break_interrupt (SIM_CPU *); + +struct frv_interrupt_queue_element * +frv_queue_software_interrupt (SIM_CPU *, SI); + +struct frv_interrupt_queue_element * +frv_queue_program_interrupt (SIM_CPU *, enum frv_interrupt_kind); + +struct frv_interrupt_queue_element * +frv_queue_external_interrupt (SIM_CPU *, enum frv_interrupt_kind); + +struct frv_interrupt_queue_element * +frv_queue_illegal_instruction_interrupt (SIM_CPU *, const CGEN_INSN *); + +struct frv_interrupt_queue_element * +frv_queue_privileged_instruction_interrupt (SIM_CPU *, const CGEN_INSN *); + +struct frv_interrupt_queue_element * +frv_queue_float_disabled_interrupt (SIM_CPU *); + +struct frv_interrupt_queue_element * +frv_queue_media_disabled_interrupt (SIM_CPU *); + +struct frv_interrupt_queue_element * +frv_queue_non_implemented_instruction_interrupt (SIM_CPU *, const CGEN_INSN *); + +struct frv_interrupt_queue_element * +frv_queue_register_exception_interrupt (SIM_CPU *, enum frv_rec); + +struct frv_interrupt_queue_element * +frv_queue_mem_address_not_aligned_interrupt (SIM_CPU *, USI); + +struct frv_interrupt_queue_element * +frv_queue_data_access_error_interrupt (SIM_CPU *, USI); + +struct frv_interrupt_queue_element * +frv_queue_instruction_access_error_interrupt (SIM_CPU *); + +struct frv_interrupt_queue_element * +frv_queue_instruction_access_exception_interrupt (SIM_CPU *); + +struct frv_interrupt_queue_element * +frv_queue_fp_exception_interrupt (SIM_CPU *, struct frv_fp_exception_info *); + +enum frv_dtt frvbf_division_exception (SIM_CPU *, enum frv_dtt, int, int); + +struct frv_interrupt_queue_element * +frv_queue_interrupt (SIM_CPU *, enum frv_interrupt_kind); + +void +frv_set_interrupt_queue_slot (SIM_CPU *, struct frv_interrupt_queue_element *); + +void frv_set_mp_exception_registers (SIM_CPU *, enum frv_msr_mtt, int); +void frv_detect_insn_access_interrupts (SIM_CPU *, SCACHE *); + +void frv_process_interrupts (SIM_CPU *); + +void frv_break_interrupt (SIM_CPU *, struct frv_interrupt *, IADDR); +void frv_non_operating_interrupt (SIM_CPU *, enum frv_interrupt_kind, IADDR); +void frv_program_interrupt ( + SIM_CPU *, struct frv_interrupt_queue_element *, IADDR +); +void frv_software_interrupt ( + SIM_CPU *, struct frv_interrupt_queue_element *, IADDR +); +void frv_external_interrupt ( + SIM_CPU *, struct frv_interrupt_queue_element *, IADDR +); +void frv_program_or_software_interrupt ( + SIM_CPU *, struct frv_interrupt *, IADDR +); +void frv_clear_interrupt_classes ( + enum frv_interrupt_class, enum frv_interrupt_class +); + +void +frv_save_data_written_for_interrupts (SIM_CPU *, CGEN_WRITE_QUEUE_ELEMENT *); + +/* Special purpose traps. */ +#define TRAP_SYSCALL 0x80 +#define TRAP_BREAKPOINT 0x81 +#define TRAP_REGDUMP1 0x82 +#define TRAP_REGDUMP2 0x83 + +/* Handle the trap insns */ +void frv_itrap (SIM_CPU *, PCADDR, USI, int); +void frv_mtrap (SIM_CPU *); +/* Handle the break insn. */ +void frv_break (SIM_CPU *); +/* Handle the rett insn. */ +USI frv_rett (SIM_CPU *current_cpu, PCADDR pc, BI debug_field); + +/* Parallel write queue flags. */ +#define FRV_WRITE_QUEUE_FORCE_WRITE 1 + +#define CGEN_WRITE_QUEUE_ELEMENT_PIPE(element) CGEN_WRITE_QUEUE_ELEMENT_WORD1 (element) + +/* Functions and macros for handling non-excepting instruction side effects. + Get and set the hardware directly, since we may be getting/setting fields + which are not accessible to the user. */ +#define GET_NECR() (GET_H_SPR (H_SPR_NECR)) +#define GET_NECR_ELOS(necr) (((necr) >> 6) & 1) +#define GET_NECR_NEN(necr) (((necr) >> 1) & 0x1f) +#define GET_NECR_VALID(necr) (((necr) ) & 1) + +#define NO_NESR (-1) +/* NESR field values. See Tables 30-33 in section 4.4.2.1 of the FRV + Architecture volume 1. */ +#define NESR_MEM_ADDRESS_NOT_ALIGNED 0x0b +#define NESR_REGISTER_NOT_ALIGNED 0x1 +#define NESR_UQI_SIZE 0 +#define NESR_QI_SIZE 1 +#define NESR_UHI_SIZE 2 +#define NESR_HI_SIZE 3 +#define NESR_SI_SIZE 4 +#define NESR_DI_SIZE 5 +#define NESR_XI_SIZE 6 + +#define GET_NESR(index) GET_H_SPR (H_SPR_NESR0 + (index)) +#define SET_NESR(index, value) ( \ + sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, \ + H_SPR_NESR0 + (index), (value)), \ + frvbf_force_update (current_cpu) \ +) +#define GET_NESR_VALID(nesr) ((nesr) & 1) +#define SET_NESR_VALID(nesr) ((nesr) |= 1) + +#define SET_NESR_EAV(nesr) ((nesr) |= (1 << 31)) + +#define GET_NESR_FR(nesr) (((nesr) >> 30) & 1) +#define SET_NESR_FR(nesr) ((nesr) |= (1 << 30)) +#define CLEAR_NESR_FR(nesr) ((nesr) &= ~(1 << 30)) + +#define GET_NESR_DRN(nesr) (((nesr) >> 24) & 0x3f) +#define SET_NESR_DRN(nesr, drn) ( \ + (nesr) = ((nesr) & ~(0x3f << 24)) | (((drn) & 0x3f) << 24) \ +) + +#define SET_NESR_SIZE(nesr, data_size) ( \ + (nesr) = ((nesr) & ~(0x7 << 21)) | (((data_size) & 0x7) << 21) \ +) + +#define SET_NESR_NEAN(nesr, index) ( \ + (nesr) = ((nesr) & ~(0x1f << 10)) | (((index) & 0x1f) << 10) \ +) + +#define GET_NESR_DAEC(nesr) (((nesr) >> 9) & 1) +#define SET_NESR_DAEC(nesr, daec) ( \ + (nesr) = ((nesr) & ~(1 << 9)) | (((daec) & 1) << 9) \ +) + +#define GET_NESR_REC(nesr) (((nesr) >> 6) & 3) +#define SET_NESR_REC(nesr, rec) ( \ + (nesr) = ((nesr) & ~(3 << 6)) | (((rec) & 3) << 6) \ +) + +#define GET_NESR_EC(nesr) (((nesr) >> 1) & 0x1f) +#define SET_NESR_EC(nesr, ec) ( \ + (nesr) = ((nesr) & ~(0x1f << 1)) | (((ec) & 0x1f) << 1) \ +) + +#define SET_NEEAR(index, address) ( \ + sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, \ + H_SPR_NEEAR0 + (index), (address)), \ + frvbf_force_update (current_cpu) \ +) + +#define GET_NE_FLAGS(flags, NE_base) ( \ + (flags)[0] = GET_H_SPR ((NE_base)), \ + (flags)[1] = GET_H_SPR ((NE_base) + 1) \ +) +#define SET_NE_FLAGS(NE_base, flags) ( \ + sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, (NE_base), \ + (flags)[0]), \ + frvbf_force_update (current_cpu), \ + sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, (NE_base) + 1, \ + (flags)[1]), \ + frvbf_force_update (current_cpu) \ +) + +#define GET_NE_FLAG(flags, index) ( \ + (index) > 31 ? \ + ((flags[0] >> ((index) - 32)) & 1) \ + : \ + ((flags[1] >> (index)) & 1) \ +) +#define SET_NE_FLAG(flags, index) ( \ + (index) > 31 ? \ + ((flags)[0] |= (1 << ((index) - 32))) \ + : \ + ((flags)[1] |= (1 << (index))) \ +) +#define CLEAR_NE_FLAG(flags, index) ( \ + (index) > 31 ? \ + ((flags)[0] &= ~(1 << ((index) - 32))) \ + : \ + ((flags)[1] &= ~(1 << (index))) \ +) + +BI frvbf_check_non_excepting_load (SIM_CPU *, SI, SI, SI, SI, QI, BI); +void frvbf_check_recovering_store (SIM_CPU *, PCADDR, SI, int, int); + +void frvbf_clear_ne_flags (SIM_CPU *, SI, BI); +void frvbf_commit (SIM_CPU *, SI, BI); + +void frvbf_fpu_error (CGEN_FPU *, int); + +void frv_vliw_setup_insn (SIM_CPU *, const CGEN_INSN *); + +extern int insns_in_slot[]; + +#define COUNT_INSNS_IN_SLOT(slot) \ +{ \ + if (WITH_PROFILE_MODEL_P) \ + ++insns_in_slot[slot]; \ +} + +#define INSNS_IN_SLOT(slot) (insns_in_slot[slot]) + +/* Multiple loads and stores. */ +void frvbf_load_multiple_GR (SIM_CPU *, PCADDR, SI, SI, int); +void frvbf_load_multiple_FRint (SIM_CPU *, PCADDR, SI, SI, int); +void frvbf_load_multiple_CPR (SIM_CPU *, PCADDR, SI, SI, int); +void frvbf_store_multiple_GR (SIM_CPU *, PCADDR, SI, SI, int); +void frvbf_store_multiple_FRint (SIM_CPU *, PCADDR, SI, SI, int); +void frvbf_store_multiple_CPR (SIM_CPU *, PCADDR, SI, SI, int); + +/* Memory and cache support. */ +QI frvbf_read_mem_QI (SIM_CPU *, IADDR, SI); +UQI frvbf_read_mem_UQI (SIM_CPU *, IADDR, SI); +HI frvbf_read_mem_HI (SIM_CPU *, IADDR, SI); +UHI frvbf_read_mem_UHI (SIM_CPU *, IADDR, SI); +SI frvbf_read_mem_SI (SIM_CPU *, IADDR, SI); +SI frvbf_read_mem_WI (SIM_CPU *, IADDR, SI); +DI frvbf_read_mem_DI (SIM_CPU *, IADDR, SI); +DF frvbf_read_mem_DF (SIM_CPU *, IADDR, SI); + +USI frvbf_read_imem_USI (SIM_CPU *, PCADDR); + +void frvbf_write_mem_QI (SIM_CPU *, IADDR, SI, QI); +void frvbf_write_mem_UQI (SIM_CPU *, IADDR, SI, UQI); +void frvbf_write_mem_HI (SIM_CPU *, IADDR, SI, HI); +void frvbf_write_mem_UHI (SIM_CPU *, IADDR, SI, UHI); +void frvbf_write_mem_SI (SIM_CPU *, IADDR, SI, SI); +void frvbf_write_mem_WI (SIM_CPU *, IADDR, SI, SI); +void frvbf_write_mem_DI (SIM_CPU *, IADDR, SI, DI); +void frvbf_write_mem_DF (SIM_CPU *, IADDR, SI, DF); + +void frvbf_mem_set_QI (SIM_CPU *, IADDR, SI, QI); +void frvbf_mem_set_HI (SIM_CPU *, IADDR, SI, HI); +void frvbf_mem_set_SI (SIM_CPU *, IADDR, SI, SI); +void frvbf_mem_set_DI (SIM_CPU *, IADDR, SI, DI); +void frvbf_mem_set_DF (SIM_CPU *, IADDR, SI, DF); +void frvbf_mem_set_XI (SIM_CPU *, IADDR, SI, SI *); + +void frv_set_write_queue_slot (SIM_CPU *current_cpu); + +/* FRV specific options. */ +extern const OPTION frv_options[]; + +#endif /* FRV_SIM_H */ diff --git a/sim/frv/frv.c b/sim/frv/frv.c new file mode 100644 index 0000000..de1ff1d --- /dev/null +++ b/sim/frv/frv.c @@ -0,0 +1,1554 @@ +/* frv simulator support code + Copyright (C) 1998, 1999, 2000, 2001, 2003 Free Software Foundation, Inc. + Contributed by Red Hat. + +This file is part of the GNU simulators. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#define WANT_CPU +#define WANT_CPU_FRVBF + +#include "sim-main.h" +#include "cgen-mem.h" +#include "cgen-ops.h" +#include "cgen-engine.h" +#include "cgen-par.h" +#include "bfd.h" +#include "gdb/sim-frv.h" +#include + +/* Maintain a flag in order to know when to write the address of the next + VLIW instruction into the LR register. Used by JMPL. JMPIL, and CALL + insns. */ +int frvbf_write_next_vliw_addr_to_LR; + +/* The contents of BUF are in target byte order. */ +int +frvbf_fetch_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len) +{ + if (SIM_FRV_GR0_REGNUM <= rn && rn <= SIM_FRV_GR63_REGNUM) + { + int hi_available, lo_available; + int grn = rn - SIM_FRV_GR0_REGNUM; + + frv_gr_registers_available (current_cpu, &hi_available, &lo_available); + + if ((grn < 32 && !lo_available) || (grn >= 32 && !hi_available)) + return 0; + else + SETTSI (buf, GET_H_GR (grn)); + } + else if (SIM_FRV_FR0_REGNUM <= rn && rn <= SIM_FRV_FR63_REGNUM) + { + int hi_available, lo_available; + int frn = rn - SIM_FRV_FR0_REGNUM; + + frv_fr_registers_available (current_cpu, &hi_available, &lo_available); + + if ((frn < 32 && !lo_available) || (frn >= 32 && !hi_available)) + return 0; + else + SETTSI (buf, GET_H_FR (frn)); + } + else if (rn == SIM_FRV_PC_REGNUM) + SETTSI (buf, GET_H_PC ()); + else if (SIM_FRV_SPR0_REGNUM <= rn && rn <= SIM_FRV_SPR4095_REGNUM) + { + /* Make sure the register is implemented. */ + FRV_REGISTER_CONTROL *control = CPU_REGISTER_CONTROL (current_cpu); + int spr = rn - SIM_FRV_SPR0_REGNUM; + if (! control->spr[spr].implemented) + return 0; + SETTSI (buf, GET_H_SPR (spr)); + } + else + { + SETTSI (buf, 0xdeadbeef); + return 0; + } + + return len; +} + +/* The contents of BUF are in target byte order. */ + +int +frvbf_store_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len) +{ + if (SIM_FRV_GR0_REGNUM <= rn && rn <= SIM_FRV_GR63_REGNUM) + { + int hi_available, lo_available; + int grn = rn - SIM_FRV_GR0_REGNUM; + + frv_gr_registers_available (current_cpu, &hi_available, &lo_available); + + if ((grn < 32 && !lo_available) || (grn >= 32 && !hi_available)) + return 0; + else + SET_H_GR (grn, GETTSI (buf)); + } + else if (SIM_FRV_FR0_REGNUM <= rn && rn <= SIM_FRV_FR63_REGNUM) + { + int hi_available, lo_available; + int frn = rn - SIM_FRV_FR0_REGNUM; + + frv_fr_registers_available (current_cpu, &hi_available, &lo_available); + + if ((frn < 32 && !lo_available) || (frn >= 32 && !hi_available)) + return 0; + else + SET_H_FR (frn, GETTSI (buf)); + } + else if (rn == SIM_FRV_PC_REGNUM) + SET_H_PC (GETTSI (buf)); + else if (SIM_FRV_SPR0_REGNUM <= rn && rn <= SIM_FRV_SPR4095_REGNUM) + { + /* Make sure the register is implemented. */ + FRV_REGISTER_CONTROL *control = CPU_REGISTER_CONTROL (current_cpu); + int spr = rn - SIM_FRV_SPR0_REGNUM; + if (! control->spr[spr].implemented) + return 0; + SET_H_SPR (spr, GETTSI (buf)); + } + else + return 0; + + return len; +} + +/* Cover fns to access the general registers. */ +USI +frvbf_h_gr_get_handler (SIM_CPU *current_cpu, UINT gr) +{ + frv_check_gr_access (current_cpu, gr); + return CPU (h_gr[gr]); +} + +void +frvbf_h_gr_set_handler (SIM_CPU *current_cpu, UINT gr, USI newval) +{ + frv_check_gr_access (current_cpu, gr); + + if (gr == 0) + return; /* Storing into gr0 has no effect. */ + + CPU (h_gr[gr]) = newval; +} + +/* Cover fns to access the floating point registers. */ +SF +frvbf_h_fr_get_handler (SIM_CPU *current_cpu, UINT fr) +{ + frv_check_fr_access (current_cpu, fr); + return CPU (h_fr[fr]); +} + +void +frvbf_h_fr_set_handler (SIM_CPU *current_cpu, UINT fr, SF newval) +{ + frv_check_fr_access (current_cpu, fr); + CPU (h_fr[fr]) = newval; +} + +/* Cover fns to access the general registers as double words. */ +static UINT +check_register_alignment (SIM_CPU *current_cpu, UINT reg, int align_mask) +{ + if (reg & align_mask) + { + SIM_DESC sd = CPU_STATE (current_cpu); + switch (STATE_ARCHITECTURE (sd)->mach) + { + case bfd_mach_fr400: + case bfd_mach_fr550: + frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION); + break; + case bfd_mach_frvtomcat: + case bfd_mach_fr500: + case bfd_mach_frv: + frv_queue_register_exception_interrupt (current_cpu, + FRV_REC_UNALIGNED); + break; + default: + break; + } + + reg &= ~align_mask; + } + + return reg; +} + +static UINT +check_fr_register_alignment (SIM_CPU *current_cpu, UINT reg, int align_mask) +{ + if (reg & align_mask) + { + SIM_DESC sd = CPU_STATE (current_cpu); + switch (STATE_ARCHITECTURE (sd)->mach) + { + case bfd_mach_fr400: + case bfd_mach_fr550: + frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION); + break; + case bfd_mach_frvtomcat: + case bfd_mach_fr500: + case bfd_mach_frv: + { + struct frv_fp_exception_info fp_info = { + FSR_NO_EXCEPTION, FTT_INVALID_FR + }; + frv_queue_fp_exception_interrupt (current_cpu, & fp_info); + } + break; + default: + break; + } + + reg &= ~align_mask; + } + + return reg; +} + +static UINT +check_memory_alignment (SIM_CPU *current_cpu, SI address, int align_mask) +{ + if (address & align_mask) + { + SIM_DESC sd = CPU_STATE (current_cpu); + switch (STATE_ARCHITECTURE (sd)->mach) + { + case bfd_mach_fr400: + frv_queue_data_access_error_interrupt (current_cpu, address); + break; + case bfd_mach_frvtomcat: + case bfd_mach_fr500: + case bfd_mach_frv: + frv_queue_mem_address_not_aligned_interrupt (current_cpu, address); + break; + default: + break; + } + + address &= ~align_mask; + } + + return address; +} + +DI +frvbf_h_gr_double_get_handler (SIM_CPU *current_cpu, UINT gr) +{ + DI value; + + if (gr == 0) + return 0; /* gr0 is always 0. */ + + /* Check the register alignment. */ + gr = check_register_alignment (current_cpu, gr, 1); + + value = GET_H_GR (gr); + value <<= 32; + value |= (USI) GET_H_GR (gr + 1); + return value; +} + +void +frvbf_h_gr_double_set_handler (SIM_CPU *current_cpu, UINT gr, DI newval) +{ + if (gr == 0) + return; /* Storing into gr0 has no effect. */ + + /* Check the register alignment. */ + gr = check_register_alignment (current_cpu, gr, 1); + + SET_H_GR (gr , (newval >> 32) & 0xffffffff); + SET_H_GR (gr + 1, (newval ) & 0xffffffff); +} + +/* Cover fns to access the floating point register as double words. */ +DF +frvbf_h_fr_double_get_handler (SIM_CPU *current_cpu, UINT fr) +{ + union { + SF as_sf[2]; + DF as_df; + } value; + + /* Check the register alignment. */ + fr = check_fr_register_alignment (current_cpu, fr, 1); + + if (CURRENT_HOST_BYTE_ORDER == LITTLE_ENDIAN) + { + value.as_sf[1] = GET_H_FR (fr); + value.as_sf[0] = GET_H_FR (fr + 1); + } + else + { + value.as_sf[0] = GET_H_FR (fr); + value.as_sf[1] = GET_H_FR (fr + 1); + } + + return value.as_df; +} + +void +frvbf_h_fr_double_set_handler (SIM_CPU *current_cpu, UINT fr, DF newval) +{ + union { + SF as_sf[2]; + DF as_df; + } value; + + /* Check the register alignment. */ + fr = check_fr_register_alignment (current_cpu, fr, 1); + + value.as_df = newval; + if (CURRENT_HOST_BYTE_ORDER == LITTLE_ENDIAN) + { + SET_H_FR (fr , value.as_sf[1]); + SET_H_FR (fr + 1, value.as_sf[0]); + } + else + { + SET_H_FR (fr , value.as_sf[0]); + SET_H_FR (fr + 1, value.as_sf[1]); + } +} + +/* Cover fns to access the floating point register as integer words. */ +USI +frvbf_h_fr_int_get_handler (SIM_CPU *current_cpu, UINT fr) +{ + union { + SF as_sf; + USI as_usi; + } value; + + value.as_sf = GET_H_FR (fr); + return value.as_usi; +} + +void +frvbf_h_fr_int_set_handler (SIM_CPU *current_cpu, UINT fr, USI newval) +{ + union { + SF as_sf; + USI as_usi; + } value; + + value.as_usi = newval; + SET_H_FR (fr, value.as_sf); +} + +/* Cover fns to access the coprocessor registers as double words. */ +DI +frvbf_h_cpr_double_get_handler (SIM_CPU *current_cpu, UINT cpr) +{ + DI value; + + /* Check the register alignment. */ + cpr = check_register_alignment (current_cpu, cpr, 1); + + value = GET_H_CPR (cpr); + value <<= 32; + value |= (USI) GET_H_CPR (cpr + 1); + return value; +} + +void +frvbf_h_cpr_double_set_handler (SIM_CPU *current_cpu, UINT cpr, DI newval) +{ + /* Check the register alignment. */ + cpr = check_register_alignment (current_cpu, cpr, 1); + + SET_H_CPR (cpr , (newval >> 32) & 0xffffffff); + SET_H_CPR (cpr + 1, (newval ) & 0xffffffff); +} + +/* Cover fns to write registers as quad words. */ +void +frvbf_h_gr_quad_set_handler (SIM_CPU *current_cpu, UINT gr, SI *newval) +{ + if (gr == 0) + return; /* Storing into gr0 has no effect. */ + + /* Check the register alignment. */ + gr = check_register_alignment (current_cpu, gr, 3); + + SET_H_GR (gr , newval[0]); + SET_H_GR (gr + 1, newval[1]); + SET_H_GR (gr + 2, newval[2]); + SET_H_GR (gr + 3, newval[3]); +} + +void +frvbf_h_fr_quad_set_handler (SIM_CPU *current_cpu, UINT fr, SI *newval) +{ + /* Check the register alignment. */ + fr = check_fr_register_alignment (current_cpu, fr, 3); + + SET_H_FR (fr , newval[0]); + SET_H_FR (fr + 1, newval[1]); + SET_H_FR (fr + 2, newval[2]); + SET_H_FR (fr + 3, newval[3]); +} + +void +frvbf_h_cpr_quad_set_handler (SIM_CPU *current_cpu, UINT cpr, SI *newval) +{ + /* Check the register alignment. */ + cpr = check_register_alignment (current_cpu, cpr, 3); + + SET_H_CPR (cpr , newval[0]); + SET_H_CPR (cpr + 1, newval[1]); + SET_H_CPR (cpr + 2, newval[2]); + SET_H_CPR (cpr + 3, newval[3]); +} + +/* Cover fns to access the special purpose registers. */ +USI +frvbf_h_spr_get_handler (SIM_CPU *current_cpu, UINT spr) +{ + /* Check access restrictions. */ + frv_check_spr_read_access (current_cpu, spr); + + switch (spr) + { + case H_SPR_PSR: + return spr_psr_get_handler (current_cpu); + case H_SPR_TBR: + return spr_tbr_get_handler (current_cpu); + case H_SPR_BPSR: + return spr_bpsr_get_handler (current_cpu); + case H_SPR_CCR: + return spr_ccr_get_handler (current_cpu); + case H_SPR_CCCR: + return spr_cccr_get_handler (current_cpu); + case H_SPR_SR0: + case H_SPR_SR1: + case H_SPR_SR2: + case H_SPR_SR3: + return spr_sr_get_handler (current_cpu, spr); + break; + default: + return CPU (h_spr[spr]); + } + return 0; +} + +void +frvbf_h_spr_set_handler (SIM_CPU *current_cpu, UINT spr, USI newval) +{ + FRV_REGISTER_CONTROL *control; + USI mask; + USI oldval; + + /* Check access restrictions. */ + frv_check_spr_write_access (current_cpu, spr); + + /* Only set those fields which are writeable. */ + control = CPU_REGISTER_CONTROL (current_cpu); + mask = control->spr[spr].read_only_mask; + oldval = GET_H_SPR (spr); + + newval = (newval & ~mask) | (oldval & mask); + + /* Some registers are represented by individual components which are + referenced more often than the register itself. */ + switch (spr) + { + case H_SPR_PSR: + spr_psr_set_handler (current_cpu, newval); + break; + case H_SPR_TBR: + spr_tbr_set_handler (current_cpu, newval); + break; + case H_SPR_BPSR: + spr_bpsr_set_handler (current_cpu, newval); + break; + case H_SPR_CCR: + spr_ccr_set_handler (current_cpu, newval); + break; + case H_SPR_CCCR: + spr_cccr_set_handler (current_cpu, newval); + break; + case H_SPR_SR0: + case H_SPR_SR1: + case H_SPR_SR2: + case H_SPR_SR3: + spr_sr_set_handler (current_cpu, spr, newval); + break; + case H_SPR_IHSR8: + frv_cache_reconfigure (current_cpu, CPU_INSN_CACHE (current_cpu)); + break; + default: + CPU (h_spr[spr]) = newval; + break; + } +} + +/* Cover fns to access the gr_hi and gr_lo registers. */ +UHI +frvbf_h_gr_hi_get_handler (SIM_CPU *current_cpu, UINT gr) +{ + return (GET_H_GR(gr) >> 16) & 0xffff; +} + +void +frvbf_h_gr_hi_set_handler (SIM_CPU *current_cpu, UINT gr, UHI newval) +{ + USI value = (GET_H_GR (gr) & 0xffff) | (newval << 16); + SET_H_GR (gr, value); +} + +UHI +frvbf_h_gr_lo_get_handler (SIM_CPU *current_cpu, UINT gr) +{ + return GET_H_GR(gr) & 0xffff; +} + +void +frvbf_h_gr_lo_set_handler (SIM_CPU *current_cpu, UINT gr, UHI newval) +{ + USI value = (GET_H_GR (gr) & 0xffff0000) | (newval & 0xffff); + SET_H_GR (gr, value); +} + +/* Cover fns to access the tbr bits. */ +USI +spr_tbr_get_handler (SIM_CPU *current_cpu) +{ + int tbr = ((GET_H_TBR_TBA () & 0xfffff) << 12) | + ((GET_H_TBR_TT () & 0xff) << 4); + + return tbr; +} + +void +spr_tbr_set_handler (SIM_CPU *current_cpu, USI newval) +{ + int tbr = newval; + + SET_H_TBR_TBA ((tbr >> 12) & 0xfffff) ; + SET_H_TBR_TT ((tbr >> 4) & 0xff) ; +} + +/* Cover fns to access the bpsr bits. */ +USI +spr_bpsr_get_handler (SIM_CPU *current_cpu) +{ + int bpsr = ((GET_H_BPSR_BS () & 0x1) << 12) | + ((GET_H_BPSR_BET () & 0x1) ); + + return bpsr; +} + +void +spr_bpsr_set_handler (SIM_CPU *current_cpu, USI newval) +{ + int bpsr = newval; + + SET_H_BPSR_BS ((bpsr >> 12) & 1); + SET_H_BPSR_BET ((bpsr ) & 1); +} + +/* Cover fns to access the psr bits. */ +USI +spr_psr_get_handler (SIM_CPU *current_cpu) +{ + int psr = ((GET_H_PSR_IMPLE () & 0xf) << 28) | + ((GET_H_PSR_VER () & 0xf) << 24) | + ((GET_H_PSR_ICE () & 0x1) << 16) | + ((GET_H_PSR_NEM () & 0x1) << 14) | + ((GET_H_PSR_CM () & 0x1) << 13) | + ((GET_H_PSR_BE () & 0x1) << 12) | + ((GET_H_PSR_ESR () & 0x1) << 11) | + ((GET_H_PSR_EF () & 0x1) << 8) | + ((GET_H_PSR_EM () & 0x1) << 7) | + ((GET_H_PSR_PIL () & 0xf) << 3) | + ((GET_H_PSR_S () & 0x1) << 2) | + ((GET_H_PSR_PS () & 0x1) << 1) | + ((GET_H_PSR_ET () & 0x1) ); + + return psr; +} + +void +spr_psr_set_handler (SIM_CPU *current_cpu, USI newval) +{ + /* The handler for PSR.S references the value of PSR.ESR, so set PSR.S + first. */ + SET_H_PSR_S ((newval >> 2) & 1); + + SET_H_PSR_IMPLE ((newval >> 28) & 0xf); + SET_H_PSR_VER ((newval >> 24) & 0xf); + SET_H_PSR_ICE ((newval >> 16) & 1); + SET_H_PSR_NEM ((newval >> 14) & 1); + SET_H_PSR_CM ((newval >> 13) & 1); + SET_H_PSR_BE ((newval >> 12) & 1); + SET_H_PSR_ESR ((newval >> 11) & 1); + SET_H_PSR_EF ((newval >> 8) & 1); + SET_H_PSR_EM ((newval >> 7) & 1); + SET_H_PSR_PIL ((newval >> 3) & 0xf); + SET_H_PSR_PS ((newval >> 1) & 1); + SET_H_PSR_ET ((newval ) & 1); +} + +void +frvbf_h_psr_s_set_handler (SIM_CPU *current_cpu, BI newval) +{ + /* If switching from user to supervisor mode, or vice-versa, then switch + the supervisor/user context. */ + int psr_s = GET_H_PSR_S (); + if (psr_s != (newval & 1)) + { + frvbf_switch_supervisor_user_context (current_cpu); + CPU (h_psr_s) = newval & 1; + } +} + +/* Cover fns to access the ccr bits. */ +USI +spr_ccr_get_handler (SIM_CPU *current_cpu) +{ + int ccr = ((GET_H_ICCR (H_ICCR_ICC3) & 0xf) << 28) | + ((GET_H_ICCR (H_ICCR_ICC2) & 0xf) << 24) | + ((GET_H_ICCR (H_ICCR_ICC1) & 0xf) << 20) | + ((GET_H_ICCR (H_ICCR_ICC0) & 0xf) << 16) | + ((GET_H_FCCR (H_FCCR_FCC3) & 0xf) << 12) | + ((GET_H_FCCR (H_FCCR_FCC2) & 0xf) << 8) | + ((GET_H_FCCR (H_FCCR_FCC1) & 0xf) << 4) | + ((GET_H_FCCR (H_FCCR_FCC0) & 0xf) ); + + return ccr; +} + +void +spr_ccr_set_handler (SIM_CPU *current_cpu, USI newval) +{ + int ccr = newval; + + SET_H_ICCR (H_ICCR_ICC3, (newval >> 28) & 0xf); + SET_H_ICCR (H_ICCR_ICC2, (newval >> 24) & 0xf); + SET_H_ICCR (H_ICCR_ICC1, (newval >> 20) & 0xf); + SET_H_ICCR (H_ICCR_ICC0, (newval >> 16) & 0xf); + SET_H_FCCR (H_FCCR_FCC3, (newval >> 12) & 0xf); + SET_H_FCCR (H_FCCR_FCC2, (newval >> 8) & 0xf); + SET_H_FCCR (H_FCCR_FCC1, (newval >> 4) & 0xf); + SET_H_FCCR (H_FCCR_FCC0, (newval ) & 0xf); +} + +QI +frvbf_set_icc_for_shift_right ( + SIM_CPU *current_cpu, SI value, SI shift, QI icc +) +{ + /* Set the C flag of the given icc to the logical OR of the bits shifted + out. */ + int mask = (1 << shift) - 1; + if ((value & mask) != 0) + return icc | 0x1; + + return icc & 0xe; +} + +QI +frvbf_set_icc_for_shift_left ( + SIM_CPU *current_cpu, SI value, SI shift, QI icc +) +{ + /* Set the V flag of the given icc to the logical OR of the bits shifted + out. */ + int mask = ((1 << shift) - 1) << (32 - shift); + if ((value & mask) != 0) + return icc | 0x2; + + return icc & 0xd; +} + +/* Cover fns to access the cccr bits. */ +USI +spr_cccr_get_handler (SIM_CPU *current_cpu) +{ + int cccr = ((GET_H_CCCR (H_CCCR_CC7) & 0x3) << 14) | + ((GET_H_CCCR (H_CCCR_CC6) & 0x3) << 12) | + ((GET_H_CCCR (H_CCCR_CC5) & 0x3) << 10) | + ((GET_H_CCCR (H_CCCR_CC4) & 0x3) << 8) | + ((GET_H_CCCR (H_CCCR_CC3) & 0x3) << 6) | + ((GET_H_CCCR (H_CCCR_CC2) & 0x3) << 4) | + ((GET_H_CCCR (H_CCCR_CC1) & 0x3) << 2) | + ((GET_H_CCCR (H_CCCR_CC0) & 0x3) ); + + return cccr; +} + +void +spr_cccr_set_handler (SIM_CPU *current_cpu, USI newval) +{ + int cccr = newval; + + SET_H_CCCR (H_CCCR_CC7, (newval >> 14) & 0x3); + SET_H_CCCR (H_CCCR_CC6, (newval >> 12) & 0x3); + SET_H_CCCR (H_CCCR_CC5, (newval >> 10) & 0x3); + SET_H_CCCR (H_CCCR_CC4, (newval >> 8) & 0x3); + SET_H_CCCR (H_CCCR_CC3, (newval >> 6) & 0x3); + SET_H_CCCR (H_CCCR_CC2, (newval >> 4) & 0x3); + SET_H_CCCR (H_CCCR_CC1, (newval >> 2) & 0x3); + SET_H_CCCR (H_CCCR_CC0, (newval ) & 0x3); +} + +/* Cover fns to access the sr bits. */ +USI +spr_sr_get_handler (SIM_CPU *current_cpu, UINT spr) +{ + /* If PSR.ESR is not set, then SR0-3 map onto SGR4-7 which will be GR4-7, + otherwise the correct mapping of USG4-7 or SGR4-7 will be in SR0-3. */ + int psr_esr = GET_H_PSR_ESR (); + if (! psr_esr) + return GET_H_GR (4 + (spr - H_SPR_SR0)); + + return CPU (h_spr[spr]); +} + +void +spr_sr_set_handler (SIM_CPU *current_cpu, UINT spr, USI newval) +{ + /* If PSR.ESR is not set, then SR0-3 map onto SGR4-7 which will be GR4-7, + otherwise the correct mapping of USG4-7 or SGR4-7 will be in SR0-3. */ + int psr_esr = GET_H_PSR_ESR (); + if (! psr_esr) + SET_H_GR (4 + (spr - H_SPR_SR0), newval); + else + CPU (h_spr[spr]) = newval; +} + +/* Switch SR0-SR4 with GR4-GR7 if PSR.ESR is set. */ +void +frvbf_switch_supervisor_user_context (SIM_CPU *current_cpu) +{ + if (GET_H_PSR_ESR ()) + { + /* We need to be in supervisor mode to swap the registers. Access the + PSR.S directly in order to avoid recursive context switches. */ + int i; + int save_psr_s = CPU (h_psr_s); + CPU (h_psr_s) = 1; + for (i = 0; i < 4; ++i) + { + int gr = i + 4; + int spr = i + H_SPR_SR0; + SI tmp = GET_H_SPR (spr); + SET_H_SPR (spr, GET_H_GR (gr)); + SET_H_GR (gr, tmp); + } + CPU (h_psr_s) = save_psr_s; + } +} + +/* Handle load/store of quad registers. */ +void +frvbf_load_quad_GR (SIM_CPU *current_cpu, PCADDR pc, SI address, SI targ_ix) +{ + int i; + SI value[4]; + + /* Check memory alignment */ + address = check_memory_alignment (current_cpu, address, 0xf); + + /* If we need to count cycles, then the cache operation will be + initiated from the model profiling functions. + See frvbf_model_.... */ + if (model_insn) + { + CPU_LOAD_ADDRESS (current_cpu) = address; + CPU_LOAD_LENGTH (current_cpu) = 16; + } + else + { + for (i = 0; i < 4; ++i) + { + value[i] = frvbf_read_mem_SI (current_cpu, pc, address); + address += 4; + } + sim_queue_fn_xi_write (current_cpu, frvbf_h_gr_quad_set_handler, targ_ix, + value); + } +} + +void +frvbf_store_quad_GR (SIM_CPU *current_cpu, PCADDR pc, SI address, SI src_ix) +{ + int i; + SI value[4]; + USI hsr0; + + /* Check register and memory alignment. */ + src_ix = check_register_alignment (current_cpu, src_ix, 3); + address = check_memory_alignment (current_cpu, address, 0xf); + + for (i = 0; i < 4; ++i) + { + /* GR0 is always 0. */ + if (src_ix == 0) + value[i] = 0; + else + value[i] = GET_H_GR (src_ix + i); + } + hsr0 = GET_HSR0 (); + if (GET_HSR0_DCE (hsr0)) + sim_queue_fn_mem_xi_write (current_cpu, frvbf_mem_set_XI, address, value); + else + sim_queue_mem_xi_write (current_cpu, address, value); +} + +void +frvbf_load_quad_FRint (SIM_CPU *current_cpu, PCADDR pc, SI address, SI targ_ix) +{ + int i; + SI value[4]; + + /* Check memory alignment */ + address = check_memory_alignment (current_cpu, address, 0xf); + + /* If we need to count cycles, then the cache operation will be + initiated from the model profiling functions. + See frvbf_model_.... */ + if (model_insn) + { + CPU_LOAD_ADDRESS (current_cpu) = address; + CPU_LOAD_LENGTH (current_cpu) = 16; + } + else + { + for (i = 0; i < 4; ++i) + { + value[i] = frvbf_read_mem_SI (current_cpu, pc, address); + address += 4; + } + sim_queue_fn_xi_write (current_cpu, frvbf_h_fr_quad_set_handler, targ_ix, + value); + } +} + +void +frvbf_store_quad_FRint (SIM_CPU *current_cpu, PCADDR pc, SI address, SI src_ix) +{ + int i; + SI value[4]; + USI hsr0; + + /* Check register and memory alignment. */ + src_ix = check_fr_register_alignment (current_cpu, src_ix, 3); + address = check_memory_alignment (current_cpu, address, 0xf); + + for (i = 0; i < 4; ++i) + value[i] = GET_H_FR (src_ix + i); + + hsr0 = GET_HSR0 (); + if (GET_HSR0_DCE (hsr0)) + sim_queue_fn_mem_xi_write (current_cpu, frvbf_mem_set_XI, address, value); + else + sim_queue_mem_xi_write (current_cpu, address, value); +} + +void +frvbf_load_quad_CPR (SIM_CPU *current_cpu, PCADDR pc, SI address, SI targ_ix) +{ + int i; + SI value[4]; + + /* Check memory alignment */ + address = check_memory_alignment (current_cpu, address, 0xf); + + /* If we need to count cycles, then the cache operation will be + initiated from the model profiling functions. + See frvbf_model_.... */ + if (model_insn) + { + CPU_LOAD_ADDRESS (current_cpu) = address; + CPU_LOAD_LENGTH (current_cpu) = 16; + } + else + { + for (i = 0; i < 4; ++i) + { + value[i] = frvbf_read_mem_SI (current_cpu, pc, address); + address += 4; + } + sim_queue_fn_xi_write (current_cpu, frvbf_h_cpr_quad_set_handler, targ_ix, + value); + } +} + +void +frvbf_store_quad_CPR (SIM_CPU *current_cpu, PCADDR pc, SI address, SI src_ix) +{ + int i; + SI value[4]; + USI hsr0; + + /* Check register and memory alignment. */ + src_ix = check_register_alignment (current_cpu, src_ix, 3); + address = check_memory_alignment (current_cpu, address, 0xf); + + for (i = 0; i < 4; ++i) + value[i] = GET_H_CPR (src_ix + i); + + hsr0 = GET_HSR0 (); + if (GET_HSR0_DCE (hsr0)) + sim_queue_fn_mem_xi_write (current_cpu, frvbf_mem_set_XI, address, value); + else + sim_queue_mem_xi_write (current_cpu, address, value); +} + +void +frvbf_signed_integer_divide ( + SIM_CPU *current_cpu, SI arg1, SI arg2, int target_index, int non_excepting +) +{ + enum frv_dtt dtt = FRV_DTT_NO_EXCEPTION; + if (arg1 == 0x80000000 && arg2 == -1) + { + /* 0x80000000/(-1) must result in 0x7fffffff when ISR.EDE is set + otherwise it may result in 0x7fffffff (sparc compatibility) or + 0x80000000 (C language compatibility). */ + USI isr; + dtt = FRV_DTT_OVERFLOW; + + isr = GET_ISR (); + if (GET_ISR_EDE (isr)) + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, target_index, + 0x7fffffff); + else + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, target_index, + 0x80000000); + frvbf_force_update (current_cpu); /* Force update of target register. */ + } + else if (arg2 == 0) + dtt = FRV_DTT_DIVISION_BY_ZERO; + else + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, target_index, + arg1 / arg2); + + /* Check for exceptions. */ + if (dtt != FRV_DTT_NO_EXCEPTION) + dtt = frvbf_division_exception (current_cpu, dtt, target_index, + non_excepting); + if (non_excepting && dtt == FRV_DTT_NO_EXCEPTION) + { + /* Non excepting instruction. Clear the NE flag for the target + register. */ + SI NE_flags[2]; + GET_NE_FLAGS (NE_flags, H_SPR_GNER0); + CLEAR_NE_FLAG (NE_flags, target_index); + SET_NE_FLAGS (H_SPR_GNER0, NE_flags); + } +} + +void +frvbf_unsigned_integer_divide ( + SIM_CPU *current_cpu, USI arg1, USI arg2, int target_index, int non_excepting +) +{ + if (arg2 == 0) + frvbf_division_exception (current_cpu, FRV_DTT_DIVISION_BY_ZERO, + target_index, non_excepting); + else + { + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, target_index, + arg1 / arg2); + if (non_excepting) + { + /* Non excepting instruction. Clear the NE flag for the target + register. */ + SI NE_flags[2]; + GET_NE_FLAGS (NE_flags, H_SPR_GNER0); + CLEAR_NE_FLAG (NE_flags, target_index); + SET_NE_FLAGS (H_SPR_GNER0, NE_flags); + } + } +} + +/* Clear accumulators. */ +void +frvbf_clear_accumulators (SIM_CPU *current_cpu, SI acc_ix, int A) +{ + SIM_DESC sd = CPU_STATE (current_cpu); + int acc_num = + (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr500) ? 8 : + (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550) ? 8 : + (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr400) ? 4 : + 63; + FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (current_cpu); + + ps->mclracc_acc = acc_ix; + ps->mclracc_A = A; + if (A == 0 || acc_ix != 0) /* Clear 1 accumuator? */ + { + /* This instruction is a nop if the referenced accumulator is not + implemented. */ + if (acc_ix < acc_num) + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, acc_ix, 0); + } + else + { + /* Clear all implemented accumulators. */ + int i; + for (i = 0; i < acc_num; ++i) + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, i, 0); + } +} + +/* Functions to aid insn semantics. */ + +/* Compute the result of the SCAN and SCANI insns after the shift and xor. */ +SI +frvbf_scan_result (SIM_CPU *current_cpu, SI value) +{ + SI i; + SI mask; + + if (value == 0) + return 63; + + /* Find the position of the first non-zero bit. + The loop will terminate since there is guaranteed to be at least one + non-zero bit. */ + mask = 1 << (sizeof (mask) * 8 - 1); + for (i = 0; (value & mask) == 0; ++i) + value <<= 1; + + return i; +} + +/* Compute the result of the cut insns. */ +SI +frvbf_cut (SIM_CPU *current_cpu, SI reg1, SI reg2, SI cut_point) +{ + SI result; + if (cut_point < 32) + { + result = reg1 << cut_point; + result |= (reg2 >> (32 - cut_point)) & ((1 << cut_point) - 1); + } + else + result = reg2 << (cut_point - 32); + + return result; +} + +/* Compute the result of the cut insns. */ +SI +frvbf_media_cut (SIM_CPU *current_cpu, DI acc, SI cut_point) +{ + /* The cut point is the lower 6 bits (signed) of what we are passed. */ + cut_point = cut_point << 26 >> 26; + + /* The cut_point is relative to bit 40 of 64 bits. */ + if (cut_point >= 0) + return (acc << (cut_point + 24)) >> 32; + + /* Extend the sign bit (bit 40) for negative cuts. */ + if (cut_point == -32) + return (acc << 24) >> 63; /* Special case for full shiftout. */ + + return (acc << 24) >> (32 + -cut_point); +} + +/* Compute the result of the cut insns. */ +SI +frvbf_media_cut_ss (SIM_CPU *current_cpu, DI acc, SI cut_point) +{ + /* The cut point is the lower 6 bits (signed) of what we are passed. */ + cut_point = cut_point << 26 >> 26; + + if (cut_point >= 0) + { + /* The cut_point is relative to bit 40 of 64 bits. */ + DI shifted = acc << (cut_point + 24); + DI unshifted = shifted >> (cut_point + 24); + + /* The result will be saturated if significant bits are shifted out. */ + if (unshifted != acc) + { + if (acc < 0) + return 0x80000000; + return 0x7fffffff; + } + } + + /* The result will not be saturated, so use the code for the normal cut. */ + return frvbf_media_cut (current_cpu, acc, cut_point); +} + +/* Compute the result of int accumulator cut (SCUTSS). */ +SI +frvbf_iacc_cut (SIM_CPU *current_cpu, DI acc, SI cut_point) +{ + /* The cut point is the lower 6 bits (signed) of what we are passed. */ + cut_point = cut_point << 25 >> 25; + + if (cut_point <= -32) + cut_point = -31; /* Special case for full shiftout. */ + + /* Negative cuts (cannot saturate). */ + if (cut_point < 0) + return acc >> (32 + -cut_point); + + /* Positive cuts will saturate if significant bits are shifted out. */ + if (acc != ((acc << cut_point) >> cut_point)) + if (acc >= 0) + return 0x7fffffff; + else + return 0x80000000; + + /* No saturate, just cut. */ + return ((acc << cut_point) >> 32); +} + +/* Compute the result of shift-left-arithmetic-with-saturation (SLASS). */ +SI +frvbf_shift_left_arith_saturate (SIM_CPU *current_cpu, SI arg1, SI arg2) +{ + int neg_arg1; + + /* FIXME: what to do with negative shift amt? */ + if (arg2 <= 0) + return arg1; + + if (arg1 == 0) + return 0; + + /* Signed shift by 31 or greater saturates by definition. */ + if (arg2 >= 31) + if (arg1 > 0) + return (SI) 0x7fffffff; + else + return (SI) 0x80000000; + + /* OK, arg2 is between 1 and 31. */ + neg_arg1 = (arg1 < 0); + do { + arg1 <<= 1; + /* Check for sign bit change (saturation). */ + if (neg_arg1 && (arg1 >= 0)) + return (SI) 0x80000000; + else if (!neg_arg1 && (arg1 < 0)) + return (SI) 0x7fffffff; + } while (--arg2 > 0); + + return arg1; +} + +/* Simulate the media custom insns. */ +void +frvbf_media_cop (SIM_CPU *current_cpu, int cop_num) +{ + /* The semantics of the insn are a nop, since it is implementation defined. + We do need to check whether it's implemented and set up for MTRAP + if it's not. */ + USI msr0 = GET_MSR (0); + if (GET_MSR_EMCI (msr0) == 0) + { + /* no interrupt queued at this time. */ + frv_set_mp_exception_registers (current_cpu, MTT_UNIMPLEMENTED_MPOP, 0); + } +} + +/* Simulate the media average (MAVEH) insn. */ +static HI +do_media_average (SIM_CPU *current_cpu, HI arg1, HI arg2) +{ + SIM_DESC sd = CPU_STATE (current_cpu); + SI sum = (arg1 + arg2); + HI result = sum >> 1; + int rounding_value; + + /* On fr400 and fr550, check the rounding mode. On other machines rounding is always + toward negative infinity and the result is already correctly rounded. */ + switch (STATE_ARCHITECTURE (sd)->mach) + { + /* Need to check rounding mode. */ + case bfd_mach_fr400: + case bfd_mach_fr550: + /* Check whether rounding will be required. Rounding will be required + if the sum is an odd number. */ + rounding_value = sum & 1; + if (rounding_value) + { + USI msr0 = GET_MSR (0); + /* Check MSR0.SRDAV to determine which bits control the rounding. */ + if (GET_MSR_SRDAV (msr0)) + { + /* MSR0.RD controls rounding. */ + switch (GET_MSR_RD (msr0)) + { + case 0: + /* Round to nearest. */ + if (result >= 0) + ++result; + break; + case 1: + /* Round toward 0. */ + if (result < 0) + ++result; + break; + case 2: + /* Round toward positive infinity. */ + ++result; + break; + case 3: + /* Round toward negative infinity. The result is already + correctly rounded. */ + break; + default: + abort (); + break; + } + } + else + { + /* MSR0.RDAV controls rounding. If set, round toward positive + infinity. Otherwise the result is already rounded correctly + toward negative infinity. */ + if (GET_MSR_RDAV (msr0)) + ++result; + } + } + break; + default: + break; + } + + return result; +} + +SI +frvbf_media_average (SIM_CPU *current_cpu, SI reg1, SI reg2) +{ + SI result; + result = do_media_average (current_cpu, reg1 & 0xffff, reg2 & 0xffff); + result &= 0xffff; + result |= do_media_average (current_cpu, (reg1 >> 16) & 0xffff, + (reg2 >> 16) & 0xffff) << 16; + return result; +} + +/* Maintain a flag in order to know when to write the address of the next + VLIW instruction into the LR register. Used by JMPL. JMPIL, and CALL. */ +void +frvbf_set_write_next_vliw_addr_to_LR (SIM_CPU *current_cpu, int value) +{ + frvbf_write_next_vliw_addr_to_LR = value; +} + +void +frvbf_set_ne_index (SIM_CPU *current_cpu, int index) +{ + USI NE_flags[2]; + + /* Save the target register so interrupt processing can set its NE flag + in the event of an exception. */ + frv_interrupt_state.ne_index = index; + + /* Clear the NE flag of the target register. It will be reset if necessary + in the event of an exception. */ + GET_NE_FLAGS (NE_flags, H_SPR_FNER0); + CLEAR_NE_FLAG (NE_flags, index); + SET_NE_FLAGS (H_SPR_FNER0, NE_flags); +} + +void +frvbf_force_update (SIM_CPU *current_cpu) +{ + CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (current_cpu); + int ix = CGEN_WRITE_QUEUE_INDEX (q); + if (ix > 0) + { + CGEN_WRITE_QUEUE_ELEMENT *item = CGEN_WRITE_QUEUE_ELEMENT (q, ix - 1); + item->flags |= FRV_WRITE_QUEUE_FORCE_WRITE; + } +} + +/* Condition code logic. */ +enum cr_ops { + andcr, orcr, xorcr, nandcr, norcr, andncr, orncr, nandncr, norncr, + num_cr_ops +}; + +enum cr_result {cr_undefined, cr_undefined1, cr_false, cr_true}; + +static enum cr_result +cr_logic[num_cr_ops][4][4] = { + /* andcr */ + { + /* undefined undefined false true */ + /* undefined */ {cr_undefined, cr_undefined, cr_undefined, cr_undefined}, + /* undefined */ {cr_undefined, cr_undefined, cr_undefined, cr_undefined}, + /* false */ {cr_undefined, cr_undefined, cr_undefined, cr_undefined}, + /* true */ {cr_undefined, cr_undefined, cr_false, cr_true } + }, + /* orcr */ + { + /* undefined undefined false true */ + /* undefined */ {cr_undefined, cr_undefined, cr_false, cr_true }, + /* undefined */ {cr_undefined, cr_undefined, cr_false, cr_true }, + /* false */ {cr_false, cr_false, cr_false, cr_true }, + /* true */ {cr_true, cr_true, cr_true, cr_true } + }, + /* xorcr */ + { + /* undefined undefined false true */ + /* undefined */ {cr_undefined, cr_undefined, cr_undefined, cr_undefined}, + /* undefined */ {cr_undefined, cr_undefined, cr_undefined, cr_undefined}, + /* false */ {cr_undefined, cr_undefined, cr_false, cr_true }, + /* true */ {cr_true, cr_true, cr_true, cr_false } + }, + /* nandcr */ + { + /* undefined undefined false true */ + /* undefined */ {cr_undefined, cr_undefined, cr_undefined, cr_undefined}, + /* undefined */ {cr_undefined, cr_undefined, cr_undefined, cr_undefined}, + /* false */ {cr_undefined, cr_undefined, cr_undefined, cr_undefined}, + /* true */ {cr_undefined, cr_undefined, cr_true, cr_false } + }, + /* norcr */ + { + /* undefined undefined false true */ + /* undefined */ {cr_undefined, cr_undefined, cr_true, cr_false }, + /* undefined */ {cr_undefined, cr_undefined, cr_true, cr_false }, + /* false */ {cr_true, cr_true, cr_true, cr_false }, + /* true */ {cr_false, cr_false, cr_false, cr_false } + }, + /* andncr */ + { + /* undefined undefined false true */ + /* undefined */ {cr_undefined, cr_undefined, cr_undefined, cr_undefined}, + /* undefined */ {cr_undefined, cr_undefined, cr_undefined, cr_undefined}, + /* false */ {cr_undefined, cr_undefined, cr_false, cr_true }, + /* true */ {cr_undefined, cr_undefined, cr_undefined, cr_undefined} + }, + /* orncr */ + { + /* undefined undefined false true */ + /* undefined */ {cr_undefined, cr_undefined, cr_false, cr_true }, + /* undefined */ {cr_undefined, cr_undefined, cr_false, cr_true }, + /* false */ {cr_true, cr_true, cr_true, cr_true }, + /* true */ {cr_false, cr_false, cr_false, cr_true } + }, + /* nandncr */ + { + /* undefined undefined false true */ + /* undefined */ {cr_undefined, cr_undefined, cr_undefined, cr_undefined}, + /* undefined */ {cr_undefined, cr_undefined, cr_undefined, cr_undefined}, + /* false */ {cr_undefined, cr_undefined, cr_true, cr_false }, + /* true */ {cr_undefined, cr_undefined, cr_undefined, cr_undefined} + }, + /* norncr */ + { + /* undefined undefined false true */ + /* undefined */ {cr_undefined, cr_undefined, cr_true, cr_false }, + /* undefined */ {cr_undefined, cr_undefined, cr_true, cr_false }, + /* false */ {cr_false, cr_false, cr_false, cr_false }, + /* true */ {cr_true, cr_true, cr_true, cr_false } + } +}; + +UQI +frvbf_cr_logic (SIM_CPU *current_cpu, SI operation, UQI arg1, UQI arg2) +{ + return cr_logic[operation][arg1][arg2]; +} + +/* Cache Manipulation. */ +void +frvbf_insn_cache_preload (SIM_CPU *current_cpu, SI address, USI length, int lock) +{ + /* If we need to count cycles, then the cache operation will be + initiated from the model profiling functions. + See frvbf_model_.... */ + int hsr0 = GET_HSR0 (); + if (GET_HSR0_ICE (hsr0)) + { + if (model_insn) + { + CPU_LOAD_ADDRESS (current_cpu) = address; + CPU_LOAD_LENGTH (current_cpu) = length; + CPU_LOAD_LOCK (current_cpu) = lock; + } + else + { + FRV_CACHE *cache = CPU_INSN_CACHE (current_cpu); + frv_cache_preload (cache, address, length, lock); + } + } +} + +void +frvbf_data_cache_preload (SIM_CPU *current_cpu, SI address, USI length, int lock) +{ + /* If we need to count cycles, then the cache operation will be + initiated from the model profiling functions. + See frvbf_model_.... */ + int hsr0 = GET_HSR0 (); + if (GET_HSR0_DCE (hsr0)) + { + if (model_insn) + { + CPU_LOAD_ADDRESS (current_cpu) = address; + CPU_LOAD_LENGTH (current_cpu) = length; + CPU_LOAD_LOCK (current_cpu) = lock; + } + else + { + FRV_CACHE *cache = CPU_DATA_CACHE (current_cpu); + frv_cache_preload (cache, address, length, lock); + } + } +} + +void +frvbf_insn_cache_unlock (SIM_CPU *current_cpu, SI address) +{ + /* If we need to count cycles, then the cache operation will be + initiated from the model profiling functions. + See frvbf_model_.... */ + int hsr0 = GET_HSR0 (); + if (GET_HSR0_ICE (hsr0)) + { + if (model_insn) + CPU_LOAD_ADDRESS (current_cpu) = address; + else + { + FRV_CACHE *cache = CPU_INSN_CACHE (current_cpu); + frv_cache_unlock (cache, address); + } + } +} + +void +frvbf_data_cache_unlock (SIM_CPU *current_cpu, SI address) +{ + /* If we need to count cycles, then the cache operation will be + initiated from the model profiling functions. + See frvbf_model_.... */ + int hsr0 = GET_HSR0 (); + if (GET_HSR0_DCE (hsr0)) + { + if (model_insn) + CPU_LOAD_ADDRESS (current_cpu) = address; + else + { + FRV_CACHE *cache = CPU_DATA_CACHE (current_cpu); + frv_cache_unlock (cache, address); + } + } +} + +void +frvbf_insn_cache_invalidate (SIM_CPU *current_cpu, SI address, int all) +{ + /* Make sure the insn was specified properly. -1 will be passed for ALL + for a icei with A=0. */ + if (all == -1) + { + frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION); + return; + } + + /* If we need to count cycles, then the cache operation will be + initiated from the model profiling functions. + See frvbf_model_.... */ + if (model_insn) + { + /* Record the all-entries flag for use in profiling. */ + FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (current_cpu); + ps->all_cache_entries = all; + CPU_LOAD_ADDRESS (current_cpu) = address; + } + else + { + FRV_CACHE *cache = CPU_INSN_CACHE (current_cpu); + if (all) + frv_cache_invalidate_all (cache, 0/* flush? */); + else + frv_cache_invalidate (cache, address, 0/* flush? */); + } +} + +void +frvbf_data_cache_invalidate (SIM_CPU *current_cpu, SI address, int all) +{ + /* Make sure the insn was specified properly. -1 will be passed for ALL + for a dcei with A=0. */ + if (all == -1) + { + frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION); + return; + } + + /* If we need to count cycles, then the cache operation will be + initiated from the model profiling functions. + See frvbf_model_.... */ + if (model_insn) + { + /* Record the all-entries flag for use in profiling. */ + FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (current_cpu); + ps->all_cache_entries = all; + CPU_LOAD_ADDRESS (current_cpu) = address; + } + else + { + FRV_CACHE *cache = CPU_DATA_CACHE (current_cpu); + if (all) + frv_cache_invalidate_all (cache, 0/* flush? */); + else + frv_cache_invalidate (cache, address, 0/* flush? */); + } +} + +void +frvbf_data_cache_flush (SIM_CPU *current_cpu, SI address, int all) +{ + /* Make sure the insn was specified properly. -1 will be passed for ALL + for a dcef with A=0. */ + if (all == -1) + { + frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION); + return; + } + + /* If we need to count cycles, then the cache operation will be + initiated from the model profiling functions. + See frvbf_model_.... */ + if (model_insn) + { + /* Record the all-entries flag for use in profiling. */ + FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (current_cpu); + ps->all_cache_entries = all; + CPU_LOAD_ADDRESS (current_cpu) = address; + } + else + { + FRV_CACHE *cache = CPU_DATA_CACHE (current_cpu); + if (all) + frv_cache_invalidate_all (cache, 1/* flush? */); + else + frv_cache_invalidate (cache, address, 1/* flush? */); + } +} diff --git a/sim/frv/interrupts.c b/sim/frv/interrupts.c new file mode 100644 index 0000000..540ee06 --- /dev/null +++ b/sim/frv/interrupts.c @@ -0,0 +1,1412 @@ +/* frv exception and interrupt support + Copyright (C) 1999, 2000, 2001 Free Software Foundation, Inc. + Contributed by Red Hat. + +This file is part of the GNU simulators. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#define WANT_CPU frvbf +#define WANT_CPU_FRVBF + +#include "sim-main.h" +#include "bfd.h" + +/* FR-V Interrupt table. + Describes the interrupts supported by the FR-V. + This table *must* be maintained in order of interrupt priority as defined by + frv_interrupt_kind. */ +#define DEFERRED 1 +#define PRECISE 1 +#define ITABLE_ENTRY(name, class, deferral, precision, offset) \ + {FRV_##name, FRV_EC_##name, class, deferral, precision, offset} + +struct frv_interrupt frv_interrupt_table[NUM_FRV_INTERRUPT_KINDS] = +{ + /* External interrupts */ + ITABLE_ENTRY(INTERRUPT_LEVEL_1, FRV_EXTERNAL_INTERRUPT, !DEFERRED, !PRECISE, 0x21), + ITABLE_ENTRY(INTERRUPT_LEVEL_2, FRV_EXTERNAL_INTERRUPT, !DEFERRED, !PRECISE, 0x22), + ITABLE_ENTRY(INTERRUPT_LEVEL_3, FRV_EXTERNAL_INTERRUPT, !DEFERRED, !PRECISE, 0x23), + ITABLE_ENTRY(INTERRUPT_LEVEL_4, FRV_EXTERNAL_INTERRUPT, !DEFERRED, !PRECISE, 0x24), + ITABLE_ENTRY(INTERRUPT_LEVEL_5, FRV_EXTERNAL_INTERRUPT, !DEFERRED, !PRECISE, 0x25), + ITABLE_ENTRY(INTERRUPT_LEVEL_6, FRV_EXTERNAL_INTERRUPT, !DEFERRED, !PRECISE, 0x26), + ITABLE_ENTRY(INTERRUPT_LEVEL_7, FRV_EXTERNAL_INTERRUPT, !DEFERRED, !PRECISE, 0x27), + ITABLE_ENTRY(INTERRUPT_LEVEL_8, FRV_EXTERNAL_INTERRUPT, !DEFERRED, !PRECISE, 0x28), + ITABLE_ENTRY(INTERRUPT_LEVEL_9, FRV_EXTERNAL_INTERRUPT, !DEFERRED, !PRECISE, 0x29), + ITABLE_ENTRY(INTERRUPT_LEVEL_10, FRV_EXTERNAL_INTERRUPT, !DEFERRED, !PRECISE, 0x2a), + ITABLE_ENTRY(INTERRUPT_LEVEL_11, FRV_EXTERNAL_INTERRUPT, !DEFERRED, !PRECISE, 0x2b), + ITABLE_ENTRY(INTERRUPT_LEVEL_12, FRV_EXTERNAL_INTERRUPT, !DEFERRED, !PRECISE, 0x2c), + ITABLE_ENTRY(INTERRUPT_LEVEL_13, FRV_EXTERNAL_INTERRUPT, !DEFERRED, !PRECISE, 0x2d), + ITABLE_ENTRY(INTERRUPT_LEVEL_14, FRV_EXTERNAL_INTERRUPT, !DEFERRED, !PRECISE, 0x2e), + ITABLE_ENTRY(INTERRUPT_LEVEL_15, FRV_EXTERNAL_INTERRUPT, !DEFERRED, !PRECISE, 0x2f), + /* Software interrupt */ + ITABLE_ENTRY(TRAP_INSTRUCTION, FRV_SOFTWARE_INTERRUPT, !DEFERRED, !PRECISE, 0x80), + /* Program interrupts */ + ITABLE_ENTRY(COMMIT_EXCEPTION, FRV_PROGRAM_INTERRUPT, !DEFERRED, !PRECISE, 0x19), + ITABLE_ENTRY(DIVISION_EXCEPTION, FRV_PROGRAM_INTERRUPT, !DEFERRED, !PRECISE, 0x17), + ITABLE_ENTRY(DATA_STORE_ERROR, FRV_PROGRAM_INTERRUPT, !DEFERRED, !PRECISE, 0x14), + ITABLE_ENTRY(DATA_ACCESS_EXCEPTION, FRV_PROGRAM_INTERRUPT, !DEFERRED, !PRECISE, 0x13), + ITABLE_ENTRY(DATA_ACCESS_MMU_MISS, FRV_PROGRAM_INTERRUPT, !DEFERRED, !PRECISE, 0x12), + ITABLE_ENTRY(DATA_ACCESS_ERROR, FRV_PROGRAM_INTERRUPT, !DEFERRED, !PRECISE, 0x11), + ITABLE_ENTRY(MP_EXCEPTION, FRV_PROGRAM_INTERRUPT, !DEFERRED, !PRECISE, 0x0e), + ITABLE_ENTRY(FP_EXCEPTION, FRV_PROGRAM_INTERRUPT, !DEFERRED, !PRECISE, 0x0d), + ITABLE_ENTRY(MEM_ADDRESS_NOT_ALIGNED, FRV_PROGRAM_INTERRUPT, !DEFERRED, !PRECISE, 0x10), + ITABLE_ENTRY(REGISTER_EXCEPTION, FRV_PROGRAM_INTERRUPT, !DEFERRED, PRECISE, 0x08), + ITABLE_ENTRY(MP_DISABLED, FRV_PROGRAM_INTERRUPT, !DEFERRED, PRECISE, 0x0b), + ITABLE_ENTRY(FP_DISABLED, FRV_PROGRAM_INTERRUPT, !DEFERRED, PRECISE, 0x0a), + ITABLE_ENTRY(PRIVILEGED_INSTRUCTION, FRV_PROGRAM_INTERRUPT, !DEFERRED, PRECISE, 0x06), + ITABLE_ENTRY(ILLEGAL_INSTRUCTION, FRV_PROGRAM_INTERRUPT, !DEFERRED, PRECISE, 0x07), + ITABLE_ENTRY(INSTRUCTION_ACCESS_EXCEPTION, FRV_PROGRAM_INTERRUPT, !DEFERRED, PRECISE, 0x03), + ITABLE_ENTRY(INSTRUCTION_ACCESS_ERROR, FRV_PROGRAM_INTERRUPT, !DEFERRED, PRECISE, 0x02), + ITABLE_ENTRY(INSTRUCTION_ACCESS_MMU_MISS, FRV_PROGRAM_INTERRUPT, !DEFERRED, PRECISE, 0x01), + ITABLE_ENTRY(COMPOUND_EXCEPTION, FRV_PROGRAM_INTERRUPT, !DEFERRED, !PRECISE, 0x20), + /* Break interrupt */ + ITABLE_ENTRY(BREAK_EXCEPTION, FRV_BREAK_INTERRUPT, !DEFERRED, !PRECISE, 0xff), + /* Reset interrupt */ + ITABLE_ENTRY(RESET, FRV_RESET_INTERRUPT, !DEFERRED, !PRECISE, 0x00) +}; + +/* The current interrupt state. */ +struct frv_interrupt_state frv_interrupt_state; + +/* maintain the address of the start of the previous VLIW insn sequence. */ +IADDR previous_vliw_pc; + +/* Add a break interrupt to the interrupt queue. */ +struct frv_interrupt_queue_element * +frv_queue_break_interrupt (SIM_CPU *current_cpu) +{ + return frv_queue_interrupt (current_cpu, FRV_BREAK_EXCEPTION); +} + +/* Add a software interrupt to the interrupt queue. */ +struct frv_interrupt_queue_element * +frv_queue_software_interrupt (SIM_CPU *current_cpu, SI offset) +{ + struct frv_interrupt_queue_element *new_element + = frv_queue_interrupt (current_cpu, FRV_TRAP_INSTRUCTION); + + struct frv_interrupt *interrupt = & frv_interrupt_table[new_element->kind]; + interrupt->handler_offset = offset; + + return new_element; +} + +/* Add a program interrupt to the interrupt queue. */ +struct frv_interrupt_queue_element * +frv_queue_program_interrupt ( + SIM_CPU *current_cpu, enum frv_interrupt_kind kind +) +{ + return frv_queue_interrupt (current_cpu, kind); +} + +/* Add an external interrupt to the interrupt queue. */ +struct frv_interrupt_queue_element * +frv_queue_external_interrupt ( + SIM_CPU *current_cpu, enum frv_interrupt_kind kind +) +{ + if (! GET_H_PSR_ET () + || (kind != FRV_INTERRUPT_LEVEL_15 && kind < GET_H_PSR_PIL ())) + return NULL; /* Leave it for later. */ + + return frv_queue_interrupt (current_cpu, kind); +} + +/* Add any interrupt to the interrupt queue. It will be added in reverse + priority order. This makes it easy to find the highest priority interrupt + at the end of the queue and to remove it after processing. */ +struct frv_interrupt_queue_element * +frv_queue_interrupt (SIM_CPU *current_cpu, enum frv_interrupt_kind kind) +{ + int i; + int j; + int limit = frv_interrupt_state.queue_index; + struct frv_interrupt_queue_element *new_element; + enum frv_interrupt_class iclass; + + if (limit >= FRV_INTERRUPT_QUEUE_SIZE) + abort (); /* TODO: Make the queue dynamic */ + + /* Find the right place in the queue. */ + for (i = 0; i < limit; ++i) + { + if (frv_interrupt_state.queue[i].kind >= kind) + break; + } + + /* Don't queue two external interrupts of the same priority. */ + iclass = frv_interrupt_table[kind].iclass; + if (i < limit && iclass == FRV_EXTERNAL_INTERRUPT) + { + if (frv_interrupt_state.queue[i].kind == kind) + return & frv_interrupt_state.queue[i]; + } + + /* Make room for the new interrupt in this spot. */ + for (j = limit - 1; j >= i; --j) + frv_interrupt_state.queue[j + 1] = frv_interrupt_state.queue[j]; + + /* Add the new interrupt. */ + frv_interrupt_state.queue_index++; + new_element = & frv_interrupt_state.queue[i]; + new_element->kind = kind; + new_element->vpc = CPU_PC_GET (current_cpu); + new_element->u.data_written.length = 0; + frv_set_interrupt_queue_slot (current_cpu, new_element); + + return new_element; +} + +struct frv_interrupt_queue_element * +frv_queue_register_exception_interrupt (SIM_CPU *current_cpu, enum frv_rec rec) +{ + struct frv_interrupt_queue_element *new_element = + frv_queue_program_interrupt (current_cpu, FRV_REGISTER_EXCEPTION); + + new_element->u.rec = rec; + + return new_element; +} + +struct frv_interrupt_queue_element * +frv_queue_mem_address_not_aligned_interrupt (SIM_CPU *current_cpu, USI addr) +{ + struct frv_interrupt_queue_element *new_element; + USI isr = GET_ISR (); + + /* Make sure that this exception is not masked. */ + if (GET_ISR_EMAM (isr)) + return NULL; + + /* Queue the interrupt. */ + new_element = frv_queue_program_interrupt (current_cpu, + FRV_MEM_ADDRESS_NOT_ALIGNED); + new_element->eaddress = addr; + new_element->u.data_written = frv_interrupt_state.data_written; + frv_interrupt_state.data_written.length = 0; + + return new_element; +} + +struct frv_interrupt_queue_element * +frv_queue_data_access_error_interrupt (SIM_CPU *current_cpu, USI addr) +{ + struct frv_interrupt_queue_element *new_element; + new_element = frv_queue_program_interrupt (current_cpu, + FRV_DATA_ACCESS_ERROR); + new_element->eaddress = addr; + return new_element; +} + +struct frv_interrupt_queue_element * +frv_queue_data_access_exception_interrupt (SIM_CPU *current_cpu) +{ + return frv_queue_program_interrupt (current_cpu, FRV_DATA_ACCESS_EXCEPTION); +} + +struct frv_interrupt_queue_element * +frv_queue_instruction_access_error_interrupt (SIM_CPU *current_cpu) +{ + return frv_queue_program_interrupt (current_cpu, FRV_INSTRUCTION_ACCESS_ERROR); +} + +struct frv_interrupt_queue_element * +frv_queue_instruction_access_exception_interrupt (SIM_CPU *current_cpu) +{ + return frv_queue_program_interrupt (current_cpu, FRV_INSTRUCTION_ACCESS_EXCEPTION); +} + +struct frv_interrupt_queue_element * +frv_queue_illegal_instruction_interrupt ( + SIM_CPU *current_cpu, const CGEN_INSN *insn +) +{ + SIM_DESC sd = CPU_STATE (current_cpu); + switch (STATE_ARCHITECTURE (sd)->mach) + { + case bfd_mach_fr400: + case bfd_mach_fr550: + break; + default: + /* Some machines generate fp_exception for this case. */ + if (frv_is_float_insn (insn) || frv_is_media_insn (insn)) + { + struct frv_fp_exception_info fp_info = { + FSR_NO_EXCEPTION, FTT_SEQUENCE_ERROR + }; + return frv_queue_fp_exception_interrupt (current_cpu, & fp_info); + } + break; + } + + return frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION); +} + +struct frv_interrupt_queue_element * +frv_queue_privileged_instruction_interrupt (SIM_CPU *current_cpu, const CGEN_INSN *insn) +{ + /* The fr550 has no privileged instruction interrupt. It uses + illegal_instruction. */ + SIM_DESC sd = CPU_STATE (current_cpu); + if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550) + return frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION); + + return frv_queue_program_interrupt (current_cpu, FRV_PRIVILEGED_INSTRUCTION); +} + +struct frv_interrupt_queue_element * +frv_queue_float_disabled_interrupt (SIM_CPU *current_cpu) +{ + /* The fr550 has no fp_disabled interrupt. It uses illegal_instruction. */ + SIM_DESC sd = CPU_STATE (current_cpu); + if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550) + return frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION); + + return frv_queue_program_interrupt (current_cpu, FRV_FP_DISABLED); +} + +struct frv_interrupt_queue_element * +frv_queue_media_disabled_interrupt (SIM_CPU *current_cpu) +{ + /* The fr550 has no mp_disabled interrupt. It uses illegal_instruction. */ + SIM_DESC sd = CPU_STATE (current_cpu); + if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550) + return frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION); + + return frv_queue_program_interrupt (current_cpu, FRV_MP_DISABLED); +} + +struct frv_interrupt_queue_element * +frv_queue_non_implemented_instruction_interrupt ( + SIM_CPU *current_cpu, const CGEN_INSN *insn +) +{ + SIM_DESC sd = CPU_STATE (current_cpu); + switch (STATE_ARCHITECTURE (sd)->mach) + { + case bfd_mach_fr400: + case bfd_mach_fr550: + break; + default: + /* Some machines generate fp_exception or mp_exception for this case. */ + if (frv_is_float_insn (insn)) + { + struct frv_fp_exception_info fp_info = { + FSR_NO_EXCEPTION, FTT_UNIMPLEMENTED_FPOP + }; + return frv_queue_fp_exception_interrupt (current_cpu, & fp_info); + } + if (frv_is_media_insn (insn)) + { + frv_set_mp_exception_registers (current_cpu, MTT_UNIMPLEMENTED_MPOP, + 0); + return NULL; /* no interrupt queued at this time. */ + } + break; + } + + return frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION); +} + +/* Queue the given fp_exception interrupt. Also update fp_info by removing + masked interrupts and updating the 'slot' flield. */ +struct frv_interrupt_queue_element * +frv_queue_fp_exception_interrupt ( + SIM_CPU *current_cpu, struct frv_fp_exception_info *fp_info +) +{ + SI fsr0 = GET_FSR (0); + int tem = GET_FSR_TEM (fsr0); + int aexc = GET_FSR_AEXC (fsr0); + struct frv_interrupt_queue_element *new_element = NULL; + + /* Update AEXC with the interrupts that are masked. */ + aexc |= fp_info->fsr_mask & ~tem; + SET_FSR_AEXC (fsr0, aexc); + SET_FSR (0, fsr0); + + /* update fsr_mask with the exceptions that are enabled. */ + fp_info->fsr_mask &= tem; + + /* If there is an unmasked interrupt then queue it, unless + this was a non-excepting insn, in which case simply set the NE + status registers. */ + if (frv_interrupt_state.ne_index != NE_NOFLAG + && fp_info->fsr_mask != FSR_NO_EXCEPTION) + { + SET_NE_FLAG (frv_interrupt_state.f_ne_flags, + frv_interrupt_state.ne_index); + /* TODO -- Set NESR for chips which support it. */ + new_element = NULL; + } + else if (fp_info->fsr_mask != FSR_NO_EXCEPTION + || fp_info->ftt == FTT_UNIMPLEMENTED_FPOP + || fp_info->ftt == FTT_SEQUENCE_ERROR + || fp_info->ftt == FTT_INVALID_FR) + { + new_element = frv_queue_program_interrupt (current_cpu, FRV_FP_EXCEPTION); + new_element->u.fp_info = *fp_info; + } + + return new_element; +} + +struct frv_interrupt_queue_element * +frv_queue_division_exception_interrupt (SIM_CPU *current_cpu, enum frv_dtt dtt) +{ + struct frv_interrupt_queue_element *new_element = + frv_queue_program_interrupt (current_cpu, FRV_DIVISION_EXCEPTION); + + new_element->u.dtt = dtt; + + return new_element; +} + +/* Check for interrupts caused by illegal insn access. These conditions are + checked in the order specified by the fr400 and fr500 LSI specs. */ +void +frv_detect_insn_access_interrupts (SIM_CPU *current_cpu, SCACHE *sc) +{ + + const CGEN_INSN *insn = sc->argbuf.idesc->idata; + SIM_DESC sd = CPU_STATE (current_cpu); + FRV_VLIW *vliw = CPU_VLIW (current_cpu); + + /* Check for vliw constraints. */ + if (vliw->constraint_violation) + frv_queue_illegal_instruction_interrupt (current_cpu, insn); + /* Check for non-excepting insns. */ + else if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_NON_EXCEPTING) + && ! GET_H_PSR_NEM ()) + frv_queue_non_implemented_instruction_interrupt (current_cpu, insn); + /* Check for conditional insns. */ + else if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_CONDITIONAL) + && ! GET_H_PSR_CM ()) + frv_queue_non_implemented_instruction_interrupt (current_cpu, insn); + /* Make sure floating point support is enabled. */ + else if (! GET_H_PSR_EF ()) + { + /* Generate fp_disabled if it is a floating point insn or if PSR.EM is + off and the insns accesses a fp register. */ + if (frv_is_float_insn (insn) + || (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR_ACCESS) + && ! GET_H_PSR_EM ())) + frv_queue_float_disabled_interrupt (current_cpu); + } + /* Make sure media support is enabled. */ + else if (! GET_H_PSR_EM ()) + { + /* Generate mp_disabled if it is a media insn. */ + if (frv_is_media_insn (insn) || CGEN_INSN_NUM (insn) == FRV_INSN_MTRAP) + frv_queue_media_disabled_interrupt (current_cpu); + } + /* Check for privileged insns. */ + else if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_PRIVILEGED) && + ! GET_H_PSR_S ()) + frv_queue_privileged_instruction_interrupt (current_cpu, insn); +#if 0 /* disable for now until we find out how FSR0.QNE gets reset. */ + else + { + /* Enter the halt state if FSR0.QNE is set and we are executing a + floating point insn, a media insn or an insn which access a FR + register. */ + SI fsr0 = GET_FSR (0); + if (GET_FSR_QNE (fsr0) + && (frv_is_float_insn (insn) || frv_is_media_insn (insn) + || CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR_ACCESS))) + { + sim_engine_halt (sd, current_cpu, NULL, GET_H_PC (), sim_stopped, + SIM_SIGINT); + } + } +#endif +} + +/* Record the current VLIW slot in the given interrupt queue element. */ +void +frv_set_interrupt_queue_slot ( + SIM_CPU *current_cpu, struct frv_interrupt_queue_element *item +) +{ + FRV_VLIW *vliw = CPU_VLIW (current_cpu); + int slot = vliw->next_slot - 1; + item->slot = (*vliw->current_vliw)[slot]; +} + +/* Handle an individual interrupt. */ +static void +handle_interrupt (SIM_CPU *current_cpu, IADDR pc) +{ + struct frv_interrupt *interrupt; + int writeback_done = 0; + while (1) + { + /* Interrupts are queued in priority order with the highest priority + last. */ + int index = frv_interrupt_state.queue_index - 1; + struct frv_interrupt_queue_element *item + = & frv_interrupt_state.queue[index]; + interrupt = & frv_interrupt_table[item->kind]; + + switch (interrupt->iclass) + { + case FRV_EXTERNAL_INTERRUPT: + /* Perform writeback first. This may cause a higher priority + interrupt. */ + if (! writeback_done) + { + frvbf_perform_writeback (current_cpu); + writeback_done = 1; + continue; + } + frv_external_interrupt (current_cpu, item, pc); + return; + case FRV_SOFTWARE_INTERRUPT: + frv_interrupt_state.queue_index = index; + frv_software_interrupt (current_cpu, item, pc); + return; + case FRV_PROGRAM_INTERRUPT: + /* If the program interrupt is not strict (imprecise), then perform + writeback first. This may, in turn, cause a higher priority + interrupt. */ + if (! interrupt->precise && ! writeback_done) + { + frv_interrupt_state.imprecise_interrupt = item; + frvbf_perform_writeback (current_cpu); + writeback_done = 1; + continue; + } + frv_interrupt_state.queue_index = index; + frv_program_interrupt (current_cpu, item, pc); + return; + case FRV_BREAK_INTERRUPT: + frv_interrupt_state.queue_index = index; + frv_break_interrupt (current_cpu, interrupt, pc); + return; + case FRV_RESET_INTERRUPT: + break; + default: + break; + } + frv_interrupt_state.queue_index = index; + break; /* out of loop. */ + } + + /* We should never get here. */ + { + SIM_DESC sd = CPU_STATE (current_cpu); + sim_engine_abort (sd, current_cpu, pc, + "interrupt class not supported %d\n", + interrupt->iclass); + } +} + +/* Check to see the if the RSTR.HR or RSTR.SR bits have been set. If so, handle + the appropriate reset interrupt. */ +static int +check_reset (SIM_CPU *current_cpu, IADDR pc) +{ + int hsr0; + int hr; + int sr; + SI rstr; + FRV_CACHE *cache = CPU_DATA_CACHE (current_cpu); + IADDR address = RSTR_ADDRESS; + + /* We don't want this to show up in the cache statistics, so read the + cache passively. */ + if (! frv_cache_read_passive_SI (cache, address, & rstr)) + rstr = sim_core_read_unaligned_4 (current_cpu, pc, read_map, address); + + hr = GET_RSTR_HR (rstr); + sr = GET_RSTR_SR (rstr); + + if (! hr && ! sr) + return 0; /* no reset. */ + + /* Reinitialize the machine state. */ + if (hr) + frv_hardware_reset (current_cpu); + else + frv_software_reset (current_cpu); + + /* Branch to the reset address. */ + hsr0 = GET_HSR0 (); + if (GET_HSR0_SA (hsr0)) + SET_H_PC (0xff000000); + else + SET_H_PC (0); + + return 1; /* reset */ +} + +/* Process any pending interrupt(s) after a group of parallel insns. */ +void +frv_process_interrupts (SIM_CPU *current_cpu) +{ + SI NE_flags[2]; + /* Need to save the pc here because writeback may change it (due to a + branch). */ + IADDR pc = CPU_PC_GET (current_cpu); + + /* Check for a reset before anything else. */ + if (check_reset (current_cpu, pc)) + return; + + /* First queue the writes for any accumulated NE flags. */ + if (frv_interrupt_state.f_ne_flags[0] != 0 + || frv_interrupt_state.f_ne_flags[1] != 0) + { + GET_NE_FLAGS (NE_flags, H_SPR_FNER0); + NE_flags[0] |= frv_interrupt_state.f_ne_flags[0]; + NE_flags[1] |= frv_interrupt_state.f_ne_flags[1]; + SET_NE_FLAGS (H_SPR_FNER0, NE_flags); + } + + /* If there is no interrupt pending, then perform parallel writeback. This + may cause an interrupt. */ + if (frv_interrupt_state.queue_index <= 0) + frvbf_perform_writeback (current_cpu); + + /* If there is an interrupt pending, then process it. */ + if (frv_interrupt_state.queue_index > 0) + handle_interrupt (current_cpu, pc); +} + +/* Find the next available ESR and return its index */ +static int +esr_for_data_access_exception ( + SIM_CPU *current_cpu, struct frv_interrupt_queue_element *item +) +{ + SIM_DESC sd = CPU_STATE (current_cpu); + if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550) + return 8; /* Use ESR8, EPCR8. */ + + if (item->slot == UNIT_I0) + return 8; /* Use ESR8, EPCR8, EAR8, EDR8. */ + + return 9; /* Use ESR9, EPCR9, EAR9. */ +} + +/* Set the next available EDR register with the data which was to be stored + and return the index of the register. */ +static int +set_edr_register ( + SIM_CPU *current_cpu, struct frv_interrupt_queue_element *item, int edr_index +) +{ + /* EDR0, EDR4 and EDR8 are available as blocks of 4. + SI data uses EDR3, EDR7 and EDR11 + DI data uses EDR2, EDR6 and EDR10 + XI data uses EDR0, EDR4 and EDR8. */ + int i; + edr_index += 4 - item->u.data_written.length; + for (i = 0; i < item->u.data_written.length; ++i) + SET_EDR (edr_index + i, item->u.data_written.words[i]); + + return edr_index; +}; + +/* Clear ESFR0, EPCRx, ESRx, EARx and EDRx. */ +static void +clear_exception_status_registers (SIM_CPU *current_cpu) +{ + int i; + /* It is only necessary to clear the flag bits indicating which registers + are valid. */ + SET_ESFR (0, 0); + SET_ESFR (1, 0); + + for (i = 0; i <= 2; ++i) + { + SI esr = GET_ESR (i); + CLEAR_ESR_VALID (esr); + SET_ESR (i, esr); + } + for (i = 8; i <= 15; ++i) + { + SI esr = GET_ESR (i); + CLEAR_ESR_VALID (esr); + SET_ESR (i, esr); + } +} + +/* Record state for media exception. */ +void +frv_set_mp_exception_registers ( + SIM_CPU *current_cpu, enum frv_msr_mtt mtt, int sie +) +{ + /* Record the interrupt factor in MSR0. */ + SI msr0 = GET_MSR (0); + if (GET_MSR_MTT (msr0) == MTT_NONE) + SET_MSR_MTT (msr0, mtt); + + /* Also set the OVF bit in the appropriate MSR as well as MSR0.AOVF. */ + if (mtt == MTT_OVERFLOW) + { + FRV_VLIW *vliw = CPU_VLIW (current_cpu); + int slot = vliw->next_slot - 1; + SIM_DESC sd = CPU_STATE (current_cpu); + + /* If this insn is in the M2 slot, then set MSR1.OVF and MSR1.SIE, + otherwise set MSR0.OVF and MSR0.SIE. */ + if (STATE_ARCHITECTURE (sd)->mach != bfd_mach_fr550 && (*vliw->current_vliw)[slot] == UNIT_FM1) + { + SI msr = GET_MSR (1); + OR_MSR_SIE (msr, sie); + SET_MSR_OVF (msr); + SET_MSR (1, msr); + } + else + { + OR_MSR_SIE (msr0, sie); + SET_MSR_OVF (msr0); + } + + /* Generate the interrupt now if MSR0.MPEM is set on fr550 */ + if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550 && GET_MSR_MPEM (msr0)) + frv_queue_program_interrupt (current_cpu, FRV_MP_EXCEPTION); + else + { + /* Regardless of the slot, set MSR0.AOVF. */ + SET_MSR_AOVF (msr0); + } + } + + SET_MSR (0, msr0); +} + +/* Determine the correct FQ register to use for the given exception. + Return -1 if a register is not available. */ +static int +fq_for_exception ( + SIM_CPU *current_cpu, struct frv_interrupt_queue_element *item +) +{ + SI fq; + struct frv_fp_exception_info *fp_info = & item->u.fp_info; + + /* For fp_exception overflow, underflow or inexact, use FQ0 or FQ1. */ + if (fp_info->ftt == FTT_IEEE_754_EXCEPTION + && (fp_info->fsr_mask & (FSR_OVERFLOW | FSR_UNDERFLOW | FSR_INEXACT))) + { + fq = GET_FQ (0); + if (! GET_FQ_VALID (fq)) + return 0; /* FQ0 is available. */ + fq = GET_FQ (1); + if (! GET_FQ_VALID (fq)) + return 1; /* FQ1 is available. */ + + /* No FQ register is available */ + { + SIM_DESC sd = CPU_STATE (current_cpu); + IADDR pc = CPU_PC_GET (current_cpu); + sim_engine_abort (sd, current_cpu, pc, "No FQ register available\n"); + } + return -1; + } + /* For other exceptions, use FQ2 if the insn was in slot F0/I0 and FQ3 + otherwise. */ + if (item->slot == UNIT_FM0 || item->slot == UNIT_I0) + return 2; + + return 3; +} + +/* Set FSR0, FQ0-FQ9, depending on the interrupt. */ +static void +set_fp_exception_registers ( + SIM_CPU *current_cpu, struct frv_interrupt_queue_element *item +) +{ + int fq_index; + SI fq; + SI insn; + SI fsr0; + IADDR pc; + struct frv_fp_exception_info *fp_info; + SIM_DESC sd = CPU_STATE (current_cpu); + + /* No FQ registers on fr550 */ + if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550) + { + /* Update the fsr. */ + fp_info = & item->u.fp_info; + fsr0 = GET_FSR (0); + SET_FSR_FTT (fsr0, fp_info->ftt); + SET_FSR (0, fsr0); + return; + } + + /* Select an FQ and update it with the exception information. */ + fq_index = fq_for_exception (current_cpu, item); + if (fq_index == -1) + return; + + fp_info = & item->u.fp_info; + fq = GET_FQ (fq_index); + SET_FQ_MIV (fq, MIV_FLOAT); + SET_FQ_SIE (fq, SIE_NIL); + SET_FQ_FTT (fq, fp_info->ftt); + SET_FQ_CEXC (fq, fp_info->fsr_mask); + SET_FQ_VALID (fq); + SET_FQ (fq_index, fq); + + /* Write the failing insn into FQx.OPC. */ + pc = item->vpc; + insn = GETMEMSI (current_cpu, pc, pc); + SET_FQ_OPC (fq_index, insn); + + /* Update the fsr. */ + fsr0 = GET_FSR (0); + SET_FSR_QNE (fsr0); /* FQ not empty */ + SET_FSR_FTT (fsr0, fp_info->ftt); + SET_FSR (0, fsr0); +} + +/* Record the state of a division exception in the ISR. */ +static void +set_isr_exception_fields ( + SIM_CPU *current_cpu, struct frv_interrupt_queue_element *item +) +{ + USI isr = GET_ISR (); + int dtt = GET_ISR_DTT (isr); + dtt |= item->u.dtt; + SET_ISR_DTT (isr, dtt); + SET_ISR (isr); +} + +/* Set ESFR0, EPCRx, ESRx, EARx and EDRx, according to the given program + interrupt. */ +static void +set_exception_status_registers ( + SIM_CPU *current_cpu, struct frv_interrupt_queue_element *item +) +{ + struct frv_interrupt *interrupt = & frv_interrupt_table[item->kind]; + int slot = (item->vpc - previous_vliw_pc) / 4; + int reg_index = -1; + int set_ear = 0; + int set_edr = 0; + int set_daec = 0; + int set_epcr = 0; + SI esr = 0; + SIM_DESC sd = CPU_STATE (current_cpu); + + /* If the interrupt is strict (precise) or the interrupt is on the insns + in the I0 pipe, then set the 0 registers. */ + if (interrupt->precise) + { + reg_index = 0; + if (interrupt->kind == FRV_REGISTER_EXCEPTION) + SET_ESR_REC (esr, item->u.rec); + else if (interrupt->kind == FRV_INSTRUCTION_ACCESS_EXCEPTION) + SET_ESR_IAEC (esr, item->u.iaec); + /* For fr550, don't set epcr for precise interrupts. */ + if (STATE_ARCHITECTURE (sd)->mach != bfd_mach_fr550) + set_epcr = 1; + } + else + { + switch (interrupt->kind) + { + case FRV_DIVISION_EXCEPTION: + set_isr_exception_fields (current_cpu, item); + /* fall thru to set reg_index. */ + case FRV_COMMIT_EXCEPTION: + /* For fr550, always use ESR0. */ + if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550) + reg_index = 0; + else if (item->slot == UNIT_I0) + reg_index = 0; + else if (item->slot == UNIT_I1) + reg_index = 1; + set_epcr = 1; + break; + case FRV_DATA_STORE_ERROR: + reg_index = 14; /* Use ESR14. */ + break; + case FRV_DATA_ACCESS_ERROR: + reg_index = 15; /* Use ESR15, EPCR15. */ + if (STATE_ARCHITECTURE (sd)->mach != bfd_mach_fr400) + set_ear = 1; + break; + case FRV_DATA_ACCESS_EXCEPTION: + set_daec = 1; + /* fall through */ + case FRV_DATA_ACCESS_MMU_MISS: + case FRV_MEM_ADDRESS_NOT_ALIGNED: + /* Get the appropriate ESR, EPCR, EAR and EDR. + EAR will be set. EDR will not be set if this is a store insn. */ + set_ear = 1; + /* For fr550, never use EDRx. */ + if (STATE_ARCHITECTURE (sd)->mach != bfd_mach_fr550) + if (item->u.data_written.length != 0) + set_edr = 1; + reg_index = esr_for_data_access_exception (current_cpu, item); + set_epcr = 1; + break; + case FRV_MP_EXCEPTION: + /* For fr550, use EPCR2 and ESR2. */ + if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550) + { + reg_index = 2; + set_epcr = 1; + } + break; /* MSR0-1, FQ0-9 are already set. */ + case FRV_FP_EXCEPTION: + set_fp_exception_registers (current_cpu, item); + /* For fr550, use EPCR2 and ESR2. */ + if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550) + { + reg_index = 2; + set_epcr = 1; + } + break; + default: + { + SIM_DESC sd = CPU_STATE (current_cpu); + IADDR pc = CPU_PC_GET (current_cpu); + sim_engine_abort (sd, current_cpu, pc, + "invalid non-strict program interrupt kind: %d\n", + interrupt->kind); + break; + } + } + } /* non-strict (imprecise) interrupt */ + + /* Now fill in the selected exception status registers. */ + if (reg_index != -1) + { + /* Now set the exception status registers. */ + SET_ESFR_FLAG (reg_index); + SET_ESR_EC (esr, interrupt->ec); + + if (set_epcr) + { + if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr400) + SET_EPCR (reg_index, previous_vliw_pc); + else + SET_EPCR (reg_index, item->vpc); + } + + if (set_ear) + { + SET_EAR (reg_index, item->eaddress); + SET_ESR_EAV (esr); + } + else + CLEAR_ESR_EAV (esr); + + if (set_edr) + { + int edn = set_edr_register (current_cpu, item, 0/* EDR0-3 */); + SET_ESR_EDN (esr, edn); + SET_ESR_EDV (esr); + } + else + CLEAR_ESR_EDV (esr); + + if (set_daec) + SET_ESR_DAEC (esr, item->u.daec); + + SET_ESR_VALID (esr); + SET_ESR (reg_index, esr); + } +} + +/* Check for compound interrupts. + Returns NULL if no interrupt is to be processed. */ +static struct frv_interrupt * +check_for_compound_interrupt ( + SIM_CPU *current_cpu, struct frv_interrupt_queue_element *item +) +{ + struct frv_interrupt *interrupt; + + /* Set the exception status registers for the original interrupt. */ + set_exception_status_registers (current_cpu, item); + interrupt = & frv_interrupt_table[item->kind]; + + if (! interrupt->precise) + { + IADDR vpc = 0; + int mask = 0; + + vpc = item->vpc; + mask = (1 << item->kind); + + /* Look for more queued program interrupts which are non-deferred + (pending inhibit), imprecise (non-strict) different than an interrupt + already found and caused by a different insn. A bit mask is used + to keep track of interrupts which have already been detected. */ + while (item != frv_interrupt_state.queue) + { + enum frv_interrupt_kind kind; + struct frv_interrupt *next_interrupt; + --item; + kind = item->kind; + next_interrupt = & frv_interrupt_table[kind]; + + if (next_interrupt->iclass != FRV_PROGRAM_INTERRUPT) + break; /* no program interrupts left. */ + + if (item->vpc == vpc) + continue; /* caused by the same insn. */ + + vpc = item->vpc; + if (! next_interrupt->precise && ! next_interrupt->deferred) + { + if (! (mask & (1 << kind))) + { + /* Set the exception status registers for the additional + interrupt. */ + set_exception_status_registers (current_cpu, item); + mask |= (1 << kind); + interrupt = & frv_interrupt_table[FRV_COMPOUND_EXCEPTION]; + } + } + } + } + + /* Return with either the original interrupt, a compound_exception, + or no exception. */ + return interrupt; +} + +/* Handle a program interrupt. */ +void +frv_program_interrupt ( + SIM_CPU *current_cpu, struct frv_interrupt_queue_element *item, IADDR pc +) +{ + struct frv_interrupt *interrupt; + + clear_exception_status_registers (current_cpu); + /* If two or more non-deferred imprecise (non-strict) interrupts occur + on two or more insns, then generate a compound_exception. */ + interrupt = check_for_compound_interrupt (current_cpu, item); + if (interrupt != NULL) + { + frv_program_or_software_interrupt (current_cpu, interrupt, pc); + frv_clear_interrupt_classes (FRV_SOFTWARE_INTERRUPT, + FRV_PROGRAM_INTERRUPT); + } +} + +/* Handle a software interrupt. */ +void +frv_software_interrupt ( + SIM_CPU *current_cpu, struct frv_interrupt_queue_element *item, IADDR pc +) +{ + struct frv_interrupt *interrupt = & frv_interrupt_table[item->kind]; + frv_program_or_software_interrupt (current_cpu, interrupt, pc); +} + +/* Handle a program interrupt or a software interrupt in non-operating mode. */ +void +frv_non_operating_interrupt ( + SIM_CPU *current_cpu, enum frv_interrupt_kind kind, IADDR pc +) +{ + SIM_DESC sd = CPU_STATE (current_cpu); + switch (kind) + { + case FRV_INTERRUPT_LEVEL_1: + case FRV_INTERRUPT_LEVEL_2: + case FRV_INTERRUPT_LEVEL_3: + case FRV_INTERRUPT_LEVEL_4: + case FRV_INTERRUPT_LEVEL_5: + case FRV_INTERRUPT_LEVEL_6: + case FRV_INTERRUPT_LEVEL_7: + case FRV_INTERRUPT_LEVEL_8: + case FRV_INTERRUPT_LEVEL_9: + case FRV_INTERRUPT_LEVEL_10: + case FRV_INTERRUPT_LEVEL_11: + case FRV_INTERRUPT_LEVEL_12: + case FRV_INTERRUPT_LEVEL_13: + case FRV_INTERRUPT_LEVEL_14: + case FRV_INTERRUPT_LEVEL_15: + sim_engine_abort (sd, current_cpu, pc, + "interrupt: external %d\n", kind + 1); + break; + case FRV_TRAP_INSTRUCTION: + break; /* handle as in operating mode. */ + case FRV_COMMIT_EXCEPTION: + sim_engine_abort (sd, current_cpu, pc, + "interrupt: commit_exception\n"); + break; + case FRV_DIVISION_EXCEPTION: + sim_engine_abort (sd, current_cpu, pc, + "interrupt: division_exception\n"); + break; + case FRV_DATA_STORE_ERROR: + sim_engine_abort (sd, current_cpu, pc, + "interrupt: data_store_error\n"); + break; + case FRV_DATA_ACCESS_EXCEPTION: + sim_engine_abort (sd, current_cpu, pc, + "interrupt: data_access_exception\n"); + break; + case FRV_DATA_ACCESS_MMU_MISS: + sim_engine_abort (sd, current_cpu, pc, + "interrupt: data_access_mmu_miss\n"); + break; + case FRV_DATA_ACCESS_ERROR: + sim_engine_abort (sd, current_cpu, pc, + "interrupt: data_access_error\n"); + break; + case FRV_MP_EXCEPTION: + sim_engine_abort (sd, current_cpu, pc, + "interrupt: mp_exception\n"); + break; + case FRV_FP_EXCEPTION: + sim_engine_abort (sd, current_cpu, pc, + "interrupt: fp_exception\n"); + break; + case FRV_MEM_ADDRESS_NOT_ALIGNED: + sim_engine_abort (sd, current_cpu, pc, + "interrupt: mem_address_not_aligned\n"); + break; + case FRV_REGISTER_EXCEPTION: + sim_engine_abort (sd, current_cpu, pc, + "interrupt: register_exception\n"); + break; + case FRV_MP_DISABLED: + sim_engine_abort (sd, current_cpu, pc, + "interrupt: mp_disabled\n"); + break; + case FRV_FP_DISABLED: + sim_engine_abort (sd, current_cpu, pc, + "interrupt: fp_disabled\n"); + break; + case FRV_PRIVILEGED_INSTRUCTION: + sim_engine_abort (sd, current_cpu, pc, + "interrupt: privileged_instruction\n"); + break; + case FRV_ILLEGAL_INSTRUCTION: + sim_engine_abort (sd, current_cpu, pc, + "interrupt: illegal_instruction\n"); + break; + case FRV_INSTRUCTION_ACCESS_EXCEPTION: + sim_engine_abort (sd, current_cpu, pc, + "interrupt: instruction_access_exception\n"); + break; + case FRV_INSTRUCTION_ACCESS_MMU_MISS: + sim_engine_abort (sd, current_cpu, pc, + "interrupt: instruction_access_mmu_miss\n"); + break; + case FRV_INSTRUCTION_ACCESS_ERROR: + sim_engine_abort (sd, current_cpu, pc, + "interrupt: insn_access_error\n"); + break; + case FRV_COMPOUND_EXCEPTION: + sim_engine_abort (sd, current_cpu, pc, + "interrupt: compound_exception\n"); + break; + case FRV_BREAK_EXCEPTION: + sim_engine_abort (sd, current_cpu, pc, + "interrupt: break_exception\n"); + break; + case FRV_RESET: + sim_engine_abort (sd, current_cpu, pc, + "interrupt: reset\n"); + break; + default: + sim_engine_abort (sd, current_cpu, pc, + "unhandled interrupt kind: %d\n", kind); + break; + } +} + +/* Handle a break interrupt. */ +void +frv_break_interrupt ( + SIM_CPU *current_cpu, struct frv_interrupt *interrupt, IADDR current_pc +) +{ + IADDR new_pc; + + /* BPCSR=PC + BPSR.BS=PSR.S + BPSR.BET=PSR.ET + PSR.S=1 + PSR.ET=0 + TBR.TT=0xff + PC=TBR + */ + /* Must set PSR.S first to allow access to supervisor-only spr registers. */ + SET_H_BPSR_BS (GET_H_PSR_S ()); + SET_H_BPSR_BET (GET_H_PSR_ET ()); + SET_H_PSR_S (1); + SET_H_PSR_ET (0); + /* Must set PSR.S first to allow access to supervisor-only spr registers. */ + SET_H_SPR (H_SPR_BPCSR, current_pc); + + /* Set the new PC in the TBR. */ + SET_H_TBR_TT (interrupt->handler_offset); + new_pc = GET_H_SPR (H_SPR_TBR); + SET_H_PC (new_pc); + + CPU_DEBUG_STATE (current_cpu) = 1; +} + +/* Handle a program interrupt or a software interrupt. */ +void +frv_program_or_software_interrupt ( + SIM_CPU *current_cpu, struct frv_interrupt *interrupt, IADDR current_pc +) +{ + USI new_pc; + int original_psr_et; + + /* PCSR=PC + PSR.PS=PSR.S + PSR.ET=0 + PSR.S=1 + if PSR.ESR==1 + SR0 through SR3=GR4 through GR7 + TBR.TT=interrupt handler offset + PC=TBR + */ + original_psr_et = GET_H_PSR_ET (); + + SET_H_PSR_PS (GET_H_PSR_S ()); + SET_H_PSR_ET (0); + SET_H_PSR_S (1); + + /* Must set PSR.S first to allow access to supervisor-only spr registers. */ + /* The PCSR depends on the precision of the interrupt. */ + if (interrupt->precise) + SET_H_SPR (H_SPR_PCSR, previous_vliw_pc); + else + SET_H_SPR (H_SPR_PCSR, current_pc); + + /* Set the new PC in the TBR. */ + SET_H_TBR_TT (interrupt->handler_offset); + new_pc = GET_H_SPR (H_SPR_TBR); + SET_H_PC (new_pc); + + /* If PSR.ET was not originally set, then enter the stopped state. */ + if (! original_psr_et) + { + SIM_DESC sd = CPU_STATE (current_cpu); + frv_non_operating_interrupt (current_cpu, interrupt->kind, current_pc); + sim_engine_halt (sd, current_cpu, NULL, new_pc, sim_stopped, SIM_SIGINT); + } +} + +/* Handle a program interrupt or a software interrupt. */ +void +frv_external_interrupt ( + SIM_CPU *current_cpu, struct frv_interrupt_queue_element *item, IADDR pc +) +{ + USI new_pc; + struct frv_interrupt *interrupt = & frv_interrupt_table[item->kind]; + + /* Don't process the interrupt if PSR.ET is not set or if it is masked. + Interrupt 15 is processed even if it appears to be masked. */ + if (! GET_H_PSR_ET () + || (interrupt->kind != FRV_INTERRUPT_LEVEL_15 + && interrupt->kind < GET_H_PSR_PIL ())) + return; /* Leave it for later. */ + + /* Remove the interrupt from the queue. */ + --frv_interrupt_state.queue_index; + + /* PCSR=PC + PSR.PS=PSR.S + PSR.ET=0 + PSR.S=1 + if PSR.ESR==1 + SR0 through SR3=GR4 through GR7 + TBR.TT=interrupt handler offset + PC=TBR + */ + SET_H_PSR_PS (GET_H_PSR_S ()); + SET_H_PSR_ET (0); + SET_H_PSR_S (1); + /* Must set PSR.S first to allow access to supervisor-only spr registers. */ + SET_H_SPR (H_SPR_PCSR, GET_H_PC ()); + + /* Set the new PC in the TBR. */ + SET_H_TBR_TT (interrupt->handler_offset); + new_pc = GET_H_SPR (H_SPR_TBR); + SET_H_PC (new_pc); +} + +/* Clear interrupts which fall within the range of classes given. */ +void +frv_clear_interrupt_classes ( + enum frv_interrupt_class low_class, enum frv_interrupt_class high_class +) +{ + int i; + int j; + int limit = frv_interrupt_state.queue_index; + + /* Find the lowest priority interrupt to be removed. */ + for (i = 0; i < limit; ++i) + { + enum frv_interrupt_kind kind = frv_interrupt_state.queue[i].kind; + struct frv_interrupt* interrupt = & frv_interrupt_table[kind]; + if (interrupt->iclass >= low_class) + break; + } + + /* Find the highest priority interrupt to be removed. */ + for (j = limit - 1; j >= i; --j) + { + enum frv_interrupt_kind kind = frv_interrupt_state.queue[j].kind; + struct frv_interrupt* interrupt = & frv_interrupt_table[kind]; + if (interrupt->iclass <= high_class) + break; + } + + /* Shuffle the remaining high priority interrupts down into the empty space + left by the deleted interrupts. */ + if (j >= i) + { + for (++j; j < limit; ++j) + frv_interrupt_state.queue[i++] = frv_interrupt_state.queue[j]; + frv_interrupt_state.queue_index -= (j - i); + } +} + +/* Save data written to memory into the interrupt state so that it can be + copied to the appropriate EDR register, if necessary, in the event of an + interrupt. */ +void +frv_save_data_written_for_interrupts ( + SIM_CPU *current_cpu, CGEN_WRITE_QUEUE_ELEMENT *item +) +{ + /* Record the slot containing the insn doing the write in the + interrupt state. */ + frv_interrupt_state.slot = CGEN_WRITE_QUEUE_ELEMENT_PIPE (item); + + /* Now record any data written to memory in the interrupt state. */ + switch (CGEN_WRITE_QUEUE_ELEMENT_KIND (item)) + { + case CGEN_BI_WRITE: + case CGEN_QI_WRITE: + case CGEN_SI_WRITE: + case CGEN_SF_WRITE: + case CGEN_PC_WRITE: + case CGEN_FN_HI_WRITE: + case CGEN_FN_SI_WRITE: + case CGEN_FN_SF_WRITE: + case CGEN_FN_DI_WRITE: + case CGEN_FN_DF_WRITE: + case CGEN_FN_XI_WRITE: + case CGEN_FN_PC_WRITE: + break; /* Ignore writes to registers. */ + case CGEN_MEM_QI_WRITE: + frv_interrupt_state.data_written.length = 1; + frv_interrupt_state.data_written.words[0] + = item->kinds.mem_qi_write.value; + break; + case CGEN_MEM_HI_WRITE: + frv_interrupt_state.data_written.length = 1; + frv_interrupt_state.data_written.words[0] + = item->kinds.mem_hi_write.value; + break; + case CGEN_MEM_SI_WRITE: + frv_interrupt_state.data_written.length = 1; + frv_interrupt_state.data_written.words[0] + = item->kinds.mem_si_write.value; + break; + case CGEN_MEM_DI_WRITE: + frv_interrupt_state.data_written.length = 2; + frv_interrupt_state.data_written.words[0] + = item->kinds.mem_di_write.value >> 32; + frv_interrupt_state.data_written.words[1] + = item->kinds.mem_di_write.value; + break; + case CGEN_MEM_DF_WRITE: + frv_interrupt_state.data_written.length = 2; + frv_interrupt_state.data_written.words[0] + = item->kinds.mem_df_write.value >> 32; + frv_interrupt_state.data_written.words[1] + = item->kinds.mem_df_write.value; + break; + case CGEN_MEM_XI_WRITE: + frv_interrupt_state.data_written.length = 4; + frv_interrupt_state.data_written.words[0] + = item->kinds.mem_xi_write.value[0]; + frv_interrupt_state.data_written.words[1] + = item->kinds.mem_xi_write.value[1]; + frv_interrupt_state.data_written.words[2] + = item->kinds.mem_xi_write.value[2]; + frv_interrupt_state.data_written.words[3] + = item->kinds.mem_xi_write.value[3]; + break; + case CGEN_FN_MEM_QI_WRITE: + frv_interrupt_state.data_written.length = 1; + frv_interrupt_state.data_written.words[0] + = item->kinds.fn_mem_qi_write.value; + break; + case CGEN_FN_MEM_HI_WRITE: + frv_interrupt_state.data_written.length = 1; + frv_interrupt_state.data_written.words[0] + = item->kinds.fn_mem_hi_write.value; + break; + case CGEN_FN_MEM_SI_WRITE: + frv_interrupt_state.data_written.length = 1; + frv_interrupt_state.data_written.words[0] + = item->kinds.fn_mem_si_write.value; + break; + case CGEN_FN_MEM_DI_WRITE: + frv_interrupt_state.data_written.length = 2; + frv_interrupt_state.data_written.words[0] + = item->kinds.fn_mem_di_write.value >> 32; + frv_interrupt_state.data_written.words[1] + = item->kinds.fn_mem_di_write.value; + break; + case CGEN_FN_MEM_DF_WRITE: + frv_interrupt_state.data_written.length = 2; + frv_interrupt_state.data_written.words[0] + = item->kinds.fn_mem_df_write.value >> 32; + frv_interrupt_state.data_written.words[1] + = item->kinds.fn_mem_df_write.value; + break; + case CGEN_FN_MEM_XI_WRITE: + frv_interrupt_state.data_written.length = 4; + frv_interrupt_state.data_written.words[0] + = item->kinds.fn_mem_xi_write.value[0]; + frv_interrupt_state.data_written.words[1] + = item->kinds.fn_mem_xi_write.value[1]; + frv_interrupt_state.data_written.words[2] + = item->kinds.fn_mem_xi_write.value[2]; + frv_interrupt_state.data_written.words[3] + = item->kinds.fn_mem_xi_write.value[3]; + break; + default: + { + SIM_DESC sd = CPU_STATE (current_cpu); + IADDR pc = CPU_PC_GET (current_cpu); + sim_engine_abort (sd, current_cpu, pc, + "unknown write kind during save for interrupt\n"); + } + break; + } +} diff --git a/sim/frv/memory.c b/sim/frv/memory.c new file mode 100644 index 0000000..4dbc652 --- /dev/null +++ b/sim/frv/memory.c @@ -0,0 +1,1063 @@ +/* frv memory model. + Copyright (C) 1999, 2000, 2001, 2003 Free Software Foundation, Inc. + Contributed by Red Hat + +This file is part of the GNU simulators. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#define WANT_CPU frvbf +#define WANT_CPU_FRVBF + +#include "sim-main.h" +#include "cgen-mem.h" +#include "bfd.h" + +/* Check for alignment and access restrictions. Return the corrected address. + */ +static SI +fr400_check_data_read_address (SIM_CPU *current_cpu, SI address, int align_mask) +{ + /* Check access restrictions for double word loads only. */ + if (align_mask == 7) + { + if ((USI)address >= 0xfe800000 && (USI)address <= 0xfeffffff) + frv_queue_data_access_error_interrupt (current_cpu, address); + } + return address; +} + +static SI +fr500_check_data_read_address (SIM_CPU *current_cpu, SI address, int align_mask) +{ + if (address & align_mask) + { + frv_queue_mem_address_not_aligned_interrupt (current_cpu, address); + address &= ~align_mask; + } + + if ((USI)address >= 0xfeff0600 && (USI)address <= 0xfeff7fff + || (USI)address >= 0xfe800000 && (USI)address <= 0xfefeffff) + frv_queue_data_access_error_interrupt (current_cpu, address); + + return address; +} + +static SI +fr550_check_data_read_address (SIM_CPU *current_cpu, SI address, int align_mask) +{ + if ((USI)address >= 0xfe800000 && (USI)address <= 0xfefeffff + || (align_mask > 0x3 + && ((USI)address >= 0xfeff0000 && (USI)address <= 0xfeffffff))) + frv_queue_data_access_error_interrupt (current_cpu, address); + + return address; +} + +static SI +check_data_read_address (SIM_CPU *current_cpu, SI address, int align_mask) +{ + SIM_DESC sd = CPU_STATE (current_cpu); + switch (STATE_ARCHITECTURE (sd)->mach) + { + case bfd_mach_fr400: + address = fr400_check_data_read_address (current_cpu, address, + align_mask); + break; + case bfd_mach_frvtomcat: + case bfd_mach_fr500: + case bfd_mach_frv: + address = fr500_check_data_read_address (current_cpu, address, + align_mask); + break; + case bfd_mach_fr550: + address = fr550_check_data_read_address (current_cpu, address, + align_mask); + break; + default: + break; + } + + return address; +} + +static SI +fr400_check_readwrite_address (SIM_CPU *current_cpu, SI address, int align_mask) +{ + if (address & align_mask) + { + /* Make sure that this exception is not masked. */ + USI isr = GET_ISR (); + if (! GET_ISR_EMAM (isr)) + { + /* Bad alignment causes a data_access_error on fr400. */ + frv_queue_data_access_error_interrupt (current_cpu, address); + } + address &= ~align_mask; + } + /* Nothing to check. */ + return address; +} + +static SI +fr500_check_readwrite_address (SIM_CPU *current_cpu, SI address, int align_mask) +{ + if ((USI)address >= 0xfe000000 && (USI)address <= 0xfe003fff + || (USI)address >= 0xfe004000 && (USI)address <= 0xfe3fffff + || (USI)address >= 0xfe400000 && (USI)address <= 0xfe403fff + || (USI)address >= 0xfe404000 && (USI)address <= 0xfe7fffff) + frv_queue_data_access_exception_interrupt (current_cpu); + + return address; +} + +static SI +fr550_check_readwrite_address (SIM_CPU *current_cpu, SI address, int align_mask) +{ + /* No alignment restrictions on fr550 */ + + if ((USI)address >= 0xfe000000 && (USI)address <= 0xfe3fffff + || (USI)address >= 0xfe408000 && (USI)address <= 0xfe7fffff) + frv_queue_data_access_exception_interrupt (current_cpu); + else + { + USI hsr0 = GET_HSR0 (); + if (! GET_HSR0_RME (hsr0) + && (USI)address >= 0xfe400000 && (USI)address <= 0xfe407fff) + frv_queue_data_access_exception_interrupt (current_cpu); + } + + return address; +} + +static SI +check_readwrite_address (SIM_CPU *current_cpu, SI address, int align_mask) +{ + SIM_DESC sd = CPU_STATE (current_cpu); + switch (STATE_ARCHITECTURE (sd)->mach) + { + case bfd_mach_fr400: + address = fr400_check_readwrite_address (current_cpu, address, + align_mask); + break; + case bfd_mach_frvtomcat: + case bfd_mach_fr500: + case bfd_mach_frv: + address = fr500_check_readwrite_address (current_cpu, address, + align_mask); + break; + case bfd_mach_fr550: + address = fr550_check_readwrite_address (current_cpu, address, + align_mask); + break; + default: + break; + } + + return address; +} + +static PCADDR +fr400_check_insn_read_address (SIM_CPU *current_cpu, PCADDR address, + int align_mask) +{ + if (address & align_mask) + { + frv_queue_instruction_access_error_interrupt (current_cpu); + address &= ~align_mask; + } + else if ((USI)address >= 0xfe800000 && (USI)address <= 0xfeffffff) + frv_queue_instruction_access_error_interrupt (current_cpu); + + return address; +} + +static PCADDR +fr500_check_insn_read_address (SIM_CPU *current_cpu, PCADDR address, + int align_mask) +{ + if (address & align_mask) + { + frv_queue_mem_address_not_aligned_interrupt (current_cpu, address); + address &= ~align_mask; + } + + if ((USI)address >= 0xfeff0600 && (USI)address <= 0xfeff7fff + || (USI)address >= 0xfe800000 && (USI)address <= 0xfefeffff) + frv_queue_instruction_access_error_interrupt (current_cpu); + else if ((USI)address >= 0xfe004000 && (USI)address <= 0xfe3fffff + || (USI)address >= 0xfe400000 && (USI)address <= 0xfe403fff + || (USI)address >= 0xfe404000 && (USI)address <= 0xfe7fffff) + frv_queue_instruction_access_exception_interrupt (current_cpu); + else + { + USI hsr0 = GET_HSR0 (); + if (! GET_HSR0_RME (hsr0) + && (USI)address >= 0xfe000000 && (USI)address <= 0xfe003fff) + frv_queue_instruction_access_exception_interrupt (current_cpu); + } + + return address; +} + +static PCADDR +fr550_check_insn_read_address (SIM_CPU *current_cpu, PCADDR address, + int align_mask) +{ + address &= ~align_mask; + + if ((USI)address >= 0xfe800000 && (USI)address <= 0xfeffffff) + frv_queue_instruction_access_error_interrupt (current_cpu); + else if ((USI)address >= 0xfe008000 && (USI)address <= 0xfe7fffff) + frv_queue_instruction_access_exception_interrupt (current_cpu); + else + { + USI hsr0 = GET_HSR0 (); + if (! GET_HSR0_RME (hsr0) + && (USI)address >= 0xfe000000 && (USI)address <= 0xfe007fff) + frv_queue_instruction_access_exception_interrupt (current_cpu); + } + + return address; +} + +static PCADDR +check_insn_read_address (SIM_CPU *current_cpu, PCADDR address, int align_mask) +{ + SIM_DESC sd = CPU_STATE (current_cpu); + switch (STATE_ARCHITECTURE (sd)->mach) + { + case bfd_mach_fr400: + address = fr400_check_insn_read_address (current_cpu, address, + align_mask); + break; + case bfd_mach_frvtomcat: + case bfd_mach_fr500: + case bfd_mach_frv: + address = fr500_check_insn_read_address (current_cpu, address, + align_mask); + break; + case bfd_mach_fr550: + address = fr550_check_insn_read_address (current_cpu, address, + align_mask); + break; + default: + break; + } + + return address; +} + +/* Memory reads. */ +QI +frvbf_read_mem_QI (SIM_CPU *current_cpu, IADDR pc, SI address) +{ + USI hsr0 = GET_HSR0 (); + FRV_CACHE *cache = CPU_DATA_CACHE (current_cpu); + + /* Check for access exceptions. */ + address = check_data_read_address (current_cpu, address, 0); + address = check_readwrite_address (current_cpu, address, 0); + + /* If we need to count cycles, then the cache operation will be + initiated from the model profiling functions. + See frvbf_model_.... */ + if (model_insn) + { + CPU_LOAD_ADDRESS (current_cpu) = address; + CPU_LOAD_LENGTH (current_cpu) = 1; + CPU_LOAD_SIGNED (current_cpu) = 1; + return 0xb7; /* any random value */ + } + + if (GET_HSR0_DCE (hsr0)) + { + int cycles; + cycles = frv_cache_read (cache, 0, address); + if (cycles != 0) + return CACHE_RETURN_DATA (cache, 0, address, QI, 1); + } + + return GETMEMQI (current_cpu, pc, address); +} + +UQI +frvbf_read_mem_UQI (SIM_CPU *current_cpu, IADDR pc, SI address) +{ + USI hsr0 = GET_HSR0 (); + FRV_CACHE *cache = CPU_DATA_CACHE (current_cpu); + + /* Check for access exceptions. */ + address = check_data_read_address (current_cpu, address, 0); + address = check_readwrite_address (current_cpu, address, 0); + + /* If we need to count cycles, then the cache operation will be + initiated from the model profiling functions. + See frvbf_model_.... */ + if (model_insn) + { + CPU_LOAD_ADDRESS (current_cpu) = address; + CPU_LOAD_LENGTH (current_cpu) = 1; + CPU_LOAD_SIGNED (current_cpu) = 0; + return 0xb7; /* any random value */ + } + + if (GET_HSR0_DCE (hsr0)) + { + int cycles; + cycles = frv_cache_read (cache, 0, address); + if (cycles != 0) + return CACHE_RETURN_DATA (cache, 0, address, UQI, 1); + } + + return GETMEMUQI (current_cpu, pc, address); +} + +/* Read a HI which spans two cache lines */ +static HI +read_mem_unaligned_HI (SIM_CPU *current_cpu, IADDR pc, SI address) +{ + HI value = frvbf_read_mem_QI (current_cpu, pc, address); + value <<= 8; + value |= frvbf_read_mem_UQI (current_cpu, pc, address + 1); + return T2H_2 (value); +} + +HI +frvbf_read_mem_HI (SIM_CPU *current_cpu, IADDR pc, SI address) +{ + USI hsr0; + FRV_CACHE *cache; + + /* Check for access exceptions. */ + address = check_data_read_address (current_cpu, address, 1); + address = check_readwrite_address (current_cpu, address, 1); + + /* If we need to count cycles, then the cache operation will be + initiated from the model profiling functions. + See frvbf_model_.... */ + hsr0 = GET_HSR0 (); + cache = CPU_DATA_CACHE (current_cpu); + if (model_insn) + { + CPU_LOAD_ADDRESS (current_cpu) = address; + CPU_LOAD_LENGTH (current_cpu) = 2; + CPU_LOAD_SIGNED (current_cpu) = 1; + return 0xb711; /* any random value */ + } + + if (GET_HSR0_DCE (hsr0)) + { + int cycles; + /* Handle access which crosses cache line boundary */ + SIM_DESC sd = CPU_STATE (current_cpu); + if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550) + { + if (DATA_CROSSES_CACHE_LINE (cache, address, 2)) + return read_mem_unaligned_HI (current_cpu, pc, address); + } + cycles = frv_cache_read (cache, 0, address); + if (cycles != 0) + return CACHE_RETURN_DATA (cache, 0, address, HI, 2); + } + + return GETMEMHI (current_cpu, pc, address); +} + +UHI +frvbf_read_mem_UHI (SIM_CPU *current_cpu, IADDR pc, SI address) +{ + USI hsr0; + FRV_CACHE *cache; + + /* Check for access exceptions. */ + address = check_data_read_address (current_cpu, address, 1); + address = check_readwrite_address (current_cpu, address, 1); + + /* If we need to count cycles, then the cache operation will be + initiated from the model profiling functions. + See frvbf_model_.... */ + hsr0 = GET_HSR0 (); + cache = CPU_DATA_CACHE (current_cpu); + if (model_insn) + { + CPU_LOAD_ADDRESS (current_cpu) = address; + CPU_LOAD_LENGTH (current_cpu) = 2; + CPU_LOAD_SIGNED (current_cpu) = 0; + return 0xb711; /* any random value */ + } + + if (GET_HSR0_DCE (hsr0)) + { + int cycles; + /* Handle access which crosses cache line boundary */ + SIM_DESC sd = CPU_STATE (current_cpu); + if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550) + { + if (DATA_CROSSES_CACHE_LINE (cache, address, 2)) + return read_mem_unaligned_HI (current_cpu, pc, address); + } + cycles = frv_cache_read (cache, 0, address); + if (cycles != 0) + return CACHE_RETURN_DATA (cache, 0, address, UHI, 2); + } + + return GETMEMUHI (current_cpu, pc, address); +} + +/* Read a SI which spans two cache lines */ +static SI +read_mem_unaligned_SI (SIM_CPU *current_cpu, IADDR pc, SI address) +{ + FRV_CACHE *cache = CPU_DATA_CACHE (current_cpu); + unsigned hi_len = cache->line_size - (address & (cache->line_size - 1)); + char valarray[4]; + SI SIvalue; + HI HIvalue; + + switch (hi_len) + { + case 1: + valarray[0] = frvbf_read_mem_QI (current_cpu, pc, address); + SIvalue = frvbf_read_mem_SI (current_cpu, pc, address + 1); + SIvalue = H2T_4 (SIvalue); + memcpy (valarray + 1, (char*)&SIvalue, 3); + break; + case 2: + HIvalue = frvbf_read_mem_HI (current_cpu, pc, address); + HIvalue = H2T_2 (HIvalue); + memcpy (valarray, (char*)&HIvalue, 2); + HIvalue = frvbf_read_mem_HI (current_cpu, pc, address + 2); + HIvalue = H2T_2 (HIvalue); + memcpy (valarray + 2, (char*)&HIvalue, 2); + break; + case 3: + SIvalue = frvbf_read_mem_SI (current_cpu, pc, address - 1); + SIvalue = H2T_4 (SIvalue); + memcpy (valarray, (char*)&SIvalue, 3); + valarray[3] = frvbf_read_mem_QI (current_cpu, pc, address + 3); + break; + default: + abort (); /* can't happen */ + } + return T2H_4 (*(SI*)valarray); +} + +SI +frvbf_read_mem_SI (SIM_CPU *current_cpu, IADDR pc, SI address) +{ + FRV_CACHE *cache; + USI hsr0; + + /* Check for access exceptions. */ + address = check_data_read_address (current_cpu, address, 3); + address = check_readwrite_address (current_cpu, address, 3); + + hsr0 = GET_HSR0 (); + cache = CPU_DATA_CACHE (current_cpu); + /* If we need to count cycles, then the cache operation will be + initiated from the model profiling functions. + See frvbf_model_.... */ + if (model_insn) + { + CPU_LOAD_ADDRESS (current_cpu) = address; + CPU_LOAD_LENGTH (current_cpu) = 4; + return 0x37111319; /* any random value */ + } + + if (GET_HSR0_DCE (hsr0)) + { + int cycles; + /* Handle access which crosses cache line boundary */ + SIM_DESC sd = CPU_STATE (current_cpu); + if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550) + { + if (DATA_CROSSES_CACHE_LINE (cache, address, 4)) + return read_mem_unaligned_SI (current_cpu, pc, address); + } + cycles = frv_cache_read (cache, 0, address); + if (cycles != 0) + return CACHE_RETURN_DATA (cache, 0, address, SI, 4); + } + + return GETMEMSI (current_cpu, pc, address); +} + +SI +frvbf_read_mem_WI (SIM_CPU *current_cpu, IADDR pc, SI address) +{ + return frvbf_read_mem_SI (current_cpu, pc, address); +} + +/* Read a SI which spans two cache lines */ +static DI +read_mem_unaligned_DI (SIM_CPU *current_cpu, IADDR pc, SI address) +{ + FRV_CACHE *cache = CPU_DATA_CACHE (current_cpu); + unsigned hi_len = cache->line_size - (address & (cache->line_size - 1)); + DI value, value1; + + switch (hi_len) + { + case 1: + value = frvbf_read_mem_QI (current_cpu, pc, address); + value <<= 56; + value1 = frvbf_read_mem_DI (current_cpu, pc, address + 1); + value1 = H2T_8 (value1); + value |= value1 & ((DI)0x00ffffff << 32); + value |= value1 & 0xffffffffu; + break; + case 2: + value = frvbf_read_mem_HI (current_cpu, pc, address); + value = H2T_2 (value); + value <<= 48; + value1 = frvbf_read_mem_DI (current_cpu, pc, address + 2); + value1 = H2T_8 (value1); + value |= value1 & ((DI)0x0000ffff << 32); + value |= value1 & 0xffffffffu; + break; + case 3: + value = frvbf_read_mem_SI (current_cpu, pc, address - 1); + value = H2T_4 (value); + value <<= 40; + value1 = frvbf_read_mem_DI (current_cpu, pc, address + 3); + value1 = H2T_8 (value1); + value |= value1 & ((DI)0x000000ff << 32); + value |= value1 & 0xffffffffu; + break; + case 4: + value = frvbf_read_mem_SI (current_cpu, pc, address); + value = H2T_4 (value); + value <<= 32; + value1 = frvbf_read_mem_SI (current_cpu, pc, address + 4); + value1 = H2T_4 (value1); + value |= value1 & 0xffffffffu; + break; + case 5: + value = frvbf_read_mem_DI (current_cpu, pc, address - 3); + value = H2T_8 (value); + value <<= 24; + value1 = frvbf_read_mem_SI (current_cpu, pc, address + 5); + value1 = H2T_4 (value1); + value |= value1 & 0x00ffffff; + break; + case 6: + value = frvbf_read_mem_DI (current_cpu, pc, address - 2); + value = H2T_8 (value); + value <<= 16; + value1 = frvbf_read_mem_HI (current_cpu, pc, address + 6); + value1 = H2T_2 (value1); + value |= value1 & 0x0000ffff; + break; + case 7: + value = frvbf_read_mem_DI (current_cpu, pc, address - 1); + value = H2T_8 (value); + value <<= 8; + value1 = frvbf_read_mem_QI (current_cpu, pc, address + 7); + value |= value1 & 0x000000ff; + break; + default: + abort (); /* can't happen */ + } + return T2H_8 (value); +} + +DI +frvbf_read_mem_DI (SIM_CPU *current_cpu, IADDR pc, SI address) +{ + USI hsr0; + FRV_CACHE *cache; + + /* Check for access exceptions. */ + address = check_data_read_address (current_cpu, address, 7); + address = check_readwrite_address (current_cpu, address, 7); + + /* If we need to count cycles, then the cache operation will be + initiated from the model profiling functions. + See frvbf_model_.... */ + hsr0 = GET_HSR0 (); + cache = CPU_DATA_CACHE (current_cpu); + if (model_insn) + { + CPU_LOAD_ADDRESS (current_cpu) = address; + CPU_LOAD_LENGTH (current_cpu) = 8; + return 0x37111319; /* any random value */ + } + + if (GET_HSR0_DCE (hsr0)) + { + int cycles; + /* Handle access which crosses cache line boundary */ + SIM_DESC sd = CPU_STATE (current_cpu); + if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550) + { + if (DATA_CROSSES_CACHE_LINE (cache, address, 8)) + return read_mem_unaligned_DI (current_cpu, pc, address); + } + cycles = frv_cache_read (cache, 0, address); + if (cycles != 0) + return CACHE_RETURN_DATA (cache, 0, address, DI, 8); + } + + return GETMEMDI (current_cpu, pc, address); +} + +DF +frvbf_read_mem_DF (SIM_CPU *current_cpu, IADDR pc, SI address) +{ + USI hsr0; + FRV_CACHE *cache; + + /* Check for access exceptions. */ + address = check_data_read_address (current_cpu, address, 7); + address = check_readwrite_address (current_cpu, address, 7); + + /* If we need to count cycles, then the cache operation will be + initiated from the model profiling functions. + See frvbf_model_.... */ + hsr0 = GET_HSR0 (); + cache = CPU_DATA_CACHE (current_cpu); + if (model_insn) + { + CPU_LOAD_ADDRESS (current_cpu) = address; + CPU_LOAD_LENGTH (current_cpu) = 8; + return 0x37111319; /* any random value */ + } + + if (GET_HSR0_DCE (hsr0)) + { + int cycles; + /* Handle access which crosses cache line boundary */ + SIM_DESC sd = CPU_STATE (current_cpu); + if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550) + { + if (DATA_CROSSES_CACHE_LINE (cache, address, 8)) + return read_mem_unaligned_DI (current_cpu, pc, address); + } + cycles = frv_cache_read (cache, 0, address); + if (cycles != 0) + return CACHE_RETURN_DATA (cache, 0, address, DF, 8); + } + + return GETMEMDF (current_cpu, pc, address); +} + +USI +frvbf_read_imem_USI (SIM_CPU *current_cpu, PCADDR vpc) +{ + USI hsr0; + vpc = check_insn_read_address (current_cpu, vpc, 3); + + hsr0 = GET_HSR0 (); + if (GET_HSR0_ICE (hsr0)) + { + FRV_CACHE *cache; + USI value; + + /* We don't want this to show up in the cache statistics. That read + is done in frvbf_simulate_insn_prefetch. So read the cache or memory + passively here. */ + cache = CPU_INSN_CACHE (current_cpu); + if (frv_cache_read_passive_SI (cache, vpc, &value)) + return value; + } + return sim_core_read_unaligned_4 (current_cpu, vpc, read_map, vpc); +} + +static SI +fr400_check_write_address (SIM_CPU *current_cpu, SI address, int align_mask) +{ + if (address & align_mask) + { + /* On the fr400, this causes a data_access_error. */ + /* Make sure that this exception is not masked. */ + USI isr = GET_ISR (); + if (! GET_ISR_EMAM (isr)) + { + /* Bad alignment causes a data_access_error on fr400. */ + frv_queue_data_access_error_interrupt (current_cpu, address); + } + address &= ~align_mask; + } + if (align_mask == 7 + && address >= 0xfe800000 && address <= 0xfeffffff) + frv_queue_program_interrupt (current_cpu, FRV_DATA_STORE_ERROR); + + return address; +} + +static SI +fr500_check_write_address (SIM_CPU *current_cpu, SI address, int align_mask) +{ + if (address & align_mask) + { + struct frv_interrupt_queue_element *item = + frv_queue_mem_address_not_aligned_interrupt (current_cpu, address); + /* Record the correct vliw slot with the interrupt. */ + if (item != NULL) + item->slot = frv_interrupt_state.slot; + address &= ~align_mask; + } + if (address >= 0xfeff0600 && address <= 0xfeff7fff + || address >= 0xfe800000 && address <= 0xfefeffff) + frv_queue_program_interrupt (current_cpu, FRV_DATA_STORE_ERROR); + + return address; +} + +static SI +fr550_check_write_address (SIM_CPU *current_cpu, SI address, int align_mask) +{ + if ((USI)address >= 0xfe800000 && (USI)address <= 0xfefeffff + || (align_mask > 0x3 + && ((USI)address >= 0xfeff0000 && (USI)address <= 0xfeffffff))) + frv_queue_program_interrupt (current_cpu, FRV_DATA_STORE_ERROR); + + return address; +} + +static SI +check_write_address (SIM_CPU *current_cpu, SI address, int align_mask) +{ + SIM_DESC sd = CPU_STATE (current_cpu); + switch (STATE_ARCHITECTURE (sd)->mach) + { + case bfd_mach_fr400: + address = fr400_check_write_address (current_cpu, address, align_mask); + break; + case bfd_mach_frvtomcat: + case bfd_mach_fr500: + case bfd_mach_frv: + address = fr500_check_write_address (current_cpu, address, align_mask); + break; + case bfd_mach_fr550: + address = fr550_check_write_address (current_cpu, address, align_mask); + break; + default: + break; + } + return address; +} + +void +frvbf_write_mem_QI (SIM_CPU *current_cpu, IADDR pc, SI address, QI value) +{ + USI hsr0; + hsr0 = GET_HSR0 (); + if (GET_HSR0_DCE (hsr0)) + sim_queue_fn_mem_qi_write (current_cpu, frvbf_mem_set_QI, address, value); + else + sim_queue_mem_qi_write (current_cpu, address, value); + frv_set_write_queue_slot (current_cpu); +} + +void +frvbf_write_mem_UQI (SIM_CPU *current_cpu, IADDR pc, SI address, UQI value) +{ + frvbf_write_mem_QI (current_cpu, pc, address, value); +} + +void +frvbf_write_mem_HI (SIM_CPU *current_cpu, IADDR pc, SI address, HI value) +{ + USI hsr0; + hsr0 = GET_HSR0 (); + if (GET_HSR0_DCE (hsr0)) + sim_queue_fn_mem_hi_write (current_cpu, frvbf_mem_set_HI, address, value); + else + sim_queue_mem_hi_write (current_cpu, address, value); + frv_set_write_queue_slot (current_cpu); +} + +void +frvbf_write_mem_UHI (SIM_CPU *current_cpu, IADDR pc, SI address, UHI value) +{ + frvbf_write_mem_HI (current_cpu, pc, address, value); +} + +void +frvbf_write_mem_SI (SIM_CPU *current_cpu, IADDR pc, SI address, SI value) +{ + USI hsr0; + hsr0 = GET_HSR0 (); + if (GET_HSR0_DCE (hsr0)) + sim_queue_fn_mem_si_write (current_cpu, frvbf_mem_set_SI, address, value); + else + sim_queue_mem_si_write (current_cpu, address, value); + frv_set_write_queue_slot (current_cpu); +} + +void +frvbf_write_mem_WI (SIM_CPU *current_cpu, IADDR pc, SI address, SI value) +{ + frvbf_write_mem_SI (current_cpu, pc, address, value); +} + +void +frvbf_write_mem_DI (SIM_CPU *current_cpu, IADDR pc, SI address, DI value) +{ + USI hsr0; + hsr0 = GET_HSR0 (); + if (GET_HSR0_DCE (hsr0)) + sim_queue_fn_mem_di_write (current_cpu, frvbf_mem_set_DI, address, value); + else + sim_queue_mem_di_write (current_cpu, address, value); + frv_set_write_queue_slot (current_cpu); +} + +void +frvbf_write_mem_DF (SIM_CPU *current_cpu, IADDR pc, SI address, DF value) +{ + USI hsr0; + hsr0 = GET_HSR0 (); + if (GET_HSR0_DCE (hsr0)) + sim_queue_fn_mem_df_write (current_cpu, frvbf_mem_set_DF, address, value); + else + sim_queue_mem_df_write (current_cpu, address, value); + frv_set_write_queue_slot (current_cpu); +} + +/* Memory writes. These do the actual writing through the cache. */ +void +frvbf_mem_set_QI (SIM_CPU *current_cpu, IADDR pc, SI address, QI value) +{ + FRV_CACHE *cache = CPU_DATA_CACHE (current_cpu); + + /* Check for access errors. */ + address = check_write_address (current_cpu, address, 0); + address = check_readwrite_address (current_cpu, address, 0); + + /* If we need to count cycles, then submit the write request to the cache + and let it prioritize the request. Otherwise perform the write now. */ + if (model_insn) + { + int slot = UNIT_I0; + frv_cache_request_store (cache, address, slot, (char *)&value, + sizeof (value)); + } + else + frv_cache_write (cache, address, (char *)&value, sizeof (value)); +} + +/* Write a HI which spans two cache lines */ +static void +mem_set_unaligned_HI (SIM_CPU *current_cpu, IADDR pc, SI address, HI value) +{ + FRV_CACHE *cache = CPU_DATA_CACHE (current_cpu); + /* value is already in target byte order */ + frv_cache_write (cache, address, (char *)&value, 1); + frv_cache_write (cache, address + 1, ((char *)&value + 1), 1); +} + +void +frvbf_mem_set_HI (SIM_CPU *current_cpu, IADDR pc, SI address, HI value) +{ + FRV_CACHE *cache; + + /* Check for access errors. */ + address = check_write_address (current_cpu, address, 1); + address = check_readwrite_address (current_cpu, address, 1); + + /* If we need to count cycles, then submit the write request to the cache + and let it prioritize the request. Otherwise perform the write now. */ + value = H2T_2 (value); + cache = CPU_DATA_CACHE (current_cpu); + if (model_insn) + { + int slot = UNIT_I0; + frv_cache_request_store (cache, address, slot, + (char *)&value, sizeof (value)); + } + else + { + /* Handle access which crosses cache line boundary */ + SIM_DESC sd = CPU_STATE (current_cpu); + if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550) + { + if (DATA_CROSSES_CACHE_LINE (cache, address, 2)) + { + mem_set_unaligned_HI (current_cpu, pc, address, value); + return; + } + } + frv_cache_write (cache, address, (char *)&value, sizeof (value)); + } +} + +/* Write a SI which spans two cache lines */ +static void +mem_set_unaligned_SI (SIM_CPU *current_cpu, IADDR pc, SI address, SI value) +{ + FRV_CACHE *cache = CPU_DATA_CACHE (current_cpu); + unsigned hi_len = cache->line_size - (address & (cache->line_size - 1)); + /* value is already in target byte order */ + frv_cache_write (cache, address, (char *)&value, hi_len); + frv_cache_write (cache, address + hi_len, (char *)&value + hi_len, 4 - hi_len); +} + +void +frvbf_mem_set_SI (SIM_CPU *current_cpu, IADDR pc, SI address, SI value) +{ + FRV_CACHE *cache; + + /* Check for access errors. */ + address = check_write_address (current_cpu, address, 3); + address = check_readwrite_address (current_cpu, address, 3); + + /* If we need to count cycles, then submit the write request to the cache + and let it prioritize the request. Otherwise perform the write now. */ + cache = CPU_DATA_CACHE (current_cpu); + value = H2T_4 (value); + if (model_insn) + { + int slot = UNIT_I0; + frv_cache_request_store (cache, address, slot, + (char *)&value, sizeof (value)); + } + else + { + /* Handle access which crosses cache line boundary */ + SIM_DESC sd = CPU_STATE (current_cpu); + if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550) + { + if (DATA_CROSSES_CACHE_LINE (cache, address, 4)) + { + mem_set_unaligned_SI (current_cpu, pc, address, value); + return; + } + } + frv_cache_write (cache, address, (char *)&value, sizeof (value)); + } +} + +/* Write a DI which spans two cache lines */ +static void +mem_set_unaligned_DI (SIM_CPU *current_cpu, IADDR pc, SI address, DI value) +{ + FRV_CACHE *cache = CPU_DATA_CACHE (current_cpu); + unsigned hi_len = cache->line_size - (address & (cache->line_size - 1)); + /* value is already in target byte order */ + frv_cache_write (cache, address, (char *)&value, hi_len); + frv_cache_write (cache, address + hi_len, (char *)&value + hi_len, 8 - hi_len); +} + +void +frvbf_mem_set_DI (SIM_CPU *current_cpu, IADDR pc, SI address, DI value) +{ + FRV_CACHE *cache; + + /* Check for access errors. */ + address = check_write_address (current_cpu, address, 7); + address = check_readwrite_address (current_cpu, address, 7); + + /* If we need to count cycles, then submit the write request to the cache + and let it prioritize the request. Otherwise perform the write now. */ + value = H2T_8 (value); + cache = CPU_DATA_CACHE (current_cpu); + if (model_insn) + { + int slot = UNIT_I0; + frv_cache_request_store (cache, address, slot, + (char *)&value, sizeof (value)); + } + else + { + /* Handle access which crosses cache line boundary */ + SIM_DESC sd = CPU_STATE (current_cpu); + if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550) + { + if (DATA_CROSSES_CACHE_LINE (cache, address, 8)) + { + mem_set_unaligned_DI (current_cpu, pc, address, value); + return; + } + } + frv_cache_write (cache, address, (char *)&value, sizeof (value)); + } +} + +void +frvbf_mem_set_DF (SIM_CPU *current_cpu, IADDR pc, SI address, DF value) +{ + FRV_CACHE *cache; + + /* Check for access errors. */ + address = check_write_address (current_cpu, address, 7); + address = check_readwrite_address (current_cpu, address, 7); + + /* If we need to count cycles, then submit the write request to the cache + and let it prioritize the request. Otherwise perform the write now. */ + value = H2T_8 (value); + cache = CPU_DATA_CACHE (current_cpu); + if (model_insn) + { + int slot = UNIT_I0; + frv_cache_request_store (cache, address, slot, + (char *)&value, sizeof (value)); + } + else + { + /* Handle access which crosses cache line boundary */ + SIM_DESC sd = CPU_STATE (current_cpu); + if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550) + { + if (DATA_CROSSES_CACHE_LINE (cache, address, 8)) + { + mem_set_unaligned_DI (current_cpu, pc, address, value); + return; + } + } + frv_cache_write (cache, address, (char *)&value, sizeof (value)); + } +} + +void +frvbf_mem_set_XI (SIM_CPU *current_cpu, IADDR pc, SI address, SI *value) +{ + int i; + FRV_CACHE *cache; + + /* Check for access errors. */ + address = check_write_address (current_cpu, address, 0xf); + address = check_readwrite_address (current_cpu, address, 0xf); + + /* TODO -- reverse word order as well? */ + for (i = 0; i < 4; ++i) + value[i] = H2T_4 (value[i]); + + /* If we need to count cycles, then submit the write request to the cache + and let it prioritize the request. Otherwise perform the write now. */ + cache = CPU_DATA_CACHE (current_cpu); + if (model_insn) + { + int slot = UNIT_I0; + frv_cache_request_store (cache, address, slot, (char*)value, 16); + } + else + frv_cache_write (cache, address, (char*)value, 16); +} + +/* Record the current VLIW slot on the element at the top of the write queue. +*/ +void +frv_set_write_queue_slot (SIM_CPU *current_cpu) +{ + FRV_VLIW *vliw = CPU_VLIW (current_cpu); + int slot = vliw->next_slot - 1; + CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (current_cpu); + int ix = CGEN_WRITE_QUEUE_INDEX (q) - 1; + CGEN_WRITE_QUEUE_ELEMENT *item = CGEN_WRITE_QUEUE_ELEMENT (q, ix); + CGEN_WRITE_QUEUE_ELEMENT_PIPE (item) = (*vliw->current_vliw)[slot]; +} diff --git a/sim/frv/mloop.in b/sim/frv/mloop.in new file mode 100644 index 0000000..073d81d --- /dev/null +++ b/sim/frv/mloop.in @@ -0,0 +1,520 @@ +# Simulator main loop for frv. -*- C -*- +# Copyright (C) 1998, 1999, 2000, 2001, 2003 Free Software Foundation, Inc. +# Contributed by Red Hat. +# +# This file is part of the GNU Simulators. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2, or (at your option) +# any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License along +# with this program; if not, write to the Free Software Foundation, Inc., +# 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# Syntax: +# /bin/sh mainloop.in command +# +# Command is one of: +# +# init +# support +# extract-{simple,scache,pbb} +# {full,fast}-exec-{simple,scache,pbb} +# +# A target need only provide a "full" version of one of simple,scache,pbb. +# If the target wants it can also provide a fast version of same. +# It can't provide more than this. + +# ??? After a few more ports are done, revisit. +# Will eventually need to machine generate a lot of this. + +case "x$1" in + +xsupport) + +cat <argbuf.semantic.sem_fast) (current_cpu, sc); + } + else + { + ARGBUF *abuf = &sc->argbuf; + const IDESC *idesc = abuf->idesc; +#if WITH_SCACHE_PBB + int virtual_p = CGEN_ATTR_VALUE (NULL, idesc->attrs, CGEN_INSN_VIRTUAL); +#else + int virtual_p = 0; +#endif + + if (! virtual_p) + { + /* FIXME: call x-before */ + if (ARGBUF_PROFILE_P (abuf)) + PROFILE_COUNT_INSN (current_cpu, abuf->addr, idesc->num); + /* FIXME: Later make cover macros: PROFILE_INSN_{INIT,FINI}. */ + if (FRV_COUNT_CYCLES (current_cpu, ARGBUF_PROFILE_P (abuf))) + { + @cpu@_model_insn_before (current_cpu, sc->first_insn_p); + model_insn = FRV_INSN_MODEL_PASS_1; + if (idesc->timing->model_fn != NULL) + (*idesc->timing->model_fn) (current_cpu, sc); + } + else + model_insn = FRV_INSN_NO_MODELING; + TRACE_INSN_INIT (current_cpu, abuf, 1); + TRACE_INSN (current_cpu, idesc->idata, + (const struct argbuf *) abuf, abuf->addr); + } +#if WITH_SCACHE + vpc = (*sc->argbuf.semantic.sem_full) (current_cpu, sc); +#else + vpc = (*sc->argbuf.semantic.sem_full) (current_cpu, abuf); +#endif + if (! virtual_p) + { + /* FIXME: call x-after */ + if (FRV_COUNT_CYCLES (current_cpu, ARGBUF_PROFILE_P (abuf))) + { + int cycles; + if (idesc->timing->model_fn != NULL) + { + model_insn = FRV_INSN_MODEL_PASS_2; + cycles = (*idesc->timing->model_fn) (current_cpu, sc); + } + else + cycles = 1; + @cpu@_model_insn_after (current_cpu, sc->last_insn_p, cycles); + } + TRACE_INSN_FINI (current_cpu, abuf, 1); + } + } + + return vpc; +} + +static void +@cpu@_parallel_write_init (SIM_CPU *current_cpu) +{ + CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (current_cpu); + CGEN_WRITE_QUEUE_CLEAR (q); + previous_vliw_pc = CPU_PC_GET(current_cpu); + frv_interrupt_state.f_ne_flags[0] = 0; + frv_interrupt_state.f_ne_flags[1] = 0; + frv_interrupt_state.imprecise_interrupt = NULL; +} + +static void +@cpu@_parallel_write_queued (SIM_CPU *current_cpu) +{ + int i; + + FRV_VLIW *vliw = CPU_VLIW (current_cpu); + CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (current_cpu); + + /* Loop over the queued writes, executing them. Set the pc to the address + of the insn which queued each write for the proper context in case an + interrupt is caused. Restore the proper pc after the writes are + completed. */ + IADDR save_pc = CPU_PC_GET (current_cpu); + IADDR new_pc = save_pc; + int branch_taken = 0; + int limit = CGEN_WRITE_QUEUE_INDEX (q); + frv_interrupt_state.data_written.length = 0; + + for (i = 0; i < limit; ++i) + { + CGEN_WRITE_QUEUE_ELEMENT *item = CGEN_WRITE_QUEUE_ELEMENT (q, i); + + /* If an imprecise interrupt was generated, then, check whether the + result should still be written. */ + if (frv_interrupt_state.imprecise_interrupt != NULL) + { + /* Only check writes by the insn causing the exception. */ + if (CGEN_WRITE_QUEUE_ELEMENT_IADDR (item) + == frv_interrupt_state.imprecise_interrupt->vpc) + { + /* Execute writes of floating point operations resulting in + overflow, underflow or inexact. */ + if (frv_interrupt_state.imprecise_interrupt->kind + == FRV_FP_EXCEPTION) + { + if ((frv_interrupt_state.imprecise_interrupt + ->u.fp_info.fsr_mask + & ~(FSR_INEXACT | FSR_OVERFLOW | FSR_UNDERFLOW))) + continue; /* Don't execute */ + } + /* Execute writes marked as 'forced'. */ + else if (! (CGEN_WRITE_QUEUE_ELEMENT_FLAGS (item) + & FRV_WRITE_QUEUE_FORCE_WRITE)) + continue; /* Don't execute */ + } + } + + /* Only execute the first branch on the queue. */ + if (CGEN_WRITE_QUEUE_ELEMENT_KIND (item) == CGEN_PC_WRITE + || CGEN_WRITE_QUEUE_ELEMENT_KIND (item) == CGEN_FN_PC_WRITE) + { + if (branch_taken) + continue; + branch_taken = 1; + if (CGEN_WRITE_QUEUE_ELEMENT_KIND (item) == CGEN_PC_WRITE) + new_pc = item->kinds.pc_write.value; + else + new_pc = item->kinds.fn_pc_write.value; + } + + CPU_PC_SET (current_cpu, CGEN_WRITE_QUEUE_ELEMENT_IADDR (item)); + frv_save_data_written_for_interrupts (current_cpu, item); + cgen_write_queue_element_execute (current_cpu, item); + } + + /* Update the LR with the address of the next insn if the flag is set. + This flag gets set in frvbf_set_write_next_vliw_to_LR by the JMPL, + JMPIL and CALL insns. */ + if (frvbf_write_next_vliw_addr_to_LR) + { + frvbf_h_spr_set_handler (current_cpu, H_SPR_LR, save_pc); + frvbf_write_next_vliw_addr_to_LR = 0; + } + + CPU_PC_SET (current_cpu, new_pc); + CGEN_WRITE_QUEUE_CLEAR (q); +} + +void +@cpu@_perform_writeback (SIM_CPU *current_cpu) +{ + @cpu@_parallel_write_queued (current_cpu); +} + +static unsigned cache_reqno = 0x80000000; /* Start value is for debugging. */ + +#if 0 /* experimental */ +/* FR400 has single prefetch. */ +static void +fr400_simulate_insn_prefetch (SIM_CPU *current_cpu, IADDR vpc) +{ + int cur_ix; + FRV_CACHE *cache; + +/* The cpu receives 8 bytes worth of insn data for each fetch aligned + on 8 byte boundary. */ +#define FR400_FETCH_SIZE 8 + + cur_ix = LS; + vpc &= ~(FR400_FETCH_SIZE - 1); + cache = CPU_INSN_CACHE (current_cpu); + + /* Request a load of the current address buffer, if necessary. */ + if (frv_insn_fetch_buffer[cur_ix].address != vpc) + { + frv_insn_fetch_buffer[cur_ix].address = vpc; + frv_insn_fetch_buffer[cur_ix].reqno = cache_reqno++; + if (FRV_COUNT_CYCLES (current_cpu, 1)) + frv_cache_request_load (cache, frv_insn_fetch_buffer[cur_ix].reqno, + frv_insn_fetch_buffer[cur_ix].address, + UNIT_I0 + cur_ix); + } + + /* Wait for the current address buffer to be loaded, if necessary. */ + if (FRV_COUNT_CYCLES (current_cpu, 1)) + { + FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (current_cpu); + int wait; + + /* Account for any branch penalty. */ + if (ps->branch_penalty > 0 && ! ps->past_first_p) + { + frv_model_advance_cycles (current_cpu, ps->branch_penalty); + frv_model_trace_wait_cycles (current_cpu, ps->branch_penalty, + "Branch penalty:"); + ps->branch_penalty = 0; + } + + /* Account for insn fetch latency. */ + wait = 0; + while (frv_insn_fetch_buffer[cur_ix].reqno != NO_REQNO) + { + frv_model_advance_cycles (current_cpu, 1); + ++wait; + } + frv_model_trace_wait_cycles (current_cpu, wait, "Insn fetch:"); + return; + } + + /* Otherwise just load the insns directly from the cache. + */ + if (frv_insn_fetch_buffer[cur_ix].reqno != NO_REQNO) + { + frv_cache_read (cache, cur_ix, vpc); + frv_insn_fetch_buffer[cur_ix].reqno = NO_REQNO; + } +} +#endif /* experimental */ + +/* FR500 has dual prefetch. */ +static void +simulate_dual_insn_prefetch (SIM_CPU *current_cpu, IADDR vpc, int fetch_size) +{ + int i; + int cur_ix, pre_ix; + SI pre_address; + FRV_CACHE *cache; + + /* See if the pc is within the addresses specified by either of the + fetch buffers. If so, that will be the current buffer. Otherwise, + arbitrarily select the LD buffer as the current one since it gets + priority in the case of interfering load requests. */ + cur_ix = LD; + vpc &= ~(fetch_size - 1); + for (i = LS; i < FRV_CACHE_PIPELINES; ++i) + { + if (frv_insn_fetch_buffer[i].address == vpc) + { + cur_ix = i; + break; + } + } + cache = CPU_INSN_CACHE (current_cpu); + + /* Request a load of the current address buffer, if necessary. */ + if (frv_insn_fetch_buffer[cur_ix].address != vpc) + { + frv_insn_fetch_buffer[cur_ix].address = vpc; + frv_insn_fetch_buffer[cur_ix].reqno = cache_reqno++; + if (FRV_COUNT_CYCLES (current_cpu, 1)) + frv_cache_request_load (cache, frv_insn_fetch_buffer[cur_ix].reqno, + frv_insn_fetch_buffer[cur_ix].address, + UNIT_I0 + cur_ix); + } + + /* If the prefetch buffer does not represent the next sequential address, then + request a load of the next sequential address. */ + pre_ix = (cur_ix + 1) % FRV_CACHE_PIPELINES; + pre_address = vpc + fetch_size; + if (frv_insn_fetch_buffer[pre_ix].address != pre_address) + { + frv_insn_fetch_buffer[pre_ix].address = pre_address; + frv_insn_fetch_buffer[pre_ix].reqno = cache_reqno++; + if (FRV_COUNT_CYCLES (current_cpu, 1)) + frv_cache_request_load (cache, frv_insn_fetch_buffer[pre_ix].reqno, + frv_insn_fetch_buffer[pre_ix].address, + UNIT_I0 + pre_ix); + } + + /* If counting cycles, account for any branch penalty and/or insn fetch + latency here. */ + if (FRV_COUNT_CYCLES (current_cpu, 1)) + { + FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (current_cpu); + int wait; + + /* Account for any branch penalty. */ + if (ps->branch_penalty > 0 && ! ps->past_first_p) + { + frv_model_advance_cycles (current_cpu, ps->branch_penalty); + frv_model_trace_wait_cycles (current_cpu, ps->branch_penalty, + "Branch penalty:"); + ps->branch_penalty = 0; + } + + /* Account for insn fetch latency. */ + wait = 0; + while (frv_insn_fetch_buffer[cur_ix].reqno != NO_REQNO) + { + frv_model_advance_cycles (current_cpu, 1); + ++wait; + } + frv_model_trace_wait_cycles (current_cpu, wait, "Insn fetch:"); + return; + } + + /* Otherwise just load the insns directly from the cache. + */ + if (frv_insn_fetch_buffer[cur_ix].reqno != NO_REQNO) + { + frv_cache_read (cache, cur_ix, vpc); + frv_insn_fetch_buffer[cur_ix].reqno = NO_REQNO; + } + if (frv_insn_fetch_buffer[pre_ix].reqno != NO_REQNO) + { + frv_cache_read (cache, pre_ix, pre_address); + frv_insn_fetch_buffer[pre_ix].reqno = NO_REQNO; + } +} + +static void +@cpu@_simulate_insn_prefetch (SIM_CPU *current_cpu, IADDR vpc) +{ + SI hsr0; + SIM_DESC sd; + + /* Nothing to do if not counting cycles and the cache is not enabled. */ + hsr0 = GET_HSR0 (); + if (! GET_HSR0_ICE (hsr0) && ! FRV_COUNT_CYCLES (current_cpu, 1)) + return; + + /* Different machines handle prefetch defferently. */ + sd = CPU_STATE (current_cpu); + switch (STATE_ARCHITECTURE (sd)->mach) + { + case bfd_mach_fr400: + simulate_dual_insn_prefetch (current_cpu, vpc, 8); + break; + case bfd_mach_frvtomcat: + case bfd_mach_fr500: + case bfd_mach_fr550: + case bfd_mach_frv: + simulate_dual_insn_prefetch (current_cpu, vpc, 16); + break; + default: + break; + } +} + +int frv_save_profile_model_p; +EOF + +;; + +xinit) + +cat <mach, + CPU_ELF_FLAGS (current_cpu)); + frv_current_fm_slot = UNIT_NIL; + + for (ninsns = 0; ! last_insn_p && ninsns < FRV_VLIW_SIZE; ++ninsns) + { + SCACHE *sc; + const CGEN_INSN *insn; + int error; + /* Go through the motions of finding the insns in the cache. */ + @cpu@_simulate_insn_prefetch (current_cpu, vpc); + + sc = @cpu@_scache_lookup (current_cpu, vpc, scache, hash_mask, FAST_P); + sc->first_insn_p = first_insn_p; + last_insn_p = sc->last_insn_p; + + /* Add the insn to the vliw and set up the interrupt state. */ + insn = sc->argbuf.idesc->idata; + error = frv_vliw_add_insn (vliw, insn); + if (! error) + frv_vliw_setup_insn (current_cpu, insn); + frv_detect_insn_access_interrupts (current_cpu, sc); + slot = (*vliw->current_vliw)[vliw->next_slot - 1]; + if (slot >= UNIT_FM0 && slot <= UNIT_FM3) + frv_current_fm_slot = slot; + + vpc = execute (current_cpu, sc, FAST_P); + + SET_H_PC (vpc); /* needed for interrupt handling */ + first_insn_p = 0; + } + + /* If the timer is enabled, and model profiling was not originally enabled, + then turn it off again. This is the only place we can currently gain + control to do this. */ + if (frv_interrupt_state.timer.enabled && ! frv_save_profile_model_p) + sim_profile_set_option (current_state, "-model", PROFILE_MODEL_IDX, "0"); + + /* Check for interrupts. Also handles writeback if necessary. */ + frv_process_interrupts (current_cpu); + + CPU_INSN_COUNT (current_cpu) += ninsns; +} +EOF + +;; + +*) + echo "Invalid argument to mainloop.in: $1" >&2 + exit 1 + ;; + +esac diff --git a/sim/frv/model.c b/sim/frv/model.c new file mode 100644 index 0000000..864c180 --- /dev/null +++ b/sim/frv/model.c @@ -0,0 +1,91181 @@ +/* Simulator model support for frvbf. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. + +This file is part of the GNU simulators. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +*/ + +#define WANT_CPU frvbf +#define WANT_CPU_FRVBF + +#include "sim-main.h" + +/* The profiling data is recorded here, but is accessed via the profiling + mechanism. After all, this is information for profiling. */ + +#if WITH_PROFILE_MODEL_P + +/* Model handlers for each insn. */ + +static int +model_frv_add (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_sub (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_and (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_or (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_xor (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_not (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_scutss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_sdiv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_nsdiv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_udiv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_nudiv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_smul (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_umul (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_smu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smass.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_smass (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smass.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_smsss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smass.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_sll (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_srl (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_sra (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_slass (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_scutss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_scutss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_scan (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cadd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_csub (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cand (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cor (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cxor (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cnot (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_csmul (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_csdiv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cudiv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_csll (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_csrl (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_csra (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cscan (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_addcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_subcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_andcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_orcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_xorcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_sllcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_srlcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_sracc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_smulcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_umulcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_caddcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_caddcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_csubcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_caddcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_csmulcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_csmulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_candcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_caddcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_corcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_caddcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cxorcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_caddcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_csllcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_caddcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_csrlcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_caddcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_csracc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_caddcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_addx (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_subx (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_addxcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_subxcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_addss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_subss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_addi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_subi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_andi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_ori (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_xori (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_sdivi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_nsdivi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_udivi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_nudivi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_smuli (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smuli.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_umuli (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smuli.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_slli (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_srli (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_srai (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_scani (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_addicc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_subicc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_andicc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_oricc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_xoricc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_smulicc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_umulicc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_sllicc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_srlicc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_sraicc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_addxi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_subxi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_addxicc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_subxicc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cmpb (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cmpba (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_setlo (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_setlo.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_sethi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_sethi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_setlos (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_setlos.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_ldsb (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_ldub (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_ldsh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_lduh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_ld (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_ldbf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_ldhf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_ldf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_ldc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_nldsb (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_nldub (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_nldsh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_nlduh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_nld (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_nldbf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_nldhf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_nldf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_ldd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_lddf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_lddc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_lddcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_nldd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_nlddf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_ldq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_ldqf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_ldqc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_nldq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_nldqf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_ldsbu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_ldubu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_ldshu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_lduhu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_ldu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_nldsbu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_nldubu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_nldshu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_nlduhu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_nldu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_ldbfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_ldhfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_ldfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_ldcu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_nldbfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_nldhfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_nldfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_lddu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_nlddu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_lddfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_lddcu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_lddcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_nlddfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_ldqu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_nldqu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_ldqfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_ldqcu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_nldqfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_ldsbi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_ldshi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_ldi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_ldubi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_lduhi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_ldbfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldbfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_ldhfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldbfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_ldfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldbfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_nldsbi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_nldubi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_nldshi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_nlduhi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_nldi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_nldbfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldbfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_nldhfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldbfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_nldfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldbfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_lddi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smuli.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_lddfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_lddfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_nlddi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smuli.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_nlddfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_lddfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_ldqi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_ldqfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_nldqfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_stb (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_sth (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_st (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_stbf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_sthf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_stf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_stc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_rstb (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_rsth (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_rst (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_rstbf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_rsthf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_rstf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_std (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_stdf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_stdc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_rstd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_rstdf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_stq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_stqf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_stqc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_rstq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_rstqf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_stbu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_sthu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_stu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_stbfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_sthfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_stfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_stcu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_stdu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_stdfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_stdcu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_stqu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_stqfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_stqcu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cldsb (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cldub (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cldsh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_clduh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cld (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cldbf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cldhf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cldf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cldd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_clddf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cldq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cldsbu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cldubu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cldshu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_clduhu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cldu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cldbfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cldhfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cldfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_clddu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_clddfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cldqu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cstb (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_csth (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cst (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cstbf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_csthf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cstf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cstd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cstdf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cstq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cstbu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_csthu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cstu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cstbfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_csthfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cstfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cstdu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cstdfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_stbi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_sthi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_sti (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_stbfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stbfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_sthfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stbfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_stfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stbfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_stdi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_stdfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_stqi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_stqfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_swap (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_swapi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cswap (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_movgf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmovgfd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_movfg (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmovfgd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_movgfd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmovgfd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_movfgd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmovfgd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_movgfq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_movgfq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_movfgq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_movfgq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cmovgf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmovgfd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cmovfg (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmovfgd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cmovgfd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmovgfd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cmovfgd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmovfgd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_movgs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_movgs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_movsg (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_movsg.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_bra (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_bno (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_beq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_bne (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_ble (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_bgt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_blt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_bge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_bls (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_bhi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_bc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_bnc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_bn (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_bp (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_bv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_bnv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fbra (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fbno (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fbne (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fbeq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fblg (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fbue (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fbul (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fbge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fblt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fbuge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fbug (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fble (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fbgt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fbule (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fbu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fbo (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_bctrlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_bralr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_bnolr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_beqlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_bnelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_blelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_bgtlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_bltlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_bgelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_blslr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_bhilr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_bclr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_bnclr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_bnlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_bplr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_bvlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_bnvlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fbralr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fbnolr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fbeqlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fbnelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fblglr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fbuelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fbullr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fbgelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fbltlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fbugelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fbuglr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fblelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fbgtlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fbulelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fbulr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fbolr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_bcralr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_bcnolr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_bceqlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_bcnelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_bclelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_bcgtlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_bcltlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_bcgelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_bclslr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_bchilr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_bcclr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_bcnclr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_bcnlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_bcplr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_bcvlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_bcnvlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fcbralr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fcbnolr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fcbeqlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fcbnelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fcblglr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fcbuelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fcbullr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fcbgelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fcbltlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fcbugelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fcbuglr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fcblelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fcbgtlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fcbulelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fcbulr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fcbolr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_jmpl (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cjmpl.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_calll (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cjmpl.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_jmpil (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_jmpil.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_callil (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_jmpil.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_call (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_call.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_rett (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_rett.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_rei (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_tra (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_tno (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_teq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_tne (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_tle (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_tgt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_tlt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_tge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_tls (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_thi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_tc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_tnc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_tn (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_tp (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_tv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_tnv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_ftra (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_ftno (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_ftne (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fteq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_ftlg (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_ftue (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_ftul (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_ftge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_ftlt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_ftuge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_ftug (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_ftle (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_ftgt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_ftule (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_ftu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fto (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_tira (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_tino (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_tieq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_tine (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_tile (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_tigt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_tilt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_tige (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_tils (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_tihi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_tic (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_tinc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_tin (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_tip (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_tiv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_tinv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_ftira (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_ftino (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_ftine (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_ftieq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_ftilg (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_ftiue (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_ftiul (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_ftige (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_ftilt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_ftiuge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_ftiug (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_ftile (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_ftigt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_ftiule (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_ftiu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_ftio (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_break (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_break.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_mtrap (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_andcr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_andcr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_orcr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_andcr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_xorcr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_andcr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_nandcr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_andcr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_norcr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_andcr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_andncr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_andcr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_orncr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_andcr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_nandncr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_andcr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_norncr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_andcr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_notcr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_andcr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_ckra (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_ckno (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_ckeq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_ckne (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_ckle (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_ckgt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cklt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_ckge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_ckls (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_ckhi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_ckc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cknc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_ckn (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_ckp (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_ckv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cknv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fckra (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fckno (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fckne (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fckeq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fcklg (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fckue (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fckul (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fckge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fcklt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fckuge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fckug (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fckle (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fckgt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fckule (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fcku (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fcko (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cckra (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cckno (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cckeq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cckne (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cckle (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cckgt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_ccklt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cckge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cckls (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cckhi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cckc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_ccknc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cckn (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cckp (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cckv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_ccknv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cfckra (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cfckno (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cfckne (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cfckeq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cfcklg (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cfckue (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cfckul (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cfckge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cfcklt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cfckuge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cfckug (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cfckle (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cfckgt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cfckule (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cfcku (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cfcko (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cjmpl (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cjmpl.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_ccalll (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cjmpl.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_ici (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_icpl.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_dci (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_icpl.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_icei (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_icei.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_dcei (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_icei.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_dcf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_icpl.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_dcef (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_icei.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_witlb (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_wdtlb (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_itlbi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_dtlbi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_icpl (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_icpl.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_dcpl (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_icpl.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_icul (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_jmpil.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_dcul (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_jmpil.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_bar (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_membar (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cop1 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cop2 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_clrgr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_clrfr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_clrga (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_clrfa (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_commitgr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_setlos.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_commitfr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mhsethis.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_commitga (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_commitfa (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fitos (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fditos.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fstoi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdstoi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fitod (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fitod.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fdtoi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdtoi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fditos (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fditos.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fdstoi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdstoi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_nfditos (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fditos.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_nfdstoi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdstoi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cfitos (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfitos.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cfstoi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfstoi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_nfitos (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fditos.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_nfstoi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdstoi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fmovs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fmovd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fmaddd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fdmovs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cfmovs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fnegs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fnegd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fmaddd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fdnegs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cfnegs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fabss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fabsd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fmaddd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fdabss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cfabss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fsqrts (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fdsqrts (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_nfdsqrts (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fsqrtd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fmaddd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cfsqrts (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_nfsqrts (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fadds (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fsubs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fmuls (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fdivs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_faddd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fmaddd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fsubd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fmaddd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fmuld (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fmaddd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fdivd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fmaddd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cfadds (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cfsubs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cfmuls (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cfdivs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_nfadds (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_nfsubs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_nfmuls (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_nfdivs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fcmps (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfcmps.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fcmpd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcmpd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cfcmps (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfcmps.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fdcmps (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_nfdcmps.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fmadds (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fmsubs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fmaddd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fmaddd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fmsubd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fmaddd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fdmadds (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_nfdmadds (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cfmadds (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cfmsubs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_nfmadds (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_nfmsubs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fmas (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fmss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fdmas (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmas.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fdmss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmas.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_nfdmas (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmas.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_nfdmss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmas.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cfmas (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmas.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cfmss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmas.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fmad (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fmsd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_nfmas (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_nfmss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fdadds (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fdsubs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fdmuls (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fddivs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fdsads (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fdmulcs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_nfdmulcs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_nfdadds (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_nfdsubs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_nfdmuls (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_nfddivs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_nfdsads (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_nfdcmps (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_nfdcmps.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_mhsetlos (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mhsetlos.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_mhsethis (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mhsethis.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_mhdsets (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mhdsets.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_mhsetloh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mhsetloh.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_mhsethih (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mhsethih.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_mhdseth (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mhdseth.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_mand (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mwcut.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_mor (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mwcut.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_mxor (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mwcut.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cmand (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmand.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cmor (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmand.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cmxor (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmand.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_mnot (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mcut.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cmnot (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmand.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_mrotli (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mwcuti.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_mrotri (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mwcuti.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_mwcut (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mwcut.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_mwcuti (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mwcuti.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_mcut (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mcut.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_mcuti (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mcuti.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_mcutss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mcut.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_mcutssi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mcuti.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_mdcutssi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdcutssi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_maveh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mwcut.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_msllhi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_msllhi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_msrlhi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_msllhi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_msrahi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_msllhi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_mdrotli (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdrotli.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_mcplhi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mcplhi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_mcpli (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mwcuti.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_msaths (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_mqsaths (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_msathu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_mcmpsh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mcmpsh.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_mcmpuh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mcmpsh.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_mabshs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mabshs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_maddhss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_maddhus (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_msubhss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_msubhus (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cmaddhss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cmaddhus (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cmsubhss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cmsubhus (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_mqaddhss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_mqaddhus (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_mqsubhss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_mqsubhus (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cmqaddhss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cmqaddhus (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cmqsubhss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cmqsubhus (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_maddaccs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdasaccs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_msubaccs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdasaccs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_mdaddaccs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdasaccs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_mdsubaccs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdasaccs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_masaccs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdasaccs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_mdasaccs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdasaccs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_mmulhs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_mmulhu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_mmulxhs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_mmulxhu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cmmulhs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cmmulhu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_mqmulhs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_mqmulhu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_mqmulxhs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_mqmulxhu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cmqmulhs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cmqmulhu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_mmachs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_mmachu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_mmrdhs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_mmrdhu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cmmachs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cmmachu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_mqmachs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_mqmachu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cmqmachs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cmqmachu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_mqxmachs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_mqxmacxhs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_mqmacxhs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_mcpxrs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_mcpxru (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_mcpxis (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_mcpxiu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cmcpxrs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cmcpxru (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cmcpxis (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cmcpxiu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_mqcpxrs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_mqcpxru (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_mqcpxis (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_mqcpxiu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_mexpdhw (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmexpdhw.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cmexpdhw (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmexpdhw.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_mexpdhd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmexpdhd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cmexpdhd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmexpdhd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_mpackh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_mdpackh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdpackh.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_munpackh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_munpackh.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_mdunpackh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdunpackh.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_mbtoh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmbtoh.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cmbtoh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmbtoh.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_mhtob (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmhtob.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cmhtob (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmhtob.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_mbtohe (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmbtohe.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_cmbtohe (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmbtohe.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_mnop (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_mclracc_0 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdasaccs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_mclracc_1 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdasaccs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_mrdacc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mcuti.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_mrdaccg (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mrdaccg.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_mwtacc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_mwtaccg (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mwtaccg.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_mcop1 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_mcop2 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_fnop (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_add (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr550_sub (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr550_and (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr550_or (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr550_xor (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr550_not (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_scutss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr550_sdiv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr550_nsdiv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr550_udiv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr550_nudiv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr550_smul (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRdoublek = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRdoublek = FLD (out_GRdoublek); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_imul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRdoublek, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr550_umul (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRdoublek = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRdoublek = FLD (out_GRdoublek); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_imul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRdoublek, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr550_smu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smass.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_smass (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smass.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_smsss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smass.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_sll (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr550_srl (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr550_sra (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr550_slass (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_scutss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_scutss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_scan (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cadd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 4)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr550_csub (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 4)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cand (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 4)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cor (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 4)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cxor (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 4)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cnot (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 3)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr550_csmul (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRdoublek = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRdoublek = FLD (out_GRdoublek); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 4)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_imul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRdoublek, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr550_csdiv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 5)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cudiv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 5)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr550_csll (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 4)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr550_csrl (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 4)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr550_csra (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 4)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cscan (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 4)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr550_addcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + referenced |= 1 << 3; + cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr550_subcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + referenced |= 1 << 3; + cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr550_andcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + if (insn_referenced & (1 << 4)) referenced |= 1 << 3; + cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr550_orcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + if (insn_referenced & (1 << 4)) referenced |= 1 << 3; + cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr550_xorcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + if (insn_referenced & (1 << 4)) referenced |= 1 << 3; + cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr550_sllcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + referenced |= 1 << 3; + cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr550_srlcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + referenced |= 1 << 3; + cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr550_sracc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + referenced |= 1 << 3; + cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr550_smulcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRdoublek = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRdoublek = FLD (out_GRdoublek); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + referenced |= 1 << 3; + cycles += frvbf_model_fr550_u_imul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRdoublek, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr550_umulcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRdoublek = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRdoublek = FLD (out_GRdoublek); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + referenced |= 1 << 3; + cycles += frvbf_model_fr550_u_imul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRdoublek, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr550_caddcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_caddcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr550_csubcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_caddcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr550_csmulcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_csmulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRdoublek = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRdoublek = FLD (out_GRdoublek); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_imul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRdoublek, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr550_candcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_caddcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr550_corcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_caddcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cxorcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_caddcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr550_csllcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_caddcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr550_csrlcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_caddcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr550_csracc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_caddcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr550_addx (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr550_subx (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr550_addxcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + referenced |= 1 << 3; + cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr550_subxcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + referenced |= 1 << 3; + cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr550_addss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_subss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_addi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr550_subi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr550_andi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr550_ori (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr550_xori (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr550_sdivi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr550_nsdivi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr550_udivi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr550_nudivi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr550_smuli (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smuli.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRdoublek = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRdoublek = FLD (out_GRdoublek); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_imul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRdoublek, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr550_umuli (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smuli.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRdoublek = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRdoublek = FLD (out_GRdoublek); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_imul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRdoublek, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr550_slli (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr550_srli (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr550_srai (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr550_scani (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr550_addicc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 2; + referenced |= 1 << 3; + cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr550_subicc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 2; + referenced |= 1 << 3; + cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr550_andicc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 2; + if (insn_referenced & (1 << 4)) referenced |= 1 << 3; + cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr550_oricc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 2; + if (insn_referenced & (1 << 4)) referenced |= 1 << 3; + cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr550_xoricc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 2; + if (insn_referenced & (1 << 4)) referenced |= 1 << 3; + cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr550_smulicc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRdoublek = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRdoublek = FLD (out_GRdoublek); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 2; + referenced |= 1 << 3; + cycles += frvbf_model_fr550_u_imul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRdoublek, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr550_umulicc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRdoublek = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRdoublek = FLD (out_GRdoublek); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 2; + referenced |= 1 << 3; + cycles += frvbf_model_fr550_u_imul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRdoublek, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr550_sllicc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 2; + referenced |= 1 << 3; + cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr550_srlicc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 2; + referenced |= 1 << 3; + cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr550_sraicc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 2; + referenced |= 1 << 3; + cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr550_addxi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr550_subxi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr550_addxicc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 2; + referenced |= 1 << 3; + cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr550_subxicc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 2; + referenced |= 1 << 3; + cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cmpb (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cmpba (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr550_setlo (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_setlo.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT out_GRkhi = -1; + INT out_GRklo = -1; + out_GRklo = FLD (out_GRklo); + referenced |= 1 << 1; + cycles += frvbf_model_fr550_u_set_hilo (current_cpu, idesc, 0, referenced, out_GRkhi, out_GRklo); + } + return cycles; +#undef FLD +} + +static int +model_fr550_sethi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_sethi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT out_GRkhi = -1; + INT out_GRklo = -1; + out_GRkhi = FLD (out_GRkhi); + referenced |= 1 << 0; + cycles += frvbf_model_fr550_u_set_hilo (current_cpu, idesc, 0, referenced, out_GRkhi, out_GRklo); + } + return cycles; +#undef FLD +} + +static int +model_fr550_setlos (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_setlos.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + out_GRk = FLD (out_GRk); + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr550_ldsb (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_ldub (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_ldsh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_lduh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_ld (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_ldbf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_ldhf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_ldf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_ldc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_nldsb (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_nldub (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_nldsh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_nlduh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_nld (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_nldbf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_FRintk = FLD (out_FRintk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_nldhf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_FRintk = FLD (out_FRintk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_nldf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_FRintk = FLD (out_FRintk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_ldd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRdoublek = FLD (out_GRdoublek); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 4)) referenced |= 1 << 3; + cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_lddf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_FRdoublek = FLD (out_FRdoublek); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr550_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_lddc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_lddcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_nldd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRdoublek = FLD (out_GRdoublek); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 3; + cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_nlddf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_FRdoublek = FLD (out_FRdoublek); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 3; + cycles += frvbf_model_fr550_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_ldq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_ldqf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_ldqc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_nldq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_nldqf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_ldsbu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_ldubu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_ldshu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_lduhu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_ldu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_nldsbu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 7)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_nldubu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 7)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_nldshu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 7)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_nlduhu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 7)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_nldu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 7)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_ldbfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_ldhfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_ldfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_ldcu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_nldbfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_FRintk = FLD (out_FRintk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_nldhfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_FRintk = FLD (out_FRintk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_nldfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_FRintk = FLD (out_FRintk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_lddu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRdoublek = FLD (out_GRdoublek); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 5)) referenced |= 1 << 3; + cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_nlddu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRdoublek = FLD (out_GRdoublek); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 3; + cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_lddfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_FRdoublek = FLD (out_FRdoublek); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr550_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_lddcu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_lddcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_nlddfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_FRdoublek = FLD (out_FRdoublek); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 3; + cycles += frvbf_model_fr550_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_ldqu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_nldqu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_ldqfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_ldqcu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_nldqfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_ldsbi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_ldshi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_ldi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_ldubi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_lduhi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_ldbfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldbfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_ldhfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldbfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_ldfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldbfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_nldsbi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 5)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_nldubi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 5)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_nldshi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 5)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_nlduhi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 5)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_nldi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 5)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_nldbfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldbfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + out_FRintk = FLD (out_FRintk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 5)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_nldhfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldbfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + out_FRintk = FLD (out_FRintk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 5)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_nldfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldbfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + out_FRintk = FLD (out_FRintk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 5)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_lddi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smuli.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + out_GRdoublek = FLD (out_GRdoublek); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 4)) referenced |= 1 << 3; + cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_lddfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_lddfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + out_FRdoublek = FLD (out_FRdoublek); + referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr550_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_nlddi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smuli.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + out_GRdoublek = FLD (out_GRdoublek); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 5)) referenced |= 1 << 3; + cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_nlddfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_lddfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + out_FRdoublek = FLD (out_FRdoublek); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 5)) referenced |= 1 << 3; + cycles += frvbf_model_fr550_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_ldqi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_ldqfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_nldqfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_stb (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_GRk = FLD (in_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_sth (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_GRk = FLD (in_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_st (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_GRk = FLD (in_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_stbf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FRintk = FLD (in_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_sthf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FRintk = FLD (in_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_stf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FRintk = FLD (in_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_stc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_rstb (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_rsth (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_rst (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_rstbf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_rsthf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_rstf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_std (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_GRdoublek = FLD (in_GRdoublek); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr550_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_stdf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FRdoublek = FLD (in_FRdoublek); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr550_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_stdc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_rstd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_rstdf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_stq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_stqf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_stqc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_rstq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_rstqf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_stbu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_GRk = FLD (in_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_sthu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_GRk = FLD (in_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_stu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_GRk = FLD (in_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_stbfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FRintk = FLD (in_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_sthfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FRintk = FLD (in_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_stfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FRintk = FLD (in_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_stcu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_stdu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_GRdoublek = FLD (in_GRdoublek); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr550_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_stdfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FRdoublek = FLD (in_FRdoublek); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr550_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_stdcu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_stqu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_stqfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_stqcu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cldsb (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 5)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cldub (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 5)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cldsh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 5)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_clduh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 5)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cld (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 5)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cldbf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_FRintk = FLD (out_FRintk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 5)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cldhf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_FRintk = FLD (out_FRintk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 5)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cldf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_FRintk = FLD (out_FRintk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 5)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cldd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRdoublek = FLD (out_GRdoublek); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 3; + cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_clddf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_FRdoublek = FLD (out_FRdoublek); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 5)) referenced |= 1 << 3; + cycles += frvbf_model_fr550_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cldq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cldsbu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 8)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cldubu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 8)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cldshu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 8)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_clduhu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 8)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cldu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 8)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cldbfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_FRintk = FLD (out_FRintk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 5)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cldhfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_FRintk = FLD (out_FRintk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 5)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cldfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_FRintk = FLD (out_FRintk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 5)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_clddu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRdoublek = FLD (out_GRdoublek); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 7)) referenced |= 1 << 3; + cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_clddfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_FRdoublek = FLD (out_FRdoublek); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 5)) referenced |= 1 << 3; + cycles += frvbf_model_fr550_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cldqu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cstb (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_GRk = FLD (in_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 3)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_csth (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_GRk = FLD (in_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 3)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cst (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_GRk = FLD (in_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 3)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cstbf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FRintk = FLD (in_FRintk); + if (insn_referenced & (1 << 2)) referenced |= 1 << 0; + if (insn_referenced & (1 << 3)) referenced |= 1 << 1; + if (insn_referenced & (1 << 1)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_csthf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FRintk = FLD (in_FRintk); + if (insn_referenced & (1 << 2)) referenced |= 1 << 0; + if (insn_referenced & (1 << 3)) referenced |= 1 << 1; + if (insn_referenced & (1 << 1)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cstf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FRintk = FLD (in_FRintk); + if (insn_referenced & (1 << 2)) referenced |= 1 << 0; + if (insn_referenced & (1 << 3)) referenced |= 1 << 1; + if (insn_referenced & (1 << 1)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cstd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_GRdoublek = FLD (in_GRdoublek); + if (insn_referenced & (1 << 2)) referenced |= 1 << 0; + if (insn_referenced & (1 << 3)) referenced |= 1 << 1; + if (insn_referenced & (1 << 1)) referenced |= 1 << 3; + cycles += frvbf_model_fr550_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cstdf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FRdoublek = FLD (in_FRdoublek); + if (insn_referenced & (1 << 2)) referenced |= 1 << 0; + if (insn_referenced & (1 << 3)) referenced |= 1 << 1; + if (insn_referenced & (1 << 1)) referenced |= 1 << 3; + cycles += frvbf_model_fr550_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cstq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cstbu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_GRk = FLD (in_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 3)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_csthu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_GRk = FLD (in_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 3)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cstu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_GRk = FLD (in_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 3)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cstbfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FRintk = FLD (in_FRintk); + if (insn_referenced & (1 << 2)) referenced |= 1 << 0; + if (insn_referenced & (1 << 3)) referenced |= 1 << 1; + if (insn_referenced & (1 << 1)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_csthfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FRintk = FLD (in_FRintk); + if (insn_referenced & (1 << 2)) referenced |= 1 << 0; + if (insn_referenced & (1 << 3)) referenced |= 1 << 1; + if (insn_referenced & (1 << 1)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cstfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FRintk = FLD (in_FRintk); + if (insn_referenced & (1 << 2)) referenced |= 1 << 0; + if (insn_referenced & (1 << 3)) referenced |= 1 << 1; + if (insn_referenced & (1 << 1)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cstdu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_GRdoublek = FLD (in_GRdoublek); + if (insn_referenced & (1 << 2)) referenced |= 1 << 0; + if (insn_referenced & (1 << 3)) referenced |= 1 << 1; + if (insn_referenced & (1 << 1)) referenced |= 1 << 3; + cycles += frvbf_model_fr550_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cstdfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FRdoublek = FLD (in_FRdoublek); + if (insn_referenced & (1 << 2)) referenced |= 1 << 0; + if (insn_referenced & (1 << 3)) referenced |= 1 << 1; + if (insn_referenced & (1 << 1)) referenced |= 1 << 3; + cycles += frvbf_model_fr550_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_stbi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRk = FLD (in_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_sthi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRk = FLD (in_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_sti (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRk = FLD (in_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_stbfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stbfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_FRintk = FLD (in_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_sthfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stbfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_FRintk = FLD (in_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_stfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stbfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_FRintk = FLD (in_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_stdi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRdoublek = FLD (in_GRdoublek); + referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr550_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_stdfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_FRdoublek = FLD (in_FRdoublek); + referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr550_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_stqi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_stqfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_swap (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_swap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_swapi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_swap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cswap (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_swap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_movgf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmovgfd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRj = -1; + INT out_FRintk = -1; + in_GRj = FLD (in_GRj); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr550_u_gr2fr (current_cpu, idesc, 0, referenced, in_GRj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_movfg (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmovfgd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRintk = -1; + INT out_GRj = -1; + in_FRintk = FLD (in_FRintk); + out_GRj = FLD (out_GRj); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr550_u_fr2gr (current_cpu, idesc, 0, referenced, in_FRintk, out_GRj); + } + return cycles; +#undef FLD +} + +static int +model_fr550_movgfd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmovgfd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRj = -1; + INT out_FRintk = -1; + in_GRj = FLD (in_GRj); + out_FRintk = FLD (out_FRintk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 4)) referenced |= 1 << 1; + cycles += frvbf_model_fr550_u_gr2fr (current_cpu, idesc, 0, referenced, in_GRj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_movfgd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmovfgd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRintk = -1; + INT out_GRj = -1; + in_FRintk = FLD (in_FRintk); + out_GRj = FLD (out_GRj); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 4)) referenced |= 1 << 1; + cycles += frvbf_model_fr550_u_fr2gr (current_cpu, idesc, 0, referenced, in_FRintk, out_GRj); + } + return cycles; +#undef FLD +} + +static int +model_fr550_movgfq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_movgfq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_movfgq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_movfgq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cmovgf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmovgfd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRj = -1; + INT out_FRintk = -1; + in_GRj = FLD (in_GRj); + out_FRintk = FLD (out_FRintk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 3)) referenced |= 1 << 1; + cycles += frvbf_model_fr550_u_gr2fr (current_cpu, idesc, 0, referenced, in_GRj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cmovfg (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmovfgd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRintk = -1; + INT out_GRj = -1; + in_FRintk = FLD (in_FRintk); + out_GRj = FLD (out_GRj); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 3)) referenced |= 1 << 1; + cycles += frvbf_model_fr550_u_fr2gr (current_cpu, idesc, 0, referenced, in_FRintk, out_GRj); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cmovgfd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmovgfd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRj = -1; + INT out_FRintk = -1; + in_GRj = FLD (in_GRj); + out_FRintk = FLD (out_FRintk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 6)) referenced |= 1 << 1; + cycles += frvbf_model_fr550_u_gr2fr (current_cpu, idesc, 0, referenced, in_GRj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cmovfgd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmovfgd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRintk = -1; + INT out_GRj = -1; + in_FRintk = FLD (in_FRintk); + out_GRj = FLD (out_GRj); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 6)) referenced |= 1 << 1; + cycles += frvbf_model_fr550_u_fr2gr (current_cpu, idesc, 0, referenced, in_FRintk, out_GRj); + } + return cycles; +#undef FLD +} + +static int +model_fr550_movgs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_movgs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRj = -1; + INT out_spr = -1; + in_GRj = FLD (in_GRj); + out_spr = FLD (out_spr); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr550_u_gr2spr (current_cpu, idesc, 0, referenced, in_GRj, out_spr); + } + return cycles; +#undef FLD +} + +static int +model_fr550_movsg (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_movsg.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_spr = -1; + INT out_GRj = -1; + in_spr = FLD (in_spr); + out_GRj = FLD (out_GRj); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr550_u_spr2gr (current_cpu, idesc, 0, referenced, in_spr, out_GRj); + } + return cycles; +#undef FLD +} + +static int +model_fr550_bra (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_bno (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_beq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_bne (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_ble (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_bgt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_blt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_bge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_bls (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_bhi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_bc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_bnc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_bn (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_bp (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_bv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_bnv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fbra (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fbno (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fbne (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fbeq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fblg (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fbue (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fbul (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fbge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fblt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fbuge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fbug (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fble (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fbgt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fbule (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fbu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fbo (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_bctrlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + if (insn_referenced & (1 << 5)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_bralr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_bnolr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_beqlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_bnelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_blelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_bgtlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_bltlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_bgelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_blslr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_bhilr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_bclr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_bnclr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_bnlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_bplr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_bvlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_bnvlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fbralr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fbnolr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fbeqlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fbnelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fblglr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fbuelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fbullr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fbgelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fbltlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fbugelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fbuglr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fblelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fbgtlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fbulelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fbulr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fbolr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_bcralr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + if (insn_referenced & (1 << 5)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_bcnolr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_bceqlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_bcnelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_bclelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_bcgtlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_bcltlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_bcgelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_bclslr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_bchilr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_bcclr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_bcnclr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_bcnlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_bcplr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_bcvlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_bcnvlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fcbralr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + if (insn_referenced & (1 << 5)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fcbnolr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fcbeqlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fcbnelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fcblglr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fcbuelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fcbullr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fcbgelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fcbltlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fcbugelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fcbuglr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fcblelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fcbgtlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fcbulelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fcbulr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fcbolr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_jmpl (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cjmpl.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_calll (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cjmpl.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_jmpil (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_jmpil.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + referenced |= 1 << 0; + referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_callil (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_jmpil.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_call (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_call.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_rett (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_rett.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_rei (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_tra (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_tno (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_teq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_tne (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_tle (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_tgt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_tlt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_tge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_tls (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_thi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_tc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_tnc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_tn (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_tp (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_tv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_tnv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_ftra (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_ftno (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_ftne (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fteq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_ftlg (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_ftue (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_ftul (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_ftge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_ftlt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_ftuge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_ftug (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_ftle (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_ftgt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_ftule (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_ftu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fto (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_tira (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + referenced |= 1 << 0; + cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_tino (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_tieq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_tine (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_tile (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_tigt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_tilt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_tige (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_tils (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_tihi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_tic (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_tinc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_tin (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_tip (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_tiv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_tinv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_ftira (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + referenced |= 1 << 0; + cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_ftino (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_ftine (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_ftieq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_ftilg (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_ftiue (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_ftiul (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_ftige (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_ftilt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_ftiuge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_ftiug (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_ftile (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_ftigt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_ftiule (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_ftiu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_ftio (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_break (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_break.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_mtrap (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_andcr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_andcr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_orcr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_andcr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_xorcr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_andcr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_nandcr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_andcr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_norcr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_andcr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_andncr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_andcr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_orncr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_andcr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_nandncr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_andcr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_norncr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_andcr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_notcr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_andcr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_ckra (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr550_ckno (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr550_ckeq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + referenced |= 1 << 0; + cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr550_ckne (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + referenced |= 1 << 0; + cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr550_ckle (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + referenced |= 1 << 0; + cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr550_ckgt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + referenced |= 1 << 0; + cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cklt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + referenced |= 1 << 0; + cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr550_ckge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + referenced |= 1 << 0; + cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr550_ckls (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + referenced |= 1 << 0; + cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr550_ckhi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + referenced |= 1 << 0; + cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr550_ckc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + referenced |= 1 << 0; + cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cknc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + referenced |= 1 << 0; + cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr550_ckn (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + referenced |= 1 << 0; + cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr550_ckp (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + referenced |= 1 << 0; + cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr550_ckv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + referenced |= 1 << 0; + cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cknv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + referenced |= 1 << 0; + cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fckra (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fckno (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fckne (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + referenced |= 1 << 1; + cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fckeq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + referenced |= 1 << 1; + cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fcklg (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + referenced |= 1 << 1; + cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fckue (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + referenced |= 1 << 1; + cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fckul (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + referenced |= 1 << 1; + cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fckge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + referenced |= 1 << 1; + cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fcklt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + referenced |= 1 << 1; + cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fckuge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + referenced |= 1 << 1; + cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fckug (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + referenced |= 1 << 1; + cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fckle (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + referenced |= 1 << 1; + cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fckgt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + referenced |= 1 << 1; + cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fckule (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + referenced |= 1 << 1; + cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fcku (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + referenced |= 1 << 1; + cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fcko (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + referenced |= 1 << 1; + cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cckra (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cckno (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cckeq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cckne (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cckle (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cckgt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr550_ccklt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cckge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cckls (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cckhi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cckc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr550_ccknc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cckn (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cckp (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cckv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr550_ccknv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cfckra (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cfckno (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cfckne (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cfckeq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cfcklg (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cfckue (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cfckul (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cfckge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cfcklt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cfckuge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cfckug (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cfckle (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cfckgt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cfckule (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cfcku (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cfcko (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cjmpl (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cjmpl.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_ccalll (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cjmpl.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_ici (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_icpl.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr550_u_ici (current_cpu, idesc, 0, referenced, in_GRi, in_GRj); + } + return cycles; +#undef FLD +} + +static int +model_fr550_dci (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_icpl.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr550_u_dci (current_cpu, idesc, 0, referenced, in_GRi, in_GRj); + } + return cycles; +#undef FLD +} + +static int +model_fr550_icei (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_icei.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + cycles += frvbf_model_fr550_u_ici (current_cpu, idesc, 0, referenced, in_GRi, in_GRj); + } + return cycles; +#undef FLD +} + +static int +model_fr550_dcei (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_icei.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + cycles += frvbf_model_fr550_u_dci (current_cpu, idesc, 0, referenced, in_GRi, in_GRj); + } + return cycles; +#undef FLD +} + +static int +model_fr550_dcf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_icpl.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr550_u_dcf (current_cpu, idesc, 0, referenced, in_GRi, in_GRj); + } + return cycles; +#undef FLD +} + +static int +model_fr550_dcef (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_icei.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + cycles += frvbf_model_fr550_u_dcf (current_cpu, idesc, 0, referenced, in_GRi, in_GRj); + } + return cycles; +#undef FLD +} + +static int +model_fr550_witlb (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_wdtlb (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_itlbi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_dtlbi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_icpl (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_icpl.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr550_u_icpl (current_cpu, idesc, 0, referenced, in_GRi, in_GRj); + } + return cycles; +#undef FLD +} + +static int +model_fr550_dcpl (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_icpl.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr550_u_dcpl (current_cpu, idesc, 0, referenced, in_GRi, in_GRj); + } + return cycles; +#undef FLD +} + +static int +model_fr550_icul (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_jmpil.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + in_GRi = FLD (in_GRi); + referenced |= 1 << 0; + cycles += frvbf_model_fr550_u_icul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj); + } + return cycles; +#undef FLD +} + +static int +model_fr550_dcul (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_jmpil.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + in_GRi = FLD (in_GRi); + referenced |= 1 << 0; + cycles += frvbf_model_fr550_u_dcul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj); + } + return cycles; +#undef FLD +} + +static int +model_fr550_bar (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_membar (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cop1 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cop2 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_clrgr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRk = -1; + in_GRk = FLD (in_GRk); + referenced |= 1 << 0; + cycles += frvbf_model_fr550_u_clrgr (current_cpu, idesc, 0, referenced, in_GRk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_clrfr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRk = -1; + in_FRk = FLD (in_FRk); + referenced |= 1 << 0; + cycles += frvbf_model_fr550_u_clrfr (current_cpu, idesc, 0, referenced, in_FRk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_clrga (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRk = -1; + cycles += frvbf_model_fr550_u_clrgr (current_cpu, idesc, 0, referenced, in_GRk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_clrfa (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRk = -1; + cycles += frvbf_model_fr550_u_clrfr (current_cpu, idesc, 0, referenced, in_FRk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_commitgr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_setlos.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRk = -1; + INT in_FRk = -1; + cycles += frvbf_model_fr550_u_commit (current_cpu, idesc, 0, referenced, in_GRk, in_FRk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_commitfr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mhsethis.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRk = -1; + INT in_FRk = -1; + cycles += frvbf_model_fr550_u_commit (current_cpu, idesc, 0, referenced, in_GRk, in_FRk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_commitga (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRk = -1; + INT in_FRk = -1; + cycles += frvbf_model_fr550_u_commit (current_cpu, idesc, 0, referenced, in_GRk, in_FRk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_commitfa (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRk = -1; + INT in_FRk = -1; + cycles += frvbf_model_fr550_u_commit (current_cpu, idesc, 0, referenced, in_GRk, in_FRk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fitos (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fditos.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRj = -1; + INT in_FRintj = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_FRintj = FLD (in_FRintj); + out_FRk = FLD (out_FRk); + referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr550_u_float_convert (current_cpu, idesc, 0, referenced, in_FRj, in_FRintj, in_FRdoublej, out_FRk, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fstoi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdstoi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRj = -1; + INT in_FRintj = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_FRj = FLD (in_FRj); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_float_convert (current_cpu, idesc, 0, referenced, in_FRj, in_FRintj, in_FRdoublej, out_FRk, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fitod (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fitod.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRj = -1; + INT in_FRintj = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_FRintj = FLD (in_FRintj); + out_FRdoublek = FLD (out_FRdoublek); + referenced |= 1 << 1; + referenced |= 1 << 5; + cycles += frvbf_model_fr550_u_float_convert (current_cpu, idesc, 0, referenced, in_FRj, in_FRintj, in_FRdoublej, out_FRk, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fdtoi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdtoi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRj = -1; + INT in_FRintj = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_FRdoublej = FLD (in_FRdoublej); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 2; + referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_float_convert (current_cpu, idesc, 0, referenced, in_FRj, in_FRintj, in_FRdoublej, out_FRk, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fditos (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fditos.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fdstoi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdstoi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_nfditos (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fditos.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_nfdstoi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdstoi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cfitos (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfitos.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRj = -1; + INT in_FRintj = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_FRintj = FLD (in_FRintj); + out_FRk = FLD (out_FRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 3)) referenced |= 1 << 3; + cycles += frvbf_model_fr550_u_float_convert (current_cpu, idesc, 0, referenced, in_FRj, in_FRintj, in_FRdoublej, out_FRk, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cfstoi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfstoi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRj = -1; + INT in_FRintj = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_FRj = FLD (in_FRj); + out_FRintk = FLD (out_FRintk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_float_convert (current_cpu, idesc, 0, referenced, in_FRj, in_FRintj, in_FRdoublej, out_FRk, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_nfitos (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fditos.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRj = -1; + INT in_FRintj = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_FRintj = FLD (in_FRintj); + out_FRk = FLD (out_FRk); + referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr550_u_float_convert (current_cpu, idesc, 0, referenced, in_FRj, in_FRintj, in_FRdoublej, out_FRk, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_nfstoi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdstoi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRj = -1; + INT in_FRintj = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_FRj = FLD (in_FRj); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_float_convert (current_cpu, idesc, 0, referenced, in_FRj, in_FRintj, in_FRdoublej, out_FRk, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fmovs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fmovd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fmaddd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT out_FRk = -1; + cycles += frvbf_model_fr550_u_fr2fr (current_cpu, idesc, 0, referenced, in_FRi, out_FRk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fdmovs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cfmovs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT out_FRk = -1; + out_FRk = FLD (out_FRk); + if (insn_referenced & (1 << 3)) referenced |= 1 << 1; + cycles += frvbf_model_fr550_u_fr2fr (current_cpu, idesc, 0, referenced, in_FRi, out_FRk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fnegs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT in_FRdoublei = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRdoublek = -1; + in_FRj = FLD (in_FRj); + out_FRk = FLD (out_FRk); + referenced |= 1 << 1; + referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_float_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fnegd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fmaddd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT in_FRdoublei = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRdoublek = -1; + in_FRdoublej = FLD (in_FRdoublej); + out_FRdoublek = FLD (out_FRdoublek); + referenced |= 1 << 3; + referenced |= 1 << 5; + cycles += frvbf_model_fr550_u_float_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fdnegs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cfnegs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT in_FRdoublei = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRdoublek = -1; + in_FRj = FLD (in_FRj); + out_FRk = FLD (out_FRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_float_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fabss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT in_FRdoublei = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRdoublek = -1; + in_FRj = FLD (in_FRj); + out_FRk = FLD (out_FRk); + referenced |= 1 << 1; + referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_float_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fabsd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fmaddd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT in_FRdoublei = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRdoublek = -1; + in_FRdoublej = FLD (in_FRdoublej); + out_FRdoublek = FLD (out_FRdoublek); + referenced |= 1 << 3; + referenced |= 1 << 5; + cycles += frvbf_model_fr550_u_float_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fdabss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cfabss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT in_FRdoublei = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRdoublek = -1; + in_FRj = FLD (in_FRj); + out_FRk = FLD (out_FRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_float_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fsqrts (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRj = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRdoublek = -1; + in_FRj = FLD (in_FRj); + out_FRk = FLD (out_FRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_float_sqrt (current_cpu, idesc, 0, referenced, in_FRj, in_FRdoublej, out_FRk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fdsqrts (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_nfdsqrts (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fsqrtd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fmaddd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cfsqrts (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRj = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRdoublek = -1; + in_FRj = FLD (in_FRj); + out_FRk = FLD (out_FRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 3)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_float_sqrt (current_cpu, idesc, 0, referenced, in_FRj, in_FRdoublej, out_FRk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_nfsqrts (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRj = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRdoublek = -1; + in_FRj = FLD (in_FRj); + out_FRk = FLD (out_FRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_float_sqrt (current_cpu, idesc, 0, referenced, in_FRj, in_FRdoublej, out_FRk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fadds (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT in_FRdoublei = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRdoublek = -1; + in_FRi = FLD (in_FRi); + in_FRj = FLD (in_FRj); + out_FRk = FLD (out_FRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_float_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fsubs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT in_FRdoublei = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRdoublek = -1; + in_FRi = FLD (in_FRi); + in_FRj = FLD (in_FRj); + out_FRk = FLD (out_FRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_float_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fmuls (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT in_FRdoublei = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRdoublek = -1; + in_FRi = FLD (in_FRi); + in_FRj = FLD (in_FRj); + out_FRk = FLD (out_FRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_float_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fdivs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT out_FRk = -1; + in_FRi = FLD (in_FRi); + in_FRj = FLD (in_FRj); + out_FRk = FLD (out_FRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_float_div (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, out_FRk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_faddd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fmaddd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fsubd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fmaddd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fmuld (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fmaddd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fdivd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fmaddd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cfadds (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT in_FRdoublei = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRdoublek = -1; + in_FRi = FLD (in_FRi); + in_FRj = FLD (in_FRj); + out_FRk = FLD (out_FRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 4)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_float_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cfsubs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT in_FRdoublei = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRdoublek = -1; + in_FRi = FLD (in_FRi); + in_FRj = FLD (in_FRj); + out_FRk = FLD (out_FRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 4)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_float_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cfmuls (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT in_FRdoublei = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRdoublek = -1; + in_FRi = FLD (in_FRi); + in_FRj = FLD (in_FRj); + out_FRk = FLD (out_FRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 4)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_float_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cfdivs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT out_FRk = -1; + in_FRi = FLD (in_FRi); + in_FRj = FLD (in_FRj); + out_FRk = FLD (out_FRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 4)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_float_div (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, out_FRk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_nfadds (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT in_FRdoublei = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRdoublek = -1; + in_FRi = FLD (in_FRi); + in_FRj = FLD (in_FRj); + out_FRk = FLD (out_FRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_float_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_nfsubs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT in_FRdoublei = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRdoublek = -1; + in_FRi = FLD (in_FRi); + in_FRj = FLD (in_FRj); + out_FRk = FLD (out_FRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_float_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_nfmuls (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT in_FRdoublei = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRdoublek = -1; + in_FRi = FLD (in_FRi); + in_FRj = FLD (in_FRj); + out_FRk = FLD (out_FRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_float_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_nfdivs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT out_FRk = -1; + in_FRi = FLD (in_FRi); + in_FRj = FLD (in_FRj); + out_FRk = FLD (out_FRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_float_div (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, out_FRk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fcmps (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfcmps.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT in_FRdoublei = -1; + INT in_FRdoublej = -1; + INT out_FCCi_2 = -1; + in_FRi = FLD (in_FRi); + in_FRj = FLD (in_FRj); + out_FCCi_2 = FLD (out_FCCi_2); + referenced |= 1 << 0; + referenced |= 1 << 1; + if (insn_referenced & (1 << 2)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_float_compare (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fcmpd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcmpd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cfcmps (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfcmps.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT in_FRdoublei = -1; + INT in_FRdoublej = -1; + INT out_FCCi_2 = -1; + in_FRi = FLD (in_FRi); + in_FRj = FLD (in_FRj); + out_FCCi_2 = FLD (out_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 4)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_float_compare (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fdcmps (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_nfdcmps.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT out_FCCi_2 = -1; + in_FRi = FLD (in_FRi); + in_FRj = FLD (in_FRj); + out_FCCi_2 = FLD (out_FCCi_2); + referenced |= 1 << 0; + referenced |= 1 << 1; + if (insn_referenced & (1 << 7)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_float_dual_compare (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, out_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fmadds (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fmsubs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fmaddd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fmaddd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fmsubd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fmaddd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fdmadds (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_nfdmadds (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cfmadds (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cfmsubs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_nfmadds (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_nfmsubs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fmas (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT in_FRdoublei = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRdoublek = -1; + in_FRi = FLD (in_FRi); + in_FRj = FLD (in_FRj); + out_FRk = FLD (out_FRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fmss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT in_FRdoublei = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRdoublek = -1; + in_FRi = FLD (in_FRi); + in_FRj = FLD (in_FRj); + out_FRk = FLD (out_FRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fdmas (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmas.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fdmss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmas.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_nfdmas (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmas.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_nfdmss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmas.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cfmas (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmas.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT in_FRdoublei = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRdoublek = -1; + in_FRi = FLD (in_FRi); + in_FRj = FLD (in_FRj); + out_FRk = FLD (out_FRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 9)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cfmss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmas.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT in_FRdoublei = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRdoublek = -1; + in_FRi = FLD (in_FRi); + in_FRj = FLD (in_FRj); + out_FRk = FLD (out_FRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 9)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fmad (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fmsd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_nfmas (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT in_FRdoublei = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRdoublek = -1; + in_FRi = FLD (in_FRi); + in_FRj = FLD (in_FRj); + out_FRk = FLD (out_FRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_nfmss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT in_FRdoublei = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRdoublek = -1; + in_FRi = FLD (in_FRi); + in_FRj = FLD (in_FRj); + out_FRk = FLD (out_FRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fdadds (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT in_FRdoublei = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRdoublek = -1; + in_FRi = FLD (in_FRi); + in_FRj = FLD (in_FRj); + out_FRk = FLD (out_FRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fdsubs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT in_FRdoublei = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRdoublek = -1; + in_FRi = FLD (in_FRi); + in_FRj = FLD (in_FRj); + out_FRk = FLD (out_FRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fdmuls (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT in_FRdoublei = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRdoublek = -1; + in_FRi = FLD (in_FRi); + in_FRj = FLD (in_FRj); + out_FRk = FLD (out_FRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fddivs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT in_FRdoublei = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRdoublek = -1; + in_FRi = FLD (in_FRi); + in_FRj = FLD (in_FRj); + out_FRk = FLD (out_FRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fdsads (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT in_FRdoublei = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRdoublek = -1; + in_FRi = FLD (in_FRi); + in_FRj = FLD (in_FRj); + out_FRk = FLD (out_FRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fdmulcs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT in_FRdoublei = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRdoublek = -1; + in_FRi = FLD (in_FRi); + in_FRj = FLD (in_FRj); + out_FRk = FLD (out_FRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_nfdmulcs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT in_FRdoublei = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRdoublek = -1; + in_FRi = FLD (in_FRi); + in_FRj = FLD (in_FRj); + out_FRk = FLD (out_FRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_nfdadds (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT in_FRdoublei = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRdoublek = -1; + in_FRi = FLD (in_FRi); + in_FRj = FLD (in_FRj); + out_FRk = FLD (out_FRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_nfdsubs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT in_FRdoublei = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRdoublek = -1; + in_FRi = FLD (in_FRi); + in_FRj = FLD (in_FRj); + out_FRk = FLD (out_FRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_nfdmuls (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT in_FRdoublei = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRdoublek = -1; + in_FRi = FLD (in_FRi); + in_FRj = FLD (in_FRj); + out_FRk = FLD (out_FRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_nfddivs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT in_FRdoublei = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRdoublek = -1; + in_FRi = FLD (in_FRi); + in_FRj = FLD (in_FRj); + out_FRk = FLD (out_FRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_nfdsads (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT in_FRdoublei = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRdoublek = -1; + in_FRi = FLD (in_FRi); + in_FRj = FLD (in_FRj); + out_FRk = FLD (out_FRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr550_nfdcmps (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_nfdcmps.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_mhsetlos (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mhsetlos.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT out_FRintk = -1; + out_FRintk = FLD (out_FRklo); + cycles += frvbf_model_fr550_u_media_set (current_cpu, idesc, 0, referenced, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_mhsethis (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mhsethis.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT out_FRintk = -1; + out_FRintk = FLD (out_FRkhi); + cycles += frvbf_model_fr550_u_media_set (current_cpu, idesc, 0, referenced, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_mhdsets (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mhdsets.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT out_FRintk = -1; + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + cycles += frvbf_model_fr550_u_media_set (current_cpu, idesc, 0, referenced, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_mhsetloh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mhsetloh.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT out_FRintk = -1; + out_FRintk = FLD (out_FRklo); + cycles += frvbf_model_fr550_u_media_set (current_cpu, idesc, 0, referenced, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_mhsethih (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mhsethih.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT out_FRintk = -1; + out_FRintk = FLD (out_FRkhi); + cycles += frvbf_model_fr550_u_media_set (current_cpu, idesc, 0, referenced, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_mhdseth (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mhdseth.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT out_FRintk = -1; + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + cycles += frvbf_model_fr550_u_media_set (current_cpu, idesc, 0, referenced, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_mand (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mwcut.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_mor (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mwcut.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_mxor (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mwcut.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cmand (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmand.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_FRintk = FLD (out_FRintk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 4)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cmor (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmand.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_FRintk = FLD (out_FRintk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 4)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cmxor (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmand.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_FRintk = FLD (out_FRintk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 4)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_mnot (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mcut.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRintj = FLD (in_FRintj); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cmnot (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmand.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRintj = FLD (in_FRintj); + out_FRintk = FLD (out_FRintk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 3)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_mrotli (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mwcuti.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_mrotri (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mwcuti.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_mwcut (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mwcut.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_mwcuti (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mwcuti.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_mcut (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mcut.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRintj = -1; + INT in_ACC40Si = -1; + INT out_FRintk = -1; + in_FRintj = FLD (in_FRintj); + in_ACC40Si = FLD (in_ACC40Si); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_media_3_acc (current_cpu, idesc, 0, referenced, in_FRintj, in_ACC40Si, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_mcuti (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mcuti.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRintj = -1; + INT in_ACC40Si = -1; + INT out_FRintk = -1; + in_ACC40Si = FLD (in_ACC40Si); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_media_3_acc (current_cpu, idesc, 0, referenced, in_FRintj, in_ACC40Si, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_mcutss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mcut.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRintj = -1; + INT in_ACC40Si = -1; + INT out_FRintk = -1; + in_FRintj = FLD (in_FRintj); + in_ACC40Si = FLD (in_ACC40Si); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_media_3_acc (current_cpu, idesc, 0, referenced, in_FRintj, in_ACC40Si, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_mcutssi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mcuti.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRintj = -1; + INT in_ACC40Si = -1; + INT out_FRintk = -1; + in_ACC40Si = FLD (in_ACC40Si); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_media_3_acc (current_cpu, idesc, 0, referenced, in_FRintj, in_ACC40Si, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_mdcutssi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdcutssi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ACC40Si = -1; + INT out_FRintkeven = -1; + in_ACC40Si = FLD (in_ACC40Si); + out_FRintkeven = FLD (out_FRintkeven); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 5)) referenced |= 1 << 1; + cycles += frvbf_model_fr550_u_media_3_acc_dual (current_cpu, idesc, 0, referenced, in_ACC40Si, out_FRintkeven); + } + return cycles; +#undef FLD +} + +static int +model_fr550_maveh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mwcut.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_msllhi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_msllhi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_msrlhi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_msllhi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_msrahi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_msllhi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_mdrotli (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdrotli.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRintieven = -1; + INT in_FRintjeven = -1; + INT out_FRintkeven = -1; + in_FRintieven = FLD (in_FRintieven); + out_FRintkeven = FLD (out_FRintkeven); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 5)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_media_quad (current_cpu, idesc, 0, referenced, in_FRintieven, in_FRintjeven, out_FRintkeven); + } + return cycles; +#undef FLD +} + +static int +model_fr550_mcplhi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mcplhi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr550_u_media_3_dual (current_cpu, idesc, 0, referenced, in_FRinti, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_mcpli (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mwcuti.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr550_u_media_3_dual (current_cpu, idesc, 0, referenced, in_FRinti, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_msaths (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr550_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_mqsaths (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRintieven = -1; + INT in_FRintjeven = -1; + INT out_FRintkeven = -1; + in_FRintieven = FLD (in_FRintieven); + in_FRintjeven = FLD (in_FRintjeven); + out_FRintkeven = FLD (out_FRintkeven); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 14)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_media_quad (current_cpu, idesc, 0, referenced, in_FRintieven, in_FRintjeven, out_FRintkeven); + } + return cycles; +#undef FLD +} + +static int +model_fr550_msathu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr550_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_mcmpsh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mcmpsh.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + cycles += frvbf_model_fr550_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_mcmpuh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mcmpsh.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + cycles += frvbf_model_fr550_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_mabshs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mabshs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRintj = FLD (in_FRintj); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_maddhss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr550_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_maddhus (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr550_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_msubhss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr550_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_msubhus (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr550_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cmaddhss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + cycles += frvbf_model_fr550_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cmaddhus (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + cycles += frvbf_model_fr550_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cmsubhss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + cycles += frvbf_model_fr550_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cmsubhus (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + cycles += frvbf_model_fr550_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_mqaddhss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRintieven = -1; + INT in_FRintjeven = -1; + INT out_FRintkeven = -1; + in_FRintieven = FLD (in_FRintieven); + in_FRintjeven = FLD (in_FRintjeven); + out_FRintkeven = FLD (out_FRintkeven); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 14)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_media_quad (current_cpu, idesc, 0, referenced, in_FRintieven, in_FRintjeven, out_FRintkeven); + } + return cycles; +#undef FLD +} + +static int +model_fr550_mqaddhus (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRintieven = -1; + INT in_FRintjeven = -1; + INT out_FRintkeven = -1; + in_FRintieven = FLD (in_FRintieven); + in_FRintjeven = FLD (in_FRintjeven); + out_FRintkeven = FLD (out_FRintkeven); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 14)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_media_quad (current_cpu, idesc, 0, referenced, in_FRintieven, in_FRintjeven, out_FRintkeven); + } + return cycles; +#undef FLD +} + +static int +model_fr550_mqsubhss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRintieven = -1; + INT in_FRintjeven = -1; + INT out_FRintkeven = -1; + in_FRintieven = FLD (in_FRintieven); + in_FRintjeven = FLD (in_FRintjeven); + out_FRintkeven = FLD (out_FRintkeven); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 14)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_media_quad (current_cpu, idesc, 0, referenced, in_FRintieven, in_FRintjeven, out_FRintkeven); + } + return cycles; +#undef FLD +} + +static int +model_fr550_mqsubhus (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRintieven = -1; + INT in_FRintjeven = -1; + INT out_FRintkeven = -1; + in_FRintieven = FLD (in_FRintieven); + in_FRintjeven = FLD (in_FRintjeven); + out_FRintkeven = FLD (out_FRintkeven); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 14)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_media_quad (current_cpu, idesc, 0, referenced, in_FRintieven, in_FRintjeven, out_FRintkeven); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cmqaddhss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRintieven = -1; + INT in_FRintjeven = -1; + INT out_FRintkeven = -1; + in_FRintieven = FLD (in_FRintieven); + in_FRintjeven = FLD (in_FRintjeven); + out_FRintkeven = FLD (out_FRintkeven); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 16)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_media_quad (current_cpu, idesc, 0, referenced, in_FRintieven, in_FRintjeven, out_FRintkeven); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cmqaddhus (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRintieven = -1; + INT in_FRintjeven = -1; + INT out_FRintkeven = -1; + in_FRintieven = FLD (in_FRintieven); + in_FRintjeven = FLD (in_FRintjeven); + out_FRintkeven = FLD (out_FRintkeven); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 16)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_media_quad (current_cpu, idesc, 0, referenced, in_FRintieven, in_FRintjeven, out_FRintkeven); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cmqsubhss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRintieven = -1; + INT in_FRintjeven = -1; + INT out_FRintkeven = -1; + in_FRintieven = FLD (in_FRintieven); + in_FRintjeven = FLD (in_FRintjeven); + out_FRintkeven = FLD (out_FRintkeven); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 16)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_media_quad (current_cpu, idesc, 0, referenced, in_FRintieven, in_FRintjeven, out_FRintkeven); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cmqsubhus (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRintieven = -1; + INT in_FRintjeven = -1; + INT out_FRintkeven = -1; + in_FRintieven = FLD (in_FRintieven); + in_FRintjeven = FLD (in_FRintjeven); + out_FRintkeven = FLD (out_FRintkeven); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 16)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_media_quad (current_cpu, idesc, 0, referenced, in_FRintieven, in_FRintjeven, out_FRintkeven); + } + return cycles; +#undef FLD +} + +static int +model_fr550_maddaccs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdasaccs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ACC40Si = -1; + INT out_ACC40Sk = -1; + in_ACC40Si = FLD (in_ACC40Si); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 4)) referenced |= 1 << 1; + cycles += frvbf_model_fr550_u_media_4_acc (current_cpu, idesc, 0, referenced, in_ACC40Si, out_ACC40Sk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_msubaccs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdasaccs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ACC40Si = -1; + INT out_ACC40Sk = -1; + in_ACC40Si = FLD (in_ACC40Si); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 4)) referenced |= 1 << 1; + cycles += frvbf_model_fr550_u_media_4_acc (current_cpu, idesc, 0, referenced, in_ACC40Si, out_ACC40Sk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_mdaddaccs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdasaccs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ACC40Si = -1; + INT out_ACC40Sk = -1; + in_ACC40Si = FLD (in_ACC40Si); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 6)) referenced |= 1 << 1; + cycles += frvbf_model_fr550_u_media_4_acc_dual (current_cpu, idesc, 0, referenced, in_ACC40Si, out_ACC40Sk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_mdsubaccs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdasaccs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ACC40Si = -1; + INT out_ACC40Sk = -1; + in_ACC40Si = FLD (in_ACC40Si); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 6)) referenced |= 1 << 1; + cycles += frvbf_model_fr550_u_media_4_acc_dual (current_cpu, idesc, 0, referenced, in_ACC40Si, out_ACC40Sk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_masaccs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdasaccs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ACC40Si = -1; + INT out_ACC40Sk = -1; + in_ACC40Si = FLD (in_ACC40Si); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 4)) referenced |= 1 << 1; + cycles += frvbf_model_fr550_u_media_4_add_sub (current_cpu, idesc, 0, referenced, in_ACC40Si, out_ACC40Sk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_mdasaccs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdasaccs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ACC40Si = -1; + INT out_ACC40Sk = -1; + in_ACC40Si = FLD (in_ACC40Si); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 6)) referenced |= 1 << 1; + cycles += frvbf_model_fr550_u_media_4_add_sub_dual (current_cpu, idesc, 0, referenced, in_ACC40Si, out_ACC40Sk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_mmulhs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 9)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_media_4 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_mmulhu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 9)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_media_4 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_mmulxhs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 9)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_media_4 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_mmulxhu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 9)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_media_4 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cmmulhs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 11)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_media_4 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cmmulhu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 11)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_media_4 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_mqmulhs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRintieven = -1; + INT in_FRintjeven = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRintieven = FLD (in_FRintieven); + in_FRintjeven = FLD (in_FRintjeven); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 13)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_media_4_quad (current_cpu, idesc, 0, referenced, in_FRintieven, in_FRintjeven, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_mqmulhu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRintieven = -1; + INT in_FRintjeven = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRintieven = FLD (in_FRintieven); + in_FRintjeven = FLD (in_FRintjeven); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 13)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_media_4_quad (current_cpu, idesc, 0, referenced, in_FRintieven, in_FRintjeven, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_mqmulxhs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRintieven = -1; + INT in_FRintjeven = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRintieven = FLD (in_FRintieven); + in_FRintjeven = FLD (in_FRintjeven); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 13)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_media_4_quad (current_cpu, idesc, 0, referenced, in_FRintieven, in_FRintjeven, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_mqmulxhu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRintieven = -1; + INT in_FRintjeven = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRintieven = FLD (in_FRintieven); + in_FRintjeven = FLD (in_FRintjeven); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 13)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_media_4_quad (current_cpu, idesc, 0, referenced, in_FRintieven, in_FRintjeven, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cmqmulhs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRintieven = -1; + INT in_FRintjeven = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRintieven = FLD (in_FRintieven); + in_FRintjeven = FLD (in_FRintjeven); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 15)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_media_4_quad (current_cpu, idesc, 0, referenced, in_FRintieven, in_FRintjeven, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cmqmulhu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRintieven = -1; + INT in_FRintjeven = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRintieven = FLD (in_FRintieven); + in_FRintjeven = FLD (in_FRintjeven); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 15)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_media_4_quad (current_cpu, idesc, 0, referenced, in_FRintieven, in_FRintjeven, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_mmachs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 11)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_media_4 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_mmachu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Uk = FLD (out_ACC40Uk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 11)) referenced |= 1 << 3; + cycles += frvbf_model_fr550_u_media_4 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_mmrdhs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 11)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_media_4 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_mmrdhu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Uk = FLD (out_ACC40Uk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 11)) referenced |= 1 << 3; + cycles += frvbf_model_fr550_u_media_4 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cmmachs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 2)) referenced |= 1 << 0; + if (insn_referenced & (1 << 3)) referenced |= 1 << 1; + if (insn_referenced & (1 << 13)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_media_4 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cmmachu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Uk = FLD (out_ACC40Uk); + if (insn_referenced & (1 << 2)) referenced |= 1 << 0; + if (insn_referenced & (1 << 3)) referenced |= 1 << 1; + if (insn_referenced & (1 << 13)) referenced |= 1 << 3; + cycles += frvbf_model_fr550_u_media_4 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_mqmachs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRintieven = -1; + INT in_FRintjeven = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRintieven = FLD (in_FRintieven); + in_FRintjeven = FLD (in_FRintjeven); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 17)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_media_4_quad (current_cpu, idesc, 0, referenced, in_FRintieven, in_FRintjeven, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_mqmachu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRintieven = -1; + INT in_FRintjeven = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRintieven = FLD (in_FRintieven); + in_FRintjeven = FLD (in_FRintjeven); + out_ACC40Uk = FLD (out_ACC40Uk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 17)) referenced |= 1 << 3; + cycles += frvbf_model_fr550_u_media_4_quad (current_cpu, idesc, 0, referenced, in_FRintieven, in_FRintjeven, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cmqmachs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRintieven = -1; + INT in_FRintjeven = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRintieven = FLD (in_FRintieven); + in_FRintjeven = FLD (in_FRintjeven); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 2)) referenced |= 1 << 0; + if (insn_referenced & (1 << 3)) referenced |= 1 << 1; + if (insn_referenced & (1 << 19)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_media_4_quad (current_cpu, idesc, 0, referenced, in_FRintieven, in_FRintjeven, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cmqmachu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRintieven = -1; + INT in_FRintjeven = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRintieven = FLD (in_FRintieven); + in_FRintjeven = FLD (in_FRintjeven); + out_ACC40Uk = FLD (out_ACC40Uk); + if (insn_referenced & (1 << 2)) referenced |= 1 << 0; + if (insn_referenced & (1 << 3)) referenced |= 1 << 1; + if (insn_referenced & (1 << 19)) referenced |= 1 << 3; + cycles += frvbf_model_fr550_u_media_4_quad (current_cpu, idesc, 0, referenced, in_FRintieven, in_FRintjeven, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_mqxmachs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRintieven = -1; + INT in_FRintjeven = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRintieven = FLD (in_FRintieven); + in_FRintjeven = FLD (in_FRintjeven); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 17)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_media_4_quad (current_cpu, idesc, 0, referenced, in_FRintieven, in_FRintjeven, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_mqxmacxhs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRintieven = -1; + INT in_FRintjeven = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRintieven = FLD (in_FRintieven); + in_FRintjeven = FLD (in_FRintjeven); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 17)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_media_4_quad (current_cpu, idesc, 0, referenced, in_FRintieven, in_FRintjeven, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_mqmacxhs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRintieven = -1; + INT in_FRintjeven = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRintieven = FLD (in_FRintieven); + in_FRintjeven = FLD (in_FRintjeven); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 17)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_media_4_quad (current_cpu, idesc, 0, referenced, in_FRintieven, in_FRintjeven, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_mcpxrs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 9)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_media_4 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_mcpxru (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 9)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_media_4 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_mcpxis (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 9)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_media_4 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_mcpxiu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 9)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_media_4 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cmcpxrs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 11)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_media_4 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cmcpxru (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 11)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_media_4 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cmcpxis (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 11)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_media_4 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cmcpxiu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 11)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_media_4 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_mqcpxrs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRintieven = -1; + INT in_FRintjeven = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRintieven = FLD (in_FRintieven); + in_FRintjeven = FLD (in_FRintjeven); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 13)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_media_4_quad (current_cpu, idesc, 0, referenced, in_FRintieven, in_FRintjeven, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_mqcpxru (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRintieven = -1; + INT in_FRintjeven = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRintieven = FLD (in_FRintieven); + in_FRintjeven = FLD (in_FRintjeven); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 13)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_media_4_quad (current_cpu, idesc, 0, referenced, in_FRintieven, in_FRintjeven, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_mqcpxis (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRintieven = -1; + INT in_FRintjeven = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRintieven = FLD (in_FRintieven); + in_FRintjeven = FLD (in_FRintjeven); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 13)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_media_4_quad (current_cpu, idesc, 0, referenced, in_FRintieven, in_FRintjeven, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_mqcpxiu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRintieven = -1; + INT in_FRintjeven = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRintieven = FLD (in_FRintieven); + in_FRintjeven = FLD (in_FRintjeven); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 13)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_media_4_quad (current_cpu, idesc, 0, referenced, in_FRintieven, in_FRintjeven, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_mexpdhw (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmexpdhw.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + cycles += frvbf_model_fr550_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cmexpdhw (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmexpdhw.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + cycles += frvbf_model_fr550_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_mexpdhd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmexpdhd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT out_FRintkeven = -1; + out_FRintkeven = FLD (out_FRintkeven); + if (insn_referenced & (1 << 6)) referenced |= 1 << 1; + cycles += frvbf_model_fr550_u_media_dual_expand (current_cpu, idesc, 0, referenced, in_FRinti, out_FRintkeven); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cmexpdhd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmexpdhd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT out_FRintkeven = -1; + out_FRintkeven = FLD (out_FRintkeven); + if (insn_referenced & (1 << 8)) referenced |= 1 << 1; + cycles += frvbf_model_fr550_u_media_dual_expand (current_cpu, idesc, 0, referenced, in_FRinti, out_FRintkeven); + } + return cycles; +#undef FLD +} + +static int +model_fr550_mpackh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + cycles += frvbf_model_fr550_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_mdpackh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdpackh.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRintieven = -1; + INT in_FRintjeven = -1; + INT out_FRintkeven = -1; + in_FRintieven = FLD (in_FRintieven); + in_FRintjeven = FLD (in_FRintjeven); + out_FRintkeven = FLD (out_FRintkeven); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 12)) referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_media_quad (current_cpu, idesc, 0, referenced, in_FRintieven, in_FRintjeven, out_FRintkeven); + } + return cycles; +#undef FLD +} + +static int +model_fr550_munpackh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_munpackh.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT out_FRintkeven = -1; + in_FRinti = FLD (in_FRinti); + out_FRintkeven = FLD (out_FRintkeven); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 7)) referenced |= 1 << 1; + cycles += frvbf_model_fr550_u_media_dual_expand (current_cpu, idesc, 0, referenced, in_FRinti, out_FRintkeven); + } + return cycles; +#undef FLD +} + +static int +model_fr550_mdunpackh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdunpackh.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_mbtoh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmbtoh.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT out_FRintkeven = -1; + out_FRintkeven = FLD (out_FRintkeven); + referenced |= 1 << 1; + cycles += frvbf_model_fr550_u_media_dual_expand (current_cpu, idesc, 0, referenced, in_FRinti, out_FRintkeven); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cmbtoh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmbtoh.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT out_FRintkeven = -1; + out_FRintkeven = FLD (out_FRintkeven); + in_FRinti = FLD (in_FRintj); + referenced |= 1 << 1; + cycles += frvbf_model_fr550_u_media_dual_expand (current_cpu, idesc, 0, referenced, in_FRinti, out_FRintkeven); + } + return cycles; +#undef FLD +} + +static int +model_fr550_mhtob (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmhtob.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT out_FRintk = -1; + out_FRintk = FLD (out_FRintk); + in_FRinti = FLD (in_FRintjeven); + referenced |= 1 << 1; + cycles += frvbf_model_fr550_u_media_3_dual (current_cpu, idesc, 0, referenced, in_FRinti, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cmhtob (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmhtob.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT out_FRintk = -1; + out_FRintk = FLD (out_FRintk); + in_FRinti = FLD (in_FRintjeven); + referenced |= 1 << 1; + cycles += frvbf_model_fr550_u_media_3_dual (current_cpu, idesc, 0, referenced, in_FRinti, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_mbtohe (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmbtohe.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_cmbtohe (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmbtohe.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_mnop (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_mclracc_0 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdasaccs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_media_3_mclracc (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_mclracc_1 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdasaccs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_media_3_mclracc (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_mrdacc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mcuti.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRintj = -1; + INT in_ACC40Si = -1; + INT out_FRintk = -1; + in_ACC40Si = FLD (in_ACC40Si); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_media_3_acc (current_cpu, idesc, 0, referenced, in_FRintj, in_ACC40Si, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_mrdaccg (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mrdaccg.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRintj = -1; + INT in_ACC40Si = -1; + INT out_FRintk = -1; + out_FRintk = FLD (out_FRintk); + in_ACC40Si = FLD (in_ACCGi); + referenced |= 1 << 2; + cycles += frvbf_model_fr550_u_media_3_acc (current_cpu, idesc, 0, referenced, in_FRintj, in_ACC40Si, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_mwtacc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_ACC40Sk = -1; + in_FRinti = FLD (in_FRinti); + in_ACC40Sk = FLD (in_ACC40Sk); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr550_u_media_3_wtacc (current_cpu, idesc, 0, referenced, in_FRinti, in_ACC40Sk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_mwtaccg (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mwtaccg.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_ACC40Sk = -1; + in_FRinti = FLD (in_FRinti); + in_ACC40Sk = FLD (in_ACCGk); + referenced |= 1 << 0; + cycles += frvbf_model_fr550_u_media_3_wtacc (current_cpu, idesc, 0, referenced, in_FRinti, in_ACC40Sk); + } + return cycles; +#undef FLD +} + +static int +model_fr550_mcop1 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_mcop2 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_fnop (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr500_add (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr500_sub (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr500_and (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr500_or (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr500_xor (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr500_not (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_scutss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr500_sdiv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr500_nsdiv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr500_udiv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr500_nudiv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr500_smul (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRdoublek = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRdoublek = FLD (out_GRdoublek); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_imul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRdoublek, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr500_umul (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRdoublek = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRdoublek = FLD (out_GRdoublek); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_imul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRdoublek, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr500_smu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smass.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr500_smass (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smass.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr500_smsss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smass.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr500_sll (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr500_srl (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr500_sra (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr500_slass (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr500_scutss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_scutss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr500_scan (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cadd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 4)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr500_csub (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 4)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cand (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 4)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cor (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 4)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cxor (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 4)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cnot (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 3)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr500_csmul (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRdoublek = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRdoublek = FLD (out_GRdoublek); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 4)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_imul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRdoublek, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr500_csdiv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 5)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cudiv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 5)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr500_csll (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 4)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr500_csrl (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 4)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr500_csra (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 4)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cscan (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 4)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr500_addcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + referenced |= 1 << 3; + cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr500_subcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + referenced |= 1 << 3; + cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr500_andcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + if (insn_referenced & (1 << 4)) referenced |= 1 << 3; + cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr500_orcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + if (insn_referenced & (1 << 4)) referenced |= 1 << 3; + cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr500_xorcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + if (insn_referenced & (1 << 4)) referenced |= 1 << 3; + cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr500_sllcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + referenced |= 1 << 3; + cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr500_srlcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + referenced |= 1 << 3; + cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr500_sracc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + referenced |= 1 << 3; + cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr500_smulcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRdoublek = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRdoublek = FLD (out_GRdoublek); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + referenced |= 1 << 3; + cycles += frvbf_model_fr500_u_imul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRdoublek, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr500_umulcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRdoublek = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRdoublek = FLD (out_GRdoublek); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + referenced |= 1 << 3; + cycles += frvbf_model_fr500_u_imul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRdoublek, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr500_caddcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_caddcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr500_csubcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_caddcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr500_csmulcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_csmulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRdoublek = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRdoublek = FLD (out_GRdoublek); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_imul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRdoublek, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr500_candcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_caddcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr500_corcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_caddcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cxorcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_caddcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr500_csllcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_caddcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr500_csrlcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_caddcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr500_csracc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_caddcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr500_addx (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr500_subx (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr500_addxcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + referenced |= 1 << 3; + cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr500_subxcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + referenced |= 1 << 3; + cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr500_addss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr500_subss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr500_addi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr500_subi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr500_andi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr500_ori (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr500_xori (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr500_sdivi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr500_nsdivi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr500_udivi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr500_nudivi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr500_smuli (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smuli.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRdoublek = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRdoublek = FLD (out_GRdoublek); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_imul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRdoublek, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr500_umuli (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smuli.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRdoublek = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRdoublek = FLD (out_GRdoublek); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_imul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRdoublek, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr500_slli (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr500_srli (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr500_srai (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr500_scani (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr500_addicc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 2; + referenced |= 1 << 3; + cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr500_subicc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 2; + referenced |= 1 << 3; + cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr500_andicc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 2; + if (insn_referenced & (1 << 4)) referenced |= 1 << 3; + cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr500_oricc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 2; + if (insn_referenced & (1 << 4)) referenced |= 1 << 3; + cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr500_xoricc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 2; + if (insn_referenced & (1 << 4)) referenced |= 1 << 3; + cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr500_smulicc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRdoublek = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRdoublek = FLD (out_GRdoublek); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 2; + referenced |= 1 << 3; + cycles += frvbf_model_fr500_u_imul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRdoublek, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr500_umulicc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRdoublek = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRdoublek = FLD (out_GRdoublek); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 2; + referenced |= 1 << 3; + cycles += frvbf_model_fr500_u_imul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRdoublek, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr500_sllicc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 2; + referenced |= 1 << 3; + cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr500_srlicc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 2; + referenced |= 1 << 3; + cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr500_sraicc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 2; + referenced |= 1 << 3; + cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr500_addxi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr500_subxi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr500_addxicc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 2; + referenced |= 1 << 3; + cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr500_subxicc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 2; + referenced |= 1 << 3; + cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cmpb (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cmpba (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr500_setlo (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_setlo.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT out_GRkhi = -1; + INT out_GRklo = -1; + out_GRklo = FLD (out_GRklo); + referenced |= 1 << 1; + cycles += frvbf_model_fr500_u_set_hilo (current_cpu, idesc, 0, referenced, out_GRkhi, out_GRklo); + } + return cycles; +#undef FLD +} + +static int +model_fr500_sethi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_sethi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT out_GRkhi = -1; + INT out_GRklo = -1; + out_GRkhi = FLD (out_GRkhi); + referenced |= 1 << 0; + cycles += frvbf_model_fr500_u_set_hilo (current_cpu, idesc, 0, referenced, out_GRkhi, out_GRklo); + } + return cycles; +#undef FLD +} + +static int +model_fr500_setlos (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_setlos.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + out_GRk = FLD (out_GRk); + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr500_ldsb (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_ldub (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_ldsh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_lduh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_ld (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_ldbf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_ldhf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_ldf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_ldc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr500_nldsb (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_nldub (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_nldsh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_nlduh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_nld (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_nldbf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_FRintk = FLD (out_FRintk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_nldhf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_FRintk = FLD (out_FRintk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_nldf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_FRintk = FLD (out_FRintk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_ldd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRdoublek = FLD (out_GRdoublek); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 4)) referenced |= 1 << 3; + cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_lddf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_FRdoublek = FLD (out_FRdoublek); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr500_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_lddc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_lddcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr500_nldd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRdoublek = FLD (out_GRdoublek); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 3; + cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_nlddf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_FRdoublek = FLD (out_FRdoublek); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 3; + cycles += frvbf_model_fr500_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_ldq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_ldqf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr500_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_ldqc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr500_nldq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_nldqf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + cycles += frvbf_model_fr500_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_ldsbu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_ldubu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_ldshu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_lduhu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_ldu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_nldsbu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 7)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_nldubu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 7)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_nldshu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 7)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_nlduhu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 7)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_nldu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 7)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_ldbfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_ldhfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_ldfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_ldcu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr500_nldbfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_FRintk = FLD (out_FRintk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_nldhfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_FRintk = FLD (out_FRintk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_nldfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_FRintk = FLD (out_FRintk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_lddu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRdoublek = FLD (out_GRdoublek); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 5)) referenced |= 1 << 3; + cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_nlddu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRdoublek = FLD (out_GRdoublek); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 3; + cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_lddfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_FRdoublek = FLD (out_FRdoublek); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr500_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_lddcu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_lddcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr500_nlddfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_FRdoublek = FLD (out_FRdoublek); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 3; + cycles += frvbf_model_fr500_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_ldqu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_nldqu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_ldqfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr500_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_ldqcu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr500_nldqfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + cycles += frvbf_model_fr500_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_ldsbi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_ldshi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_ldi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_ldubi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_lduhi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_ldbfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldbfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_ldhfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldbfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_ldfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldbfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_nldsbi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 5)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_nldubi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 5)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_nldshi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 5)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_nlduhi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 5)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_nldi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 5)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_nldbfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldbfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + out_FRintk = FLD (out_FRintk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 5)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_nldhfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldbfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + out_FRintk = FLD (out_FRintk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 5)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_nldfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldbfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + out_FRintk = FLD (out_FRintk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 5)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_lddi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smuli.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + out_GRdoublek = FLD (out_GRdoublek); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 4)) referenced |= 1 << 3; + cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_lddfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_lddfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + out_FRdoublek = FLD (out_FRdoublek); + referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr500_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_nlddi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smuli.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + out_GRdoublek = FLD (out_GRdoublek); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 5)) referenced |= 1 << 3; + cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_nlddfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_lddfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + out_FRdoublek = FLD (out_FRdoublek); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 5)) referenced |= 1 << 3; + cycles += frvbf_model_fr500_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_ldqi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + referenced |= 1 << 0; + cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_ldqfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + referenced |= 1 << 0; + cycles += frvbf_model_fr500_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_nldqfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + cycles += frvbf_model_fr500_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_stb (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_GRk = FLD (in_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_sth (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_GRk = FLD (in_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_st (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_GRk = FLD (in_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_stbf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FRintk = FLD (in_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_sthf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FRintk = FLD (in_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_stf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FRintk = FLD (in_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_stc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr500_rstb (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_GRk = FLD (in_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_gr_r_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_rsth (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_GRk = FLD (in_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_gr_r_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_rst (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_GRk = FLD (in_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_gr_r_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_rstbf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FRintk = FLD (in_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_fr_r_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_rsthf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FRintk = FLD (in_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_fr_r_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_rstf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FRintk = FLD (in_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_fr_r_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_std (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_GRdoublek = FLD (in_GRdoublek); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr500_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_stdf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FRdoublek = FLD (in_FRdoublek); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr500_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_stdc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr500_rstd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_GRdoublek = FLD (in_GRdoublek); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr500_u_gr_r_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_rstdf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FRdoublek = FLD (in_FRdoublek); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr500_u_fr_r_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_stq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr500_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_stqf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr500_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_stqc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr500_rstq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr500_u_gr_r_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_rstqf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr500_u_fr_r_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_stbu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_GRk = FLD (in_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_sthu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_GRk = FLD (in_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_stu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_GRk = FLD (in_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_stbfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FRintk = FLD (in_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_sthfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FRintk = FLD (in_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_stfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FRintk = FLD (in_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_stcu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr500_stdu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_GRdoublek = FLD (in_GRdoublek); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr500_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_stdfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FRdoublek = FLD (in_FRdoublek); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr500_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_stdcu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr500_stqu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr500_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_stqfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr500_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_stqcu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cldsb (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 5)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cldub (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 5)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cldsh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 5)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_clduh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 5)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cld (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 5)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cldbf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_FRintk = FLD (out_FRintk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 5)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cldhf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_FRintk = FLD (out_FRintk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 5)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cldf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_FRintk = FLD (out_FRintk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 5)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cldd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRdoublek = FLD (out_GRdoublek); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 3; + cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_clddf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cldq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cldsbu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 8)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cldubu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 8)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cldshu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 8)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_clduhu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 8)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cldu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 8)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cldbfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_FRintk = FLD (out_FRintk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 5)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cldhfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_FRintk = FLD (out_FRintk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 5)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cldfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_FRintk = FLD (out_FRintk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 5)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_clddu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRdoublek = FLD (out_GRdoublek); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 7)) referenced |= 1 << 3; + cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_clddfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_FRdoublek = FLD (out_FRdoublek); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 5)) referenced |= 1 << 3; + cycles += frvbf_model_fr500_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cldqu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cstb (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_GRk = FLD (in_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 3)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_csth (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_GRk = FLD (in_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 3)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cst (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_GRk = FLD (in_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 3)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cstbf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FRintk = FLD (in_FRintk); + if (insn_referenced & (1 << 2)) referenced |= 1 << 0; + if (insn_referenced & (1 << 3)) referenced |= 1 << 1; + if (insn_referenced & (1 << 1)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_csthf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FRintk = FLD (in_FRintk); + if (insn_referenced & (1 << 2)) referenced |= 1 << 0; + if (insn_referenced & (1 << 3)) referenced |= 1 << 1; + if (insn_referenced & (1 << 1)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cstf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FRintk = FLD (in_FRintk); + if (insn_referenced & (1 << 2)) referenced |= 1 << 0; + if (insn_referenced & (1 << 3)) referenced |= 1 << 1; + if (insn_referenced & (1 << 1)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cstd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_GRdoublek = FLD (in_GRdoublek); + if (insn_referenced & (1 << 2)) referenced |= 1 << 0; + if (insn_referenced & (1 << 3)) referenced |= 1 << 1; + if (insn_referenced & (1 << 1)) referenced |= 1 << 3; + cycles += frvbf_model_fr500_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cstdf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FRdoublek = FLD (in_FRdoublek); + if (insn_referenced & (1 << 2)) referenced |= 1 << 0; + if (insn_referenced & (1 << 3)) referenced |= 1 << 1; + if (insn_referenced & (1 << 1)) referenced |= 1 << 3; + cycles += frvbf_model_fr500_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cstq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + cycles += frvbf_model_fr500_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cstbu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_GRk = FLD (in_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 3)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_csthu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_GRk = FLD (in_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 3)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cstu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_GRk = FLD (in_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 3)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cstbfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FRintk = FLD (in_FRintk); + if (insn_referenced & (1 << 2)) referenced |= 1 << 0; + if (insn_referenced & (1 << 3)) referenced |= 1 << 1; + if (insn_referenced & (1 << 1)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_csthfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FRintk = FLD (in_FRintk); + if (insn_referenced & (1 << 2)) referenced |= 1 << 0; + if (insn_referenced & (1 << 3)) referenced |= 1 << 1; + if (insn_referenced & (1 << 1)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cstfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FRintk = FLD (in_FRintk); + if (insn_referenced & (1 << 2)) referenced |= 1 << 0; + if (insn_referenced & (1 << 3)) referenced |= 1 << 1; + if (insn_referenced & (1 << 1)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cstdu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_GRdoublek = FLD (in_GRdoublek); + if (insn_referenced & (1 << 2)) referenced |= 1 << 0; + if (insn_referenced & (1 << 3)) referenced |= 1 << 1; + if (insn_referenced & (1 << 1)) referenced |= 1 << 3; + cycles += frvbf_model_fr500_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cstdfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FRdoublek = FLD (in_FRdoublek); + if (insn_referenced & (1 << 2)) referenced |= 1 << 0; + if (insn_referenced & (1 << 3)) referenced |= 1 << 1; + if (insn_referenced & (1 << 1)) referenced |= 1 << 3; + cycles += frvbf_model_fr500_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_stbi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRk = FLD (in_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_sthi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRk = FLD (in_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_sti (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRk = FLD (in_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_stbfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stbfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_FRintk = FLD (in_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_sthfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stbfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_FRintk = FLD (in_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_stfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stbfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_FRintk = FLD (in_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_stdi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRdoublek = FLD (in_GRdoublek); + referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr500_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_stdfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_FRdoublek = FLD (in_FRdoublek); + referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr500_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_stqi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + referenced |= 1 << 0; + cycles += frvbf_model_fr500_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_stqfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr500_swap (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_swap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_swapi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_swap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cswap (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_swap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_movgf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmovgfd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRj = -1; + INT out_FRintk = -1; + in_GRj = FLD (in_GRj); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr500_u_gr2fr (current_cpu, idesc, 0, referenced, in_GRj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_movfg (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmovfgd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRintk = -1; + INT out_GRj = -1; + in_FRintk = FLD (in_FRintk); + out_GRj = FLD (out_GRj); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr500_u_fr2gr (current_cpu, idesc, 0, referenced, in_FRintk, out_GRj); + } + return cycles; +#undef FLD +} + +static int +model_fr500_movgfd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmovgfd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRj = -1; + INT out_FRintk = -1; + in_GRj = FLD (in_GRj); + out_FRintk = FLD (out_FRintk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 4)) referenced |= 1 << 1; + cycles += frvbf_model_fr500_u_gr2fr (current_cpu, idesc, 0, referenced, in_GRj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_movfgd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmovfgd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRintk = -1; + INT out_GRj = -1; + in_FRintk = FLD (in_FRintk); + out_GRj = FLD (out_GRj); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 4)) referenced |= 1 << 1; + cycles += frvbf_model_fr500_u_fr2gr (current_cpu, idesc, 0, referenced, in_FRintk, out_GRj); + } + return cycles; +#undef FLD +} + +static int +model_fr500_movgfq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_movgfq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr500_movfgq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_movfgq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cmovgf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmovgfd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRj = -1; + INT out_FRintk = -1; + in_GRj = FLD (in_GRj); + out_FRintk = FLD (out_FRintk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 3)) referenced |= 1 << 1; + cycles += frvbf_model_fr500_u_gr2fr (current_cpu, idesc, 0, referenced, in_GRj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cmovfg (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmovfgd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRintk = -1; + INT out_GRj = -1; + in_FRintk = FLD (in_FRintk); + out_GRj = FLD (out_GRj); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 3)) referenced |= 1 << 1; + cycles += frvbf_model_fr500_u_fr2gr (current_cpu, idesc, 0, referenced, in_FRintk, out_GRj); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cmovgfd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmovgfd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRj = -1; + INT out_FRintk = -1; + in_GRj = FLD (in_GRj); + out_FRintk = FLD (out_FRintk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 6)) referenced |= 1 << 1; + cycles += frvbf_model_fr500_u_gr2fr (current_cpu, idesc, 0, referenced, in_GRj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cmovfgd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmovfgd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRintk = -1; + INT out_GRj = -1; + in_FRintk = FLD (in_FRintk); + out_GRj = FLD (out_GRj); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 6)) referenced |= 1 << 1; + cycles += frvbf_model_fr500_u_fr2gr (current_cpu, idesc, 0, referenced, in_FRintk, out_GRj); + } + return cycles; +#undef FLD +} + +static int +model_fr500_movgs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_movgs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRj = -1; + INT out_spr = -1; + in_GRj = FLD (in_GRj); + out_spr = FLD (out_spr); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr500_u_gr2spr (current_cpu, idesc, 0, referenced, in_GRj, out_spr); + } + return cycles; +#undef FLD +} + +static int +model_fr500_movsg (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_movsg.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_spr = -1; + INT out_GRj = -1; + in_spr = FLD (in_spr); + out_GRj = FLD (out_GRj); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr500_u_spr2gr (current_cpu, idesc, 0, referenced, in_spr, out_GRj); + } + return cycles; +#undef FLD +} + +static int +model_fr500_bra (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_bno (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_beq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_bne (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_ble (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_bgt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_blt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_bge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_bls (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_bhi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_bc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_bnc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_bn (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_bp (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_bv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_bnv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fbra (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fbno (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fbne (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fbeq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fblg (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fbue (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fbul (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fbge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fblt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fbuge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fbug (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fble (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fbgt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fbule (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fbu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fbo (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_bctrlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + if (insn_referenced & (1 << 5)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_bralr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_bnolr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_beqlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_bnelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_blelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_bgtlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_bltlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_bgelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_blslr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_bhilr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_bclr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_bnclr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_bnlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_bplr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_bvlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_bnvlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fbralr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fbnolr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fbeqlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fbnelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fblglr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fbuelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fbullr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fbgelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fbltlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fbugelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fbuglr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fblelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fbgtlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fbulelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fbulr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fbolr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_bcralr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + if (insn_referenced & (1 << 5)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_bcnolr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_bceqlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_bcnelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_bclelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_bcgtlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_bcltlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_bcgelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_bclslr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_bchilr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_bcclr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_bcnclr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_bcnlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_bcplr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_bcvlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_bcnvlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fcbralr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + if (insn_referenced & (1 << 5)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fcbnolr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fcbeqlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fcbnelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fcblglr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fcbuelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fcbullr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fcbgelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fcbltlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fcbugelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fcbuglr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fcblelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fcbgtlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fcbulelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fcbulr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fcbolr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_jmpl (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cjmpl.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_calll (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cjmpl.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_jmpil (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_jmpil.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + referenced |= 1 << 0; + referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_callil (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_jmpil.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + referenced |= 1 << 0; + referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_call (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_call.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_rett (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_rett.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr500_rei (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr500_tra (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_tno (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_teq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_tne (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_tle (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_tgt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_tlt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_tge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_tls (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_thi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_tc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_tnc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_tn (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_tp (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_tv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_tnv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_ftra (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_ftno (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_ftne (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fteq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_ftlg (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_ftue (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_ftul (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_ftge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_ftlt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_ftuge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_ftug (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_ftle (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_ftgt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_ftule (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_ftu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fto (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_tira (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + referenced |= 1 << 0; + cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_tino (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_tieq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_tine (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_tile (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_tigt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_tilt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_tige (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_tils (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_tihi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_tic (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_tinc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_tin (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_tip (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_tiv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_tinv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_ftira (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + referenced |= 1 << 0; + cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_ftino (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_ftine (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_ftieq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_ftilg (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_ftiue (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_ftiul (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_ftige (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_ftilt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_ftiuge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_ftiug (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_ftile (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_ftigt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_ftiule (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_ftiu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_ftio (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_break (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_break.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr500_mtrap (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr500_andcr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_andcr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr500_orcr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_andcr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr500_xorcr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_andcr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr500_nandcr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_andcr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr500_norcr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_andcr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr500_andncr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_andcr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr500_orncr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_andcr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr500_nandncr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_andcr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr500_norncr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_andcr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr500_notcr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_andcr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr500_ckra (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr500_ckno (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr500_ckeq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + referenced |= 1 << 0; + cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr500_ckne (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + referenced |= 1 << 0; + cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr500_ckle (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + referenced |= 1 << 0; + cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr500_ckgt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + referenced |= 1 << 0; + cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cklt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + referenced |= 1 << 0; + cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr500_ckge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + referenced |= 1 << 0; + cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr500_ckls (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + referenced |= 1 << 0; + cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr500_ckhi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + referenced |= 1 << 0; + cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr500_ckc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + referenced |= 1 << 0; + cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cknc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + referenced |= 1 << 0; + cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr500_ckn (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + referenced |= 1 << 0; + cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr500_ckp (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + referenced |= 1 << 0; + cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr500_ckv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + referenced |= 1 << 0; + cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cknv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + referenced |= 1 << 0; + cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fckra (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fckno (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fckne (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + referenced |= 1 << 1; + cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fckeq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + referenced |= 1 << 1; + cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fcklg (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + referenced |= 1 << 1; + cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fckue (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + referenced |= 1 << 1; + cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fckul (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + referenced |= 1 << 1; + cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fckge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + referenced |= 1 << 1; + cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fcklt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + referenced |= 1 << 1; + cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fckuge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + referenced |= 1 << 1; + cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fckug (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + referenced |= 1 << 1; + cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fckle (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + referenced |= 1 << 1; + cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fckgt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + referenced |= 1 << 1; + cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fckule (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + referenced |= 1 << 1; + cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fcku (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + referenced |= 1 << 1; + cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fcko (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + referenced |= 1 << 1; + cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cckra (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cckno (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cckeq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cckne (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cckle (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cckgt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr500_ccklt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cckge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cckls (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cckhi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cckc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr500_ccknc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cckn (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cckp (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cckv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr500_ccknv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cfckra (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cfckno (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cfckne (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cfckeq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cfcklg (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cfckue (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cfckul (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cfckge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cfcklt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cfckuge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cfckug (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cfckle (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cfckgt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cfckule (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cfcku (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cfcko (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cjmpl (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cjmpl.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_ccalll (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cjmpl.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_ici (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_icpl.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr500_u_ici (current_cpu, idesc, 0, referenced, in_GRi, in_GRj); + } + return cycles; +#undef FLD +} + +static int +model_fr500_dci (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_icpl.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr500_u_dci (current_cpu, idesc, 0, referenced, in_GRi, in_GRj); + } + return cycles; +#undef FLD +} + +static int +model_fr500_icei (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_icei.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr500_dcei (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_icei.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr500_dcf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_icpl.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr500_u_dcf (current_cpu, idesc, 0, referenced, in_GRi, in_GRj); + } + return cycles; +#undef FLD +} + +static int +model_fr500_dcef (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_icei.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr500_witlb (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr500_wdtlb (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr500_itlbi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr500_dtlbi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr500_icpl (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_icpl.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr500_u_icpl (current_cpu, idesc, 0, referenced, in_GRi, in_GRj); + } + return cycles; +#undef FLD +} + +static int +model_fr500_dcpl (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_icpl.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr500_u_dcpl (current_cpu, idesc, 0, referenced, in_GRi, in_GRj); + } + return cycles; +#undef FLD +} + +static int +model_fr500_icul (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_jmpil.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + in_GRi = FLD (in_GRi); + referenced |= 1 << 0; + cycles += frvbf_model_fr500_u_icul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj); + } + return cycles; +#undef FLD +} + +static int +model_fr500_dcul (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_jmpil.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + in_GRi = FLD (in_GRi); + referenced |= 1 << 0; + cycles += frvbf_model_fr500_u_dcul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj); + } + return cycles; +#undef FLD +} + +static int +model_fr500_bar (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr500_u_barrier (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr500_membar (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr500_u_membar (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cop1 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cop2 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr500_clrgr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRk = -1; + in_GRk = FLD (in_GRk); + referenced |= 1 << 0; + cycles += frvbf_model_fr500_u_clrgr (current_cpu, idesc, 0, referenced, in_GRk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_clrfr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRk = -1; + in_FRk = FLD (in_FRk); + referenced |= 1 << 0; + cycles += frvbf_model_fr500_u_clrfr (current_cpu, idesc, 0, referenced, in_FRk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_clrga (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRk = -1; + cycles += frvbf_model_fr500_u_clrgr (current_cpu, idesc, 0, referenced, in_GRk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_clrfa (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRk = -1; + cycles += frvbf_model_fr500_u_clrfr (current_cpu, idesc, 0, referenced, in_FRk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_commitgr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_setlos.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRk = -1; + INT in_FRk = -1; + cycles += frvbf_model_fr500_u_commit (current_cpu, idesc, 0, referenced, in_GRk, in_FRk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_commitfr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mhsethis.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRk = -1; + INT in_FRk = -1; + cycles += frvbf_model_fr500_u_commit (current_cpu, idesc, 0, referenced, in_GRk, in_FRk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_commitga (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRk = -1; + INT in_FRk = -1; + cycles += frvbf_model_fr500_u_commit (current_cpu, idesc, 0, referenced, in_GRk, in_FRk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_commitfa (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRk = -1; + INT in_FRk = -1; + cycles += frvbf_model_fr500_u_commit (current_cpu, idesc, 0, referenced, in_GRk, in_FRk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fitos (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fditos.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRj = -1; + INT in_FRintj = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_FRintj = FLD (in_FRintj); + out_FRk = FLD (out_FRk); + referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr500_u_float_convert (current_cpu, idesc, 0, referenced, in_FRj, in_FRintj, in_FRdoublej, out_FRk, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fstoi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdstoi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRj = -1; + INT in_FRintj = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_FRj = FLD (in_FRj); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_float_convert (current_cpu, idesc, 0, referenced, in_FRj, in_FRintj, in_FRdoublej, out_FRk, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fitod (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fitod.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRj = -1; + INT in_FRintj = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_FRintj = FLD (in_FRintj); + out_FRdoublek = FLD (out_FRdoublek); + referenced |= 1 << 1; + referenced |= 1 << 5; + cycles += frvbf_model_fr500_u_float_convert (current_cpu, idesc, 0, referenced, in_FRj, in_FRintj, in_FRdoublej, out_FRk, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fdtoi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdtoi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRj = -1; + INT in_FRintj = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_FRdoublej = FLD (in_FRdoublej); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 2; + referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_float_convert (current_cpu, idesc, 0, referenced, in_FRj, in_FRintj, in_FRdoublej, out_FRk, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fditos (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fditos.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRj = -1; + INT in_FRintj = -1; + INT out_FRk = -1; + INT out_FRintk = -1; + in_FRintj = FLD (in_FRintj); + out_FRk = FLD (out_FRk); + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_float_dual_convert (current_cpu, idesc, 0, referenced, in_FRj, in_FRintj, out_FRk, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fdstoi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdstoi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRj = -1; + INT in_FRintj = -1; + INT out_FRk = -1; + INT out_FRintk = -1; + in_FRj = FLD (in_FRj); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr500_u_float_dual_convert (current_cpu, idesc, 0, referenced, in_FRj, in_FRintj, out_FRk, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_nfditos (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fditos.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRj = -1; + INT in_FRintj = -1; + INT out_FRk = -1; + INT out_FRintk = -1; + in_FRintj = FLD (in_FRintj); + out_FRk = FLD (out_FRk); + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_float_dual_convert (current_cpu, idesc, 0, referenced, in_FRj, in_FRintj, out_FRk, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_nfdstoi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdstoi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRj = -1; + INT in_FRintj = -1; + INT out_FRk = -1; + INT out_FRintk = -1; + in_FRj = FLD (in_FRj); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr500_u_float_dual_convert (current_cpu, idesc, 0, referenced, in_FRj, in_FRintj, out_FRk, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cfitos (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfitos.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRj = -1; + INT in_FRintj = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_FRintj = FLD (in_FRintj); + out_FRk = FLD (out_FRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 3)) referenced |= 1 << 3; + cycles += frvbf_model_fr500_u_float_convert (current_cpu, idesc, 0, referenced, in_FRj, in_FRintj, in_FRdoublej, out_FRk, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cfstoi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfstoi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRj = -1; + INT in_FRintj = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_FRj = FLD (in_FRj); + out_FRintk = FLD (out_FRintk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_float_convert (current_cpu, idesc, 0, referenced, in_FRj, in_FRintj, in_FRdoublej, out_FRk, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_nfitos (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fditos.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRj = -1; + INT in_FRintj = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_FRintj = FLD (in_FRintj); + out_FRk = FLD (out_FRk); + referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr500_u_float_convert (current_cpu, idesc, 0, referenced, in_FRj, in_FRintj, in_FRdoublej, out_FRk, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_nfstoi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdstoi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRj = -1; + INT in_FRintj = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_FRj = FLD (in_FRj); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_float_convert (current_cpu, idesc, 0, referenced, in_FRj, in_FRintj, in_FRdoublej, out_FRk, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fmovs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT out_FRk = -1; + out_FRk = FLD (out_FRk); + referenced |= 1 << 1; + cycles += frvbf_model_fr500_u_fr2fr (current_cpu, idesc, 0, referenced, in_FRi, out_FRk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fmovd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fmaddd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT out_FRk = -1; + cycles += frvbf_model_fr500_u_fr2fr (current_cpu, idesc, 0, referenced, in_FRi, out_FRk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fdmovs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT out_FRk = -1; + out_FRk = FLD (out_FRk); + referenced |= 1 << 1; + cycles += frvbf_model_fr500_u_fr2fr (current_cpu, idesc, 0, referenced, in_FRi, out_FRk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cfmovs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT out_FRk = -1; + out_FRk = FLD (out_FRk); + if (insn_referenced & (1 << 3)) referenced |= 1 << 1; + cycles += frvbf_model_fr500_u_fr2fr (current_cpu, idesc, 0, referenced, in_FRi, out_FRk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fnegs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT in_FRdoublei = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRdoublek = -1; + in_FRj = FLD (in_FRj); + out_FRk = FLD (out_FRk); + referenced |= 1 << 1; + referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_float_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fnegd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fmaddd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT in_FRdoublei = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRdoublek = -1; + in_FRdoublej = FLD (in_FRdoublej); + out_FRdoublek = FLD (out_FRdoublek); + referenced |= 1 << 3; + referenced |= 1 << 5; + cycles += frvbf_model_fr500_u_float_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fdnegs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT in_FRdoublei = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRdoublek = -1; + in_FRj = FLD (in_FRj); + out_FRk = FLD (out_FRk); + referenced |= 1 << 1; + referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cfnegs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT in_FRdoublei = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRdoublek = -1; + in_FRj = FLD (in_FRj); + out_FRk = FLD (out_FRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_float_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fabss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT in_FRdoublei = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRdoublek = -1; + in_FRj = FLD (in_FRj); + out_FRk = FLD (out_FRk); + referenced |= 1 << 1; + referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_float_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fabsd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fmaddd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT in_FRdoublei = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRdoublek = -1; + in_FRdoublej = FLD (in_FRdoublej); + out_FRdoublek = FLD (out_FRdoublek); + referenced |= 1 << 3; + referenced |= 1 << 5; + cycles += frvbf_model_fr500_u_float_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fdabss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT in_FRdoublei = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRdoublek = -1; + in_FRj = FLD (in_FRj); + out_FRk = FLD (out_FRk); + referenced |= 1 << 1; + referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cfabss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT in_FRdoublei = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRdoublek = -1; + in_FRj = FLD (in_FRj); + out_FRk = FLD (out_FRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_float_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fsqrts (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRj = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRdoublek = -1; + in_FRj = FLD (in_FRj); + out_FRk = FLD (out_FRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_float_sqrt (current_cpu, idesc, 0, referenced, in_FRj, in_FRdoublej, out_FRk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fdsqrts (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRj = -1; + INT out_FRk = -1; + in_FRj = FLD (in_FRj); + out_FRk = FLD (out_FRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr500_u_float_dual_sqrt (current_cpu, idesc, 0, referenced, in_FRj, out_FRk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_nfdsqrts (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRj = -1; + INT out_FRk = -1; + in_FRj = FLD (in_FRj); + out_FRk = FLD (out_FRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr500_u_float_dual_sqrt (current_cpu, idesc, 0, referenced, in_FRj, out_FRk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fsqrtd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fmaddd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRj = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRdoublek = -1; + in_FRdoublej = FLD (in_FRdoublej); + out_FRdoublek = FLD (out_FRdoublek); + referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr500_u_float_sqrt (current_cpu, idesc, 0, referenced, in_FRj, in_FRdoublej, out_FRk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cfsqrts (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRj = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRdoublek = -1; + in_FRj = FLD (in_FRj); + out_FRk = FLD (out_FRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 3)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_float_sqrt (current_cpu, idesc, 0, referenced, in_FRj, in_FRdoublej, out_FRk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_nfsqrts (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRj = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRdoublek = -1; + in_FRj = FLD (in_FRj); + out_FRk = FLD (out_FRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_float_sqrt (current_cpu, idesc, 0, referenced, in_FRj, in_FRdoublej, out_FRk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fadds (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT in_FRdoublei = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRdoublek = -1; + in_FRi = FLD (in_FRi); + in_FRj = FLD (in_FRj); + out_FRk = FLD (out_FRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_float_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fsubs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT in_FRdoublei = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRdoublek = -1; + in_FRi = FLD (in_FRi); + in_FRj = FLD (in_FRj); + out_FRk = FLD (out_FRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_float_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fmuls (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT in_FRdoublei = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRdoublek = -1; + in_FRi = FLD (in_FRi); + in_FRj = FLD (in_FRj); + out_FRk = FLD (out_FRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_float_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fdivs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT out_FRk = -1; + in_FRi = FLD (in_FRi); + in_FRj = FLD (in_FRj); + out_FRk = FLD (out_FRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_float_div (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, out_FRk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_faddd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fmaddd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT in_FRdoublei = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRdoublek = -1; + in_FRdoublei = FLD (in_FRdoublei); + in_FRdoublej = FLD (in_FRdoublej); + out_FRdoublek = FLD (out_FRdoublek); + referenced |= 1 << 2; + referenced |= 1 << 3; + referenced |= 1 << 5; + cycles += frvbf_model_fr500_u_float_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fsubd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fmaddd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT in_FRdoublei = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRdoublek = -1; + in_FRdoublei = FLD (in_FRdoublei); + in_FRdoublej = FLD (in_FRdoublej); + out_FRdoublek = FLD (out_FRdoublek); + referenced |= 1 << 2; + referenced |= 1 << 3; + referenced |= 1 << 5; + cycles += frvbf_model_fr500_u_float_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fmuld (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fmaddd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT in_FRdoublei = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRdoublek = -1; + in_FRdoublei = FLD (in_FRdoublei); + in_FRdoublej = FLD (in_FRdoublej); + out_FRdoublek = FLD (out_FRdoublek); + referenced |= 1 << 2; + referenced |= 1 << 3; + referenced |= 1 << 5; + cycles += frvbf_model_fr500_u_float_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fdivd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fmaddd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT in_FRdoublei = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRdoublek = -1; + in_FRdoublei = FLD (in_FRdoublei); + in_FRdoublej = FLD (in_FRdoublej); + out_FRdoublek = FLD (out_FRdoublek); + referenced |= 1 << 2; + referenced |= 1 << 3; + referenced |= 1 << 5; + cycles += frvbf_model_fr500_u_float_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cfadds (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT in_FRdoublei = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRdoublek = -1; + in_FRi = FLD (in_FRi); + in_FRj = FLD (in_FRj); + out_FRk = FLD (out_FRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 4)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_float_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cfsubs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT in_FRdoublei = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRdoublek = -1; + in_FRi = FLD (in_FRi); + in_FRj = FLD (in_FRj); + out_FRk = FLD (out_FRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 4)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_float_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cfmuls (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT in_FRdoublei = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRdoublek = -1; + in_FRi = FLD (in_FRi); + in_FRj = FLD (in_FRj); + out_FRk = FLD (out_FRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 4)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_float_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cfdivs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT out_FRk = -1; + in_FRi = FLD (in_FRi); + in_FRj = FLD (in_FRj); + out_FRk = FLD (out_FRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 4)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_float_div (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, out_FRk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_nfadds (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT in_FRdoublei = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRdoublek = -1; + in_FRi = FLD (in_FRi); + in_FRj = FLD (in_FRj); + out_FRk = FLD (out_FRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_float_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_nfsubs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT in_FRdoublei = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRdoublek = -1; + in_FRi = FLD (in_FRi); + in_FRj = FLD (in_FRj); + out_FRk = FLD (out_FRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_float_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_nfmuls (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT in_FRdoublei = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRdoublek = -1; + in_FRi = FLD (in_FRi); + in_FRj = FLD (in_FRj); + out_FRk = FLD (out_FRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_float_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_nfdivs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT out_FRk = -1; + in_FRi = FLD (in_FRi); + in_FRj = FLD (in_FRj); + out_FRk = FLD (out_FRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_float_div (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, out_FRk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fcmps (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfcmps.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT in_FRdoublei = -1; + INT in_FRdoublej = -1; + INT out_FCCi_2 = -1; + in_FRi = FLD (in_FRi); + in_FRj = FLD (in_FRj); + out_FCCi_2 = FLD (out_FCCi_2); + referenced |= 1 << 0; + referenced |= 1 << 1; + if (insn_referenced & (1 << 2)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_float_compare (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fcmpd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcmpd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT in_FRdoublei = -1; + INT in_FRdoublej = -1; + INT out_FCCi_2 = -1; + in_FRdoublei = FLD (in_FRdoublei); + in_FRdoublej = FLD (in_FRdoublej); + out_FCCi_2 = FLD (out_FCCi_2); + referenced |= 1 << 2; + referenced |= 1 << 3; + if (insn_referenced & (1 << 2)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_float_compare (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cfcmps (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfcmps.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT in_FRdoublei = -1; + INT in_FRdoublej = -1; + INT out_FCCi_2 = -1; + in_FRi = FLD (in_FRi); + in_FRj = FLD (in_FRj); + out_FCCi_2 = FLD (out_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 4)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_float_compare (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fdcmps (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_nfdcmps.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT out_FCCi_2 = -1; + in_FRi = FLD (in_FRi); + in_FRj = FLD (in_FRj); + out_FCCi_2 = FLD (out_FCCi_2); + referenced |= 1 << 0; + referenced |= 1 << 1; + if (insn_referenced & (1 << 7)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_float_dual_compare (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, out_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fmadds (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT in_FRdoublei = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRdoublek = -1; + in_FRi = FLD (in_FRi); + in_FRj = FLD (in_FRj); + out_FRk = FLD (out_FRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fmsubs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT in_FRdoublei = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRdoublek = -1; + in_FRi = FLD (in_FRi); + in_FRj = FLD (in_FRj); + out_FRk = FLD (out_FRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fmaddd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fmaddd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT in_FRdoublei = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRdoublek = -1; + in_FRdoublei = FLD (in_FRdoublei); + in_FRdoublej = FLD (in_FRdoublej); + out_FRdoublek = FLD (out_FRdoublek); + referenced |= 1 << 2; + referenced |= 1 << 3; + referenced |= 1 << 5; + cycles += frvbf_model_fr500_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fmsubd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fmaddd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT in_FRdoublei = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRdoublek = -1; + in_FRdoublei = FLD (in_FRdoublei); + in_FRdoublej = FLD (in_FRdoublej); + out_FRdoublek = FLD (out_FRdoublek); + referenced |= 1 << 2; + referenced |= 1 << 3; + referenced |= 1 << 5; + cycles += frvbf_model_fr500_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fdmadds (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT in_FRdoublei = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRdoublek = -1; + in_FRi = FLD (in_FRi); + in_FRj = FLD (in_FRj); + out_FRk = FLD (out_FRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_nfdmadds (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT in_FRdoublei = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRdoublek = -1; + in_FRi = FLD (in_FRi); + in_FRj = FLD (in_FRj); + out_FRk = FLD (out_FRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cfmadds (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT in_FRdoublei = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRdoublek = -1; + in_FRi = FLD (in_FRi); + in_FRj = FLD (in_FRj); + out_FRk = FLD (out_FRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 5)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cfmsubs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT in_FRdoublei = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRdoublek = -1; + in_FRi = FLD (in_FRi); + in_FRj = FLD (in_FRj); + out_FRk = FLD (out_FRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 5)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_nfmadds (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT in_FRdoublei = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRdoublek = -1; + in_FRi = FLD (in_FRi); + in_FRj = FLD (in_FRj); + out_FRk = FLD (out_FRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_nfmsubs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT in_FRdoublei = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRdoublek = -1; + in_FRi = FLD (in_FRi); + in_FRj = FLD (in_FRj); + out_FRk = FLD (out_FRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fmas (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT in_FRdoublei = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRdoublek = -1; + in_FRi = FLD (in_FRi); + in_FRj = FLD (in_FRj); + out_FRk = FLD (out_FRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fmss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT in_FRdoublei = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRdoublek = -1; + in_FRi = FLD (in_FRi); + in_FRj = FLD (in_FRj); + out_FRk = FLD (out_FRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fdmas (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmas.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fdmss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmas.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr500_nfdmas (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmas.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr500_nfdmss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmas.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cfmas (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmas.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT in_FRdoublei = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRdoublek = -1; + in_FRi = FLD (in_FRi); + in_FRj = FLD (in_FRj); + out_FRk = FLD (out_FRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 9)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cfmss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmas.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT in_FRdoublei = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRdoublek = -1; + in_FRi = FLD (in_FRi); + in_FRj = FLD (in_FRj); + out_FRk = FLD (out_FRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 9)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fmad (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fmsd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr500_nfmas (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT in_FRdoublei = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRdoublek = -1; + in_FRi = FLD (in_FRi); + in_FRj = FLD (in_FRj); + out_FRk = FLD (out_FRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_nfmss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT in_FRdoublei = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRdoublek = -1; + in_FRi = FLD (in_FRi); + in_FRj = FLD (in_FRj); + out_FRk = FLD (out_FRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fdadds (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT in_FRdoublei = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRdoublek = -1; + in_FRi = FLD (in_FRi); + in_FRj = FLD (in_FRj); + out_FRk = FLD (out_FRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fdsubs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT in_FRdoublei = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRdoublek = -1; + in_FRi = FLD (in_FRi); + in_FRj = FLD (in_FRj); + out_FRk = FLD (out_FRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fdmuls (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT in_FRdoublei = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRdoublek = -1; + in_FRi = FLD (in_FRi); + in_FRj = FLD (in_FRj); + out_FRk = FLD (out_FRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fddivs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT in_FRdoublei = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRdoublek = -1; + in_FRi = FLD (in_FRi); + in_FRj = FLD (in_FRj); + out_FRk = FLD (out_FRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fdsads (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT in_FRdoublei = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRdoublek = -1; + in_FRi = FLD (in_FRi); + in_FRj = FLD (in_FRj); + out_FRk = FLD (out_FRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fdmulcs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT in_FRdoublei = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRdoublek = -1; + in_FRi = FLD (in_FRi); + in_FRj = FLD (in_FRj); + out_FRk = FLD (out_FRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_nfdmulcs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT in_FRdoublei = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRdoublek = -1; + in_FRi = FLD (in_FRi); + in_FRj = FLD (in_FRj); + out_FRk = FLD (out_FRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_nfdadds (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT in_FRdoublei = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRdoublek = -1; + in_FRi = FLD (in_FRi); + in_FRj = FLD (in_FRj); + out_FRk = FLD (out_FRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_nfdsubs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT in_FRdoublei = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRdoublek = -1; + in_FRi = FLD (in_FRi); + in_FRj = FLD (in_FRj); + out_FRk = FLD (out_FRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_nfdmuls (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT in_FRdoublei = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRdoublek = -1; + in_FRi = FLD (in_FRi); + in_FRj = FLD (in_FRj); + out_FRk = FLD (out_FRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_nfddivs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT in_FRdoublei = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRdoublek = -1; + in_FRi = FLD (in_FRi); + in_FRj = FLD (in_FRj); + out_FRk = FLD (out_FRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_nfdsads (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT in_FRdoublei = -1; + INT in_FRdoublej = -1; + INT out_FRk = -1; + INT out_FRdoublek = -1; + in_FRi = FLD (in_FRi); + in_FRj = FLD (in_FRj); + out_FRk = FLD (out_FRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr500_nfdcmps (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_nfdcmps.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRi = -1; + INT in_FRj = -1; + INT out_FCCi_2 = -1; + in_FRi = FLD (in_FRi); + in_FRj = FLD (in_FRj); + out_FCCi_2 = FLD (out_FCCi_2); + referenced |= 1 << 0; + referenced |= 1 << 1; + if (insn_referenced & (1 << 8)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_float_dual_compare (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, out_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr500_mhsetlos (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mhsetlos.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr500_mhsethis (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mhsethis.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr500_mhdsets (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mhdsets.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr500_mhsetloh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mhsetloh.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr500_mhsethih (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mhsethih.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr500_mhdseth (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mhdseth.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr500_mand (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mwcut.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT in_ACC40Si = -1; + INT in_ACCGi = -1; + INT out_FRintk = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + INT out_ACCGk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, in_ACC40Si, in_ACCGi, out_FRintk, out_ACC40Sk, out_ACC40Uk, out_ACCGk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_mor (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mwcut.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT in_ACC40Si = -1; + INT in_ACCGi = -1; + INT out_FRintk = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + INT out_ACCGk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, in_ACC40Si, in_ACCGi, out_FRintk, out_ACC40Sk, out_ACC40Uk, out_ACCGk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_mxor (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mwcut.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT in_ACC40Si = -1; + INT in_ACCGi = -1; + INT out_FRintk = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + INT out_ACCGk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, in_ACC40Si, in_ACCGi, out_FRintk, out_ACC40Sk, out_ACC40Uk, out_ACCGk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cmand (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmand.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT in_ACC40Si = -1; + INT in_ACCGi = -1; + INT out_FRintk = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + INT out_ACCGk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_FRintk = FLD (out_FRintk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 4)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, in_ACC40Si, in_ACCGi, out_FRintk, out_ACC40Sk, out_ACC40Uk, out_ACCGk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cmor (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmand.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT in_ACC40Si = -1; + INT in_ACCGi = -1; + INT out_FRintk = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + INT out_ACCGk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_FRintk = FLD (out_FRintk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 4)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, in_ACC40Si, in_ACCGi, out_FRintk, out_ACC40Sk, out_ACC40Uk, out_ACCGk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cmxor (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmand.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT in_ACC40Si = -1; + INT in_ACCGi = -1; + INT out_FRintk = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + INT out_ACCGk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_FRintk = FLD (out_FRintk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 4)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, in_ACC40Si, in_ACCGi, out_FRintk, out_ACC40Sk, out_ACC40Uk, out_ACCGk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_mnot (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mcut.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT in_ACC40Si = -1; + INT in_ACCGi = -1; + INT out_FRintk = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + INT out_ACCGk = -1; + in_FRintj = FLD (in_FRintj); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 1; + referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, in_ACC40Si, in_ACCGi, out_FRintk, out_ACC40Sk, out_ACC40Uk, out_ACCGk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cmnot (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmand.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT in_ACC40Si = -1; + INT in_ACCGi = -1; + INT out_FRintk = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + INT out_ACCGk = -1; + in_FRintj = FLD (in_FRintj); + out_FRintk = FLD (out_FRintk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, in_ACC40Si, in_ACCGi, out_FRintk, out_ACC40Sk, out_ACC40Uk, out_ACCGk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_mrotli (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mwcuti.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT in_ACC40Si = -1; + INT in_ACCGi = -1; + INT out_FRintk = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + INT out_ACCGk = -1; + in_FRinti = FLD (in_FRinti); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, in_ACC40Si, in_ACCGi, out_FRintk, out_ACC40Sk, out_ACC40Uk, out_ACCGk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_mrotri (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mwcuti.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT in_ACC40Si = -1; + INT in_ACCGi = -1; + INT out_FRintk = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + INT out_ACCGk = -1; + in_FRinti = FLD (in_FRinti); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, in_ACC40Si, in_ACCGi, out_FRintk, out_ACC40Sk, out_ACC40Uk, out_ACCGk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_mwcut (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mwcut.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT in_ACC40Si = -1; + INT in_ACCGi = -1; + INT out_FRintk = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + INT out_ACCGk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, in_ACC40Si, in_ACCGi, out_FRintk, out_ACC40Sk, out_ACC40Uk, out_ACCGk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_mwcuti (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mwcuti.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT in_ACC40Si = -1; + INT in_ACCGi = -1; + INT out_FRintk = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + INT out_ACCGk = -1; + in_FRinti = FLD (in_FRinti); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, in_ACC40Si, in_ACCGi, out_FRintk, out_ACC40Sk, out_ACC40Uk, out_ACCGk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_mcut (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mcut.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT in_ACC40Si = -1; + INT in_ACCGi = -1; + INT out_FRintk = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + INT out_ACCGk = -1; + in_FRintj = FLD (in_FRintj); + in_ACC40Si = FLD (in_ACC40Si); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 1; + referenced |= 1 << 2; + referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, in_ACC40Si, in_ACCGi, out_FRintk, out_ACC40Sk, out_ACC40Uk, out_ACCGk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_mcuti (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mcuti.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT in_ACC40Si = -1; + INT in_ACCGi = -1; + INT out_FRintk = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + INT out_ACCGk = -1; + in_ACC40Si = FLD (in_ACC40Si); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 2; + referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, in_ACC40Si, in_ACCGi, out_FRintk, out_ACC40Sk, out_ACC40Uk, out_ACCGk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_mcutss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mcut.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT in_ACC40Si = -1; + INT in_ACCGi = -1; + INT out_FRintk = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + INT out_ACCGk = -1; + in_FRintj = FLD (in_FRintj); + in_ACC40Si = FLD (in_ACC40Si); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 1; + referenced |= 1 << 2; + referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, in_ACC40Si, in_ACCGi, out_FRintk, out_ACC40Sk, out_ACC40Uk, out_ACCGk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_mcutssi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mcuti.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT in_ACC40Si = -1; + INT in_ACCGi = -1; + INT out_FRintk = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + INT out_ACCGk = -1; + in_ACC40Si = FLD (in_ACC40Si); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 2; + referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, in_ACC40Si, in_ACCGi, out_FRintk, out_ACC40Sk, out_ACC40Uk, out_ACCGk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_mdcutssi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdcutssi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr500_maveh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mwcut.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT in_ACC40Si = -1; + INT in_ACCGi = -1; + INT out_FRintk = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + INT out_ACCGk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, in_ACC40Si, in_ACCGi, out_FRintk, out_ACC40Sk, out_ACC40Uk, out_ACCGk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_msllhi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_msllhi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT in_ACC40Si = -1; + INT in_ACCGi = -1; + INT out_FRintk = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + INT out_ACCGk = -1; + in_FRinti = FLD (in_FRinti); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, in_ACC40Si, in_ACCGi, out_FRintk, out_ACC40Sk, out_ACC40Uk, out_ACCGk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_msrlhi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_msllhi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT in_ACC40Si = -1; + INT in_ACCGi = -1; + INT out_FRintk = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + INT out_ACCGk = -1; + in_FRinti = FLD (in_FRinti); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, in_ACC40Si, in_ACCGi, out_FRintk, out_ACC40Sk, out_ACC40Uk, out_ACCGk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_msrahi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_msllhi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT in_ACC40Si = -1; + INT in_ACCGi = -1; + INT out_FRintk = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + INT out_ACCGk = -1; + in_FRinti = FLD (in_FRinti); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, in_ACC40Si, in_ACCGi, out_FRintk, out_ACC40Sk, out_ACC40Uk, out_ACCGk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_mdrotli (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdrotli.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr500_mcplhi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mcplhi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr500_mcpli (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mwcuti.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr500_msaths (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT in_ACC40Si = -1; + INT in_ACCGi = -1; + INT out_FRintk = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + INT out_ACCGk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr500_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, in_ACC40Si, in_ACCGi, out_FRintk, out_ACC40Sk, out_ACC40Uk, out_ACCGk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_mqsaths (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr500_msathu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT in_ACC40Si = -1; + INT in_ACCGi = -1; + INT out_FRintk = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + INT out_ACCGk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr500_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, in_ACC40Si, in_ACCGi, out_FRintk, out_ACC40Sk, out_ACC40Uk, out_ACCGk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_mcmpsh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mcmpsh.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT in_ACC40Si = -1; + INT in_ACCGi = -1; + INT out_FRintk = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + INT out_ACCGk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + cycles += frvbf_model_fr500_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, in_ACC40Si, in_ACCGi, out_FRintk, out_ACC40Sk, out_ACC40Uk, out_ACCGk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_mcmpuh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mcmpsh.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT in_ACC40Si = -1; + INT in_ACCGi = -1; + INT out_FRintk = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + INT out_ACCGk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + cycles += frvbf_model_fr500_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, in_ACC40Si, in_ACCGi, out_FRintk, out_ACC40Sk, out_ACC40Uk, out_ACCGk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_mabshs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mabshs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr500_maddhss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT in_ACC40Si = -1; + INT in_ACCGi = -1; + INT out_FRintk = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + INT out_ACCGk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr500_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, in_ACC40Si, in_ACCGi, out_FRintk, out_ACC40Sk, out_ACC40Uk, out_ACCGk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_maddhus (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT in_ACC40Si = -1; + INT in_ACCGi = -1; + INT out_FRintk = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + INT out_ACCGk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr500_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, in_ACC40Si, in_ACCGi, out_FRintk, out_ACC40Sk, out_ACC40Uk, out_ACCGk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_msubhss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT in_ACC40Si = -1; + INT in_ACCGi = -1; + INT out_FRintk = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + INT out_ACCGk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr500_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, in_ACC40Si, in_ACCGi, out_FRintk, out_ACC40Sk, out_ACC40Uk, out_ACCGk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_msubhus (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT in_ACC40Si = -1; + INT in_ACCGi = -1; + INT out_FRintk = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + INT out_ACCGk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr500_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, in_ACC40Si, in_ACCGi, out_FRintk, out_ACC40Sk, out_ACC40Uk, out_ACCGk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cmaddhss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT in_ACC40Si = -1; + INT in_ACCGi = -1; + INT out_FRintk = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + INT out_ACCGk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + cycles += frvbf_model_fr500_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, in_ACC40Si, in_ACCGi, out_FRintk, out_ACC40Sk, out_ACC40Uk, out_ACCGk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cmaddhus (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT in_ACC40Si = -1; + INT in_ACCGi = -1; + INT out_FRintk = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + INT out_ACCGk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + cycles += frvbf_model_fr500_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, in_ACC40Si, in_ACCGi, out_FRintk, out_ACC40Sk, out_ACC40Uk, out_ACCGk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cmsubhss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT in_ACC40Si = -1; + INT in_ACCGi = -1; + INT out_FRintk = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + INT out_ACCGk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + cycles += frvbf_model_fr500_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, in_ACC40Si, in_ACCGi, out_FRintk, out_ACC40Sk, out_ACC40Uk, out_ACCGk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cmsubhus (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT in_ACC40Si = -1; + INT in_ACCGi = -1; + INT out_FRintk = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + INT out_ACCGk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + cycles += frvbf_model_fr500_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, in_ACC40Si, in_ACCGi, out_FRintk, out_ACC40Sk, out_ACC40Uk, out_ACCGk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_mqaddhss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + out_FRintk = FLD (out_FRintkeven); + cycles += frvbf_model_fr500_u_media_quad_arith (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_mqaddhus (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + out_FRintk = FLD (out_FRintkeven); + cycles += frvbf_model_fr500_u_media_quad_arith (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_mqsubhss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + out_FRintk = FLD (out_FRintkeven); + cycles += frvbf_model_fr500_u_media_quad_arith (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_mqsubhus (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + out_FRintk = FLD (out_FRintkeven); + cycles += frvbf_model_fr500_u_media_quad_arith (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cmqaddhss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + out_FRintk = FLD (out_FRintkeven); + cycles += frvbf_model_fr500_u_media_quad_arith (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cmqaddhus (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + out_FRintk = FLD (out_FRintkeven); + cycles += frvbf_model_fr500_u_media_quad_arith (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cmqsubhss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + out_FRintk = FLD (out_FRintkeven); + cycles += frvbf_model_fr500_u_media_quad_arith (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cmqsubhus (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + out_FRintk = FLD (out_FRintkeven); + cycles += frvbf_model_fr500_u_media_quad_arith (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_maddaccs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdasaccs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr500_msubaccs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdasaccs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr500_mdaddaccs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdasaccs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr500_mdsubaccs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdasaccs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr500_masaccs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdasaccs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr500_mdasaccs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdasaccs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr500_mmulhs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 9)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_media_dual_mul (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_mmulhu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 9)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_media_dual_mul (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_mmulxhs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 9)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_media_dual_mul (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_mmulxhu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 9)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_media_dual_mul (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cmmulhs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 11)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_media_dual_mul (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cmmulhu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 11)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_media_dual_mul (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_mqmulhs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + out_ACC40Sk = FLD (out_ACC40Sk); + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + if (insn_referenced & (1 << 13)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_media_quad_mul (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_mqmulhu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + out_ACC40Sk = FLD (out_ACC40Sk); + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + if (insn_referenced & (1 << 13)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_media_quad_mul (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_mqmulxhs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + out_ACC40Sk = FLD (out_ACC40Sk); + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + if (insn_referenced & (1 << 13)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_media_quad_mul (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_mqmulxhu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + out_ACC40Sk = FLD (out_ACC40Sk); + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + if (insn_referenced & (1 << 13)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_media_quad_mul (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cmqmulhs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + out_ACC40Sk = FLD (out_ACC40Sk); + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + if (insn_referenced & (1 << 15)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_media_quad_mul (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cmqmulhu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + out_ACC40Sk = FLD (out_ACC40Sk); + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + if (insn_referenced & (1 << 15)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_media_quad_mul (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_mmachs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 11)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_media_dual_mul (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_mmachu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Uk = FLD (out_ACC40Uk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 11)) referenced |= 1 << 3; + cycles += frvbf_model_fr500_u_media_dual_mul (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_mmrdhs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 11)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_media_dual_mul (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_mmrdhu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Uk = FLD (out_ACC40Uk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 11)) referenced |= 1 << 3; + cycles += frvbf_model_fr500_u_media_dual_mul (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cmmachs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 2)) referenced |= 1 << 0; + if (insn_referenced & (1 << 3)) referenced |= 1 << 1; + if (insn_referenced & (1 << 13)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_media_dual_mul (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cmmachu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Uk = FLD (out_ACC40Uk); + if (insn_referenced & (1 << 2)) referenced |= 1 << 0; + if (insn_referenced & (1 << 3)) referenced |= 1 << 1; + if (insn_referenced & (1 << 13)) referenced |= 1 << 3; + cycles += frvbf_model_fr500_u_media_dual_mul (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_mqmachs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + out_ACC40Sk = FLD (out_ACC40Sk); + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + if (insn_referenced & (1 << 17)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_media_quad_mul (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_mqmachu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + out_ACC40Uk = FLD (out_ACC40Uk); + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + if (insn_referenced & (1 << 17)) referenced |= 1 << 3; + cycles += frvbf_model_fr500_u_media_quad_mul (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cmqmachs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + out_ACC40Sk = FLD (out_ACC40Sk); + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + if (insn_referenced & (1 << 19)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_media_quad_mul (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cmqmachu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + out_ACC40Uk = FLD (out_ACC40Uk); + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + if (insn_referenced & (1 << 19)) referenced |= 1 << 3; + cycles += frvbf_model_fr500_u_media_quad_mul (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_mqxmachs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr500_mqxmacxhs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr500_mqmacxhs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr500_mcpxrs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 9)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_media_dual_mul (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_mcpxru (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 9)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_media_dual_mul (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_mcpxis (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 9)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_media_dual_mul (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_mcpxiu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 9)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_media_dual_mul (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cmcpxrs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 11)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_media_dual_mul (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cmcpxru (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 11)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_media_dual_mul (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cmcpxis (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 11)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_media_dual_mul (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cmcpxiu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 11)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_media_dual_mul (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_mqcpxrs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + out_ACC40Sk = FLD (out_ACC40Sk); + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + if (insn_referenced & (1 << 13)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_media_quad_complex (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_mqcpxru (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + out_ACC40Sk = FLD (out_ACC40Sk); + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + if (insn_referenced & (1 << 13)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_media_quad_complex (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_mqcpxis (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + out_ACC40Sk = FLD (out_ACC40Sk); + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + if (insn_referenced & (1 << 13)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_media_quad_complex (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_mqcpxiu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + out_ACC40Sk = FLD (out_ACC40Sk); + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + if (insn_referenced & (1 << 13)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_media_quad_complex (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_mexpdhw (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmexpdhw.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT in_ACC40Si = -1; + INT in_ACCGi = -1; + INT out_FRintk = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + INT out_ACCGk = -1; + cycles += frvbf_model_fr500_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, in_ACC40Si, in_ACCGi, out_FRintk, out_ACC40Sk, out_ACC40Uk, out_ACCGk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cmexpdhw (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmexpdhw.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT in_ACC40Si = -1; + INT in_ACCGi = -1; + INT out_FRintk = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + INT out_ACCGk = -1; + cycles += frvbf_model_fr500_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, in_ACC40Si, in_ACCGi, out_FRintk, out_ACC40Sk, out_ACC40Uk, out_ACCGk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_mexpdhd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmexpdhd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT out_FRintk = -1; + out_FRintk = FLD (out_FRintkeven); + cycles += frvbf_model_fr500_u_media_dual_expand (current_cpu, idesc, 0, referenced, in_FRinti, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cmexpdhd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmexpdhd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT out_FRintk = -1; + out_FRintk = FLD (out_FRintkeven); + cycles += frvbf_model_fr500_u_media_dual_expand (current_cpu, idesc, 0, referenced, in_FRinti, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_mpackh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT in_ACC40Si = -1; + INT in_ACCGi = -1; + INT out_FRintk = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + INT out_ACCGk = -1; + cycles += frvbf_model_fr500_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, in_ACC40Si, in_ACCGi, out_FRintk, out_ACC40Sk, out_ACC40Uk, out_ACCGk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_mdpackh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdpackh.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + out_FRintk = FLD (out_FRintkeven); + cycles += frvbf_model_fr500_u_media_quad_arith (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_munpackh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_munpackh.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + out_FRintk = FLD (out_FRintkeven); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + cycles += frvbf_model_fr500_u_media_dual_expand (current_cpu, idesc, 0, referenced, in_FRinti, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_mdunpackh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdunpackh.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT out_FRintk = -1; + out_FRintk = FLD (out_FRintk); + in_FRinti = FLD (in_FRintieven); + if (insn_referenced & (1 << 9)) referenced |= 1 << 1; + cycles += frvbf_model_fr500_u_media_dual_unpack (current_cpu, idesc, 0, referenced, in_FRinti, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_mbtoh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmbtoh.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRintj = FLD (in_FRintj); + out_FRintk = FLD (out_FRintkeven); + referenced |= 1 << 0; + cycles += frvbf_model_fr500_u_media_dual_btoh (current_cpu, idesc, 0, referenced, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cmbtoh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmbtoh.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRintj = FLD (in_FRintj); + out_FRintk = FLD (out_FRintkeven); + referenced |= 1 << 0; + cycles += frvbf_model_fr500_u_media_dual_btoh (current_cpu, idesc, 0, referenced, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_mhtob (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmhtob.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRintj = -1; + INT out_FRintk = -1; + out_FRintk = FLD (out_FRintk); + in_FRintj = FLD (in_FRintjeven); + referenced |= 1 << 1; + cycles += frvbf_model_fr500_u_media_dual_htob (current_cpu, idesc, 0, referenced, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cmhtob (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmhtob.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRintj = -1; + INT out_FRintk = -1; + out_FRintk = FLD (out_FRintk); + in_FRintj = FLD (in_FRintjeven); + referenced |= 1 << 1; + cycles += frvbf_model_fr500_u_media_dual_htob (current_cpu, idesc, 0, referenced, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_mbtohe (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmbtohe.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRintj = FLD (in_FRintj); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr500_u_media_dual_btohe (current_cpu, idesc, 0, referenced, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_cmbtohe (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmbtohe.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRintj = FLD (in_FRintj); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr500_u_media_dual_btohe (current_cpu, idesc, 0, referenced, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_mnop (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr500_mclracc_0 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdasaccs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT in_ACC40Si = -1; + INT in_ACCGi = -1; + INT out_FRintk = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + INT out_ACCGk = -1; + cycles += frvbf_model_fr500_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, in_ACC40Si, in_ACCGi, out_FRintk, out_ACC40Sk, out_ACC40Uk, out_ACCGk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_mclracc_1 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdasaccs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT in_ACC40Si = -1; + INT in_ACCGi = -1; + INT out_FRintk = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + INT out_ACCGk = -1; + cycles += frvbf_model_fr500_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, in_ACC40Si, in_ACCGi, out_FRintk, out_ACC40Sk, out_ACC40Uk, out_ACCGk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_mrdacc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mcuti.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT in_ACC40Si = -1; + INT in_ACCGi = -1; + INT out_FRintk = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + INT out_ACCGk = -1; + in_ACC40Si = FLD (in_ACC40Si); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 2; + referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, in_ACC40Si, in_ACCGi, out_FRintk, out_ACC40Sk, out_ACC40Uk, out_ACCGk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_mrdaccg (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mrdaccg.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT in_ACC40Si = -1; + INT in_ACCGi = -1; + INT out_FRintk = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + INT out_ACCGk = -1; + in_ACCGi = FLD (in_ACCGi); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 3; + referenced |= 1 << 4; + cycles += frvbf_model_fr500_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, in_ACC40Si, in_ACCGi, out_FRintk, out_ACC40Sk, out_ACC40Uk, out_ACCGk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_mwtacc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT in_ACC40Si = -1; + INT in_ACCGi = -1; + INT out_FRintk = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + INT out_ACCGk = -1; + in_FRinti = FLD (in_FRinti); + out_ACC40Sk = FLD (out_ACC40Sk); + referenced |= 1 << 0; + referenced |= 1 << 5; + cycles += frvbf_model_fr500_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, in_ACC40Si, in_ACCGi, out_FRintk, out_ACC40Sk, out_ACC40Uk, out_ACCGk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_mwtaccg (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mwtaccg.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT in_ACC40Si = -1; + INT in_ACCGi = -1; + INT out_FRintk = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + INT out_ACCGk = -1; + in_FRinti = FLD (in_FRinti); + out_ACCGk = FLD (out_ACCGk); + referenced |= 1 << 0; + referenced |= 1 << 7; + cycles += frvbf_model_fr500_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, in_ACC40Si, in_ACCGi, out_FRintk, out_ACC40Sk, out_ACC40Uk, out_ACCGk); + } + return cycles; +#undef FLD +} + +static int +model_fr500_mcop1 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr500_mcop2 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr500_fnop (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_add (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_sub (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_and (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_or (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_xor (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_not (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_scutss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_sdiv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_nsdiv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_udiv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_nudiv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_smul (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_umul (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_smu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smass.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_smass (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smass.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_smsss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smass.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_sll (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_srl (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_sra (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_slass (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_scutss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_scutss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_scan (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cadd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_csub (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cand (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cor (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cxor (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cnot (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_csmul (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_csdiv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cudiv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_csll (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_csrl (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_csra (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cscan (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_addcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_subcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_andcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_orcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_xorcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_sllcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_srlcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_sracc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_smulcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_umulcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_caddcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_caddcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_csubcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_caddcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_csmulcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_csmulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_candcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_caddcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_corcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_caddcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cxorcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_caddcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_csllcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_caddcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_csrlcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_caddcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_csracc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_caddcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_addx (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_subx (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_addxcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_subxcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_addss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_subss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_addi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_subi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_andi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_ori (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_xori (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_sdivi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_nsdivi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_udivi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_nudivi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_smuli (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smuli.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_umuli (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smuli.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_slli (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_srli (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_srai (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_scani (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_addicc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_subicc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_andicc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_oricc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_xoricc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_smulicc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_umulicc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_sllicc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_srlicc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_sraicc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_addxi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_subxi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_addxicc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_subxicc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cmpb (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cmpba (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_setlo (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_setlo.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_sethi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_sethi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_setlos (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_setlos.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_ldsb (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_ldub (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_ldsh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_lduh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_ld (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_ldbf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_ldhf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_ldf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_ldc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_nldsb (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_nldub (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_nldsh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_nlduh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_nld (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_nldbf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_nldhf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_nldf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_ldd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_lddf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_lddc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_lddcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_nldd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_nlddf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_ldq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_ldqf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_ldqc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_nldq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_nldqf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_ldsbu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_ldubu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_ldshu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_lduhu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_ldu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_nldsbu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_nldubu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_nldshu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_nlduhu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_nldu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_ldbfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_ldhfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_ldfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_ldcu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_nldbfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_nldhfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_nldfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_lddu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_nlddu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_lddfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_lddcu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_lddcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_nlddfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_ldqu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_nldqu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_ldqfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_ldqcu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_nldqfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_ldsbi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_ldshi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_ldi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_ldubi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_lduhi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_ldbfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldbfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_ldhfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldbfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_ldfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldbfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_nldsbi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_nldubi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_nldshi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_nlduhi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_nldi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_nldbfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldbfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_nldhfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldbfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_nldfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldbfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_lddi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smuli.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_lddfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_lddfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_nlddi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smuli.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_nlddfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_lddfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_ldqi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_ldqfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_nldqfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_stb (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_sth (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_st (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_stbf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_sthf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_stf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_stc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_rstb (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_rsth (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_rst (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_rstbf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_rsthf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_rstf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_std (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_stdf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_stdc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_rstd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_rstdf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_stq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_stqf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_stqc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_rstq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_rstqf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_stbu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_sthu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_stu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_stbfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_sthfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_stfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_stcu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_stdu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_stdfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_stdcu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_stqu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_stqfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_stqcu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cldsb (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cldub (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cldsh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_clduh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cld (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cldbf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cldhf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cldf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cldd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_clddf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cldq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cldsbu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cldubu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cldshu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_clduhu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cldu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cldbfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cldhfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cldfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_clddu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_clddfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cldqu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cstb (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_csth (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cst (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cstbf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_csthf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cstf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cstd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cstdf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cstq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cstbu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_csthu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cstu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cstbfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_csthfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cstfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cstdu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cstdfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_stbi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_sthi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_sti (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_stbfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stbfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_sthfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stbfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_stfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stbfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_stdi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_stdfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_stqi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_stqfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_swap (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_swapi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cswap (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_movgf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmovgfd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_movfg (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmovfgd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_movgfd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmovgfd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_movfgd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmovfgd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_movgfq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_movgfq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_movfgq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_movfgq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cmovgf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmovgfd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cmovfg (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmovfgd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cmovgfd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmovgfd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cmovfgd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmovfgd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_movgs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_movgs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_movsg (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_movsg.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_bra (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_bno (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_beq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_bne (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_ble (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_bgt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_blt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_bge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_bls (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_bhi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_bc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_bnc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_bn (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_bp (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_bv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_bnv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fbra (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fbno (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fbne (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fbeq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fblg (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fbue (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fbul (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fbge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fblt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fbuge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fbug (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fble (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fbgt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fbule (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fbu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fbo (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_bctrlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_bralr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_bnolr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_beqlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_bnelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_blelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_bgtlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_bltlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_bgelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_blslr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_bhilr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_bclr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_bnclr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_bnlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_bplr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_bvlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_bnvlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fbralr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fbnolr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fbeqlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fbnelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fblglr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fbuelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fbullr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fbgelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fbltlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fbugelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fbuglr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fblelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fbgtlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fbulelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fbulr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fbolr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_bcralr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_bcnolr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_bceqlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_bcnelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_bclelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_bcgtlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_bcltlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_bcgelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_bclslr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_bchilr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_bcclr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_bcnclr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_bcnlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_bcplr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_bcvlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_bcnvlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fcbralr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fcbnolr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fcbeqlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fcbnelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fcblglr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fcbuelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fcbullr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fcbgelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fcbltlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fcbugelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fcbuglr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fcblelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fcbgtlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fcbulelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fcbulr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fcbolr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_jmpl (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cjmpl.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_calll (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cjmpl.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_jmpil (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_jmpil.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_callil (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_jmpil.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_call (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_call.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_rett (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_rett.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_rei (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_tra (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_tno (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_teq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_tne (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_tle (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_tgt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_tlt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_tge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_tls (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_thi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_tc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_tnc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_tn (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_tp (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_tv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_tnv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_ftra (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_ftno (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_ftne (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fteq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_ftlg (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_ftue (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_ftul (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_ftge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_ftlt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_ftuge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_ftug (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_ftle (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_ftgt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_ftule (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_ftu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fto (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_tira (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_tino (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_tieq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_tine (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_tile (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_tigt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_tilt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_tige (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_tils (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_tihi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_tic (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_tinc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_tin (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_tip (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_tiv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_tinv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_ftira (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_ftino (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_ftine (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_ftieq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_ftilg (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_ftiue (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_ftiul (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_ftige (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_ftilt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_ftiuge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_ftiug (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_ftile (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_ftigt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_ftiule (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_ftiu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_ftio (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_break (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_break.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_mtrap (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_andcr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_andcr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_orcr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_andcr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_xorcr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_andcr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_nandcr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_andcr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_norcr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_andcr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_andncr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_andcr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_orncr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_andcr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_nandncr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_andcr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_norncr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_andcr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_notcr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_andcr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_ckra (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_ckno (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_ckeq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_ckne (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_ckle (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_ckgt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cklt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_ckge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_ckls (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_ckhi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_ckc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cknc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_ckn (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_ckp (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_ckv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cknv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fckra (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fckno (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fckne (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fckeq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fcklg (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fckue (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fckul (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fckge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fcklt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fckuge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fckug (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fckle (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fckgt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fckule (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fcku (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fcko (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cckra (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cckno (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cckeq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cckne (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cckle (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cckgt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_ccklt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cckge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cckls (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cckhi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cckc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_ccknc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cckn (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cckp (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cckv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_ccknv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cfckra (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cfckno (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cfckne (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cfckeq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cfcklg (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cfckue (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cfckul (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cfckge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cfcklt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cfckuge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cfckug (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cfckle (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cfckgt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cfckule (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cfcku (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cfcko (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cjmpl (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cjmpl.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_ccalll (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cjmpl.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_ici (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_icpl.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_dci (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_icpl.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_icei (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_icei.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_dcei (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_icei.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_dcf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_icpl.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_dcef (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_icei.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_witlb (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_wdtlb (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_itlbi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_dtlbi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_icpl (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_icpl.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_dcpl (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_icpl.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_icul (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_jmpil.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_dcul (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_jmpil.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_bar (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_membar (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cop1 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cop2 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_clrgr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_clrfr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_clrga (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_clrfa (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_commitgr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_setlos.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_commitfr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mhsethis.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_commitga (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_commitfa (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fitos (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fditos.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fstoi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdstoi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fitod (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fitod.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fdtoi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdtoi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fditos (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fditos.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fdstoi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdstoi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_nfditos (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fditos.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_nfdstoi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdstoi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cfitos (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfitos.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cfstoi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfstoi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_nfitos (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fditos.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_nfstoi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdstoi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fmovs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fmovd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fmaddd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fdmovs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cfmovs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fnegs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fnegd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fmaddd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fdnegs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cfnegs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fabss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fabsd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fmaddd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fdabss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cfabss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fsqrts (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fdsqrts (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_nfdsqrts (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fsqrtd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fmaddd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cfsqrts (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_nfsqrts (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fadds (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fsubs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fmuls (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fdivs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_faddd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fmaddd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fsubd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fmaddd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fmuld (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fmaddd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fdivd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fmaddd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cfadds (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cfsubs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cfmuls (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cfdivs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_nfadds (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_nfsubs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_nfmuls (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_nfdivs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fcmps (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfcmps.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fcmpd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcmpd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cfcmps (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfcmps.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fdcmps (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_nfdcmps.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fmadds (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fmsubs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fmaddd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fmaddd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fmsubd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fmaddd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fdmadds (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_nfdmadds (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cfmadds (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cfmsubs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_nfmadds (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_nfmsubs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fmas (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fmss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fdmas (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmas.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fdmss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmas.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_nfdmas (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmas.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_nfdmss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmas.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cfmas (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmas.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cfmss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmas.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fmad (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fmsd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_nfmas (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_nfmss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fdadds (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fdsubs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fdmuls (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fddivs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fdsads (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fdmulcs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_nfdmulcs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_nfdadds (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_nfdsubs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_nfdmuls (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_nfddivs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_nfdsads (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_nfdcmps (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_nfdcmps.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_mhsetlos (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mhsetlos.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_mhsethis (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mhsethis.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_mhdsets (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mhdsets.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_mhsetloh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mhsetloh.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_mhsethih (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mhsethih.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_mhdseth (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mhdseth.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_mand (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mwcut.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_mor (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mwcut.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_mxor (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mwcut.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cmand (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmand.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cmor (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmand.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cmxor (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmand.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_mnot (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mcut.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cmnot (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmand.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_mrotli (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mwcuti.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_mrotri (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mwcuti.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_mwcut (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mwcut.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_mwcuti (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mwcuti.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_mcut (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mcut.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_mcuti (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mcuti.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_mcutss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mcut.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_mcutssi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mcuti.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_mdcutssi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdcutssi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_maveh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mwcut.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_msllhi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_msllhi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_msrlhi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_msllhi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_msrahi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_msllhi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_mdrotli (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdrotli.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_mcplhi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mcplhi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_mcpli (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mwcuti.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_msaths (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_mqsaths (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_msathu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_mcmpsh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mcmpsh.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_mcmpuh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mcmpsh.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_mabshs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mabshs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_maddhss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_maddhus (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_msubhss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_msubhus (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cmaddhss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cmaddhus (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cmsubhss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cmsubhus (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_mqaddhss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_mqaddhus (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_mqsubhss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_mqsubhus (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cmqaddhss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cmqaddhus (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cmqsubhss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cmqsubhus (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_maddaccs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdasaccs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_msubaccs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdasaccs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_mdaddaccs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdasaccs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_mdsubaccs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdasaccs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_masaccs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdasaccs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_mdasaccs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdasaccs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_mmulhs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_mmulhu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_mmulxhs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_mmulxhu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cmmulhs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cmmulhu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_mqmulhs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_mqmulhu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_mqmulxhs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_mqmulxhu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cmqmulhs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cmqmulhu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_mmachs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_mmachu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_mmrdhs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_mmrdhu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cmmachs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cmmachu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_mqmachs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_mqmachu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cmqmachs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cmqmachu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_mqxmachs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_mqxmacxhs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_mqmacxhs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_mcpxrs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_mcpxru (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_mcpxis (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_mcpxiu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cmcpxrs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cmcpxru (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cmcpxis (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cmcpxiu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_mqcpxrs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_mqcpxru (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_mqcpxis (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_mqcpxiu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_mexpdhw (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmexpdhw.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cmexpdhw (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmexpdhw.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_mexpdhd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmexpdhd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cmexpdhd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmexpdhd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_mpackh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_mdpackh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdpackh.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_munpackh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_munpackh.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_mdunpackh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdunpackh.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_mbtoh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmbtoh.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cmbtoh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmbtoh.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_mhtob (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmhtob.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cmhtob (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmhtob.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_mbtohe (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmbtohe.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_cmbtohe (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmbtohe.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_mnop (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_mclracc_0 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdasaccs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_mclracc_1 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdasaccs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_mrdacc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mcuti.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_mrdaccg (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mrdaccg.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_mwtacc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_mwtaccg (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mwtaccg.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_mcop1 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_mcop2 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_fnop (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_add (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr400_sub (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr400_and (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr400_or (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr400_xor (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr400_not (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_scutss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr400_sdiv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr400_nsdiv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr400_udiv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr400_nudiv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr400_smul (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRdoublek = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRdoublek = FLD (out_GRdoublek); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_imul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRdoublek, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr400_umul (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRdoublek = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRdoublek = FLD (out_GRdoublek); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_imul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRdoublek, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr400_smu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smass.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr400_smass (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smass.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr400_smsss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smass.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr400_sll (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr400_srl (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr400_sra (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr400_slass (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_scutss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_scutss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_scan (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cadd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 4)) referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr400_csub (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 4)) referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cand (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 4)) referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cor (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 4)) referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cxor (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 4)) referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cnot (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 3)) referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr400_csmul (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRdoublek = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRdoublek = FLD (out_GRdoublek); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 4)) referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_imul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRdoublek, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr400_csdiv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 5)) referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cudiv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 5)) referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr400_csll (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 4)) referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr400_csrl (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 4)) referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr400_csra (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 4)) referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cscan (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 4)) referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr400_addcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + referenced |= 1 << 3; + cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr400_subcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + referenced |= 1 << 3; + cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr400_andcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + if (insn_referenced & (1 << 4)) referenced |= 1 << 3; + cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr400_orcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + if (insn_referenced & (1 << 4)) referenced |= 1 << 3; + cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr400_xorcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + if (insn_referenced & (1 << 4)) referenced |= 1 << 3; + cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr400_sllcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + referenced |= 1 << 3; + cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr400_srlcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + referenced |= 1 << 3; + cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr400_sracc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + referenced |= 1 << 3; + cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr400_smulcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRdoublek = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRdoublek = FLD (out_GRdoublek); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + referenced |= 1 << 3; + cycles += frvbf_model_fr400_u_imul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRdoublek, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr400_umulcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRdoublek = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRdoublek = FLD (out_GRdoublek); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + referenced |= 1 << 3; + cycles += frvbf_model_fr400_u_imul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRdoublek, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr400_caddcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_caddcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr400_csubcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_caddcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr400_csmulcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_csmulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRdoublek = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRdoublek = FLD (out_GRdoublek); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_imul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRdoublek, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr400_candcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_caddcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr400_corcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_caddcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cxorcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_caddcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr400_csllcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_caddcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr400_csrlcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_caddcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr400_csracc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_caddcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr400_addx (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr400_subx (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr400_addxcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + referenced |= 1 << 3; + cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr400_subxcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + referenced |= 1 << 3; + cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr400_addss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr400_subss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr400_addi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr400_subi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr400_andi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr400_ori (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr400_xori (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr400_sdivi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr400_nsdivi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr400_udivi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr400_nudivi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr400_smuli (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smuli.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRdoublek = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRdoublek = FLD (out_GRdoublek); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_imul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRdoublek, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr400_umuli (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smuli.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRdoublek = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRdoublek = FLD (out_GRdoublek); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_imul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRdoublek, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr400_slli (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr400_srli (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr400_srai (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr400_scani (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr400_addicc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 2; + referenced |= 1 << 3; + cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr400_subicc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 2; + referenced |= 1 << 3; + cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr400_andicc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 2; + if (insn_referenced & (1 << 4)) referenced |= 1 << 3; + cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr400_oricc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 2; + if (insn_referenced & (1 << 4)) referenced |= 1 << 3; + cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr400_xoricc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 2; + if (insn_referenced & (1 << 4)) referenced |= 1 << 3; + cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr400_smulicc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRdoublek = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRdoublek = FLD (out_GRdoublek); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 2; + referenced |= 1 << 3; + cycles += frvbf_model_fr400_u_imul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRdoublek, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr400_umulicc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRdoublek = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRdoublek = FLD (out_GRdoublek); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 2; + referenced |= 1 << 3; + cycles += frvbf_model_fr400_u_imul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRdoublek, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr400_sllicc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 2; + referenced |= 1 << 3; + cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr400_srlicc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 2; + referenced |= 1 << 3; + cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr400_sraicc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 2; + referenced |= 1 << 3; + cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr400_addxi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr400_subxi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr400_addxicc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 2; + referenced |= 1 << 3; + cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr400_subxicc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 2; + referenced |= 1 << 3; + cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cmpb (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cmpba (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr400_setlo (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_setlo.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT out_GRkhi = -1; + INT out_GRklo = -1; + out_GRklo = FLD (out_GRklo); + referenced |= 1 << 1; + cycles += frvbf_model_fr400_u_set_hilo (current_cpu, idesc, 0, referenced, out_GRkhi, out_GRklo); + } + return cycles; +#undef FLD +} + +static int +model_fr400_sethi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_sethi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT out_GRkhi = -1; + INT out_GRklo = -1; + out_GRkhi = FLD (out_GRkhi); + referenced |= 1 << 0; + cycles += frvbf_model_fr400_u_set_hilo (current_cpu, idesc, 0, referenced, out_GRkhi, out_GRklo); + } + return cycles; +#undef FLD +} + +static int +model_fr400_setlos (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_setlos.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + out_GRk = FLD (out_GRk); + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr400_ldsb (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr400_ldub (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr400_ldsh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr400_lduh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr400_ld (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr400_ldbf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr400_ldhf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr400_ldf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr400_ldc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_nldsb (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_nldub (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_nldsh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_nlduh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_nld (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_nldbf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_nldhf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_nldf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_ldd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRdoublek = FLD (out_GRdoublek); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 4)) referenced |= 1 << 3; + cycles += frvbf_model_fr400_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr400_lddf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_FRdoublek = FLD (out_FRdoublek); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr400_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr400_lddc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_lddcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_nldd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_nlddf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_ldq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_ldqf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_ldqc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_nldq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_nldqf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_ldsbu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr400_ldubu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr400_ldshu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr400_lduhu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr400_ldu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr400_nldsbu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_nldubu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_nldshu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_nlduhu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_nldu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_ldbfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr400_ldhfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr400_ldfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr400_ldcu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_nldbfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_nldhfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_nldfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_lddu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRdoublek = FLD (out_GRdoublek); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 5)) referenced |= 1 << 3; + cycles += frvbf_model_fr400_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr400_nlddu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_lddfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_FRdoublek = FLD (out_FRdoublek); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr400_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr400_lddcu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_lddcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_nlddfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_ldqu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_nldqu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_ldqfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_ldqcu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_nldqfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_ldsbi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr400_ldshi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr400_ldi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr400_ldubi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr400_lduhi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr400_ldbfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldbfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr400_ldhfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldbfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr400_ldfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldbfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr400_nldsbi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_nldubi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_nldshi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_nlduhi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_nldi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_nldbfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldbfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_nldhfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldbfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_nldfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldbfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_lddi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smuli.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + out_GRdoublek = FLD (out_GRdoublek); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 4)) referenced |= 1 << 3; + cycles += frvbf_model_fr400_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr400_lddfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_lddfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + out_FRdoublek = FLD (out_FRdoublek); + referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr400_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr400_nlddi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smuli.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_nlddfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_lddfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_ldqi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_ldqfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_nldqfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_stb (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_GRk = FLD (in_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr400_sth (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_GRk = FLD (in_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr400_st (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_GRk = FLD (in_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr400_stbf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FRintk = FLD (in_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr400_sthf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FRintk = FLD (in_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr400_stf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FRintk = FLD (in_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr400_stc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_rstb (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_rsth (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_rst (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_rstbf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_rsthf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_rstf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_std (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_GRdoublek = FLD (in_GRdoublek); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr400_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr400_stdf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FRdoublek = FLD (in_FRdoublek); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr400_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr400_stdc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_rstd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_rstdf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_stq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_stqf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_stqc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_rstq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_rstqf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_stbu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_GRk = FLD (in_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr400_sthu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_GRk = FLD (in_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr400_stu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_GRk = FLD (in_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr400_stbfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FRintk = FLD (in_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr400_sthfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FRintk = FLD (in_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr400_stfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FRintk = FLD (in_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr400_stcu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_stdu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_GRdoublek = FLD (in_GRdoublek); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr400_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr400_stdfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FRdoublek = FLD (in_FRdoublek); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr400_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr400_stdcu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_stqu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_stqfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_stqcu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cldsb (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 5)) referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cldub (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 5)) referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cldsh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 5)) referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr400_clduh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 5)) referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cld (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 5)) referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cldbf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_FRintk = FLD (out_FRintk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 5)) referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cldhf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_FRintk = FLD (out_FRintk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 5)) referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cldf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_FRintk = FLD (out_FRintk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 5)) referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cldd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRdoublek = FLD (out_GRdoublek); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 3; + cycles += frvbf_model_fr400_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr400_clddf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + cycles += frvbf_model_fr400_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cldq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cldsbu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 8)) referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cldubu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 8)) referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cldshu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 8)) referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr400_clduhu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 8)) referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cldu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 8)) referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cldbfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_FRintk = FLD (out_FRintk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 5)) referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cldhfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_FRintk = FLD (out_FRintk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 5)) referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cldfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_FRintk = FLD (out_FRintk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 5)) referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr400_clddu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRdoublek = FLD (out_GRdoublek); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 7)) referenced |= 1 << 3; + cycles += frvbf_model_fr400_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr400_clddfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_FRdoublek = FLD (out_FRdoublek); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 5)) referenced |= 1 << 3; + cycles += frvbf_model_fr400_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cldqu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cstb (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_GRk = FLD (in_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 3)) referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr400_csth (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_GRk = FLD (in_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 3)) referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cst (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_GRk = FLD (in_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 3)) referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cstbf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FRintk = FLD (in_FRintk); + if (insn_referenced & (1 << 2)) referenced |= 1 << 0; + if (insn_referenced & (1 << 3)) referenced |= 1 << 1; + if (insn_referenced & (1 << 1)) referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr400_csthf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FRintk = FLD (in_FRintk); + if (insn_referenced & (1 << 2)) referenced |= 1 << 0; + if (insn_referenced & (1 << 3)) referenced |= 1 << 1; + if (insn_referenced & (1 << 1)) referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cstf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FRintk = FLD (in_FRintk); + if (insn_referenced & (1 << 2)) referenced |= 1 << 0; + if (insn_referenced & (1 << 3)) referenced |= 1 << 1; + if (insn_referenced & (1 << 1)) referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cstd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_GRdoublek = FLD (in_GRdoublek); + if (insn_referenced & (1 << 2)) referenced |= 1 << 0; + if (insn_referenced & (1 << 3)) referenced |= 1 << 1; + if (insn_referenced & (1 << 1)) referenced |= 1 << 3; + cycles += frvbf_model_fr400_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cstdf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FRdoublek = FLD (in_FRdoublek); + if (insn_referenced & (1 << 2)) referenced |= 1 << 0; + if (insn_referenced & (1 << 3)) referenced |= 1 << 1; + if (insn_referenced & (1 << 1)) referenced |= 1 << 3; + cycles += frvbf_model_fr400_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cstq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cstbu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_GRk = FLD (in_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 3)) referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr400_csthu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_GRk = FLD (in_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 3)) referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cstu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_GRk = FLD (in_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 3)) referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cstbfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FRintk = FLD (in_FRintk); + if (insn_referenced & (1 << 2)) referenced |= 1 << 0; + if (insn_referenced & (1 << 3)) referenced |= 1 << 1; + if (insn_referenced & (1 << 1)) referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr400_csthfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FRintk = FLD (in_FRintk); + if (insn_referenced & (1 << 2)) referenced |= 1 << 0; + if (insn_referenced & (1 << 3)) referenced |= 1 << 1; + if (insn_referenced & (1 << 1)) referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cstfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FRintk = FLD (in_FRintk); + if (insn_referenced & (1 << 2)) referenced |= 1 << 0; + if (insn_referenced & (1 << 3)) referenced |= 1 << 1; + if (insn_referenced & (1 << 1)) referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cstdu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_GRdoublek = FLD (in_GRdoublek); + if (insn_referenced & (1 << 2)) referenced |= 1 << 0; + if (insn_referenced & (1 << 3)) referenced |= 1 << 1; + if (insn_referenced & (1 << 1)) referenced |= 1 << 3; + cycles += frvbf_model_fr400_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cstdfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FRdoublek = FLD (in_FRdoublek); + if (insn_referenced & (1 << 2)) referenced |= 1 << 0; + if (insn_referenced & (1 << 3)) referenced |= 1 << 1; + if (insn_referenced & (1 << 1)) referenced |= 1 << 3; + cycles += frvbf_model_fr400_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr400_stbi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRk = FLD (in_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr400_sthi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRk = FLD (in_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr400_sti (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRk = FLD (in_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr400_stbfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stbfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_FRintk = FLD (in_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr400_sthfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stbfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_FRintk = FLD (in_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr400_stfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stbfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_FRintk = FLD (in_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr400_stdi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRdoublek = FLD (in_GRdoublek); + referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr400_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr400_stdfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_FRdoublek = FLD (in_FRdoublek); + referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr400_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr400_stqi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_stqfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_swap (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_swap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_swapi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_swap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cswap (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_swap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_movgf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmovgfd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRj = -1; + INT out_FRintk = -1; + in_GRj = FLD (in_GRj); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr400_u_gr2fr (current_cpu, idesc, 0, referenced, in_GRj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_movfg (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmovfgd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRintk = -1; + INT out_GRj = -1; + in_FRintk = FLD (in_FRintk); + out_GRj = FLD (out_GRj); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr400_u_fr2gr (current_cpu, idesc, 0, referenced, in_FRintk, out_GRj); + } + return cycles; +#undef FLD +} + +static int +model_fr400_movgfd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmovgfd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRj = -1; + INT out_FRintk = -1; + in_GRj = FLD (in_GRj); + out_FRintk = FLD (out_FRintk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 4)) referenced |= 1 << 1; + cycles += frvbf_model_fr400_u_gr2fr (current_cpu, idesc, 0, referenced, in_GRj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_movfgd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmovfgd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRintk = -1; + INT out_GRj = -1; + in_FRintk = FLD (in_FRintk); + out_GRj = FLD (out_GRj); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 4)) referenced |= 1 << 1; + cycles += frvbf_model_fr400_u_fr2gr (current_cpu, idesc, 0, referenced, in_FRintk, out_GRj); + } + return cycles; +#undef FLD +} + +static int +model_fr400_movgfq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_movgfq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_movfgq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_movfgq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cmovgf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmovgfd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRj = -1; + INT out_FRintk = -1; + in_GRj = FLD (in_GRj); + out_FRintk = FLD (out_FRintk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 3)) referenced |= 1 << 1; + cycles += frvbf_model_fr400_u_gr2fr (current_cpu, idesc, 0, referenced, in_GRj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cmovfg (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmovfgd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRintk = -1; + INT out_GRj = -1; + in_FRintk = FLD (in_FRintk); + out_GRj = FLD (out_GRj); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 3)) referenced |= 1 << 1; + cycles += frvbf_model_fr400_u_fr2gr (current_cpu, idesc, 0, referenced, in_FRintk, out_GRj); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cmovgfd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmovgfd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRj = -1; + INT out_FRintk = -1; + in_GRj = FLD (in_GRj); + out_FRintk = FLD (out_FRintk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 6)) referenced |= 1 << 1; + cycles += frvbf_model_fr400_u_gr2fr (current_cpu, idesc, 0, referenced, in_GRj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cmovfgd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmovfgd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRintk = -1; + INT out_GRj = -1; + in_FRintk = FLD (in_FRintk); + out_GRj = FLD (out_GRj); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 6)) referenced |= 1 << 1; + cycles += frvbf_model_fr400_u_fr2gr (current_cpu, idesc, 0, referenced, in_FRintk, out_GRj); + } + return cycles; +#undef FLD +} + +static int +model_fr400_movgs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_movgs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRj = -1; + INT out_spr = -1; + in_GRj = FLD (in_GRj); + out_spr = FLD (out_spr); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr400_u_gr2spr (current_cpu, idesc, 0, referenced, in_GRj, out_spr); + } + return cycles; +#undef FLD +} + +static int +model_fr400_movsg (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_movsg.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_spr = -1; + INT out_GRj = -1; + in_spr = FLD (in_spr); + out_GRj = FLD (out_GRj); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr400_u_spr2gr (current_cpu, idesc, 0, referenced, in_spr, out_GRj); + } + return cycles; +#undef FLD +} + +static int +model_fr400_bra (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_bno (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_beq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_bne (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_ble (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_bgt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_blt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_bge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_bls (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_bhi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_bc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_bnc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_bn (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_bp (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_bv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_bnv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fbra (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fbno (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fbne (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fbeq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fblg (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fbue (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fbul (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fbge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fblt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fbuge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fbug (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fble (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fbgt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fbule (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fbu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fbo (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_bctrlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + if (insn_referenced & (1 << 5)) referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_bralr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_bnolr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_beqlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_bnelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_blelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_bgtlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_bltlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_bgelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_blslr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_bhilr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_bclr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_bnclr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_bnlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_bplr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_bvlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_bnvlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fbralr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fbnolr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fbeqlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fbnelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fblglr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fbuelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fbullr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fbgelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fbltlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fbugelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fbuglr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fblelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fbgtlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fbulelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fbulr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fbolr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_bcralr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + if (insn_referenced & (1 << 5)) referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_bcnolr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_bceqlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_bcnelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_bclelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_bcgtlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_bcltlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_bcgelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_bclslr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_bchilr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_bcclr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_bcnclr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_bcnlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_bcplr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_bcvlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_bcnvlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fcbralr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + if (insn_referenced & (1 << 5)) referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fcbnolr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fcbeqlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fcbnelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fcblglr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fcbuelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fcbullr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fcbgelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fcbltlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fcbugelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fcbuglr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fcblelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fcbgtlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fcbulelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fcbulr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fcbolr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_jmpl (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cjmpl.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_calll (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cjmpl.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_jmpil (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_jmpil.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + referenced |= 1 << 0; + referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_callil (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_jmpil.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + referenced |= 1 << 0; + referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_call (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_call.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_rett (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_rett.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_rei (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_tra (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_tno (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_teq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_tne (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_tle (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_tgt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_tlt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_tge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_tls (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_thi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_tc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_tnc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_tn (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_tp (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_tv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_tnv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_ftra (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_ftno (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_ftne (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fteq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_ftlg (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_ftue (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_ftul (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_ftge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_ftlt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_ftuge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_ftug (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_ftle (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_ftgt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_ftule (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_ftu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fto (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_tira (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + referenced |= 1 << 0; + cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_tino (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_tieq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_tine (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_tile (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_tigt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_tilt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_tige (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_tils (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_tihi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_tic (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_tinc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_tin (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_tip (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_tiv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_tinv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_ftira (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + referenced |= 1 << 0; + cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_ftino (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_ftine (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_ftieq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_ftilg (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_ftiue (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_ftiul (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_ftige (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_ftilt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_ftiuge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_ftiug (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_ftile (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_ftigt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_ftiule (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_ftiu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_ftio (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_break (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_break.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_mtrap (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_andcr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_andcr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_orcr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_andcr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_xorcr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_andcr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_nandcr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_andcr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_norcr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_andcr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_andncr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_andcr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_orncr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_andcr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_nandncr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_andcr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_norncr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_andcr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_notcr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_andcr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_ckra (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr400_ckno (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr400_ckeq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + referenced |= 1 << 0; + cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr400_ckne (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + referenced |= 1 << 0; + cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr400_ckle (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + referenced |= 1 << 0; + cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr400_ckgt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + referenced |= 1 << 0; + cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cklt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + referenced |= 1 << 0; + cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr400_ckge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + referenced |= 1 << 0; + cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr400_ckls (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + referenced |= 1 << 0; + cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr400_ckhi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + referenced |= 1 << 0; + cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr400_ckc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + referenced |= 1 << 0; + cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cknc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + referenced |= 1 << 0; + cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr400_ckn (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + referenced |= 1 << 0; + cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr400_ckp (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + referenced |= 1 << 0; + cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr400_ckv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + referenced |= 1 << 0; + cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cknv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + referenced |= 1 << 0; + cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fckra (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fckno (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fckne (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + referenced |= 1 << 1; + cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fckeq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + referenced |= 1 << 1; + cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fcklg (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + referenced |= 1 << 1; + cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fckue (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + referenced |= 1 << 1; + cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fckul (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + referenced |= 1 << 1; + cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fckge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + referenced |= 1 << 1; + cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fcklt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + referenced |= 1 << 1; + cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fckuge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + referenced |= 1 << 1; + cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fckug (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + referenced |= 1 << 1; + cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fckle (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + referenced |= 1 << 1; + cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fckgt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + referenced |= 1 << 1; + cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fckule (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + referenced |= 1 << 1; + cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fcku (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + referenced |= 1 << 1; + cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fcko (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + referenced |= 1 << 1; + cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cckra (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cckno (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cckeq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cckne (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cckle (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cckgt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr400_ccklt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cckge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cckls (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cckhi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cckc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr400_ccknc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cckn (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cckp (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cckv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr400_ccknv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cfckra (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cfckno (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cfckne (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cfckeq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cfcklg (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cfckue (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cfckul (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cfckge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cfcklt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cfckuge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cfckug (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cfckle (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cfckgt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cfckule (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cfcku (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cfcko (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cjmpl (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cjmpl.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_ccalll (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cjmpl.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr400_ici (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_icpl.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr400_u_ici (current_cpu, idesc, 0, referenced, in_GRi, in_GRj); + } + return cycles; +#undef FLD +} + +static int +model_fr400_dci (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_icpl.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr400_u_dci (current_cpu, idesc, 0, referenced, in_GRi, in_GRj); + } + return cycles; +#undef FLD +} + +static int +model_fr400_icei (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_icei.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + cycles += frvbf_model_fr400_u_ici (current_cpu, idesc, 0, referenced, in_GRi, in_GRj); + } + return cycles; +#undef FLD +} + +static int +model_fr400_dcei (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_icei.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + cycles += frvbf_model_fr400_u_dci (current_cpu, idesc, 0, referenced, in_GRi, in_GRj); + } + return cycles; +#undef FLD +} + +static int +model_fr400_dcf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_icpl.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr400_u_dcf (current_cpu, idesc, 0, referenced, in_GRi, in_GRj); + } + return cycles; +#undef FLD +} + +static int +model_fr400_dcef (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_icei.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + cycles += frvbf_model_fr400_u_dcf (current_cpu, idesc, 0, referenced, in_GRi, in_GRj); + } + return cycles; +#undef FLD +} + +static int +model_fr400_witlb (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_wdtlb (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_itlbi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_dtlbi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_icpl (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_icpl.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr400_u_icpl (current_cpu, idesc, 0, referenced, in_GRi, in_GRj); + } + return cycles; +#undef FLD +} + +static int +model_fr400_dcpl (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_icpl.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr400_u_dcpl (current_cpu, idesc, 0, referenced, in_GRi, in_GRj); + } + return cycles; +#undef FLD +} + +static int +model_fr400_icul (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_jmpil.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + in_GRi = FLD (in_GRi); + referenced |= 1 << 0; + cycles += frvbf_model_fr400_u_icul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj); + } + return cycles; +#undef FLD +} + +static int +model_fr400_dcul (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_jmpil.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + in_GRi = FLD (in_GRi); + referenced |= 1 << 0; + cycles += frvbf_model_fr400_u_dcul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj); + } + return cycles; +#undef FLD +} + +static int +model_fr400_bar (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_barrier (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_membar (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_membar (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cop1 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cop2 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_clrgr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_clrfr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_clrga (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_clrfa (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_commitgr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_setlos.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_commitfr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mhsethis.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_commitga (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_commitfa (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fitos (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fditos.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fstoi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdstoi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fitod (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fitod.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fdtoi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdtoi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fditos (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fditos.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fdstoi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdstoi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_nfditos (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fditos.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_nfdstoi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdstoi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cfitos (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfitos.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cfstoi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfstoi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_nfitos (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fditos.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_nfstoi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdstoi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fmovs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fmovd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fmaddd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fdmovs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cfmovs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fnegs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fnegd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fmaddd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fdnegs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cfnegs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fabss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fabsd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fmaddd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fdabss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cfabss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fsqrts (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fdsqrts (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_nfdsqrts (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fsqrtd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fmaddd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cfsqrts (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_nfsqrts (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fadds (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fsubs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fmuls (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fdivs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_faddd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fmaddd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fsubd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fmaddd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fmuld (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fmaddd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fdivd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fmaddd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cfadds (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cfsubs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cfmuls (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cfdivs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_nfadds (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_nfsubs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_nfmuls (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_nfdivs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fcmps (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfcmps.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fcmpd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcmpd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cfcmps (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfcmps.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fdcmps (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_nfdcmps.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fmadds (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fmsubs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fmaddd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fmaddd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fmsubd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fmaddd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fdmadds (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_nfdmadds (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cfmadds (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cfmsubs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_nfmadds (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_nfmsubs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fmas (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fmss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fdmas (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmas.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fdmss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmas.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_nfdmas (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmas.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_nfdmss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmas.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cfmas (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmas.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cfmss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmas.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fmad (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fmsd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_nfmas (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_nfmss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fdadds (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fdsubs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fdmuls (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fddivs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fdsads (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fdmulcs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_nfdmulcs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_nfdadds (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_nfdsubs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_nfdmuls (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_nfddivs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_nfdsads (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_nfdcmps (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_nfdcmps.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_mhsetlos (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mhsetlos.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT out_FRkhi = -1; + INT out_FRklo = -1; + out_FRklo = FLD (out_FRklo); + referenced |= 1 << 1; + cycles += frvbf_model_fr400_u_media_hilo (current_cpu, idesc, 0, referenced, out_FRkhi, out_FRklo); + } + return cycles; +#undef FLD +} + +static int +model_fr400_mhsethis (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mhsethis.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT out_FRkhi = -1; + INT out_FRklo = -1; + out_FRkhi = FLD (out_FRkhi); + referenced |= 1 << 0; + cycles += frvbf_model_fr400_u_media_hilo (current_cpu, idesc, 0, referenced, out_FRkhi, out_FRklo); + } + return cycles; +#undef FLD +} + +static int +model_fr400_mhdsets (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mhdsets.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_mhsetloh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mhsetloh.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT out_FRkhi = -1; + INT out_FRklo = -1; + out_FRklo = FLD (out_FRklo); + referenced |= 1 << 1; + cycles += frvbf_model_fr400_u_media_hilo (current_cpu, idesc, 0, referenced, out_FRkhi, out_FRklo); + } + return cycles; +#undef FLD +} + +static int +model_fr400_mhsethih (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mhsethih.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT out_FRkhi = -1; + INT out_FRklo = -1; + out_FRkhi = FLD (out_FRkhi); + referenced |= 1 << 0; + cycles += frvbf_model_fr400_u_media_hilo (current_cpu, idesc, 0, referenced, out_FRkhi, out_FRklo); + } + return cycles; +#undef FLD +} + +static int +model_fr400_mhdseth (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mhdseth.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_mand (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mwcut.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_mor (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mwcut.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_mxor (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mwcut.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cmand (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmand.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_FRintk = FLD (out_FRintk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 4)) referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cmor (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmand.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_FRintk = FLD (out_FRintk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 4)) referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cmxor (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmand.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_FRintk = FLD (out_FRintk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 4)) referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_mnot (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mcut.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRintj = FLD (in_FRintj); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cmnot (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmand.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRintj = FLD (in_FRintj); + out_FRintk = FLD (out_FRintk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 3)) referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_mrotli (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mwcuti.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_media_3 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_mrotri (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mwcuti.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_media_3 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_mwcut (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mwcut.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_media_3 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_mwcuti (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mwcuti.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_media_3 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_mcut (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mcut.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ACC40Si = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_FRintk = -1; + in_ACC40Si = FLD (in_ACC40Si); + in_FRintj = FLD (in_FRintj); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr400_u_media_4 (current_cpu, idesc, 0, referenced, in_ACC40Si, in_FRintj, out_ACC40Sk, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_mcuti (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mcuti.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ACC40Si = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_FRintk = -1; + in_ACC40Si = FLD (in_ACC40Si); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr400_u_media_4 (current_cpu, idesc, 0, referenced, in_ACC40Si, in_FRintj, out_ACC40Sk, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_mcutss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mcut.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ACC40Si = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_FRintk = -1; + in_ACC40Si = FLD (in_ACC40Si); + in_FRintj = FLD (in_FRintj); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr400_u_media_4 (current_cpu, idesc, 0, referenced, in_ACC40Si, in_FRintj, out_ACC40Sk, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_mcutssi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mcuti.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ACC40Si = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_FRintk = -1; + in_ACC40Si = FLD (in_ACC40Si); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr400_u_media_4 (current_cpu, idesc, 0, referenced, in_ACC40Si, in_FRintj, out_ACC40Sk, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_mdcutssi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdcutssi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ACC40Si = -1; + INT out_FRintk = -1; + in_ACC40Si = FLD (in_ACC40Si); + out_FRintk = FLD (out_FRintkeven); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + cycles += frvbf_model_fr400_u_media_4_acc_dual (current_cpu, idesc, 0, referenced, in_ACC40Si, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_maveh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mwcut.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_msllhi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_msllhi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_media_3 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_msrlhi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_msllhi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_media_3 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_msrahi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_msllhi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr400_u_media_6 (current_cpu, idesc, 0, referenced, in_FRinti, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_mdrotli (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdrotli.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRintieven); + out_FRintk = FLD (out_FRintkeven); + cycles += frvbf_model_fr400_u_media_3_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_mcplhi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mcplhi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr400_u_media_3_dual (current_cpu, idesc, 0, referenced, in_FRinti, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_mcpli (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mwcuti.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr400_u_media_3_dual (current_cpu, idesc, 0, referenced, in_FRinti, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_msaths (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr400_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_mqsaths (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + out_FRintk = FLD (out_FRintkeven); + cycles += frvbf_model_fr400_u_media_1_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_msathu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr400_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_mcmpsh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mcmpsh.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FCCk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_FCCk = FLD (out_FCCk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 9)) referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_media_7 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FCCk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_mcmpuh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mcmpsh.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FCCk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_FCCk = FLD (out_FCCk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 9)) referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_media_7 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FCCk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_mabshs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mabshs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRintj = FLD (in_FRintj); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_maddhss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr400_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_maddhus (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr400_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_msubhss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr400_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_msubhus (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr400_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cmaddhss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + cycles += frvbf_model_fr400_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cmaddhus (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + cycles += frvbf_model_fr400_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cmsubhss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + cycles += frvbf_model_fr400_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cmsubhus (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + cycles += frvbf_model_fr400_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_mqaddhss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + out_FRintk = FLD (out_FRintkeven); + cycles += frvbf_model_fr400_u_media_1_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_mqaddhus (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + out_FRintk = FLD (out_FRintkeven); + cycles += frvbf_model_fr400_u_media_1_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_mqsubhss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + out_FRintk = FLD (out_FRintkeven); + cycles += frvbf_model_fr400_u_media_1_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_mqsubhus (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + out_FRintk = FLD (out_FRintkeven); + cycles += frvbf_model_fr400_u_media_1_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cmqaddhss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + out_FRintk = FLD (out_FRintkeven); + cycles += frvbf_model_fr400_u_media_1_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cmqaddhus (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + out_FRintk = FLD (out_FRintkeven); + cycles += frvbf_model_fr400_u_media_1_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cmqsubhss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + out_FRintk = FLD (out_FRintkeven); + cycles += frvbf_model_fr400_u_media_1_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cmqsubhus (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + out_FRintk = FLD (out_FRintkeven); + cycles += frvbf_model_fr400_u_media_1_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_maddaccs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdasaccs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ACC40Si = -1; + INT out_ACC40Sk = -1; + in_ACC40Si = FLD (in_ACC40Si); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 4)) referenced |= 1 << 1; + cycles += frvbf_model_fr400_u_media_2_acc (current_cpu, idesc, 0, referenced, in_ACC40Si, out_ACC40Sk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_msubaccs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdasaccs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ACC40Si = -1; + INT out_ACC40Sk = -1; + in_ACC40Si = FLD (in_ACC40Si); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 4)) referenced |= 1 << 1; + cycles += frvbf_model_fr400_u_media_2_acc (current_cpu, idesc, 0, referenced, in_ACC40Si, out_ACC40Sk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_mdaddaccs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdasaccs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ACC40Si = -1; + INT out_ACC40Sk = -1; + in_ACC40Si = FLD (in_ACC40Si); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 6)) referenced |= 1 << 1; + cycles += frvbf_model_fr400_u_media_2_acc_dual (current_cpu, idesc, 0, referenced, in_ACC40Si, out_ACC40Sk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_mdsubaccs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdasaccs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ACC40Si = -1; + INT out_ACC40Sk = -1; + in_ACC40Si = FLD (in_ACC40Si); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 6)) referenced |= 1 << 1; + cycles += frvbf_model_fr400_u_media_2_acc_dual (current_cpu, idesc, 0, referenced, in_ACC40Si, out_ACC40Sk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_masaccs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdasaccs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ACC40Si = -1; + INT out_ACC40Sk = -1; + in_ACC40Si = FLD (in_ACC40Si); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 4)) referenced |= 1 << 1; + cycles += frvbf_model_fr400_u_media_2_add_sub (current_cpu, idesc, 0, referenced, in_ACC40Si, out_ACC40Sk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_mdasaccs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdasaccs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ACC40Si = -1; + INT out_ACC40Sk = -1; + in_ACC40Si = FLD (in_ACC40Si); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 6)) referenced |= 1 << 1; + cycles += frvbf_model_fr400_u_media_2_add_sub_dual (current_cpu, idesc, 0, referenced, in_ACC40Si, out_ACC40Sk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_mmulhs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 9)) referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_mmulhu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 9)) referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_mmulxhs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 9)) referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_mmulxhu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 9)) referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cmmulhs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 11)) referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cmmulhu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 11)) referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_mqmulhs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + out_ACC40Sk = FLD (out_ACC40Sk); + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + if (insn_referenced & (1 << 13)) referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_mqmulhu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + out_ACC40Sk = FLD (out_ACC40Sk); + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + if (insn_referenced & (1 << 13)) referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_mqmulxhs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + out_ACC40Sk = FLD (out_ACC40Sk); + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + if (insn_referenced & (1 << 13)) referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_mqmulxhu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + out_ACC40Sk = FLD (out_ACC40Sk); + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + if (insn_referenced & (1 << 13)) referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cmqmulhs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + out_ACC40Sk = FLD (out_ACC40Sk); + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + if (insn_referenced & (1 << 15)) referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cmqmulhu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + out_ACC40Sk = FLD (out_ACC40Sk); + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + if (insn_referenced & (1 << 15)) referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_mmachs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 11)) referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_mmachu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Uk = FLD (out_ACC40Uk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 11)) referenced |= 1 << 3; + cycles += frvbf_model_fr400_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_mmrdhs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 11)) referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_mmrdhu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Uk = FLD (out_ACC40Uk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 11)) referenced |= 1 << 3; + cycles += frvbf_model_fr400_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cmmachs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 2)) referenced |= 1 << 0; + if (insn_referenced & (1 << 3)) referenced |= 1 << 1; + if (insn_referenced & (1 << 13)) referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cmmachu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Uk = FLD (out_ACC40Uk); + if (insn_referenced & (1 << 2)) referenced |= 1 << 0; + if (insn_referenced & (1 << 3)) referenced |= 1 << 1; + if (insn_referenced & (1 << 13)) referenced |= 1 << 3; + cycles += frvbf_model_fr400_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_mqmachs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + out_ACC40Sk = FLD (out_ACC40Sk); + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + if (insn_referenced & (1 << 17)) referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_mqmachu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + out_ACC40Uk = FLD (out_ACC40Uk); + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + if (insn_referenced & (1 << 17)) referenced |= 1 << 3; + cycles += frvbf_model_fr400_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cmqmachs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + out_ACC40Sk = FLD (out_ACC40Sk); + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + if (insn_referenced & (1 << 19)) referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cmqmachu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + out_ACC40Uk = FLD (out_ACC40Uk); + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + if (insn_referenced & (1 << 19)) referenced |= 1 << 3; + cycles += frvbf_model_fr400_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_mqxmachs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + out_ACC40Sk = FLD (out_ACC40Sk); + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + if (insn_referenced & (1 << 17)) referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_mqxmacxhs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + out_ACC40Sk = FLD (out_ACC40Sk); + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + if (insn_referenced & (1 << 17)) referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_mqmacxhs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + out_ACC40Sk = FLD (out_ACC40Sk); + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + if (insn_referenced & (1 << 17)) referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_mcpxrs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 9)) referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_mcpxru (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 9)) referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_mcpxis (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 9)) referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_mcpxiu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 9)) referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cmcpxrs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 11)) referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cmcpxru (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 11)) referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cmcpxis (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 11)) referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cmcpxiu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 11)) referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_mqcpxrs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + out_ACC40Sk = FLD (out_ACC40Sk); + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + if (insn_referenced & (1 << 13)) referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_mqcpxru (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + out_ACC40Sk = FLD (out_ACC40Sk); + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + if (insn_referenced & (1 << 13)) referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_mqcpxis (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + out_ACC40Sk = FLD (out_ACC40Sk); + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + if (insn_referenced & (1 << 13)) referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_mqcpxiu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + out_ACC40Sk = FLD (out_ACC40Sk); + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + if (insn_referenced & (1 << 13)) referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_mexpdhw (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmexpdhw.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + cycles += frvbf_model_fr400_u_media_3 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cmexpdhw (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmexpdhw.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + cycles += frvbf_model_fr400_u_media_3 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_mexpdhd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmexpdhd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT out_FRintk = -1; + out_FRintk = FLD (out_FRintkeven); + cycles += frvbf_model_fr400_u_media_dual_expand (current_cpu, idesc, 0, referenced, in_FRinti, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cmexpdhd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmexpdhd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT out_FRintk = -1; + out_FRintk = FLD (out_FRintkeven); + cycles += frvbf_model_fr400_u_media_dual_expand (current_cpu, idesc, 0, referenced, in_FRinti, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_mpackh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + cycles += frvbf_model_fr400_u_media_3 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_mdpackh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdpackh.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + out_FRintk = FLD (out_FRintkeven); + cycles += frvbf_model_fr400_u_media_3_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_munpackh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_munpackh.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + out_FRintk = FLD (out_FRintkeven); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + cycles += frvbf_model_fr400_u_media_dual_expand (current_cpu, idesc, 0, referenced, in_FRinti, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_mdunpackh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdunpackh.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_mbtoh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmbtoh.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT out_FRintk = -1; + out_FRintk = FLD (out_FRintkeven); + cycles += frvbf_model_fr400_u_media_dual_expand (current_cpu, idesc, 0, referenced, in_FRinti, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cmbtoh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmbtoh.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT out_FRintk = -1; + out_FRintk = FLD (out_FRintkeven); + cycles += frvbf_model_fr400_u_media_dual_expand (current_cpu, idesc, 0, referenced, in_FRinti, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_mhtob (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmhtob.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRintj = -1; + INT out_FRintk = -1; + out_FRintk = FLD (out_FRintk); + in_FRintj = FLD (in_FRintjeven); + referenced |= 1 << 1; + cycles += frvbf_model_fr400_u_media_dual_htob (current_cpu, idesc, 0, referenced, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cmhtob (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmhtob.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRintj = -1; + INT out_FRintk = -1; + out_FRintk = FLD (out_FRintk); + in_FRintj = FLD (in_FRintjeven); + referenced |= 1 << 1; + cycles += frvbf_model_fr400_u_media_dual_htob (current_cpu, idesc, 0, referenced, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_mbtohe (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmbtohe.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_cmbtohe (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmbtohe.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_mnop (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_mclracc_0 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdasaccs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ACC40Si = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_FRintk = -1; + cycles += frvbf_model_fr400_u_media_4 (current_cpu, idesc, 0, referenced, in_ACC40Si, in_FRintj, out_ACC40Sk, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_mclracc_1 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdasaccs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ACC40Si = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_FRintk = -1; + cycles += frvbf_model_fr400_u_media_4 (current_cpu, idesc, 0, referenced, in_ACC40Si, in_FRintj, out_ACC40Sk, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_mrdacc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mcuti.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ACC40Si = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_FRintk = -1; + in_ACC40Si = FLD (in_ACC40Si); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr400_u_media_4 (current_cpu, idesc, 0, referenced, in_ACC40Si, in_FRintj, out_ACC40Sk, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_mrdaccg (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mrdaccg.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ACCGi = -1; + INT in_FRinti = -1; + INT out_ACCGk = -1; + INT out_FRintk = -1; + in_ACCGi = FLD (in_ACCGi); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr400_u_media_4_accg (current_cpu, idesc, 0, referenced, in_ACCGi, in_FRinti, out_ACCGk, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_mwtacc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ACC40Si = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_FRintk = -1; + out_ACC40Sk = FLD (out_ACC40Sk); + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_media_4 (current_cpu, idesc, 0, referenced, in_ACC40Si, in_FRintj, out_ACC40Sk, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_mwtaccg (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mwtaccg.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ACCGi = -1; + INT in_FRinti = -1; + INT out_ACCGk = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + out_ACCGk = FLD (out_ACCGk); + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_media_4_accg (current_cpu, idesc, 0, referenced, in_ACCGi, in_FRinti, out_ACCGk, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr400_mcop1 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_mcop2 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_fnop (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_add (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_sub (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_and (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_or (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_xor (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_not (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_scutss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_sdiv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_nsdiv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_udiv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_nudiv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_smul (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_umul (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_smu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smass.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_smass (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smass.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_smsss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smass.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_sll (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_srl (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_sra (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_slass (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_scutss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_scutss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_scan (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cadd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_csub (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cand (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cor (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cxor (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cnot (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_csmul (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_csdiv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cudiv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_csll (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_csrl (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_csra (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cscan (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_addcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_subcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_andcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_orcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_xorcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_sllcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_srlcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_sracc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_smulcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_umulcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_caddcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_caddcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_csubcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_caddcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_csmulcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_csmulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_candcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_caddcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_corcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_caddcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cxorcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_caddcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_csllcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_caddcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_csrlcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_caddcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_csracc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_caddcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_addx (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_subx (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_addxcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_subxcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_addss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_subss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_addi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_subi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_andi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_ori (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_xori (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_sdivi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_nsdivi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_udivi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_nudivi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_smuli (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smuli.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_umuli (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smuli.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_slli (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_srli (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_srai (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_scani (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_addicc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_subicc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_andicc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_oricc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_xoricc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_smulicc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_umulicc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_sllicc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_srlicc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_sraicc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_addxi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_subxi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_addxicc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_subxicc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cmpb (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cmpba (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_setlo (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_setlo.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_sethi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_sethi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_setlos (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_setlos.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_ldsb (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_ldub (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_ldsh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_lduh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_ld (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_ldbf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_ldhf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_ldf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_ldc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_nldsb (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_nldub (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_nldsh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_nlduh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_nld (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_nldbf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_nldhf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_nldf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_ldd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_lddf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_lddc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_lddcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_nldd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_nlddf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_ldq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_ldqf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_ldqc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_nldq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_nldqf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_ldsbu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_ldubu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_ldshu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_lduhu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_ldu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_nldsbu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_nldubu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_nldshu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_nlduhu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_nldu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_ldbfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_ldhfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_ldfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_ldcu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_nldbfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_nldhfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_nldfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_lddu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_nlddu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_lddfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_lddcu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_lddcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_nlddfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_ldqu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_nldqu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_ldqfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_ldqcu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_nldqfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_ldsbi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_ldshi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_ldi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_ldubi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_lduhi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_ldbfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldbfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_ldhfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldbfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_ldfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldbfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_nldsbi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_nldubi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_nldshi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_nlduhi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_nldi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_nldbfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldbfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_nldhfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldbfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_nldfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldbfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_lddi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smuli.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_lddfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_lddfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_nlddi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smuli.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_nlddfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_lddfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_ldqi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_ldqfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_nldqfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_stb (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_sth (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_st (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_stbf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_sthf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_stf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_stc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_rstb (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_rsth (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_rst (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_rstbf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_rsthf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_rstf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_std (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_stdf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_stdc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_rstd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_rstdf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_stq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_stqf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_stqc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_rstq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_rstqf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_stbu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_sthu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_stu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_stbfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_sthfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_stfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_stcu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_stdu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_stdfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_stdcu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_stqu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_stqfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_stqcu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cldsb (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cldub (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cldsh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_clduh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cld (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cldbf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cldhf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cldf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cldd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_clddf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cldq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cldsbu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cldubu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cldshu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_clduhu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cldu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cldbfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cldhfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cldfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_clddu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_clddfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cldqu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cstb (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_csth (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cst (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cstbf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_csthf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cstf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cstd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cstdf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cstq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cstbu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_csthu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cstu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cstbfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_csthfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cstfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cstdu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cstdfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_stbi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_sthi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_sti (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_stbfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stbfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_sthfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stbfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_stfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stbfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_stdi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_stdfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_stqi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_stqfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_swap (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_swapi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cswap (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_movgf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmovgfd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_movfg (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmovfgd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_movgfd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmovgfd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_movfgd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmovfgd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_movgfq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_movgfq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_movfgq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_movfgq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cmovgf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmovgfd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cmovfg (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmovfgd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cmovgfd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmovgfd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cmovfgd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmovfgd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_movgs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_movgs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_movsg (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_movsg.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_bra (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_bno (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_beq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_bne (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_ble (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_bgt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_blt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_bge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_bls (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_bhi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_bc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_bnc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_bn (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_bp (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_bv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_bnv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fbra (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fbno (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fbne (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fbeq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fblg (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fbue (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fbul (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fbge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fblt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fbuge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fbug (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fble (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fbgt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fbule (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fbu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fbo (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_bctrlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_bralr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_bnolr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_beqlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_bnelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_blelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_bgtlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_bltlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_bgelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_blslr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_bhilr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_bclr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_bnclr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_bnlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_bplr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_bvlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_bnvlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fbralr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fbnolr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fbeqlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fbnelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fblglr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fbuelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fbullr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fbgelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fbltlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fbugelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fbuglr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fblelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fbgtlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fbulelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fbulr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fbolr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_bcralr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_bcnolr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_bceqlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_bcnelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_bclelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_bcgtlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_bcltlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_bcgelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_bclslr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_bchilr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_bcclr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_bcnclr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_bcnlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_bcplr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_bcvlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_bcnvlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fcbralr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fcbnolr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fcbeqlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fcbnelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fcblglr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fcbuelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fcbullr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fcbgelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fcbltlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fcbugelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fcbuglr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fcblelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fcbgtlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fcbulelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fcbulr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fcbolr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_jmpl (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cjmpl.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_calll (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cjmpl.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_jmpil (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_jmpil.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_callil (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_jmpil.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_call (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_call.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_rett (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_rett.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_rei (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_tra (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_tno (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_teq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_tne (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_tle (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_tgt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_tlt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_tge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_tls (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_thi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_tc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_tnc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_tn (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_tp (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_tv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_tnv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_ftra (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_ftno (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_ftne (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fteq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_ftlg (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_ftue (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_ftul (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_ftge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_ftlt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_ftuge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_ftug (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_ftle (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_ftgt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_ftule (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_ftu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fto (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_tira (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_tino (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_tieq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_tine (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_tile (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_tigt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_tilt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_tige (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_tils (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_tihi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_tic (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_tinc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_tin (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_tip (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_tiv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_tinv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_ftira (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_ftino (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_ftine (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_ftieq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_ftilg (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_ftiue (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_ftiul (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_ftige (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_ftilt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_ftiuge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_ftiug (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_ftile (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_ftigt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_ftiule (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_ftiu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_ftio (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_break (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_break.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_mtrap (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_andcr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_andcr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_orcr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_andcr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_xorcr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_andcr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_nandcr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_andcr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_norcr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_andcr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_andncr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_andcr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_orncr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_andcr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_nandncr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_andcr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_norncr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_andcr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_notcr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_andcr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_ckra (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_ckno (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_ckeq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_ckne (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_ckle (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_ckgt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cklt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_ckge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_ckls (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_ckhi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_ckc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cknc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_ckn (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_ckp (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_ckv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cknv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fckra (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fckno (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fckne (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fckeq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fcklg (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fckue (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fckul (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fckge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fcklt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fckuge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fckug (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fckle (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fckgt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fckule (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fcku (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fcko (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cckra (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cckno (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cckeq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cckne (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cckle (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cckgt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_ccklt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cckge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cckls (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cckhi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cckc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_ccknc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cckn (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cckp (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cckv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_ccknv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cfckra (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cfckno (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cfckne (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cfckeq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cfcklg (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cfckue (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cfckul (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cfckge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cfcklt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cfckuge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cfckug (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cfckle (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cfckgt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cfckule (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cfcku (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cfcko (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cjmpl (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cjmpl.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_ccalll (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cjmpl.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_ici (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_icpl.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_dci (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_icpl.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_icei (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_icei.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_dcei (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_icei.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_dcf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_icpl.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_dcef (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_icei.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_witlb (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_wdtlb (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_itlbi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_dtlbi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_icpl (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_icpl.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_dcpl (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_icpl.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_icul (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_jmpil.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_dcul (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_jmpil.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_bar (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_membar (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cop1 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cop2 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_clrgr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_clrfr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_clrga (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_clrfa (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_commitgr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_setlos.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_commitfr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mhsethis.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_commitga (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_commitfa (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fitos (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fditos.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fstoi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdstoi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fitod (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fitod.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fdtoi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdtoi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fditos (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fditos.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fdstoi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdstoi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_nfditos (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fditos.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_nfdstoi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdstoi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cfitos (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfitos.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cfstoi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfstoi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_nfitos (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fditos.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_nfstoi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdstoi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fmovs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fmovd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fmaddd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fdmovs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cfmovs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fnegs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fnegd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fmaddd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fdnegs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cfnegs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fabss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fabsd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fmaddd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fdabss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cfabss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fsqrts (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fdsqrts (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_nfdsqrts (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fsqrtd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fmaddd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cfsqrts (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_nfsqrts (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fadds (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fsubs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fmuls (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fdivs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_faddd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fmaddd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fsubd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fmaddd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fmuld (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fmaddd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fdivd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fmaddd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cfadds (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cfsubs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cfmuls (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cfdivs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_nfadds (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_nfsubs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_nfmuls (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_nfdivs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fcmps (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfcmps.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fcmpd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcmpd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cfcmps (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfcmps.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fdcmps (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_nfdcmps.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fmadds (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fmsubs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fmaddd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fmaddd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fmsubd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fmaddd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fdmadds (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_nfdmadds (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cfmadds (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cfmsubs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_nfmadds (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_nfmsubs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fmas (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fmss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fdmas (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmas.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fdmss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmas.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_nfdmas (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmas.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_nfdmss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmas.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cfmas (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmas.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cfmss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmas.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fmad (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fmsd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_nfmas (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_nfmss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fdadds (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fdsubs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fdmuls (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fddivs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fdsads (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fdmulcs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_nfdmulcs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_nfdadds (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_nfdsubs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_nfdmuls (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_nfddivs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_nfdsads (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_nfdcmps (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_nfdcmps.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_mhsetlos (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mhsetlos.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_mhsethis (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mhsethis.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_mhdsets (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mhdsets.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_mhsetloh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mhsetloh.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_mhsethih (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mhsethih.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_mhdseth (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mhdseth.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_mand (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mwcut.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_mor (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mwcut.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_mxor (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mwcut.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cmand (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmand.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cmor (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmand.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cmxor (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmand.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_mnot (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mcut.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cmnot (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmand.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_mrotli (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mwcuti.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_mrotri (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mwcuti.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_mwcut (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mwcut.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_mwcuti (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mwcuti.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_mcut (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mcut.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_mcuti (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mcuti.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_mcutss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mcut.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_mcutssi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mcuti.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_mdcutssi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdcutssi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_maveh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mwcut.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_msllhi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_msllhi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_msrlhi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_msllhi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_msrahi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_msllhi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_mdrotli (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdrotli.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_mcplhi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mcplhi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_mcpli (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mwcuti.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_msaths (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_mqsaths (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_msathu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_mcmpsh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mcmpsh.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_mcmpuh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mcmpsh.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_mabshs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mabshs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_maddhss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_maddhus (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_msubhss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_msubhus (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cmaddhss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cmaddhus (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cmsubhss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cmsubhus (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_mqaddhss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_mqaddhus (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_mqsubhss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_mqsubhus (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cmqaddhss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cmqaddhus (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cmqsubhss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cmqsubhus (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_maddaccs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdasaccs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_msubaccs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdasaccs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_mdaddaccs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdasaccs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_mdsubaccs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdasaccs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_masaccs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdasaccs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_mdasaccs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdasaccs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_mmulhs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_mmulhu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_mmulxhs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_mmulxhu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cmmulhs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cmmulhu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_mqmulhs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_mqmulhu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_mqmulxhs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_mqmulxhu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cmqmulhs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cmqmulhu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_mmachs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_mmachu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_mmrdhs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_mmrdhu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cmmachs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cmmachu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_mqmachs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_mqmachu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cmqmachs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cmqmachu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_mqxmachs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_mqxmacxhs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_mqmacxhs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_mcpxrs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_mcpxru (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_mcpxis (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_mcpxiu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cmcpxrs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cmcpxru (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cmcpxis (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cmcpxiu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_mqcpxrs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_mqcpxru (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_mqcpxis (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_mqcpxiu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_mexpdhw (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmexpdhw.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cmexpdhw (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmexpdhw.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_mexpdhd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmexpdhd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cmexpdhd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmexpdhd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_mpackh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_mdpackh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdpackh.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_munpackh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_munpackh.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_mdunpackh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdunpackh.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_mbtoh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmbtoh.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cmbtoh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmbtoh.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_mhtob (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmhtob.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cmhtob (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmhtob.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_mbtohe (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmbtohe.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_cmbtohe (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmbtohe.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_mnop (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_mclracc_0 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdasaccs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_mclracc_1 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdasaccs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_mrdacc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mcuti.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_mrdaccg (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mrdaccg.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_mwtacc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_mwtaccg (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mwtaccg.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_mcop1 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_mcop2 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_fnop (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +/* We assume UNIT_NONE == 0 because the tables don't always terminate + entries with it. */ + +/* Model timing data for `frv'. */ + +static const INSN_TIMING frv_timing[] = { + { FRVBF_INSN_X_INVALID, 0, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_X_AFTER, 0, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_X_BEFORE, 0, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_X_CTI_CHAIN, 0, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_X_CHAIN, 0, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_X_BEGIN, 0, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ADD, model_frv_add, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SUB, model_frv_sub, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_AND, model_frv_and, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_OR, model_frv_or, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_XOR, model_frv_xor, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NOT, model_frv_not, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SDIV, model_frv_sdiv, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NSDIV, model_frv_nsdiv, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_UDIV, model_frv_udiv, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NUDIV, model_frv_nudiv, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SMUL, model_frv_smul, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_UMUL, model_frv_umul, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SMU, model_frv_smu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SMASS, model_frv_smass, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SMSSS, model_frv_smsss, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SLL, model_frv_sll, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SRL, model_frv_srl, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SRA, model_frv_sra, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SLASS, model_frv_slass, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SCUTSS, model_frv_scutss, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SCAN, model_frv_scan, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CADD, model_frv_cadd, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSUB, model_frv_csub, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CAND, model_frv_cand, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_COR, model_frv_cor, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CXOR, model_frv_cxor, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CNOT, model_frv_cnot, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSMUL, model_frv_csmul, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSDIV, model_frv_csdiv, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CUDIV, model_frv_cudiv, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSLL, model_frv_csll, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSRL, model_frv_csrl, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSRA, model_frv_csra, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSCAN, model_frv_cscan, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ADDCC, model_frv_addcc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SUBCC, model_frv_subcc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ANDCC, model_frv_andcc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ORCC, model_frv_orcc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_XORCC, model_frv_xorcc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SLLCC, model_frv_sllcc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SRLCC, model_frv_srlcc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SRACC, model_frv_sracc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SMULCC, model_frv_smulcc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_UMULCC, model_frv_umulcc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CADDCC, model_frv_caddcc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSUBCC, model_frv_csubcc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSMULCC, model_frv_csmulcc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CANDCC, model_frv_candcc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CORCC, model_frv_corcc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CXORCC, model_frv_cxorcc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSLLCC, model_frv_csllcc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSRLCC, model_frv_csrlcc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSRACC, model_frv_csracc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ADDX, model_frv_addx, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SUBX, model_frv_subx, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ADDXCC, model_frv_addxcc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SUBXCC, model_frv_subxcc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ADDSS, model_frv_addss, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SUBSS, model_frv_subss, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ADDI, model_frv_addi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SUBI, model_frv_subi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ANDI, model_frv_andi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ORI, model_frv_ori, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_XORI, model_frv_xori, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SDIVI, model_frv_sdivi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NSDIVI, model_frv_nsdivi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_UDIVI, model_frv_udivi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NUDIVI, model_frv_nudivi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SMULI, model_frv_smuli, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_UMULI, model_frv_umuli, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SLLI, model_frv_slli, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SRLI, model_frv_srli, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SRAI, model_frv_srai, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SCANI, model_frv_scani, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ADDICC, model_frv_addicc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SUBICC, model_frv_subicc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ANDICC, model_frv_andicc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ORICC, model_frv_oricc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_XORICC, model_frv_xoricc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SMULICC, model_frv_smulicc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_UMULICC, model_frv_umulicc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SLLICC, model_frv_sllicc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SRLICC, model_frv_srlicc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SRAICC, model_frv_sraicc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ADDXI, model_frv_addxi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SUBXI, model_frv_subxi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ADDXICC, model_frv_addxicc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SUBXICC, model_frv_subxicc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMPB, model_frv_cmpb, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMPBA, model_frv_cmpba, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SETLO, model_frv_setlo, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SETHI, model_frv_sethi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SETLOS, model_frv_setlos, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDSB, model_frv_ldsb, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDUB, model_frv_ldub, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDSH, model_frv_ldsh, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDUH, model_frv_lduh, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LD, model_frv_ld, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDBF, model_frv_ldbf, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDHF, model_frv_ldhf, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDF, model_frv_ldf, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDC, model_frv_ldc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDSB, model_frv_nldsb, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDUB, model_frv_nldub, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDSH, model_frv_nldsh, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDUH, model_frv_nlduh, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLD, model_frv_nld, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDBF, model_frv_nldbf, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDHF, model_frv_nldhf, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDF, model_frv_nldf, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDD, model_frv_ldd, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDDF, model_frv_lddf, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDDC, model_frv_lddc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDD, model_frv_nldd, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDDF, model_frv_nlddf, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDQ, model_frv_ldq, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDQF, model_frv_ldqf, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDQC, model_frv_ldqc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDQ, model_frv_nldq, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDQF, model_frv_nldqf, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDSBU, model_frv_ldsbu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDUBU, model_frv_ldubu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDSHU, model_frv_ldshu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDUHU, model_frv_lduhu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDU, model_frv_ldu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDSBU, model_frv_nldsbu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDUBU, model_frv_nldubu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDSHU, model_frv_nldshu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDUHU, model_frv_nlduhu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDU, model_frv_nldu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDBFU, model_frv_ldbfu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDHFU, model_frv_ldhfu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDFU, model_frv_ldfu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDCU, model_frv_ldcu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDBFU, model_frv_nldbfu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDHFU, model_frv_nldhfu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDFU, model_frv_nldfu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDDU, model_frv_lddu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDDU, model_frv_nlddu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDDFU, model_frv_lddfu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDDCU, model_frv_lddcu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDDFU, model_frv_nlddfu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDQU, model_frv_ldqu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDQU, model_frv_nldqu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDQFU, model_frv_ldqfu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDQCU, model_frv_ldqcu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDQFU, model_frv_nldqfu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDSBI, model_frv_ldsbi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDSHI, model_frv_ldshi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDI, model_frv_ldi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDUBI, model_frv_ldubi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDUHI, model_frv_lduhi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDBFI, model_frv_ldbfi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDHFI, model_frv_ldhfi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDFI, model_frv_ldfi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDSBI, model_frv_nldsbi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDUBI, model_frv_nldubi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDSHI, model_frv_nldshi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDUHI, model_frv_nlduhi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDI, model_frv_nldi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDBFI, model_frv_nldbfi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDHFI, model_frv_nldhfi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDFI, model_frv_nldfi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDDI, model_frv_lddi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDDFI, model_frv_lddfi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDDI, model_frv_nlddi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDDFI, model_frv_nlddfi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDQI, model_frv_ldqi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDQFI, model_frv_ldqfi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDQFI, model_frv_nldqfi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STB, model_frv_stb, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STH, model_frv_sth, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ST, model_frv_st, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STBF, model_frv_stbf, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STHF, model_frv_sthf, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STF, model_frv_stf, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STC, model_frv_stc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_RSTB, model_frv_rstb, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_RSTH, model_frv_rsth, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_RST, model_frv_rst, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_RSTBF, model_frv_rstbf, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_RSTHF, model_frv_rsthf, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_RSTF, model_frv_rstf, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STD, model_frv_std, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STDF, model_frv_stdf, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STDC, model_frv_stdc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_RSTD, model_frv_rstd, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_RSTDF, model_frv_rstdf, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STQ, model_frv_stq, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STQF, model_frv_stqf, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STQC, model_frv_stqc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_RSTQ, model_frv_rstq, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_RSTQF, model_frv_rstqf, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STBU, model_frv_stbu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STHU, model_frv_sthu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STU, model_frv_stu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STBFU, model_frv_stbfu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STHFU, model_frv_sthfu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STFU, model_frv_stfu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STCU, model_frv_stcu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STDU, model_frv_stdu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STDFU, model_frv_stdfu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STDCU, model_frv_stdcu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STQU, model_frv_stqu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STQFU, model_frv_stqfu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STQCU, model_frv_stqcu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLDSB, model_frv_cldsb, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLDUB, model_frv_cldub, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLDSH, model_frv_cldsh, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLDUH, model_frv_clduh, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLD, model_frv_cld, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLDBF, model_frv_cldbf, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLDHF, model_frv_cldhf, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLDF, model_frv_cldf, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLDD, model_frv_cldd, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLDDF, model_frv_clddf, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLDQ, model_frv_cldq, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLDSBU, model_frv_cldsbu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLDUBU, model_frv_cldubu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLDSHU, model_frv_cldshu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLDUHU, model_frv_clduhu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLDU, model_frv_cldu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLDBFU, model_frv_cldbfu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLDHFU, model_frv_cldhfu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLDFU, model_frv_cldfu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLDDU, model_frv_clddu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLDDFU, model_frv_clddfu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLDQU, model_frv_cldqu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSTB, model_frv_cstb, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSTH, model_frv_csth, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CST, model_frv_cst, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSTBF, model_frv_cstbf, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSTHF, model_frv_csthf, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSTF, model_frv_cstf, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSTD, model_frv_cstd, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSTDF, model_frv_cstdf, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSTQ, model_frv_cstq, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSTBU, model_frv_cstbu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSTHU, model_frv_csthu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSTU, model_frv_cstu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSTBFU, model_frv_cstbfu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSTHFU, model_frv_csthfu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSTFU, model_frv_cstfu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSTDU, model_frv_cstdu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSTDFU, model_frv_cstdfu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STBI, model_frv_stbi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STHI, model_frv_sthi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STI, model_frv_sti, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STBFI, model_frv_stbfi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STHFI, model_frv_sthfi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STFI, model_frv_stfi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STDI, model_frv_stdi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STDFI, model_frv_stdfi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STQI, model_frv_stqi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STQFI, model_frv_stqfi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SWAP, model_frv_swap, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SWAPI, model_frv_swapi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSWAP, model_frv_cswap, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MOVGF, model_frv_movgf, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MOVFG, model_frv_movfg, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MOVGFD, model_frv_movgfd, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MOVFGD, model_frv_movfgd, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MOVGFQ, model_frv_movgfq, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MOVFGQ, model_frv_movfgq, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMOVGF, model_frv_cmovgf, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMOVFG, model_frv_cmovfg, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMOVGFD, model_frv_cmovgfd, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMOVFGD, model_frv_cmovfgd, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MOVGS, model_frv_movgs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MOVSG, model_frv_movsg, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BRA, model_frv_bra, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BNO, model_frv_bno, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BEQ, model_frv_beq, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BNE, model_frv_bne, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BLE, model_frv_ble, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BGT, model_frv_bgt, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BLT, model_frv_blt, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BGE, model_frv_bge, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BLS, model_frv_bls, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BHI, model_frv_bhi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BC, model_frv_bc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BNC, model_frv_bnc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BN, model_frv_bn, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BP, model_frv_bp, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BV, model_frv_bv, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BNV, model_frv_bnv, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBRA, model_frv_fbra, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBNO, model_frv_fbno, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBNE, model_frv_fbne, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBEQ, model_frv_fbeq, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBLG, model_frv_fblg, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBUE, model_frv_fbue, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBUL, model_frv_fbul, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBGE, model_frv_fbge, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBLT, model_frv_fblt, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBUGE, model_frv_fbuge, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBUG, model_frv_fbug, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBLE, model_frv_fble, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBGT, model_frv_fbgt, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBULE, model_frv_fbule, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBU, model_frv_fbu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBO, model_frv_fbo, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BCTRLR, model_frv_bctrlr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BRALR, model_frv_bralr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BNOLR, model_frv_bnolr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BEQLR, model_frv_beqlr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BNELR, model_frv_bnelr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BLELR, model_frv_blelr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BGTLR, model_frv_bgtlr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BLTLR, model_frv_bltlr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BGELR, model_frv_bgelr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BLSLR, model_frv_blslr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BHILR, model_frv_bhilr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BCLR, model_frv_bclr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BNCLR, model_frv_bnclr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BNLR, model_frv_bnlr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BPLR, model_frv_bplr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BVLR, model_frv_bvlr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BNVLR, model_frv_bnvlr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBRALR, model_frv_fbralr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBNOLR, model_frv_fbnolr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBEQLR, model_frv_fbeqlr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBNELR, model_frv_fbnelr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBLGLR, model_frv_fblglr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBUELR, model_frv_fbuelr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBULLR, model_frv_fbullr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBGELR, model_frv_fbgelr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBLTLR, model_frv_fbltlr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBUGELR, model_frv_fbugelr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBUGLR, model_frv_fbuglr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBLELR, model_frv_fblelr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBGTLR, model_frv_fbgtlr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBULELR, model_frv_fbulelr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBULR, model_frv_fbulr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBOLR, model_frv_fbolr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BCRALR, model_frv_bcralr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BCNOLR, model_frv_bcnolr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BCEQLR, model_frv_bceqlr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BCNELR, model_frv_bcnelr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BCLELR, model_frv_bclelr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BCGTLR, model_frv_bcgtlr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BCLTLR, model_frv_bcltlr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BCGELR, model_frv_bcgelr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BCLSLR, model_frv_bclslr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BCHILR, model_frv_bchilr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BCCLR, model_frv_bcclr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BCNCLR, model_frv_bcnclr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BCNLR, model_frv_bcnlr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BCPLR, model_frv_bcplr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BCVLR, model_frv_bcvlr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BCNVLR, model_frv_bcnvlr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCBRALR, model_frv_fcbralr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCBNOLR, model_frv_fcbnolr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCBEQLR, model_frv_fcbeqlr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCBNELR, model_frv_fcbnelr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCBLGLR, model_frv_fcblglr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCBUELR, model_frv_fcbuelr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCBULLR, model_frv_fcbullr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCBGELR, model_frv_fcbgelr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCBLTLR, model_frv_fcbltlr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCBUGELR, model_frv_fcbugelr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCBUGLR, model_frv_fcbuglr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCBLELR, model_frv_fcblelr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCBGTLR, model_frv_fcbgtlr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCBULELR, model_frv_fcbulelr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCBULR, model_frv_fcbulr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCBOLR, model_frv_fcbolr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_JMPL, model_frv_jmpl, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CALLL, model_frv_calll, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_JMPIL, model_frv_jmpil, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CALLIL, model_frv_callil, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CALL, model_frv_call, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_RETT, model_frv_rett, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_REI, model_frv_rei, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TRA, model_frv_tra, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TNO, model_frv_tno, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TEQ, model_frv_teq, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TNE, model_frv_tne, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TLE, model_frv_tle, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TGT, model_frv_tgt, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TLT, model_frv_tlt, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TGE, model_frv_tge, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TLS, model_frv_tls, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_THI, model_frv_thi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TC, model_frv_tc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TNC, model_frv_tnc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TN, model_frv_tn, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TP, model_frv_tp, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TV, model_frv_tv, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TNV, model_frv_tnv, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTRA, model_frv_ftra, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTNO, model_frv_ftno, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTNE, model_frv_ftne, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTEQ, model_frv_fteq, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTLG, model_frv_ftlg, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTUE, model_frv_ftue, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTUL, model_frv_ftul, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTGE, model_frv_ftge, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTLT, model_frv_ftlt, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTUGE, model_frv_ftuge, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTUG, model_frv_ftug, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTLE, model_frv_ftle, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTGT, model_frv_ftgt, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTULE, model_frv_ftule, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTU, model_frv_ftu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTO, model_frv_fto, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TIRA, model_frv_tira, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TINO, model_frv_tino, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TIEQ, model_frv_tieq, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TINE, model_frv_tine, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TILE, model_frv_tile, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TIGT, model_frv_tigt, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TILT, model_frv_tilt, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TIGE, model_frv_tige, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TILS, model_frv_tils, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TIHI, model_frv_tihi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TIC, model_frv_tic, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TINC, model_frv_tinc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TIN, model_frv_tin, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TIP, model_frv_tip, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TIV, model_frv_tiv, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TINV, model_frv_tinv, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTIRA, model_frv_ftira, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTINO, model_frv_ftino, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTINE, model_frv_ftine, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTIEQ, model_frv_ftieq, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTILG, model_frv_ftilg, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTIUE, model_frv_ftiue, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTIUL, model_frv_ftiul, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTIGE, model_frv_ftige, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTILT, model_frv_ftilt, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTIUGE, model_frv_ftiuge, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTIUG, model_frv_ftiug, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTILE, model_frv_ftile, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTIGT, model_frv_ftigt, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTIULE, model_frv_ftiule, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTIU, model_frv_ftiu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTIO, model_frv_ftio, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BREAK, model_frv_break, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MTRAP, model_frv_mtrap, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ANDCR, model_frv_andcr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ORCR, model_frv_orcr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_XORCR, model_frv_xorcr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NANDCR, model_frv_nandcr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NORCR, model_frv_norcr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ANDNCR, model_frv_andncr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ORNCR, model_frv_orncr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NANDNCR, model_frv_nandncr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NORNCR, model_frv_norncr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NOTCR, model_frv_notcr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CKRA, model_frv_ckra, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CKNO, model_frv_ckno, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CKEQ, model_frv_ckeq, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CKNE, model_frv_ckne, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CKLE, model_frv_ckle, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CKGT, model_frv_ckgt, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CKLT, model_frv_cklt, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CKGE, model_frv_ckge, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CKLS, model_frv_ckls, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CKHI, model_frv_ckhi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CKC, model_frv_ckc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CKNC, model_frv_cknc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CKN, model_frv_ckn, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CKP, model_frv_ckp, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CKV, model_frv_ckv, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CKNV, model_frv_cknv, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCKRA, model_frv_fckra, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCKNO, model_frv_fckno, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCKNE, model_frv_fckne, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCKEQ, model_frv_fckeq, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCKLG, model_frv_fcklg, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCKUE, model_frv_fckue, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCKUL, model_frv_fckul, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCKGE, model_frv_fckge, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCKLT, model_frv_fcklt, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCKUGE, model_frv_fckuge, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCKUG, model_frv_fckug, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCKLE, model_frv_fckle, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCKGT, model_frv_fckgt, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCKULE, model_frv_fckule, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCKU, model_frv_fcku, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCKO, model_frv_fcko, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CCKRA, model_frv_cckra, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CCKNO, model_frv_cckno, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CCKEQ, model_frv_cckeq, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CCKNE, model_frv_cckne, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CCKLE, model_frv_cckle, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CCKGT, model_frv_cckgt, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CCKLT, model_frv_ccklt, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CCKGE, model_frv_cckge, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CCKLS, model_frv_cckls, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CCKHI, model_frv_cckhi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CCKC, model_frv_cckc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CCKNC, model_frv_ccknc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CCKN, model_frv_cckn, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CCKP, model_frv_cckp, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CCKV, model_frv_cckv, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CCKNV, model_frv_ccknv, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFCKRA, model_frv_cfckra, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFCKNO, model_frv_cfckno, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFCKNE, model_frv_cfckne, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFCKEQ, model_frv_cfckeq, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFCKLG, model_frv_cfcklg, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFCKUE, model_frv_cfckue, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFCKUL, model_frv_cfckul, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFCKGE, model_frv_cfckge, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFCKLT, model_frv_cfcklt, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFCKUGE, model_frv_cfckuge, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFCKUG, model_frv_cfckug, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFCKLE, model_frv_cfckle, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFCKGT, model_frv_cfckgt, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFCKULE, model_frv_cfckule, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFCKU, model_frv_cfcku, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFCKO, model_frv_cfcko, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CJMPL, model_frv_cjmpl, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CCALLL, model_frv_ccalll, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ICI, model_frv_ici, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_DCI, model_frv_dci, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ICEI, model_frv_icei, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_DCEI, model_frv_dcei, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_DCF, model_frv_dcf, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_DCEF, model_frv_dcef, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_WITLB, model_frv_witlb, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_WDTLB, model_frv_wdtlb, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ITLBI, model_frv_itlbi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_DTLBI, model_frv_dtlbi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ICPL, model_frv_icpl, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_DCPL, model_frv_dcpl, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ICUL, model_frv_icul, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_DCUL, model_frv_dcul, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BAR, model_frv_bar, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MEMBAR, model_frv_membar, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_COP1, model_frv_cop1, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_COP2, model_frv_cop2, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLRGR, model_frv_clrgr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLRFR, model_frv_clrfr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLRGA, model_frv_clrga, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLRFA, model_frv_clrfa, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_COMMITGR, model_frv_commitgr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_COMMITFR, model_frv_commitfr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_COMMITGA, model_frv_commitga, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_COMMITFA, model_frv_commitfa, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FITOS, model_frv_fitos, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FSTOI, model_frv_fstoi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FITOD, model_frv_fitod, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDTOI, model_frv_fdtoi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDITOS, model_frv_fditos, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDSTOI, model_frv_fdstoi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFDITOS, model_frv_nfditos, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFDSTOI, model_frv_nfdstoi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFITOS, model_frv_cfitos, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFSTOI, model_frv_cfstoi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFITOS, model_frv_nfitos, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFSTOI, model_frv_nfstoi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FMOVS, model_frv_fmovs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FMOVD, model_frv_fmovd, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDMOVS, model_frv_fdmovs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFMOVS, model_frv_cfmovs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FNEGS, model_frv_fnegs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FNEGD, model_frv_fnegd, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDNEGS, model_frv_fdnegs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFNEGS, model_frv_cfnegs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FABSS, model_frv_fabss, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FABSD, model_frv_fabsd, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDABSS, model_frv_fdabss, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFABSS, model_frv_cfabss, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FSQRTS, model_frv_fsqrts, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDSQRTS, model_frv_fdsqrts, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFDSQRTS, model_frv_nfdsqrts, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FSQRTD, model_frv_fsqrtd, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFSQRTS, model_frv_cfsqrts, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFSQRTS, model_frv_nfsqrts, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FADDS, model_frv_fadds, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FSUBS, model_frv_fsubs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FMULS, model_frv_fmuls, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDIVS, model_frv_fdivs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FADDD, model_frv_faddd, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FSUBD, model_frv_fsubd, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FMULD, model_frv_fmuld, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDIVD, model_frv_fdivd, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFADDS, model_frv_cfadds, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFSUBS, model_frv_cfsubs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFMULS, model_frv_cfmuls, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFDIVS, model_frv_cfdivs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFADDS, model_frv_nfadds, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFSUBS, model_frv_nfsubs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFMULS, model_frv_nfmuls, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFDIVS, model_frv_nfdivs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCMPS, model_frv_fcmps, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCMPD, model_frv_fcmpd, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFCMPS, model_frv_cfcmps, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDCMPS, model_frv_fdcmps, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FMADDS, model_frv_fmadds, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FMSUBS, model_frv_fmsubs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FMADDD, model_frv_fmaddd, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FMSUBD, model_frv_fmsubd, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDMADDS, model_frv_fdmadds, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFDMADDS, model_frv_nfdmadds, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFMADDS, model_frv_cfmadds, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFMSUBS, model_frv_cfmsubs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFMADDS, model_frv_nfmadds, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFMSUBS, model_frv_nfmsubs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FMAS, model_frv_fmas, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FMSS, model_frv_fmss, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDMAS, model_frv_fdmas, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDMSS, model_frv_fdmss, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFDMAS, model_frv_nfdmas, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFDMSS, model_frv_nfdmss, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFMAS, model_frv_cfmas, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFMSS, model_frv_cfmss, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FMAD, model_frv_fmad, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FMSD, model_frv_fmsd, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFMAS, model_frv_nfmas, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFMSS, model_frv_nfmss, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDADDS, model_frv_fdadds, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDSUBS, model_frv_fdsubs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDMULS, model_frv_fdmuls, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDDIVS, model_frv_fddivs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDSADS, model_frv_fdsads, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDMULCS, model_frv_fdmulcs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFDMULCS, model_frv_nfdmulcs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFDADDS, model_frv_nfdadds, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFDSUBS, model_frv_nfdsubs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFDMULS, model_frv_nfdmuls, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFDDIVS, model_frv_nfddivs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFDSADS, model_frv_nfdsads, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFDCMPS, model_frv_nfdcmps, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MHSETLOS, model_frv_mhsetlos, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MHSETHIS, model_frv_mhsethis, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MHDSETS, model_frv_mhdsets, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MHSETLOH, model_frv_mhsetloh, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MHSETHIH, model_frv_mhsethih, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MHDSETH, model_frv_mhdseth, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MAND, model_frv_mand, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MOR, model_frv_mor, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MXOR, model_frv_mxor, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMAND, model_frv_cmand, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMOR, model_frv_cmor, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMXOR, model_frv_cmxor, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MNOT, model_frv_mnot, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMNOT, model_frv_cmnot, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MROTLI, model_frv_mrotli, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MROTRI, model_frv_mrotri, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MWCUT, model_frv_mwcut, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MWCUTI, model_frv_mwcuti, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MCUT, model_frv_mcut, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MCUTI, model_frv_mcuti, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MCUTSS, model_frv_mcutss, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MCUTSSI, model_frv_mcutssi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MDCUTSSI, model_frv_mdcutssi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MAVEH, model_frv_maveh, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MSLLHI, model_frv_msllhi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MSRLHI, model_frv_msrlhi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MSRAHI, model_frv_msrahi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MDROTLI, model_frv_mdrotli, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MCPLHI, model_frv_mcplhi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MCPLI, model_frv_mcpli, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MSATHS, model_frv_msaths, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQSATHS, model_frv_mqsaths, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MSATHU, model_frv_msathu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MCMPSH, model_frv_mcmpsh, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MCMPUH, model_frv_mcmpuh, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MABSHS, model_frv_mabshs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MADDHSS, model_frv_maddhss, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MADDHUS, model_frv_maddhus, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MSUBHSS, model_frv_msubhss, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MSUBHUS, model_frv_msubhus, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMADDHSS, model_frv_cmaddhss, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMADDHUS, model_frv_cmaddhus, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMSUBHSS, model_frv_cmsubhss, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMSUBHUS, model_frv_cmsubhus, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQADDHSS, model_frv_mqaddhss, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQADDHUS, model_frv_mqaddhus, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQSUBHSS, model_frv_mqsubhss, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQSUBHUS, model_frv_mqsubhus, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMQADDHSS, model_frv_cmqaddhss, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMQADDHUS, model_frv_cmqaddhus, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMQSUBHSS, model_frv_cmqsubhss, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMQSUBHUS, model_frv_cmqsubhus, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MADDACCS, model_frv_maddaccs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MSUBACCS, model_frv_msubaccs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MDADDACCS, model_frv_mdaddaccs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MDSUBACCS, model_frv_mdsubaccs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MASACCS, model_frv_masaccs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MDASACCS, model_frv_mdasaccs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MMULHS, model_frv_mmulhs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MMULHU, model_frv_mmulhu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MMULXHS, model_frv_mmulxhs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MMULXHU, model_frv_mmulxhu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMMULHS, model_frv_cmmulhs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMMULHU, model_frv_cmmulhu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQMULHS, model_frv_mqmulhs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQMULHU, model_frv_mqmulhu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQMULXHS, model_frv_mqmulxhs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQMULXHU, model_frv_mqmulxhu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMQMULHS, model_frv_cmqmulhs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMQMULHU, model_frv_cmqmulhu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MMACHS, model_frv_mmachs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MMACHU, model_frv_mmachu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MMRDHS, model_frv_mmrdhs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MMRDHU, model_frv_mmrdhu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMMACHS, model_frv_cmmachs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMMACHU, model_frv_cmmachu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQMACHS, model_frv_mqmachs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQMACHU, model_frv_mqmachu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMQMACHS, model_frv_cmqmachs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMQMACHU, model_frv_cmqmachu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQXMACHS, model_frv_mqxmachs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQXMACXHS, model_frv_mqxmacxhs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQMACXHS, model_frv_mqmacxhs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MCPXRS, model_frv_mcpxrs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MCPXRU, model_frv_mcpxru, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MCPXIS, model_frv_mcpxis, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MCPXIU, model_frv_mcpxiu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMCPXRS, model_frv_cmcpxrs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMCPXRU, model_frv_cmcpxru, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMCPXIS, model_frv_cmcpxis, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMCPXIU, model_frv_cmcpxiu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQCPXRS, model_frv_mqcpxrs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQCPXRU, model_frv_mqcpxru, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQCPXIS, model_frv_mqcpxis, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQCPXIU, model_frv_mqcpxiu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MEXPDHW, model_frv_mexpdhw, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMEXPDHW, model_frv_cmexpdhw, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MEXPDHD, model_frv_mexpdhd, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMEXPDHD, model_frv_cmexpdhd, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MPACKH, model_frv_mpackh, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MDPACKH, model_frv_mdpackh, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MUNPACKH, model_frv_munpackh, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MDUNPACKH, model_frv_mdunpackh, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MBTOH, model_frv_mbtoh, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMBTOH, model_frv_cmbtoh, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MHTOB, model_frv_mhtob, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMHTOB, model_frv_cmhtob, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MBTOHE, model_frv_mbtohe, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMBTOHE, model_frv_cmbtohe, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MNOP, model_frv_mnop, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MCLRACC_0, model_frv_mclracc_0, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MCLRACC_1, model_frv_mclracc_1, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MRDACC, model_frv_mrdacc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MRDACCG, model_frv_mrdaccg, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MWTACC, model_frv_mwtacc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MWTACCG, model_frv_mwtaccg, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MCOP1, model_frv_mcop1, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MCOP2, model_frv_mcop2, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FNOP, model_frv_fnop, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, +}; + +/* Model timing data for `fr550'. */ + +static const INSN_TIMING fr550_timing[] = { + { FRVBF_INSN_X_INVALID, 0, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_X_AFTER, 0, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_X_BEFORE, 0, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_X_CTI_CHAIN, 0, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_X_CHAIN, 0, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_X_BEGIN, 0, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ADD, model_fr550_add, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SUB, model_fr550_sub, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_AND, model_fr550_and, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_OR, model_fr550_or, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_XOR, model_fr550_xor, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_NOT, model_fr550_not, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SDIV, model_fr550_sdiv, { { (int) UNIT_FR550_U_IDIV, 1, 1 } } }, + { FRVBF_INSN_NSDIV, model_fr550_nsdiv, { { (int) UNIT_FR550_U_IDIV, 1, 1 } } }, + { FRVBF_INSN_UDIV, model_fr550_udiv, { { (int) UNIT_FR550_U_IDIV, 1, 1 } } }, + { FRVBF_INSN_NUDIV, model_fr550_nudiv, { { (int) UNIT_FR550_U_IDIV, 1, 1 } } }, + { FRVBF_INSN_SMUL, model_fr550_smul, { { (int) UNIT_FR550_U_IMUL, 1, 1 } } }, + { FRVBF_INSN_UMUL, model_fr550_umul, { { (int) UNIT_FR550_U_IMUL, 1, 1 } } }, + { FRVBF_INSN_SMU, model_fr550_smu, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SMASS, model_fr550_smass, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SMSSS, model_fr550_smsss, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SLL, model_fr550_sll, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SRL, model_fr550_srl, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SRA, model_fr550_sra, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SLASS, model_fr550_slass, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SCUTSS, model_fr550_scutss, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SCAN, model_fr550_scan, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_CADD, model_fr550_cadd, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_CSUB, model_fr550_csub, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_CAND, model_fr550_cand, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_COR, model_fr550_cor, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_CXOR, model_fr550_cxor, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_CNOT, model_fr550_cnot, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_CSMUL, model_fr550_csmul, { { (int) UNIT_FR550_U_IMUL, 1, 1 } } }, + { FRVBF_INSN_CSDIV, model_fr550_csdiv, { { (int) UNIT_FR550_U_IDIV, 1, 1 } } }, + { FRVBF_INSN_CUDIV, model_fr550_cudiv, { { (int) UNIT_FR550_U_IDIV, 1, 1 } } }, + { FRVBF_INSN_CSLL, model_fr550_csll, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_CSRL, model_fr550_csrl, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_CSRA, model_fr550_csra, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_CSCAN, model_fr550_cscan, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_ADDCC, model_fr550_addcc, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SUBCC, model_fr550_subcc, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_ANDCC, model_fr550_andcc, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_ORCC, model_fr550_orcc, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_XORCC, model_fr550_xorcc, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SLLCC, model_fr550_sllcc, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SRLCC, model_fr550_srlcc, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SRACC, model_fr550_sracc, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SMULCC, model_fr550_smulcc, { { (int) UNIT_FR550_U_IMUL, 1, 1 } } }, + { FRVBF_INSN_UMULCC, model_fr550_umulcc, { { (int) UNIT_FR550_U_IMUL, 1, 1 } } }, + { FRVBF_INSN_CADDCC, model_fr550_caddcc, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_CSUBCC, model_fr550_csubcc, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_CSMULCC, model_fr550_csmulcc, { { (int) UNIT_FR550_U_IMUL, 1, 1 } } }, + { FRVBF_INSN_CANDCC, model_fr550_candcc, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_CORCC, model_fr550_corcc, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_CXORCC, model_fr550_cxorcc, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_CSLLCC, model_fr550_csllcc, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_CSRLCC, model_fr550_csrlcc, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_CSRACC, model_fr550_csracc, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_ADDX, model_fr550_addx, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SUBX, model_fr550_subx, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_ADDXCC, model_fr550_addxcc, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SUBXCC, model_fr550_subxcc, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_ADDSS, model_fr550_addss, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SUBSS, model_fr550_subss, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ADDI, model_fr550_addi, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SUBI, model_fr550_subi, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_ANDI, model_fr550_andi, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_ORI, model_fr550_ori, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_XORI, model_fr550_xori, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SDIVI, model_fr550_sdivi, { { (int) UNIT_FR550_U_IDIV, 1, 1 } } }, + { FRVBF_INSN_NSDIVI, model_fr550_nsdivi, { { (int) UNIT_FR550_U_IDIV, 1, 1 } } }, + { FRVBF_INSN_UDIVI, model_fr550_udivi, { { (int) UNIT_FR550_U_IDIV, 1, 1 } } }, + { FRVBF_INSN_NUDIVI, model_fr550_nudivi, { { (int) UNIT_FR550_U_IDIV, 1, 1 } } }, + { FRVBF_INSN_SMULI, model_fr550_smuli, { { (int) UNIT_FR550_U_IMUL, 1, 1 } } }, + { FRVBF_INSN_UMULI, model_fr550_umuli, { { (int) UNIT_FR550_U_IMUL, 1, 1 } } }, + { FRVBF_INSN_SLLI, model_fr550_slli, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SRLI, model_fr550_srli, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SRAI, model_fr550_srai, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SCANI, model_fr550_scani, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_ADDICC, model_fr550_addicc, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SUBICC, model_fr550_subicc, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_ANDICC, model_fr550_andicc, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_ORICC, model_fr550_oricc, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_XORICC, model_fr550_xoricc, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SMULICC, model_fr550_smulicc, { { (int) UNIT_FR550_U_IMUL, 1, 1 } } }, + { FRVBF_INSN_UMULICC, model_fr550_umulicc, { { (int) UNIT_FR550_U_IMUL, 1, 1 } } }, + { FRVBF_INSN_SLLICC, model_fr550_sllicc, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SRLICC, model_fr550_srlicc, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SRAICC, model_fr550_sraicc, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_ADDXI, model_fr550_addxi, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SUBXI, model_fr550_subxi, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_ADDXICC, model_fr550_addxicc, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SUBXICC, model_fr550_subxicc, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_CMPB, model_fr550_cmpb, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_CMPBA, model_fr550_cmpba, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SETLO, model_fr550_setlo, { { (int) UNIT_FR550_U_SET_HILO, 1, 1 } } }, + { FRVBF_INSN_SETHI, model_fr550_sethi, { { (int) UNIT_FR550_U_SET_HILO, 1, 1 } } }, + { FRVBF_INSN_SETLOS, model_fr550_setlos, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_LDSB, model_fr550_ldsb, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDUB, model_fr550_ldub, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDSH, model_fr550_ldsh, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDUH, model_fr550_lduh, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LD, model_fr550_ld, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDBF, model_fr550_ldbf, { { (int) UNIT_FR550_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDHF, model_fr550_ldhf, { { (int) UNIT_FR550_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDF, model_fr550_ldf, { { (int) UNIT_FR550_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDC, model_fr550_ldc, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDSB, model_fr550_nldsb, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_NLDUB, model_fr550_nldub, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_NLDSH, model_fr550_nldsh, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_NLDUH, model_fr550_nlduh, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_NLD, model_fr550_nld, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_NLDBF, model_fr550_nldbf, { { (int) UNIT_FR550_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_NLDHF, model_fr550_nldhf, { { (int) UNIT_FR550_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_NLDF, model_fr550_nldf, { { (int) UNIT_FR550_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDD, model_fr550_ldd, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDDF, model_fr550_lddf, { { (int) UNIT_FR550_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDDC, model_fr550_lddc, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDD, model_fr550_nldd, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_NLDDF, model_fr550_nlddf, { { (int) UNIT_FR550_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDQ, model_fr550_ldq, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDQF, model_fr550_ldqf, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDQC, model_fr550_ldqc, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDQ, model_fr550_nldq, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDQF, model_fr550_nldqf, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDSBU, model_fr550_ldsbu, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDUBU, model_fr550_ldubu, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDSHU, model_fr550_ldshu, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDUHU, model_fr550_lduhu, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDU, model_fr550_ldu, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_NLDSBU, model_fr550_nldsbu, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_NLDUBU, model_fr550_nldubu, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_NLDSHU, model_fr550_nldshu, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_NLDUHU, model_fr550_nlduhu, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_NLDU, model_fr550_nldu, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDBFU, model_fr550_ldbfu, { { (int) UNIT_FR550_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDHFU, model_fr550_ldhfu, { { (int) UNIT_FR550_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDFU, model_fr550_ldfu, { { (int) UNIT_FR550_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDCU, model_fr550_ldcu, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDBFU, model_fr550_nldbfu, { { (int) UNIT_FR550_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_NLDHFU, model_fr550_nldhfu, { { (int) UNIT_FR550_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_NLDFU, model_fr550_nldfu, { { (int) UNIT_FR550_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDDU, model_fr550_lddu, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_NLDDU, model_fr550_nlddu, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDDFU, model_fr550_lddfu, { { (int) UNIT_FR550_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDDCU, model_fr550_lddcu, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDDFU, model_fr550_nlddfu, { { (int) UNIT_FR550_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDQU, model_fr550_ldqu, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDQU, model_fr550_nldqu, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDQFU, model_fr550_ldqfu, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDQCU, model_fr550_ldqcu, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDQFU, model_fr550_nldqfu, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDSBI, model_fr550_ldsbi, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDSHI, model_fr550_ldshi, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDI, model_fr550_ldi, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDUBI, model_fr550_ldubi, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDUHI, model_fr550_lduhi, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDBFI, model_fr550_ldbfi, { { (int) UNIT_FR550_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDHFI, model_fr550_ldhfi, { { (int) UNIT_FR550_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDFI, model_fr550_ldfi, { { (int) UNIT_FR550_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_NLDSBI, model_fr550_nldsbi, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_NLDUBI, model_fr550_nldubi, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_NLDSHI, model_fr550_nldshi, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_NLDUHI, model_fr550_nlduhi, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_NLDI, model_fr550_nldi, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_NLDBFI, model_fr550_nldbfi, { { (int) UNIT_FR550_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_NLDHFI, model_fr550_nldhfi, { { (int) UNIT_FR550_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_NLDFI, model_fr550_nldfi, { { (int) UNIT_FR550_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDDI, model_fr550_lddi, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDDFI, model_fr550_lddfi, { { (int) UNIT_FR550_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_NLDDI, model_fr550_nlddi, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_NLDDFI, model_fr550_nlddfi, { { (int) UNIT_FR550_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDQI, model_fr550_ldqi, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDQFI, model_fr550_ldqfi, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDQFI, model_fr550_nldqfi, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STB, model_fr550_stb, { { (int) UNIT_FR550_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_STH, model_fr550_sth, { { (int) UNIT_FR550_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_ST, model_fr550_st, { { (int) UNIT_FR550_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_STBF, model_fr550_stbf, { { (int) UNIT_FR550_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_STHF, model_fr550_sthf, { { (int) UNIT_FR550_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_STF, model_fr550_stf, { { (int) UNIT_FR550_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_STC, model_fr550_stc, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_RSTB, model_fr550_rstb, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_RSTH, model_fr550_rsth, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_RST, model_fr550_rst, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_RSTBF, model_fr550_rstbf, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_RSTHF, model_fr550_rsthf, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_RSTF, model_fr550_rstf, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STD, model_fr550_std, { { (int) UNIT_FR550_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_STDF, model_fr550_stdf, { { (int) UNIT_FR550_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_STDC, model_fr550_stdc, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_RSTD, model_fr550_rstd, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_RSTDF, model_fr550_rstdf, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STQ, model_fr550_stq, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STQF, model_fr550_stqf, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STQC, model_fr550_stqc, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_RSTQ, model_fr550_rstq, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_RSTQF, model_fr550_rstqf, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STBU, model_fr550_stbu, { { (int) UNIT_FR550_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_STHU, model_fr550_sthu, { { (int) UNIT_FR550_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_STU, model_fr550_stu, { { (int) UNIT_FR550_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_STBFU, model_fr550_stbfu, { { (int) UNIT_FR550_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_STHFU, model_fr550_sthfu, { { (int) UNIT_FR550_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_STFU, model_fr550_stfu, { { (int) UNIT_FR550_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_STCU, model_fr550_stcu, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STDU, model_fr550_stdu, { { (int) UNIT_FR550_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_STDFU, model_fr550_stdfu, { { (int) UNIT_FR550_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_STDCU, model_fr550_stdcu, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STQU, model_fr550_stqu, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STQFU, model_fr550_stqfu, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STQCU, model_fr550_stqcu, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLDSB, model_fr550_cldsb, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDUB, model_fr550_cldub, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDSH, model_fr550_cldsh, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDUH, model_fr550_clduh, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLD, model_fr550_cld, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDBF, model_fr550_cldbf, { { (int) UNIT_FR550_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDHF, model_fr550_cldhf, { { (int) UNIT_FR550_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDF, model_fr550_cldf, { { (int) UNIT_FR550_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDD, model_fr550_cldd, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDDF, model_fr550_clddf, { { (int) UNIT_FR550_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDQ, model_fr550_cldq, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLDSBU, model_fr550_cldsbu, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDUBU, model_fr550_cldubu, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDSHU, model_fr550_cldshu, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDUHU, model_fr550_clduhu, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDU, model_fr550_cldu, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDBFU, model_fr550_cldbfu, { { (int) UNIT_FR550_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDHFU, model_fr550_cldhfu, { { (int) UNIT_FR550_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDFU, model_fr550_cldfu, { { (int) UNIT_FR550_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDDU, model_fr550_clddu, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDDFU, model_fr550_clddfu, { { (int) UNIT_FR550_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDQU, model_fr550_cldqu, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSTB, model_fr550_cstb, { { (int) UNIT_FR550_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_CSTH, model_fr550_csth, { { (int) UNIT_FR550_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_CST, model_fr550_cst, { { (int) UNIT_FR550_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_CSTBF, model_fr550_cstbf, { { (int) UNIT_FR550_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_CSTHF, model_fr550_csthf, { { (int) UNIT_FR550_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_CSTF, model_fr550_cstf, { { (int) UNIT_FR550_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_CSTD, model_fr550_cstd, { { (int) UNIT_FR550_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_CSTDF, model_fr550_cstdf, { { (int) UNIT_FR550_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_CSTQ, model_fr550_cstq, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSTBU, model_fr550_cstbu, { { (int) UNIT_FR550_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_CSTHU, model_fr550_csthu, { { (int) UNIT_FR550_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_CSTU, model_fr550_cstu, { { (int) UNIT_FR550_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_CSTBFU, model_fr550_cstbfu, { { (int) UNIT_FR550_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_CSTHFU, model_fr550_csthfu, { { (int) UNIT_FR550_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_CSTFU, model_fr550_cstfu, { { (int) UNIT_FR550_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_CSTDU, model_fr550_cstdu, { { (int) UNIT_FR550_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_CSTDFU, model_fr550_cstdfu, { { (int) UNIT_FR550_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_STBI, model_fr550_stbi, { { (int) UNIT_FR550_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_STHI, model_fr550_sthi, { { (int) UNIT_FR550_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_STI, model_fr550_sti, { { (int) UNIT_FR550_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_STBFI, model_fr550_stbfi, { { (int) UNIT_FR550_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_STHFI, model_fr550_sthfi, { { (int) UNIT_FR550_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_STFI, model_fr550_stfi, { { (int) UNIT_FR550_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_STDI, model_fr550_stdi, { { (int) UNIT_FR550_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_STDFI, model_fr550_stdfi, { { (int) UNIT_FR550_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_STQI, model_fr550_stqi, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STQFI, model_fr550_stqfi, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SWAP, model_fr550_swap, { { (int) UNIT_FR550_U_SWAP, 1, 1 } } }, + { FRVBF_INSN_SWAPI, model_fr550_swapi, { { (int) UNIT_FR550_U_SWAP, 1, 1 } } }, + { FRVBF_INSN_CSWAP, model_fr550_cswap, { { (int) UNIT_FR550_U_SWAP, 1, 1 } } }, + { FRVBF_INSN_MOVGF, model_fr550_movgf, { { (int) UNIT_FR550_U_GR2FR, 1, 1 } } }, + { FRVBF_INSN_MOVFG, model_fr550_movfg, { { (int) UNIT_FR550_U_FR2GR, 1, 1 } } }, + { FRVBF_INSN_MOVGFD, model_fr550_movgfd, { { (int) UNIT_FR550_U_GR2FR, 1, 1 } } }, + { FRVBF_INSN_MOVFGD, model_fr550_movfgd, { { (int) UNIT_FR550_U_FR2GR, 1, 1 } } }, + { FRVBF_INSN_MOVGFQ, model_fr550_movgfq, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MOVFGQ, model_fr550_movfgq, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMOVGF, model_fr550_cmovgf, { { (int) UNIT_FR550_U_GR2FR, 1, 1 } } }, + { FRVBF_INSN_CMOVFG, model_fr550_cmovfg, { { (int) UNIT_FR550_U_FR2GR, 1, 1 } } }, + { FRVBF_INSN_CMOVGFD, model_fr550_cmovgfd, { { (int) UNIT_FR550_U_GR2FR, 1, 1 } } }, + { FRVBF_INSN_CMOVFGD, model_fr550_cmovfgd, { { (int) UNIT_FR550_U_FR2GR, 1, 1 } } }, + { FRVBF_INSN_MOVGS, model_fr550_movgs, { { (int) UNIT_FR550_U_GR2SPR, 1, 1 } } }, + { FRVBF_INSN_MOVSG, model_fr550_movsg, { { (int) UNIT_FR550_U_SPR2GR, 1, 1 } } }, + { FRVBF_INSN_BRA, model_fr550_bra, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BNO, model_fr550_bno, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BEQ, model_fr550_beq, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BNE, model_fr550_bne, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BLE, model_fr550_ble, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BGT, model_fr550_bgt, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BLT, model_fr550_blt, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BGE, model_fr550_bge, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BLS, model_fr550_bls, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BHI, model_fr550_bhi, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BC, model_fr550_bc, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BNC, model_fr550_bnc, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BN, model_fr550_bn, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BP, model_fr550_bp, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BV, model_fr550_bv, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BNV, model_fr550_bnv, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBRA, model_fr550_fbra, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBNO, model_fr550_fbno, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBNE, model_fr550_fbne, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBEQ, model_fr550_fbeq, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBLG, model_fr550_fblg, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBUE, model_fr550_fbue, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBUL, model_fr550_fbul, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBGE, model_fr550_fbge, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBLT, model_fr550_fblt, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBUGE, model_fr550_fbuge, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBUG, model_fr550_fbug, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBLE, model_fr550_fble, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBGT, model_fr550_fbgt, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBULE, model_fr550_fbule, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBU, model_fr550_fbu, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBO, model_fr550_fbo, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BCTRLR, model_fr550_bctrlr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BRALR, model_fr550_bralr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BNOLR, model_fr550_bnolr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BEQLR, model_fr550_beqlr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BNELR, model_fr550_bnelr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BLELR, model_fr550_blelr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BGTLR, model_fr550_bgtlr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BLTLR, model_fr550_bltlr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BGELR, model_fr550_bgelr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BLSLR, model_fr550_blslr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BHILR, model_fr550_bhilr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BCLR, model_fr550_bclr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BNCLR, model_fr550_bnclr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BNLR, model_fr550_bnlr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BPLR, model_fr550_bplr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BVLR, model_fr550_bvlr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BNVLR, model_fr550_bnvlr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBRALR, model_fr550_fbralr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBNOLR, model_fr550_fbnolr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBEQLR, model_fr550_fbeqlr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBNELR, model_fr550_fbnelr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBLGLR, model_fr550_fblglr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBUELR, model_fr550_fbuelr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBULLR, model_fr550_fbullr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBGELR, model_fr550_fbgelr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBLTLR, model_fr550_fbltlr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBUGELR, model_fr550_fbugelr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBUGLR, model_fr550_fbuglr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBLELR, model_fr550_fblelr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBGTLR, model_fr550_fbgtlr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBULELR, model_fr550_fbulelr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBULR, model_fr550_fbulr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBOLR, model_fr550_fbolr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BCRALR, model_fr550_bcralr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BCNOLR, model_fr550_bcnolr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BCEQLR, model_fr550_bceqlr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BCNELR, model_fr550_bcnelr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BCLELR, model_fr550_bclelr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BCGTLR, model_fr550_bcgtlr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BCLTLR, model_fr550_bcltlr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BCGELR, model_fr550_bcgelr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BCLSLR, model_fr550_bclslr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BCHILR, model_fr550_bchilr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BCCLR, model_fr550_bcclr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BCNCLR, model_fr550_bcnclr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BCNLR, model_fr550_bcnlr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BCPLR, model_fr550_bcplr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BCVLR, model_fr550_bcvlr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BCNVLR, model_fr550_bcnvlr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FCBRALR, model_fr550_fcbralr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FCBNOLR, model_fr550_fcbnolr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FCBEQLR, model_fr550_fcbeqlr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FCBNELR, model_fr550_fcbnelr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FCBLGLR, model_fr550_fcblglr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FCBUELR, model_fr550_fcbuelr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FCBULLR, model_fr550_fcbullr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FCBGELR, model_fr550_fcbgelr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FCBLTLR, model_fr550_fcbltlr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FCBUGELR, model_fr550_fcbugelr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FCBUGLR, model_fr550_fcbuglr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FCBLELR, model_fr550_fcblelr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FCBGTLR, model_fr550_fcbgtlr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FCBULELR, model_fr550_fcbulelr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FCBULR, model_fr550_fcbulr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FCBOLR, model_fr550_fcbolr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_JMPL, model_fr550_jmpl, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_CALLL, model_fr550_calll, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_JMPIL, model_fr550_jmpil, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_CALLIL, model_fr550_callil, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CALL, model_fr550_call, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_RETT, model_fr550_rett, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_REI, model_fr550_rei, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TRA, model_fr550_tra, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TNO, model_fr550_tno, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TEQ, model_fr550_teq, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TNE, model_fr550_tne, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TLE, model_fr550_tle, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TGT, model_fr550_tgt, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TLT, model_fr550_tlt, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TGE, model_fr550_tge, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TLS, model_fr550_tls, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_THI, model_fr550_thi, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TC, model_fr550_tc, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TNC, model_fr550_tnc, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TN, model_fr550_tn, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TP, model_fr550_tp, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TV, model_fr550_tv, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TNV, model_fr550_tnv, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTRA, model_fr550_ftra, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTNO, model_fr550_ftno, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTNE, model_fr550_ftne, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTEQ, model_fr550_fteq, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTLG, model_fr550_ftlg, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTUE, model_fr550_ftue, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTUL, model_fr550_ftul, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTGE, model_fr550_ftge, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTLT, model_fr550_ftlt, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTUGE, model_fr550_ftuge, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTUG, model_fr550_ftug, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTLE, model_fr550_ftle, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTGT, model_fr550_ftgt, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTULE, model_fr550_ftule, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTU, model_fr550_ftu, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTO, model_fr550_fto, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TIRA, model_fr550_tira, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TINO, model_fr550_tino, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TIEQ, model_fr550_tieq, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TINE, model_fr550_tine, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TILE, model_fr550_tile, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TIGT, model_fr550_tigt, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TILT, model_fr550_tilt, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TIGE, model_fr550_tige, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TILS, model_fr550_tils, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TIHI, model_fr550_tihi, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TIC, model_fr550_tic, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TINC, model_fr550_tinc, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TIN, model_fr550_tin, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TIP, model_fr550_tip, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TIV, model_fr550_tiv, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TINV, model_fr550_tinv, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTIRA, model_fr550_ftira, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTINO, model_fr550_ftino, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTINE, model_fr550_ftine, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTIEQ, model_fr550_ftieq, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTILG, model_fr550_ftilg, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTIUE, model_fr550_ftiue, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTIUL, model_fr550_ftiul, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTIGE, model_fr550_ftige, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTILT, model_fr550_ftilt, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTIUGE, model_fr550_ftiuge, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTIUG, model_fr550_ftiug, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTILE, model_fr550_ftile, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTIGT, model_fr550_ftigt, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTIULE, model_fr550_ftiule, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTIU, model_fr550_ftiu, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTIO, model_fr550_ftio, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_BREAK, model_fr550_break, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MTRAP, model_fr550_mtrap, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ANDCR, model_fr550_andcr, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ORCR, model_fr550_orcr, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_XORCR, model_fr550_xorcr, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NANDCR, model_fr550_nandcr, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NORCR, model_fr550_norcr, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ANDNCR, model_fr550_andncr, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ORNCR, model_fr550_orncr, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NANDNCR, model_fr550_nandncr, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NORNCR, model_fr550_norncr, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NOTCR, model_fr550_notcr, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CKRA, model_fr550_ckra, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CKNO, model_fr550_ckno, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CKEQ, model_fr550_ckeq, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CKNE, model_fr550_ckne, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CKLE, model_fr550_ckle, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CKGT, model_fr550_ckgt, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CKLT, model_fr550_cklt, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CKGE, model_fr550_ckge, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CKLS, model_fr550_ckls, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CKHI, model_fr550_ckhi, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CKC, model_fr550_ckc, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CKNC, model_fr550_cknc, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CKN, model_fr550_ckn, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CKP, model_fr550_ckp, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CKV, model_fr550_ckv, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CKNV, model_fr550_cknv, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_FCKRA, model_fr550_fckra, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_FCKNO, model_fr550_fckno, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_FCKNE, model_fr550_fckne, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_FCKEQ, model_fr550_fckeq, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_FCKLG, model_fr550_fcklg, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_FCKUE, model_fr550_fckue, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_FCKUL, model_fr550_fckul, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_FCKGE, model_fr550_fckge, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_FCKLT, model_fr550_fcklt, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_FCKUGE, model_fr550_fckuge, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_FCKUG, model_fr550_fckug, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_FCKLE, model_fr550_fckle, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_FCKGT, model_fr550_fckgt, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_FCKULE, model_fr550_fckule, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_FCKU, model_fr550_fcku, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_FCKO, model_fr550_fcko, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CCKRA, model_fr550_cckra, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CCKNO, model_fr550_cckno, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CCKEQ, model_fr550_cckeq, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CCKNE, model_fr550_cckne, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CCKLE, model_fr550_cckle, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CCKGT, model_fr550_cckgt, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CCKLT, model_fr550_ccklt, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CCKGE, model_fr550_cckge, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CCKLS, model_fr550_cckls, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CCKHI, model_fr550_cckhi, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CCKC, model_fr550_cckc, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CCKNC, model_fr550_ccknc, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CCKN, model_fr550_cckn, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CCKP, model_fr550_cckp, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CCKV, model_fr550_cckv, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CCKNV, model_fr550_ccknv, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CFCKRA, model_fr550_cfckra, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CFCKNO, model_fr550_cfckno, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CFCKNE, model_fr550_cfckne, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CFCKEQ, model_fr550_cfckeq, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CFCKLG, model_fr550_cfcklg, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CFCKUE, model_fr550_cfckue, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CFCKUL, model_fr550_cfckul, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CFCKGE, model_fr550_cfckge, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CFCKLT, model_fr550_cfcklt, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CFCKUGE, model_fr550_cfckuge, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CFCKUG, model_fr550_cfckug, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CFCKLE, model_fr550_cfckle, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CFCKGT, model_fr550_cfckgt, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CFCKULE, model_fr550_cfckule, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CFCKU, model_fr550_cfcku, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CFCKO, model_fr550_cfcko, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CJMPL, model_fr550_cjmpl, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_CCALLL, model_fr550_ccalll, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ICI, model_fr550_ici, { { (int) UNIT_FR550_U_ICI, 1, 1 } } }, + { FRVBF_INSN_DCI, model_fr550_dci, { { (int) UNIT_FR550_U_DCI, 1, 1 } } }, + { FRVBF_INSN_ICEI, model_fr550_icei, { { (int) UNIT_FR550_U_ICI, 1, 1 } } }, + { FRVBF_INSN_DCEI, model_fr550_dcei, { { (int) UNIT_FR550_U_DCI, 1, 1 } } }, + { FRVBF_INSN_DCF, model_fr550_dcf, { { (int) UNIT_FR550_U_DCF, 1, 1 } } }, + { FRVBF_INSN_DCEF, model_fr550_dcef, { { (int) UNIT_FR550_U_DCF, 1, 1 } } }, + { FRVBF_INSN_WITLB, model_fr550_witlb, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_WDTLB, model_fr550_wdtlb, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ITLBI, model_fr550_itlbi, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_DTLBI, model_fr550_dtlbi, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ICPL, model_fr550_icpl, { { (int) UNIT_FR550_U_ICPL, 1, 1 } } }, + { FRVBF_INSN_DCPL, model_fr550_dcpl, { { (int) UNIT_FR550_U_DCPL, 1, 1 } } }, + { FRVBF_INSN_ICUL, model_fr550_icul, { { (int) UNIT_FR550_U_ICUL, 1, 1 } } }, + { FRVBF_INSN_DCUL, model_fr550_dcul, { { (int) UNIT_FR550_U_DCUL, 1, 1 } } }, + { FRVBF_INSN_BAR, model_fr550_bar, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MEMBAR, model_fr550_membar, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_COP1, model_fr550_cop1, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_COP2, model_fr550_cop2, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLRGR, model_fr550_clrgr, { { (int) UNIT_FR550_U_CLRGR, 1, 1 } } }, + { FRVBF_INSN_CLRFR, model_fr550_clrfr, { { (int) UNIT_FR550_U_CLRFR, 1, 1 } } }, + { FRVBF_INSN_CLRGA, model_fr550_clrga, { { (int) UNIT_FR550_U_CLRGR, 1, 1 } } }, + { FRVBF_INSN_CLRFA, model_fr550_clrfa, { { (int) UNIT_FR550_U_CLRFR, 1, 1 } } }, + { FRVBF_INSN_COMMITGR, model_fr550_commitgr, { { (int) UNIT_FR550_U_COMMIT, 1, 1 } } }, + { FRVBF_INSN_COMMITFR, model_fr550_commitfr, { { (int) UNIT_FR550_U_COMMIT, 1, 1 } } }, + { FRVBF_INSN_COMMITGA, model_fr550_commitga, { { (int) UNIT_FR550_U_COMMIT, 1, 1 } } }, + { FRVBF_INSN_COMMITFA, model_fr550_commitfa, { { (int) UNIT_FR550_U_COMMIT, 1, 1 } } }, + { FRVBF_INSN_FITOS, model_fr550_fitos, { { (int) UNIT_FR550_U_FLOAT_CONVERT, 1, 1 } } }, + { FRVBF_INSN_FSTOI, model_fr550_fstoi, { { (int) UNIT_FR550_U_FLOAT_CONVERT, 1, 1 } } }, + { FRVBF_INSN_FITOD, model_fr550_fitod, { { (int) UNIT_FR550_U_FLOAT_CONVERT, 1, 1 } } }, + { FRVBF_INSN_FDTOI, model_fr550_fdtoi, { { (int) UNIT_FR550_U_FLOAT_CONVERT, 1, 1 } } }, + { FRVBF_INSN_FDITOS, model_fr550_fditos, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDSTOI, model_fr550_fdstoi, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFDITOS, model_fr550_nfditos, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFDSTOI, model_fr550_nfdstoi, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFITOS, model_fr550_cfitos, { { (int) UNIT_FR550_U_FLOAT_CONVERT, 1, 1 } } }, + { FRVBF_INSN_CFSTOI, model_fr550_cfstoi, { { (int) UNIT_FR550_U_FLOAT_CONVERT, 1, 1 } } }, + { FRVBF_INSN_NFITOS, model_fr550_nfitos, { { (int) UNIT_FR550_U_FLOAT_CONVERT, 1, 1 } } }, + { FRVBF_INSN_NFSTOI, model_fr550_nfstoi, { { (int) UNIT_FR550_U_FLOAT_CONVERT, 1, 1 } } }, + { FRVBF_INSN_FMOVS, model_fr550_fmovs, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FMOVD, model_fr550_fmovd, { { (int) UNIT_FR550_U_FR2FR, 1, 1 } } }, + { FRVBF_INSN_FDMOVS, model_fr550_fdmovs, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFMOVS, model_fr550_cfmovs, { { (int) UNIT_FR550_U_FR2FR, 1, 1 } } }, + { FRVBF_INSN_FNEGS, model_fr550_fnegs, { { (int) UNIT_FR550_U_FLOAT_ARITH, 1, 1 } } }, + { FRVBF_INSN_FNEGD, model_fr550_fnegd, { { (int) UNIT_FR550_U_FLOAT_ARITH, 1, 1 } } }, + { FRVBF_INSN_FDNEGS, model_fr550_fdnegs, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFNEGS, model_fr550_cfnegs, { { (int) UNIT_FR550_U_FLOAT_ARITH, 1, 1 } } }, + { FRVBF_INSN_FABSS, model_fr550_fabss, { { (int) UNIT_FR550_U_FLOAT_ARITH, 1, 1 } } }, + { FRVBF_INSN_FABSD, model_fr550_fabsd, { { (int) UNIT_FR550_U_FLOAT_ARITH, 1, 1 } } }, + { FRVBF_INSN_FDABSS, model_fr550_fdabss, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFABSS, model_fr550_cfabss, { { (int) UNIT_FR550_U_FLOAT_ARITH, 1, 1 } } }, + { FRVBF_INSN_FSQRTS, model_fr550_fsqrts, { { (int) UNIT_FR550_U_FLOAT_SQRT, 1, 1 } } }, + { FRVBF_INSN_FDSQRTS, model_fr550_fdsqrts, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFDSQRTS, model_fr550_nfdsqrts, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FSQRTD, model_fr550_fsqrtd, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFSQRTS, model_fr550_cfsqrts, { { (int) UNIT_FR550_U_FLOAT_SQRT, 1, 1 } } }, + { FRVBF_INSN_NFSQRTS, model_fr550_nfsqrts, { { (int) UNIT_FR550_U_FLOAT_SQRT, 1, 1 } } }, + { FRVBF_INSN_FADDS, model_fr550_fadds, { { (int) UNIT_FR550_U_FLOAT_ARITH, 1, 1 } } }, + { FRVBF_INSN_FSUBS, model_fr550_fsubs, { { (int) UNIT_FR550_U_FLOAT_ARITH, 1, 1 } } }, + { FRVBF_INSN_FMULS, model_fr550_fmuls, { { (int) UNIT_FR550_U_FLOAT_ARITH, 1, 1 } } }, + { FRVBF_INSN_FDIVS, model_fr550_fdivs, { { (int) UNIT_FR550_U_FLOAT_DIV, 1, 1 } } }, + { FRVBF_INSN_FADDD, model_fr550_faddd, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FSUBD, model_fr550_fsubd, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FMULD, model_fr550_fmuld, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDIVD, model_fr550_fdivd, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFADDS, model_fr550_cfadds, { { (int) UNIT_FR550_U_FLOAT_ARITH, 1, 1 } } }, + { FRVBF_INSN_CFSUBS, model_fr550_cfsubs, { { (int) UNIT_FR550_U_FLOAT_ARITH, 1, 1 } } }, + { FRVBF_INSN_CFMULS, model_fr550_cfmuls, { { (int) UNIT_FR550_U_FLOAT_ARITH, 1, 1 } } }, + { FRVBF_INSN_CFDIVS, model_fr550_cfdivs, { { (int) UNIT_FR550_U_FLOAT_DIV, 1, 1 } } }, + { FRVBF_INSN_NFADDS, model_fr550_nfadds, { { (int) UNIT_FR550_U_FLOAT_ARITH, 1, 1 } } }, + { FRVBF_INSN_NFSUBS, model_fr550_nfsubs, { { (int) UNIT_FR550_U_FLOAT_ARITH, 1, 1 } } }, + { FRVBF_INSN_NFMULS, model_fr550_nfmuls, { { (int) UNIT_FR550_U_FLOAT_ARITH, 1, 1 } } }, + { FRVBF_INSN_NFDIVS, model_fr550_nfdivs, { { (int) UNIT_FR550_U_FLOAT_DIV, 1, 1 } } }, + { FRVBF_INSN_FCMPS, model_fr550_fcmps, { { (int) UNIT_FR550_U_FLOAT_COMPARE, 1, 1 } } }, + { FRVBF_INSN_FCMPD, model_fr550_fcmpd, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFCMPS, model_fr550_cfcmps, { { (int) UNIT_FR550_U_FLOAT_COMPARE, 1, 1 } } }, + { FRVBF_INSN_FDCMPS, model_fr550_fdcmps, { { (int) UNIT_FR550_U_FLOAT_DUAL_COMPARE, 1, 3 } } }, + { FRVBF_INSN_FMADDS, model_fr550_fmadds, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FMSUBS, model_fr550_fmsubs, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FMADDD, model_fr550_fmaddd, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FMSUBD, model_fr550_fmsubd, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDMADDS, model_fr550_fdmadds, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFDMADDS, model_fr550_nfdmadds, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFMADDS, model_fr550_cfmadds, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFMSUBS, model_fr550_cfmsubs, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFMADDS, model_fr550_nfmadds, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFMSUBS, model_fr550_nfmsubs, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FMAS, model_fr550_fmas, { { (int) UNIT_FR550_U_FLOAT_DUAL_ARITH, 1, 3 } } }, + { FRVBF_INSN_FMSS, model_fr550_fmss, { { (int) UNIT_FR550_U_FLOAT_DUAL_ARITH, 1, 3 } } }, + { FRVBF_INSN_FDMAS, model_fr550_fdmas, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDMSS, model_fr550_fdmss, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFDMAS, model_fr550_nfdmas, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFDMSS, model_fr550_nfdmss, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFMAS, model_fr550_cfmas, { { (int) UNIT_FR550_U_FLOAT_DUAL_ARITH, 1, 3 } } }, + { FRVBF_INSN_CFMSS, model_fr550_cfmss, { { (int) UNIT_FR550_U_FLOAT_DUAL_ARITH, 1, 3 } } }, + { FRVBF_INSN_FMAD, model_fr550_fmad, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FMSD, model_fr550_fmsd, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFMAS, model_fr550_nfmas, { { (int) UNIT_FR550_U_FLOAT_DUAL_ARITH, 1, 3 } } }, + { FRVBF_INSN_NFMSS, model_fr550_nfmss, { { (int) UNIT_FR550_U_FLOAT_DUAL_ARITH, 1, 3 } } }, + { FRVBF_INSN_FDADDS, model_fr550_fdadds, { { (int) UNIT_FR550_U_FLOAT_DUAL_ARITH, 1, 3 } } }, + { FRVBF_INSN_FDSUBS, model_fr550_fdsubs, { { (int) UNIT_FR550_U_FLOAT_DUAL_ARITH, 1, 3 } } }, + { FRVBF_INSN_FDMULS, model_fr550_fdmuls, { { (int) UNIT_FR550_U_FLOAT_DUAL_ARITH, 1, 3 } } }, + { FRVBF_INSN_FDDIVS, model_fr550_fddivs, { { (int) UNIT_FR550_U_FLOAT_DUAL_ARITH, 1, 3 } } }, + { FRVBF_INSN_FDSADS, model_fr550_fdsads, { { (int) UNIT_FR550_U_FLOAT_DUAL_ARITH, 1, 3 } } }, + { FRVBF_INSN_FDMULCS, model_fr550_fdmulcs, { { (int) UNIT_FR550_U_FLOAT_DUAL_ARITH, 1, 3 } } }, + { FRVBF_INSN_NFDMULCS, model_fr550_nfdmulcs, { { (int) UNIT_FR550_U_FLOAT_DUAL_ARITH, 1, 3 } } }, + { FRVBF_INSN_NFDADDS, model_fr550_nfdadds, { { (int) UNIT_FR550_U_FLOAT_DUAL_ARITH, 1, 3 } } }, + { FRVBF_INSN_NFDSUBS, model_fr550_nfdsubs, { { (int) UNIT_FR550_U_FLOAT_DUAL_ARITH, 1, 3 } } }, + { FRVBF_INSN_NFDMULS, model_fr550_nfdmuls, { { (int) UNIT_FR550_U_FLOAT_DUAL_ARITH, 1, 3 } } }, + { FRVBF_INSN_NFDDIVS, model_fr550_nfddivs, { { (int) UNIT_FR550_U_FLOAT_DUAL_ARITH, 1, 3 } } }, + { FRVBF_INSN_NFDSADS, model_fr550_nfdsads, { { (int) UNIT_FR550_U_FLOAT_DUAL_ARITH, 1, 3 } } }, + { FRVBF_INSN_NFDCMPS, model_fr550_nfdcmps, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MHSETLOS, model_fr550_mhsetlos, { { (int) UNIT_FR550_U_MEDIA_SET, 1, 1 } } }, + { FRVBF_INSN_MHSETHIS, model_fr550_mhsethis, { { (int) UNIT_FR550_U_MEDIA_SET, 1, 1 } } }, + { FRVBF_INSN_MHDSETS, model_fr550_mhdsets, { { (int) UNIT_FR550_U_MEDIA_SET, 1, 1 } } }, + { FRVBF_INSN_MHSETLOH, model_fr550_mhsetloh, { { (int) UNIT_FR550_U_MEDIA_SET, 1, 1 } } }, + { FRVBF_INSN_MHSETHIH, model_fr550_mhsethih, { { (int) UNIT_FR550_U_MEDIA_SET, 1, 1 } } }, + { FRVBF_INSN_MHDSETH, model_fr550_mhdseth, { { (int) UNIT_FR550_U_MEDIA_SET, 1, 1 } } }, + { FRVBF_INSN_MAND, model_fr550_mand, { { (int) UNIT_FR550_U_MEDIA, 1, 1 } } }, + { FRVBF_INSN_MOR, model_fr550_mor, { { (int) UNIT_FR550_U_MEDIA, 1, 1 } } }, + { FRVBF_INSN_MXOR, model_fr550_mxor, { { (int) UNIT_FR550_U_MEDIA, 1, 1 } } }, + { FRVBF_INSN_CMAND, model_fr550_cmand, { { (int) UNIT_FR550_U_MEDIA, 1, 1 } } }, + { FRVBF_INSN_CMOR, model_fr550_cmor, { { (int) UNIT_FR550_U_MEDIA, 1, 1 } } }, + { FRVBF_INSN_CMXOR, model_fr550_cmxor, { { (int) UNIT_FR550_U_MEDIA, 1, 1 } } }, + { FRVBF_INSN_MNOT, model_fr550_mnot, { { (int) UNIT_FR550_U_MEDIA, 1, 1 } } }, + { FRVBF_INSN_CMNOT, model_fr550_cmnot, { { (int) UNIT_FR550_U_MEDIA, 1, 1 } } }, + { FRVBF_INSN_MROTLI, model_fr550_mrotli, { { (int) UNIT_FR550_U_MEDIA, 1, 1 } } }, + { FRVBF_INSN_MROTRI, model_fr550_mrotri, { { (int) UNIT_FR550_U_MEDIA, 1, 1 } } }, + { FRVBF_INSN_MWCUT, model_fr550_mwcut, { { (int) UNIT_FR550_U_MEDIA, 1, 1 } } }, + { FRVBF_INSN_MWCUTI, model_fr550_mwcuti, { { (int) UNIT_FR550_U_MEDIA, 1, 1 } } }, + { FRVBF_INSN_MCUT, model_fr550_mcut, { { (int) UNIT_FR550_U_MEDIA_3_ACC, 1, 1 } } }, + { FRVBF_INSN_MCUTI, model_fr550_mcuti, { { (int) UNIT_FR550_U_MEDIA_3_ACC, 1, 1 } } }, + { FRVBF_INSN_MCUTSS, model_fr550_mcutss, { { (int) UNIT_FR550_U_MEDIA_3_ACC, 1, 1 } } }, + { FRVBF_INSN_MCUTSSI, model_fr550_mcutssi, { { (int) UNIT_FR550_U_MEDIA_3_ACC, 1, 1 } } }, + { FRVBF_INSN_MDCUTSSI, model_fr550_mdcutssi, { { (int) UNIT_FR550_U_MEDIA_3_ACC_DUAL, 1, 1 } } }, + { FRVBF_INSN_MAVEH, model_fr550_maveh, { { (int) UNIT_FR550_U_MEDIA, 1, 1 } } }, + { FRVBF_INSN_MSLLHI, model_fr550_msllhi, { { (int) UNIT_FR550_U_MEDIA, 1, 1 } } }, + { FRVBF_INSN_MSRLHI, model_fr550_msrlhi, { { (int) UNIT_FR550_U_MEDIA, 1, 1 } } }, + { FRVBF_INSN_MSRAHI, model_fr550_msrahi, { { (int) UNIT_FR550_U_MEDIA, 1, 1 } } }, + { FRVBF_INSN_MDROTLI, model_fr550_mdrotli, { { (int) UNIT_FR550_U_MEDIA_QUAD, 1, 1 } } }, + { FRVBF_INSN_MCPLHI, model_fr550_mcplhi, { { (int) UNIT_FR550_U_MEDIA_3_DUAL, 1, 1 } } }, + { FRVBF_INSN_MCPLI, model_fr550_mcpli, { { (int) UNIT_FR550_U_MEDIA_3_DUAL, 1, 1 } } }, + { FRVBF_INSN_MSATHS, model_fr550_msaths, { { (int) UNIT_FR550_U_MEDIA, 1, 1 } } }, + { FRVBF_INSN_MQSATHS, model_fr550_mqsaths, { { (int) UNIT_FR550_U_MEDIA_QUAD, 1, 1 } } }, + { FRVBF_INSN_MSATHU, model_fr550_msathu, { { (int) UNIT_FR550_U_MEDIA, 1, 1 } } }, + { FRVBF_INSN_MCMPSH, model_fr550_mcmpsh, { { (int) UNIT_FR550_U_MEDIA, 1, 1 } } }, + { FRVBF_INSN_MCMPUH, model_fr550_mcmpuh, { { (int) UNIT_FR550_U_MEDIA, 1, 1 } } }, + { FRVBF_INSN_MABSHS, model_fr550_mabshs, { { (int) UNIT_FR550_U_MEDIA, 1, 1 } } }, + { FRVBF_INSN_MADDHSS, model_fr550_maddhss, { { (int) UNIT_FR550_U_MEDIA, 1, 1 } } }, + { FRVBF_INSN_MADDHUS, model_fr550_maddhus, { { (int) UNIT_FR550_U_MEDIA, 1, 1 } } }, + { FRVBF_INSN_MSUBHSS, model_fr550_msubhss, { { (int) UNIT_FR550_U_MEDIA, 1, 1 } } }, + { FRVBF_INSN_MSUBHUS, model_fr550_msubhus, { { (int) UNIT_FR550_U_MEDIA, 1, 1 } } }, + { FRVBF_INSN_CMADDHSS, model_fr550_cmaddhss, { { (int) UNIT_FR550_U_MEDIA, 1, 1 } } }, + { FRVBF_INSN_CMADDHUS, model_fr550_cmaddhus, { { (int) UNIT_FR550_U_MEDIA, 1, 1 } } }, + { FRVBF_INSN_CMSUBHSS, model_fr550_cmsubhss, { { (int) UNIT_FR550_U_MEDIA, 1, 1 } } }, + { FRVBF_INSN_CMSUBHUS, model_fr550_cmsubhus, { { (int) UNIT_FR550_U_MEDIA, 1, 1 } } }, + { FRVBF_INSN_MQADDHSS, model_fr550_mqaddhss, { { (int) UNIT_FR550_U_MEDIA_QUAD, 1, 1 } } }, + { FRVBF_INSN_MQADDHUS, model_fr550_mqaddhus, { { (int) UNIT_FR550_U_MEDIA_QUAD, 1, 1 } } }, + { FRVBF_INSN_MQSUBHSS, model_fr550_mqsubhss, { { (int) UNIT_FR550_U_MEDIA_QUAD, 1, 1 } } }, + { FRVBF_INSN_MQSUBHUS, model_fr550_mqsubhus, { { (int) UNIT_FR550_U_MEDIA_QUAD, 1, 1 } } }, + { FRVBF_INSN_CMQADDHSS, model_fr550_cmqaddhss, { { (int) UNIT_FR550_U_MEDIA_QUAD, 1, 1 } } }, + { FRVBF_INSN_CMQADDHUS, model_fr550_cmqaddhus, { { (int) UNIT_FR550_U_MEDIA_QUAD, 1, 1 } } }, + { FRVBF_INSN_CMQSUBHSS, model_fr550_cmqsubhss, { { (int) UNIT_FR550_U_MEDIA_QUAD, 1, 1 } } }, + { FRVBF_INSN_CMQSUBHUS, model_fr550_cmqsubhus, { { (int) UNIT_FR550_U_MEDIA_QUAD, 1, 1 } } }, + { FRVBF_INSN_MADDACCS, model_fr550_maddaccs, { { (int) UNIT_FR550_U_MEDIA_4_ACC, 1, 1 } } }, + { FRVBF_INSN_MSUBACCS, model_fr550_msubaccs, { { (int) UNIT_FR550_U_MEDIA_4_ACC, 1, 1 } } }, + { FRVBF_INSN_MDADDACCS, model_fr550_mdaddaccs, { { (int) UNIT_FR550_U_MEDIA_4_ACC_DUAL, 1, 1 } } }, + { FRVBF_INSN_MDSUBACCS, model_fr550_mdsubaccs, { { (int) UNIT_FR550_U_MEDIA_4_ACC_DUAL, 1, 1 } } }, + { FRVBF_INSN_MASACCS, model_fr550_masaccs, { { (int) UNIT_FR550_U_MEDIA_4_ADD_SUB, 1, 1 } } }, + { FRVBF_INSN_MDASACCS, model_fr550_mdasaccs, { { (int) UNIT_FR550_U_MEDIA_4_ADD_SUB_DUAL, 1, 1 } } }, + { FRVBF_INSN_MMULHS, model_fr550_mmulhs, { { (int) UNIT_FR550_U_MEDIA_4, 1, 1 } } }, + { FRVBF_INSN_MMULHU, model_fr550_mmulhu, { { (int) UNIT_FR550_U_MEDIA_4, 1, 1 } } }, + { FRVBF_INSN_MMULXHS, model_fr550_mmulxhs, { { (int) UNIT_FR550_U_MEDIA_4, 1, 1 } } }, + { FRVBF_INSN_MMULXHU, model_fr550_mmulxhu, { { (int) UNIT_FR550_U_MEDIA_4, 1, 1 } } }, + { FRVBF_INSN_CMMULHS, model_fr550_cmmulhs, { { (int) UNIT_FR550_U_MEDIA_4, 1, 1 } } }, + { FRVBF_INSN_CMMULHU, model_fr550_cmmulhu, { { (int) UNIT_FR550_U_MEDIA_4, 1, 1 } } }, + { FRVBF_INSN_MQMULHS, model_fr550_mqmulhs, { { (int) UNIT_FR550_U_MEDIA_4_QUAD, 1, 1 } } }, + { FRVBF_INSN_MQMULHU, model_fr550_mqmulhu, { { (int) UNIT_FR550_U_MEDIA_4_QUAD, 1, 1 } } }, + { FRVBF_INSN_MQMULXHS, model_fr550_mqmulxhs, { { (int) UNIT_FR550_U_MEDIA_4_QUAD, 1, 1 } } }, + { FRVBF_INSN_MQMULXHU, model_fr550_mqmulxhu, { { (int) UNIT_FR550_U_MEDIA_4_QUAD, 1, 1 } } }, + { FRVBF_INSN_CMQMULHS, model_fr550_cmqmulhs, { { (int) UNIT_FR550_U_MEDIA_4_QUAD, 1, 1 } } }, + { FRVBF_INSN_CMQMULHU, model_fr550_cmqmulhu, { { (int) UNIT_FR550_U_MEDIA_4_QUAD, 1, 1 } } }, + { FRVBF_INSN_MMACHS, model_fr550_mmachs, { { (int) UNIT_FR550_U_MEDIA_4, 1, 1 } } }, + { FRVBF_INSN_MMACHU, model_fr550_mmachu, { { (int) UNIT_FR550_U_MEDIA_4, 1, 1 } } }, + { FRVBF_INSN_MMRDHS, model_fr550_mmrdhs, { { (int) UNIT_FR550_U_MEDIA_4, 1, 1 } } }, + { FRVBF_INSN_MMRDHU, model_fr550_mmrdhu, { { (int) UNIT_FR550_U_MEDIA_4, 1, 1 } } }, + { FRVBF_INSN_CMMACHS, model_fr550_cmmachs, { { (int) UNIT_FR550_U_MEDIA_4, 1, 1 } } }, + { FRVBF_INSN_CMMACHU, model_fr550_cmmachu, { { (int) UNIT_FR550_U_MEDIA_4, 1, 1 } } }, + { FRVBF_INSN_MQMACHS, model_fr550_mqmachs, { { (int) UNIT_FR550_U_MEDIA_4_QUAD, 1, 1 } } }, + { FRVBF_INSN_MQMACHU, model_fr550_mqmachu, { { (int) UNIT_FR550_U_MEDIA_4_QUAD, 1, 1 } } }, + { FRVBF_INSN_CMQMACHS, model_fr550_cmqmachs, { { (int) UNIT_FR550_U_MEDIA_4_QUAD, 1, 1 } } }, + { FRVBF_INSN_CMQMACHU, model_fr550_cmqmachu, { { (int) UNIT_FR550_U_MEDIA_4_QUAD, 1, 1 } } }, + { FRVBF_INSN_MQXMACHS, model_fr550_mqxmachs, { { (int) UNIT_FR550_U_MEDIA_4_QUAD, 1, 1 } } }, + { FRVBF_INSN_MQXMACXHS, model_fr550_mqxmacxhs, { { (int) UNIT_FR550_U_MEDIA_4_QUAD, 1, 1 } } }, + { FRVBF_INSN_MQMACXHS, model_fr550_mqmacxhs, { { (int) UNIT_FR550_U_MEDIA_4_QUAD, 1, 1 } } }, + { FRVBF_INSN_MCPXRS, model_fr550_mcpxrs, { { (int) UNIT_FR550_U_MEDIA_4, 1, 1 } } }, + { FRVBF_INSN_MCPXRU, model_fr550_mcpxru, { { (int) UNIT_FR550_U_MEDIA_4, 1, 1 } } }, + { FRVBF_INSN_MCPXIS, model_fr550_mcpxis, { { (int) UNIT_FR550_U_MEDIA_4, 1, 1 } } }, + { FRVBF_INSN_MCPXIU, model_fr550_mcpxiu, { { (int) UNIT_FR550_U_MEDIA_4, 1, 1 } } }, + { FRVBF_INSN_CMCPXRS, model_fr550_cmcpxrs, { { (int) UNIT_FR550_U_MEDIA_4, 1, 1 } } }, + { FRVBF_INSN_CMCPXRU, model_fr550_cmcpxru, { { (int) UNIT_FR550_U_MEDIA_4, 1, 1 } } }, + { FRVBF_INSN_CMCPXIS, model_fr550_cmcpxis, { { (int) UNIT_FR550_U_MEDIA_4, 1, 1 } } }, + { FRVBF_INSN_CMCPXIU, model_fr550_cmcpxiu, { { (int) UNIT_FR550_U_MEDIA_4, 1, 1 } } }, + { FRVBF_INSN_MQCPXRS, model_fr550_mqcpxrs, { { (int) UNIT_FR550_U_MEDIA_4_QUAD, 1, 1 } } }, + { FRVBF_INSN_MQCPXRU, model_fr550_mqcpxru, { { (int) UNIT_FR550_U_MEDIA_4_QUAD, 1, 1 } } }, + { FRVBF_INSN_MQCPXIS, model_fr550_mqcpxis, { { (int) UNIT_FR550_U_MEDIA_4_QUAD, 1, 1 } } }, + { FRVBF_INSN_MQCPXIU, model_fr550_mqcpxiu, { { (int) UNIT_FR550_U_MEDIA_4_QUAD, 1, 1 } } }, + { FRVBF_INSN_MEXPDHW, model_fr550_mexpdhw, { { (int) UNIT_FR550_U_MEDIA, 1, 1 } } }, + { FRVBF_INSN_CMEXPDHW, model_fr550_cmexpdhw, { { (int) UNIT_FR550_U_MEDIA, 1, 1 } } }, + { FRVBF_INSN_MEXPDHD, model_fr550_mexpdhd, { { (int) UNIT_FR550_U_MEDIA_DUAL_EXPAND, 1, 1 } } }, + { FRVBF_INSN_CMEXPDHD, model_fr550_cmexpdhd, { { (int) UNIT_FR550_U_MEDIA_DUAL_EXPAND, 1, 1 } } }, + { FRVBF_INSN_MPACKH, model_fr550_mpackh, { { (int) UNIT_FR550_U_MEDIA, 1, 1 } } }, + { FRVBF_INSN_MDPACKH, model_fr550_mdpackh, { { (int) UNIT_FR550_U_MEDIA_QUAD, 1, 1 } } }, + { FRVBF_INSN_MUNPACKH, model_fr550_munpackh, { { (int) UNIT_FR550_U_MEDIA_DUAL_EXPAND, 1, 1 } } }, + { FRVBF_INSN_MDUNPACKH, model_fr550_mdunpackh, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MBTOH, model_fr550_mbtoh, { { (int) UNIT_FR550_U_MEDIA_DUAL_EXPAND, 1, 1 } } }, + { FRVBF_INSN_CMBTOH, model_fr550_cmbtoh, { { (int) UNIT_FR550_U_MEDIA_DUAL_EXPAND, 1, 1 } } }, + { FRVBF_INSN_MHTOB, model_fr550_mhtob, { { (int) UNIT_FR550_U_MEDIA_3_DUAL, 1, 1 } } }, + { FRVBF_INSN_CMHTOB, model_fr550_cmhtob, { { (int) UNIT_FR550_U_MEDIA_3_DUAL, 1, 1 } } }, + { FRVBF_INSN_MBTOHE, model_fr550_mbtohe, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMBTOHE, model_fr550_cmbtohe, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MNOP, model_fr550_mnop, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MCLRACC_0, model_fr550_mclracc_0, { { (int) UNIT_FR550_U_MEDIA_3_MCLRACC, 1, 1 } } }, + { FRVBF_INSN_MCLRACC_1, model_fr550_mclracc_1, { { (int) UNIT_FR550_U_MEDIA_3_MCLRACC, 1, 1 } } }, + { FRVBF_INSN_MRDACC, model_fr550_mrdacc, { { (int) UNIT_FR550_U_MEDIA_3_ACC, 1, 1 } } }, + { FRVBF_INSN_MRDACCG, model_fr550_mrdaccg, { { (int) UNIT_FR550_U_MEDIA_3_ACC, 1, 1 } } }, + { FRVBF_INSN_MWTACC, model_fr550_mwtacc, { { (int) UNIT_FR550_U_MEDIA_3_WTACC, 1, 1 } } }, + { FRVBF_INSN_MWTACCG, model_fr550_mwtaccg, { { (int) UNIT_FR550_U_MEDIA_3_WTACC, 1, 1 } } }, + { FRVBF_INSN_MCOP1, model_fr550_mcop1, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MCOP2, model_fr550_mcop2, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FNOP, model_fr550_fnop, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, +}; + +/* Model timing data for `fr500'. */ + +static const INSN_TIMING fr500_timing[] = { + { FRVBF_INSN_X_INVALID, 0, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_X_AFTER, 0, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_X_BEFORE, 0, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_X_CTI_CHAIN, 0, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_X_CHAIN, 0, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_X_BEGIN, 0, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ADD, model_fr500_add, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SUB, model_fr500_sub, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_AND, model_fr500_and, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_OR, model_fr500_or, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_XOR, model_fr500_xor, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_NOT, model_fr500_not, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SDIV, model_fr500_sdiv, { { (int) UNIT_FR500_U_IDIV, 1, 1 } } }, + { FRVBF_INSN_NSDIV, model_fr500_nsdiv, { { (int) UNIT_FR500_U_IDIV, 1, 1 } } }, + { FRVBF_INSN_UDIV, model_fr500_udiv, { { (int) UNIT_FR500_U_IDIV, 1, 1 } } }, + { FRVBF_INSN_NUDIV, model_fr500_nudiv, { { (int) UNIT_FR500_U_IDIV, 1, 1 } } }, + { FRVBF_INSN_SMUL, model_fr500_smul, { { (int) UNIT_FR500_U_IMUL, 1, 1 } } }, + { FRVBF_INSN_UMUL, model_fr500_umul, { { (int) UNIT_FR500_U_IMUL, 1, 1 } } }, + { FRVBF_INSN_SMU, model_fr500_smu, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SMASS, model_fr500_smass, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SMSSS, model_fr500_smsss, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SLL, model_fr500_sll, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SRL, model_fr500_srl, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SRA, model_fr500_sra, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SLASS, model_fr500_slass, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SCUTSS, model_fr500_scutss, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SCAN, model_fr500_scan, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_CADD, model_fr500_cadd, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_CSUB, model_fr500_csub, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_CAND, model_fr500_cand, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_COR, model_fr500_cor, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_CXOR, model_fr500_cxor, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_CNOT, model_fr500_cnot, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_CSMUL, model_fr500_csmul, { { (int) UNIT_FR500_U_IMUL, 1, 1 } } }, + { FRVBF_INSN_CSDIV, model_fr500_csdiv, { { (int) UNIT_FR500_U_IDIV, 1, 1 } } }, + { FRVBF_INSN_CUDIV, model_fr500_cudiv, { { (int) UNIT_FR500_U_IDIV, 1, 1 } } }, + { FRVBF_INSN_CSLL, model_fr500_csll, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_CSRL, model_fr500_csrl, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_CSRA, model_fr500_csra, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_CSCAN, model_fr500_cscan, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_ADDCC, model_fr500_addcc, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SUBCC, model_fr500_subcc, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_ANDCC, model_fr500_andcc, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_ORCC, model_fr500_orcc, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_XORCC, model_fr500_xorcc, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SLLCC, model_fr500_sllcc, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SRLCC, model_fr500_srlcc, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SRACC, model_fr500_sracc, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SMULCC, model_fr500_smulcc, { { (int) UNIT_FR500_U_IMUL, 1, 1 } } }, + { FRVBF_INSN_UMULCC, model_fr500_umulcc, { { (int) UNIT_FR500_U_IMUL, 1, 1 } } }, + { FRVBF_INSN_CADDCC, model_fr500_caddcc, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_CSUBCC, model_fr500_csubcc, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_CSMULCC, model_fr500_csmulcc, { { (int) UNIT_FR500_U_IMUL, 1, 1 } } }, + { FRVBF_INSN_CANDCC, model_fr500_candcc, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_CORCC, model_fr500_corcc, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_CXORCC, model_fr500_cxorcc, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_CSLLCC, model_fr500_csllcc, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_CSRLCC, model_fr500_csrlcc, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_CSRACC, model_fr500_csracc, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_ADDX, model_fr500_addx, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SUBX, model_fr500_subx, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_ADDXCC, model_fr500_addxcc, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SUBXCC, model_fr500_subxcc, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_ADDSS, model_fr500_addss, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SUBSS, model_fr500_subss, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ADDI, model_fr500_addi, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SUBI, model_fr500_subi, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_ANDI, model_fr500_andi, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_ORI, model_fr500_ori, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_XORI, model_fr500_xori, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SDIVI, model_fr500_sdivi, { { (int) UNIT_FR500_U_IDIV, 1, 1 } } }, + { FRVBF_INSN_NSDIVI, model_fr500_nsdivi, { { (int) UNIT_FR500_U_IDIV, 1, 1 } } }, + { FRVBF_INSN_UDIVI, model_fr500_udivi, { { (int) UNIT_FR500_U_IDIV, 1, 1 } } }, + { FRVBF_INSN_NUDIVI, model_fr500_nudivi, { { (int) UNIT_FR500_U_IDIV, 1, 1 } } }, + { FRVBF_INSN_SMULI, model_fr500_smuli, { { (int) UNIT_FR500_U_IMUL, 1, 1 } } }, + { FRVBF_INSN_UMULI, model_fr500_umuli, { { (int) UNIT_FR500_U_IMUL, 1, 1 } } }, + { FRVBF_INSN_SLLI, model_fr500_slli, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SRLI, model_fr500_srli, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SRAI, model_fr500_srai, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SCANI, model_fr500_scani, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_ADDICC, model_fr500_addicc, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SUBICC, model_fr500_subicc, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_ANDICC, model_fr500_andicc, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_ORICC, model_fr500_oricc, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_XORICC, model_fr500_xoricc, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SMULICC, model_fr500_smulicc, { { (int) UNIT_FR500_U_IMUL, 1, 1 } } }, + { FRVBF_INSN_UMULICC, model_fr500_umulicc, { { (int) UNIT_FR500_U_IMUL, 1, 1 } } }, + { FRVBF_INSN_SLLICC, model_fr500_sllicc, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SRLICC, model_fr500_srlicc, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SRAICC, model_fr500_sraicc, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_ADDXI, model_fr500_addxi, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SUBXI, model_fr500_subxi, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_ADDXICC, model_fr500_addxicc, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SUBXICC, model_fr500_subxicc, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_CMPB, model_fr500_cmpb, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMPBA, model_fr500_cmpba, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SETLO, model_fr500_setlo, { { (int) UNIT_FR500_U_SET_HILO, 1, 1 } } }, + { FRVBF_INSN_SETHI, model_fr500_sethi, { { (int) UNIT_FR500_U_SET_HILO, 1, 1 } } }, + { FRVBF_INSN_SETLOS, model_fr500_setlos, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_LDSB, model_fr500_ldsb, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDUB, model_fr500_ldub, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDSH, model_fr500_ldsh, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDUH, model_fr500_lduh, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LD, model_fr500_ld, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDBF, model_fr500_ldbf, { { (int) UNIT_FR500_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDHF, model_fr500_ldhf, { { (int) UNIT_FR500_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDF, model_fr500_ldf, { { (int) UNIT_FR500_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDC, model_fr500_ldc, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDSB, model_fr500_nldsb, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_NLDUB, model_fr500_nldub, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_NLDSH, model_fr500_nldsh, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_NLDUH, model_fr500_nlduh, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_NLD, model_fr500_nld, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_NLDBF, model_fr500_nldbf, { { (int) UNIT_FR500_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_NLDHF, model_fr500_nldhf, { { (int) UNIT_FR500_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_NLDF, model_fr500_nldf, { { (int) UNIT_FR500_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDD, model_fr500_ldd, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDDF, model_fr500_lddf, { { (int) UNIT_FR500_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDDC, model_fr500_lddc, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDD, model_fr500_nldd, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_NLDDF, model_fr500_nlddf, { { (int) UNIT_FR500_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDQ, model_fr500_ldq, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDQF, model_fr500_ldqf, { { (int) UNIT_FR500_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDQC, model_fr500_ldqc, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDQ, model_fr500_nldq, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_NLDQF, model_fr500_nldqf, { { (int) UNIT_FR500_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDSBU, model_fr500_ldsbu, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDUBU, model_fr500_ldubu, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDSHU, model_fr500_ldshu, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDUHU, model_fr500_lduhu, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDU, model_fr500_ldu, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_NLDSBU, model_fr500_nldsbu, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_NLDUBU, model_fr500_nldubu, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_NLDSHU, model_fr500_nldshu, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_NLDUHU, model_fr500_nlduhu, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_NLDU, model_fr500_nldu, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDBFU, model_fr500_ldbfu, { { (int) UNIT_FR500_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDHFU, model_fr500_ldhfu, { { (int) UNIT_FR500_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDFU, model_fr500_ldfu, { { (int) UNIT_FR500_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDCU, model_fr500_ldcu, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDBFU, model_fr500_nldbfu, { { (int) UNIT_FR500_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_NLDHFU, model_fr500_nldhfu, { { (int) UNIT_FR500_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_NLDFU, model_fr500_nldfu, { { (int) UNIT_FR500_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDDU, model_fr500_lddu, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_NLDDU, model_fr500_nlddu, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDDFU, model_fr500_lddfu, { { (int) UNIT_FR500_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDDCU, model_fr500_lddcu, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDDFU, model_fr500_nlddfu, { { (int) UNIT_FR500_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDQU, model_fr500_ldqu, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_NLDQU, model_fr500_nldqu, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDQFU, model_fr500_ldqfu, { { (int) UNIT_FR500_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDQCU, model_fr500_ldqcu, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDQFU, model_fr500_nldqfu, { { (int) UNIT_FR500_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDSBI, model_fr500_ldsbi, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDSHI, model_fr500_ldshi, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDI, model_fr500_ldi, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDUBI, model_fr500_ldubi, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDUHI, model_fr500_lduhi, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDBFI, model_fr500_ldbfi, { { (int) UNIT_FR500_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDHFI, model_fr500_ldhfi, { { (int) UNIT_FR500_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDFI, model_fr500_ldfi, { { (int) UNIT_FR500_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_NLDSBI, model_fr500_nldsbi, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_NLDUBI, model_fr500_nldubi, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_NLDSHI, model_fr500_nldshi, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_NLDUHI, model_fr500_nlduhi, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_NLDI, model_fr500_nldi, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_NLDBFI, model_fr500_nldbfi, { { (int) UNIT_FR500_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_NLDHFI, model_fr500_nldhfi, { { (int) UNIT_FR500_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_NLDFI, model_fr500_nldfi, { { (int) UNIT_FR500_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDDI, model_fr500_lddi, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDDFI, model_fr500_lddfi, { { (int) UNIT_FR500_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_NLDDI, model_fr500_nlddi, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_NLDDFI, model_fr500_nlddfi, { { (int) UNIT_FR500_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDQI, model_fr500_ldqi, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDQFI, model_fr500_ldqfi, { { (int) UNIT_FR500_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_NLDQFI, model_fr500_nldqfi, { { (int) UNIT_FR500_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_STB, model_fr500_stb, { { (int) UNIT_FR500_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_STH, model_fr500_sth, { { (int) UNIT_FR500_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_ST, model_fr500_st, { { (int) UNIT_FR500_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_STBF, model_fr500_stbf, { { (int) UNIT_FR500_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_STHF, model_fr500_sthf, { { (int) UNIT_FR500_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_STF, model_fr500_stf, { { (int) UNIT_FR500_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_STC, model_fr500_stc, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_RSTB, model_fr500_rstb, { { (int) UNIT_FR500_U_GR_R_STORE, 1, 1 } } }, + { FRVBF_INSN_RSTH, model_fr500_rsth, { { (int) UNIT_FR500_U_GR_R_STORE, 1, 1 } } }, + { FRVBF_INSN_RST, model_fr500_rst, { { (int) UNIT_FR500_U_GR_R_STORE, 1, 1 } } }, + { FRVBF_INSN_RSTBF, model_fr500_rstbf, { { (int) UNIT_FR500_U_FR_R_STORE, 1, 1 } } }, + { FRVBF_INSN_RSTHF, model_fr500_rsthf, { { (int) UNIT_FR500_U_FR_R_STORE, 1, 1 } } }, + { FRVBF_INSN_RSTF, model_fr500_rstf, { { (int) UNIT_FR500_U_FR_R_STORE, 1, 1 } } }, + { FRVBF_INSN_STD, model_fr500_std, { { (int) UNIT_FR500_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_STDF, model_fr500_stdf, { { (int) UNIT_FR500_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_STDC, model_fr500_stdc, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_RSTD, model_fr500_rstd, { { (int) UNIT_FR500_U_GR_R_STORE, 1, 1 } } }, + { FRVBF_INSN_RSTDF, model_fr500_rstdf, { { (int) UNIT_FR500_U_FR_R_STORE, 1, 1 } } }, + { FRVBF_INSN_STQ, model_fr500_stq, { { (int) UNIT_FR500_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_STQF, model_fr500_stqf, { { (int) UNIT_FR500_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_STQC, model_fr500_stqc, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_RSTQ, model_fr500_rstq, { { (int) UNIT_FR500_U_GR_R_STORE, 1, 1 } } }, + { FRVBF_INSN_RSTQF, model_fr500_rstqf, { { (int) UNIT_FR500_U_FR_R_STORE, 1, 1 } } }, + { FRVBF_INSN_STBU, model_fr500_stbu, { { (int) UNIT_FR500_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_STHU, model_fr500_sthu, { { (int) UNIT_FR500_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_STU, model_fr500_stu, { { (int) UNIT_FR500_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_STBFU, model_fr500_stbfu, { { (int) UNIT_FR500_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_STHFU, model_fr500_sthfu, { { (int) UNIT_FR500_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_STFU, model_fr500_stfu, { { (int) UNIT_FR500_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_STCU, model_fr500_stcu, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STDU, model_fr500_stdu, { { (int) UNIT_FR500_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_STDFU, model_fr500_stdfu, { { (int) UNIT_FR500_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_STDCU, model_fr500_stdcu, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STQU, model_fr500_stqu, { { (int) UNIT_FR500_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_STQFU, model_fr500_stqfu, { { (int) UNIT_FR500_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_STQCU, model_fr500_stqcu, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLDSB, model_fr500_cldsb, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDUB, model_fr500_cldub, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDSH, model_fr500_cldsh, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDUH, model_fr500_clduh, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLD, model_fr500_cld, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDBF, model_fr500_cldbf, { { (int) UNIT_FR500_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDHF, model_fr500_cldhf, { { (int) UNIT_FR500_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDF, model_fr500_cldf, { { (int) UNIT_FR500_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDD, model_fr500_cldd, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDDF, model_fr500_clddf, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDQ, model_fr500_cldq, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDSBU, model_fr500_cldsbu, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDUBU, model_fr500_cldubu, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDSHU, model_fr500_cldshu, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDUHU, model_fr500_clduhu, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDU, model_fr500_cldu, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDBFU, model_fr500_cldbfu, { { (int) UNIT_FR500_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDHFU, model_fr500_cldhfu, { { (int) UNIT_FR500_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDFU, model_fr500_cldfu, { { (int) UNIT_FR500_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDDU, model_fr500_clddu, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDDFU, model_fr500_clddfu, { { (int) UNIT_FR500_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDQU, model_fr500_cldqu, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CSTB, model_fr500_cstb, { { (int) UNIT_FR500_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_CSTH, model_fr500_csth, { { (int) UNIT_FR500_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_CST, model_fr500_cst, { { (int) UNIT_FR500_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_CSTBF, model_fr500_cstbf, { { (int) UNIT_FR500_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_CSTHF, model_fr500_csthf, { { (int) UNIT_FR500_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_CSTF, model_fr500_cstf, { { (int) UNIT_FR500_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_CSTD, model_fr500_cstd, { { (int) UNIT_FR500_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_CSTDF, model_fr500_cstdf, { { (int) UNIT_FR500_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_CSTQ, model_fr500_cstq, { { (int) UNIT_FR500_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_CSTBU, model_fr500_cstbu, { { (int) UNIT_FR500_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_CSTHU, model_fr500_csthu, { { (int) UNIT_FR500_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_CSTU, model_fr500_cstu, { { (int) UNIT_FR500_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_CSTBFU, model_fr500_cstbfu, { { (int) UNIT_FR500_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_CSTHFU, model_fr500_csthfu, { { (int) UNIT_FR500_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_CSTFU, model_fr500_cstfu, { { (int) UNIT_FR500_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_CSTDU, model_fr500_cstdu, { { (int) UNIT_FR500_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_CSTDFU, model_fr500_cstdfu, { { (int) UNIT_FR500_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_STBI, model_fr500_stbi, { { (int) UNIT_FR500_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_STHI, model_fr500_sthi, { { (int) UNIT_FR500_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_STI, model_fr500_sti, { { (int) UNIT_FR500_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_STBFI, model_fr500_stbfi, { { (int) UNIT_FR500_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_STHFI, model_fr500_sthfi, { { (int) UNIT_FR500_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_STFI, model_fr500_stfi, { { (int) UNIT_FR500_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_STDI, model_fr500_stdi, { { (int) UNIT_FR500_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_STDFI, model_fr500_stdfi, { { (int) UNIT_FR500_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_STQI, model_fr500_stqi, { { (int) UNIT_FR500_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_STQFI, model_fr500_stqfi, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SWAP, model_fr500_swap, { { (int) UNIT_FR500_U_SWAP, 1, 1 } } }, + { FRVBF_INSN_SWAPI, model_fr500_swapi, { { (int) UNIT_FR500_U_SWAP, 1, 1 } } }, + { FRVBF_INSN_CSWAP, model_fr500_cswap, { { (int) UNIT_FR500_U_SWAP, 1, 1 } } }, + { FRVBF_INSN_MOVGF, model_fr500_movgf, { { (int) UNIT_FR500_U_GR2FR, 1, 1 } } }, + { FRVBF_INSN_MOVFG, model_fr500_movfg, { { (int) UNIT_FR500_U_FR2GR, 1, 1 } } }, + { FRVBF_INSN_MOVGFD, model_fr500_movgfd, { { (int) UNIT_FR500_U_GR2FR, 1, 1 } } }, + { FRVBF_INSN_MOVFGD, model_fr500_movfgd, { { (int) UNIT_FR500_U_FR2GR, 1, 1 } } }, + { FRVBF_INSN_MOVGFQ, model_fr500_movgfq, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MOVFGQ, model_fr500_movfgq, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMOVGF, model_fr500_cmovgf, { { (int) UNIT_FR500_U_GR2FR, 1, 1 } } }, + { FRVBF_INSN_CMOVFG, model_fr500_cmovfg, { { (int) UNIT_FR500_U_FR2GR, 1, 1 } } }, + { FRVBF_INSN_CMOVGFD, model_fr500_cmovgfd, { { (int) UNIT_FR500_U_GR2FR, 1, 1 } } }, + { FRVBF_INSN_CMOVFGD, model_fr500_cmovfgd, { { (int) UNIT_FR500_U_FR2GR, 1, 1 } } }, + { FRVBF_INSN_MOVGS, model_fr500_movgs, { { (int) UNIT_FR500_U_GR2SPR, 1, 1 } } }, + { FRVBF_INSN_MOVSG, model_fr500_movsg, { { (int) UNIT_FR500_U_SPR2GR, 1, 1 } } }, + { FRVBF_INSN_BRA, model_fr500_bra, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BNO, model_fr500_bno, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BEQ, model_fr500_beq, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BNE, model_fr500_bne, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BLE, model_fr500_ble, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BGT, model_fr500_bgt, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BLT, model_fr500_blt, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BGE, model_fr500_bge, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BLS, model_fr500_bls, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BHI, model_fr500_bhi, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BC, model_fr500_bc, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BNC, model_fr500_bnc, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BN, model_fr500_bn, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BP, model_fr500_bp, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BV, model_fr500_bv, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BNV, model_fr500_bnv, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBRA, model_fr500_fbra, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBNO, model_fr500_fbno, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBNE, model_fr500_fbne, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBEQ, model_fr500_fbeq, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBLG, model_fr500_fblg, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBUE, model_fr500_fbue, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBUL, model_fr500_fbul, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBGE, model_fr500_fbge, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBLT, model_fr500_fblt, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBUGE, model_fr500_fbuge, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBUG, model_fr500_fbug, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBLE, model_fr500_fble, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBGT, model_fr500_fbgt, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBULE, model_fr500_fbule, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBU, model_fr500_fbu, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBO, model_fr500_fbo, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BCTRLR, model_fr500_bctrlr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BRALR, model_fr500_bralr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BNOLR, model_fr500_bnolr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BEQLR, model_fr500_beqlr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BNELR, model_fr500_bnelr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BLELR, model_fr500_blelr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BGTLR, model_fr500_bgtlr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BLTLR, model_fr500_bltlr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BGELR, model_fr500_bgelr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BLSLR, model_fr500_blslr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BHILR, model_fr500_bhilr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BCLR, model_fr500_bclr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BNCLR, model_fr500_bnclr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BNLR, model_fr500_bnlr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BPLR, model_fr500_bplr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BVLR, model_fr500_bvlr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BNVLR, model_fr500_bnvlr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBRALR, model_fr500_fbralr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBNOLR, model_fr500_fbnolr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBEQLR, model_fr500_fbeqlr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBNELR, model_fr500_fbnelr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBLGLR, model_fr500_fblglr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBUELR, model_fr500_fbuelr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBULLR, model_fr500_fbullr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBGELR, model_fr500_fbgelr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBLTLR, model_fr500_fbltlr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBUGELR, model_fr500_fbugelr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBUGLR, model_fr500_fbuglr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBLELR, model_fr500_fblelr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBGTLR, model_fr500_fbgtlr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBULELR, model_fr500_fbulelr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBULR, model_fr500_fbulr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBOLR, model_fr500_fbolr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BCRALR, model_fr500_bcralr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BCNOLR, model_fr500_bcnolr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BCEQLR, model_fr500_bceqlr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BCNELR, model_fr500_bcnelr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BCLELR, model_fr500_bclelr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BCGTLR, model_fr500_bcgtlr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BCLTLR, model_fr500_bcltlr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BCGELR, model_fr500_bcgelr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BCLSLR, model_fr500_bclslr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BCHILR, model_fr500_bchilr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BCCLR, model_fr500_bcclr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BCNCLR, model_fr500_bcnclr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BCNLR, model_fr500_bcnlr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BCPLR, model_fr500_bcplr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BCVLR, model_fr500_bcvlr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BCNVLR, model_fr500_bcnvlr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FCBRALR, model_fr500_fcbralr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FCBNOLR, model_fr500_fcbnolr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FCBEQLR, model_fr500_fcbeqlr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FCBNELR, model_fr500_fcbnelr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FCBLGLR, model_fr500_fcblglr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FCBUELR, model_fr500_fcbuelr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FCBULLR, model_fr500_fcbullr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FCBGELR, model_fr500_fcbgelr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FCBLTLR, model_fr500_fcbltlr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FCBUGELR, model_fr500_fcbugelr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FCBUGLR, model_fr500_fcbuglr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FCBLELR, model_fr500_fcblelr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FCBGTLR, model_fr500_fcbgtlr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FCBULELR, model_fr500_fcbulelr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FCBULR, model_fr500_fcbulr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FCBOLR, model_fr500_fcbolr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_JMPL, model_fr500_jmpl, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_CALLL, model_fr500_calll, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_JMPIL, model_fr500_jmpil, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_CALLIL, model_fr500_callil, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_CALL, model_fr500_call, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_RETT, model_fr500_rett, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_REI, model_fr500_rei, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TRA, model_fr500_tra, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TNO, model_fr500_tno, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TEQ, model_fr500_teq, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TNE, model_fr500_tne, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TLE, model_fr500_tle, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TGT, model_fr500_tgt, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TLT, model_fr500_tlt, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TGE, model_fr500_tge, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TLS, model_fr500_tls, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_THI, model_fr500_thi, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TC, model_fr500_tc, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TNC, model_fr500_tnc, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TN, model_fr500_tn, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TP, model_fr500_tp, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TV, model_fr500_tv, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TNV, model_fr500_tnv, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTRA, model_fr500_ftra, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTNO, model_fr500_ftno, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTNE, model_fr500_ftne, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTEQ, model_fr500_fteq, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTLG, model_fr500_ftlg, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTUE, model_fr500_ftue, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTUL, model_fr500_ftul, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTGE, model_fr500_ftge, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTLT, model_fr500_ftlt, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTUGE, model_fr500_ftuge, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTUG, model_fr500_ftug, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTLE, model_fr500_ftle, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTGT, model_fr500_ftgt, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTULE, model_fr500_ftule, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTU, model_fr500_ftu, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTO, model_fr500_fto, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TIRA, model_fr500_tira, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TINO, model_fr500_tino, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TIEQ, model_fr500_tieq, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TINE, model_fr500_tine, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TILE, model_fr500_tile, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TIGT, model_fr500_tigt, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TILT, model_fr500_tilt, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TIGE, model_fr500_tige, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TILS, model_fr500_tils, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TIHI, model_fr500_tihi, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TIC, model_fr500_tic, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TINC, model_fr500_tinc, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TIN, model_fr500_tin, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TIP, model_fr500_tip, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TIV, model_fr500_tiv, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TINV, model_fr500_tinv, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTIRA, model_fr500_ftira, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTINO, model_fr500_ftino, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTINE, model_fr500_ftine, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTIEQ, model_fr500_ftieq, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTILG, model_fr500_ftilg, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTIUE, model_fr500_ftiue, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTIUL, model_fr500_ftiul, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTIGE, model_fr500_ftige, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTILT, model_fr500_ftilt, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTIUGE, model_fr500_ftiuge, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTIUG, model_fr500_ftiug, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTILE, model_fr500_ftile, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTIGT, model_fr500_ftigt, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTIULE, model_fr500_ftiule, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTIU, model_fr500_ftiu, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTIO, model_fr500_ftio, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_BREAK, model_fr500_break, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MTRAP, model_fr500_mtrap, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ANDCR, model_fr500_andcr, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ORCR, model_fr500_orcr, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_XORCR, model_fr500_xorcr, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NANDCR, model_fr500_nandcr, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NORCR, model_fr500_norcr, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ANDNCR, model_fr500_andncr, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ORNCR, model_fr500_orncr, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NANDNCR, model_fr500_nandncr, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NORNCR, model_fr500_norncr, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NOTCR, model_fr500_notcr, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CKRA, model_fr500_ckra, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CKNO, model_fr500_ckno, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CKEQ, model_fr500_ckeq, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CKNE, model_fr500_ckne, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CKLE, model_fr500_ckle, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CKGT, model_fr500_ckgt, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CKLT, model_fr500_cklt, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CKGE, model_fr500_ckge, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CKLS, model_fr500_ckls, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CKHI, model_fr500_ckhi, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CKC, model_fr500_ckc, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CKNC, model_fr500_cknc, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CKN, model_fr500_ckn, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CKP, model_fr500_ckp, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CKV, model_fr500_ckv, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CKNV, model_fr500_cknv, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_FCKRA, model_fr500_fckra, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_FCKNO, model_fr500_fckno, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_FCKNE, model_fr500_fckne, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_FCKEQ, model_fr500_fckeq, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_FCKLG, model_fr500_fcklg, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_FCKUE, model_fr500_fckue, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_FCKUL, model_fr500_fckul, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_FCKGE, model_fr500_fckge, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_FCKLT, model_fr500_fcklt, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_FCKUGE, model_fr500_fckuge, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_FCKUG, model_fr500_fckug, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_FCKLE, model_fr500_fckle, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_FCKGT, model_fr500_fckgt, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_FCKULE, model_fr500_fckule, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_FCKU, model_fr500_fcku, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_FCKO, model_fr500_fcko, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CCKRA, model_fr500_cckra, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CCKNO, model_fr500_cckno, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CCKEQ, model_fr500_cckeq, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CCKNE, model_fr500_cckne, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CCKLE, model_fr500_cckle, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CCKGT, model_fr500_cckgt, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CCKLT, model_fr500_ccklt, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CCKGE, model_fr500_cckge, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CCKLS, model_fr500_cckls, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CCKHI, model_fr500_cckhi, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CCKC, model_fr500_cckc, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CCKNC, model_fr500_ccknc, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CCKN, model_fr500_cckn, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CCKP, model_fr500_cckp, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CCKV, model_fr500_cckv, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CCKNV, model_fr500_ccknv, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CFCKRA, model_fr500_cfckra, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CFCKNO, model_fr500_cfckno, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CFCKNE, model_fr500_cfckne, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CFCKEQ, model_fr500_cfckeq, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CFCKLG, model_fr500_cfcklg, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CFCKUE, model_fr500_cfckue, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CFCKUL, model_fr500_cfckul, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CFCKGE, model_fr500_cfckge, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CFCKLT, model_fr500_cfcklt, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CFCKUGE, model_fr500_cfckuge, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CFCKUG, model_fr500_cfckug, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CFCKLE, model_fr500_cfckle, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CFCKGT, model_fr500_cfckgt, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CFCKULE, model_fr500_cfckule, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CFCKU, model_fr500_cfcku, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CFCKO, model_fr500_cfcko, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CJMPL, model_fr500_cjmpl, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_CCALLL, model_fr500_ccalll, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_ICI, model_fr500_ici, { { (int) UNIT_FR500_U_ICI, 1, 1 } } }, + { FRVBF_INSN_DCI, model_fr500_dci, { { (int) UNIT_FR500_U_DCI, 1, 1 } } }, + { FRVBF_INSN_ICEI, model_fr500_icei, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_DCEI, model_fr500_dcei, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_DCF, model_fr500_dcf, { { (int) UNIT_FR500_U_DCF, 1, 1 } } }, + { FRVBF_INSN_DCEF, model_fr500_dcef, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_WITLB, model_fr500_witlb, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_WDTLB, model_fr500_wdtlb, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ITLBI, model_fr500_itlbi, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_DTLBI, model_fr500_dtlbi, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ICPL, model_fr500_icpl, { { (int) UNIT_FR500_U_ICPL, 1, 1 } } }, + { FRVBF_INSN_DCPL, model_fr500_dcpl, { { (int) UNIT_FR500_U_DCPL, 1, 1 } } }, + { FRVBF_INSN_ICUL, model_fr500_icul, { { (int) UNIT_FR500_U_ICUL, 1, 1 } } }, + { FRVBF_INSN_DCUL, model_fr500_dcul, { { (int) UNIT_FR500_U_DCUL, 1, 1 } } }, + { FRVBF_INSN_BAR, model_fr500_bar, { { (int) UNIT_FR500_U_BARRIER, 1, 1 } } }, + { FRVBF_INSN_MEMBAR, model_fr500_membar, { { (int) UNIT_FR500_U_MEMBAR, 1, 1 } } }, + { FRVBF_INSN_COP1, model_fr500_cop1, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_COP2, model_fr500_cop2, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLRGR, model_fr500_clrgr, { { (int) UNIT_FR500_U_CLRGR, 1, 1 } } }, + { FRVBF_INSN_CLRFR, model_fr500_clrfr, { { (int) UNIT_FR500_U_CLRFR, 1, 1 } } }, + { FRVBF_INSN_CLRGA, model_fr500_clrga, { { (int) UNIT_FR500_U_CLRGR, 1, 1 } } }, + { FRVBF_INSN_CLRFA, model_fr500_clrfa, { { (int) UNIT_FR500_U_CLRFR, 1, 1 } } }, + { FRVBF_INSN_COMMITGR, model_fr500_commitgr, { { (int) UNIT_FR500_U_COMMIT, 1, 1 } } }, + { FRVBF_INSN_COMMITFR, model_fr500_commitfr, { { (int) UNIT_FR500_U_COMMIT, 1, 1 } } }, + { FRVBF_INSN_COMMITGA, model_fr500_commitga, { { (int) UNIT_FR500_U_COMMIT, 1, 1 } } }, + { FRVBF_INSN_COMMITFA, model_fr500_commitfa, { { (int) UNIT_FR500_U_COMMIT, 1, 1 } } }, + { FRVBF_INSN_FITOS, model_fr500_fitos, { { (int) UNIT_FR500_U_FLOAT_CONVERT, 1, 1 } } }, + { FRVBF_INSN_FSTOI, model_fr500_fstoi, { { (int) UNIT_FR500_U_FLOAT_CONVERT, 1, 1 } } }, + { FRVBF_INSN_FITOD, model_fr500_fitod, { { (int) UNIT_FR500_U_FLOAT_CONVERT, 1, 1 } } }, + { FRVBF_INSN_FDTOI, model_fr500_fdtoi, { { (int) UNIT_FR500_U_FLOAT_CONVERT, 1, 1 } } }, + { FRVBF_INSN_FDITOS, model_fr500_fditos, { { (int) UNIT_FR500_U_FLOAT_DUAL_CONVERT, 1, 1 } } }, + { FRVBF_INSN_FDSTOI, model_fr500_fdstoi, { { (int) UNIT_FR500_U_FLOAT_DUAL_CONVERT, 1, 1 } } }, + { FRVBF_INSN_NFDITOS, model_fr500_nfditos, { { (int) UNIT_FR500_U_FLOAT_DUAL_CONVERT, 1, 1 } } }, + { FRVBF_INSN_NFDSTOI, model_fr500_nfdstoi, { { (int) UNIT_FR500_U_FLOAT_DUAL_CONVERT, 1, 1 } } }, + { FRVBF_INSN_CFITOS, model_fr500_cfitos, { { (int) UNIT_FR500_U_FLOAT_CONVERT, 1, 1 } } }, + { FRVBF_INSN_CFSTOI, model_fr500_cfstoi, { { (int) UNIT_FR500_U_FLOAT_CONVERT, 1, 1 } } }, + { FRVBF_INSN_NFITOS, model_fr500_nfitos, { { (int) UNIT_FR500_U_FLOAT_CONVERT, 1, 1 } } }, + { FRVBF_INSN_NFSTOI, model_fr500_nfstoi, { { (int) UNIT_FR500_U_FLOAT_CONVERT, 1, 1 } } }, + { FRVBF_INSN_FMOVS, model_fr500_fmovs, { { (int) UNIT_FR500_U_FR2FR, 1, 1 } } }, + { FRVBF_INSN_FMOVD, model_fr500_fmovd, { { (int) UNIT_FR500_U_FR2FR, 1, 1 } } }, + { FRVBF_INSN_FDMOVS, model_fr500_fdmovs, { { (int) UNIT_FR500_U_FR2FR, 1, 1 } } }, + { FRVBF_INSN_CFMOVS, model_fr500_cfmovs, { { (int) UNIT_FR500_U_FR2FR, 1, 1 } } }, + { FRVBF_INSN_FNEGS, model_fr500_fnegs, { { (int) UNIT_FR500_U_FLOAT_ARITH, 1, 1 } } }, + { FRVBF_INSN_FNEGD, model_fr500_fnegd, { { (int) UNIT_FR500_U_FLOAT_ARITH, 1, 1 } } }, + { FRVBF_INSN_FDNEGS, model_fr500_fdnegs, { { (int) UNIT_FR500_U_FLOAT_DUAL_ARITH, 1, 1 } } }, + { FRVBF_INSN_CFNEGS, model_fr500_cfnegs, { { (int) UNIT_FR500_U_FLOAT_ARITH, 1, 1 } } }, + { FRVBF_INSN_FABSS, model_fr500_fabss, { { (int) UNIT_FR500_U_FLOAT_ARITH, 1, 1 } } }, + { FRVBF_INSN_FABSD, model_fr500_fabsd, { { (int) UNIT_FR500_U_FLOAT_ARITH, 1, 1 } } }, + { FRVBF_INSN_FDABSS, model_fr500_fdabss, { { (int) UNIT_FR500_U_FLOAT_DUAL_ARITH, 1, 1 } } }, + { FRVBF_INSN_CFABSS, model_fr500_cfabss, { { (int) UNIT_FR500_U_FLOAT_ARITH, 1, 1 } } }, + { FRVBF_INSN_FSQRTS, model_fr500_fsqrts, { { (int) UNIT_FR500_U_FLOAT_SQRT, 1, 1 } } }, + { FRVBF_INSN_FDSQRTS, model_fr500_fdsqrts, { { (int) UNIT_FR500_U_FLOAT_DUAL_SQRT, 1, 1 } } }, + { FRVBF_INSN_NFDSQRTS, model_fr500_nfdsqrts, { { (int) UNIT_FR500_U_FLOAT_DUAL_SQRT, 1, 1 } } }, + { FRVBF_INSN_FSQRTD, model_fr500_fsqrtd, { { (int) UNIT_FR500_U_FLOAT_SQRT, 1, 1 } } }, + { FRVBF_INSN_CFSQRTS, model_fr500_cfsqrts, { { (int) UNIT_FR500_U_FLOAT_SQRT, 1, 1 } } }, + { FRVBF_INSN_NFSQRTS, model_fr500_nfsqrts, { { (int) UNIT_FR500_U_FLOAT_SQRT, 1, 1 } } }, + { FRVBF_INSN_FADDS, model_fr500_fadds, { { (int) UNIT_FR500_U_FLOAT_ARITH, 1, 1 } } }, + { FRVBF_INSN_FSUBS, model_fr500_fsubs, { { (int) UNIT_FR500_U_FLOAT_ARITH, 1, 1 } } }, + { FRVBF_INSN_FMULS, model_fr500_fmuls, { { (int) UNIT_FR500_U_FLOAT_ARITH, 1, 1 } } }, + { FRVBF_INSN_FDIVS, model_fr500_fdivs, { { (int) UNIT_FR500_U_FLOAT_DIV, 1, 1 } } }, + { FRVBF_INSN_FADDD, model_fr500_faddd, { { (int) UNIT_FR500_U_FLOAT_ARITH, 1, 1 } } }, + { FRVBF_INSN_FSUBD, model_fr500_fsubd, { { (int) UNIT_FR500_U_FLOAT_ARITH, 1, 1 } } }, + { FRVBF_INSN_FMULD, model_fr500_fmuld, { { (int) UNIT_FR500_U_FLOAT_ARITH, 1, 1 } } }, + { FRVBF_INSN_FDIVD, model_fr500_fdivd, { { (int) UNIT_FR500_U_FLOAT_ARITH, 1, 1 } } }, + { FRVBF_INSN_CFADDS, model_fr500_cfadds, { { (int) UNIT_FR500_U_FLOAT_ARITH, 1, 1 } } }, + { FRVBF_INSN_CFSUBS, model_fr500_cfsubs, { { (int) UNIT_FR500_U_FLOAT_ARITH, 1, 1 } } }, + { FRVBF_INSN_CFMULS, model_fr500_cfmuls, { { (int) UNIT_FR500_U_FLOAT_ARITH, 1, 1 } } }, + { FRVBF_INSN_CFDIVS, model_fr500_cfdivs, { { (int) UNIT_FR500_U_FLOAT_DIV, 1, 1 } } }, + { FRVBF_INSN_NFADDS, model_fr500_nfadds, { { (int) UNIT_FR500_U_FLOAT_ARITH, 1, 1 } } }, + { FRVBF_INSN_NFSUBS, model_fr500_nfsubs, { { (int) UNIT_FR500_U_FLOAT_ARITH, 1, 1 } } }, + { FRVBF_INSN_NFMULS, model_fr500_nfmuls, { { (int) UNIT_FR500_U_FLOAT_ARITH, 1, 1 } } }, + { FRVBF_INSN_NFDIVS, model_fr500_nfdivs, { { (int) UNIT_FR500_U_FLOAT_DIV, 1, 1 } } }, + { FRVBF_INSN_FCMPS, model_fr500_fcmps, { { (int) UNIT_FR500_U_FLOAT_COMPARE, 1, 1 } } }, + { FRVBF_INSN_FCMPD, model_fr500_fcmpd, { { (int) UNIT_FR500_U_FLOAT_COMPARE, 1, 1 } } }, + { FRVBF_INSN_CFCMPS, model_fr500_cfcmps, { { (int) UNIT_FR500_U_FLOAT_COMPARE, 1, 1 } } }, + { FRVBF_INSN_FDCMPS, model_fr500_fdcmps, { { (int) UNIT_FR500_U_FLOAT_DUAL_COMPARE, 1, 1 } } }, + { FRVBF_INSN_FMADDS, model_fr500_fmadds, { { (int) UNIT_FR500_U_FLOAT_DUAL_ARITH, 1, 1 } } }, + { FRVBF_INSN_FMSUBS, model_fr500_fmsubs, { { (int) UNIT_FR500_U_FLOAT_DUAL_ARITH, 1, 1 } } }, + { FRVBF_INSN_FMADDD, model_fr500_fmaddd, { { (int) UNIT_FR500_U_FLOAT_DUAL_ARITH, 1, 1 } } }, + { FRVBF_INSN_FMSUBD, model_fr500_fmsubd, { { (int) UNIT_FR500_U_FLOAT_DUAL_ARITH, 1, 1 } } }, + { FRVBF_INSN_FDMADDS, model_fr500_fdmadds, { { (int) UNIT_FR500_U_FLOAT_DUAL_ARITH, 1, 1 } } }, + { FRVBF_INSN_NFDMADDS, model_fr500_nfdmadds, { { (int) UNIT_FR500_U_FLOAT_DUAL_ARITH, 1, 1 } } }, + { FRVBF_INSN_CFMADDS, model_fr500_cfmadds, { { (int) UNIT_FR500_U_FLOAT_DUAL_ARITH, 1, 1 } } }, + { FRVBF_INSN_CFMSUBS, model_fr500_cfmsubs, { { (int) UNIT_FR500_U_FLOAT_DUAL_ARITH, 1, 1 } } }, + { FRVBF_INSN_NFMADDS, model_fr500_nfmadds, { { (int) UNIT_FR500_U_FLOAT_DUAL_ARITH, 1, 1 } } }, + { FRVBF_INSN_NFMSUBS, model_fr500_nfmsubs, { { (int) UNIT_FR500_U_FLOAT_DUAL_ARITH, 1, 1 } } }, + { FRVBF_INSN_FMAS, model_fr500_fmas, { { (int) UNIT_FR500_U_FLOAT_DUAL_ARITH, 1, 1 } } }, + { FRVBF_INSN_FMSS, model_fr500_fmss, { { (int) UNIT_FR500_U_FLOAT_DUAL_ARITH, 1, 1 } } }, + { FRVBF_INSN_FDMAS, model_fr500_fdmas, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDMSS, model_fr500_fdmss, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFDMAS, model_fr500_nfdmas, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFDMSS, model_fr500_nfdmss, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFMAS, model_fr500_cfmas, { { (int) UNIT_FR500_U_FLOAT_DUAL_ARITH, 1, 1 } } }, + { FRVBF_INSN_CFMSS, model_fr500_cfmss, { { (int) UNIT_FR500_U_FLOAT_DUAL_ARITH, 1, 1 } } }, + { FRVBF_INSN_FMAD, model_fr500_fmad, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FMSD, model_fr500_fmsd, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFMAS, model_fr500_nfmas, { { (int) UNIT_FR500_U_FLOAT_DUAL_ARITH, 1, 1 } } }, + { FRVBF_INSN_NFMSS, model_fr500_nfmss, { { (int) UNIT_FR500_U_FLOAT_DUAL_ARITH, 1, 1 } } }, + { FRVBF_INSN_FDADDS, model_fr500_fdadds, { { (int) UNIT_FR500_U_FLOAT_DUAL_ARITH, 1, 1 } } }, + { FRVBF_INSN_FDSUBS, model_fr500_fdsubs, { { (int) UNIT_FR500_U_FLOAT_DUAL_ARITH, 1, 1 } } }, + { FRVBF_INSN_FDMULS, model_fr500_fdmuls, { { (int) UNIT_FR500_U_FLOAT_DUAL_ARITH, 1, 1 } } }, + { FRVBF_INSN_FDDIVS, model_fr500_fddivs, { { (int) UNIT_FR500_U_FLOAT_DUAL_ARITH, 1, 1 } } }, + { FRVBF_INSN_FDSADS, model_fr500_fdsads, { { (int) UNIT_FR500_U_FLOAT_DUAL_ARITH, 1, 1 } } }, + { FRVBF_INSN_FDMULCS, model_fr500_fdmulcs, { { (int) UNIT_FR500_U_FLOAT_DUAL_ARITH, 1, 1 } } }, + { FRVBF_INSN_NFDMULCS, model_fr500_nfdmulcs, { { (int) UNIT_FR500_U_FLOAT_DUAL_ARITH, 1, 1 } } }, + { FRVBF_INSN_NFDADDS, model_fr500_nfdadds, { { (int) UNIT_FR500_U_FLOAT_DUAL_ARITH, 1, 1 } } }, + { FRVBF_INSN_NFDSUBS, model_fr500_nfdsubs, { { (int) UNIT_FR500_U_FLOAT_DUAL_ARITH, 1, 1 } } }, + { FRVBF_INSN_NFDMULS, model_fr500_nfdmuls, { { (int) UNIT_FR500_U_FLOAT_DUAL_ARITH, 1, 1 } } }, + { FRVBF_INSN_NFDDIVS, model_fr500_nfddivs, { { (int) UNIT_FR500_U_FLOAT_DUAL_ARITH, 1, 1 } } }, + { FRVBF_INSN_NFDSADS, model_fr500_nfdsads, { { (int) UNIT_FR500_U_FLOAT_DUAL_ARITH, 1, 1 } } }, + { FRVBF_INSN_NFDCMPS, model_fr500_nfdcmps, { { (int) UNIT_FR500_U_FLOAT_DUAL_COMPARE, 1, 1 } } }, + { FRVBF_INSN_MHSETLOS, model_fr500_mhsetlos, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MHSETHIS, model_fr500_mhsethis, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MHDSETS, model_fr500_mhdsets, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MHSETLOH, model_fr500_mhsetloh, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MHSETHIH, model_fr500_mhsethih, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MHDSETH, model_fr500_mhdseth, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MAND, model_fr500_mand, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } }, + { FRVBF_INSN_MOR, model_fr500_mor, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } }, + { FRVBF_INSN_MXOR, model_fr500_mxor, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } }, + { FRVBF_INSN_CMAND, model_fr500_cmand, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } }, + { FRVBF_INSN_CMOR, model_fr500_cmor, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } }, + { FRVBF_INSN_CMXOR, model_fr500_cmxor, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } }, + { FRVBF_INSN_MNOT, model_fr500_mnot, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } }, + { FRVBF_INSN_CMNOT, model_fr500_cmnot, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } }, + { FRVBF_INSN_MROTLI, model_fr500_mrotli, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } }, + { FRVBF_INSN_MROTRI, model_fr500_mrotri, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } }, + { FRVBF_INSN_MWCUT, model_fr500_mwcut, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } }, + { FRVBF_INSN_MWCUTI, model_fr500_mwcuti, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } }, + { FRVBF_INSN_MCUT, model_fr500_mcut, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } }, + { FRVBF_INSN_MCUTI, model_fr500_mcuti, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } }, + { FRVBF_INSN_MCUTSS, model_fr500_mcutss, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } }, + { FRVBF_INSN_MCUTSSI, model_fr500_mcutssi, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } }, + { FRVBF_INSN_MDCUTSSI, model_fr500_mdcutssi, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MAVEH, model_fr500_maveh, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } }, + { FRVBF_INSN_MSLLHI, model_fr500_msllhi, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } }, + { FRVBF_INSN_MSRLHI, model_fr500_msrlhi, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } }, + { FRVBF_INSN_MSRAHI, model_fr500_msrahi, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } }, + { FRVBF_INSN_MDROTLI, model_fr500_mdrotli, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MCPLHI, model_fr500_mcplhi, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MCPLI, model_fr500_mcpli, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MSATHS, model_fr500_msaths, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } }, + { FRVBF_INSN_MQSATHS, model_fr500_mqsaths, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MSATHU, model_fr500_msathu, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } }, + { FRVBF_INSN_MCMPSH, model_fr500_mcmpsh, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } }, + { FRVBF_INSN_MCMPUH, model_fr500_mcmpuh, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } }, + { FRVBF_INSN_MABSHS, model_fr500_mabshs, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MADDHSS, model_fr500_maddhss, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } }, + { FRVBF_INSN_MADDHUS, model_fr500_maddhus, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } }, + { FRVBF_INSN_MSUBHSS, model_fr500_msubhss, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } }, + { FRVBF_INSN_MSUBHUS, model_fr500_msubhus, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } }, + { FRVBF_INSN_CMADDHSS, model_fr500_cmaddhss, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } }, + { FRVBF_INSN_CMADDHUS, model_fr500_cmaddhus, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } }, + { FRVBF_INSN_CMSUBHSS, model_fr500_cmsubhss, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } }, + { FRVBF_INSN_CMSUBHUS, model_fr500_cmsubhus, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } }, + { FRVBF_INSN_MQADDHSS, model_fr500_mqaddhss, { { (int) UNIT_FR500_U_MEDIA_QUAD_ARITH, 1, 1 } } }, + { FRVBF_INSN_MQADDHUS, model_fr500_mqaddhus, { { (int) UNIT_FR500_U_MEDIA_QUAD_ARITH, 1, 1 } } }, + { FRVBF_INSN_MQSUBHSS, model_fr500_mqsubhss, { { (int) UNIT_FR500_U_MEDIA_QUAD_ARITH, 1, 1 } } }, + { FRVBF_INSN_MQSUBHUS, model_fr500_mqsubhus, { { (int) UNIT_FR500_U_MEDIA_QUAD_ARITH, 1, 1 } } }, + { FRVBF_INSN_CMQADDHSS, model_fr500_cmqaddhss, { { (int) UNIT_FR500_U_MEDIA_QUAD_ARITH, 1, 1 } } }, + { FRVBF_INSN_CMQADDHUS, model_fr500_cmqaddhus, { { (int) UNIT_FR500_U_MEDIA_QUAD_ARITH, 1, 1 } } }, + { FRVBF_INSN_CMQSUBHSS, model_fr500_cmqsubhss, { { (int) UNIT_FR500_U_MEDIA_QUAD_ARITH, 1, 1 } } }, + { FRVBF_INSN_CMQSUBHUS, model_fr500_cmqsubhus, { { (int) UNIT_FR500_U_MEDIA_QUAD_ARITH, 1, 1 } } }, + { FRVBF_INSN_MADDACCS, model_fr500_maddaccs, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MSUBACCS, model_fr500_msubaccs, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MDADDACCS, model_fr500_mdaddaccs, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MDSUBACCS, model_fr500_mdsubaccs, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MASACCS, model_fr500_masaccs, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MDASACCS, model_fr500_mdasaccs, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MMULHS, model_fr500_mmulhs, { { (int) UNIT_FR500_U_MEDIA_DUAL_MUL, 1, 1 } } }, + { FRVBF_INSN_MMULHU, model_fr500_mmulhu, { { (int) UNIT_FR500_U_MEDIA_DUAL_MUL, 1, 1 } } }, + { FRVBF_INSN_MMULXHS, model_fr500_mmulxhs, { { (int) UNIT_FR500_U_MEDIA_DUAL_MUL, 1, 1 } } }, + { FRVBF_INSN_MMULXHU, model_fr500_mmulxhu, { { (int) UNIT_FR500_U_MEDIA_DUAL_MUL, 1, 1 } } }, + { FRVBF_INSN_CMMULHS, model_fr500_cmmulhs, { { (int) UNIT_FR500_U_MEDIA_DUAL_MUL, 1, 1 } } }, + { FRVBF_INSN_CMMULHU, model_fr500_cmmulhu, { { (int) UNIT_FR500_U_MEDIA_DUAL_MUL, 1, 1 } } }, + { FRVBF_INSN_MQMULHS, model_fr500_mqmulhs, { { (int) UNIT_FR500_U_MEDIA_QUAD_MUL, 1, 1 } } }, + { FRVBF_INSN_MQMULHU, model_fr500_mqmulhu, { { (int) UNIT_FR500_U_MEDIA_QUAD_MUL, 1, 1 } } }, + { FRVBF_INSN_MQMULXHS, model_fr500_mqmulxhs, { { (int) UNIT_FR500_U_MEDIA_QUAD_MUL, 1, 1 } } }, + { FRVBF_INSN_MQMULXHU, model_fr500_mqmulxhu, { { (int) UNIT_FR500_U_MEDIA_QUAD_MUL, 1, 1 } } }, + { FRVBF_INSN_CMQMULHS, model_fr500_cmqmulhs, { { (int) UNIT_FR500_U_MEDIA_QUAD_MUL, 1, 1 } } }, + { FRVBF_INSN_CMQMULHU, model_fr500_cmqmulhu, { { (int) UNIT_FR500_U_MEDIA_QUAD_MUL, 1, 1 } } }, + { FRVBF_INSN_MMACHS, model_fr500_mmachs, { { (int) UNIT_FR500_U_MEDIA_DUAL_MUL, 1, 1 } } }, + { FRVBF_INSN_MMACHU, model_fr500_mmachu, { { (int) UNIT_FR500_U_MEDIA_DUAL_MUL, 1, 1 } } }, + { FRVBF_INSN_MMRDHS, model_fr500_mmrdhs, { { (int) UNIT_FR500_U_MEDIA_DUAL_MUL, 1, 1 } } }, + { FRVBF_INSN_MMRDHU, model_fr500_mmrdhu, { { (int) UNIT_FR500_U_MEDIA_DUAL_MUL, 1, 1 } } }, + { FRVBF_INSN_CMMACHS, model_fr500_cmmachs, { { (int) UNIT_FR500_U_MEDIA_DUAL_MUL, 1, 1 } } }, + { FRVBF_INSN_CMMACHU, model_fr500_cmmachu, { { (int) UNIT_FR500_U_MEDIA_DUAL_MUL, 1, 1 } } }, + { FRVBF_INSN_MQMACHS, model_fr500_mqmachs, { { (int) UNIT_FR500_U_MEDIA_QUAD_MUL, 1, 1 } } }, + { FRVBF_INSN_MQMACHU, model_fr500_mqmachu, { { (int) UNIT_FR500_U_MEDIA_QUAD_MUL, 1, 1 } } }, + { FRVBF_INSN_CMQMACHS, model_fr500_cmqmachs, { { (int) UNIT_FR500_U_MEDIA_QUAD_MUL, 1, 1 } } }, + { FRVBF_INSN_CMQMACHU, model_fr500_cmqmachu, { { (int) UNIT_FR500_U_MEDIA_QUAD_MUL, 1, 1 } } }, + { FRVBF_INSN_MQXMACHS, model_fr500_mqxmachs, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQXMACXHS, model_fr500_mqxmacxhs, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQMACXHS, model_fr500_mqmacxhs, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MCPXRS, model_fr500_mcpxrs, { { (int) UNIT_FR500_U_MEDIA_DUAL_MUL, 1, 1 } } }, + { FRVBF_INSN_MCPXRU, model_fr500_mcpxru, { { (int) UNIT_FR500_U_MEDIA_DUAL_MUL, 1, 1 } } }, + { FRVBF_INSN_MCPXIS, model_fr500_mcpxis, { { (int) UNIT_FR500_U_MEDIA_DUAL_MUL, 1, 1 } } }, + { FRVBF_INSN_MCPXIU, model_fr500_mcpxiu, { { (int) UNIT_FR500_U_MEDIA_DUAL_MUL, 1, 1 } } }, + { FRVBF_INSN_CMCPXRS, model_fr500_cmcpxrs, { { (int) UNIT_FR500_U_MEDIA_DUAL_MUL, 1, 1 } } }, + { FRVBF_INSN_CMCPXRU, model_fr500_cmcpxru, { { (int) UNIT_FR500_U_MEDIA_DUAL_MUL, 1, 1 } } }, + { FRVBF_INSN_CMCPXIS, model_fr500_cmcpxis, { { (int) UNIT_FR500_U_MEDIA_DUAL_MUL, 1, 1 } } }, + { FRVBF_INSN_CMCPXIU, model_fr500_cmcpxiu, { { (int) UNIT_FR500_U_MEDIA_DUAL_MUL, 1, 1 } } }, + { FRVBF_INSN_MQCPXRS, model_fr500_mqcpxrs, { { (int) UNIT_FR500_U_MEDIA_QUAD_COMPLEX, 1, 1 } } }, + { FRVBF_INSN_MQCPXRU, model_fr500_mqcpxru, { { (int) UNIT_FR500_U_MEDIA_QUAD_COMPLEX, 1, 1 } } }, + { FRVBF_INSN_MQCPXIS, model_fr500_mqcpxis, { { (int) UNIT_FR500_U_MEDIA_QUAD_COMPLEX, 1, 1 } } }, + { FRVBF_INSN_MQCPXIU, model_fr500_mqcpxiu, { { (int) UNIT_FR500_U_MEDIA_QUAD_COMPLEX, 1, 1 } } }, + { FRVBF_INSN_MEXPDHW, model_fr500_mexpdhw, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } }, + { FRVBF_INSN_CMEXPDHW, model_fr500_cmexpdhw, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } }, + { FRVBF_INSN_MEXPDHD, model_fr500_mexpdhd, { { (int) UNIT_FR500_U_MEDIA_DUAL_EXPAND, 1, 1 } } }, + { FRVBF_INSN_CMEXPDHD, model_fr500_cmexpdhd, { { (int) UNIT_FR500_U_MEDIA_DUAL_EXPAND, 1, 1 } } }, + { FRVBF_INSN_MPACKH, model_fr500_mpackh, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } }, + { FRVBF_INSN_MDPACKH, model_fr500_mdpackh, { { (int) UNIT_FR500_U_MEDIA_QUAD_ARITH, 1, 1 } } }, + { FRVBF_INSN_MUNPACKH, model_fr500_munpackh, { { (int) UNIT_FR500_U_MEDIA_DUAL_EXPAND, 1, 1 } } }, + { FRVBF_INSN_MDUNPACKH, model_fr500_mdunpackh, { { (int) UNIT_FR500_U_MEDIA_DUAL_UNPACK, 1, 1 } } }, + { FRVBF_INSN_MBTOH, model_fr500_mbtoh, { { (int) UNIT_FR500_U_MEDIA_DUAL_BTOH, 1, 1 } } }, + { FRVBF_INSN_CMBTOH, model_fr500_cmbtoh, { { (int) UNIT_FR500_U_MEDIA_DUAL_BTOH, 1, 1 } } }, + { FRVBF_INSN_MHTOB, model_fr500_mhtob, { { (int) UNIT_FR500_U_MEDIA_DUAL_HTOB, 1, 1 } } }, + { FRVBF_INSN_CMHTOB, model_fr500_cmhtob, { { (int) UNIT_FR500_U_MEDIA_DUAL_HTOB, 1, 1 } } }, + { FRVBF_INSN_MBTOHE, model_fr500_mbtohe, { { (int) UNIT_FR500_U_MEDIA_DUAL_BTOHE, 1, 1 } } }, + { FRVBF_INSN_CMBTOHE, model_fr500_cmbtohe, { { (int) UNIT_FR500_U_MEDIA_DUAL_BTOHE, 1, 1 } } }, + { FRVBF_INSN_MNOP, model_fr500_mnop, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MCLRACC_0, model_fr500_mclracc_0, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } }, + { FRVBF_INSN_MCLRACC_1, model_fr500_mclracc_1, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } }, + { FRVBF_INSN_MRDACC, model_fr500_mrdacc, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } }, + { FRVBF_INSN_MRDACCG, model_fr500_mrdaccg, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } }, + { FRVBF_INSN_MWTACC, model_fr500_mwtacc, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } }, + { FRVBF_INSN_MWTACCG, model_fr500_mwtaccg, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } }, + { FRVBF_INSN_MCOP1, model_fr500_mcop1, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MCOP2, model_fr500_mcop2, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FNOP, model_fr500_fnop, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, +}; + +/* Model timing data for `tomcat'. */ + +static const INSN_TIMING tomcat_timing[] = { + { FRVBF_INSN_X_INVALID, 0, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_X_AFTER, 0, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_X_BEFORE, 0, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_X_CTI_CHAIN, 0, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_X_CHAIN, 0, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_X_BEGIN, 0, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ADD, model_tomcat_add, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SUB, model_tomcat_sub, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_AND, model_tomcat_and, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_OR, model_tomcat_or, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_XOR, model_tomcat_xor, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NOT, model_tomcat_not, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SDIV, model_tomcat_sdiv, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NSDIV, model_tomcat_nsdiv, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_UDIV, model_tomcat_udiv, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NUDIV, model_tomcat_nudiv, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SMUL, model_tomcat_smul, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_UMUL, model_tomcat_umul, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SMU, model_tomcat_smu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SMASS, model_tomcat_smass, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SMSSS, model_tomcat_smsss, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SLL, model_tomcat_sll, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SRL, model_tomcat_srl, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SRA, model_tomcat_sra, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SLASS, model_tomcat_slass, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SCUTSS, model_tomcat_scutss, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SCAN, model_tomcat_scan, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CADD, model_tomcat_cadd, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSUB, model_tomcat_csub, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CAND, model_tomcat_cand, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_COR, model_tomcat_cor, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CXOR, model_tomcat_cxor, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CNOT, model_tomcat_cnot, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSMUL, model_tomcat_csmul, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSDIV, model_tomcat_csdiv, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CUDIV, model_tomcat_cudiv, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSLL, model_tomcat_csll, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSRL, model_tomcat_csrl, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSRA, model_tomcat_csra, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSCAN, model_tomcat_cscan, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ADDCC, model_tomcat_addcc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SUBCC, model_tomcat_subcc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ANDCC, model_tomcat_andcc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ORCC, model_tomcat_orcc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_XORCC, model_tomcat_xorcc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SLLCC, model_tomcat_sllcc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SRLCC, model_tomcat_srlcc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SRACC, model_tomcat_sracc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SMULCC, model_tomcat_smulcc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_UMULCC, model_tomcat_umulcc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CADDCC, model_tomcat_caddcc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSUBCC, model_tomcat_csubcc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSMULCC, model_tomcat_csmulcc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CANDCC, model_tomcat_candcc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CORCC, model_tomcat_corcc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CXORCC, model_tomcat_cxorcc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSLLCC, model_tomcat_csllcc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSRLCC, model_tomcat_csrlcc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSRACC, model_tomcat_csracc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ADDX, model_tomcat_addx, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SUBX, model_tomcat_subx, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ADDXCC, model_tomcat_addxcc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SUBXCC, model_tomcat_subxcc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ADDSS, model_tomcat_addss, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SUBSS, model_tomcat_subss, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ADDI, model_tomcat_addi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SUBI, model_tomcat_subi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ANDI, model_tomcat_andi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ORI, model_tomcat_ori, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_XORI, model_tomcat_xori, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SDIVI, model_tomcat_sdivi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NSDIVI, model_tomcat_nsdivi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_UDIVI, model_tomcat_udivi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NUDIVI, model_tomcat_nudivi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SMULI, model_tomcat_smuli, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_UMULI, model_tomcat_umuli, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SLLI, model_tomcat_slli, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SRLI, model_tomcat_srli, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SRAI, model_tomcat_srai, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SCANI, model_tomcat_scani, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ADDICC, model_tomcat_addicc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SUBICC, model_tomcat_subicc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ANDICC, model_tomcat_andicc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ORICC, model_tomcat_oricc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_XORICC, model_tomcat_xoricc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SMULICC, model_tomcat_smulicc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_UMULICC, model_tomcat_umulicc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SLLICC, model_tomcat_sllicc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SRLICC, model_tomcat_srlicc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SRAICC, model_tomcat_sraicc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ADDXI, model_tomcat_addxi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SUBXI, model_tomcat_subxi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ADDXICC, model_tomcat_addxicc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SUBXICC, model_tomcat_subxicc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMPB, model_tomcat_cmpb, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMPBA, model_tomcat_cmpba, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SETLO, model_tomcat_setlo, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SETHI, model_tomcat_sethi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SETLOS, model_tomcat_setlos, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDSB, model_tomcat_ldsb, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDUB, model_tomcat_ldub, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDSH, model_tomcat_ldsh, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDUH, model_tomcat_lduh, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LD, model_tomcat_ld, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDBF, model_tomcat_ldbf, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDHF, model_tomcat_ldhf, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDF, model_tomcat_ldf, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDC, model_tomcat_ldc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDSB, model_tomcat_nldsb, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDUB, model_tomcat_nldub, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDSH, model_tomcat_nldsh, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDUH, model_tomcat_nlduh, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLD, model_tomcat_nld, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDBF, model_tomcat_nldbf, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDHF, model_tomcat_nldhf, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDF, model_tomcat_nldf, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDD, model_tomcat_ldd, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDDF, model_tomcat_lddf, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDDC, model_tomcat_lddc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDD, model_tomcat_nldd, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDDF, model_tomcat_nlddf, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDQ, model_tomcat_ldq, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDQF, model_tomcat_ldqf, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDQC, model_tomcat_ldqc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDQ, model_tomcat_nldq, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDQF, model_tomcat_nldqf, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDSBU, model_tomcat_ldsbu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDUBU, model_tomcat_ldubu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDSHU, model_tomcat_ldshu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDUHU, model_tomcat_lduhu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDU, model_tomcat_ldu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDSBU, model_tomcat_nldsbu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDUBU, model_tomcat_nldubu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDSHU, model_tomcat_nldshu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDUHU, model_tomcat_nlduhu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDU, model_tomcat_nldu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDBFU, model_tomcat_ldbfu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDHFU, model_tomcat_ldhfu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDFU, model_tomcat_ldfu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDCU, model_tomcat_ldcu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDBFU, model_tomcat_nldbfu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDHFU, model_tomcat_nldhfu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDFU, model_tomcat_nldfu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDDU, model_tomcat_lddu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDDU, model_tomcat_nlddu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDDFU, model_tomcat_lddfu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDDCU, model_tomcat_lddcu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDDFU, model_tomcat_nlddfu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDQU, model_tomcat_ldqu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDQU, model_tomcat_nldqu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDQFU, model_tomcat_ldqfu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDQCU, model_tomcat_ldqcu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDQFU, model_tomcat_nldqfu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDSBI, model_tomcat_ldsbi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDSHI, model_tomcat_ldshi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDI, model_tomcat_ldi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDUBI, model_tomcat_ldubi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDUHI, model_tomcat_lduhi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDBFI, model_tomcat_ldbfi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDHFI, model_tomcat_ldhfi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDFI, model_tomcat_ldfi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDSBI, model_tomcat_nldsbi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDUBI, model_tomcat_nldubi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDSHI, model_tomcat_nldshi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDUHI, model_tomcat_nlduhi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDI, model_tomcat_nldi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDBFI, model_tomcat_nldbfi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDHFI, model_tomcat_nldhfi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDFI, model_tomcat_nldfi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDDI, model_tomcat_lddi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDDFI, model_tomcat_lddfi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDDI, model_tomcat_nlddi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDDFI, model_tomcat_nlddfi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDQI, model_tomcat_ldqi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDQFI, model_tomcat_ldqfi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDQFI, model_tomcat_nldqfi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STB, model_tomcat_stb, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STH, model_tomcat_sth, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ST, model_tomcat_st, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STBF, model_tomcat_stbf, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STHF, model_tomcat_sthf, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STF, model_tomcat_stf, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STC, model_tomcat_stc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_RSTB, model_tomcat_rstb, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_RSTH, model_tomcat_rsth, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_RST, model_tomcat_rst, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_RSTBF, model_tomcat_rstbf, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_RSTHF, model_tomcat_rsthf, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_RSTF, model_tomcat_rstf, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STD, model_tomcat_std, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STDF, model_tomcat_stdf, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STDC, model_tomcat_stdc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_RSTD, model_tomcat_rstd, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_RSTDF, model_tomcat_rstdf, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STQ, model_tomcat_stq, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STQF, model_tomcat_stqf, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STQC, model_tomcat_stqc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_RSTQ, model_tomcat_rstq, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_RSTQF, model_tomcat_rstqf, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STBU, model_tomcat_stbu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STHU, model_tomcat_sthu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STU, model_tomcat_stu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STBFU, model_tomcat_stbfu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STHFU, model_tomcat_sthfu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STFU, model_tomcat_stfu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STCU, model_tomcat_stcu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STDU, model_tomcat_stdu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STDFU, model_tomcat_stdfu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STDCU, model_tomcat_stdcu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STQU, model_tomcat_stqu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STQFU, model_tomcat_stqfu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STQCU, model_tomcat_stqcu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLDSB, model_tomcat_cldsb, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLDUB, model_tomcat_cldub, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLDSH, model_tomcat_cldsh, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLDUH, model_tomcat_clduh, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLD, model_tomcat_cld, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLDBF, model_tomcat_cldbf, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLDHF, model_tomcat_cldhf, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLDF, model_tomcat_cldf, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLDD, model_tomcat_cldd, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLDDF, model_tomcat_clddf, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLDQ, model_tomcat_cldq, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLDSBU, model_tomcat_cldsbu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLDUBU, model_tomcat_cldubu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLDSHU, model_tomcat_cldshu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLDUHU, model_tomcat_clduhu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLDU, model_tomcat_cldu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLDBFU, model_tomcat_cldbfu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLDHFU, model_tomcat_cldhfu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLDFU, model_tomcat_cldfu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLDDU, model_tomcat_clddu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLDDFU, model_tomcat_clddfu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLDQU, model_tomcat_cldqu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSTB, model_tomcat_cstb, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSTH, model_tomcat_csth, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CST, model_tomcat_cst, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSTBF, model_tomcat_cstbf, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSTHF, model_tomcat_csthf, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSTF, model_tomcat_cstf, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSTD, model_tomcat_cstd, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSTDF, model_tomcat_cstdf, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSTQ, model_tomcat_cstq, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSTBU, model_tomcat_cstbu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSTHU, model_tomcat_csthu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSTU, model_tomcat_cstu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSTBFU, model_tomcat_cstbfu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSTHFU, model_tomcat_csthfu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSTFU, model_tomcat_cstfu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSTDU, model_tomcat_cstdu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSTDFU, model_tomcat_cstdfu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STBI, model_tomcat_stbi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STHI, model_tomcat_sthi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STI, model_tomcat_sti, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STBFI, model_tomcat_stbfi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STHFI, model_tomcat_sthfi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STFI, model_tomcat_stfi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STDI, model_tomcat_stdi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STDFI, model_tomcat_stdfi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STQI, model_tomcat_stqi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STQFI, model_tomcat_stqfi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SWAP, model_tomcat_swap, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SWAPI, model_tomcat_swapi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSWAP, model_tomcat_cswap, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MOVGF, model_tomcat_movgf, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MOVFG, model_tomcat_movfg, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MOVGFD, model_tomcat_movgfd, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MOVFGD, model_tomcat_movfgd, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MOVGFQ, model_tomcat_movgfq, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MOVFGQ, model_tomcat_movfgq, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMOVGF, model_tomcat_cmovgf, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMOVFG, model_tomcat_cmovfg, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMOVGFD, model_tomcat_cmovgfd, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMOVFGD, model_tomcat_cmovfgd, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MOVGS, model_tomcat_movgs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MOVSG, model_tomcat_movsg, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BRA, model_tomcat_bra, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BNO, model_tomcat_bno, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BEQ, model_tomcat_beq, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BNE, model_tomcat_bne, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BLE, model_tomcat_ble, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BGT, model_tomcat_bgt, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BLT, model_tomcat_blt, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BGE, model_tomcat_bge, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BLS, model_tomcat_bls, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BHI, model_tomcat_bhi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BC, model_tomcat_bc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BNC, model_tomcat_bnc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BN, model_tomcat_bn, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BP, model_tomcat_bp, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BV, model_tomcat_bv, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BNV, model_tomcat_bnv, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBRA, model_tomcat_fbra, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBNO, model_tomcat_fbno, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBNE, model_tomcat_fbne, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBEQ, model_tomcat_fbeq, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBLG, model_tomcat_fblg, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBUE, model_tomcat_fbue, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBUL, model_tomcat_fbul, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBGE, model_tomcat_fbge, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBLT, model_tomcat_fblt, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBUGE, model_tomcat_fbuge, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBUG, model_tomcat_fbug, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBLE, model_tomcat_fble, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBGT, model_tomcat_fbgt, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBULE, model_tomcat_fbule, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBU, model_tomcat_fbu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBO, model_tomcat_fbo, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BCTRLR, model_tomcat_bctrlr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BRALR, model_tomcat_bralr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BNOLR, model_tomcat_bnolr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BEQLR, model_tomcat_beqlr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BNELR, model_tomcat_bnelr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BLELR, model_tomcat_blelr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BGTLR, model_tomcat_bgtlr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BLTLR, model_tomcat_bltlr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BGELR, model_tomcat_bgelr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BLSLR, model_tomcat_blslr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BHILR, model_tomcat_bhilr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BCLR, model_tomcat_bclr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BNCLR, model_tomcat_bnclr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BNLR, model_tomcat_bnlr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BPLR, model_tomcat_bplr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BVLR, model_tomcat_bvlr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BNVLR, model_tomcat_bnvlr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBRALR, model_tomcat_fbralr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBNOLR, model_tomcat_fbnolr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBEQLR, model_tomcat_fbeqlr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBNELR, model_tomcat_fbnelr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBLGLR, model_tomcat_fblglr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBUELR, model_tomcat_fbuelr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBULLR, model_tomcat_fbullr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBGELR, model_tomcat_fbgelr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBLTLR, model_tomcat_fbltlr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBUGELR, model_tomcat_fbugelr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBUGLR, model_tomcat_fbuglr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBLELR, model_tomcat_fblelr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBGTLR, model_tomcat_fbgtlr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBULELR, model_tomcat_fbulelr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBULR, model_tomcat_fbulr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBOLR, model_tomcat_fbolr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BCRALR, model_tomcat_bcralr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BCNOLR, model_tomcat_bcnolr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BCEQLR, model_tomcat_bceqlr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BCNELR, model_tomcat_bcnelr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BCLELR, model_tomcat_bclelr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BCGTLR, model_tomcat_bcgtlr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BCLTLR, model_tomcat_bcltlr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BCGELR, model_tomcat_bcgelr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BCLSLR, model_tomcat_bclslr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BCHILR, model_tomcat_bchilr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BCCLR, model_tomcat_bcclr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BCNCLR, model_tomcat_bcnclr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BCNLR, model_tomcat_bcnlr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BCPLR, model_tomcat_bcplr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BCVLR, model_tomcat_bcvlr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BCNVLR, model_tomcat_bcnvlr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCBRALR, model_tomcat_fcbralr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCBNOLR, model_tomcat_fcbnolr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCBEQLR, model_tomcat_fcbeqlr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCBNELR, model_tomcat_fcbnelr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCBLGLR, model_tomcat_fcblglr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCBUELR, model_tomcat_fcbuelr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCBULLR, model_tomcat_fcbullr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCBGELR, model_tomcat_fcbgelr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCBLTLR, model_tomcat_fcbltlr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCBUGELR, model_tomcat_fcbugelr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCBUGLR, model_tomcat_fcbuglr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCBLELR, model_tomcat_fcblelr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCBGTLR, model_tomcat_fcbgtlr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCBULELR, model_tomcat_fcbulelr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCBULR, model_tomcat_fcbulr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCBOLR, model_tomcat_fcbolr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_JMPL, model_tomcat_jmpl, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CALLL, model_tomcat_calll, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_JMPIL, model_tomcat_jmpil, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CALLIL, model_tomcat_callil, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CALL, model_tomcat_call, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_RETT, model_tomcat_rett, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_REI, model_tomcat_rei, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TRA, model_tomcat_tra, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TNO, model_tomcat_tno, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TEQ, model_tomcat_teq, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TNE, model_tomcat_tne, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TLE, model_tomcat_tle, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TGT, model_tomcat_tgt, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TLT, model_tomcat_tlt, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TGE, model_tomcat_tge, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TLS, model_tomcat_tls, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_THI, model_tomcat_thi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TC, model_tomcat_tc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TNC, model_tomcat_tnc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TN, model_tomcat_tn, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TP, model_tomcat_tp, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TV, model_tomcat_tv, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TNV, model_tomcat_tnv, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTRA, model_tomcat_ftra, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTNO, model_tomcat_ftno, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTNE, model_tomcat_ftne, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTEQ, model_tomcat_fteq, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTLG, model_tomcat_ftlg, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTUE, model_tomcat_ftue, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTUL, model_tomcat_ftul, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTGE, model_tomcat_ftge, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTLT, model_tomcat_ftlt, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTUGE, model_tomcat_ftuge, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTUG, model_tomcat_ftug, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTLE, model_tomcat_ftle, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTGT, model_tomcat_ftgt, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTULE, model_tomcat_ftule, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTU, model_tomcat_ftu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTO, model_tomcat_fto, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TIRA, model_tomcat_tira, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TINO, model_tomcat_tino, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TIEQ, model_tomcat_tieq, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TINE, model_tomcat_tine, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TILE, model_tomcat_tile, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TIGT, model_tomcat_tigt, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TILT, model_tomcat_tilt, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TIGE, model_tomcat_tige, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TILS, model_tomcat_tils, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TIHI, model_tomcat_tihi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TIC, model_tomcat_tic, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TINC, model_tomcat_tinc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TIN, model_tomcat_tin, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TIP, model_tomcat_tip, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TIV, model_tomcat_tiv, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TINV, model_tomcat_tinv, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTIRA, model_tomcat_ftira, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTINO, model_tomcat_ftino, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTINE, model_tomcat_ftine, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTIEQ, model_tomcat_ftieq, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTILG, model_tomcat_ftilg, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTIUE, model_tomcat_ftiue, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTIUL, model_tomcat_ftiul, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTIGE, model_tomcat_ftige, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTILT, model_tomcat_ftilt, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTIUGE, model_tomcat_ftiuge, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTIUG, model_tomcat_ftiug, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTILE, model_tomcat_ftile, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTIGT, model_tomcat_ftigt, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTIULE, model_tomcat_ftiule, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTIU, model_tomcat_ftiu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTIO, model_tomcat_ftio, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BREAK, model_tomcat_break, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MTRAP, model_tomcat_mtrap, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ANDCR, model_tomcat_andcr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ORCR, model_tomcat_orcr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_XORCR, model_tomcat_xorcr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NANDCR, model_tomcat_nandcr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NORCR, model_tomcat_norcr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ANDNCR, model_tomcat_andncr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ORNCR, model_tomcat_orncr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NANDNCR, model_tomcat_nandncr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NORNCR, model_tomcat_norncr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NOTCR, model_tomcat_notcr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CKRA, model_tomcat_ckra, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CKNO, model_tomcat_ckno, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CKEQ, model_tomcat_ckeq, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CKNE, model_tomcat_ckne, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CKLE, model_tomcat_ckle, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CKGT, model_tomcat_ckgt, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CKLT, model_tomcat_cklt, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CKGE, model_tomcat_ckge, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CKLS, model_tomcat_ckls, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CKHI, model_tomcat_ckhi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CKC, model_tomcat_ckc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CKNC, model_tomcat_cknc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CKN, model_tomcat_ckn, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CKP, model_tomcat_ckp, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CKV, model_tomcat_ckv, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CKNV, model_tomcat_cknv, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCKRA, model_tomcat_fckra, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCKNO, model_tomcat_fckno, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCKNE, model_tomcat_fckne, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCKEQ, model_tomcat_fckeq, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCKLG, model_tomcat_fcklg, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCKUE, model_tomcat_fckue, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCKUL, model_tomcat_fckul, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCKGE, model_tomcat_fckge, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCKLT, model_tomcat_fcklt, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCKUGE, model_tomcat_fckuge, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCKUG, model_tomcat_fckug, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCKLE, model_tomcat_fckle, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCKGT, model_tomcat_fckgt, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCKULE, model_tomcat_fckule, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCKU, model_tomcat_fcku, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCKO, model_tomcat_fcko, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CCKRA, model_tomcat_cckra, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CCKNO, model_tomcat_cckno, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CCKEQ, model_tomcat_cckeq, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CCKNE, model_tomcat_cckne, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CCKLE, model_tomcat_cckle, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CCKGT, model_tomcat_cckgt, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CCKLT, model_tomcat_ccklt, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CCKGE, model_tomcat_cckge, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CCKLS, model_tomcat_cckls, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CCKHI, model_tomcat_cckhi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CCKC, model_tomcat_cckc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CCKNC, model_tomcat_ccknc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CCKN, model_tomcat_cckn, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CCKP, model_tomcat_cckp, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CCKV, model_tomcat_cckv, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CCKNV, model_tomcat_ccknv, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFCKRA, model_tomcat_cfckra, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFCKNO, model_tomcat_cfckno, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFCKNE, model_tomcat_cfckne, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFCKEQ, model_tomcat_cfckeq, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFCKLG, model_tomcat_cfcklg, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFCKUE, model_tomcat_cfckue, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFCKUL, model_tomcat_cfckul, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFCKGE, model_tomcat_cfckge, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFCKLT, model_tomcat_cfcklt, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFCKUGE, model_tomcat_cfckuge, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFCKUG, model_tomcat_cfckug, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFCKLE, model_tomcat_cfckle, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFCKGT, model_tomcat_cfckgt, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFCKULE, model_tomcat_cfckule, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFCKU, model_tomcat_cfcku, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFCKO, model_tomcat_cfcko, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CJMPL, model_tomcat_cjmpl, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CCALLL, model_tomcat_ccalll, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ICI, model_tomcat_ici, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_DCI, model_tomcat_dci, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ICEI, model_tomcat_icei, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_DCEI, model_tomcat_dcei, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_DCF, model_tomcat_dcf, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_DCEF, model_tomcat_dcef, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_WITLB, model_tomcat_witlb, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_WDTLB, model_tomcat_wdtlb, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ITLBI, model_tomcat_itlbi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_DTLBI, model_tomcat_dtlbi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ICPL, model_tomcat_icpl, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_DCPL, model_tomcat_dcpl, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ICUL, model_tomcat_icul, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_DCUL, model_tomcat_dcul, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BAR, model_tomcat_bar, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MEMBAR, model_tomcat_membar, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_COP1, model_tomcat_cop1, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_COP2, model_tomcat_cop2, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLRGR, model_tomcat_clrgr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLRFR, model_tomcat_clrfr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLRGA, model_tomcat_clrga, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLRFA, model_tomcat_clrfa, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_COMMITGR, model_tomcat_commitgr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_COMMITFR, model_tomcat_commitfr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_COMMITGA, model_tomcat_commitga, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_COMMITFA, model_tomcat_commitfa, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FITOS, model_tomcat_fitos, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FSTOI, model_tomcat_fstoi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FITOD, model_tomcat_fitod, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDTOI, model_tomcat_fdtoi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDITOS, model_tomcat_fditos, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDSTOI, model_tomcat_fdstoi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFDITOS, model_tomcat_nfditos, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFDSTOI, model_tomcat_nfdstoi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFITOS, model_tomcat_cfitos, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFSTOI, model_tomcat_cfstoi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFITOS, model_tomcat_nfitos, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFSTOI, model_tomcat_nfstoi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FMOVS, model_tomcat_fmovs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FMOVD, model_tomcat_fmovd, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDMOVS, model_tomcat_fdmovs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFMOVS, model_tomcat_cfmovs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FNEGS, model_tomcat_fnegs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FNEGD, model_tomcat_fnegd, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDNEGS, model_tomcat_fdnegs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFNEGS, model_tomcat_cfnegs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FABSS, model_tomcat_fabss, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FABSD, model_tomcat_fabsd, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDABSS, model_tomcat_fdabss, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFABSS, model_tomcat_cfabss, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FSQRTS, model_tomcat_fsqrts, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDSQRTS, model_tomcat_fdsqrts, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFDSQRTS, model_tomcat_nfdsqrts, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FSQRTD, model_tomcat_fsqrtd, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFSQRTS, model_tomcat_cfsqrts, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFSQRTS, model_tomcat_nfsqrts, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FADDS, model_tomcat_fadds, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FSUBS, model_tomcat_fsubs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FMULS, model_tomcat_fmuls, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDIVS, model_tomcat_fdivs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FADDD, model_tomcat_faddd, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FSUBD, model_tomcat_fsubd, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FMULD, model_tomcat_fmuld, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDIVD, model_tomcat_fdivd, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFADDS, model_tomcat_cfadds, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFSUBS, model_tomcat_cfsubs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFMULS, model_tomcat_cfmuls, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFDIVS, model_tomcat_cfdivs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFADDS, model_tomcat_nfadds, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFSUBS, model_tomcat_nfsubs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFMULS, model_tomcat_nfmuls, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFDIVS, model_tomcat_nfdivs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCMPS, model_tomcat_fcmps, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCMPD, model_tomcat_fcmpd, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFCMPS, model_tomcat_cfcmps, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDCMPS, model_tomcat_fdcmps, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FMADDS, model_tomcat_fmadds, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FMSUBS, model_tomcat_fmsubs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FMADDD, model_tomcat_fmaddd, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FMSUBD, model_tomcat_fmsubd, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDMADDS, model_tomcat_fdmadds, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFDMADDS, model_tomcat_nfdmadds, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFMADDS, model_tomcat_cfmadds, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFMSUBS, model_tomcat_cfmsubs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFMADDS, model_tomcat_nfmadds, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFMSUBS, model_tomcat_nfmsubs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FMAS, model_tomcat_fmas, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FMSS, model_tomcat_fmss, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDMAS, model_tomcat_fdmas, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDMSS, model_tomcat_fdmss, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFDMAS, model_tomcat_nfdmas, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFDMSS, model_tomcat_nfdmss, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFMAS, model_tomcat_cfmas, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFMSS, model_tomcat_cfmss, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FMAD, model_tomcat_fmad, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FMSD, model_tomcat_fmsd, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFMAS, model_tomcat_nfmas, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFMSS, model_tomcat_nfmss, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDADDS, model_tomcat_fdadds, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDSUBS, model_tomcat_fdsubs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDMULS, model_tomcat_fdmuls, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDDIVS, model_tomcat_fddivs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDSADS, model_tomcat_fdsads, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDMULCS, model_tomcat_fdmulcs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFDMULCS, model_tomcat_nfdmulcs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFDADDS, model_tomcat_nfdadds, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFDSUBS, model_tomcat_nfdsubs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFDMULS, model_tomcat_nfdmuls, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFDDIVS, model_tomcat_nfddivs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFDSADS, model_tomcat_nfdsads, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFDCMPS, model_tomcat_nfdcmps, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MHSETLOS, model_tomcat_mhsetlos, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MHSETHIS, model_tomcat_mhsethis, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MHDSETS, model_tomcat_mhdsets, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MHSETLOH, model_tomcat_mhsetloh, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MHSETHIH, model_tomcat_mhsethih, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MHDSETH, model_tomcat_mhdseth, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MAND, model_tomcat_mand, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MOR, model_tomcat_mor, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MXOR, model_tomcat_mxor, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMAND, model_tomcat_cmand, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMOR, model_tomcat_cmor, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMXOR, model_tomcat_cmxor, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MNOT, model_tomcat_mnot, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMNOT, model_tomcat_cmnot, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MROTLI, model_tomcat_mrotli, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MROTRI, model_tomcat_mrotri, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MWCUT, model_tomcat_mwcut, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MWCUTI, model_tomcat_mwcuti, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MCUT, model_tomcat_mcut, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MCUTI, model_tomcat_mcuti, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MCUTSS, model_tomcat_mcutss, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MCUTSSI, model_tomcat_mcutssi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MDCUTSSI, model_tomcat_mdcutssi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MAVEH, model_tomcat_maveh, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MSLLHI, model_tomcat_msllhi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MSRLHI, model_tomcat_msrlhi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MSRAHI, model_tomcat_msrahi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MDROTLI, model_tomcat_mdrotli, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MCPLHI, model_tomcat_mcplhi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MCPLI, model_tomcat_mcpli, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MSATHS, model_tomcat_msaths, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQSATHS, model_tomcat_mqsaths, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MSATHU, model_tomcat_msathu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MCMPSH, model_tomcat_mcmpsh, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MCMPUH, model_tomcat_mcmpuh, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MABSHS, model_tomcat_mabshs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MADDHSS, model_tomcat_maddhss, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MADDHUS, model_tomcat_maddhus, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MSUBHSS, model_tomcat_msubhss, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MSUBHUS, model_tomcat_msubhus, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMADDHSS, model_tomcat_cmaddhss, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMADDHUS, model_tomcat_cmaddhus, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMSUBHSS, model_tomcat_cmsubhss, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMSUBHUS, model_tomcat_cmsubhus, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQADDHSS, model_tomcat_mqaddhss, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQADDHUS, model_tomcat_mqaddhus, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQSUBHSS, model_tomcat_mqsubhss, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQSUBHUS, model_tomcat_mqsubhus, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMQADDHSS, model_tomcat_cmqaddhss, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMQADDHUS, model_tomcat_cmqaddhus, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMQSUBHSS, model_tomcat_cmqsubhss, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMQSUBHUS, model_tomcat_cmqsubhus, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MADDACCS, model_tomcat_maddaccs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MSUBACCS, model_tomcat_msubaccs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MDADDACCS, model_tomcat_mdaddaccs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MDSUBACCS, model_tomcat_mdsubaccs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MASACCS, model_tomcat_masaccs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MDASACCS, model_tomcat_mdasaccs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MMULHS, model_tomcat_mmulhs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MMULHU, model_tomcat_mmulhu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MMULXHS, model_tomcat_mmulxhs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MMULXHU, model_tomcat_mmulxhu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMMULHS, model_tomcat_cmmulhs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMMULHU, model_tomcat_cmmulhu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQMULHS, model_tomcat_mqmulhs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQMULHU, model_tomcat_mqmulhu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQMULXHS, model_tomcat_mqmulxhs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQMULXHU, model_tomcat_mqmulxhu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMQMULHS, model_tomcat_cmqmulhs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMQMULHU, model_tomcat_cmqmulhu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MMACHS, model_tomcat_mmachs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MMACHU, model_tomcat_mmachu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MMRDHS, model_tomcat_mmrdhs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MMRDHU, model_tomcat_mmrdhu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMMACHS, model_tomcat_cmmachs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMMACHU, model_tomcat_cmmachu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQMACHS, model_tomcat_mqmachs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQMACHU, model_tomcat_mqmachu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMQMACHS, model_tomcat_cmqmachs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMQMACHU, model_tomcat_cmqmachu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQXMACHS, model_tomcat_mqxmachs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQXMACXHS, model_tomcat_mqxmacxhs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQMACXHS, model_tomcat_mqmacxhs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MCPXRS, model_tomcat_mcpxrs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MCPXRU, model_tomcat_mcpxru, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MCPXIS, model_tomcat_mcpxis, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MCPXIU, model_tomcat_mcpxiu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMCPXRS, model_tomcat_cmcpxrs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMCPXRU, model_tomcat_cmcpxru, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMCPXIS, model_tomcat_cmcpxis, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMCPXIU, model_tomcat_cmcpxiu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQCPXRS, model_tomcat_mqcpxrs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQCPXRU, model_tomcat_mqcpxru, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQCPXIS, model_tomcat_mqcpxis, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQCPXIU, model_tomcat_mqcpxiu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MEXPDHW, model_tomcat_mexpdhw, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMEXPDHW, model_tomcat_cmexpdhw, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MEXPDHD, model_tomcat_mexpdhd, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMEXPDHD, model_tomcat_cmexpdhd, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MPACKH, model_tomcat_mpackh, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MDPACKH, model_tomcat_mdpackh, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MUNPACKH, model_tomcat_munpackh, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MDUNPACKH, model_tomcat_mdunpackh, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MBTOH, model_tomcat_mbtoh, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMBTOH, model_tomcat_cmbtoh, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MHTOB, model_tomcat_mhtob, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMHTOB, model_tomcat_cmhtob, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MBTOHE, model_tomcat_mbtohe, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMBTOHE, model_tomcat_cmbtohe, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MNOP, model_tomcat_mnop, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MCLRACC_0, model_tomcat_mclracc_0, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MCLRACC_1, model_tomcat_mclracc_1, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MRDACC, model_tomcat_mrdacc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MRDACCG, model_tomcat_mrdaccg, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MWTACC, model_tomcat_mwtacc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MWTACCG, model_tomcat_mwtaccg, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MCOP1, model_tomcat_mcop1, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MCOP2, model_tomcat_mcop2, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FNOP, model_tomcat_fnop, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, +}; + +/* Model timing data for `fr400'. */ + +static const INSN_TIMING fr400_timing[] = { + { FRVBF_INSN_X_INVALID, 0, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_X_AFTER, 0, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_X_BEFORE, 0, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_X_CTI_CHAIN, 0, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_X_CHAIN, 0, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_X_BEGIN, 0, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ADD, model_fr400_add, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SUB, model_fr400_sub, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_AND, model_fr400_and, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_OR, model_fr400_or, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_XOR, model_fr400_xor, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_NOT, model_fr400_not, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SDIV, model_fr400_sdiv, { { (int) UNIT_FR400_U_IDIV, 1, 1 } } }, + { FRVBF_INSN_NSDIV, model_fr400_nsdiv, { { (int) UNIT_FR400_U_IDIV, 1, 1 } } }, + { FRVBF_INSN_UDIV, model_fr400_udiv, { { (int) UNIT_FR400_U_IDIV, 1, 1 } } }, + { FRVBF_INSN_NUDIV, model_fr400_nudiv, { { (int) UNIT_FR400_U_IDIV, 1, 1 } } }, + { FRVBF_INSN_SMUL, model_fr400_smul, { { (int) UNIT_FR400_U_IMUL, 1, 1 } } }, + { FRVBF_INSN_UMUL, model_fr400_umul, { { (int) UNIT_FR400_U_IMUL, 1, 1 } } }, + { FRVBF_INSN_SMU, model_fr400_smu, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SMASS, model_fr400_smass, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SMSSS, model_fr400_smsss, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SLL, model_fr400_sll, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SRL, model_fr400_srl, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SRA, model_fr400_sra, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SLASS, model_fr400_slass, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SCUTSS, model_fr400_scutss, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SCAN, model_fr400_scan, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_CADD, model_fr400_cadd, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_CSUB, model_fr400_csub, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_CAND, model_fr400_cand, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_COR, model_fr400_cor, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_CXOR, model_fr400_cxor, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_CNOT, model_fr400_cnot, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_CSMUL, model_fr400_csmul, { { (int) UNIT_FR400_U_IMUL, 1, 1 } } }, + { FRVBF_INSN_CSDIV, model_fr400_csdiv, { { (int) UNIT_FR400_U_IDIV, 1, 1 } } }, + { FRVBF_INSN_CUDIV, model_fr400_cudiv, { { (int) UNIT_FR400_U_IDIV, 1, 1 } } }, + { FRVBF_INSN_CSLL, model_fr400_csll, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_CSRL, model_fr400_csrl, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_CSRA, model_fr400_csra, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_CSCAN, model_fr400_cscan, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_ADDCC, model_fr400_addcc, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SUBCC, model_fr400_subcc, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_ANDCC, model_fr400_andcc, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_ORCC, model_fr400_orcc, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_XORCC, model_fr400_xorcc, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SLLCC, model_fr400_sllcc, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SRLCC, model_fr400_srlcc, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SRACC, model_fr400_sracc, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SMULCC, model_fr400_smulcc, { { (int) UNIT_FR400_U_IMUL, 1, 1 } } }, + { FRVBF_INSN_UMULCC, model_fr400_umulcc, { { (int) UNIT_FR400_U_IMUL, 1, 1 } } }, + { FRVBF_INSN_CADDCC, model_fr400_caddcc, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_CSUBCC, model_fr400_csubcc, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_CSMULCC, model_fr400_csmulcc, { { (int) UNIT_FR400_U_IMUL, 1, 1 } } }, + { FRVBF_INSN_CANDCC, model_fr400_candcc, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_CORCC, model_fr400_corcc, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_CXORCC, model_fr400_cxorcc, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_CSLLCC, model_fr400_csllcc, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_CSRLCC, model_fr400_csrlcc, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_CSRACC, model_fr400_csracc, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_ADDX, model_fr400_addx, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SUBX, model_fr400_subx, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_ADDXCC, model_fr400_addxcc, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SUBXCC, model_fr400_subxcc, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_ADDSS, model_fr400_addss, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SUBSS, model_fr400_subss, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_ADDI, model_fr400_addi, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SUBI, model_fr400_subi, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_ANDI, model_fr400_andi, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_ORI, model_fr400_ori, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_XORI, model_fr400_xori, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SDIVI, model_fr400_sdivi, { { (int) UNIT_FR400_U_IDIV, 1, 1 } } }, + { FRVBF_INSN_NSDIVI, model_fr400_nsdivi, { { (int) UNIT_FR400_U_IDIV, 1, 1 } } }, + { FRVBF_INSN_UDIVI, model_fr400_udivi, { { (int) UNIT_FR400_U_IDIV, 1, 1 } } }, + { FRVBF_INSN_NUDIVI, model_fr400_nudivi, { { (int) UNIT_FR400_U_IDIV, 1, 1 } } }, + { FRVBF_INSN_SMULI, model_fr400_smuli, { { (int) UNIT_FR400_U_IMUL, 1, 1 } } }, + { FRVBF_INSN_UMULI, model_fr400_umuli, { { (int) UNIT_FR400_U_IMUL, 1, 1 } } }, + { FRVBF_INSN_SLLI, model_fr400_slli, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SRLI, model_fr400_srli, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SRAI, model_fr400_srai, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SCANI, model_fr400_scani, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_ADDICC, model_fr400_addicc, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SUBICC, model_fr400_subicc, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_ANDICC, model_fr400_andicc, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_ORICC, model_fr400_oricc, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_XORICC, model_fr400_xoricc, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SMULICC, model_fr400_smulicc, { { (int) UNIT_FR400_U_IMUL, 1, 1 } } }, + { FRVBF_INSN_UMULICC, model_fr400_umulicc, { { (int) UNIT_FR400_U_IMUL, 1, 1 } } }, + { FRVBF_INSN_SLLICC, model_fr400_sllicc, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SRLICC, model_fr400_srlicc, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SRAICC, model_fr400_sraicc, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_ADDXI, model_fr400_addxi, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SUBXI, model_fr400_subxi, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_ADDXICC, model_fr400_addxicc, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SUBXICC, model_fr400_subxicc, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_CMPB, model_fr400_cmpb, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_CMPBA, model_fr400_cmpba, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SETLO, model_fr400_setlo, { { (int) UNIT_FR400_U_SET_HILO, 1, 1 } } }, + { FRVBF_INSN_SETHI, model_fr400_sethi, { { (int) UNIT_FR400_U_SET_HILO, 1, 1 } } }, + { FRVBF_INSN_SETLOS, model_fr400_setlos, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_LDSB, model_fr400_ldsb, { { (int) UNIT_FR400_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDUB, model_fr400_ldub, { { (int) UNIT_FR400_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDSH, model_fr400_ldsh, { { (int) UNIT_FR400_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDUH, model_fr400_lduh, { { (int) UNIT_FR400_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LD, model_fr400_ld, { { (int) UNIT_FR400_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDBF, model_fr400_ldbf, { { (int) UNIT_FR400_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDHF, model_fr400_ldhf, { { (int) UNIT_FR400_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDF, model_fr400_ldf, { { (int) UNIT_FR400_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDC, model_fr400_ldc, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDSB, model_fr400_nldsb, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDUB, model_fr400_nldub, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDSH, model_fr400_nldsh, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDUH, model_fr400_nlduh, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLD, model_fr400_nld, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDBF, model_fr400_nldbf, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDHF, model_fr400_nldhf, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDF, model_fr400_nldf, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDD, model_fr400_ldd, { { (int) UNIT_FR400_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDDF, model_fr400_lddf, { { (int) UNIT_FR400_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDDC, model_fr400_lddc, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDD, model_fr400_nldd, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDDF, model_fr400_nlddf, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDQ, model_fr400_ldq, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDQF, model_fr400_ldqf, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDQC, model_fr400_ldqc, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDQ, model_fr400_nldq, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDQF, model_fr400_nldqf, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDSBU, model_fr400_ldsbu, { { (int) UNIT_FR400_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDUBU, model_fr400_ldubu, { { (int) UNIT_FR400_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDSHU, model_fr400_ldshu, { { (int) UNIT_FR400_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDUHU, model_fr400_lduhu, { { (int) UNIT_FR400_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDU, model_fr400_ldu, { { (int) UNIT_FR400_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_NLDSBU, model_fr400_nldsbu, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDUBU, model_fr400_nldubu, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDSHU, model_fr400_nldshu, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDUHU, model_fr400_nlduhu, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDU, model_fr400_nldu, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDBFU, model_fr400_ldbfu, { { (int) UNIT_FR400_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDHFU, model_fr400_ldhfu, { { (int) UNIT_FR400_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDFU, model_fr400_ldfu, { { (int) UNIT_FR400_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDCU, model_fr400_ldcu, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDBFU, model_fr400_nldbfu, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDHFU, model_fr400_nldhfu, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDFU, model_fr400_nldfu, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDDU, model_fr400_lddu, { { (int) UNIT_FR400_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_NLDDU, model_fr400_nlddu, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDDFU, model_fr400_lddfu, { { (int) UNIT_FR400_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDDCU, model_fr400_lddcu, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDDFU, model_fr400_nlddfu, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDQU, model_fr400_ldqu, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDQU, model_fr400_nldqu, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDQFU, model_fr400_ldqfu, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDQCU, model_fr400_ldqcu, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDQFU, model_fr400_nldqfu, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDSBI, model_fr400_ldsbi, { { (int) UNIT_FR400_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDSHI, model_fr400_ldshi, { { (int) UNIT_FR400_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDI, model_fr400_ldi, { { (int) UNIT_FR400_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDUBI, model_fr400_ldubi, { { (int) UNIT_FR400_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDUHI, model_fr400_lduhi, { { (int) UNIT_FR400_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDBFI, model_fr400_ldbfi, { { (int) UNIT_FR400_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDHFI, model_fr400_ldhfi, { { (int) UNIT_FR400_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDFI, model_fr400_ldfi, { { (int) UNIT_FR400_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_NLDSBI, model_fr400_nldsbi, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDUBI, model_fr400_nldubi, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDSHI, model_fr400_nldshi, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDUHI, model_fr400_nlduhi, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDI, model_fr400_nldi, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDBFI, model_fr400_nldbfi, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDHFI, model_fr400_nldhfi, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDFI, model_fr400_nldfi, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDDI, model_fr400_lddi, { { (int) UNIT_FR400_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDDFI, model_fr400_lddfi, { { (int) UNIT_FR400_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_NLDDI, model_fr400_nlddi, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDDFI, model_fr400_nlddfi, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDQI, model_fr400_ldqi, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDQFI, model_fr400_ldqfi, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDQFI, model_fr400_nldqfi, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STB, model_fr400_stb, { { (int) UNIT_FR400_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_STH, model_fr400_sth, { { (int) UNIT_FR400_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_ST, model_fr400_st, { { (int) UNIT_FR400_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_STBF, model_fr400_stbf, { { (int) UNIT_FR400_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_STHF, model_fr400_sthf, { { (int) UNIT_FR400_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_STF, model_fr400_stf, { { (int) UNIT_FR400_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_STC, model_fr400_stc, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_RSTB, model_fr400_rstb, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_RSTH, model_fr400_rsth, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_RST, model_fr400_rst, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_RSTBF, model_fr400_rstbf, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_RSTHF, model_fr400_rsthf, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_RSTF, model_fr400_rstf, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STD, model_fr400_std, { { (int) UNIT_FR400_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_STDF, model_fr400_stdf, { { (int) UNIT_FR400_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_STDC, model_fr400_stdc, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_RSTD, model_fr400_rstd, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_RSTDF, model_fr400_rstdf, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STQ, model_fr400_stq, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STQF, model_fr400_stqf, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STQC, model_fr400_stqc, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_RSTQ, model_fr400_rstq, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_RSTQF, model_fr400_rstqf, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STBU, model_fr400_stbu, { { (int) UNIT_FR400_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_STHU, model_fr400_sthu, { { (int) UNIT_FR400_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_STU, model_fr400_stu, { { (int) UNIT_FR400_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_STBFU, model_fr400_stbfu, { { (int) UNIT_FR400_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_STHFU, model_fr400_sthfu, { { (int) UNIT_FR400_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_STFU, model_fr400_stfu, { { (int) UNIT_FR400_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_STCU, model_fr400_stcu, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STDU, model_fr400_stdu, { { (int) UNIT_FR400_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_STDFU, model_fr400_stdfu, { { (int) UNIT_FR400_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_STDCU, model_fr400_stdcu, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STQU, model_fr400_stqu, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STQFU, model_fr400_stqfu, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STQCU, model_fr400_stqcu, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLDSB, model_fr400_cldsb, { { (int) UNIT_FR400_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDUB, model_fr400_cldub, { { (int) UNIT_FR400_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDSH, model_fr400_cldsh, { { (int) UNIT_FR400_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDUH, model_fr400_clduh, { { (int) UNIT_FR400_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLD, model_fr400_cld, { { (int) UNIT_FR400_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDBF, model_fr400_cldbf, { { (int) UNIT_FR400_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDHF, model_fr400_cldhf, { { (int) UNIT_FR400_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDF, model_fr400_cldf, { { (int) UNIT_FR400_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDD, model_fr400_cldd, { { (int) UNIT_FR400_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDDF, model_fr400_clddf, { { (int) UNIT_FR400_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDQ, model_fr400_cldq, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLDSBU, model_fr400_cldsbu, { { (int) UNIT_FR400_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDUBU, model_fr400_cldubu, { { (int) UNIT_FR400_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDSHU, model_fr400_cldshu, { { (int) UNIT_FR400_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDUHU, model_fr400_clduhu, { { (int) UNIT_FR400_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDU, model_fr400_cldu, { { (int) UNIT_FR400_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDBFU, model_fr400_cldbfu, { { (int) UNIT_FR400_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDHFU, model_fr400_cldhfu, { { (int) UNIT_FR400_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDFU, model_fr400_cldfu, { { (int) UNIT_FR400_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDDU, model_fr400_clddu, { { (int) UNIT_FR400_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDDFU, model_fr400_clddfu, { { (int) UNIT_FR400_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDQU, model_fr400_cldqu, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSTB, model_fr400_cstb, { { (int) UNIT_FR400_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_CSTH, model_fr400_csth, { { (int) UNIT_FR400_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_CST, model_fr400_cst, { { (int) UNIT_FR400_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_CSTBF, model_fr400_cstbf, { { (int) UNIT_FR400_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_CSTHF, model_fr400_csthf, { { (int) UNIT_FR400_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_CSTF, model_fr400_cstf, { { (int) UNIT_FR400_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_CSTD, model_fr400_cstd, { { (int) UNIT_FR400_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_CSTDF, model_fr400_cstdf, { { (int) UNIT_FR400_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_CSTQ, model_fr400_cstq, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSTBU, model_fr400_cstbu, { { (int) UNIT_FR400_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_CSTHU, model_fr400_csthu, { { (int) UNIT_FR400_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_CSTU, model_fr400_cstu, { { (int) UNIT_FR400_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_CSTBFU, model_fr400_cstbfu, { { (int) UNIT_FR400_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_CSTHFU, model_fr400_csthfu, { { (int) UNIT_FR400_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_CSTFU, model_fr400_cstfu, { { (int) UNIT_FR400_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_CSTDU, model_fr400_cstdu, { { (int) UNIT_FR400_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_CSTDFU, model_fr400_cstdfu, { { (int) UNIT_FR400_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_STBI, model_fr400_stbi, { { (int) UNIT_FR400_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_STHI, model_fr400_sthi, { { (int) UNIT_FR400_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_STI, model_fr400_sti, { { (int) UNIT_FR400_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_STBFI, model_fr400_stbfi, { { (int) UNIT_FR400_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_STHFI, model_fr400_sthfi, { { (int) UNIT_FR400_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_STFI, model_fr400_stfi, { { (int) UNIT_FR400_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_STDI, model_fr400_stdi, { { (int) UNIT_FR400_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_STDFI, model_fr400_stdfi, { { (int) UNIT_FR400_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_STQI, model_fr400_stqi, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STQFI, model_fr400_stqfi, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SWAP, model_fr400_swap, { { (int) UNIT_FR400_U_SWAP, 1, 1 } } }, + { FRVBF_INSN_SWAPI, model_fr400_swapi, { { (int) UNIT_FR400_U_SWAP, 1, 1 } } }, + { FRVBF_INSN_CSWAP, model_fr400_cswap, { { (int) UNIT_FR400_U_SWAP, 1, 1 } } }, + { FRVBF_INSN_MOVGF, model_fr400_movgf, { { (int) UNIT_FR400_U_GR2FR, 1, 1 } } }, + { FRVBF_INSN_MOVFG, model_fr400_movfg, { { (int) UNIT_FR400_U_FR2GR, 1, 1 } } }, + { FRVBF_INSN_MOVGFD, model_fr400_movgfd, { { (int) UNIT_FR400_U_GR2FR, 1, 1 } } }, + { FRVBF_INSN_MOVFGD, model_fr400_movfgd, { { (int) UNIT_FR400_U_FR2GR, 1, 1 } } }, + { FRVBF_INSN_MOVGFQ, model_fr400_movgfq, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MOVFGQ, model_fr400_movfgq, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMOVGF, model_fr400_cmovgf, { { (int) UNIT_FR400_U_GR2FR, 1, 1 } } }, + { FRVBF_INSN_CMOVFG, model_fr400_cmovfg, { { (int) UNIT_FR400_U_FR2GR, 1, 1 } } }, + { FRVBF_INSN_CMOVGFD, model_fr400_cmovgfd, { { (int) UNIT_FR400_U_GR2FR, 1, 1 } } }, + { FRVBF_INSN_CMOVFGD, model_fr400_cmovfgd, { { (int) UNIT_FR400_U_FR2GR, 1, 1 } } }, + { FRVBF_INSN_MOVGS, model_fr400_movgs, { { (int) UNIT_FR400_U_GR2SPR, 1, 1 } } }, + { FRVBF_INSN_MOVSG, model_fr400_movsg, { { (int) UNIT_FR400_U_SPR2GR, 1, 1 } } }, + { FRVBF_INSN_BRA, model_fr400_bra, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BNO, model_fr400_bno, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BEQ, model_fr400_beq, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BNE, model_fr400_bne, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BLE, model_fr400_ble, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BGT, model_fr400_bgt, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BLT, model_fr400_blt, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BGE, model_fr400_bge, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BLS, model_fr400_bls, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BHI, model_fr400_bhi, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BC, model_fr400_bc, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BNC, model_fr400_bnc, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BN, model_fr400_bn, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BP, model_fr400_bp, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BV, model_fr400_bv, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BNV, model_fr400_bnv, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBRA, model_fr400_fbra, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBNO, model_fr400_fbno, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBNE, model_fr400_fbne, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBEQ, model_fr400_fbeq, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBLG, model_fr400_fblg, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBUE, model_fr400_fbue, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBUL, model_fr400_fbul, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBGE, model_fr400_fbge, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBLT, model_fr400_fblt, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBUGE, model_fr400_fbuge, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBUG, model_fr400_fbug, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBLE, model_fr400_fble, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBGT, model_fr400_fbgt, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBULE, model_fr400_fbule, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBU, model_fr400_fbu, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBO, model_fr400_fbo, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BCTRLR, model_fr400_bctrlr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BRALR, model_fr400_bralr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BNOLR, model_fr400_bnolr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BEQLR, model_fr400_beqlr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BNELR, model_fr400_bnelr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BLELR, model_fr400_blelr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BGTLR, model_fr400_bgtlr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BLTLR, model_fr400_bltlr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BGELR, model_fr400_bgelr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BLSLR, model_fr400_blslr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BHILR, model_fr400_bhilr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BCLR, model_fr400_bclr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BNCLR, model_fr400_bnclr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BNLR, model_fr400_bnlr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BPLR, model_fr400_bplr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BVLR, model_fr400_bvlr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BNVLR, model_fr400_bnvlr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBRALR, model_fr400_fbralr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBNOLR, model_fr400_fbnolr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBEQLR, model_fr400_fbeqlr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBNELR, model_fr400_fbnelr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBLGLR, model_fr400_fblglr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBUELR, model_fr400_fbuelr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBULLR, model_fr400_fbullr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBGELR, model_fr400_fbgelr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBLTLR, model_fr400_fbltlr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBUGELR, model_fr400_fbugelr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBUGLR, model_fr400_fbuglr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBLELR, model_fr400_fblelr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBGTLR, model_fr400_fbgtlr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBULELR, model_fr400_fbulelr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBULR, model_fr400_fbulr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBOLR, model_fr400_fbolr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BCRALR, model_fr400_bcralr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BCNOLR, model_fr400_bcnolr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BCEQLR, model_fr400_bceqlr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BCNELR, model_fr400_bcnelr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BCLELR, model_fr400_bclelr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BCGTLR, model_fr400_bcgtlr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BCLTLR, model_fr400_bcltlr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BCGELR, model_fr400_bcgelr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BCLSLR, model_fr400_bclslr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BCHILR, model_fr400_bchilr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BCCLR, model_fr400_bcclr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BCNCLR, model_fr400_bcnclr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BCNLR, model_fr400_bcnlr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BCPLR, model_fr400_bcplr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BCVLR, model_fr400_bcvlr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BCNVLR, model_fr400_bcnvlr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FCBRALR, model_fr400_fcbralr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FCBNOLR, model_fr400_fcbnolr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FCBEQLR, model_fr400_fcbeqlr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FCBNELR, model_fr400_fcbnelr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FCBLGLR, model_fr400_fcblglr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FCBUELR, model_fr400_fcbuelr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FCBULLR, model_fr400_fcbullr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FCBGELR, model_fr400_fcbgelr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FCBLTLR, model_fr400_fcbltlr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FCBUGELR, model_fr400_fcbugelr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FCBUGLR, model_fr400_fcbuglr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FCBLELR, model_fr400_fcblelr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FCBGTLR, model_fr400_fcbgtlr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FCBULELR, model_fr400_fcbulelr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FCBULR, model_fr400_fcbulr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FCBOLR, model_fr400_fcbolr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_JMPL, model_fr400_jmpl, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_CALLL, model_fr400_calll, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_JMPIL, model_fr400_jmpil, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_CALLIL, model_fr400_callil, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_CALL, model_fr400_call, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_RETT, model_fr400_rett, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_REI, model_fr400_rei, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TRA, model_fr400_tra, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TNO, model_fr400_tno, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TEQ, model_fr400_teq, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TNE, model_fr400_tne, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TLE, model_fr400_tle, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TGT, model_fr400_tgt, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TLT, model_fr400_tlt, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TGE, model_fr400_tge, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TLS, model_fr400_tls, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_THI, model_fr400_thi, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TC, model_fr400_tc, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TNC, model_fr400_tnc, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TN, model_fr400_tn, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TP, model_fr400_tp, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TV, model_fr400_tv, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TNV, model_fr400_tnv, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTRA, model_fr400_ftra, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTNO, model_fr400_ftno, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTNE, model_fr400_ftne, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTEQ, model_fr400_fteq, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTLG, model_fr400_ftlg, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTUE, model_fr400_ftue, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTUL, model_fr400_ftul, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTGE, model_fr400_ftge, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTLT, model_fr400_ftlt, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTUGE, model_fr400_ftuge, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTUG, model_fr400_ftug, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTLE, model_fr400_ftle, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTGT, model_fr400_ftgt, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTULE, model_fr400_ftule, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTU, model_fr400_ftu, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTO, model_fr400_fto, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TIRA, model_fr400_tira, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TINO, model_fr400_tino, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TIEQ, model_fr400_tieq, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TINE, model_fr400_tine, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TILE, model_fr400_tile, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TIGT, model_fr400_tigt, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TILT, model_fr400_tilt, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TIGE, model_fr400_tige, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TILS, model_fr400_tils, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TIHI, model_fr400_tihi, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TIC, model_fr400_tic, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TINC, model_fr400_tinc, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TIN, model_fr400_tin, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TIP, model_fr400_tip, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TIV, model_fr400_tiv, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TINV, model_fr400_tinv, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTIRA, model_fr400_ftira, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTINO, model_fr400_ftino, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTINE, model_fr400_ftine, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTIEQ, model_fr400_ftieq, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTILG, model_fr400_ftilg, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTIUE, model_fr400_ftiue, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTIUL, model_fr400_ftiul, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTIGE, model_fr400_ftige, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTILT, model_fr400_ftilt, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTIUGE, model_fr400_ftiuge, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTIUG, model_fr400_ftiug, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTILE, model_fr400_ftile, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTIGT, model_fr400_ftigt, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTIULE, model_fr400_ftiule, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTIU, model_fr400_ftiu, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTIO, model_fr400_ftio, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_BREAK, model_fr400_break, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MTRAP, model_fr400_mtrap, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ANDCR, model_fr400_andcr, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ORCR, model_fr400_orcr, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_XORCR, model_fr400_xorcr, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NANDCR, model_fr400_nandcr, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NORCR, model_fr400_norcr, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ANDNCR, model_fr400_andncr, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ORNCR, model_fr400_orncr, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NANDNCR, model_fr400_nandncr, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NORNCR, model_fr400_norncr, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NOTCR, model_fr400_notcr, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CKRA, model_fr400_ckra, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CKNO, model_fr400_ckno, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CKEQ, model_fr400_ckeq, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CKNE, model_fr400_ckne, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CKLE, model_fr400_ckle, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CKGT, model_fr400_ckgt, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CKLT, model_fr400_cklt, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CKGE, model_fr400_ckge, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CKLS, model_fr400_ckls, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CKHI, model_fr400_ckhi, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CKC, model_fr400_ckc, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CKNC, model_fr400_cknc, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CKN, model_fr400_ckn, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CKP, model_fr400_ckp, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CKV, model_fr400_ckv, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CKNV, model_fr400_cknv, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_FCKRA, model_fr400_fckra, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_FCKNO, model_fr400_fckno, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_FCKNE, model_fr400_fckne, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_FCKEQ, model_fr400_fckeq, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_FCKLG, model_fr400_fcklg, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_FCKUE, model_fr400_fckue, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_FCKUL, model_fr400_fckul, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_FCKGE, model_fr400_fckge, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_FCKLT, model_fr400_fcklt, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_FCKUGE, model_fr400_fckuge, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_FCKUG, model_fr400_fckug, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_FCKLE, model_fr400_fckle, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_FCKGT, model_fr400_fckgt, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_FCKULE, model_fr400_fckule, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_FCKU, model_fr400_fcku, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_FCKO, model_fr400_fcko, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CCKRA, model_fr400_cckra, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CCKNO, model_fr400_cckno, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CCKEQ, model_fr400_cckeq, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CCKNE, model_fr400_cckne, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CCKLE, model_fr400_cckle, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CCKGT, model_fr400_cckgt, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CCKLT, model_fr400_ccklt, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CCKGE, model_fr400_cckge, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CCKLS, model_fr400_cckls, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CCKHI, model_fr400_cckhi, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CCKC, model_fr400_cckc, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CCKNC, model_fr400_ccknc, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CCKN, model_fr400_cckn, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CCKP, model_fr400_cckp, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CCKV, model_fr400_cckv, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CCKNV, model_fr400_ccknv, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CFCKRA, model_fr400_cfckra, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CFCKNO, model_fr400_cfckno, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CFCKNE, model_fr400_cfckne, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CFCKEQ, model_fr400_cfckeq, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CFCKLG, model_fr400_cfcklg, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CFCKUE, model_fr400_cfckue, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CFCKUL, model_fr400_cfckul, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CFCKGE, model_fr400_cfckge, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CFCKLT, model_fr400_cfcklt, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CFCKUGE, model_fr400_cfckuge, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CFCKUG, model_fr400_cfckug, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CFCKLE, model_fr400_cfckle, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CFCKGT, model_fr400_cfckgt, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CFCKULE, model_fr400_cfckule, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CFCKU, model_fr400_cfcku, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CFCKO, model_fr400_cfcko, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CJMPL, model_fr400_cjmpl, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_CCALLL, model_fr400_ccalll, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_ICI, model_fr400_ici, { { (int) UNIT_FR400_U_ICI, 1, 1 } } }, + { FRVBF_INSN_DCI, model_fr400_dci, { { (int) UNIT_FR400_U_DCI, 1, 1 } } }, + { FRVBF_INSN_ICEI, model_fr400_icei, { { (int) UNIT_FR400_U_ICI, 1, 1 } } }, + { FRVBF_INSN_DCEI, model_fr400_dcei, { { (int) UNIT_FR400_U_DCI, 1, 1 } } }, + { FRVBF_INSN_DCF, model_fr400_dcf, { { (int) UNIT_FR400_U_DCF, 1, 1 } } }, + { FRVBF_INSN_DCEF, model_fr400_dcef, { { (int) UNIT_FR400_U_DCF, 1, 1 } } }, + { FRVBF_INSN_WITLB, model_fr400_witlb, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_WDTLB, model_fr400_wdtlb, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ITLBI, model_fr400_itlbi, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_DTLBI, model_fr400_dtlbi, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ICPL, model_fr400_icpl, { { (int) UNIT_FR400_U_ICPL, 1, 1 } } }, + { FRVBF_INSN_DCPL, model_fr400_dcpl, { { (int) UNIT_FR400_U_DCPL, 1, 1 } } }, + { FRVBF_INSN_ICUL, model_fr400_icul, { { (int) UNIT_FR400_U_ICUL, 1, 1 } } }, + { FRVBF_INSN_DCUL, model_fr400_dcul, { { (int) UNIT_FR400_U_DCUL, 1, 1 } } }, + { FRVBF_INSN_BAR, model_fr400_bar, { { (int) UNIT_FR400_U_BARRIER, 1, 1 } } }, + { FRVBF_INSN_MEMBAR, model_fr400_membar, { { (int) UNIT_FR400_U_MEMBAR, 1, 1 } } }, + { FRVBF_INSN_COP1, model_fr400_cop1, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_COP2, model_fr400_cop2, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLRGR, model_fr400_clrgr, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLRFR, model_fr400_clrfr, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLRGA, model_fr400_clrga, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLRFA, model_fr400_clrfa, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_COMMITGR, model_fr400_commitgr, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_COMMITFR, model_fr400_commitfr, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_COMMITGA, model_fr400_commitga, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_COMMITFA, model_fr400_commitfa, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FITOS, model_fr400_fitos, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FSTOI, model_fr400_fstoi, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FITOD, model_fr400_fitod, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDTOI, model_fr400_fdtoi, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDITOS, model_fr400_fditos, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDSTOI, model_fr400_fdstoi, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFDITOS, model_fr400_nfditos, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFDSTOI, model_fr400_nfdstoi, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFITOS, model_fr400_cfitos, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFSTOI, model_fr400_cfstoi, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFITOS, model_fr400_nfitos, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFSTOI, model_fr400_nfstoi, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FMOVS, model_fr400_fmovs, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FMOVD, model_fr400_fmovd, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDMOVS, model_fr400_fdmovs, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFMOVS, model_fr400_cfmovs, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FNEGS, model_fr400_fnegs, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FNEGD, model_fr400_fnegd, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDNEGS, model_fr400_fdnegs, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFNEGS, model_fr400_cfnegs, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FABSS, model_fr400_fabss, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FABSD, model_fr400_fabsd, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDABSS, model_fr400_fdabss, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFABSS, model_fr400_cfabss, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FSQRTS, model_fr400_fsqrts, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDSQRTS, model_fr400_fdsqrts, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFDSQRTS, model_fr400_nfdsqrts, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FSQRTD, model_fr400_fsqrtd, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFSQRTS, model_fr400_cfsqrts, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFSQRTS, model_fr400_nfsqrts, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FADDS, model_fr400_fadds, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FSUBS, model_fr400_fsubs, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FMULS, model_fr400_fmuls, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDIVS, model_fr400_fdivs, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FADDD, model_fr400_faddd, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FSUBD, model_fr400_fsubd, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FMULD, model_fr400_fmuld, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDIVD, model_fr400_fdivd, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFADDS, model_fr400_cfadds, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFSUBS, model_fr400_cfsubs, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFMULS, model_fr400_cfmuls, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFDIVS, model_fr400_cfdivs, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFADDS, model_fr400_nfadds, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFSUBS, model_fr400_nfsubs, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFMULS, model_fr400_nfmuls, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFDIVS, model_fr400_nfdivs, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCMPS, model_fr400_fcmps, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCMPD, model_fr400_fcmpd, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFCMPS, model_fr400_cfcmps, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDCMPS, model_fr400_fdcmps, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FMADDS, model_fr400_fmadds, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FMSUBS, model_fr400_fmsubs, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FMADDD, model_fr400_fmaddd, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FMSUBD, model_fr400_fmsubd, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDMADDS, model_fr400_fdmadds, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFDMADDS, model_fr400_nfdmadds, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFMADDS, model_fr400_cfmadds, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFMSUBS, model_fr400_cfmsubs, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFMADDS, model_fr400_nfmadds, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFMSUBS, model_fr400_nfmsubs, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FMAS, model_fr400_fmas, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FMSS, model_fr400_fmss, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDMAS, model_fr400_fdmas, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDMSS, model_fr400_fdmss, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFDMAS, model_fr400_nfdmas, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFDMSS, model_fr400_nfdmss, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFMAS, model_fr400_cfmas, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFMSS, model_fr400_cfmss, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FMAD, model_fr400_fmad, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FMSD, model_fr400_fmsd, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFMAS, model_fr400_nfmas, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFMSS, model_fr400_nfmss, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDADDS, model_fr400_fdadds, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDSUBS, model_fr400_fdsubs, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDMULS, model_fr400_fdmuls, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDDIVS, model_fr400_fddivs, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDSADS, model_fr400_fdsads, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDMULCS, model_fr400_fdmulcs, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFDMULCS, model_fr400_nfdmulcs, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFDADDS, model_fr400_nfdadds, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFDSUBS, model_fr400_nfdsubs, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFDMULS, model_fr400_nfdmuls, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFDDIVS, model_fr400_nfddivs, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFDSADS, model_fr400_nfdsads, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFDCMPS, model_fr400_nfdcmps, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MHSETLOS, model_fr400_mhsetlos, { { (int) UNIT_FR400_U_MEDIA_HILO, 1, 1 } } }, + { FRVBF_INSN_MHSETHIS, model_fr400_mhsethis, { { (int) UNIT_FR400_U_MEDIA_HILO, 1, 1 } } }, + { FRVBF_INSN_MHDSETS, model_fr400_mhdsets, { { (int) UNIT_FR400_U_MEDIA_1, 1, 1 } } }, + { FRVBF_INSN_MHSETLOH, model_fr400_mhsetloh, { { (int) UNIT_FR400_U_MEDIA_HILO, 1, 1 } } }, + { FRVBF_INSN_MHSETHIH, model_fr400_mhsethih, { { (int) UNIT_FR400_U_MEDIA_HILO, 1, 1 } } }, + { FRVBF_INSN_MHDSETH, model_fr400_mhdseth, { { (int) UNIT_FR400_U_MEDIA_1, 1, 1 } } }, + { FRVBF_INSN_MAND, model_fr400_mand, { { (int) UNIT_FR400_U_MEDIA_1, 1, 1 } } }, + { FRVBF_INSN_MOR, model_fr400_mor, { { (int) UNIT_FR400_U_MEDIA_1, 1, 1 } } }, + { FRVBF_INSN_MXOR, model_fr400_mxor, { { (int) UNIT_FR400_U_MEDIA_1, 1, 1 } } }, + { FRVBF_INSN_CMAND, model_fr400_cmand, { { (int) UNIT_FR400_U_MEDIA_1, 1, 1 } } }, + { FRVBF_INSN_CMOR, model_fr400_cmor, { { (int) UNIT_FR400_U_MEDIA_1, 1, 1 } } }, + { FRVBF_INSN_CMXOR, model_fr400_cmxor, { { (int) UNIT_FR400_U_MEDIA_1, 1, 1 } } }, + { FRVBF_INSN_MNOT, model_fr400_mnot, { { (int) UNIT_FR400_U_MEDIA_1, 1, 1 } } }, + { FRVBF_INSN_CMNOT, model_fr400_cmnot, { { (int) UNIT_FR400_U_MEDIA_1, 1, 1 } } }, + { FRVBF_INSN_MROTLI, model_fr400_mrotli, { { (int) UNIT_FR400_U_MEDIA_3, 1, 1 } } }, + { FRVBF_INSN_MROTRI, model_fr400_mrotri, { { (int) UNIT_FR400_U_MEDIA_3, 1, 1 } } }, + { FRVBF_INSN_MWCUT, model_fr400_mwcut, { { (int) UNIT_FR400_U_MEDIA_3, 1, 1 } } }, + { FRVBF_INSN_MWCUTI, model_fr400_mwcuti, { { (int) UNIT_FR400_U_MEDIA_3, 1, 1 } } }, + { FRVBF_INSN_MCUT, model_fr400_mcut, { { (int) UNIT_FR400_U_MEDIA_4, 1, 1 } } }, + { FRVBF_INSN_MCUTI, model_fr400_mcuti, { { (int) UNIT_FR400_U_MEDIA_4, 1, 1 } } }, + { FRVBF_INSN_MCUTSS, model_fr400_mcutss, { { (int) UNIT_FR400_U_MEDIA_4, 1, 1 } } }, + { FRVBF_INSN_MCUTSSI, model_fr400_mcutssi, { { (int) UNIT_FR400_U_MEDIA_4, 1, 1 } } }, + { FRVBF_INSN_MDCUTSSI, model_fr400_mdcutssi, { { (int) UNIT_FR400_U_MEDIA_4_ACC_DUAL, 1, 1 } } }, + { FRVBF_INSN_MAVEH, model_fr400_maveh, { { (int) UNIT_FR400_U_MEDIA_1, 1, 1 } } }, + { FRVBF_INSN_MSLLHI, model_fr400_msllhi, { { (int) UNIT_FR400_U_MEDIA_3, 1, 1 } } }, + { FRVBF_INSN_MSRLHI, model_fr400_msrlhi, { { (int) UNIT_FR400_U_MEDIA_3, 1, 1 } } }, + { FRVBF_INSN_MSRAHI, model_fr400_msrahi, { { (int) UNIT_FR400_U_MEDIA_6, 1, 1 } } }, + { FRVBF_INSN_MDROTLI, model_fr400_mdrotli, { { (int) UNIT_FR400_U_MEDIA_3_QUAD, 1, 1 } } }, + { FRVBF_INSN_MCPLHI, model_fr400_mcplhi, { { (int) UNIT_FR400_U_MEDIA_3_DUAL, 1, 1 } } }, + { FRVBF_INSN_MCPLI, model_fr400_mcpli, { { (int) UNIT_FR400_U_MEDIA_3_DUAL, 1, 1 } } }, + { FRVBF_INSN_MSATHS, model_fr400_msaths, { { (int) UNIT_FR400_U_MEDIA_1, 1, 1 } } }, + { FRVBF_INSN_MQSATHS, model_fr400_mqsaths, { { (int) UNIT_FR400_U_MEDIA_1_QUAD, 1, 1 } } }, + { FRVBF_INSN_MSATHU, model_fr400_msathu, { { (int) UNIT_FR400_U_MEDIA_1, 1, 1 } } }, + { FRVBF_INSN_MCMPSH, model_fr400_mcmpsh, { { (int) UNIT_FR400_U_MEDIA_7, 1, 1 } } }, + { FRVBF_INSN_MCMPUH, model_fr400_mcmpuh, { { (int) UNIT_FR400_U_MEDIA_7, 1, 1 } } }, + { FRVBF_INSN_MABSHS, model_fr400_mabshs, { { (int) UNIT_FR400_U_MEDIA_1, 1, 1 } } }, + { FRVBF_INSN_MADDHSS, model_fr400_maddhss, { { (int) UNIT_FR400_U_MEDIA_1, 1, 1 } } }, + { FRVBF_INSN_MADDHUS, model_fr400_maddhus, { { (int) UNIT_FR400_U_MEDIA_1, 1, 1 } } }, + { FRVBF_INSN_MSUBHSS, model_fr400_msubhss, { { (int) UNIT_FR400_U_MEDIA_1, 1, 1 } } }, + { FRVBF_INSN_MSUBHUS, model_fr400_msubhus, { { (int) UNIT_FR400_U_MEDIA_1, 1, 1 } } }, + { FRVBF_INSN_CMADDHSS, model_fr400_cmaddhss, { { (int) UNIT_FR400_U_MEDIA_1, 1, 1 } } }, + { FRVBF_INSN_CMADDHUS, model_fr400_cmaddhus, { { (int) UNIT_FR400_U_MEDIA_1, 1, 1 } } }, + { FRVBF_INSN_CMSUBHSS, model_fr400_cmsubhss, { { (int) UNIT_FR400_U_MEDIA_1, 1, 1 } } }, + { FRVBF_INSN_CMSUBHUS, model_fr400_cmsubhus, { { (int) UNIT_FR400_U_MEDIA_1, 1, 1 } } }, + { FRVBF_INSN_MQADDHSS, model_fr400_mqaddhss, { { (int) UNIT_FR400_U_MEDIA_1_QUAD, 1, 1 } } }, + { FRVBF_INSN_MQADDHUS, model_fr400_mqaddhus, { { (int) UNIT_FR400_U_MEDIA_1_QUAD, 1, 1 } } }, + { FRVBF_INSN_MQSUBHSS, model_fr400_mqsubhss, { { (int) UNIT_FR400_U_MEDIA_1_QUAD, 1, 1 } } }, + { FRVBF_INSN_MQSUBHUS, model_fr400_mqsubhus, { { (int) UNIT_FR400_U_MEDIA_1_QUAD, 1, 1 } } }, + { FRVBF_INSN_CMQADDHSS, model_fr400_cmqaddhss, { { (int) UNIT_FR400_U_MEDIA_1_QUAD, 1, 1 } } }, + { FRVBF_INSN_CMQADDHUS, model_fr400_cmqaddhus, { { (int) UNIT_FR400_U_MEDIA_1_QUAD, 1, 1 } } }, + { FRVBF_INSN_CMQSUBHSS, model_fr400_cmqsubhss, { { (int) UNIT_FR400_U_MEDIA_1_QUAD, 1, 1 } } }, + { FRVBF_INSN_CMQSUBHUS, model_fr400_cmqsubhus, { { (int) UNIT_FR400_U_MEDIA_1_QUAD, 1, 1 } } }, + { FRVBF_INSN_MADDACCS, model_fr400_maddaccs, { { (int) UNIT_FR400_U_MEDIA_2_ACC, 1, 1 } } }, + { FRVBF_INSN_MSUBACCS, model_fr400_msubaccs, { { (int) UNIT_FR400_U_MEDIA_2_ACC, 1, 1 } } }, + { FRVBF_INSN_MDADDACCS, model_fr400_mdaddaccs, { { (int) UNIT_FR400_U_MEDIA_2_ACC_DUAL, 1, 1 } } }, + { FRVBF_INSN_MDSUBACCS, model_fr400_mdsubaccs, { { (int) UNIT_FR400_U_MEDIA_2_ACC_DUAL, 1, 1 } } }, + { FRVBF_INSN_MASACCS, model_fr400_masaccs, { { (int) UNIT_FR400_U_MEDIA_2_ADD_SUB, 1, 1 } } }, + { FRVBF_INSN_MDASACCS, model_fr400_mdasaccs, { { (int) UNIT_FR400_U_MEDIA_2_ADD_SUB_DUAL, 1, 1 } } }, + { FRVBF_INSN_MMULHS, model_fr400_mmulhs, { { (int) UNIT_FR400_U_MEDIA_2, 1, 1 } } }, + { FRVBF_INSN_MMULHU, model_fr400_mmulhu, { { (int) UNIT_FR400_U_MEDIA_2, 1, 1 } } }, + { FRVBF_INSN_MMULXHS, model_fr400_mmulxhs, { { (int) UNIT_FR400_U_MEDIA_2, 1, 1 } } }, + { FRVBF_INSN_MMULXHU, model_fr400_mmulxhu, { { (int) UNIT_FR400_U_MEDIA_2, 1, 1 } } }, + { FRVBF_INSN_CMMULHS, model_fr400_cmmulhs, { { (int) UNIT_FR400_U_MEDIA_2, 1, 1 } } }, + { FRVBF_INSN_CMMULHU, model_fr400_cmmulhu, { { (int) UNIT_FR400_U_MEDIA_2, 1, 1 } } }, + { FRVBF_INSN_MQMULHS, model_fr400_mqmulhs, { { (int) UNIT_FR400_U_MEDIA_2_QUAD, 1, 1 } } }, + { FRVBF_INSN_MQMULHU, model_fr400_mqmulhu, { { (int) UNIT_FR400_U_MEDIA_2_QUAD, 1, 1 } } }, + { FRVBF_INSN_MQMULXHS, model_fr400_mqmulxhs, { { (int) UNIT_FR400_U_MEDIA_2_QUAD, 1, 1 } } }, + { FRVBF_INSN_MQMULXHU, model_fr400_mqmulxhu, { { (int) UNIT_FR400_U_MEDIA_2_QUAD, 1, 1 } } }, + { FRVBF_INSN_CMQMULHS, model_fr400_cmqmulhs, { { (int) UNIT_FR400_U_MEDIA_2_QUAD, 1, 1 } } }, + { FRVBF_INSN_CMQMULHU, model_fr400_cmqmulhu, { { (int) UNIT_FR400_U_MEDIA_2_QUAD, 1, 1 } } }, + { FRVBF_INSN_MMACHS, model_fr400_mmachs, { { (int) UNIT_FR400_U_MEDIA_2, 1, 1 } } }, + { FRVBF_INSN_MMACHU, model_fr400_mmachu, { { (int) UNIT_FR400_U_MEDIA_2, 1, 1 } } }, + { FRVBF_INSN_MMRDHS, model_fr400_mmrdhs, { { (int) UNIT_FR400_U_MEDIA_2, 1, 1 } } }, + { FRVBF_INSN_MMRDHU, model_fr400_mmrdhu, { { (int) UNIT_FR400_U_MEDIA_2, 1, 1 } } }, + { FRVBF_INSN_CMMACHS, model_fr400_cmmachs, { { (int) UNIT_FR400_U_MEDIA_2, 1, 1 } } }, + { FRVBF_INSN_CMMACHU, model_fr400_cmmachu, { { (int) UNIT_FR400_U_MEDIA_2, 1, 1 } } }, + { FRVBF_INSN_MQMACHS, model_fr400_mqmachs, { { (int) UNIT_FR400_U_MEDIA_2_QUAD, 1, 1 } } }, + { FRVBF_INSN_MQMACHU, model_fr400_mqmachu, { { (int) UNIT_FR400_U_MEDIA_2_QUAD, 1, 1 } } }, + { FRVBF_INSN_CMQMACHS, model_fr400_cmqmachs, { { (int) UNIT_FR400_U_MEDIA_2_QUAD, 1, 1 } } }, + { FRVBF_INSN_CMQMACHU, model_fr400_cmqmachu, { { (int) UNIT_FR400_U_MEDIA_2_QUAD, 1, 1 } } }, + { FRVBF_INSN_MQXMACHS, model_fr400_mqxmachs, { { (int) UNIT_FR400_U_MEDIA_2_QUAD, 1, 1 } } }, + { FRVBF_INSN_MQXMACXHS, model_fr400_mqxmacxhs, { { (int) UNIT_FR400_U_MEDIA_2_QUAD, 1, 1 } } }, + { FRVBF_INSN_MQMACXHS, model_fr400_mqmacxhs, { { (int) UNIT_FR400_U_MEDIA_2_QUAD, 1, 1 } } }, + { FRVBF_INSN_MCPXRS, model_fr400_mcpxrs, { { (int) UNIT_FR400_U_MEDIA_2, 1, 1 } } }, + { FRVBF_INSN_MCPXRU, model_fr400_mcpxru, { { (int) UNIT_FR400_U_MEDIA_2, 1, 1 } } }, + { FRVBF_INSN_MCPXIS, model_fr400_mcpxis, { { (int) UNIT_FR400_U_MEDIA_2, 1, 1 } } }, + { FRVBF_INSN_MCPXIU, model_fr400_mcpxiu, { { (int) UNIT_FR400_U_MEDIA_2, 1, 1 } } }, + { FRVBF_INSN_CMCPXRS, model_fr400_cmcpxrs, { { (int) UNIT_FR400_U_MEDIA_2, 1, 1 } } }, + { FRVBF_INSN_CMCPXRU, model_fr400_cmcpxru, { { (int) UNIT_FR400_U_MEDIA_2, 1, 1 } } }, + { FRVBF_INSN_CMCPXIS, model_fr400_cmcpxis, { { (int) UNIT_FR400_U_MEDIA_2, 1, 1 } } }, + { FRVBF_INSN_CMCPXIU, model_fr400_cmcpxiu, { { (int) UNIT_FR400_U_MEDIA_2, 1, 1 } } }, + { FRVBF_INSN_MQCPXRS, model_fr400_mqcpxrs, { { (int) UNIT_FR400_U_MEDIA_2_QUAD, 1, 1 } } }, + { FRVBF_INSN_MQCPXRU, model_fr400_mqcpxru, { { (int) UNIT_FR400_U_MEDIA_2_QUAD, 1, 1 } } }, + { FRVBF_INSN_MQCPXIS, model_fr400_mqcpxis, { { (int) UNIT_FR400_U_MEDIA_2_QUAD, 1, 1 } } }, + { FRVBF_INSN_MQCPXIU, model_fr400_mqcpxiu, { { (int) UNIT_FR400_U_MEDIA_2_QUAD, 1, 1 } } }, + { FRVBF_INSN_MEXPDHW, model_fr400_mexpdhw, { { (int) UNIT_FR400_U_MEDIA_3, 1, 1 } } }, + { FRVBF_INSN_CMEXPDHW, model_fr400_cmexpdhw, { { (int) UNIT_FR400_U_MEDIA_3, 1, 1 } } }, + { FRVBF_INSN_MEXPDHD, model_fr400_mexpdhd, { { (int) UNIT_FR400_U_MEDIA_DUAL_EXPAND, 1, 1 } } }, + { FRVBF_INSN_CMEXPDHD, model_fr400_cmexpdhd, { { (int) UNIT_FR400_U_MEDIA_DUAL_EXPAND, 1, 1 } } }, + { FRVBF_INSN_MPACKH, model_fr400_mpackh, { { (int) UNIT_FR400_U_MEDIA_3, 1, 1 } } }, + { FRVBF_INSN_MDPACKH, model_fr400_mdpackh, { { (int) UNIT_FR400_U_MEDIA_3_QUAD, 1, 1 } } }, + { FRVBF_INSN_MUNPACKH, model_fr400_munpackh, { { (int) UNIT_FR400_U_MEDIA_DUAL_EXPAND, 1, 1 } } }, + { FRVBF_INSN_MDUNPACKH, model_fr400_mdunpackh, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MBTOH, model_fr400_mbtoh, { { (int) UNIT_FR400_U_MEDIA_DUAL_EXPAND, 1, 1 } } }, + { FRVBF_INSN_CMBTOH, model_fr400_cmbtoh, { { (int) UNIT_FR400_U_MEDIA_DUAL_EXPAND, 1, 1 } } }, + { FRVBF_INSN_MHTOB, model_fr400_mhtob, { { (int) UNIT_FR400_U_MEDIA_DUAL_HTOB, 1, 1 } } }, + { FRVBF_INSN_CMHTOB, model_fr400_cmhtob, { { (int) UNIT_FR400_U_MEDIA_DUAL_HTOB, 1, 1 } } }, + { FRVBF_INSN_MBTOHE, model_fr400_mbtohe, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMBTOHE, model_fr400_cmbtohe, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MNOP, model_fr400_mnop, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MCLRACC_0, model_fr400_mclracc_0, { { (int) UNIT_FR400_U_MEDIA_4, 1, 1 } } }, + { FRVBF_INSN_MCLRACC_1, model_fr400_mclracc_1, { { (int) UNIT_FR400_U_MEDIA_4, 1, 1 } } }, + { FRVBF_INSN_MRDACC, model_fr400_mrdacc, { { (int) UNIT_FR400_U_MEDIA_4, 1, 1 } } }, + { FRVBF_INSN_MRDACCG, model_fr400_mrdaccg, { { (int) UNIT_FR400_U_MEDIA_4_ACCG, 1, 1 } } }, + { FRVBF_INSN_MWTACC, model_fr400_mwtacc, { { (int) UNIT_FR400_U_MEDIA_4, 1, 1 } } }, + { FRVBF_INSN_MWTACCG, model_fr400_mwtaccg, { { (int) UNIT_FR400_U_MEDIA_4_ACCG, 1, 1 } } }, + { FRVBF_INSN_MCOP1, model_fr400_mcop1, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MCOP2, model_fr400_mcop2, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FNOP, model_fr400_fnop, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, +}; + +/* Model timing data for `simple'. */ + +static const INSN_TIMING simple_timing[] = { + { FRVBF_INSN_X_INVALID, 0, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_X_AFTER, 0, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_X_BEFORE, 0, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_X_CTI_CHAIN, 0, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_X_CHAIN, 0, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_X_BEGIN, 0, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ADD, model_simple_add, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SUB, model_simple_sub, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_AND, model_simple_and, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_OR, model_simple_or, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_XOR, model_simple_xor, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NOT, model_simple_not, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SDIV, model_simple_sdiv, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NSDIV, model_simple_nsdiv, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_UDIV, model_simple_udiv, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NUDIV, model_simple_nudiv, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SMUL, model_simple_smul, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_UMUL, model_simple_umul, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SMU, model_simple_smu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SMASS, model_simple_smass, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SMSSS, model_simple_smsss, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SLL, model_simple_sll, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SRL, model_simple_srl, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SRA, model_simple_sra, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SLASS, model_simple_slass, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SCUTSS, model_simple_scutss, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SCAN, model_simple_scan, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CADD, model_simple_cadd, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSUB, model_simple_csub, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CAND, model_simple_cand, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_COR, model_simple_cor, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CXOR, model_simple_cxor, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CNOT, model_simple_cnot, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSMUL, model_simple_csmul, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSDIV, model_simple_csdiv, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CUDIV, model_simple_cudiv, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSLL, model_simple_csll, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSRL, model_simple_csrl, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSRA, model_simple_csra, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSCAN, model_simple_cscan, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ADDCC, model_simple_addcc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SUBCC, model_simple_subcc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ANDCC, model_simple_andcc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ORCC, model_simple_orcc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_XORCC, model_simple_xorcc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SLLCC, model_simple_sllcc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SRLCC, model_simple_srlcc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SRACC, model_simple_sracc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SMULCC, model_simple_smulcc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_UMULCC, model_simple_umulcc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CADDCC, model_simple_caddcc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSUBCC, model_simple_csubcc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSMULCC, model_simple_csmulcc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CANDCC, model_simple_candcc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CORCC, model_simple_corcc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CXORCC, model_simple_cxorcc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSLLCC, model_simple_csllcc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSRLCC, model_simple_csrlcc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSRACC, model_simple_csracc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ADDX, model_simple_addx, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SUBX, model_simple_subx, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ADDXCC, model_simple_addxcc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SUBXCC, model_simple_subxcc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ADDSS, model_simple_addss, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SUBSS, model_simple_subss, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ADDI, model_simple_addi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SUBI, model_simple_subi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ANDI, model_simple_andi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ORI, model_simple_ori, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_XORI, model_simple_xori, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SDIVI, model_simple_sdivi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NSDIVI, model_simple_nsdivi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_UDIVI, model_simple_udivi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NUDIVI, model_simple_nudivi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SMULI, model_simple_smuli, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_UMULI, model_simple_umuli, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SLLI, model_simple_slli, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SRLI, model_simple_srli, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SRAI, model_simple_srai, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SCANI, model_simple_scani, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ADDICC, model_simple_addicc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SUBICC, model_simple_subicc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ANDICC, model_simple_andicc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ORICC, model_simple_oricc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_XORICC, model_simple_xoricc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SMULICC, model_simple_smulicc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_UMULICC, model_simple_umulicc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SLLICC, model_simple_sllicc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SRLICC, model_simple_srlicc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SRAICC, model_simple_sraicc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ADDXI, model_simple_addxi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SUBXI, model_simple_subxi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ADDXICC, model_simple_addxicc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SUBXICC, model_simple_subxicc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMPB, model_simple_cmpb, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMPBA, model_simple_cmpba, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SETLO, model_simple_setlo, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SETHI, model_simple_sethi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SETLOS, model_simple_setlos, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDSB, model_simple_ldsb, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDUB, model_simple_ldub, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDSH, model_simple_ldsh, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDUH, model_simple_lduh, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LD, model_simple_ld, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDBF, model_simple_ldbf, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDHF, model_simple_ldhf, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDF, model_simple_ldf, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDC, model_simple_ldc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDSB, model_simple_nldsb, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDUB, model_simple_nldub, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDSH, model_simple_nldsh, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDUH, model_simple_nlduh, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLD, model_simple_nld, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDBF, model_simple_nldbf, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDHF, model_simple_nldhf, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDF, model_simple_nldf, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDD, model_simple_ldd, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDDF, model_simple_lddf, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDDC, model_simple_lddc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDD, model_simple_nldd, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDDF, model_simple_nlddf, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDQ, model_simple_ldq, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDQF, model_simple_ldqf, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDQC, model_simple_ldqc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDQ, model_simple_nldq, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDQF, model_simple_nldqf, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDSBU, model_simple_ldsbu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDUBU, model_simple_ldubu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDSHU, model_simple_ldshu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDUHU, model_simple_lduhu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDU, model_simple_ldu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDSBU, model_simple_nldsbu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDUBU, model_simple_nldubu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDSHU, model_simple_nldshu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDUHU, model_simple_nlduhu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDU, model_simple_nldu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDBFU, model_simple_ldbfu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDHFU, model_simple_ldhfu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDFU, model_simple_ldfu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDCU, model_simple_ldcu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDBFU, model_simple_nldbfu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDHFU, model_simple_nldhfu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDFU, model_simple_nldfu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDDU, model_simple_lddu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDDU, model_simple_nlddu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDDFU, model_simple_lddfu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDDCU, model_simple_lddcu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDDFU, model_simple_nlddfu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDQU, model_simple_ldqu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDQU, model_simple_nldqu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDQFU, model_simple_ldqfu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDQCU, model_simple_ldqcu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDQFU, model_simple_nldqfu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDSBI, model_simple_ldsbi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDSHI, model_simple_ldshi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDI, model_simple_ldi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDUBI, model_simple_ldubi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDUHI, model_simple_lduhi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDBFI, model_simple_ldbfi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDHFI, model_simple_ldhfi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDFI, model_simple_ldfi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDSBI, model_simple_nldsbi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDUBI, model_simple_nldubi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDSHI, model_simple_nldshi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDUHI, model_simple_nlduhi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDI, model_simple_nldi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDBFI, model_simple_nldbfi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDHFI, model_simple_nldhfi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDFI, model_simple_nldfi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDDI, model_simple_lddi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDDFI, model_simple_lddfi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDDI, model_simple_nlddi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDDFI, model_simple_nlddfi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDQI, model_simple_ldqi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDQFI, model_simple_ldqfi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDQFI, model_simple_nldqfi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STB, model_simple_stb, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STH, model_simple_sth, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ST, model_simple_st, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STBF, model_simple_stbf, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STHF, model_simple_sthf, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STF, model_simple_stf, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STC, model_simple_stc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_RSTB, model_simple_rstb, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_RSTH, model_simple_rsth, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_RST, model_simple_rst, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_RSTBF, model_simple_rstbf, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_RSTHF, model_simple_rsthf, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_RSTF, model_simple_rstf, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STD, model_simple_std, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STDF, model_simple_stdf, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STDC, model_simple_stdc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_RSTD, model_simple_rstd, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_RSTDF, model_simple_rstdf, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STQ, model_simple_stq, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STQF, model_simple_stqf, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STQC, model_simple_stqc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_RSTQ, model_simple_rstq, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_RSTQF, model_simple_rstqf, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STBU, model_simple_stbu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STHU, model_simple_sthu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STU, model_simple_stu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STBFU, model_simple_stbfu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STHFU, model_simple_sthfu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STFU, model_simple_stfu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STCU, model_simple_stcu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STDU, model_simple_stdu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STDFU, model_simple_stdfu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STDCU, model_simple_stdcu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STQU, model_simple_stqu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STQFU, model_simple_stqfu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STQCU, model_simple_stqcu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLDSB, model_simple_cldsb, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLDUB, model_simple_cldub, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLDSH, model_simple_cldsh, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLDUH, model_simple_clduh, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLD, model_simple_cld, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLDBF, model_simple_cldbf, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLDHF, model_simple_cldhf, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLDF, model_simple_cldf, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLDD, model_simple_cldd, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLDDF, model_simple_clddf, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLDQ, model_simple_cldq, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLDSBU, model_simple_cldsbu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLDUBU, model_simple_cldubu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLDSHU, model_simple_cldshu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLDUHU, model_simple_clduhu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLDU, model_simple_cldu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLDBFU, model_simple_cldbfu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLDHFU, model_simple_cldhfu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLDFU, model_simple_cldfu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLDDU, model_simple_clddu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLDDFU, model_simple_clddfu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLDQU, model_simple_cldqu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSTB, model_simple_cstb, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSTH, model_simple_csth, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CST, model_simple_cst, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSTBF, model_simple_cstbf, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSTHF, model_simple_csthf, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSTF, model_simple_cstf, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSTD, model_simple_cstd, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSTDF, model_simple_cstdf, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSTQ, model_simple_cstq, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSTBU, model_simple_cstbu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSTHU, model_simple_csthu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSTU, model_simple_cstu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSTBFU, model_simple_cstbfu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSTHFU, model_simple_csthfu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSTFU, model_simple_cstfu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSTDU, model_simple_cstdu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSTDFU, model_simple_cstdfu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STBI, model_simple_stbi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STHI, model_simple_sthi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STI, model_simple_sti, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STBFI, model_simple_stbfi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STHFI, model_simple_sthfi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STFI, model_simple_stfi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STDI, model_simple_stdi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STDFI, model_simple_stdfi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STQI, model_simple_stqi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STQFI, model_simple_stqfi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SWAP, model_simple_swap, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SWAPI, model_simple_swapi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSWAP, model_simple_cswap, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MOVGF, model_simple_movgf, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MOVFG, model_simple_movfg, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MOVGFD, model_simple_movgfd, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MOVFGD, model_simple_movfgd, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MOVGFQ, model_simple_movgfq, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MOVFGQ, model_simple_movfgq, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMOVGF, model_simple_cmovgf, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMOVFG, model_simple_cmovfg, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMOVGFD, model_simple_cmovgfd, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMOVFGD, model_simple_cmovfgd, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MOVGS, model_simple_movgs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MOVSG, model_simple_movsg, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BRA, model_simple_bra, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BNO, model_simple_bno, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BEQ, model_simple_beq, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BNE, model_simple_bne, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BLE, model_simple_ble, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BGT, model_simple_bgt, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BLT, model_simple_blt, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BGE, model_simple_bge, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BLS, model_simple_bls, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BHI, model_simple_bhi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BC, model_simple_bc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BNC, model_simple_bnc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BN, model_simple_bn, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BP, model_simple_bp, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BV, model_simple_bv, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BNV, model_simple_bnv, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBRA, model_simple_fbra, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBNO, model_simple_fbno, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBNE, model_simple_fbne, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBEQ, model_simple_fbeq, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBLG, model_simple_fblg, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBUE, model_simple_fbue, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBUL, model_simple_fbul, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBGE, model_simple_fbge, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBLT, model_simple_fblt, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBUGE, model_simple_fbuge, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBUG, model_simple_fbug, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBLE, model_simple_fble, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBGT, model_simple_fbgt, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBULE, model_simple_fbule, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBU, model_simple_fbu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBO, model_simple_fbo, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BCTRLR, model_simple_bctrlr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BRALR, model_simple_bralr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BNOLR, model_simple_bnolr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BEQLR, model_simple_beqlr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BNELR, model_simple_bnelr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BLELR, model_simple_blelr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BGTLR, model_simple_bgtlr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BLTLR, model_simple_bltlr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BGELR, model_simple_bgelr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BLSLR, model_simple_blslr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BHILR, model_simple_bhilr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BCLR, model_simple_bclr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BNCLR, model_simple_bnclr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BNLR, model_simple_bnlr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BPLR, model_simple_bplr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BVLR, model_simple_bvlr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BNVLR, model_simple_bnvlr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBRALR, model_simple_fbralr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBNOLR, model_simple_fbnolr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBEQLR, model_simple_fbeqlr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBNELR, model_simple_fbnelr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBLGLR, model_simple_fblglr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBUELR, model_simple_fbuelr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBULLR, model_simple_fbullr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBGELR, model_simple_fbgelr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBLTLR, model_simple_fbltlr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBUGELR, model_simple_fbugelr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBUGLR, model_simple_fbuglr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBLELR, model_simple_fblelr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBGTLR, model_simple_fbgtlr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBULELR, model_simple_fbulelr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBULR, model_simple_fbulr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FBOLR, model_simple_fbolr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BCRALR, model_simple_bcralr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BCNOLR, model_simple_bcnolr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BCEQLR, model_simple_bceqlr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BCNELR, model_simple_bcnelr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BCLELR, model_simple_bclelr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BCGTLR, model_simple_bcgtlr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BCLTLR, model_simple_bcltlr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BCGELR, model_simple_bcgelr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BCLSLR, model_simple_bclslr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BCHILR, model_simple_bchilr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BCCLR, model_simple_bcclr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BCNCLR, model_simple_bcnclr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BCNLR, model_simple_bcnlr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BCPLR, model_simple_bcplr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BCVLR, model_simple_bcvlr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BCNVLR, model_simple_bcnvlr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCBRALR, model_simple_fcbralr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCBNOLR, model_simple_fcbnolr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCBEQLR, model_simple_fcbeqlr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCBNELR, model_simple_fcbnelr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCBLGLR, model_simple_fcblglr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCBUELR, model_simple_fcbuelr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCBULLR, model_simple_fcbullr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCBGELR, model_simple_fcbgelr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCBLTLR, model_simple_fcbltlr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCBUGELR, model_simple_fcbugelr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCBUGLR, model_simple_fcbuglr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCBLELR, model_simple_fcblelr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCBGTLR, model_simple_fcbgtlr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCBULELR, model_simple_fcbulelr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCBULR, model_simple_fcbulr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCBOLR, model_simple_fcbolr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_JMPL, model_simple_jmpl, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CALLL, model_simple_calll, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_JMPIL, model_simple_jmpil, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CALLIL, model_simple_callil, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CALL, model_simple_call, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_RETT, model_simple_rett, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_REI, model_simple_rei, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TRA, model_simple_tra, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TNO, model_simple_tno, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TEQ, model_simple_teq, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TNE, model_simple_tne, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TLE, model_simple_tle, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TGT, model_simple_tgt, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TLT, model_simple_tlt, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TGE, model_simple_tge, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TLS, model_simple_tls, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_THI, model_simple_thi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TC, model_simple_tc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TNC, model_simple_tnc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TN, model_simple_tn, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TP, model_simple_tp, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TV, model_simple_tv, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TNV, model_simple_tnv, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTRA, model_simple_ftra, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTNO, model_simple_ftno, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTNE, model_simple_ftne, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTEQ, model_simple_fteq, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTLG, model_simple_ftlg, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTUE, model_simple_ftue, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTUL, model_simple_ftul, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTGE, model_simple_ftge, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTLT, model_simple_ftlt, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTUGE, model_simple_ftuge, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTUG, model_simple_ftug, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTLE, model_simple_ftle, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTGT, model_simple_ftgt, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTULE, model_simple_ftule, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTU, model_simple_ftu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTO, model_simple_fto, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TIRA, model_simple_tira, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TINO, model_simple_tino, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TIEQ, model_simple_tieq, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TINE, model_simple_tine, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TILE, model_simple_tile, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TIGT, model_simple_tigt, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TILT, model_simple_tilt, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TIGE, model_simple_tige, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TILS, model_simple_tils, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TIHI, model_simple_tihi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TIC, model_simple_tic, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TINC, model_simple_tinc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TIN, model_simple_tin, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TIP, model_simple_tip, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TIV, model_simple_tiv, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TINV, model_simple_tinv, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTIRA, model_simple_ftira, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTINO, model_simple_ftino, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTINE, model_simple_ftine, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTIEQ, model_simple_ftieq, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTILG, model_simple_ftilg, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTIUE, model_simple_ftiue, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTIUL, model_simple_ftiul, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTIGE, model_simple_ftige, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTILT, model_simple_ftilt, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTIUGE, model_simple_ftiuge, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTIUG, model_simple_ftiug, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTILE, model_simple_ftile, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTIGT, model_simple_ftigt, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTIULE, model_simple_ftiule, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTIU, model_simple_ftiu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTIO, model_simple_ftio, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BREAK, model_simple_break, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MTRAP, model_simple_mtrap, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ANDCR, model_simple_andcr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ORCR, model_simple_orcr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_XORCR, model_simple_xorcr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NANDCR, model_simple_nandcr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NORCR, model_simple_norcr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ANDNCR, model_simple_andncr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ORNCR, model_simple_orncr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NANDNCR, model_simple_nandncr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NORNCR, model_simple_norncr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NOTCR, model_simple_notcr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CKRA, model_simple_ckra, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CKNO, model_simple_ckno, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CKEQ, model_simple_ckeq, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CKNE, model_simple_ckne, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CKLE, model_simple_ckle, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CKGT, model_simple_ckgt, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CKLT, model_simple_cklt, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CKGE, model_simple_ckge, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CKLS, model_simple_ckls, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CKHI, model_simple_ckhi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CKC, model_simple_ckc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CKNC, model_simple_cknc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CKN, model_simple_ckn, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CKP, model_simple_ckp, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CKV, model_simple_ckv, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CKNV, model_simple_cknv, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCKRA, model_simple_fckra, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCKNO, model_simple_fckno, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCKNE, model_simple_fckne, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCKEQ, model_simple_fckeq, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCKLG, model_simple_fcklg, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCKUE, model_simple_fckue, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCKUL, model_simple_fckul, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCKGE, model_simple_fckge, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCKLT, model_simple_fcklt, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCKUGE, model_simple_fckuge, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCKUG, model_simple_fckug, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCKLE, model_simple_fckle, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCKGT, model_simple_fckgt, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCKULE, model_simple_fckule, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCKU, model_simple_fcku, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCKO, model_simple_fcko, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CCKRA, model_simple_cckra, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CCKNO, model_simple_cckno, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CCKEQ, model_simple_cckeq, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CCKNE, model_simple_cckne, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CCKLE, model_simple_cckle, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CCKGT, model_simple_cckgt, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CCKLT, model_simple_ccklt, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CCKGE, model_simple_cckge, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CCKLS, model_simple_cckls, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CCKHI, model_simple_cckhi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CCKC, model_simple_cckc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CCKNC, model_simple_ccknc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CCKN, model_simple_cckn, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CCKP, model_simple_cckp, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CCKV, model_simple_cckv, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CCKNV, model_simple_ccknv, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFCKRA, model_simple_cfckra, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFCKNO, model_simple_cfckno, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFCKNE, model_simple_cfckne, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFCKEQ, model_simple_cfckeq, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFCKLG, model_simple_cfcklg, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFCKUE, model_simple_cfckue, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFCKUL, model_simple_cfckul, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFCKGE, model_simple_cfckge, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFCKLT, model_simple_cfcklt, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFCKUGE, model_simple_cfckuge, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFCKUG, model_simple_cfckug, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFCKLE, model_simple_cfckle, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFCKGT, model_simple_cfckgt, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFCKULE, model_simple_cfckule, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFCKU, model_simple_cfcku, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFCKO, model_simple_cfcko, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CJMPL, model_simple_cjmpl, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CCALLL, model_simple_ccalll, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ICI, model_simple_ici, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_DCI, model_simple_dci, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ICEI, model_simple_icei, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_DCEI, model_simple_dcei, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_DCF, model_simple_dcf, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_DCEF, model_simple_dcef, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_WITLB, model_simple_witlb, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_WDTLB, model_simple_wdtlb, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ITLBI, model_simple_itlbi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_DTLBI, model_simple_dtlbi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ICPL, model_simple_icpl, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_DCPL, model_simple_dcpl, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ICUL, model_simple_icul, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_DCUL, model_simple_dcul, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_BAR, model_simple_bar, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MEMBAR, model_simple_membar, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_COP1, model_simple_cop1, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_COP2, model_simple_cop2, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLRGR, model_simple_clrgr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLRFR, model_simple_clrfr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLRGA, model_simple_clrga, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLRFA, model_simple_clrfa, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_COMMITGR, model_simple_commitgr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_COMMITFR, model_simple_commitfr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_COMMITGA, model_simple_commitga, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_COMMITFA, model_simple_commitfa, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FITOS, model_simple_fitos, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FSTOI, model_simple_fstoi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FITOD, model_simple_fitod, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDTOI, model_simple_fdtoi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDITOS, model_simple_fditos, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDSTOI, model_simple_fdstoi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFDITOS, model_simple_nfditos, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFDSTOI, model_simple_nfdstoi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFITOS, model_simple_cfitos, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFSTOI, model_simple_cfstoi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFITOS, model_simple_nfitos, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFSTOI, model_simple_nfstoi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FMOVS, model_simple_fmovs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FMOVD, model_simple_fmovd, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDMOVS, model_simple_fdmovs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFMOVS, model_simple_cfmovs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FNEGS, model_simple_fnegs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FNEGD, model_simple_fnegd, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDNEGS, model_simple_fdnegs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFNEGS, model_simple_cfnegs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FABSS, model_simple_fabss, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FABSD, model_simple_fabsd, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDABSS, model_simple_fdabss, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFABSS, model_simple_cfabss, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FSQRTS, model_simple_fsqrts, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDSQRTS, model_simple_fdsqrts, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFDSQRTS, model_simple_nfdsqrts, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FSQRTD, model_simple_fsqrtd, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFSQRTS, model_simple_cfsqrts, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFSQRTS, model_simple_nfsqrts, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FADDS, model_simple_fadds, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FSUBS, model_simple_fsubs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FMULS, model_simple_fmuls, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDIVS, model_simple_fdivs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FADDD, model_simple_faddd, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FSUBD, model_simple_fsubd, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FMULD, model_simple_fmuld, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDIVD, model_simple_fdivd, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFADDS, model_simple_cfadds, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFSUBS, model_simple_cfsubs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFMULS, model_simple_cfmuls, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFDIVS, model_simple_cfdivs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFADDS, model_simple_nfadds, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFSUBS, model_simple_nfsubs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFMULS, model_simple_nfmuls, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFDIVS, model_simple_nfdivs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCMPS, model_simple_fcmps, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCMPD, model_simple_fcmpd, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFCMPS, model_simple_cfcmps, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDCMPS, model_simple_fdcmps, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FMADDS, model_simple_fmadds, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FMSUBS, model_simple_fmsubs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FMADDD, model_simple_fmaddd, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FMSUBD, model_simple_fmsubd, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDMADDS, model_simple_fdmadds, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFDMADDS, model_simple_nfdmadds, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFMADDS, model_simple_cfmadds, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFMSUBS, model_simple_cfmsubs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFMADDS, model_simple_nfmadds, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFMSUBS, model_simple_nfmsubs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FMAS, model_simple_fmas, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FMSS, model_simple_fmss, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDMAS, model_simple_fdmas, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDMSS, model_simple_fdmss, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFDMAS, model_simple_nfdmas, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFDMSS, model_simple_nfdmss, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFMAS, model_simple_cfmas, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFMSS, model_simple_cfmss, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FMAD, model_simple_fmad, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FMSD, model_simple_fmsd, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFMAS, model_simple_nfmas, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFMSS, model_simple_nfmss, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDADDS, model_simple_fdadds, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDSUBS, model_simple_fdsubs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDMULS, model_simple_fdmuls, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDDIVS, model_simple_fddivs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDSADS, model_simple_fdsads, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDMULCS, model_simple_fdmulcs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFDMULCS, model_simple_nfdmulcs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFDADDS, model_simple_nfdadds, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFDSUBS, model_simple_nfdsubs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFDMULS, model_simple_nfdmuls, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFDDIVS, model_simple_nfddivs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFDSADS, model_simple_nfdsads, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFDCMPS, model_simple_nfdcmps, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MHSETLOS, model_simple_mhsetlos, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MHSETHIS, model_simple_mhsethis, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MHDSETS, model_simple_mhdsets, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MHSETLOH, model_simple_mhsetloh, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MHSETHIH, model_simple_mhsethih, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MHDSETH, model_simple_mhdseth, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MAND, model_simple_mand, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MOR, model_simple_mor, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MXOR, model_simple_mxor, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMAND, model_simple_cmand, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMOR, model_simple_cmor, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMXOR, model_simple_cmxor, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MNOT, model_simple_mnot, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMNOT, model_simple_cmnot, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MROTLI, model_simple_mrotli, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MROTRI, model_simple_mrotri, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MWCUT, model_simple_mwcut, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MWCUTI, model_simple_mwcuti, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MCUT, model_simple_mcut, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MCUTI, model_simple_mcuti, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MCUTSS, model_simple_mcutss, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MCUTSSI, model_simple_mcutssi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MDCUTSSI, model_simple_mdcutssi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MAVEH, model_simple_maveh, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MSLLHI, model_simple_msllhi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MSRLHI, model_simple_msrlhi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MSRAHI, model_simple_msrahi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MDROTLI, model_simple_mdrotli, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MCPLHI, model_simple_mcplhi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MCPLI, model_simple_mcpli, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MSATHS, model_simple_msaths, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQSATHS, model_simple_mqsaths, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MSATHU, model_simple_msathu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MCMPSH, model_simple_mcmpsh, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MCMPUH, model_simple_mcmpuh, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MABSHS, model_simple_mabshs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MADDHSS, model_simple_maddhss, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MADDHUS, model_simple_maddhus, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MSUBHSS, model_simple_msubhss, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MSUBHUS, model_simple_msubhus, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMADDHSS, model_simple_cmaddhss, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMADDHUS, model_simple_cmaddhus, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMSUBHSS, model_simple_cmsubhss, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMSUBHUS, model_simple_cmsubhus, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQADDHSS, model_simple_mqaddhss, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQADDHUS, model_simple_mqaddhus, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQSUBHSS, model_simple_mqsubhss, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQSUBHUS, model_simple_mqsubhus, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMQADDHSS, model_simple_cmqaddhss, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMQADDHUS, model_simple_cmqaddhus, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMQSUBHSS, model_simple_cmqsubhss, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMQSUBHUS, model_simple_cmqsubhus, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MADDACCS, model_simple_maddaccs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MSUBACCS, model_simple_msubaccs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MDADDACCS, model_simple_mdaddaccs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MDSUBACCS, model_simple_mdsubaccs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MASACCS, model_simple_masaccs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MDASACCS, model_simple_mdasaccs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MMULHS, model_simple_mmulhs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MMULHU, model_simple_mmulhu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MMULXHS, model_simple_mmulxhs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MMULXHU, model_simple_mmulxhu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMMULHS, model_simple_cmmulhs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMMULHU, model_simple_cmmulhu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQMULHS, model_simple_mqmulhs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQMULHU, model_simple_mqmulhu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQMULXHS, model_simple_mqmulxhs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQMULXHU, model_simple_mqmulxhu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMQMULHS, model_simple_cmqmulhs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMQMULHU, model_simple_cmqmulhu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MMACHS, model_simple_mmachs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MMACHU, model_simple_mmachu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MMRDHS, model_simple_mmrdhs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MMRDHU, model_simple_mmrdhu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMMACHS, model_simple_cmmachs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMMACHU, model_simple_cmmachu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQMACHS, model_simple_mqmachs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQMACHU, model_simple_mqmachu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMQMACHS, model_simple_cmqmachs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMQMACHU, model_simple_cmqmachu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQXMACHS, model_simple_mqxmachs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQXMACXHS, model_simple_mqxmacxhs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQMACXHS, model_simple_mqmacxhs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MCPXRS, model_simple_mcpxrs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MCPXRU, model_simple_mcpxru, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MCPXIS, model_simple_mcpxis, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MCPXIU, model_simple_mcpxiu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMCPXRS, model_simple_cmcpxrs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMCPXRU, model_simple_cmcpxru, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMCPXIS, model_simple_cmcpxis, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMCPXIU, model_simple_cmcpxiu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQCPXRS, model_simple_mqcpxrs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQCPXRU, model_simple_mqcpxru, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQCPXIS, model_simple_mqcpxis, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQCPXIU, model_simple_mqcpxiu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MEXPDHW, model_simple_mexpdhw, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMEXPDHW, model_simple_cmexpdhw, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MEXPDHD, model_simple_mexpdhd, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMEXPDHD, model_simple_cmexpdhd, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MPACKH, model_simple_mpackh, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MDPACKH, model_simple_mdpackh, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MUNPACKH, model_simple_munpackh, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MDUNPACKH, model_simple_mdunpackh, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MBTOH, model_simple_mbtoh, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMBTOH, model_simple_cmbtoh, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MHTOB, model_simple_mhtob, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMHTOB, model_simple_cmhtob, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MBTOHE, model_simple_mbtohe, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMBTOHE, model_simple_cmbtohe, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MNOP, model_simple_mnop, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MCLRACC_0, model_simple_mclracc_0, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MCLRACC_1, model_simple_mclracc_1, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MRDACC, model_simple_mrdacc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MRDACCG, model_simple_mrdaccg, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MWTACC, model_simple_mwtacc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MWTACCG, model_simple_mwtaccg, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MCOP1, model_simple_mcop1, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MCOP2, model_simple_mcop2, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FNOP, model_simple_fnop, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, +}; + +#endif /* WITH_PROFILE_MODEL_P */ + +static void +frv_model_init (SIM_CPU *cpu) +{ + CPU_MODEL_DATA (cpu) = (void *) zalloc (sizeof (MODEL_FRV_DATA)); +} + +static void +fr550_model_init (SIM_CPU *cpu) +{ + CPU_MODEL_DATA (cpu) = (void *) zalloc (sizeof (MODEL_FR550_DATA)); +} + +static void +fr500_model_init (SIM_CPU *cpu) +{ + CPU_MODEL_DATA (cpu) = (void *) zalloc (sizeof (MODEL_FR500_DATA)); +} + +static void +tomcat_model_init (SIM_CPU *cpu) +{ + CPU_MODEL_DATA (cpu) = (void *) zalloc (sizeof (MODEL_TOMCAT_DATA)); +} + +static void +fr400_model_init (SIM_CPU *cpu) +{ + CPU_MODEL_DATA (cpu) = (void *) zalloc (sizeof (MODEL_FR400_DATA)); +} + +static void +simple_model_init (SIM_CPU *cpu) +{ + CPU_MODEL_DATA (cpu) = (void *) zalloc (sizeof (MODEL_SIMPLE_DATA)); +} + +#if WITH_PROFILE_MODEL_P +#define TIMING_DATA(td) td +#else +#define TIMING_DATA(td) 0 +#endif + +static const MODEL frv_models[] = +{ + { "frv", & frv_mach, MODEL_FRV, TIMING_DATA (& frv_timing[0]), frv_model_init }, + { 0 } +}; + +static const MODEL fr550_models[] = +{ + { "fr550", & fr550_mach, MODEL_FR550, TIMING_DATA (& fr550_timing[0]), fr550_model_init }, + { 0 } +}; + +static const MODEL fr500_models[] = +{ + { "fr500", & fr500_mach, MODEL_FR500, TIMING_DATA (& fr500_timing[0]), fr500_model_init }, + { 0 } +}; + +static const MODEL tomcat_models[] = +{ + { "tomcat", & tomcat_mach, MODEL_TOMCAT, TIMING_DATA (& tomcat_timing[0]), tomcat_model_init }, + { 0 } +}; + +static const MODEL fr400_models[] = +{ + { "fr400", & fr400_mach, MODEL_FR400, TIMING_DATA (& fr400_timing[0]), fr400_model_init }, + { 0 } +}; + +static const MODEL simple_models[] = +{ + { "simple", & simple_mach, MODEL_SIMPLE, TIMING_DATA (& simple_timing[0]), simple_model_init }, + { 0 } +}; + +/* The properties of this cpu's implementation. */ + +static const MACH_IMP_PROPERTIES frvbf_imp_properties = +{ + sizeof (SIM_CPU), +#if WITH_SCACHE + sizeof (SCACHE) +#else + 0 +#endif +}; + + +static void +frvbf_prepare_run (SIM_CPU *cpu) +{ + if (CPU_IDESC (cpu) == NULL) + frvbf_init_idesc_table (cpu); +} + +static const CGEN_INSN * +frvbf_get_idata (SIM_CPU *cpu, int inum) +{ + return CPU_IDESC (cpu) [inum].idata; +} + +static void +frv_init_cpu (SIM_CPU *cpu) +{ + CPU_REG_FETCH (cpu) = frvbf_fetch_register; + CPU_REG_STORE (cpu) = frvbf_store_register; + CPU_PC_FETCH (cpu) = frvbf_h_pc_get; + CPU_PC_STORE (cpu) = frvbf_h_pc_set; + CPU_GET_IDATA (cpu) = frvbf_get_idata; + CPU_MAX_INSNS (cpu) = FRVBF_INSN__MAX; + CPU_INSN_NAME (cpu) = cgen_insn_name; + CPU_FULL_ENGINE_FN (cpu) = frvbf_engine_run_full; +#if WITH_FAST + CPU_FAST_ENGINE_FN (cpu) = frvbf_engine_run_fast; +#else + CPU_FAST_ENGINE_FN (cpu) = frvbf_engine_run_full; +#endif +} + +const MACH frv_mach = +{ + "frv", "frv", MACH_FRV, + 32, 32, & frv_models[0], & frvbf_imp_properties, + frv_init_cpu, + frvbf_prepare_run +}; + +static void +fr550_init_cpu (SIM_CPU *cpu) +{ + CPU_REG_FETCH (cpu) = frvbf_fetch_register; + CPU_REG_STORE (cpu) = frvbf_store_register; + CPU_PC_FETCH (cpu) = frvbf_h_pc_get; + CPU_PC_STORE (cpu) = frvbf_h_pc_set; + CPU_GET_IDATA (cpu) = frvbf_get_idata; + CPU_MAX_INSNS (cpu) = FRVBF_INSN__MAX; + CPU_INSN_NAME (cpu) = cgen_insn_name; + CPU_FULL_ENGINE_FN (cpu) = frvbf_engine_run_full; +#if WITH_FAST + CPU_FAST_ENGINE_FN (cpu) = frvbf_engine_run_fast; +#else + CPU_FAST_ENGINE_FN (cpu) = frvbf_engine_run_full; +#endif +} + +const MACH fr550_mach = +{ + "fr550", "fr550", MACH_FR550, + 32, 32, & fr550_models[0], & frvbf_imp_properties, + fr550_init_cpu, + frvbf_prepare_run +}; + +static void +fr500_init_cpu (SIM_CPU *cpu) +{ + CPU_REG_FETCH (cpu) = frvbf_fetch_register; + CPU_REG_STORE (cpu) = frvbf_store_register; + CPU_PC_FETCH (cpu) = frvbf_h_pc_get; + CPU_PC_STORE (cpu) = frvbf_h_pc_set; + CPU_GET_IDATA (cpu) = frvbf_get_idata; + CPU_MAX_INSNS (cpu) = FRVBF_INSN__MAX; + CPU_INSN_NAME (cpu) = cgen_insn_name; + CPU_FULL_ENGINE_FN (cpu) = frvbf_engine_run_full; +#if WITH_FAST + CPU_FAST_ENGINE_FN (cpu) = frvbf_engine_run_fast; +#else + CPU_FAST_ENGINE_FN (cpu) = frvbf_engine_run_full; +#endif +} + +const MACH fr500_mach = +{ + "fr500", "fr500", MACH_FR500, + 32, 32, & fr500_models[0], & frvbf_imp_properties, + fr500_init_cpu, + frvbf_prepare_run +}; + +static void +tomcat_init_cpu (SIM_CPU *cpu) +{ + CPU_REG_FETCH (cpu) = frvbf_fetch_register; + CPU_REG_STORE (cpu) = frvbf_store_register; + CPU_PC_FETCH (cpu) = frvbf_h_pc_get; + CPU_PC_STORE (cpu) = frvbf_h_pc_set; + CPU_GET_IDATA (cpu) = frvbf_get_idata; + CPU_MAX_INSNS (cpu) = FRVBF_INSN__MAX; + CPU_INSN_NAME (cpu) = cgen_insn_name; + CPU_FULL_ENGINE_FN (cpu) = frvbf_engine_run_full; +#if WITH_FAST + CPU_FAST_ENGINE_FN (cpu) = frvbf_engine_run_fast; +#else + CPU_FAST_ENGINE_FN (cpu) = frvbf_engine_run_full; +#endif +} + +const MACH tomcat_mach = +{ + "tomcat", "tomcat", MACH_TOMCAT, + 32, 32, & tomcat_models[0], & frvbf_imp_properties, + tomcat_init_cpu, + frvbf_prepare_run +}; + +static void +fr400_init_cpu (SIM_CPU *cpu) +{ + CPU_REG_FETCH (cpu) = frvbf_fetch_register; + CPU_REG_STORE (cpu) = frvbf_store_register; + CPU_PC_FETCH (cpu) = frvbf_h_pc_get; + CPU_PC_STORE (cpu) = frvbf_h_pc_set; + CPU_GET_IDATA (cpu) = frvbf_get_idata; + CPU_MAX_INSNS (cpu) = FRVBF_INSN__MAX; + CPU_INSN_NAME (cpu) = cgen_insn_name; + CPU_FULL_ENGINE_FN (cpu) = frvbf_engine_run_full; +#if WITH_FAST + CPU_FAST_ENGINE_FN (cpu) = frvbf_engine_run_fast; +#else + CPU_FAST_ENGINE_FN (cpu) = frvbf_engine_run_full; +#endif +} + +const MACH fr400_mach = +{ + "fr400", "fr400", MACH_FR400, + 32, 32, & fr400_models[0], & frvbf_imp_properties, + fr400_init_cpu, + frvbf_prepare_run +}; + +static void +simple_init_cpu (SIM_CPU *cpu) +{ + CPU_REG_FETCH (cpu) = frvbf_fetch_register; + CPU_REG_STORE (cpu) = frvbf_store_register; + CPU_PC_FETCH (cpu) = frvbf_h_pc_get; + CPU_PC_STORE (cpu) = frvbf_h_pc_set; + CPU_GET_IDATA (cpu) = frvbf_get_idata; + CPU_MAX_INSNS (cpu) = FRVBF_INSN__MAX; + CPU_INSN_NAME (cpu) = cgen_insn_name; + CPU_FULL_ENGINE_FN (cpu) = frvbf_engine_run_full; +#if WITH_FAST + CPU_FAST_ENGINE_FN (cpu) = frvbf_engine_run_fast; +#else + CPU_FAST_ENGINE_FN (cpu) = frvbf_engine_run_full; +#endif +} + +const MACH simple_mach = +{ + "simple", "simple", MACH_SIMPLE, + 32, 32, & simple_models[0], & frvbf_imp_properties, + simple_init_cpu, + frvbf_prepare_run +}; + diff --git a/sim/frv/options.c b/sim/frv/options.c new file mode 100644 index 0000000..039a01f --- /dev/null +++ b/sim/frv/options.c @@ -0,0 +1,237 @@ +/* FRV simulator memory option handling. + Copyright (C) 1999, 2000 Free Software Foundation, Inc. + Contributed by Red Hat. + +This file is part of GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#define WANT_CPU frvbf +#define WANT_CPU_FRVBF + +#include "sim-main.h" +#include "sim-assert.h" +#include "sim-options.h" + +#ifdef HAVE_STRING_H +#include +#else +#ifdef HAVE_STRINGS_H +#include +#endif +#endif +#ifdef HAVE_STDLIB_H +#include +#endif + +/* FRV specific command line options. */ + +enum { + OPTION_FRV_DATA_CACHE = OPTION_START, + OPTION_FRV_INSN_CACHE, + OPTION_FRV_PROFILE_CACHE, + OPTION_FRV_PROFILE_PARALLEL, + OPTION_FRV_TIMER, + OPTION_FRV_MEMORY_LATENCY +}; + +static DECLARE_OPTION_HANDLER (frv_option_handler); + +const OPTION frv_options[] = +{ + { {"profile", optional_argument, NULL, 'p'}, + 'p', "on|off", "Perform profiling", + frv_option_handler }, + { {"data-cache", optional_argument, NULL, OPTION_FRV_DATA_CACHE }, + '\0', "WAYS[,SETS[,LINESIZE]]", "Enable data cache", + frv_option_handler }, + { {"insn-cache", optional_argument, NULL, OPTION_FRV_INSN_CACHE }, + '\0', "WAYS[,SETS[,LINESIZE]]", "Enable instruction cache", + frv_option_handler }, + { {"profile-cache", optional_argument, NULL, OPTION_FRV_PROFILE_CACHE }, + '\0', "on|off", "Profile caches", + frv_option_handler }, + { {"profile-parallel", optional_argument, NULL, OPTION_FRV_PROFILE_PARALLEL }, + '\0', "on|off", "Profile parallelism", + frv_option_handler }, + { {"timer", required_argument, NULL, OPTION_FRV_TIMER }, + '\0', "CYCLES,INTERRUPT", "Set Interrupt Timer", + frv_option_handler }, + { {"memory-latency", required_argument, NULL, OPTION_FRV_MEMORY_LATENCY }, + '\0', "CYCLES", "Set Latency of memory", + frv_option_handler }, + { {NULL, no_argument, NULL, 0}, '\0', NULL, NULL, NULL } +}; + +static char * +parse_size (char *chp, address_word *nr_bytes) +{ + /* */ + *nr_bytes = strtoul (chp, &chp, 0); + return chp; +} + +static address_word +check_pow2 (address_word value, char *argname, char *optname, SIM_DESC sd) +{ + if ((value & (value - 1)) != 0) + { + sim_io_eprintf (sd, "%s argument to %s must be a power of 2\n", + argname, optname); + return 0; /* will enable default value. */ + } + + return value; +} + +static void +parse_cache_option (SIM_DESC sd, char *arg, char *cache_name, int is_data_cache) +{ + int i; + address_word ways = 0, sets = 0, linesize = 0; + if (arg != NULL) + { + char *chp = arg; + /* parse the arguments */ + chp = parse_size (chp, &ways); + ways = check_pow2 (ways, "WAYS", cache_name, sd); + if (*chp == ',') + { + chp = parse_size (chp + 1, &sets); + sets = check_pow2 (sets, "SETS", cache_name, sd); + if (*chp == ',') + { + chp = parse_size (chp + 1, &linesize); + linesize = check_pow2 (linesize, "LINESIZE", cache_name, sd); + } + } + } + for (i = 0; i < MAX_NR_PROCESSORS; ++i) + { + SIM_CPU *current_cpu = STATE_CPU (sd, i); + FRV_CACHE *cache = is_data_cache ? CPU_DATA_CACHE (current_cpu) + : CPU_INSN_CACHE (current_cpu); + cache->ways = ways; + cache->sets = sets; + cache->line_size = linesize; + frv_cache_init (current_cpu, cache); + } +} + +static SIM_RC +frv_option_handler (SIM_DESC sd, sim_cpu *current_cpu, int opt, + char *arg, int is_command) +{ + switch (opt) + { + case 'p' : + if (! WITH_PROFILE) + sim_io_eprintf (sd, "Profiling not compiled in, `-p' ignored\n"); + else + { + unsigned mask = PROFILE_USEFUL_MASK; + if (WITH_PROFILE_CACHE_P) + mask |= (1 << PROFILE_CACHE_IDX); + if (WITH_PROFILE_PARALLEL_P) + mask |= (1 << PROFILE_PARALLEL_IDX); + return set_profile_option_mask (sd, "profile", mask, arg); + } + break; + + case OPTION_FRV_DATA_CACHE: + parse_cache_option (sd, arg, "data_cache", 1/*is_data_cache*/); + return SIM_RC_OK; + + case OPTION_FRV_INSN_CACHE: + parse_cache_option (sd, arg, "insn_cache", 0/*is_data_cache*/); + return SIM_RC_OK; + + case OPTION_FRV_PROFILE_CACHE: + if (WITH_PROFILE_CACHE_P) + return sim_profile_set_option (sd, "-cache", PROFILE_CACHE_IDX, arg); + else + sim_io_eprintf (sd, "Cache profiling not compiled in, `--profile-cache' ignored\n"); + break; + + case OPTION_FRV_PROFILE_PARALLEL: + if (WITH_PROFILE_PARALLEL_P) + { + unsigned mask + = (1 << PROFILE_MODEL_IDX) | (1 << PROFILE_PARALLEL_IDX); + return set_profile_option_mask (sd, "-parallel", mask, arg); + } + else + sim_io_eprintf (sd, "Parallel profiling not compiled in, `--profile-parallel' ignored\n"); + break; + + case OPTION_FRV_TIMER: + { + char *chp = arg; + address_word cycles, interrupt; + chp = parse_size (chp, &cycles); + if (chp == arg) + { + sim_io_eprintf (sd, "Cycle count required for --timer\n"); + return SIM_RC_FAIL; + } + if (*chp != ',') + { + sim_io_eprintf (sd, "Interrupt number required for --timer\n"); + return SIM_RC_FAIL; + } + chp = parse_size (chp + 1, &interrupt); + if (interrupt < 1 || interrupt > 15) + { + sim_io_eprintf (sd, "Interrupt number for --timer must be greater than 0 and less that 16\n"); + return SIM_RC_FAIL; + } + frv_interrupt_state.timer.enabled = 1; + frv_interrupt_state.timer.value = cycles; + frv_interrupt_state.timer.current = 0; + frv_interrupt_state.timer.interrupt = + FRV_INTERRUPT_LEVEL_1 + interrupt - 1; + } + return SIM_RC_OK; + + case OPTION_FRV_MEMORY_LATENCY: + { + int i; + char *chp = arg; + address_word cycles; + chp = parse_size (chp, &cycles); + if (chp == arg) + { + sim_io_eprintf (sd, "Cycle count required for --memory-latency\n"); + return SIM_RC_FAIL; + } + for (i = 0; i < MAX_NR_PROCESSORS; ++i) + { + SIM_CPU *current_cpu = STATE_CPU (sd, i); + FRV_CACHE *insn_cache = CPU_INSN_CACHE (current_cpu); + FRV_CACHE *data_cache = CPU_DATA_CACHE (current_cpu); + insn_cache->memory_latency = cycles; + data_cache->memory_latency = cycles; + } + } + return SIM_RC_OK; + + default: + sim_io_eprintf (sd, "Unknown FRV option %d\n", opt); + return SIM_RC_FAIL; + + } + + return SIM_RC_FAIL; +} diff --git a/sim/frv/pipeline.c b/sim/frv/pipeline.c new file mode 100644 index 0000000..291a5dc --- /dev/null +++ b/sim/frv/pipeline.c @@ -0,0 +1,92 @@ +/* frv vliw model. + Copyright (C) 1999, 2000, 2001, 2003 Free Software Foundation, Inc. + Contributed by Red Hat. + +This file is part of the GNU simulators. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#define WANT_CPU frvbf +#define WANT_CPU_FRVBF + +#include "sim-main.h" + +/* Simulator specific vliw related functions. Additional vliw related + code used by both the simulator and the assembler is in frv.opc. */ + +int insns_in_slot[UNIT_NUM_UNITS] = {0}; + +void +frv_vliw_setup_insn (SIM_CPU *current_cpu, const CGEN_INSN *insn) +{ + FRV_VLIW *vliw; + int index; + + /* Always clear the NE index which indicates the target register + of a non excepting insn. This will be reset by the insn if + necessary. */ + frv_interrupt_state.ne_index = NE_NOFLAG; + + vliw = CPU_VLIW (current_cpu); + index = vliw->next_slot - 1; + if (frv_is_float_insn (insn)) + { + /* If the insn is to be added and is a floating point insn and + it is the first floating point insn in the vliw, then clear + FSR0.FTT. */ + int i; + for (i = 0; i < index; ++i) + if (frv_is_float_major (vliw->major[i], vliw->mach)) + break; /* found float insn. */ + if (i >= index) + { + SI fsr0 = GET_FSR (0); + SET_FSR_FTT (fsr0, FTT_NONE); + SET_FSR (0, fsr0); + } + } + else if (frv_is_media_insn (insn)) + { + /* Clear the appropriate MSR fields depending on which slot + this insn is in. */ + CGEN_ATTR_VALUE_TYPE preserve_ovf; + SI msr0 = GET_MSR (0); + + preserve_ovf = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_PRESERVE_OVF); + if ((*vliw->current_vliw)[index] == UNIT_FM0) + { + if (! preserve_ovf) + { + /* Clear MSR0.OVF and MSR0.SIE. */ + CLEAR_MSR_SIE (msr0); + CLEAR_MSR_OVF (msr0); + } + } + else + { + if (! preserve_ovf) + { + /* Clear MSR1.OVF and MSR1.SIE. */ + SI msr1 = GET_MSR (1); + CLEAR_MSR_SIE (msr1); + CLEAR_MSR_OVF (msr1); + SET_MSR (1, msr1); + } + } + SET_MSR (0, msr0); + } /* Insn is a media insns. */ + COUNT_INSNS_IN_SLOT ((*vliw->current_vliw)[index]); +} + diff --git a/sim/frv/profile-fr400.c b/sim/frv/profile-fr400.c new file mode 100644 index 0000000..698e06e --- /dev/null +++ b/sim/frv/profile-fr400.c @@ -0,0 +1,2126 @@ +/* frv simulator fr400 dependent profiling code. + + Copyright (C) 2001 Free Software Foundation, Inc. + Contributed by Red Hat + +This file is part of the GNU simulators. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +*/ +#define WANT_CPU +#define WANT_CPU_FRVBF + +#include "sim-main.h" +#include "bfd.h" + +#if WITH_PROFILE_MODEL_P + +#include "profile.h" +#include "profile-fr400.h" + +/* These functions get and set flags representing the use of + registers/resources. */ +static void set_use_not_fp_load (SIM_CPU *, INT); +static void set_use_not_media_p4 (SIM_CPU *, INT); +static void set_use_not_media_p6 (SIM_CPU *, INT); + +static void set_acc_use_not_media_p2 (SIM_CPU *, INT); +static void set_acc_use_not_media_p4 (SIM_CPU *, INT); + +void +fr400_reset_gr_flags (SIM_CPU *cpu, INT fr) +{ + set_use_not_gr_complex (cpu, fr); +} + +void +fr400_reset_fr_flags (SIM_CPU *cpu, INT fr) +{ + set_use_not_fp_load (cpu, fr); + set_use_not_media_p4 (cpu, fr); + set_use_not_media_p6 (cpu, fr); +} + +void +fr400_reset_acc_flags (SIM_CPU *cpu, INT acc) +{ + set_acc_use_not_media_p2 (cpu, acc); + set_acc_use_not_media_p4 (cpu, acc); +} + +static void +set_use_is_fp_load (SIM_CPU *cpu, INT fr, INT fr_double) +{ + MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu); + if (fr != -1) + { + fr400_reset_fr_flags (cpu, fr); + d->cur_fp_load |= (((DI)1) << fr); + } + if (fr_double != -1) + { + fr400_reset_fr_flags (cpu, fr_double); + d->cur_fp_load |= (((DI)1) << fr_double); + if (fr_double < 63) + { + fr400_reset_fr_flags (cpu, fr_double + 1); + d->cur_fp_load |= (((DI)1) << (fr_double + 1)); + } + } + +} + +static void +set_use_not_fp_load (SIM_CPU *cpu, INT fr) +{ + MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu); + if (fr != -1) + d->cur_fp_load &= ~(((DI)1) << fr); +} + +static int +use_is_fp_load (SIM_CPU *cpu, INT fr) +{ + MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu); + if (fr != -1) + return (d->prev_fp_load >> fr) & 1; + return 0; +} + +static void +set_acc_use_is_media_p2 (SIM_CPU *cpu, INT acc) +{ + MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu); + if (acc != -1) + { + fr400_reset_acc_flags (cpu, acc); + d->cur_acc_p2 |= (((DI)1) << acc); + } +} + +static void +set_acc_use_not_media_p2 (SIM_CPU *cpu, INT acc) +{ + MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu); + if (acc != -1) + d->cur_acc_p2 &= ~(((DI)1) << acc); +} + +static int +acc_use_is_media_p2 (SIM_CPU *cpu, INT acc) +{ + MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu); + if (acc != -1) + return d->cur_acc_p2 & (((DI)1) << acc); + return 0; +} + +static void +set_use_is_media_p4 (SIM_CPU *cpu, INT fr) +{ + MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu); + if (fr != -1) + { + fr400_reset_fr_flags (cpu, fr); + d->cur_fr_p4 |= (((DI)1) << fr); + } +} + +static void +set_use_not_media_p4 (SIM_CPU *cpu, INT fr) +{ + MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu); + if (fr != -1) + d->cur_fr_p4 &= ~(((DI)1) << fr); +} + +static int +use_is_media_p4 (SIM_CPU *cpu, INT fr) +{ + MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu); + if (fr != -1) + return d->cur_fr_p4 & (((DI)1) << fr); + return 0; +} + +static void +set_acc_use_is_media_p4 (SIM_CPU *cpu, INT acc) +{ + MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu); + if (acc != -1) + { + fr400_reset_acc_flags (cpu, acc); + d->cur_acc_p4 |= (((DI)1) << acc); + } +} + +static void +set_acc_use_not_media_p4 (SIM_CPU *cpu, INT acc) +{ + MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu); + if (acc != -1) + d->cur_acc_p4 &= ~(((DI)1) << acc); +} + +static int +acc_use_is_media_p4 (SIM_CPU *cpu, INT acc) +{ + MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu); + if (acc != -1) + return d->cur_acc_p4 & (((DI)1) << acc); + return 0; +} + +static void +set_use_is_media_p6 (SIM_CPU *cpu, INT fr) +{ + MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu); + if (fr != -1) + { + fr400_reset_fr_flags (cpu, fr); + d->cur_fr_p6 |= (((DI)1) << fr); + } +} + +static void +set_use_not_media_p6 (SIM_CPU *cpu, INT fr) +{ + MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu); + if (fr != -1) + d->cur_fr_p6 &= ~(((DI)1) << fr); +} + +static int +use_is_media_p6 (SIM_CPU *cpu, INT fr) +{ + MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu); + if (fr != -1) + return d->cur_fr_p6 & (((DI)1) << fr); + return 0; +} + +/* Initialize cycle counting for an insn. + FIRST_P is non-zero if this is the first insn in a set of parallel + insns. */ +void +fr400_model_insn_before (SIM_CPU *cpu, int first_p) +{ + if (first_p) + { + MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu); + FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu); + ps->cur_gr_complex = ps->prev_gr_complex; + d->cur_fp_load = d->prev_fp_load; + d->cur_fr_p4 = d->prev_fr_p4; + d->cur_fr_p6 = d->prev_fr_p6; + d->cur_acc_p2 = d->prev_acc_p2; + d->cur_acc_p4 = d->prev_acc_p4; + } +} + +/* Record the cycles computed for an insn. + LAST_P is non-zero if this is the last insn in a set of parallel insns, + and we update the total cycle count. + CYCLES is the cycle count of the insn. */ +void +fr400_model_insn_after (SIM_CPU *cpu, int last_p, int cycles) +{ + if (last_p) + { + MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu); + FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu); + ps->prev_gr_complex = ps->cur_gr_complex; + d->prev_fp_load = d->cur_fp_load; + d->prev_fr_p4 = d->cur_fr_p4; + d->prev_fr_p6 = d->cur_fr_p6; + d->prev_acc_p2 = d->cur_acc_p2; + d->prev_acc_p4 = d->cur_acc_p4; + } +} + +int +frvbf_model_fr400_u_exec (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced) +{ + return idesc->timing->units[unit_num].done; +} + +int +frvbf_model_fr400_u_integer (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRi, INT in_GRj, INT out_GRk, + INT out_ICCi_1) +{ + /* Modelling for this unit is the same as for fr500. */ + return frvbf_model_fr500_u_integer (cpu, idesc, unit_num, referenced, + in_GRi, in_GRj, out_GRk, out_ICCi_1); +} + +int +frvbf_model_fr400_u_imul (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRi, INT in_GRj, INT out_GRk, INT out_ICCi_1) +{ + /* Modelling for this unit is the same as for fr500. */ + return frvbf_model_fr500_u_imul (cpu, idesc, unit_num, referenced, + in_GRi, in_GRj, out_GRk, out_ICCi_1); +} + +int +frvbf_model_fr400_u_idiv (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRi, INT in_GRj, INT out_GRk, INT out_ICCi_1) +{ + int cycles; + FRV_VLIW *vliw; + int slot; + + /* icc0-icc4 are the upper 4 fields of the CCR. */ + if (out_ICCi_1 >= 0) + out_ICCi_1 += 4; + + vliw = CPU_VLIW (cpu); + slot = vliw->next_slot - 1; + slot = (*vliw->current_vliw)[slot] - UNIT_I0; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + { + /* The entire VLIW insn must wait if there is a dependency on a register + which is not ready yet. + The latency of the registers may be less than previously recorded, + depending on how they were used previously. + See Table 13-8 in the LSI. */ + if (in_GRi != out_GRk && in_GRi >= 0) + { + if (use_is_gr_complex (cpu, in_GRi)) + decrease_GR_busy (cpu, in_GRi, 1); + } + if (in_GRj != out_GRk && in_GRj != in_GRi && in_GRj >= 0) + { + if (use_is_gr_complex (cpu, in_GRj)) + decrease_GR_busy (cpu, in_GRj, 1); + } + vliw_wait_for_GR (cpu, in_GRi); + vliw_wait_for_GR (cpu, in_GRj); + vliw_wait_for_GR (cpu, out_GRk); + vliw_wait_for_CCR (cpu, out_ICCi_1); + vliw_wait_for_idiv_resource (cpu, slot); + handle_resource_wait (cpu); + load_wait_for_GR (cpu, in_GRi); + load_wait_for_GR (cpu, in_GRj); + load_wait_for_GR (cpu, out_GRk); + trace_vliw_wait_cycles (cpu); + return 0; + } + + /* GRk has a latency of 19 cycles! */ + cycles = idesc->timing->units[unit_num].done; + update_GR_latency (cpu, out_GRk, cycles + 19); + set_use_is_gr_complex (cpu, out_GRk); + + /* ICCi_1 has a latency of 18 cycles. */ + update_CCR_latency (cpu, out_ICCi_1, cycles + 18); + + /* the idiv resource has a latency of 18 cycles! */ + update_idiv_resource_latency (cpu, slot, cycles + 18); + + return cycles; +} + +int +frvbf_model_fr400_u_branch (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRi, INT in_GRj, + INT in_ICCi_2, INT in_ICCi_3) +{ +#define BRANCH_PREDICTED(ps) ((ps)->branch_hint & 2) + FRV_PROFILE_STATE *ps; + int cycles; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + { + /* Modelling for this unit is the same as for fr500 in pass 1. */ + return frvbf_model_fr500_u_branch (cpu, idesc, unit_num, referenced, + in_GRi, in_GRj, in_ICCi_2, in_ICCi_3); + } + + cycles = idesc->timing->units[unit_num].done; + + /* Compute the branch penalty, based on the the prediction and the out + come. When counting branches taken or not taken, don't consider branches + after the first taken branch in a vliw insn. */ + ps = CPU_PROFILE_STATE (cpu); + if (! ps->vliw_branch_taken) + { + int penalty; + /* (1 << 4): The pc is the 5th element in inputs, outputs. + ??? can be cleaned up */ + PROFILE_DATA *p = CPU_PROFILE_DATA (cpu); + int taken = (referenced & (1 << 4)) != 0; + if (taken) + { + ++PROFILE_MODEL_TAKEN_COUNT (p); + ps->vliw_branch_taken = 1; + if (BRANCH_PREDICTED (ps)) + penalty = 1; + else + penalty = 3; + } + else + { + ++PROFILE_MODEL_UNTAKEN_COUNT (p); + if (BRANCH_PREDICTED (ps)) + penalty = 3; + else + penalty = 0; + } + if (penalty > 0) + { + /* Additional 1 cycle penalty if the branch address is not 8 byte + aligned. */ + if (ps->branch_address & 7) + ++penalty; + update_branch_penalty (cpu, penalty); + PROFILE_MODEL_CTI_STALL_CYCLES (p) += penalty; + } + } + + return cycles; +} + +int +frvbf_model_fr400_u_trap (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRi, INT in_GRj, + INT in_ICCi_2, INT in_FCCi_2) +{ + /* Modelling for this unit is the same as for fr500. */ + return frvbf_model_fr500_u_trap (cpu, idesc, unit_num, referenced, + in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); +} + +int +frvbf_model_fr400_u_check (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_ICCi_3, INT in_FCCi_3) +{ + /* Modelling for this unit is the same as for fr500. */ + return frvbf_model_fr500_u_check (cpu, idesc, unit_num, referenced, + in_ICCi_3, in_FCCi_3); +} + +int +frvbf_model_fr400_u_set_hilo (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT out_GRkhi, INT out_GRklo) +{ + /* Modelling for this unit is the same as for fr500. */ + return frvbf_model_fr500_u_set_hilo (cpu, idesc, unit_num, referenced, + out_GRkhi, out_GRklo); +} + +int +frvbf_model_fr400_u_gr_load (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRi, INT in_GRj, + INT out_GRk, INT out_GRdoublek) +{ + /* Modelling for this unit is the same as for fr500. */ + return frvbf_model_fr500_u_gr_load (cpu, idesc, unit_num, referenced, + in_GRi, in_GRj, out_GRk, out_GRdoublek); +} + +int +frvbf_model_fr400_u_gr_store (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRi, INT in_GRj, + INT in_GRk, INT in_GRdoublek) +{ + /* Modelling for this unit is the same as for fr500. */ + return frvbf_model_fr500_u_gr_store (cpu, idesc, unit_num, referenced, + in_GRi, in_GRj, in_GRk, in_GRdoublek); +} + +int +frvbf_model_fr400_u_fr_load (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRi, INT in_GRj, + INT out_FRk, INT out_FRdoublek) +{ + int cycles; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + { + /* Pass 1 is the same as for fr500. */ + return frvbf_model_fr500_u_fr_load (cpu, idesc, unit_num, referenced, + in_GRi, in_GRj, out_FRk, + out_FRdoublek); + } + + cycles = idesc->timing->units[unit_num].done; + + /* The latency of FRk for a load will depend on how long it takes to retrieve + the the data from the cache or memory. */ + update_FR_latency_for_load (cpu, out_FRk, cycles); + update_FRdouble_latency_for_load (cpu, out_FRdoublek, cycles); + + set_use_is_fp_load (cpu, out_FRk, out_FRdoublek); + + return cycles; +} + +int +frvbf_model_fr400_u_fr_store (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRi, INT in_GRj, + INT in_FRk, INT in_FRdoublek) +{ + int cycles; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + { + /* The entire VLIW insn must wait if there is a dependency on a register + which is not ready yet. + The latency of the registers may be less than previously recorded, + depending on how they were used previously. + See Table 13-8 in the LSI. */ + if (in_GRi >= 0) + { + if (use_is_gr_complex (cpu, in_GRi)) + decrease_GR_busy (cpu, in_GRi, 1); + } + if (in_GRj != in_GRi && in_GRj >= 0) + { + if (use_is_gr_complex (cpu, in_GRj)) + decrease_GR_busy (cpu, in_GRj, 1); + } + if (in_FRk >= 0) + { + if (use_is_media_p4 (cpu, in_FRk) || use_is_media_p6 (cpu, in_FRk)) + decrease_FR_busy (cpu, in_FRk, 1); + else + enforce_full_fr_latency (cpu, in_FRk); + } + vliw_wait_for_GR (cpu, in_GRi); + vliw_wait_for_GR (cpu, in_GRj); + vliw_wait_for_FR (cpu, in_FRk); + vliw_wait_for_FRdouble (cpu, in_FRdoublek); + handle_resource_wait (cpu); + load_wait_for_GR (cpu, in_GRi); + load_wait_for_GR (cpu, in_GRj); + load_wait_for_FR (cpu, in_FRk); + load_wait_for_FRdouble (cpu, in_FRdoublek); + trace_vliw_wait_cycles (cpu); + return 0; + } + + cycles = idesc->timing->units[unit_num].done; + + return cycles; +} + +int +frvbf_model_fr400_u_swap (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRi, INT in_GRj, INT out_GRk) +{ + /* Modelling for this unit is the same as for fr500. */ + return frvbf_model_fr500_u_swap (cpu, idesc, unit_num, referenced, + in_GRi, in_GRj, out_GRk); +} + +int +frvbf_model_fr400_u_fr2gr (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_FRk, INT out_GRj) +{ + int cycles; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + { + /* The entire VLIW insn must wait if there is a dependency on a register + which is not ready yet. + The latency of the registers may be less than previously recorded, + depending on how they were used previously. + See Table 13-8 in the LSI. */ + if (in_FRk >= 0) + { + if (use_is_media_p4 (cpu, in_FRk) || use_is_media_p6 (cpu, in_FRk)) + decrease_FR_busy (cpu, in_FRk, 1); + else + enforce_full_fr_latency (cpu, in_FRk); + } + vliw_wait_for_FR (cpu, in_FRk); + vliw_wait_for_GR (cpu, out_GRj); + handle_resource_wait (cpu); + load_wait_for_FR (cpu, in_FRk); + load_wait_for_GR (cpu, out_GRj); + trace_vliw_wait_cycles (cpu); + return 0; + } + + /* The latency of GRj is 2 cycles. */ + cycles = idesc->timing->units[unit_num].done; + update_GR_latency (cpu, out_GRj, cycles + 2); + set_use_is_gr_complex (cpu, out_GRj); + + return cycles; +} + +int +frvbf_model_fr400_u_spr2gr (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_spr, INT out_GRj) +{ + /* Modelling for this unit is the same as for fr500. */ + return frvbf_model_fr500_u_spr2gr (cpu, idesc, unit_num, referenced, + in_spr, out_GRj); +} + +int +frvbf_model_fr400_u_gr2fr (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRj, INT out_FRk) +{ + int cycles; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + { + /* Pass 1 is the same as for fr500. */ + frvbf_model_fr500_u_gr2fr (cpu, idesc, unit_num, referenced, + in_GRj, out_FRk); + } + + /* The latency of FRk is 1 cycles. */ + cycles = idesc->timing->units[unit_num].done; + update_FR_latency (cpu, out_FRk, cycles + 1); + + return cycles; +} + +int +frvbf_model_fr400_u_gr2spr (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRj, INT out_spr) +{ + /* Modelling for this unit is the same as for fr500. */ + return frvbf_model_fr500_u_gr2spr (cpu, idesc, unit_num, referenced, + in_GRj, out_spr); +} + +int +frvbf_model_fr400_u_media_1 (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_FRi, INT in_FRj, + INT out_FRk) +{ + int cycles; + FRV_PROFILE_STATE *ps; + const CGEN_INSN *insn; + int busy_adjustment[] = {0, 0}; + int *fr; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + return 0; + + /* The preprocessing can execute right away. */ + cycles = idesc->timing->units[unit_num].done; + + ps = CPU_PROFILE_STATE (cpu); + insn = idesc->idata; + + /* The latency of the registers may be less than previously recorded, + depending on how they were used previously. + See Table 13-8 in the LSI. */ + if (in_FRi >= 0) + { + if (use_is_fp_load (cpu, in_FRi)) + { + busy_adjustment[0] = 1; + decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]); + } + else + enforce_full_fr_latency (cpu, in_FRi); + } + if (in_FRj >= 0 && in_FRj != in_FRi) + { + if (use_is_fp_load (cpu, in_FRj)) + { + busy_adjustment[1] = 1; + decrease_FR_busy (cpu, in_FRj, busy_adjustment[1]); + } + else + enforce_full_fr_latency (cpu, in_FRj); + } + + /* The post processing must wait if there is a dependency on a FR + which is not ready yet. */ + ps->post_wait = cycles; + post_wait_for_FR (cpu, in_FRi); + post_wait_for_FR (cpu, in_FRj); + post_wait_for_FR (cpu, out_FRk); + + /* Restore the busy cycles of the registers we used. */ + fr = ps->fr_busy; + if (in_FRi >= 0) + fr[in_FRi] += busy_adjustment[0]; + if (in_FRj >= 0) + fr[in_FRj] += busy_adjustment[1]; + + /* The latency of the output register will be at least the latency of the + other inputs. Once initiated, post-processing has no latency. */ + if (out_FRk >= 0) + { + update_FR_latency (cpu, out_FRk, ps->post_wait); + update_FR_ptime (cpu, out_FRk, 0); + } + + return cycles; +} + +int +frvbf_model_fr400_u_media_1_quad (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_FRi, INT in_FRj, + INT out_FRk) +{ + int cycles; + INT dual_FRi; + INT dual_FRj; + INT dual_FRk; + FRV_PROFILE_STATE *ps; + int busy_adjustment[] = {0, 0, 0, 0}; + int *fr; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + return 0; + + /* The preprocessing can execute right away. */ + cycles = idesc->timing->units[unit_num].done; + + ps = CPU_PROFILE_STATE (cpu); + dual_FRi = DUAL_REG (in_FRi); + dual_FRj = DUAL_REG (in_FRj); + dual_FRk = DUAL_REG (out_FRk); + + /* The latency of the registers may be less than previously recorded, + depending on how they were used previously. + See Table 13-8 in the LSI. */ + if (use_is_fp_load (cpu, in_FRi)) + { + busy_adjustment[0] = 1; + decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]); + } + else + enforce_full_fr_latency (cpu, in_FRi); + if (dual_FRi >= 0 && use_is_fp_load (cpu, dual_FRi)) + { + busy_adjustment[1] = 1; + decrease_FR_busy (cpu, dual_FRi, busy_adjustment[1]); + } + else + enforce_full_fr_latency (cpu, dual_FRi); + if (in_FRj != in_FRi) + { + if (use_is_fp_load (cpu, in_FRj)) + { + busy_adjustment[2] = 1; + decrease_FR_busy (cpu, in_FRj, busy_adjustment[2]); + } + else + enforce_full_fr_latency (cpu, in_FRj); + if (dual_FRj >= 0 && use_is_fp_load (cpu, dual_FRj)) + { + busy_adjustment[3] = 1; + decrease_FR_busy (cpu, dual_FRj, busy_adjustment[3]); + } + else + enforce_full_fr_latency (cpu, dual_FRj); + } + + /* The post processing must wait if there is a dependency on a FR + which is not ready yet. */ + ps->post_wait = cycles; + post_wait_for_FR (cpu, in_FRi); + post_wait_for_FR (cpu, dual_FRi); + post_wait_for_FR (cpu, in_FRj); + post_wait_for_FR (cpu, dual_FRj); + post_wait_for_FR (cpu, out_FRk); + post_wait_for_FR (cpu, dual_FRk); + + /* Restore the busy cycles of the registers we used. */ + fr = ps->fr_busy; + fr[in_FRi] += busy_adjustment[0]; + if (dual_FRi >= 0) + fr[dual_FRi] += busy_adjustment[1]; + fr[in_FRj] += busy_adjustment[2]; + if (dual_FRj >= 0) + fr[dual_FRj] += busy_adjustment[3]; + + /* The latency of the output register will be at least the latency of the + other inputs. */ + update_FR_latency (cpu, out_FRk, ps->post_wait); + + /* Once initiated, post-processing has no latency. */ + update_FR_ptime (cpu, out_FRk, 0); + + if (dual_FRk >= 0) + { + update_FR_latency (cpu, dual_FRk, ps->post_wait); + update_FR_ptime (cpu, dual_FRk, 0); + } + + return cycles; +} + +int +frvbf_model_fr400_u_media_hilo (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT out_FRkhi, INT out_FRklo) +{ + int cycles; + FRV_PROFILE_STATE *ps; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + return 0; + + /* The preprocessing can execute right away. */ + cycles = idesc->timing->units[unit_num].done; + + ps = CPU_PROFILE_STATE (cpu); + + /* The post processing must wait if there is a dependency on a FR + which is not ready yet. */ + ps->post_wait = cycles; + post_wait_for_FR (cpu, out_FRkhi); + post_wait_for_FR (cpu, out_FRklo); + + /* The latency of the output register will be at least the latency of the + other inputs. Once initiated, post-processing has no latency. */ + if (out_FRkhi >= 0) + { + update_FR_latency (cpu, out_FRkhi, ps->post_wait); + update_FR_ptime (cpu, out_FRkhi, 0); + } + if (out_FRklo >= 0) + { + update_FR_latency (cpu, out_FRklo, ps->post_wait); + update_FR_ptime (cpu, out_FRklo, 0); + } + + return cycles; +} + +int +frvbf_model_fr400_u_media_2 (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_FRi, INT in_FRj, + INT out_ACC40Sk, INT out_ACC40Uk) +{ + int cycles; + INT dual_ACC40Sk; + INT dual_ACC40Uk; + FRV_PROFILE_STATE *ps; + int busy_adjustment[] = {0, 0, 0, 0, 0, 0}; + int *fr; + int *acc; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + return 0; + + /* The preprocessing can execute right away. */ + cycles = idesc->timing->units[unit_num].done; + + ps = CPU_PROFILE_STATE (cpu); + dual_ACC40Sk = DUAL_REG (out_ACC40Sk); + dual_ACC40Uk = DUAL_REG (out_ACC40Uk); + + /* The latency of the registers may be less than previously recorded, + depending on how they were used previously. + See Table 13-8 in the LSI. */ + if (in_FRi >= 0) + { + if (use_is_fp_load (cpu, in_FRi)) + { + busy_adjustment[0] = 1; + decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]); + } + else + enforce_full_fr_latency (cpu, in_FRi); + } + if (in_FRj >= 0 && in_FRj != in_FRi) + { + if (use_is_fp_load (cpu, in_FRj)) + { + busy_adjustment[1] = 1; + decrease_FR_busy (cpu, in_FRj, busy_adjustment[1]); + } + else + enforce_full_fr_latency (cpu, in_FRj); + } + if (out_ACC40Sk >= 0) + { + if (acc_use_is_media_p2 (cpu, out_ACC40Sk)) + { + busy_adjustment[2] = 1; + decrease_ACC_busy (cpu, out_ACC40Sk, busy_adjustment[2]); + } + } + if (dual_ACC40Sk >= 0) + { + if (acc_use_is_media_p2 (cpu, dual_ACC40Sk)) + { + busy_adjustment[3] = 1; + decrease_ACC_busy (cpu, dual_ACC40Sk, busy_adjustment[3]); + } + } + if (out_ACC40Uk >= 0) + { + if (acc_use_is_media_p2 (cpu, out_ACC40Uk)) + { + busy_adjustment[4] = 1; + decrease_ACC_busy (cpu, out_ACC40Uk, busy_adjustment[4]); + } + } + if (dual_ACC40Uk >= 0) + { + if (acc_use_is_media_p2 (cpu, dual_ACC40Uk)) + { + busy_adjustment[5] = 1; + decrease_ACC_busy (cpu, dual_ACC40Uk, busy_adjustment[5]); + } + } + + /* The post processing must wait if there is a dependency on a FR + which is not ready yet. */ + ps->post_wait = cycles; + post_wait_for_FR (cpu, in_FRi); + post_wait_for_FR (cpu, in_FRj); + post_wait_for_ACC (cpu, out_ACC40Sk); + post_wait_for_ACC (cpu, dual_ACC40Sk); + post_wait_for_ACC (cpu, out_ACC40Uk); + post_wait_for_ACC (cpu, dual_ACC40Uk); + + /* Restore the busy cycles of the registers we used. */ + fr = ps->fr_busy; + acc = ps->acc_busy; + fr[in_FRi] += busy_adjustment[0]; + fr[in_FRj] += busy_adjustment[1]; + if (out_ACC40Sk >= 0) + acc[out_ACC40Sk] += busy_adjustment[2]; + if (dual_ACC40Sk >= 0) + acc[dual_ACC40Sk] += busy_adjustment[3]; + if (out_ACC40Uk >= 0) + acc[out_ACC40Uk] += busy_adjustment[4]; + if (dual_ACC40Uk >= 0) + acc[dual_ACC40Uk] += busy_adjustment[5]; + + /* The latency of the output register will be at least the latency of the + other inputs. Once initiated, post-processing will take 1 cycles. */ + if (out_ACC40Sk >= 0) + { + update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait + 1); + set_acc_use_is_media_p2 (cpu, out_ACC40Sk); + } + if (dual_ACC40Sk >= 0) + { + update_ACC_latency (cpu, dual_ACC40Sk, ps->post_wait + 1); + set_acc_use_is_media_p2 (cpu, dual_ACC40Sk); + } + if (out_ACC40Uk >= 0) + { + update_ACC_latency (cpu, out_ACC40Uk, ps->post_wait + 1); + set_acc_use_is_media_p2 (cpu, out_ACC40Uk); + } + if (dual_ACC40Uk >= 0) + { + update_ACC_latency (cpu, dual_ACC40Uk, ps->post_wait + 1); + set_acc_use_is_media_p2 (cpu, dual_ACC40Uk); + } + + return cycles; +} + +int +frvbf_model_fr400_u_media_2_quad (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_FRi, INT in_FRj, + INT out_ACC40Sk, INT out_ACC40Uk) +{ + int cycles; + INT dual_FRi; + INT dual_FRj; + INT ACC40Sk_1; + INT ACC40Sk_2; + INT ACC40Sk_3; + INT ACC40Uk_1; + INT ACC40Uk_2; + INT ACC40Uk_3; + FRV_PROFILE_STATE *ps; + int busy_adjustment[] = {0, 0, 0, 0, 0, 0, 0 ,0}; + int *fr; + int *acc; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + return 0; + + /* The preprocessing can execute right away. */ + cycles = idesc->timing->units[unit_num].done; + + dual_FRi = DUAL_REG (in_FRi); + dual_FRj = DUAL_REG (in_FRj); + ACC40Sk_1 = DUAL_REG (out_ACC40Sk); + ACC40Sk_2 = DUAL_REG (ACC40Sk_1); + ACC40Sk_3 = DUAL_REG (ACC40Sk_2); + ACC40Uk_1 = DUAL_REG (out_ACC40Uk); + ACC40Uk_2 = DUAL_REG (ACC40Uk_1); + ACC40Uk_3 = DUAL_REG (ACC40Uk_2); + + ps = CPU_PROFILE_STATE (cpu); + /* The latency of the registers may be less than previously recorded, + depending on how they were used previously. + See Table 13-8 in the LSI. */ + if (use_is_fp_load (cpu, in_FRi)) + { + busy_adjustment[0] = 1; + decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]); + } + else + enforce_full_fr_latency (cpu, in_FRi); + if (dual_FRi >= 0 && use_is_fp_load (cpu, dual_FRi)) + { + busy_adjustment[1] = 1; + decrease_FR_busy (cpu, dual_FRi, busy_adjustment[1]); + } + else + enforce_full_fr_latency (cpu, dual_FRi); + if (in_FRj != in_FRi) + { + if (use_is_fp_load (cpu, in_FRj)) + { + busy_adjustment[2] = 1; + decrease_FR_busy (cpu, in_FRj, busy_adjustment[2]); + } + else + enforce_full_fr_latency (cpu, in_FRj); + if (dual_FRj >= 0 && use_is_fp_load (cpu, dual_FRj)) + { + busy_adjustment[3] = 1; + decrease_FR_busy (cpu, dual_FRj, busy_adjustment[3]); + } + else + enforce_full_fr_latency (cpu, dual_FRj); + } + if (out_ACC40Sk >= 0) + { + if (acc_use_is_media_p2 (cpu, out_ACC40Sk)) + { + busy_adjustment[4] = 1; + decrease_ACC_busy (cpu, out_ACC40Sk, busy_adjustment[4]); + } + if (ACC40Sk_1 >= 0) + { + if (acc_use_is_media_p2 (cpu, ACC40Sk_1)) + { + busy_adjustment[5] = 1; + decrease_ACC_busy (cpu, ACC40Sk_1, busy_adjustment[5]); + } + } + if (ACC40Sk_2 >= 0) + { + if (acc_use_is_media_p2 (cpu, ACC40Sk_2)) + { + busy_adjustment[6] = 1; + decrease_ACC_busy (cpu, ACC40Sk_2, busy_adjustment[6]); + } + } + if (ACC40Sk_3 >= 0) + { + if (acc_use_is_media_p2 (cpu, ACC40Sk_3)) + { + busy_adjustment[7] = 1; + decrease_ACC_busy (cpu, ACC40Sk_3, busy_adjustment[7]); + } + } + } + else if (out_ACC40Uk >= 0) + { + if (acc_use_is_media_p2 (cpu, out_ACC40Uk)) + { + busy_adjustment[4] = 1; + decrease_ACC_busy (cpu, out_ACC40Uk, busy_adjustment[4]); + } + if (ACC40Uk_1 >= 0) + { + if (acc_use_is_media_p2 (cpu, ACC40Uk_1)) + { + busy_adjustment[5] = 1; + decrease_ACC_busy (cpu, ACC40Uk_1, busy_adjustment[5]); + } + } + if (ACC40Uk_2 >= 0) + { + if (acc_use_is_media_p2 (cpu, ACC40Uk_2)) + { + busy_adjustment[6] = 1; + decrease_ACC_busy (cpu, ACC40Uk_2, busy_adjustment[6]); + } + } + if (ACC40Uk_3 >= 0) + { + if (acc_use_is_media_p2 (cpu, ACC40Uk_3)) + { + busy_adjustment[7] = 1; + decrease_ACC_busy (cpu, ACC40Uk_3, busy_adjustment[7]); + } + } + } + + /* The post processing must wait if there is a dependency on a FR + which is not ready yet. */ + ps->post_wait = cycles; + post_wait_for_FR (cpu, in_FRi); + post_wait_for_FR (cpu, dual_FRi); + post_wait_for_FR (cpu, in_FRj); + post_wait_for_FR (cpu, dual_FRj); + post_wait_for_ACC (cpu, out_ACC40Sk); + post_wait_for_ACC (cpu, ACC40Sk_1); + post_wait_for_ACC (cpu, ACC40Sk_2); + post_wait_for_ACC (cpu, ACC40Sk_3); + post_wait_for_ACC (cpu, out_ACC40Uk); + post_wait_for_ACC (cpu, ACC40Uk_1); + post_wait_for_ACC (cpu, ACC40Uk_2); + post_wait_for_ACC (cpu, ACC40Uk_3); + + /* Restore the busy cycles of the registers we used. */ + fr = ps->fr_busy; + acc = ps->acc_busy; + fr[in_FRi] += busy_adjustment[0]; + if (dual_FRi >= 0) + fr[dual_FRi] += busy_adjustment[1]; + fr[in_FRj] += busy_adjustment[2]; + if (dual_FRj > 0) + fr[dual_FRj] += busy_adjustment[3]; + if (out_ACC40Sk >= 0) + { + acc[out_ACC40Sk] += busy_adjustment[4]; + if (ACC40Sk_1 >= 0) + acc[ACC40Sk_1] += busy_adjustment[5]; + if (ACC40Sk_2 >= 0) + acc[ACC40Sk_2] += busy_adjustment[6]; + if (ACC40Sk_3 >= 0) + acc[ACC40Sk_3] += busy_adjustment[7]; + } + else if (out_ACC40Uk >= 0) + { + acc[out_ACC40Uk] += busy_adjustment[4]; + if (ACC40Uk_1 >= 0) + acc[ACC40Uk_1] += busy_adjustment[5]; + if (ACC40Uk_2 >= 0) + acc[ACC40Uk_2] += busy_adjustment[6]; + if (ACC40Uk_3 >= 0) + acc[ACC40Uk_3] += busy_adjustment[7]; + } + + /* The latency of the output register will be at least the latency of the + other inputs. Once initiated, post-processing will take 1 cycle. */ + if (out_ACC40Sk >= 0) + { + update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait + 1); + + set_acc_use_is_media_p2 (cpu, out_ACC40Sk); + if (ACC40Sk_1 >= 0) + { + update_ACC_latency (cpu, ACC40Sk_1, ps->post_wait + 1); + + set_acc_use_is_media_p2 (cpu, ACC40Sk_1); + } + if (ACC40Sk_2 >= 0) + { + update_ACC_latency (cpu, ACC40Sk_2, ps->post_wait + 1); + + set_acc_use_is_media_p2 (cpu, ACC40Sk_2); + } + if (ACC40Sk_3 >= 0) + { + update_ACC_latency (cpu, ACC40Sk_3, ps->post_wait + 1); + + set_acc_use_is_media_p2 (cpu, ACC40Sk_3); + } + } + else if (out_ACC40Uk >= 0) + { + update_ACC_latency (cpu, out_ACC40Uk, ps->post_wait + 1); + + set_acc_use_is_media_p2 (cpu, out_ACC40Uk); + if (ACC40Uk_1 >= 0) + { + update_ACC_latency (cpu, ACC40Uk_1, ps->post_wait + 1); + + set_acc_use_is_media_p2 (cpu, ACC40Uk_1); + } + if (ACC40Uk_2 >= 0) + { + update_ACC_latency (cpu, ACC40Uk_2, ps->post_wait + 1); + + set_acc_use_is_media_p2 (cpu, ACC40Uk_2); + } + if (ACC40Uk_3 >= 0) + { + update_ACC_latency (cpu, ACC40Uk_3, ps->post_wait + 1); + + set_acc_use_is_media_p2 (cpu, ACC40Uk_3); + } + } + + return cycles; +} + +int +frvbf_model_fr400_u_media_2_acc (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_ACC40Si, INT out_ACC40Sk) +{ + int cycles; + INT ACC40Si_1; + FRV_PROFILE_STATE *ps; + int busy_adjustment[] = {0, 0, 0}; + int *acc; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + return 0; + + /* The preprocessing can execute right away. */ + cycles = idesc->timing->units[unit_num].done; + + ACC40Si_1 = DUAL_REG (in_ACC40Si); + + ps = CPU_PROFILE_STATE (cpu); + /* The latency of the registers may be less than previously recorded, + depending on how they were used previously. + See Table 13-8 in the LSI. */ + if (acc_use_is_media_p2 (cpu, in_ACC40Si)) + { + busy_adjustment[0] = 1; + decrease_ACC_busy (cpu, in_ACC40Si, busy_adjustment[0]); + } + if (ACC40Si_1 >= 0 && acc_use_is_media_p2 (cpu, ACC40Si_1)) + { + busy_adjustment[1] = 1; + decrease_ACC_busy (cpu, ACC40Si_1, busy_adjustment[1]); + } + if (out_ACC40Sk != in_ACC40Si && out_ACC40Sk != ACC40Si_1 + && acc_use_is_media_p2 (cpu, out_ACC40Sk)) + { + busy_adjustment[2] = 1; + decrease_ACC_busy (cpu, out_ACC40Sk, busy_adjustment[2]); + } + + /* The post processing must wait if there is a dependency on a register + which is not ready yet. */ + ps->post_wait = cycles; + post_wait_for_ACC (cpu, in_ACC40Si); + post_wait_for_ACC (cpu, ACC40Si_1); + post_wait_for_ACC (cpu, out_ACC40Sk); + + /* Restore the busy cycles of the registers we used. */ + acc = ps->acc_busy; + acc[in_ACC40Si] += busy_adjustment[0]; + if (ACC40Si_1 >= 0) + acc[ACC40Si_1] += busy_adjustment[1]; + acc[out_ACC40Sk] += busy_adjustment[2]; + + /* The latency of the output register will be at least the latency of the + other inputs. Once initiated, post-processing will take 1 cycle. */ + update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait + 1); + set_acc_use_is_media_p2 (cpu, out_ACC40Sk); + + return cycles; +} + +int +frvbf_model_fr400_u_media_2_acc_dual (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_ACC40Si, INT out_ACC40Sk) +{ + int cycles; + INT ACC40Si_1; + INT ACC40Si_2; + INT ACC40Si_3; + INT ACC40Sk_1; + FRV_PROFILE_STATE *ps; + int busy_adjustment[] = {0, 0, 0, 0, 0, 0}; + int *acc; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + return 0; + + /* The preprocessing can execute right away. */ + cycles = idesc->timing->units[unit_num].done; + + ACC40Si_1 = DUAL_REG (in_ACC40Si); + ACC40Si_2 = DUAL_REG (ACC40Si_1); + ACC40Si_3 = DUAL_REG (ACC40Si_2); + ACC40Sk_1 = DUAL_REG (out_ACC40Sk); + + ps = CPU_PROFILE_STATE (cpu); + /* The latency of the registers may be less than previously recorded, + depending on how they were used previously. + See Table 13-8 in the LSI. */ + if (acc_use_is_media_p2 (cpu, in_ACC40Si)) + { + busy_adjustment[0] = 1; + decrease_ACC_busy (cpu, in_ACC40Si, busy_adjustment[0]); + } + if (ACC40Si_1 >= 0 && acc_use_is_media_p2 (cpu, ACC40Si_1)) + { + busy_adjustment[1] = 1; + decrease_ACC_busy (cpu, ACC40Si_1, busy_adjustment[1]); + } + if (ACC40Si_2 >= 0 && acc_use_is_media_p2 (cpu, ACC40Si_2)) + { + busy_adjustment[2] = 1; + decrease_ACC_busy (cpu, ACC40Si_2, busy_adjustment[2]); + } + if (ACC40Si_3 >= 0 && acc_use_is_media_p2 (cpu, ACC40Si_3)) + { + busy_adjustment[3] = 1; + decrease_ACC_busy (cpu, ACC40Si_3, busy_adjustment[3]); + } + if (out_ACC40Sk != in_ACC40Si && out_ACC40Sk != ACC40Si_1 + && out_ACC40Sk != ACC40Si_2 && out_ACC40Sk != ACC40Si_3) + { + if (acc_use_is_media_p2 (cpu, out_ACC40Sk)) + { + busy_adjustment[4] = 1; + decrease_ACC_busy (cpu, out_ACC40Sk, busy_adjustment[4]); + } + } + if (ACC40Sk_1 != in_ACC40Si && ACC40Sk_1 != ACC40Si_1 + && ACC40Sk_1 != ACC40Si_2 && ACC40Sk_1 != ACC40Si_3) + { + if (acc_use_is_media_p2 (cpu, ACC40Sk_1)) + { + busy_adjustment[5] = 1; + decrease_ACC_busy (cpu, ACC40Sk_1, busy_adjustment[5]); + } + } + + /* The post processing must wait if there is a dependency on a register + which is not ready yet. */ + ps->post_wait = cycles; + post_wait_for_ACC (cpu, in_ACC40Si); + post_wait_for_ACC (cpu, ACC40Si_1); + post_wait_for_ACC (cpu, ACC40Si_2); + post_wait_for_ACC (cpu, ACC40Si_3); + post_wait_for_ACC (cpu, out_ACC40Sk); + post_wait_for_ACC (cpu, ACC40Sk_1); + + /* Restore the busy cycles of the registers we used. */ + acc = ps->acc_busy; + acc[in_ACC40Si] += busy_adjustment[0]; + if (ACC40Si_1 >= 0) + acc[ACC40Si_1] += busy_adjustment[1]; + if (ACC40Si_2 >= 0) + acc[ACC40Si_2] += busy_adjustment[2]; + if (ACC40Si_3 >= 0) + acc[ACC40Si_3] += busy_adjustment[3]; + acc[out_ACC40Sk] += busy_adjustment[4]; + if (ACC40Sk_1 >= 0) + acc[ACC40Sk_1] += busy_adjustment[5]; + + /* The latency of the output register will be at least the latency of the + other inputs. Once initiated, post-processing will take 1 cycle. */ + update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait + 1); + set_acc_use_is_media_p2 (cpu, out_ACC40Sk); + if (ACC40Sk_1 >= 0) + { + update_ACC_latency (cpu, ACC40Sk_1, ps->post_wait + 1); + set_acc_use_is_media_p2 (cpu, ACC40Sk_1); + } + + return cycles; +} + +int +frvbf_model_fr400_u_media_2_add_sub (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_ACC40Si, INT out_ACC40Sk) +{ + int cycles; + INT ACC40Si_1; + INT ACC40Sk_1; + FRV_PROFILE_STATE *ps; + int busy_adjustment[] = {0, 0, 0, 0}; + int *acc; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + return 0; + + /* The preprocessing can execute right away. */ + cycles = idesc->timing->units[unit_num].done; + + ACC40Si_1 = DUAL_REG (in_ACC40Si); + ACC40Sk_1 = DUAL_REG (out_ACC40Sk); + + ps = CPU_PROFILE_STATE (cpu); + /* The latency of the registers may be less than previously recorded, + depending on how they were used previously. + See Table 13-8 in the LSI. */ + if (acc_use_is_media_p2 (cpu, in_ACC40Si)) + { + busy_adjustment[0] = 1; + decrease_ACC_busy (cpu, in_ACC40Si, busy_adjustment[0]); + } + if (ACC40Si_1 >= 0 && acc_use_is_media_p2 (cpu, ACC40Si_1)) + { + busy_adjustment[1] = 1; + decrease_ACC_busy (cpu, ACC40Si_1, busy_adjustment[1]); + } + if (out_ACC40Sk != in_ACC40Si && out_ACC40Sk != ACC40Si_1) + { + if (acc_use_is_media_p2 (cpu, out_ACC40Sk)) + { + busy_adjustment[2] = 1; + decrease_ACC_busy (cpu, out_ACC40Sk, busy_adjustment[2]); + } + } + if (ACC40Sk_1 != in_ACC40Si && ACC40Sk_1 != ACC40Si_1) + { + if (acc_use_is_media_p2 (cpu, ACC40Sk_1)) + { + busy_adjustment[3] = 1; + decrease_ACC_busy (cpu, ACC40Sk_1, busy_adjustment[3]); + } + } + + /* The post processing must wait if there is a dependency on a register + which is not ready yet. */ + ps->post_wait = cycles; + post_wait_for_ACC (cpu, in_ACC40Si); + post_wait_for_ACC (cpu, ACC40Si_1); + post_wait_for_ACC (cpu, out_ACC40Sk); + post_wait_for_ACC (cpu, ACC40Sk_1); + + /* Restore the busy cycles of the registers we used. */ + acc = ps->acc_busy; + acc[in_ACC40Si] += busy_adjustment[0]; + if (ACC40Si_1 >= 0) + acc[ACC40Si_1] += busy_adjustment[1]; + acc[out_ACC40Sk] += busy_adjustment[2]; + if (ACC40Sk_1 >= 0) + acc[ACC40Sk_1] += busy_adjustment[3]; + + /* The latency of the output register will be at least the latency of the + other inputs. Once initiated, post-processing will take 1 cycle. */ + update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait + 1); + set_acc_use_is_media_p2 (cpu, out_ACC40Sk); + if (ACC40Sk_1 >= 0) + { + update_ACC_latency (cpu, ACC40Sk_1, ps->post_wait + 1); + set_acc_use_is_media_p2 (cpu, ACC40Sk_1); + } + + return cycles; +} + +int +frvbf_model_fr400_u_media_2_add_sub_dual (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_ACC40Si, INT out_ACC40Sk) +{ + int cycles; + INT ACC40Si_1; + INT ACC40Si_2; + INT ACC40Si_3; + INT ACC40Sk_1; + INT ACC40Sk_2; + INT ACC40Sk_3; + FRV_PROFILE_STATE *ps; + int busy_adjustment[] = {0, 0, 0, 0, 0, 0, 0, 0}; + int *acc; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + return 0; + + /* The preprocessing can execute right away. */ + cycles = idesc->timing->units[unit_num].done; + + ACC40Si_1 = DUAL_REG (in_ACC40Si); + ACC40Si_2 = DUAL_REG (ACC40Si_1); + ACC40Si_3 = DUAL_REG (ACC40Si_2); + ACC40Sk_1 = DUAL_REG (out_ACC40Sk); + ACC40Sk_2 = DUAL_REG (ACC40Sk_1); + ACC40Sk_3 = DUAL_REG (ACC40Sk_2); + + ps = CPU_PROFILE_STATE (cpu); + /* The latency of the registers may be less than previously recorded, + depending on how they were used previously. + See Table 13-8 in the LSI. */ + if (acc_use_is_media_p2 (cpu, in_ACC40Si)) + { + busy_adjustment[0] = 1; + decrease_ACC_busy (cpu, in_ACC40Si, busy_adjustment[0]); + } + if (ACC40Si_1 >= 0 && acc_use_is_media_p2 (cpu, ACC40Si_1)) + { + busy_adjustment[1] = 1; + decrease_ACC_busy (cpu, ACC40Si_1, busy_adjustment[1]); + } + if (ACC40Si_2 >= 0 && acc_use_is_media_p2 (cpu, ACC40Si_2)) + { + busy_adjustment[2] = 1; + decrease_ACC_busy (cpu, ACC40Si_2, busy_adjustment[2]); + } + if (ACC40Si_3 >= 0 && acc_use_is_media_p2 (cpu, ACC40Si_3)) + { + busy_adjustment[3] = 1; + decrease_ACC_busy (cpu, ACC40Si_3, busy_adjustment[3]); + } + if (out_ACC40Sk != in_ACC40Si && out_ACC40Sk != ACC40Si_1 + && out_ACC40Sk != ACC40Si_2 && out_ACC40Sk != ACC40Si_3) + { + if (acc_use_is_media_p2 (cpu, out_ACC40Sk)) + { + busy_adjustment[4] = 1; + decrease_ACC_busy (cpu, out_ACC40Sk, busy_adjustment[4]); + } + } + if (ACC40Sk_1 != in_ACC40Si && ACC40Sk_1 != ACC40Si_1 + && ACC40Sk_1 != ACC40Si_2 && ACC40Sk_1 != ACC40Si_3) + { + if (acc_use_is_media_p2 (cpu, ACC40Sk_1)) + { + busy_adjustment[5] = 1; + decrease_ACC_busy (cpu, ACC40Sk_1, busy_adjustment[5]); + } + } + if (ACC40Sk_2 != in_ACC40Si && ACC40Sk_2 != ACC40Si_1 + && ACC40Sk_2 != ACC40Si_2 && ACC40Sk_2 != ACC40Si_3) + { + if (acc_use_is_media_p2 (cpu, ACC40Sk_2)) + { + busy_adjustment[6] = 1; + decrease_ACC_busy (cpu, ACC40Sk_2, busy_adjustment[6]); + } + } + if (ACC40Sk_3 != in_ACC40Si && ACC40Sk_3 != ACC40Si_1 + && ACC40Sk_3 != ACC40Si_2 && ACC40Sk_3 != ACC40Si_3) + { + if (acc_use_is_media_p2 (cpu, ACC40Sk_3)) + { + busy_adjustment[7] = 1; + decrease_ACC_busy (cpu, ACC40Sk_3, busy_adjustment[7]); + } + } + + /* The post processing must wait if there is a dependency on a register + which is not ready yet. */ + ps->post_wait = cycles; + post_wait_for_ACC (cpu, in_ACC40Si); + post_wait_for_ACC (cpu, ACC40Si_1); + post_wait_for_ACC (cpu, ACC40Si_2); + post_wait_for_ACC (cpu, ACC40Si_3); + post_wait_for_ACC (cpu, out_ACC40Sk); + post_wait_for_ACC (cpu, ACC40Sk_1); + post_wait_for_ACC (cpu, ACC40Sk_2); + post_wait_for_ACC (cpu, ACC40Sk_3); + + /* Restore the busy cycles of the registers we used. */ + acc = ps->acc_busy; + acc[in_ACC40Si] += busy_adjustment[0]; + if (ACC40Si_1 >= 0) + acc[ACC40Si_1] += busy_adjustment[1]; + if (ACC40Si_2 >= 0) + acc[ACC40Si_2] += busy_adjustment[2]; + if (ACC40Si_3 >= 0) + acc[ACC40Si_3] += busy_adjustment[3]; + acc[out_ACC40Sk] += busy_adjustment[4]; + if (ACC40Sk_1 >= 0) + acc[ACC40Sk_1] += busy_adjustment[5]; + if (ACC40Sk_2 >= 0) + acc[ACC40Sk_2] += busy_adjustment[6]; + if (ACC40Sk_3 >= 0) + acc[ACC40Sk_3] += busy_adjustment[7]; + + /* The latency of the output register will be at least the latency of the + other inputs. Once initiated, post-processing will take 1 cycle. */ + update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait + 1); + set_acc_use_is_media_p2 (cpu, out_ACC40Sk); + if (ACC40Sk_1 >= 0) + { + update_ACC_latency (cpu, ACC40Sk_1, ps->post_wait + 1); + set_acc_use_is_media_p2 (cpu, ACC40Sk_1); + } + if (ACC40Sk_2 >= 0) + { + update_ACC_latency (cpu, ACC40Sk_2, ps->post_wait + 1); + set_acc_use_is_media_p2 (cpu, ACC40Sk_2); + } + if (ACC40Sk_3 >= 0) + { + update_ACC_latency (cpu, ACC40Sk_3, ps->post_wait + 1); + set_acc_use_is_media_p2 (cpu, ACC40Sk_3); + } + + return cycles; +} + +int +frvbf_model_fr400_u_media_3 (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_FRi, INT in_FRj, + INT out_FRk) +{ + /* Modelling is the same as media unit 1. */ + return frvbf_model_fr400_u_media_1 (cpu, idesc, unit_num, referenced, + in_FRi, in_FRj, out_FRk); +} + +int +frvbf_model_fr400_u_media_3_dual (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_FRi, INT out_FRk) +{ + int cycles; + INT dual_FRi; + FRV_PROFILE_STATE *ps; + int busy_adjustment[] = {0, 0}; + int *fr; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + return 0; + + /* The preprocessing can execute right away. */ + cycles = idesc->timing->units[unit_num].done; + + ps = CPU_PROFILE_STATE (cpu); + dual_FRi = DUAL_REG (in_FRi); + + /* The latency of the registers may be less than previously recorded, + depending on how they were used previously. + See Table 13-8 in the LSI. */ + if (use_is_fp_load (cpu, in_FRi)) + { + busy_adjustment[0] = 1; + decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]); + } + else + enforce_full_fr_latency (cpu, in_FRi); + if (dual_FRi >= 0 && use_is_fp_load (cpu, dual_FRi)) + { + busy_adjustment[1] = 1; + decrease_FR_busy (cpu, dual_FRi, busy_adjustment[1]); + } + else + enforce_full_fr_latency (cpu, dual_FRi); + + /* The post processing must wait if there is a dependency on a FR + which is not ready yet. */ + ps->post_wait = cycles; + post_wait_for_FR (cpu, in_FRi); + post_wait_for_FR (cpu, dual_FRi); + post_wait_for_FR (cpu, out_FRk); + + /* Restore the busy cycles of the registers we used. */ + fr = ps->fr_busy; + fr[in_FRi] += busy_adjustment[0]; + if (dual_FRi >= 0) + fr[dual_FRi] += busy_adjustment[1]; + + /* The latency of the output register will be at least the latency of the + other inputs. */ + update_FR_latency (cpu, out_FRk, ps->post_wait); + + /* Once initiated, post-processing has no latency. */ + update_FR_ptime (cpu, out_FRk, 0); + + return cycles; +} + +int +frvbf_model_fr400_u_media_3_quad (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_FRi, INT in_FRj, + INT out_FRk) +{ + /* Modelling is the same as media unit 1. */ + return frvbf_model_fr400_u_media_1_quad (cpu, idesc, unit_num, referenced, + in_FRi, in_FRj, out_FRk); +} + +int +frvbf_model_fr400_u_media_4 (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_ACC40Si, INT in_FRj, + INT out_ACC40Sk, INT out_FRk) +{ + int cycles; + FRV_PROFILE_STATE *ps; + const CGEN_INSN *insn; + int busy_adjustment[] = {0}; + int *fr; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + return 0; + + /* The preprocessing can execute right away. */ + cycles = idesc->timing->units[unit_num].done; + + ps = CPU_PROFILE_STATE (cpu); + insn = idesc->idata; + + /* The latency of the registers may be less than previously recorded, + depending on how they were used previously. + See Table 13-8 in the LSI. */ + if (in_FRj >= 0) + { + if (use_is_fp_load (cpu, in_FRj)) + { + busy_adjustment[0] = 1; + decrease_FR_busy (cpu, in_FRj, busy_adjustment[0]); + } + else + enforce_full_fr_latency (cpu, in_FRj); + } + + /* The post processing must wait if there is a dependency on a FR + which is not ready yet. */ + ps->post_wait = cycles; + post_wait_for_ACC (cpu, in_ACC40Si); + post_wait_for_ACC (cpu, out_ACC40Sk); + post_wait_for_FR (cpu, in_FRj); + post_wait_for_FR (cpu, out_FRk); + + /* Restore the busy cycles of the registers we used. */ + fr = ps->fr_busy; + + /* The latency of the output register will be at least the latency of the + other inputs. Once initiated, post-processing will take 1 cycle. */ + if (out_FRk >= 0) + { + update_FR_latency (cpu, out_FRk, ps->post_wait); + update_FR_ptime (cpu, out_FRk, 1); + /* Mark this use of the register as media unit 4. */ + set_use_is_media_p4 (cpu, out_FRk); + } + else if (out_ACC40Sk >= 0) + { + update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait); + update_ACC_ptime (cpu, out_ACC40Sk, 1); + /* Mark this use of the register as media unit 4. */ + set_acc_use_is_media_p4 (cpu, out_ACC40Sk); + } + + return cycles; +} + +int +frvbf_model_fr400_u_media_4_accg (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_ACCGi, INT in_FRinti, + INT out_ACCGk, INT out_FRintk) +{ + /* Modelling is the same as media-4 unit except use accumulator guards + as input instead of accumulators. */ + return frvbf_model_fr400_u_media_4 (cpu, idesc, unit_num, referenced, + in_ACCGi, in_FRinti, + out_ACCGk, out_FRintk); +} + +int +frvbf_model_fr400_u_media_4_acc_dual (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_ACC40Si, INT out_FRk) +{ + int cycles; + FRV_PROFILE_STATE *ps; + const CGEN_INSN *insn; + INT ACC40Si_1; + INT FRk_1; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + return 0; + + /* The preprocessing can execute right away. */ + cycles = idesc->timing->units[unit_num].done; + + ps = CPU_PROFILE_STATE (cpu); + ACC40Si_1 = DUAL_REG (in_ACC40Si); + FRk_1 = DUAL_REG (out_FRk); + + insn = idesc->idata; + + /* The post processing must wait if there is a dependency on a FR + which is not ready yet. */ + ps->post_wait = cycles; + post_wait_for_ACC (cpu, in_ACC40Si); + post_wait_for_ACC (cpu, ACC40Si_1); + post_wait_for_FR (cpu, out_FRk); + post_wait_for_FR (cpu, FRk_1); + + /* The latency of the output register will be at least the latency of the + other inputs. Once initiated, post-processing will take 1 cycle. */ + if (out_FRk >= 0) + { + update_FR_latency (cpu, out_FRk, ps->post_wait); + update_FR_ptime (cpu, out_FRk, 1); + /* Mark this use of the register as media unit 4. */ + set_use_is_media_p4 (cpu, out_FRk); + } + if (FRk_1 >= 0) + { + update_FR_latency (cpu, FRk_1, ps->post_wait); + update_FR_ptime (cpu, FRk_1, 1); + /* Mark this use of the register as media unit 4. */ + set_use_is_media_p4 (cpu, FRk_1); + } + + return cycles; +} + +int +frvbf_model_fr400_u_media_6 (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_FRi, INT out_FRk) +{ + int cycles; + FRV_PROFILE_STATE *ps; + const CGEN_INSN *insn; + int busy_adjustment[] = {0}; + int *fr; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + return 0; + + /* The preprocessing can execute right away. */ + cycles = idesc->timing->units[unit_num].done; + + ps = CPU_PROFILE_STATE (cpu); + insn = idesc->idata; + + /* The latency of the registers may be less than previously recorded, + depending on how they were used previously. + See Table 13-8 in the LSI. */ + if (in_FRi >= 0) + { + if (use_is_fp_load (cpu, in_FRi)) + { + busy_adjustment[0] = 1; + decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]); + } + else + enforce_full_fr_latency (cpu, in_FRi); + } + + /* The post processing must wait if there is a dependency on a FR + which is not ready yet. */ + ps->post_wait = cycles; + post_wait_for_FR (cpu, in_FRi); + post_wait_for_FR (cpu, out_FRk); + + /* Restore the busy cycles of the registers we used. */ + fr = ps->fr_busy; + if (in_FRi >= 0) + fr[in_FRi] += busy_adjustment[0]; + + /* The latency of the output register will be at least the latency of the + other inputs. Once initiated, post-processing will take 1 cycle. */ + if (out_FRk >= 0) + { + update_FR_latency (cpu, out_FRk, ps->post_wait); + update_FR_ptime (cpu, out_FRk, 1); + + /* Mark this use of the register as media unit 1. */ + set_use_is_media_p6 (cpu, out_FRk); + } + + return cycles; +} + +int +frvbf_model_fr400_u_media_7 (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_FRinti, INT in_FRintj, + INT out_FCCk) +{ + int cycles; + FRV_PROFILE_STATE *ps; + int busy_adjustment[] = {0, 0}; + int *fr; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + return 0; + + /* The preprocessing can execute right away. */ + cycles = idesc->timing->units[unit_num].done; + + /* The post processing must wait if there is a dependency on a FR + which is not ready yet. */ + ps = CPU_PROFILE_STATE (cpu); + + /* The latency of the registers may be less than previously recorded, + depending on how they were used previously. + See Table 13-8 in the LSI. */ + if (in_FRinti >= 0) + { + if (use_is_fp_load (cpu, in_FRinti)) + { + busy_adjustment[0] = 1; + decrease_FR_busy (cpu, in_FRinti, busy_adjustment[0]); + } + else + enforce_full_fr_latency (cpu, in_FRinti); + } + if (in_FRintj >= 0 && in_FRintj != in_FRinti) + { + if (use_is_fp_load (cpu, in_FRintj)) + { + busy_adjustment[1] = 1; + decrease_FR_busy (cpu, in_FRintj, busy_adjustment[1]); + } + else + enforce_full_fr_latency (cpu, in_FRintj); + } + + ps->post_wait = cycles; + post_wait_for_FR (cpu, in_FRinti); + post_wait_for_FR (cpu, in_FRintj); + post_wait_for_CCR (cpu, out_FCCk); + + /* Restore the busy cycles of the registers we used. */ + fr = ps->fr_busy; + if (in_FRinti >= 0) + fr[in_FRinti] += busy_adjustment[0]; + if (in_FRintj >= 0) + fr[in_FRintj] += busy_adjustment[1]; + + /* The latency of FCCi_2 will be the latency of the other inputs plus 1 + cycle. */ + update_CCR_latency (cpu, out_FCCk, ps->post_wait + 1); + + return cycles; +} + +int +frvbf_model_fr400_u_media_dual_expand (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_FRi, + INT out_FRk) +{ + /* Insns using this unit are media-3 class insns, with a dual FRk output. */ + int cycles; + INT dual_FRk; + FRV_PROFILE_STATE *ps; + int busy_adjustment[] = {0}; + int *fr; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + return 0; + + /* The preprocessing can execute right away. */ + cycles = idesc->timing->units[unit_num].done; + + /* If the previous use of the registers was a media op, + then their latency will be less than previously recorded. + See Table 13-13 in the LSI. */ + dual_FRk = DUAL_REG (out_FRk); + ps = CPU_PROFILE_STATE (cpu); + if (use_is_fp_load (cpu, in_FRi)) + { + busy_adjustment[0] = 1; + decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]); + } + else + enforce_full_fr_latency (cpu, in_FRi); + + /* The post processing must wait if there is a dependency on a FR + which is not ready yet. */ + ps->post_wait = cycles; + post_wait_for_FR (cpu, in_FRi); + post_wait_for_FR (cpu, out_FRk); + post_wait_for_FR (cpu, dual_FRk); + + /* Restore the busy cycles of the registers we used. */ + fr = ps->fr_busy; + fr[in_FRi] += busy_adjustment[0]; + + /* The latency of the output register will be at least the latency of the + other inputs. Once initiated, post-processing has no latency. */ + update_FR_latency (cpu, out_FRk, ps->post_wait); + update_FR_ptime (cpu, out_FRk, 0); + + if (dual_FRk >= 0) + { + update_FR_latency (cpu, dual_FRk, ps->post_wait); + update_FR_ptime (cpu, dual_FRk, 0); + } + + return cycles; +} + +int +frvbf_model_fr400_u_media_dual_htob (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_FRj, + INT out_FRk) +{ + /* Insns using this unit are media-3 class insns, with a dual FRj input. */ + int cycles; + INT dual_FRj; + FRV_PROFILE_STATE *ps; + int busy_adjustment[] = {0, 0}; + int *fr; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + return 0; + + /* The preprocessing can execute right away. */ + cycles = idesc->timing->units[unit_num].done; + + /* If the previous use of the registers was a media op, + then their latency will be less than previously recorded. + See Table 13-13 in the LSI. */ + dual_FRj = DUAL_REG (in_FRj); + ps = CPU_PROFILE_STATE (cpu); + if (use_is_fp_load (cpu, in_FRj)) + { + busy_adjustment[0] = 1; + decrease_FR_busy (cpu, in_FRj, busy_adjustment[0]); + } + else + enforce_full_fr_latency (cpu, in_FRj); + if (dual_FRj >= 0) + { + if (use_is_fp_load (cpu, dual_FRj)) + { + busy_adjustment[1] = 1; + decrease_FR_busy (cpu, dual_FRj, busy_adjustment[1]); + } + else + enforce_full_fr_latency (cpu, dual_FRj); + } + + /* The post processing must wait if there is a dependency on a FR + which is not ready yet. */ + ps->post_wait = cycles; + post_wait_for_FR (cpu, in_FRj); + post_wait_for_FR (cpu, dual_FRj); + post_wait_for_FR (cpu, out_FRk); + + /* Restore the busy cycles of the registers we used. */ + fr = ps->fr_busy; + fr[in_FRj] += busy_adjustment[0]; + if (dual_FRj >= 0) + fr[dual_FRj] += busy_adjustment[1]; + + /* The latency of the output register will be at least the latency of the + other inputs. */ + update_FR_latency (cpu, out_FRk, ps->post_wait); + + /* Once initiated, post-processing has no latency. */ + update_FR_ptime (cpu, out_FRk, 0); + + return cycles; +} + +int +frvbf_model_fr400_u_ici (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRi, INT in_GRj) +{ + /* Modelling for this unit is the same as for fr500. */ + return frvbf_model_fr500_u_ici (cpu, idesc, unit_num, referenced, + in_GRi, in_GRj); +} + +int +frvbf_model_fr400_u_dci (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRi, INT in_GRj) +{ + /* Modelling for this unit is the same as for fr500. */ + return frvbf_model_fr500_u_dci (cpu, idesc, unit_num, referenced, + in_GRi, in_GRj); +} + +int +frvbf_model_fr400_u_dcf (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRi, INT in_GRj) +{ + /* Modelling for this unit is the same as for fr500. */ + return frvbf_model_fr500_u_dcf (cpu, idesc, unit_num, referenced, + in_GRi, in_GRj); +} + +int +frvbf_model_fr400_u_icpl (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRi, INT in_GRj) +{ + /* Modelling for this unit is the same as for fr500. */ + return frvbf_model_fr500_u_icpl (cpu, idesc, unit_num, referenced, + in_GRi, in_GRj); +} + +int +frvbf_model_fr400_u_dcpl (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRi, INT in_GRj) +{ + /* Modelling for this unit is the same as for fr500. */ + return frvbf_model_fr500_u_dcpl (cpu, idesc, unit_num, referenced, + in_GRi, in_GRj); +} + +int +frvbf_model_fr400_u_icul (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRi, INT in_GRj) +{ + /* Modelling for this unit is the same as for fr500. */ + return frvbf_model_fr500_u_icul (cpu, idesc, unit_num, referenced, + in_GRi, in_GRj); +} + +int +frvbf_model_fr400_u_dcul (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRi, INT in_GRj) +{ + /* Modelling for this unit is the same as for fr500. */ + return frvbf_model_fr500_u_dcul (cpu, idesc, unit_num, referenced, + in_GRi, in_GRj); +} + +int +frvbf_model_fr400_u_barrier (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced) +{ + /* Modelling for this unit is the same as for fr500. */ + return frvbf_model_fr500_u_barrier (cpu, idesc, unit_num, referenced); +} + +int +frvbf_model_fr400_u_membar (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced) +{ + /* Modelling for this unit is the same as for fr500. */ + return frvbf_model_fr500_u_membar (cpu, idesc, unit_num, referenced); +} + +#endif /* WITH_PROFILE_MODEL_P */ diff --git a/sim/frv/profile-fr400.h b/sim/frv/profile-fr400.h new file mode 100644 index 0000000..cee8cf1 --- /dev/null +++ b/sim/frv/profile-fr400.h @@ -0,0 +1,31 @@ +/* Profiling definitions for the fr400 model of the FRV simulator + Copyright (C) 1998, 1999, 2000, 2001 Free Software Foundation, Inc. + Contributed by Red Hat. + +This file is part of the GNU Simulators. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef PROFILE_FR400_H +#define PROFILE_FR400_H + +void fr400_model_insn_before (SIM_CPU *, int); +void fr400_model_insn_after (SIM_CPU *, int, int); + +void fr400_reset_gr_flags (SIM_CPU *, INT); +void fr400_reset_fr_flags (SIM_CPU *, INT); +void fr400_reset_acc_flags (SIM_CPU *, INT); + +#endif /* PROFILE_FR400_H */ diff --git a/sim/frv/profile-fr500.c b/sim/frv/profile-fr500.c new file mode 100644 index 0000000..610927c --- /dev/null +++ b/sim/frv/profile-fr500.c @@ -0,0 +1,3205 @@ +/* frv simulator fr500 dependent profiling code. + + Copyright (C) 1998, 1999, 2000, 2001, 2003 Free Software Foundation, Inc. + Contributed by Red Hat + +This file is part of the GNU simulators. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +*/ +#define WANT_CPU +#define WANT_CPU_FRVBF + +#include "sim-main.h" +#include "bfd.h" + +#if WITH_PROFILE_MODEL_P + +#include "profile.h" +#include "profile-fr500.h" + +/* Initialize cycle counting for an insn. + FIRST_P is non-zero if this is the first insn in a set of parallel + insns. */ +void +fr500_model_insn_before (SIM_CPU *cpu, int first_p) +{ + if (first_p) + { + MODEL_FR500_DATA *d = CPU_MODEL_DATA (cpu); + FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu); + ps->cur_gr_complex = ps->prev_gr_complex; + d->cur_fpop = d->prev_fpop; + d->cur_media = d->prev_media; + d->cur_cc_complex = d->prev_cc_complex; + } +} + +/* Record the cycles computed for an insn. + LAST_P is non-zero if this is the last insn in a set of parallel insns, + and we update the total cycle count. + CYCLES is the cycle count of the insn. */ +void +fr500_model_insn_after (SIM_CPU *cpu, int last_p, int cycles) +{ + if (last_p) + { + MODEL_FR500_DATA *d = CPU_MODEL_DATA (cpu); + FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu); + ps->prev_gr_complex = ps->cur_gr_complex; + d->prev_fpop = d->cur_fpop; + d->prev_media = d->cur_media; + d->prev_cc_complex = d->cur_cc_complex; + } +} + +static void +set_use_is_fpop (SIM_CPU *cpu, INT fr) +{ + MODEL_FR500_DATA *d = CPU_MODEL_DATA (cpu); + fr500_reset_fr_flags (cpu, (fr)); + d->cur_fpop |= (((DI)1) << (fr)); +} + +static void +set_use_not_fpop (SIM_CPU *cpu, INT fr) +{ + MODEL_FR500_DATA *d = CPU_MODEL_DATA (cpu); + d->cur_fpop &= ~(((DI)1) << (fr)); +} + +static int +use_is_fpop (SIM_CPU *cpu, INT fr) +{ + MODEL_FR500_DATA *d = CPU_MODEL_DATA (cpu); + return d->prev_fpop & (((DI)1) << (fr)); +} + +static void +set_use_is_media ( SIM_CPU *cpu, INT fr) +{ + MODEL_FR500_DATA *d = CPU_MODEL_DATA (cpu); + fr500_reset_fr_flags (cpu, (fr)); + d->cur_media |= (((DI)1) << (fr)); +} + +static void +set_use_not_media (SIM_CPU *cpu, INT fr) +{ + MODEL_FR500_DATA *d = CPU_MODEL_DATA (cpu); + d->cur_media &= ~(((DI)1) << (fr)); +} + +static int +use_is_media (SIM_CPU *cpu, INT fr) +{ + MODEL_FR500_DATA *d = CPU_MODEL_DATA (cpu); + return d->prev_media & (((DI)1) << (fr)); +} + +static void +set_use_is_cc_complex (SIM_CPU *cpu, INT cc) +{ + MODEL_FR500_DATA *d = CPU_MODEL_DATA (cpu); + fr500_reset_cc_flags (cpu, cc); + d->cur_cc_complex |= (((DI)1) << (cc)); +} + +static void +set_use_not_cc_complex (SIM_CPU *cpu, INT cc) +{ + MODEL_FR500_DATA *d = CPU_MODEL_DATA (cpu); + d->cur_cc_complex &= ~(((DI)1) << (cc)); +} + +static int +use_is_cc_complex (SIM_CPU *cpu, INT cc) +{ + MODEL_FR500_DATA *d = CPU_MODEL_DATA (cpu); + return d->prev_cc_complex & (((DI)1) << (cc)); +} + +void +fr500_reset_fr_flags (SIM_CPU *cpu, INT fr) +{ + set_use_not_fpop (cpu, fr); + set_use_not_media (cpu, fr); +} + +void +fr500_reset_cc_flags (SIM_CPU *cpu, INT cc) +{ + set_use_not_cc_complex (cpu, cc); +} + +/* Latency of floating point registers may be less than recorded when followed + by another floating point insn. */ +static void +adjust_float_register_busy (SIM_CPU *cpu, INT in_FRi, INT in_FRj, INT out_FRk, + int cycles) +{ + /* If the registers were previously used in a floating point op, + then their latency will be less than previously recorded. + See Table 13-13 in the LSI. */ + if (in_FRi >= 0) + if (use_is_fpop (cpu, in_FRi)) + decrease_FR_busy (cpu, in_FRi, cycles); + else + enforce_full_fr_latency (cpu, in_FRi); + + if (in_FRj >= 0 && in_FRj != in_FRi) + if (use_is_fpop (cpu, in_FRj)) + decrease_FR_busy (cpu, in_FRj, cycles); + else + enforce_full_fr_latency (cpu, in_FRj); + + if (out_FRk >= 0 && out_FRk != in_FRi && out_FRk != in_FRj) + if (use_is_fpop (cpu, out_FRk)) + decrease_FR_busy (cpu, out_FRk, cycles); + else + enforce_full_fr_latency (cpu, out_FRk); +} + +/* Latency of floating point registers may be less than recorded when followed + by another floating point insn. */ +static void +adjust_double_register_busy (SIM_CPU *cpu, INT in_FRi, INT in_FRj, INT out_FRk, + int cycles) +{ + /* If the registers were previously used in a floating point op, + then their latency will be less than previously recorded. + See Table 13-13 in the LSI. */ + adjust_float_register_busy (cpu, in_FRi, in_FRj, out_FRk, cycles); + if (in_FRi >= 0) ++in_FRi; + if (in_FRj >= 0) ++in_FRj; + if (out_FRk >= 0) ++out_FRk; + adjust_float_register_busy (cpu, in_FRi, in_FRj, out_FRk, cycles); +} + +/* Latency of floating point registers is less than recorded when followed + by another floating point insn. */ +static void +restore_float_register_busy (SIM_CPU *cpu, INT in_FRi, INT in_FRj, INT out_FRk, + int cycles) +{ + /* If the registers were previously used in a floating point op, + then their latency will be less than previously recorded. + See Table 13-13 in the LSI. */ + if (in_FRi >= 0 && use_is_fpop (cpu, in_FRi)) + increase_FR_busy (cpu, in_FRi, cycles); + if (in_FRj != in_FRi && use_is_fpop (cpu, in_FRj)) + increase_FR_busy (cpu, in_FRj, cycles); + if (out_FRk != in_FRi && out_FRk != in_FRj && use_is_fpop (cpu, out_FRk)) + increase_FR_busy (cpu, out_FRk, cycles); +} + +/* Latency of floating point registers is less than recorded when followed + by another floating point insn. */ +static void +restore_double_register_busy (SIM_CPU *cpu, INT in_FRi, INT in_FRj, INT out_FRk, + int cycles) +{ + /* If the registers were previously used in a floating point op, + then their latency will be less than previously recorded. + See Table 13-13 in the LSI. */ + restore_float_register_busy (cpu, in_FRi, in_FRj, out_FRk, cycles); + if (in_FRi >= 0) ++in_FRi; + if (in_FRj >= 0) ++in_FRj; + if (out_FRk >= 0) ++out_FRk; + restore_float_register_busy (cpu, in_FRi, in_FRj, out_FRk, cycles); +} + +int +frvbf_model_fr500_u_exec (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced) +{ + return idesc->timing->units[unit_num].done; +} + +int +frvbf_model_fr500_u_integer (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRi, INT in_GRj, INT out_GRk, + INT out_ICCi_1) +{ + int cycles; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + { + /* icc0-icc4 are the upper 4 fields of the CCR. */ + if (out_ICCi_1 >= 0) + out_ICCi_1 += 4; + + /* The entire VLIW insn must wait if there is a dependency on a register + which is not ready yet. + The latency of the registers may be less than previously recorded, + depending on how they were used previously. + See Table 13-8 in the LSI. */ + if (in_GRi != out_GRk && in_GRi >= 0) + { + if (use_is_gr_complex (cpu, in_GRi)) + decrease_GR_busy (cpu, in_GRi, 1); + } + if (in_GRj != out_GRk && in_GRj != in_GRi && in_GRj >= 0) + { + if (use_is_gr_complex (cpu, in_GRj)) + decrease_GR_busy (cpu, in_GRj, 1); + } + vliw_wait_for_GR (cpu, in_GRi); + vliw_wait_for_GR (cpu, in_GRj); + vliw_wait_for_GR (cpu, out_GRk); + vliw_wait_for_CCR (cpu, out_ICCi_1); + handle_resource_wait (cpu); + load_wait_for_GR (cpu, in_GRi); + load_wait_for_GR (cpu, in_GRj); + load_wait_for_GR (cpu, out_GRk); + trace_vliw_wait_cycles (cpu); + return 0; + } + + /* GRk is available immediately to the next VLIW insn as is ICCi_1. */ + cycles = idesc->timing->units[unit_num].done; + return cycles; +} + +int +frvbf_model_fr500_u_imul (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRi, INT in_GRj, INT out_GRk, INT out_ICCi_1) +{ + int cycles; + /* icc0-icc4 are the upper 4 fields of the CCR. */ + if (out_ICCi_1 >= 0) + out_ICCi_1 += 4; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + { + /* The entire VLIW insn must wait if there is a dependency on a register + which is not ready yet. + The latency of the registers may be less than previously recorded, + depending on how they were used previously. + See Table 13-8 in the LSI. */ + if (in_GRi != out_GRk && in_GRi >= 0) + { + if (use_is_gr_complex (cpu, in_GRi)) + decrease_GR_busy (cpu, in_GRi, 1); + } + if (in_GRj != out_GRk && in_GRj != in_GRi && in_GRj >= 0) + { + if (use_is_gr_complex (cpu, in_GRj)) + decrease_GR_busy (cpu, in_GRj, 1); + } + vliw_wait_for_GR (cpu, in_GRi); + vliw_wait_for_GR (cpu, in_GRj); + vliw_wait_for_GRdouble (cpu, out_GRk); + vliw_wait_for_CCR (cpu, out_ICCi_1); + handle_resource_wait (cpu); + load_wait_for_GR (cpu, in_GRi); + load_wait_for_GR (cpu, in_GRj); + load_wait_for_GRdouble (cpu, out_GRk); + trace_vliw_wait_cycles (cpu); + return 0; + } + + /* GRk has a latency of 2 cycles. */ + cycles = idesc->timing->units[unit_num].done; + update_GRdouble_latency (cpu, out_GRk, cycles + 2); + set_use_is_gr_complex (cpu, out_GRk); + set_use_is_gr_complex (cpu, out_GRk + 1); + + /* ICCi_1 has a latency of 1 cycle. */ + update_CCR_latency (cpu, out_ICCi_1, cycles + 1); + + return cycles; +} + +int +frvbf_model_fr500_u_idiv (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRi, INT in_GRj, INT out_GRk, INT out_ICCi_1) +{ + int cycles; + FRV_VLIW *vliw; + int slot; + + /* icc0-icc4 are the upper 4 fields of the CCR. */ + if (out_ICCi_1 >= 0) + out_ICCi_1 += 4; + + vliw = CPU_VLIW (cpu); + slot = vliw->next_slot - 1; + slot = (*vliw->current_vliw)[slot] - UNIT_I0; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + { + /* The entire VLIW insn must wait if there is a dependency on a register + which is not ready yet. + The latency of the registers may be less than previously recorded, + depending on how they were used previously. + See Table 13-8 in the LSI. */ + if (in_GRi != out_GRk && in_GRi >= 0) + { + if (use_is_gr_complex (cpu, in_GRi)) + decrease_GR_busy (cpu, in_GRi, 1); + } + if (in_GRj != out_GRk && in_GRj != in_GRi && in_GRj >= 0) + { + if (use_is_gr_complex (cpu, in_GRj)) + decrease_GR_busy (cpu, in_GRj, 1); + } + vliw_wait_for_GR (cpu, in_GRi); + vliw_wait_for_GR (cpu, in_GRj); + vliw_wait_for_GR (cpu, out_GRk); + vliw_wait_for_CCR (cpu, out_ICCi_1); + vliw_wait_for_idiv_resource (cpu, slot); + handle_resource_wait (cpu); + load_wait_for_GR (cpu, in_GRi); + load_wait_for_GR (cpu, in_GRj); + load_wait_for_GR (cpu, out_GRk); + trace_vliw_wait_cycles (cpu); + return 0; + } + + /* GRk has a latency of 19 cycles! */ + cycles = idesc->timing->units[unit_num].done; + update_GR_latency (cpu, out_GRk, cycles + 19); + set_use_is_gr_complex (cpu, out_GRk); + + /* ICCi_1 has a latency of 19 cycles. */ + update_CCR_latency (cpu, out_ICCi_1, cycles + 19); + set_use_is_cc_complex (cpu, out_ICCi_1); + + if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) + { + /* GNER has a latency of 18 cycles. */ + update_SPR_latency (cpu, GNER_FOR_GR (out_GRk), cycles + 18); + } + + /* the idiv resource has a latency of 18 cycles! */ + update_idiv_resource_latency (cpu, slot, cycles + 18); + + return cycles; +} + +int +frvbf_model_fr500_u_branch (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRi, INT in_GRj, + INT in_ICCi_2, INT in_FCCi_2) +{ + int cycles; + FRV_PROFILE_STATE *ps; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + { + /* icc0-icc4 are the upper 4 fields of the CCR. */ + if (in_ICCi_2 >= 0) + in_ICCi_2 += 4; + + /* The entire VLIW insn must wait if there is a dependency on a register + which is not ready yet. + The latency of the registers may be less than previously recorded, + depending on how they were used previously. + See Table 13-8 in the LSI. */ + if (in_GRi >= 0) + { + if (use_is_gr_complex (cpu, in_GRi)) + decrease_GR_busy (cpu, in_GRi, 1); + } + if (in_GRj != in_GRi && in_GRj >= 0) + { + if (use_is_gr_complex (cpu, in_GRj)) + decrease_GR_busy (cpu, in_GRj, 1); + } + vliw_wait_for_GR (cpu, in_GRi); + vliw_wait_for_GR (cpu, in_GRj); + vliw_wait_for_CCR (cpu, in_ICCi_2); + vliw_wait_for_CCR (cpu, in_FCCi_2); + handle_resource_wait (cpu); + load_wait_for_GR (cpu, in_GRi); + load_wait_for_GR (cpu, in_GRj); + trace_vliw_wait_cycles (cpu); + return 0; + } + + /* When counting branches taken or not taken, don't consider branches after + the first taken branch in a vliw insn. */ + ps = CPU_PROFILE_STATE (cpu); + if (! ps->vliw_branch_taken) + { + /* (1 << 4): The pc is the 5th element in inputs, outputs. + ??? can be cleaned up */ + PROFILE_DATA *p = CPU_PROFILE_DATA (cpu); + int taken = (referenced & (1 << 4)) != 0; + if (taken) + { + ++PROFILE_MODEL_TAKEN_COUNT (p); + ps->vliw_branch_taken = 1; + } + else + ++PROFILE_MODEL_UNTAKEN_COUNT (p); + } + + cycles = idesc->timing->units[unit_num].done; + return cycles; +} + +int +frvbf_model_fr500_u_trap (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRi, INT in_GRj, + INT in_ICCi_2, INT in_FCCi_2) +{ + int cycles; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + { + /* icc0-icc4 are the upper 4 fields of the CCR. */ + if (in_ICCi_2 >= 0) + in_ICCi_2 += 4; + + /* The entire VLIW insn must wait if there is a dependency on a register + which is not ready yet. + The latency of the registers may be less than previously recorded, + depending on how they were used previously. + See Table 13-8 in the LSI. */ + if (in_GRi >= 0) + { + if (use_is_gr_complex (cpu, in_GRi)) + decrease_GR_busy (cpu, in_GRi, 1); + } + if (in_GRj != in_GRi && in_GRj >= 0) + { + if (use_is_gr_complex (cpu, in_GRj)) + decrease_GR_busy (cpu, in_GRj, 1); + } + vliw_wait_for_GR (cpu, in_GRi); + vliw_wait_for_GR (cpu, in_GRj); + vliw_wait_for_CCR (cpu, in_ICCi_2); + vliw_wait_for_CCR (cpu, in_FCCi_2); + handle_resource_wait (cpu); + load_wait_for_GR (cpu, in_GRi); + load_wait_for_GR (cpu, in_GRj); + trace_vliw_wait_cycles (cpu); + return 0; + } + + cycles = idesc->timing->units[unit_num].done; + return cycles; +} + +int +frvbf_model_fr500_u_check (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_ICCi_3, INT in_FCCi_3) +{ + int cycles; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + { + /* icc0-icc4 are the upper 4 fields of the CCR. */ + if (in_ICCi_3 >= 0) + in_ICCi_3 += 4; + + /* The entire VLIW insn must wait if there is a dependency on a register + which is not ready yet. */ + vliw_wait_for_CCR (cpu, in_ICCi_3); + vliw_wait_for_CCR (cpu, in_FCCi_3); + handle_resource_wait (cpu); + trace_vliw_wait_cycles (cpu); + return 0; + } + + cycles = idesc->timing->units[unit_num].done; + return cycles; +} + +int +frvbf_model_fr500_u_clrgr (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRk) +{ + int cycles; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + { + /* Wait for both GNER registers or just the one specified. */ + if (in_GRk == -1) + { + vliw_wait_for_SPR (cpu, H_SPR_GNER0); + vliw_wait_for_SPR (cpu, H_SPR_GNER1); + } + else + vliw_wait_for_SPR (cpu, GNER_FOR_GR (in_GRk)); + handle_resource_wait (cpu); + trace_vliw_wait_cycles (cpu); + return 0; + } + + cycles = idesc->timing->units[unit_num].done; + return cycles; +} + +int +frvbf_model_fr500_u_clrfr (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_FRk) +{ + int cycles; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + { + /* Wait for both GNER registers or just the one specified. */ + if (in_FRk == -1) + { + vliw_wait_for_SPR (cpu, H_SPR_FNER0); + vliw_wait_for_SPR (cpu, H_SPR_FNER1); + } + else + vliw_wait_for_SPR (cpu, FNER_FOR_FR (in_FRk)); + handle_resource_wait (cpu); + trace_vliw_wait_cycles (cpu); + return 0; + } + + cycles = idesc->timing->units[unit_num].done; + return cycles; +} + +int +frvbf_model_fr500_u_commit (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRk, INT in_FRk) +{ + int cycles; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + { + /* If GR is specified, then FR is not and vice-versa. If neither is + then it's a commitga or commitfa. Check the insn attribute to + figure out which. */ + if (in_GRk != -1) + vliw_wait_for_SPR (cpu, GNER_FOR_GR (in_GRk)); + else if (in_FRk != -1) + vliw_wait_for_SPR (cpu, FNER_FOR_FR (in_FRk)); + else if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_FR_ACCESS)) + { + vliw_wait_for_SPR (cpu, H_SPR_FNER0); + vliw_wait_for_SPR (cpu, H_SPR_FNER1); + } + else + { + vliw_wait_for_SPR (cpu, H_SPR_GNER0); + vliw_wait_for_SPR (cpu, H_SPR_GNER1); + } + handle_resource_wait (cpu); + trace_vliw_wait_cycles (cpu); + return 0; + } + + cycles = idesc->timing->units[unit_num].done; + return cycles; +} + +int +frvbf_model_fr500_u_set_hilo (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT out_GRkhi, INT out_GRklo) +{ + int cycles; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + { + /* The entire VLIW insn must wait if there is a dependency on a GR + which is not ready yet. */ + vliw_wait_for_GR (cpu, out_GRkhi); + vliw_wait_for_GR (cpu, out_GRklo); + handle_resource_wait (cpu); + load_wait_for_GR (cpu, out_GRkhi); + load_wait_for_GR (cpu, out_GRklo); + trace_vliw_wait_cycles (cpu); + return 0; + } + + /* GRk is available immediately to the next VLIW insn. */ + cycles = idesc->timing->units[unit_num].done; + + set_use_not_gr_complex (cpu, out_GRkhi); + set_use_not_gr_complex (cpu, out_GRklo); + + return cycles; +} + +int +frvbf_model_fr500_u_gr_load (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRi, INT in_GRj, + INT out_GRk, INT out_GRdoublek) +{ + int cycles; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + { + /* The entire VLIW insn must wait if there is a dependency on a register + which is not ready yet. + The latency of the registers may be less than previously recorded, + depending on how they were used previously. + See Table 13-8 in the LSI. */ + if (in_GRi != out_GRk && in_GRi != out_GRdoublek + && in_GRi != out_GRdoublek + 1 && in_GRi >= 0) + { + if (use_is_gr_complex (cpu, in_GRi)) + decrease_GR_busy (cpu, in_GRi, 1); + } + if (in_GRj != in_GRi && in_GRj != out_GRk && in_GRj != out_GRdoublek + && in_GRj != out_GRdoublek + 1 && in_GRj >= 0) + + { + if (use_is_gr_complex (cpu, in_GRj)) + decrease_GR_busy (cpu, in_GRj, 1); + } + vliw_wait_for_GR (cpu, in_GRi); + vliw_wait_for_GR (cpu, in_GRj); + vliw_wait_for_GR (cpu, out_GRk); + vliw_wait_for_GRdouble (cpu, out_GRdoublek); + handle_resource_wait (cpu); + load_wait_for_GR (cpu, in_GRi); + load_wait_for_GR (cpu, in_GRj); + load_wait_for_GR (cpu, out_GRk); + load_wait_for_GRdouble (cpu, out_GRdoublek); + trace_vliw_wait_cycles (cpu); + return 0; + } + + cycles = idesc->timing->units[unit_num].done; + + /* The latency of GRk for a load will depend on how long it takes to retrieve + the the data from the cache or memory. */ + update_GR_latency_for_load (cpu, out_GRk, cycles); + update_GRdouble_latency_for_load (cpu, out_GRdoublek, cycles); + + if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) + { + /* GNER has a latency of 2 cycles. */ + update_SPR_latency (cpu, GNER_FOR_GR (out_GRk), cycles + 2); + update_SPR_latency (cpu, GNER_FOR_GR (out_GRdoublek), cycles + 2); + } + + if (out_GRk >= 0) + set_use_is_gr_complex (cpu, out_GRk); + if (out_GRdoublek != -1) + { + set_use_is_gr_complex (cpu, out_GRdoublek); + set_use_is_gr_complex (cpu, out_GRdoublek + 1); + } + + return cycles; +} + +int +frvbf_model_fr500_u_gr_store (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRi, INT in_GRj, + INT in_GRk, INT in_GRdoublek) +{ + int cycles; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + { + /* The entire VLIW insn must wait if there is a dependency on a register + which is not ready yet. + The latency of the registers may be less than previously recorded, + depending on how they were used previously. + See Table 13-8 in the LSI. */ + if (in_GRi >= 0) + { + if (use_is_gr_complex (cpu, in_GRi)) + decrease_GR_busy (cpu, in_GRi, 1); + } + if (in_GRj != in_GRi && in_GRj >= 0) + { + if (use_is_gr_complex (cpu, in_GRj)) + decrease_GR_busy (cpu, in_GRj, 1); + } + if (in_GRk != in_GRi && in_GRk != in_GRj && in_GRk >= 0) + { + if (use_is_gr_complex (cpu, in_GRk)) + decrease_GR_busy (cpu, in_GRk, 1); + } + if (in_GRdoublek != in_GRi && in_GRdoublek != in_GRj + && in_GRdoublek + 1 != in_GRi && in_GRdoublek + 1 != in_GRj + && in_GRdoublek >= 0) + { + if (use_is_gr_complex (cpu, in_GRdoublek)) + decrease_GR_busy (cpu, in_GRdoublek, 1); + if (use_is_gr_complex (cpu, in_GRdoublek + 1)) + decrease_GR_busy (cpu, in_GRdoublek + 1, 1); + } + vliw_wait_for_GR (cpu, in_GRi); + vliw_wait_for_GR (cpu, in_GRj); + vliw_wait_for_GR (cpu, in_GRk); + vliw_wait_for_GRdouble (cpu, in_GRdoublek); + handle_resource_wait (cpu); + load_wait_for_GR (cpu, in_GRi); + load_wait_for_GR (cpu, in_GRj); + load_wait_for_GR (cpu, in_GRk); + load_wait_for_GRdouble (cpu, in_GRdoublek); + trace_vliw_wait_cycles (cpu); + return 0; + } + + cycles = idesc->timing->units[unit_num].done; + + return cycles; +} + +int +frvbf_model_fr500_u_gr_r_store (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRi, INT in_GRj, + INT in_GRk, INT in_GRdoublek) +{ + int cycles = frvbf_model_fr500_u_gr_store (cpu, idesc, unit_num, referenced, + in_GRi, in_GRj, in_GRk, + in_GRdoublek); + + if (model_insn == FRV_INSN_MODEL_PASS_2) + { + if (CPU_RSTR_INVALIDATE(cpu)) + request_cache_invalidate (cpu, CPU_DATA_CACHE (cpu), cycles); + } + + return cycles; +} + +int +frvbf_model_fr500_u_fr_load (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRi, INT in_GRj, + INT out_FRk, INT out_FRdoublek) +{ + int cycles; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + { + /* The entire VLIW insn must wait if there is a dependency on a register + which is not ready yet. + The latency of the registers may be less than previously recorded, + depending on how they were used previously. + See Table 13-8 in the LSI. */ + if (in_GRi >= 0) + { + if (use_is_gr_complex (cpu, in_GRi)) + decrease_GR_busy (cpu, in_GRi, 1); + } + if (in_GRj != in_GRi && in_GRj >= 0) + { + if (use_is_gr_complex (cpu, in_GRj)) + decrease_GR_busy (cpu, in_GRj, 1); + } + if (out_FRk >= 0) + { + if (use_is_media (cpu, out_FRk)) + decrease_FR_busy (cpu, out_FRk, 1); + else + adjust_float_register_busy (cpu, -1, -1, out_FRk, 1); + } + if (out_FRdoublek >= 0) + { + if (use_is_media (cpu, out_FRdoublek)) + decrease_FR_busy (cpu, out_FRdoublek, 1); + else + adjust_float_register_busy (cpu, -1, -1, out_FRdoublek, 1); + if (use_is_media (cpu, out_FRdoublek + 1)) + decrease_FR_busy (cpu, out_FRdoublek + 1, 1); + else + adjust_float_register_busy (cpu, -1, -1, out_FRdoublek + 1, 1); + } + vliw_wait_for_GR (cpu, in_GRi); + vliw_wait_for_GR (cpu, in_GRj); + vliw_wait_for_FR (cpu, out_FRk); + vliw_wait_for_FRdouble (cpu, out_FRdoublek); + if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) + { + vliw_wait_for_SPR (cpu, FNER_FOR_FR (out_FRk)); + vliw_wait_for_SPR (cpu, FNER_FOR_FR (out_FRdoublek)); + } + handle_resource_wait (cpu); + load_wait_for_GR (cpu, in_GRi); + load_wait_for_GR (cpu, in_GRj); + load_wait_for_FR (cpu, out_FRk); + load_wait_for_FRdouble (cpu, out_FRdoublek); + trace_vliw_wait_cycles (cpu); + return 0; + } + + cycles = idesc->timing->units[unit_num].done; + + /* The latency of FRk for a load will depend on how long it takes to retrieve + the the data from the cache or memory. */ + update_FR_latency_for_load (cpu, out_FRk, cycles); + update_FRdouble_latency_for_load (cpu, out_FRdoublek, cycles); + + if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) + { + /* FNER has a latency of 3 cycles. */ + update_SPR_latency (cpu, FNER_FOR_FR (out_FRk), cycles + 3); + update_SPR_latency (cpu, FNER_FOR_FR (out_FRdoublek), cycles + 3); + } + + fr500_reset_fr_flags (cpu, out_FRk); + + return cycles; +} + +int +frvbf_model_fr500_u_fr_store (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRi, INT in_GRj, + INT in_FRk, INT in_FRdoublek) +{ + int cycles; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + { + /* The entire VLIW insn must wait if there is a dependency on a register + which is not ready yet. + The latency of the registers may be less than previously recorded, + depending on how they were used previously. + See Table 13-8 in the LSI. */ + if (in_GRi >= 0) + { + if (use_is_gr_complex (cpu, in_GRi)) + decrease_GR_busy (cpu, in_GRi, 1); + } + if (in_GRj != in_GRi && in_GRj >= 0) + { + if (use_is_gr_complex (cpu, in_GRj)) + decrease_GR_busy (cpu, in_GRj, 1); + } + if (in_FRk >= 0) + { + if (use_is_media (cpu, in_FRk)) + decrease_FR_busy (cpu, in_FRk, 1); + else + adjust_float_register_busy (cpu, -1, -1, in_FRk, 1); + } + if (in_FRdoublek >= 0) + { + if (use_is_media (cpu, in_FRdoublek)) + decrease_FR_busy (cpu, in_FRdoublek, 1); + else + adjust_float_register_busy (cpu, -1, -1, in_FRdoublek, 1); + if (use_is_media (cpu, in_FRdoublek + 1)) + decrease_FR_busy (cpu, in_FRdoublek + 1, 1); + else + adjust_float_register_busy (cpu, -1, -1, in_FRdoublek + 1, 1); + } + vliw_wait_for_GR (cpu, in_GRi); + vliw_wait_for_GR (cpu, in_GRj); + vliw_wait_for_FR (cpu, in_FRk); + vliw_wait_for_FRdouble (cpu, in_FRdoublek); + handle_resource_wait (cpu); + load_wait_for_GR (cpu, in_GRi); + load_wait_for_GR (cpu, in_GRj); + load_wait_for_FR (cpu, in_FRk); + load_wait_for_FRdouble (cpu, in_FRdoublek); + trace_vliw_wait_cycles (cpu); + return 0; + } + + cycles = idesc->timing->units[unit_num].done; + + return cycles; +} + +int +frvbf_model_fr500_u_fr_r_store (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRi, INT in_GRj, + INT in_FRk, INT in_FRdoublek) +{ + int cycles = frvbf_model_fr500_u_fr_store (cpu, idesc, unit_num, referenced, + in_GRi, in_GRj, in_FRk, + in_FRdoublek); + + if (model_insn == FRV_INSN_MODEL_PASS_2) + { + if (CPU_RSTR_INVALIDATE(cpu)) + request_cache_invalidate (cpu, CPU_DATA_CACHE (cpu), cycles); + } + + return cycles; +} + +int +frvbf_model_fr500_u_swap (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRi, INT in_GRj, INT out_GRk) +{ + int cycles; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + { + /* The entire VLIW insn must wait if there is a dependency on a register + which is not ready yet. + The latency of the registers may be less than previously recorded, + depending on how they were used previously. + See Table 13-8 in the LSI. */ + if (in_GRi != out_GRk && in_GRi >= 0) + { + if (use_is_gr_complex (cpu, in_GRi)) + decrease_GR_busy (cpu, in_GRi, 1); + } + if (in_GRj != out_GRk && in_GRj != in_GRi && in_GRj >= 0) + { + if (use_is_gr_complex (cpu, in_GRj)) + decrease_GR_busy (cpu, in_GRj, 1); + } + vliw_wait_for_GR (cpu, in_GRi); + vliw_wait_for_GR (cpu, in_GRj); + vliw_wait_for_GR (cpu, out_GRk); + handle_resource_wait (cpu); + load_wait_for_GR (cpu, in_GRi); + load_wait_for_GR (cpu, in_GRj); + load_wait_for_GR (cpu, out_GRk); + trace_vliw_wait_cycles (cpu); + return 0; + } + + cycles = idesc->timing->units[unit_num].done; + + /* The latency of GRk will depend on how long it takes to swap + the the data from the cache or memory. */ + update_GR_latency_for_swap (cpu, out_GRk, cycles); + set_use_is_gr_complex (cpu, out_GRk); + + return cycles; +} + +int +frvbf_model_fr500_u_fr2fr (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_FRj, INT out_FRk) +{ + int cycles; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + { + /* The entire VLIW insn must wait if there is a dependency on a register + which is not ready yet. */ + if (in_FRj >= 0) + { + if (use_is_media (cpu, in_FRj)) + decrease_FR_busy (cpu, in_FRj, 1); + else + adjust_float_register_busy (cpu, -1, in_FRj, -1, 1); + } + if (out_FRk >= 0 && out_FRk != in_FRj) + { + if (use_is_media (cpu, out_FRk)) + decrease_FR_busy (cpu, out_FRk, 1); + else + adjust_float_register_busy (cpu, -1, -1, out_FRk, 1); + } + vliw_wait_for_FR (cpu, in_FRj); + vliw_wait_for_FR (cpu, out_FRk); + handle_resource_wait (cpu); + load_wait_for_FR (cpu, in_FRj); + load_wait_for_FR (cpu, out_FRk); + trace_vliw_wait_cycles (cpu); + return 0; + } + + /* The latency of FRj is 3 cycles. */ + cycles = idesc->timing->units[unit_num].done; + update_FR_latency (cpu, out_FRk, cycles + 3); + + return cycles; +} + +int +frvbf_model_fr500_u_fr2gr (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_FRk, INT out_GRj) +{ + int cycles; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + { + /* The entire VLIW insn must wait if there is a dependency on a register + which is not ready yet. */ + if (in_FRk >= 0) + { + if (use_is_media (cpu, in_FRk)) + decrease_FR_busy (cpu, in_FRk, 1); + else + adjust_float_register_busy (cpu, -1, in_FRk, -1, 1); + } + vliw_wait_for_FR (cpu, in_FRk); + vliw_wait_for_GR (cpu, out_GRj); + handle_resource_wait (cpu); + load_wait_for_FR (cpu, in_FRk); + load_wait_for_GR (cpu, out_GRj); + trace_vliw_wait_cycles (cpu); + return 0; + } + + /* The latency of GRj is 2 cycles. */ + cycles = idesc->timing->units[unit_num].done; + update_GR_latency (cpu, out_GRj, cycles + 2); + set_use_is_gr_complex (cpu, out_GRj); + + return cycles; +} + +int +frvbf_model_fr500_u_spr2gr (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_spr, INT out_GRj) +{ + int cycles; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + { + /* The entire VLIW insn must wait if there is a dependency on a register + which is not ready yet. */ + vliw_wait_for_SPR (cpu, in_spr); + vliw_wait_for_GR (cpu, out_GRj); + handle_resource_wait (cpu); + load_wait_for_GR (cpu, out_GRj); + trace_vliw_wait_cycles (cpu); + return 0; + } + + cycles = idesc->timing->units[unit_num].done; + +#if 0 /* no latency? */ + /* The latency of GRj is 2 cycles. */ + update_GR_latency (cpu, out_GRj, cycles + 2); +#endif + + return cycles; +} + +int +frvbf_model_fr500_u_gr2fr (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRj, INT out_FRk) +{ + int cycles; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + { + /* The entire VLIW insn must wait if there is a dependency on a register + which is not ready yet. + The latency of the registers may be less than previously recorded, + depending on how they were used previously. + See Table 13-8 in the LSI. */ + if (in_GRj >= 0) + { + if (use_is_gr_complex (cpu, in_GRj)) + decrease_GR_busy (cpu, in_GRj, 1); + } + if (out_FRk >= 0) + { + if (use_is_media (cpu, out_FRk)) + decrease_FR_busy (cpu, out_FRk, 1); + else + adjust_float_register_busy (cpu, -1, -1, out_FRk, 1); + } + vliw_wait_for_GR (cpu, in_GRj); + vliw_wait_for_FR (cpu, out_FRk); + handle_resource_wait (cpu); + load_wait_for_GR (cpu, in_GRj); + load_wait_for_FR (cpu, out_FRk); + trace_vliw_wait_cycles (cpu); + return 0; + } + + /* The latency of FRk is 2 cycles. */ + cycles = idesc->timing->units[unit_num].done; + update_FR_latency (cpu, out_FRk, cycles + 2); + + /* Mark this use of the register as NOT a floating point op. */ + fr500_reset_fr_flags (cpu, out_FRk); + + return cycles; +} + +int +frvbf_model_fr500_u_gr2spr (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRj, INT out_spr) +{ + int cycles; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + { + /* The entire VLIW insn must wait if there is a dependency on a register + which is not ready yet. + The latency of the registers may be less than previously recorded, + depending on how they were used previously. + See Table 13-8 in the LSI. */ + if (in_GRj >= 0) + { + if (use_is_gr_complex (cpu, in_GRj)) + decrease_GR_busy (cpu, in_GRj, 1); + } + vliw_wait_for_GR (cpu, in_GRj); + vliw_wait_for_SPR (cpu, out_spr); + handle_resource_wait (cpu); + load_wait_for_GR (cpu, in_GRj); + trace_vliw_wait_cycles (cpu); + return 0; + } + + cycles = idesc->timing->units[unit_num].done; + +#if 0 + /* The latency of spr is ? cycles. */ + update_SPR_latency (cpu, out_spr, cycles + ?); +#endif + + return cycles; +} + +int +frvbf_model_fr500_u_ici (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRi, INT in_GRj) +{ + int cycles; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + { + /* The entire VLIW insn must wait if there is a dependency on a register + which is not ready yet. + The latency of the registers may be less than previously recorded, + depending on how they were used previously. + See Table 13-8 in the LSI. */ + if (in_GRi >= 0) + { + if (use_is_gr_complex (cpu, in_GRi)) + decrease_GR_busy (cpu, in_GRi, 1); + } + if (in_GRj != in_GRi && in_GRj >= 0) + { + if (use_is_gr_complex (cpu, in_GRj)) + decrease_GR_busy (cpu, in_GRj, 1); + } + vliw_wait_for_GR (cpu, in_GRi); + vliw_wait_for_GR (cpu, in_GRj); + handle_resource_wait (cpu); + load_wait_for_GR (cpu, in_GRi); + load_wait_for_GR (cpu, in_GRj); + trace_vliw_wait_cycles (cpu); + return 0; + } + + cycles = idesc->timing->units[unit_num].done; + request_cache_invalidate (cpu, CPU_INSN_CACHE (cpu), cycles); + return cycles; +} + +int +frvbf_model_fr500_u_dci (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRi, INT in_GRj) +{ + int cycles; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + { + /* The entire VLIW insn must wait if there is a dependency on a register + which is not ready yet. + The latency of the registers may be less than previously recorded, + depending on how they were used previously. + See Table 13-8 in the LSI. */ + if (in_GRi >= 0) + { + if (use_is_gr_complex (cpu, in_GRi)) + decrease_GR_busy (cpu, in_GRi, 1); + } + if (in_GRj != in_GRi && in_GRj >= 0) + { + if (use_is_gr_complex (cpu, in_GRj)) + decrease_GR_busy (cpu, in_GRj, 1); + } + vliw_wait_for_GR (cpu, in_GRi); + vliw_wait_for_GR (cpu, in_GRj); + handle_resource_wait (cpu); + load_wait_for_GR (cpu, in_GRi); + load_wait_for_GR (cpu, in_GRj); + trace_vliw_wait_cycles (cpu); + return 0; + } + + cycles = idesc->timing->units[unit_num].done; + request_cache_invalidate (cpu, CPU_DATA_CACHE (cpu), cycles); + return cycles; +} + +int +frvbf_model_fr500_u_dcf (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRi, INT in_GRj) +{ + int cycles; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + { + /* The entire VLIW insn must wait if there is a dependency on a register + which is not ready yet. + The latency of the registers may be less than previously recorded, + depending on how they were used previously. + See Table 13-8 in the LSI. */ + if (in_GRi >= 0) + { + if (use_is_gr_complex (cpu, in_GRi)) + decrease_GR_busy (cpu, in_GRi, 1); + } + if (in_GRj != in_GRi && in_GRj >= 0) + { + if (use_is_gr_complex (cpu, in_GRj)) + decrease_GR_busy (cpu, in_GRj, 1); + } + vliw_wait_for_GR (cpu, in_GRi); + vliw_wait_for_GR (cpu, in_GRj); + handle_resource_wait (cpu); + load_wait_for_GR (cpu, in_GRi); + load_wait_for_GR (cpu, in_GRj); + trace_vliw_wait_cycles (cpu); + return 0; + } + + cycles = idesc->timing->units[unit_num].done; + request_cache_flush (cpu, CPU_DATA_CACHE (cpu), cycles); + return cycles; +} + +int +frvbf_model_fr500_u_icpl (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRi, INT in_GRj) +{ + int cycles; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + { + /* The entire VLIW insn must wait if there is a dependency on a register + which is not ready yet. + The latency of the registers may be less than previously recorded, + depending on how they were used previously. + See Table 13-8 in the LSI. */ + if (in_GRi >= 0) + { + if (use_is_gr_complex (cpu, in_GRi)) + decrease_GR_busy (cpu, in_GRi, 1); + } + if (in_GRj != in_GRi && in_GRj >= 0) + { + if (use_is_gr_complex (cpu, in_GRj)) + decrease_GR_busy (cpu, in_GRj, 1); + } + vliw_wait_for_GR (cpu, in_GRi); + vliw_wait_for_GR (cpu, in_GRj); + handle_resource_wait (cpu); + load_wait_for_GR (cpu, in_GRi); + load_wait_for_GR (cpu, in_GRj); + trace_vliw_wait_cycles (cpu); + return 0; + } + + cycles = idesc->timing->units[unit_num].done; + request_cache_preload (cpu, CPU_INSN_CACHE (cpu), cycles); + return cycles; +} + +int +frvbf_model_fr500_u_dcpl (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRi, INT in_GRj) +{ + int cycles; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + { + /* The entire VLIW insn must wait if there is a dependency on a register + which is not ready yet. + The latency of the registers may be less than previously recorded, + depending on how they were used previously. + See Table 13-8 in the LSI. */ + if (in_GRi >= 0) + { + if (use_is_gr_complex (cpu, in_GRi)) + decrease_GR_busy (cpu, in_GRi, 1); + } + if (in_GRj != in_GRi && in_GRj >= 0) + { + if (use_is_gr_complex (cpu, in_GRj)) + decrease_GR_busy (cpu, in_GRj, 1); + } + vliw_wait_for_GR (cpu, in_GRi); + vliw_wait_for_GR (cpu, in_GRj); + handle_resource_wait (cpu); + load_wait_for_GR (cpu, in_GRi); + load_wait_for_GR (cpu, in_GRj); + trace_vliw_wait_cycles (cpu); + return 0; + } + + cycles = idesc->timing->units[unit_num].done; + request_cache_preload (cpu, CPU_DATA_CACHE (cpu), cycles); + return cycles; +} + +int +frvbf_model_fr500_u_icul (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRi, INT in_GRj) +{ + int cycles; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + { + /* The entire VLIW insn must wait if there is a dependency on a register + which is not ready yet. + The latency of the registers may be less than previously recorded, + depending on how they were used previously. + See Table 13-8 in the LSI. */ + if (in_GRi >= 0) + { + if (use_is_gr_complex (cpu, in_GRi)) + decrease_GR_busy (cpu, in_GRi, 1); + } + if (in_GRj != in_GRi && in_GRj >= 0) + { + if (use_is_gr_complex (cpu, in_GRj)) + decrease_GR_busy (cpu, in_GRj, 1); + } + vliw_wait_for_GR (cpu, in_GRi); + vliw_wait_for_GR (cpu, in_GRj); + handle_resource_wait (cpu); + load_wait_for_GR (cpu, in_GRi); + load_wait_for_GR (cpu, in_GRj); + trace_vliw_wait_cycles (cpu); + return 0; + } + + cycles = idesc->timing->units[unit_num].done; + request_cache_unlock (cpu, CPU_INSN_CACHE (cpu), cycles); + return cycles; +} + +int +frvbf_model_fr500_u_dcul (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRi, INT in_GRj) +{ + int cycles; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + { + /* The entire VLIW insn must wait if there is a dependency on a register + which is not ready yet. + The latency of the registers may be less than previously recorded, + depending on how they were used previously. + See Table 13-8 in the LSI. */ + if (in_GRi >= 0) + { + if (use_is_gr_complex (cpu, in_GRi)) + decrease_GR_busy (cpu, in_GRi, 1); + } + if (in_GRj != in_GRi && in_GRj >= 0) + { + if (use_is_gr_complex (cpu, in_GRj)) + decrease_GR_busy (cpu, in_GRj, 1); + } + vliw_wait_for_GR (cpu, in_GRi); + vliw_wait_for_GR (cpu, in_GRj); + handle_resource_wait (cpu); + load_wait_for_GR (cpu, in_GRi); + load_wait_for_GR (cpu, in_GRj); + trace_vliw_wait_cycles (cpu); + return 0; + } + + cycles = idesc->timing->units[unit_num].done; + request_cache_unlock (cpu, CPU_DATA_CACHE (cpu), cycles); + return cycles; +} + +int +frvbf_model_fr500_u_float_arith (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_FRi, INT in_FRj, + INT in_FRdoublei, INT in_FRdoublej, + INT out_FRk, INT out_FRdoublek) +{ + int cycles; + FRV_PROFILE_STATE *ps; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + return 0; + + /* The preprocessing can execute right away. */ + cycles = idesc->timing->units[unit_num].done; + + /* The post processing must wait if there is a dependency on a FR + which is not ready yet. */ + adjust_float_register_busy (cpu, in_FRi, in_FRj, out_FRk, 1); + adjust_double_register_busy (cpu, in_FRdoublei, in_FRdoublej, out_FRdoublek, + 1); + ps = CPU_PROFILE_STATE (cpu); + ps->post_wait = cycles; + post_wait_for_FR (cpu, in_FRi); + post_wait_for_FR (cpu, in_FRj); + post_wait_for_FR (cpu, out_FRk); + post_wait_for_FRdouble (cpu, in_FRdoublei); + post_wait_for_FRdouble (cpu, in_FRdoublej); + post_wait_for_FRdouble (cpu, out_FRdoublek); + if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) + { + post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRk)); + post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRdoublek)); + } + restore_float_register_busy (cpu, in_FRi, in_FRj, out_FRk, 1); + restore_double_register_busy (cpu, in_FRdoublei, in_FRdoublej, out_FRdoublek, + 1); + + /* The latency of FRk will be at least the latency of the other inputs. */ + update_FR_latency (cpu, out_FRk, ps->post_wait); + update_FRdouble_latency (cpu, out_FRdoublek, ps->post_wait); + + if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) + { + update_SPR_latency (cpu, FNER_FOR_FR (out_FRk), ps->post_wait); + update_SPR_latency (cpu, FNER_FOR_FR (out_FRdoublek), ps->post_wait); + } + + /* Once initiated, post-processing will take 3 cycles. */ + update_FR_ptime (cpu, out_FRk, 3); + update_FRdouble_ptime (cpu, out_FRdoublek, 3); + + if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) + { + update_SPR_ptime (cpu, FNER_FOR_FR (out_FRk), 3); + update_SPR_ptime (cpu, FNER_FOR_FR (out_FRdoublek), 3); + } + + /* Mark this use of the register as a floating point op. */ + if (out_FRk >= 0) + set_use_is_fpop (cpu, out_FRk); + if (out_FRdoublek >= 0) + { + set_use_is_fpop (cpu, out_FRdoublek); + if (out_FRdoublek < 63) + set_use_is_fpop (cpu, out_FRdoublek + 1); + } + + return cycles; +} + +int +frvbf_model_fr500_u_float_dual_arith (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_FRi, INT in_FRj, + INT in_FRdoublei, INT in_FRdoublej, + INT out_FRk, INT out_FRdoublek) +{ + int cycles; + INT dual_FRi; + INT dual_FRj; + INT dual_FRk; + INT dual_FRdoublei; + INT dual_FRdoublej; + INT dual_FRdoublek; + FRV_PROFILE_STATE *ps; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + return 0; + + /* The preprocessing can execute right away. */ + cycles = idesc->timing->units[unit_num].done; + + /* The post processing must wait if there is a dependency on a FR + which is not ready yet. */ + dual_FRi = DUAL_REG (in_FRi); + dual_FRj = DUAL_REG (in_FRj); + dual_FRk = DUAL_REG (out_FRk); + dual_FRdoublei = DUAL_DOUBLE (in_FRdoublei); + dual_FRdoublej = DUAL_DOUBLE (in_FRdoublej); + dual_FRdoublek = DUAL_DOUBLE (out_FRdoublek); + + adjust_float_register_busy (cpu, in_FRi, in_FRj, out_FRk, 1); + adjust_float_register_busy (cpu, dual_FRi, dual_FRj, dual_FRk, 1); + adjust_double_register_busy (cpu, in_FRdoublei, in_FRdoublej, out_FRdoublek, + 1); + adjust_double_register_busy (cpu, dual_FRdoublei, dual_FRdoublej, + dual_FRdoublek, 1); + ps = CPU_PROFILE_STATE (cpu); + ps->post_wait = cycles; + post_wait_for_FR (cpu, in_FRi); + post_wait_for_FR (cpu, in_FRj); + post_wait_for_FR (cpu, out_FRk); + post_wait_for_FR (cpu, dual_FRi); + post_wait_for_FR (cpu, dual_FRj); + post_wait_for_FR (cpu, dual_FRk); + post_wait_for_FRdouble (cpu, in_FRdoublei); + post_wait_for_FRdouble (cpu, in_FRdoublej); + post_wait_for_FRdouble (cpu, out_FRdoublek); + post_wait_for_FRdouble (cpu, dual_FRdoublei); + post_wait_for_FRdouble (cpu, dual_FRdoublej); + post_wait_for_FRdouble (cpu, dual_FRdoublek); + if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) + { + post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRk)); + post_wait_for_SPR (cpu, FNER_FOR_FR (dual_FRk)); + post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRdoublek)); + post_wait_for_SPR (cpu, FNER_FOR_FR (dual_FRdoublek)); + } + restore_float_register_busy (cpu, in_FRi, in_FRj, out_FRk, 1); + restore_float_register_busy (cpu, dual_FRi, dual_FRj, dual_FRk, 1); + restore_double_register_busy (cpu, in_FRdoublei, in_FRdoublej, out_FRdoublek, + 1); + restore_double_register_busy (cpu, dual_FRdoublei, dual_FRdoublej, + dual_FRdoublek, 1); + + /* The latency of FRk will be at least the latency of the other inputs. */ + update_FR_latency (cpu, out_FRk, ps->post_wait); + update_FR_latency (cpu, dual_FRk, ps->post_wait); + update_FRdouble_latency (cpu, out_FRdoublek, ps->post_wait); + update_FRdouble_latency (cpu, dual_FRdoublek, ps->post_wait); + + if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) + { + update_SPR_latency (cpu, FNER_FOR_FR (out_FRk), ps->post_wait); + update_SPR_latency (cpu, FNER_FOR_FR (dual_FRk), ps->post_wait); + update_SPR_latency (cpu, FNER_FOR_FR (out_FRdoublek), ps->post_wait); + update_SPR_latency (cpu, FNER_FOR_FR (dual_FRdoublek), ps->post_wait); + } + + /* Once initiated, post-processing will take 3 cycles. */ + update_FR_ptime (cpu, out_FRk, 3); + update_FR_ptime (cpu, dual_FRk, 3); + update_FRdouble_ptime (cpu, out_FRdoublek, 3); + update_FRdouble_ptime (cpu, dual_FRdoublek, 3); + + if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) + { + update_SPR_ptime (cpu, FNER_FOR_FR (out_FRk), 3); + update_SPR_ptime (cpu, FNER_FOR_FR (dual_FRk), 3); + update_SPR_ptime (cpu, FNER_FOR_FR (out_FRdoublek), 3); + update_SPR_ptime (cpu, FNER_FOR_FR (dual_FRdoublek), 3); + } + + /* Mark this use of the register as a floating point op. */ + if (out_FRk >= 0) + set_use_is_fpop (cpu, out_FRk); + if (dual_FRk >= 0) + set_use_is_fpop (cpu, dual_FRk); + if (out_FRdoublek >= 0) + { + set_use_is_fpop (cpu, out_FRdoublek); + if (out_FRdoublek < 63) + set_use_is_fpop (cpu, out_FRdoublek + 1); + } + if (dual_FRdoublek >= 0) + { + set_use_is_fpop (cpu, dual_FRdoublek); + if (dual_FRdoublek < 63) + set_use_is_fpop (cpu, dual_FRdoublek + 1); + } + + return cycles; +} + +int +frvbf_model_fr500_u_float_div (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_FRi, INT in_FRj, INT out_FRk) +{ + int cycles; + FRV_VLIW *vliw; + int slot; + FRV_PROFILE_STATE *ps; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + return 0; + + cycles = idesc->timing->units[unit_num].done; + + /* The post processing must wait if there is a dependency on a FR + which is not ready yet. */ + adjust_float_register_busy (cpu, in_FRi, in_FRj, out_FRk, 1); + ps = CPU_PROFILE_STATE (cpu); + ps->post_wait = cycles; + post_wait_for_FR (cpu, in_FRi); + post_wait_for_FR (cpu, in_FRj); + post_wait_for_FR (cpu, out_FRk); + if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) + post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRk)); + vliw = CPU_VLIW (cpu); + slot = vliw->next_slot - 1; + slot = (*vliw->current_vliw)[slot] - UNIT_FM0; + post_wait_for_fdiv (cpu, slot); + restore_float_register_busy (cpu, in_FRi, in_FRj, out_FRk, 1); + + /* The latency of FRk will be at least the latency of the other inputs. */ + /* Once initiated, post-processing will take 10 cycles. */ + update_FR_latency (cpu, out_FRk, ps->post_wait); + update_FR_ptime (cpu, out_FRk, 10); + + if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) + { + /* FNER has a latency of 10 cycles. */ + update_SPR_latency (cpu, FNER_FOR_FR (out_FRk), ps->post_wait); + update_SPR_ptime (cpu, FNER_FOR_FR (out_FRk), 10); + } + + /* The latency of the fdiv unit will be at least the latency of the other + inputs. Once initiated, post-processing will take 9 cycles. */ + update_fdiv_resource_latency (cpu, slot, ps->post_wait + 9); + + /* Mark this use of the register as a floating point op. */ + set_use_is_fpop (cpu, out_FRk); + + return cycles; +} + +int +frvbf_model_fr500_u_float_sqrt (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_FRj, INT in_FRdoublej, + INT out_FRk, INT out_FRdoublek) +{ + int cycles; + FRV_VLIW *vliw; + int slot; + FRV_PROFILE_STATE *ps; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + return 0; + + cycles = idesc->timing->units[unit_num].done; + + /* The post processing must wait if there is a dependency on a FR + which is not ready yet. */ + adjust_float_register_busy (cpu, -1, in_FRj, out_FRk, 1); + adjust_double_register_busy (cpu, -1, in_FRdoublej, out_FRdoublek, 1); + ps = CPU_PROFILE_STATE (cpu); + ps->post_wait = cycles; + post_wait_for_FR (cpu, in_FRj); + post_wait_for_FR (cpu, out_FRk); + post_wait_for_FRdouble (cpu, in_FRdoublej); + post_wait_for_FRdouble (cpu, out_FRdoublek); + if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) + post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRk)); + vliw = CPU_VLIW (cpu); + slot = vliw->next_slot - 1; + slot = (*vliw->current_vliw)[slot] - UNIT_FM0; + post_wait_for_fsqrt (cpu, slot); + restore_float_register_busy (cpu, -1, in_FRj, out_FRk, 1); + restore_double_register_busy (cpu, -1, in_FRdoublej, out_FRdoublek, 1); + + /* The latency of FRk will be at least the latency of the other inputs. */ + update_FR_latency (cpu, out_FRk, ps->post_wait); + update_FRdouble_latency (cpu, out_FRdoublek, ps->post_wait); + if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) + update_SPR_latency (cpu, FNER_FOR_FR (out_FRk), ps->post_wait); + + /* Once initiated, post-processing will take 15 cycles. */ + update_FR_ptime (cpu, out_FRk, 15); + update_FRdouble_ptime (cpu, out_FRdoublek, 15); + + if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) + update_SPR_ptime (cpu, FNER_FOR_FR (out_FRk), 15); + + /* The latency of the sqrt unit will be the latency of the other + inputs plus 14 cycles. */ + update_fsqrt_resource_latency (cpu, slot, ps->post_wait + 14); + + /* Mark this use of the register as a floating point op. */ + if (out_FRk >= 0) + set_use_is_fpop (cpu, out_FRk); + if (out_FRdoublek >= 0) + { + set_use_is_fpop (cpu, out_FRdoublek); + if (out_FRdoublek < 63) + set_use_is_fpop (cpu, out_FRdoublek + 1); + } + + return cycles; +} + +int +frvbf_model_fr500_u_float_dual_sqrt (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_FRj, INT out_FRk) +{ + int cycles; + FRV_VLIW *vliw; + int slot; + INT dual_FRj; + INT dual_FRk; + FRV_PROFILE_STATE *ps; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + return 0; + + cycles = idesc->timing->units[unit_num].done; + + /* The post processing must wait if there is a dependency on a FR + which is not ready yet. */ + dual_FRj = DUAL_REG (in_FRj); + dual_FRk = DUAL_REG (out_FRk); + adjust_float_register_busy (cpu, -1, in_FRj, out_FRk, 1); + adjust_float_register_busy (cpu, -1, dual_FRj, dual_FRk, 1); + ps = CPU_PROFILE_STATE (cpu); + ps->post_wait = cycles; + post_wait_for_FR (cpu, in_FRj); + post_wait_for_FR (cpu, out_FRk); + post_wait_for_FR (cpu, dual_FRj); + post_wait_for_FR (cpu, dual_FRk); + + vliw = CPU_VLIW (cpu); + slot = vliw->next_slot - 1; + slot = (*vliw->current_vliw)[slot] - UNIT_FM0; + post_wait_for_fsqrt (cpu, slot); + restore_float_register_busy (cpu, -1, in_FRj, out_FRk, 1); + restore_float_register_busy (cpu, -1, dual_FRj, dual_FRk, 1); + + /* The latency of FRk will be at least the latency of the other inputs. */ + update_FR_latency (cpu, out_FRk, ps->post_wait); + update_FR_latency (cpu, dual_FRk, ps->post_wait); + + /* Once initiated, post-processing will take 15 cycles. */ + update_FR_ptime (cpu, out_FRk, 15); + update_FR_ptime (cpu, dual_FRk, 15); + + /* The latency of the sqrt unit will be at least the latency of the other + inputs. */ + update_fsqrt_resource_latency (cpu, slot, ps->post_wait + 14); + + /* Mark this use of the register as a floating point op. */ + if (out_FRk >= 0) + set_use_is_fpop (cpu, out_FRk); + if (dual_FRk >= 0) + set_use_is_fpop (cpu, dual_FRk); + + return cycles; +} + +int +frvbf_model_fr500_u_float_compare (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_FRi, INT in_FRj, + INT in_FRdoublei, INT in_FRdoublej, + INT out_FCCi_2) +{ + int cycles; + FRV_PROFILE_STATE *ps; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + return 0; + + /* The preprocessing can execute right away. */ + cycles = idesc->timing->units[unit_num].done; + + /* The post processing must wait if there is a dependency on a FR + which is not ready yet. */ + adjust_double_register_busy (cpu, in_FRdoublei, in_FRdoublej, -1, 1); + ps = CPU_PROFILE_STATE (cpu); + ps->post_wait = cycles; + post_wait_for_FR (cpu, in_FRi); + post_wait_for_FR (cpu, in_FRj); + post_wait_for_FRdouble (cpu, in_FRdoublei); + post_wait_for_FRdouble (cpu, in_FRdoublej); + post_wait_for_CCR (cpu, out_FCCi_2); + restore_double_register_busy (cpu, in_FRdoublei, in_FRdoublej, -1, 1); + + /* The latency of FCCi_2 will be the latency of the other inputs plus 3 + cycles. */ + update_CCR_latency (cpu, out_FCCi_2, ps->post_wait + 3); + + return cycles; +} + +int +frvbf_model_fr500_u_float_dual_compare (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_FRi, INT in_FRj, + INT out_FCCi_2) +{ + int cycles; + INT dual_FRi; + INT dual_FRj; + INT dual_FCCi_2; + FRV_PROFILE_STATE *ps; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + return 0; + + /* The preprocessing can execute right away. */ + cycles = idesc->timing->units[unit_num].done; + + /* The post processing must wait if there is a dependency on a FR + which is not ready yet. */ + ps = CPU_PROFILE_STATE (cpu); + ps->post_wait = cycles; + dual_FRi = DUAL_REG (in_FRi); + dual_FRj = DUAL_REG (in_FRj); + dual_FCCi_2 = out_FCCi_2 + 1; + adjust_float_register_busy (cpu, in_FRi, in_FRj, -1, 1); + adjust_float_register_busy (cpu, dual_FRi, dual_FRj, -1, 1); + post_wait_for_FR (cpu, in_FRi); + post_wait_for_FR (cpu, in_FRj); + post_wait_for_FR (cpu, dual_FRi); + post_wait_for_FR (cpu, dual_FRj); + post_wait_for_CCR (cpu, out_FCCi_2); + post_wait_for_CCR (cpu, dual_FCCi_2); + restore_float_register_busy (cpu, in_FRi, in_FRj, -1, 1); + restore_float_register_busy (cpu, dual_FRi, dual_FRj, -1, 1); + + /* The latency of FCCi_2 will be the latency of the other inputs plus 3 + cycles. */ + update_CCR_latency (cpu, out_FCCi_2, ps->post_wait + 3); + update_CCR_latency (cpu, dual_FCCi_2, ps->post_wait + 3); + + return cycles; +} + +int +frvbf_model_fr500_u_float_convert (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_FRj, INT in_FRintj, INT in_FRdoublej, + INT out_FRk, INT out_FRintk, + INT out_FRdoublek) +{ + int cycles; + FRV_PROFILE_STATE *ps; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + return 0; + + /* The preprocessing can execute right away. */ + cycles = idesc->timing->units[unit_num].done; + + /* The post processing must wait if there is a dependency on a FR + which is not ready yet. */ + ps = CPU_PROFILE_STATE (cpu); + ps->post_wait = cycles; + adjust_float_register_busy (cpu, -1, in_FRj, out_FRk, 1); + adjust_float_register_busy (cpu, -1, in_FRintj, out_FRintk, 1); + adjust_double_register_busy (cpu, -1, in_FRdoublej, out_FRdoublek, 1); + post_wait_for_FR (cpu, in_FRj); + post_wait_for_FR (cpu, in_FRintj); + post_wait_for_FRdouble (cpu, in_FRdoublej); + post_wait_for_FR (cpu, out_FRk); + post_wait_for_FR (cpu, out_FRintk); + post_wait_for_FRdouble (cpu, out_FRdoublek); + if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) + { + post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRk)); + post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRintk)); + post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRdoublek)); + } + restore_float_register_busy (cpu, -1, in_FRj, out_FRk, 1); + restore_float_register_busy (cpu, -1, in_FRintj, out_FRintk, 1); + restore_double_register_busy (cpu, -1, in_FRdoublej, out_FRdoublek, 1); + + /* The latency of FRk will be at least the latency of the other inputs. */ + update_FR_latency (cpu, out_FRk, ps->post_wait); + update_FR_latency (cpu, out_FRintk, ps->post_wait); + update_FRdouble_latency (cpu, out_FRdoublek, ps->post_wait); + + if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) + { + update_SPR_latency (cpu, FNER_FOR_FR (out_FRk), ps->post_wait); + update_SPR_latency (cpu, FNER_FOR_FR (out_FRintk), ps->post_wait); + update_SPR_latency (cpu, FNER_FOR_FR (out_FRdoublek), ps->post_wait); + } + + /* Once initiated, post-processing will take 3 cycles. */ + update_FR_ptime (cpu, out_FRk, 3); + update_FR_ptime (cpu, out_FRintk, 3); + update_FRdouble_ptime (cpu, out_FRdoublek, 3); + + if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) + { + update_SPR_ptime (cpu, FNER_FOR_FR (out_FRk), 3); + update_SPR_ptime (cpu, FNER_FOR_FR (out_FRintk), 3); + update_SPR_ptime (cpu, FNER_FOR_FR (out_FRdoublek), 3); + } + + /* Mark this use of the register as a floating point op. */ + if (out_FRk >= 0) + set_use_is_fpop (cpu, out_FRk); + if (out_FRintk >= 0) + set_use_is_fpop (cpu, out_FRintk); + if (out_FRdoublek >= 0) + { + set_use_is_fpop (cpu, out_FRdoublek); + set_use_is_fpop (cpu, out_FRdoublek + 1); + } + + return cycles; +} + +int +frvbf_model_fr500_u_float_dual_convert (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_FRj, INT in_FRintj, + INT out_FRk, INT out_FRintk) +{ + int cycles; + INT dual_FRj; + INT dual_FRintj; + INT dual_FRk; + INT dual_FRintk; + FRV_PROFILE_STATE *ps; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + return 0; + + /* The preprocessing can execute right away. */ + cycles = idesc->timing->units[unit_num].done; + + /* The post processing must wait if there is a dependency on a FR + which is not ready yet. */ + ps = CPU_PROFILE_STATE (cpu); + ps->post_wait = cycles; + dual_FRj = DUAL_REG (in_FRj); + dual_FRintj = DUAL_REG (in_FRintj); + dual_FRk = DUAL_REG (out_FRk); + dual_FRintk = DUAL_REG (out_FRintk); + adjust_float_register_busy (cpu, -1, in_FRj, out_FRk, 1); + adjust_float_register_busy (cpu, -1, dual_FRj, dual_FRk, 1); + adjust_float_register_busy (cpu, -1, in_FRintj, out_FRintk, 1); + adjust_float_register_busy (cpu, -1, dual_FRintj, dual_FRintk, 1); + post_wait_for_FR (cpu, in_FRj); + post_wait_for_FR (cpu, in_FRintj); + post_wait_for_FR (cpu, out_FRk); + post_wait_for_FR (cpu, out_FRintk); + post_wait_for_FR (cpu, dual_FRj); + post_wait_for_FR (cpu, dual_FRintj); + post_wait_for_FR (cpu, dual_FRk); + post_wait_for_FR (cpu, dual_FRintk); + restore_float_register_busy (cpu, -1, in_FRj, out_FRk, 1); + restore_float_register_busy (cpu, -1, dual_FRj, dual_FRk, 1); + restore_float_register_busy (cpu, -1, in_FRintj, out_FRintk, 1); + restore_float_register_busy (cpu, -1, dual_FRintj, dual_FRintk, 1); + + /* The latency of FRk will be at least the latency of the other inputs. */ + update_FR_latency (cpu, out_FRk, ps->post_wait); + update_FR_latency (cpu, out_FRintk, ps->post_wait); + update_FR_latency (cpu, dual_FRk, ps->post_wait); + update_FR_latency (cpu, dual_FRintk, ps->post_wait); + + /* Once initiated, post-processing will take 3 cycles. */ + update_FR_ptime (cpu, out_FRk, 3); + update_FR_ptime (cpu, out_FRintk, 3); + update_FR_ptime (cpu, dual_FRk, 3); + update_FR_ptime (cpu, dual_FRintk, 3); + + /* Mark this use of the register as a floating point op. */ + if (out_FRk >= 0) + set_use_is_fpop (cpu, out_FRk); + if (out_FRintk >= 0) + set_use_is_fpop (cpu, out_FRintk); + + return cycles; +} + +int +frvbf_model_fr500_u_media (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_FRi, INT in_FRj, INT in_ACC40Si, INT in_ACCGi, + INT out_FRk, + INT out_ACC40Sk, INT out_ACC40Uk, INT out_ACCGk) +{ + int cycles; + FRV_PROFILE_STATE *ps; + const CGEN_INSN *insn; + int is_media_s1; + int is_media_s2; + int busy_adjustment[] = {0, 0, 0}; + int *fr; + int *acc; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + return 0; + + /* The preprocessing can execute right away. */ + cycles = idesc->timing->units[unit_num].done; + + ps = CPU_PROFILE_STATE (cpu); + insn = idesc->idata; + + /* If the previous use of the registers was a media op, + then their latency will be less than previously recorded. + See Table 13-13 in the LSI. */ + if (in_FRi >= 0) + { + if (use_is_media (cpu, in_FRi)) + { + busy_adjustment[0] = 2; + decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]); + } + else + enforce_full_fr_latency (cpu, in_FRi); + } + if (in_FRj >= 0 && in_FRj != in_FRi) + { + if (use_is_media (cpu, in_FRj)) + { + busy_adjustment[1] = 2; + decrease_FR_busy (cpu, in_FRj, busy_adjustment[1]); + } + else + enforce_full_fr_latency (cpu, in_FRj); + } + if (out_FRk >= 0 && out_FRk != in_FRi && out_FRk != in_FRj) + { + if (use_is_media (cpu, out_FRk)) + { + busy_adjustment[2] = 2; + decrease_FR_busy (cpu, out_FRk, busy_adjustment[2]); + } + else + enforce_full_fr_latency (cpu, out_FRk); + } + + /* The post processing must wait if there is a dependency on a FR + which is not ready yet. */ + ps->post_wait = cycles; + post_wait_for_FR (cpu, in_FRi); + post_wait_for_FR (cpu, in_FRj); + post_wait_for_FR (cpu, out_FRk); + post_wait_for_ACC (cpu, in_ACC40Si); + post_wait_for_ACC (cpu, in_ACCGi); + post_wait_for_ACC (cpu, out_ACC40Sk); + post_wait_for_ACC (cpu, out_ACC40Uk); + post_wait_for_ACC (cpu, out_ACCGk); + + /* Restore the busy cycles of the registers we used. */ + fr = ps->fr_busy; + if (in_FRi >= 0) + fr[in_FRi] += busy_adjustment[0]; + if (in_FRj >= 0) + fr[in_FRj] += busy_adjustment[1]; + if (out_FRk >= 0) + fr[out_FRk] += busy_adjustment[2]; + + /* The latency of tht output register will be at least the latency of the + other inputs. Once initiated, post-processing will take 3 cycles. */ + if (out_FRk >= 0) + { + update_FR_latency (cpu, out_FRk, ps->post_wait); + update_FR_ptime (cpu, out_FRk, 3); + /* Mark this use of the register as a media op. */ + set_use_is_media (cpu, out_FRk); + } + /* The latency of tht output accumulator will be at least the latency of the + other inputs. Once initiated, post-processing will take 1 cycle. */ + if (out_ACC40Sk >= 0) + update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait + 1); + if (out_ACC40Uk >= 0) + update_ACC_latency (cpu, out_ACC40Uk, ps->post_wait + 1); + if (out_ACCGk >= 0) + update_ACC_latency (cpu, out_ACCGk, ps->post_wait + 1); + + return cycles; +} + +int +frvbf_model_fr500_u_media_quad_arith (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_FRi, INT in_FRj, + INT out_FRk) +{ + int cycles; + INT dual_FRi; + INT dual_FRj; + INT dual_FRk; + FRV_PROFILE_STATE *ps; + int busy_adjustment[] = {0, 0, 0, 0, 0, 0}; + int *fr; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + return 0; + + /* The preprocessing can execute right away. */ + cycles = idesc->timing->units[unit_num].done; + + ps = CPU_PROFILE_STATE (cpu); + dual_FRi = DUAL_REG (in_FRi); + dual_FRj = DUAL_REG (in_FRj); + dual_FRk = DUAL_REG (out_FRk); + + /* If the previous use of the registers was a media op, + then their latency will be less than previously recorded. + See Table 13-13 in the LSI. */ + if (use_is_media (cpu, in_FRi)) + { + busy_adjustment[0] = 2; + decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]); + } + else + enforce_full_fr_latency (cpu, in_FRi); + if (dual_FRi >= 0 && use_is_media (cpu, dual_FRi)) + { + busy_adjustment[1] = 2; + decrease_FR_busy (cpu, dual_FRi, busy_adjustment[1]); + } + else + enforce_full_fr_latency (cpu, dual_FRi); + if (in_FRj != in_FRi) + { + if (use_is_media (cpu, in_FRj)) + { + busy_adjustment[2] = 2; + decrease_FR_busy (cpu, in_FRj, busy_adjustment[2]); + } + else + enforce_full_fr_latency (cpu, in_FRj); + if (dual_FRj >= 0 && use_is_media (cpu, dual_FRj)) + { + busy_adjustment[3] = 2; + decrease_FR_busy (cpu, dual_FRj, busy_adjustment[3]); + } + else + enforce_full_fr_latency (cpu, dual_FRj + 1); + } + if (out_FRk != in_FRi && out_FRk != in_FRj) + { + if (use_is_media (cpu, out_FRk)) + { + busy_adjustment[4] = 2; + decrease_FR_busy (cpu, out_FRk, busy_adjustment[4]); + } + else + enforce_full_fr_latency (cpu, out_FRk); + if (dual_FRk >= 0 && use_is_media (cpu, dual_FRk)) + { + busy_adjustment[5] = 2; + decrease_FR_busy (cpu, dual_FRk, busy_adjustment[5]); + } + else + enforce_full_fr_latency (cpu, dual_FRk); + } + + /* The post processing must wait if there is a dependency on a FR + which is not ready yet. */ + ps->post_wait = cycles; + post_wait_for_FR (cpu, in_FRi); + post_wait_for_FR (cpu, dual_FRi); + post_wait_for_FR (cpu, in_FRj); + post_wait_for_FR (cpu, dual_FRj); + post_wait_for_FR (cpu, out_FRk); + post_wait_for_FR (cpu, dual_FRk); + + /* Restore the busy cycles of the registers we used. */ + fr = ps->fr_busy; + fr[in_FRi] += busy_adjustment[0]; + if (dual_FRi >= 0) + fr[dual_FRi] += busy_adjustment[1]; + fr[in_FRj] += busy_adjustment[2]; + if (dual_FRj >= 0) + fr[dual_FRj] += busy_adjustment[3]; + fr[out_FRk] += busy_adjustment[4]; + if (dual_FRk >= 0) + fr[dual_FRk] += busy_adjustment[5]; + + /* The latency of tht output register will be at least the latency of the + other inputs. */ + update_FR_latency (cpu, out_FRk, ps->post_wait); + + /* Once initiated, post-processing will take 3 cycles. */ + update_FR_ptime (cpu, out_FRk, 3); + + /* Mark this use of the register as a media op. */ + set_use_is_media (cpu, out_FRk); + if (dual_FRk >= 0) + { + update_FR_latency (cpu, dual_FRk, ps->post_wait); + update_FR_ptime (cpu, dual_FRk, 3); + /* Mark this use of the register as a media op. */ + set_use_is_media (cpu, dual_FRk); + } + + return cycles; +} + +int +frvbf_model_fr500_u_media_dual_mul (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_FRi, INT in_FRj, + INT out_ACC40Sk, INT out_ACC40Uk) +{ + int cycles; + INT dual_ACC40Sk; + INT dual_ACC40Uk; + FRV_PROFILE_STATE *ps; + int busy_adjustment[] = {0, 0, 0, 0, 0, 0}; + int *fr; + int *acc; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + return 0; + + /* The preprocessing can execute right away. */ + cycles = idesc->timing->units[unit_num].done; + + ps = CPU_PROFILE_STATE (cpu); + dual_ACC40Sk = DUAL_REG (out_ACC40Sk); + dual_ACC40Uk = DUAL_REG (out_ACC40Uk); + + /* If the previous use of the registers was a media op, + then their latency will be less than previously recorded. + See Table 13-13 in the LSI. */ + if (use_is_media (cpu, in_FRi)) + { + busy_adjustment[0] = 2; + decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]); + } + else + enforce_full_fr_latency (cpu, in_FRi); + if (in_FRj != in_FRi) + { + if (use_is_media (cpu, in_FRj)) + { + busy_adjustment[1] = 2; + decrease_FR_busy (cpu, in_FRj, busy_adjustment[1]); + } + else + enforce_full_fr_latency (cpu, in_FRj); + } + if (out_ACC40Sk >= 0) + { + busy_adjustment[2] = 1; + decrease_ACC_busy (cpu, out_ACC40Sk, busy_adjustment[2]); + } + if (dual_ACC40Sk >= 0) + { + busy_adjustment[3] = 1; + decrease_ACC_busy (cpu, dual_ACC40Sk, busy_adjustment[3]); + } + if (out_ACC40Uk >= 0) + { + busy_adjustment[4] = 1; + decrease_ACC_busy (cpu, out_ACC40Uk, busy_adjustment[4]); + } + if (dual_ACC40Uk >= 0) + { + busy_adjustment[5] = 1; + decrease_ACC_busy (cpu, dual_ACC40Uk, busy_adjustment[5]); + } + + /* The post processing must wait if there is a dependency on a FR + which is not ready yet. */ + ps->post_wait = cycles; + post_wait_for_FR (cpu, in_FRi); + post_wait_for_FR (cpu, in_FRj); + post_wait_for_ACC (cpu, out_ACC40Sk); + post_wait_for_ACC (cpu, dual_ACC40Sk); + post_wait_for_ACC (cpu, out_ACC40Uk); + post_wait_for_ACC (cpu, dual_ACC40Uk); + + /* Restore the busy cycles of the registers we used. */ + fr = ps->fr_busy; + acc = ps->acc_busy; + fr[in_FRi] += busy_adjustment[0]; + fr[in_FRj] += busy_adjustment[1]; + if (out_ACC40Sk >= 0) + acc[out_ACC40Sk] += busy_adjustment[2]; + if (dual_ACC40Sk >= 0) + acc[dual_ACC40Sk] += busy_adjustment[3]; + if (out_ACC40Uk >= 0) + acc[out_ACC40Uk] += busy_adjustment[4]; + if (dual_ACC40Uk >= 0) + acc[dual_ACC40Uk] += busy_adjustment[5]; + + /* The latency of tht output register will be at least the latency of the + other inputs. Once initiated, post-processing will take 1 cycle. */ + if (out_ACC40Sk >= 0) + update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait + 1); + if (dual_ACC40Sk >= 0) + update_ACC_latency (cpu, dual_ACC40Sk, ps->post_wait + 1); + if (out_ACC40Uk >= 0) + update_ACC_latency (cpu, out_ACC40Uk, ps->post_wait + 1); + if (dual_ACC40Uk >= 0) + update_ACC_latency (cpu, dual_ACC40Uk, ps->post_wait + 1); + + return cycles; +} + +int +frvbf_model_fr500_u_media_quad_mul (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_FRi, INT in_FRj, + INT out_ACC40Sk, INT out_ACC40Uk) +{ + int cycles; + INT FRi_1; + INT FRj_1; + INT ACC40Sk_1; + INT ACC40Sk_2; + INT ACC40Sk_3; + INT ACC40Uk_1; + INT ACC40Uk_2; + INT ACC40Uk_3; + FRV_PROFILE_STATE *ps; + int busy_adjustment[] = {0, 0, 0, 0, 0, 0, 0 ,0}; + int *fr; + int *acc; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + return 0; + + /* The preprocessing can execute right away. */ + cycles = idesc->timing->units[unit_num].done; + + FRi_1 = DUAL_REG (in_FRi); + FRj_1 = DUAL_REG (in_FRj); + ACC40Sk_1 = DUAL_REG (out_ACC40Sk); + ACC40Sk_2 = DUAL_REG (ACC40Sk_1); + ACC40Sk_3 = DUAL_REG (ACC40Sk_2); + ACC40Uk_1 = DUAL_REG (out_ACC40Uk); + ACC40Uk_2 = DUAL_REG (ACC40Uk_1); + ACC40Uk_3 = DUAL_REG (ACC40Uk_2); + + /* If the previous use of the registers was a media op, + then their latency will be less than previously recorded. + See Table 13-13 in the LSI. */ + ps = CPU_PROFILE_STATE (cpu); + if (use_is_media (cpu, in_FRi)) + { + busy_adjustment[0] = 2; + decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]); + } + else + enforce_full_fr_latency (cpu, in_FRi); + if (FRi_1 >= 0) + { + if (use_is_media (cpu, FRi_1)) + { + busy_adjustment[1] = 2; + decrease_FR_busy (cpu, FRi_1, busy_adjustment[1]); + } + else + enforce_full_fr_latency (cpu, FRi_1); + } + if (in_FRj != in_FRi) + { + if (use_is_media (cpu, in_FRj)) + { + busy_adjustment[2] = 2; + decrease_FR_busy (cpu, in_FRj, busy_adjustment[2]); + } + else + enforce_full_fr_latency (cpu, in_FRj); + if (FRj_1 >= 0) + { + if (use_is_media (cpu, FRj_1)) + { + busy_adjustment[3] = 2; + decrease_FR_busy (cpu, FRj_1, busy_adjustment[3]); + } + else + enforce_full_fr_latency (cpu, FRj_1); + } + } + if (out_ACC40Sk >= 0) + { + busy_adjustment[4] = 1; + decrease_ACC_busy (cpu, out_ACC40Sk, busy_adjustment[4]); + + if (ACC40Sk_1 >= 0) + { + busy_adjustment[5] = 1; + decrease_ACC_busy (cpu, ACC40Sk_1, busy_adjustment[5]); + } + if (ACC40Sk_2 >= 0) + { + busy_adjustment[6] = 1; + decrease_ACC_busy (cpu, ACC40Sk_2, busy_adjustment[6]); + } + if (ACC40Sk_3 >= 0) + { + busy_adjustment[7] = 1; + decrease_ACC_busy (cpu, ACC40Sk_3, busy_adjustment[7]); + } + } + else if (out_ACC40Uk >= 0) + { + busy_adjustment[4] = 1; + decrease_ACC_busy (cpu, out_ACC40Uk, busy_adjustment[4]); + + if (ACC40Uk_1 >= 0) + { + busy_adjustment[5] = 1; + decrease_ACC_busy (cpu, ACC40Uk_1, busy_adjustment[5]); + } + if (ACC40Uk_2 >= 0) + { + busy_adjustment[6] = 1; + decrease_ACC_busy (cpu, ACC40Uk_2, busy_adjustment[6]); + } + if (ACC40Uk_3 >= 0) + { + busy_adjustment[7] = 1; + decrease_ACC_busy (cpu, ACC40Uk_3, busy_adjustment[7]); + } + } + + /* The post processing must wait if there is a dependency on a FR + which is not ready yet. */ + ps->post_wait = cycles; + post_wait_for_FR (cpu, in_FRi); + post_wait_for_FR (cpu, FRi_1); + post_wait_for_FR (cpu, in_FRj); + post_wait_for_FR (cpu, FRj_1); + post_wait_for_ACC (cpu, out_ACC40Sk); + post_wait_for_ACC (cpu, ACC40Sk_1); + post_wait_for_ACC (cpu, ACC40Sk_2); + post_wait_for_ACC (cpu, ACC40Sk_3); + post_wait_for_ACC (cpu, out_ACC40Uk); + post_wait_for_ACC (cpu, ACC40Uk_1); + post_wait_for_ACC (cpu, ACC40Uk_2); + post_wait_for_ACC (cpu, ACC40Uk_3); + + /* Restore the busy cycles of the registers we used. */ + fr = ps->fr_busy; + acc = ps->acc_busy; + fr[in_FRi] += busy_adjustment[0]; + if (FRi_1 >= 0) + fr[FRi_1] += busy_adjustment[1]; + fr[in_FRj] += busy_adjustment[2]; + if (FRj_1 > 0) + fr[FRj_1] += busy_adjustment[3]; + if (out_ACC40Sk >= 0) + { + acc[out_ACC40Sk] += busy_adjustment[4]; + if (ACC40Sk_1 >= 0) + acc[ACC40Sk_1] += busy_adjustment[5]; + if (ACC40Sk_2 >= 0) + acc[ACC40Sk_2] += busy_adjustment[6]; + if (ACC40Sk_3 >= 0) + acc[ACC40Sk_3] += busy_adjustment[7]; + } + else if (out_ACC40Uk >= 0) + { + acc[out_ACC40Uk] += busy_adjustment[4]; + if (ACC40Uk_1 >= 0) + acc[ACC40Uk_1] += busy_adjustment[5]; + if (ACC40Uk_2 >= 0) + acc[ACC40Uk_2] += busy_adjustment[6]; + if (ACC40Uk_3 >= 0) + acc[ACC40Uk_3] += busy_adjustment[7]; + } + + /* The latency of tht output register will be at least the latency of the + other inputs. Once initiated, post-processing will take 1 cycle. */ + if (out_ACC40Sk >= 0) + { + update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait + 1); + if (ACC40Sk_1 >= 0) + update_ACC_latency (cpu, ACC40Sk_1, ps->post_wait + 1); + if (ACC40Sk_2 >= 0) + update_ACC_latency (cpu, ACC40Sk_2, ps->post_wait + 1); + if (ACC40Sk_3 >= 0) + update_ACC_latency (cpu, ACC40Sk_3, ps->post_wait + 1); + } + else if (out_ACC40Uk >= 0) + { + update_ACC_latency (cpu, out_ACC40Uk, ps->post_wait + 1); + if (ACC40Uk_1 >= 0) + update_ACC_latency (cpu, ACC40Uk_1, ps->post_wait + 1); + if (ACC40Uk_2 >= 0) + update_ACC_latency (cpu, ACC40Uk_2, ps->post_wait + 1); + if (ACC40Uk_3 >= 0) + update_ACC_latency (cpu, ACC40Uk_3, ps->post_wait + 1); + } + + return cycles; +} + +int +frvbf_model_fr500_u_media_quad_complex (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_FRi, INT in_FRj, + INT out_ACC40Sk) +{ + int cycles; + INT FRi_1; + INT FRj_1; + INT ACC40Sk_1; + FRV_PROFILE_STATE *ps; + int busy_adjustment[] = {0, 0, 0, 0, 0, 0}; + int *fr; + int *acc; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + return 0; + + /* The preprocessing can execute right away. */ + cycles = idesc->timing->units[unit_num].done; + + FRi_1 = DUAL_REG (in_FRi); + FRj_1 = DUAL_REG (in_FRj); + ACC40Sk_1 = DUAL_REG (out_ACC40Sk); + + /* If the previous use of the registers was a media op, + then their latency will be less than previously recorded. + See Table 13-13 in the LSI. */ + ps = CPU_PROFILE_STATE (cpu); + if (use_is_media (cpu, in_FRi)) + { + busy_adjustment[0] = 2; + decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]); + } + else + enforce_full_fr_latency (cpu, in_FRi); + if (FRi_1 >= 0) + { + if (use_is_media (cpu, FRi_1)) + { + busy_adjustment[1] = 2; + decrease_FR_busy (cpu, FRi_1, busy_adjustment[1]); + } + else + enforce_full_fr_latency (cpu, FRi_1); + } + if (in_FRj != in_FRi) + { + if (use_is_media (cpu, in_FRj)) + { + busy_adjustment[2] = 2; + decrease_FR_busy (cpu, in_FRj, busy_adjustment[2]); + } + else + enforce_full_fr_latency (cpu, in_FRj); + if (FRj_1 >= 0) + { + if (use_is_media (cpu, FRj_1)) + { + busy_adjustment[3] = 2; + decrease_FR_busy (cpu, FRj_1, busy_adjustment[3]); + } + else + enforce_full_fr_latency (cpu, FRj_1); + } + } + if (out_ACC40Sk >= 0) + { + busy_adjustment[4] = 1; + decrease_ACC_busy (cpu, out_ACC40Sk, busy_adjustment[4]); + + if (ACC40Sk_1 >= 0) + { + busy_adjustment[5] = 1; + decrease_ACC_busy (cpu, ACC40Sk_1, busy_adjustment[5]); + } + } + + /* The post processing must wait if there is a dependency on a FR + which is not ready yet. */ + ps->post_wait = cycles; + post_wait_for_FR (cpu, in_FRi); + post_wait_for_FR (cpu, FRi_1); + post_wait_for_FR (cpu, in_FRj); + post_wait_for_FR (cpu, FRj_1); + post_wait_for_ACC (cpu, out_ACC40Sk); + post_wait_for_ACC (cpu, ACC40Sk_1); + + /* Restore the busy cycles of the registers we used. */ + fr = ps->fr_busy; + acc = ps->acc_busy; + fr[in_FRi] += busy_adjustment[0]; + if (FRi_1 >= 0) + fr[FRi_1] += busy_adjustment[1]; + fr[in_FRj] += busy_adjustment[2]; + if (FRj_1 > 0) + fr[FRj_1] += busy_adjustment[3]; + if (out_ACC40Sk >= 0) + { + acc[out_ACC40Sk] += busy_adjustment[4]; + if (ACC40Sk_1 >= 0) + acc[ACC40Sk_1] += busy_adjustment[5]; + } + + /* The latency of tht output register will be at least the latency of the + other inputs. Once initiated, post-processing will take 1 cycle. */ + if (out_ACC40Sk >= 0) + { + update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait + 1); + if (ACC40Sk_1 >= 0) + update_ACC_latency (cpu, ACC40Sk_1, ps->post_wait + 1); + } + + return cycles; +} + +int +frvbf_model_fr500_u_media_dual_expand (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_FRi, + INT out_FRk) +{ + int cycles; + INT dual_FRk; + FRV_PROFILE_STATE *ps; + int busy_adjustment[] = {0, 0, 0}; + int *fr; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + return 0; + + /* The preprocessing can execute right away. */ + cycles = idesc->timing->units[unit_num].done; + + /* If the previous use of the registers was a media op, + then their latency will be less than previously recorded. + See Table 13-13 in the LSI. */ + dual_FRk = DUAL_REG (out_FRk); + ps = CPU_PROFILE_STATE (cpu); + if (use_is_media (cpu, in_FRi)) + { + busy_adjustment[0] = 2; + decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]); + } + else + enforce_full_fr_latency (cpu, in_FRi); + if (out_FRk != in_FRi) + { + if (use_is_media (cpu, out_FRk)) + { + busy_adjustment[1] = 2; + decrease_FR_busy (cpu, out_FRk, busy_adjustment[1]); + } + else + enforce_full_fr_latency (cpu, out_FRk); + } + if (dual_FRk >= 0 && dual_FRk != in_FRi) + { + if (use_is_media (cpu, dual_FRk)) + { + busy_adjustment[2] = 2; + decrease_FR_busy (cpu, dual_FRk, busy_adjustment[2]); + } + else + enforce_full_fr_latency (cpu, dual_FRk); + } + + /* The post processing must wait if there is a dependency on a FR + which is not ready yet. */ + ps->post_wait = cycles; + post_wait_for_FR (cpu, in_FRi); + post_wait_for_FR (cpu, out_FRk); + post_wait_for_FR (cpu, dual_FRk); + + /* Restore the busy cycles of the registers we used. */ + fr = ps->fr_busy; + fr[in_FRi] += busy_adjustment[0]; + fr[out_FRk] += busy_adjustment[1]; + if (dual_FRk >= 0) + fr[dual_FRk] += busy_adjustment[2]; + + /* The latency of the output register will be at least the latency of the + other inputs. Once initiated, post-processing will take 3 cycles. */ + update_FR_latency (cpu, out_FRk, ps->post_wait); + update_FR_ptime (cpu, out_FRk, 3); + + /* Mark this use of the register as a media op. */ + set_use_is_media (cpu, out_FRk); + if (dual_FRk >= 0) + { + update_FR_latency (cpu, dual_FRk, ps->post_wait); + update_FR_ptime (cpu, dual_FRk, 3); + + /* Mark this use of the register as a media op. */ + set_use_is_media (cpu, dual_FRk); + } + + return cycles; +} + +int +frvbf_model_fr500_u_media_dual_unpack (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_FRi, + INT out_FRk) +{ + int cycles; + INT FRi_1; + INT FRk_1; + INT FRk_2; + INT FRk_3; + FRV_PROFILE_STATE *ps; + int busy_adjustment[] = {0, 0, 0, 0, 0, 0}; + int *fr; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + return 0; + + /* The preprocessing can execute right away. */ + cycles = idesc->timing->units[unit_num].done; + + FRi_1 = DUAL_REG (in_FRi); + FRk_1 = DUAL_REG (out_FRk); + FRk_2 = DUAL_REG (FRk_1); + FRk_3 = DUAL_REG (FRk_2); + + /* If the previous use of the registers was a media op, + then their latency will be less than previously recorded. + See Table 13-13 in the LSI. */ + ps = CPU_PROFILE_STATE (cpu); + if (use_is_media (cpu, in_FRi)) + { + busy_adjustment[0] = 2; + decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]); + } + else + enforce_full_fr_latency (cpu, in_FRi); + if (FRi_1 >= 0 && use_is_media (cpu, FRi_1)) + { + busy_adjustment[1] = 2; + decrease_FR_busy (cpu, FRi_1, busy_adjustment[1]); + } + else + enforce_full_fr_latency (cpu, FRi_1); + if (out_FRk != in_FRi) + { + if (use_is_media (cpu, out_FRk)) + { + busy_adjustment[2] = 2; + decrease_FR_busy (cpu, out_FRk, busy_adjustment[2]); + } + else + enforce_full_fr_latency (cpu, out_FRk); + if (FRk_1 >= 0 && FRk_1 != in_FRi) + { + if (use_is_media (cpu, FRk_1)) + { + busy_adjustment[3] = 2; + decrease_FR_busy (cpu, FRk_1, busy_adjustment[3]); + } + else + enforce_full_fr_latency (cpu, FRk_1); + } + if (FRk_2 >= 0 && FRk_2 != in_FRi) + { + if (use_is_media (cpu, FRk_2)) + { + busy_adjustment[4] = 2; + decrease_FR_busy (cpu, FRk_2, busy_adjustment[4]); + } + else + enforce_full_fr_latency (cpu, FRk_2); + } + if (FRk_3 >= 0 && FRk_3 != in_FRi) + { + if (use_is_media (cpu, FRk_3)) + { + busy_adjustment[5] = 2; + decrease_FR_busy (cpu, FRk_3, busy_adjustment[5]); + } + else + enforce_full_fr_latency (cpu, FRk_3); + } + } + + /* The post processing must wait if there is a dependency on a FR + which is not ready yet. */ + ps->post_wait = cycles; + post_wait_for_FR (cpu, in_FRi); + post_wait_for_FR (cpu, FRi_1); + post_wait_for_FR (cpu, out_FRk); + post_wait_for_FR (cpu, FRk_1); + post_wait_for_FR (cpu, FRk_2); + post_wait_for_FR (cpu, FRk_3); + + /* Restore the busy cycles of the registers we used. */ + fr = ps->fr_busy; + fr[in_FRi] += busy_adjustment[0]; + if (FRi_1 >= 0) + fr[FRi_1] += busy_adjustment[1]; + fr[out_FRk] += busy_adjustment[2]; + if (FRk_1 >= 0) + fr[FRk_1] += busy_adjustment[3]; + if (FRk_2 >= 0) + fr[FRk_2] += busy_adjustment[4]; + if (FRk_3 >= 0) + fr[FRk_3] += busy_adjustment[5]; + + /* The latency of tht output register will be at least the latency of the + other inputs. Once initiated, post-processing will take 3 cycles. */ + update_FR_latency (cpu, out_FRk, ps->post_wait); + update_FR_ptime (cpu, out_FRk, 3); + + /* Mark this use of the register as a media op. */ + set_use_is_media (cpu, out_FRk); + if (FRk_1 >= 0) + { + update_FR_latency (cpu, FRk_1, ps->post_wait); + update_FR_ptime (cpu, FRk_1, 3); + + /* Mark this use of the register as a media op. */ + set_use_is_media (cpu, FRk_1); + } + if (FRk_2 >= 0) + { + update_FR_latency (cpu, FRk_2, ps->post_wait); + update_FR_ptime (cpu, FRk_2, 3); + + /* Mark this use of the register as a media op. */ + set_use_is_media (cpu, FRk_2); + } + if (FRk_3 >= 0) + { + update_FR_latency (cpu, FRk_3, ps->post_wait); + update_FR_ptime (cpu, FRk_3, 3); + + /* Mark this use of the register as a media op. */ + set_use_is_media (cpu, FRk_3); + } + + return cycles; +} + +int +frvbf_model_fr500_u_media_dual_btoh (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_FRj, + INT out_FRk) +{ + return frvbf_model_fr500_u_media_dual_expand (cpu, idesc, unit_num, + referenced, in_FRj, out_FRk); +} + +int +frvbf_model_fr500_u_media_dual_htob (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_FRj, + INT out_FRk) +{ + int cycles; + INT dual_FRj; + FRV_PROFILE_STATE *ps; + int busy_adjustment[] = {0, 0, 0}; + int *fr; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + return 0; + + /* The preprocessing can execute right away. */ + cycles = idesc->timing->units[unit_num].done; + + /* If the previous use of the registers was a media op, + then their latency will be less than previously recorded. + See Table 13-13 in the LSI. */ + dual_FRj = DUAL_REG (in_FRj); + ps = CPU_PROFILE_STATE (cpu); + if (use_is_media (cpu, in_FRj)) + { + busy_adjustment[0] = 2; + decrease_FR_busy (cpu, in_FRj, busy_adjustment[0]); + } + else + enforce_full_fr_latency (cpu, in_FRj); + if (dual_FRj >= 0) + { + if (use_is_media (cpu, dual_FRj)) + { + busy_adjustment[1] = 2; + decrease_FR_busy (cpu, dual_FRj, busy_adjustment[1]); + } + else + enforce_full_fr_latency (cpu, dual_FRj); + } + if (out_FRk != in_FRj) + { + if (use_is_media (cpu, out_FRk)) + { + busy_adjustment[2] = 2; + decrease_FR_busy (cpu, out_FRk, busy_adjustment[2]); + } + else + enforce_full_fr_latency (cpu, out_FRk); + } + + /* The post processing must wait if there is a dependency on a FR + which is not ready yet. */ + ps->post_wait = cycles; + post_wait_for_FR (cpu, in_FRj); + post_wait_for_FR (cpu, dual_FRj); + post_wait_for_FR (cpu, out_FRk); + + /* Restore the busy cycles of the registers we used. */ + fr = ps->fr_busy; + fr[in_FRj] += busy_adjustment[0]; + if (dual_FRj >= 0) + fr[dual_FRj] += busy_adjustment[1]; + fr[out_FRk] += busy_adjustment[2]; + + /* The latency of tht output register will be at least the latency of the + other inputs. */ + update_FR_latency (cpu, out_FRk, ps->post_wait); + + /* Once initiated, post-processing will take 3 cycles. */ + update_FR_ptime (cpu, out_FRk, 3); + + /* Mark this use of the register as a media op. */ + set_use_is_media (cpu, out_FRk); + + return cycles; +} + +int +frvbf_model_fr500_u_media_dual_btohe (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_FRj, + INT out_FRk) +{ + int cycles; + INT FRk_1; + INT FRk_2; + INT FRk_3; + FRV_PROFILE_STATE *ps; + int busy_adjustment[] = {0, 0, 0, 0, 0}; + int *fr; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + return 0; + + /* The preprocessing can execute right away. */ + cycles = idesc->timing->units[unit_num].done; + + FRk_1 = DUAL_REG (out_FRk); + FRk_2 = DUAL_REG (FRk_1); + FRk_3 = DUAL_REG (FRk_2); + + /* If the previous use of the registers was a media op, + then their latency will be less than previously recorded. + See Table 13-13 in the LSI. */ + ps = CPU_PROFILE_STATE (cpu); + if (use_is_media (cpu, in_FRj)) + { + busy_adjustment[0] = 2; + decrease_FR_busy (cpu, in_FRj, busy_adjustment[0]); + } + else + enforce_full_fr_latency (cpu, in_FRj); + if (out_FRk != in_FRj) + { + if (use_is_media (cpu, out_FRk)) + { + busy_adjustment[1] = 2; + decrease_FR_busy (cpu, out_FRk, busy_adjustment[1]); + } + else + enforce_full_fr_latency (cpu, out_FRk); + if (FRk_1 >= 0 && FRk_1 != in_FRj) + { + if (use_is_media (cpu, FRk_1)) + { + busy_adjustment[2] = 2; + decrease_FR_busy (cpu, FRk_1, busy_adjustment[2]); + } + else + enforce_full_fr_latency (cpu, FRk_1); + } + if (FRk_2 >= 0 && FRk_2 != in_FRj) + { + if (use_is_media (cpu, FRk_2)) + { + busy_adjustment[3] = 2; + decrease_FR_busy (cpu, FRk_2, busy_adjustment[3]); + } + else + enforce_full_fr_latency (cpu, FRk_2); + } + if (FRk_3 >= 0 && FRk_3 != in_FRj) + { + if (use_is_media (cpu, FRk_3)) + { + busy_adjustment[4] = 2; + decrease_FR_busy (cpu, FRk_3, busy_adjustment[4]); + } + else + enforce_full_fr_latency (cpu, FRk_3); + } + } + + /* The post processing must wait if there is a dependency on a FR + which is not ready yet. */ + ps->post_wait = cycles; + post_wait_for_FR (cpu, in_FRj); + post_wait_for_FR (cpu, out_FRk); + post_wait_for_FR (cpu, FRk_1); + post_wait_for_FR (cpu, FRk_2); + post_wait_for_FR (cpu, FRk_3); + + /* Restore the busy cycles of the registers we used. */ + fr = ps->fr_busy; + fr[in_FRj] += busy_adjustment[0]; + fr[out_FRk] += busy_adjustment[1]; + if (FRk_1 >= 0) + fr[FRk_1] += busy_adjustment[2]; + if (FRk_2 >= 0) + fr[FRk_2] += busy_adjustment[3]; + if (FRk_3 >= 0) + fr[FRk_3] += busy_adjustment[4]; + + /* The latency of tht output register will be at least the latency of the + other inputs. Once initiated, post-processing will take 3 cycles. */ + update_FR_latency (cpu, out_FRk, ps->post_wait); + update_FR_ptime (cpu, out_FRk, 3); + + /* Mark this use of the register as a media op. */ + set_use_is_media (cpu, out_FRk); + if (FRk_1 >= 0) + { + update_FR_latency (cpu, FRk_1, ps->post_wait); + update_FR_ptime (cpu, FRk_1, 3); + + /* Mark this use of the register as a media op. */ + set_use_is_media (cpu, FRk_1); + } + if (FRk_2 >= 0) + { + update_FR_latency (cpu, FRk_2, ps->post_wait); + update_FR_ptime (cpu, FRk_2, 3); + + /* Mark this use of the register as a media op. */ + set_use_is_media (cpu, FRk_2); + } + if (FRk_3 >= 0) + { + update_FR_latency (cpu, FRk_3, ps->post_wait); + update_FR_ptime (cpu, FRk_3, 3); + + /* Mark this use of the register as a media op. */ + set_use_is_media (cpu, FRk_3); + } + + return cycles; +} + +int +frvbf_model_fr500_u_barrier (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced) +{ + int cycles; + if (model_insn == FRV_INSN_MODEL_PASS_1) + { + int i; + /* Wait for ALL resources. */ + for (i = 0; i < 64; ++i) + { + enforce_full_fr_latency (cpu, i); + vliw_wait_for_GR (cpu, i); + vliw_wait_for_FR (cpu, i); + vliw_wait_for_ACC (cpu, i); + } + for (i = 0; i < 8; ++i) + vliw_wait_for_CCR (cpu, i); + for (i = 0; i < 2; ++i) + { + vliw_wait_for_idiv_resource (cpu, i); + vliw_wait_for_fdiv_resource (cpu, i); + vliw_wait_for_fsqrt_resource (cpu, i); + } + handle_resource_wait (cpu); + for (i = 0; i < 64; ++i) + { + load_wait_for_GR (cpu, i); + load_wait_for_FR (cpu, i); + } + trace_vliw_wait_cycles (cpu); + return 0; + } + + cycles = idesc->timing->units[unit_num].done; + return cycles; +} + +int +frvbf_model_fr500_u_membar (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced) +{ + int cycles; + if (model_insn == FRV_INSN_MODEL_PASS_1) + { + int i; + /* Wait for ALL resources, except GR and ICC. */ + for (i = 0; i < 64; ++i) + { + enforce_full_fr_latency (cpu, i); + vliw_wait_for_FR (cpu, i); + vliw_wait_for_ACC (cpu, i); + } + for (i = 0; i < 4; ++i) + vliw_wait_for_CCR (cpu, i); + for (i = 0; i < 2; ++i) + { + vliw_wait_for_idiv_resource (cpu, i); + vliw_wait_for_fdiv_resource (cpu, i); + vliw_wait_for_fsqrt_resource (cpu, i); + } + handle_resource_wait (cpu); + for (i = 0; i < 64; ++i) + { + load_wait_for_FR (cpu, i); + } + trace_vliw_wait_cycles (cpu); + return 0; + } + + cycles = idesc->timing->units[unit_num].done; + return cycles; +} + +/* The frv machine is a fictional implementation of the fr500 which implements + all frv architectural features. */ +int +frvbf_model_frv_u_exec (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced) +{ + return idesc->timing->units[unit_num].done; +} + +/* The simple machine is a fictional implementation of the fr500 which + implements limited frv architectural features. */ +int +frvbf_model_simple_u_exec (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced) +{ + return idesc->timing->units[unit_num].done; +} + +/* The tomcat machine is models a prototype fr500 machine which had a few + bugs and restrictions to work around. */ +int +frvbf_model_tomcat_u_exec (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced) +{ + return idesc->timing->units[unit_num].done; +} + +#endif /* WITH_PROFILE_MODEL_P */ diff --git a/sim/frv/profile-fr500.h b/sim/frv/profile-fr500.h new file mode 100644 index 0000000..6b3c629 --- /dev/null +++ b/sim/frv/profile-fr500.h @@ -0,0 +1,30 @@ +/* Profiling definitions for the fr500 model of the FRV simulator + Copyright (C) 1998, 1999, 2000, 2001 Free Software Foundation, Inc. + Contributed by Red Hat. + +This file is part of the GNU Simulators. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef PROFILE_FR500_H +#define PROFILE_FR500_H + +void fr500_model_insn_before (SIM_CPU *, int); +void fr500_model_insn_after (SIM_CPU *, int, int); + +void fr500_reset_fr_flags (SIM_CPU *, INT); +void fr500_reset_cc_flags (SIM_CPU *, INT); + +#endif /* PROFILE_FR500_H */ diff --git a/sim/frv/profile-fr550.c b/sim/frv/profile-fr550.c new file mode 100644 index 0000000..c92cf97 --- /dev/null +++ b/sim/frv/profile-fr550.c @@ -0,0 +1,2664 @@ +/* frv simulator fr550 dependent profiling code. + + Copyright (C) 2003 Free Software Foundation, Inc. + Contributed by Red Hat + +This file is part of the GNU simulators. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +*/ +#define WANT_CPU +#define WANT_CPU_FRVBF + +#include "sim-main.h" +#include "bfd.h" + +#if WITH_PROFILE_MODEL_P + +#include "profile.h" +#include "profile-fr550.h" + +/* Initialize cycle counting for an insn. + FIRST_P is non-zero if this is the first insn in a set of parallel + insns. */ +void +fr550_model_insn_before (SIM_CPU *cpu, int first_p) +{ + if (first_p) + { + MODEL_FR550_DATA *d = CPU_MODEL_DATA (cpu); + d->cur_fr_load = d->prev_fr_load; + d->cur_fr_complex_1 = d->prev_fr_complex_1; + d->cur_fr_complex_2 = d->prev_fr_complex_2; + d->cur_ccr_complex = d->prev_ccr_complex; + d->cur_acc_mmac = d->prev_acc_mmac; + } +} + +/* Record the cycles computed for an insn. + LAST_P is non-zero if this is the last insn in a set of parallel insns, + and we update the total cycle count. + CYCLES is the cycle count of the insn. */ +void +fr550_model_insn_after (SIM_CPU *cpu, int last_p, int cycles) +{ + if (last_p) + { + MODEL_FR550_DATA *d = CPU_MODEL_DATA (cpu); + d->prev_fr_load = d->cur_fr_load; + d->prev_fr_complex_1 = d->cur_fr_complex_1; + d->prev_fr_complex_2 = d->cur_fr_complex_2; + d->prev_ccr_complex = d->cur_ccr_complex; + d->prev_acc_mmac = d->cur_acc_mmac; + } +} + +static void fr550_reset_fr_flags (SIM_CPU *cpu, INT fr); +static void fr550_reset_ccr_flags (SIM_CPU *cpu, INT ccr); +static void fr550_reset_acc_flags (SIM_CPU *cpu, INT acc); + +static void +set_use_is_fr_load (SIM_CPU *cpu, INT fr) +{ + MODEL_FR550_DATA *d = CPU_MODEL_DATA (cpu); + fr550_reset_fr_flags (cpu, (fr)); + d->cur_fr_load |= (((DI)1) << (fr)); +} + +static void +set_use_not_fr_load (SIM_CPU *cpu, INT fr) +{ + MODEL_FR550_DATA *d = CPU_MODEL_DATA (cpu); + d->cur_fr_load &= ~(((DI)1) << (fr)); +} + +static int +use_is_fr_load (SIM_CPU *cpu, INT fr) +{ + MODEL_FR550_DATA *d = CPU_MODEL_DATA (cpu); + return d->prev_fr_load & (((DI)1) << (fr)); +} + +static void +set_use_is_fr_complex_1 (SIM_CPU *cpu, INT fr) +{ + MODEL_FR550_DATA *d = CPU_MODEL_DATA (cpu); + fr550_reset_fr_flags (cpu, (fr)); + d->cur_fr_complex_1 |= (((DI)1) << (fr)); +} + +static void +set_use_not_fr_complex_1 (SIM_CPU *cpu, INT fr) +{ + MODEL_FR550_DATA *d = CPU_MODEL_DATA (cpu); + d->cur_fr_complex_1 &= ~(((DI)1) << (fr)); +} + +static int +use_is_fr_complex_1 (SIM_CPU *cpu, INT fr) +{ + MODEL_FR550_DATA *d = CPU_MODEL_DATA (cpu); + return d->prev_fr_complex_1 & (((DI)1) << (fr)); +} + +static void +set_use_is_fr_complex_2 (SIM_CPU *cpu, INT fr) +{ + MODEL_FR550_DATA *d = CPU_MODEL_DATA (cpu); + fr550_reset_fr_flags (cpu, (fr)); + d->cur_fr_complex_2 |= (((DI)1) << (fr)); +} + +static void +set_use_not_fr_complex_2 (SIM_CPU *cpu, INT fr) +{ + MODEL_FR550_DATA *d = CPU_MODEL_DATA (cpu); + d->cur_fr_complex_2 &= ~(((DI)1) << (fr)); +} + +static int +use_is_fr_complex_2 (SIM_CPU *cpu, INT fr) +{ + MODEL_FR550_DATA *d = CPU_MODEL_DATA (cpu); + return d->prev_fr_complex_2 & (((DI)1) << (fr)); +} + +static void +set_use_is_ccr_complex (SIM_CPU *cpu, INT ccr) +{ + MODEL_FR550_DATA *d = CPU_MODEL_DATA (cpu); + fr550_reset_ccr_flags (cpu, (ccr)); + d->cur_ccr_complex |= (((SI)1) << (ccr)); +} + +static void +set_use_not_ccr_complex (SIM_CPU *cpu, INT ccr) +{ + MODEL_FR550_DATA *d = CPU_MODEL_DATA (cpu); + d->cur_ccr_complex &= ~(((SI)1) << (ccr)); +} + +static int +use_is_ccr_complex (SIM_CPU *cpu, INT ccr) +{ + MODEL_FR550_DATA *d = CPU_MODEL_DATA (cpu); + return d->prev_ccr_complex & (((SI)1) << (ccr)); +} + +static void +set_use_is_acc_mmac (SIM_CPU *cpu, INT acc) +{ + MODEL_FR550_DATA *d = CPU_MODEL_DATA (cpu); + fr550_reset_acc_flags (cpu, (acc)); + d->cur_acc_mmac |= (((DI)1) << (acc)); +} + +static void +set_use_not_acc_mmac (SIM_CPU *cpu, INT acc) +{ + MODEL_FR550_DATA *d = CPU_MODEL_DATA (cpu); + d->cur_acc_mmac &= ~(((DI)1) << (acc)); +} + +static int +use_is_acc_mmac (SIM_CPU *cpu, INT acc) +{ + MODEL_FR550_DATA *d = CPU_MODEL_DATA (cpu); + return d->prev_acc_mmac & (((DI)1) << (acc)); +} + +static void +fr550_reset_fr_flags (SIM_CPU *cpu, INT fr) +{ + set_use_not_fr_load (cpu, fr); + set_use_not_fr_complex_1 (cpu, fr); + set_use_not_fr_complex_2 (cpu, fr); +} + +static void +fr550_reset_ccr_flags (SIM_CPU *cpu, INT ccr) +{ + set_use_not_ccr_complex (cpu, ccr); +} + +static void +fr550_reset_acc_flags (SIM_CPU *cpu, INT acc) +{ + set_use_not_acc_mmac (cpu, acc); +} + +/* Detect overlap between two register ranges. Works if one of the registers + is -1 with width 1 (i.e. undefined), but not both. */ +#define REG_OVERLAP(r1, w1, r2, w2) ( \ + (r1) + (w1) - 1 >= (r2) && (r2) + (w2) - 1 >= (r1) \ +) + +/* Latency of floating point registers may be less than recorded when followed + by another floating point insn. */ +static void +adjust_float_register_busy (SIM_CPU *cpu, + INT in_FRi, int iwidth, + INT in_FRj, int jwidth, + INT out_FRk, int kwidth) +{ + int i; + /* The latency of FRk may be less than previously recorded. + See Table 14-15 in the LSI. */ + if (in_FRi >= 0) + { + for (i = 0; i < iwidth; ++i) + { + if (! REG_OVERLAP (in_FRi + i, 1, out_FRk, kwidth)) + if (use_is_fr_load (cpu, in_FRi + i)) + decrease_FR_busy (cpu, in_FRi + i, 1); + else + enforce_full_fr_latency (cpu, in_FRi + i); + } + } + + if (in_FRj >= 0) + { + for (i = 0; i < jwidth; ++i) + { + if (! REG_OVERLAP (in_FRj + i, 1, in_FRi, iwidth) + && ! REG_OVERLAP (in_FRj + i, 1, out_FRk, kwidth)) + if (use_is_fr_load (cpu, in_FRj + i)) + decrease_FR_busy (cpu, in_FRj + i, 1); + else + enforce_full_fr_latency (cpu, in_FRj + i); + } + } + + if (out_FRk >= 0) + { + for (i = 0; i < kwidth; ++i) + { + if (! REG_OVERLAP (out_FRk + i, 1, in_FRi, iwidth) + && ! REG_OVERLAP (out_FRk + i, 1, in_FRj, jwidth)) + { + if (use_is_fr_complex_1 (cpu, out_FRk + i)) + decrease_FR_busy (cpu, out_FRk + i, 1); + else if (use_is_fr_complex_2 (cpu, out_FRk + i)) + decrease_FR_busy (cpu, out_FRk + i, 2); + else + enforce_full_fr_latency (cpu, out_FRk + i); + } + } + } +} + +static void +restore_float_register_busy (SIM_CPU *cpu, + INT in_FRi, int iwidth, + INT in_FRj, int jwidth, + INT out_FRk, int kwidth) +{ + int i; + /* The latency of FRk may be less than previously recorded. + See Table 14-15 in the LSI. */ + if (in_FRi >= 0) + { + for (i = 0; i < iwidth; ++i) + { + if (! REG_OVERLAP (in_FRi + i, 1, out_FRk, kwidth)) + if (use_is_fr_load (cpu, in_FRi + i)) + increase_FR_busy (cpu, in_FRi + i, 1); + } + } + + if (in_FRj >= 0) + { + for (i = 0; i < jwidth; ++i) + { + if (! REG_OVERLAP (in_FRj + i, 1, in_FRi, iwidth) + && ! REG_OVERLAP (in_FRj + i, 1, out_FRk, kwidth)) + if (use_is_fr_load (cpu, in_FRj + i)) + increase_FR_busy (cpu, in_FRj + i, 1); + } + } + + if (out_FRk >= 0) + { + for (i = 0; i < kwidth; ++i) + { + if (! REG_OVERLAP (out_FRk + i, 1, in_FRi, iwidth) + && ! REG_OVERLAP (out_FRk + i, 1, in_FRj, jwidth)) + { + if (use_is_fr_complex_1 (cpu, out_FRk + i)) + increase_FR_busy (cpu, out_FRk + i, 1); + else if (use_is_fr_complex_2 (cpu, out_FRk + i)) + increase_FR_busy (cpu, out_FRk + i, 2); + } + } + } +} + +/* Latency of floating point registers may be less than recorded when used in a + media insns and followed by another media insn. */ +static void +adjust_float_register_busy_for_media (SIM_CPU *cpu, + INT in_FRi, int iwidth, + INT in_FRj, int jwidth, + INT out_FRk, int kwidth) +{ + int i; + /* The latency of FRk may be less than previously recorded. + See Table 14-15 in the LSI. */ + if (out_FRk >= 0) + { + for (i = 0; i < kwidth; ++i) + { + if (! REG_OVERLAP (out_FRk + i, 1, in_FRi, iwidth) + && ! REG_OVERLAP (out_FRk + i, 1, in_FRj, jwidth)) + { + if (use_is_fr_complex_1 (cpu, out_FRk + i)) + decrease_FR_busy (cpu, out_FRk + i, 1); + else + enforce_full_fr_latency (cpu, out_FRk + i); + } + } + } +} + +static void +restore_float_register_busy_for_media (SIM_CPU *cpu, + INT in_FRi, int iwidth, + INT in_FRj, int jwidth, + INT out_FRk, int kwidth) +{ + int i; + if (out_FRk >= 0) + { + for (i = 0; i < kwidth; ++i) + { + if (! REG_OVERLAP (out_FRk + i, 1, in_FRi, iwidth) + && ! REG_OVERLAP (out_FRk + i, 1, in_FRj, jwidth)) + { + if (use_is_fr_complex_1 (cpu, out_FRk + i)) + increase_FR_busy (cpu, out_FRk + i, 1); + } + } + } +} + +/* Latency of accumulator registers may be less than recorded when used in a + media insns and followed by another media insn. */ +static void +adjust_acc_busy_for_mmac (SIM_CPU *cpu, + INT in_ACC, int inwidth, + INT out_ACC, int outwidth) +{ + int i; + /* The latency of an accumulator may be less than previously recorded. + See Table 14-15 in the LSI. */ + if (in_ACC >= 0) + { + for (i = 0; i < inwidth; ++i) + { + if (use_is_acc_mmac (cpu, in_ACC + i)) + decrease_ACC_busy (cpu, in_ACC + i, 1); + else + enforce_full_acc_latency (cpu, in_ACC + i); + } + } + if (out_ACC >= 0) + { + for (i = 0; i < outwidth; ++i) + { + if (! REG_OVERLAP (out_ACC + i, 1, in_ACC, inwidth)) + { + if (use_is_acc_mmac (cpu, out_ACC + i)) + decrease_ACC_busy (cpu, out_ACC + i, 1); + else + enforce_full_acc_latency (cpu, out_ACC + i); + } + } + } +} + +static void +restore_acc_busy_for_mmac (SIM_CPU *cpu, + INT in_ACC, int inwidth, + INT out_ACC, int outwidth) +{ + int i; + if (in_ACC >= 0) + { + for (i = 0; i < inwidth; ++i) + { + if (use_is_acc_mmac (cpu, in_ACC + i)) + increase_ACC_busy (cpu, in_ACC + i, 1); + } + } + if (out_ACC >= 0) + { + for (i = 0; i < outwidth; ++i) + { + if (! REG_OVERLAP (out_ACC + i, 1, in_ACC, inwidth)) + { + if (use_is_acc_mmac (cpu, out_ACC + i)) + increase_ACC_busy (cpu, out_ACC + i, 1); + } + } + } +} + +int +frvbf_model_fr550_u_exec (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced) +{ + return idesc->timing->units[unit_num].done; +} + +int +frvbf_model_fr550_u_integer (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRi, INT in_GRj, INT out_GRk, + INT out_ICCi_1) +{ + int cycles; + + /* icc0-icc4 are the upper 4 fields of the CCR. */ + if (out_ICCi_1 >= 0) + out_ICCi_1 += 4; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + { + /* The entire VLIW insn must wait if there is a dependency on a register + which is not ready yet. */ + vliw_wait_for_GR (cpu, in_GRi); + vliw_wait_for_GR (cpu, in_GRj); + vliw_wait_for_GR (cpu, out_GRk); + vliw_wait_for_CCR (cpu, out_ICCi_1); + handle_resource_wait (cpu); + load_wait_for_GR (cpu, in_GRi); + load_wait_for_GR (cpu, in_GRj); + load_wait_for_GR (cpu, out_GRk); + trace_vliw_wait_cycles (cpu); + return 0; + } + + fr550_reset_ccr_flags (cpu, out_ICCi_1); + + /* GRk is available immediately to the next VLIW insn as is ICCi_1. */ + cycles = idesc->timing->units[unit_num].done; + return cycles; +} + +int +frvbf_model_fr550_u_imul (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRi, INT in_GRj, INT out_GRk, INT out_ICCi_1) +{ + int cycles; + /* icc0-icc4 are the upper 4 fields of the CCR. */ + if (out_ICCi_1 >= 0) + out_ICCi_1 += 4; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + { + /* The entire VLIW insn must wait if there is a dependency on a register + which is not ready yet. */ + vliw_wait_for_GR (cpu, in_GRi); + vliw_wait_for_GR (cpu, in_GRj); + vliw_wait_for_GRdouble (cpu, out_GRk); + vliw_wait_for_CCR (cpu, out_ICCi_1); + handle_resource_wait (cpu); + load_wait_for_GR (cpu, in_GRi); + load_wait_for_GR (cpu, in_GRj); + load_wait_for_GRdouble (cpu, out_GRk); + trace_vliw_wait_cycles (cpu); + return 0; + } + + /* GRk has a latency of 1 cycles. */ + cycles = idesc->timing->units[unit_num].done; + update_GRdouble_latency (cpu, out_GRk, cycles + 1); + + /* ICCi_1 has a latency of 1 cycle. */ + update_CCR_latency (cpu, out_ICCi_1, cycles + 1); + + fr550_reset_ccr_flags (cpu, out_ICCi_1); + + return cycles; +} + +int +frvbf_model_fr550_u_idiv (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRi, INT in_GRj, INT out_GRk, INT out_ICCi_1) +{ + int cycles; + FRV_VLIW *vliw; + int slot; + + /* icc0-icc4 are the upper 4 fields of the CCR. */ + if (out_ICCi_1 >= 0) + out_ICCi_1 += 4; + + vliw = CPU_VLIW (cpu); + slot = vliw->next_slot - 1; + slot = (*vliw->current_vliw)[slot] - UNIT_I0; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + { + /* The entire VLIW insn must wait if there is a dependency on a register + which is not ready yet. */ + vliw_wait_for_GR (cpu, in_GRi); + vliw_wait_for_GR (cpu, in_GRj); + vliw_wait_for_GR (cpu, out_GRk); + vliw_wait_for_CCR (cpu, out_ICCi_1); + vliw_wait_for_idiv_resource (cpu, slot); + handle_resource_wait (cpu); + load_wait_for_GR (cpu, in_GRi); + load_wait_for_GR (cpu, in_GRj); + load_wait_for_GR (cpu, out_GRk); + trace_vliw_wait_cycles (cpu); + return 0; + } + + /* GRk has a latency of 18 cycles! */ + cycles = idesc->timing->units[unit_num].done; + update_GR_latency (cpu, out_GRk, cycles + 18); + + /* ICCi_1 has a latency of 18 cycles. */ + update_CCR_latency (cpu, out_ICCi_1, cycles + 18); + + if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) + { + /* GNER has a latency of 18 cycles. */ + update_SPR_latency (cpu, GNER_FOR_GR (out_GRk), cycles + 18); + } + + /* the idiv resource has a latency of 18 cycles! */ + update_idiv_resource_latency (cpu, slot, cycles + 18); + + fr550_reset_ccr_flags (cpu, out_ICCi_1); + + return cycles; +} + +int +frvbf_model_fr550_u_branch (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRi, INT in_GRj, + INT in_ICCi_2, INT in_FCCi_2) +{ + int cycles; + FRV_PROFILE_STATE *ps; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + { + /* icc0-icc4 are the upper 4 fields of the CCR. */ + if (in_ICCi_2 >= 0) + in_ICCi_2 += 4; + + /* The entire VLIW insn must wait if there is a dependency on a register + which is not ready yet. */ + vliw_wait_for_GR (cpu, in_GRi); + vliw_wait_for_GR (cpu, in_GRj); + vliw_wait_for_CCR (cpu, in_ICCi_2); + vliw_wait_for_CCR (cpu, in_FCCi_2); + handle_resource_wait (cpu); + load_wait_for_GR (cpu, in_GRi); + load_wait_for_GR (cpu, in_GRj); + trace_vliw_wait_cycles (cpu); + return 0; + } + + /* When counting branches taken or not taken, don't consider branches after + the first taken branch in a vliw insn. */ + ps = CPU_PROFILE_STATE (cpu); + if (! ps->vliw_branch_taken) + { + /* (1 << 4): The pc is the 5th element in inputs, outputs. + ??? can be cleaned up */ + PROFILE_DATA *p = CPU_PROFILE_DATA (cpu); + int taken = (referenced & (1 << 4)) != 0; + if (taken) + { + ++PROFILE_MODEL_TAKEN_COUNT (p); + ps->vliw_branch_taken = 1; + } + else + ++PROFILE_MODEL_UNTAKEN_COUNT (p); + } + + cycles = idesc->timing->units[unit_num].done; + return cycles; +} + +int +frvbf_model_fr550_u_trap (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRi, INT in_GRj, + INT in_ICCi_2, INT in_FCCi_2) +{ + int cycles; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + { + /* icc0-icc4 are the upper 4 fields of the CCR. */ + if (in_ICCi_2 >= 0) + in_ICCi_2 += 4; + + /* The entire VLIW insn must wait if there is a dependency on a register + which is not ready yet. */ + vliw_wait_for_GR (cpu, in_GRi); + vliw_wait_for_GR (cpu, in_GRj); + vliw_wait_for_CCR (cpu, in_ICCi_2); + vliw_wait_for_CCR (cpu, in_FCCi_2); + handle_resource_wait (cpu); + load_wait_for_GR (cpu, in_GRi); + load_wait_for_GR (cpu, in_GRj); + trace_vliw_wait_cycles (cpu); + return 0; + } + + cycles = idesc->timing->units[unit_num].done; + return cycles; +} + +int +frvbf_model_fr550_u_check (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_ICCi_3, INT in_FCCi_3) +{ + /* Modelling for this unit is the same as for fr500. */ + return frvbf_model_fr500_u_check (cpu, idesc, unit_num, referenced, + in_ICCi_3, in_FCCi_3); +} + +int +frvbf_model_fr550_u_set_hilo (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT out_GRkhi, INT out_GRklo) +{ + int cycles; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + { + /* The entire VLIW insn must wait if there is a dependency on a GR + which is not ready yet. */ + vliw_wait_for_GR (cpu, out_GRkhi); + vliw_wait_for_GR (cpu, out_GRklo); + handle_resource_wait (cpu); + load_wait_for_GR (cpu, out_GRkhi); + load_wait_for_GR (cpu, out_GRklo); + trace_vliw_wait_cycles (cpu); + return 0; + } + + /* GRk is available immediately to the next VLIW insn. */ + cycles = idesc->timing->units[unit_num].done; + + return cycles; +} + +int +frvbf_model_fr550_u_gr_load (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRi, INT in_GRj, + INT out_GRk, INT out_GRdoublek) +{ + int cycles; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + { + /* The entire VLIW insn must wait if there is a dependency on a register + which is not ready yet. */ + vliw_wait_for_GR (cpu, in_GRi); + vliw_wait_for_GR (cpu, in_GRj); + vliw_wait_for_GR (cpu, out_GRk); + vliw_wait_for_GRdouble (cpu, out_GRdoublek); + handle_resource_wait (cpu); + load_wait_for_GR (cpu, in_GRi); + load_wait_for_GR (cpu, in_GRj); + load_wait_for_GR (cpu, out_GRk); + load_wait_for_GRdouble (cpu, out_GRdoublek); + trace_vliw_wait_cycles (cpu); + return 0; + } + + cycles = idesc->timing->units[unit_num].done; + + /* The latency of GRk for a load will depend on how long it takes to retrieve + the the data from the cache or memory. */ + update_GR_latency_for_load (cpu, out_GRk, cycles); + update_GRdouble_latency_for_load (cpu, out_GRdoublek, cycles); + + if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) + { + /* GNER has a latency of 2 cycles. */ + update_SPR_latency (cpu, GNER_FOR_GR (out_GRk), cycles + 2); + update_SPR_latency (cpu, GNER_FOR_GR (out_GRdoublek), cycles + 2); + } + + return cycles; +} + +int +frvbf_model_fr550_u_gr_store (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRi, INT in_GRj, + INT in_GRk, INT in_GRdoublek) +{ + int cycles; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + { + /* The entire VLIW insn must wait if there is a dependency on a register + which is not ready yet. */ + vliw_wait_for_GR (cpu, in_GRi); + vliw_wait_for_GR (cpu, in_GRj); + vliw_wait_for_GR (cpu, in_GRk); + vliw_wait_for_GRdouble (cpu, in_GRdoublek); + handle_resource_wait (cpu); + load_wait_for_GR (cpu, in_GRi); + load_wait_for_GR (cpu, in_GRj); + load_wait_for_GR (cpu, in_GRk); + load_wait_for_GRdouble (cpu, in_GRdoublek); + trace_vliw_wait_cycles (cpu); + return 0; + } + + /* The target register is available immediately. */ + cycles = idesc->timing->units[unit_num].done; + + return cycles; +} + +int +frvbf_model_fr550_u_fr_load (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRi, INT in_GRj, + INT out_FRk, INT out_FRdoublek) +{ + int cycles; + if (model_insn == FRV_INSN_MODEL_PASS_1) + { + /* The entire VLIW insn must wait if there is a dependency on a register + which is not ready yet. + The latency of the registers may be less than previously recorded, + depending on how they were used previously. + See Table 13-8 in the LSI. */ + adjust_float_register_busy (cpu, -1, 1, -1, 1, out_FRk, 1); + adjust_float_register_busy (cpu, -1, 1, -1, 1, out_FRdoublek, 2); + vliw_wait_for_GR (cpu, in_GRi); + vliw_wait_for_GR (cpu, in_GRj); + vliw_wait_for_FR (cpu, out_FRk); + vliw_wait_for_FRdouble (cpu, out_FRdoublek); + if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) + { + vliw_wait_for_SPR (cpu, FNER_FOR_FR (out_FRk)); + vliw_wait_for_SPR (cpu, FNER_FOR_FR (out_FRdoublek)); + } + handle_resource_wait (cpu); + load_wait_for_GR (cpu, in_GRi); + load_wait_for_GR (cpu, in_GRj); + load_wait_for_FR (cpu, out_FRk); + load_wait_for_FRdouble (cpu, out_FRdoublek); + trace_vliw_wait_cycles (cpu); + return 0; + } + + cycles = idesc->timing->units[unit_num].done; + + /* The latency of FRk for a load will depend on how long it takes to retrieve + the the data from the cache or memory. */ + update_FR_latency_for_load (cpu, out_FRk, cycles); + update_FRdouble_latency_for_load (cpu, out_FRdoublek, cycles); + + if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) + { + /* FNER has a latency of 3 cycles. */ + update_SPR_latency (cpu, FNER_FOR_FR (out_FRk), cycles + 3); + update_SPR_latency (cpu, FNER_FOR_FR (out_FRdoublek), cycles + 3); + } + + if (out_FRk >= 0) + set_use_is_fr_load (cpu, out_FRk); + if (out_FRdoublek >= 0) + { + set_use_is_fr_load (cpu, out_FRdoublek); + set_use_is_fr_load (cpu, out_FRdoublek + 1); + } + + return cycles; +} + +int +frvbf_model_fr550_u_fr_store (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRi, INT in_GRj, + INT in_FRk, INT in_FRdoublek) +{ + int cycles; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + { + /* The entire VLIW insn must wait if there is a dependency on a register + which is not ready yet. */ + adjust_float_register_busy (cpu, in_FRk, 1, -1, 1, -1, 1); + adjust_float_register_busy (cpu, in_FRdoublek, 2, -1, 1, -1, 1); + vliw_wait_for_GR (cpu, in_GRi); + vliw_wait_for_GR (cpu, in_GRj); + vliw_wait_for_FR (cpu, in_FRk); + vliw_wait_for_FRdouble (cpu, in_FRdoublek); + handle_resource_wait (cpu); + load_wait_for_GR (cpu, in_GRi); + load_wait_for_GR (cpu, in_GRj); + load_wait_for_FR (cpu, in_FRk); + load_wait_for_FRdouble (cpu, in_FRdoublek); + trace_vliw_wait_cycles (cpu); + return 0; + } + + /* The target register is available immediately. */ + cycles = idesc->timing->units[unit_num].done; + + return cycles; +} + +int +frvbf_model_fr550_u_ici (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRi, INT in_GRj) +{ + int cycles; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + { + /* The entire VLIW insn must wait if there is a dependency on a register + which is not ready yet. */ + vliw_wait_for_GR (cpu, in_GRi); + vliw_wait_for_GR (cpu, in_GRj); + handle_resource_wait (cpu); + load_wait_for_GR (cpu, in_GRi); + load_wait_for_GR (cpu, in_GRj); + trace_vliw_wait_cycles (cpu); + return 0; + } + + cycles = idesc->timing->units[unit_num].done; + request_cache_invalidate (cpu, CPU_INSN_CACHE (cpu), cycles); + return cycles; +} + +int +frvbf_model_fr550_u_dci (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRi, INT in_GRj) +{ + int cycles; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + { + /* The entire VLIW insn must wait if there is a dependency on a register + which is not ready yet. */ + vliw_wait_for_GR (cpu, in_GRi); + vliw_wait_for_GR (cpu, in_GRj); + handle_resource_wait (cpu); + load_wait_for_GR (cpu, in_GRi); + load_wait_for_GR (cpu, in_GRj); + trace_vliw_wait_cycles (cpu); + return 0; + } + + cycles = idesc->timing->units[unit_num].done; + request_cache_invalidate (cpu, CPU_DATA_CACHE (cpu), cycles); + return cycles; +} + +int +frvbf_model_fr550_u_dcf (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRi, INT in_GRj) +{ + int cycles; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + { + /* The entire VLIW insn must wait if there is a dependency on a register + which is not ready yet. */ + vliw_wait_for_GR (cpu, in_GRi); + vliw_wait_for_GR (cpu, in_GRj); + handle_resource_wait (cpu); + load_wait_for_GR (cpu, in_GRi); + load_wait_for_GR (cpu, in_GRj); + trace_vliw_wait_cycles (cpu); + return 0; + } + + cycles = idesc->timing->units[unit_num].done; + request_cache_flush (cpu, CPU_DATA_CACHE (cpu), cycles); + return cycles; +} + +int +frvbf_model_fr550_u_icpl (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRi, INT in_GRj) +{ + int cycles; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + { + /* The entire VLIW insn must wait if there is a dependency on a register + which is not ready yet. */ + vliw_wait_for_GR (cpu, in_GRi); + vliw_wait_for_GR (cpu, in_GRj); + handle_resource_wait (cpu); + load_wait_for_GR (cpu, in_GRi); + load_wait_for_GR (cpu, in_GRj); + trace_vliw_wait_cycles (cpu); + return 0; + } + + cycles = idesc->timing->units[unit_num].done; + request_cache_preload (cpu, CPU_INSN_CACHE (cpu), cycles); + return cycles; +} + +int +frvbf_model_fr550_u_dcpl (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRi, INT in_GRj) +{ + int cycles; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + { + /* The entire VLIW insn must wait if there is a dependency on a register + which is not ready yet. */ + vliw_wait_for_GR (cpu, in_GRi); + vliw_wait_for_GR (cpu, in_GRj); + handle_resource_wait (cpu); + load_wait_for_GR (cpu, in_GRi); + load_wait_for_GR (cpu, in_GRj); + trace_vliw_wait_cycles (cpu); + return 0; + } + + cycles = idesc->timing->units[unit_num].done; + request_cache_preload (cpu, CPU_DATA_CACHE (cpu), cycles); + return cycles; +} + +int +frvbf_model_fr550_u_icul (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRi, INT in_GRj) +{ + int cycles; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + { + /* The entire VLIW insn must wait if there is a dependency on a register + which is not ready yet. */ + vliw_wait_for_GR (cpu, in_GRi); + vliw_wait_for_GR (cpu, in_GRj); + handle_resource_wait (cpu); + load_wait_for_GR (cpu, in_GRi); + load_wait_for_GR (cpu, in_GRj); + trace_vliw_wait_cycles (cpu); + return 0; + } + + cycles = idesc->timing->units[unit_num].done; + request_cache_unlock (cpu, CPU_INSN_CACHE (cpu), cycles); + return cycles; +} + +int +frvbf_model_fr550_u_dcul (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRi, INT in_GRj) +{ + int cycles; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + { + /* The entire VLIW insn must wait if there is a dependency on a register + which is not ready yet. */ + vliw_wait_for_GR (cpu, in_GRi); + vliw_wait_for_GR (cpu, in_GRj); + handle_resource_wait (cpu); + load_wait_for_GR (cpu, in_GRi); + load_wait_for_GR (cpu, in_GRj); + trace_vliw_wait_cycles (cpu); + return 0; + } + + cycles = idesc->timing->units[unit_num].done; + request_cache_unlock (cpu, CPU_DATA_CACHE (cpu), cycles); + return cycles; +} + +int +frvbf_model_fr550_u_float_arith (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_FRi, INT in_FRj, + INT in_FRdoublei, INT in_FRdoublej, + INT out_FRk, INT out_FRdoublek) +{ + int cycles; + FRV_PROFILE_STATE *ps; + FRV_VLIW *vliw; + int slot; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + return 0; + + /* The preprocessing can execute right away. */ + cycles = idesc->timing->units[unit_num].done; + + /* The post processing must wait if there is a dependency on a FR + which is not ready yet. */ + adjust_float_register_busy (cpu, in_FRi, 1, in_FRj, 1, out_FRk, 1); + adjust_float_register_busy (cpu, in_FRdoublei, 2, in_FRdoublej, 2, out_FRdoublek, 2); + ps = CPU_PROFILE_STATE (cpu); + ps->post_wait = cycles; + vliw = CPU_VLIW (cpu); + slot = vliw->next_slot - 1; + slot = (*vliw->current_vliw)[slot] - UNIT_FM0; + post_wait_for_float (cpu, slot); + post_wait_for_FR (cpu, in_FRi); + post_wait_for_FR (cpu, in_FRj); + post_wait_for_FR (cpu, out_FRk); + post_wait_for_FRdouble (cpu, in_FRdoublei); + post_wait_for_FRdouble (cpu, in_FRdoublej); + post_wait_for_FRdouble (cpu, out_FRdoublek); + if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) + { + post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRk)); + post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRdoublek)); + } + restore_float_register_busy (cpu, in_FRi, 1, in_FRj, 1, out_FRk, 1); + restore_float_register_busy (cpu, in_FRdoublei, 2, in_FRdoublej, 2, out_FRdoublek, 2); + + /* The latency of FRk will be at least the latency of the other inputs. */ + update_FR_latency (cpu, out_FRk, ps->post_wait); + update_FRdouble_latency (cpu, out_FRdoublek, ps->post_wait); + + if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) + { + update_SPR_latency (cpu, FNER_FOR_FR (out_FRk), ps->post_wait); + update_SPR_latency (cpu, FNER_FOR_FR (out_FRdoublek), ps->post_wait); + } + + /* Once initiated, post-processing will take 2 cycles. */ + update_FR_ptime (cpu, out_FRk, 2); + update_FRdouble_ptime (cpu, out_FRdoublek, 2); + if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) + { + update_SPR_ptime (cpu, FNER_FOR_FR (out_FRk), 2); + update_SPR_ptime (cpu, FNER_FOR_FR (out_FRdoublek), 2); + } + + /* Mark this use of the register as a floating point op. */ + if (out_FRk >= 0) + set_use_is_fr_complex_2 (cpu, out_FRk); + if (out_FRdoublek >= 0) + { + set_use_is_fr_complex_2 (cpu, out_FRdoublek); + if (out_FRdoublek < 63) + set_use_is_fr_complex_2 (cpu, out_FRdoublek + 1); + } + + /* the media point unit resource has a latency of 4 cycles */ + update_media_resource_latency (cpu, slot, cycles + 4); + + return cycles; +} + +int +frvbf_model_fr550_u_float_dual_arith (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_FRi, INT in_FRj, + INT in_FRdoublei, INT in_FRdoublej, + INT out_FRk, INT out_FRdoublek) +{ + int cycles; + INT dual_FRi; + INT dual_FRj; + INT dual_FRk; + INT dual_FRdoublei; + INT dual_FRdoublej; + INT dual_FRdoublek; + FRV_PROFILE_STATE *ps; + FRV_VLIW *vliw; + int slot; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + return 0; + + /* The preprocessing can execute right away. */ + cycles = idesc->timing->units[unit_num].done; + + /* The post processing must wait if there is a dependency on a FR + which is not ready yet. */ + dual_FRi = DUAL_REG (in_FRi); + dual_FRj = DUAL_REG (in_FRj); + dual_FRk = DUAL_REG (out_FRk); + dual_FRdoublei = DUAL_DOUBLE (in_FRdoublei); + dual_FRdoublej = DUAL_DOUBLE (in_FRdoublej); + dual_FRdoublek = DUAL_DOUBLE (out_FRdoublek); + + adjust_float_register_busy (cpu, in_FRi, 2, in_FRj, 2, out_FRk, 2); + adjust_float_register_busy (cpu, in_FRdoublei, 4, in_FRdoublej, 4, out_FRdoublek, 4); + ps = CPU_PROFILE_STATE (cpu); + ps->post_wait = cycles; + vliw = CPU_VLIW (cpu); + slot = vliw->next_slot - 1; + slot = (*vliw->current_vliw)[slot] - UNIT_FM0; + post_wait_for_float (cpu, slot); + post_wait_for_FR (cpu, in_FRi); + post_wait_for_FR (cpu, in_FRj); + post_wait_for_FR (cpu, out_FRk); + post_wait_for_FR (cpu, dual_FRi); + post_wait_for_FR (cpu, dual_FRj); + post_wait_for_FR (cpu, dual_FRk); + post_wait_for_FRdouble (cpu, in_FRdoublei); + post_wait_for_FRdouble (cpu, in_FRdoublej); + post_wait_for_FRdouble (cpu, out_FRdoublek); + post_wait_for_FRdouble (cpu, dual_FRdoublei); + post_wait_for_FRdouble (cpu, dual_FRdoublej); + post_wait_for_FRdouble (cpu, dual_FRdoublek); + if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) + { + post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRk)); + post_wait_for_SPR (cpu, FNER_FOR_FR (dual_FRk)); + post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRdoublek)); + post_wait_for_SPR (cpu, FNER_FOR_FR (dual_FRdoublek)); + } + restore_float_register_busy (cpu, in_FRi, 2, in_FRj, 2, out_FRk, 2); + restore_float_register_busy (cpu, in_FRdoublei, 4, in_FRdoublej, 4, out_FRdoublek, 4); + + /* The latency of FRk will be at least the latency of the other inputs. */ + update_FR_latency (cpu, out_FRk, ps->post_wait); + update_FR_latency (cpu, dual_FRk, ps->post_wait); + update_FRdouble_latency (cpu, out_FRdoublek, ps->post_wait); + update_FRdouble_latency (cpu, dual_FRdoublek, ps->post_wait); + + if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) + { + update_SPR_latency (cpu, FNER_FOR_FR (out_FRk), ps->post_wait); + update_SPR_latency (cpu, FNER_FOR_FR (dual_FRk), ps->post_wait); + update_SPR_latency (cpu, FNER_FOR_FR (out_FRdoublek), ps->post_wait); + update_SPR_latency (cpu, FNER_FOR_FR (dual_FRdoublek), ps->post_wait); + } + + /* Once initiated, post-processing will take 3 cycles. */ + update_FR_ptime (cpu, out_FRk, 3); + update_FR_ptime (cpu, dual_FRk, 3); + update_FRdouble_ptime (cpu, out_FRdoublek, 3); + update_FRdouble_ptime (cpu, dual_FRdoublek, 3); + + if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) + { + update_SPR_ptime (cpu, FNER_FOR_FR (out_FRk), 3); + update_SPR_ptime (cpu, FNER_FOR_FR (dual_FRk), 3); + update_SPR_ptime (cpu, FNER_FOR_FR (out_FRdoublek), 3); + update_SPR_ptime (cpu, FNER_FOR_FR (dual_FRdoublek), 3); + } + + /* Mark this use of the register as a floating point op. */ + if (out_FRk >= 0) + fr550_reset_fr_flags (cpu, out_FRk); + if (dual_FRk >= 0) + fr550_reset_fr_flags (cpu, dual_FRk); + if (out_FRdoublek >= 0) + { + fr550_reset_fr_flags (cpu, out_FRdoublek); + if (out_FRdoublek < 63) + fr550_reset_fr_flags (cpu, out_FRdoublek + 1); + } + if (dual_FRdoublek >= 0) + { + fr550_reset_fr_flags (cpu, dual_FRdoublek); + if (dual_FRdoublek < 63) + fr550_reset_fr_flags (cpu, dual_FRdoublek + 1); + } + + /* the media point unit resource has a latency of 5 cycles */ + update_media_resource_latency (cpu, slot, cycles + 5); + + return cycles; +} + +int +frvbf_model_fr550_u_float_div (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_FRi, INT in_FRj, INT out_FRk) +{ + int cycles; + FRV_VLIW *vliw; + int slot; + FRV_PROFILE_STATE *ps; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + return 0; + + cycles = idesc->timing->units[unit_num].done; + + /* The post processing must wait if there is a dependency on a FR + which is not ready yet. */ + adjust_float_register_busy (cpu, in_FRi, 1, in_FRj, 1, out_FRk, 1); + ps = CPU_PROFILE_STATE (cpu); + ps->post_wait = cycles; + vliw = CPU_VLIW (cpu); + slot = vliw->next_slot - 1; + slot = (*vliw->current_vliw)[slot] - UNIT_FM0; + post_wait_for_float (cpu, slot); + post_wait_for_fdiv (cpu, slot); + post_wait_for_FR (cpu, in_FRi); + post_wait_for_FR (cpu, in_FRj); + post_wait_for_FR (cpu, out_FRk); + if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) + post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRk)); + restore_float_register_busy (cpu, in_FRi, 1, in_FRj, 1, out_FRk, 1); + + /* The latency of FRk will be at least the latency of the other inputs. */ + /* Once initiated, post-processing will take 9 cycles. */ + update_FR_latency (cpu, out_FRk, ps->post_wait); + update_FR_ptime (cpu, out_FRk, 9); + + if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) + { + /* FNER has a latency of 9 cycles. */ + update_SPR_latency (cpu, FNER_FOR_FR (out_FRk), ps->post_wait); + update_SPR_ptime (cpu, FNER_FOR_FR (out_FRk), 9); + } + + /* The latency of the fdiv unit will be at least the latency of the other + inputs. Once initiated, post-processing will take 9 cycles. */ + update_fdiv_resource_latency (cpu, slot, ps->post_wait + 9); + + /* the media point unit resource has a latency of 11 cycles */ + update_media_resource_latency (cpu, slot, cycles + 11); + + fr550_reset_fr_flags (cpu, out_FRk); + + return cycles; +} + +int +frvbf_model_fr550_u_float_sqrt (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_FRj, INT in_FRdoublej, + INT out_FRk, INT out_FRdoublek) +{ + int cycles; + FRV_VLIW *vliw; + int slot; + FRV_PROFILE_STATE *ps; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + return 0; + + cycles = idesc->timing->units[unit_num].done; + + /* The post processing must wait if there is a dependency on a FR + which is not ready yet. */ + adjust_float_register_busy (cpu, -1, 1, in_FRj, 1, out_FRk, 1); + adjust_float_register_busy (cpu, -1, 1, in_FRdoublej, 2, out_FRdoublek, 2); + ps = CPU_PROFILE_STATE (cpu); + ps->post_wait = cycles; + vliw = CPU_VLIW (cpu); + slot = vliw->next_slot - 1; + slot = (*vliw->current_vliw)[slot] - UNIT_FM0; + post_wait_for_float (cpu, slot); + post_wait_for_fsqrt (cpu, slot); + post_wait_for_FR (cpu, in_FRj); + post_wait_for_FR (cpu, out_FRk); + post_wait_for_FRdouble (cpu, in_FRdoublej); + post_wait_for_FRdouble (cpu, out_FRdoublek); + if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) + { + post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRk)); + post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRdoublek)); + } + restore_float_register_busy (cpu, -1, 1, in_FRj, 1, out_FRk, 1); + restore_float_register_busy (cpu, -1, 1, in_FRdoublej, 2, out_FRdoublek, 2); + + /* The latency of FRk will be at least the latency of the other inputs. */ + update_FR_latency (cpu, out_FRk, ps->post_wait); + update_FRdouble_latency (cpu, out_FRdoublek, ps->post_wait); + + if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) + { + /* FNER has a latency of 14 cycles. */ + update_SPR_latency (cpu, FNER_FOR_FR (out_FRk), ps->post_wait); + update_SPR_latency (cpu, FNER_FOR_FR (out_FRdoublek), ps->post_wait); + } + + /* Once initiated, post-processing will take 14 cycles. */ + update_FR_ptime (cpu, out_FRk, 14); + update_FRdouble_ptime (cpu, out_FRdoublek, 14); + + if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) + { + /* FNER has a latency of 14 cycles. */ + update_SPR_ptime (cpu, FNER_FOR_FR (out_FRk), 14); + update_SPR_ptime (cpu, FNER_FOR_FR (out_FRdoublek), 14); + } + + /* The latency of the sqrt unit will be the latency of the other + inputs plus 14 cycles. */ + update_fsqrt_resource_latency (cpu, slot, ps->post_wait + 14); + + fr550_reset_fr_flags (cpu, out_FRk); + if (out_FRdoublek != -1) + { + fr550_reset_fr_flags (cpu, out_FRdoublek); + fr550_reset_fr_flags (cpu, out_FRdoublek + 1); + } + + /* the media point unit resource has a latency of 16 cycles */ + update_media_resource_latency (cpu, slot, cycles + 16); + + return cycles; +} + +int +frvbf_model_fr550_u_float_compare (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_FRi, INT in_FRj, + INT in_FRdoublei, INT in_FRdoublej, + INT out_FCCi_2) +{ + int cycles; + FRV_PROFILE_STATE *ps; + FRV_VLIW *vliw; + int slot; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + return 0; + + /* The preprocessing can execute right away. */ + cycles = idesc->timing->units[unit_num].done; + + /* The post processing must wait if there is a dependency on a FR + which is not ready yet. */ + adjust_float_register_busy (cpu, in_FRi, 1, in_FRj, 1, -1, 1); + adjust_float_register_busy (cpu, in_FRdoublei, 2, in_FRdoublej, 2, -1, 1); + ps = CPU_PROFILE_STATE (cpu); + ps->post_wait = cycles; + vliw = CPU_VLIW (cpu); + slot = vliw->next_slot - 1; + slot = (*vliw->current_vliw)[slot] - UNIT_FM0; + post_wait_for_float (cpu, slot); + post_wait_for_FR (cpu, in_FRi); + post_wait_for_FR (cpu, in_FRj); + post_wait_for_FRdouble (cpu, in_FRdoublei); + post_wait_for_FRdouble (cpu, in_FRdoublej); + post_wait_for_CCR (cpu, out_FCCi_2); + restore_float_register_busy (cpu, in_FRi, 1, in_FRj, 1, -1, 1); + restore_float_register_busy (cpu, in_FRdoublei, 2, in_FRdoublej, 2, -1, 1); + + /* The latency of FCCi_2 will be the latency of the other inputs plus 2 + cycles. */ + update_CCR_latency (cpu, out_FCCi_2, ps->post_wait + 2); + + /* the media point unit resource has a latency of 4 cycles */ + update_media_resource_latency (cpu, slot, cycles + 4); + + set_use_is_ccr_complex (cpu, out_FCCi_2); + + return cycles; +} + +int +frvbf_model_fr550_u_float_dual_compare (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_FRi, INT in_FRj, + INT out_FCCi_2) +{ + int cycles; + INT dual_FRi; + INT dual_FRj; + INT dual_FCCi_2; + FRV_PROFILE_STATE *ps; + FRV_VLIW *vliw; + int slot; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + return 0; + + /* The preprocessing can execute right away. */ + cycles = idesc->timing->units[unit_num].done; + + /* The post processing must wait if there is a dependency on a FR + which is not ready yet. */ + ps = CPU_PROFILE_STATE (cpu); + ps->post_wait = cycles; + dual_FRi = DUAL_REG (in_FRi); + dual_FRj = DUAL_REG (in_FRj); + dual_FCCi_2 = out_FCCi_2 + 1; + adjust_float_register_busy (cpu, in_FRi, 2, in_FRj, 2, -1, 1); + vliw = CPU_VLIW (cpu); + slot = vliw->next_slot - 1; + slot = (*vliw->current_vliw)[slot] - UNIT_FM0; + post_wait_for_float (cpu, slot); + post_wait_for_FR (cpu, in_FRi); + post_wait_for_FR (cpu, in_FRj); + post_wait_for_FR (cpu, dual_FRi); + post_wait_for_FR (cpu, dual_FRj); + post_wait_for_CCR (cpu, out_FCCi_2); + post_wait_for_CCR (cpu, dual_FCCi_2); + restore_float_register_busy (cpu, in_FRi, 2, in_FRj, 2, -1, 1); + + /* The latency of FCCi_2 will be the latency of the other inputs plus 3 + cycles. */ + update_CCR_latency (cpu, out_FCCi_2, ps->post_wait + 3); + update_CCR_latency (cpu, dual_FCCi_2, ps->post_wait + 3); + + set_use_is_ccr_complex (cpu, out_FCCi_2); + if (dual_FCCi_2 >= 0) + set_use_is_ccr_complex (cpu, dual_FCCi_2); + + /* the media point unit resource has a latency of 5 cycles */ + update_media_resource_latency (cpu, slot, cycles + 5); + + return cycles; +} + +int +frvbf_model_fr550_u_float_convert (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_FRj, INT in_FRintj, INT in_FRdoublej, + INT out_FRk, INT out_FRintk, + INT out_FRdoublek) +{ + int cycles; + FRV_PROFILE_STATE *ps; + FRV_VLIW *vliw; + int slot; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + return 0; + + /* The preprocessing can execute right away. */ + cycles = idesc->timing->units[unit_num].done; + + /* The post processing must wait if there is a dependency on a FR + which is not ready yet. */ + ps = CPU_PROFILE_STATE (cpu); + ps->post_wait = cycles; + adjust_float_register_busy (cpu, -1, 1, in_FRj, 1, out_FRk, 1); + adjust_float_register_busy (cpu, -1, 1, in_FRintj, 1, out_FRintk, 1); + adjust_float_register_busy (cpu, -1, 1, in_FRdoublej, 2, out_FRdoublek, 2); + vliw = CPU_VLIW (cpu); + slot = vliw->next_slot - 1; + slot = (*vliw->current_vliw)[slot] - UNIT_FM0; + post_wait_for_float (cpu, slot); + post_wait_for_FR (cpu, in_FRj); + post_wait_for_FR (cpu, in_FRintj); + post_wait_for_FRdouble (cpu, in_FRdoublej); + post_wait_for_FR (cpu, out_FRk); + post_wait_for_FR (cpu, out_FRintk); + post_wait_for_FRdouble (cpu, out_FRdoublek); + if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) + { + post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRk)); + post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRintk)); + post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRdoublek)); + } + restore_float_register_busy (cpu, -1, 1, in_FRj, 1, out_FRk, 1); + restore_float_register_busy (cpu, -1, 1, in_FRintj, 1, out_FRintk, 1); + restore_float_register_busy (cpu, -1, 1, in_FRdoublej, 2, out_FRdoublek, 2); + + /* The latency of FRk will be at least the latency of the other inputs. */ + update_FR_latency (cpu, out_FRk, ps->post_wait); + update_FR_latency (cpu, out_FRintk, ps->post_wait); + update_FRdouble_latency (cpu, out_FRdoublek, ps->post_wait); + + if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) + { + update_SPR_latency (cpu, FNER_FOR_FR (out_FRk), ps->post_wait); + update_SPR_latency (cpu, FNER_FOR_FR (out_FRintk), ps->post_wait); + update_SPR_latency (cpu, FNER_FOR_FR (out_FRdoublek), ps->post_wait); + } + + /* Once initiated, post-processing will take 2 cycles. */ + update_FR_ptime (cpu, out_FRk, 2); + update_FR_ptime (cpu, out_FRintk, 2); + update_FRdouble_ptime (cpu, out_FRdoublek, 2); + + if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) + { + update_SPR_ptime (cpu, FNER_FOR_FR (out_FRk), 2); + update_SPR_ptime (cpu, FNER_FOR_FR (out_FRintk), 2); + update_SPR_ptime (cpu, FNER_FOR_FR (out_FRdoublek), 2); + } + + /* Mark this use of the register as a floating point op. */ + if (out_FRk >= 0) + set_use_is_fr_complex_2 (cpu, out_FRk); + if (out_FRintk >= 0) + set_use_is_fr_complex_2 (cpu, out_FRintk); + if (out_FRdoublek >= 0) + { + set_use_is_fr_complex_2 (cpu, out_FRdoublek); + set_use_is_fr_complex_2 (cpu, out_FRdoublek + 1); + } + + /* the media point unit resource has a latency of 4 cycles */ + update_media_resource_latency (cpu, slot, cycles + 4); + + return cycles; +} + +int +frvbf_model_fr550_u_spr2gr (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_spr, INT out_GRj) +{ + /* Modelling for this unit is the same as for fr500. */ + return frvbf_model_fr500_u_spr2gr (cpu, idesc, unit_num, referenced, + in_spr, out_GRj); +} + +int +frvbf_model_fr550_u_gr2spr (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRj, INT out_spr) +{ + int cycles; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + { + /* The entire VLIW insn must wait if there is a dependency on a register + which is not ready yet. */ + vliw_wait_for_GR (cpu, in_GRj); + vliw_wait_for_SPR (cpu, out_spr); + handle_resource_wait (cpu); + load_wait_for_GR (cpu, in_GRj); + trace_vliw_wait_cycles (cpu); + return 0; + } + + cycles = idesc->timing->units[unit_num].done; + +#if 0 + /* The latency of spr is ? cycles. */ + update_SPR_latency (cpu, out_spr, cycles + ?); +#endif + + return cycles; +} + +int +frvbf_model_fr550_u_gr2fr (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRj, INT out_FRk) +{ + int cycles; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + { + /* The entire VLIW insn must wait if there is a dependency on a register + which is not ready yet. + The latency of the registers may be less than previously recorded, + depending on how they were used previously. + See Table 14-15 in the LSI. */ + adjust_float_register_busy (cpu, -1, 1, -1, 1, out_FRk, 1); + vliw_wait_for_GR (cpu, in_GRj); + vliw_wait_for_FR (cpu, out_FRk); + handle_resource_wait (cpu); + load_wait_for_GR (cpu, in_GRj); + load_wait_for_FR (cpu, out_FRk); + trace_vliw_wait_cycles (cpu); + return 0; + } + + /* The latency of FRk is 1 cycles. */ + cycles = idesc->timing->units[unit_num].done; + update_FR_latency (cpu, out_FRk, cycles + 1); + + set_use_is_fr_complex_1 (cpu, out_FRk); + + return cycles; +} + +int +frvbf_model_fr550_u_swap (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRi, INT in_GRj, INT out_GRk) +{ + int cycles; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + { + /* The entire VLIW insn must wait if there is a dependency on a register + which is not ready yet. */ + vliw_wait_for_GR (cpu, in_GRi); + vliw_wait_for_GR (cpu, in_GRj); + vliw_wait_for_GR (cpu, out_GRk); + handle_resource_wait (cpu); + load_wait_for_GR (cpu, in_GRi); + load_wait_for_GR (cpu, in_GRj); + load_wait_for_GR (cpu, out_GRk); + trace_vliw_wait_cycles (cpu); + return 0; + } + + cycles = idesc->timing->units[unit_num].done; + + /* The latency of GRk will depend on how long it takes to swap + the the data from the cache or memory. */ + update_GR_latency_for_swap (cpu, out_GRk, cycles); + + return cycles; +} + +int +frvbf_model_fr550_u_fr2fr (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_FRj, INT out_FRk) +{ + int cycles; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + { + /* The entire VLIW insn must wait if there is a dependency on a register + which is not ready yet. + The latency of the registers may be less than previously recorded, + depending on how they were used previously. + See Table 14-15 in the LSI. */ + adjust_float_register_busy (cpu, -1, 1, in_FRj, 1, out_FRk, 1); + vliw_wait_for_FR (cpu, in_FRj); + vliw_wait_for_FR (cpu, out_FRk); + handle_resource_wait (cpu); + load_wait_for_FR (cpu, in_FRj); + load_wait_for_FR (cpu, out_FRk); + trace_vliw_wait_cycles (cpu); + return 0; + } + + /* The latency of FRj is 2 cycles. */ + cycles = idesc->timing->units[unit_num].done; + update_FR_latency (cpu, out_FRk, cycles + 2); + + set_use_is_fr_complex_2 (cpu, out_FRk); + + return cycles; +} + +int +frvbf_model_fr550_u_fr2gr (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_FRk, INT out_GRj) +{ + int cycles; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + { + /* The entire VLIW insn must wait if there is a dependency on a register + which is not ready yet. + The latency of the registers may be less than previously recorded, + depending on how they were used previously. + See Table 14-15 in the LSI. */ + adjust_float_register_busy (cpu, in_FRk, 1, -1, 1, -1, 1); + vliw_wait_for_FR (cpu, in_FRk); + vliw_wait_for_GR (cpu, out_GRj); + handle_resource_wait (cpu); + load_wait_for_FR (cpu, in_FRk); + load_wait_for_GR (cpu, out_GRj); + trace_vliw_wait_cycles (cpu); + return 0; + } + + /* The latency of GRj is 1 cycle. */ + cycles = idesc->timing->units[unit_num].done; + update_GR_latency (cpu, out_GRj, cycles + 1); + + return cycles; +} + +int +frvbf_model_fr550_u_clrgr (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRk) +{ + /* Modelling for this unit is the same as for fr500. */ + return frvbf_model_fr500_u_clrgr (cpu, idesc, unit_num, referenced, in_GRk); +} + +int +frvbf_model_fr550_u_clrfr (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_FRk) +{ + /* Modelling for this unit is the same as for fr500. */ + return frvbf_model_fr500_u_clrfr (cpu, idesc, unit_num, referenced, in_FRk); +} + +int +frvbf_model_fr550_u_commit (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRk, INT in_FRk) +{ + /* Modelling for this unit is the same as for fr500. */ + return frvbf_model_fr500_u_commit (cpu, idesc, unit_num, referenced, + in_GRk, in_FRk); +} + +int +frvbf_model_fr550_u_media (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_FRi, INT in_FRj, INT out_FRk) +{ + int cycles; + FRV_PROFILE_STATE *ps; + FRV_VLIW *vliw; + int slot; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + return 0; + + /* The preprocessing can execute right away. */ + cycles = idesc->timing->units[unit_num].done; + + /* If the previous use of the registers was a media op, + then their latency may be less than previously recorded. + See Table 14-15 in the LSI. */ + adjust_float_register_busy_for_media (cpu, in_FRi, 1, in_FRj, 1, out_FRk, 1); + + /* The post processing must wait if there is a dependency on a FR + which is not ready yet. */ + ps = CPU_PROFILE_STATE (cpu); + ps->post_wait = cycles; + vliw = CPU_VLIW (cpu); + slot = vliw->next_slot - 1; + slot = (*vliw->current_vliw)[slot] - UNIT_FM0; + post_wait_for_media (cpu, slot); + post_wait_for_FR (cpu, in_FRi); + post_wait_for_FR (cpu, in_FRj); + post_wait_for_FR (cpu, out_FRk); + + /* Restore the busy cycles of the registers we used. */ + restore_float_register_busy_for_media (cpu, in_FRi, 1, in_FRj, 1, out_FRk, 1); + + /* The latency of tht output register will be at least the latency of the + other inputs. Once initiated, post-processing will take 1 cycle. */ + if (out_FRk >= 0) + { + update_FR_latency (cpu, out_FRk, ps->post_wait); + update_FR_ptime (cpu, out_FRk, 1); + /* Mark this use of the register as a media op. */ + set_use_is_fr_complex_1 (cpu, out_FRk); + } + + /* the floating point unit resource has a latency of 3 cycles */ + update_float_resource_latency (cpu, slot, cycles + 3); + + return cycles; +} + +int +frvbf_model_fr550_u_media_quad (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_FRi, INT in_FRj, + INT out_FRk) +{ + int cycles; + INT dual_FRi; + INT dual_FRj; + INT dual_FRk; + FRV_PROFILE_STATE *ps; + FRV_VLIW *vliw; + int slot; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + return 0; + + /* The preprocessing can execute right away. */ + cycles = idesc->timing->units[unit_num].done; + + dual_FRi = DUAL_REG (in_FRi); + dual_FRj = DUAL_REG (in_FRj); + dual_FRk = DUAL_REG (out_FRk); + + /* The latency of the registers may be less than previously recorded, + depending on how they were used previously. + See Table 14-15 in the LSI. */ + adjust_float_register_busy_for_media (cpu, in_FRi, 2, in_FRj, 2, out_FRk, 2); + + /* The post processing must wait if there is a dependency on a FR + which is not ready yet. */ + ps = CPU_PROFILE_STATE (cpu); + ps->post_wait = cycles; + vliw = CPU_VLIW (cpu); + slot = vliw->next_slot - 1; + slot = (*vliw->current_vliw)[slot] - UNIT_FM0; + post_wait_for_media (cpu, slot); + post_wait_for_FR (cpu, in_FRi); + post_wait_for_FR (cpu, dual_FRi); + post_wait_for_FR (cpu, in_FRj); + post_wait_for_FR (cpu, dual_FRj); + post_wait_for_FR (cpu, out_FRk); + post_wait_for_FR (cpu, dual_FRk); + + /* Restore the busy cycles of the registers we used. */ + restore_float_register_busy_for_media (cpu, in_FRi, 2, in_FRj, 2, out_FRk, 2); + + /* The latency of the output register will be at least the latency of the + other inputs. Once initiated, post-processing take 1 cycle. */ + update_FR_latency (cpu, out_FRk, ps->post_wait); + update_FR_ptime (cpu, out_FRk, 1); + set_use_is_fr_complex_1 (cpu, out_FRk); + + if (dual_FRk >= 0) + { + update_FR_latency (cpu, dual_FRk, ps->post_wait); + update_FR_ptime (cpu, dual_FRk, 1); + set_use_is_fr_complex_1 (cpu, dual_FRk); + } + + /* the floating point unit resource has a latency of 3 cycles */ + update_float_resource_latency (cpu, slot, cycles + 3); + + return cycles; +} + +int +frvbf_model_fr550_u_media_dual_expand (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_FRi, INT out_FRk) +{ + int cycles; + INT dual_FRk; + FRV_PROFILE_STATE *ps; + FRV_VLIW *vliw; + int slot; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + return 0; + + /* The preprocessing can execute right away. */ + cycles = idesc->timing->units[unit_num].done; + + /* If the previous use of the registers was a media op, + then their latency will be less than previously recorded. + See Table 14-15 in the LSI. */ + dual_FRk = DUAL_REG (out_FRk); + adjust_float_register_busy_for_media (cpu, in_FRi, 1, -1, 1, out_FRk, 2); + + /* The post processing must wait if there is a dependency on a FR + which is not ready yet. */ + ps = CPU_PROFILE_STATE (cpu); + ps->post_wait = cycles; + vliw = CPU_VLIW (cpu); + slot = vliw->next_slot - 1; + slot = (*vliw->current_vliw)[slot] - UNIT_FM0; + post_wait_for_media (cpu, slot); + post_wait_for_FR (cpu, in_FRi); + post_wait_for_FR (cpu, out_FRk); + post_wait_for_FR (cpu, dual_FRk); + + /* Restore the busy cycles of the registers we used. */ + restore_float_register_busy_for_media (cpu, in_FRi, 1, -1, 1, out_FRk, 2); + + /* The latency of the output register will be at least the latency of the + other inputs. Once initiated, post-processing will take 1 cycle. */ + update_FR_latency (cpu, out_FRk, ps->post_wait); + update_FR_ptime (cpu, out_FRk, 1); + set_use_is_fr_complex_1 (cpu, out_FRk); + + if (dual_FRk >= 0) + { + update_FR_latency (cpu, dual_FRk, ps->post_wait); + update_FR_ptime (cpu, dual_FRk, 1); + set_use_is_fr_complex_1 (cpu, dual_FRk); + } + + /* the floating point unit resource has a latency of 3 cycles */ + update_float_resource_latency (cpu, slot, cycles + 3); + + return cycles; +} + +int +frvbf_model_fr550_u_media_3_dual (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_FRi, INT out_FRk) +{ + int cycles; + INT dual_FRi; + FRV_PROFILE_STATE *ps; + FRV_VLIW *vliw; + int slot; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + return 0; + + /* The preprocessing can execute right away. */ + cycles = idesc->timing->units[unit_num].done; + + dual_FRi = DUAL_REG (in_FRi); + + /* The latency of the registers may be less than previously recorded, + depending on how they were used previously. + See Table 14-15 in the LSI. */ + adjust_float_register_busy_for_media (cpu, in_FRi, 2, -1, 1, out_FRk, 1); + + /* The post processing must wait if there is a dependency on a FR + which is not ready yet. */ + ps = CPU_PROFILE_STATE (cpu); + ps->post_wait = cycles; + vliw = CPU_VLIW (cpu); + slot = vliw->next_slot - 1; + slot = (*vliw->current_vliw)[slot] - UNIT_FM0; + post_wait_for_media (cpu, slot); + post_wait_for_FR (cpu, in_FRi); + post_wait_for_FR (cpu, dual_FRi); + post_wait_for_FR (cpu, out_FRk); + + /* Restore the busy cycles of the registers we used. */ + restore_float_register_busy_for_media (cpu, in_FRi, 2, -1, 1, out_FRk, 1); + + /* The latency of the output register will be at least the latency of the + other inputs. Once initiated, post-processing takes 1 cycle. */ + update_FR_latency (cpu, out_FRk, ps->post_wait); + update_FR_ptime (cpu, out_FRk, 1); + + set_use_is_fr_complex_1 (cpu, out_FRk); + + /* the floating point unit resource has a latency of 3 cycles */ + update_float_resource_latency (cpu, slot, cycles + 3); + + return cycles; +} + +int +frvbf_model_fr550_u_media_3_acc (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_FRj, INT in_ACC40Si, + INT out_FRk) +{ + int cycles; + FRV_PROFILE_STATE *ps; + FRV_VLIW *vliw; + int slot; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + return 0; + + /* The preprocessing can execute right away. */ + cycles = idesc->timing->units[unit_num].done; + + /* If the previous use of the registers was a media op, + then their latency will be less than previously recorded. + See Table 14-15 in the LSI. */ + adjust_float_register_busy_for_media (cpu, -1, 1, in_FRj, 1, out_FRk, 1); + + /* The post processing must wait if there is a dependency on a FR + which is not ready yet. */ + ps = CPU_PROFILE_STATE (cpu); + ps->post_wait = cycles; + vliw = CPU_VLIW (cpu); + slot = vliw->next_slot - 1; + slot = (*vliw->current_vliw)[slot] - UNIT_FM0; + post_wait_for_media (cpu, slot); + post_wait_for_FR (cpu, in_FRj); + post_wait_for_FR (cpu, out_FRk); + post_wait_for_ACC (cpu, in_ACC40Si); + + /* Restore the busy cycles of the registers we used. */ + restore_float_register_busy_for_media (cpu, -1, 1, in_FRj, 1, out_FRk, 1); + + /* The latency of tht output register will be at least the latency of the + other inputs. Once initiated, post-processing will take 1 cycle. */ + update_FR_latency (cpu, out_FRk, ps->post_wait); + update_FR_ptime (cpu, out_FRk, 1); + + set_use_is_fr_complex_1 (cpu, out_FRk); + + /* the floating point unit resource has a latency of 3 cycles */ + update_float_resource_latency (cpu, slot, cycles + 3); + + return cycles; +} + +int +frvbf_model_fr550_u_media_3_acc_dual (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_ACC40Si, INT out_FRk) +{ + int cycles; + FRV_PROFILE_STATE *ps; + INT ACC40Si_1; + INT dual_FRk; + FRV_VLIW *vliw; + int slot; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + return 0; + + /* The preprocessing can execute right away. */ + cycles = idesc->timing->units[unit_num].done; + + ACC40Si_1 = DUAL_REG (in_ACC40Si); + dual_FRk = DUAL_REG (out_FRk); + + /* If the previous use of the registers was a media op, + then their latency will be less than previously recorded. + See Table 14-15 in the LSI. */ + adjust_float_register_busy_for_media (cpu, -1, 1, -1, 1, out_FRk, 2); + + /* The post processing must wait if there is a dependency on a FR + which is not ready yet. */ + ps = CPU_PROFILE_STATE (cpu); + ps->post_wait = cycles; + vliw = CPU_VLIW (cpu); + slot = vliw->next_slot - 1; + slot = (*vliw->current_vliw)[slot] - UNIT_FM0; + post_wait_for_media (cpu, slot); + post_wait_for_ACC (cpu, in_ACC40Si); + post_wait_for_ACC (cpu, ACC40Si_1); + post_wait_for_FR (cpu, out_FRk); + post_wait_for_FR (cpu, dual_FRk); + + /* Restore the busy cycles of the registers we used. */ + restore_float_register_busy_for_media (cpu, -1, 1, -1, 1, out_FRk, 2); + + /* The latency of the output register will be at least the latency of the + other inputs. Once initiated, post-processing will take 1 cycle. */ + update_FR_latency (cpu, out_FRk, ps->post_wait); + update_FR_ptime (cpu, out_FRk, 1); + set_use_is_fr_complex_1 (cpu, out_FRk); + if (dual_FRk >= 0) + { + update_FR_latency (cpu, dual_FRk, ps->post_wait); + update_FR_ptime (cpu, dual_FRk, 1); + set_use_is_fr_complex_1 (cpu, dual_FRk); + } + + /* the floating point unit resource has a latency of 3 cycles */ + update_float_resource_latency (cpu, slot, cycles + 3); + + return cycles; +} + +int +frvbf_model_fr550_u_media_3_wtacc (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_FRi, INT out_ACC40Sk) +{ + int cycles; + FRV_PROFILE_STATE *ps; + FRV_VLIW *vliw; + int slot; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + return 0; + + /* The preprocessing can execute right away. */ + cycles = idesc->timing->units[unit_num].done; + + ps = CPU_PROFILE_STATE (cpu); + + /* The latency of the registers may be less than previously recorded, + depending on how they were used previously. + See Table 14-15 in the LSI. */ + adjust_float_register_busy_for_media (cpu, in_FRi, 1, -1, 1, -1, 1); + + /* The post processing must wait if there is a dependency on a FR + which is not ready yet. */ + ps->post_wait = cycles; + vliw = CPU_VLIW (cpu); + slot = vliw->next_slot - 1; + slot = (*vliw->current_vliw)[slot] - UNIT_FM0; + post_wait_for_media (cpu, slot); + post_wait_for_FR (cpu, in_FRi); + post_wait_for_ACC (cpu, out_ACC40Sk); + + /* Restore the busy cycles of the registers we used. */ + restore_float_register_busy_for_media (cpu, in_FRi, 1, -1, 1, -1, 1); + + /* The latency of the output register will be at least the latency of the + other inputs. Once initiated, post-processing will take 1 cycle. */ + update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait); + update_ACC_ptime (cpu, out_ACC40Sk, 1); + set_use_is_acc_mmac (cpu, out_ACC40Sk); + + /* the floating point unit resource has a latency of 3 cycles */ + update_float_resource_latency (cpu, slot, cycles + 3); + + return cycles; +} + +int +frvbf_model_fr550_u_media_3_mclracc (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced) +{ + int cycles; + FRV_PROFILE_STATE *ps; + FRV_VLIW *vliw; + int slot; + int i; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + return 0; + + /* The preprocessing can execute right away. */ + cycles = idesc->timing->units[unit_num].done; + + ps = CPU_PROFILE_STATE (cpu); + + /* The post processing must wait if there is a dependency on a FR + which is not ready yet. */ + ps->post_wait = cycles; + vliw = CPU_VLIW (cpu); + slot = vliw->next_slot - 1; + slot = (*vliw->current_vliw)[slot] - UNIT_FM0; + post_wait_for_media (cpu, slot); + + /* If A was 1 and the accumulator was ACC0, then we must check all + accumulators. Otherwise just wait for the specified accumulator. */ + if (ps->mclracc_A && ps->mclracc_acc == 0) + { + for (i = 0; i < 8; ++i) + post_wait_for_ACC (cpu, i); + } + else + post_wait_for_ACC (cpu, ps->mclracc_acc); + + /* The latency of the output registers will be at least the latency of the + other inputs. Once initiated, post-processing will take 1 cycle. */ + if (ps->mclracc_A && ps->mclracc_acc == 0) + { + for (i = 0; i < 8; ++i) + { + update_ACC_latency (cpu, i, ps->post_wait); + update_ACC_ptime (cpu, i, 1); + set_use_is_acc_mmac (cpu, i); + } + } + else + { + update_ACC_latency (cpu, ps->mclracc_acc, ps->post_wait); + update_ACC_ptime (cpu, ps->mclracc_acc, 1); + set_use_is_acc_mmac (cpu, ps->mclracc_acc); + } + + /* the floating point unit resource has a latency of 3 cycles */ + update_float_resource_latency (cpu, slot, cycles + 3); + + return cycles; +} + +int +frvbf_model_fr550_u_media_set (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT out_FRk) +{ + int cycles; + FRV_PROFILE_STATE *ps; + FRV_VLIW *vliw; + int slot; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + return 0; + + /* The preprocessing can execute right away. */ + cycles = idesc->timing->units[unit_num].done; + + /* If the previous use of the registers was a media op, + then their latency will be less than previously recorded. + See Table 14-15 in the LSI. */ + adjust_float_register_busy_for_media (cpu, -1, 1, -1, 1, out_FRk, 1); + + /* The post processing must wait if there is a dependency on a FR + which is not ready yet. */ + ps = CPU_PROFILE_STATE (cpu); + ps->post_wait = cycles; + vliw = CPU_VLIW (cpu); + slot = vliw->next_slot - 1; + slot = (*vliw->current_vliw)[slot] - UNIT_FM0; + post_wait_for_media (cpu, slot); + post_wait_for_FR (cpu, out_FRk); + + /* Restore the busy cycles of the registers we used. */ + restore_float_register_busy_for_media (cpu, -1, 1, -1, 1, out_FRk, 1); + + /* The latency of the output register will be at least the latency of the + other inputs. Once initiated, post-processing takes 1 cycle. */ + update_FR_latency (cpu, out_FRk, ps->post_wait); + update_FR_ptime (cpu, out_FRk, 1); + fr550_reset_acc_flags (cpu, out_FRk); + + /* the floating point unit resource has a latency of 3 cycles */ + update_float_resource_latency (cpu, slot, cycles + 3); + + return cycles; +} + +int +frvbf_model_fr550_u_media_4 (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_FRi, INT in_FRj, + INT out_ACC40Sk, INT out_ACC40Uk) +{ + int cycles; + INT dual_ACC40Sk; + INT dual_ACC40Uk; + FRV_PROFILE_STATE *ps; + FRV_VLIW *vliw; + int slot; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + return 0; + + /* The preprocessing can execute right away. */ + cycles = idesc->timing->units[unit_num].done; + + ps = CPU_PROFILE_STATE (cpu); + dual_ACC40Sk = DUAL_REG (out_ACC40Sk); + dual_ACC40Uk = DUAL_REG (out_ACC40Uk); + + /* The latency of the registers may be less than previously recorded, + depending on how they were used previously. + See Table 14-15 in the LSI. */ + adjust_acc_busy_for_mmac (cpu, -1, 1, out_ACC40Sk, 2); + adjust_acc_busy_for_mmac (cpu, -1, 1, out_ACC40Uk, 2); + + /* The post processing must wait if there is a dependency on a FR + which is not ready yet. */ + ps->post_wait = cycles; + vliw = CPU_VLIW (cpu); + slot = vliw->next_slot - 1; + slot = (*vliw->current_vliw)[slot] - UNIT_FM0; + post_wait_for_media (cpu, slot); + post_wait_for_FR (cpu, in_FRi); + post_wait_for_FR (cpu, in_FRj); + post_wait_for_ACC (cpu, out_ACC40Sk); + post_wait_for_ACC (cpu, dual_ACC40Sk); + post_wait_for_ACC (cpu, out_ACC40Uk); + post_wait_for_ACC (cpu, dual_ACC40Uk); + + /* Restore the busy cycles of the registers we used. */ + restore_acc_busy_for_mmac (cpu, -1, 1, out_ACC40Sk, 2); + restore_acc_busy_for_mmac (cpu, -1, 1, out_ACC40Uk, 2); + + /* The latency of the output register will be at least the latency of the + other inputs. Once initiated, post-processing will take 1 cycles. */ + if (out_ACC40Sk >= 0) + { + update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait + 1); + set_use_is_acc_mmac (cpu, out_ACC40Sk); + } + if (dual_ACC40Sk >= 0) + { + update_ACC_latency (cpu, dual_ACC40Sk, ps->post_wait + 1); + set_use_is_acc_mmac (cpu, dual_ACC40Sk); + } + if (out_ACC40Uk >= 0) + { + update_ACC_latency (cpu, out_ACC40Uk, ps->post_wait + 1); + set_use_is_acc_mmac (cpu, out_ACC40Uk); + } + if (dual_ACC40Uk >= 0) + { + update_ACC_latency (cpu, dual_ACC40Uk, ps->post_wait + 1); + set_use_is_acc_mmac (cpu, dual_ACC40Uk); + } + + /* the floating point unit resource has a latency of 3 cycles */ + update_float_resource_latency (cpu, slot, cycles + 3); + + return cycles; +} + +int +frvbf_model_fr550_u_media_4_acc (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_ACC40Si, INT out_ACC40Sk) +{ + int cycles; + INT ACC40Si_1; + FRV_PROFILE_STATE *ps; + FRV_VLIW *vliw; + int slot; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + return 0; + + /* The preprocessing can execute right away. */ + cycles = idesc->timing->units[unit_num].done; + + ACC40Si_1 = DUAL_REG (in_ACC40Si); + + ps = CPU_PROFILE_STATE (cpu); + /* The latency of the registers may be less than previously recorded, + depending on how they were used previously. + See Table 14-15 in the LSI. */ + adjust_acc_busy_for_mmac (cpu, in_ACC40Si, 2, out_ACC40Sk, 1); + + /* The post processing must wait if there is a dependency on a register + which is not ready yet. */ + ps->post_wait = cycles; + vliw = CPU_VLIW (cpu); + slot = vliw->next_slot - 1; + slot = (*vliw->current_vliw)[slot] - UNIT_FM0; + post_wait_for_media (cpu, slot); + post_wait_for_ACC (cpu, in_ACC40Si); + post_wait_for_ACC (cpu, ACC40Si_1); + post_wait_for_ACC (cpu, out_ACC40Sk); + + /* Restore the busy cycles of the registers we used. */ + restore_acc_busy_for_mmac (cpu, in_ACC40Si, 2, out_ACC40Sk, 1); + + /* The latency of the output register will be at least the latency of the + other inputs. Once initiated, post-processing will take 1 cycle. */ + update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait + 1); + set_use_is_acc_mmac (cpu, out_ACC40Sk); + + /* the floating point unit resource has a latency of 3 cycles */ + update_float_resource_latency (cpu, slot, cycles + 3); + + return cycles; +} + +int +frvbf_model_fr550_u_media_4_acc_dual (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_ACC40Si, INT out_ACC40Sk) +{ + int cycles; + INT ACC40Si_1; + INT ACC40Si_2; + INT ACC40Si_3; + INT ACC40Sk_1; + FRV_PROFILE_STATE *ps; + FRV_VLIW *vliw; + int slot; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + return 0; + + /* The preprocessing can execute right away. */ + cycles = idesc->timing->units[unit_num].done; + + ACC40Si_1 = DUAL_REG (in_ACC40Si); + ACC40Si_2 = DUAL_REG (ACC40Si_1); + ACC40Si_3 = DUAL_REG (ACC40Si_2); + ACC40Sk_1 = DUAL_REG (out_ACC40Sk); + + ps = CPU_PROFILE_STATE (cpu); + /* The latency of the registers may be less than previously recorded, + depending on how they were used previously. + See Table 14-15 in the LSI. */ + adjust_acc_busy_for_mmac (cpu, in_ACC40Si, 4, out_ACC40Sk, 2); + + /* The post processing must wait if there is a dependency on a register + which is not ready yet. */ + ps->post_wait = cycles; + vliw = CPU_VLIW (cpu); + slot = vliw->next_slot - 1; + slot = (*vliw->current_vliw)[slot] - UNIT_FM0; + post_wait_for_media (cpu, slot); + post_wait_for_ACC (cpu, in_ACC40Si); + post_wait_for_ACC (cpu, ACC40Si_1); + post_wait_for_ACC (cpu, ACC40Si_2); + post_wait_for_ACC (cpu, ACC40Si_3); + post_wait_for_ACC (cpu, out_ACC40Sk); + post_wait_for_ACC (cpu, ACC40Sk_1); + + /* Restore the busy cycles of the registers we used. */ + restore_acc_busy_for_mmac (cpu, in_ACC40Si, 4, out_ACC40Sk, 2); + + /* The latency of the output register will be at least the latency of the + other inputs. Once initiated, post-processing will take 1 cycle. */ + update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait + 1); + set_use_is_acc_mmac (cpu, out_ACC40Sk); + if (ACC40Sk_1 >= 0) + { + update_ACC_latency (cpu, ACC40Sk_1, ps->post_wait + 1); + set_use_is_acc_mmac (cpu, ACC40Sk_1); + } + + /* the floating point unit resource has a latency of 3 cycles */ + update_float_resource_latency (cpu, slot, cycles + 3); + + return cycles; +} + +int +frvbf_model_fr550_u_media_4_add_sub (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_ACC40Si, INT out_ACC40Sk) +{ + int cycles; + INT ACC40Si_1; + INT ACC40Sk_1; + FRV_PROFILE_STATE *ps; + FRV_VLIW *vliw; + int slot; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + return 0; + + /* The preprocessing can execute right away. */ + cycles = idesc->timing->units[unit_num].done; + + ACC40Si_1 = DUAL_REG (in_ACC40Si); + ACC40Sk_1 = DUAL_REG (out_ACC40Sk); + + ps = CPU_PROFILE_STATE (cpu); + /* The latency of the registers may be less than previously recorded, + depending on how they were used previously. + See Table 14-15 in the LSI. */ + adjust_acc_busy_for_mmac (cpu, in_ACC40Si, 2, out_ACC40Sk, 2); + + /* The post processing must wait if there is a dependency on a register + which is not ready yet. */ + ps->post_wait = cycles; + vliw = CPU_VLIW (cpu); + slot = vliw->next_slot - 1; + slot = (*vliw->current_vliw)[slot] - UNIT_FM0; + post_wait_for_media (cpu, slot); + post_wait_for_ACC (cpu, in_ACC40Si); + post_wait_for_ACC (cpu, ACC40Si_1); + post_wait_for_ACC (cpu, out_ACC40Sk); + post_wait_for_ACC (cpu, ACC40Sk_1); + + /* Restore the busy cycles of the registers we used. */ + restore_acc_busy_for_mmac (cpu, in_ACC40Si, 2, out_ACC40Sk, 2); + + /* The latency of the output register will be at least the latency of the + other inputs. Once initiated, post-processing will take 1 cycle. */ + update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait + 1); + set_use_is_acc_mmac (cpu, out_ACC40Sk); + if (ACC40Sk_1 >= 0) + { + update_ACC_latency (cpu, ACC40Sk_1, ps->post_wait + 1); + set_use_is_acc_mmac (cpu, ACC40Sk_1); + } + + /* the floating point unit resource has a latency of 3 cycles */ + update_float_resource_latency (cpu, slot, cycles + 3); + + return cycles; +} + +int +frvbf_model_fr550_u_media_4_add_sub_dual (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_ACC40Si, INT out_ACC40Sk) +{ + int cycles; + INT ACC40Si_1; + INT ACC40Si_2; + INT ACC40Si_3; + INT ACC40Sk_1; + INT ACC40Sk_2; + INT ACC40Sk_3; + FRV_PROFILE_STATE *ps; + FRV_VLIW *vliw; + int slot; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + return 0; + + /* The preprocessing can execute right away. */ + cycles = idesc->timing->units[unit_num].done; + + ACC40Si_1 = DUAL_REG (in_ACC40Si); + ACC40Si_2 = DUAL_REG (ACC40Si_1); + ACC40Si_3 = DUAL_REG (ACC40Si_2); + ACC40Sk_1 = DUAL_REG (out_ACC40Sk); + ACC40Sk_2 = DUAL_REG (ACC40Sk_1); + ACC40Sk_3 = DUAL_REG (ACC40Sk_2); + + ps = CPU_PROFILE_STATE (cpu); + /* The latency of the registers may be less than previously recorded, + depending on how they were used previously. + See Table 14-15 in the LSI. */ + adjust_acc_busy_for_mmac (cpu, in_ACC40Si, 4, out_ACC40Sk, 4); + + /* The post processing must wait if there is a dependency on a register + which is not ready yet. */ + ps->post_wait = cycles; + vliw = CPU_VLIW (cpu); + slot = vliw->next_slot - 1; + slot = (*vliw->current_vliw)[slot] - UNIT_FM0; + post_wait_for_media (cpu, slot); + post_wait_for_ACC (cpu, in_ACC40Si); + post_wait_for_ACC (cpu, ACC40Si_1); + post_wait_for_ACC (cpu, ACC40Si_2); + post_wait_for_ACC (cpu, ACC40Si_3); + post_wait_for_ACC (cpu, out_ACC40Sk); + post_wait_for_ACC (cpu, ACC40Sk_1); + post_wait_for_ACC (cpu, ACC40Sk_2); + post_wait_for_ACC (cpu, ACC40Sk_3); + + /* Restore the busy cycles of the registers we used. */ + restore_acc_busy_for_mmac (cpu, in_ACC40Si, 4, out_ACC40Sk, 4); + + /* The latency of the output register will be at least the latency of the + other inputs. Once initiated, post-processing will take 1 cycle. */ + update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait + 1); + set_use_is_acc_mmac (cpu, out_ACC40Sk); + if (ACC40Sk_1 >= 0) + { + update_ACC_latency (cpu, ACC40Sk_1, ps->post_wait + 1); + set_use_is_acc_mmac (cpu, ACC40Sk_1); + } + if (ACC40Sk_2 >= 0) + { + update_ACC_latency (cpu, ACC40Sk_2, ps->post_wait + 1); + set_use_is_acc_mmac (cpu, ACC40Sk_2); + } + if (ACC40Sk_3 >= 0) + { + update_ACC_latency (cpu, ACC40Sk_3, ps->post_wait + 1); + set_use_is_acc_mmac (cpu, ACC40Sk_3); + } + + /* the floating point unit resource has a latency of 3 cycles */ + update_float_resource_latency (cpu, slot, cycles + 3); + + return cycles; +} + +int +frvbf_model_fr550_u_media_4_quad (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_FRi, INT in_FRj, + INT out_ACC40Sk, INT out_ACC40Uk) +{ + int cycles; + INT dual_FRi; + INT dual_FRj; + INT ACC40Sk_1; + INT ACC40Sk_2; + INT ACC40Sk_3; + INT ACC40Uk_1; + INT ACC40Uk_2; + INT ACC40Uk_3; + FRV_PROFILE_STATE *ps; + FRV_VLIW *vliw; + int slot; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + return 0; + + /* The preprocessing can execute right away. */ + cycles = idesc->timing->units[unit_num].done; + + dual_FRi = DUAL_REG (in_FRi); + dual_FRj = DUAL_REG (in_FRj); + ACC40Sk_1 = DUAL_REG (out_ACC40Sk); + ACC40Sk_2 = DUAL_REG (ACC40Sk_1); + ACC40Sk_3 = DUAL_REG (ACC40Sk_2); + ACC40Uk_1 = DUAL_REG (out_ACC40Uk); + ACC40Uk_2 = DUAL_REG (ACC40Uk_1); + ACC40Uk_3 = DUAL_REG (ACC40Uk_2); + + ps = CPU_PROFILE_STATE (cpu); + /* The latency of the registers may be less than previously recorded, + depending on how they were used previously. + See Table 14-15 in the LSI. */ + adjust_float_register_busy_for_media (cpu, in_FRi, 2, in_FRj, 2, -1, 1); + adjust_acc_busy_for_mmac (cpu, -1, 1, out_ACC40Sk, 4); + adjust_acc_busy_for_mmac (cpu, -1, 1, out_ACC40Uk, 4); + + /* The post processing must wait if there is a dependency on a FR + which is not ready yet. */ + ps->post_wait = cycles; + vliw = CPU_VLIW (cpu); + slot = vliw->next_slot - 1; + slot = (*vliw->current_vliw)[slot] - UNIT_FM0; + post_wait_for_media (cpu, slot); + post_wait_for_FR (cpu, in_FRi); + post_wait_for_FR (cpu, dual_FRi); + post_wait_for_FR (cpu, in_FRj); + post_wait_for_FR (cpu, dual_FRj); + post_wait_for_ACC (cpu, out_ACC40Sk); + post_wait_for_ACC (cpu, ACC40Sk_1); + post_wait_for_ACC (cpu, ACC40Sk_2); + post_wait_for_ACC (cpu, ACC40Sk_3); + post_wait_for_ACC (cpu, out_ACC40Uk); + post_wait_for_ACC (cpu, ACC40Uk_1); + post_wait_for_ACC (cpu, ACC40Uk_2); + post_wait_for_ACC (cpu, ACC40Uk_3); + + /* Restore the busy cycles of the registers we used. */ + restore_float_register_busy_for_media (cpu, in_FRi, 2, in_FRj, 2, -1, 1); + restore_acc_busy_for_mmac (cpu, -1, 1, out_ACC40Sk, 4); + restore_acc_busy_for_mmac (cpu, -1, 1, out_ACC40Uk, 4); + + /* The latency of the output register will be at least the latency of the + other inputs. Once initiated, post-processing will take 1 cycle. */ + if (out_ACC40Sk >= 0) + { + update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait + 1); + + set_use_is_acc_mmac (cpu, out_ACC40Sk); + if (ACC40Sk_1 >= 0) + { + update_ACC_latency (cpu, ACC40Sk_1, ps->post_wait + 1); + + set_use_is_acc_mmac (cpu, ACC40Sk_1); + } + if (ACC40Sk_2 >= 0) + { + update_ACC_latency (cpu, ACC40Sk_2, ps->post_wait + 1); + + set_use_is_acc_mmac (cpu, ACC40Sk_2); + } + if (ACC40Sk_3 >= 0) + { + update_ACC_latency (cpu, ACC40Sk_3, ps->post_wait + 1); + + set_use_is_acc_mmac (cpu, ACC40Sk_3); + } + } + else if (out_ACC40Uk >= 0) + { + update_ACC_latency (cpu, out_ACC40Uk, ps->post_wait + 1); + + set_use_is_acc_mmac (cpu, out_ACC40Uk); + if (ACC40Uk_1 >= 0) + { + update_ACC_latency (cpu, ACC40Uk_1, ps->post_wait + 1); + + set_use_is_acc_mmac (cpu, ACC40Uk_1); + } + if (ACC40Uk_2 >= 0) + { + update_ACC_latency (cpu, ACC40Uk_2, ps->post_wait + 1); + + set_use_is_acc_mmac (cpu, ACC40Uk_2); + } + if (ACC40Uk_3 >= 0) + { + update_ACC_latency (cpu, ACC40Uk_3, ps->post_wait + 1); + + set_use_is_acc_mmac (cpu, ACC40Uk_3); + } + } + + /* the floating point unit resource has a latency of 3 cycles */ + update_float_resource_latency (cpu, slot, cycles + 3); + + return cycles; +} + +#endif /* WITH_PROFILE_MODEL_P */ diff --git a/sim/frv/profile-fr550.h b/sim/frv/profile-fr550.h new file mode 100644 index 0000000..0a1659b --- /dev/null +++ b/sim/frv/profile-fr550.h @@ -0,0 +1,27 @@ +/* Profiling definitions for the fr550 model of the FRV simulator + Copyright (C) 2003 Free Software Foundation, Inc. + Contributed by Red Hat. + +This file is part of the GNU Simulators. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef PROFILE_FR550_H +#define PROFILE_FR550_H + +void fr550_model_insn_before (SIM_CPU *, int); +void fr550_model_insn_after (SIM_CPU *, int, int); + +#endif /* PROFILE_FR550_H */ diff --git a/sim/frv/profile.c b/sim/frv/profile.c new file mode 100644 index 0000000..3a3d1aa --- /dev/null +++ b/sim/frv/profile.c @@ -0,0 +1,2077 @@ +/* frv simulator machine independent profiling code. + + Copyright (C) 1998, 1999, 2000, 2001, 2003 Free Software Foundation, Inc. + Contributed by Red Hat + +This file is part of the GNU simulators. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +*/ +#define WANT_CPU +#define WANT_CPU_FRVBF + +#include "sim-main.h" +#include "bfd.h" + +#if WITH_PROFILE_MODEL_P + +#include "profile.h" +#include "profile-fr400.h" +#include "profile-fr500.h" +#include "profile-fr550.h" + +static void +reset_gr_flags (SIM_CPU *cpu, INT gr) +{ + SIM_DESC sd = CPU_STATE (cpu); + if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr400) + fr400_reset_gr_flags (cpu, gr); + /* Other machines have no gr flags right now. */ +} + +static void +reset_fr_flags (SIM_CPU *cpu, INT fr) +{ + SIM_DESC sd = CPU_STATE (cpu); + if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr400) + fr400_reset_fr_flags (cpu, fr); + else if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr500) + fr500_reset_fr_flags (cpu, fr); +} + +static void +reset_acc_flags (SIM_CPU *cpu, INT acc) +{ + SIM_DESC sd = CPU_STATE (cpu); + if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr400) + fr400_reset_acc_flags (cpu, acc); + /* Other machines have no acc flags right now. */ +} + +static void +reset_cc_flags (SIM_CPU *cpu, INT cc) +{ + SIM_DESC sd = CPU_STATE (cpu); + if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr500) + fr500_reset_cc_flags (cpu, cc); + /* Other machines have no cc flags. */ +} + +void +set_use_is_gr_complex (SIM_CPU *cpu, INT gr) +{ + if (gr != -1) + { + FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu); + reset_gr_flags (cpu, gr); + ps->cur_gr_complex |= (((DI)1) << gr); + } +} + +void +set_use_not_gr_complex (SIM_CPU *cpu, INT gr) +{ + if (gr != -1) + { + FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu); + ps->cur_gr_complex &= ~(((DI)1) << gr); + } +} + +int +use_is_gr_complex (SIM_CPU *cpu, INT gr) +{ + if (gr != -1) + { + FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu); + return ps->cur_gr_complex & (((DI)1) << gr); + } + return 0; +} + +/* Globals flag indicates whether this insn is being modeled. */ +enum FRV_INSN_MODELING model_insn = FRV_INSN_NO_MODELING; + +/* static buffer for the name of the currently most restrictive hazard. */ +static char hazard_name[100] = ""; + +/* Print information about the wait applied to an entire VLIW insn. */ +FRV_INSN_FETCH_BUFFER frv_insn_fetch_buffer[] += { + {1, NO_REQNO}, {1, NO_REQNO} /* init with impossible address. */ +}; + +enum cache_request +{ + cache_load, + cache_invalidate, + cache_flush, + cache_preload, + cache_unlock +}; + +/* A queue of load requests from the data cache. Use to keep track of loads + which are still pending. */ +/* TODO -- some of these are mutually exclusive and can use a union. */ +typedef struct +{ + FRV_CACHE *cache; + unsigned reqno; + SI address; + int length; + int is_signed; + int regnum; + int cycles; + int regtype; + int lock; + int all; + int slot; + int active; + enum cache_request request; +} CACHE_QUEUE_ELEMENT; + +#define CACHE_QUEUE_SIZE 64 /* TODO -- make queue dynamic */ +struct +{ + unsigned reqno; + int ix; + CACHE_QUEUE_ELEMENT q[CACHE_QUEUE_SIZE]; +} cache_queue = {0, 0}; + +/* Queue a request for a load from the cache. The load will be queued as + 'inactive' and will be requested after the given number + of cycles have passed from the point the load is activated. */ +void +request_cache_load (SIM_CPU *cpu, INT regnum, int regtype, int cycles) +{ + CACHE_QUEUE_ELEMENT *q; + FRV_VLIW *vliw; + int slot; + + /* For a conditional load which was not executed, CPU_LOAD_LENGTH will be + zero. */ + if (CPU_LOAD_LENGTH (cpu) == 0) + return; + + if (cache_queue.ix >= CACHE_QUEUE_SIZE) + abort (); /* TODO: Make the queue dynamic */ + + q = & cache_queue.q[cache_queue.ix]; + ++cache_queue.ix; + + q->reqno = cache_queue.reqno++; + q->request = cache_load; + q->cache = CPU_DATA_CACHE (cpu); + q->address = CPU_LOAD_ADDRESS (cpu); + q->length = CPU_LOAD_LENGTH (cpu); + q->is_signed = CPU_LOAD_SIGNED (cpu); + q->regnum = regnum; + q->regtype = regtype; + q->cycles = cycles; + q->active = 0; + + vliw = CPU_VLIW (cpu); + slot = vliw->next_slot - 1; + q->slot = (*vliw->current_vliw)[slot]; + + CPU_LOAD_LENGTH (cpu) = 0; +} + +/* Queue a request to flush the cache. The request will be queued as + 'inactive' and will be requested after the given number + of cycles have passed from the point the request is activated. */ +void +request_cache_flush (SIM_CPU *cpu, FRV_CACHE *cache, int cycles) +{ + CACHE_QUEUE_ELEMENT *q; + FRV_VLIW *vliw; + int slot; + + if (cache_queue.ix >= CACHE_QUEUE_SIZE) + abort (); /* TODO: Make the queue dynamic */ + + q = & cache_queue.q[cache_queue.ix]; + ++cache_queue.ix; + + q->reqno = cache_queue.reqno++; + q->request = cache_flush; + q->cache = cache; + q->address = CPU_LOAD_ADDRESS (cpu); + q->all = CPU_PROFILE_STATE (cpu)->all_cache_entries; + q->cycles = cycles; + q->active = 0; + + vliw = CPU_VLIW (cpu); + slot = vliw->next_slot - 1; + q->slot = (*vliw->current_vliw)[slot]; +} + +/* Queue a request to invalidate the cache. The request will be queued as + 'inactive' and will be requested after the given number + of cycles have passed from the point the request is activated. */ +void +request_cache_invalidate (SIM_CPU *cpu, FRV_CACHE *cache, int cycles) +{ + CACHE_QUEUE_ELEMENT *q; + FRV_VLIW *vliw; + int slot; + + if (cache_queue.ix >= CACHE_QUEUE_SIZE) + abort (); /* TODO: Make the queue dynamic */ + + q = & cache_queue.q[cache_queue.ix]; + ++cache_queue.ix; + + q->reqno = cache_queue.reqno++; + q->request = cache_invalidate; + q->cache = cache; + q->address = CPU_LOAD_ADDRESS (cpu); + q->all = CPU_PROFILE_STATE (cpu)->all_cache_entries; + q->cycles = cycles; + q->active = 0; + + vliw = CPU_VLIW (cpu); + slot = vliw->next_slot - 1; + q->slot = (*vliw->current_vliw)[slot]; +} + +/* Queue a request to preload the cache. The request will be queued as + 'inactive' and will be requested after the given number + of cycles have passed from the point the request is activated. */ +void +request_cache_preload (SIM_CPU *cpu, FRV_CACHE *cache, int cycles) +{ + CACHE_QUEUE_ELEMENT *q; + FRV_VLIW *vliw; + int slot; + + if (cache_queue.ix >= CACHE_QUEUE_SIZE) + abort (); /* TODO: Make the queue dynamic */ + + q = & cache_queue.q[cache_queue.ix]; + ++cache_queue.ix; + + q->reqno = cache_queue.reqno++; + q->request = cache_preload; + q->cache = cache; + q->address = CPU_LOAD_ADDRESS (cpu); + q->length = CPU_LOAD_LENGTH (cpu); + q->lock = CPU_LOAD_LOCK (cpu); + q->cycles = cycles; + q->active = 0; + + vliw = CPU_VLIW (cpu); + slot = vliw->next_slot - 1; + q->slot = (*vliw->current_vliw)[slot]; + + CPU_LOAD_LENGTH (cpu) = 0; +} + +/* Queue a request to unlock the cache. The request will be queued as + 'inactive' and will be requested after the given number + of cycles have passed from the point the request is activated. */ +void +request_cache_unlock (SIM_CPU *cpu, FRV_CACHE *cache, int cycles) +{ + CACHE_QUEUE_ELEMENT *q; + FRV_VLIW *vliw; + int slot; + + if (cache_queue.ix >= CACHE_QUEUE_SIZE) + abort (); /* TODO: Make the queue dynamic */ + + q = & cache_queue.q[cache_queue.ix]; + ++cache_queue.ix; + + q->reqno = cache_queue.reqno++; + q->request = cache_unlock; + q->cache = cache; + q->address = CPU_LOAD_ADDRESS (cpu); + q->cycles = cycles; + q->active = 0; + + vliw = CPU_VLIW (cpu); + slot = vliw->next_slot - 1; + q->slot = (*vliw->current_vliw)[slot]; +} + +static void +submit_cache_request (CACHE_QUEUE_ELEMENT *q) +{ + switch (q->request) + { + case cache_load: + frv_cache_request_load (q->cache, q->reqno, q->address, q->slot); + break; + case cache_flush: + frv_cache_request_invalidate (q->cache, q->reqno, q->address, q->slot, + q->all, 1/*flush*/); + break; + case cache_invalidate: + frv_cache_request_invalidate (q->cache, q->reqno, q->address, q->slot, + q->all, 0/*flush*/); + break; + case cache_preload: + frv_cache_request_preload (q->cache, q->address, q->slot, + q->length, q->lock); + break; + case cache_unlock: + frv_cache_request_unlock (q->cache, q->address, q->slot); + break; + default: + abort (); + } +} + +/* Activate all inactive load requests. */ +static void +activate_cache_requests (SIM_CPU *cpu) +{ + int i; + for (i = 0; i < cache_queue.ix; ++i) + { + CACHE_QUEUE_ELEMENT *q = & cache_queue.q[i]; + if (! q->active) + { + q->active = 1; + /* Submit the request now if the cycle count is zero. */ + if (q->cycles == 0) + submit_cache_request (q); + } + } +} + +/* Check to see if a load is pending which affects the given register(s). + */ +int +load_pending_for_register (SIM_CPU *cpu, int regnum, int words, int regtype) +{ + int i; + for (i = 0; i < cache_queue.ix; ++i) + { + CACHE_QUEUE_ELEMENT *q = & cache_queue.q[i]; + + /* Must be the same kind of register. */ + if (! q->active || q->request != cache_load || q->regtype != regtype) + continue; + + /* If the registers numbers are equal, then we have a match. */ + if (q->regnum == regnum) + return 1; /* load pending */ + + /* Check for overlap of a load with a multi-word register. */ + if (regnum < q->regnum) + { + if (regnum + words > q->regnum) + return 1; + } + /* Check for overlap of a multi-word load with the register. */ + else + { + int data_words = (q->length + sizeof (SI) - 1) / sizeof (SI); + if (q->regnum + data_words > regnum) + return 1; + } + } + + return 0; /* no load pending */ +} + +/* Check to see if a cache flush pending which affects the given address. */ +static int +flush_pending_for_address (SIM_CPU *cpu, SI address) +{ + int line_mask = ~(CPU_DATA_CACHE (cpu)->line_size - 1); + int i; + for (i = 0; i < cache_queue.ix; ++i) + { + CACHE_QUEUE_ELEMENT *q = & cache_queue.q[i]; + + /* Must be the same kind of request and active. */ + if (! q->active || q->request != cache_flush) + continue; + + /* If the addresses are equal, then we have a match. */ + if ((q->address & line_mask) == (address & line_mask)) + return 1; /* flush pending */ + } + + return 0; /* no flush pending */ +} + +static void +remove_cache_queue_element (SIM_CPU *cpu, int i) +{ + /* If we are removing the load of a FR register, then remember which one(s). + */ + CACHE_QUEUE_ELEMENT q = cache_queue.q[i]; + + for (--cache_queue.ix; i < cache_queue.ix; ++i) + cache_queue.q[i] = cache_queue.q[i + 1]; + + /* If we removed a load of a FR register, check to see if any other loads + of that register is still queued. If not, then apply the queued post + processing time of that register to its latency. Also apply + 1 extra cycle of latency to the register since it was a floating point + load. */ + if (q.request == cache_load && q.regtype != REGTYPE_NONE) + { + FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu); + int data_words = (q.length + sizeof (SI) - 1) / sizeof (SI); + int j; + for (j = 0; j < data_words; ++j) + { + int regnum = q.regnum + j; + if (! load_pending_for_register (cpu, regnum, 1, q.regtype)) + { + if (q.regtype == REGTYPE_FR) + { + int *fr = ps->fr_busy; + fr[regnum] += 1 + ps->fr_ptime[regnum]; + ps->fr_ptime[regnum] = 0; + } + } + } + } +} + +/* Copy data from the cache buffer to the target register(s). */ +static void +copy_load_data (SIM_CPU *current_cpu, FRV_CACHE *cache, int slot, + CACHE_QUEUE_ELEMENT *q) +{ + switch (q->length) + { + case 1: + if (q->regtype == REGTYPE_FR) + { + if (q->is_signed) + { + QI value = CACHE_RETURN_DATA (cache, slot, q->address, QI, 1); + SET_H_FR (q->regnum, value); + } + else + { + UQI value = CACHE_RETURN_DATA (cache, slot, q->address, UQI, 1); + SET_H_FR (q->regnum, value); + } + } + else + { + if (q->is_signed) + { + QI value = CACHE_RETURN_DATA (cache, slot, q->address, QI, 1); + SET_H_GR (q->regnum, value); + } + else + { + UQI value = CACHE_RETURN_DATA (cache, slot, q->address, UQI, 1); + SET_H_GR (q->regnum, value); + } + } + break; + case 2: + if (q->regtype == REGTYPE_FR) + { + if (q->is_signed) + { + HI value = CACHE_RETURN_DATA (cache, slot, q->address, HI, 2); + SET_H_FR (q->regnum, value); + } + else + { + UHI value = CACHE_RETURN_DATA (cache, slot, q->address, UHI, 2); + SET_H_FR (q->regnum, value); + } + } + else + { + if (q->is_signed) + { + HI value = CACHE_RETURN_DATA (cache, slot, q->address, HI, 2); + SET_H_GR (q->regnum, value); + } + else + { + UHI value = CACHE_RETURN_DATA (cache, slot, q->address, UHI, 2); + SET_H_GR (q->regnum, value); + } + } + break; + case 4: + if (q->regtype == REGTYPE_FR) + { + SET_H_FR (q->regnum, + CACHE_RETURN_DATA (cache, slot, q->address, SF, 4)); + } + else + { + SET_H_GR (q->regnum, + CACHE_RETURN_DATA (cache, slot, q->address, SI, 4)); + } + break; + case 8: + if (q->regtype == REGTYPE_FR) + { + SET_H_FR_DOUBLE (q->regnum, + CACHE_RETURN_DATA (cache, slot, q->address, DF, 8)); + } + else + { + SET_H_GR_DOUBLE (q->regnum, + CACHE_RETURN_DATA (cache, slot, q->address, DI, 8)); + } + break; + case 16: + if (q->regtype == REGTYPE_FR) + frvbf_h_fr_quad_set_handler (current_cpu, q->regnum, + CACHE_RETURN_DATA_ADDRESS (cache, slot, + q->address, + 16)); + else + frvbf_h_gr_quad_set_handler (current_cpu, q->regnum, + CACHE_RETURN_DATA_ADDRESS (cache, slot, + q->address, + 16)); + break; + default: + abort (); + } +} + +static int +request_complete (SIM_CPU *cpu, CACHE_QUEUE_ELEMENT *q) +{ + FRV_CACHE* cache; + if (! q->active || q->cycles > 0) + return 0; + + cache = CPU_DATA_CACHE (cpu); + switch (q->request) + { + case cache_load: + /* For loads, we must wait until the data is returned from the cache. */ + if (frv_cache_data_in_buffer (cache, 0, q->address, q->reqno)) + { + copy_load_data (cpu, cache, 0, q); + return 1; + } + if (frv_cache_data_in_buffer (cache, 1, q->address, q->reqno)) + { + copy_load_data (cpu, cache, 1, q); + return 1; + } + break; + + case cache_flush: + /* We must wait until the data is flushed. */ + if (frv_cache_data_flushed (cache, 0, q->address, q->reqno)) + return 1; + if (frv_cache_data_flushed (cache, 1, q->address, q->reqno)) + return 1; + break; + + default: + /* All other requests are complete once they've been made. */ + return 1; + } + + return 0; +} + +/* Run the insn and data caches through the given number of cycles, taking + note of load requests which are fullfilled as a result. */ +static void +run_caches (SIM_CPU *cpu, int cycles) +{ + FRV_CACHE* data_cache = CPU_DATA_CACHE (cpu); + FRV_CACHE* insn_cache = CPU_INSN_CACHE (cpu); + int i; + /* For each cycle, run the caches, noting which requests have been fullfilled + and submitting new requests on their designated cycles. */ + for (i = 0; i < cycles; ++i) + { + int j; + /* Run the caches through 1 cycle. */ + frv_cache_run (data_cache, 1); + frv_cache_run (insn_cache, 1); + + /* Note whether prefetched insn data has been loaded yet. */ + for (j = LS; j < FRV_CACHE_PIPELINES; ++j) + { + if (frv_insn_fetch_buffer[j].reqno != NO_REQNO + && frv_cache_data_in_buffer (insn_cache, j, + frv_insn_fetch_buffer[j].address, + frv_insn_fetch_buffer[j].reqno)) + frv_insn_fetch_buffer[j].reqno = NO_REQNO; + } + + /* Check to see which requests have been satisfied and which should + be submitted now. */ + for (j = 0; j < cache_queue.ix; ++j) + { + CACHE_QUEUE_ELEMENT *q = & cache_queue.q[j]; + if (! q->active) + continue; + + /* If a load has been satisfied, complete the operation and remove it + from the queue. */ + if (request_complete (cpu, q)) + { + remove_cache_queue_element (cpu, j); + --j; + continue; + } + + /* Decrease the cycle count of each queued request. + Submit a request for each queued request whose cycle count has + become zero. */ + --q->cycles; + if (q->cycles == 0) + submit_cache_request (q); + } + } +} + +static void +apply_latency_adjustments (SIM_CPU *cpu) +{ + FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu); + int i; + /* update the latencies of the registers. */ + int *fr = ps->fr_busy; + int *acc = ps->acc_busy; + for (i = 0; i < 64; ++i) + { + if (ps->fr_busy_adjust[i] > 0) + *fr -= ps->fr_busy_adjust[i]; /* OK if it goes negative. */ + if (ps->acc_busy_adjust[i] > 0) + *acc -= ps->acc_busy_adjust[i]; /* OK if it goes negative. */ + ++fr; + ++acc; + } +} + +/* Account for the number of cycles which have just passed in the latency of + various system elements. Works for negative cycles too so that latency + can be extended in the case of insn fetch latency. + If negative or zero, then no adjustment is necessary. */ +static void +update_latencies (SIM_CPU *cpu, int cycles) +{ + FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu); + int i; + /* update the latencies of the registers. */ + int *fdiv; + int *fsqrt; + int *idiv; + int *flt; + int *media; + int *ccr; + int *gr = ps->gr_busy; + int *fr = ps->fr_busy; + int *acc = ps->acc_busy; + int *spr; + /* This loop handles GR, FR and ACC registers. */ + for (i = 0; i < 64; ++i) + { + if (*gr <= cycles) + { + *gr = 0; + reset_gr_flags (cpu, i); + } + else + *gr -= cycles; + /* If the busy drops to 0, then mark the register as + "not in use". */ + if (*fr <= cycles) + { + int *fr_lat = ps->fr_latency + i; + *fr = 0; + ps->fr_busy_adjust[i] = 0; + /* Only clear flags if this register has no target latency. */ + if (*fr_lat == 0) + reset_fr_flags (cpu, i); + } + else + *fr -= cycles; + /* If the busy drops to 0, then mark the register as + "not in use". */ + if (*acc <= cycles) + { + int *acc_lat = ps->acc_latency + i; + *acc = 0; + ps->acc_busy_adjust[i] = 0; + /* Only clear flags if this register has no target latency. */ + if (*acc_lat == 0) + reset_acc_flags (cpu, i); + } + else + *acc -= cycles; + ++gr; + ++fr; + ++acc; + } + /* This loop handles CCR registers. */ + ccr = ps->ccr_busy; + for (i = 0; i < 8; ++i) + { + if (*ccr <= cycles) + { + *ccr = 0; + reset_cc_flags (cpu, i); + } + else + *ccr -= cycles; + ++ccr; + } + /* This loop handles SPR registers. */ + spr = ps->spr_busy; + for (i = 0; i < 4096; ++i) + { + if (*spr <= cycles) + *spr = 0; + else + *spr -= cycles; + ++spr; + } + /* This loop handles resources. */ + idiv = ps->idiv_busy; + fdiv = ps->fdiv_busy; + fsqrt = ps->fsqrt_busy; + for (i = 0; i < 2; ++i) + { + *idiv = (*idiv <= cycles) ? 0 : (*idiv - cycles); + *fdiv = (*fdiv <= cycles) ? 0 : (*fdiv - cycles); + *fsqrt = (*fsqrt <= cycles) ? 0 : (*fsqrt - cycles); + ++idiv; + ++fdiv; + ++fsqrt; + } + /* Float and media units can occur in 4 slots on some machines. */ + flt = ps->float_busy; + media = ps->media_busy; + for (i = 0; i < 4; ++i) + { + *flt = (*flt <= cycles) ? 0 : (*flt - cycles); + *media = (*media <= cycles) ? 0 : (*media - cycles); + ++flt; + ++media; + } +} + +/* Print information about the wait for the given number of cycles. */ +void +frv_model_trace_wait_cycles (SIM_CPU *cpu, int cycles, const char *hazard_name) +{ + if (TRACE_INSN_P (cpu) && cycles > 0) + { + SIM_DESC sd = CPU_STATE (cpu); + trace_printf (sd, cpu, "**** %s wait %d cycles ***\n", + hazard_name, cycles); + } +} + +void +trace_vliw_wait_cycles (SIM_CPU *cpu) +{ + if (TRACE_INSN_P (cpu)) + { + FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu); + frv_model_trace_wait_cycles (cpu, ps->vliw_wait, hazard_name); + } +} + +/* Wait for the given number of cycles. */ +void +frv_model_advance_cycles (SIM_CPU *cpu, int cycles) +{ + PROFILE_DATA *p = CPU_PROFILE_DATA (cpu); + update_latencies (cpu, cycles); + run_caches (cpu, cycles); + PROFILE_MODEL_TOTAL_CYCLES (p) += cycles; +} + +void +handle_resource_wait (SIM_CPU *cpu) +{ + FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu); + if (ps->vliw_wait != 0) + frv_model_advance_cycles (cpu, ps->vliw_wait); + if (ps->vliw_load_stall > ps->vliw_wait) + ps->vliw_load_stall -= ps->vliw_wait; + else + ps->vliw_load_stall = 0; +} + +/* Account for the number of cycles until these resources will be available + again. */ +static void +update_target_latencies (SIM_CPU *cpu) +{ + FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu); + int i; + /* update the latencies of the registers. */ + int *ccr_lat; + int *gr_lat = ps->gr_latency; + int *fr_lat = ps->fr_latency; + int *acc_lat = ps->acc_latency; + int *spr_lat; + int *ccr; + int *gr = ps->gr_busy; + int *fr = ps->fr_busy; + int *acc = ps->acc_busy; + int *spr; + /* This loop handles GR, FR and ACC registers. */ + for (i = 0; i < 64; ++i) + { + if (*gr_lat) + { + *gr = *gr_lat; + *gr_lat = 0; + } + if (*fr_lat) + { + *fr = *fr_lat; + *fr_lat = 0; + } + if (*acc_lat) + { + *acc = *acc_lat; + *acc_lat = 0; + } + ++gr; ++gr_lat; + ++fr; ++fr_lat; + ++acc; ++acc_lat; + } + /* This loop handles CCR registers. */ + ccr = ps->ccr_busy; + ccr_lat = ps->ccr_latency; + for (i = 0; i < 8; ++i) + { + if (*ccr_lat) + { + *ccr = *ccr_lat; + *ccr_lat = 0; + } + ++ccr; ++ccr_lat; + } + /* This loop handles SPR registers. */ + spr = ps->spr_busy; + spr_lat = ps->spr_latency; + for (i = 0; i < 4096; ++i) + { + if (*spr_lat) + { + *spr = *spr_lat; + *spr_lat = 0; + } + ++spr; ++spr_lat; + } +} + +/* Run the caches until all pending cache flushes are complete. */ +static void +wait_for_flush (SIM_CPU *cpu) +{ + SI address = CPU_LOAD_ADDRESS (cpu); + int wait = 0; + while (flush_pending_for_address (cpu, address)) + { + frv_model_advance_cycles (cpu, 1); + ++wait; + } + if (TRACE_INSN_P (cpu) && wait) + { + sprintf (hazard_name, "Data cache flush address %p:", address); + frv_model_trace_wait_cycles (cpu, wait, hazard_name); + } +} + +/* Initialize cycle counting for an insn. + FIRST_P is non-zero if this is the first insn in a set of parallel + insns. */ +void +frvbf_model_insn_before (SIM_CPU *cpu, int first_p) +{ + SIM_DESC sd = CPU_STATE (cpu); + FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu); + + ps->vliw_wait = 0; + ps->post_wait = 0; + memset (ps->fr_busy_adjust, 0, sizeof (ps->fr_busy_adjust)); + memset (ps->acc_busy_adjust, 0, sizeof (ps->acc_busy_adjust)); + + if (first_p) + { + ps->vliw_insns++; + ps->vliw_cycles = 0; + ps->vliw_branch_taken = 0; + ps->vliw_load_stall = 0; + } + + switch (STATE_ARCHITECTURE (sd)->mach) + { + case bfd_mach_fr400: + fr400_model_insn_before (cpu, first_p); + break; + case bfd_mach_fr500: + fr500_model_insn_before (cpu, first_p); + break; + case bfd_mach_fr550: + fr550_model_insn_before (cpu, first_p); + break; + default: + break; + } + + if (first_p) + wait_for_flush (cpu); +} + +/* Record the cycles computed for an insn. + LAST_P is non-zero if this is the last insn in a set of parallel insns, + and we update the total cycle count. + CYCLES is the cycle count of the insn. */ + +void +frvbf_model_insn_after (SIM_CPU *cpu, int last_p, int cycles) +{ + PROFILE_DATA *p = CPU_PROFILE_DATA (cpu); + FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu); + SIM_DESC sd = CPU_STATE (cpu); + + PROFILE_MODEL_CUR_INSN_CYCLES (p) = cycles; + + /* The number of cycles for a VLIW insn is the maximum number of cycles + used by any individual insn within it. */ + if (cycles > ps->vliw_cycles) + ps->vliw_cycles = cycles; + + if (last_p) + { + /* This is the last insn in a VLIW insn. */ + struct frv_interrupt_timer *timer = & frv_interrupt_state.timer; + + activate_cache_requests (cpu); /* before advancing cycles. */ + apply_latency_adjustments (cpu); /* must go first. */ + update_target_latencies (cpu); /* must go next. */ + frv_model_advance_cycles (cpu, ps->vliw_cycles); + + PROFILE_MODEL_LOAD_STALL_CYCLES (p) += ps->vliw_load_stall; + + /* Check the interrupt timer. cycles contains the total cycle count. */ + if (timer->enabled) + { + cycles = PROFILE_MODEL_TOTAL_CYCLES (p); + if (timer->current % timer->value + + (cycles - timer->current) >= timer->value) + frv_queue_external_interrupt (cpu, timer->interrupt); + timer->current = cycles; + } + + ps->past_first_p = 0; /* Next one will be the first in a new VLIW. */ + ps->branch_address = -1; + } + else + ps->past_first_p = 1; + + switch (STATE_ARCHITECTURE (sd)->mach) + { + case bfd_mach_fr400: + fr400_model_insn_after (cpu, last_p, cycles); + break; + case bfd_mach_fr500: + fr500_model_insn_after (cpu, last_p, cycles); + break; + case bfd_mach_fr550: + fr550_model_insn_after (cpu, last_p, cycles); + break; + default: + break; + } +} + +USI +frvbf_model_branch (SIM_CPU *current_cpu, PCADDR target, int hint) +{ + /* Record the hint and branch address for use in profiling. */ + FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (current_cpu); + ps->branch_hint = hint; + ps->branch_address = target; +} + +/* Top up the latency of the given GR by the given number of cycles. */ +void +update_GR_latency (SIM_CPU *cpu, INT out_GR, int cycles) +{ + if (out_GR >= 0) + { + FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu); + int *gr = ps->gr_latency; + if (gr[out_GR] < cycles) + gr[out_GR] = cycles; + } +} + +void +decrease_GR_busy (SIM_CPU *cpu, INT in_GR, int cycles) +{ + if (in_GR >= 0) + { + FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu); + int *gr = ps->gr_busy; + gr[in_GR] -= cycles; + } +} + +/* Top up the latency of the given double GR by the number of cycles. */ +void +update_GRdouble_latency (SIM_CPU *cpu, INT out_GR, int cycles) +{ + if (out_GR >= 0) + { + FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu); + int *gr = ps->gr_latency; + if (gr[out_GR] < cycles) + gr[out_GR] = cycles; + if (out_GR < 63 && gr[out_GR + 1] < cycles) + gr[out_GR + 1] = cycles; + } +} + +void +update_GR_latency_for_load (SIM_CPU *cpu, INT out_GR, int cycles) +{ + if (out_GR >= 0) + { + FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu); + int *gr = ps->gr_latency; + + /* The latency of the GR will be at least the number of cycles used + by the insn. */ + if (gr[out_GR] < cycles) + gr[out_GR] = cycles; + + /* The latency will also depend on how long it takes to retrieve the + data from the cache or memory. Assume that the load is issued + after the last cycle of the insn. */ + request_cache_load (cpu, out_GR, REGTYPE_NONE, cycles); + } +} + +void +update_GRdouble_latency_for_load (SIM_CPU *cpu, INT out_GR, int cycles) +{ + if (out_GR >= 0) + { + FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu); + int *gr = ps->gr_latency; + + /* The latency of the GR will be at least the number of cycles used + by the insn. */ + if (gr[out_GR] < cycles) + gr[out_GR] = cycles; + if (out_GR < 63 && gr[out_GR + 1] < cycles) + gr[out_GR + 1] = cycles; + + /* The latency will also depend on how long it takes to retrieve the + data from the cache or memory. Assume that the load is issued + after the last cycle of the insn. */ + request_cache_load (cpu, out_GR, REGTYPE_NONE, cycles); + } +} + +void +update_GR_latency_for_swap (SIM_CPU *cpu, INT out_GR, int cycles) +{ + update_GR_latency_for_load (cpu, out_GR, cycles); +} + +/* Top up the latency of the given FR by the given number of cycles. */ +void +update_FR_latency (SIM_CPU *cpu, INT out_FR, int cycles) +{ + if (out_FR >= 0) + { + FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu); + int *fr = ps->fr_latency; + if (fr[out_FR] < cycles) + fr[out_FR] = cycles; + } +} + +/* Top up the latency of the given double FR by the number of cycles. */ +void +update_FRdouble_latency (SIM_CPU *cpu, INT out_FR, int cycles) +{ + if (out_FR >= 0) + { + FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu); + int *fr = ps->fr_latency; + if (fr[out_FR] < cycles) + fr[out_FR] = cycles; + if (out_FR < 63 && fr[out_FR + 1] < cycles) + fr[out_FR + 1] = cycles; + } +} + +void +update_FR_latency_for_load (SIM_CPU *cpu, INT out_FR, int cycles) +{ + if (out_FR >= 0) + { + FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu); + int *fr = ps->fr_latency; + + /* The latency of the FR will be at least the number of cycles used + by the insn. */ + if (fr[out_FR] < cycles) + fr[out_FR] = cycles; + + /* The latency will also depend on how long it takes to retrieve the + data from the cache or memory. Assume that the load is issued + after the last cycle of the insn. */ + request_cache_load (cpu, out_FR, REGTYPE_FR, cycles); + } +} + +void +update_FRdouble_latency_for_load (SIM_CPU *cpu, INT out_FR, int cycles) +{ + if (out_FR >= 0) + { + FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu); + int *fr = ps->fr_latency; + + /* The latency of the FR will be at least the number of cycles used + by the insn. */ + if (fr[out_FR] < cycles) + fr[out_FR] = cycles; + if (out_FR < 63 && fr[out_FR + 1] < cycles) + fr[out_FR + 1] = cycles; + + /* The latency will also depend on how long it takes to retrieve the + data from the cache or memory. Assume that the load is issued + after the last cycle of the insn. */ + request_cache_load (cpu, out_FR, REGTYPE_FR, cycles); + } +} + +/* Top up the post-processing time of the given FR by the given number of + cycles. */ +void +update_FR_ptime (SIM_CPU *cpu, INT out_FR, int cycles) +{ + if (out_FR >= 0) + { + FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu); + /* If a load is pending on this register, then add the cycles to + the post processing time for this register. Otherwise apply it + directly to the latency of the register. */ + if (! load_pending_for_register (cpu, out_FR, 1, REGTYPE_FR)) + { + int *fr = ps->fr_latency; + fr[out_FR] += cycles; + } + else + ps->fr_ptime[out_FR] += cycles; + } +} + +void +update_FRdouble_ptime (SIM_CPU *cpu, INT out_FR, int cycles) +{ + if (out_FR >= 0) + { + FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu); + /* If a load is pending on this register, then add the cycles to + the post processing time for this register. Otherwise apply it + directly to the latency of the register. */ + if (! load_pending_for_register (cpu, out_FR, 2, REGTYPE_FR)) + { + int *fr = ps->fr_latency; + fr[out_FR] += cycles; + if (out_FR < 63) + fr[out_FR + 1] += cycles; + } + else + { + ps->fr_ptime[out_FR] += cycles; + if (out_FR < 63) + ps->fr_ptime[out_FR + 1] += cycles; + } + } +} + +/* Top up the post-processing time of the given ACC by the given number of + cycles. */ +void +update_ACC_ptime (SIM_CPU *cpu, INT out_ACC, int cycles) +{ + if (out_ACC >= 0) + { + FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu); + /* No load can be pending on this register. Apply the cycles + directly to the latency of the register. */ + int *acc = ps->acc_latency; + acc[out_ACC] += cycles; + } +} + +/* Top up the post-processing time of the given SPR by the given number of + cycles. */ +void +update_SPR_ptime (SIM_CPU *cpu, INT out_SPR, int cycles) +{ + if (out_SPR >= 0) + { + FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu); + /* No load can be pending on this register. Apply the cycles + directly to the latency of the register. */ + int *spr = ps->spr_latency; + spr[out_SPR] += cycles; + } +} + +void +decrease_ACC_busy (SIM_CPU *cpu, INT out_ACC, int cycles) +{ + if (out_ACC >= 0) + { + FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu); + int *acc = ps->acc_busy; + acc[out_ACC] -= cycles; + if (ps->acc_busy_adjust[out_ACC] >= 0 + && cycles > ps->acc_busy_adjust[out_ACC]) + ps->acc_busy_adjust[out_ACC] = cycles; + } +} + +void +increase_ACC_busy (SIM_CPU *cpu, INT out_ACC, int cycles) +{ + if (out_ACC >= 0) + { + FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu); + int *acc = ps->acc_busy; + acc[out_ACC] += cycles; + } +} + +void +enforce_full_acc_latency (SIM_CPU *cpu, INT in_ACC) +{ + FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu); + ps->acc_busy_adjust [in_ACC] = -1; +} + +void +decrease_FR_busy (SIM_CPU *cpu, INT out_FR, int cycles) +{ + if (out_FR >= 0) + { + FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu); + int *fr = ps->fr_busy; + fr[out_FR] -= cycles; + if (ps->fr_busy_adjust[out_FR] >= 0 + && cycles > ps->fr_busy_adjust[out_FR]) + ps->fr_busy_adjust[out_FR] = cycles; + } +} + +void +increase_FR_busy (SIM_CPU *cpu, INT out_FR, int cycles) +{ + if (out_FR >= 0) + { + FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu); + int *fr = ps->fr_busy; + fr[out_FR] += cycles; + } +} + +/* Top up the latency of the given ACC by the given number of cycles. */ +void +update_ACC_latency (SIM_CPU *cpu, INT out_ACC, int cycles) +{ + if (out_ACC >= 0) + { + FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu); + int *acc = ps->acc_latency; + if (acc[out_ACC] < cycles) + acc[out_ACC] = cycles; + } +} + +/* Top up the latency of the given CCR by the given number of cycles. */ +void +update_CCR_latency (SIM_CPU *cpu, INT out_CCR, int cycles) +{ + if (out_CCR >= 0) + { + FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu); + int *ccr = ps->ccr_latency; + if (ccr[out_CCR] < cycles) + ccr[out_CCR] = cycles; + } +} + +/* Top up the latency of the given SPR by the given number of cycles. */ +void +update_SPR_latency (SIM_CPU *cpu, INT out_SPR, int cycles) +{ + if (out_SPR >= 0) + { + FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu); + int *spr = ps->spr_latency; + if (spr[out_SPR] < cycles) + spr[out_SPR] = cycles; + } +} + +/* Top up the latency of the given integer division resource by the given + number of cycles. */ +void +update_idiv_resource_latency (SIM_CPU *cpu, INT in_resource, int cycles) +{ + /* operate directly on the busy cycles since each resource can only + be used once in a VLIW insn. */ + FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu); + int *r = ps->idiv_busy; + r[in_resource] = cycles; +} + +/* Set the latency of the given resource to the given number of cycles. */ +void +update_fdiv_resource_latency (SIM_CPU *cpu, INT in_resource, int cycles) +{ + /* operate directly on the busy cycles since each resource can only + be used once in a VLIW insn. */ + FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu); + int *r = ps->fdiv_busy; + r[in_resource] = cycles; +} + +/* Set the latency of the given resource to the given number of cycles. */ +void +update_fsqrt_resource_latency (SIM_CPU *cpu, INT in_resource, int cycles) +{ + /* operate directly on the busy cycles since each resource can only + be used once in a VLIW insn. */ + FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu); + int *r = ps->fsqrt_busy; + r[in_resource] = cycles; +} + +/* Set the latency of the given resource to the given number of cycles. */ +void +update_float_resource_latency (SIM_CPU *cpu, INT in_resource, int cycles) +{ + /* operate directly on the busy cycles since each resource can only + be used once in a VLIW insn. */ + FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu); + int *r = ps->float_busy; + r[in_resource] = cycles; +} + +void +update_media_resource_latency (SIM_CPU *cpu, INT in_resource, int cycles) +{ + /* operate directly on the busy cycles since each resource can only + be used once in a VLIW insn. */ + FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu); + int *r = ps->media_busy; + r[in_resource] = cycles; +} + +/* Set the branch penalty to the given number of cycles. */ +void +update_branch_penalty (SIM_CPU *cpu, int cycles) +{ + /* operate directly on the busy cycles since only one branch can occur + in a VLIW insn. */ + FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu); + ps->branch_penalty = cycles; +} + +/* Check the availability of the given GR register and update the number + of cycles the current VLIW insn must wait until it is available. */ +void +vliw_wait_for_GR (SIM_CPU *cpu, INT in_GR) +{ + FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu); + int *gr = ps->gr_busy; + /* If the latency of the register is greater than the current wait + then update the current wait. */ + if (in_GR >= 0 && gr[in_GR] > ps->vliw_wait) + { + if (TRACE_INSN_P (cpu)) + sprintf (hazard_name, "Data hazard for gr%d:", in_GR); + ps->vliw_wait = gr[in_GR]; + } +} + +/* Check the availability of the given GR register and update the number + of cycles the current VLIW insn must wait until it is available. */ +void +vliw_wait_for_GRdouble (SIM_CPU *cpu, INT in_GR) +{ + FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu); + int *gr = ps->gr_busy; + /* If the latency of the register is greater than the current wait + then update the current wait. */ + if (in_GR >= 0) + { + if (gr[in_GR] > ps->vliw_wait) + { + if (TRACE_INSN_P (cpu)) + sprintf (hazard_name, "Data hazard for gr%d:", in_GR); + ps->vliw_wait = gr[in_GR]; + } + if (in_GR < 63 && gr[in_GR + 1] > ps->vliw_wait) + { + if (TRACE_INSN_P (cpu)) + sprintf (hazard_name, "Data hazard for gr%d:", in_GR + 1); + ps->vliw_wait = gr[in_GR + 1]; + } + } +} + +/* Check the availability of the given FR register and update the number + of cycles the current VLIW insn must wait until it is available. */ +void +vliw_wait_for_FR (SIM_CPU *cpu, INT in_FR) +{ + FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu); + int *fr = ps->fr_busy; + /* If the latency of the register is greater than the current wait + then update the current wait. */ + if (in_FR >= 0 && fr[in_FR] > ps->vliw_wait) + { + if (TRACE_INSN_P (cpu)) + sprintf (hazard_name, "Data hazard for fr%d:", in_FR); + ps->vliw_wait = fr[in_FR]; + } +} + +/* Check the availability of the given GR register and update the number + of cycles the current VLIW insn must wait until it is available. */ +void +vliw_wait_for_FRdouble (SIM_CPU *cpu, INT in_FR) +{ + FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu); + int *fr = ps->fr_busy; + /* If the latency of the register is greater than the current wait + then update the current wait. */ + if (in_FR >= 0) + { + if (fr[in_FR] > ps->vliw_wait) + { + if (TRACE_INSN_P (cpu)) + sprintf (hazard_name, "Data hazard for fr%d:", in_FR); + ps->vliw_wait = fr[in_FR]; + } + if (in_FR < 63 && fr[in_FR + 1] > ps->vliw_wait) + { + if (TRACE_INSN_P (cpu)) + sprintf (hazard_name, "Data hazard for fr%d:", in_FR + 1); + ps->vliw_wait = fr[in_FR + 1]; + } + } +} + +/* Check the availability of the given CCR register and update the number + of cycles the current VLIW insn must wait until it is available. */ +void +vliw_wait_for_CCR (SIM_CPU *cpu, INT in_CCR) +{ + FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu); + int *ccr = ps->ccr_busy; + /* If the latency of the register is greater than the current wait + then update the current wait. */ + if (in_CCR >= 0 && ccr[in_CCR] > ps->vliw_wait) + { + if (TRACE_INSN_P (cpu)) + { + if (in_CCR > 3) + sprintf (hazard_name, "Data hazard for icc%d:", in_CCR-4); + else + sprintf (hazard_name, "Data hazard for fcc%d:", in_CCR); + } + ps->vliw_wait = ccr[in_CCR]; + } +} + +/* Check the availability of the given ACC register and update the number + of cycles the current VLIW insn must wait until it is available. */ +void +vliw_wait_for_ACC (SIM_CPU *cpu, INT in_ACC) +{ + FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu); + int *acc = ps->acc_busy; + /* If the latency of the register is greater than the current wait + then update the current wait. */ + if (in_ACC >= 0 && acc[in_ACC] > ps->vliw_wait) + { + if (TRACE_INSN_P (cpu)) + sprintf (hazard_name, "Data hazard for acc%d:", in_ACC); + ps->vliw_wait = acc[in_ACC]; + } +} + +/* Check the availability of the given SPR register and update the number + of cycles the current VLIW insn must wait until it is available. */ +void +vliw_wait_for_SPR (SIM_CPU *cpu, INT in_SPR) +{ + FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu); + int *spr = ps->spr_busy; + /* If the latency of the register is greater than the current wait + then update the current wait. */ + if (in_SPR >= 0 && spr[in_SPR] > ps->vliw_wait) + { + if (TRACE_INSN_P (cpu)) + sprintf (hazard_name, "Data hazard for spr %d:", in_SPR); + ps->vliw_wait = spr[in_SPR]; + } +} + +/* Check the availability of the given integer division resource and update + the number of cycles the current VLIW insn must wait until it is available. +*/ +void +vliw_wait_for_idiv_resource (SIM_CPU *cpu, INT in_resource) +{ + FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu); + int *r = ps->idiv_busy; + /* If the latency of the resource is greater than the current wait + then update the current wait. */ + if (r[in_resource] > ps->vliw_wait) + { + if (TRACE_INSN_P (cpu)) + { + sprintf (hazard_name, "Resource hazard for integer division in slot I%d:", in_resource); + } + ps->vliw_wait = r[in_resource]; + } +} + +/* Check the availability of the given float division resource and update + the number of cycles the current VLIW insn must wait until it is available. +*/ +void +vliw_wait_for_fdiv_resource (SIM_CPU *cpu, INT in_resource) +{ + FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu); + int *r = ps->fdiv_busy; + /* If the latency of the resource is greater than the current wait + then update the current wait. */ + if (r[in_resource] > ps->vliw_wait) + { + if (TRACE_INSN_P (cpu)) + { + sprintf (hazard_name, "Resource hazard for floating point division in slot F%d:", in_resource); + } + ps->vliw_wait = r[in_resource]; + } +} + +/* Check the availability of the given float square root resource and update + the number of cycles the current VLIW insn must wait until it is available. +*/ +void +vliw_wait_for_fsqrt_resource (SIM_CPU *cpu, INT in_resource) +{ + FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu); + int *r = ps->fsqrt_busy; + /* If the latency of the resource is greater than the current wait + then update the current wait. */ + if (r[in_resource] > ps->vliw_wait) + { + if (TRACE_INSN_P (cpu)) + { + sprintf (hazard_name, "Resource hazard for square root in slot F%d:", in_resource); + } + ps->vliw_wait = r[in_resource]; + } +} + +/* Check the availability of the given float unit resource and update + the number of cycles the current VLIW insn must wait until it is available. +*/ +void +vliw_wait_for_float_resource (SIM_CPU *cpu, INT in_resource) +{ + FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu); + int *r = ps->float_busy; + /* If the latency of the resource is greater than the current wait + then update the current wait. */ + if (r[in_resource] > ps->vliw_wait) + { + if (TRACE_INSN_P (cpu)) + { + sprintf (hazard_name, "Resource hazard for floating point unit in slot F%d:", in_resource); + } + ps->vliw_wait = r[in_resource]; + } +} + +/* Check the availability of the given media unit resource and update + the number of cycles the current VLIW insn must wait until it is available. +*/ +void +vliw_wait_for_media_resource (SIM_CPU *cpu, INT in_resource) +{ + FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu); + int *r = ps->media_busy; + /* If the latency of the resource is greater than the current wait + then update the current wait. */ + if (r[in_resource] > ps->vliw_wait) + { + if (TRACE_INSN_P (cpu)) + { + sprintf (hazard_name, "Resource hazard for media unit in slot M%d:", in_resource); + } + ps->vliw_wait = r[in_resource]; + } +} + +/* Run the caches until all requests for the given register(s) are satisfied. */ +void +load_wait_for_GR (SIM_CPU *cpu, INT in_GR) +{ + if (in_GR >= 0) + { + int wait = 0; + while (load_pending_for_register (cpu, in_GR, 1/*words*/, REGTYPE_NONE)) + { + frv_model_advance_cycles (cpu, 1); + ++wait; + } + if (wait) + { + FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu); + ps->vliw_wait += wait; + ps->vliw_load_stall += wait; + if (TRACE_INSN_P (cpu)) + sprintf (hazard_name, "Data hazard for gr%d:", in_GR); + } + } +} + +void +load_wait_for_FR (SIM_CPU *cpu, INT in_FR) +{ + if (in_FR >= 0) + { + FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu); + int *fr; + int wait = 0; + while (load_pending_for_register (cpu, in_FR, 1/*words*/, REGTYPE_FR)) + { + frv_model_advance_cycles (cpu, 1); + ++wait; + } + /* Post processing time may have been added to the register's + latency after the loads were processed. Account for that too. + */ + fr = ps->fr_busy; + if (fr[in_FR]) + { + wait += fr[in_FR]; + frv_model_advance_cycles (cpu, fr[in_FR]); + } + /* Update the vliw_wait with the number of cycles we waited for the + load and any post-processing. */ + if (wait) + { + ps->vliw_wait += wait; + ps->vliw_load_stall += wait; + if (TRACE_INSN_P (cpu)) + sprintf (hazard_name, "Data hazard for fr%d:", in_FR); + } + } +} + +void +load_wait_for_GRdouble (SIM_CPU *cpu, INT in_GR) +{ + if (in_GR >= 0) + { + int wait = 0; + while (load_pending_for_register (cpu, in_GR, 2/*words*/, REGTYPE_NONE)) + { + frv_model_advance_cycles (cpu, 1); + ++wait; + } + if (wait) + { + FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu); + ps->vliw_wait += wait; + ps->vliw_load_stall += wait; + if (TRACE_INSN_P (cpu)) + sprintf (hazard_name, "Data hazard for gr%d:", in_GR); + } + } +} + +void +load_wait_for_FRdouble (SIM_CPU *cpu, INT in_FR) +{ + if (in_FR >= 0) + { + FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu); + int *fr; + int wait = 0; + while (load_pending_for_register (cpu, in_FR, 2/*words*/, REGTYPE_FR)) + { + frv_model_advance_cycles (cpu, 1); + ++wait; + } + /* Post processing time may have been added to the registers' + latencies after the loads were processed. Account for that too. + */ + fr = ps->fr_busy; + if (fr[in_FR]) + { + wait += fr[in_FR]; + frv_model_advance_cycles (cpu, fr[in_FR]); + } + if (in_FR < 63) + { + if (fr[in_FR + 1]) + { + wait += fr[in_FR + 1]; + frv_model_advance_cycles (cpu, fr[in_FR + 1]); + } + } + /* Update the vliw_wait with the number of cycles we waited for the + load and any post-processing. */ + if (wait) + { + ps->vliw_wait += wait; + ps->vliw_load_stall += wait; + if (TRACE_INSN_P (cpu)) + sprintf (hazard_name, "Data hazard for fr%d:", in_FR); + } + } +} + +void +enforce_full_fr_latency (SIM_CPU *cpu, INT in_FR) +{ + FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu); + ps->fr_busy_adjust [in_FR] = -1; +} + +/* Calculate how long the post processing for a floating point insn must + wait for resources to become available. */ +int +post_wait_for_FR (SIM_CPU *cpu, INT in_FR) +{ + FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu); + int *fr = ps->fr_busy; + + if (in_FR >= 0 && fr[in_FR] > ps->post_wait) + { + ps->post_wait = fr[in_FR]; + if (TRACE_INSN_P (cpu)) + sprintf (hazard_name, "Data hazard for fr%d:", in_FR); + } +} + +/* Calculate how long the post processing for a floating point insn must + wait for resources to become available. */ +int +post_wait_for_FRdouble (SIM_CPU *cpu, INT in_FR) +{ + FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu); + int *fr = ps->fr_busy; + + if (in_FR >= 0) + { + if (fr[in_FR] > ps->post_wait) + { + ps->post_wait = fr[in_FR]; + if (TRACE_INSN_P (cpu)) + sprintf (hazard_name, "Data hazard for fr%d:", in_FR); + } + if (in_FR < 63 && fr[in_FR + 1] > ps->post_wait) + { + ps->post_wait = fr[in_FR + 1]; + if (TRACE_INSN_P (cpu)) + sprintf (hazard_name, "Data hazard for fr%d:", in_FR + 1); + } + } +} + +int +post_wait_for_ACC (SIM_CPU *cpu, INT in_ACC) +{ + FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu); + int *acc = ps->acc_busy; + + if (in_ACC >= 0 && acc[in_ACC] > ps->post_wait) + { + ps->post_wait = acc[in_ACC]; + if (TRACE_INSN_P (cpu)) + sprintf (hazard_name, "Data hazard for acc%d:", in_ACC); + } +} + +int +post_wait_for_CCR (SIM_CPU *cpu, INT in_CCR) +{ + FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu); + int *ccr = ps->ccr_busy; + + if (in_CCR >= 0 && ccr[in_CCR] > ps->post_wait) + { + ps->post_wait = ccr[in_CCR]; + if (TRACE_INSN_P (cpu)) + { + if (in_CCR > 3) + sprintf (hazard_name, "Data hazard for icc%d:", in_CCR - 4); + else + sprintf (hazard_name, "Data hazard for fcc%d:", in_CCR); + } + } +} + +int +post_wait_for_SPR (SIM_CPU *cpu, INT in_SPR) +{ + FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu); + int *spr = ps->spr_busy; + + if (in_SPR >= 0 && spr[in_SPR] > ps->post_wait) + { + ps->post_wait = spr[in_SPR]; + if (TRACE_INSN_P (cpu)) + sprintf (hazard_name, "Data hazard for spr[%d]:", in_SPR); + } +} + +int +post_wait_for_fdiv (SIM_CPU *cpu, INT slot) +{ + FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu); + int *fdiv = ps->fdiv_busy; + + /* Multiple floating point divisions in the same slot need only wait 1 + extra cycle. */ + if (fdiv[slot] > 0 && 1 > ps->post_wait) + { + ps->post_wait = 1; + if (TRACE_INSN_P (cpu)) + { + sprintf (hazard_name, "Resource hazard for floating point division in slot F%d:", slot); + } + } +} + +int +post_wait_for_fsqrt (SIM_CPU *cpu, INT slot) +{ + FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu); + int *fsqrt = ps->fsqrt_busy; + + /* Multiple floating point square roots in the same slot need only wait 1 + extra cycle. */ + if (fsqrt[slot] > 0 && 1 > ps->post_wait) + { + ps->post_wait = 1; + if (TRACE_INSN_P (cpu)) + { + sprintf (hazard_name, "Resource hazard for square root in slot F%d:", slot); + } + } +} + +int +post_wait_for_float (SIM_CPU *cpu, INT slot) +{ + FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu); + int *flt = ps->float_busy; + + /* Multiple floating point square roots in the same slot need only wait 1 + extra cycle. */ + if (flt[slot] > ps->post_wait) + { + ps->post_wait = flt[slot]; + if (TRACE_INSN_P (cpu)) + { + sprintf (hazard_name, "Resource hazard for floating point unit in slot F%d:", slot); + } + } +} + +int +post_wait_for_media (SIM_CPU *cpu, INT slot) +{ + FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu); + int *media = ps->media_busy; + + /* Multiple floating point square roots in the same slot need only wait 1 + extra cycle. */ + if (media[slot] > ps->post_wait) + { + ps->post_wait = media[slot]; + if (TRACE_INSN_P (cpu)) + { + sprintf (hazard_name, "Resource hazard for media unit in slot M%d:", slot); + } + } +} + +/* Print cpu-specific profile information. */ +#define COMMAS(n) sim_add_commas (comma_buf, sizeof (comma_buf), (n)) + +static void +print_cache (SIM_CPU *cpu, FRV_CACHE *cache, const char *cache_name) +{ + SIM_DESC sd = CPU_STATE (cpu); + + if (cache != NULL) + { + char comma_buf[20]; + unsigned accesses; + + sim_io_printf (sd, " %s Cache\n\n", cache_name); + accesses = cache->statistics.accesses; + sim_io_printf (sd, " Total accesses: %s\n", COMMAS (accesses)); + if (accesses != 0) + { + float rate; + unsigned hits = cache->statistics.hits; + sim_io_printf (sd, " Hits: %s\n", COMMAS (hits)); + rate = (float)hits / accesses; + sim_io_printf (sd, " Hit rate: %.2f%%\n", rate * 100); + } + } + else + sim_io_printf (sd, " Model %s has no %s cache\n", + MODEL_NAME (CPU_MODEL (cpu)), cache_name); + + sim_io_printf (sd, "\n"); +} + +/* This table must correspond to the UNIT_ATTR table in + opcodes/frv-desc.h. Only the units up to UNIT_C need be + listed since the others cannot occur after mapping. */ +static char * +slot_names[] = +{ + "none", + "I0", "I1", "I01", "I2", "I3", "IALL", + "FM0", "FM1", "FM01", "FM2", "FM3", "FMALL", "FMLOW", + "B0", "B1", "B01", + "C" +}; + +static void +print_parallel (SIM_CPU *cpu, int verbose) +{ + SIM_DESC sd = CPU_STATE (cpu); + PROFILE_DATA *p = CPU_PROFILE_DATA (cpu); + FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu); + unsigned total, vliw; + char comma_buf[20]; + float average; + + sim_io_printf (sd, "Model %s Parallelization\n\n", + MODEL_NAME (CPU_MODEL (cpu))); + + total = PROFILE_TOTAL_INSN_COUNT (p); + sim_io_printf (sd, " Total instructions: %s\n", COMMAS (total)); + vliw = ps->vliw_insns; + sim_io_printf (sd, " VLIW instructions: %s\n", COMMAS (vliw)); + average = (float)total / vliw; + sim_io_printf (sd, " Average VLIW length: %.2f\n", average); + average = (float)PROFILE_MODEL_TOTAL_CYCLES (p) / vliw; + sim_io_printf (sd, " Cycles per VLIW instruction: %.2f\n", average); + average = (float)total / PROFILE_MODEL_TOTAL_CYCLES (p); + sim_io_printf (sd, " Instructions per cycle: %.2f\n", average); + + if (verbose) + { + int i; + int max_val = 0; + int max_name_len = 0; + for (i = UNIT_NIL + 1; i < UNIT_NUM_UNITS; ++i) + { + if (INSNS_IN_SLOT (i)) + { + int len; + if (INSNS_IN_SLOT (i) > max_val) + max_val = INSNS_IN_SLOT (i); + len = strlen (slot_names[i]); + if (len > max_name_len) + max_name_len = len; + } + } + if (max_val > 0) + { + sim_io_printf (sd, "\n"); + sim_io_printf (sd, " Instructions per slot:\n"); + sim_io_printf (sd, "\n"); + for (i = UNIT_NIL + 1; i < UNIT_NUM_UNITS; ++i) + { + if (INSNS_IN_SLOT (i) != 0) + { + sim_io_printf (sd, " %*s: %*s: ", + max_name_len, slot_names[i], + max_val < 10000 ? 5 : 10, + COMMAS (INSNS_IN_SLOT (i))); + sim_profile_print_bar (sd, PROFILE_HISTOGRAM_WIDTH, + INSNS_IN_SLOT (i), + max_val); + sim_io_printf (sd, "\n"); + } + } + } /* details to print */ + } /* verbose */ + + sim_io_printf (sd, "\n"); +} + +void +frv_profile_info (SIM_CPU *cpu, int verbose) +{ + /* FIXME: Need to add smp support. */ + PROFILE_DATA *p = CPU_PROFILE_DATA (cpu); + +#if WITH_PROFILE_PARALLEL_P + if (PROFILE_FLAGS (p) [PROFILE_PARALLEL_IDX]) + print_parallel (cpu, verbose); +#endif + +#if WITH_PROFILE_CACHE_P + if (PROFILE_FLAGS (p) [PROFILE_CACHE_IDX]) + { + SIM_DESC sd = CPU_STATE (cpu); + sim_io_printf (sd, "Model %s Cache Statistics\n\n", + MODEL_NAME (CPU_MODEL (cpu))); + print_cache (cpu, CPU_INSN_CACHE (cpu), "Instruction"); + print_cache (cpu, CPU_DATA_CACHE (cpu), "Data"); + } +#endif /* WITH_PROFILE_CACHE_P */ +} + +/* A hack to get registers referenced for profiling. */ +SI frv_ref_SI (SI ref) {return ref;} +#endif /* WITH_PROFILE_MODEL_P */ diff --git a/sim/frv/profile.h b/sim/frv/profile.h new file mode 100644 index 0000000..4c6e558 --- /dev/null +++ b/sim/frv/profile.h @@ -0,0 +1,229 @@ +/* Profiling definitions for the FRV simulator + Copyright (C) 1998, 1999, 2000, 2001, 2003 Free Software Foundation, Inc. + Contributed by Red Hat. + +This file is part of the GNU Simulators. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef PROFILE_H +#define PROFILE_H + +#include "frv-desc.h" + +/* This struct defines the state of profiling. All fields are of general + use to all machines. */ +typedef struct +{ + long vliw_insns; /* total number of VLIW insns. */ + long vliw_wait; /* number of cycles that the current VLIW insn must wait. */ + long post_wait; /* number of cycles that post processing in the current + VLIW insn must wait. */ + long vliw_cycles;/* number of cycles used by current VLIW insn. */ + + int past_first_p; /* Not the first insns in the VLIW */ + + /* Register latencies. Must be signed since they can be temporarily + negative. */ + int gr_busy[64]; /* Cycles until GR is available. */ + int fr_busy[64]; /* Cycles until FR is available. */ + int acc_busy[64]; /* Cycles until FR is available. */ + int ccr_busy[8]; /* Cycles until ICC/FCC is available. */ + int spr_busy[4096]; /* Cycles until spr is available. */ + int idiv_busy[2]; /* Cycles until integer division unit is available. */ + int fdiv_busy[2]; /* Cycles until float division unit is available. */ + int fsqrt_busy[2]; /* Cycles until square root unit is available. */ + int float_busy[4]; /* Cycles until floating point unit is available. */ + int media_busy[4]; /* Cycles until media unit is available. */ + int branch_penalty; /* Cycles until branch is complete. */ + + int gr_latency[64]; /* Cycles until target GR is available. */ + int fr_latency[64]; /* Cycles until target FR is available. */ + int acc_latency[64]; /* Cycles until target FR is available. */ + int ccr_latency[8]; /* Cycles until target ICC/FCC is available. */ + int spr_latency[4096]; /* Cycles until target spr is available. */ + + /* Some registers are busy for a shorter number of cycles than normal + depending on how they are used next. the xxx_busy_adjust arrays keep track + of how many cycles to adjust down. + */ + int fr_busy_adjust[64]; + int acc_busy_adjust[64]; + + /* Register flags. Each bit represents one register. */ + DI cur_gr_complex; + DI prev_gr_complex; + + /* Keep track of the total queued post-processing time required before a + resource is available. This is applied to the resource's latency once all + pending loads for the resource are completed. */ + int fr_ptime[64]; + + int branch_hint; /* hint field from branch insn. */ + USI branch_address; /* Address of predicted branch. */ + USI insn_fetch_address;/* Address of sequential insns fetched. */ + int mclracc_acc; /* ACC number of register cleared by mclracc. */ + int mclracc_A; /* A field of mclracc. */ + + /* We need to know when the first branch of a vliw insn is taken, so that + we don't consider the remaining branches in the vliw insn. */ + int vliw_branch_taken; + + /* Keep track of the maximum load stall for each VLIW insn. */ + int vliw_load_stall; + + /* Need to know if all cache entries are affected by various cache + operations. */ + int all_cache_entries; +} FRV_PROFILE_STATE; + +#define DUAL_REG(reg) ((reg) >= 0 && (reg) < 63 ? (reg) + 1 : -1) +#define DUAL_DOUBLE(reg) ((reg) >= 0 && (reg) < 61 ? (reg) + 2 : -1) + +/* Return the GNER register associated with the given GR register. + There is no GNER associated with gr0. */ +#define GNER_FOR_GR(gr) ((gr) > 63 ? -1 : \ + (gr) > 31 ? H_SPR_GNER0 : \ + (gr) > 0 ? H_SPR_GNER1 : \ + -1) +/* Return the GNER register associated with the given GR register. + There is no GNER associated with gr0. */ +#define FNER_FOR_FR(fr) ((fr) > 63 ? -1 : \ + (fr) > 31 ? H_SPR_FNER0 : \ + (fr) > 0 ? H_SPR_FNER1 : \ + -1) + +/* Top up the latency of the given GR by the given number of cycles. */ +void update_GR_latency (SIM_CPU *, INT, int); +void update_GRdouble_latency (SIM_CPU *, INT, int); +void update_GR_latency_for_load (SIM_CPU *, INT, int); +void update_GRdouble_latency_for_load (SIM_CPU *, INT, int); +void update_GR_latency_for_swap (SIM_CPU *, INT, int); +void update_FR_latency (SIM_CPU *, INT, int); +void update_FRdouble_latency (SIM_CPU *, INT, int); +void update_FR_latency_for_load (SIM_CPU *, INT, int); +void update_FRdouble_latency_for_load (SIM_CPU *, INT, int); +void update_FR_ptime (SIM_CPU *, INT, int); +void update_FRdouble_ptime (SIM_CPU *, INT, int); +void decrease_ACC_busy (SIM_CPU *, INT, int); +void decrease_FR_busy (SIM_CPU *, INT, int); +void decrease_GR_busy (SIM_CPU *, INT, int); +void increase_FR_busy (SIM_CPU *, INT, int); +void increase_ACC_busy (SIM_CPU *, INT, int); +void update_ACC_latency (SIM_CPU *, INT, int); +void update_CCR_latency (SIM_CPU *, INT, int); +void update_SPR_latency (SIM_CPU *, INT, int); +void update_idiv_resource_latency (SIM_CPU *, INT, int); +void update_fdiv_resource_latency (SIM_CPU *, INT, int); +void update_fsqrt_resource_latency (SIM_CPU *, INT, int); +void update_float_resource_latency (SIM_CPU *, INT, int); +void update_media_resource_latency (SIM_CPU *, INT, int); +void update_branch_penalty (SIM_CPU *, int); +void update_ACC_ptime (SIM_CPU *, INT, int); +void update_SPR_ptime (SIM_CPU *, INT, int); +void vliw_wait_for_GR (SIM_CPU *, INT); +void vliw_wait_for_GRdouble (SIM_CPU *, INT); +void vliw_wait_for_FR (SIM_CPU *, INT); +void vliw_wait_for_FRdouble (SIM_CPU *, INT); +void vliw_wait_for_CCR (SIM_CPU *, INT); +void vliw_wait_for_ACC (SIM_CPU *, INT); +void vliw_wait_for_SPR (SIM_CPU *, INT); +void vliw_wait_for_idiv_resource (SIM_CPU *, INT); +void vliw_wait_for_fdiv_resource (SIM_CPU *, INT); +void vliw_wait_for_fsqrt_resource (SIM_CPU *, INT); +void vliw_wait_for_float_resource (SIM_CPU *, INT); +void vliw_wait_for_media_resource (SIM_CPU *, INT); +void load_wait_for_GR (SIM_CPU *, INT); +void load_wait_for_FR (SIM_CPU *, INT); +void load_wait_for_GRdouble (SIM_CPU *, INT); +void load_wait_for_FRdouble (SIM_CPU *, INT); +void enforce_full_fr_latency (SIM_CPU *, INT); +void enforce_full_acc_latency (SIM_CPU *, INT); +int post_wait_for_FR (SIM_CPU *, INT); +int post_wait_for_FRdouble (SIM_CPU *, INT); +int post_wait_for_ACC (SIM_CPU *, INT); +int post_wait_for_CCR (SIM_CPU *, INT); +int post_wait_for_SPR (SIM_CPU *, INT); +int post_wait_for_fdiv (SIM_CPU *, INT); +int post_wait_for_fsqrt (SIM_CPU *, INT); +int post_wait_for_float (SIM_CPU *, INT); +int post_wait_for_media (SIM_CPU *, INT); + +void trace_vliw_wait_cycles (SIM_CPU *); +void handle_resource_wait (SIM_CPU *); + +void request_cache_load (SIM_CPU *, INT, int, int); +void request_cache_flush (SIM_CPU *, FRV_CACHE *, int); +void request_cache_invalidate (SIM_CPU *, FRV_CACHE *, int); +void request_cache_preload (SIM_CPU *, FRV_CACHE *, int); +void request_cache_unlock (SIM_CPU *, FRV_CACHE *, int); +int load_pending_for_register (SIM_CPU *, int, int, int); + +void set_use_is_gr_complex (SIM_CPU *, INT); +void set_use_not_gr_complex (SIM_CPU *, INT); +int use_is_gr_complex (SIM_CPU *, INT); + +typedef struct +{ + SI address; + unsigned reqno; +} FRV_INSN_FETCH_BUFFER; + +extern FRV_INSN_FETCH_BUFFER frv_insn_fetch_buffer[]; + +PROFILE_INFO_CPU_CALLBACK_FN frv_profile_info; + +enum { + /* Simulator specific profile bits begin here. */ + /* Profile caches. */ + PROFILE_CACHE_IDX = PROFILE_NEXT_IDX, + /* Profile parallelization. */ + PROFILE_PARALLEL_IDX +}; + +/* Masks so WITH_PROFILE can have symbolic values. + The case choice here is on purpose. The lowercase parts are args to + --with-profile. */ +#define PROFILE_cache (1 << PROFILE_INSN_IDX) +#define PROFILE_parallel (1 << PROFILE_INSN_IDX) + +/* Preprocessor macros to simplify tests of WITH_PROFILE. */ +#define WITH_PROFILE_CACHE_P (WITH_PROFILE & PROFILE_insn) +#define WITH_PROFILE_PARALLEL_P (WITH_PROFILE & PROFILE_insn) + +#define FRV_COUNT_CYCLES(cpu, condition) \ + ((PROFILE_MODEL_P (cpu) && (condition)) || frv_interrupt_state.timer.enabled) + +/* Modelling support. */ +extern int frv_save_profile_model_p; + +extern enum FRV_INSN_MODELING { + FRV_INSN_NO_MODELING = 0, + FRV_INSN_MODEL_PASS_1, + FRV_INSN_MODEL_PASS_2, + FRV_INSN_MODEL_WRITEBACK +} model_insn; + +void +frv_model_advance_cycles (SIM_CPU *, int); +void +frv_model_trace_wait_cycles (SIM_CPU *, int, const char *); + +/* Register types for queued load requests. */ +#define REGTYPE_NONE 0 +#define REGTYPE_FR 1 +#define REGTYPE_ACC 2 + +#endif /* PROFILE_H */ diff --git a/sim/frv/registers.c b/sim/frv/registers.c new file mode 100644 index 0000000..685e53f --- /dev/null +++ b/sim/frv/registers.c @@ -0,0 +1,5581 @@ +/* frv simulator support code + Copyright (C) 2000, 2001, 2003 Free Software Foundation, Inc. + Contributed by Red Hat. + +This file is part of the GNU simulators. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#define WANT_CPU +#define WANT_CPU_FRVBF + +#include "sim-main.h" +#include "bfd.h" + +#define IMPL 1 /* Implemented */ +#define SUP 1 /* Supervisor register */ +#define USER 0 /* User register */ + +#define RESERVED {0x00000000, 0x00000000, 0x00000000, 0xffffffff, ! IMPL, USER} + +/* SPR definitions for the general FRV architecture. + All registers and all features should be enabled. + Initial and reset values are taken from the fr500 LSI. */ +static FRV_SPR_CONTROL_INFO frv_spr[] = +{ + {0x0000107e, 0x0000007c, 0x000060fd, 0xffff9600, IMPL, SUP}, /* PSR */ + {0x00000000, 0x00000000, 0x00000000, 0x00000003, IMPL, SUP}, /* PCSR */ + {0x00000000, 0x00000000, 0xffffffff, 0x00000003, IMPL, SUP}, /* BPCSR */ + {0x00000000, 0x00000000, 0x00000000, 0x000007ff, IMPL, SUP}, /* TBR */ + {0x00000000, 0x00000000, 0x00000000, 0xffffeffe, IMPL, SUP}, /* BPSR */ + + /* spr registers 5-15 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, + + {0x000003c0, 0x00000000, 0xce400000, 0x313fec38, IMPL, SUP}, /* HSR0 */ + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, /* HSR7 */ + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, /* HSR15 */ + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, /* HSR23 */ + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, /* HSR31 */ + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, /* HSR39 */ + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, /* HSR47 */ + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, /* HSR55 */ + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, /* HSR63 */ + + /* spr registers 80-255 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0x00000000, IMPL, USER}, /* CCR */ + + /* spr registers 257-262 are reserved */ + RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0xffff0000, IMPL, USER}, /* CCCR */ + + /* spr registers 264-271 are reserved */ + RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0x00000003, IMPL, USER}, /* LR */ + {0x00000000, 0x00000000, 0x00000000, 0x00000000, IMPL, USER}, /* LCR */ + + /* spr registers 274-279 and 282-287 are reserved. */ + /* spr registers 280 and 281 are iacc0h and iacc0l (fr405). */ + RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + {0x00000000, 0x00000000, 0x00000000, 0x00000000, IMPL, USER}, /* IACC0H */ + {0x00000000, 0x00000000, 0x00000000, 0x00000000, IMPL, USER}, /* IACC0L */ + RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, + + {0xe0000021, 0x20000000, 0xe0000000, 0xffffffc2, IMPL, USER}, /* ISR */ + + /* spr registers 289-351 are reserved */ + RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, USER}, /* NEEAR0 */ + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, USER}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, USER}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, USER}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, USER}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, USER}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, USER}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, USER}, /* NEEAR7 */ + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, USER}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, USER}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, USER}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, USER}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, USER}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, USER}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, USER}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, USER}, /* NEEAR15 */ + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, USER}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, USER}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, USER}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, USER}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, USER}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, USER}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, USER}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, USER}, /* NEEAR23 */ + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, USER}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, USER}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, USER}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, USER}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, USER}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, USER}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, USER}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, USER}, /* NEEAR31 */ + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, USER}, /* NESR0 */ + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, USER}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, USER}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, USER}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, USER}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, USER}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, USER}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, USER}, /* NESR7 */ + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, USER}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, USER}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, USER}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, USER}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, USER}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, USER}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, USER}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, USER}, /* NESR15 */ + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, USER}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, USER}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, USER}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, USER}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, USER}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, USER}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, USER}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, USER}, /* NESR23 */ + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, USER}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, USER}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, USER}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, USER}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, USER}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, USER}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, USER}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, USER}, /* NESR31 */ + + {0x0000007f, 0x0000007f, 0x00000000, 0xffffffff, IMPL, USER}, /* NECR */ + + /* spr registers 417-431 are reserved */ + RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0x00000000, IMPL, USER}, /* GNER0 */ + {0x00000000, 0x00000000, 0x00000000, 0x00000000, IMPL, USER}, /* GNER1 */ + {0x00000000, 0x00000000, 0x00000000, 0x00000000, IMPL, USER}, /* FNER0 */ + {0x00000000, 0x00000000, 0x00000000, 0x00000000, IMPL, USER}, /* FNER1 */ + + /* spr registers 436-511 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* EPCR0 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* EPCR7 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* EPCR15 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* EPCR23 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* EPCR31 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* EPCR39 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* EPCR47 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* EPCR55 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* EPCR63 */ + + {0x00000100, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* ESR0 */ + {0x00000026, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* ESR7 */ + {0x00000200, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000200, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000200, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000200, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000200, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000200, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* ESR15 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* ESR23 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* ESR31 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* ESR39 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* ESR47 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* ESR55 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* ESR63 */ + + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, /* EIR0 */ + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, /* EIR7 */ + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, /* EIR15 */ + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, /* EIR23 */ + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, /* EIR31 */ + + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* ESFR0 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* ESFR1 */ + + /* spr registers 674-767 are reserved */ + RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0x00000000, IMPL, SUP}, /* SR0 */ + {0x00000000, 0x00000000, 0x00000000, 0x00000000, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x00000000, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x00000000, IMPL, SUP}, /* SR3 */ + + /* spr registers 772-1023 are reserved */ + RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, + + {0x00800000, 0x00000000, 0x00000000, 0xc0f103ff, IMPL, USER}, /* FSR0 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, /* FSR7 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, /* FSR15 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, /* FSR23 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, /* FSR31 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, /* FSR39 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, /* FSR47 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, /* FSR55 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, /* FSR63 */ + + /* Each FQ register is a pair of 32 bit registers. */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* FQ0 */ + {0x00000000, 0x00000000, 0x00000000, 0xfffffffe, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xfffffffe, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xfffffffe, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xfffffffe, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xfffffffe, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xfffffffe, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xfffffffe, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* FQ7 */ + {0x00000000, 0x00000000, 0x00000000, 0xfffffffe, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xfffffffe, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xfffffffe, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xfffffffe, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xfffffffe, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xfffffffe, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xfffffffe, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xfffffffe, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* FQ15 */ + {0x00000000, 0x00000000, 0x00000000, 0xfffffffe, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xfffffffe, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xfffffffe, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xfffffffe, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xfffffffe, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xfffffffe, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xfffffffe, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xfffffffe, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* FQ23 */ + {0x00000000, 0x00000000, 0x00000000, 0xfffffffe, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xfffffffe, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xfffffffe, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xfffffffe, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xfffffffe, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xfffffffe, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xfffffffe, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xfffffffe, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* FQ31 */ + {0x00000000, 0x00000000, 0x00000000, 0xfffffffe, IMPL, SUP}, + + /* spr registers 1152-1271 are reserved */ + RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, /* MCILR0 */ + {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, /* MCILR1 */ + + /* spr registers 1274-1279 are reserved */ + RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x01e00000, 0x3fff8fc0, IMPL, USER}, /* MSR0 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffc1, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, /* MSR7 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, /* MSR15 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, /* MSR23 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, /* MSR31 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, /* MSR39 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, /* MSR47 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, /* MSR55 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, /* MSR63 */ + + /* Each MQ register is a pair of 32 bit registers. */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* MQ0 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* MQ7 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* MQ15 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* MQ23 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* MQ31 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + + /* Accumulators are read-only by the user except for special + insns and side effect of other insns. */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, /* ACC0 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, /* ACC7 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, /* ACC15 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, /* ACC23 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, /* ACC31 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, /* ACC39 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, /* ACC47 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, /* ACC55 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, /* ACC63 */ + + /* Accumulator guards are read-only by the user except for special + insns and side effect of other insns. */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, /* ACCG0 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, /* ACCG7 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, /* ACCG15 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, /* ACCG23 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, /* ACCG31 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, /* ACCG39 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, /* ACCG47 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, /* ACCG55 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, /* ACCG63 */ + + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* EAR0 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* EAR7 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* EAR15 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* EAR23 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* EAR31 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* EAR39 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* EAR47 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* EAR55 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* EAR63 */ + + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* EDR0 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* EDR7 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* EDR15 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* EDR23 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* EDR31 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* EDR39 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* EDR47 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* EDR55 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* EDR63 */ + + {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP}, /* IAMLR0 */ + {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP}, /* IAMLR7 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* IAMLR15 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* IAMLR23 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* IAMLR31 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* IAMLR39 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* IAMLR47 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* IAMLR55 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* IAMLR63 */ + + {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP}, /* IAMPR0 */ + {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP}, /* IAMPR7 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* IAMPR15 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* IAMPR23 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* IAMPR31 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* IAMPR39 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* IAMPR47 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* IAMPR55 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* IAMPR63 */ + + {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP}, /* DAMLR0 */ + {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP}, /* DAMLR7 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DAMLR15 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DAMLR23 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DAMLR31 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DAMLR39 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DAMLR47 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DAMLR55 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DAMLR63 */ + + {0x00000000, 0x00000000, 0x00000001, 0x000fff00, IMPL, SUP}, /* DAMPR0 */ + {0x00000000, 0x00000000, 0x00000001, 0x000fff00, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000001, 0x000fff00, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000001, 0x000fff00, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000001, 0x000fff00, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000001, 0x000fff00, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000001, 0x000fff00, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000001, 0x000fff00, IMPL, SUP}, /* DAMPR7 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DAMPR15 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DAMPR23 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DAMPR31 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DAMPR39 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DAMPR47 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DAMPR55 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DAMPR63 */ + + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* AMCR */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* STBAR */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* MMCR */ + + /* spr registers 1923-2047 are reserved */ + RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DCR */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* BRR */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* NMAR */ + + RESERVED, /* spr register 2051 */ + + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* IBAR0 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* IBAR3 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DBAR0 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DBAR3 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DBDR00 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DBDR03 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DBDR10 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DBDR13 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DBDR20 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DBDR23 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DBDR30 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DBDR33 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DBMR00 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DBMR03 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DBMR10 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DBMR13 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DBMR20 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DBMR23 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DBMR30 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DBMR33 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* CPCFR */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, /* CPCR */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, /* CPSR */ + + RESERVED, /* spr register 2095 */ + + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, /* CPESR0 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, /* CPESR1 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, /* CPEMR0 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, /* CPEMR1 */ + + /* spr registers 2100-2199 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + + /* spr registers 2200-2299 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + + /* spr registers 2300-2399 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + + /* spr registers 2400-2499 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + + /* spr registers 2500-2599 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + + /* spr registers 2600-2699 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + + /* spr registers 2700-2799 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + + /* spr registers 2800-2899 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + + /* spr registers 2900-2999 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + + /* spr registers 3000-3099 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + + /* spr registers 3100-3199 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + + /* spr registers 3200-3299 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + + /* spr registers 3300-3399 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + + /* spr registers 3400-3499 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + + /* spr registers 3500-3599 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + + /* spr registers 3600-3699 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + + /* spr registers 3700-3799 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + + /* spr registers 3800-3847 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0xffffffff, 0xfffffffe, IMPL, SUP}, /* IHSR8 */ + + /* spr registers 3849-4095 are reserved */ + RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED +}; + +/* SPR definitions for the fr500 machine. + See the FR500 LSI for implementation details. */ +static FRV_SPR_CONTROL_INFO fr500_spr[] = +{ + {0x1000107e, 0x1000107c, 0xff0071fd, 0xffff9e00, IMPL, SUP}, /* PSR */ + {0x00000000, 0x00000000, 0x00000003, 0x00000003, IMPL, SUP}, /* PCSR */ + {0x00000000, 0x00000000, 0xffffffff, 0x00000003, IMPL, SUP}, /* BPCSR */ + {0x00000000, 0x00000000, 0x0000000f, 0x000007ff, IMPL, SUP}, /* TBR */ + {0x00000000, 0x00000000, 0x00000000, 0xffffeffe, IMPL, SUP}, /* BPSR */ + + /* spr registers 5-15 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, + + {0x000003c0, 0x00000000, 0xce000c00, 0x313fec38, IMPL, SUP}, /* HSR0 */ + + /* HSR1-63 are unimplemented on the fr500. */ + RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, + + /* spr registers 80-255 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0x00000000, IMPL, USER}, /* CCR */ + + /* spr registers 257-262 are reserved */ + RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0xffff0000, IMPL, USER}, /* CCCR */ + + /* spr registers 264-271 are reserved */ + RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x00000003, 0x00000003, IMPL, USER}, /* LR */ + {0x00000000, 0x00000000, 0x00000000, 0x00000000, IMPL, USER}, /* LCR */ + + /* spr registers 274-287 are reserved */ + RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, + + {0x20000021, 0x20000000, 0xa0000000, 0xffffffc2, IMPL, USER}, /* ISR */ + + /* spr registers 289-351 are reserved */ + RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, + + /* NEEAR0-31 are unimplemented on the fr500. */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, + + /* NESR0-31 are unimplemented on the fr500. */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, + + /* NECR is unimplemented on the fr500. */ + RESERVED, + + /* spr registers 417-431 are reserved */ + RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0x00000000, IMPL, USER}, /* GNER0 */ + {0x00000000, 0x00000000, 0x00000000, 0x00000000, IMPL, USER}, /* GNER1 */ + {0x00000000, 0x00000000, 0x00000000, 0x00000000, IMPL, USER}, /* FNER0 */ + {0x00000000, 0x00000000, 0x00000000, 0x00000000, IMPL, USER}, /* FNER1 */ + + /* spr registers 436-511 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* EPCR0 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + + /* EPCR2-7 are unimplemented on the fr500. */ + RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* EPCR8 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* EPCR13 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + + /* EPCR16-63 are unimplemented on the fr500. */ + RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, + + {0x00000100, 0x00000100, 0x00000100, 0xffffffff, IMPL, SUP}, /* ESR0 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + + /* ESR2-7 are unimplemented on the fr500. */ + RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* ESR8 */ + {0x00000800, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000800, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000800, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* ESR13 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + + /* ESR16-63 are unimplemented on the fr500. */ + RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, + + /* EIR0-31 are unimplemented on the fr500. */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, + + /* ESFR0 is unimplemented on the fr500. */ + RESERVED, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* ESFR1 */ + + /* spr registers 674-767 are reserved */ + RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, + + /* SR0-SR3 are unimplemented on the fr500. */ + RESERVED, RESERVED, RESERVED, RESERVED, + + /* spr registers 772-1023 are reserved */ + RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, + + {0x00800000, 0x00800000, 0x00800000, 0xc0f103ff, IMPL, USER}, /* FSR0 */ + + /* FSR1-63 are unimplemented on the fr500. */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, + + /* Each FQ register is a pair of 32 bit registers. */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* FQ0 */ + {0x00000000, 0x00000000, 0x00000000, 0xfffffffe, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xfffffffe, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xfffffffe, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xfffffffe, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xfffffffe, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xfffffffe, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xfffffffe, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* FQ7 */ + {0x00000000, 0x00000000, 0x00000000, 0xfffffffe, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xfffffffe, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xfffffffe, IMPL, SUP}, + + /* FQ10-31 are unimplemented on the fr500. */ + /* Each FQ register is a pair of 32 bit registers. */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, + + /* spr registers 1152-1271 are reserved */ + RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, + + /* MCILR0-1 are unimplemented on the fr500. */ + RESERVED, RESERVED, + + /* spr registers 1274-1279 are reserved */ + RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x01e00000, 0x3fff8fc0, IMPL, USER}, /* MSR0 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffc1, IMPL, USER}, + + /* MSR2-63 are unimplemented on the fr500. */ + RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, + + /* MQ0-31 are unimplemented on the fr500. */ + /* Each MQ register is a pair of 32 bit registers. */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, + + /* Accumulators are read-only by the user except for special + insns and side effect of other insns. */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, /* ACC0 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, /* ACC7 */ + + /* ACC8-63 are unimplemented on the fr500. */ + RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, + + /* Accumulator guards are read-only by the user except for special + insns and side effect of other insns. */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, /* ACCG0 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, /* ACCG7 */ + + /* ACCG8-63 are unimplemented on the fr500. */ + RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, + + /* EAR0-7 are unimplemented on the fr500. */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* EAR8 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* EAR13 */ + + /* EAR14-63 are unimplemented on the fr500. */ + RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, + + /* EDR0-1 are unimplemented on the fr500. */ + RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* EDR2 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + + /* EDR4-5 are unimplemented on the fr500. */ + RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* EDR6 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + + /* EDR8-9 are unimplemented on the fr500. */ + RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* EDR10 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + + /* EDR12-63 are unimplemented on the fr500. */ + RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP}, /* IAMLR0 */ + {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP}, /* IAMLR7 */ + + /* IAMLR08-63 are unimplemented on the fr500. */ + RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP}, /* IAMPR0 */ + {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP}, /* IAMPR7 */ + + /* IAMPR08-63 are unimplemented on the fr500. */ + RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP}, /* DAMLR0 */ + {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP}, /* DAMLR7 */ + + /* DAMLR08-63 are unimplemented on the fr500. */ + RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP}, /* DAMPR0 */ + {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP}, /* DAMPR7 */ + + /* DAMPR08-63 are unimplemented on the fr500. */ + RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, + + {0x00000808, 0x00000808, 0x0000ffff, 0xffffffff, IMPL, SUP}, /* AMCR */ + + /* STBAR, MMCR not implemented on the fr500. */ + RESERVED, RESERVED, + + /* spr registers 1923-2047 are reserved */ + RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DCR */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* BRR */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* NMAR */ + + RESERVED, /* spr register 2051 */ + + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* IBAR0 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* IBAR3 */ + + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DBAR0 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DBAR3 */ + + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DBDR00 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + + /* DBDR02-03 are unimplemented on the fr500. */ + RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DBDR10 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + + /* DBDR12-13 are unimplemented on the fr500. */ + RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DBDR20 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + + /* DBDR22-23 are unimplemented on the fr500. */ + RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DBDR30 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + + /* DBDR32-33 are unimplemented on the fr500. */ + RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DBMR00 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + + /* DBMR02-03 are unimplemented on the fr500. */ + RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DBMR10 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + + /* DBMR12-13 are unimplemented on the fr500. */ + RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DBMR20 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + + /* DBMR22-23 are unimplemented on the fr500. */ + RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DBMR30 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + + /* DBMR32-33 are unimplemented on the fr500. */ + RESERVED, RESERVED, + + /* CPCFR, CPCR and CPSR are unimplemented on the fr500. */ + RESERVED, RESERVED, RESERVED, + + RESERVED, /* spr register 2095 */ + + /* CPESR0-1 are unimplemented on the fr500. */ + RESERVED, RESERVED, + + /* CPEMR0-1 are unimplemented on the fr500. */ + RESERVED, RESERVED, + + /* spr registers 2100-2199 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + + /* spr registers 2200-2299 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + + /* spr registers 2300-2399 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + + /* spr registers 2400-2499 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + + /* spr registers 2500-2599 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + + /* spr registers 2600-2699 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + + /* spr registers 2700-2799 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + + /* spr registers 2800-2899 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + + /* spr registers 2900-2999 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + + /* spr registers 3000-3099 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + + /* spr registers 3100-3199 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + + /* spr registers 3200-3299 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + + /* spr registers 3300-3399 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + + /* spr registers 3400-3499 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + + /* spr registers 3500-3599 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + + /* spr registers 3600-3699 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + + /* spr registers 3700-3799 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + + /* spr registers 3800-3847 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0xfffffffe, IMPL, SUP}, /* IHSR8 */ + + /* spr registers 3849-4095 are reserved */ + RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED +}; + +/* SPR definitions for the fr550 machine. + See the FR550 LSI for implementation details. */ +static FRV_SPR_CONTROL_INFO fr550_spr[] = +{ + {0x3000107e, 0x3000107c, 0xff0071fd, 0xffff9e00, IMPL, SUP}, /* PSR */ + {0x00000000, 0x00000000, 0x00000003, 0x00000003, IMPL, SUP}, /* PCSR */ + {0x00000000, 0x00000000, 0xffffffff, 0x00000003, IMPL, SUP}, /* BPCSR */ + {0x00000000, 0x00000000, 0x0000000f, 0x000007ff, IMPL, SUP}, /* TBR */ + {0x00000000, 0x00000000, 0x00000000, 0xffffeffe, IMPL, SUP}, /* BPSR */ + + /* spr registers 5-15 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, + + {0x000003c0, 0x00000000, 0xce000c00, 0x313fec38, IMPL, SUP}, /* HSR0 */ + + /* HSR1-63 are unimplemented on the fr550. */ + RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, + + /* spr registers 80-255 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0x00000000, IMPL, USER}, /* CCR */ + + /* spr registers 257-262 are reserved */ + RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0xffff0000, IMPL, USER}, /* CCCR */ + + /* spr registers 264-271 are reserved */ + RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x00000003, 0x00000003, IMPL, USER}, /* LR */ + {0x00000000, 0x00000000, 0x00000000, 0x00000000, IMPL, USER}, /* LCR */ + + /* spr registers 274-287 are reserved */ + RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, + + {0x20000030, 0x20000000, 0xa0000000, 0xffffffd3, IMPL, USER}, /* ISR */ + + /* spr registers 289-351 are reserved */ + RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, + + /* NEEAR0-31 are unimplemented on the fr550. */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, + + /* NESR0-31 are unimplemented on the fr550. */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, + + /* NECR is unimplemented on the fr550. */ + RESERVED, + + /* spr registers 417-431 are reserved */ + RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0x00000000, IMPL, USER}, /* GNER0 */ + {0x00000000, 0x00000000, 0x00000000, 0x00000000, IMPL, USER}, /* GNER1 */ + {0x00000000, 0x00000000, 0x00000000, 0x00000000, IMPL, USER}, /* FNER0 */ + {0x00000000, 0x00000000, 0x00000000, 0x00000000, IMPL, USER}, /* FNER1 */ + + /* spr registers 436-511 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* EPCR0 */ + RESERVED, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* EPCR2 */ + + /* EPCR3-7 are unimplemented on the fr550. */ + RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* EPCR8 */ + + /* EPCR9-63 are unimplemented on the fr550. */ + RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, + + {0x00000100, 0x00000100, 0x00000100, 0xffffffff, IMPL, SUP}, /* ESR0 */ + RESERVED, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* ESR2 */ + + /* ESR3-7 are unimplemented on the fr550. */ + RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, + + {0x00000200, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* ESR8 */ + + /* ESR9-13 are unimplemented on the fr550. */ + RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* ESR14 */ + {0x00000020, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + + /* ESR16-63 are unimplemented on the fr550. */ + RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, + + /* EIR0-31 are unimplemented on the fr550. */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, + + /* ESFR0 is unimplemented on the fr550. */ + RESERVED, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* ESFR1 */ + + /* spr registers 674-767 are reserved */ + RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, + + /* SR0-SR3 are unimplemented on the fr550. */ + RESERVED, RESERVED, RESERVED, RESERVED, + + /* spr registers 772-1023 are reserved */ + RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, + + {0x00800000, 0x00800000, 0xc0e00000, 0xc0fe03ff, IMPL, USER}, /* FSR0 */ + + /* FSR1-63 are unimplemented on the fr550. */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, + + /* FQ0-31 are unimplemented on the fr550. */ + /* Each FQ register is a pair of 32 bit registers. */ + RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, + + /* spr registers 1152-1271 are reserved */ + RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, + + /* MCILR0-1 are unimplemented on the fr550. */ + RESERVED, RESERVED, + + /* spr registers 1274-1279 are reserved */ + RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + + {0x00001002, 0x00000000, 0x01e00000, 0x07ffffc2, IMPL, USER}, /* MSR0 */ + + /* MSR1-63 are unimplemented on the fr550. */ + RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, + + /* MQ0-31 are unimplemented on the fr550. */ + /* Each MQ register is a pair of 32 bit registers. */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, + + /* Accumulators are read-only by the user except for special + insns and side effect of other insns. */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, /* ACC0 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, /* ACC7 */ + + /* ACC8-63 are unimplemented on the fr550. */ + RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, + + /* Accumulator guards are read-only by the user except for special + insns and side effect of other insns. */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, /* ACCG0 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, /* ACCG7 */ + + /* ACCG8-63 are unimplemented on the fr550. */ + RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, + + /* EAR0-7 are unimplemented on the fr550. */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* EAR8 */ + + /* EAR9-14 are unimplemented on the fr550. */ + RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* EAR15 */ + + /* EAR16-63 are unimplemented on the fr550. */ + RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, + + /* EDR0-63 are unimplemented on the fr550. */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP}, /* IAMLR0 */ + {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP}, /* IAMLR8 */ + {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP}, /* IAMLR15 */ + + /* IAMLR16-63 are unimplemented on the fr550. */ + RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP}, /* IAMPR0 */ + {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP}, /* IAMPR8 */ + {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP}, /* IAMPR15 */ + + /* IAMPR16-63 are unimplemented on the fr550. */ + RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP}, /* DAMLR0 */ + {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP}, /* DAMLR8 */ + {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP}, /* DAMLR15 */ + + /* DAMLR16-63 are unimplemented on the fr550. */ + RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP}, /* DAMPR0 */ + {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP}, /* DAMPR8 */ + {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP}, /* DAMPR15 */ + + /* DAMPR16-63 are unimplemented on the fr550. */ + RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, + + {0x00001010, 0x00001010, 0x0000ffff, 0xffffffff, IMPL, SUP}, /* AMCR */ + + /* STBAR, MMCR not implemented on the fr550. */ + RESERVED, RESERVED, + + /* spr registers 1923-2047 are reserved */ + RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DCR */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* BRR */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* NMAR */ + + RESERVED, /* spr register 2051 */ + + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* IBAR0 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* IBAR3 */ + + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DBAR0 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DBAR3 */ + + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DBDR00 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + + /* DBDR02-03 are unimplemented on the fr550. */ + RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DBDR10 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + + /* DBDR12-13 are unimplemented on the fr550. */ + RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DBDR20 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + + /* DBDR22-23 are unimplemented on the fr550. */ + RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DBDR30 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + + /* DBDR32-33 are unimplemented on the fr550. */ + RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DBMR00 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + + /* DBMR02-03 are unimplemented on the fr550. */ + RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DBMR10 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + + /* DBMR12-13 are unimplemented on the fr550. */ + RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DBMR20 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + + /* DBMR22-23 are unimplemented on the fr550. */ + RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DBMR30 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + + /* DBMR32-33 are unimplemented on the fr550. */ + RESERVED, RESERVED, + + /* CPCFR, CPCR and CPSR are unimplemented on the fr550. */ + RESERVED, RESERVED, RESERVED, + + RESERVED, /* spr register 2095 */ + + /* CPESR0-1 are unimplemented on the fr550. */ + RESERVED, RESERVED, + + /* CPEMR0-1 are unimplemented on the fr550. */ + RESERVED, RESERVED, + + /* spr registers 2100-2199 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + + /* spr registers 2200-2299 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + + /* spr registers 2300-2399 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + + /* spr registers 2400-2499 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + + /* spr registers 2500-2599 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + + /* spr registers 2600-2699 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + + /* spr registers 2700-2799 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + + /* spr registers 2800-2899 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + + /* spr registers 2900-2999 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + + /* spr registers 3000-3099 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + + /* spr registers 3100-3199 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + + /* spr registers 3200-3299 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + + /* spr registers 3300-3399 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + + /* spr registers 3400-3499 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + + /* spr registers 3500-3599 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + + /* spr registers 3600-3699 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + + /* spr registers 3700-3799 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + + /* spr registers 3800-3847 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, + + {0x00000001, 0x00000000, 0x00000000, 0xffff88fd, IMPL, SUP}, /* IHSR8 */ + + /* spr registers 3849-4095 are reserved */ + RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED +}; + +/* SPR definitions for the fr400 machine. + See the FR400 LSI for implementation details. */ +static FRV_SPR_CONTROL_INFO fr400_spr[] = +{ + {0x200030fe, 0x200030fc, 0xf00030fd, 0xffffff80, IMPL, SUP}, /* PSR */ + {0x00000000, 0x00000000, 0x00000003, 0x00000003, IMPL, SUP}, /* PCSR */ + {0x00000000, 0x00000000, 0xffffffff, 0x00000003, IMPL, SUP}, /* BPCSR */ + {0x00000000, 0x00000000, 0x0000000f, 0x000007ff, IMPL, SUP}, /* TBR */ + {0x00000000, 0x00000000, 0x00000000, 0xffffeffe, IMPL, SUP}, /* BPSR */ + + /* spr registers 5-15 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, + + {0x00000d40, 0x00000d40, 0xcc400fc0, 0x317feff8, IMPL, SUP}, /* HSR0 */ + + /* HSR1-63 are unimplemented on the fr400. */ + RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, + + /* spr registers 80-255 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0x00000000, IMPL, USER}, /* CCR */ + + /* spr registers 257-262 are reserved */ + RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0xffff0000, IMPL, USER}, /* CCCR */ + + /* spr registers 264-271 are reserved */ + RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x00000003, 0x00000003, IMPL, USER}, /* LR */ + {0x00000000, 0x00000000, 0x00000000, 0x00000000, IMPL, USER}, /* LCR */ + + /* spr registers 274-279 and 282-287 are reserved. */ + /* spr registers 280 and 281 are iacc0h and iacc0l (fr405). */ + RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + {0x00000000, 0x00000000, 0x00000000, 0x00000000, IMPL, USER}, /* IACC0H */ + {0x00000000, 0x00000000, 0x00000000, 0x00000000, IMPL, USER}, /* IACC0L */ + RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, + + {0x20000021, 0x20000000, 0xa0000000, 0xffffffc2, IMPL, USER}, /* ISR */ + + /* spr registers 289-351 are reserved */ + RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, + + /* NEEAR0-31 are unimplemented on the fr400. */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, + + /* NESR0-31 are unimplemented on the fr400. */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, + + /* NECR is unimplemented on the fr400. */ + RESERVED, + + /* spr registers 417-431 are reserved */ + RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, + + /* GNER0, GNER1, FNER0, FNER1 are unimplemented on the fr400. */ + RESERVED, RESERVED, RESERVED, RESERVED, + + /* spr registers 436-511 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* EPCR0 */ + + /* EPCR1-63 are unimplemented on the fr400. */ + RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, + + {0x00000100, 0x00000100, 0x00000100, 0xffffffff, IMPL, SUP}, /* ESR0 */ + + /* ESR1-13 are unimplemented on the fr400. */ + RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* ESR14 */ + {0x00000800, 0x00000800, 0x00000800, 0xffffffff, IMPL, SUP}, + + /* ESR16-63 are unimplemented on the fr400. */ + RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, + + /* EIR0-31 are unimplemented on the fr400. */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, + + /* ESFR0 is unimplemented on the fr400. */ + RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* ESFR1 */ + + /* spr registers 674-767 are reserved */ + RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, + + /* SR0-3 ARE unimplemented on the fr400. */ + RESERVED, RESERVED, RESERVED, RESERVED, + + /* spr registers 772-1023 are reserved */ + RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, + + /* FSR0-63 are unimplemented on the fr400. */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, + + /* FQ0-31 are unimplemented on the fr400. */ + /* Each FQ register is a pair of 32 bit registers. */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, + + /* spr registers 1152-1271 are reserved */ + RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, + + /* MCILR0-1 are unimplemented on the fr400. */ + RESERVED, RESERVED, + + /* spr registers 1274-1279 are reserved */ + RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x01c00000, 0x0fff8fc0, IMPL, USER}, /* MSR0 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffcd, IMPL, USER}, + + /* MSR2-63 are unimplemented on the fr400. */ + RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, + + /* MQ0-31 are unimplemented on the fr400. */ + /* Each MQ register is a pair of 32 bit registers. */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, + + /* Accumulators are read-only by the user except for special + insns and side effect of other insns. */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, /* ACC0 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + + /* ACC4-63 are unimplemented on the fr400. */ + RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, + + /* Accumulator guards are read-only by the user except for special + insns and side effect of other insns. */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, /* ACCG0 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + + /* ACCG4-63 are unimplemented on the fr400. */ + RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, + + /* EAR0-14 are unimplemented on the fr400. */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* EAR15 */ + + /* EAR16-63 are unimplemented on the fr400. */ + RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, + + /* EDR0-63 are unimplemented on the fr400. */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, + + /* IAMLR0-63 are unimplemented on the fr400. */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0x000fff02, IMPL, SUP}, /* IAMPR0 */ + {0x00000000, 0x00000000, 0x00000000, 0x000fff02, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fff02, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fff02, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fff02, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fff02, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fff02, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x000fff02, IMPL, SUP}, /* IAMPR7 */ + + /* IAMPR08-63 are unimplemented on the fr400. */ + RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, + + /* DAMLR0-63 are unimplemented on the fr400. */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x00000001, 0x000fff00, IMPL, SUP}, /* DAMPR0 */ + {0x00000000, 0x00000000, 0x00000001, 0x000fff00, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000001, 0x000fff00, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000001, 0x000fff00, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000001, 0x000fff00, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000001, 0x000fff00, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000001, 0x000fff00, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000001, 0x000fff00, IMPL, SUP}, /* DAMPR7 */ + + /* DAMPR08-63 are unimplemented on the fr400. */ + RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, + + {0x00000808, 0x00000808, 0x00000808, 0xffffffff, IMPL, SUP}, /* AMCR */ + + /* STBAR, MMCR not implemented on the fr400. */ + RESERVED, RESERVED, + + /* spr registers 1923-2047 are reserved */ + RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DCR */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* BRR */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* NMAR */ + + RESERVED, /* spr register 2051 */ + + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* IBAR0 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* IBAR3 */ + + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DBAR0 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + + /* DBAR2-3 not implemented on the fr400. */ + RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DBDR00 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + + /* DBDR02-03 are unimplemented on the fr400. */ + RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DBDR10 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + + /* DBDR12-13 are unimplemented on the fr400. */ + RESERVED, RESERVED, + + /* DBDR20-23 are unimplemented on the fr400. */ + RESERVED, RESERVED, RESERVED, RESERVED, + + /* DBDR30-33 are unimplemented on the fr400. */ + RESERVED, RESERVED, RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DBMR00 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + + /* DBMR02-03 are unimplemented on the fr400. */ + RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DBMR10 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + + /* DBMR12-13 are unimplemented on the fr400. */ + RESERVED, RESERVED, + + /* DBMR20-23 are unimplemented on the fr400. */ + RESERVED, RESERVED, RESERVED, RESERVED, + + /* DBMR30-33 are unimplemented on the fr400. */ + RESERVED, RESERVED, RESERVED, RESERVED, + + /* CPCFR, CPCR and CPSR are unimplemented on the fr400. */ + RESERVED, RESERVED, RESERVED, + + RESERVED, /* spr register 2095 */ + + /* CPESR0-1 are unimplemented on the fr400. */ + RESERVED, RESERVED, + + /* CPEMR0-1 are unimplemented on the fr400. */ + RESERVED, RESERVED, + + /* spr registers 2100-2199 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + + /* spr registers 2200-2299 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + + /* spr registers 2300-2399 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + + /* spr registers 2400-2499 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + + /* spr registers 2500-2599 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + + /* spr registers 2600-2699 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + + /* spr registers 2700-2799 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + + /* spr registers 2800-2899 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + + /* spr registers 2900-2999 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + + /* spr registers 3000-3099 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + + /* spr registers 3100-3199 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + + /* spr registers 3200-3299 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + + /* spr registers 3300-3399 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + + /* spr registers 3400-3499 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + + /* spr registers 3500-3599 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + + /* spr registers 3600-3699 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + + /* spr registers 3700-3799 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + + /* spr registers 3800-3899 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + + /* spr registers 3900-3999 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + + /* spr registers 4000-4095 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED +}; + +/* Initialize register control for this cpu */ +void +frv_register_control_init (SIM_CPU *cpu) +{ + FRV_REGISTER_CONTROL *control = CPU_REGISTER_CONTROL (cpu); + SIM_DESC sd = CPU_STATE (cpu); + int mach = STATE_ARCHITECTURE (sd)->mach; + + if (sizeof (fr400_spr) != FRV_MAX_SPR * sizeof (*fr400_spr)) + abort (); + if (sizeof (fr500_spr) != FRV_MAX_SPR * sizeof (*fr500_spr)) + abort (); + if (sizeof (fr550_spr) != FRV_MAX_SPR * sizeof (*fr550_spr)) + abort (); + if (sizeof (frv_spr) != FRV_MAX_SPR * sizeof (*frv_spr)) + abort (); + + switch (mach) + { + case bfd_mach_frvtomcat: + case bfd_mach_fr500: + control->fr = 1; + control->cpr = 0; + control->spr = fr500_spr; + return; + case bfd_mach_fr550: + control->fr = 1; + control->cpr = 0; + control->spr = fr550_spr; + return; + case bfd_mach_fr400: + control->fr = 1; + control->cpr = 0; + control->spr = fr400_spr; + return; + case bfd_mach_frvsimple: + control->fr = 0; + control->cpr = 0; + control->spr = fr500_spr; /* Use the same spr configuration as fr500. */ + return; + case bfd_mach_frv: + control->fr = 1; + control->cpr = 1; + control->spr = frv_spr; + return; + } + + { + IADDR pc = CPU_PC_GET (cpu); + sim_engine_abort (sd, cpu, pc, + "Register control not defined for bfd machine %d\n", + mach); + } +} + +/* Initialize spr registers. Used during startup and during hardware reset. */ +void +frv_initialize_spr (SIM_CPU *current_cpu) +{ + FRV_REGISTER_CONTROL *control = CPU_REGISTER_CONTROL (current_cpu); + FRV_SPR_CONTROL_INFO *spr_control; + USI save_mask; + int i; + + /* Make sure that PSR.S is set in order to avoid access problems. + Set the hardware directly to avoid user/supervisor state change. */ + CPU (h_psr_s) = 1; + + /* Now initialize each register except PSR. */ + for (i = 0; i < FRV_MAX_SPR; ++i) + { + /* Make sure that the register is implemented and is not PSR. */ + spr_control = & control->spr[i]; + if (spr_control->implemented && i != H_SPR_PSR) + { + /* Temporarily disable the read-only mask for this register in order + to initialize read-only fields. */ + save_mask = spr_control->read_only_mask; + spr_control->read_only_mask = 0; + SET_H_SPR (i, spr_control->init_value); + spr_control->read_only_mask = save_mask; + } + } + + /* Now explicitely set PSR in order to get the correct setting for PSR.S. */ + spr_control = & control->spr[H_SPR_PSR]; + save_mask = spr_control->read_only_mask; + spr_control->read_only_mask = 0; + SET_H_SPR (H_SPR_PSR, spr_control->init_value); + spr_control->read_only_mask = save_mask; +} + +/* Reset spr registers. Used during software reset. */ +void +frv_reset_spr (SIM_CPU *current_cpu) +{ + FRV_REGISTER_CONTROL *control = CPU_REGISTER_CONTROL (current_cpu); + FRV_SPR_CONTROL_INFO *spr_control; + USI mask; + USI new_val; + int i; + int psr_s; + + /* Save PSR.S so that it can be stored in PSR.PS when initialization is + complete. */ + psr_s = GET_H_PSR_S (); + + /* Make sure that PSR.S is set in order to avoid access problems. + Set the hardware directly to avoid user/supervisor state change. */ + CPU (h_psr_s) = 1; + + /* Now reset each register except PSR. */ + for (i = 0; i < FRV_MAX_SPR; ++i) + { + /* Make sure that the register is implemented and is not PSR. */ + spr_control = & control->spr[i]; + if (spr_control->implemented && i != H_SPR_PSR) + { + mask = spr_control->reset_mask; + new_val = GET_H_SPR (i) & ~mask; + new_val |= spr_control->reset_value & mask; + SET_H_SPR (i, new_val); + } + } + + /* Now explicitely set PSR in order to get the correct setting for PSR.S. */ + spr_control = & control->spr[H_SPR_PSR]; + mask = spr_control->reset_mask; + new_val = GET_H_SPR (H_SPR_PSR) & ~mask; + new_val |= spr_control->reset_value & mask; + SET_H_SPR (H_SPR_PSR, new_val); + + /* Now set PSR.PS with the previous value of PSR.S. */ + SET_H_PSR_PS (psr_s); +} + +/* Check access to spr registers. */ +void +frv_check_spr_read_access (SIM_CPU *current_cpu, UINT spr) +{ + FRV_REGISTER_CONTROL *control = CPU_REGISTER_CONTROL (current_cpu); + + if (! control->spr[spr].implemented) + { + SIM_DESC sd = CPU_STATE (current_cpu); + switch (STATE_ARCHITECTURE (sd)->mach) + { + case bfd_mach_fr400: + /* On the fr400: if this is an unimplemented accumulator, then + generate an illegal_instruction_interrupt, otherwise no interrupt. + */ + if (spr >= H_SPR_ACC4 && spr <= H_SPR_ACC63 + || spr >= H_SPR_ACCG4 && spr <= H_SPR_ACCG63) + frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION); + break; + case bfd_mach_fr550: + /* No interrupt on the fr550 */ + break; + default: + frv_queue_register_exception_interrupt (current_cpu, FRV_REC_UNIMPLEMENTED); + break; + } + } +} + +void +frv_check_spr_write_access (SIM_CPU *current_cpu, UINT spr) +{ + /* Both a register exception (unimplemented) and a privileged insn exception + are possible. Check for both and the let the priority be resolved by the + exception handling code. */ + FRV_REGISTER_CONTROL *control = CPU_REGISTER_CONTROL (current_cpu); + + /* Write access check is a superset of the read access check. */ + frv_check_spr_read_access (current_cpu, spr); + + /* Check for write to supervisor register. */ + if (control->spr[spr].supervisor && ! GET_H_PSR_S ()) + frv_queue_program_interrupt (current_cpu, FRV_PRIVILEGED_INSTRUCTION); +} + +void +frv_fr_registers_available ( + SIM_CPU *current_cpu, int *hi_available, int *lo_available +) +{ + int all_implemented; + SI hsr0 = GET_HSR0 (); + + /* If ! all_implemented, then registers 0-32 are available, otherwise check + availability of the hi/lo banks by checking the HSR0 register. */ + all_implemented = ! GET_HSR0_FRN (hsr0); + *hi_available = all_implemented && GET_HSR0_FRHE (hsr0); + *lo_available = (! all_implemented) || GET_HSR0_FRLE (hsr0); +} + +void +frv_gr_registers_available ( + SIM_CPU *current_cpu, int *hi_available, int *lo_available +) +{ + int all_implemented; + SI hsr0 = GET_HSR0 (); + + /* If ! all_implemented, then registers 0-32 are available, otherwise check + availability of the hi/lo banks by checking the HSR0 register. */ + all_implemented = ! GET_HSR0_GRN (hsr0); + *hi_available = all_implemented && GET_HSR0_GRHE (hsr0); + *lo_available = (! all_implemented) || GET_HSR0_GRLE (hsr0); +} + +/* Return 1 if the given register is available, 0 otherwise. TARGET_INDEX==-1 + means to check for any register available. */ +int +frv_check_register_access ( + SIM_CPU *current_cpu, + SI target_index, + int hi_available, + int lo_available +) +{ + SIM_DESC sd; + if (target_index > 31) + { + if (hi_available) + return 1; + } + else + { + if (lo_available) + return 1; + + if (target_index == -1 && hi_available) + return 1; + } + + /* The register is not available. Generate an exception. */ + sd = CPU_STATE (current_cpu); + switch (STATE_ARCHITECTURE (sd)->mach) + { + case bfd_mach_fr400: + case bfd_mach_fr550: + /* On some machines this generates an illegal_instruction interrupt. */ + frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION); + break; + default: + /* On other machines, it's a register_exception. */ + frv_queue_register_exception_interrupt (current_cpu, FRV_REC_UNIMPLEMENTED); + break; + } + return 0; +} + +/* Return 1 if the given register is available, 0 otherwise. TARGET_INDEX==-1 + means to check for any register available. */ +int +frv_check_gr_access (SIM_CPU *current_cpu, SI target_index) +{ + int hi_available; + int lo_available; + + frv_gr_registers_available (current_cpu, & hi_available, & lo_available); + return frv_check_register_access (current_cpu, target_index, + hi_available, lo_available); +} + +/* Return 1 if the given register is available, 0 otherwise. TARGET_INDEX==-1 + means to check for any register available. */ +int +frv_check_fr_access (SIM_CPU *current_cpu, SI target_index) +{ + int hi_available; + int lo_available; + + frv_fr_registers_available (current_cpu, & hi_available, & lo_available); + return frv_check_register_access (current_cpu, target_index, + hi_available, lo_available); +} diff --git a/sim/frv/registers.h b/sim/frv/registers.h new file mode 100644 index 0000000..dba4d96 --- /dev/null +++ b/sim/frv/registers.h @@ -0,0 +1,59 @@ +/* Register definitions for the FRV simulator + Copyright (C) 2000 Free Software Foundation, Inc. + Contributed by Red Hat. + +This file is part of the GNU Simulators. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef REGISTERS_H +#define REGISTERS_H + +#define FRV_MAX_GR 64 +#define FRV_MAX_FR 64 +#define FRV_MAX_CPR 64 +#define FRV_MAX_SPR 4096 + +/* Register init, reset values and read_only masks. */ +typedef struct +{ + USI init_value; /* initial value */ + USI reset_value; /* value for software reset */ + USI reset_mask; /* bits which are reset */ + USI read_only_mask; /* bits which are read-only */ + char implemented; /* 1==register is implemented */ + char supervisor; /* 1==register is supervisor-only */ +} FRV_SPR_CONTROL_INFO; + +typedef struct +{ + int fr; /* FR registers implemented */ + int cpr; /* coprocessor registers implemented */ + FRV_SPR_CONTROL_INFO *spr; /* SPR implementation details */ +} FRV_REGISTER_CONTROL; + +void frv_register_control_init (SIM_CPU *); +void frv_initialize_spr (SIM_CPU *); +void frv_reset_spr (SIM_CPU *); + +void frv_check_spr_access (SIM_CPU *, UINT); + +void frv_fr_registers_available (SIM_CPU *, int *, int *); +void frv_gr_registers_available (SIM_CPU *, int *, int *); +int frv_check_register_access (SIM_CPU *, SI, int, int); +int frv_check_gr_access (SIM_CPU *, SI); +int frv_check_fr_access (SIM_CPU *, SI); + +#endif /* REGISTERS_H */ diff --git a/sim/frv/reset.c b/sim/frv/reset.c new file mode 100644 index 0000000..070a431 --- /dev/null +++ b/sim/frv/reset.c @@ -0,0 +1,152 @@ +/* frv simulator support code + Copyright (C) 1999, 2000, 2001, 2003 Free Software Foundation, Inc. + Contributed by Red Hat. + +This file is part of the GNU simulators. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#define WANT_CPU +#define WANT_CPU_FRVBF + +#include "sim-main.h" +#include "bfd.h" + +/* Initialize the frv simulator. */ +void +frv_initialize (SIM_CPU *current_cpu, SIM_DESC sd) +{ + FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (current_cpu); + PROFILE_DATA *p = CPU_PROFILE_DATA (current_cpu); + FRV_CACHE *insn_cache = CPU_INSN_CACHE (current_cpu); + FRV_CACHE *data_cache = CPU_DATA_CACHE (current_cpu); + int insn_cache_enabled = CACHE_INITIALIZED (insn_cache); + int data_cache_enabled = CACHE_INITIALIZED (data_cache); + USI hsr0; + + /* Initialize the register control information first since some of the + register values are used in further configuration. */ + frv_register_control_init (current_cpu); + + /* We need to ensure that the caches are initialized even if they are not + initially enabled (via commandline) because they can be enabled by + software. */ + if (! insn_cache_enabled) + frv_cache_init (current_cpu, CPU_INSN_CACHE (current_cpu)); + if (! data_cache_enabled) + frv_cache_init (current_cpu, CPU_DATA_CACHE (current_cpu)); + + /* Set the default cpu frequency if it has not been set on the command + line. */ + if (PROFILE_CPU_FREQ (p) == 0) + PROFILE_CPU_FREQ (p) = 266000000; /* 266MHz */ + + /* Allocate one cache line of memory containing the address of the reset + register Use the largest of the insn cache line size and the data cache + line size. */ + { + int addr = RSTR_ADDRESS; + void *aligned_buffer; + int bytes; + + if (CPU_INSN_CACHE (current_cpu)->line_size + > CPU_DATA_CACHE (current_cpu)->line_size) + bytes = CPU_INSN_CACHE (current_cpu)->line_size; + else + bytes = CPU_DATA_CACHE (current_cpu)->line_size; + + /* 'bytes' is a power of 2. Calculate the starting address of the + cache line. */ + addr &= ~(bytes - 1); + aligned_buffer = zalloc (bytes); /* clear */ + sim_core_attach (sd, NULL, 0, access_read_write, 0, addr, bytes, + 0, NULL, aligned_buffer); + } + + PROFILE_INFO_CPU_CALLBACK(p) = frv_profile_info; + ps->insn_fetch_address = -1; + ps->branch_address = -1; + + cgen_init_accurate_fpu (current_cpu, CGEN_CPU_FPU (current_cpu), + frvbf_fpu_error); + + /* Now perform power-on reset. */ + frv_power_on_reset (current_cpu); + + /* Make sure that HSR0.ICE and HSR0.DCE are set properly. */ + hsr0 = GET_HSR0 (); + if (insn_cache_enabled) + SET_HSR0_ICE (hsr0); + else + CLEAR_HSR0_ICE (hsr0); + if (data_cache_enabled) + SET_HSR0_DCE (hsr0); + else + CLEAR_HSR0_DCE (hsr0); + SET_HSR0 (hsr0); +} + +/* Initialize the frv simulator. */ +void +frv_term (SIM_DESC sd) +{ + /* If the timer is enabled, and model profiling was not originally enabled, + then turn it off again. This is the only place we can currently gain + control to do this. */ + if (frv_interrupt_state.timer.enabled && ! frv_save_profile_model_p) + sim_profile_set_option (current_state, "-model", PROFILE_MODEL_IDX, "0"); +} + +/* Perform a power on reset. */ +void +frv_power_on_reset (SIM_CPU *cpu) +{ + /* GR, FR and CPR registers are undefined at initialization time. */ + frv_initialize_spr (cpu); + /* Initialize the RSTR register (in memory). */ + if (frv_cache_enabled (CPU_DATA_CACHE (cpu))) + frvbf_mem_set_SI (cpu, CPU_PC_GET (cpu), RSTR_ADDRESS, RSTR_INITIAL_VALUE); + else + SETMEMSI (cpu, CPU_PC_GET (cpu), RSTR_ADDRESS, RSTR_INITIAL_VALUE); +} + +/* Perform a hardware reset. */ +void +frv_hardware_reset (SIM_CPU *cpu) +{ + /* GR, FR and CPR registers are undefined at hardware reset. */ + frv_initialize_spr (cpu); + /* Reset the RSTR register (in memory). */ + if (frv_cache_enabled (CPU_DATA_CACHE (cpu))) + frvbf_mem_set_SI (cpu, CPU_PC_GET (cpu), RSTR_ADDRESS, RSTR_HARDWARE_RESET); + else + SETMEMSI (cpu, CPU_PC_GET (cpu), RSTR_ADDRESS, RSTR_HARDWARE_RESET); + /* Reset the insn and data caches. */ + frv_cache_invalidate_all (CPU_INSN_CACHE (cpu), 0/* no flush */); + frv_cache_invalidate_all (CPU_DATA_CACHE (cpu), 0/* no flush */); +} + +/* Perform a software reset. */ +void +frv_software_reset (SIM_CPU *cpu) +{ + /* GR, FR and CPR registers are undefined at software reset. */ + frv_reset_spr (cpu); + /* Reset the RSTR register (in memory). */ + if (frv_cache_enabled (CPU_DATA_CACHE (cpu))) + frvbf_mem_set_SI (cpu, CPU_PC_GET (cpu), RSTR_ADDRESS, RSTR_SOFTWARE_RESET); + else + SETMEMSI (cpu, CPU_PC_GET (cpu), RSTR_ADDRESS, RSTR_SOFTWARE_RESET); +} diff --git a/sim/frv/sem.c b/sim/frv/sem.c new file mode 100644 index 0000000..4f2883b --- /dev/null +++ b/sim/frv/sem.c @@ -0,0 +1,28866 @@ +/* Simulator instruction semantics for frvbf. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. + +This file is part of the GNU simulators. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +*/ + +#define WANT_CPU frvbf +#define WANT_CPU_FRVBF + +#include "sim-main.h" +#include "cgen-mem.h" +#include "cgen-ops.h" + +#undef GET_ATTR +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_##attr) +#else +#define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_/**/attr) +#endif + +/* This is used so that we can compile two copies of the semantic code, + one with full feature support and one without that runs fast(er). + FAST_P, when desired, is defined on the command line, -DFAST_P=1. */ +#if FAST_P +#define SEM_FN_NAME(cpu,fn) XCONCAT3 (cpu,_semf_,fn) +#undef TRACE_RESULT +#define TRACE_RESULT(cpu, abuf, name, type, val) +#else +#define SEM_FN_NAME(cpu,fn) XCONCAT3 (cpu,_sem_,fn) +#endif + +/* x-invalid: --invalid-- */ + +static SEM_PC +SEM_FN_NAME (frvbf,x_invalid) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + { + /* Update the recorded pc in the cpu state struct. + Only necessary for WITH_SCACHE case, but to avoid the + conditional compilation .... */ + SET_H_PC (pc); + /* Virtual insns have zero size. Overwrite vpc with address of next insn + using the default-insn-bitsize spec. When executing insns in parallel + we may want to queue the fault and continue execution. */ + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + vpc = sim_engine_invalid_insn (current_cpu, pc, vpc); + } + + return vpc; +#undef FLD +} + +/* x-after: --after-- */ + +static SEM_PC +SEM_FN_NAME (frvbf,x_after) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + { +#if WITH_SCACHE_PBB_FRVBF + frvbf_pbb_after (current_cpu, sem_arg); +#endif + } + + return vpc; +#undef FLD +} + +/* x-before: --before-- */ + +static SEM_PC +SEM_FN_NAME (frvbf,x_before) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + { +#if WITH_SCACHE_PBB_FRVBF + frvbf_pbb_before (current_cpu, sem_arg); +#endif + } + + return vpc; +#undef FLD +} + +/* x-cti-chain: --cti-chain-- */ + +static SEM_PC +SEM_FN_NAME (frvbf,x_cti_chain) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + { +#if WITH_SCACHE_PBB_FRVBF +#ifdef DEFINE_SWITCH + vpc = frvbf_pbb_cti_chain (current_cpu, sem_arg, + pbb_br_type, pbb_br_npc); + BREAK (sem); +#else + /* FIXME: Allow provision of explicit ifmt spec in insn spec. */ + vpc = frvbf_pbb_cti_chain (current_cpu, sem_arg, + CPU_PBB_BR_TYPE (current_cpu), + CPU_PBB_BR_NPC (current_cpu)); +#endif +#endif + } + + return vpc; +#undef FLD +} + +/* x-chain: --chain-- */ + +static SEM_PC +SEM_FN_NAME (frvbf,x_chain) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + { +#if WITH_SCACHE_PBB_FRVBF + vpc = frvbf_pbb_chain (current_cpu, sem_arg); +#ifdef DEFINE_SWITCH + BREAK (sem); +#endif +#endif + } + + return vpc; +#undef FLD +} + +/* x-begin: --begin-- */ + +static SEM_PC +SEM_FN_NAME (frvbf,x_begin) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + { +#if WITH_SCACHE_PBB_FRVBF +#if defined DEFINE_SWITCH || defined FAST_P + /* In the switch case FAST_P is a constant, allowing several optimizations + in any called inline functions. */ + vpc = frvbf_pbb_begin (current_cpu, FAST_P); +#else +#if 0 /* cgen engine can't handle dynamic fast/full switching yet. */ + vpc = frvbf_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (current_cpu))); +#else + vpc = frvbf_pbb_begin (current_cpu, 0); +#endif +#endif +#endif + } + + return vpc; +#undef FLD +} + +/* add: add$pack $GRi,$GRj,$GRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,add) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* sub: sub$pack $GRi,$GRj,$GRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,sub) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = SUBSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* and: and$pack $GRi,$GRj,$GRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,and) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = ANDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* or: or$pack $GRi,$GRj,$GRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,or) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = ORSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* xor: xor$pack $GRi,$GRj,$GRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,xor) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = XORSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* not: not$pack $GRj,$GRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,not) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_scutss.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = INVSI (GET_H_GR (FLD (f_GRj))); + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* sdiv: sdiv$pack $GRi,$GRj,$GRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,sdiv) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_signed_integer_divide (current_cpu, GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)), FLD (f_GRk), 0); +; /*clobber*/ +} + + return vpc; +#undef FLD +} + +/* nsdiv: nsdiv$pack $GRi,$GRj,$GRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,nsdiv) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_signed_integer_divide (current_cpu, GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)), FLD (f_GRk), 1); +; /*clobber*/ +} + + return vpc; +#undef FLD +} + +/* udiv: udiv$pack $GRi,$GRj,$GRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,udiv) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_unsigned_integer_divide (current_cpu, GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)), FLD (f_GRk), 0); +; /*clobber*/ +} + + return vpc; +#undef FLD +} + +/* nudiv: nudiv$pack $GRi,$GRj,$GRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,nudiv) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_unsigned_integer_divide (current_cpu, GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)), FLD (f_GRk), 1); +; /*clobber*/ +} + + return vpc; +#undef FLD +} + +/* smul: smul$pack $GRi,$GRj,$GRdoublek */ + +static SEM_PC +SEM_FN_NAME (frvbf,smul) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + DI opval = MULDI (EXTSIDI (GET_H_GR (FLD (f_GRi))), EXTSIDI (GET_H_GR (FLD (f_GRj)))); + sim_queue_fn_di_write (current_cpu, frvbf_h_gr_double_set, FLD (f_GRk), opval); + TRACE_RESULT (current_cpu, abuf, "gr_double", 'D', opval); + } + + return vpc; +#undef FLD +} + +/* umul: umul$pack $GRi,$GRj,$GRdoublek */ + +static SEM_PC +SEM_FN_NAME (frvbf,umul) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + DI opval = MULDI (ZEXTSIDI (GET_H_GR (FLD (f_GRi))), ZEXTSIDI (GET_H_GR (FLD (f_GRj)))); + sim_queue_fn_di_write (current_cpu, frvbf_h_gr_double_set, FLD (f_GRk), opval); + TRACE_RESULT (current_cpu, abuf, "gr_double", 'D', opval); + } + + return vpc; +#undef FLD +} + +/* smu: smu$pack $GRi,$GRj */ + +static SEM_PC +SEM_FN_NAME (frvbf,smu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smass.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + DI opval = MULDI (EXTSIDI (GET_H_GR (FLD (f_GRi))), EXTSIDI (GET_H_GR (FLD (f_GRj)))); + sim_queue_fn_di_write (current_cpu, frvbf_h_iacc0_set, ((UINT) 0), opval); + TRACE_RESULT (current_cpu, abuf, "iacc0", 'D', opval); + } + + return vpc; +#undef FLD +} + +/* smass: smass$pack $GRi,$GRj */ + +static SEM_PC +SEM_FN_NAME (frvbf,smass) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smass.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + DI opval = (ANDIF (ANDIF (GTDI (MULDI (EXTSIDI (GET_H_GR (FLD (f_GRi))), EXTSIDI (GET_H_GR (FLD (f_GRj)))), 0), GTDI (GET_H_IACC0 (((UINT) 0)), 0)), LTDI (SUBDI (9223372036854775807, MULDI (EXTSIDI (GET_H_GR (FLD (f_GRi))), EXTSIDI (GET_H_GR (FLD (f_GRj))))), GET_H_IACC0 (((UINT) 0))))) ? (MAKEDI (2147483647, 0xffffffff)) : (ANDIF (ANDIF (LTDI (MULDI (EXTSIDI (GET_H_GR (FLD (f_GRi))), EXTSIDI (GET_H_GR (FLD (f_GRj)))), 0), LTDI (GET_H_IACC0 (((UINT) 0)), 0)), GTDI (SUBDI (9223372036854775808, MULDI (EXTSIDI (GET_H_GR (FLD (f_GRi))), EXTSIDI (GET_H_GR (FLD (f_GRj))))), GET_H_IACC0 (((UINT) 0))))) ? (MAKEDI (0x80000000, 0)) : (ADDDI (GET_H_IACC0 (((UINT) 0)), MULDI (EXTSIDI (GET_H_GR (FLD (f_GRi))), EXTSIDI (GET_H_GR (FLD (f_GRj)))))); + sim_queue_fn_di_write (current_cpu, frvbf_h_iacc0_set, ((UINT) 0), opval); + TRACE_RESULT (current_cpu, abuf, "iacc0", 'D', opval); + } + + return vpc; +#undef FLD +} + +/* smsss: smsss$pack $GRi,$GRj */ + +static SEM_PC +SEM_FN_NAME (frvbf,smsss) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smass.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + DI opval = (ANDIF (ANDIF (LTDI (MULDI (EXTSIDI (GET_H_GR (FLD (f_GRi))), EXTSIDI (GET_H_GR (FLD (f_GRj)))), 0), GTDI (GET_H_IACC0 (((UINT) 0)), 0)), LTDI (ADDDI (9223372036854775807, MULDI (EXTSIDI (GET_H_GR (FLD (f_GRi))), EXTSIDI (GET_H_GR (FLD (f_GRj))))), GET_H_IACC0 (((UINT) 0))))) ? (MAKEDI (2147483647, 0xffffffff)) : (ANDIF (ANDIF (GTDI (MULDI (EXTSIDI (GET_H_GR (FLD (f_GRi))), EXTSIDI (GET_H_GR (FLD (f_GRj)))), 0), LTDI (GET_H_IACC0 (((UINT) 0)), 0)), GTDI (ADDDI (9223372036854775808, MULDI (EXTSIDI (GET_H_GR (FLD (f_GRi))), EXTSIDI (GET_H_GR (FLD (f_GRj))))), GET_H_IACC0 (((UINT) 0))))) ? (MAKEDI (0x80000000, 0)) : (SUBDI (GET_H_IACC0 (((UINT) 0)), MULDI (EXTSIDI (GET_H_GR (FLD (f_GRi))), EXTSIDI (GET_H_GR (FLD (f_GRj)))))); + sim_queue_fn_di_write (current_cpu, frvbf_h_iacc0_set, ((UINT) 0), opval); + TRACE_RESULT (current_cpu, abuf, "iacc0", 'D', opval); + } + + return vpc; +#undef FLD +} + +/* sll: sll$pack $GRi,$GRj,$GRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,sll) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = SLLSI (GET_H_GR (FLD (f_GRi)), ANDSI (GET_H_GR (FLD (f_GRj)), 31)); + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* srl: srl$pack $GRi,$GRj,$GRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,srl) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = SRLSI (GET_H_GR (FLD (f_GRi)), ANDSI (GET_H_GR (FLD (f_GRj)), 31)); + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* sra: sra$pack $GRi,$GRj,$GRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,sra) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = SRASI (GET_H_GR (FLD (f_GRi)), ANDSI (GET_H_GR (FLD (f_GRj)), 31)); + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* slass: slass$pack $GRi,$GRj,$GRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,slass) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = frvbf_shift_left_arith_saturate (current_cpu, GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* scutss: scutss$pack $GRj,$GRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,scutss) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_scutss.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = frvbf_iacc_cut (current_cpu, GET_H_IACC0 (((UINT) 0)), GET_H_GR (FLD (f_GRj))); + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* scan: scan$pack $GRi,$GRj,$GRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,scan) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + SI tmp_tmp1; + SI tmp_tmp2; + tmp_tmp1 = GET_H_GR (FLD (f_GRi)); + tmp_tmp2 = SRASI (GET_H_GR (FLD (f_GRj)), 1); + { + SI opval = frvbf_scan_result (current_cpu, XORSI (tmp_tmp1, tmp_tmp2)); + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} + + return vpc; +#undef FLD +} + +/* cadd: cadd$pack $GRi,$GRj,$GRk,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cadd) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { + { + SI opval = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* csub: csub$pack $GRi,$GRj,$GRk,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,csub) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { + { + SI opval = SUBSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cand: cand$pack $GRi,$GRj,$GRk,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cand) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { + { + SI opval = ANDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cor: cor$pack $GRi,$GRj,$GRk,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cor) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { + { + SI opval = ORSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cxor: cxor$pack $GRi,$GRj,$GRk,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cxor) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { + { + SI opval = XORSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cnot: cnot$pack $GRj,$GRk,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cnot) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { + { + SI opval = INVSI (GET_H_GR (FLD (f_GRj))); + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* csmul: csmul$pack $GRi,$GRj,$GRdoublek,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,csmul) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { + { + DI opval = MULDI (EXTSIDI (GET_H_GR (FLD (f_GRi))), EXTSIDI (GET_H_GR (FLD (f_GRj)))); + sim_queue_fn_di_write (current_cpu, frvbf_h_gr_double_set, FLD (f_GRk), opval); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "gr_double", 'D', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* csdiv: csdiv$pack $GRi,$GRj,$GRk,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,csdiv) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +{ +frvbf_signed_integer_divide (current_cpu, GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)), FLD (f_GRk), 0); +; /*clobber*/ +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cudiv: cudiv$pack $GRi,$GRj,$GRk,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cudiv) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +{ +frvbf_unsigned_integer_divide (current_cpu, GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)), FLD (f_GRk), 0); +; /*clobber*/ +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* csll: csll$pack $GRi,$GRj,$GRk,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,csll) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { + { + SI opval = SLLSI (GET_H_GR (FLD (f_GRi)), ANDSI (GET_H_GR (FLD (f_GRj)), 31)); + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* csrl: csrl$pack $GRi,$GRj,$GRk,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,csrl) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { + { + SI opval = SRLSI (GET_H_GR (FLD (f_GRi)), ANDSI (GET_H_GR (FLD (f_GRj)), 31)); + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* csra: csra$pack $GRi,$GRj,$GRk,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,csra) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { + { + SI opval = SRASI (GET_H_GR (FLD (f_GRi)), ANDSI (GET_H_GR (FLD (f_GRj)), 31)); + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cscan: cscan$pack $GRi,$GRj,$GRk,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cscan) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +{ + SI tmp_tmp1; + SI tmp_tmp2; + tmp_tmp1 = GET_H_GR (FLD (f_GRi)); + tmp_tmp2 = SRASI (GET_H_GR (FLD (f_GRj)), 1); + { + SI opval = frvbf_scan_result (current_cpu, XORSI (tmp_tmp1, tmp_tmp2)); + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* addcc: addcc$pack $GRi,$GRj,$GRk,$ICCi_1 */ + +static SEM_PC +SEM_FN_NAME (frvbf,addcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + BI tmp_tmp; + QI tmp_cc; + SI tmp_result; + tmp_cc = CPU (h_iccr[FLD (f_ICCi_1)]); + tmp_tmp = ADDOFSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)), 0); +if (EQBI (tmp_tmp, 0)) { + tmp_cc = ANDQI (tmp_cc, 13); +} else { + tmp_cc = ORQI (tmp_cc, 2); +} + tmp_tmp = ADDCFSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)), 0); +if (EQBI (tmp_tmp, 0)) { + tmp_cc = ANDQI (tmp_cc, 14); +} else { + tmp_cc = ORQI (tmp_cc, 1); +} + tmp_result = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); +if (EQSI (tmp_result, 0)) { + tmp_cc = ORQI (ANDQI (tmp_cc, 7), 4); +} else { +if (LTSI (tmp_result, 0)) { + tmp_cc = ORQI (ANDQI (tmp_cc, 11), 8); +} else { + tmp_cc = ANDQI (tmp_cc, 3); +} +} + { + SI opval = tmp_result; + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + { + UQI opval = tmp_cc; + sim_queue_qi_write (current_cpu, & CPU (h_iccr[FLD (f_ICCi_1)]), opval); + TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval); + } +} + + return vpc; +#undef FLD +} + +/* subcc: subcc$pack $GRi,$GRj,$GRk,$ICCi_1 */ + +static SEM_PC +SEM_FN_NAME (frvbf,subcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + BI tmp_tmp; + QI tmp_cc; + SI tmp_result; + tmp_cc = CPU (h_iccr[FLD (f_ICCi_1)]); + tmp_tmp = SUBOFSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)), 0); +if (EQBI (tmp_tmp, 0)) { + tmp_cc = ANDQI (tmp_cc, 13); +} else { + tmp_cc = ORQI (tmp_cc, 2); +} + tmp_tmp = SUBCFSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)), 0); +if (EQBI (tmp_tmp, 0)) { + tmp_cc = ANDQI (tmp_cc, 14); +} else { + tmp_cc = ORQI (tmp_cc, 1); +} + tmp_result = SUBSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); +if (EQSI (tmp_result, 0)) { + tmp_cc = ORQI (ANDQI (tmp_cc, 7), 4); +} else { +if (LTSI (tmp_result, 0)) { + tmp_cc = ORQI (ANDQI (tmp_cc, 11), 8); +} else { + tmp_cc = ANDQI (tmp_cc, 3); +} +} + { + SI opval = tmp_result; + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + { + UQI opval = tmp_cc; + sim_queue_qi_write (current_cpu, & CPU (h_iccr[FLD (f_ICCi_1)]), opval); + TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval); + } +} + + return vpc; +#undef FLD +} + +/* andcc: andcc$pack $GRi,$GRj,$GRk,$ICCi_1 */ + +static SEM_PC +SEM_FN_NAME (frvbf,andcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + SI tmp_tmp; + tmp_tmp = ANDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); + { + SI opval = tmp_tmp; + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +if (EQSI (tmp_tmp, 0)) { + { + UQI opval = ORQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_1)]), 7), 4); + sim_queue_qi_write (current_cpu, & CPU (h_iccr[FLD (f_ICCi_1)]), opval); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval); + } +} else { +if (LTSI (tmp_tmp, 0)) { + { + UQI opval = ORQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_1)]), 11), 8); + sim_queue_qi_write (current_cpu, & CPU (h_iccr[FLD (f_ICCi_1)]), opval); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval); + } +} else { + { + UQI opval = ANDQI (CPU (h_iccr[FLD (f_ICCi_1)]), 3); + sim_queue_qi_write (current_cpu, & CPU (h_iccr[FLD (f_ICCi_1)]), opval); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval); + } +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* orcc: orcc$pack $GRi,$GRj,$GRk,$ICCi_1 */ + +static SEM_PC +SEM_FN_NAME (frvbf,orcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + SI tmp_tmp; + tmp_tmp = ORSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); + { + SI opval = tmp_tmp; + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +if (EQSI (tmp_tmp, 0)) { + { + UQI opval = ORQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_1)]), 7), 4); + sim_queue_qi_write (current_cpu, & CPU (h_iccr[FLD (f_ICCi_1)]), opval); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval); + } +} else { +if (LTSI (tmp_tmp, 0)) { + { + UQI opval = ORQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_1)]), 11), 8); + sim_queue_qi_write (current_cpu, & CPU (h_iccr[FLD (f_ICCi_1)]), opval); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval); + } +} else { + { + UQI opval = ANDQI (CPU (h_iccr[FLD (f_ICCi_1)]), 3); + sim_queue_qi_write (current_cpu, & CPU (h_iccr[FLD (f_ICCi_1)]), opval); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval); + } +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* xorcc: xorcc$pack $GRi,$GRj,$GRk,$ICCi_1 */ + +static SEM_PC +SEM_FN_NAME (frvbf,xorcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + SI tmp_tmp; + tmp_tmp = XORSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); + { + SI opval = tmp_tmp; + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +if (EQSI (tmp_tmp, 0)) { + { + UQI opval = ORQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_1)]), 7), 4); + sim_queue_qi_write (current_cpu, & CPU (h_iccr[FLD (f_ICCi_1)]), opval); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval); + } +} else { +if (LTSI (tmp_tmp, 0)) { + { + UQI opval = ORQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_1)]), 11), 8); + sim_queue_qi_write (current_cpu, & CPU (h_iccr[FLD (f_ICCi_1)]), opval); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval); + } +} else { + { + UQI opval = ANDQI (CPU (h_iccr[FLD (f_ICCi_1)]), 3); + sim_queue_qi_write (current_cpu, & CPU (h_iccr[FLD (f_ICCi_1)]), opval); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval); + } +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* sllcc: sllcc$pack $GRi,$GRj,$GRk,$ICCi_1 */ + +static SEM_PC +SEM_FN_NAME (frvbf,sllcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + SI tmp_shift; + SI tmp_tmp; + QI tmp_cc; + tmp_shift = ANDSI (GET_H_GR (FLD (f_GRj)), 31); + tmp_cc = frvbf_set_icc_for_shift_left (current_cpu, GET_H_GR (FLD (f_GRi)), tmp_shift, CPU (h_iccr[FLD (f_ICCi_1)])); + tmp_tmp = SLLSI (GET_H_GR (FLD (f_GRi)), tmp_shift); + { + SI opval = tmp_tmp; + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +if (EQSI (tmp_tmp, 0)) { + tmp_cc = ORQI (ANDQI (tmp_cc, 7), 4); +} else { +if (LTSI (tmp_tmp, 0)) { + tmp_cc = ORQI (ANDQI (tmp_cc, 11), 8); +} else { + tmp_cc = ANDQI (tmp_cc, 3); +} +} + { + UQI opval = tmp_cc; + sim_queue_qi_write (current_cpu, & CPU (h_iccr[FLD (f_ICCi_1)]), opval); + TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval); + } +} + + return vpc; +#undef FLD +} + +/* srlcc: srlcc$pack $GRi,$GRj,$GRk,$ICCi_1 */ + +static SEM_PC +SEM_FN_NAME (frvbf,srlcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + SI tmp_shift; + SI tmp_tmp; + QI tmp_cc; + tmp_shift = ANDSI (GET_H_GR (FLD (f_GRj)), 31); + tmp_cc = frvbf_set_icc_for_shift_right (current_cpu, GET_H_GR (FLD (f_GRi)), tmp_shift, CPU (h_iccr[FLD (f_ICCi_1)])); + tmp_tmp = SRLSI (GET_H_GR (FLD (f_GRi)), tmp_shift); + { + SI opval = tmp_tmp; + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +if (EQSI (tmp_tmp, 0)) { + tmp_cc = ORQI (ANDQI (tmp_cc, 7), 4); +} else { +if (LTSI (tmp_tmp, 0)) { + tmp_cc = ORQI (ANDQI (tmp_cc, 11), 8); +} else { + tmp_cc = ANDQI (tmp_cc, 3); +} +} + { + UQI opval = tmp_cc; + sim_queue_qi_write (current_cpu, & CPU (h_iccr[FLD (f_ICCi_1)]), opval); + TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval); + } +} + + return vpc; +#undef FLD +} + +/* sracc: sracc$pack $GRi,$GRj,$GRk,$ICCi_1 */ + +static SEM_PC +SEM_FN_NAME (frvbf,sracc) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + SI tmp_shift; + SI tmp_tmp; + QI tmp_cc; + tmp_shift = ANDSI (GET_H_GR (FLD (f_GRj)), 31); + tmp_cc = frvbf_set_icc_for_shift_right (current_cpu, GET_H_GR (FLD (f_GRi)), tmp_shift, CPU (h_iccr[FLD (f_ICCi_1)])); + tmp_tmp = SRASI (GET_H_GR (FLD (f_GRi)), tmp_shift); + { + SI opval = tmp_tmp; + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +if (EQSI (tmp_tmp, 0)) { + tmp_cc = ORQI (ANDQI (tmp_cc, 7), 4); +} else { +if (LTSI (tmp_tmp, 0)) { + tmp_cc = ORQI (ANDQI (tmp_cc, 11), 8); +} else { + tmp_cc = ANDQI (tmp_cc, 3); +} +} + { + UQI opval = tmp_cc; + sim_queue_qi_write (current_cpu, & CPU (h_iccr[FLD (f_ICCi_1)]), opval); + TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval); + } +} + + return vpc; +#undef FLD +} + +/* smulcc: smulcc$pack $GRi,$GRj,$GRdoublek,$ICCi_1 */ + +static SEM_PC +SEM_FN_NAME (frvbf,smulcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + DI tmp_tmp; + QI tmp_cc; + tmp_cc = CPU (h_iccr[FLD (f_ICCi_1)]); + tmp_tmp = MULDI (EXTSIDI (GET_H_GR (FLD (f_GRi))), EXTSIDI (GET_H_GR (FLD (f_GRj)))); +if (EQDI (SRLDI (tmp_tmp, 63), 0)) { + tmp_cc = ANDQI (tmp_cc, 7); +} else { + tmp_cc = ORQI (tmp_cc, 8); +} +if (EQBI (EQDI (tmp_tmp, 0), 0)) { + tmp_cc = ANDQI (tmp_cc, 11); +} else { + tmp_cc = ORQI (tmp_cc, 4); +} + { + DI opval = tmp_tmp; + sim_queue_fn_di_write (current_cpu, frvbf_h_gr_double_set, FLD (f_GRk), opval); + TRACE_RESULT (current_cpu, abuf, "gr_double", 'D', opval); + } + { + UQI opval = tmp_cc; + sim_queue_qi_write (current_cpu, & CPU (h_iccr[FLD (f_ICCi_1)]), opval); + TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval); + } +} + + return vpc; +#undef FLD +} + +/* umulcc: umulcc$pack $GRi,$GRj,$GRdoublek,$ICCi_1 */ + +static SEM_PC +SEM_FN_NAME (frvbf,umulcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + DI tmp_tmp; + QI tmp_cc; + tmp_cc = CPU (h_iccr[FLD (f_ICCi_1)]); + tmp_tmp = MULDI (ZEXTSIDI (GET_H_GR (FLD (f_GRi))), ZEXTSIDI (GET_H_GR (FLD (f_GRj)))); +if (EQDI (SRLDI (tmp_tmp, 63), 0)) { + tmp_cc = ANDQI (tmp_cc, 7); +} else { + tmp_cc = ORQI (tmp_cc, 8); +} +if (EQBI (EQDI (tmp_tmp, 0), 0)) { + tmp_cc = ANDQI (tmp_cc, 11); +} else { + tmp_cc = ORQI (tmp_cc, 4); +} + { + DI opval = tmp_tmp; + sim_queue_fn_di_write (current_cpu, frvbf_h_gr_double_set, FLD (f_GRk), opval); + TRACE_RESULT (current_cpu, abuf, "gr_double", 'D', opval); + } + { + UQI opval = tmp_cc; + sim_queue_qi_write (current_cpu, & CPU (h_iccr[FLD (f_ICCi_1)]), opval); + TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval); + } +} + + return vpc; +#undef FLD +} + +/* caddcc: caddcc$pack $GRi,$GRj,$GRk,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,caddcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_caddcc.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +{ + BI tmp_tmp; + QI tmp_cc; + SI tmp_result; + tmp_cc = CPU (h_iccr[((FLD (f_CCi)) & (3))]); + tmp_tmp = ADDOFSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)), 0); +if (EQBI (tmp_tmp, 0)) { + tmp_cc = ANDQI (tmp_cc, 13); +} else { + tmp_cc = ORQI (tmp_cc, 2); +} + tmp_tmp = ADDCFSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)), 0); +if (EQBI (tmp_tmp, 0)) { + tmp_cc = ANDQI (tmp_cc, 14); +} else { + tmp_cc = ORQI (tmp_cc, 1); +} + tmp_result = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); +if (EQSI (tmp_result, 0)) { + tmp_cc = ORQI (ANDQI (tmp_cc, 7), 4); +} else { +if (LTSI (tmp_result, 0)) { + tmp_cc = ORQI (ANDQI (tmp_cc, 11), 8); +} else { + tmp_cc = ANDQI (tmp_cc, 3); +} +} + { + SI opval = tmp_result; + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + { + UQI opval = tmp_cc; + sim_queue_qi_write (current_cpu, & CPU (h_iccr[((FLD (f_CCi)) & (3))]), opval); + written |= (1 << 7); + TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* csubcc: csubcc$pack $GRi,$GRj,$GRk,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,csubcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_caddcc.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +{ + BI tmp_tmp; + QI tmp_cc; + SI tmp_result; + tmp_cc = CPU (h_iccr[((FLD (f_CCi)) & (3))]); + tmp_tmp = SUBOFSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)), 0); +if (EQBI (tmp_tmp, 0)) { + tmp_cc = ANDQI (tmp_cc, 13); +} else { + tmp_cc = ORQI (tmp_cc, 2); +} + tmp_tmp = SUBCFSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)), 0); +if (EQBI (tmp_tmp, 0)) { + tmp_cc = ANDQI (tmp_cc, 14); +} else { + tmp_cc = ORQI (tmp_cc, 1); +} + tmp_result = SUBSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); +if (EQSI (tmp_result, 0)) { + tmp_cc = ORQI (ANDQI (tmp_cc, 7), 4); +} else { +if (LTSI (tmp_result, 0)) { + tmp_cc = ORQI (ANDQI (tmp_cc, 11), 8); +} else { + tmp_cc = ANDQI (tmp_cc, 3); +} +} + { + SI opval = tmp_result; + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + { + UQI opval = tmp_cc; + sim_queue_qi_write (current_cpu, & CPU (h_iccr[((FLD (f_CCi)) & (3))]), opval); + written |= (1 << 7); + TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* csmulcc: csmulcc$pack $GRi,$GRj,$GRdoublek,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,csmulcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_csmulcc.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +{ + DI tmp_tmp; + QI tmp_cc; + tmp_cc = CPU (h_iccr[((FLD (f_CCi)) & (3))]); + tmp_tmp = MULDI (EXTSIDI (GET_H_GR (FLD (f_GRi))), EXTSIDI (GET_H_GR (FLD (f_GRj)))); +if (EQDI (SRLDI (tmp_tmp, 63), 0)) { + tmp_cc = ANDQI (tmp_cc, 7); +} else { + tmp_cc = ORQI (tmp_cc, 8); +} +if (EQBI (EQDI (tmp_tmp, 0), 0)) { + tmp_cc = ANDQI (tmp_cc, 11); +} else { + tmp_cc = ORQI (tmp_cc, 4); +} + { + DI opval = tmp_tmp; + sim_queue_fn_di_write (current_cpu, frvbf_h_gr_double_set, FLD (f_GRk), opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "gr_double", 'D', opval); + } + { + UQI opval = tmp_cc; + sim_queue_qi_write (current_cpu, & CPU (h_iccr[((FLD (f_CCi)) & (3))]), opval); + written |= (1 << 7); + TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* candcc: candcc$pack $GRi,$GRj,$GRk,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,candcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_caddcc.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +{ + SI tmp_tmp; + tmp_tmp = ANDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); + { + SI opval = tmp_tmp; + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +if (EQSI (tmp_tmp, 0)) { + { + UQI opval = ORQI (ANDQI (CPU (h_iccr[((FLD (f_CCi)) & (3))]), 7), 4); + sim_queue_qi_write (current_cpu, & CPU (h_iccr[((FLD (f_CCi)) & (3))]), opval); + written |= (1 << 7); + TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval); + } +} else { +if (LTSI (tmp_tmp, 0)) { + { + UQI opval = ORQI (ANDQI (CPU (h_iccr[((FLD (f_CCi)) & (3))]), 11), 8); + sim_queue_qi_write (current_cpu, & CPU (h_iccr[((FLD (f_CCi)) & (3))]), opval); + written |= (1 << 7); + TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval); + } +} else { + { + UQI opval = ANDQI (CPU (h_iccr[((FLD (f_CCi)) & (3))]), 3); + sim_queue_qi_write (current_cpu, & CPU (h_iccr[((FLD (f_CCi)) & (3))]), opval); + written |= (1 << 7); + TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval); + } +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* corcc: corcc$pack $GRi,$GRj,$GRk,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,corcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_caddcc.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +{ + SI tmp_tmp; + tmp_tmp = ORSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); + { + SI opval = tmp_tmp; + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +if (EQSI (tmp_tmp, 0)) { + { + UQI opval = ORQI (ANDQI (CPU (h_iccr[((FLD (f_CCi)) & (3))]), 7), 4); + sim_queue_qi_write (current_cpu, & CPU (h_iccr[((FLD (f_CCi)) & (3))]), opval); + written |= (1 << 7); + TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval); + } +} else { +if (LTSI (tmp_tmp, 0)) { + { + UQI opval = ORQI (ANDQI (CPU (h_iccr[((FLD (f_CCi)) & (3))]), 11), 8); + sim_queue_qi_write (current_cpu, & CPU (h_iccr[((FLD (f_CCi)) & (3))]), opval); + written |= (1 << 7); + TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval); + } +} else { + { + UQI opval = ANDQI (CPU (h_iccr[((FLD (f_CCi)) & (3))]), 3); + sim_queue_qi_write (current_cpu, & CPU (h_iccr[((FLD (f_CCi)) & (3))]), opval); + written |= (1 << 7); + TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval); + } +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cxorcc: cxorcc$pack $GRi,$GRj,$GRk,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cxorcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_caddcc.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +{ + SI tmp_tmp; + tmp_tmp = XORSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); + { + SI opval = tmp_tmp; + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +if (EQSI (tmp_tmp, 0)) { + { + UQI opval = ORQI (ANDQI (CPU (h_iccr[((FLD (f_CCi)) & (3))]), 7), 4); + sim_queue_qi_write (current_cpu, & CPU (h_iccr[((FLD (f_CCi)) & (3))]), opval); + written |= (1 << 7); + TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval); + } +} else { +if (LTSI (tmp_tmp, 0)) { + { + UQI opval = ORQI (ANDQI (CPU (h_iccr[((FLD (f_CCi)) & (3))]), 11), 8); + sim_queue_qi_write (current_cpu, & CPU (h_iccr[((FLD (f_CCi)) & (3))]), opval); + written |= (1 << 7); + TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval); + } +} else { + { + UQI opval = ANDQI (CPU (h_iccr[((FLD (f_CCi)) & (3))]), 3); + sim_queue_qi_write (current_cpu, & CPU (h_iccr[((FLD (f_CCi)) & (3))]), opval); + written |= (1 << 7); + TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval); + } +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* csllcc: csllcc$pack $GRi,$GRj,$GRk,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,csllcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_caddcc.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +{ + SI tmp_shift; + SI tmp_tmp; + QI tmp_cc; + tmp_shift = ANDSI (GET_H_GR (FLD (f_GRj)), 31); + tmp_cc = frvbf_set_icc_for_shift_left (current_cpu, GET_H_GR (FLD (f_GRi)), tmp_shift, CPU (h_iccr[((FLD (f_CCi)) & (3))])); + tmp_tmp = SLLSI (GET_H_GR (FLD (f_GRi)), tmp_shift); + { + SI opval = tmp_tmp; + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +if (EQSI (tmp_tmp, 0)) { + tmp_cc = ORQI (ANDQI (tmp_cc, 7), 4); +} else { +if (LTSI (tmp_tmp, 0)) { + tmp_cc = ORQI (ANDQI (tmp_cc, 11), 8); +} else { + tmp_cc = ANDQI (tmp_cc, 3); +} +} + { + UQI opval = tmp_cc; + sim_queue_qi_write (current_cpu, & CPU (h_iccr[((FLD (f_CCi)) & (3))]), opval); + written |= (1 << 7); + TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* csrlcc: csrlcc$pack $GRi,$GRj,$GRk,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,csrlcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_caddcc.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +{ + SI tmp_shift; + SI tmp_tmp; + QI tmp_cc; + tmp_shift = ANDSI (GET_H_GR (FLD (f_GRj)), 31); + tmp_cc = frvbf_set_icc_for_shift_right (current_cpu, GET_H_GR (FLD (f_GRi)), tmp_shift, CPU (h_iccr[((FLD (f_CCi)) & (3))])); + tmp_tmp = SRLSI (GET_H_GR (FLD (f_GRi)), tmp_shift); + { + SI opval = tmp_tmp; + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +if (EQSI (tmp_tmp, 0)) { + tmp_cc = ORQI (ANDQI (tmp_cc, 7), 4); +} else { +if (LTSI (tmp_tmp, 0)) { + tmp_cc = ORQI (ANDQI (tmp_cc, 11), 8); +} else { + tmp_cc = ANDQI (tmp_cc, 3); +} +} + { + UQI opval = tmp_cc; + sim_queue_qi_write (current_cpu, & CPU (h_iccr[((FLD (f_CCi)) & (3))]), opval); + written |= (1 << 7); + TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* csracc: csracc$pack $GRi,$GRj,$GRk,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,csracc) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_caddcc.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +{ + SI tmp_shift; + SI tmp_tmp; + QI tmp_cc; + tmp_shift = ANDSI (GET_H_GR (FLD (f_GRj)), 31); + tmp_cc = frvbf_set_icc_for_shift_right (current_cpu, GET_H_GR (FLD (f_GRi)), tmp_shift, CPU (h_iccr[((FLD (f_CCi)) & (3))])); + tmp_tmp = SRASI (GET_H_GR (FLD (f_GRi)), tmp_shift); + { + SI opval = tmp_tmp; + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +if (EQSI (tmp_tmp, 0)) { + tmp_cc = ORQI (ANDQI (tmp_cc, 7), 4); +} else { +if (LTSI (tmp_tmp, 0)) { + tmp_cc = ORQI (ANDQI (tmp_cc, 11), 8); +} else { + tmp_cc = ANDQI (tmp_cc, 3); +} +} + { + UQI opval = tmp_cc; + sim_queue_qi_write (current_cpu, & CPU (h_iccr[((FLD (f_CCi)) & (3))]), opval); + written |= (1 << 7); + TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* addx: addx$pack $GRi,$GRj,$GRk,$ICCi_1 */ + +static SEM_PC +SEM_FN_NAME (frvbf,addx) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = ADDCSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)), TRUNCQIBI (ANDQI (CPU (h_iccr[FLD (f_ICCi_1)]), 1))); + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* subx: subx$pack $GRi,$GRj,$GRk,$ICCi_1 */ + +static SEM_PC +SEM_FN_NAME (frvbf,subx) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = SUBCSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)), TRUNCQIBI (ANDQI (CPU (h_iccr[FLD (f_ICCi_1)]), 1))); + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* addxcc: addxcc$pack $GRi,$GRj,$GRk,$ICCi_1 */ + +static SEM_PC +SEM_FN_NAME (frvbf,addxcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + SI tmp_tmp; + QI tmp_cc; + tmp_cc = CPU (h_iccr[FLD (f_ICCi_1)]); + tmp_tmp = ADDCSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)), TRUNCQIBI (ANDQI (tmp_cc, 1))); +if (EQSI (ADDOFSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)), TRUNCQIBI (ANDQI (tmp_cc, 1))), 0)) { + tmp_cc = ANDQI (tmp_cc, 13); +} else { + tmp_cc = ORQI (tmp_cc, 2); +} +if (EQSI (ADDCFSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)), TRUNCQIBI (ANDQI (tmp_cc, 1))), 0)) { + tmp_cc = ANDQI (tmp_cc, 14); +} else { + tmp_cc = ORQI (tmp_cc, 1); +} +if (EQSI (tmp_tmp, 0)) { + tmp_cc = ORQI (ANDQI (tmp_cc, 7), 4); +} else { +if (LTSI (tmp_tmp, 0)) { + tmp_cc = ORQI (ANDQI (tmp_cc, 11), 8); +} else { + tmp_cc = ANDQI (tmp_cc, 3); +} +} + { + SI opval = tmp_tmp; + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + { + UQI opval = tmp_cc; + sim_queue_qi_write (current_cpu, & CPU (h_iccr[FLD (f_ICCi_1)]), opval); + TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval); + } +} + + return vpc; +#undef FLD +} + +/* subxcc: subxcc$pack $GRi,$GRj,$GRk,$ICCi_1 */ + +static SEM_PC +SEM_FN_NAME (frvbf,subxcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + SI tmp_tmp; + QI tmp_cc; + tmp_cc = CPU (h_iccr[FLD (f_ICCi_1)]); + tmp_tmp = SUBCSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)), TRUNCQIBI (ANDQI (tmp_cc, 1))); +if (EQSI (SUBOFSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)), TRUNCQIBI (ANDQI (tmp_cc, 1))), 0)) { + tmp_cc = ANDQI (tmp_cc, 13); +} else { + tmp_cc = ORQI (tmp_cc, 2); +} +if (EQSI (SUBCFSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)), TRUNCQIBI (ANDQI (tmp_cc, 1))), 0)) { + tmp_cc = ANDQI (tmp_cc, 14); +} else { + tmp_cc = ORQI (tmp_cc, 1); +} +if (EQSI (tmp_tmp, 0)) { + tmp_cc = ORQI (ANDQI (tmp_cc, 7), 4); +} else { +if (LTSI (tmp_tmp, 0)) { + tmp_cc = ORQI (ANDQI (tmp_cc, 11), 8); +} else { + tmp_cc = ANDQI (tmp_cc, 3); +} +} + { + SI opval = tmp_tmp; + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + { + UQI opval = tmp_cc; + sim_queue_qi_write (current_cpu, & CPU (h_iccr[FLD (f_ICCi_1)]), opval); + TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval); + } +} + + return vpc; +#undef FLD +} + +/* addss: addss$pack $GRi,$GRj,$GRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,addss) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + { + SI opval = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +if (ADDOFSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)), 0)) { + { + SI opval = (GTSI (GET_H_GR (FLD (f_GRi)), 0)) ? (2147483647) : (LTSI (GET_H_GR (FLD (f_GRi)), 0)) ? (0x80000000) : (0); + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} +} + + return vpc; +#undef FLD +} + +/* subss: subss$pack $GRi,$GRj,$GRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,subss) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + { + SI opval = SUBSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +if (SUBOFSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)), 0)) { + { + SI opval = (GTSI (GET_H_GR (FLD (f_GRi)), 0)) ? (2147483647) : (LTSI (GET_H_GR (FLD (f_GRi)), 0)) ? (0x80000000) : (0); + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} +} + + return vpc; +#undef FLD +} + +/* addi: addi$pack $GRi,$s12,$GRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,addi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = ADDSI (GET_H_GR (FLD (f_GRi)), FLD (f_d12)); + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* subi: subi$pack $GRi,$s12,$GRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,subi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = SUBSI (GET_H_GR (FLD (f_GRi)), FLD (f_d12)); + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* andi: andi$pack $GRi,$s12,$GRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,andi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = ANDSI (GET_H_GR (FLD (f_GRi)), FLD (f_d12)); + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* ori: ori$pack $GRi,$s12,$GRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,ori) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = ORSI (GET_H_GR (FLD (f_GRi)), FLD (f_d12)); + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* xori: xori$pack $GRi,$s12,$GRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,xori) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = XORSI (GET_H_GR (FLD (f_GRi)), FLD (f_d12)); + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* sdivi: sdivi$pack $GRi,$s12,$GRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,sdivi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_signed_integer_divide (current_cpu, GET_H_GR (FLD (f_GRi)), FLD (f_d12), FLD (f_GRk), 0); +; /*clobber*/ +} + + return vpc; +#undef FLD +} + +/* nsdivi: nsdivi$pack $GRi,$s12,$GRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,nsdivi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_signed_integer_divide (current_cpu, GET_H_GR (FLD (f_GRi)), FLD (f_d12), FLD (f_GRk), 1); +; /*clobber*/ +} + + return vpc; +#undef FLD +} + +/* udivi: udivi$pack $GRi,$s12,$GRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,udivi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_unsigned_integer_divide (current_cpu, GET_H_GR (FLD (f_GRi)), FLD (f_d12), FLD (f_GRk), 0); +; /*clobber*/ +} + + return vpc; +#undef FLD +} + +/* nudivi: nudivi$pack $GRi,$s12,$GRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,nudivi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_unsigned_integer_divide (current_cpu, GET_H_GR (FLD (f_GRi)), FLD (f_d12), FLD (f_GRk), 1); +; /*clobber*/ +} + + return vpc; +#undef FLD +} + +/* smuli: smuli$pack $GRi,$s12,$GRdoublek */ + +static SEM_PC +SEM_FN_NAME (frvbf,smuli) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smuli.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + DI opval = MULDI (EXTSIDI (GET_H_GR (FLD (f_GRi))), EXTSIDI (FLD (f_d12))); + sim_queue_fn_di_write (current_cpu, frvbf_h_gr_double_set, FLD (f_GRk), opval); + TRACE_RESULT (current_cpu, abuf, "gr_double", 'D', opval); + } + + return vpc; +#undef FLD +} + +/* umuli: umuli$pack $GRi,$s12,$GRdoublek */ + +static SEM_PC +SEM_FN_NAME (frvbf,umuli) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smuli.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + DI opval = MULDI (ZEXTSIDI (GET_H_GR (FLD (f_GRi))), ZEXTSIDI (FLD (f_d12))); + sim_queue_fn_di_write (current_cpu, frvbf_h_gr_double_set, FLD (f_GRk), opval); + TRACE_RESULT (current_cpu, abuf, "gr_double", 'D', opval); + } + + return vpc; +#undef FLD +} + +/* slli: slli$pack $GRi,$s12,$GRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,slli) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = SLLSI (GET_H_GR (FLD (f_GRi)), ANDSI (FLD (f_d12), 31)); + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* srli: srli$pack $GRi,$s12,$GRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,srli) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = SRLSI (GET_H_GR (FLD (f_GRi)), ANDSI (FLD (f_d12), 31)); + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* srai: srai$pack $GRi,$s12,$GRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,srai) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = SRASI (GET_H_GR (FLD (f_GRi)), ANDSI (FLD (f_d12), 31)); + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* scani: scani$pack $GRi,$s12,$GRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,scani) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + SI tmp_tmp1; + SI tmp_tmp2; + tmp_tmp1 = GET_H_GR (FLD (f_GRi)); + tmp_tmp2 = SRASI (FLD (f_d12), 1); + { + SI opval = frvbf_scan_result (current_cpu, XORSI (tmp_tmp1, tmp_tmp2)); + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} + + return vpc; +#undef FLD +} + +/* addicc: addicc$pack $GRi,$s10,$GRk,$ICCi_1 */ + +static SEM_PC +SEM_FN_NAME (frvbf,addicc) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + BI tmp_tmp; + QI tmp_cc; + SI tmp_result; + tmp_cc = CPU (h_iccr[FLD (f_ICCi_1)]); + tmp_tmp = ADDOFSI (GET_H_GR (FLD (f_GRi)), FLD (f_s10), 0); +if (EQBI (tmp_tmp, 0)) { + tmp_cc = ANDQI (tmp_cc, 13); +} else { + tmp_cc = ORQI (tmp_cc, 2); +} + tmp_tmp = ADDCFSI (GET_H_GR (FLD (f_GRi)), FLD (f_s10), 0); +if (EQBI (tmp_tmp, 0)) { + tmp_cc = ANDQI (tmp_cc, 14); +} else { + tmp_cc = ORQI (tmp_cc, 1); +} + tmp_result = ADDSI (GET_H_GR (FLD (f_GRi)), FLD (f_s10)); +if (EQSI (tmp_result, 0)) { + tmp_cc = ORQI (ANDQI (tmp_cc, 7), 4); +} else { +if (LTSI (tmp_result, 0)) { + tmp_cc = ORQI (ANDQI (tmp_cc, 11), 8); +} else { + tmp_cc = ANDQI (tmp_cc, 3); +} +} + { + SI opval = tmp_result; + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + { + UQI opval = tmp_cc; + sim_queue_qi_write (current_cpu, & CPU (h_iccr[FLD (f_ICCi_1)]), opval); + TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval); + } +} + + return vpc; +#undef FLD +} + +/* subicc: subicc$pack $GRi,$s10,$GRk,$ICCi_1 */ + +static SEM_PC +SEM_FN_NAME (frvbf,subicc) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + BI tmp_tmp; + QI tmp_cc; + SI tmp_result; + tmp_cc = CPU (h_iccr[FLD (f_ICCi_1)]); + tmp_tmp = SUBOFSI (GET_H_GR (FLD (f_GRi)), FLD (f_s10), 0); +if (EQBI (tmp_tmp, 0)) { + tmp_cc = ANDQI (tmp_cc, 13); +} else { + tmp_cc = ORQI (tmp_cc, 2); +} + tmp_tmp = SUBCFSI (GET_H_GR (FLD (f_GRi)), FLD (f_s10), 0); +if (EQBI (tmp_tmp, 0)) { + tmp_cc = ANDQI (tmp_cc, 14); +} else { + tmp_cc = ORQI (tmp_cc, 1); +} + tmp_result = SUBSI (GET_H_GR (FLD (f_GRi)), FLD (f_s10)); +if (EQSI (tmp_result, 0)) { + tmp_cc = ORQI (ANDQI (tmp_cc, 7), 4); +} else { +if (LTSI (tmp_result, 0)) { + tmp_cc = ORQI (ANDQI (tmp_cc, 11), 8); +} else { + tmp_cc = ANDQI (tmp_cc, 3); +} +} + { + SI opval = tmp_result; + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + { + UQI opval = tmp_cc; + sim_queue_qi_write (current_cpu, & CPU (h_iccr[FLD (f_ICCi_1)]), opval); + TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval); + } +} + + return vpc; +#undef FLD +} + +/* andicc: andicc$pack $GRi,$s10,$GRk,$ICCi_1 */ + +static SEM_PC +SEM_FN_NAME (frvbf,andicc) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + SI tmp_tmp; + tmp_tmp = ANDSI (GET_H_GR (FLD (f_GRi)), FLD (f_s10)); + { + SI opval = tmp_tmp; + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +if (EQSI (tmp_tmp, 0)) { + { + UQI opval = ORQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_1)]), 7), 4); + sim_queue_qi_write (current_cpu, & CPU (h_iccr[FLD (f_ICCi_1)]), opval); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval); + } +} else { +if (LTSI (tmp_tmp, 0)) { + { + UQI opval = ORQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_1)]), 11), 8); + sim_queue_qi_write (current_cpu, & CPU (h_iccr[FLD (f_ICCi_1)]), opval); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval); + } +} else { + { + UQI opval = ANDQI (CPU (h_iccr[FLD (f_ICCi_1)]), 3); + sim_queue_qi_write (current_cpu, & CPU (h_iccr[FLD (f_ICCi_1)]), opval); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval); + } +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* oricc: oricc$pack $GRi,$s10,$GRk,$ICCi_1 */ + +static SEM_PC +SEM_FN_NAME (frvbf,oricc) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + SI tmp_tmp; + tmp_tmp = ORSI (GET_H_GR (FLD (f_GRi)), FLD (f_s10)); + { + SI opval = tmp_tmp; + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +if (EQSI (tmp_tmp, 0)) { + { + UQI opval = ORQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_1)]), 7), 4); + sim_queue_qi_write (current_cpu, & CPU (h_iccr[FLD (f_ICCi_1)]), opval); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval); + } +} else { +if (LTSI (tmp_tmp, 0)) { + { + UQI opval = ORQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_1)]), 11), 8); + sim_queue_qi_write (current_cpu, & CPU (h_iccr[FLD (f_ICCi_1)]), opval); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval); + } +} else { + { + UQI opval = ANDQI (CPU (h_iccr[FLD (f_ICCi_1)]), 3); + sim_queue_qi_write (current_cpu, & CPU (h_iccr[FLD (f_ICCi_1)]), opval); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval); + } +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* xoricc: xoricc$pack $GRi,$s10,$GRk,$ICCi_1 */ + +static SEM_PC +SEM_FN_NAME (frvbf,xoricc) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + SI tmp_tmp; + tmp_tmp = XORSI (GET_H_GR (FLD (f_GRi)), FLD (f_s10)); + { + SI opval = tmp_tmp; + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +if (EQSI (tmp_tmp, 0)) { + { + UQI opval = ORQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_1)]), 7), 4); + sim_queue_qi_write (current_cpu, & CPU (h_iccr[FLD (f_ICCi_1)]), opval); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval); + } +} else { +if (LTSI (tmp_tmp, 0)) { + { + UQI opval = ORQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_1)]), 11), 8); + sim_queue_qi_write (current_cpu, & CPU (h_iccr[FLD (f_ICCi_1)]), opval); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval); + } +} else { + { + UQI opval = ANDQI (CPU (h_iccr[FLD (f_ICCi_1)]), 3); + sim_queue_qi_write (current_cpu, & CPU (h_iccr[FLD (f_ICCi_1)]), opval); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval); + } +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* smulicc: smulicc$pack $GRi,$s10,$GRdoublek,$ICCi_1 */ + +static SEM_PC +SEM_FN_NAME (frvbf,smulicc) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulicc.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + DI tmp_tmp; + QI tmp_cc; + tmp_cc = CPU (h_iccr[FLD (f_ICCi_1)]); + tmp_tmp = MULDI (EXTSIDI (GET_H_GR (FLD (f_GRi))), EXTSIDI (FLD (f_s10))); +if (EQDI (SRLDI (tmp_tmp, 63), 0)) { + tmp_cc = ANDQI (tmp_cc, 7); +} else { + tmp_cc = ORQI (tmp_cc, 8); +} +if (EQBI (EQDI (tmp_tmp, 0), 0)) { + tmp_cc = ANDQI (tmp_cc, 11); +} else { + tmp_cc = ORQI (tmp_cc, 4); +} + { + DI opval = tmp_tmp; + sim_queue_fn_di_write (current_cpu, frvbf_h_gr_double_set, FLD (f_GRk), opval); + TRACE_RESULT (current_cpu, abuf, "gr_double", 'D', opval); + } + { + UQI opval = tmp_cc; + sim_queue_qi_write (current_cpu, & CPU (h_iccr[FLD (f_ICCi_1)]), opval); + TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval); + } +} + + return vpc; +#undef FLD +} + +/* umulicc: umulicc$pack $GRi,$s10,$GRdoublek,$ICCi_1 */ + +static SEM_PC +SEM_FN_NAME (frvbf,umulicc) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulicc.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + DI tmp_tmp; + QI tmp_cc; + tmp_cc = CPU (h_iccr[FLD (f_ICCi_1)]); + tmp_tmp = MULDI (ZEXTSIDI (GET_H_GR (FLD (f_GRi))), ZEXTSIDI (FLD (f_s10))); +if (EQDI (SRLDI (tmp_tmp, 63), 0)) { + tmp_cc = ANDQI (tmp_cc, 7); +} else { + tmp_cc = ORQI (tmp_cc, 8); +} +if (EQBI (EQDI (tmp_tmp, 0), 0)) { + tmp_cc = ANDQI (tmp_cc, 11); +} else { + tmp_cc = ORQI (tmp_cc, 4); +} + { + DI opval = tmp_tmp; + sim_queue_fn_di_write (current_cpu, frvbf_h_gr_double_set, FLD (f_GRk), opval); + TRACE_RESULT (current_cpu, abuf, "gr_double", 'D', opval); + } + { + UQI opval = tmp_cc; + sim_queue_qi_write (current_cpu, & CPU (h_iccr[FLD (f_ICCi_1)]), opval); + TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval); + } +} + + return vpc; +#undef FLD +} + +/* sllicc: sllicc$pack $GRi,$s10,$GRk,$ICCi_1 */ + +static SEM_PC +SEM_FN_NAME (frvbf,sllicc) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + SI tmp_shift; + SI tmp_tmp; + QI tmp_cc; + tmp_shift = ANDSI (FLD (f_s10), 31); + tmp_cc = frvbf_set_icc_for_shift_left (current_cpu, GET_H_GR (FLD (f_GRi)), tmp_shift, CPU (h_iccr[FLD (f_ICCi_1)])); + tmp_tmp = SLLSI (GET_H_GR (FLD (f_GRi)), tmp_shift); + { + SI opval = tmp_tmp; + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +if (EQSI (tmp_tmp, 0)) { + tmp_cc = ORQI (ANDQI (tmp_cc, 7), 4); +} else { +if (LTSI (tmp_tmp, 0)) { + tmp_cc = ORQI (ANDQI (tmp_cc, 11), 8); +} else { + tmp_cc = ANDQI (tmp_cc, 3); +} +} + { + UQI opval = tmp_cc; + sim_queue_qi_write (current_cpu, & CPU (h_iccr[FLD (f_ICCi_1)]), opval); + TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval); + } +} + + return vpc; +#undef FLD +} + +/* srlicc: srlicc$pack $GRi,$s10,$GRk,$ICCi_1 */ + +static SEM_PC +SEM_FN_NAME (frvbf,srlicc) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + SI tmp_shift; + SI tmp_tmp; + QI tmp_cc; + tmp_shift = ANDSI (FLD (f_s10), 31); + tmp_cc = frvbf_set_icc_for_shift_right (current_cpu, GET_H_GR (FLD (f_GRi)), tmp_shift, CPU (h_iccr[FLD (f_ICCi_1)])); + tmp_tmp = SRLSI (GET_H_GR (FLD (f_GRi)), tmp_shift); + { + SI opval = tmp_tmp; + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +if (EQSI (tmp_tmp, 0)) { + tmp_cc = ORQI (ANDQI (tmp_cc, 7), 4); +} else { +if (LTSI (tmp_tmp, 0)) { + tmp_cc = ORQI (ANDQI (tmp_cc, 11), 8); +} else { + tmp_cc = ANDQI (tmp_cc, 3); +} +} + { + UQI opval = tmp_cc; + sim_queue_qi_write (current_cpu, & CPU (h_iccr[FLD (f_ICCi_1)]), opval); + TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval); + } +} + + return vpc; +#undef FLD +} + +/* sraicc: sraicc$pack $GRi,$s10,$GRk,$ICCi_1 */ + +static SEM_PC +SEM_FN_NAME (frvbf,sraicc) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + SI tmp_shift; + SI tmp_tmp; + QI tmp_cc; + tmp_shift = ANDSI (FLD (f_s10), 31); + tmp_cc = frvbf_set_icc_for_shift_right (current_cpu, GET_H_GR (FLD (f_GRi)), tmp_shift, CPU (h_iccr[FLD (f_ICCi_1)])); + tmp_tmp = SRASI (GET_H_GR (FLD (f_GRi)), tmp_shift); + { + SI opval = tmp_tmp; + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +if (EQSI (tmp_tmp, 0)) { + tmp_cc = ORQI (ANDQI (tmp_cc, 7), 4); +} else { +if (LTSI (tmp_tmp, 0)) { + tmp_cc = ORQI (ANDQI (tmp_cc, 11), 8); +} else { + tmp_cc = ANDQI (tmp_cc, 3); +} +} + { + UQI opval = tmp_cc; + sim_queue_qi_write (current_cpu, & CPU (h_iccr[FLD (f_ICCi_1)]), opval); + TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval); + } +} + + return vpc; +#undef FLD +} + +/* addxi: addxi$pack $GRi,$s10,$GRk,$ICCi_1 */ + +static SEM_PC +SEM_FN_NAME (frvbf,addxi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = ADDCSI (GET_H_GR (FLD (f_GRi)), FLD (f_s10), TRUNCQIBI (ANDQI (CPU (h_iccr[FLD (f_ICCi_1)]), 1))); + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* subxi: subxi$pack $GRi,$s10,$GRk,$ICCi_1 */ + +static SEM_PC +SEM_FN_NAME (frvbf,subxi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = SUBCSI (GET_H_GR (FLD (f_GRi)), FLD (f_s10), TRUNCQIBI (ANDQI (CPU (h_iccr[FLD (f_ICCi_1)]), 1))); + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* addxicc: addxicc$pack $GRi,$s10,$GRk,$ICCi_1 */ + +static SEM_PC +SEM_FN_NAME (frvbf,addxicc) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + SI tmp_tmp; + QI tmp_cc; + tmp_cc = CPU (h_iccr[FLD (f_ICCi_1)]); + tmp_tmp = ADDCSI (GET_H_GR (FLD (f_GRi)), FLD (f_s10), TRUNCQIBI (ANDQI (tmp_cc, 1))); +if (EQSI (ADDOFSI (GET_H_GR (FLD (f_GRi)), FLD (f_s10), TRUNCQIBI (ANDQI (tmp_cc, 1))), 0)) { + tmp_cc = ANDQI (tmp_cc, 13); +} else { + tmp_cc = ORQI (tmp_cc, 2); +} +if (EQSI (ADDCFSI (GET_H_GR (FLD (f_GRi)), FLD (f_s10), TRUNCQIBI (ANDQI (tmp_cc, 1))), 0)) { + tmp_cc = ANDQI (tmp_cc, 14); +} else { + tmp_cc = ORQI (tmp_cc, 1); +} +if (EQSI (tmp_tmp, 0)) { + tmp_cc = ORQI (ANDQI (tmp_cc, 7), 4); +} else { +if (LTSI (tmp_tmp, 0)) { + tmp_cc = ORQI (ANDQI (tmp_cc, 11), 8); +} else { + tmp_cc = ANDQI (tmp_cc, 3); +} +} + { + SI opval = tmp_tmp; + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + { + UQI opval = tmp_cc; + sim_queue_qi_write (current_cpu, & CPU (h_iccr[FLD (f_ICCi_1)]), opval); + TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval); + } +} + + return vpc; +#undef FLD +} + +/* subxicc: subxicc$pack $GRi,$s10,$GRk,$ICCi_1 */ + +static SEM_PC +SEM_FN_NAME (frvbf,subxicc) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + SI tmp_tmp; + QI tmp_cc; + tmp_cc = CPU (h_iccr[FLD (f_ICCi_1)]); + tmp_tmp = SUBCSI (GET_H_GR (FLD (f_GRi)), FLD (f_s10), TRUNCQIBI (ANDQI (tmp_cc, 1))); +if (EQSI (SUBOFSI (GET_H_GR (FLD (f_GRi)), FLD (f_s10), TRUNCQIBI (ANDQI (tmp_cc, 1))), 0)) { + tmp_cc = ANDQI (tmp_cc, 13); +} else { + tmp_cc = ORQI (tmp_cc, 2); +} +if (EQSI (SUBCFSI (GET_H_GR (FLD (f_GRi)), FLD (f_s10), TRUNCQIBI (ANDQI (tmp_cc, 1))), 0)) { + tmp_cc = ANDQI (tmp_cc, 14); +} else { + tmp_cc = ORQI (tmp_cc, 1); +} +if (EQSI (tmp_tmp, 0)) { + tmp_cc = ORQI (ANDQI (tmp_cc, 7), 4); +} else { +if (LTSI (tmp_tmp, 0)) { + tmp_cc = ORQI (ANDQI (tmp_cc, 11), 8); +} else { + tmp_cc = ANDQI (tmp_cc, 3); +} +} + { + SI opval = tmp_tmp; + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + { + UQI opval = tmp_cc; + sim_queue_qi_write (current_cpu, & CPU (h_iccr[FLD (f_ICCi_1)]), opval); + TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval); + } +} + + return vpc; +#undef FLD +} + +/* cmpb: cmpb$pack $GRi,$GRj,$ICCi_1 */ + +static SEM_PC +SEM_FN_NAME (frvbf,cmpb) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + QI tmp_cc; +if (EQBI (EQSI (ANDSI (GET_H_GR (FLD (f_GRi)), 0xff000000), ANDSI (GET_H_GR (FLD (f_GRj)), 0xff000000)), 0)) { + tmp_cc = ANDQI (tmp_cc, 7); +} else { + tmp_cc = ORQI (tmp_cc, 8); +} +if (EQBI (EQSI (ANDSI (GET_H_GR (FLD (f_GRi)), 16711680), ANDSI (GET_H_GR (FLD (f_GRj)), 16711680)), 0)) { + tmp_cc = ANDQI (tmp_cc, 11); +} else { + tmp_cc = ORQI (tmp_cc, 4); +} +if (EQBI (EQSI (ANDSI (GET_H_GR (FLD (f_GRi)), 65280), ANDSI (GET_H_GR (FLD (f_GRj)), 65280)), 0)) { + tmp_cc = ANDQI (tmp_cc, 13); +} else { + tmp_cc = ORQI (tmp_cc, 2); +} +if (EQBI (EQSI (ANDSI (GET_H_GR (FLD (f_GRi)), 255), ANDSI (GET_H_GR (FLD (f_GRj)), 255)), 0)) { + tmp_cc = ANDQI (tmp_cc, 14); +} else { + tmp_cc = ORQI (tmp_cc, 1); +} + { + UQI opval = tmp_cc; + sim_queue_qi_write (current_cpu, & CPU (h_iccr[FLD (f_ICCi_1)]), opval); + TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval); + } +} + + return vpc; +#undef FLD +} + +/* cmpba: cmpba$pack $GRi,$GRj,$ICCi_1 */ + +static SEM_PC +SEM_FN_NAME (frvbf,cmpba) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + QI tmp_cc; + tmp_cc = 0; +if (EQBI (ORIF (EQSI (ANDSI (GET_H_GR (FLD (f_GRi)), 0xff000000), ANDSI (GET_H_GR (FLD (f_GRj)), 0xff000000)), ORIF (EQSI (ANDSI (GET_H_GR (FLD (f_GRi)), 16711680), ANDSI (GET_H_GR (FLD (f_GRj)), 16711680)), ORIF (EQSI (ANDSI (GET_H_GR (FLD (f_GRi)), 65280), ANDSI (GET_H_GR (FLD (f_GRj)), 65280)), EQSI (ANDSI (GET_H_GR (FLD (f_GRi)), 255), ANDSI (GET_H_GR (FLD (f_GRj)), 255))))), 0)) { + tmp_cc = ANDQI (tmp_cc, 14); +} else { + tmp_cc = ORQI (tmp_cc, 1); +} + { + UQI opval = tmp_cc; + sim_queue_qi_write (current_cpu, & CPU (h_iccr[FLD (f_ICCi_1)]), opval); + TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval); + } +} + + return vpc; +#undef FLD +} + +/* setlo: setlo$pack $ulo16,$GRklo */ + +static SEM_PC +SEM_FN_NAME (frvbf,setlo) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_setlo.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + UHI opval = FLD (f_u16); + sim_queue_fn_hi_write (current_cpu, frvbf_h_gr_lo_set, FLD (f_GRk), opval); + TRACE_RESULT (current_cpu, abuf, "gr_lo", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* sethi: sethi$pack $uhi16,$GRkhi */ + +static SEM_PC +SEM_FN_NAME (frvbf,sethi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_sethi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + UHI opval = FLD (f_u16); + sim_queue_fn_hi_write (current_cpu, frvbf_h_gr_hi_set, FLD (f_GRk), opval); + TRACE_RESULT (current_cpu, abuf, "gr_hi", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* setlos: setlos$pack $slo16,$GRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,setlos) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_setlos.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = FLD (f_s16); + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* ldsb: ldsb$pack @($GRi,$GRj),$GRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,ldsb) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = frvbf_read_mem_QI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)))); + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* ldub: ldub$pack @($GRi,$GRj),$GRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,ldub) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = frvbf_read_mem_UQI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)))); + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* ldsh: ldsh$pack @($GRi,$GRj),$GRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,ldsh) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = frvbf_read_mem_HI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)))); + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* lduh: lduh$pack @($GRi,$GRj),$GRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,lduh) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = frvbf_read_mem_UHI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)))); + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* ld: ld$pack @($GRi,$GRj),$GRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,ld) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = frvbf_read_mem_SI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)))); + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* ldbf: ldbf$pack @($GRi,$GRj),$FRintk */ + +static SEM_PC +SEM_FN_NAME (frvbf,ldbf) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = frvbf_read_mem_UQI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)))); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* ldhf: ldhf$pack @($GRi,$GRj),$FRintk */ + +static SEM_PC +SEM_FN_NAME (frvbf,ldhf) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = frvbf_read_mem_UHI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)))); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* ldf: ldf$pack @($GRi,$GRj),$FRintk */ + +static SEM_PC +SEM_FN_NAME (frvbf,ldf) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = frvbf_read_mem_SI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)))); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* ldc: ldc$pack @($GRi,$GRj),$CPRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,ldc) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldcu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = frvbf_read_mem_SI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)))); + sim_queue_si_write (current_cpu, & CPU (h_cpr[FLD (f_CPRk)]), opval); + TRACE_RESULT (current_cpu, abuf, "cpr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* nldsb: nldsb$pack @($GRi,$GRj),$GRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,nldsb) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + BI tmp_do_op; + tmp_do_op = frvbf_check_non_excepting_load (current_cpu, FLD (f_GRi), FLD (f_GRj), FLD (f_GRk), 0, 1, 0); +if (tmp_do_op) { + { + SI opval = frvbf_read_mem_QI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)))); + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* nldub: nldub$pack @($GRi,$GRj),$GRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,nldub) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + BI tmp_do_op; + tmp_do_op = frvbf_check_non_excepting_load (current_cpu, FLD (f_GRi), FLD (f_GRj), FLD (f_GRk), 0, 0, 0); +if (tmp_do_op) { + { + SI opval = frvbf_read_mem_UQI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)))); + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* nldsh: nldsh$pack @($GRi,$GRj),$GRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,nldsh) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + BI tmp_do_op; + tmp_do_op = frvbf_check_non_excepting_load (current_cpu, FLD (f_GRi), FLD (f_GRj), FLD (f_GRk), 0, 3, 0); +if (tmp_do_op) { + { + SI opval = frvbf_read_mem_HI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)))); + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* nlduh: nlduh$pack @($GRi,$GRj),$GRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,nlduh) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + BI tmp_do_op; + tmp_do_op = frvbf_check_non_excepting_load (current_cpu, FLD (f_GRi), FLD (f_GRj), FLD (f_GRk), 0, 2, 0); +if (tmp_do_op) { + { + SI opval = frvbf_read_mem_UHI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)))); + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* nld: nld$pack @($GRi,$GRj),$GRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,nld) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + BI tmp_do_op; + tmp_do_op = frvbf_check_non_excepting_load (current_cpu, FLD (f_GRi), FLD (f_GRj), FLD (f_GRk), 0, 4, 0); +if (tmp_do_op) { + { + SI opval = frvbf_read_mem_SI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)))); + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* nldbf: nldbf$pack @($GRi,$GRj),$FRintk */ + +static SEM_PC +SEM_FN_NAME (frvbf,nldbf) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + BI tmp_do_op; + tmp_do_op = frvbf_check_non_excepting_load (current_cpu, FLD (f_GRi), FLD (f_GRj), FLD (f_FRk), 0, 0, 1); +if (tmp_do_op) { + { + SI opval = frvbf_read_mem_UQI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)))); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* nldhf: nldhf$pack @($GRi,$GRj),$FRintk */ + +static SEM_PC +SEM_FN_NAME (frvbf,nldhf) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + BI tmp_do_op; + tmp_do_op = frvbf_check_non_excepting_load (current_cpu, FLD (f_GRi), FLD (f_GRj), FLD (f_FRk), 0, 2, 1); +if (tmp_do_op) { + { + SI opval = frvbf_read_mem_UHI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)))); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* nldf: nldf$pack @($GRi,$GRj),$FRintk */ + +static SEM_PC +SEM_FN_NAME (frvbf,nldf) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + BI tmp_do_op; + tmp_do_op = frvbf_check_non_excepting_load (current_cpu, FLD (f_GRi), FLD (f_GRj), FLD (f_FRk), 0, 4, 1); +if (tmp_do_op) { + { + SI opval = frvbf_read_mem_SI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)))); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* ldd: ldd$pack @($GRi,$GRj),$GRdoublek */ + +static SEM_PC +SEM_FN_NAME (frvbf,ldd) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + SI tmp_address; +if (NESI (FLD (f_GRk), 0)) { +{ + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); + { + DI opval = frvbf_read_mem_DI (current_cpu, pc, tmp_address); + sim_queue_fn_di_write (current_cpu, frvbf_h_gr_double_set, FLD (f_GRk), opval); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "gr_double", 'D', opval); + } +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* lddf: lddf$pack @($GRi,$GRj),$FRdoublek */ + +static SEM_PC +SEM_FN_NAME (frvbf,lddf) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddfu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + SI tmp_address; +{ + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); + { + DF opval = frvbf_read_mem_DF (current_cpu, pc, tmp_address); + sim_queue_fn_df_write (current_cpu, frvbf_h_fr_double_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr_double", 'f', opval); + } +} +} + + return vpc; +#undef FLD +} + +/* lddc: lddc$pack @($GRi,$GRj),$CPRdoublek */ + +static SEM_PC +SEM_FN_NAME (frvbf,lddc) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_lddcu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + SI tmp_address; +{ + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); + { + DI opval = frvbf_read_mem_DI (current_cpu, pc, tmp_address); + sim_queue_fn_di_write (current_cpu, frvbf_h_cpr_double_set, FLD (f_CPRk), opval); + TRACE_RESULT (current_cpu, abuf, "cpr_double", 'D', opval); + } +} +} + + return vpc; +#undef FLD +} + +/* nldd: nldd$pack @($GRi,$GRj),$GRdoublek */ + +static SEM_PC +SEM_FN_NAME (frvbf,nldd) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + SI tmp_address; +{ + BI tmp_do_op; + tmp_do_op = frvbf_check_non_excepting_load (current_cpu, FLD (f_GRi), FLD (f_GRj), FLD (f_GRk), 0, 5, 0); +if (tmp_do_op) { +if (NESI (FLD (f_GRk), 0)) { +{ + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); + { + DI opval = frvbf_read_mem_DI (current_cpu, pc, tmp_address); + sim_queue_fn_di_write (current_cpu, frvbf_h_gr_double_set, FLD (f_GRk), opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "gr_double", 'D', opval); + } +} +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* nlddf: nlddf$pack @($GRi,$GRj),$FRdoublek */ + +static SEM_PC +SEM_FN_NAME (frvbf,nlddf) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddfu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + SI tmp_address; +{ + BI tmp_do_op; + tmp_do_op = frvbf_check_non_excepting_load (current_cpu, FLD (f_GRi), FLD (f_GRj), FLD (f_FRk), 0, 5, 1); +if (tmp_do_op) { +{ + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); + { + DF opval = frvbf_read_mem_DF (current_cpu, pc, tmp_address); + sim_queue_fn_df_write (current_cpu, frvbf_h_fr_double_set, FLD (f_FRk), opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "fr_double", 'f', opval); + } +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* ldq: ldq$pack @($GRi,$GRj),$GRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,ldq) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + SI tmp_address; +{ + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); +frvbf_load_quad_GR (current_cpu, pc, tmp_address, FLD (f_GRk)); +} +} + + return vpc; +#undef FLD +} + +/* ldqf: ldqf$pack @($GRi,$GRj),$FRintk */ + +static SEM_PC +SEM_FN_NAME (frvbf,ldqf) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + SI tmp_address; +{ + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); +frvbf_load_quad_FRint (current_cpu, pc, tmp_address, FLD (f_FRk)); +} +} + + return vpc; +#undef FLD +} + +/* ldqc: ldqc$pack @($GRi,$GRj),$CPRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,ldqc) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdcu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + SI tmp_address; +{ + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); +frvbf_load_quad_CPR (current_cpu, pc, tmp_address, FLD (f_CPRk)); +} +} + + return vpc; +#undef FLD +} + +/* nldq: nldq$pack @($GRi,$GRj),$GRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,nldq) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + SI tmp_address; +{ + BI tmp_do_op; + tmp_do_op = frvbf_check_non_excepting_load (current_cpu, FLD (f_GRi), FLD (f_GRj), FLD (f_GRk), 0, 6, 0); +if (tmp_do_op) { +{ + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); +frvbf_load_quad_GR (current_cpu, pc, tmp_address, FLD (f_GRk)); +} +} +} +} + + return vpc; +#undef FLD +} + +/* nldqf: nldqf$pack @($GRi,$GRj),$FRintk */ + +static SEM_PC +SEM_FN_NAME (frvbf,nldqf) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + SI tmp_address; +{ + BI tmp_do_op; + tmp_do_op = frvbf_check_non_excepting_load (current_cpu, FLD (f_GRi), FLD (f_GRj), FLD (f_FRk), 0, 6, 1); +if (tmp_do_op) { +{ + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); +frvbf_load_quad_FRint (current_cpu, pc, tmp_address, FLD (f_FRk)); +} +} +} +} + + return vpc; +#undef FLD +} + +/* ldsbu: ldsbu$pack @($GRi,$GRj),$GRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,ldsbu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + USI tmp_address; + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); + { + SI opval = frvbf_read_mem_QI (current_cpu, pc, tmp_address); + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +if (NESI (FLD (f_GRi), FLD (f_GRk))) { +{ + { + SI opval = tmp_address; + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval); + written |= (1 << 5); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +frvbf_force_update (current_cpu); +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* ldubu: ldubu$pack @($GRi,$GRj),$GRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,ldubu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + USI tmp_address; + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); + { + SI opval = frvbf_read_mem_UQI (current_cpu, pc, tmp_address); + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +if (NESI (FLD (f_GRi), FLD (f_GRk))) { +{ + { + SI opval = tmp_address; + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval); + written |= (1 << 5); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +frvbf_force_update (current_cpu); +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* ldshu: ldshu$pack @($GRi,$GRj),$GRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,ldshu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + USI tmp_address; + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); + { + SI opval = frvbf_read_mem_HI (current_cpu, pc, tmp_address); + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +if (NESI (FLD (f_GRi), FLD (f_GRk))) { +{ + { + SI opval = tmp_address; + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval); + written |= (1 << 5); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +frvbf_force_update (current_cpu); +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* lduhu: lduhu$pack @($GRi,$GRj),$GRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,lduhu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + USI tmp_address; + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); + { + SI opval = frvbf_read_mem_UHI (current_cpu, pc, tmp_address); + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +if (NESI (FLD (f_GRi), FLD (f_GRk))) { +{ + { + SI opval = tmp_address; + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval); + written |= (1 << 5); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +frvbf_force_update (current_cpu); +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* ldu: ldu$pack @($GRi,$GRj),$GRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,ldu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + USI tmp_address; + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); + { + SI opval = frvbf_read_mem_SI (current_cpu, pc, tmp_address); + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +if (NESI (FLD (f_GRi), FLD (f_GRk))) { +{ + { + SI opval = tmp_address; + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval); + written |= (1 << 5); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +frvbf_force_update (current_cpu); +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* nldsbu: nldsbu$pack @($GRi,$GRj),$GRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,nldsbu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + BI tmp_do_op; + tmp_do_op = frvbf_check_non_excepting_load (current_cpu, FLD (f_GRi), FLD (f_GRj), FLD (f_GRk), 0, 1, 0); +if (tmp_do_op) { +{ + USI tmp_address; + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); + { + SI opval = frvbf_read_mem_QI (current_cpu, pc, tmp_address); + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + written |= (1 << 7); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +if (NESI (FLD (f_GRi), FLD (f_GRk))) { +{ + { + SI opval = tmp_address; + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +frvbf_force_update (current_cpu); +} +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* nldubu: nldubu$pack @($GRi,$GRj),$GRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,nldubu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + BI tmp_do_op; + tmp_do_op = frvbf_check_non_excepting_load (current_cpu, FLD (f_GRi), FLD (f_GRj), FLD (f_GRk), 0, 0, 0); +if (tmp_do_op) { +{ + USI tmp_address; + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); + { + SI opval = frvbf_read_mem_UQI (current_cpu, pc, tmp_address); + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + written |= (1 << 7); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +if (NESI (FLD (f_GRi), FLD (f_GRk))) { +{ + { + SI opval = tmp_address; + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +frvbf_force_update (current_cpu); +} +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* nldshu: nldshu$pack @($GRi,$GRj),$GRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,nldshu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + BI tmp_do_op; + tmp_do_op = frvbf_check_non_excepting_load (current_cpu, FLD (f_GRi), FLD (f_GRj), FLD (f_GRk), 0, 3, 0); +if (tmp_do_op) { +{ + USI tmp_address; + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); + { + SI opval = frvbf_read_mem_HI (current_cpu, pc, tmp_address); + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + written |= (1 << 7); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +if (NESI (FLD (f_GRi), FLD (f_GRk))) { +{ + { + SI opval = tmp_address; + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +frvbf_force_update (current_cpu); +} +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* nlduhu: nlduhu$pack @($GRi,$GRj),$GRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,nlduhu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + BI tmp_do_op; + tmp_do_op = frvbf_check_non_excepting_load (current_cpu, FLD (f_GRi), FLD (f_GRj), FLD (f_GRk), 0, 2, 0); +if (tmp_do_op) { +{ + USI tmp_address; + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); + { + SI opval = frvbf_read_mem_UHI (current_cpu, pc, tmp_address); + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + written |= (1 << 7); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +if (NESI (FLD (f_GRi), FLD (f_GRk))) { +{ + { + SI opval = tmp_address; + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +frvbf_force_update (current_cpu); +} +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* nldu: nldu$pack @($GRi,$GRj),$GRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,nldu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + BI tmp_do_op; + tmp_do_op = frvbf_check_non_excepting_load (current_cpu, FLD (f_GRi), FLD (f_GRj), FLD (f_GRk), 0, 4, 0); +if (tmp_do_op) { +{ + USI tmp_address; + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); + { + SI opval = frvbf_read_mem_SI (current_cpu, pc, tmp_address); + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + written |= (1 << 7); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +if (NESI (FLD (f_GRi), FLD (f_GRk))) { +{ + { + SI opval = tmp_address; + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +frvbf_force_update (current_cpu); +} +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* ldbfu: ldbfu$pack @($GRi,$GRj),$FRintk */ + +static SEM_PC +SEM_FN_NAME (frvbf,ldbfu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + USI tmp_address; + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); + { + SI opval = frvbf_read_mem_UQI (current_cpu, pc, tmp_address); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } + { + SI opval = tmp_address; + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +frvbf_force_update (current_cpu); +} + + return vpc; +#undef FLD +} + +/* ldhfu: ldhfu$pack @($GRi,$GRj),$FRintk */ + +static SEM_PC +SEM_FN_NAME (frvbf,ldhfu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + USI tmp_address; + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); + { + SI opval = frvbf_read_mem_UHI (current_cpu, pc, tmp_address); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } + { + SI opval = tmp_address; + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +frvbf_force_update (current_cpu); +} + + return vpc; +#undef FLD +} + +/* ldfu: ldfu$pack @($GRi,$GRj),$FRintk */ + +static SEM_PC +SEM_FN_NAME (frvbf,ldfu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + USI tmp_address; + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); + { + SI opval = frvbf_read_mem_SI (current_cpu, pc, tmp_address); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } + { + SI opval = tmp_address; + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +frvbf_force_update (current_cpu); +} + + return vpc; +#undef FLD +} + +/* ldcu: ldcu$pack @($GRi,$GRj),$CPRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,ldcu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldcu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + USI tmp_address; + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); + { + SI opval = frvbf_read_mem_SI (current_cpu, pc, tmp_address); + sim_queue_si_write (current_cpu, & CPU (h_cpr[FLD (f_CPRk)]), opval); + TRACE_RESULT (current_cpu, abuf, "cpr", 'x', opval); + } + { + SI opval = tmp_address; + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +frvbf_force_update (current_cpu); +} + + return vpc; +#undef FLD +} + +/* nldbfu: nldbfu$pack @($GRi,$GRj),$FRintk */ + +static SEM_PC +SEM_FN_NAME (frvbf,nldbfu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + BI tmp_do_op; + tmp_do_op = frvbf_check_non_excepting_load (current_cpu, FLD (f_GRi), FLD (f_GRj), FLD (f_FRk), 0, 0, 1); +if (tmp_do_op) { +{ + USI tmp_address; + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); + { + SI opval = frvbf_read_mem_UQI (current_cpu, pc, tmp_address); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } + { + SI opval = tmp_address; + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval); + written |= (1 << 7); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +frvbf_force_update (current_cpu); +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* nldhfu: nldhfu$pack @($GRi,$GRj),$FRintk */ + +static SEM_PC +SEM_FN_NAME (frvbf,nldhfu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + BI tmp_do_op; + tmp_do_op = frvbf_check_non_excepting_load (current_cpu, FLD (f_GRi), FLD (f_GRj), FLD (f_FRk), 0, 2, 1); +if (tmp_do_op) { +{ + USI tmp_address; + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); + { + SI opval = frvbf_read_mem_UHI (current_cpu, pc, tmp_address); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } + { + SI opval = tmp_address; + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval); + written |= (1 << 7); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +frvbf_force_update (current_cpu); +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* nldfu: nldfu$pack @($GRi,$GRj),$FRintk */ + +static SEM_PC +SEM_FN_NAME (frvbf,nldfu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + BI tmp_do_op; + tmp_do_op = frvbf_check_non_excepting_load (current_cpu, FLD (f_GRi), FLD (f_GRj), FLD (f_FRk), 0, 4, 1); +if (tmp_do_op) { +{ + USI tmp_address; + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); + { + SI opval = frvbf_read_mem_SI (current_cpu, pc, tmp_address); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } + { + SI opval = tmp_address; + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval); + written |= (1 << 7); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +frvbf_force_update (current_cpu); +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* lddu: lddu$pack @($GRi,$GRj),$GRdoublek */ + +static SEM_PC +SEM_FN_NAME (frvbf,lddu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + SI tmp_address; +if (NESI (FLD (f_GRk), 0)) { +{ + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); + { + DI opval = frvbf_read_mem_DI (current_cpu, pc, tmp_address); + sim_queue_fn_di_write (current_cpu, frvbf_h_gr_double_set, FLD (f_GRk), opval); + written |= (1 << 5); + TRACE_RESULT (current_cpu, abuf, "gr_double", 'D', opval); + } +} +} +if (NESI (FLD (f_GRi), FLD (f_GRk))) { +{ + { + SI opval = tmp_address; + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +frvbf_force_update (current_cpu); +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* nlddu: nlddu$pack @($GRi,$GRj),$GRdoublek */ + +static SEM_PC +SEM_FN_NAME (frvbf,nlddu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + BI tmp_do_op; + tmp_do_op = frvbf_check_non_excepting_load (current_cpu, FLD (f_GRi), FLD (f_GRj), FLD (f_GRk), 0, 5, 0); +if (tmp_do_op) { +{ + SI tmp_address; +if (NESI (FLD (f_GRk), 0)) { +{ + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); + { + DI opval = frvbf_read_mem_DI (current_cpu, pc, tmp_address); + sim_queue_fn_di_write (current_cpu, frvbf_h_gr_double_set, FLD (f_GRk), opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "gr_double", 'D', opval); + } +} +} +if (NESI (FLD (f_GRi), FLD (f_GRk))) { +{ + { + SI opval = tmp_address; + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval); + written |= (1 << 7); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +frvbf_force_update (current_cpu); +} +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* lddfu: lddfu$pack @($GRi,$GRj),$FRdoublek */ + +static SEM_PC +SEM_FN_NAME (frvbf,lddfu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddfu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + SI tmp_address; +{ + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); + { + DF opval = frvbf_read_mem_DF (current_cpu, pc, tmp_address); + sim_queue_fn_df_write (current_cpu, frvbf_h_fr_double_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr_double", 'f', opval); + } +} + { + SI opval = tmp_address; + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +frvbf_force_update (current_cpu); +} + + return vpc; +#undef FLD +} + +/* lddcu: lddcu$pack @($GRi,$GRj),$CPRdoublek */ + +static SEM_PC +SEM_FN_NAME (frvbf,lddcu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_lddcu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + SI tmp_address; +{ + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); + { + DI opval = frvbf_read_mem_DI (current_cpu, pc, tmp_address); + sim_queue_fn_di_write (current_cpu, frvbf_h_cpr_double_set, FLD (f_CPRk), opval); + TRACE_RESULT (current_cpu, abuf, "cpr_double", 'D', opval); + } +} + { + SI opval = tmp_address; + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +frvbf_force_update (current_cpu); +} + + return vpc; +#undef FLD +} + +/* nlddfu: nlddfu$pack @($GRi,$GRj),$FRdoublek */ + +static SEM_PC +SEM_FN_NAME (frvbf,nlddfu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddfu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + BI tmp_do_op; + tmp_do_op = frvbf_check_non_excepting_load (current_cpu, FLD (f_GRi), FLD (f_GRj), FLD (f_FRk), 0, 5, 1); +if (tmp_do_op) { +{ + SI tmp_address; +{ + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); + { + DF opval = frvbf_read_mem_DF (current_cpu, pc, tmp_address); + sim_queue_fn_df_write (current_cpu, frvbf_h_fr_double_set, FLD (f_FRk), opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "fr_double", 'f', opval); + } +} + { + SI opval = tmp_address; + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval); + written |= (1 << 7); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +frvbf_force_update (current_cpu); +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* ldqu: ldqu$pack @($GRi,$GRj),$GRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,ldqu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + SI tmp_address; +{ + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); +frvbf_load_quad_GR (current_cpu, pc, tmp_address, FLD (f_GRk)); +} +if (NESI (FLD (f_GRi), FLD (f_GRk))) { +{ + { + SI opval = tmp_address; + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval); + written |= (1 << 5); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +frvbf_force_update (current_cpu); +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* nldqu: nldqu$pack @($GRi,$GRj),$GRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,nldqu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + BI tmp_do_op; + tmp_do_op = frvbf_check_non_excepting_load (current_cpu, FLD (f_GRi), FLD (f_GRj), FLD (f_GRk), 0, 6, 0); +if (tmp_do_op) { +{ + SI tmp_address; +{ + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); +frvbf_load_quad_GR (current_cpu, pc, tmp_address, FLD (f_GRk)); +} +if (NESI (FLD (f_GRi), FLD (f_GRk))) { +{ + { + SI opval = tmp_address; + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +frvbf_force_update (current_cpu); +} +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* ldqfu: ldqfu$pack @($GRi,$GRj),$FRintk */ + +static SEM_PC +SEM_FN_NAME (frvbf,ldqfu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + SI tmp_address; +{ + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); +frvbf_load_quad_FRint (current_cpu, pc, tmp_address, FLD (f_FRk)); +} + { + SI opval = tmp_address; + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +frvbf_force_update (current_cpu); +} + + return vpc; +#undef FLD +} + +/* ldqcu: ldqcu$pack @($GRi,$GRj),$CPRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,ldqcu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdcu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + SI tmp_address; +{ + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); +frvbf_load_quad_CPR (current_cpu, pc, tmp_address, FLD (f_CPRk)); +} + { + SI opval = tmp_address; + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +frvbf_force_update (current_cpu); +} + + return vpc; +#undef FLD +} + +/* nldqfu: nldqfu$pack @($GRi,$GRj),$FRintk */ + +static SEM_PC +SEM_FN_NAME (frvbf,nldqfu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + BI tmp_do_op; + tmp_do_op = frvbf_check_non_excepting_load (current_cpu, FLD (f_GRi), FLD (f_GRj), FLD (f_FRk), 0, 6, 1); +if (tmp_do_op) { +{ + SI tmp_address; +{ + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); +frvbf_load_quad_FRint (current_cpu, pc, tmp_address, FLD (f_FRk)); +} + { + SI opval = tmp_address; + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +frvbf_force_update (current_cpu); +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* ldsbi: ldsbi$pack @($GRi,$d12),$GRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,ldsbi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = frvbf_read_mem_QI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), FLD (f_d12))); + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* ldshi: ldshi$pack @($GRi,$d12),$GRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,ldshi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = frvbf_read_mem_HI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), FLD (f_d12))); + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* ldi: ldi$pack @($GRi,$d12),$GRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,ldi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = frvbf_read_mem_SI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), FLD (f_d12))); + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* ldubi: ldubi$pack @($GRi,$d12),$GRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,ldubi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = frvbf_read_mem_UQI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), FLD (f_d12))); + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* lduhi: lduhi$pack @($GRi,$d12),$GRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,lduhi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = frvbf_read_mem_UHI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), FLD (f_d12))); + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* ldbfi: ldbfi$pack @($GRi,$d12),$FRintk */ + +static SEM_PC +SEM_FN_NAME (frvbf,ldbfi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldbfi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = frvbf_read_mem_UQI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), FLD (f_d12))); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* ldhfi: ldhfi$pack @($GRi,$d12),$FRintk */ + +static SEM_PC +SEM_FN_NAME (frvbf,ldhfi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldbfi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = frvbf_read_mem_UHI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), FLD (f_d12))); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* ldfi: ldfi$pack @($GRi,$d12),$FRintk */ + +static SEM_PC +SEM_FN_NAME (frvbf,ldfi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldbfi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = frvbf_read_mem_SI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), FLD (f_d12))); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* nldsbi: nldsbi$pack @($GRi,$d12),$GRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,nldsbi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + BI tmp_do_op; + tmp_do_op = frvbf_check_non_excepting_load (current_cpu, FLD (f_GRi), -1, FLD (f_GRk), FLD (f_d12), 1, 0); +if (tmp_do_op) { + { + SI opval = frvbf_read_mem_QI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), FLD (f_d12))); + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + written |= (1 << 5); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* nldubi: nldubi$pack @($GRi,$d12),$GRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,nldubi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + BI tmp_do_op; + tmp_do_op = frvbf_check_non_excepting_load (current_cpu, FLD (f_GRi), -1, FLD (f_GRk), FLD (f_d12), 0, 0); +if (tmp_do_op) { + { + SI opval = frvbf_read_mem_UQI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), FLD (f_d12))); + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + written |= (1 << 5); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* nldshi: nldshi$pack @($GRi,$d12),$GRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,nldshi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + BI tmp_do_op; + tmp_do_op = frvbf_check_non_excepting_load (current_cpu, FLD (f_GRi), -1, FLD (f_GRk), FLD (f_d12), 3, 0); +if (tmp_do_op) { + { + SI opval = frvbf_read_mem_HI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), FLD (f_d12))); + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + written |= (1 << 5); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* nlduhi: nlduhi$pack @($GRi,$d12),$GRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,nlduhi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + BI tmp_do_op; + tmp_do_op = frvbf_check_non_excepting_load (current_cpu, FLD (f_GRi), -1, FLD (f_GRk), FLD (f_d12), 2, 0); +if (tmp_do_op) { + { + SI opval = frvbf_read_mem_UHI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), FLD (f_d12))); + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + written |= (1 << 5); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* nldi: nldi$pack @($GRi,$d12),$GRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,nldi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + BI tmp_do_op; + tmp_do_op = frvbf_check_non_excepting_load (current_cpu, FLD (f_GRi), -1, FLD (f_GRk), FLD (f_d12), 4, 0); +if (tmp_do_op) { + { + SI opval = frvbf_read_mem_SI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), FLD (f_d12))); + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + written |= (1 << 5); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* nldbfi: nldbfi$pack @($GRi,$d12),$FRintk */ + +static SEM_PC +SEM_FN_NAME (frvbf,nldbfi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldbfi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + BI tmp_do_op; + tmp_do_op = frvbf_check_non_excepting_load (current_cpu, FLD (f_GRi), -1, FLD (f_FRk), FLD (f_d12), 0, 1); +if (tmp_do_op) { + { + SI opval = frvbf_read_mem_UQI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), FLD (f_d12))); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + written |= (1 << 5); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* nldhfi: nldhfi$pack @($GRi,$d12),$FRintk */ + +static SEM_PC +SEM_FN_NAME (frvbf,nldhfi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldbfi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + BI tmp_do_op; + tmp_do_op = frvbf_check_non_excepting_load (current_cpu, FLD (f_GRi), -1, FLD (f_FRk), FLD (f_d12), 2, 1); +if (tmp_do_op) { + { + SI opval = frvbf_read_mem_UHI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), FLD (f_d12))); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + written |= (1 << 5); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* nldfi: nldfi$pack @($GRi,$d12),$FRintk */ + +static SEM_PC +SEM_FN_NAME (frvbf,nldfi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldbfi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + BI tmp_do_op; + tmp_do_op = frvbf_check_non_excepting_load (current_cpu, FLD (f_GRi), -1, FLD (f_FRk), FLD (f_d12), 4, 1); +if (tmp_do_op) { + { + SI opval = frvbf_read_mem_SI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), FLD (f_d12))); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + written |= (1 << 5); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* lddi: lddi$pack @($GRi,$d12),$GRdoublek */ + +static SEM_PC +SEM_FN_NAME (frvbf,lddi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smuli.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + SI tmp_address; +if (NESI (FLD (f_GRk), 0)) { +{ + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), FLD (f_d12)); + { + DI opval = frvbf_read_mem_DI (current_cpu, pc, tmp_address); + sim_queue_fn_di_write (current_cpu, frvbf_h_gr_double_set, FLD (f_GRk), opval); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "gr_double", 'D', opval); + } +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* lddfi: lddfi$pack @($GRi,$d12),$FRdoublek */ + +static SEM_PC +SEM_FN_NAME (frvbf,lddfi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_lddfi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + SI tmp_address; +{ + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), FLD (f_d12)); + { + DF opval = frvbf_read_mem_DF (current_cpu, pc, tmp_address); + sim_queue_fn_df_write (current_cpu, frvbf_h_fr_double_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr_double", 'f', opval); + } +} +} + + return vpc; +#undef FLD +} + +/* nlddi: nlddi$pack @($GRi,$d12),$GRdoublek */ + +static SEM_PC +SEM_FN_NAME (frvbf,nlddi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smuli.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + SI tmp_address; +{ + BI tmp_do_op; + tmp_do_op = frvbf_check_non_excepting_load (current_cpu, FLD (f_GRi), -1, FLD (f_GRk), FLD (f_d12), 5, 0); +if (tmp_do_op) { +if (NESI (FLD (f_GRk), 0)) { +{ + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), FLD (f_d12)); + { + DI opval = frvbf_read_mem_DI (current_cpu, pc, tmp_address); + sim_queue_fn_di_write (current_cpu, frvbf_h_gr_double_set, FLD (f_GRk), opval); + written |= (1 << 5); + TRACE_RESULT (current_cpu, abuf, "gr_double", 'D', opval); + } +} +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* nlddfi: nlddfi$pack @($GRi,$d12),$FRdoublek */ + +static SEM_PC +SEM_FN_NAME (frvbf,nlddfi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_lddfi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + SI tmp_address; +{ + BI tmp_do_op; + tmp_do_op = frvbf_check_non_excepting_load (current_cpu, FLD (f_GRi), -1, FLD (f_FRk), FLD (f_d12), 5, 1); +if (tmp_do_op) { +{ + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), FLD (f_d12)); + { + DF opval = frvbf_read_mem_DF (current_cpu, pc, tmp_address); + sim_queue_fn_df_write (current_cpu, frvbf_h_fr_double_set, FLD (f_FRk), opval); + written |= (1 << 5); + TRACE_RESULT (current_cpu, abuf, "fr_double", 'f', opval); + } +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* ldqi: ldqi$pack @($GRi,$d12),$GRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,ldqi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + SI tmp_address; +{ + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), FLD (f_d12)); +frvbf_load_quad_GR (current_cpu, pc, tmp_address, FLD (f_GRk)); +} +} + + return vpc; +#undef FLD +} + +/* ldqfi: ldqfi$pack @($GRi,$d12),$FRintk */ + +static SEM_PC +SEM_FN_NAME (frvbf,ldqfi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdfi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + SI tmp_address; +{ + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), FLD (f_d12)); +frvbf_load_quad_FRint (current_cpu, pc, tmp_address, FLD (f_FRk)); +} +} + + return vpc; +#undef FLD +} + +/* nldqfi: nldqfi$pack @($GRi,$d12),$FRintk */ + +static SEM_PC +SEM_FN_NAME (frvbf,nldqfi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdfi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + SI tmp_address; +{ + BI tmp_do_op; + tmp_do_op = frvbf_check_non_excepting_load (current_cpu, FLD (f_GRi), -1, FLD (f_FRk), FLD (f_d12), 6, 1); +if (tmp_do_op) { +{ + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), FLD (f_d12)); +frvbf_load_quad_FRint (current_cpu, pc, tmp_address, FLD (f_FRk)); +} +} +} +} + + return vpc; +#undef FLD +} + +/* stb: stb$pack $GRk,@($GRi,$GRj) */ + +static SEM_PC +SEM_FN_NAME (frvbf,stb) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +frvbf_write_mem_QI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))), GET_H_GR (FLD (f_GRk))); + + return vpc; +#undef FLD +} + +/* sth: sth$pack $GRk,@($GRi,$GRj) */ + +static SEM_PC +SEM_FN_NAME (frvbf,sth) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +frvbf_write_mem_HI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))), GET_H_GR (FLD (f_GRk))); + + return vpc; +#undef FLD +} + +/* st: st$pack $GRk,@($GRi,$GRj) */ + +static SEM_PC +SEM_FN_NAME (frvbf,st) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +frvbf_write_mem_SI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))), GET_H_GR (FLD (f_GRk))); + + return vpc; +#undef FLD +} + +/* stbf: stbf$pack $FRintk,@($GRi,$GRj) */ + +static SEM_PC +SEM_FN_NAME (frvbf,stbf) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +frvbf_write_mem_QI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))), GET_H_FR_INT (FLD (f_FRk))); + + return vpc; +#undef FLD +} + +/* sthf: sthf$pack $FRintk,@($GRi,$GRj) */ + +static SEM_PC +SEM_FN_NAME (frvbf,sthf) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +frvbf_write_mem_HI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))), GET_H_FR_INT (FLD (f_FRk))); + + return vpc; +#undef FLD +} + +/* stf: stf$pack $FRintk,@($GRi,$GRj) */ + +static SEM_PC +SEM_FN_NAME (frvbf,stf) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +frvbf_write_mem_SI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))), GET_H_FR_INT (FLD (f_FRk))); + + return vpc; +#undef FLD +} + +/* stc: stc$pack $CPRk,@($GRi,$GRj) */ + +static SEM_PC +SEM_FN_NAME (frvbf,stc) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stcu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +frvbf_write_mem_SI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))), CPU (h_cpr[FLD (f_CPRk)])); + + return vpc; +#undef FLD +} + +/* rstb: rstb$pack $GRk,@($GRi,$GRj) */ + +static SEM_PC +SEM_FN_NAME (frvbf,rstb) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + SI tmp_address; + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); +frvbf_write_mem_QI (current_cpu, pc, tmp_address, GET_H_GR (FLD (f_GRk))); +frvbf_check_recovering_store (current_cpu, tmp_address, FLD (f_GRk), 1, 0); +} + + return vpc; +#undef FLD +} + +/* rsth: rsth$pack $GRk,@($GRi,$GRj) */ + +static SEM_PC +SEM_FN_NAME (frvbf,rsth) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + SI tmp_address; + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); +frvbf_write_mem_HI (current_cpu, pc, tmp_address, GET_H_GR (FLD (f_GRk))); +frvbf_check_recovering_store (current_cpu, tmp_address, FLD (f_GRk), 2, 0); +} + + return vpc; +#undef FLD +} + +/* rst: rst$pack $GRk,@($GRi,$GRj) */ + +static SEM_PC +SEM_FN_NAME (frvbf,rst) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + SI tmp_address; + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); +frvbf_write_mem_SI (current_cpu, pc, tmp_address, GET_H_GR (FLD (f_GRk))); +frvbf_check_recovering_store (current_cpu, tmp_address, FLD (f_GRk), 4, 0); +} + + return vpc; +#undef FLD +} + +/* rstbf: rstbf$pack $FRintk,@($GRi,$GRj) */ + +static SEM_PC +SEM_FN_NAME (frvbf,rstbf) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + SI tmp_address; + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); +frvbf_write_mem_QI (current_cpu, pc, tmp_address, GET_H_FR_INT (FLD (f_FRk))); +frvbf_check_recovering_store (current_cpu, tmp_address, FLD (f_FRk), 1, 1); +} + + return vpc; +#undef FLD +} + +/* rsthf: rsthf$pack $FRintk,@($GRi,$GRj) */ + +static SEM_PC +SEM_FN_NAME (frvbf,rsthf) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + SI tmp_address; + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); +frvbf_write_mem_HI (current_cpu, pc, tmp_address, GET_H_FR_INT (FLD (f_FRk))); +frvbf_check_recovering_store (current_cpu, tmp_address, FLD (f_FRk), 2, 1); +} + + return vpc; +#undef FLD +} + +/* rstf: rstf$pack $FRintk,@($GRi,$GRj) */ + +static SEM_PC +SEM_FN_NAME (frvbf,rstf) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + SI tmp_address; + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); +frvbf_write_mem_SI (current_cpu, pc, tmp_address, GET_H_FR_INT (FLD (f_FRk))); +frvbf_check_recovering_store (current_cpu, tmp_address, FLD (f_FRk), 4, 1); +} + + return vpc; +#undef FLD +} + +/* std: std$pack $GRdoublek,@($GRi,$GRj) */ + +static SEM_PC +SEM_FN_NAME (frvbf,std) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + SI tmp_address; +{ + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); +frvbf_write_mem_DI (current_cpu, pc, tmp_address, GET_H_GR_DOUBLE (FLD (f_GRk))); +} +} + + return vpc; +#undef FLD +} + +/* stdf: stdf$pack $FRdoublek,@($GRi,$GRj) */ + +static SEM_PC +SEM_FN_NAME (frvbf,stdf) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + SI tmp_address; +{ + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); +frvbf_write_mem_DF (current_cpu, pc, tmp_address, GET_H_FR_DOUBLE (FLD (f_FRk))); +} +} + + return vpc; +#undef FLD +} + +/* stdc: stdc$pack $CPRdoublek,@($GRi,$GRj) */ + +static SEM_PC +SEM_FN_NAME (frvbf,stdc) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdcu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + SI tmp_address; +{ + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); +frvbf_write_mem_DI (current_cpu, pc, tmp_address, GET_H_CPR_DOUBLE (FLD (f_CPRk))); +} +} + + return vpc; +#undef FLD +} + +/* rstd: rstd$pack $GRdoublek,@($GRi,$GRj) */ + +static SEM_PC +SEM_FN_NAME (frvbf,rstd) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + SI tmp_address; +{ + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); +frvbf_write_mem_DI (current_cpu, pc, tmp_address, GET_H_GR_DOUBLE (FLD (f_GRk))); +} +frvbf_check_recovering_store (current_cpu, tmp_address, FLD (f_GRk), 8, 0); +} + + return vpc; +#undef FLD +} + +/* rstdf: rstdf$pack $FRdoublek,@($GRi,$GRj) */ + +static SEM_PC +SEM_FN_NAME (frvbf,rstdf) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + SI tmp_address; +{ + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); +frvbf_write_mem_DF (current_cpu, pc, tmp_address, GET_H_FR_DOUBLE (FLD (f_FRk))); +} +frvbf_check_recovering_store (current_cpu, tmp_address, FLD (f_FRk), 8, 1); +} + + return vpc; +#undef FLD +} + +/* stq: stq$pack $GRk,@($GRi,$GRj) */ + +static SEM_PC +SEM_FN_NAME (frvbf,stq) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + SI tmp_address; +{ + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); +frvbf_store_quad_GR (current_cpu, pc, tmp_address, FLD (f_GRk)); +} +} + + return vpc; +#undef FLD +} + +/* stqf: stqf$pack $FRintk,@($GRi,$GRj) */ + +static SEM_PC +SEM_FN_NAME (frvbf,stqf) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + SI tmp_address; +{ + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); +frvbf_store_quad_FRint (current_cpu, pc, tmp_address, FLD (f_FRk)); +} +} + + return vpc; +#undef FLD +} + +/* stqc: stqc$pack $CPRk,@($GRi,$GRj) */ + +static SEM_PC +SEM_FN_NAME (frvbf,stqc) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdcu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + SI tmp_address; +{ + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); +frvbf_store_quad_CPR (current_cpu, pc, tmp_address, FLD (f_CPRk)); +} +} + + return vpc; +#undef FLD +} + +/* rstq: rstq$pack $GRk,@($GRi,$GRj) */ + +static SEM_PC +SEM_FN_NAME (frvbf,rstq) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + SI tmp_address; +{ + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); +frvbf_store_quad_GR (current_cpu, pc, tmp_address, FLD (f_GRk)); +} +frvbf_check_recovering_store (current_cpu, tmp_address, FLD (f_GRk), 16, 0); +} + + return vpc; +#undef FLD +} + +/* rstqf: rstqf$pack $FRintk,@($GRi,$GRj) */ + +static SEM_PC +SEM_FN_NAME (frvbf,rstqf) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + SI tmp_address; +{ + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); +frvbf_store_quad_FRint (current_cpu, pc, tmp_address, FLD (f_FRk)); +} +frvbf_check_recovering_store (current_cpu, tmp_address, FLD (f_FRk), 16, 1); +} + + return vpc; +#undef FLD +} + +/* stbu: stbu$pack $GRk,@($GRi,$GRj) */ + +static SEM_PC +SEM_FN_NAME (frvbf,stbu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + USI tmp_address; + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); +frvbf_write_mem_QI (current_cpu, pc, tmp_address, GET_H_GR (FLD (f_GRk))); + { + SI opval = tmp_address; + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} + + return vpc; +#undef FLD +} + +/* sthu: sthu$pack $GRk,@($GRi,$GRj) */ + +static SEM_PC +SEM_FN_NAME (frvbf,sthu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + USI tmp_address; + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); +frvbf_write_mem_HI (current_cpu, pc, tmp_address, GET_H_GR (FLD (f_GRk))); + { + SI opval = tmp_address; + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} + + return vpc; +#undef FLD +} + +/* stu: stu$pack $GRk,@($GRi,$GRj) */ + +static SEM_PC +SEM_FN_NAME (frvbf,stu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + USI tmp_address; + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); +frvbf_write_mem_WI (current_cpu, pc, tmp_address, GET_H_GR (FLD (f_GRk))); + { + SI opval = tmp_address; + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} + + return vpc; +#undef FLD +} + +/* stbfu: stbfu$pack $FRintk,@($GRi,$GRj) */ + +static SEM_PC +SEM_FN_NAME (frvbf,stbfu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + USI tmp_address; + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); +frvbf_write_mem_QI (current_cpu, pc, tmp_address, GET_H_FR_INT (FLD (f_FRk))); + { + SI opval = tmp_address; + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} + + return vpc; +#undef FLD +} + +/* sthfu: sthfu$pack $FRintk,@($GRi,$GRj) */ + +static SEM_PC +SEM_FN_NAME (frvbf,sthfu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + USI tmp_address; + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); +frvbf_write_mem_HI (current_cpu, pc, tmp_address, GET_H_FR_INT (FLD (f_FRk))); + { + SI opval = tmp_address; + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} + + return vpc; +#undef FLD +} + +/* stfu: stfu$pack $FRintk,@($GRi,$GRj) */ + +static SEM_PC +SEM_FN_NAME (frvbf,stfu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + USI tmp_address; + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); +frvbf_write_mem_SI (current_cpu, pc, tmp_address, GET_H_FR_INT (FLD (f_FRk))); + { + SI opval = tmp_address; + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} + + return vpc; +#undef FLD +} + +/* stcu: stcu$pack $CPRk,@($GRi,$GRj) */ + +static SEM_PC +SEM_FN_NAME (frvbf,stcu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stcu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + USI tmp_address; + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); +frvbf_write_mem_SI (current_cpu, pc, tmp_address, CPU (h_cpr[FLD (f_CPRk)])); + { + SI opval = tmp_address; + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} + + return vpc; +#undef FLD +} + +/* stdu: stdu$pack $GRdoublek,@($GRi,$GRj) */ + +static SEM_PC +SEM_FN_NAME (frvbf,stdu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + SI tmp_address; +{ + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); +frvbf_write_mem_DI (current_cpu, pc, tmp_address, GET_H_GR_DOUBLE (FLD (f_GRk))); +} + { + SI opval = tmp_address; + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} + + return vpc; +#undef FLD +} + +/* stdfu: stdfu$pack $FRdoublek,@($GRi,$GRj) */ + +static SEM_PC +SEM_FN_NAME (frvbf,stdfu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + SI tmp_address; +{ + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); +frvbf_write_mem_DF (current_cpu, pc, tmp_address, GET_H_FR_DOUBLE (FLD (f_FRk))); +} + { + SI opval = tmp_address; + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} + + return vpc; +#undef FLD +} + +/* stdcu: stdcu$pack $CPRdoublek,@($GRi,$GRj) */ + +static SEM_PC +SEM_FN_NAME (frvbf,stdcu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdcu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + SI tmp_address; +{ + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); +frvbf_write_mem_DI (current_cpu, pc, tmp_address, GET_H_CPR_DOUBLE (FLD (f_CPRk))); +} + { + SI opval = tmp_address; + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} + + return vpc; +#undef FLD +} + +/* stqu: stqu$pack $GRk,@($GRi,$GRj) */ + +static SEM_PC +SEM_FN_NAME (frvbf,stqu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + SI tmp_address; +{ + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); +frvbf_store_quad_GR (current_cpu, pc, tmp_address, FLD (f_GRk)); +} + { + SI opval = tmp_address; + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} + + return vpc; +#undef FLD +} + +/* stqfu: stqfu$pack $FRintk,@($GRi,$GRj) */ + +static SEM_PC +SEM_FN_NAME (frvbf,stqfu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + SI tmp_address; +{ + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); +frvbf_store_quad_FRint (current_cpu, pc, tmp_address, FLD (f_FRk)); +} + { + SI opval = tmp_address; + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} + + return vpc; +#undef FLD +} + +/* stqcu: stqcu$pack $CPRk,@($GRi,$GRj) */ + +static SEM_PC +SEM_FN_NAME (frvbf,stqcu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdcu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + SI tmp_address; +{ + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); +frvbf_store_quad_CPR (current_cpu, pc, tmp_address, FLD (f_CPRk)); +} + { + SI opval = tmp_address; + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} + + return vpc; +#undef FLD +} + +/* cldsb: cldsb$pack @($GRi,$GRj),$GRk,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cldsb) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { + { + SI opval = frvbf_read_mem_QI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)))); + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + written |= (1 << 5); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cldub: cldub$pack @($GRi,$GRj),$GRk,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cldub) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { + { + SI opval = frvbf_read_mem_UQI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)))); + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + written |= (1 << 5); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cldsh: cldsh$pack @($GRi,$GRj),$GRk,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cldsh) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { + { + SI opval = frvbf_read_mem_HI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)))); + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + written |= (1 << 5); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* clduh: clduh$pack @($GRi,$GRj),$GRk,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,clduh) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { + { + SI opval = frvbf_read_mem_UHI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)))); + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + written |= (1 << 5); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cld: cld$pack @($GRi,$GRj),$GRk,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cld) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { + { + SI opval = frvbf_read_mem_SI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)))); + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + written |= (1 << 5); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cldbf: cldbf$pack @($GRi,$GRj),$FRintk,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cldbf) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { + { + SI opval = frvbf_read_mem_UQI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)))); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + written |= (1 << 5); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cldhf: cldhf$pack @($GRi,$GRj),$FRintk,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cldhf) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { + { + SI opval = frvbf_read_mem_UHI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)))); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + written |= (1 << 5); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cldf: cldf$pack @($GRi,$GRj),$FRintk,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cldf) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { + { + SI opval = frvbf_read_mem_SI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)))); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + written |= (1 << 5); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cldd: cldd$pack @($GRi,$GRj),$GRdoublek,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cldd) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +{ + SI tmp_address; +if (NESI (FLD (f_GRk), 0)) { +{ + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); + { + DI opval = frvbf_read_mem_DI (current_cpu, pc, tmp_address); + sim_queue_fn_di_write (current_cpu, frvbf_h_gr_double_set, FLD (f_GRk), opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "gr_double", 'D', opval); + } +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* clddf: clddf$pack @($GRi,$GRj),$FRdoublek,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,clddf) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddfu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +{ + SI tmp_address; +{ + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); + { + DF opval = frvbf_read_mem_DF (current_cpu, pc, tmp_address); + sim_queue_fn_df_write (current_cpu, frvbf_h_fr_double_set, FLD (f_FRk), opval); + written |= (1 << 5); + TRACE_RESULT (current_cpu, abuf, "fr_double", 'f', opval); + } +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cldq: cldq$pack @($GRi,$GRj),$GRk,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cldq) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +{ + SI tmp_address; +{ + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); +frvbf_load_quad_GR (current_cpu, pc, tmp_address, FLD (f_GRk)); +} +} +} + + return vpc; +#undef FLD +} + +/* cldsbu: cldsbu$pack @($GRi,$GRj),$GRk,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cldsbu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +{ + SI tmp_address; + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); + { + SI opval = frvbf_read_mem_QI (current_cpu, pc, tmp_address); + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + written |= (1 << 8); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +if (NESI (FLD (f_GRi), FLD (f_GRk))) { + { + SI opval = tmp_address; + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval); + written |= (1 << 7); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cldubu: cldubu$pack @($GRi,$GRj),$GRk,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cldubu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +{ + SI tmp_address; + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); + { + SI opval = frvbf_read_mem_UQI (current_cpu, pc, tmp_address); + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + written |= (1 << 8); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +if (NESI (FLD (f_GRi), FLD (f_GRk))) { + { + SI opval = tmp_address; + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval); + written |= (1 << 7); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cldshu: cldshu$pack @($GRi,$GRj),$GRk,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cldshu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +{ + SI tmp_address; + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); + { + SI opval = frvbf_read_mem_HI (current_cpu, pc, tmp_address); + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + written |= (1 << 8); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +if (NESI (FLD (f_GRi), FLD (f_GRk))) { + { + SI opval = tmp_address; + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval); + written |= (1 << 7); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* clduhu: clduhu$pack @($GRi,$GRj),$GRk,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,clduhu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +{ + SI tmp_address; + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); + { + SI opval = frvbf_read_mem_UHI (current_cpu, pc, tmp_address); + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + written |= (1 << 8); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +if (NESI (FLD (f_GRi), FLD (f_GRk))) { + { + SI opval = tmp_address; + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval); + written |= (1 << 7); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cldu: cldu$pack @($GRi,$GRj),$GRk,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cldu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +{ + SI tmp_address; + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); + { + SI opval = frvbf_read_mem_SI (current_cpu, pc, tmp_address); + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + written |= (1 << 8); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +if (NESI (FLD (f_GRi), FLD (f_GRk))) { + { + SI opval = tmp_address; + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval); + written |= (1 << 7); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cldbfu: cldbfu$pack @($GRi,$GRj),$FRintk,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cldbfu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +{ + SI tmp_address; + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); + { + SI opval = frvbf_read_mem_UQI (current_cpu, pc, tmp_address); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + written |= (1 << 5); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } + { + SI opval = tmp_address; + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cldhfu: cldhfu$pack @($GRi,$GRj),$FRintk,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cldhfu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +{ + SI tmp_address; + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); + { + SI opval = frvbf_read_mem_UHI (current_cpu, pc, tmp_address); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + written |= (1 << 5); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } + { + SI opval = tmp_address; + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cldfu: cldfu$pack @($GRi,$GRj),$FRintk,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cldfu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +{ + SI tmp_address; + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); + { + SI opval = frvbf_read_mem_SI (current_cpu, pc, tmp_address); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + written |= (1 << 5); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } + { + SI opval = tmp_address; + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* clddu: clddu$pack @($GRi,$GRj),$GRdoublek,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,clddu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +{ + SI tmp_address; +if (NESI (FLD (f_GRk), 0)) { +{ + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); + { + DI opval = frvbf_read_mem_DI (current_cpu, pc, tmp_address); + sim_queue_fn_di_write (current_cpu, frvbf_h_gr_double_set, FLD (f_GRk), opval); + written |= (1 << 7); + TRACE_RESULT (current_cpu, abuf, "gr_double", 'D', opval); + } +} +} +if (NESI (FLD (f_GRi), FLD (f_GRk))) { + { + SI opval = tmp_address; + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval); + written |= (1 << 8); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* clddfu: clddfu$pack @($GRi,$GRj),$FRdoublek,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,clddfu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddfu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +{ + SI tmp_address; +{ + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); + { + DF opval = frvbf_read_mem_DF (current_cpu, pc, tmp_address); + sim_queue_fn_df_write (current_cpu, frvbf_h_fr_double_set, FLD (f_FRk), opval); + written |= (1 << 5); + TRACE_RESULT (current_cpu, abuf, "fr_double", 'f', opval); + } +} + { + SI opval = tmp_address; + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cldqu: cldqu$pack @($GRi,$GRj),$GRk,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cldqu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +{ + SI tmp_address; +{ + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); +frvbf_load_quad_GR (current_cpu, pc, tmp_address, FLD (f_GRk)); +} +if (NESI (FLD (f_GRi), FLD (f_GRk))) { + { + SI opval = tmp_address; + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval); + written |= (1 << 7); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cstb: cstb$pack $GRk,@($GRi,$GRj),$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cstb) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +frvbf_write_mem_QI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))), GET_H_GR (FLD (f_GRk))); +} + + return vpc; +#undef FLD +} + +/* csth: csth$pack $GRk,@($GRi,$GRj),$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,csth) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +frvbf_write_mem_HI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))), GET_H_GR (FLD (f_GRk))); +} + + return vpc; +#undef FLD +} + +/* cst: cst$pack $GRk,@($GRi,$GRj),$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cst) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +frvbf_write_mem_SI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))), GET_H_GR (FLD (f_GRk))); +} + + return vpc; +#undef FLD +} + +/* cstbf: cstbf$pack $FRintk,@($GRi,$GRj),$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cstbf) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +frvbf_write_mem_QI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))), GET_H_FR_INT (FLD (f_FRk))); +} + + return vpc; +#undef FLD +} + +/* csthf: csthf$pack $FRintk,@($GRi,$GRj),$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,csthf) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +frvbf_write_mem_HI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))), GET_H_FR_INT (FLD (f_FRk))); +} + + return vpc; +#undef FLD +} + +/* cstf: cstf$pack $FRintk,@($GRi,$GRj),$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cstf) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +frvbf_write_mem_SI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))), GET_H_FR_INT (FLD (f_FRk))); +} + + return vpc; +#undef FLD +} + +/* cstd: cstd$pack $GRdoublek,@($GRi,$GRj),$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cstd) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +{ + SI tmp_address; +{ + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); +frvbf_write_mem_DI (current_cpu, pc, tmp_address, GET_H_GR_DOUBLE (FLD (f_GRk))); +} +} +} + + return vpc; +#undef FLD +} + +/* cstdf: cstdf$pack $FRdoublek,@($GRi,$GRj),$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cstdf) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +{ + SI tmp_address; +{ + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); +frvbf_write_mem_DF (current_cpu, pc, tmp_address, GET_H_FR_DOUBLE (FLD (f_FRk))); +} +} +} + + return vpc; +#undef FLD +} + +/* cstq: cstq$pack $GRk,@($GRi,$GRj),$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cstq) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +{ + SI tmp_address; +{ + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); +frvbf_store_quad_GR (current_cpu, pc, tmp_address, FLD (f_GRk)); +} +} +} + + return vpc; +#undef FLD +} + +/* cstbu: cstbu$pack $GRk,@($GRi,$GRj),$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cstbu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +{ + SI tmp_address; + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); +frvbf_write_mem_QI (current_cpu, pc, tmp_address, GET_H_GR (FLD (f_GRk))); + { + SI opval = tmp_address; + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* csthu: csthu$pack $GRk,@($GRi,$GRj),$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,csthu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +{ + SI tmp_address; + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); +frvbf_write_mem_HI (current_cpu, pc, tmp_address, GET_H_GR (FLD (f_GRk))); + { + SI opval = tmp_address; + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cstu: cstu$pack $GRk,@($GRi,$GRj),$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cstu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +{ + SI tmp_address; + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); +frvbf_write_mem_SI (current_cpu, pc, tmp_address, GET_H_GR (FLD (f_GRk))); + { + SI opval = tmp_address; + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cstbfu: cstbfu$pack $FRintk,@($GRi,$GRj),$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cstbfu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +{ + SI tmp_address; + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); +frvbf_write_mem_QI (current_cpu, pc, tmp_address, GET_H_FR_INT (FLD (f_FRk))); + { + SI opval = tmp_address; + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* csthfu: csthfu$pack $FRintk,@($GRi,$GRj),$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,csthfu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +{ + SI tmp_address; + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); +frvbf_write_mem_HI (current_cpu, pc, tmp_address, GET_H_FR_INT (FLD (f_FRk))); + { + SI opval = tmp_address; + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cstfu: cstfu$pack $FRintk,@($GRi,$GRj),$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cstfu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +{ + SI tmp_address; + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); +frvbf_write_mem_SI (current_cpu, pc, tmp_address, GET_H_FR_INT (FLD (f_FRk))); + { + SI opval = tmp_address; + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cstdu: cstdu$pack $GRdoublek,@($GRi,$GRj),$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cstdu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +{ + SI tmp_address; +{ + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); +frvbf_write_mem_DI (current_cpu, pc, tmp_address, GET_H_GR_DOUBLE (FLD (f_GRk))); +} + { + SI opval = tmp_address; + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cstdfu: cstdfu$pack $FRdoublek,@($GRi,$GRj),$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cstdfu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +{ + SI tmp_address; +{ + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); +frvbf_write_mem_DF (current_cpu, pc, tmp_address, GET_H_FR_DOUBLE (FLD (f_FRk))); +} + { + SI opval = tmp_address; + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* stbi: stbi$pack $GRk,@($GRi,$d12) */ + +static SEM_PC +SEM_FN_NAME (frvbf,stbi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +frvbf_write_mem_QI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), FLD (f_d12)), GET_H_GR (FLD (f_GRk))); + + return vpc; +#undef FLD +} + +/* sthi: sthi$pack $GRk,@($GRi,$d12) */ + +static SEM_PC +SEM_FN_NAME (frvbf,sthi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +frvbf_write_mem_HI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), FLD (f_d12)), GET_H_GR (FLD (f_GRk))); + + return vpc; +#undef FLD +} + +/* sti: sti$pack $GRk,@($GRi,$d12) */ + +static SEM_PC +SEM_FN_NAME (frvbf,sti) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +frvbf_write_mem_SI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), FLD (f_d12)), GET_H_GR (FLD (f_GRk))); + + return vpc; +#undef FLD +} + +/* stbfi: stbfi$pack $FRintk,@($GRi,$d12) */ + +static SEM_PC +SEM_FN_NAME (frvbf,stbfi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stbfi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +frvbf_write_mem_QI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), FLD (f_d12)), GET_H_FR_INT (FLD (f_FRk))); + + return vpc; +#undef FLD +} + +/* sthfi: sthfi$pack $FRintk,@($GRi,$d12) */ + +static SEM_PC +SEM_FN_NAME (frvbf,sthfi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stbfi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +frvbf_write_mem_HI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), FLD (f_d12)), GET_H_FR_INT (FLD (f_FRk))); + + return vpc; +#undef FLD +} + +/* stfi: stfi$pack $FRintk,@($GRi,$d12) */ + +static SEM_PC +SEM_FN_NAME (frvbf,stfi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stbfi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +frvbf_write_mem_SI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), FLD (f_d12)), GET_H_FR_INT (FLD (f_FRk))); + + return vpc; +#undef FLD +} + +/* stdi: stdi$pack $GRdoublek,@($GRi,$d12) */ + +static SEM_PC +SEM_FN_NAME (frvbf,stdi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + SI tmp_address; +{ + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), FLD (f_d12)); +frvbf_write_mem_DI (current_cpu, pc, tmp_address, GET_H_GR_DOUBLE (FLD (f_GRk))); +} +} + + return vpc; +#undef FLD +} + +/* stdfi: stdfi$pack $FRdoublek,@($GRi,$d12) */ + +static SEM_PC +SEM_FN_NAME (frvbf,stdfi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdfi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + SI tmp_address; +{ + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), FLD (f_d12)); +frvbf_write_mem_DF (current_cpu, pc, tmp_address, GET_H_FR_DOUBLE (FLD (f_FRk))); +} +} + + return vpc; +#undef FLD +} + +/* stqi: stqi$pack $GRk,@($GRi,$d12) */ + +static SEM_PC +SEM_FN_NAME (frvbf,stqi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + SI tmp_address; +{ + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), FLD (f_d12)); +frvbf_store_quad_GR (current_cpu, pc, tmp_address, FLD (f_GRk)); +} +} + + return vpc; +#undef FLD +} + +/* stqfi: stqfi$pack $FRintk,@($GRi,$d12) */ + +static SEM_PC +SEM_FN_NAME (frvbf,stqfi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdfi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + SI tmp_address; +{ + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), FLD (f_d12)); +frvbf_store_quad_FRint (current_cpu, pc, tmp_address, FLD (f_FRk)); +} +} + + return vpc; +#undef FLD +} + +/* swap: swap$pack @($GRi,$GRj),$GRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,swap) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + SI tmp_tmp; + SI tmp_address; + tmp_tmp = GET_H_GR (FLD (f_GRk)); + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); +frvbf_check_swap_address (current_cpu, tmp_address); + { + SI opval = frvbf_read_mem_WI (current_cpu, pc, tmp_address); + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +frvbf_write_mem_WI (current_cpu, pc, tmp_address, tmp_tmp); +} + + return vpc; +#undef FLD +} + +/* swapi: swapi$pack @($GRi,$d12),$GRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,swapi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + SI tmp_tmp; + SI tmp_address; + tmp_tmp = GET_H_GR (FLD (f_GRk)); + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), FLD (f_d12)); +frvbf_check_swap_address (current_cpu, tmp_address); + { + SI opval = frvbf_read_mem_WI (current_cpu, pc, tmp_address); + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +frvbf_write_mem_WI (current_cpu, pc, tmp_address, tmp_tmp); +} + + return vpc; +#undef FLD +} + +/* cswap: cswap$pack @($GRi,$GRj),$GRk,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cswap) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +{ + SI tmp_tmp; + SI tmp_address; + tmp_tmp = GET_H_GR (FLD (f_GRk)); + tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); +frvbf_check_swap_address (current_cpu, tmp_address); + { + SI opval = frvbf_read_mem_WI (current_cpu, pc, tmp_address); + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +frvbf_write_mem_WI (current_cpu, pc, tmp_address, tmp_tmp); +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* movgf: movgf$pack $GRj,$FRintk */ + +static SEM_PC +SEM_FN_NAME (frvbf,movgf) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmovgfd.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = GET_H_GR (FLD (f_GRj)); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* movfg: movfg$pack $FRintk,$GRj */ + +static SEM_PC +SEM_FN_NAME (frvbf,movfg) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmovfgd.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = GET_H_FR_INT (FLD (f_FRk)); + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRj), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* movgfd: movgfd$pack $GRj,$FRintk */ + +static SEM_PC +SEM_FN_NAME (frvbf,movgfd) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmovgfd.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQSI (FLD (f_GRj), 0)) { +{ + { + SI opval = 0; + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } + { + USI opval = 0; + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, ((FLD (f_FRk)) + (1)), opval); + written |= (1 << 5); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } +} +} else { +{ + { + SI opval = GET_H_GR (FLD (f_GRj)); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } + { + USI opval = GET_H_GR (((FLD (f_GRj)) + (1))); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, ((FLD (f_FRk)) + (1)), opval); + written |= (1 << 5); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* movfgd: movfgd$pack $FRintk,$GRj */ + +static SEM_PC +SEM_FN_NAME (frvbf,movfgd) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmovfgd.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (NESI (FLD (f_GRj), 0)) { +{ + { + SI opval = GET_H_FR_INT (FLD (f_FRk)); + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRj), opval); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + { + USI opval = GET_H_FR_INT (((FLD (f_FRk)) + (1))); + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, ((FLD (f_GRj)) + (1)), opval); + written |= (1 << 5); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* movgfq: movgfq$pack $GRj,$FRintk */ + +static SEM_PC +SEM_FN_NAME (frvbf,movgfq) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_movgfq.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQSI (FLD (f_GRj), 0)) { +{ + { + SI opval = 0; + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } + { + USI opval = 0; + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, ((FLD (f_FRk)) + (1)), opval); + written |= (1 << 7); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } + { + USI opval = 0; + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, ((FLD (f_FRk)) + (2)), opval); + written |= (1 << 8); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } + { + USI opval = 0; + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, ((FLD (f_FRk)) + (3)), opval); + written |= (1 << 9); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } +} +} else { +{ + { + SI opval = GET_H_GR (FLD (f_GRj)); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } + { + USI opval = GET_H_GR (((FLD (f_GRj)) + (1))); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, ((FLD (f_FRk)) + (1)), opval); + written |= (1 << 7); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } + { + USI opval = GET_H_GR (((FLD (f_GRj)) + (2))); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, ((FLD (f_FRk)) + (2)), opval); + written |= (1 << 8); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } + { + USI opval = GET_H_GR (((FLD (f_GRj)) + (3))); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, ((FLD (f_FRk)) + (3)), opval); + written |= (1 << 9); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* movfgq: movfgq$pack $FRintk,$GRj */ + +static SEM_PC +SEM_FN_NAME (frvbf,movfgq) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_movfgq.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (NESI (FLD (f_GRj), 0)) { +{ + { + SI opval = GET_H_FR_INT (FLD (f_FRk)); + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRj), opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + { + USI opval = GET_H_FR_INT (((FLD (f_FRk)) + (1))); + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, ((FLD (f_GRj)) + (1)), opval); + written |= (1 << 7); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + { + USI opval = GET_H_FR_INT (((FLD (f_FRk)) + (2))); + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, ((FLD (f_GRj)) + (2)), opval); + written |= (1 << 8); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + { + USI opval = GET_H_FR_INT (((FLD (f_FRk)) + (3))); + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, ((FLD (f_GRj)) + (3)), opval); + written |= (1 << 9); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cmovgf: cmovgf$pack $GRj,$FRintk,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cmovgf) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmovgfd.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { + { + SI opval = GET_H_GR (FLD (f_GRj)); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cmovfg: cmovfg$pack $FRintk,$GRj,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cmovfg) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmovfgd.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { + { + SI opval = GET_H_FR_INT (FLD (f_FRk)); + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRj), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cmovgfd: cmovgfd$pack $GRj,$FRintk,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cmovgfd) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmovgfd.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +if (EQSI (FLD (f_GRj), 0)) { +{ + { + SI opval = 0; + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } + { + USI opval = 0; + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, ((FLD (f_FRk)) + (1)), opval); + written |= (1 << 7); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } +} +} else { +{ + { + SI opval = GET_H_GR (FLD (f_GRj)); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } + { + USI opval = GET_H_GR (((FLD (f_GRj)) + (1))); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, ((FLD (f_FRk)) + (1)), opval); + written |= (1 << 7); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cmovfgd: cmovfgd$pack $FRintk,$GRj,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cmovfgd) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmovfgd.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (ANDIF (NESI (FLD (f_GRj), 0), EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2)))) { +{ + { + SI opval = GET_H_FR_INT (FLD (f_FRk)); + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRj), opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + { + USI opval = GET_H_FR_INT (((FLD (f_FRk)) + (1))); + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, ((FLD (f_GRj)) + (1)), opval); + written |= (1 << 7); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* movgs: movgs$pack $GRj,$spr */ + +static SEM_PC +SEM_FN_NAME (frvbf,movgs) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_movgs.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + USI opval = GET_H_GR (FLD (f_GRj)); + sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, FLD (f_spr), opval); + TRACE_RESULT (current_cpu, abuf, "spr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* movsg: movsg$pack $spr,$GRj */ + +static SEM_PC +SEM_FN_NAME (frvbf,movsg) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_movsg.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = GET_H_SPR (FLD (f_spr)); + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRj), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* bra: bra$pack $hint_taken$label16 */ + +static SEM_PC +SEM_FN_NAME (frvbf,bra) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_model_branch (current_cpu, FLD (i_label16), FLD (f_hint)); + { + USI opval = FLD (i_label16); + sim_queue_pc_write (current_cpu, opval); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} + + return vpc; +#undef FLD +} + +/* bno: bno$pack$hint_not_taken */ + +static SEM_PC +SEM_FN_NAME (frvbf,bno) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +frvbf_model_branch (current_cpu, FLD (i_label16), FLD (f_hint)); + + return vpc; +#undef FLD +} + +/* beq: beq$pack $ICCi_2,$hint,$label16 */ + +static SEM_PC +SEM_FN_NAME (frvbf,beq) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_model_branch (current_cpu, FLD (i_label16), FLD (f_hint)); +if (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 4), 2))) { + { + USI opval = FLD (i_label16); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* bne: bne$pack $ICCi_2,$hint,$label16 */ + +static SEM_PC +SEM_FN_NAME (frvbf,bne) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_model_branch (current_cpu, FLD (i_label16), FLD (f_hint)); +if (NOTBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 4), 2)))) { + { + USI opval = FLD (i_label16); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* ble: ble$pack $ICCi_2,$hint,$label16 */ + +static SEM_PC +SEM_FN_NAME (frvbf,ble) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_model_branch (current_cpu, FLD (i_label16), FLD (f_hint)); +if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 4), 2)), XORBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 8), 3)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 2), 1))))) { + { + USI opval = FLD (i_label16); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* bgt: bgt$pack $ICCi_2,$hint,$label16 */ + +static SEM_PC +SEM_FN_NAME (frvbf,bgt) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_model_branch (current_cpu, FLD (i_label16), FLD (f_hint)); +if (NOTBI (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 4), 2)), XORBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 8), 3)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 2), 1)))))) { + { + USI opval = FLD (i_label16); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* blt: blt$pack $ICCi_2,$hint,$label16 */ + +static SEM_PC +SEM_FN_NAME (frvbf,blt) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_model_branch (current_cpu, FLD (i_label16), FLD (f_hint)); +if (XORBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 8), 3)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 2), 1)))) { + { + USI opval = FLD (i_label16); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* bge: bge$pack $ICCi_2,$hint,$label16 */ + +static SEM_PC +SEM_FN_NAME (frvbf,bge) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_model_branch (current_cpu, FLD (i_label16), FLD (f_hint)); +if (NOTBI (XORBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 8), 3)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 2), 1))))) { + { + USI opval = FLD (i_label16); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* bls: bls$pack $ICCi_2,$hint,$label16 */ + +static SEM_PC +SEM_FN_NAME (frvbf,bls) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_model_branch (current_cpu, FLD (i_label16), FLD (f_hint)); +if (ORIF (TRUNCQIBI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 1)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 4), 2)))) { + { + USI opval = FLD (i_label16); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* bhi: bhi$pack $ICCi_2,$hint,$label16 */ + +static SEM_PC +SEM_FN_NAME (frvbf,bhi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_model_branch (current_cpu, FLD (i_label16), FLD (f_hint)); +if (NOTBI (ORIF (TRUNCQIBI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 1)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 4), 2))))) { + { + USI opval = FLD (i_label16); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* bc: bc$pack $ICCi_2,$hint,$label16 */ + +static SEM_PC +SEM_FN_NAME (frvbf,bc) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_model_branch (current_cpu, FLD (i_label16), FLD (f_hint)); +if (TRUNCQIBI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 1))) { + { + USI opval = FLD (i_label16); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* bnc: bnc$pack $ICCi_2,$hint,$label16 */ + +static SEM_PC +SEM_FN_NAME (frvbf,bnc) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_model_branch (current_cpu, FLD (i_label16), FLD (f_hint)); +if (NOTBI (TRUNCQIBI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 1)))) { + { + USI opval = FLD (i_label16); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* bn: bn$pack $ICCi_2,$hint,$label16 */ + +static SEM_PC +SEM_FN_NAME (frvbf,bn) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_model_branch (current_cpu, FLD (i_label16), FLD (f_hint)); +if (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 8), 3))) { + { + USI opval = FLD (i_label16); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* bp: bp$pack $ICCi_2,$hint,$label16 */ + +static SEM_PC +SEM_FN_NAME (frvbf,bp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_model_branch (current_cpu, FLD (i_label16), FLD (f_hint)); +if (NOTBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 8), 3)))) { + { + USI opval = FLD (i_label16); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* bv: bv$pack $ICCi_2,$hint,$label16 */ + +static SEM_PC +SEM_FN_NAME (frvbf,bv) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_model_branch (current_cpu, FLD (i_label16), FLD (f_hint)); +if (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 2), 1))) { + { + USI opval = FLD (i_label16); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* bnv: bnv$pack $ICCi_2,$hint,$label16 */ + +static SEM_PC +SEM_FN_NAME (frvbf,bnv) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_model_branch (current_cpu, FLD (i_label16), FLD (f_hint)); +if (NOTBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 2), 1)))) { + { + USI opval = FLD (i_label16); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* fbra: fbra$pack $hint_taken$label16 */ + +static SEM_PC +SEM_FN_NAME (frvbf,fbra) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_model_branch (current_cpu, FLD (i_label16), FLD (f_hint)); + { + USI opval = FLD (i_label16); + sim_queue_pc_write (current_cpu, opval); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} + + return vpc; +#undef FLD +} + +/* fbno: fbno$pack$hint_not_taken */ + +static SEM_PC +SEM_FN_NAME (frvbf,fbno) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +frvbf_model_branch (current_cpu, FLD (i_label16), FLD (f_hint)); + + return vpc; +#undef FLD +} + +/* fbne: fbne$pack $FCCi_2,$hint,$label16 */ + +static SEM_PC +SEM_FN_NAME (frvbf,fbne) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_model_branch (current_cpu, FLD (i_label16), FLD (f_hint)); +if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 4), 2)), ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 2), 1)), TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 1))))) { + { + USI opval = FLD (i_label16); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* fbeq: fbeq$pack $FCCi_2,$hint,$label16 */ + +static SEM_PC +SEM_FN_NAME (frvbf,fbeq) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_model_branch (current_cpu, FLD (i_label16), FLD (f_hint)); +if (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 8), 3))) { + { + USI opval = FLD (i_label16); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* fblg: fblg$pack $FCCi_2,$hint,$label16 */ + +static SEM_PC +SEM_FN_NAME (frvbf,fblg) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_model_branch (current_cpu, FLD (i_label16), FLD (f_hint)); +if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 4), 2)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 2), 1)))) { + { + USI opval = FLD (i_label16); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* fbue: fbue$pack $FCCi_2,$hint,$label16 */ + +static SEM_PC +SEM_FN_NAME (frvbf,fbue) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_model_branch (current_cpu, FLD (i_label16), FLD (f_hint)); +if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 8), 3)), TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 1)))) { + { + USI opval = FLD (i_label16); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* fbul: fbul$pack $FCCi_2,$hint,$label16 */ + +static SEM_PC +SEM_FN_NAME (frvbf,fbul) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_model_branch (current_cpu, FLD (i_label16), FLD (f_hint)); +if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 4), 2)), TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 1)))) { + { + USI opval = FLD (i_label16); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* fbge: fbge$pack $FCCi_2,$hint,$label16 */ + +static SEM_PC +SEM_FN_NAME (frvbf,fbge) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_model_branch (current_cpu, FLD (i_label16), FLD (f_hint)); +if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 8), 3)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 2), 1)))) { + { + USI opval = FLD (i_label16); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* fblt: fblt$pack $FCCi_2,$hint,$label16 */ + +static SEM_PC +SEM_FN_NAME (frvbf,fblt) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_model_branch (current_cpu, FLD (i_label16), FLD (f_hint)); +if (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 4), 2))) { + { + USI opval = FLD (i_label16); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* fbuge: fbuge$pack $FCCi_2,$hint,$label16 */ + +static SEM_PC +SEM_FN_NAME (frvbf,fbuge) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_model_branch (current_cpu, FLD (i_label16), FLD (f_hint)); +if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 8), 3)), ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 2), 1)), TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 1))))) { + { + USI opval = FLD (i_label16); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* fbug: fbug$pack $FCCi_2,$hint,$label16 */ + +static SEM_PC +SEM_FN_NAME (frvbf,fbug) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_model_branch (current_cpu, FLD (i_label16), FLD (f_hint)); +if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 2), 1)), TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 1)))) { + { + USI opval = FLD (i_label16); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* fble: fble$pack $FCCi_2,$hint,$label16 */ + +static SEM_PC +SEM_FN_NAME (frvbf,fble) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_model_branch (current_cpu, FLD (i_label16), FLD (f_hint)); +if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 8), 3)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 4), 2)))) { + { + USI opval = FLD (i_label16); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* fbgt: fbgt$pack $FCCi_2,$hint,$label16 */ + +static SEM_PC +SEM_FN_NAME (frvbf,fbgt) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_model_branch (current_cpu, FLD (i_label16), FLD (f_hint)); +if (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 2), 1))) { + { + USI opval = FLD (i_label16); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* fbule: fbule$pack $FCCi_2,$hint,$label16 */ + +static SEM_PC +SEM_FN_NAME (frvbf,fbule) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_model_branch (current_cpu, FLD (i_label16), FLD (f_hint)); +if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 8), 3)), ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 4), 2)), TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 1))))) { + { + USI opval = FLD (i_label16); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* fbu: fbu$pack $FCCi_2,$hint,$label16 */ + +static SEM_PC +SEM_FN_NAME (frvbf,fbu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_model_branch (current_cpu, FLD (i_label16), FLD (f_hint)); +if (TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 1))) { + { + USI opval = FLD (i_label16); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* fbo: fbo$pack $FCCi_2,$hint,$label16 */ + +static SEM_PC +SEM_FN_NAME (frvbf,fbo) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_model_branch (current_cpu, FLD (i_label16), FLD (f_hint)); +if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 8), 3)), ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 4), 2)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 2), 1))))) { + { + USI opval = FLD (i_label16); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* bctrlr: bctrlr$pack $ccond,$hint */ + +static SEM_PC +SEM_FN_NAME (frvbf,bctrlr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint)); +{ + SI tmp_tmp; + tmp_tmp = SUBSI (GET_H_SPR (((UINT) 273)), 1); + { + USI opval = tmp_tmp; + sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, ((UINT) 273), opval); + TRACE_RESULT (current_cpu, abuf, "spr", 'x', opval); + } +if (EQSI (FLD (f_ccond), 0)) { +if (NESI (tmp_tmp, 0)) { + { + USI opval = GET_H_SPR (((UINT) 272)); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 5); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} else { +if (EQSI (tmp_tmp, 0)) { + { + USI opval = GET_H_SPR (((UINT) 272)); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 5); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* bralr: bralr$pack$hint_taken */ + +static SEM_PC +SEM_FN_NAME (frvbf,bralr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint)); + { + USI opval = GET_H_SPR (((UINT) 272)); + sim_queue_pc_write (current_cpu, opval); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} + + return vpc; +#undef FLD +} + +/* bnolr: bnolr$pack$hint_not_taken */ + +static SEM_PC +SEM_FN_NAME (frvbf,bnolr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint)); + + return vpc; +#undef FLD +} + +/* beqlr: beqlr$pack $ICCi_2,$hint */ + +static SEM_PC +SEM_FN_NAME (frvbf,beqlr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint)); +if (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 4), 2))) { + { + USI opval = GET_H_SPR (((UINT) 272)); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* bnelr: bnelr$pack $ICCi_2,$hint */ + +static SEM_PC +SEM_FN_NAME (frvbf,bnelr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint)); +if (NOTBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 4), 2)))) { + { + USI opval = GET_H_SPR (((UINT) 272)); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* blelr: blelr$pack $ICCi_2,$hint */ + +static SEM_PC +SEM_FN_NAME (frvbf,blelr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint)); +if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 4), 2)), XORBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 8), 3)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 2), 1))))) { + { + USI opval = GET_H_SPR (((UINT) 272)); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* bgtlr: bgtlr$pack $ICCi_2,$hint */ + +static SEM_PC +SEM_FN_NAME (frvbf,bgtlr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint)); +if (NOTBI (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 4), 2)), XORBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 8), 3)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 2), 1)))))) { + { + USI opval = GET_H_SPR (((UINT) 272)); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* bltlr: bltlr$pack $ICCi_2,$hint */ + +static SEM_PC +SEM_FN_NAME (frvbf,bltlr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint)); +if (XORBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 8), 3)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 2), 1)))) { + { + USI opval = GET_H_SPR (((UINT) 272)); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* bgelr: bgelr$pack $ICCi_2,$hint */ + +static SEM_PC +SEM_FN_NAME (frvbf,bgelr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint)); +if (NOTBI (XORBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 8), 3)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 2), 1))))) { + { + USI opval = GET_H_SPR (((UINT) 272)); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* blslr: blslr$pack $ICCi_2,$hint */ + +static SEM_PC +SEM_FN_NAME (frvbf,blslr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint)); +if (ORIF (TRUNCQIBI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 1)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 4), 2)))) { + { + USI opval = GET_H_SPR (((UINT) 272)); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* bhilr: bhilr$pack $ICCi_2,$hint */ + +static SEM_PC +SEM_FN_NAME (frvbf,bhilr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint)); +if (NOTBI (ORIF (TRUNCQIBI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 1)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 4), 2))))) { + { + USI opval = GET_H_SPR (((UINT) 272)); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* bclr: bclr$pack $ICCi_2,$hint */ + +static SEM_PC +SEM_FN_NAME (frvbf,bclr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint)); +if (TRUNCQIBI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 1))) { + { + USI opval = GET_H_SPR (((UINT) 272)); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* bnclr: bnclr$pack $ICCi_2,$hint */ + +static SEM_PC +SEM_FN_NAME (frvbf,bnclr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint)); +if (NOTBI (TRUNCQIBI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 1)))) { + { + USI opval = GET_H_SPR (((UINT) 272)); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* bnlr: bnlr$pack $ICCi_2,$hint */ + +static SEM_PC +SEM_FN_NAME (frvbf,bnlr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint)); +if (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 8), 3))) { + { + USI opval = GET_H_SPR (((UINT) 272)); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* bplr: bplr$pack $ICCi_2,$hint */ + +static SEM_PC +SEM_FN_NAME (frvbf,bplr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint)); +if (NOTBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 8), 3)))) { + { + USI opval = GET_H_SPR (((UINT) 272)); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* bvlr: bvlr$pack $ICCi_2,$hint */ + +static SEM_PC +SEM_FN_NAME (frvbf,bvlr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint)); +if (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 2), 1))) { + { + USI opval = GET_H_SPR (((UINT) 272)); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* bnvlr: bnvlr$pack $ICCi_2,$hint */ + +static SEM_PC +SEM_FN_NAME (frvbf,bnvlr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint)); +if (NOTBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 2), 1)))) { + { + USI opval = GET_H_SPR (((UINT) 272)); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* fbralr: fbralr$pack$hint_taken */ + +static SEM_PC +SEM_FN_NAME (frvbf,fbralr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint)); + { + USI opval = GET_H_SPR (((UINT) 272)); + sim_queue_pc_write (current_cpu, opval); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} + + return vpc; +#undef FLD +} + +/* fbnolr: fbnolr$pack$hint_not_taken */ + +static SEM_PC +SEM_FN_NAME (frvbf,fbnolr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint)); + + return vpc; +#undef FLD +} + +/* fbeqlr: fbeqlr$pack $FCCi_2,$hint */ + +static SEM_PC +SEM_FN_NAME (frvbf,fbeqlr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint)); +if (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 8), 3))) { + { + USI opval = GET_H_SPR (((UINT) 272)); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* fbnelr: fbnelr$pack $FCCi_2,$hint */ + +static SEM_PC +SEM_FN_NAME (frvbf,fbnelr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint)); +if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 4), 2)), ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 2), 1)), TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 1))))) { + { + USI opval = GET_H_SPR (((UINT) 272)); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* fblglr: fblglr$pack $FCCi_2,$hint */ + +static SEM_PC +SEM_FN_NAME (frvbf,fblglr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint)); +if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 4), 2)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 2), 1)))) { + { + USI opval = GET_H_SPR (((UINT) 272)); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* fbuelr: fbuelr$pack $FCCi_2,$hint */ + +static SEM_PC +SEM_FN_NAME (frvbf,fbuelr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint)); +if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 8), 3)), TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 1)))) { + { + USI opval = GET_H_SPR (((UINT) 272)); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* fbullr: fbullr$pack $FCCi_2,$hint */ + +static SEM_PC +SEM_FN_NAME (frvbf,fbullr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint)); +if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 4), 2)), TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 1)))) { + { + USI opval = GET_H_SPR (((UINT) 272)); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* fbgelr: fbgelr$pack $FCCi_2,$hint */ + +static SEM_PC +SEM_FN_NAME (frvbf,fbgelr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint)); +if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 8), 3)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 2), 1)))) { + { + USI opval = GET_H_SPR (((UINT) 272)); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* fbltlr: fbltlr$pack $FCCi_2,$hint */ + +static SEM_PC +SEM_FN_NAME (frvbf,fbltlr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint)); +if (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 4), 2))) { + { + USI opval = GET_H_SPR (((UINT) 272)); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* fbugelr: fbugelr$pack $FCCi_2,$hint */ + +static SEM_PC +SEM_FN_NAME (frvbf,fbugelr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint)); +if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 8), 3)), ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 2), 1)), TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 1))))) { + { + USI opval = GET_H_SPR (((UINT) 272)); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* fbuglr: fbuglr$pack $FCCi_2,$hint */ + +static SEM_PC +SEM_FN_NAME (frvbf,fbuglr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint)); +if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 2), 1)), TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 1)))) { + { + USI opval = GET_H_SPR (((UINT) 272)); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* fblelr: fblelr$pack $FCCi_2,$hint */ + +static SEM_PC +SEM_FN_NAME (frvbf,fblelr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint)); +if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 8), 3)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 4), 2)))) { + { + USI opval = GET_H_SPR (((UINT) 272)); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* fbgtlr: fbgtlr$pack $FCCi_2,$hint */ + +static SEM_PC +SEM_FN_NAME (frvbf,fbgtlr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint)); +if (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 2), 1))) { + { + USI opval = GET_H_SPR (((UINT) 272)); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* fbulelr: fbulelr$pack $FCCi_2,$hint */ + +static SEM_PC +SEM_FN_NAME (frvbf,fbulelr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint)); +if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 8), 3)), ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 4), 2)), TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 1))))) { + { + USI opval = GET_H_SPR (((UINT) 272)); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* fbulr: fbulr$pack $FCCi_2,$hint */ + +static SEM_PC +SEM_FN_NAME (frvbf,fbulr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint)); +if (TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 1))) { + { + USI opval = GET_H_SPR (((UINT) 272)); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* fbolr: fbolr$pack $FCCi_2,$hint */ + +static SEM_PC +SEM_FN_NAME (frvbf,fbolr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint)); +if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 8), 3)), ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 4), 2)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 2), 1))))) { + { + USI opval = GET_H_SPR (((UINT) 272)); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* bcralr: bcralr$pack $ccond$hint_taken */ + +static SEM_PC +SEM_FN_NAME (frvbf,bcralr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint)); +{ + SI tmp_tmp; + tmp_tmp = SUBSI (GET_H_SPR (((UINT) 273)), 1); + { + USI opval = tmp_tmp; + sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, ((UINT) 273), opval); + TRACE_RESULT (current_cpu, abuf, "spr", 'x', opval); + } +if (EQSI (FLD (f_ccond), 0)) { +if (NESI (tmp_tmp, 0)) { + { + USI opval = GET_H_SPR (((UINT) 272)); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 5); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} else { +if (EQSI (tmp_tmp, 0)) { + { + USI opval = GET_H_SPR (((UINT) 272)); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 5); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* bcnolr: bcnolr$pack$hint_not_taken */ + +static SEM_PC +SEM_FN_NAME (frvbf,bcnolr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint)); +{ + SI tmp_tmp; + tmp_tmp = SUBSI (GET_H_SPR (((UINT) 273)), 1); + { + USI opval = tmp_tmp; + sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, ((UINT) 273), opval); + TRACE_RESULT (current_cpu, abuf, "spr", 'x', opval); + } +((void) 0); /*nop*/ +} +} + + return vpc; +#undef FLD +} + +/* bceqlr: bceqlr$pack $ICCi_2,$ccond,$hint */ + +static SEM_PC +SEM_FN_NAME (frvbf,bceqlr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint)); +{ + SI tmp_tmp; + tmp_tmp = SUBSI (GET_H_SPR (((UINT) 273)), 1); + { + USI opval = tmp_tmp; + sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, ((UINT) 273), opval); + TRACE_RESULT (current_cpu, abuf, "spr", 'x', opval); + } +if (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 4), 2))) { +if (EQSI (FLD (f_ccond), 0)) { +if (NESI (tmp_tmp, 0)) { + { + USI opval = GET_H_SPR (((UINT) 272)); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} else { +if (EQSI (tmp_tmp, 0)) { + { + USI opval = GET_H_SPR (((UINT) 272)); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* bcnelr: bcnelr$pack $ICCi_2,$ccond,$hint */ + +static SEM_PC +SEM_FN_NAME (frvbf,bcnelr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint)); +{ + SI tmp_tmp; + tmp_tmp = SUBSI (GET_H_SPR (((UINT) 273)), 1); + { + USI opval = tmp_tmp; + sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, ((UINT) 273), opval); + TRACE_RESULT (current_cpu, abuf, "spr", 'x', opval); + } +if (NOTBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 4), 2)))) { +if (EQSI (FLD (f_ccond), 0)) { +if (NESI (tmp_tmp, 0)) { + { + USI opval = GET_H_SPR (((UINT) 272)); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} else { +if (EQSI (tmp_tmp, 0)) { + { + USI opval = GET_H_SPR (((UINT) 272)); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* bclelr: bclelr$pack $ICCi_2,$ccond,$hint */ + +static SEM_PC +SEM_FN_NAME (frvbf,bclelr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint)); +{ + SI tmp_tmp; + tmp_tmp = SUBSI (GET_H_SPR (((UINT) 273)), 1); + { + USI opval = tmp_tmp; + sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, ((UINT) 273), opval); + TRACE_RESULT (current_cpu, abuf, "spr", 'x', opval); + } +if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 4), 2)), XORBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 8), 3)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 2), 1))))) { +if (EQSI (FLD (f_ccond), 0)) { +if (NESI (tmp_tmp, 0)) { + { + USI opval = GET_H_SPR (((UINT) 272)); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} else { +if (EQSI (tmp_tmp, 0)) { + { + USI opval = GET_H_SPR (((UINT) 272)); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* bcgtlr: bcgtlr$pack $ICCi_2,$ccond,$hint */ + +static SEM_PC +SEM_FN_NAME (frvbf,bcgtlr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint)); +{ + SI tmp_tmp; + tmp_tmp = SUBSI (GET_H_SPR (((UINT) 273)), 1); + { + USI opval = tmp_tmp; + sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, ((UINT) 273), opval); + TRACE_RESULT (current_cpu, abuf, "spr", 'x', opval); + } +if (NOTBI (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 4), 2)), XORBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 8), 3)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 2), 1)))))) { +if (EQSI (FLD (f_ccond), 0)) { +if (NESI (tmp_tmp, 0)) { + { + USI opval = GET_H_SPR (((UINT) 272)); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} else { +if (EQSI (tmp_tmp, 0)) { + { + USI opval = GET_H_SPR (((UINT) 272)); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* bcltlr: bcltlr$pack $ICCi_2,$ccond,$hint */ + +static SEM_PC +SEM_FN_NAME (frvbf,bcltlr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint)); +{ + SI tmp_tmp; + tmp_tmp = SUBSI (GET_H_SPR (((UINT) 273)), 1); + { + USI opval = tmp_tmp; + sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, ((UINT) 273), opval); + TRACE_RESULT (current_cpu, abuf, "spr", 'x', opval); + } +if (XORBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 8), 3)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 2), 1)))) { +if (EQSI (FLD (f_ccond), 0)) { +if (NESI (tmp_tmp, 0)) { + { + USI opval = GET_H_SPR (((UINT) 272)); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} else { +if (EQSI (tmp_tmp, 0)) { + { + USI opval = GET_H_SPR (((UINT) 272)); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* bcgelr: bcgelr$pack $ICCi_2,$ccond,$hint */ + +static SEM_PC +SEM_FN_NAME (frvbf,bcgelr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint)); +{ + SI tmp_tmp; + tmp_tmp = SUBSI (GET_H_SPR (((UINT) 273)), 1); + { + USI opval = tmp_tmp; + sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, ((UINT) 273), opval); + TRACE_RESULT (current_cpu, abuf, "spr", 'x', opval); + } +if (NOTBI (XORBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 8), 3)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 2), 1))))) { +if (EQSI (FLD (f_ccond), 0)) { +if (NESI (tmp_tmp, 0)) { + { + USI opval = GET_H_SPR (((UINT) 272)); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} else { +if (EQSI (tmp_tmp, 0)) { + { + USI opval = GET_H_SPR (((UINT) 272)); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* bclslr: bclslr$pack $ICCi_2,$ccond,$hint */ + +static SEM_PC +SEM_FN_NAME (frvbf,bclslr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint)); +{ + SI tmp_tmp; + tmp_tmp = SUBSI (GET_H_SPR (((UINT) 273)), 1); + { + USI opval = tmp_tmp; + sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, ((UINT) 273), opval); + TRACE_RESULT (current_cpu, abuf, "spr", 'x', opval); + } +if (ORIF (TRUNCQIBI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 1)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 4), 2)))) { +if (EQSI (FLD (f_ccond), 0)) { +if (NESI (tmp_tmp, 0)) { + { + USI opval = GET_H_SPR (((UINT) 272)); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} else { +if (EQSI (tmp_tmp, 0)) { + { + USI opval = GET_H_SPR (((UINT) 272)); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* bchilr: bchilr$pack $ICCi_2,$ccond,$hint */ + +static SEM_PC +SEM_FN_NAME (frvbf,bchilr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint)); +{ + SI tmp_tmp; + tmp_tmp = SUBSI (GET_H_SPR (((UINT) 273)), 1); + { + USI opval = tmp_tmp; + sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, ((UINT) 273), opval); + TRACE_RESULT (current_cpu, abuf, "spr", 'x', opval); + } +if (NOTBI (ORIF (TRUNCQIBI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 1)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 4), 2))))) { +if (EQSI (FLD (f_ccond), 0)) { +if (NESI (tmp_tmp, 0)) { + { + USI opval = GET_H_SPR (((UINT) 272)); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} else { +if (EQSI (tmp_tmp, 0)) { + { + USI opval = GET_H_SPR (((UINT) 272)); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* bcclr: bcclr$pack $ICCi_2,$ccond,$hint */ + +static SEM_PC +SEM_FN_NAME (frvbf,bcclr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint)); +{ + SI tmp_tmp; + tmp_tmp = SUBSI (GET_H_SPR (((UINT) 273)), 1); + { + USI opval = tmp_tmp; + sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, ((UINT) 273), opval); + TRACE_RESULT (current_cpu, abuf, "spr", 'x', opval); + } +if (TRUNCQIBI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 1))) { +if (EQSI (FLD (f_ccond), 0)) { +if (NESI (tmp_tmp, 0)) { + { + USI opval = GET_H_SPR (((UINT) 272)); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} else { +if (EQSI (tmp_tmp, 0)) { + { + USI opval = GET_H_SPR (((UINT) 272)); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* bcnclr: bcnclr$pack $ICCi_2,$ccond,$hint */ + +static SEM_PC +SEM_FN_NAME (frvbf,bcnclr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint)); +{ + SI tmp_tmp; + tmp_tmp = SUBSI (GET_H_SPR (((UINT) 273)), 1); + { + USI opval = tmp_tmp; + sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, ((UINT) 273), opval); + TRACE_RESULT (current_cpu, abuf, "spr", 'x', opval); + } +if (NOTBI (TRUNCQIBI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 1)))) { +if (EQSI (FLD (f_ccond), 0)) { +if (NESI (tmp_tmp, 0)) { + { + USI opval = GET_H_SPR (((UINT) 272)); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} else { +if (EQSI (tmp_tmp, 0)) { + { + USI opval = GET_H_SPR (((UINT) 272)); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* bcnlr: bcnlr$pack $ICCi_2,$ccond,$hint */ + +static SEM_PC +SEM_FN_NAME (frvbf,bcnlr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint)); +{ + SI tmp_tmp; + tmp_tmp = SUBSI (GET_H_SPR (((UINT) 273)), 1); + { + USI opval = tmp_tmp; + sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, ((UINT) 273), opval); + TRACE_RESULT (current_cpu, abuf, "spr", 'x', opval); + } +if (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 8), 3))) { +if (EQSI (FLD (f_ccond), 0)) { +if (NESI (tmp_tmp, 0)) { + { + USI opval = GET_H_SPR (((UINT) 272)); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} else { +if (EQSI (tmp_tmp, 0)) { + { + USI opval = GET_H_SPR (((UINT) 272)); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* bcplr: bcplr$pack $ICCi_2,$ccond,$hint */ + +static SEM_PC +SEM_FN_NAME (frvbf,bcplr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint)); +{ + SI tmp_tmp; + tmp_tmp = SUBSI (GET_H_SPR (((UINT) 273)), 1); + { + USI opval = tmp_tmp; + sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, ((UINT) 273), opval); + TRACE_RESULT (current_cpu, abuf, "spr", 'x', opval); + } +if (NOTBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 8), 3)))) { +if (EQSI (FLD (f_ccond), 0)) { +if (NESI (tmp_tmp, 0)) { + { + USI opval = GET_H_SPR (((UINT) 272)); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} else { +if (EQSI (tmp_tmp, 0)) { + { + USI opval = GET_H_SPR (((UINT) 272)); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* bcvlr: bcvlr$pack $ICCi_2,$ccond,$hint */ + +static SEM_PC +SEM_FN_NAME (frvbf,bcvlr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint)); +{ + SI tmp_tmp; + tmp_tmp = SUBSI (GET_H_SPR (((UINT) 273)), 1); + { + USI opval = tmp_tmp; + sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, ((UINT) 273), opval); + TRACE_RESULT (current_cpu, abuf, "spr", 'x', opval); + } +if (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 2), 1))) { +if (EQSI (FLD (f_ccond), 0)) { +if (NESI (tmp_tmp, 0)) { + { + USI opval = GET_H_SPR (((UINT) 272)); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} else { +if (EQSI (tmp_tmp, 0)) { + { + USI opval = GET_H_SPR (((UINT) 272)); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* bcnvlr: bcnvlr$pack $ICCi_2,$ccond,$hint */ + +static SEM_PC +SEM_FN_NAME (frvbf,bcnvlr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint)); +{ + SI tmp_tmp; + tmp_tmp = SUBSI (GET_H_SPR (((UINT) 273)), 1); + { + USI opval = tmp_tmp; + sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, ((UINT) 273), opval); + TRACE_RESULT (current_cpu, abuf, "spr", 'x', opval); + } +if (NOTBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 2), 1)))) { +if (EQSI (FLD (f_ccond), 0)) { +if (NESI (tmp_tmp, 0)) { + { + USI opval = GET_H_SPR (((UINT) 272)); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} else { +if (EQSI (tmp_tmp, 0)) { + { + USI opval = GET_H_SPR (((UINT) 272)); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* fcbralr: fcbralr$pack $ccond$hint_taken */ + +static SEM_PC +SEM_FN_NAME (frvbf,fcbralr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint)); +{ + SI tmp_tmp; + tmp_tmp = SUBSI (GET_H_SPR (((UINT) 273)), 1); + { + USI opval = tmp_tmp; + sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, ((UINT) 273), opval); + TRACE_RESULT (current_cpu, abuf, "spr", 'x', opval); + } +if (EQSI (FLD (f_ccond), 0)) { +if (NESI (tmp_tmp, 0)) { + { + USI opval = GET_H_SPR (((UINT) 272)); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 5); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} else { +if (EQSI (tmp_tmp, 0)) { + { + USI opval = GET_H_SPR (((UINT) 272)); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 5); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* fcbnolr: fcbnolr$pack$hint_not_taken */ + +static SEM_PC +SEM_FN_NAME (frvbf,fcbnolr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint)); +{ + SI tmp_tmp; + tmp_tmp = SUBSI (GET_H_SPR (((UINT) 273)), 1); + { + USI opval = tmp_tmp; + sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, ((UINT) 273), opval); + TRACE_RESULT (current_cpu, abuf, "spr", 'x', opval); + } +((void) 0); /*nop*/ +} +} + + return vpc; +#undef FLD +} + +/* fcbeqlr: fcbeqlr$pack $FCCi_2,$ccond,$hint */ + +static SEM_PC +SEM_FN_NAME (frvbf,fcbeqlr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint)); +{ + SI tmp_tmp; + tmp_tmp = SUBSI (GET_H_SPR (((UINT) 273)), 1); + { + USI opval = tmp_tmp; + sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, ((UINT) 273), opval); + TRACE_RESULT (current_cpu, abuf, "spr", 'x', opval); + } +if (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 8), 3))) { +if (EQSI (FLD (f_ccond), 0)) { +if (NESI (tmp_tmp, 0)) { + { + USI opval = GET_H_SPR (((UINT) 272)); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} else { +if (EQSI (tmp_tmp, 0)) { + { + USI opval = GET_H_SPR (((UINT) 272)); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* fcbnelr: fcbnelr$pack $FCCi_2,$ccond,$hint */ + +static SEM_PC +SEM_FN_NAME (frvbf,fcbnelr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint)); +{ + SI tmp_tmp; + tmp_tmp = SUBSI (GET_H_SPR (((UINT) 273)), 1); + { + USI opval = tmp_tmp; + sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, ((UINT) 273), opval); + TRACE_RESULT (current_cpu, abuf, "spr", 'x', opval); + } +if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 4), 2)), ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 2), 1)), TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 1))))) { +if (EQSI (FLD (f_ccond), 0)) { +if (NESI (tmp_tmp, 0)) { + { + USI opval = GET_H_SPR (((UINT) 272)); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} else { +if (EQSI (tmp_tmp, 0)) { + { + USI opval = GET_H_SPR (((UINT) 272)); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* fcblglr: fcblglr$pack $FCCi_2,$ccond,$hint */ + +static SEM_PC +SEM_FN_NAME (frvbf,fcblglr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint)); +{ + SI tmp_tmp; + tmp_tmp = SUBSI (GET_H_SPR (((UINT) 273)), 1); + { + USI opval = tmp_tmp; + sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, ((UINT) 273), opval); + TRACE_RESULT (current_cpu, abuf, "spr", 'x', opval); + } +if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 4), 2)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 2), 1)))) { +if (EQSI (FLD (f_ccond), 0)) { +if (NESI (tmp_tmp, 0)) { + { + USI opval = GET_H_SPR (((UINT) 272)); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} else { +if (EQSI (tmp_tmp, 0)) { + { + USI opval = GET_H_SPR (((UINT) 272)); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* fcbuelr: fcbuelr$pack $FCCi_2,$ccond,$hint */ + +static SEM_PC +SEM_FN_NAME (frvbf,fcbuelr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint)); +{ + SI tmp_tmp; + tmp_tmp = SUBSI (GET_H_SPR (((UINT) 273)), 1); + { + USI opval = tmp_tmp; + sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, ((UINT) 273), opval); + TRACE_RESULT (current_cpu, abuf, "spr", 'x', opval); + } +if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 8), 3)), TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 1)))) { +if (EQSI (FLD (f_ccond), 0)) { +if (NESI (tmp_tmp, 0)) { + { + USI opval = GET_H_SPR (((UINT) 272)); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} else { +if (EQSI (tmp_tmp, 0)) { + { + USI opval = GET_H_SPR (((UINT) 272)); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* fcbullr: fcbullr$pack $FCCi_2,$ccond,$hint */ + +static SEM_PC +SEM_FN_NAME (frvbf,fcbullr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint)); +{ + SI tmp_tmp; + tmp_tmp = SUBSI (GET_H_SPR (((UINT) 273)), 1); + { + USI opval = tmp_tmp; + sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, ((UINT) 273), opval); + TRACE_RESULT (current_cpu, abuf, "spr", 'x', opval); + } +if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 4), 2)), TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 1)))) { +if (EQSI (FLD (f_ccond), 0)) { +if (NESI (tmp_tmp, 0)) { + { + USI opval = GET_H_SPR (((UINT) 272)); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} else { +if (EQSI (tmp_tmp, 0)) { + { + USI opval = GET_H_SPR (((UINT) 272)); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* fcbgelr: fcbgelr$pack $FCCi_2,$ccond,$hint */ + +static SEM_PC +SEM_FN_NAME (frvbf,fcbgelr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint)); +{ + SI tmp_tmp; + tmp_tmp = SUBSI (GET_H_SPR (((UINT) 273)), 1); + { + USI opval = tmp_tmp; + sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, ((UINT) 273), opval); + TRACE_RESULT (current_cpu, abuf, "spr", 'x', opval); + } +if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 8), 3)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 2), 1)))) { +if (EQSI (FLD (f_ccond), 0)) { +if (NESI (tmp_tmp, 0)) { + { + USI opval = GET_H_SPR (((UINT) 272)); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} else { +if (EQSI (tmp_tmp, 0)) { + { + USI opval = GET_H_SPR (((UINT) 272)); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* fcbltlr: fcbltlr$pack $FCCi_2,$ccond,$hint */ + +static SEM_PC +SEM_FN_NAME (frvbf,fcbltlr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint)); +{ + SI tmp_tmp; + tmp_tmp = SUBSI (GET_H_SPR (((UINT) 273)), 1); + { + USI opval = tmp_tmp; + sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, ((UINT) 273), opval); + TRACE_RESULT (current_cpu, abuf, "spr", 'x', opval); + } +if (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 4), 2))) { +if (EQSI (FLD (f_ccond), 0)) { +if (NESI (tmp_tmp, 0)) { + { + USI opval = GET_H_SPR (((UINT) 272)); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} else { +if (EQSI (tmp_tmp, 0)) { + { + USI opval = GET_H_SPR (((UINT) 272)); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* fcbugelr: fcbugelr$pack $FCCi_2,$ccond,$hint */ + +static SEM_PC +SEM_FN_NAME (frvbf,fcbugelr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint)); +{ + SI tmp_tmp; + tmp_tmp = SUBSI (GET_H_SPR (((UINT) 273)), 1); + { + USI opval = tmp_tmp; + sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, ((UINT) 273), opval); + TRACE_RESULT (current_cpu, abuf, "spr", 'x', opval); + } +if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 8), 3)), ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 2), 1)), TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 1))))) { +if (EQSI (FLD (f_ccond), 0)) { +if (NESI (tmp_tmp, 0)) { + { + USI opval = GET_H_SPR (((UINT) 272)); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} else { +if (EQSI (tmp_tmp, 0)) { + { + USI opval = GET_H_SPR (((UINT) 272)); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* fcbuglr: fcbuglr$pack $FCCi_2,$ccond,$hint */ + +static SEM_PC +SEM_FN_NAME (frvbf,fcbuglr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint)); +{ + SI tmp_tmp; + tmp_tmp = SUBSI (GET_H_SPR (((UINT) 273)), 1); + { + USI opval = tmp_tmp; + sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, ((UINT) 273), opval); + TRACE_RESULT (current_cpu, abuf, "spr", 'x', opval); + } +if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 2), 1)), TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 1)))) { +if (EQSI (FLD (f_ccond), 0)) { +if (NESI (tmp_tmp, 0)) { + { + USI opval = GET_H_SPR (((UINT) 272)); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} else { +if (EQSI (tmp_tmp, 0)) { + { + USI opval = GET_H_SPR (((UINT) 272)); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* fcblelr: fcblelr$pack $FCCi_2,$ccond,$hint */ + +static SEM_PC +SEM_FN_NAME (frvbf,fcblelr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint)); +{ + SI tmp_tmp; + tmp_tmp = SUBSI (GET_H_SPR (((UINT) 273)), 1); + { + USI opval = tmp_tmp; + sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, ((UINT) 273), opval); + TRACE_RESULT (current_cpu, abuf, "spr", 'x', opval); + } +if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 8), 3)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 4), 2)))) { +if (EQSI (FLD (f_ccond), 0)) { +if (NESI (tmp_tmp, 0)) { + { + USI opval = GET_H_SPR (((UINT) 272)); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} else { +if (EQSI (tmp_tmp, 0)) { + { + USI opval = GET_H_SPR (((UINT) 272)); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* fcbgtlr: fcbgtlr$pack $FCCi_2,$ccond,$hint */ + +static SEM_PC +SEM_FN_NAME (frvbf,fcbgtlr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint)); +{ + SI tmp_tmp; + tmp_tmp = SUBSI (GET_H_SPR (((UINT) 273)), 1); + { + USI opval = tmp_tmp; + sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, ((UINT) 273), opval); + TRACE_RESULT (current_cpu, abuf, "spr", 'x', opval); + } +if (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 2), 1))) { +if (EQSI (FLD (f_ccond), 0)) { +if (NESI (tmp_tmp, 0)) { + { + USI opval = GET_H_SPR (((UINT) 272)); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} else { +if (EQSI (tmp_tmp, 0)) { + { + USI opval = GET_H_SPR (((UINT) 272)); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* fcbulelr: fcbulelr$pack $FCCi_2,$ccond,$hint */ + +static SEM_PC +SEM_FN_NAME (frvbf,fcbulelr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint)); +{ + SI tmp_tmp; + tmp_tmp = SUBSI (GET_H_SPR (((UINT) 273)), 1); + { + USI opval = tmp_tmp; + sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, ((UINT) 273), opval); + TRACE_RESULT (current_cpu, abuf, "spr", 'x', opval); + } +if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 8), 3)), ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 4), 2)), TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 1))))) { +if (EQSI (FLD (f_ccond), 0)) { +if (NESI (tmp_tmp, 0)) { + { + USI opval = GET_H_SPR (((UINT) 272)); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} else { +if (EQSI (tmp_tmp, 0)) { + { + USI opval = GET_H_SPR (((UINT) 272)); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* fcbulr: fcbulr$pack $FCCi_2,$ccond,$hint */ + +static SEM_PC +SEM_FN_NAME (frvbf,fcbulr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint)); +{ + SI tmp_tmp; + tmp_tmp = SUBSI (GET_H_SPR (((UINT) 273)), 1); + { + USI opval = tmp_tmp; + sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, ((UINT) 273), opval); + TRACE_RESULT (current_cpu, abuf, "spr", 'x', opval); + } +if (TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 1))) { +if (EQSI (FLD (f_ccond), 0)) { +if (NESI (tmp_tmp, 0)) { + { + USI opval = GET_H_SPR (((UINT) 272)); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} else { +if (EQSI (tmp_tmp, 0)) { + { + USI opval = GET_H_SPR (((UINT) 272)); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* fcbolr: fcbolr$pack $FCCi_2,$ccond,$hint */ + +static SEM_PC +SEM_FN_NAME (frvbf,fcbolr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint)); +{ + SI tmp_tmp; + tmp_tmp = SUBSI (GET_H_SPR (((UINT) 273)), 1); + { + USI opval = tmp_tmp; + sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, ((UINT) 273), opval); + TRACE_RESULT (current_cpu, abuf, "spr", 'x', opval); + } +if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 8), 3)), ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 4), 2)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 2), 1))))) { +if (EQSI (FLD (f_ccond), 0)) { +if (NESI (tmp_tmp, 0)) { + { + USI opval = GET_H_SPR (((UINT) 272)); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} else { +if (EQSI (tmp_tmp, 0)) { + { + USI opval = GET_H_SPR (((UINT) 272)); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* jmpl: jmpl$pack @($GRi,$GRj) */ + +static SEM_PC +SEM_FN_NAME (frvbf,jmpl) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cjmpl.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +if (EQSI (FLD (f_LI), 1)) { +frvbf_set_write_next_vliw_addr_to_LR (current_cpu, 1); +} + { + USI opval = ANDSI (ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))), 0xfffffffc); + sim_queue_pc_write (current_cpu, opval); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +frvbf_model_branch (current_cpu, pc, 2); +} + + return vpc; +#undef FLD +} + +/* calll: calll$pack @($GRi,$GRj) */ + +static SEM_PC +SEM_FN_NAME (frvbf,calll) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cjmpl.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +if (EQSI (FLD (f_LI), 1)) { +frvbf_set_write_next_vliw_addr_to_LR (current_cpu, 1); +} + { + USI opval = ANDSI (ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))), 0xfffffffc); + sim_queue_pc_write (current_cpu, opval); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +frvbf_model_branch (current_cpu, pc, 2); +} + + return vpc; +#undef FLD +} + +/* jmpil: jmpil$pack @($GRi,$s12) */ + +static SEM_PC +SEM_FN_NAME (frvbf,jmpil) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_jmpil.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +if (EQSI (FLD (f_LI), 1)) { +frvbf_set_write_next_vliw_addr_to_LR (current_cpu, 1); +} + { + USI opval = ANDSI (ADDSI (GET_H_GR (FLD (f_GRi)), FLD (f_d12)), 0xfffffffc); + sim_queue_pc_write (current_cpu, opval); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +frvbf_model_branch (current_cpu, pc, 2); +} + + return vpc; +#undef FLD +} + +/* callil: callil$pack @($GRi,$s12) */ + +static SEM_PC +SEM_FN_NAME (frvbf,callil) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_jmpil.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +if (EQSI (FLD (f_LI), 1)) { +frvbf_set_write_next_vliw_addr_to_LR (current_cpu, 1); +} + { + USI opval = ANDSI (ADDSI (GET_H_GR (FLD (f_GRi)), FLD (f_d12)), 0xfffffffc); + sim_queue_pc_write (current_cpu, opval); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +frvbf_model_branch (current_cpu, pc, 2); +} + + return vpc; +#undef FLD +} + +/* call: call$pack $label24 */ + +static SEM_PC +SEM_FN_NAME (frvbf,call) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_call.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_set_write_next_vliw_addr_to_LR (current_cpu, 1); + { + USI opval = FLD (i_label24); + sim_queue_pc_write (current_cpu, opval); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +frvbf_model_branch (current_cpu, pc, 2); +} + + return vpc; +#undef FLD +} + +/* rett: rett$pack $debug */ + +static SEM_PC +SEM_FN_NAME (frvbf,rett) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_rett.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + { + USI opval = frv_rett (current_cpu, pc, FLD (f_debug)); + sim_queue_pc_write (current_cpu, opval); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +frvbf_model_branch (current_cpu, pc, 2); +} + + return vpc; +#undef FLD +} + +/* rei: rei$pack $eir */ + +static SEM_PC +SEM_FN_NAME (frvbf,rei) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + return vpc; +#undef FLD +} + +/* tra: tra$pack $GRi,$GRj */ + +static SEM_PC +SEM_FN_NAME (frvbf,tra) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +if (NEBI (CPU (h_psr_esr), 0)) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +} +} +frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* tno: tno$pack */ + +static SEM_PC +SEM_FN_NAME (frvbf,tno) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + return vpc; +#undef FLD +} + +/* teq: teq$pack $ICCi_2,$GRi,$GRj */ + +static SEM_PC +SEM_FN_NAME (frvbf,teq) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 4), 2))) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +if (NEBI (CPU (h_psr_esr), 0)) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +} +} +frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* tne: tne$pack $ICCi_2,$GRi,$GRj */ + +static SEM_PC +SEM_FN_NAME (frvbf,tne) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (NOTBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 4), 2)))) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +if (NEBI (CPU (h_psr_esr), 0)) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +} +} +frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* tle: tle$pack $ICCi_2,$GRi,$GRj */ + +static SEM_PC +SEM_FN_NAME (frvbf,tle) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 4), 2)), XORBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 8), 3)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 2), 1))))) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +if (NEBI (CPU (h_psr_esr), 0)) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +} +} +frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* tgt: tgt$pack $ICCi_2,$GRi,$GRj */ + +static SEM_PC +SEM_FN_NAME (frvbf,tgt) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (NOTBI (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 4), 2)), XORBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 8), 3)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 2), 1)))))) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +if (NEBI (CPU (h_psr_esr), 0)) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +} +} +frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* tlt: tlt$pack $ICCi_2,$GRi,$GRj */ + +static SEM_PC +SEM_FN_NAME (frvbf,tlt) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (XORBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 8), 3)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 2), 1)))) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +if (NEBI (CPU (h_psr_esr), 0)) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +} +} +frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* tge: tge$pack $ICCi_2,$GRi,$GRj */ + +static SEM_PC +SEM_FN_NAME (frvbf,tge) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (NOTBI (XORBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 8), 3)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 2), 1))))) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +if (NEBI (CPU (h_psr_esr), 0)) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +} +} +frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* tls: tls$pack $ICCi_2,$GRi,$GRj */ + +static SEM_PC +SEM_FN_NAME (frvbf,tls) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (ORIF (TRUNCQIBI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 1)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 4), 2)))) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +if (NEBI (CPU (h_psr_esr), 0)) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +} +} +frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* thi: thi$pack $ICCi_2,$GRi,$GRj */ + +static SEM_PC +SEM_FN_NAME (frvbf,thi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (NOTBI (ORIF (TRUNCQIBI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 1)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 4), 2))))) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +if (NEBI (CPU (h_psr_esr), 0)) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +} +} +frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* tc: tc$pack $ICCi_2,$GRi,$GRj */ + +static SEM_PC +SEM_FN_NAME (frvbf,tc) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (TRUNCQIBI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 1))) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +if (NEBI (CPU (h_psr_esr), 0)) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +} +} +frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* tnc: tnc$pack $ICCi_2,$GRi,$GRj */ + +static SEM_PC +SEM_FN_NAME (frvbf,tnc) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (NOTBI (TRUNCQIBI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 1)))) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +if (NEBI (CPU (h_psr_esr), 0)) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +} +} +frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* tn: tn$pack $ICCi_2,$GRi,$GRj */ + +static SEM_PC +SEM_FN_NAME (frvbf,tn) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 8), 3))) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +if (NEBI (CPU (h_psr_esr), 0)) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +} +} +frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* tp: tp$pack $ICCi_2,$GRi,$GRj */ + +static SEM_PC +SEM_FN_NAME (frvbf,tp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (NOTBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 8), 3)))) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +if (NEBI (CPU (h_psr_esr), 0)) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +} +} +frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* tv: tv$pack $ICCi_2,$GRi,$GRj */ + +static SEM_PC +SEM_FN_NAME (frvbf,tv) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 2), 1))) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +if (NEBI (CPU (h_psr_esr), 0)) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +} +} +frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* tnv: tnv$pack $ICCi_2,$GRi,$GRj */ + +static SEM_PC +SEM_FN_NAME (frvbf,tnv) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (NOTBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 2), 1)))) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +if (NEBI (CPU (h_psr_esr), 0)) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +} +} +frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* ftra: ftra$pack $GRi,$GRj */ + +static SEM_PC +SEM_FN_NAME (frvbf,ftra) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +if (NEBI (CPU (h_psr_esr), 0)) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +} +} +frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* ftno: ftno$pack */ + +static SEM_PC +SEM_FN_NAME (frvbf,ftno) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + return vpc; +#undef FLD +} + +/* ftne: ftne$pack $FCCi_2,$GRi,$GRj */ + +static SEM_PC +SEM_FN_NAME (frvbf,ftne) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 4), 2)), ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 2), 1)), TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 1))))) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +if (NEBI (CPU (h_psr_esr), 0)) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +} +} +frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* fteq: fteq$pack $FCCi_2,$GRi,$GRj */ + +static SEM_PC +SEM_FN_NAME (frvbf,fteq) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 8), 3))) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +if (NEBI (CPU (h_psr_esr), 0)) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +} +} +frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* ftlg: ftlg$pack $FCCi_2,$GRi,$GRj */ + +static SEM_PC +SEM_FN_NAME (frvbf,ftlg) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 4), 2)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 2), 1)))) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +if (NEBI (CPU (h_psr_esr), 0)) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +} +} +frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* ftue: ftue$pack $FCCi_2,$GRi,$GRj */ + +static SEM_PC +SEM_FN_NAME (frvbf,ftue) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 8), 3)), TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 1)))) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +if (NEBI (CPU (h_psr_esr), 0)) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +} +} +frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* ftul: ftul$pack $FCCi_2,$GRi,$GRj */ + +static SEM_PC +SEM_FN_NAME (frvbf,ftul) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 4), 2)), TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 1)))) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +if (NEBI (CPU (h_psr_esr), 0)) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +} +} +frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* ftge: ftge$pack $FCCi_2,$GRi,$GRj */ + +static SEM_PC +SEM_FN_NAME (frvbf,ftge) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 8), 3)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 2), 1)))) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +if (NEBI (CPU (h_psr_esr), 0)) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +} +} +frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* ftlt: ftlt$pack $FCCi_2,$GRi,$GRj */ + +static SEM_PC +SEM_FN_NAME (frvbf,ftlt) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 4), 2))) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +if (NEBI (CPU (h_psr_esr), 0)) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +} +} +frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* ftuge: ftuge$pack $FCCi_2,$GRi,$GRj */ + +static SEM_PC +SEM_FN_NAME (frvbf,ftuge) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 8), 3)), ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 2), 1)), TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 1))))) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +if (NEBI (CPU (h_psr_esr), 0)) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +} +} +frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* ftug: ftug$pack $FCCi_2,$GRi,$GRj */ + +static SEM_PC +SEM_FN_NAME (frvbf,ftug) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 2), 1)), TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 1)))) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +if (NEBI (CPU (h_psr_esr), 0)) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +} +} +frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* ftle: ftle$pack $FCCi_2,$GRi,$GRj */ + +static SEM_PC +SEM_FN_NAME (frvbf,ftle) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 8), 3)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 4), 2)))) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +if (NEBI (CPU (h_psr_esr), 0)) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +} +} +frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* ftgt: ftgt$pack $FCCi_2,$GRi,$GRj */ + +static SEM_PC +SEM_FN_NAME (frvbf,ftgt) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 2), 1))) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +if (NEBI (CPU (h_psr_esr), 0)) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +} +} +frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* ftule: ftule$pack $FCCi_2,$GRi,$GRj */ + +static SEM_PC +SEM_FN_NAME (frvbf,ftule) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 8), 3)), ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 4), 2)), TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 1))))) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +if (NEBI (CPU (h_psr_esr), 0)) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +} +} +frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* ftu: ftu$pack $FCCi_2,$GRi,$GRj */ + +static SEM_PC +SEM_FN_NAME (frvbf,ftu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 1))) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +if (NEBI (CPU (h_psr_esr), 0)) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +} +} +frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* fto: fto$pack $FCCi_2,$GRi,$GRj */ + +static SEM_PC +SEM_FN_NAME (frvbf,fto) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 8), 3)), ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 4), 2)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 2), 1))))) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +if (NEBI (CPU (h_psr_esr), 0)) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +} +} +frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* tira: tira$pack $GRi,$s12 */ + +static SEM_PC +SEM_FN_NAME (frvbf,tira) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +if (NEBI (CPU (h_psr_esr), 0)) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +} +} +frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), FLD (f_d12)); +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* tino: tino$pack */ + +static SEM_PC +SEM_FN_NAME (frvbf,tino) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + return vpc; +#undef FLD +} + +/* tieq: tieq$pack $ICCi_2,$GRi,$s12 */ + +static SEM_PC +SEM_FN_NAME (frvbf,tieq) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 4), 2))) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +if (NEBI (CPU (h_psr_esr), 0)) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +} +} +frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), FLD (f_d12)); +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* tine: tine$pack $ICCi_2,$GRi,$s12 */ + +static SEM_PC +SEM_FN_NAME (frvbf,tine) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (NOTBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 4), 2)))) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +if (NEBI (CPU (h_psr_esr), 0)) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +} +} +frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), FLD (f_d12)); +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* tile: tile$pack $ICCi_2,$GRi,$s12 */ + +static SEM_PC +SEM_FN_NAME (frvbf,tile) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 4), 2)), XORBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 8), 3)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 2), 1))))) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +if (NEBI (CPU (h_psr_esr), 0)) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +} +} +frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), FLD (f_d12)); +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* tigt: tigt$pack $ICCi_2,$GRi,$s12 */ + +static SEM_PC +SEM_FN_NAME (frvbf,tigt) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (NOTBI (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 4), 2)), XORBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 8), 3)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 2), 1)))))) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +if (NEBI (CPU (h_psr_esr), 0)) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +} +} +frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), FLD (f_d12)); +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* tilt: tilt$pack $ICCi_2,$GRi,$s12 */ + +static SEM_PC +SEM_FN_NAME (frvbf,tilt) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (XORBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 8), 3)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 2), 1)))) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +if (NEBI (CPU (h_psr_esr), 0)) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +} +} +frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), FLD (f_d12)); +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* tige: tige$pack $ICCi_2,$GRi,$s12 */ + +static SEM_PC +SEM_FN_NAME (frvbf,tige) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (NOTBI (XORBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 8), 3)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 2), 1))))) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +if (NEBI (CPU (h_psr_esr), 0)) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +} +} +frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), FLD (f_d12)); +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* tils: tils$pack $ICCi_2,$GRi,$s12 */ + +static SEM_PC +SEM_FN_NAME (frvbf,tils) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (ORIF (TRUNCQIBI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 1)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 4), 2)))) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +if (NEBI (CPU (h_psr_esr), 0)) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +} +} +frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), FLD (f_d12)); +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* tihi: tihi$pack $ICCi_2,$GRi,$s12 */ + +static SEM_PC +SEM_FN_NAME (frvbf,tihi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (NOTBI (ORIF (TRUNCQIBI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 1)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 4), 2))))) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +if (NEBI (CPU (h_psr_esr), 0)) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +} +} +frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), FLD (f_d12)); +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* tic: tic$pack $ICCi_2,$GRi,$s12 */ + +static SEM_PC +SEM_FN_NAME (frvbf,tic) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (TRUNCQIBI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 1))) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +if (NEBI (CPU (h_psr_esr), 0)) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +} +} +frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), FLD (f_d12)); +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* tinc: tinc$pack $ICCi_2,$GRi,$s12 */ + +static SEM_PC +SEM_FN_NAME (frvbf,tinc) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (NOTBI (TRUNCQIBI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 1)))) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +if (NEBI (CPU (h_psr_esr), 0)) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +} +} +frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), FLD (f_d12)); +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* tin: tin$pack $ICCi_2,$GRi,$s12 */ + +static SEM_PC +SEM_FN_NAME (frvbf,tin) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 8), 3))) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +if (NEBI (CPU (h_psr_esr), 0)) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +} +} +frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), FLD (f_d12)); +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* tip: tip$pack $ICCi_2,$GRi,$s12 */ + +static SEM_PC +SEM_FN_NAME (frvbf,tip) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (NOTBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 8), 3)))) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +if (NEBI (CPU (h_psr_esr), 0)) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +} +} +frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), FLD (f_d12)); +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* tiv: tiv$pack $ICCi_2,$GRi,$s12 */ + +static SEM_PC +SEM_FN_NAME (frvbf,tiv) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 2), 1))) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +if (NEBI (CPU (h_psr_esr), 0)) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +} +} +frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), FLD (f_d12)); +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* tinv: tinv$pack $ICCi_2,$GRi,$s12 */ + +static SEM_PC +SEM_FN_NAME (frvbf,tinv) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (NOTBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 2), 1)))) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +if (NEBI (CPU (h_psr_esr), 0)) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +} +} +frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), FLD (f_d12)); +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* ftira: ftira$pack $GRi,$s12 */ + +static SEM_PC +SEM_FN_NAME (frvbf,ftira) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +if (NEBI (CPU (h_psr_esr), 0)) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +} +} +frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), FLD (f_d12)); +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* ftino: ftino$pack */ + +static SEM_PC +SEM_FN_NAME (frvbf,ftino) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + return vpc; +#undef FLD +} + +/* ftine: ftine$pack $FCCi_2,$GRi,$s12 */ + +static SEM_PC +SEM_FN_NAME (frvbf,ftine) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 4), 2)), ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 2), 1)), TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 1))))) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +if (NEBI (CPU (h_psr_esr), 0)) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +} +} +frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), FLD (f_d12)); +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* ftieq: ftieq$pack $FCCi_2,$GRi,$s12 */ + +static SEM_PC +SEM_FN_NAME (frvbf,ftieq) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 8), 3))) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +if (NEBI (CPU (h_psr_esr), 0)) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +} +} +frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), FLD (f_d12)); +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* ftilg: ftilg$pack $FCCi_2,$GRi,$s12 */ + +static SEM_PC +SEM_FN_NAME (frvbf,ftilg) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 4), 2)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 2), 1)))) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +if (NEBI (CPU (h_psr_esr), 0)) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +} +} +frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), FLD (f_d12)); +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* ftiue: ftiue$pack $FCCi_2,$GRi,$s12 */ + +static SEM_PC +SEM_FN_NAME (frvbf,ftiue) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 8), 3)), TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 1)))) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +if (NEBI (CPU (h_psr_esr), 0)) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +} +} +frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), FLD (f_d12)); +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* ftiul: ftiul$pack $FCCi_2,$GRi,$s12 */ + +static SEM_PC +SEM_FN_NAME (frvbf,ftiul) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 4), 2)), TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 1)))) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +if (NEBI (CPU (h_psr_esr), 0)) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +} +} +frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), FLD (f_d12)); +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* ftige: ftige$pack $FCCi_2,$GRi,$s12 */ + +static SEM_PC +SEM_FN_NAME (frvbf,ftige) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 8), 3)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 2), 1)))) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +if (NEBI (CPU (h_psr_esr), 0)) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +} +} +frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), FLD (f_d12)); +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* ftilt: ftilt$pack $FCCi_2,$GRi,$s12 */ + +static SEM_PC +SEM_FN_NAME (frvbf,ftilt) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 4), 2))) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +if (NEBI (CPU (h_psr_esr), 0)) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +} +} +frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), FLD (f_d12)); +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* ftiuge: ftiuge$pack $FCCi_2,$GRi,$s12 */ + +static SEM_PC +SEM_FN_NAME (frvbf,ftiuge) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 8), 3)), ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 2), 1)), TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 1))))) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +if (NEBI (CPU (h_psr_esr), 0)) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +} +} +frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), FLD (f_d12)); +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* ftiug: ftiug$pack $FCCi_2,$GRi,$s12 */ + +static SEM_PC +SEM_FN_NAME (frvbf,ftiug) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 2), 1)), TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 1)))) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +if (NEBI (CPU (h_psr_esr), 0)) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +} +} +frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), FLD (f_d12)); +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* ftile: ftile$pack $FCCi_2,$GRi,$s12 */ + +static SEM_PC +SEM_FN_NAME (frvbf,ftile) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 8), 3)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 4), 2)))) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +if (NEBI (CPU (h_psr_esr), 0)) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +} +} +frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), FLD (f_d12)); +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* ftigt: ftigt$pack $FCCi_2,$GRi,$s12 */ + +static SEM_PC +SEM_FN_NAME (frvbf,ftigt) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 2), 1))) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +if (NEBI (CPU (h_psr_esr), 0)) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +} +} +frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), FLD (f_d12)); +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* ftiule: ftiule$pack $FCCi_2,$GRi,$s12 */ + +static SEM_PC +SEM_FN_NAME (frvbf,ftiule) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 8), 3)), ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 4), 2)), TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 1))))) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +if (NEBI (CPU (h_psr_esr), 0)) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +} +} +frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), FLD (f_d12)); +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* ftiu: ftiu$pack $FCCi_2,$GRi,$s12 */ + +static SEM_PC +SEM_FN_NAME (frvbf,ftiu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 1))) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +if (NEBI (CPU (h_psr_esr), 0)) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +} +} +frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), FLD (f_d12)); +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* ftio: ftio$pack $FCCi_2,$GRi,$s12 */ + +static SEM_PC +SEM_FN_NAME (frvbf,ftio) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 8), 3)), ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 4), 2)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 2), 1))))) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +if (NEBI (CPU (h_psr_esr), 0)) { +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +} +} +frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), FLD (f_d12)); +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* break: break$pack */ + +static SEM_PC +SEM_FN_NAME (frvbf,break) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_break.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +; /*clobber*/ +frv_break (current_cpu); +} + + return vpc; +#undef FLD +} + +/* mtrap: mtrap$pack */ + +static SEM_PC +SEM_FN_NAME (frvbf,mtrap) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +frv_mtrap (current_cpu); + + return vpc; +#undef FLD +} + +/* andcr: andcr$pack $CRi,$CRj,$CRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,andcr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_andcr.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + UQI opval = frvbf_cr_logic (current_cpu, 0, CPU (h_cccr[FLD (f_CRi)]), CPU (h_cccr[FLD (f_CRj)])); + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRk)]), opval); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* orcr: orcr$pack $CRi,$CRj,$CRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,orcr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_andcr.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + UQI opval = frvbf_cr_logic (current_cpu, 1, CPU (h_cccr[FLD (f_CRi)]), CPU (h_cccr[FLD (f_CRj)])); + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRk)]), opval); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* xorcr: xorcr$pack $CRi,$CRj,$CRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,xorcr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_andcr.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + UQI opval = frvbf_cr_logic (current_cpu, 2, CPU (h_cccr[FLD (f_CRi)]), CPU (h_cccr[FLD (f_CRj)])); + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRk)]), opval); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* nandcr: nandcr$pack $CRi,$CRj,$CRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,nandcr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_andcr.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + UQI opval = frvbf_cr_logic (current_cpu, 3, CPU (h_cccr[FLD (f_CRi)]), CPU (h_cccr[FLD (f_CRj)])); + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRk)]), opval); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* norcr: norcr$pack $CRi,$CRj,$CRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,norcr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_andcr.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + UQI opval = frvbf_cr_logic (current_cpu, 4, CPU (h_cccr[FLD (f_CRi)]), CPU (h_cccr[FLD (f_CRj)])); + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRk)]), opval); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* andncr: andncr$pack $CRi,$CRj,$CRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,andncr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_andcr.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + UQI opval = frvbf_cr_logic (current_cpu, 5, CPU (h_cccr[FLD (f_CRi)]), CPU (h_cccr[FLD (f_CRj)])); + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRk)]), opval); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* orncr: orncr$pack $CRi,$CRj,$CRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,orncr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_andcr.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + UQI opval = frvbf_cr_logic (current_cpu, 6, CPU (h_cccr[FLD (f_CRi)]), CPU (h_cccr[FLD (f_CRj)])); + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRk)]), opval); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* nandncr: nandncr$pack $CRi,$CRj,$CRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,nandncr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_andcr.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + UQI opval = frvbf_cr_logic (current_cpu, 7, CPU (h_cccr[FLD (f_CRi)]), CPU (h_cccr[FLD (f_CRj)])); + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRk)]), opval); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* norncr: norncr$pack $CRi,$CRj,$CRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,norncr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_andcr.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + UQI opval = frvbf_cr_logic (current_cpu, 8, CPU (h_cccr[FLD (f_CRi)]), CPU (h_cccr[FLD (f_CRj)])); + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRk)]), opval); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* notcr: notcr$pack $CRj,$CRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,notcr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_andcr.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + UQI opval = XORQI (CPU (h_cccr[FLD (f_CRj)]), 1); + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRk)]), opval); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* ckra: ckra$pack $CRj_int */ + +static SEM_PC +SEM_FN_NAME (frvbf,ckra) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + UQI opval = 3; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* ckno: ckno$pack $CRj_int */ + +static SEM_PC +SEM_FN_NAME (frvbf,ckno) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + UQI opval = 2; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* ckeq: ckeq$pack $ICCi_3,$CRj_int */ + +static SEM_PC +SEM_FN_NAME (frvbf,ckeq) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_3)]), 4), 2))) { + { + UQI opval = 3; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval); + written |= (1 << 1); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} else { + { + UQI opval = 2; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval); + written |= (1 << 1); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* ckne: ckne$pack $ICCi_3,$CRj_int */ + +static SEM_PC +SEM_FN_NAME (frvbf,ckne) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (NOTBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_3)]), 4), 2)))) { + { + UQI opval = 3; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval); + written |= (1 << 1); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} else { + { + UQI opval = 2; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval); + written |= (1 << 1); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* ckle: ckle$pack $ICCi_3,$CRj_int */ + +static SEM_PC +SEM_FN_NAME (frvbf,ckle) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_3)]), 4), 2)), XORBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_3)]), 8), 3)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_3)]), 2), 1))))) { + { + UQI opval = 3; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval); + written |= (1 << 1); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} else { + { + UQI opval = 2; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval); + written |= (1 << 1); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* ckgt: ckgt$pack $ICCi_3,$CRj_int */ + +static SEM_PC +SEM_FN_NAME (frvbf,ckgt) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (NOTBI (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_3)]), 4), 2)), XORBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_3)]), 8), 3)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_3)]), 2), 1)))))) { + { + UQI opval = 3; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval); + written |= (1 << 1); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} else { + { + UQI opval = 2; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval); + written |= (1 << 1); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cklt: cklt$pack $ICCi_3,$CRj_int */ + +static SEM_PC +SEM_FN_NAME (frvbf,cklt) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (XORBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_3)]), 8), 3)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_3)]), 2), 1)))) { + { + UQI opval = 3; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval); + written |= (1 << 1); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} else { + { + UQI opval = 2; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval); + written |= (1 << 1); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* ckge: ckge$pack $ICCi_3,$CRj_int */ + +static SEM_PC +SEM_FN_NAME (frvbf,ckge) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (NOTBI (XORBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_3)]), 8), 3)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_3)]), 2), 1))))) { + { + UQI opval = 3; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval); + written |= (1 << 1); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} else { + { + UQI opval = 2; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval); + written |= (1 << 1); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* ckls: ckls$pack $ICCi_3,$CRj_int */ + +static SEM_PC +SEM_FN_NAME (frvbf,ckls) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (ORIF (TRUNCQIBI (ANDQI (CPU (h_iccr[FLD (f_ICCi_3)]), 1)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_3)]), 4), 2)))) { + { + UQI opval = 3; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval); + written |= (1 << 1); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} else { + { + UQI opval = 2; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval); + written |= (1 << 1); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* ckhi: ckhi$pack $ICCi_3,$CRj_int */ + +static SEM_PC +SEM_FN_NAME (frvbf,ckhi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (NOTBI (ORIF (TRUNCQIBI (ANDQI (CPU (h_iccr[FLD (f_ICCi_3)]), 1)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_3)]), 4), 2))))) { + { + UQI opval = 3; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval); + written |= (1 << 1); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} else { + { + UQI opval = 2; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval); + written |= (1 << 1); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* ckc: ckc$pack $ICCi_3,$CRj_int */ + +static SEM_PC +SEM_FN_NAME (frvbf,ckc) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (TRUNCQIBI (ANDQI (CPU (h_iccr[FLD (f_ICCi_3)]), 1))) { + { + UQI opval = 3; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval); + written |= (1 << 1); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} else { + { + UQI opval = 2; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval); + written |= (1 << 1); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cknc: cknc$pack $ICCi_3,$CRj_int */ + +static SEM_PC +SEM_FN_NAME (frvbf,cknc) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (NOTBI (TRUNCQIBI (ANDQI (CPU (h_iccr[FLD (f_ICCi_3)]), 1)))) { + { + UQI opval = 3; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval); + written |= (1 << 1); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} else { + { + UQI opval = 2; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval); + written |= (1 << 1); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* ckn: ckn$pack $ICCi_3,$CRj_int */ + +static SEM_PC +SEM_FN_NAME (frvbf,ckn) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_3)]), 8), 3))) { + { + UQI opval = 3; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval); + written |= (1 << 1); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} else { + { + UQI opval = 2; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval); + written |= (1 << 1); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* ckp: ckp$pack $ICCi_3,$CRj_int */ + +static SEM_PC +SEM_FN_NAME (frvbf,ckp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (NOTBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_3)]), 8), 3)))) { + { + UQI opval = 3; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval); + written |= (1 << 1); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} else { + { + UQI opval = 2; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval); + written |= (1 << 1); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* ckv: ckv$pack $ICCi_3,$CRj_int */ + +static SEM_PC +SEM_FN_NAME (frvbf,ckv) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_3)]), 2), 1))) { + { + UQI opval = 3; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval); + written |= (1 << 1); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} else { + { + UQI opval = 2; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval); + written |= (1 << 1); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cknv: cknv$pack $ICCi_3,$CRj_int */ + +static SEM_PC +SEM_FN_NAME (frvbf,cknv) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (NOTBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_3)]), 2), 1)))) { + { + UQI opval = 3; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval); + written |= (1 << 1); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} else { + { + UQI opval = 2; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval); + written |= (1 << 1); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* fckra: fckra$pack $CRj_float */ + +static SEM_PC +SEM_FN_NAME (frvbf,fckra) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + UQI opval = 3; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* fckno: fckno$pack $CRj_float */ + +static SEM_PC +SEM_FN_NAME (frvbf,fckno) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + UQI opval = 2; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* fckne: fckne$pack $FCCi_3,$CRj_float */ + +static SEM_PC +SEM_FN_NAME (frvbf,fckne) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 4), 2)), ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 2), 1)), TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 1))))) { + { + UQI opval = 3; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval); + written |= (1 << 1); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} else { + { + UQI opval = 2; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval); + written |= (1 << 1); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* fckeq: fckeq$pack $FCCi_3,$CRj_float */ + +static SEM_PC +SEM_FN_NAME (frvbf,fckeq) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 8), 3))) { + { + UQI opval = 3; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval); + written |= (1 << 1); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} else { + { + UQI opval = 2; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval); + written |= (1 << 1); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* fcklg: fcklg$pack $FCCi_3,$CRj_float */ + +static SEM_PC +SEM_FN_NAME (frvbf,fcklg) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 4), 2)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 2), 1)))) { + { + UQI opval = 3; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval); + written |= (1 << 1); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} else { + { + UQI opval = 2; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval); + written |= (1 << 1); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* fckue: fckue$pack $FCCi_3,$CRj_float */ + +static SEM_PC +SEM_FN_NAME (frvbf,fckue) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 8), 3)), TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 1)))) { + { + UQI opval = 3; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval); + written |= (1 << 1); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} else { + { + UQI opval = 2; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval); + written |= (1 << 1); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* fckul: fckul$pack $FCCi_3,$CRj_float */ + +static SEM_PC +SEM_FN_NAME (frvbf,fckul) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 4), 2)), TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 1)))) { + { + UQI opval = 3; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval); + written |= (1 << 1); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} else { + { + UQI opval = 2; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval); + written |= (1 << 1); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* fckge: fckge$pack $FCCi_3,$CRj_float */ + +static SEM_PC +SEM_FN_NAME (frvbf,fckge) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 8), 3)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 2), 1)))) { + { + UQI opval = 3; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval); + written |= (1 << 1); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} else { + { + UQI opval = 2; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval); + written |= (1 << 1); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* fcklt: fcklt$pack $FCCi_3,$CRj_float */ + +static SEM_PC +SEM_FN_NAME (frvbf,fcklt) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 4), 2))) { + { + UQI opval = 3; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval); + written |= (1 << 1); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} else { + { + UQI opval = 2; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval); + written |= (1 << 1); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* fckuge: fckuge$pack $FCCi_3,$CRj_float */ + +static SEM_PC +SEM_FN_NAME (frvbf,fckuge) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 8), 3)), ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 2), 1)), TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 1))))) { + { + UQI opval = 3; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval); + written |= (1 << 1); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} else { + { + UQI opval = 2; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval); + written |= (1 << 1); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* fckug: fckug$pack $FCCi_3,$CRj_float */ + +static SEM_PC +SEM_FN_NAME (frvbf,fckug) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 2), 1)), TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 1)))) { + { + UQI opval = 3; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval); + written |= (1 << 1); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} else { + { + UQI opval = 2; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval); + written |= (1 << 1); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* fckle: fckle$pack $FCCi_3,$CRj_float */ + +static SEM_PC +SEM_FN_NAME (frvbf,fckle) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 8), 3)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 4), 2)))) { + { + UQI opval = 3; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval); + written |= (1 << 1); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} else { + { + UQI opval = 2; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval); + written |= (1 << 1); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* fckgt: fckgt$pack $FCCi_3,$CRj_float */ + +static SEM_PC +SEM_FN_NAME (frvbf,fckgt) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 2), 1))) { + { + UQI opval = 3; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval); + written |= (1 << 1); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} else { + { + UQI opval = 2; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval); + written |= (1 << 1); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* fckule: fckule$pack $FCCi_3,$CRj_float */ + +static SEM_PC +SEM_FN_NAME (frvbf,fckule) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 8), 3)), ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 4), 2)), TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 1))))) { + { + UQI opval = 3; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval); + written |= (1 << 1); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} else { + { + UQI opval = 2; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval); + written |= (1 << 1); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* fcku: fcku$pack $FCCi_3,$CRj_float */ + +static SEM_PC +SEM_FN_NAME (frvbf,fcku) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 1))) { + { + UQI opval = 3; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval); + written |= (1 << 1); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} else { + { + UQI opval = 2; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval); + written |= (1 << 1); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* fcko: fcko$pack $FCCi_3,$CRj_float */ + +static SEM_PC +SEM_FN_NAME (frvbf,fcko) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 8), 3)), ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 4), 2)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 2), 1))))) { + { + UQI opval = 3; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval); + written |= (1 << 1); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} else { + { + UQI opval = 2; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval); + written |= (1 << 1); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cckra: cckra$pack $CRj_int,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cckra) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { + { + UQI opval = 3; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} else { + { + UQI opval = 0; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cckno: cckno$pack $CRj_int,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cckno) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { + { + UQI opval = 2; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} else { + { + UQI opval = 0; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cckeq: cckeq$pack $ICCi_3,$CRj_int,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cckeq) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +if (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_3)]), 4), 2))) { + { + UQI opval = 3; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} else { + { + UQI opval = 2; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} +} else { + { + UQI opval = 0; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cckne: cckne$pack $ICCi_3,$CRj_int,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cckne) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +if (NOTBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_3)]), 4), 2)))) { + { + UQI opval = 3; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} else { + { + UQI opval = 2; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} +} else { + { + UQI opval = 0; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cckle: cckle$pack $ICCi_3,$CRj_int,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cckle) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_3)]), 4), 2)), XORBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_3)]), 8), 3)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_3)]), 2), 1))))) { + { + UQI opval = 3; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} else { + { + UQI opval = 2; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} +} else { + { + UQI opval = 0; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cckgt: cckgt$pack $ICCi_3,$CRj_int,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cckgt) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +if (NOTBI (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_3)]), 4), 2)), XORBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_3)]), 8), 3)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_3)]), 2), 1)))))) { + { + UQI opval = 3; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} else { + { + UQI opval = 2; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} +} else { + { + UQI opval = 0; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* ccklt: ccklt$pack $ICCi_3,$CRj_int,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,ccklt) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +if (XORBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_3)]), 8), 3)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_3)]), 2), 1)))) { + { + UQI opval = 3; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} else { + { + UQI opval = 2; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} +} else { + { + UQI opval = 0; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cckge: cckge$pack $ICCi_3,$CRj_int,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cckge) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +if (NOTBI (XORBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_3)]), 8), 3)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_3)]), 2), 1))))) { + { + UQI opval = 3; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} else { + { + UQI opval = 2; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} +} else { + { + UQI opval = 0; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cckls: cckls$pack $ICCi_3,$CRj_int,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cckls) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +if (ORIF (TRUNCQIBI (ANDQI (CPU (h_iccr[FLD (f_ICCi_3)]), 1)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_3)]), 4), 2)))) { + { + UQI opval = 3; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} else { + { + UQI opval = 2; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} +} else { + { + UQI opval = 0; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cckhi: cckhi$pack $ICCi_3,$CRj_int,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cckhi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +if (NOTBI (ORIF (TRUNCQIBI (ANDQI (CPU (h_iccr[FLD (f_ICCi_3)]), 1)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_3)]), 4), 2))))) { + { + UQI opval = 3; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} else { + { + UQI opval = 2; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} +} else { + { + UQI opval = 0; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cckc: cckc$pack $ICCi_3,$CRj_int,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cckc) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +if (TRUNCQIBI (ANDQI (CPU (h_iccr[FLD (f_ICCi_3)]), 1))) { + { + UQI opval = 3; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} else { + { + UQI opval = 2; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} +} else { + { + UQI opval = 0; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* ccknc: ccknc$pack $ICCi_3,$CRj_int,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,ccknc) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +if (NOTBI (TRUNCQIBI (ANDQI (CPU (h_iccr[FLD (f_ICCi_3)]), 1)))) { + { + UQI opval = 3; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} else { + { + UQI opval = 2; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} +} else { + { + UQI opval = 0; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cckn: cckn$pack $ICCi_3,$CRj_int,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cckn) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +if (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_3)]), 8), 3))) { + { + UQI opval = 3; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} else { + { + UQI opval = 2; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} +} else { + { + UQI opval = 0; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cckp: cckp$pack $ICCi_3,$CRj_int,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cckp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +if (NOTBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_3)]), 8), 3)))) { + { + UQI opval = 3; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} else { + { + UQI opval = 2; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} +} else { + { + UQI opval = 0; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cckv: cckv$pack $ICCi_3,$CRj_int,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cckv) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +if (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_3)]), 2), 1))) { + { + UQI opval = 3; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} else { + { + UQI opval = 2; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} +} else { + { + UQI opval = 0; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* ccknv: ccknv$pack $ICCi_3,$CRj_int,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,ccknv) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +if (NOTBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_3)]), 2), 1)))) { + { + UQI opval = 3; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} else { + { + UQI opval = 2; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} +} else { + { + UQI opval = 0; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cfckra: cfckra$pack $CRj_float,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cfckra) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { + { + UQI opval = 3; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} else { + { + UQI opval = 0; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cfckno: cfckno$pack $CRj_float,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cfckno) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { + { + UQI opval = 2; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} else { + { + UQI opval = 0; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cfckne: cfckne$pack $FCCi_3,$CRj_float,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cfckne) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 4), 2)), ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 2), 1)), TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 1))))) { + { + UQI opval = 3; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} else { + { + UQI opval = 2; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} +} else { + { + UQI opval = 0; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cfckeq: cfckeq$pack $FCCi_3,$CRj_float,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cfckeq) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +if (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 8), 3))) { + { + UQI opval = 3; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} else { + { + UQI opval = 2; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} +} else { + { + UQI opval = 0; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cfcklg: cfcklg$pack $FCCi_3,$CRj_float,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cfcklg) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 4), 2)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 2), 1)))) { + { + UQI opval = 3; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} else { + { + UQI opval = 2; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} +} else { + { + UQI opval = 0; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cfckue: cfckue$pack $FCCi_3,$CRj_float,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cfckue) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 8), 3)), TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 1)))) { + { + UQI opval = 3; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} else { + { + UQI opval = 2; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} +} else { + { + UQI opval = 0; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cfckul: cfckul$pack $FCCi_3,$CRj_float,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cfckul) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 4), 2)), TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 1)))) { + { + UQI opval = 3; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} else { + { + UQI opval = 2; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} +} else { + { + UQI opval = 0; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cfckge: cfckge$pack $FCCi_3,$CRj_float,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cfckge) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 8), 3)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 2), 1)))) { + { + UQI opval = 3; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} else { + { + UQI opval = 2; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} +} else { + { + UQI opval = 0; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cfcklt: cfcklt$pack $FCCi_3,$CRj_float,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cfcklt) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +if (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 4), 2))) { + { + UQI opval = 3; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} else { + { + UQI opval = 2; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} +} else { + { + UQI opval = 0; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cfckuge: cfckuge$pack $FCCi_3,$CRj_float,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cfckuge) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 8), 3)), ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 2), 1)), TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 1))))) { + { + UQI opval = 3; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} else { + { + UQI opval = 2; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} +} else { + { + UQI opval = 0; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cfckug: cfckug$pack $FCCi_3,$CRj_float,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cfckug) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 2), 1)), TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 1)))) { + { + UQI opval = 3; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} else { + { + UQI opval = 2; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} +} else { + { + UQI opval = 0; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cfckle: cfckle$pack $FCCi_3,$CRj_float,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cfckle) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 8), 3)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 4), 2)))) { + { + UQI opval = 3; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} else { + { + UQI opval = 2; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} +} else { + { + UQI opval = 0; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cfckgt: cfckgt$pack $FCCi_3,$CRj_float,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cfckgt) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +if (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 2), 1))) { + { + UQI opval = 3; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} else { + { + UQI opval = 2; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} +} else { + { + UQI opval = 0; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cfckule: cfckule$pack $FCCi_3,$CRj_float,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cfckule) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 8), 3)), ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 4), 2)), TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 1))))) { + { + UQI opval = 3; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} else { + { + UQI opval = 2; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} +} else { + { + UQI opval = 0; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cfcku: cfcku$pack $FCCi_3,$CRj_float,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cfcku) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +if (TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 1))) { + { + UQI opval = 3; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} else { + { + UQI opval = 2; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} +} else { + { + UQI opval = 0; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cfcko: cfcko$pack $FCCi_3,$CRj_float,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cfcko) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 8), 3)), ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 4), 2)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 2), 1))))) { + { + UQI opval = 3; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} else { + { + UQI opval = 2; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} +} else { + { + UQI opval = 0; + sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cjmpl: cjmpl$pack @($GRi,$GRj),$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cjmpl) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cjmpl.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +{ +if (EQSI (FLD (f_LI), 1)) { +frvbf_set_write_next_vliw_addr_to_LR (current_cpu, 1); +} + { + USI opval = ANDSI (ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))), 0xfffffffc); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +frvbf_model_branch (current_cpu, pc, 2); +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* ccalll: ccalll$pack @($GRi,$GRj),$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,ccalll) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cjmpl.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +{ +if (EQSI (FLD (f_LI), 1)) { +frvbf_set_write_next_vliw_addr_to_LR (current_cpu, 1); +} + { + USI opval = ANDSI (ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))), 0xfffffffc); + sim_queue_pc_write (current_cpu, opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +frvbf_model_branch (current_cpu, pc, 2); +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* ici: ici$pack @($GRi,$GRj) */ + +static SEM_PC +SEM_FN_NAME (frvbf,ici) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_icpl.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +frvbf_insn_cache_invalidate (current_cpu, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))), 0); + + return vpc; +#undef FLD +} + +/* dci: dci$pack @($GRi,$GRj) */ + +static SEM_PC +SEM_FN_NAME (frvbf,dci) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_icpl.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +frvbf_data_cache_invalidate (current_cpu, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))), 0); + + return vpc; +#undef FLD +} + +/* icei: icei$pack @($GRi,$GRj),$ae */ + +static SEM_PC +SEM_FN_NAME (frvbf,icei) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_icei.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQSI (FLD (f_ae), 0)) { +frvbf_insn_cache_invalidate (current_cpu, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))), -1); +} else { +frvbf_insn_cache_invalidate (current_cpu, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))), FLD (f_ae)); +} + + return vpc; +#undef FLD +} + +/* dcei: dcei$pack @($GRi,$GRj),$ae */ + +static SEM_PC +SEM_FN_NAME (frvbf,dcei) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_icei.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQSI (FLD (f_ae), 0)) { +frvbf_data_cache_invalidate (current_cpu, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))), -1); +} else { +frvbf_data_cache_invalidate (current_cpu, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))), FLD (f_ae)); +} + + return vpc; +#undef FLD +} + +/* dcf: dcf$pack @($GRi,$GRj) */ + +static SEM_PC +SEM_FN_NAME (frvbf,dcf) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_icpl.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +frvbf_data_cache_flush (current_cpu, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))), 0); + + return vpc; +#undef FLD +} + +/* dcef: dcef$pack @($GRi,$GRj),$ae */ + +static SEM_PC +SEM_FN_NAME (frvbf,dcef) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_icei.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQSI (FLD (f_ae), 0)) { +frvbf_data_cache_flush (current_cpu, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))), -1); +} else { +frvbf_data_cache_flush (current_cpu, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))), FLD (f_ae)); +} + + return vpc; +#undef FLD +} + +/* witlb: witlb$pack $GRk,@($GRi,$GRj) */ + +static SEM_PC +SEM_FN_NAME (frvbf,witlb) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + return vpc; +#undef FLD +} + +/* wdtlb: wdtlb$pack $GRk,@($GRi,$GRj) */ + +static SEM_PC +SEM_FN_NAME (frvbf,wdtlb) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + return vpc; +#undef FLD +} + +/* itlbi: itlbi$pack @($GRi,$GRj) */ + +static SEM_PC +SEM_FN_NAME (frvbf,itlbi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + return vpc; +#undef FLD +} + +/* dtlbi: dtlbi$pack @($GRi,$GRj) */ + +static SEM_PC +SEM_FN_NAME (frvbf,dtlbi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + return vpc; +#undef FLD +} + +/* icpl: icpl$pack $GRi,$GRj,$lock */ + +static SEM_PC +SEM_FN_NAME (frvbf,icpl) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_icpl.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +frvbf_insn_cache_preload (current_cpu, GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)), FLD (f_lock)); + + return vpc; +#undef FLD +} + +/* dcpl: dcpl$pack $GRi,$GRj,$lock */ + +static SEM_PC +SEM_FN_NAME (frvbf,dcpl) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_icpl.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +frvbf_data_cache_preload (current_cpu, GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)), FLD (f_lock)); + + return vpc; +#undef FLD +} + +/* icul: icul$pack $GRi */ + +static SEM_PC +SEM_FN_NAME (frvbf,icul) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_jmpil.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +frvbf_insn_cache_unlock (current_cpu, GET_H_GR (FLD (f_GRi))); + + return vpc; +#undef FLD +} + +/* dcul: dcul$pack $GRi */ + +static SEM_PC +SEM_FN_NAME (frvbf,dcul) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_jmpil.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +frvbf_data_cache_unlock (current_cpu, GET_H_GR (FLD (f_GRi))); + + return vpc; +#undef FLD +} + +/* bar: bar$pack */ + +static SEM_PC +SEM_FN_NAME (frvbf,bar) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + return vpc; +#undef FLD +} + +/* membar: membar$pack */ + +static SEM_PC +SEM_FN_NAME (frvbf,membar) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + return vpc; +#undef FLD +} + +/* cop1: cop1$pack $s6_1,$CPRi,$CPRj,$CPRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,cop1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + return vpc; +#undef FLD +} + +/* cop2: cop2$pack $s6_1,$CPRi,$CPRj,$CPRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,cop2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + return vpc; +#undef FLD +} + +/* clrgr: clrgr$pack $GRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,clrgr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frv_ref_SI (GET_H_GR (FLD (f_GRk))); +frvbf_clear_ne_flags (current_cpu, FLD (f_GRk), 0); +} + + return vpc; +#undef FLD +} + +/* clrfr: clrfr$pack $FRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,clrfr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frv_ref_SI (GET_H_FR (FLD (f_FRk))); +frvbf_clear_ne_flags (current_cpu, FLD (f_FRk), 1); +} + + return vpc; +#undef FLD +} + +/* clrga: clrga$pack */ + +static SEM_PC +SEM_FN_NAME (frvbf,clrga) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +frvbf_clear_ne_flags (current_cpu, -1, 0); + + return vpc; +#undef FLD +} + +/* clrfa: clrfa$pack */ + +static SEM_PC +SEM_FN_NAME (frvbf,clrfa) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +frvbf_clear_ne_flags (current_cpu, -1, 1); + + return vpc; +#undef FLD +} + +/* commitgr: commitgr$pack $GRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,commitgr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_setlos.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +frvbf_commit (current_cpu, FLD (f_GRk), 0); + + return vpc; +#undef FLD +} + +/* commitfr: commitfr$pack $FRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,commitfr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mhsethis.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +frvbf_commit (current_cpu, FLD (f_FRk), 1); + + return vpc; +#undef FLD +} + +/* commitga: commitga$pack */ + +static SEM_PC +SEM_FN_NAME (frvbf,commitga) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +frvbf_commit (current_cpu, -1, 0); + + return vpc; +#undef FLD +} + +/* commitfa: commitfa$pack */ + +static SEM_PC +SEM_FN_NAME (frvbf,commitfa) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +frvbf_commit (current_cpu, -1, 1); + + return vpc; +#undef FLD +} + +/* fitos: fitos$pack $FRintj,$FRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,fitos) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fditos.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->floatsisf) (CGEN_CPU_FPU (current_cpu), GET_H_FR_INT (FLD (f_FRj))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } + + return vpc; +#undef FLD +} + +/* fstoi: fstoi$pack $FRj,$FRintk */ + +static SEM_PC +SEM_FN_NAME (frvbf,fstoi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdstoi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = (* CGEN_CPU_FPU (current_cpu)->ops->fixsfsi) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRj))); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* fitod: fitod$pack $FRintj,$FRdoublek */ + +static SEM_PC +SEM_FN_NAME (frvbf,fitod) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fitod.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + DF opval = (* CGEN_CPU_FPU (current_cpu)->ops->floatsidf) (CGEN_CPU_FPU (current_cpu), GET_H_FR_INT (FLD (f_FRj))); + sim_queue_fn_df_write (current_cpu, frvbf_h_fr_double_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr_double", 'f', opval); + } + + return vpc; +#undef FLD +} + +/* fdtoi: fdtoi$pack $FRdoublej,$FRintk */ + +static SEM_PC +SEM_FN_NAME (frvbf,fdtoi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdtoi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = (* CGEN_CPU_FPU (current_cpu)->ops->fixdfsi) (CGEN_CPU_FPU (current_cpu), GET_H_FR_DOUBLE (FLD (f_FRj))); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* fditos: fditos$pack $FRintj,$FRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,fditos) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fditos.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->floatsisf) (CGEN_CPU_FPU (current_cpu), GET_H_FR_INT (FLD (f_FRj))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->floatsisf) (CGEN_CPU_FPU (current_cpu), GET_H_FR_INT (((FLD (f_FRj)) + (1)))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } +} + + return vpc; +#undef FLD +} + +/* fdstoi: fdstoi$pack $FRj,$FRintk */ + +static SEM_PC +SEM_FN_NAME (frvbf,fdstoi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdstoi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + { + SI opval = (* CGEN_CPU_FPU (current_cpu)->ops->fixsfsi) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRj))); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } + { + USI opval = (* CGEN_CPU_FPU (current_cpu)->ops->fixsfsi) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRj)) + (1)))); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, ((FLD (f_FRk)) + (1)), opval); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } +} + + return vpc; +#undef FLD +} + +/* nfditos: nfditos$pack $FRintj,$FRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,nfditos) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fditos.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_set_ne_index (current_cpu, FLD (f_FRk)); + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->floatsisf) (CGEN_CPU_FPU (current_cpu), GET_H_FR_INT (FLD (f_FRj))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } +frvbf_set_ne_index (current_cpu, ADDSI (FLD (f_FRk), 1)); + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->floatsisf) (CGEN_CPU_FPU (current_cpu), GET_H_FR_INT (((FLD (f_FRj)) + (1)))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } +} + + return vpc; +#undef FLD +} + +/* nfdstoi: nfdstoi$pack $FRj,$FRintk */ + +static SEM_PC +SEM_FN_NAME (frvbf,nfdstoi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdstoi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_set_ne_index (current_cpu, FLD (f_FRk)); + { + SI opval = (* CGEN_CPU_FPU (current_cpu)->ops->fixsfsi) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRj))); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } +frvbf_set_ne_index (current_cpu, ADDSI (FLD (f_FRk), 1)); + { + USI opval = (* CGEN_CPU_FPU (current_cpu)->ops->fixsfsi) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRj)) + (1)))); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, ((FLD (f_FRk)) + (1)), opval); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } +} + + return vpc; +#undef FLD +} + +/* cfitos: cfitos$pack $FRintj,$FRk,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cfitos) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfitos.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->floatsisf) (CGEN_CPU_FPU (current_cpu), GET_H_FR_INT (FLD (f_FRj))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cfstoi: cfstoi$pack $FRj,$FRintk,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cfstoi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfstoi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { + { + SI opval = (* CGEN_CPU_FPU (current_cpu)->ops->fixsfsi) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRj))); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* nfitos: nfitos$pack $FRintj,$FRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,nfitos) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fditos.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_set_ne_index (current_cpu, FLD (f_FRk)); + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->floatsisf) (CGEN_CPU_FPU (current_cpu), GET_H_FR_INT (FLD (f_FRj))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } +} + + return vpc; +#undef FLD +} + +/* nfstoi: nfstoi$pack $FRj,$FRintk */ + +static SEM_PC +SEM_FN_NAME (frvbf,nfstoi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdstoi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_set_ne_index (current_cpu, FLD (f_FRk)); + { + SI opval = (* CGEN_CPU_FPU (current_cpu)->ops->fixsfsi) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRj))); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } +} + + return vpc; +#undef FLD +} + +/* fmovs: fmovs$pack $FRj,$FRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,fmovs) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SF opval = GET_H_FR (FLD (f_FRj)); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } + + return vpc; +#undef FLD +} + +/* fmovd: fmovd$pack $FRdoublej,$FRdoublek */ + +static SEM_PC +SEM_FN_NAME (frvbf,fmovd) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fmaddd.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + DF opval = GET_H_FR_DOUBLE (FLD (f_FRj)); + sim_queue_fn_df_write (current_cpu, frvbf_h_fr_double_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr_double", 'f', opval); + } + + return vpc; +#undef FLD +} + +/* fdmovs: fdmovs$pack $FRj,$FRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,fdmovs) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + { + SF opval = GET_H_FR (FLD (f_FRj)); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } + { + SF opval = GET_H_FR (((FLD (f_FRj)) + (1))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } +} + + return vpc; +#undef FLD +} + +/* cfmovs: cfmovs$pack $FRj,$FRk,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cfmovs) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { + { + SF opval = GET_H_FR (FLD (f_FRj)); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* fnegs: fnegs$pack $FRj,$FRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,fnegs) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->negsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRj))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } + + return vpc; +#undef FLD +} + +/* fnegd: fnegd$pack $FRdoublej,$FRdoublek */ + +static SEM_PC +SEM_FN_NAME (frvbf,fnegd) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fmaddd.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + DF opval = (* CGEN_CPU_FPU (current_cpu)->ops->negdf) (CGEN_CPU_FPU (current_cpu), GET_H_FR_DOUBLE (FLD (f_FRj))); + sim_queue_fn_df_write (current_cpu, frvbf_h_fr_double_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr_double", 'f', opval); + } + + return vpc; +#undef FLD +} + +/* fdnegs: fdnegs$pack $FRj,$FRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,fdnegs) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->negsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRj))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->negsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRj)) + (1)))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } +} + + return vpc; +#undef FLD +} + +/* cfnegs: cfnegs$pack $FRj,$FRk,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cfnegs) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->negsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRj))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* fabss: fabss$pack $FRj,$FRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,fabss) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->abssf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRj))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } + + return vpc; +#undef FLD +} + +/* fabsd: fabsd$pack $FRdoublej,$FRdoublek */ + +static SEM_PC +SEM_FN_NAME (frvbf,fabsd) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fmaddd.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + DF opval = (* CGEN_CPU_FPU (current_cpu)->ops->absdf) (CGEN_CPU_FPU (current_cpu), GET_H_FR_DOUBLE (FLD (f_FRj))); + sim_queue_fn_df_write (current_cpu, frvbf_h_fr_double_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr_double", 'f', opval); + } + + return vpc; +#undef FLD +} + +/* fdabss: fdabss$pack $FRj,$FRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,fdabss) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->abssf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRj))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->abssf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRj)) + (1)))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } +} + + return vpc; +#undef FLD +} + +/* cfabss: cfabss$pack $FRj,$FRk,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cfabss) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->abssf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRj))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* fsqrts: fsqrts$pack $FRj,$FRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,fsqrts) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->sqrtsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRj))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } + + return vpc; +#undef FLD +} + +/* fdsqrts: fdsqrts$pack $FRj,$FRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,fdsqrts) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->sqrtsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRj))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->sqrtsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRj)) + (1)))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } +} + + return vpc; +#undef FLD +} + +/* nfdsqrts: nfdsqrts$pack $FRj,$FRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,nfdsqrts) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_set_ne_index (current_cpu, FLD (f_FRk)); + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->sqrtsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRj))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } +frvbf_set_ne_index (current_cpu, ADDSI (FLD (f_FRk), 1)); + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->sqrtsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRj)) + (1)))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } +} + + return vpc; +#undef FLD +} + +/* fsqrtd: fsqrtd$pack $FRdoublej,$FRdoublek */ + +static SEM_PC +SEM_FN_NAME (frvbf,fsqrtd) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fmaddd.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + DF opval = (* CGEN_CPU_FPU (current_cpu)->ops->sqrtdf) (CGEN_CPU_FPU (current_cpu), GET_H_FR_DOUBLE (FLD (f_FRj))); + sim_queue_fn_df_write (current_cpu, frvbf_h_fr_double_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr_double", 'f', opval); + } + + return vpc; +#undef FLD +} + +/* cfsqrts: cfsqrts$pack $FRj,$FRk,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cfsqrts) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->sqrtsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRj))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* nfsqrts: nfsqrts$pack $FRj,$FRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,nfsqrts) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_set_ne_index (current_cpu, FLD (f_FRk)); + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->sqrtsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRj))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } +} + + return vpc; +#undef FLD +} + +/* fadds: fadds$pack $FRi,$FRj,$FRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,fadds) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->addsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } + + return vpc; +#undef FLD +} + +/* fsubs: fsubs$pack $FRi,$FRj,$FRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,fsubs) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->subsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } + + return vpc; +#undef FLD +} + +/* fmuls: fmuls$pack $FRi,$FRj,$FRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,fmuls) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } + + return vpc; +#undef FLD +} + +/* fdivs: fdivs$pack $FRi,$FRj,$FRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,fdivs) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->divsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } + + return vpc; +#undef FLD +} + +/* faddd: faddd$pack $FRdoublei,$FRdoublej,$FRdoublek */ + +static SEM_PC +SEM_FN_NAME (frvbf,faddd) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fmaddd.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + DF opval = (* CGEN_CPU_FPU (current_cpu)->ops->adddf) (CGEN_CPU_FPU (current_cpu), GET_H_FR_DOUBLE (FLD (f_FRi)), GET_H_FR_DOUBLE (FLD (f_FRj))); + sim_queue_fn_df_write (current_cpu, frvbf_h_fr_double_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr_double", 'f', opval); + } + + return vpc; +#undef FLD +} + +/* fsubd: fsubd$pack $FRdoublei,$FRdoublej,$FRdoublek */ + +static SEM_PC +SEM_FN_NAME (frvbf,fsubd) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fmaddd.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + DF opval = (* CGEN_CPU_FPU (current_cpu)->ops->subdf) (CGEN_CPU_FPU (current_cpu), GET_H_FR_DOUBLE (FLD (f_FRi)), GET_H_FR_DOUBLE (FLD (f_FRj))); + sim_queue_fn_df_write (current_cpu, frvbf_h_fr_double_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr_double", 'f', opval); + } + + return vpc; +#undef FLD +} + +/* fmuld: fmuld$pack $FRdoublei,$FRdoublej,$FRdoublek */ + +static SEM_PC +SEM_FN_NAME (frvbf,fmuld) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fmaddd.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + DF opval = (* CGEN_CPU_FPU (current_cpu)->ops->muldf) (CGEN_CPU_FPU (current_cpu), GET_H_FR_DOUBLE (FLD (f_FRi)), GET_H_FR_DOUBLE (FLD (f_FRj))); + sim_queue_fn_df_write (current_cpu, frvbf_h_fr_double_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr_double", 'f', opval); + } + + return vpc; +#undef FLD +} + +/* fdivd: fdivd$pack $FRdoublei,$FRdoublej,$FRdoublek */ + +static SEM_PC +SEM_FN_NAME (frvbf,fdivd) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fmaddd.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + DF opval = (* CGEN_CPU_FPU (current_cpu)->ops->divdf) (CGEN_CPU_FPU (current_cpu), GET_H_FR_DOUBLE (FLD (f_FRi)), GET_H_FR_DOUBLE (FLD (f_FRj))); + sim_queue_fn_df_write (current_cpu, frvbf_h_fr_double_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr_double", 'f', opval); + } + + return vpc; +#undef FLD +} + +/* cfadds: cfadds$pack $FRi,$FRj,$FRk,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cfadds) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->addsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cfsubs: cfsubs$pack $FRi,$FRj,$FRk,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cfsubs) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->subsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cfmuls: cfmuls$pack $FRi,$FRj,$FRk,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cfmuls) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cfdivs: cfdivs$pack $FRi,$FRj,$FRk,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cfdivs) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->divsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* nfadds: nfadds$pack $FRi,$FRj,$FRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,nfadds) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_set_ne_index (current_cpu, FLD (f_FRk)); + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->addsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } +} + + return vpc; +#undef FLD +} + +/* nfsubs: nfsubs$pack $FRi,$FRj,$FRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,nfsubs) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_set_ne_index (current_cpu, FLD (f_FRk)); + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->subsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } +} + + return vpc; +#undef FLD +} + +/* nfmuls: nfmuls$pack $FRi,$FRj,$FRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,nfmuls) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_set_ne_index (current_cpu, FLD (f_FRk)); + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } +} + + return vpc; +#undef FLD +} + +/* nfdivs: nfdivs$pack $FRi,$FRj,$FRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,nfdivs) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_set_ne_index (current_cpu, FLD (f_FRk)); + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->divsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } +} + + return vpc; +#undef FLD +} + +/* fcmps: fcmps$pack $FRi,$FRj,$FCCi_2 */ + +static SEM_PC +SEM_FN_NAME (frvbf,fcmps) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfcmps.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if ((* CGEN_CPU_FPU (current_cpu)->ops->gtsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)))) { + { + UQI opval = 2; + sim_queue_qi_write (current_cpu, & CPU (h_fccr[FLD (f_FCCi_2)]), opval); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval); + } +} else { +if ((* CGEN_CPU_FPU (current_cpu)->ops->eqsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)))) { + { + UQI opval = 8; + sim_queue_qi_write (current_cpu, & CPU (h_fccr[FLD (f_FCCi_2)]), opval); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval); + } +} else { +if ((* CGEN_CPU_FPU (current_cpu)->ops->ltsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)))) { + { + UQI opval = 4; + sim_queue_qi_write (current_cpu, & CPU (h_fccr[FLD (f_FCCi_2)]), opval); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval); + } +} else { + { + UQI opval = 1; + sim_queue_qi_write (current_cpu, & CPU (h_fccr[FLD (f_FCCi_2)]), opval); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval); + } +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* fcmpd: fcmpd$pack $FRdoublei,$FRdoublej,$FCCi_2 */ + +static SEM_PC +SEM_FN_NAME (frvbf,fcmpd) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcmpd.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if ((* CGEN_CPU_FPU (current_cpu)->ops->gtdf) (CGEN_CPU_FPU (current_cpu), GET_H_FR_DOUBLE (FLD (f_FRi)), GET_H_FR_DOUBLE (FLD (f_FRj)))) { + { + UQI opval = 2; + sim_queue_qi_write (current_cpu, & CPU (h_fccr[FLD (f_FCCi_2)]), opval); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval); + } +} else { +if ((* CGEN_CPU_FPU (current_cpu)->ops->eqdf) (CGEN_CPU_FPU (current_cpu), GET_H_FR_DOUBLE (FLD (f_FRi)), GET_H_FR_DOUBLE (FLD (f_FRj)))) { + { + UQI opval = 8; + sim_queue_qi_write (current_cpu, & CPU (h_fccr[FLD (f_FCCi_2)]), opval); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval); + } +} else { +if ((* CGEN_CPU_FPU (current_cpu)->ops->ltdf) (CGEN_CPU_FPU (current_cpu), GET_H_FR_DOUBLE (FLD (f_FRi)), GET_H_FR_DOUBLE (FLD (f_FRj)))) { + { + UQI opval = 4; + sim_queue_qi_write (current_cpu, & CPU (h_fccr[FLD (f_FCCi_2)]), opval); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval); + } +} else { + { + UQI opval = 1; + sim_queue_qi_write (current_cpu, & CPU (h_fccr[FLD (f_FCCi_2)]), opval); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval); + } +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cfcmps: cfcmps$pack $FRi,$FRj,$FCCi_2,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cfcmps) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfcmps.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +if ((* CGEN_CPU_FPU (current_cpu)->ops->gtsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)))) { + { + UQI opval = 2; + sim_queue_qi_write (current_cpu, & CPU (h_fccr[FLD (f_FCCi_2)]), opval); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval); + } +} else { +if ((* CGEN_CPU_FPU (current_cpu)->ops->eqsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)))) { + { + UQI opval = 8; + sim_queue_qi_write (current_cpu, & CPU (h_fccr[FLD (f_FCCi_2)]), opval); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval); + } +} else { +if ((* CGEN_CPU_FPU (current_cpu)->ops->ltsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)))) { + { + UQI opval = 4; + sim_queue_qi_write (current_cpu, & CPU (h_fccr[FLD (f_FCCi_2)]), opval); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval); + } +} else { + { + UQI opval = 1; + sim_queue_qi_write (current_cpu, & CPU (h_fccr[FLD (f_FCCi_2)]), opval); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval); + } +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* fdcmps: fdcmps$pack $FRi,$FRj,$FCCi_2 */ + +static SEM_PC +SEM_FN_NAME (frvbf,fdcmps) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_nfdcmps.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +if ((* CGEN_CPU_FPU (current_cpu)->ops->gtsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)))) { + { + UQI opval = 2; + sim_queue_qi_write (current_cpu, & CPU (h_fccr[FLD (f_FCCi_2)]), opval); + written |= (1 << 7); + TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval); + } +} else { +if ((* CGEN_CPU_FPU (current_cpu)->ops->eqsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)))) { + { + UQI opval = 8; + sim_queue_qi_write (current_cpu, & CPU (h_fccr[FLD (f_FCCi_2)]), opval); + written |= (1 << 7); + TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval); + } +} else { +if ((* CGEN_CPU_FPU (current_cpu)->ops->ltsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)))) { + { + UQI opval = 4; + sim_queue_qi_write (current_cpu, & CPU (h_fccr[FLD (f_FCCi_2)]), opval); + written |= (1 << 7); + TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval); + } +} else { + { + UQI opval = 1; + sim_queue_qi_write (current_cpu, & CPU (h_fccr[FLD (f_FCCi_2)]), opval); + written |= (1 << 7); + TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval); + } +} +} +} +if ((* CGEN_CPU_FPU (current_cpu)->ops->gtsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1))))) { + { + UQI opval = 2; + sim_queue_qi_write (current_cpu, & CPU (h_fccr[((FLD (f_FCCi_2)) + (1))]), opval); + written |= (1 << 8); + TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval); + } +} else { +if ((* CGEN_CPU_FPU (current_cpu)->ops->eqsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1))))) { + { + UQI opval = 8; + sim_queue_qi_write (current_cpu, & CPU (h_fccr[((FLD (f_FCCi_2)) + (1))]), opval); + written |= (1 << 8); + TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval); + } +} else { +if ((* CGEN_CPU_FPU (current_cpu)->ops->ltsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1))))) { + { + UQI opval = 4; + sim_queue_qi_write (current_cpu, & CPU (h_fccr[((FLD (f_FCCi_2)) + (1))]), opval); + written |= (1 << 8); + TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval); + } +} else { + { + UQI opval = 1; + sim_queue_qi_write (current_cpu, & CPU (h_fccr[((FLD (f_FCCi_2)) + (1))]), opval); + written |= (1 << 8); + TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval); + } +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* fmadds: fmadds$pack $FRi,$FRj,$FRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,fmadds) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->addsf) (CGEN_CPU_FPU (current_cpu), (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj))), GET_H_FR (FLD (f_FRk))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } + + return vpc; +#undef FLD +} + +/* fmsubs: fmsubs$pack $FRi,$FRj,$FRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,fmsubs) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->subsf) (CGEN_CPU_FPU (current_cpu), (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj))), GET_H_FR (FLD (f_FRk))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } + + return vpc; +#undef FLD +} + +/* fmaddd: fmaddd$pack $FRdoublei,$FRdoublej,$FRdoublek */ + +static SEM_PC +SEM_FN_NAME (frvbf,fmaddd) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fmaddd.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + DF opval = (* CGEN_CPU_FPU (current_cpu)->ops->adddf) (CGEN_CPU_FPU (current_cpu), (* CGEN_CPU_FPU (current_cpu)->ops->muldf) (CGEN_CPU_FPU (current_cpu), GET_H_FR_DOUBLE (FLD (f_FRi)), GET_H_FR_DOUBLE (FLD (f_FRj))), GET_H_FR_DOUBLE (FLD (f_FRk))); + sim_queue_fn_df_write (current_cpu, frvbf_h_fr_double_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr_double", 'f', opval); + } + + return vpc; +#undef FLD +} + +/* fmsubd: fmsubd$pack $FRdoublei,$FRdoublej,$FRdoublek */ + +static SEM_PC +SEM_FN_NAME (frvbf,fmsubd) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fmaddd.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + DF opval = (* CGEN_CPU_FPU (current_cpu)->ops->subdf) (CGEN_CPU_FPU (current_cpu), (* CGEN_CPU_FPU (current_cpu)->ops->muldf) (CGEN_CPU_FPU (current_cpu), GET_H_FR_DOUBLE (FLD (f_FRi)), GET_H_FR_DOUBLE (FLD (f_FRj))), GET_H_FR_DOUBLE (FLD (f_FRk))); + sim_queue_fn_df_write (current_cpu, frvbf_h_fr_double_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr_double", 'f', opval); + } + + return vpc; +#undef FLD +} + +/* fdmadds: fdmadds$pack $FRi,$FRj,$FRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,fdmadds) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->addsf) (CGEN_CPU_FPU (current_cpu), (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj))), GET_H_FR (FLD (f_FRk))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->addsf) (CGEN_CPU_FPU (current_cpu), (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1)))), GET_H_FR (((FLD (f_FRk)) + (1)))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } +} + + return vpc; +#undef FLD +} + +/* nfdmadds: nfdmadds$pack $FRi,$FRj,$FRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,nfdmadds) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_set_ne_index (current_cpu, FLD (f_FRk)); + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->addsf) (CGEN_CPU_FPU (current_cpu), (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj))), GET_H_FR (FLD (f_FRk))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } +frvbf_set_ne_index (current_cpu, ADDSI (FLD (f_FRk), 1)); + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->addsf) (CGEN_CPU_FPU (current_cpu), (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1)))), GET_H_FR (((FLD (f_FRk)) + (1)))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } +} + + return vpc; +#undef FLD +} + +/* cfmadds: cfmadds$pack $FRi,$FRj,$FRk,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cfmadds) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->addsf) (CGEN_CPU_FPU (current_cpu), (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj))), GET_H_FR (FLD (f_FRk))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval); + written |= (1 << 5); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cfmsubs: cfmsubs$pack $FRi,$FRj,$FRk,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cfmsubs) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->subsf) (CGEN_CPU_FPU (current_cpu), (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj))), GET_H_FR (FLD (f_FRk))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval); + written |= (1 << 5); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* nfmadds: nfmadds$pack $FRi,$FRj,$FRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,nfmadds) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_set_ne_index (current_cpu, FLD (f_FRk)); + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->addsf) (CGEN_CPU_FPU (current_cpu), (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj))), GET_H_FR (FLD (f_FRk))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } +} + + return vpc; +#undef FLD +} + +/* nfmsubs: nfmsubs$pack $FRi,$FRj,$FRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,nfmsubs) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_set_ne_index (current_cpu, FLD (f_FRk)); + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->subsf) (CGEN_CPU_FPU (current_cpu), (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj))), GET_H_FR (FLD (f_FRk))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } +} + + return vpc; +#undef FLD +} + +/* fmas: fmas$pack $FRi,$FRj,$FRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,fmas) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->addsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1)))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } +} + + return vpc; +#undef FLD +} + +/* fmss: fmss$pack $FRi,$FRj,$FRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,fmss) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->subsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1)))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } +} + + return vpc; +#undef FLD +} + +/* fdmas: fdmas$pack $FRi,$FRj,$FRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,fdmas) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmas.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->addsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1)))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (2))), GET_H_FR (((FLD (f_FRj)) + (2)))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (2)), opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->addsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (3))), GET_H_FR (((FLD (f_FRj)) + (3)))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (3)), opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } +} + + return vpc; +#undef FLD +} + +/* fdmss: fdmss$pack $FRi,$FRj,$FRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,fdmss) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmas.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->subsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1)))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (2))), GET_H_FR (((FLD (f_FRj)) + (2)))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (2)), opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->subsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (3))), GET_H_FR (((FLD (f_FRj)) + (3)))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (3)), opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } +} + + return vpc; +#undef FLD +} + +/* nfdmas: nfdmas$pack $FRi,$FRj,$FRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,nfdmas) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmas.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_set_ne_index (current_cpu, FLD (f_FRk)); +frvbf_set_ne_index (current_cpu, ADDSI (FLD (f_FRk), 1)); +frvbf_set_ne_index (current_cpu, ADDSI (FLD (f_FRk), 2)); +frvbf_set_ne_index (current_cpu, ADDSI (FLD (f_FRk), 3)); + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->addsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1)))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (2))), GET_H_FR (((FLD (f_FRj)) + (2)))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (2)), opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->addsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (3))), GET_H_FR (((FLD (f_FRj)) + (3)))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (3)), opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } +} + + return vpc; +#undef FLD +} + +/* nfdmss: nfdmss$pack $FRi,$FRj,$FRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,nfdmss) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmas.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_set_ne_index (current_cpu, FLD (f_FRk)); +frvbf_set_ne_index (current_cpu, ADDSI (FLD (f_FRk), 1)); +frvbf_set_ne_index (current_cpu, ADDSI (FLD (f_FRk), 2)); +frvbf_set_ne_index (current_cpu, ADDSI (FLD (f_FRk), 3)); + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->subsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1)))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (2))), GET_H_FR (((FLD (f_FRj)) + (2)))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (2)), opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->subsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (3))), GET_H_FR (((FLD (f_FRj)) + (3)))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (3)), opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } +} + + return vpc; +#undef FLD +} + +/* cfmas: cfmas$pack $FRi,$FRj,$FRk,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cfmas) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmas.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +{ + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval); + written |= (1 << 9); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->addsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1)))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval); + written |= (1 << 10); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cfmss: cfmss$pack $FRi,$FRj,$FRk,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cfmss) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmas.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +{ + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval); + written |= (1 << 9); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->subsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1)))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval); + written |= (1 << 10); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* fmad: fmad$pack $FRi,$FRj,$FRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,fmad) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->ftruncdfsf) (CGEN_CPU_FPU (current_cpu), (* CGEN_CPU_FPU (current_cpu)->ops->muldf) (CGEN_CPU_FPU (current_cpu), (* CGEN_CPU_FPU (current_cpu)->ops->fextsfdf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi))), (* CGEN_CPU_FPU (current_cpu)->ops->fextsfdf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRj))))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->ftruncdfsf) (CGEN_CPU_FPU (current_cpu), (* CGEN_CPU_FPU (current_cpu)->ops->adddf) (CGEN_CPU_FPU (current_cpu), (* CGEN_CPU_FPU (current_cpu)->ops->fextsfdf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1)))), (* CGEN_CPU_FPU (current_cpu)->ops->fextsfdf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRj)) + (1)))))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } +} + + return vpc; +#undef FLD +} + +/* fmsd: fmsd$pack $FRi,$FRj,$FRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,fmsd) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->ftruncdfsf) (CGEN_CPU_FPU (current_cpu), (* CGEN_CPU_FPU (current_cpu)->ops->muldf) (CGEN_CPU_FPU (current_cpu), (* CGEN_CPU_FPU (current_cpu)->ops->fextsfdf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi))), (* CGEN_CPU_FPU (current_cpu)->ops->fextsfdf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRj))))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->ftruncdfsf) (CGEN_CPU_FPU (current_cpu), (* CGEN_CPU_FPU (current_cpu)->ops->subdf) (CGEN_CPU_FPU (current_cpu), (* CGEN_CPU_FPU (current_cpu)->ops->fextsfdf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1)))), (* CGEN_CPU_FPU (current_cpu)->ops->fextsfdf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRj)) + (1)))))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } +} + + return vpc; +#undef FLD +} + +/* nfmas: nfmas$pack $FRi,$FRj,$FRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,nfmas) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_set_ne_index (current_cpu, FLD (f_FRk)); + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } +frvbf_set_ne_index (current_cpu, ADDSI (FLD (f_FRk), 1)); + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->addsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1)))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } +} + + return vpc; +#undef FLD +} + +/* nfmss: nfmss$pack $FRi,$FRj,$FRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,nfmss) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_set_ne_index (current_cpu, FLD (f_FRk)); + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } +frvbf_set_ne_index (current_cpu, ADDSI (FLD (f_FRk), 1)); + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->subsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1)))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } +} + + return vpc; +#undef FLD +} + +/* fdadds: fdadds$pack $FRi,$FRj,$FRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,fdadds) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->addsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->addsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1)))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } +} + + return vpc; +#undef FLD +} + +/* fdsubs: fdsubs$pack $FRi,$FRj,$FRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,fdsubs) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->subsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->subsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1)))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } +} + + return vpc; +#undef FLD +} + +/* fdmuls: fdmuls$pack $FRi,$FRj,$FRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,fdmuls) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1)))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } +} + + return vpc; +#undef FLD +} + +/* fddivs: fddivs$pack $FRi,$FRj,$FRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,fddivs) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->divsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->divsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1)))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } +} + + return vpc; +#undef FLD +} + +/* fdsads: fdsads$pack $FRi,$FRj,$FRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,fdsads) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->addsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->subsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1)))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } +} + + return vpc; +#undef FLD +} + +/* fdmulcs: fdmulcs$pack $FRi,$FRj,$FRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,fdmulcs) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (((FLD (f_FRj)) + (1)))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (FLD (f_FRj))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } +} + + return vpc; +#undef FLD +} + +/* nfdmulcs: nfdmulcs$pack $FRi,$FRj,$FRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,nfdmulcs) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_set_ne_index (current_cpu, FLD (f_FRk)); + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (((FLD (f_FRj)) + (1)))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } +frvbf_set_ne_index (current_cpu, ADDSI (FLD (f_FRk), 1)); + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (FLD (f_FRj))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } +} + + return vpc; +#undef FLD +} + +/* nfdadds: nfdadds$pack $FRi,$FRj,$FRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,nfdadds) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_set_ne_index (current_cpu, FLD (f_FRk)); + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->addsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } +frvbf_set_ne_index (current_cpu, ADDSI (FLD (f_FRk), 1)); + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->addsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1)))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } +} + + return vpc; +#undef FLD +} + +/* nfdsubs: nfdsubs$pack $FRi,$FRj,$FRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,nfdsubs) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_set_ne_index (current_cpu, FLD (f_FRk)); + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->subsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } +frvbf_set_ne_index (current_cpu, ADDSI (FLD (f_FRk), 1)); + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->subsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1)))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } +} + + return vpc; +#undef FLD +} + +/* nfdmuls: nfdmuls$pack $FRi,$FRj,$FRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,nfdmuls) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_set_ne_index (current_cpu, FLD (f_FRk)); + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } +frvbf_set_ne_index (current_cpu, ADDSI (FLD (f_FRk), 1)); + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1)))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } +} + + return vpc; +#undef FLD +} + +/* nfddivs: nfddivs$pack $FRi,$FRj,$FRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,nfddivs) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_set_ne_index (current_cpu, FLD (f_FRk)); + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->divsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } +frvbf_set_ne_index (current_cpu, ADDSI (FLD (f_FRk), 1)); + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->divsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1)))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } +} + + return vpc; +#undef FLD +} + +/* nfdsads: nfdsads$pack $FRi,$FRj,$FRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,nfdsads) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_set_ne_index (current_cpu, FLD (f_FRk)); + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->addsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } +frvbf_set_ne_index (current_cpu, ADDSI (FLD (f_FRk), 1)); + { + SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->subsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1)))); + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } +} + + return vpc; +#undef FLD +} + +/* nfdcmps: nfdcmps$pack $FRi,$FRj,$FCCi_2 */ + +static SEM_PC +SEM_FN_NAME (frvbf,nfdcmps) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_nfdcmps.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frvbf_set_ne_index (current_cpu, FLD (f_FRk)); +if ((* CGEN_CPU_FPU (current_cpu)->ops->gtsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)))) { + { + UQI opval = 2; + sim_queue_qi_write (current_cpu, & CPU (h_fccr[FLD (f_FCCi_2)]), opval); + written |= (1 << 8); + TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval); + } +} else { +if ((* CGEN_CPU_FPU (current_cpu)->ops->eqsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)))) { + { + UQI opval = 8; + sim_queue_qi_write (current_cpu, & CPU (h_fccr[FLD (f_FCCi_2)]), opval); + written |= (1 << 8); + TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval); + } +} else { +if ((* CGEN_CPU_FPU (current_cpu)->ops->ltsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)))) { + { + UQI opval = 4; + sim_queue_qi_write (current_cpu, & CPU (h_fccr[FLD (f_FCCi_2)]), opval); + written |= (1 << 8); + TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval); + } +} else { + { + UQI opval = 1; + sim_queue_qi_write (current_cpu, & CPU (h_fccr[FLD (f_FCCi_2)]), opval); + written |= (1 << 8); + TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval); + } +} +} +} +frvbf_set_ne_index (current_cpu, ADDSI (FLD (f_FRk), 1)); +if ((* CGEN_CPU_FPU (current_cpu)->ops->gtsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1))))) { + { + UQI opval = 2; + sim_queue_qi_write (current_cpu, & CPU (h_fccr[((FLD (f_FCCi_2)) + (1))]), opval); + written |= (1 << 9); + TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval); + } +} else { +if ((* CGEN_CPU_FPU (current_cpu)->ops->eqsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1))))) { + { + UQI opval = 8; + sim_queue_qi_write (current_cpu, & CPU (h_fccr[((FLD (f_FCCi_2)) + (1))]), opval); + written |= (1 << 9); + TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval); + } +} else { +if ((* CGEN_CPU_FPU (current_cpu)->ops->ltsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1))))) { + { + UQI opval = 4; + sim_queue_qi_write (current_cpu, & CPU (h_fccr[((FLD (f_FCCi_2)) + (1))]), opval); + written |= (1 << 9); + TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval); + } +} else { + { + UQI opval = 1; + sim_queue_qi_write (current_cpu, & CPU (h_fccr[((FLD (f_FCCi_2)) + (1))]), opval); + written |= (1 << 9); + TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval); + } +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* mhsetlos: mhsetlos$pack $u12,$FRklo */ + +static SEM_PC +SEM_FN_NAME (frvbf,mhsetlos) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mhsetlos.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + UHI opval = FLD (f_u12); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* mhsethis: mhsethis$pack $u12,$FRkhi */ + +static SEM_PC +SEM_FN_NAME (frvbf,mhsethis) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mhsethis.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + UHI opval = FLD (f_u12); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* mhdsets: mhdsets$pack $u12,$FRintk */ + +static SEM_PC +SEM_FN_NAME (frvbf,mhdsets) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mhdsets.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + { + SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRk))); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } + { + UHI opval = FLD (f_u12); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } + { + UHI opval = FLD (f_u12); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +} + + return vpc; +#undef FLD +} + +/* mhsetloh: mhsetloh$pack $s5,$FRklo */ + +static SEM_PC +SEM_FN_NAME (frvbf,mhsetloh) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mhsetloh.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + HI tmp_tmp; + tmp_tmp = GET_H_FR_LO (FLD (f_FRk)); + tmp_tmp = ANDHI (tmp_tmp, 2047); + tmp_tmp = ORHI (tmp_tmp, SLLSI (ANDSI (FLD (f_s5), 31), 11)); + { + UHI opval = tmp_tmp; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +} + + return vpc; +#undef FLD +} + +/* mhsethih: mhsethih$pack $s5,$FRkhi */ + +static SEM_PC +SEM_FN_NAME (frvbf,mhsethih) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mhsethih.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + HI tmp_tmp; + tmp_tmp = GET_H_FR_HI (FLD (f_FRk)); + tmp_tmp = ANDHI (tmp_tmp, 2047); + tmp_tmp = ORHI (tmp_tmp, SLLSI (ANDSI (FLD (f_s5), 31), 11)); + { + UHI opval = tmp_tmp; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } +} + + return vpc; +#undef FLD +} + +/* mhdseth: mhdseth$pack $s5,$FRintk */ + +static SEM_PC +SEM_FN_NAME (frvbf,mhdseth) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mhdseth.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + { + SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRk))); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } +{ + HI tmp_tmp; + tmp_tmp = GET_H_FR_HI (((FLD (f_FRk)) + (0))); + tmp_tmp = ANDHI (tmp_tmp, 2047); + tmp_tmp = ORHI (tmp_tmp, SLLSI (ANDSI (FLD (f_s5), 31), 11)); + { + UHI opval = tmp_tmp; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } +} +{ + HI tmp_tmp; + tmp_tmp = GET_H_FR_LO (((FLD (f_FRk)) + (0))); + tmp_tmp = ANDHI (tmp_tmp, 2047); + tmp_tmp = ORHI (tmp_tmp, SLLSI (ANDSI (FLD (f_s5), 31), 11)); + { + UHI opval = tmp_tmp; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +} +} + + return vpc; +#undef FLD +} + +/* mand: mand$pack $FRinti,$FRintj,$FRintk */ + +static SEM_PC +SEM_FN_NAME (frvbf,mand) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mwcut.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = ANDSI (GET_H_FR_INT (FLD (f_FRi)), GET_H_FR_INT (FLD (f_FRj))); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* mor: mor$pack $FRinti,$FRintj,$FRintk */ + +static SEM_PC +SEM_FN_NAME (frvbf,mor) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mwcut.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = ORSI (GET_H_FR_INT (FLD (f_FRi)), GET_H_FR_INT (FLD (f_FRj))); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* mxor: mxor$pack $FRinti,$FRintj,$FRintk */ + +static SEM_PC +SEM_FN_NAME (frvbf,mxor) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mwcut.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = XORSI (GET_H_FR_INT (FLD (f_FRi)), GET_H_FR_INT (FLD (f_FRj))); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* cmand: cmand$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cmand) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmand.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { + { + SI opval = ANDSI (GET_H_FR_INT (FLD (f_FRi)), GET_H_FR_INT (FLD (f_FRj))); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cmor: cmor$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cmor) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmand.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { + { + SI opval = ORSI (GET_H_FR_INT (FLD (f_FRi)), GET_H_FR_INT (FLD (f_FRj))); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cmxor: cmxor$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cmxor) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmand.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { + { + SI opval = XORSI (GET_H_FR_INT (FLD (f_FRi)), GET_H_FR_INT (FLD (f_FRj))); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* mnot: mnot$pack $FRintj,$FRintk */ + +static SEM_PC +SEM_FN_NAME (frvbf,mnot) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mcut.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = INVSI (GET_H_FR_INT (FLD (f_FRj))); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* cmnot: cmnot$pack $FRintj,$FRintk,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cmnot) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmand.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { + { + SI opval = INVSI (GET_H_FR_INT (FLD (f_FRj))); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* mrotli: mrotli$pack $FRinti,$u6,$FRintk */ + +static SEM_PC +SEM_FN_NAME (frvbf,mrotli) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mwcuti.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = ROLSI (GET_H_FR_INT (FLD (f_FRi)), ANDSI (FLD (f_u6), 31)); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* mrotri: mrotri$pack $FRinti,$u6,$FRintk */ + +static SEM_PC +SEM_FN_NAME (frvbf,mrotri) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mwcuti.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = RORSI (GET_H_FR_INT (FLD (f_FRi)), ANDSI (FLD (f_u6), 31)); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* mwcut: mwcut$pack $FRinti,$FRintj,$FRintk */ + +static SEM_PC +SEM_FN_NAME (frvbf,mwcut) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mwcut.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = frvbf_cut (current_cpu, GET_H_FR_INT (FLD (f_FRi)), GET_H_FR_INT (((FLD (f_FRi)) + (1))), GET_H_FR_INT (FLD (f_FRj))); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* mwcuti: mwcuti$pack $FRinti,$u6,$FRintk */ + +static SEM_PC +SEM_FN_NAME (frvbf,mwcuti) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mwcuti.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = frvbf_cut (current_cpu, GET_H_FR_INT (FLD (f_FRi)), GET_H_FR_INT (((FLD (f_FRi)) + (1))), FLD (f_u6)); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* mcut: mcut$pack $ACC40Si,$FRintj,$FRintk */ + +static SEM_PC +SEM_FN_NAME (frvbf,mcut) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mcut.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = frvbf_media_cut (current_cpu, GET_H_ACC40S (FLD (f_ACC40Si)), GET_H_FR_INT (FLD (f_FRj))); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* mcuti: mcuti$pack $ACC40Si,$s6,$FRintk */ + +static SEM_PC +SEM_FN_NAME (frvbf,mcuti) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mcuti.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = frvbf_media_cut (current_cpu, GET_H_ACC40S (FLD (f_ACC40Si)), FLD (f_s6)); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* mcutss: mcutss$pack $ACC40Si,$FRintj,$FRintk */ + +static SEM_PC +SEM_FN_NAME (frvbf,mcutss) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mcut.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = frvbf_media_cut_ss (current_cpu, GET_H_ACC40S (FLD (f_ACC40Si)), GET_H_FR_INT (FLD (f_FRj))); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* mcutssi: mcutssi$pack $ACC40Si,$s6,$FRintk */ + +static SEM_PC +SEM_FN_NAME (frvbf,mcutssi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mcuti.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = frvbf_media_cut_ss (current_cpu, GET_H_ACC40S (FLD (f_ACC40Si)), FLD (f_s6)); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* mdcutssi: mdcutssi$pack $ACC40Si,$s6,$FRintkeven */ + +static SEM_PC +SEM_FN_NAME (frvbf,mdcutssi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdcutssi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (ANDSI (FLD (f_ACC40Si), SUBSI (2, 1))) { +frvbf_media_acc_not_aligned (current_cpu); +} else { +if (ANDSI (FLD (f_FRk), SUBSI (2, 1))) { +frvbf_media_register_not_aligned (current_cpu); +} else { +{ + { + SI opval = frvbf_media_cut_ss (current_cpu, GET_H_ACC40S (FLD (f_ACC40Si)), FLD (f_s6)); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + written |= (1 << 5); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } + { + USI opval = frvbf_media_cut_ss (current_cpu, GET_H_ACC40S (((FLD (f_ACC40Si)) + (1))), FLD (f_s6)); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, ((FLD (f_FRk)) + (1)), opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* maveh: maveh$pack $FRinti,$FRintj,$FRintk */ + +static SEM_PC +SEM_FN_NAME (frvbf,maveh) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mwcut.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = frvbf_media_average (current_cpu, GET_H_FR_INT (FLD (f_FRi)), GET_H_FR_INT (FLD (f_FRj))); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* msllhi: msllhi$pack $FRinti,$u6,$FRintk */ + +static SEM_PC +SEM_FN_NAME (frvbf,msllhi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_msllhi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + { + SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRi))); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRi), opval); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } + { + SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRk))); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } + { + UHI opval = SLLHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), ANDSI (FLD (f_u6), 15)); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } + { + UHI opval = SLLHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), ANDSI (FLD (f_u6), 15)); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +} + + return vpc; +#undef FLD +} + +/* msrlhi: msrlhi$pack $FRinti,$u6,$FRintk */ + +static SEM_PC +SEM_FN_NAME (frvbf,msrlhi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_msllhi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + { + SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRi))); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRi), opval); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } + { + SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRk))); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } + { + UHI opval = SRLHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), ANDSI (FLD (f_u6), 15)); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } + { + UHI opval = SRLHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), ANDSI (FLD (f_u6), 15)); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +} + + return vpc; +#undef FLD +} + +/* msrahi: msrahi$pack $FRinti,$u6,$FRintk */ + +static SEM_PC +SEM_FN_NAME (frvbf,msrahi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_msllhi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + { + SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRi))); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRi), opval); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } + { + SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRk))); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } + { + UHI opval = SRAHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), ANDSI (FLD (f_u6), 15)); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } + { + UHI opval = SRAHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), ANDSI (FLD (f_u6), 15)); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +} + + return vpc; +#undef FLD +} + +/* mdrotli: mdrotli$pack $FRintieven,$s6,$FRintkeven */ + +static SEM_PC +SEM_FN_NAME (frvbf,mdrotli) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdrotli.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (ORIF (ANDSI (FLD (f_FRi), SUBSI (2, 1)), ANDSI (FLD (f_FRk), SUBSI (2, 1)))) { +frvbf_media_register_not_aligned (current_cpu); +} else { +{ + { + SI opval = ROLSI (GET_H_FR_INT (FLD (f_FRi)), ANDSI (FLD (f_s6), 31)); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + written |= (1 << 5); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } + { + USI opval = ROLSI (GET_H_FR_INT (((FLD (f_FRi)) + (1))), ANDSI (FLD (f_s6), 31)); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, ((FLD (f_FRk)) + (1)), opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* mcplhi: mcplhi$pack $FRinti,$u6,$FRintk */ + +static SEM_PC +SEM_FN_NAME (frvbf,mcplhi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mcplhi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + HI tmp_arg1; + HI tmp_arg2; + HI tmp_shift; + { + SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRi))); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRi), opval); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } + { + SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRk))); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } + tmp_shift = ANDSI (FLD (f_u6), 15); + tmp_arg1 = SLLHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), tmp_shift); +if (NEHI (tmp_shift, 0)) { +{ + tmp_arg2 = GET_H_FR_HI (((FLD (f_FRi)) + (1))); + tmp_arg2 = SRLHI (SLLHI (tmp_arg2, SUBSI (15, tmp_shift)), SUBSI (15, tmp_shift)); + tmp_arg1 = ORHI (tmp_arg1, tmp_arg2); +} +} + { + UHI opval = tmp_arg1; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } +} + + return vpc; +#undef FLD +} + +/* mcpli: mcpli$pack $FRinti,$u6,$FRintk */ + +static SEM_PC +SEM_FN_NAME (frvbf,mcpli) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mwcuti.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + SI tmp_tmp; + SI tmp_shift; + tmp_shift = ANDSI (FLD (f_u6), 31); + tmp_tmp = SLLSI (GET_H_FR_INT (FLD (f_FRi)), tmp_shift); +if (NESI (tmp_shift, 0)) { +{ + SI tmp_tmp1; + tmp_tmp1 = SRLSI (SLLSI (GET_H_FR_INT (((FLD (f_FRi)) + (1))), SUBSI (31, tmp_shift)), SUBSI (31, tmp_shift)); + tmp_tmp = ORSI (tmp_tmp, tmp_tmp1); +} +} + { + SI opval = tmp_tmp; + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } +} + + return vpc; +#undef FLD +} + +/* msaths: msaths$pack $FRinti,$FRintj,$FRintk */ + +static SEM_PC +SEM_FN_NAME (frvbf,msaths) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + HI tmp_argihi; + HI tmp_argilo; + HI tmp_argjhi; + HI tmp_argjlo; +{ + tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); + tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); +} +if (GTHI (tmp_argihi, tmp_argjhi)) { + { + UHI opval = tmp_argjhi; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 9); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } +} else { +if (LTHI (tmp_argihi, INVHI (tmp_argjhi))) { + { + UHI opval = INVHI (tmp_argjhi); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 9); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } +} else { + { + UHI opval = tmp_argihi; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 9); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } +} +} +if (GTHI (tmp_argilo, tmp_argjlo)) { + { + UHI opval = tmp_argjlo; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 10); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +} else { +if (LTHI (tmp_argilo, INVHI (tmp_argjlo))) { + { + UHI opval = INVHI (tmp_argjlo); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 10); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +} else { + { + UHI opval = tmp_argilo; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 10); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* mqsaths: mqsaths$pack $FRintieven,$FRintjeven,$FRintkeven */ + +static SEM_PC +SEM_FN_NAME (frvbf,mqsaths) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (ORIF (ANDSI (FLD (f_FRi), SUBSI (2, 1)), ORIF (ANDSI (FLD (f_FRj), SUBSI (2, 1)), ANDSI (FLD (f_FRk), SUBSI (2, 1))))) { +frvbf_media_register_not_aligned (current_cpu); +} else { +{ + HI tmp_argihi; + HI tmp_argilo; + HI tmp_argjhi; + HI tmp_argjlo; + { + SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRk))); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + written |= (1 << 14); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } +{ + tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); + tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); +} +if (GTHI (tmp_argihi, tmp_argjhi)) { + { + UHI opval = tmp_argjhi; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 15); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } +} else { +if (LTHI (tmp_argihi, INVHI (tmp_argjhi))) { + { + UHI opval = INVHI (tmp_argjhi); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 15); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } +} else { + { + UHI opval = tmp_argihi; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 15); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } +} +} +if (GTHI (tmp_argilo, tmp_argjlo)) { + { + UHI opval = tmp_argjlo; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 17); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +} else { +if (LTHI (tmp_argilo, INVHI (tmp_argjlo))) { + { + UHI opval = INVHI (tmp_argjlo); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 17); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +} else { + { + UHI opval = tmp_argilo; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 17); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +} +} +{ + tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); + tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); +} +if (GTHI (tmp_argihi, tmp_argjhi)) { + { + UHI opval = tmp_argjhi; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (1)), opval); + written |= (1 << 16); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } +} else { +if (LTHI (tmp_argihi, INVHI (tmp_argjhi))) { + { + UHI opval = INVHI (tmp_argjhi); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (1)), opval); + written |= (1 << 16); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } +} else { + { + UHI opval = tmp_argihi; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (1)), opval); + written |= (1 << 16); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } +} +} +if (GTHI (tmp_argilo, tmp_argjlo)) { + { + UHI opval = tmp_argjlo; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (1)), opval); + written |= (1 << 18); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +} else { +if (LTHI (tmp_argilo, INVHI (tmp_argjlo))) { + { + UHI opval = INVHI (tmp_argjlo); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (1)), opval); + written |= (1 << 18); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +} else { + { + UHI opval = tmp_argilo; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (1)), opval); + written |= (1 << 18); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* msathu: msathu$pack $FRinti,$FRintj,$FRintk */ + +static SEM_PC +SEM_FN_NAME (frvbf,msathu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + UHI tmp_argihi; + UHI tmp_argilo; + UHI tmp_argjhi; + UHI tmp_argjlo; +{ + tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); + tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); +} +if (GTUHI (tmp_argihi, tmp_argjhi)) { + { + UHI opval = tmp_argjhi; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 9); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } +} else { + { + UHI opval = tmp_argihi; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 9); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } +} +if (GTUHI (tmp_argilo, tmp_argjlo)) { + { + UHI opval = tmp_argjlo; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 10); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +} else { + { + UHI opval = tmp_argilo; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 10); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* mcmpsh: mcmpsh$pack $FRinti,$FRintj,$FCCk */ + +static SEM_PC +SEM_FN_NAME (frvbf,mcmpsh) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mcmpsh.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (ANDSI (FLD (f_FCCk), SUBSI (2, 1))) { +frvbf_media_cr_not_aligned (current_cpu); +} else { +{ + HI tmp_argihi; + HI tmp_argilo; + HI tmp_argjhi; + HI tmp_argjlo; +{ + tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); + tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); +} +if (GTHI (tmp_argihi, tmp_argjhi)) { + { + UQI opval = 2; + sim_queue_qi_write (current_cpu, & CPU (h_fccr[FLD (f_FCCk)]), opval); + written |= (1 << 9); + TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval); + } +} else { +if (EQHI (tmp_argihi, tmp_argjhi)) { + { + UQI opval = 8; + sim_queue_qi_write (current_cpu, & CPU (h_fccr[FLD (f_FCCk)]), opval); + written |= (1 << 9); + TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval); + } +} else { +if (LTHI (tmp_argihi, tmp_argjhi)) { + { + UQI opval = 4; + sim_queue_qi_write (current_cpu, & CPU (h_fccr[FLD (f_FCCk)]), opval); + written |= (1 << 9); + TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval); + } +} else { + { + UQI opval = 1; + sim_queue_qi_write (current_cpu, & CPU (h_fccr[FLD (f_FCCk)]), opval); + written |= (1 << 9); + TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval); + } +} +} +} +if (GTHI (tmp_argilo, tmp_argjlo)) { + { + UQI opval = 2; + sim_queue_qi_write (current_cpu, & CPU (h_fccr[((FLD (f_FCCk)) + (1))]), opval); + written |= (1 << 10); + TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval); + } +} else { +if (EQHI (tmp_argilo, tmp_argjlo)) { + { + UQI opval = 8; + sim_queue_qi_write (current_cpu, & CPU (h_fccr[((FLD (f_FCCk)) + (1))]), opval); + written |= (1 << 10); + TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval); + } +} else { +if (LTHI (tmp_argilo, tmp_argjlo)) { + { + UQI opval = 4; + sim_queue_qi_write (current_cpu, & CPU (h_fccr[((FLD (f_FCCk)) + (1))]), opval); + written |= (1 << 10); + TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval); + } +} else { + { + UQI opval = 1; + sim_queue_qi_write (current_cpu, & CPU (h_fccr[((FLD (f_FCCk)) + (1))]), opval); + written |= (1 << 10); + TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval); + } +} +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* mcmpuh: mcmpuh$pack $FRinti,$FRintj,$FCCk */ + +static SEM_PC +SEM_FN_NAME (frvbf,mcmpuh) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mcmpsh.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (ANDSI (FLD (f_FCCk), SUBSI (2, 1))) { +frvbf_media_cr_not_aligned (current_cpu); +} else { +{ + UHI tmp_argihi; + UHI tmp_argilo; + UHI tmp_argjhi; + UHI tmp_argjlo; +{ + tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); + tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); +} +if (GTUHI (tmp_argihi, tmp_argjhi)) { + { + UQI opval = 2; + sim_queue_qi_write (current_cpu, & CPU (h_fccr[FLD (f_FCCk)]), opval); + written |= (1 << 9); + TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval); + } +} else { +if (EQHI (tmp_argihi, tmp_argjhi)) { + { + UQI opval = 8; + sim_queue_qi_write (current_cpu, & CPU (h_fccr[FLD (f_FCCk)]), opval); + written |= (1 << 9); + TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval); + } +} else { +if (LTUHI (tmp_argihi, tmp_argjhi)) { + { + UQI opval = 4; + sim_queue_qi_write (current_cpu, & CPU (h_fccr[FLD (f_FCCk)]), opval); + written |= (1 << 9); + TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval); + } +} else { + { + UQI opval = 1; + sim_queue_qi_write (current_cpu, & CPU (h_fccr[FLD (f_FCCk)]), opval); + written |= (1 << 9); + TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval); + } +} +} +} +if (GTUHI (tmp_argilo, tmp_argjlo)) { + { + UQI opval = 2; + sim_queue_qi_write (current_cpu, & CPU (h_fccr[((FLD (f_FCCk)) + (1))]), opval); + written |= (1 << 10); + TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval); + } +} else { +if (EQHI (tmp_argilo, tmp_argjlo)) { + { + UQI opval = 8; + sim_queue_qi_write (current_cpu, & CPU (h_fccr[((FLD (f_FCCk)) + (1))]), opval); + written |= (1 << 10); + TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval); + } +} else { +if (LTUHI (tmp_argilo, tmp_argjlo)) { + { + UQI opval = 4; + sim_queue_qi_write (current_cpu, & CPU (h_fccr[((FLD (f_FCCk)) + (1))]), opval); + written |= (1 << 10); + TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval); + } +} else { + { + UQI opval = 1; + sim_queue_qi_write (current_cpu, & CPU (h_fccr[((FLD (f_FCCk)) + (1))]), opval); + written |= (1 << 10); + TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval); + } +} +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* mabshs: mabshs$pack $FRintj,$FRintk */ + +static SEM_PC +SEM_FN_NAME (frvbf,mabshs) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mabshs.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + HI tmp_arghi; + HI tmp_arglo; + { + SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRj))); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRj), opval); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } + { + SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRk))); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } + tmp_arghi = GET_H_FR_HI (((FLD (f_FRj)) + (0))); + tmp_arglo = GET_H_FR_LO (((FLD (f_FRj)) + (0))); +if (GTDI (ABSHI (tmp_arghi), 32767)) { +{ + { + UHI opval = 32767; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 8); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { +if (LTDI (ABSHI (tmp_arghi), -32768)) { +{ + { + UHI opval = -32768; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 8); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { + { + UHI opval = ABSHI (tmp_arghi); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 8); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } +} +} +if (GTDI (ABSHI (tmp_arglo), 32767)) { +{ + { + UHI opval = 32767; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 9); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +frvbf_media_overflow (current_cpu, 4); +} +} else { +if (LTDI (ABSHI (tmp_arglo), -32768)) { +{ + { + UHI opval = -32768; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 9); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +frvbf_media_overflow (current_cpu, 4); +} +} else { + { + UHI opval = ABSHI (tmp_arglo); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 9); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* maddhss: maddhss$pack $FRinti,$FRintj,$FRintk */ + +static SEM_PC +SEM_FN_NAME (frvbf,maddhss) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + HI tmp_argihi; + HI tmp_argilo; + HI tmp_argjhi; + HI tmp_argjlo; +{ + tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); + tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); +} +{ + DI tmp_tmp; + tmp_tmp = ADDHI (tmp_argihi, tmp_argjhi); +if (GTDI (tmp_tmp, 32767)) { +{ + { + UHI opval = 32767; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 9); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { +if (LTDI (tmp_tmp, -32768)) { +{ + { + UHI opval = -32768; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 9); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { + { + UHI opval = tmp_tmp; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 9); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } +} +} +} +{ + DI tmp_tmp; + tmp_tmp = ADDHI (tmp_argilo, tmp_argjlo); +if (GTDI (tmp_tmp, 32767)) { +{ + { + UHI opval = 32767; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 10); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +frvbf_media_overflow (current_cpu, 4); +} +} else { +if (LTDI (tmp_tmp, -32768)) { +{ + { + UHI opval = -32768; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 10); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +frvbf_media_overflow (current_cpu, 4); +} +} else { + { + UHI opval = tmp_tmp; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 10); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* maddhus: maddhus$pack $FRinti,$FRintj,$FRintk */ + +static SEM_PC +SEM_FN_NAME (frvbf,maddhus) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + UHI tmp_argihi; + UHI tmp_argilo; + UHI tmp_argjhi; + UHI tmp_argjlo; +{ + tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); + tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); +} +{ + DI tmp_tmp; + tmp_tmp = ADDHI (tmp_argihi, tmp_argjhi); +if (GTDI (tmp_tmp, 65535)) { +{ + { + UHI opval = 65535; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 9); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { +if (LTDI (tmp_tmp, 0)) { +{ + { + UHI opval = 0; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 9); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { + { + UHI opval = tmp_tmp; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 9); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } +} +} +} +{ + DI tmp_tmp; + tmp_tmp = ADDHI (tmp_argilo, tmp_argjlo); +if (GTDI (tmp_tmp, 65535)) { +{ + { + UHI opval = 65535; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 10); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +frvbf_media_overflow (current_cpu, 4); +} +} else { +if (LTDI (tmp_tmp, 0)) { +{ + { + UHI opval = 0; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 10); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +frvbf_media_overflow (current_cpu, 4); +} +} else { + { + UHI opval = tmp_tmp; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 10); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* msubhss: msubhss$pack $FRinti,$FRintj,$FRintk */ + +static SEM_PC +SEM_FN_NAME (frvbf,msubhss) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + HI tmp_argihi; + HI tmp_argilo; + HI tmp_argjhi; + HI tmp_argjlo; +{ + tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); + tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); +} +{ + DI tmp_tmp; + tmp_tmp = SUBHI (tmp_argihi, tmp_argjhi); +if (GTDI (tmp_tmp, 32767)) { +{ + { + UHI opval = 32767; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 9); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { +if (LTDI (tmp_tmp, -32768)) { +{ + { + UHI opval = -32768; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 9); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { + { + UHI opval = tmp_tmp; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 9); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } +} +} +} +{ + DI tmp_tmp; + tmp_tmp = SUBHI (tmp_argilo, tmp_argjlo); +if (GTDI (tmp_tmp, 32767)) { +{ + { + UHI opval = 32767; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 10); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +frvbf_media_overflow (current_cpu, 4); +} +} else { +if (LTDI (tmp_tmp, -32768)) { +{ + { + UHI opval = -32768; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 10); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +frvbf_media_overflow (current_cpu, 4); +} +} else { + { + UHI opval = tmp_tmp; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 10); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* msubhus: msubhus$pack $FRinti,$FRintj,$FRintk */ + +static SEM_PC +SEM_FN_NAME (frvbf,msubhus) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + UHI tmp_argihi; + UHI tmp_argilo; + UHI tmp_argjhi; + UHI tmp_argjlo; +{ + tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); + tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); +} +{ + DI tmp_tmp; + tmp_tmp = SUBHI (tmp_argihi, tmp_argjhi); +if (GTDI (tmp_tmp, 65535)) { +{ + { + UHI opval = 65535; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 9); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { +if (LTDI (tmp_tmp, 0)) { +{ + { + UHI opval = 0; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 9); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { + { + UHI opval = tmp_tmp; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 9); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } +} +} +} +{ + DI tmp_tmp; + tmp_tmp = SUBHI (tmp_argilo, tmp_argjlo); +if (GTDI (tmp_tmp, 65535)) { +{ + { + UHI opval = 65535; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 10); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +frvbf_media_overflow (current_cpu, 4); +} +} else { +if (LTDI (tmp_tmp, 0)) { +{ + { + UHI opval = 0; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 10); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +frvbf_media_overflow (current_cpu, 4); +} +} else { + { + UHI opval = tmp_tmp; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 10); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cmaddhss: cmaddhss$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cmaddhss) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +{ + HI tmp_argihi; + HI tmp_argilo; + HI tmp_argjhi; + HI tmp_argjlo; +{ + tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); + tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); +} +{ + DI tmp_tmp; + tmp_tmp = ADDHI (tmp_argihi, tmp_argjhi); +if (GTDI (tmp_tmp, 32767)) { +{ + { + UHI opval = 32767; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 11); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { +if (LTDI (tmp_tmp, -32768)) { +{ + { + UHI opval = -32768; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 11); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { + { + UHI opval = tmp_tmp; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 11); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } +} +} +} +{ + DI tmp_tmp; + tmp_tmp = ADDHI (tmp_argilo, tmp_argjlo); +if (GTDI (tmp_tmp, 32767)) { +{ + { + UHI opval = 32767; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 12); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +frvbf_media_overflow (current_cpu, 4); +} +} else { +if (LTDI (tmp_tmp, -32768)) { +{ + { + UHI opval = -32768; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 12); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +frvbf_media_overflow (current_cpu, 4); +} +} else { + { + UHI opval = tmp_tmp; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 12); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +} +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cmaddhus: cmaddhus$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cmaddhus) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +{ + UHI tmp_argihi; + UHI tmp_argilo; + UHI tmp_argjhi; + UHI tmp_argjlo; +{ + tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); + tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); +} +{ + DI tmp_tmp; + tmp_tmp = ADDHI (tmp_argihi, tmp_argjhi); +if (GTDI (tmp_tmp, 65535)) { +{ + { + UHI opval = 65535; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 11); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { +if (LTDI (tmp_tmp, 0)) { +{ + { + UHI opval = 0; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 11); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { + { + UHI opval = tmp_tmp; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 11); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } +} +} +} +{ + DI tmp_tmp; + tmp_tmp = ADDHI (tmp_argilo, tmp_argjlo); +if (GTDI (tmp_tmp, 65535)) { +{ + { + UHI opval = 65535; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 12); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +frvbf_media_overflow (current_cpu, 4); +} +} else { +if (LTDI (tmp_tmp, 0)) { +{ + { + UHI opval = 0; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 12); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +frvbf_media_overflow (current_cpu, 4); +} +} else { + { + UHI opval = tmp_tmp; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 12); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +} +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cmsubhss: cmsubhss$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cmsubhss) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +{ + HI tmp_argihi; + HI tmp_argilo; + HI tmp_argjhi; + HI tmp_argjlo; +{ + tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); + tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); +} +{ + DI tmp_tmp; + tmp_tmp = SUBHI (tmp_argihi, tmp_argjhi); +if (GTDI (tmp_tmp, 32767)) { +{ + { + UHI opval = 32767; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 11); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { +if (LTDI (tmp_tmp, -32768)) { +{ + { + UHI opval = -32768; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 11); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { + { + UHI opval = tmp_tmp; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 11); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } +} +} +} +{ + DI tmp_tmp; + tmp_tmp = SUBHI (tmp_argilo, tmp_argjlo); +if (GTDI (tmp_tmp, 32767)) { +{ + { + UHI opval = 32767; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 12); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +frvbf_media_overflow (current_cpu, 4); +} +} else { +if (LTDI (tmp_tmp, -32768)) { +{ + { + UHI opval = -32768; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 12); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +frvbf_media_overflow (current_cpu, 4); +} +} else { + { + UHI opval = tmp_tmp; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 12); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +} +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cmsubhus: cmsubhus$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cmsubhus) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +{ + UHI tmp_argihi; + UHI tmp_argilo; + UHI tmp_argjhi; + UHI tmp_argjlo; +{ + tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); + tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); +} +{ + DI tmp_tmp; + tmp_tmp = SUBHI (tmp_argihi, tmp_argjhi); +if (GTDI (tmp_tmp, 65535)) { +{ + { + UHI opval = 65535; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 11); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { +if (LTDI (tmp_tmp, 0)) { +{ + { + UHI opval = 0; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 11); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { + { + UHI opval = tmp_tmp; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 11); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } +} +} +} +{ + DI tmp_tmp; + tmp_tmp = SUBHI (tmp_argilo, tmp_argjlo); +if (GTDI (tmp_tmp, 65535)) { +{ + { + UHI opval = 65535; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 12); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +frvbf_media_overflow (current_cpu, 4); +} +} else { +if (LTDI (tmp_tmp, 0)) { +{ + { + UHI opval = 0; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 12); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +frvbf_media_overflow (current_cpu, 4); +} +} else { + { + UHI opval = tmp_tmp; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 12); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +} +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* mqaddhss: mqaddhss$pack $FRintieven,$FRintjeven,$FRintkeven */ + +static SEM_PC +SEM_FN_NAME (frvbf,mqaddhss) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (ORIF (ANDSI (FLD (f_FRi), SUBSI (2, 1)), ORIF (ANDSI (FLD (f_FRj), SUBSI (2, 1)), ANDSI (FLD (f_FRk), SUBSI (2, 1))))) { +frvbf_media_register_not_aligned (current_cpu); +} else { +{ + HI tmp_argihi; + HI tmp_argilo; + HI tmp_argjhi; + HI tmp_argjlo; + { + SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRk))); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + written |= (1 << 14); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } +{ + tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); + tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); +} +{ + DI tmp_tmp; + tmp_tmp = ADDHI (tmp_argihi, tmp_argjhi); +if (GTDI (tmp_tmp, 32767)) { +{ + { + UHI opval = 32767; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 15); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { +if (LTDI (tmp_tmp, -32768)) { +{ + { + UHI opval = -32768; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 15); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { + { + UHI opval = tmp_tmp; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 15); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } +} +} +} +{ + DI tmp_tmp; + tmp_tmp = ADDHI (tmp_argilo, tmp_argjlo); +if (GTDI (tmp_tmp, 32767)) { +{ + { + UHI opval = 32767; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 17); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +frvbf_media_overflow (current_cpu, 4); +} +} else { +if (LTDI (tmp_tmp, -32768)) { +{ + { + UHI opval = -32768; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 17); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +frvbf_media_overflow (current_cpu, 4); +} +} else { + { + UHI opval = tmp_tmp; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 17); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +} +} +} +{ + tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); + tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); +} +{ + DI tmp_tmp; + tmp_tmp = ADDHI (tmp_argihi, tmp_argjhi); +if (GTDI (tmp_tmp, 32767)) { +{ + { + UHI opval = 32767; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (1)), opval); + written |= (1 << 16); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } +frvbf_media_overflow (current_cpu, 2); +} +} else { +if (LTDI (tmp_tmp, -32768)) { +{ + { + UHI opval = -32768; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (1)), opval); + written |= (1 << 16); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } +frvbf_media_overflow (current_cpu, 2); +} +} else { + { + UHI opval = tmp_tmp; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (1)), opval); + written |= (1 << 16); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } +} +} +} +{ + DI tmp_tmp; + tmp_tmp = ADDHI (tmp_argilo, tmp_argjlo); +if (GTDI (tmp_tmp, 32767)) { +{ + { + UHI opval = 32767; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (1)), opval); + written |= (1 << 18); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +frvbf_media_overflow (current_cpu, 1); +} +} else { +if (LTDI (tmp_tmp, -32768)) { +{ + { + UHI opval = -32768; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (1)), opval); + written |= (1 << 18); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +frvbf_media_overflow (current_cpu, 1); +} +} else { + { + UHI opval = tmp_tmp; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (1)), opval); + written |= (1 << 18); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +} +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* mqaddhus: mqaddhus$pack $FRintieven,$FRintjeven,$FRintkeven */ + +static SEM_PC +SEM_FN_NAME (frvbf,mqaddhus) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (ORIF (ANDSI (FLD (f_FRi), SUBSI (2, 1)), ORIF (ANDSI (FLD (f_FRj), SUBSI (2, 1)), ANDSI (FLD (f_FRk), SUBSI (2, 1))))) { +frvbf_media_register_not_aligned (current_cpu); +} else { +{ + UHI tmp_argihi; + UHI tmp_argilo; + UHI tmp_argjhi; + UHI tmp_argjlo; + { + SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRk))); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + written |= (1 << 14); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } +{ + tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); + tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); +} +{ + DI tmp_tmp; + tmp_tmp = ADDHI (tmp_argihi, tmp_argjhi); +if (GTDI (tmp_tmp, 65535)) { +{ + { + UHI opval = 65535; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 15); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { +if (LTDI (tmp_tmp, 0)) { +{ + { + UHI opval = 0; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 15); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { + { + UHI opval = tmp_tmp; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 15); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } +} +} +} +{ + DI tmp_tmp; + tmp_tmp = ADDHI (tmp_argilo, tmp_argjlo); +if (GTDI (tmp_tmp, 65535)) { +{ + { + UHI opval = 65535; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 17); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +frvbf_media_overflow (current_cpu, 4); +} +} else { +if (LTDI (tmp_tmp, 0)) { +{ + { + UHI opval = 0; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 17); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +frvbf_media_overflow (current_cpu, 4); +} +} else { + { + UHI opval = tmp_tmp; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 17); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +} +} +} +{ + tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); + tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); +} +{ + DI tmp_tmp; + tmp_tmp = ADDHI (tmp_argihi, tmp_argjhi); +if (GTDI (tmp_tmp, 65535)) { +{ + { + UHI opval = 65535; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (1)), opval); + written |= (1 << 16); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } +frvbf_media_overflow (current_cpu, 2); +} +} else { +if (LTDI (tmp_tmp, 0)) { +{ + { + UHI opval = 0; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (1)), opval); + written |= (1 << 16); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } +frvbf_media_overflow (current_cpu, 2); +} +} else { + { + UHI opval = tmp_tmp; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (1)), opval); + written |= (1 << 16); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } +} +} +} +{ + DI tmp_tmp; + tmp_tmp = ADDHI (tmp_argilo, tmp_argjlo); +if (GTDI (tmp_tmp, 65535)) { +{ + { + UHI opval = 65535; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (1)), opval); + written |= (1 << 18); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +frvbf_media_overflow (current_cpu, 1); +} +} else { +if (LTDI (tmp_tmp, 0)) { +{ + { + UHI opval = 0; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (1)), opval); + written |= (1 << 18); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +frvbf_media_overflow (current_cpu, 1); +} +} else { + { + UHI opval = tmp_tmp; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (1)), opval); + written |= (1 << 18); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +} +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* mqsubhss: mqsubhss$pack $FRintieven,$FRintjeven,$FRintkeven */ + +static SEM_PC +SEM_FN_NAME (frvbf,mqsubhss) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (ORIF (ANDSI (FLD (f_FRi), SUBSI (2, 1)), ORIF (ANDSI (FLD (f_FRj), SUBSI (2, 1)), ANDSI (FLD (f_FRk), SUBSI (2, 1))))) { +frvbf_media_register_not_aligned (current_cpu); +} else { +{ + HI tmp_argihi; + HI tmp_argilo; + HI tmp_argjhi; + HI tmp_argjlo; + { + SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRk))); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + written |= (1 << 14); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } +{ + tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); + tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); +} +{ + DI tmp_tmp; + tmp_tmp = SUBHI (tmp_argihi, tmp_argjhi); +if (GTDI (tmp_tmp, 32767)) { +{ + { + UHI opval = 32767; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 15); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { +if (LTDI (tmp_tmp, -32768)) { +{ + { + UHI opval = -32768; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 15); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { + { + UHI opval = tmp_tmp; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 15); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } +} +} +} +{ + DI tmp_tmp; + tmp_tmp = SUBHI (tmp_argilo, tmp_argjlo); +if (GTDI (tmp_tmp, 32767)) { +{ + { + UHI opval = 32767; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 17); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +frvbf_media_overflow (current_cpu, 4); +} +} else { +if (LTDI (tmp_tmp, -32768)) { +{ + { + UHI opval = -32768; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 17); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +frvbf_media_overflow (current_cpu, 4); +} +} else { + { + UHI opval = tmp_tmp; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 17); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +} +} +} +{ + tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); + tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); +} +{ + DI tmp_tmp; + tmp_tmp = SUBHI (tmp_argihi, tmp_argjhi); +if (GTDI (tmp_tmp, 32767)) { +{ + { + UHI opval = 32767; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (1)), opval); + written |= (1 << 16); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } +frvbf_media_overflow (current_cpu, 2); +} +} else { +if (LTDI (tmp_tmp, -32768)) { +{ + { + UHI opval = -32768; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (1)), opval); + written |= (1 << 16); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } +frvbf_media_overflow (current_cpu, 2); +} +} else { + { + UHI opval = tmp_tmp; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (1)), opval); + written |= (1 << 16); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } +} +} +} +{ + DI tmp_tmp; + tmp_tmp = SUBHI (tmp_argilo, tmp_argjlo); +if (GTDI (tmp_tmp, 32767)) { +{ + { + UHI opval = 32767; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (1)), opval); + written |= (1 << 18); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +frvbf_media_overflow (current_cpu, 1); +} +} else { +if (LTDI (tmp_tmp, -32768)) { +{ + { + UHI opval = -32768; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (1)), opval); + written |= (1 << 18); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +frvbf_media_overflow (current_cpu, 1); +} +} else { + { + UHI opval = tmp_tmp; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (1)), opval); + written |= (1 << 18); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +} +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* mqsubhus: mqsubhus$pack $FRintieven,$FRintjeven,$FRintkeven */ + +static SEM_PC +SEM_FN_NAME (frvbf,mqsubhus) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (ORIF (ANDSI (FLD (f_FRi), SUBSI (2, 1)), ORIF (ANDSI (FLD (f_FRj), SUBSI (2, 1)), ANDSI (FLD (f_FRk), SUBSI (2, 1))))) { +frvbf_media_register_not_aligned (current_cpu); +} else { +{ + UHI tmp_argihi; + UHI tmp_argilo; + UHI tmp_argjhi; + UHI tmp_argjlo; + { + SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRk))); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + written |= (1 << 14); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } +{ + tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); + tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); +} +{ + DI tmp_tmp; + tmp_tmp = SUBHI (tmp_argihi, tmp_argjhi); +if (GTDI (tmp_tmp, 65535)) { +{ + { + UHI opval = 65535; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 15); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { +if (LTDI (tmp_tmp, 0)) { +{ + { + UHI opval = 0; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 15); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { + { + UHI opval = tmp_tmp; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 15); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } +} +} +} +{ + DI tmp_tmp; + tmp_tmp = SUBHI (tmp_argilo, tmp_argjlo); +if (GTDI (tmp_tmp, 65535)) { +{ + { + UHI opval = 65535; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 17); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +frvbf_media_overflow (current_cpu, 4); +} +} else { +if (LTDI (tmp_tmp, 0)) { +{ + { + UHI opval = 0; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 17); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +frvbf_media_overflow (current_cpu, 4); +} +} else { + { + UHI opval = tmp_tmp; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 17); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +} +} +} +{ + tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); + tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); +} +{ + DI tmp_tmp; + tmp_tmp = SUBHI (tmp_argihi, tmp_argjhi); +if (GTDI (tmp_tmp, 65535)) { +{ + { + UHI opval = 65535; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (1)), opval); + written |= (1 << 16); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } +frvbf_media_overflow (current_cpu, 2); +} +} else { +if (LTDI (tmp_tmp, 0)) { +{ + { + UHI opval = 0; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (1)), opval); + written |= (1 << 16); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } +frvbf_media_overflow (current_cpu, 2); +} +} else { + { + UHI opval = tmp_tmp; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (1)), opval); + written |= (1 << 16); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } +} +} +} +{ + DI tmp_tmp; + tmp_tmp = SUBHI (tmp_argilo, tmp_argjlo); +if (GTDI (tmp_tmp, 65535)) { +{ + { + UHI opval = 65535; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (1)), opval); + written |= (1 << 18); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +frvbf_media_overflow (current_cpu, 1); +} +} else { +if (LTDI (tmp_tmp, 0)) { +{ + { + UHI opval = 0; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (1)), opval); + written |= (1 << 18); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +frvbf_media_overflow (current_cpu, 1); +} +} else { + { + UHI opval = tmp_tmp; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (1)), opval); + written |= (1 << 18); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +} +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cmqaddhss: cmqaddhss$pack $FRintieven,$FRintjeven,$FRintkeven,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cmqaddhss) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (ORIF (ANDSI (FLD (f_FRi), SUBSI (2, 1)), ORIF (ANDSI (FLD (f_FRj), SUBSI (2, 1)), ANDSI (FLD (f_FRk), SUBSI (2, 1))))) { +frvbf_media_register_not_aligned (current_cpu); +} else { +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +{ + HI tmp_argihi; + HI tmp_argilo; + HI tmp_argjhi; + HI tmp_argjlo; + { + SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRk))); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + written |= (1 << 16); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } +{ + tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); + tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); +} +{ + DI tmp_tmp; + tmp_tmp = ADDHI (tmp_argihi, tmp_argjhi); +if (GTDI (tmp_tmp, 32767)) { +{ + { + UHI opval = 32767; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 17); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { +if (LTDI (tmp_tmp, -32768)) { +{ + { + UHI opval = -32768; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 17); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { + { + UHI opval = tmp_tmp; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 17); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } +} +} +} +{ + DI tmp_tmp; + tmp_tmp = ADDHI (tmp_argilo, tmp_argjlo); +if (GTDI (tmp_tmp, 32767)) { +{ + { + UHI opval = 32767; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 19); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +frvbf_media_overflow (current_cpu, 4); +} +} else { +if (LTDI (tmp_tmp, -32768)) { +{ + { + UHI opval = -32768; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 19); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +frvbf_media_overflow (current_cpu, 4); +} +} else { + { + UHI opval = tmp_tmp; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 19); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +} +} +} +{ + tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); + tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); +} +{ + DI tmp_tmp; + tmp_tmp = ADDHI (tmp_argihi, tmp_argjhi); +if (GTDI (tmp_tmp, 32767)) { +{ + { + UHI opval = 32767; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (1)), opval); + written |= (1 << 18); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } +frvbf_media_overflow (current_cpu, 2); +} +} else { +if (LTDI (tmp_tmp, -32768)) { +{ + { + UHI opval = -32768; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (1)), opval); + written |= (1 << 18); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } +frvbf_media_overflow (current_cpu, 2); +} +} else { + { + UHI opval = tmp_tmp; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (1)), opval); + written |= (1 << 18); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } +} +} +} +{ + DI tmp_tmp; + tmp_tmp = ADDHI (tmp_argilo, tmp_argjlo); +if (GTDI (tmp_tmp, 32767)) { +{ + { + UHI opval = 32767; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (1)), opval); + written |= (1 << 20); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +frvbf_media_overflow (current_cpu, 1); +} +} else { +if (LTDI (tmp_tmp, -32768)) { +{ + { + UHI opval = -32768; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (1)), opval); + written |= (1 << 20); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +frvbf_media_overflow (current_cpu, 1); +} +} else { + { + UHI opval = tmp_tmp; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (1)), opval); + written |= (1 << 20); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +} +} +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cmqaddhus: cmqaddhus$pack $FRintieven,$FRintjeven,$FRintkeven,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cmqaddhus) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (ORIF (ANDSI (FLD (f_FRi), SUBSI (2, 1)), ORIF (ANDSI (FLD (f_FRj), SUBSI (2, 1)), ANDSI (FLD (f_FRk), SUBSI (2, 1))))) { +frvbf_media_register_not_aligned (current_cpu); +} else { +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +{ + UHI tmp_argihi; + UHI tmp_argilo; + UHI tmp_argjhi; + UHI tmp_argjlo; + { + SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRk))); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + written |= (1 << 16); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } +{ + tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); + tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); +} +{ + DI tmp_tmp; + tmp_tmp = ADDHI (tmp_argihi, tmp_argjhi); +if (GTDI (tmp_tmp, 65535)) { +{ + { + UHI opval = 65535; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 17); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { +if (LTDI (tmp_tmp, 0)) { +{ + { + UHI opval = 0; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 17); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { + { + UHI opval = tmp_tmp; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 17); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } +} +} +} +{ + DI tmp_tmp; + tmp_tmp = ADDHI (tmp_argilo, tmp_argjlo); +if (GTDI (tmp_tmp, 65535)) { +{ + { + UHI opval = 65535; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 19); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +frvbf_media_overflow (current_cpu, 4); +} +} else { +if (LTDI (tmp_tmp, 0)) { +{ + { + UHI opval = 0; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 19); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +frvbf_media_overflow (current_cpu, 4); +} +} else { + { + UHI opval = tmp_tmp; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 19); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +} +} +} +{ + tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); + tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); +} +{ + DI tmp_tmp; + tmp_tmp = ADDHI (tmp_argihi, tmp_argjhi); +if (GTDI (tmp_tmp, 65535)) { +{ + { + UHI opval = 65535; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (1)), opval); + written |= (1 << 18); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } +frvbf_media_overflow (current_cpu, 2); +} +} else { +if (LTDI (tmp_tmp, 0)) { +{ + { + UHI opval = 0; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (1)), opval); + written |= (1 << 18); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } +frvbf_media_overflow (current_cpu, 2); +} +} else { + { + UHI opval = tmp_tmp; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (1)), opval); + written |= (1 << 18); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } +} +} +} +{ + DI tmp_tmp; + tmp_tmp = ADDHI (tmp_argilo, tmp_argjlo); +if (GTDI (tmp_tmp, 65535)) { +{ + { + UHI opval = 65535; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (1)), opval); + written |= (1 << 20); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +frvbf_media_overflow (current_cpu, 1); +} +} else { +if (LTDI (tmp_tmp, 0)) { +{ + { + UHI opval = 0; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (1)), opval); + written |= (1 << 20); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +frvbf_media_overflow (current_cpu, 1); +} +} else { + { + UHI opval = tmp_tmp; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (1)), opval); + written |= (1 << 20); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +} +} +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cmqsubhss: cmqsubhss$pack $FRintieven,$FRintjeven,$FRintkeven,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cmqsubhss) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (ORIF (ANDSI (FLD (f_FRi), SUBSI (2, 1)), ORIF (ANDSI (FLD (f_FRj), SUBSI (2, 1)), ANDSI (FLD (f_FRk), SUBSI (2, 1))))) { +frvbf_media_register_not_aligned (current_cpu); +} else { +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +{ + HI tmp_argihi; + HI tmp_argilo; + HI tmp_argjhi; + HI tmp_argjlo; + { + SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRk))); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + written |= (1 << 16); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } +{ + tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); + tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); +} +{ + DI tmp_tmp; + tmp_tmp = SUBHI (tmp_argihi, tmp_argjhi); +if (GTDI (tmp_tmp, 32767)) { +{ + { + UHI opval = 32767; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 17); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { +if (LTDI (tmp_tmp, -32768)) { +{ + { + UHI opval = -32768; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 17); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { + { + UHI opval = tmp_tmp; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 17); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } +} +} +} +{ + DI tmp_tmp; + tmp_tmp = SUBHI (tmp_argilo, tmp_argjlo); +if (GTDI (tmp_tmp, 32767)) { +{ + { + UHI opval = 32767; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 19); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +frvbf_media_overflow (current_cpu, 4); +} +} else { +if (LTDI (tmp_tmp, -32768)) { +{ + { + UHI opval = -32768; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 19); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +frvbf_media_overflow (current_cpu, 4); +} +} else { + { + UHI opval = tmp_tmp; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 19); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +} +} +} +{ + tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); + tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); +} +{ + DI tmp_tmp; + tmp_tmp = SUBHI (tmp_argihi, tmp_argjhi); +if (GTDI (tmp_tmp, 32767)) { +{ + { + UHI opval = 32767; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (1)), opval); + written |= (1 << 18); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } +frvbf_media_overflow (current_cpu, 2); +} +} else { +if (LTDI (tmp_tmp, -32768)) { +{ + { + UHI opval = -32768; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (1)), opval); + written |= (1 << 18); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } +frvbf_media_overflow (current_cpu, 2); +} +} else { + { + UHI opval = tmp_tmp; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (1)), opval); + written |= (1 << 18); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } +} +} +} +{ + DI tmp_tmp; + tmp_tmp = SUBHI (tmp_argilo, tmp_argjlo); +if (GTDI (tmp_tmp, 32767)) { +{ + { + UHI opval = 32767; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (1)), opval); + written |= (1 << 20); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +frvbf_media_overflow (current_cpu, 1); +} +} else { +if (LTDI (tmp_tmp, -32768)) { +{ + { + UHI opval = -32768; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (1)), opval); + written |= (1 << 20); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +frvbf_media_overflow (current_cpu, 1); +} +} else { + { + UHI opval = tmp_tmp; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (1)), opval); + written |= (1 << 20); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +} +} +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cmqsubhus: cmqsubhus$pack $FRintieven,$FRintjeven,$FRintkeven,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cmqsubhus) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (ORIF (ANDSI (FLD (f_FRi), SUBSI (2, 1)), ORIF (ANDSI (FLD (f_FRj), SUBSI (2, 1)), ANDSI (FLD (f_FRk), SUBSI (2, 1))))) { +frvbf_media_register_not_aligned (current_cpu); +} else { +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +{ + UHI tmp_argihi; + UHI tmp_argilo; + UHI tmp_argjhi; + UHI tmp_argjlo; + { + SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRk))); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + written |= (1 << 16); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } +{ + tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); + tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); +} +{ + DI tmp_tmp; + tmp_tmp = SUBHI (tmp_argihi, tmp_argjhi); +if (GTDI (tmp_tmp, 65535)) { +{ + { + UHI opval = 65535; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 17); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { +if (LTDI (tmp_tmp, 0)) { +{ + { + UHI opval = 0; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 17); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { + { + UHI opval = tmp_tmp; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 17); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } +} +} +} +{ + DI tmp_tmp; + tmp_tmp = SUBHI (tmp_argilo, tmp_argjlo); +if (GTDI (tmp_tmp, 65535)) { +{ + { + UHI opval = 65535; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 19); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +frvbf_media_overflow (current_cpu, 4); +} +} else { +if (LTDI (tmp_tmp, 0)) { +{ + { + UHI opval = 0; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 19); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +frvbf_media_overflow (current_cpu, 4); +} +} else { + { + UHI opval = tmp_tmp; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 19); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +} +} +} +{ + tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); + tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); +} +{ + DI tmp_tmp; + tmp_tmp = SUBHI (tmp_argihi, tmp_argjhi); +if (GTDI (tmp_tmp, 65535)) { +{ + { + UHI opval = 65535; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (1)), opval); + written |= (1 << 18); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } +frvbf_media_overflow (current_cpu, 2); +} +} else { +if (LTDI (tmp_tmp, 0)) { +{ + { + UHI opval = 0; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (1)), opval); + written |= (1 << 18); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } +frvbf_media_overflow (current_cpu, 2); +} +} else { + { + UHI opval = tmp_tmp; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (1)), opval); + written |= (1 << 18); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } +} +} +} +{ + DI tmp_tmp; + tmp_tmp = SUBHI (tmp_argilo, tmp_argjlo); +if (GTDI (tmp_tmp, 65535)) { +{ + { + UHI opval = 65535; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (1)), opval); + written |= (1 << 20); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +frvbf_media_overflow (current_cpu, 1); +} +} else { +if (LTDI (tmp_tmp, 0)) { +{ + { + UHI opval = 0; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (1)), opval); + written |= (1 << 20); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +frvbf_media_overflow (current_cpu, 1); +} +} else { + { + UHI opval = tmp_tmp; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (1)), opval); + written |= (1 << 20); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +} +} +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* maddaccs: maddaccs$pack $ACC40Si,$ACC40Sk */ + +static SEM_PC +SEM_FN_NAME (frvbf,maddaccs) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdasaccs.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Si))) { +if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Sk))) { +if (ANDSI (FLD (f_ACC40Si), SUBSI (2, 1))) { +frvbf_media_acc_not_aligned (current_cpu); +} else { +{ + DI tmp_tmp; + tmp_tmp = ADDDI (GET_H_ACC40S (FLD (f_ACC40Si)), GET_H_ACC40S (((FLD (f_ACC40Si)) + (1)))); +if (GTDI (tmp_tmp, 549755813887)) { +{ + { + DI opval = 549755813887; + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { +if (LTDI (tmp_tmp, INVDI (549755813887))) { +{ + { + DI opval = INVDI (549755813887); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { + { + DI opval = tmp_tmp; + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +} +} +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* msubaccs: msubaccs$pack $ACC40Si,$ACC40Sk */ + +static SEM_PC +SEM_FN_NAME (frvbf,msubaccs) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdasaccs.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Si))) { +if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Sk))) { +if (ANDSI (FLD (f_ACC40Si), SUBSI (2, 1))) { +frvbf_media_acc_not_aligned (current_cpu); +} else { +{ + DI tmp_tmp; + tmp_tmp = SUBDI (GET_H_ACC40S (FLD (f_ACC40Si)), GET_H_ACC40S (((FLD (f_ACC40Si)) + (1)))); +if (GTDI (tmp_tmp, 549755813887)) { +{ + { + DI opval = 549755813887; + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { +if (LTDI (tmp_tmp, INVDI (549755813887))) { +{ + { + DI opval = INVDI (549755813887); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { + { + DI opval = tmp_tmp; + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +} +} +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* mdaddaccs: mdaddaccs$pack $ACC40Si,$ACC40Sk */ + +static SEM_PC +SEM_FN_NAME (frvbf,mdaddaccs) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdasaccs.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Si))) { +if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Sk))) { +if (ANDSI (FLD (f_ACC40Si), SUBSI (4, 1))) { +frvbf_media_acc_not_aligned (current_cpu); +} else { +if (ANDSI (FLD (f_ACC40Sk), SUBSI (2, 1))) { +frvbf_media_acc_not_aligned (current_cpu); +} else { +{ +{ + DI tmp_tmp; + tmp_tmp = ADDDI (GET_H_ACC40S (FLD (f_ACC40Si)), GET_H_ACC40S (((FLD (f_ACC40Si)) + (1)))); +if (GTDI (tmp_tmp, 549755813887)) { +{ + { + DI opval = 549755813887; + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { +if (LTDI (tmp_tmp, INVDI (549755813887))) { +{ + { + DI opval = INVDI (549755813887); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { + { + DI opval = tmp_tmp; + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +} +} +} +{ + DI tmp_tmp; + tmp_tmp = ADDDI (GET_H_ACC40S (((FLD (f_ACC40Si)) + (2))), GET_H_ACC40S (((FLD (f_ACC40Si)) + (3)))); +if (GTDI (tmp_tmp, 549755813887)) { +{ + { + DI opval = 549755813887; + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval); + written |= (1 << 7); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 4); +} +} else { +if (LTDI (tmp_tmp, INVDI (549755813887))) { +{ + { + DI opval = INVDI (549755813887); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval); + written |= (1 << 7); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 4); +} +} else { + { + DI opval = tmp_tmp; + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval); + written |= (1 << 7); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +} +} +} +} +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* mdsubaccs: mdsubaccs$pack $ACC40Si,$ACC40Sk */ + +static SEM_PC +SEM_FN_NAME (frvbf,mdsubaccs) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdasaccs.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Si))) { +if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Sk))) { +if (ANDSI (FLD (f_ACC40Si), SUBSI (4, 1))) { +frvbf_media_acc_not_aligned (current_cpu); +} else { +if (ANDSI (FLD (f_ACC40Sk), SUBSI (2, 1))) { +frvbf_media_acc_not_aligned (current_cpu); +} else { +{ +{ + DI tmp_tmp; + tmp_tmp = SUBDI (GET_H_ACC40S (FLD (f_ACC40Si)), GET_H_ACC40S (((FLD (f_ACC40Si)) + (1)))); +if (GTDI (tmp_tmp, 549755813887)) { +{ + { + DI opval = 549755813887; + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { +if (LTDI (tmp_tmp, INVDI (549755813887))) { +{ + { + DI opval = INVDI (549755813887); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { + { + DI opval = tmp_tmp; + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +} +} +} +{ + DI tmp_tmp; + tmp_tmp = SUBDI (GET_H_ACC40S (((FLD (f_ACC40Si)) + (2))), GET_H_ACC40S (((FLD (f_ACC40Si)) + (3)))); +if (GTDI (tmp_tmp, 549755813887)) { +{ + { + DI opval = 549755813887; + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval); + written |= (1 << 7); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 4); +} +} else { +if (LTDI (tmp_tmp, INVDI (549755813887))) { +{ + { + DI opval = INVDI (549755813887); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval); + written |= (1 << 7); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 4); +} +} else { + { + DI opval = tmp_tmp; + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval); + written |= (1 << 7); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +} +} +} +} +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* masaccs: masaccs$pack $ACC40Si,$ACC40Sk */ + +static SEM_PC +SEM_FN_NAME (frvbf,masaccs) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdasaccs.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Si))) { +if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Sk))) { +if (ANDSI (FLD (f_ACC40Si), SUBSI (2, 1))) { +frvbf_media_acc_not_aligned (current_cpu); +} else { +if (ANDSI (FLD (f_ACC40Sk), SUBSI (2, 1))) { +frvbf_media_acc_not_aligned (current_cpu); +} else { +{ +{ + DI tmp_tmp; + tmp_tmp = ADDDI (GET_H_ACC40S (FLD (f_ACC40Si)), GET_H_ACC40S (((FLD (f_ACC40Si)) + (1)))); +if (GTDI (tmp_tmp, 549755813887)) { +{ + { + DI opval = 549755813887; + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { +if (LTDI (tmp_tmp, INVDI (549755813887))) { +{ + { + DI opval = INVDI (549755813887); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { + { + DI opval = tmp_tmp; + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +} +} +} +{ + DI tmp_tmp; + tmp_tmp = SUBDI (GET_H_ACC40S (FLD (f_ACC40Si)), GET_H_ACC40S (((FLD (f_ACC40Si)) + (1)))); +if (GTDI (tmp_tmp, 549755813887)) { +{ + { + DI opval = 549755813887; + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval); + written |= (1 << 5); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 4); +} +} else { +if (LTDI (tmp_tmp, INVDI (549755813887))) { +{ + { + DI opval = INVDI (549755813887); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval); + written |= (1 << 5); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 4); +} +} else { + { + DI opval = tmp_tmp; + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval); + written |= (1 << 5); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +} +} +} +} +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* mdasaccs: mdasaccs$pack $ACC40Si,$ACC40Sk */ + +static SEM_PC +SEM_FN_NAME (frvbf,mdasaccs) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdasaccs.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Si))) { +if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Sk))) { +if (ANDSI (FLD (f_ACC40Si), SUBSI (4, 1))) { +frvbf_media_acc_not_aligned (current_cpu); +} else { +if (ANDSI (FLD (f_ACC40Sk), SUBSI (4, 1))) { +frvbf_media_acc_not_aligned (current_cpu); +} else { +{ +{ + DI tmp_tmp; + tmp_tmp = ADDDI (GET_H_ACC40S (FLD (f_ACC40Si)), GET_H_ACC40S (((FLD (f_ACC40Si)) + (1)))); +if (GTDI (tmp_tmp, 549755813887)) { +{ + { + DI opval = 549755813887; + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { +if (LTDI (tmp_tmp, INVDI (549755813887))) { +{ + { + DI opval = INVDI (549755813887); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { + { + DI opval = tmp_tmp; + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +} +} +} +{ + DI tmp_tmp; + tmp_tmp = SUBDI (GET_H_ACC40S (FLD (f_ACC40Si)), GET_H_ACC40S (((FLD (f_ACC40Si)) + (1)))); +if (GTDI (tmp_tmp, 549755813887)) { +{ + { + DI opval = 549755813887; + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval); + written |= (1 << 7); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 4); +} +} else { +if (LTDI (tmp_tmp, INVDI (549755813887))) { +{ + { + DI opval = INVDI (549755813887); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval); + written |= (1 << 7); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 4); +} +} else { + { + DI opval = tmp_tmp; + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval); + written |= (1 << 7); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +} +} +} +{ + DI tmp_tmp; + tmp_tmp = ADDDI (GET_H_ACC40S (((FLD (f_ACC40Si)) + (2))), GET_H_ACC40S (((FLD (f_ACC40Si)) + (3)))); +if (GTDI (tmp_tmp, 549755813887)) { +{ + { + DI opval = 549755813887; + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (2)), opval); + written |= (1 << 8); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 2); +} +} else { +if (LTDI (tmp_tmp, INVDI (549755813887))) { +{ + { + DI opval = INVDI (549755813887); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (2)), opval); + written |= (1 << 8); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 2); +} +} else { + { + DI opval = tmp_tmp; + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (2)), opval); + written |= (1 << 8); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +} +} +} +{ + DI tmp_tmp; + tmp_tmp = SUBDI (GET_H_ACC40S (((FLD (f_ACC40Si)) + (2))), GET_H_ACC40S (((FLD (f_ACC40Si)) + (3)))); +if (GTDI (tmp_tmp, 549755813887)) { +{ + { + DI opval = 549755813887; + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (3)), opval); + written |= (1 << 9); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 1); +} +} else { +if (LTDI (tmp_tmp, INVDI (549755813887))) { +{ + { + DI opval = INVDI (549755813887); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (3)), opval); + written |= (1 << 9); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 1); +} +} else { + { + DI opval = tmp_tmp; + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (3)), opval); + written |= (1 << 9); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +} +} +} +} +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* mmulhs: mmulhs$pack $FRinti,$FRintj,$ACC40Sk */ + +static SEM_PC +SEM_FN_NAME (frvbf,mmulhs) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Sk))) { +if (ANDSI (FLD (f_ACC40Sk), SUBSI (2, 1))) { +frvbf_media_acc_not_aligned (current_cpu); +} else { +{ + HI tmp_argihi; + HI tmp_argilo; + HI tmp_argjhi; + HI tmp_argjlo; +{ + tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); + tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); +} + { + DI opval = MULDI (EXTHIDI (tmp_argihi), EXTHIDI (tmp_argjhi)); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval); + written |= (1 << 9); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } + { + DI opval = MULDI (EXTHIDI (tmp_argilo), EXTHIDI (tmp_argjlo)); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval); + written |= (1 << 10); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* mmulhu: mmulhu$pack $FRinti,$FRintj,$ACC40Sk */ + +static SEM_PC +SEM_FN_NAME (frvbf,mmulhu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Sk))) { +if (ANDSI (FLD (f_ACC40Sk), SUBSI (2, 1))) { +frvbf_media_acc_not_aligned (current_cpu); +} else { +{ + UHI tmp_argihi; + UHI tmp_argilo; + UHI tmp_argjhi; + UHI tmp_argjlo; +{ + tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); + tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); +} + { + DI opval = MULDI (ZEXTHIDI (tmp_argihi), ZEXTHIDI (tmp_argjhi)); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval); + written |= (1 << 9); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } + { + DI opval = MULDI (ZEXTHIDI (tmp_argilo), ZEXTHIDI (tmp_argjlo)); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval); + written |= (1 << 10); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* mmulxhs: mmulxhs$pack $FRinti,$FRintj,$ACC40Sk */ + +static SEM_PC +SEM_FN_NAME (frvbf,mmulxhs) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Sk))) { +if (ANDSI (FLD (f_ACC40Sk), SUBSI (2, 1))) { +frvbf_media_acc_not_aligned (current_cpu); +} else { +{ + HI tmp_argihi; + HI tmp_argilo; + HI tmp_argjhi; + HI tmp_argjlo; +{ + tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); + tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); +} + { + DI opval = MULDI (EXTHIDI (tmp_argihi), EXTHIDI (tmp_argjlo)); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval); + written |= (1 << 9); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } + { + DI opval = MULDI (EXTHIDI (tmp_argilo), EXTHIDI (tmp_argjhi)); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval); + written |= (1 << 10); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* mmulxhu: mmulxhu$pack $FRinti,$FRintj,$ACC40Sk */ + +static SEM_PC +SEM_FN_NAME (frvbf,mmulxhu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Sk))) { +if (ANDSI (FLD (f_ACC40Sk), SUBSI (2, 1))) { +frvbf_media_acc_not_aligned (current_cpu); +} else { +{ + UHI tmp_argihi; + UHI tmp_argilo; + UHI tmp_argjhi; + UHI tmp_argjlo; +{ + tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); + tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); +} + { + DI opval = MULDI (ZEXTHIDI (tmp_argihi), ZEXTHIDI (tmp_argjlo)); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval); + written |= (1 << 9); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } + { + DI opval = MULDI (ZEXTHIDI (tmp_argilo), ZEXTHIDI (tmp_argjhi)); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval); + written |= (1 << 10); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cmmulhs: cmmulhs$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cmmulhs) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Sk))) { +if (ANDSI (FLD (f_ACC40Sk), SUBSI (2, 1))) { +frvbf_media_acc_not_aligned (current_cpu); +} else { +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +{ + HI tmp_argihi; + HI tmp_argilo; + HI tmp_argjhi; + HI tmp_argjlo; +{ + tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); + tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); +} + { + DI opval = MULDI (EXTHIDI (tmp_argihi), EXTHIDI (tmp_argjhi)); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval); + written |= (1 << 11); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } + { + DI opval = MULDI (EXTHIDI (tmp_argilo), EXTHIDI (tmp_argjlo)); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval); + written |= (1 << 12); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cmmulhu: cmmulhu$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cmmulhu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Sk))) { +if (ANDSI (FLD (f_ACC40Sk), SUBSI (2, 1))) { +frvbf_media_acc_not_aligned (current_cpu); +} else { +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +{ + UHI tmp_argihi; + UHI tmp_argilo; + UHI tmp_argjhi; + UHI tmp_argjlo; +{ + tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); + tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); +} + { + DI opval = MULDI (ZEXTHIDI (tmp_argihi), ZEXTHIDI (tmp_argjhi)); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval); + written |= (1 << 11); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } + { + DI opval = MULDI (ZEXTHIDI (tmp_argilo), ZEXTHIDI (tmp_argjlo)); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval); + written |= (1 << 12); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* mqmulhs: mqmulhs$pack $FRintieven,$FRintjeven,$ACC40Sk */ + +static SEM_PC +SEM_FN_NAME (frvbf,mqmulhs) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Sk))) { +if (ANDSI (FLD (f_ACC40Sk), SUBSI (4, 1))) { +frvbf_media_acc_not_aligned (current_cpu); +} else { +if (ORIF (ANDSI (FLD (f_FRi), SUBSI (2, 1)), ANDSI (FLD (f_FRj), SUBSI (2, 1)))) { +frvbf_media_register_not_aligned (current_cpu); +} else { +{ + HI tmp_argihi; + HI tmp_argilo; + HI tmp_argjhi; + HI tmp_argjlo; +{ + tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); + tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); +} + { + DI opval = MULDI (EXTHIDI (tmp_argihi), EXTHIDI (tmp_argjhi)); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval); + written |= (1 << 13); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } + { + DI opval = MULDI (EXTHIDI (tmp_argilo), EXTHIDI (tmp_argjlo)); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval); + written |= (1 << 14); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +{ + tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); + tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); +} + { + DI opval = MULDI (EXTHIDI (tmp_argihi), EXTHIDI (tmp_argjhi)); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (2)), opval); + written |= (1 << 15); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } + { + DI opval = MULDI (EXTHIDI (tmp_argilo), EXTHIDI (tmp_argjlo)); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (3)), opval); + written |= (1 << 16); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* mqmulhu: mqmulhu$pack $FRintieven,$FRintjeven,$ACC40Sk */ + +static SEM_PC +SEM_FN_NAME (frvbf,mqmulhu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Sk))) { +if (ANDSI (FLD (f_ACC40Sk), SUBSI (4, 1))) { +frvbf_media_acc_not_aligned (current_cpu); +} else { +if (ORIF (ANDSI (FLD (f_FRi), SUBSI (2, 1)), ANDSI (FLD (f_FRj), SUBSI (2, 1)))) { +frvbf_media_register_not_aligned (current_cpu); +} else { +{ + UHI tmp_argihi; + UHI tmp_argilo; + UHI tmp_argjhi; + UHI tmp_argjlo; +{ + tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); + tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); +} + { + DI opval = MULDI (ZEXTHIDI (tmp_argihi), ZEXTHIDI (tmp_argjhi)); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval); + written |= (1 << 13); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } + { + DI opval = MULDI (ZEXTHIDI (tmp_argilo), ZEXTHIDI (tmp_argjlo)); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval); + written |= (1 << 14); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +{ + tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); + tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); +} + { + DI opval = MULDI (ZEXTHIDI (tmp_argihi), ZEXTHIDI (tmp_argjhi)); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (2)), opval); + written |= (1 << 15); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } + { + DI opval = MULDI (ZEXTHIDI (tmp_argilo), ZEXTHIDI (tmp_argjlo)); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (3)), opval); + written |= (1 << 16); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* mqmulxhs: mqmulxhs$pack $FRintieven,$FRintjeven,$ACC40Sk */ + +static SEM_PC +SEM_FN_NAME (frvbf,mqmulxhs) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Sk))) { +if (ANDSI (FLD (f_ACC40Sk), SUBSI (4, 1))) { +frvbf_media_acc_not_aligned (current_cpu); +} else { +if (ORIF (ANDSI (FLD (f_FRi), SUBSI (2, 1)), ANDSI (FLD (f_FRj), SUBSI (2, 1)))) { +frvbf_media_register_not_aligned (current_cpu); +} else { +{ + HI tmp_argihi; + HI tmp_argilo; + HI tmp_argjhi; + HI tmp_argjlo; +{ + tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); + tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); +} + { + DI opval = MULDI (EXTHIDI (tmp_argihi), EXTHIDI (tmp_argjlo)); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval); + written |= (1 << 13); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } + { + DI opval = MULDI (EXTHIDI (tmp_argilo), EXTHIDI (tmp_argjhi)); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval); + written |= (1 << 14); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +{ + tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); + tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); +} + { + DI opval = MULDI (EXTHIDI (tmp_argihi), EXTHIDI (tmp_argjlo)); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (2)), opval); + written |= (1 << 15); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } + { + DI opval = MULDI (EXTHIDI (tmp_argilo), EXTHIDI (tmp_argjhi)); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (3)), opval); + written |= (1 << 16); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* mqmulxhu: mqmulxhu$pack $FRintieven,$FRintjeven,$ACC40Sk */ + +static SEM_PC +SEM_FN_NAME (frvbf,mqmulxhu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Sk))) { +if (ANDSI (FLD (f_ACC40Sk), SUBSI (4, 1))) { +frvbf_media_acc_not_aligned (current_cpu); +} else { +if (ORIF (ANDSI (FLD (f_FRi), SUBSI (2, 1)), ANDSI (FLD (f_FRj), SUBSI (2, 1)))) { +frvbf_media_register_not_aligned (current_cpu); +} else { +{ + UHI tmp_argihi; + UHI tmp_argilo; + UHI tmp_argjhi; + UHI tmp_argjlo; +{ + tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); + tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); +} + { + DI opval = MULDI (ZEXTHIDI (tmp_argihi), ZEXTHIDI (tmp_argjlo)); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval); + written |= (1 << 13); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } + { + DI opval = MULDI (ZEXTHIDI (tmp_argilo), ZEXTHIDI (tmp_argjhi)); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval); + written |= (1 << 14); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +{ + tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); + tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); +} + { + DI opval = MULDI (ZEXTHIDI (tmp_argihi), ZEXTHIDI (tmp_argjlo)); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (2)), opval); + written |= (1 << 15); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } + { + DI opval = MULDI (ZEXTHIDI (tmp_argilo), ZEXTHIDI (tmp_argjhi)); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (3)), opval); + written |= (1 << 16); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cmqmulhs: cmqmulhs$pack $FRintieven,$FRintjeven,$ACC40Sk,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cmqmulhs) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Sk))) { +if (ANDSI (FLD (f_ACC40Sk), SUBSI (4, 1))) { +frvbf_media_acc_not_aligned (current_cpu); +} else { +if (ORIF (ANDSI (FLD (f_FRi), SUBSI (2, 1)), ANDSI (FLD (f_FRj), SUBSI (2, 1)))) { +frvbf_media_register_not_aligned (current_cpu); +} else { +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +{ + HI tmp_argihi; + HI tmp_argilo; + HI tmp_argjhi; + HI tmp_argjlo; +{ + tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); + tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); +} + { + DI opval = MULDI (EXTHIDI (tmp_argihi), EXTHIDI (tmp_argjhi)); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval); + written |= (1 << 15); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } + { + DI opval = MULDI (EXTHIDI (tmp_argilo), EXTHIDI (tmp_argjlo)); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval); + written |= (1 << 16); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +{ + tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); + tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); +} + { + DI opval = MULDI (EXTHIDI (tmp_argihi), EXTHIDI (tmp_argjhi)); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (2)), opval); + written |= (1 << 17); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } + { + DI opval = MULDI (EXTHIDI (tmp_argilo), EXTHIDI (tmp_argjlo)); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (3)), opval); + written |= (1 << 18); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +} +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cmqmulhu: cmqmulhu$pack $FRintieven,$FRintjeven,$ACC40Sk,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cmqmulhu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Sk))) { +if (ANDSI (FLD (f_ACC40Sk), SUBSI (4, 1))) { +frvbf_media_acc_not_aligned (current_cpu); +} else { +if (ORIF (ANDSI (FLD (f_FRi), SUBSI (2, 1)), ANDSI (FLD (f_FRj), SUBSI (2, 1)))) { +frvbf_media_register_not_aligned (current_cpu); +} else { +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +{ + UHI tmp_argihi; + UHI tmp_argilo; + UHI tmp_argjhi; + UHI tmp_argjlo; +{ + tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); + tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); +} + { + DI opval = MULDI (ZEXTHIDI (tmp_argihi), ZEXTHIDI (tmp_argjhi)); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval); + written |= (1 << 15); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } + { + DI opval = MULDI (ZEXTHIDI (tmp_argilo), ZEXTHIDI (tmp_argjlo)); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval); + written |= (1 << 16); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +{ + tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); + tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); +} + { + DI opval = MULDI (ZEXTHIDI (tmp_argihi), ZEXTHIDI (tmp_argjhi)); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (2)), opval); + written |= (1 << 17); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } + { + DI opval = MULDI (ZEXTHIDI (tmp_argilo), ZEXTHIDI (tmp_argjlo)); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (3)), opval); + written |= (1 << 18); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +} +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* mmachs: mmachs$pack $FRinti,$FRintj,$ACC40Sk */ + +static SEM_PC +SEM_FN_NAME (frvbf,mmachs) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Sk))) { +if (ANDSI (FLD (f_ACC40Sk), SUBSI (2, 1))) { +frvbf_media_acc_not_aligned (current_cpu); +} else { +{ + HI tmp_argihi; + HI tmp_argilo; + HI tmp_argjhi; + HI tmp_argjlo; +{ + tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); + tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); +} +{ + DI tmp_tmp; + tmp_tmp = ADDDI (GET_H_ACC40S (FLD (f_ACC40Sk)), MULDI (EXTHIDI (tmp_argihi), EXTHIDI (tmp_argjhi))); +if (GTDI (tmp_tmp, MAKEDI (127, 0xffffffff))) { +{ + { + DI opval = MAKEDI (127, 0xffffffff); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval); + written |= (1 << 11); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { +if (LTDI (tmp_tmp, MAKEDI (0xffffff80, 0))) { +{ + { + DI opval = MAKEDI (0xffffff80, 0); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval); + written |= (1 << 11); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { + { + DI opval = tmp_tmp; + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval); + written |= (1 << 11); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +} +} +} +{ + DI tmp_tmp; + tmp_tmp = ADDDI (GET_H_ACC40S (((FLD (f_ACC40Sk)) + (1))), MULDI (EXTHIDI (tmp_argilo), EXTHIDI (tmp_argjlo))); +if (GTDI (tmp_tmp, MAKEDI (127, 0xffffffff))) { +{ + { + DI opval = MAKEDI (127, 0xffffffff); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval); + written |= (1 << 12); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 4); +} +} else { +if (LTDI (tmp_tmp, MAKEDI (0xffffff80, 0))) { +{ + { + DI opval = MAKEDI (0xffffff80, 0); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval); + written |= (1 << 12); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 4); +} +} else { + { + DI opval = tmp_tmp; + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval); + written |= (1 << 12); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +} +} +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* mmachu: mmachu$pack $FRinti,$FRintj,$ACC40Uk */ + +static SEM_PC +SEM_FN_NAME (frvbf,mmachu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Uk))) { +if (ANDSI (FLD (f_ACC40Uk), SUBSI (2, 1))) { +frvbf_media_acc_not_aligned (current_cpu); +} else { +{ + UHI tmp_argihi; + UHI tmp_argilo; + UHI tmp_argjhi; + UHI tmp_argjlo; +{ + tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); + tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); +} +{ + DI tmp_tmp; + tmp_tmp = ADDDI (GET_H_ACC40U (FLD (f_ACC40Uk)), MULDI (ZEXTHIDI (tmp_argihi), ZEXTHIDI (tmp_argjhi))); +if (GTDI (tmp_tmp, MAKEDI (255, 0xffffffff))) { +{ + { + UDI opval = MAKEDI (255, 0xffffffff); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40U_set, FLD (f_ACC40Uk), opval); + written |= (1 << 11); + TRACE_RESULT (current_cpu, abuf, "acc40U", 'D', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { +if (LTDI (tmp_tmp, MAKEDI (0, 0))) { +{ + { + UDI opval = MAKEDI (0, 0); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40U_set, FLD (f_ACC40Uk), opval); + written |= (1 << 11); + TRACE_RESULT (current_cpu, abuf, "acc40U", 'D', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { + { + UDI opval = tmp_tmp; + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40U_set, FLD (f_ACC40Uk), opval); + written |= (1 << 11); + TRACE_RESULT (current_cpu, abuf, "acc40U", 'D', opval); + } +} +} +} +{ + DI tmp_tmp; + tmp_tmp = ADDDI (GET_H_ACC40U (((FLD (f_ACC40Uk)) + (1))), MULDI (ZEXTHIDI (tmp_argilo), ZEXTHIDI (tmp_argjlo))); +if (GTDI (tmp_tmp, MAKEDI (255, 0xffffffff))) { +{ + { + UDI opval = MAKEDI (255, 0xffffffff); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40U_set, ((FLD (f_ACC40Uk)) + (1)), opval); + written |= (1 << 12); + TRACE_RESULT (current_cpu, abuf, "acc40U", 'D', opval); + } +frvbf_media_overflow (current_cpu, 4); +} +} else { +if (LTDI (tmp_tmp, MAKEDI (0, 0))) { +{ + { + UDI opval = MAKEDI (0, 0); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40U_set, ((FLD (f_ACC40Uk)) + (1)), opval); + written |= (1 << 12); + TRACE_RESULT (current_cpu, abuf, "acc40U", 'D', opval); + } +frvbf_media_overflow (current_cpu, 4); +} +} else { + { + UDI opval = tmp_tmp; + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40U_set, ((FLD (f_ACC40Uk)) + (1)), opval); + written |= (1 << 12); + TRACE_RESULT (current_cpu, abuf, "acc40U", 'D', opval); + } +} +} +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* mmrdhs: mmrdhs$pack $FRinti,$FRintj,$ACC40Sk */ + +static SEM_PC +SEM_FN_NAME (frvbf,mmrdhs) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Sk))) { +if (ANDSI (FLD (f_ACC40Sk), SUBSI (2, 1))) { +frvbf_media_acc_not_aligned (current_cpu); +} else { +{ + HI tmp_argihi; + HI tmp_argilo; + HI tmp_argjhi; + HI tmp_argjlo; +{ + tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); + tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); +} +{ + DI tmp_tmp; + tmp_tmp = SUBDI (GET_H_ACC40S (FLD (f_ACC40Sk)), MULDI (EXTHIDI (tmp_argihi), EXTHIDI (tmp_argjhi))); +if (GTDI (tmp_tmp, MAKEDI (127, 0xffffffff))) { +{ + { + DI opval = MAKEDI (127, 0xffffffff); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval); + written |= (1 << 11); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { +if (LTDI (tmp_tmp, MAKEDI (0xffffff80, 0))) { +{ + { + DI opval = MAKEDI (0xffffff80, 0); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval); + written |= (1 << 11); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { + { + DI opval = tmp_tmp; + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval); + written |= (1 << 11); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +} +} +} +{ + DI tmp_tmp; + tmp_tmp = SUBDI (GET_H_ACC40S (((FLD (f_ACC40Sk)) + (1))), MULDI (EXTHIDI (tmp_argilo), EXTHIDI (tmp_argjlo))); +if (GTDI (tmp_tmp, MAKEDI (127, 0xffffffff))) { +{ + { + DI opval = MAKEDI (127, 0xffffffff); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval); + written |= (1 << 12); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 4); +} +} else { +if (LTDI (tmp_tmp, MAKEDI (0xffffff80, 0))) { +{ + { + DI opval = MAKEDI (0xffffff80, 0); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval); + written |= (1 << 12); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 4); +} +} else { + { + DI opval = tmp_tmp; + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval); + written |= (1 << 12); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +} +} +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* mmrdhu: mmrdhu$pack $FRinti,$FRintj,$ACC40Uk */ + +static SEM_PC +SEM_FN_NAME (frvbf,mmrdhu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Uk))) { +if (ANDSI (FLD (f_ACC40Uk), SUBSI (2, 1))) { +frvbf_media_acc_not_aligned (current_cpu); +} else { +{ + UHI tmp_argihi; + UHI tmp_argilo; + UHI tmp_argjhi; + UHI tmp_argjlo; +{ + tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); + tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); +} +{ + DI tmp_tmp; + tmp_tmp = SUBDI (GET_H_ACC40U (FLD (f_ACC40Uk)), MULDI (ZEXTHIDI (tmp_argihi), ZEXTHIDI (tmp_argjhi))); +if (GTDI (tmp_tmp, MAKEDI (255, 0xffffffff))) { +{ + { + UDI opval = MAKEDI (255, 0xffffffff); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40U_set, FLD (f_ACC40Uk), opval); + written |= (1 << 11); + TRACE_RESULT (current_cpu, abuf, "acc40U", 'D', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { +if (LTDI (tmp_tmp, MAKEDI (0, 0))) { +{ + { + UDI opval = MAKEDI (0, 0); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40U_set, FLD (f_ACC40Uk), opval); + written |= (1 << 11); + TRACE_RESULT (current_cpu, abuf, "acc40U", 'D', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { + { + UDI opval = tmp_tmp; + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40U_set, FLD (f_ACC40Uk), opval); + written |= (1 << 11); + TRACE_RESULT (current_cpu, abuf, "acc40U", 'D', opval); + } +} +} +} +{ + DI tmp_tmp; + tmp_tmp = SUBDI (GET_H_ACC40U (((FLD (f_ACC40Uk)) + (1))), MULDI (ZEXTHIDI (tmp_argilo), ZEXTHIDI (tmp_argjlo))); +if (GTDI (tmp_tmp, MAKEDI (255, 0xffffffff))) { +{ + { + UDI opval = MAKEDI (255, 0xffffffff); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40U_set, ((FLD (f_ACC40Uk)) + (1)), opval); + written |= (1 << 12); + TRACE_RESULT (current_cpu, abuf, "acc40U", 'D', opval); + } +frvbf_media_overflow (current_cpu, 4); +} +} else { +if (LTDI (tmp_tmp, MAKEDI (0, 0))) { +{ + { + UDI opval = MAKEDI (0, 0); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40U_set, ((FLD (f_ACC40Uk)) + (1)), opval); + written |= (1 << 12); + TRACE_RESULT (current_cpu, abuf, "acc40U", 'D', opval); + } +frvbf_media_overflow (current_cpu, 4); +} +} else { + { + UDI opval = tmp_tmp; + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40U_set, ((FLD (f_ACC40Uk)) + (1)), opval); + written |= (1 << 12); + TRACE_RESULT (current_cpu, abuf, "acc40U", 'D', opval); + } +} +} +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cmmachs: cmmachs$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cmmachs) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Sk))) { +if (ANDSI (FLD (f_ACC40Sk), SUBSI (2, 1))) { +frvbf_media_acc_not_aligned (current_cpu); +} else { +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +{ + HI tmp_argihi; + HI tmp_argilo; + HI tmp_argjhi; + HI tmp_argjlo; +{ + tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); + tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); +} +{ + DI tmp_tmp; + tmp_tmp = ADDDI (GET_H_ACC40S (FLD (f_ACC40Sk)), MULDI (EXTHIDI (tmp_argihi), EXTHIDI (tmp_argjhi))); +if (GTDI (tmp_tmp, MAKEDI (127, 0xffffffff))) { +{ + { + DI opval = MAKEDI (127, 0xffffffff); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval); + written |= (1 << 13); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { +if (LTDI (tmp_tmp, MAKEDI (0xffffff80, 0))) { +{ + { + DI opval = MAKEDI (0xffffff80, 0); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval); + written |= (1 << 13); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { + { + DI opval = tmp_tmp; + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval); + written |= (1 << 13); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +} +} +} +{ + DI tmp_tmp; + tmp_tmp = ADDDI (GET_H_ACC40S (((FLD (f_ACC40Sk)) + (1))), MULDI (EXTHIDI (tmp_argilo), EXTHIDI (tmp_argjlo))); +if (GTDI (tmp_tmp, MAKEDI (127, 0xffffffff))) { +{ + { + DI opval = MAKEDI (127, 0xffffffff); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval); + written |= (1 << 14); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 4); +} +} else { +if (LTDI (tmp_tmp, MAKEDI (0xffffff80, 0))) { +{ + { + DI opval = MAKEDI (0xffffff80, 0); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval); + written |= (1 << 14); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 4); +} +} else { + { + DI opval = tmp_tmp; + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval); + written |= (1 << 14); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +} +} +} +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cmmachu: cmmachu$pack $FRinti,$FRintj,$ACC40Uk,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cmmachu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Uk))) { +if (ANDSI (FLD (f_ACC40Uk), SUBSI (2, 1))) { +frvbf_media_acc_not_aligned (current_cpu); +} else { +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +{ + UHI tmp_argihi; + UHI tmp_argilo; + UHI tmp_argjhi; + UHI tmp_argjlo; +{ + tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); + tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); +} +{ + DI tmp_tmp; + tmp_tmp = ADDDI (GET_H_ACC40U (FLD (f_ACC40Uk)), MULDI (ZEXTHIDI (tmp_argihi), ZEXTHIDI (tmp_argjhi))); +if (GTDI (tmp_tmp, MAKEDI (255, 0xffffffff))) { +{ + { + UDI opval = MAKEDI (255, 0xffffffff); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40U_set, FLD (f_ACC40Uk), opval); + written |= (1 << 13); + TRACE_RESULT (current_cpu, abuf, "acc40U", 'D', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { +if (LTDI (tmp_tmp, MAKEDI (0, 0))) { +{ + { + UDI opval = MAKEDI (0, 0); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40U_set, FLD (f_ACC40Uk), opval); + written |= (1 << 13); + TRACE_RESULT (current_cpu, abuf, "acc40U", 'D', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { + { + UDI opval = tmp_tmp; + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40U_set, FLD (f_ACC40Uk), opval); + written |= (1 << 13); + TRACE_RESULT (current_cpu, abuf, "acc40U", 'D', opval); + } +} +} +} +{ + DI tmp_tmp; + tmp_tmp = ADDDI (GET_H_ACC40U (((FLD (f_ACC40Uk)) + (1))), MULDI (ZEXTHIDI (tmp_argilo), ZEXTHIDI (tmp_argjlo))); +if (GTDI (tmp_tmp, MAKEDI (255, 0xffffffff))) { +{ + { + UDI opval = MAKEDI (255, 0xffffffff); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40U_set, ((FLD (f_ACC40Uk)) + (1)), opval); + written |= (1 << 14); + TRACE_RESULT (current_cpu, abuf, "acc40U", 'D', opval); + } +frvbf_media_overflow (current_cpu, 4); +} +} else { +if (LTDI (tmp_tmp, MAKEDI (0, 0))) { +{ + { + UDI opval = MAKEDI (0, 0); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40U_set, ((FLD (f_ACC40Uk)) + (1)), opval); + written |= (1 << 14); + TRACE_RESULT (current_cpu, abuf, "acc40U", 'D', opval); + } +frvbf_media_overflow (current_cpu, 4); +} +} else { + { + UDI opval = tmp_tmp; + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40U_set, ((FLD (f_ACC40Uk)) + (1)), opval); + written |= (1 << 14); + TRACE_RESULT (current_cpu, abuf, "acc40U", 'D', opval); + } +} +} +} +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* mqmachs: mqmachs$pack $FRintieven,$FRintjeven,$ACC40Sk */ + +static SEM_PC +SEM_FN_NAME (frvbf,mqmachs) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Sk))) { +if (ANDSI (FLD (f_ACC40Sk), SUBSI (4, 1))) { +frvbf_media_acc_not_aligned (current_cpu); +} else { +if (ORIF (ANDSI (FLD (f_FRi), SUBSI (2, 1)), ANDSI (FLD (f_FRj), SUBSI (2, 1)))) { +frvbf_media_register_not_aligned (current_cpu); +} else { +{ + HI tmp_argihi; + HI tmp_argilo; + HI tmp_argjhi; + HI tmp_argjlo; +{ + tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); + tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); +} +{ + DI tmp_tmp; + tmp_tmp = ADDDI (GET_H_ACC40S (FLD (f_ACC40Sk)), MULDI (EXTHIDI (tmp_argihi), EXTHIDI (tmp_argjhi))); +if (GTDI (tmp_tmp, MAKEDI (127, 0xffffffff))) { +{ + { + DI opval = MAKEDI (127, 0xffffffff); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval); + written |= (1 << 17); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { +if (LTDI (tmp_tmp, MAKEDI (0xffffff80, 0))) { +{ + { + DI opval = MAKEDI (0xffffff80, 0); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval); + written |= (1 << 17); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { + { + DI opval = tmp_tmp; + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval); + written |= (1 << 17); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +} +} +} +{ + DI tmp_tmp; + tmp_tmp = ADDDI (GET_H_ACC40S (((FLD (f_ACC40Sk)) + (1))), MULDI (EXTHIDI (tmp_argilo), EXTHIDI (tmp_argjlo))); +if (GTDI (tmp_tmp, MAKEDI (127, 0xffffffff))) { +{ + { + DI opval = MAKEDI (127, 0xffffffff); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval); + written |= (1 << 18); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 4); +} +} else { +if (LTDI (tmp_tmp, MAKEDI (0xffffff80, 0))) { +{ + { + DI opval = MAKEDI (0xffffff80, 0); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval); + written |= (1 << 18); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 4); +} +} else { + { + DI opval = tmp_tmp; + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval); + written |= (1 << 18); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +} +} +} +{ + tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); + tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); +} +{ + DI tmp_tmp; + tmp_tmp = ADDDI (GET_H_ACC40S (((FLD (f_ACC40Sk)) + (2))), MULDI (EXTHIDI (tmp_argihi), EXTHIDI (tmp_argjhi))); +if (GTDI (tmp_tmp, MAKEDI (127, 0xffffffff))) { +{ + { + DI opval = MAKEDI (127, 0xffffffff); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (2)), opval); + written |= (1 << 19); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 2); +} +} else { +if (LTDI (tmp_tmp, MAKEDI (0xffffff80, 0))) { +{ + { + DI opval = MAKEDI (0xffffff80, 0); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (2)), opval); + written |= (1 << 19); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 2); +} +} else { + { + DI opval = tmp_tmp; + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (2)), opval); + written |= (1 << 19); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +} +} +} +{ + DI tmp_tmp; + tmp_tmp = ADDDI (GET_H_ACC40S (((FLD (f_ACC40Sk)) + (3))), MULDI (EXTHIDI (tmp_argilo), EXTHIDI (tmp_argjlo))); +if (GTDI (tmp_tmp, MAKEDI (127, 0xffffffff))) { +{ + { + DI opval = MAKEDI (127, 0xffffffff); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (3)), opval); + written |= (1 << 20); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 1); +} +} else { +if (LTDI (tmp_tmp, MAKEDI (0xffffff80, 0))) { +{ + { + DI opval = MAKEDI (0xffffff80, 0); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (3)), opval); + written |= (1 << 20); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 1); +} +} else { + { + DI opval = tmp_tmp; + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (3)), opval); + written |= (1 << 20); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +} +} +} +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* mqmachu: mqmachu$pack $FRintieven,$FRintjeven,$ACC40Uk */ + +static SEM_PC +SEM_FN_NAME (frvbf,mqmachu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Uk))) { +if (ANDSI (FLD (f_ACC40Uk), SUBSI (4, 1))) { +frvbf_media_acc_not_aligned (current_cpu); +} else { +if (ORIF (ANDSI (FLD (f_FRi), SUBSI (2, 1)), ANDSI (FLD (f_FRj), SUBSI (2, 1)))) { +frvbf_media_register_not_aligned (current_cpu); +} else { +{ + UHI tmp_argihi; + UHI tmp_argilo; + UHI tmp_argjhi; + UHI tmp_argjlo; +{ + tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); + tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); +} +{ + DI tmp_tmp; + tmp_tmp = ADDDI (GET_H_ACC40U (FLD (f_ACC40Uk)), MULDI (ZEXTHIDI (tmp_argihi), ZEXTHIDI (tmp_argjhi))); +if (GTDI (tmp_tmp, MAKEDI (255, 0xffffffff))) { +{ + { + UDI opval = MAKEDI (255, 0xffffffff); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40U_set, FLD (f_ACC40Uk), opval); + written |= (1 << 17); + TRACE_RESULT (current_cpu, abuf, "acc40U", 'D', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { +if (LTDI (tmp_tmp, MAKEDI (0, 0))) { +{ + { + UDI opval = MAKEDI (0, 0); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40U_set, FLD (f_ACC40Uk), opval); + written |= (1 << 17); + TRACE_RESULT (current_cpu, abuf, "acc40U", 'D', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { + { + UDI opval = tmp_tmp; + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40U_set, FLD (f_ACC40Uk), opval); + written |= (1 << 17); + TRACE_RESULT (current_cpu, abuf, "acc40U", 'D', opval); + } +} +} +} +{ + DI tmp_tmp; + tmp_tmp = ADDDI (GET_H_ACC40U (((FLD (f_ACC40Uk)) + (1))), MULDI (ZEXTHIDI (tmp_argilo), ZEXTHIDI (tmp_argjlo))); +if (GTDI (tmp_tmp, MAKEDI (255, 0xffffffff))) { +{ + { + UDI opval = MAKEDI (255, 0xffffffff); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40U_set, ((FLD (f_ACC40Uk)) + (1)), opval); + written |= (1 << 18); + TRACE_RESULT (current_cpu, abuf, "acc40U", 'D', opval); + } +frvbf_media_overflow (current_cpu, 4); +} +} else { +if (LTDI (tmp_tmp, MAKEDI (0, 0))) { +{ + { + UDI opval = MAKEDI (0, 0); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40U_set, ((FLD (f_ACC40Uk)) + (1)), opval); + written |= (1 << 18); + TRACE_RESULT (current_cpu, abuf, "acc40U", 'D', opval); + } +frvbf_media_overflow (current_cpu, 4); +} +} else { + { + UDI opval = tmp_tmp; + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40U_set, ((FLD (f_ACC40Uk)) + (1)), opval); + written |= (1 << 18); + TRACE_RESULT (current_cpu, abuf, "acc40U", 'D', opval); + } +} +} +} +{ + tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); + tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); +} +{ + DI tmp_tmp; + tmp_tmp = ADDDI (GET_H_ACC40U (((FLD (f_ACC40Uk)) + (2))), MULDI (ZEXTHIDI (tmp_argihi), ZEXTHIDI (tmp_argjhi))); +if (GTDI (tmp_tmp, MAKEDI (255, 0xffffffff))) { +{ + { + UDI opval = MAKEDI (255, 0xffffffff); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40U_set, ((FLD (f_ACC40Uk)) + (2)), opval); + written |= (1 << 19); + TRACE_RESULT (current_cpu, abuf, "acc40U", 'D', opval); + } +frvbf_media_overflow (current_cpu, 2); +} +} else { +if (LTDI (tmp_tmp, MAKEDI (0, 0))) { +{ + { + UDI opval = MAKEDI (0, 0); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40U_set, ((FLD (f_ACC40Uk)) + (2)), opval); + written |= (1 << 19); + TRACE_RESULT (current_cpu, abuf, "acc40U", 'D', opval); + } +frvbf_media_overflow (current_cpu, 2); +} +} else { + { + UDI opval = tmp_tmp; + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40U_set, ((FLD (f_ACC40Uk)) + (2)), opval); + written |= (1 << 19); + TRACE_RESULT (current_cpu, abuf, "acc40U", 'D', opval); + } +} +} +} +{ + DI tmp_tmp; + tmp_tmp = ADDDI (GET_H_ACC40U (((FLD (f_ACC40Uk)) + (3))), MULDI (ZEXTHIDI (tmp_argilo), ZEXTHIDI (tmp_argjlo))); +if (GTDI (tmp_tmp, MAKEDI (255, 0xffffffff))) { +{ + { + UDI opval = MAKEDI (255, 0xffffffff); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40U_set, ((FLD (f_ACC40Uk)) + (3)), opval); + written |= (1 << 20); + TRACE_RESULT (current_cpu, abuf, "acc40U", 'D', opval); + } +frvbf_media_overflow (current_cpu, 1); +} +} else { +if (LTDI (tmp_tmp, MAKEDI (0, 0))) { +{ + { + UDI opval = MAKEDI (0, 0); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40U_set, ((FLD (f_ACC40Uk)) + (3)), opval); + written |= (1 << 20); + TRACE_RESULT (current_cpu, abuf, "acc40U", 'D', opval); + } +frvbf_media_overflow (current_cpu, 1); +} +} else { + { + UDI opval = tmp_tmp; + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40U_set, ((FLD (f_ACC40Uk)) + (3)), opval); + written |= (1 << 20); + TRACE_RESULT (current_cpu, abuf, "acc40U", 'D', opval); + } +} +} +} +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cmqmachs: cmqmachs$pack $FRintieven,$FRintjeven,$ACC40Sk,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cmqmachs) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Sk))) { +if (ANDSI (FLD (f_ACC40Sk), SUBSI (4, 1))) { +frvbf_media_acc_not_aligned (current_cpu); +} else { +if (ORIF (ANDSI (FLD (f_FRi), SUBSI (2, 1)), ANDSI (FLD (f_FRj), SUBSI (2, 1)))) { +frvbf_media_register_not_aligned (current_cpu); +} else { +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +{ + HI tmp_argihi; + HI tmp_argilo; + HI tmp_argjhi; + HI tmp_argjlo; +{ + tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); + tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); +} +{ + DI tmp_tmp; + tmp_tmp = ADDDI (GET_H_ACC40S (FLD (f_ACC40Sk)), MULDI (EXTHIDI (tmp_argihi), EXTHIDI (tmp_argjhi))); +if (GTDI (tmp_tmp, MAKEDI (127, 0xffffffff))) { +{ + { + DI opval = MAKEDI (127, 0xffffffff); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval); + written |= (1 << 19); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { +if (LTDI (tmp_tmp, MAKEDI (0xffffff80, 0))) { +{ + { + DI opval = MAKEDI (0xffffff80, 0); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval); + written |= (1 << 19); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { + { + DI opval = tmp_tmp; + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval); + written |= (1 << 19); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +} +} +} +{ + DI tmp_tmp; + tmp_tmp = ADDDI (GET_H_ACC40S (((FLD (f_ACC40Sk)) + (1))), MULDI (EXTHIDI (tmp_argilo), EXTHIDI (tmp_argjlo))); +if (GTDI (tmp_tmp, MAKEDI (127, 0xffffffff))) { +{ + { + DI opval = MAKEDI (127, 0xffffffff); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval); + written |= (1 << 20); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 4); +} +} else { +if (LTDI (tmp_tmp, MAKEDI (0xffffff80, 0))) { +{ + { + DI opval = MAKEDI (0xffffff80, 0); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval); + written |= (1 << 20); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 4); +} +} else { + { + DI opval = tmp_tmp; + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval); + written |= (1 << 20); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +} +} +} +{ + tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); + tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); +} +{ + DI tmp_tmp; + tmp_tmp = ADDDI (GET_H_ACC40S (((FLD (f_ACC40Sk)) + (2))), MULDI (EXTHIDI (tmp_argihi), EXTHIDI (tmp_argjhi))); +if (GTDI (tmp_tmp, MAKEDI (127, 0xffffffff))) { +{ + { + DI opval = MAKEDI (127, 0xffffffff); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (2)), opval); + written |= (1 << 21); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 2); +} +} else { +if (LTDI (tmp_tmp, MAKEDI (0xffffff80, 0))) { +{ + { + DI opval = MAKEDI (0xffffff80, 0); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (2)), opval); + written |= (1 << 21); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 2); +} +} else { + { + DI opval = tmp_tmp; + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (2)), opval); + written |= (1 << 21); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +} +} +} +{ + DI tmp_tmp; + tmp_tmp = ADDDI (GET_H_ACC40S (((FLD (f_ACC40Sk)) + (3))), MULDI (EXTHIDI (tmp_argilo), EXTHIDI (tmp_argjlo))); +if (GTDI (tmp_tmp, MAKEDI (127, 0xffffffff))) { +{ + { + DI opval = MAKEDI (127, 0xffffffff); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (3)), opval); + written |= (1 << 22); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 1); +} +} else { +if (LTDI (tmp_tmp, MAKEDI (0xffffff80, 0))) { +{ + { + DI opval = MAKEDI (0xffffff80, 0); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (3)), opval); + written |= (1 << 22); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 1); +} +} else { + { + DI opval = tmp_tmp; + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (3)), opval); + written |= (1 << 22); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +} +} +} +} +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cmqmachu: cmqmachu$pack $FRintieven,$FRintjeven,$ACC40Uk,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cmqmachu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachu.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Uk))) { +if (ANDSI (FLD (f_ACC40Uk), SUBSI (4, 1))) { +frvbf_media_acc_not_aligned (current_cpu); +} else { +if (ORIF (ANDSI (FLD (f_FRi), SUBSI (2, 1)), ANDSI (FLD (f_FRj), SUBSI (2, 1)))) { +frvbf_media_register_not_aligned (current_cpu); +} else { +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +{ + UHI tmp_argihi; + UHI tmp_argilo; + UHI tmp_argjhi; + UHI tmp_argjlo; +{ + tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); + tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); +} +{ + DI tmp_tmp; + tmp_tmp = ADDDI (GET_H_ACC40U (FLD (f_ACC40Uk)), MULDI (ZEXTHIDI (tmp_argihi), ZEXTHIDI (tmp_argjhi))); +if (GTDI (tmp_tmp, MAKEDI (255, 0xffffffff))) { +{ + { + UDI opval = MAKEDI (255, 0xffffffff); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40U_set, FLD (f_ACC40Uk), opval); + written |= (1 << 19); + TRACE_RESULT (current_cpu, abuf, "acc40U", 'D', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { +if (LTDI (tmp_tmp, MAKEDI (0, 0))) { +{ + { + UDI opval = MAKEDI (0, 0); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40U_set, FLD (f_ACC40Uk), opval); + written |= (1 << 19); + TRACE_RESULT (current_cpu, abuf, "acc40U", 'D', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { + { + UDI opval = tmp_tmp; + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40U_set, FLD (f_ACC40Uk), opval); + written |= (1 << 19); + TRACE_RESULT (current_cpu, abuf, "acc40U", 'D', opval); + } +} +} +} +{ + DI tmp_tmp; + tmp_tmp = ADDDI (GET_H_ACC40U (((FLD (f_ACC40Uk)) + (1))), MULDI (ZEXTHIDI (tmp_argilo), ZEXTHIDI (tmp_argjlo))); +if (GTDI (tmp_tmp, MAKEDI (255, 0xffffffff))) { +{ + { + UDI opval = MAKEDI (255, 0xffffffff); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40U_set, ((FLD (f_ACC40Uk)) + (1)), opval); + written |= (1 << 20); + TRACE_RESULT (current_cpu, abuf, "acc40U", 'D', opval); + } +frvbf_media_overflow (current_cpu, 4); +} +} else { +if (LTDI (tmp_tmp, MAKEDI (0, 0))) { +{ + { + UDI opval = MAKEDI (0, 0); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40U_set, ((FLD (f_ACC40Uk)) + (1)), opval); + written |= (1 << 20); + TRACE_RESULT (current_cpu, abuf, "acc40U", 'D', opval); + } +frvbf_media_overflow (current_cpu, 4); +} +} else { + { + UDI opval = tmp_tmp; + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40U_set, ((FLD (f_ACC40Uk)) + (1)), opval); + written |= (1 << 20); + TRACE_RESULT (current_cpu, abuf, "acc40U", 'D', opval); + } +} +} +} +{ + tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); + tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); +} +{ + DI tmp_tmp; + tmp_tmp = ADDDI (GET_H_ACC40U (((FLD (f_ACC40Uk)) + (2))), MULDI (ZEXTHIDI (tmp_argihi), ZEXTHIDI (tmp_argjhi))); +if (GTDI (tmp_tmp, MAKEDI (255, 0xffffffff))) { +{ + { + UDI opval = MAKEDI (255, 0xffffffff); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40U_set, ((FLD (f_ACC40Uk)) + (2)), opval); + written |= (1 << 21); + TRACE_RESULT (current_cpu, abuf, "acc40U", 'D', opval); + } +frvbf_media_overflow (current_cpu, 2); +} +} else { +if (LTDI (tmp_tmp, MAKEDI (0, 0))) { +{ + { + UDI opval = MAKEDI (0, 0); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40U_set, ((FLD (f_ACC40Uk)) + (2)), opval); + written |= (1 << 21); + TRACE_RESULT (current_cpu, abuf, "acc40U", 'D', opval); + } +frvbf_media_overflow (current_cpu, 2); +} +} else { + { + UDI opval = tmp_tmp; + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40U_set, ((FLD (f_ACC40Uk)) + (2)), opval); + written |= (1 << 21); + TRACE_RESULT (current_cpu, abuf, "acc40U", 'D', opval); + } +} +} +} +{ + DI tmp_tmp; + tmp_tmp = ADDDI (GET_H_ACC40U (((FLD (f_ACC40Uk)) + (3))), MULDI (ZEXTHIDI (tmp_argilo), ZEXTHIDI (tmp_argjlo))); +if (GTDI (tmp_tmp, MAKEDI (255, 0xffffffff))) { +{ + { + UDI opval = MAKEDI (255, 0xffffffff); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40U_set, ((FLD (f_ACC40Uk)) + (3)), opval); + written |= (1 << 22); + TRACE_RESULT (current_cpu, abuf, "acc40U", 'D', opval); + } +frvbf_media_overflow (current_cpu, 1); +} +} else { +if (LTDI (tmp_tmp, MAKEDI (0, 0))) { +{ + { + UDI opval = MAKEDI (0, 0); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40U_set, ((FLD (f_ACC40Uk)) + (3)), opval); + written |= (1 << 22); + TRACE_RESULT (current_cpu, abuf, "acc40U", 'D', opval); + } +frvbf_media_overflow (current_cpu, 1); +} +} else { + { + UDI opval = tmp_tmp; + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40U_set, ((FLD (f_ACC40Uk)) + (3)), opval); + written |= (1 << 22); + TRACE_RESULT (current_cpu, abuf, "acc40U", 'D', opval); + } +} +} +} +} +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* mqxmachs: mqxmachs$pack $FRintieven,$FRintjeven,$ACC40Sk */ + +static SEM_PC +SEM_FN_NAME (frvbf,mqxmachs) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Sk))) { +if (ANDSI (FLD (f_ACC40Sk), SUBSI (4, 1))) { +frvbf_media_acc_not_aligned (current_cpu); +} else { +if (ORIF (ANDSI (FLD (f_FRi), SUBSI (2, 1)), ANDSI (FLD (f_FRj), SUBSI (2, 1)))) { +frvbf_media_register_not_aligned (current_cpu); +} else { +{ + HI tmp_argihi; + HI tmp_argilo; + HI tmp_argjhi; + HI tmp_argjlo; +{ + tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); + tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); +} +{ + DI tmp_tmp; + tmp_tmp = ADDDI (GET_H_ACC40S (((FLD (f_ACC40Sk)) + (2))), MULDI (EXTHIDI (tmp_argihi), EXTHIDI (tmp_argjhi))); +if (GTDI (tmp_tmp, MAKEDI (127, 0xffffffff))) { +{ + { + DI opval = MAKEDI (127, 0xffffffff); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (2)), opval); + written |= (1 << 19); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 2); +} +} else { +if (LTDI (tmp_tmp, MAKEDI (0xffffff80, 0))) { +{ + { + DI opval = MAKEDI (0xffffff80, 0); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (2)), opval); + written |= (1 << 19); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 2); +} +} else { + { + DI opval = tmp_tmp; + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (2)), opval); + written |= (1 << 19); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +} +} +} +{ + DI tmp_tmp; + tmp_tmp = ADDDI (GET_H_ACC40S (((FLD (f_ACC40Sk)) + (3))), MULDI (EXTHIDI (tmp_argilo), EXTHIDI (tmp_argjlo))); +if (GTDI (tmp_tmp, MAKEDI (127, 0xffffffff))) { +{ + { + DI opval = MAKEDI (127, 0xffffffff); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (3)), opval); + written |= (1 << 20); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 1); +} +} else { +if (LTDI (tmp_tmp, MAKEDI (0xffffff80, 0))) { +{ + { + DI opval = MAKEDI (0xffffff80, 0); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (3)), opval); + written |= (1 << 20); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 1); +} +} else { + { + DI opval = tmp_tmp; + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (3)), opval); + written |= (1 << 20); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +} +} +} +{ + tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); + tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); +} +{ + DI tmp_tmp; + tmp_tmp = ADDDI (GET_H_ACC40S (FLD (f_ACC40Sk)), MULDI (EXTHIDI (tmp_argihi), EXTHIDI (tmp_argjhi))); +if (GTDI (tmp_tmp, MAKEDI (127, 0xffffffff))) { +{ + { + DI opval = MAKEDI (127, 0xffffffff); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval); + written |= (1 << 17); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { +if (LTDI (tmp_tmp, MAKEDI (0xffffff80, 0))) { +{ + { + DI opval = MAKEDI (0xffffff80, 0); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval); + written |= (1 << 17); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { + { + DI opval = tmp_tmp; + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval); + written |= (1 << 17); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +} +} +} +{ + DI tmp_tmp; + tmp_tmp = ADDDI (GET_H_ACC40S (((FLD (f_ACC40Sk)) + (1))), MULDI (EXTHIDI (tmp_argilo), EXTHIDI (tmp_argjlo))); +if (GTDI (tmp_tmp, MAKEDI (127, 0xffffffff))) { +{ + { + DI opval = MAKEDI (127, 0xffffffff); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval); + written |= (1 << 18); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 4); +} +} else { +if (LTDI (tmp_tmp, MAKEDI (0xffffff80, 0))) { +{ + { + DI opval = MAKEDI (0xffffff80, 0); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval); + written |= (1 << 18); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 4); +} +} else { + { + DI opval = tmp_tmp; + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval); + written |= (1 << 18); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +} +} +} +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* mqxmacxhs: mqxmacxhs$pack $FRintieven,$FRintjeven,$ACC40Sk */ + +static SEM_PC +SEM_FN_NAME (frvbf,mqxmacxhs) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Sk))) { +if (ANDSI (FLD (f_ACC40Sk), SUBSI (4, 1))) { +frvbf_media_acc_not_aligned (current_cpu); +} else { +if (ORIF (ANDSI (FLD (f_FRi), SUBSI (2, 1)), ANDSI (FLD (f_FRj), SUBSI (2, 1)))) { +frvbf_media_register_not_aligned (current_cpu); +} else { +{ + HI tmp_argihi; + HI tmp_argilo; + HI tmp_argjhi; + HI tmp_argjlo; +{ + tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); + tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); +} +{ + DI tmp_tmp; + tmp_tmp = ADDDI (GET_H_ACC40S (((FLD (f_ACC40Sk)) + (2))), MULDI (EXTHIDI (tmp_argihi), EXTHIDI (tmp_argjlo))); +if (GTDI (tmp_tmp, MAKEDI (127, 0xffffffff))) { +{ + { + DI opval = MAKEDI (127, 0xffffffff); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (2)), opval); + written |= (1 << 19); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 2); +} +} else { +if (LTDI (tmp_tmp, MAKEDI (0xffffff80, 0))) { +{ + { + DI opval = MAKEDI (0xffffff80, 0); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (2)), opval); + written |= (1 << 19); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 2); +} +} else { + { + DI opval = tmp_tmp; + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (2)), opval); + written |= (1 << 19); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +} +} +} +{ + DI tmp_tmp; + tmp_tmp = ADDDI (GET_H_ACC40S (((FLD (f_ACC40Sk)) + (3))), MULDI (EXTHIDI (tmp_argilo), EXTHIDI (tmp_argjhi))); +if (GTDI (tmp_tmp, MAKEDI (127, 0xffffffff))) { +{ + { + DI opval = MAKEDI (127, 0xffffffff); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (3)), opval); + written |= (1 << 20); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 1); +} +} else { +if (LTDI (tmp_tmp, MAKEDI (0xffffff80, 0))) { +{ + { + DI opval = MAKEDI (0xffffff80, 0); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (3)), opval); + written |= (1 << 20); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 1); +} +} else { + { + DI opval = tmp_tmp; + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (3)), opval); + written |= (1 << 20); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +} +} +} +{ + tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); + tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); +} +{ + DI tmp_tmp; + tmp_tmp = ADDDI (GET_H_ACC40S (FLD (f_ACC40Sk)), MULDI (EXTHIDI (tmp_argihi), EXTHIDI (tmp_argjlo))); +if (GTDI (tmp_tmp, MAKEDI (127, 0xffffffff))) { +{ + { + DI opval = MAKEDI (127, 0xffffffff); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval); + written |= (1 << 17); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { +if (LTDI (tmp_tmp, MAKEDI (0xffffff80, 0))) { +{ + { + DI opval = MAKEDI (0xffffff80, 0); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval); + written |= (1 << 17); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { + { + DI opval = tmp_tmp; + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval); + written |= (1 << 17); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +} +} +} +{ + DI tmp_tmp; + tmp_tmp = ADDDI (GET_H_ACC40S (((FLD (f_ACC40Sk)) + (1))), MULDI (EXTHIDI (tmp_argilo), EXTHIDI (tmp_argjhi))); +if (GTDI (tmp_tmp, MAKEDI (127, 0xffffffff))) { +{ + { + DI opval = MAKEDI (127, 0xffffffff); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval); + written |= (1 << 18); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 4); +} +} else { +if (LTDI (tmp_tmp, MAKEDI (0xffffff80, 0))) { +{ + { + DI opval = MAKEDI (0xffffff80, 0); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval); + written |= (1 << 18); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 4); +} +} else { + { + DI opval = tmp_tmp; + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval); + written |= (1 << 18); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +} +} +} +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* mqmacxhs: mqmacxhs$pack $FRintieven,$FRintjeven,$ACC40Sk */ + +static SEM_PC +SEM_FN_NAME (frvbf,mqmacxhs) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Sk))) { +if (ANDSI (FLD (f_ACC40Sk), SUBSI (4, 1))) { +frvbf_media_acc_not_aligned (current_cpu); +} else { +if (ORIF (ANDSI (FLD (f_FRi), SUBSI (2, 1)), ANDSI (FLD (f_FRj), SUBSI (2, 1)))) { +frvbf_media_register_not_aligned (current_cpu); +} else { +{ + HI tmp_argihi; + HI tmp_argilo; + HI tmp_argjhi; + HI tmp_argjlo; +{ + tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); + tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); +} +{ + DI tmp_tmp; + tmp_tmp = ADDDI (GET_H_ACC40S (FLD (f_ACC40Sk)), MULDI (EXTHIDI (tmp_argihi), EXTHIDI (tmp_argjlo))); +if (GTDI (tmp_tmp, MAKEDI (127, 0xffffffff))) { +{ + { + DI opval = MAKEDI (127, 0xffffffff); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval); + written |= (1 << 17); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { +if (LTDI (tmp_tmp, MAKEDI (0xffffff80, 0))) { +{ + { + DI opval = MAKEDI (0xffffff80, 0); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval); + written |= (1 << 17); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { + { + DI opval = tmp_tmp; + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval); + written |= (1 << 17); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +} +} +} +{ + DI tmp_tmp; + tmp_tmp = ADDDI (GET_H_ACC40S (((FLD (f_ACC40Sk)) + (1))), MULDI (EXTHIDI (tmp_argilo), EXTHIDI (tmp_argjhi))); +if (GTDI (tmp_tmp, MAKEDI (127, 0xffffffff))) { +{ + { + DI opval = MAKEDI (127, 0xffffffff); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval); + written |= (1 << 18); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 4); +} +} else { +if (LTDI (tmp_tmp, MAKEDI (0xffffff80, 0))) { +{ + { + DI opval = MAKEDI (0xffffff80, 0); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval); + written |= (1 << 18); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 4); +} +} else { + { + DI opval = tmp_tmp; + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval); + written |= (1 << 18); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +} +} +} +{ + tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); + tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); +} +{ + DI tmp_tmp; + tmp_tmp = ADDDI (GET_H_ACC40S (((FLD (f_ACC40Sk)) + (2))), MULDI (EXTHIDI (tmp_argihi), EXTHIDI (tmp_argjlo))); +if (GTDI (tmp_tmp, MAKEDI (127, 0xffffffff))) { +{ + { + DI opval = MAKEDI (127, 0xffffffff); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (2)), opval); + written |= (1 << 19); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 2); +} +} else { +if (LTDI (tmp_tmp, MAKEDI (0xffffff80, 0))) { +{ + { + DI opval = MAKEDI (0xffffff80, 0); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (2)), opval); + written |= (1 << 19); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 2); +} +} else { + { + DI opval = tmp_tmp; + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (2)), opval); + written |= (1 << 19); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +} +} +} +{ + DI tmp_tmp; + tmp_tmp = ADDDI (GET_H_ACC40S (((FLD (f_ACC40Sk)) + (3))), MULDI (EXTHIDI (tmp_argilo), EXTHIDI (tmp_argjhi))); +if (GTDI (tmp_tmp, MAKEDI (127, 0xffffffff))) { +{ + { + DI opval = MAKEDI (127, 0xffffffff); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (3)), opval); + written |= (1 << 20); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 1); +} +} else { +if (LTDI (tmp_tmp, MAKEDI (0xffffff80, 0))) { +{ + { + DI opval = MAKEDI (0xffffff80, 0); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (3)), opval); + written |= (1 << 20); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 1); +} +} else { + { + DI opval = tmp_tmp; + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (3)), opval); + written |= (1 << 20); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +} +} +} +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* mcpxrs: mcpxrs$pack $FRinti,$FRintj,$ACC40Sk */ + +static SEM_PC +SEM_FN_NAME (frvbf,mcpxrs) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Sk))) { +{ + HI tmp_argihi; + HI tmp_argilo; + HI tmp_argjhi; + HI tmp_argjlo; +{ + tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); + tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); +} +{ + DI tmp_tmp1; + DI tmp_tmp2; + tmp_tmp1 = MULDI (EXTHIDI (tmp_argihi), EXTHIDI (tmp_argjhi)); + tmp_tmp2 = MULDI (EXTHIDI (tmp_argilo), EXTHIDI (tmp_argjlo)); + tmp_tmp1 = SUBDI (tmp_tmp1, tmp_tmp2); +if (GTDI (tmp_tmp1, MAKEDI (127, 0xffffffff))) { +{ + { + DI opval = MAKEDI (127, 0xffffffff); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval); + written |= (1 << 9); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { +if (LTDI (tmp_tmp1, MAKEDI (0xffffff80, 0))) { +{ + { + DI opval = MAKEDI (0xffffff80, 0); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval); + written |= (1 << 9); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { + { + DI opval = tmp_tmp1; + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval); + written |= (1 << 9); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +} +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* mcpxru: mcpxru$pack $FRinti,$FRintj,$ACC40Sk */ + +static SEM_PC +SEM_FN_NAME (frvbf,mcpxru) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Sk))) { +{ + UHI tmp_argihi; + UHI tmp_argilo; + UHI tmp_argjhi; + UHI tmp_argjlo; +{ + tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); + tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); +} +{ + DI tmp_tmp1; + DI tmp_tmp2; + tmp_tmp1 = MULDI (ZEXTHIDI (tmp_argihi), ZEXTHIDI (tmp_argjhi)); + tmp_tmp2 = MULDI (ZEXTHIDI (tmp_argilo), ZEXTHIDI (tmp_argjlo)); + tmp_tmp1 = SUBDI (tmp_tmp1, tmp_tmp2); +if (GTDI (tmp_tmp1, MAKEDI (255, 0xffffffff))) { +{ + { + DI opval = MAKEDI (255, 0xffffffff); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval); + written |= (1 << 9); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { +if (LTDI (tmp_tmp1, MAKEDI (0, 0))) { +{ + { + DI opval = MAKEDI (0, 0); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval); + written |= (1 << 9); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { + { + DI opval = tmp_tmp1; + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval); + written |= (1 << 9); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +} +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* mcpxis: mcpxis$pack $FRinti,$FRintj,$ACC40Sk */ + +static SEM_PC +SEM_FN_NAME (frvbf,mcpxis) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Sk))) { +{ + HI tmp_argihi; + HI tmp_argilo; + HI tmp_argjhi; + HI tmp_argjlo; +{ + tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); + tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); +} +{ + DI tmp_tmp1; + DI tmp_tmp2; + tmp_tmp1 = MULDI (EXTHIDI (tmp_argihi), EXTHIDI (tmp_argjlo)); + tmp_tmp2 = MULDI (EXTHIDI (tmp_argilo), EXTHIDI (tmp_argjhi)); + tmp_tmp1 = ADDDI (tmp_tmp1, tmp_tmp2); +if (GTDI (tmp_tmp1, MAKEDI (127, 0xffffffff))) { +{ + { + DI opval = MAKEDI (127, 0xffffffff); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval); + written |= (1 << 9); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { +if (LTDI (tmp_tmp1, MAKEDI (0xffffff80, 0))) { +{ + { + DI opval = MAKEDI (0xffffff80, 0); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval); + written |= (1 << 9); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { + { + DI opval = tmp_tmp1; + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval); + written |= (1 << 9); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +} +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* mcpxiu: mcpxiu$pack $FRinti,$FRintj,$ACC40Sk */ + +static SEM_PC +SEM_FN_NAME (frvbf,mcpxiu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Sk))) { +{ + UHI tmp_argihi; + UHI tmp_argilo; + UHI tmp_argjhi; + UHI tmp_argjlo; +{ + tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); + tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); +} +{ + DI tmp_tmp1; + DI tmp_tmp2; + tmp_tmp1 = MULDI (ZEXTHIDI (tmp_argihi), ZEXTHIDI (tmp_argjlo)); + tmp_tmp2 = MULDI (ZEXTHIDI (tmp_argilo), ZEXTHIDI (tmp_argjhi)); + tmp_tmp1 = ADDDI (tmp_tmp1, tmp_tmp2); +if (GTDI (tmp_tmp1, MAKEDI (255, 0xffffffff))) { +{ + { + DI opval = MAKEDI (255, 0xffffffff); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval); + written |= (1 << 9); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { +if (LTDI (tmp_tmp1, MAKEDI (0, 0))) { +{ + { + DI opval = MAKEDI (0, 0); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval); + written |= (1 << 9); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { + { + DI opval = tmp_tmp1; + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval); + written |= (1 << 9); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +} +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cmcpxrs: cmcpxrs$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cmcpxrs) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Sk))) { +{ + HI tmp_argihi; + HI tmp_argilo; + HI tmp_argjhi; + HI tmp_argjlo; +{ + tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); + tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); +} +{ + DI tmp_tmp1; + DI tmp_tmp2; + tmp_tmp1 = MULDI (EXTHIDI (tmp_argihi), EXTHIDI (tmp_argjhi)); + tmp_tmp2 = MULDI (EXTHIDI (tmp_argilo), EXTHIDI (tmp_argjlo)); + tmp_tmp1 = SUBDI (tmp_tmp1, tmp_tmp2); +if (GTDI (tmp_tmp1, MAKEDI (127, 0xffffffff))) { +{ + { + DI opval = MAKEDI (127, 0xffffffff); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval); + written |= (1 << 11); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { +if (LTDI (tmp_tmp1, MAKEDI (0xffffff80, 0))) { +{ + { + DI opval = MAKEDI (0xffffff80, 0); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval); + written |= (1 << 11); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { + { + DI opval = tmp_tmp1; + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval); + written |= (1 << 11); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +} +} +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cmcpxru: cmcpxru$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cmcpxru) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Sk))) { +{ + UHI tmp_argihi; + UHI tmp_argilo; + UHI tmp_argjhi; + UHI tmp_argjlo; +{ + tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); + tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); +} +{ + DI tmp_tmp1; + DI tmp_tmp2; + tmp_tmp1 = MULDI (ZEXTHIDI (tmp_argihi), ZEXTHIDI (tmp_argjhi)); + tmp_tmp2 = MULDI (ZEXTHIDI (tmp_argilo), ZEXTHIDI (tmp_argjlo)); + tmp_tmp1 = SUBDI (tmp_tmp1, tmp_tmp2); +if (GTDI (tmp_tmp1, MAKEDI (255, 0xffffffff))) { +{ + { + DI opval = MAKEDI (255, 0xffffffff); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval); + written |= (1 << 11); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { +if (LTDI (tmp_tmp1, MAKEDI (0, 0))) { +{ + { + DI opval = MAKEDI (0, 0); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval); + written |= (1 << 11); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { + { + DI opval = tmp_tmp1; + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval); + written |= (1 << 11); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +} +} +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cmcpxis: cmcpxis$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cmcpxis) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Sk))) { +{ + HI tmp_argihi; + HI tmp_argilo; + HI tmp_argjhi; + HI tmp_argjlo; +{ + tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); + tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); +} +{ + DI tmp_tmp1; + DI tmp_tmp2; + tmp_tmp1 = MULDI (EXTHIDI (tmp_argihi), EXTHIDI (tmp_argjlo)); + tmp_tmp2 = MULDI (EXTHIDI (tmp_argilo), EXTHIDI (tmp_argjhi)); + tmp_tmp1 = ADDDI (tmp_tmp1, tmp_tmp2); +if (GTDI (tmp_tmp1, MAKEDI (127, 0xffffffff))) { +{ + { + DI opval = MAKEDI (127, 0xffffffff); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval); + written |= (1 << 11); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { +if (LTDI (tmp_tmp1, MAKEDI (0xffffff80, 0))) { +{ + { + DI opval = MAKEDI (0xffffff80, 0); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval); + written |= (1 << 11); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { + { + DI opval = tmp_tmp1; + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval); + written |= (1 << 11); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +} +} +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cmcpxiu: cmcpxiu$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cmcpxiu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Sk))) { +{ + UHI tmp_argihi; + UHI tmp_argilo; + UHI tmp_argjhi; + UHI tmp_argjlo; +{ + tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); + tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); +} +{ + DI tmp_tmp1; + DI tmp_tmp2; + tmp_tmp1 = MULDI (ZEXTHIDI (tmp_argihi), ZEXTHIDI (tmp_argjlo)); + tmp_tmp2 = MULDI (ZEXTHIDI (tmp_argilo), ZEXTHIDI (tmp_argjhi)); + tmp_tmp1 = ADDDI (tmp_tmp1, tmp_tmp2); +if (GTDI (tmp_tmp1, MAKEDI (255, 0xffffffff))) { +{ + { + DI opval = MAKEDI (255, 0xffffffff); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval); + written |= (1 << 11); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { +if (LTDI (tmp_tmp1, MAKEDI (0, 0))) { +{ + { + DI opval = MAKEDI (0, 0); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval); + written |= (1 << 11); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { + { + DI opval = tmp_tmp1; + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval); + written |= (1 << 11); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +} +} +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* mqcpxrs: mqcpxrs$pack $FRintieven,$FRintjeven,$ACC40Sk */ + +static SEM_PC +SEM_FN_NAME (frvbf,mqcpxrs) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Sk))) { +if (ANDSI (FLD (f_ACC40Sk), SUBSI (2, 1))) { +frvbf_media_acc_not_aligned (current_cpu); +} else { +if (ORIF (ANDSI (FLD (f_FRi), SUBSI (2, 1)), ANDSI (FLD (f_FRj), SUBSI (2, 1)))) { +frvbf_media_register_not_aligned (current_cpu); +} else { +{ + HI tmp_argihi; + HI tmp_argilo; + HI tmp_argjhi; + HI tmp_argjlo; +{ + tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); + tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); +} +{ + DI tmp_tmp1; + DI tmp_tmp2; + tmp_tmp1 = MULDI (EXTHIDI (tmp_argihi), EXTHIDI (tmp_argjhi)); + tmp_tmp2 = MULDI (EXTHIDI (tmp_argilo), EXTHIDI (tmp_argjlo)); + tmp_tmp1 = SUBDI (tmp_tmp1, tmp_tmp2); +if (GTDI (tmp_tmp1, MAKEDI (127, 0xffffffff))) { +{ + { + DI opval = MAKEDI (127, 0xffffffff); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval); + written |= (1 << 13); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { +if (LTDI (tmp_tmp1, MAKEDI (0xffffff80, 0))) { +{ + { + DI opval = MAKEDI (0xffffff80, 0); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval); + written |= (1 << 13); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { + { + DI opval = tmp_tmp1; + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval); + written |= (1 << 13); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +} +} +} +{ + tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); + tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); +} +{ + DI tmp_tmp1; + DI tmp_tmp2; + tmp_tmp1 = MULDI (EXTHIDI (tmp_argihi), EXTHIDI (tmp_argjhi)); + tmp_tmp2 = MULDI (EXTHIDI (tmp_argilo), EXTHIDI (tmp_argjlo)); + tmp_tmp1 = SUBDI (tmp_tmp1, tmp_tmp2); +if (GTDI (tmp_tmp1, MAKEDI (127, 0xffffffff))) { +{ + { + DI opval = MAKEDI (127, 0xffffffff); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval); + written |= (1 << 14); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 4); +} +} else { +if (LTDI (tmp_tmp1, MAKEDI (0xffffff80, 0))) { +{ + { + DI opval = MAKEDI (0xffffff80, 0); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval); + written |= (1 << 14); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 4); +} +} else { + { + DI opval = tmp_tmp1; + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval); + written |= (1 << 14); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +} +} +} +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* mqcpxru: mqcpxru$pack $FRintieven,$FRintjeven,$ACC40Sk */ + +static SEM_PC +SEM_FN_NAME (frvbf,mqcpxru) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Sk))) { +if (ANDSI (FLD (f_ACC40Sk), SUBSI (2, 1))) { +frvbf_media_acc_not_aligned (current_cpu); +} else { +if (ORIF (ANDSI (FLD (f_FRi), SUBSI (2, 1)), ANDSI (FLD (f_FRj), SUBSI (2, 1)))) { +frvbf_media_register_not_aligned (current_cpu); +} else { +{ + UHI tmp_argihi; + UHI tmp_argilo; + UHI tmp_argjhi; + UHI tmp_argjlo; +{ + tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); + tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); +} +{ + DI tmp_tmp1; + DI tmp_tmp2; + tmp_tmp1 = MULDI (ZEXTHIDI (tmp_argihi), ZEXTHIDI (tmp_argjhi)); + tmp_tmp2 = MULDI (ZEXTHIDI (tmp_argilo), ZEXTHIDI (tmp_argjlo)); + tmp_tmp1 = SUBDI (tmp_tmp1, tmp_tmp2); +if (GTDI (tmp_tmp1, MAKEDI (255, 0xffffffff))) { +{ + { + DI opval = MAKEDI (255, 0xffffffff); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval); + written |= (1 << 13); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { +if (LTDI (tmp_tmp1, MAKEDI (0, 0))) { +{ + { + DI opval = MAKEDI (0, 0); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval); + written |= (1 << 13); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { + { + DI opval = tmp_tmp1; + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval); + written |= (1 << 13); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +} +} +} +{ + tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); + tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); +} +{ + DI tmp_tmp1; + DI tmp_tmp2; + tmp_tmp1 = MULDI (ZEXTHIDI (tmp_argihi), ZEXTHIDI (tmp_argjhi)); + tmp_tmp2 = MULDI (ZEXTHIDI (tmp_argilo), ZEXTHIDI (tmp_argjlo)); + tmp_tmp1 = SUBDI (tmp_tmp1, tmp_tmp2); +if (GTDI (tmp_tmp1, MAKEDI (255, 0xffffffff))) { +{ + { + DI opval = MAKEDI (255, 0xffffffff); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval); + written |= (1 << 14); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 4); +} +} else { +if (LTDI (tmp_tmp1, MAKEDI (0, 0))) { +{ + { + DI opval = MAKEDI (0, 0); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval); + written |= (1 << 14); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 4); +} +} else { + { + DI opval = tmp_tmp1; + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval); + written |= (1 << 14); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +} +} +} +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* mqcpxis: mqcpxis$pack $FRintieven,$FRintjeven,$ACC40Sk */ + +static SEM_PC +SEM_FN_NAME (frvbf,mqcpxis) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Sk))) { +if (ANDSI (FLD (f_ACC40Sk), SUBSI (2, 1))) { +frvbf_media_acc_not_aligned (current_cpu); +} else { +if (ORIF (ANDSI (FLD (f_FRi), SUBSI (2, 1)), ANDSI (FLD (f_FRj), SUBSI (2, 1)))) { +frvbf_media_register_not_aligned (current_cpu); +} else { +{ + HI tmp_argihi; + HI tmp_argilo; + HI tmp_argjhi; + HI tmp_argjlo; +{ + tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); + tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); +} +{ + DI tmp_tmp1; + DI tmp_tmp2; + tmp_tmp1 = MULDI (EXTHIDI (tmp_argihi), EXTHIDI (tmp_argjlo)); + tmp_tmp2 = MULDI (EXTHIDI (tmp_argilo), EXTHIDI (tmp_argjhi)); + tmp_tmp1 = ADDDI (tmp_tmp1, tmp_tmp2); +if (GTDI (tmp_tmp1, MAKEDI (127, 0xffffffff))) { +{ + { + DI opval = MAKEDI (127, 0xffffffff); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval); + written |= (1 << 13); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { +if (LTDI (tmp_tmp1, MAKEDI (0xffffff80, 0))) { +{ + { + DI opval = MAKEDI (0xffffff80, 0); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval); + written |= (1 << 13); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { + { + DI opval = tmp_tmp1; + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval); + written |= (1 << 13); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +} +} +} +{ + tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); + tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); +} +{ + DI tmp_tmp1; + DI tmp_tmp2; + tmp_tmp1 = MULDI (EXTHIDI (tmp_argihi), EXTHIDI (tmp_argjlo)); + tmp_tmp2 = MULDI (EXTHIDI (tmp_argilo), EXTHIDI (tmp_argjhi)); + tmp_tmp1 = ADDDI (tmp_tmp1, tmp_tmp2); +if (GTDI (tmp_tmp1, MAKEDI (127, 0xffffffff))) { +{ + { + DI opval = MAKEDI (127, 0xffffffff); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval); + written |= (1 << 14); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 4); +} +} else { +if (LTDI (tmp_tmp1, MAKEDI (0xffffff80, 0))) { +{ + { + DI opval = MAKEDI (0xffffff80, 0); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval); + written |= (1 << 14); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 4); +} +} else { + { + DI opval = tmp_tmp1; + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval); + written |= (1 << 14); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +} +} +} +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* mqcpxiu: mqcpxiu$pack $FRintieven,$FRintjeven,$ACC40Sk */ + +static SEM_PC +SEM_FN_NAME (frvbf,mqcpxiu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Sk))) { +if (ANDSI (FLD (f_ACC40Sk), SUBSI (2, 1))) { +frvbf_media_acc_not_aligned (current_cpu); +} else { +if (ORIF (ANDSI (FLD (f_FRi), SUBSI (2, 1)), ANDSI (FLD (f_FRj), SUBSI (2, 1)))) { +frvbf_media_register_not_aligned (current_cpu); +} else { +{ + UHI tmp_argihi; + UHI tmp_argilo; + UHI tmp_argjhi; + UHI tmp_argjlo; +{ + tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); + tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); +} +{ + DI tmp_tmp1; + DI tmp_tmp2; + tmp_tmp1 = MULDI (ZEXTHIDI (tmp_argihi), ZEXTHIDI (tmp_argjlo)); + tmp_tmp2 = MULDI (ZEXTHIDI (tmp_argilo), ZEXTHIDI (tmp_argjhi)); + tmp_tmp1 = ADDDI (tmp_tmp1, tmp_tmp2); +if (GTDI (tmp_tmp1, MAKEDI (255, 0xffffffff))) { +{ + { + DI opval = MAKEDI (255, 0xffffffff); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval); + written |= (1 << 13); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { +if (LTDI (tmp_tmp1, MAKEDI (0, 0))) { +{ + { + DI opval = MAKEDI (0, 0); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval); + written |= (1 << 13); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 8); +} +} else { + { + DI opval = tmp_tmp1; + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval); + written |= (1 << 13); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +} +} +} +{ + tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); + tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); +} +{ + DI tmp_tmp1; + DI tmp_tmp2; + tmp_tmp1 = MULDI (ZEXTHIDI (tmp_argihi), ZEXTHIDI (tmp_argjlo)); + tmp_tmp2 = MULDI (ZEXTHIDI (tmp_argilo), ZEXTHIDI (tmp_argjhi)); + tmp_tmp1 = ADDDI (tmp_tmp1, tmp_tmp2); +if (GTDI (tmp_tmp1, MAKEDI (255, 0xffffffff))) { +{ + { + DI opval = MAKEDI (255, 0xffffffff); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval); + written |= (1 << 14); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 4); +} +} else { +if (LTDI (tmp_tmp1, MAKEDI (0, 0))) { +{ + { + DI opval = MAKEDI (0, 0); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval); + written |= (1 << 14); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +frvbf_media_overflow (current_cpu, 4); +} +} else { + { + DI opval = tmp_tmp1; + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval); + written |= (1 << 14); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } +} +} +} +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* mexpdhw: mexpdhw$pack $FRinti,$u6,$FRintk */ + +static SEM_PC +SEM_FN_NAME (frvbf,mexpdhw) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmexpdhw.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + UHI tmp_tmp; +if (ANDSI (FLD (f_u6), 1)) { + tmp_tmp = GET_H_FR_LO (((FLD (f_FRi)) + (0))); +} else { + tmp_tmp = GET_H_FR_HI (((FLD (f_FRi)) + (0))); +} + { + UHI opval = tmp_tmp; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } + { + UHI opval = tmp_tmp; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +} + + return vpc; +#undef FLD +} + +/* cmexpdhw: cmexpdhw$pack $FRinti,$u6,$FRintk,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cmexpdhw) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmexpdhw.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +{ + UHI tmp_tmp; +if (ANDSI (FLD (f_u6), 1)) { + tmp_tmp = GET_H_FR_LO (((FLD (f_FRi)) + (0))); +} else { + tmp_tmp = GET_H_FR_HI (((FLD (f_FRi)) + (0))); +} + { + UHI opval = tmp_tmp; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 7); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } + { + UHI opval = tmp_tmp; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 8); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* mexpdhd: mexpdhd$pack $FRinti,$u6,$FRintkeven */ + +static SEM_PC +SEM_FN_NAME (frvbf,mexpdhd) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmexpdhd.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (ANDSI (FLD (f_FRk), SUBSI (2, 1))) { +frvbf_media_register_not_aligned (current_cpu); +} else { +{ + UHI tmp_tmp; + { + SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRk))); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } +if (ANDSI (FLD (f_u6), 1)) { + tmp_tmp = GET_H_FR_LO (((FLD (f_FRi)) + (0))); +} else { + tmp_tmp = GET_H_FR_HI (((FLD (f_FRi)) + (0))); +} + { + UHI opval = tmp_tmp; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 7); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } + { + UHI opval = tmp_tmp; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 9); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } + { + UHI opval = tmp_tmp; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (1)), opval); + written |= (1 << 8); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } + { + UHI opval = tmp_tmp; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (1)), opval); + written |= (1 << 10); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cmexpdhd: cmexpdhd$pack $FRinti,$u6,$FRintkeven,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cmexpdhd) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmexpdhd.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (ANDSI (FLD (f_FRk), SUBSI (2, 1))) { +frvbf_media_register_not_aligned (current_cpu); +} else { +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +{ + UHI tmp_tmp; + { + SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRk))); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + written |= (1 << 8); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } +if (ANDSI (FLD (f_u6), 1)) { + tmp_tmp = GET_H_FR_LO (((FLD (f_FRi)) + (0))); +} else { + tmp_tmp = GET_H_FR_HI (((FLD (f_FRi)) + (0))); +} + { + UHI opval = tmp_tmp; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 9); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } + { + UHI opval = tmp_tmp; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 11); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } + { + UHI opval = tmp_tmp; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (1)), opval); + written |= (1 << 10); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } + { + UHI opval = tmp_tmp; + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (1)), opval); + written |= (1 << 12); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* mpackh: mpackh$pack $FRinti,$FRintj,$FRintk */ + +static SEM_PC +SEM_FN_NAME (frvbf,mpackh) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + { + UHI opval = GET_H_FR_LO (((FLD (f_FRi)) + (0))); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } + { + UHI opval = GET_H_FR_LO (((FLD (f_FRj)) + (0))); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +} + + return vpc; +#undef FLD +} + +/* mdpackh: mdpackh$pack $FRintieven,$FRintjeven,$FRintkeven */ + +static SEM_PC +SEM_FN_NAME (frvbf,mdpackh) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdpackh.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (ORIF (ANDSI (FLD (f_FRi), SUBSI (2, 1)), ORIF (ANDSI (FLD (f_FRj), SUBSI (2, 1)), ANDSI (FLD (f_FRk), SUBSI (2, 1))))) { +frvbf_media_register_not_aligned (current_cpu); +} else { +{ + { + SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRi))); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRi), opval); + written |= (1 << 10); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } + { + SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRj))); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRj), opval); + written |= (1 << 11); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } + { + SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRk))); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + written |= (1 << 12); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } +{ + { + UHI opval = GET_H_FR_LO (((FLD (f_FRi)) + (0))); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 13); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } + { + UHI opval = GET_H_FR_LO (((FLD (f_FRj)) + (0))); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 15); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +} +{ + { + UHI opval = GET_H_FR_LO (((FLD (f_FRi)) + (1))); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (1)), opval); + written |= (1 << 14); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } + { + UHI opval = GET_H_FR_LO (((FLD (f_FRj)) + (1))); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (1)), opval); + written |= (1 << 16); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* munpackh: munpackh$pack $FRinti,$FRintkeven */ + +static SEM_PC +SEM_FN_NAME (frvbf,munpackh) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_munpackh.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (ANDSI (FLD (f_FRk), SUBSI (2, 1))) { +frvbf_media_register_not_aligned (current_cpu); +} else { +{ + { + SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRi))); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRi), opval); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } + { + SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRk))); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + written |= (1 << 7); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } +{ + { + UHI opval = GET_H_FR_HI (((FLD (f_FRi)) + (0))); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 8); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } + { + UHI opval = GET_H_FR_HI (((FLD (f_FRi)) + (0))); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 10); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } + { + UHI opval = GET_H_FR_LO (((FLD (f_FRi)) + (0))); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (ADDSI (0, 1))), opval); + written |= (1 << 9); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } + { + UHI opval = GET_H_FR_LO (((FLD (f_FRi)) + (0))); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (ADDSI (0, 1))), opval); + written |= (1 << 11); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* mdunpackh: mdunpackh$pack $FRintieven,$FRintk */ + +static SEM_PC +SEM_FN_NAME (frvbf,mdunpackh) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdunpackh.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (ORIF (ANDSI (FLD (f_FRi), SUBSI (2, 1)), ANDSI (FLD (f_FRk), SUBSI (4, 1)))) { +frvbf_media_register_not_aligned (current_cpu); +} else { +{ + { + SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRi))); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRi), opval); + written |= (1 << 8); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } + { + SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRk))); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + written |= (1 << 9); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } +{ + { + UHI opval = GET_H_FR_HI (((FLD (f_FRi)) + (0))); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 10); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } + { + UHI opval = GET_H_FR_HI (((FLD (f_FRi)) + (0))); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 14); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } + { + UHI opval = GET_H_FR_LO (((FLD (f_FRi)) + (0))); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (ADDSI (0, 1))), opval); + written |= (1 << 12); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } + { + UHI opval = GET_H_FR_LO (((FLD (f_FRi)) + (0))); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (ADDSI (0, 1))), opval); + written |= (1 << 16); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +} +{ + { + UHI opval = GET_H_FR_HI (((FLD (f_FRi)) + (1))); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (2)), opval); + written |= (1 << 11); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } + { + UHI opval = GET_H_FR_HI (((FLD (f_FRi)) + (1))); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (2)), opval); + written |= (1 << 15); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } + { + UHI opval = GET_H_FR_LO (((FLD (f_FRi)) + (1))); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (ADDSI (2, 1))), opval); + written |= (1 << 13); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } + { + UHI opval = GET_H_FR_LO (((FLD (f_FRi)) + (1))); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (ADDSI (2, 1))), opval); + written |= (1 << 17); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* mbtoh: mbtoh$pack $FRintj,$FRintkeven */ + +static SEM_PC +SEM_FN_NAME (frvbf,mbtoh) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmbtoh.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + { + SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRj))); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRj), opval); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } + { + SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRk))); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } +if (ANDSI (FLD (f_FRk), SUBSI (2, 1))) { +frvbf_media_register_not_aligned (current_cpu); +} else { +{ + { + UHI opval = GET_H_FR_3 (((FLD (f_FRj)) + (0))); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 10); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } + { + UHI opval = GET_H_FR_2 (((FLD (f_FRj)) + (0))); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 12); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } + { + UHI opval = GET_H_FR_1 (((FLD (f_FRj)) + (0))); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (1)), opval); + written |= (1 << 11); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } + { + UHI opval = GET_H_FR_0 (((FLD (f_FRj)) + (0))); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (1)), opval); + written |= (1 << 13); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cmbtoh: cmbtoh$pack $FRintj,$FRintkeven,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cmbtoh) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmbtoh.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + { + SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRj))); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRj), opval); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } + { + SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRk))); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } +if (ANDSI (FLD (f_FRk), SUBSI (2, 1))) { +frvbf_media_register_not_aligned (current_cpu); +} else { +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +{ + { + UHI opval = GET_H_FR_3 (((FLD (f_FRj)) + (0))); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 12); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } + { + UHI opval = GET_H_FR_2 (((FLD (f_FRj)) + (0))); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 14); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } + { + UHI opval = GET_H_FR_1 (((FLD (f_FRj)) + (0))); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (1)), opval); + written |= (1 << 13); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } + { + UHI opval = GET_H_FR_0 (((FLD (f_FRj)) + (0))); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (1)), opval); + written |= (1 << 15); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* mhtob: mhtob$pack $FRintjeven,$FRintk */ + +static SEM_PC +SEM_FN_NAME (frvbf,mhtob) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmhtob.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + { + SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRj))); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRj), opval); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } + { + SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRk))); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } +if (ANDSI (FLD (f_FRj), SUBSI (2, 1))) { +frvbf_media_register_not_aligned (current_cpu); +} else { +{ + { + UHI opval = GET_H_FR_HI (((FLD (f_FRj)) + (0))); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_3_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 13); + TRACE_RESULT (current_cpu, abuf, "fr_3", 'x', opval); + } + { + UHI opval = GET_H_FR_LO (((FLD (f_FRj)) + (0))); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_2_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 12); + TRACE_RESULT (current_cpu, abuf, "fr_2", 'x', opval); + } + { + UHI opval = GET_H_FR_HI (((FLD (f_FRj)) + (1))); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_1_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 11); + TRACE_RESULT (current_cpu, abuf, "fr_1", 'x', opval); + } + { + UHI opval = GET_H_FR_LO (((FLD (f_FRj)) + (1))); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_0_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 10); + TRACE_RESULT (current_cpu, abuf, "fr_0", 'x', opval); + } +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cmhtob: cmhtob$pack $FRintjeven,$FRintk,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cmhtob) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmhtob.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + { + SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRj))); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRj), opval); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } + { + SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRk))); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } +if (ANDSI (FLD (f_FRj), SUBSI (2, 1))) { +frvbf_media_register_not_aligned (current_cpu); +} else { +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +{ + { + UHI opval = GET_H_FR_HI (((FLD (f_FRj)) + (0))); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_3_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 15); + TRACE_RESULT (current_cpu, abuf, "fr_3", 'x', opval); + } + { + UHI opval = GET_H_FR_LO (((FLD (f_FRj)) + (0))); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_2_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 14); + TRACE_RESULT (current_cpu, abuf, "fr_2", 'x', opval); + } + { + UHI opval = GET_H_FR_HI (((FLD (f_FRj)) + (1))); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_1_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 13); + TRACE_RESULT (current_cpu, abuf, "fr_1", 'x', opval); + } + { + UHI opval = GET_H_FR_LO (((FLD (f_FRj)) + (1))); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_0_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 12); + TRACE_RESULT (current_cpu, abuf, "fr_0", 'x', opval); + } +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* mbtohe: mbtohe$pack $FRintj,$FRintk */ + +static SEM_PC +SEM_FN_NAME (frvbf,mbtohe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmbtohe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + { + SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRj))); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRj), opval); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } + { + SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRk))); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } +if (ANDSI (FLD (f_FRk), SUBSI (4, 1))) { +frvbf_media_register_not_aligned (current_cpu); +} else { +{ + { + UHI opval = GET_H_FR_3 (((FLD (f_FRj)) + (0))); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 10); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } + { + UHI opval = GET_H_FR_3 (((FLD (f_FRj)) + (0))); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 14); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } + { + UHI opval = GET_H_FR_2 (((FLD (f_FRj)) + (0))); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (1)), opval); + written |= (1 << 11); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } + { + UHI opval = GET_H_FR_2 (((FLD (f_FRj)) + (0))); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (1)), opval); + written |= (1 << 15); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } + { + UHI opval = GET_H_FR_1 (((FLD (f_FRj)) + (0))); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (2)), opval); + written |= (1 << 12); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } + { + UHI opval = GET_H_FR_1 (((FLD (f_FRj)) + (0))); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (2)), opval); + written |= (1 << 16); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } + { + UHI opval = GET_H_FR_0 (((FLD (f_FRj)) + (0))); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (3)), opval); + written |= (1 << 13); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } + { + UHI opval = GET_H_FR_0 (((FLD (f_FRj)) + (0))); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (3)), opval); + written |= (1 << 17); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* cmbtohe: cmbtohe$pack $FRintj,$FRintk,$CCi,$cond */ + +static SEM_PC +SEM_FN_NAME (frvbf,cmbtohe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmbtohe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + { + SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRj))); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRj), opval); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } + { + SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRk))); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } +if (ANDSI (FLD (f_FRk), SUBSI (4, 1))) { +frvbf_media_register_not_aligned (current_cpu); +} else { +if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { +{ + { + UHI opval = GET_H_FR_3 (((FLD (f_FRj)) + (0))); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 12); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } + { + UHI opval = GET_H_FR_3 (((FLD (f_FRj)) + (0))); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 16); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } + { + UHI opval = GET_H_FR_2 (((FLD (f_FRj)) + (0))); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (1)), opval); + written |= (1 << 13); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } + { + UHI opval = GET_H_FR_2 (((FLD (f_FRj)) + (0))); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (1)), opval); + written |= (1 << 17); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } + { + UHI opval = GET_H_FR_1 (((FLD (f_FRj)) + (0))); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (2)), opval); + written |= (1 << 14); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } + { + UHI opval = GET_H_FR_1 (((FLD (f_FRj)) + (0))); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (2)), opval); + written |= (1 << 18); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } + { + UHI opval = GET_H_FR_0 (((FLD (f_FRj)) + (0))); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (3)), opval); + written |= (1 << 15); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } + { + UHI opval = GET_H_FR_0 (((FLD (f_FRj)) + (0))); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (3)), opval); + written |= (1 << 19); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +} +} +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* mnop: mnop$pack */ + +static SEM_PC +SEM_FN_NAME (frvbf,mnop) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + return vpc; +#undef FLD +} + +/* mclracc-0: mclracc$pack $ACC40Sk,$A0 */ + +static SEM_PC +SEM_FN_NAME (frvbf,mclracc_0) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdasaccs.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +frvbf_clear_accumulators (current_cpu, FLD (f_ACC40Sk), 0); + + return vpc; +#undef FLD +} + +/* mclracc-1: mclracc$pack $ACC40Sk,$A1 */ + +static SEM_PC +SEM_FN_NAME (frvbf,mclracc_1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdasaccs.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +frvbf_clear_accumulators (current_cpu, FLD (f_ACC40Sk), 1); + + return vpc; +#undef FLD +} + +/* mrdacc: mrdacc$pack $ACC40Si,$FRintk */ + +static SEM_PC +SEM_FN_NAME (frvbf,mrdacc) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mcuti.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = GET_H_ACC40S (FLD (f_ACC40Si)); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* mrdaccg: mrdaccg$pack $ACCGi,$FRintk */ + +static SEM_PC +SEM_FN_NAME (frvbf,mrdaccg) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mrdaccg.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = GET_H_ACCG (FLD (f_ACCGi)); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* mwtacc: mwtacc$pack $FRinti,$ACC40Sk */ + +static SEM_PC +SEM_FN_NAME (frvbf,mwtacc) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + DI opval = ORDI (ANDDI (GET_H_ACC40S (FLD (f_ACC40Sk)), MAKEDI (0xffffffff, 0)), GET_H_FR_INT (FLD (f_FRi))); + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval); + TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval); + } + + return vpc; +#undef FLD +} + +/* mwtaccg: mwtaccg$pack $FRinti,$ACCGk */ + +static SEM_PC +SEM_FN_NAME (frvbf,mwtaccg) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mwtaccg.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +frv_ref_SI (GET_H_ACCG (FLD (f_ACCGk))); + { + USI opval = GET_H_FR_INT (FLD (f_FRi)); + sim_queue_fn_si_write (current_cpu, frvbf_h_accg_set, FLD (f_ACCGk), opval); + TRACE_RESULT (current_cpu, abuf, "accg", 'x', opval); + } +} + + return vpc; +#undef FLD +} + +/* mcop1: mcop1$pack $FRi,$FRj,$FRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,mcop1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +frvbf_media_cop (current_cpu, 1); + + return vpc; +#undef FLD +} + +/* mcop2: mcop2$pack $FRi,$FRj,$FRk */ + +static SEM_PC +SEM_FN_NAME (frvbf,mcop2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +frvbf_media_cop (current_cpu, 2); + + return vpc; +#undef FLD +} + +/* fnop: fnop$pack */ + +static SEM_PC +SEM_FN_NAME (frvbf,fnop) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + return vpc; +#undef FLD +} + +/* Table of all semantic fns. */ + +static const struct sem_fn_desc sem_fns[] = { + { FRVBF_INSN_X_INVALID, SEM_FN_NAME (frvbf,x_invalid) }, + { FRVBF_INSN_X_AFTER, SEM_FN_NAME (frvbf,x_after) }, + { FRVBF_INSN_X_BEFORE, SEM_FN_NAME (frvbf,x_before) }, + { FRVBF_INSN_X_CTI_CHAIN, SEM_FN_NAME (frvbf,x_cti_chain) }, + { FRVBF_INSN_X_CHAIN, SEM_FN_NAME (frvbf,x_chain) }, + { FRVBF_INSN_X_BEGIN, SEM_FN_NAME (frvbf,x_begin) }, + { FRVBF_INSN_ADD, SEM_FN_NAME (frvbf,add) }, + { FRVBF_INSN_SUB, SEM_FN_NAME (frvbf,sub) }, + { FRVBF_INSN_AND, SEM_FN_NAME (frvbf,and) }, + { FRVBF_INSN_OR, SEM_FN_NAME (frvbf,or) }, + { FRVBF_INSN_XOR, SEM_FN_NAME (frvbf,xor) }, + { FRVBF_INSN_NOT, SEM_FN_NAME (frvbf,not) }, + { FRVBF_INSN_SDIV, SEM_FN_NAME (frvbf,sdiv) }, + { FRVBF_INSN_NSDIV, SEM_FN_NAME (frvbf,nsdiv) }, + { FRVBF_INSN_UDIV, SEM_FN_NAME (frvbf,udiv) }, + { FRVBF_INSN_NUDIV, SEM_FN_NAME (frvbf,nudiv) }, + { FRVBF_INSN_SMUL, SEM_FN_NAME (frvbf,smul) }, + { FRVBF_INSN_UMUL, SEM_FN_NAME (frvbf,umul) }, + { FRVBF_INSN_SMU, SEM_FN_NAME (frvbf,smu) }, + { FRVBF_INSN_SMASS, SEM_FN_NAME (frvbf,smass) }, + { FRVBF_INSN_SMSSS, SEM_FN_NAME (frvbf,smsss) }, + { FRVBF_INSN_SLL, SEM_FN_NAME (frvbf,sll) }, + { FRVBF_INSN_SRL, SEM_FN_NAME (frvbf,srl) }, + { FRVBF_INSN_SRA, SEM_FN_NAME (frvbf,sra) }, + { FRVBF_INSN_SLASS, SEM_FN_NAME (frvbf,slass) }, + { FRVBF_INSN_SCUTSS, SEM_FN_NAME (frvbf,scutss) }, + { FRVBF_INSN_SCAN, SEM_FN_NAME (frvbf,scan) }, + { FRVBF_INSN_CADD, SEM_FN_NAME (frvbf,cadd) }, + { FRVBF_INSN_CSUB, SEM_FN_NAME (frvbf,csub) }, + { FRVBF_INSN_CAND, SEM_FN_NAME (frvbf,cand) }, + { FRVBF_INSN_COR, SEM_FN_NAME (frvbf,cor) }, + { FRVBF_INSN_CXOR, SEM_FN_NAME (frvbf,cxor) }, + { FRVBF_INSN_CNOT, SEM_FN_NAME (frvbf,cnot) }, + { FRVBF_INSN_CSMUL, SEM_FN_NAME (frvbf,csmul) }, + { FRVBF_INSN_CSDIV, SEM_FN_NAME (frvbf,csdiv) }, + { FRVBF_INSN_CUDIV, SEM_FN_NAME (frvbf,cudiv) }, + { FRVBF_INSN_CSLL, SEM_FN_NAME (frvbf,csll) }, + { FRVBF_INSN_CSRL, SEM_FN_NAME (frvbf,csrl) }, + { FRVBF_INSN_CSRA, SEM_FN_NAME (frvbf,csra) }, + { FRVBF_INSN_CSCAN, SEM_FN_NAME (frvbf,cscan) }, + { FRVBF_INSN_ADDCC, SEM_FN_NAME (frvbf,addcc) }, + { FRVBF_INSN_SUBCC, SEM_FN_NAME (frvbf,subcc) }, + { FRVBF_INSN_ANDCC, SEM_FN_NAME (frvbf,andcc) }, + { FRVBF_INSN_ORCC, SEM_FN_NAME (frvbf,orcc) }, + { FRVBF_INSN_XORCC, SEM_FN_NAME (frvbf,xorcc) }, + { FRVBF_INSN_SLLCC, SEM_FN_NAME (frvbf,sllcc) }, + { FRVBF_INSN_SRLCC, SEM_FN_NAME (frvbf,srlcc) }, + { FRVBF_INSN_SRACC, SEM_FN_NAME (frvbf,sracc) }, + { FRVBF_INSN_SMULCC, SEM_FN_NAME (frvbf,smulcc) }, + { FRVBF_INSN_UMULCC, SEM_FN_NAME (frvbf,umulcc) }, + { FRVBF_INSN_CADDCC, SEM_FN_NAME (frvbf,caddcc) }, + { FRVBF_INSN_CSUBCC, SEM_FN_NAME (frvbf,csubcc) }, + { FRVBF_INSN_CSMULCC, SEM_FN_NAME (frvbf,csmulcc) }, + { FRVBF_INSN_CANDCC, SEM_FN_NAME (frvbf,candcc) }, + { FRVBF_INSN_CORCC, SEM_FN_NAME (frvbf,corcc) }, + { FRVBF_INSN_CXORCC, SEM_FN_NAME (frvbf,cxorcc) }, + { FRVBF_INSN_CSLLCC, SEM_FN_NAME (frvbf,csllcc) }, + { FRVBF_INSN_CSRLCC, SEM_FN_NAME (frvbf,csrlcc) }, + { FRVBF_INSN_CSRACC, SEM_FN_NAME (frvbf,csracc) }, + { FRVBF_INSN_ADDX, SEM_FN_NAME (frvbf,addx) }, + { FRVBF_INSN_SUBX, SEM_FN_NAME (frvbf,subx) }, + { FRVBF_INSN_ADDXCC, SEM_FN_NAME (frvbf,addxcc) }, + { FRVBF_INSN_SUBXCC, SEM_FN_NAME (frvbf,subxcc) }, + { FRVBF_INSN_ADDSS, SEM_FN_NAME (frvbf,addss) }, + { FRVBF_INSN_SUBSS, SEM_FN_NAME (frvbf,subss) }, + { FRVBF_INSN_ADDI, SEM_FN_NAME (frvbf,addi) }, + { FRVBF_INSN_SUBI, SEM_FN_NAME (frvbf,subi) }, + { FRVBF_INSN_ANDI, SEM_FN_NAME (frvbf,andi) }, + { FRVBF_INSN_ORI, SEM_FN_NAME (frvbf,ori) }, + { FRVBF_INSN_XORI, SEM_FN_NAME (frvbf,xori) }, + { FRVBF_INSN_SDIVI, SEM_FN_NAME (frvbf,sdivi) }, + { FRVBF_INSN_NSDIVI, SEM_FN_NAME (frvbf,nsdivi) }, + { FRVBF_INSN_UDIVI, SEM_FN_NAME (frvbf,udivi) }, + { FRVBF_INSN_NUDIVI, SEM_FN_NAME (frvbf,nudivi) }, + { FRVBF_INSN_SMULI, SEM_FN_NAME (frvbf,smuli) }, + { FRVBF_INSN_UMULI, SEM_FN_NAME (frvbf,umuli) }, + { FRVBF_INSN_SLLI, SEM_FN_NAME (frvbf,slli) }, + { FRVBF_INSN_SRLI, SEM_FN_NAME (frvbf,srli) }, + { FRVBF_INSN_SRAI, SEM_FN_NAME (frvbf,srai) }, + { FRVBF_INSN_SCANI, SEM_FN_NAME (frvbf,scani) }, + { FRVBF_INSN_ADDICC, SEM_FN_NAME (frvbf,addicc) }, + { FRVBF_INSN_SUBICC, SEM_FN_NAME (frvbf,subicc) }, + { FRVBF_INSN_ANDICC, SEM_FN_NAME (frvbf,andicc) }, + { FRVBF_INSN_ORICC, SEM_FN_NAME (frvbf,oricc) }, + { FRVBF_INSN_XORICC, SEM_FN_NAME (frvbf,xoricc) }, + { FRVBF_INSN_SMULICC, SEM_FN_NAME (frvbf,smulicc) }, + { FRVBF_INSN_UMULICC, SEM_FN_NAME (frvbf,umulicc) }, + { FRVBF_INSN_SLLICC, SEM_FN_NAME (frvbf,sllicc) }, + { FRVBF_INSN_SRLICC, SEM_FN_NAME (frvbf,srlicc) }, + { FRVBF_INSN_SRAICC, SEM_FN_NAME (frvbf,sraicc) }, + { FRVBF_INSN_ADDXI, SEM_FN_NAME (frvbf,addxi) }, + { FRVBF_INSN_SUBXI, SEM_FN_NAME (frvbf,subxi) }, + { FRVBF_INSN_ADDXICC, SEM_FN_NAME (frvbf,addxicc) }, + { FRVBF_INSN_SUBXICC, SEM_FN_NAME (frvbf,subxicc) }, + { FRVBF_INSN_CMPB, SEM_FN_NAME (frvbf,cmpb) }, + { FRVBF_INSN_CMPBA, SEM_FN_NAME (frvbf,cmpba) }, + { FRVBF_INSN_SETLO, SEM_FN_NAME (frvbf,setlo) }, + { FRVBF_INSN_SETHI, SEM_FN_NAME (frvbf,sethi) }, + { FRVBF_INSN_SETLOS, SEM_FN_NAME (frvbf,setlos) }, + { FRVBF_INSN_LDSB, SEM_FN_NAME (frvbf,ldsb) }, + { FRVBF_INSN_LDUB, SEM_FN_NAME (frvbf,ldub) }, + { FRVBF_INSN_LDSH, SEM_FN_NAME (frvbf,ldsh) }, + { FRVBF_INSN_LDUH, SEM_FN_NAME (frvbf,lduh) }, + { FRVBF_INSN_LD, SEM_FN_NAME (frvbf,ld) }, + { FRVBF_INSN_LDBF, SEM_FN_NAME (frvbf,ldbf) }, + { FRVBF_INSN_LDHF, SEM_FN_NAME (frvbf,ldhf) }, + { FRVBF_INSN_LDF, SEM_FN_NAME (frvbf,ldf) }, + { FRVBF_INSN_LDC, SEM_FN_NAME (frvbf,ldc) }, + { FRVBF_INSN_NLDSB, SEM_FN_NAME (frvbf,nldsb) }, + { FRVBF_INSN_NLDUB, SEM_FN_NAME (frvbf,nldub) }, + { FRVBF_INSN_NLDSH, SEM_FN_NAME (frvbf,nldsh) }, + { FRVBF_INSN_NLDUH, SEM_FN_NAME (frvbf,nlduh) }, + { FRVBF_INSN_NLD, SEM_FN_NAME (frvbf,nld) }, + { FRVBF_INSN_NLDBF, SEM_FN_NAME (frvbf,nldbf) }, + { FRVBF_INSN_NLDHF, SEM_FN_NAME (frvbf,nldhf) }, + { FRVBF_INSN_NLDF, SEM_FN_NAME (frvbf,nldf) }, + { FRVBF_INSN_LDD, SEM_FN_NAME (frvbf,ldd) }, + { FRVBF_INSN_LDDF, SEM_FN_NAME (frvbf,lddf) }, + { FRVBF_INSN_LDDC, SEM_FN_NAME (frvbf,lddc) }, + { FRVBF_INSN_NLDD, SEM_FN_NAME (frvbf,nldd) }, + { FRVBF_INSN_NLDDF, SEM_FN_NAME (frvbf,nlddf) }, + { FRVBF_INSN_LDQ, SEM_FN_NAME (frvbf,ldq) }, + { FRVBF_INSN_LDQF, SEM_FN_NAME (frvbf,ldqf) }, + { FRVBF_INSN_LDQC, SEM_FN_NAME (frvbf,ldqc) }, + { FRVBF_INSN_NLDQ, SEM_FN_NAME (frvbf,nldq) }, + { FRVBF_INSN_NLDQF, SEM_FN_NAME (frvbf,nldqf) }, + { FRVBF_INSN_LDSBU, SEM_FN_NAME (frvbf,ldsbu) }, + { FRVBF_INSN_LDUBU, SEM_FN_NAME (frvbf,ldubu) }, + { FRVBF_INSN_LDSHU, SEM_FN_NAME (frvbf,ldshu) }, + { FRVBF_INSN_LDUHU, SEM_FN_NAME (frvbf,lduhu) }, + { FRVBF_INSN_LDU, SEM_FN_NAME (frvbf,ldu) }, + { FRVBF_INSN_NLDSBU, SEM_FN_NAME (frvbf,nldsbu) }, + { FRVBF_INSN_NLDUBU, SEM_FN_NAME (frvbf,nldubu) }, + { FRVBF_INSN_NLDSHU, SEM_FN_NAME (frvbf,nldshu) }, + { FRVBF_INSN_NLDUHU, SEM_FN_NAME (frvbf,nlduhu) }, + { FRVBF_INSN_NLDU, SEM_FN_NAME (frvbf,nldu) }, + { FRVBF_INSN_LDBFU, SEM_FN_NAME (frvbf,ldbfu) }, + { FRVBF_INSN_LDHFU, SEM_FN_NAME (frvbf,ldhfu) }, + { FRVBF_INSN_LDFU, SEM_FN_NAME (frvbf,ldfu) }, + { FRVBF_INSN_LDCU, SEM_FN_NAME (frvbf,ldcu) }, + { FRVBF_INSN_NLDBFU, SEM_FN_NAME (frvbf,nldbfu) }, + { FRVBF_INSN_NLDHFU, SEM_FN_NAME (frvbf,nldhfu) }, + { FRVBF_INSN_NLDFU, SEM_FN_NAME (frvbf,nldfu) }, + { FRVBF_INSN_LDDU, SEM_FN_NAME (frvbf,lddu) }, + { FRVBF_INSN_NLDDU, SEM_FN_NAME (frvbf,nlddu) }, + { FRVBF_INSN_LDDFU, SEM_FN_NAME (frvbf,lddfu) }, + { FRVBF_INSN_LDDCU, SEM_FN_NAME (frvbf,lddcu) }, + { FRVBF_INSN_NLDDFU, SEM_FN_NAME (frvbf,nlddfu) }, + { FRVBF_INSN_LDQU, SEM_FN_NAME (frvbf,ldqu) }, + { FRVBF_INSN_NLDQU, SEM_FN_NAME (frvbf,nldqu) }, + { FRVBF_INSN_LDQFU, SEM_FN_NAME (frvbf,ldqfu) }, + { FRVBF_INSN_LDQCU, SEM_FN_NAME (frvbf,ldqcu) }, + { FRVBF_INSN_NLDQFU, SEM_FN_NAME (frvbf,nldqfu) }, + { FRVBF_INSN_LDSBI, SEM_FN_NAME (frvbf,ldsbi) }, + { FRVBF_INSN_LDSHI, SEM_FN_NAME (frvbf,ldshi) }, + { FRVBF_INSN_LDI, SEM_FN_NAME (frvbf,ldi) }, + { FRVBF_INSN_LDUBI, SEM_FN_NAME (frvbf,ldubi) }, + { FRVBF_INSN_LDUHI, SEM_FN_NAME (frvbf,lduhi) }, + { FRVBF_INSN_LDBFI, SEM_FN_NAME (frvbf,ldbfi) }, + { FRVBF_INSN_LDHFI, SEM_FN_NAME (frvbf,ldhfi) }, + { FRVBF_INSN_LDFI, SEM_FN_NAME (frvbf,ldfi) }, + { FRVBF_INSN_NLDSBI, SEM_FN_NAME (frvbf,nldsbi) }, + { FRVBF_INSN_NLDUBI, SEM_FN_NAME (frvbf,nldubi) }, + { FRVBF_INSN_NLDSHI, SEM_FN_NAME (frvbf,nldshi) }, + { FRVBF_INSN_NLDUHI, SEM_FN_NAME (frvbf,nlduhi) }, + { FRVBF_INSN_NLDI, SEM_FN_NAME (frvbf,nldi) }, + { FRVBF_INSN_NLDBFI, SEM_FN_NAME (frvbf,nldbfi) }, + { FRVBF_INSN_NLDHFI, SEM_FN_NAME (frvbf,nldhfi) }, + { FRVBF_INSN_NLDFI, SEM_FN_NAME (frvbf,nldfi) }, + { FRVBF_INSN_LDDI, SEM_FN_NAME (frvbf,lddi) }, + { FRVBF_INSN_LDDFI, SEM_FN_NAME (frvbf,lddfi) }, + { FRVBF_INSN_NLDDI, SEM_FN_NAME (frvbf,nlddi) }, + { FRVBF_INSN_NLDDFI, SEM_FN_NAME (frvbf,nlddfi) }, + { FRVBF_INSN_LDQI, SEM_FN_NAME (frvbf,ldqi) }, + { FRVBF_INSN_LDQFI, SEM_FN_NAME (frvbf,ldqfi) }, + { FRVBF_INSN_NLDQFI, SEM_FN_NAME (frvbf,nldqfi) }, + { FRVBF_INSN_STB, SEM_FN_NAME (frvbf,stb) }, + { FRVBF_INSN_STH, SEM_FN_NAME (frvbf,sth) }, + { FRVBF_INSN_ST, SEM_FN_NAME (frvbf,st) }, + { FRVBF_INSN_STBF, SEM_FN_NAME (frvbf,stbf) }, + { FRVBF_INSN_STHF, SEM_FN_NAME (frvbf,sthf) }, + { FRVBF_INSN_STF, SEM_FN_NAME (frvbf,stf) }, + { FRVBF_INSN_STC, SEM_FN_NAME (frvbf,stc) }, + { FRVBF_INSN_RSTB, SEM_FN_NAME (frvbf,rstb) }, + { FRVBF_INSN_RSTH, SEM_FN_NAME (frvbf,rsth) }, + { FRVBF_INSN_RST, SEM_FN_NAME (frvbf,rst) }, + { FRVBF_INSN_RSTBF, SEM_FN_NAME (frvbf,rstbf) }, + { FRVBF_INSN_RSTHF, SEM_FN_NAME (frvbf,rsthf) }, + { FRVBF_INSN_RSTF, SEM_FN_NAME (frvbf,rstf) }, + { FRVBF_INSN_STD, SEM_FN_NAME (frvbf,std) }, + { FRVBF_INSN_STDF, SEM_FN_NAME (frvbf,stdf) }, + { FRVBF_INSN_STDC, SEM_FN_NAME (frvbf,stdc) }, + { FRVBF_INSN_RSTD, SEM_FN_NAME (frvbf,rstd) }, + { FRVBF_INSN_RSTDF, SEM_FN_NAME (frvbf,rstdf) }, + { FRVBF_INSN_STQ, SEM_FN_NAME (frvbf,stq) }, + { FRVBF_INSN_STQF, SEM_FN_NAME (frvbf,stqf) }, + { FRVBF_INSN_STQC, SEM_FN_NAME (frvbf,stqc) }, + { FRVBF_INSN_RSTQ, SEM_FN_NAME (frvbf,rstq) }, + { FRVBF_INSN_RSTQF, SEM_FN_NAME (frvbf,rstqf) }, + { FRVBF_INSN_STBU, SEM_FN_NAME (frvbf,stbu) }, + { FRVBF_INSN_STHU, SEM_FN_NAME (frvbf,sthu) }, + { FRVBF_INSN_STU, SEM_FN_NAME (frvbf,stu) }, + { FRVBF_INSN_STBFU, SEM_FN_NAME (frvbf,stbfu) }, + { FRVBF_INSN_STHFU, SEM_FN_NAME (frvbf,sthfu) }, + { FRVBF_INSN_STFU, SEM_FN_NAME (frvbf,stfu) }, + { FRVBF_INSN_STCU, SEM_FN_NAME (frvbf,stcu) }, + { FRVBF_INSN_STDU, SEM_FN_NAME (frvbf,stdu) }, + { FRVBF_INSN_STDFU, SEM_FN_NAME (frvbf,stdfu) }, + { FRVBF_INSN_STDCU, SEM_FN_NAME (frvbf,stdcu) }, + { FRVBF_INSN_STQU, SEM_FN_NAME (frvbf,stqu) }, + { FRVBF_INSN_STQFU, SEM_FN_NAME (frvbf,stqfu) }, + { FRVBF_INSN_STQCU, SEM_FN_NAME (frvbf,stqcu) }, + { FRVBF_INSN_CLDSB, SEM_FN_NAME (frvbf,cldsb) }, + { FRVBF_INSN_CLDUB, SEM_FN_NAME (frvbf,cldub) }, + { FRVBF_INSN_CLDSH, SEM_FN_NAME (frvbf,cldsh) }, + { FRVBF_INSN_CLDUH, SEM_FN_NAME (frvbf,clduh) }, + { FRVBF_INSN_CLD, SEM_FN_NAME (frvbf,cld) }, + { FRVBF_INSN_CLDBF, SEM_FN_NAME (frvbf,cldbf) }, + { FRVBF_INSN_CLDHF, SEM_FN_NAME (frvbf,cldhf) }, + { FRVBF_INSN_CLDF, SEM_FN_NAME (frvbf,cldf) }, + { FRVBF_INSN_CLDD, SEM_FN_NAME (frvbf,cldd) }, + { FRVBF_INSN_CLDDF, SEM_FN_NAME (frvbf,clddf) }, + { FRVBF_INSN_CLDQ, SEM_FN_NAME (frvbf,cldq) }, + { FRVBF_INSN_CLDSBU, SEM_FN_NAME (frvbf,cldsbu) }, + { FRVBF_INSN_CLDUBU, SEM_FN_NAME (frvbf,cldubu) }, + { FRVBF_INSN_CLDSHU, SEM_FN_NAME (frvbf,cldshu) }, + { FRVBF_INSN_CLDUHU, SEM_FN_NAME (frvbf,clduhu) }, + { FRVBF_INSN_CLDU, SEM_FN_NAME (frvbf,cldu) }, + { FRVBF_INSN_CLDBFU, SEM_FN_NAME (frvbf,cldbfu) }, + { FRVBF_INSN_CLDHFU, SEM_FN_NAME (frvbf,cldhfu) }, + { FRVBF_INSN_CLDFU, SEM_FN_NAME (frvbf,cldfu) }, + { FRVBF_INSN_CLDDU, SEM_FN_NAME (frvbf,clddu) }, + { FRVBF_INSN_CLDDFU, SEM_FN_NAME (frvbf,clddfu) }, + { FRVBF_INSN_CLDQU, SEM_FN_NAME (frvbf,cldqu) }, + { FRVBF_INSN_CSTB, SEM_FN_NAME (frvbf,cstb) }, + { FRVBF_INSN_CSTH, SEM_FN_NAME (frvbf,csth) }, + { FRVBF_INSN_CST, SEM_FN_NAME (frvbf,cst) }, + { FRVBF_INSN_CSTBF, SEM_FN_NAME (frvbf,cstbf) }, + { FRVBF_INSN_CSTHF, SEM_FN_NAME (frvbf,csthf) }, + { FRVBF_INSN_CSTF, SEM_FN_NAME (frvbf,cstf) }, + { FRVBF_INSN_CSTD, SEM_FN_NAME (frvbf,cstd) }, + { FRVBF_INSN_CSTDF, SEM_FN_NAME (frvbf,cstdf) }, + { FRVBF_INSN_CSTQ, SEM_FN_NAME (frvbf,cstq) }, + { FRVBF_INSN_CSTBU, SEM_FN_NAME (frvbf,cstbu) }, + { FRVBF_INSN_CSTHU, SEM_FN_NAME (frvbf,csthu) }, + { FRVBF_INSN_CSTU, SEM_FN_NAME (frvbf,cstu) }, + { FRVBF_INSN_CSTBFU, SEM_FN_NAME (frvbf,cstbfu) }, + { FRVBF_INSN_CSTHFU, SEM_FN_NAME (frvbf,csthfu) }, + { FRVBF_INSN_CSTFU, SEM_FN_NAME (frvbf,cstfu) }, + { FRVBF_INSN_CSTDU, SEM_FN_NAME (frvbf,cstdu) }, + { FRVBF_INSN_CSTDFU, SEM_FN_NAME (frvbf,cstdfu) }, + { FRVBF_INSN_STBI, SEM_FN_NAME (frvbf,stbi) }, + { FRVBF_INSN_STHI, SEM_FN_NAME (frvbf,sthi) }, + { FRVBF_INSN_STI, SEM_FN_NAME (frvbf,sti) }, + { FRVBF_INSN_STBFI, SEM_FN_NAME (frvbf,stbfi) }, + { FRVBF_INSN_STHFI, SEM_FN_NAME (frvbf,sthfi) }, + { FRVBF_INSN_STFI, SEM_FN_NAME (frvbf,stfi) }, + { FRVBF_INSN_STDI, SEM_FN_NAME (frvbf,stdi) }, + { FRVBF_INSN_STDFI, SEM_FN_NAME (frvbf,stdfi) }, + { FRVBF_INSN_STQI, SEM_FN_NAME (frvbf,stqi) }, + { FRVBF_INSN_STQFI, SEM_FN_NAME (frvbf,stqfi) }, + { FRVBF_INSN_SWAP, SEM_FN_NAME (frvbf,swap) }, + { FRVBF_INSN_SWAPI, SEM_FN_NAME (frvbf,swapi) }, + { FRVBF_INSN_CSWAP, SEM_FN_NAME (frvbf,cswap) }, + { FRVBF_INSN_MOVGF, SEM_FN_NAME (frvbf,movgf) }, + { FRVBF_INSN_MOVFG, SEM_FN_NAME (frvbf,movfg) }, + { FRVBF_INSN_MOVGFD, SEM_FN_NAME (frvbf,movgfd) }, + { FRVBF_INSN_MOVFGD, SEM_FN_NAME (frvbf,movfgd) }, + { FRVBF_INSN_MOVGFQ, SEM_FN_NAME (frvbf,movgfq) }, + { FRVBF_INSN_MOVFGQ, SEM_FN_NAME (frvbf,movfgq) }, + { FRVBF_INSN_CMOVGF, SEM_FN_NAME (frvbf,cmovgf) }, + { FRVBF_INSN_CMOVFG, SEM_FN_NAME (frvbf,cmovfg) }, + { FRVBF_INSN_CMOVGFD, SEM_FN_NAME (frvbf,cmovgfd) }, + { FRVBF_INSN_CMOVFGD, SEM_FN_NAME (frvbf,cmovfgd) }, + { FRVBF_INSN_MOVGS, SEM_FN_NAME (frvbf,movgs) }, + { FRVBF_INSN_MOVSG, SEM_FN_NAME (frvbf,movsg) }, + { FRVBF_INSN_BRA, SEM_FN_NAME (frvbf,bra) }, + { FRVBF_INSN_BNO, SEM_FN_NAME (frvbf,bno) }, + { FRVBF_INSN_BEQ, SEM_FN_NAME (frvbf,beq) }, + { FRVBF_INSN_BNE, SEM_FN_NAME (frvbf,bne) }, + { FRVBF_INSN_BLE, SEM_FN_NAME (frvbf,ble) }, + { FRVBF_INSN_BGT, SEM_FN_NAME (frvbf,bgt) }, + { FRVBF_INSN_BLT, SEM_FN_NAME (frvbf,blt) }, + { FRVBF_INSN_BGE, SEM_FN_NAME (frvbf,bge) }, + { FRVBF_INSN_BLS, SEM_FN_NAME (frvbf,bls) }, + { FRVBF_INSN_BHI, SEM_FN_NAME (frvbf,bhi) }, + { FRVBF_INSN_BC, SEM_FN_NAME (frvbf,bc) }, + { FRVBF_INSN_BNC, SEM_FN_NAME (frvbf,bnc) }, + { FRVBF_INSN_BN, SEM_FN_NAME (frvbf,bn) }, + { FRVBF_INSN_BP, SEM_FN_NAME (frvbf,bp) }, + { FRVBF_INSN_BV, SEM_FN_NAME (frvbf,bv) }, + { FRVBF_INSN_BNV, SEM_FN_NAME (frvbf,bnv) }, + { FRVBF_INSN_FBRA, SEM_FN_NAME (frvbf,fbra) }, + { FRVBF_INSN_FBNO, SEM_FN_NAME (frvbf,fbno) }, + { FRVBF_INSN_FBNE, SEM_FN_NAME (frvbf,fbne) }, + { FRVBF_INSN_FBEQ, SEM_FN_NAME (frvbf,fbeq) }, + { FRVBF_INSN_FBLG, SEM_FN_NAME (frvbf,fblg) }, + { FRVBF_INSN_FBUE, SEM_FN_NAME (frvbf,fbue) }, + { FRVBF_INSN_FBUL, SEM_FN_NAME (frvbf,fbul) }, + { FRVBF_INSN_FBGE, SEM_FN_NAME (frvbf,fbge) }, + { FRVBF_INSN_FBLT, SEM_FN_NAME (frvbf,fblt) }, + { FRVBF_INSN_FBUGE, SEM_FN_NAME (frvbf,fbuge) }, + { FRVBF_INSN_FBUG, SEM_FN_NAME (frvbf,fbug) }, + { FRVBF_INSN_FBLE, SEM_FN_NAME (frvbf,fble) }, + { FRVBF_INSN_FBGT, SEM_FN_NAME (frvbf,fbgt) }, + { FRVBF_INSN_FBULE, SEM_FN_NAME (frvbf,fbule) }, + { FRVBF_INSN_FBU, SEM_FN_NAME (frvbf,fbu) }, + { FRVBF_INSN_FBO, SEM_FN_NAME (frvbf,fbo) }, + { FRVBF_INSN_BCTRLR, SEM_FN_NAME (frvbf,bctrlr) }, + { FRVBF_INSN_BRALR, SEM_FN_NAME (frvbf,bralr) }, + { FRVBF_INSN_BNOLR, SEM_FN_NAME (frvbf,bnolr) }, + { FRVBF_INSN_BEQLR, SEM_FN_NAME (frvbf,beqlr) }, + { FRVBF_INSN_BNELR, SEM_FN_NAME (frvbf,bnelr) }, + { FRVBF_INSN_BLELR, SEM_FN_NAME (frvbf,blelr) }, + { FRVBF_INSN_BGTLR, SEM_FN_NAME (frvbf,bgtlr) }, + { FRVBF_INSN_BLTLR, SEM_FN_NAME (frvbf,bltlr) }, + { FRVBF_INSN_BGELR, SEM_FN_NAME (frvbf,bgelr) }, + { FRVBF_INSN_BLSLR, SEM_FN_NAME (frvbf,blslr) }, + { FRVBF_INSN_BHILR, SEM_FN_NAME (frvbf,bhilr) }, + { FRVBF_INSN_BCLR, SEM_FN_NAME (frvbf,bclr) }, + { FRVBF_INSN_BNCLR, SEM_FN_NAME (frvbf,bnclr) }, + { FRVBF_INSN_BNLR, SEM_FN_NAME (frvbf,bnlr) }, + { FRVBF_INSN_BPLR, SEM_FN_NAME (frvbf,bplr) }, + { FRVBF_INSN_BVLR, SEM_FN_NAME (frvbf,bvlr) }, + { FRVBF_INSN_BNVLR, SEM_FN_NAME (frvbf,bnvlr) }, + { FRVBF_INSN_FBRALR, SEM_FN_NAME (frvbf,fbralr) }, + { FRVBF_INSN_FBNOLR, SEM_FN_NAME (frvbf,fbnolr) }, + { FRVBF_INSN_FBEQLR, SEM_FN_NAME (frvbf,fbeqlr) }, + { FRVBF_INSN_FBNELR, SEM_FN_NAME (frvbf,fbnelr) }, + { FRVBF_INSN_FBLGLR, SEM_FN_NAME (frvbf,fblglr) }, + { FRVBF_INSN_FBUELR, SEM_FN_NAME (frvbf,fbuelr) }, + { FRVBF_INSN_FBULLR, SEM_FN_NAME (frvbf,fbullr) }, + { FRVBF_INSN_FBGELR, SEM_FN_NAME (frvbf,fbgelr) }, + { FRVBF_INSN_FBLTLR, SEM_FN_NAME (frvbf,fbltlr) }, + { FRVBF_INSN_FBUGELR, SEM_FN_NAME (frvbf,fbugelr) }, + { FRVBF_INSN_FBUGLR, SEM_FN_NAME (frvbf,fbuglr) }, + { FRVBF_INSN_FBLELR, SEM_FN_NAME (frvbf,fblelr) }, + { FRVBF_INSN_FBGTLR, SEM_FN_NAME (frvbf,fbgtlr) }, + { FRVBF_INSN_FBULELR, SEM_FN_NAME (frvbf,fbulelr) }, + { FRVBF_INSN_FBULR, SEM_FN_NAME (frvbf,fbulr) }, + { FRVBF_INSN_FBOLR, SEM_FN_NAME (frvbf,fbolr) }, + { FRVBF_INSN_BCRALR, SEM_FN_NAME (frvbf,bcralr) }, + { FRVBF_INSN_BCNOLR, SEM_FN_NAME (frvbf,bcnolr) }, + { FRVBF_INSN_BCEQLR, SEM_FN_NAME (frvbf,bceqlr) }, + { FRVBF_INSN_BCNELR, SEM_FN_NAME (frvbf,bcnelr) }, + { FRVBF_INSN_BCLELR, SEM_FN_NAME (frvbf,bclelr) }, + { FRVBF_INSN_BCGTLR, SEM_FN_NAME (frvbf,bcgtlr) }, + { FRVBF_INSN_BCLTLR, SEM_FN_NAME (frvbf,bcltlr) }, + { FRVBF_INSN_BCGELR, SEM_FN_NAME (frvbf,bcgelr) }, + { FRVBF_INSN_BCLSLR, SEM_FN_NAME (frvbf,bclslr) }, + { FRVBF_INSN_BCHILR, SEM_FN_NAME (frvbf,bchilr) }, + { FRVBF_INSN_BCCLR, SEM_FN_NAME (frvbf,bcclr) }, + { FRVBF_INSN_BCNCLR, SEM_FN_NAME (frvbf,bcnclr) }, + { FRVBF_INSN_BCNLR, SEM_FN_NAME (frvbf,bcnlr) }, + { FRVBF_INSN_BCPLR, SEM_FN_NAME (frvbf,bcplr) }, + { FRVBF_INSN_BCVLR, SEM_FN_NAME (frvbf,bcvlr) }, + { FRVBF_INSN_BCNVLR, SEM_FN_NAME (frvbf,bcnvlr) }, + { FRVBF_INSN_FCBRALR, SEM_FN_NAME (frvbf,fcbralr) }, + { FRVBF_INSN_FCBNOLR, SEM_FN_NAME (frvbf,fcbnolr) }, + { FRVBF_INSN_FCBEQLR, SEM_FN_NAME (frvbf,fcbeqlr) }, + { FRVBF_INSN_FCBNELR, SEM_FN_NAME (frvbf,fcbnelr) }, + { FRVBF_INSN_FCBLGLR, SEM_FN_NAME (frvbf,fcblglr) }, + { FRVBF_INSN_FCBUELR, SEM_FN_NAME (frvbf,fcbuelr) }, + { FRVBF_INSN_FCBULLR, SEM_FN_NAME (frvbf,fcbullr) }, + { FRVBF_INSN_FCBGELR, SEM_FN_NAME (frvbf,fcbgelr) }, + { FRVBF_INSN_FCBLTLR, SEM_FN_NAME (frvbf,fcbltlr) }, + { FRVBF_INSN_FCBUGELR, SEM_FN_NAME (frvbf,fcbugelr) }, + { FRVBF_INSN_FCBUGLR, SEM_FN_NAME (frvbf,fcbuglr) }, + { FRVBF_INSN_FCBLELR, SEM_FN_NAME (frvbf,fcblelr) }, + { FRVBF_INSN_FCBGTLR, SEM_FN_NAME (frvbf,fcbgtlr) }, + { FRVBF_INSN_FCBULELR, SEM_FN_NAME (frvbf,fcbulelr) }, + { FRVBF_INSN_FCBULR, SEM_FN_NAME (frvbf,fcbulr) }, + { FRVBF_INSN_FCBOLR, SEM_FN_NAME (frvbf,fcbolr) }, + { FRVBF_INSN_JMPL, SEM_FN_NAME (frvbf,jmpl) }, + { FRVBF_INSN_CALLL, SEM_FN_NAME (frvbf,calll) }, + { FRVBF_INSN_JMPIL, SEM_FN_NAME (frvbf,jmpil) }, + { FRVBF_INSN_CALLIL, SEM_FN_NAME (frvbf,callil) }, + { FRVBF_INSN_CALL, SEM_FN_NAME (frvbf,call) }, + { FRVBF_INSN_RETT, SEM_FN_NAME (frvbf,rett) }, + { FRVBF_INSN_REI, SEM_FN_NAME (frvbf,rei) }, + { FRVBF_INSN_TRA, SEM_FN_NAME (frvbf,tra) }, + { FRVBF_INSN_TNO, SEM_FN_NAME (frvbf,tno) }, + { FRVBF_INSN_TEQ, SEM_FN_NAME (frvbf,teq) }, + { FRVBF_INSN_TNE, SEM_FN_NAME (frvbf,tne) }, + { FRVBF_INSN_TLE, SEM_FN_NAME (frvbf,tle) }, + { FRVBF_INSN_TGT, SEM_FN_NAME (frvbf,tgt) }, + { FRVBF_INSN_TLT, SEM_FN_NAME (frvbf,tlt) }, + { FRVBF_INSN_TGE, SEM_FN_NAME (frvbf,tge) }, + { FRVBF_INSN_TLS, SEM_FN_NAME (frvbf,tls) }, + { FRVBF_INSN_THI, SEM_FN_NAME (frvbf,thi) }, + { FRVBF_INSN_TC, SEM_FN_NAME (frvbf,tc) }, + { FRVBF_INSN_TNC, SEM_FN_NAME (frvbf,tnc) }, + { FRVBF_INSN_TN, SEM_FN_NAME (frvbf,tn) }, + { FRVBF_INSN_TP, SEM_FN_NAME (frvbf,tp) }, + { FRVBF_INSN_TV, SEM_FN_NAME (frvbf,tv) }, + { FRVBF_INSN_TNV, SEM_FN_NAME (frvbf,tnv) }, + { FRVBF_INSN_FTRA, SEM_FN_NAME (frvbf,ftra) }, + { FRVBF_INSN_FTNO, SEM_FN_NAME (frvbf,ftno) }, + { FRVBF_INSN_FTNE, SEM_FN_NAME (frvbf,ftne) }, + { FRVBF_INSN_FTEQ, SEM_FN_NAME (frvbf,fteq) }, + { FRVBF_INSN_FTLG, SEM_FN_NAME (frvbf,ftlg) }, + { FRVBF_INSN_FTUE, SEM_FN_NAME (frvbf,ftue) }, + { FRVBF_INSN_FTUL, SEM_FN_NAME (frvbf,ftul) }, + { FRVBF_INSN_FTGE, SEM_FN_NAME (frvbf,ftge) }, + { FRVBF_INSN_FTLT, SEM_FN_NAME (frvbf,ftlt) }, + { FRVBF_INSN_FTUGE, SEM_FN_NAME (frvbf,ftuge) }, + { FRVBF_INSN_FTUG, SEM_FN_NAME (frvbf,ftug) }, + { FRVBF_INSN_FTLE, SEM_FN_NAME (frvbf,ftle) }, + { FRVBF_INSN_FTGT, SEM_FN_NAME (frvbf,ftgt) }, + { FRVBF_INSN_FTULE, SEM_FN_NAME (frvbf,ftule) }, + { FRVBF_INSN_FTU, SEM_FN_NAME (frvbf,ftu) }, + { FRVBF_INSN_FTO, SEM_FN_NAME (frvbf,fto) }, + { FRVBF_INSN_TIRA, SEM_FN_NAME (frvbf,tira) }, + { FRVBF_INSN_TINO, SEM_FN_NAME (frvbf,tino) }, + { FRVBF_INSN_TIEQ, SEM_FN_NAME (frvbf,tieq) }, + { FRVBF_INSN_TINE, SEM_FN_NAME (frvbf,tine) }, + { FRVBF_INSN_TILE, SEM_FN_NAME (frvbf,tile) }, + { FRVBF_INSN_TIGT, SEM_FN_NAME (frvbf,tigt) }, + { FRVBF_INSN_TILT, SEM_FN_NAME (frvbf,tilt) }, + { FRVBF_INSN_TIGE, SEM_FN_NAME (frvbf,tige) }, + { FRVBF_INSN_TILS, SEM_FN_NAME (frvbf,tils) }, + { FRVBF_INSN_TIHI, SEM_FN_NAME (frvbf,tihi) }, + { FRVBF_INSN_TIC, SEM_FN_NAME (frvbf,tic) }, + { FRVBF_INSN_TINC, SEM_FN_NAME (frvbf,tinc) }, + { FRVBF_INSN_TIN, SEM_FN_NAME (frvbf,tin) }, + { FRVBF_INSN_TIP, SEM_FN_NAME (frvbf,tip) }, + { FRVBF_INSN_TIV, SEM_FN_NAME (frvbf,tiv) }, + { FRVBF_INSN_TINV, SEM_FN_NAME (frvbf,tinv) }, + { FRVBF_INSN_FTIRA, SEM_FN_NAME (frvbf,ftira) }, + { FRVBF_INSN_FTINO, SEM_FN_NAME (frvbf,ftino) }, + { FRVBF_INSN_FTINE, SEM_FN_NAME (frvbf,ftine) }, + { FRVBF_INSN_FTIEQ, SEM_FN_NAME (frvbf,ftieq) }, + { FRVBF_INSN_FTILG, SEM_FN_NAME (frvbf,ftilg) }, + { FRVBF_INSN_FTIUE, SEM_FN_NAME (frvbf,ftiue) }, + { FRVBF_INSN_FTIUL, SEM_FN_NAME (frvbf,ftiul) }, + { FRVBF_INSN_FTIGE, SEM_FN_NAME (frvbf,ftige) }, + { FRVBF_INSN_FTILT, SEM_FN_NAME (frvbf,ftilt) }, + { FRVBF_INSN_FTIUGE, SEM_FN_NAME (frvbf,ftiuge) }, + { FRVBF_INSN_FTIUG, SEM_FN_NAME (frvbf,ftiug) }, + { FRVBF_INSN_FTILE, SEM_FN_NAME (frvbf,ftile) }, + { FRVBF_INSN_FTIGT, SEM_FN_NAME (frvbf,ftigt) }, + { FRVBF_INSN_FTIULE, SEM_FN_NAME (frvbf,ftiule) }, + { FRVBF_INSN_FTIU, SEM_FN_NAME (frvbf,ftiu) }, + { FRVBF_INSN_FTIO, SEM_FN_NAME (frvbf,ftio) }, + { FRVBF_INSN_BREAK, SEM_FN_NAME (frvbf,break) }, + { FRVBF_INSN_MTRAP, SEM_FN_NAME (frvbf,mtrap) }, + { FRVBF_INSN_ANDCR, SEM_FN_NAME (frvbf,andcr) }, + { FRVBF_INSN_ORCR, SEM_FN_NAME (frvbf,orcr) }, + { FRVBF_INSN_XORCR, SEM_FN_NAME (frvbf,xorcr) }, + { FRVBF_INSN_NANDCR, SEM_FN_NAME (frvbf,nandcr) }, + { FRVBF_INSN_NORCR, SEM_FN_NAME (frvbf,norcr) }, + { FRVBF_INSN_ANDNCR, SEM_FN_NAME (frvbf,andncr) }, + { FRVBF_INSN_ORNCR, SEM_FN_NAME (frvbf,orncr) }, + { FRVBF_INSN_NANDNCR, SEM_FN_NAME (frvbf,nandncr) }, + { FRVBF_INSN_NORNCR, SEM_FN_NAME (frvbf,norncr) }, + { FRVBF_INSN_NOTCR, SEM_FN_NAME (frvbf,notcr) }, + { FRVBF_INSN_CKRA, SEM_FN_NAME (frvbf,ckra) }, + { FRVBF_INSN_CKNO, SEM_FN_NAME (frvbf,ckno) }, + { FRVBF_INSN_CKEQ, SEM_FN_NAME (frvbf,ckeq) }, + { FRVBF_INSN_CKNE, SEM_FN_NAME (frvbf,ckne) }, + { FRVBF_INSN_CKLE, SEM_FN_NAME (frvbf,ckle) }, + { FRVBF_INSN_CKGT, SEM_FN_NAME (frvbf,ckgt) }, + { FRVBF_INSN_CKLT, SEM_FN_NAME (frvbf,cklt) }, + { FRVBF_INSN_CKGE, SEM_FN_NAME (frvbf,ckge) }, + { FRVBF_INSN_CKLS, SEM_FN_NAME (frvbf,ckls) }, + { FRVBF_INSN_CKHI, SEM_FN_NAME (frvbf,ckhi) }, + { FRVBF_INSN_CKC, SEM_FN_NAME (frvbf,ckc) }, + { FRVBF_INSN_CKNC, SEM_FN_NAME (frvbf,cknc) }, + { FRVBF_INSN_CKN, SEM_FN_NAME (frvbf,ckn) }, + { FRVBF_INSN_CKP, SEM_FN_NAME (frvbf,ckp) }, + { FRVBF_INSN_CKV, SEM_FN_NAME (frvbf,ckv) }, + { FRVBF_INSN_CKNV, SEM_FN_NAME (frvbf,cknv) }, + { FRVBF_INSN_FCKRA, SEM_FN_NAME (frvbf,fckra) }, + { FRVBF_INSN_FCKNO, SEM_FN_NAME (frvbf,fckno) }, + { FRVBF_INSN_FCKNE, SEM_FN_NAME (frvbf,fckne) }, + { FRVBF_INSN_FCKEQ, SEM_FN_NAME (frvbf,fckeq) }, + { FRVBF_INSN_FCKLG, SEM_FN_NAME (frvbf,fcklg) }, + { FRVBF_INSN_FCKUE, SEM_FN_NAME (frvbf,fckue) }, + { FRVBF_INSN_FCKUL, SEM_FN_NAME (frvbf,fckul) }, + { FRVBF_INSN_FCKGE, SEM_FN_NAME (frvbf,fckge) }, + { FRVBF_INSN_FCKLT, SEM_FN_NAME (frvbf,fcklt) }, + { FRVBF_INSN_FCKUGE, SEM_FN_NAME (frvbf,fckuge) }, + { FRVBF_INSN_FCKUG, SEM_FN_NAME (frvbf,fckug) }, + { FRVBF_INSN_FCKLE, SEM_FN_NAME (frvbf,fckle) }, + { FRVBF_INSN_FCKGT, SEM_FN_NAME (frvbf,fckgt) }, + { FRVBF_INSN_FCKULE, SEM_FN_NAME (frvbf,fckule) }, + { FRVBF_INSN_FCKU, SEM_FN_NAME (frvbf,fcku) }, + { FRVBF_INSN_FCKO, SEM_FN_NAME (frvbf,fcko) }, + { FRVBF_INSN_CCKRA, SEM_FN_NAME (frvbf,cckra) }, + { FRVBF_INSN_CCKNO, SEM_FN_NAME (frvbf,cckno) }, + { FRVBF_INSN_CCKEQ, SEM_FN_NAME (frvbf,cckeq) }, + { FRVBF_INSN_CCKNE, SEM_FN_NAME (frvbf,cckne) }, + { FRVBF_INSN_CCKLE, SEM_FN_NAME (frvbf,cckle) }, + { FRVBF_INSN_CCKGT, SEM_FN_NAME (frvbf,cckgt) }, + { FRVBF_INSN_CCKLT, SEM_FN_NAME (frvbf,ccklt) }, + { FRVBF_INSN_CCKGE, SEM_FN_NAME (frvbf,cckge) }, + { FRVBF_INSN_CCKLS, SEM_FN_NAME (frvbf,cckls) }, + { FRVBF_INSN_CCKHI, SEM_FN_NAME (frvbf,cckhi) }, + { FRVBF_INSN_CCKC, SEM_FN_NAME (frvbf,cckc) }, + { FRVBF_INSN_CCKNC, SEM_FN_NAME (frvbf,ccknc) }, + { FRVBF_INSN_CCKN, SEM_FN_NAME (frvbf,cckn) }, + { FRVBF_INSN_CCKP, SEM_FN_NAME (frvbf,cckp) }, + { FRVBF_INSN_CCKV, SEM_FN_NAME (frvbf,cckv) }, + { FRVBF_INSN_CCKNV, SEM_FN_NAME (frvbf,ccknv) }, + { FRVBF_INSN_CFCKRA, SEM_FN_NAME (frvbf,cfckra) }, + { FRVBF_INSN_CFCKNO, SEM_FN_NAME (frvbf,cfckno) }, + { FRVBF_INSN_CFCKNE, SEM_FN_NAME (frvbf,cfckne) }, + { FRVBF_INSN_CFCKEQ, SEM_FN_NAME (frvbf,cfckeq) }, + { FRVBF_INSN_CFCKLG, SEM_FN_NAME (frvbf,cfcklg) }, + { FRVBF_INSN_CFCKUE, SEM_FN_NAME (frvbf,cfckue) }, + { FRVBF_INSN_CFCKUL, SEM_FN_NAME (frvbf,cfckul) }, + { FRVBF_INSN_CFCKGE, SEM_FN_NAME (frvbf,cfckge) }, + { FRVBF_INSN_CFCKLT, SEM_FN_NAME (frvbf,cfcklt) }, + { FRVBF_INSN_CFCKUGE, SEM_FN_NAME (frvbf,cfckuge) }, + { FRVBF_INSN_CFCKUG, SEM_FN_NAME (frvbf,cfckug) }, + { FRVBF_INSN_CFCKLE, SEM_FN_NAME (frvbf,cfckle) }, + { FRVBF_INSN_CFCKGT, SEM_FN_NAME (frvbf,cfckgt) }, + { FRVBF_INSN_CFCKULE, SEM_FN_NAME (frvbf,cfckule) }, + { FRVBF_INSN_CFCKU, SEM_FN_NAME (frvbf,cfcku) }, + { FRVBF_INSN_CFCKO, SEM_FN_NAME (frvbf,cfcko) }, + { FRVBF_INSN_CJMPL, SEM_FN_NAME (frvbf,cjmpl) }, + { FRVBF_INSN_CCALLL, SEM_FN_NAME (frvbf,ccalll) }, + { FRVBF_INSN_ICI, SEM_FN_NAME (frvbf,ici) }, + { FRVBF_INSN_DCI, SEM_FN_NAME (frvbf,dci) }, + { FRVBF_INSN_ICEI, SEM_FN_NAME (frvbf,icei) }, + { FRVBF_INSN_DCEI, SEM_FN_NAME (frvbf,dcei) }, + { FRVBF_INSN_DCF, SEM_FN_NAME (frvbf,dcf) }, + { FRVBF_INSN_DCEF, SEM_FN_NAME (frvbf,dcef) }, + { FRVBF_INSN_WITLB, SEM_FN_NAME (frvbf,witlb) }, + { FRVBF_INSN_WDTLB, SEM_FN_NAME (frvbf,wdtlb) }, + { FRVBF_INSN_ITLBI, SEM_FN_NAME (frvbf,itlbi) }, + { FRVBF_INSN_DTLBI, SEM_FN_NAME (frvbf,dtlbi) }, + { FRVBF_INSN_ICPL, SEM_FN_NAME (frvbf,icpl) }, + { FRVBF_INSN_DCPL, SEM_FN_NAME (frvbf,dcpl) }, + { FRVBF_INSN_ICUL, SEM_FN_NAME (frvbf,icul) }, + { FRVBF_INSN_DCUL, SEM_FN_NAME (frvbf,dcul) }, + { FRVBF_INSN_BAR, SEM_FN_NAME (frvbf,bar) }, + { FRVBF_INSN_MEMBAR, SEM_FN_NAME (frvbf,membar) }, + { FRVBF_INSN_COP1, SEM_FN_NAME (frvbf,cop1) }, + { FRVBF_INSN_COP2, SEM_FN_NAME (frvbf,cop2) }, + { FRVBF_INSN_CLRGR, SEM_FN_NAME (frvbf,clrgr) }, + { FRVBF_INSN_CLRFR, SEM_FN_NAME (frvbf,clrfr) }, + { FRVBF_INSN_CLRGA, SEM_FN_NAME (frvbf,clrga) }, + { FRVBF_INSN_CLRFA, SEM_FN_NAME (frvbf,clrfa) }, + { FRVBF_INSN_COMMITGR, SEM_FN_NAME (frvbf,commitgr) }, + { FRVBF_INSN_COMMITFR, SEM_FN_NAME (frvbf,commitfr) }, + { FRVBF_INSN_COMMITGA, SEM_FN_NAME (frvbf,commitga) }, + { FRVBF_INSN_COMMITFA, SEM_FN_NAME (frvbf,commitfa) }, + { FRVBF_INSN_FITOS, SEM_FN_NAME (frvbf,fitos) }, + { FRVBF_INSN_FSTOI, SEM_FN_NAME (frvbf,fstoi) }, + { FRVBF_INSN_FITOD, SEM_FN_NAME (frvbf,fitod) }, + { FRVBF_INSN_FDTOI, SEM_FN_NAME (frvbf,fdtoi) }, + { FRVBF_INSN_FDITOS, SEM_FN_NAME (frvbf,fditos) }, + { FRVBF_INSN_FDSTOI, SEM_FN_NAME (frvbf,fdstoi) }, + { FRVBF_INSN_NFDITOS, SEM_FN_NAME (frvbf,nfditos) }, + { FRVBF_INSN_NFDSTOI, SEM_FN_NAME (frvbf,nfdstoi) }, + { FRVBF_INSN_CFITOS, SEM_FN_NAME (frvbf,cfitos) }, + { FRVBF_INSN_CFSTOI, SEM_FN_NAME (frvbf,cfstoi) }, + { FRVBF_INSN_NFITOS, SEM_FN_NAME (frvbf,nfitos) }, + { FRVBF_INSN_NFSTOI, SEM_FN_NAME (frvbf,nfstoi) }, + { FRVBF_INSN_FMOVS, SEM_FN_NAME (frvbf,fmovs) }, + { FRVBF_INSN_FMOVD, SEM_FN_NAME (frvbf,fmovd) }, + { FRVBF_INSN_FDMOVS, SEM_FN_NAME (frvbf,fdmovs) }, + { FRVBF_INSN_CFMOVS, SEM_FN_NAME (frvbf,cfmovs) }, + { FRVBF_INSN_FNEGS, SEM_FN_NAME (frvbf,fnegs) }, + { FRVBF_INSN_FNEGD, SEM_FN_NAME (frvbf,fnegd) }, + { FRVBF_INSN_FDNEGS, SEM_FN_NAME (frvbf,fdnegs) }, + { FRVBF_INSN_CFNEGS, SEM_FN_NAME (frvbf,cfnegs) }, + { FRVBF_INSN_FABSS, SEM_FN_NAME (frvbf,fabss) }, + { FRVBF_INSN_FABSD, SEM_FN_NAME (frvbf,fabsd) }, + { FRVBF_INSN_FDABSS, SEM_FN_NAME (frvbf,fdabss) }, + { FRVBF_INSN_CFABSS, SEM_FN_NAME (frvbf,cfabss) }, + { FRVBF_INSN_FSQRTS, SEM_FN_NAME (frvbf,fsqrts) }, + { FRVBF_INSN_FDSQRTS, SEM_FN_NAME (frvbf,fdsqrts) }, + { FRVBF_INSN_NFDSQRTS, SEM_FN_NAME (frvbf,nfdsqrts) }, + { FRVBF_INSN_FSQRTD, SEM_FN_NAME (frvbf,fsqrtd) }, + { FRVBF_INSN_CFSQRTS, SEM_FN_NAME (frvbf,cfsqrts) }, + { FRVBF_INSN_NFSQRTS, SEM_FN_NAME (frvbf,nfsqrts) }, + { FRVBF_INSN_FADDS, SEM_FN_NAME (frvbf,fadds) }, + { FRVBF_INSN_FSUBS, SEM_FN_NAME (frvbf,fsubs) }, + { FRVBF_INSN_FMULS, SEM_FN_NAME (frvbf,fmuls) }, + { FRVBF_INSN_FDIVS, SEM_FN_NAME (frvbf,fdivs) }, + { FRVBF_INSN_FADDD, SEM_FN_NAME (frvbf,faddd) }, + { FRVBF_INSN_FSUBD, SEM_FN_NAME (frvbf,fsubd) }, + { FRVBF_INSN_FMULD, SEM_FN_NAME (frvbf,fmuld) }, + { FRVBF_INSN_FDIVD, SEM_FN_NAME (frvbf,fdivd) }, + { FRVBF_INSN_CFADDS, SEM_FN_NAME (frvbf,cfadds) }, + { FRVBF_INSN_CFSUBS, SEM_FN_NAME (frvbf,cfsubs) }, + { FRVBF_INSN_CFMULS, SEM_FN_NAME (frvbf,cfmuls) }, + { FRVBF_INSN_CFDIVS, SEM_FN_NAME (frvbf,cfdivs) }, + { FRVBF_INSN_NFADDS, SEM_FN_NAME (frvbf,nfadds) }, + { FRVBF_INSN_NFSUBS, SEM_FN_NAME (frvbf,nfsubs) }, + { FRVBF_INSN_NFMULS, SEM_FN_NAME (frvbf,nfmuls) }, + { FRVBF_INSN_NFDIVS, SEM_FN_NAME (frvbf,nfdivs) }, + { FRVBF_INSN_FCMPS, SEM_FN_NAME (frvbf,fcmps) }, + { FRVBF_INSN_FCMPD, SEM_FN_NAME (frvbf,fcmpd) }, + { FRVBF_INSN_CFCMPS, SEM_FN_NAME (frvbf,cfcmps) }, + { FRVBF_INSN_FDCMPS, SEM_FN_NAME (frvbf,fdcmps) }, + { FRVBF_INSN_FMADDS, SEM_FN_NAME (frvbf,fmadds) }, + { FRVBF_INSN_FMSUBS, SEM_FN_NAME (frvbf,fmsubs) }, + { FRVBF_INSN_FMADDD, SEM_FN_NAME (frvbf,fmaddd) }, + { FRVBF_INSN_FMSUBD, SEM_FN_NAME (frvbf,fmsubd) }, + { FRVBF_INSN_FDMADDS, SEM_FN_NAME (frvbf,fdmadds) }, + { FRVBF_INSN_NFDMADDS, SEM_FN_NAME (frvbf,nfdmadds) }, + { FRVBF_INSN_CFMADDS, SEM_FN_NAME (frvbf,cfmadds) }, + { FRVBF_INSN_CFMSUBS, SEM_FN_NAME (frvbf,cfmsubs) }, + { FRVBF_INSN_NFMADDS, SEM_FN_NAME (frvbf,nfmadds) }, + { FRVBF_INSN_NFMSUBS, SEM_FN_NAME (frvbf,nfmsubs) }, + { FRVBF_INSN_FMAS, SEM_FN_NAME (frvbf,fmas) }, + { FRVBF_INSN_FMSS, SEM_FN_NAME (frvbf,fmss) }, + { FRVBF_INSN_FDMAS, SEM_FN_NAME (frvbf,fdmas) }, + { FRVBF_INSN_FDMSS, SEM_FN_NAME (frvbf,fdmss) }, + { FRVBF_INSN_NFDMAS, SEM_FN_NAME (frvbf,nfdmas) }, + { FRVBF_INSN_NFDMSS, SEM_FN_NAME (frvbf,nfdmss) }, + { FRVBF_INSN_CFMAS, SEM_FN_NAME (frvbf,cfmas) }, + { FRVBF_INSN_CFMSS, SEM_FN_NAME (frvbf,cfmss) }, + { FRVBF_INSN_FMAD, SEM_FN_NAME (frvbf,fmad) }, + { FRVBF_INSN_FMSD, SEM_FN_NAME (frvbf,fmsd) }, + { FRVBF_INSN_NFMAS, SEM_FN_NAME (frvbf,nfmas) }, + { FRVBF_INSN_NFMSS, SEM_FN_NAME (frvbf,nfmss) }, + { FRVBF_INSN_FDADDS, SEM_FN_NAME (frvbf,fdadds) }, + { FRVBF_INSN_FDSUBS, SEM_FN_NAME (frvbf,fdsubs) }, + { FRVBF_INSN_FDMULS, SEM_FN_NAME (frvbf,fdmuls) }, + { FRVBF_INSN_FDDIVS, SEM_FN_NAME (frvbf,fddivs) }, + { FRVBF_INSN_FDSADS, SEM_FN_NAME (frvbf,fdsads) }, + { FRVBF_INSN_FDMULCS, SEM_FN_NAME (frvbf,fdmulcs) }, + { FRVBF_INSN_NFDMULCS, SEM_FN_NAME (frvbf,nfdmulcs) }, + { FRVBF_INSN_NFDADDS, SEM_FN_NAME (frvbf,nfdadds) }, + { FRVBF_INSN_NFDSUBS, SEM_FN_NAME (frvbf,nfdsubs) }, + { FRVBF_INSN_NFDMULS, SEM_FN_NAME (frvbf,nfdmuls) }, + { FRVBF_INSN_NFDDIVS, SEM_FN_NAME (frvbf,nfddivs) }, + { FRVBF_INSN_NFDSADS, SEM_FN_NAME (frvbf,nfdsads) }, + { FRVBF_INSN_NFDCMPS, SEM_FN_NAME (frvbf,nfdcmps) }, + { FRVBF_INSN_MHSETLOS, SEM_FN_NAME (frvbf,mhsetlos) }, + { FRVBF_INSN_MHSETHIS, SEM_FN_NAME (frvbf,mhsethis) }, + { FRVBF_INSN_MHDSETS, SEM_FN_NAME (frvbf,mhdsets) }, + { FRVBF_INSN_MHSETLOH, SEM_FN_NAME (frvbf,mhsetloh) }, + { FRVBF_INSN_MHSETHIH, SEM_FN_NAME (frvbf,mhsethih) }, + { FRVBF_INSN_MHDSETH, SEM_FN_NAME (frvbf,mhdseth) }, + { FRVBF_INSN_MAND, SEM_FN_NAME (frvbf,mand) }, + { FRVBF_INSN_MOR, SEM_FN_NAME (frvbf,mor) }, + { FRVBF_INSN_MXOR, SEM_FN_NAME (frvbf,mxor) }, + { FRVBF_INSN_CMAND, SEM_FN_NAME (frvbf,cmand) }, + { FRVBF_INSN_CMOR, SEM_FN_NAME (frvbf,cmor) }, + { FRVBF_INSN_CMXOR, SEM_FN_NAME (frvbf,cmxor) }, + { FRVBF_INSN_MNOT, SEM_FN_NAME (frvbf,mnot) }, + { FRVBF_INSN_CMNOT, SEM_FN_NAME (frvbf,cmnot) }, + { FRVBF_INSN_MROTLI, SEM_FN_NAME (frvbf,mrotli) }, + { FRVBF_INSN_MROTRI, SEM_FN_NAME (frvbf,mrotri) }, + { FRVBF_INSN_MWCUT, SEM_FN_NAME (frvbf,mwcut) }, + { FRVBF_INSN_MWCUTI, SEM_FN_NAME (frvbf,mwcuti) }, + { FRVBF_INSN_MCUT, SEM_FN_NAME (frvbf,mcut) }, + { FRVBF_INSN_MCUTI, SEM_FN_NAME (frvbf,mcuti) }, + { FRVBF_INSN_MCUTSS, SEM_FN_NAME (frvbf,mcutss) }, + { FRVBF_INSN_MCUTSSI, SEM_FN_NAME (frvbf,mcutssi) }, + { FRVBF_INSN_MDCUTSSI, SEM_FN_NAME (frvbf,mdcutssi) }, + { FRVBF_INSN_MAVEH, SEM_FN_NAME (frvbf,maveh) }, + { FRVBF_INSN_MSLLHI, SEM_FN_NAME (frvbf,msllhi) }, + { FRVBF_INSN_MSRLHI, SEM_FN_NAME (frvbf,msrlhi) }, + { FRVBF_INSN_MSRAHI, SEM_FN_NAME (frvbf,msrahi) }, + { FRVBF_INSN_MDROTLI, SEM_FN_NAME (frvbf,mdrotli) }, + { FRVBF_INSN_MCPLHI, SEM_FN_NAME (frvbf,mcplhi) }, + { FRVBF_INSN_MCPLI, SEM_FN_NAME (frvbf,mcpli) }, + { FRVBF_INSN_MSATHS, SEM_FN_NAME (frvbf,msaths) }, + { FRVBF_INSN_MQSATHS, SEM_FN_NAME (frvbf,mqsaths) }, + { FRVBF_INSN_MSATHU, SEM_FN_NAME (frvbf,msathu) }, + { FRVBF_INSN_MCMPSH, SEM_FN_NAME (frvbf,mcmpsh) }, + { FRVBF_INSN_MCMPUH, SEM_FN_NAME (frvbf,mcmpuh) }, + { FRVBF_INSN_MABSHS, SEM_FN_NAME (frvbf,mabshs) }, + { FRVBF_INSN_MADDHSS, SEM_FN_NAME (frvbf,maddhss) }, + { FRVBF_INSN_MADDHUS, SEM_FN_NAME (frvbf,maddhus) }, + { FRVBF_INSN_MSUBHSS, SEM_FN_NAME (frvbf,msubhss) }, + { FRVBF_INSN_MSUBHUS, SEM_FN_NAME (frvbf,msubhus) }, + { FRVBF_INSN_CMADDHSS, SEM_FN_NAME (frvbf,cmaddhss) }, + { FRVBF_INSN_CMADDHUS, SEM_FN_NAME (frvbf,cmaddhus) }, + { FRVBF_INSN_CMSUBHSS, SEM_FN_NAME (frvbf,cmsubhss) }, + { FRVBF_INSN_CMSUBHUS, SEM_FN_NAME (frvbf,cmsubhus) }, + { FRVBF_INSN_MQADDHSS, SEM_FN_NAME (frvbf,mqaddhss) }, + { FRVBF_INSN_MQADDHUS, SEM_FN_NAME (frvbf,mqaddhus) }, + { FRVBF_INSN_MQSUBHSS, SEM_FN_NAME (frvbf,mqsubhss) }, + { FRVBF_INSN_MQSUBHUS, SEM_FN_NAME (frvbf,mqsubhus) }, + { FRVBF_INSN_CMQADDHSS, SEM_FN_NAME (frvbf,cmqaddhss) }, + { FRVBF_INSN_CMQADDHUS, SEM_FN_NAME (frvbf,cmqaddhus) }, + { FRVBF_INSN_CMQSUBHSS, SEM_FN_NAME (frvbf,cmqsubhss) }, + { FRVBF_INSN_CMQSUBHUS, SEM_FN_NAME (frvbf,cmqsubhus) }, + { FRVBF_INSN_MADDACCS, SEM_FN_NAME (frvbf,maddaccs) }, + { FRVBF_INSN_MSUBACCS, SEM_FN_NAME (frvbf,msubaccs) }, + { FRVBF_INSN_MDADDACCS, SEM_FN_NAME (frvbf,mdaddaccs) }, + { FRVBF_INSN_MDSUBACCS, SEM_FN_NAME (frvbf,mdsubaccs) }, + { FRVBF_INSN_MASACCS, SEM_FN_NAME (frvbf,masaccs) }, + { FRVBF_INSN_MDASACCS, SEM_FN_NAME (frvbf,mdasaccs) }, + { FRVBF_INSN_MMULHS, SEM_FN_NAME (frvbf,mmulhs) }, + { FRVBF_INSN_MMULHU, SEM_FN_NAME (frvbf,mmulhu) }, + { FRVBF_INSN_MMULXHS, SEM_FN_NAME (frvbf,mmulxhs) }, + { FRVBF_INSN_MMULXHU, SEM_FN_NAME (frvbf,mmulxhu) }, + { FRVBF_INSN_CMMULHS, SEM_FN_NAME (frvbf,cmmulhs) }, + { FRVBF_INSN_CMMULHU, SEM_FN_NAME (frvbf,cmmulhu) }, + { FRVBF_INSN_MQMULHS, SEM_FN_NAME (frvbf,mqmulhs) }, + { FRVBF_INSN_MQMULHU, SEM_FN_NAME (frvbf,mqmulhu) }, + { FRVBF_INSN_MQMULXHS, SEM_FN_NAME (frvbf,mqmulxhs) }, + { FRVBF_INSN_MQMULXHU, SEM_FN_NAME (frvbf,mqmulxhu) }, + { FRVBF_INSN_CMQMULHS, SEM_FN_NAME (frvbf,cmqmulhs) }, + { FRVBF_INSN_CMQMULHU, SEM_FN_NAME (frvbf,cmqmulhu) }, + { FRVBF_INSN_MMACHS, SEM_FN_NAME (frvbf,mmachs) }, + { FRVBF_INSN_MMACHU, SEM_FN_NAME (frvbf,mmachu) }, + { FRVBF_INSN_MMRDHS, SEM_FN_NAME (frvbf,mmrdhs) }, + { FRVBF_INSN_MMRDHU, SEM_FN_NAME (frvbf,mmrdhu) }, + { FRVBF_INSN_CMMACHS, SEM_FN_NAME (frvbf,cmmachs) }, + { FRVBF_INSN_CMMACHU, SEM_FN_NAME (frvbf,cmmachu) }, + { FRVBF_INSN_MQMACHS, SEM_FN_NAME (frvbf,mqmachs) }, + { FRVBF_INSN_MQMACHU, SEM_FN_NAME (frvbf,mqmachu) }, + { FRVBF_INSN_CMQMACHS, SEM_FN_NAME (frvbf,cmqmachs) }, + { FRVBF_INSN_CMQMACHU, SEM_FN_NAME (frvbf,cmqmachu) }, + { FRVBF_INSN_MQXMACHS, SEM_FN_NAME (frvbf,mqxmachs) }, + { FRVBF_INSN_MQXMACXHS, SEM_FN_NAME (frvbf,mqxmacxhs) }, + { FRVBF_INSN_MQMACXHS, SEM_FN_NAME (frvbf,mqmacxhs) }, + { FRVBF_INSN_MCPXRS, SEM_FN_NAME (frvbf,mcpxrs) }, + { FRVBF_INSN_MCPXRU, SEM_FN_NAME (frvbf,mcpxru) }, + { FRVBF_INSN_MCPXIS, SEM_FN_NAME (frvbf,mcpxis) }, + { FRVBF_INSN_MCPXIU, SEM_FN_NAME (frvbf,mcpxiu) }, + { FRVBF_INSN_CMCPXRS, SEM_FN_NAME (frvbf,cmcpxrs) }, + { FRVBF_INSN_CMCPXRU, SEM_FN_NAME (frvbf,cmcpxru) }, + { FRVBF_INSN_CMCPXIS, SEM_FN_NAME (frvbf,cmcpxis) }, + { FRVBF_INSN_CMCPXIU, SEM_FN_NAME (frvbf,cmcpxiu) }, + { FRVBF_INSN_MQCPXRS, SEM_FN_NAME (frvbf,mqcpxrs) }, + { FRVBF_INSN_MQCPXRU, SEM_FN_NAME (frvbf,mqcpxru) }, + { FRVBF_INSN_MQCPXIS, SEM_FN_NAME (frvbf,mqcpxis) }, + { FRVBF_INSN_MQCPXIU, SEM_FN_NAME (frvbf,mqcpxiu) }, + { FRVBF_INSN_MEXPDHW, SEM_FN_NAME (frvbf,mexpdhw) }, + { FRVBF_INSN_CMEXPDHW, SEM_FN_NAME (frvbf,cmexpdhw) }, + { FRVBF_INSN_MEXPDHD, SEM_FN_NAME (frvbf,mexpdhd) }, + { FRVBF_INSN_CMEXPDHD, SEM_FN_NAME (frvbf,cmexpdhd) }, + { FRVBF_INSN_MPACKH, SEM_FN_NAME (frvbf,mpackh) }, + { FRVBF_INSN_MDPACKH, SEM_FN_NAME (frvbf,mdpackh) }, + { FRVBF_INSN_MUNPACKH, SEM_FN_NAME (frvbf,munpackh) }, + { FRVBF_INSN_MDUNPACKH, SEM_FN_NAME (frvbf,mdunpackh) }, + { FRVBF_INSN_MBTOH, SEM_FN_NAME (frvbf,mbtoh) }, + { FRVBF_INSN_CMBTOH, SEM_FN_NAME (frvbf,cmbtoh) }, + { FRVBF_INSN_MHTOB, SEM_FN_NAME (frvbf,mhtob) }, + { FRVBF_INSN_CMHTOB, SEM_FN_NAME (frvbf,cmhtob) }, + { FRVBF_INSN_MBTOHE, SEM_FN_NAME (frvbf,mbtohe) }, + { FRVBF_INSN_CMBTOHE, SEM_FN_NAME (frvbf,cmbtohe) }, + { FRVBF_INSN_MNOP, SEM_FN_NAME (frvbf,mnop) }, + { FRVBF_INSN_MCLRACC_0, SEM_FN_NAME (frvbf,mclracc_0) }, + { FRVBF_INSN_MCLRACC_1, SEM_FN_NAME (frvbf,mclracc_1) }, + { FRVBF_INSN_MRDACC, SEM_FN_NAME (frvbf,mrdacc) }, + { FRVBF_INSN_MRDACCG, SEM_FN_NAME (frvbf,mrdaccg) }, + { FRVBF_INSN_MWTACC, SEM_FN_NAME (frvbf,mwtacc) }, + { FRVBF_INSN_MWTACCG, SEM_FN_NAME (frvbf,mwtaccg) }, + { FRVBF_INSN_MCOP1, SEM_FN_NAME (frvbf,mcop1) }, + { FRVBF_INSN_MCOP2, SEM_FN_NAME (frvbf,mcop2) }, + { FRVBF_INSN_FNOP, SEM_FN_NAME (frvbf,fnop) }, + { 0, 0 } +}; + +/* Add the semantic fns to IDESC_TABLE. */ + +void +SEM_FN_NAME (frvbf,init_idesc_table) (SIM_CPU *current_cpu) +{ + IDESC *idesc_table = CPU_IDESC (current_cpu); + const struct sem_fn_desc *sf; + int mach_num = MACH_NUM (CPU_MACH (current_cpu)); + + for (sf = &sem_fns[0]; sf->fn != 0; ++sf) + { + const CGEN_INSN *insn = idesc_table[sf->index].idata; + int valid_p = (CGEN_INSN_VIRTUAL_P (insn) + || CGEN_INSN_MACH_HAS_P (insn, mach_num)); +#if FAST_P + if (valid_p) + idesc_table[sf->index].sem_fast = sf->fn; + else + idesc_table[sf->index].sem_fast = SEM_FN_NAME (frvbf,x_invalid); +#else + if (valid_p) + idesc_table[sf->index].sem_full = sf->fn; + else + idesc_table[sf->index].sem_full = SEM_FN_NAME (frvbf,x_invalid); +#endif + } +} + diff --git a/sim/frv/sim-if.c b/sim/frv/sim-if.c new file mode 100644 index 0000000..f3ffbcc --- /dev/null +++ b/sim/frv/sim-if.c @@ -0,0 +1,251 @@ +/* Main simulator entry points specific to the FRV. + Copyright (C) 1998, 1999, 2000 Free Software Foundation, Inc. + Contributed by Red Hat. + +This file is part of the GNU simulators. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#define WANT_CPU +#define WANT_CPU_FRVBF +#include "sim-main.h" +#ifdef HAVE_STDLIB_H +#include +#endif +#include "sim-options.h" +#include "libiberty.h" +#include "bfd.h" +#include "elf-bfd.h" + +static void free_state (SIM_DESC); +static void print_frv_misc_cpu (SIM_CPU *cpu, int verbose); + +/* Records simulator descriptor so utilities like frv_dump_regs can be + called from gdb. */ +SIM_DESC current_state; + +/* Cover function of sim_state_free to free the cpu buffers as well. */ + +static void +free_state (SIM_DESC sd) +{ + if (STATE_MODULES (sd) != NULL) + sim_module_uninstall (sd); + sim_cpu_free_all (sd); + sim_state_free (sd); +} + +/* Create an instance of the simulator. */ + +SIM_DESC +sim_open (kind, callback, abfd, argv) + SIM_OPEN_KIND kind; + host_callback *callback; + bfd *abfd; + char **argv; +{ + char c; + int i; + unsigned long elf_flags = 0; + SIM_DESC sd = sim_state_alloc (kind, callback); + + /* The cpu data is kept in a separately allocated chunk of memory. */ + if (sim_cpu_alloc_all (sd, 1, cgen_cpu_max_extra_bytes ()) != SIM_RC_OK) + { + free_state (sd); + return 0; + } + +#if 0 /* FIXME: pc is in mach-specific struct */ + /* FIXME: watchpoints code shouldn't need this */ + { + SIM_CPU *current_cpu = STATE_CPU (sd, 0); + STATE_WATCHPOINTS (sd)->pc = &(PC); + STATE_WATCHPOINTS (sd)->sizeof_pc = sizeof (PC); + } +#endif + + if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK) + { + free_state (sd); + return 0; + } + + /* These options override any module options. + Obviously ambiguity should be avoided, however the caller may wish to + augment the meaning of an option. */ + sim_add_option_table (sd, NULL, frv_options); + + /* getopt will print the error message so we just have to exit if this fails. + FIXME: Hmmm... in the case of gdb we need getopt to call + print_filtered. */ + if (sim_parse_args (sd, argv) != SIM_RC_OK) + { + free_state (sd); + return 0; + } + +#if 0 + /* Allocate a handler for the control registers and other devices + if no memory for that range has been allocated by the user. + All are allocated in one chunk to keep things from being + unnecessarily complicated. */ + if (sim_core_read_buffer (sd, NULL, read_map, &c, FRV_DEVICE_ADDR, 1) == 0) + sim_core_attach (sd, NULL, + 0 /*level*/, + access_read_write, + 0 /*space ???*/, + FRV_DEVICE_ADDR, FRV_DEVICE_LEN /*nr_bytes*/, + 0 /*modulo*/, + &frv_devices, + NULL /*buffer*/); +#endif + + /* Allocate core managed memory if none specified by user. + Use address 4 here in case the user wanted address 0 unmapped. */ + if (sim_core_read_buffer (sd, NULL, read_map, &c, 4, 1) == 0) + sim_do_commandf (sd, "memory region 0,0x%lx", FRV_DEFAULT_MEM_SIZE); + + /* check for/establish the reference program image */ + if (sim_analyze_program (sd, + (STATE_PROG_ARGV (sd) != NULL + ? *STATE_PROG_ARGV (sd) + : NULL), + abfd) != SIM_RC_OK) + { + free_state (sd); + return 0; + } + + /* set machine and architecture correctly instead of defaulting to frv */ + { + bfd *prog_bfd = STATE_PROG_BFD (sd); + if (prog_bfd != NULL) + { + struct elf_backend_data *backend_data; + + if (bfd_get_arch (prog_bfd) != bfd_arch_frv) + { + sim_io_eprintf (sd, "%s: \"%s\" is not a FRV object file\n", + STATE_MY_NAME (sd), + bfd_get_filename (prog_bfd)); + free_state (sd); + return 0; + } + + backend_data = get_elf_backend_data (prog_bfd); + + if (backend_data != NULL) + backend_data->elf_backend_object_p (prog_bfd); + + elf_flags = elf_elfheader (prog_bfd)->e_flags; + } + } + + /* Establish any remaining configuration options. */ + if (sim_config (sd) != SIM_RC_OK) + { + free_state (sd); + return 0; + } + + if (sim_post_argv_init (sd) != SIM_RC_OK) + { + free_state (sd); + return 0; + } + + /* Open a copy of the cpu descriptor table. */ + { + CGEN_CPU_DESC cd = frv_cgen_cpu_open_1 (STATE_ARCHITECTURE (sd)->printable_name, + CGEN_ENDIAN_BIG); + for (i = 0; i < MAX_NR_PROCESSORS; ++i) + { + SIM_CPU *cpu = STATE_CPU (sd, i); + CPU_CPU_DESC (cpu) = cd; + CPU_DISASSEMBLER (cpu) = sim_cgen_disassemble_insn; + CPU_ELF_FLAGS (cpu) = elf_flags; + } + frv_cgen_init_dis (cd); + } + + /* Initialize various cgen things not done by common framework. + Must be done after frv_cgen_cpu_open. */ + cgen_init (sd); + + /* CPU specific initialization. */ + for (i = 0; i < MAX_NR_PROCESSORS; ++i) + { + SIM_CPU* cpu = STATE_CPU (sd, i); + frv_initialize (cpu, sd); + } + + /* Store in a global so things like sparc32_dump_regs can be invoked + from the gdb command line. */ + current_state = sd; + + return sd; +} + +void +sim_close (sd, quitting) + SIM_DESC sd; + int quitting; +{ + int i; + /* Terminate cache support. */ + for (i = 0; i < MAX_NR_PROCESSORS; ++i) + { + SIM_CPU* cpu = STATE_CPU (sd, i); + frv_cache_term (CPU_INSN_CACHE (cpu)); + frv_cache_term (CPU_DATA_CACHE (cpu)); + } + + frv_cgen_cpu_close (CPU_CPU_DESC (STATE_CPU (sd, 0))); + sim_module_uninstall (sd); +} + +SIM_RC +sim_create_inferior (sd, abfd, argv, envp) + SIM_DESC sd; + bfd *abfd; + char **argv; + char **envp; +{ + SIM_CPU *current_cpu = STATE_CPU (sd, 0); + SIM_ADDR addr; + + if (abfd != NULL) + addr = bfd_get_start_address (abfd); + else + addr = 0; + sim_pc_set (current_cpu, addr); + +#if 0 + STATE_ARGV (sd) = sim_copy_argv (argv); + STATE_ENVP (sd) = sim_copy_argv (envp); +#endif + + return SIM_RC_OK; +} + +void +sim_do_command (sd, cmd) + SIM_DESC sd; + char *cmd; +{ + if (sim_args_command (sd, cmd) != SIM_RC_OK) + sim_io_eprintf (sd, "Unknown command `%s'\n", cmd); +} diff --git a/sim/frv/sim-main.h b/sim/frv/sim-main.h new file mode 100644 index 0000000..927685a --- /dev/null +++ b/sim/frv/sim-main.h @@ -0,0 +1,139 @@ +/* frv simulator support code + Copyright (C) 1998, 2000, 2001 Free Software Foundation, Inc. + Contributed by Red Hat. + +This file is part of the GNU simulators. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* Main header for the frv. */ + +#define USING_SIM_BASE_H /* FIXME: quick hack */ + +struct _sim_cpu; /* FIXME: should be in sim-basics.h */ +typedef struct _sim_cpu SIM_CPU; + +/* Set the mask of unsupported traces. */ +#define WITH_TRACE \ + (~(TRACE_alu | TRACE_decode | TRACE_memory | TRACE_model | TRACE_fpu \ + | TRACE_branch | TRACE_debug)) + +/* sim-basics.h includes config.h but cgen-types.h must be included before + sim-basics.h and cgen-types.h needs config.h. */ +#include "config.h" + +#include "symcat.h" +#include "sim-basics.h" +#include "cgen-types.h" +#include "frv-desc.h" +#include "frv-opc.h" +#include "arch.h" + +/* These must be defined before sim-base.h. */ +typedef USI sim_cia; + +#define CIA_GET(cpu) CPU_PC_GET (cpu) +#define CIA_SET(cpu,val) CPU_PC_SET ((cpu), (val)) + +void frv_sim_engine_halt_hook (SIM_DESC, SIM_CPU *, sim_cia); +#define SIM_ENGINE_HALT_HOOK(SD, LAST_CPU, CIA) \ + frv_sim_engine_halt_hook ((SD), (LAST_CPU), (CIA)) + +#define SIM_ENGINE_RESTART_HOOK(SD, LAST_CPU, CIA) 0 + +#include "sim-base.h" +#include "cgen-sim.h" +#include "frv-sim.h" +#include "cache.h" +#include "registers.h" +#include "profile.h" + +/* The _sim_cpu struct. */ + +struct _sim_cpu { + /* sim/common cpu base. */ + sim_cpu_base base; + + /* Static parts of cgen. */ + CGEN_CPU cgen_cpu; + + /* CPU specific parts go here. + Note that in files that don't need to access these pieces WANT_CPU_FOO + won't be defined and thus these parts won't appear. This is ok in the + sense that things work. It is a source of bugs though. + One has to of course be careful to not take the size of this + struct and no structure members accessed in non-cpu specific files can + go after here. Oh for a better language. */ +#if defined (WANT_CPU_FRVBF) + FRVBF_CPU_DATA cpu_data; + + /* Control information for registers */ + FRV_REGISTER_CONTROL register_control; +#define CPU_REGISTER_CONTROL(cpu) (& (cpu)->register_control) + + FRV_VLIW vliw; +#define CPU_VLIW(cpu) (& (cpu)->vliw) + + FRV_CACHE insn_cache; +#define CPU_INSN_CACHE(cpu) (& (cpu)->insn_cache) + + FRV_CACHE data_cache; +#define CPU_DATA_CACHE(cpu) (& (cpu)->data_cache) + + FRV_PROFILE_STATE profile_state; +#define CPU_PROFILE_STATE(cpu) (& (cpu)->profile_state) + + int debug_state; +#define CPU_DEBUG_STATE(cpu) ((cpu)->debug_state) + + SI load_address; +#define CPU_LOAD_ADDRESS(cpu) ((cpu)->load_address) + + SI load_length; +#define CPU_LOAD_LENGTH(cpu) ((cpu)->load_length) + + SI load_flag; +#define CPU_LOAD_SIGNED(cpu) ((cpu)->load_flag) +#define CPU_LOAD_LOCK(cpu) ((cpu)->load_flag) + + SI store_flag; +#define CPU_RSTR_INVALIDATE(cpu) ((cpu)->store_flag) + + unsigned long elf_flags; +#define CPU_ELF_FLAGS(cpu) ((cpu)->elf_flags) +#endif /* defined (WANT_CPU_FRVBF) */ +}; + +/* The sim_state struct. */ + +struct sim_state { + sim_cpu *cpu; +#define STATE_CPU(sd, n) (/*&*/ (sd)->cpu) + + CGEN_STATE cgen_state; + + sim_state_base base; +}; + +/* Misc. */ + +/* Catch address exceptions. */ +extern SIM_CORE_SIGNAL_FN frv_core_signal; +#define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \ +frv_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), \ + (TRANSFER), (ERROR)) + +/* Default memory size. */ +#define FRV_DEFAULT_MEM_SIZE 0x800000 /* 8M */ diff --git a/sim/frv/tconfig.in b/sim/frv/tconfig.in new file mode 100644 index 0000000..a53ad23 --- /dev/null +++ b/sim/frv/tconfig.in @@ -0,0 +1,42 @@ +/* FRV target configuration file. -*- C -*- */ + +/* Define this if the simulator can vary the size of memory. + See the xxx simulator for an example. + This enables the `-m size' option. + The memory size is stored in STATE_MEM_SIZE. */ +/* Not used for FRV since we use the memory module. TODO -- check this */ +/* #define SIM_HAVE_MEM_SIZE */ + +/* See sim-hload.c. We properly handle LMA. -- TODO: check this */ +#define SIM_HANDLES_LMA 1 + +/* For MSPR support. FIXME: revisit. */ +#define WITH_DEVICES 1 + +/* FIXME: Revisit. */ +#ifdef HAVE_DV_SOCKSER +MODULE_INSTALL_FN dv_sockser_install; +#define MODULE_LIST dv_sockser_install, +#endif + +#if 0 +/* Enable watchpoints. */ +#define WITH_WATCHPOINTS 1 +#endif + +/* ??? Temporary hack until model support unified. */ +#define SIM_HAVE_MODEL + +/* Define this to enable the intrinsic breakpoint mechanism. */ +/* FIXME: may be able to remove SIM_HAVE_BREAKPOINTS since it essentially + duplicates ifdef SIM_BREAKPOINT (right?) */ +#if 0 +#define SIM_HAVE_BREAKPOINTS +#define SIM_BREAKPOINT { 0x10, 0xf1 } +#define SIM_BREAKPOINT_SIZE 2 +#endif + +/* This is a global setting. Different cpu families can't mix-n-match -scache + and -pbb. However some cpu families may use -simple while others use + one of -scache/-pbb. ???? */ +#define WITH_SCACHE_PBB 0 diff --git a/sim/frv/traps.c b/sim/frv/traps.c new file mode 100644 index 0000000..f7b4b74 --- /dev/null +++ b/sim/frv/traps.c @@ -0,0 +1,997 @@ +/* frv trap support + Copyright (C) 1999, 2000, 2001, 2003 Free Software Foundation, Inc. + Contributed by Red Hat. + +This file is part of the GNU simulators. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#define WANT_CPU frvbf +#define WANT_CPU_FRVBF + +#include "sim-main.h" +#include "targ-vals.h" +#include "cgen-engine.h" +#include "cgen-par.h" +#include "sim-fpu.h" + +#include "bfd.h" +#include "libiberty.h" + +CGEN_ATTR_VALUE_TYPE frv_current_fm_slot; + +/* The semantic code invokes this for invalid (unrecognized) instructions. */ + +SEM_PC +sim_engine_invalid_insn (SIM_CPU *current_cpu, IADDR cia, SEM_PC vpc) +{ + frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION); + return vpc; +} + +/* Process an address exception. */ + +void +frv_core_signal (SIM_DESC sd, SIM_CPU *current_cpu, sim_cia cia, + unsigned int map, int nr_bytes, address_word addr, + transfer_type transfer, sim_core_signals sig) +{ + if (sig == sim_core_unaligned_signal) + { + if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr400) + frv_queue_data_access_error_interrupt (current_cpu, addr); + else + frv_queue_mem_address_not_aligned_interrupt (current_cpu, addr); + } + + frv_term (sd); + sim_core_signal (sd, current_cpu, cia, map, nr_bytes, addr, transfer, sig); +} + +void +frv_sim_engine_halt_hook (SIM_DESC sd, SIM_CPU *current_cpu, sim_cia cia) +{ + int i; + if (current_cpu != NULL) + CIA_SET (current_cpu, cia); + + /* Invalidate the insn and data caches of all cpus. */ + for (i = 0; i < MAX_NR_PROCESSORS; ++i) + { + current_cpu = STATE_CPU (sd, i); + frv_cache_invalidate_all (CPU_INSN_CACHE (current_cpu), 0); + frv_cache_invalidate_all (CPU_DATA_CACHE (current_cpu), 1); + } + frv_term (sd); +} + +/* Read/write functions for system call interface. */ + +static int +syscall_read_mem (host_callback *cb, struct cb_syscall *sc, + unsigned long taddr, char *buf, int bytes) +{ + SIM_DESC sd = (SIM_DESC) sc->p1; + SIM_CPU *cpu = (SIM_CPU *) sc->p2; + + frv_cache_invalidate_all (CPU_DATA_CACHE (cpu), 1); + return sim_core_read_buffer (sd, cpu, read_map, buf, taddr, bytes); +} + +static int +syscall_write_mem (host_callback *cb, struct cb_syscall *sc, + unsigned long taddr, const char *buf, int bytes) +{ + SIM_DESC sd = (SIM_DESC) sc->p1; + SIM_CPU *cpu = (SIM_CPU *) sc->p2; + + frv_cache_invalidate_all (CPU_INSN_CACHE (cpu), 0); + frv_cache_invalidate_all (CPU_DATA_CACHE (cpu), 1); + return sim_core_write_buffer (sd, cpu, write_map, buf, taddr, bytes); +} + +/* Handle TRA and TIRA insns. */ +void +frv_itrap (SIM_CPU *current_cpu, PCADDR pc, USI base, SI offset) +{ + SIM_DESC sd = CPU_STATE (current_cpu); + host_callback *cb = STATE_CALLBACK (sd); + USI num = ((base + offset) & 0x7f) + 0x80; + +#ifdef SIM_HAVE_BREAKPOINTS + /* Check for breakpoints "owned" by the simulator first, regardless + of --environment. */ + if (num == TRAP_BREAKPOINT) + { + /* First try sim-break.c. If it's a breakpoint the simulator "owns" + it doesn't return. Otherwise it returns and let's us try. */ + sim_handle_breakpoint (sd, current_cpu, pc); + /* Fall through. */ + } +#endif + + if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT) + { + frv_queue_software_interrupt (current_cpu, num); + return; + } + + switch (num) + { + case TRAP_SYSCALL : + { + CB_SYSCALL s; + CB_SYSCALL_INIT (&s); + s.func = GET_H_GR (7); + s.arg1 = GET_H_GR (8); + s.arg2 = GET_H_GR (9); + s.arg3 = GET_H_GR (10); + + if (s.func == TARGET_SYS_exit) + { + sim_engine_halt (sd, current_cpu, NULL, pc, sim_exited, s.arg1); + } + + s.p1 = (PTR) sd; + s.p2 = (PTR) current_cpu; + s.read_mem = syscall_read_mem; + s.write_mem = syscall_write_mem; + cb_syscall (cb, &s); + SET_H_GR (8, s.result); + SET_H_GR (9, s.result2); + SET_H_GR (10, s.errcode); + break; + } + + case TRAP_BREAKPOINT: + sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped, SIM_SIGTRAP); + break; + + /* Add support for dumping registers, either at fixed traps, or all + unknown traps if configured with --enable-sim-trapdump. */ + default: +#if !TRAPDUMP + frv_queue_software_interrupt (current_cpu, num); + return; +#endif + +#ifdef TRAP_REGDUMP1 + case TRAP_REGDUMP1: +#endif + +#ifdef TRAP_REGDUMP2 + case TRAP_REGDUMP2: +#endif + +#if TRAPDUMP || (defined (TRAP_REGDUMP1)) || (defined (TRAP_REGDUMP2)) + { + char buf[256]; + int i, j; + + buf[0] = 0; + if (STATE_TEXT_SECTION (sd) + && pc >= STATE_TEXT_START (sd) + && pc < STATE_TEXT_END (sd)) + { + const char *pc_filename = (const char *)0; + const char *pc_function = (const char *)0; + unsigned int pc_linenum = 0; + + if (bfd_find_nearest_line (STATE_PROG_BFD (sd), + STATE_TEXT_SECTION (sd), + (struct bfd_symbol **) 0, + pc - STATE_TEXT_START (sd), + &pc_filename, &pc_function, &pc_linenum) + && (pc_function || pc_filename)) + { + char *p = buf+2; + buf[0] = ' '; + buf[1] = '('; + if (pc_function) + { + strcpy (p, pc_function); + p += strlen (p); + } + else + { + char *q = (char *) strrchr (pc_filename, '/'); + strcpy (p, (q) ? q+1 : pc_filename); + p += strlen (p); + } + + if (pc_linenum) + { + sprintf (p, " line %d", pc_linenum); + p += strlen (p); + } + + p[0] = ')'; + p[1] = '\0'; + if ((p+1) - buf > sizeof (buf)) + abort (); + } + } + + sim_io_printf (sd, + "\nRegister dump, pc = 0x%.8x%s, base = %u, offset = %d\n", + (unsigned)pc, buf, (unsigned)base, (int)offset); + + for (i = 0; i < 64; i += 8) + { + long g0 = (long)GET_H_GR (i); + long g1 = (long)GET_H_GR (i+1); + long g2 = (long)GET_H_GR (i+2); + long g3 = (long)GET_H_GR (i+3); + long g4 = (long)GET_H_GR (i+4); + long g5 = (long)GET_H_GR (i+5); + long g6 = (long)GET_H_GR (i+6); + long g7 = (long)GET_H_GR (i+7); + + if ((g0 | g1 | g2 | g3 | g4 | g5 | g6 | g7) != 0) + sim_io_printf (sd, + "\tgr%02d - gr%02d: 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx\n", + i, i+7, g0, g1, g2, g3, g4, g5, g6, g7); + } + + for (i = 0; i < 64; i += 8) + { + long f0 = (long)GET_H_FR (i); + long f1 = (long)GET_H_FR (i+1); + long f2 = (long)GET_H_FR (i+2); + long f3 = (long)GET_H_FR (i+3); + long f4 = (long)GET_H_FR (i+4); + long f5 = (long)GET_H_FR (i+5); + long f6 = (long)GET_H_FR (i+6); + long f7 = (long)GET_H_FR (i+7); + + if ((f0 | f1 | f2 | f3 | f4 | f5 | f6 | f7) != 0) + sim_io_printf (sd, + "\tfr%02d - fr%02d: 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx\n", + i, i+7, f0, f1, f2, f3, f4, f5, f6, f7); + } + + sim_io_printf (sd, + "\tlr/lcr/cc/ccc: 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx\n", + (long)GET_H_SPR (272), + (long)GET_H_SPR (273), + (long)GET_H_SPR (256), + (long)GET_H_SPR (263)); + } + break; +#endif + } +} + +/* Handle the MTRAP insn. */ +void +frv_mtrap (SIM_CPU *current_cpu) +{ + SIM_DESC sd = CPU_STATE (current_cpu); + + /* Check the status of media exceptions in MSR0. */ + SI msr = GET_MSR (0); + if (GET_MSR_AOVF (msr) || GET_MSR_MTT (msr) && STATE_ARCHITECTURE (sd)->mach != bfd_mach_fr550) + frv_queue_program_interrupt (current_cpu, FRV_MP_EXCEPTION); +} + +/* Handle the BREAK insn. */ +void +frv_break (SIM_CPU *current_cpu) +{ + IADDR pc; + SIM_DESC sd = CPU_STATE (current_cpu); + +#ifdef SIM_HAVE_BREAKPOINTS + /* First try sim-break.c. If it's a breakpoint the simulator "owns" + it doesn't return. Otherwise it returns and let's us try. */ + pc = GET_H_PC (); + sim_handle_breakpoint (sd, current_cpu, pc); + /* Fall through. */ +#endif + + if (STATE_ENVIRONMENT (sd) != OPERATING_ENVIRONMENT) + { + /* Invalidate the insn cache because the debugger will presumably + replace the breakpoint insn with the real one. */ +#ifndef SIM_HAVE_BREAKPOINTS + pc = GET_H_PC (); +#endif + sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped, SIM_SIGTRAP); + } + + frv_queue_break_interrupt (current_cpu); +} + +/* Return from trap. */ +USI +frv_rett (SIM_CPU *current_cpu, PCADDR pc, BI debug_field) +{ + USI new_pc; + /* if (normal running mode and debug_field==0 + PC=PCSR + PSR.ET=1 + PSR.S=PSR.PS + else if (debug running mode and debug_field==1) + PC=(BPCSR) + PSR.ET=BPSR.BET + PSR.S=BPSR.BS + change to normal running mode + */ + int psr_s = GET_H_PSR_S (); + int psr_et = GET_H_PSR_ET (); + + /* Check for exceptions in the priority order listed in the FRV Architecture + Volume 2. */ + if (! psr_s) + { + /* Halt if PSR.ET is not set. See chapter 6 of the LSI. */ + if (! psr_et) + { + SIM_DESC sd = CPU_STATE (current_cpu); + sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped, SIM_SIGTRAP); + } + + /* privileged_instruction interrupt will have already been queued by + frv_detect_insn_access_interrupts. */ + new_pc = pc + 4; + } + else if (psr_et) + { + /* Halt if PSR.S is set. See chapter 6 of the LSI. */ + if (psr_s) + { + SIM_DESC sd = CPU_STATE (current_cpu); + sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped, SIM_SIGTRAP); + } + + frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION); + new_pc = pc + 4; + } + else if (! CPU_DEBUG_STATE (current_cpu) && debug_field == 0) + { + USI psr = GET_PSR (); + /* Return from normal running state. */ + new_pc = GET_H_SPR (H_SPR_PCSR); + SET_PSR_ET (psr, 1); + SET_PSR_S (psr, GET_PSR_PS (psr)); + sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, H_SPR_PSR, psr); + } + else if (CPU_DEBUG_STATE (current_cpu) && debug_field == 1) + { + USI psr = GET_PSR (); + /* Return from debug state. */ + new_pc = GET_H_SPR (H_SPR_BPCSR); + SET_PSR_ET (psr, GET_H_BPSR_BET ()); + SET_PSR_S (psr, GET_H_BPSR_BS ()); + sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, H_SPR_PSR, psr); + CPU_DEBUG_STATE (current_cpu) = 0; + } + else + new_pc = pc + 4; + + return new_pc; +} + +/* Functions for handling non-excepting instruction side effects. */ +static SI next_available_nesr (SIM_CPU *current_cpu, SI current_index) +{ + FRV_REGISTER_CONTROL *control = CPU_REGISTER_CONTROL (current_cpu); + if (control->spr[H_SPR_NECR].implemented) + { + int limit; + USI necr = GET_NECR (); + + /* See if any NESRs are implemented. First need to check the validity of + the NECR. */ + if (! GET_NECR_VALID (necr)) + return NO_NESR; + + limit = GET_NECR_NEN (necr); + for (++current_index; current_index < limit; ++current_index) + { + SI nesr = GET_NESR (current_index); + if (! GET_NESR_VALID (nesr)) + return current_index; + } + } + return NO_NESR; +} + +static SI next_valid_nesr (SIM_CPU *current_cpu, SI current_index) +{ + FRV_REGISTER_CONTROL *control = CPU_REGISTER_CONTROL (current_cpu); + if (control->spr[H_SPR_NECR].implemented) + { + int limit; + USI necr = GET_NECR (); + + /* See if any NESRs are implemented. First need to check the validity of + the NECR. */ + if (! GET_NECR_VALID (necr)) + return NO_NESR; + + limit = GET_NECR_NEN (necr); + for (++current_index; current_index < limit; ++current_index) + { + SI nesr = GET_NESR (current_index); + if (GET_NESR_VALID (nesr)) + return current_index; + } + } + return NO_NESR; +} + +BI +frvbf_check_non_excepting_load ( + SIM_CPU *current_cpu, SI base_index, SI disp_index, SI target_index, + SI immediate_disp, QI data_size, BI is_float +) +{ + BI rc = 1; /* perform the load. */ + SIM_DESC sd = CPU_STATE (current_cpu); + int daec = 0; + int rec = 0; + int ec = 0; + USI necr; + int do_elos; + SI NE_flags[2]; + SI NE_base; + SI nesr; + SI ne_index; + FRV_REGISTER_CONTROL *control; + + SI address = GET_H_GR (base_index); + if (disp_index >= 0) + address += GET_H_GR (disp_index); + else + address += immediate_disp; + + /* Check for interrupt factors. */ + switch (data_size) + { + case NESR_UQI_SIZE: + case NESR_QI_SIZE: + break; + case NESR_UHI_SIZE: + case NESR_HI_SIZE: + if (address & 1) + ec = 1; + break; + case NESR_SI_SIZE: + if (address & 3) + ec = 1; + break; + case NESR_DI_SIZE: + if (address & 7) + ec = 1; + if (target_index & 1) + rec = 1; + break; + case NESR_XI_SIZE: + if (address & 0xf) + ec = 1; + if (target_index & 3) + rec = 1; + break; + default: + { + IADDR pc = GET_H_PC (); + sim_engine_abort (sd, current_cpu, pc, + "check_non_excepting_load: Incorrect data_size\n"); + break; + } + } + + control = CPU_REGISTER_CONTROL (current_cpu); + if (control->spr[H_SPR_NECR].implemented) + { + necr = GET_NECR (); + do_elos = GET_NECR_VALID (necr) && GET_NECR_ELOS (necr); + } + else + do_elos = 0; + + /* NECR, NESR, NEEAR are only implemented for the full frv machine. */ + if (do_elos) + { + ne_index = next_available_nesr (current_cpu, NO_NESR); + if (ne_index == NO_NESR) + { + IADDR pc = GET_H_PC (); + sim_engine_abort (sd, current_cpu, pc, + "No available NESR register\n"); + } + + /* Fill in the basic fields of the NESR. */ + nesr = GET_NESR (ne_index); + SET_NESR_VALID (nesr); + SET_NESR_EAV (nesr); + SET_NESR_DRN (nesr, target_index); + SET_NESR_SIZE (nesr, data_size); + SET_NESR_NEAN (nesr, ne_index); + if (is_float) + SET_NESR_FR (nesr); + else + CLEAR_NESR_FR (nesr); + + /* Set the corresponding NEEAR. */ + SET_NEEAR (ne_index, address); + + SET_NESR_DAEC (nesr, 0); + SET_NESR_REC (nesr, 0); + SET_NESR_EC (nesr, 0); + } + + /* Set the NE flag corresponding to the target register if an interrupt + factor was detected. + daec is not checked here yet, but is declared for future reference. */ + if (is_float) + NE_base = H_SPR_FNER0; + else + NE_base = H_SPR_GNER0; + + GET_NE_FLAGS (NE_flags, NE_base); + if (rec) + { + SET_NE_FLAG (NE_flags, target_index); + if (do_elos) + SET_NESR_REC (nesr, NESR_REGISTER_NOT_ALIGNED); + } + + if (ec) + { + SET_NE_FLAG (NE_flags, target_index); + if (do_elos) + SET_NESR_EC (nesr, NESR_MEM_ADDRESS_NOT_ALIGNED); + } + + if (do_elos) + SET_NESR (ne_index, nesr); + + /* If no interrupt factor was detected then set the NE flag on the + target register if the NE flag on one of the input registers + is already set. */ + if (! rec && ! ec && ! daec) + { + BI ne_flag = GET_NE_FLAG (NE_flags, base_index); + if (disp_index >= 0) + ne_flag |= GET_NE_FLAG (NE_flags, disp_index); + if (ne_flag) + { + SET_NE_FLAG (NE_flags, target_index); + rc = 0; /* Do not perform the load. */ + } + else + CLEAR_NE_FLAG (NE_flags, target_index); + } + + SET_NE_FLAGS (NE_base, NE_flags); + + return rc; /* perform the load? */ +} + +/* Record state for media exception: media_cr_not_aligned. */ +void +frvbf_media_cr_not_aligned (SIM_CPU *current_cpu) +{ + SIM_DESC sd = CPU_STATE (current_cpu); + + /* On some machines this generates an illegal_instruction interrupt. */ + switch (STATE_ARCHITECTURE (sd)->mach) + { + case bfd_mach_fr400: + case bfd_mach_fr550: + frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION); + break; + default: + frv_set_mp_exception_registers (current_cpu, MTT_CR_NOT_ALIGNED, 0); + break; + } +} + +/* Record state for media exception: media_acc_not_aligned. */ +void +frvbf_media_acc_not_aligned (SIM_CPU *current_cpu) +{ + SIM_DESC sd = CPU_STATE (current_cpu); + + /* On some machines this generates an illegal_instruction interrupt. */ + switch (STATE_ARCHITECTURE (sd)->mach) + { + case bfd_mach_fr400: + case bfd_mach_fr550: + frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION); + break; + default: + frv_set_mp_exception_registers (current_cpu, MTT_ACC_NOT_ALIGNED, 0); + break; + } +} + +/* Record state for media exception: media_register_not_aligned. */ +void +frvbf_media_register_not_aligned (SIM_CPU *current_cpu) +{ + SIM_DESC sd = CPU_STATE (current_cpu); + + /* On some machines this generates an illegal_instruction interrupt. */ + switch (STATE_ARCHITECTURE (sd)->mach) + { + case bfd_mach_fr400: + case bfd_mach_fr550: + frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION); + break; + default: + frv_set_mp_exception_registers (current_cpu, MTT_INVALID_FR, 0); + break; + } +} + +/* Record state for media exception: media_overflow. */ +void +frvbf_media_overflow (SIM_CPU *current_cpu, int sie) +{ + frv_set_mp_exception_registers (current_cpu, MTT_OVERFLOW, sie); +} + +/* Queue a division exception. */ +enum frv_dtt +frvbf_division_exception (SIM_CPU *current_cpu, enum frv_dtt dtt, + int target_index, int non_excepting) +{ + /* If there was an overflow and it is masked, then record it in + ISR.AEXC. */ + USI isr = GET_ISR (); + if ((dtt & FRV_DTT_OVERFLOW) && GET_ISR_EDE (isr)) + { + dtt &= ~FRV_DTT_OVERFLOW; + SET_ISR_AEXC (isr); + SET_ISR (isr); + } + if (dtt != FRV_DTT_NO_EXCEPTION) + { + if (non_excepting) + { + /* Non excepting instruction, simply set the NE flag for the target + register. */ + SI NE_flags[2]; + GET_NE_FLAGS (NE_flags, H_SPR_GNER0); + SET_NE_FLAG (NE_flags, target_index); + SET_NE_FLAGS (H_SPR_GNER0, NE_flags); + } + else + frv_queue_division_exception_interrupt (current_cpu, dtt); + } + return dtt; +} + +void +frvbf_check_recovering_store ( + SIM_CPU *current_cpu, PCADDR address, SI regno, int size, int is_float +) +{ + FRV_CACHE *cache = CPU_DATA_CACHE (current_cpu); + int reg_ix; + + CPU_RSTR_INVALIDATE(current_cpu) = 0; + + for (reg_ix = next_valid_nesr (current_cpu, NO_NESR); + reg_ix != NO_NESR; + reg_ix = next_valid_nesr (current_cpu, reg_ix)) + { + if (address == GET_H_SPR (H_SPR_NEEAR0 + reg_ix)) + { + SI nesr = GET_NESR (reg_ix); + int nesr_drn = GET_NESR_DRN (nesr); + BI nesr_fr = GET_NESR_FR (nesr); + SI remain; + + /* Invalidate cache block containing this address. + If we need to count cycles, then the cache operation will be + initiated from the model profiling functions. + See frvbf_model_.... */ + if (model_insn) + { + CPU_RSTR_INVALIDATE(current_cpu) = 1; + CPU_LOAD_ADDRESS (current_cpu) = address; + } + else + frv_cache_invalidate (cache, address, 1/* flush */); + + /* Copy the stored value to the register indicated by NESR.DRN. */ + for (remain = size; remain > 0; remain -= 4) + { + SI value; + + if (is_float) + value = GET_H_FR (regno); + else + value = GET_H_GR (regno); + + switch (size) + { + case 1: + value &= 0xff; + break; + case 2: + value &= 0xffff; + break; + default: + break; + } + + if (nesr_fr) + sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, nesr_drn, + value); + else + sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, nesr_drn, + value); + + nesr_drn++; + regno++; + } + break; /* Only consider the first matching register. */ + } + } /* loop over active neear registers. */ +} + +SI +frvbf_check_acc_range (SIM_CPU *current_cpu, SI regno) +{ + /* Only applicable to fr550 */ + SIM_DESC sd = CPU_STATE (current_cpu); + if (STATE_ARCHITECTURE (sd)->mach != bfd_mach_fr550) + return; + + /* On the fr550, media insns in slots 0 and 2 can only access + accumulators acc0-acc3. Insns in slots 1 and 3 can only access + accumulators acc4-acc7 */ + switch (frv_current_fm_slot) + { + case UNIT_FM0: + case UNIT_FM2: + if (regno <= 3) + return 1; /* all is ok */ + break; + case UNIT_FM1: + case UNIT_FM3: + if (regno >= 4) + return 1; /* all is ok */ + break; + } + + /* The specified accumulator is out of range. Queue an illegal_instruction + interrupt. */ + frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION); + return 0; +} + +void +frvbf_check_swap_address (SIM_CPU *current_cpu, SI address) +{ + /* Only applicable to fr550 */ + SIM_DESC sd = CPU_STATE (current_cpu); + if (STATE_ARCHITECTURE (sd)->mach != bfd_mach_fr550) + return; + + /* Adress must be aligned on a word boundary. */ + if (address & 0x3) + frv_queue_data_access_exception_interrupt (current_cpu); +} + +static void +clear_nesr_neear (SIM_CPU *current_cpu, SI target_index, BI is_float) +{ + int reg_ix; + + /* Only implemented for full frv. */ + SIM_DESC sd = CPU_STATE (current_cpu); + if (STATE_ARCHITECTURE (sd)->mach != bfd_mach_frv) + return; + + /* Clear the appropriate NESR and NEEAR registers. */ + for (reg_ix = next_valid_nesr (current_cpu, NO_NESR); + reg_ix != NO_NESR; + reg_ix = next_valid_nesr (current_cpu, reg_ix)) + { + SI nesr; + /* The register is available, now check if it is active. */ + nesr = GET_NESR (reg_ix); + if (GET_NESR_FR (nesr) == is_float) + { + if (target_index < 0 || GET_NESR_DRN (nesr) == target_index) + { + SET_NESR (reg_ix, 0); + SET_NEEAR (reg_ix, 0); + } + } + } +} + +static void +clear_ne_flags ( + SIM_CPU *current_cpu, + SI target_index, + int hi_available, + int lo_available, + SI NE_base +) +{ + SI NE_flags[2]; + int exception; + + GET_NE_FLAGS (NE_flags, NE_base); + if (target_index >= 0) + CLEAR_NE_FLAG (NE_flags, target_index); + else + { + if (lo_available) + NE_flags[1] = 0; + if (hi_available) + NE_flags[0] = 0; + } + SET_NE_FLAGS (NE_base, NE_flags); +} + +/* Return 1 if the given register is available, 0 otherwise. TARGET_INDEX==-1 + means to check for any register available. */ +static void +which_registers_available ( + SIM_CPU *current_cpu, int *hi_available, int *lo_available, int is_float +) +{ + if (is_float) + frv_fr_registers_available (current_cpu, hi_available, lo_available); + else + frv_gr_registers_available (current_cpu, hi_available, lo_available); +} + +void +frvbf_clear_ne_flags (SIM_CPU *current_cpu, SI target_index, BI is_float) +{ + int hi_available; + int lo_available; + int exception; + SI NE_base; + USI necr; + FRV_REGISTER_CONTROL *control; + + /* Check for availability of the target register(s). */ + which_registers_available (current_cpu, & hi_available, & lo_available, + is_float); + + /* Check to make sure that the target register is available. */ + if (! frv_check_register_access (current_cpu, target_index, + hi_available, lo_available)) + return; + + /* Determine whether we're working with GR or FR registers. */ + if (is_float) + NE_base = H_SPR_FNER0; + else + NE_base = H_SPR_GNER0; + + /* Always clear the appropriate NE flags. */ + clear_ne_flags (current_cpu, target_index, hi_available, lo_available, + NE_base); + + /* Clear the appropriate NESR and NEEAR registers. */ + control = CPU_REGISTER_CONTROL (current_cpu); + if (control->spr[H_SPR_NECR].implemented) + { + necr = GET_NECR (); + if (GET_NECR_VALID (necr) && GET_NECR_ELOS (necr)) + clear_nesr_neear (current_cpu, target_index, is_float); + } +} + +void +frvbf_commit (SIM_CPU *current_cpu, SI target_index, BI is_float) +{ + SI NE_base; + SI NE_flags[2]; + BI NE_flag; + int exception; + int hi_available; + int lo_available; + USI necr; + FRV_REGISTER_CONTROL *control; + + /* Check for availability of the target register(s). */ + which_registers_available (current_cpu, & hi_available, & lo_available, + is_float); + + /* Check to make sure that the target register is available. */ + if (! frv_check_register_access (current_cpu, target_index, + hi_available, lo_available)) + return; + + /* Determine whether we're working with GR or FR registers. */ + if (is_float) + NE_base = H_SPR_FNER0; + else + NE_base = H_SPR_GNER0; + + /* Determine whether a ne exception is pending. */ + GET_NE_FLAGS (NE_flags, NE_base); + if (target_index >= 0) + NE_flag = GET_NE_FLAG (NE_flags, target_index); + else + { + NE_flag = + hi_available && NE_flags[0] != 0 || lo_available && NE_flags[1] != 0; + } + + /* Always clear the appropriate NE flags. */ + clear_ne_flags (current_cpu, target_index, hi_available, lo_available, + NE_base); + + control = CPU_REGISTER_CONTROL (current_cpu); + if (control->spr[H_SPR_NECR].implemented) + { + necr = GET_NECR (); + if (GET_NECR_VALID (necr) && GET_NECR_ELOS (necr) && NE_flag) + { + /* Clear the appropriate NESR and NEEAR registers. */ + clear_nesr_neear (current_cpu, target_index, is_float); + frv_queue_program_interrupt (current_cpu, FRV_COMMIT_EXCEPTION); + } + } +} + +/* Generate the appropriate fp_exception(s) based on the given status code. */ +void +frvbf_fpu_error (CGEN_FPU* fpu, int status) +{ + struct frv_fp_exception_info fp_info = { + FSR_NO_EXCEPTION, FTT_IEEE_754_EXCEPTION + }; + + if (status & + (sim_fpu_status_invalid_snan | + sim_fpu_status_invalid_qnan | + sim_fpu_status_invalid_isi | + sim_fpu_status_invalid_idi | + sim_fpu_status_invalid_zdz | + sim_fpu_status_invalid_imz | + sim_fpu_status_invalid_cvi | + sim_fpu_status_invalid_cmp | + sim_fpu_status_invalid_sqrt)) + fp_info.fsr_mask |= FSR_INVALID_OPERATION; + + if (status & sim_fpu_status_invalid_div0) + fp_info.fsr_mask |= FSR_DIVISION_BY_ZERO; + + if (status & sim_fpu_status_inexact) + fp_info.fsr_mask |= FSR_INEXACT; + + if (status & sim_fpu_status_overflow) + fp_info.fsr_mask |= FSR_OVERFLOW; + + if (status & sim_fpu_status_underflow) + fp_info.fsr_mask |= FSR_UNDERFLOW; + + if (status & sim_fpu_status_denorm) + { + fp_info.fsr_mask |= FSR_DENORMAL_INPUT; + fp_info.ftt = FTT_DENORMAL_INPUT; + } + + if (fp_info.fsr_mask != FSR_NO_EXCEPTION) + { + SIM_CPU *current_cpu = (SIM_CPU *)fpu->owner; + frv_queue_fp_exception_interrupt (current_cpu, & fp_info); + } +} diff --git a/sim/h8300/sim-main.h b/sim/h8300/sim-main.h new file mode 100644 index 0000000..284a558 --- /dev/null +++ b/sim/h8300/sim-main.h @@ -0,0 +1,172 @@ +/* Main header for the Hitachi h8/300 architecture. */ + +#include "bfd.h" + +#ifndef SIM_MAIN_H +#define SIM_MAIN_H + +#define DEBUG + +/* These define the size of main memory for the simulator. + + Note the size of main memory for the H8/300H is only 256k. Keeping it + small makes the simulator run much faster and consume less memory. + + The linker knows about the limited size of the simulator's main memory + on the H8/300H (via the h8300h.sc linker script). So if you change + H8300H_MSIZE, be sure to fix the linker script too. + + Also note that there's a separate "eightbit" area aside from main + memory. For simplicity, the simulator assumes any data memory reference + outside of main memory refers to the eightbit area (in theory, this + can only happen when simulating H8/300H programs). We make no attempt + to catch overlapping addresses, wrapped addresses, etc etc. */ + +#define H8300_MSIZE (1 << 16) + +/* avolkov: + Next 2 macros are ugly for any workstation, but while they're work. + Memory size MUST be configurable. */ +#define H8300H_MSIZE (1 << 18) +#define H8300S_MSIZE (1 << 24) + +#define CSIZE 1024 + +enum h8_regnum { + R0_REGNUM = 0, + R1_REGNUM = 1, + R2_REGNUM = 2, + R3_REGNUM = 3, + R4_REGNUM = 4, + R5_REGNUM = 5, + R6_REGNUM = 6, + R7_REGNUM = 7, + + SP_REGNUM = R7_REGNUM, /* Contains address of top of stack */ + FP_REGNUM = R6_REGNUM, /* Contains address of executing + stack frame */ + CCR_REGNUM = 8, /* Contains processor status */ + PC_REGNUM = 9, /* Contains program counter */ + CYCLE_REGNUM = 10, + EXR_REGNUM = 11, + INST_REGNUM = 12, + TICK_REGNUM = 13, + MACH_REGNUM = 14, + MACL_REGNUM = 15, + SBR_REGNUM = 16, + VBR_REGNUM = 17, + + ZERO_REGNUM = 18 +}; + +enum h8_typecodes { + OP_NULL, + OP_REG, /* Register direct. */ + OP_LOWREG, /* Special reg syntax for "bra". */ + OP_DISP, /* Register indirect w/displacement. */ + /* Note: h8300, h8300h, and h8300s permit only pre-decr and post-incr. */ + OP_PREDEC, /* Register indirect w/pre-decrement. */ + OP_POSTDEC, /* Register indirect w/post-decrement. */ + OP_PREINC, /* Register indirect w/pre-increment. */ + OP_POSTINC, /* Register indirect w/post-increment. */ + OP_PCREL, /* PC Relative. */ + OP_MEM, /* Absolute memory address. */ + OP_CCR, /* Condition Code Register. */ + OP_IMM, /* Immediate value. */ + /*OP_ABS*/ /* Un-used (duplicates op_mem?). */ + OP_EXR, /* EXtended control Register. */ + OP_SBR, /* Vector Base Register. */ + OP_VBR, /* Short-address Base Register. */ + OP_MACH, /* Multiply Accumulator - high. */ + OP_MACL, /* Multiply Accumulator - low. */ + /* FIXME: memory indirect? */ + OP_INDEXB, /* Byte index mode */ + OP_INDEXW, /* Word index mode */ + OP_INDEXL /* Long index mode */ +}; + +#include "sim-basics.h" + +/* Define sim_cia. */ +typedef unsigned32 sim_cia; + +#include "sim-base.h" + +/* Structure used to describe addressing */ + +typedef struct +{ + int type; + int reg; + int literal; +} ea_type; + +/* Struct for instruction decoder. */ +typedef struct +{ + ea_type src; + ea_type dst; + ea_type op3; + int opcode; + int next_pc; + int oldpc; + int cycles; +#ifdef DEBUG + struct h8_opcode *op; +#endif +} decoded_inst; + +struct _sim_cpu { + unsigned int regs[20]; /* 8 GR's plus ZERO, SBR, and VBR. */ + unsigned int pc; + + int macS; /* MAC Saturating mode */ + int macV; /* MAC Overflow */ + int macN; /* MAC Negative */ + int macZ; /* MAC Zero */ + + int delayed_branch; + char **command_line; /* Pointer to command line arguments. */ + + unsigned char *memory; + unsigned char *eightbit; + int mask; + + sim_cpu_base base; +}; + +/* The sim_state struct. */ +struct sim_state { + struct _sim_cpu *cpu; + unsigned int sim_cache_size; + decoded_inst *sim_cache; + unsigned short *cache_idx; + unsigned long memory_size; + int cache_top; + int compiles; +#ifdef ADEBUG + int stats[O_LAST]; +#endif + sim_state_base base; +}; + +/* The current state of the processor; registers, memory, etc. */ + +#define CIA_GET(CPU) (cpu_get_pc (CPU)) +#define CIA_SET(CPU, VAL) (cpu_set_pc ((CPU), (VAL))) +#define STATE_CPU(SD, N) ((SD)->cpu) /* Single Processor. */ +#define cpu_set_pc(CPU, VAL) (((CPU)->pc) = (VAL)) +#define cpu_get_pc(CPU) (((CPU)->pc)) + +/* Magic numbers used to distinguish an exit from a breakpoint. */ +#define LIBC_EXIT_MAGIC1 0xdead +#define LIBC_EXIT_MAGIC2 0xbeef +/* Local version of macros for decoding exit status. + (included here rather than try to find target version of wait.h) +*/ +#define SIM_WIFEXITED(V) (((V) & 0xff) == 0) +#define SIM_WIFSTOPPED(V) (!SIM_WIFEXITED (V)) +#define SIM_WEXITSTATUS(V) (((V) >> 8) & 0xff) +#define SIM_WSTOPSIG(V) ((V) & 0x7f) + +#endif /* SIM_MAIN_H */ diff --git a/sim/m32r/cpu2.c b/sim/m32r/cpu2.c new file mode 100644 index 0000000..1749880 --- /dev/null +++ b/sim/m32r/cpu2.c @@ -0,0 +1,197 @@ +/* Misc. support for CPU family m32r2f. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. + +This file is part of the GNU simulators. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +*/ + +#define WANT_CPU m32r2f +#define WANT_CPU_M32R2F + +#include "sim-main.h" +#include "cgen-ops.h" + +/* Get the value of h-pc. */ + +USI +m32r2f_h_pc_get (SIM_CPU *current_cpu) +{ + return CPU (h_pc); +} + +/* Set a value for h-pc. */ + +void +m32r2f_h_pc_set (SIM_CPU *current_cpu, USI newval) +{ + CPU (h_pc) = newval; +} + +/* Get the value of h-gr. */ + +SI +m32r2f_h_gr_get (SIM_CPU *current_cpu, UINT regno) +{ + return CPU (h_gr[regno]); +} + +/* Set a value for h-gr. */ + +void +m32r2f_h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval) +{ + CPU (h_gr[regno]) = newval; +} + +/* Get the value of h-cr. */ + +USI +m32r2f_h_cr_get (SIM_CPU *current_cpu, UINT regno) +{ + return GET_H_CR (regno); +} + +/* Set a value for h-cr. */ + +void +m32r2f_h_cr_set (SIM_CPU *current_cpu, UINT regno, USI newval) +{ + SET_H_CR (regno, newval); +} + +/* Get the value of h-accum. */ + +DI +m32r2f_h_accum_get (SIM_CPU *current_cpu) +{ + return GET_H_ACCUM (); +} + +/* Set a value for h-accum. */ + +void +m32r2f_h_accum_set (SIM_CPU *current_cpu, DI newval) +{ + SET_H_ACCUM (newval); +} + +/* Get the value of h-accums. */ + +DI +m32r2f_h_accums_get (SIM_CPU *current_cpu, UINT regno) +{ + return GET_H_ACCUMS (regno); +} + +/* Set a value for h-accums. */ + +void +m32r2f_h_accums_set (SIM_CPU *current_cpu, UINT regno, DI newval) +{ + SET_H_ACCUMS (regno, newval); +} + +/* Get the value of h-cond. */ + +BI +m32r2f_h_cond_get (SIM_CPU *current_cpu) +{ + return CPU (h_cond); +} + +/* Set a value for h-cond. */ + +void +m32r2f_h_cond_set (SIM_CPU *current_cpu, BI newval) +{ + CPU (h_cond) = newval; +} + +/* Get the value of h-psw. */ + +UQI +m32r2f_h_psw_get (SIM_CPU *current_cpu) +{ + return GET_H_PSW (); +} + +/* Set a value for h-psw. */ + +void +m32r2f_h_psw_set (SIM_CPU *current_cpu, UQI newval) +{ + SET_H_PSW (newval); +} + +/* Get the value of h-bpsw. */ + +UQI +m32r2f_h_bpsw_get (SIM_CPU *current_cpu) +{ + return CPU (h_bpsw); +} + +/* Set a value for h-bpsw. */ + +void +m32r2f_h_bpsw_set (SIM_CPU *current_cpu, UQI newval) +{ + CPU (h_bpsw) = newval; +} + +/* Get the value of h-bbpsw. */ + +UQI +m32r2f_h_bbpsw_get (SIM_CPU *current_cpu) +{ + return CPU (h_bbpsw); +} + +/* Set a value for h-bbpsw. */ + +void +m32r2f_h_bbpsw_set (SIM_CPU *current_cpu, UQI newval) +{ + CPU (h_bbpsw) = newval; +} + +/* Get the value of h-lock. */ + +BI +m32r2f_h_lock_get (SIM_CPU *current_cpu) +{ + return CPU (h_lock); +} + +/* Set a value for h-lock. */ + +void +m32r2f_h_lock_set (SIM_CPU *current_cpu, BI newval) +{ + CPU (h_lock) = newval; +} + +/* Record trace results for INSN. */ + +void +m32r2f_record_trace_results (SIM_CPU *current_cpu, CGEN_INSN *insn, + int *indices, TRACE_RECORD *tr) +{ +} diff --git a/sim/m32r/cpu2.h b/sim/m32r/cpu2.h new file mode 100644 index 0000000..8ae49e4 --- /dev/null +++ b/sim/m32r/cpu2.h @@ -0,0 +1,1046 @@ +/* CPU family header for m32r2f. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. + +This file is part of the GNU simulators. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +*/ + +#ifndef CPU_M32R2F_H +#define CPU_M32R2F_H + +/* Maximum number of instructions that are fetched at a time. + This is for LIW type instructions sets (e.g. m32r). */ +#define MAX_LIW_INSNS 2 + +/* Maximum number of instructions that can be executed in parallel. */ +#define MAX_PARALLEL_INSNS 2 + +/* CPU state information. */ +typedef struct { + /* Hardware elements. */ + struct { + /* program counter */ + USI h_pc; +#define GET_H_PC() CPU (h_pc) +#define SET_H_PC(x) (CPU (h_pc) = (x)) + /* general registers */ + SI h_gr[16]; +#define GET_H_GR(a1) CPU (h_gr)[a1] +#define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x)) + /* control registers */ + USI h_cr[16]; +#define GET_H_CR(index) m32r2f_h_cr_get_handler (current_cpu, index) +#define SET_H_CR(index, x) \ +do { \ +m32r2f_h_cr_set_handler (current_cpu, (index), (x));\ +;} while (0) + /* accumulator */ + DI h_accum; +#define GET_H_ACCUM() m32r2f_h_accum_get_handler (current_cpu) +#define SET_H_ACCUM(x) \ +do { \ +m32r2f_h_accum_set_handler (current_cpu, (x));\ +;} while (0) + /* accumulators */ + DI h_accums[2]; +#define GET_H_ACCUMS(index) m32r2f_h_accums_get_handler (current_cpu, index) +#define SET_H_ACCUMS(index, x) \ +do { \ +m32r2f_h_accums_set_handler (current_cpu, (index), (x));\ +;} while (0) + /* condition bit */ + BI h_cond; +#define GET_H_COND() CPU (h_cond) +#define SET_H_COND(x) (CPU (h_cond) = (x)) + /* psw part of psw */ + UQI h_psw; +#define GET_H_PSW() m32r2f_h_psw_get_handler (current_cpu) +#define SET_H_PSW(x) \ +do { \ +m32r2f_h_psw_set_handler (current_cpu, (x));\ +;} while (0) + /* backup psw */ + UQI h_bpsw; +#define GET_H_BPSW() CPU (h_bpsw) +#define SET_H_BPSW(x) (CPU (h_bpsw) = (x)) + /* backup bpsw */ + UQI h_bbpsw; +#define GET_H_BBPSW() CPU (h_bbpsw) +#define SET_H_BBPSW(x) (CPU (h_bbpsw) = (x)) + /* lock */ + BI h_lock; +#define GET_H_LOCK() CPU (h_lock) +#define SET_H_LOCK(x) (CPU (h_lock) = (x)) + } hardware; +#define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware) +} M32R2F_CPU_DATA; + +/* Cover fns for register access. */ +USI m32r2f_h_pc_get (SIM_CPU *); +void m32r2f_h_pc_set (SIM_CPU *, USI); +SI m32r2f_h_gr_get (SIM_CPU *, UINT); +void m32r2f_h_gr_set (SIM_CPU *, UINT, SI); +USI m32r2f_h_cr_get (SIM_CPU *, UINT); +void m32r2f_h_cr_set (SIM_CPU *, UINT, USI); +DI m32r2f_h_accum_get (SIM_CPU *); +void m32r2f_h_accum_set (SIM_CPU *, DI); +DI m32r2f_h_accums_get (SIM_CPU *, UINT); +void m32r2f_h_accums_set (SIM_CPU *, UINT, DI); +BI m32r2f_h_cond_get (SIM_CPU *); +void m32r2f_h_cond_set (SIM_CPU *, BI); +UQI m32r2f_h_psw_get (SIM_CPU *); +void m32r2f_h_psw_set (SIM_CPU *, UQI); +UQI m32r2f_h_bpsw_get (SIM_CPU *); +void m32r2f_h_bpsw_set (SIM_CPU *, UQI); +UQI m32r2f_h_bbpsw_get (SIM_CPU *); +void m32r2f_h_bbpsw_set (SIM_CPU *, UQI); +BI m32r2f_h_lock_get (SIM_CPU *); +void m32r2f_h_lock_set (SIM_CPU *, BI); + +/* These must be hand-written. */ +extern CPUREG_FETCH_FN m32r2f_fetch_register; +extern CPUREG_STORE_FN m32r2f_store_register; + +typedef struct { + int empty; +} MODEL_M32R2_DATA; + +/* Instruction argument buffer. */ + +union sem_fields { + struct { /* no operands */ + int empty; + } fmt_empty; + struct { /* */ + UINT f_uimm8; + } sfmt_clrpsw; + struct { /* */ + UINT f_uimm4; + } sfmt_trap; + struct { /* */ + IADDR i_disp24; + unsigned char out_h_gr_SI_14; + } sfmt_bl24; + struct { /* */ + IADDR i_disp8; + unsigned char out_h_gr_SI_14; + } sfmt_bl8; + struct { /* */ + SI f_imm1; + UINT f_accd; + UINT f_accs; + } sfmt_rac_dsi; + struct { /* */ + SI* i_dr; + UINT f_hi16; + UINT f_r1; + unsigned char out_dr; + } sfmt_seth; + struct { /* */ + SI* i_src1; + UINT f_accs; + UINT f_r1; + unsigned char in_src1; + } sfmt_mvtachi_a; + struct { /* */ + SI* i_dr; + UINT f_accs; + UINT f_r1; + unsigned char out_dr; + } sfmt_mvfachi_a; + struct { /* */ + ADDR i_uimm24; + SI* i_dr; + UINT f_r1; + unsigned char out_dr; + } sfmt_ld24; + struct { /* */ + SI* i_sr; + UINT f_r2; + unsigned char in_sr; + unsigned char out_h_gr_SI_14; + } sfmt_jl; + struct { /* */ + SI* i_sr; + INT f_simm16; + UINT f_r2; + UINT f_uimm3; + unsigned char in_sr; + } sfmt_bset; + struct { /* */ + SI* i_dr; + UINT f_r1; + UINT f_uimm5; + unsigned char in_dr; + unsigned char out_dr; + } sfmt_slli; + struct { /* */ + SI* i_dr; + INT f_simm8; + UINT f_r1; + unsigned char in_dr; + unsigned char out_dr; + } sfmt_addi; + struct { /* */ + SI* i_src1; + SI* i_src2; + UINT f_r1; + UINT f_r2; + unsigned char in_src1; + unsigned char in_src2; + unsigned char out_src2; + } sfmt_st_plus; + struct { /* */ + SI* i_src1; + SI* i_src2; + INT f_simm16; + UINT f_r1; + UINT f_r2; + unsigned char in_src1; + unsigned char in_src2; + } sfmt_st_d; + struct { /* */ + SI* i_src1; + SI* i_src2; + UINT f_acc; + UINT f_r1; + UINT f_r2; + unsigned char in_src1; + unsigned char in_src2; + } sfmt_machi_a; + struct { /* */ + SI* i_dr; + SI* i_sr; + UINT f_r1; + UINT f_r2; + unsigned char in_sr; + unsigned char out_dr; + unsigned char out_sr; + } sfmt_ld_plus; + struct { /* */ + IADDR i_disp16; + SI* i_src1; + SI* i_src2; + UINT f_r1; + UINT f_r2; + unsigned char in_src1; + unsigned char in_src2; + } sfmt_beq; + struct { /* */ + SI* i_dr; + SI* i_sr; + UINT f_r1; + UINT f_r2; + UINT f_uimm16; + unsigned char in_sr; + unsigned char out_dr; + } sfmt_and3; + struct { /* */ + SI* i_dr; + SI* i_sr; + INT f_simm16; + UINT f_r1; + UINT f_r2; + unsigned char in_sr; + unsigned char out_dr; + } sfmt_add3; + struct { /* */ + SI* i_dr; + SI* i_sr; + UINT f_r1; + UINT f_r2; + unsigned char in_dr; + unsigned char in_sr; + unsigned char out_dr; + } sfmt_add; +#if WITH_SCACHE_PBB + /* Writeback handler. */ + struct { + /* Pointer to argbuf entry for insn whose results need writing back. */ + const struct argbuf *abuf; + } write; + /* x-before handler */ + struct { + /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/ + int first_p; + } before; + /* x-after handler */ + struct { + int empty; + } after; + /* This entry is used to terminate each pbb. */ + struct { + /* Number of insns in pbb. */ + int insn_count; + /* Next pbb to execute. */ + SCACHE *next; + SCACHE *branch_target; + } chain; +#endif +}; + +/* The ARGBUF struct. */ +struct argbuf { + /* These are the baseclass definitions. */ + IADDR addr; + const IDESC *idesc; + char trace_p; + char profile_p; + /* ??? Temporary hack for skip insns. */ + char skip_count; + char unused; + /* cpu specific data follows */ + union sem semantic; + int written; + union sem_fields fields; +}; + +/* A cached insn. + + ??? SCACHE used to contain more than just argbuf. We could delete the + type entirely and always just use ARGBUF, but for future concerns and as + a level of abstraction it is left in. */ + +struct scache { + struct argbuf argbuf; +}; + +/* Macros to simplify extraction, reading and semantic code. + These define and assign the local vars that contain the insn's fields. */ + +#define EXTRACT_IFMT_EMPTY_VARS \ + unsigned int length; +#define EXTRACT_IFMT_EMPTY_CODE \ + length = 0; \ + +#define EXTRACT_IFMT_ADD_VARS \ + UINT f_op1; \ + UINT f_r1; \ + UINT f_op2; \ + UINT f_r2; \ + unsigned int length; +#define EXTRACT_IFMT_ADD_CODE \ + length = 2; \ + f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \ + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \ + f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \ + f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \ + +#define EXTRACT_IFMT_ADD3_VARS \ + UINT f_op1; \ + UINT f_r1; \ + UINT f_op2; \ + UINT f_r2; \ + INT f_simm16; \ + unsigned int length; +#define EXTRACT_IFMT_ADD3_CODE \ + length = 4; \ + f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \ + f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \ + f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \ + f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \ + f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \ + +#define EXTRACT_IFMT_AND3_VARS \ + UINT f_op1; \ + UINT f_r1; \ + UINT f_op2; \ + UINT f_r2; \ + UINT f_uimm16; \ + unsigned int length; +#define EXTRACT_IFMT_AND3_CODE \ + length = 4; \ + f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \ + f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \ + f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \ + f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \ + f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \ + +#define EXTRACT_IFMT_OR3_VARS \ + UINT f_op1; \ + UINT f_r1; \ + UINT f_op2; \ + UINT f_r2; \ + UINT f_uimm16; \ + unsigned int length; +#define EXTRACT_IFMT_OR3_CODE \ + length = 4; \ + f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \ + f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \ + f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \ + f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \ + f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \ + +#define EXTRACT_IFMT_ADDI_VARS \ + UINT f_op1; \ + UINT f_r1; \ + INT f_simm8; \ + unsigned int length; +#define EXTRACT_IFMT_ADDI_CODE \ + length = 2; \ + f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \ + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \ + f_simm8 = EXTRACT_MSB0_INT (insn, 16, 8, 8); \ + +#define EXTRACT_IFMT_ADDV3_VARS \ + UINT f_op1; \ + UINT f_r1; \ + UINT f_op2; \ + UINT f_r2; \ + INT f_simm16; \ + unsigned int length; +#define EXTRACT_IFMT_ADDV3_CODE \ + length = 4; \ + f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \ + f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \ + f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \ + f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \ + f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \ + +#define EXTRACT_IFMT_BC8_VARS \ + UINT f_op1; \ + UINT f_r1; \ + SI f_disp8; \ + unsigned int length; +#define EXTRACT_IFMT_BC8_CODE \ + length = 2; \ + f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \ + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \ + f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \ + +#define EXTRACT_IFMT_BC24_VARS \ + UINT f_op1; \ + UINT f_r1; \ + SI f_disp24; \ + unsigned int length; +#define EXTRACT_IFMT_BC24_CODE \ + length = 4; \ + f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \ + f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \ + f_disp24 = ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc)); \ + +#define EXTRACT_IFMT_BEQ_VARS \ + UINT f_op1; \ + UINT f_r1; \ + UINT f_op2; \ + UINT f_r2; \ + SI f_disp16; \ + unsigned int length; +#define EXTRACT_IFMT_BEQ_CODE \ + length = 4; \ + f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \ + f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \ + f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \ + f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \ + f_disp16 = ((((EXTRACT_MSB0_INT (insn, 32, 16, 16)) << (2))) + (pc)); \ + +#define EXTRACT_IFMT_BEQZ_VARS \ + UINT f_op1; \ + UINT f_r1; \ + UINT f_op2; \ + UINT f_r2; \ + SI f_disp16; \ + unsigned int length; +#define EXTRACT_IFMT_BEQZ_CODE \ + length = 4; \ + f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \ + f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \ + f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \ + f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \ + f_disp16 = ((((EXTRACT_MSB0_INT (insn, 32, 16, 16)) << (2))) + (pc)); \ + +#define EXTRACT_IFMT_CMP_VARS \ + UINT f_op1; \ + UINT f_r1; \ + UINT f_op2; \ + UINT f_r2; \ + unsigned int length; +#define EXTRACT_IFMT_CMP_CODE \ + length = 2; \ + f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \ + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \ + f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \ + f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \ + +#define EXTRACT_IFMT_CMPI_VARS \ + UINT f_op1; \ + UINT f_r1; \ + UINT f_op2; \ + UINT f_r2; \ + INT f_simm16; \ + unsigned int length; +#define EXTRACT_IFMT_CMPI_CODE \ + length = 4; \ + f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \ + f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \ + f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \ + f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \ + f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \ + +#define EXTRACT_IFMT_CMPZ_VARS \ + UINT f_op1; \ + UINT f_r1; \ + UINT f_op2; \ + UINT f_r2; \ + unsigned int length; +#define EXTRACT_IFMT_CMPZ_CODE \ + length = 2; \ + f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \ + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \ + f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \ + f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \ + +#define EXTRACT_IFMT_DIV_VARS \ + UINT f_op1; \ + UINT f_r1; \ + UINT f_op2; \ + UINT f_r2; \ + INT f_simm16; \ + unsigned int length; +#define EXTRACT_IFMT_DIV_CODE \ + length = 4; \ + f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \ + f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \ + f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \ + f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \ + f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \ + +#define EXTRACT_IFMT_JC_VARS \ + UINT f_op1; \ + UINT f_r1; \ + UINT f_op2; \ + UINT f_r2; \ + unsigned int length; +#define EXTRACT_IFMT_JC_CODE \ + length = 2; \ + f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \ + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \ + f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \ + f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \ + +#define EXTRACT_IFMT_LD24_VARS \ + UINT f_op1; \ + UINT f_r1; \ + UINT f_uimm24; \ + unsigned int length; +#define EXTRACT_IFMT_LD24_CODE \ + length = 4; \ + f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \ + f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \ + f_uimm24 = EXTRACT_MSB0_UINT (insn, 32, 8, 24); \ + +#define EXTRACT_IFMT_LDI16_VARS \ + UINT f_op1; \ + UINT f_r1; \ + UINT f_op2; \ + UINT f_r2; \ + INT f_simm16; \ + unsigned int length; +#define EXTRACT_IFMT_LDI16_CODE \ + length = 4; \ + f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \ + f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \ + f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \ + f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \ + f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \ + +#define EXTRACT_IFMT_MACHI_A_VARS \ + UINT f_op1; \ + UINT f_r1; \ + UINT f_acc; \ + UINT f_op23; \ + UINT f_r2; \ + unsigned int length; +#define EXTRACT_IFMT_MACHI_A_CODE \ + length = 2; \ + f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \ + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \ + f_acc = EXTRACT_MSB0_UINT (insn, 16, 8, 1); \ + f_op23 = EXTRACT_MSB0_UINT (insn, 16, 9, 3); \ + f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \ + +#define EXTRACT_IFMT_MVFACHI_A_VARS \ + UINT f_op1; \ + UINT f_r1; \ + UINT f_op2; \ + UINT f_accs; \ + UINT f_op3; \ + unsigned int length; +#define EXTRACT_IFMT_MVFACHI_A_CODE \ + length = 2; \ + f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \ + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \ + f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \ + f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2); \ + f_op3 = EXTRACT_MSB0_UINT (insn, 16, 14, 2); \ + +#define EXTRACT_IFMT_MVFC_VARS \ + UINT f_op1; \ + UINT f_r1; \ + UINT f_op2; \ + UINT f_r2; \ + unsigned int length; +#define EXTRACT_IFMT_MVFC_CODE \ + length = 2; \ + f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \ + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \ + f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \ + f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \ + +#define EXTRACT_IFMT_MVTACHI_A_VARS \ + UINT f_op1; \ + UINT f_r1; \ + UINT f_op2; \ + UINT f_accs; \ + UINT f_op3; \ + unsigned int length; +#define EXTRACT_IFMT_MVTACHI_A_CODE \ + length = 2; \ + f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \ + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \ + f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \ + f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2); \ + f_op3 = EXTRACT_MSB0_UINT (insn, 16, 14, 2); \ + +#define EXTRACT_IFMT_MVTC_VARS \ + UINT f_op1; \ + UINT f_r1; \ + UINT f_op2; \ + UINT f_r2; \ + unsigned int length; +#define EXTRACT_IFMT_MVTC_CODE \ + length = 2; \ + f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \ + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \ + f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \ + f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \ + +#define EXTRACT_IFMT_NOP_VARS \ + UINT f_op1; \ + UINT f_r1; \ + UINT f_op2; \ + UINT f_r2; \ + unsigned int length; +#define EXTRACT_IFMT_NOP_CODE \ + length = 2; \ + f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \ + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \ + f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \ + f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \ + +#define EXTRACT_IFMT_RAC_DSI_VARS \ + UINT f_op1; \ + UINT f_accd; \ + UINT f_bits67; \ + UINT f_op2; \ + UINT f_accs; \ + UINT f_bit14; \ + SI f_imm1; \ + unsigned int length; +#define EXTRACT_IFMT_RAC_DSI_CODE \ + length = 2; \ + f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \ + f_accd = EXTRACT_MSB0_UINT (insn, 16, 4, 2); \ + f_bits67 = EXTRACT_MSB0_UINT (insn, 16, 6, 2); \ + f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \ + f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2); \ + f_bit14 = EXTRACT_MSB0_UINT (insn, 16, 14, 1); \ + f_imm1 = ((EXTRACT_MSB0_UINT (insn, 16, 15, 1)) + (1)); \ + +#define EXTRACT_IFMT_SETH_VARS \ + UINT f_op1; \ + UINT f_r1; \ + UINT f_op2; \ + UINT f_r2; \ + UINT f_hi16; \ + unsigned int length; +#define EXTRACT_IFMT_SETH_CODE \ + length = 4; \ + f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \ + f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \ + f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \ + f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \ + f_hi16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \ + +#define EXTRACT_IFMT_SLLI_VARS \ + UINT f_op1; \ + UINT f_r1; \ + UINT f_shift_op2; \ + UINT f_uimm5; \ + unsigned int length; +#define EXTRACT_IFMT_SLLI_CODE \ + length = 2; \ + f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \ + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \ + f_shift_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 3); \ + f_uimm5 = EXTRACT_MSB0_UINT (insn, 16, 11, 5); \ + +#define EXTRACT_IFMT_ST_D_VARS \ + UINT f_op1; \ + UINT f_r1; \ + UINT f_op2; \ + UINT f_r2; \ + INT f_simm16; \ + unsigned int length; +#define EXTRACT_IFMT_ST_D_CODE \ + length = 4; \ + f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \ + f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \ + f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \ + f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \ + f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \ + +#define EXTRACT_IFMT_TRAP_VARS \ + UINT f_op1; \ + UINT f_r1; \ + UINT f_op2; \ + UINT f_uimm4; \ + unsigned int length; +#define EXTRACT_IFMT_TRAP_CODE \ + length = 2; \ + f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \ + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \ + f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \ + f_uimm4 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \ + +#define EXTRACT_IFMT_SATB_VARS \ + UINT f_op1; \ + UINT f_r1; \ + UINT f_op2; \ + UINT f_r2; \ + UINT f_uimm16; \ + unsigned int length; +#define EXTRACT_IFMT_SATB_CODE \ + length = 4; \ + f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \ + f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \ + f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \ + f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \ + f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \ + +#define EXTRACT_IFMT_CLRPSW_VARS \ + UINT f_op1; \ + UINT f_r1; \ + UINT f_uimm8; \ + unsigned int length; +#define EXTRACT_IFMT_CLRPSW_CODE \ + length = 2; \ + f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \ + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \ + f_uimm8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); \ + +#define EXTRACT_IFMT_BSET_VARS \ + UINT f_op1; \ + UINT f_bit4; \ + UINT f_uimm3; \ + UINT f_op2; \ + UINT f_r2; \ + INT f_simm16; \ + unsigned int length; +#define EXTRACT_IFMT_BSET_CODE \ + length = 4; \ + f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \ + f_bit4 = EXTRACT_MSB0_UINT (insn, 32, 4, 1); \ + f_uimm3 = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \ + f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \ + f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \ + f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \ + +#define EXTRACT_IFMT_BTST_VARS \ + UINT f_op1; \ + UINT f_bit4; \ + UINT f_uimm3; \ + UINT f_op2; \ + UINT f_r2; \ + unsigned int length; +#define EXTRACT_IFMT_BTST_CODE \ + length = 2; \ + f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \ + f_bit4 = EXTRACT_MSB0_UINT (insn, 16, 4, 1); \ + f_uimm3 = EXTRACT_MSB0_UINT (insn, 16, 5, 3); \ + f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \ + f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \ + +/* Queued output values of an instruction. */ + +struct parexec { + union { + struct { /* empty sformat for unspecified field list */ + int empty; + } sfmt_empty; + struct { /* e.g. add $dr,$sr */ + SI dr; + } sfmt_add; + struct { /* e.g. add3 $dr,$sr,$hash$slo16 */ + SI dr; + } sfmt_add3; + struct { /* e.g. and3 $dr,$sr,$uimm16 */ + SI dr; + } sfmt_and3; + struct { /* e.g. or3 $dr,$sr,$hash$ulo16 */ + SI dr; + } sfmt_or3; + struct { /* e.g. addi $dr,$simm8 */ + SI dr; + } sfmt_addi; + struct { /* e.g. addv $dr,$sr */ + BI condbit; + SI dr; + } sfmt_addv; + struct { /* e.g. addv3 $dr,$sr,$simm16 */ + BI condbit; + SI dr; + } sfmt_addv3; + struct { /* e.g. addx $dr,$sr */ + BI condbit; + SI dr; + } sfmt_addx; + struct { /* e.g. bc.s $disp8 */ + USI pc; + } sfmt_bc8; + struct { /* e.g. bc.l $disp24 */ + USI pc; + } sfmt_bc24; + struct { /* e.g. beq $src1,$src2,$disp16 */ + USI pc; + } sfmt_beq; + struct { /* e.g. beqz $src2,$disp16 */ + USI pc; + } sfmt_beqz; + struct { /* e.g. bl.s $disp8 */ + SI h_gr_SI_14; + USI pc; + } sfmt_bl8; + struct { /* e.g. bl.l $disp24 */ + SI h_gr_SI_14; + USI pc; + } sfmt_bl24; + struct { /* e.g. bcl.s $disp8 */ + SI h_gr_SI_14; + USI pc; + } sfmt_bcl8; + struct { /* e.g. bcl.l $disp24 */ + SI h_gr_SI_14; + USI pc; + } sfmt_bcl24; + struct { /* e.g. bra.s $disp8 */ + USI pc; + } sfmt_bra8; + struct { /* e.g. bra.l $disp24 */ + USI pc; + } sfmt_bra24; + struct { /* e.g. cmp $src1,$src2 */ + BI condbit; + } sfmt_cmp; + struct { /* e.g. cmpi $src2,$simm16 */ + BI condbit; + } sfmt_cmpi; + struct { /* e.g. cmpz $src2 */ + BI condbit; + } sfmt_cmpz; + struct { /* e.g. div $dr,$sr */ + SI dr; + } sfmt_div; + struct { /* e.g. jc $sr */ + USI pc; + } sfmt_jc; + struct { /* e.g. jl $sr */ + SI h_gr_SI_14; + USI pc; + } sfmt_jl; + struct { /* e.g. jmp $sr */ + USI pc; + } sfmt_jmp; + struct { /* e.g. ld $dr,@$sr */ + SI dr; + } sfmt_ld; + struct { /* e.g. ld $dr,@($slo16,$sr) */ + SI dr; + } sfmt_ld_d; + struct { /* e.g. ldb $dr,@$sr */ + SI dr; + } sfmt_ldb; + struct { /* e.g. ldb $dr,@($slo16,$sr) */ + SI dr; + } sfmt_ldb_d; + struct { /* e.g. ldh $dr,@$sr */ + SI dr; + } sfmt_ldh; + struct { /* e.g. ldh $dr,@($slo16,$sr) */ + SI dr; + } sfmt_ldh_d; + struct { /* e.g. ld $dr,@$sr+ */ + SI dr; + SI sr; + } sfmt_ld_plus; + struct { /* e.g. ld24 $dr,$uimm24 */ + SI dr; + } sfmt_ld24; + struct { /* e.g. ldi8 $dr,$simm8 */ + SI dr; + } sfmt_ldi8; + struct { /* e.g. ldi16 $dr,$hash$slo16 */ + SI dr; + } sfmt_ldi16; + struct { /* e.g. lock $dr,@$sr */ + SI dr; + BI h_lock_BI; + } sfmt_lock; + struct { /* e.g. machi $src1,$src2,$acc */ + DI acc; + } sfmt_machi_a; + struct { /* e.g. mulhi $src1,$src2,$acc */ + DI acc; + } sfmt_mulhi_a; + struct { /* e.g. mv $dr,$sr */ + SI dr; + } sfmt_mv; + struct { /* e.g. mvfachi $dr,$accs */ + SI dr; + } sfmt_mvfachi_a; + struct { /* e.g. mvfc $dr,$scr */ + SI dr; + } sfmt_mvfc; + struct { /* e.g. mvtachi $src1,$accs */ + DI accs; + } sfmt_mvtachi_a; + struct { /* e.g. mvtc $sr,$dcr */ + USI dcr; + } sfmt_mvtc; + struct { /* e.g. nop */ + int empty; + } sfmt_nop; + struct { /* e.g. rac $accd,$accs,$imm1 */ + DI accd; + } sfmt_rac_dsi; + struct { /* e.g. rte */ + UQI h_bpsw_UQI; + USI h_cr_USI_6; + UQI h_psw_UQI; + USI pc; + } sfmt_rte; + struct { /* e.g. seth $dr,$hash$hi16 */ + SI dr; + } sfmt_seth; + struct { /* e.g. sll3 $dr,$sr,$simm16 */ + SI dr; + } sfmt_sll3; + struct { /* e.g. slli $dr,$uimm5 */ + SI dr; + } sfmt_slli; + struct { /* e.g. st $src1,@$src2 */ + SI h_memory_SI_src2; + USI h_memory_SI_src2_idx; + } sfmt_st; + struct { /* e.g. st $src1,@($slo16,$src2) */ + SI h_memory_SI_add__DFLT_src2_slo16; + USI h_memory_SI_add__DFLT_src2_slo16_idx; + } sfmt_st_d; + struct { /* e.g. stb $src1,@$src2 */ + QI h_memory_QI_src2; + USI h_memory_QI_src2_idx; + } sfmt_stb; + struct { /* e.g. stb $src1,@($slo16,$src2) */ + QI h_memory_QI_add__DFLT_src2_slo16; + USI h_memory_QI_add__DFLT_src2_slo16_idx; + } sfmt_stb_d; + struct { /* e.g. sth $src1,@$src2 */ + HI h_memory_HI_src2; + USI h_memory_HI_src2_idx; + } sfmt_sth; + struct { /* e.g. sth $src1,@($slo16,$src2) */ + HI h_memory_HI_add__DFLT_src2_slo16; + USI h_memory_HI_add__DFLT_src2_slo16_idx; + } sfmt_sth_d; + struct { /* e.g. st $src1,@+$src2 */ + SI h_memory_SI_new_src2; + USI h_memory_SI_new_src2_idx; + SI src2; + } sfmt_st_plus; + struct { /* e.g. sth $src1,@$src2+ */ + HI h_memory_HI_new_src2; + USI h_memory_HI_new_src2_idx; + SI src2; + } sfmt_sth_plus; + struct { /* e.g. stb $src1,@$src2+ */ + QI h_memory_QI_new_src2; + USI h_memory_QI_new_src2_idx; + SI src2; + } sfmt_stb_plus; + struct { /* e.g. trap $uimm4 */ + UQI h_bbpsw_UQI; + UQI h_bpsw_UQI; + USI h_cr_USI_14; + USI h_cr_USI_6; + UQI h_psw_UQI; + SI pc; + } sfmt_trap; + struct { /* e.g. unlock $src1,@$src2 */ + BI h_lock_BI; + SI h_memory_SI_src2; + USI h_memory_SI_src2_idx; + } sfmt_unlock; + struct { /* e.g. satb $dr,$sr */ + SI dr; + } sfmt_satb; + struct { /* e.g. sat $dr,$sr */ + SI dr; + } sfmt_sat; + struct { /* e.g. sadd */ + DI h_accums_DI_0; + } sfmt_sadd; + struct { /* e.g. macwu1 $src1,$src2 */ + DI h_accums_DI_1; + } sfmt_macwu1; + struct { /* e.g. msblo $src1,$src2 */ + DI accum; + } sfmt_msblo; + struct { /* e.g. mulwu1 $src1,$src2 */ + DI h_accums_DI_1; + } sfmt_mulwu1; + struct { /* e.g. sc */ + int empty; + } sfmt_sc; + struct { /* e.g. clrpsw $uimm8 */ + USI h_cr_USI_0; + } sfmt_clrpsw; + struct { /* e.g. setpsw $uimm8 */ + USI h_cr_USI_0; + } sfmt_setpsw; + struct { /* e.g. bset $uimm3,@($slo16,$sr) */ + QI h_memory_QI_add__DFLT_sr_slo16; + USI h_memory_QI_add__DFLT_sr_slo16_idx; + } sfmt_bset; + struct { /* e.g. btst $uimm3,$sr */ + BI condbit; + } sfmt_btst; + } operands; + /* For conditionally written operands, bitmask of which ones were. */ + int written; +}; + +/* Collection of various things for the trace handler to use. */ + +typedef struct trace_record { + IADDR pc; + /* FIXME:wip */ +} TRACE_RECORD; + +#endif /* CPU_M32R2F_H */ diff --git a/sim/m32r/decode2.c b/sim/m32r/decode2.c new file mode 100644 index 0000000..d98db5e --- /dev/null +++ b/sim/m32r/decode2.c @@ -0,0 +1,2609 @@ +/* Simulator instruction decoder for m32r2f. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. + +This file is part of the GNU simulators. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +*/ + +#define WANT_CPU m32r2f +#define WANT_CPU_M32R2F + +#include "sim-main.h" +#include "sim-assert.h" + +/* Insn can't be executed in parallel. + Or is that "do NOt Pass to Air defense Radar"? :-) */ +#define NOPAR (-1) + +/* The instruction descriptor array. + This is computed at runtime. Space for it is not malloc'd to save a + teensy bit of cpu in the decoder. Moving it to malloc space is trivial + but won't be done until necessary (we don't currently support the runtime + addition of instructions nor an SMP machine with different cpus). */ +static IDESC m32r2f_insn_data[M32R2F_INSN__MAX]; + +/* Commas between elements are contained in the macros. + Some of these are conditionally compiled out. */ + +static const struct insn_sem m32r2f_insn_sem[] = +{ + { VIRTUAL_INSN_X_INVALID, M32R2F_INSN_X_INVALID, M32R2F_SFMT_EMPTY, NOPAR, NOPAR }, + { VIRTUAL_INSN_X_AFTER, M32R2F_INSN_X_AFTER, M32R2F_SFMT_EMPTY, NOPAR, NOPAR }, + { VIRTUAL_INSN_X_BEFORE, M32R2F_INSN_X_BEFORE, M32R2F_SFMT_EMPTY, NOPAR, NOPAR }, + { VIRTUAL_INSN_X_CTI_CHAIN, M32R2F_INSN_X_CTI_CHAIN, M32R2F_SFMT_EMPTY, NOPAR, NOPAR }, + { VIRTUAL_INSN_X_CHAIN, M32R2F_INSN_X_CHAIN, M32R2F_SFMT_EMPTY, NOPAR, NOPAR }, + { VIRTUAL_INSN_X_BEGIN, M32R2F_INSN_X_BEGIN, M32R2F_SFMT_EMPTY, NOPAR, NOPAR }, + { M32R_INSN_ADD, M32R2F_INSN_ADD, M32R2F_SFMT_ADD, M32R2F_INSN_PAR_ADD, M32R2F_INSN_WRITE_ADD }, + { M32R_INSN_ADD3, M32R2F_INSN_ADD3, M32R2F_SFMT_ADD3, NOPAR, NOPAR }, + { M32R_INSN_AND, M32R2F_INSN_AND, M32R2F_SFMT_ADD, M32R2F_INSN_PAR_AND, M32R2F_INSN_WRITE_AND }, + { M32R_INSN_AND3, M32R2F_INSN_AND3, M32R2F_SFMT_AND3, NOPAR, NOPAR }, + { M32R_INSN_OR, M32R2F_INSN_OR, M32R2F_SFMT_ADD, M32R2F_INSN_PAR_OR, M32R2F_INSN_WRITE_OR }, + { M32R_INSN_OR3, M32R2F_INSN_OR3, M32R2F_SFMT_OR3, NOPAR, NOPAR }, + { M32R_INSN_XOR, M32R2F_INSN_XOR, M32R2F_SFMT_ADD, M32R2F_INSN_PAR_XOR, M32R2F_INSN_WRITE_XOR }, + { M32R_INSN_XOR3, M32R2F_INSN_XOR3, M32R2F_SFMT_AND3, NOPAR, NOPAR }, + { M32R_INSN_ADDI, M32R2F_INSN_ADDI, M32R2F_SFMT_ADDI, M32R2F_INSN_PAR_ADDI, M32R2F_INSN_WRITE_ADDI }, + { M32R_INSN_ADDV, M32R2F_INSN_ADDV, M32R2F_SFMT_ADDV, M32R2F_INSN_PAR_ADDV, M32R2F_INSN_WRITE_ADDV }, + { M32R_INSN_ADDV3, M32R2F_INSN_ADDV3, M32R2F_SFMT_ADDV3, NOPAR, NOPAR }, + { M32R_INSN_ADDX, M32R2F_INSN_ADDX, M32R2F_SFMT_ADDX, M32R2F_INSN_PAR_ADDX, M32R2F_INSN_WRITE_ADDX }, + { M32R_INSN_BC8, M32R2F_INSN_BC8, M32R2F_SFMT_BC8, M32R2F_INSN_PAR_BC8, M32R2F_INSN_WRITE_BC8 }, + { M32R_INSN_BC24, M32R2F_INSN_BC24, M32R2F_SFMT_BC24, NOPAR, NOPAR }, + { M32R_INSN_BEQ, M32R2F_INSN_BEQ, M32R2F_SFMT_BEQ, NOPAR, NOPAR }, + { M32R_INSN_BEQZ, M32R2F_INSN_BEQZ, M32R2F_SFMT_BEQZ, NOPAR, NOPAR }, + { M32R_INSN_BGEZ, M32R2F_INSN_BGEZ, M32R2F_SFMT_BEQZ, NOPAR, NOPAR }, + { M32R_INSN_BGTZ, M32R2F_INSN_BGTZ, M32R2F_SFMT_BEQZ, NOPAR, NOPAR }, + { M32R_INSN_BLEZ, M32R2F_INSN_BLEZ, M32R2F_SFMT_BEQZ, NOPAR, NOPAR }, + { M32R_INSN_BLTZ, M32R2F_INSN_BLTZ, M32R2F_SFMT_BEQZ, NOPAR, NOPAR }, + { M32R_INSN_BNEZ, M32R2F_INSN_BNEZ, M32R2F_SFMT_BEQZ, NOPAR, NOPAR }, + { M32R_INSN_BL8, M32R2F_INSN_BL8, M32R2F_SFMT_BL8, M32R2F_INSN_PAR_BL8, M32R2F_INSN_WRITE_BL8 }, + { M32R_INSN_BL24, M32R2F_INSN_BL24, M32R2F_SFMT_BL24, NOPAR, NOPAR }, + { M32R_INSN_BCL8, M32R2F_INSN_BCL8, M32R2F_SFMT_BCL8, M32R2F_INSN_PAR_BCL8, M32R2F_INSN_WRITE_BCL8 }, + { M32R_INSN_BCL24, M32R2F_INSN_BCL24, M32R2F_SFMT_BCL24, NOPAR, NOPAR }, + { M32R_INSN_BNC8, M32R2F_INSN_BNC8, M32R2F_SFMT_BC8, M32R2F_INSN_PAR_BNC8, M32R2F_INSN_WRITE_BNC8 }, + { M32R_INSN_BNC24, M32R2F_INSN_BNC24, M32R2F_SFMT_BC24, NOPAR, NOPAR }, + { M32R_INSN_BNE, M32R2F_INSN_BNE, M32R2F_SFMT_BEQ, NOPAR, NOPAR }, + { M32R_INSN_BRA8, M32R2F_INSN_BRA8, M32R2F_SFMT_BRA8, M32R2F_INSN_PAR_BRA8, M32R2F_INSN_WRITE_BRA8 }, + { M32R_INSN_BRA24, M32R2F_INSN_BRA24, M32R2F_SFMT_BRA24, NOPAR, NOPAR }, + { M32R_INSN_BNCL8, M32R2F_INSN_BNCL8, M32R2F_SFMT_BCL8, M32R2F_INSN_PAR_BNCL8, M32R2F_INSN_WRITE_BNCL8 }, + { M32R_INSN_BNCL24, M32R2F_INSN_BNCL24, M32R2F_SFMT_BCL24, NOPAR, NOPAR }, + { M32R_INSN_CMP, M32R2F_INSN_CMP, M32R2F_SFMT_CMP, M32R2F_INSN_PAR_CMP, M32R2F_INSN_WRITE_CMP }, + { M32R_INSN_CMPI, M32R2F_INSN_CMPI, M32R2F_SFMT_CMPI, NOPAR, NOPAR }, + { M32R_INSN_CMPU, M32R2F_INSN_CMPU, M32R2F_SFMT_CMP, M32R2F_INSN_PAR_CMPU, M32R2F_INSN_WRITE_CMPU }, + { M32R_INSN_CMPUI, M32R2F_INSN_CMPUI, M32R2F_SFMT_CMPI, NOPAR, NOPAR }, + { M32R_INSN_CMPEQ, M32R2F_INSN_CMPEQ, M32R2F_SFMT_CMP, M32R2F_INSN_PAR_CMPEQ, M32R2F_INSN_WRITE_CMPEQ }, + { M32R_INSN_CMPZ, M32R2F_INSN_CMPZ, M32R2F_SFMT_CMPZ, M32R2F_INSN_PAR_CMPZ, M32R2F_INSN_WRITE_CMPZ }, + { M32R_INSN_DIV, M32R2F_INSN_DIV, M32R2F_SFMT_DIV, NOPAR, NOPAR }, + { M32R_INSN_DIVU, M32R2F_INSN_DIVU, M32R2F_SFMT_DIV, NOPAR, NOPAR }, + { M32R_INSN_REM, M32R2F_INSN_REM, M32R2F_SFMT_DIV, NOPAR, NOPAR }, + { M32R_INSN_REMU, M32R2F_INSN_REMU, M32R2F_SFMT_DIV, NOPAR, NOPAR }, + { M32R_INSN_REMH, M32R2F_INSN_REMH, M32R2F_SFMT_DIV, NOPAR, NOPAR }, + { M32R_INSN_REMUH, M32R2F_INSN_REMUH, M32R2F_SFMT_DIV, NOPAR, NOPAR }, + { M32R_INSN_REMB, M32R2F_INSN_REMB, M32R2F_SFMT_DIV, NOPAR, NOPAR }, + { M32R_INSN_REMUB, M32R2F_INSN_REMUB, M32R2F_SFMT_DIV, NOPAR, NOPAR }, + { M32R_INSN_DIVUH, M32R2F_INSN_DIVUH, M32R2F_SFMT_DIV, NOPAR, NOPAR }, + { M32R_INSN_DIVB, M32R2F_INSN_DIVB, M32R2F_SFMT_DIV, NOPAR, NOPAR }, + { M32R_INSN_DIVUB, M32R2F_INSN_DIVUB, M32R2F_SFMT_DIV, NOPAR, NOPAR }, + { M32R_INSN_DIVH, M32R2F_INSN_DIVH, M32R2F_SFMT_DIV, NOPAR, NOPAR }, + { M32R_INSN_JC, M32R2F_INSN_JC, M32R2F_SFMT_JC, M32R2F_INSN_PAR_JC, M32R2F_INSN_WRITE_JC }, + { M32R_INSN_JNC, M32R2F_INSN_JNC, M32R2F_SFMT_JC, M32R2F_INSN_PAR_JNC, M32R2F_INSN_WRITE_JNC }, + { M32R_INSN_JL, M32R2F_INSN_JL, M32R2F_SFMT_JL, M32R2F_INSN_PAR_JL, M32R2F_INSN_WRITE_JL }, + { M32R_INSN_JMP, M32R2F_INSN_JMP, M32R2F_SFMT_JMP, M32R2F_INSN_PAR_JMP, M32R2F_INSN_WRITE_JMP }, + { M32R_INSN_LD, M32R2F_INSN_LD, M32R2F_SFMT_LD, M32R2F_INSN_PAR_LD, M32R2F_INSN_WRITE_LD }, + { M32R_INSN_LD_D, M32R2F_INSN_LD_D, M32R2F_SFMT_LD_D, NOPAR, NOPAR }, + { M32R_INSN_LDB, M32R2F_INSN_LDB, M32R2F_SFMT_LDB, M32R2F_INSN_PAR_LDB, M32R2F_INSN_WRITE_LDB }, + { M32R_INSN_LDB_D, M32R2F_INSN_LDB_D, M32R2F_SFMT_LDB_D, NOPAR, NOPAR }, + { M32R_INSN_LDH, M32R2F_INSN_LDH, M32R2F_SFMT_LDH, M32R2F_INSN_PAR_LDH, M32R2F_INSN_WRITE_LDH }, + { M32R_INSN_LDH_D, M32R2F_INSN_LDH_D, M32R2F_SFMT_LDH_D, NOPAR, NOPAR }, + { M32R_INSN_LDUB, M32R2F_INSN_LDUB, M32R2F_SFMT_LDB, M32R2F_INSN_PAR_LDUB, M32R2F_INSN_WRITE_LDUB }, + { M32R_INSN_LDUB_D, M32R2F_INSN_LDUB_D, M32R2F_SFMT_LDB_D, NOPAR, NOPAR }, + { M32R_INSN_LDUH, M32R2F_INSN_LDUH, M32R2F_SFMT_LDH, M32R2F_INSN_PAR_LDUH, M32R2F_INSN_WRITE_LDUH }, + { M32R_INSN_LDUH_D, M32R2F_INSN_LDUH_D, M32R2F_SFMT_LDH_D, NOPAR, NOPAR }, + { M32R_INSN_LD_PLUS, M32R2F_INSN_LD_PLUS, M32R2F_SFMT_LD_PLUS, M32R2F_INSN_PAR_LD_PLUS, M32R2F_INSN_WRITE_LD_PLUS }, + { M32R_INSN_LD24, M32R2F_INSN_LD24, M32R2F_SFMT_LD24, NOPAR, NOPAR }, + { M32R_INSN_LDI8, M32R2F_INSN_LDI8, M32R2F_SFMT_LDI8, M32R2F_INSN_PAR_LDI8, M32R2F_INSN_WRITE_LDI8 }, + { M32R_INSN_LDI16, M32R2F_INSN_LDI16, M32R2F_SFMT_LDI16, NOPAR, NOPAR }, + { M32R_INSN_LOCK, M32R2F_INSN_LOCK, M32R2F_SFMT_LOCK, M32R2F_INSN_PAR_LOCK, M32R2F_INSN_WRITE_LOCK }, + { M32R_INSN_MACHI_A, M32R2F_INSN_MACHI_A, M32R2F_SFMT_MACHI_A, M32R2F_INSN_PAR_MACHI_A, M32R2F_INSN_WRITE_MACHI_A }, + { M32R_INSN_MACLO_A, M32R2F_INSN_MACLO_A, M32R2F_SFMT_MACHI_A, M32R2F_INSN_PAR_MACLO_A, M32R2F_INSN_WRITE_MACLO_A }, + { M32R_INSN_MACWHI_A, M32R2F_INSN_MACWHI_A, M32R2F_SFMT_MACHI_A, M32R2F_INSN_PAR_MACWHI_A, M32R2F_INSN_WRITE_MACWHI_A }, + { M32R_INSN_MACWLO_A, M32R2F_INSN_MACWLO_A, M32R2F_SFMT_MACHI_A, M32R2F_INSN_PAR_MACWLO_A, M32R2F_INSN_WRITE_MACWLO_A }, + { M32R_INSN_MUL, M32R2F_INSN_MUL, M32R2F_SFMT_ADD, M32R2F_INSN_PAR_MUL, M32R2F_INSN_WRITE_MUL }, + { M32R_INSN_MULHI_A, M32R2F_INSN_MULHI_A, M32R2F_SFMT_MULHI_A, M32R2F_INSN_PAR_MULHI_A, M32R2F_INSN_WRITE_MULHI_A }, + { M32R_INSN_MULLO_A, M32R2F_INSN_MULLO_A, M32R2F_SFMT_MULHI_A, M32R2F_INSN_PAR_MULLO_A, M32R2F_INSN_WRITE_MULLO_A }, + { M32R_INSN_MULWHI_A, M32R2F_INSN_MULWHI_A, M32R2F_SFMT_MULHI_A, M32R2F_INSN_PAR_MULWHI_A, M32R2F_INSN_WRITE_MULWHI_A }, + { M32R_INSN_MULWLO_A, M32R2F_INSN_MULWLO_A, M32R2F_SFMT_MULHI_A, M32R2F_INSN_PAR_MULWLO_A, M32R2F_INSN_WRITE_MULWLO_A }, + { M32R_INSN_MV, M32R2F_INSN_MV, M32R2F_SFMT_MV, M32R2F_INSN_PAR_MV, M32R2F_INSN_WRITE_MV }, + { M32R_INSN_MVFACHI_A, M32R2F_INSN_MVFACHI_A, M32R2F_SFMT_MVFACHI_A, M32R2F_INSN_PAR_MVFACHI_A, M32R2F_INSN_WRITE_MVFACHI_A }, + { M32R_INSN_MVFACLO_A, M32R2F_INSN_MVFACLO_A, M32R2F_SFMT_MVFACHI_A, M32R2F_INSN_PAR_MVFACLO_A, M32R2F_INSN_WRITE_MVFACLO_A }, + { M32R_INSN_MVFACMI_A, M32R2F_INSN_MVFACMI_A, M32R2F_SFMT_MVFACHI_A, M32R2F_INSN_PAR_MVFACMI_A, M32R2F_INSN_WRITE_MVFACMI_A }, + { M32R_INSN_MVFC, M32R2F_INSN_MVFC, M32R2F_SFMT_MVFC, M32R2F_INSN_PAR_MVFC, M32R2F_INSN_WRITE_MVFC }, + { M32R_INSN_MVTACHI_A, M32R2F_INSN_MVTACHI_A, M32R2F_SFMT_MVTACHI_A, M32R2F_INSN_PAR_MVTACHI_A, M32R2F_INSN_WRITE_MVTACHI_A }, + { M32R_INSN_MVTACLO_A, M32R2F_INSN_MVTACLO_A, M32R2F_SFMT_MVTACHI_A, M32R2F_INSN_PAR_MVTACLO_A, M32R2F_INSN_WRITE_MVTACLO_A }, + { M32R_INSN_MVTC, M32R2F_INSN_MVTC, M32R2F_SFMT_MVTC, M32R2F_INSN_PAR_MVTC, M32R2F_INSN_WRITE_MVTC }, + { M32R_INSN_NEG, M32R2F_INSN_NEG, M32R2F_SFMT_MV, M32R2F_INSN_PAR_NEG, M32R2F_INSN_WRITE_NEG }, + { M32R_INSN_NOP, M32R2F_INSN_NOP, M32R2F_SFMT_NOP, M32R2F_INSN_PAR_NOP, M32R2F_INSN_WRITE_NOP }, + { M32R_INSN_NOT, M32R2F_INSN_NOT, M32R2F_SFMT_MV, M32R2F_INSN_PAR_NOT, M32R2F_INSN_WRITE_NOT }, + { M32R_INSN_RAC_DSI, M32R2F_INSN_RAC_DSI, M32R2F_SFMT_RAC_DSI, M32R2F_INSN_PAR_RAC_DSI, M32R2F_INSN_WRITE_RAC_DSI }, + { M32R_INSN_RACH_DSI, M32R2F_INSN_RACH_DSI, M32R2F_SFMT_RAC_DSI, M32R2F_INSN_PAR_RACH_DSI, M32R2F_INSN_WRITE_RACH_DSI }, + { M32R_INSN_RTE, M32R2F_INSN_RTE, M32R2F_SFMT_RTE, M32R2F_INSN_PAR_RTE, M32R2F_INSN_WRITE_RTE }, + { M32R_INSN_SETH, M32R2F_INSN_SETH, M32R2F_SFMT_SETH, NOPAR, NOPAR }, + { M32R_INSN_SLL, M32R2F_INSN_SLL, M32R2F_SFMT_ADD, M32R2F_INSN_PAR_SLL, M32R2F_INSN_WRITE_SLL }, + { M32R_INSN_SLL3, M32R2F_INSN_SLL3, M32R2F_SFMT_SLL3, NOPAR, NOPAR }, + { M32R_INSN_SLLI, M32R2F_INSN_SLLI, M32R2F_SFMT_SLLI, M32R2F_INSN_PAR_SLLI, M32R2F_INSN_WRITE_SLLI }, + { M32R_INSN_SRA, M32R2F_INSN_SRA, M32R2F_SFMT_ADD, M32R2F_INSN_PAR_SRA, M32R2F_INSN_WRITE_SRA }, + { M32R_INSN_SRA3, M32R2F_INSN_SRA3, M32R2F_SFMT_SLL3, NOPAR, NOPAR }, + { M32R_INSN_SRAI, M32R2F_INSN_SRAI, M32R2F_SFMT_SLLI, M32R2F_INSN_PAR_SRAI, M32R2F_INSN_WRITE_SRAI }, + { M32R_INSN_SRL, M32R2F_INSN_SRL, M32R2F_SFMT_ADD, M32R2F_INSN_PAR_SRL, M32R2F_INSN_WRITE_SRL }, + { M32R_INSN_SRL3, M32R2F_INSN_SRL3, M32R2F_SFMT_SLL3, NOPAR, NOPAR }, + { M32R_INSN_SRLI, M32R2F_INSN_SRLI, M32R2F_SFMT_SLLI, M32R2F_INSN_PAR_SRLI, M32R2F_INSN_WRITE_SRLI }, + { M32R_INSN_ST, M32R2F_INSN_ST, M32R2F_SFMT_ST, M32R2F_INSN_PAR_ST, M32R2F_INSN_WRITE_ST }, + { M32R_INSN_ST_D, M32R2F_INSN_ST_D, M32R2F_SFMT_ST_D, NOPAR, NOPAR }, + { M32R_INSN_STB, M32R2F_INSN_STB, M32R2F_SFMT_STB, M32R2F_INSN_PAR_STB, M32R2F_INSN_WRITE_STB }, + { M32R_INSN_STB_D, M32R2F_INSN_STB_D, M32R2F_SFMT_STB_D, NOPAR, NOPAR }, + { M32R_INSN_STH, M32R2F_INSN_STH, M32R2F_SFMT_STH, M32R2F_INSN_PAR_STH, M32R2F_INSN_WRITE_STH }, + { M32R_INSN_STH_D, M32R2F_INSN_STH_D, M32R2F_SFMT_STH_D, NOPAR, NOPAR }, + { M32R_INSN_ST_PLUS, M32R2F_INSN_ST_PLUS, M32R2F_SFMT_ST_PLUS, M32R2F_INSN_PAR_ST_PLUS, M32R2F_INSN_WRITE_ST_PLUS }, + { M32R_INSN_STH_PLUS, M32R2F_INSN_STH_PLUS, M32R2F_SFMT_STH_PLUS, M32R2F_INSN_PAR_STH_PLUS, M32R2F_INSN_WRITE_STH_PLUS }, + { M32R_INSN_STB_PLUS, M32R2F_INSN_STB_PLUS, M32R2F_SFMT_STB_PLUS, M32R2F_INSN_PAR_STB_PLUS, M32R2F_INSN_WRITE_STB_PLUS }, + { M32R_INSN_ST_MINUS, M32R2F_INSN_ST_MINUS, M32R2F_SFMT_ST_PLUS, M32R2F_INSN_PAR_ST_MINUS, M32R2F_INSN_WRITE_ST_MINUS }, + { M32R_INSN_SUB, M32R2F_INSN_SUB, M32R2F_SFMT_ADD, M32R2F_INSN_PAR_SUB, M32R2F_INSN_WRITE_SUB }, + { M32R_INSN_SUBV, M32R2F_INSN_SUBV, M32R2F_SFMT_ADDV, M32R2F_INSN_PAR_SUBV, M32R2F_INSN_WRITE_SUBV }, + { M32R_INSN_SUBX, M32R2F_INSN_SUBX, M32R2F_SFMT_ADDX, M32R2F_INSN_PAR_SUBX, M32R2F_INSN_WRITE_SUBX }, + { M32R_INSN_TRAP, M32R2F_INSN_TRAP, M32R2F_SFMT_TRAP, M32R2F_INSN_PAR_TRAP, M32R2F_INSN_WRITE_TRAP }, + { M32R_INSN_UNLOCK, M32R2F_INSN_UNLOCK, M32R2F_SFMT_UNLOCK, M32R2F_INSN_PAR_UNLOCK, M32R2F_INSN_WRITE_UNLOCK }, + { M32R_INSN_SATB, M32R2F_INSN_SATB, M32R2F_SFMT_SATB, NOPAR, NOPAR }, + { M32R_INSN_SATH, M32R2F_INSN_SATH, M32R2F_SFMT_SATB, NOPAR, NOPAR }, + { M32R_INSN_SAT, M32R2F_INSN_SAT, M32R2F_SFMT_SAT, NOPAR, NOPAR }, + { M32R_INSN_PCMPBZ, M32R2F_INSN_PCMPBZ, M32R2F_SFMT_CMPZ, M32R2F_INSN_PAR_PCMPBZ, M32R2F_INSN_WRITE_PCMPBZ }, + { M32R_INSN_SADD, M32R2F_INSN_SADD, M32R2F_SFMT_SADD, M32R2F_INSN_PAR_SADD, M32R2F_INSN_WRITE_SADD }, + { M32R_INSN_MACWU1, M32R2F_INSN_MACWU1, M32R2F_SFMT_MACWU1, M32R2F_INSN_PAR_MACWU1, M32R2F_INSN_WRITE_MACWU1 }, + { M32R_INSN_MSBLO, M32R2F_INSN_MSBLO, M32R2F_SFMT_MSBLO, M32R2F_INSN_PAR_MSBLO, M32R2F_INSN_WRITE_MSBLO }, + { M32R_INSN_MULWU1, M32R2F_INSN_MULWU1, M32R2F_SFMT_MULWU1, M32R2F_INSN_PAR_MULWU1, M32R2F_INSN_WRITE_MULWU1 }, + { M32R_INSN_MACLH1, M32R2F_INSN_MACLH1, M32R2F_SFMT_MACWU1, M32R2F_INSN_PAR_MACLH1, M32R2F_INSN_WRITE_MACLH1 }, + { M32R_INSN_SC, M32R2F_INSN_SC, M32R2F_SFMT_SC, M32R2F_INSN_PAR_SC, M32R2F_INSN_WRITE_SC }, + { M32R_INSN_SNC, M32R2F_INSN_SNC, M32R2F_SFMT_SC, M32R2F_INSN_PAR_SNC, M32R2F_INSN_WRITE_SNC }, + { M32R_INSN_CLRPSW, M32R2F_INSN_CLRPSW, M32R2F_SFMT_CLRPSW, M32R2F_INSN_PAR_CLRPSW, M32R2F_INSN_WRITE_CLRPSW }, + { M32R_INSN_SETPSW, M32R2F_INSN_SETPSW, M32R2F_SFMT_SETPSW, M32R2F_INSN_PAR_SETPSW, M32R2F_INSN_WRITE_SETPSW }, + { M32R_INSN_BSET, M32R2F_INSN_BSET, M32R2F_SFMT_BSET, NOPAR, NOPAR }, + { M32R_INSN_BCLR, M32R2F_INSN_BCLR, M32R2F_SFMT_BSET, NOPAR, NOPAR }, + { M32R_INSN_BTST, M32R2F_INSN_BTST, M32R2F_SFMT_BTST, M32R2F_INSN_PAR_BTST, M32R2F_INSN_WRITE_BTST }, +}; + +static const struct insn_sem m32r2f_insn_sem_invalid = { + VIRTUAL_INSN_X_INVALID, M32R2F_INSN_X_INVALID, M32R2F_SFMT_EMPTY, NOPAR, NOPAR +}; + +/* Initialize an IDESC from the compile-time computable parts. */ + +static INLINE void +init_idesc (SIM_CPU *cpu, IDESC *id, const struct insn_sem *t) +{ + const CGEN_INSN *insn_table = CGEN_CPU_INSN_TABLE (CPU_CPU_DESC (cpu))->init_entries; + + id->num = t->index; + id->sfmt = t->sfmt; + if ((int) t->type <= 0) + id->idata = & cgen_virtual_insn_table[- (int) t->type]; + else + id->idata = & insn_table[t->type]; + id->attrs = CGEN_INSN_ATTRS (id->idata); + /* Oh my god, a magic number. */ + id->length = CGEN_INSN_BITSIZE (id->idata) / 8; + +#if WITH_PROFILE_MODEL_P + id->timing = & MODEL_TIMING (CPU_MODEL (cpu)) [t->index]; + { + SIM_DESC sd = CPU_STATE (cpu); + SIM_ASSERT (t->index == id->timing->num); + } +#endif + + /* Semantic pointers are initialized elsewhere. */ +} + +/* Initialize the instruction descriptor table. */ + +void +m32r2f_init_idesc_table (SIM_CPU *cpu) +{ + IDESC *id,*tabend; + const struct insn_sem *t,*tend; + int tabsize = M32R2F_INSN__MAX; + IDESC *table = m32r2f_insn_data; + + memset (table, 0, tabsize * sizeof (IDESC)); + + /* First set all entries to the `invalid insn'. */ + t = & m32r2f_insn_sem_invalid; + for (id = table, tabend = table + tabsize; id < tabend; ++id) + init_idesc (cpu, id, t); + + /* Now fill in the values for the chosen cpu. */ + for (t = m32r2f_insn_sem, tend = t + sizeof (m32r2f_insn_sem) / sizeof (*t); + t != tend; ++t) + { + init_idesc (cpu, & table[t->index], t); + if (t->par_index != NOPAR) + { + init_idesc (cpu, &table[t->par_index], t); + table[t->index].par_idesc = &table[t->par_index]; + } + if (t->par_index != NOPAR) + { + init_idesc (cpu, &table[t->write_index], t); + table[t->par_index].par_idesc = &table[t->write_index]; + } + } + + /* Link the IDESC table into the cpu. */ + CPU_IDESC (cpu) = table; +} + +/* Given an instruction, return a pointer to its IDESC entry. */ + +const IDESC * +m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, + CGEN_INSN_INT base_insn, CGEN_INSN_INT entire_insn, + ARGBUF *abuf) +{ + /* Result of decoder. */ + M32R2F_INSN_TYPE itype; + + { + CGEN_INSN_INT insn = base_insn; + + { + unsigned int val = (((insn >> 8) & (15 << 4)) | ((insn >> 4) & (15 << 0))); + switch (val) + { + case 0 : itype = M32R2F_INSN_SUBV; goto extract_sfmt_addv; + case 1 : itype = M32R2F_INSN_SUBX; goto extract_sfmt_addx; + case 2 : itype = M32R2F_INSN_SUB; goto extract_sfmt_add; + case 3 : itype = M32R2F_INSN_NEG; goto extract_sfmt_mv; + case 4 : itype = M32R2F_INSN_CMP; goto extract_sfmt_cmp; + case 5 : itype = M32R2F_INSN_CMPU; goto extract_sfmt_cmp; + case 6 : itype = M32R2F_INSN_CMPEQ; goto extract_sfmt_cmp; + case 7 : + { + unsigned int val = (((insn >> 8) & (3 << 0))); + switch (val) + { + case 0 : itype = M32R2F_INSN_CMPZ; goto extract_sfmt_cmpz; + case 3 : itype = M32R2F_INSN_PCMPBZ; goto extract_sfmt_cmpz; + default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 8 : itype = M32R2F_INSN_ADDV; goto extract_sfmt_addv; + case 9 : itype = M32R2F_INSN_ADDX; goto extract_sfmt_addx; + case 10 : itype = M32R2F_INSN_ADD; goto extract_sfmt_add; + case 11 : itype = M32R2F_INSN_NOT; goto extract_sfmt_mv; + case 12 : itype = M32R2F_INSN_AND; goto extract_sfmt_add; + case 13 : itype = M32R2F_INSN_XOR; goto extract_sfmt_add; + case 14 : itype = M32R2F_INSN_OR; goto extract_sfmt_add; + case 15 : itype = M32R2F_INSN_BTST; goto extract_sfmt_btst; + case 16 : itype = M32R2F_INSN_SRL; goto extract_sfmt_add; + case 18 : itype = M32R2F_INSN_SRA; goto extract_sfmt_add; + case 20 : itype = M32R2F_INSN_SLL; goto extract_sfmt_add; + case 22 : itype = M32R2F_INSN_MUL; goto extract_sfmt_add; + case 24 : itype = M32R2F_INSN_MV; goto extract_sfmt_mv; + case 25 : itype = M32R2F_INSN_MVFC; goto extract_sfmt_mvfc; + case 26 : itype = M32R2F_INSN_MVTC; goto extract_sfmt_mvtc; + case 28 : + { + unsigned int val = (((insn >> 8) & (3 << 0))); + switch (val) + { + case 0 : itype = M32R2F_INSN_JC; goto extract_sfmt_jc; + case 1 : itype = M32R2F_INSN_JNC; goto extract_sfmt_jc; + case 2 : itype = M32R2F_INSN_JL; goto extract_sfmt_jl; + case 3 : itype = M32R2F_INSN_JMP; goto extract_sfmt_jmp; + default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 29 : itype = M32R2F_INSN_RTE; goto extract_sfmt_rte; + case 31 : itype = M32R2F_INSN_TRAP; goto extract_sfmt_trap; + case 32 : itype = M32R2F_INSN_STB; goto extract_sfmt_stb; + case 33 : itype = M32R2F_INSN_STB_PLUS; goto extract_sfmt_stb_plus; + case 34 : itype = M32R2F_INSN_STH; goto extract_sfmt_sth; + case 35 : itype = M32R2F_INSN_STH_PLUS; goto extract_sfmt_sth_plus; + case 36 : itype = M32R2F_INSN_ST; goto extract_sfmt_st; + case 37 : itype = M32R2F_INSN_UNLOCK; goto extract_sfmt_unlock; + case 38 : itype = M32R2F_INSN_ST_PLUS; goto extract_sfmt_st_plus; + case 39 : itype = M32R2F_INSN_ST_MINUS; goto extract_sfmt_st_plus; + case 40 : itype = M32R2F_INSN_LDB; goto extract_sfmt_ldb; + case 41 : itype = M32R2F_INSN_LDUB; goto extract_sfmt_ldb; + case 42 : itype = M32R2F_INSN_LDH; goto extract_sfmt_ldh; + case 43 : itype = M32R2F_INSN_LDUH; goto extract_sfmt_ldh; + case 44 : itype = M32R2F_INSN_LD; goto extract_sfmt_ld; + case 45 : itype = M32R2F_INSN_LOCK; goto extract_sfmt_lock; + case 46 : itype = M32R2F_INSN_LD_PLUS; goto extract_sfmt_ld_plus; + case 48 : /* fall through */ + case 56 : itype = M32R2F_INSN_MULHI_A; goto extract_sfmt_mulhi_a; + case 49 : /* fall through */ + case 57 : itype = M32R2F_INSN_MULLO_A; goto extract_sfmt_mulhi_a; + case 50 : /* fall through */ + case 58 : itype = M32R2F_INSN_MULWHI_A; goto extract_sfmt_mulhi_a; + case 51 : /* fall through */ + case 59 : itype = M32R2F_INSN_MULWLO_A; goto extract_sfmt_mulhi_a; + case 52 : /* fall through */ + case 60 : itype = M32R2F_INSN_MACHI_A; goto extract_sfmt_machi_a; + case 53 : /* fall through */ + case 61 : itype = M32R2F_INSN_MACLO_A; goto extract_sfmt_machi_a; + case 54 : /* fall through */ + case 62 : itype = M32R2F_INSN_MACWHI_A; goto extract_sfmt_machi_a; + case 55 : /* fall through */ + case 63 : itype = M32R2F_INSN_MACWLO_A; goto extract_sfmt_machi_a; + case 64 : /* fall through */ + case 65 : /* fall through */ + case 66 : /* fall through */ + case 67 : /* fall through */ + case 68 : /* fall through */ + case 69 : /* fall through */ + case 70 : /* fall through */ + case 71 : /* fall through */ + case 72 : /* fall through */ + case 73 : /* fall through */ + case 74 : /* fall through */ + case 75 : /* fall through */ + case 76 : /* fall through */ + case 77 : /* fall through */ + case 78 : /* fall through */ + case 79 : itype = M32R2F_INSN_ADDI; goto extract_sfmt_addi; + case 80 : /* fall through */ + case 81 : itype = M32R2F_INSN_SRLI; goto extract_sfmt_slli; + case 82 : /* fall through */ + case 83 : itype = M32R2F_INSN_SRAI; goto extract_sfmt_slli; + case 84 : /* fall through */ + case 85 : itype = M32R2F_INSN_SLLI; goto extract_sfmt_slli; + case 87 : + { + unsigned int val = (((insn >> 0) & (1 << 0))); + switch (val) + { + case 0 : itype = M32R2F_INSN_MVTACHI_A; goto extract_sfmt_mvtachi_a; + case 1 : itype = M32R2F_INSN_MVTACLO_A; goto extract_sfmt_mvtachi_a; + default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 88 : itype = M32R2F_INSN_RACH_DSI; goto extract_sfmt_rac_dsi; + case 89 : itype = M32R2F_INSN_RAC_DSI; goto extract_sfmt_rac_dsi; + case 90 : itype = M32R2F_INSN_MULWU1; goto extract_sfmt_mulwu1; + case 91 : itype = M32R2F_INSN_MACWU1; goto extract_sfmt_macwu1; + case 92 : itype = M32R2F_INSN_MACLH1; goto extract_sfmt_macwu1; + case 93 : itype = M32R2F_INSN_MSBLO; goto extract_sfmt_msblo; + case 94 : itype = M32R2F_INSN_SADD; goto extract_sfmt_sadd; + case 95 : + { + unsigned int val = (((insn >> 0) & (3 << 0))); + switch (val) + { + case 0 : itype = M32R2F_INSN_MVFACHI_A; goto extract_sfmt_mvfachi_a; + case 1 : itype = M32R2F_INSN_MVFACLO_A; goto extract_sfmt_mvfachi_a; + case 2 : itype = M32R2F_INSN_MVFACMI_A; goto extract_sfmt_mvfachi_a; + default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 96 : /* fall through */ + case 97 : /* fall through */ + case 98 : /* fall through */ + case 99 : /* fall through */ + case 100 : /* fall through */ + case 101 : /* fall through */ + case 102 : /* fall through */ + case 103 : /* fall through */ + case 104 : /* fall through */ + case 105 : /* fall through */ + case 106 : /* fall through */ + case 107 : /* fall through */ + case 108 : /* fall through */ + case 109 : /* fall through */ + case 110 : /* fall through */ + case 111 : itype = M32R2F_INSN_LDI8; goto extract_sfmt_ldi8; + case 112 : + { + unsigned int val = (((insn >> 7) & (15 << 1)) | ((insn >> 0) & (1 << 0))); + switch (val) + { + case 0 : itype = M32R2F_INSN_NOP; goto extract_sfmt_nop; + case 2 : /* fall through */ + case 3 : itype = M32R2F_INSN_SETPSW; goto extract_sfmt_setpsw; + case 4 : /* fall through */ + case 5 : itype = M32R2F_INSN_CLRPSW; goto extract_sfmt_clrpsw; + case 9 : itype = M32R2F_INSN_SC; goto extract_sfmt_sc; + case 11 : itype = M32R2F_INSN_SNC; goto extract_sfmt_sc; + case 16 : /* fall through */ + case 17 : itype = M32R2F_INSN_BCL8; goto extract_sfmt_bcl8; + case 18 : /* fall through */ + case 19 : itype = M32R2F_INSN_BNCL8; goto extract_sfmt_bcl8; + case 24 : /* fall through */ + case 25 : itype = M32R2F_INSN_BC8; goto extract_sfmt_bc8; + case 26 : /* fall through */ + case 27 : itype = M32R2F_INSN_BNC8; goto extract_sfmt_bc8; + case 28 : /* fall through */ + case 29 : itype = M32R2F_INSN_BL8; goto extract_sfmt_bl8; + case 30 : /* fall through */ + case 31 : itype = M32R2F_INSN_BRA8; goto extract_sfmt_bra8; + default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 113 : /* fall through */ + case 114 : /* fall through */ + case 115 : /* fall through */ + case 116 : /* fall through */ + case 117 : /* fall through */ + case 118 : /* fall through */ + case 119 : /* fall through */ + case 120 : /* fall through */ + case 121 : /* fall through */ + case 122 : /* fall through */ + case 123 : /* fall through */ + case 124 : /* fall through */ + case 125 : /* fall through */ + case 126 : /* fall through */ + case 127 : + { + unsigned int val = (((insn >> 8) & (15 << 0))); + switch (val) + { + case 1 : itype = M32R2F_INSN_SETPSW; goto extract_sfmt_setpsw; + case 2 : itype = M32R2F_INSN_CLRPSW; goto extract_sfmt_clrpsw; + case 8 : itype = M32R2F_INSN_BCL8; goto extract_sfmt_bcl8; + case 9 : itype = M32R2F_INSN_BNCL8; goto extract_sfmt_bcl8; + case 12 : itype = M32R2F_INSN_BC8; goto extract_sfmt_bc8; + case 13 : itype = M32R2F_INSN_BNC8; goto extract_sfmt_bc8; + case 14 : itype = M32R2F_INSN_BL8; goto extract_sfmt_bl8; + case 15 : itype = M32R2F_INSN_BRA8; goto extract_sfmt_bra8; + default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 132 : itype = M32R2F_INSN_CMPI; goto extract_sfmt_cmpi; + case 133 : itype = M32R2F_INSN_CMPUI; goto extract_sfmt_cmpi; + case 134 : + { + unsigned int val = (((insn >> -8) & (3 << 0))); + switch (val) + { + case 0 : itype = M32R2F_INSN_SAT; goto extract_sfmt_sat; + case 2 : itype = M32R2F_INSN_SATH; goto extract_sfmt_satb; + case 3 : itype = M32R2F_INSN_SATB; goto extract_sfmt_satb; + default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 136 : itype = M32R2F_INSN_ADDV3; goto extract_sfmt_addv3; + case 138 : itype = M32R2F_INSN_ADD3; goto extract_sfmt_add3; + case 140 : itype = M32R2F_INSN_AND3; goto extract_sfmt_and3; + case 141 : itype = M32R2F_INSN_XOR3; goto extract_sfmt_and3; + case 142 : itype = M32R2F_INSN_OR3; goto extract_sfmt_or3; + case 144 : + { + unsigned int val = (((insn >> -13) & (3 << 0))); + switch (val) + { + case 0 : itype = M32R2F_INSN_DIV; goto extract_sfmt_div; + case 2 : itype = M32R2F_INSN_DIVH; goto extract_sfmt_div; + case 3 : itype = M32R2F_INSN_DIVB; goto extract_sfmt_div; + default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 145 : + { + unsigned int val = (((insn >> -13) & (3 << 0))); + switch (val) + { + case 0 : itype = M32R2F_INSN_DIVU; goto extract_sfmt_div; + case 2 : itype = M32R2F_INSN_DIVUH; goto extract_sfmt_div; + case 3 : itype = M32R2F_INSN_DIVUB; goto extract_sfmt_div; + default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 146 : + { + unsigned int val = (((insn >> -13) & (3 << 0))); + switch (val) + { + case 0 : itype = M32R2F_INSN_REM; goto extract_sfmt_div; + case 2 : itype = M32R2F_INSN_REMH; goto extract_sfmt_div; + case 3 : itype = M32R2F_INSN_REMB; goto extract_sfmt_div; + default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 147 : + { + unsigned int val = (((insn >> -13) & (3 << 0))); + switch (val) + { + case 0 : itype = M32R2F_INSN_REMU; goto extract_sfmt_div; + case 2 : itype = M32R2F_INSN_REMUH; goto extract_sfmt_div; + case 3 : itype = M32R2F_INSN_REMUB; goto extract_sfmt_div; + default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 152 : itype = M32R2F_INSN_SRL3; goto extract_sfmt_sll3; + case 154 : itype = M32R2F_INSN_SRA3; goto extract_sfmt_sll3; + case 156 : itype = M32R2F_INSN_SLL3; goto extract_sfmt_sll3; + case 159 : itype = M32R2F_INSN_LDI16; goto extract_sfmt_ldi16; + case 160 : itype = M32R2F_INSN_STB_D; goto extract_sfmt_stb_d; + case 162 : itype = M32R2F_INSN_STH_D; goto extract_sfmt_sth_d; + case 164 : itype = M32R2F_INSN_ST_D; goto extract_sfmt_st_d; + case 166 : itype = M32R2F_INSN_BSET; goto extract_sfmt_bset; + case 167 : itype = M32R2F_INSN_BCLR; goto extract_sfmt_bset; + case 168 : itype = M32R2F_INSN_LDB_D; goto extract_sfmt_ldb_d; + case 169 : itype = M32R2F_INSN_LDUB_D; goto extract_sfmt_ldb_d; + case 170 : itype = M32R2F_INSN_LDH_D; goto extract_sfmt_ldh_d; + case 171 : itype = M32R2F_INSN_LDUH_D; goto extract_sfmt_ldh_d; + case 172 : itype = M32R2F_INSN_LD_D; goto extract_sfmt_ld_d; + case 176 : itype = M32R2F_INSN_BEQ; goto extract_sfmt_beq; + case 177 : itype = M32R2F_INSN_BNE; goto extract_sfmt_beq; + case 184 : itype = M32R2F_INSN_BEQZ; goto extract_sfmt_beqz; + case 185 : itype = M32R2F_INSN_BNEZ; goto extract_sfmt_beqz; + case 186 : itype = M32R2F_INSN_BLTZ; goto extract_sfmt_beqz; + case 187 : itype = M32R2F_INSN_BGEZ; goto extract_sfmt_beqz; + case 188 : itype = M32R2F_INSN_BLEZ; goto extract_sfmt_beqz; + case 189 : itype = M32R2F_INSN_BGTZ; goto extract_sfmt_beqz; + case 220 : itype = M32R2F_INSN_SETH; goto extract_sfmt_seth; + case 224 : /* fall through */ + case 225 : /* fall through */ + case 226 : /* fall through */ + case 227 : /* fall through */ + case 228 : /* fall through */ + case 229 : /* fall through */ + case 230 : /* fall through */ + case 231 : /* fall through */ + case 232 : /* fall through */ + case 233 : /* fall through */ + case 234 : /* fall through */ + case 235 : /* fall through */ + case 236 : /* fall through */ + case 237 : /* fall through */ + case 238 : /* fall through */ + case 239 : itype = M32R2F_INSN_LD24; goto extract_sfmt_ld24; + case 240 : /* fall through */ + case 241 : /* fall through */ + case 242 : /* fall through */ + case 243 : /* fall through */ + case 244 : /* fall through */ + case 245 : /* fall through */ + case 246 : /* fall through */ + case 247 : /* fall through */ + case 248 : /* fall through */ + case 249 : /* fall through */ + case 250 : /* fall through */ + case 251 : /* fall through */ + case 252 : /* fall through */ + case 253 : /* fall through */ + case 254 : /* fall through */ + case 255 : + { + unsigned int val = (((insn >> 8) & (7 << 0))); + switch (val) + { + case 0 : itype = M32R2F_INSN_BCL24; goto extract_sfmt_bcl24; + case 1 : itype = M32R2F_INSN_BNCL24; goto extract_sfmt_bcl24; + case 4 : itype = M32R2F_INSN_BC24; goto extract_sfmt_bc24; + case 5 : itype = M32R2F_INSN_BNC24; goto extract_sfmt_bc24; + case 6 : itype = M32R2F_INSN_BL24; goto extract_sfmt_bl24; + case 7 : itype = M32R2F_INSN_BRA24; goto extract_sfmt_bra24; + default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + } + + /* The instruction has been decoded, now extract the fields. */ + + extract_sfmt_empty: + { + const IDESC *idesc = &m32r2f_insn_data[itype]; +#define FLD(f) abuf->fields.fmt_empty.f + + + /* Record the fields for the semantic handler. */ + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_empty", (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_add: + { + const IDESC *idesc = &m32r2f_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_add.f + UINT f_r1; + UINT f_r2; + + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); + + /* Record the fields for the semantic handler. */ + FLD (f_r1) = f_r1; + FLD (f_r2) = f_r2; + FLD (i_dr) = & CPU (h_gr)[f_r1]; + FLD (i_sr) = & CPU (h_gr)[f_r2]; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_dr) = f_r1; + FLD (in_sr) = f_r2; + FLD (out_dr) = f_r1; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_add3: + { + const IDESC *idesc = &m32r2f_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_add3.f + UINT f_r1; + UINT f_r2; + INT f_simm16; + + f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); + f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); + + /* Record the fields for the semantic handler. */ + FLD (f_simm16) = f_simm16; + FLD (f_r2) = f_r2; + FLD (f_r1) = f_r1; + FLD (i_sr) = & CPU (h_gr)[f_r2]; + FLD (i_dr) = & CPU (h_gr)[f_r1]; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add3", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_sr) = f_r2; + FLD (out_dr) = f_r1; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_and3: + { + const IDESC *idesc = &m32r2f_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_and3.f + UINT f_r1; + UINT f_r2; + UINT f_uimm16; + + f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); + f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); + + /* Record the fields for the semantic handler. */ + FLD (f_r2) = f_r2; + FLD (f_uimm16) = f_uimm16; + FLD (f_r1) = f_r1; + FLD (i_sr) = & CPU (h_gr)[f_r2]; + FLD (i_dr) = & CPU (h_gr)[f_r1]; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_and3", "f_r2 0x%x", 'x', f_r2, "f_uimm16 0x%x", 'x', f_uimm16, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_sr) = f_r2; + FLD (out_dr) = f_r1; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_or3: + { + const IDESC *idesc = &m32r2f_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_and3.f + UINT f_r1; + UINT f_r2; + UINT f_uimm16; + + f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); + f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); + + /* Record the fields for the semantic handler. */ + FLD (f_r2) = f_r2; + FLD (f_uimm16) = f_uimm16; + FLD (f_r1) = f_r1; + FLD (i_sr) = & CPU (h_gr)[f_r2]; + FLD (i_dr) = & CPU (h_gr)[f_r1]; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_or3", "f_r2 0x%x", 'x', f_r2, "f_uimm16 0x%x", 'x', f_uimm16, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_sr) = f_r2; + FLD (out_dr) = f_r1; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_addi: + { + const IDESC *idesc = &m32r2f_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_addi.f + UINT f_r1; + INT f_simm8; + + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_simm8 = EXTRACT_MSB0_INT (insn, 16, 8, 8); + + /* Record the fields for the semantic handler. */ + FLD (f_r1) = f_r1; + FLD (f_simm8) = f_simm8; + FLD (i_dr) = & CPU (h_gr)[f_r1]; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addi", "f_r1 0x%x", 'x', f_r1, "f_simm8 0x%x", 'x', f_simm8, "dr 0x%x", 'x', f_r1, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_dr) = f_r1; + FLD (out_dr) = f_r1; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_addv: + { + const IDESC *idesc = &m32r2f_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_add.f + UINT f_r1; + UINT f_r2; + + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); + + /* Record the fields for the semantic handler. */ + FLD (f_r1) = f_r1; + FLD (f_r2) = f_r2; + FLD (i_dr) = & CPU (h_gr)[f_r1]; + FLD (i_sr) = & CPU (h_gr)[f_r2]; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addv", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_dr) = f_r1; + FLD (in_sr) = f_r2; + FLD (out_dr) = f_r1; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_addv3: + { + const IDESC *idesc = &m32r2f_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_add3.f + UINT f_r1; + UINT f_r2; + INT f_simm16; + + f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); + f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); + + /* Record the fields for the semantic handler. */ + FLD (f_simm16) = f_simm16; + FLD (f_r2) = f_r2; + FLD (f_r1) = f_r1; + FLD (i_sr) = & CPU (h_gr)[f_r2]; + FLD (i_dr) = & CPU (h_gr)[f_r1]; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addv3", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_sr) = f_r2; + FLD (out_dr) = f_r1; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_addx: + { + const IDESC *idesc = &m32r2f_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_add.f + UINT f_r1; + UINT f_r2; + + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); + + /* Record the fields for the semantic handler. */ + FLD (f_r1) = f_r1; + FLD (f_r2) = f_r2; + FLD (i_dr) = & CPU (h_gr)[f_r1]; + FLD (i_sr) = & CPU (h_gr)[f_r2]; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addx", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_dr) = f_r1; + FLD (in_sr) = f_r2; + FLD (out_dr) = f_r1; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_bc8: + { + const IDESC *idesc = &m32r2f_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_bl8.f + SI f_disp8; + + f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); + + /* Record the fields for the semantic handler. */ + FLD (i_disp8) = f_disp8; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bc8", "disp8 0x%x", 'x', f_disp8, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_bc24: + { + const IDESC *idesc = &m32r2f_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_bl24.f + SI f_disp24; + + f_disp24 = ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc)); + + /* Record the fields for the semantic handler. */ + FLD (i_disp24) = f_disp24; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bc24", "disp24 0x%x", 'x', f_disp24, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_beq: + { + const IDESC *idesc = &m32r2f_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_beq.f + UINT f_r1; + UINT f_r2; + SI f_disp16; + + f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); + f_disp16 = ((((EXTRACT_MSB0_INT (insn, 32, 16, 16)) << (2))) + (pc)); + + /* Record the fields for the semantic handler. */ + FLD (f_r1) = f_r1; + FLD (f_r2) = f_r2; + FLD (i_disp16) = f_disp16; + FLD (i_src1) = & CPU (h_gr)[f_r1]; + FLD (i_src2) = & CPU (h_gr)[f_r2]; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_beq", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "disp16 0x%x", 'x', f_disp16, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_src1) = f_r1; + FLD (in_src2) = f_r2; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_beqz: + { + const IDESC *idesc = &m32r2f_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_beq.f + UINT f_r2; + SI f_disp16; + + f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); + f_disp16 = ((((EXTRACT_MSB0_INT (insn, 32, 16, 16)) << (2))) + (pc)); + + /* Record the fields for the semantic handler. */ + FLD (f_r2) = f_r2; + FLD (i_disp16) = f_disp16; + FLD (i_src2) = & CPU (h_gr)[f_r2]; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_beqz", "f_r2 0x%x", 'x', f_r2, "disp16 0x%x", 'x', f_disp16, "src2 0x%x", 'x', f_r2, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_src2) = f_r2; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_bl8: + { + const IDESC *idesc = &m32r2f_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_bl8.f + SI f_disp8; + + f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); + + /* Record the fields for the semantic handler. */ + FLD (i_disp8) = f_disp8; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bl8", "disp8 0x%x", 'x', f_disp8, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (out_h_gr_SI_14) = 14; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_bl24: + { + const IDESC *idesc = &m32r2f_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_bl24.f + SI f_disp24; + + f_disp24 = ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc)); + + /* Record the fields for the semantic handler. */ + FLD (i_disp24) = f_disp24; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bl24", "disp24 0x%x", 'x', f_disp24, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (out_h_gr_SI_14) = 14; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_bcl8: + { + const IDESC *idesc = &m32r2f_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_bl8.f + SI f_disp8; + + f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); + + /* Record the fields for the semantic handler. */ + FLD (i_disp8) = f_disp8; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bcl8", "disp8 0x%x", 'x', f_disp8, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (out_h_gr_SI_14) = 14; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_bcl24: + { + const IDESC *idesc = &m32r2f_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_bl24.f + SI f_disp24; + + f_disp24 = ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc)); + + /* Record the fields for the semantic handler. */ + FLD (i_disp24) = f_disp24; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bcl24", "disp24 0x%x", 'x', f_disp24, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (out_h_gr_SI_14) = 14; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_bra8: + { + const IDESC *idesc = &m32r2f_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_bl8.f + SI f_disp8; + + f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); + + /* Record the fields for the semantic handler. */ + FLD (i_disp8) = f_disp8; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bra8", "disp8 0x%x", 'x', f_disp8, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_bra24: + { + const IDESC *idesc = &m32r2f_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_bl24.f + SI f_disp24; + + f_disp24 = ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc)); + + /* Record the fields for the semantic handler. */ + FLD (i_disp24) = f_disp24; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bra24", "disp24 0x%x", 'x', f_disp24, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_cmp: + { + const IDESC *idesc = &m32r2f_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_st_plus.f + UINT f_r1; + UINT f_r2; + + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); + + /* Record the fields for the semantic handler. */ + FLD (f_r1) = f_r1; + FLD (f_r2) = f_r2; + FLD (i_src1) = & CPU (h_gr)[f_r1]; + FLD (i_src2) = & CPU (h_gr)[f_r2]; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmp", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_src1) = f_r1; + FLD (in_src2) = f_r2; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_cmpi: + { + const IDESC *idesc = &m32r2f_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_st_d.f + UINT f_r2; + INT f_simm16; + + f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); + f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); + + /* Record the fields for the semantic handler. */ + FLD (f_simm16) = f_simm16; + FLD (f_r2) = f_r2; + FLD (i_src2) = & CPU (h_gr)[f_r2]; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmpi", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "src2 0x%x", 'x', f_r2, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_src2) = f_r2; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_cmpz: + { + const IDESC *idesc = &m32r2f_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_st_plus.f + UINT f_r2; + + f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); + + /* Record the fields for the semantic handler. */ + FLD (f_r2) = f_r2; + FLD (i_src2) = & CPU (h_gr)[f_r2]; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmpz", "f_r2 0x%x", 'x', f_r2, "src2 0x%x", 'x', f_r2, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_src2) = f_r2; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_div: + { + const IDESC *idesc = &m32r2f_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_add.f + UINT f_r1; + UINT f_r2; + + f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); + + /* Record the fields for the semantic handler. */ + FLD (f_r1) = f_r1; + FLD (f_r2) = f_r2; + FLD (i_dr) = & CPU (h_gr)[f_r1]; + FLD (i_sr) = & CPU (h_gr)[f_r2]; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_div", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_dr) = f_r1; + FLD (in_sr) = f_r2; + FLD (out_dr) = f_r1; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_jc: + { + const IDESC *idesc = &m32r2f_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_jl.f + UINT f_r2; + + f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); + + /* Record the fields for the semantic handler. */ + FLD (f_r2) = f_r2; + FLD (i_sr) = & CPU (h_gr)[f_r2]; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jc", "f_r2 0x%x", 'x', f_r2, "sr 0x%x", 'x', f_r2, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_sr) = f_r2; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_jl: + { + const IDESC *idesc = &m32r2f_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_jl.f + UINT f_r2; + + f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); + + /* Record the fields for the semantic handler. */ + FLD (f_r2) = f_r2; + FLD (i_sr) = & CPU (h_gr)[f_r2]; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jl", "f_r2 0x%x", 'x', f_r2, "sr 0x%x", 'x', f_r2, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_sr) = f_r2; + FLD (out_h_gr_SI_14) = 14; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_jmp: + { + const IDESC *idesc = &m32r2f_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_jl.f + UINT f_r2; + + f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); + + /* Record the fields for the semantic handler. */ + FLD (f_r2) = f_r2; + FLD (i_sr) = & CPU (h_gr)[f_r2]; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jmp", "f_r2 0x%x", 'x', f_r2, "sr 0x%x", 'x', f_r2, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_sr) = f_r2; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_ld: + { + const IDESC *idesc = &m32r2f_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_ld_plus.f + UINT f_r1; + UINT f_r2; + + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); + + /* Record the fields for the semantic handler. */ + FLD (f_r2) = f_r2; + FLD (f_r1) = f_r1; + FLD (i_sr) = & CPU (h_gr)[f_r2]; + FLD (i_dr) = & CPU (h_gr)[f_r1]; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_sr) = f_r2; + FLD (out_dr) = f_r1; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_ld_d: + { + const IDESC *idesc = &m32r2f_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_add3.f + UINT f_r1; + UINT f_r2; + INT f_simm16; + + f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); + f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); + + /* Record the fields for the semantic handler. */ + FLD (f_simm16) = f_simm16; + FLD (f_r2) = f_r2; + FLD (f_r1) = f_r1; + FLD (i_sr) = & CPU (h_gr)[f_r2]; + FLD (i_dr) = & CPU (h_gr)[f_r1]; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld_d", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_sr) = f_r2; + FLD (out_dr) = f_r1; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_ldb: + { + const IDESC *idesc = &m32r2f_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_ld_plus.f + UINT f_r1; + UINT f_r2; + + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); + + /* Record the fields for the semantic handler. */ + FLD (f_r2) = f_r2; + FLD (f_r1) = f_r1; + FLD (i_sr) = & CPU (h_gr)[f_r2]; + FLD (i_dr) = & CPU (h_gr)[f_r1]; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldb", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_sr) = f_r2; + FLD (out_dr) = f_r1; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_ldb_d: + { + const IDESC *idesc = &m32r2f_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_add3.f + UINT f_r1; + UINT f_r2; + INT f_simm16; + + f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); + f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); + + /* Record the fields for the semantic handler. */ + FLD (f_simm16) = f_simm16; + FLD (f_r2) = f_r2; + FLD (f_r1) = f_r1; + FLD (i_sr) = & CPU (h_gr)[f_r2]; + FLD (i_dr) = & CPU (h_gr)[f_r1]; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldb_d", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_sr) = f_r2; + FLD (out_dr) = f_r1; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_ldh: + { + const IDESC *idesc = &m32r2f_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_ld_plus.f + UINT f_r1; + UINT f_r2; + + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); + + /* Record the fields for the semantic handler. */ + FLD (f_r2) = f_r2; + FLD (f_r1) = f_r1; + FLD (i_sr) = & CPU (h_gr)[f_r2]; + FLD (i_dr) = & CPU (h_gr)[f_r1]; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldh", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_sr) = f_r2; + FLD (out_dr) = f_r1; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_ldh_d: + { + const IDESC *idesc = &m32r2f_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_add3.f + UINT f_r1; + UINT f_r2; + INT f_simm16; + + f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); + f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); + + /* Record the fields for the semantic handler. */ + FLD (f_simm16) = f_simm16; + FLD (f_r2) = f_r2; + FLD (f_r1) = f_r1; + FLD (i_sr) = & CPU (h_gr)[f_r2]; + FLD (i_dr) = & CPU (h_gr)[f_r1]; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldh_d", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_sr) = f_r2; + FLD (out_dr) = f_r1; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_ld_plus: + { + const IDESC *idesc = &m32r2f_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_ld_plus.f + UINT f_r1; + UINT f_r2; + + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); + + /* Record the fields for the semantic handler. */ + FLD (f_r2) = f_r2; + FLD (f_r1) = f_r1; + FLD (i_sr) = & CPU (h_gr)[f_r2]; + FLD (i_dr) = & CPU (h_gr)[f_r1]; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld_plus", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_sr) = f_r2; + FLD (out_dr) = f_r1; + FLD (out_sr) = f_r2; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_ld24: + { + const IDESC *idesc = &m32r2f_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_ld24.f + UINT f_r1; + UINT f_uimm24; + + f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); + f_uimm24 = EXTRACT_MSB0_UINT (insn, 32, 8, 24); + + /* Record the fields for the semantic handler. */ + FLD (f_r1) = f_r1; + FLD (i_uimm24) = f_uimm24; + FLD (i_dr) = & CPU (h_gr)[f_r1]; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld24", "f_r1 0x%x", 'x', f_r1, "uimm24 0x%x", 'x', f_uimm24, "dr 0x%x", 'x', f_r1, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (out_dr) = f_r1; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_ldi8: + { + const IDESC *idesc = &m32r2f_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_addi.f + UINT f_r1; + INT f_simm8; + + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_simm8 = EXTRACT_MSB0_INT (insn, 16, 8, 8); + + /* Record the fields for the semantic handler. */ + FLD (f_simm8) = f_simm8; + FLD (f_r1) = f_r1; + FLD (i_dr) = & CPU (h_gr)[f_r1]; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldi8", "f_simm8 0x%x", 'x', f_simm8, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (out_dr) = f_r1; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_ldi16: + { + const IDESC *idesc = &m32r2f_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_add3.f + UINT f_r1; + INT f_simm16; + + f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); + f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); + + /* Record the fields for the semantic handler. */ + FLD (f_simm16) = f_simm16; + FLD (f_r1) = f_r1; + FLD (i_dr) = & CPU (h_gr)[f_r1]; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldi16", "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (out_dr) = f_r1; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_lock: + { + const IDESC *idesc = &m32r2f_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_ld_plus.f + UINT f_r1; + UINT f_r2; + + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); + + /* Record the fields for the semantic handler. */ + FLD (f_r2) = f_r2; + FLD (f_r1) = f_r1; + FLD (i_sr) = & CPU (h_gr)[f_r2]; + FLD (i_dr) = & CPU (h_gr)[f_r1]; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lock", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_sr) = f_r2; + FLD (out_dr) = f_r1; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_machi_a: + { + const IDESC *idesc = &m32r2f_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_machi_a.f + UINT f_r1; + UINT f_acc; + UINT f_r2; + + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_acc = EXTRACT_MSB0_UINT (insn, 16, 8, 1); + f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); + + /* Record the fields for the semantic handler. */ + FLD (f_acc) = f_acc; + FLD (f_r1) = f_r1; + FLD (f_r2) = f_r2; + FLD (i_src1) = & CPU (h_gr)[f_r1]; + FLD (i_src2) = & CPU (h_gr)[f_r2]; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_machi_a", "f_acc 0x%x", 'x', f_acc, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_src1) = f_r1; + FLD (in_src2) = f_r2; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_mulhi_a: + { + const IDESC *idesc = &m32r2f_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_machi_a.f + UINT f_r1; + UINT f_acc; + UINT f_r2; + + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_acc = EXTRACT_MSB0_UINT (insn, 16, 8, 1); + f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); + + /* Record the fields for the semantic handler. */ + FLD (f_r1) = f_r1; + FLD (f_r2) = f_r2; + FLD (f_acc) = f_acc; + FLD (i_src1) = & CPU (h_gr)[f_r1]; + FLD (i_src2) = & CPU (h_gr)[f_r2]; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mulhi_a", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "f_acc 0x%x", 'x', f_acc, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_src1) = f_r1; + FLD (in_src2) = f_r2; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_mv: + { + const IDESC *idesc = &m32r2f_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_ld_plus.f + UINT f_r1; + UINT f_r2; + + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); + + /* Record the fields for the semantic handler. */ + FLD (f_r2) = f_r2; + FLD (f_r1) = f_r1; + FLD (i_sr) = & CPU (h_gr)[f_r2]; + FLD (i_dr) = & CPU (h_gr)[f_r1]; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mv", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_sr) = f_r2; + FLD (out_dr) = f_r1; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_mvfachi_a: + { + const IDESC *idesc = &m32r2f_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_mvfachi_a.f + UINT f_r1; + UINT f_accs; + + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2); + + /* Record the fields for the semantic handler. */ + FLD (f_accs) = f_accs; + FLD (f_r1) = f_r1; + FLD (i_dr) = & CPU (h_gr)[f_r1]; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvfachi_a", "f_accs 0x%x", 'x', f_accs, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (out_dr) = f_r1; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_mvfc: + { + const IDESC *idesc = &m32r2f_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_ld_plus.f + UINT f_r1; + UINT f_r2; + + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); + + /* Record the fields for the semantic handler. */ + FLD (f_r2) = f_r2; + FLD (f_r1) = f_r1; + FLD (i_dr) = & CPU (h_gr)[f_r1]; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvfc", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (out_dr) = f_r1; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_mvtachi_a: + { + const IDESC *idesc = &m32r2f_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_mvtachi_a.f + UINT f_r1; + UINT f_accs; + + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2); + + /* Record the fields for the semantic handler. */ + FLD (f_accs) = f_accs; + FLD (f_r1) = f_r1; + FLD (i_src1) = & CPU (h_gr)[f_r1]; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvtachi_a", "f_accs 0x%x", 'x', f_accs, "f_r1 0x%x", 'x', f_r1, "src1 0x%x", 'x', f_r1, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_src1) = f_r1; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_mvtc: + { + const IDESC *idesc = &m32r2f_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_ld_plus.f + UINT f_r1; + UINT f_r2; + + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); + + /* Record the fields for the semantic handler. */ + FLD (f_r2) = f_r2; + FLD (f_r1) = f_r1; + FLD (i_sr) = & CPU (h_gr)[f_r2]; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvtc", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_sr) = f_r2; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_nop: + { + const IDESC *idesc = &m32r2f_insn_data[itype]; +#define FLD(f) abuf->fields.fmt_empty.f + + + /* Record the fields for the semantic handler. */ + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_nop", (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_rac_dsi: + { + const IDESC *idesc = &m32r2f_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_rac_dsi.f + UINT f_accd; + UINT f_accs; + SI f_imm1; + + f_accd = EXTRACT_MSB0_UINT (insn, 16, 4, 2); + f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2); + f_imm1 = ((EXTRACT_MSB0_UINT (insn, 16, 15, 1)) + (1)); + + /* Record the fields for the semantic handler. */ + FLD (f_accs) = f_accs; + FLD (f_imm1) = f_imm1; + FLD (f_accd) = f_accd; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rac_dsi", "f_accs 0x%x", 'x', f_accs, "f_imm1 0x%x", 'x', f_imm1, "f_accd 0x%x", 'x', f_accd, (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_rte: + { + const IDESC *idesc = &m32r2f_insn_data[itype]; +#define FLD(f) abuf->fields.fmt_empty.f + + + /* Record the fields for the semantic handler. */ + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rte", (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_seth: + { + const IDESC *idesc = &m32r2f_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_seth.f + UINT f_r1; + UINT f_hi16; + + f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); + f_hi16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); + + /* Record the fields for the semantic handler. */ + FLD (f_hi16) = f_hi16; + FLD (f_r1) = f_r1; + FLD (i_dr) = & CPU (h_gr)[f_r1]; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_seth", "f_hi16 0x%x", 'x', f_hi16, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (out_dr) = f_r1; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_sll3: + { + const IDESC *idesc = &m32r2f_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_add3.f + UINT f_r1; + UINT f_r2; + INT f_simm16; + + f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); + f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); + + /* Record the fields for the semantic handler. */ + FLD (f_simm16) = f_simm16; + FLD (f_r2) = f_r2; + FLD (f_r1) = f_r1; + FLD (i_sr) = & CPU (h_gr)[f_r2]; + FLD (i_dr) = & CPU (h_gr)[f_r1]; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sll3", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_sr) = f_r2; + FLD (out_dr) = f_r1; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_slli: + { + const IDESC *idesc = &m32r2f_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_slli.f + UINT f_r1; + UINT f_uimm5; + + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_uimm5 = EXTRACT_MSB0_UINT (insn, 16, 11, 5); + + /* Record the fields for the semantic handler. */ + FLD (f_r1) = f_r1; + FLD (f_uimm5) = f_uimm5; + FLD (i_dr) = & CPU (h_gr)[f_r1]; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_slli", "f_r1 0x%x", 'x', f_r1, "f_uimm5 0x%x", 'x', f_uimm5, "dr 0x%x", 'x', f_r1, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_dr) = f_r1; + FLD (out_dr) = f_r1; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_st: + { + const IDESC *idesc = &m32r2f_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_st_plus.f + UINT f_r1; + UINT f_r2; + + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); + + /* Record the fields for the semantic handler. */ + FLD (f_r1) = f_r1; + FLD (f_r2) = f_r2; + FLD (i_src1) = & CPU (h_gr)[f_r1]; + FLD (i_src2) = & CPU (h_gr)[f_r2]; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_src1) = f_r1; + FLD (in_src2) = f_r2; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_st_d: + { + const IDESC *idesc = &m32r2f_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_st_d.f + UINT f_r1; + UINT f_r2; + INT f_simm16; + + f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); + f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); + + /* Record the fields for the semantic handler. */ + FLD (f_simm16) = f_simm16; + FLD (f_r1) = f_r1; + FLD (f_r2) = f_r2; + FLD (i_src1) = & CPU (h_gr)[f_r1]; + FLD (i_src2) = & CPU (h_gr)[f_r2]; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st_d", "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_src1) = f_r1; + FLD (in_src2) = f_r2; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_stb: + { + const IDESC *idesc = &m32r2f_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_st_plus.f + UINT f_r1; + UINT f_r2; + + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); + + /* Record the fields for the semantic handler. */ + FLD (f_r1) = f_r1; + FLD (f_r2) = f_r2; + FLD (i_src1) = & CPU (h_gr)[f_r1]; + FLD (i_src2) = & CPU (h_gr)[f_r2]; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_src1) = f_r1; + FLD (in_src2) = f_r2; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_stb_d: + { + const IDESC *idesc = &m32r2f_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_st_d.f + UINT f_r1; + UINT f_r2; + INT f_simm16; + + f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); + f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); + + /* Record the fields for the semantic handler. */ + FLD (f_simm16) = f_simm16; + FLD (f_r1) = f_r1; + FLD (f_r2) = f_r2; + FLD (i_src1) = & CPU (h_gr)[f_r1]; + FLD (i_src2) = & CPU (h_gr)[f_r2]; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb_d", "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_src1) = f_r1; + FLD (in_src2) = f_r2; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_sth: + { + const IDESC *idesc = &m32r2f_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_st_plus.f + UINT f_r1; + UINT f_r2; + + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); + + /* Record the fields for the semantic handler. */ + FLD (f_r1) = f_r1; + FLD (f_r2) = f_r2; + FLD (i_src1) = & CPU (h_gr)[f_r1]; + FLD (i_src2) = & CPU (h_gr)[f_r2]; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sth", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_src1) = f_r1; + FLD (in_src2) = f_r2; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_sth_d: + { + const IDESC *idesc = &m32r2f_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_st_d.f + UINT f_r1; + UINT f_r2; + INT f_simm16; + + f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); + f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); + + /* Record the fields for the semantic handler. */ + FLD (f_simm16) = f_simm16; + FLD (f_r1) = f_r1; + FLD (f_r2) = f_r2; + FLD (i_src1) = & CPU (h_gr)[f_r1]; + FLD (i_src2) = & CPU (h_gr)[f_r2]; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sth_d", "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_src1) = f_r1; + FLD (in_src2) = f_r2; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_st_plus: + { + const IDESC *idesc = &m32r2f_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_st_plus.f + UINT f_r1; + UINT f_r2; + + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); + + /* Record the fields for the semantic handler. */ + FLD (f_r1) = f_r1; + FLD (f_r2) = f_r2; + FLD (i_src1) = & CPU (h_gr)[f_r1]; + FLD (i_src2) = & CPU (h_gr)[f_r2]; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st_plus", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_src1) = f_r1; + FLD (in_src2) = f_r2; + FLD (out_src2) = f_r2; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_sth_plus: + { + const IDESC *idesc = &m32r2f_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_st_plus.f + UINT f_r1; + UINT f_r2; + + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); + + /* Record the fields for the semantic handler. */ + FLD (f_r1) = f_r1; + FLD (f_r2) = f_r2; + FLD (i_src1) = & CPU (h_gr)[f_r1]; + FLD (i_src2) = & CPU (h_gr)[f_r2]; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sth_plus", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_src1) = f_r1; + FLD (in_src2) = f_r2; + FLD (out_src2) = f_r2; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_stb_plus: + { + const IDESC *idesc = &m32r2f_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_st_plus.f + UINT f_r1; + UINT f_r2; + + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); + + /* Record the fields for the semantic handler. */ + FLD (f_r1) = f_r1; + FLD (f_r2) = f_r2; + FLD (i_src1) = & CPU (h_gr)[f_r1]; + FLD (i_src2) = & CPU (h_gr)[f_r2]; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb_plus", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_src1) = f_r1; + FLD (in_src2) = f_r2; + FLD (out_src2) = f_r2; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_trap: + { + const IDESC *idesc = &m32r2f_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_trap.f + UINT f_uimm4; + + f_uimm4 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); + + /* Record the fields for the semantic handler. */ + FLD (f_uimm4) = f_uimm4; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_trap", "f_uimm4 0x%x", 'x', f_uimm4, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_unlock: + { + const IDESC *idesc = &m32r2f_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_st_plus.f + UINT f_r1; + UINT f_r2; + + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); + + /* Record the fields for the semantic handler. */ + FLD (f_r1) = f_r1; + FLD (f_r2) = f_r2; + FLD (i_src1) = & CPU (h_gr)[f_r1]; + FLD (i_src2) = & CPU (h_gr)[f_r2]; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_unlock", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_src1) = f_r1; + FLD (in_src2) = f_r2; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_satb: + { + const IDESC *idesc = &m32r2f_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_ld_plus.f + UINT f_r1; + UINT f_r2; + + f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); + + /* Record the fields for the semantic handler. */ + FLD (f_r2) = f_r2; + FLD (f_r1) = f_r1; + FLD (i_sr) = & CPU (h_gr)[f_r2]; + FLD (i_dr) = & CPU (h_gr)[f_r1]; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_satb", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_sr) = f_r2; + FLD (out_dr) = f_r1; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_sat: + { + const IDESC *idesc = &m32r2f_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_ld_plus.f + UINT f_r1; + UINT f_r2; + + f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); + + /* Record the fields for the semantic handler. */ + FLD (f_r2) = f_r2; + FLD (f_r1) = f_r1; + FLD (i_sr) = & CPU (h_gr)[f_r2]; + FLD (i_dr) = & CPU (h_gr)[f_r1]; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sat", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_sr) = f_r2; + FLD (out_dr) = f_r1; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_sadd: + { + const IDESC *idesc = &m32r2f_insn_data[itype]; +#define FLD(f) abuf->fields.fmt_empty.f + + + /* Record the fields for the semantic handler. */ + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sadd", (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_macwu1: + { + const IDESC *idesc = &m32r2f_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_st_plus.f + UINT f_r1; + UINT f_r2; + + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); + + /* Record the fields for the semantic handler. */ + FLD (f_r1) = f_r1; + FLD (f_r2) = f_r2; + FLD (i_src1) = & CPU (h_gr)[f_r1]; + FLD (i_src2) = & CPU (h_gr)[f_r2]; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_macwu1", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_src1) = f_r1; + FLD (in_src2) = f_r2; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_msblo: + { + const IDESC *idesc = &m32r2f_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_st_plus.f + UINT f_r1; + UINT f_r2; + + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); + + /* Record the fields for the semantic handler. */ + FLD (f_r1) = f_r1; + FLD (f_r2) = f_r2; + FLD (i_src1) = & CPU (h_gr)[f_r1]; + FLD (i_src2) = & CPU (h_gr)[f_r2]; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_msblo", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_src1) = f_r1; + FLD (in_src2) = f_r2; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_mulwu1: + { + const IDESC *idesc = &m32r2f_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_st_plus.f + UINT f_r1; + UINT f_r2; + + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); + + /* Record the fields for the semantic handler. */ + FLD (f_r1) = f_r1; + FLD (f_r2) = f_r2; + FLD (i_src1) = & CPU (h_gr)[f_r1]; + FLD (i_src2) = & CPU (h_gr)[f_r2]; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mulwu1", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_src1) = f_r1; + FLD (in_src2) = f_r2; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_sc: + { + const IDESC *idesc = &m32r2f_insn_data[itype]; +#define FLD(f) abuf->fields.fmt_empty.f + + + /* Record the fields for the semantic handler. */ + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sc", (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_clrpsw: + { + const IDESC *idesc = &m32r2f_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_clrpsw.f + UINT f_uimm8; + + f_uimm8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); + + /* Record the fields for the semantic handler. */ + FLD (f_uimm8) = f_uimm8; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_clrpsw", "f_uimm8 0x%x", 'x', f_uimm8, (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_setpsw: + { + const IDESC *idesc = &m32r2f_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_clrpsw.f + UINT f_uimm8; + + f_uimm8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); + + /* Record the fields for the semantic handler. */ + FLD (f_uimm8) = f_uimm8; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_setpsw", "f_uimm8 0x%x", 'x', f_uimm8, (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_bset: + { + const IDESC *idesc = &m32r2f_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_bset.f + UINT f_uimm3; + UINT f_r2; + INT f_simm16; + + f_uimm3 = EXTRACT_MSB0_UINT (insn, 32, 5, 3); + f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); + f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); + + /* Record the fields for the semantic handler. */ + FLD (f_simm16) = f_simm16; + FLD (f_r2) = f_r2; + FLD (f_uimm3) = f_uimm3; + FLD (i_sr) = & CPU (h_gr)[f_r2]; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bset", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_uimm3 0x%x", 'x', f_uimm3, "sr 0x%x", 'x', f_r2, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_sr) = f_r2; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_btst: + { + const IDESC *idesc = &m32r2f_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_bset.f + UINT f_uimm3; + UINT f_r2; + + f_uimm3 = EXTRACT_MSB0_UINT (insn, 16, 5, 3); + f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); + + /* Record the fields for the semantic handler. */ + FLD (f_r2) = f_r2; + FLD (f_uimm3) = f_uimm3; + FLD (i_sr) = & CPU (h_gr)[f_r2]; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_btst", "f_r2 0x%x", 'x', f_r2, "f_uimm3 0x%x", 'x', f_uimm3, "sr 0x%x", 'x', f_r2, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_sr) = f_r2; + } +#endif +#undef FLD + return idesc; + } + +} diff --git a/sim/m32r/decode2.h b/sim/m32r/decode2.h new file mode 100644 index 0000000..280247e --- /dev/null +++ b/sim/m32r/decode2.h @@ -0,0 +1,151 @@ +/* Decode header for m32r2f. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. + +This file is part of the GNU simulators. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +*/ + +#ifndef M32R2F_DECODE_H +#define M32R2F_DECODE_H + +extern const IDESC *m32r2f_decode (SIM_CPU *, IADDR, + CGEN_INSN_INT, CGEN_INSN_INT, + ARGBUF *); +extern void m32r2f_init_idesc_table (SIM_CPU *); +extern void m32r2f_sem_init_idesc_table (SIM_CPU *); +extern void m32r2f_semf_init_idesc_table (SIM_CPU *); + +/* Enum declaration for instructions in cpu family m32r2f. */ +typedef enum m32r2f_insn_type { + M32R2F_INSN_X_INVALID, M32R2F_INSN_X_AFTER, M32R2F_INSN_X_BEFORE, M32R2F_INSN_X_CTI_CHAIN + , M32R2F_INSN_X_CHAIN, M32R2F_INSN_X_BEGIN, M32R2F_INSN_ADD, M32R2F_INSN_ADD3 + , M32R2F_INSN_AND, M32R2F_INSN_AND3, M32R2F_INSN_OR, M32R2F_INSN_OR3 + , M32R2F_INSN_XOR, M32R2F_INSN_XOR3, M32R2F_INSN_ADDI, M32R2F_INSN_ADDV + , M32R2F_INSN_ADDV3, M32R2F_INSN_ADDX, M32R2F_INSN_BC8, M32R2F_INSN_BC24 + , M32R2F_INSN_BEQ, M32R2F_INSN_BEQZ, M32R2F_INSN_BGEZ, M32R2F_INSN_BGTZ + , M32R2F_INSN_BLEZ, M32R2F_INSN_BLTZ, M32R2F_INSN_BNEZ, M32R2F_INSN_BL8 + , M32R2F_INSN_BL24, M32R2F_INSN_BCL8, M32R2F_INSN_BCL24, M32R2F_INSN_BNC8 + , M32R2F_INSN_BNC24, M32R2F_INSN_BNE, M32R2F_INSN_BRA8, M32R2F_INSN_BRA24 + , M32R2F_INSN_BNCL8, M32R2F_INSN_BNCL24, M32R2F_INSN_CMP, M32R2F_INSN_CMPI + , M32R2F_INSN_CMPU, M32R2F_INSN_CMPUI, M32R2F_INSN_CMPEQ, M32R2F_INSN_CMPZ + , M32R2F_INSN_DIV, M32R2F_INSN_DIVU, M32R2F_INSN_REM, M32R2F_INSN_REMU + , M32R2F_INSN_REMH, M32R2F_INSN_REMUH, M32R2F_INSN_REMB, M32R2F_INSN_REMUB + , M32R2F_INSN_DIVUH, M32R2F_INSN_DIVB, M32R2F_INSN_DIVUB, M32R2F_INSN_DIVH + , M32R2F_INSN_JC, M32R2F_INSN_JNC, M32R2F_INSN_JL, M32R2F_INSN_JMP + , M32R2F_INSN_LD, M32R2F_INSN_LD_D, M32R2F_INSN_LDB, M32R2F_INSN_LDB_D + , M32R2F_INSN_LDH, M32R2F_INSN_LDH_D, M32R2F_INSN_LDUB, M32R2F_INSN_LDUB_D + , M32R2F_INSN_LDUH, M32R2F_INSN_LDUH_D, M32R2F_INSN_LD_PLUS, M32R2F_INSN_LD24 + , M32R2F_INSN_LDI8, M32R2F_INSN_LDI16, M32R2F_INSN_LOCK, M32R2F_INSN_MACHI_A + , M32R2F_INSN_MACLO_A, M32R2F_INSN_MACWHI_A, M32R2F_INSN_MACWLO_A, M32R2F_INSN_MUL + , M32R2F_INSN_MULHI_A, M32R2F_INSN_MULLO_A, M32R2F_INSN_MULWHI_A, M32R2F_INSN_MULWLO_A + , M32R2F_INSN_MV, M32R2F_INSN_MVFACHI_A, M32R2F_INSN_MVFACLO_A, M32R2F_INSN_MVFACMI_A + , M32R2F_INSN_MVFC, M32R2F_INSN_MVTACHI_A, M32R2F_INSN_MVTACLO_A, M32R2F_INSN_MVTC + , M32R2F_INSN_NEG, M32R2F_INSN_NOP, M32R2F_INSN_NOT, M32R2F_INSN_RAC_DSI + , M32R2F_INSN_RACH_DSI, M32R2F_INSN_RTE, M32R2F_INSN_SETH, M32R2F_INSN_SLL + , M32R2F_INSN_SLL3, M32R2F_INSN_SLLI, M32R2F_INSN_SRA, M32R2F_INSN_SRA3 + , M32R2F_INSN_SRAI, M32R2F_INSN_SRL, M32R2F_INSN_SRL3, M32R2F_INSN_SRLI + , M32R2F_INSN_ST, M32R2F_INSN_ST_D, M32R2F_INSN_STB, M32R2F_INSN_STB_D + , M32R2F_INSN_STH, M32R2F_INSN_STH_D, M32R2F_INSN_ST_PLUS, M32R2F_INSN_STH_PLUS + , M32R2F_INSN_STB_PLUS, M32R2F_INSN_ST_MINUS, M32R2F_INSN_SUB, M32R2F_INSN_SUBV + , M32R2F_INSN_SUBX, M32R2F_INSN_TRAP, M32R2F_INSN_UNLOCK, M32R2F_INSN_SATB + , M32R2F_INSN_SATH, M32R2F_INSN_SAT, M32R2F_INSN_PCMPBZ, M32R2F_INSN_SADD + , M32R2F_INSN_MACWU1, M32R2F_INSN_MSBLO, M32R2F_INSN_MULWU1, M32R2F_INSN_MACLH1 + , M32R2F_INSN_SC, M32R2F_INSN_SNC, M32R2F_INSN_CLRPSW, M32R2F_INSN_SETPSW + , M32R2F_INSN_BSET, M32R2F_INSN_BCLR, M32R2F_INSN_BTST, M32R2F_INSN_PAR_ADD + , M32R2F_INSN_WRITE_ADD, M32R2F_INSN_PAR_AND, M32R2F_INSN_WRITE_AND, M32R2F_INSN_PAR_OR + , M32R2F_INSN_WRITE_OR, M32R2F_INSN_PAR_XOR, M32R2F_INSN_WRITE_XOR, M32R2F_INSN_PAR_ADDI + , M32R2F_INSN_WRITE_ADDI, M32R2F_INSN_PAR_ADDV, M32R2F_INSN_WRITE_ADDV, M32R2F_INSN_PAR_ADDX + , M32R2F_INSN_WRITE_ADDX, M32R2F_INSN_PAR_BC8, M32R2F_INSN_WRITE_BC8, M32R2F_INSN_PAR_BL8 + , M32R2F_INSN_WRITE_BL8, M32R2F_INSN_PAR_BCL8, M32R2F_INSN_WRITE_BCL8, M32R2F_INSN_PAR_BNC8 + , M32R2F_INSN_WRITE_BNC8, M32R2F_INSN_PAR_BRA8, M32R2F_INSN_WRITE_BRA8, M32R2F_INSN_PAR_BNCL8 + , M32R2F_INSN_WRITE_BNCL8, M32R2F_INSN_PAR_CMP, M32R2F_INSN_WRITE_CMP, M32R2F_INSN_PAR_CMPU + , M32R2F_INSN_WRITE_CMPU, M32R2F_INSN_PAR_CMPEQ, M32R2F_INSN_WRITE_CMPEQ, M32R2F_INSN_PAR_CMPZ + , M32R2F_INSN_WRITE_CMPZ, M32R2F_INSN_PAR_JC, M32R2F_INSN_WRITE_JC, M32R2F_INSN_PAR_JNC + , M32R2F_INSN_WRITE_JNC, M32R2F_INSN_PAR_JL, M32R2F_INSN_WRITE_JL, M32R2F_INSN_PAR_JMP + , M32R2F_INSN_WRITE_JMP, M32R2F_INSN_PAR_LD, M32R2F_INSN_WRITE_LD, M32R2F_INSN_PAR_LDB + , M32R2F_INSN_WRITE_LDB, M32R2F_INSN_PAR_LDH, M32R2F_INSN_WRITE_LDH, M32R2F_INSN_PAR_LDUB + , M32R2F_INSN_WRITE_LDUB, M32R2F_INSN_PAR_LDUH, M32R2F_INSN_WRITE_LDUH, M32R2F_INSN_PAR_LD_PLUS + , M32R2F_INSN_WRITE_LD_PLUS, M32R2F_INSN_PAR_LDI8, M32R2F_INSN_WRITE_LDI8, M32R2F_INSN_PAR_LOCK + , M32R2F_INSN_WRITE_LOCK, M32R2F_INSN_PAR_MACHI_A, M32R2F_INSN_WRITE_MACHI_A, M32R2F_INSN_PAR_MACLO_A + , M32R2F_INSN_WRITE_MACLO_A, M32R2F_INSN_PAR_MACWHI_A, M32R2F_INSN_WRITE_MACWHI_A, M32R2F_INSN_PAR_MACWLO_A + , M32R2F_INSN_WRITE_MACWLO_A, M32R2F_INSN_PAR_MUL, M32R2F_INSN_WRITE_MUL, M32R2F_INSN_PAR_MULHI_A + , M32R2F_INSN_WRITE_MULHI_A, M32R2F_INSN_PAR_MULLO_A, M32R2F_INSN_WRITE_MULLO_A, M32R2F_INSN_PAR_MULWHI_A + , M32R2F_INSN_WRITE_MULWHI_A, M32R2F_INSN_PAR_MULWLO_A, M32R2F_INSN_WRITE_MULWLO_A, M32R2F_INSN_PAR_MV + , M32R2F_INSN_WRITE_MV, M32R2F_INSN_PAR_MVFACHI_A, M32R2F_INSN_WRITE_MVFACHI_A, M32R2F_INSN_PAR_MVFACLO_A + , M32R2F_INSN_WRITE_MVFACLO_A, M32R2F_INSN_PAR_MVFACMI_A, M32R2F_INSN_WRITE_MVFACMI_A, M32R2F_INSN_PAR_MVFC + , M32R2F_INSN_WRITE_MVFC, M32R2F_INSN_PAR_MVTACHI_A, M32R2F_INSN_WRITE_MVTACHI_A, M32R2F_INSN_PAR_MVTACLO_A + , M32R2F_INSN_WRITE_MVTACLO_A, M32R2F_INSN_PAR_MVTC, M32R2F_INSN_WRITE_MVTC, M32R2F_INSN_PAR_NEG + , M32R2F_INSN_WRITE_NEG, M32R2F_INSN_PAR_NOP, M32R2F_INSN_WRITE_NOP, M32R2F_INSN_PAR_NOT + , M32R2F_INSN_WRITE_NOT, M32R2F_INSN_PAR_RAC_DSI, M32R2F_INSN_WRITE_RAC_DSI, M32R2F_INSN_PAR_RACH_DSI + , M32R2F_INSN_WRITE_RACH_DSI, M32R2F_INSN_PAR_RTE, M32R2F_INSN_WRITE_RTE, M32R2F_INSN_PAR_SLL + , M32R2F_INSN_WRITE_SLL, M32R2F_INSN_PAR_SLLI, M32R2F_INSN_WRITE_SLLI, M32R2F_INSN_PAR_SRA + , M32R2F_INSN_WRITE_SRA, M32R2F_INSN_PAR_SRAI, M32R2F_INSN_WRITE_SRAI, M32R2F_INSN_PAR_SRL + , M32R2F_INSN_WRITE_SRL, M32R2F_INSN_PAR_SRLI, M32R2F_INSN_WRITE_SRLI, M32R2F_INSN_PAR_ST + , M32R2F_INSN_WRITE_ST, M32R2F_INSN_PAR_STB, M32R2F_INSN_WRITE_STB, M32R2F_INSN_PAR_STH + , M32R2F_INSN_WRITE_STH, M32R2F_INSN_PAR_ST_PLUS, M32R2F_INSN_WRITE_ST_PLUS, M32R2F_INSN_PAR_STH_PLUS + , M32R2F_INSN_WRITE_STH_PLUS, M32R2F_INSN_PAR_STB_PLUS, M32R2F_INSN_WRITE_STB_PLUS, M32R2F_INSN_PAR_ST_MINUS + , M32R2F_INSN_WRITE_ST_MINUS, M32R2F_INSN_PAR_SUB, M32R2F_INSN_WRITE_SUB, M32R2F_INSN_PAR_SUBV + , M32R2F_INSN_WRITE_SUBV, M32R2F_INSN_PAR_SUBX, M32R2F_INSN_WRITE_SUBX, M32R2F_INSN_PAR_TRAP + , M32R2F_INSN_WRITE_TRAP, M32R2F_INSN_PAR_UNLOCK, M32R2F_INSN_WRITE_UNLOCK, M32R2F_INSN_PAR_PCMPBZ + , M32R2F_INSN_WRITE_PCMPBZ, M32R2F_INSN_PAR_SADD, M32R2F_INSN_WRITE_SADD, M32R2F_INSN_PAR_MACWU1 + , M32R2F_INSN_WRITE_MACWU1, M32R2F_INSN_PAR_MSBLO, M32R2F_INSN_WRITE_MSBLO, M32R2F_INSN_PAR_MULWU1 + , M32R2F_INSN_WRITE_MULWU1, M32R2F_INSN_PAR_MACLH1, M32R2F_INSN_WRITE_MACLH1, M32R2F_INSN_PAR_SC + , M32R2F_INSN_WRITE_SC, M32R2F_INSN_PAR_SNC, M32R2F_INSN_WRITE_SNC, M32R2F_INSN_PAR_CLRPSW + , M32R2F_INSN_WRITE_CLRPSW, M32R2F_INSN_PAR_SETPSW, M32R2F_INSN_WRITE_SETPSW, M32R2F_INSN_PAR_BTST + , M32R2F_INSN_WRITE_BTST, M32R2F_INSN__MAX +} M32R2F_INSN_TYPE; + +/* Enum declaration for semantic formats in cpu family m32r2f. */ +typedef enum m32r2f_sfmt_type { + M32R2F_SFMT_EMPTY, M32R2F_SFMT_ADD, M32R2F_SFMT_ADD3, M32R2F_SFMT_AND3 + , M32R2F_SFMT_OR3, M32R2F_SFMT_ADDI, M32R2F_SFMT_ADDV, M32R2F_SFMT_ADDV3 + , M32R2F_SFMT_ADDX, M32R2F_SFMT_BC8, M32R2F_SFMT_BC24, M32R2F_SFMT_BEQ + , M32R2F_SFMT_BEQZ, M32R2F_SFMT_BL8, M32R2F_SFMT_BL24, M32R2F_SFMT_BCL8 + , M32R2F_SFMT_BCL24, M32R2F_SFMT_BRA8, M32R2F_SFMT_BRA24, M32R2F_SFMT_CMP + , M32R2F_SFMT_CMPI, M32R2F_SFMT_CMPZ, M32R2F_SFMT_DIV, M32R2F_SFMT_JC + , M32R2F_SFMT_JL, M32R2F_SFMT_JMP, M32R2F_SFMT_LD, M32R2F_SFMT_LD_D + , M32R2F_SFMT_LDB, M32R2F_SFMT_LDB_D, M32R2F_SFMT_LDH, M32R2F_SFMT_LDH_D + , M32R2F_SFMT_LD_PLUS, M32R2F_SFMT_LD24, M32R2F_SFMT_LDI8, M32R2F_SFMT_LDI16 + , M32R2F_SFMT_LOCK, M32R2F_SFMT_MACHI_A, M32R2F_SFMT_MULHI_A, M32R2F_SFMT_MV + , M32R2F_SFMT_MVFACHI_A, M32R2F_SFMT_MVFC, M32R2F_SFMT_MVTACHI_A, M32R2F_SFMT_MVTC + , M32R2F_SFMT_NOP, M32R2F_SFMT_RAC_DSI, M32R2F_SFMT_RTE, M32R2F_SFMT_SETH + , M32R2F_SFMT_SLL3, M32R2F_SFMT_SLLI, M32R2F_SFMT_ST, M32R2F_SFMT_ST_D + , M32R2F_SFMT_STB, M32R2F_SFMT_STB_D, M32R2F_SFMT_STH, M32R2F_SFMT_STH_D + , M32R2F_SFMT_ST_PLUS, M32R2F_SFMT_STH_PLUS, M32R2F_SFMT_STB_PLUS, M32R2F_SFMT_TRAP + , M32R2F_SFMT_UNLOCK, M32R2F_SFMT_SATB, M32R2F_SFMT_SAT, M32R2F_SFMT_SADD + , M32R2F_SFMT_MACWU1, M32R2F_SFMT_MSBLO, M32R2F_SFMT_MULWU1, M32R2F_SFMT_SC + , M32R2F_SFMT_CLRPSW, M32R2F_SFMT_SETPSW, M32R2F_SFMT_BSET, M32R2F_SFMT_BTST +} M32R2F_SFMT_TYPE; + +/* Function unit handlers (user written). */ + +extern int m32r2f_model_m32r2_u_store (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*src1*/, INT /*src2*/); +extern int m32r2f_model_m32r2_u_load (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*sr*/, INT /*dr*/); +extern int m32r2f_model_m32r2_u_cti (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*sr*/); +extern int m32r2f_model_m32r2_u_mac (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*src1*/, INT /*src2*/); +extern int m32r2f_model_m32r2_u_cmp (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*src1*/, INT /*src2*/); +extern int m32r2f_model_m32r2_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*sr*/, INT /*dr*/, INT /*dr*/); + +/* Profiling before/after handlers (user written) */ + +extern void m32r2f_model_insn_before (SIM_CPU *, int /*first_p*/); +extern void m32r2f_model_insn_after (SIM_CPU *, int /*last_p*/, int /*cycles*/); + +#endif /* M32R2F_DECODE_H */ diff --git a/sim/m32r/m32r2.c b/sim/m32r/m32r2.c new file mode 100644 index 0000000..594ce8a --- /dev/null +++ b/sim/m32r/m32r2.c @@ -0,0 +1,311 @@ +/* m32r2 simulator support code + Copyright (C) 1997, 1998, 2003 Free Software Foundation, Inc. + Contributed by Cygnus Support. + + This file is part of GDB, the GNU debugger. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#define WANT_CPU m32r2f +#define WANT_CPU_M32R2F + +#include "sim-main.h" +#include "cgen-mem.h" +#include "cgen-ops.h" + +/* The contents of BUF are in target byte order. */ + +int +m32r2f_fetch_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len) +{ + return m32rbf_fetch_register (current_cpu, rn, buf, len); +} + +/* The contents of BUF are in target byte order. */ + +int +m32r2f_store_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len) +{ + return m32rbf_store_register (current_cpu, rn, buf, len); +} + +/* Cover fns to get/set the control registers. + FIXME: Duplicated from m32r.c. The issue is structure offsets. */ + +USI +m32r2f_h_cr_get_handler (SIM_CPU *current_cpu, UINT cr) +{ + switch (cr) + { + case H_CR_PSW : /* PSW. */ + return (((CPU (h_bpsw) & 0xc1) << 8) + | ((CPU (h_psw) & 0xc0) << 0) + | GET_H_COND ()); + case H_CR_BBPSW : /* Backup backup psw. */ + return CPU (h_bbpsw) & 0xc1; + case H_CR_CBR : /* Condition bit. */ + return GET_H_COND (); + case H_CR_SPI : /* Interrupt stack pointer. */ + if (! GET_H_SM ()) + return CPU (h_gr[H_GR_SP]); + else + return CPU (h_cr[H_CR_SPI]); + case H_CR_SPU : /* User stack pointer. */ + if (GET_H_SM ()) + return CPU (h_gr[H_GR_SP]); + else + return CPU (h_cr[H_CR_SPU]); + case H_CR_BPC : /* Backup pc. */ + return CPU (h_cr[H_CR_BPC]) & 0xfffffffe; + case H_CR_BBPC : /* Backup backup pc. */ + return CPU (h_cr[H_CR_BBPC]) & 0xfffffffe; + case 4 : /* ??? unspecified, but apparently available */ + case 5 : /* ??? unspecified, but apparently available */ + return CPU (h_cr[cr]); + default : + return 0; + } +} + +void +m32r2f_h_cr_set_handler (SIM_CPU *current_cpu, UINT cr, USI newval) +{ + switch (cr) + { + case H_CR_PSW : /* psw */ + { + int old_sm = (CPU (h_psw) & 0x80) != 0; + int new_sm = (newval & 0x80) != 0; + CPU (h_bpsw) = (newval >> 8) & 0xff; + CPU (h_psw) = newval & 0xff; + SET_H_COND (newval & 1); + /* When switching stack modes, update the registers. */ + if (old_sm != new_sm) + { + if (old_sm) + { + /* Switching user -> system. */ + CPU (h_cr[H_CR_SPU]) = CPU (h_gr[H_GR_SP]); + CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPI]); + } + else + { + /* Switching system -> user. */ + CPU (h_cr[H_CR_SPI]) = CPU (h_gr[H_GR_SP]); + CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPU]); + } + } + break; + } + case H_CR_BBPSW : /* backup backup psw */ + CPU (h_bbpsw) = newval & 0xff; + break; + case H_CR_CBR : /* condition bit */ + SET_H_COND (newval & 1); + break; + case H_CR_SPI : /* interrupt stack pointer */ + if (! GET_H_SM ()) + CPU (h_gr[H_GR_SP]) = newval; + else + CPU (h_cr[H_CR_SPI]) = newval; + break; + case H_CR_SPU : /* user stack pointer */ + if (GET_H_SM ()) + CPU (h_gr[H_GR_SP]) = newval; + else + CPU (h_cr[H_CR_SPU]) = newval; + break; + case H_CR_BPC : /* backup pc */ + CPU (h_cr[H_CR_BPC]) = newval; + break; + case H_CR_BBPC : /* backup backup pc */ + CPU (h_cr[H_CR_BBPC]) = newval; + break; + case 4 : /* ??? unspecified, but apparently available */ + case 5 : /* ??? unspecified, but apparently available */ + CPU (h_cr[cr]) = newval; + break; + default : + /* ignore */ + break; + } +} + +/* Cover fns to access h-psw. */ + +UQI +m32r2f_h_psw_get_handler (SIM_CPU *current_cpu) +{ + return (CPU (h_psw) & 0xfe) | (CPU (h_cond) & 1); +} + +void +m32r2f_h_psw_set_handler (SIM_CPU *current_cpu, UQI newval) +{ + CPU (h_psw) = newval; + CPU (h_cond) = newval & 1; +} + +/* Cover fns to access h-accum. */ + +DI +m32r2f_h_accum_get_handler (SIM_CPU *current_cpu) +{ + /* Sign extend the top 8 bits. */ + DI r; + r = ANDDI (CPU (h_accum), MAKEDI (0xffffff, 0xffffffff)); + r = XORDI (r, MAKEDI (0x800000, 0)); + r = SUBDI (r, MAKEDI (0x800000, 0)); + return r; +} + +void +m32r2f_h_accum_set_handler (SIM_CPU *current_cpu, DI newval) +{ + CPU (h_accum) = newval; +} + +/* Cover fns to access h-accums. */ + +DI +m32r2f_h_accums_get_handler (SIM_CPU *current_cpu, UINT regno) +{ + /* FIXME: Yes, this is just a quick hack. */ + DI r; + if (regno == 0) + r = CPU (h_accum); + else + r = CPU (h_accums[1]); + /* Sign extend the top 8 bits. */ + r = ANDDI (r, MAKEDI (0xffffff, 0xffffffff)); + r = XORDI (r, MAKEDI (0x800000, 0)); + r = SUBDI (r, MAKEDI (0x800000, 0)); + return r; +} + +void +m32r2f_h_accums_set_handler (SIM_CPU *current_cpu, UINT regno, DI newval) +{ + /* FIXME: Yes, this is just a quick hack. */ + if (regno == 0) + CPU (h_accum) = newval; + else + CPU (h_accums[1]) = newval; +} + +#if WITH_PROFILE_MODEL_P + +/* Initialize cycle counting for an insn. + FIRST_P is non-zero if this is the first insn in a set of parallel + insns. */ + +void +m32r2f_model_insn_before (SIM_CPU *cpu, int first_p) +{ + m32rbf_model_insn_before (cpu, first_p); +} + +/* Record the cycles computed for an insn. + LAST_P is non-zero if this is the last insn in a set of parallel insns, + and we update the total cycle count. + CYCLES is the cycle count of the insn. */ + +void +m32r2f_model_insn_after (SIM_CPU *cpu, int last_p, int cycles) +{ + m32rbf_model_insn_after (cpu, last_p, cycles); +} + +static INLINE void +check_load_stall (SIM_CPU *cpu, int regno) +{ + UINT h_gr = CPU_M32R_MISC_PROFILE (cpu)->load_regs; + + if (regno != -1 + && (h_gr & (1 << regno)) != 0) + { + CPU_M32R_MISC_PROFILE (cpu)->load_stall += 2; + if (TRACE_INSN_P (cpu)) + cgen_trace_printf (cpu, " ; Load stall of 2 cycles."); + } +} + +int +m32r2f_model_m32r2_u_exec (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT sr, INT sr2, INT dr) +{ + check_load_stall (cpu, sr); + check_load_stall (cpu, sr2); + return idesc->timing->units[unit_num].done; +} + +int +m32r2f_model_m32r2_u_cmp (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT src1, INT src2) +{ + check_load_stall (cpu, src1); + check_load_stall (cpu, src2); + return idesc->timing->units[unit_num].done; +} + +int +m32r2f_model_m32r2_u_mac (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT src1, INT src2) +{ + check_load_stall (cpu, src1); + check_load_stall (cpu, src2); + return idesc->timing->units[unit_num].done; +} + +int +m32r2f_model_m32r2_u_cti (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT sr) +{ + PROFILE_DATA *profile = CPU_PROFILE_DATA (cpu); + int taken_p = (referenced & (1 << 1)) != 0; + + check_load_stall (cpu, sr); + if (taken_p) + { + CPU_M32R_MISC_PROFILE (cpu)->cti_stall += 2; + PROFILE_MODEL_TAKEN_COUNT (profile) += 1; + } + else + PROFILE_MODEL_UNTAKEN_COUNT (profile) += 1; + return idesc->timing->units[unit_num].done; +} + +int +m32r2f_model_m32r2_u_load (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT sr, INT dr) +{ + CPU_M32R_MISC_PROFILE (cpu)->load_regs_pending |= (1 << dr); + return idesc->timing->units[unit_num].done; +} + +int +m32r2f_model_m32r2_u_store (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT src1, INT src2) +{ + return idesc->timing->units[unit_num].done; +} + +#endif /* WITH_PROFILE_MODEL_P */ diff --git a/sim/m32r/mloop2.in b/sim/m32r/mloop2.in new file mode 100644 index 0000000..bb9b0b2 --- /dev/null +++ b/sim/m32r/mloop2.in @@ -0,0 +1,484 @@ +# Simulator main loop for m32r2. -*- C -*- +# Copyright (C) 1996, 1997, 1998, 2003 Free Software Foundation, Inc. +# +# This file is part of GDB, the GNU debugger. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2, or (at your option) +# any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License along +# with this program; if not, write to the Free Software Foundation, Inc., +# 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# Syntax: +# /bin/sh mainloop.in command +# +# Command is one of: +# +# init +# support +# extract-{simple,scache,pbb} +# {full,fast}-exec-{simple,scache,pbb} +# +# A target need only provide a "full" version of one of simple,scache,pbb. +# If the target wants it can also provide a fast version of same, or if +# the slow (full featured) version is `simple', then the fast version can be +# one of scache/pbb. +# A target can't provide more than this. + +# ??? After a few more ports are done, revisit. +# Will eventually need to machine generate a lot of this. + +case "x$1" in + +xsupport) + +cat <argbuf; + id1 = id1->par_idesc; + abuf->fields.write.abuf = &sc1->argbuf; + @cpu@_fill_argbuf (current_cpu, abuf, id1, pc, 0); + /* no need to set trace_p,profile_p */ +#if 0 /* not currently needed for id2 since results written directly */ + abuf = &sc[1].argbuf; + id2 = id2->par_idesc; + abuf->fields.write.abuf = &sc2->argbuf; + @cpu@_fill_argbuf (current_cpu, abuf, id2, pc + 2, 0); + /* no need to set trace_p,profile_p */ +#endif +} + +static INLINE const IDESC * +emit_16 (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn, + SCACHE *sc, int fast_p, int parallel_p) +{ + ARGBUF *abuf = &sc->argbuf; + const IDESC *id = @cpu@_decode (current_cpu, pc, insn, insn, abuf); + + if (parallel_p) + id = id->par_idesc; + @cpu@_fill_argbuf (current_cpu, abuf, id, pc, fast_p); + return id; +} + +static INLINE const IDESC * +emit_full16 (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn, SCACHE *sc, + int trace_p, int profile_p) +{ + const IDESC *id; + + @cpu@_emit_before (current_cpu, sc, pc, 1); + id = emit_16 (current_cpu, pc, insn, sc + 1, 0, 0); + @cpu@_emit_after (current_cpu, sc + 2, pc); + sc[1].argbuf.trace_p = trace_p; + sc[1].argbuf.profile_p = profile_p; + return id; +} + +static INLINE const IDESC * +emit_parallel (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn, + SCACHE *sc, int fast_p) +{ + const IDESC *id,*id2; + + /* Emit both insns, then emit a finisher-upper. + We speed things up by handling the second insn serially + [not parallelly]. Then the writeback only has to deal + with the first insn. */ + /* ??? Revisit to handle exceptions right. */ + + /* FIXME: No need to handle this parallely if second is nop. */ + id = emit_16 (current_cpu, pc, insn >> 16, sc, fast_p, 1); + + /* Note that this can never be a cti. No cti's go in the S pipeline. */ + id2 = emit_16 (current_cpu, pc + 2, insn & 0x7fff, sc + 1, fast_p, 0); + + /* Set sc/snc insns notion of where to skip to. */ + if (IDESC_SKIP_P (id)) + SEM_SKIP_COMPILE (current_cpu, sc, 1); + + /* Emit code to finish executing the semantics + (write back the results). */ + emit_par_finish (current_cpu, pc, sc + 2, sc, id, sc + 1, id2); + + return id; +} + +static INLINE const IDESC * +emit_full_parallel (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn, + SCACHE *sc, int trace_p, int profile_p) +{ + const IDESC *id,*id2; + + /* Emit both insns, then emit a finisher-upper. + We speed things up by handling the second insn serially + [not parallelly]. Then the writeback only has to deal + with the first insn. */ + /* ??? Revisit to handle exceptions right. */ + + @cpu@_emit_before (current_cpu, sc, pc, 1); + + /* FIXME: No need to handle this parallelly if second is nop. */ + id = emit_16 (current_cpu, pc, insn >> 16, sc + 1, 0, 1); + sc[1].argbuf.trace_p = trace_p; + sc[1].argbuf.profile_p = profile_p; + + @cpu@_emit_before (current_cpu, sc + 2, pc, 0); + + /* Note that this can never be a cti. No cti's go in the S pipeline. */ + id2 = emit_16 (current_cpu, pc + 2, insn & 0x7fff, sc + 3, 0, 0); + sc[3].argbuf.trace_p = trace_p; + sc[3].argbuf.profile_p = profile_p; + + /* Set sc/snc insns notion of where to skip to. */ + if (IDESC_SKIP_P (id)) + SEM_SKIP_COMPILE (current_cpu, sc, 4); + + /* Emit code to finish executing the semantics + (write back the results). */ + emit_par_finish (current_cpu, pc, sc + 4, sc + 1, id, sc + 3, id2); + + @cpu@_emit_after (current_cpu, sc + 5, pc); + + return id; +} + +static INLINE const IDESC * +emit_32 (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn, + SCACHE *sc, int fast_p) +{ + ARGBUF *abuf = &sc->argbuf; + const IDESC *id = @cpu@_decode (current_cpu, pc, + (USI) insn >> 16, insn, abuf); + + @cpu@_fill_argbuf (current_cpu, abuf, id, pc, fast_p); + return id; +} + +static INLINE const IDESC * +emit_full32 (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn, SCACHE *sc, + int trace_p, int profile_p) +{ + const IDESC *id; + + @cpu@_emit_before (current_cpu, sc, pc, 1); + id = emit_32 (current_cpu, pc, insn, sc + 1, 0); + @cpu@_emit_after (current_cpu, sc + 2, pc); + sc[1].argbuf.trace_p = trace_p; + sc[1].argbuf.profile_p = profile_p; + return id; +} + +EOF + +;; + +xinit) + +# Nothing needed. + +;; + +xextract-pbb) + +# Inputs: current_cpu, pc, sc, max_insns, FAST_P +# Outputs: sc, pc +# sc must be left pointing past the last created entry. +# pc must be left pointing past the last created entry. +# If the pbb is terminated by a cti insn, SET_CTI_VPC(sc) must be called +# to record the vpc of the cti insn. +# SET_INSN_COUNT(n) must be called to record number of real insns. + +cat < 0) + { + USI insn = GETIMEMUSI (current_cpu, pc); + if ((SI) insn < 0) + { + /* 32 bit insn */ + idesc = emit_32 (current_cpu, pc, insn, sc, 1); + ++sc; + --max_insns; + ++icount; + pc += 4; + if (IDESC_CTI_P (idesc)) + { + SET_CTI_VPC (sc - 1); + break; + } + } + else + { + if ((insn & 0x8000) != 0) /* parallel? */ + { + /* Yep. Here's the "interesting" [sic] part. */ + idesc = emit_parallel (current_cpu, pc, insn, sc, 1); + sc += 3; + max_insns -= 3; + icount += 2; + pc += 4; + if (IDESC_CTI_P (idesc)) + { + SET_CTI_VPC (sc - 3); + break; + } + } + else /* 2 serial 16 bit insns */ + { + idesc = emit_16 (current_cpu, pc, insn >> 16, sc, 1, 0); + ++sc; + --max_insns; + ++icount; + pc += 2; + if (IDESC_CTI_P (idesc)) + { + SET_CTI_VPC (sc - 1); + break; + } + /* While we're guaranteed that there's room to extract the + insn, when single stepping we can't; the pbb must stop + after the first insn. */ + if (max_insns == 0) + break; + idesc = emit_16 (current_cpu, pc, insn & 0x7fff, sc, 1, 0); + ++sc; + --max_insns; + ++icount; + pc += 2; + if (IDESC_CTI_P (idesc)) + { + SET_CTI_VPC (sc - 1); + break; + } + } + } + } + } + else /* ! FAST_P */ + { + while (max_insns > 0) + { + USI insn = GETIMEMUSI (current_cpu, pc); + int trace_p = PC_IN_TRACE_RANGE_P (current_cpu, pc); + int profile_p = PC_IN_PROFILE_RANGE_P (current_cpu, pc); + SCACHE *cti_sc; /* ??? tmp hack */ + if ((SI) insn < 0) + { + /* 32 bit insn + Only emit before/after handlers if necessary. */ + if (trace_p || profile_p) + { + idesc = emit_full32 (current_cpu, pc, insn, sc, + trace_p, profile_p); + cti_sc = sc + 1; + sc += 3; + max_insns -= 3; + } + else + { + idesc = emit_32 (current_cpu, pc, insn, sc, 0); + cti_sc = sc; + ++sc; + --max_insns; + } + ++icount; + pc += 4; + if (IDESC_CTI_P (idesc)) + { + SET_CTI_VPC (cti_sc); + break; + } + } + else + { + if ((insn & 0x8000) != 0) /* parallel? */ + { + /* Yep. Here's the "interesting" [sic] part. + Only emit before/after handlers if necessary. */ + if (trace_p || profile_p) + { + idesc = emit_full_parallel (current_cpu, pc, insn, sc, + trace_p, profile_p); + cti_sc = sc + 1; + sc += 6; + max_insns -= 6; + } + else + { + idesc = emit_parallel (current_cpu, pc, insn, sc, 0); + cti_sc = sc; + sc += 3; + max_insns -= 3; + } + icount += 2; + pc += 4; + if (IDESC_CTI_P (idesc)) + { + SET_CTI_VPC (cti_sc); + break; + } + } + else /* 2 serial 16 bit insns */ + { + /* Only emit before/after handlers if necessary. */ + if (trace_p || profile_p) + { + idesc = emit_full16 (current_cpu, pc, insn >> 16, sc, + trace_p, profile_p); + cti_sc = sc + 1; + sc += 3; + max_insns -= 3; + } + else + { + idesc = emit_16 (current_cpu, pc, insn >> 16, sc, 0, 0); + cti_sc = sc; + ++sc; + --max_insns; + } + ++icount; + pc += 2; + if (IDESC_CTI_P (idesc)) + { + SET_CTI_VPC (cti_sc); + break; + } + /* While we're guaranteed that there's room to extract the + insn, when single stepping we can't; the pbb must stop + after the first insn. */ + if (max_insns <= 0) + break; + /* Use the same trace/profile address for the 2nd insn. + Saves us having to compute it and they come in pairs + anyway (e.g. can never branch to the 2nd insn). */ + if (trace_p || profile_p) + { + idesc = emit_full16 (current_cpu, pc, insn & 0x7fff, sc, + trace_p, profile_p); + cti_sc = sc + 1; + sc += 3; + max_insns -= 3; + } + else + { + idesc = emit_16 (current_cpu, pc, insn & 0x7fff, sc, 0, 0); + cti_sc = sc; + ++sc; + --max_insns; + } + ++icount; + pc += 2; + if (IDESC_CTI_P (idesc)) + { + SET_CTI_VPC (cti_sc); + break; + } + } + } + } + } + + Finish: + SET_INSN_COUNT (icount); +} +EOF + +;; + +xfull-exec-pbb) + +# Inputs: current_cpu, vpc, FAST_P +# Outputs: vpc +# vpc is the virtual program counter. + +cat <&2 + exit 1 + ;; + +esac diff --git a/sim/m32r/model2.c b/sim/m32r/model2.c new file mode 100644 index 0000000..7328ea4 --- /dev/null +++ b/sim/m32r/model2.c @@ -0,0 +1,3253 @@ +/* Simulator model support for m32r2f. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. + +This file is part of the GNU simulators. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +*/ + +#define WANT_CPU m32r2f +#define WANT_CPU_M32R2F + +#include "sim-main.h" + +/* The profiling data is recorded here, but is accessed via the profiling + mechanism. After all, this is information for profiling. */ + +#if WITH_PROFILE_MODEL_P + +/* Model handlers for each insn. */ + +static int +model_m32r2_add (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_add.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_sr = FLD (in_sr); + in_dr = FLD (in_dr); + out_dr = FLD (out_dr); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_add3 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_add3.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_sr = FLD (in_sr); + out_dr = FLD (out_dr); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_and (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_add.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_sr = FLD (in_sr); + in_dr = FLD (in_dr); + out_dr = FLD (out_dr); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_and3 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_and3.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_sr = FLD (in_sr); + out_dr = FLD (out_dr); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_or (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_add.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_sr = FLD (in_sr); + in_dr = FLD (in_dr); + out_dr = FLD (out_dr); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_or3 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_and3.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_sr = FLD (in_sr); + out_dr = FLD (out_dr); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_xor (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_add.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_sr = FLD (in_sr); + in_dr = FLD (in_dr); + out_dr = FLD (out_dr); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_xor3 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_and3.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_sr = FLD (in_sr); + out_dr = FLD (out_dr); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_addi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_dr = FLD (in_dr); + out_dr = FLD (out_dr); + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_addv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_add.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_sr = FLD (in_sr); + in_dr = FLD (in_dr); + out_dr = FLD (out_dr); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_addv3 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_add3.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_sr = FLD (in_sr); + out_dr = FLD (out_dr); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_addx (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_add.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_sr = FLD (in_sr); + in_dr = FLD (in_dr); + out_dr = FLD (out_dr); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_bc8 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bl8.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = -1; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_bc24 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bl24.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = -1; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_beq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = -1; + if (insn_referenced & (1 << 3)) referenced |= 1 << 1; + cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr); + } + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_src1 = -1; + INT in_src2 = -1; + in_src1 = FLD (in_src1); + in_src2 = FLD (in_src2); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_beqz (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = -1; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr); + } + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_src1 = -1; + INT in_src2 = -1; + in_src2 = FLD (in_src2); + referenced |= 1 << 1; + cycles += m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_bgez (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = -1; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr); + } + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_src1 = -1; + INT in_src2 = -1; + in_src2 = FLD (in_src2); + referenced |= 1 << 1; + cycles += m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_bgtz (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = -1; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr); + } + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_src1 = -1; + INT in_src2 = -1; + in_src2 = FLD (in_src2); + referenced |= 1 << 1; + cycles += m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_blez (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = -1; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr); + } + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_src1 = -1; + INT in_src2 = -1; + in_src2 = FLD (in_src2); + referenced |= 1 << 1; + cycles += m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_bltz (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = -1; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr); + } + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_src1 = -1; + INT in_src2 = -1; + in_src2 = FLD (in_src2); + referenced |= 1 << 1; + cycles += m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_bnez (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = -1; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr); + } + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_src1 = -1; + INT in_src2 = -1; + in_src2 = FLD (in_src2); + referenced |= 1 << 1; + cycles += m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_bl8 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bl8.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = -1; + referenced |= 1 << 1; + cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_bl24 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bl24.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = -1; + referenced |= 1 << 1; + cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_bcl8 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bl8.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = -1; + if (insn_referenced & (1 << 4)) referenced |= 1 << 1; + cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_bcl24 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bl24.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = -1; + if (insn_referenced & (1 << 4)) referenced |= 1 << 1; + cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_bnc8 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bl8.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = -1; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_bnc24 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bl24.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = -1; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_bne (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = -1; + if (insn_referenced & (1 << 3)) referenced |= 1 << 1; + cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr); + } + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_src1 = -1; + INT in_src2 = -1; + in_src1 = FLD (in_src1); + in_src2 = FLD (in_src2); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_bra8 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bl8.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = -1; + referenced |= 1 << 1; + cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_bra24 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bl24.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = -1; + referenced |= 1 << 1; + cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_bncl8 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bl8.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = -1; + if (insn_referenced & (1 << 4)) referenced |= 1 << 1; + cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_bncl24 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bl24.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = -1; + if (insn_referenced & (1 << 4)) referenced |= 1 << 1; + cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_cmp (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_st_plus.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_src1 = -1; + INT in_src2 = -1; + in_src1 = FLD (in_src1); + in_src2 = FLD (in_src2); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_cmpi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_st_d.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_src1 = -1; + INT in_src2 = -1; + in_src2 = FLD (in_src2); + referenced |= 1 << 1; + cycles += m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_cmpu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_st_plus.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_src1 = -1; + INT in_src2 = -1; + in_src1 = FLD (in_src1); + in_src2 = FLD (in_src2); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_cmpui (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_st_d.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_src1 = -1; + INT in_src2 = -1; + in_src2 = FLD (in_src2); + referenced |= 1 << 1; + cycles += m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_cmpeq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_st_plus.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_src1 = -1; + INT in_src2 = -1; + in_src1 = FLD (in_src1); + in_src2 = FLD (in_src2); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_cmpz (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_st_plus.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_src1 = -1; + INT in_src2 = -1; + in_src2 = FLD (in_src2); + referenced |= 1 << 1; + cycles += m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_div (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_add.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_sr = FLD (in_sr); + in_dr = FLD (in_dr); + out_dr = FLD (out_dr); + referenced |= 1 << 0; + if (insn_referenced & (1 << 0)) referenced |= 1 << 1; + if (insn_referenced & (1 << 2)) referenced |= 1 << 2; + cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_divu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_add.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_sr = FLD (in_sr); + in_dr = FLD (in_dr); + out_dr = FLD (out_dr); + referenced |= 1 << 0; + if (insn_referenced & (1 << 0)) referenced |= 1 << 1; + if (insn_referenced & (1 << 2)) referenced |= 1 << 2; + cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_rem (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_add.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_sr = FLD (in_sr); + in_dr = FLD (in_dr); + out_dr = FLD (out_dr); + referenced |= 1 << 0; + if (insn_referenced & (1 << 0)) referenced |= 1 << 1; + if (insn_referenced & (1 << 2)) referenced |= 1 << 2; + cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_remu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_add.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_sr = FLD (in_sr); + in_dr = FLD (in_dr); + out_dr = FLD (out_dr); + referenced |= 1 << 0; + if (insn_referenced & (1 << 0)) referenced |= 1 << 1; + if (insn_referenced & (1 << 2)) referenced |= 1 << 2; + cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_remh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_add.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_sr = FLD (in_sr); + in_dr = FLD (in_dr); + out_dr = FLD (out_dr); + referenced |= 1 << 0; + if (insn_referenced & (1 << 0)) referenced |= 1 << 1; + if (insn_referenced & (1 << 2)) referenced |= 1 << 2; + cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_remuh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_add.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_sr = FLD (in_sr); + in_dr = FLD (in_dr); + out_dr = FLD (out_dr); + referenced |= 1 << 0; + if (insn_referenced & (1 << 0)) referenced |= 1 << 1; + if (insn_referenced & (1 << 2)) referenced |= 1 << 2; + cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_remb (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_add.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_sr = FLD (in_sr); + in_dr = FLD (in_dr); + out_dr = FLD (out_dr); + referenced |= 1 << 0; + if (insn_referenced & (1 << 0)) referenced |= 1 << 1; + if (insn_referenced & (1 << 2)) referenced |= 1 << 2; + cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_remub (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_add.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_sr = FLD (in_sr); + in_dr = FLD (in_dr); + out_dr = FLD (out_dr); + referenced |= 1 << 0; + if (insn_referenced & (1 << 0)) referenced |= 1 << 1; + if (insn_referenced & (1 << 2)) referenced |= 1 << 2; + cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_divuh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_add.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_sr = FLD (in_sr); + in_dr = FLD (in_dr); + out_dr = FLD (out_dr); + referenced |= 1 << 0; + if (insn_referenced & (1 << 0)) referenced |= 1 << 1; + if (insn_referenced & (1 << 2)) referenced |= 1 << 2; + cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_divb (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_add.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_sr = FLD (in_sr); + in_dr = FLD (in_dr); + out_dr = FLD (out_dr); + referenced |= 1 << 0; + if (insn_referenced & (1 << 0)) referenced |= 1 << 1; + if (insn_referenced & (1 << 2)) referenced |= 1 << 2; + cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_divub (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_add.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_sr = FLD (in_sr); + in_dr = FLD (in_dr); + out_dr = FLD (out_dr); + referenced |= 1 << 0; + if (insn_referenced & (1 << 0)) referenced |= 1 << 1; + if (insn_referenced & (1 << 2)) referenced |= 1 << 2; + cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_divh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_add.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_sr = FLD (in_sr); + in_dr = FLD (in_dr); + out_dr = FLD (out_dr); + referenced |= 1 << 0; + if (insn_referenced & (1 << 0)) referenced |= 1 << 1; + if (insn_referenced & (1 << 2)) referenced |= 1 << 2; + cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_jc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_jl.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = -1; + in_sr = FLD (in_sr); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_jnc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_jl.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = -1; + in_sr = FLD (in_sr); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_jl (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_jl.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = -1; + in_sr = FLD (in_sr); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_jmp (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_jl.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = -1; + in_sr = FLD (in_sr); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_ld (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ld_plus.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = 0; + INT out_dr = 0; + in_sr = FLD (in_sr); + out_dr = FLD (out_dr); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += m32r2f_model_m32r2_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_ld_d (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_add3.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = 0; + INT out_dr = 0; + in_sr = FLD (in_sr); + out_dr = FLD (out_dr); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += m32r2f_model_m32r2_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_ldb (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ld_plus.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = 0; + INT out_dr = 0; + in_sr = FLD (in_sr); + out_dr = FLD (out_dr); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += m32r2f_model_m32r2_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_ldb_d (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_add3.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = 0; + INT out_dr = 0; + in_sr = FLD (in_sr); + out_dr = FLD (out_dr); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += m32r2f_model_m32r2_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_ldh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ld_plus.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = 0; + INT out_dr = 0; + in_sr = FLD (in_sr); + out_dr = FLD (out_dr); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += m32r2f_model_m32r2_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_ldh_d (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_add3.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = 0; + INT out_dr = 0; + in_sr = FLD (in_sr); + out_dr = FLD (out_dr); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += m32r2f_model_m32r2_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_ldub (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ld_plus.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = 0; + INT out_dr = 0; + in_sr = FLD (in_sr); + out_dr = FLD (out_dr); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += m32r2f_model_m32r2_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_ldub_d (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_add3.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = 0; + INT out_dr = 0; + in_sr = FLD (in_sr); + out_dr = FLD (out_dr); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += m32r2f_model_m32r2_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_lduh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ld_plus.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = 0; + INT out_dr = 0; + in_sr = FLD (in_sr); + out_dr = FLD (out_dr); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += m32r2f_model_m32r2_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_lduh_d (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_add3.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = 0; + INT out_dr = 0; + in_sr = FLD (in_sr); + out_dr = FLD (out_dr); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += m32r2f_model_m32r2_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_ld_plus (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ld_plus.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = 0; + INT out_dr = 0; + in_sr = FLD (in_sr); + out_dr = FLD (out_dr); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += m32r2f_model_m32r2_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr); + } + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_dr = FLD (in_sr); + out_dr = FLD (out_sr); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 1, referenced, in_sr, in_dr, out_dr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_ld24 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ld24.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + out_dr = FLD (out_dr); + referenced |= 1 << 2; + cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_ldi8 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + out_dr = FLD (out_dr); + referenced |= 1 << 2; + cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_ldi16 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_add3.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + out_dr = FLD (out_dr); + referenced |= 1 << 2; + cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_lock (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ld_plus.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = 0; + INT out_dr = 0; + in_sr = FLD (in_sr); + out_dr = FLD (out_dr); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += m32r2f_model_m32r2_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_machi_a (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_machi_a.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_src1 = -1; + INT in_src2 = -1; + in_src1 = FLD (in_src1); + in_src2 = FLD (in_src2); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_maclo_a (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_machi_a.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_src1 = -1; + INT in_src2 = -1; + in_src1 = FLD (in_src1); + in_src2 = FLD (in_src2); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_macwhi_a (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_machi_a.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_src1 = -1; + INT in_src2 = -1; + in_src1 = FLD (in_src1); + in_src2 = FLD (in_src2); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_macwlo_a (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_machi_a.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_src1 = -1; + INT in_src2 = -1; + in_src1 = FLD (in_src1); + in_src2 = FLD (in_src2); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_mul (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_add.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_sr = FLD (in_sr); + in_dr = FLD (in_dr); + out_dr = FLD (out_dr); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_mulhi_a (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_machi_a.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_src1 = -1; + INT in_src2 = -1; + in_src1 = FLD (in_src1); + in_src2 = FLD (in_src2); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_mullo_a (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_machi_a.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_src1 = -1; + INT in_src2 = -1; + in_src1 = FLD (in_src1); + in_src2 = FLD (in_src2); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_mulwhi_a (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_machi_a.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_src1 = -1; + INT in_src2 = -1; + in_src1 = FLD (in_src1); + in_src2 = FLD (in_src2); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_mulwlo_a (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_machi_a.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_src1 = -1; + INT in_src2 = -1; + in_src1 = FLD (in_src1); + in_src2 = FLD (in_src2); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_mv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ld_plus.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_sr = FLD (in_sr); + out_dr = FLD (out_dr); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_mvfachi_a (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mvfachi_a.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + out_dr = FLD (out_dr); + referenced |= 1 << 2; + cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_mvfaclo_a (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mvfachi_a.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + out_dr = FLD (out_dr); + referenced |= 1 << 2; + cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_mvfacmi_a (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mvfachi_a.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + out_dr = FLD (out_dr); + referenced |= 1 << 2; + cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_mvfc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ld_plus.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + out_dr = FLD (out_dr); + referenced |= 1 << 2; + cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_mvtachi_a (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mvtachi_a.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_sr = FLD (in_src1); + cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_mvtaclo_a (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mvtachi_a.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_sr = FLD (in_src1); + cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_mvtc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ld_plus.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_sr = FLD (in_sr); + referenced |= 1 << 0; + cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_neg (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ld_plus.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_sr = FLD (in_sr); + out_dr = FLD (out_dr); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_nop (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_not (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ld_plus.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_sr = FLD (in_sr); + out_dr = FLD (out_dr); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_rac_dsi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_rac_dsi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_src1 = -1; + INT in_src2 = -1; + cycles += m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_rach_dsi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_rac_dsi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_src1 = -1; + INT in_src2 = -1; + cycles += m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_rte (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_seth (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_seth.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + out_dr = FLD (out_dr); + referenced |= 1 << 2; + cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_sll (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_add.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_sr = FLD (in_sr); + in_dr = FLD (in_dr); + out_dr = FLD (out_dr); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_sll3 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_add3.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_sr = FLD (in_sr); + out_dr = FLD (out_dr); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_slli (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_slli.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_dr = FLD (in_dr); + out_dr = FLD (out_dr); + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_sra (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_add.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_sr = FLD (in_sr); + in_dr = FLD (in_dr); + out_dr = FLD (out_dr); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_sra3 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_add3.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_sr = FLD (in_sr); + out_dr = FLD (out_dr); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_srai (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_slli.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_dr = FLD (in_dr); + out_dr = FLD (out_dr); + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_srl (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_add.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_sr = FLD (in_sr); + in_dr = FLD (in_dr); + out_dr = FLD (out_dr); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_srl3 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_add3.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_sr = FLD (in_sr); + out_dr = FLD (out_dr); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_srli (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_slli.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_dr = FLD (in_dr); + out_dr = FLD (out_dr); + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_st (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_st_plus.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_src1 = 0; + INT in_src2 = 0; + in_src1 = FLD (in_src1); + in_src2 = FLD (in_src2); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += m32r2f_model_m32r2_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_st_d (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_st_d.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_src1 = 0; + INT in_src2 = 0; + in_src1 = FLD (in_src1); + in_src2 = FLD (in_src2); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += m32r2f_model_m32r2_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_stb (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_st_plus.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_src1 = 0; + INT in_src2 = 0; + in_src1 = FLD (in_src1); + in_src2 = FLD (in_src2); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += m32r2f_model_m32r2_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_stb_d (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_st_d.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_src1 = 0; + INT in_src2 = 0; + in_src1 = FLD (in_src1); + in_src2 = FLD (in_src2); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += m32r2f_model_m32r2_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_sth (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_st_plus.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_src1 = 0; + INT in_src2 = 0; + in_src1 = FLD (in_src1); + in_src2 = FLD (in_src2); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += m32r2f_model_m32r2_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_sth_d (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_st_d.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_src1 = 0; + INT in_src2 = 0; + in_src1 = FLD (in_src1); + in_src2 = FLD (in_src2); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += m32r2f_model_m32r2_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_st_plus (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_st_plus.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_src1 = 0; + INT in_src2 = 0; + in_src1 = FLD (in_src1); + in_src2 = FLD (in_src2); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += m32r2f_model_m32r2_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2); + } + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_dr = FLD (in_src2); + out_dr = FLD (out_src2); + cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 1, referenced, in_sr, in_dr, out_dr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_sth_plus (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_st_plus.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_src1 = 0; + INT in_src2 = 0; + in_src1 = FLD (in_src1); + in_src2 = FLD (in_src2); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += m32r2f_model_m32r2_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2); + } + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_dr = FLD (in_src2); + out_dr = FLD (out_src2); + cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 1, referenced, in_sr, in_dr, out_dr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_stb_plus (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_st_plus.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_src1 = 0; + INT in_src2 = 0; + in_src1 = FLD (in_src1); + in_src2 = FLD (in_src2); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += m32r2f_model_m32r2_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2); + } + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_dr = FLD (in_src2); + out_dr = FLD (out_src2); + cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 1, referenced, in_sr, in_dr, out_dr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_st_minus (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_st_plus.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_src1 = 0; + INT in_src2 = 0; + in_src1 = FLD (in_src1); + in_src2 = FLD (in_src2); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += m32r2f_model_m32r2_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2); + } + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_dr = FLD (in_src2); + out_dr = FLD (out_src2); + cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 1, referenced, in_sr, in_dr, out_dr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_sub (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_add.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_sr = FLD (in_sr); + in_dr = FLD (in_dr); + out_dr = FLD (out_dr); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_subv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_add.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_sr = FLD (in_sr); + in_dr = FLD (in_dr); + out_dr = FLD (out_dr); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_subx (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_add.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_sr = FLD (in_sr); + in_dr = FLD (in_dr); + out_dr = FLD (out_dr); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_trap (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_trap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_unlock (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_st_plus.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = 0; + INT out_dr = 0; + cycles += m32r2f_model_m32r2_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_satb (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ld_plus.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_sr = FLD (in_sr); + out_dr = FLD (out_dr); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_sath (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ld_plus.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_sr = FLD (in_sr); + out_dr = FLD (out_dr); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_sat (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ld_plus.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_sr = FLD (in_sr); + out_dr = FLD (out_dr); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_pcmpbz (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_st_plus.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_src1 = -1; + INT in_src2 = -1; + in_src2 = FLD (in_src2); + referenced |= 1 << 1; + cycles += m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_sadd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_src1 = -1; + INT in_src2 = -1; + cycles += m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_macwu1 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_st_plus.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_src1 = -1; + INT in_src2 = -1; + in_src1 = FLD (in_src1); + in_src2 = FLD (in_src2); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_msblo (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_st_plus.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_src1 = -1; + INT in_src2 = -1; + in_src1 = FLD (in_src1); + in_src2 = FLD (in_src2); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_mulwu1 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_st_plus.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_src1 = -1; + INT in_src2 = -1; + in_src1 = FLD (in_src1); + in_src2 = FLD (in_src2); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_maclh1 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_st_plus.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_src1 = -1; + INT in_src2 = -1; + in_src1 = FLD (in_src1); + in_src2 = FLD (in_src2); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_sc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_snc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_clrpsw (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clrpsw.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_setpsw (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clrpsw.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_bset (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bset.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_sr = FLD (in_sr); + referenced |= 1 << 0; + cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_bclr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bset.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_sr = FLD (in_sr); + referenced |= 1 << 0; + cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); + } + return cycles; +#undef FLD +} + +static int +model_m32r2_btst (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bset.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_sr = FLD (in_sr); + referenced |= 1 << 0; + cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); + } + return cycles; +#undef FLD +} + +/* We assume UNIT_NONE == 0 because the tables don't always terminate + entries with it. */ + +/* Model timing data for `m32r2'. */ + +static const INSN_TIMING m32r2_timing[] = { + { M32R2F_INSN_X_INVALID, 0, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } }, + { M32R2F_INSN_X_AFTER, 0, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } }, + { M32R2F_INSN_X_BEFORE, 0, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } }, + { M32R2F_INSN_X_CTI_CHAIN, 0, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } }, + { M32R2F_INSN_X_CHAIN, 0, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } }, + { M32R2F_INSN_X_BEGIN, 0, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } }, + { M32R2F_INSN_ADD, model_m32r2_add, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } }, + { M32R2F_INSN_ADD3, model_m32r2_add3, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } }, + { M32R2F_INSN_AND, model_m32r2_and, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } }, + { M32R2F_INSN_AND3, model_m32r2_and3, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } }, + { M32R2F_INSN_OR, model_m32r2_or, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } }, + { M32R2F_INSN_OR3, model_m32r2_or3, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } }, + { M32R2F_INSN_XOR, model_m32r2_xor, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } }, + { M32R2F_INSN_XOR3, model_m32r2_xor3, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } }, + { M32R2F_INSN_ADDI, model_m32r2_addi, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } }, + { M32R2F_INSN_ADDV, model_m32r2_addv, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } }, + { M32R2F_INSN_ADDV3, model_m32r2_addv3, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } }, + { M32R2F_INSN_ADDX, model_m32r2_addx, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } }, + { M32R2F_INSN_BC8, model_m32r2_bc8, { { (int) UNIT_M32R2_U_CTI, 1, 1 } } }, + { M32R2F_INSN_BC24, model_m32r2_bc24, { { (int) UNIT_M32R2_U_CTI, 1, 1 } } }, + { M32R2F_INSN_BEQ, model_m32r2_beq, { { (int) UNIT_M32R2_U_CTI, 1, 1 }, { (int) UNIT_M32R2_U_CMP, 1, 0 } } }, + { M32R2F_INSN_BEQZ, model_m32r2_beqz, { { (int) UNIT_M32R2_U_CTI, 1, 1 }, { (int) UNIT_M32R2_U_CMP, 1, 0 } } }, + { M32R2F_INSN_BGEZ, model_m32r2_bgez, { { (int) UNIT_M32R2_U_CTI, 1, 1 }, { (int) UNIT_M32R2_U_CMP, 1, 0 } } }, + { M32R2F_INSN_BGTZ, model_m32r2_bgtz, { { (int) UNIT_M32R2_U_CTI, 1, 1 }, { (int) UNIT_M32R2_U_CMP, 1, 0 } } }, + { M32R2F_INSN_BLEZ, model_m32r2_blez, { { (int) UNIT_M32R2_U_CTI, 1, 1 }, { (int) UNIT_M32R2_U_CMP, 1, 0 } } }, + { M32R2F_INSN_BLTZ, model_m32r2_bltz, { { (int) UNIT_M32R2_U_CTI, 1, 1 }, { (int) UNIT_M32R2_U_CMP, 1, 0 } } }, + { M32R2F_INSN_BNEZ, model_m32r2_bnez, { { (int) UNIT_M32R2_U_CTI, 1, 1 }, { (int) UNIT_M32R2_U_CMP, 1, 0 } } }, + { M32R2F_INSN_BL8, model_m32r2_bl8, { { (int) UNIT_M32R2_U_CTI, 1, 1 } } }, + { M32R2F_INSN_BL24, model_m32r2_bl24, { { (int) UNIT_M32R2_U_CTI, 1, 1 } } }, + { M32R2F_INSN_BCL8, model_m32r2_bcl8, { { (int) UNIT_M32R2_U_CTI, 1, 1 } } }, + { M32R2F_INSN_BCL24, model_m32r2_bcl24, { { (int) UNIT_M32R2_U_CTI, 1, 1 } } }, + { M32R2F_INSN_BNC8, model_m32r2_bnc8, { { (int) UNIT_M32R2_U_CTI, 1, 1 } } }, + { M32R2F_INSN_BNC24, model_m32r2_bnc24, { { (int) UNIT_M32R2_U_CTI, 1, 1 } } }, + { M32R2F_INSN_BNE, model_m32r2_bne, { { (int) UNIT_M32R2_U_CTI, 1, 1 }, { (int) UNIT_M32R2_U_CMP, 1, 0 } } }, + { M32R2F_INSN_BRA8, model_m32r2_bra8, { { (int) UNIT_M32R2_U_CTI, 1, 1 } } }, + { M32R2F_INSN_BRA24, model_m32r2_bra24, { { (int) UNIT_M32R2_U_CTI, 1, 1 } } }, + { M32R2F_INSN_BNCL8, model_m32r2_bncl8, { { (int) UNIT_M32R2_U_CTI, 1, 1 } } }, + { M32R2F_INSN_BNCL24, model_m32r2_bncl24, { { (int) UNIT_M32R2_U_CTI, 1, 1 } } }, + { M32R2F_INSN_CMP, model_m32r2_cmp, { { (int) UNIT_M32R2_U_CMP, 1, 1 } } }, + { M32R2F_INSN_CMPI, model_m32r2_cmpi, { { (int) UNIT_M32R2_U_CMP, 1, 1 } } }, + { M32R2F_INSN_CMPU, model_m32r2_cmpu, { { (int) UNIT_M32R2_U_CMP, 1, 1 } } }, + { M32R2F_INSN_CMPUI, model_m32r2_cmpui, { { (int) UNIT_M32R2_U_CMP, 1, 1 } } }, + { M32R2F_INSN_CMPEQ, model_m32r2_cmpeq, { { (int) UNIT_M32R2_U_CMP, 1, 1 } } }, + { M32R2F_INSN_CMPZ, model_m32r2_cmpz, { { (int) UNIT_M32R2_U_CMP, 1, 1 } } }, + { M32R2F_INSN_DIV, model_m32r2_div, { { (int) UNIT_M32R2_U_EXEC, 1, 37 } } }, + { M32R2F_INSN_DIVU, model_m32r2_divu, { { (int) UNIT_M32R2_U_EXEC, 1, 37 } } }, + { M32R2F_INSN_REM, model_m32r2_rem, { { (int) UNIT_M32R2_U_EXEC, 1, 37 } } }, + { M32R2F_INSN_REMU, model_m32r2_remu, { { (int) UNIT_M32R2_U_EXEC, 1, 37 } } }, + { M32R2F_INSN_REMH, model_m32r2_remh, { { (int) UNIT_M32R2_U_EXEC, 1, 21 } } }, + { M32R2F_INSN_REMUH, model_m32r2_remuh, { { (int) UNIT_M32R2_U_EXEC, 1, 21 } } }, + { M32R2F_INSN_REMB, model_m32r2_remb, { { (int) UNIT_M32R2_U_EXEC, 1, 21 } } }, + { M32R2F_INSN_REMUB, model_m32r2_remub, { { (int) UNIT_M32R2_U_EXEC, 1, 21 } } }, + { M32R2F_INSN_DIVUH, model_m32r2_divuh, { { (int) UNIT_M32R2_U_EXEC, 1, 21 } } }, + { M32R2F_INSN_DIVB, model_m32r2_divb, { { (int) UNIT_M32R2_U_EXEC, 1, 21 } } }, + { M32R2F_INSN_DIVUB, model_m32r2_divub, { { (int) UNIT_M32R2_U_EXEC, 1, 21 } } }, + { M32R2F_INSN_DIVH, model_m32r2_divh, { { (int) UNIT_M32R2_U_EXEC, 1, 21 } } }, + { M32R2F_INSN_JC, model_m32r2_jc, { { (int) UNIT_M32R2_U_CTI, 1, 1 } } }, + { M32R2F_INSN_JNC, model_m32r2_jnc, { { (int) UNIT_M32R2_U_CTI, 1, 1 } } }, + { M32R2F_INSN_JL, model_m32r2_jl, { { (int) UNIT_M32R2_U_CTI, 1, 1 } } }, + { M32R2F_INSN_JMP, model_m32r2_jmp, { { (int) UNIT_M32R2_U_CTI, 1, 1 } } }, + { M32R2F_INSN_LD, model_m32r2_ld, { { (int) UNIT_M32R2_U_LOAD, 1, 1 } } }, + { M32R2F_INSN_LD_D, model_m32r2_ld_d, { { (int) UNIT_M32R2_U_LOAD, 1, 2 } } }, + { M32R2F_INSN_LDB, model_m32r2_ldb, { { (int) UNIT_M32R2_U_LOAD, 1, 1 } } }, + { M32R2F_INSN_LDB_D, model_m32r2_ldb_d, { { (int) UNIT_M32R2_U_LOAD, 1, 2 } } }, + { M32R2F_INSN_LDH, model_m32r2_ldh, { { (int) UNIT_M32R2_U_LOAD, 1, 1 } } }, + { M32R2F_INSN_LDH_D, model_m32r2_ldh_d, { { (int) UNIT_M32R2_U_LOAD, 1, 2 } } }, + { M32R2F_INSN_LDUB, model_m32r2_ldub, { { (int) UNIT_M32R2_U_LOAD, 1, 1 } } }, + { M32R2F_INSN_LDUB_D, model_m32r2_ldub_d, { { (int) UNIT_M32R2_U_LOAD, 1, 2 } } }, + { M32R2F_INSN_LDUH, model_m32r2_lduh, { { (int) UNIT_M32R2_U_LOAD, 1, 1 } } }, + { M32R2F_INSN_LDUH_D, model_m32r2_lduh_d, { { (int) UNIT_M32R2_U_LOAD, 1, 2 } } }, + { M32R2F_INSN_LD_PLUS, model_m32r2_ld_plus, { { (int) UNIT_M32R2_U_LOAD, 1, 1 }, { (int) UNIT_M32R2_U_EXEC, 1, 0 } } }, + { M32R2F_INSN_LD24, model_m32r2_ld24, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } }, + { M32R2F_INSN_LDI8, model_m32r2_ldi8, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } }, + { M32R2F_INSN_LDI16, model_m32r2_ldi16, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } }, + { M32R2F_INSN_LOCK, model_m32r2_lock, { { (int) UNIT_M32R2_U_LOAD, 1, 1 } } }, + { M32R2F_INSN_MACHI_A, model_m32r2_machi_a, { { (int) UNIT_M32R2_U_MAC, 1, 1 } } }, + { M32R2F_INSN_MACLO_A, model_m32r2_maclo_a, { { (int) UNIT_M32R2_U_MAC, 1, 1 } } }, + { M32R2F_INSN_MACWHI_A, model_m32r2_macwhi_a, { { (int) UNIT_M32R2_U_MAC, 1, 1 } } }, + { M32R2F_INSN_MACWLO_A, model_m32r2_macwlo_a, { { (int) UNIT_M32R2_U_MAC, 1, 1 } } }, + { M32R2F_INSN_MUL, model_m32r2_mul, { { (int) UNIT_M32R2_U_EXEC, 1, 4 } } }, + { M32R2F_INSN_MULHI_A, model_m32r2_mulhi_a, { { (int) UNIT_M32R2_U_MAC, 1, 1 } } }, + { M32R2F_INSN_MULLO_A, model_m32r2_mullo_a, { { (int) UNIT_M32R2_U_MAC, 1, 1 } } }, + { M32R2F_INSN_MULWHI_A, model_m32r2_mulwhi_a, { { (int) UNIT_M32R2_U_MAC, 1, 1 } } }, + { M32R2F_INSN_MULWLO_A, model_m32r2_mulwlo_a, { { (int) UNIT_M32R2_U_MAC, 1, 1 } } }, + { M32R2F_INSN_MV, model_m32r2_mv, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } }, + { M32R2F_INSN_MVFACHI_A, model_m32r2_mvfachi_a, { { (int) UNIT_M32R2_U_EXEC, 1, 2 } } }, + { M32R2F_INSN_MVFACLO_A, model_m32r2_mvfaclo_a, { { (int) UNIT_M32R2_U_EXEC, 1, 2 } } }, + { M32R2F_INSN_MVFACMI_A, model_m32r2_mvfacmi_a, { { (int) UNIT_M32R2_U_EXEC, 1, 2 } } }, + { M32R2F_INSN_MVFC, model_m32r2_mvfc, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } }, + { M32R2F_INSN_MVTACHI_A, model_m32r2_mvtachi_a, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } }, + { M32R2F_INSN_MVTACLO_A, model_m32r2_mvtaclo_a, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } }, + { M32R2F_INSN_MVTC, model_m32r2_mvtc, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } }, + { M32R2F_INSN_NEG, model_m32r2_neg, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } }, + { M32R2F_INSN_NOP, model_m32r2_nop, { { (int) UNIT_M32R2_U_EXEC, 1, 0 } } }, + { M32R2F_INSN_NOT, model_m32r2_not, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } }, + { M32R2F_INSN_RAC_DSI, model_m32r2_rac_dsi, { { (int) UNIT_M32R2_U_MAC, 1, 1 } } }, + { M32R2F_INSN_RACH_DSI, model_m32r2_rach_dsi, { { (int) UNIT_M32R2_U_MAC, 1, 1 } } }, + { M32R2F_INSN_RTE, model_m32r2_rte, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } }, + { M32R2F_INSN_SETH, model_m32r2_seth, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } }, + { M32R2F_INSN_SLL, model_m32r2_sll, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } }, + { M32R2F_INSN_SLL3, model_m32r2_sll3, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } }, + { M32R2F_INSN_SLLI, model_m32r2_slli, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } }, + { M32R2F_INSN_SRA, model_m32r2_sra, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } }, + { M32R2F_INSN_SRA3, model_m32r2_sra3, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } }, + { M32R2F_INSN_SRAI, model_m32r2_srai, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } }, + { M32R2F_INSN_SRL, model_m32r2_srl, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } }, + { M32R2F_INSN_SRL3, model_m32r2_srl3, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } }, + { M32R2F_INSN_SRLI, model_m32r2_srli, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } }, + { M32R2F_INSN_ST, model_m32r2_st, { { (int) UNIT_M32R2_U_STORE, 1, 1 } } }, + { M32R2F_INSN_ST_D, model_m32r2_st_d, { { (int) UNIT_M32R2_U_STORE, 1, 2 } } }, + { M32R2F_INSN_STB, model_m32r2_stb, { { (int) UNIT_M32R2_U_STORE, 1, 1 } } }, + { M32R2F_INSN_STB_D, model_m32r2_stb_d, { { (int) UNIT_M32R2_U_STORE, 1, 2 } } }, + { M32R2F_INSN_STH, model_m32r2_sth, { { (int) UNIT_M32R2_U_STORE, 1, 1 } } }, + { M32R2F_INSN_STH_D, model_m32r2_sth_d, { { (int) UNIT_M32R2_U_STORE, 1, 2 } } }, + { M32R2F_INSN_ST_PLUS, model_m32r2_st_plus, { { (int) UNIT_M32R2_U_STORE, 1, 1 }, { (int) UNIT_M32R2_U_EXEC, 1, 0 } } }, + { M32R2F_INSN_STH_PLUS, model_m32r2_sth_plus, { { (int) UNIT_M32R2_U_STORE, 1, 1 }, { (int) UNIT_M32R2_U_EXEC, 1, 0 } } }, + { M32R2F_INSN_STB_PLUS, model_m32r2_stb_plus, { { (int) UNIT_M32R2_U_STORE, 1, 1 }, { (int) UNIT_M32R2_U_EXEC, 1, 0 } } }, + { M32R2F_INSN_ST_MINUS, model_m32r2_st_minus, { { (int) UNIT_M32R2_U_STORE, 1, 1 }, { (int) UNIT_M32R2_U_EXEC, 1, 0 } } }, + { M32R2F_INSN_SUB, model_m32r2_sub, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } }, + { M32R2F_INSN_SUBV, model_m32r2_subv, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } }, + { M32R2F_INSN_SUBX, model_m32r2_subx, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } }, + { M32R2F_INSN_TRAP, model_m32r2_trap, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } }, + { M32R2F_INSN_UNLOCK, model_m32r2_unlock, { { (int) UNIT_M32R2_U_LOAD, 1, 1 } } }, + { M32R2F_INSN_SATB, model_m32r2_satb, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } }, + { M32R2F_INSN_SATH, model_m32r2_sath, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } }, + { M32R2F_INSN_SAT, model_m32r2_sat, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } }, + { M32R2F_INSN_PCMPBZ, model_m32r2_pcmpbz, { { (int) UNIT_M32R2_U_CMP, 1, 1 } } }, + { M32R2F_INSN_SADD, model_m32r2_sadd, { { (int) UNIT_M32R2_U_MAC, 1, 1 } } }, + { M32R2F_INSN_MACWU1, model_m32r2_macwu1, { { (int) UNIT_M32R2_U_MAC, 1, 1 } } }, + { M32R2F_INSN_MSBLO, model_m32r2_msblo, { { (int) UNIT_M32R2_U_MAC, 1, 1 } } }, + { M32R2F_INSN_MULWU1, model_m32r2_mulwu1, { { (int) UNIT_M32R2_U_MAC, 1, 1 } } }, + { M32R2F_INSN_MACLH1, model_m32r2_maclh1, { { (int) UNIT_M32R2_U_MAC, 1, 1 } } }, + { M32R2F_INSN_SC, model_m32r2_sc, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } }, + { M32R2F_INSN_SNC, model_m32r2_snc, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } }, + { M32R2F_INSN_CLRPSW, model_m32r2_clrpsw, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } }, + { M32R2F_INSN_SETPSW, model_m32r2_setpsw, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } }, + { M32R2F_INSN_BSET, model_m32r2_bset, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } }, + { M32R2F_INSN_BCLR, model_m32r2_bclr, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } }, + { M32R2F_INSN_BTST, model_m32r2_btst, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } }, +}; + +#endif /* WITH_PROFILE_MODEL_P */ + +static void +m32r2_model_init (SIM_CPU *cpu) +{ + CPU_MODEL_DATA (cpu) = (void *) zalloc (sizeof (MODEL_M32R2_DATA)); +} + +#if WITH_PROFILE_MODEL_P +#define TIMING_DATA(td) td +#else +#define TIMING_DATA(td) 0 +#endif + +static const MODEL m32r2_models[] = +{ + { "m32r2", & m32r2_mach, MODEL_M32R2, TIMING_DATA (& m32r2_timing[0]), m32r2_model_init }, + { 0 } +}; + +/* The properties of this cpu's implementation. */ + +static const MACH_IMP_PROPERTIES m32r2f_imp_properties = +{ + sizeof (SIM_CPU), +#if WITH_SCACHE + sizeof (SCACHE) +#else + 0 +#endif +}; + + +static void +m32r2f_prepare_run (SIM_CPU *cpu) +{ + if (CPU_IDESC (cpu) == NULL) + m32r2f_init_idesc_table (cpu); +} + +static const CGEN_INSN * +m32r2f_get_idata (SIM_CPU *cpu, int inum) +{ + return CPU_IDESC (cpu) [inum].idata; +} + +static void +m32r2_init_cpu (SIM_CPU *cpu) +{ + CPU_REG_FETCH (cpu) = m32r2f_fetch_register; + CPU_REG_STORE (cpu) = m32r2f_store_register; + CPU_PC_FETCH (cpu) = m32r2f_h_pc_get; + CPU_PC_STORE (cpu) = m32r2f_h_pc_set; + CPU_GET_IDATA (cpu) = m32r2f_get_idata; + CPU_MAX_INSNS (cpu) = M32R2F_INSN__MAX; + CPU_INSN_NAME (cpu) = cgen_insn_name; + CPU_FULL_ENGINE_FN (cpu) = m32r2f_engine_run_full; +#if WITH_FAST + CPU_FAST_ENGINE_FN (cpu) = m32r2f_engine_run_fast; +#else + CPU_FAST_ENGINE_FN (cpu) = m32r2f_engine_run_full; +#endif +} + +const MACH m32r2_mach = +{ + "m32r2", "m32r2", MACH_M32R2, + 32, 32, & m32r2_models[0], & m32r2f_imp_properties, + m32r2_init_cpu, + m32r2f_prepare_run +}; + diff --git a/sim/m32r/sem2-switch.c b/sim/m32r/sem2-switch.c new file mode 100644 index 0000000..82af4cd --- /dev/null +++ b/sim/m32r/sem2-switch.c @@ -0,0 +1,6822 @@ +/* Simulator instruction semantics for m32r2f. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. + +This file is part of the GNU simulators. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +*/ + +#ifdef DEFINE_LABELS + + /* The labels have the case they have because the enum of insn types + is all uppercase and in the non-stdc case the insn symbol is built + into the enum name. */ + + static struct { + int index; + void *label; + } labels[] = { + { M32R2F_INSN_X_INVALID, && case_sem_INSN_X_INVALID }, + { M32R2F_INSN_X_AFTER, && case_sem_INSN_X_AFTER }, + { M32R2F_INSN_X_BEFORE, && case_sem_INSN_X_BEFORE }, + { M32R2F_INSN_X_CTI_CHAIN, && case_sem_INSN_X_CTI_CHAIN }, + { M32R2F_INSN_X_CHAIN, && case_sem_INSN_X_CHAIN }, + { M32R2F_INSN_X_BEGIN, && case_sem_INSN_X_BEGIN }, + { M32R2F_INSN_ADD, && case_sem_INSN_ADD }, + { M32R2F_INSN_ADD3, && case_sem_INSN_ADD3 }, + { M32R2F_INSN_AND, && case_sem_INSN_AND }, + { M32R2F_INSN_AND3, && case_sem_INSN_AND3 }, + { M32R2F_INSN_OR, && case_sem_INSN_OR }, + { M32R2F_INSN_OR3, && case_sem_INSN_OR3 }, + { M32R2F_INSN_XOR, && case_sem_INSN_XOR }, + { M32R2F_INSN_XOR3, && case_sem_INSN_XOR3 }, + { M32R2F_INSN_ADDI, && case_sem_INSN_ADDI }, + { M32R2F_INSN_ADDV, && case_sem_INSN_ADDV }, + { M32R2F_INSN_ADDV3, && case_sem_INSN_ADDV3 }, + { M32R2F_INSN_ADDX, && case_sem_INSN_ADDX }, + { M32R2F_INSN_BC8, && case_sem_INSN_BC8 }, + { M32R2F_INSN_BC24, && case_sem_INSN_BC24 }, + { M32R2F_INSN_BEQ, && case_sem_INSN_BEQ }, + { M32R2F_INSN_BEQZ, && case_sem_INSN_BEQZ }, + { M32R2F_INSN_BGEZ, && case_sem_INSN_BGEZ }, + { M32R2F_INSN_BGTZ, && case_sem_INSN_BGTZ }, + { M32R2F_INSN_BLEZ, && case_sem_INSN_BLEZ }, + { M32R2F_INSN_BLTZ, && case_sem_INSN_BLTZ }, + { M32R2F_INSN_BNEZ, && case_sem_INSN_BNEZ }, + { M32R2F_INSN_BL8, && case_sem_INSN_BL8 }, + { M32R2F_INSN_BL24, && case_sem_INSN_BL24 }, + { M32R2F_INSN_BCL8, && case_sem_INSN_BCL8 }, + { M32R2F_INSN_BCL24, && case_sem_INSN_BCL24 }, + { M32R2F_INSN_BNC8, && case_sem_INSN_BNC8 }, + { M32R2F_INSN_BNC24, && case_sem_INSN_BNC24 }, + { M32R2F_INSN_BNE, && case_sem_INSN_BNE }, + { M32R2F_INSN_BRA8, && case_sem_INSN_BRA8 }, + { M32R2F_INSN_BRA24, && case_sem_INSN_BRA24 }, + { M32R2F_INSN_BNCL8, && case_sem_INSN_BNCL8 }, + { M32R2F_INSN_BNCL24, && case_sem_INSN_BNCL24 }, + { M32R2F_INSN_CMP, && case_sem_INSN_CMP }, + { M32R2F_INSN_CMPI, && case_sem_INSN_CMPI }, + { M32R2F_INSN_CMPU, && case_sem_INSN_CMPU }, + { M32R2F_INSN_CMPUI, && case_sem_INSN_CMPUI }, + { M32R2F_INSN_CMPEQ, && case_sem_INSN_CMPEQ }, + { M32R2F_INSN_CMPZ, && case_sem_INSN_CMPZ }, + { M32R2F_INSN_DIV, && case_sem_INSN_DIV }, + { M32R2F_INSN_DIVU, && case_sem_INSN_DIVU }, + { M32R2F_INSN_REM, && case_sem_INSN_REM }, + { M32R2F_INSN_REMU, && case_sem_INSN_REMU }, + { M32R2F_INSN_REMH, && case_sem_INSN_REMH }, + { M32R2F_INSN_REMUH, && case_sem_INSN_REMUH }, + { M32R2F_INSN_REMB, && case_sem_INSN_REMB }, + { M32R2F_INSN_REMUB, && case_sem_INSN_REMUB }, + { M32R2F_INSN_DIVUH, && case_sem_INSN_DIVUH }, + { M32R2F_INSN_DIVB, && case_sem_INSN_DIVB }, + { M32R2F_INSN_DIVUB, && case_sem_INSN_DIVUB }, + { M32R2F_INSN_DIVH, && case_sem_INSN_DIVH }, + { M32R2F_INSN_JC, && case_sem_INSN_JC }, + { M32R2F_INSN_JNC, && case_sem_INSN_JNC }, + { M32R2F_INSN_JL, && case_sem_INSN_JL }, + { M32R2F_INSN_JMP, && case_sem_INSN_JMP }, + { M32R2F_INSN_LD, && case_sem_INSN_LD }, + { M32R2F_INSN_LD_D, && case_sem_INSN_LD_D }, + { M32R2F_INSN_LDB, && case_sem_INSN_LDB }, + { M32R2F_INSN_LDB_D, && case_sem_INSN_LDB_D }, + { M32R2F_INSN_LDH, && case_sem_INSN_LDH }, + { M32R2F_INSN_LDH_D, && case_sem_INSN_LDH_D }, + { M32R2F_INSN_LDUB, && case_sem_INSN_LDUB }, + { M32R2F_INSN_LDUB_D, && case_sem_INSN_LDUB_D }, + { M32R2F_INSN_LDUH, && case_sem_INSN_LDUH }, + { M32R2F_INSN_LDUH_D, && case_sem_INSN_LDUH_D }, + { M32R2F_INSN_LD_PLUS, && case_sem_INSN_LD_PLUS }, + { M32R2F_INSN_LD24, && case_sem_INSN_LD24 }, + { M32R2F_INSN_LDI8, && case_sem_INSN_LDI8 }, + { M32R2F_INSN_LDI16, && case_sem_INSN_LDI16 }, + { M32R2F_INSN_LOCK, && case_sem_INSN_LOCK }, + { M32R2F_INSN_MACHI_A, && case_sem_INSN_MACHI_A }, + { M32R2F_INSN_MACLO_A, && case_sem_INSN_MACLO_A }, + { M32R2F_INSN_MACWHI_A, && case_sem_INSN_MACWHI_A }, + { M32R2F_INSN_MACWLO_A, && case_sem_INSN_MACWLO_A }, + { M32R2F_INSN_MUL, && case_sem_INSN_MUL }, + { M32R2F_INSN_MULHI_A, && case_sem_INSN_MULHI_A }, + { M32R2F_INSN_MULLO_A, && case_sem_INSN_MULLO_A }, + { M32R2F_INSN_MULWHI_A, && case_sem_INSN_MULWHI_A }, + { M32R2F_INSN_MULWLO_A, && case_sem_INSN_MULWLO_A }, + { M32R2F_INSN_MV, && case_sem_INSN_MV }, + { M32R2F_INSN_MVFACHI_A, && case_sem_INSN_MVFACHI_A }, + { M32R2F_INSN_MVFACLO_A, && case_sem_INSN_MVFACLO_A }, + { M32R2F_INSN_MVFACMI_A, && case_sem_INSN_MVFACMI_A }, + { M32R2F_INSN_MVFC, && case_sem_INSN_MVFC }, + { M32R2F_INSN_MVTACHI_A, && case_sem_INSN_MVTACHI_A }, + { M32R2F_INSN_MVTACLO_A, && case_sem_INSN_MVTACLO_A }, + { M32R2F_INSN_MVTC, && case_sem_INSN_MVTC }, + { M32R2F_INSN_NEG, && case_sem_INSN_NEG }, + { M32R2F_INSN_NOP, && case_sem_INSN_NOP }, + { M32R2F_INSN_NOT, && case_sem_INSN_NOT }, + { M32R2F_INSN_RAC_DSI, && case_sem_INSN_RAC_DSI }, + { M32R2F_INSN_RACH_DSI, && case_sem_INSN_RACH_DSI }, + { M32R2F_INSN_RTE, && case_sem_INSN_RTE }, + { M32R2F_INSN_SETH, && case_sem_INSN_SETH }, + { M32R2F_INSN_SLL, && case_sem_INSN_SLL }, + { M32R2F_INSN_SLL3, && case_sem_INSN_SLL3 }, + { M32R2F_INSN_SLLI, && case_sem_INSN_SLLI }, + { M32R2F_INSN_SRA, && case_sem_INSN_SRA }, + { M32R2F_INSN_SRA3, && case_sem_INSN_SRA3 }, + { M32R2F_INSN_SRAI, && case_sem_INSN_SRAI }, + { M32R2F_INSN_SRL, && case_sem_INSN_SRL }, + { M32R2F_INSN_SRL3, && case_sem_INSN_SRL3 }, + { M32R2F_INSN_SRLI, && case_sem_INSN_SRLI }, + { M32R2F_INSN_ST, && case_sem_INSN_ST }, + { M32R2F_INSN_ST_D, && case_sem_INSN_ST_D }, + { M32R2F_INSN_STB, && case_sem_INSN_STB }, + { M32R2F_INSN_STB_D, && case_sem_INSN_STB_D }, + { M32R2F_INSN_STH, && case_sem_INSN_STH }, + { M32R2F_INSN_STH_D, && case_sem_INSN_STH_D }, + { M32R2F_INSN_ST_PLUS, && case_sem_INSN_ST_PLUS }, + { M32R2F_INSN_STH_PLUS, && case_sem_INSN_STH_PLUS }, + { M32R2F_INSN_STB_PLUS, && case_sem_INSN_STB_PLUS }, + { M32R2F_INSN_ST_MINUS, && case_sem_INSN_ST_MINUS }, + { M32R2F_INSN_SUB, && case_sem_INSN_SUB }, + { M32R2F_INSN_SUBV, && case_sem_INSN_SUBV }, + { M32R2F_INSN_SUBX, && case_sem_INSN_SUBX }, + { M32R2F_INSN_TRAP, && case_sem_INSN_TRAP }, + { M32R2F_INSN_UNLOCK, && case_sem_INSN_UNLOCK }, + { M32R2F_INSN_SATB, && case_sem_INSN_SATB }, + { M32R2F_INSN_SATH, && case_sem_INSN_SATH }, + { M32R2F_INSN_SAT, && case_sem_INSN_SAT }, + { M32R2F_INSN_PCMPBZ, && case_sem_INSN_PCMPBZ }, + { M32R2F_INSN_SADD, && case_sem_INSN_SADD }, + { M32R2F_INSN_MACWU1, && case_sem_INSN_MACWU1 }, + { M32R2F_INSN_MSBLO, && case_sem_INSN_MSBLO }, + { M32R2F_INSN_MULWU1, && case_sem_INSN_MULWU1 }, + { M32R2F_INSN_MACLH1, && case_sem_INSN_MACLH1 }, + { M32R2F_INSN_SC, && case_sem_INSN_SC }, + { M32R2F_INSN_SNC, && case_sem_INSN_SNC }, + { M32R2F_INSN_CLRPSW, && case_sem_INSN_CLRPSW }, + { M32R2F_INSN_SETPSW, && case_sem_INSN_SETPSW }, + { M32R2F_INSN_BSET, && case_sem_INSN_BSET }, + { M32R2F_INSN_BCLR, && case_sem_INSN_BCLR }, + { M32R2F_INSN_BTST, && case_sem_INSN_BTST }, + { M32R2F_INSN_PAR_ADD, && case_sem_INSN_PAR_ADD }, + { M32R2F_INSN_WRITE_ADD, && case_sem_INSN_WRITE_ADD }, + { M32R2F_INSN_PAR_AND, && case_sem_INSN_PAR_AND }, + { M32R2F_INSN_WRITE_AND, && case_sem_INSN_WRITE_AND }, + { M32R2F_INSN_PAR_OR, && case_sem_INSN_PAR_OR }, + { M32R2F_INSN_WRITE_OR, && case_sem_INSN_WRITE_OR }, + { M32R2F_INSN_PAR_XOR, && case_sem_INSN_PAR_XOR }, + { M32R2F_INSN_WRITE_XOR, && case_sem_INSN_WRITE_XOR }, + { M32R2F_INSN_PAR_ADDI, && case_sem_INSN_PAR_ADDI }, + { M32R2F_INSN_WRITE_ADDI, && case_sem_INSN_WRITE_ADDI }, + { M32R2F_INSN_PAR_ADDV, && case_sem_INSN_PAR_ADDV }, + { M32R2F_INSN_WRITE_ADDV, && case_sem_INSN_WRITE_ADDV }, + { M32R2F_INSN_PAR_ADDX, && case_sem_INSN_PAR_ADDX }, + { M32R2F_INSN_WRITE_ADDX, && case_sem_INSN_WRITE_ADDX }, + { M32R2F_INSN_PAR_BC8, && case_sem_INSN_PAR_BC8 }, + { M32R2F_INSN_WRITE_BC8, && case_sem_INSN_WRITE_BC8 }, + { M32R2F_INSN_PAR_BL8, && case_sem_INSN_PAR_BL8 }, + { M32R2F_INSN_WRITE_BL8, && case_sem_INSN_WRITE_BL8 }, + { M32R2F_INSN_PAR_BCL8, && case_sem_INSN_PAR_BCL8 }, + { M32R2F_INSN_WRITE_BCL8, && case_sem_INSN_WRITE_BCL8 }, + { M32R2F_INSN_PAR_BNC8, && case_sem_INSN_PAR_BNC8 }, + { M32R2F_INSN_WRITE_BNC8, && case_sem_INSN_WRITE_BNC8 }, + { M32R2F_INSN_PAR_BRA8, && case_sem_INSN_PAR_BRA8 }, + { M32R2F_INSN_WRITE_BRA8, && case_sem_INSN_WRITE_BRA8 }, + { M32R2F_INSN_PAR_BNCL8, && case_sem_INSN_PAR_BNCL8 }, + { M32R2F_INSN_WRITE_BNCL8, && case_sem_INSN_WRITE_BNCL8 }, + { M32R2F_INSN_PAR_CMP, && case_sem_INSN_PAR_CMP }, + { M32R2F_INSN_WRITE_CMP, && case_sem_INSN_WRITE_CMP }, + { M32R2F_INSN_PAR_CMPU, && case_sem_INSN_PAR_CMPU }, + { M32R2F_INSN_WRITE_CMPU, && case_sem_INSN_WRITE_CMPU }, + { M32R2F_INSN_PAR_CMPEQ, && case_sem_INSN_PAR_CMPEQ }, + { M32R2F_INSN_WRITE_CMPEQ, && case_sem_INSN_WRITE_CMPEQ }, + { M32R2F_INSN_PAR_CMPZ, && case_sem_INSN_PAR_CMPZ }, + { M32R2F_INSN_WRITE_CMPZ, && case_sem_INSN_WRITE_CMPZ }, + { M32R2F_INSN_PAR_JC, && case_sem_INSN_PAR_JC }, + { M32R2F_INSN_WRITE_JC, && case_sem_INSN_WRITE_JC }, + { M32R2F_INSN_PAR_JNC, && case_sem_INSN_PAR_JNC }, + { M32R2F_INSN_WRITE_JNC, && case_sem_INSN_WRITE_JNC }, + { M32R2F_INSN_PAR_JL, && case_sem_INSN_PAR_JL }, + { M32R2F_INSN_WRITE_JL, && case_sem_INSN_WRITE_JL }, + { M32R2F_INSN_PAR_JMP, && case_sem_INSN_PAR_JMP }, + { M32R2F_INSN_WRITE_JMP, && case_sem_INSN_WRITE_JMP }, + { M32R2F_INSN_PAR_LD, && case_sem_INSN_PAR_LD }, + { M32R2F_INSN_WRITE_LD, && case_sem_INSN_WRITE_LD }, + { M32R2F_INSN_PAR_LDB, && case_sem_INSN_PAR_LDB }, + { M32R2F_INSN_WRITE_LDB, && case_sem_INSN_WRITE_LDB }, + { M32R2F_INSN_PAR_LDH, && case_sem_INSN_PAR_LDH }, + { M32R2F_INSN_WRITE_LDH, && case_sem_INSN_WRITE_LDH }, + { M32R2F_INSN_PAR_LDUB, && case_sem_INSN_PAR_LDUB }, + { M32R2F_INSN_WRITE_LDUB, && case_sem_INSN_WRITE_LDUB }, + { M32R2F_INSN_PAR_LDUH, && case_sem_INSN_PAR_LDUH }, + { M32R2F_INSN_WRITE_LDUH, && case_sem_INSN_WRITE_LDUH }, + { M32R2F_INSN_PAR_LD_PLUS, && case_sem_INSN_PAR_LD_PLUS }, + { M32R2F_INSN_WRITE_LD_PLUS, && case_sem_INSN_WRITE_LD_PLUS }, + { M32R2F_INSN_PAR_LDI8, && case_sem_INSN_PAR_LDI8 }, + { M32R2F_INSN_WRITE_LDI8, && case_sem_INSN_WRITE_LDI8 }, + { M32R2F_INSN_PAR_LOCK, && case_sem_INSN_PAR_LOCK }, + { M32R2F_INSN_WRITE_LOCK, && case_sem_INSN_WRITE_LOCK }, + { M32R2F_INSN_PAR_MACHI_A, && case_sem_INSN_PAR_MACHI_A }, + { M32R2F_INSN_WRITE_MACHI_A, && case_sem_INSN_WRITE_MACHI_A }, + { M32R2F_INSN_PAR_MACLO_A, && case_sem_INSN_PAR_MACLO_A }, + { M32R2F_INSN_WRITE_MACLO_A, && case_sem_INSN_WRITE_MACLO_A }, + { M32R2F_INSN_PAR_MACWHI_A, && case_sem_INSN_PAR_MACWHI_A }, + { M32R2F_INSN_WRITE_MACWHI_A, && case_sem_INSN_WRITE_MACWHI_A }, + { M32R2F_INSN_PAR_MACWLO_A, && case_sem_INSN_PAR_MACWLO_A }, + { M32R2F_INSN_WRITE_MACWLO_A, && case_sem_INSN_WRITE_MACWLO_A }, + { M32R2F_INSN_PAR_MUL, && case_sem_INSN_PAR_MUL }, + { M32R2F_INSN_WRITE_MUL, && case_sem_INSN_WRITE_MUL }, + { M32R2F_INSN_PAR_MULHI_A, && case_sem_INSN_PAR_MULHI_A }, + { M32R2F_INSN_WRITE_MULHI_A, && case_sem_INSN_WRITE_MULHI_A }, + { M32R2F_INSN_PAR_MULLO_A, && case_sem_INSN_PAR_MULLO_A }, + { M32R2F_INSN_WRITE_MULLO_A, && case_sem_INSN_WRITE_MULLO_A }, + { M32R2F_INSN_PAR_MULWHI_A, && case_sem_INSN_PAR_MULWHI_A }, + { M32R2F_INSN_WRITE_MULWHI_A, && case_sem_INSN_WRITE_MULWHI_A }, + { M32R2F_INSN_PAR_MULWLO_A, && case_sem_INSN_PAR_MULWLO_A }, + { M32R2F_INSN_WRITE_MULWLO_A, && case_sem_INSN_WRITE_MULWLO_A }, + { M32R2F_INSN_PAR_MV, && case_sem_INSN_PAR_MV }, + { M32R2F_INSN_WRITE_MV, && case_sem_INSN_WRITE_MV }, + { M32R2F_INSN_PAR_MVFACHI_A, && case_sem_INSN_PAR_MVFACHI_A }, + { M32R2F_INSN_WRITE_MVFACHI_A, && case_sem_INSN_WRITE_MVFACHI_A }, + { M32R2F_INSN_PAR_MVFACLO_A, && case_sem_INSN_PAR_MVFACLO_A }, + { M32R2F_INSN_WRITE_MVFACLO_A, && case_sem_INSN_WRITE_MVFACLO_A }, + { M32R2F_INSN_PAR_MVFACMI_A, && case_sem_INSN_PAR_MVFACMI_A }, + { M32R2F_INSN_WRITE_MVFACMI_A, && case_sem_INSN_WRITE_MVFACMI_A }, + { M32R2F_INSN_PAR_MVFC, && case_sem_INSN_PAR_MVFC }, + { M32R2F_INSN_WRITE_MVFC, && case_sem_INSN_WRITE_MVFC }, + { M32R2F_INSN_PAR_MVTACHI_A, && case_sem_INSN_PAR_MVTACHI_A }, + { M32R2F_INSN_WRITE_MVTACHI_A, && case_sem_INSN_WRITE_MVTACHI_A }, + { M32R2F_INSN_PAR_MVTACLO_A, && case_sem_INSN_PAR_MVTACLO_A }, + { M32R2F_INSN_WRITE_MVTACLO_A, && case_sem_INSN_WRITE_MVTACLO_A }, + { M32R2F_INSN_PAR_MVTC, && case_sem_INSN_PAR_MVTC }, + { M32R2F_INSN_WRITE_MVTC, && case_sem_INSN_WRITE_MVTC }, + { M32R2F_INSN_PAR_NEG, && case_sem_INSN_PAR_NEG }, + { M32R2F_INSN_WRITE_NEG, && case_sem_INSN_WRITE_NEG }, + { M32R2F_INSN_PAR_NOP, && case_sem_INSN_PAR_NOP }, + { M32R2F_INSN_WRITE_NOP, && case_sem_INSN_WRITE_NOP }, + { M32R2F_INSN_PAR_NOT, && case_sem_INSN_PAR_NOT }, + { M32R2F_INSN_WRITE_NOT, && case_sem_INSN_WRITE_NOT }, + { M32R2F_INSN_PAR_RAC_DSI, && case_sem_INSN_PAR_RAC_DSI }, + { M32R2F_INSN_WRITE_RAC_DSI, && case_sem_INSN_WRITE_RAC_DSI }, + { M32R2F_INSN_PAR_RACH_DSI, && case_sem_INSN_PAR_RACH_DSI }, + { M32R2F_INSN_WRITE_RACH_DSI, && case_sem_INSN_WRITE_RACH_DSI }, + { M32R2F_INSN_PAR_RTE, && case_sem_INSN_PAR_RTE }, + { M32R2F_INSN_WRITE_RTE, && case_sem_INSN_WRITE_RTE }, + { M32R2F_INSN_PAR_SLL, && case_sem_INSN_PAR_SLL }, + { M32R2F_INSN_WRITE_SLL, && case_sem_INSN_WRITE_SLL }, + { M32R2F_INSN_PAR_SLLI, && case_sem_INSN_PAR_SLLI }, + { M32R2F_INSN_WRITE_SLLI, && case_sem_INSN_WRITE_SLLI }, + { M32R2F_INSN_PAR_SRA, && case_sem_INSN_PAR_SRA }, + { M32R2F_INSN_WRITE_SRA, && case_sem_INSN_WRITE_SRA }, + { M32R2F_INSN_PAR_SRAI, && case_sem_INSN_PAR_SRAI }, + { M32R2F_INSN_WRITE_SRAI, && case_sem_INSN_WRITE_SRAI }, + { M32R2F_INSN_PAR_SRL, && case_sem_INSN_PAR_SRL }, + { M32R2F_INSN_WRITE_SRL, && case_sem_INSN_WRITE_SRL }, + { M32R2F_INSN_PAR_SRLI, && case_sem_INSN_PAR_SRLI }, + { M32R2F_INSN_WRITE_SRLI, && case_sem_INSN_WRITE_SRLI }, + { M32R2F_INSN_PAR_ST, && case_sem_INSN_PAR_ST }, + { M32R2F_INSN_WRITE_ST, && case_sem_INSN_WRITE_ST }, + { M32R2F_INSN_PAR_STB, && case_sem_INSN_PAR_STB }, + { M32R2F_INSN_WRITE_STB, && case_sem_INSN_WRITE_STB }, + { M32R2F_INSN_PAR_STH, && case_sem_INSN_PAR_STH }, + { M32R2F_INSN_WRITE_STH, && case_sem_INSN_WRITE_STH }, + { M32R2F_INSN_PAR_ST_PLUS, && case_sem_INSN_PAR_ST_PLUS }, + { M32R2F_INSN_WRITE_ST_PLUS, && case_sem_INSN_WRITE_ST_PLUS }, + { M32R2F_INSN_PAR_STH_PLUS, && case_sem_INSN_PAR_STH_PLUS }, + { M32R2F_INSN_WRITE_STH_PLUS, && case_sem_INSN_WRITE_STH_PLUS }, + { M32R2F_INSN_PAR_STB_PLUS, && case_sem_INSN_PAR_STB_PLUS }, + { M32R2F_INSN_WRITE_STB_PLUS, && case_sem_INSN_WRITE_STB_PLUS }, + { M32R2F_INSN_PAR_ST_MINUS, && case_sem_INSN_PAR_ST_MINUS }, + { M32R2F_INSN_WRITE_ST_MINUS, && case_sem_INSN_WRITE_ST_MINUS }, + { M32R2F_INSN_PAR_SUB, && case_sem_INSN_PAR_SUB }, + { M32R2F_INSN_WRITE_SUB, && case_sem_INSN_WRITE_SUB }, + { M32R2F_INSN_PAR_SUBV, && case_sem_INSN_PAR_SUBV }, + { M32R2F_INSN_WRITE_SUBV, && case_sem_INSN_WRITE_SUBV }, + { M32R2F_INSN_PAR_SUBX, && case_sem_INSN_PAR_SUBX }, + { M32R2F_INSN_WRITE_SUBX, && case_sem_INSN_WRITE_SUBX }, + { M32R2F_INSN_PAR_TRAP, && case_sem_INSN_PAR_TRAP }, + { M32R2F_INSN_WRITE_TRAP, && case_sem_INSN_WRITE_TRAP }, + { M32R2F_INSN_PAR_UNLOCK, && case_sem_INSN_PAR_UNLOCK }, + { M32R2F_INSN_WRITE_UNLOCK, && case_sem_INSN_WRITE_UNLOCK }, + { M32R2F_INSN_PAR_PCMPBZ, && case_sem_INSN_PAR_PCMPBZ }, + { M32R2F_INSN_WRITE_PCMPBZ, && case_sem_INSN_WRITE_PCMPBZ }, + { M32R2F_INSN_PAR_SADD, && case_sem_INSN_PAR_SADD }, + { M32R2F_INSN_WRITE_SADD, && case_sem_INSN_WRITE_SADD }, + { M32R2F_INSN_PAR_MACWU1, && case_sem_INSN_PAR_MACWU1 }, + { M32R2F_INSN_WRITE_MACWU1, && case_sem_INSN_WRITE_MACWU1 }, + { M32R2F_INSN_PAR_MSBLO, && case_sem_INSN_PAR_MSBLO }, + { M32R2F_INSN_WRITE_MSBLO, && case_sem_INSN_WRITE_MSBLO }, + { M32R2F_INSN_PAR_MULWU1, && case_sem_INSN_PAR_MULWU1 }, + { M32R2F_INSN_WRITE_MULWU1, && case_sem_INSN_WRITE_MULWU1 }, + { M32R2F_INSN_PAR_MACLH1, && case_sem_INSN_PAR_MACLH1 }, + { M32R2F_INSN_WRITE_MACLH1, && case_sem_INSN_WRITE_MACLH1 }, + { M32R2F_INSN_PAR_SC, && case_sem_INSN_PAR_SC }, + { M32R2F_INSN_WRITE_SC, && case_sem_INSN_WRITE_SC }, + { M32R2F_INSN_PAR_SNC, && case_sem_INSN_PAR_SNC }, + { M32R2F_INSN_WRITE_SNC, && case_sem_INSN_WRITE_SNC }, + { M32R2F_INSN_PAR_CLRPSW, && case_sem_INSN_PAR_CLRPSW }, + { M32R2F_INSN_WRITE_CLRPSW, && case_sem_INSN_WRITE_CLRPSW }, + { M32R2F_INSN_PAR_SETPSW, && case_sem_INSN_PAR_SETPSW }, + { M32R2F_INSN_WRITE_SETPSW, && case_sem_INSN_WRITE_SETPSW }, + { M32R2F_INSN_PAR_BTST, && case_sem_INSN_PAR_BTST }, + { M32R2F_INSN_WRITE_BTST, && case_sem_INSN_WRITE_BTST }, + { 0, 0 } + }; + int i; + + for (i = 0; labels[i].label != 0; ++i) + { +#if FAST_P + CPU_IDESC (current_cpu) [labels[i].index].sem_fast_lab = labels[i].label; +#else + CPU_IDESC (current_cpu) [labels[i].index].sem_full_lab = labels[i].label; +#endif + } + +#undef DEFINE_LABELS +#endif /* DEFINE_LABELS */ + +#ifdef DEFINE_SWITCH + +/* If hyper-fast [well not unnecessarily slow] execution is selected, turn + off frills like tracing and profiling. */ +/* FIXME: A better way would be to have TRACE_RESULT check for something + that can cause it to be optimized out. Another way would be to emit + special handlers into the instruction "stream". */ + +#if FAST_P +#undef TRACE_RESULT +#define TRACE_RESULT(cpu, abuf, name, type, val) +#endif + +#undef GET_ATTR +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_##attr) +#else +#define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_/**/attr) +#endif + +{ + +#if WITH_SCACHE_PBB + +/* Branch to next handler without going around main loop. */ +#define NEXT(vpc) goto * SEM_ARGBUF (vpc) -> semantic.sem_case +SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) + +#else /* ! WITH_SCACHE_PBB */ + +#define NEXT(vpc) BREAK (sem) +#ifdef __GNUC__ +#if FAST_P + SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_fast_lab) +#else + SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_full_lab) +#endif +#else + SWITCH (sem, SEM_ARGBUF (sc) -> idesc->num) +#endif + +#endif /* ! WITH_SCACHE_PBB */ + + { + + CASE (sem, INSN_X_INVALID) : /* --invalid-- */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + { + /* Update the recorded pc in the cpu state struct. + Only necessary for WITH_SCACHE case, but to avoid the + conditional compilation .... */ + SET_H_PC (pc); + /* Virtual insns have zero size. Overwrite vpc with address of next insn + using the default-insn-bitsize spec. When executing insns in parallel + we may want to queue the fault and continue execution. */ + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + vpc = sim_engine_invalid_insn (current_cpu, pc, vpc); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_X_AFTER) : /* --after-- */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + { +#if WITH_SCACHE_PBB_M32R2F + m32r2f_pbb_after (current_cpu, sem_arg); +#endif + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_X_BEFORE) : /* --before-- */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + { +#if WITH_SCACHE_PBB_M32R2F + m32r2f_pbb_before (current_cpu, sem_arg); +#endif + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_X_CTI_CHAIN) : /* --cti-chain-- */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + { +#if WITH_SCACHE_PBB_M32R2F +#ifdef DEFINE_SWITCH + vpc = m32r2f_pbb_cti_chain (current_cpu, sem_arg, + pbb_br_type, pbb_br_npc); + BREAK (sem); +#else + /* FIXME: Allow provision of explicit ifmt spec in insn spec. */ + vpc = m32r2f_pbb_cti_chain (current_cpu, sem_arg, + CPU_PBB_BR_TYPE (current_cpu), + CPU_PBB_BR_NPC (current_cpu)); +#endif +#endif + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_X_CHAIN) : /* --chain-- */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + { +#if WITH_SCACHE_PBB_M32R2F + vpc = m32r2f_pbb_chain (current_cpu, sem_arg); +#ifdef DEFINE_SWITCH + BREAK (sem); +#endif +#endif + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_X_BEGIN) : /* --begin-- */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + { +#if WITH_SCACHE_PBB_M32R2F +#if defined DEFINE_SWITCH || defined FAST_P + /* In the switch case FAST_P is a constant, allowing several optimizations + in any called inline functions. */ + vpc = m32r2f_pbb_begin (current_cpu, FAST_P); +#else +#if 0 /* cgen engine can't handle dynamic fast/full switching yet. */ + vpc = m32r2f_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (current_cpu))); +#else + vpc = m32r2f_pbb_begin (current_cpu, 0); +#endif +#endif +#endif + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_ADD) : /* add $dr,$sr */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_add.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + SI opval = ADDSI (* FLD (i_dr), * FLD (i_sr)); + * FLD (i_dr) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_ADD3) : /* add3 $dr,$sr,$hash$slo16 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_add3.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = ADDSI (* FLD (i_sr), FLD (f_simm16)); + * FLD (i_dr) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_AND) : /* and $dr,$sr */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_add.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + SI opval = ANDSI (* FLD (i_dr), * FLD (i_sr)); + * FLD (i_dr) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_AND3) : /* and3 $dr,$sr,$uimm16 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_and3.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = ANDSI (* FLD (i_sr), FLD (f_uimm16)); + * FLD (i_dr) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_OR) : /* or $dr,$sr */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_add.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + SI opval = ORSI (* FLD (i_dr), * FLD (i_sr)); + * FLD (i_dr) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_OR3) : /* or3 $dr,$sr,$hash$ulo16 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_and3.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = ORSI (* FLD (i_sr), FLD (f_uimm16)); + * FLD (i_dr) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_XOR) : /* xor $dr,$sr */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_add.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + SI opval = XORSI (* FLD (i_dr), * FLD (i_sr)); + * FLD (i_dr) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_XOR3) : /* xor3 $dr,$sr,$uimm16 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_and3.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = XORSI (* FLD (i_sr), FLD (f_uimm16)); + * FLD (i_dr) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_ADDI) : /* addi $dr,$simm8 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_addi.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + SI opval = ADDSI (* FLD (i_dr), FLD (f_simm8)); + * FLD (i_dr) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_ADDV) : /* addv $dr,$sr */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_add.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + +{ + SI temp0;BI temp1; + temp0 = ADDSI (* FLD (i_dr), * FLD (i_sr)); + temp1 = ADDOFSI (* FLD (i_dr), * FLD (i_sr), 0); + { + SI opval = temp0; + * FLD (i_dr) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + { + BI opval = temp1; + CPU (h_cond) = opval; + TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval); + } +} + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_ADDV3) : /* addv3 $dr,$sr,$simm16 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_add3.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + SI temp0;BI temp1; + temp0 = ADDSI (* FLD (i_sr), FLD (f_simm16)); + temp1 = ADDOFSI (* FLD (i_sr), FLD (f_simm16), 0); + { + SI opval = temp0; + * FLD (i_dr) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + { + BI opval = temp1; + CPU (h_cond) = opval; + TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval); + } +} + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_ADDX) : /* addx $dr,$sr */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_add.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + +{ + SI temp0;BI temp1; + temp0 = ADDCSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond)); + temp1 = ADDCFSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond)); + { + SI opval = temp0; + * FLD (i_dr) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + { + BI opval = temp1; + CPU (h_cond) = opval; + TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval); + } +} + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_BC8) : /* bc.s $disp8 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_bl8.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + +if (CPU (h_cond)) { + { + USI opval = FLD (i_disp8); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_BC24) : /* bc.l $disp24 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_bl24.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (CPU (h_cond)) { + { + USI opval = FLD (i_disp24); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_BEQ) : /* beq $src1,$src2,$disp16 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_beq.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQSI (* FLD (i_src1), * FLD (i_src2))) { + { + USI opval = FLD (i_disp16); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_BEQZ) : /* beqz $src2,$disp16 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_beq.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQSI (* FLD (i_src2), 0)) { + { + USI opval = FLD (i_disp16); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_BGEZ) : /* bgez $src2,$disp16 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_beq.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (GESI (* FLD (i_src2), 0)) { + { + USI opval = FLD (i_disp16); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_BGTZ) : /* bgtz $src2,$disp16 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_beq.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (GTSI (* FLD (i_src2), 0)) { + { + USI opval = FLD (i_disp16); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_BLEZ) : /* blez $src2,$disp16 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_beq.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (LESI (* FLD (i_src2), 0)) { + { + USI opval = FLD (i_disp16); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_BLTZ) : /* bltz $src2,$disp16 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_beq.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (LTSI (* FLD (i_src2), 0)) { + { + USI opval = FLD (i_disp16); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_BNEZ) : /* bnez $src2,$disp16 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_beq.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (NESI (* FLD (i_src2), 0)) { + { + USI opval = FLD (i_disp16); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_BL8) : /* bl.s $disp8 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_bl8.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + +{ + { + SI opval = ADDSI (ANDSI (pc, -4), 4); + CPU (h_gr[((UINT) 14)]) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + { + USI opval = FLD (i_disp8); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} + + SEM_BRANCH_FINI (vpc); +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_BL24) : /* bl.l $disp24 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_bl24.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + { + SI opval = ADDSI (pc, 4); + CPU (h_gr[((UINT) 14)]) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + { + USI opval = FLD (i_disp24); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} + + SEM_BRANCH_FINI (vpc); +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_BCL8) : /* bcl.s $disp8 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_bl8.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + +if (CPU (h_cond)) { +{ + { + SI opval = ADDSI (ANDSI (pc, -4), 4); + CPU (h_gr[((UINT) 14)]) = opval; + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + { + USI opval = FLD (i_disp8); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_BCL24) : /* bcl.l $disp24 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_bl24.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (CPU (h_cond)) { +{ + { + SI opval = ADDSI (pc, 4); + CPU (h_gr[((UINT) 14)]) = opval; + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + { + USI opval = FLD (i_disp24); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_BNC8) : /* bnc.s $disp8 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_bl8.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + +if (NOTBI (CPU (h_cond))) { + { + USI opval = FLD (i_disp8); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_BNC24) : /* bnc.l $disp24 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_bl24.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (NOTBI (CPU (h_cond))) { + { + USI opval = FLD (i_disp24); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_BNE) : /* bne $src1,$src2,$disp16 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_beq.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (NESI (* FLD (i_src1), * FLD (i_src2))) { + { + USI opval = FLD (i_disp16); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_BRA8) : /* bra.s $disp8 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_bl8.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + USI opval = FLD (i_disp8); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } + + SEM_BRANCH_FINI (vpc); +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_BRA24) : /* bra.l $disp24 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_bl24.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + USI opval = FLD (i_disp24); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } + + SEM_BRANCH_FINI (vpc); +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_BNCL8) : /* bncl.s $disp8 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_bl8.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + +if (NOTBI (CPU (h_cond))) { +{ + { + SI opval = ADDSI (ANDSI (pc, -4), 4); + CPU (h_gr[((UINT) 14)]) = opval; + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + { + USI opval = FLD (i_disp8); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_BNCL24) : /* bncl.l $disp24 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_bl24.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (NOTBI (CPU (h_cond))) { +{ + { + SI opval = ADDSI (pc, 4); + CPU (h_gr[((UINT) 14)]) = opval; + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + { + USI opval = FLD (i_disp24); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_CMP) : /* cmp $src1,$src2 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_st_plus.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + BI opval = LTSI (* FLD (i_src1), * FLD (i_src2)); + CPU (h_cond) = opval; + TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_CMPI) : /* cmpi $src2,$simm16 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_st_d.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + BI opval = LTSI (* FLD (i_src2), FLD (f_simm16)); + CPU (h_cond) = opval; + TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_CMPU) : /* cmpu $src1,$src2 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_st_plus.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + BI opval = LTUSI (* FLD (i_src1), * FLD (i_src2)); + CPU (h_cond) = opval; + TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_CMPUI) : /* cmpui $src2,$simm16 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_st_d.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + BI opval = LTUSI (* FLD (i_src2), FLD (f_simm16)); + CPU (h_cond) = opval; + TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_CMPEQ) : /* cmpeq $src1,$src2 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_st_plus.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + BI opval = EQSI (* FLD (i_src1), * FLD (i_src2)); + CPU (h_cond) = opval; + TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_CMPZ) : /* cmpz $src2 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_st_plus.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + BI opval = EQSI (* FLD (i_src2), 0); + CPU (h_cond) = opval; + TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_DIV) : /* div $dr,$sr */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_add.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (NESI (* FLD (i_sr), 0)) { + { + SI opval = DIVSI (* FLD (i_dr), * FLD (i_sr)); + * FLD (i_dr) = opval; + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} + + abuf->written = written; +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_DIVU) : /* divu $dr,$sr */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_add.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (NESI (* FLD (i_sr), 0)) { + { + SI opval = UDIVSI (* FLD (i_dr), * FLD (i_sr)); + * FLD (i_dr) = opval; + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} + + abuf->written = written; +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_REM) : /* rem $dr,$sr */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_add.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (NESI (* FLD (i_sr), 0)) { + { + SI opval = MODSI (* FLD (i_dr), * FLD (i_sr)); + * FLD (i_dr) = opval; + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} + + abuf->written = written; +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_REMU) : /* remu $dr,$sr */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_add.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (NESI (* FLD (i_sr), 0)) { + { + SI opval = UMODSI (* FLD (i_dr), * FLD (i_sr)); + * FLD (i_dr) = opval; + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} + + abuf->written = written; +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_REMH) : /* remh $dr,$sr */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_add.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (NESI (* FLD (i_sr), 0)) { + { + SI opval = MODSI (EXTHISI (TRUNCSIHI (* FLD (i_dr))), * FLD (i_sr)); + * FLD (i_dr) = opval; + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} + + abuf->written = written; +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_REMUH) : /* remuh $dr,$sr */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_add.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (NESI (* FLD (i_sr), 0)) { + { + SI opval = UMODSI (* FLD (i_dr), * FLD (i_sr)); + * FLD (i_dr) = opval; + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} + + abuf->written = written; +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_REMB) : /* remb $dr,$sr */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_add.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (NESI (* FLD (i_sr), 0)) { + { + SI opval = MODSI (EXTBISI (TRUNCSIBI (* FLD (i_dr))), * FLD (i_sr)); + * FLD (i_dr) = opval; + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} + + abuf->written = written; +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_REMUB) : /* remub $dr,$sr */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_add.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (NESI (* FLD (i_sr), 0)) { + { + SI opval = UMODSI (* FLD (i_dr), * FLD (i_sr)); + * FLD (i_dr) = opval; + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} + + abuf->written = written; +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_DIVUH) : /* divuh $dr,$sr */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_add.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (NESI (* FLD (i_sr), 0)) { + { + SI opval = UDIVSI (* FLD (i_dr), * FLD (i_sr)); + * FLD (i_dr) = opval; + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} + + abuf->written = written; +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_DIVB) : /* divb $dr,$sr */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_add.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (NESI (* FLD (i_sr), 0)) { + { + SI opval = DIVSI (EXTBISI (TRUNCSIBI (* FLD (i_dr))), * FLD (i_sr)); + * FLD (i_dr) = opval; + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} + + abuf->written = written; +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_DIVUB) : /* divub $dr,$sr */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_add.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (NESI (* FLD (i_sr), 0)) { + { + SI opval = UDIVSI (* FLD (i_dr), * FLD (i_sr)); + * FLD (i_dr) = opval; + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} + + abuf->written = written; +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_DIVH) : /* divh $dr,$sr */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_add.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (NESI (* FLD (i_sr), 0)) { + { + SI opval = DIVSI (EXTHISI (TRUNCSIHI (* FLD (i_dr))), * FLD (i_sr)); + * FLD (i_dr) = opval; + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} + + abuf->written = written; +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_JC) : /* jc $sr */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_jl.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + +if (CPU (h_cond)) { + { + USI opval = ANDSI (* FLD (i_sr), -4); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_JNC) : /* jnc $sr */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_jl.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + +if (NOTBI (CPU (h_cond))) { + { + USI opval = ANDSI (* FLD (i_sr), -4); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_JL) : /* jl $sr */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_jl.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + +{ + SI temp0;USI temp1; + temp0 = ADDSI (ANDSI (pc, -4), 4); + temp1 = ANDSI (* FLD (i_sr), -4); + { + SI opval = temp0; + CPU (h_gr[((UINT) 14)]) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + { + USI opval = temp1; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} + + SEM_BRANCH_FINI (vpc); +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_JMP) : /* jmp $sr */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_jl.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + USI opval = ANDSI (* FLD (i_sr), -4); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } + + SEM_BRANCH_FINI (vpc); +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_LD) : /* ld $dr,@$sr */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_ld_plus.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + SI opval = GETMEMSI (current_cpu, pc, * FLD (i_sr)); + * FLD (i_dr) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_LD_D) : /* ld $dr,@($slo16,$sr) */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_add3.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = GETMEMSI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))); + * FLD (i_dr) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_LDB) : /* ldb $dr,@$sr */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_ld_plus.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + SI opval = EXTQISI (GETMEMQI (current_cpu, pc, * FLD (i_sr))); + * FLD (i_dr) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_LDB_D) : /* ldb $dr,@($slo16,$sr) */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_add3.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = EXTQISI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16)))); + * FLD (i_dr) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_LDH) : /* ldh $dr,@$sr */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_ld_plus.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + SI opval = EXTHISI (GETMEMHI (current_cpu, pc, * FLD (i_sr))); + * FLD (i_dr) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_LDH_D) : /* ldh $dr,@($slo16,$sr) */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_add3.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = EXTHISI (GETMEMHI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16)))); + * FLD (i_dr) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_LDUB) : /* ldub $dr,@$sr */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_ld_plus.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, * FLD (i_sr))); + * FLD (i_dr) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_LDUB_D) : /* ldub $dr,@($slo16,$sr) */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_add3.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16)))); + * FLD (i_dr) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_LDUH) : /* lduh $dr,@$sr */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_ld_plus.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, * FLD (i_sr))); + * FLD (i_dr) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_LDUH_D) : /* lduh $dr,@($slo16,$sr) */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_add3.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16)))); + * FLD (i_dr) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_LD_PLUS) : /* ld $dr,@$sr+ */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_ld_plus.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + +{ + SI temp0;SI temp1; + temp0 = GETMEMSI (current_cpu, pc, * FLD (i_sr)); + temp1 = ADDSI (* FLD (i_sr), 4); + { + SI opval = temp0; + * FLD (i_dr) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + { + SI opval = temp1; + * FLD (i_sr) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_LD24) : /* ld24 $dr,$uimm24 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_ld24.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = FLD (i_uimm24); + * FLD (i_dr) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_LDI8) : /* ldi8 $dr,$simm8 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_addi.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + SI opval = FLD (f_simm8); + * FLD (i_dr) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_LDI16) : /* ldi16 $dr,$hash$slo16 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_add3.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = FLD (f_simm16); + * FLD (i_dr) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_LOCK) : /* lock $dr,@$sr */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_ld_plus.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + +{ + { + BI opval = 1; + CPU (h_lock) = opval; + TRACE_RESULT (current_cpu, abuf, "lock", 'x', opval); + } + { + SI opval = GETMEMSI (current_cpu, pc, * FLD (i_sr)); + * FLD (i_dr) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_MACHI_A) : /* machi $src1,$src2,$acc */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_machi_a.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUMS (FLD (f_acc)), MULDI (EXTSIDI (ANDSI (* FLD (i_src1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16))))), 8), 8); + SET_H_ACCUMS (FLD (f_acc), opval); + TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_MACLO_A) : /* maclo $src1,$src2,$acc */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_machi_a.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUMS (FLD (f_acc)), MULDI (EXTSIDI (SLLSI (* FLD (i_src1), 16)), EXTHIDI (TRUNCSIHI (* FLD (i_src2))))), 8), 8); + SET_H_ACCUMS (FLD (f_acc), opval); + TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_MACWHI_A) : /* macwhi $src1,$src2,$acc */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_machi_a.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + DI opval = ADDDI (GET_H_ACCUMS (FLD (f_acc)), MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16))))); + SET_H_ACCUMS (FLD (f_acc), opval); + TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_MACWLO_A) : /* macwlo $src1,$src2,$acc */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_machi_a.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + DI opval = ADDDI (GET_H_ACCUMS (FLD (f_acc)), MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (* FLD (i_src2))))); + SET_H_ACCUMS (FLD (f_acc), opval); + TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_MUL) : /* mul $dr,$sr */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_add.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + SI opval = MULSI (* FLD (i_dr), * FLD (i_sr)); + * FLD (i_dr) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_MULHI_A) : /* mulhi $src1,$src2,$acc */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_machi_a.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + DI opval = SRADI (SLLDI (MULDI (EXTSIDI (ANDSI (* FLD (i_src1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16)))), 16), 16); + SET_H_ACCUMS (FLD (f_acc), opval); + TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_MULLO_A) : /* mullo $src1,$src2,$acc */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_machi_a.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + DI opval = SRADI (SLLDI (MULDI (EXTSIDI (SLLSI (* FLD (i_src1), 16)), EXTHIDI (TRUNCSIHI (* FLD (i_src2)))), 16), 16); + SET_H_ACCUMS (FLD (f_acc), opval); + TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_MULWHI_A) : /* mulwhi $src1,$src2,$acc */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_machi_a.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + DI opval = MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16)))); + SET_H_ACCUMS (FLD (f_acc), opval); + TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_MULWLO_A) : /* mulwlo $src1,$src2,$acc */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_machi_a.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + DI opval = MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (* FLD (i_src2)))); + SET_H_ACCUMS (FLD (f_acc), opval); + TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_MV) : /* mv $dr,$sr */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_ld_plus.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + SI opval = * FLD (i_sr); + * FLD (i_dr) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_MVFACHI_A) : /* mvfachi $dr,$accs */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_mvfachi_a.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + SI opval = TRUNCDISI (SRADI (GET_H_ACCUMS (FLD (f_accs)), 32)); + * FLD (i_dr) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_MVFACLO_A) : /* mvfaclo $dr,$accs */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_mvfachi_a.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + SI opval = TRUNCDISI (GET_H_ACCUMS (FLD (f_accs))); + * FLD (i_dr) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_MVFACMI_A) : /* mvfacmi $dr,$accs */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_mvfachi_a.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + SI opval = TRUNCDISI (SRADI (GET_H_ACCUMS (FLD (f_accs)), 16)); + * FLD (i_dr) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_MVFC) : /* mvfc $dr,$scr */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_ld_plus.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + SI opval = GET_H_CR (FLD (f_r2)); + * FLD (i_dr) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_MVTACHI_A) : /* mvtachi $src1,$accs */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_mvtachi_a.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + DI opval = ORDI (ANDDI (GET_H_ACCUMS (FLD (f_accs)), MAKEDI (0, 0xffffffff)), SLLDI (EXTSIDI (* FLD (i_src1)), 32)); + SET_H_ACCUMS (FLD (f_accs), opval); + TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_MVTACLO_A) : /* mvtaclo $src1,$accs */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_mvtachi_a.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + DI opval = ORDI (ANDDI (GET_H_ACCUMS (FLD (f_accs)), MAKEDI (0xffffffff, 0)), ZEXTSIDI (* FLD (i_src1))); + SET_H_ACCUMS (FLD (f_accs), opval); + TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_MVTC) : /* mvtc $sr,$dcr */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_ld_plus.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + USI opval = * FLD (i_sr); + SET_H_CR (FLD (f_r1), opval); + TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_NEG) : /* neg $dr,$sr */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_ld_plus.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + SI opval = NEGSI (* FLD (i_sr)); + * FLD (i_dr) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_NOP) : /* nop */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + +PROFILE_COUNT_FILLNOPS (current_cpu, abuf->addr); + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_NOT) : /* not $dr,$sr */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_ld_plus.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + SI opval = INVSI (* FLD (i_sr)); + * FLD (i_dr) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_RAC_DSI) : /* rac $accd,$accs,$imm1 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_rac_dsi.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + +{ + DI tmp_tmp1; + tmp_tmp1 = SLLDI (GET_H_ACCUMS (FLD (f_accs)), FLD (f_imm1)); + tmp_tmp1 = ADDDI (tmp_tmp1, MAKEDI (0, 32768)); + { + DI opval = (GTDI (tmp_tmp1, MAKEDI (32767, 0xffff0000))) ? (MAKEDI (32767, 0xffff0000)) : (LTDI (tmp_tmp1, MAKEDI (0xffff8000, 0))) ? (MAKEDI (0xffff8000, 0)) : (ANDDI (tmp_tmp1, MAKEDI (0xffffffff, 0xffff0000))); + SET_H_ACCUMS (FLD (f_accd), opval); + TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval); + } +} + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_RACH_DSI) : /* rach $accd,$accs,$imm1 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_rac_dsi.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + +{ + DI tmp_tmp1; + tmp_tmp1 = SLLDI (GET_H_ACCUMS (FLD (f_accs)), FLD (f_imm1)); + tmp_tmp1 = ADDDI (tmp_tmp1, MAKEDI (0, 0x80000000)); + { + DI opval = (GTDI (tmp_tmp1, MAKEDI (32767, 0))) ? (MAKEDI (32767, 0)) : (LTDI (tmp_tmp1, MAKEDI (0xffff8000, 0))) ? (MAKEDI (0xffff8000, 0)) : (ANDDI (tmp_tmp1, MAKEDI (0xffffffff, 0))); + SET_H_ACCUMS (FLD (f_accd), opval); + TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval); + } +} + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_RTE) : /* rte */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + +{ + { + USI opval = ANDSI (GET_H_CR (((UINT) 6)), -4); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } + { + USI opval = GET_H_CR (((UINT) 14)); + SET_H_CR (((UINT) 6), opval); + TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval); + } + { + UQI opval = CPU (h_bpsw); + SET_H_PSW (opval); + TRACE_RESULT (current_cpu, abuf, "psw", 'x', opval); + } + { + UQI opval = CPU (h_bbpsw); + CPU (h_bpsw) = opval; + TRACE_RESULT (current_cpu, abuf, "bpsw", 'x', opval); + } +} + + SEM_BRANCH_FINI (vpc); +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_SETH) : /* seth $dr,$hash$hi16 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_seth.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = SLLSI (FLD (f_hi16), 16); + * FLD (i_dr) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_SLL) : /* sll $dr,$sr */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_add.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + SI opval = SLLSI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31)); + * FLD (i_dr) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_SLL3) : /* sll3 $dr,$sr,$simm16 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_add3.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = SLLSI (* FLD (i_sr), ANDSI (FLD (f_simm16), 31)); + * FLD (i_dr) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_SLLI) : /* slli $dr,$uimm5 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_slli.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + SI opval = SLLSI (* FLD (i_dr), FLD (f_uimm5)); + * FLD (i_dr) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_SRA) : /* sra $dr,$sr */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_add.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + SI opval = SRASI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31)); + * FLD (i_dr) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_SRA3) : /* sra3 $dr,$sr,$simm16 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_add3.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = SRASI (* FLD (i_sr), ANDSI (FLD (f_simm16), 31)); + * FLD (i_dr) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_SRAI) : /* srai $dr,$uimm5 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_slli.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + SI opval = SRASI (* FLD (i_dr), FLD (f_uimm5)); + * FLD (i_dr) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_SRL) : /* srl $dr,$sr */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_add.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + SI opval = SRLSI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31)); + * FLD (i_dr) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_SRL3) : /* srl3 $dr,$sr,$simm16 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_add3.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = SRLSI (* FLD (i_sr), ANDSI (FLD (f_simm16), 31)); + * FLD (i_dr) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_SRLI) : /* srli $dr,$uimm5 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_slli.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + SI opval = SRLSI (* FLD (i_dr), FLD (f_uimm5)); + * FLD (i_dr) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_ST) : /* st $src1,@$src2 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_st_plus.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + SI opval = * FLD (i_src1); + SETMEMSI (current_cpu, pc, * FLD (i_src2), opval); + TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_ST_D) : /* st $src1,@($slo16,$src2) */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_st_d.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = * FLD (i_src1); + SETMEMSI (current_cpu, pc, ADDSI (* FLD (i_src2), FLD (f_simm16)), opval); + TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_STB) : /* stb $src1,@$src2 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_st_plus.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + QI opval = * FLD (i_src1); + SETMEMQI (current_cpu, pc, * FLD (i_src2), opval); + TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_STB_D) : /* stb $src1,@($slo16,$src2) */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_st_d.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + QI opval = * FLD (i_src1); + SETMEMQI (current_cpu, pc, ADDSI (* FLD (i_src2), FLD (f_simm16)), opval); + TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_STH) : /* sth $src1,@$src2 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_st_plus.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + HI opval = * FLD (i_src1); + SETMEMHI (current_cpu, pc, * FLD (i_src2), opval); + TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_STH_D) : /* sth $src1,@($slo16,$src2) */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_st_d.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + HI opval = * FLD (i_src1); + SETMEMHI (current_cpu, pc, ADDSI (* FLD (i_src2), FLD (f_simm16)), opval); + TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_ST_PLUS) : /* st $src1,@+$src2 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_st_plus.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + +{ + SI tmp_new_src2; + tmp_new_src2 = ADDSI (* FLD (i_src2), 4); + { + SI opval = * FLD (i_src1); + SETMEMSI (current_cpu, pc, tmp_new_src2, opval); + TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); + } + { + SI opval = tmp_new_src2; + * FLD (i_src2) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_STH_PLUS) : /* sth $src1,@$src2+ */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_st_plus.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + +{ + HI tmp_new_src2; + { + HI opval = * FLD (i_src1); + SETMEMHI (current_cpu, pc, tmp_new_src2, opval); + TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); + } + tmp_new_src2 = ADDSI (* FLD (i_src2), 2); + { + SI opval = tmp_new_src2; + * FLD (i_src2) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_STB_PLUS) : /* stb $src1,@$src2+ */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_st_plus.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + +{ + QI tmp_new_src2; + { + QI opval = * FLD (i_src1); + SETMEMQI (current_cpu, pc, tmp_new_src2, opval); + TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); + } + tmp_new_src2 = ADDSI (* FLD (i_src2), 1); + { + SI opval = tmp_new_src2; + * FLD (i_src2) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_ST_MINUS) : /* st $src1,@-$src2 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_st_plus.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + +{ + SI tmp_new_src2; + tmp_new_src2 = SUBSI (* FLD (i_src2), 4); + { + SI opval = * FLD (i_src1); + SETMEMSI (current_cpu, pc, tmp_new_src2, opval); + TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); + } + { + SI opval = tmp_new_src2; + * FLD (i_src2) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_SUB) : /* sub $dr,$sr */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_add.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + SI opval = SUBSI (* FLD (i_dr), * FLD (i_sr)); + * FLD (i_dr) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_SUBV) : /* subv $dr,$sr */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_add.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + +{ + SI temp0;BI temp1; + temp0 = SUBSI (* FLD (i_dr), * FLD (i_sr)); + temp1 = SUBOFSI (* FLD (i_dr), * FLD (i_sr), 0); + { + SI opval = temp0; + * FLD (i_dr) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + { + BI opval = temp1; + CPU (h_cond) = opval; + TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval); + } +} + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_SUBX) : /* subx $dr,$sr */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_add.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + +{ + SI temp0;BI temp1; + temp0 = SUBCSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond)); + temp1 = SUBCFSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond)); + { + SI opval = temp0; + * FLD (i_dr) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + { + BI opval = temp1; + CPU (h_cond) = opval; + TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval); + } +} + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_TRAP) : /* trap $uimm4 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_trap.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + +{ + { + USI opval = GET_H_CR (((UINT) 6)); + SET_H_CR (((UINT) 14), opval); + TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval); + } + { + USI opval = ADDSI (pc, 4); + SET_H_CR (((UINT) 6), opval); + TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval); + } + { + UQI opval = CPU (h_bpsw); + CPU (h_bbpsw) = opval; + TRACE_RESULT (current_cpu, abuf, "bbpsw", 'x', opval); + } + { + UQI opval = GET_H_PSW (); + CPU (h_bpsw) = opval; + TRACE_RESULT (current_cpu, abuf, "bpsw", 'x', opval); + } + { + UQI opval = ANDQI (GET_H_PSW (), 128); + SET_H_PSW (opval); + TRACE_RESULT (current_cpu, abuf, "psw", 'x', opval); + } + { + SI opval = m32r_trap (current_cpu, pc, FLD (f_uimm4)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} + + SEM_BRANCH_FINI (vpc); +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_UNLOCK) : /* unlock $src1,@$src2 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_st_plus.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + +{ +if (CPU (h_lock)) { + { + SI opval = * FLD (i_src1); + SETMEMSI (current_cpu, pc, * FLD (i_src2), opval); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); + } +} + { + BI opval = 0; + CPU (h_lock) = opval; + TRACE_RESULT (current_cpu, abuf, "lock", 'x', opval); + } +} + + abuf->written = written; +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_SATB) : /* satb $dr,$sr */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_ld_plus.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = (GESI (* FLD (i_sr), 127)) ? (127) : (LESI (* FLD (i_sr), -128)) ? (-128) : (* FLD (i_sr)); + * FLD (i_dr) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_SATH) : /* sath $dr,$sr */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_ld_plus.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = (GESI (* FLD (i_sr), 32767)) ? (32767) : (LESI (* FLD (i_sr), -32768)) ? (-32768) : (* FLD (i_sr)); + * FLD (i_dr) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_SAT) : /* sat $dr,$sr */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_ld_plus.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = ((CPU (h_cond)) ? (((LTSI (* FLD (i_sr), 0)) ? (2147483647) : (0x80000000))) : (* FLD (i_sr))); + * FLD (i_dr) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_PCMPBZ) : /* pcmpbz $src2 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_st_plus.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + BI opval = (EQSI (ANDSI (* FLD (i_src2), 255), 0)) ? (1) : (EQSI (ANDSI (* FLD (i_src2), 65280), 0)) ? (1) : (EQSI (ANDSI (* FLD (i_src2), 16711680), 0)) ? (1) : (EQSI (ANDSI (* FLD (i_src2), 0xff000000), 0)) ? (1) : (0); + CPU (h_cond) = opval; + TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_SADD) : /* sadd */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + DI opval = ADDDI (SRADI (GET_H_ACCUMS (((UINT) 1)), 16), GET_H_ACCUMS (((UINT) 0))); + SET_H_ACCUMS (((UINT) 0), opval); + TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_MACWU1) : /* macwu1 $src1,$src2 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_st_plus.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUMS (((UINT) 1)), MULDI (EXTSIDI (* FLD (i_src1)), EXTSIDI (ANDSI (* FLD (i_src2), 65535)))), 8), 8); + SET_H_ACCUMS (((UINT) 1), opval); + TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_MSBLO) : /* msblo $src1,$src2 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_st_plus.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + DI opval = SRADI (SLLDI (SUBDI (GET_H_ACCUM (), SRADI (SLLDI (MULDI (EXTHIDI (TRUNCSIHI (* FLD (i_src1))), EXTHIDI (TRUNCSIHI (* FLD (i_src2)))), 32), 16)), 8), 8); + SET_H_ACCUM (opval); + TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_MULWU1) : /* mulwu1 $src1,$src2 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_st_plus.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + DI opval = SRADI (SLLDI (MULDI (EXTSIDI (* FLD (i_src1)), EXTSIDI (ANDSI (* FLD (i_src2), 65535))), 16), 16); + SET_H_ACCUMS (((UINT) 1), opval); + TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_MACLH1) : /* maclh1 $src1,$src2 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_st_plus.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUMS (((UINT) 1)), SLLDI (EXTSIDI (MULSI (EXTHISI (TRUNCSIHI (* FLD (i_src1))), SRASI (* FLD (i_src2), 16))), 16)), 8), 8); + SET_H_ACCUMS (((UINT) 1), opval); + TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_SC) : /* sc */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + +if (ZEXTBISI (CPU (h_cond))) + SEM_SKIP_INSN (current_cpu, sem_arg, vpc); + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_SNC) : /* snc */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + +if (ZEXTBISI (NOTBI (CPU (h_cond)))) + SEM_SKIP_INSN (current_cpu, sem_arg, vpc); + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_CLRPSW) : /* clrpsw $uimm8 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_clrpsw.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + SI opval = ANDSI (GET_H_CR (((UINT) 0)), ORSI (INVBI (FLD (f_uimm8)), 65280)); + SET_H_CR (((UINT) 0), opval); + TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_SETPSW) : /* setpsw $uimm8 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_clrpsw.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + SI opval = FLD (f_uimm8); + SET_H_CR (((UINT) 0), opval); + TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_BSET) : /* bset $uimm3,@($slo16,$sr) */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_bset.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + QI opval = ORQI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))), SLLSI (1, SUBSI (7, FLD (f_uimm3)))); + SETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16)), opval); + TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_BCLR) : /* bclr $uimm3,@($slo16,$sr) */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_bset.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + QI opval = ANDQI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))), INVQI (SLLSI (1, SUBSI (7, FLD (f_uimm3))))); + SETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16)), opval); + TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_BTST) : /* btst $uimm3,$sr */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_bset.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + BI opval = ANDQI (SRLSI (* FLD (i_sr), SUBSI (7, FLD (f_uimm3))), 1); + CPU (h_cond) = opval; + TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_PAR_ADD) : /* add $dr,$sr */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_add.f +#define OPRND(f) par_exec->operands.sfmt_add.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + SI opval = ADDSI (* FLD (i_dr), * FLD (i_sr)); + OPRND (dr) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef OPRND +#undef FLD +} + NEXT (vpc); + +CASE (sem, INSN_WRITE_ADD) : /* add $dr,$sr */ + { + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; +#define FLD(f) abuf->fields.sfmt_add.f +#define OPRND(f) par_exec->operands.sfmt_add.f + int UNUSED written = abuf->written; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + * FLD (i_dr) = OPRND (dr); + +#undef OPRND +#undef FLD + } + NEXT (vpc); + + CASE (sem, INSN_PAR_AND) : /* and $dr,$sr */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_add.f +#define OPRND(f) par_exec->operands.sfmt_add.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + SI opval = ANDSI (* FLD (i_dr), * FLD (i_sr)); + OPRND (dr) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef OPRND +#undef FLD +} + NEXT (vpc); + +CASE (sem, INSN_WRITE_AND) : /* and $dr,$sr */ + { + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; +#define FLD(f) abuf->fields.sfmt_add.f +#define OPRND(f) par_exec->operands.sfmt_add.f + int UNUSED written = abuf->written; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + * FLD (i_dr) = OPRND (dr); + +#undef OPRND +#undef FLD + } + NEXT (vpc); + + CASE (sem, INSN_PAR_OR) : /* or $dr,$sr */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_add.f +#define OPRND(f) par_exec->operands.sfmt_add.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + SI opval = ORSI (* FLD (i_dr), * FLD (i_sr)); + OPRND (dr) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef OPRND +#undef FLD +} + NEXT (vpc); + +CASE (sem, INSN_WRITE_OR) : /* or $dr,$sr */ + { + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; +#define FLD(f) abuf->fields.sfmt_add.f +#define OPRND(f) par_exec->operands.sfmt_add.f + int UNUSED written = abuf->written; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + * FLD (i_dr) = OPRND (dr); + +#undef OPRND +#undef FLD + } + NEXT (vpc); + + CASE (sem, INSN_PAR_XOR) : /* xor $dr,$sr */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_add.f +#define OPRND(f) par_exec->operands.sfmt_add.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + SI opval = XORSI (* FLD (i_dr), * FLD (i_sr)); + OPRND (dr) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef OPRND +#undef FLD +} + NEXT (vpc); + +CASE (sem, INSN_WRITE_XOR) : /* xor $dr,$sr */ + { + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; +#define FLD(f) abuf->fields.sfmt_add.f +#define OPRND(f) par_exec->operands.sfmt_add.f + int UNUSED written = abuf->written; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + * FLD (i_dr) = OPRND (dr); + +#undef OPRND +#undef FLD + } + NEXT (vpc); + + CASE (sem, INSN_PAR_ADDI) : /* addi $dr,$simm8 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_addi.f +#define OPRND(f) par_exec->operands.sfmt_addi.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + SI opval = ADDSI (* FLD (i_dr), FLD (f_simm8)); + OPRND (dr) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef OPRND +#undef FLD +} + NEXT (vpc); + +CASE (sem, INSN_WRITE_ADDI) : /* addi $dr,$simm8 */ + { + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; +#define FLD(f) abuf->fields.sfmt_addi.f +#define OPRND(f) par_exec->operands.sfmt_addi.f + int UNUSED written = abuf->written; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + * FLD (i_dr) = OPRND (dr); + +#undef OPRND +#undef FLD + } + NEXT (vpc); + + CASE (sem, INSN_PAR_ADDV) : /* addv $dr,$sr */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_add.f +#define OPRND(f) par_exec->operands.sfmt_addv.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + +{ + SI temp0;BI temp1; + temp0 = ADDSI (* FLD (i_dr), * FLD (i_sr)); + temp1 = ADDOFSI (* FLD (i_dr), * FLD (i_sr), 0); + { + SI opval = temp0; + OPRND (dr) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + { + BI opval = temp1; + OPRND (condbit) = opval; + TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval); + } +} + +#undef OPRND +#undef FLD +} + NEXT (vpc); + +CASE (sem, INSN_WRITE_ADDV) : /* addv $dr,$sr */ + { + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; +#define FLD(f) abuf->fields.sfmt_add.f +#define OPRND(f) par_exec->operands.sfmt_addv.f + int UNUSED written = abuf->written; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + CPU (h_cond) = OPRND (condbit); + * FLD (i_dr) = OPRND (dr); + +#undef OPRND +#undef FLD + } + NEXT (vpc); + + CASE (sem, INSN_PAR_ADDX) : /* addx $dr,$sr */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_add.f +#define OPRND(f) par_exec->operands.sfmt_addx.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + +{ + SI temp0;BI temp1; + temp0 = ADDCSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond)); + temp1 = ADDCFSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond)); + { + SI opval = temp0; + OPRND (dr) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + { + BI opval = temp1; + OPRND (condbit) = opval; + TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval); + } +} + +#undef OPRND +#undef FLD +} + NEXT (vpc); + +CASE (sem, INSN_WRITE_ADDX) : /* addx $dr,$sr */ + { + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; +#define FLD(f) abuf->fields.sfmt_add.f +#define OPRND(f) par_exec->operands.sfmt_addx.f + int UNUSED written = abuf->written; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + CPU (h_cond) = OPRND (condbit); + * FLD (i_dr) = OPRND (dr); + +#undef OPRND +#undef FLD + } + NEXT (vpc); + + CASE (sem, INSN_PAR_BC8) : /* bc.s $disp8 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_bl8.f +#define OPRND(f) par_exec->operands.sfmt_bc8.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + +if (CPU (h_cond)) { + { + USI opval = FLD (i_disp8); + OPRND (pc) = opval; + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} + + abuf->written = written; +#undef OPRND +#undef FLD +} + NEXT (vpc); + +CASE (sem, INSN_WRITE_BC8) : /* bc.s $disp8 */ + { + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; +#define FLD(f) abuf->fields.sfmt_bl8.f +#define OPRND(f) par_exec->operands.sfmt_bc8.f + int UNUSED written = abuf->written; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + if (written & (1 << 2)) + { + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc); + } + + SEM_BRANCH_FINI (vpc); +#undef OPRND +#undef FLD + } + NEXT (vpc); + + CASE (sem, INSN_PAR_BL8) : /* bl.s $disp8 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_bl8.f +#define OPRND(f) par_exec->operands.sfmt_bl8.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + +{ + { + SI opval = ADDSI (ANDSI (pc, -4), 4); + OPRND (h_gr_SI_14) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + { + USI opval = FLD (i_disp8); + OPRND (pc) = opval; + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} + +#undef OPRND +#undef FLD +} + NEXT (vpc); + +CASE (sem, INSN_WRITE_BL8) : /* bl.s $disp8 */ + { + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; +#define FLD(f) abuf->fields.sfmt_bl8.f +#define OPRND(f) par_exec->operands.sfmt_bl8.f + int UNUSED written = abuf->written; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + CPU (h_gr[((UINT) 14)]) = OPRND (h_gr_SI_14); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc); + + SEM_BRANCH_FINI (vpc); +#undef OPRND +#undef FLD + } + NEXT (vpc); + + CASE (sem, INSN_PAR_BCL8) : /* bcl.s $disp8 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_bl8.f +#define OPRND(f) par_exec->operands.sfmt_bcl8.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + +if (CPU (h_cond)) { +{ + { + SI opval = ADDSI (ANDSI (pc, -4), 4); + OPRND (h_gr_SI_14) = opval; + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + { + USI opval = FLD (i_disp8); + OPRND (pc) = opval; + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} + + abuf->written = written; +#undef OPRND +#undef FLD +} + NEXT (vpc); + +CASE (sem, INSN_WRITE_BCL8) : /* bcl.s $disp8 */ + { + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; +#define FLD(f) abuf->fields.sfmt_bl8.f +#define OPRND(f) par_exec->operands.sfmt_bcl8.f + int UNUSED written = abuf->written; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + if (written & (1 << 3)) + { + CPU (h_gr[((UINT) 14)]) = OPRND (h_gr_SI_14); + } + if (written & (1 << 4)) + { + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc); + } + + SEM_BRANCH_FINI (vpc); +#undef OPRND +#undef FLD + } + NEXT (vpc); + + CASE (sem, INSN_PAR_BNC8) : /* bnc.s $disp8 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_bl8.f +#define OPRND(f) par_exec->operands.sfmt_bc8.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + +if (NOTBI (CPU (h_cond))) { + { + USI opval = FLD (i_disp8); + OPRND (pc) = opval; + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} + + abuf->written = written; +#undef OPRND +#undef FLD +} + NEXT (vpc); + +CASE (sem, INSN_WRITE_BNC8) : /* bnc.s $disp8 */ + { + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; +#define FLD(f) abuf->fields.sfmt_bl8.f +#define OPRND(f) par_exec->operands.sfmt_bc8.f + int UNUSED written = abuf->written; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + if (written & (1 << 2)) + { + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc); + } + + SEM_BRANCH_FINI (vpc); +#undef OPRND +#undef FLD + } + NEXT (vpc); + + CASE (sem, INSN_PAR_BRA8) : /* bra.s $disp8 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_bl8.f +#define OPRND(f) par_exec->operands.sfmt_bra8.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + USI opval = FLD (i_disp8); + OPRND (pc) = opval; + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } + +#undef OPRND +#undef FLD +} + NEXT (vpc); + +CASE (sem, INSN_WRITE_BRA8) : /* bra.s $disp8 */ + { + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; +#define FLD(f) abuf->fields.sfmt_bl8.f +#define OPRND(f) par_exec->operands.sfmt_bra8.f + int UNUSED written = abuf->written; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc); + + SEM_BRANCH_FINI (vpc); +#undef OPRND +#undef FLD + } + NEXT (vpc); + + CASE (sem, INSN_PAR_BNCL8) : /* bncl.s $disp8 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_bl8.f +#define OPRND(f) par_exec->operands.sfmt_bcl8.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + +if (NOTBI (CPU (h_cond))) { +{ + { + SI opval = ADDSI (ANDSI (pc, -4), 4); + OPRND (h_gr_SI_14) = opval; + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + { + USI opval = FLD (i_disp8); + OPRND (pc) = opval; + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} + + abuf->written = written; +#undef OPRND +#undef FLD +} + NEXT (vpc); + +CASE (sem, INSN_WRITE_BNCL8) : /* bncl.s $disp8 */ + { + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; +#define FLD(f) abuf->fields.sfmt_bl8.f +#define OPRND(f) par_exec->operands.sfmt_bcl8.f + int UNUSED written = abuf->written; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + if (written & (1 << 3)) + { + CPU (h_gr[((UINT) 14)]) = OPRND (h_gr_SI_14); + } + if (written & (1 << 4)) + { + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc); + } + + SEM_BRANCH_FINI (vpc); +#undef OPRND +#undef FLD + } + NEXT (vpc); + + CASE (sem, INSN_PAR_CMP) : /* cmp $src1,$src2 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_st_plus.f +#define OPRND(f) par_exec->operands.sfmt_cmp.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + BI opval = LTSI (* FLD (i_src1), * FLD (i_src2)); + OPRND (condbit) = opval; + TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval); + } + +#undef OPRND +#undef FLD +} + NEXT (vpc); + +CASE (sem, INSN_WRITE_CMP) : /* cmp $src1,$src2 */ + { + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; +#define FLD(f) abuf->fields.sfmt_st_plus.f +#define OPRND(f) par_exec->operands.sfmt_cmp.f + int UNUSED written = abuf->written; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + CPU (h_cond) = OPRND (condbit); + +#undef OPRND +#undef FLD + } + NEXT (vpc); + + CASE (sem, INSN_PAR_CMPU) : /* cmpu $src1,$src2 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_st_plus.f +#define OPRND(f) par_exec->operands.sfmt_cmp.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + BI opval = LTUSI (* FLD (i_src1), * FLD (i_src2)); + OPRND (condbit) = opval; + TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval); + } + +#undef OPRND +#undef FLD +} + NEXT (vpc); + +CASE (sem, INSN_WRITE_CMPU) : /* cmpu $src1,$src2 */ + { + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; +#define FLD(f) abuf->fields.sfmt_st_plus.f +#define OPRND(f) par_exec->operands.sfmt_cmp.f + int UNUSED written = abuf->written; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + CPU (h_cond) = OPRND (condbit); + +#undef OPRND +#undef FLD + } + NEXT (vpc); + + CASE (sem, INSN_PAR_CMPEQ) : /* cmpeq $src1,$src2 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_st_plus.f +#define OPRND(f) par_exec->operands.sfmt_cmp.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + BI opval = EQSI (* FLD (i_src1), * FLD (i_src2)); + OPRND (condbit) = opval; + TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval); + } + +#undef OPRND +#undef FLD +} + NEXT (vpc); + +CASE (sem, INSN_WRITE_CMPEQ) : /* cmpeq $src1,$src2 */ + { + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; +#define FLD(f) abuf->fields.sfmt_st_plus.f +#define OPRND(f) par_exec->operands.sfmt_cmp.f + int UNUSED written = abuf->written; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + CPU (h_cond) = OPRND (condbit); + +#undef OPRND +#undef FLD + } + NEXT (vpc); + + CASE (sem, INSN_PAR_CMPZ) : /* cmpz $src2 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_st_plus.f +#define OPRND(f) par_exec->operands.sfmt_cmpz.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + BI opval = EQSI (* FLD (i_src2), 0); + OPRND (condbit) = opval; + TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval); + } + +#undef OPRND +#undef FLD +} + NEXT (vpc); + +CASE (sem, INSN_WRITE_CMPZ) : /* cmpz $src2 */ + { + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; +#define FLD(f) abuf->fields.sfmt_st_plus.f +#define OPRND(f) par_exec->operands.sfmt_cmpz.f + int UNUSED written = abuf->written; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + CPU (h_cond) = OPRND (condbit); + +#undef OPRND +#undef FLD + } + NEXT (vpc); + + CASE (sem, INSN_PAR_JC) : /* jc $sr */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_jl.f +#define OPRND(f) par_exec->operands.sfmt_jc.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + +if (CPU (h_cond)) { + { + USI opval = ANDSI (* FLD (i_sr), -4); + OPRND (pc) = opval; + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} + + abuf->written = written; +#undef OPRND +#undef FLD +} + NEXT (vpc); + +CASE (sem, INSN_WRITE_JC) : /* jc $sr */ + { + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; +#define FLD(f) abuf->fields.sfmt_jl.f +#define OPRND(f) par_exec->operands.sfmt_jc.f + int UNUSED written = abuf->written; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + if (written & (1 << 2)) + { + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc); + } + + SEM_BRANCH_FINI (vpc); +#undef OPRND +#undef FLD + } + NEXT (vpc); + + CASE (sem, INSN_PAR_JNC) : /* jnc $sr */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_jl.f +#define OPRND(f) par_exec->operands.sfmt_jc.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + +if (NOTBI (CPU (h_cond))) { + { + USI opval = ANDSI (* FLD (i_sr), -4); + OPRND (pc) = opval; + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} + + abuf->written = written; +#undef OPRND +#undef FLD +} + NEXT (vpc); + +CASE (sem, INSN_WRITE_JNC) : /* jnc $sr */ + { + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; +#define FLD(f) abuf->fields.sfmt_jl.f +#define OPRND(f) par_exec->operands.sfmt_jc.f + int UNUSED written = abuf->written; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + if (written & (1 << 2)) + { + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc); + } + + SEM_BRANCH_FINI (vpc); +#undef OPRND +#undef FLD + } + NEXT (vpc); + + CASE (sem, INSN_PAR_JL) : /* jl $sr */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_jl.f +#define OPRND(f) par_exec->operands.sfmt_jl.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + +{ + SI temp0;USI temp1; + temp0 = ADDSI (ANDSI (pc, -4), 4); + temp1 = ANDSI (* FLD (i_sr), -4); + { + SI opval = temp0; + OPRND (h_gr_SI_14) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + { + USI opval = temp1; + OPRND (pc) = opval; + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} + +#undef OPRND +#undef FLD +} + NEXT (vpc); + +CASE (sem, INSN_WRITE_JL) : /* jl $sr */ + { + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; +#define FLD(f) abuf->fields.sfmt_jl.f +#define OPRND(f) par_exec->operands.sfmt_jl.f + int UNUSED written = abuf->written; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + CPU (h_gr[((UINT) 14)]) = OPRND (h_gr_SI_14); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc); + + SEM_BRANCH_FINI (vpc); +#undef OPRND +#undef FLD + } + NEXT (vpc); + + CASE (sem, INSN_PAR_JMP) : /* jmp $sr */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_jl.f +#define OPRND(f) par_exec->operands.sfmt_jmp.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + USI opval = ANDSI (* FLD (i_sr), -4); + OPRND (pc) = opval; + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } + +#undef OPRND +#undef FLD +} + NEXT (vpc); + +CASE (sem, INSN_WRITE_JMP) : /* jmp $sr */ + { + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; +#define FLD(f) abuf->fields.sfmt_jl.f +#define OPRND(f) par_exec->operands.sfmt_jmp.f + int UNUSED written = abuf->written; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc); + + SEM_BRANCH_FINI (vpc); +#undef OPRND +#undef FLD + } + NEXT (vpc); + + CASE (sem, INSN_PAR_LD) : /* ld $dr,@$sr */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_ld_plus.f +#define OPRND(f) par_exec->operands.sfmt_ld.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + SI opval = GETMEMSI (current_cpu, pc, * FLD (i_sr)); + OPRND (dr) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef OPRND +#undef FLD +} + NEXT (vpc); + +CASE (sem, INSN_WRITE_LD) : /* ld $dr,@$sr */ + { + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; +#define FLD(f) abuf->fields.sfmt_ld_plus.f +#define OPRND(f) par_exec->operands.sfmt_ld.f + int UNUSED written = abuf->written; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + * FLD (i_dr) = OPRND (dr); + +#undef OPRND +#undef FLD + } + NEXT (vpc); + + CASE (sem, INSN_PAR_LDB) : /* ldb $dr,@$sr */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_ld_plus.f +#define OPRND(f) par_exec->operands.sfmt_ldb.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + SI opval = EXTQISI (GETMEMQI (current_cpu, pc, * FLD (i_sr))); + OPRND (dr) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef OPRND +#undef FLD +} + NEXT (vpc); + +CASE (sem, INSN_WRITE_LDB) : /* ldb $dr,@$sr */ + { + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; +#define FLD(f) abuf->fields.sfmt_ld_plus.f +#define OPRND(f) par_exec->operands.sfmt_ldb.f + int UNUSED written = abuf->written; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + * FLD (i_dr) = OPRND (dr); + +#undef OPRND +#undef FLD + } + NEXT (vpc); + + CASE (sem, INSN_PAR_LDH) : /* ldh $dr,@$sr */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_ld_plus.f +#define OPRND(f) par_exec->operands.sfmt_ldh.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + SI opval = EXTHISI (GETMEMHI (current_cpu, pc, * FLD (i_sr))); + OPRND (dr) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef OPRND +#undef FLD +} + NEXT (vpc); + +CASE (sem, INSN_WRITE_LDH) : /* ldh $dr,@$sr */ + { + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; +#define FLD(f) abuf->fields.sfmt_ld_plus.f +#define OPRND(f) par_exec->operands.sfmt_ldh.f + int UNUSED written = abuf->written; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + * FLD (i_dr) = OPRND (dr); + +#undef OPRND +#undef FLD + } + NEXT (vpc); + + CASE (sem, INSN_PAR_LDUB) : /* ldub $dr,@$sr */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_ld_plus.f +#define OPRND(f) par_exec->operands.sfmt_ldb.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, * FLD (i_sr))); + OPRND (dr) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef OPRND +#undef FLD +} + NEXT (vpc); + +CASE (sem, INSN_WRITE_LDUB) : /* ldub $dr,@$sr */ + { + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; +#define FLD(f) abuf->fields.sfmt_ld_plus.f +#define OPRND(f) par_exec->operands.sfmt_ldb.f + int UNUSED written = abuf->written; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + * FLD (i_dr) = OPRND (dr); + +#undef OPRND +#undef FLD + } + NEXT (vpc); + + CASE (sem, INSN_PAR_LDUH) : /* lduh $dr,@$sr */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_ld_plus.f +#define OPRND(f) par_exec->operands.sfmt_ldh.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, * FLD (i_sr))); + OPRND (dr) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef OPRND +#undef FLD +} + NEXT (vpc); + +CASE (sem, INSN_WRITE_LDUH) : /* lduh $dr,@$sr */ + { + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; +#define FLD(f) abuf->fields.sfmt_ld_plus.f +#define OPRND(f) par_exec->operands.sfmt_ldh.f + int UNUSED written = abuf->written; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + * FLD (i_dr) = OPRND (dr); + +#undef OPRND +#undef FLD + } + NEXT (vpc); + + CASE (sem, INSN_PAR_LD_PLUS) : /* ld $dr,@$sr+ */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_ld_plus.f +#define OPRND(f) par_exec->operands.sfmt_ld_plus.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + +{ + SI temp0;SI temp1; + temp0 = GETMEMSI (current_cpu, pc, * FLD (i_sr)); + temp1 = ADDSI (* FLD (i_sr), 4); + { + SI opval = temp0; + OPRND (dr) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + { + SI opval = temp1; + OPRND (sr) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} + +#undef OPRND +#undef FLD +} + NEXT (vpc); + +CASE (sem, INSN_WRITE_LD_PLUS) : /* ld $dr,@$sr+ */ + { + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; +#define FLD(f) abuf->fields.sfmt_ld_plus.f +#define OPRND(f) par_exec->operands.sfmt_ld_plus.f + int UNUSED written = abuf->written; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + * FLD (i_dr) = OPRND (dr); + * FLD (i_sr) = OPRND (sr); + +#undef OPRND +#undef FLD + } + NEXT (vpc); + + CASE (sem, INSN_PAR_LDI8) : /* ldi8 $dr,$simm8 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_addi.f +#define OPRND(f) par_exec->operands.sfmt_ldi8.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + SI opval = FLD (f_simm8); + OPRND (dr) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef OPRND +#undef FLD +} + NEXT (vpc); + +CASE (sem, INSN_WRITE_LDI8) : /* ldi8 $dr,$simm8 */ + { + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; +#define FLD(f) abuf->fields.sfmt_addi.f +#define OPRND(f) par_exec->operands.sfmt_ldi8.f + int UNUSED written = abuf->written; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + * FLD (i_dr) = OPRND (dr); + +#undef OPRND +#undef FLD + } + NEXT (vpc); + + CASE (sem, INSN_PAR_LOCK) : /* lock $dr,@$sr */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_ld_plus.f +#define OPRND(f) par_exec->operands.sfmt_lock.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + +{ + { + BI opval = 1; + OPRND (h_lock_BI) = opval; + TRACE_RESULT (current_cpu, abuf, "lock", 'x', opval); + } + { + SI opval = GETMEMSI (current_cpu, pc, * FLD (i_sr)); + OPRND (dr) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} + +#undef OPRND +#undef FLD +} + NEXT (vpc); + +CASE (sem, INSN_WRITE_LOCK) : /* lock $dr,@$sr */ + { + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; +#define FLD(f) abuf->fields.sfmt_ld_plus.f +#define OPRND(f) par_exec->operands.sfmt_lock.f + int UNUSED written = abuf->written; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + * FLD (i_dr) = OPRND (dr); + CPU (h_lock) = OPRND (h_lock_BI); + +#undef OPRND +#undef FLD + } + NEXT (vpc); + + CASE (sem, INSN_PAR_MACHI_A) : /* machi $src1,$src2,$acc */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_machi_a.f +#define OPRND(f) par_exec->operands.sfmt_machi_a.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUMS (FLD (f_acc)), MULDI (EXTSIDI (ANDSI (* FLD (i_src1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16))))), 8), 8); + OPRND (acc) = opval; + TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval); + } + +#undef OPRND +#undef FLD +} + NEXT (vpc); + +CASE (sem, INSN_WRITE_MACHI_A) : /* machi $src1,$src2,$acc */ + { + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; +#define FLD(f) abuf->fields.sfmt_machi_a.f +#define OPRND(f) par_exec->operands.sfmt_machi_a.f + int UNUSED written = abuf->written; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + SET_H_ACCUMS (FLD (f_acc), OPRND (acc)); + +#undef OPRND +#undef FLD + } + NEXT (vpc); + + CASE (sem, INSN_PAR_MACLO_A) : /* maclo $src1,$src2,$acc */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_machi_a.f +#define OPRND(f) par_exec->operands.sfmt_machi_a.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUMS (FLD (f_acc)), MULDI (EXTSIDI (SLLSI (* FLD (i_src1), 16)), EXTHIDI (TRUNCSIHI (* FLD (i_src2))))), 8), 8); + OPRND (acc) = opval; + TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval); + } + +#undef OPRND +#undef FLD +} + NEXT (vpc); + +CASE (sem, INSN_WRITE_MACLO_A) : /* maclo $src1,$src2,$acc */ + { + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; +#define FLD(f) abuf->fields.sfmt_machi_a.f +#define OPRND(f) par_exec->operands.sfmt_machi_a.f + int UNUSED written = abuf->written; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + SET_H_ACCUMS (FLD (f_acc), OPRND (acc)); + +#undef OPRND +#undef FLD + } + NEXT (vpc); + + CASE (sem, INSN_PAR_MACWHI_A) : /* macwhi $src1,$src2,$acc */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_machi_a.f +#define OPRND(f) par_exec->operands.sfmt_machi_a.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + DI opval = ADDDI (GET_H_ACCUMS (FLD (f_acc)), MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16))))); + OPRND (acc) = opval; + TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval); + } + +#undef OPRND +#undef FLD +} + NEXT (vpc); + +CASE (sem, INSN_WRITE_MACWHI_A) : /* macwhi $src1,$src2,$acc */ + { + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; +#define FLD(f) abuf->fields.sfmt_machi_a.f +#define OPRND(f) par_exec->operands.sfmt_machi_a.f + int UNUSED written = abuf->written; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + SET_H_ACCUMS (FLD (f_acc), OPRND (acc)); + +#undef OPRND +#undef FLD + } + NEXT (vpc); + + CASE (sem, INSN_PAR_MACWLO_A) : /* macwlo $src1,$src2,$acc */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_machi_a.f +#define OPRND(f) par_exec->operands.sfmt_machi_a.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + DI opval = ADDDI (GET_H_ACCUMS (FLD (f_acc)), MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (* FLD (i_src2))))); + OPRND (acc) = opval; + TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval); + } + +#undef OPRND +#undef FLD +} + NEXT (vpc); + +CASE (sem, INSN_WRITE_MACWLO_A) : /* macwlo $src1,$src2,$acc */ + { + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; +#define FLD(f) abuf->fields.sfmt_machi_a.f +#define OPRND(f) par_exec->operands.sfmt_machi_a.f + int UNUSED written = abuf->written; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + SET_H_ACCUMS (FLD (f_acc), OPRND (acc)); + +#undef OPRND +#undef FLD + } + NEXT (vpc); + + CASE (sem, INSN_PAR_MUL) : /* mul $dr,$sr */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_add.f +#define OPRND(f) par_exec->operands.sfmt_add.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + SI opval = MULSI (* FLD (i_dr), * FLD (i_sr)); + OPRND (dr) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef OPRND +#undef FLD +} + NEXT (vpc); + +CASE (sem, INSN_WRITE_MUL) : /* mul $dr,$sr */ + { + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; +#define FLD(f) abuf->fields.sfmt_add.f +#define OPRND(f) par_exec->operands.sfmt_add.f + int UNUSED written = abuf->written; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + * FLD (i_dr) = OPRND (dr); + +#undef OPRND +#undef FLD + } + NEXT (vpc); + + CASE (sem, INSN_PAR_MULHI_A) : /* mulhi $src1,$src2,$acc */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_machi_a.f +#define OPRND(f) par_exec->operands.sfmt_mulhi_a.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + DI opval = SRADI (SLLDI (MULDI (EXTSIDI (ANDSI (* FLD (i_src1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16)))), 16), 16); + OPRND (acc) = opval; + TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval); + } + +#undef OPRND +#undef FLD +} + NEXT (vpc); + +CASE (sem, INSN_WRITE_MULHI_A) : /* mulhi $src1,$src2,$acc */ + { + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; +#define FLD(f) abuf->fields.sfmt_machi_a.f +#define OPRND(f) par_exec->operands.sfmt_mulhi_a.f + int UNUSED written = abuf->written; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + SET_H_ACCUMS (FLD (f_acc), OPRND (acc)); + +#undef OPRND +#undef FLD + } + NEXT (vpc); + + CASE (sem, INSN_PAR_MULLO_A) : /* mullo $src1,$src2,$acc */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_machi_a.f +#define OPRND(f) par_exec->operands.sfmt_mulhi_a.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + DI opval = SRADI (SLLDI (MULDI (EXTSIDI (SLLSI (* FLD (i_src1), 16)), EXTHIDI (TRUNCSIHI (* FLD (i_src2)))), 16), 16); + OPRND (acc) = opval; + TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval); + } + +#undef OPRND +#undef FLD +} + NEXT (vpc); + +CASE (sem, INSN_WRITE_MULLO_A) : /* mullo $src1,$src2,$acc */ + { + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; +#define FLD(f) abuf->fields.sfmt_machi_a.f +#define OPRND(f) par_exec->operands.sfmt_mulhi_a.f + int UNUSED written = abuf->written; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + SET_H_ACCUMS (FLD (f_acc), OPRND (acc)); + +#undef OPRND +#undef FLD + } + NEXT (vpc); + + CASE (sem, INSN_PAR_MULWHI_A) : /* mulwhi $src1,$src2,$acc */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_machi_a.f +#define OPRND(f) par_exec->operands.sfmt_mulhi_a.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + DI opval = MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16)))); + OPRND (acc) = opval; + TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval); + } + +#undef OPRND +#undef FLD +} + NEXT (vpc); + +CASE (sem, INSN_WRITE_MULWHI_A) : /* mulwhi $src1,$src2,$acc */ + { + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; +#define FLD(f) abuf->fields.sfmt_machi_a.f +#define OPRND(f) par_exec->operands.sfmt_mulhi_a.f + int UNUSED written = abuf->written; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + SET_H_ACCUMS (FLD (f_acc), OPRND (acc)); + +#undef OPRND +#undef FLD + } + NEXT (vpc); + + CASE (sem, INSN_PAR_MULWLO_A) : /* mulwlo $src1,$src2,$acc */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_machi_a.f +#define OPRND(f) par_exec->operands.sfmt_mulhi_a.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + DI opval = MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (* FLD (i_src2)))); + OPRND (acc) = opval; + TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval); + } + +#undef OPRND +#undef FLD +} + NEXT (vpc); + +CASE (sem, INSN_WRITE_MULWLO_A) : /* mulwlo $src1,$src2,$acc */ + { + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; +#define FLD(f) abuf->fields.sfmt_machi_a.f +#define OPRND(f) par_exec->operands.sfmt_mulhi_a.f + int UNUSED written = abuf->written; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + SET_H_ACCUMS (FLD (f_acc), OPRND (acc)); + +#undef OPRND +#undef FLD + } + NEXT (vpc); + + CASE (sem, INSN_PAR_MV) : /* mv $dr,$sr */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_ld_plus.f +#define OPRND(f) par_exec->operands.sfmt_mv.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + SI opval = * FLD (i_sr); + OPRND (dr) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef OPRND +#undef FLD +} + NEXT (vpc); + +CASE (sem, INSN_WRITE_MV) : /* mv $dr,$sr */ + { + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; +#define FLD(f) abuf->fields.sfmt_ld_plus.f +#define OPRND(f) par_exec->operands.sfmt_mv.f + int UNUSED written = abuf->written; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + * FLD (i_dr) = OPRND (dr); + +#undef OPRND +#undef FLD + } + NEXT (vpc); + + CASE (sem, INSN_PAR_MVFACHI_A) : /* mvfachi $dr,$accs */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_mvfachi_a.f +#define OPRND(f) par_exec->operands.sfmt_mvfachi_a.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + SI opval = TRUNCDISI (SRADI (GET_H_ACCUMS (FLD (f_accs)), 32)); + OPRND (dr) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef OPRND +#undef FLD +} + NEXT (vpc); + +CASE (sem, INSN_WRITE_MVFACHI_A) : /* mvfachi $dr,$accs */ + { + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; +#define FLD(f) abuf->fields.sfmt_mvfachi_a.f +#define OPRND(f) par_exec->operands.sfmt_mvfachi_a.f + int UNUSED written = abuf->written; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + * FLD (i_dr) = OPRND (dr); + +#undef OPRND +#undef FLD + } + NEXT (vpc); + + CASE (sem, INSN_PAR_MVFACLO_A) : /* mvfaclo $dr,$accs */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_mvfachi_a.f +#define OPRND(f) par_exec->operands.sfmt_mvfachi_a.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + SI opval = TRUNCDISI (GET_H_ACCUMS (FLD (f_accs))); + OPRND (dr) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef OPRND +#undef FLD +} + NEXT (vpc); + +CASE (sem, INSN_WRITE_MVFACLO_A) : /* mvfaclo $dr,$accs */ + { + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; +#define FLD(f) abuf->fields.sfmt_mvfachi_a.f +#define OPRND(f) par_exec->operands.sfmt_mvfachi_a.f + int UNUSED written = abuf->written; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + * FLD (i_dr) = OPRND (dr); + +#undef OPRND +#undef FLD + } + NEXT (vpc); + + CASE (sem, INSN_PAR_MVFACMI_A) : /* mvfacmi $dr,$accs */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_mvfachi_a.f +#define OPRND(f) par_exec->operands.sfmt_mvfachi_a.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + SI opval = TRUNCDISI (SRADI (GET_H_ACCUMS (FLD (f_accs)), 16)); + OPRND (dr) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef OPRND +#undef FLD +} + NEXT (vpc); + +CASE (sem, INSN_WRITE_MVFACMI_A) : /* mvfacmi $dr,$accs */ + { + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; +#define FLD(f) abuf->fields.sfmt_mvfachi_a.f +#define OPRND(f) par_exec->operands.sfmt_mvfachi_a.f + int UNUSED written = abuf->written; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + * FLD (i_dr) = OPRND (dr); + +#undef OPRND +#undef FLD + } + NEXT (vpc); + + CASE (sem, INSN_PAR_MVFC) : /* mvfc $dr,$scr */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_ld_plus.f +#define OPRND(f) par_exec->operands.sfmt_mvfc.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + SI opval = GET_H_CR (FLD (f_r2)); + OPRND (dr) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef OPRND +#undef FLD +} + NEXT (vpc); + +CASE (sem, INSN_WRITE_MVFC) : /* mvfc $dr,$scr */ + { + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; +#define FLD(f) abuf->fields.sfmt_ld_plus.f +#define OPRND(f) par_exec->operands.sfmt_mvfc.f + int UNUSED written = abuf->written; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + * FLD (i_dr) = OPRND (dr); + +#undef OPRND +#undef FLD + } + NEXT (vpc); + + CASE (sem, INSN_PAR_MVTACHI_A) : /* mvtachi $src1,$accs */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_mvtachi_a.f +#define OPRND(f) par_exec->operands.sfmt_mvtachi_a.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + DI opval = ORDI (ANDDI (GET_H_ACCUMS (FLD (f_accs)), MAKEDI (0, 0xffffffff)), SLLDI (EXTSIDI (* FLD (i_src1)), 32)); + OPRND (accs) = opval; + TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval); + } + +#undef OPRND +#undef FLD +} + NEXT (vpc); + +CASE (sem, INSN_WRITE_MVTACHI_A) : /* mvtachi $src1,$accs */ + { + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; +#define FLD(f) abuf->fields.sfmt_mvtachi_a.f +#define OPRND(f) par_exec->operands.sfmt_mvtachi_a.f + int UNUSED written = abuf->written; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + SET_H_ACCUMS (FLD (f_accs), OPRND (accs)); + +#undef OPRND +#undef FLD + } + NEXT (vpc); + + CASE (sem, INSN_PAR_MVTACLO_A) : /* mvtaclo $src1,$accs */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_mvtachi_a.f +#define OPRND(f) par_exec->operands.sfmt_mvtachi_a.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + DI opval = ORDI (ANDDI (GET_H_ACCUMS (FLD (f_accs)), MAKEDI (0xffffffff, 0)), ZEXTSIDI (* FLD (i_src1))); + OPRND (accs) = opval; + TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval); + } + +#undef OPRND +#undef FLD +} + NEXT (vpc); + +CASE (sem, INSN_WRITE_MVTACLO_A) : /* mvtaclo $src1,$accs */ + { + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; +#define FLD(f) abuf->fields.sfmt_mvtachi_a.f +#define OPRND(f) par_exec->operands.sfmt_mvtachi_a.f + int UNUSED written = abuf->written; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + SET_H_ACCUMS (FLD (f_accs), OPRND (accs)); + +#undef OPRND +#undef FLD + } + NEXT (vpc); + + CASE (sem, INSN_PAR_MVTC) : /* mvtc $sr,$dcr */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_ld_plus.f +#define OPRND(f) par_exec->operands.sfmt_mvtc.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + USI opval = * FLD (i_sr); + OPRND (dcr) = opval; + TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval); + } + +#undef OPRND +#undef FLD +} + NEXT (vpc); + +CASE (sem, INSN_WRITE_MVTC) : /* mvtc $sr,$dcr */ + { + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; +#define FLD(f) abuf->fields.sfmt_ld_plus.f +#define OPRND(f) par_exec->operands.sfmt_mvtc.f + int UNUSED written = abuf->written; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + SET_H_CR (FLD (f_r1), OPRND (dcr)); + +#undef OPRND +#undef FLD + } + NEXT (vpc); + + CASE (sem, INSN_PAR_NEG) : /* neg $dr,$sr */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_ld_plus.f +#define OPRND(f) par_exec->operands.sfmt_mv.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + SI opval = NEGSI (* FLD (i_sr)); + OPRND (dr) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef OPRND +#undef FLD +} + NEXT (vpc); + +CASE (sem, INSN_WRITE_NEG) : /* neg $dr,$sr */ + { + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; +#define FLD(f) abuf->fields.sfmt_ld_plus.f +#define OPRND(f) par_exec->operands.sfmt_mv.f + int UNUSED written = abuf->written; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + * FLD (i_dr) = OPRND (dr); + +#undef OPRND +#undef FLD + } + NEXT (vpc); + + CASE (sem, INSN_PAR_NOP) : /* nop */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f +#define OPRND(f) par_exec->operands.sfmt_nop.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + +PROFILE_COUNT_FILLNOPS (current_cpu, abuf->addr); + +#undef OPRND +#undef FLD +} + NEXT (vpc); + +CASE (sem, INSN_WRITE_NOP) : /* nop */ + { + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; +#define FLD(f) abuf->fields.fmt_empty.f +#define OPRND(f) par_exec->operands.sfmt_nop.f + int UNUSED written = abuf->written; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + +#undef OPRND +#undef FLD + } + NEXT (vpc); + + CASE (sem, INSN_PAR_NOT) : /* not $dr,$sr */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_ld_plus.f +#define OPRND(f) par_exec->operands.sfmt_mv.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + SI opval = INVSI (* FLD (i_sr)); + OPRND (dr) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef OPRND +#undef FLD +} + NEXT (vpc); + +CASE (sem, INSN_WRITE_NOT) : /* not $dr,$sr */ + { + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; +#define FLD(f) abuf->fields.sfmt_ld_plus.f +#define OPRND(f) par_exec->operands.sfmt_mv.f + int UNUSED written = abuf->written; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + * FLD (i_dr) = OPRND (dr); + +#undef OPRND +#undef FLD + } + NEXT (vpc); + + CASE (sem, INSN_PAR_RAC_DSI) : /* rac $accd,$accs,$imm1 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_rac_dsi.f +#define OPRND(f) par_exec->operands.sfmt_rac_dsi.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + +{ + DI tmp_tmp1; + tmp_tmp1 = SLLDI (GET_H_ACCUMS (FLD (f_accs)), FLD (f_imm1)); + tmp_tmp1 = ADDDI (tmp_tmp1, MAKEDI (0, 32768)); + { + DI opval = (GTDI (tmp_tmp1, MAKEDI (32767, 0xffff0000))) ? (MAKEDI (32767, 0xffff0000)) : (LTDI (tmp_tmp1, MAKEDI (0xffff8000, 0))) ? (MAKEDI (0xffff8000, 0)) : (ANDDI (tmp_tmp1, MAKEDI (0xffffffff, 0xffff0000))); + OPRND (accd) = opval; + TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval); + } +} + +#undef OPRND +#undef FLD +} + NEXT (vpc); + +CASE (sem, INSN_WRITE_RAC_DSI) : /* rac $accd,$accs,$imm1 */ + { + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; +#define FLD(f) abuf->fields.sfmt_rac_dsi.f +#define OPRND(f) par_exec->operands.sfmt_rac_dsi.f + int UNUSED written = abuf->written; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + SET_H_ACCUMS (FLD (f_accd), OPRND (accd)); + +#undef OPRND +#undef FLD + } + NEXT (vpc); + + CASE (sem, INSN_PAR_RACH_DSI) : /* rach $accd,$accs,$imm1 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_rac_dsi.f +#define OPRND(f) par_exec->operands.sfmt_rac_dsi.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + +{ + DI tmp_tmp1; + tmp_tmp1 = SLLDI (GET_H_ACCUMS (FLD (f_accs)), FLD (f_imm1)); + tmp_tmp1 = ADDDI (tmp_tmp1, MAKEDI (0, 0x80000000)); + { + DI opval = (GTDI (tmp_tmp1, MAKEDI (32767, 0))) ? (MAKEDI (32767, 0)) : (LTDI (tmp_tmp1, MAKEDI (0xffff8000, 0))) ? (MAKEDI (0xffff8000, 0)) : (ANDDI (tmp_tmp1, MAKEDI (0xffffffff, 0))); + OPRND (accd) = opval; + TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval); + } +} + +#undef OPRND +#undef FLD +} + NEXT (vpc); + +CASE (sem, INSN_WRITE_RACH_DSI) : /* rach $accd,$accs,$imm1 */ + { + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; +#define FLD(f) abuf->fields.sfmt_rac_dsi.f +#define OPRND(f) par_exec->operands.sfmt_rac_dsi.f + int UNUSED written = abuf->written; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + SET_H_ACCUMS (FLD (f_accd), OPRND (accd)); + +#undef OPRND +#undef FLD + } + NEXT (vpc); + + CASE (sem, INSN_PAR_RTE) : /* rte */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f +#define OPRND(f) par_exec->operands.sfmt_rte.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + +{ + { + USI opval = ANDSI (GET_H_CR (((UINT) 6)), -4); + OPRND (pc) = opval; + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } + { + USI opval = GET_H_CR (((UINT) 14)); + OPRND (h_cr_USI_6) = opval; + TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval); + } + { + UQI opval = CPU (h_bpsw); + OPRND (h_psw_UQI) = opval; + TRACE_RESULT (current_cpu, abuf, "psw", 'x', opval); + } + { + UQI opval = CPU (h_bbpsw); + OPRND (h_bpsw_UQI) = opval; + TRACE_RESULT (current_cpu, abuf, "bpsw", 'x', opval); + } +} + +#undef OPRND +#undef FLD +} + NEXT (vpc); + +CASE (sem, INSN_WRITE_RTE) : /* rte */ + { + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; +#define FLD(f) abuf->fields.fmt_empty.f +#define OPRND(f) par_exec->operands.sfmt_rte.f + int UNUSED written = abuf->written; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + CPU (h_bpsw) = OPRND (h_bpsw_UQI); + SET_H_CR (((UINT) 6), OPRND (h_cr_USI_6)); + SET_H_PSW (OPRND (h_psw_UQI)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc); + + SEM_BRANCH_FINI (vpc); +#undef OPRND +#undef FLD + } + NEXT (vpc); + + CASE (sem, INSN_PAR_SLL) : /* sll $dr,$sr */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_add.f +#define OPRND(f) par_exec->operands.sfmt_add.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + SI opval = SLLSI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31)); + OPRND (dr) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef OPRND +#undef FLD +} + NEXT (vpc); + +CASE (sem, INSN_WRITE_SLL) : /* sll $dr,$sr */ + { + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; +#define FLD(f) abuf->fields.sfmt_add.f +#define OPRND(f) par_exec->operands.sfmt_add.f + int UNUSED written = abuf->written; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + * FLD (i_dr) = OPRND (dr); + +#undef OPRND +#undef FLD + } + NEXT (vpc); + + CASE (sem, INSN_PAR_SLLI) : /* slli $dr,$uimm5 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_slli.f +#define OPRND(f) par_exec->operands.sfmt_slli.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + SI opval = SLLSI (* FLD (i_dr), FLD (f_uimm5)); + OPRND (dr) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef OPRND +#undef FLD +} + NEXT (vpc); + +CASE (sem, INSN_WRITE_SLLI) : /* slli $dr,$uimm5 */ + { + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; +#define FLD(f) abuf->fields.sfmt_slli.f +#define OPRND(f) par_exec->operands.sfmt_slli.f + int UNUSED written = abuf->written; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + * FLD (i_dr) = OPRND (dr); + +#undef OPRND +#undef FLD + } + NEXT (vpc); + + CASE (sem, INSN_PAR_SRA) : /* sra $dr,$sr */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_add.f +#define OPRND(f) par_exec->operands.sfmt_add.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + SI opval = SRASI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31)); + OPRND (dr) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef OPRND +#undef FLD +} + NEXT (vpc); + +CASE (sem, INSN_WRITE_SRA) : /* sra $dr,$sr */ + { + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; +#define FLD(f) abuf->fields.sfmt_add.f +#define OPRND(f) par_exec->operands.sfmt_add.f + int UNUSED written = abuf->written; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + * FLD (i_dr) = OPRND (dr); + +#undef OPRND +#undef FLD + } + NEXT (vpc); + + CASE (sem, INSN_PAR_SRAI) : /* srai $dr,$uimm5 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_slli.f +#define OPRND(f) par_exec->operands.sfmt_slli.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + SI opval = SRASI (* FLD (i_dr), FLD (f_uimm5)); + OPRND (dr) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef OPRND +#undef FLD +} + NEXT (vpc); + +CASE (sem, INSN_WRITE_SRAI) : /* srai $dr,$uimm5 */ + { + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; +#define FLD(f) abuf->fields.sfmt_slli.f +#define OPRND(f) par_exec->operands.sfmt_slli.f + int UNUSED written = abuf->written; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + * FLD (i_dr) = OPRND (dr); + +#undef OPRND +#undef FLD + } + NEXT (vpc); + + CASE (sem, INSN_PAR_SRL) : /* srl $dr,$sr */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_add.f +#define OPRND(f) par_exec->operands.sfmt_add.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + SI opval = SRLSI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31)); + OPRND (dr) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef OPRND +#undef FLD +} + NEXT (vpc); + +CASE (sem, INSN_WRITE_SRL) : /* srl $dr,$sr */ + { + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; +#define FLD(f) abuf->fields.sfmt_add.f +#define OPRND(f) par_exec->operands.sfmt_add.f + int UNUSED written = abuf->written; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + * FLD (i_dr) = OPRND (dr); + +#undef OPRND +#undef FLD + } + NEXT (vpc); + + CASE (sem, INSN_PAR_SRLI) : /* srli $dr,$uimm5 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_slli.f +#define OPRND(f) par_exec->operands.sfmt_slli.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + SI opval = SRLSI (* FLD (i_dr), FLD (f_uimm5)); + OPRND (dr) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef OPRND +#undef FLD +} + NEXT (vpc); + +CASE (sem, INSN_WRITE_SRLI) : /* srli $dr,$uimm5 */ + { + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; +#define FLD(f) abuf->fields.sfmt_slli.f +#define OPRND(f) par_exec->operands.sfmt_slli.f + int UNUSED written = abuf->written; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + * FLD (i_dr) = OPRND (dr); + +#undef OPRND +#undef FLD + } + NEXT (vpc); + + CASE (sem, INSN_PAR_ST) : /* st $src1,@$src2 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_st_plus.f +#define OPRND(f) par_exec->operands.sfmt_st.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + SI opval = * FLD (i_src1); + OPRND (h_memory_SI_src2_idx) = * FLD (i_src2); + OPRND (h_memory_SI_src2) = opval; + TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); + } + +#undef OPRND +#undef FLD +} + NEXT (vpc); + +CASE (sem, INSN_WRITE_ST) : /* st $src1,@$src2 */ + { + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; +#define FLD(f) abuf->fields.sfmt_st_plus.f +#define OPRND(f) par_exec->operands.sfmt_st.f + int UNUSED written = abuf->written; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + SETMEMSI (current_cpu, pc, OPRND (h_memory_SI_src2_idx), OPRND (h_memory_SI_src2)); + +#undef OPRND +#undef FLD + } + NEXT (vpc); + + CASE (sem, INSN_PAR_STB) : /* stb $src1,@$src2 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_st_plus.f +#define OPRND(f) par_exec->operands.sfmt_stb.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + QI opval = * FLD (i_src1); + OPRND (h_memory_QI_src2_idx) = * FLD (i_src2); + OPRND (h_memory_QI_src2) = opval; + TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); + } + +#undef OPRND +#undef FLD +} + NEXT (vpc); + +CASE (sem, INSN_WRITE_STB) : /* stb $src1,@$src2 */ + { + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; +#define FLD(f) abuf->fields.sfmt_st_plus.f +#define OPRND(f) par_exec->operands.sfmt_stb.f + int UNUSED written = abuf->written; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + SETMEMQI (current_cpu, pc, OPRND (h_memory_QI_src2_idx), OPRND (h_memory_QI_src2)); + +#undef OPRND +#undef FLD + } + NEXT (vpc); + + CASE (sem, INSN_PAR_STH) : /* sth $src1,@$src2 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_st_plus.f +#define OPRND(f) par_exec->operands.sfmt_sth.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + HI opval = * FLD (i_src1); + OPRND (h_memory_HI_src2_idx) = * FLD (i_src2); + OPRND (h_memory_HI_src2) = opval; + TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); + } + +#undef OPRND +#undef FLD +} + NEXT (vpc); + +CASE (sem, INSN_WRITE_STH) : /* sth $src1,@$src2 */ + { + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; +#define FLD(f) abuf->fields.sfmt_st_plus.f +#define OPRND(f) par_exec->operands.sfmt_sth.f + int UNUSED written = abuf->written; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + SETMEMHI (current_cpu, pc, OPRND (h_memory_HI_src2_idx), OPRND (h_memory_HI_src2)); + +#undef OPRND +#undef FLD + } + NEXT (vpc); + + CASE (sem, INSN_PAR_ST_PLUS) : /* st $src1,@+$src2 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_st_plus.f +#define OPRND(f) par_exec->operands.sfmt_st_plus.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + +{ + SI tmp_new_src2; + tmp_new_src2 = ADDSI (* FLD (i_src2), 4); + { + SI opval = * FLD (i_src1); + OPRND (h_memory_SI_new_src2_idx) = tmp_new_src2; + OPRND (h_memory_SI_new_src2) = opval; + TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); + } + { + SI opval = tmp_new_src2; + OPRND (src2) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} + +#undef OPRND +#undef FLD +} + NEXT (vpc); + +CASE (sem, INSN_WRITE_ST_PLUS) : /* st $src1,@+$src2 */ + { + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; +#define FLD(f) abuf->fields.sfmt_st_plus.f +#define OPRND(f) par_exec->operands.sfmt_st_plus.f + int UNUSED written = abuf->written; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + SETMEMSI (current_cpu, pc, OPRND (h_memory_SI_new_src2_idx), OPRND (h_memory_SI_new_src2)); + * FLD (i_src2) = OPRND (src2); + +#undef OPRND +#undef FLD + } + NEXT (vpc); + + CASE (sem, INSN_PAR_STH_PLUS) : /* sth $src1,@$src2+ */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_st_plus.f +#define OPRND(f) par_exec->operands.sfmt_sth_plus.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + +{ + HI tmp_new_src2; + { + HI opval = * FLD (i_src1); + OPRND (h_memory_HI_new_src2_idx) = tmp_new_src2; + OPRND (h_memory_HI_new_src2) = opval; + TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); + } + tmp_new_src2 = ADDSI (* FLD (i_src2), 2); + { + SI opval = tmp_new_src2; + OPRND (src2) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} + +#undef OPRND +#undef FLD +} + NEXT (vpc); + +CASE (sem, INSN_WRITE_STH_PLUS) : /* sth $src1,@$src2+ */ + { + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; +#define FLD(f) abuf->fields.sfmt_st_plus.f +#define OPRND(f) par_exec->operands.sfmt_sth_plus.f + int UNUSED written = abuf->written; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + SETMEMHI (current_cpu, pc, OPRND (h_memory_HI_new_src2_idx), OPRND (h_memory_HI_new_src2)); + * FLD (i_src2) = OPRND (src2); + +#undef OPRND +#undef FLD + } + NEXT (vpc); + + CASE (sem, INSN_PAR_STB_PLUS) : /* stb $src1,@$src2+ */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_st_plus.f +#define OPRND(f) par_exec->operands.sfmt_stb_plus.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + +{ + QI tmp_new_src2; + { + QI opval = * FLD (i_src1); + OPRND (h_memory_QI_new_src2_idx) = tmp_new_src2; + OPRND (h_memory_QI_new_src2) = opval; + TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); + } + tmp_new_src2 = ADDSI (* FLD (i_src2), 1); + { + SI opval = tmp_new_src2; + OPRND (src2) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} + +#undef OPRND +#undef FLD +} + NEXT (vpc); + +CASE (sem, INSN_WRITE_STB_PLUS) : /* stb $src1,@$src2+ */ + { + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; +#define FLD(f) abuf->fields.sfmt_st_plus.f +#define OPRND(f) par_exec->operands.sfmt_stb_plus.f + int UNUSED written = abuf->written; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + SETMEMQI (current_cpu, pc, OPRND (h_memory_QI_new_src2_idx), OPRND (h_memory_QI_new_src2)); + * FLD (i_src2) = OPRND (src2); + +#undef OPRND +#undef FLD + } + NEXT (vpc); + + CASE (sem, INSN_PAR_ST_MINUS) : /* st $src1,@-$src2 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_st_plus.f +#define OPRND(f) par_exec->operands.sfmt_st_plus.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + +{ + SI tmp_new_src2; + tmp_new_src2 = SUBSI (* FLD (i_src2), 4); + { + SI opval = * FLD (i_src1); + OPRND (h_memory_SI_new_src2_idx) = tmp_new_src2; + OPRND (h_memory_SI_new_src2) = opval; + TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); + } + { + SI opval = tmp_new_src2; + OPRND (src2) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} + +#undef OPRND +#undef FLD +} + NEXT (vpc); + +CASE (sem, INSN_WRITE_ST_MINUS) : /* st $src1,@-$src2 */ + { + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; +#define FLD(f) abuf->fields.sfmt_st_plus.f +#define OPRND(f) par_exec->operands.sfmt_st_plus.f + int UNUSED written = abuf->written; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + SETMEMSI (current_cpu, pc, OPRND (h_memory_SI_new_src2_idx), OPRND (h_memory_SI_new_src2)); + * FLD (i_src2) = OPRND (src2); + +#undef OPRND +#undef FLD + } + NEXT (vpc); + + CASE (sem, INSN_PAR_SUB) : /* sub $dr,$sr */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_add.f +#define OPRND(f) par_exec->operands.sfmt_add.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + SI opval = SUBSI (* FLD (i_dr), * FLD (i_sr)); + OPRND (dr) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef OPRND +#undef FLD +} + NEXT (vpc); + +CASE (sem, INSN_WRITE_SUB) : /* sub $dr,$sr */ + { + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; +#define FLD(f) abuf->fields.sfmt_add.f +#define OPRND(f) par_exec->operands.sfmt_add.f + int UNUSED written = abuf->written; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + * FLD (i_dr) = OPRND (dr); + +#undef OPRND +#undef FLD + } + NEXT (vpc); + + CASE (sem, INSN_PAR_SUBV) : /* subv $dr,$sr */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_add.f +#define OPRND(f) par_exec->operands.sfmt_addv.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + +{ + SI temp0;BI temp1; + temp0 = SUBSI (* FLD (i_dr), * FLD (i_sr)); + temp1 = SUBOFSI (* FLD (i_dr), * FLD (i_sr), 0); + { + SI opval = temp0; + OPRND (dr) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + { + BI opval = temp1; + OPRND (condbit) = opval; + TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval); + } +} + +#undef OPRND +#undef FLD +} + NEXT (vpc); + +CASE (sem, INSN_WRITE_SUBV) : /* subv $dr,$sr */ + { + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; +#define FLD(f) abuf->fields.sfmt_add.f +#define OPRND(f) par_exec->operands.sfmt_addv.f + int UNUSED written = abuf->written; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + CPU (h_cond) = OPRND (condbit); + * FLD (i_dr) = OPRND (dr); + +#undef OPRND +#undef FLD + } + NEXT (vpc); + + CASE (sem, INSN_PAR_SUBX) : /* subx $dr,$sr */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_add.f +#define OPRND(f) par_exec->operands.sfmt_addx.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + +{ + SI temp0;BI temp1; + temp0 = SUBCSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond)); + temp1 = SUBCFSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond)); + { + SI opval = temp0; + OPRND (dr) = opval; + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + { + BI opval = temp1; + OPRND (condbit) = opval; + TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval); + } +} + +#undef OPRND +#undef FLD +} + NEXT (vpc); + +CASE (sem, INSN_WRITE_SUBX) : /* subx $dr,$sr */ + { + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; +#define FLD(f) abuf->fields.sfmt_add.f +#define OPRND(f) par_exec->operands.sfmt_addx.f + int UNUSED written = abuf->written; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + CPU (h_cond) = OPRND (condbit); + * FLD (i_dr) = OPRND (dr); + +#undef OPRND +#undef FLD + } + NEXT (vpc); + + CASE (sem, INSN_PAR_TRAP) : /* trap $uimm4 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_trap.f +#define OPRND(f) par_exec->operands.sfmt_trap.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + +{ + { + USI opval = GET_H_CR (((UINT) 6)); + OPRND (h_cr_USI_14) = opval; + TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval); + } + { + USI opval = ADDSI (pc, 4); + OPRND (h_cr_USI_6) = opval; + TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval); + } + { + UQI opval = CPU (h_bpsw); + OPRND (h_bbpsw_UQI) = opval; + TRACE_RESULT (current_cpu, abuf, "bbpsw", 'x', opval); + } + { + UQI opval = GET_H_PSW (); + OPRND (h_bpsw_UQI) = opval; + TRACE_RESULT (current_cpu, abuf, "bpsw", 'x', opval); + } + { + UQI opval = ANDQI (GET_H_PSW (), 128); + OPRND (h_psw_UQI) = opval; + TRACE_RESULT (current_cpu, abuf, "psw", 'x', opval); + } + { + SI opval = m32r_trap (current_cpu, pc, FLD (f_uimm4)); + OPRND (pc) = opval; + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} + +#undef OPRND +#undef FLD +} + NEXT (vpc); + +CASE (sem, INSN_WRITE_TRAP) : /* trap $uimm4 */ + { + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; +#define FLD(f) abuf->fields.sfmt_trap.f +#define OPRND(f) par_exec->operands.sfmt_trap.f + int UNUSED written = abuf->written; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + CPU (h_bbpsw) = OPRND (h_bbpsw_UQI); + CPU (h_bpsw) = OPRND (h_bpsw_UQI); + SET_H_CR (((UINT) 14), OPRND (h_cr_USI_14)); + SET_H_CR (((UINT) 6), OPRND (h_cr_USI_6)); + SET_H_PSW (OPRND (h_psw_UQI)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc); + + SEM_BRANCH_FINI (vpc); +#undef OPRND +#undef FLD + } + NEXT (vpc); + + CASE (sem, INSN_PAR_UNLOCK) : /* unlock $src1,@$src2 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_st_plus.f +#define OPRND(f) par_exec->operands.sfmt_unlock.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + +{ +if (CPU (h_lock)) { + { + SI opval = * FLD (i_src1); + OPRND (h_memory_SI_src2_idx) = * FLD (i_src2); + OPRND (h_memory_SI_src2) = opval; + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); + } +} + { + BI opval = 0; + OPRND (h_lock_BI) = opval; + TRACE_RESULT (current_cpu, abuf, "lock", 'x', opval); + } +} + + abuf->written = written; +#undef OPRND +#undef FLD +} + NEXT (vpc); + +CASE (sem, INSN_WRITE_UNLOCK) : /* unlock $src1,@$src2 */ + { + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; +#define FLD(f) abuf->fields.sfmt_st_plus.f +#define OPRND(f) par_exec->operands.sfmt_unlock.f + int UNUSED written = abuf->written; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + CPU (h_lock) = OPRND (h_lock_BI); + if (written & (1 << 4)) + { + SETMEMSI (current_cpu, pc, OPRND (h_memory_SI_src2_idx), OPRND (h_memory_SI_src2)); + } + +#undef OPRND +#undef FLD + } + NEXT (vpc); + + CASE (sem, INSN_PAR_PCMPBZ) : /* pcmpbz $src2 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_st_plus.f +#define OPRND(f) par_exec->operands.sfmt_cmpz.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + BI opval = (EQSI (ANDSI (* FLD (i_src2), 255), 0)) ? (1) : (EQSI (ANDSI (* FLD (i_src2), 65280), 0)) ? (1) : (EQSI (ANDSI (* FLD (i_src2), 16711680), 0)) ? (1) : (EQSI (ANDSI (* FLD (i_src2), 0xff000000), 0)) ? (1) : (0); + OPRND (condbit) = opval; + TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval); + } + +#undef OPRND +#undef FLD +} + NEXT (vpc); + +CASE (sem, INSN_WRITE_PCMPBZ) : /* pcmpbz $src2 */ + { + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; +#define FLD(f) abuf->fields.sfmt_st_plus.f +#define OPRND(f) par_exec->operands.sfmt_cmpz.f + int UNUSED written = abuf->written; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + CPU (h_cond) = OPRND (condbit); + +#undef OPRND +#undef FLD + } + NEXT (vpc); + + CASE (sem, INSN_PAR_SADD) : /* sadd */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f +#define OPRND(f) par_exec->operands.sfmt_sadd.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + DI opval = ADDDI (SRADI (GET_H_ACCUMS (((UINT) 1)), 16), GET_H_ACCUMS (((UINT) 0))); + OPRND (h_accums_DI_0) = opval; + TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval); + } + +#undef OPRND +#undef FLD +} + NEXT (vpc); + +CASE (sem, INSN_WRITE_SADD) : /* sadd */ + { + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; +#define FLD(f) abuf->fields.fmt_empty.f +#define OPRND(f) par_exec->operands.sfmt_sadd.f + int UNUSED written = abuf->written; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + SET_H_ACCUMS (((UINT) 0), OPRND (h_accums_DI_0)); + +#undef OPRND +#undef FLD + } + NEXT (vpc); + + CASE (sem, INSN_PAR_MACWU1) : /* macwu1 $src1,$src2 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_st_plus.f +#define OPRND(f) par_exec->operands.sfmt_macwu1.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUMS (((UINT) 1)), MULDI (EXTSIDI (* FLD (i_src1)), EXTSIDI (ANDSI (* FLD (i_src2), 65535)))), 8), 8); + OPRND (h_accums_DI_1) = opval; + TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval); + } + +#undef OPRND +#undef FLD +} + NEXT (vpc); + +CASE (sem, INSN_WRITE_MACWU1) : /* macwu1 $src1,$src2 */ + { + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; +#define FLD(f) abuf->fields.sfmt_st_plus.f +#define OPRND(f) par_exec->operands.sfmt_macwu1.f + int UNUSED written = abuf->written; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + SET_H_ACCUMS (((UINT) 1), OPRND (h_accums_DI_1)); + +#undef OPRND +#undef FLD + } + NEXT (vpc); + + CASE (sem, INSN_PAR_MSBLO) : /* msblo $src1,$src2 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_st_plus.f +#define OPRND(f) par_exec->operands.sfmt_msblo.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + DI opval = SRADI (SLLDI (SUBDI (GET_H_ACCUM (), SRADI (SLLDI (MULDI (EXTHIDI (TRUNCSIHI (* FLD (i_src1))), EXTHIDI (TRUNCSIHI (* FLD (i_src2)))), 32), 16)), 8), 8); + OPRND (accum) = opval; + TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval); + } + +#undef OPRND +#undef FLD +} + NEXT (vpc); + +CASE (sem, INSN_WRITE_MSBLO) : /* msblo $src1,$src2 */ + { + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; +#define FLD(f) abuf->fields.sfmt_st_plus.f +#define OPRND(f) par_exec->operands.sfmt_msblo.f + int UNUSED written = abuf->written; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + SET_H_ACCUM (OPRND (accum)); + +#undef OPRND +#undef FLD + } + NEXT (vpc); + + CASE (sem, INSN_PAR_MULWU1) : /* mulwu1 $src1,$src2 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_st_plus.f +#define OPRND(f) par_exec->operands.sfmt_mulwu1.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + DI opval = SRADI (SLLDI (MULDI (EXTSIDI (* FLD (i_src1)), EXTSIDI (ANDSI (* FLD (i_src2), 65535))), 16), 16); + OPRND (h_accums_DI_1) = opval; + TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval); + } + +#undef OPRND +#undef FLD +} + NEXT (vpc); + +CASE (sem, INSN_WRITE_MULWU1) : /* mulwu1 $src1,$src2 */ + { + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; +#define FLD(f) abuf->fields.sfmt_st_plus.f +#define OPRND(f) par_exec->operands.sfmt_mulwu1.f + int UNUSED written = abuf->written; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + SET_H_ACCUMS (((UINT) 1), OPRND (h_accums_DI_1)); + +#undef OPRND +#undef FLD + } + NEXT (vpc); + + CASE (sem, INSN_PAR_MACLH1) : /* maclh1 $src1,$src2 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_st_plus.f +#define OPRND(f) par_exec->operands.sfmt_macwu1.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUMS (((UINT) 1)), SLLDI (EXTSIDI (MULSI (EXTHISI (TRUNCSIHI (* FLD (i_src1))), SRASI (* FLD (i_src2), 16))), 16)), 8), 8); + OPRND (h_accums_DI_1) = opval; + TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval); + } + +#undef OPRND +#undef FLD +} + NEXT (vpc); + +CASE (sem, INSN_WRITE_MACLH1) : /* maclh1 $src1,$src2 */ + { + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; +#define FLD(f) abuf->fields.sfmt_st_plus.f +#define OPRND(f) par_exec->operands.sfmt_macwu1.f + int UNUSED written = abuf->written; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + SET_H_ACCUMS (((UINT) 1), OPRND (h_accums_DI_1)); + +#undef OPRND +#undef FLD + } + NEXT (vpc); + + CASE (sem, INSN_PAR_SC) : /* sc */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f +#define OPRND(f) par_exec->operands.sfmt_sc.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + +if (ZEXTBISI (CPU (h_cond))) + SEM_SKIP_INSN (current_cpu, sem_arg, vpc); + +#undef OPRND +#undef FLD +} + NEXT (vpc); + +CASE (sem, INSN_WRITE_SC) : /* sc */ + { + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; +#define FLD(f) abuf->fields.fmt_empty.f +#define OPRND(f) par_exec->operands.sfmt_sc.f + int UNUSED written = abuf->written; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + +#undef OPRND +#undef FLD + } + NEXT (vpc); + + CASE (sem, INSN_PAR_SNC) : /* snc */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f +#define OPRND(f) par_exec->operands.sfmt_sc.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + +if (ZEXTBISI (NOTBI (CPU (h_cond)))) + SEM_SKIP_INSN (current_cpu, sem_arg, vpc); + +#undef OPRND +#undef FLD +} + NEXT (vpc); + +CASE (sem, INSN_WRITE_SNC) : /* snc */ + { + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; +#define FLD(f) abuf->fields.fmt_empty.f +#define OPRND(f) par_exec->operands.sfmt_sc.f + int UNUSED written = abuf->written; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + +#undef OPRND +#undef FLD + } + NEXT (vpc); + + CASE (sem, INSN_PAR_CLRPSW) : /* clrpsw $uimm8 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_clrpsw.f +#define OPRND(f) par_exec->operands.sfmt_clrpsw.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + SI opval = ANDSI (GET_H_CR (((UINT) 0)), ORSI (INVBI (FLD (f_uimm8)), 65280)); + OPRND (h_cr_USI_0) = opval; + TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval); + } + +#undef OPRND +#undef FLD +} + NEXT (vpc); + +CASE (sem, INSN_WRITE_CLRPSW) : /* clrpsw $uimm8 */ + { + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; +#define FLD(f) abuf->fields.sfmt_clrpsw.f +#define OPRND(f) par_exec->operands.sfmt_clrpsw.f + int UNUSED written = abuf->written; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + SET_H_CR (((UINT) 0), OPRND (h_cr_USI_0)); + +#undef OPRND +#undef FLD + } + NEXT (vpc); + + CASE (sem, INSN_PAR_SETPSW) : /* setpsw $uimm8 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_clrpsw.f +#define OPRND(f) par_exec->operands.sfmt_setpsw.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + SI opval = FLD (f_uimm8); + OPRND (h_cr_USI_0) = opval; + TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval); + } + +#undef OPRND +#undef FLD +} + NEXT (vpc); + +CASE (sem, INSN_WRITE_SETPSW) : /* setpsw $uimm8 */ + { + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; +#define FLD(f) abuf->fields.sfmt_clrpsw.f +#define OPRND(f) par_exec->operands.sfmt_setpsw.f + int UNUSED written = abuf->written; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + SET_H_CR (((UINT) 0), OPRND (h_cr_USI_0)); + +#undef OPRND +#undef FLD + } + NEXT (vpc); + + CASE (sem, INSN_PAR_BTST) : /* btst $uimm3,$sr */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_bset.f +#define OPRND(f) par_exec->operands.sfmt_btst.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + BI opval = ANDQI (SRLSI (* FLD (i_sr), SUBSI (7, FLD (f_uimm3))), 1); + OPRND (condbit) = opval; + TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval); + } + +#undef OPRND +#undef FLD +} + NEXT (vpc); + +CASE (sem, INSN_WRITE_BTST) : /* btst $uimm3,$sr */ + { + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; +#define FLD(f) abuf->fields.sfmt_bset.f +#define OPRND(f) par_exec->operands.sfmt_btst.f + int UNUSED written = abuf->written; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + CPU (h_cond) = OPRND (condbit); + +#undef OPRND +#undef FLD + } + NEXT (vpc); + + + } + ENDSWITCH (sem) /* End of semantic switch. */ + + /* At this point `vpc' contains the next insn to execute. */ +} + +#undef DEFINE_SWITCH +#endif /* DEFINE_SWITCH */ diff --git a/sim/ppc/altivec.igen b/sim/ppc/altivec.igen new file mode 100644 index 0000000..9f10b26 --- /dev/null +++ b/sim/ppc/altivec.igen @@ -0,0 +1,2356 @@ +# Altivec instruction set, for PSIM, the PowerPC simulator. + +# Copyright 2003 Free Software Foundation, Inc. + +# Contributed by Red Hat Inc; developed under contract from Motorola. +# Written by matthew green . + +# This file is part of GDB. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. + +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. + +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, +# Boston, MA 02111-1307, USA. */ + + +# +# Motorola AltiVec instructions. +# + +:cache:av:::VS:VS: +:cache:av::vreg *:vS:VS:(cpu_registers(processor)->altivec.vr + VS) +:cache:av::unsigned32:VS_BITMASK:VS:(1 << VS) +:cache:av:::VA:VA: +:cache:av::vreg *:vA:VA:(cpu_registers(processor)->altivec.vr + VA) +:cache:av::unsigned32:VA_BITMASK:VA:(1 << VA) +:cache:av:::VB:VB: +:cache:av::vreg *:vB:VB:(cpu_registers(processor)->altivec.vr + VB) +:cache:av::unsigned32:VB_BITMASK:VB:(1 << VB) +:cache:av:::VC:VC: +:cache:av::vreg *:vC:VC:(cpu_registers(processor)->altivec.vr + VC) +:cache:av::unsigned32:VC_BITMASK:VC:(1 << VC) + +# Flags for model.h +::model-macro::: + #define PPC_INSN_INT_VR(OUT_MASK, IN_MASK, OUT_VMASK, IN_VMASK) \ + do { \ + if (CURRENT_MODEL_ISSUE > 0) \ + ppc_insn_int_vr(MY_INDEX, cpu_model(processor), OUT_MASK, IN_MASK, OUT_VMASK, IN_VMASK); \ + } while (0) + + #define PPC_INSN_VR(OUT_VMASK, IN_VMASK) \ + do { \ + if (CURRENT_MODEL_ISSUE > 0) \ + ppc_insn_vr(MY_INDEX, cpu_model(processor), OUT_VMASK, IN_VMASK); \ + } while (0) + + #define PPC_INSN_VR_CR(OUT_VMASK, IN_VMASK, CR_MASK) \ + do { \ + if (CURRENT_MODEL_ISSUE > 0) \ + ppc_insn_vr_cr(MY_INDEX, cpu_model(processor), OUT_VMASK, IN_VMASK, CR_MASK); \ + } while (0) + + #define PPC_INSN_VR_VSCR(OUT_VMASK, IN_VMASK) \ + do { \ + if (CURRENT_MODEL_ISSUE > 0) \ + ppc_insn_vr_vscr(MY_INDEX, cpu_model(processor), OUT_VMASK, IN_VMASK); \ + } while (0) + + #define PPC_INSN_FROM_VSCR(VR_MASK) \ + do { \ + if (CURRENT_MODEL_ISSUE > 0) \ + ppc_insn_from_vscr(MY_INDEX, cpu_model(processor), VR_MASK); \ + } while (0) + + #define PPC_INSN_TO_VSCR(VR_MASK) \ + do { \ + if (CURRENT_MODEL_ISSUE > 0) \ + ppc_insn_to_vscr(MY_INDEX, cpu_model(processor), VR_MASK); \ + } while (0) + +# Trace waiting for AltiVec registers to become available +void::model-static::model_trace_altivec_busy_p:model_data *model_ptr, unsigned32 vr_busy + int i; + if (vr_busy) { + vr_busy &= model_ptr->vr_busy; + for(i = 0; i < 32; i++) { + if (((1 << i) & vr_busy) != 0) { + TRACE(trace_model, ("Waiting for register v%d.\n", i)); + } + } + } + if (model_ptr->vscr_busy) + TRACE(trace_model, ("Waiting for VSCR\n")); + +# Trace making AltiVec registers busy +void::model-static::model_trace_altivec_make_busy:model_data *model_ptr, unsigned32 vr_mask, unsigned32 cr_mask + int i; + if (vr_mask) { + for(i = 0; i < 32; i++) { + if (((1 << i) & vr_mask) != 0) { + TRACE(trace_model, ("Register v%d is now busy.\n", i)); + } + } + } + if (cr_mask) { + for(i = 0; i < 8; i++) { + if (((1 << i) & cr_mask) != 0) { + TRACE(trace_model, ("Register cr%d is now busy.\n", i)); + } + } + } + +# Schedule an AltiVec instruction that takes integer input registers and produces output registers +void::model-function::ppc_insn_int_vr:itable_index index, model_data *model_ptr, const unsigned32 out_mask, const unsigned32 in_mask, const unsigned32 out_vmask, const unsigned32 in_vmask + const unsigned32 int_mask = out_mask | in_mask; + const unsigned32 vr_mask = out_vmask | in_vmask; + model_busy *busy_ptr; + + if ((model_ptr->int_busy & int_mask) != 0 || (model_ptr->vr_busy & vr_mask)) { + model_new_cycle(model_ptr); /* don't count first dependency as a stall */ + + while ((model_ptr->int_busy & int_mask) != 0 || (model_ptr->vr_busy & vr_mask)) { + if (WITH_TRACE && ppc_trace[trace_model]) { + model_trace_busy_p(model_ptr, int_mask, 0, 0, PPC_NO_SPR); + model_trace_altivec_busy_p(model_ptr, vr_mask); + } + + model_ptr->nr_stalls_data++; + model_new_cycle(model_ptr); + } + } + + busy_ptr = model_wait_for_unit(index, model_ptr, &model_ptr->timing[index]); + model_ptr->int_busy |= out_mask; + busy_ptr->int_busy |= out_mask; + model_ptr->vr_busy |= out_vmask; + busy_ptr->vr_busy |= out_vmask; + + if (out_mask) + busy_ptr->nr_writebacks = (PPC_ONE_BIT_SET_P(out_vmask)) ? 1 : 2; + + if (out_vmask) + busy_ptr->nr_writebacks += (PPC_ONE_BIT_SET_P(out_vmask)) ? 1 : 2; + + if (WITH_TRACE && ppc_trace[trace_model]) { + model_trace_make_busy(model_ptr, out_mask, 0, 0); + model_trace_altivec_make_busy(model_ptr, vr_mask, 0); + } + +# Schedule an AltiVec instruction that takes vector input registers and produces vector output registers +void::model-function::ppc_insn_vr:itable_index index, model_data *model_ptr, const unsigned32 out_vmask, const unsigned32 in_vmask + const unsigned32 vr_mask = out_vmask | in_vmask; + model_busy *busy_ptr; + + if (model_ptr->vr_busy & vr_mask) { + model_new_cycle(model_ptr); /* don't count first dependency as a stall */ + + while (model_ptr->vr_busy & vr_mask) { + if (WITH_TRACE && ppc_trace[trace_model]) { + model_trace_altivec_busy_p(model_ptr, vr_mask); + } + + model_ptr->nr_stalls_data++; + model_new_cycle(model_ptr); + } + } + + busy_ptr = model_wait_for_unit(index, model_ptr, &model_ptr->timing[index]); + model_ptr->vr_busy |= out_vmask; + busy_ptr->vr_busy |= out_vmask; + if (out_vmask) + busy_ptr->nr_writebacks = (PPC_ONE_BIT_SET_P(out_vmask)) ? 1 : 2; + + if (WITH_TRACE && ppc_trace[trace_model]) { + model_trace_altivec_make_busy(model_ptr, vr_mask, 0); + } + +# Schedule an AltiVec instruction that takes vector input registers and produces vector output registers, touches CR +void::model-function::ppc_insn_vr_cr:itable_index index, model_data *model_ptr, const unsigned32 out_vmask, const unsigned32 in_vmask, const unsigned32 cr_mask + const unsigned32 vr_mask = out_vmask | in_vmask; + model_busy *busy_ptr; + + if ((model_ptr->vr_busy & vr_mask) || (model_ptr->cr_fpscr_busy & cr_mask)) { + model_new_cycle(model_ptr); /* don't count first dependency as a stall */ + + while ((model_ptr->vr_busy & vr_mask) || (model_ptr->cr_fpscr_busy & cr_mask)) { + if (WITH_TRACE && ppc_trace[trace_model]) { + model_trace_busy_p(model_ptr, 0, 0, cr_mask, PPC_NO_SPR); + model_trace_altivec_busy_p(model_ptr, vr_mask); + } + + model_ptr->nr_stalls_data++; + model_new_cycle(model_ptr); + } + } + + busy_ptr = model_wait_for_unit(index, model_ptr, &model_ptr->timing[index]); + model_ptr->cr_fpscr_busy |= cr_mask; + busy_ptr->cr_fpscr_busy |= cr_mask; + model_ptr->vr_busy |= out_vmask; + busy_ptr->vr_busy |= out_vmask; + + if (out_vmask) + busy_ptr->nr_writebacks = (PPC_ONE_BIT_SET_P(out_vmask)) ? 1 : 2; + + if (cr_mask) + busy_ptr->nr_writebacks++; + + if (WITH_TRACE && ppc_trace[trace_model]) + model_trace_altivec_make_busy(model_ptr, vr_mask, cr_mask); + +# Schedule an AltiVec instruction that takes vector input registers and produces vector output registers, touches VSCR +void::model-function::ppc_insn_vr_vscr:itable_index index, model_data *model_ptr, const unsigned32 out_vmask, const unsigned32 in_vmask + const unsigned32 vr_mask = out_vmask | in_vmask; + model_busy *busy_ptr; + + if ((model_ptr->vr_busy & vr_mask) != 0 || model_ptr->vscr_busy != 0) { + model_new_cycle(model_ptr); /* don't count first dependency as a stall */ + + while ((model_ptr->vr_busy & vr_mask) != 0 || model_ptr->vscr_busy != 0) { + if (WITH_TRACE && ppc_trace[trace_model]) + model_trace_altivec_busy_p(model_ptr, vr_mask); + + model_ptr->nr_stalls_data++; + model_new_cycle(model_ptr); + } + } + + busy_ptr = model_wait_for_unit(index, model_ptr, &model_ptr->timing[index]); + model_ptr->vr_busy |= out_vmask; + busy_ptr->vr_busy |= out_vmask; + model_ptr->vscr_busy = 1; + busy_ptr->vscr_busy = 1; + + if (out_vmask) + busy_ptr->nr_writebacks = 1 + (PPC_ONE_BIT_SET_P(out_vmask)) ? 1 : 2; + + if (WITH_TRACE && ppc_trace[trace_model]) + model_trace_altivec_make_busy(model_ptr, vr_mask, 0); + +# Schedule an MFVSCR instruction that VSCR input register and produces an AltiVec output register +void::model-function::ppc_insn_from_vscr:itable_index index, model_data *model_ptr, const unsigned32 vr_mask + model_busy *busy_ptr; + + while ((model_ptr->vr_busy & vr_mask) != 0 || model_ptr->vscr_busy != 0) { + if (WITH_TRACE && ppc_trace[trace_model]) + model_trace_altivec_busy_p(model_ptr, vr_mask); + + model_ptr->nr_stalls_data++; + model_new_cycle(model_ptr); + } + busy_ptr = model_wait_for_unit(index, model_ptr, &model_ptr->timing[index]); + model_ptr->cr_fpscr_busy |= vr_mask; + busy_ptr->cr_fpscr_busy |= vr_mask; + + if (vr_mask) + busy_ptr->nr_writebacks = 1; + + model_ptr->vr_busy |= vr_mask; + if (WITH_TRACE && ppc_trace[trace_model]) + model_trace_altivec_make_busy(model_ptr, vr_mask, 0); + +# Schedule an MTVSCR instruction that one AltiVec input register and produces a vscr output register +void::model-function::ppc_insn_to_vscr:itable_index index, model_data *model_ptr, const unsigned32 vr_mask + model_busy *busy_ptr; + + while ((model_ptr->vr_busy & vr_mask) != 0 || model_ptr->vscr_busy != 0) { + if (WITH_TRACE && ppc_trace[trace_model]) + model_trace_altivec_busy_p(model_ptr, vr_mask); + + model_ptr->nr_stalls_data++; + model_new_cycle(model_ptr); + } + busy_ptr = model_wait_for_unit(index, model_ptr, &model_ptr->timing[index]); + busy_ptr ->vscr_busy = 1; + model_ptr->vscr_busy = 1; + busy_ptr->nr_writebacks = 1; + + TRACE(trace_model,("Making VSCR busy.\n")); + +# The follow are AltiVec saturate operations + +signed8::model-function::altivec_signed_saturate_8:signed16 val, int *sat + signed8 rv; + if (val > 127) { + rv = 127; + *sat = 1; + } else if (val < -128) { + rv = -128; + *sat = 1; + } else { + rv = val; + *sat = 0; + } + return rv; + +signed16::model-function::altivec_signed_saturate_16:signed32 val, int *sat + signed16 rv; + if (val > 32767) { + rv = 32767; + *sat = 1; + } else if (val < -32768) { + rv = -32768; + *sat = 1; + } else { + rv = val; + *sat = 0; + } + return rv; + +signed32::model-function::altivec_signed_saturate_32:signed64 val, int *sat + signed32 rv; + if (val > 2147483647) { + rv = 2147483647; + *sat = 1; + } else if (val < -2147483648LL) { + rv = -2147483648LL; + *sat = 1; + } else { + rv = val; + *sat = 0; + } + return rv; + +unsigned8::model-function::altivec_unsigned_saturate_8:signed16 val, int *sat + unsigned8 rv; + if (val > 255) { + rv = 255; + *sat = 1; + } else if (val < 0) { + rv = 0; + *sat = 1; + } else { + rv = val; + *sat = 0; + } + return rv; + +unsigned16::model-function::altivec_unsigned_saturate_16:signed32 val, int *sat + unsigned16 rv; + if (val > 65535) { + rv = 65535; + *sat = 1; + } else if (val < 0) { + rv = 0; + *sat = 1; + } else { + rv = val; + *sat = 0; + } + return rv; + +unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat + unsigned32 rv; + if (val > 4294967295LL) { + rv = 4294967295LL; + *sat = 1; + } else if (val < 0) { + rv = 0; + *sat = 1; + } else { + rv = val; + *sat = 0; + } + return rv; + +# +# Load instructions, 6-14 ... 6-22. +# + +0.31,6.VS,11.RA,16.RB,21.7,31.0:X:av:lvebx %VD, %RA, %RB:Load Vector Element Byte Indexed + unsigned_word b; + unsigned_word EA; + unsigned_word eb; + if (RA_is_0) b = 0; + else b = *rA; + EA = b + *rB; + eb = EA & 0xf; + (*vS).b[AV_BINDEX(eb)] = MEM(unsigned, EA, 1); + PPC_INSN_INT_VR(0, RA_BITMASK | RB_BITMASK, VS_BITMASK, 0); + +0.31,6.VS,11.RA,16.RB,21.39,31.0:X:av:lvehx %VD, %RA, %RB:Load Vector Element Half Word Indexed + unsigned_word b; + unsigned_word EA; + unsigned_word eb; + if (RA_is_0) b = 0; + else b = *rA; + EA = (b + *rB) & ~1; + eb = EA & 0xf; + (*vS).h[AV_HINDEX(eb/2)] = MEM(unsigned, EA, 2); + PPC_INSN_INT_VR(0, RA_BITMASK | RB_BITMASK, VS_BITMASK, 0); + +0.31,6.VS,11.RA,16.RB,21.71,31.0:X:av:lvewx %VD, %RA, %RB:Load Vector Element Word Indexed + unsigned_word b; + unsigned_word EA; + unsigned_word eb; + if (RA_is_0) b = 0; + else b = *rA; + EA = (b + *rB) & ~3; + eb = EA & 0xf; + (*vS).w[eb/4] = MEM(unsigned, EA, 4); + PPC_INSN_INT_VR(0, RA_BITMASK | RB_BITMASK, VS_BITMASK, 0); + + +0.31,6.VS,11.RA,16.RB,21.6,31.0:X:av:lvsl %VD, %RA, %RB:Load Vector for Shift Left + unsigned_word b; + unsigned_word addr; + int i, j; + if (RA_is_0) b = 0; + else b = *rA; + addr = b + *rB; + j = addr & 0xf; + for (i = 0; i < 16; i++) + if (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN) + (*vS).b[AV_BINDEX(i)] = j++; + else + (*vS).b[AV_BINDEX(15 - i)] = j++; + PPC_INSN_INT_VR(0, RA_BITMASK | RB_BITMASK, VS_BITMASK, 0); + +0.31,6.VS,11.RA,16.RB,21.38,31.0:X:av:lvsr %VD, %RA, %RB:Load Vector for Shift Right + unsigned_word b; + unsigned_word addr; + int i, j; + if (RA_is_0) b = 0; + else b = *rA; + addr = b + *rB; + j = 0x10 - (addr & 0xf); + for (i = 0; i < 16; i++) + if (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN) + (*vS).b[AV_BINDEX(i)] = j++; + else + (*vS).b[AV_BINDEX(15 - i)] = j++; + PPC_INSN_INT_VR(0, RA_BITMASK | RB_BITMASK, VS_BITMASK, 0); + + +0.31,6.VS,11.RA,16.RB,21.103,31.0:X:av:lvx %VD, %RA, %RB:Load Vector Indexed + unsigned_word b; + unsigned_word EA; + if (RA_is_0) b = 0; + else b = *rA; + EA = (b + *rB) & ~0xf; + if (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN) { + (*vS).w[0] = MEM(unsigned, EA + 0, 4); + (*vS).w[1] = MEM(unsigned, EA + 4, 4); + (*vS).w[2] = MEM(unsigned, EA + 8, 4); + (*vS).w[3] = MEM(unsigned, EA + 12, 4); + } else { + (*vS).w[0] = MEM(unsigned, EA + 12, 4); + (*vS).w[1] = MEM(unsigned, EA + 8, 4); + (*vS).w[2] = MEM(unsigned, EA + 4, 4); + (*vS).w[3] = MEM(unsigned, EA + 0, 4); + } + PPC_INSN_INT_VR(0, RA_BITMASK | RB_BITMASK, VS_BITMASK, 0); + +0.31,6.VS,11.RA,16.RB,21.359,31.0:X:av:lvxl %VD, %RA, %RB:Load Vector Indexed LRU + unsigned_word b; + unsigned_word EA; + if (RA_is_0) b = 0; + else b = *rA; + EA = (b + *rB) & ~0xf; + if (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN) { + (*vS).w[0] = MEM(unsigned, EA + 0, 4); + (*vS).w[1] = MEM(unsigned, EA + 4, 4); + (*vS).w[2] = MEM(unsigned, EA + 8, 4); + (*vS).w[3] = MEM(unsigned, EA + 12, 4); + } else { + (*vS).w[0] = MEM(unsigned, EA + 12, 4); + (*vS).w[1] = MEM(unsigned, EA + 8, 4); + (*vS).w[2] = MEM(unsigned, EA + 4, 4); + (*vS).w[3] = MEM(unsigned, EA + 0, 4); + } + PPC_INSN_INT_VR(0, RA_BITMASK | RB_BITMASK, VS_BITMASK, 0); + +# +# Move to/from VSCR instructions, 6-23 & 6-24. +# + +0.4,6.VS,11.0,16.0,21.1540:VX:av:mfvscr %VS:Move from Vector Status and Control Register + (*vS).w[0] = 0; + (*vS).w[1] = 0; + (*vS).w[2] = 0; + (*vS).w[3] = VSCR; + PPC_INSN_FROM_VSCR(VS_BITMASK); + +0.4,6.0,11.0,16.VB,21.1604:VX:av:mtvscr %VB:Move to Vector Status and Control Register + VSCR = (*vB).w[3]; + PPC_INSN_TO_VSCR(VB_BITMASK); + +# +# Store instructions, 6-25 ... 6-29. +# + +0.31,6.VS,11.RA,16.RB,21.135,31.0:X:av:stvebx %VD, %RA, %RB:Store Vector Element Byte Indexed + unsigned_word b; + unsigned_word EA; + unsigned_word eb; + if (RA_is_0) b = 0; + else b = *rA; + EA = b + *rB; + eb = EA & 0xf; + if (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN) + STORE(EA, 1, (*vS).b[eb]); + else + STORE(EA, 1, (*vS).b[15-eb]); + PPC_INSN_INT_VR(0, RA_BITMASK | RB_BITMASK, VS_BITMASK, 0); + +0.31,6.VS,11.RA,16.RB,21.167,31.0:X:av:stvehx %VD, %RA, %RB:Store Vector Element Half Word Indexed + unsigned_word b; + unsigned_word EA; + unsigned_word eb; + if (RA_is_0) b = 0; + else b = *rA; + EA = (b + *rB) & ~1; + eb = EA & 0xf; + if (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN) + STORE(EA, 2, (*vS).h[eb/2]); + else + STORE(EA, 2, (*vS).h[7-eb]); + PPC_INSN_INT_VR(0, RA_BITMASK | RB_BITMASK, VS_BITMASK, 0); + +0.31,6.VS,11.RA,16.RB,21.199,31.0:X:av:stvewx %VD, %RA, %RB:Store Vector Element Word Indexed + unsigned_word b; + unsigned_word EA; + unsigned_word eb; + if (RA_is_0) b = 0; + else b = *rA; + EA = (b + *rB) & ~3; + eb = EA & 0xf; + if (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN) + STORE(EA, 4, (*vS).w[eb/4]); + else + STORE(EA, 4, (*vS).w[3-(eb/4)]); + PPC_INSN_INT_VR(0, RA_BITMASK | RB_BITMASK, VS_BITMASK, 0); + +0.31,6.VS,11.RA,16.RB,21.231,31.0:X:av:stvx %VD, %RA, %RB:Store Vector Indexed + unsigned_word b; + unsigned_word EA; + if (RA_is_0) b = 0; + else b = *rA; + EA = (b + *rB) & ~0xf; + if (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN) { + STORE(EA + 0, 4, (*vS).w[0]); + STORE(EA + 4, 4, (*vS).w[1]); + STORE(EA + 8, 4, (*vS).w[2]); + STORE(EA + 12, 4, (*vS).w[3]); + } else { + STORE(EA + 12, 4, (*vS).w[0]); + STORE(EA + 8, 4, (*vS).w[1]); + STORE(EA + 4, 4, (*vS).w[2]); + STORE(EA + 0, 4, (*vS).w[3]); + } + PPC_INSN_INT_VR(0, RA_BITMASK | RB_BITMASK, VS_BITMASK, 0); + +0.31,6.VS,11.RA,16.RB,21.487,31.0:X:av:stvxl %VD, %RA, %RB:Store Vector Indexed LRU + unsigned_word b; + unsigned_word EA; + if (RA_is_0) b = 0; + else b = *rA; + EA = (b + *rB) & ~0xf; + if (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN) { + STORE(EA + 0, 4, (*vS).w[0]); + STORE(EA + 4, 4, (*vS).w[1]); + STORE(EA + 8, 4, (*vS).w[2]); + STORE(EA + 12, 4, (*vS).w[3]); + } else { + STORE(EA + 12, 4, (*vS).w[0]); + STORE(EA + 8, 4, (*vS).w[1]); + STORE(EA + 4, 4, (*vS).w[2]); + STORE(EA + 0, 4, (*vS).w[3]); + } + PPC_INSN_INT_VR(0, RA_BITMASK | RB_BITMASK, VS_BITMASK, 0); + +# +# Vector Add instructions, 6-30 ... 6-40. +# + +0.4,6.VS,11.VA,16.VB,21.384:VX:av:vaddcuw %VD, %VA, %VB:Vector Add Carryout Unsigned Word + unsigned64 temp; + int i; + for (i = 0; i < 4; i++) { + temp = (unsigned64)(*vA).w[i] + (unsigned64)(*vB).w[i]; + (*vS).w[i] = temp >> 32; + } + PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); + +0.4,6.VS,11.VA,16.VB,21.10:VX:av:vaddfp %VD, %VA, %VB:Vector Add Floating Point + int i; + unsigned32 f; + sim_fpu a, b, d; + for (i = 0; i < 4; i++) { + sim_fpu_32to (&a, (*vA).w[i]); + sim_fpu_32to (&b, (*vB).w[i]); + sim_fpu_add (&d, &a, &b); + sim_fpu_to32 (&f, &d); + (*vS).w[i] = f; + } + PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); + +0.4,6.VS,11.VA,16.VB,21.768:VX:av:vaddsbs %VD, %VA, %VB:Vector Add Signed Byte Saturate + int i, sat, tempsat; + signed16 temp; + for (i = 0; i < 16; i++) { + temp = (signed16)(signed8)(*vA).b[i] + (signed16)(signed8)(*vB).b[i]; + (*vS).b[i] = altivec_signed_saturate_8(temp, &tempsat); + sat |= tempsat; + } + ALTIVEC_SET_SAT(sat); + PPC_INSN_VR_VSCR(VS_BITMASK, VA_BITMASK | VB_BITMASK); + +0.4,6.VS,11.VA,16.VB,21.832:VX:av:vaddshs %VD, %VA, %VB:Vector Add Signed Half Word Saturate + int i, sat, tempsat; + signed32 temp, a, b; + for (i = 0; i < 8; i++) { + a = (signed32)(signed16)(*vA).h[i]; + b = (signed32)(signed16)(*vB).h[i]; + temp = a + b; + (*vS).h[i] = altivec_signed_saturate_16(temp, &tempsat); + sat |= tempsat; + } + ALTIVEC_SET_SAT(sat); + PPC_INSN_VR_VSCR(VS_BITMASK, VA_BITMASK | VB_BITMASK); + +0.4,6.VS,11.VA,16.VB,21.896:VX:av:vaddsws %VD, %VA, %VB:Vector Add Signed Word Saturate + int i, sat, tempsat; + signed64 temp; + for (i = 0; i < 4; i++) { + temp = (signed64)(signed32)(*vA).w[i] + (signed64)(signed32)(*vB).w[i]; + (*vS).w[i] = altivec_signed_saturate_32(temp, &tempsat); + sat |= tempsat; + } + ALTIVEC_SET_SAT(sat); + PPC_INSN_VR_VSCR(VS_BITMASK, VA_BITMASK | VB_BITMASK); + +0.4,6.VS,11.VA,16.VB,21.0:VX:av:vaddubm %VD, %VA, %VB:Vector Add Unsigned Byte Modulo + int i; + for (i = 0; i < 16; i++) + (*vS).b[i] = ((*vA).b[i] + (*vB).b[i]) & 0xff; + PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); + +0.4,6.VS,11.VA,16.VB,21.512:VX:av:vaddubs %VD, %VA, %VB:Vector Add Unsigned Byte Saturate + int i, sat, tempsat; + signed16 temp; + sat = 0; + for (i = 0; i < 16; i++) { + temp = (signed16)(unsigned8)(*vA).b[i] + (signed16)(unsigned8)(*vB).b[i]; + (*vS).b[i] = altivec_unsigned_saturate_8(temp, &tempsat); + sat |= tempsat; + } + ALTIVEC_SET_SAT(sat); + PPC_INSN_VR_VSCR(VS_BITMASK, VA_BITMASK | VB_BITMASK); + +0.4,6.VS,11.VA,16.VB,21.64:VX:av:vadduhm %VD, %VA, %VB:Vector Add Unsigned Half Word Modulo + int i; + for (i = 0; i < 8; i++) + (*vS).h[i] = ((*vA).h[i] + (*vB).h[i]) & 0xffff; + PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); + +0.4,6.VS,11.VA,16.VB,21.576:VX:av:vadduhs %VD, %VA, %VB:Vector Add Unsigned Half Word Saturate + int i, sat, tempsat; + signed32 temp; + for (i = 0; i < 8; i++) { + temp = (signed32)(unsigned16)(*vA).h[i] + (signed32)(unsigned16)(*vB).h[i]; + (*vS).h[i] = altivec_unsigned_saturate_16(temp, &tempsat); + sat |= tempsat; + } + ALTIVEC_SET_SAT(sat); + PPC_INSN_VR_VSCR(VS_BITMASK, VA_BITMASK | VB_BITMASK); + +0.4,6.VS,11.VA,16.VB,21.128:VX:av:vadduwm %VD, %VA, %VB:Vector Add Unsigned Word Modulo + int i; + for (i = 0; i < 4; i++) + (*vS).w[i] = (*vA).w[i] + (*vB).w[i]; + PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); + +0.4,6.VS,11.VA,16.VB,21.640:VX:av:vadduws %VD, %VA, %VB:Vector Add Unsigned Word Saturate + int i, sat, tempsat; + signed64 temp; + for (i = 0; i < 4; i++) { + temp = (signed64)(unsigned32)(*vA).w[i] + (signed64)(unsigned32)(*vB).w[i]; + (*vS).w[i] = altivec_unsigned_saturate_32(temp, &tempsat); + sat |= tempsat; + } + ALTIVEC_SET_SAT(sat); + PPC_INSN_VR_VSCR(VS_BITMASK, VA_BITMASK | VB_BITMASK); + +# +# Vector AND instructions, 6-41, 6-42 +# + +0.4,6.VS,11.VA,16.VB,21.1028:VX:av:vand %VD, %VA, %VB:Vector Logical AND + int i; + for (i = 0; i < 4; i++) + (*vS).w[i] = (*vA).w[i] & (*vB).w[i]; + PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); + +0.4,6.VS,11.VA,16.VB,21.1092:VX:av:vandc %VD, %VA, %VB:Vector Logical AND with Compliment + int i; + for (i = 0; i < 4; i++) + (*vS).w[i] = (*vA).w[i] & ~((*vB).w[i]); + PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); + + +# +# Vector Average instructions, 6-43, 6-48 +# + +0.4,6.VS,11.VA,16.VB,21.1282:VX:av:vavgsb %VD, %VA, %VB:Vector Average Signed Byte + int i; + signed16 temp, a, b; + for (i = 0; i < 16; i++) { + a = (signed16)(signed8)(*vA).b[i]; + b = (signed16)(signed8)(*vB).b[i]; + temp = a + b + 1; + (*vS).b[i] = (temp >> 1) & 0xff; + } + PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); + +0.4,6.VS,11.VA,16.VB,21.1346:VX:av:vavgsh %VD, %VA, %VB:Vector Average Signed Half Word + int i; + signed32 temp, a, b; + for (i = 0; i < 8; i++) { + a = (signed32)(signed16)(*vA).h[i]; + b = (signed32)(signed16)(*vB).h[i]; + temp = a + b + 1; + (*vS).h[i] = (temp >> 1) & 0xffff; + } + PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); + +0.4,6.VS,11.VA,16.VB,21.1410:VX:av:vavgsw %VD, %VA, %VB:Vector Average Signed Word + int i; + signed64 temp, a, b; + for (i = 0; i < 4; i++) { + a = (signed64)(signed32)(*vA).w[i]; + b = (signed64)(signed32)(*vB).w[i]; + temp = a + b + 1; + (*vS).w[i] = (temp >> 1) & 0xffffffff; + } + PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); + +0.4,6.VS,11.VA,16.VB,21.1026:VX:av:vavgub %VD, %VA, %VB:Vector Average Unsigned Byte + int i; + unsigned16 temp, a, b; + for (i = 0; i < 16; i++) { + a = (*vA).b[i]; + b = (*vB).b[i]; + temp = a + b + 1; + (*vS).b[i] = (temp >> 1) & 0xff; + } + PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); + +0.4,6.VS,11.VA,16.VB,21.1090:VX:av:vavguh %VD, %VA, %VB:Vector Average Unsigned Half Word + int i; + unsigned32 temp, a, b; + for (i = 0; i < 8; i++) { + a = (*vA).h[i]; + b = (*vB).h[i]; + temp = a + b + 1; + (*vS).h[i] = (temp >> 1) & 0xffff; + } + PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); + +0.4,6.VS,11.VA,16.VB,21.1154:VX:av:vavguw %VD, %VA, %VB:Vector Average Unsigned Word + int i; + unsigned64 temp, a, b; + for (i = 0; i < 4; i++) { + a = (*vA).w[i]; + b = (*vB).w[i]; + temp = a + b + 1; + (*vS).w[i] = (temp >> 1) & 0xffffffff; + } + PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); + +# +# Vector Fixed Point Convert instructions, 6-49, 6-50 +# + +0.4,6.VS,11.UIMM,16.VB,21.842:VX:av:vcfsx %VD, %VB, %UIMM:Vector Convert From Signed Fixed-Point Word + int i; + unsigned32 f; + sim_fpu b, div, d; + for (i = 0; i < 4; i++) { + sim_fpu_32to (&b, (*vB).w[i]); + sim_fpu_u32to (&div, 2 << UIMM, sim_fpu_round_default); + sim_fpu_div (&d, &b, &div); + sim_fpu_to32 (&f, &d); + (*vS).w[i] = f; + } + PPC_INSN_VR(VS_BITMASK, VB_BITMASK); + +0.4,6.VS,11.UIMM,16.VB,21.778:VX:av:vcfux %VD, %VA, %UIMM:Vector Convert From Unsigned Fixed-Point Word + int i; + unsigned32 f; + sim_fpu b, d, div; + for (i = 0; i < 4; i++) { + sim_fpu_32to (&b, (*vB).w[i]); + sim_fpu_u32to (&div, 2 << UIMM, sim_fpu_round_default); + sim_fpu_div (&d, &b, &div); + sim_fpu_to32u (&f, &d, sim_fpu_round_default); + (*vS).w[i] = f; + } + PPC_INSN_VR(VS_BITMASK, VB_BITMASK); + +# +# Vector Compare instructions, 6-51 ... 6-64 +# + +0.4,6.VS,11.VA,16.VB,21.RC,22.966:VXR:av:vcmpbpfpx %VD, %VA, %VB:Vector Compare Bounds Floating Point + int i, le, ge; + sim_fpu a, b, d; + for (i = 0; i < 4; i++) { + sim_fpu_32to (&a, (*vA).w[i]); + sim_fpu_32to (&b, (*vB).w[i]); + le = sim_fpu_is_le(&a, &b); + ge = sim_fpu_is_ge(&a, &b); + (*vS).w[i] = (le ? 0 : 1 << 31) | (ge ? 0 : 1 << 30); + } + if (RC) + ALTIVEC_SET_CR6(vS, 0); + PPC_INSN_VR_CR(VS_BITMASK, VA_BITMASK | VB_BITMASK, RC ? 0x000000f0 : 0); + +0.4,6.VS,11.VA,16.VB,21.RC,22.198:VXR:av:vcmpeqfpx %VD, %VA, %VB:Vector Compare Equal-to-Floating Point + int i; + sim_fpu a, b; + for (i = 0; i < 4; i++) { + sim_fpu_32to (&a, (*vA).w[i]); + sim_fpu_32to (&b, (*vB).w[i]); + if (sim_fpu_is_eq(&a, &b)) + (*vS).w[i] = 0xffffffff; + else + (*vS).w[i] = 0; + } + if (RC) + ALTIVEC_SET_CR6(vS, 1); + PPC_INSN_VR_CR(VS_BITMASK, VA_BITMASK | VB_BITMASK, RC ? 0x000000f0 : 0); + +0.4,6.VS,11.VA,16.VB,21.RC,22.6:VXR:av:vcmpequbx %VD, %VA, %VB:Vector Compare Equal-to Unsigned Byte + int i; + for (i = 0; i < 16; i++) + if ((*vA).b[i] == (*vB).b[i]) + (*vS).b[i] = 0xff; + else + (*vS).b[i] = 0; + if (RC) + ALTIVEC_SET_CR6(vS, 1); + PPC_INSN_VR_CR(VS_BITMASK, VA_BITMASK | VB_BITMASK, RC ? 0x000000f0 : 0); + +0.4,6.VS,11.VA,16.VB,21.RC,22.70:VXR:av:vcmpequhx %VD, %VA, %VB:Vector Compare Equal-to Unsigned Half Word + int i; + for (i = 0; i < 8; i++) + if ((*vA).h[i] == (*vB).h[i]) + (*vS).h[i] = 0xffff; + else + (*vS).h[i] = 0; + if (RC) + ALTIVEC_SET_CR6(vS, 1); + PPC_INSN_VR_CR(VS_BITMASK, VA_BITMASK | VB_BITMASK, RC ? 0x000000f0 : 0); + +0.4,6.VS,11.VA,16.VB,21.RC,22.134:VXR:av:vcmpequwx %VD, %VA, %VB:Vector Compare Equal-to Unsigned Word + int i; + for (i = 0; i < 4; i++) + if ((*vA).w[i] == (*vB).w[i]) + (*vS).w[i] = 0xffffffff; + else + (*vS).w[i] = 0; + if (RC) + ALTIVEC_SET_CR6(vS, 1); + PPC_INSN_VR_CR(VS_BITMASK, VA_BITMASK | VB_BITMASK, RC ? 0x000000f0 : 0); + +0.4,6.VS,11.VA,16.VB,21.RC,22.454:VXR:av:vcmpgefpx %VD, %VA, %VB:Vector Compare Greater-Than-or-Equal-to Floating Point + int i; + sim_fpu a, b; + for (i = 0; i < 4; i++) { + sim_fpu_32to (&a, (*vA).w[i]); + sim_fpu_32to (&b, (*vB).w[i]); + if (sim_fpu_is_ge(&a, &b)) + (*vS).w[i] = 0xffffffff; + else + (*vS).w[i] = 0; + } + if (RC) + ALTIVEC_SET_CR6(vS, 1); + PPC_INSN_VR_CR(VS_BITMASK, VA_BITMASK | VB_BITMASK, RC ? 0x000000f0 : 0); + +0.4,6.VS,11.VA,16.VB,21.RC,22.710:VXR:av:vcmpgtfpx %VD, %VA, %VB:Vector Compare Greater-Than Floating Point + int i; + sim_fpu a, b; + for (i = 0; i < 4; i++) { + sim_fpu_32to (&a, (*vA).w[i]); + sim_fpu_32to (&b, (*vB).w[i]); + if (sim_fpu_is_gt(&a, &b)) + (*vS).w[i] = 0xffffffff; + else + (*vS).w[i] = 0; + } + if (RC) + ALTIVEC_SET_CR6(vS, 1); + PPC_INSN_VR_CR(VS_BITMASK, VA_BITMASK | VB_BITMASK, RC ? 0x000000f0 : 0); + +0.4,6.VS,11.VA,16.VB,21.RC,22.774:VXR:av:vcmpgtsbx %VD, %VA, %VB:Vector Compare Greater-Than Signed Byte + int i; + signed8 a, b; + for (i = 0; i < 16; i++) { + a = (*vA).b[i]; + b = (*vB).b[i]; + if (a > b) + (*vS).b[i] = 0xff; + else + (*vS).b[i] = 0; + } + if (RC) + ALTIVEC_SET_CR6(vS, 1); + PPC_INSN_VR_CR(VS_BITMASK, VA_BITMASK | VB_BITMASK, RC ? 0x000000f0 : 0); + +0.4,6.VS,11.VA,16.VB,21.RC,22.838:VXR:av:vcmpgtshx %VD, %VA, %VB:Vector Compare Greater-Than Signed Half Word + int i; + signed16 a, b; + for (i = 0; i < 8; i++) { + a = (*vA).h[i]; + b = (*vB).h[i]; + if (a > b) + (*vS).h[i] = 0xffff; + else + (*vS).h[i] = 0; + } + if (RC) + ALTIVEC_SET_CR6(vS, 1); + PPC_INSN_VR_CR(VS_BITMASK, VA_BITMASK | VB_BITMASK, RC ? 0x000000f0 : 0); + +0.4,6.VS,11.VA,16.VB,21.RC,22.902:VXR:av:vcmpgtswx %VD, %VA, %VB:Vector Compare Greater-Than Signed Word + int i; + signed32 a, b; + for (i = 0; i < 4; i++) { + a = (*vA).w[i]; + b = (*vB).w[i]; + if (a > b) + (*vS).w[i] = 0xffffffff; + else + (*vS).w[i] = 0; + } + if (RC) + ALTIVEC_SET_CR6(vS, 1); + PPC_INSN_VR_CR(VS_BITMASK, VA_BITMASK | VB_BITMASK, RC ? 0x000000f0 : 0); + +0.4,6.VS,11.VA,16.VB,21.RC,22.518:VXR:av:vcmpgtubx %VD, %VA, %VB:Vector Compare Greater-Than Unsigned Byte + int i; + unsigned8 a, b; + for (i = 0; i < 16; i++) { + a = (*vA).b[i]; + b = (*vB).b[i]; + if (a > b) + (*vS).b[i] = 0xff; + else + (*vS).b[i] = 0; + } + if (RC) + ALTIVEC_SET_CR6(vS, 1); + PPC_INSN_VR_CR(VS_BITMASK, VA_BITMASK | VB_BITMASK, RC ? 0x000000f0 : 0); + +0.4,6.VS,11.VA,16.VB,21.RC,22.582:VXR:av:vcmpgtuhx %VD, %VA, %VB:Vector Compare Greater-Than Unsigned Half Word + int i; + unsigned16 a, b; + for (i = 0; i < 8; i++) { + a = (*vA).h[i]; + b = (*vB).h[i]; + if (a > b) + (*vS).h[i] = 0xffff; + else + (*vS).h[i] = 0; + } + if (RC) + ALTIVEC_SET_CR6(vS, 1); + PPC_INSN_VR_CR(VS_BITMASK, VA_BITMASK | VB_BITMASK, RC ? 0x000000f0 : 0); + +0.4,6.VS,11.VA,16.VB,21.RC,22.646:VXR:av:vcmpgtuwx %VD, %VA, %VB:Vector Compare Greater-Than Unsigned Word + int i; + unsigned32 a, b; + for (i = 0; i < 4; i++) { + a = (*vA).w[i]; + b = (*vB).w[i]; + if (a > b) + (*vS).w[i] = 0xffffffff; + else + (*vS).w[i] = 0; + } + if (RC) + ALTIVEC_SET_CR6(vS, 1); + PPC_INSN_VR_CR(VS_BITMASK, VA_BITMASK | VB_BITMASK, RC ? 0x000000f0 : 0); + +# +# Vector Convert instructions, 6-65, 6-66. +# + +0.4,6.VS,11.UIMM,16.VB,21.970:VX:av:vctsxs %VD, %VB, %UIMM:Vector Convert to Signed Fixed-Point Word Saturate + int i, sat, tempsat; + signed64 temp; + sim_fpu a, b, m; + sat = 0; + for (i = 0; i < 4; i++) { + sim_fpu_32to (&b, (*vB).w[i]); + sim_fpu_u32to (&m, 2 << UIMM, sim_fpu_round_default); + sim_fpu_mul (&a, &b, &m); + sim_fpu_to64i (&temp, &a, sim_fpu_round_default); + (*vS).w[i] = altivec_signed_saturate_32(temp, &tempsat); + sat |= tempsat; + } + ALTIVEC_SET_SAT(sat); + PPC_INSN_VR_VSCR(VS_BITMASK, VB_BITMASK); + +0.4,6.VS,11.UIMM,16.VB,21.906:VX:av:vctuxs %VD, %VB, %UIMM:Vector Convert to Unsigned Fixed-Point Word Saturate + int i, sat, tempsat; + signed64 temp; + sim_fpu a, b, m; + sat = 0; + for (i = 0; i < 4; i++) { + sim_fpu_32to (&b, (*vB).w[i]); + sim_fpu_u32to (&m, 2 << UIMM, sim_fpu_round_default); + sim_fpu_mul (&a, &b, &m); + sim_fpu_to64u (&temp, &a, sim_fpu_round_default); + (*vS).w[i] = altivec_unsigned_saturate_32(temp, &tempsat); + sat |= tempsat; + } + ALTIVEC_SET_SAT(sat); + PPC_INSN_VR_VSCR(VS_BITMASK, VB_BITMASK); + +# +# Vector Estimate instructions, 6-67 ... 6-70. +# + +0.4,6.VS,11.0,16.VB,21.394:VX:av:vexptefp %VD, %VB:Vector 2 Raised to the Exponent Estimate Floating Point + int i; + unsigned32 f; + signed32 bi; + sim_fpu b, d; + for (i = 0; i < 4; i++) { + /*HACK!*/ + sim_fpu_32to (&b, (*vB).w[i]); + sim_fpu_to32i (&bi, &b, sim_fpu_round_default); + bi = 2 ^ bi; + sim_fpu_32to (&d, bi); + sim_fpu_to32 (&f, &d); + (*vS).w[i] = f; + } + PPC_INSN_VR_VSCR(VS_BITMASK, VB_BITMASK); + +0.4,6.VS,11.0,16.VB,21.458:VX:av:vlogefp %VD, %VB:Vector Log2 Estimate Floating Point + int i; + unsigned32 c, u, f; + sim_fpu b, cfpu, d; + for (i = 0; i < 4; i++) { + /*HACK!*/ + sim_fpu_32to (&b, (*vB).w[i]); + sim_fpu_to32u (&u, &b, sim_fpu_round_default); + for (c = 0; (u /= 2) > 1; c++) + ; + sim_fpu_32to (&cfpu, c); + sim_fpu_add (&d, &b, &cfpu); + sim_fpu_to32 (&f, &d); + (*vS).w[i] = f; + } + PPC_INSN_VR_VSCR(VS_BITMASK, VB_BITMASK); + +# +# Vector Multiply Add instruction, 6-71 +# + +0.4,6.VS,11.VA,16.VB,21.VC,26.46:VAX:av:vmaddfp %VD, %VA, %VB, %VC:Vector Multiply Add Floating Point + int i; + unsigned32 f; + sim_fpu a, b, c, d, e; + for (i = 0; i < 4; i++) { + sim_fpu_32to (&a, (*vA).w[i]); + sim_fpu_32to (&b, (*vB).w[i]); + sim_fpu_32to (&c, (*vC).w[i]); + sim_fpu_mul (&e, &a, &c); + sim_fpu_add (&d, &e, &b); + sim_fpu_to32 (&f, &d); + (*vS).w[i] = f; + } + PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK | VC_BITMASK); + + +# +# Vector Maximum instructions, 6-72 ... 6-78. +# + +0.4,6.VS,11.VA,16.VB,21.1034:VX:av:vmaxfp %VD, %VA, %VB:Vector Maximum Floating Point + int i; + unsigned32 f; + sim_fpu a, b, d; + for (i = 0; i < 4; i++) { + sim_fpu_32to (&a, (*vA).w[i]); + sim_fpu_32to (&b, (*vB).w[i]); + sim_fpu_max (&d, &a, &b); + sim_fpu_to32 (&f, &d); + (*vS).w[i] = f; + } + PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); + +0.4,6.VS,11.VA,16.VB,21.258:VX:av:vmaxsb %VD, %VA, %VB:Vector Maximum Signed Byte + int i; + signed8 a, b; + for (i = 0; i < 16; i++) { + a = (*vA).b[i]; + b = (*vB).b[i]; + if (a > b) + (*vS).b[i] = a; + else + (*vS).b[i] = b; + } + PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); + +0.4,6.VS,11.VA,16.VB,21.322:VX:av:vmaxsh %VD, %VA, %VB:Vector Maximum Signed Half Word + int i; + signed16 a, b; + for (i = 0; i < 8; i++) { + a = (*vA).h[i]; + b = (*vB).h[i]; + if (a > b) + (*vS).h[i] = a; + else + (*vS).h[i] = b; + } + PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); + +0.4,6.VS,11.VA,16.VB,21.386:VX:av:vmaxsw %VD, %VA, %VB:Vector Maximum Signed Word + int i; + signed32 a, b; + for (i = 0; i < 4; i++) { + a = (*vA).w[i]; + b = (*vB).w[i]; + if (a > b) + (*vS).w[i] = a; + else + (*vS).w[i] = b; + } + PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); + +0.4,6.VS,11.VA,16.VB,21.2:VX:av:vmaxub %VD, %VA, %VB:Vector Maximum Unsigned Byte + int i; + unsigned8 a, b; + for (i = 0; i < 16; i++) { + a = (*vA).b[i]; + b = (*vB).b[i]; + if (a > b) + (*vS).b[i] = a; + else + (*vS).b[i] = b; + }; + PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); + +0.4,6.VS,11.VA,16.VB,21.66:VX:av:vmaxus %VD, %VA, %VB:Vector Maximum Unsigned Half Word + int i; + unsigned16 a, b; + for (i = 0; i < 8; i++) { + a = (*vA).h[i]; + b = (*vB).h[i]; + if (a > b) + (*vS).h[i] = a; + else + (*vS).h[i] = b; + } + PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); + +0.4,6.VS,11.VA,16.VB,21.130:VX:av:vmaxuw %VD, %VA, %VB:Vector Maximum Unsigned Word + int i; + unsigned32 a, b; + for (i = 0; i < 4; i++) { + a = (*vA).w[i]; + b = (*vB).w[i]; + if (a > b) + (*vS).w[i] = a; + else + (*vS).w[i] = b; + } + PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); + + +# +# Vector Multiple High instructions, 6-79, 6-80. +# + +0.4,6.VS,11.VA,16.VB,21.VC,26.32:VAX:av:vmhaddshs %VD, %VA, %VB, %VC:Vector Multiple High and Add Signed Half Word Saturate + int i, sat, tempsat; + signed16 a, b; + signed32 prod, temp, c; + for (i = 0; i < 8; i++) { + a = (*vA).h[i]; + b = (*vB).h[i]; + c = (signed32)(signed16)(*vC).h[i]; + prod = (signed32)a * (signed32)b; + temp = (prod >> 15) + c; + (*vS).h[i] = altivec_signed_saturate_16(temp, &tempsat); + sat |= tempsat; + } + ALTIVEC_SET_SAT(sat); + PPC_INSN_VR_VSCR(VS_BITMASK, VA_BITMASK | VB_BITMASK | VC_BITMASK); + +0.4,6.VS,11.VA,16.VB,21.VC,26.33:VAX:av:vmhraddshs %VD, %VA, %VB, %VC:Vector Multiple High Round and Add Signed Half Word Saturate + int i, sat, tempsat; + signed16 a, b; + signed32 prod, temp, c; + for (i = 0; i < 8; i++) { + a = (*vA).h[i]; + b = (*vB).h[i]; + c = (signed32)(signed16)(*vC).h[i]; + prod = (signed32)a * (signed32)b; + prod += 0x4000; + temp = (prod >> 15) + c; + (*vS).h[i] = altivec_signed_saturate_16(temp, &tempsat); + sat |= tempsat; + } + ALTIVEC_SET_SAT(sat); + PPC_INSN_VR_VSCR(VS_BITMASK, VA_BITMASK | VB_BITMASK | VC_BITMASK); + + +# +# Vector Minimum instructions, 6-81 ... 6-87 +# + +0.4,6.VS,11.VA,16.VB,21.1098:VX:av:vminfp %VD, %VA, %VB:Vector Minimum Floating Point + int i; + unsigned32 f; + sim_fpu a, b, d; + for (i = 0; i < 4; i++) { + sim_fpu_32to (&a, (*vA).w[i]); + sim_fpu_32to (&b, (*vB).w[i]); + sim_fpu_min (&d, &a, &b); + sim_fpu_to32 (&f, &d); + (*vS).w[i] = f; + } + PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); + +0.4,6.VS,11.VA,16.VB,21.770:VX:av:vminsb %VD, %VA, %VB:Vector Minimum Signed Byte + int i; + signed8 a, b; + for (i = 0; i < 16; i++) { + a = (*vA).b[i]; + b = (*vB).b[i]; + if (a < b) + (*vS).b[i] = a; + else + (*vS).b[i] = b; + } + PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); + +0.4,6.VS,11.VA,16.VB,21.834:VX:av:vminsh %VD, %VA, %VB:Vector Minimum Signed Half Word + int i; + signed16 a, b; + for (i = 0; i < 8; i++) { + a = (*vA).h[i]; + b = (*vB).h[i]; + if (a < b) + (*vS).h[i] = a; + else + (*vS).h[i] = b; + } + PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); + +0.4,6.VS,11.VA,16.VB,21.898:VX:av:vminsw %VD, %VA, %VB:Vector Minimum Signed Word + int i; + signed32 a, b; + for (i = 0; i < 4; i++) { + a = (*vA).w[i]; + b = (*vB).w[i]; + if (a < b) + (*vS).w[i] = a; + else + (*vS).w[i] = b; + } + PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); + +0.4,6.VS,11.VA,16.VB,21.514:VX:av:vminub %VD, %VA, %VB:Vector Minimum Unsigned Byte + int i; + unsigned8 a, b; + for (i = 0; i < 16; i++) { + a = (*vA).b[i]; + b = (*vB).b[i]; + if (a < b) + (*vS).b[i] = a; + else + (*vS).b[i] = b; + }; + PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); + +0.4,6.VS,11.VA,16.VB,21.578:VX:av:vminuh %VD, %VA, %VB:Vector Minimum Unsigned Half Word + int i; + unsigned16 a, b; + for (i = 0; i < 8; i++) { + a = (*vA).h[i]; + b = (*vB).h[i]; + if (a < b) + (*vS).h[i] = a; + else + (*vS).h[i] = b; + } + PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); + +0.4,6.VS,11.VA,16.VB,21.642:VX:av:vminuw %VD, %VA, %VB:Vector Minimum Unsigned Word + int i; + unsigned32 a, b; + for (i = 0; i < 4; i++) { + a = (*vA).w[i]; + b = (*vB).w[i]; + if (a < b) + (*vS).w[i] = a; + else + (*vS).w[i] = b; + } + PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); + + +# +# Vector Multiply Low instruction, 6-88 +# + +0.4,6.VS,11.VA,16.VB,21.VC,26.34:VAX:av:vmladduhm %VD, %VA, %VB, %VC:Vector Multiply Low and Add Unsigned Half Word Modulo + int i; + unsigned16 a, b, c; + unsigned32 prod; + for (i = 0; i < 8; i++) { + a = (*vA).h[i]; + b = (*vB).h[i]; + c = (*vC).h[i]; + prod = (unsigned32)a * (unsigned32)b; + (*vS).h[i] = (prod + c) & 0xffff; + } + PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK | VC_BITMASK); + + +# +# Vector Merge instructions, 6-89 ... 6-94 +# + +0.4,6.VS,11.VA,16.VB,21.12:VX:av:vmrghb %VD, %VA, %VB:Vector Merge High Byte + int i; + for (i = 0; i < 16; i += 2) { + (*vS).b[AV_BINDEX(i)] = (*vA).b[AV_BINDEX(i/2)]; + (*vS).b[AV_BINDEX(i+1)] = (*vB).b[AV_BINDEX(i/2)]; + } + PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); + +0.4,6.VS,11.VA,16.VB,21.76:VX:av:vmrghh %VD, %VA, %VB:Vector Merge High Half Word + int i; + for (i = 0; i < 8; i += 2) { + (*vS).h[AV_HINDEX(i)] = (*vA).h[AV_HINDEX(i/2)]; + (*vS).h[AV_HINDEX(i+1)] = (*vB).h[AV_HINDEX(i/2)]; + } + PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); + +0.4,6.VS,11.VA,16.VB,21.140:VX:av:vmrghw %VD, %VA, %VB:Vector Merge High Word + int i; + for (i = 0; i < 4; i += 2) { + (*vS).w[i] = (*vA).w[i/2]; + (*vS).w[i+1] = (*vB).w[i/2]; + } + PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); + +0.4,6.VS,11.VA,16.VB,21.268:VX:av:vmrglb %VD, %VA, %VB:Vector Merge Low Byte + int i; + for (i = 0; i < 16; i += 2) { + (*vS).b[AV_BINDEX(i)] = (*vA).b[AV_BINDEX((i/2) + 8)]; + (*vS).b[AV_BINDEX(i+1)] = (*vB).b[AV_BINDEX((i/2) + 8)]; + } + PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); + +0.4,6.VS,11.VA,16.VB,21.332:VX:av:vmrglh %VD, %VA, %VB:Vector Merge Low Half Word + int i; + for (i = 0; i < 8; i += 2) { + (*vS).h[AV_HINDEX(i)] = (*vA).h[AV_HINDEX((i/2) + 4)]; + (*vS).h[AV_HINDEX(i+1)] = (*vB).h[AV_HINDEX((i/2) + 4)]; + } + PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); + +0.4,6.VS,11.VA,16.VB,21.396:VX:av:vmrglw %VD, %VA, %VB:Vector Merge Low Word + int i; + for (i = 0; i < 4; i += 2) { + (*vS).w[i] = (*vA).w[(i/2) + 2]; + (*vS).w[i+1] = (*vB).w[(i/2) + 2]; + } + PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); + + +# +# Vector Multiply Sum instructions, 6-95 ... 6-100 +# + +0.4,6.VS,11.VA,16.VB,21.VC,26.37:VAX:av:vmsummbm %VD, %VA, %VB, %VC:Vector Multiply Sum Mixed-Sign Byte Modulo + int i, j; + signed32 temp; + signed16 prod, a; + unsigned16 b; + for (i = 0; i < 4; i++) { + temp = (*vC).w[i]; + for (j = 0; j < 4; j++) { + a = (signed16)(signed8)(*vA).b[i*4+j]; + b = (*vB).b[i*4+j]; + prod = a * b; + temp += (signed32)prod; + } + (*vS).w[i] = temp; + } + PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK | VC_BITMASK); + +0.4,6.VS,11.VA,16.VB,21.VC,26.40:VAX:av:vmsumshm %VD, %VA, %VB, %VC:Vector Multiply Sum Signed Half Word Modulo + int i, j; + signed32 temp, prod, a, b; + for (i = 0; i < 4; i++) { + temp = (*vC).w[i]; + for (j = 0; j < 2; j++) { + a = (signed32)(signed16)(*vA).h[i*2+j]; + b = (signed32)(signed16)(*vB).h[i*2+j]; + prod = a * b; + temp += prod; + } + (*vS).w[i] = temp; + } + PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK | VC_BITMASK); + +0.4,6.VS,11.VA,16.VB,21.VC,26.41:VAX:av:vmsumshs %VD, %VA, %VB, %VC:Vector Multiply Sum Signed Half Word Saturate + int i, j, sat, tempsat; + signed64 temp; + signed32 prod, a, b; + sat = 0; + for (i = 0; i < 4; i++) { + temp = (signed64)(signed32)(*vC).w[i]; + for (j = 0; j < 2; j++) { + a = (signed32)(signed16)(*vA).h[i*2+j]; + b = (signed32)(signed16)(*vB).h[i*2+j]; + prod = a * b; + temp += (signed64)prod; + } + (*vS).w[i] = altivec_signed_saturate_32(temp, &tempsat); + sat |= tempsat; + } + ALTIVEC_SET_SAT(sat); + PPC_INSN_VR_VSCR(VS_BITMASK, VA_BITMASK | VB_BITMASK | VC_BITMASK); + +0.4,6.VS,11.VA,16.VB,21.VC,26.36:VAX:av:vmsumubm %VD, %VA, %VB, %VC:Vector Multiply Sum Unsigned Byte Modulo + int i, j; + unsigned32 temp; + unsigned16 prod, a, b; + for (i = 0; i < 4; i++) { + temp = (*vC).w[i]; + for (j = 0; j < 4; j++) { + a = (*vA).b[i*4+j]; + b = (*vB).b[i*4+j]; + prod = a * b; + temp += prod; + } + (*vS).w[i] = temp; + } + PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK | VC_BITMASK); + +0.4,6.VS,11.VA,16.VB,21.VC,26.38:VAX:av:vmsumuhm %VD, %VA, %VB, %VC:Vector Multiply Sum Unsigned Half Word Modulo + int i, j; + unsigned32 temp, prod, a, b; + for (i = 0; i < 4; i++) { + temp = (*vC).w[i]; + for (j = 0; j < 2; j++) { + a = (*vA).h[i*2+j]; + b = (*vB).h[i*2+j]; + prod = a * b; + temp += prod; + } + (*vS).w[i] = temp; + } + PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK | VC_BITMASK); + +0.4,6.VS,11.VA,16.VB,21.VC,26.39:VAX:av:vmsumuhs %VD, %VA, %VB, %VC:Vector Multiply Sum Unsigned Half Word Saturate + int i, j, sat, tempsat; + unsigned32 temp, prod, a, b; + sat = 0; + for (i = 0; i < 4; i++) { + temp = (*vC).w[i]; + for (j = 0; j < 2; j++) { + a = (*vA).h[i*2+j]; + b = (*vB).h[i*2+j]; + prod = a * b; + temp += prod; + } + (*vS).w[i] = altivec_unsigned_saturate_32(temp, &tempsat); + sat |= tempsat; + } + ALTIVEC_SET_SAT(sat); + PPC_INSN_VR_VSCR(VS_BITMASK, VA_BITMASK | VB_BITMASK | VC_BITMASK); + + +# +# Vector Multiply Even/Odd instructions, 6-101 ... 6-108 +# + +0.4,6.VS,11.VA,16.VB,21.776:VX:av:vmulesb %VD, %VA, %VB:Vector Multiply Even Signed Byte + int i; + signed8 a, b; + signed16 prod; + for (i = 0; i < 8; i++) { + a = (*vA).b[AV_BINDEX(i*2)]; + b = (*vB).b[AV_BINDEX(i*2)]; + prod = a * b; + (*vS).h[AV_HINDEX(i)] = prod; + } + PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); + +0.4,6.VS,11.VA,16.VB,21.840:VX:av:vmulesh %VD, %VA, %VB:Vector Multiply Even Signed Half Word + int i; + signed16 a, b; + signed32 prod; + for (i = 0; i < 4; i++) { + a = (*vA).h[AV_HINDEX(i*2)]; + b = (*vB).h[AV_HINDEX(i*2)]; + prod = a * b; + (*vS).w[i] = prod; + } + PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); + +0.4,6.VS,11.VA,16.VB,21.520:VX:av:vmuleub %VD, %VA, %VB:Vector Multiply Even Unsigned Byte + int i; + unsigned8 a, b; + unsigned16 prod; + for (i = 0; i < 8; i++) { + a = (*vA).b[AV_BINDEX(i*2)]; + b = (*vB).b[AV_BINDEX(i*2)]; + prod = a * b; + (*vS).h[AV_HINDEX(i)] = prod; + } + PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); + +0.4,6.VS,11.VA,16.VB,21.584:VX:av:vmuleuh %VD, %VA, %VB:Vector Multiply Even Unsigned Half Word + int i; + unsigned16 a, b; + unsigned32 prod; + for (i = 0; i < 4; i++) { + a = (*vA).h[AV_HINDEX(i*2)]; + b = (*vB).h[AV_HINDEX(i*2)]; + prod = a * b; + (*vS).w[i] = prod; + } + PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); + +0.4,6.VS,11.VA,16.VB,21.264:VX:av:vmulosb %VD, %VA, %VB:Vector Multiply Odd Signed Byte + int i; + signed8 a, b; + signed16 prod; + for (i = 0; i < 8; i++) { + a = (*vA).b[AV_BINDEX((i*2)+1)]; + b = (*vB).b[AV_BINDEX((i*2)+1)]; + prod = a * b; + (*vS).h[AV_HINDEX(i)] = prod; + } + PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); + +0.4,6.VS,11.VA,16.VB,21.328:VX:av:vmulosh %VD, %VA, %VB:Vector Multiply Odd Signed Half Word + int i; + signed16 a, b; + signed32 prod; + for (i = 0; i < 4; i++) { + a = (*vA).h[AV_HINDEX((i*2)+1)]; + b = (*vB).h[AV_HINDEX((i*2)+1)]; + prod = a * b; + (*vS).w[i] = prod; + } + PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); + +0.4,6.VS,11.VA,16.VB,21.8:VX:av:vmuloub %VD, %VA, %VB:Vector Multiply Odd Unsigned Byte + int i; + unsigned8 a, b; + unsigned16 prod; + for (i = 0; i < 8; i++) { + a = (*vA).b[AV_BINDEX((i*2)+1)]; + b = (*vB).b[AV_BINDEX((i*2)+1)]; + prod = a * b; + (*vS).h[AV_HINDEX(i)] = prod; + } + PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); + +0.4,6.VS,11.VA,16.VB,21.72:VX:av:vmulouh %VD, %VA, %VB:Vector Multiply Odd Unsigned Half Word + int i; + unsigned16 a, b; + unsigned32 prod; + for (i = 0; i < 4; i++) { + a = (*vA).h[AV_HINDEX((i*2)+1)]; + b = (*vB).h[AV_HINDEX((i*2)+1)]; + prod = a * b; + (*vS).w[i] = prod; + } + PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); + + +# +# Vector Negative Multiply-Subtract instruction, 6-109 +# + +0.4,6.VS,11.VA,16.VB,21.VC,26.47:VX:av:vnmsubfp %VD, %VA, %VB, %VC:Vector Negative Multiply-Subtract Floating Point + int i; + unsigned32 f; + sim_fpu a, b, c, d, i1, i2; + for (i = 0; i < 4; i++) { + sim_fpu_32to (&a, (*vA).w[i]); + sim_fpu_32to (&b, (*vB).w[i]); + sim_fpu_32to (&c, (*vC).w[i]); + sim_fpu_mul (&i1, &a, &c); + sim_fpu_sub (&i2, &i1, &b); + sim_fpu_neg (&d, &i2); + sim_fpu_to32 (&f, &d); + (*vS).w[i] = f; + } + PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK | VC_BITMASK); + + +# +# Vector Logical OR instructions, 6-110, 6-111, 6-177 +# + +0.4,6.VS,11.VA,16.VB,21.1284:VX:av:vnor %VD, %VA, %VB:Vector Logical NOR + int i; + for (i = 0; i < 4; i++) + (*vS).w[i] = ~((*vA).w[i] | (*vB).w[i]); + PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); + +0.4,6.VS,11.VA,16.VB,21.1156:VX:av:vor %VD, %VA, %VB:Vector Logical OR + int i; + for (i = 0; i < 4; i++) + (*vS).w[i] = (*vA).w[i] | (*vB).w[i]; + PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); + +0.4,6.VS,11.VA,16.VB,21.1220:VX:av:vxor %VD, %VA, %VB:Vector Logical XOR + int i; + for (i = 0; i < 4; i++) + (*vS).w[i] = (*vA).w[i] ^ (*vB).w[i]; + PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); + + +# +# Vector Permute instruction, 6-112 +# + +0.4,6.VS,11.VA,16.VB,21.VC,26.43:VX:av:vperm %VD, %VA, %VB, %VC:Vector Permute + int i, who; + for (i = 0; i < 16; i++) { + who = (*vC).b[AV_BINDEX(i)] & 0x1f; + if (who & 0x10) + (*vS).b[AV_BINDEX(i)] = (*vB).b[AV_BINDEX(who & 0xf)]; + else + (*vS).b[AV_BINDEX(i)] = (*vA).b[AV_BINDEX(who & 0xf)]; + } + PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK | VC_BITMASK); + + +# +# Vector Pack instructions, 6-113 ... 6-121 +# + +0.4,6.VS,11.VA,16.VB,21.782:VX:av:vpkpx %VD, %VA, %VB:Vector Pack Pixel32 + int i; + for (i = 0; i < 4; i++) { + (*vS).h[AV_HINDEX(i+4)] = ((((*vB).w[i]) >> 9) & 0xfc00) + | ((((*vB).w[i]) >> 6) & 0x03e0) + | ((((*vB).w[i]) >> 3) & 0x001f); + (*vS).h[AV_HINDEX(i)] = ((((*vA).w[i]) >> 9) & 0xfc00) + | ((((*vA).w[i]) >> 6) & 0x03e0) + | ((((*vA).w[i]) >> 3) & 0x001f); + } + PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); + +0.4,6.VS,11.VA,16.VB,21.398:VX:av:vpkshss %VD, %VA, %VB:Vector Pack Signed Half Word Signed Saturate + int i, sat, tempsat; + signed16 temp; + sat = 0; + for (i = 0; i < 16; i++) { + if (i < 8) + temp = (*vA).h[AV_HINDEX(i)]; + else + temp = (*vB).h[AV_HINDEX(i-8)]; + (*vS).b[AV_BINDEX(i)] = altivec_signed_saturate_8(temp, &tempsat); + sat |= tempsat; + } + ALTIVEC_SET_SAT(sat); + PPC_INSN_VR_VSCR(VS_BITMASK, VA_BITMASK | VB_BITMASK); + +0.4,6.VS,11.VA,16.VB,21.270:VX:av:vpkshus %VD, %VA, %VB:Vector Pack Signed Half Word Unsigned Saturate + int i, sat, tempsat; + signed16 temp; + sat = 0; + for (i = 0; i < 16; i++) { + if (i < 8) + temp = (*vA).h[AV_HINDEX(i)]; + else + temp = (*vB).h[AV_HINDEX(i-8)]; + (*vS).b[AV_BINDEX(i)] = altivec_unsigned_saturate_8(temp, &tempsat); + sat |= tempsat; + } + ALTIVEC_SET_SAT(sat); + PPC_INSN_VR_VSCR(VS_BITMASK, VA_BITMASK | VB_BITMASK); + +0.4,6.VS,11.VA,16.VB,21.462:VX:av:vpkswss %VD, %VA, %VB:Vector Pack Signed Word Signed Saturate + int i, sat, tempsat; + signed32 temp; + sat = 0; + for (i = 0; i < 8; i++) { + if (i < 4) + temp = (*vA).w[i]; + else + temp = (*vB).w[i-4]; + (*vS).h[AV_HINDEX(i)] = altivec_signed_saturate_16(temp, &tempsat); + sat |= tempsat; + } + ALTIVEC_SET_SAT(sat); + PPC_INSN_VR_VSCR(VS_BITMASK, VA_BITMASK | VB_BITMASK); + +0.4,6.VS,11.VA,16.VB,21.334:VX:av:vpkswus %VD, %VA, %VB:Vector Pack Signed Word Unsigned Saturate + int i, sat, tempsat; + signed32 temp; + sat = 0; + for (i = 0; i < 8; i++) { + if (i < 4) + temp = (*vA).w[i]; + else + temp = (*vB).w[i-4]; + (*vS).h[AV_HINDEX(i)] = altivec_unsigned_saturate_16(temp, &tempsat); + sat |= tempsat; + } + ALTIVEC_SET_SAT(sat); + PPC_INSN_VR_VSCR(VS_BITMASK, VA_BITMASK | VB_BITMASK); + +0.4,6.VS,11.VA,16.VB,21.14:VX:av:vpkuhum %VD, %VA, %VB:Vector Pack Unsigned Half Word Unsigned Modulo + int i; + for (i = 0; i < 16; i++) + if (i < 8) + (*vS).b[AV_BINDEX(i)] = (*vA).h[AV_HINDEX(i)]; + else + (*vS).b[AV_BINDEX(i)] = (*vB).h[AV_HINDEX(i-8)]; + PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); + +0.4,6.VS,11.VA,16.VB,21.142:VX:av:vpkuhus %VD, %VA, %VB:Vector Pack Unsigned Half Word Unsigned Saturate + int i, sat, tempsat; + signed16 temp; + sat = 0; + for (i = 0; i < 16; i++) { + if (i < 8) + temp = (*vA).h[AV_HINDEX(i)]; + else + temp = (*vB).h[AV_HINDEX(i-8)]; + /* force positive in signed16, ok as we'll toss the bit away anyway */ + temp &= ~0x8000; + (*vS).b[AV_BINDEX(i)] = altivec_unsigned_saturate_8(temp, &tempsat); + sat |= tempsat; + } + ALTIVEC_SET_SAT(sat); + PPC_INSN_VR_VSCR(VS_BITMASK, VA_BITMASK | VB_BITMASK); + +0.4,6.VS,11.VA,16.VB,21.78:VX:av:vpkuwum %VD, %VA, %VB:Vector Pack Unsigned Word Unsigned Modulo + int i; + for (i = 0; i < 8; i++) + if (i < 8) + (*vS).h[AV_HINDEX(i)] = (*vA).w[i]; + else + (*vS).h[AV_HINDEX(i)] = (*vB).w[i-8]; + PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); + +0.4,6.VS,11.VA,16.VB,21.206:VX:av:vpkuwus %VD, %VA, %VB:Vector Pack Unsigned Word Unsigned Saturate + int i, sat, tempsat; + signed32 temp; + sat = 0; + for (i = 0; i < 8; i++) { + if (i < 4) + temp = (*vA).w[i]; + else + temp = (*vB).w[i-4]; + /* force positive in signed32, ok as we'll toss the bit away anyway */ + temp &= ~0x80000000; + (*vS).h[AV_HINDEX(i)] = altivec_unsigned_saturate_16(temp, &tempsat); + sat |= tempsat; + } + ALTIVEC_SET_SAT(sat); + PPC_INSN_VR_VSCR(VS_BITMASK, VA_BITMASK | VB_BITMASK); + + +# +# Vector Reciprocal instructions, 6-122, 6-123, 6-131 +# + +0.4,6.VS,11.0,16.VB,21.266:VX:av:vrefp %VD, %VB:Vector Reciprocal Estimate Floating Point + int i; + unsigned32 f; + sim_fpu op, d; + for (i = 0; i < 4; i++) { + sim_fpu_32to (&op, (*vB).w[i]); + sim_fpu_div (&d, &sim_fpu_one, &op); + sim_fpu_to32 (&f, &d); + (*vS).w[i] = f; + } + PPC_INSN_VR(VS_BITMASK, VB_BITMASK); + +0.4,6.VS,11.0,16.VB,21.330:VX:av:vrsqrtefp %VD, %VB:Vector Reciprocal Square Root Estimate Floating Point + int i; + unsigned32 f; + sim_fpu op, i1, one, d; + for (i = 0; i < 4; i++) { + sim_fpu_32to (&op, (*vB).w[i]); + sim_fpu_sqrt (&i1, &op); + sim_fpu_div (&d, &sim_fpu_one, &i1); + sim_fpu_to32 (&f, &d); + (*vS).w[i] = f; + } + PPC_INSN_VR(VS_BITMASK, VB_BITMASK); + + +# +# Vector Round instructions, 6-124 ... 6-127 +# + +0.4,6.VS,11.0,16.VB,21.714:VX:av:vrfim %VD, %VB:Vector Round to Floating-Point Integer towards Minus Infinity + int i; + unsigned32 f; + sim_fpu op; + for (i = 0; i < 4; i++) { + sim_fpu_32to (&op, (*vB).w[i]); + sim_fpu_round_32(&op, sim_fpu_round_down, sim_fpu_denorm_default); + sim_fpu_to32 (&f, &op); + (*vS).w[i] = f; + } + PPC_INSN_VR(VS_BITMASK, VB_BITMASK); + +0.4,6.VS,11.0,16.VB,21.522:VX:av:vrfin %VD, %VB:Vector Round to Floating-Point Integer Nearest + int i; + unsigned32 f; + sim_fpu op; + for (i = 0; i < 4; i++) { + sim_fpu_32to (&op, (*vB).w[i]); + sim_fpu_round_32(&op, sim_fpu_round_near, sim_fpu_denorm_default); + sim_fpu_to32 (&f, &op); + (*vS).w[i] = f; + } + PPC_INSN_VR(VS_BITMASK, VB_BITMASK); + +0.4,6.VS,11.0,16.VB,21.650:VX:av:vrfip %VD, %VB:Vector Round to Floating-Point Integer towards Plus Infinity + int i; + unsigned32 f; + sim_fpu op; + for (i = 0; i < 4; i++) { + sim_fpu_32to (&op, (*vB).w[i]); + sim_fpu_round_32(&op, sim_fpu_round_up, sim_fpu_denorm_default); + sim_fpu_to32 (&f, &op); + (*vS).w[i] = f; + } + PPC_INSN_VR(VS_BITMASK, VB_BITMASK); + +0.4,6.VS,11.0,16.VB,21.586:VX:av:vrfiz %VD, %VB:Vector Round to Floating-Point Integer towards Zero + int i; + unsigned32 f; + sim_fpu op; + for (i = 0; i < 4; i++) { + sim_fpu_32to (&op, (*vB).w[i]); + sim_fpu_round_32(&op, sim_fpu_round_zero, sim_fpu_denorm_default); + sim_fpu_to32 (&f, &op); + (*vS).w[i] = f; + } + PPC_INSN_VR(VS_BITMASK, VB_BITMASK); + + +# +# Vector Rotate Left instructions, 6-128 ... 6-130 +# + +0.4,6.VS,11.VA,16.VB,21.4:VX:av:vrlb %VD, %VA, %VB:Vector Rotate Left Integer Byte + int i; + unsigned16 temp; + for (i = 0; i < 16; i++) { + temp = (unsigned16)(*vA).b[i] << (((*vB).b[i]) & 7); + (*vS).b[i] = (temp & 0xff) | ((temp >> 8) & 0xff); + } + PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); + +0.4,6.VS,11.VA,16.VB,21.68:VX:av:vrlh %VD, %VA, %VB:Vector Rotate Left Integer Half Word + int i; + unsigned32 temp; + for (i = 0; i < 8; i++) { + temp = (unsigned32)(*vA).h[i] << (((*vB).h[i]) & 0xf); + (*vS).h[i] = (temp & 0xffff) | ((temp >> 16) & 0xffff); + } + PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); + +0.4,6.VS,11.VA,16.VB,21.132:VX:av:vrlw %VD, %VA, %VB:Vector Rotate Left Integer Word + int i; + unsigned64 temp; + for (i = 0; i < 4; i++) { + temp = (unsigned64)(*vA).w[i] << (((*vB).w[i]) & 0x1f); + (*vS).w[i] = (temp & 0xffffffff) | ((temp >> 32) & 0xffffffff); + } + PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); + + +# +# Vector Conditional Select instruction, 6-133 +# + +0.4,6.VS,11.VA,16.VB,21.VC,26.42:VAX:av:vsel %VD, %VA, %VB, %VC:Vector Conditional Select + int i; + unsigned32 c; + for (i = 0; i < 4; i++) { + c = (*vC).w[i]; + (*vS).w[i] = ((*vB).w[i] & c) | ((*vA).w[i] & ~c); + } + PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK | VC_BITMASK); + +# +# Vector Shift Left instructions, 6-134 ... 6-139 +# + +0.4,6.VS,11.VA,16.VB,21.452:VX:av:vsl %VD, %VA, %VB:Vector Shift Left + int sh, i, j, carry, new_carry; + sh = (*vB).b[0] & 7; /* don't bother checking everything */ + carry = 0; + for (j = 3; j >= 0; j--) { + if (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN) + i = j; + else + i = (j + 2) % 4; + new_carry = (*vA).w[i] >> (32 - sh); + (*vS).w[i] = ((*vA).w[i] << sh) | carry; + carry = new_carry; + } + PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); + +0.4,6.VS,11.VA,16.VB,21.260:VX:av:vslb %VD, %VA, %VB:Vector Shift Left Integer Byte + int i, sh; + for (i = 0; i < 16; i++) { + sh = ((*vB).b[i]) & 7; + (*vS).b[i] = (*vA).b[i] << sh; + } + PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); + +0.4,6.VS,11.VA,16.VB,21.0,22.SH,26.44:VX:av:vsldol %VD, %VA, %VB:Vector Shift Left Double by Octet Immediate + int i, j; + for (j = 0, i = SH; i < 16; i++) + (*vS).b[j++] = (*vA).b[i]; + for (i = 0; i < SH; i++) + (*vS).b[j++] = (*vB).b[i]; + PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); + +0.4,6.VS,11.VA,16.VB,21.324:VX:av:vslh %VD, %VA, %VB:Vector Shift Left Half Word + int i, sh; + for (i = 0; i < 8; i++) { + sh = ((*vB).h[i]) & 0xf; + (*vS).h[i] = (*vA).h[i] << sh; + } + PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); + +0.4,6.VS,11.VA,16.VB,21.1036:VX:av:vslo %VD, %VA, %VB:Vector Shift Left by Octet + int i, sh; + if (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN) + sh = ((*vB).b[AV_BINDEX(15)] >> 3) & 0xf; + else + sh = ((*vB).b[AV_BINDEX(0)] >> 3) & 0xf; + for (i = 0; i < 16; i++) { + if (15 - i > sh) + (*vS).b[AV_BINDEX(i)] = (*vA).b[AV_BINDEX(i + sh)]; + else + (*vS).b[AV_BINDEX(i)] = 0; + } + PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); + +0.4,6.VS,11.VA,16.VB,21.388:VX:av:vslw %VD, %VA, %VB:Vector Shift Left Integer Word + int i, sh; + for (i = 0; i < 4; i++) { + sh = ((*vB).w[i]) & 0x1f; + (*vS).w[i] = (*vA).w[i] << sh; + } + PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); + + +# +# Vector Splat instructions, 6-140 ... 6-145 +# + +0.4,6.VS,11.UIMM,16.VB,21.524:VX:av:vspltb %VD, %VB, %UIMM:Vector Splat Byte + int i; + unsigned8 b; + b = (*vB).b[AV_BINDEX(UIMM & 0xf)]; + for (i = 0; i < 16; i++) + (*vS).b[i] = b; + PPC_INSN_VR(VS_BITMASK, VB_BITMASK); + +0.4,6.VS,11.UIMM,16.VB,21.588:VX:av:vsplth %VD, %VB, %UIMM:Vector Splat Half Word + int i; + unsigned16 h; + h = (*vB).h[AV_HINDEX(UIMM & 0x7)]; + for (i = 0; i < 8; i++) + (*vS).h[i] = h; + PPC_INSN_VR(VS_BITMASK, VB_BITMASK); + +0.4,6.VS,11.SIMM,16.0,21.780:VX:av:vspltisb %VD, %SIMM:Vector Splat Immediate Signed Byte + int i; + signed8 b = SIMM; + /* manual 5-bit signed extension */ + if (b & 0x10) + b -= 0x20; + for (i = 0; i < 16; i++) + (*vS).b[i] = b; + PPC_INSN_VR(VS_BITMASK, 0); + +0.4,6.VS,11.SIMM,16.0,21.844:VX:av:vspltish %VD, %SIMM:Vector Splat Immediate Signed Half Word + int i; + signed16 h = SIMM; + /* manual 5-bit signed extension */ + if (h & 0x10) + h -= 0x20; + for (i = 0; i < 8; i++) + (*vS).h[i] = h; + PPC_INSN_VR(VS_BITMASK, 0); + +0.4,6.VS,11.SIMM,16.0,21.908:VX:av:vspltisw %VD, %SIMM:Vector Splat Immediate Signed Word + int i; + signed32 w = SIMM; + /* manual 5-bit signed extension */ + if (w & 0x10) + w -= 0x20; + for (i = 0; i < 4; i++) + (*vS).w[i] = w; + PPC_INSN_VR(VS_BITMASK, 0); + +0.4,6.VS,11.UIMM,16.VB,21.652:VX:av:vspltw %VD, %VB, %UIMM:Vector Splat Word + int i; + unsigned32 w; + w = (*vB).w[UIMM & 0x3]; + for (i = 0; i < 4; i++) + (*vS).w[i] = w; + PPC_INSN_VR(VS_BITMASK, VB_BITMASK); + + +# +# Vector Shift Right instructions, 6-146 ... 6-154 +# + +0.4,6.VS,11.VA,16.VB,21.708:VX:av:vsr %VD, %VA, %VB:Vector Shift Right + int sh, i, j, carry, new_carry; + sh = (*vB).b[0] & 7; /* don't bother checking everything */ + carry = 0; + for (j = 0; j < 4; j++) { + if (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN) + i = j; + else + i = (j + 2) % 4; + new_carry = (*vA).w[i] << (32 - sh); + (*vS).w[i] = ((*vA).w[i] >> sh) | carry; + carry = new_carry; + } + PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); + +0.4,6.VS,11.VA,16.VB,21.772:VX:av:vsrab %VD, %VA, %VB:Vector Shift Right Algebraic Byte + int i, sh; + signed16 a; + for (i = 0; i < 16; i++) { + sh = ((*vB).b[i]) & 7; + a = (signed16)(signed8)(*vA).b[i]; + (*vS).b[i] = (a >> sh) & 0xff; + } + PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); + +0.4,6.VS,11.VA,16.VB,21.836:VX:av:vsrah %VD, %VA, %VB:Vector Shift Right Algebraic Half Word + int i, sh; + signed32 a; + for (i = 0; i < 8; i++) { + sh = ((*vB).h[i]) & 0xf; + a = (signed32)(signed16)(*vA).h[i]; + (*vS).h[i] = (a >> sh) & 0xffff; + } + PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); + +0.4,6.VS,11.VA,16.VB,21.900:VX:av:vsraw %VD, %VA, %VB:Vector Shift Right Algebraic Word + int i, sh; + signed64 a; + for (i = 0; i < 4; i++) { + sh = ((*vB).w[i]) & 0xf; + a = (signed64)(signed32)(*vA).w[i]; + (*vS).w[i] = (a >> sh) & 0xffffffff; + } + PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); + +0.4,6.VS,11.VA,16.VB,21.516:VX:av:vsrb %VD, %VA, %VB:Vector Shift Right Byte + int i, sh; + for (i = 0; i < 16; i++) { + sh = ((*vB).b[i]) & 7; + (*vS).b[i] = (*vA).b[i] >> sh; + } + PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); + +0.4,6.VS,11.VA,16.VB,21.580:VX:av:vsrh %VD, %VA, %VB:Vector Shift Right Half Word + int i, sh; + for (i = 0; i < 8; i++) { + sh = ((*vB).h[i]) & 0xf; + (*vS).h[i] = (*vA).h[i] >> sh; + } + PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); + +0.4,6.VS,11.VA,16.VB,21.1100:VX:av:vsro %VD, %VA, %VB:Vector Shift Right Octet + int i, sh; + if (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN) + sh = ((*vB).b[AV_BINDEX(15)] >> 3) & 0xf; + else + sh = ((*vB).b[AV_BINDEX(0)] >> 3) & 0xf; + for (i = 0; i < 16; i++) { + if (i < sh) + (*vS).b[AV_BINDEX(i)] = 0; + else + (*vS).b[AV_BINDEX(i)] = (*vA).b[AV_BINDEX(i - sh)]; + } + PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); + +0.4,6.VS,11.VA,16.VB,21.644:VX:av:vsrw %VD, %VA, %VB:Vector Shift Right Word + int i, sh; + for (i = 0; i < 4; i++) { + sh = ((*vB).w[i]) & 0x1f; + (*vS).w[i] = (*vA).w[i] >> sh; + } + PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); + + +# +# Vector Subtract instructions, 6-155 ... 6-165 +# + +0.4,6.VS,11.VA,16.VB,21.1408:VX:av:vsubcuw %VD, %VA, %VB:Vector Subtract Carryout Unsigned Word + int i; + signed64 temp, a, b; + for (i = 0; i < 4; i++) { + a = (signed64)(unsigned32)(*vA).w[i]; + b = (signed64)(unsigned32)(*vB).w[i]; + temp = a - b; + (*vS).w[i] = ~(temp >> 32) & 1; + } + PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); + +0.4,6.VS,11.VA,16.VB,21.74:VX:av:vsubfp %VD, %VA, %VB:Vector Subtract Floating Point + int i; + unsigned32 f; + sim_fpu a, b, d; + for (i = 0; i < 4; i++) { + sim_fpu_32to (&a, (*vA).w[i]); + sim_fpu_32to (&b, (*vB).w[i]); + sim_fpu_sub (&d, &a, &b); + sim_fpu_to32 (&f, &d); + (*vS).w[i] = f; + } + PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); + +0.4,6.VS,11.VA,16.VB,21.1792:VX:av:vsubsbs %VD, %VA, %VB:Vector Subtract Signed Byte Saturate + int i, sat, tempsat; + signed16 temp; + sat = 0; + for (i = 0; i < 16; i++) { + temp = (signed16)(signed8)(*vA).b[i] - (signed16)(signed8)(*vB).b[i]; + (*vS).b[i] = altivec_signed_saturate_8(temp, &tempsat); + sat |= tempsat; + } + ALTIVEC_SET_SAT(sat); + PPC_INSN_VR_VSCR(VS_BITMASK, VA_BITMASK | VB_BITMASK); + +0.4,6.VS,11.VA,16.VB,21.1856:VX:av:vsubshs %VD, %VA, %VB:Vector Subtract Signed Half Word Saturate + int i, sat, tempsat; + signed32 temp; + sat = 0; + for (i = 0; i < 8; i++) { + temp = (signed32)(signed16)(*vA).h[i] - (signed32)(signed16)(*vB).h[i]; + (*vS).h[i] = altivec_signed_saturate_16(temp, &tempsat); + sat |= tempsat; + } + ALTIVEC_SET_SAT(sat); + PPC_INSN_VR_VSCR(VS_BITMASK, VA_BITMASK | VB_BITMASK); + +0.4,6.VS,11.VA,16.VB,21.1920:VX:av:vsubsws %VD, %VA, %VB:Vector Subtract Signed Word Saturate + int i, sat, tempsat; + signed64 temp; + sat = 0; + for (i = 0; i < 4; i++) { + temp = (signed64)(signed32)(*vA).w[i] - (signed64)(signed32)(*vB).w[i]; + (*vS).w[i] = altivec_signed_saturate_32(temp, &tempsat); + sat |= tempsat; + } + ALTIVEC_SET_SAT(sat); + PPC_INSN_VR_VSCR(VS_BITMASK, VA_BITMASK | VB_BITMASK); + +0.4,6.VS,11.VA,16.VB,21.1024:VX:av:vsububm %VD, %VA, %VB:Vector Subtract Unsigned Byte Modulo + int i; + for (i = 0; i < 16; i++) + (*vS).b[i] = (*vA).b[i] - (*vB).b[i]; + PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); + +0.4,6.VS,11.VA,16.VB,21.1536:VX:av:vsububs %VD, %VA, %VB:Vector Subtract Unsigned Byte Saturate + int i, sat, tempsat; + signed16 temp; + sat = 0; + for (i = 0; i < 16; i++) { + temp = (signed16)(unsigned8)(*vA).b[i] - (signed16)(unsigned8)(*vB).b[i]; + (*vS).b[i] = altivec_unsigned_saturate_8(temp, &tempsat); + sat |= tempsat; + } + ALTIVEC_SET_SAT(sat); + PPC_INSN_VR_VSCR(VS_BITMASK, VA_BITMASK | VB_BITMASK); + +0.4,6.VS,11.VA,16.VB,21.1088:VX:av:vsubuhm %VD, %VA, %VB:Vector Subtract Unsigned Half Word Modulo + int i; + for (i = 0; i < 8; i++) + (*vS).h[i] = ((*vA).h[i] - (*vB).h[i]) & 0xffff; + PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); + +0.4,6.VS,11.VA,16.VB,21.1600:VX:av:vsubuhs %VD, %VA, %VB:Vector Subtract Unsigned Half Word Saturate + int i, sat, tempsat; + signed32 temp; + for (i = 0; i < 8; i++) { + temp = (signed32)(unsigned16)(*vA).h[i] - (signed32)(unsigned16)(*vB).h[i]; + (*vS).h[i] = altivec_unsigned_saturate_16(temp, &tempsat); + sat |= tempsat; + } + ALTIVEC_SET_SAT(sat); + PPC_INSN_VR_VSCR(VS_BITMASK, VA_BITMASK | VB_BITMASK); + +0.4,6.VS,11.VA,16.VB,21.1152:VX:av:vsubuwm %VD, %VA, %VB:Vector Subtract Unsigned Word Modulo + int i; + for (i = 0; i < 4; i++) + (*vS).w[i] = (*vA).w[i] - (*vB).w[i]; + PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK); + +0.4,6.VS,11.VA,16.VB,21.1664:VX:av:vsubuws %VD, %VA, %VB:Vector Subtract Unsigned Word Saturate + int i, sat, tempsat; + signed64 temp; + for (i = 0; i < 4; i++) { + temp = (signed64)(unsigned32)(*vA).w[i] - (signed64)(unsigned32)(*vB).w[i]; + (*vS).w[i] = altivec_unsigned_saturate_32(temp, &tempsat); + sat |= tempsat; + } + ALTIVEC_SET_SAT(sat); + PPC_INSN_VR_VSCR(VS_BITMASK, VA_BITMASK | VB_BITMASK); + + +# +# Vector Sum instructions, 6-166 ... 6-170 +# + +0.4,6.VS,11.VA,16.VB,21.1928:VX:av:vsumsws %VD, %VA, %VB:Vector Sum Across Signed Word Saturate + int i, sat; + signed64 temp; + temp = (signed64)(signed32)(*vB).w[3]; + for (i = 0; i < 4; i++) + temp += (signed64)(signed32)(*vA).w[i]; + (*vS).w[3] = altivec_signed_saturate_32(temp, &sat); + (*vS).w[0] = (*vS).w[1] = (*vS).w[2] = 0; + ALTIVEC_SET_SAT(sat); + PPC_INSN_VR_VSCR(VS_BITMASK, VA_BITMASK | VB_BITMASK); + +0.4,6.VS,11.VA,16.VB,21.1672:VX:av:vsum2sws %VD, %VA, %VB:Vector Sum Across Partial (1/2) Signed Word Saturate + int i, j, sat, tempsat; + signed64 temp; + for (j = 0; j < 4; j += 2) { + temp = (signed64)(signed32)(*vB).w[j+1]; + temp += (signed64)(signed32)(*vA).w[j] + (signed64)(signed32)(*vA).w[j+1]; + (*vS).w[j+1] = altivec_signed_saturate_32(temp, &tempsat); + sat |= tempsat; + } + (*vS).w[0] = (*vS).w[2] = 0; + ALTIVEC_SET_SAT(sat); + PPC_INSN_VR_VSCR(VS_BITMASK, VA_BITMASK | VB_BITMASK); + +0.4,6.VS,11.VA,16.VB,21.1800:VX:av:vsum4sbs %VD, %VA, %VB:Vector Sum Across Partial (1/4) Signed Byte Saturate + int i, j, sat, tempsat; + signed64 temp; + for (j = 0; j < 4; j++) { + temp = (signed64)(signed32)(*vB).w[j]; + for (i = 0; i < 4; i++) + temp += (signed64)(signed8)(*vA).b[i+(j*4)]; + (*vS).w[j] = altivec_signed_saturate_32(temp, &tempsat); + sat |= tempsat; + } + ALTIVEC_SET_SAT(sat); + PPC_INSN_VR_VSCR(VS_BITMASK, VA_BITMASK | VB_BITMASK); + +0.4,6.VS,11.VA,16.VB,21.1608:VX:av:vsum4shs %VD, %VA, %VB:Vector Sum Across Partial (1/4) Signed Half Word Saturate + int i, j, sat, tempsat; + signed64 temp; + for (j = 0; j < 4; j++) { + temp = (signed64)(signed32)(*vB).w[j]; + for (i = 0; i < 2; i++) + temp += (signed64)(signed16)(*vA).h[i+(j*2)]; + (*vS).w[j] = altivec_signed_saturate_32(temp, &tempsat); + sat |= tempsat; + } + ALTIVEC_SET_SAT(sat); + PPC_INSN_VR_VSCR(VS_BITMASK, VA_BITMASK | VB_BITMASK); + +0.4,6.VS,11.VA,16.VB,21.1544:VX:av:vsum4ubs %VD, %VA, %VB:Vector Sum Across Partial (1/4) Unsigned Byte Saturate + int i, j, sat, tempsat; + signed64 utemp; + signed64 temp; + for (j = 0; j < 4; j++) { + utemp = (signed64)(unsigned32)(*vB).w[j]; + for (i = 0; i < 4; i++) + utemp += (signed64)(unsigned16)(*vA).b[i+(j*4)]; + temp = utemp; + (*vS).w[j] = altivec_unsigned_saturate_32(temp, &tempsat); + sat |= tempsat; + } + ALTIVEC_SET_SAT(sat); + PPC_INSN_VR_VSCR(VS_BITMASK, VA_BITMASK | VB_BITMASK); + + +# +# Vector Unpack instructions, 6-171 ... 6-176 +# + +0.4,6.VS,11.0,16.VB,21.846:VX:av:vupkhpx %VD, %VB:Vector Unpack High Pixel16 + int i; + unsigned16 h; + for (i = 0; i < 4; i++) { + h = (*vB).h[AV_HINDEX(i)]; + (*vS).w[i] = ((h & 0x8000) ? 0xff000000 : 0) + | ((h & 0x7c00) << 6) + | ((h & 0x03e0) << 3) + | ((h & 0x001f)); + } + PPC_INSN_VR(VS_BITMASK, VB_BITMASK); + +0.4,6.VS,11.0,16.VB,21.526:VX:av:vupkhsb %VD, %VB:Vector Unpack High Signed Byte + int i; + for (i = 0; i < 8; i++) + (*vS).h[AV_HINDEX(i)] = (signed16)(signed8)(*vB).b[AV_BINDEX(i)]; + PPC_INSN_VR(VS_BITMASK, VB_BITMASK); + +0.4,6.VS,11.0,16.VB,21.590:VX:av:vupkhsh %VD, %VB:Vector Unpack High Signed Half Word + int i; + for (i = 0; i < 4; i++) + (*vS).w[i] = (signed32)(signed16)(*vB).h[AV_HINDEX(i)]; + PPC_INSN_VR(VS_BITMASK, VB_BITMASK); + +0.4,6.VS,11.0,16.VB,21.974:VX:av:vupklpx %VD, %VB:Vector Unpack Low Pixel16 + int i; + unsigned16 h; + for (i = 0; i < 4; i++) { + h = (*vB).h[AV_HINDEX(i + 4)]; + (*vS).w[i] = ((h & 0x8000) ? 0xff000000 : 0) + | ((h & 0x7c00) << 6) + | ((h & 0x03e0) << 3) + | ((h & 0x001f)); + } + PPC_INSN_VR(VS_BITMASK, VB_BITMASK); + +0.4,6.VS,11.0,16.VB,21.654:VX:av:vupklsb %VD, %VB:Vector Unpack Low Signed Byte + int i; + for (i = 0; i < 8; i++) + (*vS).h[AV_HINDEX(i)] = (signed16)(signed8)(*vB).b[AV_BINDEX(i + 8)]; + PPC_INSN_VR(VS_BITMASK, VB_BITMASK); + +0.4,6.VS,11.0,16.VB,21.718:VX:av:vupklsh %VD, %VB:Vector Unpack Low Signed Half Word + int i; + for (i = 0; i < 4; i++) + (*vS).w[i] = (signed32)(signed16)(*vB).h[AV_HINDEX(i + 4)]; + PPC_INSN_VR(VS_BITMASK, VB_BITMASK); diff --git a/sim/ppc/altivec_expression.h b/sim/ppc/altivec_expression.h new file mode 100644 index 0000000..6cf2e76 --- /dev/null +++ b/sim/ppc/altivec_expression.h @@ -0,0 +1,50 @@ +/* Altivec expression macros, for PSIM, the PowerPC simulator. + + Copyright 2003 Free Software Foundation, Inc. + + Contributed by Red Hat Inc; developed under contract from Motorola. + Written by matthew green . + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +/* AltiVec macro helpers. */ + +#define ALTIVEC_SET_CR6(vS, checkone) \ +do { \ + if (checkone && ((*vS).w[0] == 0xffffffff && \ + (*vS).w[1] == 0xffffffff && \ + (*vS).w[2] == 0xffffffff && \ + (*vS).w[3] == 0xffffffff)) \ + CR_SET(6, 1 << 3); \ + else if ((*vS).w[0] == 0 && \ + (*vS).w[1] == 0 && \ + (*vS).w[2] == 0 && \ + (*vS).w[3] == 0) \ + CR_SET(6, 1 << 1); \ + else \ + CR_SET(6, 0); \ +} while (0) + +#define VSCR_SAT 0x00000001 +#define VSCR_NJ 0x00010000 + +#define ALTIVEC_SET_SAT(sat) \ +do { \ + if (sat) \ + VSCR |= VSCR_SAT; \ +} while (0) diff --git a/sim/ppc/altivec_registers.h b/sim/ppc/altivec_registers.h new file mode 100644 index 0000000..923f5c4 --- /dev/null +++ b/sim/ppc/altivec_registers.h @@ -0,0 +1,63 @@ +/* Altivec registers, for PSIM, the PowerPC simulator. + + Copyright 2003 Free Software Foundation, Inc. + + Contributed by Red Hat Inc; developed under contract from Motorola. + Written by matthew green . + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +/* Manage this as 4 32-bit entities, 8 16-bit entities or 16 8-bit + entities. */ +typedef union +{ + unsigned8 b[16]; + unsigned16 h[8]; + unsigned32 w[4]; +} vreg; + +typedef unsigned32 vscreg; + +struct altivec_regs { + /* AltiVec Registers */ + vreg vr[32]; + vscreg vscr; +}; + +/* AltiVec registers */ +#define VR(N) cpu_registers(processor)->altivec.vr[N] + +/* AltiVec vector status and control register */ +#define VSCR cpu_registers(processor)->altivec.vscr + +/* AltiVec endian helpers, wrong endian hosts vs targets need to be + sure to get the right bytes/halfs/words when the order matters. + Note that many AltiVec instructions do not depend on byte order and + work on N independant bits of data. This is only for the + instructions that actually move data around. */ + +#if (WITH_HOST_BYTE_ORDER == BIG_ENDIAN) +#define AV_BINDEX(x) ((x) & 15) +#define AV_HINDEX(x) ((x) & 7) +#else +static char endian_b2l_bindex[16] = { 3, 2, 1, 0, 7, 6, 5, 4, + 11, 10, 9, 8, 15, 14, 13, 12 }; +static char endian_b2l_hindex[16] = { 1, 0, 3, 2, 5, 4, 7, 6 }; +#define AV_BINDEX(x) endian_b2l_bindex[(x) & 15] +#define AV_HINDEX(x) endian_b2l_hindex[(x) & 7] +#endif diff --git a/sim/ppc/e500.igen b/sim/ppc/e500.igen new file mode 100644 index 0000000..f4ebfc7 --- /dev/null +++ b/sim/ppc/e500.igen @@ -0,0 +1,3348 @@ +# e500 core instructions, for PSIM, the PowerPC simulator. + +# Copyright 2003 Free Software Foundation, Inc. + +# Contributed by Red Hat Inc; developed under contract from Motorola. +# Written by matthew green . + +# This file is part of GDB. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2, or (at your option) +# any later version. + +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. + +# You should have received a copy of the GNU General Public License +# along with This program; see the file COPYING. If not, write to +# the Free Software Foundation, 59 Temple Place - Suite 330, +# Boston, MA 02111-1307, USA. + +# +# e500 Core Complex Instructions +# + +:cache:e500::signed_word *:rAh:RA:(cpu_registers(processor)->e500.gprh + RA) +:cache:e500::signed_word *:rSh:RS:(cpu_registers(processor)->e500.gprh + RS) +:cache:e500::signed_word *:rBh:RB:(cpu_registers(processor)->e500.gprh + RB) + +# Flags for model.h +::model-macro::: + #define PPC_INSN_INT_SPR(OUT_MASK, IN_MASK, SPR) \ + do { \ + if (CURRENT_MODEL_ISSUE > 0) \ + ppc_insn_int_spr(MY_INDEX, cpu_model(processor), OUT_MASK, IN_MASK, SPR); \ + } while (0) + +# Schedule an instruction that takes 2 integer register and produces a special purpose output register plus an integer output register +void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr, const unsigned32 out_mask, const unsigned32 in_mask, const unsigned nSPR + const unsigned32 int_mask = out_mask | in_mask; + model_busy *busy_ptr; + + while ((model_ptr->int_busy & int_mask) != 0 || model_ptr->spr_busy[nSPR] != 0) { + if (WITH_TRACE && ppc_trace[trace_model]) + model_trace_busy_p(model_ptr, int_mask, 0, 0, nSPR); + + model_ptr->nr_stalls_data++; + model_new_cycle(model_ptr); + } + + busy_ptr = model_wait_for_unit(index, model_ptr, &model_ptr->timing[index]); + busy_ptr->int_busy |= out_mask; + model_ptr->int_busy |= out_mask; + busy_ptr->spr_busy = nSPR; + model_ptr->spr_busy[nSPR] = 1; + busy_ptr->nr_writebacks = (PPC_ONE_BIT_SET_P(out_mask)) ? 3 : 2; + TRACE(trace_model,("Making register %s busy.\n", spr_name(nSPR))); + +# +# SPE Modulo Fractional Multiplication handling support +# +:function:e500::unsigned64:ev_multiply16_smf:signed16 a, signed16 b, int *sat + signed32 a32 = a, b32 = b, rv32; + rv32 = a * b; + *sat = (rv32 & (3<<30)) == (3<<30); + return (signed64)rv32 << 1; + +:function:e500::unsigned64:ev_multiply32_smf:signed32 a, signed32 b, int *sat + signed64 rv64, a64 = a, b64 = b; + rv64 = a64 * b64; + *sat = (rv64 & ((signed64)3<<62)) == ((signed64)3<<62); + /* Loses top sign bit. */ + return rv64 << 1; +# +# SPE Saturation handling support +# +:function:e500::signed32:ev_multiply16_ssf:signed16 a, signed16 b, int *sat + signed32 rv32; + if (a == 0xffff8000 && b == 0xffff8000) + { + rv32 = 0x7fffffffL; + * sat = 1; + return rv32; + } + else + { + signed32 a32 = a, b32 = b; + + rv32 = a * b; + * sat = (rv32 & (3<<30)) == (3<<30); + return (signed64)rv32 << 1; + } + +:function:e500::signed64:ev_multiply32_ssf:signed32 a, signed32 b, int *sat + signed64 rv64; + if (a == 0x80000000 && b == 0x80000000) + { + rv64 = 0x7fffffffffffffffLL; + * sat = 1; + return rv64; + } + else + { + signed64 a64 = a, b64 = b; + rv64 = a64 * b64; + *sat = (rv64 & ((signed64)3<<62)) == ((signed64)3<<62); + /* Loses top sign bit. */ + return rv64 << 1; + } + +# +# SPE FP handling support +# + +:function:e500::void:ev_check_guard:sim_fpu *a, int fg, int fx, cpu *processor + unsigned64 guard; + guard = sim_fpu_guard(a, 0); + if (guard & 1) + EV_SET_SPEFSCR_BITS(fg); + if (guard & ~1) + EV_SET_SPEFSCR_BITS(fx); + +:function:e500::void:booke_sim_fpu_32to:sim_fpu *dst, unsigned32 packed + sim_fpu_32to (dst, packed); + + /* Set normally unused fields to allow booke arithmetic. */ + if (dst->class == sim_fpu_class_infinity) + { + dst->normal_exp = 128; + dst->fraction = ((unsigned64)1 << 60); + } + else if (dst->class == sim_fpu_class_qnan + || dst->class == sim_fpu_class_snan) + { + dst->normal_exp = 128; + /* This is set, but without the implicit bit, so we have to or + in the implicit bit. */ + dst->fraction |= ((unsigned64)1 << 60); + } + +:function:e500::int:booke_sim_fpu_add:sim_fpu *d, sim_fpu *a, sim_fpu *b, int inv, int over, int under, cpu *processor + int invalid_operand, overflow_result, underflow_result; + int dest_exp; + + invalid_operand = 0; + overflow_result = 0; + underflow_result = 0; + + /* Treat NaN, Inf, and denorm like normal numbers, and signal invalid + operand if it hasn't already been done. */ + if (EV_IS_INFDENORMNAN (a)) + { + a->class = sim_fpu_class_number; + + EV_SET_SPEFSCR_BITS (inv); + invalid_operand = 1; + } + if (EV_IS_INFDENORMNAN (b)) + { + b->class = sim_fpu_class_number; + + if (! invalid_operand) + { + EV_SET_SPEFSCR_BITS (inv); + invalid_operand = 1; + } + } + + sim_fpu_add (d, a, b); + + dest_exp = booke_sim_fpu_exp (d); + /* If this is a denorm, force to zero, and signal underflow if + we haven't already indicated invalid operand. */ + if (dest_exp <= -127) + { + int sign = d->sign; + + *d = sim_fpu_zero; + d->sign = sign; + if (! invalid_operand) + { + EV_SET_SPEFSCR_BITS (under); + underflow_result = 1; + } + } + /* If this is Inf/NaN, force to pmax/nmax, and signal overflow if + we haven't already indicated invalid operand. */ + else if (dest_exp >= 127) + { + int sign = d->sign; + + *d = sim_fpu_max32; + d->sign = sign; + if (! invalid_operand) + { + EV_SET_SPEFSCR_BITS (over); + overflow_result = 1; + } + } + /* Destination sign is sign of operand with larger magnitude, or + the sign of the first operand if operands have the same + magnitude. Thus if the result is zero, we force it to have + the sign of the first operand. */ + else if (d->fraction == 0) + d->sign = a->sign; + + return invalid_operand || overflow_result || underflow_result; + +:function:e500::unsigned32:ev_fs_add:unsigned32 aa, unsigned32 bb, int inv, int over, int under, int fg, int fx, cpu *processor + sim_fpu a, b, d; + unsigned32 w; + int exception; + + booke_sim_fpu_32to (&a, aa); + booke_sim_fpu_32to (&b, bb); + + exception = booke_sim_fpu_add (&d, &a, &b, inv, over, under, + processor); + + sim_fpu_to32 (&w, &d); + if (! exception) + ev_check_guard(&d, fg, fx, processor); + return w; + +:function:e500::unsigned32:ev_fs_sub:unsigned32 aa, unsigned32 bb, int inv, int over, int under, int fg, int fx, cpu *processor + sim_fpu a, b, d; + unsigned32 w; + int exception; + + booke_sim_fpu_32to (&a, aa); + booke_sim_fpu_32to (&b, bb); + + /* Invert sign of second operand, and add. */ + b.sign = ! b.sign; + exception = booke_sim_fpu_add (&d, &a, &b, inv, over, under, + processor); + + sim_fpu_to32 (&w, &d); + if (! exception) + ev_check_guard(&d, fg, fx, processor); + return w; + +# sim_fpu_exp leaves the normal_exp field undefined for Inf and NaN. +# The booke algorithms require exp values, so we fake them here. +# fixme: It also apparently does the same for zero, but should not. +:function:e500::unsigned32:booke_sim_fpu_exp:sim_fpu *x + int y = sim_fpu_is (x); + if (y == SIM_FPU_IS_PZERO || y == SIM_FPU_IS_NZERO) + return 0; + else if (y == SIM_FPU_IS_SNAN || y == SIM_FPU_IS_QNAN + || y == SIM_FPU_IS_NINF || y == SIM_FPU_IS_PINF) + return 128; + else + return sim_fpu_exp (x); + +:function:e500::unsigned32:ev_fs_mul:unsigned32 aa, unsigned32 bb, int inv, int over, int under, int fg, int fx, cpu *processor + sim_fpu a, b, d; + unsigned32 w; + int sa, sb, ea, eb, ei; + sim_fpu_32to (&a, aa); + sim_fpu_32to (&b, bb); + sa = sim_fpu_sign(&a); + sb = sim_fpu_sign(&b); + ea = booke_sim_fpu_exp(&a); + eb = booke_sim_fpu_exp(&b); + ei = ea + eb + 127; + if (sim_fpu_is_zero (&a) || sim_fpu_is_zero (&b)) + w = 0; + else if (sa == sb) { + if (ei >= 254) { + w = EV_PMAX; + EV_SET_SPEFSCR_BITS(over); + } else if (ei < 1) { + d = sim_fpu_zero; + sim_fpu_to32 (&w, &d); + w &= 0x7fffffff; /* Clear sign bit. */ + } else { + goto normal_mul; + } + } else { + if (ei >= 254) { + w = EV_NMAX; + EV_SET_SPEFSCR_BITS(over); + } else if (ei < 1) { + d = sim_fpu_zero; + sim_fpu_to32 (&w, &d); + w |= 0x80000000; /* Set sign bit. */ + } else { + normal_mul: + if (EV_IS_INFDENORMNAN(&a) || EV_IS_INFDENORMNAN(&b)) + EV_SET_SPEFSCR_BITS(inv); + sim_fpu_mul (&d, &a, &b); + sim_fpu_to32 (&w, &d); + } + } + return w; + +:function:e500::unsigned32:ev_fs_div:unsigned32 aa, unsigned32 bb, int inv, int over, int under, int dbz, int fg, int fx, cpu *processor + sim_fpu a, b, d; + unsigned32 w; + int sa, sb, ea, eb, ei; + + sim_fpu_32to (&a, aa); + sim_fpu_32to (&b, bb); + sa = sim_fpu_sign(&a); + sb = sim_fpu_sign(&b); + ea = booke_sim_fpu_exp(&a); + eb = booke_sim_fpu_exp(&b); + ei = ea - eb + 127; + + /* Special cases to handle behaviour of e500 hardware. + cf case 107543. */ + if (sim_fpu_is_nan (&a) || sim_fpu_is_nan (&b) + || sim_fpu_is_zero (&a) || sim_fpu_is_zero (&b)) + { + if (sim_fpu_is_snan (&a) || sim_fpu_is_snan (&b)) + { + if (bb == 0x3f800000) + w = EV_PMAX; + else if (aa == 0x7fc00001) + w = 0x3fbffffe; + else + goto normal_div; + } + else + goto normal_div; + } + else if (sim_fpu_is_infinity (&a) && sim_fpu_is_infinity (&b)) + { + if (sa == sb) + sim_fpu_32to (&d, 0x3f800000); + else + sim_fpu_32to (&d, 0xbf800000); + sim_fpu_to32 (&w, &d); + } + else if (sa == sb) { + if (ei > 254) { + w = EV_PMAX; + EV_SET_SPEFSCR_BITS(over); + } else if (ei <= 1) { + d = sim_fpu_zero; + sim_fpu_to32 (&w, &d); + w &= 0x7fffffff; /* Clear sign bit. */ + } else { + goto normal_div; + } + } else { + if (ei > 254) { + w = EV_NMAX; + EV_SET_SPEFSCR_BITS(over); + } else if (ei <= 1) { + d = sim_fpu_zero; + sim_fpu_to32 (&w, &d); + w |= 0x80000000; /* Set sign bit. */ + } else { + normal_div: + if (EV_IS_INFDENORMNAN(&a) || EV_IS_INFDENORMNAN(&b)) + EV_SET_SPEFSCR_BITS(inv); + if (sim_fpu_is_zero (&b)) + { + if (sim_fpu_is_zero (&a)) + EV_SET_SPEFSCR_BITS(dbz); + else + EV_SET_SPEFSCR_BITS(inv); + w = sa ? EV_NMAX : EV_PMAX; + } + else + { + sim_fpu_div (&d, &a, &b); + sim_fpu_to32 (&w, &d); + ev_check_guard(&d, fg, fx, processor); + } + } + } + return w; + + +# +# A.2.7 Integer SPE Simple Instructions +# + +0.4,6.RS,11.RA,16.RB,21.512:X:e500:evaddw %RS,%RA,%RB:Vector Add Word + unsigned32 w1, w2; + w1 = *rBh + *rAh; + w2 = *rB + *rA; + EV_SET_REG2(*rSh, *rS, w1, w2); + //printf("evaddw: *rSh = %08x; *rS = %08x; w1 = %08x w2 = %08x\n", *rSh, *rS, w1, w2); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); + +0.4,6.RS,11.IMM,16.RB,21.514:X:e500:evaddiw %RS,%RB,%IMM:Vector Add Immediate Word + unsigned32 w1, w2; + w1 = *rBh + IMM; + w2 = *rB + IMM; + EV_SET_REG2(*rSh, *rS, w1, w2); + //printf("evaddiw: *rSh = %08x; *rS = %08x; w1 = %08x w2 = %08x\n", *rSh, *rS, w1, w2); + PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0); + +0.4,6.RS,11.RA,16.RB,21.516:X:e500:evsubfw %RS,%RA,%RB:Vector Subtract from Word + unsigned32 w1, w2; + w1 = *rBh - *rAh; + w2 = *rB - *rA; + EV_SET_REG2(*rSh, *rS, w1, w2); + //printf("evsubfw: *rSh = %08x; *rS = %08x; w1 = %08x w2 = %08x\n", *rSh, *rS, w1, w2); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); + +0.4,6.RS,11.IMM,16.RB,21.518:X:e500:evsubifw %RS,%RB,%IMM:Vector Subtract Immediate from Word + unsigned32 w1, w2; + w1 = *rBh - IMM; + w2 = *rB - IMM; + EV_SET_REG2(*rSh, *rS, w1, w2); + //printf("evsubifw: *rSh = %08x; *rS = %08x; IMM = %d\n", *rSh, *rS, IMM); + PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0); + +0.4,6.RS,11.RA,16.0,21.520:X:e500:evabs %RS,%RA:Vector Absolute Value + signed32 w1, w2; + w1 = *rAh; + if (w1 < 0 && w1 != 0x80000000) + w1 = -w1; + w2 = *rA; + if (w2 < 0 && w2 != 0x80000000) + w2 = -w2; + EV_SET_REG2(*rSh, *rS, w1, w2); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0); + +0.4,6.RS,11.RA,16.0,21.521:X:e500:evneg %RS,%RA:Vector Negate + signed32 w1, w2; + w1 = *rAh; + /* the negative most negative number is the most negative number */ + if (w1 != 0x80000000) + w1 = -w1; + w2 = *rA; + if (w2 != 0x80000000) + w2 = -w2; + EV_SET_REG2(*rSh, *rS, w1, w2); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0); + +0.4,6.RS,11.RA,16.0,21.522:X:e500:evextsb %RS,%RA:Vector Extend Signed Byte + unsigned64 w1, w2; + w1 = *rAh & 0xff; + if (w1 & 0x80) + w1 |= 0xffffff00; + w2 = *rA & 0xff; + if (w2 & 0x80) + w2 |= 0xffffff00; + EV_SET_REG2(*rSh, *rS, w1, w2); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK , 0); + +0.4,6.RS,11.RA,16.0,21.523:X:e500:evextsb %RS,%RA:Vector Extend Signed Half Word + unsigned64 w1, w2; + w1 = *rAh & 0xffff; + if (w1 & 0x8000) + w1 |= 0xffff0000; + w2 = *rA & 0xffff; + if (w2 & 0x8000) + w2 |= 0xffff0000; + EV_SET_REG2(*rSh, *rS, w1, w2); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0); + +0.4,6.RS,11.RA,16.RB,21.529:X:e500:evand %RS,%RA,%RB:Vector AND + unsigned32 w1, w2; + w1 = *rBh & *rAh; + w2 = *rB & *rA; + EV_SET_REG2(*rSh, *rS, w1, w2); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); + +0.4,6.RS,11.RA,16.RB,21.535:X:e500:evor %RS,%RA,%RB:Vector OR + unsigned32 w1, w2; + w1 = *rBh | *rAh; + w2 = *rB | *rA; + EV_SET_REG2(*rSh, *rS, w1, w2); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); + +0.4,6.RS,11.RA,16.RB,21.534:X:e500:evxor %RS,%RA,%RB:Vector XOR + unsigned32 w1, w2; + w1 = *rBh ^ *rAh; + w2 = *rB ^ *rA; + EV_SET_REG2(*rSh, *rS, w1, w2); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); + +0.4,6.RS,11.RA,16.RB,21.542:X:e500:evnand %RS,%RA,%RB:Vector NAND + unsigned32 w1, w2; + w1 = ~(*rBh & *rAh); + w2 = ~(*rB & *rA); + EV_SET_REG2(*rSh, *rS, w1, w2); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); + +0.4,6.RS,11.RA,16.RB,21.536:X:e500:evnor %RS,%RA,%RB:Vector NOR + unsigned32 w1, w2; + w1 = ~(*rBh | *rAh); + w2 = ~(*rB | *rA); + EV_SET_REG2(*rSh, *rS, w1, w2); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); + +0.4,6.RS,11.RA,16.RB,21.537:X:e500:eveqv %RS,%RA,%RB:Vector Equivalent + unsigned32 w1, w2; + w1 = (~*rBh) ^ *rAh; + w2 = (~*rB) ^ *rA; + EV_SET_REG2(*rSh, *rS, w1, w2); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); + +0.4,6.RS,11.RA,16.RB,21.530:X:e500:evandc %RS,%RA,%RB:Vector AND with Compliment + unsigned32 w1, w2; + w1 = (~*rBh) & *rAh; + w2 = (~*rB) & *rA; + EV_SET_REG2(*rSh, *rS, w1, w2); + //printf("evandc: *rSh = %08x; *rS = %08x\n", *rSh, *rS); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); + +0.4,6.RS,11.RA,16.RB,21.539:X:e500:evorc %RS,%RA,%RB:Vector OR with Compliment + unsigned32 w1, w2; + w1 = (~*rBh) | *rAh; + w2 = (~*rB) | *rA; + EV_SET_REG2(*rSh, *rS, w1, w2); + //printf("evorc: *rSh = %08x; *rS = %08x\n", *rSh, *rS); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); + +0.4,6.RS,11.RA,16.RB,21.552:X:e500:evrlw %RS,%RA,%RB:Vector Rotate Left Word + unsigned32 nh, nl, w1, w2; + nh = *rBh & 0x1f; + nl = *rB & 0x1f; + w1 = ((unsigned32)*rAh) << nh | ((unsigned32)*rAh) >> (32 - nh); + w2 = ((unsigned32)*rA) << nl | ((unsigned32)*rA) >> (32 - nl); + EV_SET_REG2(*rSh, *rS, w1, w2); + //printf("evrlw: nh %d nl %d *rSh = %08x; *rS = %08x\n", nh, nl, *rSh, *rS); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); + +0.4,6.RS,11.RA,16.UIMM,21.554:X:e500:evrlwi %RS,%RA,%UIMM:Vector Rotate Left Word Immediate + unsigned32 w1, w2, imm; + imm = (unsigned32)UIMM; + w1 = ((unsigned32)*rAh) << imm | ((unsigned32)*rAh) >> (32 - imm); + w2 = ((unsigned32)*rA) << imm | ((unsigned32)*rA) >> (32 - imm); + EV_SET_REG2(*rSh, *rS, w1, w2); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0); + +0.4,6.RS,11.RA,16.RB,21.548:X:e500:evslw %RS,%RA,%RB:Vector Shift Left Word + unsigned32 nh, nl, w1, w2; + nh = *rBh & 0x1f; + nl = *rB & 0x1f; + w1 = ((unsigned32)*rAh) << nh; + w2 = ((unsigned32)*rA) << nl; + EV_SET_REG2(*rSh, *rS, w1, w2); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); + +0.4,6.RS,11.RA,16.UIMM,21.550:X:e500:evslwi %RS,%RA,%UIMM:Vector Shift Left Word Immediate + unsigned32 w1, w2, imm = UIMM; + w1 = ((unsigned32)*rAh) << imm; + w2 = ((unsigned32)*rA) << imm; + EV_SET_REG2(*rSh, *rS, w1, w2); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0); + +0.4,6.RS,11.RA,16.RB,21.545:X:e500:evsrws %RS,%RA,%RB:Vector Shift Right Word Signed + signed32 w1, w2; + unsigned32 nh, nl; + nh = *rBh & 0x1f; + nl = *rB & 0x1f; + w1 = ((signed32)*rAh) >> nh; + w2 = ((signed32)*rA) >> nl; + EV_SET_REG2(*rSh, *rS, w1, w2); + //printf("evsrws: nh %d nl %d *rSh = %08x; *rS = %08x\n", nh, nl, *rSh, *rS); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); + +0.4,6.RS,11.RA,16.RB,21.544:X:e500:evsrwu %RS,%RA,%RB:Vector Shift Right Word Unsigned + unsigned32 w1, w2, nh, nl; + nh = *rBh & 0x1f; + nl = *rB & 0x1f; + w1 = ((unsigned32)*rAh) >> nh; + w2 = ((unsigned32)*rA) >> nl; + EV_SET_REG2(*rSh, *rS, w1, w2); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); + +0.4,6.RS,11.RA,16.UIMM,21.547:X:e500:evsrwis %RS,%RA,%UIMM:Vector Shift Right Word Immediate Signed + signed32 w1, w2; + unsigned32 imm = UIMM; + w1 = ((signed32)*rAh) >> imm; + w2 = ((signed32)*rA) >> imm; + EV_SET_REG2(*rSh, *rS, w1, w2); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0); + +0.4,6.RS,11.RA,16.UIMM,21.546:X:e500:evsrwiu %RS,%RA,%UIMM:Vector Shift Right Word Immediate Unsigned + unsigned32 w1, w2, imm = UIMM; + w1 = ((unsigned32)*rAh) >> imm; + w2 = ((unsigned32)*rA) >> imm; + EV_SET_REG2(*rSh, *rS, w1, w2); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0); + +0.4,6.RS,11.RA,16.0,21.525:X:e500:evcntlzw %RS,%RA:Vector Count Leading Zeros Word + unsigned32 w1, w2, mask, c1, c2; + for (c1 = 0, mask = 0x80000000, w1 = *rAh; + !(w1 & mask) && mask != 0; mask >>= 1) + c1++; + for (c2 = 0, mask = 0x80000000, w2 = *rA; + !(w2 & mask) && mask != 0; mask >>= 1) + c2++; + EV_SET_REG2(*rSh, *rS, c1, c2); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0); + +0.4,6.RS,11.RA,16.0,21.526:X:e500:evcntlsw %RS,%RA:Vector Count Leading Sign Bits Word + unsigned32 w1, w2, mask, sign_bit, c1, c2; + for (c1 = 0, mask = 0x80000000, w1 = *rAh, sign_bit = w1 & mask; + ((w1 & mask) == sign_bit) && mask != 0; + mask >>= 1, sign_bit >>= 1) + c1++; + for (c2 = 0, mask = 0x80000000, w2 = *rA, sign_bit = w2 & mask; + ((w2 & mask) == sign_bit) && mask != 0; + mask >>= 1, sign_bit >>= 1) + c2++; + EV_SET_REG2(*rSh, *rS, c1, c2); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0); + +0.4,6.RS,11.RA,16.0,21.524:X:e500:evrndw %RS,%RA:Vector Round Word + unsigned32 w1, w2; + w1 = ((unsigned32)*rAh + 0x8000) & 0xffff0000; + w2 = ((unsigned32)*rA + 0x8000) & 0xffff0000; + EV_SET_REG2(*rSh, *rS, w1, w2); + //printf("evrndw: *rSh = %08x; *rS = %08x\n", *rSh, *rS); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0); + +0.4,6.RS,11.RA,16.RB,21.556:X:e500:evmergehi %RS,%RA,%RB:Vector Merge Hi + unsigned32 w1, w2; + w1 = *rAh; + w2 = *rBh; + EV_SET_REG2(*rSh, *rS, w1, w2); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); + +0.4,6.RS,11.RA,16.RB,21.557:X:e500:evmergelo %RS,%RA,%RB:Vector Merge Low + unsigned32 w1, w2; + w1 = *rA; + w2 = *rB; + EV_SET_REG2(*rSh, *rS, w1, w2); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); + +0.4,6.RS,11.RA,16.RB,21.559:X:e500:evmergelohi %RS,%RA,%RB:Vector Merge Low Hi + unsigned32 w1, w2; + w1 = *rA; + w2 = *rBh; + EV_SET_REG2(*rSh, *rS, w1, w2); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); + +0.4,6.RS,11.RA,16.RB,21.558:X:e500:evmergehilo %RS,%RA,%RB:Vector Merge Hi Low + unsigned32 w1, w2; + w1 = *rAh; + w2 = *rB; + EV_SET_REG2(*rSh, *rS, w1, w2); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); + +0.4,6.RS,11.SIMM,16.0,21.553:X:e500:evsplati %RS,%SIMM:Vector Splat Immediate + unsigned32 w; + w = SIMM & 0x1f; + if (w & 0x10) + w |= 0xffffffe0; + EV_SET_REG2(*rSh, *rS, w, w); + PPC_INSN_INT(RS_BITMASK, 0, 0); + +0.4,6.RS,11.SIMM,16.0,21.555:X:e500:evsplatfi %RS,%SIMM:Vector Splat Fractional Immediate + unsigned32 w; + w = SIMM << 27; + EV_SET_REG2(*rSh, *rS, w, w); + PPC_INSN_INT(RS_BITMASK, 0, 0); + +0.4,6.BF,9.0,11.RA,16.RB,21.561:X:e500:evcmpgts %BF,%RA,%RB:Vector Compare Greater Than Signed + signed32 ah, al, bh, bl; + int w, ch, cl; + ah = *rAh; + al = *rA; + bh = *rBh; + bl = *rB; + if (ah > bh) + ch = 1; + else + ch = 0; + if (al > bl) + cl = 1; + else + cl = 0; + w = ch << 3 | cl << 2 | (ch | cl) << 1 | (ch & cl); + CR_SET(BF, w); + PPC_INSN_INT_CR(0, RA_BITMASK | RB_BITMASK, BF_BITMASK); + +0.4,6.BF,9.0,11.RA,16.RB,21.560:X:e500:evcmpgtu %BF,%RA,%RB:Vector Compare Greater Than Unsigned + unsigned32 ah, al, bh, bl; + int w, ch, cl; + ah = *rAh; + al = *rA; + bh = *rBh; + bl = *rB; + if (ah > bh) + ch = 1; + else + ch = 0; + if (al > bl) + cl = 1; + else + cl = 0; + w = ch << 3 | cl << 2 | (ch | cl) << 1 | (ch & cl); + CR_SET(BF, w); + PPC_INSN_INT_CR(0, RA_BITMASK | RB_BITMASK, BF_BITMASK); + +0.4,6.BF,9.0,11.RA,16.RB,21.563:X:e500:evcmplts %BF,%RA,%RB:Vector Compare Less Than Signed + signed32 ah, al, bh, bl; + int w, ch, cl; + ah = *rAh; + al = *rA; + bh = *rBh; + bl = *rB; + if (ah < bh) + ch = 1; + else + ch = 0; + if (al < bl) + cl = 1; + else + cl = 0; + w = ch << 3 | cl << 2 | (ch | cl) << 1 | (ch & cl); + CR_SET(BF, w); + PPC_INSN_INT_CR(0, RA_BITMASK | RB_BITMASK, BF_BITMASK); + +0.4,6.BF,9.0,11.RA,16.RB,21.562:X:e500:evcmpltu %BF,%RA,%RB:Vector Compare Less Than Unsigned + unsigned32 ah, al, bh, bl; + int w, ch, cl; + ah = *rAh; + al = *rA; + bh = *rBh; + bl = *rB; + if (ah < bh) + ch = 1; + else + ch = 0; + if (al < bl) + cl = 1; + else + cl = 0; + w = ch << 3 | cl << 2 | (ch | cl) << 1 | (ch & cl); + CR_SET(BF, w); + PPC_INSN_INT_CR(0, RA_BITMASK | RB_BITMASK, BF_BITMASK); + +0.4,6.BF,9.0,11.RA,16.RB,21.564:X:e500:evcmpeq %BF,%RA,%RB:Vector Compare Equal + unsigned32 ah, al, bh, bl; + int w, ch, cl; + ah = *rAh; + al = *rA; + bh = *rBh; + bl = *rB; + if (ah == bh) + ch = 1; + else + ch = 0; + if (al == bl) + cl = 1; + else + cl = 0; + w = ch << 3 | cl << 2 | (ch | cl) << 1 | (ch & cl); + CR_SET(BF, w); + //printf("evcmpeq: ch %d cl %d BF %d, CR is now %08x\n", ch, cl, BF, CR); + PPC_INSN_INT_CR(0, RA_BITMASK | RB_BITMASK, BF_BITMASK); + +0.4,6.RS,11.RA,16.RB,21.79,29.CRFS:X:e500:evsel %RS,%RA,%RB,%CRFS:Vector Select + unsigned32 w1, w2; + int cr; + cr = CR_FIELD(CRFS); + if (cr & 8) + w1 = *rAh; + else + w1 = *rBh; + if (cr & 4) + w2 = *rA; + else + w2 = *rB; + EV_SET_REG2(*rSh, *rS, w1, w2); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); + +0.4,6.RS,11.RA,16.RB,21.527:X:e500:brinc %RS,%RA,%RB:Bit Reversed Increment + unsigned32 w1, w2, a, d, mask; + mask = (*rB) & 0xffff; + a = (*rA) & 0xffff; + d = EV_BITREVERSE16(1 + EV_BITREVERSE16(a | ~mask)); + *rS = ((*rA) & 0xffff0000) | (d & 0xffff); + //printf("brinc: *rS = %08x\n", *rS); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); + +# +# A.2.8 Integer SPE Complex Instructions +# + +0.4,6.RS,11.RA,16.RB,21.1031:EVX:e500:evmhossf %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Saturate Fractional + signed16 al, ah, bl, bh; + signed32 tl, th; + int movl, movh; + + al = (signed16) EV_LOHALF (*rA); + ah = (signed16) EV_LOHALF (*rAh); + bl = (signed16) EV_LOHALF (*rB); + bh = (signed16) EV_LOHALF (*rBh); + tl = ev_multiply16_ssf (al, bl, &movl); + th = ev_multiply16_ssf (ah, bh, &movh); + EV_SET_REG2 (*rSh, *rS, EV_SATURATE (movh, 0x7fffffff, th), + EV_SATURATE (movl, 0x7fffffff, tl)); + EV_SET_SPEFSCR_OV (movl, movh); + PPC_INSN_INT_SPR (RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); + +0.4,6.RS,11.RA,16.RB,21.1063:EVX:e500:evmhossfa %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Saturate Fractional Accumulate + signed16 al, ah, bl, bh; + signed32 tl, th; + int movl, movh; + + al = (signed16) EV_LOHALF (*rA); + ah = (signed16) EV_LOHALF (*rAh); + bl = (signed16) EV_LOHALF (*rB); + bh = (signed16) EV_LOHALF (*rBh); + tl = ev_multiply16_ssf (al, bl, &movl); + th = ev_multiply16_ssf (ah, bh, &movh); + EV_SET_REG2 (*rSh, *rS, EV_SATURATE (movh, 0x7fffffff, th), + EV_SATURATE (movl, 0x7fffffff, tl)); + EV_SET_SPEFSCR_OV (movl, movh); + PPC_INSN_INT_SPR (RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); + +0.4,6.RS,11.RA,16.RB,21.1039:EVX:e500:evmhosmf %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Modulo Fractional + signed16 al, ah, bl, bh; + signed32 tl, th; + int dummy; + + al = (signed16) EV_LOHALF (*rA); + ah = (signed16) EV_LOHALF (*rAh); + bl = (signed16) EV_LOHALF (*rB); + bh = (signed16) EV_LOHALF (*rBh); + tl = ev_multiply16_smf (al, bl, & dummy); + th = ev_multiply16_smf (ah, bh, & dummy); + EV_SET_REG2 (*rSh, *rS, th, tl); + PPC_INSN_INT (RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); + +0.4,6.RS,11.RA,16.RB,21.1071:EVX:e500:evmhosmfa %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Modulo Fractional Accumulate + signed32 al, ah, bl, bh; + signed32 tl, th; + int dummy; + + al = (signed16) EV_LOHALF (*rA); + ah = (signed16) EV_LOHALF (*rAh); + bl = (signed16) EV_LOHALF (*rB); + bh = (signed16) EV_LOHALF (*rBh); + tl = ev_multiply16_smf (al, bl, & dummy); + th = ev_multiply16_smf (ah, bh, & dummy); + EV_SET_REG2_ACC (*rSh, *rS, th, tl); + PPC_INSN_INT (RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); + +0.4,6.RS,11.RA,16.RB,21.1037:EVX:e500:evmhosmi %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Modulo Integer + signed32 al, ah, bl, bh, tl, th; + al = (signed32)(signed16)EV_LOHALF(*rA); + ah = (signed32)(signed16)EV_LOHALF(*rAh); + bl = (signed32)(signed16)EV_LOHALF(*rB); + bh = (signed32)(signed16)EV_LOHALF(*rBh); + tl = al * bl; + th = ah * bh; + EV_SET_REG2(*rSh, *rS, th, tl); + //printf("evmhosmi: *rSh = %08x; *rS = %08x\n", *rSh, *rS); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); + +0.4,6.RS,11.RA,16.RB,21.1069:EVX:e500:evmhosmia %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Modulo Integer Accumulate + signed32 al, ah, bl, bh, tl, th; + al = (signed32)(signed16)EV_LOHALF(*rA); + ah = (signed32)(signed16)EV_LOHALF(*rAh); + bl = (signed32)(signed16)EV_LOHALF(*rB); + bh = (signed32)(signed16)EV_LOHALF(*rBh); + tl = al * bl; + th = ah * bh; + EV_SET_REG2_ACC(*rSh, *rS, th, tl); + //printf("evmhosmia: ACC = %08x; *rSh = %08x; *rS = %08x\n", ACC, *rSh, *rS); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); + +0.4,6.RS,11.RA,16.RB,21.1036:EVX:e500:evmhoumi %RS,%RA,%RB:Vector Multiply Half Words Odd Unsigned Modulo Integer + unsigned32 al, ah, bl, bh, tl, th; + al = (unsigned32)(unsigned16)EV_LOHALF(*rA); + ah = (unsigned32)(unsigned16)EV_LOHALF(*rAh); + bl = (unsigned32)(unsigned16)EV_LOHALF(*rB); + bh = (unsigned32)(unsigned16)EV_LOHALF(*rBh); + tl = al * bl; + th = ah * bh; + EV_SET_REG2(*rSh, *rS, th, tl); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); + +0.4,6.RS,11.RA,16.RB,21.1068:EVX:e500:evmhoumia %RS,%RA,%RB:Vector Multiply Half Words Odd Unsigned Modulo Integer Accumulate + unsigned32 al, ah, bl, bh, tl, th; + al = (unsigned32)(unsigned16)EV_LOHALF(*rA); + ah = (unsigned32)(unsigned16)EV_LOHALF(*rAh); + bl = (unsigned32)(unsigned16)EV_LOHALF(*rB); + bh = (unsigned32)(unsigned16)EV_LOHALF(*rBh); + tl = al * bl; + th = ah * bh; + EV_SET_REG2_ACC(*rSh, *rS, th, tl); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); + +0.4,6.RS,11.RA,16.RB,21.1027:EVX:e500:evmhessf %RS,%RA,%RB:Vector Multiply Half Words Even Signed Saturate Fractional + signed16 al, ah, bl, bh; + signed32 tl, th; + int movl, movh; + + al = (signed16) EV_HIHALF (*rA); + ah = (signed16) EV_HIHALF (*rAh); + bl = (signed16) EV_HIHALF (*rB); + bh = (signed16) EV_HIHALF (*rBh); + tl = ev_multiply16_ssf (al, bl, &movl); + th = ev_multiply16_ssf (ah, bh, &movh); + EV_SET_REG2 (*rSh, *rS, EV_SATURATE (movh, 0x7fffffff, th), + EV_SATURATE (movl, 0x7fffffff, tl)); + EV_SET_SPEFSCR_OV (movl, movh); + PPC_INSN_INT_SPR (RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); + +0.4,6.RS,11.RA,16.RB,21.1059:EVX:e500:evmhessfa %RS,%RA,%RB:Vector Multiply Half Words Even Signed Saturate Fractional Accumulate + signed16 al, ah, bl, bh; + signed32 tl, th; + int movl, movh; + + al = (signed16) EV_HIHALF (*rA); + ah = (signed16) EV_HIHALF (*rAh); + bl = (signed16) EV_HIHALF (*rB); + bh = (signed16) EV_HIHALF (*rBh); + tl = ev_multiply16_ssf (al, bl, &movl); + th = ev_multiply16_ssf (ah, bh, &movh); + EV_SET_REG2_ACC (*rSh, *rS, EV_SATURATE (movh, 0x7fffffff, th), + EV_SATURATE (movl, 0x7fffffff, tl)); + EV_SET_SPEFSCR_OV (movl, movh); + PPC_INSN_INT_SPR (RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); + +0.4,6.RS,11.RA,16.RB,21.1035:EVX:e500:evmhesmf %RS,%RA,%RB:Vector Multiply Half Words Even Signed Modulo Fractional + signed16 al, ah, bl, bh; + signed64 tl, th; + int movl, movh; + + al = (signed16) EV_HIHALF (*rA); + ah = (signed16) EV_HIHALF (*rAh); + bl = (signed16) EV_HIHALF (*rB); + bh = (signed16) EV_HIHALF (*rBh); + tl = ev_multiply16_smf (al, bl, &movl); + th = ev_multiply16_smf (ah, bh, &movh); + EV_SET_REG2 (*rSh, *rS, th, tl); + EV_SET_SPEFSCR_OV (movl, movh); + PPC_INSN_INT_SPR (RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); + +0.4,6.RS,11.RA,16.RB,21.1067:EVX:e500:evmhesmfa %RS,%RA,%RB:Vector Multiply Half Words Even Signed Modulo Fractional Accumulate + signed16 al, ah, bl, bh; + signed32 tl, th; + int dummy; + + al = (signed16) EV_HIHALF (*rA); + ah = (signed16) EV_HIHALF (*rAh); + bl = (signed16) EV_HIHALF (*rB); + bh = (signed16) EV_HIHALF (*rBh); + tl = ev_multiply16_smf (al, bl, & dummy); + th = ev_multiply16_smf (ah, bh, & dummy); + EV_SET_REG2_ACC (*rSh, *rS, th, tl); + PPC_INSN_INT (RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); + +0.4,6.RS,11.RA,16.RB,21.1033:EVX:e500:evmhesmi %RS,%RA,%RB:Vector Multiply Half Words Even Signed Modulo Integer + signed16 al, ah, bl, bh; + signed32 tl, th; + + al = (signed16) EV_HIHALF (*rA); + ah = (signed16) EV_HIHALF (*rAh); + bl = (signed16) EV_HIHALF (*rB); + bh = (signed16) EV_HIHALF (*rBh); + tl = al * bl; + th = ah * bh; + EV_SET_REG2 (*rSh, *rS, th, tl); + PPC_INSN_INT (RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); + +0.4,6.RS,11.RA,16.RB,21.1065:EVX:e500:evmhesmia %RS,%RA,%RB:Vector Multiply Half Words Even Signed Modulo Integer Accumulate + signed32 al, ah, bl, bh, tl, th; + al = (signed32)(signed16)EV_HIHALF(*rA); + ah = (signed32)(signed16)EV_HIHALF(*rAh); + bl = (signed32)(signed16)EV_HIHALF(*rB); + bh = (signed32)(signed16)EV_HIHALF(*rBh); + tl = al * bl; + th = ah * bh; + EV_SET_REG2_ACC(*rSh, *rS, th, tl); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); + +0.4,6.RS,11.RA,16.RB,21.1032:EVX:e500:evmheumi %RS,%RA,%RB:Vector Multiply Half Words Even Unsigned Modulo Integer + unsigned32 al, ah, bl, bh, tl, th; + al = (unsigned32)(unsigned16)EV_HIHALF(*rA); + ah = (unsigned32)(unsigned16)EV_HIHALF(*rAh); + bl = (unsigned32)(unsigned16)EV_HIHALF(*rB); + bh = (unsigned32)(unsigned16)EV_HIHALF(*rBh); + tl = al * bl; + th = ah * bh; + EV_SET_REG2(*rSh, *rS, th, tl); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); + +0.4,6.RS,11.RA,16.RB,21.1064:EVX:e500:evmheumia %RS,%RA,%RB:Vector Multiply Half Words Even Unsigned Modulo Integer Accumulate + unsigned32 al, ah, bl, bh, tl, th; + al = (unsigned32)(unsigned16)EV_HIHALF(*rA); + ah = (unsigned32)(unsigned16)EV_HIHALF(*rAh); + bl = (unsigned32)(unsigned16)EV_HIHALF(*rB); + bh = (unsigned32)(unsigned16)EV_HIHALF(*rBh); + tl = al * bl; + th = ah * bh; + EV_SET_REG2_ACC(*rSh, *rS, th, tl); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); + +0.4,6.RS,11.RA,16.RB,21.1287:EVX:e500:evmhossfaaw %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Saturate Fractional and Accumulate into Words + signed16 al, ah, bl, bh; + signed32 t1, t2; + signed64 tl, th; + int movl, movh, ovl, ovh; + + al = (signed16) EV_LOHALF (*rA); + ah = (signed16) EV_LOHALF (*rAh); + bl = (signed16) EV_LOHALF (*rB); + bh = (signed16) EV_LOHALF (*rBh); + t1 = ev_multiply16_ssf (ah, bh, &movh); + t2 = ev_multiply16_ssf (al, bl, &movl); + th = EV_ACCHIGH + EV_SATURATE (movh, 0x7fffffff, t1); + tl = EV_ACCLOW + EV_SATURATE (movl, 0x7fffffff, t2); + ovh = EV_SAT_P_S32 (th); + ovl = EV_SAT_P_S32 (tl); + EV_SET_REG2_ACC (*rSh, *rS, EV_SATURATE_ACC (ovh, th, 0x80000000, 0x7fffffff, th), + EV_SATURATE_ACC (ovl, tl, 0x80000000, 0x7fffffff, tl)); + EV_SET_SPEFSCR_OV (movl | ovl, movh | ovh); + PPC_INSN_INT_SPR (RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); + +0.4,6.RS,11.RA,16.RB,21.1285:EVX:e500:evmhossiaaw %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Saturate Integer and Accumulate into Words + signed32 al, ah, bl, bh; + signed64 t1, t2, tl, th; + int ovl, ovh; + al = (signed32)(signed16)EV_LOHALF(*rA); + ah = (signed32)(signed16)EV_LOHALF(*rAh); + bl = (signed32)(signed16)EV_LOHALF(*rB); + bh = (signed32)(signed16)EV_LOHALF(*rBh); + t1 = ah * bh; + t2 = al * bl; + th = EV_ACCHIGH + t1; + tl = EV_ACCLOW + t2; + ovh = EV_SAT_P_S32(th); + ovl = EV_SAT_P_S32(tl); + EV_SET_REG2_ACC(*rSh, *rS, EV_SATURATE_ACC(ovh, th, 0x80000000, 0x7fffffff, th), + EV_SATURATE_ACC(ovl, tl, 0x80000000, 0x7fffffff, tl)); + //printf("evmhossiaaw: ovh %d ovl %d al %d ah %d bl %d bh %d t1 %qd t2 %qd tl %qd th %qd\n", ovh, ovl, al, ah, bl, bh, t1, t2, tl, th); + //printf("evmhossiaaw: ACC = %08x.%08x; *rSh = %08x; *rS = %08x\n", (int)(ACC >> 32), (int)ACC, *rSh, *rS); + EV_SET_SPEFSCR_OV(ovl, ovh); + PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); + +0.4,6.RS,11.RA,16.RB,21.1295:EVX:e500:evmhosmfaaw %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Modulo Fractional and Accumulate into Words + signed32 al, ah, bl, bh; + signed64 t1, t2, tl, th; + al = (signed32)(signed16)EV_LOHALF(*rA); + ah = (signed32)(signed16)EV_LOHALF(*rAh); + bl = (signed32)(signed16)EV_LOHALF(*rB); + bh = (signed32)(signed16)EV_LOHALF(*rBh); + t1 = ((signed64)ah * bh) << 1; + t2 = ((signed64)al * bl) << 1; + th = EV_ACCHIGH + (t1 & 0xffffffff); + tl = EV_ACCLOW + (t2 & 0xffffffff); + EV_SET_REG2_ACC(*rSh, *rS, th & 0xffffffff, tl & 0xffffffff); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); + +0.4,6.RS,11.RA,16.RB,21.1293:EVX:e500:evmhosmiaaw %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Modulo Integer and Accumulate into Words + signed32 al, ah, bl, bh; + signed64 t1, t2, tl, th; + al = (signed32)(signed16)EV_LOHALF(*rA); + ah = (signed32)(signed16)EV_LOHALF(*rAh); + bl = (signed32)(signed16)EV_LOHALF(*rB); + bh = (signed32)(signed16)EV_LOHALF(*rBh); + t1 = ah * bh; + t2 = al * bl; + th = EV_ACCHIGH + t1; + tl = EV_ACCLOW + t2; + EV_SET_REG2_ACC(*rSh, *rS, th & 0xffffffff, tl & 0xffffffff); + //printf("evmhosmiaaw: al %d ah %d bl %d bh %d t1 %qd t2 %qd tl %qd th %qd\n", al, ah, bl, bh, t1, t2, tl, th); + //printf("evmhosmiaaw: ACC = %08x.%08x; *rSh = %08x; *rS = %08x\n", (int)(ACC >> 32), (int)ACC, *rSh, *rS); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); + +0.4,6.RS,11.RA,16.RB,21.1284:EVX:e500:evmhousiaaw %RS,%RA,%RB:Vector Multiply Half Words Odd Unsigned Saturate Integer and Accumulate into Words + unsigned32 al, ah, bl, bh; + unsigned64 t1, t2; + signed64 tl, th; + int ovl, ovh; + al = (unsigned32)(unsigned16)EV_LOHALF(*rA); + ah = (unsigned32)(unsigned16)EV_LOHALF(*rAh); + bl = (unsigned32)(unsigned16)EV_LOHALF(*rB); + bh = (unsigned32)(unsigned16)EV_LOHALF(*rBh); + t1 = ah * bh; + t2 = al * bl; + th = (signed64)EV_ACCHIGH + (signed64)t1; + tl = (signed64)EV_ACCLOW + (signed64)t2; + ovh = EV_SAT_P_U32(th); + ovl = EV_SAT_P_U32(tl); + EV_SET_REG2_ACC(*rSh, *rS, EV_SATURATE_ACC(ovh, th, 0, 0xffffffff, th), + EV_SATURATE_ACC(ovl, tl, 0, 0xffffffff, tl)); + //printf("evmhousiaaw: al %u ah %u bl %u bh %u t1 %qu t2 %qu tl %qu th %qu\n", al, ah, bl, bh, t1, t2, tl, th); + //printf("evmhousiaaw: ACC = %08x.%08x; *rSh = %08x; *rS = %08x\n", (int)(ACC >> 32), (int)ACC, *rSh, *rS); + EV_SET_SPEFSCR_OV(ovl, ovh); + PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); + +0.4,6.RS,11.RA,16.RB,21.1292:EVX:e500:evmhoumiaaw %RS,%RA,%RB:Vector Multiply Half Words Odd Unsigned Modulo Integer and Accumulate into Words + unsigned32 al, ah, bl, bh; + unsigned32 t1, t2; + signed64 tl, th; + al = (unsigned32)(unsigned16)EV_LOHALF(*rA); + ah = (unsigned32)(unsigned16)EV_LOHALF(*rAh); + bl = (unsigned32)(unsigned16)EV_LOHALF(*rB); + bh = (unsigned32)(unsigned16)EV_LOHALF(*rBh); + t1 = ah * bh; + t2 = al * bl; + th = EV_ACCHIGH + t1; + tl = EV_ACCLOW + t2; + EV_SET_REG2_ACC(*rSh, *rS, th & 0xffffffff, tl & 0xffffffff); + //printf("evmhoumiaaw: al %u ah %u bl %u bh %u t1 %qu t2 %qu tl %qu th %qu\n", al, ah, bl, bh, t1, t2, tl, th); + //printf("evmhoumiaaw: ACC = %08x.%08x; *rSh = %08x; *rS = %08x\n", (int)(ACC >> 32), (int)ACC, *rSh, *rS); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); + +0.4,6.RS,11.RA,16.RB,21.1283:EVX:e500:evmhessfaaw %RS,%RA,%RB:Vector Multiply Half Words Even Signed Saturate Fractional and Accumulate into Words + signed16 al, ah, bl, bh; + signed32 t1, t2; + signed64 tl, th; + int movl, movh, ovl, ovh; + + al = (signed16) EV_HIHALF (*rA); + ah = (signed16) EV_HIHALF (*rAh); + bl = (signed16) EV_HIHALF (*rB); + bh = (signed16) EV_HIHALF (*rBh); + t1 = ev_multiply16_ssf (ah, bh, &movh); + t2 = ev_multiply16_ssf (al, bl, &movl); + th = EV_ACCHIGH + EV_SATURATE (movh, 0x7fffffff, t1); + tl = EV_ACCLOW + EV_SATURATE (movl, 0x7fffffff, t2); + ovh = EV_SAT_P_S32 (th); + ovl = EV_SAT_P_S32 (tl); + EV_SET_REG2_ACC (*rSh, *rS, EV_SATURATE_ACC (ovh, th, 0x80000000, 0x7fffffff, th), + EV_SATURATE_ACC (ovl, tl, 0x80000000, 0x7fffffff, tl)); + EV_SET_SPEFSCR_OV (movl | ovl, movh | ovh); + PPC_INSN_INT_SPR (RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); + +0.4,6.RS,11.RA,16.RB,21.1281:EVX:e500:evmhessiaaw %RS,%RA,%RB:Vector Multiply Half Words Even Signed Saturate Integer and Accumulate into Words + signed32 al, ah, bl, bh; + signed64 t1, t2, tl, th; + int ovl, ovh; + al = (signed32)(signed16)EV_HIHALF(*rA); + ah = (signed32)(signed16)EV_HIHALF(*rAh); + bl = (signed32)(signed16)EV_HIHALF(*rB); + bh = (signed32)(signed16)EV_HIHALF(*rBh); + t1 = ah * bh; + t2 = al * bl; + th = EV_ACCHIGH + t1; + tl = EV_ACCLOW + t2; + ovh = EV_SAT_P_S32(th); + ovl = EV_SAT_P_S32(tl); + EV_SET_REG2_ACC(*rSh, *rS, EV_SATURATE_ACC(ovh, th, 0x80000000, 0x7fffffff, th), + EV_SATURATE_ACC(ovl, tl, 0x80000000, 0x7fffffff, tl)); + //printf("evmhessiaaw: ovh %d ovl %d al %d ah %d bl %d bh %d t1 %qd t2 %qd tl %qd th %qd\n", ovh, ovl, al, ah, bl, bh, t1, t2, tl, th); + //printf("evmhessiaaw: ACC = %08x.%08x; *rSh = %08x; *rS = %08x\n", (int)(ACC >> 32), (int)ACC, *rSh, *rS); + EV_SET_SPEFSCR_OV(ovl, ovh); + PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); + +0.4,6.RS,11.RA,16.RB,21.1291:EVX:e500:evmhesmfaaw %RS,%RA,%RB:Vector Multiply Half Words Even Signed Modulo Fractional and Accumulate into Words + signed16 al, ah, bl, bh; + signed32 t1, t2, th, tl; + int dummy; + + al = (signed16)EV_HIHALF(*rA); + ah = (signed16)EV_HIHALF(*rAh); + bl = (signed16)EV_HIHALF(*rB); + bh = (signed16)EV_HIHALF(*rBh); + t1 = ev_multiply16_smf (ah, bh, &dummy); + t2 = ev_multiply16_smf (al, bl, &dummy); + th = EV_ACCHIGH + t1; + tl = EV_ACCLOW + t2; + EV_SET_REG2_ACC(*rSh, *rS, th, tl); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); + +0.4,6.RS,11.RA,16.RB,21.1289:EVX:e500:evmhesmiaaw %RS,%RA,%RB:Vector Multiply Half Words Even Signed Modulo Integer and Accumulate into Words + signed32 al, ah, bl, bh; + signed64 t1, t2, tl, th; + al = (signed32)(signed16)EV_HIHALF(*rA); + ah = (signed32)(signed16)EV_HIHALF(*rAh); + bl = (signed32)(signed16)EV_HIHALF(*rB); + bh = (signed32)(signed16)EV_HIHALF(*rBh); + t1 = ah * bh; + t2 = al * bl; + th = EV_ACCHIGH + t1; + tl = EV_ACCLOW + t2; + EV_SET_REG2_ACC(*rSh, *rS, th & 0xffffffff, tl & 0xffffffff); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); + +0.4,6.RS,11.RA,16.RB,21.1280:EVX:e500:evmheusiaaw %RS,%RA,%RB:Vector Multiply Half Words Even Unsigned Saturate Integer and Accumulate into Words + unsigned32 al, ah, bl, bh; + unsigned64 t1, t2; + signed64 tl, th; + int ovl, ovh; + al = (unsigned32)(unsigned16)EV_HIHALF(*rA); + ah = (unsigned32)(unsigned16)EV_HIHALF(*rAh); + bl = (unsigned32)(unsigned16)EV_HIHALF(*rB); + bh = (unsigned32)(unsigned16)EV_HIHALF(*rBh); + t1 = ah * bh; + t2 = al * bl; + th = (signed64)EV_ACCHIGH + (signed64)t1; + tl = (signed64)EV_ACCLOW + (signed64)t2; + ovh = EV_SAT_P_U32(th); + ovl = EV_SAT_P_U32(tl); + EV_SET_REG2_ACC(*rSh, *rS, EV_SATURATE_ACC(ovh, th, 0, 0xffffffff, th), + EV_SATURATE_ACC(ovl, tl, 0, 0xffffffff, tl)); + EV_SET_SPEFSCR_OV(ovl, ovh); + PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); + +0.4,6.RS,11.RA,16.RB,21.1288:EVX:e500:evmheumiaaw %RS,%RA,%RB:Vector Multiply Half Words Even Unsigned Modulo Integer and Accumulate into Words + unsigned32 al, ah, bl, bh; + unsigned32 t1, t2; + unsigned64 tl, th; + al = (unsigned32)(unsigned16)EV_HIHALF(*rA); + ah = (unsigned32)(unsigned16)EV_HIHALF(*rAh); + bl = (unsigned32)(unsigned16)EV_HIHALF(*rB); + bh = (unsigned32)(unsigned16)EV_HIHALF(*rBh); + t1 = ah * bh; + t2 = al * bl; + th = EV_ACCHIGH + t1; + tl = EV_ACCLOW + t2; + EV_SET_REG2_ACC(*rSh, *rS, th & 0xffffffff, tl & 0xffffffff); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); + + +0.4,6.RS,11.RA,16.RB,21.1415:EVX:e500:evmhossfanw %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Saturate Fractional and Accumulate Negative into Words + signed16 al, ah, bl, bh; + signed32 t1, t2; + signed64 tl, th; + int movl, movh, ovl, ovh; + + al = (signed16) EV_LOHALF (*rA); + ah = (signed16) EV_LOHALF (*rAh); + bl = (signed16) EV_LOHALF (*rB); + bh = (signed16) EV_LOHALF (*rBh); + t1 = ev_multiply16_ssf (ah, bh, &movh); + t2 = ev_multiply16_ssf (al, bl, &movl); + th = EV_ACCHIGH - EV_SATURATE (movh, 0x7fffffff, t1); + tl = EV_ACCLOW - EV_SATURATE (movl, 0x7fffffff, t2); + ovh = EV_SAT_P_S32 (th); + ovl = EV_SAT_P_S32 (tl); + EV_SET_REG2_ACC (*rSh, *rS, EV_SATURATE_ACC (ovh, th, 0x80000000, 0x7fffffff, th), + EV_SATURATE_ACC (ovl, tl, 0x80000000, 0x7fffffff, tl)); + EV_SET_SPEFSCR_OV (movl | ovl, movh | ovh); + PPC_INSN_INT_SPR (RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); + +0.4,6.RS,11.RA,16.RB,21.1413:EVX:e500:evmhossianw %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Saturate Integer and Accumulate Negative into Words + signed32 al, ah, bl, bh; + signed64 t1, t2, tl, th; + int ovl, ovh; + al = (signed32)(signed16)EV_LOHALF(*rA); + ah = (signed32)(signed16)EV_LOHALF(*rAh); + bl = (signed32)(signed16)EV_LOHALF(*rB); + bh = (signed32)(signed16)EV_LOHALF(*rBh); + t1 = ah * bh; + t2 = al * bl; + th = EV_ACCHIGH - t1; + tl = EV_ACCLOW - t2; + ovh = EV_SAT_P_S32(th); + ovl = EV_SAT_P_S32(tl); + EV_SET_REG2_ACC(*rSh, *rS, EV_SATURATE_ACC(ovh, th, 0x80000000, 0x7fffffff, th), + EV_SATURATE_ACC(ovl, tl, 0x80000000, 0x7fffffff, tl)); + EV_SET_SPEFSCR_OV(ovl, ovh); + //printf("evmhossianw: ACC = %08x; *rSh = %08x; *rS = %08x\n", ACC, *rSh, *rS); + PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); + +0.4,6.RS,11.RA,16.RB,21.1423:EVX:e500:evmhosmfanw %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Modulo Fractional and Accumulate Negative into Words + signed32 al, ah, bl, bh; + signed64 t1, t2, tl, th; + al = (signed32)(signed16)EV_LOHALF(*rA); + ah = (signed32)(signed16)EV_LOHALF(*rAh); + bl = (signed32)(signed16)EV_LOHALF(*rB); + bh = (signed32)(signed16)EV_LOHALF(*rBh); + t1 = ((signed64)ah * bh) << 1; + t2 = ((signed64)al * bl) << 1; + th = EV_ACCHIGH - (t1 & 0xffffffff); + tl = EV_ACCLOW - (t2 & 0xffffffff); + EV_SET_REG2_ACC(*rSh, *rS, th & 0xffffffff, tl & 0xffffffff); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); + +0.4,6.RS,11.RA,16.RB,21.1421:EVX:e500:evmhosmianw %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Modulo Integer and Accumulate Negative into Words + signed32 al, ah, bl, bh; + signed64 t1, t2, tl, th; + al = (signed32)(signed16)EV_LOHALF(*rA); + ah = (signed32)(signed16)EV_LOHALF(*rAh); + bl = (signed32)(signed16)EV_LOHALF(*rB); + bh = (signed32)(signed16)EV_LOHALF(*rBh); + t1 = ah * bh; + t2 = al * bl; + th = EV_ACCHIGH - t1; + tl = EV_ACCLOW - t2; + EV_SET_REG2_ACC(*rSh, *rS, th & 0xffffffff, tl & 0xffffffff); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); + +0.4,6.RS,11.RA,16.RB,21.1412:EVX:e500:evmhousianw %RS,%RA,%RB:Vector Multiply Half Words Odd Unsigned Saturate Integer and Accumulate Negative into Words + unsigned32 al, ah, bl, bh; + unsigned64 t1, t2; + signed64 tl, th; + int ovl, ovh; + al = (unsigned32)(unsigned16)EV_LOHALF(*rA); + ah = (unsigned32)(unsigned16)EV_LOHALF(*rAh); + bl = (unsigned32)(unsigned16)EV_LOHALF(*rB); + bh = (unsigned32)(unsigned16)EV_LOHALF(*rBh); + t1 = ah * bh; + t2 = al * bl; + th = (signed64)EV_ACCHIGH - (signed64)t1; + tl = (signed64)EV_ACCLOW - (signed64)t2; + ovl = EV_SAT_P_U32(tl); + ovh = EV_SAT_P_U32(th); + EV_SET_REG2_ACC(*rSh, *rS, EV_SATURATE_ACC(ovh, th, 0, 0xffffffff, th), + EV_SATURATE_ACC(ovl, tl, 0, 0xffffffff, tl)); + //printf("evmhousianw: ovh %d ovl %d al %d ah %d bl %d bh %d t1 %qd t2 %qd tl %qd th %qd\n", ovh, ovl, al, ah, bl, bh, t1, t2, tl, th); + //printf("evmoussianw: ACC = %08x.%08x; *rSh = %08x; *rS = %08x\n", (int)(ACC >> 32), (int)ACC, *rSh, *rS); + EV_SET_SPEFSCR_OV(ovl, ovh); + PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); + +0.4,6.RS,11.RA,16.RB,21.1420:EVX:e500:evmhoumianw %RS,%RA,%RB:Vector Multiply Half Words Odd Unsigned Modulo Integer and Accumulate Negative into Words + unsigned32 al, ah, bl, bh; + unsigned32 t1, t2; + unsigned64 tl, th; + al = (unsigned32)(unsigned16)EV_LOHALF(*rA); + ah = (unsigned32)(unsigned16)EV_LOHALF(*rAh); + bl = (unsigned32)(unsigned16)EV_LOHALF(*rB); + bh = (unsigned32)(unsigned16)EV_LOHALF(*rBh); + t1 = ah * bh; + t2 = al * bl; + th = EV_ACCHIGH - t1; + tl = EV_ACCLOW - t2; + EV_SET_REG2_ACC(*rSh, *rS, th & 0xffffffff, tl & 0xffffffff); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); + +0.4,6.RS,11.RA,16.RB,21.1411:EVX:e500:evmhessfanw %RS,%RA,%RB:Vector Multiply Half Words Even Signed Saturate Fractional and Accumulate Negative into Words + signed16 al, ah, bl, bh; + signed32 t1, t2; + signed64 tl, th; + int movl, movh, ovl, ovh; + + al = (signed16) EV_HIHALF (*rA); + ah = (signed16) EV_HIHALF (*rAh); + bl = (signed16) EV_HIHALF (*rB); + bh = (signed16) EV_HIHALF (*rBh); + t1 = ev_multiply16_ssf (ah, bh, &movh); + t2 = ev_multiply16_ssf (al, bl, &movl); + th = EV_ACCHIGH - EV_SATURATE (movh, 0x7fffffff, t1); + tl = EV_ACCLOW - EV_SATURATE (movl, 0x7fffffff, t2); + ovh = EV_SAT_P_S32 (th); + ovl = EV_SAT_P_S32 (tl); + EV_SET_REG2_ACC (*rSh, *rS, EV_SATURATE_ACC (ovh, th, 0x80000000, 0x7fffffff, th), + EV_SATURATE_ACC (ovl, tl, 0x80000000, 0x7fffffff, tl)); + EV_SET_SPEFSCR_OV (movl | ovl, movh | ovh); + PPC_INSN_INT_SPR (RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); + +0.4,6.RS,11.RA,16.RB,21.1409:EVX:e500:evmhessianw %RS,%RA,%RB:Vector Multiply Half Words Even Signed Saturate Integer and Accumulate Negative into Words + signed32 al, ah, bl, bh; + signed64 t1, t2, tl, th; + int ovl, ovh; + al = (signed32)(signed16)EV_HIHALF(*rA); + ah = (signed32)(signed16)EV_HIHALF(*rAh); + bl = (signed32)(signed16)EV_HIHALF(*rB); + bh = (signed32)(signed16)EV_HIHALF(*rBh); + t1 = ah * bh; + t2 = al * bl; + th = EV_ACCHIGH - t1; + tl = EV_ACCLOW - t2; + ovh = EV_SAT_P_S32(th); + ovl = EV_SAT_P_S32(tl); + EV_SET_REG2_ACC(*rSh, *rS, EV_SATURATE_ACC(ovh, th, 0x80000000, 0x7fffffff, th), + EV_SATURATE_ACC(ovl, tl, 0x80000000, 0x7fffffff, tl)); + EV_SET_SPEFSCR_OV(ovl, ovh); + PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); + +0.4,6.RS,11.RA,16.RB,21.1419:EVX:e500:evmhesmfanw %RS,%RA,%RB:Vector Multiply Half Words Even Signed Modulo Fractional and Accumulate Negative into Words + signed32 al, ah, bl, bh; + signed64 t1, t2, tl, th; + al = (unsigned32)(unsigned16)EV_HIHALF(*rA); + ah = (unsigned32)(unsigned16)EV_HIHALF(*rAh); + bl = (unsigned32)(unsigned16)EV_HIHALF(*rB); + bh = (unsigned32)(unsigned16)EV_HIHALF(*rBh); + t1 = ((signed64)ah * bh) << 1; + t2 = ((signed64)al * bl) << 1; + th = EV_ACCHIGH - (t1 & 0xffffffff); + tl = EV_ACCLOW - (t2 & 0xffffffff); + EV_SET_REG2_ACC(*rSh, *rS, th & 0xffffffff, tl & 0xffffffff); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); + +0.4,6.RS,11.RA,16.RB,21.1417:EVX:e500:evmhesmianw %RS,%RA,%RB:Vector Multiply Half Words Even Signed Modulo Integer and Accumulate Negative into Words + signed32 al, ah, bl, bh; + signed64 t1, t2, tl, th; + al = (signed32)(signed16)EV_HIHALF(*rA); + ah = (signed32)(signed16)EV_HIHALF(*rAh); + bl = (signed32)(signed16)EV_HIHALF(*rB); + bh = (signed32)(signed16)EV_HIHALF(*rBh); + t1 = ah * bh; + t2 = al * bl; + th = EV_ACCHIGH - t1; + tl = EV_ACCLOW - t2; + EV_SET_REG2_ACC(*rSh, *rS, th & 0xffffffff, tl & 0xffffffff); + //printf("evmhesmianw: al %d ah %d bl %d bh %d t1 %qd t2 %qd tl %qd th %qd\n", al, ah, bl, bh, t1, t2, tl, th); + //printf("evmhesmianw: ACC = %08x.%08x; *rSh = %08x; *rS = %08x\n", (int)(ACC >> 32), (int)ACC, *rSh, *rS); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); + +0.4,6.RS,11.RA,16.RB,21.1408:EVX:e500:evmheusianw %RS,%RA,%RB:Vector Multiply Half Words Even Unsigned Saturate Integer and Accumulate Negative into Words + unsigned32 al, ah, bl, bh; + unsigned64 t1, t2; + signed64 tl, th; + int ovl, ovh; + al = (unsigned32)(unsigned16)EV_HIHALF(*rA); + ah = (unsigned32)(unsigned16)EV_HIHALF(*rAh); + bl = (unsigned32)(unsigned16)EV_HIHALF(*rB); + bh = (unsigned32)(unsigned16)EV_HIHALF(*rBh); + t1 = ah * bh; + t2 = al * bl; + th = (signed64)EV_ACCHIGH - (signed64)t1; + tl = (signed64)EV_ACCLOW - (signed64)t2; + ovl = EV_SAT_P_U32(tl); + ovh = EV_SAT_P_U32(th); + EV_SET_REG2_ACC(*rSh, *rS, EV_SATURATE_ACC(ovh, th, 0, 0xffffffff, th), + EV_SATURATE_ACC(ovl, tl, 0, 0xffffffff, tl)); + //printf("evmheusianw: ovh %d ovl %d al %u ah %u bl %u bh %u t1 %qu t2 %qu tl %qd th %qd\n", ovh, ovl, al, ah, bl, bh, t1, t2, tl, th); + //printf("evmheusianw: ACC = %08x.%08x; *rSh = %08x; *rS = %08x\n", (int)(ACC >> 32), (int)ACC, *rSh, *rS); + EV_SET_SPEFSCR_OV(ovl, ovh); + PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); + +0.4,6.RS,11.RA,16.RB,21.1416:EVX:e500:evmheumianw %RS,%RA,%RB:Vector Multiply Half Words Even Unsigned Modulo Integer and Accumulate Negative into Words + unsigned32 al, ah, bl, bh; + unsigned32 t1, t2; + unsigned64 tl, th; + al = (unsigned32)(unsigned16)EV_HIHALF(*rA); + ah = (unsigned32)(unsigned16)EV_HIHALF(*rAh); + bl = (unsigned32)(unsigned16)EV_HIHALF(*rB); + bh = (unsigned32)(unsigned16)EV_HIHALF(*rBh); + t1 = ah * bh; + t2 = al * bl; + th = EV_ACCHIGH - t1; + tl = EV_ACCLOW - t2; + EV_SET_REG2_ACC(*rSh, *rS, th & 0xffffffff, tl & 0xffffffff); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); + +0.4,6.RS,11.RA,16.RB,21.1327:EVX:e500:evmhogsmfaa %RS,%RA,%RB:Multiply Half Words Odd Guarded Signed Modulo Fractional and Accumulate + signed32 a, b; + signed64 t1, t2; + a = (signed32)(signed16)EV_LOHALF(*rA); + b = (signed32)(signed16)EV_LOHALF(*rB); + t1 = EV_MUL16_SSF(a, b); + if (t1 & ((unsigned64)1 << 32)) + t1 |= 0xfffffffe00000000; + t2 = ACC + t1; + EV_SET_REG1_ACC(*rSh, *rS, t2); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); + +0.4,6.RS,11.RA,16.RB,21.1325:EVX:e500:evmhogsmiaa %RS,%RA,%RB:Multiply Half Words Odd Guarded Signed Modulo Integer and Accumulate + signed32 a, b; + signed64 t1, t2; + a = (signed32)(signed16)EV_LOHALF(*rA); + b = (signed32)(signed16)EV_LOHALF(*rB); + t1 = (signed64)a * (signed64)b; + t2 = (signed64)ACC + t1; + EV_SET_REG1_ACC(*rSh, *rS, t2); + //printf("evmhogsmiaa: a %d b %d t1 %qd t2 %qd\n", a, b, t1, t2); + //printf("evmhogsmiaa: ACC = %08x.%08x; *rSh = %08x; *rS = %08x\n", (int)(ACC >> 32), (int)ACC, *rSh, *rS); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); + +0.4,6.RS,11.RA,16.RB,21.1324:EVX:e500:evmhogumiaa %RS,%RA,%RB:Multiply Half Words Odd Guarded Unsigned Modulo Integer and Accumulate + unsigned32 a, b; + unsigned64 t1, t2; + a = (unsigned32)(unsigned16)EV_LOHALF(*rA); + b = (unsigned32)(unsigned16)EV_LOHALF(*rB); + t1 = a * b; + t2 = ACC + t1; + EV_SET_REG1_ACC(*rSh, *rS, t2); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); + +0.4,6.RS,11.RA,16.RB,21.1323:EVX:e500:evmhegsmfaa %RS,%RA,%RB:Multiply Half Words Even Guarded Signed Modulo Fractional and Accumulate + signed32 a, b; + signed64 t1, t2; + a = (signed32)(signed16)EV_HIHALF(*rA); + b = (signed32)(signed16)EV_HIHALF(*rB); + t1 = EV_MUL16_SSF(a, b); + if (t1 & ((unsigned64)1 << 32)) + t1 |= 0xfffffffe00000000; + t2 = ACC + t1; + EV_SET_REG1_ACC(*rSh, *rS, t2); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); + +0.4,6.RS,11.RA,16.RB,21.1321:EVX:e500:evmhegsmiaa %RS,%RA,%RB:Multiply Half Words Even Guarded Signed Modulo Integer and Accumulate + signed32 a, b; + signed64 t1, t2; + a = (signed32)(signed16)EV_HIHALF(*rA); + b = (signed32)(signed16)EV_HIHALF(*rB); + t1 = (signed64)(a * b); + t2 = ACC + t1; + EV_SET_REG1_ACC(*rSh, *rS, t2); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); + +0.4,6.RS,11.RA,16.RB,21.1320:EVX:e500:evmhegumiaa %RS,%RA,%RB:Multiply Half Words Even Guarded Unsigned Modulo Integer and Accumulate + unsigned32 a, b; + unsigned64 t1, t2; + a = (unsigned32)(unsigned16)EV_HIHALF(*rA); + b = (unsigned32)(unsigned16)EV_HIHALF(*rB); + t1 = a * b; + t2 = ACC + t1; + EV_SET_REG1_ACC(*rSh, *rS, t2); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); + + +0.4,6.RS,11.RA,16.RB,21.1455:EVX:e500:evmhogsmfan %RS,%RA,%RB:Multiply Half Words Odd Guarded Signed Modulo Fractional and Accumulate Negative + signed32 a, b; + signed64 t1, t2; + a = (signed32)(signed16)EV_LOHALF(*rA); + b = (signed32)(signed16)EV_LOHALF(*rB); + t1 = EV_MUL16_SSF(a, b); + if (t1 & ((unsigned64)1 << 32)) + t1 |= 0xfffffffe00000000; + t2 = ACC - t1; + EV_SET_REG1_ACC(*rSh, *rS, t2); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); + +0.4,6.RS,11.RA,16.RB,21.1453:EVX:e500:evmhogsmian %RS,%RA,%RB:Multiply Half Words Odd Guarded Signed Modulo Integer and Accumulate Negative + signed32 a, b; + signed64 t1, t2; + a = (signed32)(signed16)EV_LOHALF(*rA); + b = (signed32)(signed16)EV_LOHALF(*rB); + t1 = (signed64)a * (signed64)b; + t2 = ACC - t1; + EV_SET_REG1_ACC(*rSh, *rS, t2); + //printf("evmhogsmian: a %d b %d t1 %qd t2 %qd\n", a, b, t1, t2); + //printf("evmhogsmian: ACC = %08x.%08x; *rSh = %08x; *rS = %08x\n", (int)(ACC >> 32), (int)ACC, *rSh, *rS); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); + +0.4,6.RS,11.RA,16.RB,21.1452:EVX:e500:evmhogumian %RS,%RA,%RB:Multiply Half Words Odd Guarded Unsigned Modulo Integer and Accumulate Negative + unsigned32 a, b; + unsigned64 t1, t2; + a = (unsigned32)(unsigned16)EV_LOHALF(*rA); + b = (unsigned32)(unsigned16)EV_LOHALF(*rB); + t1 = (unsigned64)a * (unsigned64)b; + t2 = ACC - t1; + EV_SET_REG1_ACC(*rSh, *rS, t2); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); + +0.4,6.RS,11.RA,16.RB,21.1451:EVX:e500:evmhegsmfan %RS,%RA,%RB:Multiply Half Words Even Guarded Signed Modulo Fractional and Accumulate Negative + signed32 a, b; + signed64 t1, t2; + a = (signed32)(signed16)EV_HIHALF(*rA); + b = (signed32)(signed16)EV_HIHALF(*rB); + t1 = EV_MUL16_SSF(a, b); + if (t1 & ((unsigned64)1 << 32)) + t1 |= 0xfffffffe00000000; + t2 = ACC - t1; + EV_SET_REG1_ACC(*rSh, *rS, t2); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); + +0.4,6.RS,11.RA,16.RB,21.1449:EVX:e500:evmhegsmian %RS,%RA,%RB:Multiply Half Words Even Guarded Signed Modulo Integer and Accumulate Negative + signed32 a, b; + signed64 t1, t2; + a = (signed32)(signed16)EV_HIHALF(*rA); + b = (signed32)(signed16)EV_HIHALF(*rB); + t1 = (signed64)a * (signed64)b; + t2 = ACC - t1; + EV_SET_REG1_ACC(*rSh, *rS, t2); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); + +0.4,6.RS,11.RA,16.RB,21.1448:EVX:e500:evmhegumian %RS,%RA,%RB:Multiply Half Words Even Guarded Unsigned Modulo Integer and Accumulate Negative + unsigned32 a, b; + unsigned64 t1, t2; + a = (unsigned32)(unsigned16)EV_HIHALF(*rA); + b = (unsigned32)(unsigned16)EV_HIHALF(*rB); + t1 = (unsigned64)a * (unsigned64)b; + t2 = ACC - t1; + EV_SET_REG1_ACC(*rSh, *rS, t2); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); + + +0.4,6.RS,11.RA,16.RB,21.1095:EVX:e500:evmwhssf %RS,%RA,%RB:Vector Multiply Word High Signed Saturate Fractional + signed32 al, ah, bl, bh; + signed64 t1, t2; + int movl, movh; + al = *rA; + ah = *rAh; + bl = *rB; + bh = *rBh; + t1 = ev_multiply32_ssf(al, bl, &movl); + t2 = ev_multiply32_ssf(ah, bh, &movh); + EV_SET_REG2(*rSh, *rS, EV_SATURATE(movh, 0x7fffffff, t2 >> 32), + EV_SATURATE(movl, 0x7fffffff, t1 >> 32)); + EV_SET_SPEFSCR_OV(movl, movh); + PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); + +0.4,6.RS,11.RA,16.RB,21.1127:EVX:e500:evmwhssfa %RS,%RA,%RB:Vector Multiply Word High Signed Saturate Fractional and Accumulate + signed32 al, ah, bl, bh; + signed64 t1, t2; + int movl, movh; + al = *rA; + ah = *rAh; + bl = *rB; + bh = *rBh; + t1 = ev_multiply32_ssf(al, bl, &movl); + t2 = ev_multiply32_ssf(ah, bh, &movh); + EV_SET_REG2_ACC(*rSh, *rS, EV_SATURATE(movh, 0x7fffffff, t2 >> 32), + EV_SATURATE(movl, 0x7fffffff, t1 >> 32)); + EV_SET_SPEFSCR_OV(movl, movh); + PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); + +0.4,6.RS,11.RA,16.RB,21.1103:EVX:e500:evmwhsmf %RS,%RA,%RB:Vector Multiply Word High Signed Modulo Fractional + signed32 al, ah, bl, bh; + signed64 t1, t2; + al = *rA; + ah = *rAh; + bl = *rB; + bh = *rBh; + t1 = EV_MUL32_SSF(al, bl); + t2 = EV_MUL32_SSF(ah, bh); + EV_SET_REG2(*rSh, *rS, t2 >> 32, t1 >> 32); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); + +0.4,6.RS,11.RA,16.RB,21.1135:EVX:e500:evmwhsmfa %RS,%RA,%RB:Vector Multiply Word High Signed Modulo Fractional and Accumulate + signed32 al, ah, bl, bh; + signed64 t1, t2; + al = *rA; + ah = *rAh; + bl = *rB; + bh = *rBh; + t1 = EV_MUL32_SSF(al, bl); + t2 = EV_MUL32_SSF(ah, bh); + EV_SET_REG2_ACC(*rSh, *rS, t2 >> 32, t1 >> 32); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); + +0.4,6.RS,11.RA,16.RB,21.1101:EVX:e500:evmwhsmi %RS,%RA,%RB:Vector Multiply Word High Signed Modulo Integer + signed32 al, ah, bl, bh; + signed64 t1, t2; + al = *rA; + ah = *rAh; + bl = *rB; + bh = *rBh; + t1 = (signed64)al * (signed64)bl; + t2 = (signed64)ah * (signed64)bh; + EV_SET_REG2(*rSh, *rS, t2 >> 32, t1 >> 32); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); + +0.4,6.RS,11.RA,16.RB,21.1133:EVX:e500:evmwhsmia %RS,%RA,%RB:Vector Multiply Word High Signed Modulo Integer and Accumulate + signed32 al, ah, bl, bh; + signed64 t1, t2; + al = *rA; + ah = *rAh; + bl = *rB; + bh = *rBh; + t1 = (signed64)al * (signed64)bl; + t2 = (signed64)ah * (signed64)bh; + EV_SET_REG2_ACC(*rSh, *rS, t2 >> 32, t1 >> 32); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); + +0.4,6.RS,11.RA,16.RB,21.1100:EVX:e500:evmwhumi %RS,%RA,%RB:Vector Multiply Word High Unsigned Modulo Integer + unsigned32 al, ah, bl, bh; + unsigned64 t1, t2; + al = *rA; + ah = *rAh; + bl = *rB; + bh = *rBh; + t1 = (unsigned64)al * (unsigned64)bl; + t2 = (unsigned64)ah * (unsigned64)bh; + EV_SET_REG2(*rSh, *rS, t2 >> 32, t1 >> 32); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); + +0.4,6.RS,11.RA,16.RB,21.1132:EVX:e500:evmwhumia %RS,%RA,%RB:Vector Multiply Word High Unsigned Modulo Integer and Accumulate + unsigned32 al, ah, bl, bh; + unsigned64 t1, t2; + al = *rA; + ah = *rAh; + bl = *rB; + bh = *rBh; + t1 = (unsigned64)al * (unsigned64)bl; + t2 = (unsigned64)ah * (unsigned64)bh; + EV_SET_REG2_ACC(*rSh, *rS, t2 >> 32, t1 >> 32); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); + + +0.4,6.RS,11.RA,16.RB,21.1091:EVX:e500:evmwlssf %RS,%RA,%RB:Vector Multiply Word Low Signed Saturate Fractional + signed32 al, ah, bl, bh; + signed64 t1, t2; + int movl, movh; + al = *rA; + ah = *rAh; + bl = *rB; + bh = *rBh; + t1 = ev_multiply32_ssf(al, bl, &movl); + t2 = ev_multiply32_ssf(ah, bh, &movh); + EV_SET_REG2(*rSh, *rS, EV_SATURATE(movh, 0xffffffff, t2), + EV_SATURATE(movl, 0xffffffff, t1)); + EV_SET_SPEFSCR_OV(movl, movh); + PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); + +0.4,6.RS,11.RA,16.RB,21.1123:EVX:e500:evmwlssfa %RS,%RA,%RB:Vector Multiply Word Low Signed Saturate Fractional and Accumulate + signed32 al, ah, bl, bh; + signed64 t1, t2; + int movl, movh; + al = *rA; + ah = *rAh; + bl = *rB; + bh = *rBh; + t1 = ev_multiply32_ssf(al, bl, &movl); + t2 = ev_multiply32_ssf(ah, bh, &movh); + EV_SET_REG2_ACC(*rSh, *rS, EV_SATURATE(movh, 0xffffffff, t2), + EV_SATURATE(movl, 0xffffffff, t1)); + EV_SET_SPEFSCR_OV(movl, movh); + PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); + +0.4,6.RS,11.RA,16.RB,21.1099:EVX:e500:evmwlsmf %RS,%RA,%RB:Vector Multiply Word Low Signed Modulo Fractional + signed32 al, ah, bl, bh; + signed64 t1, t2; + al = *rA; + ah = *rAh; + bl = *rB; + bh = *rBh; + t1 = EV_MUL32_SSF(al, bl); + t2 = EV_MUL32_SSF(ah, bh); + EV_SET_REG2(*rSh, *rS, t2, t1); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); + +0.4,6.RS,11.RA,16.RB,21.1131:EVX:e500:evmwlsmfa %RS,%RA,%RB:Vector Multiply Word Low Signed Modulo Fractional and Accumulate + signed32 al, ah, bl, bh; + signed64 t1, t2; + al = *rA; + ah = *rAh; + bl = *rB; + bh = *rBh; + t1 = EV_MUL32_SSF(al, bl); + t2 = EV_MUL32_SSF(ah, bh); + EV_SET_REG2_ACC(*rSh, *rS, t2, t1); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); + +0.4,6.RS,11.RA,16.RB,21.1096:EVX:e500:evmwlumi %RS,%RA,%RB:Vector Multiply Word Low Unsigned Modulo Integer + unsigned32 al, ah, bl, bh; + unsigned64 t1, t2; + al = *rA; + ah = *rAh; + bl = *rB; + bh = *rBh; + t1 = (unsigned64)al * (unsigned64)bl; + t2 = (unsigned64)ah * (unsigned64)bh; + EV_SET_REG2(*rSh, *rS, t2, t1); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); + +0.4,6.RS,11.RA,16.RB,21.1128:EVX:e500:evmwlumia %RS,%RA,%RB:Vector Multiply Word Low Unsigned Modulo Integer and Accumulate + unsigned32 al, ah, bl, bh; + unsigned64 t1, t2; + al = *rA; + ah = *rAh; + bl = *rB; + bh = *rBh; + t1 = (unsigned64)al * (unsigned64)bl; + t2 = (unsigned64)ah * (unsigned64)bh; + EV_SET_REG2_ACC(*rSh, *rS, t2, t1); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); + + +0.4,6.RS,11.RA,16.RB,21.1347:EVX:e500:evmwlssfaaw %RS,%RA,%RB:Vector Multiply Word Low Signed Saturate Fractional and Accumulate in Words + signed32 al, ah, bl, bh; + signed64 t1, t2, tl, th; + int movl, movh, ovl, ovh; + al = *rA; + ah = *rAh; + bl = *rB; + bh = *rBh; + t1 = ev_multiply32_ssf(ah, bh, &movh); + t2 = ev_multiply32_ssf(al, bl, &movl); + th = EV_ACCHIGH + EV_SATURATE(movh, 0xffffffff, t1); + tl = EV_ACCLOW + EV_SATURATE(movl, 0xffffffff, t2); + ovh = EV_SAT_P_S32(th); + ovl = EV_SAT_P_S32(tl); + EV_SET_REG2_ACC(*rSh, *rS, EV_SATURATE_ACC(ovh, th, 0x80000000, 0x7fffffff, th), + EV_SATURATE_ACC(ovl, tl, 0x80000000, 0x7fffffff, tl)); + EV_SET_SPEFSCR_OV(movl | ovl, movh | ovh); + PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); + +0.4,6.RS,11.RA,16.RB,21.1345:EVX:e500:evmwlssiaaw %RS,%RA,%RB:Vector Multiply Word Low Signed Saturate Integer and Accumulate in Words + signed32 al, ah, bl, bh; + signed64 t1, t2, tl, th; + int ovl, ovh; + al = *rA; + ah = *rAh; + bl = *rB; + bh = *rBh; + t1 = (signed64)ah * (signed64)bh; + t2 = (signed64)al * (signed64)bl; + th = EV_ACCHIGH + (t1 & 0xffffffff); + tl = EV_ACCLOW + (t2 & 0xffffffff); + ovh = EV_SAT_P_S32(th); + ovl = EV_SAT_P_S32(tl); + EV_SET_REG2_ACC(*rSh, *rS, EV_SATURATE_ACC(ovh, th, 0x80000000, 0x7fffffff, th), + EV_SATURATE_ACC(ovl, tl, 0x80000000, 0x7fffffff, tl)); + EV_SET_SPEFSCR_OV(ovl, ovh); + PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); + +0.4,6.RS,11.RA,16.RB,21.1355:EVX:e500:evmwlsmfaaw %RS,%RA,%RB:Vector Multiply Word Low Signed Modulo Fractional and Accumulate in Words + signed32 al, ah, bl, bh; + signed64 t1, t2; + int mov; + al = *rA; + ah = *rAh; + bl = *rB; + bh = *rBh; + t1 = ev_multiply32_smf(ah, bh, &mov); + t2 = ev_multiply32_smf(al, bl, &mov); + EV_SET_REG2_ACC(*rSh, *rS, EV_ACCHIGH + (t1 & 0xffffffff), + EV_ACCLOW + (t2 & 0xffffffff)); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); + +0.4,6.RS,11.RA,16.RB,21.1353:EVX:e500:evmwlsmiaaw %RS,%RA,%RB:Vector Multiply Word Low Signed Modulo Integer and Accumulate in Words + signed32 al, ah, bl, bh; + signed64 t1, t2; + al = *rA; + ah = *rAh; + bl = *rB; + bh = *rBh; + t1 = (signed64)ah * (signed64)bh; + t2 = (signed64)al * (signed64)bl; + EV_SET_REG2_ACC(*rSh, *rS, EV_ACCHIGH + (t1 & 0xffffffff), + EV_ACCLOW + (t2 & 0xffffffff)); + //printf("evmwlsmiaaw: al %d ah %d bl %d bh %d t1 %qd t2 %qd\n", al, ah, bl, bh, t1, t2); + //printf("evmwlsmiaaw: *rSh = %08x; *rS = %08x\n", *rSh, *rS); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); + +0.4,6.RS,11.RA,16.RB,21.1344:EVX:e500:evmwlusiaaw %RS,%RA,%RB:Vector Multiply Word Low Unsigned Saturate Integer and Accumulate in Words + unsigned32 al, ah, bl, bh; + unsigned64 t1, t2, tl, th; + int ovl, ovh; + al = *rA; + ah = *rAh; + bl = *rB; + bh = *rBh; + t1 = (unsigned64)ah * (unsigned64)bh; + t2 = (unsigned64)al * (unsigned64)bl; + th = EV_ACCHIGH + (t1 & 0xffffffff); + tl = EV_ACCLOW + (t2 & 0xffffffff); + ovh = (th >> 32); + ovl = (tl >> 32); + EV_SET_REG2_ACC(*rSh, *rS, EV_SATURATE(ovh, 0xffffffff, th), + EV_SATURATE(ovl, 0xffffffff, tl)); + EV_SET_SPEFSCR_OV(ovl, ovh); + PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); + +0.4,6.RS,11.RA,16.RB,21.1352:EVX:e500:evmwlumiaaw %RS,%RA,%RB:Vector Multiply Word Low Unsigned Modulo Integer and Accumulate in Words + unsigned32 al, ah, bl, bh; + unsigned64 t1, t2; + al = *rA; + ah = *rAh; + bl = *rB; + bh = *rBh; + t1 = (unsigned64)ah * (unsigned64)bh; + t2 = (unsigned64)al * (unsigned64)bl; + EV_SET_REG2_ACC(*rSh, *rS, EV_ACCHIGH + (t1 & 0xffffffff), + EV_ACCLOW + (t2 & 0xffffffff)); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); + + +0.4,6.RS,11.RA,16.RB,21.1475:EVX:e500:evmwlssfanw %RS,%RA,%RB:Vector Multiply Word Low Signed Saturate Fractional and Accumulate Negative in Words + signed32 al, ah, bl, bh; + signed64 t1, t2, tl, th; + int movl, movh, ovl, ovh; + al = *rA; + ah = *rAh; + bl = *rB; + bh = *rBh; + t1 = ev_multiply32_ssf(ah, bh, &movh); + t2 = ev_multiply32_ssf(al, bl, &movl); + th = EV_ACCHIGH - EV_SATURATE(movh, 0xffffffff, t1); + tl = EV_ACCLOW - EV_SATURATE(movl, 0xffffffff, t2); + ovh = EV_SAT_P_S32(th); + ovl = EV_SAT_P_S32(tl); + EV_SET_REG2_ACC(*rSh, *rS, EV_SATURATE_ACC(ovh, th, 0x80000000, 0x7fffffff, th), + EV_SATURATE_ACC(ovl, tl, 0x80000000, 0x7fffffff, tl)); + EV_SET_SPEFSCR_OV(movl | ovl, movh | ovh); + PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); + +0.4,6.RS,11.RA,16.RB,21.1473:EVX:e500:evmwlssianw %RS,%RA,%RB:Vector Multiply Word Low Signed Saturate Integer and Accumulate Negative in Words + signed32 al, ah, bl, bh; + signed64 t1, t2, tl, th; + int ovl, ovh; + al = *rA; + ah = *rAh; + bl = *rB; + bh = *rBh; + t1 = (signed64)ah * (signed64)bh; + t2 = (signed64)al * (signed64)bl; + th = EV_ACCHIGH - (t1 & 0xffffffff); + tl = EV_ACCLOW - (t2 & 0xffffffff); + ovh = EV_SAT_P_S32(th); + ovl = EV_SAT_P_S32(tl); + EV_SET_REG2_ACC(*rSh, *rS, EV_SATURATE_ACC(ovh, th, 0x80000000, 0x7fffffff, th), + EV_SATURATE_ACC(ovl, tl, 0x80000000, 0x7fffffff, tl)); + EV_SET_SPEFSCR_OV(ovl, ovh); + PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); + +0.4,6.RS,11.RA,16.RB,21.1483:EVX:e500:evmwlsmfanw %RS,%RA,%RB:Vector Multiply Word Low Signed Modulo Fractional and Accumulate Negative in Words + signed32 al, ah, bl, bh; + signed64 t1, t2; + int mov; + al = *rA; + ah = *rAh; + bl = *rB; + bh = *rBh; + t1 = ev_multiply32_smf(ah, bh, &mov); + t2 = ev_multiply32_smf(al, bl, &mov); + EV_SET_REG2_ACC(*rSh, *rS, EV_ACCHIGH - (t1 & 0xffffffff), + EV_ACCLOW - (t2 & 0xffffffff)); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); + +0.4,6.RS,11.RA,16.RB,21.1481:EVX:e500:evmwlsmianw %RS,%RA,%RB:Vector Multiply Word Low Signed Modulo Integer and Accumulate Negative in Words + signed32 al, ah, bl, bh; + signed64 t1, t2; + al = *rA; + ah = *rAh; + bl = *rB; + bh = *rBh; + t1 = (signed64)ah * (signed64)bh; + t2 = (signed64)al * (signed64)bl; + EV_SET_REG2_ACC(*rSh, *rS, EV_ACCHIGH - (t1 & 0xffffffff), + EV_ACCLOW - (t2 & 0xffffffff)); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); + +0.4,6.RS,11.RA,16.RB,21.1472:EVX:e500:evmwlusianw %RS,%RA,%RB:Vector Multiply Word Low Unsigned Saturate Integer and Accumulate Negative in Words + unsigned32 al, ah, bl, bh; + unsigned64 t1, t2, tl, th; + int ovl, ovh; + al = *rA; + ah = *rAh; + bl = *rB; + bh = *rBh; + t1 = (unsigned64)ah * (unsigned64)bh; + t2 = (unsigned64)al * (unsigned64)bl; + th = EV_ACCHIGH - (t1 & 0xffffffff); + tl = EV_ACCLOW - (t2 & 0xffffffff); + ovh = (th >> 32); + ovl = (tl >> 32); + EV_SET_REG2_ACC(*rSh, *rS, EV_SATURATE(ovh, 0xffffffff, th), + EV_SATURATE(ovl, 0xffffffff, tl)); + //printf("evmwlusianw: ovl %d ovh %d al %d ah %d bl %d bh %d t1 %qd t2 %qd th %qd tl %qd\n", ovl, ovh, al, ah, al, bh, t1, t2, th, tl); + //printf("evmwlusianw: ACC = %08x.%08x; *rSh = %08x; *rS = %08x\n", (int)(ACC >> 32), (int)ACC, *rSh, *rS); + EV_SET_SPEFSCR_OV(ovl, ovh); + PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); + +0.4,6.RS,11.RA,16.RB,21.1480:EVX:e500:evmwlumianw %RS,%RA,%RB:Vector Multiply Word Low Unsigned Modulo Integer and Accumulate Negative in Words + unsigned32 al, ah, bl, bh; + unsigned64 t1, t2; + al = *rA; + ah = *rAh; + bl = *rB; + bh = *rBh; + t1 = (unsigned64)ah * (unsigned64)bh; + t2 = (unsigned64)al * (unsigned64)bl; + EV_SET_REG2_ACC(*rSh, *rS, EV_ACCHIGH - (t1 & 0xffffffff), + EV_ACCLOW - (t2 & 0xffffffff)); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); + + +0.4,6.RS,11.RA,16.RB,21.1107:EVX:e500:evmwssf %RS,%RA,%RB:Vector Multiply Word Signed Saturate Fractional + signed32 a, b; + signed64 t; + int movl; + a = *rA; + b = *rB; + t = ev_multiply32_ssf(a, b, &movl); + EV_SET_REG1(*rSh, *rS, EV_SATURATE(movl, 0x7fffffffffffffff, t)); + EV_SET_SPEFSCR_OV(movl, 0); + PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); + +0.4,6.RS,11.RA,16.RB,21.1139:EVX:e500:evmwssfa %RS,%RA,%RB:Vector Multiply Word Signed Saturate Fractional and Accumulate + signed32 a, b; + signed64 t; + int movl; + a = *rA; + b = *rB; + t = ev_multiply32_ssf(a, b, &movl); + EV_SET_REG1_ACC(*rSh, *rS, EV_SATURATE(movl, 0x7fffffffffffffff, t)); + EV_SET_SPEFSCR_OV(movl, 0); + PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); + +0.4,6.RS,11.RA,16.RB,21.1115:EVX:e500:evmwsmf %RS,%RA,%RB:Vector Multiply Word Signed Modulo Fractional + signed32 a, b; + signed64 t; + int movl; + a = *rA; + b = *rB; + t = ev_multiply32_smf(a, b, &movl); + EV_SET_REG1(*rSh, *rS, t); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); + +0.4,6.RS,11.RA,16.RB,21.1147:EVX:e500:evmwsmfa %RS,%RA,%RB:Vector Multiply Word Signed Modulo Fractional and Accumulate + signed32 a, b; + signed64 t; + int movl; + a = *rA; + b = *rB; + t = ev_multiply32_smf(a, b, &movl); + EV_SET_REG1_ACC(*rSh, *rS, t); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); + +0.4,6.RS,11.RA,16.RB,21.1113:EVX:e500:evmwsmi %RS,%RA,%RB:Vector Multiply Word Signed Modulo Integer + signed32 a, b; + signed64 t; + int movl; + a = *rA; + b = *rB; + t = (signed64)a * (signed64)b; + EV_SET_REG1(*rSh, *rS, t); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); + +0.4,6.RS,11.RA,16.RB,21.1145:EVX:e500:evmwsmia %RS,%RA,%RB:Vector Multiply Word Signed Modulo Integer and Accumulate + signed32 a, b; + signed64 t; + int movl; + a = *rA; + b = *rB; + t = (signed64)a * (signed64)b; + EV_SET_REG1_ACC(*rSh, *rS, t); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); + +0.4,6.RS,11.RA,16.RB,21.1112:EVX:e500:evmwumi %RS,%RA,%RB:Vector Multiply Word Unigned Modulo Integer + unsigned32 a, b; + unsigned64 t; + int movl; + a = *rA; + b = *rB; + t = (signed64)a * (signed64)b; + EV_SET_REG1(*rSh, *rS, t); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); + +0.4,6.RS,11.RA,16.RB,21.1144:EVX:e500:evmwumia %RS,%RA,%RB:Vector Multiply Word Unigned Modulo Integer and Accumulate + unsigned32 a, b; + unsigned64 t; + int movl; + a = *rA; + b = *rB; + t = (signed64)a * (signed64)b; + EV_SET_REG1_ACC(*rSh, *rS, t); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); + + +0.4,6.RS,11.RA,16.RB,21.1363:EVX:e500:evmwssfaa %RS,%RA,%RB:Vector Multiply Word Signed Saturate Fractional Add and Accumulate + signed64 t1, t2; + signed32 a, b; + int movl; + a = *rA; + b = *rB; + t1 = ev_multiply32_ssf(a, b, &movl); + t2 = ACC + EV_SATURATE(movl, 0x7fffffffffffffff, t1); + EV_SET_REG1_ACC(*rSh, *rS, t2); + EV_SET_SPEFSCR_OV(movl, 0); + PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); + +0.4,6.RS,11.RA,16.RB,21.1371:EVX:e500:evmwsmfaa %RS,%RA,%RB:Vector Multiply Word Signed Modulo Fractional Add and Accumulate + signed64 t1, t2; + signed32 a, b; + int movl; + a = *rA; + b = *rB; + t1 = ev_multiply32_smf(a, b, &movl); + t2 = ACC + t1; + EV_SET_REG1_ACC(*rSh, *rS, t2); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); + +0.4,6.RS,11.RA,16.RB,21.1369:EVX:e500:evmwsmiaa %RS,%RA,%RB:Vector Multiply Word Signed Modulo Integer And and Accumulate + signed64 t1, t2; + signed32 a, b; + a = *rA; + b = *rB; + t1 = (signed64)a * (signed64)b; + t2 = ACC + t1; + EV_SET_REG1_ACC(*rSh, *rS, t2); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); + +0.4,6.RS,11.RA,16.RB,21.1368:EVX:e500:evmwumiaa %RS,%RA,%RB:Vector Multiply Word Unsigned Modulo Integer Add and Accumulate + unsigned64 t1, t2; + unsigned32 a, b; + a = *rA; + b = *rB; + t1 = (unsigned64)a * (unsigned64)b; + t2 = ACC + t1; + EV_SET_REG1_ACC(*rSh, *rS, t2); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); + + +0.4,6.RS,11.RA,16.RB,21.1491:EVX:e500:evmwssfan %RS,%RA,%RB:Vector Multiply Word Signed Saturate Fractional and Accumulate Negative + signed64 t1, t2; + signed32 a, b; + int movl; + a = *rA; + b = *rB; + t1 = ev_multiply32_ssf(a, b, &movl); + t2 = ACC - EV_SATURATE(movl, 0x7fffffffffffffff, t1); + EV_SET_REG1_ACC(*rSh, *rS, t2); + EV_SET_SPEFSCR_OV(movl, 0); + PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); + +0.4,6.RS,11.RA,16.RB,21.1499:EVX:e500:evmwsmfan %RS,%RA,%RB:Vector Multiply Word Signed Modulo Fractional and Accumulate Negative + signed64 t1, t2; + signed32 a, b; + int movl; + a = *rA; + b = *rB; + t1 = ev_multiply32_smf(a, b, &movl); + t2 = ACC - t1; + EV_SET_REG1_ACC(*rSh, *rS, t2); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); + +0.4,6.RS,11.RA,16.RB,21.1497:EVX:e500:evmwsmian %RS,%RA,%RB:Vector Multiply Word Signed Modulo Integer and Accumulate Negative + signed64 t1, t2; + signed32 a, b; + a = *rA; + b = *rB; + t1 = (signed64)a * (signed64)b; + t2 = ACC - t1; + EV_SET_REG1_ACC(*rSh, *rS, t2); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); + +0.4,6.RS,11.RA,16.RB,21.1496:EVX:e500:evmwumian %RS,%RA,%RB:Vector Multiply Word Unsigned Modulo Integer and Accumulate Negative + unsigned64 t1, t2; + unsigned32 a, b; + a = *rA; + b = *rB; + t1 = (unsigned64)a * (unsigned64)b; + t2 = ACC - t1; + EV_SET_REG1_ACC(*rSh, *rS, t2); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); + + +0.4,6.RS,11.RA,16.0,21.1217:EVX:e500:evaddssiaaw %RS,%RA:Vector Add Signed Saturate Integer to Accumulator Word + signed64 t1, t2; + signed32 al, ah; + int ovl, ovh; + al = *rA; + ah = *rAh; + t1 = (signed64)EV_ACCHIGH + (signed64)ah; + t2 = (signed64)EV_ACCLOW + (signed64)al; + ovh = EV_SAT_P_S32(t1); + ovl = EV_SAT_P_S32(t2); + EV_SET_REG2_ACC(*rSh, *rS, EV_SATURATE_ACC(ovh, t1 & ((unsigned64)1 << 32), 0x80000000, 0x7fffffff, t1), + EV_SATURATE_ACC(ovl, t2 & ((unsigned64)1 << 32), 0x80000000, 0x7fffffff, t2)); + EV_SET_SPEFSCR_OV(ovl, ovh); + PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK, spr_spefscr); + +0.4,6.RS,11.RA,16.0,21.1225:EVX:e500:evaddsmiaaw %RS,%RA:Vector Add Signed Modulo Integer to Accumulator Word + signed64 t1, t2; + signed32 al, ah; + al = *rA; + ah = *rAh; + t1 = (signed64)EV_ACCHIGH + (signed64)ah; + t2 = (signed64)EV_ACCLOW + (signed64)al; + EV_SET_REG2_ACC(*rSh, *rS, t1, t2); + //printf("evaddsmiaaw: al %d ah %d t1 %qd t2 %qd\n", al, ah, t1, t2); + //printf("evaddsmiaaw: ACC = %08x.%08x; *rSh = %08x; *rS = %08x\n", (int)(ACC >> 32), (int)ACC, *rSh, *rS); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0); + +0.4,6.RS,11.RA,16.0,21.1216:EVX:e500:evaddusiaaw %RS,%RA:Vector Add Unsigned Saturate Integer to Accumulator Word + signed64 t1, t2; + unsigned32 al, ah; + int ovl, ovh; + al = *rA; + ah = *rAh; + t1 = (signed64)EV_ACCHIGH + (signed64)ah; + t2 = (signed64)EV_ACCLOW + (signed64)al; + ovh = EV_SAT_P_U32(t1); + ovl = EV_SAT_P_U32(t2); + EV_SET_REG2_ACC(*rSh, *rS, EV_SATURATE(ovh, 0xffffffff, t1), + EV_SATURATE(ovl, 0xffffffff, t2)); + //printf("evaddusiaaw: ovl %d ovh %d al %d ah %d t1 %qd t2 %qd\n", ovl, ovh, al, ah, t1, t2); + //printf("evaddusiaaw: ACC = %08x.%08x; *rSh = %08x; *rS = %08x\n", (int)(ACC >> 32), (int)ACC, *rSh, *rS); + EV_SET_SPEFSCR_OV(ovl, ovh); + PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK, spr_spefscr); + +0.4,6.RS,11.RA,16.0,21.1224:EVX:e500:evaddumiaaw %RS,%RA:Vector Add Unsigned Modulo Integer to Accumulator Word + unsigned64 t1, t2; + unsigned32 al, ah; + al = *rA; + ah = *rAh; + t1 = (unsigned64)EV_ACCHIGH + (unsigned64)ah; + t2 = EV_ACCLOW + al; + EV_SET_REG2_ACC(*rSh, *rS, t1, t2); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0); + + +0.4,6.RS,11.RA,16.0,21.1219:EVX:e500:evsubfssiaaw %RS,%RA:Vector Subtract Signed Saturate Integer to Accumulator Word + signed64 t1, t2; + signed32 al, ah; + int ovl, ovh; + al = *rA; + ah = *rAh; + t1 = (signed64)EV_ACCHIGH - (signed64)ah; + t2 = (signed64)EV_ACCLOW - (signed64)al; + ovh = EV_SAT_P_S32(t1); + ovl = EV_SAT_P_S32(t2); + EV_SET_REG2_ACC(*rSh, *rS, EV_SATURATE_ACC(ovh, t1, 0x80000000, 0x7fffffff, t1), + EV_SATURATE_ACC(ovl, t2, 0x80000000, 0x7fffffff, t2)); + EV_SET_SPEFSCR_OV(ovl, ovh); + PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK, spr_spefscr); + +0.4,6.RS,11.RA,16.0,21.1227:EVX:e500:evsubfsmiaaw %RS,%RA:Vector Subtract Signed Modulo Integer to Accumulator Word + signed64 t1, t2; + signed32 al, ah; + al = *rA; + ah = *rAh; + t1 = (signed64)EV_ACCHIGH - (signed64)ah; + t2 = (signed64)EV_ACCLOW - (signed64)al; + EV_SET_REG2_ACC(*rSh, *rS, t1, t2); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0); + +0.4,6.RS,11.RA,16.0,21.1218:EVX:e500:evsubfusiaaw %RS,%RA:Vector Subtract Unsigned Saturate Integer to Accumulator Word + signed64 t1, t2; + unsigned32 al, ah; + int ovl, ovh; + + al = *rA; + ah = *rAh; + t1 = (signed64)EV_ACCHIGH - (signed64)ah; + t2 = (signed64)EV_ACCLOW - (signed64)al; + ovh = EV_SAT_P_U32(t1); + ovl = EV_SAT_P_U32(t2); + EV_SET_REG2_ACC(*rSh, *rS, EV_SATURATE(ovh, 0, t1), + EV_SATURATE(ovl, 0, t2)); + EV_SET_SPEFSCR_OV(ovl, ovh); + PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK, spr_spefscr); + +0.4,6.RS,11.RA,16.0,21.1226:EVX:e500:evsubfumiaaw %RS,%RA:Vector Subtract Unsigned Modulo Integer to Accumulator Word + unsigned64 t1, t2; + unsigned32 al, ah; + al = *rA; + ah = *rAh; + t1 = (unsigned64)EV_ACCHIGH - (unsigned64)ah; + t2 = (unsigned64)EV_ACCLOW - (unsigned64)al; + EV_SET_REG2_ACC(*rSh, *rS, t1, t2); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0); + + +0.4,6.RS,11.RA,16.0,21.1220:EVX:e500:evmra %RS,%RA:Initialize Accumulator + EV_SET_REG2_ACC(*rSh, *rS, *rAh, *rA); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0); + +0.4,6.RS,11.RA,16.RB,21.1222:EVX:e500:evdivws %RS,%RA,%RB:Vector Divide Word Signed + signed32 dividendh, dividendl, divisorh, divisorl; + signed32 w1, w2; + int ovh, ovl; + dividendh = *rAh; + dividendl = *rA; + divisorh = *rBh; + divisorl = *rB; + if (dividendh < 0 && divisorh == 0) { + w1 = 0x80000000; + ovh = 1; + } else if (dividendh > 0 && divisorh == 0) { + w1 = 0x7fffffff; + ovh = 1; + } else if (dividendh == 0x80000000 && divisorh == -1) { + w1 = 0x7fffffff; + ovh = 1; + } else { + w1 = dividendh / divisorh; + ovh = 0; + } + if (dividendl < 0 && divisorl == 0) { + w2 = 0x80000000; + ovl = 1; + } else if (dividendl > 0 && divisorl == 0) { + w2 = 0x7fffffff; + ovl = 1; + } else if (dividendl == 0x80000000 && divisorl == -1) { + w2 = 0x7fffffff; + ovl = 1; + } else { + w2 = dividendl / divisorl; + ovl = 0; + } + EV_SET_REG2(*rSh, *rS, w1, w2); + EV_SET_SPEFSCR_OV(ovl, ovh); + PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK, spr_spefscr); + + +0.4,6.RS,11.RA,16.RB,21.1223:EVX:e500:evdivwu %RS,%RA,%RB:Vector Divide Word Unsigned + unsigned32 dividendh, dividendl, divisorh, divisorl; + unsigned32 w1, w2; + int ovh, ovl; + dividendh = *rAh; + dividendl = *rA; + divisorh = *rBh; + divisorl = *rB; + if (divisorh == 0) { + w1 = 0xffffffff; + ovh = 1; + } else { + w1 = dividendh / divisorh; + ovh = 0; + } + if (divisorl == 0) { + w2 = 0xffffffff; + ovl = 1; + } else { + w2 = dividendl / divisorl; + ovl = 0; + } + EV_SET_REG2(*rSh, *rS, w1, w2); + EV_SET_SPEFSCR_OV(ovl, ovh); + PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK, spr_spefscr); + + +# +# A.2.9 Floating Point SPE Instructions +# + +0.4,6.RS,11.RA,16.0,21.644:EVX:e500:evfsabs %RS,%RA:Vector Floating-Point Absolute Value + unsigned32 w1, w2; + w1 = *rAh & 0x7fffffff; + w2 = *rA & 0x7fffffff; + EV_SET_REG2(*rSh, *rS, w1, w2); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0); + +0.4,6.RS,11.RA,16.0,21.645:EVX:e500:evfsnabs %RS,%RA:Vector Floating-Point Negative Absolute Value + unsigned32 w1, w2; + w1 = *rAh | 0x80000000; + w2 = *rA | 0x80000000; + EV_SET_REG2(*rSh, *rS, w1, w2); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0); + +0.4,6.RS,11.RA,16.0,21.646:EVX:e500:evfsneg %RS,%RA:Vector Floating-Point Negate + unsigned32 w1, w2; + w1 = *rAh; + w2 = *rA; + w1 = (w1 & 0x7fffffff) | ((~w1) & 0x80000000); + w2 = (w2 & 0x7fffffff) | ((~w2) & 0x80000000); + EV_SET_REG2(*rSh, *rS, w1, w2); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0); + +0.4,6.RS,11.RA,16.RB,21.640:EVX:e500:evfsadd %RS,%RA,%RB:Vector Floating-Point Add + unsigned32 w1, w2; + w1 = ev_fs_add (*rAh, *rBh, spefscr_finvh, spefscr_fovfh, spefscr_funfh, spefscr_fgh, spefscr_fxh, processor); + w2 = ev_fs_add (*rA, *rB, spefscr_finv, spefscr_fovf, spefscr_funf, spefscr_fgh, spefscr_fxh, processor); + EV_SET_REG2(*rSh, *rS, w1, w2); + PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); + +0.4,6.RS,11.RA,16.RB,21.641:EVX:e500:evfssub %RS,%RA,%RB:Vector Floating-Point Subtract + unsigned32 w1, w2; + w1 = ev_fs_sub (*rAh, *rBh, spefscr_finvh, spefscr_fovfh, spefscr_funfh, spefscr_fgh, spefscr_fxh, processor); + w2 = ev_fs_sub (*rA, *rB, spefscr_finv, spefscr_fovf, spefscr_funf, spefscr_fgh, spefscr_fxh, processor); + EV_SET_REG2(*rSh, *rS, w1, w2); + PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); + +0.4,6.RS,11.RA,16.RB,21.648:EVX:e500:evfsmul %RS,%RA,%RB:Vector Floating-Point Multiply + unsigned32 w1, w2; + w1 = ev_fs_mul (*rAh, *rBh, spefscr_finvh, spefscr_fovfh, spefscr_funfh, spefscr_fgh, spefscr_fxh, processor); + w2 = ev_fs_mul (*rA, *rB, spefscr_finv, spefscr_fovf, spefscr_funf, spefscr_fgh, spefscr_fxh, processor); + EV_SET_REG2(*rSh, *rS, w1, w2); + PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); + +0.4,6.RS,11.RA,16.RB,21.649:EVX:e500:evfsdiv %RS,%RA,%RB:Vector Floating-Point Divide + signed32 w1, w2; + w1 = ev_fs_div (*rAh, *rBh, spefscr_finvh, spefscr_fovfh, spefscr_funfh, spefscr_fdbzh, spefscr_fgh, spefscr_fxh, processor); + w2 = ev_fs_div (*rA, *rB, spefscr_finv, spefscr_fovf, spefscr_funf, spefscr_fdbz, spefscr_fg, spefscr_fx, processor); + EV_SET_REG2(*rSh, *rS, w1, w2); + PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); + +0.4,6.BF,9./,11.RA,16.RB,21.652:EVX:e500:evfscmpgt %BF,%RA,%RB:Vector Floating-Point Compare Greater Than + sim_fpu al, ah, bl, bh; + int w, ch, cl; + sim_fpu_32to (&al, *rA); + sim_fpu_32to (&ah, *rAh); + sim_fpu_32to (&bl, *rB); + sim_fpu_32to (&bh, *rBh); + if (EV_IS_INFDENORMNAN(&al) || EV_IS_INFDENORMNAN(&bl)) + EV_SET_SPEFSCR_BITS(spefscr_finv); + if (EV_IS_INFDENORMNAN(&ah) || EV_IS_INFDENORMNAN(&bh)) + EV_SET_SPEFSCR_BITS(spefscr_finvh); + if (sim_fpu_is_gt(&ah, &bh)) + ch = 1; + else + ch = 0; + if (sim_fpu_is_gt(&al, &bl)) + cl = 1; + else + cl = 0; + w = ch << 3 | cl << 2 | (ch | cl) << 1 | (ch & cl); + CR_SET(BF, w); + PPC_INSN_INT_SPR(0, RA_BITMASK | RB_BITMASK, spr_spefscr); + +0.4,6.BF,9./,11.RA,16.RB,21.653:EVX:e500:evfscmplt %BF,%RA,%RB:Vector Floating-Point Compare Less Than + sim_fpu al, ah, bl, bh; + int w, ch, cl; + sim_fpu_32to (&al, *rA); + sim_fpu_32to (&ah, *rAh); + sim_fpu_32to (&bl, *rB); + sim_fpu_32to (&bh, *rBh); + if (EV_IS_INFDENORMNAN(&al) || EV_IS_INFDENORMNAN(&bl)) + EV_SET_SPEFSCR_BITS(spefscr_finv); + if (EV_IS_INFDENORMNAN(&ah) || EV_IS_INFDENORMNAN(&bh)) + EV_SET_SPEFSCR_BITS(spefscr_finvh); + if (sim_fpu_is_lt(&ah, &bh)) + ch = 1; + else + ch = 0; + if (sim_fpu_is_lt(&al, &bl)) + cl = 1; + else + cl = 0; + w = ch << 3 | cl << 2 | (ch | cl) << 1 | (ch & cl); + CR_SET(BF, w); + PPC_INSN_INT_SPR(0, RA_BITMASK | RB_BITMASK, spr_spefscr); + +0.4,6.BF,9./,11.RA,16.RB,21.654:EVX:e500:evfscmpeq %BF,%RA,%RB:Vector Floating-Point Compare Equal + sim_fpu al, ah, bl, bh; + int w, ch, cl; + sim_fpu_32to (&al, *rA); + sim_fpu_32to (&ah, *rAh); + sim_fpu_32to (&bl, *rB); + sim_fpu_32to (&bh, *rBh); + if (EV_IS_INFDENORMNAN(&al) || EV_IS_INFDENORMNAN(&bl)) + EV_SET_SPEFSCR_BITS(spefscr_finv); + if (EV_IS_INFDENORMNAN(&ah) || EV_IS_INFDENORMNAN(&bh)) + EV_SET_SPEFSCR_BITS(spefscr_finvh); + if (sim_fpu_is_eq(&ah, &bh)) + ch = 1; + else + ch = 0; + if (sim_fpu_is_eq(&al, &bl)) + cl = 1; + else + cl = 0; + w = ch << 3 | cl << 2 | (ch | cl) << 1 | (ch & cl); + CR_SET(BF, w); + PPC_INSN_INT_SPR(0, RA_BITMASK | RB_BITMASK, spr_spefscr); + +0.4,6.BF,9./,11.RA,16.RB,21.668:EVX:e500:evfststgt %BF,%RA,%RB:Vector Floating-Point Test Greater Than + sim_fpu al, ah, bl, bh; + int w, ch, cl; + sim_fpu_32to (&al, *rA); + sim_fpu_32to (&ah, *rAh); + sim_fpu_32to (&bl, *rB); + sim_fpu_32to (&bh, *rBh); + if (sim_fpu_is_gt(&ah, &bh)) + ch = 1; + else + ch = 0; + if (sim_fpu_is_gt(&al, &bl)) + cl = 1; + else + cl = 0; + w = ch << 3 | cl << 2 | (ch | cl) << 1 | (ch & cl); + CR_SET(BF, w); + PPC_INSN_INT_CR(0, RA_BITMASK | RB_BITMASK, BF_BITMASK); + +0.4,6.BF,9./,11.RA,16.RB,21.669:EVX:e500:evfststlt %BF,%RA,%RB:Vector Floating-Point Test Less Than + sim_fpu al, ah, bl, bh; + int w, ch, cl; + sim_fpu_32to (&al, *rA); + sim_fpu_32to (&ah, *rAh); + sim_fpu_32to (&bl, *rB); + sim_fpu_32to (&bh, *rBh); + if (sim_fpu_is_lt(&ah, &bh)) + ch = 1; + else + ch = 0; + if (sim_fpu_is_lt(&al, &bl)) + cl = 1; + else + cl = 0; + w = ch << 3 | cl << 2 | (ch | cl) << 1 | (ch & cl); + CR_SET(BF, w); + PPC_INSN_INT_CR(0, RA_BITMASK | RB_BITMASK, BF_BITMASK); + +0.4,6.BF,9./,11.RA,16.RB,21.670:EVX:e500:evfststeq %BF,%RA,%RB:Vector Floating-Point Test Equal + sim_fpu al, ah, bl, bh; + int w, ch, cl; + sim_fpu_32to (&al, *rA); + sim_fpu_32to (&ah, *rAh); + sim_fpu_32to (&bl, *rB); + sim_fpu_32to (&bh, *rBh); + if (sim_fpu_is_eq(&ah, &bh)) + ch = 1; + else + ch = 0; + if (sim_fpu_is_eq(&al, &bl)) + cl = 1; + else + cl = 0; + w = ch << 3 | cl << 2 | (ch | cl) << 1 | (ch & cl); + CR_SET(BF, w); + PPC_INSN_INT_CR(0, RA_BITMASK | RB_BITMASK, BF_BITMASK); + +0.4,6.RS,11.0,16.RB,21.656:EVX:e500:evfscfui %RS,%RB:Vector Convert Floating-Point from Unsigned Integer + unsigned32 f, w1, w2; + sim_fpu b; + + sim_fpu_u32to (&b, *rBh, sim_fpu_round_default); + sim_fpu_to32 (&w1, &b); + sim_fpu_u32to (&b, *rB, sim_fpu_round_default); + sim_fpu_to32 (&w2, &b); + + EV_SET_REG2(*rSh, *rS, w1, w2); + PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0); + +0.4,6.RS,11.0,16.RB,21.664:EVX:e500:evfsctuiz %RS,%RB:Vector Convert Floating-Point to Unsigned Integer with Round toward Zero + unsigned32 w1, w2; + sim_fpu b; + + sim_fpu_32to (&b, *rBh); + sim_fpu_to32u (&w1, &b, sim_fpu_round_zero); + sim_fpu_32to (&b, *rB); + sim_fpu_to32u (&w2, &b, sim_fpu_round_zero); + + EV_SET_REG2(*rSh, *rS, w1, w2); + PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0); + +0.4,6.RS,11.0,16.RB,21.657:EVX:e500:evfscfsi %RS,%RB:Vector Convert Floating-Point from Signed Integer + signed32 w1, w2; + sim_fpu b, x, y; + + sim_fpu_i32to (&b, *rBh, sim_fpu_round_default); + sim_fpu_to32 (&w1, &b); + sim_fpu_i32to (&b, *rB, sim_fpu_round_default); + sim_fpu_to32 (&w2, &b); + + EV_SET_REG2(*rSh, *rS, w1, w2); + PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0); + +0.4,6.RS,11.0,16.RB,21.658:EVX:e500:evfscfuf %RS,%RB:Vector Convert Floating-Point from Unsigned Fraction + unsigned32 w1, w2, bh, bl; + sim_fpu b, x, y; + bh = *rBh; + if (bh == 0xffffffff) + sim_fpu_to32 (&w1, &sim_fpu_one); + else { + sim_fpu_u64to (&x, 0x100000000, sim_fpu_round_default); + sim_fpu_u32to (&y, bh, sim_fpu_round_default); + sim_fpu_div (&b, &y, &x); + sim_fpu_to32 (&w1, &b); + } + bl = *rB; + if (bl == 0xffffffff) + sim_fpu_to32 (&w2, &sim_fpu_one); + else { + sim_fpu_u64to (&x, 0x100000000, sim_fpu_round_default); + sim_fpu_u32to (&y, bl, sim_fpu_round_default); + sim_fpu_div (&b, &y, &x); + sim_fpu_to32 (&w2, &b); + } + EV_SET_REG2(*rSh, *rS, w1, w2); + PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0); + +0.4,6.RS,11.0,16.RB,21.659:EVX:e500:evfscfsf %RS,%RB:Vector Convert Floating-Point from Signed Fraction + unsigned32 w1, w2; + sim_fpu b, x, y; + + sim_fpu_u32to (&x, 0x80000000, sim_fpu_round_default); + sim_fpu_i32to (&y, *rBh, sim_fpu_round_default); + sim_fpu_div (&b, &y, &x); + sim_fpu_to32 (&w1, &b); + + sim_fpu_u32to (&x, 0x80000000, sim_fpu_round_default); + sim_fpu_i32to (&y, *rB, sim_fpu_round_default); + sim_fpu_div (&b, &y, &x); + sim_fpu_to32 (&w2, &b); + + EV_SET_REG2(*rSh, *rS, w1, w2); + PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0); + +0.4,6.RS,11.0,16.RB,21.660:EVX:e500:evfsctui %RS,%RB:Vector Convert Floating-Point to Unsigned Integer + unsigned32 w1, w2; + sim_fpu b; + + sim_fpu_32to (&b, *rBh); + sim_fpu_to32u (&w1, &b, sim_fpu_round_default); + sim_fpu_32to (&b, *rB); + sim_fpu_to32u (&w2, &b, sim_fpu_round_default); + + EV_SET_REG2(*rSh, *rS, w1, w2); + PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0); + +0.4,6.RS,11.0,16.RB,21.661:EVX:e500:evfsctsi %RS,%RB:Vector Convert Floating-Point to Signed Integer + signed32 w1, w2; + sim_fpu b; + + sim_fpu_32to (&b, *rBh); + sim_fpu_to32i (&w1, &b, sim_fpu_round_default); + sim_fpu_32to (&b, *rB); + sim_fpu_to32i (&w2, &b, sim_fpu_round_default); + + EV_SET_REG2(*rSh, *rS, w1, w2); + PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0); + +0.4,6.RS,11.0,16.RB,21.666:EVX:e500:evfsctsiz %RS,%RB:Vector Convert Floating-Point to Signed Integer with Round toward Zero + signed32 w1, w2; + sim_fpu b; + + sim_fpu_32to (&b, *rBh); + sim_fpu_to32i (&w1, &b, sim_fpu_round_zero); + sim_fpu_32to (&b, *rB); + sim_fpu_to32i (&w2, &b, sim_fpu_round_zero); + + EV_SET_REG2(*rSh, *rS, w1, w2); + PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0); + +0.4,6.RS,11.0,16.RB,21.662:EVX:e500:evfsctuf %RS,%RB:Vector Convert Floating-Point to Unsigned Fraction + unsigned32 w1, w2; + sim_fpu b, x, y; + + sim_fpu_u64to (&x, 0x100000000, sim_fpu_round_default); + sim_fpu_32to (&y, *rBh); + sim_fpu_mul (&b, &y, &x); + sim_fpu_to32u (&w1, &b, sim_fpu_round_default); + + sim_fpu_u64to (&x, 0x100000000, sim_fpu_round_default); + sim_fpu_32to (&y, *rB); + sim_fpu_mul (&b, &y, &x); + sim_fpu_to32u (&w2, &b, sim_fpu_round_default); + + EV_SET_REG2(*rSh, *rS, w1, w2); + PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0); + +0.4,6.RS,11.0,16.RB,21.663:EVX:e500:evfsctsf %RS,%RB:Vector Convert Floating-Point to Signed Fraction + signed32 w1, w2; + sim_fpu b, x, y; + + sim_fpu_32to (&y, *rBh); + sim_fpu_u32to (&x, 0x80000000, sim_fpu_round_default); + sim_fpu_mul (&b, &y, &x); + sim_fpu_to32i (&w1, &b, sim_fpu_round_near); + + sim_fpu_32to (&y, *rB); + sim_fpu_u32to (&x, 0x80000000, sim_fpu_round_default); + sim_fpu_mul (&b, &y, &x); + sim_fpu_to32i (&w2, &b, sim_fpu_round_near); + + EV_SET_REG2(*rSh, *rS, w1, w2); + PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0); + + +0.4,6.RS,11.RA,16.0,21.708:EVX:e500:efsabs %RS,%RA:Floating-Point Absolute Value + unsigned32 w1, w2; + w1 = *rSh; + w2 = *rA & 0x7fffffff; + EV_SET_REG2(*rSh, *rS, w1, w2); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0); + +0.4,6.RS,11.RA,16.0,21.709:EVX:e500:efsnabs %RS,%RA:Floating-Point Negative Absolute Value + unsigned32 w1, w2; + w1 = *rSh; + w2 = *rA | 0x80000000; + EV_SET_REG2(*rSh, *rS, w1, w2); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0); + +0.4,6.RS,11.RA,16.0,21.710:EVX:e500:efsneg %RS,%RA:Floating-Point Negate + unsigned32 w1, w2; + w1 = *rSh; + w2 = (*rA & 0x7fffffff) | ((~*rA) & 0x80000000); + EV_SET_REG2(*rSh, *rS, w1, w2); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0); + +0.4,6.RS,11.RA,16.RB,21.704:EVX:e500:efsadd %RS,%RA,%RB:Floating-Point Add + unsigned32 w; + w = ev_fs_add (*rA, *rB, spefscr_finv, spefscr_fovf, spefscr_funf, spefscr_fgh, spefscr_fxh, processor); + EV_SET_REG(*rS, w); + PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); + +0.4,6.RS,11.RA,16.RB,21.705:EVX:e500:efssub %RS,%RA,%RB:Floating-Point Subtract + unsigned32 w; + w = ev_fs_sub (*rA, *rB, spefscr_finv, spefscr_fovf, spefscr_funf, spefscr_fgh, spefscr_fxh, processor); + EV_SET_REG(*rS, w); + PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); + +0.4,6.RS,11.RA,16.RB,21.712:EVX:e500:efsmul %RS,%RA,%RB:Floating-Point Multiply + unsigned32 w; + w = ev_fs_mul (*rA, *rB, spefscr_finv, spefscr_fovf, spefscr_funf, spefscr_fgh, spefscr_fxh, processor); + EV_SET_REG(*rS, w); + PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); + +0.4,6.RS,11.RA,16.RB,21.713:EVX:e500:efsdiv %RS,%RA,%RB:Floating-Point Divide + unsigned32 w; + w = ev_fs_div (*rA, *rB, spefscr_finv, spefscr_fovf, spefscr_funf, spefscr_fdbz, spefscr_fg, spefscr_fx, processor); + EV_SET_REG(*rS, w); + PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); + +0.4,6.BF,9./,11.RA,16.RB,21.716:EVX:e500:efscmpgt %BF,%RA,%RB:Floating-Point Compare Greater Than + sim_fpu a, b; + int w, cl; + sim_fpu_32to (&a, *rA); + sim_fpu_32to (&b, *rB); + if (EV_IS_INFDENORMNAN(&a) || EV_IS_INFDENORMNAN(&b)) + EV_SET_SPEFSCR_BITS(spefscr_finv); + if (sim_fpu_is_gt(&a, &b)) + cl = 1; + else + cl = 0; + w = cl << 2 | cl << 1; + CR_SET(BF, w); + PPC_INSN_INT_SPR(0, RA_BITMASK | RB_BITMASK, spr_spefscr); + +0.4,6.BF,9./,11.RA,16.RB,21.717:EVX:e500:efscmplt %BF,%RA,%RB:Floating-Point Compare Less Than + sim_fpu al, bl; + int w, cl; + sim_fpu_32to (&al, *rA); + sim_fpu_32to (&bl, *rB); + if (EV_IS_INFDENORMNAN(&al) || EV_IS_INFDENORMNAN(&bl)) + EV_SET_SPEFSCR_BITS(spefscr_finv); + if (sim_fpu_is_lt(&al, &bl)) + cl = 1; + else + cl = 0; + w = cl << 2 | cl << 1; + CR_SET(BF, w); + PPC_INSN_INT_SPR(0, RA_BITMASK | RB_BITMASK, spr_spefscr); + +0.4,6.BF,9./,11.RA,16.RB,21.718:EVX:e500:efscmpeq %BF,%RA,%RB:Floating-Point Compare Equal + sim_fpu al, bl; + int w, cl; + sim_fpu_32to (&al, *rA); + sim_fpu_32to (&bl, *rB); + if (EV_IS_INFDENORMNAN(&al) || EV_IS_INFDENORMNAN(&bl)) + EV_SET_SPEFSCR_BITS(spefscr_finv); + if (sim_fpu_is_eq(&al, &bl)) + cl = 1; + else + cl = 0; + w = cl << 2 | cl << 1; + CR_SET(BF, w); + PPC_INSN_INT_SPR(0, RA_BITMASK | RB_BITMASK, spr_spefscr); + +0.4,6.BF,9./,11.RA,16.RB,21.732:EVX:e500:efststgt %BF,%RA,%RB:Floating-Point Test Greater Than + sim_fpu al, bl; + int w, cl; + sim_fpu_32to (&al, *rA); + sim_fpu_32to (&bl, *rB); + if (sim_fpu_is_gt(&al, &bl)) + cl = 1; + else + cl = 0; + w = cl << 2 | cl << 1; + CR_SET(BF, w); + PPC_INSN_INT_CR(0, RA_BITMASK | RB_BITMASK, BF_BITMASK); + +0.4,6.BF,9./,11.RA,16.RB,21.733:EVX:e500:efststlt %BF,%RA,%RB:Floating-Point Test Less Than + sim_fpu al, bl; + int w, cl; + sim_fpu_32to (&al, *rA); + sim_fpu_32to (&bl, *rB); + if (sim_fpu_is_lt(&al, &bl)) + cl = 1; + else + cl = 0; + w = cl << 2 | cl << 1; + CR_SET(BF, w); + PPC_INSN_INT_CR(0, RA_BITMASK | RB_BITMASK, BF_BITMASK); + +0.4,6.BF,9./,11.RA,16.RB,21.734:EVX:e500:efststeq %BF,%RA,%RB:Floating-Point Test Equal + sim_fpu al, bl; + int w, cl; + sim_fpu_32to (&al, *rA); + sim_fpu_32to (&bl, *rB); + if (sim_fpu_is_eq(&al, &bl)) + cl = 1; + else + cl = 0; + w = cl << 2 | cl << 1; + CR_SET(BF, w); + PPC_INSN_INT_CR(0, RA_BITMASK | RB_BITMASK, BF_BITMASK); + +0.4,6.RS,11.0,16.RB,21.721:EVX:e500:efscfsi %RS,%RB:Convert Floating-Point from Signed Integer + signed32 f, w1, w2; + sim_fpu b; + w1 = *rSh; + sim_fpu_i32to (&b, *rB, sim_fpu_round_default); + sim_fpu_to32 (&w2, &b); + EV_SET_REG2(*rSh, *rS, w1, w2); + PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0); + +0.4,6.RS,11.0,16.RB,21.720:EVX:e500:efscfui %RS,%RB:Convert Floating-Point from Unsigned Integer + unsigned32 w1, w2; + sim_fpu b; + w1 = *rSh; + sim_fpu_u32to (&b, *rB, sim_fpu_round_default); + sim_fpu_to32 (&w2, &b); + EV_SET_REG2(*rSh, *rS, w1, w2); + PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0); + +0.4,6.RS,11.0,16.RB,21.723:EVX:e500:efscfsf %RS,%RB:Convert Floating-Point from Signed Fraction + unsigned32 w1, w2; + sim_fpu b, x, y; + w1 = *rSh; + sim_fpu_u32to (&x, 0x80000000, sim_fpu_round_default); + sim_fpu_i32to (&y, *rB, sim_fpu_round_default); + sim_fpu_div (&b, &y, &x); + sim_fpu_to32 (&w2, &b); + EV_SET_REG2(*rSh, *rS, w1, w2); + PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0); + +0.4,6.RS,11.0,16.RB,21.722:EVX:e500:efscfuf %RS,%RB:Convert Floating-Point from Unsigned Fraction + unsigned32 w1, w2, bl; + sim_fpu b, x, y; + w1 = *rSh; + bl = *rB; + if (bl == 0xffffffff) + sim_fpu_to32 (&w2, &sim_fpu_one); + else { + sim_fpu_u64to (&x, 0x100000000, sim_fpu_round_default); + sim_fpu_u32to (&y, bl, sim_fpu_round_default); + sim_fpu_div (&b, &y, &x); + sim_fpu_to32 (&w2, &b); + } + EV_SET_REG2(*rSh, *rS, w1, w2); + PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0); + +0.4,6.RS,11.0,16.RB,21.725:EVX:e500:efsctsi %RS,%RB:Convert Floating-Point to Signed Integer + signed64 temp; + signed32 w1, w2; + sim_fpu b; + w1 = *rSh; + sim_fpu_32to (&b, *rB); + sim_fpu_to32i (&w2, &b, sim_fpu_round_default); + EV_SET_REG2(*rSh, *rS, w1, w2); + PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0); + +0.4,6.RS,11.0,16.RB,21.730:EVX:e500:efsctsiz %RS,%RB:Convert Floating-Point to Signed Integer with Round toward Zero + signed64 temp; + signed32 w1, w2; + sim_fpu b; + w1 = *rSh; + sim_fpu_32to (&b, *rB); + sim_fpu_to32i (&w2, &b, sim_fpu_round_zero); + EV_SET_REG2(*rSh, *rS, w1, w2); + PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0); + +0.4,6.RS,11.0,16.RB,21.724:EVX:e500:efsctui %RS,%RB:Convert Floating-Point to Unsigned Integer + unsigned64 temp; + signed32 w1, w2; + sim_fpu b; + w1 = *rSh; + sim_fpu_32to (&b, *rB); + sim_fpu_to32u (&w2, &b, sim_fpu_round_default); + EV_SET_REG2(*rSh, *rS, w1, w2); + PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0); + +0.4,6.RS,11.0,16.RB,21.728:EVX:e500:efsctuiz %RS,%RB:Convert Floating-Point to Unsigned Integer with Round toward Zero + unsigned64 temp; + signed32 w1, w2; + sim_fpu b; + w1 = *rSh; + sim_fpu_32to (&b, *rB); + sim_fpu_to32u (&w2, &b, sim_fpu_round_zero); + EV_SET_REG2(*rSh, *rS, w1, w2); + PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0); + +0.4,6.RS,11.0,16.RB,21.727:EVX:e500:efsctsf %RS,%RB:Convert Floating-Point to Signed Fraction + unsigned32 w1, w2; + sim_fpu b, x, y; + w1 = *rSh; + sim_fpu_32to (&y, *rB); + sim_fpu_u32to (&x, 0x80000000, sim_fpu_round_default); + sim_fpu_mul (&b, &y, &x); + sim_fpu_to32i (&w2, &b, sim_fpu_round_default); + sim_fpu_to32 (&w2, &b); + EV_SET_REG2(*rSh, *rS, w1, w2); + PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0); + +0.4,6.RS,11.0,16.RB,21.726:EVX:e500:efsctuf %RS,%RB:Convert Floating-Point to Unsigned Fraction + unsigned32 w1, w2; + sim_fpu b, x, y; + w1 = *rSh; + sim_fpu_u64to (&x, 0x100000000, sim_fpu_round_default); + sim_fpu_32to (&y, *rB); + sim_fpu_mul (&b, &y, &x); + sim_fpu_to32u (&w2, &b, sim_fpu_round_default); + EV_SET_REG2(*rSh, *rS, w1, w2); + PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0); + + +# +# A.2.10 Vector Load/Store Instructions +# + +0.4,6.RS,11.RA,16.UIMM,21.769:EVX:e500:evldd %RS,%RA,%UIMM:Vector Load Double Word into Double Word + unsigned64 m; + unsigned_word b; + unsigned_word EA; + if (RA_is_0) b = 0; + else b = *rA; + EA = b + (UIMM << 3); + m = MEM(unsigned, EA, 8); + EV_SET_REG1(*rSh, *rS, m); + //printf("evldd(%d<-%d + %u): m %08x.%08x, *rSh %x *rS %x\n", RS, RA, UIMM, (int)(m >> 32), (int)m, *rSh, *rS); + PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1), 0); + +0.4,6.RS,11.RA,16.RB,21.768:EVX:e500:evlddx %RS,%RA,%RB:Vector Load Double Word into Double Word Indexed + unsigned64 m; + unsigned_word b; + unsigned_word EA; + if (RA_is_0) b = 0; + else b = *rA; + EA = b + *rB; + m = MEM(unsigned, EA, 8); + EV_SET_REG1(*rSh, *rS, m); + PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1) | RB_BITMASK, 0); + +0.4,6.RS,11.RA,16.UIMM,21.771:EVX:e500:evldw %RS,%RA,%UIMM:Vector Load Double into Two Words + unsigned_word b; + unsigned_word EA; + unsigned32 w1, w2; + if (RA_is_0) b = 0; + else b = *rA; + EA = b + (UIMM << 3); + w1 = MEM(unsigned, EA, 4); + w2 = MEM(unsigned, EA + 4, 4); + EV_SET_REG2(*rSh, *rS, w1, w2); + PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1), 0); + +0.4,6.RS,11.RA,16.RB,21.770:EVX:e500:evldwx %RS,%RA,%RB:Vector Load Double into Two Words Indexed + unsigned_word b; + unsigned_word EA; + unsigned32 w1, w2; + if (RA_is_0) b = 0; + else b = *rA; + EA = b + *rB; + w1 = MEM(unsigned, EA, 4); + w2 = MEM(unsigned, EA + 4, 4); + EV_SET_REG2(*rSh, *rS, w1, w2); + PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1) | RB_BITMASK, 0); + +0.4,6.RS,11.RA,16.UIMM,21.773:EVX:e500:evldh %RS,%RA,%UIMM:Vector Load Double into 4 Half Words + unsigned_word b; + unsigned_word EA; + unsigned16 h1, h2, h3, h4; + if (RA_is_0) b = 0; + else b = *rA; + EA = b + (UIMM << 3); + h1 = MEM(unsigned, EA, 2); + h2 = MEM(unsigned, EA + 2, 2); + h3 = MEM(unsigned, EA + 4, 2); + h4 = MEM(unsigned, EA + 6, 2); + EV_SET_REG4(*rSh, *rS, h1, h2, h3, h4); + PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1), 0); + +0.4,6.RS,11.RA,16.RB,21.772:EVX:e500:evldhx %RS,%RA,%RB:Vector Load Double into 4 Half Words Indexed + unsigned_word b; + unsigned_word EA; + unsigned16 h1, h2, h3, h4; + if (RA_is_0) b = 0; + else b = *rA; + EA = b + *rB; + h1 = MEM(unsigned, EA, 2); + h2 = MEM(unsigned, EA + 2, 2); + h3 = MEM(unsigned, EA + 4, 2); + h4 = MEM(unsigned, EA + 6, 2); + EV_SET_REG4(*rSh, *rS, h1, h2, h3, h4); + PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1) | RB_BITMASK, 0); + +0.4,6.RS,11.RA,16.UIMM,21.785:EVX:e500:evlwhe %RS,%RA,%UIMM:Vector Load Word into Two Half Words Even + unsigned_word b; + unsigned_word EA; + unsigned16 h1, h2, h3, h4; + if (RA_is_0) b = 0; + else b = *rA; + EA = b + (UIMM << 2); + h1 = MEM(unsigned, EA, 2); + h2 = 0; + h3 = MEM(unsigned, EA + 2, 2); + h4 = 0; + EV_SET_REG4(*rSh, *rS, h1, h2, h3, h4); + PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1), 0); + +0.4,6.RS,11.RA,16.RB,21.784:EVX:e500:evlwhex %RS,%RA,%RB:Vector Load Word into Two Half Words Even Indexed + unsigned_word b; + unsigned_word EA; + unsigned16 h1, h2, h3, h4; + if (RA_is_0) b = 0; + else b = *rA; + EA = b + *rB; + h1 = MEM(unsigned, EA, 2); + h2 = 0; + h3 = MEM(unsigned, EA + 2, 2); + h4 = 0; + EV_SET_REG4(*rSh, *rS, h1, h2, h3, h4); + PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1) | RB_BITMASK, 0); + +0.4,6.RS,11.RA,16.UIMM,21.789:EVX:e500:evlwhou %RS,%RA,%UIMM:Vector Load Word into Two Half Words Odd Unsigned zero-extended + unsigned_word b; + unsigned_word EA; + unsigned16 h1, h2, h3, h4; + if (RA_is_0) b = 0; + else b = *rA; + EA = b + (UIMM << 2); + h1 = 0; + h2 = MEM(unsigned, EA, 2); + h3 = 0; + h4 = MEM(unsigned, EA + 2, 2); + EV_SET_REG4(*rSh, *rS, h1, h2, h3, h4); + PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1), 0); + +0.4,6.RS,11.RA,16.RB,21.788:EVX:e500:evlwhoux %RS,%RA,%RB:Vector Load Word into Two Half Words Odd Unsigned Indexed zero-extended + unsigned_word b; + unsigned_word EA; + unsigned16 h1, h2, h3, h4; + if (RA_is_0) b = 0; + else b = *rA; + EA = b + *rB; + h1 = 0; + h2 = MEM(unsigned, EA, 2); + h3 = 0; + h4 = MEM(unsigned, EA + 2, 2); + EV_SET_REG4(*rSh, *rS, h1, h2, h3, h4); + PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1) | RB_BITMASK, 0); + +0.4,6.RS,11.RA,16.UIMM,21.791:EVX:e500:evlwhos %RS,%RA,%UIMM:Vector Load Word into Half Words Odd Signed with sign extension + unsigned_word b; + unsigned_word EA; + unsigned16 h1, h2, h3, h4; + if (RA_is_0) b = 0; + else b = *rA; + EA = b + (UIMM << 2); + h2 = MEM(unsigned, EA, 2); + if (h2 & 0x8000) + h1 = 0xffff; + else + h1 = 0; + h4 = MEM(unsigned, EA + 2, 2); + if (h4 & 0x8000) + h3 = 0xffff; + else + h3 = 0; + EV_SET_REG4(*rSh, *rS, h1, h2, h3, h4); + PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1), 0); + +0.4,6.RS,11.RA,16.RB,21.790:EVX:e500:evlwhosx %RS,%RA,%RB:Vector Load Word into Half Words Odd Signed Indexed with sign extension + unsigned_word b; + unsigned_word EA; + unsigned16 h1, h2, h3, h4; + if (RA_is_0) b = 0; + else b = *rA; + EA = b + *rB; + h2 = MEM(unsigned, EA, 2); + if (h2 & 0x8000) + h1 = 0xffff; + else + h1 = 0; + h4 = MEM(unsigned, EA + 2, 2); + if (h4 & 0x8000) + h3 = 0xffff; + else + h3 = 0; + EV_SET_REG4(*rSh, *rS, h1, h2, h3, h4); + PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1) | RB_BITMASK, 0); + +0.4,6.RS,11.RA,16.UIMM,21.793:EVX:e500:evlwwsplat %RS,%RA,%UIMM:Vector Load Word into Word and Splat + unsigned_word b; + unsigned_word EA; + unsigned32 w1; + if (RA_is_0) b = 0; + else b = *rA; + EA = b + (UIMM << 2); + w1 = MEM(unsigned, EA, 4); + EV_SET_REG2(*rSh, *rS, w1, w1); + PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1), 0); + +0.4,6.RS,11.RA,16.RB,21.792:EVX:e500:evlwwsplatx %RS,%RA,%RB:Vector Load Word into Word and Splat Indexed + unsigned_word b; + unsigned_word EA; + unsigned32 w1; + if (RA_is_0) b = 0; + else b = *rA; + EA = b + *rB; + w1 = MEM(unsigned, EA, 4); + EV_SET_REG2(*rSh, *rS, w1, w1); + PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1) | RB_BITMASK, 0); + +0.4,6.RS,11.RA,16.UIMM,21.797:EVX:e500:evlwhsplat %RS,%RA,%UIMM:Vector Load Word into 2 Half Words and Splat + unsigned_word b; + unsigned_word EA; + unsigned16 h1, h2; + if (RA_is_0) b = 0; + else b = *rA; + EA = b + (UIMM << 2); + h1 = MEM(unsigned, EA, 2); + h2 = MEM(unsigned, EA + 2, 2); + EV_SET_REG4(*rSh, *rS, h1, h1, h2, h2); + PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1), 0); + +0.4,6.RS,11.RA,16.RB,21.796:EVX:e500:evlwhsplatx %RS,%RA,%RB:Vector Load Word into 2 Half Words and Splat Indexed + unsigned_word b; + unsigned_word EA; + unsigned16 h1, h2; + if (RA_is_0) b = 0; + else b = *rA; + EA = b + *rB; + h1 = MEM(unsigned, EA, 2); + h2 = MEM(unsigned, EA + 2, 2); + EV_SET_REG4(*rSh, *rS, h1, h1, h2, h2); + PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1) | RB_BITMASK, 0); + +0.4,6.RS,11.RA,16.UIMM,21.777:EVX:e500:evlhhesplat %RS,%RA,%UIMM:Vector Load Half Word into Half Words Even and Splat + unsigned_word b; + unsigned_word EA; + unsigned16 h; + if (RA_is_0) b = 0; + else b = *rA; + EA = b + (UIMM << 1); + h = MEM(unsigned, EA, 2); + EV_SET_REG4(*rSh, *rS, h, 0, h, 0); + PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1), 0); + +0.4,6.RS,11.RA,16.RB,21.776:EVX:e500:evlhhesplatx %RS,%RA,%RB:Vector Load Half Word into Half Words Even and Splat Indexed + unsigned_word b; + unsigned_word EA; + unsigned16 h; + if (RA_is_0) b = 0; + else b = *rA; + EA = b + *rB; + h = MEM(unsigned, EA, 2); + EV_SET_REG4(*rSh, *rS, h, 0, h, 0); + PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1) | RB_BITMASK, 0); + +0.4,6.RS,11.RA,16.UIMM,21.781:EVX:e500:evlhhousplat %RS,%RA,%UIMM:Vector Load Half Word into Half Word Odd Unsigned and Splat + unsigned_word b; + unsigned_word EA; + unsigned16 h; + if (RA_is_0) b = 0; + else b = *rA; + EA = b + (UIMM << 1); + h = MEM(unsigned, EA, 2); + EV_SET_REG4(*rSh, *rS, 0, h, 0, h); + PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1), 0); + +0.4,6.RS,11.RA,16.RB,21.780:EVX:e500:evlhhousplatx %RS,%RA,%RB:Vector Load Half Word into Half Word Odd Unsigned and Splat Indexed + unsigned_word b; + unsigned_word EA; + unsigned16 h; + if (RA_is_0) b = 0; + else b = *rA; + EA = b + *rB; + h = MEM(unsigned, EA, 2); + EV_SET_REG4(*rSh, *rS, 0, h, 0, h); + PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1) | RB_BITMASK, 0); + +0.4,6.RS,11.RA,16.UIMM,21.783:EVX:e500:evlhhossplat %RS,%RA,%UIMM:Vector Load Half Word into Half Word Odd Signed and Splat + unsigned_word b; + unsigned_word EA; + unsigned16 h1, h2; + if (RA_is_0) b = 0; + else b = *rA; + EA = b + (UIMM << 1); + h2 = MEM(unsigned, EA, 2); + if (h2 & 0x8000) + h1 = 0xffff; + else + h1 = 0; + EV_SET_REG4(*rSh, *rS, h1, h2, h1, h2); + PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1), 0); + +0.4,6.RS,11.RA,16.RB,21.782:EVX:e500:evlhhossplatx %RS,%RA,%RB:Vector Load Half Word into Half Word Odd Signed and Splat Indexed + unsigned_word b; + unsigned_word EA; + unsigned16 h1, h2; + if (RA_is_0) b = 0; + else b = *rA; + EA = b + *rB; + h2 = MEM(unsigned, EA, 2); + if (h2 & 0x8000) + h1 = 0xffff; + else + h1 = 0; + EV_SET_REG4(*rSh, *rS, h1, h2, h1, h2); + PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1) | RB_BITMASK, 0); + + +0.4,6.RS,11.RA,16.UIMM,21.801:EVX:e500:evstdd %RS,%RA,%UIMM:Vector Store Double of Double + unsigned_word b; + unsigned_word EA; + if (RA_is_0) b = 0; + else b = *rA; + EA = b + (UIMM << 3); + STORE(EA, 4, (*rSh)); + STORE(EA + 4, 4, (*rS)); + PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1), 0); + +0.4,6.RS,11.RA,16.RB,21.800:EVX:e500:evstddx %RS,%RA,%RB:Vector Store Double of Double Indexed + unsigned_word b; + unsigned_word EA; + if (RA_is_0) b = 0; + else b = *rA; + EA = b + *rB; + STORE(EA, 4, (*rSh)); + STORE(EA + 4, 4, (*rS)); + PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1) | RB_BITMASK, 0); + +0.4,6.RS,11.RA,16.UIMM,21.803:EVX:e500:evstdw %RS,%RA,%UIMM:Vector Store Double of Two Words + unsigned_word b; + unsigned_word EA; + unsigned32 w1, w2; + if (RA_is_0) b = 0; + else b = *rA; + EA = b + (UIMM << 3); + w1 = *rSh; + w2 = *rS; + STORE(EA + 0, 4, w1); + STORE(EA + 4, 4, w2); + PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1), 0); + +0.4,6.RS,11.RA,16.RB,21.802:EVX:e500:evstdwx %RS,%RA,%RB:Vector Store Double of Two Words Indexed + unsigned_word b; + unsigned_word EA; + unsigned32 w1, w2; + if (RA_is_0) b = 0; + else b = *rA; + EA = b + *rB; + w1 = *rSh; + w2 = *rS; + STORE(EA + 0, 4, w1); + STORE(EA + 4, 4, w2); + PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1) | RB_BITMASK, 0); + +0.4,6.RS,11.RA,16.UIMM,21.805:EVX:e500:evstdh %RS,%RA,%UIMM:Vector Store Double of Four Half Words + unsigned_word b; + unsigned_word EA; + unsigned16 h1, h2, h3, h4; + if (RA_is_0) b = 0; + else b = *rA; + EA = b + (UIMM << 3); + h1 = EV_HIHALF(*rSh); + h2 = EV_LOHALF(*rSh); + h3 = EV_HIHALF(*rS); + h4 = EV_LOHALF(*rS); + STORE(EA + 0, 2, h1); + STORE(EA + 2, 2, h2); + STORE(EA + 4, 2, h3); + STORE(EA + 6, 2, h4); + PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1), 0); + +0.4,6.RS,11.RA,16.RB,21.804:EVX:e500:evstdhx %RS,%RA,%RB:Vector Store Double of Four Half Words Indexed + unsigned_word b; + unsigned_word EA; + unsigned16 h1, h2, h3, h4; + if (RA_is_0) b = 0; + else b = *rA; + EA = b + *rB; + h1 = EV_HIHALF(*rSh); + h2 = EV_LOHALF(*rSh); + h3 = EV_HIHALF(*rS); + h4 = EV_LOHALF(*rS); + STORE(EA + 0, 2, h1); + STORE(EA + 2, 2, h2); + STORE(EA + 4, 2, h3); + STORE(EA + 6, 2, h4); + PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1) | RB_BITMASK, 0); + +0.4,6.RS,11.RA,16.UIMM,21.825:EVX:e500:evstwwe %RS,%RA,%UIMM:Vector Store Word of Word from Even + unsigned_word b; + unsigned_word EA; + unsigned32 w; + if (RA_is_0) b = 0; + else b = *rA; + EA = b + (UIMM << 3); + w = *rSh; + STORE(EA, 4, w); + PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1), 0); + +0.4,6.RS,11.RA,16.RB,21.824:EVX:e500:evstwwex %RS,%RA,%RB:Vector Store Word of Word from Even Indexed + unsigned_word b; + unsigned_word EA; + unsigned32 w; + if (RA_is_0) b = 0; + else b = *rA; + EA = b + *rB; + w = *rSh; + STORE(EA, 4, w); + PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1) | RB_BITMASK, 0); + +0.4,6.RS,11.RA,16.UIMM,21.829:EVX:e500:evstwwo %RS,%RA,%UIMM:Vector Store Word of Word from Odd + unsigned_word b; + unsigned_word EA; + unsigned32 w; + if (RA_is_0) b = 0; + else b = *rA; + EA = b + (UIMM << 3); + w = *rS; + STORE(EA, 4, w); + PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1), 0); + +0.4,6.RS,11.RA,16.RB,21.828:EVX:e500:evstwwox %RS,%RA,%RB:Vector Store Word of Word from Odd Indexed + unsigned_word b; + unsigned_word EA; + unsigned32 w; + if (RA_is_0) b = 0; + else b = *rA; + EA = b + *rB; + w = *rS; + STORE(EA, 4, w); + PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1) | RB_BITMASK, 0); + +0.4,6.RS,11.RA,16.UIMM,21.817:EVX:e500:evstwhe %RS,%RA,%UIMM:Vector Store Word of Two Half Words from Even + unsigned_word b; + unsigned_word EA; + unsigned16 h1, h2; + if (RA_is_0) b = 0; + else b = *rA; + EA = b + (UIMM << 3); + h1 = EV_HIHALF(*rSh); + h2 = EV_HIHALF(*rS); + STORE(EA + 0, 2, h1); + STORE(EA + 2, 2, h2); + PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1), 0); + +0.4,6.RS,11.RA,16.RB,21.816:EVX:e500:evstwhex %RS,%RA,%RB:Vector Store Word of Two Half Words from Even Indexed + unsigned_word b; + unsigned_word EA; + unsigned16 h1, h2; + if (RA_is_0) b = 0; + else b = *rA; + EA = b + *rB; + h1 = EV_HIHALF(*rSh); + h2 = EV_HIHALF(*rS); + STORE(EA + 0, 2, h1); + STORE(EA + 2, 2, h2); + PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1) | RB_BITMASK, 0); + +0.4,6.RS,11.RA,16.UIMM,21.821:EVX:e500:evstwho %RS,%RA,%UIMM:Vector Store Word of Two Half Words from Odd + unsigned_word b; + unsigned_word EA; + unsigned16 h1, h2; + if (RA_is_0) b = 0; + else b = *rA; + EA = b + (UIMM << 3); + h1 = EV_LOHALF(*rSh); + h2 = EV_LOHALF(*rS); + STORE(EA + 0, 2, h1); + STORE(EA + 2, 2, h2); + PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1), 0); + +0.4,6.RS,11.RA,16.RB,21.820:EVX:e500:evstwhox %RS,%RA,%RB:Vector Store Word of Two Half Words from Odd Indexed + unsigned_word b; + unsigned_word EA; + unsigned16 h1, h2; + if (RA_is_0) b = 0; + else b = *rA; + EA = b + *rB; + h1 = EV_LOHALF(*rSh); + h2 = EV_LOHALF(*rS); + STORE(EA + 0, 2, h1); + STORE(EA + 2, 2, h2); + PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1) | RB_BITMASK, 0); + + +# +# 4.5.1 Integer Select Instruction +# + +0.31,6.RS,11.RA,16.RB,21.CRB,26.30:X:e500:isel %RS,%RA,%RB,%CRB:Integer Select + if (CR & (1 << (31 - (unsigned)CRB))) + if (RA_is_0) + EV_SET_REG1(*rSh, *rS, 0); + else + EV_SET_REG2(*rSh, *rS, *rAh, *rA); + else + EV_SET_REG2(*rSh, *rS, *rBh, *rB); + PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); diff --git a/sim/ppc/e500_expression.h b/sim/ppc/e500_expression.h new file mode 100644 index 0000000..c634a1c --- /dev/null +++ b/sim/ppc/e500_expression.h @@ -0,0 +1,173 @@ +/* e500 expression macros, for PSIM, the PowerPC simulator. + + Copyright 2003 Free Software Foundation, Inc. + + Contributed by Red Hat Inc; developed under contract from Motorola. + Written by matthew green . + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +/* e500 register dance */ +#define EV_SET_REG4(sh, sl, h0, h1, h2, h3) do { \ + (sh) = (((h0) & 0xffff) << 16) | ((h1) & 0xffff); \ + (sl) = (((h2) & 0xffff) << 16) | ((h3) & 0xffff); \ +} while (0) +#define EV_SET_REG4_ACC(sh, sl, h0, h1, h2, h3) do { \ + (sh) = (((h0) & 0xffff) << 16) | ((h1) & 0xffff); \ + (sl) = (((h2) & 0xffff) << 16) | ((h3) & 0xffff); \ + ACC = ((unsigned64)(sh) << 32) | (sl & 0xffffffff); \ +} while (0) + +#define EV_SET_REG2(sh, sl, dh, dl) do { \ + (sh) = (dh) & 0xffffffff; \ + (sl) = (dl) & 0xffffffff; \ +} while (0) +#define EV_SET_REG2_ACC(sh, sl, dh, dl) do { \ + (sh) = (dh) & 0xffffffff; \ + (sl) = (dl) & 0xffffffff; \ + ACC = ((unsigned64)(sh) << 32) | ((sl) & 0xffffffff); \ +} while (0) + +#define EV_SET_REG1(sh, sl, d) do { \ + (sh) = ((unsigned64)(d) >> 32) & 0xffffffff; \ + (sl) = (d) & 0xffffffff; \ +} while (0) +#define EV_SET_REG1_ACC(sh, sl, d) do { \ + (sh) = ((unsigned64)(d) >> 32) & 0xffffffff; \ + (sl) = (d) & 0xffffffff; \ + ACC = (d); \ +} while (0) + +#define EV_SET_REG(s, d) do { \ + (s) = (d) & 0xffffffff; \ +} while (0) + +/* get the low or high half word of a word */ +#define EV_LOHALF(x) ((unsigned32)(x) & 0xffff) +#define EV_HIHALF(x) (((unsigned32)(x) >> 16) & 0xffff) + +/* partially visible accumulator accessors */ +#define EV_SET_ACC(rh, rl) \ + ACC = ((unsigned64)(rh) << 32) | ((rl) & 0xffffffff) + +#define EV_ACCLOW (ACC & 0xffffffff) +#define EV_ACCHIGH ((ACC >> 32) & 0xffffffff) + +/* bit manipulation macros needed for e500 SPE */ +#define EV_BITREVERSE16(x) \ + (((x) & 0x0001) << 15) \ + | (((x) & 0x0002) << 13) \ + | (((x) & 0x0004) << 11) \ + | (((x) & 0x0008) << 9) \ + | (((x) & 0x0010) << 7) \ + | (((x) & 0x0020) << 5) \ + | (((x) & 0x0040) << 3) \ + | (((x) & 0x0080) << 1) \ + | (((x) & 0x0100) >> 1) \ + | (((x) & 0x0200) >> 3) \ + | (((x) & 0x0400) >> 5) \ + | (((x) & 0x0800) >> 7) \ + | (((x) & 0x1000) >> 9) \ + | (((x) & 0x2000) >> 11) \ + | (((x) & 0x4000) >> 13) \ + | (((x) & 0x8000) >> 15) + +/* saturation helpers */ +#define EV_MUL16_SSF(a,b) ((signed64)((signed32)(signed16)(a) * (signed32)(signed16)(b)) << 1) +/* this one loses the top sign bit; be careful */ +#define EV_MUL32_SSF(a,b) (((signed64)(signed32)(a) * (signed64)(signed32)(b)) << 1) +#define EV_SAT_P_S32(x) ((((signed64)(x)) < -0x80000000LL) || (((signed64)(x)) > 0x7fffffffLL)) +#define EV_SAT_P_U32(x) ((((signed64)(x)) < -0LL) || (((signed64)(x)) > 0xffffffffLL)) + +#define EV_SATURATE(flag, sat_val, val) \ + ((flag) ? (sat_val) : (val)) + +#define EV_SATURATE_ACC(flag, sign, negative_sat_val, positive_sat_val, val) \ + ((flag) ? ((((sign) >> 63) & 1) ? (negative_sat_val) : (positive_sat_val)) : (val)) + +/* SPEFSCR handling. */ + +/* These bits must be clear. */ +#define EV_SPEFSCR_MASK (BIT(40) | BIT(41) | spefscr_mode | BIT(56)) + +/* The Inexact and Divide by zero sticky bits are based on others. */ +#define EV_SET_SPEFSCR(bits) do { \ + int finxs = (bits) & (spefscr_fgh|spefscr_fxh|spefscr_fg|spefscr_fx); \ + int fdbzs = (bits) & (spefscr_fdbzh|spefscr_fdbz); \ + SPREG(spr_spefscr) = ((bits) & ~EV_SPEFSCR_MASK) | \ + (finxs ? spefscr_finxs : 0) | \ + (fdbzs ? spefscr_fdbzs : 0); \ +} while (0) + +#define EV_SET_SPEFSCR_BITS(s) \ + EV_SET_SPEFSCR(SPREG(spr_spefscr) | (s)) + +#define EV_SET_SPEFSCR_OV(l,h) do { \ + unsigned32 _sPefScR = SPREG(spr_spefscr); \ + if (l) \ + _sPefScR |= spefscr_ov | spefscr_sov; \ + else \ + _sPefScR &= ~spefscr_ov; \ + if (h) \ + _sPefScR |= spefscr_ovh | spefscr_sovh; \ + else \ + _sPefScR &= ~spefscr_ovh; \ + EV_SET_SPEFSCR(_sPefScR); \ +} while (0) + +/* SPE floating point helpers. */ + +#define EV_PMAX 0x7f7fffff +#define EV_NMAX 0xff7fffff +#define EV_PMIN 0x00800001 +#define EV_NMIN 0x80800001 + +#define EV_IS_INFDENORMNAN(x) \ + (sim_fpu_is_infinity(x) || sim_fpu_is_denorm(x) || sim_fpu_is_nan(x)) + +/* These aren't used (yet?) For now, SPU is always enabled. + Would be nice if they were generated by igen for e500. */ +#define SPU_BEGIN \ +{ \ + if (MSR & msr_e500_spu_enable) { \ + +#define SPU_END \ + } else { \ + /* FIXME: raise SPU unavailable. */ \ + } \ +} + +/* These are also not yet used. */ +#define SPU_FP_BEGIN \ +{ + +#define SPU_FP_END \ + { \ + unsigned s = SPEFSCR; \ + /* Check SPEFSCR; raise exceptions if any required. */ \ + if (((spefscr_finxe || spefscr_finve) \ + && (s & (spefscr_finvh|spefscr_finv))) \ + || ((spefscr_finxe || spefscr_fdbze) \ + && (s & (spefscr_fdbzh|spefscr_fdbz))) \ + || ((spefscr_finxe || spefscr_funfe) \ + && (s & (spefscr_funfh|spefscr_funf))) \ + || ((spefscr_finxe || spefscr_fovfe) \ + && (s & (spefscr_fovfh|spefscr_fovf)))) \ + /* FIXME: raise exceptions. */; \ + } \ +} diff --git a/sim/ppc/e500_registers.h b/sim/ppc/e500_registers.h new file mode 100644 index 0000000..cd12ab5 --- /dev/null +++ b/sim/ppc/e500_registers.h @@ -0,0 +1,83 @@ +/* e500 registers, for PSIM, the PowerPC simulator. + + Copyright 2003 Free Software Foundation, Inc. + + Contributed by Red Hat Inc; developed under contract from Motorola. + Written by matthew green . + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +/* e500 accumulator. */ + +typedef unsigned64 accreg; + +enum { + msr_e500_spu_enable = BIT(38) +}; + +/* E500 regsiters. */ + +enum + { + spefscr_sovh = BIT(32), /* summary integer overlow (high) */ + spefscr_ovh = BIT(33), /* int overflow (high) */ + spefscr_fgh = BIT(34), /* FP guard (high) */ + spefscr_fxh = BIT(35), /* FP sticky (high) */ + spefscr_finvh = BIT(36), /* FP invalid operand (high) */ + spefscr_fdbzh = BIT(37), /* FP divide by zero (high) */ + spefscr_funfh = BIT(38), /* FP underflow (high) */ + spefscr_fovfh = BIT(39), /* FP overflow (high) */ + spefscr_finxs = BIT(42), /* FP inexact sticky */ + spefscr_finvs = BIT(43), /* FP invalid operand sticky */ + spefscr_fdbzs = BIT(44), /* FP divide by zero sticky */ + spefscr_funfs = BIT(45), /* FP underflow sticky */ + spefscr_fovfs = BIT(46), /* FP overflow sticky */ + spefscr_mode = BIT(47), /* SPU MODE (read only) */ + spefscr_sov = BIT(48), /* Summary integer overlow (low) */ + spefscr_ov = BIT(49), /* int overflow (low) */ + spefscr_fg = BIT(50), /* FP guard (low) */ + spefscr_fx = BIT(51), /* FP sticky (low) */ + spefscr_finv = BIT(52), /* FP invalid operand (low) */ + spefscr_fdbz = BIT(53), /* FP divide by zero (low) */ + spefscr_funf = BIT(54), /* FP underflow (low) */ + spefscr_fovf = BIT(55), /* FP overflow (low) */ + spefscr_finxe = BIT(57), /* FP inexact enable */ + spefscr_finve = BIT(58), /* FP invalid operand enable */ + spefscr_fdbze = BIT(59), /* FP divide by zero enable */ + spefscr_funfe = BIT(60), /* FP underflow enable */ + spefscr_fovfe = BIT(61), /* FP overflow enable */ + spefscr_frmc0 = BIT(62), /* FP round mode control */ + spefscr_frmc1 = BIT(63), + spefscr_frmc = (spefscr_frmc0 | spefscr_frmc1), +}; + +struct e500_regs { + /* e500 high bits. */ + signed_word gprh[32]; + /* Accumulator */ + accreg acc; +}; + +/* SPE partially visible acculator */ +#define ACC cpu_registers(processor)->e500.acc + +/* e500 register high bits */ +#define GPRH(N) cpu_registers(processor)->e500.gprh[N] + +/* e500 unified vector register */ +#define EVR(N) ((((unsigned64)GPRH(N)) << 32) | GPR(N)) diff --git a/sim/testsuite/frv-elf/ChangeLog b/sim/testsuite/frv-elf/ChangeLog new file mode 100644 index 0000000..5d6b82c --- /dev/null +++ b/sim/testsuite/frv-elf/ChangeLog @@ -0,0 +1,34 @@ +2000-07-26 Dave Brolley + + * Makefile.in (TESTS): Don't run cache.ok + * cache.s: Use softune syntax for jmpl. + +2000-07-19 Dave Brolley + + * cache.s (pass): Use softune syntax for tira. + * exit47.s (pass): Use softune syntax for tira. + * grloop.s (pass): Use softune syntax for tira. + * hello.s (pass): Use softune syntax for tira. + +Thu Aug 19 18:00:16 1999 Dave Brolley + + * hello.s: Fix sethi, setlo insn usage. + +Mon Jun 21 17:33:37 1999 Dave Brolley + + * Makefile.in (TESTS): Add grloop.ok. + * grloop.s: New testcase. + +Fri Jun 18 17:55:02 1999 Dave Brolley + + * exit47.s: Use proper syscalls interface. + * hello.s: Use proper syscalls interface. + +Mon May 31 12:03:38 1999 Dave Brolley + + * hello.s,loop.s,exit47.s: Convert to frv insn set. + +Thu May 6 16:36:30 1999 Dave Brolley + + * Directory created. + diff --git a/sim/testsuite/frv-elf/Makefile.in b/sim/testsuite/frv-elf/Makefile.in new file mode 100644 index 0000000..795bdd1 --- /dev/null +++ b/sim/testsuite/frv-elf/Makefile.in @@ -0,0 +1,159 @@ +# Makefile for regression testing the frv simulator. +# Copyright (C) 1998 Free Software Foundation, Inc. + +# This file is part of GDB. + +# GDB is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2, or (at your option) +# any later version. + +# GDB is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. + +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +VPATH = @srcdir@ +srcdir = @srcdir@ +srcroot = $(srcdir)/../../.. + +prefix = @prefix@ +exec_prefix = @exec_prefix@ + +host_alias = @host_alias@ +target_alias = @target_alias@ +program_transform_name = @program_transform_name@ +build_canonical = @build@ +host_canonical = @host@ +target_canonical = @target@ +target_cpu = @target_cpu@ + + +SHELL = @SHELL@ +SUBDIRS = @subdirs@ +RPATH_ENVVAR = @RPATH_ENVVAR@ + +EXPECT = `if [ -f ../../../expect/expect ] ; then \ + echo ../../../expect/expect ; \ + else echo expect ; fi` + +RUNTEST = $(RUNTEST_FOR_TARGET) + +RUNTESTFLAGS = + +RUNTEST_FOR_TARGET = `\ + if [ -f $${srcroot}/dejagnu/runtest ]; then \ + echo $${srcroot}/dejagnu/runtest; \ + else \ + if [ "$(host_canonical)" = "$(target_canonical)" ]; then \ + echo runtest; \ + else \ + t='$(program_transform_name)'; echo runtest | sed -e '' $$t; \ + fi; \ + fi` + + +AS_FOR_TARGET = `\ + if [ -x ../../../gas/as-new ]; then \ + echo ../../../gas/as-new ; \ + else \ + echo $(target_alias)-as ; \ + fi` + +LD_FOR_TARGET = `\ + if [ -x ../../../ld/ld-new ]; then \ + echo ../../../ld/ld-new ; \ + else \ + echo $(target_alias)-ld ; \ + fi` + +RUN_FOR_TARGET = `\ + if [ -x ../../../sim/${target_cpu}/run ]; then \ + echo ../../../sim/${target_cpu}/run ; \ + else \ + echo $(target_alias)-run ; \ + fi` + +TESTS = \ + exit47.ko \ + grloop.ok \ + hello.ok + + +check: sanity $(TESTS) +sanity: + @eval echo AS_FOR_TARGET = $(AS_FOR_TARGET) + @eval echo LD_FOR_TARGET = $(LD_FOR_TARGET) + @eval echo RUN_FOR_TARGET = $(RUN_FOR_TARGET) + + + +# Rules for running all the tests, put into three types +# exit success, exit fail, print "Hello World" + +.u.log: + uudecode $*.u + $(RUN_FOR_TARGET) $* > $*.log + + +# Rules for running the tests + +.SUFFIXES: .u .ok .run .hi .ko +.run.ok: + rm -f tmp-$* $*.hi + ulimit -t 5 ; $(RUN_FOR_TARGET) $*.run > tmp-$* + mv tmp-$* $*.ok +.run.hi: + rm -f tmp-$* $*.hi diff-$* + ulimit -t 5 ; $(RUN_FOR_TARGET) $*.run > tmp-$* + echo "Hello World" | diff - tmp-$* > diff-$* + cat tmp-$* diff-$* > $*.hi +.run.ko: + rm -f tmp-$* $*.ko + set +e ; \ + ulimit -t 5 ; $(RUN_FOR_TARGET) $*.run > tmp-$* ; \ + if [ $$? -eq 47 ] ; then \ + exit 0 ; \ + else \ + exit 1 ; \ + fi + mv tmp-$* $*.ko + + +# Rules for building all the tests and packing them into +# uuencoded files. + +uuencode: em-pstr.u em-e0.u em-e47.u em-pchr.u + +.SUFFIXES: .u .s .run +.s.u: + rm -f $*.o $*.run + $(AS_FOR_TARGET) $(srcdir)/$*.s -o $*.o + $(LD_FOR_TARGET) -o $* $*.o + uuencode < $* $* > $*.u + rm -f $*.o $* +.s.run: + rm -f $*.o $*.run + $(AS_FOR_TARGET) $(srcdir)/$*.s -o $*.o + $(LD_FOR_TARGET) -o $*.run $*.o + rm -f $*.o $* + + +clean mostlyclean: + rm -f *~ core *.o a.out + rm -f $(TESTS) + +distclean maintainer-clean realclean: clean + rm -f *~ core + rm -f Makefile config.status *-init.exp + rm -fr *.log summary detail *.plog *.sum *.psum site.* + +Makefile : Makefile.in config.status + $(SHELL) config.status + +config.status: configure + $(SHELL) config.status --recheck diff --git a/sim/testsuite/frv-elf/cache.s b/sim/testsuite/frv-elf/cache.s new file mode 100644 index 0000000..2ed0e1e --- /dev/null +++ b/sim/testsuite/frv-elf/cache.s @@ -0,0 +1,164 @@ +# run with --memory-region 0xff000000,4 --memory-region 0xfe000000,00404000 +; Exit with return code + .macro exit rc + setlos.p #1,gr7 + setlos \rc,gr8 + tira gr0,#0 + .endm + +; Pass the test case + .macro pass +pass: + setlos.p #5,gr10 + setlos #1,gr8 + setlos #5,gr7 + sethi.p %hi(passmsg),gr9 + setlo %lo(passmsg),gr9 + tira gr0,#0 + exit #0 + .endm + +; Fail the testcase + .macro fail +fail\@: + setlos.p #5,gr10 + setlos #1,gr8 + setlos #5,gr7 + sethi.p %hi(failmsg),gr9 + setlo %lo(failmsg),gr9 + tira gr0,#0 + exit #1 + .endm + + .data +failmsg: + .ascii "fail\n" +passmsg: + .ascii "pass\n" + + .text + .global _start +_start: + movsg hsr0,gr10 ; enable insn and data caches + sethi.p 0xc800,gr11 ; in copy-back mode + setlo 0x0000,gr11 + or gr10,gr11,gr10 + movgs gr10,hsr0 + + sethi.p 0x7,sp + setlo 0x0000,sp + + ; fill the cache + sethi.p %hi(done1),gr10 + setlo %lo(done1),gr10 + movgs gr10,lr + setlos.p 0x1000,gr10 + setlos 0x0,gr11 + movgs gr10,lcr +write1: st.p gr11,@(sp,gr11) + addi.p gr11,4,gr11 + bctrlr.p 1,0 + bra write1 +done1: + ; read it back + sethi.p %hi(done2),gr10 + setlo %lo(done2),gr10 + movgs gr10,lr + setlos.p 0x1000,gr10 + setlos 0x0,gr11 + movgs gr10,lcr +read1: ld @(sp,gr11),gr12 + cmp gr11,gr12,icc0 + bne icc0,1,fail + addi.p gr11,4,gr11 + bctrlr.p 1,0 + bra read1 +done2: + + ; fill the cache twice + sethi.p %hi(done3),gr10 + setlo %lo(done3),gr10 + movgs gr10,lr + setlos.p 0x2000,gr10 + setlos 0x0,gr11 + movgs gr10,lcr +write3: st.p gr11,@(sp,gr11) + addi.p gr11,4,gr11 + bctrlr.p 1,0 + bra write3 +done3: + ; read it back + sethi.p %hi(done4),gr10 + setlo %lo(done4),gr10 + movgs gr10,lr + setlos.p 0x2000,gr10 + setlos 0x0,gr11 + movgs gr10,lcr +read4: ld @(sp,gr11),gr12 + cmp gr11,gr12,icc0 + bne icc0,1,fail + addi.p gr11,4,gr11 + bctrlr.p 1,0 + bra read4 +done4: + ; read it back in reverse + sethi.p %hi(done5),gr10 + setlo %lo(done5),gr10 + movgs gr10,lr + setlos.p 0x2000,gr10 + setlos 0x7ffc,gr11 + movgs gr10,lcr +read5: ld @(sp,gr11),gr12 + cmp gr11,gr12,icc0 + bne icc0,1,fail + subi.p gr11,4,gr11 + bctrlr.p 1,0 + bra read5 +done5: + + ; access data and insns in non-cache areas + sethi.p 0x8038,gr11 ; bctrlr 0,0 + setlo 0x2000,gr11 + + sethi.p 0xff00,gr10 ; documented area + setlo 0x0000,gr10 + sti gr11,@(gr10,0) + jmpl @(gr10,gr0) + + ; enable RAM mode + movsg hsr0,gr10 + sethi.p 0x0040,gr12 + setlo 0x0000,gr12 + or gr10,gr12,gr10 + movgs gr10,hsr0 + + sethi.p 0xfe00,gr10 ; documented area + setlo 0x0400,gr10 + sti gr11,@(gr10,0) + jmpl @(gr10,gr0) + + sethi.p 0xfe40,gr10 ; documented area + setlo 0x0400,gr10 + sti gr11,@(gr10,0) + dcf @(gr10,gr0) + jmpl @(gr10,gr0) + + sethi.p 0x0007,gr10 ; non RAM area + setlo 0x0000,gr10 + sti gr11,@(gr10,0) + jmpl @(gr10,gr0) + + sethi.p 0xfe00,gr10 ; insn RAM area + setlo 0x0000,gr10 + sti gr11,@(gr10,0) + jmpl @(gr10,gr0) + + sethi.p 0xfe40,gr10 ; data RAM area + setlo 0x0000,gr10 + sti gr11,@(gr10,0) + dcf @(gr10,gr0) + jmpl @(gr10,gr0) + + pass +fail: + fail diff --git a/sim/testsuite/frv-elf/configure b/sim/testsuite/frv-elf/configure new file mode 100755 index 0000000..25c2793 --- /dev/null +++ b/sim/testsuite/frv-elf/configure @@ -0,0 +1,905 @@ +#! /bin/sh + +# Guess values for system-dependent variables and create Makefiles. +# Generated automatically using autoconf version 2.13 +# Copyright (C) 1992, 93, 94, 95, 96 Free Software Foundation, Inc. +# +# This configure script is free software; the Free Software Foundation +# gives unlimited permission to copy, distribute and modify it. + +# Defaults: +ac_help= +ac_default_prefix=/usr/local +# Any additions from configure.in: + +# Initialize some variables set by options. +# The variables have the same names as the options, with +# dashes changed to underlines. +build=NONE +cache_file=./config.cache +exec_prefix=NONE +host=NONE +no_create= +nonopt=NONE +no_recursion= +prefix=NONE +program_prefix=NONE +program_suffix=NONE +program_transform_name=s,x,x, +silent= +site= +srcdir= +target=NONE +verbose= +x_includes=NONE +x_libraries=NONE +bindir='${exec_prefix}/bin' +sbindir='${exec_prefix}/sbin' +libexecdir='${exec_prefix}/libexec' +datadir='${prefix}/share' +sysconfdir='${prefix}/etc' +sharedstatedir='${prefix}/com' +localstatedir='${prefix}/var' +libdir='${exec_prefix}/lib' +includedir='${prefix}/include' +oldincludedir='/usr/include' +infodir='${prefix}/info' +mandir='${prefix}/man' + +# Initialize some other variables. +subdirs= +MFLAGS= MAKEFLAGS= +SHELL=${CONFIG_SHELL-/bin/sh} +# Maximum number of lines to put in a shell here document. +ac_max_here_lines=12 + +ac_prev= +for ac_option +do + + # If the previous option needs an argument, assign it. + if test -n "$ac_prev"; then + eval "$ac_prev=\$ac_option" + ac_prev= + continue + fi + + case "$ac_option" in + -*=*) ac_optarg=`echo "$ac_option" | sed 's/[-_a-zA-Z0-9]*=//'` ;; + *) ac_optarg= ;; + esac + + # Accept the important Cygnus configure options, so we can diagnose typos. + + case "$ac_option" in + + -bindir | --bindir | --bindi | --bind | --bin | --bi) + ac_prev=bindir ;; + -bindir=* | --bindir=* | --bindi=* | --bind=* | --bin=* | --bi=*) + bindir="$ac_optarg" ;; + + -build | --build | --buil | --bui | --bu) + ac_prev=build ;; + -build=* | --build=* | --buil=* | --bui=* | --bu=*) + build="$ac_optarg" ;; + + -cache-file | --cache-file | --cache-fil | --cache-fi \ + | --cache-f | --cache- | --cache | --cach | --cac | --ca | --c) + ac_prev=cache_file ;; + -cache-file=* | --cache-file=* | --cache-fil=* | --cache-fi=* \ + | --cache-f=* | --cache-=* | --cache=* | --cach=* | --cac=* | --ca=* | --c=*) + cache_file="$ac_optarg" ;; + + -datadir | --datadir | --datadi | --datad | --data | --dat | --da) + ac_prev=datadir ;; + -datadir=* | --datadir=* | --datadi=* | --datad=* | --data=* | --dat=* \ + | --da=*) + datadir="$ac_optarg" ;; + + -disable-* | --disable-*) + ac_feature=`echo $ac_option|sed -e 's/-*disable-//'` + # Reject names that are not valid shell variable names. + if test -n "`echo $ac_feature| sed 's/[-a-zA-Z0-9_]//g'`"; then + { echo "configure: error: $ac_feature: invalid feature name" 1>&2; exit 1; } + fi + ac_feature=`echo $ac_feature| sed 's/-/_/g'` + eval "enable_${ac_feature}=no" ;; + + -enable-* | --enable-*) + ac_feature=`echo $ac_option|sed -e 's/-*enable-//' -e 's/=.*//'` + # Reject names that are not valid shell variable names. + if test -n "`echo $ac_feature| sed 's/[-_a-zA-Z0-9]//g'`"; then + { echo "configure: error: $ac_feature: invalid feature name" 1>&2; exit 1; } + fi + ac_feature=`echo $ac_feature| sed 's/-/_/g'` + case "$ac_option" in + *=*) ;; + *) ac_optarg=yes ;; + esac + eval "enable_${ac_feature}='$ac_optarg'" ;; + + -exec-prefix | --exec_prefix | --exec-prefix | --exec-prefi \ + | --exec-pref | --exec-pre | --exec-pr | --exec-p | --exec- \ + | --exec | --exe | --ex) + ac_prev=exec_prefix ;; + -exec-prefix=* | --exec_prefix=* | --exec-prefix=* | --exec-prefi=* \ + | --exec-pref=* | --exec-pre=* | --exec-pr=* | --exec-p=* | --exec-=* \ + | --exec=* | --exe=* | --ex=*) + exec_prefix="$ac_optarg" ;; + + -gas | --gas | --ga | --g) + # Obsolete; use --with-gas. + with_gas=yes ;; + + -help | --help | --hel | --he) + # Omit some internal or obsolete options to make the list less imposing. + # This message is too long to be a string in the A/UX 3.1 sh. + cat << EOF +Usage: configure [options] [host] +Options: [defaults in brackets after descriptions] +Configuration: + --cache-file=FILE cache test results in FILE + --help print this message + --no-create do not create output files + --quiet, --silent do not print \`checking...' messages + --version print the version of autoconf that created configure +Directory and file names: + --prefix=PREFIX install architecture-independent files in PREFIX + [$ac_default_prefix] + --exec-prefix=EPREFIX install architecture-dependent files in EPREFIX + [same as prefix] + --bindir=DIR user executables in DIR [EPREFIX/bin] + --sbindir=DIR system admin executables in DIR [EPREFIX/sbin] + --libexecdir=DIR program executables in DIR [EPREFIX/libexec] + --datadir=DIR read-only architecture-independent data in DIR + [PREFIX/share] + --sysconfdir=DIR read-only single-machine data in DIR [PREFIX/etc] + --sharedstatedir=DIR modifiable architecture-independent data in DIR + [PREFIX/com] + --localstatedir=DIR modifiable single-machine data in DIR [PREFIX/var] + --libdir=DIR object code libraries in DIR [EPREFIX/lib] + --includedir=DIR C header files in DIR [PREFIX/include] + --oldincludedir=DIR C header files for non-gcc in DIR [/usr/include] + --infodir=DIR info documentation in DIR [PREFIX/info] + --mandir=DIR man documentation in DIR [PREFIX/man] + --srcdir=DIR find the sources in DIR [configure dir or ..] + --program-prefix=PREFIX prepend PREFIX to installed program names + --program-suffix=SUFFIX append SUFFIX to installed program names + --program-transform-name=PROGRAM + run sed PROGRAM on installed program names +EOF + cat << EOF +Host type: + --build=BUILD configure for building on BUILD [BUILD=HOST] + --host=HOST configure for HOST [guessed] + --target=TARGET configure for TARGET [TARGET=HOST] +Features and packages: + --disable-FEATURE do not include FEATURE (same as --enable-FEATURE=no) + --enable-FEATURE[=ARG] include FEATURE [ARG=yes] + --with-PACKAGE[=ARG] use PACKAGE [ARG=yes] + --without-PACKAGE do not use PACKAGE (same as --with-PACKAGE=no) + --x-includes=DIR X include files are in DIR + --x-libraries=DIR X library files are in DIR +EOF + if test -n "$ac_help"; then + echo "--enable and --with options recognized:$ac_help" + fi + exit 0 ;; + + -host | --host | --hos | --ho) + ac_prev=host ;; + -host=* | --host=* | --hos=* | --ho=*) + host="$ac_optarg" ;; + + -includedir | --includedir | --includedi | --included | --include \ + | --includ | --inclu | --incl | --inc) + ac_prev=includedir ;; + -includedir=* | --includedir=* | --includedi=* | --included=* | --include=* \ + | --includ=* | --inclu=* | --incl=* | --inc=*) + includedir="$ac_optarg" ;; + + -infodir | --infodir | --infodi | --infod | --info | --inf) + ac_prev=infodir ;; + -infodir=* | --infodir=* | --infodi=* | --infod=* | --info=* | --inf=*) + infodir="$ac_optarg" ;; + + -libdir | --libdir | --libdi | --libd) + ac_prev=libdir ;; + -libdir=* | --libdir=* | --libdi=* | --libd=*) + libdir="$ac_optarg" ;; + + -libexecdir | --libexecdir | --libexecdi | --libexecd | --libexec \ + | --libexe | --libex | --libe) + ac_prev=libexecdir ;; + -libexecdir=* | --libexecdir=* | --libexecdi=* | --libexecd=* | --libexec=* \ + | --libexe=* | --libex=* | --libe=*) + libexecdir="$ac_optarg" ;; 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then + echo "configure: warning: $ac_option: invalid host type" 1>&2 + fi + if test "x$nonopt" != xNONE; then + { echo "configure: error: can only configure for one host and one target at a time" 1>&2; exit 1; } + fi + nonopt="$ac_option" + ;; + + esac +done + +if test -n "$ac_prev"; then + { echo "configure: error: missing argument to --`echo $ac_prev | sed 's/_/-/g'`" 1>&2; exit 1; } +fi + +trap 'rm -fr conftest* confdefs* core core.* *.core $ac_clean_files; exit 1' 1 2 15 + +# File descriptor usage: +# 0 standard input +# 1 file creation +# 2 errors and warnings +# 3 some systems may open it to /dev/tty +# 4 used on the Kubota Titan +# 6 checking for... messages and results +# 5 compiler messages saved in config.log +if test "$silent" = yes; then + exec 6>/dev/null +else + exec 6>&1 +fi +exec 5>./config.log + +echo "\ +This file contains any messages produced by compilers while +running configure, to aid debugging if configure makes a mistake. +" 1>&5 + +# Strip out --no-create and --no-recursion so they do not pile up. +# Also quote any args containing shell metacharacters. +ac_configure_args= +for ac_arg +do + case "$ac_arg" in + -no-create | --no-create | --no-creat | --no-crea | --no-cre \ + | --no-cr | --no-c) ;; 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You are not allowed to specify --host, --target, and nonopt at the +# same time. +# 2. Host defaults to nonopt. +# 3. If nonopt is not specified, then host defaults to the current host, +# as determined by config.guess. +# 4. Target and build default to nonopt. +# 5. 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It is not useful on other systems. +# If it contains results you don't want to keep, you may remove or edit it. +# +# By default, configure uses ./config.cache as the cache file, +# creating it if it does not exist already. You can give configure +# the --cache-file=FILE option to use a different cache file; that is +# what configure does when it calls configure scripts in +# subdirectories, so they share the cache. +# Giving --cache-file=/dev/null disables caching, for debugging configure. +# config.status only pays attention to the cache file if you give it the +# --recheck option to rerun configure. +# +EOF +# The following way of writing the cache mishandles newlines in values, +# but we know of no workaround that is simple, portable, and efficient. +# So, don't put newlines in cache variables' values. +# Ultrix sh set writes to stderr and can't be redirected directly, +# and sets the high bit in the cache file unless we assign to the vars. +(set) 2>&1 | + case `(ac_space=' '; set | grep ac_space) 2>&1` in + *ac_space=\ *) + # `set' does not quote correctly, so add quotes (double-quote substitution + # turns \\\\ into \\, and sed turns \\ into \). + sed -n \ + -e "s/'/'\\\\''/g" \ + -e "s/^\\([a-zA-Z0-9_]*_cv_[a-zA-Z0-9_]*\\)=\\(.*\\)/\\1=\${\\1='\\2'}/p" + ;; + *) + # `set' quotes correctly as required by POSIX, so do not add quotes. + sed -n -e 's/^\([a-zA-Z0-9_]*_cv_[a-zA-Z0-9_]*\)=\(.*\)/\1=${\1=\2}/p' + ;; + esac >> confcache +if cmp -s $cache_file confcache; then + : +else + if test -w $cache_file; then + echo "updating cache $cache_file" + cat confcache > $cache_file + else + echo "not updating unwritable cache $cache_file" + fi +fi +rm -f confcache + +trap 'rm -fr conftest* confdefs* core core.* *.core $ac_clean_files; exit 1' 1 2 15 + +test "x$prefix" = xNONE && prefix=$ac_default_prefix +# Let make expand exec_prefix. +test "x$exec_prefix" = xNONE && exec_prefix='${prefix}' + +# Any assignment to VPATH causes Sun make to only execute +# the first set of double-colon rules, so remove it if not needed. +# If there is a colon in the path, we need to keep it. +if test "x$srcdir" = x.; then + ac_vpsub='/^[ ]*VPATH[ ]*=[^:]*$/d' +fi + +trap 'rm -f $CONFIG_STATUS conftest*; exit 1' 1 2 15 + +# Transform confdefs.h into DEFS. +# Protect against shell expansion while executing Makefile rules. +# Protect against Makefile macro expansion. +cat > conftest.defs <<\EOF +s%#define \([A-Za-z_][A-Za-z0-9_]*\) *\(.*\)%-D\1=\2%g +s%[ `~#$^&*(){}\\|;'"<>?]%\\&%g +s%\[%\\&%g +s%\]%\\&%g +s%\$%$$%g +EOF +DEFS=`sed -f conftest.defs confdefs.h | tr '\012' ' '` +rm -f conftest.defs + + +# Without the "./", some shells look in PATH for config.status. +: ${CONFIG_STATUS=./config.status} + +echo creating $CONFIG_STATUS +rm -f $CONFIG_STATUS +cat > $CONFIG_STATUS </dev/null | sed 1q`: +# +# $0 $ac_configure_args +# +# Compiler output produced by configure, useful for debugging +# configure, is in ./config.log if it exists. + +ac_cs_usage="Usage: $CONFIG_STATUS [--recheck] [--version] [--help]" +for ac_option +do + case "\$ac_option" in + -recheck | --recheck | --rechec | --reche | --rech | --rec | --re | --r) + echo "running \${CONFIG_SHELL-/bin/sh} $0 $ac_configure_args --no-create --no-recursion" + exec \${CONFIG_SHELL-/bin/sh} $0 $ac_configure_args --no-create --no-recursion ;; + -version | --version | --versio | --versi | --vers | --ver | --ve | --v) + echo "$CONFIG_STATUS generated by autoconf version 2.13" + exit 0 ;; + -help | --help | --hel | --he | --h) + echo "\$ac_cs_usage"; exit 0 ;; + *) echo "\$ac_cs_usage"; exit 1 ;; + esac +done + +ac_given_srcdir=$srcdir + +trap 'rm -fr `echo "Makefile" | sed "s/:[^ ]*//g"` conftest*; exit 1' 1 2 15 +EOF +cat >> $CONFIG_STATUS < conftest.subs <<\\CEOF +$ac_vpsub +$extrasub +s%@SHELL@%$SHELL%g +s%@CFLAGS@%$CFLAGS%g +s%@CPPFLAGS@%$CPPFLAGS%g +s%@CXXFLAGS@%$CXXFLAGS%g +s%@FFLAGS@%$FFLAGS%g +s%@DEFS@%$DEFS%g +s%@LDFLAGS@%$LDFLAGS%g +s%@LIBS@%$LIBS%g +s%@exec_prefix@%$exec_prefix%g +s%@prefix@%$prefix%g +s%@program_transform_name@%$program_transform_name%g +s%@bindir@%$bindir%g +s%@sbindir@%$sbindir%g +s%@libexecdir@%$libexecdir%g +s%@datadir@%$datadir%g +s%@sysconfdir@%$sysconfdir%g +s%@sharedstatedir@%$sharedstatedir%g +s%@localstatedir@%$localstatedir%g +s%@libdir@%$libdir%g +s%@includedir@%$includedir%g +s%@oldincludedir@%$oldincludedir%g +s%@infodir@%$infodir%g +s%@mandir@%$mandir%g +s%@CC@%$CC%g +s%@host@%$host%g +s%@host_alias@%$host_alias%g +s%@host_cpu@%$host_cpu%g +s%@host_vendor@%$host_vendor%g +s%@host_os@%$host_os%g +s%@target@%$target%g +s%@target_alias@%$target_alias%g +s%@target_cpu@%$target_cpu%g +s%@target_vendor@%$target_vendor%g +s%@target_os@%$target_os%g +s%@build@%$build%g +s%@build_alias@%$build_alias%g +s%@build_cpu@%$build_cpu%g +s%@build_vendor@%$build_vendor%g +s%@build_os@%$build_os%g + +CEOF +EOF + +cat >> $CONFIG_STATUS <<\EOF + +# Split the substitutions into bite-sized pieces for seds with +# small command number limits, like on Digital OSF/1 and HP-UX. +ac_max_sed_cmds=90 # Maximum number of lines to put in a sed script. +ac_file=1 # Number of current file. +ac_beg=1 # First line for current file. +ac_end=$ac_max_sed_cmds # Line after last line for current file. +ac_more_lines=: +ac_sed_cmds="" +while $ac_more_lines; do + if test $ac_beg -gt 1; then + sed "1,${ac_beg}d; ${ac_end}q" conftest.subs > conftest.s$ac_file + else + sed "${ac_end}q" conftest.subs > conftest.s$ac_file + fi + if test ! -s conftest.s$ac_file; then + ac_more_lines=false + rm -f conftest.s$ac_file + else + if test -z "$ac_sed_cmds"; then + ac_sed_cmds="sed -f conftest.s$ac_file" + else + ac_sed_cmds="$ac_sed_cmds | sed -f conftest.s$ac_file" + fi + ac_file=`expr $ac_file + 1` + ac_beg=$ac_end + ac_end=`expr $ac_end + $ac_max_sed_cmds` + fi +done +if test -z "$ac_sed_cmds"; then + ac_sed_cmds=cat +fi +EOF + +cat >> $CONFIG_STATUS <> $CONFIG_STATUS <<\EOF +for ac_file in .. $CONFIG_FILES; do if test "x$ac_file" != x..; then + # Support "outfile[:infile[:infile...]]", defaulting infile="outfile.in". + case "$ac_file" in + *:*) ac_file_in=`echo "$ac_file"|sed 's%[^:]*:%%'` + ac_file=`echo "$ac_file"|sed 's%:.*%%'` ;; + *) ac_file_in="${ac_file}.in" ;; + esac + + # Adjust a relative srcdir, top_srcdir, and INSTALL for subdirectories. + + # Remove last slash and all that follows it. Not all systems have dirname. + ac_dir=`echo $ac_file|sed 's%/[^/][^/]*$%%'` + if test "$ac_dir" != "$ac_file" && test "$ac_dir" != .; then + # The file is in a subdirectory. + test ! -d "$ac_dir" && mkdir "$ac_dir" + ac_dir_suffix="/`echo $ac_dir|sed 's%^\./%%'`" + # A "../" for each directory in $ac_dir_suffix. + ac_dots=`echo $ac_dir_suffix|sed 's%/[^/]*%../%g'` + else + ac_dir_suffix= ac_dots= + fi + + case "$ac_given_srcdir" in + .) srcdir=. + if test -z "$ac_dots"; then top_srcdir=. + else top_srcdir=`echo $ac_dots|sed 's%/$%%'`; fi ;; + /*) srcdir="$ac_given_srcdir$ac_dir_suffix"; top_srcdir="$ac_given_srcdir" ;; + *) # Relative path. + srcdir="$ac_dots$ac_given_srcdir$ac_dir_suffix" + top_srcdir="$ac_dots$ac_given_srcdir" ;; + esac + + + echo creating "$ac_file" + rm -f "$ac_file" + configure_input="Generated automatically from `echo $ac_file_in|sed 's%.*/%%'` by configure." + case "$ac_file" in + *Makefile*) ac_comsub="1i\\ +# $configure_input" ;; + *) ac_comsub= ;; + esac + + ac_file_inputs=`echo $ac_file_in|sed -e "s%^%$ac_given_srcdir/%" -e "s%:% $ac_given_srcdir/%g"` + sed -e "$ac_comsub +s%@configure_input@%$configure_input%g +s%@srcdir@%$srcdir%g +s%@top_srcdir@%$top_srcdir%g +" $ac_file_inputs | (eval "$ac_sed_cmds") > $ac_file +fi; done +rm -f conftest.s* + +EOF +cat >> $CONFIG_STATUS <> $CONFIG_STATUS <<\EOF + +exit 0 +EOF +chmod +x $CONFIG_STATUS +rm -fr confdefs* $ac_clean_files +test "$no_create" = yes || ${CONFIG_SHELL-/bin/sh} $CONFIG_STATUS || exit 1 + diff --git a/sim/testsuite/frv-elf/configure.in b/sim/testsuite/frv-elf/configure.in new file mode 100644 index 0000000..e74389e --- /dev/null +++ b/sim/testsuite/frv-elf/configure.in @@ -0,0 +1,19 @@ +dnl Process this file file with autoconf to produce a configure script. +dnl This file is a shell script fragment that supplies the information +dnl necessary to tailor a template configure script into the configure +dnl script appropriate for this directory. For more information, check +dnl any existing configure script. + +AC_PREREQ(2.5) +dnl FIXME - think of a truly uniq file to this directory +AC_INIT(Makefile.in) + +CC=${CC-cc} +AC_SUBST(CC) +AC_CONFIG_AUX_DIR(`cd $srcdir;pwd`/../../..) +AC_CANONICAL_SYSTEM + +AC_SUBST(target_cpu) + + +AC_OUTPUT(Makefile) diff --git a/sim/testsuite/frv-elf/exit47.s b/sim/testsuite/frv-elf/exit47.s new file mode 100644 index 0000000..70e56b3 --- /dev/null +++ b/sim/testsuite/frv-elf/exit47.s @@ -0,0 +1,5 @@ + .global _start +_start: + setlos #47,gr8 + setlos #1,gr7 + tira gr0,#0 diff --git a/sim/testsuite/frv-elf/grloop.s b/sim/testsuite/frv-elf/grloop.s new file mode 100644 index 0000000..844ad1d --- /dev/null +++ b/sim/testsuite/frv-elf/grloop.s @@ -0,0 +1,10 @@ + .global _start +_start: + setlo 0x0400,gr10 +loop: + addicc gr10,-1,gr10,icc0 + bne icc0,0,loop +; exit (0) + setlos #0,gr8 + setlos #1,gr7 + tira gr0,#0 diff --git a/sim/testsuite/frv-elf/hello.s b/sim/testsuite/frv-elf/hello.s new file mode 100644 index 0000000..0151feb --- /dev/null +++ b/sim/testsuite/frv-elf/hello.s @@ -0,0 +1,16 @@ + .global _start +_start: + +; write (hello world) + setlos #14,gr10 + sethi %hi(hello),gr9 + setlo %lo(hello),gr9 + setlos #1,gr8 + setlos #5,gr7 + tira gr0,#0 +; exit (0) + setlos #0,gr8 + setlos #1,gr7 + tira gr0,#0 + +hello: .ascii "Hello World!\r\n" diff --git a/sim/testsuite/frv-elf/loop.s b/sim/testsuite/frv-elf/loop.s new file mode 100644 index 0000000..8489c13 --- /dev/null +++ b/sim/testsuite/frv-elf/loop.s @@ -0,0 +1,2 @@ + .global _start +_start: bra icc0,0,_start diff --git a/sim/testsuite/sim/arm/adc.cgs b/sim/testsuite/sim/arm/adc.cgs new file mode 100644 index 0000000..b6659a1 --- /dev/null +++ b/sim/testsuite/sim/arm/adc.cgs @@ -0,0 +1,43 @@ +# arm testcase for adc +# mach: all + +# ??? Unfinished, more tests needed. + + .include "testutils.inc" + + start + +# adc$cond${set-cc?} $rd,$rn,$imm12 + + .global adc_imm +adc_imm: + mvi_h_gr r4,1 + mvi_h_cnvz 0,0,0,0 + adc r5,r4,#1 + test_h_cnvz 0,0,0,0 + test_h_gr r5,2 + +# adc$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm} + + .global adc_reg_imm_shift +adc_reg_imm_shift: + mvi_h_gr r4,1 + mvi_h_gr r5,1 + mvi_h_cnvz 0,0,0,0 + adc r6,r4,r5,lsl #2 + test_h_cnvz 0,0,0,0 + test_h_gr r6,5 + +# adc$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg} + + .global adc_reg_reg_shift +adc_reg_reg_shift: + mvi_h_gr r4,1 + mvi_h_gr r5,1 + mvi_h_gr r6,2 + mvi_h_cnvz 0,0,0,0 + adc r7,r4,r5,lsl r6 + test_h_cnvz 0,0,0,0 + test_h_gr r7,5 + + pass diff --git a/sim/testsuite/sim/arm/add.cgs b/sim/testsuite/sim/arm/add.cgs new file mode 100644 index 0000000..eba32e0 --- /dev/null +++ b/sim/testsuite/sim/arm/add.cgs @@ -0,0 +1,43 @@ +# arm testcase for add +# mach: all + +# ??? Unfinished, more tests needed. + + .include "testutils.inc" + + start + +# add$cond${set-cc?} $rd,$rn,$imm12 + + .global add_imm +add_imm: + mvi_h_gr r4,1 + mvi_h_cnvz 0,0,0,0 + add r5,r4,#1 + test_h_cnvz 0,0,0,0 + test_h_gr r5,2 + +# add$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm} + + .global add_reg_imm_shift +add_reg_imm_shift: + mvi_h_gr r4,1 + mvi_h_gr r5,1 + mvi_h_cnvz 0,0,0,0 + add r6,r4,r5,lsl #2 + test_h_cnvz 0,0,0,0 + test_h_gr r6,5 + +# add$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg} + + .global add_reg_reg_shift +add_reg_reg_shift: + mvi_h_gr r4,1 + mvi_h_gr r5,1 + mvi_h_gr r6,2 + mvi_h_cnvz 0,0,0,0 + add r7,r4,r5,lsl r6 + test_h_cnvz 0,0,0,0 + test_h_gr r7,5 + + pass diff --git a/sim/testsuite/sim/arm/allinsn.exp b/sim/testsuite/sim/arm/allinsn.exp new file mode 100644 index 0000000..ec8402f --- /dev/null +++ b/sim/testsuite/sim/arm/allinsn.exp @@ -0,0 +1,28 @@ +# ARM simulator testsuite. + +if { [istarget arm*-*-*] || [istarget xscale*-*-*] } { + # load support procs (none yet) + # load_lib cgen.exp + + # all machines + set all_machs "xscale" + + if [is_remote host] { + remote_download host $srcdir/$subdir/testutils.inc + } + + # The .cgs suffix is for "cgen .s". + foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.cgs]] { + # If we're only testing specific files and this isn't one of them, + # skip it. + if ![runtest_file_p $runtests $src] { + continue + } + + run_sim_test $src $all_machs + } + + if [is_remote host] { + remote_file host delete testutils.inc + } +} diff --git a/sim/testsuite/sim/arm/and.cgs b/sim/testsuite/sim/arm/and.cgs new file mode 100644 index 0000000..cd8f003 --- /dev/null +++ b/sim/testsuite/sim/arm/and.cgs @@ -0,0 +1,43 @@ +# arm testcase for and +# mach: all + +# ??? Unfinished, more tests needed. + + .include "testutils.inc" + + start + +# and$cond${set-cc?} $rd,$rn,$imm12 + + .global and_imm +and_imm: + mvi_h_gr r4,1 + mvi_h_cnvz 0,0,0,0 + and r5,r4,#1 + test_h_cnvz 0,0,0,0 + test_h_gr r5,1 + +# and$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm} + + .global and_reg_imm_shift +and_reg_imm_shift: + mvi_h_gr r4,1 + mvi_h_gr r5,1 + mvi_h_cnvz 0,0,0,0 + and r6,r4,r5,lsl #1 + test_h_cnvz 0,0,0,0 + test_h_gr r6,0 + +# and$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg} + + .global and_reg_reg_shift +and_reg_reg_shift: + mvi_h_gr r4,1 + mvi_h_gr r5,1 + mvi_h_gr r6,1 + mvi_h_cnvz 0,0,0,0 + and r7,r4,r5,lsl r6 + test_h_cnvz 0,0,0,0 + test_h_gr r7,0 + + pass diff --git a/sim/testsuite/sim/arm/b.cgs b/sim/testsuite/sim/arm/b.cgs new file mode 100644 index 0000000..414b963 --- /dev/null +++ b/sim/testsuite/sim/arm/b.cgs @@ -0,0 +1,261 @@ +# arm testcase for b$cond $offset24 +# mach: all + +# ??? Still need to test edge cases. + + .include "testutils.inc" + + start + + .global b +b: + +# b foo + + b balways1 + fail +balways1: + +# beq foo + + mvi_h_gr r4,4 + mvi_h_gr r5,4 + cmp r4,r5 + beq beq1 + fail +beq1: + mvi_h_gr r5,5 + cmp r4,r5 + beq beq2 + b beq3 +beq2: + fail +beq3: + +# bne foo + + mvi_h_gr r4,4 + mvi_h_gr r5,5 + cmp r4,r5 + bne bne1 + fail +bne1: + mvi_h_gr r5,4 + cmp r4,r5 + bne bne2 + b bne3 +bne2: + fail +bne3: + +# bcs foo + + mvi_h_cnvz 1,0,0,0 + bcs bcs1 + fail +bcs1: + mvi_h_cnvz 0,0,0,0 + bcs bcs2 + b bcs3 +bcs2: + fail +bcs3: + +# bcc foo + + mvi_h_cnvz 0,0,0,0 + bcc bcc1 + fail +bcc1: + mvi_h_cnvz 1,0,0,0 + bcc bcc2 + b bcc3 +bcc2: + fail +bcc3: + +# bmi foo + + mvi_h_cnvz 0,1,0,0 + bmi bmi1 + fail +bmi1: + mvi_h_cnvz 0,0,0,0 + bmi bmi2 + b bmi3 +bmi2: + fail +bmi3: + +# bpl foo + + mvi_h_cnvz 0,0,0,0 + bpl bpl1 + fail +bpl1: + mvi_h_cnvz 0,1,0,0 + bpl bpl2 + b bpl3 +bpl2: + fail +bpl3: + +# bvs foo + + mvi_h_cnvz 0,0,1,0 + bvs bvs1 + fail +bvs1: + mvi_h_cnvz 0,0,0,0 + bvs bvs2 + b bvs3 +bvs2: + fail +bvs3: + +# bvc foo + + mvi_h_cnvz 0,0,0,0 + bvc bvc1 + fail +bvc1: + mvi_h_cnvz 0,0,1,0 + bvc bvc2 + b bvc3 +bvc2: + fail +bvc3: + +# bhi foo + + mvi_h_gr r4,5 + mvi_h_gr r5,4 + cmp r4,r5 + bhi bhi1 + fail +bhi1: + mvi_h_gr r5,5 + cmp r4,r5 + bhi bhi2 + b bhi3 +bhi2: + fail +bhi3: + mvi_h_gr r5,6 + cmp r4,r5 + bhi bhi4 + b bhi5 +bhi4: + fail +bhi5: + +# bls foo + + mvi_h_gr r4,4 + mvi_h_gr r5,5 + cmp r4,r5 + bls bls1 + fail +bls1: + mvi_h_gr r5,4 + cmp r4,r5 + bls bls2 + fail +bls2: + mvi_h_gr r5,3 + cmp r4,r5 + bls bls3 + b bls4 +bls3: + fail +bls4: + +# bge foo + + mvi_h_gr r4,4 + mvi_h_gr r5,4 + cmp r4,r5 + bge bge1 + fail +bge1: + mvi_h_gr r5,3 + cmp r4,r5 + bge bge2 + fail +bge2: + mvi_h_gr r5,5 + cmp r4,r5 + bge bge3 + b bge4 +bge3: + fail +bge4: + +# blt foo + + mvi_h_gr r4,4 + mvi_h_gr r5,5 + cmp r4,r5 + blt blt1 + fail +blt1: + mvi_h_gr r5,4 + cmp r4,r5 + blt blt2 + b blt3 +blt2: + fail +blt3: + mvi_h_gr r5,3 + cmp r4,r5 + blt blt4 + b blt5 +blt4: + fail +blt5: + +# bgt foo + + mvi_h_gr r4,4 + mvi_h_gr r5,3 + cmp r4,r5 + bgt bgt1 + fail +bgt1: + mvi_h_gr r5,4 + cmp r4,r5 + bgt bgt2 + b bgt3 +bgt2: + fail +bgt3: + mvi_h_gr r5,5 + cmp r4,r5 + bgt bgt4 + b bgt5 +bgt4: + fail +bgt5: + +# ble foo + + mvi_h_gr r4,4 + mvi_h_gr r5,4 + cmp r4,r5 + ble ble1 + fail +ble1: + mvi_h_gr r5,5 + cmp r4,r5 + ble ble2 + fail +ble2: + mvi_h_gr r5,3 + cmp r4,r5 + ble ble3 + b ble4 +ble3: + fail +ble4: + + pass diff --git a/sim/testsuite/sim/arm/bic.cgs b/sim/testsuite/sim/arm/bic.cgs new file mode 100644 index 0000000..37a9b6c --- /dev/null +++ b/sim/testsuite/sim/arm/bic.cgs @@ -0,0 +1,43 @@ +# arm testcase for bic +# mach: all + +# ??? Unfinished, more tests needed. + + .include "testutils.inc" + + start + +# bic$cond${set-cc?} $rd,$rn,$imm12 + + .global bic_imm +bic_imm: + mvi_h_gr r4,1 + mvi_h_cnvz 0,0,0,0 + bic r5,r4,#0 + test_h_cnvz 0,0,0,0 + test_h_gr r5,1 + +# bic$cond${set-cc?} $rd,$rn,$rm,${operbic2-shifttype} ${operbic2-shiftimm} + + .global bic_reg_imm_shift +bic_reg_imm_shift: + mvi_h_gr r4,7 + mvi_h_gr r5,1 + mvi_h_cnvz 0,0,0,0 + bic r6,r4,r5,lsl #1 + test_h_cnvz 0,0,0,0 + test_h_gr r6,5 + +# bic$cond${set-cc?} $rd,$rn,$rm,${operbic2-shifttype} ${operbic2-shiftreg} + + .global bic_reg_reg_shift +bic_reg_reg_shift: + mvi_h_gr r4,7 + mvi_h_gr r5,1 + mvi_h_gr r6,1 + mvi_h_cnvz 0,0,0,0 + bic r7,r4,r5,lsl r6 + test_h_cnvz 0,0,0,0 + test_h_gr r7,5 + + pass diff --git a/sim/testsuite/sim/arm/bl.cgs b/sim/testsuite/sim/arm/bl.cgs new file mode 100644 index 0000000..fbc7ef5 --- /dev/null +++ b/sim/testsuite/sim/arm/bl.cgs @@ -0,0 +1,21 @@ +# arm testcase for bl$cond $offset24 +# mach: all + + .include "testutils.inc" + + start + + .global bl +bl: + mvi_h_gr r14,0 + bl bl2 +bl1: + fail +bl2: + mvaddr_h_gr r4,bl1 + cmp r14,r4 + beq bl3 + fail +bl3: + + pass diff --git a/sim/testsuite/sim/arm/bx.cgs b/sim/testsuite/sim/arm/bx.cgs new file mode 100644 index 0000000..4c18af4 --- /dev/null +++ b/sim/testsuite/sim/arm/bx.cgs @@ -0,0 +1,12 @@ +# arm testcase for bx$cond $rn +# mach: unfinished + + .include "testutils.inc" + + start + + .global bx +bx: + bx0 pc + + pass diff --git a/sim/testsuite/sim/arm/cmn.cgs b/sim/testsuite/sim/arm/cmn.cgs new file mode 100644 index 0000000..1829fc7 --- /dev/null +++ b/sim/testsuite/sim/arm/cmn.cgs @@ -0,0 +1,36 @@ +# arm testcase for cmn${cond}${set-cc?} $rn,$imm12 +# mach: unfinished + + .include "testutils.inc" + + start + + .global cmn_imm +cmn_imm: + cmn00 pc,0 + + pass +# arm testcase for cmn$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm} +# mach: unfinished + + .include "testutils.inc" + + start + + .global cmn_reg_imm_shift +cmn_reg_imm_shift: + cmn00 pc,pc,pc,lsl 0 + + pass +# arm testcase for cmn$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg} +# mach: unfinished + + .include "testutils.inc" + + start + + .global cmn_reg_reg_shift +cmn_reg_reg_shift: + cmn00 pc,pc,pc,lsl pc + + pass diff --git a/sim/testsuite/sim/arm/cmp.cgs b/sim/testsuite/sim/arm/cmp.cgs new file mode 100644 index 0000000..ab9dd59 --- /dev/null +++ b/sim/testsuite/sim/arm/cmp.cgs @@ -0,0 +1,36 @@ +# arm testcase for cmp${cond}${set-cc?} $rn,$imm12 +# mach: unfinished + + .include "testutils.inc" + + start + + .global cmp_imm +cmp_imm: + cmp00 pc,0 + + pass +# arm testcase for cmp$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm} +# mach: unfinished + + .include "testutils.inc" + + start + + .global cmp_reg_imm_shift +cmp_reg_imm_shift: + cmp00 pc,pc,pc,lsl 0 + + pass +# arm testcase for cmp$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg} +# mach: unfinished + + .include "testutils.inc" + + start + + .global cmp_reg_reg_shift +cmp_reg_reg_shift: + cmp00 pc,pc,pc,lsl pc + + pass diff --git a/sim/testsuite/sim/arm/eor.cgs b/sim/testsuite/sim/arm/eor.cgs new file mode 100644 index 0000000..5bbb1c6 --- /dev/null +++ b/sim/testsuite/sim/arm/eor.cgs @@ -0,0 +1,36 @@ +# arm testcase for eor$cond${set-cc?} $rd,$rn,$imm12 +# mach: unfinished + + .include "testutils.inc" + + start + + .global eor_imm +eor_imm: + eor00 pc,pc,0 + + pass +# arm testcase for eor$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm} +# mach: unfinished + + .include "testutils.inc" + + start + + .global eor_reg_imm_shift +eor_reg_imm_shift: + eor00 pc,pc,pc,lsl 0 + + pass +# arm testcase for eor$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg} +# mach: unfinished + + .include "testutils.inc" + + start + + .global eor_reg_reg_shift +eor_reg_reg_shift: + eor00 pc,pc,pc,lsl pc + + pass diff --git a/sim/testsuite/sim/arm/hello.ms b/sim/testsuite/sim/arm/hello.ms new file mode 100644 index 0000000..b063c29 --- /dev/null +++ b/sim/testsuite/sim/arm/hello.ms @@ -0,0 +1,91 @@ +# output(): Hello, world.\n +# mach(): all + +# Emit hello world while switching back and forth between arm/thumb. +# ??? Unfinished + + .macro invalid +# This is "undefined" but it's not properly decoded yet. + .word 0x07ffffff +# This is stc which isn't recognized yet. + stc 0,cr0,[r0] + .endm + + .global _start +_start: +# Run some simple insns to confirm the engine is at least working. + nop + +# Skip over output text. + + bl skip_output + +hello_text: + .asciz "Hello, world.\n" + + .p2align 2 +skip_output: + +# Prime loop. + + mov r4, r14 + +output_next: + +# Switch arm->thumb to output next chacter. +# At this point r4 must point to the next character to output. + + adr r0, into_thumb + 1 + bx r0 + +into_thumb: + .thumb + +# Output a character. + + mov r0,#3 @ writec angel call + mov r1,r4 + swi 0xab @ ??? Confirm number. + +# Switch thumb->arm. + + adr r5, back_to_arm + bx r5 + + .p2align 2 +back_to_arm: + .arm + +# Load next character, see if done. + + add r4,r4,#1 + sub r3,r3,r3 + ldrb r5,[r4,r3] + teq r5,#0 + beq done + +# Output a character (in arm mode). + + mov r0,#3 + mov r1,r4 + swi #0x123456 + +# Load next character, see if done. + + add r4,r4,#1 + sub r3,r3,r3 + ldrb r5,[r4,r3] + teq r5,#0 + bne output_next + +done: + mov r0,#0x18 + ldr r1,exit_code + swi #0x123456 + +# If that fails, try to die with an invalid insn. + + invalid + +exit_code: + .word 0x20026 diff --git a/sim/testsuite/sim/arm/iwmmxt/iwmmxt.exp b/sim/testsuite/sim/arm/iwmmxt/iwmmxt.exp new file mode 100644 index 0000000..f3d0f0a --- /dev/null +++ b/sim/testsuite/sim/arm/iwmmxt/iwmmxt.exp @@ -0,0 +1,28 @@ +# Intel(r) Wireless MMX(tm) technology simulator testsuite. + +if { [istarget xscale*-*-*] } { + # load support procs (none yet) + # load_lib cgen.exp + + # all machines + set all_machs "xscale" + + if [is_remote host] { + remote_download host $srcdir/$subdir/testutils.inc + } + + # The .cgs suffix is for "cgen .s". + foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.cgs]] { + # If we're only testing specific files and this isn't one of them, + # skip it. + if ![runtest_file_p $runtests $src] { + continue + } + + run_sim_test $src $all_machs + } + + if [is_remote host] { + remote_file host delete testutils.inc + } +} diff --git a/sim/testsuite/sim/arm/iwmmxt/tbcst.cgs b/sim/testsuite/sim/arm/iwmmxt/tbcst.cgs new file mode 100644 index 0000000..b7138df --- /dev/null +++ b/sim/testsuite/sim/arm/iwmmxt/tbcst.cgs @@ -0,0 +1,65 @@ +# Intel(r) Wireless MMX(tm) technology testcase for TBCST +# mach: xscale +# as: -mcpu=xscale+iwmmxt + + .include "testutils.inc" + + start + + .global tbcst +tbcst: + # Enable access to CoProcessors 0 & 1 before + # we attempt these instructions. + + mvi_h_gr r1, 3 + mcr p15, 0, r1, cr15, cr1, 0 + + # Test Byte Wide Broadcast + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x111111ff + + tmcrr wr0, r0, r1 + + tbcstb wr0, r2 + + tmrrc r0, r1, wr0 + + test_h_gr r0, 0xffffffff + test_h_gr r1, 0xffffffff + test_h_gr r2, 0x111111ff + + # Test Half Word Wide Broadcast + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x111111ff + + tmcrr wr0, r0, r1 + + tbcsth wr0, r2 + + tmrrc r0, r1, wr0 + + test_h_gr r0, 0x11ff11ff + test_h_gr r1, 0x11ff11ff + test_h_gr r2, 0x111111ff + + # Test Word Wide Broadcast + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x111111ff + + tmcrr wr0, r0, r1 + + tbcstw wr0, r2 + + tmrrc r0, r1, wr0 + + test_h_gr r0, 0x111111ff + test_h_gr r1, 0x111111ff + test_h_gr r2, 0x111111ff + + pass diff --git a/sim/testsuite/sim/arm/iwmmxt/testutils.inc b/sim/testsuite/sim/arm/iwmmxt/testutils.inc new file mode 100644 index 0000000..ae49db8 --- /dev/null +++ b/sim/testsuite/sim/arm/iwmmxt/testutils.inc @@ -0,0 +1,118 @@ +# r0-r3 are used as tmps, consider them call clobbered by these macros. +# This uses the angel rom monitor calls. +# ??? How do we use the \@ facility of .macros ??? +# @ is the comment char! + + .macro mvi_h_gr reg, val + ldr \reg,[pc] + b . + 8 + .word \val + .endm + + .macro mvaddr_h_gr reg, addr + ldr \reg,[pc] + b . + 8 + .word \addr + .endm + + .macro start + .data +failmsg: + .asciz "fail\n" +passmsg: + .asciz "pass\n" + .text + +do_pass: + ldr r1, passmsg_addr + mov r0, #4 + swi #0x123456 + exit 0 +passmsg_addr: + .word passmsg + +do_fail: + ldr r1, failmsg_addr + mov r0, #4 + swi #0x123456 + exit 1 +failmsg_addr: + .word failmsg + + .global _start +_start: + .endm + +# *** Other macros know pass/fail are 4 bytes in size! Yuck. + + .macro pass + b do_pass + .endm + + .macro fail + b do_fail + .endm + + .macro exit rc + # ??? This works with the ARMulator but maybe not others. + #mov r0, #\rc + #swi #1 + # This seems to be portable (though it ignores rc). + mov r0,#0x18 + mvi_h_gr r1, 0x20026 + swi #0x123456 + # If that returns, punt with a sigill. + stc 0,cr0,[r0] + .endm + +# Other macros know this only clobbers r0. +# WARNING: It also clobbers the condition codes (FIXME). + .macro test_h_gr reg, val + mvaddr_h_gr r0, \val + cmp \reg, r0 + beq . + 8 + fail + .endm + + .macro mvi_h_cnvz c, n, v, z + mov r0, #0 + .if \c + orr r0, r0, #0x20000000 + .endif + .if \n + orr r0, r0, #0x80000000 + .endif + .if \v + orr r0, r0, #0x10000000 + .endif + .if \z + orr r0, r0, #0x40000000 + .endif + mrs r1, cpsr + bic r1, r1, #0xf0000000 + orr r1, r1, r0 + msr cpsr, r1 + # ??? nops needed + .endm + +# ??? Preserve condition codes? + .macro test_h_cnvz c, n, v, z + mov r0, #0 + .if \c + orr r0, r0, #0x20000000 + .endif + .if \n + orr r0, r0, #0x80000000 + .endif + .if \v + orr r0, r0, #0x10000000 + .endif + .if \z + orr r0, r0, #0x40000000 + .endif + mrs r1, cpsr + and r1, r1, #0xf0000000 + cmp r0, r1 + beq . + 8 + fail + .endm diff --git a/sim/testsuite/sim/arm/iwmmxt/textrm.cgs b/sim/testsuite/sim/arm/iwmmxt/textrm.cgs new file mode 100644 index 0000000..fb3dc94 --- /dev/null +++ b/sim/testsuite/sim/arm/iwmmxt/textrm.cgs @@ -0,0 +1,113 @@ +# Intel(r) Wireless MMX(tm) technology testcase for TEXTRM +# mach: xscale +# as: -mcpu=xscale+iwmmxt + + .include "testutils.inc" + + start + + .global textrm +textrm: + # Enable access to CoProcessors 0 & 1 before + # we attempt these instructions. + + mvi_h_gr r1, 3 + mcr p15, 0, r1, cr15, cr1, 0 + + # Test Unsigned Byte Wide Extraction + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x111111ff + + tmcrr wr0, r0, r1 + + textrmub r2, wr0, #3 + + tmrrc r0, r1, wr0 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x00000012 + + # Test Signed Byte Wide Extraction + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x111111ff + + tmcrr wr0, r0, r1 + + textrmsb r2, wr0, #4 + + tmrrc r0, r1, wr0 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0xfffffff0 + + # Test Unsigned Half Word Wide Extraction + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x111111ff + + tmcrr wr0, r0, r1 + + textrmuh r2, wr0, #3 + + tmrrc r0, r1, wr0 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x00009abc + + # Test Signed Half Word Wide Extraction + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x111111ff + + tmcrr wr0, r0, r1 + + textrmsh r2, wr0, #1 + + tmrrc r0, r1, wr0 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x00001234 + + # Test Unsigned Word Wide Extraction + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x111111ff + + tmcrr wr0, r0, r1 + + textrmuw r2, wr0, #0 + + tmrrc r0, r1, wr0 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x12345678 + + # Test Signed Word Wide Extraction + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x111111ff + + tmcrr wr0, r0, r1 + + textrmsw r2, wr0, #1 + + tmrrc r0, r1, wr0 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x9abcdef0 + + pass diff --git a/sim/testsuite/sim/arm/iwmmxt/tinsr.cgs b/sim/testsuite/sim/arm/iwmmxt/tinsr.cgs new file mode 100644 index 0000000..f457b19 --- /dev/null +++ b/sim/testsuite/sim/arm/iwmmxt/tinsr.cgs @@ -0,0 +1,65 @@ +# Intel(r) Wireless MMX(tm) technology testcase for TINSR +# mach: xscale +# as: -mcpu=xscale+iwmmxt + + .include "testutils.inc" + + start + + .global tinsr +tinsr: + # Enable access to CoProcessors 0 & 1 before + # we attempt these instructions. + + mvi_h_gr r1, 3 + mcr p15, 0, r1, cr15, cr1, 0 + + # Test Byte Wide Insertion + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x111111ff + + tmcrr wr0, r0, r1 + + tinsrb wr0, r2, #3 + + tmrrc r0, r1, wr0 + + test_h_gr r0, 0xff345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x111111ff + + # Test Half Word Wide Insertion + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x111111ff + + tmcrr wr0, r0, r1 + + tinsrh wr0, r2, #2 + + tmrrc r0, r1, wr0 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abc11ff + test_h_gr r2, 0x111111ff + + # Test Word Wide Insertion + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x111111ff + + tmcrr wr0, r0, r1 + + tinsrw wr0, r2, #1 + + tmrrc r0, r1, wr0 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x111111ff + test_h_gr r2, 0x111111ff + + pass diff --git a/sim/testsuite/sim/arm/iwmmxt/tmia.cgs b/sim/testsuite/sim/arm/iwmmxt/tmia.cgs new file mode 100644 index 0000000..0b0da66 --- /dev/null +++ b/sim/testsuite/sim/arm/iwmmxt/tmia.cgs @@ -0,0 +1,35 @@ +# Intel(r) Wireless MMX(tm) technology testcase for TMIA +# mach: xscale +# as: -mcpu=xscale+iwmmxt + + .include "testutils.inc" + + start + + .global tmia +tmia: + # Enable access to CoProcessors 0 & 1 before + # we attempt these instructions. + + mvi_h_gr r1, 3 + mcr p15, 0, r1, cr15, cr1, 0 + + # Test Multilply Accumulate + + mvi_h_gr r0, 0x11223344 + mvi_h_gr r1, 0x55667788 + mvi_h_gr r2, 0x12345678 + mvi_h_gr r3, 0x9abcdef0 + + tmcrr wr0, r0, r1 + + tmia wr0, r2, r3 + + tmrrc r0, r1, wr0 + + test_h_gr r0, 0x354f53c4 + test_h_gr r1, 0x4e330b5e + test_h_gr r2, 0x12345678 + test_h_gr r3, 0x9abcdef0 + + pass diff --git a/sim/testsuite/sim/arm/iwmmxt/tmiaph.cgs b/sim/testsuite/sim/arm/iwmmxt/tmiaph.cgs new file mode 100644 index 0000000..3778b0a --- /dev/null +++ b/sim/testsuite/sim/arm/iwmmxt/tmiaph.cgs @@ -0,0 +1,35 @@ +# Intel(r) Wireless MMX(tm) technology testcase for TMIAPH +# mach: xscale +# as: -mcpu=xscale+iwmmxt + + .include "testutils.inc" + + start + + .global tmiaph +tmiaph: + # Enable access to CoProcessors 0 & 1 before + # we attempt these instructions. + + mvi_h_gr r1, 3 + mcr p15, 0, r1, cr15, cr1, 0 + + # Test Multilply Accumulate + + mvi_h_gr r0, 0x11223344 + mvi_h_gr r1, 0x55667788 + mvi_h_gr r2, 0x12345678 + mvi_h_gr r3, 0x9abcdef0 + + tmcrr wr0, r0, r1 + + tmiaph wr0, r2, r3 + + tmrrc r0, r1, wr0 + + test_h_gr r0, 0xfec3f9f4 + test_h_gr r1, 0x55667787 + test_h_gr r2, 0x12345678 + test_h_gr r3, 0x9abcdef0 + + pass diff --git a/sim/testsuite/sim/arm/iwmmxt/tmiaxy.cgs b/sim/testsuite/sim/arm/iwmmxt/tmiaxy.cgs new file mode 100644 index 0000000..e7a7b73 --- /dev/null +++ b/sim/testsuite/sim/arm/iwmmxt/tmiaxy.cgs @@ -0,0 +1,89 @@ +# Intel(r) Wireless MMX(tm) technology testcase for TMIAxy +# mach: xscale +# as: -mcpu=xscale+iwmmxt + + .include "testutils.inc" + + start + + .global tmiaXY +tmiaXY: + # Enable access to CoProcessors 0 & 1 before + # we attempt these instructions. + + mvi_h_gr r1, 3 + mcr p15, 0, r1, cr15, cr1, 0 + + # Test Bottom Bottom Multilply Accumulate + + mvi_h_gr r0, 0x11223344 + mvi_h_gr r1, 0x55667788 + mvi_h_gr r2, 0x12345678 + mvi_h_gr r3, 0x9abcdef0 + + tmcrr wr0, r0, r1 + + tmiaBB wr0, r2, r3 + + tmrrc r0, r1, wr0 + + test_h_gr r0, 0x05f753c4 + test_h_gr r1, 0x55667788 + test_h_gr r2, 0x12345678 + test_h_gr r3, 0x9abcdef0 + + # Test Bottom Top Multilply Accumulate + + mvi_h_gr r0, 0x11223344 + mvi_h_gr r1, 0x55667788 + mvi_h_gr r2, 0x12345678 + mvi_h_gr r3, 0x9abcdef0 + + tmcrr wr0, r0, r1 + + tmiaBT wr0, r2, r3 + + tmrrc r0, r1, wr0 + + test_h_gr r0, 0xeeede364 + test_h_gr r1, 0x55667787 + test_h_gr r2, 0x12345678 + test_h_gr r3, 0x9abcdef0 + + # Test Top Bottom Multilply Accumulate + + mvi_h_gr r0, 0x11223344 + mvi_h_gr r1, 0x55667788 + mvi_h_gr r2, 0x12345678 + mvi_h_gr r3, 0x9abcdef0 + + tmcrr wr0, r0, r1 + + tmiaTB wr0, r2, r3 + + tmrrc r0, r1, wr0 + + test_h_gr r0, 0x0ec85c04 + test_h_gr r1, 0x55667788 + test_h_gr r2, 0x12345678 + test_h_gr r3, 0x9abcdef0 + + # Test Top Top Multilply Accumulate + + mvi_h_gr r0, 0x11223344 + mvi_h_gr r1, 0x55667788 + mvi_h_gr r2, 0x12345678 + mvi_h_gr r3, 0x9abcdef0 + + tmcrr wr0, r0, r1 + + tmiaTT wr0, r2, r3 + + tmrrc r0, r1, wr0 + + test_h_gr r0, 0x09eed974 + test_h_gr r1, 0x55667788 + test_h_gr r2, 0x12345678 + test_h_gr r3, 0x9abcdef0 + + pass diff --git a/sim/testsuite/sim/arm/iwmmxt/tmovmsk.cgs b/sim/testsuite/sim/arm/iwmmxt/tmovmsk.cgs new file mode 100644 index 0000000..cfea5b7 --- /dev/null +++ b/sim/testsuite/sim/arm/iwmmxt/tmovmsk.cgs @@ -0,0 +1,65 @@ +# Intel(r) Wireless MMX(tm) technology testcase for TMOVMSK +# mach: xscale +# as: -mcpu=xscale+iwmmxt + + .include "testutils.inc" + + start + + .global tmovmsk +tmovmsk: + # Enable access to CoProcessors 0 & 1 before + # we attempt these instructions. + + mvi_h_gr r1, 3 + mcr p15, 0, r1, cr15, cr1, 0 + + # Test Byte Wide Mask Transfer + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0 + + tmcrr wr0, r0, r1 + + tmovmskb r2, wr0 + + tmrrc r0, r1, wr0 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x000000f0 + + # Test Half Word Wide Mask Transfer + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0 + + tmcrr wr0, r0, r1 + + tmovmskh r2, wr0 + + tmrrc r0, r1, wr0 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x0000000c + + # Test Word Wide Mask Transfer + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0 + + tmcrr wr0, r0, r1 + + tmovmskw r2, wr0 + + tmrrc r0, r1, wr0 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x00000002 + + pass diff --git a/sim/testsuite/sim/arm/iwmmxt/wacc.cgs b/sim/testsuite/sim/arm/iwmmxt/wacc.cgs new file mode 100644 index 0000000..b3ffea1 --- /dev/null +++ b/sim/testsuite/sim/arm/iwmmxt/wacc.cgs @@ -0,0 +1,77 @@ +# Intel(r) Wireless MMX(tm) technology testcase for WACC +# mach: xscale +# as: -mcpu=xscale+iwmmxt + + .include "testutils.inc" + + start + + .global wacc +wacc: + # Enable access to CoProcessors 0 & 1 before + # we attempt these instructions. + + mvi_h_gr r1, 3 + mcr p15, 0, r1, cr15, cr1, 0 + + # Test Unsigned Byte Wide Accumulation + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0 + mvi_h_gr r3, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + + waccb wr1, wr0 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x00000438 + test_h_gr r3, 0x00000000 + + # Test Unsigned Half Word Wide Accumulation + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0 + mvi_h_gr r3, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + + wacch wr1, wr0 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x0001e258 + test_h_gr r3, 0x00000000 + + # Test Unsigned Word Wide Accumulation + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0 + mvi_h_gr r3, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + + waccw wr1, wr0 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0xacf13568 + test_h_gr r3, 0x00000000 + + pass diff --git a/sim/testsuite/sim/arm/iwmmxt/wadd.cgs b/sim/testsuite/sim/arm/iwmmxt/wadd.cgs new file mode 100644 index 0000000..bb4d0ab --- /dev/null +++ b/sim/testsuite/sim/arm/iwmmxt/wadd.cgs @@ -0,0 +1,251 @@ +# Intel(r) Wireless MMX(tm) technology testcase for WADD +# mach: xscale +# as: -mcpu=xscale+iwmmxt + + .include "testutils.inc" + + start + + .global wadd +wadd: + # Enable access to CoProcessors 0 & 1 before + # we attempt these instructions. + + mvi_h_gr r1, 3 + mcr p15, 0, r1, cr15, cr1, 0 + + # Test UnSaturated Byte Addition + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcde00 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x11111111 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + waddb wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcde00 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x11111111 + test_h_gr r4, 0x23456789 + test_h_gr r5, 0xabcdef11 + + # Test Unsigned Saturated Byte Addition + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcde00 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x11111111 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + waddbus wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcde00 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x11111111 + test_h_gr r4, 0x23456789 + test_h_gr r5, 0xabcdef11 + + # Test Signed Saturated Byte Addition + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcde00 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x11111111 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + waddbss wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcde00 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x11111111 + test_h_gr r4, 0x2345677f + test_h_gr r5, 0xabcdef11 + + # Test UnSaturated Halfword Addition + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcde00 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x11111111 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + waddh wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcde00 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x11111111 + test_h_gr r4, 0x23456789 + test_h_gr r5, 0xabcdef11 + + # Test Unsigned Saturated Halfword Addition + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcde00 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x11111111 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + waddhus wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcde00 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x11111111 + test_h_gr r4, 0x23456789 + test_h_gr r5, 0xabcdef11 + + # Test Signed Saturated Halfword Addition + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcde00 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x11111111 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + waddhss wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcde00 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x11111111 + test_h_gr r4, 0x23456789 + test_h_gr r5, 0xabcdef11 + + # Test UnSaturated Word Addition + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcde00 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x11111111 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + waddw wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcde00 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x11111111 + test_h_gr r4, 0x23456789 + test_h_gr r5, 0xabcdef11 + + # Test Unsigned Saturated Word Addition + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcde00 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x11111111 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + waddwus wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcde00 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x11111111 + test_h_gr r4, 0x23456789 + test_h_gr r5, 0xabcdef11 + + # Test Signed Saturated Word Addition + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcde00 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x11111111 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + waddwss wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcde00 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x11111111 + test_h_gr r4, 0x23456789 + test_h_gr r5, 0xabcdef11 + + pass diff --git a/sim/testsuite/sim/arm/iwmmxt/waligni.cgs b/sim/testsuite/sim/arm/iwmmxt/waligni.cgs new file mode 100644 index 0000000..dc99dae --- /dev/null +++ b/sim/testsuite/sim/arm/iwmmxt/waligni.cgs @@ -0,0 +1,43 @@ +# Intel(r) Wireless MMX(tm) technology testcase for WALIGNI +# mach: xscale +# as: -mcpu=xscale+iwmmxt + + .include "testutils.inc" + + start + + .global waligni +waligni: + # Enable access to CoProcessors 0 & 1 before + # we attempt these instructions. + + mvi_h_gr r1, 3 + mcr p15, 0, r1, cr15, cr1, 0 + + # Test 2 byte align + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x00000000 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + waligni wr2, wr0, wr1, #2 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x00000000 + test_h_gr r4, 0xdef01234 + test_h_gr r5, 0x11119abc + + pass diff --git a/sim/testsuite/sim/arm/iwmmxt/walignr.cgs b/sim/testsuite/sim/arm/iwmmxt/walignr.cgs new file mode 100644 index 0000000..85df51e --- /dev/null +++ b/sim/testsuite/sim/arm/iwmmxt/walignr.cgs @@ -0,0 +1,137 @@ +# Intel(r) Wireless MMX(tm) technology testcase for WALIGNR +# mach: xscale +# as: -mcpu=xscale+iwmmxt + + .include "testutils.inc" + + start + + .global walignr +walignr: + # Enable access to CoProcessors 0 & 1 before + # we attempt these instructions. + + mvi_h_gr r1, 3 + mcr p15, 0, r1, cr15, cr1, 0 + + # Test 0 byte align + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x00000000 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + mvi_h_gr r6, 3 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + tmcr wcgr0, r6 + + walignr0 wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + tmrc r6, wcgr0 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x00000000 + test_h_gr r4, 0xbcdef012 + test_h_gr r5, 0x1111119a + test_h_gr r6, 3 + + # Test 1 byte align + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x00000000 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + mvi_h_gr r6, 4 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + tmcr wcgr1, r6 + + walignr1 wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + tmrc r6, wcgr1 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x00000000 + test_h_gr r4, 0x9abcdef0 + test_h_gr r5, 0x11111111 + test_h_gr r6, 4 + + # Test 2 byte align + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x00000000 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + mvi_h_gr r6, 2 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + tmcr wcgr2, r6 + + walignr2 wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + tmrc r6, wcgr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x00000000 + test_h_gr r4, 0xdef01234 + test_h_gr r5, 0x11119abc + test_h_gr r6, 2 + + # Test 3 byte align + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x00000000 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + mvi_h_gr r6, 5 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + tmcr wcgr3, r6 + + walignr3 wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + tmrc r6, wcgr3 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x00000000 + test_h_gr r4, 0x119abcde + test_h_gr r5, 0x00111111 + test_h_gr r6, 5 + + pass diff --git a/sim/testsuite/sim/arm/iwmmxt/wand.cgs b/sim/testsuite/sim/arm/iwmmxt/wand.cgs new file mode 100644 index 0000000..018383f --- /dev/null +++ b/sim/testsuite/sim/arm/iwmmxt/wand.cgs @@ -0,0 +1,41 @@ +# Intel(r) Wireless MMX(tm) technology testcase for WAND +# mach: xscale +# as: -mcpu=xscale+iwmmxt + + .include "testutils.inc" + + start + + .global wand +wand: + # Enable access to CoProcessors 0 & 1 before + # we attempt these instructions. + + mvi_h_gr r1, 3 + mcr p15, 0, r1, cr15, cr1, 0 + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x00000000 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wand wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x00000000 + test_h_gr r4, 0x10101010 + test_h_gr r5, 0x00000000 + + pass diff --git a/sim/testsuite/sim/arm/iwmmxt/wandn.cgs b/sim/testsuite/sim/arm/iwmmxt/wandn.cgs new file mode 100644 index 0000000..f2c2305 --- /dev/null +++ b/sim/testsuite/sim/arm/iwmmxt/wandn.cgs @@ -0,0 +1,41 @@ +# Intel(r) Wireless MMX(tm) technology testcase for WANDN +# mach: xscale +# as: -mcpu=xscale+iwmmxt + + .include "testutils.inc" + + start + + .global wandn +wandn: + # Enable access to CoProcessors 0 & 1 before + # we attempt these instructions. + + mvi_h_gr r1, 3 + mcr p15, 0, r1, cr15, cr1, 0 + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x00000000 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wandn wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x00000000 + test_h_gr r4, 0x02244668 + test_h_gr r5, 0x9abcdef0 + + pass diff --git a/sim/testsuite/sim/arm/iwmmxt/wavg2.cgs b/sim/testsuite/sim/arm/iwmmxt/wavg2.cgs new file mode 100644 index 0000000..cac2c1a --- /dev/null +++ b/sim/testsuite/sim/arm/iwmmxt/wavg2.cgs @@ -0,0 +1,121 @@ +# Intel(r) Wireless MMX(tm) technology testcase for WAVG2 +# mach: xscale +# as: -mcpu=xscale+iwmmxt + + .include "testutils.inc" + + start + + .global wavg2 +wavg2: + # Enable access to CoProcessors 0 & 1 before + # we attempt these instructions. + + mvi_h_gr r1, 3 + mcr p15, 0, r1, cr15, cr1, 0 + + # Test Byte Wide Averaging + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x22222222 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wavg2b wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x22222222 + test_h_gr r4, 0x11223344 + test_h_gr r5, 0x5e6f8089 + + # Test Byte Wide Averaging with Rounding + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x22222222 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wavg2br wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x22222222 + test_h_gr r4, 0x12233445 + test_h_gr r5, 0x5e6f8089 + + # Test Half Word Wide Averaging + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x22222222 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wavg2h wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x22222222 + test_h_gr r4, 0x11a233c4 + test_h_gr r5, 0x5e6f8089 + + # Test Half Word Wide Averaging with Rounding + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x22222222 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wavg2hr wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x22222222 + test_h_gr r4, 0x11a333c5 + test_h_gr r5, 0x5e6f8089 + + pass diff --git a/sim/testsuite/sim/arm/iwmmxt/wcmpeq.cgs b/sim/testsuite/sim/arm/iwmmxt/wcmpeq.cgs new file mode 100644 index 0000000..13ef3dc --- /dev/null +++ b/sim/testsuite/sim/arm/iwmmxt/wcmpeq.cgs @@ -0,0 +1,95 @@ +# Intel(r) Wireless MMX(tm) technology testcase for WCMPEQ +# mach: xscale +# as: -mcpu=xscale+iwmmxt + + .include "testutils.inc" + + start + + .global wcmpeq +wcmpeq: + # Enable access to CoProcessors 0 & 1 before + # we attempt these instructions. + + mvi_h_gr r1, 3 + mcr p15, 0, r1, cr15, cr1, 0 + + # Test Byte Wide Compare Equal To + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcde00 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x9abcde00 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wcmpeqb wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcde00 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x9abcde00 + test_h_gr r4, 0x00000000 + test_h_gr r5, 0xffffffff + + # Test Half Word Wide Compare Equal To + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcde00 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x9abcde00 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wcmpeqh wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcde00 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x9abcde00 + test_h_gr r4, 0x00000000 + test_h_gr r5, 0xffffffff + + # Test Word Wide Compare Equal To + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcde00 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x9abcde00 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wcmpeqw wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcde00 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x9abcde00 + test_h_gr r4, 0x00000000 + test_h_gr r5, 0xffffffff + + pass diff --git a/sim/testsuite/sim/arm/iwmmxt/wcmpgt.cgs b/sim/testsuite/sim/arm/iwmmxt/wcmpgt.cgs new file mode 100644 index 0000000..33086c9 --- /dev/null +++ b/sim/testsuite/sim/arm/iwmmxt/wcmpgt.cgs @@ -0,0 +1,173 @@ +# Intel(r) Wireless MMX(tm) technology testcase for WCMPGT +# mach: xscale +# as: -mcpu=xscale+iwmmxt + + .include "testutils.inc" + + start + + .global wcmpgt +wcmpgt: + # Enable access to CoProcessors 0 & 1 before + # we attempt these instructions. + + mvi_h_gr r1, 3 + mcr p15, 0, r1, cr15, cr1, 0 + + # Test Unsigned Byte Wide Compare Greater Than + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcde00 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x22222222 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wcmpgtub wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcde00 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x22222222 + test_h_gr r4, 0xffffffff + test_h_gr r5, 0xffffff00 + + # Test Signed Byte Wide Compare Greater Than + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcde00 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x22222222 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wcmpgtsb wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcde00 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x22222222 + test_h_gr r4, 0xffffffff + test_h_gr r5, 0x00000000 + + # Test Unsigned Half Word Wide Compare Greater Than + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcde00 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x22222222 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wcmpgtuh wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcde00 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x22222222 + test_h_gr r4, 0xffffffff + test_h_gr r5, 0xffffffff + + # Test Signed Half Word Wide Compare Greater Than + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcde00 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x22222222 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wcmpgtsh wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcde00 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x22222222 + test_h_gr r4, 0xffffffff + test_h_gr r5, 0x00000000 + + # Test Unsigned Word Wide Compare Greater Than + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcde00 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x22222222 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wcmpgtuw wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcde00 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x22222222 + test_h_gr r4, 0xffffffff + test_h_gr r5, 0xffffffff + + # Test Signed Word Wide Compare Greater Than + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcde00 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x22222222 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wcmpgtsw wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcde00 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x22222222 + test_h_gr r4, 0xffffffff + test_h_gr r5, 0x00000000 + + pass diff --git a/sim/testsuite/sim/arm/iwmmxt/wmac.cgs b/sim/testsuite/sim/arm/iwmmxt/wmac.cgs new file mode 100644 index 0000000..0857ef9 --- /dev/null +++ b/sim/testsuite/sim/arm/iwmmxt/wmac.cgs @@ -0,0 +1,121 @@ +# Intel(r) Wireless MMX(tm) technology testcase for WMAC +# mach: xscale +# as: -mcpu=xscale+iwmmxt + + .include "testutils.inc" + + start + + .global wmac +wmac: + # Enable access to CoProcessors 0 & 1 before + # we attempt these instructions. + + mvi_h_gr r1, 3 + mcr p15, 0, r1, cr15, cr1, 0 + + # Test Unsigned, Multiply Accumulate, Non-zeroing + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x22222222 + mvi_h_gr r4, 0x33333333 + mvi_h_gr r5, 0x44444444 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wmacu wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x22222222 + test_h_gr r4, 0x6c889377 + test_h_gr r5, 0x44444444 + + # Test Unsigned, Multiply Accumulate, Zeroing + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x22222222 + mvi_h_gr r4, 0x33333333 + mvi_h_gr r5, 0x44444444 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wmacuz wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x22222222 + test_h_gr r4, 0x39556044 + test_h_gr r5, 0x00000000 + + # Test Signed, Multiply Accumulate, Non-zeroing + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x22222222 + mvi_h_gr r4, 0x33333333 + mvi_h_gr r5, 0x44444444 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wmacs wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x22222222 + test_h_gr r4, 0x28449377 + test_h_gr r5, 0x44444444 + + # Test Signed, Multiply Accumulate, Zeroing + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x22222222 + mvi_h_gr r4, 0x33333333 + mvi_h_gr r5, 0x44444444 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wmacsz wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x22222222 + test_h_gr r4, 0xf5116044 + test_h_gr r5, 0xffffffff + + pass diff --git a/sim/testsuite/sim/arm/iwmmxt/wmadd.cgs b/sim/testsuite/sim/arm/iwmmxt/wmadd.cgs new file mode 100644 index 0000000..564b3be --- /dev/null +++ b/sim/testsuite/sim/arm/iwmmxt/wmadd.cgs @@ -0,0 +1,69 @@ +# Intel(r) Wireless MMX(tm) technology testcase for WMADD +# mach: xscale +# as: -mcpu=xscale+iwmmxt + + .include "testutils.inc" + + start + + .global wmadd +wmadd: + # Enable access to CoProcessors 0 & 1 before + # we attempt these instructions. + + mvi_h_gr r1, 3 + mcr p15, 0, r1, cr15, cr1, 0 + + # Test Unsigned, Multiply Addition + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x22222222 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wmaddu wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x22222222 + test_h_gr r4, 0x06fa5f6c + test_h_gr r5, 0x325b00d8 + + # Test Signed, Multiply Addition + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x22222222 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wmadds wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x22222222 + test_h_gr r4, 0x06fa5f6c + test_h_gr r5, 0xee1700d8 + + pass diff --git a/sim/testsuite/sim/arm/iwmmxt/wmax.cgs b/sim/testsuite/sim/arm/iwmmxt/wmax.cgs new file mode 100644 index 0000000..3a684ce --- /dev/null +++ b/sim/testsuite/sim/arm/iwmmxt/wmax.cgs @@ -0,0 +1,173 @@ +# Intel(r) Wireless MMX(tm) technology testcase for WMAX +# mach: xscale +# as: -mcpu=xscale+iwmmxt + + .include "testutils.inc" + + start + + .global wmax +wmax: + # Enable access to CoProcessors 0 & 1 before + # we attempt these instructions. + + mvi_h_gr r1, 3 + mcr p15, 0, r1, cr15, cr1, 0 + + # Test Unsigned Byte Maximum + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcde00 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x11111111 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wmaxub wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcde00 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x11111111 + test_h_gr r4, 0x12345678 + test_h_gr r5, 0x9abcde11 + + # Test Signed Byte Maximum + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcde00 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x11111111 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wmaxsb wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcde00 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x11111111 + test_h_gr r4, 0x12345678 + test_h_gr r5, 0x11111111 + + # Test Unsigned Halfword Maximum + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcde00 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x11111111 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wmaxuh wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcde00 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x11111111 + test_h_gr r4, 0x12345678 + test_h_gr r5, 0x9abcde00 + + # Test Signed Halfword Maximum + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcde00 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x11111111 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wmaxsh wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcde00 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x11111111 + test_h_gr r4, 0x12345678 + test_h_gr r5, 0x11111111 + + # Test Unsigned Word Maximum + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcde00 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x11111111 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wmaxuw wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcde00 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x11111111 + test_h_gr r4, 0x12345678 + test_h_gr r5, 0x9abcde00 + + # Test Signed Word Maximum + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcde00 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x11111111 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wmaxsw wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcde00 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x11111111 + test_h_gr r4, 0x12345678 + test_h_gr r5, 0x11111111 + + pass diff --git a/sim/testsuite/sim/arm/iwmmxt/wmin.cgs b/sim/testsuite/sim/arm/iwmmxt/wmin.cgs new file mode 100644 index 0000000..3bc1c08 --- /dev/null +++ b/sim/testsuite/sim/arm/iwmmxt/wmin.cgs @@ -0,0 +1,173 @@ +# Intel(r) Wireless MMX(tm) technology testcase for WMIN +# mach: xscale +# as: -mcpu=xscale+iwmmxt + + .include "testutils.inc" + + start + + .global wmin +wmin: + # Enable access to CoProcessors 0 & 1 before + # we attempt these instructions. + + mvi_h_gr r1, 3 + mcr p15, 0, r1, cr15, cr1, 0 + + # Test Unsigned Byte Minimum + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcde00 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x11111111 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wminub wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcde00 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x11111111 + test_h_gr r4, 0x11111111 + test_h_gr r5, 0x11111100 + + # Test Signed Byte Minimum + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcde00 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x11111111 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wminsb wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcde00 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x11111111 + test_h_gr r4, 0x11111111 + test_h_gr r5, 0x9abcde00 + + # Test Unsigned Halfword Minimum + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcde00 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x11111111 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wminuh wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcde00 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x11111111 + test_h_gr r4, 0x11111111 + test_h_gr r5, 0x11111111 + + # Test Signed Halfword Minimum + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcde00 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x11111111 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wminsh wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcde00 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x11111111 + test_h_gr r4, 0x11111111 + test_h_gr r5, 0x9abcde00 + + # Test Unsigned Word Minimum + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcde00 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x11111111 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wminuw wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcde00 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x11111111 + test_h_gr r4, 0x11111111 + test_h_gr r5, 0x11111111 + + # Test Signed Word Minimum + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcde00 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x11111111 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wminsw wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcde00 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x11111111 + test_h_gr r4, 0x11111111 + test_h_gr r5, 0x9abcde00 + + pass diff --git a/sim/testsuite/sim/arm/iwmmxt/wmov.cgs b/sim/testsuite/sim/arm/iwmmxt/wmov.cgs new file mode 100644 index 0000000..e86fed6 --- /dev/null +++ b/sim/testsuite/sim/arm/iwmmxt/wmov.cgs @@ -0,0 +1,35 @@ +# Intel(r) Wireless MMX(tm) technology testcase for WMOV +# mach: xscale +# as: -mcpu=xscale+iwmmxt + + .include "testutils.inc" + + start + + .global wmov +wmov: + # Enable access to CoProcessors 0 & 1 before + # we attempt these instructions. + + mvi_h_gr r1, 3 + mcr p15, 0, r1, cr15, cr1, 0 + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0 + mvi_h_gr r3, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + + wmov wr1, wr0 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x12345678 + test_h_gr r3, 0x9abcdef0 + + pass diff --git a/sim/testsuite/sim/arm/iwmmxt/wmul.cgs b/sim/testsuite/sim/arm/iwmmxt/wmul.cgs new file mode 100644 index 0000000..0978b63 --- /dev/null +++ b/sim/testsuite/sim/arm/iwmmxt/wmul.cgs @@ -0,0 +1,121 @@ +# Intel(r) Wireless MMX(tm) technology testcase for WMUL +# mach: xscale +# as: -mcpu=xscale+iwmmxt + + .include "testutils.inc" + + start + + .global wmul +wmul: + # Enable access to CoProcessors 0 & 1 before + # we attempt these instructions. + + mvi_h_gr r1, 3 + mcr p15, 0, r1, cr15, cr1, 0 + + # Test Unsigned, Most Significant Multiply + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x22222222 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wmulum wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x22222222 + test_h_gr r4, 0x013605c3 + test_h_gr r5, 0x14a11db9 + + # Test Unsigned, Least Significant Multiply + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x22222222 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wmulul wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x22222222 + test_h_gr r4, 0xa974b5f8 + test_h_gr r5, 0x84f87be0 + + # Test Signed, Most Significant Multiply + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x22222222 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wmulsm wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x22222222 + test_h_gr r4, 0x013605c3 + test_h_gr r5, 0xf27ffb97 + + # Test Signed, Least Significant Multiply + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x22222222 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wmulsl wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x22222222 + test_h_gr r4, 0xa974b5f8 + test_h_gr r5, 0x84f87be0 + + pass diff --git a/sim/testsuite/sim/arm/iwmmxt/wor.cgs b/sim/testsuite/sim/arm/iwmmxt/wor.cgs new file mode 100644 index 0000000..48d5f53 --- /dev/null +++ b/sim/testsuite/sim/arm/iwmmxt/wor.cgs @@ -0,0 +1,41 @@ +# Intel(r) Wireless MMX(tm) technology testcase for WOR +# mach: xscale +# as: -mcpu=xscale+iwmmxt + + .include "testutils.inc" + + start + + .global wor +wor: + # Enable access to CoProcessors 0 & 1 before + # we attempt these instructions. + + mvi_h_gr r1, 3 + mcr p15, 0, r1, cr15, cr1, 0 + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x00000000 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wor wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x00000000 + test_h_gr r4, 0x13355779 + test_h_gr r5, 0x9abcdef0 + + pass diff --git a/sim/testsuite/sim/arm/iwmmxt/wpack.cgs b/sim/testsuite/sim/arm/iwmmxt/wpack.cgs new file mode 100644 index 0000000..0546bd4 --- /dev/null +++ b/sim/testsuite/sim/arm/iwmmxt/wpack.cgs @@ -0,0 +1,173 @@ +# Intel(r) Wireless MMX(tm) technology testcase for WPACK +# mach: xscale +# as: -mcpu=xscale+iwmmxt + + .include "testutils.inc" + + start + + .global wpack +wpack: + # Enable access to CoProcessors 0 & 1 before + # we attempt these instructions. + + mvi_h_gr r1, 3 + mcr p15, 0, r1, cr15, cr1, 0 + + # Test Halfword, Unsigned Saturation, Packing + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x00000000 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wpackhus wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x00000000 + test_h_gr r4, 0x0000ffff + test_h_gr r5, 0x0000ffff + + # Test Halfword, Signed Saturation, Packing + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x00000000 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wpackhss wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x00000000 + test_h_gr r4, 0x80807f7f + test_h_gr r5, 0x00007f7f + + # Test Word, Unsigned Saturation, Packing + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x00000000 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wpackwus wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x00000000 + test_h_gr r4, 0x0000ffff + test_h_gr r5, 0x0000ffff + + # Test Word, Signed Saturation, Packing + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x00000000 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wpackwss wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x00000000 + test_h_gr r4, 0x80007fff + test_h_gr r5, 0x00007fff + + # Test Double Word, Unsigned Saturation, Packing + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x00000000 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wpackdus wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x00000000 + test_h_gr r4, 0x00000000 + test_h_gr r5, 0x11111111 + + # Test Double Word, Signed Saturation, Packing + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x00000000 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wpackdss wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x00000000 + test_h_gr r4, 0x80000000 + test_h_gr r5, 0x11111111 + + pass diff --git a/sim/testsuite/sim/arm/iwmmxt/wror.cgs b/sim/testsuite/sim/arm/iwmmxt/wror.cgs new file mode 100644 index 0000000..e329916 --- /dev/null +++ b/sim/testsuite/sim/arm/iwmmxt/wror.cgs @@ -0,0 +1,167 @@ +# Intel(r) Wireless MMX(tm) technology testcase for WROR +# mach: xscale +# as: -mcpu=xscale+iwmmxt + + .include "testutils.inc" + + start + + .global wror +wror: + # Enable access to CoProcessors 0 & 1 before + # we attempt these instructions. + + mvi_h_gr r1, 3 + mcr p15, 0, r1, cr15, cr1, 0 + + # Test Halfword wide rotate right by register + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x00000000 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wrorh wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x00000000 + test_h_gr r4, 0x091a2b3c + test_h_gr r5, 0x4d5e6f78 + + # Test Halfword wide rotate right by CG register + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0 + mvi_h_gr r4, 0 + + tmcrr wr0, r0, r1 + tmcr wcgr0, r2 + tmcrr wr1, r2, r3 + + wrorhg wr1, wr0, wcgr0 + + tmrrc r0, r1, wr0 + tmrc r2, wcgr0 + tmrrc r3, r4, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x091a2b3c + test_h_gr r4, 0x4d5e6f78 + + # Test Word wide rotate right by register + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x00000000 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wrorw wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x00000000 + test_h_gr r4, 0x2b3c091a + test_h_gr r5, 0x6f784d5e + + # Test Word wide rotate right by CG register + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0 + mvi_h_gr r4, 0 + + tmcrr wr0, r0, r1 + tmcr wcgr0, r2 + tmcrr wr1, r2, r3 + + wrorwg wr1, wr0, wcgr0 + + tmrrc r0, r1, wr0 + tmrc r2, wcgr0 + tmrrc r3, r4, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x2b3c091a + test_h_gr r4, 0x6f784d5e + + # Test Double Word wide rotate right by register + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x00000000 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wrord wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x00000000 + test_h_gr r4, 0x6f78091a + test_h_gr r5, 0x2b3c4d5e + + # Test Double Word wide rotate right by CG register + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0 + mvi_h_gr r4, 0 + + tmcrr wr0, r0, r1 + tmcr wcgr0, r2 + tmcrr wr1, r2, r3 + + wrordg wr1, wr0, wcgr0 + + tmrrc r0, r1, wr0 + tmrc r2, wcgr0 + tmrrc r3, r4, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x6f78091a + test_h_gr r4, 0x2b3c4d5e + + pass diff --git a/sim/testsuite/sim/arm/iwmmxt/wsad.cgs b/sim/testsuite/sim/arm/iwmmxt/wsad.cgs new file mode 100644 index 0000000..34a20cc --- /dev/null +++ b/sim/testsuite/sim/arm/iwmmxt/wsad.cgs @@ -0,0 +1,121 @@ +# Intel(r) Wireless MMX(tm) technology testcase for WSAD +# mach: xscale +# as: -mcpu=xscale+iwmmxt + + .include "testutils.inc" + + start + + .global wsad +wsad: + # Enable access to CoProcessors 0 & 1 before + # we attempt these instructions. + + mvi_h_gr r1, 3 + mcr p15, 0, r1, cr15, cr1, 0 + + # Test Byte wide absolute accumulation + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x22222222 + mvi_h_gr r4, 0x22222222 + mvi_h_gr r5, 0x22222222 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wsadb wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x22222222 + test_h_gr r4, 0x2222258e + test_h_gr r5, 0x00000000 + + # Test Byte wide absolute accumulation with zeroing + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x22222222 + mvi_h_gr r4, 0x22222222 + mvi_h_gr r5, 0x22222222 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wsadbz wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x22222222 + test_h_gr r4, 0x0000036c + test_h_gr r5, 0x00000000 + + # Test Halfword wide absolute accumulation + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x22222222 + mvi_h_gr r4, 0x22222222 + mvi_h_gr r5, 0x22222222 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wsadh wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x22222222 + test_h_gr r4, 0x22239e14 + test_h_gr r5, 0x00000000 + + # Test Halfword wide absolute accumulation with zeroing + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x22222222 + mvi_h_gr r4, 0x22222222 + mvi_h_gr r5, 0x22222222 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wsadhz wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x22222222 + test_h_gr r4, 0x00017bf2 + test_h_gr r5, 0x00000000 + + pass diff --git a/sim/testsuite/sim/arm/iwmmxt/wshufh.cgs b/sim/testsuite/sim/arm/iwmmxt/wshufh.cgs new file mode 100644 index 0000000..d5cff1e --- /dev/null +++ b/sim/testsuite/sim/arm/iwmmxt/wshufh.cgs @@ -0,0 +1,35 @@ +# Intel(r) Wireless MMX(tm) technology testcase for WSHUFH +# mach: xscale +# as: -mcpu=xscale+iwmmxt + + .include "testutils.inc" + + start + + .global wshufh +wshufh: + # Enable access to CoProcessors 0 & 1 before + # we attempt these instructions. + + mvi_h_gr r1, 3 + mcr p15, 0, r1, cr15, cr1, 0 + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0 + mvi_h_gr r3, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + + wshufh wr1, wr0, #0x1b + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0xdef09abc + test_h_gr r3, 0x56781234 + + pass diff --git a/sim/testsuite/sim/arm/iwmmxt/wsll.cgs b/sim/testsuite/sim/arm/iwmmxt/wsll.cgs new file mode 100644 index 0000000..17d7893 --- /dev/null +++ b/sim/testsuite/sim/arm/iwmmxt/wsll.cgs @@ -0,0 +1,167 @@ +# Intel(r) Wireless MMX(tm) technology testcase for WSLL +# mach: xscale +# as: -mcpu=xscale+iwmmxt + + .include "testutils.inc" + + start + + .global wsll +wsll: + # Enable access to CoProcessors 0 & 1 before + # we attempt these instructions. + + mvi_h_gr r1, 3 + mcr p15, 0, r1, cr15, cr1, 0 + + # Test Halfword Logical Shift Left + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111104 + mvi_h_gr r3, 0x11111111 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wsllh wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111104 + test_h_gr r3, 0x11111111 + test_h_gr r4, 0x23406780 + test_h_gr r5, 0xabc0ef00 + + # Test Halfword Aritc Shift Left by CG register + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111104 + mvi_h_gr r3, 0 + mvi_h_gr r4, 0 + + tmcrr wr0, r0, r1 + tmcr wcgr1, r2 + tmcrr wr1, r3, r4 + + wsllhg wr1, wr0, wcgr1 + + tmrrc r0, r1, wr0 + tmrc r2, wcgr1 + tmrrc r3, r4, wr1 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111104 + test_h_gr r3, 0x23406780 + test_h_gr r4, 0xabc0ef00 + + # Test Word Logical Shift Left + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111104 + mvi_h_gr r3, 0x11111111 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wsllw wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111104 + test_h_gr r3, 0x11111111 + test_h_gr r4, 0x23456780 + test_h_gr r5, 0xabcdef00 + + # Test Word Logical Shift Left by CG register + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111104 + mvi_h_gr r3, 0 + mvi_h_gr r4, 0 + + tmcrr wr0, r0, r1 + tmcr wcgr2, r2 + tmcrr wr1, r3, r4 + + wsllwg wr1, wr0, wcgr2 + + tmrrc r0, r1, wr0 + tmrc r2, wcgr2 + tmrrc r3, r4, wr1 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111104 + test_h_gr r3, 0x23456780 + test_h_gr r4, 0xabcdef00 + + # Test Double Word Logical Shift Left + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdefc + mvi_h_gr r2, 0x11111104 + mvi_h_gr r3, 0x11111111 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wslld wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdefc + test_h_gr r2, 0x11111104 + test_h_gr r3, 0x11111111 + test_h_gr r4, 0x23456780 + test_h_gr r5, 0xabcdefc1 + + # Test Double Word Logical Shift Left by CG register + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdefc + mvi_h_gr r2, 0x11111104 + mvi_h_gr r3, 0 + mvi_h_gr r4, 0 + + tmcrr wr0, r0, r1 + tmcr wcgr3, r2 + tmcrr wr1, r3, r4 + + wslldg wr1, wr0, wcgr3 + + tmrrc r0, r1, wr0 + tmrc r2, wcgr3 + tmrrc r3, r4, wr1 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdefc + test_h_gr r2, 0x11111104 + test_h_gr r3, 0x23456780 + test_h_gr r4, 0xabcdefc1 + + pass diff --git a/sim/testsuite/sim/arm/iwmmxt/wsra.cgs b/sim/testsuite/sim/arm/iwmmxt/wsra.cgs new file mode 100644 index 0000000..db998bb --- /dev/null +++ b/sim/testsuite/sim/arm/iwmmxt/wsra.cgs @@ -0,0 +1,167 @@ +# Intel(r) Wireless MMX(tm) technology testcase for WSRA +# mach: xscale +# as: -mcpu=xscale+iwmmxt + + .include "testutils.inc" + + start + + .global wsra +wsra: + # Enable access to CoProcessors 0 & 1 before + # we attempt these instructions. + + mvi_h_gr r1, 3 + mcr p15, 0, r1, cr15, cr1, 0 + + # Test Halfword Arithmetic Shift Right + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111104 + mvi_h_gr r3, 0x11111111 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wsrah wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111104 + test_h_gr r3, 0x11111111 + test_h_gr r4, 0x01230567 + test_h_gr r5, 0xf9abfdef + + # Test Halfword Arithmetic Shift Right by CG register + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111104 + mvi_h_gr r3, 0 + mvi_h_gr r4, 0 + + tmcrr wr0, r0, r1 + tmcr wcgr1, r2 + tmcrr wr1, r3, r4 + + wsrahg wr1, wr0, wcgr1 + + tmrrc r0, r1, wr0 + tmrc r2, wcgr1 + tmrrc r3, r4, wr1 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111104 + test_h_gr r3, 0x01230567 + test_h_gr r4, 0xf9abfdef + + # Test Word Arithmetic Shift Right + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111104 + mvi_h_gr r3, 0x11111111 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wsraw wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111104 + test_h_gr r3, 0x11111111 + test_h_gr r4, 0x01234567 + test_h_gr r5, 0xf9abcdef + + # Test Word Arithmetic Shift Right by CG register + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111104 + mvi_h_gr r3, 0 + mvi_h_gr r4, 0 + + tmcrr wr0, r0, r1 + tmcr wcgr2, r2 + tmcrr wr1, r3, r4 + + wsrawg wr1, wr0, wcgr2 + + tmrrc r0, r1, wr0 + tmrc r2, wcgr2 + tmrrc r3, r4, wr1 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111104 + test_h_gr r3, 0x01234567 + test_h_gr r4, 0xf9abcdef + + # Test Double Word Arithmetic Shift Right + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdefc + mvi_h_gr r2, 0x11111104 + mvi_h_gr r3, 0x11111111 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wsrad wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdefc + test_h_gr r2, 0x11111104 + test_h_gr r3, 0x11111111 + test_h_gr r4, 0xc1234567 + test_h_gr r5, 0xf9abcdef + + # Test Double Word Arithmetic Shift Right by CG register + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdefc + mvi_h_gr r2, 0x11111104 + mvi_h_gr r3, 0 + mvi_h_gr r4, 0 + + tmcrr wr0, r0, r1 + tmcr wcgr3, r2 + tmcrr wr1, r3, r4 + + wsradg wr1, wr0, wcgr3 + + tmrrc r0, r1, wr0 + tmrc r2, wcgr3 + tmrrc r3, r4, wr1 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdefc + test_h_gr r2, 0x11111104 + test_h_gr r3, 0xc1234567 + test_h_gr r4, 0xf9abcdef + + pass diff --git a/sim/testsuite/sim/arm/iwmmxt/wsrl.cgs b/sim/testsuite/sim/arm/iwmmxt/wsrl.cgs new file mode 100644 index 0000000..416a464 --- /dev/null +++ b/sim/testsuite/sim/arm/iwmmxt/wsrl.cgs @@ -0,0 +1,167 @@ +# Intel(r) Wireless MMX(tm) technology testcase for WSRL +# mach: xscale +# as: -mcpu=xscale+iwmmxt + + .include "testutils.inc" + + start + + .global wsrl +wsrl: + # Enable access to CoProcessors 0 & 1 before + # we attempt these instructions. + + mvi_h_gr r1, 3 + mcr p15, 0, r1, cr15, cr1, 0 + + # Test Halfword Logical Shift Right + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111104 + mvi_h_gr r3, 0x11111111 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wsrlh wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111104 + test_h_gr r3, 0x11111111 + test_h_gr r4, 0x01230567 + test_h_gr r5, 0x09ab0def + + # Test Halfword Logical Shift Right by CG register + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111104 + mvi_h_gr r3, 0 + mvi_h_gr r4, 0 + + tmcrr wr0, r0, r1 + tmcr wcgr1, r2 + tmcrr wr1, r3, r4 + + wsrlhg wr1, wr0, wcgr1 + + tmrrc r0, r1, wr0 + tmrc r2, wcgr1 + tmrrc r3, r4, wr1 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111104 + test_h_gr r3, 0x01230567 + test_h_gr r4, 0x09ab0def + + # Test Word Logical Shift Right + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111104 + mvi_h_gr r3, 0x11111111 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wsrlw wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111104 + test_h_gr r3, 0x11111111 + test_h_gr r4, 0x01234567 + test_h_gr r5, 0x09abcdef + + # Test Word Logical Shift Right by CG register + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111104 + mvi_h_gr r3, 0 + mvi_h_gr r4, 0 + + tmcrr wr0, r0, r1 + tmcr wcgr2, r2 + tmcrr wr1, r3, r4 + + wsrlwg wr1, wr0, wcgr2 + + tmrrc r0, r1, wr0 + tmrc r2, wcgr2 + tmrrc r3, r4, wr1 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111104 + test_h_gr r3, 0x01234567 + test_h_gr r4, 0x09abcdef + + # Test Double Word Logical Shift Right + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdefc + mvi_h_gr r2, 0x11111104 + mvi_h_gr r3, 0x11111111 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wsrld wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdefc + test_h_gr r2, 0x11111104 + test_h_gr r3, 0x11111111 + test_h_gr r4, 0xc1234567 + test_h_gr r5, 0x09abcdef + + # Test Double Word Logical Shift Right by CG register + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdefc + mvi_h_gr r2, 0x11111104 + mvi_h_gr r3, 0 + mvi_h_gr r4, 0 + + tmcrr wr0, r0, r1 + tmcr wcgr3, r2 + tmcrr wr1, r3, r4 + + wsrldg wr1, wr0, wcgr3 + + tmrrc r0, r1, wr0 + tmrc r2, wcgr3 + tmrrc r3, r4, wr1 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdefc + test_h_gr r2, 0x11111104 + test_h_gr r3, 0xc1234567 + test_h_gr r4, 0x09abcdef + + pass diff --git a/sim/testsuite/sim/arm/iwmmxt/wsub.cgs b/sim/testsuite/sim/arm/iwmmxt/wsub.cgs new file mode 100644 index 0000000..b0e77be --- /dev/null +++ b/sim/testsuite/sim/arm/iwmmxt/wsub.cgs @@ -0,0 +1,251 @@ +# Intel(r) Wireless MMX(tm) technology testcase for WSUB +# mach: xscale +# as: -mcpu=xscale+iwmmxt + + .include "testutils.inc" + + start + + .global wsub +wsub: + # Enable access to CoProcessors 0 & 1 before + # we attempt these instructions. + + mvi_h_gr r1, 3 + mcr p15, 0, r1, cr15, cr1, 0 + + # Test Unsaturated Byte subtraction + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcde00 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x11111111 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wsubb wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcde00 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x11111111 + test_h_gr r4, 0x01234567 + test_h_gr r5, 0x89abcdef + + # Test Unsigned saturated Byte subtraction + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcde00 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x11111111 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wsubbus wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcde00 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x11111111 + test_h_gr r4, 0x01234567 + test_h_gr r5, 0x89abcd00 + + # Test Signed saturated Byte subtraction + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcde00 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x11111111 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wsubbss wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcde00 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x11111111 + test_h_gr r4, 0x01234567 + test_h_gr r5, 0x89abcdef + + # Test Unsaturated Halfword subtraction + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcde00 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x11111111 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wsubh wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcde00 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x11111111 + test_h_gr r4, 0x01234567 + test_h_gr r5, 0x89abccef + + # Test Unsigned saturated Halfword subtraction + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcde00 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x11111111 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wsubhus wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcde00 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x11111111 + test_h_gr r4, 0x01234567 + test_h_gr r5, 0x89abccef + + # Test Signed saturated Halfword subtraction + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcde00 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x11111111 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wsubhss wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcde00 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x11111111 + test_h_gr r4, 0x01234567 + test_h_gr r5, 0x89abccef + + # Test Unsaturated Word subtraction + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcde00 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x11111111 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wsubw wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcde00 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x11111111 + test_h_gr r4, 0x01234567 + test_h_gr r5, 0x89abccef + + # Test Unsigned saturated Word subtraction + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcde00 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x11111111 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wsubwus wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcde00 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x11111111 + test_h_gr r4, 0x01234567 + test_h_gr r5, 0x89abccef + + # Test Signed saturated Word subtraction + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcde00 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x11111111 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wsubwss wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcde00 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x11111111 + test_h_gr r4, 0x01234567 + test_h_gr r5, 0x89abccef + + pass diff --git a/sim/testsuite/sim/arm/iwmmxt/wunpckeh.cgs b/sim/testsuite/sim/arm/iwmmxt/wunpckeh.cgs new file mode 100644 index 0000000..32a70f4 --- /dev/null +++ b/sim/testsuite/sim/arm/iwmmxt/wunpckeh.cgs @@ -0,0 +1,137 @@ +# Intel(r) Wireless MMX(tm) technology testcase for WUNPCKEH +# mach: xscale +# as: -mcpu=xscale+iwmmxt + + .include "testutils.inc" + + start + + .global wunpckeh +wunpckeh: + # Enable access to CoProcessors 0 & 1 before + # we attempt these instructions. + + mvi_h_gr r1, 3 + mcr p15, 0, r1, cr15, cr1, 0 + + # Test Unsigned Byte Unpacking + + mvi_h_gr r0, 0x12345687 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0 + mvi_h_gr r3, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + + wunpckehub wr1, wr0 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + + test_h_gr r0, 0x12345687 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x00de00f0 + test_h_gr r3, 0x009a00bc + + # Test Signed Byte Unpacking + + mvi_h_gr r0, 0x12345687 + mvi_h_gr r1, 0x7abcdef0 + mvi_h_gr r2, 0 + mvi_h_gr r3, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + + wunpckehsb wr1, wr0 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + + test_h_gr r0, 0x12345687 + test_h_gr r1, 0x7abcdef0 + test_h_gr r2, 0xffdefff0 + test_h_gr r3, 0x007affbc + + # Test Unsigned Halfword Unpacking + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0 + mvi_h_gr r3, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + + wunpckehuh wr1, wr0 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x0000def0 + test_h_gr r3, 0x00009abc + + # Test Signed Halfword Unpacking + + mvi_h_gr r0, 0x12348678 + mvi_h_gr r1, 0x7abcdef0 + mvi_h_gr r2, 0 + mvi_h_gr r3, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + + wunpckehsh wr1, wr0 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + + test_h_gr r0, 0x12348678 + test_h_gr r1, 0x7abcdef0 + test_h_gr r2, 0xffffdef0 + test_h_gr r3, 0x00007abc + + # Test Unsigned Word Unpacking + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0 + mvi_h_gr r3, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + + wunpckehuw wr1, wr0 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x9abcdef0 + test_h_gr r3, 0x00000000 + + # Test Signed Word Unpacking + + mvi_h_gr r0, 0x82345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0 + mvi_h_gr r3, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + + wunpckehsw wr1, wr0 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + + test_h_gr r0, 0x82345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x9abcdef0 + test_h_gr r3, 0xffffffff + + pass diff --git a/sim/testsuite/sim/arm/iwmmxt/wunpckel.cgs b/sim/testsuite/sim/arm/iwmmxt/wunpckel.cgs new file mode 100644 index 0000000..a6ffb4f --- /dev/null +++ b/sim/testsuite/sim/arm/iwmmxt/wunpckel.cgs @@ -0,0 +1,137 @@ +# Intel(r) Wireless MMX(tm) technology testcase for WUNPCKEL +# mach: xscale +# as: -mcpu=xscale+iwmmxt + + .include "testutils.inc" + + start + + .global wunpckel +wunpckel: + # Enable access to CoProcessors 0 & 1 before + # we attempt these instructions. + + mvi_h_gr r1, 3 + mcr p15, 0, r1, cr15, cr1, 0 + + # Test Unsigned Byte Unpacking + + mvi_h_gr r0, 0x12345687 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0 + mvi_h_gr r3, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + + wunpckelub wr1, wr0 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + + test_h_gr r0, 0x12345687 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x00560087 + test_h_gr r3, 0x00120034 + + # Test Signed Byte Unpacking + + mvi_h_gr r0, 0x12345687 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0 + mvi_h_gr r3, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + + wunpckelsb wr1, wr0 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + + test_h_gr r0, 0x12345687 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x0056ff87 + test_h_gr r3, 0x00120034 + + # Test Unsigned Halfword Unpacking + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0 + mvi_h_gr r3, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + + wunpckeluh wr1, wr0 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x00005678 + test_h_gr r3, 0x00001234 + + # Test Signed Halfword Unpacking + + mvi_h_gr r0, 0x12348678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0 + mvi_h_gr r3, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + + wunpckelsh wr1, wr0 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + + test_h_gr r0, 0x12348678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0xffff8678 + test_h_gr r3, 0x00001234 + + # Test Unsigned Word Unpacking + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0 + mvi_h_gr r3, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + + wunpckeluw wr1, wr0 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x12345678 + test_h_gr r3, 0x00000000 + + # Test Signed Word Unpacking + + mvi_h_gr r0, 0x82345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0 + mvi_h_gr r3, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + + wunpckelsw wr1, wr0 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + + test_h_gr r0, 0x82345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x82345678 + test_h_gr r3, 0xffffffff + + pass diff --git a/sim/testsuite/sim/arm/iwmmxt/wunpckih.cgs b/sim/testsuite/sim/arm/iwmmxt/wunpckih.cgs new file mode 100644 index 0000000..41fed0e --- /dev/null +++ b/sim/testsuite/sim/arm/iwmmxt/wunpckih.cgs @@ -0,0 +1,95 @@ +# Intel(r) Wireless MMX(tm) technology testcase for WUNPCKIH +# mach: xscale +# as: -mcpu=xscale+iwmmxt + + .include "testutils.inc" + + start + + .global wunpckih +wunpckih: + # Enable access to CoProcessors 0 & 1 before + # we attempt these instructions. + + mvi_h_gr r1, 3 + mcr p15, 0, r1, cr15, cr1, 0 + + # Test Byte unpacking + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x00000000 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wunpckihb wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x00000000 + test_h_gr r4, 0x00de00f0 + test_h_gr r5, 0x009a00bc + + # Test Halfword unpacking + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x00000000 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wunpckihh wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x00000000 + test_h_gr r4, 0x0000def0 + test_h_gr r5, 0x00009abc + + # Test Word unpacking + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x00000000 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wunpckihw wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x00000000 + test_h_gr r4, 0x9abcdef0 + test_h_gr r5, 0x00000000 + + pass diff --git a/sim/testsuite/sim/arm/iwmmxt/wunpckil.cgs b/sim/testsuite/sim/arm/iwmmxt/wunpckil.cgs new file mode 100644 index 0000000..7bd7300 --- /dev/null +++ b/sim/testsuite/sim/arm/iwmmxt/wunpckil.cgs @@ -0,0 +1,95 @@ +# Intel(r) Wireless MMX(tm) technology testcase for WUNPCKIL +# mach: xscale +# as: -mcpu=xscale+iwmmxt + + .include "testutils.inc" + + start + + .global wunpckil +wunpckil: + # Enable access to CoProcessors 0 & 1 before + # we attempt these instructions. + + mvi_h_gr r1, 3 + mcr p15, 0, r1, cr15, cr1, 0 + + # Test Byte unpacking + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x00000000 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wunpckilb wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x00000000 + test_h_gr r4, 0x11561178 + test_h_gr r5, 0x11121134 + + # Test Halfword unpacking + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x00000000 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wunpckilh wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x00000000 + test_h_gr r4, 0x11115678 + test_h_gr r5, 0x11111234 + + # Test Word unpacking + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x00000000 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wunpckilw wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x00000000 + test_h_gr r4, 0x12345678 + test_h_gr r5, 0x11111111 + + pass diff --git a/sim/testsuite/sim/arm/iwmmxt/wxor.cgs b/sim/testsuite/sim/arm/iwmmxt/wxor.cgs new file mode 100644 index 0000000..95e1fc8 --- /dev/null +++ b/sim/testsuite/sim/arm/iwmmxt/wxor.cgs @@ -0,0 +1,41 @@ +# Intel(r) Wireless MMX(tm) technology testcase for WXOR +# mach: xscale +# as: -mcpu=xscale+iwmmxt + + .include "testutils.inc" + + start + + .global wxor +wxor: + # Enable access to CoProcessors 0 & 1 before + # we attempt these instructions. + + mvi_h_gr r1, 3 + mcr p15, 0, r1, cr15, cr1, 0 + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x00000000 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wxor wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcdef0 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x00000000 + test_h_gr r4, 0x03254769 + test_h_gr r5, 0x9abcdef0 + + pass diff --git a/sim/testsuite/sim/arm/iwmmxt/wzero.cgs b/sim/testsuite/sim/arm/iwmmxt/wzero.cgs new file mode 100644 index 0000000..78fa7c5 --- /dev/null +++ b/sim/testsuite/sim/arm/iwmmxt/wzero.cgs @@ -0,0 +1,29 @@ +# Intel(r) Wireless MMX(tm) technology testcase for WZERO +# mach: xscale +# as: -mcpu=xscale+iwmmxt + + .include "testutils.inc" + + start + + .global wzero +wzero: + # Enable access to CoProcessors 0 & 1 before + # we attempt these instructions. + + mvi_h_gr r1, 3 + mcr p15, 0, r1, cr15, cr1, 0 + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcdef0 + + tmcrr wr0, r0, r1 + + wzero wr0 + + tmrrc r0, r1, wr0 + + test_h_gr r0, 0x00000000 + test_h_gr r1, 0x00000000 + + pass diff --git a/sim/testsuite/sim/arm/ldm.cgs b/sim/testsuite/sim/arm/ldm.cgs new file mode 100644 index 0000000..6831a83 --- /dev/null +++ b/sim/testsuite/sim/arm/ldm.cgs @@ -0,0 +1,89 @@ +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldmda_wb +ldmda_wb: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldmda +ldmda: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldmdb_wb +ldmdb_wb: + + pass +# arm testcase for ldm$cond .. +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldmdb +ldmdb: + ldm0 .. + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldmia_wb +ldmia_wb: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldmia +ldmia: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldmib_wb +ldmib_wb: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldmib +ldmib: + + pass diff --git a/sim/testsuite/sim/arm/ldr.cgs b/sim/testsuite/sim/arm/ldr.cgs new file mode 100644 index 0000000..437b68c --- /dev/null +++ b/sim/testsuite/sim/arm/ldr.cgs @@ -0,0 +1,192 @@ +# arm testcase for ldr${cond} $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldr_post_dec_imm_offset +ldr_post_dec_imm_offset: + ldr0 pc,??? + + pass +# arm testcase for ldr${cond}t $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldr_post_dec_nonpriv_imm_offset +ldr_post_dec_nonpriv_imm_offset: + ldr0t pc,??? + + pass +# arm testcase for ldr${cond}t $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldr_post_dec_nonpriv_reg_offset +ldr_post_dec_nonpriv_reg_offset: + ldr0t pc,??? + + pass +# arm testcase for ldr${cond} $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldr_post_dec_reg_offset +ldr_post_dec_reg_offset: + ldr0 pc,??? + + pass +# arm testcase for ldr${cond} $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldr_post_inc_imm_offset +ldr_post_inc_imm_offset: + ldr0 pc,??? + + pass +# arm testcase for ldr${cond}t $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldr_post_inc_nonpriv_imm_offset +ldr_post_inc_nonpriv_imm_offset: + ldr0t pc,??? + + pass +# arm testcase for ldr${cond}t $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldr_post_inc_nonpriv_reg_offset +ldr_post_inc_nonpriv_reg_offset: + ldr0t pc,??? + + pass +# arm testcase for ldr${cond} $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldr_post_inc_reg_offset +ldr_post_inc_reg_offset: + ldr0 pc,??? + + pass +# arm testcase for ldr${cond} $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldr_pre_dec_imm_offset +ldr_pre_dec_imm_offset: + ldr0 pc,??? + + pass +# arm testcase for ldr${cond} $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldr_pre_dec_reg_offset +ldr_pre_dec_reg_offset: + ldr0 pc,??? + + pass +# arm testcase for ldr${cond} $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldr_pre_dec_wb_imm_offset +ldr_pre_dec_wb_imm_offset: + ldr0 pc,??? + + pass +# arm testcase for ldr${cond} $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldr_pre_dec_wb_reg_offset +ldr_pre_dec_wb_reg_offset: + ldr0 pc,??? + + pass +# arm testcase for ldr${cond} $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldr_pre_inc_imm_offset +ldr_pre_inc_imm_offset: + ldr0 pc,??? + + pass +# arm testcase for ldr${cond} $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldr_pre_inc_reg_offset +ldr_pre_inc_reg_offset: + ldr0 pc,??? + + pass +# arm testcase for ldr${cond} $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldr_pre_inc_wb_imm_offset +ldr_pre_inc_wb_imm_offset: + ldr0 pc,??? + + pass +# arm testcase for ldr${cond} $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldr_pre_inc_wb_reg_offset +ldr_pre_inc_wb_reg_offset: + ldr0 pc,??? + + pass diff --git a/sim/testsuite/sim/arm/ldrb.cgs b/sim/testsuite/sim/arm/ldrb.cgs new file mode 100644 index 0000000..b09880c --- /dev/null +++ b/sim/testsuite/sim/arm/ldrb.cgs @@ -0,0 +1,192 @@ +# arm testcase for ldr${cond}b $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrb_post_dec_imm_offset +ldrb_post_dec_imm_offset: + ldr0b pc,??? + + pass +# arm testcase for ldr${cond}bt $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrb_post_dec_nonpriv_imm_offset +ldrb_post_dec_nonpriv_imm_offset: + ldr0bt pc,??? + + pass +# arm testcase for ldr${cond}bt $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrb_post_dec_nonpriv_reg_offset +ldrb_post_dec_nonpriv_reg_offset: + ldr0bt pc,??? + + pass +# arm testcase for ldr${cond}b $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrb_post_dec_reg_offset +ldrb_post_dec_reg_offset: + ldr0b pc,??? + + pass +# arm testcase for ldr${cond}b $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrb_post_inc_imm_offset +ldrb_post_inc_imm_offset: + ldr0b pc,??? + + pass +# arm testcase for ldr${cond}bt $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrb_post_inc_nonpriv_imm_offset +ldrb_post_inc_nonpriv_imm_offset: + ldr0bt pc,??? + + pass +# arm testcase for ldr${cond}bt $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrb_post_inc_nonpriv_reg_offset +ldrb_post_inc_nonpriv_reg_offset: + ldr0bt pc,??? + + pass +# arm testcase for ldr${cond}b $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrb_post_inc_reg_offset +ldrb_post_inc_reg_offset: + ldr0b pc,??? + + pass +# arm testcase for ldr${cond}b $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrb_pre_dec_imm_offset +ldrb_pre_dec_imm_offset: + ldr0b pc,??? + + pass +# arm testcase for ldr${cond}b $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrb_pre_dec_reg_offset +ldrb_pre_dec_reg_offset: + ldr0b pc,??? + + pass +# arm testcase for ldr${cond}b $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrb_pre_dec_wb_imm_offset +ldrb_pre_dec_wb_imm_offset: + ldr0b pc,??? + + pass +# arm testcase for ldr${cond}b $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrb_pre_dec_wb_reg_offset +ldrb_pre_dec_wb_reg_offset: + ldr0b pc,??? + + pass +# arm testcase for ldr${cond}b $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrb_pre_inc_imm_offset +ldrb_pre_inc_imm_offset: + ldr0b pc,??? + + pass +# arm testcase for ldr${cond}b $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrb_pre_inc_reg_offset +ldrb_pre_inc_reg_offset: + ldr0b pc,??? + + pass +# arm testcase for ldr${cond}b $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrb_pre_inc_wb_imm_offset +ldrb_pre_inc_wb_imm_offset: + ldr0b pc,??? + + pass +# arm testcase for ldr${cond}b $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrb_pre_inc_wb_reg_offset +ldrb_pre_inc_wb_reg_offset: + ldr0b pc,??? + + pass diff --git a/sim/testsuite/sim/arm/ldrh.cgs b/sim/testsuite/sim/arm/ldrh.cgs new file mode 100644 index 0000000..16a4323 --- /dev/null +++ b/sim/testsuite/sim/arm/ldrh.cgs @@ -0,0 +1,132 @@ +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrh_post_dec_imm_offset +ldrh_post_dec_imm_offset: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrh_post_dec_reg_offset +ldrh_post_dec_reg_offset: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrh_post_inc_imm_offset +ldrh_post_inc_imm_offset: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrh_post_inc_reg_offset +ldrh_post_inc_reg_offset: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrh_pre_dec_imm_offset +ldrh_pre_dec_imm_offset: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrh_pre_dec_reg_offset +ldrh_pre_dec_reg_offset: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrh_pre_dec_wb_imm_offset +ldrh_pre_dec_wb_imm_offset: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrh_pre_dec_wb_reg_offset +ldrh_pre_dec_wb_reg_offset: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrh_pre_inc_imm_offset +ldrh_pre_inc_imm_offset: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrh_pre_inc_reg_offset +ldrh_pre_inc_reg_offset: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrh_pre_inc_wb_imm_offset +ldrh_pre_inc_wb_imm_offset: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrh_pre_inc_wb_reg_offset +ldrh_pre_inc_wb_reg_offset: + + pass diff --git a/sim/testsuite/sim/arm/ldrsb.cgs b/sim/testsuite/sim/arm/ldrsb.cgs new file mode 100644 index 0000000..4d08f4c --- /dev/null +++ b/sim/testsuite/sim/arm/ldrsb.cgs @@ -0,0 +1,132 @@ +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrsb_post_dec_imm_offset +ldrsb_post_dec_imm_offset: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrsb_post_dec_reg_offset +ldrsb_post_dec_reg_offset: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrsb_post_inc_imm_offset +ldrsb_post_inc_imm_offset: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrsb_post_inc_reg_offset +ldrsb_post_inc_reg_offset: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrsb_pre_dec_imm_offset +ldrsb_pre_dec_imm_offset: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrsb_pre_dec_reg_offset +ldrsb_pre_dec_reg_offset: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrsb_pre_dec_wb_imm_offset +ldrsb_pre_dec_wb_imm_offset: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrsb_pre_dec_wb_reg_offset +ldrsb_pre_dec_wb_reg_offset: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrsb_pre_inc_imm_offset +ldrsb_pre_inc_imm_offset: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrsb_pre_inc_reg_offset +ldrsb_pre_inc_reg_offset: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrsb_pre_inc_wb_imm_offset +ldrsb_pre_inc_wb_imm_offset: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrsb_pre_inc_wb_reg_offset +ldrsb_pre_inc_wb_reg_offset: + + pass diff --git a/sim/testsuite/sim/arm/ldrsh.cgs b/sim/testsuite/sim/arm/ldrsh.cgs new file mode 100644 index 0000000..5a6e7c7 --- /dev/null +++ b/sim/testsuite/sim/arm/ldrsh.cgs @@ -0,0 +1,132 @@ +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrsh_post_dec_imm_offset +ldrsh_post_dec_imm_offset: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrsh_post_dec_reg_offset +ldrsh_post_dec_reg_offset: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrsh_post_inc_imm_offset +ldrsh_post_inc_imm_offset: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrsh_post_inc_reg_offset +ldrsh_post_inc_reg_offset: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrsh_pre_dec_imm_offset +ldrsh_pre_dec_imm_offset: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrsh_pre_dec_reg_offset +ldrsh_pre_dec_reg_offset: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrsh_pre_dec_wb_imm_offset +ldrsh_pre_dec_wb_imm_offset: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrsh_pre_dec_wb_reg_offset +ldrsh_pre_dec_wb_reg_offset: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrsh_pre_inc_imm_offset +ldrsh_pre_inc_imm_offset: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrsh_pre_inc_reg_offset +ldrsh_pre_inc_reg_offset: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrsh_pre_inc_wb_imm_offset +ldrsh_pre_inc_wb_imm_offset: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrsh_pre_inc_wb_reg_offset +ldrsh_pre_inc_wb_reg_offset: + + pass diff --git a/sim/testsuite/sim/arm/misaligned1.ms b/sim/testsuite/sim/arm/misaligned1.ms new file mode 100644 index 0000000..69fda47 --- /dev/null +++ b/sim/testsuite/sim/arm/misaligned1.ms @@ -0,0 +1,61 @@ +# Test LDR instructions with offsets misaligned by 1 byte. +# mach(): all + + .macro invalid +# This is "undefined" but it's not properly decoded yet. + .word 0x07ffffff +# This is stc which isn't recognized yet. + stc 0,cr0,[r0] + .endm + + .global _start +_start: +# Run some simple insns to confirm the engine is at least working. + nop + +# Skip over output text. + bl do_test + +pass: + .asciz "pass\n" + .p2align 2 + +do_test: + mov r4, r14 + bl continue +word1: + .word 0x5555 +continue: + ldr r6, [r14, #1] + ldr r7, word2 + cmp r6, r7 + # Failed. + bne done + +output_next: +# Output a character (in arm mode). + mov r0,#3 + mov r1,r4 + swi #0x123456 + +# Load next character, see if done. + add r4,r4,#1 + sub r3,r3,r3 + ldrb r5,[r4,r3] + teq r5,#0 + bne output_next + +done: + mov r0,#0x18 + ldr r1,exit_code + swi #0x123456 + +# If that fails, try to die with an invalid insn. + invalid + +exit_code: + .word 0x20026 + .word 0xFFFFFFFF +word2: + .word 0x55000055 + .word 0xFFFFFFFF diff --git a/sim/testsuite/sim/arm/misaligned2.ms b/sim/testsuite/sim/arm/misaligned2.ms new file mode 100644 index 0000000..3a03326 --- /dev/null +++ b/sim/testsuite/sim/arm/misaligned2.ms @@ -0,0 +1,60 @@ +# Test LDR instructions with offsets misaligned by 2 bytes. +# mach(): all + + .macro invalid +# This is "undefined" but it's not properly decoded yet. + .word 0x07ffffff +# This is stc which isn't recognized yet. + stc 0,cr0,[r0] + .endm + + .global _start +_start: +# Run some simple insns to confirm the engine is at least working. + nop + +# Skip over output text. + bl do_test + +pass: + .asciz "pass\n" + .p2align 2 + +do_test: + mov r4, r14 + bl continue +word1: + .word 0x5555 +continue: + ldr r6, [r14, #2] + ldr r7, word2 + cmp r6, r7 + # Failed. + bne done + +output_next: +# Output a character (in arm mode). + mov r0,#3 + mov r1,r4 + swi #0x123456 + +# Load next character, see if done. + add r4,r4,#1 + sub r3,r3,r3 + ldrb r5,[r4,r3] + teq r5,#0 + bne output_next + +done: + mov r0,#0x18 + ldr r1,exit_code + swi #0x123456 + +# If that fails, try to die with an invalid insn. + invalid + +exit_code: + .word 0x20026 + +word2: + .word 0x55550000 diff --git a/sim/testsuite/sim/arm/misaligned3.ms b/sim/testsuite/sim/arm/misaligned3.ms new file mode 100644 index 0000000..bf2d9f1 --- /dev/null +++ b/sim/testsuite/sim/arm/misaligned3.ms @@ -0,0 +1,62 @@ +# Test LDR instructions with offsets misaligned by 3 bytes. +# mach(): all + + .macro invalid +# This is "undefined" but it's not properly decoded yet. + .word 0x07ffffff +# This is stc which isn't recognized yet. + stc 0,cr0,[r0] + .endm + + .global _start +_start: +# Run some simple insns to confirm the engine is at least working. + nop + +# Skip over output text. + bl do_test + +pass: + .asciz "pass\n" + .p2align 2 + +do_test: + mov r4, r14 + bl continue +word1: + .word 0x5555 +continue: + ldr r6, [r14, #3] + ldr r7, word2 + cmp r6, r7 + # Failed. + bne done + +output_next: +# Output a character (in arm mode). + mov r0,#3 + mov r1,r4 + swi #0x123456 + +# Load next character, see if done. + add r4,r4,#1 + sub r3,r3,r3 + ldrb r5,[r4,r3] + teq r5,#0 + bne output_next + +done: + mov r0,#0x18 + ldr r1,exit_code + swi #0x123456 + +# If that fails, try to die with an invalid insn. + invalid + +exit_code: + .word 0x20026 + + .word 0xFFFFFFFF +word2: + .word 0x555500 + .word 0xFFFFFFFF diff --git a/sim/testsuite/sim/arm/misc.exp b/sim/testsuite/sim/arm/misc.exp new file mode 100644 index 0000000..1e8006f --- /dev/null +++ b/sim/testsuite/sim/arm/misc.exp @@ -0,0 +1,20 @@ +# Miscellaneous ARM simulator testcases + +if { [istarget arm*-*-*] || [istarget thumb*-*-*] || [istarget xscale*-*-*] } { + # load support procs + # load_lib cgen.exp + + # all machines + set all_machs "arm7tdmi" + + # The .ms suffix is for "miscellaneous .s". + foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.ms]] { + # If we're only testing specific files and this isn't one of them, + # skip it. + if ![runtest_file_p $runtests $src] { + continue + } + + run_sim_test $src $all_machs + } +} diff --git a/sim/testsuite/sim/arm/mla.cgs b/sim/testsuite/sim/arm/mla.cgs new file mode 100644 index 0000000..c82dd0c --- /dev/null +++ b/sim/testsuite/sim/arm/mla.cgs @@ -0,0 +1,12 @@ +# arm testcase for mla$cond${set-cc?} ${mul-rd},$rm,$rs,${mul-rn} +# mach: unfinished + + .include "testutils.inc" + + start + + .global mla +mla: + mla00 pc,pc,pc,pc + + pass diff --git a/sim/testsuite/sim/arm/mov.cgs b/sim/testsuite/sim/arm/mov.cgs new file mode 100644 index 0000000..d2a83d3 --- /dev/null +++ b/sim/testsuite/sim/arm/mov.cgs @@ -0,0 +1,36 @@ +# arm testcase for mov$cond${set-cc?} $rd,$imm12 +# mach: unfinished + + .include "testutils.inc" + + start + + .global mov_imm +mov_imm: + mov00 pc,0 + + pass +# arm testcase for mov$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm} +# mach: unfinished + + .include "testutils.inc" + + start + + .global mov_reg_imm_shift +mov_reg_imm_shift: + mov00 pc,pc,pc,lsl 0 + + pass +# arm testcase for mov$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg} +# mach: unfinished + + .include "testutils.inc" + + start + + .global mov_reg_reg_shift +mov_reg_reg_shift: + mov00 pc,pc,pc,lsl pc + + pass diff --git a/sim/testsuite/sim/arm/mrs.cgs b/sim/testsuite/sim/arm/mrs.cgs new file mode 100644 index 0000000..22c5e95 --- /dev/null +++ b/sim/testsuite/sim/arm/mrs.cgs @@ -0,0 +1,24 @@ +# arm testcase for mrs$cond $rd,cpsr +# mach: unfinished + + .include "testutils.inc" + + start + + .global mrs_c +mrs_c: + mrs0 pc,cpsr + + pass +# arm testcase for mrs$cond $rd,spsr +# mach: unfinished + + .include "testutils.inc" + + start + + .global mrs_s +mrs_s: + mrs0 pc,spsr + + pass diff --git a/sim/testsuite/sim/arm/msr.cgs b/sim/testsuite/sim/arm/msr.cgs new file mode 100644 index 0000000..c79f0bd --- /dev/null +++ b/sim/testsuite/sim/arm/msr.cgs @@ -0,0 +1,24 @@ +# arm testcase for msr$cond cpsr,$rm +# mach: unfinished + + .include "testutils.inc" + + start + + .global msr_c +msr_c: + msr0 cpsr,pc + + pass +# arm testcase for msr$cond spsr,$rm +# mach: unfinished + + .include "testutils.inc" + + start + + .global msr_s +msr_s: + msr0 spsr,pc + + pass diff --git a/sim/testsuite/sim/arm/mul.cgs b/sim/testsuite/sim/arm/mul.cgs new file mode 100644 index 0000000..4f0a926 --- /dev/null +++ b/sim/testsuite/sim/arm/mul.cgs @@ -0,0 +1,12 @@ +# arm testcase for mul$cond${set-cc?} ${mul-rd},$rm,$rs +# mach: unfinished + + .include "testutils.inc" + + start + + .global mul +mul: + mul00 pc,pc,pc + + pass diff --git a/sim/testsuite/sim/arm/mvn.cgs b/sim/testsuite/sim/arm/mvn.cgs new file mode 100644 index 0000000..92fd3a4 --- /dev/null +++ b/sim/testsuite/sim/arm/mvn.cgs @@ -0,0 +1,36 @@ +# arm testcase for mvn$cond${set-cc?} $rd,$imm12 +# mach: unfinished + + .include "testutils.inc" + + start + + .global mvn_imm +mvn_imm: + mvn00 pc,0 + + pass +# arm testcase for mvn$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm} +# mach: unfinished + + .include "testutils.inc" + + start + + .global mvn_reg_imm_shift +mvn_reg_imm_shift: + mvn00 pc,pc,pc,lsl 0 + + pass +# arm testcase for mvn$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg} +# mach: unfinished + + .include "testutils.inc" + + start + + .global mvn_reg_reg_shift +mvn_reg_reg_shift: + mvn00 pc,pc,pc,lsl pc + + pass diff --git a/sim/testsuite/sim/arm/orr.cgs b/sim/testsuite/sim/arm/orr.cgs new file mode 100644 index 0000000..3fc67ad --- /dev/null +++ b/sim/testsuite/sim/arm/orr.cgs @@ -0,0 +1,36 @@ +# arm testcase for orr$cond${set-cc?} $rd,$rn,$imm12 +# mach: unfinished + + .include "testutils.inc" + + start + + .global orr_imm +orr_imm: + orr00 pc,pc,0 + + pass +# arm testcase for orr$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm} +# mach: unfinished + + .include "testutils.inc" + + start + + .global orr_reg_imm_shift +orr_reg_imm_shift: + orr00 pc,pc,pc,lsl 0 + + pass +# arm testcase for orr$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg} +# mach: unfinished + + .include "testutils.inc" + + start + + .global orr_reg_reg_shift +orr_reg_reg_shift: + orr00 pc,pc,pc,lsl pc + + pass diff --git a/sim/testsuite/sim/arm/rsb.cgs b/sim/testsuite/sim/arm/rsb.cgs new file mode 100644 index 0000000..14edc35 --- /dev/null +++ b/sim/testsuite/sim/arm/rsb.cgs @@ -0,0 +1,36 @@ +# arm testcase for rsb$cond${set-cc?} $rd,$rn,$imm12 +# mach: unfinished + + .include "testutils.inc" + + start + + .global rsb_imm +rsb_imm: + rsb00 pc,pc,0 + + pass +# arm testcase for rsb$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm} +# mach: unfinished + + .include "testutils.inc" + + start + + .global rsb_reg_imm_shift +rsb_reg_imm_shift: + rsb00 pc,pc,pc,lsl 0 + + pass +# arm testcase for rsb$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg} +# mach: unfinished + + .include "testutils.inc" + + start + + .global rsb_reg_reg_shift +rsb_reg_reg_shift: + rsb00 pc,pc,pc,lsl pc + + pass diff --git a/sim/testsuite/sim/arm/rsc.cgs b/sim/testsuite/sim/arm/rsc.cgs new file mode 100644 index 0000000..078fbcc --- /dev/null +++ b/sim/testsuite/sim/arm/rsc.cgs @@ -0,0 +1,36 @@ +# arm testcase for rsc$cond${set-cc?} $rd,$rn,$imm12 +# mach: unfinished + + .include "testutils.inc" + + start + + .global rsc_imm +rsc_imm: + rsc00 pc,pc,0 + + pass +# arm testcase for rsc$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm} +# mach: unfinished + + .include "testutils.inc" + + start + + .global rsc_reg_imm_shift +rsc_reg_imm_shift: + rsc00 pc,pc,pc,lsl 0 + + pass +# arm testcase for rsc$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg} +# mach: unfinished + + .include "testutils.inc" + + start + + .global rsc_reg_reg_shift +rsc_reg_reg_shift: + rsc00 pc,pc,pc,lsl pc + + pass diff --git a/sim/testsuite/sim/arm/sbc.cgs b/sim/testsuite/sim/arm/sbc.cgs new file mode 100644 index 0000000..9462702 --- /dev/null +++ b/sim/testsuite/sim/arm/sbc.cgs @@ -0,0 +1,36 @@ +# arm testcase for sbc$cond${set-cc?} $rd,$rn,$imm12 +# mach: unfinished + + .include "testutils.inc" + + start + + .global sbc_imm +sbc_imm: + sbc00 pc,pc,0 + + pass +# arm testcase for sbc$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm} +# mach: unfinished + + .include "testutils.inc" + + start + + .global sbc_reg_imm_shift +sbc_reg_imm_shift: + sbc00 pc,pc,pc,lsl 0 + + pass +# arm testcase for sbc$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg} +# mach: unfinished + + .include "testutils.inc" + + start + + .global sbc_reg_reg_shift +sbc_reg_reg_shift: + sbc00 pc,pc,pc,lsl pc + + pass diff --git a/sim/testsuite/sim/arm/smlal.cgs b/sim/testsuite/sim/arm/smlal.cgs new file mode 100644 index 0000000..4ad1373 --- /dev/null +++ b/sim/testsuite/sim/arm/smlal.cgs @@ -0,0 +1,12 @@ +# arm testcase for smlal$cond${set-cc?} $rdlo,$rdhi,$rm,$rs +# mach: unfinished + + .include "testutils.inc" + + start + + .global smlal +smlal: + smlal00 pc,pc,pc,pc + + pass diff --git a/sim/testsuite/sim/arm/smull.cgs b/sim/testsuite/sim/arm/smull.cgs new file mode 100644 index 0000000..22e3960 --- /dev/null +++ b/sim/testsuite/sim/arm/smull.cgs @@ -0,0 +1,12 @@ +# arm testcase for smull$cond${set-cc?} $rdlo,$rdhi,$rm,$rs +# mach: unfinished + + .include "testutils.inc" + + start + + .global smull +smull: + smull00 pc,pc,pc,pc + + pass diff --git a/sim/testsuite/sim/arm/stm.cgs b/sim/testsuite/sim/arm/stm.cgs new file mode 100644 index 0000000..c381216 --- /dev/null +++ b/sim/testsuite/sim/arm/stm.cgs @@ -0,0 +1,88 @@ +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global stmda_wb +stmda_wb: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global stmda +stmda: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global stmdb_wb +stmdb_wb: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global stmdb +stmdb: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global stmia_wb +stmia_wb: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global stmia +stmia: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global stmib_wb +stmib_wb: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global stmib +stmib: + + pass diff --git a/sim/testsuite/sim/arm/str.cgs b/sim/testsuite/sim/arm/str.cgs new file mode 100644 index 0000000..82c683b --- /dev/null +++ b/sim/testsuite/sim/arm/str.cgs @@ -0,0 +1,192 @@ +# arm testcase for ldr${cond} $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global str_post_dec_imm_offset +str_post_dec_imm_offset: + ldr0 pc,??? + + pass +# arm testcase for ldr${cond}t $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global str_post_dec_nonpriv_imm_offset +str_post_dec_nonpriv_imm_offset: + ldr0t pc,??? + + pass +# arm testcase for str${cond}t $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global str_post_dec_nonpriv_reg_offset +str_post_dec_nonpriv_reg_offset: + str0t pc,??? + + pass +# arm testcase for str${cond} $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global str_post_dec_reg_offset +str_post_dec_reg_offset: + str0 pc,??? + + pass +# arm testcase for ldr${cond} $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global str_post_inc_imm_offset +str_post_inc_imm_offset: + ldr0 pc,??? + + pass +# arm testcase for ldr${cond}t $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global str_post_inc_nonpriv_imm_offset +str_post_inc_nonpriv_imm_offset: + ldr0t pc,??? + + pass +# arm testcase for str${cond}t $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global str_post_inc_nonpriv_reg_offset +str_post_inc_nonpriv_reg_offset: + str0t pc,??? + + pass +# arm testcase for str${cond} $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global str_post_inc_reg_offset +str_post_inc_reg_offset: + str0 pc,??? + + pass +# arm testcase for ldr${cond} $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global str_pre_dec_imm_offset +str_pre_dec_imm_offset: + ldr0 pc,??? + + pass +# arm testcase for str${cond} $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global str_pre_dec_reg_offset +str_pre_dec_reg_offset: + str0 pc,??? + + pass +# arm testcase for ldr${cond} $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global str_pre_dec_wb_imm_offset +str_pre_dec_wb_imm_offset: + ldr0 pc,??? + + pass +# arm testcase for str${cond} $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global str_pre_dec_wb_reg_offset +str_pre_dec_wb_reg_offset: + str0 pc,??? + + pass +# arm testcase for ldr${cond} $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global str_pre_inc_imm_offset +str_pre_inc_imm_offset: + ldr0 pc,??? + + pass +# arm testcase for str${cond} $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global str_pre_inc_reg_offset +str_pre_inc_reg_offset: + str0 pc,??? + + pass +# arm testcase for ldr${cond} $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global str_pre_inc_wb_imm_offset +str_pre_inc_wb_imm_offset: + ldr0 pc,??? + + pass +# arm testcase for str${cond} $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global str_pre_inc_wb_reg_offset +str_pre_inc_wb_reg_offset: + str0 pc,??? + + pass diff --git a/sim/testsuite/sim/arm/strb.cgs b/sim/testsuite/sim/arm/strb.cgs new file mode 100644 index 0000000..875a649 --- /dev/null +++ b/sim/testsuite/sim/arm/strb.cgs @@ -0,0 +1,192 @@ +# arm testcase for ldr${cond}b $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global strb_post_dec_imm_offset +strb_post_dec_imm_offset: + ldr0b pc,??? + + pass +# arm testcase for ldr${cond}t $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global strb_post_dec_nonpriv_imm_offset +strb_post_dec_nonpriv_imm_offset: + ldr0t pc,??? + + pass +# arm testcase for str${cond}t $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global strb_post_dec_nonpriv_reg_offset +strb_post_dec_nonpriv_reg_offset: + str0t pc,??? + + pass +# arm testcase for str${cond}b $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global strb_post_dec_reg_offset +strb_post_dec_reg_offset: + str0b pc,??? + + pass +# arm testcase for ldr${cond} $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global strb_post_inc_imm_offset +strb_post_inc_imm_offset: + ldr0 pc,??? + + pass +# arm testcase for ldr${cond}t $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global strb_post_inc_nonpriv_imm_offset +strb_post_inc_nonpriv_imm_offset: + ldr0t pc,??? + + pass +# arm testcase for str${cond}t $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global strb_post_inc_nonpriv_reg_offset +strb_post_inc_nonpriv_reg_offset: + str0t pc,??? + + pass +# arm testcase for str${cond} $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global strb_post_inc_reg_offset +strb_post_inc_reg_offset: + str0 pc,??? + + pass +# arm testcase for ldr${cond} $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global strb_pre_dec_imm_offset +strb_pre_dec_imm_offset: + ldr0 pc,??? + + pass +# arm testcase for str${cond} $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global strb_pre_dec_reg_offset +strb_pre_dec_reg_offset: + str0 pc,??? + + pass +# arm testcase for ldr${cond} $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global strb_pre_dec_wb_imm_offset +strb_pre_dec_wb_imm_offset: + ldr0 pc,??? + + pass +# arm testcase for str${cond} $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global strb_pre_dec_wb_reg_offset +strb_pre_dec_wb_reg_offset: + str0 pc,??? + + pass +# arm testcase for ldr${cond} $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global strb_pre_inc_imm_offset +strb_pre_inc_imm_offset: + ldr0 pc,??? + + pass +# arm testcase for str${cond} $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global strb_pre_inc_reg_offset +strb_pre_inc_reg_offset: + str0 pc,??? + + pass +# arm testcase for ldr${cond} $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global strb_pre_inc_wb_imm_offset +strb_pre_inc_wb_imm_offset: + ldr0 pc,??? + + pass +# arm testcase for str${cond} $rd,??? +# mach: unfinished + + .include "testutils.inc" + + start + + .global strb_pre_inc_wb_reg_offset +strb_pre_inc_wb_reg_offset: + str0 pc,??? + + pass diff --git a/sim/testsuite/sim/arm/strh.cgs b/sim/testsuite/sim/arm/strh.cgs new file mode 100644 index 0000000..e111d48 --- /dev/null +++ b/sim/testsuite/sim/arm/strh.cgs @@ -0,0 +1,132 @@ +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global strh_post_dec_imm_offset +strh_post_dec_imm_offset: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global strh_post_dec_reg_offset +strh_post_dec_reg_offset: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global strh_post_inc_imm_offset +strh_post_inc_imm_offset: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global strh_post_inc_reg_offset +strh_post_inc_reg_offset: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global strh_pre_dec_imm_offset +strh_pre_dec_imm_offset: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global strh_pre_dec_reg_offset +strh_pre_dec_reg_offset: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global strh_pre_dec_wb_imm_offset +strh_pre_dec_wb_imm_offset: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global strh_pre_dec_wb_reg_offset +strh_pre_dec_wb_reg_offset: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global strh_pre_inc_imm_offset +strh_pre_inc_imm_offset: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global strh_pre_inc_reg_offset +strh_pre_inc_reg_offset: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global strh_pre_inc_wb_imm_offset +strh_pre_inc_wb_imm_offset: + + pass +# arm testcase for FIXME +# mach: unfinished + + .include "testutils.inc" + + start + + .global strh_pre_inc_wb_reg_offset +strh_pre_inc_wb_reg_offset: + + pass diff --git a/sim/testsuite/sim/arm/sub.cgs b/sim/testsuite/sim/arm/sub.cgs new file mode 100644 index 0000000..50f222c --- /dev/null +++ b/sim/testsuite/sim/arm/sub.cgs @@ -0,0 +1,36 @@ +# arm testcase for sub$cond${set-cc?} $rd,$rn,$imm12 +# mach: unfinished + + .include "testutils.inc" + + start + + .global sub_imm +sub_imm: + sub00 pc,pc,0 + + pass +# arm testcase for sub$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm} +# mach: unfinished + + .include "testutils.inc" + + start + + .global sub_reg_imm_shift +sub_reg_imm_shift: + sub00 pc,pc,pc,lsl 0 + + pass +# arm testcase for sub$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg} +# mach: unfinished + + .include "testutils.inc" + + start + + .global sub_reg_reg_shift +sub_reg_reg_shift: + sub00 pc,pc,pc,lsl pc + + pass diff --git a/sim/testsuite/sim/arm/swi.cgs b/sim/testsuite/sim/arm/swi.cgs new file mode 100644 index 0000000..0c23d43 --- /dev/null +++ b/sim/testsuite/sim/arm/swi.cgs @@ -0,0 +1,12 @@ +# arm testcase for swi$cond ${swi-comment} +# mach: unfinished + + .include "testutils.inc" + + start + + .global swi +swi: + swi0 0 + + pass diff --git a/sim/testsuite/sim/arm/swp.cgs b/sim/testsuite/sim/arm/swp.cgs new file mode 100644 index 0000000..f965ef2 --- /dev/null +++ b/sim/testsuite/sim/arm/swp.cgs @@ -0,0 +1,12 @@ +# arm testcase for swp$cond $rd,$rm,[$rn] +# mach: unfinished + + .include "testutils.inc" + + start + + .global swp +swp: + swp0 pc,pc,[pc] + + pass diff --git a/sim/testsuite/sim/arm/swpb.cgs b/sim/testsuite/sim/arm/swpb.cgs new file mode 100644 index 0000000..6f8a076 --- /dev/null +++ b/sim/testsuite/sim/arm/swpb.cgs @@ -0,0 +1,12 @@ +# arm testcase for swpb${cond}b $rd,$rm,[$rn] +# mach: unfinished + + .include "testutils.inc" + + start + + .global swpb +swpb: + swpb0b pc,pc,[pc] + + pass diff --git a/sim/testsuite/sim/arm/teq.cgs b/sim/testsuite/sim/arm/teq.cgs new file mode 100644 index 0000000..6c69347 --- /dev/null +++ b/sim/testsuite/sim/arm/teq.cgs @@ -0,0 +1,36 @@ +# arm testcase for teq${cond}${set-cc?} $rn,$imm12 +# mach: unfinished + + .include "testutils.inc" + + start + + .global teq_imm +teq_imm: + teq00 pc,0 + + pass +# arm testcase for teq$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm} +# mach: unfinished + + .include "testutils.inc" + + start + + .global teq_reg_imm_shift +teq_reg_imm_shift: + teq00 pc,pc,pc,lsl 0 + + pass +# arm testcase for teq$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg} +# mach: unfinished + + .include "testutils.inc" + + start + + .global teq_reg_reg_shift +teq_reg_reg_shift: + teq00 pc,pc,pc,lsl pc + + pass diff --git a/sim/testsuite/sim/arm/testutils.inc b/sim/testsuite/sim/arm/testutils.inc new file mode 100644 index 0000000..ae49db8 --- /dev/null +++ b/sim/testsuite/sim/arm/testutils.inc @@ -0,0 +1,118 @@ +# r0-r3 are used as tmps, consider them call clobbered by these macros. +# This uses the angel rom monitor calls. +# ??? How do we use the \@ facility of .macros ??? +# @ is the comment char! + + .macro mvi_h_gr reg, val + ldr \reg,[pc] + b . + 8 + .word \val + .endm + + .macro mvaddr_h_gr reg, addr + ldr \reg,[pc] + b . + 8 + .word \addr + .endm + + .macro start + .data +failmsg: + .asciz "fail\n" +passmsg: + .asciz "pass\n" + .text + +do_pass: + ldr r1, passmsg_addr + mov r0, #4 + swi #0x123456 + exit 0 +passmsg_addr: + .word passmsg + +do_fail: + ldr r1, failmsg_addr + mov r0, #4 + swi #0x123456 + exit 1 +failmsg_addr: + .word failmsg + + .global _start +_start: + .endm + +# *** Other macros know pass/fail are 4 bytes in size! Yuck. + + .macro pass + b do_pass + .endm + + .macro fail + b do_fail + .endm + + .macro exit rc + # ??? This works with the ARMulator but maybe not others. + #mov r0, #\rc + #swi #1 + # This seems to be portable (though it ignores rc). + mov r0,#0x18 + mvi_h_gr r1, 0x20026 + swi #0x123456 + # If that returns, punt with a sigill. + stc 0,cr0,[r0] + .endm + +# Other macros know this only clobbers r0. +# WARNING: It also clobbers the condition codes (FIXME). + .macro test_h_gr reg, val + mvaddr_h_gr r0, \val + cmp \reg, r0 + beq . + 8 + fail + .endm + + .macro mvi_h_cnvz c, n, v, z + mov r0, #0 + .if \c + orr r0, r0, #0x20000000 + .endif + .if \n + orr r0, r0, #0x80000000 + .endif + .if \v + orr r0, r0, #0x10000000 + .endif + .if \z + orr r0, r0, #0x40000000 + .endif + mrs r1, cpsr + bic r1, r1, #0xf0000000 + orr r1, r1, r0 + msr cpsr, r1 + # ??? nops needed + .endm + +# ??? Preserve condition codes? + .macro test_h_cnvz c, n, v, z + mov r0, #0 + .if \c + orr r0, r0, #0x20000000 + .endif + .if \n + orr r0, r0, #0x80000000 + .endif + .if \v + orr r0, r0, #0x10000000 + .endif + .if \z + orr r0, r0, #0x40000000 + .endif + mrs r1, cpsr + and r1, r1, #0xf0000000 + cmp r0, r1 + beq . + 8 + fail + .endm diff --git a/sim/testsuite/sim/arm/thumb/adc.cgs b/sim/testsuite/sim/arm/thumb/adc.cgs new file mode 100644 index 0000000..58d74c1 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/adc.cgs @@ -0,0 +1,12 @@ +# arm testcase for adc $rd,$rs +# mach: unfinished + + .include "testutils.inc" + + start + + .global alu_adc +alu_adc: + adc r0,r0 + + pass diff --git a/sim/testsuite/sim/arm/thumb/add-hd-hs.cgs b/sim/testsuite/sim/arm/thumb/add-hd-hs.cgs new file mode 100644 index 0000000..0307acc --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/add-hd-hs.cgs @@ -0,0 +1,12 @@ +# arm testcase for add $hd,$hs +# mach: unfinished + + .include "testutils.inc" + + start + + .global add_hd_hs +add_hd_hs: + add r8,r8 + + pass diff --git a/sim/testsuite/sim/arm/thumb/add-hd-rs.cgs b/sim/testsuite/sim/arm/thumb/add-hd-rs.cgs new file mode 100644 index 0000000..ca080f7 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/add-hd-rs.cgs @@ -0,0 +1,12 @@ +# arm testcase for add $hd,$rs +# mach: unfinished + + .include "testutils.inc" + + start + + .global add_hd_rs +add_hd_rs: + add r8,r0 + + pass diff --git a/sim/testsuite/sim/arm/thumb/add-rd-hs.cgs b/sim/testsuite/sim/arm/thumb/add-rd-hs.cgs new file mode 100644 index 0000000..46373a0 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/add-rd-hs.cgs @@ -0,0 +1,12 @@ +# arm testcase for add $rd,$hs +# mach: unfinished + + .include "testutils.inc" + + start + + .global add_rd_hs +add_rd_hs: + add r0,r8 + + pass diff --git a/sim/testsuite/sim/arm/thumb/add-sp.cgs b/sim/testsuite/sim/arm/thumb/add-sp.cgs new file mode 100644 index 0000000..54efa2a --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/add-sp.cgs @@ -0,0 +1,12 @@ +# arm testcase for add sp,#$sword7 +# mach: unfinished + + .include "testutils.inc" + + start + + .global add_sp +add_sp: + add sp,#0 + + pass diff --git a/sim/testsuite/sim/arm/thumb/add.cgs b/sim/testsuite/sim/arm/thumb/add.cgs new file mode 100644 index 0000000..63cc20c --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/add.cgs @@ -0,0 +1,12 @@ +# arm testcase for add $rd,$rs,$rn +# mach: unfinished + + .include "testutils.inc" + + start + + .global add +add: + add r0,r0,r0 + + pass diff --git a/sim/testsuite/sim/arm/thumb/addi.cgs b/sim/testsuite/sim/arm/thumb/addi.cgs new file mode 100644 index 0000000..00ec76d --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/addi.cgs @@ -0,0 +1,12 @@ +# arm testcase for add $rd,$rs,#$offset3 +# mach: unfinished + + .include "testutils.inc" + + start + + .global addi +addi: + add r0,r0,#0 + + pass diff --git a/sim/testsuite/sim/arm/thumb/addi8.cgs b/sim/testsuite/sim/arm/thumb/addi8.cgs new file mode 100644 index 0000000..d8e9f81 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/addi8.cgs @@ -0,0 +1,12 @@ +# arm testcase for add ${bit10-rd},#$offset8 +# mach: unfinished + + .include "testutils.inc" + + start + + .global addi8 +addi8: + add r0,#0 + + pass diff --git a/sim/testsuite/sim/arm/thumb/allthumb.exp b/sim/testsuite/sim/arm/thumb/allthumb.exp new file mode 100644 index 0000000..9674bca --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/allthumb.exp @@ -0,0 +1,21 @@ +# ARM simulator testsuite. + +if { [istarget arm*-*-*] + || [istarget thumb*-*-*] } { + # load support procs (none yet) + # load_lib cgen.exp + + # all machines + set all_machs "arm7tdmi" + + # The .cgs suffix is for "cgen .s". + foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.cgs]] { + # If we're only testing specific files and this isn't one of them, + # skip it. + if ![runtest_file_p $runtests $src] { + continue + } + + run_sim_test $src $all_machs + } +} diff --git a/sim/testsuite/sim/arm/thumb/and.cgs b/sim/testsuite/sim/arm/thumb/and.cgs new file mode 100644 index 0000000..d67adf4 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/and.cgs @@ -0,0 +1,12 @@ +# arm testcase for and $rd,$rs +# mach: unfinished + + .include "testutils.inc" + + start + + .global alu_and +alu_and: + and r0,r0 + + pass diff --git a/sim/testsuite/sim/arm/thumb/asr.cgs b/sim/testsuite/sim/arm/thumb/asr.cgs new file mode 100644 index 0000000..4d21dae --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/asr.cgs @@ -0,0 +1,14 @@ +# arm testcase for asr $rd,$rs +# mach: unfinished + + .include "testutils.inc" + + start + + .global alu_asr +alu_asr: + asr r0,r0 + +# FIXME: Also asr $rd,$rs,#$offset5 + + pass diff --git a/sim/testsuite/sim/arm/thumb/b.cgs b/sim/testsuite/sim/arm/thumb/b.cgs new file mode 100644 index 0000000..ecae537 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/b.cgs @@ -0,0 +1,12 @@ +# arm testcase for b $offset11 +# mach: unfinished + + .include "testutils.inc" + + start + + .global b +b: + b footext + + pass diff --git a/sim/testsuite/sim/arm/thumb/bcc.cgs b/sim/testsuite/sim/arm/thumb/bcc.cgs new file mode 100644 index 0000000..6c84458 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/bcc.cgs @@ -0,0 +1,12 @@ +# arm testcase for bcc $soffset8 +# mach: unfinished + + .include "testutils.inc" + + start + + .global bcc +bcc: + bcc footext + + pass diff --git a/sim/testsuite/sim/arm/thumb/bcs.cgs b/sim/testsuite/sim/arm/thumb/bcs.cgs new file mode 100644 index 0000000..a29a8fb --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/bcs.cgs @@ -0,0 +1,12 @@ +# arm testcase for bcs $soffset8 +# mach: unfinished + + .include "testutils.inc" + + start + + .global bcs +bcs: + bcs footext + + pass diff --git a/sim/testsuite/sim/arm/thumb/beq.cgs b/sim/testsuite/sim/arm/thumb/beq.cgs new file mode 100644 index 0000000..33f3748 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/beq.cgs @@ -0,0 +1,12 @@ +# arm testcase for beq $soffset8 +# mach: unfinished + + .include "testutils.inc" + + start + + .global beq +beq: + beq footext + + pass diff --git a/sim/testsuite/sim/arm/thumb/bge.cgs b/sim/testsuite/sim/arm/thumb/bge.cgs new file mode 100644 index 0000000..4eb543d --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/bge.cgs @@ -0,0 +1,12 @@ +# arm testcase for bge $soffset8 +# mach: unfinished + + .include "testutils.inc" + + start + + .global bge +bge: + bge footext + + pass diff --git a/sim/testsuite/sim/arm/thumb/bgt.cgs b/sim/testsuite/sim/arm/thumb/bgt.cgs new file mode 100644 index 0000000..1ffe092 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/bgt.cgs @@ -0,0 +1,12 @@ +# arm testcase for bgt $soffset8 +# mach: unfinished + + .include "testutils.inc" + + start + + .global bgt +bgt: + bgt footext + + pass diff --git a/sim/testsuite/sim/arm/thumb/bhi.cgs b/sim/testsuite/sim/arm/thumb/bhi.cgs new file mode 100644 index 0000000..c9811c6 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/bhi.cgs @@ -0,0 +1,12 @@ +# arm testcase for bhi $soffset8 +# mach: unfinished + + .include "testutils.inc" + + start + + .global bhi +bhi: + bhi footext + + pass diff --git a/sim/testsuite/sim/arm/thumb/bic.cgs b/sim/testsuite/sim/arm/thumb/bic.cgs new file mode 100644 index 0000000..6dca1ef --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/bic.cgs @@ -0,0 +1,12 @@ +# arm testcase for bic $rd,$rs +# mach: unfinished + + .include "testutils.inc" + + start + + .global alu_bic +alu_bic: + bic r0,r0 + + pass diff --git a/sim/testsuite/sim/arm/thumb/bl-hi.cgs b/sim/testsuite/sim/arm/thumb/bl-hi.cgs new file mode 100644 index 0000000..c7400c7 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/bl-hi.cgs @@ -0,0 +1,12 @@ +# arm testcase for bl-hi ${lbwl-hi} +# mach: unfinished + + .include "testutils.inc" + + start + + .global bl_hi +bl_hi: + bl-hi 0 + + pass diff --git a/sim/testsuite/sim/arm/thumb/bl-lo.cgs b/sim/testsuite/sim/arm/thumb/bl-lo.cgs new file mode 100644 index 0000000..ed76613 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/bl-lo.cgs @@ -0,0 +1,12 @@ +# arm testcase for bl-lo ${lbwl-lo} +# mach: unfinished + + .include "testutils.inc" + + start + + .global bl_lo +bl_lo: + bl-lo 0 + + pass diff --git a/sim/testsuite/sim/arm/thumb/ble.cgs b/sim/testsuite/sim/arm/thumb/ble.cgs new file mode 100644 index 0000000..e9c5a8f --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/ble.cgs @@ -0,0 +1,12 @@ +# arm testcase for ble $soffset8 +# mach: unfinished + + .include "testutils.inc" + + start + + .global ble +ble: + ble footext + + pass diff --git a/sim/testsuite/sim/arm/thumb/bls.cgs b/sim/testsuite/sim/arm/thumb/bls.cgs new file mode 100644 index 0000000..483412b --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/bls.cgs @@ -0,0 +1,12 @@ +# arm testcase for bls $soffset8 +# mach: unfinished + + .include "testutils.inc" + + start + + .global bls +bls: + bls footext + + pass diff --git a/sim/testsuite/sim/arm/thumb/blt.cgs b/sim/testsuite/sim/arm/thumb/blt.cgs new file mode 100644 index 0000000..0fbcbe8 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/blt.cgs @@ -0,0 +1,12 @@ +# arm testcase for blt $soffset8 +# mach: unfinished + + .include "testutils.inc" + + start + + .global blt +blt: + blt footext + + pass diff --git a/sim/testsuite/sim/arm/thumb/bmi.cgs b/sim/testsuite/sim/arm/thumb/bmi.cgs new file mode 100644 index 0000000..8f7558a --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/bmi.cgs @@ -0,0 +1,12 @@ +# arm testcase for bmi $soffset8 +# mach: unfinished + + .include "testutils.inc" + + start + + .global bmi +bmi: + bmi footext + + pass diff --git a/sim/testsuite/sim/arm/thumb/bne.cgs b/sim/testsuite/sim/arm/thumb/bne.cgs new file mode 100644 index 0000000..a5ac348 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/bne.cgs @@ -0,0 +1,12 @@ +# arm testcase for bne $soffset8 +# mach: unfinished + + .include "testutils.inc" + + start + + .global bne +bne: + bne footext + + pass diff --git a/sim/testsuite/sim/arm/thumb/bpl.cgs b/sim/testsuite/sim/arm/thumb/bpl.cgs new file mode 100644 index 0000000..8f64259 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/bpl.cgs @@ -0,0 +1,12 @@ +# arm testcase for bpl $soffset8 +# mach: unfinished + + .include "testutils.inc" + + start + + .global bpl +bpl: + bpl footext + + pass diff --git a/sim/testsuite/sim/arm/thumb/bvc.cgs b/sim/testsuite/sim/arm/thumb/bvc.cgs new file mode 100644 index 0000000..bbd3af5 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/bvc.cgs @@ -0,0 +1,12 @@ +# arm testcase for bvc $soffset8 +# mach: unfinished + + .include "testutils.inc" + + start + + .global bvc +bvc: + bvc footext + + pass diff --git a/sim/testsuite/sim/arm/thumb/bvs.cgs b/sim/testsuite/sim/arm/thumb/bvs.cgs new file mode 100644 index 0000000..8c9a551 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/bvs.cgs @@ -0,0 +1,12 @@ +# arm testcase for bvs $soffset8 +# mach: unfinished + + .include "testutils.inc" + + start + + .global bvs +bvs: + bvs footext + + pass diff --git a/sim/testsuite/sim/arm/thumb/bx-hs.cgs b/sim/testsuite/sim/arm/thumb/bx-hs.cgs new file mode 100644 index 0000000..d963387 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/bx-hs.cgs @@ -0,0 +1,12 @@ +# arm testcase for bx $hs +# mach: unfinished + + .include "testutils.inc" + + start + + .global bx_hs +bx_hs: + bx r8 + + pass diff --git a/sim/testsuite/sim/arm/thumb/bx-rs.cgs b/sim/testsuite/sim/arm/thumb/bx-rs.cgs new file mode 100644 index 0000000..f6db8c8 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/bx-rs.cgs @@ -0,0 +1,12 @@ +# arm testcase for bx $rs +# mach: unfinished + + .include "testutils.inc" + + start + + .global bx_rs +bx_rs: + bx r0 + + pass diff --git a/sim/testsuite/sim/arm/thumb/cmn.cgs b/sim/testsuite/sim/arm/thumb/cmn.cgs new file mode 100644 index 0000000..96d53a1 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/cmn.cgs @@ -0,0 +1,12 @@ +# arm testcase for cmn $rd,$rs +# mach: unfinished + + .include "testutils.inc" + + start + + .global alu_cmn +alu_cmn: + cmn r0,r0 + + pass diff --git a/sim/testsuite/sim/arm/thumb/cmp-hd-hs.cgs b/sim/testsuite/sim/arm/thumb/cmp-hd-hs.cgs new file mode 100644 index 0000000..96a91a2 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/cmp-hd-hs.cgs @@ -0,0 +1,12 @@ +# arm testcase for cmp $hd,$hs +# mach: unfinished + + .include "testutils.inc" + + start + + .global cmp_hd_hs +cmp_hd_hs: + cmp r8,r8 + + pass diff --git a/sim/testsuite/sim/arm/thumb/cmp-hd-rs.cgs b/sim/testsuite/sim/arm/thumb/cmp-hd-rs.cgs new file mode 100644 index 0000000..9fc4875 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/cmp-hd-rs.cgs @@ -0,0 +1,12 @@ +# arm testcase for cmp $hd,$rs +# mach: unfinished + + .include "testutils.inc" + + start + + .global cmp_hd_rs +cmp_hd_rs: + cmp r8,r0 + + pass diff --git a/sim/testsuite/sim/arm/thumb/cmp-rd-hs.cgs b/sim/testsuite/sim/arm/thumb/cmp-rd-hs.cgs new file mode 100644 index 0000000..e3f7a4a --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/cmp-rd-hs.cgs @@ -0,0 +1,12 @@ +# arm testcase for cmp $rd,$hs +# mach: unfinished + + .include "testutils.inc" + + start + + .global cmp_rd_hs +cmp_rd_hs: + cmp r0,r8 + + pass diff --git a/sim/testsuite/sim/arm/thumb/cmp.cgs b/sim/testsuite/sim/arm/thumb/cmp.cgs new file mode 100644 index 0000000..7564099 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/cmp.cgs @@ -0,0 +1,14 @@ +# arm testcase for cmp ${bit10-rd},#$offset8 +# mach: unfinished + + .include "testutils.inc" + + start + + .global cmp +cmp: + cmp r0,#0 + +# FIXME: Also: cmp $rd,$rs + + pass diff --git a/sim/testsuite/sim/arm/thumb/eor.cgs b/sim/testsuite/sim/arm/thumb/eor.cgs new file mode 100644 index 0000000..cc6021c --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/eor.cgs @@ -0,0 +1,12 @@ +# arm testcase for eor $rd,$rs +# mach: unfinished + + .include "testutils.inc" + + start + + .global alu_eor +alu_eor: + eor r0,r0 + + pass diff --git a/sim/testsuite/sim/arm/thumb/lda-pc.cgs b/sim/testsuite/sim/arm/thumb/lda-pc.cgs new file mode 100644 index 0000000..74407e2 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/lda-pc.cgs @@ -0,0 +1,12 @@ +# arm testcase for add ${bit10-rd},pc,$word8 +# mach: unfinished + + .include "testutils.inc" + + start + + .global lda_pc +lda_pc: + add r0,pc,0 + + pass diff --git a/sim/testsuite/sim/arm/thumb/lda-sp.cgs b/sim/testsuite/sim/arm/thumb/lda-sp.cgs new file mode 100644 index 0000000..ce2b62e --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/lda-sp.cgs @@ -0,0 +1,12 @@ +# arm testcase for add ${bit10-rd},sp,$word8 +# mach: unfinished + + .include "testutils.inc" + + start + + .global lda_sp +lda_sp: + add r0,sp,0 + + pass diff --git a/sim/testsuite/sim/arm/thumb/ldmia.cgs b/sim/testsuite/sim/arm/thumb/ldmia.cgs new file mode 100644 index 0000000..550031e --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/ldmia.cgs @@ -0,0 +1,12 @@ +# arm testcase for ldmia $rb!,{$rlist} +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldmia +ldmia: + ldmia r0!,{0} + + pass diff --git a/sim/testsuite/sim/arm/thumb/ldr-imm.cgs b/sim/testsuite/sim/arm/thumb/ldr-imm.cgs new file mode 100644 index 0000000..a757f33 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/ldr-imm.cgs @@ -0,0 +1,12 @@ +# arm testcase for ldr $rd,[$rb,#${offset5-7}] +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldr_imm +ldr_imm: + ldr r0,[r0,#0] + + pass diff --git a/sim/testsuite/sim/arm/thumb/ldr-pc.cgs b/sim/testsuite/sim/arm/thumb/ldr-pc.cgs new file mode 100644 index 0000000..8227562 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/ldr-pc.cgs @@ -0,0 +1,12 @@ +# arm testcase for ldr ${bit10-rd},[pc,#$word8] +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldr_pc +ldr_pc: + ldr r0,[pc,#0] + + pass diff --git a/sim/testsuite/sim/arm/thumb/ldr-sprel.cgs b/sim/testsuite/sim/arm/thumb/ldr-sprel.cgs new file mode 100644 index 0000000..11eee26 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/ldr-sprel.cgs @@ -0,0 +1,12 @@ +# arm testcase for ldr ${bit10-rd},[sp,#$word8] +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldr_sprel +ldr_sprel: + ldr r0,[sp,#0] + + pass diff --git a/sim/testsuite/sim/arm/thumb/ldr.cgs b/sim/testsuite/sim/arm/thumb/ldr.cgs new file mode 100644 index 0000000..03af925 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/ldr.cgs @@ -0,0 +1,12 @@ +# arm testcase for ldr $rd,[$rb,$ro] +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldr +ldr: + ldr r0,[r0,r0] + + pass diff --git a/sim/testsuite/sim/arm/thumb/ldrb-imm.cgs b/sim/testsuite/sim/arm/thumb/ldrb-imm.cgs new file mode 100644 index 0000000..c1eeafe --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/ldrb-imm.cgs @@ -0,0 +1,12 @@ +# arm testcase for ldrb $rd,[$rb,#$offset5] +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrb_imm +ldrb_imm: + ldrb r0,[r0,#0] + + pass diff --git a/sim/testsuite/sim/arm/thumb/ldrb.cgs b/sim/testsuite/sim/arm/thumb/ldrb.cgs new file mode 100644 index 0000000..316a10f --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/ldrb.cgs @@ -0,0 +1,12 @@ +# arm testcase for ldrb $rd,[$rb,$ro] +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrb +ldrb: + ldrb r0,[r0,r0] + + pass diff --git a/sim/testsuite/sim/arm/thumb/ldrh-imm.cgs b/sim/testsuite/sim/arm/thumb/ldrh-imm.cgs new file mode 100644 index 0000000..81ea1e0 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/ldrh-imm.cgs @@ -0,0 +1,12 @@ +# arm testcase for ldrh $rd,[$rb,#${offset5-6}] +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrh_imm +ldrh_imm: + ldrh r0,[r0,#0] + + pass diff --git a/sim/testsuite/sim/arm/thumb/ldrh.cgs b/sim/testsuite/sim/arm/thumb/ldrh.cgs new file mode 100644 index 0000000..3ff8f4e --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/ldrh.cgs @@ -0,0 +1,12 @@ +# arm testcase for ldrh $rd,[$rb,$ro] +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrh +ldrh: + ldrh r0,[r0,r0] + + pass diff --git a/sim/testsuite/sim/arm/thumb/ldsb.cgs b/sim/testsuite/sim/arm/thumb/ldsb.cgs new file mode 100644 index 0000000..e1612c9 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/ldsb.cgs @@ -0,0 +1,12 @@ +# arm testcase for ldsb $rd,[$rb,$ro] +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldsb +ldsb: + ldsb r0,[r0,r0] + + pass diff --git a/sim/testsuite/sim/arm/thumb/ldsh.cgs b/sim/testsuite/sim/arm/thumb/ldsh.cgs new file mode 100644 index 0000000..46d49ac --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/ldsh.cgs @@ -0,0 +1,12 @@ +# arm testcase for ldsh $rd,[$rb,$ro] +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldsh +ldsh: + ldsh r0,[r0,r0] + + pass diff --git a/sim/testsuite/sim/arm/thumb/lsl.cgs b/sim/testsuite/sim/arm/thumb/lsl.cgs new file mode 100644 index 0000000..05222e7 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/lsl.cgs @@ -0,0 +1,14 @@ +# arm testcase for lsl $rd,$rs,#$offset5 +# mach: unfinished + + .include "testutils.inc" + + start + + .global lsl +lsl: + lsl r0,r0,#0 + +# FIXME: Also lsl $rd,$rs + + pass diff --git a/sim/testsuite/sim/arm/thumb/lsr.cgs b/sim/testsuite/sim/arm/thumb/lsr.cgs new file mode 100644 index 0000000..fe38fe0 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/lsr.cgs @@ -0,0 +1,14 @@ +# arm testcase for lsr $rd,$rs,#$offset5 +# mach: unfinished + + .include "testutils.inc" + + start + + .global lsr +lsr: + lsr r0,r0,#0 + +# FIXME: Also lsr $rd,$rs + + pass diff --git a/sim/testsuite/sim/arm/thumb/mov-hd-hs.cgs b/sim/testsuite/sim/arm/thumb/mov-hd-hs.cgs new file mode 100644 index 0000000..2050908 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/mov-hd-hs.cgs @@ -0,0 +1,12 @@ +# arm testcase for mov $hd,$hs +# mach: unfinished + + .include "testutils.inc" + + start + + .global mov_hd_hs +mov_hd_hs: + mov r8,r8 + + pass diff --git a/sim/testsuite/sim/arm/thumb/mov-hd-rs.cgs b/sim/testsuite/sim/arm/thumb/mov-hd-rs.cgs new file mode 100644 index 0000000..3d229c3 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/mov-hd-rs.cgs @@ -0,0 +1,12 @@ +# arm testcase for mov $hd,$rs +# mach: unfinished + + .include "testutils.inc" + + start + + .global mov_hd_rs +mov_hd_rs: + mov r8,r0 + + pass diff --git a/sim/testsuite/sim/arm/thumb/mov-rd-hs.cgs b/sim/testsuite/sim/arm/thumb/mov-rd-hs.cgs new file mode 100644 index 0000000..0661dfa --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/mov-rd-hs.cgs @@ -0,0 +1,12 @@ +# arm testcase for mov $rd,$hs +# mach: unfinished + + .include "testutils.inc" + + start + + .global mov_rd_hs +mov_rd_hs: + mov r0,r8 + + pass diff --git a/sim/testsuite/sim/arm/thumb/mov.cgs b/sim/testsuite/sim/arm/thumb/mov.cgs new file mode 100644 index 0000000..b497b0f --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/mov.cgs @@ -0,0 +1,12 @@ +# arm testcase for mov ${bit10-rd},#$offset8 +# mach: unfinished + + .include "testutils.inc" + + start + + .global mov +mov: + mov r0,#0 + + pass diff --git a/sim/testsuite/sim/arm/thumb/mul.cgs b/sim/testsuite/sim/arm/thumb/mul.cgs new file mode 100644 index 0000000..d160c56 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/mul.cgs @@ -0,0 +1,12 @@ +# arm testcase for mul $rd,$rs +# mach: unfinished + + .include "testutils.inc" + + start + + .global alu_mul +alu_mul: + mul r0,r0 + + pass diff --git a/sim/testsuite/sim/arm/thumb/mvn.cgs b/sim/testsuite/sim/arm/thumb/mvn.cgs new file mode 100644 index 0000000..606ce85 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/mvn.cgs @@ -0,0 +1,12 @@ +# arm testcase for mvn $rd,$rs +# mach: unfinished + + .include "testutils.inc" + + start + + .global alu_mvn +alu_mvn: + mvn r0,r0 + + pass diff --git a/sim/testsuite/sim/arm/thumb/neg.cgs b/sim/testsuite/sim/arm/thumb/neg.cgs new file mode 100644 index 0000000..09f0c81 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/neg.cgs @@ -0,0 +1,12 @@ +# arm testcase for neg $rd,$rs +# mach: unfinished + + .include "testutils.inc" + + start + + .global alu_neg +alu_neg: + neg r0,r0 + + pass diff --git a/sim/testsuite/sim/arm/thumb/orr.cgs b/sim/testsuite/sim/arm/thumb/orr.cgs new file mode 100644 index 0000000..de6f688 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/orr.cgs @@ -0,0 +1,12 @@ +# arm testcase for orr $rd,$rs +# mach: unfinished + + .include "testutils.inc" + + start + + .global alu_orr +alu_orr: + orr r0,r0 + + pass diff --git a/sim/testsuite/sim/arm/thumb/pop-pc.cgs b/sim/testsuite/sim/arm/thumb/pop-pc.cgs new file mode 100644 index 0000000..4579cad --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/pop-pc.cgs @@ -0,0 +1,12 @@ +# arm testcase for pop {${rlist-pc}} +# mach: unfinished + + .include "testutils.inc" + + start + + .global pop_pc +pop_pc: + pop {0} + + pass diff --git a/sim/testsuite/sim/arm/thumb/pop.cgs b/sim/testsuite/sim/arm/thumb/pop.cgs new file mode 100644 index 0000000..b156e1d --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/pop.cgs @@ -0,0 +1,12 @@ +# arm testcase for pop {$rlist} +# mach: unfinished + + .include "testutils.inc" + + start + + .global pop +pop: + pop {0} + + pass diff --git a/sim/testsuite/sim/arm/thumb/push-lr.cgs b/sim/testsuite/sim/arm/thumb/push-lr.cgs new file mode 100644 index 0000000..ee700a4 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/push-lr.cgs @@ -0,0 +1,12 @@ +# arm testcase for push {${rlist-lr}} +# mach: unfinished + + .include "testutils.inc" + + start + + .global push_lr +push_lr: + push {0} + + pass diff --git a/sim/testsuite/sim/arm/thumb/push.cgs b/sim/testsuite/sim/arm/thumb/push.cgs new file mode 100644 index 0000000..ff94ca5 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/push.cgs @@ -0,0 +1,12 @@ +# arm testcase for push {$rlist} +# mach: unfinished + + .include "testutils.inc" + + start + + .global push +push: + push {0} + + pass diff --git a/sim/testsuite/sim/arm/thumb/ror.cgs b/sim/testsuite/sim/arm/thumb/ror.cgs new file mode 100644 index 0000000..991fa66 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/ror.cgs @@ -0,0 +1,12 @@ +# arm testcase for ror $rd,$rs +# mach: unfinished + + .include "testutils.inc" + + start + + .global alu_ror +alu_ror: + ror r0,r0 + + pass diff --git a/sim/testsuite/sim/arm/thumb/sbc.cgs b/sim/testsuite/sim/arm/thumb/sbc.cgs new file mode 100644 index 0000000..078b061 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/sbc.cgs @@ -0,0 +1,12 @@ +# arm testcase for sbc $rd,$rs +# mach: unfinished + + .include "testutils.inc" + + start + + .global alu_sbc +alu_sbc: + sbc r0,r0 + + pass diff --git a/sim/testsuite/sim/arm/thumb/stmia.cgs b/sim/testsuite/sim/arm/thumb/stmia.cgs new file mode 100644 index 0000000..0e1c30c --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/stmia.cgs @@ -0,0 +1,12 @@ +# arm testcase for stmia $rb!,{$rlist} +# mach: unfinished + + .include "testutils.inc" + + start + + .global stmia +stmia: + stmia r0!,{0} + + pass diff --git a/sim/testsuite/sim/arm/thumb/str-imm.cgs b/sim/testsuite/sim/arm/thumb/str-imm.cgs new file mode 100644 index 0000000..ce75941 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/str-imm.cgs @@ -0,0 +1,12 @@ +# arm testcase for str $rd,[$rb,#${offset5-7}] +# mach: unfinished + + .include "testutils.inc" + + start + + .global str_imm +str_imm: + str r0,[r0,#0] + + pass diff --git a/sim/testsuite/sim/arm/thumb/str-sprel.cgs b/sim/testsuite/sim/arm/thumb/str-sprel.cgs new file mode 100644 index 0000000..132edfb --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/str-sprel.cgs @@ -0,0 +1,12 @@ +# arm testcase for str ${bit10-rd},[sp,#$word8] +# mach: unfinished + + .include "testutils.inc" + + start + + .global str_sprel +str_sprel: + str r0,[sp,#0] + + pass diff --git a/sim/testsuite/sim/arm/thumb/str.cgs b/sim/testsuite/sim/arm/thumb/str.cgs new file mode 100644 index 0000000..073e20b --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/str.cgs @@ -0,0 +1,12 @@ +# arm testcase for str $rd,[$rb,$ro] +# mach: unfinished + + .include "testutils.inc" + + start + + .global str +str: + str r0,[r0,r0] + + pass diff --git a/sim/testsuite/sim/arm/thumb/strb-imm.cgs b/sim/testsuite/sim/arm/thumb/strb-imm.cgs new file mode 100644 index 0000000..2b5bcf7 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/strb-imm.cgs @@ -0,0 +1,12 @@ +# arm testcase for strb $rd,[$rb,#$offset5] +# mach: unfinished + + .include "testutils.inc" + + start + + .global strb_imm +strb_imm: + strb r0,[r0,#0] + + pass diff --git a/sim/testsuite/sim/arm/thumb/strb.cgs b/sim/testsuite/sim/arm/thumb/strb.cgs new file mode 100644 index 0000000..b7cb763 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/strb.cgs @@ -0,0 +1,12 @@ +# arm testcase for strb $rd,[$rb,$ro] +# mach: unfinished + + .include "testutils.inc" + + start + + .global strb +strb: + strb r0,[r0,r0] + + pass diff --git a/sim/testsuite/sim/arm/thumb/strh-imm.cgs b/sim/testsuite/sim/arm/thumb/strh-imm.cgs new file mode 100644 index 0000000..9500288 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/strh-imm.cgs @@ -0,0 +1,12 @@ +# arm testcase for strh $rd,[$rb,#${offset5-6}] +# mach: unfinished + + .include "testutils.inc" + + start + + .global strh_imm +strh_imm: + strh r0,[r0,#0] + + pass diff --git a/sim/testsuite/sim/arm/thumb/strh.cgs b/sim/testsuite/sim/arm/thumb/strh.cgs new file mode 100644 index 0000000..13f3a0d --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/strh.cgs @@ -0,0 +1,12 @@ +# arm testcase for strh $rd,[$rb,$ro] +# mach: unfinished + + .include "testutils.inc" + + start + + .global strh +strh: + strh r0,[r0,r0] + + pass diff --git a/sim/testsuite/sim/arm/thumb/sub-sp.cgs b/sim/testsuite/sim/arm/thumb/sub-sp.cgs new file mode 100644 index 0000000..e676f58 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/sub-sp.cgs @@ -0,0 +1,12 @@ +# arm testcase for add sp,#-$sword7 +# mach: unfinished + + .include "testutils.inc" + + start + + .global sub_sp +sub_sp: + add sp,#-0 + + pass diff --git a/sim/testsuite/sim/arm/thumb/sub.cgs b/sim/testsuite/sim/arm/thumb/sub.cgs new file mode 100644 index 0000000..91cd7ab --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/sub.cgs @@ -0,0 +1,12 @@ +# arm testcase for sub $rd,$rs,$rn +# mach: unfinished + + .include "testutils.inc" + + start + + .global sub +sub: + sub r0,r0,r0 + + pass diff --git a/sim/testsuite/sim/arm/thumb/subi.cgs b/sim/testsuite/sim/arm/thumb/subi.cgs new file mode 100644 index 0000000..044efd0 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/subi.cgs @@ -0,0 +1,12 @@ +# arm testcase for sub $rd,$rs,#$offset3 +# mach: unfinished + + .include "testutils.inc" + + start + + .global subi +subi: + sub r0,r0,#0 + + pass diff --git a/sim/testsuite/sim/arm/thumb/subi8.cgs b/sim/testsuite/sim/arm/thumb/subi8.cgs new file mode 100644 index 0000000..0c4d717 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/subi8.cgs @@ -0,0 +1,12 @@ +# arm testcase for sub ${bit10-rd},#$offset8 +# mach: unfinished + + .include "testutils.inc" + + start + + .global subi8 +subi8: + sub r0,#0 + + pass diff --git a/sim/testsuite/sim/arm/thumb/swi.cgs b/sim/testsuite/sim/arm/thumb/swi.cgs new file mode 100644 index 0000000..1724c14 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/swi.cgs @@ -0,0 +1,12 @@ +# arm testcase for swi $value8 +# mach: unfinished + + .include "testutils.inc" + + start + + .global swi +swi: + swi 0 + + pass diff --git a/sim/testsuite/sim/arm/thumb/testutils.inc b/sim/testsuite/sim/arm/thumb/testutils.inc new file mode 100644 index 0000000..bdae29b --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/testutils.inc @@ -0,0 +1,91 @@ +# FIXME: wip, copied from ../testutils.inc +# r0-r3 are used as tmps, consider them call clobbered by these macros. +# This uses the angel rom monitor calls. +# ??? How do we use the \@ facility of .macros ??? +# @ is the comment char! + + .macro a_mvi_h_gr reg, val + ldr \reg,[pc] + b . + 8 + .word \val + .endm + + .macro mvaddr_h_gr reg, addr + ldr \reg,[pc] + b . + 8 + .word \val + .endm + + .macro start + .data +failmsg: + .asciz "fail\n" +passmsg: + .asciz "pass\n" + .text + +do_pass: + ldr r1, passmsg_addr + mov r0, #4 + swi #0x123456 + exit 0 +passmsg_addr: + .word passmsg + +do_fail: + ldr r1, failmsg_addr + mov r0, #4 + swi #0x123456 + exit 1 +failmsg_addr: + .word failmsg + + .global _start +_start: + .endm + +# *** Other macros know pass/fail are 4 bytes in size! Yuck. + + .macro pass + b do_pass + .endm + + .macro fail + b do_fail + .endm + + .macro exit rc + mov r1, #\rc + mov r0, #0x2a @ decimal 42 + swi #1 + # If that returns, punt with a sigill. + stc 0,cr0,[r0] + .endm + +# Other macros know this only clobbers r0. + .macro test_h_gr reg, val + mvaddr_h_gr r0, \val + cmp \reg, r0 + beq . + 8 + fail + .endm + + .macro mvi_h_cc c, n, v, z + ldi8 r0, 0 + ldi8 r1, 1 + .if xxx + cmp r0, r1 + .else + cmp r1, r0 + .endif + .endm + + .macro test_h_cc c, n, v, z + .if xxx + bc . + 8 + fail + .else + bnc . + 8 + fail + .endif + .endm diff --git a/sim/testsuite/sim/arm/thumb/tst.cgs b/sim/testsuite/sim/arm/thumb/tst.cgs new file mode 100644 index 0000000..068fccc --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/tst.cgs @@ -0,0 +1,12 @@ +# arm testcase for tst $rd,$rs +# mach: unfinished + + .include "testutils.inc" + + start + + .global alu_tst +alu_tst: + tst r0,r0 + + pass diff --git a/sim/testsuite/sim/arm/tst.cgs b/sim/testsuite/sim/arm/tst.cgs new file mode 100644 index 0000000..f071707 --- /dev/null +++ b/sim/testsuite/sim/arm/tst.cgs @@ -0,0 +1,36 @@ +# arm testcase for tst${cond}${set-cc?} $rn,$imm12 +# mach: unfinished + + .include "testutils.inc" + + start + + .global tst_imm +tst_imm: + tst00 pc,0 + + pass +# arm testcase for tst$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm} +# mach: unfinished + + .include "testutils.inc" + + start + + .global tst_reg_imm_shift +tst_reg_imm_shift: + tst00 pc,pc,pc,lsl 0 + + pass +# arm testcase for tst$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg} +# mach: unfinished + + .include "testutils.inc" + + start + + .global tst_reg_reg_shift +tst_reg_reg_shift: + tst00 pc,pc,pc,lsl pc + + pass diff --git a/sim/testsuite/sim/arm/umlal.cgs b/sim/testsuite/sim/arm/umlal.cgs new file mode 100644 index 0000000..1c17fb6 --- /dev/null +++ b/sim/testsuite/sim/arm/umlal.cgs @@ -0,0 +1,12 @@ +# arm testcase for umlal$cond${set-cc?} $rdlo,$rdhi,$rm,$rs +# mach: unfinished + + .include "testutils.inc" + + start + + .global umlal +umlal: + umlal00 pc,pc,pc,pc + + pass diff --git a/sim/testsuite/sim/arm/umull.cgs b/sim/testsuite/sim/arm/umull.cgs new file mode 100644 index 0000000..a58541c --- /dev/null +++ b/sim/testsuite/sim/arm/umull.cgs @@ -0,0 +1,12 @@ +# arm testcase for umull$cond${set-cc?} $rdlo,$rdhi,$rm,$rs +# mach: unfinished + + .include "testutils.inc" + + start + + .global umull +umull: + umull00 pc,pc,pc,pc + + pass diff --git a/sim/testsuite/sim/arm/xscale/blx.cgs b/sim/testsuite/sim/arm/xscale/blx.cgs new file mode 100644 index 0000000..854647b --- /dev/null +++ b/sim/testsuite/sim/arm/xscale/blx.cgs @@ -0,0 +1,31 @@ +# arm testcase for bl$cond $offset24 +# mach: all + + .include "testutils.inc" + + start + + .arm + blx thumb + + .thumb + .thumb_func +thumb: + nop + blx next + blx PASS + nop + nop + + .section text1, "ax" + .arm +next: + add r0, r1, r0 + bx lr + +FAIL: + fail +PASS: + pass + + diff --git a/sim/testsuite/sim/arm/xscale/mia.cgs b/sim/testsuite/sim/arm/xscale/mia.cgs new file mode 100644 index 0000000..a3f729e --- /dev/null +++ b/sim/testsuite/sim/arm/xscale/mia.cgs @@ -0,0 +1,35 @@ +# XSCALE testcase for MIA +# mach: xscale +# as: -mcpu=xscale + + .include "testutils.inc" + + start + + .global mia +mia: + # Enable access to CoProcessors 0 & 1 before + # we attempt these instructions. + + mvi_h_gr r1, 3 + mcr p15, 0, r1, cr15, cr1, 0 + + # Test Multilply Accumulate + + mvi_h_gr r0, 0x11223344 + mvi_h_gr r1, 0x55667788 + mvi_h_gr r2, 0x12345678 + mvi_h_gr r3, 0x9abcdef0 + + mar acc0, r0, r1 + + mia acc0, r2, r3 + + mra r0, r1, acc0 + + test_h_gr r0, 0x354f53c4 + test_h_gr r1, 0x4e330b5e + test_h_gr r2, 0x12345678 + test_h_gr r3, 0x9abcdef0 + + pass diff --git a/sim/testsuite/sim/arm/xscale/miaph.cgs b/sim/testsuite/sim/arm/xscale/miaph.cgs new file mode 100644 index 0000000..53fb201 --- /dev/null +++ b/sim/testsuite/sim/arm/xscale/miaph.cgs @@ -0,0 +1,35 @@ +# XSCALE testcase for MIAPH +# mach: xscale +# as: -mcpu=xscale + + .include "testutils.inc" + + start + + .global miaph +miaph: + # Enable access to CoProcessors 0 & 1 before + # we attempt these instructions. + + mvi_h_gr r1, 3 + mcr p15, 0, r1, cr15, cr1, 0 + + # Test Multilply Accumulate + + mvi_h_gr r0, 0x11223344 + mvi_h_gr r1, 0x55667788 + mvi_h_gr r2, 0x12345678 + mvi_h_gr r3, 0x9abcdef0 + + mar acc0, r0, r1 + + miaph acc0, r2, r3 + + mra r0, r1, acc0 + + test_h_gr r0, 0xfec3f9f4 + test_h_gr r1, 0x55667787 + test_h_gr r2, 0x12345678 + test_h_gr r3, 0x9abcdef0 + + pass diff --git a/sim/testsuite/sim/arm/xscale/miaxy.cgs b/sim/testsuite/sim/arm/xscale/miaxy.cgs new file mode 100644 index 0000000..624564e --- /dev/null +++ b/sim/testsuite/sim/arm/xscale/miaxy.cgs @@ -0,0 +1,89 @@ +# XSCALE testcase for MIAxy +# mach: xscale +# as: -mcpu=xscale + + .include "testutils.inc" + + start + + .global miaXY +miaXY: + # Enable access to CoProcessors 0 & 1 before + # we attempt these instructions. + + mvi_h_gr r1, 3 + mcr p15, 0, r1, cr15, cr1, 0 + + # Test Bottom Bottom Multilply Accumulate + + mvi_h_gr r0, 0x11223344 + mvi_h_gr r1, 0x55667788 + mvi_h_gr r2, 0x12345678 + mvi_h_gr r3, 0x9abcdef0 + + mar acc0, r0, r1 + + miaBB acc0, r2, r3 + + mra r0, r1, acc0 + + test_h_gr r0, 0x05f753c4 + test_h_gr r1, 0x55667788 + test_h_gr r2, 0x12345678 + test_h_gr r3, 0x9abcdef0 + + # Test Bottom Top Multilply Accumulate + + mvi_h_gr r0, 0x11223344 + mvi_h_gr r1, 0x55667788 + mvi_h_gr r2, 0x12345678 + mvi_h_gr r3, 0x9abcdef0 + + mar acc0, r0, r1 + + miaBT acc0, r2, r3 + + mra r0, r1, acc0 + + test_h_gr r0, 0xeeede364 + test_h_gr r1, 0x55667787 + test_h_gr r2, 0x12345678 + test_h_gr r3, 0x9abcdef0 + + # Test Top Bottom Multilply Accumulate + + mvi_h_gr r0, 0x11223344 + mvi_h_gr r1, 0x55667788 + mvi_h_gr r2, 0x12345678 + mvi_h_gr r3, 0x9abcdef0 + + mar acc0, r0, r1 + + miaTB acc0, r2, r3 + + mra r0, r1, acc0 + + test_h_gr r0, 0x0ec85c04 + test_h_gr r1, 0x55667788 + test_h_gr r2, 0x12345678 + test_h_gr r3, 0x9abcdef0 + + # Test Top Top Multilply Accumulate + + mvi_h_gr r0, 0x11223344 + mvi_h_gr r1, 0x55667788 + mvi_h_gr r2, 0x12345678 + mvi_h_gr r3, 0x9abcdef0 + + mar acc0, r0, r1 + + miaTT acc0, r2, r3 + + mra r0, r1, acc0 + + test_h_gr r0, 0x09eed974 + test_h_gr r1, 0x55667788 + test_h_gr r2, 0x12345678 + test_h_gr r3, 0x9abcdef0 + + pass diff --git a/sim/testsuite/sim/arm/xscale/mra.cgs b/sim/testsuite/sim/arm/xscale/mra.cgs new file mode 100644 index 0000000..be4d9df --- /dev/null +++ b/sim/testsuite/sim/arm/xscale/mra.cgs @@ -0,0 +1,30 @@ +# XScale testcase for MAR and MRA +# mach: xscale +# as: -mcpu=xscale + + .include "testutils.inc" + + start + + .global mar_mra +mar_mra: + mvi_h_gr r2,0 + mvi_h_gr r3,0 + mvi_h_gr r4,0x0000EFA0 + mvi_h_gr r5,0xA0A0A0A0 + + # Enable access to CoProcessors 0 & 1 before + # we attempt these instructions. + + mvi_h_gr r1, 3 + mcr p15, 0, r1, cr15, cr1, 0 + + mar acc0, r5, r4 + mra r2, r3, acc0 + + test_h_gr r2,0xA0A0A0A0 + test_h_gr r3,0x0000EFA0 + test_h_gr r4,0x0000EFA0 + test_h_gr r5,0xA0A0A0A0 + + pass diff --git a/sim/testsuite/sim/arm/xscale/testutils.inc b/sim/testsuite/sim/arm/xscale/testutils.inc new file mode 100644 index 0000000..ae49db8 --- /dev/null +++ b/sim/testsuite/sim/arm/xscale/testutils.inc @@ -0,0 +1,118 @@ +# r0-r3 are used as tmps, consider them call clobbered by these macros. +# This uses the angel rom monitor calls. +# ??? How do we use the \@ facility of .macros ??? +# @ is the comment char! + + .macro mvi_h_gr reg, val + ldr \reg,[pc] + b . + 8 + .word \val + .endm + + .macro mvaddr_h_gr reg, addr + ldr \reg,[pc] + b . + 8 + .word \addr + .endm + + .macro start + .data +failmsg: + .asciz "fail\n" +passmsg: + .asciz "pass\n" + .text + +do_pass: + ldr r1, passmsg_addr + mov r0, #4 + swi #0x123456 + exit 0 +passmsg_addr: + .word passmsg + +do_fail: + ldr r1, failmsg_addr + mov r0, #4 + swi #0x123456 + exit 1 +failmsg_addr: + .word failmsg + + .global _start +_start: + .endm + +# *** Other macros know pass/fail are 4 bytes in size! Yuck. + + .macro pass + b do_pass + .endm + + .macro fail + b do_fail + .endm + + .macro exit rc + # ??? This works with the ARMulator but maybe not others. + #mov r0, #\rc + #swi #1 + # This seems to be portable (though it ignores rc). + mov r0,#0x18 + mvi_h_gr r1, 0x20026 + swi #0x123456 + # If that returns, punt with a sigill. + stc 0,cr0,[r0] + .endm + +# Other macros know this only clobbers r0. +# WARNING: It also clobbers the condition codes (FIXME). + .macro test_h_gr reg, val + mvaddr_h_gr r0, \val + cmp \reg, r0 + beq . + 8 + fail + .endm + + .macro mvi_h_cnvz c, n, v, z + mov r0, #0 + .if \c + orr r0, r0, #0x20000000 + .endif + .if \n + orr r0, r0, #0x80000000 + .endif + .if \v + orr r0, r0, #0x10000000 + .endif + .if \z + orr r0, r0, #0x40000000 + .endif + mrs r1, cpsr + bic r1, r1, #0xf0000000 + orr r1, r1, r0 + msr cpsr, r1 + # ??? nops needed + .endm + +# ??? Preserve condition codes? + .macro test_h_cnvz c, n, v, z + mov r0, #0 + .if \c + orr r0, r0, #0x20000000 + .endif + .if \n + orr r0, r0, #0x80000000 + .endif + .if \v + orr r0, r0, #0x10000000 + .endif + .if \z + orr r0, r0, #0x40000000 + .endif + mrs r1, cpsr + and r1, r1, #0xf0000000 + cmp r0, r1 + beq . + 8 + fail + .endm diff --git a/sim/testsuite/sim/arm/xscale/xscale.exp b/sim/testsuite/sim/arm/xscale/xscale.exp new file mode 100644 index 0000000..3756929 --- /dev/null +++ b/sim/testsuite/sim/arm/xscale/xscale.exp @@ -0,0 +1,28 @@ +# XSCALE simulator testsuite. + +if { [istarget xscale*-*-*] } { + # load support procs (none yet) + # load_lib cgen.exp + + # all machines + set all_machs "xscale" + + if [is_remote host] { + remote_download host $srcdir/$subdir/testutils.inc + } + + # The .cgs suffix is for "cgen .s". + foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.cgs]] { + # If we're only testing specific files and this isn't one of them, + # skip it. + if ![runtest_file_p $runtests $src] { + continue + } + + run_sim_test $src $all_machs + } + + if [is_remote host] { + remote_file host delete testutils.inc + } +} diff --git a/sim/testsuite/sim/frv/add.cgs b/sim/testsuite/sim/frv/add.cgs new file mode 100644 index 0000000..54fdfd5 --- /dev/null +++ b/sim/testsuite/sim/frv/add.cgs @@ -0,0 +1,23 @@ +# frv testcase for add $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global add +add: + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + add gr7,gr8,gr8 + test_gr_immed 3,gr8 + + set_gr_limmed 0x7fff,0xffff,gr7 + set_gr_immed 1,gr8 + add gr7,gr8,gr8 + test_gr_limmed 0x8000,0x0000,gr8 + + add gr8,gr8,gr8 + test_gr_immed 0,gr8 + + pass diff --git a/sim/testsuite/sim/frv/add.pcgs b/sim/testsuite/sim/frv/add.pcgs new file mode 100644 index 0000000..cf49976 --- /dev/null +++ b/sim/testsuite/sim/frv/add.pcgs @@ -0,0 +1,25 @@ +# frv parallel testcase for add $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global add +add: + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + add.p gr7,gr8,gr8 + add gr7,gr8,gr9 + add.p gr7,gr8,gr10 + add gr7,gr8,gr11 + add.p gr7,gr8,gr12 + add gr7,gr8,gr13 + test_gr_immed 3,gr8 + test_gr_immed 3,gr9 + test_gr_immed 4,gr10 + test_gr_immed 4,gr11 + test_gr_immed 4,gr12 + test_gr_immed 4,gr13 + + pass diff --git a/sim/testsuite/sim/frv/addcc.cgs b/sim/testsuite/sim/frv/addcc.cgs new file mode 100644 index 0000000..d2e33d8 --- /dev/null +++ b/sim/testsuite/sim/frv/addcc.cgs @@ -0,0 +1,36 @@ +# frv testcase for addcc $GRi,$GRj,$GRk,$ICCi_1 +# mach: all + + .include "testutils.inc" + + start + + .global addcc +addcc: + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + addcc gr7,gr8,gr8,icc0 + test_icc 0 0 0 0 icc0 + test_gr_immed 3,gr8 + + set_gr_limmed 0x7fff,0xffff,gr7 + set_gr_immed 1,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + addcc gr7,gr8,gr8,icc0 + test_icc 1 0 1 0 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_icc 0x08,0 ; Set mask opposite of expected + addcc gr8,gr8,gr8,icc0 + test_icc 0 1 1 1 icc0 + test_gr_immed 0,gr8 + + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x08,0 ; Set mask opposite of expected + addcc gr8,gr8,gr8,icc0; test zero, carry and overflow bits + test_icc 0 1 1 1 icc0 + test_gr_immed 0,gr8 + + + pass diff --git a/sim/testsuite/sim/frv/addi.cgs b/sim/testsuite/sim/frv/addi.cgs new file mode 100644 index 0000000..3d60c5d --- /dev/null +++ b/sim/testsuite/sim/frv/addi.cgs @@ -0,0 +1,25 @@ +# frv testcase for addi $GRi,$s12,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global addi +addi: + set_gr_immed 4,gr8 + addi gr8,0,gr8 + test_gr_immed 4,gr8 + addi gr8,1,gr8 + test_gr_immed 5,gr8 + addi gr8,15,gr8 + test_gr_immed 20,gr8 + set_gr_limmed 0x7fff,0xffff,gr8 + addi gr8,1,gr8 + test_gr_limmed 0x8000,0x0000,gr8 + addi gr8,0x7ff,gr8 + test_gr_limmed 0x8000,0x07ff,gr8 + addi gr8,-2048,gr8 + test_gr_limmed 0x7fff,0xffff,gr8 + + pass diff --git a/sim/testsuite/sim/frv/addicc.cgs b/sim/testsuite/sim/frv/addicc.cgs new file mode 100644 index 0000000..6f2a197 --- /dev/null +++ b/sim/testsuite/sim/frv/addicc.cgs @@ -0,0 +1,30 @@ +# frv testcase for addicc $GRi,$s10,$GRk,$ICCi_1 +# mach: all + + .include "testutils.inc" + + start + + .global addicc +addicc: + ; Test add $u4Ri + set_gr_immed 4,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + addicc gr8,0,gr8,icc0 + test_icc 0 0 0 0 icc0 + test_gr_immed 4,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + addicc gr8,1,gr8,icc0 + test_icc 0 0 0 0 icc0 + test_gr_immed 5,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + addicc gr8,15,gr8,icc0 + test_icc 0 0 0 0 icc0 + test_gr_immed 20,gr8 + set_gr_limmed 0x7fff,0xffff,gr8 ; test neg and overflow bits + set_icc 0x05,0 ; Set mask opposite of expected + addicc gr8,1,gr8,icc0 + test_icc 1 0 1 0 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + pass diff --git a/sim/testsuite/sim/frv/addx.cgs b/sim/testsuite/sim/frv/addx.cgs new file mode 100644 index 0000000..259a694 --- /dev/null +++ b/sim/testsuite/sim/frv/addx.cgs @@ -0,0 +1,49 @@ +# frv testcase for addx $GRi,$GRj,$GRk,$ICCi_1 +# mach: all + + .include "testutils.inc" + + start + + .global addx +addx: + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + set_icc 0x0e,0 ; Make sure carry bit is off + addx gr7,gr8,gr8,icc0 + test_icc 1 1 1 0 icc0 + test_gr_immed 3,gr8 + + set_gr_limmed 0x7fff,0xffff,gr7 + set_gr_immed 1,gr8 + set_icc 0x04,0 ; Make sure carry bit is off + addx gr7,gr8,gr8,icc0 + test_icc 0 1 0 0 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_icc 0x08,0 ; Make sure carry bit is off + addx gr8,gr8,gr8,icc0 + test_icc 1 0 0 0 icc0 + test_gr_immed 0,gr8 + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + set_icc 0x0f,0 ; Make sure carry bit is on + addx gr7,gr8,gr8,icc0 + test_icc 1 1 1 1 icc0 + test_gr_immed 4,gr8 + + set_gr_limmed 0x7fff,0xffff,gr7 + set_gr_immed 0,gr8 + set_icc 0x05,0 ; Make sure carry bit is on + addx gr7,gr8,gr8,icc0 + test_icc 0 1 0 1 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0x7fff,0xffff,gr7 + set_icc 0x0b,0 ; Make sure carry bit is on + addx gr7,gr8,gr8,icc0 + test_icc 1 0 1 1 icc0 + test_gr_immed 0,gr8 + + pass diff --git a/sim/testsuite/sim/frv/addxcc.cgs b/sim/testsuite/sim/frv/addxcc.cgs new file mode 100644 index 0000000..230c047 --- /dev/null +++ b/sim/testsuite/sim/frv/addxcc.cgs @@ -0,0 +1,49 @@ +# frv testcase for addxcc $GRi,$GRj,$GRk,$ICCi_1 +# mach: all + + .include "testutils.inc" + + start + + .global addxcc +addxcc: + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + set_icc 0x0e,0 ; Make sure carry bit is off + addxcc gr7,gr8,gr8,icc0 + test_icc 0 0 0 0 icc0 + test_gr_immed 3,gr8 + + set_gr_limmed 0x7fff,0xffff,gr7 + set_gr_immed 1,gr8 + set_icc 0x04,0 ; Make sure carry bit is off + addxcc gr7,gr8,gr8,icc0 + test_icc 1 0 1 0 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_icc 0x08,0 ; Make sure carry bit is off + addxcc gr8,gr8,gr8,icc0 + test_icc 0 1 1 1 icc0 + test_gr_immed 0,gr8 + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + set_icc 0x0f,0 ; Make sure carry bit is on + addxcc gr7,gr8,gr8,icc0 + test_icc 0 0 0 0 icc0 + test_gr_immed 4,gr8 + + set_gr_limmed 0x7fff,0xffff,gr7 + set_gr_immed 0,gr8 + set_icc 0x05,0 ; Make sure carry bit is on + addxcc gr7,gr8,gr8,icc0 + test_icc 1 0 1 0 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0x7fff,0xffff,gr7 + set_icc 0x0b,0 ; Make sure carry bit is on + addxcc gr7,gr8,gr8,icc0 + test_icc 0 1 0 1 icc0 + test_gr_immed 0,gr8 + + pass diff --git a/sim/testsuite/sim/frv/addxi.cgs b/sim/testsuite/sim/frv/addxi.cgs new file mode 100644 index 0000000..c36272a --- /dev/null +++ b/sim/testsuite/sim/frv/addxi.cgs @@ -0,0 +1,46 @@ +# frv testcase for addxi $GRi,$s10,$GRk,$ICCi_1 +# mach: all + + .include "testutils.inc" + + start + + .global addxi +addxi: + set_gr_immed 2,gr8 + set_icc 0x0e,0 ; Make sure carry bit is off + addxi gr8,1,gr8,icc0 + test_icc 1 1 1 0 icc0 + test_gr_immed 3,gr8 + + set_gr_limmed 0x7fff,0xffff,gr8 + set_icc 0x04,0 ; Make sure carry bit is off + addxi gr8,1,gr8,icc0 + test_icc 0 1 0 0 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xffff,0xff00,gr8 + set_icc 0x08,0 ; Make sure carry bit is off + addxi gr8,0x100,gr8,icc0 + test_icc 1 0 0 0 icc0 + test_gr_immed 0,gr8 + + set_gr_immed 2,gr8 + set_icc 0x0f,0 ; Make sure carry bit is on + addxi gr8,1,gr8,icc0 + test_icc 1 1 1 1 icc0 + test_gr_immed 4,gr8 + + set_gr_limmed 0x7fff,0xffff,gr8 + set_icc 0x05,0 ; Make sure carry bit is on + addxi gr8,0,gr8,icc0 + test_icc 0 1 0 1 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xffff,0xfeff,gr8 + set_icc 0x0b,0 ; Make sure carry bit is on + addxi gr8,0x100,gr8,icc0 + test_icc 1 0 1 1 icc0 + test_gr_immed 0,gr8 + + pass diff --git a/sim/testsuite/sim/frv/addxicc.cgs b/sim/testsuite/sim/frv/addxicc.cgs new file mode 100644 index 0000000..831fec3 --- /dev/null +++ b/sim/testsuite/sim/frv/addxicc.cgs @@ -0,0 +1,46 @@ +# frv testcase for addxicc $GRi,$s10,$GRk,$ICCi_1 +# mach: all + + .include "testutils.inc" + + start + + .global addxicc +addxicc: + set_gr_immed 2,gr8 + set_icc 0x0e,0 ; Make sure carry bit is off + addxicc gr8,1,gr8,icc0 + test_icc 0 0 0 0 icc0 + test_gr_immed 3,gr8 + + set_gr_limmed 0x7fff,0xffff,gr8 + set_icc 0x04,0 ; Make sure carry bit is off + addxicc gr8,1,gr8,icc0 + test_icc 1 0 1 0 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xffff,0xff00,gr8 + set_icc 0x08,0 ; Make sure carry bit is off + addxicc gr8,0x100,gr8,icc0 + test_icc 0 1 0 1 icc0 + test_gr_immed 0,gr8 + + set_gr_immed 2,gr8 + set_icc 0x0f,0 ; Make sure carry bit is on + addxicc gr8,1,gr8,icc0 + test_icc 0 0 0 0 icc0 + test_gr_immed 4,gr8 + + set_gr_limmed 0x7fff,0xffff,gr8 + set_icc 0x05,0 ; Make sure carry bit is on + addxicc gr8,0,gr8,icc0 + test_icc 1 0 1 0 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xffff,0xfeff,gr8 + set_icc 0x0b,0 ; Make sure carry bit is on + addxicc gr8,0x100,gr8,icc0 + test_icc 0 1 0 1 icc0 + test_gr_immed 0,gr8 + + pass diff --git a/sim/testsuite/sim/frv/allinsn.exp b/sim/testsuite/sim/frv/allinsn.exp new file mode 100644 index 0000000..220550d --- /dev/null +++ b/sim/testsuite/sim/frv/allinsn.exp @@ -0,0 +1,19 @@ +# FRV simulator testsuite. + +if [istarget frv*-*] { + # load support procs (none yet) + # load_lib cgen.exp + # all machines + set all_machs "frv fr500 fr550 fr400" + set cpu_option -mcpu + + # The .cgs suffix is for "cgen .s". + foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.cgs]] { + # If we're only testing specific files and this isn't one of them, + # skip it. + if ![runtest_file_p $runtests $src] { + continue + } + run_sim_test $src $all_machs + } +} diff --git a/sim/testsuite/sim/frv/and.cgs b/sim/testsuite/sim/frv/and.cgs new file mode 100644 index 0000000..a1773f1 --- /dev/null +++ b/sim/testsuite/sim/frv/and.cgs @@ -0,0 +1,29 @@ +# frv testcase for and $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global and +and: + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x0b,0 ; Set mask opposite of expected + and gr7,gr8,gr8 + test_icc 1 0 1 1 icc0 + test_gr_immed 0,gr8 + + set_gr_limmed 0xffff,0x0000,gr8 + set_icc 0x04,0 ; Set mask opposite of expected + and gr7,gr8,gr8 + test_icc 0 1 0 0 icc0 + test_gr_limmed 0xaaaa,0x0000,gr8 + + set_gr_limmed 0x0000,0xffff,gr8 + set_icc 0x0d,0 ; Set mask opposite of expected + and gr7,gr8,gr8 + test_icc 1 1 0 1 icc0 + test_gr_limmed 0x0000,0xaaaa,gr8 + + pass diff --git a/sim/testsuite/sim/frv/andcc.cgs b/sim/testsuite/sim/frv/andcc.cgs new file mode 100644 index 0000000..a2a04d2 --- /dev/null +++ b/sim/testsuite/sim/frv/andcc.cgs @@ -0,0 +1,29 @@ +# frv testcase for andcc $GRi,$GRj,$GRk,$ICCi_1 +# mach: all + + .include "testutils.inc" + + start + + .global andcc +andcc: + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x0b,0 ; Set mask opposite of expected + andcc gr7,gr8,gr8,icc0 + test_icc 0 1 1 1 icc0 + test_gr_immed 0,gr8 + + set_gr_limmed 0xffff,0x0000,gr8 + set_icc 0x04,0 ; Set mask opposite of expected + andcc gr7,gr8,gr8,icc0 + test_icc 1 0 0 0 icc0 + test_gr_limmed 0xaaaa,0x0000,gr8 + + set_gr_limmed 0x0000,0xffff,gr8 + set_icc 0x0d,0 ; Set mask opposite of expected + andcc gr7,gr8,gr8,icc0 + test_icc 0 0 0 1 icc0 + test_gr_limmed 0x0000,0xaaaa,gr8 + + pass diff --git a/sim/testsuite/sim/frv/andcr.cgs b/sim/testsuite/sim/frv/andcr.cgs new file mode 100644 index 0000000..9fbbaff --- /dev/null +++ b/sim/testsuite/sim/frv/andcr.cgs @@ -0,0 +1,59 @@ +# frv testcase for andcr $CCi,$CCj,$CCk +# mach: all + + .include "testutils.inc" + + start + + .global andcr +andcr: + set_spr_immed 0x1b1b,cccr + andcr cc7,cc7,cc3 + test_spr_immed 0x1b1b,cccr + + andcr cc7,cc6,cc3 + test_spr_immed 0x1b1b,cccr + + andcr cc7,cc5,cc3 + test_spr_immed 0x1b1b,cccr + + andcr cc7,cc4,cc3 + test_spr_immed 0x1b1b,cccr + + andcr cc6,cc7,cc3 + test_spr_immed 0x1b1b,cccr + + andcr cc6,cc6,cc3 + test_spr_immed 0x1b1b,cccr + + andcr cc6,cc5,cc3 + test_spr_immed 0x1b1b,cccr + + andcr cc6,cc4,cc3 + test_spr_immed 0x1b1b,cccr + + andcr cc5,cc7,cc3 + test_spr_immed 0x1b1b,cccr + + andcr cc5,cc6,cc3 + test_spr_immed 0x1b1b,cccr + + andcr cc5,cc5,cc3 + test_spr_immed 0x1b1b,cccr + + andcr cc5,cc4,cc3 + test_spr_immed 0x1b1b,cccr + + andcr cc4,cc7,cc3 + test_spr_immed 0x1b1b,cccr + + andcr cc4,cc6,cc3 + test_spr_immed 0x1b1b,cccr + + andcr cc4,cc5,cc3 + test_spr_immed 0x1b9b,cccr + + andcr cc4,cc4,cc3 + test_spr_immed 0x1bdb,cccr + + pass diff --git a/sim/testsuite/sim/frv/andi.cgs b/sim/testsuite/sim/frv/andi.cgs new file mode 100644 index 0000000..e9fdf75 --- /dev/null +++ b/sim/testsuite/sim/frv/andi.cgs @@ -0,0 +1,26 @@ +# frv testcase for andi $GRi,$s12,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global andi +andi: + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_icc 0x0b,0 ; Set mask opposite of expected + andi gr7,0x555,gr8 + test_icc 1 0 1 1 icc0 + test_gr_immed 0,gr8 + + set_icc 0x04,0 ; Set mask opposite of expected + andi gr7,-2048,gr8 + test_icc 0 1 0 0 icc0 + test_gr_limmed 0xaaaa,0xa800,gr8 + + set_icc 0x0d,0 ; Set mask opposite of expected + andi gr7,-1,gr8 + test_icc 1 1 0 1 icc0 + test_gr_limmed 0xaaaa,0xaaaa,gr8 + + pass diff --git a/sim/testsuite/sim/frv/andicc.cgs b/sim/testsuite/sim/frv/andicc.cgs new file mode 100644 index 0000000..6508059 --- /dev/null +++ b/sim/testsuite/sim/frv/andicc.cgs @@ -0,0 +1,26 @@ +# frv testcase for andicc $GRi,$s10,$GRk,$ICCi_1 +# mach: all + + .include "testutils.inc" + + start + + .global andicc +andicc: + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_icc 0x0b,0 ; Set mask opposite of expected + andicc gr7,0x155,gr8,icc0 + test_icc 0 1 1 1 icc0 + test_gr_immed 0,gr8 + + set_icc 0x04,0 ; Set mask opposite of expected + andicc gr7,-512,gr8,icc0 + test_icc 1 0 0 0 icc0 + test_gr_limmed 0xaaaa,0xaa00,gr8 + + set_icc 0x05,0 ; Set mask opposite of expected + andicc gr7,-1,gr8,icc0 + test_icc 1 0 0 1 icc0 + test_gr_limmed 0xaaaa,0xaaaa,gr8 + + pass diff --git a/sim/testsuite/sim/frv/andncr.cgs b/sim/testsuite/sim/frv/andncr.cgs new file mode 100644 index 0000000..31fd1f7 --- /dev/null +++ b/sim/testsuite/sim/frv/andncr.cgs @@ -0,0 +1,59 @@ +# frv testcase for andncr $CCi,$CCj,$CCk +# mach: all + + .include "testutils.inc" + + start + + .global andncr +andncr: + set_spr_immed 0x1b1b,cccr + andncr cc7,cc7,cc3 + test_spr_immed 0x1b1b,cccr + + andncr cc7,cc6,cc3 + test_spr_immed 0x1b1b,cccr + + andncr cc7,cc5,cc3 + test_spr_immed 0x1b1b,cccr + + andncr cc7,cc4,cc3 + test_spr_immed 0x1b1b,cccr + + andncr cc6,cc7,cc3 + test_spr_immed 0x1b1b,cccr + + andncr cc6,cc6,cc3 + test_spr_immed 0x1b1b,cccr + + andncr cc6,cc5,cc3 + test_spr_immed 0x1b1b,cccr + + andncr cc6,cc4,cc3 + test_spr_immed 0x1b1b,cccr + + andncr cc5,cc7,cc3 + test_spr_immed 0x1b1b,cccr + + andncr cc5,cc6,cc3 + test_spr_immed 0x1b1b,cccr + + andncr cc5,cc5,cc3 + test_spr_immed 0x1b9b,cccr + + andncr cc5,cc4,cc3 + test_spr_immed 0x1bdb,cccr + + andncr cc4,cc7,cc3 + test_spr_immed 0x1b1b,cccr + + andncr cc4,cc6,cc3 + test_spr_immed 0x1b1b,cccr + + andncr cc4,cc5,cc3 + test_spr_immed 0x1b1b,cccr + + andncr cc4,cc4,cc3 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/bar.cgs b/sim/testsuite/sim/frv/bar.cgs new file mode 100644 index 0000000..df6a9ca --- /dev/null +++ b/sim/testsuite/sim/frv/bar.cgs @@ -0,0 +1,12 @@ +# frv testcase for bar +# mach: all + + .include "testutils.inc" + + start + + .global bar +bar: + bar + + pass diff --git a/sim/testsuite/sim/frv/bc.cgs b/sim/testsuite/sim/frv/bc.cgs new file mode 100644 index 0000000..a5c612c --- /dev/null +++ b/sim/testsuite/sim/frv/bc.cgs @@ -0,0 +1,61 @@ +# frv testcase for bc $ICCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global bc +bc: + set_icc 0x0 0 + bc icc0,0,bad + set_icc 0x1 1 + bc icc1,1,ok2 + fail +ok2: + set_icc 0x2 2 + bc icc2,2,bad + set_icc 0x3 3 + bc icc3,3,ok4 + fail +ok4: + set_icc 0x4 0 + bc icc0,0,bad + set_icc 0x5 1 + bc icc1,1,ok6 + fail +ok6: + set_icc 0x6 2 + bc icc2,2,bad + set_icc 0x7 3 + bc icc3,3,ok8 + fail +ok8: + set_icc 0x8 0 + bc icc0,0,bad + set_icc 0x9 1 + bc icc1,1,oka + fail +oka: + set_icc 0xa 2 + bc icc2,2,bad + set_icc 0xb 3 + bc icc3,3,okc + fail +okc: + set_icc 0xc 0 + bc icc0,0,bad + set_icc 0xd 1 + bc icc1,1,oke + fail +oke: + set_icc 0xe 2 + bc icc2,2,bad + set_icc 0xf 3 + bc icc3,3,okg + fail +okg: + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/bcclr.cgs b/sim/testsuite/sim/frv/bcclr.cgs new file mode 100644 index 0000000..248be13 --- /dev/null +++ b/sim/testsuite/sim/frv/bcclr.cgs @@ -0,0 +1,293 @@ +# frv testcase for bcclr $ICCi,$ccond,$hint +# mach: all + + .include "testutils.inc" + + start + + .global bcclr +bcclr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcclr icc0,0,0 + + set_spr_addr ok2,lr + set_icc 0x1 1 + bcclr icc1,0,1 + fail +ok2: + set_spr_addr bad,lr + set_icc 0x2 2 + bcclr icc2,0,2 + + set_spr_addr ok4,lr + set_icc 0x3 3 + bcclr icc3,0,3 + fail +ok4: + set_spr_addr bad,lr + set_icc 0x4 0 + bcclr icc0,0,0 + + set_spr_addr ok6,lr + set_icc 0x5 1 + bcclr icc1,0,1 + fail +ok6: + set_spr_addr bad,lr + set_icc 0x6 2 + bcclr icc2,0,2 + + set_spr_addr ok8,lr + set_icc 0x7 3 + bcclr icc3,0,3 + fail +ok8: + set_spr_addr bad,lr + set_icc 0x8 0 + bcclr icc0,0,0 + + set_spr_addr oka,lr + set_icc 0x9 1 + bcclr icc1,0,1 + fail +oka: + set_spr_addr bad,lr + set_icc 0xa 2 + bcclr icc2,0,2 + + set_spr_addr okc,lr + set_icc 0xb 3 + bcclr icc3,0,3 + fail +okc: + set_spr_addr bad,lr + set_icc 0xc 0 + bcclr icc0,0,0 + + set_spr_addr oke,lr + set_icc 0xd 1 + bcclr icc1,0,1 + fail +oke: + set_spr_addr bad,lr + set_icc 0xe 2 + bcclr icc2,0,2 + + set_spr_addr okg,lr + set_icc 0xf 3 + bcclr icc3,0,3 + fail +okg: + + ; ccond is true + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcclr icc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr oki,lr + set_icc 0x1 1 + bcclr icc1,1,1 + fail +oki: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x2 2 + bcclr icc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr okk,lr + set_icc 0x3 3 + bcclr icc3,1,3 + fail +okk: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x4 0 + bcclr icc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr okm,lr + set_icc 0x5 1 + bcclr icc1,1,1 + fail +okm: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x6 2 + bcclr icc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr oko,lr + set_icc 0x7 3 + bcclr icc3,1,3 + fail +oko: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x8 0 + bcclr icc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr okq,lr + set_icc 0x9 1 + bcclr icc1,1,1 + fail +okq: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xa 2 + bcclr icc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr oks,lr + set_icc 0xb 3 + bcclr icc3,1,3 + fail +oks: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xc 0 + bcclr icc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr oku,lr + set_icc 0xd 1 + bcclr icc1,1,1 + fail +oku: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xe 2 + bcclr icc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr okw,lr + set_icc 0xf 3 + bcclr icc3,1,3 + fail +okw: + ; ccond is false + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcclr icc0,1,0 + + set_icc 0x1 1 + bcclr icc1,1,1 + + set_icc 0x2 2 + bcclr icc2,1,2 + + set_icc 0x3 3 + bcclr icc3,1,3 + + set_icc 0x4 0 + bcclr icc0,1,0 + + set_icc 0x5 1 + bcclr icc1,1,1 + + set_icc 0x6 2 + bcclr icc2,1,2 + + set_icc 0x7 3 + bcclr icc3,1,3 + + set_icc 0x8 0 + bcclr icc0,1,0 + + set_icc 0x9 1 + bcclr icc1,1,1 + + set_icc 0xa 2 + bcclr icc2,1,2 + + set_icc 0xb 3 + bcclr icc3,1,3 + + set_icc 0xc 0 + bcclr icc0,1,0 + + set_icc 0xd 1 + bcclr icc1,1,1 + + set_icc 0xe 2 + bcclr icc2,1,2 + + set_icc 0xf 3 + bcclr icc3,1,3 + + ; ccond is false + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcclr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x1 1 + bcclr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0x2 2 + bcclr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0x3 3 + bcclr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0x4 0 + bcclr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x5 1 + bcclr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0x6 2 + bcclr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0x7 3 + bcclr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0x8 0 + bcclr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x9 1 + bcclr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0xa 2 + bcclr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0xb 3 + bcclr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0xc 0 + bcclr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0xd 1 + bcclr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0xe 2 + bcclr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0xf 3 + bcclr icc3,0,3 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/bceqlr.cgs b/sim/testsuite/sim/frv/bceqlr.cgs new file mode 100644 index 0000000..bacabf4 --- /dev/null +++ b/sim/testsuite/sim/frv/bceqlr.cgs @@ -0,0 +1,293 @@ +# frv testcase for bceqlr $ICCi,$ccond,$hint +# mach: all + + .include "testutils.inc" + + start + + .global bceqlr +bceqlr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bceqlr icc0,0,0 + + set_spr_addr bad,lr + set_icc 0x1 1 + bceqlr icc1,0,1 + + set_spr_addr bad,lr + set_icc 0x2 2 + bceqlr icc2,0,2 + + set_spr_addr bad,lr + set_icc 0x3 3 + bceqlr icc3,0,3 + + set_spr_addr ok5,lr + set_icc 0x4 0 + bceqlr icc0,0,0 + fail +ok5: + set_spr_addr ok6,lr + set_icc 0x5 1 + bceqlr icc1,0,1 + fail +ok6: + set_spr_addr ok7,lr + set_icc 0x6 2 + bceqlr icc2,0,2 + fail +ok7: + set_spr_addr ok8,lr + set_icc 0x7 3 + bceqlr icc3,0,3 + fail +ok8: + set_spr_addr bad,lr + set_icc 0x8 0 + bceqlr icc0,0,0 + + set_spr_addr bad,lr + set_icc 0x9 1 + bceqlr icc1,0,1 + + set_spr_addr bad,lr + set_icc 0xa 2 + bceqlr icc2,0,2 + + set_spr_addr bad,lr + set_icc 0xb 3 + bceqlr icc3,0,3 + + set_spr_addr okd,lr + set_icc 0xc 0 + bceqlr icc0,0,0 + fail +okd: + set_spr_addr oke,lr + set_icc 0xd 1 + bceqlr icc1,0,1 + fail +oke: + set_spr_addr okf,lr + set_icc 0xe 2 + bceqlr icc2,0,2 + fail +okf: + set_spr_addr okg,lr + set_icc 0xf 3 + bceqlr icc3,0,3 + fail +okg: + + ; ccond is true + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bceqlr icc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x1 1 + bceqlr icc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x2 2 + bceqlr icc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x3 3 + bceqlr icc3,1,3 + + set_spr_immed 1,lcr + set_spr_addr okl,lr + set_icc 0x4 0 + bceqlr icc0,1,0 + fail +okl: + set_spr_immed 1,lcr + set_spr_addr okm,lr + set_icc 0x5 1 + bceqlr icc1,1,1 + fail +okm: + set_spr_immed 1,lcr + set_spr_addr okn,lr + set_icc 0x6 2 + bceqlr icc2,1,2 + fail +okn: + set_spr_immed 1,lcr + set_spr_addr oko,lr + set_icc 0x7 3 + bceqlr icc3,1,3 + fail +oko: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x8 0 + bceqlr icc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x9 1 + bceqlr icc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xa 2 + bceqlr icc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xb 3 + bceqlr icc3,1,3 + + set_spr_immed 1,lcr + set_spr_addr okt,lr + set_icc 0xc 0 + bceqlr icc0,1,0 + fail +okt: + set_spr_immed 1,lcr + set_spr_addr oku,lr + set_icc 0xd 1 + bceqlr icc1,1,1 + fail +oku: + set_spr_immed 1,lcr + set_spr_addr okv,lr + set_icc 0xe 2 + bceqlr icc2,1,2 + fail +okv: + set_spr_immed 1,lcr + set_spr_addr okw,lr + set_icc 0xf 3 + bceqlr icc3,1,3 + fail +okw: + ; ccond is false + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bceqlr icc0,1,0 + + set_icc 0x1 1 + bceqlr icc1,1,1 + + set_icc 0x2 2 + bceqlr icc2,1,2 + + set_icc 0x3 3 + bceqlr icc3,1,3 + + set_icc 0x4 0 + bceqlr icc0,1,0 + + set_icc 0x5 1 + bceqlr icc1,1,1 + + set_icc 0x6 2 + bceqlr icc2,1,2 + + set_icc 0x7 3 + bceqlr icc3,1,3 + + set_icc 0x8 0 + bceqlr icc0,1,0 + + set_icc 0x9 1 + bceqlr icc1,1,1 + + set_icc 0xa 2 + bceqlr icc2,1,2 + + set_icc 0xb 3 + bceqlr icc3,1,3 + + set_icc 0xc 0 + bceqlr icc0,1,0 + + set_icc 0xd 1 + bceqlr icc1,1,1 + + set_icc 0xe 2 + bceqlr icc2,1,2 + + set_icc 0xf 3 + bceqlr icc3,1,3 + + ; ccond is false + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bceqlr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x1 1 + bceqlr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0x2 2 + bceqlr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0x3 3 + bceqlr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0x4 0 + bceqlr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x5 1 + bceqlr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0x6 2 + bceqlr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0x7 3 + bceqlr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0x8 0 + bceqlr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x9 1 + bceqlr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0xa 2 + bceqlr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0xb 3 + bceqlr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0xc 0 + bceqlr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0xd 1 + bceqlr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0xe 2 + bceqlr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0xf 3 + bceqlr icc3,0,3 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/bcgelr.cgs b/sim/testsuite/sim/frv/bcgelr.cgs new file mode 100644 index 0000000..72bd374 --- /dev/null +++ b/sim/testsuite/sim/frv/bcgelr.cgs @@ -0,0 +1,293 @@ +# frv testcase for bcgelr $ICCi,$ccond,$hint +# mach: all + + .include "testutils.inc" + + start + + .global bcgelr +bcgelr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr ok1,lr + set_icc 0x0 0 + bcgelr icc0,0,0 + fail +ok1: + set_spr_addr ok2,lr + set_icc 0x1 1 + bcgelr icc1,0,1 + fail +ok2: + set_spr_addr bad,lr + set_icc 0x2 2 + bcgelr icc2,0,2 + + set_spr_addr bad,lr + set_icc 0x3 3 + bcgelr icc3,0,3 + + set_spr_addr ok5,lr + set_icc 0x4 0 + bcgelr icc0,0,0 + fail +ok5: + set_spr_addr ok6,lr + set_icc 0x5 1 + bcgelr icc1,0,1 + fail +ok6: + set_spr_addr bad,lr + set_icc 0x6 2 + bcgelr icc2,0,2 + + set_spr_addr bad,lr + set_icc 0x7 3 + bcgelr icc3,0,3 + + set_spr_addr bad,lr + set_icc 0x8 0 + bcgelr icc0,0,0 + + set_spr_addr bad,lr + set_icc 0x9 1 + bcgelr icc1,0,1 + + set_spr_addr okb,lr + set_icc 0xa 2 + bcgelr icc2,0,2 + fail +okb: + set_spr_addr okc,lr + set_icc 0xb 3 + bcgelr icc3,0,3 + fail +okc: + set_spr_addr bad,lr + set_icc 0xc 0 + bcgelr icc0,0,0 + + set_spr_addr bad,lr + set_icc 0xd 1 + bcgelr icc1,0,1 + + set_spr_addr okf,lr + set_icc 0xe 2 + bcgelr icc2,0,2 + fail +okf: + set_spr_addr okg,lr + set_icc 0xf 3 + bcgelr icc3,0,3 + fail +okg: + + ; ccond is true + set_spr_immed 1,lcr + set_spr_addr okh,lr + set_icc 0x0 0 + bcgelr icc0,1,0 + fail +okh: + set_spr_immed 1,lcr + set_spr_addr oki,lr + set_icc 0x1 1 + bcgelr icc1,1,1 + fail +oki: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x2 2 + bcgelr icc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x3 3 + bcgelr icc3,1,3 + + set_spr_immed 1,lcr + set_spr_addr okl,lr + set_icc 0x4 0 + bcgelr icc0,1,0 + fail +okl: + set_spr_immed 1,lcr + set_spr_addr okm,lr + set_icc 0x5 1 + bcgelr icc1,1,1 + fail +okm: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x6 2 + bcgelr icc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x7 3 + bcgelr icc3,1,3 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x8 0 + bcgelr icc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x9 1 + bcgelr icc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr okr,lr + set_icc 0xa 2 + bcgelr icc2,1,2 + fail +okr: + set_spr_immed 1,lcr + set_spr_addr oks,lr + set_icc 0xb 3 + bcgelr icc3,1,3 + fail +oks: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xc 0 + bcgelr icc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xd 1 + bcgelr icc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr okv,lr + set_icc 0xe 2 + bcgelr icc2,1,2 + fail +okv: + set_spr_immed 1,lcr + set_spr_addr okw,lr + set_icc 0xf 3 + bcgelr icc3,1,3 + fail +okw: + ; ccond is false + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcgelr icc0,1,0 + + set_icc 0x1 1 + bcgelr icc1,1,1 + + set_icc 0x2 2 + bcgelr icc2,1,2 + + set_icc 0x3 3 + bcgelr icc3,1,3 + + set_icc 0x4 0 + bcgelr icc0,1,0 + + set_icc 0x5 1 + bcgelr icc1,1,1 + + set_icc 0x6 2 + bcgelr icc2,1,2 + + set_icc 0x7 3 + bcgelr icc3,1,3 + + set_icc 0x8 0 + bcgelr icc0,1,0 + + set_icc 0x9 1 + bcgelr icc1,1,1 + + set_icc 0xa 2 + bcgelr icc2,1,2 + + set_icc 0xb 3 + bcgelr icc3,1,3 + + set_icc 0xc 0 + bcgelr icc0,1,0 + + set_icc 0xd 1 + bcgelr icc1,1,1 + + set_icc 0xe 2 + bcgelr icc2,1,2 + + set_icc 0xf 3 + bcgelr icc3,1,3 + + ; ccond is false + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcgelr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x1 1 + bcgelr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0x2 2 + bcgelr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0x3 3 + bcgelr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0x4 0 + bcgelr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x5 1 + bcgelr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0x6 2 + bcgelr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0x7 3 + bcgelr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0x8 0 + bcgelr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x9 1 + bcgelr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0xa 2 + bcgelr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0xb 3 + bcgelr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0xc 0 + bcgelr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0xd 1 + bcgelr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0xe 2 + bcgelr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0xf 3 + bcgelr icc3,0,3 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/bcgtlr.cgs b/sim/testsuite/sim/frv/bcgtlr.cgs new file mode 100644 index 0000000..edffed8 --- /dev/null +++ b/sim/testsuite/sim/frv/bcgtlr.cgs @@ -0,0 +1,284 @@ +# frv testcase for bcgtlr $ICCi,$ccond,$hint +# mach: all + + .include "testutils.inc" + + start + + .global bcgtlr +bcgtlr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr ok1,lr + set_icc 0x0 0 + bcgtlr icc0,0,0 + fail +ok1: + set_spr_addr ok2,lr + set_icc 0x1 1 + bcgtlr icc1,0,1 + fail +ok2: + set_spr_addr bad,lr + set_icc 0x2 2 + bcgtlr icc2,0,2 + + set_spr_addr bad,lr + set_icc 0x3 3 + bcgtlr icc3,0,3 + + set_spr_addr bad,lr + set_icc 0x4 0 + bcgtlr icc0,0,0 + + set_spr_addr bad,lr + set_icc 0x5 1 + bcgtlr icc1,0,1 + + set_spr_addr bad,lr + set_icc 0x6 2 + bcgtlr icc2,0,2 + + set_spr_addr bad,lr + set_icc 0x7 3 + bcgtlr icc3,0,3 + + set_spr_addr bad,lr + set_icc 0x8 0 + bcgtlr icc0,0,0 + + set_spr_addr bad,lr + set_icc 0x9 1 + bcgtlr icc1,0,1 + + set_spr_addr okb,lr + set_icc 0xa 2 + bcgtlr icc2,0,2 + fail +okb: + set_spr_addr okc,lr + set_icc 0xb 3 + bcgtlr icc3,0,3 + fail +okc: + set_spr_addr bad,lr + set_icc 0xc 0 + bcgtlr icc0,0,0 + + set_spr_addr bad,lr + set_icc 0xd 1 + bcgtlr icc1,0,1 + + set_spr_addr bad,lr + set_icc 0xe 2 + bcgtlr icc2,0,2 + + set_spr_addr bad,lr + set_icc 0xf 3 + bcgtlr icc3,0,3 + + ; ccond is true + set_spr_immed 1,lcr + set_spr_addr okh,lr + set_icc 0x0 0 + bcgtlr icc0,1,0 + fail +okh: + set_spr_immed 1,lcr + set_spr_addr oki,lr + set_icc 0x1 1 + bcgtlr icc1,1,1 + fail +oki: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x2 2 + bcgtlr icc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x3 3 + bcgtlr icc3,1,3 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x4 0 + bcgtlr icc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x5 1 + bcgtlr icc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x6 2 + bcgtlr icc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x7 3 + bcgtlr icc3,1,3 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x8 0 + bcgtlr icc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x9 1 + bcgtlr icc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr okr,lr + set_icc 0xa 2 + bcgtlr icc2,1,2 + fail +okr: + set_spr_immed 1,lcr + set_spr_addr oks,lr + set_icc 0xb 3 + bcgtlr icc3,1,3 + fail +oks: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xc 0 + bcgtlr icc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xd 1 + bcgtlr icc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xe 2 + bcgtlr icc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xf 3 + bcgtlr icc3,1,3 + + ; ccond is false + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcgtlr icc0,1,0 + + set_icc 0x1 1 + bcgtlr icc1,1,1 + + set_icc 0x2 2 + bcgtlr icc2,1,2 + + set_icc 0x3 3 + bcgtlr icc3,1,3 + + set_icc 0x4 0 + bcgtlr icc0,1,0 + + set_icc 0x5 1 + bcgtlr icc1,1,1 + + set_icc 0x6 2 + bcgtlr icc2,1,2 + + set_icc 0x7 3 + bcgtlr icc3,1,3 + + set_icc 0x8 0 + bcgtlr icc0,1,0 + + set_icc 0x9 1 + bcgtlr icc1,1,1 + + set_icc 0xa 2 + bcgtlr icc2,1,2 + + set_icc 0xb 3 + bcgtlr icc3,1,3 + + set_icc 0xc 0 + bcgtlr icc0,1,0 + + set_icc 0xd 1 + bcgtlr icc1,1,1 + + set_icc 0xe 2 + bcgtlr icc2,1,2 + + set_icc 0xf 3 + bcgtlr icc3,1,3 + + ; ccond is false + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcgtlr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x1 1 + bcgtlr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0x2 2 + bcgtlr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0x3 3 + bcgtlr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0x4 0 + bcgtlr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x5 1 + bcgtlr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0x6 2 + bcgtlr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0x7 3 + bcgtlr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0x8 0 + bcgtlr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x9 1 + bcgtlr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0xa 2 + bcgtlr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0xb 3 + bcgtlr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0xc 0 + bcgtlr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0xd 1 + bcgtlr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0xe 2 + bcgtlr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0xf 3 + bcgtlr icc3,0,3 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/bchilr.cgs b/sim/testsuite/sim/frv/bchilr.cgs new file mode 100644 index 0000000..ea7e2f4 --- /dev/null +++ b/sim/testsuite/sim/frv/bchilr.cgs @@ -0,0 +1,284 @@ +# frv testcase for bchilr $ICCi,$ccond,$hint +# mach: all + + .include "testutils.inc" + + start + + .global bchilr +bchilr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr ok1,lr + set_icc 0x0 0 + bchilr icc0,0,0 + fail +ok1: + set_spr_addr bad,lr + set_icc 0x1 1 + bchilr icc1,0,1 + + set_spr_addr ok3,lr + set_icc 0x2 2 + bchilr icc2,0,2 + fail +ok3: + set_spr_addr bad,lr + set_icc 0x3 3 + bchilr icc3,0,3 + + set_spr_addr bad,lr + set_icc 0x4 0 + bchilr icc0,0,0 + + set_spr_addr bad,lr + set_icc 0x5 1 + bchilr icc1,0,1 + + set_spr_addr bad,lr + set_icc 0x6 2 + bchilr icc2,0,2 + + set_spr_addr bad,lr + set_icc 0x7 3 + bchilr icc3,0,3 + + set_spr_addr ok9,lr + set_icc 0x8 0 + bchilr icc0,0,0 + fail +ok9: + set_spr_addr bad,lr + set_icc 0x9 1 + bchilr icc1,0,1 + + set_spr_addr okb,lr + set_icc 0xa 2 + bchilr icc2,0,2 + fail +okb: + set_spr_addr bad,lr + set_icc 0xb 3 + bchilr icc3,0,3 + + set_spr_addr bad,lr + set_icc 0xc 0 + bchilr icc0,0,0 + + set_spr_addr bad,lr + set_icc 0xd 1 + bchilr icc1,0,1 + + set_spr_addr bad,lr + set_icc 0xe 2 + bchilr icc2,0,2 + + set_spr_addr bad,lr + set_icc 0xf 3 + bchilr icc3,0,3 + + ; ccond is true + set_spr_immed 1,lcr + set_spr_addr okh,lr + set_icc 0x0 0 + bchilr icc0,1,0 + fail +okh: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x1 1 + bchilr icc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr okj,lr + set_icc 0x2 2 + bchilr icc2,1,2 + fail +okj: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x3 3 + bchilr icc3,1,3 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x4 0 + bchilr icc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x5 1 + bchilr icc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x6 2 + bchilr icc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x7 3 + bchilr icc3,1,3 + + set_spr_immed 1,lcr + set_spr_addr okp,lr + set_icc 0x8 0 + bchilr icc0,1,0 + fail +okp: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x9 1 + bchilr icc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr okr,lr + set_icc 0xa 2 + bchilr icc2,1,2 + fail +okr: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xb 3 + bchilr icc3,1,3 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xc 0 + bchilr icc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xd 1 + bchilr icc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xe 2 + bchilr icc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xf 3 + bchilr icc3,1,3 + + ; ccond is false + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bchilr icc0,1,0 + + set_icc 0x1 1 + bchilr icc1,1,1 + + set_icc 0x2 2 + bchilr icc2,1,2 + + set_icc 0x3 3 + bchilr icc3,1,3 + + set_icc 0x4 0 + bchilr icc0,1,0 + + set_icc 0x5 1 + bchilr icc1,1,1 + + set_icc 0x6 2 + bchilr icc2,1,2 + + set_icc 0x7 3 + bchilr icc3,1,3 + + set_icc 0x8 0 + bchilr icc0,1,0 + + set_icc 0x9 1 + bchilr icc1,1,1 + + set_icc 0xa 2 + bchilr icc2,1,2 + + set_icc 0xb 3 + bchilr icc3,1,3 + + set_icc 0xc 0 + bchilr icc0,1,0 + + set_icc 0xd 1 + bchilr icc1,1,1 + + set_icc 0xe 2 + bchilr icc2,1,2 + + set_icc 0xf 3 + bchilr icc3,1,3 + + ; ccond is false + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bchilr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x1 1 + bchilr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0x2 2 + bchilr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0x3 3 + bchilr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0x4 0 + bchilr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x5 1 + bchilr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0x6 2 + bchilr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0x7 3 + bchilr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0x8 0 + bchilr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x9 1 + bchilr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0xa 2 + bchilr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0xb 3 + bchilr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0xc 0 + bchilr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0xd 1 + bchilr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0xe 2 + bchilr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0xf 3 + bchilr icc3,0,3 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/bclelr.cgs b/sim/testsuite/sim/frv/bclelr.cgs new file mode 100644 index 0000000..6668c77 --- /dev/null +++ b/sim/testsuite/sim/frv/bclelr.cgs @@ -0,0 +1,301 @@ +# frv testcase for bclelr $ICCi,$ccond,$hint +# mach: all + + .include "testutils.inc" + + start + + .global bclelr +bclelr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bclelr icc0,0,0 + + set_spr_addr bad,lr + set_icc 0x1 1 + bclelr icc1,0,1 + + set_spr_addr ok3,lr + set_icc 0x2 2 + bclelr icc2,0,2 + fail +ok3: + set_spr_addr ok4,lr + set_icc 0x3 3 + bclelr icc3,0,3 + fail +ok4: + set_spr_addr ok5,lr + set_icc 0x4 0 + bclelr icc0,0,0 + fail +ok5: + set_spr_addr ok6,lr + set_icc 0x5 1 + bclelr icc1,0,1 + fail +ok6: + set_spr_addr ok7,lr + set_icc 0x6 2 + bclelr icc2,0,2 + fail +ok7: + set_spr_addr ok8,lr + set_icc 0x7 3 + bclelr icc3,0,3 + fail +ok8: + set_spr_addr ok9,lr + set_icc 0x8 0 + bclelr icc0,0,0 + fail +ok9: + set_spr_addr oka,lr + set_icc 0x9 1 + bclelr icc1,0,1 + fail +oka: + set_spr_addr bad,lr + set_icc 0xa 2 + bclelr icc2,0,2 + + set_spr_addr bad,lr + set_icc 0xb 3 + bclelr icc3,0,3 + + set_spr_addr okd,lr + set_icc 0xc 0 + bclelr icc0,0,0 + fail +okd: + set_spr_addr oke,lr + set_icc 0xd 1 + bclelr icc1,0,1 + fail +oke: + set_spr_addr okf,lr + set_icc 0xe 2 + bclelr icc2,0,2 + fail +okf: + set_spr_addr okg,lr + set_icc 0xf 3 + bclelr icc3,0,3 + fail +okg: + + ; ccond is true + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bclelr icc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x1 1 + bclelr icc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr okj,lr + set_icc 0x2 2 + bclelr icc2,1,2 + fail +okj: + set_spr_immed 1,lcr + set_spr_addr okk,lr + set_icc 0x3 3 + bclelr icc3,1,3 + fail +okk: + set_spr_immed 1,lcr + set_spr_addr okl,lr + set_icc 0x4 0 + bclelr icc0,1,0 + fail +okl: + set_spr_immed 1,lcr + set_spr_addr okm,lr + set_icc 0x5 1 + bclelr icc1,1,1 + fail +okm: + set_spr_immed 1,lcr + set_spr_addr okn,lr + set_icc 0x6 2 + bclelr icc2,1,2 + fail +okn: + set_spr_immed 1,lcr + set_spr_addr oko,lr + set_icc 0x7 3 + bclelr icc3,1,3 + fail +oko: + set_spr_immed 1,lcr + set_spr_addr okp,lr + set_icc 0x8 0 + bclelr icc0,1,0 + fail +okp: + set_spr_immed 1,lcr + set_spr_addr okq,lr + set_icc 0x9 1 + bclelr icc1,1,1 + fail +okq: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xa 2 + bclelr icc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xb 3 + bclelr icc3,1,3 + + set_spr_immed 1,lcr + set_spr_addr okt,lr + set_icc 0xc 0 + bclelr icc0,1,0 + fail +okt: + set_spr_immed 1,lcr + set_spr_addr oku,lr + set_icc 0xd 1 + bclelr icc1,1,1 + fail +oku: + set_spr_immed 1,lcr + set_spr_addr okv,lr + set_icc 0xe 2 + bclelr icc2,1,2 + fail +okv: + set_spr_immed 1,lcr + set_spr_addr okw,lr + set_icc 0xf 3 + bclelr icc3,1,3 + fail +okw: + ; ccond is false + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bclelr icc0,1,0 + + set_icc 0x1 1 + bclelr icc1,1,1 + + set_icc 0x2 2 + bclelr icc2,1,2 + + set_icc 0x3 3 + bclelr icc3,1,3 + + set_icc 0x4 0 + bclelr icc0,1,0 + + set_icc 0x5 1 + bclelr icc1,1,1 + + set_icc 0x6 2 + bclelr icc2,1,2 + + set_icc 0x7 3 + bclelr icc3,1,3 + + set_icc 0x8 0 + bclelr icc0,1,0 + + set_icc 0x9 1 + bclelr icc1,1,1 + + set_icc 0xa 2 + bclelr icc2,1,2 + + set_icc 0xb 3 + bclelr icc3,1,3 + + set_icc 0xc 0 + bclelr icc0,1,0 + + set_icc 0xd 1 + bclelr icc1,1,1 + + set_icc 0xe 2 + bclelr icc2,1,2 + + set_icc 0xf 3 + bclelr icc3,1,3 + + ; ccond is false + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bclelr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x1 1 + bclelr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0x2 2 + bclelr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0x3 3 + bclelr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0x4 0 + bclelr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x5 1 + bclelr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0x6 2 + bclelr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0x7 3 + bclelr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0x8 0 + bclelr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x9 1 + bclelr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0xa 2 + bclelr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0xb 3 + bclelr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0xc 0 + bclelr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0xd 1 + bclelr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0xe 2 + bclelr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0xf 3 + bclelr icc3,0,3 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/bclr.cgs b/sim/testsuite/sim/frv/bclr.cgs new file mode 100644 index 0000000..d36563b --- /dev/null +++ b/sim/testsuite/sim/frv/bclr.cgs @@ -0,0 +1,84 @@ +# frv testcase for bclr $ICCi,$hint +# mach: all + + .include "testutils.inc" + + start + + .global bclr +bclr: + set_spr_addr bad,lr + set_icc 0x0 0 + bclr icc0,0 + + set_spr_addr ok2,lr + set_icc 0x1 1 + bclr icc1,1 + fail +ok2: + set_spr_addr bad,lr + set_icc 0x2 2 + bclr icc2,2 + + set_spr_addr ok4,lr + set_icc 0x3 3 + bclr icc3,3 + fail +ok4: + set_spr_addr bad,lr + set_icc 0x4 0 + bclr icc0,0 + + set_spr_addr ok6,lr + set_icc 0x5 1 + bclr icc1,1 + fail +ok6: + set_spr_addr bad,lr + set_icc 0x6 2 + bclr icc2,2 + + set_spr_addr ok8,lr + set_icc 0x7 3 + bclr icc3,3 + fail +ok8: + set_spr_addr bad,lr + set_icc 0x8 0 + bclr icc0,0 + + set_spr_addr oka,lr + set_icc 0x9 1 + bclr icc1,1 + fail +oka: + set_spr_addr bad,lr + set_icc 0xa 2 + bclr icc2,2 + + set_spr_addr okc,lr + set_icc 0xb 3 + bclr icc3,3 + fail +okc: + set_spr_addr bad,lr + set_icc 0xc 0 + bclr icc0,0 + + set_spr_addr oke,lr + set_icc 0xd 1 + bclr icc1,1 + fail +oke: + set_spr_addr bad,lr + set_icc 0xe 2 + bclr icc2,2 + + set_spr_addr okg,lr + set_icc 0xf 3 + bclr icc3,3 + fail +okg: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/bclslr.cgs b/sim/testsuite/sim/frv/bclslr.cgs new file mode 100644 index 0000000..37b91bc --- /dev/null +++ b/sim/testsuite/sim/frv/bclslr.cgs @@ -0,0 +1,301 @@ +# frv testcase for bclslr $ICCi,$ccond,$hint +# mach: all + + .include "testutils.inc" + + start + + .global bclslr +bclslr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bclslr icc0,0,0 + + set_spr_addr ok2,lr + set_icc 0x1 1 + bclslr icc1,0,1 + fail +ok2: + set_spr_addr bad,lr + set_icc 0x2 2 + bclslr icc2,0,2 + + set_spr_addr ok4,lr + set_icc 0x3 3 + bclslr icc3,0,3 + fail +ok4: + set_spr_addr ok5,lr + set_icc 0x4 0 + bclslr icc0,0,0 + fail +ok5: + set_spr_addr ok6,lr + set_icc 0x5 1 + bclslr icc1,0,1 + fail +ok6: + set_spr_addr ok7,lr + set_icc 0x6 2 + bclslr icc2,0,2 + fail +ok7: + set_spr_addr ok8,lr + set_icc 0x7 3 + bclslr icc3,0,3 + fail +ok8: + set_spr_addr bad,lr + set_icc 0x8 0 + bclslr icc0,0,0 + + set_spr_addr oka,lr + set_icc 0x9 1 + bclslr icc1,0,1 + fail +oka: + set_spr_addr bad,lr + set_icc 0xa 2 + bclslr icc2,0,2 + + set_spr_addr okc,lr + set_icc 0xb 3 + bclslr icc3,0,3 + fail +okc: + set_spr_addr okd,lr + set_icc 0xc 0 + bclslr icc0,0,0 + fail +okd: + set_spr_addr oke,lr + set_icc 0xd 1 + bclslr icc1,0,1 + fail +oke: + set_spr_addr okf,lr + set_icc 0xe 2 + bclslr icc2,0,2 + fail +okf: + set_spr_addr okg,lr + set_icc 0xf 3 + bclslr icc3,0,3 + fail +okg: + + ; ccond is true + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bclslr icc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr oki,lr + set_icc 0x1 1 + bclslr icc1,1,1 + fail +oki: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x2 2 + bclslr icc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr okk,lr + set_icc 0x3 3 + bclslr icc3,1,3 + fail +okk: + set_spr_immed 1,lcr + set_spr_addr okl,lr + set_icc 0x4 0 + bclslr icc0,1,0 + fail +okl: + set_spr_immed 1,lcr + set_spr_addr okm,lr + set_icc 0x5 1 + bclslr icc1,1,1 + fail +okm: + set_spr_immed 1,lcr + set_spr_addr okn,lr + set_icc 0x6 2 + bclslr icc2,1,2 + fail +okn: + set_spr_immed 1,lcr + set_spr_addr oko,lr + set_icc 0x7 3 + bclslr icc3,1,3 + fail +oko: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x8 0 + bclslr icc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr okq,lr + set_icc 0x9 1 + bclslr icc1,1,1 + fail +okq: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xa 2 + bclslr icc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr oks,lr + set_icc 0xb 3 + bclslr icc3,1,3 + fail +oks: + set_spr_immed 1,lcr + set_spr_addr okt,lr + set_icc 0xc 0 + bclslr icc0,1,0 + fail +okt: + set_spr_immed 1,lcr + set_spr_addr oku,lr + set_icc 0xd 1 + bclslr icc1,1,1 + fail +oku: + set_spr_immed 1,lcr + set_spr_addr okv,lr + set_icc 0xe 2 + bclslr icc2,1,2 + fail +okv: + set_spr_immed 1,lcr + set_spr_addr okw,lr + set_icc 0xf 3 + bclslr icc3,1,3 + fail +okw: + ; ccond is false + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bclslr icc0,1,0 + + set_icc 0x1 1 + bclslr icc1,1,1 + + set_icc 0x2 2 + bclslr icc2,1,2 + + set_icc 0x3 3 + bclslr icc3,1,3 + + set_icc 0x4 0 + bclslr icc0,1,0 + + set_icc 0x5 1 + bclslr icc1,1,1 + + set_icc 0x6 2 + bclslr icc2,1,2 + + set_icc 0x7 3 + bclslr icc3,1,3 + + set_icc 0x8 0 + bclslr icc0,1,0 + + set_icc 0x9 1 + bclslr icc1,1,1 + + set_icc 0xa 2 + bclslr icc2,1,2 + + set_icc 0xb 3 + bclslr icc3,1,3 + + set_icc 0xc 0 + bclslr icc0,1,0 + + set_icc 0xd 1 + bclslr icc1,1,1 + + set_icc 0xe 2 + bclslr icc2,1,2 + + set_icc 0xf 3 + bclslr icc3,1,3 + + ; ccond is false + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bclslr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x1 1 + bclslr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0x2 2 + bclslr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0x3 3 + bclslr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0x4 0 + bclslr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x5 1 + bclslr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0x6 2 + bclslr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0x7 3 + bclslr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0x8 0 + bclslr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x9 1 + bclslr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0xa 2 + bclslr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0xb 3 + bclslr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0xc 0 + bclslr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0xd 1 + bclslr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0xe 2 + bclslr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0xf 3 + bclslr icc3,0,3 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/bcltlr.cgs b/sim/testsuite/sim/frv/bcltlr.cgs new file mode 100644 index 0000000..0ba6bfa --- /dev/null +++ b/sim/testsuite/sim/frv/bcltlr.cgs @@ -0,0 +1,292 @@ +# frv testcase for bcltlr $ICCi,$ccond,$hint +# mach: all + + .include "testutils.inc" + + start + + .global bcltlr +bcltlr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcltlr icc0,0,0 + + set_spr_addr bad,lr + set_icc 0x1 1 + bcltlr icc1,0,1 + + set_spr_addr ok3,lr + set_icc 0x2 2 + bcltlr icc2,0,2 + fail +ok3: + set_spr_addr ok4,lr + set_icc 0x3 3 + bcltlr icc3,0,3 + fail +ok4: + set_spr_addr bad,lr + set_icc 0x4 0 + bcltlr icc0,0,0 + + set_spr_addr bad,lr + set_icc 0x5 1 + bcltlr icc1,0,1 + + set_spr_addr ok7,lr + set_icc 0x6 2 + bcltlr icc2,0,2 + fail +ok7: + set_spr_addr ok8,lr + set_icc 0x7 3 + bcltlr icc3,0,3 + fail +ok8: + set_spr_addr ok9,lr + set_icc 0x8 0 + bcltlr icc0,0,0 + fail +ok9: + set_spr_addr oka,lr + set_icc 0x9 1 + bcltlr icc1,0,1 + fail +oka: + set_spr_addr bad,lr + set_icc 0xa 2 + bcltlr icc2,0,2 + + set_spr_addr bad,lr + set_icc 0xb 3 + bcltlr icc3,0,3 + + set_spr_addr okd,lr + set_icc 0xc 0 + bcltlr icc0,0,0 + fail +okd: + set_spr_addr oke,lr + set_icc 0xd 1 + bcltlr icc1,0,1 + fail +oke: + set_spr_addr bad,lr + set_icc 0xe 2 + bcltlr icc2,0,2 + + set_spr_addr bad,lr + set_icc 0xf 3 + bcltlr icc3,0,3 + + ; ccond is true + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcltlr icc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x1 1 + bcltlr icc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr okj,lr + set_icc 0x2 2 + bcltlr icc2,1,2 + fail +okj: + set_spr_immed 1,lcr + set_spr_addr okk,lr + set_icc 0x3 3 + bcltlr icc3,1,3 + fail +okk: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x4 0 + bcltlr icc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x5 1 + bcltlr icc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr okn,lr + set_icc 0x6 2 + bcltlr icc2,1,2 + fail +okn: + set_spr_immed 1,lcr + set_spr_addr oko,lr + set_icc 0x7 3 + bcltlr icc3,1,3 + fail +oko: + set_spr_immed 1,lcr + set_spr_addr okp,lr + set_icc 0x8 0 + bcltlr icc0,1,0 + fail +okp: + set_spr_immed 1,lcr + set_spr_addr okq,lr + set_icc 0x9 1 + bcltlr icc1,1,1 + fail +okq: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xa 2 + bcltlr icc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xb 3 + bcltlr icc3,1,3 + + set_spr_immed 1,lcr + set_spr_addr okt,lr + set_icc 0xc 0 + bcltlr icc0,1,0 + fail +okt: + set_spr_immed 1,lcr + set_spr_addr oku,lr + set_icc 0xd 1 + bcltlr icc1,1,1 + fail +oku: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xe 2 + bcltlr icc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xf 3 + bcltlr icc3,1,3 + + ; ccond is false + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcltlr icc0,1,0 + + set_icc 0x1 1 + bcltlr icc1,1,1 + + set_icc 0x2 2 + bcltlr icc2,1,2 + + set_icc 0x3 3 + bcltlr icc3,1,3 + + set_icc 0x4 0 + bcltlr icc0,1,0 + + set_icc 0x5 1 + bcltlr icc1,1,1 + + set_icc 0x6 2 + bcltlr icc2,1,2 + + set_icc 0x7 3 + bcltlr icc3,1,3 + + set_icc 0x8 0 + bcltlr icc0,1,0 + + set_icc 0x9 1 + bcltlr icc1,1,1 + + set_icc 0xa 2 + bcltlr icc2,1,2 + + set_icc 0xb 3 + bcltlr icc3,1,3 + + set_icc 0xc 0 + bcltlr icc0,1,0 + + set_icc 0xd 1 + bcltlr icc1,1,1 + + set_icc 0xe 2 + bcltlr icc2,1,2 + + set_icc 0xf 3 + bcltlr icc3,1,3 + + ; ccond is false + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcltlr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x1 1 + bcltlr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0x2 2 + bcltlr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0x3 3 + bcltlr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0x4 0 + bcltlr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x5 1 + bcltlr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0x6 2 + bcltlr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0x7 3 + bcltlr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0x8 0 + bcltlr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x9 1 + bcltlr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0xa 2 + bcltlr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0xb 3 + bcltlr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0xc 0 + bcltlr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0xd 1 + bcltlr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0xe 2 + bcltlr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0xf 3 + bcltlr icc3,0,3 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/bcnclr.cgs b/sim/testsuite/sim/frv/bcnclr.cgs new file mode 100644 index 0000000..51824a6 --- /dev/null +++ b/sim/testsuite/sim/frv/bcnclr.cgs @@ -0,0 +1,293 @@ +# frv testcase for bcnclr $ICCi,$ccond,$hint +# mach: all + + .include "testutils.inc" + + start + + .global bcnclr +bcnclr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr ok1,lr + set_icc 0x0 0 + bcnclr icc0,0,0 + fail +ok1: + set_spr_addr bad,lr + set_icc 0x1 1 + bcnclr icc1,0,1 + + set_spr_addr ok3,lr + set_icc 0x2 2 + bcnclr icc2,0,2 + fail +ok3: + set_spr_addr bad,lr + set_icc 0x3 3 + bcnclr icc3,0,3 + + set_spr_addr ok5,lr + set_icc 0x4 0 + bcnclr icc0,0,0 + fail +ok5: + set_spr_addr bad,lr + set_icc 0x5 1 + bcnclr icc1,0,1 + + set_spr_addr ok7,lr + set_icc 0x6 2 + bcnclr icc2,0,2 + fail +ok7: + set_spr_addr bad,lr + set_icc 0x7 3 + bcnclr icc3,0,3 + + set_spr_addr ok9,lr + set_icc 0x8 0 + bcnclr icc0,0,0 + fail +ok9: + set_spr_addr bad,lr + set_icc 0x9 1 + bcnclr icc1,0,1 + + set_spr_addr okb,lr + set_icc 0xa 2 + bcnclr icc2,0,2 + fail +okb: + set_spr_addr bad,lr + set_icc 0xb 3 + bcnclr icc3,0,3 + + set_spr_addr okd,lr + set_icc 0xc 0 + bcnclr icc0,0,0 + fail +okd: + set_spr_addr bad,lr + set_icc 0xd 1 + bcnclr icc1,0,1 + + set_spr_addr okf,lr + set_icc 0xe 2 + bcnclr icc2,0,2 + fail +okf: + set_spr_addr bad,lr + set_icc 0xf 3 + bcnclr icc3,0,3 + + + ; ccond is true + set_spr_immed 1,lcr + set_spr_addr okh,lr + set_icc 0x0 0 + bcnclr icc0,1,0 + fail +okh: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x1 1 + bcnclr icc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr okj,lr + set_icc 0x2 2 + bcnclr icc2,1,2 + fail +okj: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x3 3 + bcnclr icc3,1,3 + + set_spr_immed 1,lcr + set_spr_addr okl,lr + set_icc 0x4 0 + bcnclr icc0,1,0 + fail +okl: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x5 1 + bcnclr icc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr okn,lr + set_icc 0x6 2 + bcnclr icc2,1,2 + fail +okn: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x7 3 + bcnclr icc3,1,3 + + set_spr_immed 1,lcr + set_spr_addr okp,lr + set_icc 0x8 0 + bcnclr icc0,1,0 + fail +okp: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x9 1 + bcnclr icc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr okr,lr + set_icc 0xa 2 + bcnclr icc2,1,2 + fail +okr: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xb 3 + bcnclr icc3,1,3 + + set_spr_immed 1,lcr + set_spr_addr okt,lr + set_icc 0xc 0 + bcnclr icc0,1,0 + fail +okt: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xd 1 + bcnclr icc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr okv,lr + set_icc 0xe 2 + bcnclr icc2,1,2 + fail +okv: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xf 3 + bcnclr icc3,1,3 + + ; ccond is false + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcnclr icc0,1,0 + + set_icc 0x1 1 + bcnclr icc1,1,1 + + set_icc 0x2 2 + bcnclr icc2,1,2 + + set_icc 0x3 3 + bcnclr icc3,1,3 + + set_icc 0x4 0 + bcnclr icc0,1,0 + + set_icc 0x5 1 + bcnclr icc1,1,1 + + set_icc 0x6 2 + bcnclr icc2,1,2 + + set_icc 0x7 3 + bcnclr icc3,1,3 + + set_icc 0x8 0 + bcnclr icc0,1,0 + + set_icc 0x9 1 + bcnclr icc1,1,1 + + set_icc 0xa 2 + bcnclr icc2,1,2 + + set_icc 0xb 3 + bcnclr icc3,1,3 + + set_icc 0xc 0 + bcnclr icc0,1,0 + + set_icc 0xd 1 + bcnclr icc1,1,1 + + set_icc 0xe 2 + bcnclr icc2,1,2 + + set_icc 0xf 3 + bcnclr icc3,1,3 + + ; ccond is false + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcnclr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x1 1 + bcnclr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0x2 2 + bcnclr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0x3 3 + bcnclr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0x4 0 + bcnclr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x5 1 + bcnclr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0x6 2 + bcnclr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0x7 3 + bcnclr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0x8 0 + bcnclr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x9 1 + bcnclr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0xa 2 + bcnclr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0xb 3 + bcnclr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0xc 0 + bcnclr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0xd 1 + bcnclr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0xe 2 + bcnclr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0xf 3 + bcnclr icc3,0,3 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/bcnelr.cgs b/sim/testsuite/sim/frv/bcnelr.cgs new file mode 100644 index 0000000..55be2d3 --- /dev/null +++ b/sim/testsuite/sim/frv/bcnelr.cgs @@ -0,0 +1,292 @@ +# frv testcase for bcnelr $ICCi,$ccond,$hint +# mach: all + + .include "testutils.inc" + + start + + .global bcnelr +bcnelr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr ok1,lr + set_icc 0x0 0 + bcnelr icc0,0,0 + fail +ok1: + set_spr_addr ok2,lr + set_icc 0x1 1 + bcnelr icc1,0,1 + fail +ok2: + set_spr_addr ok3,lr + set_icc 0x2 2 + bcnelr icc2,0,2 + fail +ok3: + set_spr_addr ok4,lr + set_icc 0x3 3 + bcnelr icc3,0,3 + fail +ok4: + set_spr_addr bad,lr + set_icc 0x4 0 + bcnelr icc0,0,0 + + set_spr_addr bad,lr + set_icc 0x5 1 + bcnelr icc1,0,1 + + set_spr_addr bad,lr + set_icc 0x6 2 + bcnelr icc2,0,2 + + set_spr_addr bad,lr + set_icc 0x7 3 + bcnelr icc3,0,3 + + set_spr_addr ok9,lr + set_icc 0x8 0 + bcnelr icc0,0,0 + fail +ok9: + set_spr_addr oka,lr + set_icc 0x9 1 + bcnelr icc1,0,1 + fail +oka: + set_spr_addr okb,lr + set_icc 0xa 2 + bcnelr icc2,0,2 + fail +okb: + set_spr_addr okc,lr + set_icc 0xb 3 + bcnelr icc3,0,3 + fail +okc: + set_spr_addr bad,lr + set_icc 0xc 0 + bcnelr icc0,0,0 + + set_spr_addr bad,lr + set_icc 0xd 1 + bcnelr icc1,0,1 + + set_spr_addr bad,lr + set_icc 0xe 2 + bcnelr icc2,0,2 + + set_spr_addr bad,lr + set_icc 0xf 3 + bcnelr icc3,0,3 + + ; ccond is true + set_spr_immed 1,lcr + set_spr_addr okh,lr + set_icc 0x0 0 + bcnelr icc0,1,0 + fail +okh: + set_spr_immed 1,lcr + set_spr_addr oki,lr + set_icc 0x1 1 + bcnelr icc1,1,1 + fail +oki: + set_spr_immed 1,lcr + set_spr_addr okj,lr + set_icc 0x2 2 + bcnelr icc2,1,2 + fail +okj: + set_spr_immed 1,lcr + set_spr_addr okk,lr + set_icc 0x3 3 + bcnelr icc3,1,3 + fail +okk: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x4 0 + bcnelr icc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x5 1 + bcnelr icc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x6 2 + bcnelr icc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x7 3 + bcnelr icc3,1,3 + + set_spr_immed 1,lcr + set_spr_addr okp,lr + set_icc 0x8 0 + bcnelr icc0,1,0 + fail +okp: + set_spr_immed 1,lcr + set_spr_addr okq,lr + set_icc 0x9 1 + bcnelr icc1,1,1 + fail +okq: + set_spr_immed 1,lcr + set_spr_addr okr,lr + set_icc 0xa 2 + bcnelr icc2,1,2 + fail +okr: + set_spr_immed 1,lcr + set_spr_addr oks,lr + set_icc 0xb 3 + bcnelr icc3,1,3 + fail +oks: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xc 0 + bcnelr icc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xd 1 + bcnelr icc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xe 2 + bcnelr icc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xf 3 + bcnelr icc3,1,3 + + ; ccond is false + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcnelr icc0,1,0 + + set_icc 0x1 1 + bcnelr icc1,1,1 + + set_icc 0x2 2 + bcnelr icc2,1,2 + + set_icc 0x3 3 + bcnelr icc3,1,3 + + set_icc 0x4 0 + bcnelr icc0,1,0 + + set_icc 0x5 1 + bcnelr icc1,1,1 + + set_icc 0x6 2 + bcnelr icc2,1,2 + + set_icc 0x7 3 + bcnelr icc3,1,3 + + set_icc 0x8 0 + bcnelr icc0,1,0 + + set_icc 0x9 1 + bcnelr icc1,1,1 + + set_icc 0xa 2 + bcnelr icc2,1,2 + + set_icc 0xb 3 + bcnelr icc3,1,3 + + set_icc 0xc 0 + bcnelr icc0,1,0 + + set_icc 0xd 1 + bcnelr icc1,1,1 + + set_icc 0xe 2 + bcnelr icc2,1,2 + + set_icc 0xf 3 + bcnelr icc3,1,3 + + ; ccond is false + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcnelr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x1 1 + bcnelr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0x2 2 + bcnelr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0x3 3 + bcnelr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0x4 0 + bcnelr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x5 1 + bcnelr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0x6 2 + bcnelr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0x7 3 + bcnelr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0x8 0 + bcnelr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x9 1 + bcnelr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0xa 2 + bcnelr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0xb 3 + bcnelr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0xc 0 + bcnelr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0xd 1 + bcnelr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0xe 2 + bcnelr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0xf 3 + bcnelr icc3,0,3 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/bcnlr.cgs b/sim/testsuite/sim/frv/bcnlr.cgs new file mode 100644 index 0000000..8ddfcaa --- /dev/null +++ b/sim/testsuite/sim/frv/bcnlr.cgs @@ -0,0 +1,293 @@ +# frv testcase for bcnlr $ICCi,$ccond,$hint +# mach: all + + .include "testutils.inc" + + start + + .global bcnlr +bcnlr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcnlr icc0,0,0 + + set_spr_addr bad,lr + set_icc 0x1 1 + bcnlr icc1,0,1 + + set_spr_addr bad,lr + set_icc 0x2 2 + bcnlr icc2,0,2 + + set_spr_addr bad,lr + set_icc 0x3 3 + bcnlr icc3,0,3 + + set_spr_addr bad,lr + set_icc 0x4 0 + bcnlr icc0,0,0 + + set_spr_addr bad,lr + set_icc 0x5 1 + bcnlr icc1,0,1 + + set_spr_addr bad,lr + set_icc 0x6 2 + bcnlr icc2,0,2 + + set_spr_addr bad,lr + set_icc 0x7 3 + bcnlr icc3,0,3 + + set_spr_addr ok9,lr + set_icc 0x8 0 + bcnlr icc0,0,0 + fail +ok9: + set_spr_addr oka,lr + set_icc 0x9 1 + bcnlr icc1,0,1 + fail +oka: + set_spr_addr okb,lr + set_icc 0xa 2 + bcnlr icc2,0,2 + fail +okb: + set_spr_addr okc,lr + set_icc 0xb 3 + bcnlr icc3,0,3 + fail +okc: + set_spr_addr okd,lr + set_icc 0xc 0 + bcnlr icc0,0,0 + fail +okd: + set_spr_addr oke,lr + set_icc 0xd 1 + bcnlr icc1,0,1 + fail +oke: + set_spr_addr okf,lr + set_icc 0xe 2 + bcnlr icc2,0,2 + fail +okf: + set_spr_addr okg,lr + set_icc 0xf 3 + bcnlr icc3,0,3 + fail +okg: + + ; ccond is true + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcnlr icc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x1 1 + bcnlr icc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x2 2 + bcnlr icc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x3 3 + bcnlr icc3,1,3 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x4 0 + bcnlr icc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x5 1 + bcnlr icc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x6 2 + bcnlr icc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x7 3 + bcnlr icc3,1,3 + + set_spr_immed 1,lcr + set_spr_addr okp,lr + set_icc 0x8 0 + bcnlr icc0,1,0 + fail +okp: + set_spr_immed 1,lcr + set_spr_addr okq,lr + set_icc 0x9 1 + bcnlr icc1,1,1 + fail +okq: + set_spr_immed 1,lcr + set_spr_addr okr,lr + set_icc 0xa 2 + bcnlr icc2,1,2 + fail +okr: + set_spr_immed 1,lcr + set_spr_addr oks,lr + set_icc 0xb 3 + bcnlr icc3,1,3 + fail +oks: + set_spr_immed 1,lcr + set_spr_addr okt,lr + set_icc 0xc 0 + bcnlr icc0,1,0 + fail +okt: + set_spr_immed 1,lcr + set_spr_addr oku,lr + set_icc 0xd 1 + bcnlr icc1,1,1 + fail +oku: + set_spr_immed 1,lcr + set_spr_addr okv,lr + set_icc 0xe 2 + bcnlr icc2,1,2 + fail +okv: + set_spr_immed 1,lcr + set_spr_addr okw,lr + set_icc 0xf 3 + bcnlr icc3,1,3 + fail +okw: + ; ccond is false + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcnlr icc0,1,0 + + set_icc 0x1 1 + bcnlr icc1,1,1 + + set_icc 0x2 2 + bcnlr icc2,1,2 + + set_icc 0x3 3 + bcnlr icc3,1,3 + + set_icc 0x4 0 + bcnlr icc0,1,0 + + set_icc 0x5 1 + bcnlr icc1,1,1 + + set_icc 0x6 2 + bcnlr icc2,1,2 + + set_icc 0x7 3 + bcnlr icc3,1,3 + + set_icc 0x8 0 + bcnlr icc0,1,0 + + set_icc 0x9 1 + bcnlr icc1,1,1 + + set_icc 0xa 2 + bcnlr icc2,1,2 + + set_icc 0xb 3 + bcnlr icc3,1,3 + + set_icc 0xc 0 + bcnlr icc0,1,0 + + set_icc 0xd 1 + bcnlr icc1,1,1 + + set_icc 0xe 2 + bcnlr icc2,1,2 + + set_icc 0xf 3 + bcnlr icc3,1,3 + + ; ccond is false + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcnlr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x1 1 + bcnlr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0x2 2 + bcnlr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0x3 3 + bcnlr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0x4 0 + bcnlr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x5 1 + bcnlr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0x6 2 + bcnlr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0x7 3 + bcnlr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0x8 0 + bcnlr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x9 1 + bcnlr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0xa 2 + bcnlr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0xb 3 + bcnlr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0xc 0 + bcnlr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0xd 1 + bcnlr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0xe 2 + bcnlr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0xf 3 + bcnlr icc3,0,3 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/bcnolr.cgs b/sim/testsuite/sim/frv/bcnolr.cgs new file mode 100644 index 0000000..04f0b8d --- /dev/null +++ b/sim/testsuite/sim/frv/bcnolr.cgs @@ -0,0 +1,246 @@ +# frv testcase for bcnolr +# mach: all + + .include "testutils.inc" + + start + + .global bcnolr +bcnolr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcnolr + + set_icc 0x1 1 + bcnolr + + set_icc 0x2 2 + bcnolr + + set_icc 0x3 3 + bcnolr + + set_icc 0x4 0 + bcnolr + + set_icc 0x5 1 + bcnolr + + set_icc 0x6 2 + bcnolr + + set_icc 0x7 3 + bcnolr + + set_icc 0x8 0 + bcnolr + + set_icc 0x9 1 + bcnolr + + set_icc 0xa 2 + bcnolr + + set_icc 0xb 3 + bcnolr + + set_icc 0xc 0 + bcnolr + + set_icc 0xd 1 + bcnolr + + set_icc 0xe 2 + bcnolr + + set_icc 0xf 3 + bcnolr + + ; ccond is true + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcnolr + + set_spr_immed 1,lcr + set_icc 0x1 1 + bcnolr + + set_spr_immed 1,lcr + set_icc 0x2 2 + bcnolr + + set_spr_immed 1,lcr + set_icc 0x3 3 + bcnolr + + set_spr_immed 1,lcr + set_icc 0x4 0 + bcnolr + + set_spr_immed 1,lcr + set_icc 0x5 1 + bcnolr + + set_spr_immed 1,lcr + set_icc 0x6 2 + bcnolr + + set_spr_immed 1,lcr + set_icc 0x7 3 + bcnolr + + set_spr_immed 1,lcr + set_icc 0x8 0 + bcnolr + + set_spr_immed 1,lcr + set_icc 0x9 1 + bcnolr + + set_spr_immed 1,lcr + set_icc 0xa 2 + bcnolr + + set_spr_immed 1,lcr + set_icc 0xb 3 + bcnolr + + set_spr_immed 1,lcr + set_icc 0xc 0 + bcnolr + + set_spr_immed 1,lcr + set_icc 0xd 1 + bcnolr + + set_spr_immed 1,lcr + set_icc 0xe 2 + bcnolr + + set_spr_immed 1,lcr + set_icc 0xf 3 + bcnolr + + ; ccond is false + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcnolr + + set_icc 0x1 1 + bcnolr + + set_icc 0x2 2 + bcnolr + + set_icc 0x3 3 + bcnolr + + set_icc 0x4 0 + bcnolr + + set_icc 0x5 1 + bcnolr + + set_icc 0x6 2 + bcnolr + + set_icc 0x7 3 + bcnolr + + set_icc 0x8 0 + bcnolr + + set_icc 0x9 1 + bcnolr + + set_icc 0xa 2 + bcnolr + + set_icc 0xb 3 + bcnolr + + set_icc 0xc 0 + bcnolr + + set_icc 0xd 1 + bcnolr + + set_icc 0xe 2 + bcnolr + + set_icc 0xf 3 + bcnolr + + ; ccond is false + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcnolr + + set_spr_immed 1,lcr + set_icc 0x1 1 + bcnolr + + set_spr_immed 1,lcr + set_icc 0x2 2 + bcnolr + + set_spr_immed 1,lcr + set_icc 0x3 3 + bcnolr + + set_spr_immed 1,lcr + set_icc 0x4 0 + bcnolr + + set_spr_immed 1,lcr + set_icc 0x5 1 + bcnolr + + set_spr_immed 1,lcr + set_icc 0x6 2 + bcnolr + + set_spr_immed 1,lcr + set_icc 0x7 3 + bcnolr + + set_spr_immed 1,lcr + set_icc 0x8 0 + bcnolr + + set_spr_immed 1,lcr + set_icc 0x9 1 + bcnolr + + set_spr_immed 1,lcr + set_icc 0xa 2 + bcnolr + + set_spr_immed 1,lcr + set_icc 0xb 3 + bcnolr + + set_spr_immed 1,lcr + set_icc 0xc 0 + bcnolr + + set_spr_immed 1,lcr + set_icc 0xd 1 + bcnolr + + set_spr_immed 1,lcr + set_icc 0xe 2 + bcnolr + + set_spr_immed 1,lcr + set_icc 0xf 3 + bcnolr + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/bcnvlr.cgs b/sim/testsuite/sim/frv/bcnvlr.cgs new file mode 100644 index 0000000..2451557 --- /dev/null +++ b/sim/testsuite/sim/frv/bcnvlr.cgs @@ -0,0 +1,292 @@ +# frv testcase for bcnvlr $ICCi,$ccond,$hint +# mach: all + + .include "testutils.inc" + + start + + .global bcnvlr +bcnvlr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr ok1,lr + set_icc 0x0 0 + bcnvlr icc0,0,0 + fail +ok1: + set_spr_addr ok2,lr + set_icc 0x1 1 + bcnvlr icc1,0,1 + fail +ok2: + set_spr_addr bad,lr + set_icc 0x2 2 + bcnvlr icc2,0,2 + + set_spr_addr bad,lr + set_icc 0x3 3 + bcnvlr icc3,0,3 + + set_spr_addr ok5,lr + set_icc 0x4 0 + bcnvlr icc0,0,0 + fail +ok5: + set_spr_addr ok6,lr + set_icc 0x5 1 + bcnvlr icc1,0,1 + fail +ok6: + set_spr_addr bad,lr + set_icc 0x6 2 + bcnvlr icc2,0,2 + + set_spr_addr bad,lr + set_icc 0x7 3 + bcnvlr icc3,0,3 + + set_spr_addr ok9,lr + set_icc 0x8 0 + bcnvlr icc0,0,0 + fail +ok9: + set_spr_addr oka,lr + set_icc 0x9 1 + bcnvlr icc1,0,1 + fail +oka: + set_spr_addr bad,lr + set_icc 0xa 2 + bcnvlr icc2,0,2 + + set_spr_addr bad,lr + set_icc 0xb 3 + bcnvlr icc3,0,3 + + set_spr_addr okd,lr + set_icc 0xc 0 + bcnvlr icc0,0,0 + fail +okd: + set_spr_addr oke,lr + set_icc 0xd 1 + bcnvlr icc1,0,1 + fail +oke: + set_spr_addr bad,lr + set_icc 0xe 2 + bcnvlr icc2,0,2 + + set_spr_addr bad,lr + set_icc 0xf 3 + bcnvlr icc3,0,3 + + ; ccond is true + set_spr_immed 1,lcr + set_spr_addr okh,lr + set_icc 0x0 0 + bcnvlr icc0,1,0 + fail +okh: + set_spr_immed 1,lcr + set_spr_addr oki,lr + set_icc 0x1 1 + bcnvlr icc1,1,1 + fail +oki: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x2 2 + bcnvlr icc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x3 3 + bcnvlr icc3,1,3 + + set_spr_immed 1,lcr + set_spr_addr okl,lr + set_icc 0x4 0 + bcnvlr icc0,1,0 + fail +okl: + set_spr_immed 1,lcr + set_spr_addr okm,lr + set_icc 0x5 1 + bcnvlr icc1,1,1 + fail +okm: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x6 2 + bcnvlr icc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x7 3 + bcnvlr icc3,1,3 + + set_spr_immed 1,lcr + set_spr_addr okp,lr + set_icc 0x8 0 + bcnvlr icc0,1,0 + fail +okp: + set_spr_immed 1,lcr + set_spr_addr okq,lr + set_icc 0x9 1 + bcnvlr icc1,1,1 + fail +okq: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xa 2 + bcnvlr icc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xb 3 + bcnvlr icc3,1,3 + + set_spr_immed 1,lcr + set_spr_addr okt,lr + set_icc 0xc 0 + bcnvlr icc0,1,0 + fail +okt: + set_spr_immed 1,lcr + set_spr_addr oku,lr + set_icc 0xd 1 + bcnvlr icc1,1,1 + fail +oku: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xe 2 + bcnvlr icc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xf 3 + bcnvlr icc3,1,3 + + ; ccond is false + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcnvlr icc0,1,0 + + set_icc 0x1 1 + bcnvlr icc1,1,1 + + set_icc 0x2 2 + bcnvlr icc2,1,2 + + set_icc 0x3 3 + bcnvlr icc3,1,3 + + set_icc 0x4 0 + bcnvlr icc0,1,0 + + set_icc 0x5 1 + bcnvlr icc1,1,1 + + set_icc 0x6 2 + bcnvlr icc2,1,2 + + set_icc 0x7 3 + bcnvlr icc3,1,3 + + set_icc 0x8 0 + bcnvlr icc0,1,0 + + set_icc 0x9 1 + bcnvlr icc1,1,1 + + set_icc 0xa 2 + bcnvlr icc2,1,2 + + set_icc 0xb 3 + bcnvlr icc3,1,3 + + set_icc 0xc 0 + bcnvlr icc0,1,0 + + set_icc 0xd 1 + bcnvlr icc1,1,1 + + set_icc 0xe 2 + bcnvlr icc2,1,2 + + set_icc 0xf 3 + bcnvlr icc3,1,3 + + ; ccond is false + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcnvlr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x1 1 + bcnvlr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0x2 2 + bcnvlr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0x3 3 + bcnvlr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0x4 0 + bcnvlr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x5 1 + bcnvlr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0x6 2 + bcnvlr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0x7 3 + bcnvlr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0x8 0 + bcnvlr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x9 1 + bcnvlr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0xa 2 + bcnvlr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0xb 3 + bcnvlr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0xc 0 + bcnvlr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0xd 1 + bcnvlr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0xe 2 + bcnvlr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0xf 3 + bcnvlr icc3,0,3 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/bcplr.cgs b/sim/testsuite/sim/frv/bcplr.cgs new file mode 100644 index 0000000..fef3ccb --- /dev/null +++ b/sim/testsuite/sim/frv/bcplr.cgs @@ -0,0 +1,292 @@ +# frv testcase for bcplr $ICCi,$ccond,$hint +# mach: all + + .include "testutils.inc" + + start + + .global bcplr +bcplr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr ok1,lr + set_icc 0x0 0 + bcplr icc0,0,0 + fail +ok1: + set_spr_addr ok2,lr + set_icc 0x1 1 + bcplr icc1,0,1 + fail +ok2: + set_spr_addr ok3,lr + set_icc 0x2 2 + bcplr icc2,0,2 + fail +ok3: + set_spr_addr ok4,lr + set_icc 0x3 3 + bcplr icc3,0,3 + fail +ok4: + set_spr_addr ok5,lr + set_icc 0x4 0 + bcplr icc0,0,0 + fail +ok5: + set_spr_addr ok6,lr + set_icc 0x5 1 + bcplr icc1,0,1 + fail +ok6: + set_spr_addr ok7,lr + set_icc 0x6 2 + bcplr icc2,0,2 + fail +ok7: + set_spr_addr ok8,lr + set_icc 0x7 3 + bcplr icc3,0,3 + fail +ok8: + set_spr_addr bad,lr + set_icc 0x8 0 + bcplr icc0,0,0 + + set_spr_addr bad,lr + set_icc 0x9 1 + bcplr icc1,0,1 + + set_spr_addr bad,lr + set_icc 0xa 2 + bcplr icc2,0,2 + + set_spr_addr bad,lr + set_icc 0xb 3 + bcplr icc3,0,3 + + set_spr_addr bad,lr + set_icc 0xc 0 + bcplr icc0,0,0 + + set_spr_addr bad,lr + set_icc 0xd 1 + bcplr icc1,0,1 + + set_spr_addr bad,lr + set_icc 0xe 2 + bcplr icc2,0,2 + + set_spr_addr bad,lr + set_icc 0xf 3 + bcplr icc3,0,3 + + ; ccond is true + set_spr_immed 1,lcr + set_spr_addr okh,lr + set_icc 0x0 0 + bcplr icc0,1,0 + fail +okh: + set_spr_immed 1,lcr + set_spr_addr oki,lr + set_icc 0x1 1 + bcplr icc1,1,1 + fail +oki: + set_spr_immed 1,lcr + set_spr_addr okj,lr + set_icc 0x2 2 + bcplr icc2,1,2 + fail +okj: + set_spr_immed 1,lcr + set_spr_addr okk,lr + set_icc 0x3 3 + bcplr icc3,1,3 + fail +okk: + set_spr_immed 1,lcr + set_spr_addr okl,lr + set_icc 0x4 0 + bcplr icc0,1,0 + fail +okl: + set_spr_immed 1,lcr + set_spr_addr okm,lr + set_icc 0x5 1 + bcplr icc1,1,1 + fail +okm: + set_spr_immed 1,lcr + set_spr_addr okn,lr + set_icc 0x6 2 + bcplr icc2,1,2 + fail +okn: + set_spr_immed 1,lcr + set_spr_addr oko,lr + set_icc 0x7 3 + bcplr icc3,1,3 + fail +oko: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x8 0 + bcplr icc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x9 1 + bcplr icc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xa 2 + bcplr icc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xb 3 + bcplr icc3,1,3 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xc 0 + bcplr icc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xd 1 + bcplr icc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xe 2 + bcplr icc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xf 3 + bcplr icc3,1,3 + + ; ccond is false + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcplr icc0,1,0 + + set_icc 0x1 1 + bcplr icc1,1,1 + + set_icc 0x2 2 + bcplr icc2,1,2 + + set_icc 0x3 3 + bcplr icc3,1,3 + + set_icc 0x4 0 + bcplr icc0,1,0 + + set_icc 0x5 1 + bcplr icc1,1,1 + + set_icc 0x6 2 + bcplr icc2,1,2 + + set_icc 0x7 3 + bcplr icc3,1,3 + + set_icc 0x8 0 + bcplr icc0,1,0 + + set_icc 0x9 1 + bcplr icc1,1,1 + + set_icc 0xa 2 + bcplr icc2,1,2 + + set_icc 0xb 3 + bcplr icc3,1,3 + + set_icc 0xc 0 + bcplr icc0,1,0 + + set_icc 0xd 1 + bcplr icc1,1,1 + + set_icc 0xe 2 + bcplr icc2,1,2 + + set_icc 0xf 3 + bcplr icc3,1,3 + + ; ccond is false + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcplr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x1 1 + bcplr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0x2 2 + bcplr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0x3 3 + bcplr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0x4 0 + bcplr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x5 1 + bcplr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0x6 2 + bcplr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0x7 3 + bcplr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0x8 0 + bcplr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x9 1 + bcplr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0xa 2 + bcplr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0xb 3 + bcplr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0xc 0 + bcplr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0xd 1 + bcplr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0xe 2 + bcplr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0xf 3 + bcplr icc3,0,3 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/bcralr.cgs b/sim/testsuite/sim/frv/bcralr.cgs new file mode 100644 index 0000000..612363d --- /dev/null +++ b/sim/testsuite/sim/frv/bcralr.cgs @@ -0,0 +1,309 @@ +# frv testcase for bcralr $ccond +# mach: all + + .include "testutils.inc" + + start + + .global bcralr +bcralr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr ok1,lr + set_icc 0x0 0 + bcralr 0 + fail +ok1: + set_spr_addr ok2,lr + set_icc 0x1 1 + bcralr 0 + fail +ok2: + set_spr_addr ok3,lr + set_icc 0x2 2 + bcralr 0 + fail +ok3: + set_spr_addr ok4,lr + set_icc 0x3 3 + bcralr 0 + fail +ok4: + set_spr_addr ok5,lr + set_icc 0x4 0 + bcralr 0 + fail +ok5: + set_spr_addr ok6,lr + set_icc 0x5 1 + bcralr 0 + fail +ok6: + set_spr_addr ok7,lr + set_icc 0x6 2 + bcralr 0 + fail +ok7: + set_spr_addr ok8,lr + set_icc 0x7 3 + bcralr 0 + fail +ok8: + set_spr_addr ok9,lr + set_icc 0x8 0 + bcralr 0 + fail +ok9: + set_spr_addr oka,lr + set_icc 0x9 1 + bcralr 0 + fail +oka: + set_spr_addr okb,lr + set_icc 0xa 2 + bcralr 0 + fail +okb: + set_spr_addr okc,lr + set_icc 0xb 3 + bcralr 0 + fail +okc: + set_spr_addr okd,lr + set_icc 0xc 0 + bcralr 0 + fail +okd: + set_spr_addr oke,lr + set_icc 0xd 1 + bcralr 0 + fail +oke: + set_spr_addr okf,lr + set_icc 0xe 2 + bcralr 0 + fail +okf: + set_spr_addr okg,lr + set_icc 0xf 3 + bcralr 0 + fail +okg: + + ; ccond is true + set_spr_immed 1,lcr + set_spr_addr okh,lr + set_icc 0x0 0 + bcralr 1 + fail +okh: + set_spr_immed 1,lcr + set_spr_addr oki,lr + set_icc 0x1 1 + bcralr 1 + fail +oki: + set_spr_immed 1,lcr + set_spr_addr okj,lr + set_icc 0x2 2 + bcralr 1 + fail +okj: + set_spr_immed 1,lcr + set_spr_addr okk,lr + set_icc 0x3 3 + bcralr 1 + fail +okk: + set_spr_immed 1,lcr + set_spr_addr okl,lr + set_icc 0x4 0 + bcralr 1 + fail +okl: + set_spr_immed 1,lcr + set_spr_addr okm,lr + set_icc 0x5 1 + bcralr 1 + fail +okm: + set_spr_immed 1,lcr + set_spr_addr okn,lr + set_icc 0x6 2 + bcralr 1 + fail +okn: + set_spr_immed 1,lcr + set_spr_addr oko,lr + set_icc 0x7 3 + bcralr 1 + fail +oko: + set_spr_immed 1,lcr + set_spr_addr okp,lr + set_icc 0x8 0 + bcralr 1 + fail +okp: + set_spr_immed 1,lcr + set_spr_addr okq,lr + set_icc 0x9 1 + bcralr 1 + fail +okq: + set_spr_immed 1,lcr + set_spr_addr okr,lr + set_icc 0xa 2 + bcralr 1 + fail +okr: + set_spr_immed 1,lcr + set_spr_addr oks,lr + set_icc 0xb 3 + bcralr 1 + fail +oks: + set_spr_immed 1,lcr + set_spr_addr okt,lr + set_icc 0xc 0 + bcralr 1 + fail +okt: + set_spr_immed 1,lcr + set_spr_addr oku,lr + set_icc 0xd 1 + bcralr 1 + fail +oku: + set_spr_immed 1,lcr + set_spr_addr okv,lr + set_icc 0xe 2 + bcralr 1 + fail +okv: + set_spr_immed 1,lcr + set_spr_addr okw,lr + set_icc 0xf 3 + bcralr 1 + fail +okw: + ; ccond is false + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcralr 1 + + set_icc 0x1 1 + bcralr 1 + + set_icc 0x2 2 + bcralr 1 + + set_icc 0x3 3 + bcralr 1 + + set_icc 0x4 0 + bcralr 1 + + set_icc 0x5 1 + bcralr 1 + + set_icc 0x6 2 + bcralr 1 + + set_icc 0x7 3 + bcralr 1 + + set_icc 0x8 0 + bcralr 1 + + set_icc 0x9 1 + bcralr 1 + + set_icc 0xa 2 + bcralr 1 + + set_icc 0xb 3 + bcralr 1 + + set_icc 0xc 0 + bcralr 1 + + set_icc 0xd 1 + bcralr 1 + + set_icc 0xe 2 + bcralr 1 + + set_icc 0xf 3 + bcralr 1 + + ; ccond is false + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcralr 0 + + set_spr_immed 1,lcr + set_icc 0x1 1 + bcralr 0 + + set_spr_immed 1,lcr + set_icc 0x2 2 + bcralr 0 + + set_spr_immed 1,lcr + set_icc 0x3 3 + bcralr 0 + + set_spr_immed 1,lcr + set_icc 0x4 0 + bcralr 0 + + set_spr_immed 1,lcr + set_icc 0x5 1 + bcralr 0 + + set_spr_immed 1,lcr + set_icc 0x6 2 + bcralr 0 + + set_spr_immed 1,lcr + set_icc 0x7 3 + bcralr 0 + + set_spr_immed 1,lcr + set_icc 0x8 0 + bcralr 0 + + set_spr_immed 1,lcr + set_icc 0x9 1 + bcralr 0 + + set_spr_immed 1,lcr + set_icc 0xa 2 + bcralr 0 + + set_spr_immed 1,lcr + set_icc 0xb 3 + bcralr 0 + + set_spr_immed 1,lcr + set_icc 0xc 0 + bcralr 0 + + set_spr_immed 1,lcr + set_icc 0xd 1 + bcralr 0 + + set_spr_immed 1,lcr + set_icc 0xe 2 + bcralr 0 + + set_spr_immed 1,lcr + set_icc 0xf 3 + bcralr 0 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/bctrlr.cgs b/sim/testsuite/sim/frv/bctrlr.cgs new file mode 100644 index 0000000..b00cb97 --- /dev/null +++ b/sim/testsuite/sim/frv/bctrlr.cgs @@ -0,0 +1,29 @@ +# frv testcase for bctrlr $ccond,$hint +# mach: all + + .include "testutils.inc" + + start + + .global bctrlr +bctrlr: + set_spr_addr bad,lr + set_spr_immed 1,lcr + bctrlr 0,0 + + set_spr_addr ok1,lr + set_spr_immed 2,lcr + bctrlr 0,0 + fail +ok1: + set_spr_addr bad,lr + set_spr_immed 2,lcr + bctrlr 1,0 + + set_spr_addr ok2,lr + bctrlr 1,0 + fail +ok2: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/bcvlr.cgs b/sim/testsuite/sim/frv/bcvlr.cgs new file mode 100644 index 0000000..b25d646 --- /dev/null +++ b/sim/testsuite/sim/frv/bcvlr.cgs @@ -0,0 +1,293 @@ +# frv testcase for bcvlr $ICCi,$ccond,$hint +# mach: all + + .include "testutils.inc" + + start + + .global bcvlr +bcvlr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcvlr icc0,0,0 + + set_spr_addr bad,lr + set_icc 0x1 1 + bcvlr icc1,0,1 + + set_spr_addr ok3,lr + set_icc 0x2 2 + bcvlr icc2,0,2 + fail +ok3: + set_spr_addr ok4,lr + set_icc 0x3 3 + bcvlr icc3,0,3 + fail +ok4: + set_spr_addr bad,lr + set_icc 0x4 0 + bcvlr icc0,0,0 + + set_spr_addr bad,lr + set_icc 0x5 1 + bcvlr icc1,0,1 + + set_spr_addr ok7,lr + set_icc 0x6 2 + bcvlr icc2,0,2 + fail +ok7: + set_spr_addr ok8,lr + set_icc 0x7 3 + bcvlr icc3,0,3 + fail +ok8: + set_spr_addr bad,lr + set_icc 0x8 0 + bcvlr icc0,0,0 + + set_spr_addr bad,lr + set_icc 0x9 1 + bcvlr icc1,0,1 + + set_spr_addr okb,lr + set_icc 0xa 2 + bcvlr icc2,0,2 + fail +okb: + set_spr_addr okc,lr + set_icc 0xb 3 + bcvlr icc3,0,3 + fail +okc: + set_spr_addr bad,lr + set_icc 0xc 0 + bcvlr icc0,0,0 + + set_spr_addr bad,lr + set_icc 0xd 1 + bcvlr icc1,0,1 + + set_spr_addr okf,lr + set_icc 0xe 2 + bcvlr icc2,0,2 + fail +okf: + set_spr_addr okg,lr + set_icc 0xf 3 + bcvlr icc3,0,3 + fail +okg: + + ; ccond is true + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcvlr icc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x1 1 + bcvlr icc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr okj,lr + set_icc 0x2 2 + bcvlr icc2,1,2 + fail +okj: + set_spr_immed 1,lcr + set_spr_addr okk,lr + set_icc 0x3 3 + bcvlr icc3,1,3 + fail +okk: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x4 0 + bcvlr icc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x5 1 + bcvlr icc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr okn,lr + set_icc 0x6 2 + bcvlr icc2,1,2 + fail +okn: + set_spr_immed 1,lcr + set_spr_addr oko,lr + set_icc 0x7 3 + bcvlr icc3,1,3 + fail +oko: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x8 0 + bcvlr icc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x9 1 + bcvlr icc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr okr,lr + set_icc 0xa 2 + bcvlr icc2,1,2 + fail +okr: + set_spr_immed 1,lcr + set_spr_addr oks,lr + set_icc 0xb 3 + bcvlr icc3,1,3 + fail +oks: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xc 0 + bcvlr icc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0xd 1 + bcvlr icc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr okv,lr + set_icc 0xe 2 + bcvlr icc2,1,2 + fail +okv: + set_spr_immed 1,lcr + set_spr_addr okw,lr + set_icc 0xf 3 + bcvlr icc3,1,3 + fail +okw: + ; ccond is false + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcvlr icc0,1,0 + + set_icc 0x1 1 + bcvlr icc1,1,1 + + set_icc 0x2 2 + bcvlr icc2,1,2 + + set_icc 0x3 3 + bcvlr icc3,1,3 + + set_icc 0x4 0 + bcvlr icc0,1,0 + + set_icc 0x5 1 + bcvlr icc1,1,1 + + set_icc 0x6 2 + bcvlr icc2,1,2 + + set_icc 0x7 3 + bcvlr icc3,1,3 + + set_icc 0x8 0 + bcvlr icc0,1,0 + + set_icc 0x9 1 + bcvlr icc1,1,1 + + set_icc 0xa 2 + bcvlr icc2,1,2 + + set_icc 0xb 3 + bcvlr icc3,1,3 + + set_icc 0xc 0 + bcvlr icc0,1,0 + + set_icc 0xd 1 + bcvlr icc1,1,1 + + set_icc 0xe 2 + bcvlr icc2,1,2 + + set_icc 0xf 3 + bcvlr icc3,1,3 + + ; ccond is false + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_icc 0x0 0 + bcvlr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x1 1 + bcvlr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0x2 2 + bcvlr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0x3 3 + bcvlr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0x4 0 + bcvlr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x5 1 + bcvlr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0x6 2 + bcvlr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0x7 3 + bcvlr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0x8 0 + bcvlr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0x9 1 + bcvlr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0xa 2 + bcvlr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0xb 3 + bcvlr icc3,0,3 + + set_spr_immed 1,lcr + set_icc 0xc 0 + bcvlr icc0,0,0 + + set_spr_immed 1,lcr + set_icc 0xd 1 + bcvlr icc1,0,1 + + set_spr_immed 1,lcr + set_icc 0xe 2 + bcvlr icc2,0,2 + + set_spr_immed 1,lcr + set_icc 0xf 3 + bcvlr icc3,0,3 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/beq.cgs b/sim/testsuite/sim/frv/beq.cgs new file mode 100644 index 0000000..b3706dc --- /dev/null +++ b/sim/testsuite/sim/frv/beq.cgs @@ -0,0 +1,61 @@ +# frv testcase for beq $ICCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global beq +beq: + set_icc 0x0 0 + beq icc0,0,bad + set_icc 0x1 1 + beq icc1,1,bad + set_icc 0x2 2 + beq icc2,2,bad + set_icc 0x3 3 + beq icc3,3,bad + set_icc 0x4 0 + beq icc0,0,ok1 + fail +ok1: + set_icc 0x5 1 + beq icc1,1,ok2 + fail +ok2: + set_icc 0x6 2 + beq icc2,2,ok3 + fail +ok3: + set_icc 0x7 3 + beq icc3,3,ok4 + fail +ok4: + set_icc 0x8 0 + beq icc0,0,bad + set_icc 0x9 1 + beq icc1,1,bad + set_icc 0xa 2 + beq icc2,2,bad + set_icc 0xb 3 + beq icc3,3,bad + set_icc 0xc 0 + beq icc0,0,ok5 + fail +ok5: + set_icc 0xd 1 + beq icc1,1,ok6 + fail +ok6: + set_icc 0xe 2 + beq icc2,2,ok7 + fail +ok7: + set_icc 0xf 3 + beq icc3,3,ok8 + fail +ok8: + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/beqlr.cgs b/sim/testsuite/sim/frv/beqlr.cgs new file mode 100644 index 0000000..772b9fa --- /dev/null +++ b/sim/testsuite/sim/frv/beqlr.cgs @@ -0,0 +1,71 @@ +# frv testcase for beqlr $ICCi,$hint +# mach: all + + .include "testutils.inc" + + start + + .global beqlr +beqlr: + set_spr_addr bad,lr + set_icc 0x0 0 + beqlr icc0,0 + set_icc 0x1 1 + beqlr icc1,1 + set_icc 0x2 2 + beqlr icc2,2 + set_icc 0x3 3 + beqlr icc3,3 + set_spr_addr ok1,lr + set_icc 0x4 0 + beqlr icc0,0 + fail +ok1: + set_spr_addr ok2,lr + set_icc 0x5 1 + beqlr icc1,1 + fail +ok2: + set_spr_addr ok3,lr + set_icc 0x6 2 + beqlr icc2,2 + fail +ok3: + set_spr_addr ok4,lr + set_icc 0x7 3 + beqlr icc3,3 + fail +ok4: + set_spr_addr bad,lr + set_icc 0x8 0 + beqlr icc0,0 + set_icc 0x9 1 + beqlr icc1,1 + set_icc 0xa 2 + beqlr icc2,2 + set_icc 0xb 3 + beqlr icc3,3 + set_spr_addr ok5,lr + set_icc 0xc 0 + beqlr icc0,0 + fail +ok5: + set_spr_addr ok6,lr + set_icc 0xd 1 + beqlr icc1,1 + fail +ok6: + set_spr_addr ok7,lr + set_icc 0xe 2 + beqlr icc2,2 + fail +ok7: + set_spr_addr ok8,lr + set_icc 0xf 3 + beqlr icc3,3 + fail +ok8: + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/bge.cgs b/sim/testsuite/sim/frv/bge.cgs new file mode 100644 index 0000000..7ebead7 --- /dev/null +++ b/sim/testsuite/sim/frv/bge.cgs @@ -0,0 +1,61 @@ +# frv testcase for bge $ICCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global bge +bge: + set_icc 0x0 0 + bge icc0,0,ok1 + fail +ok1: + set_icc 0x1 1 + bge icc1,1,ok2 + fail +ok2: + set_icc 0x2 2 + bge icc2,2,bad + set_icc 0x3 3 + bge icc3,3,bad + set_icc 0x4 0 + bge icc0,0,ok5 + fail +ok5: + set_icc 0x5 1 + bge icc1,1,ok6 + fail +ok6: + set_icc 0x6 2 + bge icc2,2,bad + set_icc 0x7 3 + bge icc3,3,bad + set_icc 0x8 0 + bge icc0,0,bad + set_icc 0x9 1 + bge icc1,1,bad + set_icc 0xa 2 + bge icc2,2,okb + fail +okb: + set_icc 0xb 3 + bge icc3,3,okc + fail +okc: + set_icc 0xc 0 + bge icc0,0,bad + set_icc 0xd 1 + bge icc1,1,bad + set_icc 0xe 2 + bge icc2,2,okf + fail +okf: + set_icc 0xf 3 + bge icc3,3,okg + fail +okg: + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/bgelr.cgs b/sim/testsuite/sim/frv/bgelr.cgs new file mode 100644 index 0000000..806770a --- /dev/null +++ b/sim/testsuite/sim/frv/bgelr.cgs @@ -0,0 +1,84 @@ +# frv testcase for bgelr $ICCi,$hint +# mach: all + + .include "testutils.inc" + + start + + .global bgelr +bgelr: + set_spr_addr ok1,lr + set_icc 0x0 0 + bgelr icc0,0 + fail +ok1: + set_spr_addr ok2,lr + set_icc 0x1 1 + bgelr icc1,1 + fail +ok2: + set_spr_addr bad,lr + set_icc 0x2 2 + bgelr icc2,2 + + set_spr_addr bad,lr + set_icc 0x3 3 + bgelr icc3,3 + + set_spr_addr ok5,lr + set_icc 0x4 0 + bgelr icc0,0 + fail +ok5: + set_spr_addr ok6,lr + set_icc 0x5 1 + bgelr icc1,1 + fail +ok6: + set_spr_addr bad,lr + set_icc 0x6 2 + bgelr icc2,2 + + set_spr_addr bad,lr + set_icc 0x7 3 + bgelr icc3,3 + + set_spr_addr bad,lr + set_icc 0x8 0 + bgelr icc0,0 + + set_spr_addr bad,lr + set_icc 0x9 1 + bgelr icc1,1 + + set_spr_addr okb,lr + set_icc 0xa 2 + bgelr icc2,2 + fail +okb: + set_spr_addr okc,lr + set_icc 0xb 3 + bgelr icc3,3 + fail +okc: + set_spr_addr bad,lr + set_icc 0xc 0 + bgelr icc0,0 + + set_spr_addr bad,lr + set_icc 0xd 1 + bgelr icc1,1 + + set_spr_addr okf,lr + set_icc 0xe 2 + bgelr icc2,2 + fail +okf: + set_spr_addr okg,lr + set_icc 0xf 3 + bgelr icc3,3 + fail +okg: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/bgt.cgs b/sim/testsuite/sim/frv/bgt.cgs new file mode 100644 index 0000000..98b1b17 --- /dev/null +++ b/sim/testsuite/sim/frv/bgt.cgs @@ -0,0 +1,53 @@ +# frv testcase for bgt $ICCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global bgt +bgt: + set_icc 0x0 0 + bgt icc0,0,ok1 + fail +ok1: + set_icc 0x1 1 + bgt icc1,1,ok2 + fail +ok2: + set_icc 0x2 2 + bgt icc2,2,bad + set_icc 0x3 3 + bgt icc3,3,bad + set_icc 0x4 0 + bgt icc0,0,bad + set_icc 0x5 1 + bgt icc1,1,bad + set_icc 0x6 2 + bgt icc2,2,bad + set_icc 0x7 3 + bgt icc3,3,bad + set_icc 0x8 0 + bgt icc0,0,bad + set_icc 0x9 1 + bgt icc1,1,bad + set_icc 0xa 2 + bgt icc2,2,okb + fail +okb: + set_icc 0xb 3 + bgt icc3,3,okc + fail +okc: + set_icc 0xc 0 + bgt icc0,0,bad + set_icc 0xd 1 + bgt icc1,1,bad + set_icc 0xe 2 + bgt icc2,2,bad + set_icc 0xf 3 + bgt icc3,3,bad + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/bgtlr.cgs b/sim/testsuite/sim/frv/bgtlr.cgs new file mode 100644 index 0000000..ad44a2c --- /dev/null +++ b/sim/testsuite/sim/frv/bgtlr.cgs @@ -0,0 +1,80 @@ +# frv testcase for bgtlr $ICCi,$hint +# mach: all + + .include "testutils.inc" + + start + + .global bgtlr +bgtlr: + set_spr_addr ok1,lr + set_icc 0x0 0 + bgtlr icc0,0 + fail +ok1: + set_spr_addr ok2,lr + set_icc 0x1 1 + bgtlr icc1,1 + fail +ok2: + set_spr_addr bad,lr + set_icc 0x2 2 + bgtlr icc2,2 + + set_spr_addr bad,lr + set_icc 0x3 3 + bgtlr icc3,3 + + set_spr_addr bad,lr + set_icc 0x4 0 + bgtlr icc0,0 + + set_spr_addr bad,lr + set_icc 0x5 1 + bgtlr icc1,1 + + set_spr_addr bad,lr + set_icc 0x6 2 + bgtlr icc2,2 + + set_spr_addr bad,lr + set_icc 0x7 3 + bgtlr icc3,3 + + set_spr_addr bad,lr + set_icc 0x8 0 + bgtlr icc0,0 + + set_spr_addr bad,lr + set_icc 0x9 1 + bgtlr icc1,1 + + set_spr_addr okb,lr + set_icc 0xa 2 + bgtlr icc2,2 + fail +okb: + set_spr_addr okc,lr + set_icc 0xb 3 + bgtlr icc3,3 + fail +okc: + set_spr_addr bad,lr + set_icc 0xc 0 + bgtlr icc0,0 + + set_spr_addr bad,lr + set_icc 0xd 1 + bgtlr icc1,1 + + set_spr_addr bad,lr + set_icc 0xe 2 + bgtlr icc2,2 + + set_spr_addr bad,lr + set_icc 0xf 3 + bgtlr icc3,3 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/bhi.cgs b/sim/testsuite/sim/frv/bhi.cgs new file mode 100644 index 0000000..a92c0c0 --- /dev/null +++ b/sim/testsuite/sim/frv/bhi.cgs @@ -0,0 +1,53 @@ +# frv testcase for bhi $ICCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global bhi +bhi: + set_icc 0x0 0 + bhi icc0,0,ok1 + fail +ok1: + set_icc 0x1 1 + bhi icc1,1,bad + set_icc 0x2 2 + bhi icc2,2,ok3 + fail +ok3: + set_icc 0x3 3 + bhi icc3,3,bad + set_icc 0x4 0 + bhi icc0,0,bad + set_icc 0x5 1 + bhi icc1,1,bad + set_icc 0x6 2 + bhi icc2,2,bad + set_icc 0x7 3 + bhi icc3,3,bad + set_icc 0x8 0 + bhi icc0,0,ok9 + fail +ok9: + set_icc 0x9 1 + bhi icc1,1,bad + set_icc 0xa 2 + bhi icc2,2,okb + fail +okb: + set_icc 0xb 3 + bhi icc3,3,bad + set_icc 0xc 0 + bhi icc0,0,bad + set_icc 0xd 1 + bhi icc1,1,bad + set_icc 0xe 2 + bhi icc2,2,bad + set_icc 0xf 3 + bhi icc3,3,bad + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/bhilr.cgs b/sim/testsuite/sim/frv/bhilr.cgs new file mode 100644 index 0000000..927643b --- /dev/null +++ b/sim/testsuite/sim/frv/bhilr.cgs @@ -0,0 +1,80 @@ +# frv testcase for bhilr $ICCi,$hint +# mach: all + + .include "testutils.inc" + + start + + .global bhilr +bhilr: + set_spr_addr ok1,lr + set_icc 0x0 0 + bhilr icc0,0 + fail +ok1: + set_spr_addr bad,lr + set_icc 0x1 1 + bhilr icc1,1 + + set_spr_addr ok3,lr + set_icc 0x2 2 + bhilr icc2,2 + fail +ok3: + set_spr_addr bad,lr + set_icc 0x3 3 + bhilr icc3,3 + + set_spr_addr bad,lr + set_icc 0x4 0 + bhilr icc0,0 + + set_spr_addr bad,lr + set_icc 0x5 1 + bhilr icc1,1 + + set_spr_addr bad,lr + set_icc 0x6 2 + bhilr icc2,2 + + set_spr_addr bad,lr + set_icc 0x7 3 + bhilr icc3,3 + + set_spr_addr ok9,lr + set_icc 0x8 0 + bhilr icc0,0 + fail +ok9: + set_spr_addr bad,lr + set_icc 0x9 1 + bhilr icc1,1 + + set_spr_addr okb,lr + set_icc 0xa 2 + bhilr icc2,2 + fail +okb: + set_spr_addr bad,lr + set_icc 0xb 3 + bhilr icc3,3 + + set_spr_addr bad,lr + set_icc 0xc 0 + bhilr icc0,0 + + set_spr_addr bad,lr + set_icc 0xd 1 + bhilr icc1,1 + + set_spr_addr bad,lr + set_icc 0xe 2 + bhilr icc2,2 + + set_spr_addr bad,lr + set_icc 0xf 3 + bhilr icc3,3 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/ble.cgs b/sim/testsuite/sim/frv/ble.cgs new file mode 100644 index 0000000..c358766 --- /dev/null +++ b/sim/testsuite/sim/frv/ble.cgs @@ -0,0 +1,69 @@ +# frv testcase for ble $ICCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global ble +ble: + set_icc 0x0 0 + ble icc0,0,bad + set_icc 0x1 1 + ble icc1,1,bad + set_icc 0x2 2 + ble icc2,2,ok3 + fail +ok3: + set_icc 0x3 3 + ble icc3,3,ok4 + fail +ok4: + set_icc 0x4 0 + ble icc0,0,ok5 + fail +ok5: + set_icc 0x5 1 + ble icc1,1,ok6 + fail +ok6: + set_icc 0x6 2 + ble icc2,2,ok7 + fail +ok7: + set_icc 0x7 3 + ble icc3,3,ok8 + fail +ok8: + set_icc 0x8 0 + ble icc0,0,ok9 + fail +ok9: + set_icc 0x9 1 + ble icc1,1,oka + fail +oka: + set_icc 0xa 2 + ble icc2,2,bad + set_icc 0xb 3 + ble icc3,3,bad + set_icc 0xc 0 + ble icc0,0,okd + fail +okd: + set_icc 0xd 1 + ble icc1,1,oke + fail +oke: + set_icc 0xe 2 + ble icc2,2,okf + fail +okf: + set_icc 0xf 3 + ble icc3,3,okg + fail +okg: + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/blelr.cgs b/sim/testsuite/sim/frv/blelr.cgs new file mode 100644 index 0000000..dbb8e84 --- /dev/null +++ b/sim/testsuite/sim/frv/blelr.cgs @@ -0,0 +1,88 @@ +# frv testcase for blelr $ICCi,$hint +# mach: all + + .include "testutils.inc" + + start + + .global blelr +blelr: + set_spr_addr bad,lr + set_icc 0x0 0 + blelr icc0,0 + + set_spr_addr bad,lr + set_icc 0x1 1 + blelr icc1,1 + + set_spr_addr ok3,lr + set_icc 0x2 2 + blelr icc2,2 + fail +ok3: + set_spr_addr ok4,lr + set_icc 0x3 3 + blelr icc3,3 + fail +ok4: + set_spr_addr ok5,lr + set_icc 0x4 0 + blelr icc0,0 + fail +ok5: + set_spr_addr ok6,lr + set_icc 0x5 1 + blelr icc1,1 + fail +ok6: + set_spr_addr ok7,lr + set_icc 0x6 2 + blelr icc2,2 + fail +ok7: + set_spr_addr ok8,lr + set_icc 0x7 3 + blelr icc3,3 + fail +ok8: + set_spr_addr ok9,lr + set_icc 0x8 0 + blelr icc0,0 + fail +ok9: + set_spr_addr oka,lr + set_icc 0x9 1 + blelr icc1,1 + fail +oka: + set_spr_addr bad,lr + set_icc 0xa 2 + blelr icc2,2 + + set_spr_addr bad,lr + set_icc 0xb 3 + blelr icc3,3 + + set_spr_addr okd,lr + set_icc 0xc 0 + blelr icc0,0 + fail +okd: + set_spr_addr oke,lr + set_icc 0xd 1 + blelr icc1,1 + fail +oke: + set_spr_addr okf,lr + set_icc 0xe 2 + blelr icc2,2 + fail +okf: + set_spr_addr okg,lr + set_icc 0xf 3 + blelr icc3,3 + fail +okg: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/bls.cgs b/sim/testsuite/sim/frv/bls.cgs new file mode 100644 index 0000000..e868de6 --- /dev/null +++ b/sim/testsuite/sim/frv/bls.cgs @@ -0,0 +1,69 @@ +# frv testcase for bls $ICCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global bls +bls: + set_icc 0x0 0 + bls icc0,0,bad + set_icc 0x1 1 + bls icc1,1,ok2 + fail +ok2: + set_icc 0x2 2 + bls icc2,2,bad + set_icc 0x3 3 + bls icc3,3,ok4 + fail +ok4: + set_icc 0x4 0 + bls icc0,0,ok5 + fail +ok5: + set_icc 0x5 1 + bls icc1,1,ok6 + fail +ok6: + set_icc 0x6 2 + bls icc2,2,ok7 + fail +ok7: + set_icc 0x7 3 + bls icc3,3,ok8 + fail +ok8: + set_icc 0x8 0 + bls icc0,0,bad + set_icc 0x9 1 + bls icc1,1,oka + fail +oka: + set_icc 0xa 2 + bls icc2,2,bad + set_icc 0xb 3 + bls icc3,3,okc + fail +okc: + set_icc 0xc 0 + bls icc0,0,okd + fail +okd: + set_icc 0xd 1 + bls icc1,1,oke + fail +oke: + set_icc 0xe 2 + bls icc2,2,okf + fail +okf: + set_icc 0xf 3 + bls icc3,3,okg + fail +okg: + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/blslr.cgs b/sim/testsuite/sim/frv/blslr.cgs new file mode 100644 index 0000000..5166c52 --- /dev/null +++ b/sim/testsuite/sim/frv/blslr.cgs @@ -0,0 +1,88 @@ +# frv testcase for blslr $ICCi,$hint +# mach: all + + .include "testutils.inc" + + start + + .global blslr +blslr: + set_spr_addr bad,lr + set_icc 0x0 0 + blslr icc0,0 + + set_spr_addr ok2,lr + set_icc 0x1 1 + blslr icc1,1 + fail +ok2: + set_spr_addr bad,lr + set_icc 0x2 2 + blslr icc2,2 + + set_spr_addr ok4,lr + set_icc 0x3 3 + blslr icc3,3 + fail +ok4: + set_spr_addr ok5,lr + set_icc 0x4 0 + blslr icc0,0 + fail +ok5: + set_spr_addr ok6,lr + set_icc 0x5 1 + blslr icc1,1 + fail +ok6: + set_spr_addr ok7,lr + set_icc 0x6 2 + blslr icc2,2 + fail +ok7: + set_spr_addr ok8,lr + set_icc 0x7 3 + blslr icc3,3 + fail +ok8: + set_spr_addr bad,lr + set_icc 0x8 0 + blslr icc0,0 + + set_spr_addr oka,lr + set_icc 0x9 1 + blslr icc1,1 + fail +oka: + set_spr_addr bad,lr + set_icc 0xa 2 + blslr icc2,2 + + set_spr_addr okc,lr + set_icc 0xb 3 + blslr icc3,3 + fail +okc: + set_spr_addr okd,lr + set_icc 0xc 0 + blslr icc0,0 + fail +okd: + set_spr_addr oke,lr + set_icc 0xd 1 + blslr icc1,1 + fail +oke: + set_spr_addr okf,lr + set_icc 0xe 2 + blslr icc2,2 + fail +okf: + set_spr_addr okg,lr + set_icc 0xf 3 + blslr icc3,3 + fail +okg: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/blt.cgs b/sim/testsuite/sim/frv/blt.cgs new file mode 100644 index 0000000..639f971 --- /dev/null +++ b/sim/testsuite/sim/frv/blt.cgs @@ -0,0 +1,61 @@ +# frv testcase for blt $ICCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global blt +blt: + set_icc 0x0 0 + blt icc0,0,bad + set_icc 0x1 1 + blt icc1,1,bad + set_icc 0x2 2 + blt icc2,2,ok3 + fail +ok3: + set_icc 0x3 3 + blt icc3,3,ok4 + fail +ok4: + set_icc 0x4 0 + blt icc0,0,bad + set_icc 0x5 1 + blt icc1,1,bad + set_icc 0x6 2 + blt icc2,2,ok7 + fail +ok7: + set_icc 0x7 3 + blt icc3,3,ok8 + fail +ok8: + set_icc 0x8 0 + blt icc0,0,ok9 + fail +ok9: + set_icc 0x9 1 + blt icc1,1,oka + fail +oka: + set_icc 0xa 2 + blt icc2,2,bad + set_icc 0xb 3 + blt icc3,3,bad + set_icc 0xc 0 + blt icc0,0,okd + fail +okd: + set_icc 0xd 1 + blt icc1,1,oke + fail +oke: + set_icc 0xe 2 + blt icc2,2,bad + set_icc 0xf 3 + blt icc3,3,bad + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/bltlr.cgs b/sim/testsuite/sim/frv/bltlr.cgs new file mode 100644 index 0000000..fcf04b5 --- /dev/null +++ b/sim/testsuite/sim/frv/bltlr.cgs @@ -0,0 +1,84 @@ +# frv testcase for bltlr $ICCi,$hint +# mach: all + + .include "testutils.inc" + + start + + .global bltlr +bltlr: + set_spr_addr bad,lr + set_icc 0x0 0 + bltlr icc0,0 + + set_spr_addr bad,lr + set_icc 0x1 1 + bltlr icc1,1 + + set_spr_addr ok3,lr + set_icc 0x2 2 + bltlr icc2,2 + fail +ok3: + set_spr_addr ok4,lr + set_icc 0x3 3 + bltlr icc3,3 + fail +ok4: + set_spr_addr bad,lr + set_icc 0x4 0 + bltlr icc0,0 + + set_spr_addr bad,lr + set_icc 0x5 1 + bltlr icc1,1 + + set_spr_addr ok7,lr + set_icc 0x6 2 + bltlr icc2,2 + fail +ok7: + set_spr_addr ok8,lr + set_icc 0x7 3 + bltlr icc3,3 + fail +ok8: + set_spr_addr ok9,lr + set_icc 0x8 0 + bltlr icc0,0 + fail +ok9: + set_spr_addr oka,lr + set_icc 0x9 1 + bltlr icc1,1 + fail +oka: + set_spr_addr bad,lr + set_icc 0xa 2 + bltlr icc2,2 + + set_spr_addr bad,lr + set_icc 0xb 3 + bltlr icc3,3 + + set_spr_addr okd,lr + set_icc 0xc 0 + bltlr icc0,0 + fail +okd: + set_spr_addr oke,lr + set_icc 0xd 1 + bltlr icc1,1 + fail +oke: + set_spr_addr bad,lr + set_icc 0xe 2 + bltlr icc2,2 + + set_spr_addr bad,lr + set_icc 0xf 3 + bltlr icc3,3 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/bn.cgs b/sim/testsuite/sim/frv/bn.cgs new file mode 100644 index 0000000..e5ff397 --- /dev/null +++ b/sim/testsuite/sim/frv/bn.cgs @@ -0,0 +1,61 @@ +# frv testcase for bn $ICCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global bn +bn: + set_icc 0x0 0 + bn icc0,0,bad + set_icc 0x1 1 + bn icc1,1,bad + set_icc 0x2 2 + bn icc2,2,bad + set_icc 0x3 3 + bn icc3,3,bad + set_icc 0x4 0 + bn icc0,0,bad + set_icc 0x5 1 + bn icc1,1,bad + set_icc 0x6 2 + bn icc2,2,bad + set_icc 0x7 3 + bn icc3,3,bad + set_icc 0x8 0 + bn icc0,0,ok9 + fail +ok9: + set_icc 0x9 1 + bn icc1,1,oka + fail +oka: + set_icc 0xa 2 + bn icc2,2,okb + fail +okb: + set_icc 0xb 3 + bn icc3,3,okc + fail +okc: + set_icc 0xc 0 + bn icc0,0,okd + fail +okd: + set_icc 0xd 1 + bn icc1,1,oke + fail +oke: + set_icc 0xe 2 + bn icc2,2,okf + fail +okf: + set_icc 0xf 3 + bn icc3,3,okg + fail +okg: + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/bnc.cgs b/sim/testsuite/sim/frv/bnc.cgs new file mode 100644 index 0000000..6f14e6c --- /dev/null +++ b/sim/testsuite/sim/frv/bnc.cgs @@ -0,0 +1,61 @@ +# frv testcase for bnc $ICCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global bnc +bnc: + set_icc 0x0 0 + bnc icc0,0,ok1 + fail +ok1: + set_icc 0x1 1 + bnc icc1,1,bad + set_icc 0x2 2 + bnc icc2,2,ok3 + fail +ok3: + set_icc 0x3 3 + bnc icc3,3,bad + set_icc 0x4 0 + bnc icc0,0,ok5 + fail +ok5: + set_icc 0x5 1 + bnc icc1,1,bad + set_icc 0x6 2 + bnc icc2,2,ok7 + fail +ok7: + set_icc 0x7 3 + bnc icc3,3,bad + set_icc 0x8 0 + bnc icc0,0,ok9 + fail +ok9: + set_icc 0x9 1 + bnc icc1,1,bad + set_icc 0xa 2 + bnc icc2,2,okb + fail +okb: + set_icc 0xb 3 + bnc icc3,3,bad + set_icc 0xc 0 + bnc icc0,0,okd + fail +okd: + set_icc 0xd 1 + bnc icc1,1,bad + set_icc 0xe 2 + bnc icc2,2,okf + fail +okf: + set_icc 0xf 3 + bnc icc3,3,bad + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/bnclr.cgs b/sim/testsuite/sim/frv/bnclr.cgs new file mode 100644 index 0000000..d24f8eb --- /dev/null +++ b/sim/testsuite/sim/frv/bnclr.cgs @@ -0,0 +1,84 @@ +# frv testcase for bnclr $ICCi,$hint +# mach: all + + .include "testutils.inc" + + start + + .global bnclr +bnclr: + set_spr_addr ok1,lr + set_icc 0x0 0 + bnclr icc0,0 + fail +ok1: + set_spr_addr bad,lr + set_icc 0x1 1 + bnclr icc1,1 + + set_spr_addr ok3,lr + set_icc 0x2 2 + bnclr icc2,2 + fail +ok3: + set_spr_addr bad,lr + set_icc 0x3 3 + bnclr icc3,3 + + set_spr_addr ok5,lr + set_icc 0x4 0 + bnclr icc0,0 + fail +ok5: + set_spr_addr bad,lr + set_icc 0x5 1 + bnclr icc1,1 + + set_spr_addr ok7,lr + set_icc 0x6 2 + bnclr icc2,2 + fail +ok7: + set_spr_addr bad,lr + set_icc 0x7 3 + bnclr icc3,3 + + set_spr_addr ok9,lr + set_icc 0x8 0 + bnclr icc0,0 + fail +ok9: + set_spr_addr bad,lr + set_icc 0x9 1 + bnclr icc1,1 + + set_spr_addr okb,lr + set_icc 0xa 2 + bnclr icc2,2 + fail +okb: + set_spr_addr bad,lr + set_icc 0xb 3 + bnclr icc3,3 + + set_spr_addr okd,lr + set_icc 0xc 0 + bnclr icc0,0 + fail +okd: + set_spr_addr bad,lr + set_icc 0xd 1 + bnclr icc1,1 + + set_spr_addr okf,lr + set_icc 0xe 2 + bnclr icc2,2 + fail +okf: + set_spr_addr bad,lr + set_icc 0xf 3 + bnclr icc3,3 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/bne.cgs b/sim/testsuite/sim/frv/bne.cgs new file mode 100644 index 0000000..f0f0894 --- /dev/null +++ b/sim/testsuite/sim/frv/bne.cgs @@ -0,0 +1,61 @@ +# frv testcase for bne $ICCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global bne +bne: + set_icc 0x0 0 + bne icc0,0,ok1 + fail +ok1: + set_icc 0x1 1 + bne icc1,1,ok2 + fail +ok2: + set_icc 0x2 2 + bne icc2,2,ok3 + fail +ok3: + set_icc 0x3 3 + bne icc3,3,ok4 + fail +ok4: + set_icc 0x4 0 + bne icc0,0,bad + set_icc 0x5 1 + bne icc1,1,bad + set_icc 0x6 2 + bne icc2,2,bad + set_icc 0x7 3 + bne icc3,3,bad + set_icc 0x8 0 + bne icc0,0,ok9 + fail +ok9: + set_icc 0x9 1 + bne icc1,1,oka + fail +oka: + set_icc 0xa 2 + bne icc2,2,okb + fail +okb: + set_icc 0xb 3 + bne icc3,3,okc + fail +okc: + set_icc 0xc 0 + bne icc0,0,bad + set_icc 0xd 1 + bne icc1,1,bad + set_icc 0xe 2 + bne icc2,2,bad + set_icc 0xf 3 + bne icc3,3,bad + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/bnelr.cgs b/sim/testsuite/sim/frv/bnelr.cgs new file mode 100644 index 0000000..7a477b8 --- /dev/null +++ b/sim/testsuite/sim/frv/bnelr.cgs @@ -0,0 +1,84 @@ +# frv testcase for bnelr $ICCi,$hint +# mach: all + + .include "testutils.inc" + + start + + .global bnelr +bnelr: + set_spr_addr ok1,lr + set_icc 0x0 0 + bnelr icc0,0 + fail +ok1: + set_spr_addr ok2,lr + set_icc 0x1 1 + bnelr icc1,1 + fail +ok2: + set_spr_addr ok3,lr + set_icc 0x2 2 + bnelr icc2,2 + fail +ok3: + set_spr_addr ok4,lr + set_icc 0x3 3 + bnelr icc3,3 + fail +ok4: + set_spr_addr bad,lr + set_icc 0x4 0 + bnelr icc0,0 + + set_spr_addr bad,lr + set_icc 0x5 1 + bnelr icc1,1 + + set_spr_addr bad,lr + set_icc 0x6 2 + bnelr icc2,2 + + set_spr_addr bad,lr + set_icc 0x7 3 + bnelr icc3,3 + + set_spr_addr ok9,lr + set_icc 0x8 0 + bnelr icc0,0 + fail +ok9: + set_spr_addr oka,lr + set_icc 0x9 1 + bnelr icc1,1 + fail +oka: + set_spr_addr okb,lr + set_icc 0xa 2 + bnelr icc2,2 + fail +okb: + set_spr_addr okc,lr + set_icc 0xb 3 + bnelr icc3,3 + fail +okc: + set_spr_addr bad,lr + set_icc 0xc 0 + bnelr icc0,0 + + set_spr_addr bad,lr + set_icc 0xd 1 + bnelr icc1,1 + + set_spr_addr bad,lr + set_icc 0xe 2 + bnelr icc2,2 + + set_spr_addr bad,lr + set_icc 0xf 3 + bnelr icc3,3 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/bnlr.cgs b/sim/testsuite/sim/frv/bnlr.cgs new file mode 100644 index 0000000..de32b05 --- /dev/null +++ b/sim/testsuite/sim/frv/bnlr.cgs @@ -0,0 +1,84 @@ +# frv testcase for bnlr $ICCi,$hint +# mach: all + + .include "testutils.inc" + + start + + .global bnlr +bnlr: + set_spr_addr bad,lr + set_icc 0x0 0 + bnlr icc0,0 + + set_spr_addr bad,lr + set_icc 0x1 1 + bnlr icc1,1 + + set_spr_addr bad,lr + set_icc 0x2 2 + bnlr icc2,2 + + set_spr_addr bad,lr + set_icc 0x3 3 + bnlr icc3,3 + + set_spr_addr bad,lr + set_icc 0x4 0 + bnlr icc0,0 + + set_spr_addr bad,lr + set_icc 0x5 1 + bnlr icc1,1 + + set_spr_addr bad,lr + set_icc 0x6 2 + bnlr icc2,2 + + set_spr_addr bad,lr + set_icc 0x7 3 + bnlr icc3,3 + + set_spr_addr ok9,lr + set_icc 0x8 0 + bnlr icc0,0 + fail +ok9: + set_spr_addr oka,lr + set_icc 0x9 1 + bnlr icc1,1 + fail +oka: + set_spr_addr okb,lr + set_icc 0xa 2 + bnlr icc2,2 + fail +okb: + set_spr_addr okc,lr + set_icc 0xb 3 + bnlr icc3,3 + fail +okc: + set_spr_addr okd,lr + set_icc 0xc 0 + bnlr icc0,0 + fail +okd: + set_spr_addr oke,lr + set_icc 0xd 1 + bnlr icc1,1 + fail +oke: + set_spr_addr okf,lr + set_icc 0xe 2 + bnlr icc2,2 + fail +okf: + set_spr_addr okg,lr + set_icc 0xf 3 + bnlr icc3,3 + fail +okg: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/bno.cgs b/sim/testsuite/sim/frv/bno.cgs new file mode 100644 index 0000000..005e422 --- /dev/null +++ b/sim/testsuite/sim/frv/bno.cgs @@ -0,0 +1,45 @@ +# frv testcase for bno $ICCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global bno +bno: + set_icc 0x0 0 + bno + set_icc 0x1 1 + bno + set_icc 0x2 2 + bno + set_icc 0x3 3 + bno + set_icc 0x4 0 + bno + set_icc 0x5 1 + bno + set_icc 0x6 2 + bno + set_icc 0x7 3 + bno + set_icc 0x8 0 + bno + set_icc 0x9 1 + bno + set_icc 0xa 2 + bno + set_icc 0xb 3 + bno + set_icc 0xc 0 + bno + set_icc 0xd 1 + bno + set_icc 0xe 2 + bno + set_icc 0xf 3 + bno + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/bnolr.cgs b/sim/testsuite/sim/frv/bnolr.cgs new file mode 100644 index 0000000..ae69f6f --- /dev/null +++ b/sim/testsuite/sim/frv/bnolr.cgs @@ -0,0 +1,61 @@ +# frv testcase for bnolr +# mach: all + + .include "testutils.inc" + + start + + .global bnolr +bnolr: + set_spr_addr bad,lr + set_icc 0x0 0 + bnolr + + set_icc 0x1 1 + bnolr + + set_icc 0x2 2 + bnolr + + set_icc 0x3 3 + bnolr + + set_icc 0x4 0 + bnolr + + set_icc 0x5 1 + bnolr + + set_icc 0x6 2 + bnolr + + set_icc 0x7 3 + bnolr + + set_icc 0x8 0 + bnolr + + set_icc 0x9 1 + bnolr + + set_icc 0xa 2 + bnolr + + set_icc 0xb 3 + bnolr + + set_icc 0xc 0 + bnolr + + set_icc 0xd 1 + bnolr + + set_icc 0xe 2 + bnolr + + set_icc 0xf 3 + bnolr + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/bnv.cgs b/sim/testsuite/sim/frv/bnv.cgs new file mode 100644 index 0000000..29ec57a --- /dev/null +++ b/sim/testsuite/sim/frv/bnv.cgs @@ -0,0 +1,61 @@ +# frv testcase for bnv $ICCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global bnv +bnv: + set_icc 0x0 0 + bnv icc0,0,ok1 + fail +ok1: + set_icc 0x1 1 + bnv icc1,1,ok2 + fail +ok2: + set_icc 0x2 2 + bnv icc2,2,bad + set_icc 0x3 3 + bnv icc3,3,bad + set_icc 0x4 0 + bnv icc0,0,ok5 + fail +ok5: + set_icc 0x5 1 + bnv icc1,1,ok6 + fail +ok6: + set_icc 0x6 2 + bnv icc2,2,bad + set_icc 0x7 3 + bnv icc3,3,bad + set_icc 0x8 0 + bnv icc0,0,ok9 + fail +ok9: + set_icc 0x9 1 + bnv icc1,1,oka + fail +oka: + set_icc 0xa 2 + bnv icc2,2,bad + set_icc 0xb 3 + bnv icc3,3,bad + set_icc 0xc 0 + bnv icc0,0,okd + fail +okd: + set_icc 0xd 1 + bnv icc1,1,oke + fail +oke: + set_icc 0xe 2 + bnv icc2,2,bad + set_icc 0xf 3 + bnv icc3,3,bad + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/bnvlr.cgs b/sim/testsuite/sim/frv/bnvlr.cgs new file mode 100644 index 0000000..de40f9c --- /dev/null +++ b/sim/testsuite/sim/frv/bnvlr.cgs @@ -0,0 +1,84 @@ +# frv testcase for bnvlr $ICCi,$hint +# mach: all + + .include "testutils.inc" + + start + + .global bnvlr +bnvlr: + set_spr_addr ok1,lr + set_icc 0x0 0 + bnvlr icc0,0 + fail +ok1: + set_spr_addr ok2,lr + set_icc 0x1 1 + bnvlr icc1,1 + fail +ok2: + set_spr_addr bad,lr + set_icc 0x2 2 + bnvlr icc2,2 + + set_spr_addr bad,lr + set_icc 0x3 3 + bnvlr icc3,3 + + set_spr_addr ok5,lr + set_icc 0x4 0 + bnvlr icc0,0 + fail +ok5: + set_spr_addr ok6,lr + set_icc 0x5 1 + bnvlr icc1,1 + fail +ok6: + set_spr_addr bad,lr + set_icc 0x6 2 + bnvlr icc2,2 + + set_spr_addr bad,lr + set_icc 0x7 3 + bnvlr icc3,3 + + set_spr_addr ok9,lr + set_icc 0x8 0 + bnvlr icc0,0 + fail +ok9: + set_spr_addr oka,lr + set_icc 0x9 1 + bnvlr icc1,1 + fail +oka: + set_spr_addr bad,lr + set_icc 0xa 2 + bnvlr icc2,2 + + set_spr_addr bad,lr + set_icc 0xb 3 + bnvlr icc3,3 + + set_spr_addr okd,lr + set_icc 0xc 0 + bnvlr icc0,0 + fail +okd: + set_spr_addr oke,lr + set_icc 0xd 1 + bnvlr icc1,1 + fail +oke: + set_spr_addr bad,lr + set_icc 0xe 2 + bnvlr icc2,2 + + set_spr_addr bad,lr + set_icc 0xf 3 + bnvlr icc3,3 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/bp.cgs b/sim/testsuite/sim/frv/bp.cgs new file mode 100644 index 0000000..0bc1e7f --- /dev/null +++ b/sim/testsuite/sim/frv/bp.cgs @@ -0,0 +1,61 @@ +# frv testcase for bp $ICCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global bp +bp: + set_icc 0x0 0 + bp icc0,0,ok1 + fail +ok1: + set_icc 0x1 1 + bp icc1,1,ok2 + fail +ok2: + set_icc 0x2 2 + bp icc2,2,ok3 + fail +ok3: + set_icc 0x3 3 + bp icc3,3,ok4 + fail +ok4: + set_icc 0x4 0 + bp icc0,0,ok5 + fail +ok5: + set_icc 0x5 1 + bp icc1,1,ok6 + fail +ok6: + set_icc 0x6 2 + bp icc2,2,ok7 + fail +ok7: + set_icc 0x7 3 + bp icc3,3,ok8 + fail +ok8: + set_icc 0x8 0 + bp icc0,0,bad + set_icc 0x9 1 + bp icc1,1,bad + set_icc 0xa 2 + bp icc2,2,bad + set_icc 0xb 3 + bp icc3,3,bad + set_icc 0xc 0 + bp icc0,0,bad + set_icc 0xd 1 + bp icc1,1,bad + set_icc 0xe 2 + bp icc2,2,bad + set_icc 0xf 3 + bp icc3,3,bad + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/bplr.cgs b/sim/testsuite/sim/frv/bplr.cgs new file mode 100644 index 0000000..2bd9bb6 --- /dev/null +++ b/sim/testsuite/sim/frv/bplr.cgs @@ -0,0 +1,84 @@ +# frv testcase for bplr $ICCi,$hint +# mach: all + + .include "testutils.inc" + + start + + .global bplr +bplr: + set_spr_addr ok1,lr + set_icc 0x0 0 + bplr icc0,0 + fail +ok1: + set_spr_addr ok2,lr + set_icc 0x1 1 + bplr icc1,1 + fail +ok2: + set_spr_addr ok3,lr + set_icc 0x2 2 + bplr icc2,2 + fail +ok3: + set_spr_addr ok4,lr + set_icc 0x3 3 + bplr icc3,3 + fail +ok4: + set_spr_addr ok5,lr + set_icc 0x4 0 + bplr icc0,0 + fail +ok5: + set_spr_addr ok6,lr + set_icc 0x5 1 + bplr icc1,1 + fail +ok6: + set_spr_addr ok7,lr + set_icc 0x6 2 + bplr icc2,2 + fail +ok7: + set_spr_addr ok8,lr + set_icc 0x7 3 + bplr icc3,3 + fail +ok8: + set_spr_addr bad,lr + set_icc 0x8 0 + bplr icc0,0 + + set_spr_addr bad,lr + set_icc 0x9 1 + bplr icc1,1 + + set_spr_addr bad,lr + set_icc 0xa 2 + bplr icc2,2 + + set_spr_addr bad,lr + set_icc 0xb 3 + bplr icc3,3 + + set_spr_addr bad,lr + set_icc 0xc 0 + bplr icc0,0 + + set_spr_addr bad,lr + set_icc 0xd 1 + bplr icc1,1 + + set_spr_addr bad,lr + set_icc 0xe 2 + bplr icc2,2 + + set_spr_addr bad,lr + set_icc 0xf 3 + bplr icc3,3 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/bra.cgs b/sim/testsuite/sim/frv/bra.cgs new file mode 100644 index 0000000..e6b312b --- /dev/null +++ b/sim/testsuite/sim/frv/bra.cgs @@ -0,0 +1,75 @@ +# frv testcase for bra $ICCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global bra +bra: + set_icc 0x0 0 + bra ok1 + fail +ok1: + set_icc 0x1 1 + bra ok2 + fail +ok2: + set_icc 0x2 2 + bra ok3 + fail +ok3: + set_icc 0x3 3 + bra ok4 + fail +ok4: + set_icc 0x4 0 + bra ok5 + fail +ok5: + set_icc 0x5 1 + bra ok6 + fail +ok6: + set_icc 0x6 2 + bra ok7 + fail +ok7: + set_icc 0x7 3 + bra ok8 + fail +ok8: + set_icc 0x8 0 + bra ok9 + fail +ok9: + set_icc 0x9 1 + bra oka + fail +oka: + set_icc 0xa 2 + bra okb + fail +okb: + set_icc 0xb 3 + bra okc + fail +okc: + set_icc 0xc 0 + bra okd + fail +okd: + set_icc 0xd 1 + bra oke + fail +oke: + set_icc 0xe 2 + bra okf + fail +okf: + set_icc 0xf 3 + bra okg + fail +okg: + + pass diff --git a/sim/testsuite/sim/frv/bralr.cgs b/sim/testsuite/sim/frv/bralr.cgs new file mode 100644 index 0000000..3928209 --- /dev/null +++ b/sim/testsuite/sim/frv/bralr.cgs @@ -0,0 +1,91 @@ +# frv testcase for bralr +# mach: all + + .include "testutils.inc" + + start + + .global bralr +bralr: + set_spr_addr ok1,lr + set_icc 0x0 0 + bralr + fail +ok1: + set_spr_addr ok2,lr + set_icc 0x1 1 + bralr + fail +ok2: + set_spr_addr ok3,lr + set_icc 0x2 2 + bralr + fail +ok3: + set_spr_addr ok4,lr + set_icc 0x3 3 + bralr + fail +ok4: + set_spr_addr ok5,lr + set_icc 0x4 0 + bralr + fail +ok5: + set_spr_addr ok6,lr + set_icc 0x5 1 + bralr + fail +ok6: + set_spr_addr ok7,lr + set_icc 0x6 2 + bralr + fail +ok7: + set_spr_addr ok8,lr + set_icc 0x7 3 + bralr + fail +ok8: + set_spr_addr ok9,lr + set_icc 0x8 0 + bralr + fail +ok9: + set_spr_addr oka,lr + set_icc 0x9 1 + bralr + fail +oka: + set_spr_addr okb,lr + set_icc 0xa 2 + bralr + fail +okb: + set_spr_addr okc,lr + set_icc 0xb 3 + bralr + fail +okc: + set_spr_addr okd,lr + set_icc 0xc 0 + bralr + fail +okd: + set_spr_addr oke,lr + set_icc 0xd 1 + bralr + fail +oke: + set_spr_addr okf,lr + set_icc 0xe 2 + bralr + fail +okf: + set_spr_addr okg,lr + set_icc 0xf 3 + bralr + fail +okg: + + pass diff --git a/sim/testsuite/sim/frv/branch.pcgs b/sim/testsuite/sim/frv/branch.pcgs new file mode 100644 index 0000000..013b0ba --- /dev/null +++ b/sim/testsuite/sim/frv/branch.pcgs @@ -0,0 +1,63 @@ +# frv parallel testcase for branching +# mach: fr500 fr550 frv + + .include "testutils.inc" + + start + + .global branch +branch: ; All insns in VLIW execute + setlos.p 1,gr1 + setlos 0,gr2 + setlos.p 0,gr3 + bra ok1 + setlos.p 2,gr2 + setlos 3,gr3 + fail +ok1: + test_gr_immed 1,gr1 + test_gr_immed 0,gr2 + test_gr_immed 0,gr3 + + ; 1st branch is taken + bra.p ok5 + bra ok4 + bra.p ok3 + bra ok2 + fail +ok2: + fail +ok3: + fail +ok4: + fail +ok5: + ; 1st true branch is taken + set_icc 0x4 1 + bne.p icc1,1,ok6 + blt icc1,1,ok7 + beq.p icc1,1,ok9 + ble icc1,1,ok8 + fail +ok6: + fail +ok7: + fail +ok8: + fail +ok9: + ; combination of the above + set_icc 0x4 1 + setlos.p 4,gr4 + setlos.p 0,gr5 + bne.p icc1,1,oka + beq icc1,1,okb + setlos 5,gr5 + fail +oka: + fail +okb: + test_gr_immed 4,gr4 + test_gr_immed 0,gr5 + + pass diff --git a/sim/testsuite/sim/frv/break.cgs b/sim/testsuite/sim/frv/break.cgs new file mode 100644 index 0000000..b2a61a0 --- /dev/null +++ b/sim/testsuite/sim/frv/break.cgs @@ -0,0 +1,58 @@ +# FRV testcase for break +# mach: all + + .include "testutils.inc" + + start + + .global tra +tra: + ; Can't test break anymore in the user environment because it is the + ; debugger's breakpoint insn. Just pass this test for now. + pass + + + + + + set_gr_spr tbr,gr7 + and_gr_immed -4081,gr7 ; clear tbr.tt + inc_gr_immed 0xff0,gr7 ; break handler + set_bctrlr_0_0 gr7 + set_spr_immed 128,lcr + + test_spr_bits 0x4,2,0x1,psr ; psr.s is set + test_spr_bits 0x1,0,0x0,psr ; psr.et is clear + set_spr_addr ok1,lr + break +ret: + or_spr_immed 0x00000001,psr ; turn on psr.et + and_spr_immed 0xfffffffb,psr ; turn off psr.s + test_spr_bits 0x4,2,0x0,psr ; psr.s is clear + test_spr_bits 0x1,0,0x1,psr ; psr.et is set + set_spr_addr ok0,lr + break +ret1: + test_spr_bits 0x4,2,0x0,psr ; psr.s is clear + test_spr_bits 0x1,0,0x1,psr ; psr.et is set + pass + + ; check interrupt for second break +ok0: test_spr_addr ret1,bpcsr + test_spr_bits 0x1000,12,0x0,bpsr ; bpsr.bs is clear + test_spr_bits 0x0001,0,0x1,bpsr ; bpsr.et is set + test_spr_bits 0x4,2,0x1,psr ; psr.s is set + test_spr_bits 0x1,0,0x0,psr ; psr.et is clear + rett 0 ; nop + rett 1 + + ; check interrupt for first break +ok1: test_spr_addr ret,bpcsr + test_spr_bits 0x1000,12,0x1,bpsr ; bpsr.bs is set + test_spr_bits 0x0001,0,0x0,bpsr ; bpsr.et is clear + test_spr_bits 0x4,2,0x1,psr ; psr.s is set + test_spr_bits 0x1,0,0x0,psr ; psr.et is clear + rett 0 ; nop + rett 1 + + diff --git a/sim/testsuite/sim/frv/bv.cgs b/sim/testsuite/sim/frv/bv.cgs new file mode 100644 index 0000000..e2f8174 --- /dev/null +++ b/sim/testsuite/sim/frv/bv.cgs @@ -0,0 +1,61 @@ +# frv testcase for bv $ICCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global bv +bv: + set_icc 0x0 0 + bv icc0,0,bad + set_icc 0x1 1 + bv icc1,1,bad + set_icc 0x2 2 + bv icc2,2,ok3 + fail +ok3: + set_icc 0x3 3 + bv icc3,3,ok4 + fail +ok4: + set_icc 0x4 0 + bv icc0,0,bad + set_icc 0x5 1 + bv icc1,1,bad + set_icc 0x6 2 + bv icc2,2,ok7 + fail +ok7: + set_icc 0x7 3 + bv icc3,3,ok8 + fail +ok8: + set_icc 0x8 0 + bv icc0,0,bad + set_icc 0x9 1 + bv icc1,1,bad + set_icc 0xa 2 + bv icc2,2,okb + fail +okb: + set_icc 0xb 3 + bv icc3,3,okc + fail +okc: + set_icc 0xc 0 + bv icc0,0,bad + set_icc 0xd 1 + bv icc1,1,bad + set_icc 0xe 2 + bv icc2,2,okf + fail +okf: + set_icc 0xf 3 + bv icc3,3,okg + fail +okg: + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/bvlr.cgs b/sim/testsuite/sim/frv/bvlr.cgs new file mode 100644 index 0000000..b7ba9d8 --- /dev/null +++ b/sim/testsuite/sim/frv/bvlr.cgs @@ -0,0 +1,84 @@ +# frv testcase for bvlr $ICCi,$hint +# mach: all + + .include "testutils.inc" + + start + + .global bvlr +bvlr: + set_spr_addr bad,lr + set_icc 0x0 0 + bvlr icc0,0 + + set_spr_addr bad,lr + set_icc 0x1 1 + bvlr icc1,1 + + set_spr_addr ok3,lr + set_icc 0x2 2 + bvlr icc2,2 + fail +ok3: + set_spr_addr ok4,lr + set_icc 0x3 3 + bvlr icc3,3 + fail +ok4: + set_spr_addr bad,lr + set_icc 0x4 0 + bvlr icc0,0 + + set_spr_addr bad,lr + set_icc 0x5 1 + bvlr icc1,1 + + set_spr_addr ok7,lr + set_icc 0x6 2 + bvlr icc2,2 + fail +ok7: + set_spr_addr ok8,lr + set_icc 0x7 3 + bvlr icc3,3 + fail +ok8: + set_spr_addr bad,lr + set_icc 0x8 0 + bvlr icc0,0 + + set_spr_addr bad,lr + set_icc 0x9 1 + bvlr icc1,1 + + set_spr_addr okb,lr + set_icc 0xa 2 + bvlr icc2,2 + fail +okb: + set_spr_addr okc,lr + set_icc 0xb 3 + bvlr icc3,3 + fail +okc: + set_spr_addr bad,lr + set_icc 0xc 0 + bvlr icc0,0 + + set_spr_addr bad,lr + set_icc 0xd 1 + bvlr icc1,1 + + set_spr_addr okf,lr + set_icc 0xe 2 + bvlr icc2,2 + fail +okf: + set_spr_addr okg,lr + set_icc 0xf 3 + bvlr icc3,3 + fail +okg: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/cadd.cgs b/sim/testsuite/sim/frv/cadd.cgs new file mode 100644 index 0000000..291b8fb --- /dev/null +++ b/sim/testsuite/sim/frv/cadd.cgs @@ -0,0 +1,90 @@ +# frv testcase for cadd $GRi,$GRj,$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cadd +cadd: + set_spr_immed 0x1b1b,cccr + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + cadd gr7,gr8,gr8,cc4,1 + test_gr_immed 3,gr8 + + set_gr_limmed 0x7fff,0xffff,gr7 + set_gr_immed 1,gr8 + cadd gr7,gr8,gr8,cc4,1 + test_gr_limmed 0x8000,0x0000,gr8 + + cadd gr8,gr8,gr8,cc4,1 + test_gr_immed 0,gr8 + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + cadd gr7,gr8,gr8,cc4,0 + test_gr_immed 2,gr8 + + set_gr_limmed 0x7fff,0xffff,gr7 + set_gr_immed 1,gr8 + cadd gr7,gr8,gr8,cc4,0 + test_gr_immed 1,gr8 + + cadd gr8,gr8,gr8,cc4,0 + test_gr_immed 1,gr8 + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + cadd gr7,gr8,gr8,cc5,0 + test_gr_immed 3,gr8 + + set_gr_limmed 0x7fff,0xffff,gr7 + set_gr_immed 1,gr8 + cadd gr7,gr8,gr8,cc5,0 + test_gr_limmed 0x8000,0x0000,gr8 + + cadd gr8,gr8,gr8,cc5,0 + test_gr_immed 0,gr8 + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + cadd gr7,gr8,gr8,cc5,1 + test_gr_immed 2,gr8 + + set_gr_limmed 0x7fff,0xffff,gr7 + set_gr_immed 1,gr8 + cadd gr7,gr8,gr8,cc5,1 + test_gr_immed 1,gr8 + + cadd gr8,gr8,gr8,cc5,1 + test_gr_immed 1,gr8 + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + cadd gr7,gr8,gr8,cc6,1 + test_gr_immed 2,gr8 + + set_gr_limmed 0x7fff,0xffff,gr7 + set_gr_immed 1,gr8 + cadd gr7,gr8,gr8,cc6,0 + test_gr_immed 1,gr8 + + cadd gr8,gr8,gr8,cc6,1 + test_gr_immed 1,gr8 + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + cadd gr7,gr8,gr8,cc7,0 + test_gr_immed 2,gr8 + + set_gr_limmed 0x7fff,0xffff,gr7 + set_gr_immed 1,gr8 + cadd gr7,gr8,gr8,cc7,1 + test_gr_immed 1,gr8 + + cadd gr8,gr8,gr8,cc7,0 + test_gr_immed 1,gr8 + + pass diff --git a/sim/testsuite/sim/frv/caddcc.cgs b/sim/testsuite/sim/frv/caddcc.cgs new file mode 100644 index 0000000..ddfd41e --- /dev/null +++ b/sim/testsuite/sim/frv/caddcc.cgs @@ -0,0 +1,163 @@ +# frv testcase for caddcc $GRi,$GRj,$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global caddcc +caddcc: + set_spr_immed 0x1b1b,cccr + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + caddcc gr7,gr8,gr8,cc0,1 + test_icc 0 0 0 0 icc0 + test_gr_immed 3,gr8 + + set_gr_limmed 0x7fff,0xffff,gr7 + set_gr_immed 1,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + caddcc gr7,gr8,gr8,cc0,1 + test_icc 1 0 1 0 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_icc 0x08,0 ; Set mask opposite of expected + caddcc gr8,gr8,gr8,cc4,1 + test_icc 0 1 1 1 icc0 + test_gr_immed 0,gr8 + + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x08,0 ; Set mask opposite of expected + caddcc gr8,gr8,gr8,cc4,1; test zero, carry and overflow bits + test_icc 0 1 1 1 icc0 + test_gr_immed 0,gr8 + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + caddcc gr7,gr8,gr8,cc0,0 + test_icc 1 1 1 1 icc0 + test_gr_immed 2,gr8 + + set_gr_limmed 0x7fff,0xffff,gr7 + set_gr_immed 1,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + caddcc gr7,gr8,gr8,cc0,0 + test_icc 0 1 0 1 icc0 + test_gr_immed 1,gr8 + + set_icc 0x08,0 ; Set mask opposite of expected + caddcc gr8,gr8,gr8,cc4,0 + test_icc 1 0 0 0 icc0 + test_gr_immed 1,gr8 + + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x08,0 ; Set mask opposite of expected + caddcc gr8,gr8,gr8,cc4,0; test zero, carry and overflow bits + test_icc 1 0 0 0 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + set_icc 0x0f,1 ; Set mask opposite of expected + caddcc gr7,gr8,gr8,cc1,0 + test_icc 0 0 0 0 icc1 + test_gr_immed 3,gr8 + + set_gr_limmed 0x7fff,0xffff,gr7 + set_gr_immed 1,gr8 + set_icc 0x05,1 ; Set mask opposite of expected + caddcc gr7,gr8,gr8,cc1,0 + test_icc 1 0 1 0 icc1 + test_gr_limmed 0x8000,0x0000,gr8 + + set_icc 0x08,1 ; Set mask opposite of expected + caddcc gr8,gr8,gr8,cc5,0 + test_icc 0 1 1 1 icc1 + test_gr_immed 0,gr8 + + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x08,1 ; Set mask opposite of expected + caddcc gr8,gr8,gr8,cc5,0; test zero, carry and overflow bits + test_icc 0 1 1 1 icc1 + test_gr_immed 0,gr8 + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + set_icc 0x0f,1 ; Set mask opposite of expected + caddcc gr7,gr8,gr8,cc1,1 + test_icc 1 1 1 1 icc1 + test_gr_immed 2,gr8 + + set_gr_limmed 0x7fff,0xffff,gr7 + set_gr_immed 1,gr8 + set_icc 0x05,1 ; Set mask opposite of expected + caddcc gr7,gr8,gr8,cc1,1 + test_icc 0 1 0 1 icc1 + test_gr_immed 1,gr8 + + set_icc 0x08,1 ; Set mask opposite of expected + caddcc gr8,gr8,gr8,cc5,1 + test_icc 1 0 0 0 icc1 + test_gr_immed 1,gr8 + + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x08,1 ; Set mask opposite of expected + caddcc gr8,gr8,gr8,cc5,1; test zero, carry and overflow bits + test_icc 1 0 0 0 icc1 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + set_icc 0x0f,2 ; Set mask opposite of expected + caddcc gr7,gr8,gr8,cc2,0 + test_icc 1 1 1 1 icc2 + test_gr_immed 2,gr8 + + set_gr_limmed 0x7fff,0xffff,gr7 + set_gr_immed 1,gr8 + set_icc 0x05,2 ; Set mask opposite of expected + caddcc gr7,gr8,gr8,cc2,0 + test_icc 0 1 0 1 icc2 + test_gr_immed 1,gr8 + + set_icc 0x08,2 ; Set mask opposite of expected + caddcc gr8,gr8,gr8,cc6,1 + test_icc 1 0 0 0 icc2 + test_gr_immed 1,gr8 + + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x08,2 ; Set mask opposite of expected + caddcc gr8,gr8,gr8,cc6,1; test zero, carry and overflow bits + test_icc 1 0 0 0 icc2 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + set_icc 0x0f,3 ; Set mask opposite of expected + caddcc gr7,gr8,gr8,cc3,0 + test_icc 1 1 1 1 icc3 + test_gr_immed 2,gr8 + + set_gr_limmed 0x7fff,0xffff,gr7 + set_gr_immed 1,gr8 + set_icc 0x05,3 ; Set mask opposite of expected + caddcc gr7,gr8,gr8,cc3,0 + test_icc 0 1 0 1 icc3 + test_gr_immed 1,gr8 + + set_icc 0x08,3 ; Set mask opposite of expected + caddcc gr8,gr8,gr8,cc7,1 + test_icc 1 0 0 0 icc3 + test_gr_immed 1,gr8 + + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x08,3 ; Set mask opposite of expected + caddcc gr8,gr8,gr8,cc7,1; test zero, carry and overflow bits + test_icc 1 0 0 0 icc3 + test_gr_limmed 0x8000,0x0000,gr8 + + + pass diff --git a/sim/testsuite/sim/frv/call.cgs b/sim/testsuite/sim/frv/call.cgs new file mode 100644 index 0000000..5f0d767 --- /dev/null +++ b/sim/testsuite/sim/frv/call.cgs @@ -0,0 +1,17 @@ +# frv testcase for call $label24 +# mach: all + + .include "testutils.inc" + + start + + .global call +call: + set_spr_immed 0,lr + call ok1 +bad1: + fail +ok1: + test_spr_addr bad1,lr + + pass diff --git a/sim/testsuite/sim/frv/call.pcgs b/sim/testsuite/sim/frv/call.pcgs new file mode 100644 index 0000000..7f452c6 --- /dev/null +++ b/sim/testsuite/sim/frv/call.pcgs @@ -0,0 +1,30 @@ +# frv parallel testcase for call $label24 +# mach: fr500 fr550 frv + + .include "testutils.inc" + + start + + .global call +call: + set_spr_immed 0,lr + call ok1 +bad1: + fail +ok1: + test_spr_addr bad1,lr + + set_spr_immed 0,lr + setlos.p 0,gr5 + call.p ok2 + bra bad3 +bad2: + setlos 5,gr5 + fail +bad3: + fail +ok2: + test_spr_addr bad2,lr + test_gr_immed 0,gr5 + + pass diff --git a/sim/testsuite/sim/frv/callil.cgs b/sim/testsuite/sim/frv/callil.cgs new file mode 100644 index 0000000..eac63e8 --- /dev/null +++ b/sim/testsuite/sim/frv/callil.cgs @@ -0,0 +1,26 @@ +# frv testcase for callil @($GRi,$d12),$LI +# mach: all + + .include "testutils.inc" + + start + + .global callil +callil: + set_gr_addr ok2,gr8 + inc_gr_immed -2047,gr8 + callil @(gr8,0x7ff) +bad2: + fail +ok2: + test_spr_addr bad2,lr + + set_gr_addr ok3,gr8 + inc_gr_immed 2048,gr8 + callil @(gr8,-2048) +bad3: + fail +ok3: + test_spr_addr bad3,lr + + pass diff --git a/sim/testsuite/sim/frv/calll.cgs b/sim/testsuite/sim/frv/calll.cgs new file mode 100644 index 0000000..eee73bc --- /dev/null +++ b/sim/testsuite/sim/frv/calll.cgs @@ -0,0 +1,28 @@ +# frv testcase for calll @($GRi,$GRj) +# mach: all + + .include "testutils.inc" + + start + + .global calll +calll: + set_gr_addr ok2,gr8 + inc_gr_immed -4,gr8 + inc_gr_immed 4,gr9 + calll @(gr8,gr9) +bad2: + fail +ok2: + test_spr_addr bad2,lr + + set_gr_addr ok3,gr8 + inc_gr_immed 4,gr8 + set_gr_immed -4,gr9 + calll @(gr8,gr9) +bad3: + fail +ok3: + test_spr_addr bad3,lr + + pass diff --git a/sim/testsuite/sim/frv/cand.cgs b/sim/testsuite/sim/frv/cand.cgs new file mode 100644 index 0000000..6113593 --- /dev/null +++ b/sim/testsuite/sim/frv/cand.cgs @@ -0,0 +1,126 @@ +# frv testcase for cand $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global cand +cand: + set_spr_immed 0x1b1b,cccr + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x0b,0 ; Set mask opposite of expected + cand gr7,gr8,gr8,cc0,1 + test_icc 1 0 1 1 icc0 + test_gr_immed 0,gr8 + + set_gr_limmed 0xffff,0x0000,gr8 + set_icc 0x04,0 ; Set mask opposite of expected + cand gr7,gr8,gr8,cc0,1 + test_icc 0 1 0 0 icc0 + test_gr_limmed 0xaaaa,0x0000,gr8 + + set_gr_limmed 0x0000,0xffff,gr8 + set_icc 0x0d,0 ; Set mask opposite of expected + cand gr7,gr8,gr8,cc4,1 + test_icc 1 1 0 1 icc0 + test_gr_limmed 0x0000,0xaaaa,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x0b,0 ; Set mask opposite of expected + cand gr7,gr8,gr8,cc0,0 + test_icc 1 0 1 1 icc0 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_limmed 0xffff,0x0000,gr8 + set_icc 0x04,0 ; Set mask opposite of expected + cand gr7,gr8,gr8,cc0,0 + test_icc 0 1 0 0 icc0 + test_gr_limmed 0xffff,0x0000,gr8 + + set_gr_limmed 0x0000,0xffff,gr8 + set_icc 0x0d,0 ; Set mask opposite of expected + cand gr7,gr8,gr8,cc4,0 + test_icc 1 1 0 1 icc0 + test_gr_limmed 0x0000,0xffff,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x0b,1 ; Set mask opposite of expected + cand gr7,gr8,gr8,cc1,0 + test_icc 1 0 1 1 icc1 + test_gr_immed 0,gr8 + + set_gr_limmed 0xffff,0x0000,gr8 + set_icc 0x04,1 ; Set mask opposite of expected + cand gr7,gr8,gr8,cc1,0 + test_icc 0 1 0 0 icc1 + test_gr_limmed 0xaaaa,0x0000,gr8 + + set_gr_limmed 0x0000,0xffff,gr8 + set_icc 0x0d,1 ; Set mask opposite of expected + cand gr7,gr8,gr8,cc5,0 + test_icc 1 1 0 1 icc1 + test_gr_limmed 0x0000,0xaaaa,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x0b,1 ; Set mask opposite of expected + cand gr7,gr8,gr8,cc1,1 + test_icc 1 0 1 1 icc1 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_limmed 0xffff,0x0000,gr8 + set_icc 0x04,1 ; Set mask opposite of expected + cand gr7,gr8,gr8,cc1,1 + test_icc 0 1 0 0 icc1 + test_gr_limmed 0xffff,0x0000,gr8 + + set_gr_limmed 0x0000,0xffff,gr8 + set_icc 0x0d,1 ; Set mask opposite of expected + cand gr7,gr8,gr8,cc5,1 + test_icc 1 1 0 1 icc1 + test_gr_limmed 0x0000,0xffff,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x0b,2 ; Set mask opposite of expected + cand gr7,gr8,gr8,cc2,0 + test_icc 1 0 1 1 icc2 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_limmed 0xffff,0x0000,gr8 + set_icc 0x04,2 ; Set mask opposite of expected + cand gr7,gr8,gr8,cc2,0 + test_icc 0 1 0 0 icc2 + test_gr_limmed 0xffff,0x0000,gr8 + + set_gr_limmed 0x0000,0xffff,gr8 + set_icc 0x0d,2 ; Set mask opposite of expected + cand gr7,gr8,gr8,cc6,1 + test_icc 1 1 0 1 icc2 + test_gr_limmed 0x0000,0xffff,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x0b,3 ; Set mask opposite of expected + cand gr7,gr8,gr8,cc3,0 + test_icc 1 0 1 1 icc3 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_limmed 0xffff,0x0000,gr8 + set_icc 0x04,3 ; Set mask opposite of expected + cand gr7,gr8,gr8,cc3,0 + test_icc 0 1 0 0 icc3 + test_gr_limmed 0xffff,0x0000,gr8 + + set_gr_limmed 0x0000,0xffff,gr8 + set_icc 0x0d,3 ; Set mask opposite of expected + cand gr7,gr8,gr8,cc7,1 + test_icc 1 1 0 1 icc3 + test_gr_limmed 0x0000,0xffff,gr8 + + pass diff --git a/sim/testsuite/sim/frv/candcc.cgs b/sim/testsuite/sim/frv/candcc.cgs new file mode 100644 index 0000000..c16df73 --- /dev/null +++ b/sim/testsuite/sim/frv/candcc.cgs @@ -0,0 +1,126 @@ +# frv testcase for candcc $GRi,$GRj,$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global candcc +candcc: + set_spr_immed 0x1b1b,cccr + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x0b,0 ; Set mask opposite of expected + candcc gr7,gr8,gr8,cc0,1 + test_icc 0 1 1 1 icc0 + test_gr_immed 0,gr8 + + set_gr_limmed 0xffff,0x0000,gr8 + set_icc 0x04,0 ; Set mask opposite of expected + candcc gr7,gr8,gr8,cc0,1 + test_icc 1 0 0 0 icc0 + test_gr_limmed 0xaaaa,0x0000,gr8 + + set_gr_limmed 0x0000,0xffff,gr8 + set_icc 0x0d,0 ; Set mask opposite of expected + candcc gr7,gr8,gr8,cc4,1 + test_icc 0 0 0 1 icc0 + test_gr_limmed 0x0000,0xaaaa,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x0b,0 ; Set mask opposite of expected + candcc gr7,gr8,gr8,cc0,0 + test_icc 1 0 1 1 icc0 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_limmed 0xffff,0x0000,gr8 + set_icc 0x04,0 ; Set mask opposite of expected + candcc gr7,gr8,gr8,cc0,0 + test_icc 0 1 0 0 icc0 + test_gr_limmed 0xffff,0x0000,gr8 + + set_gr_limmed 0x0000,0xffff,gr8 + set_icc 0x0d,0 ; Set mask opposite of expected + candcc gr7,gr8,gr8,cc4,0 + test_icc 1 1 0 1 icc0 + test_gr_limmed 0x0000,0xffff,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x0b,1 ; Set mask opposite of expected + candcc gr7,gr8,gr8,cc1,0 + test_icc 0 1 1 1 icc1 + test_gr_immed 0,gr8 + + set_gr_limmed 0xffff,0x0000,gr8 + set_icc 0x04,1 ; Set mask opposite of expected + candcc gr7,gr8,gr8,cc1,0 + test_icc 1 0 0 0 icc1 + test_gr_limmed 0xaaaa,0x0000,gr8 + + set_gr_limmed 0x0000,0xffff,gr8 + set_icc 0x0d,1 ; Set mask opposite of expected + candcc gr7,gr8,gr8,cc5,0 + test_icc 0 0 0 1 icc1 + test_gr_limmed 0x0000,0xaaaa,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x0b,1 ; Set mask opposite of expected + candcc gr7,gr8,gr8,cc1,1 + test_icc 1 0 1 1 icc1 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_limmed 0xffff,0x0000,gr8 + set_icc 0x04,1 ; Set mask opposite of expected + candcc gr7,gr8,gr8,cc1,1 + test_icc 0 1 0 0 icc1 + test_gr_limmed 0xffff,0x0000,gr8 + + set_gr_limmed 0x0000,0xffff,gr8 + set_icc 0x0d,1 ; Set mask opposite of expected + candcc gr7,gr8,gr8,cc5,1 + test_icc 1 1 0 1 icc1 + test_gr_limmed 0x0000,0xffff,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x0b,2 ; Set mask opposite of expected + candcc gr7,gr8,gr8,cc2,0 + test_icc 1 0 1 1 icc2 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_limmed 0xffff,0x0000,gr8 + set_icc 0x04,2 ; Set mask opposite of expected + candcc gr7,gr8,gr8,cc2,0 + test_icc 0 1 0 0 icc2 + test_gr_limmed 0xffff,0x0000,gr8 + + set_gr_limmed 0x0000,0xffff,gr8 + set_icc 0x0d,2 ; Set mask opposite of expected + candcc gr7,gr8,gr8,cc6,1 + test_icc 1 1 0 1 icc2 + test_gr_limmed 0x0000,0xffff,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x0b,3 ; Set mask opposite of expected + candcc gr7,gr8,gr8,cc3,0 + test_icc 1 0 1 1 icc3 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_limmed 0xffff,0x0000,gr8 + set_icc 0x04,3 ; Set mask opposite of expected + candcc gr7,gr8,gr8,cc3,0 + test_icc 0 1 0 0 icc3 + test_gr_limmed 0xffff,0x0000,gr8 + + set_gr_limmed 0x0000,0xffff,gr8 + set_icc 0x0d,3 ; Set mask opposite of expected + candcc gr7,gr8,gr8,cc7,1 + test_icc 1 1 0 1 icc3 + test_gr_limmed 0x0000,0xffff,gr8 + + pass diff --git a/sim/testsuite/sim/frv/ccalll.cgs b/sim/testsuite/sim/frv/ccalll.cgs new file mode 100644 index 0000000..dcfd300 --- /dev/null +++ b/sim/testsuite/sim/frv/ccalll.cgs @@ -0,0 +1,101 @@ +# frv testcase for ccalll @($GRi,$GRj),$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global ccalll +ccalll: + set_spr_immed 0x1b1b,cccr + + set_gr_addr ok2,gr8 + inc_gr_immed -4,gr8 + inc_gr_immed 4,gr9 + ccalll @(gr8,gr9),cc0,1 +bad2: + fail +ok2: + test_spr_addr bad2,lr + + set_gr_addr ok3,gr8 + inc_gr_immed 4,gr8 + set_gr_immed -4,gr9 + ccalll @(gr8,gr9),cc4,1 +bad3: + fail +ok3: + test_spr_addr bad3,lr + + set_spr_immed 0,lr + set_gr_addr bad,gr8 + inc_gr_immed -4,gr8 + set_gr_immed 4,gr9 + ccalll @(gr8,gr9),cc0,0 + test_spr_addr 0,lr + + set_gr_addr bad,gr8 + inc_gr_immed 4,gr8 + set_gr_immed -4,gr9 + ccalll @(gr8,gr9),cc4,0 + test_spr_addr 0,lr + + set_gr_addr ok5,gr8 + inc_gr_immed -4,gr8 + set_gr_immed 4,gr9 + ccalll @(gr8,gr9),cc1,0 +bad5: + fail +ok5: + test_spr_addr bad5,lr + + set_gr_addr ok6,gr8 + inc_gr_immed 4,gr8 + set_gr_immed -4,gr9 + ccalll @(gr8,gr9),cc5,0 +bad6: + fail +ok6: + test_spr_addr bad6,lr + + set_spr_immed 0,lr + set_gr_addr bad,gr8 + inc_gr_immed -4,gr8 + set_gr_immed 4,gr9 + ccalll @(gr8,gr9),cc1,1 + test_spr_addr 0,lr + + set_gr_addr bad,gr8 + inc_gr_immed 4,gr8 + set_gr_immed -4,gr9 + ccalll @(gr8,gr9),cc5,1 + test_spr_addr 0,lr + + set_gr_addr bad,gr8 + inc_gr_immed -4,gr8 + set_gr_immed 4,gr9 + ccalll @(gr8,gr9),cc2,1 + test_spr_addr 0,lr + + set_gr_addr bad,gr8 + inc_gr_immed 4,gr8 + set_gr_immed -4,gr9 + ccalll @(gr8,gr9),cc6,0 + test_spr_addr 0,lr + + set_gr_addr bad,gr8 + inc_gr_immed -4,gr8 + set_gr_immed 4,gr9 + ccalll @(gr8,gr9),cc3,0 + test_spr_addr 0,lr + + set_gr_addr bad,gr8 + inc_gr_immed 4,gr8 + set_gr_immed -4,gr9 + ccalll @(gr8,gr9),cc7,1 + test_spr_addr 0,lr + + pass +bad: + fail + diff --git a/sim/testsuite/sim/frv/cckc.cgs b/sim/testsuite/sim/frv/cckc.cgs new file mode 100644 index 0000000..70eabee --- /dev/null +++ b/sim/testsuite/sim/frv/cckc.cgs @@ -0,0 +1,490 @@ +# frv testcase for cckc $ICCi,$CCj_int,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cckc +cckc: + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckc icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckc icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckc icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckc icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckc icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckc icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckc icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckc icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckc icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckc icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckc icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckc icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckc icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckc icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckc icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckc icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckc icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckc icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckc icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckc icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckc icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckc icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckc icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckc icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckc icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckc icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckc icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckc icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckc icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckc icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckc icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckc icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckc icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckc icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckc icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckc icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckc icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckc icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckc icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckc icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckc icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckc icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckc icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckc icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckc icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckc icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckc icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckc icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckc icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckc icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckc icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckc icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckc icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckc icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckc icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckc icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckc icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckc icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckc icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckc icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckc icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckc icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckc icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckc icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckc icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckc icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckc icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckc icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckc icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckc icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckc icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckc icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckc icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckc icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckc icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckc icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckc icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckc icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckc icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckc icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckc icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckc icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckc icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckc icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckc icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckc icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckc icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckc icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckc icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckc icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckc icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckc icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckc icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckc icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckc icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckc icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/cckeq.cgs b/sim/testsuite/sim/frv/cckeq.cgs new file mode 100644 index 0000000..2c86f18 --- /dev/null +++ b/sim/testsuite/sim/frv/cckeq.cgs @@ -0,0 +1,490 @@ +# frv testcase for cckeq $ICCi,$CCj_int,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cckeq +cckeq: + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckeq icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckeq icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckeq icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckeq icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckeq icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckeq icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckeq icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckeq icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckeq icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckeq icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckeq icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckeq icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckeq icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckeq icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckeq icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckeq icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckeq icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckeq icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckeq icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckeq icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckeq icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckeq icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckeq icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckeq icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckeq icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckeq icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckeq icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckeq icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckeq icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckeq icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckeq icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckeq icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckeq icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckeq icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckeq icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckeq icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckeq icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckeq icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckeq icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckeq icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckeq icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckeq icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckeq icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckeq icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckeq icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckeq icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckeq icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckeq icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckeq icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckeq icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckeq icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckeq icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckeq icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckeq icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckeq icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckeq icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckeq icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckeq icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckeq icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckeq icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckeq icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckeq icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckeq icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckeq icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckeq icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckeq icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckeq icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckeq icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckeq icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckeq icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckeq icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckeq icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckeq icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckeq icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckeq icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckeq icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckeq icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckeq icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckeq icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckeq icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckeq icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckeq icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckeq icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckeq icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckeq icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckeq icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckeq icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckeq icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckeq icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckeq icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckeq icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckeq icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckeq icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckeq icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckeq icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckeq icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/cckge.cgs b/sim/testsuite/sim/frv/cckge.cgs new file mode 100644 index 0000000..6938f1e --- /dev/null +++ b/sim/testsuite/sim/frv/cckge.cgs @@ -0,0 +1,490 @@ +# frv testcase for cckge $ICCi,$CCj_int,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cckge +cckge: + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckge icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckge icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckge icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckge icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckge icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckge icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckge icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckge icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckge icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckge icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckge icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckge icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckge icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckge icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckge icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckge icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckge icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckge icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckge icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckge icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckge icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckge icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckge icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckge icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckge icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckge icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckge icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckge icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckge icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckge icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckge icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckge icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckge icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckge icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckge icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckge icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckge icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckge icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckge icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckge icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckge icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckge icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckge icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckge icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckge icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckge icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckge icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckge icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckge icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckge icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckge icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckge icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckge icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckge icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckge icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckge icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckge icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckge icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckge icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckge icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckge icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckge icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckge icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckge icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckge icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckge icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckge icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckge icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckge icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckge icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckge icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckge icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckge icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckge icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckge icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckge icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckge icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckge icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckge icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckge icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckge icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckge icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckge icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckge icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckge icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckge icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckge icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckge icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckge icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckge icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckge icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckge icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckge icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckge icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckge icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckge icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/cckgt.cgs b/sim/testsuite/sim/frv/cckgt.cgs new file mode 100644 index 0000000..e0745dd --- /dev/null +++ b/sim/testsuite/sim/frv/cckgt.cgs @@ -0,0 +1,490 @@ +# frv testcase for cckgt $ICCi,$CCj_int,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cckgt +cckgt: + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckgt icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckgt icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckgt icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckgt icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckgt icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckgt icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckgt icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckgt icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckgt icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckgt icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckgt icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckgt icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckgt icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckgt icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckgt icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckgt icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckgt icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckgt icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckgt icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckgt icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckgt icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckgt icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckgt icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckgt icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckgt icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckgt icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckgt icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckgt icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckgt icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckgt icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckgt icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckgt icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckgt icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckgt icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckgt icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckgt icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckgt icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckgt icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckgt icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckgt icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckgt icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckgt icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckgt icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckgt icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckgt icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckgt icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckgt icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckgt icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckgt icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckgt icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckgt icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckgt icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckgt icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckgt icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckgt icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckgt icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckgt icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckgt icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckgt icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckgt icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckgt icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckgt icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckgt icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckgt icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckgt icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckgt icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckgt icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckgt icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckgt icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckgt icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckgt icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckgt icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckgt icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckgt icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckgt icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckgt icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckgt icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckgt icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckgt icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckgt icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckgt icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckgt icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckgt icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckgt icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckgt icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckgt icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckgt icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckgt icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckgt icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckgt icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckgt icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckgt icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckgt icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckgt icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckgt icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckgt icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/cckhi.cgs b/sim/testsuite/sim/frv/cckhi.cgs new file mode 100644 index 0000000..4741f5a --- /dev/null +++ b/sim/testsuite/sim/frv/cckhi.cgs @@ -0,0 +1,490 @@ +# frv testcase for cckhi $ICCi,$CCj_int,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cckhi +cckhi: + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckhi icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckhi icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckhi icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckhi icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckhi icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckhi icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckhi icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckhi icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckhi icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckhi icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckhi icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckhi icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckhi icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckhi icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckhi icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckhi icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckhi icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckhi icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckhi icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckhi icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckhi icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckhi icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckhi icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckhi icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckhi icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckhi icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckhi icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckhi icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckhi icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckhi icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckhi icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckhi icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckhi icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckhi icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckhi icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckhi icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckhi icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckhi icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckhi icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckhi icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckhi icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckhi icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckhi icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckhi icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckhi icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckhi icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckhi icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckhi icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckhi icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckhi icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckhi icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckhi icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckhi icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckhi icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckhi icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckhi icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckhi icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckhi icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckhi icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckhi icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckhi icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckhi icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckhi icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckhi icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckhi icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckhi icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckhi icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckhi icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckhi icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckhi icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckhi icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckhi icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckhi icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckhi icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckhi icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckhi icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckhi icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckhi icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckhi icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckhi icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckhi icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckhi icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckhi icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckhi icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckhi icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckhi icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckhi icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckhi icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckhi icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckhi icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckhi icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckhi icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckhi icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckhi icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckhi icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckhi icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/cckle.cgs b/sim/testsuite/sim/frv/cckle.cgs new file mode 100644 index 0000000..9d88214 --- /dev/null +++ b/sim/testsuite/sim/frv/cckle.cgs @@ -0,0 +1,490 @@ +# frv testcase for cckle $ICCi,$CCj_int,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cckle +cckle: + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckle icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckle icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckle icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckle icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckle icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckle icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckle icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckle icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckle icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckle icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckle icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckle icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckle icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckle icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckle icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckle icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckle icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckle icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckle icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckle icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckle icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckle icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckle icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckle icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckle icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckle icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckle icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckle icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckle icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckle icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckle icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckle icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckle icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckle icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckle icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckle icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckle icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckle icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckle icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckle icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckle icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckle icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckle icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckle icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckle icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckle icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckle icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckle icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckle icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckle icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckle icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckle icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckle icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckle icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckle icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckle icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckle icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckle icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckle icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckle icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckle icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckle icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckle icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckle icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckle icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckle icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckle icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckle icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckle icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckle icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckle icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckle icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckle icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckle icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckle icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckle icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckle icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckle icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckle icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckle icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckle icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckle icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckle icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckle icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckle icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckle icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckle icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckle icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckle icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckle icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckle icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckle icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckle icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckle icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckle icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckle icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/cckls.cgs b/sim/testsuite/sim/frv/cckls.cgs new file mode 100644 index 0000000..a78b779 --- /dev/null +++ b/sim/testsuite/sim/frv/cckls.cgs @@ -0,0 +1,490 @@ +# frv testcase for cckls $ICCi,$CCj_int,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cckls +cckls: + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckls icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckls icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckls icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckls icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckls icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckls icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckls icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckls icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckls icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckls icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckls icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckls icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckls icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckls icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckls icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckls icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckls icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckls icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckls icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckls icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckls icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckls icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckls icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckls icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckls icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckls icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckls icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckls icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckls icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckls icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckls icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckls icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckls icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckls icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckls icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckls icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckls icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckls icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckls icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckls icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckls icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckls icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckls icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckls icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckls icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckls icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckls icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckls icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckls icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckls icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckls icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckls icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckls icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckls icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckls icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckls icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckls icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckls icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckls icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckls icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckls icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckls icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckls icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckls icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckls icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckls icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckls icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckls icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckls icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckls icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckls icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckls icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckls icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckls icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckls icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckls icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckls icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckls icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckls icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckls icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckls icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckls icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckls icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckls icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckls icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckls icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckls icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckls icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckls icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckls icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckls icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckls icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckls icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckls icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckls icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckls icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/ccklt.cgs b/sim/testsuite/sim/frv/ccklt.cgs new file mode 100644 index 0000000..c14c632 --- /dev/null +++ b/sim/testsuite/sim/frv/ccklt.cgs @@ -0,0 +1,490 @@ +# frv testcase for ccklt $ICCi,$CCj_int,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global ccklt +ccklt: + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + ccklt icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + ccklt icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + ccklt icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + ccklt icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + ccklt icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + ccklt icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + ccklt icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + ccklt icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + ccklt icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + ccklt icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + ccklt icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + ccklt icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + ccklt icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + ccklt icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + ccklt icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + ccklt icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + ccklt icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + ccklt icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + ccklt icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + ccklt icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + ccklt icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + ccklt icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + ccklt icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + ccklt icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + ccklt icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + ccklt icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + ccklt icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + ccklt icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + ccklt icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + ccklt icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + ccklt icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + ccklt icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + ccklt icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + ccklt icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + ccklt icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + ccklt icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + ccklt icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + ccklt icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + ccklt icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + ccklt icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + ccklt icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + ccklt icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + ccklt icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + ccklt icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + ccklt icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + ccklt icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + ccklt icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + ccklt icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + ccklt icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + ccklt icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + ccklt icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + ccklt icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + ccklt icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + ccklt icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + ccklt icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + ccklt icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + ccklt icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + ccklt icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + ccklt icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + ccklt icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + ccklt icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + ccklt icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + ccklt icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + ccklt icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + ccklt icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + ccklt icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + ccklt icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + ccklt icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + ccklt icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + ccklt icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + ccklt icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + ccklt icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + ccklt icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + ccklt icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + ccklt icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + ccklt icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + ccklt icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + ccklt icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + ccklt icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + ccklt icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + ccklt icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + ccklt icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + ccklt icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + ccklt icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + ccklt icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + ccklt icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + ccklt icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + ccklt icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + ccklt icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + ccklt icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + ccklt icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + ccklt icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + ccklt icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + ccklt icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + ccklt icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + ccklt icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/cckn.cgs b/sim/testsuite/sim/frv/cckn.cgs new file mode 100644 index 0000000..d423124 --- /dev/null +++ b/sim/testsuite/sim/frv/cckn.cgs @@ -0,0 +1,490 @@ +# frv testcase for cckn $ICCi,$CCj_int,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cckn +cckn: + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckn icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckn icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckn icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckn icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckn icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckn icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckn icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckn icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckn icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckn icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckn icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckn icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckn icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckn icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckn icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckn icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckn icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckn icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckn icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckn icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckn icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckn icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckn icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckn icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckn icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckn icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckn icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckn icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckn icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckn icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckn icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckn icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckn icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckn icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckn icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckn icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckn icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckn icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckn icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckn icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckn icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckn icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckn icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckn icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckn icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckn icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckn icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckn icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckn icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckn icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckn icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckn icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckn icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckn icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckn icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckn icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckn icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckn icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckn icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckn icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckn icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckn icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckn icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckn icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckn icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckn icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckn icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckn icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckn icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckn icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckn icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckn icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckn icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckn icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckn icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckn icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckn icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckn icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckn icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckn icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckn icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckn icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckn icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckn icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckn icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckn icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckn icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckn icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckn icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckn icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckn icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckn icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckn icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckn icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckn icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckn icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/ccknc.cgs b/sim/testsuite/sim/frv/ccknc.cgs new file mode 100644 index 0000000..0478f27 --- /dev/null +++ b/sim/testsuite/sim/frv/ccknc.cgs @@ -0,0 +1,490 @@ +# frv testcase for ccknc $ICCi,$CCj_int,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global ccknc +ccknc: + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + ccknc icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + ccknc icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + ccknc icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + ccknc icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + ccknc icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + ccknc icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + ccknc icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + ccknc icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + ccknc icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + ccknc icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + ccknc icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + ccknc icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + ccknc icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + ccknc icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + ccknc icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + ccknc icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + ccknc icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + ccknc icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + ccknc icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + ccknc icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + ccknc icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + ccknc icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + ccknc icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + ccknc icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + ccknc icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + ccknc icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + ccknc icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + ccknc icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + ccknc icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + ccknc icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + ccknc icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + ccknc icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + ccknc icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + ccknc icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + ccknc icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + ccknc icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + ccknc icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + ccknc icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + ccknc icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + ccknc icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + ccknc icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + ccknc icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + ccknc icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + ccknc icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + ccknc icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + ccknc icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + ccknc icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + ccknc icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + ccknc icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + ccknc icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + ccknc icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + ccknc icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + ccknc icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + ccknc icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + ccknc icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + ccknc icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + ccknc icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + ccknc icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + ccknc icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + ccknc icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + ccknc icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + ccknc icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + ccknc icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + ccknc icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + ccknc icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + ccknc icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + ccknc icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + ccknc icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + ccknc icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + ccknc icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + ccknc icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + ccknc icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + ccknc icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + ccknc icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + ccknc icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + ccknc icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + ccknc icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + ccknc icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + ccknc icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + ccknc icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + ccknc icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + ccknc icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + ccknc icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + ccknc icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + ccknc icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + ccknc icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + ccknc icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + ccknc icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + ccknc icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + ccknc icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + ccknc icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + ccknc icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + ccknc icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + ccknc icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + ccknc icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + ccknc icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/cckne.cgs b/sim/testsuite/sim/frv/cckne.cgs new file mode 100644 index 0000000..d8af1e3 --- /dev/null +++ b/sim/testsuite/sim/frv/cckne.cgs @@ -0,0 +1,490 @@ +# frv testcase for cckne $ICCi,$CCj_int,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cckne +cckne: + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckne icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckne icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckne icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckne icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckne icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckne icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckne icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckne icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckne icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckne icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckne icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckne icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckne icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckne icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckne icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckne icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckne icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckne icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckne icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckne icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckne icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckne icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckne icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckne icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckne icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckne icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckne icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckne icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckne icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckne icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckne icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckne icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckne icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckne icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckne icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckne icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckne icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckne icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckne icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckne icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckne icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckne icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckne icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckne icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckne icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckne icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckne icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckne icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckne icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckne icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckne icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckne icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckne icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckne icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckne icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckne icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckne icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckne icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckne icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckne icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckne icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckne icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckne icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckne icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckne icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckne icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckne icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckne icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckne icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckne icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckne icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckne icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckne icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckne icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckne icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckne icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckne icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckne icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckne icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckne icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckne icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckne icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckne icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckne icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckne icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckne icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckne icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckne icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckne icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckne icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckne icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckne icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckne icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckne icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckne icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckne icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/cckno.cgs b/sim/testsuite/sim/frv/cckno.cgs new file mode 100644 index 0000000..8c3c927 --- /dev/null +++ b/sim/testsuite/sim/frv/cckno.cgs @@ -0,0 +1,490 @@ +# frv testcase for cckno $CCj_int,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cckno +cckno: + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckno cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckno cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckno cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckno cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckno cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckno cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckno cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckno cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckno cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckno cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckno cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckno cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckno cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckno cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckno cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckno cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckno cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckno cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckno cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckno cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckno cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckno cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckno cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckno cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckno cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckno cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckno cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckno cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckno cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckno cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckno cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckno cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckno cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckno cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckno cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckno cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckno cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckno cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckno cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckno cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckno cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckno cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckno cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckno cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckno cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckno cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckno cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckno cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckno cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckno cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckno cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckno cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckno cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckno cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckno cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckno cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckno cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckno cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckno cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckno cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckno cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckno cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckno cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckno cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckno cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckno cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckno cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckno cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckno cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckno cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckno cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckno cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckno cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckno cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckno cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckno cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckno cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckno cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckno cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckno cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckno cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckno cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckno cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckno cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckno cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckno cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckno cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckno cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckno cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckno cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckno cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckno cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckno cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckno cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckno cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckno cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/ccknv.cgs b/sim/testsuite/sim/frv/ccknv.cgs new file mode 100644 index 0000000..333edca --- /dev/null +++ b/sim/testsuite/sim/frv/ccknv.cgs @@ -0,0 +1,490 @@ +# frv testcase for ccknv $ICCi,$CCj_int,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global ccknv +ccknv: + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + ccknv icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + ccknv icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + ccknv icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + ccknv icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + ccknv icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + ccknv icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + ccknv icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + ccknv icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + ccknv icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + ccknv icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + ccknv icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + ccknv icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + ccknv icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + ccknv icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + ccknv icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + ccknv icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + ccknv icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + ccknv icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + ccknv icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + ccknv icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + ccknv icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + ccknv icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + ccknv icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + ccknv icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + ccknv icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + ccknv icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + ccknv icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + ccknv icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + ccknv icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + ccknv icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + ccknv icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + ccknv icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + ccknv icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + ccknv icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + ccknv icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + ccknv icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + ccknv icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + ccknv icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + ccknv icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + ccknv icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + ccknv icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + ccknv icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + ccknv icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + ccknv icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + ccknv icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + ccknv icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + ccknv icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + ccknv icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + ccknv icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + ccknv icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + ccknv icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + ccknv icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + ccknv icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + ccknv icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + ccknv icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + ccknv icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + ccknv icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + ccknv icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + ccknv icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + ccknv icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + ccknv icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + ccknv icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + ccknv icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + ccknv icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + ccknv icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + ccknv icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + ccknv icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + ccknv icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + ccknv icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + ccknv icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + ccknv icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + ccknv icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + ccknv icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + ccknv icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + ccknv icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + ccknv icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + ccknv icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + ccknv icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + ccknv icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + ccknv icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + ccknv icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + ccknv icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + ccknv icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + ccknv icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + ccknv icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + ccknv icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + ccknv icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + ccknv icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + ccknv icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + ccknv icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + ccknv icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + ccknv icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + ccknv icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + ccknv icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + ccknv icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + ccknv icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/cckp.cgs b/sim/testsuite/sim/frv/cckp.cgs new file mode 100644 index 0000000..53570d9 --- /dev/null +++ b/sim/testsuite/sim/frv/cckp.cgs @@ -0,0 +1,490 @@ +# frv testcase for cckp $ICCi,$CCj_int,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cckp +cckp: + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckp icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckp icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckp icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckp icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckp icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckp icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckp icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckp icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckp icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckp icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckp icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckp icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckp icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckp icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckp icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckp icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckp icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckp icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckp icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckp icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckp icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckp icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckp icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckp icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckp icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckp icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckp icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckp icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckp icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckp icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckp icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckp icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckp icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckp icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckp icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckp icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckp icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckp icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckp icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckp icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckp icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckp icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckp icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckp icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckp icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckp icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckp icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckp icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckp icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckp icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckp icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckp icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckp icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckp icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckp icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckp icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckp icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckp icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckp icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckp icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckp icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckp icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckp icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckp icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckp icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckp icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckp icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckp icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckp icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckp icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckp icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckp icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckp icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckp icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckp icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckp icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckp icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckp icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckp icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckp icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckp icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckp icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckp icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckp icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckp icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckp icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckp icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckp icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckp icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckp icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckp icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckp icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckp icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckp icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckp icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckp icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/cckra.cgs b/sim/testsuite/sim/frv/cckra.cgs new file mode 100644 index 0000000..c0b27fc --- /dev/null +++ b/sim/testsuite/sim/frv/cckra.cgs @@ -0,0 +1,480 @@ +# frv testcase for cckra $CCj_int,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cckra +cckra: + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckra cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckra cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckra cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckra cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckra cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckra cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckra cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckra cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckra cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckra cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckra cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckra cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckra cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckra cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckra cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckra cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckra cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckra cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckra cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckra cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckra cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckra cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckra cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckra cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckra cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckra cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckra cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckra cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckra cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckra cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckra cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckra cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckra cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckra cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckra cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckra cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckra cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckra cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckra cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckra cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckra cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckra cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckra cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckra cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckra cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckra cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckra cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckra cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckra cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckra cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckra cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckra cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckra cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckra cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckra cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckra cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckra cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckra cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckra cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckra cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckra cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckra cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckra cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckra cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckra cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckra cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckra cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckra cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckra cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckra cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckra cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckra cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckra cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckra cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckra cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckra cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckra cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckra cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckra cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckra cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckra cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckra cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckra cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckra cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckra cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckra cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckra cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckra cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckra cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckra cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckra cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckra cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckra cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckra cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/cckv.cgs b/sim/testsuite/sim/frv/cckv.cgs new file mode 100644 index 0000000..9ebb6e3 --- /dev/null +++ b/sim/testsuite/sim/frv/cckv.cgs @@ -0,0 +1,490 @@ +# frv testcase for cckv $ICCi,$CCj_int,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cckv +cckv: + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckv icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckv icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckv icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckv icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckv icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckv icc0,cc7,cc0,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckv icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckv icc0,cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckv icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckv icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckv icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckv icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckv icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckv icc0,cc7,cc4,1 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckv icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckv icc0,cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckv icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckv icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckv icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckv icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckv icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckv icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckv icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckv icc0,cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckv icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckv icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckv icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckv icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckv icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckv icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckv icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckv icc0,cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckv icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckv icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckv icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckv icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckv icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckv icc0,cc7,cc1,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckv icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckv icc0,cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckv icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckv icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckv icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckv icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckv icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckv icc0,cc7,cc5,0 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckv icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckv icc0,cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckv icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckv icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckv icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckv icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckv icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckv icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckv icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckv icc0,cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckv icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckv icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckv icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckv icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckv icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckv icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckv icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckv icc0,cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckv icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckv icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckv icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckv icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckv icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckv icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckv icc0,cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckv icc0,cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckv icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckv icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckv icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckv icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckv icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckv icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckv icc0,cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckv icc0,cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckv icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckv icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckv icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckv icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckv icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckv icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckv icc0,cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckv icc0,cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckv icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckv icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckv icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckv icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckv icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckv icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckv icc0,cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckv icc0,cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/ccmp.cgs b/sim/testsuite/sim/frv/ccmp.cgs new file mode 100644 index 0000000..52d5310 --- /dev/null +++ b/sim/testsuite/sim/frv/ccmp.cgs @@ -0,0 +1,134 @@ +# frv testcase for ccmp $GRi,$GRj,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global ccmp +ccmp: + set_spr_immed 0x1b1b,cccr + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + ccmp gr8,gr7,cc0,1 + test_icc 0 0 0 0 icc0 + + set_gr_immed 1,gr7 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0d,0 ; Set mask opposite of expected + ccmp gr8,gr7,cc0,1 + test_icc 0 0 1 0 icc0 + + set_icc 0x0b,0 ; Set mask opposite of expected + ccmp gr8,gr8,cc4,1 + test_icc 0 1 0 0 icc0 + + set_gr_immed 0,gr8 + set_icc 0x06,0 ; Set mask opposite of expected + ccmp gr8,gr7,cc4,1 + test_icc 1 0 0 1 icc0 + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + ccmp gr8,gr7,cc0,0 + test_icc 1 1 1 1 icc0 + + set_gr_immed 1,gr7 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0d,0 ; Set mask opposite of expected + ccmp gr8,gr7,cc0,0 + test_icc 1 1 0 1 icc0 + + set_icc 0x0b,0 ; Set mask opposite of expected + ccmp gr8,gr8,cc4,0 + test_icc 1 0 1 1 icc0 + + set_icc 0x06,0 ; Set mask opposite of expected + ccmp gr8,gr7,cc4,0 + test_icc 0 1 1 0 icc0 + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + set_icc 0x0f,1 ; Set mask opposite of expected + ccmp gr8,gr7,cc1,0 + test_icc 0 0 0 0 icc1 + + set_gr_immed 1,gr7 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0d,1 ; Set mask opposite of expected + ccmp gr8,gr7,cc1,0 + test_icc 0 0 1 0 icc1 + + set_icc 0x0b,1 ; Set mask opposite of expected + ccmp gr8,gr8,cc5,0 + test_icc 0 1 0 0 icc1 + + set_gr_immed 0,gr8 + set_icc 0x06,1 ; Set mask opposite of expected + ccmp gr8,gr7,cc5,0 + test_icc 1 0 0 1 icc1 + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + set_icc 0x0f,1 ; Set mask opposite of expected + ccmp gr8,gr7,cc1,1 + test_icc 1 1 1 1 icc1 + + set_gr_immed 1,gr7 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0d,1 ; Set mask opposite of expected + ccmp gr8,gr7,cc1,1 + test_icc 1 1 0 1 icc1 + + set_icc 0x0b,1 ; Set mask opposite of expected + ccmp gr8,gr8,cc5,1 + test_icc 1 0 1 1 icc1 + + set_icc 0x06,1 ; Set mask opposite of expected + ccmp gr8,gr7,cc5,1 + test_icc 0 1 1 0 icc1 + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + set_icc 0x0f,2 ; Set mask opposite of expected + ccmp gr8,gr7,cc2,0 + test_icc 1 1 1 1 icc2 + + set_gr_immed 1,gr7 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0d,2 ; Set mask opposite of expected + ccmp gr8,gr7,cc2,0 + test_icc 1 1 0 1 icc2 + + set_icc 0x0b,2 ; Set mask opposite of expected + ccmp gr8,gr8,cc6,1 + test_icc 1 0 1 1 icc2 + + set_icc 0x06,2 ; Set mask opposite of expected + ccmp gr8,gr7,cc6,1 + test_icc 0 1 1 0 icc2 + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + set_icc 0x0f,3 ; Set mask opposite of expected + ccmp gr8,gr7,cc3,0 + test_icc 1 1 1 1 icc3 + + set_gr_immed 1,gr7 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0d,3 ; Set mask opposite of expected + ccmp gr8,gr7,cc3,0 + test_icc 1 1 0 1 icc3 + + set_icc 0x0b,3 ; Set mask opposite of expected + ccmp gr8,gr8,cc7,1 + test_icc 1 0 1 1 icc3 + + set_icc 0x06,3 ; Set mask opposite of expected + ccmp gr8,gr7,cc7,1 + test_icc 0 1 1 0 icc3 + + pass diff --git a/sim/testsuite/sim/frv/cfabss.cgs b/sim/testsuite/sim/frv/cfabss.cgs new file mode 100644 index 0000000..752a40b --- /dev/null +++ b/sim/testsuite/sim/frv/cfabss.cgs @@ -0,0 +1,96 @@ +# frv testcase for cfabss $FRj,$FRk,$CCi,$cond +# mach: fr500 fr550 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global cfabss +cfabss: + set_spr_immed 0x1b1b,cccr + + cfabss fr0,fr1,cc0,1 + test_fr_fr fr1,fr52 + cfabss fr8,fr1,cc0,1 + test_fr_fr fr1,fr28 + cfabss fr12,fr1,cc0,1 + test_fr_fr fr1,fr24 + cfabss fr24,fr1,cc4,1 + test_fr_fr fr1,fr24 + cfabss fr28,fr1,cc4,1 + test_fr_fr fr1,fr28 + cfabss fr52,fr1,cc4,1 + test_fr_fr fr1,fr52 + + cfabss fr0,fr1,cc1,0 + test_fr_fr fr1,fr52 + cfabss fr8,fr1,cc1,0 + test_fr_fr fr1,fr28 + cfabss fr12,fr1,cc1,0 + test_fr_fr fr1,fr24 + cfabss fr24,fr1,cc5,0 + test_fr_fr fr1,fr24 + cfabss fr28,fr1,cc5,0 + test_fr_fr fr1,fr28 + cfabss fr52,fr1,cc5,0 + test_fr_fr fr1,fr52 + + set_fr_iimmed 0xdead,0xbeef,fr1 + cfabss fr0,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfabss fr8,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfabss fr12,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfabss fr24,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfabss fr28,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfabss fr52,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + + set_fr_iimmed 0xdead,0xbeef,fr1 + cfabss fr0,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfabss fr8,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfabss fr12,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfabss fr24,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfabss fr28,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfabss fr52,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + + set_fr_iimmed 0xdead,0xbeef,fr1 + cfabss fr0,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfabss fr8,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfabss fr12,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfabss fr24,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfabss fr28,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfabss fr52,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + + set_fr_iimmed 0xdead,0xbeef,fr1 + cfabss fr0,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfabss fr8,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfabss fr12,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfabss fr24,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfabss fr28,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfabss fr52,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + + pass diff --git a/sim/testsuite/sim/frv/cfadds.cgs b/sim/testsuite/sim/frv/cfadds.cgs new file mode 100644 index 0000000..158ac93 --- /dev/null +++ b/sim/testsuite/sim/frv/cfadds.cgs @@ -0,0 +1,456 @@ +# frv testcase for cfadds $FRi,$FRj,$FRk,$CCi,$cond +# mach: fr500 fr550 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global cfadds +cfadds: + set_spr_immed 0x1b1b,cccr + + cfadds fr16,fr0,fr1,cc0,1 + test_fr_fr fr1,fr0 + cfadds fr16,fr4,fr1,cc0,1 + test_fr_fr fr1,fr4 + cfadds fr16,fr8,fr1,cc0,1 + test_fr_fr fr1,fr8 + cfadds fr16,fr12,fr1,cc0,1 + test_fr_fr fr1,fr12 + cfadds fr16,fr16,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfadds fr16,fr20,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfadds fr16,fr24,fr1,cc0,1 + test_fr_fr fr1,fr24 + cfadds fr16,fr28,fr1,cc0,1 + test_fr_fr fr1,fr28 + cfadds fr16,fr32,fr1,cc0,1 + test_fr_fr fr1,fr32 + cfadds fr16,fr36,fr1,cc0,1 + test_fr_fr fr1,fr36 + cfadds fr16,fr40,fr1,cc0,1 + test_fr_fr fr1,fr40 + cfadds fr16,fr44,fr1,cc0,1 + test_fr_fr fr1,fr44 + cfadds fr16,fr48,fr1,cc0,1 + test_fr_fr fr1,fr48 + cfadds fr16,fr52,fr1,cc0,1 + test_fr_fr fr1,fr52 + + cfadds fr20,fr0,fr1,cc0,1 + test_fr_fr fr1,fr0 + cfadds fr20,fr4,fr1,cc0,1 + test_fr_fr fr1,fr4 + cfadds fr20,fr8,fr1,cc4,1 + test_fr_fr fr1,fr8 + cfadds fr20,fr12,fr1,cc4,1 + test_fr_fr fr1,fr12 + cfadds fr20,fr16,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfadds fr20,fr20,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfadds fr20,fr24,fr1,cc4,1 + test_fr_fr fr1,fr24 + cfadds fr20,fr28,fr1,cc4,1 + test_fr_fr fr1,fr28 + cfadds fr20,fr32,fr1,cc4,1 + test_fr_fr fr1,fr32 + cfadds fr20,fr36,fr1,cc4,1 + test_fr_fr fr1,fr36 + cfadds fr20,fr40,fr1,cc4,1 + test_fr_fr fr1,fr40 + cfadds fr20,fr44,fr1,cc4,1 + test_fr_fr fr1,fr44 + cfadds fr20,fr48,fr1,cc4,1 + test_fr_fr fr1,fr48 + cfadds fr20,fr52,fr1,cc4,1 + test_fr_fr fr1,fr52 + + cfadds fr8,fr28,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfadds fr12,fr24,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfadds fr24,fr12,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfadds fr28,fr8,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + + cfadds fr36,fr40,fr1,cc4,1 + test_fr_fr fr1,fr44 + + cfadds fr16,fr0,fr1,cc1,0 + test_fr_fr fr1,fr0 + cfadds fr16,fr4,fr1,cc1,0 + test_fr_fr fr1,fr4 + cfadds fr16,fr8,fr1,cc1,0 + test_fr_fr fr1,fr8 + cfadds fr16,fr12,fr1,cc1,0 + test_fr_fr fr1,fr12 + cfadds fr16,fr16,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfadds fr16,fr20,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfadds fr16,fr24,fr1,cc1,0 + test_fr_fr fr1,fr24 + cfadds fr16,fr28,fr1,cc1,0 + test_fr_fr fr1,fr28 + cfadds fr16,fr32,fr1,cc1,0 + test_fr_fr fr1,fr32 + cfadds fr16,fr36,fr1,cc1,0 + test_fr_fr fr1,fr36 + cfadds fr16,fr40,fr1,cc1,0 + test_fr_fr fr1,fr40 + cfadds fr16,fr44,fr1,cc1,0 + test_fr_fr fr1,fr44 + cfadds fr16,fr48,fr1,cc1,0 + test_fr_fr fr1,fr48 + cfadds fr16,fr52,fr1,cc1,0 + test_fr_fr fr1,fr52 + + cfadds fr20,fr0,fr1,cc1,0 + test_fr_fr fr1,fr0 + cfadds fr20,fr4,fr1,cc1,0 + test_fr_fr fr1,fr4 + cfadds fr20,fr8,fr1,cc5,0 + test_fr_fr fr1,fr8 + cfadds fr20,fr12,fr1,cc5,0 + test_fr_fr fr1,fr12 + cfadds fr20,fr16,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfadds fr20,fr20,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfadds fr20,fr24,fr1,cc5,0 + test_fr_fr fr1,fr24 + cfadds fr20,fr28,fr1,cc5,0 + test_fr_fr fr1,fr28 + cfadds fr20,fr32,fr1,cc5,0 + test_fr_fr fr1,fr32 + cfadds fr20,fr36,fr1,cc5,0 + test_fr_fr fr1,fr36 + cfadds fr20,fr40,fr1,cc5,0 + test_fr_fr fr1,fr40 + cfadds fr20,fr44,fr1,cc5,0 + test_fr_fr fr1,fr44 + cfadds fr20,fr48,fr1,cc5,0 + test_fr_fr fr1,fr48 + cfadds fr20,fr52,fr1,cc5,0 + test_fr_fr fr1,fr52 + + cfadds fr8,fr28,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfadds fr12,fr24,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfadds fr24,fr12,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfadds fr28,fr8,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + + cfadds fr36,fr40,fr1,cc5,0 + test_fr_fr fr1,fr44 + + set_fr_iimmed 0xdead,0xbeef,fr1 + cfadds fr16,fr0,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr4,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr8,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr12,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr16,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr20,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr24,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr28,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr32,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr36,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr40,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr44,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr48,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr52,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + + cfadds fr20,fr0,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr4,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr8,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr12,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr16,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr20,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr24,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr28,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr32,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr36,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr40,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr44,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr48,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr52,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + + cfadds fr8,fr28,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr12,fr24,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr24,fr12,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr28,fr8,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + + cfadds fr36,fr40,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + + set_fr_iimmed 0xdead,0xbeef,fr1 + cfadds fr16,fr0,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr4,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr8,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr12,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr16,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr20,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr24,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr28,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr32,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr36,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr40,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr44,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr48,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr52,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfadds fr20,fr0,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr4,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr8,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr12,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr16,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr20,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr24,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr28,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr32,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr36,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr40,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr44,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr48,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr52,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfadds fr8,fr28,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr12,fr24,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr24,fr12,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr28,fr8,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfadds fr36,fr40,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + + set_fr_iimmed 0xdead,0xbeef,fr1 + cfadds fr16,fr0,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr4,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr8,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr12,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr16,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr20,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr24,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr28,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr32,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr36,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr40,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr44,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr48,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr52,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + + cfadds fr20,fr0,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr4,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr8,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr12,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr16,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr20,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr24,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr28,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr32,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr36,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr40,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr44,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr48,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr52,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + + cfadds fr8,fr28,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr12,fr24,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr24,fr12,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr28,fr8,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + + cfadds fr36,fr40,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 +; + set_fr_iimmed 0xdead,0xbeef,fr1 + cfadds fr16,fr0,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr4,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr8,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr12,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr16,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr20,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr24,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr28,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr32,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr36,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr40,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr44,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr48,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr16,fr52,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfadds fr20,fr0,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr4,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr8,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr12,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr16,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr20,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr24,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr28,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr32,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr36,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr40,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr44,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr48,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr20,fr52,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfadds fr8,fr28,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr12,fr24,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr24,fr12,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfadds fr28,fr8,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfadds fr36,fr40,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + + pass + + diff --git a/sim/testsuite/sim/frv/cfckeq.cgs b/sim/testsuite/sim/frv/cfckeq.cgs new file mode 100644 index 0000000..467568a --- /dev/null +++ b/sim/testsuite/sim/frv/cfckeq.cgs @@ -0,0 +1,490 @@ +# frv testcase for cfckeq $FCCi,$CCj_float,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cfckeq +cfckeq: + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckeq fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckeq fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckeq fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckeq fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckeq fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckeq fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckeq fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckeq fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckeq fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckeq fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckeq fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckeq fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckeq fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckeq fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckeq fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckeq fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckeq fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckeq fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckeq fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckeq fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckeq fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckeq fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckeq fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckeq fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckeq fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckeq fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckeq fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckeq fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckeq fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckeq fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckeq fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckeq fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckeq fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckeq fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckeq fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckeq fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckeq fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckeq fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckeq fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckeq fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckeq fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckeq fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckeq fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckeq fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckeq fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckeq fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckeq fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckeq fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckeq fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckeq fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckeq fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckeq fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckeq fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckeq fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckeq fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckeq fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckeq fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckeq fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckeq fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckeq fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckeq fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckeq fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckeq fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckeq fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckeq fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckeq fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckeq fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckeq fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckeq fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckeq fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckeq fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckeq fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckeq fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckeq fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckeq fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckeq fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckeq fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckeq fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckeq fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckeq fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckeq fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckeq fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckeq fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckeq fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckeq fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckeq fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckeq fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckeq fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckeq fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckeq fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckeq fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckeq fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckeq fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckeq fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckeq fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckeq fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/cfckge.cgs b/sim/testsuite/sim/frv/cfckge.cgs new file mode 100644 index 0000000..ba2de95 --- /dev/null +++ b/sim/testsuite/sim/frv/cfckge.cgs @@ -0,0 +1,490 @@ +# frv testcase for cfckge $FCCi,$CCj_float,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cfckge +cfckge: + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckge fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckge fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckge fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckge fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckge fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckge fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckge fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckge fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckge fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckge fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckge fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckge fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckge fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckge fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckge fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckge fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckge fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckge fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckge fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckge fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckge fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckge fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckge fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckge fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckge fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckge fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckge fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckge fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckge fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckge fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckge fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckge fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckge fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckge fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckge fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckge fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckge fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckge fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckge fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckge fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckge fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckge fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckge fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckge fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckge fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckge fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckge fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckge fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckge fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckge fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckge fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckge fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckge fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckge fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckge fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckge fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckge fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckge fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckge fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckge fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckge fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckge fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckge fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckge fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckge fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckge fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckge fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckge fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckge fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckge fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckge fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckge fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckge fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckge fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckge fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckge fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckge fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckge fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckge fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckge fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckge fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckge fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckge fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckge fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckge fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckge fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckge fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckge fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckge fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckge fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckge fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckge fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckge fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckge fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckge fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckge fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/cfckgt.cgs b/sim/testsuite/sim/frv/cfckgt.cgs new file mode 100644 index 0000000..7858c17 --- /dev/null +++ b/sim/testsuite/sim/frv/cfckgt.cgs @@ -0,0 +1,490 @@ +# frv testcase for cfckgt $FCCi,$CCj_float,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cfckgt +cfckgt: + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckgt fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckgt fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckgt fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckgt fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckgt fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckgt fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckgt fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckgt fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckgt fcc0,cc3,cc4,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckgt fcc0,cc3,cc4,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckgt fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckgt fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckgt fcc0,cc3,cc4,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckgt fcc0,cc3,cc4,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckgt fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckgt fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckgt fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckgt fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckgt fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckgt fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckgt fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckgt fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckgt fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckgt fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckgt fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckgt fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckgt fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckgt fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckgt fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckgt fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckgt fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckgt fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckgt fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckgt fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckgt fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckgt fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckgt fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckgt fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckgt fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckgt fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckgt fcc0,cc3,cc5,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckgt fcc0,cc3,cc5,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckgt fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckgt fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckgt fcc0,cc3,cc5,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckgt fcc0,cc3,cc5,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckgt fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckgt fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckgt fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckgt fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckgt fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckgt fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckgt fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckgt fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckgt fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckgt fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckgt fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckgt fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckgt fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckgt fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckgt fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckgt fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckgt fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckgt fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckgt fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckgt fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckgt fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckgt fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckgt fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckgt fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckgt fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckgt fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckgt fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckgt fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckgt fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckgt fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckgt fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckgt fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckgt fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckgt fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckgt fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckgt fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckgt fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckgt fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckgt fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckgt fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckgt fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckgt fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckgt fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckgt fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckgt fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckgt fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckgt fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckgt fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckgt fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckgt fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/cfckle.cgs b/sim/testsuite/sim/frv/cfckle.cgs new file mode 100644 index 0000000..fb2b1b85 --- /dev/null +++ b/sim/testsuite/sim/frv/cfckle.cgs @@ -0,0 +1,490 @@ +# frv testcase for cfckle $FCCi,$CCj_float$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cfckle +cfckle: + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckle fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckle fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckle fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckle fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckle fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckle fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckle fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckle fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckle fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckle fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckle fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckle fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckle fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckle fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckle fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckle fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckle fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckle fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckle fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckle fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckle fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckle fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckle fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckle fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckle fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckle fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckle fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckle fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckle fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckle fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckle fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckle fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckle fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckle fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckle fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckle fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckle fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckle fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckle fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckle fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckle fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckle fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckle fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckle fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckle fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckle fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckle fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckle fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckle fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckle fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckle fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckle fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckle fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckle fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckle fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckle fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckle fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckle fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckle fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckle fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckle fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckle fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckle fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckle fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckle fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckle fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckle fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckle fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckle fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckle fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckle fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckle fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckle fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckle fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckle fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckle fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckle fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckle fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckle fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckle fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckle fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckle fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckle fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckle fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckle fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckle fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckle fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckle fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckle fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckle fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckle fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckle fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckle fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckle fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckle fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckle fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/cfcklg.cgs b/sim/testsuite/sim/frv/cfcklg.cgs new file mode 100644 index 0000000..22deb52 --- /dev/null +++ b/sim/testsuite/sim/frv/cfcklg.cgs @@ -0,0 +1,490 @@ +# frv testcase for cfcklg $FCCi,$CCj_float$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cfcklg +cfcklg: + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfcklg fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfcklg fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfcklg fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfcklg fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfcklg fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfcklg fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfcklg fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfcklg fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfcklg fcc0,cc3,cc4,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfcklg fcc0,cc3,cc4,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfcklg fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfcklg fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfcklg fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfcklg fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfcklg fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfcklg fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfcklg fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfcklg fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfcklg fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfcklg fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfcklg fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfcklg fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfcklg fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfcklg fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfcklg fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfcklg fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfcklg fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfcklg fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfcklg fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfcklg fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfcklg fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfcklg fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfcklg fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfcklg fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfcklg fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfcklg fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfcklg fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfcklg fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfcklg fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfcklg fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfcklg fcc0,cc3,cc5,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfcklg fcc0,cc3,cc5,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfcklg fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfcklg fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfcklg fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfcklg fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfcklg fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfcklg fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfcklg fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfcklg fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfcklg fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfcklg fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfcklg fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfcklg fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfcklg fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfcklg fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfcklg fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfcklg fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfcklg fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfcklg fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfcklg fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfcklg fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfcklg fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfcklg fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfcklg fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfcklg fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfcklg fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfcklg fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfcklg fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfcklg fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfcklg fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfcklg fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfcklg fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfcklg fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfcklg fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfcklg fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfcklg fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfcklg fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfcklg fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfcklg fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfcklg fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfcklg fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfcklg fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfcklg fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfcklg fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfcklg fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfcklg fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfcklg fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfcklg fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfcklg fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfcklg fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfcklg fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfcklg fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfcklg fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfcklg fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfcklg fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/cfcklt.cgs b/sim/testsuite/sim/frv/cfcklt.cgs new file mode 100644 index 0000000..ffabcd2 --- /dev/null +++ b/sim/testsuite/sim/frv/cfcklt.cgs @@ -0,0 +1,490 @@ +# frv testcase for cfcklt $FCCi,$CCj_float,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cfcklt +cfcklt: + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfcklt fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfcklt fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfcklt fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfcklt fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfcklt fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfcklt fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfcklt fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfcklt fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfcklt fcc0,cc3,cc4,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfcklt fcc0,cc3,cc4,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfcklt fcc0,cc3,cc4,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfcklt fcc0,cc3,cc4,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfcklt fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfcklt fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfcklt fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfcklt fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfcklt fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfcklt fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfcklt fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfcklt fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfcklt fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfcklt fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfcklt fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfcklt fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfcklt fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfcklt fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfcklt fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfcklt fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfcklt fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfcklt fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfcklt fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfcklt fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfcklt fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfcklt fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfcklt fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfcklt fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfcklt fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfcklt fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfcklt fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfcklt fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfcklt fcc0,cc3,cc5,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfcklt fcc0,cc3,cc5,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfcklt fcc0,cc3,cc5,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfcklt fcc0,cc3,cc5,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfcklt fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfcklt fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfcklt fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfcklt fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfcklt fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfcklt fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfcklt fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfcklt fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfcklt fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfcklt fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfcklt fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfcklt fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfcklt fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfcklt fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfcklt fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfcklt fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfcklt fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfcklt fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfcklt fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfcklt fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfcklt fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfcklt fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfcklt fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfcklt fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfcklt fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfcklt fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfcklt fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfcklt fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfcklt fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfcklt fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfcklt fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfcklt fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfcklt fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfcklt fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfcklt fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfcklt fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfcklt fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfcklt fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfcklt fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfcklt fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfcklt fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfcklt fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfcklt fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfcklt fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfcklt fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfcklt fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfcklt fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfcklt fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfcklt fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfcklt fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfcklt fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfcklt fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/cfckne.cgs b/sim/testsuite/sim/frv/cfckne.cgs new file mode 100644 index 0000000..da6846f --- /dev/null +++ b/sim/testsuite/sim/frv/cfckne.cgs @@ -0,0 +1,490 @@ +# frv testcase for cfckne $FCCi,$CCj_float,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cfckne +cfckne: + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckne fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckne fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckne fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckne fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckne fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckne fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckne fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckne fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckne fcc0,cc3,cc4,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckne fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckne fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckne fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckne fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckne fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckne fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckne fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckne fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckne fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckne fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckne fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckne fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckne fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckne fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckne fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckne fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckne fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckne fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckne fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckne fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckne fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckne fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckne fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckne fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckne fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckne fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckne fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckne fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckne fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckne fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckne fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckne fcc0,cc3,cc5,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckne fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckne fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckne fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckne fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckne fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckne fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckne fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckne fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckne fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckne fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckne fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckne fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckne fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckne fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckne fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckne fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckne fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckne fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckne fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckne fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckne fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckne fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckne fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckne fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckne fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckne fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckne fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckne fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckne fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckne fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckne fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckne fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckne fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckne fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckne fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckne fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckne fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckne fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckne fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckne fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckne fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckne fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckne fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckne fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckne fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckne fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckne fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckne fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckne fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckne fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckne fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckne fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckne fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckne fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckne fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/cfckno.cgs b/sim/testsuite/sim/frv/cfckno.cgs new file mode 100644 index 0000000..5681960 --- /dev/null +++ b/sim/testsuite/sim/frv/cfckno.cgs @@ -0,0 +1,490 @@ +# frv testcase for cfckno $CCj_float,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cfckno +cfckno: + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckno cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckno cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckno cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckno cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckno cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckno cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckno cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckno cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckno cc3,cc4,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckno cc3,cc4,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckno cc3,cc4,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckno cc3,cc4,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckno cc3,cc4,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckno cc3,cc4,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckno cc3,cc4,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckno cc3,cc4,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckno cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckno cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckno cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckno cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckno cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckno cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckno cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckno cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckno cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckno cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckno cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckno cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckno cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckno cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckno cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckno cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckno cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckno cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckno cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckno cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckno cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckno cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckno cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckno cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckno cc3,cc5,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckno cc3,cc5,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckno cc3,cc5,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckno cc3,cc5,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckno cc3,cc5,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckno cc3,cc5,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckno cc3,cc5,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckno cc3,cc5,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckno cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckno cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckno cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckno cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckno cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckno cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckno cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckno cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckno cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckno cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckno cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckno cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckno cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckno cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckno cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckno cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckno cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckno cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckno cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckno cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckno cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckno cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckno cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckno cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckno cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckno cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckno cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckno cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckno cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckno cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckno cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckno cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckno cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckno cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckno cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckno cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckno cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckno cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckno cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckno cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckno cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckno cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckno cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckno cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckno cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckno cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckno cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckno cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/cfcko.cgs b/sim/testsuite/sim/frv/cfcko.cgs new file mode 100644 index 0000000..ac55fc3 --- /dev/null +++ b/sim/testsuite/sim/frv/cfcko.cgs @@ -0,0 +1,490 @@ +# frv testcase for cfcko $FCCi,$CCj_float,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cfcko +cfcko: + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfcko fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfcko fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfcko fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfcko fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfcko fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfcko fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfcko fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfcko fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfcko fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfcko fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfcko fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfcko fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfcko fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfcko fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfcko fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfcko fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfcko fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfcko fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfcko fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfcko fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfcko fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfcko fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfcko fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfcko fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfcko fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfcko fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfcko fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfcko fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfcko fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfcko fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfcko fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfcko fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfcko fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfcko fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfcko fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfcko fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfcko fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfcko fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfcko fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfcko fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfcko fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfcko fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfcko fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfcko fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfcko fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfcko fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfcko fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfcko fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfcko fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfcko fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfcko fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfcko fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfcko fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfcko fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfcko fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfcko fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfcko fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfcko fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfcko fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfcko fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfcko fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfcko fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfcko fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfcko fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfcko fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfcko fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfcko fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfcko fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfcko fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfcko fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfcko fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfcko fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfcko fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfcko fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfcko fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfcko fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfcko fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfcko fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfcko fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfcko fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfcko fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfcko fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfcko fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfcko fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfcko fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfcko fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfcko fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfcko fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfcko fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfcko fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfcko fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfcko fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfcko fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfcko fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfcko fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfcko fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/cfckra.cgs b/sim/testsuite/sim/frv/cfckra.cgs new file mode 100644 index 0000000..0cabd8f --- /dev/null +++ b/sim/testsuite/sim/frv/cfckra.cgs @@ -0,0 +1,490 @@ +# frv testcase for cfckra $CCj_float,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cfckra +cfckra: + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckra cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckra cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckra cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckra cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckra cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckra cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckra cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckra cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckra cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckra cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckra cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckra cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckra cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckra cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckra cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckra cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckra cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckra cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckra cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckra cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckra cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckra cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckra cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckra cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckra cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckra cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckra cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckra cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckra cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckra cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckra cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckra cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckra cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckra cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckra cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckra cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckra cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckra cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckra cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckra cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckra cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckra cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckra cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckra cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckra cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckra cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckra cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckra cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckra cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckra cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckra cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckra cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckra cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckra cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckra cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckra cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckra cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckra cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckra cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckra cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckra cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckra cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckra cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckra cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckra cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckra cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckra cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckra cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckra cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckra cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckra cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckra cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckra cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckra cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckra cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckra cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckra cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckra cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckra cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckra cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckra cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckra cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckra cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckra cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckra cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckra cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckra cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckra cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckra cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckra cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckra cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckra cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckra cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckra cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckra cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckra cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/cfcku.cgs b/sim/testsuite/sim/frv/cfcku.cgs new file mode 100644 index 0000000..0f56e7e --- /dev/null +++ b/sim/testsuite/sim/frv/cfcku.cgs @@ -0,0 +1,490 @@ +# frv testcase for cfcku $FCCi,$CCj_float,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cfcku +cfcku: + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfcku fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfcku fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfcku fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfcku fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfcku fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfcku fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfcku fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfcku fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfcku fcc0,cc3,cc4,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfcku fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfcku fcc0,cc3,cc4,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfcku fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfcku fcc0,cc3,cc4,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfcku fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfcku fcc0,cc3,cc4,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfcku fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfcku fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfcku fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfcku fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfcku fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfcku fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfcku fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfcku fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfcku fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfcku fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfcku fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfcku fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfcku fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfcku fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfcku fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfcku fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfcku fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfcku fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfcku fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfcku fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfcku fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfcku fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfcku fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfcku fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfcku fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfcku fcc0,cc3,cc5,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfcku fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfcku fcc0,cc3,cc5,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfcku fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfcku fcc0,cc3,cc5,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfcku fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfcku fcc0,cc3,cc5,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfcku fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfcku fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfcku fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfcku fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfcku fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfcku fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfcku fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfcku fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfcku fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfcku fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfcku fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfcku fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfcku fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfcku fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfcku fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfcku fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfcku fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfcku fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfcku fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfcku fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfcku fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfcku fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfcku fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfcku fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfcku fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfcku fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfcku fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfcku fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfcku fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfcku fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfcku fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfcku fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfcku fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfcku fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfcku fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfcku fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfcku fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfcku fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfcku fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfcku fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfcku fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfcku fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfcku fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfcku fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfcku fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfcku fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfcku fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfcku fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfcku fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/cfckue.cgs b/sim/testsuite/sim/frv/cfckue.cgs new file mode 100644 index 0000000..447c2ba --- /dev/null +++ b/sim/testsuite/sim/frv/cfckue.cgs @@ -0,0 +1,490 @@ +# frv testcase for cfckue $FCCi,$CCj_float,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cfckue +cfckue: + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckue fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckue fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckue fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckue fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckue fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckue fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckue fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckue fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckue fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckue fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckue fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckue fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckue fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckue fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckue fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckue fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckue fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckue fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckue fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckue fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckue fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckue fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckue fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckue fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckue fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckue fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckue fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckue fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckue fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckue fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckue fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckue fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckue fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckue fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckue fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckue fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckue fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckue fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckue fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckue fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckue fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckue fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckue fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckue fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckue fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckue fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckue fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckue fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckue fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckue fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckue fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckue fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckue fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckue fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckue fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckue fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckue fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckue fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckue fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckue fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckue fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckue fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckue fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckue fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckue fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckue fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckue fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckue fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckue fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckue fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckue fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckue fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckue fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckue fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckue fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckue fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckue fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckue fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckue fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckue fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckue fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckue fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckue fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckue fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckue fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckue fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckue fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckue fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckue fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckue fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckue fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckue fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckue fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckue fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckue fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckue fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/cfckug.cgs b/sim/testsuite/sim/frv/cfckug.cgs new file mode 100644 index 0000000..7442f84 --- /dev/null +++ b/sim/testsuite/sim/frv/cfckug.cgs @@ -0,0 +1,490 @@ +# frv testcase for cfckug $FCCi,$CCj_float,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cfckug +cfckug: + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckug fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckug fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckug fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckug fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckug fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckug fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckug fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckug fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckug fcc0,cc3,cc4,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckug fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckug fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckug fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckug fcc0,cc3,cc4,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckug fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckug fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckug fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckug fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckug fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckug fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckug fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckug fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckug fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckug fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckug fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckug fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckug fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckug fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckug fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckug fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckug fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckug fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckug fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckug fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckug fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckug fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckug fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckug fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckug fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckug fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckug fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckug fcc0,cc3,cc5,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckug fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckug fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckug fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckug fcc0,cc3,cc5,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckug fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckug fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckug fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckug fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckug fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckug fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckug fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckug fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckug fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckug fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckug fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckug fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckug fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckug fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckug fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckug fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckug fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckug fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckug fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckug fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckug fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckug fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckug fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckug fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckug fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckug fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckug fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckug fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckug fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckug fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckug fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckug fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckug fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckug fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckug fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckug fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckug fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckug fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckug fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckug fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckug fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckug fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckug fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckug fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckug fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckug fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckug fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckug fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckug fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckug fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckug fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/cfckuge.cgs b/sim/testsuite/sim/frv/cfckuge.cgs new file mode 100644 index 0000000..8eaf92f --- /dev/null +++ b/sim/testsuite/sim/frv/cfckuge.cgs @@ -0,0 +1,490 @@ +# frv testcase for cfckuge $FCCi,$CCj_float,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cfckuge +cfckuge: + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckuge fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckuge fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckuge fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckuge fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckuge fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckuge fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckuge fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckuge fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckuge fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckuge fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckuge fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckuge fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckuge fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckuge fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckuge fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckuge fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckuge fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckuge fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckuge fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckuge fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckuge fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckuge fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckuge fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckuge fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckuge fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckuge fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckuge fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckuge fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckuge fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckuge fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckuge fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckuge fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckuge fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckuge fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckuge fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckuge fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckuge fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckuge fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckuge fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckuge fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckuge fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckuge fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckuge fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckuge fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckuge fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckuge fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckuge fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckuge fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckuge fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckuge fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckuge fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckuge fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckuge fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckuge fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckuge fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckuge fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckuge fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckuge fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckuge fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckuge fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckuge fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckuge fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckuge fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckuge fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckuge fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckuge fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckuge fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckuge fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckuge fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckuge fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckuge fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckuge fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckuge fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckuge fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckuge fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckuge fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckuge fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckuge fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckuge fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckuge fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckuge fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckuge fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckuge fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckuge fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckuge fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckuge fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckuge fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckuge fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckuge fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckuge fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckuge fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckuge fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckuge fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckuge fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckuge fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckuge fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/cfckul.cgs b/sim/testsuite/sim/frv/cfckul.cgs new file mode 100644 index 0000000..5945a8a --- /dev/null +++ b/sim/testsuite/sim/frv/cfckul.cgs @@ -0,0 +1,410 @@ +# frv testcase for cfckul $FCCi,$CCj_float,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cfckul +cfckul: + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckul fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckul fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckul fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckul fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckul fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckul fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckul fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckul fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckul fcc0,cc3,cc4,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckul fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckul fcc0,cc3,cc4,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckul fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckul fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckul fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckul fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckul fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckul fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckul fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckul fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckul fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckul fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckul fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckul fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckul fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckul fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckul fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckul fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckul fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckul fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckul fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckul fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckul fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckul fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckul fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckul fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckul fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckul fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckul fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckul fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckul fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckul fcc0,cc3,cc5,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckul fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckul fcc0,cc3,cc5,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckul fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckul fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckul fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckul fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckul fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckul fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckul fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckul fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckul fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckul fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckul fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckul fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckul fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckul fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckul fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckul fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckul fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckul fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckul fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckul fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckul fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckul fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckul fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckul fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckul fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckul fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckul fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckul fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckul fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckul fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckul fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckul fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckul fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckul fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckul fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckul fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckul fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/cfckule.cgs b/sim/testsuite/sim/frv/cfckule.cgs new file mode 100644 index 0000000..aaf655e --- /dev/null +++ b/sim/testsuite/sim/frv/cfckule.cgs @@ -0,0 +1,490 @@ +# frv testcase for cfckule $FCCi,$CCj_float,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cfckule +cfckule: + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckule fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckule fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckule fcc0,cc3,cc0,1 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckule fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckule fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckule fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckule fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckule fcc0,cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckule fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckule fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckule fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckule fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckule fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckule fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckule fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckule fcc0,cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckule fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckule fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckule fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckule fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckule fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckule fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckule fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckule fcc0,cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckule fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckule fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckule fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckule fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckule fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckule fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckule fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckule fcc0,cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckule fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckule fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckule fcc0,cc3,cc1,0 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckule fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckule fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckule fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckule fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckule fcc0,cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckule fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckule fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckule fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckule fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckule fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckule fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckule fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckule fcc0,cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckule fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckule fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckule fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckule fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckule fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckule fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckule fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckule fcc0,cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckule fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckule fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckule fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckule fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckule fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckule fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckule fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckule fcc0,cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckule fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckule fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckule fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckule fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckule fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckule fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckule fcc0,cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckule fcc0,cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckule fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckule fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckule fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckule fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckule fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckule fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckule fcc0,cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckule fcc0,cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckule fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckule fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckule fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckule fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckule fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckule fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckule fcc0,cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckule fcc0,cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckule fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckule fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckule fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckule fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckule fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckule fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckule fcc0,cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckule fcc0,cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/cfcmps.cgs b/sim/testsuite/sim/frv/cfcmps.cgs new file mode 100644 index 0000000..168e618 --- /dev/null +++ b/sim/testsuite/sim/frv/cfcmps.cgs @@ -0,0 +1,3542 @@ +# frv testcase for cfcmps $FRi,$FRj,$FCCi,$CCi,$cond_2 +# mach: fr500 fr550 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global cfcmps +cfcmps: + set_spr_immed 0x1b1b,cccr + + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr0,fr0,fcc0,cc0,1 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr4,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr8,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr12,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr16,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr20,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr24,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr28,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr32,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr36,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr40,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr44,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr48,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr52,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr0,fr56,fcc0,cc0,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr0,fr60,fcc0,cc0,1 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr4,fr0,fcc0,cc0,1 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr4,fr4,fcc0,cc0,1 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr8,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr12,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr16,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr20,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr24,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr28,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr32,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr36,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr40,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr44,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr48,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr52,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr4,fr56,fcc0,cc0,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr4,fr60,fcc0,cc0,1 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr8,fr0,fcc0,cc0,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr8,fr4,fcc0,cc0,1 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr8,fr8,fcc0,cc0,1 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr12,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr16,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr20,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr24,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr28,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr32,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr36,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr40,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr44,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr48,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr52,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr8,fr56,fcc0,cc0,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr8,fr60,fcc0,cc0,1 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr12,fr0,fcc0,cc0,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr12,fr4,fcc0,cc0,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr12,fr8,fcc0,cc0,1 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr12,fr12,fcc0,cc0,1 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr16,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr20,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr24,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr28,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr32,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr36,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr40,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr44,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr48,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr52,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr12,fr56,fcc0,cc0,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr12,fr60,fcc0,cc0,1 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr16,fr0,fcc0,cc0,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr16,fr4,fcc0,cc0,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr16,fr8,fcc0,cc0,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr16,fr12,fcc0,cc0,1 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr16,fr16,fcc0,cc0,1 + test_fcc 0x8,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr16,fr20,fcc0,cc0,1 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr24,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr28,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr32,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr36,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr40,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr44,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr48,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr52,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr16,fr56,fcc0,cc0,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr16,fr60,fcc0,cc0,1 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr20,fr0,fcc0,cc0,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr20,fr4,fcc0,cc0,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr20,fr8,fcc0,cc0,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr20,fr12,fcc0,cc0,1 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr20,fr16,fcc0,cc0,1 + test_fcc 0x8,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr20,fr20,fcc0,cc0,1 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr24,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr28,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr32,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr36,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr40,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr44,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr48,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr52,fcc0,cc0,1 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr20,fr56,fcc0,cc0,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr20,fr60,fcc0,cc0,1 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr0,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr4,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr8,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr12,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr16,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr20,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr24,fr24,fcc0,cc4,1 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr28,fcc0,cc4,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr32,fcc0,cc4,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr36,fcc0,cc4,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr40,fcc0,cc4,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr44,fcc0,cc4,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr48,fcc0,cc4,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr52,fcc0,cc4,1 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr24,fr56,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr24,fr60,fcc0,cc4,1 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr0,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr4,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr8,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr12,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr16,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr20,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr24,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr28,fr28,fcc0,cc4,1 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr32,fcc0,cc4,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr36,fcc0,cc4,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr40,fcc0,cc4,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr44,fcc0,cc4,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr48,fcc0,cc4,1 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr52,fcc0,cc4,1 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr28,fr56,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr28,fr60,fcc0,cc4,1 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr0,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr4,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr8,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr12,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr16,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr20,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr24,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr28,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr32,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr36,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr40,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr44,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr48,fr48,fcc0,cc4,1 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr48,fr52,fcc0,cc4,1 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr48,fr56,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr48,fr60,fcc0,cc4,1 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr0,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr4,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr8,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr12,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr16,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr20,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr24,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr28,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr32,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr36,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr40,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr44,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr48,fcc0,cc4,1 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr52,fr52,fcc0,cc4,1 + test_fcc 0x8,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr52,fr56,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr52,fr60,fcc0,cc4,1 + test_fcc 0x1,0 + + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr0,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr4,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr8,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr12,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr16,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr20,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr24,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr28,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr32,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr36,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr40,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr44,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr48,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr52,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr56,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr60,fcc0,cc4,1 + test_fcc 0x1,0 + + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr0,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr4,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr8,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr12,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr16,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr20,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr24,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr28,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr32,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr36,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr40,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr44,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr48,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr52,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr56,fcc0,cc4,1 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr60,fcc0,cc4,1 + test_fcc 0x1,0 +; + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr0,fr0,fcc0,cc1,0 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr4,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr8,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr12,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr16,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr20,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr24,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr28,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr32,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr36,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr40,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr44,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr48,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr52,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr0,fr56,fcc0,cc1,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr0,fr60,fcc0,cc1,0 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr4,fr0,fcc0,cc1,0 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr4,fr4,fcc0,cc1,0 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr8,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr12,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr16,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr20,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr24,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr28,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr32,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr36,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr40,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr44,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr48,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr52,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr4,fr56,fcc0,cc1,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr4,fr60,fcc0,cc1,0 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr8,fr0,fcc0,cc1,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr8,fr4,fcc0,cc1,0 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr8,fr8,fcc0,cc1,0 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr12,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr16,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr20,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr24,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr28,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr32,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr36,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr40,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr44,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr48,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr52,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr8,fr56,fcc0,cc1,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr8,fr60,fcc0,cc1,0 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr12,fr0,fcc0,cc1,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr12,fr4,fcc0,cc1,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr12,fr8,fcc0,cc1,0 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr12,fr12,fcc0,cc1,0 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr16,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr20,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr24,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr28,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr32,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr36,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr40,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr44,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr48,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr52,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr12,fr56,fcc0,cc1,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr12,fr60,fcc0,cc1,0 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr16,fr0,fcc0,cc1,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr16,fr4,fcc0,cc1,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr16,fr8,fcc0,cc1,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr16,fr12,fcc0,cc1,0 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr16,fr16,fcc0,cc1,0 + test_fcc 0x8,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr16,fr20,fcc0,cc1,0 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr24,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr28,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr32,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr36,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr40,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr44,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr48,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr52,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr16,fr56,fcc0,cc1,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr16,fr60,fcc0,cc1,0 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr20,fr0,fcc0,cc1,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr20,fr4,fcc0,cc1,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr20,fr8,fcc0,cc1,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr20,fr12,fcc0,cc1,0 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr20,fr16,fcc0,cc1,0 + test_fcc 0x8,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr20,fr20,fcc0,cc1,0 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr24,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr28,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr32,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr36,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr40,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr44,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr48,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr52,fcc0,cc1,0 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr20,fr56,fcc0,cc1,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr20,fr60,fcc0,cc1,0 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr0,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr4,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr8,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr12,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr16,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr20,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr24,fr24,fcc0,cc5,0 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr28,fcc0,cc5,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr32,fcc0,cc5,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr36,fcc0,cc5,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr40,fcc0,cc5,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr44,fcc0,cc5,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr48,fcc0,cc5,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr52,fcc0,cc5,0 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr24,fr56,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr24,fr60,fcc0,cc5,0 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr0,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr4,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr8,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr12,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr16,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr20,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr24,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr28,fr28,fcc0,cc5,0 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr32,fcc0,cc5,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr36,fcc0,cc5,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr40,fcc0,cc5,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr44,fcc0,cc5,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr48,fcc0,cc5,0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr52,fcc0,cc5,0 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr28,fr56,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr28,fr60,fcc0,cc5,0 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr0,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr4,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr8,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr12,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr16,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr20,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr24,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr28,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr32,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr36,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr40,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr44,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr48,fr48,fcc0,cc5,0 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr48,fr52,fcc0,cc5,0 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr48,fr56,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr48,fr60,fcc0,cc5,0 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr0,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr4,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr8,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr12,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr16,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr20,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr24,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr28,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr32,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr36,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr40,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr44,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr48,fcc0,cc5,0 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr52,fr52,fcc0,cc5,0 + test_fcc 0x8,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr52,fr56,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr52,fr60,fcc0,cc5,0 + test_fcc 0x1,0 + + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr0,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr4,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr8,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr12,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr16,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr20,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr24,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr28,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr32,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr36,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr40,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr44,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr48,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr52,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr56,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr60,fcc0,cc5,0 + test_fcc 0x1,0 + + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr0,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr4,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr8,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr12,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr16,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr20,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr24,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr28,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr32,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr36,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr40,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr44,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr48,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr52,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr56,fcc0,cc5,0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr60,fcc0,cc5,0 + test_fcc 0x1,0 +; + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr0,fr0,fcc0,cc0,0 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr4,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr8,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr12,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr16,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr20,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr24,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr28,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr32,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr36,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr40,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr44,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr48,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr52,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr0,fr56,fcc0,cc0,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr0,fr60,fcc0,cc0,0 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr4,fr0,fcc0,cc0,0 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr4,fr4,fcc0,cc0,0 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr8,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr12,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr16,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr20,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr24,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr28,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr32,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr36,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr40,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr44,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr48,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr52,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr4,fr56,fcc0,cc0,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr4,fr60,fcc0,cc0,0 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr8,fr0,fcc0,cc0,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr8,fr4,fcc0,cc0,0 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr8,fr8,fcc0,cc0,0 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr12,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr16,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr20,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr24,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr28,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr32,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr36,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr40,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr44,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr48,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr52,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr8,fr56,fcc0,cc0,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr8,fr60,fcc0,cc0,0 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr12,fr0,fcc0,cc0,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr12,fr4,fcc0,cc0,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr12,fr8,fcc0,cc0,0 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr12,fr12,fcc0,cc0,0 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr16,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr20,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr24,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr28,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr32,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr36,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr40,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr44,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr48,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr52,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr12,fr56,fcc0,cc0,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr12,fr60,fcc0,cc0,0 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr16,fr0,fcc0,cc0,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr16,fr4,fcc0,cc0,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr16,fr8,fcc0,cc0,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr16,fr12,fcc0,cc0,0 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr16,fr16,fcc0,cc0,0 + test_fcc 0x7,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr16,fr20,fcc0,cc0,0 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr24,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr28,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr32,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr36,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr40,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr44,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr48,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr52,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr16,fr56,fcc0,cc0,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr16,fr60,fcc0,cc0,0 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr20,fr0,fcc0,cc0,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr20,fr4,fcc0,cc0,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr20,fr8,fcc0,cc0,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr20,fr12,fcc0,cc0,0 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr20,fr16,fcc0,cc0,0 + test_fcc 0x7,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr20,fr20,fcc0,cc0,0 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr24,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr28,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr32,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr36,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr40,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr44,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr48,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr52,fcc0,cc0,0 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr20,fr56,fcc0,cc0,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr20,fr60,fcc0,cc0,0 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr0,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr4,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr8,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr12,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr16,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr20,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr24,fr24,fcc0,cc4,0 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr28,fcc0,cc4,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr32,fcc0,cc4,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr36,fcc0,cc4,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr40,fcc0,cc4,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr44,fcc0,cc4,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr48,fcc0,cc4,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr52,fcc0,cc4,0 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr24,fr56,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr24,fr60,fcc0,cc4,0 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr0,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr4,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr8,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr12,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr16,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr20,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr24,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr28,fr28,fcc0,cc4,0 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr32,fcc0,cc4,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr36,fcc0,cc4,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr40,fcc0,cc4,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr44,fcc0,cc4,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr48,fcc0,cc4,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr52,fcc0,cc4,0 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr28,fr56,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr28,fr60,fcc0,cc4,0 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr0,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr4,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr8,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr12,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr16,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr20,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr24,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr28,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr32,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr36,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr40,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr44,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr48,fr48,fcc0,cc4,0 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr48,fr52,fcc0,cc4,0 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr48,fr56,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr48,fr60,fcc0,cc4,0 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr0,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr4,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr8,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr12,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr16,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr20,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr24,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr28,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr32,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr36,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr40,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr44,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr48,fcc0,cc4,0 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr52,fr52,fcc0,cc4,0 + test_fcc 0x7,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr52,fr56,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr52,fr60,fcc0,cc4,0 + test_fcc 0xe,0 + + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr0,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr4,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr8,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr12,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr16,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr20,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr24,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr28,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr32,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr36,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr40,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr44,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr48,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr52,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr56,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr60,fcc0,cc4,0 + test_fcc 0xe,0 + + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr0,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr4,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr8,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr12,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr16,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr20,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr24,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr28,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr32,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr36,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr40,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr44,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr48,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr52,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr56,fcc0,cc4,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr60,fcc0,cc4,0 + test_fcc 0xe,0 +; + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr0,fr0,fcc0,cc1,1 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr4,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr8,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr12,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr16,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr20,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr24,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr28,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr32,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr36,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr40,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr44,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr48,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr52,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr0,fr56,fcc0,cc1,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr0,fr60,fcc0,cc1,1 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr4,fr0,fcc0,cc1,1 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr4,fr4,fcc0,cc1,1 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr8,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr12,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr16,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr20,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr24,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr28,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr32,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr36,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr40,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr44,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr48,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr52,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr4,fr56,fcc0,cc1,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr4,fr60,fcc0,cc1,1 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr8,fr0,fcc0,cc1,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr8,fr4,fcc0,cc1,1 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr8,fr8,fcc0,cc1,1 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr12,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr16,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr20,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr24,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr28,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr32,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr36,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr40,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr44,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr48,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr52,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr8,fr56,fcc0,cc1,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr8,fr60,fcc0,cc1,1 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr12,fr0,fcc0,cc1,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr12,fr4,fcc0,cc1,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr12,fr8,fcc0,cc1,1 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr12,fr12,fcc0,cc1,1 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr16,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr20,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr24,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr28,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr32,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr36,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr40,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr44,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr48,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr52,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr12,fr56,fcc0,cc1,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr12,fr60,fcc0,cc1,1 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr16,fr0,fcc0,cc1,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr16,fr4,fcc0,cc1,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr16,fr8,fcc0,cc1,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr16,fr12,fcc0,cc1,1 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr16,fr16,fcc0,cc1,1 + test_fcc 0x7,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr16,fr20,fcc0,cc1,1 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr24,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr28,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr32,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr36,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr40,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr44,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr48,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr52,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr16,fr56,fcc0,cc1,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr16,fr60,fcc0,cc1,1 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr20,fr0,fcc0,cc1,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr20,fr4,fcc0,cc1,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr20,fr8,fcc0,cc1,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr20,fr12,fcc0,cc1,1 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr20,fr16,fcc0,cc1,1 + test_fcc 0x7,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr20,fr20,fcc0,cc1,1 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr24,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr28,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr32,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr36,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr40,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr44,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr48,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr52,fcc0,cc1,1 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr20,fr56,fcc0,cc1,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr20,fr60,fcc0,cc1,1 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr0,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr4,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr8,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr12,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr16,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr20,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr24,fr24,fcc0,cc5,1 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr28,fcc0,cc5,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr32,fcc0,cc5,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr36,fcc0,cc5,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr40,fcc0,cc5,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr44,fcc0,cc5,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr48,fcc0,cc5,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr52,fcc0,cc5,1 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr24,fr56,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr24,fr60,fcc0,cc5,1 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr0,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr4,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr8,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr12,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr16,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr20,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr24,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr28,fr28,fcc0,cc5,1 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr32,fcc0,cc5,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr36,fcc0,cc5,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr40,fcc0,cc5,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr44,fcc0,cc5,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr48,fcc0,cc5,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr52,fcc0,cc5,1 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr28,fr56,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr28,fr60,fcc0,cc5,1 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr0,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr4,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr8,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr12,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr16,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr20,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr24,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr28,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr32,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr36,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr40,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr44,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr48,fr48,fcc0,cc5,1 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr48,fr52,fcc0,cc5,1 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr48,fr56,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr48,fr60,fcc0,cc5,1 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr0,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr4,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr8,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr12,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr16,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr20,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr24,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr28,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr32,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr36,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr40,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr44,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr48,fcc0,cc5,1 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr52,fr52,fcc0,cc5,1 + test_fcc 0x7,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr52,fr56,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr52,fr60,fcc0,cc5,1 + test_fcc 0xe,0 + + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr0,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr4,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr8,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr12,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr16,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr20,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr24,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr28,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr32,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr36,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr40,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr44,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr48,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr52,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr56,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr60,fcc0,cc5,1 + test_fcc 0xe,0 + + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr0,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr4,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr8,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr12,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr16,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr20,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr24,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr28,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr32,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr36,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr40,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr44,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr48,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr52,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr56,fcc0,cc5,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr60,fcc0,cc5,1 + test_fcc 0xe,0 +; + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr0,fr0,fcc0,cc2,1 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr4,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr8,fcc0,cc2,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr12,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr16,fcc0,cc2,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr20,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr24,fcc0,cc2,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr28,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr32,fcc0,cc2,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr36,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr40,fcc0,cc2,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr44,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr48,fcc0,cc2,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr52,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr0,fr56,fcc0,cc2,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr0,fr60,fcc0,cc2,0 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr4,fr0,fcc0,cc2,1 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr4,fr4,fcc0,cc2,0 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr8,fcc0,cc2,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr12,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr16,fcc0,cc2,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr20,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr24,fcc0,cc2,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr28,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr32,fcc0,cc2,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr36,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr40,fcc0,cc2,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr44,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr48,fcc0,cc2,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr52,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr4,fr56,fcc0,cc2,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr4,fr60,fcc0,cc2,0 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr8,fr0,fcc0,cc2,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr8,fr4,fcc0,cc2,0 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr8,fr8,fcc0,cc2,1 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr12,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr16,fcc0,cc2,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr20,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr24,fcc0,cc2,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr28,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr32,fcc0,cc2,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr36,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr40,fcc0,cc2,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr44,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr48,fcc0,cc2,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr52,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr8,fr56,fcc0,cc2,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr8,fr60,fcc0,cc2,0 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr12,fr0,fcc0,cc2,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr12,fr4,fcc0,cc2,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr12,fr8,fcc0,cc2,1 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr12,fr12,fcc0,cc2,0 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr16,fcc0,cc2,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr20,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr24,fcc0,cc2,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr28,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr32,fcc0,cc2,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr36,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr40,fcc0,cc2,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr44,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr48,fcc0,cc2,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr52,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr12,fr56,fcc0,cc2,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr12,fr60,fcc0,cc2,0 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr16,fr0,fcc0,cc2,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr16,fr4,fcc0,cc2,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr16,fr8,fcc0,cc2,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr16,fr12,fcc0,cc2,0 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr16,fr16,fcc0,cc2,1 + test_fcc 0x7,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr16,fr20,fcc0,cc2,0 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr24,fcc0,cc2,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr28,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr32,fcc0,cc2,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr36,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr40,fcc0,cc2,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr44,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr48,fcc0,cc2,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr52,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr16,fr56,fcc0,cc2,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr16,fr60,fcc0,cc2,0 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr20,fr0,fcc0,cc2,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr20,fr4,fcc0,cc2,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr20,fr8,fcc0,cc2,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr20,fr12,fcc0,cc2,0 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr20,fr16,fcc0,cc2,1 + test_fcc 0x7,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr20,fr20,fcc0,cc2,0 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr24,fcc0,cc2,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr28,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr32,fcc0,cc2,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr36,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr40,fcc0,cc2,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr44,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr48,fcc0,cc2,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr52,fcc0,cc2,0 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr20,fr56,fcc0,cc2,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr20,fr60,fcc0,cc2,0 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr0,fcc0,cc6,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr4,fcc0,cc6,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr8,fcc0,cc6,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr12,fcc0,cc6,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr16,fcc0,cc6,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr20,fcc0,cc6,0 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr24,fr24,fcc0,cc6,1 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr28,fcc0,cc6,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr32,fcc0,cc6,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr36,fcc0,cc6,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr40,fcc0,cc6,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr44,fcc0,cc6,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr48,fcc0,cc6,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr52,fcc0,cc6,0 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr24,fr56,fcc0,cc6,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr24,fr60,fcc0,cc6,0 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr0,fcc0,cc6,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr4,fcc0,cc6,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr8,fcc0,cc6,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr12,fcc0,cc6,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr16,fcc0,cc6,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr20,fcc0,cc6,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr24,fcc0,cc6,1 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr28,fr28,fcc0,cc6,0 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr32,fcc0,cc6,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr36,fcc0,cc6,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr40,fcc0,cc6,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr44,fcc0,cc6,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr48,fcc0,cc6,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr52,fcc0,cc6,0 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr28,fr56,fcc0,cc6,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr28,fr60,fcc0,cc6,0 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr0,fcc0,cc6,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr4,fcc0,cc6,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr8,fcc0,cc6,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr12,fcc0,cc6,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr16,fcc0,cc6,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr20,fcc0,cc6,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr24,fcc0,cc6,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr28,fcc0,cc6,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr32,fcc0,cc6,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr36,fcc0,cc6,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr40,fcc0,cc6,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr44,fcc0,cc6,0 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr48,fr48,fcc0,cc6,1 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr48,fr52,fcc0,cc6,0 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr48,fr56,fcc0,cc6,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr48,fr60,fcc0,cc6,0 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr0,fcc0,cc6,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr4,fcc0,cc6,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr8,fcc0,cc6,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr12,fcc0,cc6,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr16,fcc0,cc6,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr20,fcc0,cc6,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr24,fcc0,cc6,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr28,fcc0,cc6,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr32,fcc0,cc6,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr36,fcc0,cc6,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr40,fcc0,cc6,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr44,fcc0,cc6,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr48,fcc0,cc6,1 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr52,fr52,fcc0,cc6,0 + test_fcc 0x7,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr52,fr56,fcc0,cc6,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr52,fr60,fcc0,cc6,0 + test_fcc 0xe,0 + + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr0,fcc0,cc6,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr4,fcc0,cc6,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr8,fcc0,cc6,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr12,fcc0,cc6,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr16,fcc0,cc6,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr20,fcc0,cc6,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr24,fcc0,cc6,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr28,fcc0,cc6,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr32,fcc0,cc6,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr36,fcc0,cc6,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr40,fcc0,cc6,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr44,fcc0,cc6,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr48,fcc0,cc6,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr52,fcc0,cc6,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr56,fcc0,cc6,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr60,fcc0,cc6,0 + test_fcc 0xe,0 + + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr0,fcc0,cc6,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr4,fcc0,cc6,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr8,fcc0,cc6,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr12,fcc0,cc6,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr16,fcc0,cc6,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr20,fcc0,cc6,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr24,fcc0,cc6,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr28,fcc0,cc6,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr32,fcc0,cc6,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr36,fcc0,cc6,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr40,fcc0,cc6,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr44,fcc0,cc6,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr48,fcc0,cc6,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr52,fcc0,cc6,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr56,fcc0,cc6,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr60,fcc0,cc6,1 + test_fcc 0xe,0 + + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr0,fr0,fcc0,cc3,1 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr4,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr8,fcc0,cc3,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr12,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr16,fcc0,cc3,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr20,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr24,fcc0,cc3,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr28,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr32,fcc0,cc3,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr36,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr40,fcc0,cc3,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr44,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr48,fcc0,cc3,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr0,fr52,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr0,fr56,fcc0,cc3,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr0,fr60,fcc0,cc3,0 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr4,fr0,fcc0,cc3,1 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr4,fr4,fcc0,cc3,0 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr8,fcc0,cc3,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr12,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr16,fcc0,cc3,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr20,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr24,fcc0,cc3,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr28,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr32,fcc0,cc3,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr36,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr40,fcc0,cc3,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr44,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr48,fcc0,cc3,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr4,fr52,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr4,fr56,fcc0,cc3,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr4,fr60,fcc0,cc3,0 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr8,fr0,fcc0,cc3,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr8,fr4,fcc0,cc3,0 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr8,fr8,fcc0,cc3,1 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr12,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr16,fcc0,cc3,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr20,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr24,fcc0,cc3,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr28,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr32,fcc0,cc3,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr36,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr40,fcc0,cc3,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr44,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr48,fcc0,cc3,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr8,fr52,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr8,fr56,fcc0,cc3,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr8,fr60,fcc0,cc3,0 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr12,fr0,fcc0,cc3,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr12,fr4,fcc0,cc3,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr12,fr8,fcc0,cc3,1 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr12,fr12,fcc0,cc3,0 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr16,fcc0,cc3,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr20,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr24,fcc0,cc3,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr28,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr32,fcc0,cc3,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr36,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr40,fcc0,cc3,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr44,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr48,fcc0,cc3,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr12,fr52,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr12,fr56,fcc0,cc3,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr12,fr60,fcc0,cc3,0 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr16,fr0,fcc0,cc3,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr16,fr4,fcc0,cc3,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr16,fr8,fcc0,cc3,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr16,fr12,fcc0,cc3,0 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr16,fr16,fcc0,cc3,1 + test_fcc 0x7,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr16,fr20,fcc0,cc3,0 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr24,fcc0,cc3,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr28,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr32,fcc0,cc3,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr36,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr40,fcc0,cc3,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr44,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr48,fcc0,cc3,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr16,fr52,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr16,fr56,fcc0,cc3,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr16,fr60,fcc0,cc3,0 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr20,fr0,fcc0,cc3,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr20,fr4,fcc0,cc3,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr20,fr8,fcc0,cc3,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr20,fr12,fcc0,cc3,0 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr20,fr16,fcc0,cc3,1 + test_fcc 0x7,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr20,fr20,fcc0,cc3,0 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr24,fcc0,cc3,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr28,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr32,fcc0,cc3,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr36,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr40,fcc0,cc3,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr44,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr48,fcc0,cc3,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr20,fr52,fcc0,cc3,0 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr20,fr56,fcc0,cc3,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr20,fr60,fcc0,cc3,0 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr0,fcc0,cc7,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr4,fcc0,cc7,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr8,fcc0,cc7,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr12,fcc0,cc7,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr16,fcc0,cc7,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr24,fr20,fcc0,cc7,0 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr24,fr24,fcc0,cc7,1 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr28,fcc0,cc7,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr32,fcc0,cc7,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr36,fcc0,cc7,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr40,fcc0,cc7,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr44,fcc0,cc7,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr48,fcc0,cc7,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr24,fr52,fcc0,cc7,0 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr24,fr56,fcc0,cc7,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr24,fr60,fcc0,cc7,0 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr0,fcc0,cc7,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr4,fcc0,cc7,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr8,fcc0,cc7,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr12,fcc0,cc7,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr16,fcc0,cc7,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr20,fcc0,cc7,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr28,fr24,fcc0,cc7,1 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr28,fr28,fcc0,cc7,0 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr32,fcc0,cc7,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr36,fcc0,cc7,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr40,fcc0,cc7,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr44,fcc0,cc7,0 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr48,fcc0,cc7,1 + test_fcc 0xb,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr28,fr52,fcc0,cc7,0 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr28,fr56,fcc0,cc7,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr28,fr60,fcc0,cc7,0 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr0,fcc0,cc7,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr4,fcc0,cc7,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr8,fcc0,cc7,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr12,fcc0,cc7,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr16,fcc0,cc7,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr20,fcc0,cc7,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr24,fcc0,cc7,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr28,fcc0,cc7,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr32,fcc0,cc7,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr36,fcc0,cc7,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr40,fcc0,cc7,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr48,fr44,fcc0,cc7,0 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr48,fr48,fcc0,cc7,1 + test_fcc 0x7,0 + set_fcc 0xb,0 ; Set mask opposite of expected + cfcmps fr48,fr52,fcc0,cc7,0 + test_fcc 0xb,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr48,fr56,fcc0,cc7,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr48,fr60,fcc0,cc7,0 + test_fcc 0xe,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr0,fcc0,cc7,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr4,fcc0,cc7,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr8,fcc0,cc7,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr12,fcc0,cc7,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr16,fcc0,cc7,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr20,fcc0,cc7,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr24,fcc0,cc7,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr28,fcc0,cc7,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr32,fcc0,cc7,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr36,fcc0,cc7,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr40,fcc0,cc7,1 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr44,fcc0,cc7,0 + test_fcc 0xd,0 + set_fcc 0xd,0 ; Set mask opposite of expected + cfcmps fr52,fr48,fcc0,cc7,1 + test_fcc 0xd,0 + set_fcc 0x7,0 ; Set mask opposite of expected + cfcmps fr52,fr52,fcc0,cc7,0 + test_fcc 0x7,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr52,fr56,fcc0,cc7,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr52,fr60,fcc0,cc7,0 + test_fcc 0xe,0 + + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr0,fcc0,cc7,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr4,fcc0,cc7,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr8,fcc0,cc7,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr12,fcc0,cc7,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr16,fcc0,cc7,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr20,fcc0,cc7,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr24,fcc0,cc7,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr28,fcc0,cc7,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr32,fcc0,cc7,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr36,fcc0,cc7,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr40,fcc0,cc7,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr44,fcc0,cc7,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr48,fcc0,cc7,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr52,fcc0,cc7,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr56,fcc0,cc7,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr56,fr60,fcc0,cc7,0 + test_fcc 0xe,0 + + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr0,fcc0,cc7,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr4,fcc0,cc7,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr8,fcc0,cc7,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr12,fcc0,cc7,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr16,fcc0,cc7,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr20,fcc0,cc7,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr24,fcc0,cc7,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr28,fcc0,cc7,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr32,fcc0,cc7,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr36,fcc0,cc7,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr40,fcc0,cc7,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr44,fcc0,cc7,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr48,fcc0,cc7,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr52,fcc0,cc7,1 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr56,fcc0,cc7,0 + test_fcc 0xe,0 + set_fcc 0xe,0 ; Set mask opposite of expected + cfcmps fr60,fr60,fcc0,cc7,1 + test_fcc 0xe,0 + + pass diff --git a/sim/testsuite/sim/frv/cfdivs.cgs b/sim/testsuite/sim/frv/cfdivs.cgs new file mode 100644 index 0000000..e776f80 --- /dev/null +++ b/sim/testsuite/sim/frv/cfdivs.cgs @@ -0,0 +1,696 @@ +# frv testcase for cfdivs $FRi,$FRj,$FRk,$CCi,$cond +# mach: fr500 fr550 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global cfdivs +cfdivs: + set_spr_immed 0x1b1b,cccr + + cfdivs fr0,fr28,fr1,cc0,1 + test_fr_fr fr1,fr0 + cfdivs fr4,fr28,fr1,cc0,1 + test_fr_fr fr1,fr4 + cfdivs fr8,fr28,fr1,cc0,1 + test_fr_fr fr1,fr8 + cfdivs fr12,fr28,fr1,cc0,1 + test_fr_fr fr1,fr12 + cfdivs fr16,fr28,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr20,fr28,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr24,fr28,fr1,cc0,1 + test_fr_fr fr1,fr24 + cfdivs fr28,fr28,fr1,cc0,1 + test_fr_fr fr1,fr28 + cfdivs fr32,fr28,fr1,cc0,1 + test_fr_fr fr1,fr32 + cfdivs fr36,fr28,fr1,cc0,1 + test_fr_fr fr1,fr36 + cfdivs fr40,fr28,fr1,cc0,1 + test_fr_fr fr1,fr40 + cfdivs fr44,fr28,fr1,cc0,1 + test_fr_fr fr1,fr44 + cfdivs fr48,fr28,fr1,cc0,1 + test_fr_fr fr1,fr48 + cfdivs fr52,fr28,fr1,cc0,1 + test_fr_fr fr1,fr52 + + cfdivs fr16,fr0,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr16,fr4,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr16,fr8,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr16,fr12,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr16,fr24,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr16,fr28,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr16,fr32,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr16,fr36,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr16,fr40,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr16,fr44,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr16,fr48,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr16,fr52,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + + cfdivs fr20,fr0,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr20,fr4,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr20,fr8,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr20,fr12,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr20,fr24,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr20,fr28,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr20,fr32,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr20,fr36,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr20,fr40,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr20,fr44,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr20,fr48,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr20,fr52,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + + cfdivs fr8,fr28,fr1,cc4,1 + test_fr_fr fr1,fr8 + cfdivs fr28,fr8,fr1,cc4,1 + test_fr_fr fr1,fr8 + + cfdivs fr40,fr32,fr1,cc4,1 + test_fr_fr fr1,fr36 +; + cfdivs fr0,fr28,fr1,cc1,0 + test_fr_fr fr1,fr0 + cfdivs fr4,fr28,fr1,cc1,0 + test_fr_fr fr1,fr4 + cfdivs fr8,fr28,fr1,cc1,0 + test_fr_fr fr1,fr8 + cfdivs fr12,fr28,fr1,cc1,0 + test_fr_fr fr1,fr12 + cfdivs fr16,fr28,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr20,fr28,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr24,fr28,fr1,cc1,0 + test_fr_fr fr1,fr24 + cfdivs fr28,fr28,fr1,cc1,0 + test_fr_fr fr1,fr28 + cfdivs fr32,fr28,fr1,cc1,0 + test_fr_fr fr1,fr32 + cfdivs fr36,fr28,fr1,cc1,0 + test_fr_fr fr1,fr36 + cfdivs fr40,fr28,fr1,cc1,0 + test_fr_fr fr1,fr40 + cfdivs fr44,fr28,fr1,cc1,0 + test_fr_fr fr1,fr44 + cfdivs fr48,fr28,fr1,cc1,0 + test_fr_fr fr1,fr48 + cfdivs fr52,fr28,fr1,cc1,0 + test_fr_fr fr1,fr52 + + cfdivs fr16,fr0,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr16,fr4,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr16,fr8,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr16,fr12,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr16,fr24,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr16,fr28,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr16,fr32,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr16,fr36,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr16,fr40,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr16,fr44,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr16,fr48,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr16,fr52,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + + cfdivs fr20,fr0,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr20,fr4,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr20,fr8,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr20,fr12,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr20,fr24,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr20,fr28,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr20,fr32,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr20,fr36,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr20,fr40,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr20,fr44,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr20,fr48,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfdivs fr20,fr52,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + + cfdivs fr8,fr28,fr1,cc5,0 + test_fr_fr fr1,fr8 + cfdivs fr28,fr8,fr1,cc5,0 + test_fr_fr fr1,fr8 + + cfdivs fr40,fr32,fr1,cc5,0 + test_fr_fr fr1,fr36 +; + set_fr_iimmed 0xdead,0xbeef,fr1 + cfdivs fr0,fr28,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr4,fr28,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr8,fr28,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr12,fr28,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr28,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr28,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr24,fr28,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr28,fr28,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr32,fr28,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr36,fr28,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr40,fr28,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr44,fr28,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr48,fr28,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr52,fr28,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + + cfdivs fr16,fr0,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr4,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr8,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr12,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr24,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr28,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr32,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr36,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr40,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr44,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr48,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr52,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfdivs fr20,fr0,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr4,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr8,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr12,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr24,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr28,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr32,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr36,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr40,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr44,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr48,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr52,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfdivs fr8,fr28,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr28,fr8,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + + cfdivs fr40,fr32,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 +; + set_fr_iimmed 0xdead,0xbeef,fr1 + cfdivs fr0,fr28,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr4,fr28,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr8,fr28,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr12,fr28,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr28,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr28,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr24,fr28,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr28,fr28,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr32,fr28,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr36,fr28,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr40,fr28,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr44,fr28,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr48,fr28,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr52,fr28,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfdivs fr16,fr0,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr4,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr8,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr12,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr24,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr28,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr32,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr36,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr40,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr44,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr48,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr52,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfdivs fr20,fr0,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr4,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr8,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr12,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr24,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr28,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr32,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr36,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr40,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr44,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr48,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr52,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfdivs fr8,fr28,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr28,fr8,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfdivs fr40,fr32,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 +; + set_fr_iimmed 0xdead,0xbeef,fr1 + cfdivs fr0,fr28,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr4,fr28,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr8,fr28,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr12,fr28,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr28,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr28,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr24,fr28,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr28,fr28,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr32,fr28,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr36,fr28,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr40,fr28,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr44,fr28,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr48,fr28,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr52,fr28,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfdivs fr16,fr0,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr4,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr8,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr12,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr24,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr28,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr32,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr36,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr40,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr44,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr48,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr52,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfdivs fr20,fr0,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr4,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr8,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr12,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr24,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr28,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr32,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr36,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr40,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr44,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr48,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr52,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfdivs fr8,fr28,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr28,fr8,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfdivs fr40,fr32,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 +; + set_fr_iimmed 0xdead,0xbeef,fr1 + cfdivs fr0,fr28,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr4,fr28,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr8,fr28,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr12,fr28,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr28,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr28,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr24,fr28,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr28,fr28,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr32,fr28,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr36,fr28,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr40,fr28,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr44,fr28,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr48,fr28,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr52,fr28,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfdivs fr16,fr0,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr4,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr8,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr12,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr24,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr28,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr32,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr36,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr40,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr44,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr48,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr16,fr52,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfdivs fr20,fr0,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr4,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr8,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr12,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr24,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr28,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr32,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr36,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr40,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr44,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr48,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr20,fr52,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfdivs fr8,fr28,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfdivs fr28,fr8,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfdivs fr40,fr32,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + + pass diff --git a/sim/testsuite/sim/frv/cfitos.cgs b/sim/testsuite/sim/frv/cfitos.cgs new file mode 100644 index 0000000..b24184e --- /dev/null +++ b/sim/testsuite/sim/frv/cfitos.cgs @@ -0,0 +1,88 @@ +# frv testcase for cfitos $FRj,$FRk,$CCi,$cond +# mach: fr500 fr550 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global cfitos +cfitos: + set_spr_immed 0x1b1b,cccr + + set_fr_iimmed 0,0,fr1 + cfitos fr1,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + + set_fr_iimmed 0x0000,0x0002,fr1 + cfitos fr1,fr1,cc0,1 + test_fr_fr fr1,fr32 + + set_fr_iimmed 0xdead,0xbeef,fr1 + cfitos fr1,fr1,cc4,1 + test_fr_iimmed 0xce054904,fr1 + + set_fr_iimmed 0,0,fr1 + cfitos fr1,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + + set_fr_iimmed 0x0000,0x0002,fr1 + cfitos fr1,fr1,cc1,0 + test_fr_fr fr1,fr32 + + set_fr_iimmed 0xdead,0xbeef,fr1 + cfitos fr1,fr1,cc5,0 + test_fr_iimmed 0xce054904,fr1 + + set_fr_iimmed 0,0,fr1 + cfitos fr1,fr1,cc0,0 + test_fr_iimmed 0,fr1 + + set_fr_iimmed 0x0000,0x0002,fr1 + cfitos fr1,fr1,cc0,0 + test_fr_iimmed 0x00000002,fr1 + + set_fr_iimmed 0xdead,0xbeef,fr1 + cfitos fr1,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + + set_fr_iimmed 0,0,fr1 + cfitos fr1,fr1,cc1,1 + test_fr_iimmed 0,fr1 + + set_fr_iimmed 0x0000,0x0002,fr1 + cfitos fr1,fr1,cc1,1 + test_fr_iimmed 0x00000002,fr1 + + set_fr_iimmed 0xdead,0xbeef,fr1 + cfitos fr1,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + + set_fr_iimmed 0,0,fr1 + cfitos fr1,fr1,cc2,1 + test_fr_iimmed 0,fr1 + + set_fr_iimmed 0x0000,0x0002,fr1 + cfitos fr1,fr1,cc2,0 + test_fr_iimmed 0x00000002,fr1 + + set_fr_iimmed 0xdead,0xbeef,fr1 + cfitos fr1,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + + set_fr_iimmed 0,0,fr1 + cfitos fr1,fr1,cc3,0 + test_fr_iimmed 0,fr1 + + set_fr_iimmed 0x0000,0x0002,fr1 + cfitos fr1,fr1,cc3,1 + test_fr_iimmed 0x00000002,fr1 + + set_fr_iimmed 0xdead,0xbeef,fr1 + cfitos fr1,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + + pass diff --git a/sim/testsuite/sim/frv/cfmadds.cgs b/sim/testsuite/sim/frv/cfmadds.cgs new file mode 100644 index 0000000..a30f7bf --- /dev/null +++ b/sim/testsuite/sim/frv/cfmadds.cgs @@ -0,0 +1,627 @@ +# frv testcase for cfmadds $GRi,$GRj,$GRk,$CCi,$cond +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global cfmadds +cfmadds: + set_spr_immed 0x1b1b,cccr + + set_fr_fr fr16,fr1 + cfmadds fr16,fr4,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr16,fr8,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr16,fr12,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr16,fr16,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr16,fr20,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr16,fr24,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr16,fr28,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr16,fr32,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr16,fr36,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr16,fr40,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr16,fr44,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr16,fr48,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + + cfmadds fr20,fr4,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr20,fr8,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr20,fr12,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr20,fr16,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr20,fr20,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr20,fr24,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr20,fr28,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr20,fr32,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr20,fr36,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr20,fr40,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr20,fr44,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr20,fr48,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + + set_fr_fr fr16,fr1 + cfmadds fr28,fr0,fr1,cc4,1 + test_fr_fr fr1,fr0 + set_fr_fr fr16,fr1 + cfmadds fr28,fr4,fr1,cc4,1 + test_fr_fr fr1,fr4 + set_fr_fr fr16,fr1 + cfmadds fr28,fr8,fr1,cc4,1 + test_fr_fr fr1,fr8 + set_fr_fr fr16,fr1 + cfmadds fr28,fr12,fr1,cc4,1 + test_fr_fr fr1,fr12 + set_fr_fr fr16,fr1 + cfmadds fr28,fr16,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + set_fr_fr fr16,fr1 + cfmadds fr28,fr20,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + set_fr_fr fr16,fr1 + cfmadds fr28,fr24,fr1,cc4,1 + test_fr_fr fr1,fr24 + set_fr_fr fr16,fr1 + cfmadds fr28,fr28,fr1,cc4,1 + test_fr_fr fr1,fr28 + set_fr_fr fr16,fr1 + cfmadds fr28,fr32,fr1,cc4,1 + test_fr_fr fr1,fr32 + set_fr_fr fr16,fr1 + cfmadds fr28,fr36,fr1,cc4,1 + test_fr_fr fr1,fr36 + set_fr_fr fr16,fr1 + cfmadds fr28,fr40,fr1,cc4,1 + test_fr_fr fr1,fr40 + set_fr_fr fr16,fr1 + cfmadds fr28,fr44,fr1,cc4,1 + test_fr_fr fr1,fr44 + set_fr_fr fr16,fr1 + cfmadds fr28,fr48,fr1,cc4,1 + test_fr_fr fr1,fr48 + set_fr_fr fr16,fr1 + cfmadds fr28,fr52,fr1,cc4,1 + test_fr_fr fr1,fr52 + + set_fr_fr fr36,fr1 + cfmadds fr28,fr8,fr1,cc4,1 + test_fr_fr fr1,fr32 + cfmadds fr8,fr28,fr1,cc4,1 + test_fr_fr fr1,fr28 + + set_fr_fr fr36,fr1 + cfmadds fr32,fr36,fr1,cc4,1 + test_fr_fr fr1,fr44 +; + set_fr_fr fr16,fr1 + cfmadds fr16,fr4,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr16,fr8,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr16,fr12,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr16,fr16,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr16,fr20,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr16,fr24,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr16,fr28,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr16,fr32,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr16,fr36,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr16,fr40,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr16,fr44,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr16,fr48,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + + cfmadds fr20,fr4,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr20,fr8,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr20,fr12,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr20,fr16,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr20,fr20,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr20,fr24,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr20,fr28,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr20,fr32,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr20,fr36,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr20,fr40,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr20,fr44,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmadds fr20,fr48,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + + set_fr_fr fr16,fr1 + cfmadds fr28,fr0,fr1,cc5,0 + test_fr_fr fr1,fr0 + set_fr_fr fr16,fr1 + cfmadds fr28,fr4,fr1,cc5,0 + test_fr_fr fr1,fr4 + set_fr_fr fr16,fr1 + cfmadds fr28,fr8,fr1,cc5,0 + test_fr_fr fr1,fr8 + set_fr_fr fr16,fr1 + cfmadds fr28,fr12,fr1,cc5,0 + test_fr_fr fr1,fr12 + set_fr_fr fr16,fr1 + cfmadds fr28,fr16,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + set_fr_fr fr16,fr1 + cfmadds fr28,fr20,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + set_fr_fr fr16,fr1 + cfmadds fr28,fr24,fr1,cc5,0 + test_fr_fr fr1,fr24 + set_fr_fr fr16,fr1 + cfmadds fr28,fr28,fr1,cc5,0 + test_fr_fr fr1,fr28 + set_fr_fr fr16,fr1 + cfmadds fr28,fr32,fr1,cc5,0 + test_fr_fr fr1,fr32 + set_fr_fr fr16,fr1 + cfmadds fr28,fr36,fr1,cc5,0 + test_fr_fr fr1,fr36 + set_fr_fr fr16,fr1 + cfmadds fr28,fr40,fr1,cc5,0 + test_fr_fr fr1,fr40 + set_fr_fr fr16,fr1 + cfmadds fr28,fr44,fr1,cc5,0 + test_fr_fr fr1,fr44 + set_fr_fr fr16,fr1 + cfmadds fr28,fr48,fr1,cc5,0 + test_fr_fr fr1,fr48 + set_fr_fr fr16,fr1 + cfmadds fr28,fr52,fr1,cc5,0 + test_fr_fr fr1,fr52 + + set_fr_fr fr36,fr1 + cfmadds fr28,fr8,fr1,cc5,0 + test_fr_fr fr1,fr32 + cfmadds fr8,fr28,fr1,cc5,0 + test_fr_fr fr1,fr28 + + set_fr_fr fr36,fr1 + cfmadds fr32,fr36,fr1,cc5,0 + test_fr_fr fr1,fr44 +; + set_fr_fr fr48,fr1 + cfmadds fr16,fr4,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmadds fr16,fr8,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmadds fr16,fr12,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmadds fr16,fr16,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmadds fr16,fr20,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmadds fr16,fr24,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmadds fr16,fr28,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmadds fr16,fr32,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmadds fr16,fr36,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmadds fr16,fr40,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmadds fr16,fr44,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmadds fr16,fr48,fr1,cc0,0 + test_fr_fr fr1,fr48 + + cfmadds fr20,fr4,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmadds fr20,fr8,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmadds fr20,fr12,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmadds fr20,fr16,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmadds fr20,fr20,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmadds fr20,fr24,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmadds fr20,fr28,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmadds fr20,fr32,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmadds fr20,fr36,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmadds fr20,fr40,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmadds fr20,fr44,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmadds fr20,fr48,fr1,cc4,0 + test_fr_fr fr1,fr48 + + cfmadds fr28,fr0,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmadds fr28,fr4,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmadds fr28,fr8,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmadds fr28,fr12,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmadds fr28,fr16,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmadds fr28,fr20,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmadds fr28,fr24,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmadds fr28,fr28,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmadds fr28,fr32,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmadds fr28,fr36,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmadds fr28,fr40,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmadds fr28,fr44,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmadds fr28,fr48,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmadds fr28,fr52,fr1,cc4,0 + test_fr_fr fr1,fr48 + + cfmadds fr28,fr8,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmadds fr8,fr28,fr1,cc4,0 + test_fr_fr fr1,fr48 + + cfmadds fr32,fr36,fr1,cc4,0 + test_fr_fr fr1,fr48 +; + set_fr_fr fr48,fr1 + cfmadds fr16,fr4,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmadds fr16,fr8,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmadds fr16,fr12,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmadds fr16,fr16,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmadds fr16,fr20,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmadds fr16,fr24,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmadds fr16,fr28,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmadds fr16,fr32,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmadds fr16,fr36,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmadds fr16,fr40,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmadds fr16,fr44,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmadds fr16,fr48,fr1,cc1,1 + test_fr_fr fr1,fr48 + + cfmadds fr20,fr4,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmadds fr20,fr8,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmadds fr20,fr12,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmadds fr20,fr16,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmadds fr20,fr20,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmadds fr20,fr24,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmadds fr20,fr28,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmadds fr20,fr32,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmadds fr20,fr36,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmadds fr20,fr40,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmadds fr20,fr44,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmadds fr20,fr48,fr1,cc5,1 + test_fr_fr fr1,fr48 + + cfmadds fr28,fr0,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmadds fr28,fr4,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmadds fr28,fr8,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmadds fr28,fr12,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmadds fr28,fr16,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmadds fr28,fr20,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmadds fr28,fr24,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmadds fr28,fr28,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmadds fr28,fr32,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmadds fr28,fr36,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmadds fr28,fr40,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmadds fr28,fr44,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmadds fr28,fr48,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmadds fr28,fr52,fr1,cc5,1 + test_fr_fr fr1,fr48 + + cfmadds fr28,fr8,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmadds fr8,fr28,fr1,cc5,1 + test_fr_fr fr1,fr48 + + cfmadds fr32,fr36,fr1,cc5,1 + test_fr_fr fr1,fr48 +; + set_fr_fr fr48,fr1 + cfmadds fr16,fr4,fr1,cc2,1 + test_fr_fr fr1,fr48 + cfmadds fr16,fr8,fr1,cc2,0 + test_fr_fr fr1,fr48 + cfmadds fr16,fr12,fr1,cc2,1 + test_fr_fr fr1,fr48 + cfmadds fr16,fr16,fr1,cc2,0 + test_fr_fr fr1,fr48 + cfmadds fr16,fr20,fr1,cc2,1 + test_fr_fr fr1,fr48 + cfmadds fr16,fr24,fr1,cc2,0 + test_fr_fr fr1,fr48 + cfmadds fr16,fr28,fr1,cc2,1 + test_fr_fr fr1,fr48 + cfmadds fr16,fr32,fr1,cc2,0 + test_fr_fr fr1,fr48 + cfmadds fr16,fr36,fr1,cc2,1 + test_fr_fr fr1,fr48 + cfmadds fr16,fr40,fr1,cc2,0 + test_fr_fr fr1,fr48 + cfmadds fr16,fr44,fr1,cc2,1 + test_fr_fr fr1,fr48 + cfmadds fr16,fr48,fr1,cc2,0 + test_fr_fr fr1,fr48 + + cfmadds fr20,fr4,fr1,cc2,1 + test_fr_fr fr1,fr48 + cfmadds fr20,fr8,fr1,cc2,0 + test_fr_fr fr1,fr48 + cfmadds fr20,fr12,fr1,cc2,1 + test_fr_fr fr1,fr48 + cfmadds fr20,fr16,fr1,cc2,0 + test_fr_fr fr1,fr48 + cfmadds fr20,fr20,fr1,cc2,1 + test_fr_fr fr1,fr48 + cfmadds fr20,fr24,fr1,cc2,0 + test_fr_fr fr1,fr48 + cfmadds fr20,fr28,fr1,cc2,1 + test_fr_fr fr1,fr48 + cfmadds fr20,fr32,fr1,cc2,0 + test_fr_fr fr1,fr48 + cfmadds fr20,fr36,fr1,cc2,1 + test_fr_fr fr1,fr48 + cfmadds fr20,fr40,fr1,cc6,0 + test_fr_fr fr1,fr48 + cfmadds fr20,fr44,fr1,cc6,1 + test_fr_fr fr1,fr48 + cfmadds fr20,fr48,fr1,cc6,0 + test_fr_fr fr1,fr48 + + cfmadds fr28,fr0,fr1,cc6,1 + test_fr_fr fr1,fr48 + cfmadds fr28,fr4,fr1,cc6,0 + test_fr_fr fr1,fr48 + cfmadds fr28,fr8,fr1,cc6,1 + test_fr_fr fr1,fr48 + cfmadds fr28,fr12,fr1,cc6,0 + test_fr_fr fr1,fr48 + cfmadds fr28,fr16,fr1,cc6,1 + test_fr_fr fr1,fr48 + cfmadds fr28,fr20,fr1,cc6,0 + test_fr_fr fr1,fr48 + cfmadds fr28,fr24,fr1,cc6,1 + test_fr_fr fr1,fr48 + cfmadds fr28,fr28,fr1,cc6,0 + test_fr_fr fr1,fr48 + cfmadds fr28,fr32,fr1,cc6,1 + test_fr_fr fr1,fr48 + cfmadds fr28,fr36,fr1,cc6,0 + test_fr_fr fr1,fr48 + cfmadds fr28,fr40,fr1,cc6,1 + test_fr_fr fr1,fr48 + cfmadds fr28,fr44,fr1,cc6,0 + test_fr_fr fr1,fr48 + cfmadds fr28,fr48,fr1,cc6,1 + test_fr_fr fr1,fr48 + cfmadds fr28,fr52,fr1,cc6,0 + test_fr_fr fr1,fr48 + + cfmadds fr28,fr8,fr1,cc6,1 + test_fr_fr fr1,fr48 + cfmadds fr8,fr28,fr1,cc6,0 + test_fr_fr fr1,fr48 + + cfmadds fr32,fr36,fr1,cc6,1 + test_fr_fr fr1,fr48 +; + set_fr_fr fr48,fr1 + cfmadds fr16,fr4,fr1,cc3,1 + test_fr_fr fr1,fr48 + cfmadds fr16,fr8,fr1,cc3,0 + test_fr_fr fr1,fr48 + cfmadds fr16,fr12,fr1,cc3,1 + test_fr_fr fr1,fr48 + cfmadds fr16,fr16,fr1,cc3,0 + test_fr_fr fr1,fr48 + cfmadds fr16,fr20,fr1,cc3,1 + test_fr_fr fr1,fr48 + cfmadds fr16,fr24,fr1,cc3,0 + test_fr_fr fr1,fr48 + cfmadds fr16,fr28,fr1,cc3,1 + test_fr_fr fr1,fr48 + cfmadds fr16,fr32,fr1,cc3,0 + test_fr_fr fr1,fr48 + cfmadds fr16,fr36,fr1,cc3,1 + test_fr_fr fr1,fr48 + cfmadds fr16,fr40,fr1,cc3,0 + test_fr_fr fr1,fr48 + cfmadds fr16,fr44,fr1,cc3,1 + test_fr_fr fr1,fr48 + cfmadds fr16,fr48,fr1,cc3,0 + test_fr_fr fr1,fr48 + + cfmadds fr20,fr4,fr1,cc3,1 + test_fr_fr fr1,fr48 + cfmadds fr20,fr8,fr1,cc3,0 + test_fr_fr fr1,fr48 + cfmadds fr20,fr12,fr1,cc3,1 + test_fr_fr fr1,fr48 + cfmadds fr20,fr16,fr1,cc3,0 + test_fr_fr fr1,fr48 + cfmadds fr20,fr20,fr1,cc3,1 + test_fr_fr fr1,fr48 + cfmadds fr20,fr24,fr1,cc3,0 + test_fr_fr fr1,fr48 + cfmadds fr20,fr28,fr1,cc3,1 + test_fr_fr fr1,fr48 + cfmadds fr20,fr32,fr1,cc3,0 + test_fr_fr fr1,fr48 + cfmadds fr20,fr36,fr1,cc3,1 + test_fr_fr fr1,fr48 + cfmadds fr20,fr40,fr1,cc7,0 + test_fr_fr fr1,fr48 + cfmadds fr20,fr44,fr1,cc7,1 + test_fr_fr fr1,fr48 + cfmadds fr20,fr48,fr1,cc7,0 + test_fr_fr fr1,fr48 + + cfmadds fr28,fr0,fr1,cc7,1 + test_fr_fr fr1,fr48 + cfmadds fr28,fr4,fr1,cc7,0 + test_fr_fr fr1,fr48 + cfmadds fr28,fr8,fr1,cc7,1 + test_fr_fr fr1,fr48 + cfmadds fr28,fr12,fr1,cc7,0 + test_fr_fr fr1,fr48 + cfmadds fr28,fr16,fr1,cc7,1 + test_fr_fr fr1,fr48 + cfmadds fr28,fr20,fr1,cc7,0 + test_fr_fr fr1,fr48 + cfmadds fr28,fr24,fr1,cc7,1 + test_fr_fr fr1,fr48 + cfmadds fr28,fr28,fr1,cc7,0 + test_fr_fr fr1,fr48 + cfmadds fr28,fr32,fr1,cc7,1 + test_fr_fr fr1,fr48 + cfmadds fr28,fr36,fr1,cc7,0 + test_fr_fr fr1,fr48 + cfmadds fr28,fr40,fr1,cc7,1 + test_fr_fr fr1,fr48 + cfmadds fr28,fr44,fr1,cc7,0 + test_fr_fr fr1,fr48 + cfmadds fr28,fr48,fr1,cc7,1 + test_fr_fr fr1,fr48 + cfmadds fr28,fr52,fr1,cc7,0 + test_fr_fr fr1,fr48 + + cfmadds fr28,fr8,fr1,cc7,1 + test_fr_fr fr1,fr48 + cfmadds fr8,fr28,fr1,cc7,0 + test_fr_fr fr1,fr48 + + cfmadds fr32,fr36,fr1,cc7,1 + test_fr_fr fr1,fr48 +; + pass diff --git a/sim/testsuite/sim/frv/cfmas.cgs b/sim/testsuite/sim/frv/cfmas.cgs new file mode 100644 index 0000000..8c0dc05 --- /dev/null +++ b/sim/testsuite/sim/frv/cfmas.cgs @@ -0,0 +1,775 @@ +# frv testcase for cfmas $FRi,$FRj,$FRk,$CCi,$cond +# mach: fr500 fr550 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + load_float_constants1 + + .global cfmas +cfmas: + set_spr_immed 0x1b1b,cccr + + cfmas fr16,fr4,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr4 + cfmas fr16,fr8,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr8 + cfmas fr16,fr12,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr12 + cfmas fr16,fr16,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + cfmas fr16,fr20,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + cfmas fr16,fr24,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr24 + cfmas fr16,fr28,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr28 + cfmas fr16,fr32,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr32 + cfmas fr16,fr36,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr36 + cfmas fr16,fr40,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr40 + cfmas fr16,fr44,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr44 + cfmas fr16,fr48,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr48 + + cfmas fr20,fr4,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr4 + cfmas fr20,fr8,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr8 + cfmas fr20,fr12,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr12 + cfmas fr20,fr16,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + cfmas fr20,fr20,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + cfmas fr20,fr24,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr24 + cfmas fr20,fr28,fr2,cc4,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr28 + cfmas fr20,fr32,fr2,cc4,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr32 + cfmas fr20,fr36,fr2,cc4,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr36 + cfmas fr20,fr40,fr2,cc4,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr40 + cfmas fr20,fr44,fr2,cc4,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr44 + cfmas fr20,fr48,fr2,cc4,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr48 + + cfmas fr28,fr0,fr2,cc4,1 + test_fr_fr fr2,fr0 + cfmas fr28,fr4,fr2,cc4,1 + test_fr_fr fr2,fr4 + cfmas fr28,fr8,fr2,cc4,1 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + cfmas fr28,fr12,fr2,cc4,1 + test_fr_fr fr2,fr12 + cfmas fr28,fr16,fr2,cc4,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmas fr28,fr20,fr2,cc4,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmas fr28,fr24,fr2,cc4,1 + test_fr_fr fr2,fr24 + cfmas fr28,fr28,fr2,cc4,1 + test_fr_fr fr2,fr28 + cfmas fr28,fr32,fr2,cc4,1 + test_fr_fr fr2,fr32 + test_fr_fr fr3,fr36 + cfmas fr28,fr36,fr2,cc4,1 + test_fr_fr fr2,fr36 + cfmas fr28,fr40,fr2,cc4,1 + test_fr_fr fr2,fr40 + cfmas fr28,fr44,fr2,cc4,1 + test_fr_fr fr2,fr44 + cfmas fr28,fr48,fr2,cc4,1 + test_fr_fr fr2,fr48 + cfmas fr28,fr52,fr2,cc4,1 + test_fr_fr fr2,fr52 + + cfmas fr28,fr8,fr2,cc4,1 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + cfmas fr8,fr28,fr2,cc4,1 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + + cfmas fr32,fr36,fr2,cc4,1 + test_fr_fr fr2,fr40 +; + cfmas fr16,fr4,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr4 + cfmas fr16,fr8,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr8 + cfmas fr16,fr12,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr12 + cfmas fr16,fr16,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + cfmas fr16,fr20,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + cfmas fr16,fr24,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr24 + cfmas fr16,fr28,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr28 + cfmas fr16,fr32,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr32 + cfmas fr16,fr36,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr36 + cfmas fr16,fr40,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr40 + cfmas fr16,fr44,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr44 + cfmas fr16,fr48,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr48 + + cfmas fr20,fr4,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr4 + cfmas fr20,fr8,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr8 + cfmas fr20,fr12,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr12 + cfmas fr20,fr16,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + cfmas fr20,fr20,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + cfmas fr20,fr24,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr24 + cfmas fr20,fr28,fr2,cc5,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr28 + cfmas fr20,fr32,fr2,cc5,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr32 + cfmas fr20,fr36,fr2,cc5,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr36 + cfmas fr20,fr40,fr2,cc5,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr40 + cfmas fr20,fr44,fr2,cc5,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr44 + cfmas fr20,fr48,fr2,cc5,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr48 + + cfmas fr28,fr0,fr2,cc5,0 + test_fr_fr fr2,fr0 + cfmas fr28,fr4,fr2,cc5,0 + test_fr_fr fr2,fr4 + cfmas fr28,fr8,fr2,cc5,0 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + cfmas fr28,fr12,fr2,cc5,0 + test_fr_fr fr2,fr12 + cfmas fr28,fr16,fr2,cc5,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmas fr28,fr20,fr2,cc5,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmas fr28,fr24,fr2,cc5,0 + test_fr_fr fr2,fr24 + cfmas fr28,fr28,fr2,cc5,0 + test_fr_fr fr2,fr28 + cfmas fr28,fr32,fr2,cc5,0 + test_fr_fr fr2,fr32 + test_fr_fr fr3,fr36 + cfmas fr28,fr36,fr2,cc5,0 + test_fr_fr fr2,fr36 + cfmas fr28,fr40,fr2,cc5,0 + test_fr_fr fr2,fr40 + cfmas fr28,fr44,fr2,cc5,0 + test_fr_fr fr2,fr44 + cfmas fr28,fr48,fr2,cc5,0 + test_fr_fr fr2,fr48 + cfmas fr28,fr52,fr2,cc5,0 + test_fr_fr fr2,fr52 + + cfmas fr28,fr8,fr2,cc5,0 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + cfmas fr8,fr28,fr2,cc5,0 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + + cfmas fr32,fr36,fr2,cc5,0 + test_fr_fr fr2,fr40 +; + set_fr_iimmed 0x1111,0x1111,fr2 + set_fr_iimmed 0x2222,0x2222,fr3 + cfmas fr16,fr4,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr8,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr12,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr16,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr20,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr24,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr28,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr32,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr36,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr40,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr44,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr48,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + + cfmas fr20,fr4,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr8,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr12,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr16,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr20,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr24,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + cfmas fr20,fr28,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr32,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr36,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr40,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr44,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr48,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + + cfmas fr28,fr0,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr4,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr8,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr28,fr12,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr16,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr20,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr24,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr28,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr32,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr28,fr36,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr40,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr44,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr48,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr52,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + + cfmas fr28,fr8,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr8,fr28,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + + cfmas fr32,fr36,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 +; + set_fr_iimmed 0x1111,0x1111,fr2 + set_fr_iimmed 0x2222,0x2222,fr3 + cfmas fr16,fr4,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr8,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr12,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr16,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr20,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr24,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr28,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr32,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr36,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr40,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr44,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr48,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + + cfmas fr20,fr4,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr8,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr12,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr16,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr20,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr24,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + cfmas fr20,fr28,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr32,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr36,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr40,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr44,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr48,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + + cfmas fr28,fr0,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr4,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr8,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr28,fr12,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr16,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr20,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr24,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr28,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr32,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr28,fr36,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr40,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr44,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr48,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr52,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + + cfmas fr28,fr8,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr8,fr28,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + + cfmas fr32,fr36,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 +; + set_fr_iimmed 0x1111,0x1111,fr2 + set_fr_iimmed 0x2222,0x2222,fr3 + cfmas fr16,fr4,fr2,cc2,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr8,fr2,cc2,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr12,fr2,cc2,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr16,fr2,cc2,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr20,fr2,cc2,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr24,fr2,cc2,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr28,fr2,cc2,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr32,fr2,cc2,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr36,fr2,cc2,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr40,fr2,cc2,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr44,fr2,cc2,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr48,fr2,cc2,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + + cfmas fr20,fr4,fr2,cc2,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr8,fr2,cc2,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr12,fr2,cc2,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr16,fr2,cc2,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr20,fr2,cc2,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr24,fr2,cc2,0 + test_fr_iimmed 0x11111111,fr2 + cfmas fr20,fr28,fr2,cc6,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr32,fr2,cc6,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr36,fr2,cc6,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr40,fr2,cc6,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr44,fr2,cc6,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr48,fr2,cc6,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + + cfmas fr28,fr0,fr2,cc6,1 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr4,fr2,cc6,0 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr8,fr2,cc6,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr28,fr12,fr2,cc6,0 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr16,fr2,cc6,1 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr20,fr2,cc6,0 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr24,fr2,cc6,1 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr28,fr2,cc6,0 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr32,fr2,cc6,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr28,fr36,fr2,cc6,0 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr40,fr2,cc6,1 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr44,fr2,cc6,0 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr48,fr2,cc6,1 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr52,fr2,cc6,0 + test_fr_iimmed 0x11111111,fr2 + + cfmas fr28,fr8,fr2,cc6,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr8,fr28,fr2,cc6,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + + cfmas fr32,fr36,fr2,cc6,1 + test_fr_iimmed 0x11111111,fr2 +; + set_fr_iimmed 0x1111,0x1111,fr2 + set_fr_iimmed 0x2222,0x2222,fr3 + cfmas fr16,fr4,fr2,cc3,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr8,fr2,cc3,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr12,fr2,cc3,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr16,fr2,cc3,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr20,fr2,cc3,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr24,fr2,cc3,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr28,fr2,cc3,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr32,fr2,cc3,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr36,fr2,cc3,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr40,fr2,cc3,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr44,fr2,cc3,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr16,fr48,fr2,cc3,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + + cfmas fr20,fr4,fr2,cc3,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr8,fr2,cc3,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr12,fr2,cc3,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr16,fr2,cc3,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr20,fr2,cc3,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr24,fr2,cc3,0 + test_fr_iimmed 0x11111111,fr2 + cfmas fr20,fr28,fr2,cc7,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr32,fr2,cc7,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr36,fr2,cc7,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr40,fr2,cc7,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr44,fr2,cc7,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr20,fr48,fr2,cc7,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + + cfmas fr28,fr0,fr2,cc7,1 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr4,fr2,cc7,0 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr8,fr2,cc7,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr28,fr12,fr2,cc7,0 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr16,fr2,cc7,1 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr20,fr2,cc7,0 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr24,fr2,cc7,1 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr28,fr2,cc7,0 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr32,fr2,cc7,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr28,fr36,fr2,cc7,0 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr40,fr2,cc7,1 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr44,fr2,cc7,0 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr48,fr2,cc7,1 + test_fr_iimmed 0x11111111,fr2 + cfmas fr28,fr52,fr2,cc7,0 + test_fr_iimmed 0x11111111,fr2 + + cfmas fr28,fr8,fr2,cc7,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmas fr8,fr28,fr2,cc7,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + + cfmas fr32,fr36,fr2,cc7,1 + test_fr_iimmed 0x11111111,fr2 + + pass diff --git a/sim/testsuite/sim/frv/cfmovs.cgs b/sim/testsuite/sim/frv/cfmovs.cgs new file mode 100644 index 0000000..310bac3 --- /dev/null +++ b/sim/testsuite/sim/frv/cfmovs.cgs @@ -0,0 +1,216 @@ +# frv testcase for cfmovs $FRj,$FRk,$CCi,$cond +# mach: fr500 fr550 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global cfmovs +cfmovs: + set_spr_immed 0x1b1b,cccr + + cfmovs fr0,fr1,cc0,1 + test_fr_fr fr0,fr1 + cfmovs fr4,fr1,cc0,1 + test_fr_fr fr4,fr1 + cfmovs fr8,fr1,cc0,1 + test_fr_fr fr8,fr1 + cfmovs fr12,fr1,cc0,1 + test_fr_fr fr12,fr1 + cfmovs fr16,fr1,cc0,1 + test_fr_fr fr16,fr1 + cfmovs fr20,fr1,cc0,1 + test_fr_fr fr20,fr1 + cfmovs fr24,fr1,cc0,1 + test_fr_fr fr24,fr1 + cfmovs fr28,fr1,cc0,1 + test_fr_fr fr28,fr1 + cfmovs fr32,fr1,cc4,1 + test_fr_fr fr32,fr1 + cfmovs fr36,fr1,cc4,1 + test_fr_fr fr36,fr1 + cfmovs fr40,fr1,cc4,1 + test_fr_fr fr40,fr1 + cfmovs fr44,fr1,cc4,1 + test_fr_fr fr44,fr1 + cfmovs fr48,fr1,cc4,1 + test_fr_fr fr48,fr1 + cfmovs fr52,fr1,cc4,1 + test_fr_fr fr52,fr1 + cfmovs fr56,fr1,cc4,1 + test_fr_iimmed 0x7fc00000,fr1 + cfmovs fr60,fr1,cc4,1 + test_fr_iimmed 0x7f800001,fr1 + + cfmovs fr0,fr1,cc1,0 + test_fr_fr fr0,fr1 + cfmovs fr4,fr1,cc1,0 + test_fr_fr fr4,fr1 + cfmovs fr8,fr1,cc1,0 + test_fr_fr fr8,fr1 + cfmovs fr12,fr1,cc1,0 + test_fr_fr fr12,fr1 + cfmovs fr16,fr1,cc1,0 + test_fr_fr fr16,fr1 + cfmovs fr20,fr1,cc1,0 + test_fr_fr fr20,fr1 + cfmovs fr24,fr1,cc1,0 + test_fr_fr fr24,fr1 + cfmovs fr28,fr1,cc1,0 + test_fr_fr fr28,fr1 + cfmovs fr32,fr1,cc5,0 + test_fr_fr fr32,fr1 + cfmovs fr36,fr1,cc5,0 + test_fr_fr fr36,fr1 + cfmovs fr40,fr1,cc5,0 + test_fr_fr fr40,fr1 + cfmovs fr44,fr1,cc5,0 + test_fr_fr fr44,fr1 + cfmovs fr48,fr1,cc5,0 + test_fr_fr fr48,fr1 + cfmovs fr52,fr1,cc5,0 + test_fr_fr fr52,fr1 + cfmovs fr56,fr1,cc5,0 + test_fr_iimmed 0x7fc00000,fr1 + cfmovs fr60,fr1,cc5,0 + test_fr_iimmed 0x7f800001,fr1 + + set_fr_iimmed 0xdead,0xbeef,fr1 + cfmovs fr0,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr4,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr8,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr12,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr16,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr20,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr24,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr28,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr32,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr36,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr40,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr44,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr48,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr52,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr56,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr60,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + + set_fr_iimmed 0xdead,0xbeef,fr1 + cfmovs fr0,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr4,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr8,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr12,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr16,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr20,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr24,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr28,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr32,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr36,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr40,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr44,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr48,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr52,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr56,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr60,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + + set_fr_iimmed 0xdead,0xbeef,fr1 + cfmovs fr0,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr4,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr8,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr12,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr16,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr20,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr24,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr28,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr32,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr36,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr40,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr44,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr48,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr52,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr56,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr60,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + + set_fr_iimmed 0xdead,0xbeef,fr1 + cfmovs fr0,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr4,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr8,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr12,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr16,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr20,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr24,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr28,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr32,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr36,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr40,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr44,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr48,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr52,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr56,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmovs fr60,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + + pass diff --git a/sim/testsuite/sim/frv/cfmss.cgs b/sim/testsuite/sim/frv/cfmss.cgs new file mode 100644 index 0000000..c31fba3 --- /dev/null +++ b/sim/testsuite/sim/frv/cfmss.cgs @@ -0,0 +1,697 @@ +# frv testcase for cfmss $FRi,$FRj,$FRk,$CCi,$cond +# mach: fr500 fr550 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + load_float_constants1 + + .global cfmss +cfmss: + set_spr_immed 0x1b1b,cccr + + cfmss fr16,fr4,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmss fr16,fr8,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr28 + cfmss fr16,fr12,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmss fr16,fr16,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + cfmss fr16,fr20,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + cfmss fr16,fr24,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmss fr16,fr28,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr8 + cfmss fr16,fr32,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmss fr16,fr36,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmss fr16,fr40,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmss fr16,fr44,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmss fr16,fr48,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + + cfmss fr20,fr4,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmss fr20,fr8,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr28 + cfmss fr20,fr12,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmss fr20,fr16,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + cfmss fr20,fr20,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + cfmss fr20,fr24,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmss fr20,fr28,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr8 + cfmss fr20,fr32,fr2,cc0,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmss fr20,fr36,fr2,cc4,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmss fr20,fr40,fr2,cc4,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmss fr20,fr44,fr2,cc4,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmss fr20,fr48,fr2,cc4,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + + cfmss fr28,fr0,fr2,cc4,1 + test_fr_fr fr2,fr0 + cfmss fr28,fr4,fr2,cc4,1 + test_fr_fr fr2,fr4 + cfmss fr28,fr8,fr2,cc4,1 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr32 + cfmss fr28,fr12,fr2,cc4,1 + test_fr_fr fr2,fr12 + cfmss fr28,fr16,fr2,cc4,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr28 + cfmss fr28,fr20,fr2,cc4,1 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr28 + cfmss fr28,fr24,fr2,cc4,1 + test_fr_fr fr2,fr24 + cfmss fr28,fr28,fr2,cc4,1 + test_fr_fr fr2,fr28 + test_fr_fr fr3,fr20 + test_fr_fr fr3,fr16 + cfmss fr28,fr32,fr2,cc4,1 + test_fr_fr fr2,fr32 + test_fr_fr fr3,fr8 + cfmss fr28,fr36,fr2,cc4,1 + test_fr_fr fr2,fr36 + cfmss fr28,fr40,fr2,cc4,1 + test_fr_fr fr2,fr40 + cfmss fr28,fr44,fr2,cc4,1 + test_fr_fr fr2,fr44 + cfmss fr28,fr48,fr2,cc4,1 + test_fr_fr fr2,fr48 + cfmss fr28,fr52,fr2,cc4,1 + test_fr_fr fr2,fr52 + + cfmss fr28,fr8,fr2,cc4,1 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr32 + cfmss fr8,fr28,fr2,cc4,1 + test_fr_fr fr2,fr8 + + cfmss fr32,fr36,fr2,cc4,1 + test_fr_fr fr2,fr40 + test_fr_fr fr3,fr8 +; + cfmss fr16,fr4,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmss fr16,fr8,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr28 + cfmss fr16,fr12,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmss fr16,fr16,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + cfmss fr16,fr20,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + cfmss fr16,fr24,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmss fr16,fr28,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr8 + cfmss fr16,fr32,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmss fr16,fr36,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmss fr16,fr40,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmss fr16,fr44,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmss fr16,fr48,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + + cfmss fr20,fr4,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmss fr20,fr8,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr28 + cfmss fr20,fr12,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmss fr20,fr16,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + cfmss fr20,fr20,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + cfmss fr20,fr24,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmss fr20,fr28,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr8 + cfmss fr20,fr32,fr2,cc1,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmss fr20,fr36,fr2,cc5,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmss fr20,fr40,fr2,cc5,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmss fr20,fr44,fr2,cc5,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + cfmss fr20,fr48,fr2,cc5,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + + cfmss fr28,fr0,fr2,cc5,0 + test_fr_fr fr2,fr0 + cfmss fr28,fr4,fr2,cc5,0 + test_fr_fr fr2,fr4 + cfmss fr28,fr8,fr2,cc5,0 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr32 + cfmss fr28,fr12,fr2,cc5,0 + test_fr_fr fr2,fr12 + cfmss fr28,fr16,fr2,cc5,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr28 + cfmss fr28,fr20,fr2,cc5,0 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr28 + cfmss fr28,fr24,fr2,cc5,0 + test_fr_fr fr2,fr24 + cfmss fr28,fr28,fr2,cc5,0 + test_fr_fr fr2,fr28 + test_fr_fr fr3,fr20 + test_fr_fr fr3,fr16 + cfmss fr28,fr32,fr2,cc5,0 + test_fr_fr fr2,fr32 + test_fr_fr fr3,fr8 + cfmss fr28,fr36,fr2,cc5,0 + test_fr_fr fr2,fr36 + cfmss fr28,fr40,fr2,cc5,0 + test_fr_fr fr2,fr40 + cfmss fr28,fr44,fr2,cc5,0 + test_fr_fr fr2,fr44 + cfmss fr28,fr48,fr2,cc5,0 + test_fr_fr fr2,fr48 + cfmss fr28,fr52,fr2,cc5,0 + test_fr_fr fr2,fr52 + + cfmss fr28,fr8,fr2,cc5,0 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr32 + cfmss fr8,fr28,fr2,cc5,0 + test_fr_fr fr2,fr8 + + cfmss fr32,fr36,fr2,cc5,0 + test_fr_fr fr2,fr40 + test_fr_fr fr3,fr8 +; + set_fr_iimmed 0x1111,0x1111,fr2 + set_fr_iimmed 0x2222,0x2222,fr3 + cfmss fr16,fr4,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr16,fr8,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr16,fr12,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr16,fr16,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr16,fr20,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr16,fr24,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr16,fr28,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr16,fr32,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr16,fr36,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr16,fr40,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr16,fr44,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr16,fr48,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + + cfmss fr20,fr4,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr20,fr8,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr20,fr12,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr20,fr16,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr20,fr20,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr20,fr24,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr20,fr28,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr20,fr32,fr2,cc0,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr20,fr36,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr20,fr40,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr20,fr44,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr20,fr48,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + + cfmss fr28,fr0,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr4,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr8,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr28,fr12,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr16,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr28,fr20,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr28,fr24,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr28,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr28,fr32,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr28,fr36,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr40,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr44,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr48,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr52,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + + cfmss fr28,fr8,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr8,fr28,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + + cfmss fr32,fr36,fr2,cc4,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 +; + set_fr_iimmed 0x1111,0x1111,fr2 + set_fr_iimmed 0x2222,0x2222,fr3 + cfmss fr16,fr4,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr16,fr8,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr16,fr12,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr16,fr16,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr16,fr20,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr16,fr24,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr16,fr28,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr16,fr32,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr16,fr36,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr16,fr40,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr16,fr44,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr16,fr48,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + + cfmss fr20,fr4,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr20,fr8,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr20,fr12,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr20,fr16,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr20,fr20,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr20,fr24,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr20,fr28,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr20,fr32,fr2,cc1,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr20,fr36,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr20,fr40,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr20,fr44,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr20,fr48,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + + cfmss fr28,fr0,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr4,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr8,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr28,fr12,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr16,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr28,fr20,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr28,fr24,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr28,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr28,fr32,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr28,fr36,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr40,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr44,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr48,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr52,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + + cfmss fr28,fr8,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr8,fr28,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + + cfmss fr32,fr36,fr2,cc5,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 +; + set_fr_iimmed 0x1111,0x1111,fr2 + set_fr_iimmed 0x2222,0x2222,fr3 + cfmss fr16,fr4,fr2,cc2,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr16,fr8,fr2,cc2,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr16,fr12,fr2,cc2,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr16,fr16,fr2,cc2,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr16,fr20,fr2,cc2,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr16,fr24,fr2,cc2,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr16,fr28,fr2,cc2,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr16,fr32,fr2,cc2,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr16,fr36,fr2,cc2,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr16,fr40,fr2,cc2,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr16,fr44,fr2,cc2,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr16,fr48,fr2,cc2,0 + test_fr_iimmed 0x11111111,fr2 + + cfmss fr20,fr4,fr2,cc2,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr20,fr8,fr2,cc2,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr20,fr12,fr2,cc2,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr20,fr16,fr2,cc2,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr20,fr20,fr2,cc2,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr20,fr24,fr2,cc2,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr20,fr28,fr2,cc2,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr20,fr32,fr2,cc2,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr20,fr36,fr2,cc6,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr20,fr40,fr2,cc6,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr20,fr44,fr2,cc6,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr20,fr48,fr2,cc6,0 + test_fr_iimmed 0x11111111,fr2 + + cfmss fr28,fr0,fr2,cc6,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr4,fr2,cc6,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr8,fr2,cc6,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr28,fr12,fr2,cc6,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr16,fr2,cc6,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr28,fr20,fr2,cc6,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr28,fr24,fr2,cc6,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr28,fr2,cc6,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr28,fr32,fr2,cc6,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr28,fr36,fr2,cc6,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr40,fr2,cc6,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr44,fr2,cc6,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr48,fr2,cc6,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr52,fr2,cc6,0 + test_fr_iimmed 0x11111111,fr2 + + cfmss fr28,fr8,fr2,cc6,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr8,fr28,fr2,cc6,0 + test_fr_iimmed 0x11111111,fr2 + + cfmss fr32,fr36,fr2,cc6,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 +; + set_fr_iimmed 0x1111,0x1111,fr2 + set_fr_iimmed 0x2222,0x2222,fr3 + cfmss fr16,fr4,fr2,cc3,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr16,fr8,fr2,cc3,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr16,fr12,fr2,cc3,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr16,fr16,fr2,cc3,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr16,fr20,fr2,cc3,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr16,fr24,fr2,cc3,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr16,fr28,fr2,cc3,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr16,fr32,fr2,cc3,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr16,fr36,fr2,cc3,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr16,fr40,fr2,cc3,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr16,fr44,fr2,cc3,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr16,fr48,fr2,cc3,0 + test_fr_iimmed 0x11111111,fr2 + + cfmss fr20,fr4,fr2,cc3,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr20,fr8,fr2,cc3,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr20,fr12,fr2,cc3,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr20,fr16,fr2,cc3,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr20,fr20,fr2,cc3,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr20,fr24,fr2,cc3,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr20,fr28,fr2,cc3,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr20,fr32,fr2,cc3,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr20,fr36,fr2,cc7,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr20,fr40,fr2,cc7,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr20,fr44,fr2,cc7,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr20,fr48,fr2,cc7,0 + test_fr_iimmed 0x11111111,fr2 + + cfmss fr28,fr0,fr2,cc7,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr4,fr2,cc7,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr8,fr2,cc7,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr28,fr12,fr2,cc7,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr16,fr2,cc7,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr28,fr20,fr2,cc7,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr28,fr24,fr2,cc7,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr28,fr2,cc7,0 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr28,fr32,fr2,cc7,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr28,fr36,fr2,cc7,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr40,fr2,cc7,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr44,fr2,cc7,0 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr48,fr2,cc7,1 + test_fr_iimmed 0x11111111,fr2 + cfmss fr28,fr52,fr2,cc7,0 + test_fr_iimmed 0x11111111,fr2 + + cfmss fr28,fr8,fr2,cc7,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + cfmss fr8,fr28,fr2,cc7,0 + test_fr_iimmed 0x11111111,fr2 + + cfmss fr32,fr36,fr2,cc7,1 + test_fr_iimmed 0x11111111,fr2 + test_fr_iimmed 0x22222222,fr3 + + pass diff --git a/sim/testsuite/sim/frv/cfmsubs.cgs b/sim/testsuite/sim/frv/cfmsubs.cgs new file mode 100644 index 0000000..bc74da4 --- /dev/null +++ b/sim/testsuite/sim/frv/cfmsubs.cgs @@ -0,0 +1,629 @@ +# frv testcase for cfmsubs $GRi,$GRj,$GRk,$CCi,$cond +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global cfmsubs +cfmsubs: + set_spr_immed 0x1b1b,cccr + + set_fr_fr fr16,fr1 + cfmsubs fr16,fr4,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr16,fr8,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr16,fr12,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr16,fr16,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr16,fr20,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr16,fr24,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr16,fr28,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr16,fr32,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr16,fr36,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr16,fr40,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr16,fr44,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr16,fr48,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + + cfmsubs fr20,fr4,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr20,fr8,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr20,fr12,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr20,fr16,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr20,fr20,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr20,fr24,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr20,fr28,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr20,fr32,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr20,fr36,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr20,fr40,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr20,fr44,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr20,fr48,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + + set_fr_fr fr16,fr1 + cfmsubs fr28,fr0,fr1,cc4,1 + test_fr_fr fr1,fr0 + set_fr_fr fr16,fr1 + cfmsubs fr28,fr4,fr1,cc4,1 + test_fr_fr fr1,fr4 + set_fr_fr fr16,fr1 + cfmsubs fr28,fr8,fr1,cc4,1 + test_fr_fr fr1,fr8 + set_fr_fr fr16,fr1 + cfmsubs fr28,fr12,fr1,cc4,1 + test_fr_fr fr1,fr12 + set_fr_fr fr16,fr1 + cfmsubs fr28,fr16,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + set_fr_fr fr16,fr1 + cfmsubs fr28,fr20,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + set_fr_fr fr16,fr1 + cfmsubs fr28,fr24,fr1,cc4,1 + test_fr_fr fr1,fr24 + set_fr_fr fr16,fr1 + cfmsubs fr28,fr28,fr1,cc4,1 + test_fr_fr fr1,fr28 + set_fr_fr fr16,fr1 + cfmsubs fr28,fr32,fr1,cc4,1 + test_fr_fr fr1,fr32 + set_fr_fr fr16,fr1 + cfmsubs fr28,fr36,fr1,cc4,1 + test_fr_fr fr1,fr36 + set_fr_fr fr16,fr1 + cfmsubs fr28,fr40,fr1,cc4,1 + test_fr_fr fr1,fr40 + set_fr_fr fr16,fr1 + cfmsubs fr28,fr44,fr1,cc4,1 + test_fr_fr fr1,fr44 + set_fr_fr fr16,fr1 + cfmsubs fr28,fr48,fr1,cc4,1 + test_fr_fr fr1,fr48 + set_fr_fr fr16,fr1 + cfmsubs fr28,fr52,fr1,cc4,1 + test_fr_fr fr1,fr52 + + set_fr_fr fr32,fr1 + cfmsubs fr8,fr8,fr1,cc4,1 + test_fr_fr fr1,fr8 + set_fr_fr fr36,fr1 + cfmsubs fr36,fr36,fr1,cc4,1 + test_fr_fr fr1,fr40 + + cfmsubs fr32,fr36,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 +; + set_fr_fr fr16,fr1 + cfmsubs fr16,fr4,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr16,fr8,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr16,fr12,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr16,fr16,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr16,fr20,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr16,fr24,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr16,fr28,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr16,fr32,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr16,fr36,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr16,fr40,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr16,fr44,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr16,fr48,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + + cfmsubs fr20,fr4,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr20,fr8,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr20,fr12,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr20,fr16,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr20,fr20,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr20,fr24,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr20,fr28,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr20,fr32,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr20,fr36,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr20,fr40,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr20,fr44,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmsubs fr20,fr48,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + + set_fr_fr fr16,fr1 + cfmsubs fr28,fr0,fr1,cc5,0 + test_fr_fr fr1,fr0 + set_fr_fr fr16,fr1 + cfmsubs fr28,fr4,fr1,cc5,0 + test_fr_fr fr1,fr4 + set_fr_fr fr16,fr1 + cfmsubs fr28,fr8,fr1,cc5,0 + test_fr_fr fr1,fr8 + set_fr_fr fr16,fr1 + cfmsubs fr28,fr12,fr1,cc5,0 + test_fr_fr fr1,fr12 + set_fr_fr fr16,fr1 + cfmsubs fr28,fr16,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + set_fr_fr fr16,fr1 + cfmsubs fr28,fr20,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + set_fr_fr fr16,fr1 + cfmsubs fr28,fr24,fr1,cc5,0 + test_fr_fr fr1,fr24 + set_fr_fr fr16,fr1 + cfmsubs fr28,fr28,fr1,cc5,0 + test_fr_fr fr1,fr28 + set_fr_fr fr16,fr1 + cfmsubs fr28,fr32,fr1,cc5,0 + test_fr_fr fr1,fr32 + set_fr_fr fr16,fr1 + cfmsubs fr28,fr36,fr1,cc5,0 + test_fr_fr fr1,fr36 + set_fr_fr fr16,fr1 + cfmsubs fr28,fr40,fr1,cc5,0 + test_fr_fr fr1,fr40 + set_fr_fr fr16,fr1 + cfmsubs fr28,fr44,fr1,cc5,0 + test_fr_fr fr1,fr44 + set_fr_fr fr16,fr1 + cfmsubs fr28,fr48,fr1,cc5,0 + test_fr_fr fr1,fr48 + set_fr_fr fr16,fr1 + cfmsubs fr28,fr52,fr1,cc5,0 + test_fr_fr fr1,fr52 + + set_fr_fr fr32,fr1 + cfmsubs fr8,fr8,fr1,cc5,0 + test_fr_fr fr1,fr8 + set_fr_fr fr36,fr1 + cfmsubs fr36,fr36,fr1,cc5,0 + test_fr_fr fr1,fr40 + + cfmsubs fr32,fr36,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 +; + set_fr_fr fr48,fr1 + cfmsubs fr16,fr4,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr8,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr12,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr16,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr20,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr24,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr28,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr32,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr36,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr40,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr44,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr48,fr1,cc0,0 + test_fr_fr fr1,fr48 + + cfmsubs fr20,fr4,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr8,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr12,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr16,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr20,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr24,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr28,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr32,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr36,fr1,cc0,0 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr40,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr44,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr48,fr1,cc4,0 + test_fr_fr fr1,fr48 + + cfmsubs fr28,fr0,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr4,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr8,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr12,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr16,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr20,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr24,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr28,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr32,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr36,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr40,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr44,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr48,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr52,fr1,cc4,0 + test_fr_fr fr1,fr48 + + cfmsubs fr8,fr8,fr1,cc4,0 + test_fr_fr fr1,fr48 + cfmsubs fr36,fr36,fr1,cc4,0 + test_fr_fr fr1,fr48 + + cfmsubs fr32,fr36,fr1,cc4,0 + test_fr_fr fr1,fr48 +; + set_fr_fr fr48,fr1 + cfmsubs fr16,fr4,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr8,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr12,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr16,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr20,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr24,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr28,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr32,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr36,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr40,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr44,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr48,fr1,cc1,1 + test_fr_fr fr1,fr48 + + cfmsubs fr20,fr4,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr8,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr12,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr16,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr20,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr24,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr28,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr32,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr36,fr1,cc1,1 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr40,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr44,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr48,fr1,cc5,1 + test_fr_fr fr1,fr48 + + cfmsubs fr28,fr0,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr4,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr8,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr12,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr16,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr20,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr24,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr28,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr32,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr36,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr40,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr44,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr48,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr52,fr1,cc5,1 + test_fr_fr fr1,fr48 + + cfmsubs fr8,fr8,fr1,cc5,1 + test_fr_fr fr1,fr48 + cfmsubs fr36,fr36,fr1,cc5,1 + test_fr_fr fr1,fr48 + + cfmsubs fr32,fr36,fr1,cc5,1 + test_fr_fr fr1,fr48 +; + set_fr_fr fr48,fr1 + cfmsubs fr16,fr4,fr1,cc2,0 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr8,fr1,cc2,1 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr12,fr1,cc2,0 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr16,fr1,cc2,1 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr20,fr1,cc2,0 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr24,fr1,cc2,1 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr28,fr1,cc2,0 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr32,fr1,cc2,1 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr36,fr1,cc2,0 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr40,fr1,cc2,1 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr44,fr1,cc2,0 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr48,fr1,cc2,1 + test_fr_fr fr1,fr48 + + cfmsubs fr20,fr4,fr1,cc2,0 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr8,fr1,cc2,1 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr12,fr1,cc2,0 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr16,fr1,cc2,1 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr20,fr1,cc2,0 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr24,fr1,cc2,1 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr28,fr1,cc2,0 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr32,fr1,cc2,1 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr36,fr1,cc2,0 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr40,fr1,cc6,1 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr44,fr1,cc6,0 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr48,fr1,cc6,1 + test_fr_fr fr1,fr48 + + cfmsubs fr28,fr0,fr1,cc6,0 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr4,fr1,cc6,1 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr8,fr1,cc6,0 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr12,fr1,cc6,1 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr16,fr1,cc6,0 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr20,fr1,cc6,1 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr24,fr1,cc6,0 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr28,fr1,cc6,1 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr32,fr1,cc6,0 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr36,fr1,cc6,1 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr40,fr1,cc6,0 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr44,fr1,cc6,1 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr48,fr1,cc6,0 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr52,fr1,cc6,1 + test_fr_fr fr1,fr48 + + cfmsubs fr8,fr8,fr1,cc6,0 + test_fr_fr fr1,fr48 + cfmsubs fr36,fr36,fr1,cc6,1 + test_fr_fr fr1,fr48 + + cfmsubs fr32,fr36,fr1,cc6,0 + test_fr_fr fr1,fr48 +; + set_fr_fr fr48,fr1 + cfmsubs fr16,fr4,fr1,cc3,0 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr8,fr1,cc3,1 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr12,fr1,cc3,0 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr16,fr1,cc3,1 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr20,fr1,cc3,0 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr24,fr1,cc3,1 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr28,fr1,cc3,0 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr32,fr1,cc3,1 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr36,fr1,cc3,0 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr40,fr1,cc3,1 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr44,fr1,cc3,0 + test_fr_fr fr1,fr48 + cfmsubs fr16,fr48,fr1,cc3,1 + test_fr_fr fr1,fr48 + + cfmsubs fr20,fr4,fr1,cc3,0 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr8,fr1,cc3,1 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr12,fr1,cc3,0 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr16,fr1,cc3,1 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr20,fr1,cc3,0 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr24,fr1,cc3,1 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr28,fr1,cc3,0 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr32,fr1,cc3,1 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr36,fr1,cc3,0 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr40,fr1,cc7,1 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr44,fr1,cc7,0 + test_fr_fr fr1,fr48 + cfmsubs fr20,fr48,fr1,cc7,1 + test_fr_fr fr1,fr48 + + cfmsubs fr28,fr0,fr1,cc7,0 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr4,fr1,cc7,1 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr8,fr1,cc7,0 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr12,fr1,cc7,1 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr16,fr1,cc7,0 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr20,fr1,cc7,1 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr24,fr1,cc7,0 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr28,fr1,cc7,1 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr32,fr1,cc7,0 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr36,fr1,cc7,1 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr40,fr1,cc7,0 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr44,fr1,cc7,1 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr48,fr1,cc7,0 + test_fr_fr fr1,fr48 + cfmsubs fr28,fr52,fr1,cc7,1 + test_fr_fr fr1,fr48 + + cfmsubs fr8,fr8,fr1,cc7,0 + test_fr_fr fr1,fr48 + cfmsubs fr36,fr36,fr1,cc7,1 + test_fr_fr fr1,fr48 + + cfmsubs fr32,fr36,fr1,cc7,0 + test_fr_fr fr1,fr48 +; + pass diff --git a/sim/testsuite/sim/frv/cfmuls.cgs b/sim/testsuite/sim/frv/cfmuls.cgs new file mode 100644 index 0000000..773c95a --- /dev/null +++ b/sim/testsuite/sim/frv/cfmuls.cgs @@ -0,0 +1,696 @@ +# frv testcase for cfmuls $FRi,$FRj,$FRk,$CCi,$cond +# mach: fr500 fr550 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global cfmuls +cfmuls: + set_spr_immed 0x1b1b,cccr + + cfmuls fr16,fr4,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr16,fr8,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr16,fr12,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr16,fr16,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr16,fr20,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr16,fr24,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr16,fr28,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr16,fr32,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr16,fr36,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr16,fr40,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr16,fr44,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr16,fr48,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + + cfmuls fr20,fr4,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr20,fr8,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr20,fr12,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr20,fr16,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr20,fr20,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr20,fr24,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr20,fr28,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr20,fr32,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr20,fr36,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr20,fr40,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr20,fr44,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr20,fr48,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + + cfmuls fr28,fr0,fr1,cc4,1 + test_fr_fr fr1,fr0 + cfmuls fr28,fr4,fr1,cc4,1 + test_fr_fr fr1,fr4 + cfmuls fr28,fr8,fr1,cc4,1 + test_fr_fr fr1,fr8 + cfmuls fr28,fr12,fr1,cc4,1 + test_fr_fr fr1,fr12 + cfmuls fr28,fr16,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr28,fr20,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr28,fr24,fr1,cc4,1 + test_fr_fr fr1,fr24 + cfmuls fr28,fr28,fr1,cc4,1 + test_fr_fr fr1,fr28 + cfmuls fr28,fr32,fr1,cc4,1 + test_fr_fr fr1,fr32 + cfmuls fr28,fr36,fr1,cc4,1 + test_fr_fr fr1,fr36 + cfmuls fr28,fr40,fr1,cc4,1 + test_fr_fr fr1,fr40 + cfmuls fr28,fr44,fr1,cc4,1 + test_fr_fr fr1,fr44 + cfmuls fr28,fr48,fr1,cc4,1 + test_fr_fr fr1,fr48 + cfmuls fr28,fr52,fr1,cc4,1 + test_fr_fr fr1,fr52 + + cfmuls fr28,fr8,fr1,cc4,1 + test_fr_fr fr1,fr8 + cfmuls fr8,fr28,fr1,cc4,1 + test_fr_fr fr1,fr8 + + cfmuls fr32,fr36,fr1,cc4,1 + test_fr_fr fr1,fr40 +; + cfmuls fr16,fr4,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr16,fr8,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr16,fr12,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr16,fr16,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr16,fr20,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr16,fr24,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr16,fr28,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr16,fr32,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr16,fr36,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr16,fr40,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr16,fr44,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr16,fr48,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + + cfmuls fr20,fr4,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr20,fr8,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr20,fr12,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr20,fr16,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr20,fr20,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr20,fr24,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr20,fr28,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr20,fr32,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr20,fr36,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr20,fr40,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr20,fr44,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr20,fr48,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + + cfmuls fr28,fr0,fr1,cc5,0 + test_fr_fr fr1,fr0 + cfmuls fr28,fr4,fr1,cc5,0 + test_fr_fr fr1,fr4 + cfmuls fr28,fr8,fr1,cc5,0 + test_fr_fr fr1,fr8 + cfmuls fr28,fr12,fr1,cc5,0 + test_fr_fr fr1,fr12 + cfmuls fr28,fr16,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr28,fr20,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfmuls fr28,fr24,fr1,cc5,0 + test_fr_fr fr1,fr24 + cfmuls fr28,fr28,fr1,cc5,0 + test_fr_fr fr1,fr28 + cfmuls fr28,fr32,fr1,cc5,0 + test_fr_fr fr1,fr32 + cfmuls fr28,fr36,fr1,cc5,0 + test_fr_fr fr1,fr36 + cfmuls fr28,fr40,fr1,cc5,0 + test_fr_fr fr1,fr40 + cfmuls fr28,fr44,fr1,cc5,0 + test_fr_fr fr1,fr44 + cfmuls fr28,fr48,fr1,cc5,0 + test_fr_fr fr1,fr48 + cfmuls fr28,fr52,fr1,cc5,0 + test_fr_fr fr1,fr52 + + cfmuls fr28,fr8,fr1,cc5,0 + test_fr_fr fr1,fr8 + cfmuls fr8,fr28,fr1,cc5,0 + test_fr_fr fr1,fr8 + + cfmuls fr32,fr36,fr1,cc5,0 + test_fr_fr fr1,fr40 +; + set_fr_iimmed 0xdead,0xbeef,fr1 + cfmuls fr16,fr4,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr8,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr12,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr16,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr20,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr24,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr28,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr32,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr36,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr40,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr44,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr48,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfmuls fr20,fr4,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr8,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr12,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr16,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr20,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr24,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr28,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr32,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr36,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr40,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr44,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr48,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfmuls fr28,fr0,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr4,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr8,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr12,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr16,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr20,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr24,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr28,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr32,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr36,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr40,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr44,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr48,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr52,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + + cfmuls fr28,fr8,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr8,fr28,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + + cfmuls fr32,fr36,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 +; + set_fr_iimmed 0xdead,0xbeef,fr1 + cfmuls fr16,fr4,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr8,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr12,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr16,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr20,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr24,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr28,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr32,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr36,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr40,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr44,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr48,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfmuls fr20,fr4,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr8,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr12,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr16,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr20,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr24,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr28,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr32,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr36,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr40,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr44,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr48,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfmuls fr28,fr0,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr4,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr8,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr12,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr16,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr20,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr24,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr28,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr32,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr36,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr40,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr44,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr48,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr52,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfmuls fr28,fr8,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr8,fr28,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfmuls fr32,fr36,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 +; + set_fr_iimmed 0xdead,0xbeef,fr1 + cfmuls fr16,fr4,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr8,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr12,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr16,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr20,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr24,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr28,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr32,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr36,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr40,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr44,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr48,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfmuls fr20,fr4,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr8,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr12,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr16,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr20,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr24,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr28,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr32,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr36,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr40,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr44,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr48,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfmuls fr28,fr0,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr4,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr8,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr12,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr16,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr20,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr24,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr28,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr32,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr36,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr40,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr44,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr48,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr52,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + + cfmuls fr28,fr8,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr8,fr28,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + + cfmuls fr32,fr36,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 +; + set_fr_iimmed 0xdead,0xbeef,fr1 + cfmuls fr16,fr4,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr8,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr12,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr16,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr20,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr24,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr28,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr32,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr36,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr40,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr44,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr16,fr48,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfmuls fr20,fr4,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr8,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr12,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr16,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr20,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr24,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr28,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr32,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr36,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr40,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr44,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr20,fr48,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfmuls fr28,fr0,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr4,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr8,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr12,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr16,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr20,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr24,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr28,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr32,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr36,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr40,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr44,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr48,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr28,fr52,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + + cfmuls fr28,fr8,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfmuls fr8,fr28,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + + cfmuls fr32,fr36,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + + pass diff --git a/sim/testsuite/sim/frv/cfnegs.cgs b/sim/testsuite/sim/frv/cfnegs.cgs new file mode 100644 index 0000000..c1f2b25 --- /dev/null +++ b/sim/testsuite/sim/frv/cfnegs.cgs @@ -0,0 +1,96 @@ +# frv testcase for cfnegs $FRj,$FRk,$CCi,$cond +# mach: fr500 fr550 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global cfnegs +cfnegs: + set_spr_immed 0x1b1b,cccr + + cfnegs fr0,fr1,cc0,1 + test_fr_fr fr1,fr52 + cfnegs fr8,fr1,cc0,1 + test_fr_fr fr1,fr28 + cfnegs fr12,fr1,cc0,1 + test_fr_fr fr1,fr24 + cfnegs fr24,fr1,cc4,1 + test_fr_fr fr1,fr12 + cfnegs fr28,fr1,cc4,1 + test_fr_fr fr1,fr8 + cfnegs fr52,fr1,cc4,1 + test_fr_fr fr1,fr0 + + cfnegs fr0,fr1,cc1,0 + test_fr_fr fr1,fr52 + cfnegs fr8,fr1,cc1,0 + test_fr_fr fr1,fr28 + cfnegs fr12,fr1,cc1,0 + test_fr_fr fr1,fr24 + cfnegs fr24,fr1,cc5,0 + test_fr_fr fr1,fr12 + cfnegs fr28,fr1,cc5,0 + test_fr_fr fr1,fr8 + cfnegs fr52,fr1,cc5,0 + test_fr_fr fr1,fr0 + + set_fr_iimmed 0xdead,0xbeef,fr1 + cfnegs fr0,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfnegs fr8,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfnegs fr12,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfnegs fr24,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfnegs fr28,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfnegs fr52,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + + set_fr_iimmed 0xdead,0xbeef,fr1 + cfnegs fr0,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfnegs fr8,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfnegs fr12,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfnegs fr24,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfnegs fr28,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfnegs fr52,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + + set_fr_iimmed 0xdead,0xbeef,fr1 + cfnegs fr0,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfnegs fr8,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfnegs fr12,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfnegs fr24,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfnegs fr28,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfnegs fr52,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + + set_fr_iimmed 0xdead,0xbeef,fr1 + cfnegs fr0,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfnegs fr8,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfnegs fr12,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfnegs fr24,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfnegs fr28,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfnegs fr52,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + + pass diff --git a/sim/testsuite/sim/frv/cfsqrts.cgs b/sim/testsuite/sim/frv/cfsqrts.cgs new file mode 100644 index 0000000..ee7a9a5 --- /dev/null +++ b/sim/testsuite/sim/frv/cfsqrts.cgs @@ -0,0 +1,60 @@ +# frv testcase for cfsqrts $FRj,$FRk,$CCi,$cond +# mach: fr500 fr550 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global cfsqrts +cfsqrts: + set_spr_immed 0x1b1b,cccr + + cfsqrts fr44,fr1,cc0,1 ; 9.0 + test_fr_fr fr1,fr36 ; 3.0 + + set_fr_iimmed 0x4049,0x0fdb,fr10 ; 3.141592654 + cfsqrts fr10,fr10,cc4,1 + test_fr_iimmed 0x3fe2dfc5,fr10 ; 1.7724539 + + cfsqrts fr44,fr1,cc1,0 ; 9.0 + test_fr_fr fr1,fr36 ; 3.0 + + set_fr_iimmed 0x4049,0x0fdb,fr10 ; 3.141592654 + cfsqrts fr10,fr10,cc5,0 + test_fr_iimmed 0x3fe2dfc5,fr10 ; 1.7724539 + + set_fr_fr fr0,fr1 + cfsqrts fr44,fr1,cc0,0 ; 9.0 + test_fr_fr fr1,fr0 + + set_fr_iimmed 0x4049,0x0fdb,fr10 ; 3.141592654 + cfsqrts fr10,fr10,cc4,0 + test_fr_iimmed 0x40490fdb,fr10 + + set_fr_fr fr0,fr1 + cfsqrts fr44,fr1,cc1,1 ; 9.0 + test_fr_fr fr1,fr0 + + set_fr_iimmed 0x4049,0x0fdb,fr10 ; 3.141592654 + cfsqrts fr10,fr10,cc5,1 + test_fr_iimmed 0x40490fdb,fr10 + + set_fr_fr fr0,fr1 + cfsqrts fr44,fr1,cc2,0 ; 9.0 + test_fr_fr fr1,fr0 + + set_fr_iimmed 0x4049,0x0fdb,fr10 ; 3.141592654 + cfsqrts fr10,fr10,cc6,1 + test_fr_iimmed 0x40490fdb,fr10 + + set_fr_fr fr0,fr1 + cfsqrts fr44,fr1,cc3,1 ; 9.0 + test_fr_fr fr1,fr0 + + set_fr_iimmed 0x4049,0x0fdb,fr10 ; 3.141592654 + cfsqrts fr10,fr10,cc7,0 + test_fr_iimmed 0x40490fdb,fr10 + + pass diff --git a/sim/testsuite/sim/frv/cfstoi.cgs b/sim/testsuite/sim/frv/cfstoi.cgs new file mode 100644 index 0000000..9ba8d12 --- /dev/null +++ b/sim/testsuite/sim/frv/cfstoi.cgs @@ -0,0 +1,83 @@ +# frv testcase for cfstoi $FRj,$FRk,$CCi,$cond +# mach: fr500 fr550 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global cfstoi +cfstoi: + set_spr_immed 0x1b1b,cccr + + cfstoi fr16,fr1,cc0,1 + test_fr_iimmed 0,fr1 + cfstoi fr20,fr1,cc0,1 + test_fr_iimmed 0,fr1 + + cfstoi fr32,fr1,cc4,1 + test_fr_iimmed 0x00000002,fr1 + + set_fr_iimmed 0xce05,0x4904,fr1 + cfstoi fr1,fr1,cc4,1 + test_fr_iimmed 0xdeadbf00,fr1 + + cfstoi fr16,fr1,cc1,0 + test_fr_iimmed 0,fr1 + cfstoi fr20,fr1,cc1,0 + test_fr_iimmed 0,fr1 + + cfstoi fr32,fr1,cc5,0 + test_fr_iimmed 0x00000002,fr1 + + set_fr_iimmed 0xce05,0x4904,fr1 + cfstoi fr1,fr1,cc5,0 + test_fr_iimmed 0xdeadbf00,fr1 + + set_fr_iimmed 0xdead,0xbeef,fr1 + cfstoi fr16,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfstoi fr20,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + + cfstoi fr32,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + + cfstoi fr1,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + + cfstoi fr16,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfstoi fr20,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfstoi fr32,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfstoi fr1,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfstoi fr16,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfstoi fr20,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + + cfstoi fr32,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfstoi fr1,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + + cfstoi fr16,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfstoi fr20,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + + cfstoi fr32,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfstoi fr1,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + + pass diff --git a/sim/testsuite/sim/frv/cfsubs.cgs b/sim/testsuite/sim/frv/cfsubs.cgs new file mode 100644 index 0000000..3bc7db1 --- /dev/null +++ b/sim/testsuite/sim/frv/cfsubs.cgs @@ -0,0 +1,412 @@ +# frv testcase for cfsubs $FRi,$FRj,$FRk,$CCi,$cond +# mach: fr500 fr550 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global cfsubs +cfsubs: + set_spr_immed 0x1b1b,cccr + + cfsubs fr0,fr16,fr1,cc0,1 + test_fr_fr fr1,fr0 + cfsubs fr4,fr16,fr1,cc0,1 + test_fr_fr fr1,fr4 + cfsubs fr8,fr16,fr1,cc0,1 + test_fr_fr fr1,fr8 + cfsubs fr12,fr16,fr1,cc0,1 + test_fr_fr fr1,fr12 + cfsubs fr16,fr16,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfsubs fr20,fr16,fr1,cc0,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfsubs fr24,fr16,fr1,cc0,1 + test_fr_fr fr1,fr24 + cfsubs fr28,fr16,fr1,cc0,1 + test_fr_fr fr1,fr28 + cfsubs fr32,fr16,fr1,cc0,1 + test_fr_fr fr1,fr32 + cfsubs fr36,fr16,fr1,cc0,1 + test_fr_fr fr1,fr36 + cfsubs fr40,fr16,fr1,cc0,1 + test_fr_fr fr1,fr40 + cfsubs fr44,fr16,fr1,cc0,1 + test_fr_fr fr1,fr44 + cfsubs fr48,fr16,fr1,cc0,1 + test_fr_fr fr1,fr48 + cfsubs fr52,fr16,fr1,cc0,1 + test_fr_fr fr1,fr52 + + cfsubs fr0,fr20,fr1,cc0,1 + test_fr_fr fr1,fr0 + cfsubs fr4,fr20,fr1,cc4,1 + test_fr_fr fr1,fr4 + cfsubs fr8,fr20,fr1,cc4,1 + test_fr_fr fr1,fr8 + cfsubs fr12,fr20,fr1,cc4,1 + test_fr_fr fr1,fr12 + cfsubs fr16,fr20,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfsubs fr20,fr20,fr1,cc4,1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfsubs fr24,fr20,fr1,cc4,1 + test_fr_fr fr1,fr24 + cfsubs fr28,fr20,fr1,cc4,1 + test_fr_fr fr1,fr28 + cfsubs fr32,fr20,fr1,cc4,1 + test_fr_fr fr1,fr32 + cfsubs fr36,fr20,fr1,cc4,1 + test_fr_fr fr1,fr36 + cfsubs fr40,fr20,fr1,cc4,1 + test_fr_fr fr1,fr40 + cfsubs fr44,fr20,fr1,cc4,1 + test_fr_fr fr1,fr44 + cfsubs fr48,fr20,fr1,cc4,1 + test_fr_fr fr1,fr48 + cfsubs fr52,fr20,fr1,cc4,1 + test_fr_fr fr1,fr52 + + cfsubs fr32,fr36,fr1,cc4,1 + test_fr_fr fr1,fr8 + + cfsubs fr44,fr40,fr1,cc4,1 + test_fr_fr fr1,fr36 +; + cfsubs fr0,fr16,fr1,cc1,0 + test_fr_fr fr1,fr0 + cfsubs fr4,fr16,fr1,cc1,0 + test_fr_fr fr1,fr4 + cfsubs fr8,fr16,fr1,cc1,0 + test_fr_fr fr1,fr8 + cfsubs fr12,fr16,fr1,cc1,0 + test_fr_fr fr1,fr12 + cfsubs fr16,fr16,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfsubs fr20,fr16,fr1,cc1,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfsubs fr24,fr16,fr1,cc1,0 + test_fr_fr fr1,fr24 + cfsubs fr28,fr16,fr1,cc1,0 + test_fr_fr fr1,fr28 + cfsubs fr32,fr16,fr1,cc1,0 + test_fr_fr fr1,fr32 + cfsubs fr36,fr16,fr1,cc1,0 + test_fr_fr fr1,fr36 + cfsubs fr40,fr16,fr1,cc1,0 + test_fr_fr fr1,fr40 + cfsubs fr44,fr16,fr1,cc1,0 + test_fr_fr fr1,fr44 + cfsubs fr48,fr16,fr1,cc1,0 + test_fr_fr fr1,fr48 + cfsubs fr52,fr16,fr1,cc1,0 + test_fr_fr fr1,fr52 + + cfsubs fr0,fr20,fr1,cc1,0 + test_fr_fr fr1,fr0 + cfsubs fr4,fr20,fr1,cc5,0 + test_fr_fr fr1,fr4 + cfsubs fr8,fr20,fr1,cc5,0 + test_fr_fr fr1,fr8 + cfsubs fr12,fr20,fr1,cc5,0 + test_fr_fr fr1,fr12 + cfsubs fr16,fr20,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfsubs fr20,fr20,fr1,cc5,0 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + cfsubs fr24,fr20,fr1,cc5,0 + test_fr_fr fr1,fr24 + cfsubs fr28,fr20,fr1,cc5,0 + test_fr_fr fr1,fr28 + cfsubs fr32,fr20,fr1,cc5,0 + test_fr_fr fr1,fr32 + cfsubs fr36,fr20,fr1,cc5,0 + test_fr_fr fr1,fr36 + cfsubs fr40,fr20,fr1,cc5,0 + test_fr_fr fr1,fr40 + cfsubs fr44,fr20,fr1,cc5,0 + test_fr_fr fr1,fr44 + cfsubs fr48,fr20,fr1,cc5,0 + test_fr_fr fr1,fr48 + cfsubs fr52,fr20,fr1,cc5,0 + test_fr_fr fr1,fr52 + + cfsubs fr32,fr36,fr1,cc5,0 + test_fr_fr fr1,fr8 + + cfsubs fr44,fr40,fr1,cc5,0 + test_fr_fr fr1,fr36 + + set_fr_iimmed 0xdead,0xbeef,fr1 + cfsubs fr0,fr16,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr4,fr16,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr8,fr16,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr12,fr16,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr16,fr16,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr20,fr16,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr24,fr16,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr28,fr16,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr32,fr16,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr36,fr16,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr40,fr16,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr44,fr16,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr48,fr16,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr52,fr16,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + + cfsubs fr0,fr20,fr1,cc0,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr4,fr20,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr8,fr20,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr12,fr20,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr16,fr20,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr20,fr20,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr24,fr20,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr28,fr20,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr32,fr20,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr36,fr20,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr40,fr20,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr44,fr20,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr48,fr20,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr52,fr20,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + + cfsubs fr32,fr36,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 + + cfsubs fr44,fr40,fr1,cc4,0 + test_fr_iimmed 0xdeadbeef,fr1 +; + set_fr_iimmed 0xdead,0xbeef,fr1 + cfsubs fr0,fr16,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr4,fr16,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr8,fr16,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr12,fr16,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr16,fr16,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr20,fr16,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr24,fr16,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr28,fr16,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr32,fr16,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr36,fr16,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr40,fr16,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr44,fr16,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr48,fr16,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr52,fr16,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfsubs fr0,fr20,fr1,cc1,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr4,fr20,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr8,fr20,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr12,fr20,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr16,fr20,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr20,fr20,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr24,fr20,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr28,fr20,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr32,fr20,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr36,fr20,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr40,fr20,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr44,fr20,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr48,fr20,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr52,fr20,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfsubs fr32,fr36,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfsubs fr44,fr40,fr1,cc5,1 + test_fr_iimmed 0xdeadbeef,fr1 +; + set_fr_iimmed 0xdead,0xbeef,fr1 + cfsubs fr0,fr16,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr4,fr16,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr8,fr16,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr12,fr16,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr16,fr16,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr20,fr16,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr24,fr16,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr28,fr16,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr32,fr16,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr36,fr16,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr40,fr16,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr44,fr16,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr48,fr16,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr52,fr16,fr1,cc2,1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfsubs fr0,fr20,fr1,cc2,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr4,fr20,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr8,fr20,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr12,fr20,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr16,fr20,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr20,fr20,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr24,fr20,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr28,fr20,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr32,fr20,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr36,fr20,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr40,fr20,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr44,fr20,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr48,fr20,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr52,fr20,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfsubs fr32,fr36,fr1,cc6,0 + test_fr_iimmed 0xdeadbeef,fr1 + + cfsubs fr44,fr40,fr1,cc6,1 + test_fr_iimmed 0xdeadbeef,fr1 +; + set_fr_iimmed 0xdead,0xbeef,fr1 + cfsubs fr0,fr16,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr4,fr16,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr8,fr16,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr12,fr16,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr16,fr16,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr20,fr16,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr24,fr16,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr28,fr16,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr32,fr16,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr36,fr16,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr40,fr16,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr44,fr16,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr48,fr16,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr52,fr16,fr1,cc3,1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfsubs fr0,fr20,fr1,cc3,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr4,fr20,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr8,fr20,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr12,fr20,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr16,fr20,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr20,fr20,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr24,fr20,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr28,fr20,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr32,fr20,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr36,fr20,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr40,fr20,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr44,fr20,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr48,fr20,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + cfsubs fr52,fr20,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + + cfsubs fr32,fr36,fr1,cc7,0 + test_fr_iimmed 0xdeadbeef,fr1 + + cfsubs fr44,fr40,fr1,cc7,1 + test_fr_iimmed 0xdeadbeef,fr1 + + pass + + diff --git a/sim/testsuite/sim/frv/cjmpl.cgs b/sim/testsuite/sim/frv/cjmpl.cgs new file mode 100644 index 0000000..df7be86 --- /dev/null +++ b/sim/testsuite/sim/frv/cjmpl.cgs @@ -0,0 +1,55 @@ +# frv testcase for cjmpl @($GRi,$GRj),$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cjmpl +cjmpl: + set_spr_immed 0x1b1b,cccr + + set_spr_immed 0,lr + set_gr_addr ok1,gr8 + set_gr_immed 0,gr9 + cjmpl @(gr8,gr9),cc0,1 + fail +ok1: + test_spr_immed 0,lr + + set_spr_immed 0,lr + set_gr_addr bad,gr8 + set_gr_immed 0,gr9 + cjmpl @(gr8,gr9),cc0,0 + test_spr_immed 0,lr + + set_spr_immed 0,lr + set_gr_addr ok4,gr8 + set_gr_immed 3,gr9 ; target gets aligned down + cjmpl @(gr8,gr9),cc1,0 + fail +ok4: + test_spr_immed 0,lr + + set_spr_immed 0,lr + set_gr_addr bad,gr8 + set_gr_immed 0,gr9 + cjmpl @(gr8,gr9),cc1,1 + test_spr_immed 0,lr + + set_spr_immed 0,lr + set_gr_addr bad,gr8 + set_gr_immed 0,gr9 + cjmpl @(gr8,gr9),cc2,0 + test_spr_immed 0,lr + + set_spr_immed 0,lr + set_gr_addr bad,gr8 + set_gr_immed 0,gr9 + cjmpl @(gr8,gr9),cc3,1 + test_spr_immed 0,lr + + pass +bad: + fail + diff --git a/sim/testsuite/sim/frv/ckc.cgs b/sim/testsuite/sim/frv/ckc.cgs new file mode 100644 index 0000000..a849dd4 --- /dev/null +++ b/sim/testsuite/sim/frv/ckc.cgs @@ -0,0 +1,90 @@ +# frv testcase for ckc $ICCi,$CCj_int +# mach: all + + .include "testutils.inc" + + start + + .global ckc +ckc: + set_spr_immed 0x1b1b,cccr + set_icc 0x0 0 + ckc icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x1 0 + ckc icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x2 0 + ckc icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x3 0 + ckc icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x4 0 + ckc icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x5 0 + ckc icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x6 0 + ckc icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x7 0 + ckc icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x8 0 + ckc icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x9 0 + ckc icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xa 0 + ckc icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xb 0 + ckc icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xc 0 + ckc icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xd 0 + ckc icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xe 0 + ckc icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xf 0 + ckc icc0,cc7 + test_spr_immed 0xdb1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/ckeq.cgs b/sim/testsuite/sim/frv/ckeq.cgs new file mode 100644 index 0000000..241dc9d --- /dev/null +++ b/sim/testsuite/sim/frv/ckeq.cgs @@ -0,0 +1,90 @@ +# frv testcase for ckeq $ICCi,$CCj_int +# mach: all + + .include "testutils.inc" + + start + + .global ckeq +ckeq: + set_spr_immed 0x1b1b,cccr + set_icc 0x0 0 + ckeq icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x1 0 + ckeq icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x2 0 + ckeq icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x3 0 + ckeq icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x4 0 + ckeq icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x5 0 + ckeq icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x6 0 + ckeq icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x7 0 + ckeq icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x8 0 + ckeq icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x9 0 + ckeq icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xa 0 + ckeq icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xb 0 + ckeq icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xc 0 + ckeq icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xd 0 + ckeq icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xe 0 + ckeq icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xf 0 + ckeq icc0,cc7 + test_spr_immed 0xdb1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/ckge.cgs b/sim/testsuite/sim/frv/ckge.cgs new file mode 100644 index 0000000..58eefd3 --- /dev/null +++ b/sim/testsuite/sim/frv/ckge.cgs @@ -0,0 +1,90 @@ +# frv testcase for ckge $ICCi,$CCj_int +# mach: all + + .include "testutils.inc" + + start + + .global ckge +ckge: + set_spr_immed 0x1b1b,cccr + set_icc 0x0 0 + ckge icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x1 0 + ckge icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x2 0 + ckge icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x3 0 + ckge icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x4 0 + ckge icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x5 0 + ckge icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x6 0 + ckge icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x7 0 + ckge icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x8 0 + ckge icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x9 0 + ckge icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xa 0 + ckge icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xb 0 + ckge icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xc 0 + ckge icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xd 0 + ckge icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xe 0 + ckge icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xf 0 + ckge icc0,cc7 + test_spr_immed 0xdb1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/ckgt.cgs b/sim/testsuite/sim/frv/ckgt.cgs new file mode 100644 index 0000000..7d4b6a8 --- /dev/null +++ b/sim/testsuite/sim/frv/ckgt.cgs @@ -0,0 +1,90 @@ +# frv testcase for ckgt $ICCi,$CCj_int +# mach: all + + .include "testutils.inc" + + start + + .global ckgt +ckgt: + set_spr_immed 0x1b1b,cccr + set_icc 0x0 0 + ckgt icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x1 0 + ckgt icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x2 0 + ckgt icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x3 0 + ckgt icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x4 0 + ckgt icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x5 0 + ckgt icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x6 0 + ckgt icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x7 0 + ckgt icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x8 0 + ckgt icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x9 0 + ckgt icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xa 0 + ckgt icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xb 0 + ckgt icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xc 0 + ckgt icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xd 0 + ckgt icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xe 0 + ckgt icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xf 0 + ckgt icc0,cc7 + test_spr_immed 0x9b1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/ckhi.cgs b/sim/testsuite/sim/frv/ckhi.cgs new file mode 100644 index 0000000..5c55937 --- /dev/null +++ b/sim/testsuite/sim/frv/ckhi.cgs @@ -0,0 +1,90 @@ +# frv testcase for ckhi $ICCi,$CCj_int +# mach: all + + .include "testutils.inc" + + start + + .global ckhi +ckhi: + set_spr_immed 0x1b1b,cccr + set_icc 0x0 0 + ckhi icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x1 0 + ckhi icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x2 0 + ckhi icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x3 0 + ckhi icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x4 0 + ckhi icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x5 0 + ckhi icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x6 0 + ckhi icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x7 0 + ckhi icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x8 0 + ckhi icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x9 0 + ckhi icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xa 0 + ckhi icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xb 0 + ckhi icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xc 0 + ckhi icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xd 0 + ckhi icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xe 0 + ckhi icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xf 0 + ckhi icc0,cc7 + test_spr_immed 0x9b1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/ckle.cgs b/sim/testsuite/sim/frv/ckle.cgs new file mode 100644 index 0000000..8a6f445 --- /dev/null +++ b/sim/testsuite/sim/frv/ckle.cgs @@ -0,0 +1,90 @@ +# frv testcase for ckle $ICCi,$CCj_int +# mach: all + + .include "testutils.inc" + + start + + .global ckle +ckle: + set_spr_immed 0x1b1b,cccr + set_icc 0x0 0 + ckle icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x1 0 + ckle icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x2 0 + ckle icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x3 0 + ckle icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x4 0 + ckle icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x5 0 + ckle icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x6 0 + ckle icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x7 0 + ckle icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x8 0 + ckle icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x9 0 + ckle icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xa 0 + ckle icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xb 0 + ckle icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xc 0 + ckle icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xd 0 + ckle icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xe 0 + ckle icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xf 0 + ckle icc0,cc7 + test_spr_immed 0xdb1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/ckls.cgs b/sim/testsuite/sim/frv/ckls.cgs new file mode 100644 index 0000000..ca5822f --- /dev/null +++ b/sim/testsuite/sim/frv/ckls.cgs @@ -0,0 +1,90 @@ +# frv testcase for ckls $ICCi,$CCj_int +# mach: all + + .include "testutils.inc" + + start + + .global ckls +ckls: + set_spr_immed 0x1b1b,cccr + set_icc 0x0 0 + ckls icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x1 0 + ckls icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x2 0 + ckls icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x3 0 + ckls icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x4 0 + ckls icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x5 0 + ckls icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x6 0 + ckls icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x7 0 + ckls icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x8 0 + ckls icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x9 0 + ckls icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xa 0 + ckls icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xb 0 + ckls icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xc 0 + ckls icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xd 0 + ckls icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xe 0 + ckls icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xf 0 + ckls icc0,cc7 + test_spr_immed 0xdb1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/cklt.cgs b/sim/testsuite/sim/frv/cklt.cgs new file mode 100644 index 0000000..f5848af --- /dev/null +++ b/sim/testsuite/sim/frv/cklt.cgs @@ -0,0 +1,90 @@ +# frv testcase for cklt $ICCi,$CCj_int +# mach: all + + .include "testutils.inc" + + start + + .global cklt +cklt: + set_spr_immed 0x1b1b,cccr + set_icc 0x0 0 + cklt icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x1 0 + cklt icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x2 0 + cklt icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x3 0 + cklt icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x4 0 + cklt icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x5 0 + cklt icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x6 0 + cklt icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x7 0 + cklt icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x8 0 + cklt icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x9 0 + cklt icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xa 0 + cklt icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xb 0 + cklt icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xc 0 + cklt icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xd 0 + cklt icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xe 0 + cklt icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xf 0 + cklt icc0,cc7 + test_spr_immed 0x9b1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/ckn.cgs b/sim/testsuite/sim/frv/ckn.cgs new file mode 100644 index 0000000..073a2f1 --- /dev/null +++ b/sim/testsuite/sim/frv/ckn.cgs @@ -0,0 +1,90 @@ +# frv testcase for ckn $ICCi,$CCj_int +# mach: all + + .include "testutils.inc" + + start + + .global ckn +ckn: + set_spr_immed 0x1b1b,cccr + set_icc 0x0 0 + ckn icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x1 0 + ckn icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x2 0 + ckn icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x3 0 + ckn icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x4 0 + ckn icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x5 0 + ckn icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x6 0 + ckn icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x7 0 + ckn icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x8 0 + ckn icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x9 0 + ckn icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xa 0 + ckn icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xb 0 + ckn icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xc 0 + ckn icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xd 0 + ckn icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xe 0 + ckn icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xf 0 + ckn icc0,cc7 + test_spr_immed 0xdb1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/cknc.cgs b/sim/testsuite/sim/frv/cknc.cgs new file mode 100644 index 0000000..a1359a9 --- /dev/null +++ b/sim/testsuite/sim/frv/cknc.cgs @@ -0,0 +1,90 @@ +# frv testcase for cknc $ICCi,$CCj_int +# mach: all + + .include "testutils.inc" + + start + + .global cknc +cknc: + set_spr_immed 0x1b1b,cccr + set_icc 0x0 0 + cknc icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x1 0 + cknc icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x2 0 + cknc icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x3 0 + cknc icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x4 0 + cknc icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x5 0 + cknc icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x6 0 + cknc icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x7 0 + cknc icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x8 0 + cknc icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x9 0 + cknc icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xa 0 + cknc icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xb 0 + cknc icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xc 0 + cknc icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xd 0 + cknc icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xe 0 + cknc icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xf 0 + cknc icc0,cc7 + test_spr_immed 0x9b1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/ckne.cgs b/sim/testsuite/sim/frv/ckne.cgs new file mode 100644 index 0000000..b9c2935 --- /dev/null +++ b/sim/testsuite/sim/frv/ckne.cgs @@ -0,0 +1,90 @@ +# frv testcase for ckne $ICCi,$CCj_int +# mach: all + + .include "testutils.inc" + + start + + .global ckne +ckne: + set_spr_immed 0x1b1b,cccr + set_icc 0x0 0 + ckne icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x1 0 + ckne icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x2 0 + ckne icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x3 0 + ckne icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x4 0 + ckne icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x5 0 + ckne icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x6 0 + ckne icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x7 0 + ckne icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x8 0 + ckne icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x9 0 + ckne icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xa 0 + ckne icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xb 0 + ckne icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xc 0 + ckne icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xd 0 + ckne icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xe 0 + ckne icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xf 0 + ckne icc0,cc7 + test_spr_immed 0x9b1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/ckno.cgs b/sim/testsuite/sim/frv/ckno.cgs new file mode 100644 index 0000000..e387b46 --- /dev/null +++ b/sim/testsuite/sim/frv/ckno.cgs @@ -0,0 +1,90 @@ +# frv testcase for ckno $CCj_int +# mach: all + + .include "testutils.inc" + + start + + .global ckno +ckno: + set_spr_immed 0x1b1b,cccr + set_icc 0x0 0 + ckno cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x1 0 + ckno cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x2 0 + ckno cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x3 0 + ckno cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x4 0 + ckno cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x5 0 + ckno cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x6 0 + ckno cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x7 0 + ckno cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x8 0 + ckno cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x9 0 + ckno cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xa 0 + ckno cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xb 0 + ckno cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xc 0 + ckno cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xd 0 + ckno cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xe 0 + ckno cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xf 0 + ckno cc7 + test_spr_immed 0x9b1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/cknv.cgs b/sim/testsuite/sim/frv/cknv.cgs new file mode 100644 index 0000000..039eb7d --- /dev/null +++ b/sim/testsuite/sim/frv/cknv.cgs @@ -0,0 +1,90 @@ +# frv testcase for cknv $ICCi,$CCj_int +# mach: all + + .include "testutils.inc" + + start + + .global cknv +cknv: + set_spr_immed 0x1b1b,cccr + set_icc 0x0 0 + cknv icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x1 0 + cknv icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x2 0 + cknv icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x3 0 + cknv icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x4 0 + cknv icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x5 0 + cknv icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x6 0 + cknv icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x7 0 + cknv icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x8 0 + cknv icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x9 0 + cknv icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xa 0 + cknv icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xb 0 + cknv icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xc 0 + cknv icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xd 0 + cknv icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xe 0 + cknv icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xf 0 + cknv icc0,cc7 + test_spr_immed 0x9b1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/ckp.cgs b/sim/testsuite/sim/frv/ckp.cgs new file mode 100644 index 0000000..49129ec --- /dev/null +++ b/sim/testsuite/sim/frv/ckp.cgs @@ -0,0 +1,90 @@ +# frv testcase for ckp $ICCi,$CCj_int +# mach: all + + .include "testutils.inc" + + start + + .global ckp +ckp: + set_spr_immed 0x1b1b,cccr + set_icc 0x0 0 + ckp icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x1 0 + ckp icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x2 0 + ckp icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x3 0 + ckp icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x4 0 + ckp icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x5 0 + ckp icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x6 0 + ckp icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x7 0 + ckp icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x8 0 + ckp icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x9 0 + ckp icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xa 0 + ckp icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xb 0 + ckp icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xc 0 + ckp icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xd 0 + ckp icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xe 0 + ckp icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xf 0 + ckp icc0,cc7 + test_spr_immed 0x9b1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/ckra.cgs b/sim/testsuite/sim/frv/ckra.cgs new file mode 100644 index 0000000..b542b10 --- /dev/null +++ b/sim/testsuite/sim/frv/ckra.cgs @@ -0,0 +1,90 @@ +# frv testcase for ckra $CCj_int +# mach: all + + .include "testutils.inc" + + start + + .global ckra +ckra: + set_spr_immed 0x1b1b,cccr + set_icc 0x0 0 + ckra cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x1 0 + ckra cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x2 0 + ckra cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x3 0 + ckra cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x4 0 + ckra cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x5 0 + ckra cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x6 0 + ckra cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x7 0 + ckra cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x8 0 + ckra cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x9 0 + ckra cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xa 0 + ckra cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xb 0 + ckra cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xc 0 + ckra cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xd 0 + ckra cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xe 0 + ckra cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xf 0 + ckra cc7 + test_spr_immed 0xdb1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/ckv.cgs b/sim/testsuite/sim/frv/ckv.cgs new file mode 100644 index 0000000..338c286 --- /dev/null +++ b/sim/testsuite/sim/frv/ckv.cgs @@ -0,0 +1,90 @@ +# frv testcase for ckv $ICCi,$CCj_int +# mach: all + + .include "testutils.inc" + + start + + .global ckv +ckv: + set_spr_immed 0x1b1b,cccr + set_icc 0x0 0 + ckv icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x1 0 + ckv icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x2 0 + ckv icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x3 0 + ckv icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x4 0 + ckv icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x5 0 + ckv icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x6 0 + ckv icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x7 0 + ckv icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x8 0 + ckv icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0x9 0 + ckv icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xa 0 + ckv icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xb 0 + ckv icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xc 0 + ckv icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xd 0 + ckv icc0,cc7 + test_spr_immed 0x9b1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xe 0 + ckv icc0,cc7 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x1b1b,cccr + set_icc 0xf 0 + ckv icc0,cc7 + test_spr_immed 0xdb1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/cld.cgs b/sim/testsuite/sim/frv/cld.cgs new file mode 100644 index 0000000..62e1324 --- /dev/null +++ b/sim/testsuite/sim/frv/cld.cgs @@ -0,0 +1,126 @@ +# frv testcase for cld @($GRi,$GRj),$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cld +cld: + set_spr_immed 0x1b1b,cccr + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + cld @(sp,gr7),gr8,cc0,1 + test_gr_limmed 0xdead,0xbeef,gr8 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + cld @(sp,gr7),gr8,cc0,1 + test_gr_limmed 0xdead,0xbeef,gr8 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed 8,sp + set_gr_immed -4,gr7 + cld @(sp,gr7),gr8,cc4,1 + test_gr_limmed 0xdead,0xbeef,gr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + cld @(sp,gr7),gr8,cc0,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + cld @(sp,gr7),gr8,cc0,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed 8,sp + set_gr_immed -4,gr7 + cld @(sp,gr7),gr8,cc4,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + cld @(sp,gr7),gr8,cc1,0 + test_gr_limmed 0xdead,0xbeef,gr8 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + cld @(sp,gr7),gr8,cc1,0 + test_gr_limmed 0xdead,0xbeef,gr8 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed 8,sp + set_gr_immed -4,gr7 + cld @(sp,gr7),gr8,cc5,0 + test_gr_limmed 0xdead,0xbeef,gr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + cld @(sp,gr7),gr8,cc1,1 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + cld @(sp,gr7),gr8,cc1,1 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed 8,sp + set_gr_immed -4,gr7 + cld @(sp,gr7),gr8,cc5,1 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + cld @(sp,gr7),gr8,cc2,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + cld @(sp,gr7),gr8,cc2,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed 8,sp + set_gr_immed -4,gr7 + cld @(sp,gr7),gr8,cc6,1 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + cld @(sp,gr7),gr8,cc3,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + cld @(sp,gr7),gr8,cc3,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed 8,sp + set_gr_immed -4,gr7 + cld @(sp,gr7),gr8,cc7,1 + test_gr_limmed 0xbeef,0xdead,gr8 + + pass diff --git a/sim/testsuite/sim/frv/cldbf.cgs b/sim/testsuite/sim/frv/cldbf.cgs new file mode 100644 index 0000000..46d65ea --- /dev/null +++ b/sim/testsuite/sim/frv/cldbf.cgs @@ -0,0 +1,114 @@ +# frv testcase for cldbf @($GRi,$GRj),$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cldbf +cldbf: + set_spr_immed 0x1b1b,cccr + + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldbf @(sp,gr7),fr8,cc0,1 + test_fr_limmed 0x0000,0x00de,fr8 + + set_gr_immed 1,gr7 + cldbf @(sp,gr7),fr8,cc0,1 + test_fr_limmed 0x0000,0x00ad,fr8 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldbf @(sp,gr7),fr8,cc4,1 + test_fr_limmed 0x0000,0x0000,fr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldbf @(sp,gr7),fr8,cc0,0 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_gr_immed 1,gr7 + cldbf @(sp,gr7),fr8,cc0,0 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldbf @(sp,gr7),fr8,cc4,0 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldbf @(sp,gr7),fr8,cc1,0 + test_fr_limmed 0x0000,0x00de,fr8 + + set_gr_immed 1,gr7 + cldbf @(sp,gr7),fr8,cc1,0 + test_fr_limmed 0x0000,0x00ad,fr8 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldbf @(sp,gr7),fr8,cc5,0 + test_fr_limmed 0x0000,0x0000,fr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldbf @(sp,gr7),fr8,cc1,1 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_gr_immed 1,gr7 + cldbf @(sp,gr7),fr8,cc1,1 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldbf @(sp,gr7),fr8,cc5,1 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldbf @(sp,gr7),fr8,cc2,0 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_gr_immed 1,gr7 + cldbf @(sp,gr7),fr8,cc2,1 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldbf @(sp,gr7),fr8,cc6,0 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldbf @(sp,gr7),fr8,cc3,1 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_gr_immed 1,gr7 + cldbf @(sp,gr7),fr8,cc3,0 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldbf @(sp,gr7),fr8,cc7,1 + test_fr_limmed 0xbeef,0xdead,fr8 + + pass diff --git a/sim/testsuite/sim/frv/cldbfu.cgs b/sim/testsuite/sim/frv/cldbfu.cgs new file mode 100644 index 0000000..bde4ff1 --- /dev/null +++ b/sim/testsuite/sim/frv/cldbfu.cgs @@ -0,0 +1,154 @@ +# frv testcase for cldbfu @($GRi,$GRj),$FRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cldbfu +cldbfu: + set_spr_immed 0x1b1b,cccr + set_gr_gr sp,gr21 + + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldbfu @(sp,gr7),fr8,cc0,1 + test_fr_limmed 0x0000,0x00de,fr8 + test_gr_gr sp,gr20 + + inc_gr_immed 1,gr20 + set_gr_immed 1,gr7 + cldbfu @(sp,gr7),fr8,cc0,1 + test_fr_limmed 0x0000,0x00ad,fr8 + test_gr_gr sp,gr20 + + inc_gr_immed 2,gr20 + inc_gr_immed -1,sp + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldbfu @(sp,gr7),fr8,cc4,1 + test_fr_limmed 0x0000,0x0000,fr8 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldbfu @(sp,gr7),fr8,cc0,0 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + set_gr_immed 1,gr7 + cldbfu @(sp,gr7),fr8,cc0,0 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,gr20 + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldbfu @(sp,gr7),fr8,cc4,0 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldbfu @(sp,gr7),fr8,cc1,0 + test_fr_limmed 0x0000,0x00de,fr8 + test_gr_gr sp,gr20 + + inc_gr_immed 1,gr20 + set_gr_immed 1,gr7 + cldbfu @(sp,gr7),fr8,cc1,0 + test_fr_limmed 0x0000,0x00ad,fr8 + test_gr_gr sp,gr20 + + inc_gr_immed 2,gr20 + inc_gr_immed -1,sp + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldbfu @(sp,gr7),fr8,cc5,0 + test_fr_limmed 0x0000,0x0000,fr8 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldbfu @(sp,gr7),fr8,cc1,1 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + set_gr_immed 1,gr7 + cldbfu @(sp,gr7),fr8,cc1,1 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,gr20 + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldbfu @(sp,gr7),fr8,cc5,1 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldbfu @(sp,gr7),fr8,cc2,0 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + set_gr_immed 1,gr7 + cldbfu @(sp,gr7),fr8,cc2,1 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,gr20 + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldbfu @(sp,gr7),fr8,cc6,0 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldbfu @(sp,gr7),fr8,cc3,1 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + set_gr_immed 1,gr7 + cldbfu @(sp,gr7),fr8,cc3,0 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,gr20 + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldbfu @(sp,gr7),fr8,cc7,1 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + pass diff --git a/sim/testsuite/sim/frv/cldd.cgs b/sim/testsuite/sim/frv/cldd.cgs new file mode 100644 index 0000000..709eba1 --- /dev/null +++ b/sim/testsuite/sim/frv/cldd.cgs @@ -0,0 +1,168 @@ +# frv testcase for cldd @($GRi,$GRj),$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cldd +cldd: + set_spr_immed 0x1b1b,cccr + + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + + set_gr_immed 0,gr7 + cldd @(sp,gr7),gr8,cc0,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + cldd @(sp,gr7),gr8,cc0,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + cldd @(sp,gr7),gr8,cc4,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + + set_gr_immed 0,gr7 + cldd @(sp,gr7),gr8,cc0,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + cldd @(sp,gr7),gr8,cc0,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + cldd @(sp,gr7),gr8,cc4,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + + set_gr_immed 0,gr7 + cldd @(sp,gr7),gr8,cc1,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + cldd @(sp,gr7),gr8,cc1,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + cldd @(sp,gr7),gr8,cc5,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + + set_gr_immed 0,gr7 + cldd @(sp,gr7),gr8,cc1,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + cldd @(sp,gr7),gr8,cc1,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + cldd @(sp,gr7),gr8,cc5,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + + set_gr_immed 0,gr7 + cldd @(sp,gr7),gr8,cc2,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + cldd @(sp,gr7),gr8,cc2,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + cldd @(sp,gr7),gr8,cc6,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + + set_gr_immed 0,gr7 + cldd @(sp,gr7),gr8,cc3,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + cldd @(sp,gr7),gr8,cc3,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + cldd @(sp,gr7),gr8,cc7,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + + pass diff --git a/sim/testsuite/sim/frv/clddf.cgs b/sim/testsuite/sim/frv/clddf.cgs new file mode 100644 index 0000000..c5416ed --- /dev/null +++ b/sim/testsuite/sim/frv/clddf.cgs @@ -0,0 +1,174 @@ +# frv testcase for clddf @($GRi,$GRj),$FRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global clddf +clddf: + set_spr_immed 0x1b1b,cccr + + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + + set_gr_immed 0,gr7 + clddf @(sp,gr7),fr8,cc0,1 + test_fr_limmed 0xbeef,0xdead,fr8 + test_fr_limmed 0xdead,0xbeef,fr9 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + clddf @(sp,gr7),fr8,cc0,1 + test_fr_limmed 0xbeef,0xdead,fr8 + test_fr_limmed 0xdead,0xbeef,fr9 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + clddf @(sp,gr7),fr8,cc4,1 + test_fr_limmed 0xbeef,0xdead,fr8 + test_fr_limmed 0xdead,0xbeef,fr9 + + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + + set_gr_immed 0,gr7 + clddf @(sp,gr7),fr8,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + clddf @(sp,gr7),fr8,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + clddf @(sp,gr7),fr8,cc4,0 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + + set_gr_immed 0,gr7 + clddf @(sp,gr7),fr8,cc1,0 + test_fr_limmed 0xbeef,0xdead,fr8 + test_fr_limmed 0xdead,0xbeef,fr9 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + clddf @(sp,gr7),fr8,cc1,0 + test_fr_limmed 0xbeef,0xdead,fr8 + test_fr_limmed 0xdead,0xbeef,fr9 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + clddf @(sp,gr7),fr8,cc5,0 + test_fr_limmed 0xbeef,0xdead,fr8 + test_fr_limmed 0xdead,0xbeef,fr9 + + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + + set_gr_immed 0,gr7 + clddf @(sp,gr7),fr8,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + clddf @(sp,gr7),fr8,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + clddf @(sp,gr7),fr8,cc5,1 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + + set_gr_immed 0,gr7 + clddf @(sp,gr7),fr8,cc2,0 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + clddf @(sp,gr7),fr8,cc2,1 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + clddf @(sp,gr7),fr8,cc6,0 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + + set_gr_immed 0,gr7 + clddf @(sp,gr7),fr8,cc3,1 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + clddf @(sp,gr7),fr8,cc3,0 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + clddf @(sp,gr7),fr8,cc7,1 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + + pass diff --git a/sim/testsuite/sim/frv/clddfu.cgs b/sim/testsuite/sim/frv/clddfu.cgs new file mode 100644 index 0000000..ab981aa --- /dev/null +++ b/sim/testsuite/sim/frv/clddfu.cgs @@ -0,0 +1,212 @@ +# frv testcase for clddfu @($GRi,$GRj),$FRk,$CCi,$ccond +# mach: all + + .include "testutils.inc" + + start + + .global clddfu +clddfu: + set_spr_immed 0x1b1b,cccr + set_gr_gr sp,gr21 + + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_gr sp,gr20 + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + + set_gr_immed 0,gr7 + clddfu @(sp,gr7),fr8,cc0,1 + test_fr_limmed 0xbeef,0xdead,fr8 + test_fr_limmed 0xdead,0xbeef,fr9 + test_gr_gr sp,gr20 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + clddfu @(sp,gr7),fr8,cc0,1 + test_fr_limmed 0xbeef,0xdead,fr8 + test_fr_limmed 0xdead,0xbeef,fr9 + test_gr_gr sp,gr20 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed 8,sp + set_gr_immed -8,gr7 + clddfu @(sp,gr7),fr8,cc4,1 + test_fr_limmed 0xbeef,0xdead,fr8 + test_fr_limmed 0xdead,0xbeef,fr9 + test_gr_gr sp,gr20 + + set_gr_gr sp,gr21 + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_gr sp,gr20 + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + + set_gr_immed 0,gr7 + clddfu @(sp,gr7),fr8,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + test_gr_gr sp,gr20 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed -8,gr20 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + clddfu @(sp,gr7),fr8,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + test_gr_gr sp,gr20 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed 16,gr20 + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + clddfu @(sp,gr7),fr8,cc4,0 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + test_gr_gr sp,gr20 + + set_gr_gr sp,gr21 + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_gr sp,gr20 + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + + set_gr_immed 0,gr7 + clddfu @(sp,gr7),fr8,cc1,0 + test_fr_limmed 0xbeef,0xdead,fr8 + test_fr_limmed 0xdead,0xbeef,fr9 + test_gr_gr sp,gr20 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + clddfu @(sp,gr7),fr8,cc1,0 + test_fr_limmed 0xbeef,0xdead,fr8 + test_fr_limmed 0xdead,0xbeef,fr9 + test_gr_gr sp,gr20 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed 8,sp + set_gr_immed -8,gr7 + clddfu @(sp,gr7),fr8,cc5,0 + test_fr_limmed 0xbeef,0xdead,fr8 + test_fr_limmed 0xdead,0xbeef,fr9 + test_gr_gr sp,gr20 + + set_gr_gr sp,gr21 + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_gr sp,gr20 + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + + set_gr_immed 0,gr7 + clddfu @(sp,gr7),fr8,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + test_gr_gr sp,gr20 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed -8,gr20 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + clddfu @(sp,gr7),fr8,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + test_gr_gr sp,gr20 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed 16,gr20 + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + clddfu @(sp,gr7),fr8,cc5,1 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + test_gr_gr sp,gr20 + + set_gr_gr sp,gr21 + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_gr sp,gr20 + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + + set_gr_immed 0,gr7 + clddfu @(sp,gr7),fr8,cc2,0 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + test_gr_gr sp,gr20 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed -8,gr20 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + clddfu @(sp,gr7),fr8,cc2,1 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + test_gr_gr sp,gr20 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed 16,gr20 + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + clddfu @(sp,gr7),fr8,cc6,0 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + test_gr_gr sp,gr20 + + set_gr_gr sp,gr21 + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_gr sp,gr20 + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + + set_gr_immed 0,gr7 + clddfu @(sp,gr7),fr8,cc3,1 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + test_gr_gr sp,gr20 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed -8,gr20 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + clddfu @(sp,gr7),fr8,cc3,0 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + test_gr_gr sp,gr20 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed 16,gr20 + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + clddfu @(sp,gr7),fr8,cc7,1 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + test_gr_gr sp,gr20 + + pass diff --git a/sim/testsuite/sim/frv/clddu.cgs b/sim/testsuite/sim/frv/clddu.cgs new file mode 100644 index 0000000..91df6d8 --- /dev/null +++ b/sim/testsuite/sim/frv/clddu.cgs @@ -0,0 +1,219 @@ +# frv testcase for clddu @($GRi,$GRj),$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global clddu +clddu: + set_spr_immed 0x1b1b,cccr + set_gr_gr sp,gr21 + + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_gr sp,gr20 + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + + set_gr_immed 0,gr7 + clddu @(sp,gr7),gr8,cc0,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + test_gr_gr sp,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + clddu @(sp,gr7),gr8,cc0,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + test_gr_gr sp,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed 8,sp + set_gr_immed -8,gr7 + clddu @(sp,gr7),gr8,cc4,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_gr sp,gr20 + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + + set_gr_immed 0,gr7 + clddu @(sp,gr7),gr8,cc0,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_gr sp,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed -8,gr20 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + clddu @(sp,gr7),gr8,cc0,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_gr sp,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed 16,gr20 + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + clddu @(sp,gr7),gr8,cc4,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_gr sp,gr20 + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + + set_gr_immed 0,gr7 + clddu @(sp,gr7),gr8,cc1,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + test_gr_gr sp,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + clddu @(sp,gr7),gr8,cc1,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + test_gr_gr sp,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed 8,sp + set_gr_immed -8,gr7 + clddu @(sp,gr7),gr8,cc5,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_gr sp,gr20 + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + + set_gr_immed 0,gr7 + clddu @(sp,gr7),gr8,cc1,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_gr sp,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed -8,gr20 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + clddu @(sp,gr7),gr8,cc1,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_gr sp,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed 16,gr20 + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + clddu @(sp,gr7),gr8,cc5,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_gr sp,gr20 + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + + set_gr_immed 0,gr7 + clddu @(sp,gr7),gr8,cc2,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_gr sp,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed -8,gr20 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + clddu @(sp,gr7),gr8,cc2,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_gr sp,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed 16,gr20 + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + clddu @(sp,gr7),gr8,cc6,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_gr sp,gr20 + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + + set_gr_immed 0,gr7 + clddu @(sp,gr7),gr8,cc3,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_gr sp,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed -8,gr20 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + clddu @(sp,gr7),gr8,cc3,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_gr sp,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed 16,gr20 + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + clddu @(sp,gr7),gr8,cc7,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_gr sp,gr20 + + set_gr_gr gr21,gr8 + inc_gr_immed -12,gr8 + set_gr_immed 8,gr7 + clddu @(gr8,gr7),gr8,cc0,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + + pass diff --git a/sim/testsuite/sim/frv/cldf.cgs b/sim/testsuite/sim/frv/cldf.cgs new file mode 100644 index 0000000..011a02a --- /dev/null +++ b/sim/testsuite/sim/frv/cldf.cgs @@ -0,0 +1,126 @@ +# frv testcase for cldf @($GRi,$GRj),$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cldf +cldf: + set_spr_immed 0x1b1b,cccr + + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldf @(sp,gr7),fr8,cc0,1 + test_fr_limmed 0xdead,0xbeef,fr8 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + cldf @(sp,gr7),fr8,cc0,1 + test_fr_limmed 0xdead,0xbeef,fr8 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed 8,sp + set_gr_immed -4,gr7 + cldf @(sp,gr7),fr8,cc4,1 + test_fr_limmed 0xdead,0xbeef,fr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldf @(sp,gr7),fr8,cc0,0 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + cldf @(sp,gr7),fr8,cc0,0 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed 8,sp + set_gr_immed -4,gr7 + cldf @(sp,gr7),fr8,cc4,0 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldf @(sp,gr7),fr8,cc1,0 + test_fr_limmed 0xdead,0xbeef,fr8 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + cldf @(sp,gr7),fr8,cc1,0 + test_fr_limmed 0xdead,0xbeef,fr8 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed 8,sp + set_gr_immed -4,gr7 + cldf @(sp,gr7),fr8,cc5,0 + test_fr_limmed 0xdead,0xbeef,fr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldf @(sp,gr7),fr8,cc1,1 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + cldf @(sp,gr7),fr8,cc1,1 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed 8,sp + set_gr_immed -4,gr7 + cldf @(sp,gr7),fr8,cc5,1 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldf @(sp,gr7),fr8,cc2,0 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + cldf @(sp,gr7),fr8,cc2,1 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed 8,sp + set_gr_immed -4,gr7 + cldf @(sp,gr7),fr8,cc6,0 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldf @(sp,gr7),fr8,cc3,1 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + cldf @(sp,gr7),fr8,cc3,0 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed 8,sp + set_gr_immed -4,gr7 + cldf @(sp,gr7),fr8,cc7,1 + test_fr_limmed 0xbeef,0xdead,fr8 + + pass diff --git a/sim/testsuite/sim/frv/cldfu.cgs b/sim/testsuite/sim/frv/cldfu.cgs new file mode 100644 index 0000000..d4abef0 --- /dev/null +++ b/sim/testsuite/sim/frv/cldfu.cgs @@ -0,0 +1,164 @@ +# frv testcase for cldfu @($GRi,$GRj),$FRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cldfu +cldfu: + set_spr_immed 0x1b1b,cccr + set_gr_gr sp,gr21 + + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldfu @(sp,gr7),fr8,cc0,1 + test_fr_limmed 0xdead,0xbeef,fr8 + test_gr_gr sp,gr20 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + cldfu @(sp,gr7),fr8,cc0,1 + test_fr_limmed 0xdead,0xbeef,fr8 + test_gr_gr sp,gr20 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed 4,sp + set_gr_immed -4,gr7 + cldfu @(sp,gr7),fr8,cc4,1 + test_fr_limmed 0xdead,0xbeef,fr8 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldfu @(sp,gr7),fr8,cc0,0 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed -4,gr20 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + cldfu @(sp,gr7),fr8,cc0,0 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed 8,gr20 + inc_gr_immed 8,sp + set_gr_immed -4,gr7 + cldfu @(sp,gr7),fr8,cc4,0 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldfu @(sp,gr7),fr8,cc1,0 + test_fr_limmed 0xdead,0xbeef,fr8 + test_gr_gr sp,gr20 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + cldfu @(sp,gr7),fr8,cc1,0 + test_fr_limmed 0xdead,0xbeef,fr8 + test_gr_gr sp,gr20 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed 4,sp + set_gr_immed -4,gr7 + cldfu @(sp,gr7),fr8,cc5,0 + test_fr_limmed 0xdead,0xbeef,fr8 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldfu @(sp,gr7),fr8,cc1,1 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed -4,gr20 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + cldfu @(sp,gr7),fr8,cc1,1 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed 8,gr20 + inc_gr_immed 8,sp + set_gr_immed -4,gr7 + cldfu @(sp,gr7),fr8,cc5,1 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldfu @(sp,gr7),fr8,cc2,0 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed -4,gr20 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + cldfu @(sp,gr7),fr8,cc2,1 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed 8,gr20 + inc_gr_immed 8,sp + set_gr_immed -4,gr7 + cldfu @(sp,gr7),fr8,cc6,0 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldfu @(sp,gr7),fr8,cc3,1 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed -4,gr20 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + cldfu @(sp,gr7),fr8,cc3,0 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed 8,gr20 + inc_gr_immed 8,sp + set_gr_immed -4,gr7 + cldfu @(sp,gr7),fr8,cc7,1 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + pass diff --git a/sim/testsuite/sim/frv/cldhf.cgs b/sim/testsuite/sim/frv/cldhf.cgs new file mode 100644 index 0000000..26972ed --- /dev/null +++ b/sim/testsuite/sim/frv/cldhf.cgs @@ -0,0 +1,114 @@ +# frv testcase for cldhf @($GRi,$GRj),$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cldhf +cldhf: + set_spr_immed 0x1b1b,cccr + + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldhf @(sp,gr7),fr8,cc0,1 + test_fr_limmed 0x0000,0xdead,fr8 + + set_gr_immed 2,gr7 + cldhf @(sp,gr7),fr8,cc0,1 + test_fr_limmed 0x0000,0xbeef,fr8 + + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + cldhf @(sp,gr7),fr8,cc4,1 + test_fr_limmed 0x0000,0x0000,fr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldhf @(sp,gr7),fr8,cc0,0 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_gr_immed 2,gr7 + cldhf @(sp,gr7),fr8,cc0,0 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + cldhf @(sp,gr7),fr8,cc4,0 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldhf @(sp,gr7),fr8,cc1,0 + test_fr_limmed 0x0000,0xdead,fr8 + + set_gr_immed 2,gr7 + cldhf @(sp,gr7),fr8,cc1,0 + test_fr_limmed 0x0000,0xbeef,fr8 + + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + cldhf @(sp,gr7),fr8,cc5,0 + test_fr_limmed 0x0000,0x0000,fr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldhf @(sp,gr7),fr8,cc1,1 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_gr_immed 2,gr7 + cldhf @(sp,gr7),fr8,cc1,1 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + cldhf @(sp,gr7),fr8,cc5,1 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldhf @(sp,gr7),fr8,cc2,0 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_gr_immed 2,gr7 + cldhf @(sp,gr7),fr8,cc2,1 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + cldhf @(sp,gr7),fr8,cc6,0 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldhf @(sp,gr7),fr8,cc3,1 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_gr_immed 2,gr7 + cldhf @(sp,gr7),fr8,cc3,0 + test_fr_limmed 0xbeef,0xdead,fr8 + + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + cldhf @(sp,gr7),fr8,cc7,1 + test_fr_limmed 0xbeef,0xdead,fr8 + + pass diff --git a/sim/testsuite/sim/frv/cldhfu.cgs b/sim/testsuite/sim/frv/cldhfu.cgs new file mode 100644 index 0000000..062e398 --- /dev/null +++ b/sim/testsuite/sim/frv/cldhfu.cgs @@ -0,0 +1,152 @@ +# frv testcase for cldhfu @($GRi,$GRj),$FRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cldhfu +cldhfu: + set_spr_immed 0x1b1b,cccr + set_gr_gr sp,gr21 + + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldhfu @(sp,gr7),fr8,cc0,1 + test_fr_limmed 0x0000,0xdead,fr8 + test_gr_gr sp,gr20 + + inc_gr_immed 2,gr20 + set_gr_immed 2,gr7 + cldhfu @(sp,gr7),fr8,cc0,1 + test_fr_limmed 0x0000,0xbeef,fr8 + test_gr_gr sp,gr20 + + inc_gr_immed -2,sp + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + cldhfu @(sp,gr7),fr8,cc4,1 + test_fr_limmed 0x0000,0x0000,fr8 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldhfu @(sp,gr7),fr8,cc0,0 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + set_gr_immed 2,gr7 + cldhfu @(sp,gr7),fr8,cc0,0 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + inc_gr_immed 4,gr20 + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + cldhfu @(sp,gr7),fr8,cc4,0 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldhfu @(sp,gr7),fr8,cc1,0 + test_fr_limmed 0x0000,0xdead,fr8 + test_gr_gr sp,gr20 + + inc_gr_immed 2,gr20 + set_gr_immed 2,gr7 + cldhfu @(sp,gr7),fr8,cc1,0 + test_fr_limmed 0x0000,0xbeef,fr8 + test_gr_gr sp,gr20 + + inc_gr_immed -2,sp + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + cldhfu @(sp,gr7),fr8,cc5,0 + test_fr_limmed 0x0000,0x0000,fr8 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldhfu @(sp,gr7),fr8,cc1,1 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + set_gr_immed 2,gr7 + cldhfu @(sp,gr7),fr8,cc1,1 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + inc_gr_immed 4,gr20 + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + cldhfu @(sp,gr7),fr8,cc5,1 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldhfu @(sp,gr7),fr8,cc2,0 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + set_gr_immed 2,gr7 + cldhfu @(sp,gr7),fr8,cc2,1 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + inc_gr_immed 4,gr20 + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + cldhfu @(sp,gr7),fr8,cc6,0 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + cldhfu @(sp,gr7),fr8,cc3,1 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + set_gr_immed 2,gr7 + cldhfu @(sp,gr7),fr8,cc3,0 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + inc_gr_immed 4,gr20 + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + cldhfu @(sp,gr7),fr8,cc7,1 + test_fr_limmed 0xbeef,0xdead,fr8 + test_gr_gr sp,gr20 + + pass diff --git a/sim/testsuite/sim/frv/cldq.cgs b/sim/testsuite/sim/frv/cldq.cgs new file mode 100644 index 0000000..bfb433b --- /dev/null +++ b/sim/testsuite/sim/frv/cldq.cgs @@ -0,0 +1,276 @@ +# frv testcase for cldq @($GRi,$GRj),$GRk,$CCi,$cond +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global cldq +cldq: + set_spr_immed 0x1b1b,cccr + + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0x1234,0x5678,sp + inc_gr_immed -4,sp + set_mem_limmed 0x9abc,0xdef0,sp + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + + set_gr_immed 0,gr7 + cldq @(sp,gr7),gr8,cc0,1 + test_gr_limmed 0x9abc,0xdef0,gr8 + test_gr_limmed 0x1234,0x5678,gr9 + test_gr_limmed 0xbeef,0xdead,gr10 + test_gr_limmed 0xdead,0xbeef,gr11 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed -16,sp + set_gr_immed 16,gr7 + cldq @(sp,gr7),gr8,cc0,1 + test_gr_limmed 0x9abc,0xdef0,gr8 + test_gr_limmed 0x1234,0x5678,gr9 + test_gr_limmed 0xbeef,0xdead,gr10 + test_gr_limmed 0xdead,0xbeef,gr11 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed 32,sp + set_gr_immed -16,gr7 + cldq @(sp,gr7),gr8,cc4,1 + test_gr_limmed 0x9abc,0xdef0,gr8 + test_gr_limmed 0x1234,0x5678,gr9 + test_gr_limmed 0xbeef,0xdead,gr10 + test_gr_limmed 0xdead,0xbeef,gr11 + + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0x1234,0x5678,sp + inc_gr_immed -4,sp + set_mem_limmed 0x9abc,0xdef0,sp + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + + set_gr_immed 0,gr7 + cldq @(sp,gr7),gr8,cc0,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_limmed 0x1234,0x5678,gr10 + test_gr_limmed 0x9abc,0xdef0,gr11 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed -16,sp + set_gr_immed 16,gr7 + cldq @(sp,gr7),gr8,cc0,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_limmed 0x1234,0x5678,gr10 + test_gr_limmed 0x9abc,0xdef0,gr11 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed 32,sp + set_gr_immed -16,gr7 + cldq @(sp,gr7),gr8,cc4,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_limmed 0x1234,0x5678,gr10 + test_gr_limmed 0x9abc,0xdef0,gr11 + + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0x1234,0x5678,sp + inc_gr_immed -4,sp + set_mem_limmed 0x9abc,0xdef0,sp + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + + set_gr_immed 0,gr7 + cldq @(sp,gr7),gr8,cc1,0 + test_gr_limmed 0x9abc,0xdef0,gr8 + test_gr_limmed 0x1234,0x5678,gr9 + test_gr_limmed 0xbeef,0xdead,gr10 + test_gr_limmed 0xdead,0xbeef,gr11 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed -16,sp + set_gr_immed 16,gr7 + cldq @(sp,gr7),gr8,cc1,0 + test_gr_limmed 0x9abc,0xdef0,gr8 + test_gr_limmed 0x1234,0x5678,gr9 + test_gr_limmed 0xbeef,0xdead,gr10 + test_gr_limmed 0xdead,0xbeef,gr11 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed 32,sp + set_gr_immed -16,gr7 + cldq @(sp,gr7),gr8,cc5,0 + test_gr_limmed 0x9abc,0xdef0,gr8 + test_gr_limmed 0x1234,0x5678,gr9 + test_gr_limmed 0xbeef,0xdead,gr10 + test_gr_limmed 0xdead,0xbeef,gr11 + + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0x1234,0x5678,sp + inc_gr_immed -4,sp + set_mem_limmed 0x9abc,0xdef0,sp + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + + set_gr_immed 0,gr7 + cldq @(sp,gr7),gr8,cc1,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_limmed 0x1234,0x5678,gr10 + test_gr_limmed 0x9abc,0xdef0,gr11 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed -16,sp + set_gr_immed 16,gr7 + cldq @(sp,gr7),gr8,cc1,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_limmed 0x1234,0x5678,gr10 + test_gr_limmed 0x9abc,0xdef0,gr11 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed 32,sp + set_gr_immed -16,gr7 + cldq @(sp,gr7),gr8,cc5,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_limmed 0x1234,0x5678,gr10 + test_gr_limmed 0x9abc,0xdef0,gr11 + + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0x1234,0x5678,sp + inc_gr_immed -4,sp + set_mem_limmed 0x9abc,0xdef0,sp + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + + set_gr_immed 0,gr7 + cldq @(sp,gr7),gr8,cc2,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_limmed 0x1234,0x5678,gr10 + test_gr_limmed 0x9abc,0xdef0,gr11 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed -16,sp + set_gr_immed 16,gr7 + cldq @(sp,gr7),gr8,cc2,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_limmed 0x1234,0x5678,gr10 + test_gr_limmed 0x9abc,0xdef0,gr11 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed 32,sp + set_gr_immed -16,gr7 + cldq @(sp,gr7),gr8,cc6,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_limmed 0x1234,0x5678,gr10 + test_gr_limmed 0x9abc,0xdef0,gr11 + + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0x1234,0x5678,sp + inc_gr_immed -4,sp + set_mem_limmed 0x9abc,0xdef0,sp + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + + set_gr_immed 0,gr7 + cldq @(sp,gr7),gr8,cc3,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_limmed 0x1234,0x5678,gr10 + test_gr_limmed 0x9abc,0xdef0,gr11 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed -16,sp + set_gr_immed 16,gr7 + cldq @(sp,gr7),gr8,cc3,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_limmed 0x1234,0x5678,gr10 + test_gr_limmed 0x9abc,0xdef0,gr11 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed 32,sp + set_gr_immed -16,gr7 + cldq @(sp,gr7),gr8,cc7,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_limmed 0x1234,0x5678,gr10 + test_gr_limmed 0x9abc,0xdef0,gr11 + + pass diff --git a/sim/testsuite/sim/frv/cldqu.cgs b/sim/testsuite/sim/frv/cldqu.cgs new file mode 100644 index 0000000..fa0949a --- /dev/null +++ b/sim/testsuite/sim/frv/cldqu.cgs @@ -0,0 +1,318 @@ +# frv testcase for cldqu @($GRi,$GRj),$GRk,$CCi,$cond +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global cldqu +cldqu: + set_spr_immed 0x1b1b,cccr + set_gr_gr sp,gr21 + + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0x1234,0x5678,sp + inc_gr_immed -4,sp + set_mem_limmed 0x9abc,0xdef0,sp + set_gr_gr sp,gr20 + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + + set_gr_immed 0,gr7 + cldqu @(sp,gr7),gr8,cc0,1 + test_gr_limmed 0x9abc,0xdef0,gr8 + test_gr_limmed 0x1234,0x5678,gr9 + test_gr_limmed 0xbeef,0xdead,gr10 + test_gr_limmed 0xdead,0xbeef,gr11 + test_gr_gr sp,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed -16,sp + set_gr_immed 16,gr7 + cldqu @(sp,gr7),gr8,cc0,1 + test_gr_limmed 0x9abc,0xdef0,gr8 + test_gr_limmed 0x1234,0x5678,gr9 + test_gr_limmed 0xbeef,0xdead,gr10 + test_gr_limmed 0xdead,0xbeef,gr11 + test_gr_gr sp,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed 16,sp + set_gr_immed -16,gr7 + cldqu @(sp,gr7),gr8,cc4,1 + test_gr_limmed 0x9abc,0xdef0,gr8 + test_gr_limmed 0x1234,0x5678,gr9 + test_gr_limmed 0xbeef,0xdead,gr10 + test_gr_limmed 0xdead,0xbeef,gr11 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0x1234,0x5678,sp + inc_gr_immed -4,sp + set_mem_limmed 0x9abc,0xdef0,sp + set_gr_gr sp,gr20 + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + + set_gr_immed 0,gr7 + cldqu @(sp,gr7),gr8,cc0,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_limmed 0x1234,0x5678,gr10 + test_gr_limmed 0x9abc,0xdef0,gr11 + test_gr_gr sp,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed -16,gr20 + inc_gr_immed -16,sp + set_gr_immed 16,gr7 + cldqu @(sp,gr7),gr8,cc0,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_limmed 0x1234,0x5678,gr10 + test_gr_limmed 0x9abc,0xdef0,gr11 + test_gr_gr sp,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed 32,gr20 + inc_gr_immed 32,sp + set_gr_immed -16,gr7 + cldqu @(sp,gr7),gr8,cc4,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_limmed 0x1234,0x5678,gr10 + test_gr_limmed 0x9abc,0xdef0,gr11 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0x1234,0x5678,sp + inc_gr_immed -4,sp + set_mem_limmed 0x9abc,0xdef0,sp + set_gr_gr sp,gr20 + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + + set_gr_immed 0,gr7 + cldqu @(sp,gr7),gr8,cc1,0 + test_gr_limmed 0x9abc,0xdef0,gr8 + test_gr_limmed 0x1234,0x5678,gr9 + test_gr_limmed 0xbeef,0xdead,gr10 + test_gr_limmed 0xdead,0xbeef,gr11 + test_gr_gr sp,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed -16,sp + set_gr_immed 16,gr7 + cldqu @(sp,gr7),gr8,cc1,0 + test_gr_limmed 0x9abc,0xdef0,gr8 + test_gr_limmed 0x1234,0x5678,gr9 + test_gr_limmed 0xbeef,0xdead,gr10 + test_gr_limmed 0xdead,0xbeef,gr11 + test_gr_gr sp,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed 16,sp + set_gr_immed -16,gr7 + cldqu @(sp,gr7),gr8,cc5,0 + test_gr_limmed 0x9abc,0xdef0,gr8 + test_gr_limmed 0x1234,0x5678,gr9 + test_gr_limmed 0xbeef,0xdead,gr10 + test_gr_limmed 0xdead,0xbeef,gr11 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0x1234,0x5678,sp + inc_gr_immed -4,sp + set_mem_limmed 0x9abc,0xdef0,sp + set_gr_gr sp,gr20 + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + + set_gr_immed 0,gr7 + cldqu @(sp,gr7),gr8,cc1,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_limmed 0x1234,0x5678,gr10 + test_gr_limmed 0x9abc,0xdef0,gr11 + test_gr_gr sp,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed -16,gr20 + inc_gr_immed -16,sp + set_gr_immed 16,gr7 + cldqu @(sp,gr7),gr8,cc1,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_limmed 0x1234,0x5678,gr10 + test_gr_limmed 0x9abc,0xdef0,gr11 + test_gr_gr sp,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed 32,gr20 + inc_gr_immed 32,sp + set_gr_immed -16,gr7 + cldqu @(sp,gr7),gr8,cc5,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_limmed 0x1234,0x5678,gr10 + test_gr_limmed 0x9abc,0xdef0,gr11 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0x1234,0x5678,sp + inc_gr_immed -4,sp + set_mem_limmed 0x9abc,0xdef0,sp + set_gr_gr sp,gr20 + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + + set_gr_immed 0,gr7 + cldqu @(sp,gr7),gr8,cc2,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_limmed 0x1234,0x5678,gr10 + test_gr_limmed 0x9abc,0xdef0,gr11 + test_gr_gr sp,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed -16,gr20 + inc_gr_immed -16,sp + set_gr_immed 16,gr7 + cldqu @(sp,gr7),gr8,cc2,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_limmed 0x1234,0x5678,gr10 + test_gr_limmed 0x9abc,0xdef0,gr11 + test_gr_gr sp,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed 32,gr20 + inc_gr_immed 32,sp + set_gr_immed -16,gr7 + cldqu @(sp,gr7),gr8,cc6,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_limmed 0x1234,0x5678,gr10 + test_gr_limmed 0x9abc,0xdef0,gr11 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0x1234,0x5678,sp + inc_gr_immed -4,sp + set_mem_limmed 0x9abc,0xdef0,sp + set_gr_gr sp,gr20 + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + + set_gr_immed 0,gr7 + cldqu @(sp,gr7),gr8,cc3,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_limmed 0x1234,0x5678,gr10 + test_gr_limmed 0x9abc,0xdef0,gr11 + test_gr_gr sp,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed -16,gr20 + inc_gr_immed -16,sp + set_gr_immed 16,gr7 + cldqu @(sp,gr7),gr8,cc3,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_limmed 0x1234,0x5678,gr10 + test_gr_limmed 0x9abc,0xdef0,gr11 + test_gr_gr sp,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed 32,gr20 + inc_gr_immed 32,sp + set_gr_immed -16,gr7 + cldqu @(sp,gr7),gr8,cc7,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_limmed 0x1234,0x5678,gr10 + test_gr_limmed 0x9abc,0xdef0,gr11 + test_gr_gr sp,gr20 + + set_gr_gr gr21,gr8 + inc_gr_immed -28,gr8 + set_gr_immed 16,gr7 + cldqu @(gr8,gr7),gr8,cc0,1 + test_gr_limmed 0x9abc,0xdef0,gr8 + test_gr_limmed 0x1234,0x5678,gr9 + test_gr_limmed 0xbeef,0xdead,gr10 + test_gr_limmed 0xdead,0xbeef,gr11 + + pass diff --git a/sim/testsuite/sim/frv/cldsb.cgs b/sim/testsuite/sim/frv/cldsb.cgs new file mode 100644 index 0000000..ea8dd94 --- /dev/null +++ b/sim/testsuite/sim/frv/cldsb.cgs @@ -0,0 +1,114 @@ +# frv testcase for cldsb @($GRi,$GRj),$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cldsb +cldsb: + set_spr_immed 0x1b1b,cccr + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + cldsb @(sp,gr7),gr8,cc0,1 + test_gr_limmed 0xffff,0xffde,gr8 + + set_gr_immed 1,gr7 + cldsb @(sp,gr7),gr8,cc0,1 + test_gr_limmed 0xffff,0xffad,gr8 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldsb @(sp,gr7),gr8,cc4,1 + test_gr_immed 0,gr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + cldsb @(sp,gr7),gr8,cc0,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 1,gr7 + cldsb @(sp,gr7),gr8,cc0,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldsb @(sp,gr7),gr8,cc4,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + cldsb @(sp,gr7),gr8,cc1,0 + test_gr_limmed 0xffff,0xffde,gr8 + + set_gr_immed 1,gr7 + cldsb @(sp,gr7),gr8,cc1,0 + test_gr_limmed 0xffff,0xffad,gr8 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldsb @(sp,gr7),gr8,cc5,0 + test_gr_immed 0,gr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + cldsb @(sp,gr7),gr8,cc1,1 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 1,gr7 + cldsb @(sp,gr7),gr8,cc1,1 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldsb @(sp,gr7),gr8,cc5,1 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + cldsb @(sp,gr7),gr8,cc2,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 1,gr7 + cldsb @(sp,gr7),gr8,cc2,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldsb @(sp,gr7),gr8,cc6,1 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + cldsb @(sp,gr7),gr8,cc3,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 1,gr7 + cldsb @(sp,gr7),gr8,cc3,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldsb @(sp,gr7),gr8,cc7,1 + test_gr_limmed 0xbeef,0xdead,gr8 + + pass diff --git a/sim/testsuite/sim/frv/cldsbu.cgs b/sim/testsuite/sim/frv/cldsbu.cgs new file mode 100644 index 0000000..a4057f1 --- /dev/null +++ b/sim/testsuite/sim/frv/cldsbu.cgs @@ -0,0 +1,162 @@ +# frv testcase for cldsbu @($GRi,$GRj),$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cldsbu +cldsbu: + set_spr_immed 0x1b1b,cccr + set_gr_gr sp,gr20 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + cldsbu @(sp,gr7),gr8,cc0,1 + test_gr_limmed 0xffff,0xffde,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed 1,gr9 + set_gr_immed 1,gr7 + cldsbu @(sp,gr7),gr8,cc0,1 + test_gr_limmed 0xffff,0xffad,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed 2,gr9 + inc_gr_immed -1,sp + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldsbu @(sp,gr7),gr8,cc4,1 + test_gr_immed 0,gr8 + test_gr_gr sp,gr9 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + cldsbu @(sp,gr7),gr8,cc0,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_immed 1,gr7 + cldsbu @(sp,gr7),gr8,cc0,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + inc_gr_immed 4,gr9 + set_gr_immed -1,gr7 + cldsbu @(sp,gr7),gr8,cc4,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + cldsbu @(sp,gr7),gr8,cc1,0 + test_gr_limmed 0xffff,0xffde,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed 1,gr9 + set_gr_immed 1,gr7 + cldsbu @(sp,gr7),gr8,cc1,0 + test_gr_limmed 0xffff,0xffad,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed 2,gr9 + inc_gr_immed -1,sp + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldsbu @(sp,gr7),gr8,cc5,0 + test_gr_immed 0,gr8 + test_gr_gr sp,gr9 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + cldsbu @(sp,gr7),gr8,cc1,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_immed 1,gr7 + cldsbu @(sp,gr7),gr8,cc1,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + inc_gr_immed 4,gr9 + set_gr_immed -1,gr7 + cldsbu @(sp,gr7),gr8,cc5,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + cldsbu @(sp,gr7),gr8,cc2,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_immed 1,gr7 + cldsbu @(sp,gr7),gr8,cc2,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + inc_gr_immed 4,gr9 + set_gr_immed -1,gr7 + cldsbu @(sp,gr7),gr8,cc6,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + cldsbu @(sp,gr7),gr8,cc3,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_immed 1,gr7 + cldsbu @(sp,gr7),gr8,cc3,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + inc_gr_immed 4,gr9 + set_gr_immed -1,gr7 + cldsbu @(sp,gr7),gr8,cc7,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr8 + set_gr_immed 1,gr7 + cldsbu @(gr8,gr7),gr8,cc0,1 + test_gr_limmed 0xffff,0xffad,gr8 + + pass + diff --git a/sim/testsuite/sim/frv/cldsh.cgs b/sim/testsuite/sim/frv/cldsh.cgs new file mode 100644 index 0000000..091d720 --- /dev/null +++ b/sim/testsuite/sim/frv/cldsh.cgs @@ -0,0 +1,114 @@ +# frv testcase for cldsh @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global cldsh +cldsh: + set_spr_immed 0x1b1b,cccr + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + cldsh @(sp,gr7),gr8,cc0,1 + test_gr_limmed 0xffff,0xdead,gr8 + + set_gr_immed 2,gr7 + cldsh @(sp,gr7),gr8,cc0,1 + test_gr_limmed 0xffff,0xbeef,gr8 + + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + cldsh @(sp,gr7),gr8,cc4,1 + test_gr_immed 0,gr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + cldsh @(sp,gr7),gr8,cc0,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 2,gr7 + cldsh @(sp,gr7),gr8,cc0,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + cldsh @(sp,gr7),gr8,cc4,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + cldsh @(sp,gr7),gr8,cc1,0 + test_gr_limmed 0xffff,0xdead,gr8 + + set_gr_immed 2,gr7 + cldsh @(sp,gr7),gr8,cc1,0 + test_gr_limmed 0xffff,0xbeef,gr8 + + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + cldsh @(sp,gr7),gr8,cc5,0 + test_gr_immed 0,gr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + cldsh @(sp,gr7),gr8,cc1,1 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 2,gr7 + cldsh @(sp,gr7),gr8,cc1,1 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + cldsh @(sp,gr7),gr8,cc5,1 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + cldsh @(sp,gr7),gr8,cc2,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 2,gr7 + cldsh @(sp,gr7),gr8,cc2,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + cldsh @(sp,gr7),gr8,cc6,1 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + cldsh @(sp,gr7),gr8,cc3,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 2,gr7 + cldsh @(sp,gr7),gr8,cc3,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + cldsh @(sp,gr7),gr8,cc7,1 + test_gr_limmed 0xbeef,0xdead,gr8 + + pass diff --git a/sim/testsuite/sim/frv/cldshu.cgs b/sim/testsuite/sim/frv/cldshu.cgs new file mode 100644 index 0000000..491352e --- /dev/null +++ b/sim/testsuite/sim/frv/cldshu.cgs @@ -0,0 +1,159 @@ +# frv testcase for cldshu @($GRi,$GRj),$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cldshu +cldshu: + set_spr_immed 0x1b1b,cccr + set_gr_gr sp,gr20 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + cldshu @(sp,gr7),gr8,cc0,1 + test_gr_limmed 0xffff,0xdead,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed 2,gr9 + set_gr_immed 2,gr7 + cldshu @(sp,gr7),gr8,cc0,1 + test_gr_limmed 0xffff,0xbeef,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed -2,sp + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + cldshu @(sp,gr7),gr8,cc4,1 + test_gr_immed 0,gr8 + test_gr_gr sp,gr9 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + cldshu @(sp,gr7),gr8,cc0,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_immed 2,gr7 + cldshu @(sp,gr7),gr8,cc0,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed 4,gr9 + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + cldshu @(sp,gr7),gr8,cc4,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + cldshu @(sp,gr7),gr8,cc1,0 + test_gr_limmed 0xffff,0xdead,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed 2,gr9 + set_gr_immed 2,gr7 + cldshu @(sp,gr7),gr8,cc1,0 + test_gr_limmed 0xffff,0xbeef,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed -2,sp + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + cldshu @(sp,gr7),gr8,cc5,0 + test_gr_immed 0,gr8 + test_gr_gr sp,gr9 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + cldshu @(sp,gr7),gr8,cc1,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_immed 2,gr7 + cldshu @(sp,gr7),gr8,cc1,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed 4,gr9 + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + cldshu @(sp,gr7),gr8,cc5,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + cldshu @(sp,gr7),gr8,cc2,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_immed 2,gr7 + cldshu @(sp,gr7),gr8,cc2,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed 4,gr9 + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + cldshu @(sp,gr7),gr8,cc6,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + cldshu @(sp,gr7),gr8,cc3,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_immed 2,gr7 + cldshu @(sp,gr7),gr8,cc3,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed 4,gr9 + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + cldshu @(sp,gr7),gr8,cc7,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr8 + set_gr_immed 2,gr7 + cldshu @(gr8,gr7),gr8,cc0,1 + test_gr_limmed 0xffff,0xbeef,gr8 + + pass diff --git a/sim/testsuite/sim/frv/cldu.cgs b/sim/testsuite/sim/frv/cldu.cgs new file mode 100644 index 0000000..61cf606 --- /dev/null +++ b/sim/testsuite/sim/frv/cldu.cgs @@ -0,0 +1,172 @@ +# frv testcase for cldu @($GRi,$GRj),$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cldu +cldu: + set_spr_immed 0x1b1b,cccr + set_gr_gr sp,gr20 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + cldu @(sp,gr7),gr8,cc0,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_gr sp,gr9 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + cldu @(sp,gr7),gr8,cc0,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_gr sp,gr9 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed 4,sp + set_gr_immed -4,gr7 + cldu @(sp,gr7),gr8,cc4,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_gr sp,gr9 + + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + cldu @(sp,gr7),gr8,cc0,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed -4,gr9 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + cldu @(sp,gr7),gr8,cc0,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed 8,gr9 + inc_gr_immed 8,sp + set_gr_immed -4,gr7 + cldu @(sp,gr7),gr8,cc4,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + cldu @(sp,gr7),gr8,cc1,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_gr sp,gr9 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + cldu @(sp,gr7),gr8,cc1,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_gr sp,gr9 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed 4,sp + set_gr_immed -4,gr7 + cldu @(sp,gr7),gr8,cc5,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_gr sp,gr9 + + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + cldu @(sp,gr7),gr8,cc1,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed -4,gr9 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + cldu @(sp,gr7),gr8,cc1,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed 8,gr9 + inc_gr_immed 8,sp + set_gr_immed -4,gr7 + cldu @(sp,gr7),gr8,cc5,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + cldu @(sp,gr7),gr8,cc2,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed -4,gr9 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + cldu @(sp,gr7),gr8,cc2,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed 8,gr9 + inc_gr_immed 8,sp + set_gr_immed -4,gr7 + cldu @(sp,gr7),gr8,cc6,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + cldu @(sp,gr7),gr8,cc3,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed -4,gr9 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + cldu @(sp,gr7),gr8,cc3,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed 8,gr9 + inc_gr_immed 8,sp + set_gr_immed -4,gr7 + cldu @(sp,gr7),gr8,cc7,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr8 + inc_gr_immed -4,gr8 + set_gr_immed 4,gr7 + cldu @(gr8,gr7),gr8,cc0,1 + test_gr_limmed 0xdead,0xbeef,gr8 + + pass diff --git a/sim/testsuite/sim/frv/cldub.cgs b/sim/testsuite/sim/frv/cldub.cgs new file mode 100644 index 0000000..b1f0776 --- /dev/null +++ b/sim/testsuite/sim/frv/cldub.cgs @@ -0,0 +1,114 @@ +# frv testcase for cldub @($GRi,$GRj),$GRk,$cci,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cldub +cldub: + set_spr_immed 0x1b1b,cccr + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + cldub @(sp,gr7),gr8,cc0,1 + test_gr_limmed 0x0000,0x00de,gr8 + + set_gr_immed 1,gr7 + cldub @(sp,gr7),gr8,cc0,1 + test_gr_limmed 0x0000,0x00ad,gr8 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldub @(sp,gr7),gr8,cc4,1 + test_gr_limmed 0x0000,0x0000,gr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + cldub @(sp,gr7),gr8,cc0,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 1,gr7 + cldub @(sp,gr7),gr8,cc0,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldub @(sp,gr7),gr8,cc4,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + cldub @(sp,gr7),gr8,cc1,0 + test_gr_limmed 0x0000,0x00de,gr8 + + set_gr_immed 1,gr7 + cldub @(sp,gr7),gr8,cc1,0 + test_gr_limmed 0x0000,0x00ad,gr8 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldub @(sp,gr7),gr8,cc5,0 + test_gr_limmed 0x0000,0x0000,gr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + cldub @(sp,gr7),gr8,cc1,1 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 1,gr7 + cldub @(sp,gr7),gr8,cc1,1 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldub @(sp,gr7),gr8,cc5,1 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + cldub @(sp,gr7),gr8,cc2,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 1,gr7 + cldub @(sp,gr7),gr8,cc2,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldub @(sp,gr7),gr8,cc6,1 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + cldub @(sp,gr7),gr8,cc3,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 1,gr7 + cldub @(sp,gr7),gr8,cc3,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldub @(sp,gr7),gr8,cc7,1 + test_gr_limmed 0xbeef,0xdead,gr8 + + pass diff --git a/sim/testsuite/sim/frv/cldubu.cgs b/sim/testsuite/sim/frv/cldubu.cgs new file mode 100644 index 0000000..c9f9579 --- /dev/null +++ b/sim/testsuite/sim/frv/cldubu.cgs @@ -0,0 +1,155 @@ +# frv testcase for cldubu @($GRi,$GRj),$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cldubu +cldubu: + set_spr_immed 0x1b1b,cccr + set_gr_gr sp,gr20 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + cldubu @(sp,gr7),gr8,cc0,1 + test_gr_limmed 0x0000,0x00de,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed 1,gr9 + set_gr_immed 1,gr7 + cldubu @(sp,gr7),gr8,cc0,1 + test_gr_limmed 0x0000,0x00ad,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed 2,gr9 + inc_gr_immed -1,sp + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldubu @(sp,gr7),gr8,cc4,1 + test_gr_limmed 0x0000,0x0000,gr8 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + cldubu @(sp,gr7),gr8,cc0,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_immed 1,gr7 + cldubu @(sp,gr7),gr8,cc0,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed 4,gr9 + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldubu @(sp,gr7),gr8,cc4,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + cldubu @(sp,gr7),gr8,cc1,0 + test_gr_limmed 0x0000,0x00de,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed 1,gr9 + set_gr_immed 1,gr7 + cldubu @(sp,gr7),gr8,cc1,0 + test_gr_limmed 0x0000,0x00ad,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed 2,gr9 + inc_gr_immed -1,sp + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldubu @(sp,gr7),gr8,cc5,0 + test_gr_limmed 0x0000,0x0000,gr8 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + cldubu @(sp,gr7),gr8,cc1,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_immed 1,gr7 + cldubu @(sp,gr7),gr8,cc1,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed 4,gr9 + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldubu @(sp,gr7),gr8,cc5,1 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + cldubu @(sp,gr7),gr8,cc2,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_immed 1,gr7 + cldubu @(sp,gr7),gr8,cc2,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed 4,gr9 + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldubu @(sp,gr7),gr8,cc6,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + cldubu @(sp,gr7),gr8,cc3,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_immed 1,gr7 + cldubu @(sp,gr7),gr8,cc3,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed 4,gr9 + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + cldubu @(sp,gr7),gr8,cc7,1 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr8 + set_gr_immed 1,gr7 + cldubu @(gr8,gr7),gr8,cc0,1 + test_gr_limmed 0x0000,0x00ad,gr8 + + pass diff --git a/sim/testsuite/sim/frv/clduh.cgs b/sim/testsuite/sim/frv/clduh.cgs new file mode 100644 index 0000000..a9e505c --- /dev/null +++ b/sim/testsuite/sim/frv/clduh.cgs @@ -0,0 +1,114 @@ +# frv testcase for clduh @($GRi,$GRj),$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global clduh +clduh: + set_spr_immed 0x1b1b,cccr + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + clduh @(sp,gr7),gr8,cc0,1 + test_gr_limmed 0x0000,0xdead,gr8 + + set_gr_immed 2,gr7 + clduh @(sp,gr7),gr8,cc0,1 + test_gr_limmed 0x0000,0xbeef,gr8 + + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + clduh @(sp,gr7),gr8,cc4,1 + test_gr_limmed 0x0000,0x0000,gr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + clduh @(sp,gr7),gr8,cc0,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 2,gr7 + clduh @(sp,gr7),gr8,cc0,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + clduh @(sp,gr7),gr8,cc4,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + clduh @(sp,gr7),gr8,cc1,0 + test_gr_limmed 0x0000,0xdead,gr8 + + set_gr_immed 2,gr7 + clduh @(sp,gr7),gr8,cc1,0 + test_gr_limmed 0x0000,0xbeef,gr8 + + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + clduh @(sp,gr7),gr8,cc5,0 + test_gr_limmed 0x0000,0x0000,gr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + clduh @(sp,gr7),gr8,cc1,1 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 2,gr7 + clduh @(sp,gr7),gr8,cc1,1 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + clduh @(sp,gr7),gr8,cc5,1 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + clduh @(sp,gr7),gr8,cc2,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 2,gr7 + clduh @(sp,gr7),gr8,cc2,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + clduh @(sp,gr7),gr8,cc6,1 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + clduh @(sp,gr7),gr8,cc3,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 2,gr7 + clduh @(sp,gr7),gr8,cc3,0 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + clduh @(sp,gr7),gr8,cc7,1 + test_gr_limmed 0xbeef,0xdead,gr8 + + pass diff --git a/sim/testsuite/sim/frv/clduhu.cgs b/sim/testsuite/sim/frv/clduhu.cgs new file mode 100644 index 0000000..80eb381 --- /dev/null +++ b/sim/testsuite/sim/frv/clduhu.cgs @@ -0,0 +1,159 @@ +# frv testcase for clduhu @($GRi,$GRj),$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global clduhu +clduhu: + set_spr_immed 0x1b1b,cccr + set_gr_gr sp,gr20 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + clduhu @(sp,gr7),gr8,cc0,1 + test_gr_limmed 0x0000,0xdead,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed 2,gr9 + set_gr_immed 2,gr7 + clduhu @(sp,gr7),gr8,cc0,1 + test_gr_limmed 0x0000,0xbeef,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed -2,sp + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + clduhu @(sp,gr7),gr8,cc4,1 + test_gr_limmed 0x0000,0x0000,gr8 + test_gr_gr sp,gr9 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + clduhu @(sp,gr7),gr8,cc0,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_immed 2,gr7 + clduhu @(sp,gr7),gr8,cc0,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed 4,gr9 + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + clduhu @(sp,gr7),gr8,cc4,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + clduhu @(sp,gr7),gr8,cc1,0 + test_gr_limmed 0x0000,0xdead,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed 2,gr9 + set_gr_immed 2,gr7 + clduhu @(sp,gr7),gr8,cc1,0 + test_gr_limmed 0x0000,0xbeef,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed -2,sp + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + clduhu @(sp,gr7),gr8,cc5,0 + test_gr_limmed 0x0000,0x0000,gr8 + test_gr_gr sp,gr9 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + clduhu @(sp,gr7),gr8,cc1,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_immed 2,gr7 + clduhu @(sp,gr7),gr8,cc1,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed 4,gr9 + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + clduhu @(sp,gr7),gr8,cc5,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + clduhu @(sp,gr7),gr8,cc2,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_immed 2,gr7 + clduhu @(sp,gr7),gr8,cc2,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed 4,gr9 + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + clduhu @(sp,gr7),gr8,cc6,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + clduhu @(sp,gr7),gr8,cc3,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_immed 2,gr7 + clduhu @(sp,gr7),gr8,cc3,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed 4,gr9 + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + clduhu @(sp,gr7),gr8,cc7,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_gr sp,gr9 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr8 + set_gr_immed 2,gr7 + clduhu @(gr8,gr7),gr8,cc0,1 + test_gr_limmed 0x0000,0xbeef,gr8 + + pass diff --git a/sim/testsuite/sim/frv/clrfa.cgs b/sim/testsuite/sim/frv/clrfa.cgs new file mode 100644 index 0000000..8bba605 --- /dev/null +++ b/sim/testsuite/sim/frv/clrfa.cgs @@ -0,0 +1,27 @@ +# frv testcase for clrfa +# mach: frv + + .include "testutils.inc" + + start + + .global clrfa +clrfa: + nldfi @(sp,0),fr20 ; Activate fr20 with nesr.fr==1 + or_spr_immed 0x00100000,fner1 + nldi @(sp,0),gr20 ; Activate gr20 with nesr.fr==0 + or_spr_immed 0x00200000,fner1 + nldfi @(sp,0),fr52 ; Activate fr52 with nesr.fr==1 + or_spr_immed 0x00100000,fner0 + + clrfa + test_spr_immed 0x00000000,fner1 + test_spr_immed 0x00000000,fner0 + test_spr_immed 0,nesr0 + test_spr_immed 0,neear0 + test_spr_immed 0x94800401,nesr1 + test_spr_gr neear1,sp + test_spr_immed 0,nesr2 + test_spr_immed 0,neear2 + + pass diff --git a/sim/testsuite/sim/frv/clrfr.cgs b/sim/testsuite/sim/frv/clrfr.cgs new file mode 100644 index 0000000..9112815 --- /dev/null +++ b/sim/testsuite/sim/frv/clrfr.cgs @@ -0,0 +1,27 @@ +# frv testcase for clrfr $FRk +# mach: frv + + .include "testutils.inc" + + start + + .global clrfr +clrfr: + nldfi @(sp,0),fr20 ; Activate fr20 with nesr.fr==1 + or_spr_immed 0x00100000,fner1 + nldi @(sp,0),gr20 ; Activate gr20 with nesr.fr==0 + or_spr_immed 0x00200000,fner1 + nldfi @(sp,0),fr52 ; Activate fr52 with nesr.fr==1 + or_spr_immed 0x00100000,fner0 + + clrfr fr20 + test_spr_immed 0x00200000,fner1 + test_spr_immed 0x00100000,fner0 + test_spr_immed 0,nesr0 + test_spr_immed 0,neear0 + test_spr_immed 0x94800401,nesr1 + test_spr_gr neear1,sp + test_spr_immed 0xf4800801,nesr2 + test_spr_gr neear2,sp + + pass diff --git a/sim/testsuite/sim/frv/clrga.cgs b/sim/testsuite/sim/frv/clrga.cgs new file mode 100644 index 0000000..9e9a9a9 --- /dev/null +++ b/sim/testsuite/sim/frv/clrga.cgs @@ -0,0 +1,27 @@ +# frv testcase for clrga +# mach: frv + + .include "testutils.inc" + + start + + .global clrga +clrga: + nldi @(sp,0),gr20 ; Activate gr20 with nesr.fr==0 + or_spr_immed 0x00100000,gner1 + nldfi @(sp,0),fr20 ; Activate fr20 with nesr.fr==1 + or_spr_immed 0x00200000,gner1 + nldi @(sp,0),gr52 ; Activate gr52 with nesr.fr==0 + or_spr_immed 0x00100000,gner0 + + clrga + test_spr_immed 0x00000000,gner1 + test_spr_immed 0x00000000,gner0 + test_spr_immed 0,nesr0 + test_spr_immed 0,neear0 + test_spr_immed 0xd4800401,nesr1 + test_spr_gr neear1,sp + test_spr_immed 0,nesr2 + test_spr_immed 0,neear2 + + pass diff --git a/sim/testsuite/sim/frv/clrgr.cgs b/sim/testsuite/sim/frv/clrgr.cgs new file mode 100644 index 0000000..049b9e3 --- /dev/null +++ b/sim/testsuite/sim/frv/clrgr.cgs @@ -0,0 +1,27 @@ +# frv testcase for clrgr $GRk +# mach: frv + + .include "testutils.inc" + + start + + .global clrgr +clrgr: + nldi @(sp,0),gr20 ; Activate gr20 with nesr.fr==0 + or_spr_immed 0x00100000,gner1 + nldfi @(sp,0),fr20 ; Activate fr20 with nesr.fr==1 + or_spr_immed 0x00200000,gner1 + nldi @(sp,0),gr52 ; Activate gr52 with nesr.fr==0 + or_spr_immed 0x00100000,gner0 + + clrgr gr20 + test_spr_immed 0x00200000,gner1 + test_spr_immed 0x00100000,gner0 + test_spr_immed 0,nesr0 + test_spr_immed 0,neear0 + test_spr_immed 0xd4800401,nesr1 + test_spr_gr neear1,sp + test_spr_immed 0xb4800801,nesr2 + test_spr_gr neear2,sp + + pass diff --git a/sim/testsuite/sim/frv/cmaddhss.cgs b/sim/testsuite/sim/frv/cmaddhss.cgs new file mode 100644 index 0000000..1f04e67 --- /dev/null +++ b/sim/testsuite/sim/frv/cmaddhss.cgs @@ -0,0 +1,562 @@ +# frv testcase for cmaddhss $FRi,$FRj,$FRj,$CCi,$cond +# mach: frv fr500 fr400 + + .include "testutils.inc" + + start + + .global maddhss +maddhss: + set_spr_immed 0x1b1b,cccr + + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmaddhss fr10,fr11,fr12,cc0,1 + test_fr_limmed 0x0000,0x0000,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + cmaddhss fr10,fr11,fr12,cc0,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + cmaddhss fr10,fr11,fr12,cc0,1 + test_fr_limmed 0xbeef,0xdead,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmaddhss fr10,fr11,fr12,cc0,1 + test_fr_limmed 0x2345,0x6789,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + cmaddhss fr10,fr11,fr12,cc0,1 + test_fr_limmed 0x1233,0x5677,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmaddhss fr10,fr11,fr12,cc4,1 + test_fr_limmed 0x7fff,0x7fff,fr12 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xffff,0xfffe,fr11 + cmaddhss fr10,fr11,fr12,cc4,1 + test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set + test_fr_limmed 0x8000,0x8000,fr12 + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + cmaddhss fr10,fr11,fr12,cc4,1 + test_fr_limmed 0x8000,0x8000,fr12 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmaddhss.p fr10,fr10,fr12,cc4,1 + cmaddhss fr11,fr11,fr13,cc4,1 + test_fr_limmed 0x0002,0x0002,fr12 + test_fr_limmed 0x7fff,0x7fff,fr13 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie not set + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 0x3c,2,0xc,msr1 ; msr1.sie is set + test_spr_bits 2,1,1,msr1 ; msr1.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmaddhss fr10,fr11,fr12,cc1,0 + test_fr_limmed 0x0000,0x0000,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + cmaddhss fr10,fr11,fr12,cc1,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + cmaddhss fr10,fr11,fr12,cc1,0 + test_fr_limmed 0xbeef,0xdead,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmaddhss fr10,fr11,fr12,cc1,0 + test_fr_limmed 0x2345,0x6789,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + cmaddhss fr10,fr11,fr12,cc1,0 + test_fr_limmed 0x1233,0x5677,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmaddhss fr10,fr11,fr12,cc5,0 + test_fr_limmed 0x7fff,0x7fff,fr12 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xffff,0xfffe,fr11 + cmaddhss fr10,fr11,fr12,cc5,0 + test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set + test_fr_limmed 0x8000,0x8000,fr12 + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + cmaddhss fr10,fr11,fr12,cc5,0 + test_fr_limmed 0x8000,0x8000,fr12 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmaddhss.p fr10,fr10,fr12,cc5,0 + cmaddhss fr11,fr11,fr13,cc5,0 + test_fr_limmed 0x0002,0x0002,fr12 + test_fr_limmed 0x7fff,0x7fff,fr13 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie not set + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 0x3c,2,0xc,msr1 ; msr1.sie is set + test_spr_bits 2,1,1,msr1 ; msr1.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_fr_iimmed 0xdead,0xbeef,fr12 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmaddhss fr10,fr11,fr12,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + cmaddhss fr10,fr11,fr12,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + cmaddhss fr10,fr11,fr12,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmaddhss fr10,fr11,fr12,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + cmaddhss fr10,fr11,fr12,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmaddhss fr10,fr11,fr12,cc4,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xffff,0xfffe,fr11 + cmaddhss fr10,fr11,fr12,cc4,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + cmaddhss fr10,fr11,fr12,cc4,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xbeef,0xdead,fr13 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmaddhss.p fr10,fr10,fr12,cc4,0 + cmaddhss fr11,fr11,fr13,cc4,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_fr_limmed 0xbeef,0xdead,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xdead,0xbeef,fr12 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmaddhss fr10,fr11,fr12,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + cmaddhss fr10,fr11,fr12,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + cmaddhss fr10,fr11,fr12,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmaddhss fr10,fr11,fr12,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + cmaddhss fr10,fr11,fr12,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmaddhss fr10,fr11,fr12,cc5,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xffff,0xfffe,fr11 + cmaddhss fr10,fr11,fr12,cc5,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + cmaddhss fr10,fr11,fr12,cc5,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xbeef,0xdead,fr13 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmaddhss.p fr10,fr10,fr12,cc5,1 + cmaddhss fr11,fr11,fr13,cc5,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_fr_limmed 0xbeef,0xdead,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xdead,0xbeef,fr12 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmaddhss fr10,fr11,fr12,cc2,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + cmaddhss fr10,fr11,fr12,cc2,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + cmaddhss fr10,fr11,fr12,cc2,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmaddhss fr10,fr11,fr12,cc2,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + cmaddhss fr10,fr11,fr12,cc2,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmaddhss fr10,fr11,fr12,cc6,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xffff,0xfffe,fr11 + cmaddhss fr10,fr11,fr12,cc6,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + cmaddhss fr10,fr11,fr12,cc6,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xbeef,0xdead,fr13 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmaddhss.p fr10,fr10,fr12,cc6,1 + cmaddhss fr11,fr11,fr13,cc6,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_fr_limmed 0xbeef,0xdead,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set +; + set_fr_iimmed 0xdead,0xbeef,fr12 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmaddhss fr10,fr11,fr12,cc3,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + cmaddhss fr10,fr11,fr12,cc3,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + cmaddhss fr10,fr11,fr12,cc3,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmaddhss fr10,fr11,fr12,cc3,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + cmaddhss fr10,fr11,fr12,cc3,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmaddhss fr10,fr11,fr12,cc7,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xffff,0xfffe,fr11 + cmaddhss fr10,fr11,fr12,cc7,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + cmaddhss fr10,fr11,fr12,cc7,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xbeef,0xdead,fr13 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmaddhss.p fr10,fr10,fr12,cc7,1 + cmaddhss fr11,fr11,fr13,cc7,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_fr_limmed 0xbeef,0xdead,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + pass diff --git a/sim/testsuite/sim/frv/cmaddhus.cgs b/sim/testsuite/sim/frv/cmaddhus.cgs new file mode 100644 index 0000000..76da81d --- /dev/null +++ b/sim/testsuite/sim/frv/cmaddhus.cgs @@ -0,0 +1,496 @@ +# frv testcase for cmaddhus $FRi,$FRj,$FRj,$CCi,$cond +# mach: frv fr500 fr400 + + .include "testutils.inc" + + start + + .global cmaddhus +cmaddhus: + set_spr_immed 0x1b1b,cccr + + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmaddhus fr10,fr11,fr12,cc0,1 + test_fr_limmed 0x0000,0x0000,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + cmaddhus fr10,fr11,fr12,cc0,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + cmaddhus fr10,fr11,fr12,cc0,1 + test_fr_limmed 0xbeef,0xdead,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmaddhus fr10,fr11,fr12,cc0,1 + test_fr_limmed 0x2345,0x6789,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmaddhus fr10,fr11,fr12,cc4,1 + test_fr_limmed 0x8000,0x7fff,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xfffe,0xfffe,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + cmaddhus fr10,fr11,fr12,cc4,1 + test_fr_limmed 0xffff,0xffff,fr12 + test_spr_bits 0x3c,2,4,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0002,0x0001,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + cmaddhus fr10,fr11,fr12,cc4,1 + test_fr_limmed 0xffff,0xffff,fr12 + test_spr_bits 0x3c,2,8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + cmaddhus.p fr10,fr10,fr12,cc4,1 + cmaddhus fr11,fr11,fr13,cc4,1 + test_fr_limmed 0x0002,0x0002,fr12 + test_fr_limmed 0xffff,0xffff,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 0x3c,2,0xc,msr1 ; msr1.sie is set + test_spr_bits 2,1,1,msr1 ; msr1.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmaddhus fr10,fr11,fr12,cc1,0 + test_fr_limmed 0x0000,0x0000,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + cmaddhus fr10,fr11,fr12,cc1,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + cmaddhus fr10,fr11,fr12,cc1,0 + test_fr_limmed 0xbeef,0xdead,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmaddhus fr10,fr11,fr12,cc1,0 + test_fr_limmed 0x2345,0x6789,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmaddhus fr10,fr11,fr12,cc5,0 + test_fr_limmed 0x8000,0x7fff,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xfffe,0xfffe,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + cmaddhus fr10,fr11,fr12,cc5,0 + test_fr_limmed 0xffff,0xffff,fr12 + test_spr_bits 0x3c,2,4,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0002,0x0001,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + cmaddhus fr10,fr11,fr12,cc5,0 + test_fr_limmed 0xffff,0xffff,fr12 + test_spr_bits 0x3c,2,8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + cmaddhus.p fr10,fr10,fr12,cc5,0 + cmaddhus fr11,fr11,fr13,cc5,0 + test_fr_limmed 0x0002,0x0002,fr12 + test_fr_limmed 0xffff,0xffff,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 0x3c,2,0xc,msr1 ; msr1.sie is set + test_spr_bits 2,1,1,msr1 ; msr1.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_fr_iimmed 0xdead,0xbeef,fr12 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmaddhus fr10,fr11,fr12,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xbeef,0x0000,fr10 + set_fr_iimmed 0x0000,0xdead,fr11 + cmaddhus fr10,fr11,fr12,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + cmaddhus fr10,fr11,fr12,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmaddhus fr10,fr11,fr12,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmaddhus fr10,fr11,fr12,cc4,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xfffe,0xfffe,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + cmaddhus fr10,fr11,fr12,cc4,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0002,0x0001,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + cmaddhus fr10,fr11,fr12,cc4,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xbeef,0xdead,fr13 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + cmaddhus.p fr10,fr10,fr12,cc4,0 + cmaddhus fr11,fr11,fr13,cc4,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_fr_limmed 0xbeef,0xdead,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xdead,0xbeef,fr12 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmaddhus fr10,fr11,fr12,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xbeef,0x0000,fr10 + set_fr_iimmed 0x0000,0xdead,fr11 + cmaddhus fr10,fr11,fr12,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + cmaddhus fr10,fr11,fr12,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmaddhus fr10,fr11,fr12,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmaddhus fr10,fr11,fr12,cc5,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xfffe,0xfffe,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + cmaddhus fr10,fr11,fr12,cc5,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0002,0x0001,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + cmaddhus fr10,fr11,fr12,cc5,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xbeef,0xdead,fr13 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + cmaddhus.p fr10,fr10,fr12,cc5,1 + cmaddhus fr11,fr11,fr13,cc5,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_fr_limmed 0xbeef,0xdead,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xdead,0xbeef,fr12 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmaddhus fr10,fr11,fr12,cc2,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xbeef,0x0000,fr10 + set_fr_iimmed 0x0000,0xdead,fr11 + cmaddhus fr10,fr11,fr12,cc2,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + cmaddhus fr10,fr11,fr12,cc2,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmaddhus fr10,fr11,fr12,cc2,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmaddhus fr10,fr11,fr12,cc6,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xfffe,0xfffe,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + cmaddhus fr10,fr11,fr12,cc6,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0002,0x0001,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + cmaddhus fr10,fr11,fr12,cc6,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xbeef,0xdead,fr13 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + cmaddhus.p fr10,fr10,fr12,cc6,0 + cmaddhus fr11,fr11,fr13,cc6,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_fr_limmed 0xbeef,0xdead,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xdead,0xbeef,fr12 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmaddhus fr10,fr11,fr12,cc3,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xbeef,0x0000,fr10 + set_fr_iimmed 0x0000,0xdead,fr11 + cmaddhus fr10,fr11,fr12,cc3,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + cmaddhus fr10,fr11,fr12,cc3,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmaddhus fr10,fr11,fr12,cc3,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmaddhus fr10,fr11,fr12,cc7,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xfffe,0xfffe,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + cmaddhus fr10,fr11,fr12,cc7,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0002,0x0001,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + cmaddhus fr10,fr11,fr12,cc7,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xbeef,0xdead,fr13 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + cmaddhus.p fr10,fr10,fr12,cc7,0 + cmaddhus fr11,fr11,fr13,cc7,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_fr_limmed 0xbeef,0xdead,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + pass diff --git a/sim/testsuite/sim/frv/cmand.cgs b/sim/testsuite/sim/frv/cmand.cgs new file mode 100644 index 0000000..7ed9e4d --- /dev/null +++ b/sim/testsuite/sim/frv/cmand.cgs @@ -0,0 +1,89 @@ +# frv testcase for cmand $FRinti,$FRintj,$FRintk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cmand +cmand: + set_spr_immed 0x1b1b,cccr + + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + set_fr_iimmed 0x5555,0x5555,fr8 + cmand fr7,fr8,fr8,cc0,1 + test_fr_iimmed 0,fr8 + + set_fr_iimmed 0xffff,0x0000,fr8 + cmand fr7,fr8,fr8,cc0,1 + test_fr_iimmed 0xaaaa0000,fr8 + + set_fr_iimmed 0x0000,0xffff,fr8 + cmand fr7,fr8,fr8,cc4,1 + test_fr_iimmed 0x0000aaaa,fr8 + + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + set_fr_iimmed 0x5555,0x5555,fr8 + cmand fr7,fr8,fr8,cc1,0 + test_fr_iimmed 0,fr8 + + set_fr_iimmed 0xffff,0x0000,fr8 + cmand fr7,fr8,fr8,cc1,0 + test_fr_iimmed 0xaaaa0000,fr8 + + set_fr_iimmed 0x0000,0xffff,fr8 + cmand fr7,fr8,fr8,cc5,0 + test_fr_iimmed 0x0000aaaa,fr8 + + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + set_fr_iimmed 0x5555,0x5555,fr8 + cmand fr7,fr8,fr8,cc0,0 + test_fr_iimmed 0x55555555,fr8 + + set_fr_iimmed 0xffff,0x0000,fr8 + cmand fr7,fr8,fr8,cc0,0 + test_fr_iimmed 0xffff0000,fr8 + + set_fr_iimmed 0x0000,0xffff,fr8 + cmand fr7,fr8,fr8,cc4,0 + test_fr_iimmed 0x0000ffff,fr8 + + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + set_fr_iimmed 0x5555,0x5555,fr8 + cmand fr7,fr8,fr8,cc1,1 + test_fr_iimmed 0x55555555,fr8 + + set_fr_iimmed 0xffff,0x0000,fr8 + cmand fr7,fr8,fr8,cc1,1 + test_fr_iimmed 0xffff0000,fr8 + + set_fr_iimmed 0x0000,0xffff,fr8 + cmand fr7,fr8,fr8,cc5,1 + test_fr_iimmed 0x0000ffff,fr8 + + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + set_fr_iimmed 0x5555,0x5555,fr8 + cmand fr7,fr8,fr8,cc2,0 + test_fr_iimmed 0x55555555,fr8 + + set_fr_iimmed 0xffff,0x0000,fr8 + cmand fr7,fr8,fr8,cc2,1 + test_fr_iimmed 0xffff0000,fr8 + + set_fr_iimmed 0x0000,0xffff,fr8 + cmand fr7,fr8,fr8,cc6,0 + test_fr_iimmed 0x0000ffff,fr8 + + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + set_fr_iimmed 0x5555,0x5555,fr8 + cmand fr7,fr8,fr8,cc3,1 + test_fr_iimmed 0x55555555,fr8 + + set_fr_iimmed 0xffff,0x0000,fr8 + cmand fr7,fr8,fr8,cc3,0 + test_fr_iimmed 0xffff0000,fr8 + + set_fr_iimmed 0x0000,0xffff,fr8 + cmand fr7,fr8,fr8,cc7,1 + test_fr_iimmed 0x0000ffff,fr8 + pass diff --git a/sim/testsuite/sim/frv/cmbtoh.cgs b/sim/testsuite/sim/frv/cmbtoh.cgs new file mode 100644 index 0000000..5e7c91a --- /dev/null +++ b/sim/testsuite/sim/frv/cmbtoh.cgs @@ -0,0 +1,74 @@ +# frv testcase for cmbtoh $FRj,$FRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cmbtoh +cmbtoh: + set_spr_immed 0x1b1b,cccr + + set_fr_iimmed 0xdead,0xbeef,fr10 + cmbtoh fr10,fr12,cc0,1 + test_fr_limmed 0x00de,0x00ad,fr12 + test_fr_limmed 0x00be,0x00ef,fr13 + + set_fr_iimmed 0x1234,0x5678,fr10 + cmbtoh fr10,fr12,cc4,1 + test_fr_limmed 0x0012,0x0034,fr12 + test_fr_limmed 0x0056,0x0078,fr13 + + set_fr_iimmed 0xdead,0xbeef,fr10 + cmbtoh fr10,fr12,cc1,0 + test_fr_limmed 0x00de,0x00ad,fr12 + test_fr_limmed 0x00be,0x00ef,fr13 + + set_fr_iimmed 0x1234,0x5678,fr10 + cmbtoh fr10,fr12,cc5,0 + test_fr_limmed 0x0012,0x0034,fr12 + test_fr_limmed 0x0056,0x0078,fr13 + + set_fr_iimmed 0x1111,0x1111,fr12 + set_fr_iimmed 0x2222,0x2222,fr13 + set_fr_iimmed 0xdead,0xbeef,fr10 + cmbtoh fr10,fr12,cc0,0 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + + set_fr_iimmed 0x1234,0x5678,fr10 + cmbtoh fr10,fr12,cc4,0 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + + set_fr_iimmed 0xdead,0xbeef,fr10 + cmbtoh fr10,fr12,cc1,1 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + + set_fr_iimmed 0x1234,0x5678,fr10 + cmbtoh fr10,fr12,cc5,1 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + + set_fr_iimmed 0xdead,0xbeef,fr10 + cmbtoh fr10,fr12,cc2,1 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + + set_fr_iimmed 0x1234,0x5678,fr10 + cmbtoh fr10,fr12,cc6,0 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + + set_fr_iimmed 0xdead,0xbeef,fr10 + cmbtoh fr10,fr12,cc3,1 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + + set_fr_iimmed 0x1234,0x5678,fr10 + cmbtoh fr10,fr12,cc7,0 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + + pass diff --git a/sim/testsuite/sim/frv/cmbtohe.cgs b/sim/testsuite/sim/frv/cmbtohe.cgs new file mode 100644 index 0000000..eb6b514 --- /dev/null +++ b/sim/testsuite/sim/frv/cmbtohe.cgs @@ -0,0 +1,100 @@ +# frv testcase for cmbtohe $FRj,$FRk +# mach: frv + + .include "testutils.inc" + + start + + .global cmbtohe +cmbtohe: + set_spr_immed 0x1b1b,cccr + + set_fr_iimmed 0xdead,0xbeef,fr10 + cmbtohe fr10,fr12,cc0,1 + test_fr_limmed 0x00de,0x00de,fr12 + test_fr_limmed 0x00ad,0x00ad,fr13 + test_fr_limmed 0x00be,0x00be,fr14 + test_fr_limmed 0x00ef,0x00ef,fr15 + + set_fr_iimmed 0x1234,0x5678,fr10 + cmbtohe fr10,fr12,cc4,1 + test_fr_limmed 0x0012,0x0012,fr12 + test_fr_limmed 0x0034,0x0034,fr13 + test_fr_limmed 0x0056,0x0056,fr14 + test_fr_limmed 0x0078,0x0078,fr15 + + set_fr_iimmed 0xdead,0xbeef,fr10 + cmbtohe fr10,fr12,cc1,0 + test_fr_limmed 0x00de,0x00de,fr12 + test_fr_limmed 0x00ad,0x00ad,fr13 + test_fr_limmed 0x00be,0x00be,fr14 + test_fr_limmed 0x00ef,0x00ef,fr15 + + set_fr_iimmed 0x1234,0x5678,fr10 + cmbtohe fr10,fr12,cc5,0 + test_fr_limmed 0x0012,0x0012,fr12 + test_fr_limmed 0x0034,0x0034,fr13 + test_fr_limmed 0x0056,0x0056,fr14 + test_fr_limmed 0x0078,0x0078,fr15 + + set_fr_iimmed 0x1111,0x1111,fr12 + set_fr_iimmed 0x2222,0x2222,fr13 + set_fr_iimmed 0x3333,0x3333,fr14 + set_fr_iimmed 0x4444,0x4444,fr15 + set_fr_iimmed 0xdead,0xbeef,fr10 + cmbtohe fr10,fr12,cc0,0 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + test_fr_limmed 0x3333,0x3333,fr14 + test_fr_limmed 0x4444,0x4444,fr15 + + set_fr_iimmed 0x1234,0x5678,fr10 + cmbtohe fr10,fr12,cc4,0 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + test_fr_limmed 0x3333,0x3333,fr14 + test_fr_limmed 0x4444,0x4444,fr15 + + set_fr_iimmed 0xdead,0xbeef,fr10 + cmbtohe fr10,fr12,cc1,1 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + test_fr_limmed 0x3333,0x3333,fr14 + test_fr_limmed 0x4444,0x4444,fr15 + + set_fr_iimmed 0x1234,0x5678,fr10 + cmbtohe fr10,fr12,cc5,1 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + test_fr_limmed 0x3333,0x3333,fr14 + test_fr_limmed 0x4444,0x4444,fr15 + + set_fr_iimmed 0xdead,0xbeef,fr10 + cmbtohe fr10,fr12,cc2,1 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + test_fr_limmed 0x3333,0x3333,fr14 + test_fr_limmed 0x4444,0x4444,fr15 + + set_fr_iimmed 0x1234,0x5678,fr10 + cmbtohe fr10,fr12,cc6,0 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + test_fr_limmed 0x3333,0x3333,fr14 + test_fr_limmed 0x4444,0x4444,fr15 + + set_fr_iimmed 0xdead,0xbeef,fr10 + cmbtohe fr10,fr12,cc3,0 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + test_fr_limmed 0x3333,0x3333,fr14 + test_fr_limmed 0x4444,0x4444,fr15 + + set_fr_iimmed 0x1234,0x5678,fr10 + cmbtohe fr10,fr12,cc7,1 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + test_fr_limmed 0x3333,0x3333,fr14 + test_fr_limmed 0x4444,0x4444,fr15 + + pass diff --git a/sim/testsuite/sim/frv/cmcpxis.cgs b/sim/testsuite/sim/frv/cmcpxis.cgs new file mode 100644 index 0000000..ded0300 --- /dev/null +++ b/sim/testsuite/sim/frv/cmcpxis.cgs @@ -0,0 +1,971 @@ +# frv testcase for cmcpxis $GRi,$GRj,$ACCk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cmcpxis +cmcpxis: + set_spr_immed 0x1b1b,cccr + + ; Positive operands + set_fr_iimmed 2,4,fr7 ; multiply small numbers + set_fr_iimmed 5,3,fr8 + cmcpxis fr7,fr8,acc0,cc0,1 + test_accg_immed 0x00,accg0 + test_acc_immed 26,acc0 + + set_fr_iimmed 3,1,fr7 ; multiply by 0 + set_fr_iimmed 0,2,fr8 + cmcpxis fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,1,fr8 + cmcpxis fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_immed 3,acc0 + + set_fr_iimmed 0x3ff8,2,fr7 ; 15 bit result + set_fr_iimmed 0x0007,2,fr8 + cmcpxis fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_limmed 0,0x7ffe,acc0 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 0x2000,2,fr8 + cmcpxis fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0xc000,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxis fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0x0001,acc0 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 1,0xfffd,fr8 + cmcpxis fr7,fr8,acc0,cc0,1 + test_accg_immed 0xff,accg0 + test_acc_immed -9,acc0 + + set_fr_iimmed 0xfffe,2,fr7 ; multiply by 1 + set_fr_iimmed 0xfffe,1,fr8 + cmcpxis fr7,fr8,acc0,cc0,1 + test_accg_immed 0xff,accg0 + test_acc_immed -6,acc0 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 0xfffe,1,fr8 + cmcpxis fr7,fr8,acc0,cc0,1 + test_accg_immed 0xff,accg0 + test_acc_immed -2,acc0 + + set_fr_iimmed 0x2001,0xffff,fr7 ; 15 bit result + set_fr_iimmed 0xffff,0xfffe,fr8 + cmcpxis fr7,fr8,acc0,cc4,1 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xbfff,acc0 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0x0003,0xfffe,fr8 + cmcpxis fr7,fr8,acc0,cc4,1 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0x7ffa,acc0 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max negative result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxis fr7,fr8,acc0,cc4,1 + test_accg_immed 0xff,accg0 + test_acc_limmed 0x8001,0x0000,acc0 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxis fr7,fr8,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_limmed 0x8000,0x0000,acc0 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffc,fr7 ; multiply small numbers + set_fr_iimmed 0xfffb,0xfffd,fr8 + cmcpxis fr7,fr8,acc0,cc4,1 + test_accg_immed 0x00,accg0 + test_acc_immed 26,acc0 + + set_fr_iimmed 0xffff,0xffff,fr7 ; multiply by -1 + set_fr_iimmed 0xffff,0xfffe,fr8 + cmcpxis fr7,fr8,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_immed 3,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; almost max positive result + set_fr_iimmed 0x8001,0x7fff,fr8 + cmcpxis fr7,fr8,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + + set_fr_iimmed 0x8000,0x0000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxis fr7,fr8,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_immed 0x40000000,acc0 + + ; Positive operands + set_fr_iimmed 2,4,fr7 ; multiply small numbers + set_fr_iimmed 5,3,fr8 + cmcpxis fr7,fr8,acc0,cc1,0 + test_accg_immed 0x00,accg0 + test_acc_immed 26,acc0 + + set_fr_iimmed 3,1,fr7 ; multiply by 0 + set_fr_iimmed 0,2,fr8 + cmcpxis fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,1,fr8 + cmcpxis fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_immed 3,acc0 + + set_fr_iimmed 0x3ff8,2,fr7 ; 15 bit result + set_fr_iimmed 0x0007,2,fr8 + cmcpxis fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_limmed 0,0x7ffe,acc0 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 0x2000,2,fr8 + cmcpxis fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0xc000,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxis fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0x0001,acc0 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 1,0xfffd,fr8 + cmcpxis fr7,fr8,acc0,cc1,0 + test_accg_immed 0xff,accg0 + test_acc_immed -9,acc0 + + set_fr_iimmed 0xfffe,2,fr7 ; multiply by 1 + set_fr_iimmed 0xfffe,1,fr8 + cmcpxis fr7,fr8,acc0,cc1,0 + test_accg_immed 0xff,accg0 + test_acc_immed -6,acc0 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 0xfffe,1,fr8 + cmcpxis fr7,fr8,acc0,cc1,0 + test_accg_immed 0xff,accg0 + test_acc_immed -2,acc0 + + set_fr_iimmed 0x2001,0xffff,fr7 ; 15 bit result + set_fr_iimmed 0xffff,0xfffe,fr8 + cmcpxis fr7,fr8,acc0,cc5,0 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xbfff,acc0 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0x0003,0xfffe,fr8 + cmcpxis fr7,fr8,acc0,cc5,0 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0x7ffa,acc0 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max negative result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxis fr7,fr8,acc0,cc5,0 + test_accg_immed 0xff,accg0 + test_acc_limmed 0x8001,0x0000,acc0 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxis fr7,fr8,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_limmed 0x8000,0x0000,acc0 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffc,fr7 ; multiply small numbers + set_fr_iimmed 0xfffb,0xfffd,fr8 + cmcpxis fr7,fr8,acc0,cc5,0 + test_accg_immed 0x00,accg0 + test_acc_immed 26,acc0 + + set_fr_iimmed 0xffff,0xffff,fr7 ; multiply by -1 + set_fr_iimmed 0xffff,0xfffe,fr8 + cmcpxis fr7,fr8,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_immed 3,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; almost max positive result + set_fr_iimmed 0x8001,0x7fff,fr8 + cmcpxis fr7,fr8,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + + set_fr_iimmed 0x8000,0x0000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxis fr7,fr8,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_immed 0x40000000,acc0 + + ; Positive operands + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_fr_iimmed 2,4,fr7 ; multiply small numbers + set_fr_iimmed 5,3,fr8 + cmcpxis fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 3,1,fr7 ; multiply by 0 + set_fr_iimmed 0,2,fr8 + cmcpxis fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,1,fr8 + cmcpxis fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 0x0007,2,fr8 + cmcpxis fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 0x2000,2,fr8 + cmcpxis fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxis fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 1,0xfffd,fr8 + cmcpxis fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,2,fr7 ; multiply by 1 + set_fr_iimmed 0xfffe,1,fr8 + cmcpxis fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 0xfffe,1,fr8 + cmcpxis fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfff9,0xfffe,fr8 + cmcpxis fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0x0003,0xfffe,fr8 + cmcpxis fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxis fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxis fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffc,fr7 ; multiply small numbers + set_fr_iimmed 0xfffb,0xfffd,fr8 + cmcpxis fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xffff,0xffff,fr7 ; multiply by -1 + set_fr_iimmed 0xffff,0xfffe,fr8 + cmcpxis fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; almost max positive result + set_fr_iimmed 0x8001,0x7fff,fr8 + cmcpxis fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x0000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxis fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + ; Positive operands + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_fr_iimmed 2,4,fr7 ; multiply small numbers + set_fr_iimmed 5,3,fr8 + cmcpxis fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 3,1,fr7 ; multiply by 0 + set_fr_iimmed 0,2,fr8 + cmcpxis fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,1,fr8 + cmcpxis fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 0x0007,2,fr8 + cmcpxis fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 0x2000,2,fr8 + cmcpxis fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxis fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 1,0xfffd,fr8 + cmcpxis fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,2,fr7 ; multiply by 1 + set_fr_iimmed 0xfffe,1,fr8 + cmcpxis fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 0xfffe,1,fr8 + cmcpxis fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfff9,0xfffe,fr8 + cmcpxis fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0x0003,0xfffe,fr8 + cmcpxis fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxis fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxis fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffc,fr7 ; multiply small numbers + set_fr_iimmed 0xfffb,0xfffd,fr8 + cmcpxis fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xffff,0xffff,fr7 ; multiply by -1 + set_fr_iimmed 0xffff,0xfffe,fr8 + cmcpxis fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; almost max positive result + set_fr_iimmed 0x8001,0x7fff,fr8 + cmcpxis fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x0000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxis fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + ; Positive operands + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_fr_iimmed 2,4,fr7 ; multiply small numbers + set_fr_iimmed 5,3,fr8 + cmcpxis fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 3,1,fr7 ; multiply by 0 + set_fr_iimmed 0,2,fr8 + cmcpxis fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,1,fr8 + cmcpxis fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 0x0007,2,fr8 + cmcpxis fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 0x2000,2,fr8 + cmcpxis fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxis fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 1,0xfffd,fr8 + cmcpxis fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,2,fr7 ; multiply by 1 + set_fr_iimmed 0xfffe,1,fr8 + cmcpxis fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 0xfffe,1,fr8 + cmcpxis fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfff9,0xfffe,fr8 + cmcpxis fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0x0003,0xfffe,fr8 + cmcpxis fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxis fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxis fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffc,fr7 ; multiply small numbers + set_fr_iimmed 0xfffb,0xfffd,fr8 + cmcpxis fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xffff,0xffff,fr7 ; multiply by -1 + set_fr_iimmed 0xffff,0xfffe,fr8 + cmcpxis fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; almost max positive result + set_fr_iimmed 0x8001,0x7fff,fr8 + cmcpxis fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x0000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxis fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + ; Positive operands + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_fr_iimmed 2,4,fr7 ; multiply small numbers + set_fr_iimmed 5,3,fr8 + cmcpxis fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 3,1,fr7 ; multiply by 0 + set_fr_iimmed 0,2,fr8 + cmcpxis fr7,fr8,acc0,cc2,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,1,fr8 + cmcpxis fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 0x0007,2,fr8 + cmcpxis fr7,fr8,acc0,cc2,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 0x2000,2,fr8 + cmcpxis fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxis fr7,fr8,acc0,cc2,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 1,0xfffd,fr8 + cmcpxis fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,2,fr7 ; multiply by 1 + set_fr_iimmed 0xfffe,1,fr8 + cmcpxis fr7,fr8,acc0,cc2,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 0xfffe,1,fr8 + cmcpxis fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfff9,0xfffe,fr8 + cmcpxis fr7,fr8,acc0,cc6,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0x0003,0xfffe,fr8 + cmcpxis fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxis fr7,fr8,acc0,cc6,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxis fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffc,fr7 ; multiply small numbers + set_fr_iimmed 0xfffb,0xfffd,fr8 + cmcpxis fr7,fr8,acc0,cc6,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xffff,0xffff,fr7 ; multiply by -1 + set_fr_iimmed 0xffff,0xfffe,fr8 + cmcpxis fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; almost max positive result + set_fr_iimmed 0x8001,0x7fff,fr8 + cmcpxis fr7,fr8,acc0,cc6,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x0000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxis fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + ; Positive operands + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_fr_iimmed 2,4,fr7 ; multiply small numbers + set_fr_iimmed 5,3,fr8 + cmcpxis fr7,fr8,acc0,cc2,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 3,1,fr7 ; multiply by 0 + set_fr_iimmed 0,2,fr8 + cmcpxis fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,1,fr8 + cmcpxis fr7,fr8,acc0,cc2,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 0x0007,2,fr8 + cmcpxis fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 0x2000,2,fr8 + cmcpxis fr7,fr8,acc0,cc2,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxis fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 1,0xfffd,fr8 + cmcpxis fr7,fr8,acc0,cc2,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,2,fr7 ; multiply by 1 + set_fr_iimmed 0xfffe,1,fr8 + cmcpxis fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 0xfffe,1,fr8 + cmcpxis fr7,fr8,acc0,cc6,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfff9,0xfffe,fr8 + cmcpxis fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0x0003,0xfffe,fr8 + cmcpxis fr7,fr8,acc0,cc6,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxis fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxis fr7,fr8,acc0,cc6,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffc,fr7 ; multiply small numbers + set_fr_iimmed 0xfffb,0xfffd,fr8 + cmcpxis fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xffff,0xffff,fr7 ; multiply by -1 + set_fr_iimmed 0xffff,0xfffe,fr8 + cmcpxis fr7,fr8,acc0,cc6,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; almost max positive result + set_fr_iimmed 0x8001,0x7fff,fr8 + cmcpxis fr7,fr8,acc0,cc6,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x0000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxis fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 +; + ; Positive operands + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_fr_iimmed 2,4,fr7 ; multiply small numbers + set_fr_iimmed 5,3,fr8 + cmcpxis fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 3,1,fr7 ; multiply by 0 + set_fr_iimmed 0,2,fr8 + cmcpxis fr7,fr8,acc0,cc3,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,1,fr8 + cmcpxis fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 0x0007,2,fr8 + cmcpxis fr7,fr8,acc0,cc3,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 0x2000,2,fr8 + cmcpxis fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxis fr7,fr8,acc0,cc3,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 1,0xfffd,fr8 + cmcpxis fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,2,fr7 ; multiply by 1 + set_fr_iimmed 0xfffe,1,fr8 + cmcpxis fr7,fr8,acc0,cc3,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 0xfffe,1,fr8 + cmcpxis fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfff9,0xfffe,fr8 + cmcpxis fr7,fr8,acc0,cc6,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0x0003,0xfffe,fr8 + cmcpxis fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxis fr7,fr8,acc0,cc6,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxis fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffc,fr7 ; multiply small numbers + set_fr_iimmed 0xfffb,0xfffd,fr8 + cmcpxis fr7,fr8,acc0,cc6,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xffff,0xffff,fr7 ; multiply by -1 + set_fr_iimmed 0xffff,0xfffe,fr8 + cmcpxis fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; almost max positive result + set_fr_iimmed 0x8001,0x7fff,fr8 + cmcpxis fr7,fr8,acc0,cc6,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x0000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxis fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + ; Positive operands + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_fr_iimmed 2,4,fr7 ; multiply small numbers + set_fr_iimmed 5,3,fr8 + cmcpxis fr7,fr8,acc0,cc3,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 3,1,fr7 ; multiply by 0 + set_fr_iimmed 0,2,fr8 + cmcpxis fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,1,fr8 + cmcpxis fr7,fr8,acc0,cc3,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 0x0007,2,fr8 + cmcpxis fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 0x2000,2,fr8 + cmcpxis fr7,fr8,acc0,cc3,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxis fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 1,0xfffd,fr8 + cmcpxis fr7,fr8,acc0,cc3,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,2,fr7 ; multiply by 1 + set_fr_iimmed 0xfffe,1,fr8 + cmcpxis fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 0xfffe,1,fr8 + cmcpxis fr7,fr8,acc0,cc7,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfff9,0xfffe,fr8 + cmcpxis fr7,fr8,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0x0003,0xfffe,fr8 + cmcpxis fr7,fr8,acc0,cc7,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxis fr7,fr8,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxis fr7,fr8,acc0,cc7,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffc,fr7 ; multiply small numbers + set_fr_iimmed 0xfffb,0xfffd,fr8 + cmcpxis fr7,fr8,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xffff,0xffff,fr7 ; multiply by -1 + set_fr_iimmed 0xffff,0xfffe,fr8 + cmcpxis fr7,fr8,acc0,cc7,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; almost max positive result + set_fr_iimmed 0x8001,0x7fff,fr8 + cmcpxis fr7,fr8,acc0,cc7,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x0000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxis fr7,fr8,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + pass diff --git a/sim/testsuite/sim/frv/cmcpxiu.cgs b/sim/testsuite/sim/frv/cmcpxiu.cgs new file mode 100644 index 0000000..90a92bc --- /dev/null +++ b/sim/testsuite/sim/frv/cmcpxiu.cgs @@ -0,0 +1,508 @@ +# frv testcase for cmcpxiu $GRi,$GRj,$GRk,$CCi,$cond +# mach: frv fr500 fr400 + + .include "testutils.inc" + + start + + .global cmcpxiu +cmcpxiu: + set_spr_immed 0x1b1b,cccr + + set_fr_iimmed 4,2,fr7 ; multiply small numbers + set_fr_iimmed 3,5,fr8 + cmcpxiu fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_immed 26,acc0 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 1,3,fr8 + cmcpxiu fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_immed 5,acc0 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 0,2,fr8 + cmcpxiu fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + + set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result + set_fr_iimmed 0x0001,2,fr8 + cmcpxiu fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x7fff,acc0 + + set_fr_iimmed 0x4000,1,fr7 ; 16 bit result + set_fr_iimmed 0x0001,2,fr8 + cmcpxiu fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8001,acc0 + + set_fr_iimmed 0x4000,1,fr7 ; 17 bit result + set_fr_iimmed 0x0001,4,fr8 + cmcpxiu fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_immed 0x00010001,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxiu fr7,fr8,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x0000,0x8000,fr8 + cmcpxiu fr7,fr8,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_limmed 0x4000,0x0000,acc0 + + set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_limmed 0xfffe,0x0001,acc0 + + set_fr_iimmed 0xfffe,0xffff,fr7 ; almost max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc4,1 + test_accg_immed 1,accg0 + test_acc_immed 0xfffb0003,acc0 + + set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc4,1 + test_accg_immed 1,accg0 + test_acc_immed 0xfffc0002,acc0 + + set_fr_iimmed 4,2,fr7 ; multiply small numbers + set_fr_iimmed 3,5,fr8 + cmcpxiu fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_immed 26,acc0 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 1,3,fr8 + cmcpxiu fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_immed 5,acc0 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 0,2,fr8 + cmcpxiu fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + + set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result + set_fr_iimmed 0x0001,2,fr8 + cmcpxiu fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x7fff,acc0 + + set_fr_iimmed 0x4000,1,fr7 ; 16 bit result + set_fr_iimmed 0x0001,2,fr8 + cmcpxiu fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8001,acc0 + + set_fr_iimmed 0x4000,1,fr7 ; 17 bit result + set_fr_iimmed 0x0001,4,fr8 + cmcpxiu fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_immed 0x00010001,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxiu fr7,fr8,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x0000,0x8000,fr8 + cmcpxiu fr7,fr8,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_limmed 0x4000,0x0000,acc0 + + set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_limmed 0xfffe,0x0001,acc0 + + set_fr_iimmed 0xfffe,0xffff,fr7 ; almost max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc5,0 + test_accg_immed 1,accg0 + test_acc_immed 0xfffb0003,acc0 + + set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc5,0 + test_accg_immed 1,accg0 + test_acc_immed 0xfffc0002,acc0 + + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_fr_iimmed 4,2,fr7 ; multiply small numbers + set_fr_iimmed 3,5,fr8 + cmcpxiu fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 1,3,fr8 + cmcpxiu fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 0,2,fr8 + cmcpxiu fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result + set_fr_iimmed 0x0001,2,fr8 + cmcpxiu fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,1,fr7 ; 16 bit result + set_fr_iimmed 0x0001,4,fr8 + cmcpxiu fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,1,fr7 ; 17 bit result + set_fr_iimmed 0x0001,4,fr8 + cmcpxiu fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxiu fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x0000,0x8000,fr8 + cmcpxiu fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0001,fr7 ; saturation + set_fr_iimmed 0x0001,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x0000,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_fr_iimmed 4,2,fr7 ; multiply small numbers + set_fr_iimmed 3,5,fr8 + cmcpxiu fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 1,3,fr8 + cmcpxiu fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 0,2,fr8 + cmcpxiu fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result + set_fr_iimmed 0x0001,2,fr8 + cmcpxiu fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,1,fr7 ; 16 bit result + set_fr_iimmed 0x0001,4,fr8 + cmcpxiu fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,1,fr7 ; 17 bit result + set_fr_iimmed 0x0001,4,fr8 + cmcpxiu fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxiu fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x0000,0x8000,fr8 + cmcpxiu fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0001,fr7 ; saturation + set_fr_iimmed 0x0001,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x0000,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_fr_iimmed 4,2,fr7 ; multiply small numbers + set_fr_iimmed 3,5,fr8 + cmcpxiu fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 1,3,fr8 + cmcpxiu fr7,fr8,acc0,cc2,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 0,2,fr8 + cmcpxiu fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result + set_fr_iimmed 0x0001,2,fr8 + cmcpxiu fr7,fr8,acc0,cc2,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,1,fr7 ; 16 bit result + set_fr_iimmed 0x0001,4,fr8 + cmcpxiu fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,1,fr7 ; 17 bit result + set_fr_iimmed 0x0001,4,fr8 + cmcpxiu fr7,fr8,acc0,cc2,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxiu fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x0000,0x8000,fr8 + cmcpxiu fr7,fr8,acc0,cc6,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0001,fr7 ; saturation + set_fr_iimmed 0x0001,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc6,0 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x0000,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc6,1 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc6,0 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_fr_iimmed 4,2,fr7 ; multiply small numbers + set_fr_iimmed 3,5,fr8 + cmcpxiu fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 1,3,fr8 + cmcpxiu fr7,fr8,acc0,cc3,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 0,2,fr8 + cmcpxiu fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result + set_fr_iimmed 0x0001,2,fr8 + cmcpxiu fr7,fr8,acc0,cc3,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,1,fr7 ; 16 bit result + set_fr_iimmed 0x0001,4,fr8 + cmcpxiu fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,1,fr7 ; 17 bit result + set_fr_iimmed 0x0001,4,fr8 + cmcpxiu fr7,fr8,acc0,cc3,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxiu fr7,fr8,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x0000,0x8000,fr8 + cmcpxiu fr7,fr8,acc0,cc7,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0001,fr7 ; saturation + set_fr_iimmed 0x0001,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc7,0 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x0000,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc7,1 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc7,0 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + pass diff --git a/sim/testsuite/sim/frv/cmcpxrs.cgs b/sim/testsuite/sim/frv/cmcpxrs.cgs new file mode 100644 index 0000000..ea1242c --- /dev/null +++ b/sim/testsuite/sim/frv/cmcpxrs.cgs @@ -0,0 +1,649 @@ +# frv testcase for cmcpxrs $GRi,$GRj,$ACCk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cmcpxrs +cmcpxrs: + set_spr_immed 0x1b1b,cccr + + ; Positive operands + set_fr_iimmed 2,4,fr7 ; multiply small numbers + set_fr_iimmed 3,5,fr8 + cmcpxrs fr7,fr8,acc0,cc0,1 + test_accg_immed 0xff,accg0 + test_acc_immed -14,acc0 + + set_fr_iimmed 3,1,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmcpxrs fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,1,fr8 + cmcpxrs fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_immed 1,acc0 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x0007,fr8 + cmcpxrs fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_limmed 0,0x7ff0,acc0 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x2000,fr8 + cmcpxrs fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x4000,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxrs fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0x0001,acc0 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,1,fr8 + cmcpxrs fr7,fr8,acc0,cc0,1 + test_accg_immed 0xff,accg0 + test_acc_immed -3,acc0 + + set_fr_iimmed 0xfffe,2,fr7 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr8 + cmcpxrs fr7,fr8,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_immed 2,acc0 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 1,0xfffe,fr8 + cmcpxrs fr7,fr8,acc0,cc4,1 + test_accg_immed 0xff,accg0 + test_acc_immed -2,acc0 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfffe,0xfff9,fr8 + cmcpxrs fr7,fr8,acc0,cc4,1 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xbff0,acc0 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0xfffe,0x0003,fr8 + cmcpxrs fr7,fr8,acc0,cc4,1 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0x8006,acc0 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxrs fr7,fr8,acc0,cc4,1 + test_accg_immed 0xff,accg0 + test_acc_limmed 0x8000,0x8000,acc0 + + set_fr_iimmed 0x8000,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxrs fr7,fr8,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_limmed 0x7fff,0x8000,acc0 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffc,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffb,fr8 + cmcpxrs fr7,fr8,acc0,cc4,1 + test_accg_immed 0xff,accg0 + test_acc_immed -14,acc0 + + set_fr_iimmed 0xffff,0xffff,fr7 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr8 + cmcpxrs fr7,fr8,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_immed 1,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; almost max positive result + set_fr_iimmed 0x7fff,0x8001,fr8 + cmcpxrs fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + + set_fr_iimmed 0x8000,0x0000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxrs fr7,fr8,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_immed 0x40000000,acc0 + + set_fr_iimmed 2,4,fr7 ; multiply small numbers + set_fr_iimmed 3,5,fr8 + cmcpxrs fr7,fr8,acc0,cc1,0 + test_accg_immed 0xff,accg0 + test_acc_immed -14,acc0 + + set_fr_iimmed 3,1,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmcpxrs fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,1,fr8 + cmcpxrs fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_immed 1,acc0 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x0007,fr8 + cmcpxrs fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_limmed 0,0x7ff0,acc0 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x2000,fr8 + cmcpxrs fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x4000,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxrs fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0x0001,acc0 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,1,fr8 + cmcpxrs fr7,fr8,acc0,cc1,0 + test_accg_immed 0xff,accg0 + test_acc_immed -3,acc0 + + set_fr_iimmed 0xfffe,2,fr7 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr8 + cmcpxrs fr7,fr8,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_immed 2,acc0 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 1,0xfffe,fr8 + cmcpxrs fr7,fr8,acc0,cc5,0 + test_accg_immed 0xff,accg0 + test_acc_immed -2,acc0 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfffe,0xfff9,fr8 + cmcpxrs fr7,fr8,acc0,cc5,0 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xbff0,acc0 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0xfffe,0x0003,fr8 + cmcpxrs fr7,fr8,acc0,cc5,0 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0x8006,acc0 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxrs fr7,fr8,acc0,cc5,0 + test_accg_immed 0xff,accg0 + test_acc_limmed 0x8000,0x8000,acc0 + + set_fr_iimmed 0x8000,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxrs fr7,fr8,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_limmed 0x7fff,0x8000,acc0 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffc,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffb,fr8 + cmcpxrs fr7,fr8,acc0,cc5,0 + test_accg_immed 0xff,accg0 + test_acc_immed -14,acc0 + + set_fr_iimmed 0xffff,0xffff,fr7 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr8 + cmcpxrs fr7,fr8,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_immed 1,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; almost max positive result + set_fr_iimmed 0x7fff,0x8001,fr8 + cmcpxrs fr7,fr8,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + + set_fr_iimmed 0x8000,0x0000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxrs fr7,fr8,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_immed 0x40000000,acc0 + + ; Positive operands + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_fr_iimmed 2,4,fr7 ; multiply small numbers + set_fr_iimmed 3,5,fr8 + cmcpxrs fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 3,1,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmcpxrs fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,1,fr8 + cmcpxrs fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x0007,fr8 + cmcpxrs fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x2000,fr8 + cmcpxrs fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxrs fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,1,fr8 + cmcpxrs fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,2,fr7 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr8 + cmcpxrs fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 1,0xfffe,fr8 + cmcpxrs fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfffe,0xfff9,fr8 + cmcpxrs fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0xfffe,0x0003,fr8 + cmcpxrs fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxrs fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxrs fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffc,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffb,fr8 + cmcpxrs fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xffff,0xffff,fr7 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr8 + cmcpxrs fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; almost max positive result + set_fr_iimmed 0x7fff,0x8001,fr8 + cmcpxrs fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x0000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxrs fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + ; Positive operands + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_fr_iimmed 2,4,fr7 ; multiply small numbers + set_fr_iimmed 3,5,fr8 + cmcpxrs fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 3,1,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmcpxrs fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,1,fr8 + cmcpxrs fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x0007,fr8 + cmcpxrs fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x2000,fr8 + cmcpxrs fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxrs fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,1,fr8 + cmcpxrs fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,2,fr7 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr8 + cmcpxrs fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 1,0xfffe,fr8 + cmcpxrs fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfffe,0xfff9,fr8 + cmcpxrs fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0xfffe,0x0003,fr8 + cmcpxrs fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxrs fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxrs fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffc,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffb,fr8 + cmcpxrs fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xffff,0xffff,fr7 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr8 + cmcpxrs fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; almost max positive result + set_fr_iimmed 0x7fff,0x8001,fr8 + cmcpxrs fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x0000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxrs fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + ; Positive operands + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_fr_iimmed 2,4,fr7 ; multiply small numbers + set_fr_iimmed 3,5,fr8 + cmcpxrs fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 3,1,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmcpxrs fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,1,fr8 + cmcpxrs fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x0007,fr8 + cmcpxrs fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x2000,fr8 + cmcpxrs fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxrs fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,1,fr8 + cmcpxrs fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,2,fr7 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr8 + cmcpxrs fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 1,0xfffe,fr8 + cmcpxrs fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfffe,0xfff9,fr8 + cmcpxrs fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0xfffe,0x0003,fr8 + cmcpxrs fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxrs fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxrs fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffc,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffb,fr8 + cmcpxrs fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xffff,0xffff,fr7 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr8 + cmcpxrs fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; almost max positive result + set_fr_iimmed 0x7fff,0x8001,fr8 + cmcpxrs fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x0000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxrs fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 +; + ; Positive operands + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_fr_iimmed 2,4,fr7 ; multiply small numbers + set_fr_iimmed 3,5,fr8 + cmcpxrs fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 3,1,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmcpxrs fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,1,fr8 + cmcpxrs fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x0007,fr8 + cmcpxrs fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x2000,fr8 + cmcpxrs fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxrs fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,1,fr8 + cmcpxrs fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,2,fr7 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr8 + cmcpxrs fr7,fr8,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 1,0xfffe,fr8 + cmcpxrs fr7,fr8,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfffe,0xfff9,fr8 + cmcpxrs fr7,fr8,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0xfffe,0x0003,fr8 + cmcpxrs fr7,fr8,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxrs fr7,fr8,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxrs fr7,fr8,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffc,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffb,fr8 + cmcpxrs fr7,fr8,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xffff,0xffff,fr7 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr8 + cmcpxrs fr7,fr8,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; almost max positive result + set_fr_iimmed 0x7fff,0x8001,fr8 + cmcpxrs fr7,fr8,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x0000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmcpxrs fr7,fr8,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + pass diff --git a/sim/testsuite/sim/frv/cmcpxru.cgs b/sim/testsuite/sim/frv/cmcpxru.cgs new file mode 100644 index 0000000..f9217b6 --- /dev/null +++ b/sim/testsuite/sim/frv/cmcpxru.cgs @@ -0,0 +1,544 @@ +# frv testcase for cmcpxru $GRi,$GRj,$GRk,$CCi,$cond +# mach: frv fr500 fr400 + + .include "testutils.inc" + + start + + .global cmcpxru +cmcpxru: + set_spr_immed 0x1b1b,cccr + + set_fr_iimmed 4,2,fr7 ; multiply small numbers + set_fr_iimmed 5,3,fr8 + cmcpxru fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_immed 14,acc0 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 3,1,fr8 + cmcpxru fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_immed 1,acc0 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmcpxru fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + + set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result + set_fr_iimmed 2,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x7ffd,acc0 + + set_fr_iimmed 0x4000,1,fr7 ; 16 bit result + set_fr_iimmed 4,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0xffff,acc0 + + set_fr_iimmed 0x8000,1,fr7 ; 17 bit result + set_fr_iimmed 4,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_immed 0x0001ffff,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxru fr7,fr8,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x0000,fr8 + cmcpxru fr7,fr8,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_limmed 0x4000,0x0000,acc0 + + set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxru fr7,fr8,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_limmed 0xfffe,0x0001,acc0 + + set_fr_iimmed 0x0000,0x0001,fr7 ; saturation + set_fr_iimmed 0xffff,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc4,1 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + + set_fr_iimmed 0x0000,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxru fr7,fr8,acc0,cc4,1 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + + set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxru fr7,fr8,acc0,cc4,1 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + + set_fr_iimmed 4,2,fr7 ; multiply small numbers + set_fr_iimmed 5,3,fr8 + cmcpxru fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_immed 14,acc0 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 3,1,fr8 + cmcpxru fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_immed 1,acc0 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmcpxru fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + + set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result + set_fr_iimmed 2,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x7ffd,acc0 + + set_fr_iimmed 0x4000,1,fr7 ; 16 bit result + set_fr_iimmed 4,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0xffff,acc0 + + set_fr_iimmed 0x8000,1,fr7 ; 17 bit result + set_fr_iimmed 4,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_immed 0x0001ffff,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxru fr7,fr8,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x0000,fr8 + cmcpxru fr7,fr8,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_limmed 0x4000,0x0000,acc0 + + set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxru fr7,fr8,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_limmed 0xfffe,0x0001,acc0 + + set_fr_iimmed 0x0000,0x0001,fr7 ; saturation + set_fr_iimmed 0xffff,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc5,0 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + + set_fr_iimmed 0x0000,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxru fr7,fr8,acc0,cc5,0 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + + set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxru fr7,fr8,acc0,cc5,0 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_fr_iimmed 4,2,fr7 ; multiply small numbers + set_fr_iimmed 5,3,fr8 + cmcpxru fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 3,1,fr8 + cmcpxru fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmcpxru fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result + set_fr_iimmed 2,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,1,fr7 ; 16 bit result + set_fr_iimmed 4,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,1,fr7 ; 17 bit result + set_fr_iimmed 4,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxru fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x0000,fr8 + cmcpxru fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxru fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x0000,0x0001,fr7 ; saturation + set_fr_iimmed 0xffff,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x0000,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxru fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxru fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_fr_iimmed 4,2,fr7 ; multiply small numbers + set_fr_iimmed 5,3,fr8 + cmcpxru fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 3,1,fr8 + cmcpxru fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmcpxru fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result + set_fr_iimmed 2,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,1,fr7 ; 16 bit result + set_fr_iimmed 4,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,1,fr7 ; 17 bit result + set_fr_iimmed 4,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxru fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x0000,fr8 + cmcpxru fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxru fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x0000,0x0001,fr7 ; saturation + set_fr_iimmed 0xffff,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x0000,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxru fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxru fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_fr_iimmed 4,2,fr7 ; multiply small numbers + set_fr_iimmed 5,3,fr8 + cmcpxru fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 3,1,fr8 + cmcpxru fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmcpxru fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result + set_fr_iimmed 2,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,1,fr7 ; 16 bit result + set_fr_iimmed 4,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,1,fr7 ; 17 bit result + set_fr_iimmed 4,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxru fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x0000,fr8 + cmcpxru fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxru fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x0000,0x0001,fr7 ; saturation + set_fr_iimmed 0xffff,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc6,1 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x0000,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxru fr7,fr8,acc0,cc6,1 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxru fr7,fr8,acc0,cc6,1 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 +; + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_fr_iimmed 4,2,fr7 ; multiply small numbers + set_fr_iimmed 5,3,fr8 + cmcpxru fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 3,1,fr8 + cmcpxru fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmcpxru fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result + set_fr_iimmed 2,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,1,fr7 ; 16 bit result + set_fr_iimmed 4,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,1,fr7 ; 17 bit result + set_fr_iimmed 4,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxru fr7,fr8,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x0000,fr8 + cmcpxru fr7,fr8,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxru fr7,fr8,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x0000,0x0001,fr7 ; saturation + set_fr_iimmed 0xffff,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc7,1 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x0000,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxru fr7,fr8,acc0,cc7,1 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxru fr7,fr8,acc0,cc7,1 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + pass diff --git a/sim/testsuite/sim/frv/cmexpdhd.cgs b/sim/testsuite/sim/frv/cmexpdhd.cgs new file mode 100644 index 0000000..33a3c00 --- /dev/null +++ b/sim/testsuite/sim/frv/cmexpdhd.cgs @@ -0,0 +1,116 @@ +# frv testcase for cmexpdhd $FRi,$s6,$FRj,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cmexpdhd +cmexpdhd: + set_spr_immed 0x1b1b,cccr + + set_fr_iimmed 0xdead,0xbeef,fr10 + cmexpdhd fr10,0,fr12,cc0,1 + test_fr_limmed 0xdead,0xdead,fr12 + test_fr_limmed 0xdead,0xdead,fr13 + + cmexpdhd fr10,1,fr12,cc0,1 + test_fr_limmed 0xbeef,0xbeef,fr12 + test_fr_limmed 0xbeef,0xbeef,fr13 + + cmexpdhd fr10,62,fr12,cc4,1 + test_fr_limmed 0xdead,0xdead,fr12 + test_fr_limmed 0xdead,0xdead,fr13 + + cmexpdhd fr10,63,fr12,cc4,1 + test_fr_limmed 0xbeef,0xbeef,fr12 + test_fr_limmed 0xbeef,0xbeef,fr13 + + set_fr_iimmed 0xdead,0xbeef,fr10 + cmexpdhd fr10,0,fr12,cc1,0 + test_fr_limmed 0xdead,0xdead,fr12 + test_fr_limmed 0xdead,0xdead,fr13 + + cmexpdhd fr10,1,fr12,cc1,0 + test_fr_limmed 0xbeef,0xbeef,fr12 + test_fr_limmed 0xbeef,0xbeef,fr13 + + cmexpdhd fr10,62,fr12,cc5,0 + test_fr_limmed 0xdead,0xdead,fr12 + test_fr_limmed 0xdead,0xdead,fr13 + + cmexpdhd fr10,63,fr12,cc5,0 + test_fr_limmed 0xbeef,0xbeef,fr12 + test_fr_limmed 0xbeef,0xbeef,fr13 + + set_fr_iimmed 0x1111,0x1111,fr12 + set_fr_iimmed 0x2222,0x2222,fr13 + set_fr_iimmed 0xdead,0xbeef,fr10 + cmexpdhd fr10,0,fr12,cc0,0 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + + cmexpdhd fr10,1,fr12,cc0,0 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + + cmexpdhd fr10,62,fr12,cc4,0 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + + cmexpdhd fr10,63,fr12,cc4,0 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + + set_fr_iimmed 0xdead,0xbeef,fr10 + cmexpdhd fr10,0,fr12,cc1,1 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + + cmexpdhd fr10,1,fr12,cc1,1 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + + cmexpdhd fr10,62,fr12,cc5,1 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + + cmexpdhd fr10,63,fr12,cc5,1 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + + set_fr_iimmed 0xdead,0xbeef,fr10 + cmexpdhd fr10,0,fr12,cc2,1 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + + cmexpdhd fr10,1,fr12,cc2,0 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + + cmexpdhd fr10,62,fr12,cc6,1 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + + cmexpdhd fr10,63,fr12,cc6,0 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + + set_fr_iimmed 0xdead,0xbeef,fr10 + cmexpdhd fr10,0,fr12,cc3,1 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + + cmexpdhd fr10,1,fr12,cc3,0 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + + cmexpdhd fr10,62,fr12,cc7,1 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + + cmexpdhd fr10,63,fr12,cc7,0 + test_fr_limmed 0x1111,0x1111,fr12 + test_fr_limmed 0x2222,0x2222,fr13 + + pass diff --git a/sim/testsuite/sim/frv/cmexpdhw.cgs b/sim/testsuite/sim/frv/cmexpdhw.cgs new file mode 100644 index 0000000..330d404 --- /dev/null +++ b/sim/testsuite/sim/frv/cmexpdhw.cgs @@ -0,0 +1,91 @@ +# frv testcase for cmexpdhw $FRi,$s6,$FRj,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cmexpdhw +cmexpdhw: + set_spr_immed 0x1b1b,cccr + + set_fr_iimmed 0xdead,0xbeef,fr10 + cmexpdhw fr10,0,fr12,cc0,1 + test_fr_limmed 0xdead,0xdead,fr12 + + cmexpdhw fr10,1,fr12,cc0,1 + test_fr_limmed 0xbeef,0xbeef,fr12 + + cmexpdhw fr10,62,fr12,cc4,1 + test_fr_limmed 0xdead,0xdead,fr12 + + cmexpdhw fr10,63,fr12,cc4,1 + test_fr_limmed 0xbeef,0xbeef,fr12 + + set_fr_iimmed 0xdead,0xbeef,fr10 + cmexpdhw fr10,0,fr12,cc1,0 + test_fr_limmed 0xdead,0xdead,fr12 + + cmexpdhw fr10,1,fr12,cc1,0 + test_fr_limmed 0xbeef,0xbeef,fr12 + + cmexpdhw fr10,62,fr12,cc5,0 + test_fr_limmed 0xdead,0xdead,fr12 + + cmexpdhw fr10,63,fr12,cc5,0 + test_fr_limmed 0xbeef,0xbeef,fr12 + + set_fr_iimmed 0x1111,0x1111,fr12 + set_fr_iimmed 0xdead,0xbeef,fr10 + cmexpdhw fr10,0,fr12,cc0,0 + test_fr_limmed 0x1111,0x1111,fr12 + + cmexpdhw fr10,1,fr12,cc0,0 + test_fr_limmed 0x1111,0x1111,fr12 + + cmexpdhw fr10,62,fr12,cc4,0 + test_fr_limmed 0x1111,0x1111,fr12 + + cmexpdhw fr10,63,fr12,cc4,0 + test_fr_limmed 0x1111,0x1111,fr12 + + set_fr_iimmed 0xdead,0xbeef,fr10 + cmexpdhw fr10,0,fr12,cc1,1 + test_fr_limmed 0x1111,0x1111,fr12 + + cmexpdhw fr10,1,fr12,cc1,1 + test_fr_limmed 0x1111,0x1111,fr12 + + cmexpdhw fr10,62,fr12,cc5,1 + test_fr_limmed 0x1111,0x1111,fr12 + + cmexpdhw fr10,63,fr12,cc5,1 + test_fr_limmed 0x1111,0x1111,fr12 + + set_fr_iimmed 0xdead,0xbeef,fr10 + cmexpdhw fr10,0,fr12,cc2,1 + test_fr_limmed 0x1111,0x1111,fr12 + + cmexpdhw fr10,1,fr12,cc2,0 + test_fr_limmed 0x1111,0x1111,fr12 + + cmexpdhw fr10,62,fr12,cc6,1 + test_fr_limmed 0x1111,0x1111,fr12 + + cmexpdhw fr10,63,fr12,cc6,0 + test_fr_limmed 0x1111,0x1111,fr12 + + set_fr_iimmed 0xdead,0xbeef,fr10 + cmexpdhw fr10,0,fr12,cc3,1 + test_fr_limmed 0x1111,0x1111,fr12 + + cmexpdhw fr10,1,fr12,cc3,0 + test_fr_limmed 0x1111,0x1111,fr12 + + cmexpdhw fr10,62,fr12,cc7,1 + test_fr_limmed 0x1111,0x1111,fr12 + + cmexpdhw fr10,63,fr12,cc7,0 + test_fr_limmed 0x1111,0x1111,fr12 + + pass diff --git a/sim/testsuite/sim/frv/cmhtob.cgs b/sim/testsuite/sim/frv/cmhtob.cgs new file mode 100644 index 0000000..a3f00c5 --- /dev/null +++ b/sim/testsuite/sim/frv/cmhtob.cgs @@ -0,0 +1,103 @@ +# frv testcase for cmhtob $FRj,$FRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cmhtob +cmhtob: + set_spr_immed 0x1b1b,cccr + + set_fr_iimmed 0x00ad,0x00ef,fr10 + set_fr_iimmed 0x0034,0x0078,fr11 + cmhtob fr10,fr12,cc0,1 + test_fr_limmed 0xadef,0x3478,fr12 + + set_fr_iimmed 0xdead,0xbeef,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + cmhtob fr10,fr12,cc0,1 + test_fr_limmed 0xffff,0xffff,fr12 + + set_fr_iimmed 0x0134,0x0878,fr10 + set_fr_iimmed 0x10ad,0x80ef,fr11 + cmhtob fr10,fr12,cc4,1 + test_fr_limmed 0xffff,0xffff,fr12 + + set_fr_iimmed 0x00ad,0x00ef,fr10 + set_fr_iimmed 0x0034,0x0078,fr11 + cmhtob fr10,fr12,cc1,0 + test_fr_limmed 0xadef,0x3478,fr12 + + set_fr_iimmed 0xdead,0xbeef,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + cmhtob fr10,fr12,cc1,0 + test_fr_limmed 0xffff,0xffff,fr12 + + set_fr_iimmed 0x0134,0x0878,fr10 + set_fr_iimmed 0x10ad,0x80ef,fr11 + cmhtob fr10,fr12,cc5,0 + test_fr_limmed 0xffff,0xffff,fr12 + + set_fr_iimmed 0x1111,0x1111,fr12 + set_fr_iimmed 0x00ad,0x00ef,fr10 + set_fr_iimmed 0x0034,0x0078,fr11 + cmhtob fr10,fr12,cc0,0 + test_fr_limmed 0x1111,0x1111,fr12 + + set_fr_iimmed 0xdead,0xbeef,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + cmhtob fr10,fr12,cc0,0 + test_fr_limmed 0x1111,0x1111,fr12 + + set_fr_iimmed 0x0134,0x0878,fr10 + set_fr_iimmed 0x10ad,0x80ef,fr11 + cmhtob fr10,fr12,cc4,0 + test_fr_limmed 0x1111,0x1111,fr12 + + set_fr_iimmed 0x00ad,0x00ef,fr10 + set_fr_iimmed 0x0034,0x0078,fr11 + cmhtob fr10,fr12,cc1,1 + test_fr_limmed 0x1111,0x1111,fr12 + + set_fr_iimmed 0xdead,0xbeef,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + cmhtob fr10,fr12,cc1,1 + test_fr_limmed 0x1111,0x1111,fr12 + + set_fr_iimmed 0x0134,0x0878,fr10 + set_fr_iimmed 0x10ad,0x80ef,fr11 + cmhtob fr10,fr12,cc5,1 + test_fr_limmed 0x1111,0x1111,fr12 + + set_fr_iimmed 0x00ad,0x00ef,fr10 + set_fr_iimmed 0x0034,0x0078,fr11 + cmhtob fr10,fr12,cc2,1 + test_fr_limmed 0x1111,0x1111,fr12 + + set_fr_iimmed 0xdead,0xbeef,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + cmhtob fr10,fr12,cc2,0 + test_fr_limmed 0x1111,0x1111,fr12 + + set_fr_iimmed 0x0134,0x0878,fr10 + set_fr_iimmed 0x10ad,0x80ef,fr11 + cmhtob fr10,fr12,cc6,1 + test_fr_limmed 0x1111,0x1111,fr12 + + set_fr_iimmed 0x00ad,0x00ef,fr10 + set_fr_iimmed 0x0034,0x0078,fr11 + cmhtob fr10,fr12,cc3,1 + test_fr_limmed 0x1111,0x1111,fr12 + + set_fr_iimmed 0xdead,0xbeef,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + cmhtob fr10,fr12,cc7,0 + test_fr_limmed 0x1111,0x1111,fr12 + + set_fr_iimmed 0x0134,0x0878,fr10 + set_fr_iimmed 0x10ad,0x80ef,fr11 + cmhtob fr10,fr12,cc7,1 + test_fr_limmed 0x1111,0x1111,fr12 + + pass diff --git a/sim/testsuite/sim/frv/cmmachs.cgs b/sim/testsuite/sim/frv/cmmachs.cgs new file mode 100644 index 0000000..2131b7e --- /dev/null +++ b/sim/testsuite/sim/frv/cmmachs.cgs @@ -0,0 +1,1631 @@ +# frv testcase for cmmachs $GRi,$GRj,$ACCk,$CCi,$cond +# mach: frv fr500 fr400 + + .include "testutils.inc" + + start + + .global cmmachs +cmmachs: + set_spr_immed 0x1b1b,cccr + + ; Positive operands + set_spr_immed 0x0,msr0 + set_spr_immed 0x0,msr1 + set_accg_immed 0x0,accg0 + set_acc_immed 0x0,acc0 + set_accg_immed 0x0,accg1 + set_acc_immed 0x0,acc1 + set_fr_iimmed 2,3,fr7 ; multiply small numbers + set_fr_iimmed 3,2,fr8 + cmmachs fr7,fr8,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + + set_fr_iimmed 0,1,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmachs fr7,fr8,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,2,fr8 + cmmachs fr7,fr8,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 8,acc0 + test_accg_immed 0,accg1 + test_acc_immed 8,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmachs fr7,fr8,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0,0x8006,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0,0x8006,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmachs fr7,fr8,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0001,0x0006,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0001,0x0006,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x4000,0x0007,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x4000,0x0007,acc1 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr8 + cmmachs fr7,fr8,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x4000,0x0001,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x4000,0x0001,acc1 + + set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr8 + cmmachs fr7,fr8,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0xffff,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0xffff,acc1 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr8 + cmmachs fr7,fr8,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0xffff,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0xffff,acc1 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr8 + cmmachs fr7,fr8,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0xbffd,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0xbffd,acc1 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr8 + cmmachs fr7,fr8,acc0,cc4,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0x3ffd,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0x3ffd,acc1 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc4,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xbffd,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xbffd,acc1 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr8 + cmmachs fr7,fr8,acc0,cc4,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xc003,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xc003,acc1 + + set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr8 + cmmachs fr7,fr8,acc0,cc4,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xc005,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xc005,acc1 + + set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr8 + cmmachs fr7,fr8,acc0,cc4,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0x3ffec006,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3ffec006,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmachs fr7,fr8,acc0,cc4,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0x7ffec006,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x7ffec006,acc1 + + set_accg_immed 0x7f,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0x7f,accg1 + set_acc_immed 0xffffffff,acc1 + set_fr_iimmed 1,1,fr7 + set_fr_iimmed 1,1,fr8 + cmmachs fr7,fr8,acc0,cc4,1 +;;;;;;;;;;;; + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc4,1 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + + set_accg_immed -128,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed -128,accg1 + set_acc_immed 0,acc1 + set_fr_iimmed 0xffff,0,fr7 + set_fr_iimmed 1,0xffff,fr8 + cmmachs fr7,fr8,acc0,cc4,1 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x80,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x0000,0x8000,fr7 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc4,1 + test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x80,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + + ; Positive operands + set_spr_immed 0x0,msr0 + set_spr_immed 0x0,msr1 + set_accg_immed 0x0,accg0 ; saturation + set_acc_immed 0x0,acc0 + set_accg_immed 0x0,accg1 + set_acc_immed 0x0,acc1 + set_fr_iimmed 2,3,fr7 ; multiply small numbers + set_fr_iimmed 3,2,fr8 + cmmachs fr7,fr8,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + + set_fr_iimmed 0,1,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmachs fr7,fr8,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,2,fr8 + cmmachs fr7,fr8,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 8,acc0 + test_accg_immed 0,accg1 + test_acc_immed 8,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmachs fr7,fr8,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0,0x8006,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0,0x8006,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmachs fr7,fr8,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0001,0x0006,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0001,0x0006,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x4000,0x0007,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x4000,0x0007,acc1 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr8 + cmmachs fr7,fr8,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x4000,0x0001,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x4000,0x0001,acc1 + + set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr8 + cmmachs fr7,fr8,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0xffff,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0xffff,acc1 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr8 + cmmachs fr7,fr8,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0xffff,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0xffff,acc1 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr8 + cmmachs fr7,fr8,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0xbffd,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0xbffd,acc1 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr8 + cmmachs fr7,fr8,acc0,cc5,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0x3ffd,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0x3ffd,acc1 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc5,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xbffd,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xbffd,acc1 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr8 + cmmachs fr7,fr8,acc0,cc5,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xc003,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xc003,acc1 + + set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr8 + cmmachs fr7,fr8,acc0,cc5,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xc005,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xc005,acc1 + + set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr8 + cmmachs fr7,fr8,acc0,cc5,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0x3ffec006,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3ffec006,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmachs fr7,fr8,acc0,cc5,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0x7ffec006,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x7ffec006,acc1 + + set_accg_immed 0x7f,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0x7f,accg1 + set_acc_immed 0xffffffff,acc1 + set_fr_iimmed 1,1,fr7 + set_fr_iimmed 1,1,fr8 + cmmachs fr7,fr8,acc0,cc5,0 + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc5,0 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + + set_accg_immed 0x80,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed 0x80,accg1 + set_acc_immed 0,acc1 + set_fr_iimmed 0xffff,0,fr7 + set_fr_iimmed 1,0xffff,fr8 + cmmachs fr7,fr8,acc0,cc5,0 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x80,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x0000,0x8000,fr7 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc5,0 + test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x80,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + + ; Positive operands + set_spr_immed 0x0,msr0 + set_spr_immed 0x0,msr1 + set_accg_immed 0x0,accg0 + set_acc_immed 0x0,acc0 + set_accg_immed 0x0,accg1 + set_acc_immed 0x0,acc1 + set_fr_iimmed 2,3,fr7 ; multiply small numbers + set_fr_iimmed 3,2,fr8 + cmmachs fr7,fr8,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0,1,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmachs fr7,fr8,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,2,fr8 + cmmachs fr7,fr8,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmachs fr7,fr8,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmachs fr7,fr8,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr8 + cmmachs fr7,fr8,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr8 + cmmachs fr7,fr8,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr8 + cmmachs fr7,fr8,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr8 + cmmachs fr7,fr8,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr8 + cmmachs fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr8 + cmmachs fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr8 + cmmachs fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr8 + cmmachs fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmachs fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_accg_immed 0x7f,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0x7f,accg1 + set_acc_immed 0xffffffff,acc1 + set_fr_iimmed 1,1,fr7 + set_fr_iimmed 1,1,fr8 + cmmachs fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x7f,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_immed 0xffffffff,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x7f,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_immed 0xffffffff,acc1 + + set_accg_immed 0x80,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed 0x80,accg1 + set_acc_immed 0,acc1 + set_fr_iimmed 0xffff,0,fr7 + set_fr_iimmed 1,0xffff,fr8 + cmmachs fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x80,accg0 ; saturation + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x0000,0x8000,fr7 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x80,accg0 ; saturation + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + + ; Positive operands + set_spr_immed 0x0,msr0 + set_spr_immed 0x0,msr1 + set_accg_immed 0x0,accg0 + set_acc_immed 0x0,acc0 + set_accg_immed 0x0,accg1 + set_acc_immed 0x0,acc1 + set_fr_iimmed 2,3,fr7 ; multiply small numbers + set_fr_iimmed 3,2,fr8 + cmmachs fr7,fr8,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0,1,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmachs fr7,fr8,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,2,fr8 + cmmachs fr7,fr8,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmachs fr7,fr8,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmachs fr7,fr8,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr8 + cmmachs fr7,fr8,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr8 + cmmachs fr7,fr8,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr8 + cmmachs fr7,fr8,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr8 + cmmachs fr7,fr8,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr8 + cmmachs fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr8 + cmmachs fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr8 + cmmachs fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr8 + cmmachs fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmachs fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_accg_immed 0x7f,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0x7f,accg1 + set_acc_immed 0xffffffff,acc1 + set_fr_iimmed 1,1,fr7 + set_fr_iimmed 1,1,fr8 + cmmachs fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x7f,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_immed 0xffffffff,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x7f,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_immed 0xffffffff,acc1 + + set_accg_immed 0x80,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed 0x80,accg1 + set_acc_immed 0,acc1 + set_fr_iimmed 0xffff,0,fr7 + set_fr_iimmed 1,0xffff,fr8 + cmmachs fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x80,accg0 ; saturation + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x0000,0x8000,fr7 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x80,accg0 ; saturation + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + + ; Positive operands + set_spr_immed 0x0,msr0 + set_spr_immed 0x0,msr1 + set_accg_immed 0x0,accg0 + set_acc_immed 0x0,acc0 + set_accg_immed 0x0,accg1 + set_acc_immed 0x0,acc1 + set_fr_iimmed 2,3,fr7 ; multiply small numbers + set_fr_iimmed 3,2,fr8 + cmmachs fr7,fr8,acc0,cc2,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0,1,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmachs fr7,fr8,acc0,cc2,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,2,fr8 + cmmachs fr7,fr8,acc0,cc2,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmachs fr7,fr8,acc0,cc2,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmachs fr7,fr8,acc0,cc2,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc2,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr8 + cmmachs fr7,fr8,acc0,cc2,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr8 + cmmachs fr7,fr8,acc0,cc2,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr8 + cmmachs fr7,fr8,acc0,cc2,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr8 + cmmachs fr7,fr8,acc0,cc2,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr8 + cmmachs fr7,fr8,acc0,cc6,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc6,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr8 + cmmachs fr7,fr8,acc0,cc6,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr8 + cmmachs fr7,fr8,acc0,cc6,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr8 + cmmachs fr7,fr8,acc0,cc6,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmachs fr7,fr8,acc0,cc6,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_accg_immed 0x7f,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0x7f,accg1 + set_acc_immed 0xffffffff,acc1 + set_fr_iimmed 1,1,fr7 + set_fr_iimmed 1,1,fr8 + cmmachs fr7,fr8,acc0,cc6,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x7f,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_immed 0xffffffff,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc6,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x7f,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_immed 0xffffffff,acc1 + + set_accg_immed 0x80,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed 0x80,accg1 + set_acc_immed 0,acc1 + set_fr_iimmed 0xffff,0,fr7 + set_fr_iimmed 1,0xffff,fr8 + cmmachs fr7,fr8,acc0,cc6,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x80,accg0 ; saturation + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x0000,0x8000,fr7 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc6,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x80,accg0 ; saturation + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 +; + ; Positive operands + set_spr_immed 0x0,msr0 + set_spr_immed 0x0,msr1 + set_accg_immed 0x0,accg0 + set_acc_immed 0x0,acc0 + set_accg_immed 0x0,accg1 + set_acc_immed 0x0,acc1 + set_fr_iimmed 2,3,fr7 ; multiply small numbers + set_fr_iimmed 3,2,fr8 + cmmachs fr7,fr8,acc0,cc3,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0,1,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmachs fr7,fr8,acc0,cc3,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,2,fr8 + cmmachs fr7,fr8,acc0,cc3,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmachs fr7,fr8,acc0,cc3,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmachs fr7,fr8,acc0,cc3,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc3,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr8 + cmmachs fr7,fr8,acc0,cc3,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr8 + cmmachs fr7,fr8,acc0,cc3,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr8 + cmmachs fr7,fr8,acc0,cc3,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr8 + cmmachs fr7,fr8,acc0,cc3,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr8 + cmmachs fr7,fr8,acc0,cc7,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc7,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr8 + cmmachs fr7,fr8,acc0,cc7,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr8 + cmmachs fr7,fr8,acc0,cc7,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr8 + cmmachs fr7,fr8,acc0,cc7,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmachs fr7,fr8,acc0,cc7,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_accg_immed 0x7f,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0x7f,accg1 + set_acc_immed 0xffffffff,acc1 + set_fr_iimmed 1,1,fr7 + set_fr_iimmed 1,1,fr8 + cmmachs fr7,fr8,acc0,cc7,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x7f,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_immed 0xffffffff,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc7,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x7f,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_immed 0xffffffff,acc1 + + set_accg_immed 0x80,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed 0x80,accg1 + set_acc_immed 0,acc1 + set_fr_iimmed 0xffff,0,fr7 + set_fr_iimmed 1,0xffff,fr8 + cmmachs fr7,fr8,acc0,cc7,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x80,accg0 ; saturation + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x0000,0x8000,fr7 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc7,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x80,accg0 ; saturation + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + + pass diff --git a/sim/testsuite/sim/frv/cmmachu.cgs b/sim/testsuite/sim/frv/cmmachu.cgs new file mode 100644 index 0000000..8948f15 --- /dev/null +++ b/sim/testsuite/sim/frv/cmmachu.cgs @@ -0,0 +1,864 @@ +# frv testcase for cmmachu $GRi,$GRj,$GRk,$CCi,$cond +# mach: frv fr500 fr400 + + .include "testutils.inc" + + start + + .global cmmachu +cmmachu: + set_spr_immed 0x1b1b,cccr + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_accg_immed 0,accg0 + set_acc_immed 0,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0,acc1 + set_fr_iimmed 3,2,fr7 ; multiply small numbers + set_fr_iimmed 2,3,fr8 + cmmachu fr7,fr8,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 2,1,fr8 + cmmachu fr7,fr8,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 8,acc0 + test_accg_immed 0,accg1 + test_acc_immed 8,acc1 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmachu fr7,fr8,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 8,acc0 + test_accg_immed 0,accg1 + test_acc_immed 8,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmachu fr7,fr8,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8006,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8006,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmachu fr7,fr8,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0001,0x0006,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0001,0x0006,acc1 + + set_fr_iimmed 0x8000,2,fr7 ; 17 bit result + set_fr_iimmed 2,0x8000,fr8 + cmmachu fr7,fr8,acc0,cc4,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0x00020006,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x00020006,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachu fr7,fr8,acc0,cc4,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0x40010007,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x40010007,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmachu fr7,fr8,acc0,cc4,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x8001,0x0007,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x8001,0x0007,acc1 + + set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmmachu fr7,fr8,acc0,cc4,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 1,accg0 + test_acc_limmed 0x7fff,0x0008,acc0 + test_accg_immed 1,accg1 + test_acc_limmed 0x7fff,0x0008,acc1 + + set_accg_immed 0xff,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xffffffff,acc1 + set_fr_iimmed 1,1,fr7 + set_fr_iimmed 1,1,fr8 + cmmachu fr7,fr8,acc0,cc4,1 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + + set_fr_iimmed 0xffff,0x0000,fr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cmmachu fr7,fr8,acc0,cc4,1 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_accg_immed 0,accg0 + set_acc_immed 0,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0,acc1 + set_fr_iimmed 3,2,fr7 ; multiply small numbers + set_fr_iimmed 2,3,fr8 + cmmachu fr7,fr8,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 2,1,fr8 + cmmachu fr7,fr8,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 8,acc0 + test_accg_immed 0,accg1 + test_acc_immed 8,acc1 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmachu fr7,fr8,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 8,acc0 + test_accg_immed 0,accg1 + test_acc_immed 8,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmachu fr7,fr8,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8006,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8006,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmachu fr7,fr8,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0001,0x0006,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0001,0x0006,acc1 + + set_fr_iimmed 0x8000,2,fr7 ; 17 bit result + set_fr_iimmed 2,0x8000,fr8 + cmmachu fr7,fr8,acc0,cc5,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0x00020006,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x00020006,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachu fr7,fr8,acc0,cc5,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0x40010007,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x40010007,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmachu fr7,fr8,acc0,cc5,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x8001,0x0007,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x8001,0x0007,acc1 + + set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmmachu fr7,fr8,acc0,cc5,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 1,accg0 + test_acc_limmed 0x7fff,0x0008,acc0 + test_accg_immed 1,accg1 + test_acc_limmed 0x7fff,0x0008,acc1 + + set_accg_immed 0xff,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xffffffff,acc1 + set_fr_iimmed 1,1,fr7 + set_fr_iimmed 1,1,fr8 + cmmachu fr7,fr8,acc0,cc5,0 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + + set_fr_iimmed 0xffff,0x0000,fr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cmmachu fr7,fr8,acc0,cc5,0 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_fr_iimmed 3,2,fr7 ; multiply small numbers + set_fr_iimmed 2,3,fr8 + cmmachu fr7,fr8,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 2,1,fr8 + cmmachu fr7,fr8,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmachu fr7,fr8,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmachu fr7,fr8,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmachu fr7,fr8,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x8000,2,fr7 ; 17 bit result + set_fr_iimmed 2,0x8000,fr8 + cmmachu fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachu fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmachu fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmmachu fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_accg_immed 0xff,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xffffffff,acc1 + set_fr_iimmed 1,1,fr7 + set_fr_iimmed 1,1,fr8 + cmmachu fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed 0xffffffff,acc1 + + set_fr_iimmed 0xffff,0x0000,fr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cmmachu fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed 0xffffffff,acc1 + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_fr_iimmed 3,2,fr7 ; multiply small numbers + set_fr_iimmed 2,3,fr8 + cmmachu fr7,fr8,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 2,1,fr8 + cmmachu fr7,fr8,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmachu fr7,fr8,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmachu fr7,fr8,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmachu fr7,fr8,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x8000,2,fr7 ; 17 bit result + set_fr_iimmed 2,0x8000,fr8 + cmmachu fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachu fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmachu fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmmachu fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_accg_immed 0xff,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xffffffff,acc1 + set_fr_iimmed 1,1,fr7 + set_fr_iimmed 1,1,fr8 + cmmachu fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed 0xffffffff,acc1 + + set_fr_iimmed 0xffff,0x0000,fr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cmmachu fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed 0xffffffff,acc1 + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_fr_iimmed 3,2,fr7 ; multiply small numbers + set_fr_iimmed 2,3,fr8 + cmmachu fr7,fr8,acc0,cc2,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 2,1,fr8 + cmmachu fr7,fr8,acc0,cc2,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmachu fr7,fr8,acc0,cc2,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmachu fr7,fr8,acc0,cc2,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmachu fr7,fr8,acc0,cc2,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x8000,2,fr7 ; 17 bit result + set_fr_iimmed 2,0x8000,fr8 + cmmachu fr7,fr8,acc0,cc6,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachu fr7,fr8,acc0,cc6,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmachu fr7,fr8,acc0,cc6,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmmachu fr7,fr8,acc0,cc6,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_accg_immed 0xff,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xffffffff,acc1 + set_fr_iimmed 1,1,fr7 + set_fr_iimmed 1,1,fr8 + cmmachu fr7,fr8,acc0,cc6,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed 0xffffffff,acc1 + + set_fr_iimmed 0xffff,0x0000,fr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cmmachu fr7,fr8,acc0,cc6,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed 0xffffffff,acc1 +; + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_fr_iimmed 3,2,fr7 ; multiply small numbers + set_fr_iimmed 2,3,fr8 + cmmachu fr7,fr8,acc0,cc3,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 2,1,fr8 + cmmachu fr7,fr8,acc0,cc3,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmachu fr7,fr8,acc0,cc3,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmachu fr7,fr8,acc0,cc3,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmachu fr7,fr8,acc0,cc3,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x8000,2,fr7 ; 17 bit result + set_fr_iimmed 2,0x8000,fr8 + cmmachu fr7,fr8,acc0,cc7,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachu fr7,fr8,acc0,cc7,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmachu fr7,fr8,acc0,cc7,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmmachu fr7,fr8,acc0,cc7,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_accg_immed 0xff,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xffffffff,acc1 + set_fr_iimmed 1,1,fr7 + set_fr_iimmed 1,1,fr8 + cmmachu fr7,fr8,acc0,cc7,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed 0xffffffff,acc1 + + set_fr_iimmed 0xffff,0x0000,fr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cmmachu fr7,fr8,acc0,cc7,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed 0xffffffff,acc1 + + pass diff --git a/sim/testsuite/sim/frv/cmmulhs.cgs b/sim/testsuite/sim/frv/cmmulhs.cgs new file mode 100644 index 0000000..01ee598 --- /dev/null +++ b/sim/testsuite/sim/frv/cmmulhs.cgs @@ -0,0 +1,814 @@ +# frv testcase for cmmulhs $GRi,$GRj,$ACCk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cmmulhs +cmmulhs: + set_spr_immed 0x1b1b,cccr + + ; Positive operands + set_fr_iimmed 2,3,fr7 ; multiply small numbers + set_fr_iimmed 3,2,fr8 + cmmulhs fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + + set_fr_iimmed 0,1,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmulhs fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,2,fr8 + cmmulhs fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_immed 2,acc0 + test_accg_immed 0,accg1 + test_acc_immed 2,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmulhs fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_limmed 0,0x7ffe,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0,0x7ffe,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmulhs fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8000,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8000,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmulhs fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0x0001,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0x0001,acc1 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr8 + cmmulhs fr7,fr8,acc0,cc0,1 + test_accg_immed 0xff,accg0 + test_acc_immed -6,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed -6,acc1 + + set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr8 + cmmulhs fr7,fr8,acc0,cc0,1 + test_accg_immed 0xff,accg0 + test_acc_immed -2,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed -2,acc1 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr8 + cmmulhs fr7,fr8,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr8 + cmmulhs fr7,fr8,acc0,cc4,1 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xbffe,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xbffe,acc1 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr8 + cmmulhs fr7,fr8,acc0,cc4,1 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0x8000,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0x8000,acc1 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr8 + cmmulhs fr7,fr8,acc0,cc4,1 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xc000,0x8000,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xc000,0x8000,acc1 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr8 + cmmulhs fr7,fr8,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + + set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr8 + cmmulhs fr7,fr8,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_immed 2,acc0 + test_accg_immed 0,accg1 + test_acc_immed 2,acc1 + + set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr8 + cmmulhs fr7,fr8,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fff0001,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmulhs fr7,fr8,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_immed 0x40000000,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x40000000,acc1 + + ; Positive operands + set_fr_iimmed 2,3,fr7 ; multiply small numbers + set_fr_iimmed 3,2,fr8 + cmmulhs fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + + set_fr_iimmed 0,1,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmulhs fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,2,fr8 + cmmulhs fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_immed 2,acc0 + test_accg_immed 0,accg1 + test_acc_immed 2,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmulhs fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_limmed 0,0x7ffe,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0,0x7ffe,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmulhs fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8000,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8000,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmulhs fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0x0001,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0x0001,acc1 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr8 + cmmulhs fr7,fr8,acc0,cc1,0 + test_accg_immed 0xff,accg0 + test_acc_immed -6,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed -6,acc1 + + set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr8 + cmmulhs fr7,fr8,acc0,cc1,0 + test_accg_immed 0xff,accg0 + test_acc_immed -2,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed -2,acc1 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr8 + cmmulhs fr7,fr8,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr8 + cmmulhs fr7,fr8,acc0,cc5,0 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xbffe,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xbffe,acc1 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr8 + cmmulhs fr7,fr8,acc0,cc5,0 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0x8000,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0x8000,acc1 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr8 + cmmulhs fr7,fr8,acc0,cc5,0 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xc000,0x8000,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xc000,0x8000,acc1 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr8 + cmmulhs fr7,fr8,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + + set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr8 + cmmulhs fr7,fr8,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_immed 2,acc0 + test_accg_immed 0,accg1 + test_acc_immed 2,acc1 + + set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr8 + cmmulhs fr7,fr8,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fff0001,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmulhs fr7,fr8,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_immed 0x40000000,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x40000000,acc1 + + ; Positive operands + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_fr_iimmed 2,3,fr7 ; multiply small numbers + set_fr_iimmed 3,2,fr8 + cmmulhs fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0,1,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmulhs fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,2,fr8 + cmmulhs fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmulhs fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmulhs fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmulhs fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr8 + cmmulhs fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr8 + cmmulhs fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr8 + cmmulhs fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr8 + cmmulhs fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr8 + cmmulhs fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr8 + cmmulhs fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr8 + cmmulhs fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr8 + cmmulhs fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr8 + cmmulhs fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmulhs fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + ; Positive operands + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_fr_iimmed 2,3,fr7 ; multiply small numbers + set_fr_iimmed 3,2,fr8 + cmmulhs fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0,1,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmulhs fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,2,fr8 + cmmulhs fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmulhs fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmulhs fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmulhs fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr8 + cmmulhs fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr8 + cmmulhs fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr8 + cmmulhs fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr8 + cmmulhs fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr8 + cmmulhs fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr8 + cmmulhs fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr8 + cmmulhs fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr8 + cmmulhs fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr8 + cmmulhs fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmulhs fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + ; Positive operands + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_fr_iimmed 2,3,fr7 ; multiply small numbers + set_fr_iimmed 3,2,fr8 + cmmulhs fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0,1,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmulhs fr7,fr8,acc0,cc2,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,2,fr8 + cmmulhs fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmulhs fr7,fr8,acc0,cc2,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmulhs fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmulhs fr7,fr8,acc0,cc2,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr8 + cmmulhs fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr8 + cmmulhs fr7,fr8,acc0,cc2,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr8 + cmmulhs fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr8 + cmmulhs fr7,fr8,acc0,cc6,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr8 + cmmulhs fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr8 + cmmulhs fr7,fr8,acc0,cc6,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr8 + cmmulhs fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr8 + cmmulhs fr7,fr8,acc0,cc6,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr8 + cmmulhs fr7,fr8,acc0,cc6,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmulhs fr7,fr8,acc0,cc6,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + ; Positive operands + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_fr_iimmed 2,3,fr7 ; multiply small numbers + set_fr_iimmed 3,2,fr8 + cmmulhs fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0,1,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmulhs fr7,fr8,acc0,cc3,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,2,fr8 + cmmulhs fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmulhs fr7,fr8,acc0,cc3,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmulhs fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmulhs fr7,fr8,acc0,cc3,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr8 + cmmulhs fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr8 + cmmulhs fr7,fr8,acc0,cc3,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr8 + cmmulhs fr7,fr8,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr8 + cmmulhs fr7,fr8,acc0,cc7,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr8 + cmmulhs fr7,fr8,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr8 + cmmulhs fr7,fr8,acc0,cc7,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr8 + cmmulhs fr7,fr8,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr8 + cmmulhs fr7,fr8,acc0,cc7,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr8 + cmmulhs fr7,fr8,acc0,cc7,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmulhs fr7,fr8,acc0,cc7,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + pass diff --git a/sim/testsuite/sim/frv/cmmulhu.cgs b/sim/testsuite/sim/frv/cmmulhu.cgs new file mode 100644 index 0000000..9e8fbb8 --- /dev/null +++ b/sim/testsuite/sim/frv/cmmulhu.cgs @@ -0,0 +1,460 @@ +# frv testcase for cmmulhu $GRi,$GRj,$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cmmulhu +cmmulhu: + set_spr_immed 0x1b1b,cccr + + set_fr_iimmed 3,2,fr7 ; multiply small numbers + set_fr_iimmed 2,3,fr8 + cmmulhu fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 2,1,fr8 + cmmulhu fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_immed 2,acc0 + test_accg_immed 0,accg1 + test_acc_immed 2,acc1 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmulhu fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmulhu fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x7ffe,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x7ffe,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmulhu fr7,fr8,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8000,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8000,acc1 + + set_fr_iimmed 0x8000,2,fr7 ; 17 bit result + set_fr_iimmed 2,0x8000,fr8 + cmmulhu fr7,fr8,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_immed 0x00010000,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x00010000,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmulhu fr7,fr8,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fff0001,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmulhu fr7,fr8,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_limmed 0x4000,0x0000,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x4000,0x0000,acc1 + + set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmmulhu fr7,fr8,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_limmed 0xfffe,0x0001,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0xfffe,0x0001,acc1 + + set_fr_iimmed 3,2,fr7 ; multiply small numbers + set_fr_iimmed 2,3,fr8 + cmmulhu fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 2,1,fr8 + cmmulhu fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_immed 2,acc0 + test_accg_immed 0,accg1 + test_acc_immed 2,acc1 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmulhu fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmulhu fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x7ffe,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x7ffe,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmulhu fr7,fr8,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8000,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8000,acc1 + + set_fr_iimmed 0x8000,2,fr7 ; 17 bit result + set_fr_iimmed 2,0x8000,fr8 + cmmulhu fr7,fr8,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_immed 0x00010000,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x00010000,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmulhu fr7,fr8,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fff0001,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmulhu fr7,fr8,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_limmed 0x4000,0x0000,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x4000,0x0000,acc1 + + set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmmulhu fr7,fr8,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_limmed 0xfffe,0x0001,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0xfffe,0x0001,acc1 + + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_fr_iimmed 3,2,fr7 ; multiply small numbers + set_fr_iimmed 2,3,fr8 + cmmulhu fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 2,1,fr8 + cmmulhu fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmulhu fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmulhu fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmulhu fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x8000,2,fr7 ; 17 bit result + set_fr_iimmed 2,0x8000,fr8 + cmmulhu fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmulhu fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmulhu fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmmulhu fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_fr_iimmed 3,2,fr7 ; multiply small numbers + set_fr_iimmed 2,3,fr8 + cmmulhu fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 2,1,fr8 + cmmulhu fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmulhu fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmulhu fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmulhu fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x8000,2,fr7 ; 17 bit result + set_fr_iimmed 2,0x8000,fr8 + cmmulhu fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmulhu fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmulhu fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmmulhu fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_fr_iimmed 3,2,fr7 ; multiply small numbers + set_fr_iimmed 2,3,fr8 + cmmulhu fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 2,1,fr8 + cmmulhu fr7,fr8,acc0,cc2,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmulhu fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmulhu fr7,fr8,acc0,cc2,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmulhu fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x8000,2,fr7 ; 17 bit result + set_fr_iimmed 2,0x8000,fr8 + cmmulhu fr7,fr8,acc0,cc6,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmulhu fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmulhu fr7,fr8,acc0,cc6,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmmulhu fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_fr_iimmed 3,2,fr7 ; multiply small numbers + set_fr_iimmed 2,3,fr8 + cmmulhu fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 2,1,fr8 + cmmulhu fr7,fr8,acc0,cc3,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmulhu fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmulhu fr7,fr8,acc0,cc3,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmulhu fr7,fr8,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x8000,2,fr7 ; 17 bit result + set_fr_iimmed 2,0x8000,fr8 + cmmulhu fr7,fr8,acc0,cc7,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmulhu fr7,fr8,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmulhu fr7,fr8,acc0,cc7,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmmulhu fr7,fr8,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + pass diff --git a/sim/testsuite/sim/frv/cmnot.cgs b/sim/testsuite/sim/frv/cmnot.cgs new file mode 100644 index 0000000..cc93c01 --- /dev/null +++ b/sim/testsuite/sim/frv/cmnot.cgs @@ -0,0 +1,60 @@ +# frv testcase for cmnot $FRintj,$FRintk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cmnot +cmnot: + set_spr_immed 0x1b1b,cccr + + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + cmnot fr7,fr7,cc0,1 + test_fr_iimmed 0x55555555,fr7 + + set_fr_iimmed 0xdead,0xbeef,fr7 + cmnot fr7,fr7,cc4,1 + test_fr_iimmed 0x21524110,fr7 + + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + cmnot fr7,fr7,cc1,0 + test_fr_iimmed 0x55555555,fr7 + + set_fr_iimmed 0xdead,0xbeef,fr7 + cmnot fr7,fr7,cc5,0 + test_fr_iimmed 0x21524110,fr7 + + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + cmnot fr7,fr7,cc0,0 + test_fr_iimmed 0xaaaaaaaa,fr7 + + set_fr_iimmed 0xdead,0xbeef,fr7 + cmnot fr7,fr7,cc4,0 + test_fr_iimmed 0xdeadbeef,fr7 + + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + cmnot fr7,fr7,cc1,1 + test_fr_iimmed 0xaaaaaaaa,fr7 + + set_fr_iimmed 0xdead,0xbeef,fr7 + cmnot fr7,fr7,cc5,1 + test_fr_iimmed 0xdeadbeef,fr7 + + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + cmnot fr7,fr7,cc2,0 + test_fr_iimmed 0xaaaaaaaa,fr7 + + set_fr_iimmed 0xdead,0xbeef,fr7 + cmnot fr7,fr7,cc6,1 + test_fr_iimmed 0xdeadbeef,fr7 + + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + cmnot fr7,fr7,cc3,0 + test_fr_iimmed 0xaaaaaaaa,fr7 + + set_fr_iimmed 0xdead,0xbeef,fr7 + cmnot fr7,fr7,cc7,1 + test_fr_iimmed 0xdeadbeef,fr7 + + pass diff --git a/sim/testsuite/sim/frv/cmor.cgs b/sim/testsuite/sim/frv/cmor.cgs new file mode 100644 index 0000000..ebdc5f2 --- /dev/null +++ b/sim/testsuite/sim/frv/cmor.cgs @@ -0,0 +1,101 @@ +# frv testcase for cmor $FRinti,$FRintj,$FRintk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cmor +cmor: + set_spr_immed 0x1b1b,cccr + + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + set_fr_iimmed 0x5555,0x5555,fr8 + cmor fr7,fr8,fr8,cc0,1 + test_fr_iimmed 0xffffffff,fr8 + + set_fr_iimmed 0x0000,0x0000,fr7 + set_fr_iimmed 0x0000,0x0000,fr8 + cmor fr7,fr8,fr8,cc0,1 + test_fr_iimmed 0x00000000,fr8 + + set_fr_iimmed 0xdead,0x0000,fr7 + set_fr_iimmed 0x0000,0xbeef,fr8 + cmor fr7,fr8,fr8,cc4,1 + test_fr_iimmed 0xdeadbeef,fr8 + + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + set_fr_iimmed 0x5555,0x5555,fr8 + cmor fr7,fr8,fr8,cc1,0 + test_fr_iimmed 0xffffffff,fr8 + + set_fr_iimmed 0x0000,0x0000,fr7 + set_fr_iimmed 0x0000,0x0000,fr8 + cmor fr7,fr8,fr8,cc1,0 + test_fr_iimmed 0x00000000,fr8 + + set_fr_iimmed 0xdead,0x0000,fr7 + set_fr_iimmed 0x0000,0xbeef,fr8 + cmor fr7,fr8,fr8,cc5,0 + test_fr_iimmed 0xdeadbeef,fr8 + + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + set_fr_iimmed 0x5555,0x5555,fr8 + cmor fr7,fr8,fr8,cc0,0 + test_fr_iimmed 0x55555555,fr8 + + set_fr_iimmed 0xdead,0xbeef,fr7 + set_fr_iimmed 0x0000,0x0000,fr8 + cmor fr7,fr8,fr8,cc0,0 + test_fr_iimmed 0x00000000,fr8 + + set_fr_iimmed 0xdead,0x0000,fr7 + set_fr_iimmed 0x0000,0xbeef,fr8 + cmor fr7,fr8,fr8,cc4,0 + test_fr_iimmed 0x0000beef,fr8 + + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + set_fr_iimmed 0x5555,0x5555,fr8 + cmor fr7,fr8,fr8,cc1,1 + test_fr_iimmed 0x55555555,fr8 + + set_fr_iimmed 0xdead,0xbeef,fr7 + set_fr_iimmed 0x0000,0x0000,fr8 + cmor fr7,fr8,fr8,cc1,1 + test_fr_iimmed 0x00000000,fr8 + + set_fr_iimmed 0xdead,0x0000,fr7 + set_fr_iimmed 0x0000,0xbeef,fr8 + cmor fr7,fr8,fr8,cc5,1 + test_fr_iimmed 0x0000beef,fr8 + + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + set_fr_iimmed 0x5555,0x5555,fr8 + cmor fr7,fr8,fr8,cc2,0 + test_fr_iimmed 0x55555555,fr8 + + set_fr_iimmed 0xdead,0xbeef,fr7 + set_fr_iimmed 0x0000,0x0000,fr8 + cmor fr7,fr8,fr8,cc2,1 + test_fr_iimmed 0x00000000,fr8 + + set_fr_iimmed 0xdead,0x0000,fr7 + set_fr_iimmed 0x0000,0xbeef,fr8 + cmor fr7,fr8,fr8,cc6,0 + test_fr_iimmed 0x0000beef,fr8 + + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + set_fr_iimmed 0x5555,0x5555,fr8 + cmor fr7,fr8,fr8,cc3,1 + test_fr_iimmed 0x55555555,fr8 + + set_fr_iimmed 0xdead,0xbeef,fr7 + set_fr_iimmed 0x0000,0x0000,fr8 + cmor fr7,fr8,fr8,cc3,0 + test_fr_iimmed 0x00000000,fr8 + + set_fr_iimmed 0xdead,0x0000,fr7 + set_fr_iimmed 0x0000,0xbeef,fr8 + cmor fr7,fr8,fr8,cc7,1 + test_fr_iimmed 0x0000beef,fr8 + pass diff --git a/sim/testsuite/sim/frv/cmov.cgs b/sim/testsuite/sim/frv/cmov.cgs new file mode 100644 index 0000000..236bb20 --- /dev/null +++ b/sim/testsuite/sim/frv/cmov.cgs @@ -0,0 +1,54 @@ +# frv testcase for cmov $GRi,$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cmov +cmov: + set_spr_immed 0x1b1b,cccr + + set_gr_immed 0x00007fff,gr7 + set_gr_immed 0xdeadbeef,gr8 + set_icc 0x08,0 ; Set mask opposite of expected + cmov gr7,gr8,cc0,0 + test_icc 1 0 0 0 icc0 + test_gr_immed 0xdeadbeef,gr8 + + set_gr_immed 0x00007fff,gr7 + set_gr_immed 0xdeadbeef,gr8 + set_icc 0x08,0 ; Set mask opposite of expected + cmov gr7,gr8,cc0,1 + test_icc 1 0 0 0 icc0 + test_gr_immed 0x00007fff,gr8 + + set_gr_immed 0x00007fff,gr7 + set_gr_immed 0xdeadbeef,gr8 + set_icc 0x08,1 ; Set mask opposite of expected + cmov gr7,gr8,cc1,0 + test_icc 1 0 0 0 icc1 + test_gr_immed 0x00007fff,gr8 + + set_gr_immed 0x00007fff,gr7 + set_gr_immed 0xdeadbeef,gr8 + set_icc 0x08,1 ; Set mask opposite of expected + cmov gr7,gr8,cc1,1 + test_icc 1 0 0 0 icc1 + test_gr_immed 0xdeadbeef,gr8 + + set_gr_immed 0x00007fff,gr7 + set_gr_immed 0xdeadbeef,gr8 + set_icc 0x08,2 ; Set mask opposite of expected + cmov gr7,gr8,cc2,0 + test_icc 1 0 0 0 icc2 + test_gr_immed 0xdeadbeef,gr8 + + set_gr_immed 0x00007fff,gr7 + set_gr_immed 0xdeadbeef,gr8 + set_icc 0x08,3 ; Set mask opposite of expected + cmov gr7,gr8,cc3,0 + test_icc 1 0 0 0 icc3 + test_gr_immed 0xdeadbeef,gr8 + + pass diff --git a/sim/testsuite/sim/frv/cmovfg.cgs b/sim/testsuite/sim/frv/cmovfg.cgs new file mode 100644 index 0000000..4109842 --- /dev/null +++ b/sim/testsuite/sim/frv/cmovfg.cgs @@ -0,0 +1,84 @@ +# frv testcase for cmovfg $FRk,$GRj,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cmovfg +cmovfg: + set_spr_immed 0x1b1b,cccr + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_gr_limmed 0,0,gr8 + cmovfg fr8,gr8,cc0,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_fr_limmed 0xdead,0xbeef,fr8 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_gr_limmed 0,0,gr8 + cmovfg fr8,gr8,cc4,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_fr_limmed 0xdead,0xbeef,fr8 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_gr_limmed 0,0,gr8 + cmovfg fr8,gr8,cc0,0 + test_gr_limmed 0,0,gr8 + test_fr_limmed 0xdead,0xbeef,fr8 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_gr_limmed 0,0,gr8 + cmovfg fr8,gr8,cc4,0 + test_gr_limmed 0,0,gr8 + test_fr_limmed 0xdead,0xbeef,fr8 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_gr_limmed 0,0,gr8 + cmovfg fr8,gr8,cc1,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_fr_limmed 0xdead,0xbeef,fr8 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_gr_limmed 0,0,gr8 + cmovfg fr8,gr8,cc5,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_fr_limmed 0xdead,0xbeef,fr8 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_gr_limmed 0,0,gr8 + cmovfg fr8,gr8,cc1,1 + test_gr_limmed 0,0,gr8 + test_fr_limmed 0xdead,0xbeef,fr8 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_gr_limmed 0,0,gr8 + cmovfg fr8,gr8,cc5,1 + test_gr_limmed 0,0,gr8 + test_fr_limmed 0xdead,0xbeef,fr8 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_gr_limmed 0,0,gr8 + cmovfg fr8,gr8,cc2,0 + test_gr_limmed 0,0,gr8 + test_fr_limmed 0xdead,0xbeef,fr8 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_gr_limmed 0,0,gr8 + cmovfg fr8,gr8,cc2,1 + test_gr_limmed 0,0,gr8 + test_fr_limmed 0xdead,0xbeef,fr8 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_gr_limmed 0,0,gr8 + cmovfg fr8,gr8,cc3,1 + test_gr_limmed 0,0,gr8 + test_fr_limmed 0xdead,0xbeef,fr8 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_gr_limmed 0,0,gr8 + cmovfg fr8,gr8,cc7,0 + test_gr_limmed 0,0,gr8 + test_fr_limmed 0xdead,0xbeef,fr8 + + pass diff --git a/sim/testsuite/sim/frv/cmovfgd.cgs b/sim/testsuite/sim/frv/cmovfgd.cgs new file mode 100644 index 0000000..5d1757d --- /dev/null +++ b/sim/testsuite/sim/frv/cmovfgd.cgs @@ -0,0 +1,132 @@ +# frv testcase for cmovfgd $FRk,$GRj,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cmovfgd +cmovfgd: + set_spr_immed 0x1b1b,cccr + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_gr_limmed 0,0,gr8 + set_gr_limmed 0,0,gr9 + cmovfgd fr8,gr8,cc0,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_gr_limmed 0,0,gr8 + set_gr_limmed 0,0,gr9 + cmovfgd fr8,gr8,cc4,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_gr_limmed 0,0,gr8 + set_gr_limmed 0,0,gr9 + cmovfgd fr8,gr8,cc0,0 + test_gr_limmed 0,0,gr8 + test_gr_limmed 0,0,gr9 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_gr_limmed 0,0,gr8 + set_gr_limmed 0,0,gr9 + cmovfgd fr8,gr8,cc4,0 + test_gr_limmed 0,0,gr8 + test_gr_limmed 0,0,gr9 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_gr_limmed 0,0,gr8 + set_gr_limmed 0,0,gr9 + cmovfgd fr8,gr8,cc1,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_gr_limmed 0,0,gr8 + set_gr_limmed 0,0,gr9 + cmovfgd fr8,gr8,cc5,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_gr_limmed 0,0,gr8 + set_gr_limmed 0,0,gr9 + cmovfgd fr8,gr8,cc1,1 + test_gr_limmed 0,0,gr8 + test_gr_limmed 0,0,gr9 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_gr_limmed 0,0,gr8 + set_gr_limmed 0,0,gr9 + cmovfgd fr8,gr8,cc5,1 + test_gr_limmed 0,0,gr8 + test_gr_limmed 0,0,gr9 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_gr_limmed 0,0,gr8 + set_gr_limmed 0,0,gr9 + cmovfgd fr8,gr8,cc2,0 + test_gr_limmed 0,0,gr8 + test_gr_limmed 0,0,gr9 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_gr_limmed 0,0,gr8 + set_gr_limmed 0,0,gr9 + cmovfgd fr8,gr8,cc6,1 + test_gr_limmed 0,0,gr8 + test_gr_limmed 0,0,gr9 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_gr_limmed 0,0,gr8 + set_gr_limmed 0,0,gr9 + cmovfgd fr8,gr8,cc3,1 + test_gr_limmed 0,0,gr8 + test_gr_limmed 0,0,gr9 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_gr_limmed 0,0,gr8 + set_gr_limmed 0,0,gr9 + cmovfgd fr8,gr8,cc7,0 + test_gr_limmed 0,0,gr8 + test_gr_limmed 0,0,gr9 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + + pass diff --git a/sim/testsuite/sim/frv/cmovgf.cgs b/sim/testsuite/sim/frv/cmovgf.cgs new file mode 100644 index 0000000..58ed1d8 --- /dev/null +++ b/sim/testsuite/sim/frv/cmovgf.cgs @@ -0,0 +1,84 @@ +# frv testcase for cmovgf $GRj,$FRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cmovgf +cmovgf: + set_spr_immed 0x1b1b,cccr + + set_gr_limmed 0xdead,0xbeef,gr8 + set_fr_iimmed 0,0,fr8 + cmovgf gr8,fr8,cc0,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_fr_limmed 0xdead,0xbeef,fr8 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_fr_iimmed 0,0,fr8 + cmovgf gr8,fr8,cc4,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_fr_limmed 0xdead,0xbeef,fr8 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_fr_iimmed 0,0,fr8 + cmovgf gr8,fr8,cc0,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_fr_limmed 0,0,fr8 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_fr_iimmed 0,0,fr8 + cmovgf gr8,fr8,cc4,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_fr_limmed 0,0,fr8 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_fr_iimmed 0,0,fr8 + cmovgf gr8,fr8,cc1,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_fr_limmed 0xdead,0xbeef,fr8 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_fr_iimmed 0,0,fr8 + cmovgf gr8,fr8,cc5,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_fr_limmed 0xdead,0xbeef,fr8 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_fr_iimmed 0,0,fr8 + cmovgf gr8,fr8,cc1,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_fr_limmed 0,0,fr8 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_fr_iimmed 0,0,fr8 + cmovgf gr8,fr8,cc5,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_fr_limmed 0,0,fr8 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_fr_iimmed 0,0,fr8 + cmovgf gr8,fr8,cc2,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_fr_limmed 0,0,fr8 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_fr_iimmed 0,0,fr8 + cmovgf gr8,fr8,cc6,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_fr_limmed 0,0,fr8 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_fr_iimmed 0,0,fr8 + cmovgf gr8,fr8,cc3,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_fr_limmed 0,0,fr8 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_fr_iimmed 0,0,fr8 + cmovgf gr8,fr8,cc7,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_fr_limmed 0,0,fr8 + + pass diff --git a/sim/testsuite/sim/frv/cmovgfd.cgs b/sim/testsuite/sim/frv/cmovgfd.cgs new file mode 100644 index 0000000..67bb272 --- /dev/null +++ b/sim/testsuite/sim/frv/cmovgfd.cgs @@ -0,0 +1,132 @@ +# frv testcase for cmovgfd $GRj,$FRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cmovgfd +cmovgfd: + set_spr_immed 0x1b1b,cccr + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_fr_iimmed 0,0,fr8 + set_fr_iimmed 0,0,fr9 + cmovgfd gr8,fr8,cc0,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_fr_iimmed 0,0,fr8 + set_fr_iimmed 0,0,fr9 + cmovgfd gr8,fr8,cc4,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_fr_iimmed 0,0,fr8 + set_fr_iimmed 0,0,fr9 + cmovgfd gr8,fr8,cc0,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_fr_limmed 0,0,fr8 + test_fr_limmed 0,0,fr9 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_fr_iimmed 0,0,fr8 + set_fr_iimmed 0,0,fr9 + cmovgfd gr8,fr8,cc4,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_fr_limmed 0,0,fr8 + test_fr_limmed 0,0,fr9 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_fr_iimmed 0,0,fr8 + set_fr_iimmed 0,0,fr9 + cmovgfd gr8,fr8,cc1,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_fr_iimmed 0,0,fr8 + set_fr_iimmed 0,0,fr9 + cmovgfd gr8,fr8,cc5,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_fr_iimmed 0,0,fr8 + set_fr_iimmed 0,0,fr9 + cmovgfd gr8,fr8,cc1,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_fr_limmed 0,0,fr8 + test_fr_limmed 0,0,fr9 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_fr_iimmed 0,0,fr8 + set_fr_iimmed 0,0,fr9 + cmovgfd gr8,fr8,cc5,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_fr_limmed 0,0,fr8 + test_fr_limmed 0,0,fr9 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_fr_iimmed 0,0,fr8 + set_fr_iimmed 0,0,fr9 + cmovgfd gr8,fr8,cc2,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_fr_limmed 0,0,fr8 + test_fr_limmed 0,0,fr9 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_fr_iimmed 0,0,fr8 + set_fr_iimmed 0,0,fr9 + cmovgfd gr8,fr8,cc6,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_fr_limmed 0,0,fr8 + test_fr_limmed 0,0,fr9 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_fr_iimmed 0,0,fr8 + set_fr_iimmed 0,0,fr9 + cmovgfd gr8,fr8,cc3,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_fr_limmed 0,0,fr8 + test_fr_limmed 0,0,fr9 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_fr_iimmed 0,0,fr8 + set_fr_iimmed 0,0,fr9 + cmovgfd gr8,fr8,cc7,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_fr_limmed 0,0,fr8 + test_fr_limmed 0,0,fr9 + + pass diff --git a/sim/testsuite/sim/frv/cmp.cgs b/sim/testsuite/sim/frv/cmp.cgs new file mode 100644 index 0000000..e6694c1 --- /dev/null +++ b/sim/testsuite/sim/frv/cmp.cgs @@ -0,0 +1,31 @@ +# frv testcase for cmp $GRi,$GRj,$ICCi_1 +# mach: all + + .include "testutils.inc" + + start + + .global cmp +cmp: + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + cmp gr8,gr7,icc0 + test_icc 0 0 0 0 icc0 + + set_gr_immed 1,gr7 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0d,0 ; Set mask opposite of expected + cmp gr8,gr7,icc0 + test_icc 0 0 1 0 icc0 + + set_icc 0x0b,0 ; Set mask opposite of expected + cmp gr8,gr8,icc0 + test_icc 0 1 0 0 icc0 + + set_gr_immed 0,gr8 + set_icc 0x06,0 ; Set mask opposite of expected + cmp gr8,gr7,icc0 + test_icc 1 0 0 1 icc0 + + pass diff --git a/sim/testsuite/sim/frv/cmpb.cgs b/sim/testsuite/sim/frv/cmpb.cgs new file mode 100644 index 0000000..94b9836 --- /dev/null +++ b/sim/testsuite/sim/frv/cmpb.cgs @@ -0,0 +1,41 @@ +# frv testcase for cmpb $GRi,$GRj,$ICCi_1 +# mach: fr400 fr550 + + .include "testutils.inc" + + start + + .global cmpb +cmpb: + set_gr_limmed 0xdead,0xbeef,gr7 + set_gr_limmed 0xdead,0xbeef,gr8 + set_icc 0x00,0 ; Set mask opposite of expected + cmpb gr7,gr8,icc0 + test_icc 1 1 1 1 icc0 + + set_gr_limmed 0x21ad,0xbeef,gr8 + set_icc 0x08,0 ; Set mask opposite of expected + cmpb gr7,gr8,icc0 + test_icc 0 1 1 1 icc0 + + set_gr_limmed 0xde52,0xbeef,gr8 + set_icc 0x04,0 ; Set mask opposite of expected + cmpb gr7,gr8,icc0 + test_icc 1 0 1 1 icc0 + + set_gr_limmed 0xdead,0x41ef,gr8 + set_icc 0x02,0 ; Set mask opposite of expected + cmpb gr7,gr8,icc0 + test_icc 1 1 0 1 icc0 + + set_gr_limmed 0xdead,0xbe10,gr8 + set_icc 0x01,0 ; Set mask opposite of expected + cmpb gr7,gr8,icc0 + test_icc 1 1 1 0 icc0 + + set_gr_limmed 0xbeef,0xdead,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + cmpb gr7,gr8,icc0 + test_icc 0 0 0 0 icc0 + + pass diff --git a/sim/testsuite/sim/frv/cmpba.cgs b/sim/testsuite/sim/frv/cmpba.cgs new file mode 100644 index 0000000..160b9ef --- /dev/null +++ b/sim/testsuite/sim/frv/cmpba.cgs @@ -0,0 +1,41 @@ +# frv testcase for cmpba $GRi,$GRj,$ICCi_1 +# mach: fr400 fr550 + + .include "testutils.inc" + + start + + .global cmpba +cmpba: + set_gr_limmed 0xdead,0xbeef,gr7 + set_gr_limmed 0xdead,0xbeef,gr8 + set_icc 0x0e,0 ; Set mask opposite of expected + cmpba gr7,gr8,icc0 + test_icc 0 0 0 1 icc0 + + set_gr_limmed 0x21ad,0xbeef,gr8 + set_icc 0x0e,0 ; Set mask opposite of expected + cmpba gr7,gr8,icc0 + test_icc 0 0 0 1 icc0 + + set_gr_limmed 0xde52,0xbeef,gr8 + set_icc 0x0e,0 ; Set mask opposite of expected + cmpba gr7,gr8,icc0 + test_icc 0 0 0 1 icc0 + + set_gr_limmed 0xdead,0x41ef,gr8 + set_icc 0x0e,0 ; Set mask opposite of expected + cmpba gr7,gr8,icc0 + test_icc 0 0 0 1 icc0 + + set_gr_limmed 0xdead,0xbe10,gr8 + set_icc 0x03,0 ; Set mask opposite of expected + cmpba gr7,gr8,icc0 + test_icc 0 0 0 1 icc0 + + set_gr_limmed 0xbeef,0xdead,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + cmpba gr7,gr8,icc0 + test_icc 0 0 0 0 icc0 + + pass diff --git a/sim/testsuite/sim/frv/cmpi.cgs b/sim/testsuite/sim/frv/cmpi.cgs new file mode 100644 index 0000000..a8324db --- /dev/null +++ b/sim/testsuite/sim/frv/cmpi.cgs @@ -0,0 +1,50 @@ +# frv testcase for cmpi $GRi,$s12,$ICCi_1 +# mach: all + + .include "testutils.inc" + + start + + .global cmpi +cmpi: + set_gr_immed 2,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + cmpi gr8,1,icc0 + test_icc 0 0 0 0 icc0 + + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0d,0 ; Set mask opposite of expected + cmpi gr8,1,icc0 + test_icc 0 0 1 0 icc0 + + set_gr_immed 0x1ff,gr8 + set_icc 0x0b,0 ; Set mask opposite of expected + cmpi gr8,0x1ff,icc0 + test_icc 0 1 0 0 icc0 + + set_gr_immed 0,gr8 + set_icc 0x06,0 ; Set mask opposite of expected + cmpi gr8,1,icc0 + test_icc 1 0 0 1 icc0 + + set_gr_immed 2,gr8 + set_icc 0x0e,0 ; Set mask opposite of expected + cmpi gr8,-1,icc0 + test_icc 0 0 0 1 icc0 + + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x06,0 ; Set mask opposite of expected + cmpi gr8,-1,icc0 + test_icc 1 0 0 1 icc0 + + set_gr_immed -512,gr8 + set_icc 0x0b,0 ; Set mask opposite of expected + cmpi gr8,-512,icc0 + test_icc 0 1 0 0 icc0 + + set_gr_immed 0,gr8 + set_icc 0x0e,0 ; Set mask opposite of expected + cmpi gr8,-1,icc0 + test_icc 0 0 0 1 icc0 + + pass diff --git a/sim/testsuite/sim/frv/cmqmachs.cgs b/sim/testsuite/sim/frv/cmqmachs.cgs new file mode 100644 index 0000000..4acd62a --- /dev/null +++ b/sim/testsuite/sim/frv/cmqmachs.cgs @@ -0,0 +1,1268 @@ +# frv testcase for cmqmachs $GRi,$GRj,$ACCk,$CCi,$cond +# mach: frv fr500 fr400 + + .include "testutils.inc" + + start + + .global cmqmachs +cmqmachs: + set_spr_immed 0x1b1b,cccr + + ; Positive operands + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_accg_immed 0,accg0 + set_acc_immed 0,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0,acc2 + set_accg_immed 0,accg3 + set_acc_immed 0,acc3 + set_fr_iimmed 2,3,fr8 ; multiply small numbers + set_fr_iimmed 3,2,fr10 + set_fr_iimmed 0,1,fr9 ; multiply by 0 + set_fr_iimmed 2,0,fr11 + cmqmachs fr8,fr10,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0,acc3 + + set_fr_iimmed 2,1,fr8 ; multiply by 1 + set_fr_iimmed 1,2,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmachs fr8,fr10,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 8,acc0 + test_accg_immed 0,accg1 + test_acc_immed 8,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0,0x7ffe,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0,0x7ffe,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8008,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8008,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x3fff,0x7fff,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x3fff,0x7fff,acc3 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr10 + set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr11 + cmqmachs fr8,fr10,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8002,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8002,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x3fff,0x7ffd,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x3fff,0x7ffd,acc3 + + set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr10 + set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr11 + cmqmachs fr8,fr10,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8002,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8002,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x3fff,0x3ffb,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x3fff,0x3ffb,acc3 + + set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr10 + set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc4,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x0002,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x0002,acc1 + test_accg_immed 0xff,accg2 + test_acc_limmed 0xffff,0xbffb,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0xffff,0xbffb,acc3 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr10 + set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr11 + cmqmachs fr8,fr10,acc0,cc4,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x0008,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x0008,acc1 + test_accg_immed 0xff,accg2 + test_acc_limmed 0xffff,0xbffd,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0xffff,0xbffd,acc3 + + set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmachs fr8,fr10,acc0,cc4,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0009,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fff0009,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0x3fffbffd,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0x3fffbffd,acc3 + + set_accg_immed 0x7f,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0x7f,accg1 + set_acc_immed 0xffffffff,acc1 + set_accg_immed 0x7f,accg2 ; saturation + set_acc_immed 0xffffffff,acc2 + set_accg_immed 0x7f,accg3 + set_acc_immed 0xffffffff,acc3 + set_fr_iimmed 1,1,fr8 + set_fr_iimmed 1,1,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc4,1 + test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + test_accg_immed 0x7f,accg2 + test_acc_limmed 0xffff,0xffff,acc2 + test_accg_immed 0x7f,accg3 + test_acc_limmed 0xffff,0xffff,acc3 + + set_accg_immed 0x80,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed 0x80,accg1 + set_acc_immed 0,acc1 + set_accg_immed 0x80,accg2 ; saturation + set_acc_immed 0,acc2 + set_accg_immed 0x80,accg3 + set_acc_immed 0,acc3 + set_fr_iimmed 0xffff,0,fr8 + set_fr_iimmed 1,0xffff,fr10 + set_fr_iimmed 0x0000,0x8000,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc4,1 + test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x80,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + test_accg_immed 0x80,accg2 + test_acc_immed 0,acc2 + test_accg_immed 0x80,accg3 + test_acc_immed 0,acc3 + + ; Positive operands + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_accg_immed 0,accg0 + set_acc_immed 0,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0,acc2 + set_accg_immed 0,accg3 + set_acc_immed 0,acc3 + set_fr_iimmed 2,3,fr8 ; multiply small numbers + set_fr_iimmed 3,2,fr10 + set_fr_iimmed 0,1,fr9 ; multiply by 0 + set_fr_iimmed 2,0,fr11 + cmqmachs fr8,fr10,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0,acc3 + + set_fr_iimmed 2,1,fr8 ; multiply by 1 + set_fr_iimmed 1,2,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmachs fr8,fr10,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 8,acc0 + test_accg_immed 0,accg1 + test_acc_immed 8,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0,0x7ffe,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0,0x7ffe,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8008,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8008,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x3fff,0x7fff,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x3fff,0x7fff,acc3 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr10 + set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr11 + cmqmachs fr8,fr10,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8002,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8002,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x3fff,0x7ffd,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x3fff,0x7ffd,acc3 + + set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr10 + set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr11 + cmqmachs fr8,fr10,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8002,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8002,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x3fff,0x3ffb,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x3fff,0x3ffb,acc3 + + set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr10 + set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc5,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x0002,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x0002,acc1 + test_accg_immed 0xff,accg2 + test_acc_limmed 0xffff,0xbffb,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0xffff,0xbffb,acc3 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr10 + set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr11 + cmqmachs fr8,fr10,acc0,cc5,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x0008,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x0008,acc1 + test_accg_immed 0xff,accg2 + test_acc_limmed 0xffff,0xbffd,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0xffff,0xbffd,acc3 + + set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmachs fr8,fr10,acc0,cc5,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0009,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fff0009,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0x3fffbffd,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0x3fffbffd,acc3 + + set_accg_immed 0x7f,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0x7f,accg1 + set_acc_immed 0xffffffff,acc1 + set_accg_immed 0x7f,accg2 ; saturation + set_acc_immed 0xffffffff,acc2 + set_accg_immed 0x7f,accg3 + set_acc_immed 0xffffffff,acc3 + set_fr_iimmed 1,1,fr8 + set_fr_iimmed 1,1,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc5,0 + test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + test_accg_immed 0x7f,accg2 + test_acc_limmed 0xffff,0xffff,acc2 + test_accg_immed 0x7f,accg3 + test_acc_limmed 0xffff,0xffff,acc3 + + set_accg_immed 0x80,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed 0x80,accg1 + set_acc_immed 0,acc1 + set_accg_immed 0x80,accg2 ; saturation + set_acc_immed 0,acc2 + set_accg_immed 0x80,accg3 + set_acc_immed 0,acc3 + set_fr_iimmed 0xffff,0,fr8 + set_fr_iimmed 1,0xffff,fr10 + set_fr_iimmed 0x0000,0x8000,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc5,0 + test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x80,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + test_accg_immed 0x80,accg2 + test_acc_immed 0,acc2 + test_accg_immed 0x80,accg3 + test_acc_immed 0,acc3 + + ; Positive operands + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_accg_immed 0x00000033,accg2 + set_acc_immed 0x33333333,acc2 + set_accg_immed 0x00000044,accg3 + set_acc_immed 0x44444444,acc3 + set_fr_iimmed 2,3,fr8 ; multiply small numbers + set_fr_iimmed 3,2,fr10 + set_fr_iimmed 0,1,fr9 ; multiply by 0 + set_fr_iimmed 2,0,fr11 + cmqmachs fr8,fr10,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 2,1,fr8 ; multiply by 1 + set_fr_iimmed 1,2,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmachs fr8,fr10,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr10 + set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr11 + cmqmachs fr8,fr10,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr10 + set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr11 + cmqmachs fr8,fr10,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr10 + set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr10 + set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr11 + cmqmachs fr8,fr10,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmachs fr8,fr10,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_accg_immed 0x7f,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0x7f,accg1 + set_acc_immed 0xffffffff,acc1 + set_accg_immed 0x7f,accg2 ; saturation + set_acc_immed 0xffffffff,acc2 + set_accg_immed 0x7f,accg3 + set_acc_immed 0xffffffff,acc3 + set_fr_iimmed 1,1,fr8 + set_fr_iimmed 1,1,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x7f,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_immed 0xffffffff,acc1 + test_accg_immed 0x7f,accg2 ; saturation + test_acc_immed 0xffffffff,acc2 + test_accg_immed 0x7f,accg3 + test_acc_immed 0xffffffff,acc3 + + set_accg_immed 0x80,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed 0x80,accg1 + set_acc_immed 0,acc1 + set_accg_immed 0x80,accg2 ; saturation + set_acc_immed 0,acc2 + set_accg_immed 0x80,accg3 + set_acc_immed 0,acc3 + set_fr_iimmed 0xffff,0,fr8 + set_fr_iimmed 1,0xffff,fr10 + set_fr_iimmed 0x0000,0x8000,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x80,accg0 ; saturation + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + test_accg_immed 0x80,accg2 ; saturation + test_acc_immed 0,acc2 + test_accg_immed 0x80,accg3 + test_acc_immed 0,acc3 + + ; Positive operands + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_accg_immed 0x00000033,accg2 + set_acc_immed 0x33333333,acc2 + set_accg_immed 0x00000044,accg3 + set_acc_immed 0x44444444,acc3 + set_fr_iimmed 2,3,fr8 ; multiply small numbers + set_fr_iimmed 3,2,fr10 + set_fr_iimmed 0,1,fr9 ; multiply by 0 + set_fr_iimmed 2,0,fr11 + cmqmachs fr8,fr10,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 2,1,fr8 ; multiply by 1 + set_fr_iimmed 1,2,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmachs fr8,fr10,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr10 + set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr11 + cmqmachs fr8,fr10,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr10 + set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr11 + cmqmachs fr8,fr10,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr10 + set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr10 + set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr11 + cmqmachs fr8,fr10,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmachs fr8,fr10,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_accg_immed 0x7f,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0x7f,accg1 + set_acc_immed 0xffffffff,acc1 + set_accg_immed 0x7f,accg2 ; saturation + set_acc_immed 0xffffffff,acc2 + set_accg_immed 0x7f,accg3 + set_acc_immed 0xffffffff,acc3 + set_fr_iimmed 1,1,fr8 + set_fr_iimmed 1,1,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x7f,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_immed 0xffffffff,acc1 + test_accg_immed 0x7f,accg2 ; saturation + test_acc_immed 0xffffffff,acc2 + test_accg_immed 0x7f,accg3 + test_acc_immed 0xffffffff,acc3 + + set_accg_immed 0x80,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed 0x80,accg1 + set_acc_immed 0,acc1 + set_accg_immed 0x80,accg2 ; saturation + set_acc_immed 0,acc2 + set_accg_immed 0x80,accg3 + set_acc_immed 0,acc3 + set_fr_iimmed 0xffff,0,fr8 + set_fr_iimmed 1,0xffff,fr10 + set_fr_iimmed 0x0000,0x8000,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x80,accg0 ; saturation + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + test_accg_immed 0x80,accg2 ; saturation + test_acc_immed 0,acc2 + test_accg_immed 0x80,accg3 + test_acc_immed 0,acc3 + + ; Positive operands + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_accg_immed 0x00000033,accg2 + set_acc_immed 0x33333333,acc2 + set_accg_immed 0x00000044,accg3 + set_acc_immed 0x44444444,acc3 + set_fr_iimmed 2,3,fr8 ; multiply small numbers + set_fr_iimmed 3,2,fr10 + set_fr_iimmed 0,1,fr9 ; multiply by 0 + set_fr_iimmed 2,0,fr11 + cmqmachs fr8,fr10,acc0,cc2,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 2,1,fr8 ; multiply by 1 + set_fr_iimmed 1,2,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmachs fr8,fr10,acc0,cc2,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc2,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr10 + set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr11 + cmqmachs fr8,fr10,acc0,cc2,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr10 + set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr11 + cmqmachs fr8,fr10,acc0,cc2,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr10 + set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc6,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr10 + set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr11 + cmqmachs fr8,fr10,acc0,cc6,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmachs fr8,fr10,acc0,cc6,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_accg_immed 0x7f,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0x7f,accg1 + set_acc_immed 0xffffffff,acc1 + set_accg_immed 0x7f,accg2 ; saturation + set_acc_immed 0xffffffff,acc2 + set_accg_immed 0x7f,accg3 + set_acc_immed 0xffffffff,acc3 + set_fr_iimmed 1,1,fr8 + set_fr_iimmed 1,1,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc6,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x7f,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_immed 0xffffffff,acc1 + test_accg_immed 0x7f,accg2 ; saturation + test_acc_immed 0xffffffff,acc2 + test_accg_immed 0x7f,accg3 + test_acc_immed 0xffffffff,acc3 + + set_accg_immed 0x80,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed 0x80,accg1 + set_acc_immed 0,acc1 + set_accg_immed 0x80,accg2 ; saturation + set_acc_immed 0,acc2 + set_accg_immed 0x80,accg3 + set_acc_immed 0,acc3 + set_fr_iimmed 0xffff,0,fr8 + set_fr_iimmed 1,0xffff,fr10 + set_fr_iimmed 0x0000,0x8000,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc6,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x80,accg0 ; saturation + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + test_accg_immed 0x80,accg2 ; saturation + test_acc_immed 0,acc2 + test_accg_immed 0x80,accg3 + test_acc_immed 0,acc3 +; + ; Positive operands + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_accg_immed 0x00000033,accg2 + set_acc_immed 0x33333333,acc2 + set_accg_immed 0x00000044,accg3 + set_acc_immed 0x44444444,acc3 + set_fr_iimmed 2,3,fr8 ; multiply small numbers + set_fr_iimmed 3,2,fr10 + set_fr_iimmed 0,1,fr9 ; multiply by 0 + set_fr_iimmed 2,0,fr11 + cmqmachs fr8,fr10,acc0,cc3,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 2,1,fr8 ; multiply by 1 + set_fr_iimmed 1,2,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmachs fr8,fr10,acc0,cc3,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc3,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr10 + set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr11 + cmqmachs fr8,fr10,acc0,cc3,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr10 + set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr11 + cmqmachs fr8,fr10,acc0,cc3,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr10 + set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc7,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr10 + set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr11 + cmqmachs fr8,fr10,acc0,cc7,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmachs fr8,fr10,acc0,cc7,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_accg_immed 0x7f,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0x7f,accg1 + set_acc_immed 0xffffffff,acc1 + set_accg_immed 0x7f,accg2 ; saturation + set_acc_immed 0xffffffff,acc2 + set_accg_immed 0x7f,accg3 + set_acc_immed 0xffffffff,acc3 + set_fr_iimmed 1,1,fr8 + set_fr_iimmed 1,1,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc7,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x7f,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_immed 0xffffffff,acc1 + test_accg_immed 0x7f,accg2 ; saturation + test_acc_immed 0xffffffff,acc2 + test_accg_immed 0x7f,accg3 + test_acc_immed 0xffffffff,acc3 + + set_accg_immed 0x80,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed 0x80,accg1 + set_acc_immed 0,acc1 + set_accg_immed 0x80,accg2 ; saturation + set_acc_immed 0,acc2 + set_accg_immed 0x80,accg3 + set_acc_immed 0,acc3 + set_fr_iimmed 0xffff,0,fr8 + set_fr_iimmed 1,0xffff,fr10 + set_fr_iimmed 0x0000,0x8000,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc7,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x80,accg0 ; saturation + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + test_accg_immed 0x80,accg2 ; saturation + test_acc_immed 0,acc2 + test_accg_immed 0x80,accg3 + test_acc_immed 0,acc3 + + pass + + diff --git a/sim/testsuite/sim/frv/cmqmachu.cgs b/sim/testsuite/sim/frv/cmqmachu.cgs new file mode 100644 index 0000000..1be1389 --- /dev/null +++ b/sim/testsuite/sim/frv/cmqmachu.cgs @@ -0,0 +1,876 @@ +# frv testcase for cmqmachu $GRi,$GRj,$GRk,$CCi,$cond +# mach: frv fr500 fr400 + + .include "testutils.inc" + + start + + .global cmqmachu +cmqmachu: + set_spr_immed 0x1b1b,cccr + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_accg_immed 0,accg0 + set_acc_immed 0,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0,acc2 + set_accg_immed 0,accg3 + set_acc_immed 0,acc3 + set_fr_iimmed 3,2,fr8 ; multiply small numbers + set_fr_iimmed 2,3,fr10 + set_fr_iimmed 1,2,fr9 ; multiply by 1 + set_fr_iimmed 2,1,fr11 + cmqmachu fr8,fr10,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + test_accg_immed 0,accg2 + test_acc_immed 2,acc2 + test_accg_immed 0,accg3 + test_acc_immed 2,acc3 + + set_fr_iimmed 0,2,fr8 ; multiply by 0 + set_fr_iimmed 2,0,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmachu fr8,fr10,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x8000,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x8000,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x8000,2,fr9 ; 17 bit result + set_fr_iimmed 2,0x8000,fr11 + cmqmachu fr8,fr10,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8006,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8006,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0x00018000,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0x00018000,acc3 + + set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmachu fr8,fr10,acc0,cc4,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0x3fff8007,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fff8007,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x4001,0x8000,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x4001,0x8000,acc3 + + set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr11 + cmqmachu fr8,fr10,acc0,cc4,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 1,accg0 + test_acc_limmed 0x3ffd,0x8008,acc0 + test_accg_immed 1,accg1 + test_acc_limmed 0x3ffd,0x8008,acc1 + test_accg_immed 1,accg2 + test_acc_limmed 0x3fff,0x8001,acc2 + test_accg_immed 1,accg3 + test_acc_limmed 0x3fff,0x8001,acc3 + + set_accg_immed 0xff,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xffffffff,acc1 + set_accg_immed 0xff,accg2 ; saturation + set_acc_immed 0xffffffff,acc2 + set_accg_immed 0xff,accg3 + set_acc_immed 0xffffffff,acc3 + set_fr_iimmed 1,1,fr8 + set_fr_iimmed 1,1,fr10 + set_fr_iimmed 1,1,fr9 + set_fr_iimmed 1,1,fr11 + cmqmachu fr8,fr10,acc0,cc4,1 + test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + test_accg_immed 0xff,accg2 + test_acc_limmed 0xffff,0xffff,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0xffff,0xffff,acc3 + + set_fr_iimmed 0xffff,0x0000,fr8 + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0x0000,0xffff,fr9 + set_fr_iimmed 0xffff,0xffff,fr11 + cmqmachu fr8,fr10,acc0,cc4,1 + test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + test_accg_immed 0xff,accg2 + test_acc_limmed 0xffff,0xffff,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0xffff,0xffff,acc3 + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_accg_immed 0,accg0 + set_acc_immed 0,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0,acc2 + set_accg_immed 0,accg3 + set_acc_immed 0,acc3 + set_fr_iimmed 3,2,fr8 ; multiply small numbers + set_fr_iimmed 2,3,fr10 + set_fr_iimmed 1,2,fr9 ; multiply by 1 + set_fr_iimmed 2,1,fr11 + cmqmachu fr8,fr10,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + test_accg_immed 0,accg2 + test_acc_immed 2,acc2 + test_accg_immed 0,accg3 + test_acc_immed 2,acc3 + + set_fr_iimmed 0,2,fr8 ; multiply by 0 + set_fr_iimmed 2,0,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmachu fr8,fr10,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x8000,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x8000,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x8000,2,fr9 ; 17 bit result + set_fr_iimmed 2,0x8000,fr11 + cmqmachu fr8,fr10,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8006,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8006,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0x00018000,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0x00018000,acc3 + + set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmachu fr8,fr10,acc0,cc5,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0x3fff8007,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fff8007,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x4001,0x8000,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x4001,0x8000,acc3 + + set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr11 + cmqmachu fr8,fr10,acc0,cc5,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 1,accg0 + test_acc_limmed 0x3ffd,0x8008,acc0 + test_accg_immed 1,accg1 + test_acc_limmed 0x3ffd,0x8008,acc1 + test_accg_immed 1,accg2 + test_acc_limmed 0x3fff,0x8001,acc2 + test_accg_immed 1,accg3 + test_acc_limmed 0x3fff,0x8001,acc3 + + set_accg_immed 0xff,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xffffffff,acc1 + set_accg_immed 0xff,accg2 ; saturation + set_acc_immed 0xffffffff,acc2 + set_accg_immed 0xff,accg3 + set_acc_immed 0xffffffff,acc3 + set_fr_iimmed 1,1,fr8 + set_fr_iimmed 1,1,fr10 + set_fr_iimmed 1,1,fr9 + set_fr_iimmed 1,1,fr11 + cmqmachu fr8,fr10,acc0,cc5,0 + test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + test_accg_immed 0xff,accg2 + test_acc_limmed 0xffff,0xffff,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0xffff,0xffff,acc3 + + set_fr_iimmed 0xffff,0x0000,fr8 + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0x0000,0xffff,fr9 + set_fr_iimmed 0xffff,0xffff,fr11 + cmqmachu fr8,fr10,acc0,cc5,0 + test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + test_accg_immed 0xff,accg2 + test_acc_limmed 0xffff,0xffff,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0xffff,0xffff,acc3 + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_accg_immed 0x00000033,accg2 + set_acc_immed 0x33333333,acc2 + set_accg_immed 0x00000044,accg3 + set_acc_immed 0x44444444,acc3 + set_fr_iimmed 3,2,fr8 ; multiply small numbers + set_fr_iimmed 2,3,fr10 + set_fr_iimmed 1,2,fr9 ; multiply by 1 + set_fr_iimmed 2,1,fr11 + cmqmachu fr8,fr10,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0,2,fr8 ; multiply by 0 + set_fr_iimmed 2,0,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmachu fr8,fr10,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x8000,2,fr9 ; 17 bit result + set_fr_iimmed 2,0x8000,fr11 + cmqmachu fr8,fr10,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmachu fr8,fr10,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr11 + cmqmachu fr8,fr10,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_accg_immed 0xff,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xffffffff,acc1 + set_accg_immed 0xff,accg2 ; saturation + set_acc_immed 0xffffffff,acc2 + set_accg_immed 0xff,accg3 + set_acc_immed 0xffffffff,acc3 + set_fr_iimmed 1,1,fr8 + set_fr_iimmed 1,1,fr10 + set_fr_iimmed 1,1,fr9 + set_fr_iimmed 1,1,fr11 + cmqmachu fr8,fr10,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed 0xffffffff,acc1 + test_accg_immed 0xff,accg2 ; saturation + test_acc_immed 0xffffffff,acc2 + test_accg_immed 0xff,accg3 + test_acc_immed 0xffffffff,acc3 + + set_fr_iimmed 0xffff,0x0000,fr8 + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0x0000,0xffff,fr9 + set_fr_iimmed 0xffff,0xffff,fr11 + cmqmachu fr8,fr10,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed 0xffffffff,acc1 + test_accg_immed 0xff,accg2 ; saturation + test_acc_immed 0xffffffff,acc2 + test_accg_immed 0xff,accg3 + test_acc_immed 0xffffffff,acc3 + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_accg_immed 0x00000033,accg2 + set_acc_immed 0x33333333,acc2 + set_accg_immed 0x00000044,accg3 + set_acc_immed 0x44444444,acc3 + set_fr_iimmed 3,2,fr8 ; multiply small numbers + set_fr_iimmed 2,3,fr10 + set_fr_iimmed 1,2,fr9 ; multiply by 1 + set_fr_iimmed 2,1,fr11 + cmqmachu fr8,fr10,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0,2,fr8 ; multiply by 0 + set_fr_iimmed 2,0,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmachu fr8,fr10,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x8000,2,fr9 ; 17 bit result + set_fr_iimmed 2,0x8000,fr11 + cmqmachu fr8,fr10,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmachu fr8,fr10,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr11 + cmqmachu fr8,fr10,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_accg_immed 0xff,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xffffffff,acc1 + set_accg_immed 0xff,accg2 ; saturation + set_acc_immed 0xffffffff,acc2 + set_accg_immed 0xff,accg3 + set_acc_immed 0xffffffff,acc3 + set_fr_iimmed 1,1,fr8 + set_fr_iimmed 1,1,fr10 + set_fr_iimmed 1,1,fr9 + set_fr_iimmed 1,1,fr11 + cmqmachu fr8,fr10,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed 0xffffffff,acc1 + test_accg_immed 0xff,accg2 ; saturation + test_acc_immed 0xffffffff,acc2 + test_accg_immed 0xff,accg3 + test_acc_immed 0xffffffff,acc3 + + set_fr_iimmed 0xffff,0x0000,fr8 + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0x0000,0xffff,fr9 + set_fr_iimmed 0xffff,0xffff,fr11 + cmqmachu fr8,fr10,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed 0xffffffff,acc1 + test_accg_immed 0xff,accg2 ; saturation + test_acc_immed 0xffffffff,acc2 + test_accg_immed 0xff,accg3 + test_acc_immed 0xffffffff,acc3 + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_accg_immed 0x00000033,accg2 + set_acc_immed 0x33333333,acc2 + set_accg_immed 0x00000044,accg3 + set_acc_immed 0x44444444,acc3 + set_fr_iimmed 3,2,fr8 ; multiply small numbers + set_fr_iimmed 2,3,fr10 + set_fr_iimmed 1,2,fr9 ; multiply by 1 + set_fr_iimmed 2,1,fr11 + cmqmachu fr8,fr10,acc0,cc2,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0,2,fr8 ; multiply by 0 + set_fr_iimmed 2,0,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmachu fr8,fr10,acc0,cc2,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x8000,2,fr9 ; 17 bit result + set_fr_iimmed 2,0x8000,fr11 + cmqmachu fr8,fr10,acc0,cc2,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmachu fr8,fr10,acc0,cc6,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr11 + cmqmachu fr8,fr10,acc0,cc6,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_accg_immed 0xff,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xffffffff,acc1 + set_accg_immed 0xff,accg2 ; saturation + set_acc_immed 0xffffffff,acc2 + set_accg_immed 0xff,accg3 + set_acc_immed 0xffffffff,acc3 + set_fr_iimmed 1,1,fr8 + set_fr_iimmed 1,1,fr10 + set_fr_iimmed 1,1,fr9 + set_fr_iimmed 1,1,fr11 + cmqmachu fr8,fr10,acc0,cc6,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed 0xffffffff,acc1 + test_accg_immed 0xff,accg2 ; saturation + test_acc_immed 0xffffffff,acc2 + test_accg_immed 0xff,accg3 + test_acc_immed 0xffffffff,acc3 + + set_fr_iimmed 0xffff,0x0000,fr8 + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0x0000,0xffff,fr9 + set_fr_iimmed 0xffff,0xffff,fr11 + cmqmachu fr8,fr10,acc0,cc6,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed 0xffffffff,acc1 + test_accg_immed 0xff,accg2 ; saturation + test_acc_immed 0xffffffff,acc2 + test_accg_immed 0xff,accg3 + test_acc_immed 0xffffffff,acc3 +; + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_accg_immed 0x00000033,accg2 + set_acc_immed 0x33333333,acc2 + set_accg_immed 0x00000044,accg3 + set_acc_immed 0x44444444,acc3 + set_fr_iimmed 3,2,fr8 ; multiply small numbers + set_fr_iimmed 2,3,fr10 + set_fr_iimmed 1,2,fr9 ; multiply by 1 + set_fr_iimmed 2,1,fr11 + cmqmachu fr8,fr10,acc0,cc3,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0,2,fr8 ; multiply by 0 + set_fr_iimmed 2,0,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmachu fr8,fr10,acc0,cc3,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x8000,2,fr9 ; 17 bit result + set_fr_iimmed 2,0x8000,fr11 + cmqmachu fr8,fr10,acc0,cc3,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmachu fr8,fr10,acc0,cc7,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr11 + cmqmachu fr8,fr10,acc0,cc7,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_accg_immed 0xff,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xffffffff,acc1 + set_accg_immed 0xff,accg2 ; saturation + set_acc_immed 0xffffffff,acc2 + set_accg_immed 0xff,accg3 + set_acc_immed 0xffffffff,acc3 + set_fr_iimmed 1,1,fr8 + set_fr_iimmed 1,1,fr10 + set_fr_iimmed 1,1,fr9 + set_fr_iimmed 1,1,fr11 + cmqmachu fr8,fr10,acc0,cc7,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed 0xffffffff,acc1 + test_accg_immed 0xff,accg2 ; saturation + test_acc_immed 0xffffffff,acc2 + test_accg_immed 0xff,accg3 + test_acc_immed 0xffffffff,acc3 + + set_fr_iimmed 0xffff,0x0000,fr8 + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0x0000,0xffff,fr9 + set_fr_iimmed 0xffff,0xffff,fr11 + cmqmachu fr8,fr10,acc0,cc7,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed 0xffffffff,acc1 + test_accg_immed 0xff,accg2 ; saturation + test_acc_immed 0xffffffff,acc2 + test_accg_immed 0xff,accg3 + test_acc_immed 0xffffffff,acc3 + + pass diff --git a/sim/testsuite/sim/frv/cmqmulhs.cgs b/sim/testsuite/sim/frv/cmqmulhs.cgs new file mode 100644 index 0000000..b315737 --- /dev/null +++ b/sim/testsuite/sim/frv/cmqmulhs.cgs @@ -0,0 +1,734 @@ +# frv testcase for cmqmulhs $GRi,$GRj,$ACCk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cmqmulhs +cmqmulhs: + set_spr_immed 0x1b1b,cccr + + ; Positive operands + set_fr_iimmed 2,3,fr8 ; multiply small numbers + set_fr_iimmed 3,2,fr10 + set_fr_iimmed 0,1,fr9 ; multiply by 0 + set_fr_iimmed 2,0,fr11 + cmqmulhs fr8,fr10,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0,acc3 + + set_fr_iimmed 2,1,fr8 ; multiply by 1 + set_fr_iimmed 1,2,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmulhs fr8,fr10,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_immed 2,acc0 + test_accg_immed 0,accg1 + test_acc_immed 2,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0,0x7ffe,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0,0x7ffe,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmulhs fr8,fr10,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8000,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8000,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x3fff,0x0001,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x3fff,0x0001,acc3 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr10 + set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr11 + cmqmulhs fr8,fr10,acc0,cc0,1 + test_accg_immed 0xff,accg0 + test_acc_immed -6,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed -6,acc1 + test_accg_immed 0xff,accg2 + test_acc_immed -2,acc2 + test_accg_immed 0xff,accg3 + test_acc_immed -2,acc3 + + set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr10 + set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr11 + cmqmulhs fr8,fr10,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + test_accg_immed 0xff,accg2 + test_acc_limmed 0xffff,0xbffe,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0xffff,0xbffe,acc3 + + set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr10 + set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr11 + cmqmulhs fr8,fr10,acc0,cc4,1 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0x8000,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0x8000,acc1 + test_accg_immed 0xff,accg2 + test_acc_limmed 0xc000,0x8000,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0xc000,0x8000,acc3 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr10 + set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr11 + cmqmulhs fr8,fr10,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + test_accg_immed 0,accg2 + test_acc_immed 2,acc2 + test_accg_immed 0,accg3 + test_acc_immed 2,acc3 + + set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmulhs fr8,fr10,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fff0001,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0x40000000,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0x40000000,acc3 + + ; Positive operands + set_fr_iimmed 2,3,fr8 ; multiply small numbers + set_fr_iimmed 3,2,fr10 + set_fr_iimmed 0,1,fr9 ; multiply by 0 + set_fr_iimmed 2,0,fr11 + cmqmulhs fr8,fr10,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0,acc3 + + set_fr_iimmed 2,1,fr8 ; multiply by 1 + set_fr_iimmed 1,2,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmulhs fr8,fr10,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_immed 2,acc0 + test_accg_immed 0,accg1 + test_acc_immed 2,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0,0x7ffe,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0,0x7ffe,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmulhs fr8,fr10,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8000,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8000,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x3fff,0x0001,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x3fff,0x0001,acc3 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr10 + set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr11 + cmqmulhs fr8,fr10,acc0,cc1,0 + test_accg_immed 0xff,accg0 + test_acc_immed -6,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed -6,acc1 + test_accg_immed 0xff,accg2 + test_acc_immed -2,acc2 + test_accg_immed 0xff,accg3 + test_acc_immed -2,acc3 + + set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr10 + set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr11 + cmqmulhs fr8,fr10,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + test_accg_immed 0xff,accg2 + test_acc_limmed 0xffff,0xbffe,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0xffff,0xbffe,acc3 + + set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr10 + set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr11 + cmqmulhs fr8,fr10,acc0,cc5,0 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0x8000,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0x8000,acc1 + test_accg_immed 0xff,accg2 + test_acc_limmed 0xc000,0x8000,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0xc000,0x8000,acc3 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr10 + set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr11 + cmqmulhs fr8,fr10,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + test_accg_immed 0,accg2 + test_acc_immed 2,acc2 + test_accg_immed 0,accg3 + test_acc_immed 2,acc3 + + set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmulhs fr8,fr10,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fff0001,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0x40000000,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0x40000000,acc3 + + ; Positive operands + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_accg_immed 0x00000033,accg2 + set_acc_immed 0x33333333,acc2 + set_accg_immed 0x00000044,accg3 + set_acc_immed 0x44444444,acc3 + set_fr_iimmed 2,3,fr8 ; multiply small numbers + set_fr_iimmed 3,2,fr10 + set_fr_iimmed 0,1,fr9 ; multiply by 0 + set_fr_iimmed 2,0,fr11 + cmqmulhs fr8,fr10,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 2,1,fr8 ; multiply by 1 + set_fr_iimmed 1,2,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmulhs fr8,fr10,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmulhs fr8,fr10,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr10 + set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr11 + cmqmulhs fr8,fr10,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr10 + set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr11 + cmqmulhs fr8,fr10,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr10 + set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr11 + cmqmulhs fr8,fr10,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr10 + set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr11 + cmqmulhs fr8,fr10,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmulhs fr8,fr10,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + ; Positive operands + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_accg_immed 0x00000033,accg2 + set_acc_immed 0x33333333,acc2 + set_accg_immed 0x00000044,accg3 + set_acc_immed 0x44444444,acc3 + set_fr_iimmed 2,3,fr8 ; multiply small numbers + set_fr_iimmed 3,2,fr10 + set_fr_iimmed 0,1,fr9 ; multiply by 0 + set_fr_iimmed 2,0,fr11 + cmqmulhs fr8,fr10,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 2,1,fr8 ; multiply by 1 + set_fr_iimmed 1,2,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmulhs fr8,fr10,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmulhs fr8,fr10,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr10 + set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr11 + cmqmulhs fr8,fr10,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr10 + set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr11 + cmqmulhs fr8,fr10,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr10 + set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr11 + cmqmulhs fr8,fr10,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr10 + set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr11 + cmqmulhs fr8,fr10,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmulhs fr8,fr10,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + ; Positive operands + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_accg_immed 0x00000033,accg2 + set_acc_immed 0x33333333,acc2 + set_accg_immed 0x00000044,accg3 + set_acc_immed 0x44444444,acc3 + set_fr_iimmed 2,3,fr8 ; multiply small numbers + set_fr_iimmed 3,2,fr10 + set_fr_iimmed 0,1,fr9 ; multiply by 0 + set_fr_iimmed 2,0,fr11 + cmqmulhs fr8,fr10,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 2,1,fr8 ; multiply by 1 + set_fr_iimmed 1,2,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmulhs fr8,fr10,acc0,cc2,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmulhs fr8,fr10,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr10 + set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr11 + cmqmulhs fr8,fr10,acc0,cc2,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr10 + set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr11 + cmqmulhs fr8,fr10,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr10 + set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr11 + cmqmulhs fr8,fr10,acc0,cc6,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr10 + set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr11 + cmqmulhs fr8,fr10,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmulhs fr8,fr10,acc0,cc6,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 +; + ; Positive operands + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_accg_immed 0x00000033,accg2 + set_acc_immed 0x33333333,acc2 + set_accg_immed 0x00000044,accg3 + set_acc_immed 0x44444444,acc3 + set_fr_iimmed 2,3,fr8 ; multiply small numbers + set_fr_iimmed 3,2,fr10 + set_fr_iimmed 0,1,fr9 ; multiply by 0 + set_fr_iimmed 2,0,fr11 + cmqmulhs fr8,fr10,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 2,1,fr8 ; multiply by 1 + set_fr_iimmed 1,2,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmulhs fr8,fr10,acc0,cc3,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmulhs fr8,fr10,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr10 + set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr11 + cmqmulhs fr8,fr10,acc0,cc3,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr10 + set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr11 + cmqmulhs fr8,fr10,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr10 + set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr11 + cmqmulhs fr8,fr10,acc0,cc7,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr10 + set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr11 + cmqmulhs fr8,fr10,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmulhs fr8,fr10,acc0,cc7,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + pass diff --git a/sim/testsuite/sim/frv/cmqmulhu.cgs b/sim/testsuite/sim/frv/cmqmulhu.cgs new file mode 100644 index 0000000..36f0c2f --- /dev/null +++ b/sim/testsuite/sim/frv/cmqmulhu.cgs @@ -0,0 +1,464 @@ +# frv testcase for cmqmulhu $GRi,$GRj,$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cmqmulhu +cmqmulhu: + set_spr_immed 0x1b1b,cccr + + set_fr_iimmed 3,2,fr8 ; multiply small numbers + set_fr_iimmed 2,3,fr10 + set_fr_iimmed 1,2,fr9 ; multiply by 1 + set_fr_iimmed 2,1,fr11 + cmqmulhu fr8,fr10,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + test_accg_immed 0,accg2 + test_acc_immed 2,acc2 + test_accg_immed 0,accg3 + test_acc_immed 2,acc3 + + set_fr_iimmed 0,2,fr8 ; multiply by 0 + set_fr_iimmed 2,0,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmulhu fr8,fr10,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x7ffe,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x7ffe,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x8000,2,fr9 ; 17 bit result + set_fr_iimmed 2,0x8000,fr11 + cmqmulhu fr8,fr10,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8000,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8000,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0x00010000,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0x00010000,acc3 + + set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmulhu fr8,fr10,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fff0001,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x4000,0x0000,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x4000,0x0000,acc3 + + set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr11 + cmqmulhu fr8,fr10,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_limmed 0xfffe,0x0001,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0xfffe,0x0001,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0xfffe,0x0001,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0xfffe,0x0001,acc3 + + set_fr_iimmed 3,2,fr8 ; multiply small numbers + set_fr_iimmed 2,3,fr10 + set_fr_iimmed 1,2,fr9 ; multiply by 1 + set_fr_iimmed 2,1,fr11 + cmqmulhu fr8,fr10,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + test_accg_immed 0,accg2 + test_acc_immed 2,acc2 + test_accg_immed 0,accg3 + test_acc_immed 2,acc3 + + set_fr_iimmed 0,2,fr8 ; multiply by 0 + set_fr_iimmed 2,0,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmulhu fr8,fr10,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x7ffe,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x7ffe,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x8000,2,fr9 ; 17 bit result + set_fr_iimmed 2,0x8000,fr11 + cmqmulhu fr8,fr10,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8000,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8000,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0x00010000,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0x00010000,acc3 + + set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmulhu fr8,fr10,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fff0001,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x4000,0x0000,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x4000,0x0000,acc3 + + set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr11 + cmqmulhu fr8,fr10,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_limmed 0xfffe,0x0001,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0xfffe,0x0001,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0xfffe,0x0001,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0xfffe,0x0001,acc3 + + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_accg_immed 0x00000033,accg2 + set_acc_immed 0x33333333,acc2 + set_accg_immed 0x00000044,accg3 + set_acc_immed 0x44444444,acc3 + set_fr_iimmed 3,2,fr8 ; multiply small numbers + set_fr_iimmed 2,3,fr10 + set_fr_iimmed 1,2,fr9 ; multiply by 1 + set_fr_iimmed 2,1,fr11 + cmqmulhu fr8,fr10,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0,2,fr8 ; multiply by 0 + set_fr_iimmed 2,0,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmulhu fr8,fr10,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x8000,2,fr9 ; 17 bit result + set_fr_iimmed 2,0x8000,fr11 + cmqmulhu fr8,fr10,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmulhu fr8,fr10,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr11 + cmqmulhu fr8,fr10,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_accg_immed 0x00000033,accg2 + set_acc_immed 0x33333333,acc2 + set_accg_immed 0x00000044,accg3 + set_acc_immed 0x44444444,acc3 + set_fr_iimmed 3,2,fr8 ; multiply small numbers + set_fr_iimmed 2,3,fr10 + set_fr_iimmed 1,2,fr9 ; multiply by 1 + set_fr_iimmed 2,1,fr11 + cmqmulhu fr8,fr10,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0,2,fr8 ; multiply by 0 + set_fr_iimmed 2,0,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmulhu fr8,fr10,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x8000,2,fr9 ; 17 bit result + set_fr_iimmed 2,0x8000,fr11 + cmqmulhu fr8,fr10,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmulhu fr8,fr10,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr11 + cmqmulhu fr8,fr10,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_accg_immed 0x00000033,accg2 + set_acc_immed 0x33333333,acc2 + set_accg_immed 0x00000044,accg3 + set_acc_immed 0x44444444,acc3 + set_fr_iimmed 3,2,fr8 ; multiply small numbers + set_fr_iimmed 2,3,fr10 + set_fr_iimmed 1,2,fr9 ; multiply by 1 + set_fr_iimmed 2,1,fr11 + cmqmulhu fr8,fr10,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0,2,fr8 ; multiply by 0 + set_fr_iimmed 2,0,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmulhu fr8,fr10,acc0,cc2,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x8000,2,fr9 ; 17 bit result + set_fr_iimmed 2,0x8000,fr11 + cmqmulhu fr8,fr10,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmulhu fr8,fr10,acc0,cc6,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr11 + cmqmulhu fr8,fr10,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 +; + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_accg_immed 0x00000033,accg2 + set_acc_immed 0x33333333,acc2 + set_accg_immed 0x00000044,accg3 + set_acc_immed 0x44444444,acc3 + set_fr_iimmed 3,2,fr8 ; multiply small numbers + set_fr_iimmed 2,3,fr10 + set_fr_iimmed 1,2,fr9 ; multiply by 1 + set_fr_iimmed 2,1,fr11 + cmqmulhu fr8,fr10,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0,2,fr8 ; multiply by 0 + set_fr_iimmed 2,0,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmulhu fr8,fr10,acc0,cc3,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x8000,2,fr9 ; 17 bit result + set_fr_iimmed 2,0x8000,fr11 + cmqmulhu fr8,fr10,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmulhu fr8,fr10,acc0,cc7,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr11 + cmqmulhu fr8,fr10,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + pass diff --git a/sim/testsuite/sim/frv/cmsubhss.cgs b/sim/testsuite/sim/frv/cmsubhss.cgs new file mode 100644 index 0000000..386b27d --- /dev/null +++ b/sim/testsuite/sim/frv/cmsubhss.cgs @@ -0,0 +1,562 @@ +# frv testcase for cmsubhss $FRi,$FRj,$FRj,$CCi,$cond +# mach: frv fr500 fr400 + + .include "testutils.inc" + + start + + .global cmsubhss +cmsubhss: + set_spr_immed 0x1b1b,cccr + + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmsubhss fr10,fr11,fr12,cc0,1 + test_fr_limmed 0x0000,0x0000,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + cmsubhss fr10,fr11,fr12,cc0,1 + test_fr_limmed 0xdead,0x4111,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + cmsubhss fr10,fr11,fr12,cc0,1 + test_fr_limmed 0x4111,0xdead,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmsubhss fr10,fr11,fr12,cc0,1 + test_fr_limmed 0x0123,0x4567,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + cmsubhss fr10,fr11,fr12,cc0,1 + test_fr_limmed 0x1235,0x5679,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0xfffe,0xffff,fr11 + cmsubhss fr10,fr11,fr12,cc4,1 + test_fr_limmed 0x7fff,0x7fff,fr12 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + cmsubhss fr10,fr11,fr12,cc4,1 + test_fr_limmed 0x8000,0x8000,fr12 + test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmsubhss fr10,fr11,fr12,cc4,1 + test_fr_limmed 0x8000,0x8000,fr12 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + cmsubhss.p fr10,fr10,fr12,cc4,1 + cmsubhss fr11,fr10,fr13,cc4,1 + test_fr_limmed 0x0000,0x0000,fr12 + test_fr_limmed 0x8000,0x8000,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 0x3c,2,0xc,msr1 ; msr0.sie is set + test_spr_bits 2,1,1,msr1 ; msr1.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmsubhss fr10,fr11,fr12,cc1,0 + test_fr_limmed 0x0000,0x0000,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + cmsubhss fr10,fr11,fr12,cc1,0 + test_fr_limmed 0xdead,0x4111,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + cmsubhss fr10,fr11,fr12,cc1,0 + test_fr_limmed 0x4111,0xdead,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmsubhss fr10,fr11,fr12,cc1,0 + test_fr_limmed 0x0123,0x4567,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + cmsubhss fr10,fr11,fr12,cc1,0 + test_fr_limmed 0x1235,0x5679,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0xfffe,0xffff,fr11 + cmsubhss fr10,fr11,fr12,cc5,0 + test_fr_limmed 0x7fff,0x7fff,fr12 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + cmsubhss fr10,fr11,fr12,cc5,0 + test_fr_limmed 0x8000,0x8000,fr12 + test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmsubhss fr10,fr11,fr12,cc5,0 + test_fr_limmed 0x8000,0x8000,fr12 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + cmsubhss.p fr10,fr10,fr12,cc5,0 + cmsubhss fr11,fr10,fr13,cc5,0 + test_fr_limmed 0x0000,0x0000,fr12 + test_fr_limmed 0x8000,0x8000,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 0x3c,2,0xc,msr1 ; msr0.sie is set + test_spr_bits 2,1,1,msr1 ; msr1.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_fr_iimmed 0xdead,0xbeef,fr12 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmsubhss fr10,fr11,fr12,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + cmsubhss fr10,fr11,fr12,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + cmsubhss fr10,fr11,fr12,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmsubhss fr10,fr11,fr12,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + cmsubhss fr10,fr11,fr12,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0xfffe,0xffff,fr11 + cmsubhss fr10,fr11,fr12,cc4,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + cmsubhss fr10,fr11,fr12,cc4,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmsubhss fr10,fr11,fr12,cc4,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xbeef,0xdead,fr13 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + cmsubhss.p fr10,fr10,fr12,cc4,0 + cmsubhss fr11,fr10,fr13,cc4,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_fr_limmed 0xbeef,0xdead,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xdead,0xbeef,fr12 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmsubhss fr10,fr11,fr12,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + cmsubhss fr10,fr11,fr12,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + cmsubhss fr10,fr11,fr12,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmsubhss fr10,fr11,fr12,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + cmsubhss fr10,fr11,fr12,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0xfffe,0xffff,fr11 + cmsubhss fr10,fr11,fr12,cc5,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + cmsubhss fr10,fr11,fr12,cc5,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmsubhss fr10,fr11,fr12,cc5,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xbeef,0xdead,fr13 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + cmsubhss.p fr10,fr10,fr12,cc5,1 + cmsubhss fr11,fr10,fr13,cc5,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_fr_limmed 0xbeef,0xdead,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xdead,0xbeef,fr12 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmsubhss fr10,fr11,fr12,cc2,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + cmsubhss fr10,fr11,fr12,cc2,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + cmsubhss fr10,fr11,fr12,cc2,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmsubhss fr10,fr11,fr12,cc2,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + cmsubhss fr10,fr11,fr12,cc2,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0xfffe,0xffff,fr11 + cmsubhss fr10,fr11,fr12,cc6,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + cmsubhss fr10,fr11,fr12,cc6,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmsubhss fr10,fr11,fr12,cc6,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xbeef,0xdead,fr13 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + cmsubhss.p fr10,fr10,fr12,cc6,1 + cmsubhss fr11,fr10,fr13,cc6,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_fr_limmed 0xbeef,0xdead,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set +; + set_fr_iimmed 0xdead,0xbeef,fr12 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmsubhss fr10,fr11,fr12,cc3,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + cmsubhss fr10,fr11,fr12,cc3,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + cmsubhss fr10,fr11,fr12,cc3,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmsubhss fr10,fr11,fr12,cc3,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + cmsubhss fr10,fr11,fr12,cc3,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0xfffe,0xffff,fr11 + cmsubhss fr10,fr11,fr12,cc7,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + cmsubhss fr10,fr11,fr12,cc7,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmsubhss fr10,fr11,fr12,cc7,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xbeef,0xdead,fr13 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + cmsubhss.p fr10,fr10,fr12,cc7,1 + cmsubhss fr11,fr10,fr13,cc7,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_fr_limmed 0xbeef,0xdead,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + pass diff --git a/sim/testsuite/sim/frv/cmsubhus.cgs b/sim/testsuite/sim/frv/cmsubhus.cgs new file mode 100644 index 0000000..2a8f343 --- /dev/null +++ b/sim/testsuite/sim/frv/cmsubhus.cgs @@ -0,0 +1,442 @@ +# frv testcase for cmsubhus $FRi,$FRj,$FRj,$CCi,$cond +# mach: frv fr500 fr400 + + .include "testutils.inc" + + start + + .global cmsubhus +cmsubhus: + set_spr_immed 0x1b1b,cccr + + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmsubhus fr10,fr11,fr12,cc0,1 + test_fr_limmed 0x0000,0x0000,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xdead,0xbeef,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmsubhus fr10,fr11,fr12,cc0,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmsubhus fr10,fr11,fr12,cc0,1 + test_fr_limmed 0x0123,0x4567,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmsubhus fr10,fr11,fr12,cc0,1 + test_fr_limmed 0x7ffc,0x7ffd,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + cmsubhus fr10,fr11,fr12,cc4,1 + test_fr_limmed 0x0000,0x0000,fr12 + test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmsubhus fr10,fr11,fr12,cc4,1 + test_fr_limmed 0x0000,0x0000,fr12 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0002,fr11 + cmsubhus.p fr10,fr10,fr12,cc4,1 + cmsubhus fr10,fr11,fr13,cc4,1 + test_fr_limmed 0x0000,0x0000,fr12 + test_fr_limmed 0x0000,0x0000,fr13 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 0x3c,2,0xc,msr1 ; msr1.sie is set + test_spr_bits 2,1,1,msr1 ; msr1.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmsubhus fr10,fr11,fr12,cc1,0 + test_fr_limmed 0x0000,0x0000,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xdead,0xbeef,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmsubhus fr10,fr11,fr12,cc1,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmsubhus fr10,fr11,fr12,cc1,0 + test_fr_limmed 0x0123,0x4567,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmsubhus fr10,fr11,fr12,cc1,0 + test_fr_limmed 0x7ffc,0x7ffd,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + cmsubhus fr10,fr11,fr12,cc5,0 + test_fr_limmed 0x0000,0x0000,fr12 + test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmsubhus fr10,fr11,fr12,cc5,0 + test_fr_limmed 0x0000,0x0000,fr12 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0002,fr11 + cmsubhus.p fr10,fr10,fr12,cc5,0 + cmsubhus fr10,fr11,fr13,cc5,0 + test_fr_limmed 0x0000,0x0000,fr12 + test_fr_limmed 0x0000,0x0000,fr13 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 0x3c,2,0xc,msr1 ; msr1.sie is set + test_spr_bits 2,1,1,msr1 ; msr1.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_fr_iimmed 0xdead,0xbeef,fr12 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmsubhus fr10,fr11,fr12,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xbeef,0xdead,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmsubhus fr10,fr11,fr12,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmsubhus fr10,fr11,fr12,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmsubhus fr10,fr11,fr12,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + cmsubhus fr10,fr11,fr12,cc4,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmsubhus fr10,fr11,fr12,cc4,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xbeef,0xdead,fr13 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0002,fr11 + cmsubhus.p fr10,fr10,fr12,cc4,0 + cmsubhus fr10,fr11,fr13,cc4,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_fr_limmed 0xbeef,0xdead,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xdead,0xbeef,fr12 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmsubhus fr10,fr11,fr12,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xbeef,0xdead,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmsubhus fr10,fr11,fr12,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmsubhus fr10,fr11,fr12,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmsubhus fr10,fr11,fr12,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + cmsubhus fr10,fr11,fr12,cc5,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmsubhus fr10,fr11,fr12,cc5,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xbeef,0xdead,fr13 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0002,fr11 + cmsubhus.p fr10,fr10,fr12,cc5,1 + cmsubhus fr10,fr11,fr13,cc5,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_fr_limmed 0xbeef,0xdead,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xdead,0xbeef,fr12 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmsubhus fr10,fr11,fr12,cc2,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xbeef,0xdead,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmsubhus fr10,fr11,fr12,cc2,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmsubhus fr10,fr11,fr12,cc2,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmsubhus fr10,fr11,fr12,cc2,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + cmsubhus fr10,fr11,fr12,cc6,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmsubhus fr10,fr11,fr12,cc6,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xbeef,0xdead,fr13 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0002,fr11 + cmsubhus.p fr10,fr10,fr12,cc6,0 + cmsubhus fr10,fr11,fr13,cc6,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_fr_limmed 0xbeef,0xdead,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set +; + set_fr_iimmed 0xdead,0xbeef,fr12 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmsubhus fr10,fr11,fr12,cc3,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xbeef,0xdead,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmsubhus fr10,fr11,fr12,cc3,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmsubhus fr10,fr11,fr12,cc3,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmsubhus fr10,fr11,fr12,cc3,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + cmsubhus fr10,fr11,fr12,cc7,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmsubhus fr10,fr11,fr12,cc7,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xbeef,0xdead,fr13 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0002,fr11 + cmsubhus.p fr10,fr10,fr12,cc7,0 + cmsubhus fr10,fr11,fr13,cc7,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_fr_limmed 0xbeef,0xdead,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + pass diff --git a/sim/testsuite/sim/frv/cmxor.cgs b/sim/testsuite/sim/frv/cmxor.cgs new file mode 100644 index 0000000..236e2fe --- /dev/null +++ b/sim/testsuite/sim/frv/cmxor.cgs @@ -0,0 +1,132 @@ +# frv testcase for cmxor $FRinti,$FRintj,$FRintk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cmxor +cmxor: + set_spr_immed 0x1b1b,cccr + + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + set_fr_iimmed 0x5555,0x5555,fr8 + cmxor fr7,fr8,fr8,cc0,1 + test_fr_iimmed 0xffffffff,fr8 + + set_fr_iimmed 0x0000,0x0000,fr7 + set_fr_iimmed 0x0000,0x0000,fr8 + cmxor fr7,fr8,fr8,cc0,1 + test_fr_iimmed 0x00000000,fr8 + + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + set_fr_iimmed 0xaaaa,0xaaaa,fr8 + cmxor fr7,fr8,fr8,cc4,1 + test_fr_iimmed 0x00000000,fr8 + + set_fr_iimmed 0xdead,0x0000,fr7 + set_fr_iimmed 0x0000,0xbeef,fr8 + cmxor fr7,fr8,fr8,cc4,1 + test_fr_iimmed 0xdeadbeef,fr8 + + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + set_fr_iimmed 0x5555,0x5555,fr8 + cmxor fr7,fr8,fr8,cc1,0 + test_fr_iimmed 0xffffffff,fr8 + + set_fr_iimmed 0x0000,0x0000,fr7 + set_fr_iimmed 0x0000,0x0000,fr8 + cmxor fr7,fr8,fr8,cc1,0 + test_fr_iimmed 0x00000000,fr8 + + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + set_fr_iimmed 0xaaaa,0xaaaa,fr8 + cmxor fr7,fr8,fr8,cc5,0 + test_fr_iimmed 0x00000000,fr8 + + set_fr_iimmed 0xdead,0x0000,fr7 + set_fr_iimmed 0x0000,0xbeef,fr8 + cmxor fr7,fr8,fr8,cc5,0 + test_fr_iimmed 0xdeadbeef,fr8 + + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + set_fr_iimmed 0x5555,0x5555,fr8 + cmxor fr7,fr8,fr8,cc0,0 + test_fr_iimmed 0x55555555,fr8 + + set_fr_iimmed 0xdead,0xbeef,fr7 + set_fr_iimmed 0x0000,0x0000,fr8 + cmxor fr7,fr8,fr8,cc0,0 + test_fr_iimmed 0x00000000,fr8 + + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + set_fr_iimmed 0xaaaa,0xaaaa,fr8 + cmxor fr7,fr8,fr8,cc4,0 + test_fr_iimmed 0xaaaaaaaa,fr8 + + set_fr_iimmed 0xdead,0x0000,fr7 + set_fr_iimmed 0x0000,0xbeef,fr8 + cmxor fr7,fr8,fr8,cc4,0 + test_fr_iimmed 0x0000beef,fr8 + + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + set_fr_iimmed 0x5555,0x5555,fr8 + cmxor fr7,fr8,fr8,cc1,1 + test_fr_iimmed 0x55555555,fr8 + + set_fr_iimmed 0xdead,0xbeef,fr7 + set_fr_iimmed 0x0000,0x0000,fr8 + cmxor fr7,fr8,fr8,cc1,1 + test_fr_iimmed 0x00000000,fr8 + + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + set_fr_iimmed 0xaaaa,0xaaaa,fr8 + cmxor fr7,fr8,fr8,cc5,1 + test_fr_iimmed 0xaaaaaaaa,fr8 + + set_fr_iimmed 0xdead,0x0000,fr7 + set_fr_iimmed 0x0000,0xbeef,fr8 + cmxor fr7,fr8,fr8,cc5,1 + test_fr_iimmed 0x0000beef,fr8 + + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + set_fr_iimmed 0x5555,0x5555,fr8 + cmxor fr7,fr8,fr8,cc2,0 + test_fr_iimmed 0x55555555,fr8 + + set_fr_iimmed 0xdead,0xbeef,fr7 + set_fr_iimmed 0x0000,0x0000,fr8 + cmxor fr7,fr8,fr8,cc2,1 + test_fr_iimmed 0x00000000,fr8 + + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + set_fr_iimmed 0xaaaa,0xaaaa,fr8 + cmxor fr7,fr8,fr8,cc6,0 + test_fr_iimmed 0xaaaaaaaa,fr8 + + set_fr_iimmed 0xdead,0x0000,fr7 + set_fr_iimmed 0x0000,0xbeef,fr8 + cmxor fr7,fr8,fr8,cc6,1 + test_fr_iimmed 0x0000beef,fr8 + + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + set_fr_iimmed 0x5555,0x5555,fr8 + cmxor fr7,fr8,fr8,cc3,0 + test_fr_iimmed 0x55555555,fr8 + + set_fr_iimmed 0xdead,0xbeef,fr7 + set_fr_iimmed 0x0000,0x0000,fr8 + cmxor fr7,fr8,fr8,cc3,1 + test_fr_iimmed 0x00000000,fr8 + + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + set_fr_iimmed 0xaaaa,0xaaaa,fr8 + cmxor fr7,fr8,fr8,cc7,0 + test_fr_iimmed 0xaaaaaaaa,fr8 + + set_fr_iimmed 0xdead,0x0000,fr7 + set_fr_iimmed 0x0000,0xbeef,fr8 + cmxor fr7,fr8,fr8,cc7,1 + test_fr_iimmed 0x0000beef,fr8 + + pass diff --git a/sim/testsuite/sim/frv/cnot.cgs b/sim/testsuite/sim/frv/cnot.cgs new file mode 100644 index 0000000..3169887 --- /dev/null +++ b/sim/testsuite/sim/frv/cnot.cgs @@ -0,0 +1,60 @@ +# frv testcase for cnot $GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global cnot +cnot: + set_spr_immed 0x1b1b,cccr + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + cnot gr7,gr7,cc0,1 + test_gr_limmed 0x5555,0x5555,gr7 + + set_gr_limmed 0xdead,0xbeef,gr7 + cnot gr7,gr7,cc4,1 + test_gr_limmed 0x2152,0x4110,gr7 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + cnot gr7,gr7,cc0,0 + test_gr_limmed 0xaaaa,0xaaaa,gr7 + + set_gr_limmed 0xdead,0xbeef,gr7 + cnot gr7,gr7,cc4,0 + test_gr_limmed 0xdead,0xbeef,gr7 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + cnot gr7,gr7,cc1,0 + test_gr_limmed 0x5555,0x5555,gr7 + + set_gr_limmed 0xdead,0xbeef,gr7 + cnot gr7,gr7,cc5,0 + test_gr_limmed 0x2152,0x4110,gr7 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + cnot gr7,gr7,cc1,1 + test_gr_limmed 0xaaaa,0xaaaa,gr7 + + set_gr_limmed 0xdead,0xbeef,gr7 + cnot gr7,gr7,cc5,1 + test_gr_limmed 0xdead,0xbeef,gr7 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + cnot gr7,gr7,cc2,0 + test_gr_limmed 0xaaaa,0xaaaa,gr7 + + set_gr_limmed 0xdead,0xbeef,gr7 + cnot gr7,gr7,cc6,1 + test_gr_limmed 0xdead,0xbeef,gr7 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + cnot gr7,gr7,cc3,0 + test_gr_limmed 0xaaaa,0xaaaa,gr7 + + set_gr_limmed 0xdead,0xbeef,gr7 + cnot gr7,gr7,cc7,1 + test_gr_limmed 0xdead,0xbeef,gr7 + + pass diff --git a/sim/testsuite/sim/frv/commitfa.cgs b/sim/testsuite/sim/frv/commitfa.cgs new file mode 100644 index 0000000..8208cab --- /dev/null +++ b/sim/testsuite/sim/frv/commitfa.cgs @@ -0,0 +1,61 @@ +# frv testcase for commitfa +# mach: frv + + .include "testutils.inc" + + start + + .global commitfa +commitfa: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr17 + inc_gr_immed 0x190,gr17 ; address of exception handler + set_bctrlr_0_0 gr17 + set_spr_immed 128,lcr + set_psr_et 1 + set_gr_immed 0,gr15 + + nldfi @(sp,0),fr20 ; Activate fr20 with nesr.fr==1 + nldi @(sp,0),gr20 ; Activate gr20 with nesr.fr==0 + nldfi @(sp,0),fr52 ; Activate fr52 with nesr.fr==1 + set_spr_immed 0x00000000,fner1 + set_spr_immed 0x00000000,fner0 + set_spr_addr bad,lr + commitfa ; should be nop + test_spr_immed 0x00000000,fner1 + test_spr_immed 0x00000000,fner0 + test_spr_immed 0xd4800001,nesr0 + test_spr_gr neear0,sp + test_spr_immed 0x94800401,nesr1 + test_spr_gr neear1,sp + test_spr_immed 0xf4800801,nesr2 + test_spr_gr neear2,sp + + or_spr_immed 0x00100000,fner1 + or_spr_immed 0x00200000,fner1 + or_spr_immed 0x00100000,fner0 + set_spr_addr ok,lr + set_gr_addr com1,gr16 +com1: commitfa + test_gr_immed 1,gr15 + + pass + +ok: test_spr_immed 0x1,esfr1 ; esr0 is active + test_spr_gr epcr0,gr16 + test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid + test_spr_bits 0x003e,1,0x14,esr0 ; esr0.ec is set + test_spr_bits 0x0800,11,0x0,esr0 ; esr0.eav is clear + test_spr_bits 0x01000,12,0x0,esr0 ; esr0.edv is clear + test_spr_immed 0x00000000,fner1 + test_spr_immed 0x00000000,fner0 + test_spr_immed 0,nesr0 + test_spr_immed 0,neear0 + test_spr_immed 0x94800401,nesr1 + test_spr_gr neear1,sp + test_spr_immed 0,nesr2 + test_spr_immed 0,neear2 + inc_gr_immed 1,gr15 + rett 0 + +bad: fail diff --git a/sim/testsuite/sim/frv/commitfr.cgs b/sim/testsuite/sim/frv/commitfr.cgs new file mode 100644 index 0000000..97491dc --- /dev/null +++ b/sim/testsuite/sim/frv/commitfr.cgs @@ -0,0 +1,61 @@ +# frv testcase for commitfr $FRk +# mach: frv + + .include "testutils.inc" + + start + + .global commitfr +commitfr: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr17 + inc_gr_immed 0x190,gr17 ; address of exception handler + set_bctrlr_0_0 gr17 + set_spr_immed 128,lcr + set_psr_et 1 + set_gr_immed 0,gr15 + + nldfi @(sp,0),fr20 ; Activate fr20 with nesr.fr==1 + nldi @(sp,0),gr20 ; Activate gr20 with nesr.fr==0 + nldfi @(sp,0),fr52 ; Activate fr52 with nesr.fr==1 + set_spr_immed 0x00000000,fner1 + set_spr_immed 0x00000000,fner0 + set_spr_addr bad,lr + commitfr fr20 ; should be nop + test_spr_immed 0x00000000,fner1 + test_spr_immed 0x00000000,fner0 + test_spr_immed 0xd4800001,nesr0 + test_spr_gr neear0,sp + test_spr_immed 0x94800401,nesr1 + test_spr_gr neear1,sp + test_spr_immed 0xf4800801,nesr2 + test_spr_gr neear2,sp + + or_spr_immed 0x00100000,fner1 + or_spr_immed 0x00200000,fner1 + or_spr_immed 0x00100000,fner0 + set_spr_addr ok,lr + set_gr_addr com1,gr16 +com1: commitfr fr20 + test_gr_immed 1,gr15 + + pass + +ok: test_spr_immed 0x1,esfr1 ; esr0 is active + test_spr_gr epcr0,gr16 + test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid + test_spr_bits 0x003e,1,0x14,esr0 ; esr0.ec is set + test_spr_bits 0x0800,11,0x0,esr0 ; esr0.eav is clear + test_spr_bits 0x01000,12,0x0,esr0 ; esr0.edv is clear + test_spr_immed 0x00200000,fner1 + test_spr_immed 0x00100000,fner0 + test_spr_immed 0,nesr0 + test_spr_immed 0,neear0 + test_spr_immed 0x94800401,nesr1 + test_spr_gr neear1,sp + test_spr_immed 0xf4800801,nesr2 + test_spr_gr neear2,sp + inc_gr_immed 1,gr15 + rett 0 + +bad: fail diff --git a/sim/testsuite/sim/frv/commitga.cgs b/sim/testsuite/sim/frv/commitga.cgs new file mode 100644 index 0000000..57100b8 --- /dev/null +++ b/sim/testsuite/sim/frv/commitga.cgs @@ -0,0 +1,62 @@ +# frv testcase for commitga +# mach: frv + + .include "testutils.inc" + + start + + .global commitga +commitga: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr17 + inc_gr_immed 0x190,gr17 ; address of exception handler + set_bctrlr_0_0 gr17 + set_spr_immed 128,lcr + set_psr_et 1 + set_gr_immed 0,gr15 + + nldi @(sp,0),gr20 ; Activate gr20 with nesr.fr==0 + nldfi @(sp,0),fr20 ; Activate fr20 with nesr.fr==1 + nldi @(sp,0),gr52 ; Activate gr52 with nesr.fr==0 + set_spr_immed 0x00000000,gner1 + set_spr_immed 0x00000000,gner0 + set_spr_addr bad,lr + commitga ; should be a nop + test_gr_immed 0,gr15 + test_spr_immed 0x00000000,gner1 + test_spr_immed 0x00000000,gner0 + test_spr_immed 0x94800001,nesr0 + test_spr_gr neear0,sp + test_spr_immed 0xd4800401,nesr1 + test_spr_gr neear1,sp + test_spr_immed 0xb4800801,nesr2 + test_spr_gr neear2,sp + + or_spr_immed 0x00100000,gner1 + or_spr_immed 0x00200000,gner1 + or_spr_immed 0x00100000,gner0 + set_spr_addr ok,lr + set_gr_addr com1,gr16 +com1: commitga + test_gr_immed 1,gr15 + + pass + +ok: test_spr_immed 0x1,esfr1 ; esr0 is active + test_spr_gr epcr0,gr16 + test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid + test_spr_bits 0x003e,1,0x14,esr0 ; esr0.ec is set + test_spr_bits 0x0800,11,0x0,esr0 ; esr0.eav is clear + test_spr_bits 0x01000,12,0x0,esr0 ; esr0.edv is clear + test_spr_immed 0x00000000,gner1 + test_spr_immed 0x00000000,gner0 + test_spr_immed 0,nesr0 + test_spr_immed 0,neear0 + test_spr_immed 0xd4800401,nesr1 + test_spr_gr neear1,sp + test_spr_immed 0,nesr2 + test_spr_immed 0,neear0 + inc_gr_immed 1,gr15 + rett 0 + +bad: fail diff --git a/sim/testsuite/sim/frv/commitgr.cgs b/sim/testsuite/sim/frv/commitgr.cgs new file mode 100644 index 0000000..45553da --- /dev/null +++ b/sim/testsuite/sim/frv/commitgr.cgs @@ -0,0 +1,62 @@ +# frv testcase for commitgr $GRk +# mach: frv + + .include "testutils.inc" + + start + + .global commitgr +commitgr: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr17 + inc_gr_immed 0x190,gr17 ; address of exception handler + set_bctrlr_0_0 gr17 + set_spr_immed 128,lcr + set_psr_et 1 + set_gr_immed 0,gr15 + + nldi @(sp,0),gr20 ; Activate gr20 with nesr.fr==0 + nldfi @(sp,0),fr20 ; Activate fr20 with nesr.fr==1 + nldi @(sp,0),gr52 ; Activate gr52 with nesr.fr==0 + set_spr_immed 0x00000000,gner1 + set_spr_immed 0x00000000,gner0 + set_spr_addr bad,lr + commitgr gr20 ; should only clear ne flags + test_gr_immed 0,gr15 + test_spr_immed 0x00000000,gner1 + test_spr_immed 0x00000000,gner0 + test_spr_immed 0x94800001,nesr0 + test_spr_gr neear0,sp + test_spr_immed 0xd4800401,nesr1 + test_spr_gr neear1,sp + test_spr_immed 0xb4800801,nesr2 + test_spr_gr neear2,sp + + or_spr_immed 0x00100000,gner1 + or_spr_immed 0x00200000,gner1 + or_spr_immed 0x00100000,gner0 + set_spr_addr ok,lr + set_gr_addr com1,gr16 +com1: commitgr gr20 + test_gr_immed 1,gr15 + + pass + +ok: test_spr_immed 0x1,esfr1 ; esr0 is active + test_spr_gr epcr0,gr16 + test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid + test_spr_bits 0x003e,1,0x14,esr0 ; esr0.ec is set + test_spr_bits 0x0800,11,0x0,esr0 ; esr0.eav is clear + test_spr_bits 0x01000,12,0x0,esr0 ; esr0.edv is clear + test_spr_immed 0x00200000,gner1 + test_spr_immed 0x00100000,gner0 + test_spr_immed 0,nesr0 + test_spr_immed 0,neear0 + test_spr_immed 0xd4800401,nesr1 + test_spr_gr neear1,sp + test_spr_immed 0xb4800801,nesr2 + test_spr_gr neear2,sp + inc_gr_immed 1,gr15 + rett 0 + +bad: fail diff --git a/sim/testsuite/sim/frv/cop1.cgs b/sim/testsuite/sim/frv/cop1.cgs new file mode 100644 index 0000000..652e355 --- /dev/null +++ b/sim/testsuite/sim/frv/cop1.cgs @@ -0,0 +1,14 @@ +# frv testcase for cop1 $s6_1,$CPRi,$CPRj,$CPRk +# mach: frv + + .include "testutils.inc" + + start + + .global cop1 +cop1: + cop1 0,cpr0,cpr15,cpr31 + cop1 31,cpr32,cpr45,cpr63 + cop1 -32,cpr32,cpr45,cpr63 + + pass diff --git a/sim/testsuite/sim/frv/cop2.cgs b/sim/testsuite/sim/frv/cop2.cgs new file mode 100644 index 0000000..858ed2b --- /dev/null +++ b/sim/testsuite/sim/frv/cop2.cgs @@ -0,0 +1,14 @@ +# frv testcase for cop2 $s6_1,$CPRi,$CPRj,$CPRk +# mach: frv + + .include "testutils.inc" + + start + + .global cop2 +cop2: + cop2 0,cpr0,cpr15,cpr31 + cop2 31,cpr32,cpr45,cpr63 + cop2 -32,cpr32,cpr45,cpr63 + + pass diff --git a/sim/testsuite/sim/frv/cor.cgs b/sim/testsuite/sim/frv/cor.cgs new file mode 100644 index 0000000..ef19985 --- /dev/null +++ b/sim/testsuite/sim/frv/cor.cgs @@ -0,0 +1,138 @@ +# frv testcase for cor $GRi,$GRj,$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cor +cor: + set_spr_immed 0x1b1b,cccr + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x07,0 ; Set mask opposite of expected + cor gr7,gr8,gr8,cc0,1 + test_icc 0 1 1 1 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + + set_gr_immed 0x00000000,gr7 + set_gr_immed 0x00000000,gr8 + set_icc 0x08,0 ; Set mask opposite of expected + cor gr7,gr8,gr8,cc0,1 + test_icc 1 0 0 0 icc0 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0x0000,gr7 + set_gr_limmed 0x0000,0xbeef,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + cor gr7,gr8,gr8,cc4,1 + test_icc 0 1 0 1 icc0 + test_gr_limmed 0xdead,0xbeef,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x07,0 ; Set mask opposite of expected + cor gr7,gr8,gr8,cc0,0 + test_icc 0 1 1 1 icc0 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_immed 0x00007fff,gr7 + set_gr_immed 0x00000000,gr8 + set_icc 0x08,0 ; Set mask opposite of expected + cor gr7,gr8,gr8,cc0,0 + test_icc 1 0 0 0 icc0 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0x0000,gr7 + set_gr_limmed 0x0000,0xbeef,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + cor gr7,gr8,gr8,cc4,0 + test_icc 0 1 0 1 icc0 + test_gr_limmed 0x0000,0xbeef,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x07,1 ; Set mask opposite of expected + cor gr7,gr8,gr8,cc1,0 + test_icc 0 1 1 1 icc1 + test_gr_limmed 0xffff,0xffff,gr8 + + set_gr_immed 0x00000000,gr7 + set_gr_immed 0x00000000,gr8 + set_icc 0x08,1 ; Set mask opposite of expected + cor gr7,gr8,gr8,cc1,0 + test_icc 1 0 0 0 icc1 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0x0000,gr7 + set_gr_limmed 0x0000,0xbeef,gr8 + set_icc 0x05,1 ; Set mask opposite of expected + cor gr7,gr8,gr8,cc5,0 + test_icc 0 1 0 1 icc1 + test_gr_limmed 0xdead,0xbeef,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x07,1 ; Set mask opposite of expected + cor gr7,gr8,gr8,cc1,1 + test_icc 0 1 1 1 icc1 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_immed 0x00007fff,gr7 + set_gr_immed 0x00000000,gr8 + set_icc 0x08,1 ; Set mask opposite of expected + cor gr7,gr8,gr8,cc1,1 + test_icc 1 0 0 0 icc1 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0x0000,gr7 + set_gr_limmed 0x0000,0xbeef,gr8 + set_icc 0x05,1 ; Set mask opposite of expected + cor gr7,gr8,gr8,cc5,1 + test_icc 0 1 0 1 icc1 + test_gr_limmed 0x0000,0xbeef,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x07,2 ; Set mask opposite of expected + cor gr7,gr8,gr8,cc2,0 + test_icc 0 1 1 1 icc2 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_immed 0x00007fff,gr7 + set_gr_immed 0x00000000,gr8 + set_icc 0x08,2 ; Set mask opposite of expected + cor gr7,gr8,gr8,cc2,0 + test_icc 1 0 0 0 icc2 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0x0000,gr7 + set_gr_limmed 0x0000,0xbeef,gr8 + set_icc 0x05,2 ; Set mask opposite of expected + cor gr7,gr8,gr8,cc6,1 + test_icc 0 1 0 1 icc2 + test_gr_limmed 0x0000,0xbeef,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x07,3 ; Set mask opposite of expected + cor gr7,gr8,gr8,cc3,0 + test_icc 0 1 1 1 icc3 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_immed 0x00007fff,gr7 + set_gr_immed 0x00000000,gr8 + set_icc 0x08,3 ; Set mask opposite of expected + cor gr7,gr8,gr8,cc3,0 + test_icc 1 0 0 0 icc3 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0x0000,gr7 + set_gr_limmed 0x0000,0xbeef,gr8 + set_icc 0x05,3 ; Set mask opposite of expected + cor gr7,gr8,gr8,cc7,1 + test_icc 0 1 0 1 icc3 + test_gr_limmed 0x0000,0xbeef,gr8 + + pass diff --git a/sim/testsuite/sim/frv/corcc.cgs b/sim/testsuite/sim/frv/corcc.cgs new file mode 100644 index 0000000..5276658 --- /dev/null +++ b/sim/testsuite/sim/frv/corcc.cgs @@ -0,0 +1,138 @@ +# frv testcase for corcc $GRi,$GRj,$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global corcc +corcc: + set_spr_immed 0x1b1b,cccr + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x07,0 ; Set mask opposite of expected + corcc gr7,gr8,gr8,cc0,1 + test_icc 1 0 1 1 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + + set_gr_immed 0x00000000,gr7 + set_gr_immed 0x00000000,gr8 + set_icc 0x08,0 ; Set mask opposite of expected + corcc gr7,gr8,gr8,cc0,1 + test_icc 0 1 0 0 icc0 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0x0000,gr7 + set_gr_limmed 0x0000,0xbeef,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + corcc gr7,gr8,gr8,cc4,1 + test_icc 1 0 0 1 icc0 + test_gr_limmed 0xdead,0xbeef,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x07,0 ; Set mask opposite of expected + corcc gr7,gr8,gr8,cc0,0 + test_icc 0 1 1 1 icc0 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_immed 0x00007fff,gr7 + set_gr_immed 0x00000000,gr8 + set_icc 0x08,0 ; Set mask opposite of expected + corcc gr7,gr8,gr8,cc0,0 + test_icc 1 0 0 0 icc0 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0x0000,gr7 + set_gr_limmed 0x0000,0xbeef,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + corcc gr7,gr8,gr8,cc4,0 + test_icc 0 1 0 1 icc0 + test_gr_limmed 0x0000,0xbeef,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x07,1 ; Set mask opposite of expected + corcc gr7,gr8,gr8,cc1,0 + test_icc 1 0 1 1 icc1 + test_gr_limmed 0xffff,0xffff,gr8 + + set_gr_immed 0x00000000,gr7 + set_gr_immed 0x00000000,gr8 + set_icc 0x08,1 ; Set mask opposite of expected + corcc gr7,gr8,gr8,cc1,0 + test_icc 0 1 0 0 icc1 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0x0000,gr7 + set_gr_limmed 0x0000,0xbeef,gr8 + set_icc 0x05,1 ; Set mask opposite of expected + corcc gr7,gr8,gr8,cc5,0 + test_icc 1 0 0 1 icc1 + test_gr_limmed 0xdead,0xbeef,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x07,1 ; Set mask opposite of expected + corcc gr7,gr8,gr8,cc1,1 + test_icc 0 1 1 1 icc1 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_immed 0x00007fff,gr7 + set_gr_immed 0x00000000,gr8 + set_icc 0x08,1 ; Set mask opposite of expected + corcc gr7,gr8,gr8,cc1,1 + test_icc 1 0 0 0 icc1 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0x0000,gr7 + set_gr_limmed 0x0000,0xbeef,gr8 + set_icc 0x05,1 ; Set mask opposite of expected + corcc gr7,gr8,gr8,cc5,1 + test_icc 0 1 0 1 icc1 + test_gr_limmed 0x0000,0xbeef,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x07,2 ; Set mask opposite of expected + corcc gr7,gr8,gr8,cc2,0 + test_icc 0 1 1 1 icc2 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_immed 0x00007fff,gr7 + set_gr_immed 0x00000000,gr8 + set_icc 0x08,2 ; Set mask opposite of expected + corcc gr7,gr8,gr8,cc2,0 + test_icc 1 0 0 0 icc2 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0x0000,gr7 + set_gr_limmed 0x0000,0xbeef,gr8 + set_icc 0x05,2 ; Set mask opposite of expected + corcc gr7,gr8,gr8,cc6,1 + test_icc 0 1 0 1 icc2 + test_gr_limmed 0x0000,0xbeef,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x07,3 ; Set mask opposite of expected + corcc gr7,gr8,gr8,cc3,0 + test_icc 0 1 1 1 icc3 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_immed 0x00007fff,gr7 + set_gr_immed 0x00000000,gr8 + set_icc 0x08,3 ; Set mask opposite of expected + corcc gr7,gr8,gr8,cc3,0 + test_icc 1 0 0 0 icc3 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0x0000,gr7 + set_gr_limmed 0x0000,0xbeef,gr8 + set_icc 0x05,3 ; Set mask opposite of expected + corcc gr7,gr8,gr8,cc7,1 + test_icc 0 1 0 1 icc3 + test_gr_limmed 0x0000,0xbeef,gr8 + + pass diff --git a/sim/testsuite/sim/frv/cscan.cgs b/sim/testsuite/sim/frv/cscan.cgs new file mode 100644 index 0000000..505bb5a --- /dev/null +++ b/sim/testsuite/sim/frv/cscan.cgs @@ -0,0 +1,394 @@ +# frv testcase for cscan $GRi,$GRj,$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cscan +cscan: + set_spr_immed 0x1b1b,cccr + + set_gr_limmed 0x2aaa,0xaaaa,gr7 + set_gr_limmed 0xaaaa,0x5555,gr8 + cscan gr7,gr8,gr9,cc0,1 + test_gr_immed 0,gr9 + test_gr_limmed 0x2aaa,0xaaaa,gr7 + test_gr_limmed 0xaaaa,0x5555,gr8 + + set_gr_limmed 0x2aaa,0xaaaa,gr7 + set_gr_limmed 0xaaaa,0xaaab,gr8 + cscan gr7,gr8,gr9,cc0,1 + test_gr_immed 0,gr9 + test_gr_limmed 0x2aaa,0xaaaa,gr7 + test_gr_limmed 0xaaaa,0xaaab,gr8 + + set_gr_limmed 0xd555,0x5555,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + cscan gr7,gr8,gr9,cc0,1 + test_gr_immed 63,gr9 + test_gr_limmed 0xd555,0x5555,gr7 + test_gr_limmed 0xaaaa,0xaaaa,gr8 + + set_gr_limmed 0xd555,0x5555,gr7 + set_gr_limmed 0xaaaa,0xaaab,gr8 + cscan gr7,gr8,gr9,cc0,1 + test_gr_immed 63,gr9 + test_gr_limmed 0xd555,0x5555,gr7 + test_gr_limmed 0xaaaa,0xaaab,gr8 + + set_gr_limmed 0xffff,0xffff,gr7 + set_gr_limmed 0x7fff,0xffff,gr8 + cscan gr7,gr8,gr9,cc0,1 + test_gr_immed 0,gr9 + test_gr_limmed 0xffff,0xffff,gr7 + test_gr_limmed 0x7fff,0xffff,gr8 + + set_gr_limmed 0xffff,0xffff,gr7 + set_gr_limmed 0xbfff,0xffff,gr8 + cscan gr7,gr8,gr9,cc4,1 + test_gr_immed 2,gr9 + test_gr_limmed 0xffff,0xffff,gr7 + test_gr_limmed 0xbfff,0xffff,gr8 + + set_gr_limmed 0xffff,0xffff,gr7 + set_gr_limmed 0xfffe,0xffff,gr8 + cscan gr7,gr8,gr9,cc4,1 + test_gr_immed 16,gr9 + test_gr_limmed 0xffff,0xffff,gr7 + test_gr_limmed 0xfffe,0xffff,gr8 + + set_gr_limmed 0xffff,0xffff,gr7 + set_gr_limmed 0xffff,0xfffd,gr8 + cscan gr7,gr8,gr9,cc4,1 + test_gr_immed 31,gr9 + test_gr_limmed 0xffff,0xffff,gr7 + test_gr_limmed 0xffff,0xfffd,gr8 + + set_gr_limmed 0xdead,0xbeef,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + cscan gr7,gr8,gr9,cc4,1 + test_gr_immed 7,gr9 + test_gr_limmed 0xdead,0xbeef,gr7 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0x7fff,gr9 + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + cscan gr7,gr8,gr9,cc0,0 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0xaaaa,0xaaaa,gr7 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_limmed 0xaaaa,0xaaab,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + cscan gr7,gr8,gr9,cc0,0 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0xaaaa,0xaaab,gr7 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_limmed 0x5555,0x5555,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + cscan gr7,gr8,gr9,cc0,0 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0x5555,0x5555,gr7 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_limmed 0x5555,0x5555,gr7 + set_gr_limmed 0x5555,0x5554,gr8 + cscan gr7,gr8,gr9,cc0,0 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0x5555,0x5555,gr7 + test_gr_limmed 0x5555,0x5554,gr8 + + set_gr_limmed 0xffff,0xffff,gr7 + set_gr_limmed 0x7fff,0xffff,gr8 + cscan gr7,gr8,gr9,cc0,0 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0xffff,0xffff,gr7 + test_gr_limmed 0x7fff,0xffff,gr8 + + set_gr_limmed 0xffff,0xffff,gr7 + set_gr_limmed 0xbfff,0xffff,gr8 + cscan gr7,gr8,gr9,cc4,0 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0xffff,0xffff,gr7 + test_gr_limmed 0xbfff,0xffff,gr8 + + set_gr_limmed 0xffff,0xffff,gr7 + set_gr_limmed 0xfffe,0xffff,gr8 + cscan gr7,gr8,gr9,cc4,0 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0xffff,0xffff,gr7 + test_gr_limmed 0xfffe,0xffff,gr8 + + set_gr_limmed 0xffff,0xffff,gr7 + set_gr_limmed 0xffff,0xfffd,gr8 + cscan gr7,gr8,gr9,cc4,0 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0xffff,0xffff,gr7 + test_gr_limmed 0xffff,0xfffd,gr8 + + set_gr_limmed 0xdead,0xbeef,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + cscan gr7,gr8,gr9,cc4,0 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0xdead,0xbeef,gr7 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_limmed 0x2aaa,0xaaaa,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + cscan gr7,gr8,gr9,cc1,0 + test_gr_immed 0,gr9 + test_gr_limmed 0x2aaa,0xaaaa,gr7 + test_gr_limmed 0xaaaa,0xaaaa,gr8 + + set_gr_limmed 0x2aaa,0xaaaa,gr7 + set_gr_limmed 0xaaaa,0xaaab,gr8 + cscan gr7,gr8,gr9,cc1,0 + test_gr_immed 0,gr9 + test_gr_limmed 0x2aaa,0xaaaa,gr7 + test_gr_limmed 0xaaaa,0xaaab,gr8 + + set_gr_limmed 0xd555,0x5555,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + cscan gr7,gr8,gr9,cc1,0 + test_gr_immed 63,gr9 + test_gr_limmed 0xd555,0x5555,gr7 + test_gr_limmed 0xaaaa,0xaaaa,gr8 + + set_gr_limmed 0xd555,0x5555,gr7 + set_gr_limmed 0xaaaa,0xaaab,gr8 + cscan gr7,gr8,gr9,cc1,0 + test_gr_immed 63,gr9 + test_gr_limmed 0xd555,0x5555,gr7 + test_gr_limmed 0xaaaa,0xaaab,gr8 + + set_gr_limmed 0xffff,0xffff,gr7 + set_gr_limmed 0x7fff,0xffff,gr8 + cscan gr7,gr8,gr9,cc1,0 + test_gr_immed 0,gr9 + test_gr_limmed 0xffff,0xffff,gr7 + test_gr_limmed 0x7fff,0xffff,gr8 + + set_gr_limmed 0xffff,0xffff,gr7 + set_gr_limmed 0xbfff,0xffff,gr8 + cscan gr7,gr8,gr9,cc5,0 + test_gr_immed 2,gr9 + test_gr_limmed 0xffff,0xffff,gr7 + test_gr_limmed 0xbfff,0xffff,gr8 + + set_gr_limmed 0xffff,0xffff,gr7 + set_gr_limmed 0xfffe,0xffff,gr8 + cscan gr7,gr8,gr9,cc5,0 + test_gr_immed 16,gr9 + test_gr_limmed 0xffff,0xffff,gr7 + test_gr_limmed 0xfffe,0xffff,gr8 + + set_gr_limmed 0xffff,0xffff,gr7 + set_gr_limmed 0xffff,0xfffd,gr8 + cscan gr7,gr8,gr9,cc5,0 + test_gr_immed 31,gr9 + test_gr_limmed 0xffff,0xffff,gr7 + test_gr_limmed 0xffff,0xfffd,gr8 + + set_gr_limmed 0xdead,0xbeef,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + cscan gr7,gr8,gr9,cc5,0 + test_gr_immed 7,gr9 + test_gr_limmed 0xdead,0xbeef,gr7 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0x7fff,gr9 + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + cscan gr7,gr8,gr9,cc1,1 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0xaaaa,0xaaaa,gr7 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_limmed 0xaaaa,0xaaab,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + cscan gr7,gr8,gr9,cc1,1 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0xaaaa,0xaaab,gr7 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_limmed 0x5555,0x5555,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + cscan gr7,gr8,gr9,cc1,1 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0x5555,0x5555,gr7 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_limmed 0x5555,0x5555,gr7 + set_gr_limmed 0x5555,0x5554,gr8 + cscan gr7,gr8,gr9,cc1,1 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0x5555,0x5555,gr7 + test_gr_limmed 0x5555,0x5554,gr8 + + set_gr_limmed 0xffff,0xffff,gr7 + set_gr_limmed 0x7fff,0xffff,gr8 + cscan gr7,gr8,gr9,cc1,1 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0xffff,0xffff,gr7 + test_gr_limmed 0x7fff,0xffff,gr8 + + set_gr_limmed 0xffff,0xffff,gr7 + set_gr_limmed 0xbfff,0xffff,gr8 + cscan gr7,gr8,gr9,cc5,1 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0xffff,0xffff,gr7 + test_gr_limmed 0xbfff,0xffff,gr8 + + set_gr_limmed 0xffff,0xffff,gr7 + set_gr_limmed 0xfffe,0xffff,gr8 + cscan gr7,gr8,gr9,cc5,1 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0xffff,0xffff,gr7 + test_gr_limmed 0xfffe,0xffff,gr8 + + set_gr_limmed 0xffff,0xffff,gr7 + set_gr_limmed 0xffff,0xfffd,gr8 + cscan gr7,gr8,gr9,cc5,1 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0xffff,0xffff,gr7 + test_gr_limmed 0xffff,0xfffd,gr8 + + set_gr_limmed 0xdead,0xbeef,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + cscan gr7,gr8,gr9,cc5,1 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0xdead,0xbeef,gr7 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0x7fff,gr9 + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + cscan gr7,gr8,gr9,cc2,0 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0xaaaa,0xaaaa,gr7 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_limmed 0xaaaa,0xaaab,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + cscan gr7,gr8,gr9,cc2,1 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0xaaaa,0xaaab,gr7 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_limmed 0x5555,0x5555,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + cscan gr7,gr8,gr9,cc2,0 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0x5555,0x5555,gr7 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_limmed 0x5555,0x5555,gr7 + set_gr_limmed 0x5555,0x5554,gr8 + cscan gr7,gr8,gr9,cc2,1 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0x5555,0x5555,gr7 + test_gr_limmed 0x5555,0x5554,gr8 + + set_gr_limmed 0xffff,0xffff,gr7 + set_gr_limmed 0x7fff,0xffff,gr8 + cscan gr7,gr8,gr9,cc2,0 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0xffff,0xffff,gr7 + test_gr_limmed 0x7fff,0xffff,gr8 + + set_gr_limmed 0xffff,0xffff,gr7 + set_gr_limmed 0xbfff,0xffff,gr8 + cscan gr7,gr8,gr9,cc6,1 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0xffff,0xffff,gr7 + test_gr_limmed 0xbfff,0xffff,gr8 + + set_gr_limmed 0xffff,0xffff,gr7 + set_gr_limmed 0xfffe,0xffff,gr8 + cscan gr7,gr8,gr9,cc6,0 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0xffff,0xffff,gr7 + test_gr_limmed 0xfffe,0xffff,gr8 + + set_gr_limmed 0xffff,0xffff,gr7 + set_gr_limmed 0xffff,0xfffd,gr8 + cscan gr7,gr8,gr9,cc6,1 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0xffff,0xffff,gr7 + test_gr_limmed 0xffff,0xfffd,gr8 + + set_gr_limmed 0xdead,0xbeef,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + cscan gr7,gr8,gr9,cc6,0 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0xdead,0xbeef,gr7 + test_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0x7fff,gr9 + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + cscan gr7,gr8,gr9,cc3,1 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0xaaaa,0xaaaa,gr7 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_limmed 0xaaaa,0xaaab,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + cscan gr7,gr8,gr9,cc3,0 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0xaaaa,0xaaab,gr7 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_limmed 0x5555,0x5555,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + cscan gr7,gr8,gr9,cc3,1 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0x5555,0x5555,gr7 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_limmed 0x5555,0x5555,gr7 + set_gr_limmed 0x5555,0x5554,gr8 + cscan gr7,gr8,gr9,cc3,0 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0x5555,0x5555,gr7 + test_gr_limmed 0x5555,0x5554,gr8 + + set_gr_limmed 0xffff,0xffff,gr7 + set_gr_limmed 0x7fff,0xffff,gr8 + cscan gr7,gr8,gr9,cc3,1 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0xffff,0xffff,gr7 + test_gr_limmed 0x7fff,0xffff,gr8 + + set_gr_limmed 0xffff,0xffff,gr7 + set_gr_limmed 0xbfff,0xffff,gr8 + cscan gr7,gr8,gr9,cc7,0 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0xffff,0xffff,gr7 + test_gr_limmed 0xbfff,0xffff,gr8 + + set_gr_limmed 0xffff,0xffff,gr7 + set_gr_limmed 0xfffe,0xffff,gr8 + cscan gr7,gr8,gr9,cc7,1 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0xffff,0xffff,gr7 + test_gr_limmed 0xfffe,0xffff,gr8 + + set_gr_limmed 0xffff,0xffff,gr7 + set_gr_limmed 0xffff,0xfffd,gr8 + cscan gr7,gr8,gr9,cc7,0 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0xffff,0xffff,gr7 + test_gr_limmed 0xffff,0xfffd,gr8 + + set_gr_limmed 0xdead,0xbeef,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + cscan gr7,gr8,gr9,cc7,1 + test_gr_immed 0x7fff,gr9 + test_gr_limmed 0xdead,0xbeef,gr7 + test_gr_limmed 0xbeef,0xdead,gr8 + + pass diff --git a/sim/testsuite/sim/frv/csdiv.cgs b/sim/testsuite/sim/frv/csdiv.cgs new file mode 100644 index 0000000..c6bfb97 --- /dev/null +++ b/sim/testsuite/sim/frv/csdiv.cgs @@ -0,0 +1,190 @@ +# frv testcase for csdiv $GRi,$GRj,$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global csdiv +csdiv: + set_spr_immed 0x1b1b,cccr + + ; simple division 12 / 3 + set_gr_immed 3,gr3 + set_gr_immed 12,gr1 + csdiv gr1,gr3,gr2,cc4,1 + test_gr_immed 4,gr2 + + ; Random example + set_gr_limmed 0x0123,0x4567,gr3 + set_gr_limmed 0xfedc,0xba98,gr1 + csdiv gr1,gr3,gr2,cc4,1 + test_gr_immed -1,gr2 + + ; Special case from the Arch Spec Vol 2 + and_spr_immed -33,isr ; turn off isr.edem + ; set up exception handler + set_psr_et 1 + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr17 + inc_gr_immed 0x170,gr17 ; address of exception handler + set_bctrlr_0_0 gr17 + set_spr_immed 128,lcr + set_gr_immed 0,gr15 + + ; divide will cause overflow + set_spr_addr ok1,lr + set_gr_addr e1,gr17 + set_gr_immed -1,gr3 + set_gr_limmed 0x8000,0x0000,gr1 +e1: csdiv gr1,gr3,gr2,cc4,1 + test_gr_immed 1,gr15 + test_gr_limmed 0x8000,0x0000,gr2 + + ; Special case from the Arch Spec Vol 2 + or_spr_immed 0x20,isr ; turn on isr.edem + set_gr_immed -1,gr3 + set_gr_limmed 0x8000,0x0000,gr1 + csdiv gr1,gr3,gr2,cc4,1 + test_gr_limmed 0x7fff,0xffff,gr2 + + ; simple division 12 / 3 + set_gr_immed 3,gr3 + set_gr_immed 12,gr1 + csdiv gr1,gr3,gr2,cc4,0 + test_gr_limmed 0x7fff,0xffff,gr2 + + ; Random example + set_gr_limmed 0x0123,0x4567,gr3 + set_gr_limmed 0xfedc,0xba98,gr1 + csdiv gr1,gr3,gr2,cc4,0 + test_gr_limmed 0x7fff,0xffff,gr2 + + ; Special case from the Arch Spec Vol 2 + and_spr_immed -33,isr ; turn off isr.edem + set_gr_immed -1,gr3 + set_gr_limmed 0x8000,0x0000,gr1 + csdiv gr1,gr3,gr2,cc4,0 + test_gr_limmed 0x7fff,0xffff,gr2 + + or_spr_immed 0x20,isr ; turn on isr.edem + set_gr_immed -1,gr3 + set_gr_limmed 0x8000,0x0000,gr1 + csdiv gr1,gr3,gr2,cc4,0 + test_gr_limmed 0x7fff,0xffff,gr2 + + ; simple division 12 / 3 + set_gr_immed 3,gr3 + set_gr_immed 12,gr1 + csdiv gr1,gr3,gr2,cc5,0 + test_gr_immed 4,gr2 + + ; Random example + set_gr_limmed 0x0123,0x4567,gr3 + set_gr_limmed 0xfedc,0xba98,gr1 + csdiv gr1,gr3,gr2,cc5,0 + test_gr_immed -1,gr2 + + ; Special case from the Arch Spec Vol 2 + and_spr_immed -33,isr ; turn off isr.edem + ; divide will cause overflow + set_spr_addr ok1,lr + set_gr_addr e2,gr17 + set_gr_immed -1,gr3 + set_gr_limmed 0x8000,0x0000,gr1 +e2: csdiv gr1,gr3,gr2,cc5,0 + test_gr_immed 2,gr15 + test_gr_limmed 0x8000,0x0000,gr2 + + ; Special case from the Arch Spec Vol 2 + or_spr_immed 0x20,isr ; turn on isr.edem + set_gr_immed -1,gr3 + set_gr_limmed 0x8000,0x0000,gr1 + csdiv gr1,gr3,gr2,cc5,0 + test_gr_limmed 0x7fff,0xffff,gr2 + + ; simple division 12 / 3 + set_gr_immed 3,gr3 + set_gr_immed 12,gr1 + csdiv gr1,gr3,gr2,cc5,1 + test_gr_limmed 0x7fff,0xffff,gr2 + + ; Random example + set_gr_limmed 0x0123,0x4567,gr3 + set_gr_limmed 0xfedc,0xba98,gr1 + csdiv gr1,gr3,gr2,cc5,1 + test_gr_limmed 0x7fff,0xffff,gr2 + + ; Special case from the Arch Spec Vol 2 + and_spr_immed -33,isr ; turn off isr.edem + set_gr_immed -1,gr3 + set_gr_limmed 0x8000,0x0000,gr1 + csdiv gr1,gr3,gr2,cc5,1 + test_gr_limmed 0x7fff,0xffff,gr2 + + or_spr_immed 0x20,isr ; turn on isr.edem + set_gr_immed -1,gr3 + set_gr_limmed 0x8000,0x0000,gr1 + csdiv gr1,gr3,gr2,cc5,1 + test_gr_limmed 0x7fff,0xffff,gr2 + + ; simple division 12 / 3 + set_gr_immed 3,gr3 + set_gr_immed 12,gr1 + csdiv gr1,gr3,gr2,cc6,0 + test_gr_limmed 0x7fff,0xffff,gr2 + + ; Random example + set_gr_limmed 0x0123,0x4567,gr3 + set_gr_limmed 0xfedc,0xba98,gr1 + csdiv gr1,gr3,gr2,cc6,0 + test_gr_limmed 0x7fff,0xffff,gr2 + + ; Special case from the Arch Spec Vol 2 + and_spr_immed -33,isr ; turn off isr.edem + set_gr_immed -1,gr3 + set_gr_limmed 0x8000,0x0000,gr1 + csdiv gr1,gr3,gr2,cc6,0 + test_gr_limmed 0x7fff,0xffff,gr2 + + or_spr_immed 0x20,isr ; turn on isr.edem + set_gr_immed -1,gr3 + set_gr_limmed 0x8000,0x0000,gr1 + csdiv gr1,gr3,gr2,cc6,0 + test_gr_limmed 0x7fff,0xffff,gr2 + + ; simple division 12 / 3 + set_gr_immed 3,gr3 + set_gr_immed 12,gr1 + csdiv gr1,gr3,gr2,cc7,1 + test_gr_limmed 0x7fff,0xffff,gr2 + + ; Random example + set_gr_limmed 0x0123,0x4567,gr3 + set_gr_limmed 0xfedc,0xba98,gr1 + csdiv gr1,gr3,gr2,cc7,1 + test_gr_limmed 0x7fff,0xffff,gr2 + + ; Special case from the Arch Spec Vol 2 + and_spr_immed -33,isr ; turn off isr.edem + set_gr_immed -1,gr3 + set_gr_limmed 0x8000,0x0000,gr1 + csdiv gr1,gr3,gr2,cc7,1 + test_gr_limmed 0x7fff,0xffff,gr2 + + or_spr_immed 0x20,isr ; turn on isr.edem + set_gr_immed -1,gr3 + set_gr_limmed 0x8000,0x0000,gr1 + csdiv gr1,gr3,gr2,cc7,1 + test_gr_limmed 0x7fff,0xffff,gr2 + + pass + +ok1: ; exception handler for overflow + test_spr_bits 0x18,3,0x2,isr ; isr.dtt is set + test_spr_gr epcr0,gr17 ; return address set + test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid + test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set + inc_gr_immed 1,gr15 + rett 0 + fail diff --git a/sim/testsuite/sim/frv/csll.cgs b/sim/testsuite/sim/frv/csll.cgs new file mode 100644 index 0000000..0186756 --- /dev/null +++ b/sim/testsuite/sim/frv/csll.cgs @@ -0,0 +1,180 @@ +# frv testcase for csll $GRi,$GRj,$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global csll +csll: + set_spr_immed 0x1b1b,cccr + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_immed 2,gr8 + set_icc 0x0d,0 ; Set mask opposite of expected + csll gr8,gr7,gr8,cc0,1 + test_icc 1 1 0 1 icc0 + test_gr_immed 2,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_immed 2,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + csll gr8,gr7,gr8,cc0,1 + test_icc 1 1 1 1 icc0 + test_gr_immed 4,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_immed 1,gr8 + set_icc 0x07,0 ; Set mask opposite of expected + csll gr8,gr7,gr8,cc4,1 + test_icc 0 1 1 1 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_immed 2,gr8 + set_icc 0x0a,0 ; Set mask opposite of expected + csll gr8,gr7,gr8,cc4,1 + test_icc 1 0 1 0 icc0 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_immed 2,gr8 + set_icc 0x0d,0 ; Set mask opposite of expected + csll gr8,gr7,gr8,cc0,0 + test_icc 1 1 0 1 icc0 + test_gr_immed 2,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_immed 2,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + csll gr8,gr7,gr8,cc0,0 + test_icc 1 1 1 1 icc0 + test_gr_immed 2,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_immed 1,gr8 + set_icc 0x07,0 ; Set mask opposite of expected + csll gr8,gr7,gr8,cc4,0 + test_icc 0 1 1 1 icc0 + test_gr_immed 1,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_immed 2,gr8 + set_icc 0x0a,0 ; Set mask opposite of expected + csll gr8,gr7,gr8,cc4,0 + test_icc 1 0 1 0 icc0 + test_gr_immed 2,gr8 + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_immed 2,gr8 + set_icc 0x0d,1 ; Set mask opposite of expected + csll gr8,gr7,gr8,cc1,0 + test_icc 1 1 0 1 icc1 + test_gr_immed 2,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_immed 2,gr8 + set_icc 0x0f,1 ; Set mask opposite of expected + csll gr8,gr7,gr8,cc1,0 + test_icc 1 1 1 1 icc1 + test_gr_immed 4,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_immed 1,gr8 + set_icc 0x07,1 ; Set mask opposite of expected + csll gr8,gr7,gr8,cc5,0 + test_icc 0 1 1 1 icc1 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_immed 2,gr8 + set_icc 0x0a,1 ; Set mask opposite of expected + csll gr8,gr7,gr8,cc5,0 + test_icc 1 0 1 0 icc1 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_immed 2,gr8 + set_icc 0x0d,1 ; Set mask opposite of expected + csll gr8,gr7,gr8,cc1,1 + test_icc 1 1 0 1 icc1 + test_gr_immed 2,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_immed 2,gr8 + set_icc 0x0f,1 ; Set mask opposite of expected + csll gr8,gr7,gr8,cc1,1 + test_icc 1 1 1 1 icc1 + test_gr_immed 2,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_immed 1,gr8 + set_icc 0x07,1 ; Set mask opposite of expected + csll gr8,gr7,gr8,cc5,1 + test_icc 0 1 1 1 icc1 + test_gr_immed 1,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_immed 2,gr8 + set_icc 0x0a,1 ; Set mask opposite of expected + csll gr8,gr7,gr8,cc5,1 + test_icc 1 0 1 0 icc1 + test_gr_immed 2,gr8 + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_immed 2,gr8 + set_icc 0x0d,2 ; Set mask opposite of expected + csll gr8,gr7,gr8,cc2,0 + test_icc 1 1 0 1 icc2 + test_gr_immed 2,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_immed 2,gr8 + set_icc 0x0f,2 ; Set mask opposite of expected + csll gr8,gr7,gr8,cc2,0 + test_icc 1 1 1 1 icc2 + test_gr_immed 2,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_immed 1,gr8 + set_icc 0x07,2 ; Set mask opposite of expected + csll gr8,gr7,gr8,cc6,1 + test_icc 0 1 1 1 icc2 + test_gr_immed 1,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_immed 2,gr8 + set_icc 0x0a,2 ; Set mask opposite of expected + csll gr8,gr7,gr8,cc6,1 + test_icc 1 0 1 0 icc2 + test_gr_immed 2,gr8 + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_immed 2,gr8 + set_icc 0x0d,3 ; Set mask opposite of expected + csll gr8,gr7,gr8,cc3,0 + test_icc 1 1 0 1 icc3 + test_gr_immed 2,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_immed 2,gr8 + set_icc 0x0f,3 ; Set mask opposite of expected + csll gr8,gr7,gr8,cc3,0 + test_icc 1 1 1 1 icc3 + test_gr_immed 2,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_immed 1,gr8 + set_icc 0x07,3 ; Set mask opposite of expected + csll gr8,gr7,gr8,cc7,1 + test_icc 0 1 1 1 icc3 + test_gr_immed 1,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_immed 2,gr8 + set_icc 0x0a,3 ; Set mask opposite of expected + csll gr8,gr7,gr8,cc7,1 + test_icc 1 0 1 0 icc3 + test_gr_immed 2,gr8 + + pass diff --git a/sim/testsuite/sim/frv/csllcc.cgs b/sim/testsuite/sim/frv/csllcc.cgs new file mode 100644 index 0000000..0c5b9af --- /dev/null +++ b/sim/testsuite/sim/frv/csllcc.cgs @@ -0,0 +1,180 @@ +# frv testcase for csllcc $GRi,$GRj,$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global csllcc +csllcc: + set_spr_immed 0x1b1b,cccr + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_immed 2,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + csllcc gr8,gr7,gr8,cc0,1 + test_icc 0 0 0 1 icc0 + test_gr_immed 2,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_immed 2,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + csllcc gr8,gr7,gr8,cc0,1 + test_icc 0 0 0 1 icc0 + test_gr_immed 4,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_immed 1,gr8 + set_icc 0x07,0 ; Set mask opposite of expected + csllcc gr8,gr7,gr8,cc4,1 + test_icc 1 0 0 1 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_immed 2,gr8 + set_icc 0x08,0 ; Set mask opposite of expected + csllcc gr8,gr7,gr8,cc4,1 + test_icc 0 1 1 0 icc0 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_immed 2,gr8 + set_icc 0x0d,0 ; Set mask opposite of expected + csllcc gr8,gr7,gr8,cc0,0 + test_icc 1 1 0 1 icc0 + test_gr_immed 2,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_immed 2,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + csllcc gr8,gr7,gr8,cc0,0 + test_icc 1 1 1 1 icc0 + test_gr_immed 2,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_immed 1,gr8 + set_icc 0x07,0 ; Set mask opposite of expected + csllcc gr8,gr7,gr8,cc4,0 + test_icc 0 1 1 1 icc0 + test_gr_immed 1,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_immed 2,gr8 + set_icc 0x0a,0 ; Set mask opposite of expected + csllcc gr8,gr7,gr8,cc4,0 + test_icc 1 0 1 0 icc0 + test_gr_immed 2,gr8 + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_immed 2,gr8 + set_icc 0x0f,1 ; Set mask opposite of expected + csllcc gr8,gr7,gr8,cc1,0 + test_icc 0 0 0 1 icc1 + test_gr_immed 2,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_immed 2,gr8 + set_icc 0x0f,1 ; Set mask opposite of expected + csllcc gr8,gr7,gr8,cc1,0 + test_icc 0 0 0 1 icc1 + test_gr_immed 4,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_immed 1,gr8 + set_icc 0x07,1 ; Set mask opposite of expected + csllcc gr8,gr7,gr8,cc5,0 + test_icc 1 0 0 1 icc1 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_immed 2,gr8 + set_icc 0x08,1 ; Set mask opposite of expected + csllcc gr8,gr7,gr8,cc5,0 + test_icc 0 1 1 0 icc1 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_immed 2,gr8 + set_icc 0x0d,1 ; Set mask opposite of expected + csllcc gr8,gr7,gr8,cc1,1 + test_icc 1 1 0 1 icc1 + test_gr_immed 2,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_immed 2,gr8 + set_icc 0x0f,1 ; Set mask opposite of expected + csllcc gr8,gr7,gr8,cc1,1 + test_icc 1 1 1 1 icc1 + test_gr_immed 2,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_immed 1,gr8 + set_icc 0x07,1 ; Set mask opposite of expected + csllcc gr8,gr7,gr8,cc5,1 + test_icc 0 1 1 1 icc1 + test_gr_immed 1,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_immed 2,gr8 + set_icc 0x0a,1 ; Set mask opposite of expected + csllcc gr8,gr7,gr8,cc5,1 + test_icc 1 0 1 0 icc1 + test_gr_immed 2,gr8 + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_immed 2,gr8 + set_icc 0x0d,2 ; Set mask opposite of expected + csllcc gr8,gr7,gr8,cc2,0 + test_icc 1 1 0 1 icc2 + test_gr_immed 2,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_immed 2,gr8 + set_icc 0x0f,2 ; Set mask opposite of expected + csllcc gr8,gr7,gr8,cc2,0 + test_icc 1 1 1 1 icc2 + test_gr_immed 2,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_immed 1,gr8 + set_icc 0x07,2 ; Set mask opposite of expected + csllcc gr8,gr7,gr8,cc6,1 + test_icc 0 1 1 1 icc2 + test_gr_immed 1,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_immed 2,gr8 + set_icc 0x0a,2 ; Set mask opposite of expected + csllcc gr8,gr7,gr8,cc6,1 + test_icc 1 0 1 0 icc2 + test_gr_immed 2,gr8 + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_immed 2,gr8 + set_icc 0x0d,3 ; Set mask opposite of expected + csllcc gr8,gr7,gr8,cc3,0 + test_icc 1 1 0 1 icc3 + test_gr_immed 2,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_immed 2,gr8 + set_icc 0x0f,3 ; Set mask opposite of expected + csllcc gr8,gr7,gr8,cc3,0 + test_icc 1 1 1 1 icc3 + test_gr_immed 2,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_immed 1,gr8 + set_icc 0x07,3 ; Set mask opposite of expected + csllcc gr8,gr7,gr8,cc7,1 + test_icc 0 1 1 1 icc3 + test_gr_immed 1,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_immed 2,gr8 + set_icc 0x0a,3 ; Set mask opposite of expected + csllcc gr8,gr7,gr8,cc7,1 + test_icc 1 0 1 0 icc3 + test_gr_immed 2,gr8 + + pass diff --git a/sim/testsuite/sim/frv/csmul.cgs b/sim/testsuite/sim/frv/csmul.cgs new file mode 100644 index 0000000..25346e7 --- /dev/null +++ b/sim/testsuite/sim/frv/csmul.cgs @@ -0,0 +1,1044 @@ +# frv testcase for csmul $GRi,$GRj,$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global csmul +csmul: + set_spr_immed 0x1b1b,cccr + + ; Positive operands + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc4,1 + test_gr_immed 0,gr8 + test_gr_immed 6,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc4,1 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed 2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + csmul gr7,gr8,gr8,cc4,1 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc4,1 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + csmul gr7,gr8,gr8,cc4,1 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc4,1 + test_gr_immed 0,gr8 + test_gr_limmed 0x7fff,0xfffe,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc4,1 + test_gr_immed 0,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed 4,gr8 + csmul gr7,gr8,gr8,cc4,1 + test_gr_immed 1,gr8 + test_gr_limmed 0x0000,0x0000,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result + set_gr_limmed 0x7fff,0xffff,gr8 + csmul gr7,gr8,gr8,cc4,1 + test_gr_limmed 0x3fff,0xffff,gr8 + test_gr_immed 0x00000001,gr9 + + ; Mixed operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc4,1 + test_gr_immed -1,gr8 + test_gr_immed -6,gr9 + + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc4,1 + test_gr_immed -1,gr8 + test_gr_immed -6,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc4,1 + test_gr_immed -1,gr8 + test_gr_immed -2,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + csmul gr7,gr8,gr8,cc4,1 + test_gr_immed -1,gr8 + test_gr_immed -2,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc4,1 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + csmul gr7,gr8,gr8,cc4,1 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc4,1 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0xbfff,0xfffe,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc4,1 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc4,1 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0x7fff,0xfffe,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed -4,gr8 + csmul gr7,gr8,gr8,cc4,1 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0x0000,0x0000,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result + set_gr_limmed 0x8000,0x0000,gr8 + csmul gr7,gr8,gr8,cc4,1 + test_gr_limmed 0xc000,0x0000,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + ; Negative operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc4,1 + test_gr_immed 0,gr8 + test_gr_immed 6,gr9 + + set_gr_immed -1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc4,1 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed -1,gr8 + csmul gr7,gr8,gr8,cc4,1 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc4,1 + test_gr_immed 0,gr8 + test_gr_limmed 0x7fff,0xfffe,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc4,1 + test_gr_immed 0,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result + set_gr_immed -4,gr8 + csmul gr7,gr8,gr8,cc4,1 + test_gr_immed 1,gr8 + test_gr_immed 0x00000000,gr9 + + set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result + set_gr_limmed 0x8000,0x0001,gr8 + csmul gr7,gr8,gr8,cc4,1 + test_gr_limmed 0x3fff,0xffff,gr8 + test_gr_immed 0x00000001,gr9 + + + set_gr_limmed 0x8000,0x0000,gr7 ; max positive result + set_gr_limmed 0x8000,0x0000,gr8 + csmul gr7,gr8,gr8,cc4,1 + test_gr_limmed 0x4000,0x0000,gr8 + test_gr_immed 0x00000000,gr9 + + ; Positive operands + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc5,0 + test_gr_immed 0,gr8 + test_gr_immed 6,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc5,0 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed 2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + csmul gr7,gr8,gr8,cc5,0 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc5,0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + csmul gr7,gr8,gr8,cc5,0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc5,0 + test_gr_immed 0,gr8 + test_gr_limmed 0x7fff,0xfffe,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc5,0 + test_gr_immed 0,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed 4,gr8 + csmul gr7,gr8,gr8,cc5,0 + test_gr_immed 1,gr8 + test_gr_limmed 0x0000,0x0000,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result + set_gr_limmed 0x7fff,0xffff,gr8 + csmul gr7,gr8,gr8,cc5,0 + test_gr_limmed 0x3fff,0xffff,gr8 + test_gr_immed 0x00000001,gr9 + + ; Mixed operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc5,0 + test_gr_immed -1,gr8 + test_gr_immed -6,gr9 + + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc5,0 + test_gr_immed -1,gr8 + test_gr_immed -6,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc5,0 + test_gr_immed -1,gr8 + test_gr_immed -2,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + csmul gr7,gr8,gr8,cc5,0 + test_gr_immed -1,gr8 + test_gr_immed -2,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc5,0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + csmul gr7,gr8,gr8,cc5,0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc5,0 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0xbfff,0xfffe,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc5,0 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc5,0 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0x7fff,0xfffe,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed -4,gr8 + csmul gr7,gr8,gr8,cc5,0 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0x0000,0x0000,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result + set_gr_limmed 0x8000,0x0000,gr8 + csmul gr7,gr8,gr8,cc5,0 + test_gr_limmed 0xc000,0x0000,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + ; Negative operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc5,0 + test_gr_immed 0,gr8 + test_gr_immed 6,gr9 + + set_gr_immed -1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc5,0 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed -1,gr8 + csmul gr7,gr8,gr8,cc5,0 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc5,0 + test_gr_immed 0,gr8 + test_gr_limmed 0x7fff,0xfffe,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc5,0 + test_gr_immed 0,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result + set_gr_immed -4,gr8 + csmul gr7,gr8,gr8,cc5,0 + test_gr_immed 1,gr8 + test_gr_immed 0x00000000,gr9 + + set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result + set_gr_limmed 0x8000,0x0001,gr8 + csmul gr7,gr8,gr8,cc5,0 + test_gr_limmed 0x3fff,0xffff,gr8 + test_gr_immed 0x00000001,gr9 + + + set_gr_limmed 0x8000,0x0000,gr7 ; max positive result + set_gr_limmed 0x8000,0x0000,gr8 + csmul gr7,gr8,gr8,cc5,0 + test_gr_limmed 0x4000,0x0000,gr8 + test_gr_immed 0x00000000,gr9 + + ; Positive operands + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc4,0 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc4,0 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + csmul gr7,gr8,gr8,cc4,0 + test_gr_immed 1,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc4,0 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + csmul gr7,gr8,gr8,cc4,0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc4,0 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc4,0 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed 4,gr8 + csmul gr7,gr8,gr8,cc4,0 + test_gr_immed 4,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result + set_gr_limmed 0x7fff,0xffff,gr8 + csmul gr7,gr8,gr8,cc4,0 + test_gr_limmed 0x7fff,0xffff,gr8 + test_gr_immed 0,gr9 + + ; Mixed operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc4,0 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc4,0 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc4,0 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + csmul gr7,gr8,gr8,cc4,0 + test_gr_immed 1,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc4,0 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + csmul gr7,gr8,gr8,cc4,0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc4,0 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc4,0 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc4,0 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed -4,gr8 + csmul gr7,gr8,gr8,cc4,0 + test_gr_immed -4,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result + set_gr_limmed 0x8000,0x0000,gr8 + csmul gr7,gr8,gr8,cc4,0 + test_gr_limmed 0x8000,0x0000,gr8 + test_gr_immed 0,gr9 + + ; Negative operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc4,0 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc4,0 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed -1,gr8 + csmul gr7,gr8,gr8,cc4,0 + test_gr_immed -1,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc4,0 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc4,0 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result + set_gr_immed -4,gr8 + csmul gr7,gr8,gr8,cc4,0 + test_gr_immed -4,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result + set_gr_limmed 0x8000,0x0001,gr8 + csmul gr7,gr8,gr8,cc4,0 + test_gr_limmed 0x8000,0x0001,gr8 + test_gr_immed 0,gr9 + + + set_gr_limmed 0x8000,0x0000,gr7 ; max positive result + set_gr_limmed 0x8000,0x0000,gr8 + csmul gr7,gr8,gr8,cc4,0 + test_gr_limmed 0x8000,0x0000,gr8 + test_gr_immed 0,gr9 + + ; Positive operands + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc5,1 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc5,1 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + csmul gr7,gr8,gr8,cc5,1 + test_gr_immed 1,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc5,1 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + csmul gr7,gr8,gr8,cc5,1 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc5,1 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc5,1 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed 4,gr8 + csmul gr7,gr8,gr8,cc5,1 + test_gr_immed 4,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result + set_gr_limmed 0x7fff,0xffff,gr8 + csmul gr7,gr8,gr8,cc5,1 + test_gr_limmed 0x7fff,0xffff,gr8 + test_gr_immed 0,gr9 + + ; Mixed operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc5,1 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc5,1 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc5,1 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + csmul gr7,gr8,gr8,cc5,1 + test_gr_immed 1,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc5,1 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + csmul gr7,gr8,gr8,cc5,1 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc5,1 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc5,1 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc5,1 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed -4,gr8 + csmul gr7,gr8,gr8,cc5,1 + test_gr_immed -4,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result + set_gr_limmed 0x8000,0x0000,gr8 + csmul gr7,gr8,gr8,cc5,1 + test_gr_limmed 0x8000,0x0000,gr8 + test_gr_immed 0,gr9 + + ; Negative operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc5,1 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc5,1 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed -1,gr8 + csmul gr7,gr8,gr8,cc5,1 + test_gr_immed -1,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc5,1 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc5,1 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result + set_gr_immed -4,gr8 + csmul gr7,gr8,gr8,cc5,1 + test_gr_immed -4,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result + set_gr_limmed 0x8000,0x0001,gr8 + csmul gr7,gr8,gr8,cc5,1 + test_gr_limmed 0x8000,0x0001,gr8 + test_gr_immed 0,gr9 + + + set_gr_limmed 0x8000,0x0000,gr7 ; max positive result + set_gr_limmed 0x8000,0x0000,gr8 + csmul gr7,gr8,gr8,cc5,1 + test_gr_limmed 0x8000,0x0000,gr8 + test_gr_immed 0,gr9 + + ; Positive operands + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc6,0 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc6,0 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + csmul gr7,gr8,gr8,cc6,0 + test_gr_immed 1,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc6,0 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + csmul gr7,gr8,gr8,cc6,0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc6,0 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc6,0 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed 4,gr8 + csmul gr7,gr8,gr8,cc6,0 + test_gr_immed 4,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result + set_gr_limmed 0x7fff,0xffff,gr8 + csmul gr7,gr8,gr8,cc6,0 + test_gr_limmed 0x7fff,0xffff,gr8 + test_gr_immed 0,gr9 + + ; Mixed operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc6,0 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc6,0 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc6,0 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + csmul gr7,gr8,gr8,cc6,0 + test_gr_immed 1,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc6,0 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + csmul gr7,gr8,gr8,cc6,0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc6,0 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc6,0 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc6,0 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed -4,gr8 + csmul gr7,gr8,gr8,cc6,0 + test_gr_immed -4,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result + set_gr_limmed 0x8000,0x0000,gr8 + csmul gr7,gr8,gr8,cc6,0 + test_gr_limmed 0x8000,0x0000,gr8 + test_gr_immed 0,gr9 + + ; Negative operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc6,0 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc6,0 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed -1,gr8 + csmul gr7,gr8,gr8,cc6,0 + test_gr_immed -1,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc6,0 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc6,0 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result + set_gr_immed -4,gr8 + csmul gr7,gr8,gr8,cc6,0 + test_gr_immed -4,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result + set_gr_limmed 0x8000,0x0001,gr8 + csmul gr7,gr8,gr8,cc6,0 + test_gr_limmed 0x8000,0x0001,gr8 + test_gr_immed 0,gr9 + + + set_gr_limmed 0x8000,0x0000,gr7 ; max positive result + set_gr_limmed 0x8000,0x0000,gr8 + csmul gr7,gr8,gr8,cc6,0 + test_gr_limmed 0x8000,0x0000,gr8 + test_gr_immed 0,gr9 + + ; Positive operands + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc7,1 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc7,1 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + csmul gr7,gr8,gr8,cc7,1 + test_gr_immed 1,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc7,1 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + csmul gr7,gr8,gr8,cc7,1 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc7,1 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc7,1 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed 4,gr8 + csmul gr7,gr8,gr8,cc7,1 + test_gr_immed 4,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result + set_gr_limmed 0x7fff,0xffff,gr8 + csmul gr7,gr8,gr8,cc7,1 + test_gr_limmed 0x7fff,0xffff,gr8 + test_gr_immed 0,gr9 + + ; Mixed operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + csmul gr7,gr8,gr8,cc7,1 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc7,1 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc7,1 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + csmul gr7,gr8,gr8,cc7,1 + test_gr_immed 1,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc7,1 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + csmul gr7,gr8,gr8,cc7,1 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc7,1 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc7,1 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc7,1 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed -4,gr8 + csmul gr7,gr8,gr8,cc7,1 + test_gr_immed -4,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result + set_gr_limmed 0x8000,0x0000,gr8 + csmul gr7,gr8,gr8,cc7,1 + test_gr_limmed 0x8000,0x0000,gr8 + test_gr_immed 0,gr9 + + ; Negative operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc7,1 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc7,1 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed -1,gr8 + csmul gr7,gr8,gr8,cc7,1 + test_gr_immed -1,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc7,1 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + csmul gr7,gr8,gr8,cc7,1 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result + set_gr_immed -4,gr8 + csmul gr7,gr8,gr8,cc7,1 + test_gr_immed -4,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result + set_gr_limmed 0x8000,0x0001,gr8 + csmul gr7,gr8,gr8,cc7,1 + test_gr_limmed 0x8000,0x0001,gr8 + test_gr_immed 0,gr9 + + + set_gr_limmed 0x8000,0x0000,gr7 ; max positive result + set_gr_limmed 0x8000,0x0000,gr8 + csmul gr7,gr8,gr8,cc7,1 + test_gr_limmed 0x8000,0x0000,gr8 + test_gr_immed 0,gr9 + + pass diff --git a/sim/testsuite/sim/frv/csmulcc.cgs b/sim/testsuite/sim/frv/csmulcc.cgs new file mode 100644 index 0000000..26c7e66 --- /dev/null +++ b/sim/testsuite/sim/frv/csmulcc.cgs @@ -0,0 +1,1380 @@ +# frv testcase for csmulcc $GRi,$GRj,$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global csmulcc +csmulcc: + set_spr_immed 0x1b1b,cccr + + ; Positive operands + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + set_icc 0xc,0 + csmulcc gr7,gr8,gr8,cc0,1 + test_icc 0 0 0 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 6,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed 2,gr8 + set_icc 0xd,0 + csmulcc gr7,gr8,gr8,cc0,1 + test_icc 0 0 0 1 icc0 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed 2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + set_icc 0xe,0 + csmulcc gr7,gr8,gr8,cc4,1 + test_icc 0 0 1 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed 2,gr8 + set_icc 0xb,0 + csmulcc gr7,gr8,gr8,cc4,1 + test_icc 0 1 1 1 icc0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + set_icc 0x8,0 + csmulcc gr7,gr8,gr8,cc0,1 + test_icc 0 1 0 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result + set_gr_immed 2,gr8 + set_icc 0xd,0 + csmulcc gr7,gr8,gr8,cc0,1 + test_icc 0 0 0 1 icc0 + test_gr_immed 0,gr8 + test_gr_limmed 0x7fff,0xfffe,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed 2,gr8 + set_icc 0xe,0 + csmulcc gr7,gr8,gr8,cc4,1 + test_icc 0 0 1 0 icc0 + test_gr_immed 0,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed 4,gr8 + set_icc 0xf,0 + csmulcc gr7,gr8,gr8,cc4,1 + test_icc 0 0 1 1 icc0 + test_gr_immed 1,gr8 + test_gr_limmed 0x0000,0x0000,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result + set_gr_limmed 0x7fff,0xffff,gr8 + set_icc 0xc,0 + csmulcc gr7,gr8,gr8,cc0,1 + test_icc 0 0 0 0 icc0 + test_gr_limmed 0x3fff,0xffff,gr8 + test_gr_immed 0x00000001,gr9 + + ; Mixed operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + set_icc 0x5,0 + csmulcc gr7,gr8,gr8,cc0,1 + test_icc 1 0 0 1 icc0 + test_gr_immed -1,gr8 + test_gr_immed -6,gr9 + + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + set_icc 0x6,0 + csmulcc gr7,gr8,gr8,cc4,1 + test_icc 1 0 1 0 icc0 + test_gr_immed -1,gr8 + test_gr_immed -6,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + set_icc 0x7,0 + csmulcc gr7,gr8,gr8,cc4,1 + test_icc 1 0 1 1 icc0 + test_gr_immed -1,gr8 + test_gr_immed -2,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + set_icc 0x4,0 + csmulcc gr7,gr8,gr8,cc0,1 + test_icc 1 0 0 0 icc0 + test_gr_immed -1,gr8 + test_gr_immed -2,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed -2,gr8 + set_icc 0x9,0 + csmulcc gr7,gr8,gr8,cc0,1 + test_icc 0 1 0 1 icc0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + set_icc 0xa,0 + csmulcc gr7,gr8,gr8,cc4,1 + test_icc 0 1 1 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result + set_gr_immed -2,gr8 + set_icc 0x7,0 + csmulcc gr7,gr8,gr8,cc4,1 + test_icc 1 0 1 1 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0xbfff,0xfffe,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + set_icc 0x4,0 + csmulcc gr7,gr8,gr8,cc0,1 + test_icc 1 0 0 0 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result + set_gr_immed -2,gr8 + set_icc 0x5,0 + csmulcc gr7,gr8,gr8,cc0,1 + test_icc 1 0 0 1 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0x7fff,0xfffe,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed -4,gr8 + set_icc 0x6,0 + csmulcc gr7,gr8,gr8,cc4,1 + test_icc 1 0 1 0 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0x0000,0x0000,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x7,0 + csmulcc gr7,gr8,gr8,cc4,1 + test_icc 1 0 1 1 icc0 + test_gr_limmed 0xc000,0x0000,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + ; Negative operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + set_icc 0xc,0 + csmulcc gr7,gr8,gr8,cc0,1 + test_icc 0 0 0 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 6,gr9 + + set_gr_immed -1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + set_icc 0xd,0 + csmulcc gr7,gr8,gr8,cc0,1 + test_icc 0 0 0 1 icc0 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed -1,gr8 + set_icc 0xe,0 + csmulcc gr7,gr8,gr8,cc4,1 + test_icc 0 0 1 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result + set_gr_immed -2,gr8 + set_icc 0xf,0 + csmulcc gr7,gr8,gr8,cc4,1 + test_icc 0 0 1 1 icc0 + test_gr_immed 0,gr8 + test_gr_limmed 0x7fff,0xfffe,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + set_icc 0xc,0 + csmulcc gr7,gr8,gr8,cc0,1 + test_icc 0 0 0 0 icc0 + test_gr_immed 0,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result + set_gr_immed -4,gr8 + set_icc 0xd,0 + csmulcc gr7,gr8,gr8,cc0,1 + test_icc 0 0 0 1 icc0 + test_gr_immed 1,gr8 + test_gr_immed 0x00000000,gr9 + + set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result + set_gr_limmed 0x8000,0x0001,gr8 + set_icc 0xe,0 + csmulcc gr7,gr8,gr8,cc4,1 + test_icc 0 0 1 0 icc0 + test_gr_limmed 0x3fff,0xffff,gr8 + test_gr_immed 0x00000001,gr9 + + + set_gr_limmed 0x8000,0x0000,gr7 ; max positive result + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0xf,0 + csmulcc gr7,gr8,gr8,cc4,1 + test_icc 0 0 1 1 icc0 + test_gr_limmed 0x4000,0x0000,gr8 + test_gr_immed 0x00000000,gr9 + + ; Positive operands + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + set_icc 0x0,0 + csmulcc gr7,gr8,gr8,cc0,0 + test_icc 0 0 0 0 icc0 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed 2,gr8 + set_icc 0x1,0 + csmulcc gr7,gr8,gr8,cc0,0 + test_icc 0 0 0 1 icc0 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + set_icc 0x2,0 + csmulcc gr7,gr8,gr8,cc4,0 + test_icc 0 0 1 0 icc0 + test_gr_immed 1,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed 2,gr8 + set_icc 0x3,0 + csmulcc gr7,gr8,gr8,cc4,0 + test_icc 0 0 1 1 icc0 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + set_icc 0x4,0 + csmulcc gr7,gr8,gr8,cc0,0 + test_icc 0 1 0 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result + set_gr_immed 2,gr8 + set_icc 0x5,0 + csmulcc gr7,gr8,gr8,cc0,0 + test_icc 0 1 0 1 icc0 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed 2,gr8 + set_icc 0x6,0 + csmulcc gr7,gr8,gr8,cc4,0 + test_icc 0 1 1 0 icc0 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed 4,gr8 + set_icc 0x7,0 + csmulcc gr7,gr8,gr8,cc4,0 + test_icc 0 1 1 1 icc0 + test_gr_immed 4,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result + set_gr_limmed 0x7fff,0xffff,gr8 + set_icc 0x8,0 + csmulcc gr7,gr8,gr8,cc0,0 + test_icc 1 0 0 0 icc0 + test_gr_limmed 0x7fff,0xffff,gr8 + test_gr_immed 0,gr9 + + ; Mixed operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + set_icc 0x9,0 + csmulcc gr7,gr8,gr8,cc0,0 + test_icc 1 0 0 1 icc0 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + set_icc 0xa,0 + csmulcc gr7,gr8,gr8,cc4,0 + test_icc 1 0 1 0 icc0 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + set_icc 0xb,0 + csmulcc gr7,gr8,gr8,cc4,0 + test_icc 1 0 1 1 icc0 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + set_icc 0xc,0 + csmulcc gr7,gr8,gr8,cc0,0 + test_icc 1 1 0 0 icc0 + test_gr_immed 1,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed -2,gr8 + set_icc 0xd,0 + csmulcc gr7,gr8,gr8,cc0,0 + test_icc 1 1 0 1 icc0 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + set_icc 0xe,0 + csmulcc gr7,gr8,gr8,cc4,0 + test_icc 1 1 1 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result + set_gr_immed -2,gr8 + set_icc 0xf,0 + csmulcc gr7,gr8,gr8,cc4,0 + test_icc 1 1 1 1 icc0 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + set_icc 0x0,0 + csmulcc gr7,gr8,gr8,cc0,0 + test_icc 0 0 0 0 icc0 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result + set_gr_immed -2,gr8 + set_icc 0x1,0 + csmulcc gr7,gr8,gr8,cc0,0 + test_icc 0 0 0 1 icc0 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed -4,gr8 + set_icc 0x2,0 + csmulcc gr7,gr8,gr8,cc4,0 + test_icc 0 0 1 0 icc0 + test_gr_immed -4,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x3,0 + csmulcc gr7,gr8,gr8,cc4,0 + test_icc 0 0 1 1 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + test_gr_immed 0,gr9 + + ; Negative operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + set_icc 0x4,0 + csmulcc gr7,gr8,gr8,cc0,0 + test_icc 0 1 0 0 icc0 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + set_icc 0x5,0 + csmulcc gr7,gr8,gr8,cc0,0 + test_icc 0 1 0 1 icc0 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed -1,gr8 + set_icc 0x6,0 + csmulcc gr7,gr8,gr8,cc4,0 + test_icc 0 1 1 0 icc0 + test_gr_immed -1,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result + set_gr_immed -2,gr8 + set_icc 0x7,0 + csmulcc gr7,gr8,gr8,cc4,0 + test_icc 0 1 1 1 icc0 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + set_icc 0x8,0 + csmulcc gr7,gr8,gr8,cc0,0 + test_icc 1 0 0 0 icc0 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result + set_gr_immed -4,gr8 + set_icc 0x9,0 + csmulcc gr7,gr8,gr8,cc0,0 + test_icc 1 0 0 1 icc0 + test_gr_immed -4,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result + set_gr_limmed 0x8000,0x0001,gr8 + set_icc 0xa,0 + csmulcc gr7,gr8,gr8,cc4,0 + test_icc 1 0 1 0 icc0 + test_gr_limmed 0x8000,0x0001,gr8 + test_gr_immed 0,gr9 + + + set_gr_limmed 0x8000,0x0000,gr7 ; max positive result + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0xb,0 + csmulcc gr7,gr8,gr8,cc4,0 + test_icc 1 0 1 1 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + test_gr_immed 0,gr9 + + ; Positive operands + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + set_icc 0xc,1 + csmulcc gr7,gr8,gr8,cc1,0 + test_icc 0 0 0 0 icc1 + test_gr_immed 0,gr8 + test_gr_immed 6,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed 2,gr8 + set_icc 0xd,1 + csmulcc gr7,gr8,gr8,cc1,0 + test_icc 0 0 0 1 icc1 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed 2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + set_icc 0xe,1 + csmulcc gr7,gr8,gr8,cc5,0 + test_icc 0 0 1 0 icc1 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed 2,gr8 + set_icc 0xb,1 + csmulcc gr7,gr8,gr8,cc5,0 + test_icc 0 1 1 1 icc1 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + set_icc 0x8,1 + csmulcc gr7,gr8,gr8,cc1,0 + test_icc 0 1 0 0 icc1 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result + set_gr_immed 2,gr8 + set_icc 0xd,1 + csmulcc gr7,gr8,gr8,cc1,0 + test_icc 0 0 0 1 icc1 + test_gr_immed 0,gr8 + test_gr_limmed 0x7fff,0xfffe,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed 2,gr8 + set_icc 0xe,1 + csmulcc gr7,gr8,gr8,cc5,0 + test_icc 0 0 1 0 icc1 + test_gr_immed 0,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed 4,gr8 + set_icc 0xf,1 + csmulcc gr7,gr8,gr8,cc5,0 + test_icc 0 0 1 1 icc1 + test_gr_immed 1,gr8 + test_gr_limmed 0x0000,0x0000,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result + set_gr_limmed 0x7fff,0xffff,gr8 + set_icc 0xc,1 + csmulcc gr7,gr8,gr8,cc1,0 + test_icc 0 0 0 0 icc1 + test_gr_limmed 0x3fff,0xffff,gr8 + test_gr_immed 0x00000001,gr9 + + ; Mixed operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + set_icc 0x5,1 + csmulcc gr7,gr8,gr8,cc1,0 + test_icc 1 0 0 1 icc1 + test_gr_immed -1,gr8 + test_gr_immed -6,gr9 + + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + set_icc 0x6,1 + csmulcc gr7,gr8,gr8,cc5,0 + test_icc 1 0 1 0 icc1 + test_gr_immed -1,gr8 + test_gr_immed -6,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + set_icc 0x7,1 + csmulcc gr7,gr8,gr8,cc5,0 + test_icc 1 0 1 1 icc1 + test_gr_immed -1,gr8 + test_gr_immed -2,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + set_icc 0x4,1 + csmulcc gr7,gr8,gr8,cc1,0 + test_icc 1 0 0 0 icc1 + test_gr_immed -1,gr8 + test_gr_immed -2,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed -2,gr8 + set_icc 0x9,1 + csmulcc gr7,gr8,gr8,cc1,0 + test_icc 0 1 0 1 icc1 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + set_icc 0xa,1 + csmulcc gr7,gr8,gr8,cc5,0 + test_icc 0 1 1 0 icc1 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result + set_gr_immed -2,gr8 + set_icc 0x7,1 + csmulcc gr7,gr8,gr8,cc5,0 + test_icc 1 0 1 1 icc1 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0xbfff,0xfffe,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + set_icc 0x4,1 + csmulcc gr7,gr8,gr8,cc1,0 + test_icc 1 0 0 0 icc1 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result + set_gr_immed -2,gr8 + set_icc 0x5,1 + csmulcc gr7,gr8,gr8,cc1,0 + test_icc 1 0 0 1 icc1 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0x7fff,0xfffe,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed -4,gr8 + set_icc 0x6,1 + csmulcc gr7,gr8,gr8,cc5,0 + test_icc 1 0 1 0 icc1 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0x0000,0x0000,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x7,1 + csmulcc gr7,gr8,gr8,cc5,0 + test_icc 1 0 1 1 icc1 + test_gr_limmed 0xc000,0x0000,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + ; Negative operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + set_icc 0xc,1 + csmulcc gr7,gr8,gr8,cc1,0 + test_icc 0 0 0 0 icc1 + test_gr_immed 0,gr8 + test_gr_immed 6,gr9 + + set_gr_immed -1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + set_icc 0xd,1 + csmulcc gr7,gr8,gr8,cc1,0 + test_icc 0 0 0 1 icc1 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed -1,gr8 + set_icc 0xe,1 + csmulcc gr7,gr8,gr8,cc5,0 + test_icc 0 0 1 0 icc1 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result + set_gr_immed -2,gr8 + set_icc 0xf,1 + csmulcc gr7,gr8,gr8,cc5,0 + test_icc 0 0 1 1 icc1 + test_gr_immed 0,gr8 + test_gr_limmed 0x7fff,0xfffe,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + set_icc 0xc,1 + csmulcc gr7,gr8,gr8,cc1,0 + test_icc 0 0 0 0 icc1 + test_gr_immed 0,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result + set_gr_immed -4,gr8 + set_icc 0xd,1 + csmulcc gr7,gr8,gr8,cc1,0 + test_icc 0 0 0 1 icc1 + test_gr_immed 1,gr8 + test_gr_immed 0x00000000,gr9 + + set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result + set_gr_limmed 0x8000,0x0001,gr8 + set_icc 0xe,1 + csmulcc gr7,gr8,gr8,cc5,0 + test_icc 0 0 1 0 icc1 + test_gr_limmed 0x3fff,0xffff,gr8 + test_gr_immed 0x00000001,gr9 + + + set_gr_limmed 0x8000,0x0000,gr7 ; max positive result + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0xf,1 + csmulcc gr7,gr8,gr8,cc5,0 + test_icc 0 0 1 1 icc1 + test_gr_limmed 0x4000,0x0000,gr8 + test_gr_immed 0x00000000,gr9 + + ; Positive operands + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + set_icc 0x0,1 + csmulcc gr7,gr8,gr8,cc1,1 + test_icc 0 0 0 0 icc1 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed 2,gr8 + set_icc 0x1,1 + csmulcc gr7,gr8,gr8,cc1,1 + test_icc 0 0 0 1 icc1 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + set_icc 0x2,1 + csmulcc gr7,gr8,gr8,cc5,1 + test_icc 0 0 1 0 icc1 + test_gr_immed 1,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed 2,gr8 + set_icc 0x3,1 + csmulcc gr7,gr8,gr8,cc5,1 + test_icc 0 0 1 1 icc1 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + set_icc 0x4,1 + csmulcc gr7,gr8,gr8,cc1,1 + test_icc 0 1 0 0 icc1 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result + set_gr_immed 2,gr8 + set_icc 0x5,1 + csmulcc gr7,gr8,gr8,cc1,1 + test_icc 0 1 0 1 icc1 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed 2,gr8 + set_icc 0x6,1 + csmulcc gr7,gr8,gr8,cc5,1 + test_icc 0 1 1 0 icc1 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed 4,gr8 + set_icc 0x7,1 + csmulcc gr7,gr8,gr8,cc5,1 + test_icc 0 1 1 1 icc1 + test_gr_immed 4,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result + set_gr_limmed 0x7fff,0xffff,gr8 + set_icc 0x8,1 + csmulcc gr7,gr8,gr8,cc1,1 + test_icc 1 0 0 0 icc1 + test_gr_limmed 0x7fff,0xffff,gr8 + test_gr_immed 0,gr9 + + ; Mixed operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + set_icc 0x9,1 + csmulcc gr7,gr8,gr8,cc1,1 + test_icc 1 0 0 1 icc1 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + set_icc 0xa,1 + csmulcc gr7,gr8,gr8,cc5,1 + test_icc 1 0 1 0 icc1 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + set_icc 0xb,1 + csmulcc gr7,gr8,gr8,cc5,1 + test_icc 1 0 1 1 icc1 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + set_icc 0xc,1 + csmulcc gr7,gr8,gr8,cc1,1 + test_icc 1 1 0 0 icc1 + test_gr_immed 1,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed -2,gr8 + set_icc 0xd,1 + csmulcc gr7,gr8,gr8,cc1,1 + test_icc 1 1 0 1 icc1 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + set_icc 0xe,1 + csmulcc gr7,gr8,gr8,cc5,1 + test_icc 1 1 1 0 icc1 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result + set_gr_immed -2,gr8 + set_icc 0xf,1 + csmulcc gr7,gr8,gr8,cc5,1 + test_icc 1 1 1 1 icc1 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + set_icc 0x0,1 + csmulcc gr7,gr8,gr8,cc1,1 + test_icc 0 0 0 0 icc1 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result + set_gr_immed -2,gr8 + set_icc 0x1,1 + csmulcc gr7,gr8,gr8,cc1,1 + test_icc 0 0 0 1 icc1 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed -4,gr8 + set_icc 0x2,1 + csmulcc gr7,gr8,gr8,cc5,1 + test_icc 0 0 1 0 icc1 + test_gr_immed -4,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x3,1 + csmulcc gr7,gr8,gr8,cc5,1 + test_icc 0 0 1 1 icc1 + test_gr_limmed 0x8000,0x0000,gr8 + test_gr_immed 0,gr9 + + ; Negative operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + set_icc 0x4,1 + csmulcc gr7,gr8,gr8,cc1,1 + test_icc 0 1 0 0 icc1 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + set_icc 0x5,1 + csmulcc gr7,gr8,gr8,cc1,1 + test_icc 0 1 0 1 icc1 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed -1,gr8 + set_icc 0x6,1 + csmulcc gr7,gr8,gr8,cc5,1 + test_icc 0 1 1 0 icc1 + test_gr_immed -1,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result + set_gr_immed -2,gr8 + set_icc 0x7,1 + csmulcc gr7,gr8,gr8,cc5,1 + test_icc 0 1 1 1 icc1 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + set_icc 0x8,1 + csmulcc gr7,gr8,gr8,cc1,1 + test_icc 1 0 0 0 icc1 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result + set_gr_immed -4,gr8 + set_icc 0x9,1 + csmulcc gr7,gr8,gr8,cc1,1 + test_icc 1 0 0 1 icc1 + test_gr_immed -4,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result + set_gr_limmed 0x8000,0x0001,gr8 + set_icc 0xa,1 + csmulcc gr7,gr8,gr8,cc5,1 + test_icc 1 0 1 0 icc1 + test_gr_limmed 0x8000,0x0001,gr8 + test_gr_immed 0,gr9 + + + set_gr_limmed 0x8000,0x0000,gr7 ; max positive result + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0xb,1 + csmulcc gr7,gr8,gr8,cc5,1 + test_icc 1 0 1 1 icc1 + test_gr_limmed 0x8000,0x0000,gr8 + test_gr_immed 0,gr9 + + ; Positive operands + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + set_icc 0x0,2 + csmulcc gr7,gr8,gr8,cc2,0 + test_icc 0 0 0 0 icc2 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed 2,gr8 + set_icc 0x1,2 + csmulcc gr7,gr8,gr8,cc2,1 + test_icc 0 0 0 1 icc2 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + set_icc 0x2,2 + csmulcc gr7,gr8,gr8,cc6,0 + test_icc 0 0 1 0 icc2 + test_gr_immed 1,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed 2,gr8 + set_icc 0x3,2 + csmulcc gr7,gr8,gr8,cc6,1 + test_icc 0 0 1 1 icc2 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + set_icc 0x4,2 + csmulcc gr7,gr8,gr8,cc2,0 + test_icc 0 1 0 0 icc2 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result + set_gr_immed 2,gr8 + set_icc 0x5,2 + csmulcc gr7,gr8,gr8,cc2,1 + test_icc 0 1 0 1 icc2 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed 2,gr8 + set_icc 0x6,2 + csmulcc gr7,gr8,gr8,cc6,1 + test_icc 0 1 1 0 icc2 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed 4,gr8 + set_icc 0x7,2 + csmulcc gr7,gr8,gr8,cc6,0 + test_icc 0 1 1 1 icc2 + test_gr_immed 4,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result + set_gr_limmed 0x7fff,0xffff,gr8 + set_icc 0x8,2 + csmulcc gr7,gr8,gr8,cc2,1 + test_icc 1 0 0 0 icc2 + test_gr_limmed 0x7fff,0xffff,gr8 + test_gr_immed 0,gr9 + + ; Mixed operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + set_icc 0x9,2 + csmulcc gr7,gr8,gr8,cc2,0 + test_icc 1 0 0 1 icc2 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + set_icc 0xa,2 + csmulcc gr7,gr8,gr8,cc6,1 + test_icc 1 0 1 0 icc2 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + set_icc 0xb,2 + csmulcc gr7,gr8,gr8,cc6,0 + test_icc 1 0 1 1 icc2 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + set_icc 0xc,2 + csmulcc gr7,gr8,gr8,cc2,1 + test_icc 1 1 0 0 icc2 + test_gr_immed 1,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed -2,gr8 + set_icc 0xd,2 + csmulcc gr7,gr8,gr8,cc2,0 + test_icc 1 1 0 1 icc2 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + set_icc 0xe,2 + csmulcc gr7,gr8,gr8,cc6,1 + test_icc 1 1 1 0 icc2 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result + set_gr_immed -2,gr8 + set_icc 0xf,2 + csmulcc gr7,gr8,gr8,cc6,0 + test_icc 1 1 1 1 icc2 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + set_icc 0x0,2 + csmulcc gr7,gr8,gr8,cc2,1 + test_icc 0 0 0 0 icc2 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result + set_gr_immed -2,gr8 + set_icc 0x1,2 + csmulcc gr7,gr8,gr8,cc2,0 + test_icc 0 0 0 1 icc2 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed -4,gr8 + set_icc 0x2,2 + csmulcc gr7,gr8,gr8,cc6,1 + test_icc 0 0 1 0 icc2 + test_gr_immed -4,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x3,2 + csmulcc gr7,gr8,gr8,cc6,0 + test_icc 0 0 1 1 icc2 + test_gr_limmed 0x8000,0x0000,gr8 + test_gr_immed 0,gr9 + + ; Negative operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + set_icc 0x4,2 + csmulcc gr7,gr8,gr8,cc2,1 + test_icc 0 1 0 0 icc2 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + set_icc 0x5,2 + csmulcc gr7,gr8,gr8,cc2,0 + test_icc 0 1 0 1 icc2 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed -1,gr8 + set_icc 0x6,2 + csmulcc gr7,gr8,gr8,cc6,1 + test_icc 0 1 1 0 icc2 + test_gr_immed -1,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result + set_gr_immed -2,gr8 + set_icc 0x7,2 + csmulcc gr7,gr8,gr8,cc6,0 + test_icc 0 1 1 1 icc2 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + set_icc 0x8,2 + csmulcc gr7,gr8,gr8,cc2,1 + test_icc 1 0 0 0 icc2 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result + set_gr_immed -4,gr8 + set_icc 0x9,2 + csmulcc gr7,gr8,gr8,cc2,0 + test_icc 1 0 0 1 icc2 + test_gr_immed -4,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result + set_gr_limmed 0x8000,0x0001,gr8 + set_icc 0xa,2 + csmulcc gr7,gr8,gr8,cc6,1 + test_icc 1 0 1 0 icc2 + test_gr_limmed 0x8000,0x0001,gr8 + test_gr_immed 0,gr9 + + + set_gr_limmed 0x8000,0x0000,gr7 ; max positive result + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0xb,2 + csmulcc gr7,gr8,gr8,cc6,0 + test_icc 1 0 1 1 icc2 + test_gr_limmed 0x8000,0x0000,gr8 + test_gr_immed 0,gr9 + + ; Positive operands + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + set_icc 0x0,3 + csmulcc gr7,gr8,gr8,cc3,0 + test_icc 0 0 0 0 icc3 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed 2,gr8 + set_icc 0x1,3 + csmulcc gr7,gr8,gr8,cc3,1 + test_icc 0 0 0 1 icc3 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + set_icc 0x2,3 + csmulcc gr7,gr8,gr8,cc7,0 + test_icc 0 0 1 0 icc3 + test_gr_immed 1,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed 2,gr8 + set_icc 0x3,3 + csmulcc gr7,gr8,gr8,cc7,1 + test_icc 0 0 1 1 icc3 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + set_icc 0x4,3 + csmulcc gr7,gr8,gr8,cc3,0 + test_icc 0 1 0 0 icc3 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result + set_gr_immed 2,gr8 + set_icc 0x5,3 + csmulcc gr7,gr8,gr8,cc3,1 + test_icc 0 1 0 1 icc3 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed 2,gr8 + set_icc 0x6,3 + csmulcc gr7,gr8,gr8,cc7,1 + test_icc 0 1 1 0 icc3 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed 4,gr8 + set_icc 0x7,3 + csmulcc gr7,gr8,gr8,cc7,0 + test_icc 0 1 1 1 icc3 + test_gr_immed 4,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result + set_gr_limmed 0x7fff,0xffff,gr8 + set_icc 0x8,3 + csmulcc gr7,gr8,gr8,cc3,1 + test_icc 1 0 0 0 icc3 + test_gr_limmed 0x7fff,0xffff,gr8 + test_gr_immed 0,gr9 + + ; Mixed operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + set_icc 0x9,3 + csmulcc gr7,gr8,gr8,cc3,0 + test_icc 1 0 0 1 icc3 + test_gr_immed 2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + set_icc 0xa,3 + csmulcc gr7,gr8,gr8,cc7,1 + test_icc 1 0 1 0 icc3 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + set_icc 0xb,3 + csmulcc gr7,gr8,gr8,cc7,0 + test_icc 1 0 1 1 icc3 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + set_icc 0xc,3 + csmulcc gr7,gr8,gr8,cc3,1 + test_icc 1 1 0 0 icc3 + test_gr_immed 1,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed -2,gr8 + set_icc 0xd,3 + csmulcc gr7,gr8,gr8,cc3,0 + test_icc 1 1 0 1 icc3 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + set_icc 0xe,3 + csmulcc gr7,gr8,gr8,cc7,1 + test_icc 1 1 1 0 icc3 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result + set_gr_immed -2,gr8 + set_icc 0xf,3 + csmulcc gr7,gr8,gr8,cc7,0 + test_icc 1 1 1 1 icc3 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + set_icc 0x0,3 + csmulcc gr7,gr8,gr8,cc3,1 + test_icc 0 0 0 0 icc3 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result + set_gr_immed -2,gr8 + set_icc 0x1,3 + csmulcc gr7,gr8,gr8,cc3,0 + test_icc 0 0 0 1 icc3 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed -4,gr8 + set_icc 0x2,3 + csmulcc gr7,gr8,gr8,cc7,1 + test_icc 0 0 1 0 icc3 + test_gr_immed -4,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x3,3 + csmulcc gr7,gr8,gr8,cc7,0 + test_icc 0 0 1 1 icc3 + test_gr_limmed 0x8000,0x0000,gr8 + test_gr_immed 0,gr9 + + ; Negative operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + set_icc 0x4,3 + csmulcc gr7,gr8,gr8,cc3,1 + test_icc 0 1 0 0 icc3 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + set_icc 0x5,3 + csmulcc gr7,gr8,gr8,cc3,0 + test_icc 0 1 0 1 icc3 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed -1,gr8 + set_icc 0x6,3 + csmulcc gr7,gr8,gr8,cc7,1 + test_icc 0 1 1 0 icc3 + test_gr_immed -1,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result + set_gr_immed -2,gr8 + set_icc 0x7,3 + csmulcc gr7,gr8,gr8,cc7,0 + test_icc 0 1 1 1 icc3 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + set_icc 0x8,3 + csmulcc gr7,gr8,gr8,cc3,1 + test_icc 1 0 0 0 icc3 + test_gr_immed -2,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result + set_gr_immed -4,gr8 + set_icc 0x9,3 + csmulcc gr7,gr8,gr8,cc3,0 + test_icc 1 0 0 1 icc3 + test_gr_immed -4,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result + set_gr_limmed 0x8000,0x0001,gr8 + set_icc 0xa,3 + csmulcc gr7,gr8,gr8,cc7,1 + test_icc 1 0 1 0 icc3 + test_gr_limmed 0x8000,0x0001,gr8 + test_gr_immed 0,gr9 + + + set_gr_limmed 0x8000,0x0000,gr7 ; max positive result + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0xb,3 + csmulcc gr7,gr8,gr8,cc7,0 + test_icc 1 0 1 1 icc3 + test_gr_limmed 0x8000,0x0000,gr8 + test_gr_immed 0,gr9 + + pass diff --git a/sim/testsuite/sim/frv/csra.cgs b/sim/testsuite/sim/frv/csra.cgs new file mode 100644 index 0000000..f59de05 --- /dev/null +++ b/sim/testsuite/sim/frv/csra.cgs @@ -0,0 +1,180 @@ +# frv testcase for csra $GRi,$GRj,$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global csra +csra: + set_spr_immed 0x1b1b,cccr + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + csra gr8,gr7,gr8,cc0,1 + test_icc 0 1 0 1 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + csra gr8,gr7,gr8,cc0,1 + test_icc 1 1 1 1 icc0 + test_gr_limmed 0xc000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + csra gr8,gr7,gr8,cc4,1 + test_icc 1 1 1 1 icc0 + test_gr_immed -1,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,0 ; Set mask opposite of expected + csra gr8,gr7,gr8,cc4,1 + test_icc 1 0 1 0 icc0 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + csra gr8,gr7,gr8,cc0,0 + test_icc 0 1 0 1 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + csra gr8,gr7,gr8,cc0,0 + test_icc 1 1 1 1 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + csra gr8,gr7,gr8,cc4,0 + test_icc 1 1 1 1 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,0 ; Set mask opposite of expected + csra gr8,gr7,gr8,cc4,0 + test_icc 1 0 1 0 icc0 + test_gr_limmed 0x4000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,1 ; Set mask opposite of expected + csra gr8,gr7,gr8,cc1,0 + test_icc 0 1 0 1 icc1 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,1 ; Set mask opposite of expected + csra gr8,gr7,gr8,cc1,0 + test_icc 1 1 1 1 icc1 + test_gr_limmed 0xc000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,1 ; Set mask opposite of expected + csra gr8,gr7,gr8,cc5,0 + test_icc 1 1 1 1 icc1 + test_gr_immed -1,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,1 ; Set mask opposite of expected + csra gr8,gr7,gr8,cc5,0 + test_icc 1 0 1 0 icc1 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,1 ; Set mask opposite of expected + csra gr8,gr7,gr8,cc1,1 + test_icc 0 1 0 1 icc1 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,1 ; Set mask opposite of expected + csra gr8,gr7,gr8,cc1,1 + test_icc 1 1 1 1 icc1 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,1 ; Set mask opposite of expected + csra gr8,gr7,gr8,cc5,1 + test_icc 1 1 1 1 icc1 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,1 ; Set mask opposite of expected + csra gr8,gr7,gr8,cc5,1 + test_icc 1 0 1 0 icc1 + test_gr_limmed 0x4000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,2 ; Set mask opposite of expected + csra gr8,gr7,gr8,cc2,0 + test_icc 0 1 0 1 icc2 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,2 ; Set mask opposite of expected + csra gr8,gr7,gr8,cc2,0 + test_icc 1 1 1 1 icc2 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,2 ; Set mask opposite of expected + csra gr8,gr7,gr8,cc6,1 + test_icc 1 1 1 1 icc2 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,2 ; Set mask opposite of expected + csra gr8,gr7,gr8,cc6,1 + test_icc 1 0 1 0 icc2 + test_gr_limmed 0x4000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,3 ; Set mask opposite of expected + csra gr8,gr7,gr8,cc3,0 + test_icc 0 1 0 1 icc3 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,3 ; Set mask opposite of expected + csra gr8,gr7,gr8,cc3,0 + test_icc 1 1 1 1 icc3 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,3 ; Set mask opposite of expected + csra gr8,gr7,gr8,cc7,1 + test_icc 1 1 1 1 icc3 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,3 ; Set mask opposite of expected + csra gr8,gr7,gr8,cc7,1 + test_icc 1 0 1 0 icc3 + test_gr_limmed 0x4000,0x0000,gr8 + + pass diff --git a/sim/testsuite/sim/frv/csracc.cgs b/sim/testsuite/sim/frv/csracc.cgs new file mode 100644 index 0000000..64d4cbf --- /dev/null +++ b/sim/testsuite/sim/frv/csracc.cgs @@ -0,0 +1,180 @@ +# frv testcase for csracc $GRi,$GRj,$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global csracc +csracc: + set_spr_immed 0x1b1b,cccr + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + csracc gr8,gr7,gr8,cc0,1 + test_icc 1 0 0 0 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x07,0 ; Set mask opposite of expected + csracc gr8,gr7,gr8,cc0,1 + test_icc 1 0 1 0 icc0 + test_gr_limmed 0xc000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x07,0 ; Set mask opposite of expected + csracc gr8,gr7,gr8,cc4,1 + test_icc 1 0 1 0 icc0 + test_gr_immed -1,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,0 ; Set mask opposite of expected + csracc gr8,gr7,gr8,cc4,1 + test_icc 0 1 1 1 icc0 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + csracc gr8,gr7,gr8,cc0,0 + test_icc 0 1 0 1 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + csracc gr8,gr7,gr8,cc0,0 + test_icc 1 1 1 1 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + csracc gr8,gr7,gr8,cc4,0 + test_icc 1 1 1 1 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,0 ; Set mask opposite of expected + csracc gr8,gr7,gr8,cc4,0 + test_icc 1 0 1 0 icc0 + test_gr_limmed 0x4000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,1 ; Set mask opposite of expected + csracc gr8,gr7,gr8,cc1,0 + test_icc 1 0 0 0 icc1 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x07,1 ; Set mask opposite of expected + csracc gr8,gr7,gr8,cc1,0 + test_icc 1 0 1 0 icc1 + test_gr_limmed 0xc000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x07,1 ; Set mask opposite of expected + csracc gr8,gr7,gr8,cc5,0 + test_icc 1 0 1 0 icc1 + test_gr_immed -1,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,1 ; Set mask opposite of expected + csracc gr8,gr7,gr8,cc5,0 + test_icc 0 1 1 1 icc1 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,1 ; Set mask opposite of expected + csracc gr8,gr7,gr8,cc1,1 + test_icc 0 1 0 1 icc1 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,1 ; Set mask opposite of expected + csracc gr8,gr7,gr8,cc1,1 + test_icc 1 1 1 1 icc1 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,1 ; Set mask opposite of expected + csracc gr8,gr7,gr8,cc5,1 + test_icc 1 1 1 1 icc1 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,1 ; Set mask opposite of expected + csracc gr8,gr7,gr8,cc5,1 + test_icc 1 0 1 0 icc1 + test_gr_limmed 0x4000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,2 ; Set mask opposite of expected + csracc gr8,gr7,gr8,cc2,0 + test_icc 0 1 0 1 icc2 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,2 ; Set mask opposite of expected + csracc gr8,gr7,gr8,cc2,0 + test_icc 1 1 1 1 icc2 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,2 ; Set mask opposite of expected + csracc gr8,gr7,gr8,cc6,1 + test_icc 1 1 1 1 icc2 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,2 ; Set mask opposite of expected + csracc gr8,gr7,gr8,cc6,1 + test_icc 1 0 1 0 icc2 + test_gr_limmed 0x4000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,3 ; Set mask opposite of expected + csracc gr8,gr7,gr8,cc3,0 + test_icc 0 1 0 1 icc3 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,3 ; Set mask opposite of expected + csracc gr8,gr7,gr8,cc3,0 + test_icc 1 1 1 1 icc3 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,3 ; Set mask opposite of expected + csracc gr8,gr7,gr8,cc7,1 + test_icc 1 1 1 1 icc3 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,3 ; Set mask opposite of expected + csracc gr8,gr7,gr8,cc7,1 + test_icc 1 0 1 0 icc3 + test_gr_limmed 0x4000,0x0000,gr8 + + pass diff --git a/sim/testsuite/sim/frv/csrl.cgs b/sim/testsuite/sim/frv/csrl.cgs new file mode 100644 index 0000000..7a71db4 --- /dev/null +++ b/sim/testsuite/sim/frv/csrl.cgs @@ -0,0 +1,180 @@ +# frv testcase for csrl $GRi,$GRj,$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global csrl +csrl: + set_spr_immed 0x1b1b,cccr + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + csrl gr8,gr7,gr8,cc0,1 + test_icc 0 1 0 1 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + csrl gr8,gr7,gr8,cc0,1 + test_icc 1 1 1 1 icc0 + test_gr_limmed 0x4000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + csrl gr8,gr7,gr8,cc4,1 + test_icc 1 1 1 1 icc0 + test_gr_immed 1,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,0 ; Set mask opposite of expected + csrl gr8,gr7,gr8,cc4,1 + test_icc 1 0 1 0 icc0 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + csrl gr8,gr7,gr8,cc0,0 + test_icc 0 1 0 1 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + csrl gr8,gr7,gr8,cc0,0 + test_icc 1 1 1 1 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + csrl gr8,gr7,gr8,cc4,0 + test_icc 1 1 1 1 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,0 ; Set mask opposite of expected + csrl gr8,gr7,gr8,cc4,0 + test_icc 1 0 1 0 icc0 + test_gr_limmed 0x4000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,1 ; Set mask opposite of expected + csrl gr8,gr7,gr8,cc1,0 + test_icc 0 1 0 1 icc1 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,1 ; Set mask opposite of expected + csrl gr8,gr7,gr8,cc1,0 + test_icc 1 1 1 1 icc1 + test_gr_limmed 0x4000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,1 ; Set mask opposite of expected + csrl gr8,gr7,gr8,cc5,0 + test_icc 1 1 1 1 icc1 + test_gr_immed 1,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,1 ; Set mask opposite of expected + csrl gr8,gr7,gr8,cc5,0 + test_icc 1 0 1 0 icc1 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,1 ; Set mask opposite of expected + csrl gr8,gr7,gr8,cc1,1 + test_icc 0 1 0 1 icc1 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,1 ; Set mask opposite of expected + csrl gr8,gr7,gr8,cc1,1 + test_icc 1 1 1 1 icc1 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,1 ; Set mask opposite of expected + csrl gr8,gr7,gr8,cc5,1 + test_icc 1 1 1 1 icc1 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,1 ; Set mask opposite of expected + csrl gr8,gr7,gr8,cc5,1 + test_icc 1 0 1 0 icc1 + test_gr_limmed 0x4000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,2 ; Set mask opposite of expected + csrl gr8,gr7,gr8,cc2,0 + test_icc 0 1 0 1 icc2 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,2 ; Set mask opposite of expected + csrl gr8,gr7,gr8,cc2,0 + test_icc 1 1 1 1 icc2 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,2 ; Set mask opposite of expected + csrl gr8,gr7,gr8,cc6,1 + test_icc 1 1 1 1 icc2 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,2 ; Set mask opposite of expected + csrl gr8,gr7,gr8,cc6,1 + test_icc 1 0 1 0 icc2 + test_gr_limmed 0x4000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,3 ; Set mask opposite of expected + csrl gr8,gr7,gr8,cc3,0 + test_icc 0 1 0 1 icc3 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,3 ; Set mask opposite of expected + csrl gr8,gr7,gr8,cc3,0 + test_icc 1 1 1 1 icc3 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,3 ; Set mask opposite of expected + csrl gr8,gr7,gr8,cc7,1 + test_icc 1 1 1 1 icc3 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,3 ; Set mask opposite of expected + csrl gr8,gr7,gr8,cc7,1 + test_icc 1 0 1 0 icc3 + test_gr_limmed 0x4000,0x0000,gr8 + + pass diff --git a/sim/testsuite/sim/frv/csrlcc.cgs b/sim/testsuite/sim/frv/csrlcc.cgs new file mode 100644 index 0000000..fb89456 --- /dev/null +++ b/sim/testsuite/sim/frv/csrlcc.cgs @@ -0,0 +1,180 @@ +# frv testcase for csrlcc $GRi,$GRj,$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global csrlcc +csrlcc: + set_spr_immed 0x1b1b,cccr + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + csrlcc gr8,gr7,gr8,cc0,1 + test_icc 1 0 0 0 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + csrlcc gr8,gr7,gr8,cc0,1 + test_icc 0 0 1 0 icc0 + test_gr_limmed 0x4000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + csrlcc gr8,gr7,gr8,cc4,1 + test_icc 0 0 1 0 icc0 + test_gr_immed 1,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,0 ; Set mask opposite of expected + csrlcc gr8,gr7,gr8,cc4,1 + test_icc 0 1 1 1 icc0 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + csrlcc gr8,gr7,gr8,cc0,0 + test_icc 0 1 0 1 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + csrlcc gr8,gr7,gr8,cc0,0 + test_icc 1 1 1 1 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + csrlcc gr8,gr7,gr8,cc4,0 + test_icc 1 1 1 1 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,0 ; Set mask opposite of expected + csrlcc gr8,gr7,gr8,cc4,0 + test_icc 1 0 1 0 icc0 + test_gr_limmed 0x4000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,1 ; Set mask opposite of expected + csrlcc gr8,gr7,gr8,cc1,0 + test_icc 1 0 0 0 icc1 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,1 ; Set mask opposite of expected + csrlcc gr8,gr7,gr8,cc1,0 + test_icc 0 0 1 0 icc1 + test_gr_limmed 0x4000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,1 ; Set mask opposite of expected + csrlcc gr8,gr7,gr8,cc5,0 + test_icc 0 0 1 0 icc1 + test_gr_immed 1,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,1 ; Set mask opposite of expected + csrlcc gr8,gr7,gr8,cc5,0 + test_icc 0 1 1 1 icc1 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,1 ; Set mask opposite of expected + csrlcc gr8,gr7,gr8,cc1,1 + test_icc 0 1 0 1 icc1 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,1 ; Set mask opposite of expected + csrlcc gr8,gr7,gr8,cc1,1 + test_icc 1 1 1 1 icc1 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,1 ; Set mask opposite of expected + csrlcc gr8,gr7,gr8,cc5,1 + test_icc 1 1 1 1 icc1 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,1 ; Set mask opposite of expected + csrlcc gr8,gr7,gr8,cc5,1 + test_icc 1 0 1 0 icc1 + test_gr_limmed 0x4000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,2 ; Set mask opposite of expected + csrlcc gr8,gr7,gr8,cc2,0 + test_icc 0 1 0 1 icc2 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,2 ; Set mask opposite of expected + csrlcc gr8,gr7,gr8,cc2,0 + test_icc 1 1 1 1 icc2 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,2 ; Set mask opposite of expected + csrlcc gr8,gr7,gr8,cc6,1 + test_icc 1 1 1 1 icc2 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,2 ; Set mask opposite of expected + csrlcc gr8,gr7,gr8,cc6,1 + test_icc 1 0 1 0 icc2 + test_gr_limmed 0x4000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,3 ; Set mask opposite of expected + csrlcc gr8,gr7,gr8,cc3,0 + test_icc 0 1 0 1 icc3 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,3 ; Set mask opposite of expected + csrlcc gr8,gr7,gr8,cc3,0 + test_icc 1 1 1 1 icc3 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,3 ; Set mask opposite of expected + csrlcc gr8,gr7,gr8,cc7,1 + test_icc 1 1 1 1 icc3 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,3 ; Set mask opposite of expected + csrlcc gr8,gr7,gr8,cc7,1 + test_icc 1 0 1 0 icc3 + test_gr_limmed 0x4000,0x0000,gr8 + + pass diff --git a/sim/testsuite/sim/frv/cst.cgs b/sim/testsuite/sim/frv/cst.cgs new file mode 100644 index 0000000..8244edf --- /dev/null +++ b/sim/testsuite/sim/frv/cst.cgs @@ -0,0 +1,126 @@ +# frv testcase for cst $GRk,@($GRi,$GRj) +# mach: all + + .include "testutils.inc" + + start + + .global cst +cst: + set_spr_immed 0x1b1b,cccr + set_gr_gr sp,gr21 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + cst gr8,@(sp,gr7),cc0,1 + test_mem_limmed 0xffff,0xffff,gr21 + + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + set_gr_limmed 0xeeee,0xffff,gr8 + cst gr8,@(sp,gr7),cc0,1 + test_mem_limmed 0xeeee,0xffff,gr21 + + inc_gr_immed 8,sp + set_gr_immed -4,gr7 + set_gr_limmed 0xcccc,0xdddd,gr8 + cst gr8,@(sp,gr7),cc4,1 + test_mem_limmed 0xcccc,0xdddd,gr21 + + set_gr_gr gr21,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + cst gr8,@(sp,gr7),cc0,0 + test_mem_limmed 0xdead,0xbeef,gr21 + + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + set_gr_limmed 0xeeee,0xffff,gr8 + cst gr8,@(sp,gr7),cc0,0 + test_mem_limmed 0xdead,0xbeef,gr21 + + inc_gr_immed 8,sp + set_gr_immed -4,gr7 + set_gr_limmed 0xcccc,0xdddd,gr8 + cst gr8,@(sp,gr7),cc4,0 + test_mem_limmed 0xdead,0xbeef,gr21 + + set_gr_gr gr21,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + cst gr8,@(sp,gr7),cc1,0 + test_mem_limmed 0xffff,0xffff,gr21 + + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + set_gr_limmed 0xeeee,0xffff,gr8 + cst gr8,@(sp,gr7),cc1,0 + test_mem_limmed 0xeeee,0xffff,gr21 + + inc_gr_immed 8,sp + set_gr_immed -4,gr7 + set_gr_limmed 0xcccc,0xdddd,gr8 + cst gr8,@(sp,gr7),cc5,0 + test_mem_limmed 0xcccc,0xdddd,gr21 + + set_gr_gr gr21,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + cst gr8,@(sp,gr7),cc1,1 + test_mem_limmed 0xdead,0xbeef,gr21 + + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + set_gr_limmed 0xeeee,0xffff,gr8 + cst gr8,@(sp,gr7),cc1,1 + test_mem_limmed 0xdead,0xbeef,gr21 + + inc_gr_immed 8,sp + set_gr_immed -4,gr7 + set_gr_limmed 0xcccc,0xdddd,gr8 + cst gr8,@(sp,gr7),cc5,1 + test_mem_limmed 0xdead,0xbeef,gr21 + + set_gr_gr gr21,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + cst gr8,@(sp,gr7),cc2,0 + test_mem_limmed 0xdead,0xbeef,gr21 + + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + set_gr_limmed 0xeeee,0xffff,gr8 + cst gr8,@(sp,gr7),cc2,1 + test_mem_limmed 0xdead,0xbeef,gr21 + + inc_gr_immed 8,sp + set_gr_immed -4,gr7 + set_gr_limmed 0xcccc,0xdddd,gr8 + cst gr8,@(sp,gr7),cc6,0 + test_mem_limmed 0xdead,0xbeef,gr21 + + set_gr_gr gr21,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + cst gr8,@(sp,gr7),cc3,1 + test_mem_limmed 0xdead,0xbeef,gr21 + + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + set_gr_limmed 0xeeee,0xffff,gr8 + cst gr8,@(sp,gr7),cc3,0 + test_mem_limmed 0xdead,0xbeef,gr21 + + inc_gr_immed 8,sp + set_gr_immed -4,gr7 + set_gr_limmed 0xcccc,0xdddd,gr8 + cst gr8,@(sp,gr7),cc7,1 + test_mem_limmed 0xdead,0xbeef,gr21 + + pass diff --git a/sim/testsuite/sim/frv/cstb.cgs b/sim/testsuite/sim/frv/cstb.cgs new file mode 100644 index 0000000..7b62558 --- /dev/null +++ b/sim/testsuite/sim/frv/cstb.cgs @@ -0,0 +1,120 @@ +# frv testcase for cstb $GRk,@($GRi,$GRj) +# mach: all + + .include "testutils.inc" + + start + + .global add +add: + set_spr_immed 0x1b1b,cccr + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + cstb gr8,@(sp,gr7),cc0,1 + test_mem_limmed 0xffad,0xbeef,sp + + set_gr_immed 2,gr7 + set_gr_limmed 0xffff,0xffee,gr8 + cstb gr8,@(sp,gr7),cc0,1 + test_mem_limmed 0xffad,0xeeef,sp + + set_gr_immed -1,gr7 + inc_gr_immed 4,sp + set_gr_limmed 0xffff,0xff00,gr8 + cstb gr8,@(sp,gr7),cc4,1 + inc_gr_immed -4,sp + test_mem_limmed 0xffad,0xee00,sp + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + cstb gr8,@(sp,gr7),cc0,0 + test_mem_limmed 0xdead,0xbeef,sp + + set_gr_immed 2,gr7 + set_gr_limmed 0xffff,0xffee,gr8 + cstb gr8,@(sp,gr7),cc0,0 + test_mem_limmed 0xdead,0xbeef,sp + + set_gr_immed -1,gr7 + inc_gr_immed 4,sp + set_gr_limmed 0xffff,0xff00,gr8 + cstb gr8,@(sp,gr7),cc4,0 + inc_gr_immed -4,sp + test_mem_limmed 0xdead,0xbeef,sp + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + cstb gr8,@(sp,gr7),cc1,0 + test_mem_limmed 0xffad,0xbeef,sp + + set_gr_immed 2,gr7 + set_gr_limmed 0xffff,0xffee,gr8 + cstb gr8,@(sp,gr7),cc1,0 + test_mem_limmed 0xffad,0xeeef,sp + + set_gr_immed -1,gr7 + inc_gr_immed 4,sp + set_gr_limmed 0xffff,0xff00,gr8 + cstb gr8,@(sp,gr7),cc5,0 + inc_gr_immed -4,sp + test_mem_limmed 0xffad,0xee00,sp + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + cstb gr8,@(sp,gr7),cc1,1 + test_mem_limmed 0xdead,0xbeef,sp + + set_gr_immed 2,gr7 + set_gr_limmed 0xffff,0xffee,gr8 + cstb gr8,@(sp,gr7),cc1,1 + test_mem_limmed 0xdead,0xbeef,sp + + set_gr_immed -1,gr7 + inc_gr_immed 4,sp + set_gr_limmed 0xffff,0xff00,gr8 + cstb gr8,@(sp,gr7),cc5,1 + inc_gr_immed -4,sp + test_mem_limmed 0xdead,0xbeef,sp + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + cstb gr8,@(sp,gr7),cc2,0 + test_mem_limmed 0xdead,0xbeef,sp + + set_gr_immed 2,gr7 + set_gr_limmed 0xffff,0xffee,gr8 + cstb gr8,@(sp,gr7),cc2,1 + test_mem_limmed 0xdead,0xbeef,sp + + set_gr_immed -1,gr7 + inc_gr_immed 4,sp + set_gr_limmed 0xffff,0xff00,gr8 + cstb gr8,@(sp,gr7),cc6,0 + inc_gr_immed -4,sp + test_mem_limmed 0xdead,0xbeef,sp + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + cstb gr8,@(sp,gr7),cc3,1 + test_mem_limmed 0xdead,0xbeef,sp + + set_gr_immed 2,gr7 + set_gr_limmed 0xffff,0xffee,gr8 + cstb gr8,@(sp,gr7),cc3,0 + test_mem_limmed 0xdead,0xbeef,sp + + set_gr_immed -1,gr7 + inc_gr_immed 4,sp + set_gr_limmed 0xffff,0xff00,gr8 + cstb gr8,@(sp,gr7),cc7,1 + inc_gr_immed -4,sp + test_mem_limmed 0xdead,0xbeef,sp + + pass diff --git a/sim/testsuite/sim/frv/cstbf.cgs b/sim/testsuite/sim/frv/cstbf.cgs new file mode 100644 index 0000000..23e1ae4 --- /dev/null +++ b/sim/testsuite/sim/frv/cstbf.cgs @@ -0,0 +1,120 @@ +# frv testcase for cstbf $FRk,@($GRi,$GRj),$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cstbf +cstbf: + set_spr_immed 0x1b1b,cccr + set_gr_gr sp,gr20 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cstbf fr8,@(sp,gr7),cc0,1 + test_mem_limmed 0xffad,0xbeef,gr20 + + set_gr_immed 2,gr7 + set_fr_iimmed 0xffff,0xffaa,fr8 + cstbf fr8,@(sp,gr7),cc0,1 + test_mem_limmed 0xffad,0xaaef,gr20 + + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + set_fr_iimmed 0xffff,0xffbb,fr8 + cstbf fr8,@(sp,gr7),cc4,1 + test_mem_limmed 0xffad,0xaabb,gr20 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cstbf fr8,@(sp,gr7),cc0,0 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_immed 2,gr7 + set_fr_iimmed 0xffff,0xffaa,fr8 + cstbf fr8,@(sp,gr7),cc0,0 + test_mem_limmed 0xdead,0xbeef,gr20 + + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + set_fr_iimmed 0xffff,0xffbb,fr8 + cstbf fr8,@(sp,gr7),cc4,0 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cstbf fr8,@(sp,gr7),cc1,0 + test_mem_limmed 0xffad,0xbeef,gr20 + + set_gr_immed 2,gr7 + set_fr_iimmed 0xffff,0xffaa,fr8 + cstbf fr8,@(sp,gr7),cc1,0 + test_mem_limmed 0xffad,0xaaef,gr20 + + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + set_fr_iimmed 0xffff,0xffbb,fr8 + cstbf fr8,@(sp,gr7),cc5,0 + test_mem_limmed 0xffad,0xaabb,gr20 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cstbf fr8,@(sp,gr7),cc1,1 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_immed 2,gr7 + set_fr_iimmed 0xffff,0xffaa,fr8 + cstbf fr8,@(sp,gr7),cc1,1 + test_mem_limmed 0xdead,0xbeef,gr20 + + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + set_fr_iimmed 0xffff,0xffbb,fr8 + cstbf fr8,@(sp,gr7),cc5,1 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cstbf fr8,@(sp,gr7),cc2,0 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_immed 2,gr7 + set_fr_iimmed 0xffff,0xffaa,fr8 + cstbf fr8,@(sp,gr7),cc2,1 + test_mem_limmed 0xdead,0xbeef,gr20 + + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + set_fr_iimmed 0xffff,0xffbb,fr8 + cstbf fr8,@(sp,gr7),cc6,0 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cstbf fr8,@(sp,gr7),cc3,1 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_immed 2,gr7 + set_fr_iimmed 0xffff,0xffaa,fr8 + cstbf fr8,@(sp,gr7),cc3,0 + test_mem_limmed 0xdead,0xbeef,gr20 + + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + set_fr_iimmed 0xffff,0xffbb,fr8 + cstbf fr8,@(sp,gr7),cc7,1 + test_mem_limmed 0xdead,0xbeef,gr20 + + pass diff --git a/sim/testsuite/sim/frv/cstbfu.cgs b/sim/testsuite/sim/frv/cstbfu.cgs new file mode 100644 index 0000000..01943be --- /dev/null +++ b/sim/testsuite/sim/frv/cstbfu.cgs @@ -0,0 +1,152 @@ +# frv testcase for cstbfu $FRk,@($GRi,$GRj),$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cstbfu +cstbfu: + set_spr_immed 0x1b1b,cccr + set_gr_gr sp,gr20 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr21 + set_gr_immed 0,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cstbfu fr8,@(sp,gr7),cc0,1 + test_mem_limmed 0xffad,0xbeef,gr20 + test_gr_gr sp,gr21 + + inc_gr_immed 2,gr21 + set_gr_immed 2,gr7 + set_fr_iimmed 0xffff,0xffaa,fr8 + cstbfu fr8,@(sp,gr7),cc0,1 + test_mem_limmed 0xffad,0xaaef,gr20 + test_gr_gr sp,gr21 + + inc_gr_immed 1,gr21 + inc_gr_immed 2,sp + set_gr_immed -1,gr7 + set_fr_iimmed 0xffff,0xffbb,fr8 + cstbfu fr8,@(sp,gr7),cc4,1 + test_mem_limmed 0xffad,0xaabb,gr20 + test_gr_gr sp,gr21 + + set_gr_gr gr20,sp + set_gr_gr sp,gr21 + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cstbfu fr8,@(sp,gr7),cc0,0 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + set_gr_immed 2,gr7 + set_fr_iimmed 0xffff,0xffaa,fr8 + cstbfu fr8,@(sp,gr7),cc0,0 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + inc_gr_immed 4,gr21 + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + set_fr_iimmed 0xffff,0xffbb,fr8 + cstbfu fr8,@(sp,gr7),cc4,0 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr21 + set_gr_immed 0,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cstbfu fr8,@(sp,gr7),cc1,0 + test_mem_limmed 0xffad,0xbeef,gr20 + test_gr_gr sp,gr21 + + inc_gr_immed 2,gr21 + set_gr_immed 2,gr7 + set_fr_iimmed 0xffff,0xffaa,fr8 + cstbfu fr8,@(sp,gr7),cc1,0 + test_mem_limmed 0xffad,0xaaef,gr20 + test_gr_gr sp,gr21 + + inc_gr_immed 1,gr21 + inc_gr_immed 2,sp + set_gr_immed -1,gr7 + set_fr_iimmed 0xffff,0xffbb,fr8 + cstbfu fr8,@(sp,gr7),cc5,0 + test_mem_limmed 0xffad,0xaabb,gr20 + test_gr_gr sp,gr21 + + set_gr_gr gr20,sp + set_gr_gr sp,gr21 + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cstbfu fr8,@(sp,gr7),cc1,1 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + set_gr_immed 2,gr7 + set_fr_iimmed 0xffff,0xffaa,fr8 + cstbfu fr8,@(sp,gr7),cc1,1 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + inc_gr_immed 4,gr21 + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + set_fr_iimmed 0xffff,0xffbb,fr8 + cstbfu fr8,@(sp,gr7),cc5,1 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + set_gr_gr gr20,sp + set_gr_gr sp,gr21 + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cstbfu fr8,@(sp,gr7),cc2,0 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + set_gr_immed 2,gr7 + set_fr_iimmed 0xffff,0xffaa,fr8 + cstbfu fr8,@(sp,gr7),cc2,1 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + inc_gr_immed 4,gr21 + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + set_fr_iimmed 0xffff,0xffbb,fr8 + cstbfu fr8,@(sp,gr7),cc6,0 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + set_gr_gr gr20,sp + set_gr_gr sp,gr21 + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cstbfu fr8,@(sp,gr7),cc3,1 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + set_gr_immed 2,gr7 + set_fr_iimmed 0xffff,0xffaa,fr8 + cstbfu fr8,@(sp,gr7),cc3,0 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + inc_gr_immed 4,gr21 + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + set_fr_iimmed 0xffff,0xffbb,fr8 + cstbfu fr8,@(sp,gr7),cc7,1 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + pass diff --git a/sim/testsuite/sim/frv/cstbu.cgs b/sim/testsuite/sim/frv/cstbu.cgs new file mode 100644 index 0000000..f8a9d0f --- /dev/null +++ b/sim/testsuite/sim/frv/cstbu.cgs @@ -0,0 +1,152 @@ +# frv testcase for cstbu $GRk,@($GRi,$GRj),$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cstbu +cstbu: + set_spr_immed 0x1b1b,cccr + set_gr_gr sp,gr21 + + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + cstbu gr8,@(sp,gr7),cc0,1 + test_mem_limmed 0xffad,0xbeef,sp + test_gr_gr sp,gr20 + + inc_gr_immed 2,gr20 + set_gr_immed 2,gr7 + set_gr_limmed 0xffff,0xffee,gr8 + cstbu gr8,@(sp,gr7),cc0,1 + test_mem_limmed 0xffad,0xeeef,gr21 + test_gr_gr sp,gr20 + + inc_gr_immed 1,gr20 + set_gr_immed -1,gr7 + inc_gr_immed 2,sp + set_gr_limmed 0xffff,0xff00,gr8 + cstbu gr8,@(sp,gr7),cc4,1 + inc_gr_immed -4,sp + test_mem_limmed 0xffad,0xee00,gr21 + + set_gr_gr gr21,sp + set_gr_gr gr21,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + cstbu gr8,@(sp,gr7),cc0,0 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + set_gr_immed 2,gr7 + set_gr_limmed 0xffff,0xffee,gr8 + cstbu gr8,@(sp,gr7),cc0,0 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + set_gr_immed -1,gr7 + inc_gr_immed 4,gr20 + inc_gr_immed 4,sp + set_gr_limmed 0xffff,0xff00,gr8 + cstbu gr8,@(sp,gr7),cc4,0 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + cstbu gr8,@(sp,gr7),cc1,0 + test_mem_limmed 0xffad,0xbeef,sp + test_gr_gr sp,gr20 + + inc_gr_immed 2,gr20 + set_gr_immed 2,gr7 + set_gr_limmed 0xffff,0xffee,gr8 + cstbu gr8,@(sp,gr7),cc1,0 + test_mem_limmed 0xffad,0xeeef,gr21 + test_gr_gr sp,gr20 + + inc_gr_immed 1,gr20 + set_gr_immed -1,gr7 + inc_gr_immed 2,sp + set_gr_limmed 0xffff,0xff00,gr8 + cstbu gr8,@(sp,gr7),cc5,0 + inc_gr_immed -4,sp + test_mem_limmed 0xffad,0xee00,gr21 + + set_gr_gr gr21,sp + set_gr_gr gr21,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + cstbu gr8,@(sp,gr7),cc1,1 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + set_gr_immed 2,gr7 + set_gr_limmed 0xffff,0xffee,gr8 + cstbu gr8,@(sp,gr7),cc1,1 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + set_gr_immed -1,gr7 + inc_gr_immed 4,gr20 + inc_gr_immed 4,sp + set_gr_limmed 0xffff,0xff00,gr8 + cstbu gr8,@(sp,gr7),cc5,1 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_gr_gr gr21,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + cstbu gr8,@(sp,gr7),cc2,0 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + set_gr_immed 2,gr7 + set_gr_limmed 0xffff,0xffee,gr8 + cstbu gr8,@(sp,gr7),cc2,1 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + set_gr_immed -1,gr7 + inc_gr_immed 4,gr20 + inc_gr_immed 4,sp + set_gr_limmed 0xffff,0xff00,gr8 + cstbu gr8,@(sp,gr7),cc6,0 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_gr_gr gr21,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + cstbu gr8,@(sp,gr7),cc3,1 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + set_gr_immed 2,gr7 + set_gr_limmed 0xffff,0xffee,gr8 + cstbu gr8,@(sp,gr7),cc3,0 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + set_gr_immed -1,gr7 + inc_gr_immed 4,gr20 + inc_gr_immed 4,sp + set_gr_limmed 0xffff,0xff00,gr8 + cstbu gr8,@(sp,gr7),cc7,1 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + pass diff --git a/sim/testsuite/sim/frv/cstd.cgs b/sim/testsuite/sim/frv/cstd.cgs new file mode 100644 index 0000000..6904414 --- /dev/null +++ b/sim/testsuite/sim/frv/cstd.cgs @@ -0,0 +1,221 @@ +# frv testcase for cstd $GRk,@($GRi,$GRj) +# mach: all + + .include "testutils.inc" + + start + + .global cstd +cstd: + set_spr_immed 0x1b1b,cccr + + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr20 + set_gr_gr sp,gr21 + + set_gr_immed 0,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_limmed 0xdead,0xbeef,gr9 + cstd gr8,@(sp,gr7),cc0,1 + test_mem_limmed 0xbeef,0xdead,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xbeef,gr21 + + set_gr_gr gr20,gr21 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_gr_limmed 0xbbbb,0xbbbb,gr9 + cstd gr8,@(sp,gr7),cc0,1 + test_mem_limmed 0xaaaa,0xaaaa,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbbbb,0xbbbb,gr21 + + set_gr_gr gr20,gr21 + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + set_gr_limmed 0xcccc,0xcccc,gr8 + set_gr_limmed 0xdddd,0xdddd,gr9 + cstd gr8,@(sp,gr7),cc4,1 + test_mem_limmed 0xcccc,0xcccc,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdddd,0xdddd,gr21 + + set_gr_gr gr20,gr21 + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed 4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + + set_gr_immed 0,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_limmed 0xdead,0xbeef,gr9 + cstd gr8,@(sp,gr7),cc0,0 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + + set_gr_gr gr20,gr21 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_gr_limmed 0xbbbb,0xbbbb,gr9 + cstd gr8,@(sp,gr7),cc0,0 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + + set_gr_gr gr20,gr21 + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + set_gr_limmed 0xcccc,0xcccc,gr8 + set_gr_limmed 0xdddd,0xdddd,gr9 + cstd gr8,@(sp,gr7),cc4,0 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + + set_gr_gr gr20,gr21 + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed 4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + + set_gr_immed 0,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_limmed 0xdead,0xbeef,gr9 + cstd gr8,@(sp,gr7),cc1,0 + test_mem_limmed 0xbeef,0xdead,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xbeef,gr21 + + set_gr_gr gr20,gr21 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_gr_limmed 0xbbbb,0xbbbb,gr9 + cstd gr8,@(sp,gr7),cc1,0 + test_mem_limmed 0xaaaa,0xaaaa,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbbbb,0xbbbb,gr21 + + set_gr_gr gr20,gr21 + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + set_gr_limmed 0xcccc,0xcccc,gr8 + set_gr_limmed 0xdddd,0xdddd,gr9 + cstd gr8,@(sp,gr7),cc5,0 + test_mem_limmed 0xcccc,0xcccc,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdddd,0xdddd,gr21 + + set_gr_gr gr20,gr21 + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed 4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + + set_gr_immed 0,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_limmed 0xdead,0xbeef,gr9 + cstd gr8,@(sp,gr7),cc1,1 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + + set_gr_gr gr20,gr21 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_gr_limmed 0xbbbb,0xbbbb,gr9 + cstd gr8,@(sp,gr7),cc1,1 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + + set_gr_gr gr20,gr21 + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + set_gr_limmed 0xcccc,0xcccc,gr8 + set_gr_limmed 0xdddd,0xdddd,gr9 + cstd gr8,@(sp,gr7),cc5,1 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + + set_gr_gr gr20,gr21 + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed 4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + + set_gr_immed 0,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_limmed 0xdead,0xbeef,gr9 + cstd gr8,@(sp,gr7),cc2,0 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + + set_gr_gr gr20,gr21 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_gr_limmed 0xbbbb,0xbbbb,gr9 + cstd gr8,@(sp,gr7),cc2,1 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + + set_gr_gr gr20,gr21 + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + set_gr_limmed 0xcccc,0xcccc,gr8 + set_gr_limmed 0xdddd,0xdddd,gr9 + cstd gr8,@(sp,gr7),cc6,0 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + + set_gr_gr gr20,gr21 + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed 4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + + set_gr_immed 0,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_limmed 0xdead,0xbeef,gr9 + cstd gr8,@(sp,gr7),cc3,1 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + + set_gr_gr gr20,gr21 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_gr_limmed 0xbbbb,0xbbbb,gr9 + cstd gr8,@(sp,gr7),cc3,0 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + + set_gr_gr gr20,gr21 + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + set_gr_limmed 0xcccc,0xcccc,gr8 + set_gr_limmed 0xdddd,0xdddd,gr9 + cstd gr8,@(sp,gr7),cc7,1 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + + pass diff --git a/sim/testsuite/sim/frv/cstdf.cgs b/sim/testsuite/sim/frv/cstdf.cgs new file mode 100644 index 0000000..fabbe93 --- /dev/null +++ b/sim/testsuite/sim/frv/cstdf.cgs @@ -0,0 +1,222 @@ +# frv testcase for cstdf $GRk,@($GRi,$GRj),$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cstdf +cstdf: + set_spr_immed 0x1b1b,cccr + set_gr_gr sp,gr20 + + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr21 + + set_gr_immed 0,gr7 + set_fr_iimmed 0xbeef,0xdead,fr8 + set_fr_iimmed 0xdead,0xbeef,fr9 + cstdf fr8,@(sp,gr7),cc0,1 + set_gr_gr gr21,gr22 + test_mem_limmed 0xbeef,0xdead,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xdead,0xbeef,gr22 + + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + set_fr_iimmed 0xaaaa,0xaaaa,fr8 + set_fr_iimmed 0xbbbb,0xbbbb,fr9 + cstdf fr8,@(sp,gr7),cc0,1 + set_gr_gr gr21,gr22 + test_mem_limmed 0xaaaa,0xaaaa,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xbbbb,0xbbbb,gr22 + + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + set_fr_iimmed 0xcccc,0xcccc,fr8 + set_fr_iimmed 0xdddd,0xdddd,fr9 + cstdf fr8,@(sp,gr7),cc4,1 + set_gr_gr gr21,gr22 + test_mem_limmed 0xcccc,0xcccc,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xdddd,0xdddd,gr22 + + set_gr_gr gr20,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr21 + + set_gr_immed 0,gr7 + set_fr_iimmed 0xbeef,0xdead,fr8 + set_fr_iimmed 0xdead,0xbeef,fr9 + cstdf fr8,@(sp,gr7),cc0,0 + set_gr_gr gr21,gr22 + test_mem_limmed 0xdead,0xbeef,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xbeef,0xdead,gr22 + + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + set_fr_iimmed 0xaaaa,0xaaaa,fr8 + set_fr_iimmed 0xbbbb,0xbbbb,fr9 + cstdf fr8,@(sp,gr7),cc0,0 + set_gr_gr gr21,gr22 + test_mem_limmed 0xdead,0xbeef,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xbeef,0xdead,gr22 + + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + set_fr_iimmed 0xcccc,0xcccc,fr8 + set_fr_iimmed 0xdddd,0xdddd,fr9 + cstdf fr8,@(sp,gr7),cc4,0 + set_gr_gr gr21,gr22 + test_mem_limmed 0xdead,0xbeef,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xbeef,0xdead,gr22 + + set_gr_gr gr20,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr21 + + set_gr_immed 0,gr7 + set_fr_iimmed 0xbeef,0xdead,fr8 + set_fr_iimmed 0xdead,0xbeef,fr9 + cstdf fr8,@(sp,gr7),cc1,0 + set_gr_gr gr21,gr22 + test_mem_limmed 0xbeef,0xdead,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xdead,0xbeef,gr22 + + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + set_fr_iimmed 0xaaaa,0xaaaa,fr8 + set_fr_iimmed 0xbbbb,0xbbbb,fr9 + cstdf fr8,@(sp,gr7),cc1,0 + set_gr_gr gr21,gr22 + test_mem_limmed 0xaaaa,0xaaaa,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xbbbb,0xbbbb,gr22 + + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + set_fr_iimmed 0xcccc,0xcccc,fr8 + set_fr_iimmed 0xdddd,0xdddd,fr9 + cstdf fr8,@(sp,gr7),cc5,0 + set_gr_gr gr21,gr22 + test_mem_limmed 0xcccc,0xcccc,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xdddd,0xdddd,gr22 + + set_gr_gr gr20,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr21 + + set_gr_immed 0,gr7 + set_fr_iimmed 0xbeef,0xdead,fr8 + set_fr_iimmed 0xdead,0xbeef,fr9 + cstdf fr8,@(sp,gr7),cc1,1 + set_gr_gr gr21,gr22 + test_mem_limmed 0xdead,0xbeef,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xbeef,0xdead,gr22 + + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + set_fr_iimmed 0xaaaa,0xaaaa,fr8 + set_fr_iimmed 0xbbbb,0xbbbb,fr9 + cstdf fr8,@(sp,gr7),cc1,1 + set_gr_gr gr21,gr22 + test_mem_limmed 0xdead,0xbeef,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xbeef,0xdead,gr22 + + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + set_fr_iimmed 0xcccc,0xcccc,fr8 + set_fr_iimmed 0xdddd,0xdddd,fr9 + cstdf fr8,@(sp,gr7),cc5,1 + set_gr_gr gr21,gr22 + test_mem_limmed 0xdead,0xbeef,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xbeef,0xdead,gr22 + + set_gr_gr gr20,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr21 + + set_gr_immed 0,gr7 + set_fr_iimmed 0xbeef,0xdead,fr8 + set_fr_iimmed 0xdead,0xbeef,fr9 + cstdf fr8,@(sp,gr7),cc2,0 + set_gr_gr gr21,gr22 + test_mem_limmed 0xdead,0xbeef,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xbeef,0xdead,gr22 + + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + set_fr_iimmed 0xaaaa,0xaaaa,fr8 + set_fr_iimmed 0xbbbb,0xbbbb,fr9 + cstdf fr8,@(sp,gr7),cc2,1 + set_gr_gr gr21,gr22 + test_mem_limmed 0xdead,0xbeef,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xbeef,0xdead,gr22 + + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + set_fr_iimmed 0xcccc,0xcccc,fr8 + set_fr_iimmed 0xdddd,0xdddd,fr9 + cstdf fr8,@(sp,gr7),cc6,0 + set_gr_gr gr21,gr22 + test_mem_limmed 0xdead,0xbeef,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xbeef,0xdead,gr22 + + set_gr_gr gr20,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr21 + + set_gr_immed 0,gr7 + set_fr_iimmed 0xbeef,0xdead,fr8 + set_fr_iimmed 0xdead,0xbeef,fr9 + cstdf fr8,@(sp,gr7),cc3,1 + set_gr_gr gr21,gr22 + test_mem_limmed 0xdead,0xbeef,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xbeef,0xdead,gr22 + + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + set_fr_iimmed 0xaaaa,0xaaaa,fr8 + set_fr_iimmed 0xbbbb,0xbbbb,fr9 + cstdf fr8,@(sp,gr7),cc3,0 + set_gr_gr gr21,gr22 + test_mem_limmed 0xdead,0xbeef,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xbeef,0xdead,gr22 + + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + set_fr_iimmed 0xcccc,0xcccc,fr8 + set_fr_iimmed 0xdddd,0xdddd,fr9 + cstdf fr8,@(sp,gr7),cc7,1 + set_gr_gr gr21,gr22 + test_mem_limmed 0xdead,0xbeef,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xbeef,0xdead,gr22 + + pass diff --git a/sim/testsuite/sim/frv/cstdfu.cgs b/sim/testsuite/sim/frv/cstdfu.cgs new file mode 100644 index 0000000..b489bc9 --- /dev/null +++ b/sim/testsuite/sim/frv/cstdfu.cgs @@ -0,0 +1,248 @@ +# frv testcase for cstdfu $GRk,@($GRi,$GRj),$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cstdfu +cstdfu: + set_spr_immed 0x1b1b,cccr + set_gr_gr sp,gr20 + + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr21 + + set_gr_immed 0,gr7 + set_fr_iimmed 0xbeef,0xdead,fr8 + set_fr_iimmed 0xdead,0xbeef,fr9 + cstdfu fr8,@(sp,gr7),cc0,1 + set_gr_gr gr21,gr22 + test_mem_limmed 0xbeef,0xdead,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xdead,0xbeef,gr22 + test_gr_gr sp,gr21 + + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + set_fr_iimmed 0xaaaa,0xaaaa,fr8 + set_fr_iimmed 0xbbbb,0xbbbb,fr9 + cstdfu fr8,@(sp,gr7),cc0,1 + set_gr_gr gr21,gr22 + test_mem_limmed 0xaaaa,0xaaaa,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xbbbb,0xbbbb,gr22 + test_gr_gr sp,gr21 + + inc_gr_immed 8,sp + set_gr_immed -8,gr7 + set_fr_iimmed 0xcccc,0xcccc,fr8 + set_fr_iimmed 0xdddd,0xdddd,fr9 + cstdfu fr8,@(sp,gr7),cc4,1 + set_gr_gr gr21,gr22 + test_mem_limmed 0xcccc,0xcccc,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xdddd,0xdddd,gr22 + test_gr_gr sp,gr21 + + set_gr_gr gr20,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr21 + + set_gr_immed 0,gr7 + set_fr_iimmed 0xbeef,0xdead,fr8 + set_fr_iimmed 0xdead,0xbeef,fr9 + cstdfu fr8,@(sp,gr7),cc0,0 + set_gr_gr gr21,gr22 + test_mem_limmed 0xdead,0xbeef,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xbeef,0xdead,gr22 + test_gr_gr sp,gr21 + + inc_gr_immed -8,sp + set_gr_gr sp,gr23 + set_gr_immed 8,gr7 + set_fr_iimmed 0xaaaa,0xaaaa,fr8 + set_fr_iimmed 0xbbbb,0xbbbb,fr9 + cstdfu fr8,@(sp,gr7),cc0,0 + set_gr_gr gr21,gr22 + test_mem_limmed 0xdead,0xbeef,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xbeef,0xdead,gr22 + test_gr_gr sp,gr23 + + inc_gr_immed 16,sp + set_gr_gr sp,gr23 + set_gr_immed -8,gr7 + set_fr_iimmed 0xcccc,0xcccc,fr8 + set_fr_iimmed 0xdddd,0xdddd,fr9 + cstdfu fr8,@(sp,gr7),cc4,0 + set_gr_gr gr21,gr22 + test_mem_limmed 0xdead,0xbeef,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xbeef,0xdead,gr22 + test_gr_gr sp,gr23 + + set_gr_gr gr20,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr21 + + set_gr_immed 0,gr7 + set_fr_iimmed 0xbeef,0xdead,fr8 + set_fr_iimmed 0xdead,0xbeef,fr9 + cstdfu fr8,@(sp,gr7),cc1,0 + set_gr_gr gr21,gr22 + test_mem_limmed 0xbeef,0xdead,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xdead,0xbeef,gr22 + test_gr_gr sp,gr21 + + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + set_fr_iimmed 0xaaaa,0xaaaa,fr8 + set_fr_iimmed 0xbbbb,0xbbbb,fr9 + cstdfu fr8,@(sp,gr7),cc1,0 + set_gr_gr gr21,gr22 + test_mem_limmed 0xaaaa,0xaaaa,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xbbbb,0xbbbb,gr22 + test_gr_gr sp,gr21 + + inc_gr_immed 8,sp + set_gr_immed -8,gr7 + set_fr_iimmed 0xcccc,0xcccc,fr8 + set_fr_iimmed 0xdddd,0xdddd,fr9 + cstdfu fr8,@(sp,gr7),cc5,0 + set_gr_gr gr21,gr22 + test_mem_limmed 0xcccc,0xcccc,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xdddd,0xdddd,gr22 + test_gr_gr sp,gr21 + + set_gr_gr gr20,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr21 + + set_gr_immed 0,gr7 + set_fr_iimmed 0xbeef,0xdead,fr8 + set_fr_iimmed 0xdead,0xbeef,fr9 + cstdfu fr8,@(sp,gr7),cc1,1 + set_gr_gr gr21,gr22 + test_mem_limmed 0xdead,0xbeef,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xbeef,0xdead,gr22 + test_gr_gr sp,gr21 + + inc_gr_immed -8,sp + set_gr_gr sp,gr23 + set_gr_immed 8,gr7 + set_fr_iimmed 0xaaaa,0xaaaa,fr8 + set_fr_iimmed 0xbbbb,0xbbbb,fr9 + cstdfu fr8,@(sp,gr7),cc1,1 + set_gr_gr gr21,gr22 + test_mem_limmed 0xdead,0xbeef,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xbeef,0xdead,gr22 + test_gr_gr sp,gr23 + + inc_gr_immed 16,sp + set_gr_gr sp,gr23 + set_gr_immed -8,gr7 + set_fr_iimmed 0xcccc,0xcccc,fr8 + set_fr_iimmed 0xdddd,0xdddd,fr9 + cstdfu fr8,@(sp,gr7),cc5,1 + set_gr_gr gr21,gr22 + test_mem_limmed 0xdead,0xbeef,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xbeef,0xdead,gr22 + test_gr_gr sp,gr23 + + set_gr_gr gr20,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr21 + + set_gr_immed 0,gr7 + set_fr_iimmed 0xbeef,0xdead,fr8 + set_fr_iimmed 0xdead,0xbeef,fr9 + cstdfu fr8,@(sp,gr7),cc2,0 + set_gr_gr gr21,gr22 + test_mem_limmed 0xdead,0xbeef,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xbeef,0xdead,gr22 + test_gr_gr sp,gr21 + + inc_gr_immed -8,sp + set_gr_gr sp,gr23 + set_gr_immed 8,gr7 + set_fr_iimmed 0xaaaa,0xaaaa,fr8 + set_fr_iimmed 0xbbbb,0xbbbb,fr9 + cstdfu fr8,@(sp,gr7),cc2,1 + set_gr_gr gr21,gr22 + test_mem_limmed 0xdead,0xbeef,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xbeef,0xdead,gr22 + test_gr_gr sp,gr23 + + inc_gr_immed 16,sp + set_gr_gr sp,gr23 + set_gr_immed -8,gr7 + set_fr_iimmed 0xcccc,0xcccc,fr8 + set_fr_iimmed 0xdddd,0xdddd,fr9 + cstdfu fr8,@(sp,gr7),cc6,0 + set_gr_gr gr21,gr22 + test_mem_limmed 0xdead,0xbeef,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xbeef,0xdead,gr22 + test_gr_gr sp,gr23 + + set_gr_gr gr20,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr21 + + set_gr_immed 0,gr7 + set_fr_iimmed 0xbeef,0xdead,fr8 + set_fr_iimmed 0xdead,0xbeef,fr9 + cstdfu fr8,@(sp,gr7),cc3,1 + set_gr_gr gr21,gr22 + test_mem_limmed 0xdead,0xbeef,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xbeef,0xdead,gr22 + test_gr_gr sp,gr21 + + inc_gr_immed -8,sp + set_gr_gr sp,gr23 + set_gr_immed 8,gr7 + set_fr_iimmed 0xaaaa,0xaaaa,fr8 + set_fr_iimmed 0xbbbb,0xbbbb,fr9 + cstdfu fr8,@(sp,gr7),cc3,0 + set_gr_gr gr21,gr22 + test_mem_limmed 0xdead,0xbeef,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xbeef,0xdead,gr22 + test_gr_gr sp,gr23 + + inc_gr_immed 16,sp + set_gr_gr sp,gr23 + set_gr_immed -8,gr7 + set_fr_iimmed 0xcccc,0xcccc,fr8 + set_fr_iimmed 0xdddd,0xdddd,fr9 + cstdfu fr8,@(sp,gr7),cc7,1 + set_gr_gr gr21,gr22 + test_mem_limmed 0xdead,0xbeef,gr22 + inc_gr_immed 4,gr22 + test_mem_limmed 0xbeef,0xdead,gr22 + test_gr_gr sp,gr23 + + pass diff --git a/sim/testsuite/sim/frv/cstdu.cgs b/sim/testsuite/sim/frv/cstdu.cgs new file mode 100644 index 0000000..a996ef6 --- /dev/null +++ b/sim/testsuite/sim/frv/cstdu.cgs @@ -0,0 +1,251 @@ +# frv testcase for cstdu $GRk,@($GRi,$GRj),$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cstdu +cstdu: + set_spr_immed 0x1b1b,cccr + + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr20 + set_gr_gr sp,gr21 + + set_gr_immed 0,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_limmed 0xdead,0xbeef,gr9 + cstdu gr8,@(sp,gr7),cc0,1 + test_mem_limmed 0xbeef,0xdead,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + set_gr_gr gr20,gr21 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_gr_limmed 0xbbbb,0xbbbb,gr9 + cstdu gr8,@(sp,gr7),cc0,1 + test_mem_limmed 0xaaaa,0xaaaa,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbbbb,0xbbbb,gr21 + test_gr_gr sp,gr20 + + set_gr_gr gr20,gr21 + inc_gr_immed 8,sp + set_gr_immed -8,gr7 + set_gr_limmed 0xcccc,0xcccc,gr8 + set_gr_limmed 0xdddd,0xdddd,gr9 + cstdu gr8,@(sp,gr7),cc4,1 + test_mem_limmed 0xcccc,0xcccc,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdddd,0xdddd,gr21 + test_gr_gr sp,gr20 + + set_gr_gr gr20,gr21 + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed 4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + + set_gr_gr sp,gr22 + set_gr_immed 0,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_limmed 0xdead,0xbeef,gr9 + cstdu gr8,@(sp,gr7),cc0,0 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + test_gr_gr sp,gr22 + + set_gr_gr gr20,gr21 + inc_gr_immed -8,sp + set_gr_gr sp,gr22 + set_gr_immed 8,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_gr_limmed 0xbbbb,0xbbbb,gr9 + cstdu gr8,@(sp,gr7),cc0,0 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + test_gr_gr sp,gr22 + + set_gr_gr gr20,gr21 + inc_gr_immed 16,sp + set_gr_gr sp,gr22 + set_gr_immed -8,gr7 + set_gr_limmed 0xcccc,0xcccc,gr8 + set_gr_limmed 0xdddd,0xdddd,gr9 + cstdu gr8,@(sp,gr7),cc4,0 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + test_gr_gr sp,gr22 + + set_gr_gr gr20,gr21 + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed 4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + + set_gr_immed 0,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_limmed 0xdead,0xbeef,gr9 + cstdu gr8,@(sp,gr7),cc1,0 + test_mem_limmed 0xbeef,0xdead,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + set_gr_gr gr20,gr21 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_gr_limmed 0xbbbb,0xbbbb,gr9 + cstdu gr8,@(sp,gr7),cc1,0 + test_mem_limmed 0xaaaa,0xaaaa,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbbbb,0xbbbb,gr21 + test_gr_gr sp,gr20 + + set_gr_gr gr20,gr21 + inc_gr_immed 8,sp + set_gr_immed -8,gr7 + set_gr_limmed 0xcccc,0xcccc,gr8 + set_gr_limmed 0xdddd,0xdddd,gr9 + cstdu gr8,@(sp,gr7),cc5,0 + test_mem_limmed 0xcccc,0xcccc,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdddd,0xdddd,gr21 + test_gr_gr sp,gr20 + + set_gr_gr gr20,gr21 + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed 4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + + set_gr_gr sp,gr22 + set_gr_immed 0,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_limmed 0xdead,0xbeef,gr9 + cstdu gr8,@(sp,gr7),cc1,1 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + test_gr_gr sp,gr22 + + set_gr_gr gr20,gr21 + inc_gr_immed -8,sp + set_gr_gr sp,gr22 + set_gr_immed 8,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_gr_limmed 0xbbbb,0xbbbb,gr9 + cstdu gr8,@(sp,gr7),cc1,1 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + test_gr_gr sp,gr22 + + set_gr_gr gr20,gr21 + inc_gr_immed 16,sp + set_gr_gr sp,gr22 + set_gr_immed -8,gr7 + set_gr_limmed 0xcccc,0xcccc,gr8 + set_gr_limmed 0xdddd,0xdddd,gr9 + cstdu gr8,@(sp,gr7),cc5,1 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + test_gr_gr sp,gr22 + + set_gr_gr gr20,gr21 + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed 4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + + set_gr_gr sp,gr22 + set_gr_immed 0,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_limmed 0xdead,0xbeef,gr9 + cstdu gr8,@(sp,gr7),cc2,0 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + test_gr_gr sp,gr22 + + set_gr_gr gr20,gr21 + inc_gr_immed -8,sp + set_gr_gr sp,gr22 + set_gr_immed 8,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_gr_limmed 0xbbbb,0xbbbb,gr9 + cstdu gr8,@(sp,gr7),cc2,1 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + test_gr_gr sp,gr22 + + set_gr_gr gr20,gr21 + inc_gr_immed 16,sp + set_gr_gr sp,gr22 + set_gr_immed -8,gr7 + set_gr_limmed 0xcccc,0xcccc,gr8 + set_gr_limmed 0xdddd,0xdddd,gr9 + cstdu gr8,@(sp,gr7),cc6,0 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + test_gr_gr sp,gr22 + + set_gr_gr gr20,gr21 + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed 4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + + set_gr_gr sp,gr22 + set_gr_immed 0,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_limmed 0xdead,0xbeef,gr9 + cstdu gr8,@(sp,gr7),cc3,1 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + test_gr_gr sp,gr22 + + set_gr_gr gr20,gr21 + inc_gr_immed -8,sp + set_gr_gr sp,gr22 + set_gr_immed 8,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_gr_limmed 0xbbbb,0xbbbb,gr9 + cstdu gr8,@(sp,gr7),cc3,0 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + test_gr_gr sp,gr22 + + set_gr_gr gr20,gr21 + inc_gr_immed 16,sp + set_gr_gr sp,gr22 + set_gr_immed -8,gr7 + set_gr_limmed 0xcccc,0xcccc,gr8 + set_gr_limmed 0xdddd,0xdddd,gr9 + cstdu gr8,@(sp,gr7),cc7,1 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + test_gr_gr sp,gr22 + + pass diff --git a/sim/testsuite/sim/frv/cstf.cgs b/sim/testsuite/sim/frv/cstf.cgs new file mode 100644 index 0000000..94c0f05 --- /dev/null +++ b/sim/testsuite/sim/frv/cstf.cgs @@ -0,0 +1,126 @@ +# frv testcase for cstf $FRk,@($GRi,$GRj),$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cstf +cstf: + set_spr_immed 0x1b1b,cccr + set_gr_gr sp,gr20 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cstf fr8,@(sp,gr7),cc0,1 + test_mem_limmed 0xffff,0xffff,gr20 + + set_gr_immed 4,gr7 + inc_gr_immed -4,sp + set_fr_iimmed 0xeeee,0xeeee,fr8 + cstf fr8,@(sp,gr7),cc0,1 + test_mem_limmed 0xeeee,0xeeee,gr20 + + set_gr_immed -4,gr7 + inc_gr_immed 8,sp + set_fr_iimmed 0xdddd,0xdddd,fr8 + cstf fr8,@(sp,gr7),cc4,1 + test_mem_limmed 0xdddd,0xdddd,gr20 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cstf fr8,@(sp,gr7),cc0,0 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_immed 4,gr7 + inc_gr_immed -4,sp + set_fr_iimmed 0xeeee,0xeeee,fr8 + cstf fr8,@(sp,gr7),cc0,0 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_immed -4,gr7 + inc_gr_immed 8,sp + set_fr_iimmed 0xdddd,0xdddd,fr8 + cstf fr8,@(sp,gr7),cc4,0 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cstf fr8,@(sp,gr7),cc1,0 + test_mem_limmed 0xffff,0xffff,gr20 + + set_gr_immed 4,gr7 + inc_gr_immed -4,sp + set_fr_iimmed 0xeeee,0xeeee,fr8 + cstf fr8,@(sp,gr7),cc1,0 + test_mem_limmed 0xeeee,0xeeee,gr20 + + set_gr_immed -4,gr7 + inc_gr_immed 8,sp + set_fr_iimmed 0xdddd,0xdddd,fr8 + cstf fr8,@(sp,gr7),cc5,0 + test_mem_limmed 0xdddd,0xdddd,gr20 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cstf fr8,@(sp,gr7),cc1,1 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_immed 4,gr7 + inc_gr_immed -4,sp + set_fr_iimmed 0xeeee,0xeeee,fr8 + cstf fr8,@(sp,gr7),cc1,1 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_immed -4,gr7 + inc_gr_immed 8,sp + set_fr_iimmed 0xdddd,0xdddd,fr8 + cstf fr8,@(sp,gr7),cc5,1 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cstf fr8,@(sp,gr7),cc2,0 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_immed 4,gr7 + inc_gr_immed -4,sp + set_fr_iimmed 0xeeee,0xeeee,fr8 + cstf fr8,@(sp,gr7),cc2,1 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_immed -4,gr7 + inc_gr_immed 8,sp + set_fr_iimmed 0xdddd,0xdddd,fr8 + cstf fr8,@(sp,gr7),cc6,0 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cstf fr8,@(sp,gr7),cc3,1 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_immed 4,gr7 + inc_gr_immed -4,sp + set_fr_iimmed 0xeeee,0xeeee,fr8 + cstf fr8,@(sp,gr7),cc3,0 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_immed -4,gr7 + inc_gr_immed 8,sp + set_fr_iimmed 0xdddd,0xdddd,fr8 + cstf fr8,@(sp,gr7),cc7,1 + test_mem_limmed 0xdead,0xbeef,gr20 + + pass diff --git a/sim/testsuite/sim/frv/cstfu.cgs b/sim/testsuite/sim/frv/cstfu.cgs new file mode 100644 index 0000000..ee450c8 --- /dev/null +++ b/sim/testsuite/sim/frv/cstfu.cgs @@ -0,0 +1,158 @@ +# frv testcase for cstfu $FRk,@($GRi,$GRj),$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cstfu +cstfu: + set_spr_immed 0x1b1b,cccr + set_gr_gr sp,gr20 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr21 + set_gr_immed 0,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cstfu fr8,@(sp,gr7),cc0,1 + test_mem_limmed 0xffff,0xffff,gr20 + test_gr_gr sp,gr21 + + set_gr_immed 4,gr7 + inc_gr_immed -4,sp + set_fr_iimmed 0xeeee,0xeeee,fr8 + cstfu fr8,@(sp,gr7),cc0,1 + test_mem_limmed 0xeeee,0xeeee,gr20 + test_gr_gr sp,gr21 + + set_gr_immed -4,gr7 + inc_gr_immed 4,sp + set_fr_iimmed 0xdddd,0xdddd,fr8 + cstfu fr8,@(sp,gr7),cc4,1 + test_mem_limmed 0xdddd,0xdddd,gr20 + test_gr_gr sp,gr21 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr21 + set_gr_immed 0,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cstfu fr8,@(sp,gr7),cc0,0 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + set_gr_immed 4,gr7 + inc_gr_immed -4,sp + inc_gr_immed -4,gr21 + set_fr_iimmed 0xeeee,0xeeee,fr8 + cstfu fr8,@(sp,gr7),cc0,0 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + set_gr_immed -4,gr7 + inc_gr_immed 8,sp + inc_gr_immed 8,gr21 + set_fr_iimmed 0xdddd,0xdddd,fr8 + cstfu fr8,@(sp,gr7),cc4,0 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr21 + set_gr_immed 0,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cstfu fr8,@(sp,gr7),cc1,0 + test_mem_limmed 0xffff,0xffff,gr20 + test_gr_gr sp,gr21 + + set_gr_immed 4,gr7 + inc_gr_immed -4,sp + set_fr_iimmed 0xeeee,0xeeee,fr8 + cstfu fr8,@(sp,gr7),cc1,0 + test_mem_limmed 0xeeee,0xeeee,gr20 + test_gr_gr sp,gr21 + + set_gr_immed -4,gr7 + inc_gr_immed 4,sp + set_fr_iimmed 0xdddd,0xdddd,fr8 + cstfu fr8,@(sp,gr7),cc5,0 + test_mem_limmed 0xdddd,0xdddd,gr20 + test_gr_gr sp,gr21 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr21 + set_gr_immed 0,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cstfu fr8,@(sp,gr7),cc1,1 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + set_gr_immed 4,gr7 + inc_gr_immed -4,sp + inc_gr_immed -4,gr21 + set_fr_iimmed 0xeeee,0xeeee,fr8 + cstfu fr8,@(sp,gr7),cc1,1 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + set_gr_immed -4,gr7 + inc_gr_immed 8,sp + inc_gr_immed 8,gr21 + set_fr_iimmed 0xdddd,0xdddd,fr8 + cstfu fr8,@(sp,gr7),cc5,1 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr21 + set_gr_immed 0,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cstfu fr8,@(sp,gr7),cc2,0 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + set_gr_immed 4,gr7 + inc_gr_immed -4,sp + inc_gr_immed -4,gr21 + set_fr_iimmed 0xeeee,0xeeee,fr8 + cstfu fr8,@(sp,gr7),cc2,1 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + set_gr_immed -4,gr7 + inc_gr_immed 8,sp + inc_gr_immed 8,gr21 + set_fr_iimmed 0xdddd,0xdddd,fr8 + cstfu fr8,@(sp,gr7),cc6,0 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr21 + set_gr_immed 0,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cstfu fr8,@(sp,gr7),cc3,1 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + set_gr_immed 4,gr7 + inc_gr_immed -4,sp + inc_gr_immed -4,gr21 + set_fr_iimmed 0xeeee,0xeeee,fr8 + cstfu fr8,@(sp,gr7),cc3,0 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + set_gr_immed -4,gr7 + inc_gr_immed 8,sp + inc_gr_immed 8,gr21 + set_fr_iimmed 0xdddd,0xdddd,fr8 + cstfu fr8,@(sp,gr7),cc7,1 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + pass diff --git a/sim/testsuite/sim/frv/csth.cgs b/sim/testsuite/sim/frv/csth.cgs new file mode 100644 index 0000000..b9f743c --- /dev/null +++ b/sim/testsuite/sim/frv/csth.cgs @@ -0,0 +1,120 @@ +# frv testcase for csth $GRk,@($GRi,$GRj),$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global csth +csth: + set_spr_immed 0x1b1b,cccr + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + csth gr8,@(sp,gr7),cc0,1 + test_mem_limmed 0xffff,0xbeef,sp + + set_gr_immed 2,gr7 + set_gr_limmed 0xffff,0xeeee,gr8 + csth gr8,@(sp,gr7),cc0,1 + test_mem_limmed 0xffff,0xeeee,sp + + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + set_gr_limmed 0xffff,0xdddd,gr8 + csth gr8,@(sp,gr7),cc4,1 + inc_gr_immed -4,sp + test_mem_limmed 0xffff,0xdddd,sp + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + csth gr8,@(sp,gr7),cc0,0 + test_mem_limmed 0xdead,0xbeef,sp + + set_gr_immed 2,gr7 + set_gr_limmed 0xffff,0xeeee,gr8 + csth gr8,@(sp,gr7),cc0,0 + test_mem_limmed 0xdead,0xbeef,sp + + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + set_gr_limmed 0xffff,0xdddd,gr8 + csth gr8,@(sp,gr7),cc4,0 + inc_gr_immed -4,sp + test_mem_limmed 0xdead,0xbeef,sp + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + csth gr8,@(sp,gr7),cc1,0 + test_mem_limmed 0xffff,0xbeef,sp + + set_gr_immed 2,gr7 + set_gr_limmed 0xffff,0xeeee,gr8 + csth gr8,@(sp,gr7),cc1,0 + test_mem_limmed 0xffff,0xeeee,sp + + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + set_gr_limmed 0xffff,0xdddd,gr8 + csth gr8,@(sp,gr7),cc5,0 + inc_gr_immed -4,sp + test_mem_limmed 0xffff,0xdddd,sp + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + csth gr8,@(sp,gr7),cc1,1 + test_mem_limmed 0xdead,0xbeef,sp + + set_gr_immed 2,gr7 + set_gr_limmed 0xffff,0xeeee,gr8 + csth gr8,@(sp,gr7),cc1,1 + test_mem_limmed 0xdead,0xbeef,sp + + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + set_gr_limmed 0xffff,0xdddd,gr8 + csth gr8,@(sp,gr7),cc5,1 + inc_gr_immed -4,sp + test_mem_limmed 0xdead,0xbeef,sp + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + csth gr8,@(sp,gr7),cc2,0 + test_mem_limmed 0xdead,0xbeef,sp + + set_gr_immed 2,gr7 + set_gr_limmed 0xffff,0xeeee,gr8 + csth gr8,@(sp,gr7),cc2,1 + test_mem_limmed 0xdead,0xbeef,sp + + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + set_gr_limmed 0xffff,0xdddd,gr8 + csth gr8,@(sp,gr7),cc6,0 + inc_gr_immed -4,sp + test_mem_limmed 0xdead,0xbeef,sp + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + csth gr8,@(sp,gr7),cc3,1 + test_mem_limmed 0xdead,0xbeef,sp + + set_gr_immed 2,gr7 + set_gr_limmed 0xffff,0xeeee,gr8 + csth gr8,@(sp,gr7),cc3,0 + test_mem_limmed 0xdead,0xbeef,sp + + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + set_gr_limmed 0xffff,0xdddd,gr8 + csth gr8,@(sp,gr7),cc7,1 + inc_gr_immed -4,sp + test_mem_limmed 0xdead,0xbeef,sp + + pass diff --git a/sim/testsuite/sim/frv/csthf.cgs b/sim/testsuite/sim/frv/csthf.cgs new file mode 100644 index 0000000..21a64c8 --- /dev/null +++ b/sim/testsuite/sim/frv/csthf.cgs @@ -0,0 +1,120 @@ +# frv testcase for csthf $FRk,@($GRi,$GRj),$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global csthf +csthf: + set_spr_immed 0x1b1b,cccr + set_gr_gr sp,gr20 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_fr_iimmed 0x1111,0xffff,fr8 + csthf fr8,@(sp,gr7),cc0,1 + test_mem_limmed 0xffff,0xbeef,gr20 + + set_gr_immed 2,gr7 + set_fr_iimmed 0xffff,0xaaaa,fr8 + csthf fr8,@(sp,gr7),cc0,1 + test_mem_limmed 0xffff,0xaaaa,gr20 + + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + set_fr_iimmed 0x2222,0xbbbb,fr8 + csthf fr8,@(sp,gr7),cc4,1 + test_mem_limmed 0xffff,0xbbbb,gr20 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_fr_iimmed 0x1111,0xffff,fr8 + csthf fr8,@(sp,gr7),cc0,0 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_immed 2,gr7 + set_fr_iimmed 0xffff,0xaaaa,fr8 + csthf fr8,@(sp,gr7),cc0,0 + test_mem_limmed 0xdead,0xbeef,gr20 + + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + set_fr_iimmed 0x2222,0xbbbb,fr8 + csthf fr8,@(sp,gr7),cc4,0 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_fr_iimmed 0x1111,0xffff,fr8 + csthf fr8,@(sp,gr7),cc1,0 + test_mem_limmed 0xffff,0xbeef,gr20 + + set_gr_immed 2,gr7 + set_fr_iimmed 0xffff,0xaaaa,fr8 + csthf fr8,@(sp,gr7),cc1,0 + test_mem_limmed 0xffff,0xaaaa,gr20 + + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + set_fr_iimmed 0x2222,0xbbbb,fr8 + csthf fr8,@(sp,gr7),cc5,0 + test_mem_limmed 0xffff,0xbbbb,gr20 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_fr_iimmed 0x1111,0xffff,fr8 + csthf fr8,@(sp,gr7),cc1,1 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_immed 2,gr7 + set_fr_iimmed 0xffff,0xaaaa,fr8 + csthf fr8,@(sp,gr7),cc1,1 + test_mem_limmed 0xdead,0xbeef,gr20 + + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + set_fr_iimmed 0x2222,0xbbbb,fr8 + csthf fr8,@(sp,gr7),cc5,1 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_fr_iimmed 0x1111,0xffff,fr8 + csthf fr8,@(sp,gr7),cc2,0 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_immed 2,gr7 + set_fr_iimmed 0xffff,0xaaaa,fr8 + csthf fr8,@(sp,gr7),cc2,1 + test_mem_limmed 0xdead,0xbeef,gr20 + + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + set_fr_iimmed 0x2222,0xbbbb,fr8 + csthf fr8,@(sp,gr7),cc6,0 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_fr_iimmed 0x1111,0xffff,fr8 + csthf fr8,@(sp,gr7),cc3,1 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_immed 2,gr7 + set_fr_iimmed 0xffff,0xaaaa,fr8 + csthf fr8,@(sp,gr7),cc3,0 + test_mem_limmed 0xdead,0xbeef,gr20 + + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + set_fr_iimmed 0x2222,0xbbbb,fr8 + csthf fr8,@(sp,gr7),cc7,1 + test_mem_limmed 0xdead,0xbeef,gr20 + + pass diff --git a/sim/testsuite/sim/frv/csthfu.cgs b/sim/testsuite/sim/frv/csthfu.cgs new file mode 100644 index 0000000..252ae7d --- /dev/null +++ b/sim/testsuite/sim/frv/csthfu.cgs @@ -0,0 +1,150 @@ +# frv testcase for csthfu $FRk,@($GRi,$GRj),$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global csthfu +csthfu: + set_spr_immed 0x1b1b,cccr + set_gr_gr sp,gr20 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr21 + set_gr_immed 0,gr7 + set_fr_iimmed 0x1111,0xffff,fr8 + csthfu fr8,@(sp,gr7),cc0,1 + test_mem_limmed 0xffff,0xbeef,gr20 + test_gr_gr sp,gr21 + + inc_gr_immed 2,gr21 + set_gr_immed 2,gr7 + set_fr_iimmed 0xffff,0xaaaa,fr8 + csthfu fr8,@(sp,gr7),cc0,1 + test_mem_limmed 0xffff,0xaaaa,gr20 + test_gr_gr sp,gr21 + + inc_gr_immed 2,sp + set_gr_immed -2,gr7 + set_fr_iimmed 0x2222,0xbbbb,fr8 + csthfu fr8,@(sp,gr7),cc4,1 + test_mem_limmed 0xffff,0xbbbb,gr20 + test_gr_gr sp,gr21 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr21 + set_gr_immed 0,gr7 + set_fr_iimmed 0x1111,0xffff,fr8 + csthfu fr8,@(sp,gr7),cc0,0 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + set_gr_immed 2,gr7 + set_fr_iimmed 0xffff,0xaaaa,fr8 + csthfu fr8,@(sp,gr7),cc0,0 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + inc_gr_immed 4,gr21 + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + set_fr_iimmed 0x2222,0xbbbb,fr8 + csthfu fr8,@(sp,gr7),cc4,0 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr21 + set_gr_immed 0,gr7 + set_fr_iimmed 0x1111,0xffff,fr8 + csthfu fr8,@(sp,gr7),cc1,0 + test_mem_limmed 0xffff,0xbeef,gr20 + test_gr_gr sp,gr21 + + inc_gr_immed 2,gr21 + set_gr_immed 2,gr7 + set_fr_iimmed 0xffff,0xaaaa,fr8 + csthfu fr8,@(sp,gr7),cc1,0 + test_mem_limmed 0xffff,0xaaaa,gr20 + test_gr_gr sp,gr21 + + inc_gr_immed 2,sp + set_gr_immed -2,gr7 + set_fr_iimmed 0x2222,0xbbbb,fr8 + csthfu fr8,@(sp,gr7),cc5,0 + test_mem_limmed 0xffff,0xbbbb,gr20 + test_gr_gr sp,gr21 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr21 + set_gr_immed 0,gr7 + set_fr_iimmed 0x1111,0xffff,fr8 + csthfu fr8,@(sp,gr7),cc1,1 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + set_gr_immed 2,gr7 + set_fr_iimmed 0xffff,0xaaaa,fr8 + csthfu fr8,@(sp,gr7),cc1,1 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + inc_gr_immed 4,gr21 + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + set_fr_iimmed 0x2222,0xbbbb,fr8 + csthfu fr8,@(sp,gr7),cc5,1 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr21 + set_gr_immed 0,gr7 + set_fr_iimmed 0x1111,0xffff,fr8 + csthfu fr8,@(sp,gr7),cc2,0 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + set_gr_immed 2,gr7 + set_fr_iimmed 0xffff,0xaaaa,fr8 + csthfu fr8,@(sp,gr7),cc2,1 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + inc_gr_immed 4,gr21 + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + set_fr_iimmed 0x2222,0xbbbb,fr8 + csthfu fr8,@(sp,gr7),cc6,0 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr21 + set_gr_immed 0,gr7 + set_fr_iimmed 0x1111,0xffff,fr8 + csthfu fr8,@(sp,gr7),cc3,1 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + set_gr_immed 2,gr7 + set_fr_iimmed 0xffff,0xaaaa,fr8 + csthfu fr8,@(sp,gr7),cc3,0 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + inc_gr_immed 4,gr21 + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + set_fr_iimmed 0x2222,0xbbbb,fr8 + csthfu fr8,@(sp,gr7),cc7,1 + test_mem_limmed 0xdead,0xbeef,gr20 + test_gr_gr sp,gr21 + + pass diff --git a/sim/testsuite/sim/frv/csthu.cgs b/sim/testsuite/sim/frv/csthu.cgs new file mode 100644 index 0000000..c7e2255 --- /dev/null +++ b/sim/testsuite/sim/frv/csthu.cgs @@ -0,0 +1,150 @@ +# frv testcase for csthu $GRk,@($GRi,$GRj),$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global csthu +csthu: + set_spr_immed 0x1b1b,cccr + set_gr_gr sp,gr20 + set_gr_gr sp,gr21 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + csthu gr8,@(sp,gr7),cc0,1 + test_mem_limmed 0xffff,0xbeef,gr21 + test_gr_gr sp,gr20 + + inc_gr_immed 2,gr20 + set_gr_immed 2,gr7 + set_gr_limmed 0xdead,0xeeee,gr8 + csthu gr8,@(sp,gr7),cc0,1 + test_mem_limmed 0xffff,0xeeee,gr21 + test_gr_gr sp,gr20 + + inc_gr_immed 2,sp + set_gr_immed -2,gr7 + set_gr_limmed 0xffff,0xdddd,gr8 + csthu gr8,@(sp,gr7),cc4,1 + test_mem_limmed 0xffff,0xdddd,gr21 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_gr_gr gr21,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + csthu gr8,@(sp,gr7),cc0,0 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + set_gr_immed 2,gr7 + set_gr_limmed 0xffff,0xeeee,gr8 + csthu gr8,@(sp,gr7),cc0,0 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + inc_gr_immed 4,gr20 + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + set_gr_limmed 0xffff,0xdddd,gr8 + csthu gr8,@(sp,gr7),cc4,0 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + set_gr_gr gr21,gr20 + set_gr_gr gr21,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + csthu gr8,@(sp,gr7),cc1,0 + test_mem_limmed 0xffff,0xbeef,gr21 + test_gr_gr sp,gr20 + + inc_gr_immed 2,gr20 + set_gr_immed 2,gr7 + set_gr_limmed 0xdead,0xeeee,gr8 + csthu gr8,@(sp,gr7),cc1,0 + test_mem_limmed 0xffff,0xeeee,gr21 + test_gr_gr sp,gr20 + + inc_gr_immed 2,sp + set_gr_immed -2,gr7 + set_gr_limmed 0xffff,0xdddd,gr8 + csthu gr8,@(sp,gr7),cc5,0 + test_mem_limmed 0xffff,0xdddd,gr21 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_gr_gr gr21,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + csthu gr8,@(sp,gr7),cc1,1 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + set_gr_immed 2,gr7 + set_gr_limmed 0xffff,0xeeee,gr8 + csthu gr8,@(sp,gr7),cc1,1 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + inc_gr_immed 4,gr20 + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + set_gr_limmed 0xffff,0xdddd,gr8 + csthu gr8,@(sp,gr7),cc5,1 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_gr_gr gr21,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + csthu gr8,@(sp,gr7),cc2,0 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + set_gr_immed 2,gr7 + set_gr_limmed 0xffff,0xeeee,gr8 + csthu gr8,@(sp,gr7),cc2,1 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + inc_gr_immed 4,gr20 + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + set_gr_limmed 0xffff,0xdddd,gr8 + csthu gr8,@(sp,gr7),cc6,0 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_gr_gr gr21,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + csthu gr8,@(sp,gr7),cc3,1 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + set_gr_immed 2,gr7 + set_gr_limmed 0xffff,0xeeee,gr8 + csthu gr8,@(sp,gr7),cc3,0 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + inc_gr_immed 4,gr20 + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + set_gr_limmed 0xffff,0xdddd,gr8 + csthu gr8,@(sp,gr7),cc7,1 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + pass diff --git a/sim/testsuite/sim/frv/cstq.cgs b/sim/testsuite/sim/frv/cstq.cgs new file mode 100644 index 0000000..6f18332 --- /dev/null +++ b/sim/testsuite/sim/frv/cstq.cgs @@ -0,0 +1,355 @@ +# frv testcase for cstq $GRk,@($GRi,$GRj),$CCi,$cond +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global cstq +cstq: + set_spr_immed 0x1b1b,cccr + + set_gr_gr sp,gr22 + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xbeef,sp + set_gr_gr sp,gr20 + set_gr_gr sp,gr21 + + set_gr_immed 0,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_limmed 0xdead,0xbeef,gr9 + set_gr_limmed 0xdead,0xdead,gr10 + set_gr_limmed 0xbeef,0xbeef,gr11 + cstq gr8,@(sp,gr7),cc0,1 + test_mem_limmed 0xbeef,0xdead,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xdead,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xbeef,gr21 + + set_gr_gr gr20,gr21 + inc_gr_immed -16,sp + set_gr_immed 16,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_gr_limmed 0xbbbb,0xbbbb,gr9 + set_gr_limmed 0xcccc,0xcccc,gr10 + set_gr_limmed 0xdddd,0xdddd,gr11 + cstq gr8,@(sp,gr7),cc0,1 + test_mem_limmed 0xaaaa,0xaaaa,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbbbb,0xbbbb,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xcccc,0xcccc,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdddd,0xdddd,gr21 + + set_gr_gr gr20,gr21 + inc_gr_immed 32,sp + set_gr_immed -16,gr7 + set_gr_limmed 0x1111,0x1111,gr8 + set_gr_limmed 0x2222,0x2222,gr9 + set_gr_limmed 0x3333,0x3333,gr10 + set_gr_limmed 0x4444,0x4444,gr11 + cstq gr8,@(sp,gr7),cc4,1 + test_mem_limmed 0x1111,0x1111,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0x2222,0x2222,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0x3333,0x3333,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0x4444,0x4444,gr21 + + set_gr_gr gr22,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xbeef,sp + set_gr_gr sp,gr20 + set_gr_gr sp,gr21 + + set_gr_immed 0,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_limmed 0xdead,0xbeef,gr9 + set_gr_limmed 0xdead,0xdead,gr10 + set_gr_limmed 0xbeef,0xbeef,gr11 + cstq gr8,@(sp,gr7),cc0,0 + test_mem_limmed 0xbeef,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xdead,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + + set_gr_gr gr20,gr21 + inc_gr_immed -16,sp + set_gr_immed 16,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_gr_limmed 0xbbbb,0xbbbb,gr9 + set_gr_limmed 0xcccc,0xcccc,gr10 + set_gr_limmed 0xdddd,0xdddd,gr11 + cstq gr8,@(sp,gr7),cc0,0 + test_mem_limmed 0xbeef,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xdead,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + + set_gr_gr gr20,gr21 + inc_gr_immed 32,sp + set_gr_immed -16,gr7 + set_gr_limmed 0x1111,0x1111,gr8 + set_gr_limmed 0x2222,0x2222,gr9 + set_gr_limmed 0x3333,0x3333,gr10 + set_gr_limmed 0x4444,0x4444,gr11 + cstq gr8,@(sp,gr7),cc4,0 + test_mem_limmed 0xbeef,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xdead,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + + set_gr_gr gr22,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xbeef,sp + set_gr_gr sp,gr20 + set_gr_gr sp,gr21 + + set_gr_immed 0,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_limmed 0xdead,0xbeef,gr9 + set_gr_limmed 0xdead,0xdead,gr10 + set_gr_limmed 0xbeef,0xbeef,gr11 + cstq gr8,@(sp,gr7),cc1,0 + test_mem_limmed 0xbeef,0xdead,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xdead,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xbeef,gr21 + + set_gr_gr gr20,gr21 + inc_gr_immed -16,sp + set_gr_immed 16,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_gr_limmed 0xbbbb,0xbbbb,gr9 + set_gr_limmed 0xcccc,0xcccc,gr10 + set_gr_limmed 0xdddd,0xdddd,gr11 + cstq gr8,@(sp,gr7),cc1,0 + test_mem_limmed 0xaaaa,0xaaaa,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbbbb,0xbbbb,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xcccc,0xcccc,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdddd,0xdddd,gr21 + + set_gr_gr gr20,gr21 + inc_gr_immed 32,sp + set_gr_immed -16,gr7 + set_gr_limmed 0x1111,0x1111,gr8 + set_gr_limmed 0x2222,0x2222,gr9 + set_gr_limmed 0x3333,0x3333,gr10 + set_gr_limmed 0x4444,0x4444,gr11 + cstq gr8,@(sp,gr7),cc5,0 + test_mem_limmed 0x1111,0x1111,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0x2222,0x2222,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0x3333,0x3333,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0x4444,0x4444,gr21 + + set_gr_gr gr22,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xbeef,sp + set_gr_gr sp,gr20 + set_gr_gr sp,gr21 + + set_gr_immed 0,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_limmed 0xdead,0xbeef,gr9 + set_gr_limmed 0xdead,0xdead,gr10 + set_gr_limmed 0xbeef,0xbeef,gr11 + cstq gr8,@(sp,gr7),cc1,1 + test_mem_limmed 0xbeef,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xdead,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + + set_gr_gr gr20,gr21 + inc_gr_immed -16,sp + set_gr_immed 16,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_gr_limmed 0xbbbb,0xbbbb,gr9 + set_gr_limmed 0xcccc,0xcccc,gr10 + set_gr_limmed 0xdddd,0xdddd,gr11 + cstq gr8,@(sp,gr7),cc1,1 + test_mem_limmed 0xbeef,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xdead,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + + set_gr_gr gr20,gr21 + inc_gr_immed 32,sp + set_gr_immed -16,gr7 + set_gr_limmed 0x1111,0x1111,gr8 + set_gr_limmed 0x2222,0x2222,gr9 + set_gr_limmed 0x3333,0x3333,gr10 + set_gr_limmed 0x4444,0x4444,gr11 + cstq gr8,@(sp,gr7),cc5,1 + test_mem_limmed 0xbeef,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xdead,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + + set_gr_gr gr22,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xbeef,sp + set_gr_gr sp,gr20 + set_gr_gr sp,gr21 + + set_gr_immed 0,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_limmed 0xdead,0xbeef,gr9 + set_gr_limmed 0xdead,0xdead,gr10 + set_gr_limmed 0xbeef,0xbeef,gr11 + cstq gr8,@(sp,gr7),cc2,0 + test_mem_limmed 0xbeef,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xdead,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + + set_gr_gr gr20,gr21 + inc_gr_immed -16,sp + set_gr_immed 16,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_gr_limmed 0xbbbb,0xbbbb,gr9 + set_gr_limmed 0xcccc,0xcccc,gr10 + set_gr_limmed 0xdddd,0xdddd,gr11 + cstq gr8,@(sp,gr7),cc2,1 + test_mem_limmed 0xbeef,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xdead,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + + set_gr_gr gr20,gr21 + inc_gr_immed 32,sp + set_gr_immed -16,gr7 + set_gr_limmed 0x1111,0x1111,gr8 + set_gr_limmed 0x2222,0x2222,gr9 + set_gr_limmed 0x3333,0x3333,gr10 + set_gr_limmed 0x4444,0x4444,gr11 + cstq gr8,@(sp,gr7),cc6,0 + test_mem_limmed 0xbeef,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xdead,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + + set_gr_gr gr22,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xbeef,sp + set_gr_gr sp,gr20 + set_gr_gr sp,gr21 + + set_gr_immed 0,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_limmed 0xdead,0xbeef,gr9 + set_gr_limmed 0xdead,0xdead,gr10 + set_gr_limmed 0xbeef,0xbeef,gr11 + cstq gr8,@(sp,gr7),cc3,1 + test_mem_limmed 0xbeef,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xdead,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + + set_gr_gr gr20,gr21 + inc_gr_immed -16,sp + set_gr_immed 16,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_gr_limmed 0xbbbb,0xbbbb,gr9 + set_gr_limmed 0xcccc,0xcccc,gr10 + set_gr_limmed 0xdddd,0xdddd,gr11 + cstq gr8,@(sp,gr7),cc3,0 + test_mem_limmed 0xbeef,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xdead,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + + set_gr_gr gr20,gr21 + inc_gr_immed 32,sp + set_gr_immed -16,gr7 + set_gr_limmed 0x1111,0x1111,gr8 + set_gr_limmed 0x2222,0x2222,gr9 + set_gr_limmed 0x3333,0x3333,gr10 + set_gr_limmed 0x4444,0x4444,gr11 + cstq gr8,@(sp,gr7),cc7,1 + test_mem_limmed 0xbeef,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xdead,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xdead,0xbeef,gr21 + inc_gr_immed 4,gr21 + test_mem_limmed 0xbeef,0xdead,gr21 + + pass diff --git a/sim/testsuite/sim/frv/cstu.cgs b/sim/testsuite/sim/frv/cstu.cgs new file mode 100644 index 0000000..81a5b82 --- /dev/null +++ b/sim/testsuite/sim/frv/cstu.cgs @@ -0,0 +1,152 @@ +# frv testcase for cstu $GRk,@($GRi,$GRj),$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cstu +cstu: + set_spr_immed 0x1b1b,cccr + set_gr_gr sp,gr21 + + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + cstu gr8,@(sp,gr7),cc0,1 + test_mem_limmed 0xffff,0xffff,gr21 + test_gr_gr sp,gr21 + + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + set_gr_limmed 0xeeee,0xffff,gr8 + cstu gr8,@(sp,gr7),cc0,1 + test_mem_limmed 0xeeee,0xffff,gr21 + test_gr_gr sp,gr21 + + inc_gr_immed 4,sp + set_gr_immed -4,gr7 + set_gr_limmed 0xcccc,0xdddd,gr8 + cstu gr8,@(sp,gr7),cc4,1 + test_mem_limmed 0xcccc,0xdddd,gr21 + test_gr_gr sp,gr21 + + set_gr_gr gr21,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + cstu gr8,@(sp,gr7),cc0,0 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr21 + + inc_gr_immed -4,sp + set_gr_gr sp,gr20 + set_gr_immed 4,gr7 + set_gr_limmed 0xeeee,0xffff,gr8 + cstu gr8,@(sp,gr7),cc0,0 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + inc_gr_immed 8,sp + set_gr_gr sp,gr20 + set_gr_immed -4,gr7 + set_gr_limmed 0xcccc,0xdddd,gr8 + cstu gr8,@(sp,gr7),cc4,0 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + cstu gr8,@(sp,gr7),cc1,0 + test_mem_limmed 0xffff,0xffff,gr21 + test_gr_gr sp,gr21 + + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + set_gr_limmed 0xeeee,0xffff,gr8 + cstu gr8,@(sp,gr7),cc1,0 + test_mem_limmed 0xeeee,0xffff,gr21 + test_gr_gr sp,gr21 + + inc_gr_immed 4,sp + set_gr_immed -4,gr7 + set_gr_limmed 0xcccc,0xdddd,gr8 + cstu gr8,@(sp,gr7),cc5,0 + test_mem_limmed 0xcccc,0xdddd,gr21 + test_gr_gr sp,gr21 + + set_gr_gr gr21,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + cstu gr8,@(sp,gr7),cc1,1 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr21 + + inc_gr_immed -4,sp + set_gr_gr sp,gr20 + set_gr_immed 4,gr7 + set_gr_limmed 0xeeee,0xffff,gr8 + cstu gr8,@(sp,gr7),cc1,1 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + inc_gr_immed 8,sp + set_gr_gr sp,gr20 + set_gr_immed -4,gr7 + set_gr_limmed 0xcccc,0xdddd,gr8 + cstu gr8,@(sp,gr7),cc5,1 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + cstu gr8,@(sp,gr7),cc2,0 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr21 + + inc_gr_immed -4,sp + set_gr_gr sp,gr20 + set_gr_immed 4,gr7 + set_gr_limmed 0xeeee,0xffff,gr8 + cstu gr8,@(sp,gr7),cc2,1 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + inc_gr_immed 8,sp + set_gr_gr sp,gr20 + set_gr_immed -4,gr7 + set_gr_limmed 0xcccc,0xdddd,gr8 + cstu gr8,@(sp,gr7),cc6,0 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + set_gr_gr gr21,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + cstu gr8,@(sp,gr7),cc3,1 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr21 + + inc_gr_immed -4,sp + set_gr_gr sp,gr20 + set_gr_immed 4,gr7 + set_gr_limmed 0xeeee,0xffff,gr8 + cstu gr8,@(sp,gr7),cc3,0 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + inc_gr_immed 8,sp + set_gr_gr sp,gr20 + set_gr_immed -4,gr7 + set_gr_limmed 0xcccc,0xdddd,gr8 + cstu gr8,@(sp,gr7),cc7,1 + test_mem_limmed 0xdead,0xbeef,gr21 + test_gr_gr sp,gr20 + + pass diff --git a/sim/testsuite/sim/frv/csub.cgs b/sim/testsuite/sim/frv/csub.cgs new file mode 100644 index 0000000..7d07c14 --- /dev/null +++ b/sim/testsuite/sim/frv/csub.cgs @@ -0,0 +1,108 @@ +# frv testcase for csub $GRi,$GRj,$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global csub +csub: + set_spr_immed 0x1b1b,cccr + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + csub gr8,gr7,gr8,cc4,1 + test_gr_immed 1,gr8 + + set_gr_immed 1,gr7 + set_gr_limmed 0x8000,0x0000,gr8 + csub gr8,gr7,gr8,cc4,1 + test_gr_limmed 0x7fff,0xffff,gr8 + + csub gr8,gr8,gr8,cc4,1 + test_gr_immed 0,gr8 + + csub gr8,gr7,gr8,cc4,1 + test_gr_immed -1,gr8 + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + csub gr8,gr7,gr8,cc4,0 + test_gr_immed 2,gr8 + + set_gr_immed 1,gr7 + set_gr_limmed 0x8000,0x0000,gr8 + csub gr8,gr7,gr8,cc4,0 + test_gr_limmed 0x8000,0x0000,gr8 + + csub gr8,gr8,gr8,cc4,0 + test_gr_limmed 0x8000,0x0000,gr8 + + csub gr8,gr7,gr8,cc4,0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + csub gr8,gr7,gr8,cc5,0 + test_gr_immed 1,gr8 + + set_gr_immed 1,gr7 + set_gr_limmed 0x8000,0x0000,gr8 + csub gr8,gr7,gr8,cc5,0 + test_gr_limmed 0x7fff,0xffff,gr8 + + csub gr8,gr8,gr8,cc5,0 + test_gr_immed 0,gr8 + + csub gr8,gr7,gr8,cc5,0 + test_gr_immed -1,gr8 + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + csub gr8,gr7,gr8,cc5,1 + test_gr_immed 2,gr8 + + set_gr_immed 1,gr7 + set_gr_limmed 0x8000,0x0000,gr8 + csub gr8,gr7,gr8,cc5,1 + test_gr_limmed 0x8000,0x0000,gr8 + + csub gr8,gr8,gr8,cc5,1 + test_gr_limmed 0x8000,0x0000,gr8 + + csub gr8,gr7,gr8,cc5,1 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + csub gr8,gr7,gr8,cc6,1 + test_gr_immed 2,gr8 + + set_gr_immed 1,gr7 + set_gr_limmed 0x8000,0x0000,gr8 + csub gr8,gr7,gr8,cc6,0 + test_gr_limmed 0x8000,0x0000,gr8 + + csub gr8,gr8,gr8,cc6,1 + test_gr_limmed 0x8000,0x0000,gr8 + + csub gr8,gr7,gr8,cc6,0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + csub gr8,gr7,gr8,cc7,0 + test_gr_immed 2,gr8 + + set_gr_immed 1,gr7 + set_gr_limmed 0x8000,0x0000,gr8 + csub gr8,gr7,gr8,cc7,1 + test_gr_limmed 0x8000,0x0000,gr8 + + csub gr8,gr8,gr8,cc7,0 + test_gr_limmed 0x8000,0x0000,gr8 + + csub gr8,gr7,gr8,cc7,1 + test_gr_limmed 0x8000,0x0000,gr8 + + pass diff --git a/sim/testsuite/sim/frv/csubcc.cgs b/sim/testsuite/sim/frv/csubcc.cgs new file mode 100644 index 0000000..64cd93b --- /dev/null +++ b/sim/testsuite/sim/frv/csubcc.cgs @@ -0,0 +1,156 @@ +# frv testcase for csubcc $GRi,$GRj,$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global csubcc +csubcc: + set_spr_immed 0x1b1b,cccr + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + csubcc gr8,gr7,gr8,cc0,1 + test_icc 0 0 0 0 icc0 + test_gr_immed 1,gr8 + + set_gr_immed 1,gr7 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0d,0 ; Set mask opposite of expected + csubcc gr8,gr7,gr8,cc0,1 + test_icc 0 0 1 0 icc0 + test_gr_limmed 0x7fff,0xffff,gr8 + + set_icc 0x0b,0 ; Set mask opposite of expected + csubcc gr8,gr8,gr8,cc4,1 + test_icc 0 1 0 0 icc0 + test_gr_immed 0,gr8 + + set_icc 0x06,0 ; Set mask opposite of expected + csubcc gr8,gr7,gr8,cc4,1 + test_icc 1 0 0 1 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + csubcc gr8,gr7,gr8,cc0,0 + test_icc 1 1 1 1 icc0 + test_gr_immed 2,gr8 + + set_gr_immed 1,gr7 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0d,0 ; Set mask opposite of expected + csubcc gr8,gr7,gr8,cc0,0 + test_icc 1 1 0 1 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_icc 0x0b,0 ; Set mask opposite of expected + csubcc gr8,gr8,gr8,cc4,0 + test_icc 1 0 1 1 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_icc 0x06,0 ; Set mask opposite of expected + csubcc gr8,gr7,gr8,cc4,0 + test_icc 0 1 1 0 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + set_icc 0x0f,1 ; Set mask opposite of expected + csubcc gr8,gr7,gr8,cc1,0 + test_icc 0 0 0 0 icc1 + test_gr_immed 1,gr8 + + set_gr_immed 1,gr7 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0d,1 ; Set mask opposite of expected + csubcc gr8,gr7,gr8,cc1,0 + test_icc 0 0 1 0 icc1 + test_gr_limmed 0x7fff,0xffff,gr8 + + set_icc 0x0b,1 ; Set mask opposite of expected + csubcc gr8,gr8,gr8,cc5,0 + test_icc 0 1 0 0 icc1 + test_gr_immed 0,gr8 + + set_icc 0x06,1 ; Set mask opposite of expected + csubcc gr8,gr7,gr8,cc5,0 + test_icc 1 0 0 1 icc1 + test_gr_limmed 0xffff,0xffff,gr8 + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + set_icc 0x0f,1 ; Set mask opposite of expected + csubcc gr8,gr7,gr8,cc1,1 + test_icc 1 1 1 1 icc1 + test_gr_immed 2,gr8 + + set_gr_immed 1,gr7 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0d,1 ; Set mask opposite of expected + csubcc gr8,gr7,gr8,cc1,1 + test_icc 1 1 0 1 icc1 + test_gr_limmed 0x8000,0x0000,gr8 + + set_icc 0x0b,1 ; Set mask opposite of expected + csubcc gr8,gr8,gr8,cc5,1 + test_icc 1 0 1 1 icc1 + test_gr_limmed 0x8000,0x0000,gr8 + + set_icc 0x06,1 ; Set mask opposite of expected + csubcc gr8,gr7,gr8,cc5,1 + test_icc 0 1 1 0 icc1 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + set_icc 0x0f,2 ; Set mask opposite of expected + csubcc gr8,gr7,gr8,cc2,0 + test_icc 1 1 1 1 icc2 + test_gr_immed 2,gr8 + + set_gr_immed 1,gr7 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0d,2 ; Set mask opposite of expected + csubcc gr8,gr7,gr8,cc2,0 + test_icc 1 1 0 1 icc2 + test_gr_limmed 0x8000,0x0000,gr8 + + set_icc 0x0b,2 ; Set mask opposite of expected + csubcc gr8,gr8,gr8,cc6,1 + test_icc 1 0 1 1 icc2 + test_gr_limmed 0x8000,0x0000,gr8 + + set_icc 0x06,2 ; Set mask opposite of expected + csubcc gr8,gr7,gr8,cc6,1 + test_icc 0 1 1 0 icc2 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + set_icc 0x0f,3 ; Set mask opposite of expected + csubcc gr8,gr7,gr8,cc3,0 + test_icc 1 1 1 1 icc3 + test_gr_immed 2,gr8 + + set_gr_immed 1,gr7 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0d,3 ; Set mask opposite of expected + csubcc gr8,gr7,gr8,cc3,0 + test_icc 1 1 0 1 icc3 + test_gr_limmed 0x8000,0x0000,gr8 + + set_icc 0x0b,3 ; Set mask opposite of expected + csubcc gr8,gr8,gr8,cc7,1 + test_icc 1 0 1 1 icc3 + test_gr_limmed 0x8000,0x0000,gr8 + + set_icc 0x06,3 ; Set mask opposite of expected + csubcc gr8,gr7,gr8,cc7,1 + test_icc 0 1 1 0 icc3 + test_gr_limmed 0x8000,0x0000,gr8 + + pass diff --git a/sim/testsuite/sim/frv/cswap.cgs b/sim/testsuite/sim/frv/cswap.cgs new file mode 100644 index 0000000..19a51d5 --- /dev/null +++ b/sim/testsuite/sim/frv/cswap.cgs @@ -0,0 +1,212 @@ +# frv testcase for cswap @($GRi,$GRj),$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cswap +cswap: + set_spr_immed 0x1b1b,cccr + + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_gr_gr sp,gr21 + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_gr_gr sp,gr22 + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed 4,sp + + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_immed -4,gr7 + cswap @(sp,gr7),gr8,cc0,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_mem_limmed 0xbeef,0xdead,gr22 + test_mem_limmed 0xbeef,0xdead,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_immed 0,gr7 + cswap @(sp,gr7),gr8,cc0,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_mem_limmed 0xbeef,0xdead,gr22 + test_mem_limmed 0xdead,0xbeef,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_immed 4,gr7 + cswap @(sp,gr7),gr8,cc4,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_mem_limmed 0xbeef,0xdead,gr22 + test_mem_limmed 0xdead,0xbeef,gr21 + test_mem_limmed 0xbeef,0xdead,gr20 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_gr_gr sp,gr21 + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_gr_gr sp,gr22 + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed 4,sp + + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_immed -4,gr7 + cswap @(sp,gr7),gr8,cc0,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_mem_limmed 0xdead,0xbeef,gr22 + test_mem_limmed 0xbeef,0xdead,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_immed 0,gr7 + cswap @(sp,gr7),gr8,cc0,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_mem_limmed 0xdead,0xbeef,gr22 + test_mem_limmed 0xbeef,0xdead,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_immed 4,gr7 + cswap @(sp,gr7),gr8,cc4,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_mem_limmed 0xdead,0xbeef,gr22 + test_mem_limmed 0xbeef,0xdead,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_gr_gr sp,gr21 + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_gr_gr sp,gr22 + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed 4,sp + + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_immed -4,gr7 + cswap @(sp,gr7),gr8,cc1,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_mem_limmed 0xbeef,0xdead,gr22 + test_mem_limmed 0xbeef,0xdead,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_immed 0,gr7 + cswap @(sp,gr7),gr8,cc1,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_mem_limmed 0xbeef,0xdead,gr22 + test_mem_limmed 0xdead,0xbeef,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_immed 4,gr7 + cswap @(sp,gr7),gr8,cc5,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_mem_limmed 0xbeef,0xdead,gr22 + test_mem_limmed 0xdead,0xbeef,gr21 + test_mem_limmed 0xbeef,0xdead,gr20 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_gr_gr sp,gr21 + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_gr_gr sp,gr22 + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed 4,sp + + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_immed -4,gr7 + cswap @(sp,gr7),gr8,cc1,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_mem_limmed 0xdead,0xbeef,gr22 + test_mem_limmed 0xbeef,0xdead,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_immed 0,gr7 + cswap @(sp,gr7),gr8,cc1,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_mem_limmed 0xdead,0xbeef,gr22 + test_mem_limmed 0xbeef,0xdead,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_immed 4,gr7 + cswap @(sp,gr7),gr8,cc5,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_mem_limmed 0xdead,0xbeef,gr22 + test_mem_limmed 0xbeef,0xdead,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_gr_gr sp,gr21 + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_gr_gr sp,gr22 + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed 4,sp + + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_immed -4,gr7 + cswap @(sp,gr7),gr8,cc2,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_mem_limmed 0xdead,0xbeef,gr22 + test_mem_limmed 0xbeef,0xdead,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_immed 0,gr7 + cswap @(sp,gr7),gr8,cc2,1 + test_gr_limmed 0xdead,0xbeef,gr8 + test_mem_limmed 0xdead,0xbeef,gr22 + test_mem_limmed 0xbeef,0xdead,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_immed 4,gr7 + cswap @(sp,gr7),gr8,cc6,0 + test_gr_limmed 0xbeef,0xdead,gr8 + test_mem_limmed 0xdead,0xbeef,gr22 + test_mem_limmed 0xbeef,0xdead,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_gr gr20,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_gr_gr sp,gr21 + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_gr_gr sp,gr22 + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed 4,sp + + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_immed -4,gr7 + cswap @(sp,gr7),gr8,cc3,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_mem_limmed 0xdead,0xbeef,gr22 + test_mem_limmed 0xbeef,0xdead,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_immed 0,gr7 + cswap @(sp,gr7),gr8,cc3,0 + test_gr_limmed 0xdead,0xbeef,gr8 + test_mem_limmed 0xdead,0xbeef,gr22 + test_mem_limmed 0xbeef,0xdead,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_immed 4,gr7 + cswap @(sp,gr7),gr8,cc7,1 + test_gr_limmed 0xbeef,0xdead,gr8 + test_mem_limmed 0xdead,0xbeef,gr22 + test_mem_limmed 0xbeef,0xdead,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + pass diff --git a/sim/testsuite/sim/frv/cudiv.cgs b/sim/testsuite/sim/frv/cudiv.cgs new file mode 100644 index 0000000..78f44ae --- /dev/null +++ b/sim/testsuite/sim/frv/cudiv.cgs @@ -0,0 +1,96 @@ +# frv testcase for cudiv $GRi,$GRj,$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cudiv +cudiv: + set_spr_immed 0x1b1b,cccr + + ; simple division 12 / 3 + set_gr_immed 0x00000003,gr2 + set_gr_immed 0x0000000c,gr3 + cudiv gr3,gr2,gr3,cc0,1 + test_gr_immed 0x00000003,gr2 + test_gr_immed 0x00000004,gr3 + + ; example 1 from division in the fr30 manual + set_gr_limmed 0x0123,0x4567,gr2 + set_gr_limmed 0xfedc,0xba98,gr3 + cudiv gr3,gr2,gr3,cc4,1 + test_gr_limmed 0x0123,0x4567,gr2 + test_gr_immed 0x000000e0,gr3 + + ; simple division 12 / 3 + set_gr_immed 0x00000003,gr2 + set_gr_immed 0x0000000c,gr3 + cudiv gr3,gr2,gr3,cc0,0 + test_gr_immed 0x00000003,gr2 + test_gr_immed 0x0000000c,gr3 + + ; example 1 from division in the fr30 manual + set_gr_limmed 0x0123,0x4567,gr2 + set_gr_limmed 0xfedc,0xba98,gr3 + cudiv gr3,gr2,gr3,cc4,0 + test_gr_limmed 0x0123,0x4567,gr2 + test_gr_limmed 0xfedc,0xba98,gr3 + + ; simple division 12 / 3 + set_gr_immed 0x00000003,gr2 + set_gr_immed 0x0000000c,gr3 + cudiv gr3,gr2,gr3,cc1,0 + test_gr_immed 0x00000003,gr2 + test_gr_immed 0x00000004,gr3 + + ; example 1 from division in the fr30 manual + set_gr_limmed 0x0123,0x4567,gr2 + set_gr_limmed 0xfedc,0xba98,gr3 + cudiv gr3,gr2,gr3,cc5,0 + test_gr_limmed 0x0123,0x4567,gr2 + test_gr_immed 0x000000e0,gr3 + + ; simple division 12 / 3 + set_gr_immed 0x00000003,gr2 + set_gr_immed 0x0000000c,gr3 + cudiv gr3,gr2,gr3,cc1,1 + test_gr_immed 0x00000003,gr2 + test_gr_immed 0x0000000c,gr3 + + ; example 1 from division in the fr30 manual + set_gr_limmed 0x0123,0x4567,gr2 + set_gr_limmed 0xfedc,0xba98,gr3 + cudiv gr3,gr2,gr3,cc5,1 + test_gr_limmed 0x0123,0x4567,gr2 + test_gr_limmed 0xfedc,0xba98,gr3 + + ; simple division 12 / 3 + set_gr_immed 0x00000003,gr2 + set_gr_immed 0x0000000c,gr3 + cudiv gr3,gr2,gr3,cc2,0 + test_gr_immed 0x00000003,gr2 + test_gr_immed 0x0000000c,gr3 + + ; example 1 from division in the fr30 manual + set_gr_limmed 0x0123,0x4567,gr2 + set_gr_limmed 0xfedc,0xba98,gr3 + cudiv gr3,gr2,gr3,cc6,1 + test_gr_limmed 0x0123,0x4567,gr2 + test_gr_limmed 0xfedc,0xba98,gr3 + + ; simple division 12 / 3 + set_gr_immed 0x00000003,gr2 + set_gr_immed 0x0000000c,gr3 + cudiv gr3,gr2,gr3,cc3,0 + test_gr_immed 0x00000003,gr2 + test_gr_immed 0x0000000c,gr3 + + ; example 1 from division in the fr30 manual + set_gr_limmed 0x0123,0x4567,gr2 + set_gr_limmed 0xfedc,0xba98,gr3 + cudiv gr3,gr2,gr3,cc7,1 + test_gr_limmed 0x0123,0x4567,gr2 + test_gr_limmed 0xfedc,0xba98,gr3 + + pass diff --git a/sim/testsuite/sim/frv/cxor.cgs b/sim/testsuite/sim/frv/cxor.cgs new file mode 100644 index 0000000..54a672d --- /dev/null +++ b/sim/testsuite/sim/frv/cxor.cgs @@ -0,0 +1,180 @@ +# frv testcase for cxor $GRi,$GRj,$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cxor +cxor: + set_spr_immed 0x1b1b,cccr + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x07,0 ; Set mask opposite of expected + cxor gr7,gr8,gr8,cc0,1 + test_icc 0 1 1 1 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + + set_gr_immed 0x00000000,gr7 + set_gr_immed 0x00000000,gr8 + set_icc 0x08,0 ; Set mask opposite of expected + cxor gr7,gr8,gr8,cc0,1 + test_icc 1 0 0 0 icc0 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_icc 0x0b,0 ; Set mask opposite of expected + cxor gr7,gr8,gr8,cc4,1 + test_icc 1 0 1 1 icc0 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0x0000,gr7 + set_gr_limmed 0x0000,0xbeef,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + cxor gr7,gr8,gr8,cc4,1 + test_icc 0 1 0 1 icc0 + test_gr_limmed 0xdead,0xbeef,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x07,0 ; Set mask opposite of expected + cxor gr7,gr8,gr8,cc0,0 + test_icc 0 1 1 1 icc0 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_immed 0x00007fff,gr7 + set_gr_immed 0x00000000,gr8 + set_icc 0x08,0 ; Set mask opposite of expected + cxor gr7,gr8,gr8,cc0,0 + test_icc 1 0 0 0 icc0 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_icc 0x0b,0 ; Set mask opposite of expected + cxor gr7,gr8,gr8,cc4,0 + test_icc 1 0 1 1 icc0 + test_gr_limmed 0xaaaa,0xaaaa,gr8 + + set_gr_limmed 0xdead,0x0000,gr7 + set_gr_limmed 0x0000,0xbeef,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + cxor gr7,gr8,gr8,cc4,0 + test_icc 0 1 0 1 icc0 + test_gr_limmed 0x0000,0xbeef,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x07,1 ; Set mask opposite of expected + cxor gr7,gr8,gr8,cc1,0 + test_icc 0 1 1 1 icc1 + test_gr_limmed 0xffff,0xffff,gr8 + + set_gr_immed 0x00000000,gr7 + set_gr_immed 0x00000000,gr8 + set_icc 0x08,1 ; Set mask opposite of expected + cxor gr7,gr8,gr8,cc1,0 + test_icc 1 0 0 0 icc1 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_icc 0x0b,1 ; Set mask opposite of expected + cxor gr7,gr8,gr8,cc5,0 + test_icc 1 0 1 1 icc1 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0x0000,gr7 + set_gr_limmed 0x0000,0xbeef,gr8 + set_icc 0x05,1 ; Set mask opposite of expected + cxor gr7,gr8,gr8,cc5,0 + test_icc 0 1 0 1 icc1 + test_gr_limmed 0xdead,0xbeef,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x07,1 ; Set mask opposite of expected + cxor gr7,gr8,gr8,cc1,1 + test_icc 0 1 1 1 icc1 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_immed 0x00007fff,gr7 + set_gr_immed 0x00000000,gr8 + set_icc 0x08,1 ; Set mask opposite of expected + cxor gr7,gr8,gr8,cc1,1 + test_icc 1 0 0 0 icc1 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_icc 0x0b,1 ; Set mask opposite of expected + cxor gr7,gr8,gr8,cc5,1 + test_icc 1 0 1 1 icc1 + test_gr_limmed 0xaaaa,0xaaaa,gr8 + + set_gr_limmed 0xdead,0x0000,gr7 + set_gr_limmed 0x0000,0xbeef,gr8 + set_icc 0x05,1 ; Set mask opposite of expected + cxor gr7,gr8,gr8,cc5,1 + test_icc 0 1 0 1 icc1 + test_gr_limmed 0x0000,0xbeef,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x07,2 ; Set mask opposite of expected + cxor gr7,gr8,gr8,cc2,0 + test_icc 0 1 1 1 icc2 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_immed 0x00007fff,gr7 + set_gr_immed 0x00000000,gr8 + set_icc 0x08,2 ; Set mask opposite of expected + cxor gr7,gr8,gr8,cc2,0 + test_icc 1 0 0 0 icc2 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_icc 0x0b,2 ; Set mask opposite of expected + cxor gr7,gr8,gr8,cc6,1 + test_icc 1 0 1 1 icc2 + test_gr_limmed 0xaaaa,0xaaaa,gr8 + + set_gr_limmed 0xdead,0x0000,gr7 + set_gr_limmed 0x0000,0xbeef,gr8 + set_icc 0x05,2 ; Set mask opposite of expected + cxor gr7,gr8,gr8,cc6,1 + test_icc 0 1 0 1 icc2 + test_gr_limmed 0x0000,0xbeef,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x07,3 ; Set mask opposite of expected + cxor gr7,gr8,gr8,cc3,0 + test_icc 0 1 1 1 icc3 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_immed 0x00007fff,gr7 + set_gr_immed 0x00000000,gr8 + set_icc 0x08,3 ; Set mask opposite of expected + cxor gr7,gr8,gr8,cc3,0 + test_icc 1 0 0 0 icc3 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_icc 0x0b,3 ; Set mask opposite of expected + cxor gr7,gr8,gr8,cc7,1 + test_icc 1 0 1 1 icc3 + test_gr_limmed 0xaaaa,0xaaaa,gr8 + + set_gr_limmed 0xdead,0x0000,gr7 + set_gr_limmed 0x0000,0xbeef,gr8 + set_icc 0x05,3 ; Set mask opposite of expected + cxor gr7,gr8,gr8,cc7,1 + test_icc 0 1 0 1 icc3 + test_gr_limmed 0x0000,0xbeef,gr8 + + pass diff --git a/sim/testsuite/sim/frv/cxorcc.cgs b/sim/testsuite/sim/frv/cxorcc.cgs new file mode 100644 index 0000000..86d917d --- /dev/null +++ b/sim/testsuite/sim/frv/cxorcc.cgs @@ -0,0 +1,180 @@ +# frv testcase for cxorcc $GRi,$GRj,$GRk,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cxorcc +cxorcc: + set_spr_immed 0x1b1b,cccr + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x07,0 ; Set mask opposite of expected + cxorcc gr7,gr8,gr8,cc0,1 + test_icc 1 0 1 1 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + + set_gr_immed 0x00000000,gr7 + set_gr_immed 0x00000000,gr8 + set_icc 0x08,0 ; Set mask opposite of expected + cxorcc gr7,gr8,gr8,cc0,1 + test_icc 0 1 0 0 icc0 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_icc 0x0b,0 ; Set mask opposite of expected + cxorcc gr7,gr8,gr8,cc4,1 + test_icc 0 1 1 1 icc0 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0x0000,gr7 + set_gr_limmed 0x0000,0xbeef,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + cxorcc gr7,gr8,gr8,cc4,1 + test_icc 1 0 0 1 icc0 + test_gr_limmed 0xdead,0xbeef,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x07,0 ; Set mask opposite of expected + cxorcc gr7,gr8,gr8,cc0,0 + test_icc 0 1 1 1 icc0 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_immed 0x00007fff,gr7 + set_gr_immed 0x00000000,gr8 + set_icc 0x08,0 ; Set mask opposite of expected + cxorcc gr7,gr8,gr8,cc0,0 + test_icc 1 0 0 0 icc0 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_icc 0x0b,0 ; Set mask opposite of expected + cxorcc gr7,gr8,gr8,cc4,0 + test_icc 1 0 1 1 icc0 + test_gr_limmed 0xaaaa,0xaaaa,gr8 + + set_gr_limmed 0xdead,0x0000,gr7 + set_gr_limmed 0x0000,0xbeef,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + cxorcc gr7,gr8,gr8,cc4,0 + test_icc 0 1 0 1 icc0 + test_gr_limmed 0x0000,0xbeef,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x07,1 ; Set mask opposite of expected + cxorcc gr7,gr8,gr8,cc1,0 + test_icc 1 0 1 1 icc1 + test_gr_limmed 0xffff,0xffff,gr8 + + set_gr_immed 0x00000000,gr7 + set_gr_immed 0x00000000,gr8 + set_icc 0x08,1 ; Set mask opposite of expected + cxorcc gr7,gr8,gr8,cc1,0 + test_icc 0 1 0 0 icc1 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_icc 0x0b,1 ; Set mask opposite of expected + cxorcc gr7,gr8,gr8,cc5,0 + test_icc 0 1 1 1 icc1 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0x0000,gr7 + set_gr_limmed 0x0000,0xbeef,gr8 + set_icc 0x05,1 ; Set mask opposite of expected + cxorcc gr7,gr8,gr8,cc5,0 + test_icc 1 0 0 1 icc1 + test_gr_limmed 0xdead,0xbeef,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x07,1 ; Set mask opposite of expected + cxorcc gr7,gr8,gr8,cc1,1 + test_icc 0 1 1 1 icc1 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_immed 0x00007fff,gr7 + set_gr_immed 0x00000000,gr8 + set_icc 0x08,1 ; Set mask opposite of expected + cxorcc gr7,gr8,gr8,cc1,1 + test_icc 1 0 0 0 icc1 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_icc 0x0b,1 ; Set mask opposite of expected + cxorcc gr7,gr8,gr8,cc5,1 + test_icc 1 0 1 1 icc1 + test_gr_limmed 0xaaaa,0xaaaa,gr8 + + set_gr_limmed 0xdead,0x0000,gr7 + set_gr_limmed 0x0000,0xbeef,gr8 + set_icc 0x05,1 ; Set mask opposite of expected + cxorcc gr7,gr8,gr8,cc5,1 + test_icc 0 1 0 1 icc1 + test_gr_limmed 0x0000,0xbeef,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x07,2 ; Set mask opposite of expected + cxorcc gr7,gr8,gr8,cc2,0 + test_icc 0 1 1 1 icc2 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_immed 0x00007fff,gr7 + set_gr_immed 0x00000000,gr8 + set_icc 0x08,2 ; Set mask opposite of expected + cxorcc gr7,gr8,gr8,cc2,0 + test_icc 1 0 0 0 icc2 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_icc 0x0b,2 ; Set mask opposite of expected + cxorcc gr7,gr8,gr8,cc6,1 + test_icc 1 0 1 1 icc2 + test_gr_limmed 0xaaaa,0xaaaa,gr8 + + set_gr_limmed 0xdead,0x0000,gr7 + set_gr_limmed 0x0000,0xbeef,gr8 + set_icc 0x05,2 ; Set mask opposite of expected + cxorcc gr7,gr8,gr8,cc6,1 + test_icc 0 1 0 1 icc2 + test_gr_limmed 0x0000,0xbeef,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x07,3 ; Set mask opposite of expected + cxorcc gr7,gr8,gr8,cc3,0 + test_icc 0 1 1 1 icc3 + test_gr_limmed 0x5555,0x5555,gr8 + + set_gr_immed 0x00007fff,gr7 + set_gr_immed 0x00000000,gr8 + set_icc 0x08,3 ; Set mask opposite of expected + cxorcc gr7,gr8,gr8,cc3,0 + test_icc 1 0 0 0 icc3 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_icc 0x0b,3 ; Set mask opposite of expected + cxorcc gr7,gr8,gr8,cc7,1 + test_icc 1 0 1 1 icc3 + test_gr_limmed 0xaaaa,0xaaaa,gr8 + + set_gr_limmed 0xdead,0x0000,gr7 + set_gr_limmed 0x0000,0xbeef,gr8 + set_icc 0x05,3 ; Set mask opposite of expected + cxorcc gr7,gr8,gr8,cc7,1 + test_icc 0 1 0 1 icc3 + test_gr_limmed 0x0000,0xbeef,gr8 + + pass diff --git a/sim/testsuite/sim/frv/dcef.cgs b/sim/testsuite/sim/frv/dcef.cgs new file mode 100644 index 0000000..74475ef --- /dev/null +++ b/sim/testsuite/sim/frv/dcef.cgs @@ -0,0 +1,50 @@ +# frv testcase for dcef @(GRi,GRj),a +# mach: fr400 fr550 + + .include "testutils.inc" + + start + + .global dcef +dcef: + and_spr_immed 0x7fffffff,hsr0 ; data cache only: copy-back mode + set_gr_addr doit,gr10 + set_gr_immed 0,gr11 + set_gr_immed 1,gr12 + set_gr_immed 2,gr13 + set_gr_immed 3,gr14 + + set_spr_addr ok1,lr + bra doit +ok1: test_gr_immed 1,gr11 + + set_mem_immed 0x9600b00d,gr10 ; change to add gr11,gr13,gr11 in cache + set_spr_addr ok2,lr + bra doit +ok2: test_gr_immed 2,gr11 ; still only added 1 + + set_gr_addr doit1,gr10 + set_mem_immed 0x9600b00d,gr10 ; change to add gr11,gr13,gr11 in cache + dcef @(gr10,gr0),1 ; flush data cache + set_spr_addr ok3,lr + bra doit1 +ok3: test_gr_immed 4,gr11 ; added 2 this time + + set_gr_addr doit2,gr10 + set_mem_immed 0x9600b00e,gr10 ; change to add gr11,gr14,gr11 in cache + dcef @(gr0,gr0),1 ; flush data cache + set_spr_addr ok4,lr + bra doit2 +ok4: test_gr_immed 7,gr11 ; added 3 this time + + pass + +doit: add gr11,gr12,gr11 + bralr + +doit1: add gr11,gr12,gr11 + bralr + +doit2: add gr11,gr12,gr11 + bralr + diff --git a/sim/testsuite/sim/frv/dcei.cgs b/sim/testsuite/sim/frv/dcei.cgs new file mode 100644 index 0000000..6254c06 --- /dev/null +++ b/sim/testsuite/sim/frv/dcei.cgs @@ -0,0 +1,27 @@ +# frv testcase for dcei @(GRi,GRj),a +# mach: fr400 fr550 + + .include "testutils.inc" + + start + + .global dcei +dcei: + or_spr_immed 0x08000000,hsr0 ; data cache: copy-back mode + + set_mem_immed 0xdeadbeef,sp + test_mem_immed 0xdeadbeef,sp + + flush_data_cache sp + set_mem_immed 0xbeefdead,sp + test_mem_immed 0xbeefdead,sp + + dcei @(sp,gr0),1 + test_mem_immed 0xdeadbeef,sp + + set_mem_immed 0xbeefdead,sp + test_mem_immed 0xbeefdead,sp + dcei @(gr0,gr0),1 + test_mem_immed 0xdeadbeef,sp + + pass diff --git a/sim/testsuite/sim/frv/dcf.cgs b/sim/testsuite/sim/frv/dcf.cgs new file mode 100644 index 0000000..f6e670e --- /dev/null +++ b/sim/testsuite/sim/frv/dcf.cgs @@ -0,0 +1,39 @@ +# FRV testcase for dcf @(GRi,GRj) +# mach: all + + .include "testutils.inc" + + start + + .global dcf +dcf: + and_spr_immed 0x7fffffff,hsr0 ; data cache only: copy-back mode + set_gr_addr doit,gr10 + set_gr_immed 0,gr11 + set_gr_immed 1,gr12 + set_gr_immed 2,gr13 + + set_spr_addr ok1,lr + bra doit +ok1: test_gr_immed 1,gr11 + + set_mem_immed 0x9600b00d,gr10 ; change to add gr11,gr13,gr11 in cache + set_spr_addr ok2,lr + bra doit +ok2: test_gr_immed 2,gr11 ; still only added 1 + + set_gr_addr doit1,gr10 + set_mem_immed 0x9600b00d,gr10 ; change to add gr11,gr13,gr11 in cache + dcf @(gr10,gr0) ; flush data cache + set_spr_addr ok3,lr + bra doit1 +ok3: test_gr_immed 4,gr11 ; added 2 this time + + pass + +doit: add gr11,gr12,gr11 + bralr + +doit1: add gr11,gr12,gr11 + bralr + diff --git a/sim/testsuite/sim/frv/dci.cgs b/sim/testsuite/sim/frv/dci.cgs new file mode 100644 index 0000000..de481c3 --- /dev/null +++ b/sim/testsuite/sim/frv/dci.cgs @@ -0,0 +1,22 @@ +# FRV testcase for dci @(GRi,GRj) +# mach: all + + .include "testutils.inc" + + start + + .global dci +dci: + or_spr_immed 0x08000000,hsr0 ; data cache: copy-back mode + + set_mem_immed 0xdeadbeef,sp + test_mem_immed 0xdeadbeef,sp + + flush_data_cache sp + set_mem_immed 0xbeefdead,sp + test_mem_immed 0xbeefdead,sp + + dci @(sp,gr0) + test_mem_immed 0xdeadbeef,sp + + pass diff --git a/sim/testsuite/sim/frv/fabsd.cgs b/sim/testsuite/sim/frv/fabsd.cgs new file mode 100644 index 0000000..41a485e --- /dev/null +++ b/sim/testsuite/sim/frv/fabsd.cgs @@ -0,0 +1,26 @@ +# frv testcase for fabsd $FRj,$FRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + double_constants + start + load_double_constants + + .global fabsd +fabsd: + fabsd fr0,fr2 + test_dfr_dfr fr2,fr52 + fabsd fr8,fr2 + test_dfr_dfr fr2,fr28 + fabsd fr12,fr2 + test_dfr_dfr fr2,fr24 + fabsd fr24,fr2 + test_dfr_dfr fr2,fr24 + fabsd fr28,fr2 + test_dfr_dfr fr2,fr28 + fabsd fr52,fr2 + test_dfr_dfr fr2,fr52 + + pass diff --git a/sim/testsuite/sim/frv/fabss.cgs b/sim/testsuite/sim/frv/fabss.cgs new file mode 100644 index 0000000..f48514a --- /dev/null +++ b/sim/testsuite/sim/frv/fabss.cgs @@ -0,0 +1,25 @@ +# frv testcase for fabss $FRj,$FRk +# mach: fr500 fr550 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global fabss +fabss: + fabss fr0,fr1 + test_fr_fr fr1,fr52 + fabss fr8,fr1 + test_fr_fr fr1,fr28 + fabss fr12,fr1 + test_fr_fr fr1,fr24 + fabss fr24,fr1 + test_fr_fr fr1,fr24 + fabss fr28,fr1 + test_fr_fr fr1,fr28 + fabss fr52,fr1 + test_fr_fr fr1,fr52 + + pass diff --git a/sim/testsuite/sim/frv/faddd.cgs b/sim/testsuite/sim/frv/faddd.cgs new file mode 100644 index 0000000..dbb6373 --- /dev/null +++ b/sim/testsuite/sim/frv/faddd.cgs @@ -0,0 +1,93 @@ +# frv testcase for faddd $GRi,$GRj,$GRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + double_constants + start + load_double_constants + + .global faddd +faddd: + faddd fr16,fr0,fr2 + test_dfr_dfr fr2,fr0 + faddd fr16,fr4,fr2 + test_dfr_dfr fr2,fr4 + faddd fr16,fr8,fr2 + test_dfr_dfr fr2,fr8 + faddd fr16,fr12,fr2 + test_dfr_dfr fr2,fr12 + faddd fr16,fr16,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + faddd fr16,fr20,fr2 + test_dfr_dfr fr2,fr26 + test_dfr_dfr fr2,fr20 + faddd fr16,fr24,fr2 + test_dfr_dfr fr2,fr24 + faddd fr16,fr28,fr2 + test_dfr_dfr fr2,fr28 + faddd fr16,fr32,fr2 + test_dfr_dfr fr2,fr32 + faddd fr16,fr36,fr2 + test_dfr_dfr fr2,fr36 + faddd fr16,fr40,fr2 + test_dfr_dfr fr2,fr40 + faddd fr16,fr44,fr2 + test_dfr_dfr fr2,fr44 + faddd fr16,fr48,fr2 + test_dfr_dfr fr2,fr48 + faddd fr16,fr52,fr2 + test_dfr_dfr fr2,fr52 + + faddd fr20,fr0,fr2 + test_dfr_dfr fr2,fr0 + faddd fr20,fr4,fr2 + test_dfr_dfr fr2,fr4 + faddd fr20,fr8,fr2 + test_dfr_dfr fr2,fr8 + faddd fr20,fr12,fr2 + test_dfr_dfr fr2,fr12 + faddd fr20,fr16,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + faddd fr20,fr20,fr2 + test_dfr_dfr fr2,fr26 + test_dfr_dfr fr2,fr20 + faddd fr20,fr24,fr2 + test_dfr_dfr fr2,fr24 + faddd fr20,fr28,fr2 + test_dfr_dfr fr2,fr28 + faddd fr20,fr32,fr2 + test_dfr_dfr fr2,fr32 + faddd fr20,fr36,fr2 + test_dfr_dfr fr2,fr36 + faddd fr20,fr40,fr2 + test_dfr_dfr fr2,fr40 + faddd fr20,fr44,fr2 + test_dfr_dfr fr2,fr44 + faddd fr20,fr48,fr2 + test_dfr_dfr fr2,fr48 + faddd fr20,fr52,fr2 + test_dfr_dfr fr2,fr52 + + faddd fr8,fr28,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + faddd fr12,fr24,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + faddd fr24,fr12,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + faddd fr28,fr8,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + + faddd fr36,fr40,fr2 + test_dfr_dfr fr2,fr44 + + pass + + diff --git a/sim/testsuite/sim/frv/fadds.cgs b/sim/testsuite/sim/frv/fadds.cgs new file mode 100644 index 0000000..d741ac9 --- /dev/null +++ b/sim/testsuite/sim/frv/fadds.cgs @@ -0,0 +1,92 @@ +# frv testcase for fadds $GRi,$GRj,$GRk +# mach: fr500 fr550 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global fadds +fadds: + fadds fr16,fr0,fr1 + test_fr_fr fr1,fr0 + fadds fr16,fr4,fr1 + test_fr_fr fr1,fr4 + fadds fr16,fr8,fr1 + test_fr_fr fr1,fr8 + fadds fr16,fr12,fr1 + test_fr_fr fr1,fr12 + fadds fr16,fr16,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fadds fr16,fr20,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fadds fr16,fr24,fr1 + test_fr_fr fr1,fr24 + fadds fr16,fr28,fr1 + test_fr_fr fr1,fr28 + fadds fr16,fr32,fr1 + test_fr_fr fr1,fr32 + fadds fr16,fr36,fr1 + test_fr_fr fr1,fr36 + fadds fr16,fr40,fr1 + test_fr_fr fr1,fr40 + fadds fr16,fr44,fr1 + test_fr_fr fr1,fr44 + fadds fr16,fr48,fr1 + test_fr_fr fr1,fr48 + fadds fr16,fr52,fr1 + test_fr_fr fr1,fr52 + + fadds fr20,fr0,fr1 + test_fr_fr fr1,fr0 + fadds fr20,fr4,fr1 + test_fr_fr fr1,fr4 + fadds fr20,fr8,fr1 + test_fr_fr fr1,fr8 + fadds fr20,fr12,fr1 + test_fr_fr fr1,fr12 + fadds fr20,fr16,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fadds fr20,fr20,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fadds fr20,fr24,fr1 + test_fr_fr fr1,fr24 + fadds fr20,fr28,fr1 + test_fr_fr fr1,fr28 + fadds fr20,fr32,fr1 + test_fr_fr fr1,fr32 + fadds fr20,fr36,fr1 + test_fr_fr fr1,fr36 + fadds fr20,fr40,fr1 + test_fr_fr fr1,fr40 + fadds fr20,fr44,fr1 + test_fr_fr fr1,fr44 + fadds fr20,fr48,fr1 + test_fr_fr fr1,fr48 + fadds fr20,fr52,fr1 + test_fr_fr fr1,fr52 + + fadds fr8,fr28,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fadds fr12,fr24,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fadds fr24,fr12,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fadds fr28,fr8,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + + fadds fr36,fr40,fr1 + test_fr_fr fr1,fr44 + + pass + + diff --git a/sim/testsuite/sim/frv/fbeq.cgs b/sim/testsuite/sim/frv/fbeq.cgs new file mode 100644 index 0000000..e51b2c9 --- /dev/null +++ b/sim/testsuite/sim/frv/fbeq.cgs @@ -0,0 +1,61 @@ +# frv testcase for fbeq $FCCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global fbeq +fbeq: + set_fcc 0x0 0 + fbeq fcc0,0,bad + set_fcc 0x1 1 + fbeq fcc1,1,bad + set_fcc 0x2 2 + fbeq fcc2,2,bad + set_fcc 0x3 3 + fbeq fcc3,3,bad + set_fcc 0x4 0 + fbeq fcc0,0,bad + set_fcc 0x5 1 + fbeq fcc1,1,bad + set_fcc 0x6 2 + fbeq fcc2,2,bad + set_fcc 0x7 3 + fbeq fcc3,3,bad + set_fcc 0x8 0 + fbeq fcc0,0,ok9 + fail +ok9: + set_fcc 0x9 1 + fbeq fcc1,1,oka + fail +oka: + set_fcc 0xa 2 + fbeq fcc2,2,okb + fail +okb: + set_fcc 0xb 3 + fbeq fcc3,3,okc + fail +okc: + set_fcc 0xc 0 + fbeq fcc0,0,okd + fail +okd: + set_fcc 0xd 1 + fbeq fcc1,1,oke + fail +oke: + set_fcc 0xe 2 + fbeq fcc2,2,okf + fail +okf: + set_fcc 0xf 3 + fbeq fcc3,3,okg + fail +okg: + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/fbeqlr.cgs b/sim/testsuite/sim/frv/fbeqlr.cgs new file mode 100644 index 0000000..af29cb9 --- /dev/null +++ b/sim/testsuite/sim/frv/fbeqlr.cgs @@ -0,0 +1,84 @@ +# frv testcase for fbeqlr $FCCi,$hint +# mach: all + + .include "testutils.inc" + + start + + .global fbeqlr +fbeqlr: + set_spr_addr bad,lr + set_fcc 0x0 0 + fbeqlr fcc0,0 + + set_spr_addr bad,lr + set_fcc 0x1 1 + fbeqlr fcc1,1 + + set_spr_addr bad,lr + set_fcc 0x2 2 + fbeqlr fcc2,2 + + set_spr_addr bad,lr + set_fcc 0x3 3 + fbeqlr fcc3,3 + + set_spr_addr bad,lr + set_fcc 0x4 0 + fbeqlr fcc0,0 + + set_spr_addr bad,lr + set_fcc 0x5 1 + fbeqlr fcc1,1 + + set_spr_addr bad,lr + set_fcc 0x6 2 + fbeqlr fcc2,2 + + set_spr_addr bad,lr + set_fcc 0x7 3 + fbeqlr fcc3,3 + + set_spr_addr ok9,lr + set_fcc 0x8 0 + fbeqlr fcc0,0 + fail +ok9: + set_spr_addr oka,lr + set_fcc 0x9 1 + fbeqlr fcc1,1 + fail +oka: + set_spr_addr okb,lr + set_fcc 0xa 2 + fbeqlr fcc2,2 + fail +okb: + set_spr_addr okc,lr + set_fcc 0xb 3 + fbeqlr fcc3,3 + fail +okc: + set_spr_addr okd,lr + set_fcc 0xc 0 + fbeqlr fcc0,0 + fail +okd: + set_spr_addr oke,lr + set_fcc 0xd 1 + fbeqlr fcc1,1 + fail +oke: + set_spr_addr okf,lr + set_fcc 0xe 2 + fbeqlr fcc2,2 + fail +okf: + set_spr_addr okg,lr + set_fcc 0xf 3 + fbeqlr fcc3,3 + fail +okg: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/fbge.cgs b/sim/testsuite/sim/frv/fbge.cgs new file mode 100644 index 0000000..a20029e --- /dev/null +++ b/sim/testsuite/sim/frv/fbge.cgs @@ -0,0 +1,69 @@ +# frv testcase for fbge $FCCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global fbge +fbge: + set_fcc 0x0 0 + fbge fcc0,0,bad + set_fcc 0x1 1 + fbge fcc1,1,bad + set_fcc 0x2 2 + fbge fcc2,2,ok3 + fail +ok3: + set_fcc 0x3 3 + fbge fcc3,3,ok4 + fail +ok4: + set_fcc 0x4 0 + fbge fcc0,0,bad + set_fcc 0x5 1 + fbge fcc1,1,bad + set_fcc 0x6 2 + fbge fcc2,2,ok7 + fail +ok7: + set_fcc 0x7 3 + fbge fcc3,3,ok8 + fail +ok8: + set_fcc 0x8 0 + fbge fcc0,0,ok9 + fail +ok9: + set_fcc 0x9 1 + fbge fcc1,1,oka + fail +oka: + set_fcc 0xa 2 + fbge fcc2,2,okb + fail +okb: + set_fcc 0xb 3 + fbge fcc3,3,okc + fail +okc: + set_fcc 0xc 0 + fbge fcc0,0,okd + fail +okd: + set_fcc 0xd 1 + fbge fcc1,1,oke + fail +oke: + set_fcc 0xe 2 + fbge fcc2,2,okf + fail +okf: + set_fcc 0xf 3 + fbge fcc3,3,okg + fail +okg: + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/fbgelr.cgs b/sim/testsuite/sim/frv/fbgelr.cgs new file mode 100644 index 0000000..59e9410 --- /dev/null +++ b/sim/testsuite/sim/frv/fbgelr.cgs @@ -0,0 +1,88 @@ +# frv testcase for fbgelr $FCCi,$hint +# mach: all + + .include "testutils.inc" + + start + + .global fbgelr +fbgelr: + set_spr_addr bad,lr + set_fcc 0x0 0 + fbgelr fcc0,0 + + set_spr_addr bad,lr + set_fcc 0x1 1 + fbgelr fcc1,1 + + set_spr_addr ok3,lr + set_fcc 0x2 2 + fbgelr fcc2,2 + fail +ok3: + set_spr_addr ok4,lr + set_fcc 0x3 3 + fbgelr fcc3,3 + fail +ok4: + set_spr_addr bad,lr + set_fcc 0x4 0 + fbgelr fcc0,0 + + set_spr_addr bad,lr + set_fcc 0x5 1 + fbgelr fcc1,1 + + set_spr_addr ok7,lr + set_fcc 0x6 2 + fbgelr fcc2,2 + fail +ok7: + set_spr_addr ok8,lr + set_fcc 0x7 3 + fbgelr fcc3,3 + fail +ok8: + set_spr_addr ok9,lr + set_fcc 0x8 0 + fbgelr fcc0,0 + fail +ok9: + set_spr_addr oka,lr + set_fcc 0x9 1 + fbgelr fcc1,1 + fail +oka: + set_spr_addr okb,lr + set_fcc 0xa 2 + fbgelr fcc2,2 + fail +okb: + set_spr_addr okc,lr + set_fcc 0xb 3 + fbgelr fcc3,3 + fail +okc: + set_spr_addr okd,lr + set_fcc 0xc 0 + fbgelr fcc0,0 + fail +okd: + set_spr_addr oke,lr + set_fcc 0xd 1 + fbgelr fcc1,1 + fail +oke: + set_spr_addr okf,lr + set_fcc 0xe 2 + fbgelr fcc2,2 + fail +okf: + set_spr_addr okg,lr + set_fcc 0xf 3 + fbgelr fcc3,3 + fail +okg: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/fbgt.cgs b/sim/testsuite/sim/frv/fbgt.cgs new file mode 100644 index 0000000..7cc4ea7 --- /dev/null +++ b/sim/testsuite/sim/frv/fbgt.cgs @@ -0,0 +1,61 @@ +# frv testcase for fbgt $FCCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global fbgt +fbgt: + set_fcc 0x0 0 + fbgt fcc0,0,bad + set_fcc 0x1 1 + fbgt fcc1,1,bad + set_fcc 0x2 2 + fbgt fcc2,2,ok3 + fail +ok3: + set_fcc 0x3 3 + fbgt fcc3,3,ok4 + fail +ok4: + set_fcc 0x4 0 + fbgt fcc0,0,bad + set_fcc 0x5 1 + fbgt fcc1,1,bad + set_fcc 0x6 2 + fbgt fcc2,2,ok7 + fail +ok7: + set_fcc 0x7 3 + fbgt fcc3,3,ok8 + fail +ok8: + set_fcc 0x8 0 + fbgt fcc0,0,bad + set_fcc 0x9 1 + fbgt fcc1,1,bad + set_fcc 0xa 2 + fbgt fcc2,2,okb + fail +okb: + set_fcc 0xb 3 + fbgt fcc3,3,okc + fail +okc: + set_fcc 0xc 0 + fbgt fcc0,0,bad + set_fcc 0xd 1 + fbgt fcc1,1,bad + set_fcc 0xe 2 + fbgt fcc2,2,okf + fail +okf: + set_fcc 0xf 3 + fbgt fcc3,3,okg + fail +okg: + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/fbgtlr.cgs b/sim/testsuite/sim/frv/fbgtlr.cgs new file mode 100644 index 0000000..7e4a7a5 --- /dev/null +++ b/sim/testsuite/sim/frv/fbgtlr.cgs @@ -0,0 +1,84 @@ +# frv testcase for fbgtlr $FCCi,$hint +# mach: all + + .include "testutils.inc" + + start + + .global fbgtlr +fbgtlr: + set_spr_addr bad,lr + set_fcc 0x0 0 + fbgtlr fcc0,0 + + set_spr_addr bad,lr + set_fcc 0x1 1 + fbgtlr fcc1,1 + + set_spr_addr ok3,lr + set_fcc 0x2 2 + fbgtlr fcc2,2 + fail +ok3: + set_spr_addr ok4,lr + set_fcc 0x3 3 + fbgtlr fcc3,3 + fail +ok4: + set_spr_addr bad,lr + set_fcc 0x4 0 + fbgtlr fcc0,0 + + set_spr_addr bad,lr + set_fcc 0x5 1 + fbgtlr fcc1,1 + + set_spr_addr ok7,lr + set_fcc 0x6 2 + fbgtlr fcc2,2 + fail +ok7: + set_spr_addr ok8,lr + set_fcc 0x7 3 + fbgtlr fcc3,3 + fail +ok8: + set_spr_addr bad,lr + set_fcc 0x8 0 + fbgtlr fcc0,0 + + set_spr_addr bad,lr + set_fcc 0x9 1 + fbgtlr fcc1,1 + + set_spr_addr okb,lr + set_fcc 0xa 2 + fbgtlr fcc2,2 + fail +okb: + set_spr_addr okc,lr + set_fcc 0xb 3 + fbgtlr fcc3,3 + fail +okc: + set_spr_addr bad,lr + set_fcc 0xc 0 + fbgtlr fcc0,0 + + set_spr_addr bad,lr + set_fcc 0xd 1 + fbgtlr fcc1,1 + + set_spr_addr okf,lr + set_fcc 0xe 2 + fbgtlr fcc2,2 + fail +okf: + set_spr_addr okg,lr + set_fcc 0xf 3 + fbgtlr fcc3,3 + fail +okg: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/fble.cgs b/sim/testsuite/sim/frv/fble.cgs new file mode 100644 index 0000000..e52936a --- /dev/null +++ b/sim/testsuite/sim/frv/fble.cgs @@ -0,0 +1,69 @@ +# frv testcase for fble $FCCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global fble +fble: + set_fcc 0x0 0 + fble fcc0,0,bad + set_fcc 0x1 1 + fble fcc1,1,bad + set_fcc 0x2 2 + fble fcc2,2,bad + set_fcc 0x3 3 + fble fcc3,3,bad + set_fcc 0x4 0 + fble fcc0,0,ok5 + fail +ok5: + set_fcc 0x5 1 + fble fcc1,1,ok6 + fail +ok6: + set_fcc 0x6 2 + fble fcc2,2,ok7 + fail +ok7: + set_fcc 0x7 3 + fble fcc3,3,ok8 + fail +ok8: + set_fcc 0x8 0 + fble fcc0,0,ok9 + fail +ok9: + set_fcc 0x9 1 + fble fcc1,1,oka + fail +oka: + set_fcc 0xa 2 + fble fcc2,2,okb + fail +okb: + set_fcc 0xb 3 + fble fcc3,3,okc + fail +okc: + set_fcc 0xc 0 + fble fcc0,0,okd + fail +okd: + set_fcc 0xd 1 + fble fcc1,1,oke + fail +oke: + set_fcc 0xe 2 + fble fcc2,2,okf + fail +okf: + set_fcc 0xf 3 + fble fcc3,3,okg + fail +okg: + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/fblelr.cgs b/sim/testsuite/sim/frv/fblelr.cgs new file mode 100644 index 0000000..92a47bc --- /dev/null +++ b/sim/testsuite/sim/frv/fblelr.cgs @@ -0,0 +1,89 @@ +# frv testcase for fblelr $FCCi,$hint +# mach: all + + .include "testutils.inc" + + start + + .global fblelr +fblelr: + set_spr_addr bad,lr + set_fcc 0x0 0 + fblelr fcc0,0 + + set_spr_addr bad,lr + set_fcc 0x1 1 + fblelr fcc1,1 + + set_spr_addr bad,lr + set_fcc 0x2 2 + fblelr fcc2,2 + + set_spr_addr bad,lr + set_fcc 0x3 3 + fblelr fcc3,3 + + set_spr_addr ok5,lr + set_fcc 0x4 0 + fblelr fcc0,0 + fail +ok5: + set_spr_addr ok6,lr + set_fcc 0x5 1 + fblelr fcc1,1 + fail +ok6: + set_spr_addr ok7,lr + set_fcc 0x6 2 + fblelr fcc2,2 + fail +ok7: + set_spr_addr ok8,lr + set_fcc 0x7 3 + fblelr fcc3,3 + fail +ok8: + set_spr_addr ok9,lr + set_fcc 0x8 0 + fblelr fcc0,0 + fail +ok9: + set_spr_addr oka,lr + set_fcc 0x9 1 + fblelr fcc1,1 + fail +oka: + set_spr_addr okb,lr + set_fcc 0xa 2 + fblelr fcc2,2 + fail +okb: + set_spr_addr okc,lr + set_fcc 0xb 3 + fblelr fcc3,3 + fail +okc: + set_spr_addr okd,lr + set_fcc 0xc 0 + fblelr fcc0,0 + fail +okd: + set_spr_addr oke,lr + set_fcc 0xd 1 + fblelr fcc1,1 + fail +oke: + set_spr_addr okf,lr + set_fcc 0xe 2 + fblelr fcc2,2 + fail +okf: + set_spr_addr okg,lr + set_fcc 0xf 3 + fblelr fcc3,3 + fail +okg: + pass +bad: + fail + diff --git a/sim/testsuite/sim/frv/fblg.cgs b/sim/testsuite/sim/frv/fblg.cgs new file mode 100644 index 0000000..a16f802 --- /dev/null +++ b/sim/testsuite/sim/frv/fblg.cgs @@ -0,0 +1,69 @@ +# frv testcase for fblg $FCCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global fblg +fblg: + set_fcc 0x0 0 + fblg fcc0,0,bad + set_fcc 0x1 1 + fblg fcc1,1,bad + set_fcc 0x2 2 + fblg fcc2,2,ok3 + fail +ok3: + set_fcc 0x3 3 + fblg fcc3,3,ok4 + fail +ok4: + set_fcc 0x4 0 + fblg fcc0,0,ok5 + fail +ok5: + set_fcc 0x5 1 + fblg fcc1,1,ok6 + fail +ok6: + set_fcc 0x6 2 + fblg fcc2,2,ok7 + fail +ok7: + set_fcc 0x7 3 + fblg fcc3,3,ok8 + fail +ok8: + set_fcc 0x8 0 + fblg fcc0,0,bad + set_fcc 0x9 1 + fblg fcc1,1,bad + set_fcc 0xa 2 + fblg fcc2,2,okb + fail +okb: + set_fcc 0xb 3 + fblg fcc3,3,okc + fail +okc: + set_fcc 0xc 0 + fblg fcc0,0,okd + fail +okd: + set_fcc 0xd 1 + fblg fcc1,1,oke + fail +oke: + set_fcc 0xe 2 + fblg fcc2,2,okf + fail +okf: + set_fcc 0xf 3 + fblg fcc3,3,okg + fail +okg: + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/fblglr.cgs b/sim/testsuite/sim/frv/fblglr.cgs new file mode 100644 index 0000000..e7a32b0 --- /dev/null +++ b/sim/testsuite/sim/frv/fblglr.cgs @@ -0,0 +1,88 @@ +# frv testcase for fblglr $FCCi,$hint +# mach: all + + .include "testutils.inc" + + start + + .global fblglr +fblglr: + set_spr_addr bad,lr + set_fcc 0x0 0 + fblglr fcc0,0 + + set_spr_addr bad,lr + set_fcc 0x1 1 + fblglr fcc1,1 + + set_spr_addr ok3,lr + set_fcc 0x2 2 + fblglr fcc2,2 + fail +ok3: + set_spr_addr ok4,lr + set_fcc 0x3 3 + fblglr fcc3,3 + fail +ok4: + set_spr_addr ok5,lr + set_fcc 0x4 0 + fblglr fcc0,0 + fail +ok5: + set_spr_addr ok6,lr + set_fcc 0x5 1 + fblglr fcc1,1 + fail +ok6: + set_spr_addr ok7,lr + set_fcc 0x6 2 + fblglr fcc2,2 + fail +ok7: + set_spr_addr ok8,lr + set_fcc 0x7 3 + fblglr fcc3,3 + fail +ok8: + set_spr_addr bad,lr + set_fcc 0x8 0 + fblglr fcc0,0 + + set_spr_addr bad,lr + set_fcc 0x9 1 + fblglr fcc1,1 + + set_spr_addr okb,lr + set_fcc 0xa 2 + fblglr fcc2,2 + fail +okb: + set_spr_addr okc,lr + set_fcc 0xb 3 + fblglr fcc3,3 + fail +okc: + set_spr_addr okd,lr + set_fcc 0xc 0 + fblglr fcc0,0 + fail +okd: + set_spr_addr oke,lr + set_fcc 0xd 1 + fblglr fcc1,1 + fail +oke: + set_spr_addr okf,lr + set_fcc 0xe 2 + fblglr fcc2,2 + fail +okf: + set_spr_addr okg,lr + set_fcc 0xf 3 + fblglr fcc3,3 + fail +okg: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/fblt.cgs b/sim/testsuite/sim/frv/fblt.cgs new file mode 100644 index 0000000..ef7e5c7 --- /dev/null +++ b/sim/testsuite/sim/frv/fblt.cgs @@ -0,0 +1,61 @@ +# frv testcase for fblt $FCCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global fblt +fblt: + set_fcc 0x0 0 + fblt fcc0,0,bad + set_fcc 0x1 1 + fblt fcc1,1,bad + set_fcc 0x2 2 + fblt fcc2,2,bad + set_fcc 0x3 3 + fblt fcc3,3,bad + set_fcc 0x4 0 + fblt fcc0,0,ok5 + fail +ok5: + set_fcc 0x5 1 + fblt fcc1,1,ok6 + fail +ok6: + set_fcc 0x6 2 + fblt fcc2,2,ok7 + fail +ok7: + set_fcc 0x7 3 + fblt fcc3,3,ok8 + fail +ok8: + set_fcc 0x8 0 + fblt fcc0,0,bad + set_fcc 0x9 1 + fblt fcc1,1,bad + set_fcc 0xa 2 + fblt fcc2,2,bad + set_fcc 0xb 3 + fblt fcc3,3,bad + set_fcc 0xc 0 + fblt fcc0,0,okd + fail +okd: + set_fcc 0xd 1 + fblt fcc1,1,oke + fail +oke: + set_fcc 0xe 2 + fblt fcc2,2,okf + fail +okf: + set_fcc 0xf 3 + fblt fcc3,3,okg + fail +okg: + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/fbltlr.cgs b/sim/testsuite/sim/frv/fbltlr.cgs new file mode 100644 index 0000000..0a2c436 --- /dev/null +++ b/sim/testsuite/sim/frv/fbltlr.cgs @@ -0,0 +1,84 @@ +# frv testcase for fbltlr $FCCi,$hint +# mach: all + + .include "testutils.inc" + + start + + .global fbltlr +fbltlr: + set_spr_addr bad,lr + set_fcc 0x0 0 + fbltlr fcc0,0 + + set_spr_addr bad,lr + set_fcc 0x1 1 + fbltlr fcc1,1 + + set_spr_addr bad,lr + set_fcc 0x2 2 + fbltlr fcc2,2 + + set_spr_addr bad,lr + set_fcc 0x3 3 + fbltlr fcc3,3 + + set_spr_addr ok5,lr + set_fcc 0x4 0 + fbltlr fcc0,0 + fail +ok5: + set_spr_addr ok6,lr + set_fcc 0x5 1 + fbltlr fcc1,1 + fail +ok6: + set_spr_addr ok7,lr + set_fcc 0x6 2 + fbltlr fcc2,2 + fail +ok7: + set_spr_addr ok8,lr + set_fcc 0x7 3 + fbltlr fcc3,3 + fail +ok8: + set_spr_addr bad,lr + set_fcc 0x8 0 + fbltlr fcc0,0 + + set_spr_addr bad,lr + set_fcc 0x9 1 + fbltlr fcc1,1 + + set_spr_addr bad,lr + set_fcc 0xa 2 + fbltlr fcc2,2 + + set_spr_addr bad,lr + set_fcc 0xb 3 + fbltlr fcc3,3 + + set_spr_addr okd,lr + set_fcc 0xc 0 + fbltlr fcc0,0 + fail +okd: + set_spr_addr oke,lr + set_fcc 0xd 1 + fbltlr fcc1,1 + fail +oke: + set_spr_addr okf,lr + set_fcc 0xe 2 + fbltlr fcc2,2 + fail +okf: + set_spr_addr okg,lr + set_fcc 0xf 3 + fbltlr fcc3,3 + fail +okg: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/fbne.cgs b/sim/testsuite/sim/frv/fbne.cgs new file mode 100644 index 0000000..f376eea --- /dev/null +++ b/sim/testsuite/sim/frv/fbne.cgs @@ -0,0 +1,73 @@ +# frv testcase for fbne $FCCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global fbne +fbne: + set_fcc 0x0 0 + fbne fcc0,0,bad + set_fcc 0x1 1 + fbne fcc1,1,ok2 + fail +ok2: + set_fcc 0x2 2 + fbne fcc2,2,ok3 + fail +ok3: + set_fcc 0x3 3 + fbne fcc3,3,ok4 + fail +ok4: + set_fcc 0x4 0 + fbne fcc0,0,ok5 + fail +ok5: + set_fcc 0x5 1 + fbne fcc1,1,ok6 + fail +ok6: + set_fcc 0x6 2 + fbne fcc2,2,ok7 + fail +ok7: + set_fcc 0x7 3 + fbne fcc3,3,ok8 + fail +ok8: + set_fcc 0x8 0 + fbne fcc0,0,bad + set_fcc 0x9 1 + fbne fcc1,1,oka + fail +oka: + set_fcc 0xa 2 + fbne fcc2,2,okb + fail +okb: + set_fcc 0xb 3 + fbne fcc3,3,okc + fail +okc: + set_fcc 0xc 0 + fbne fcc0,0,okd + fail +okd: + set_fcc 0xd 1 + fbne fcc1,1,oke + fail +oke: + set_fcc 0xe 2 + fbne fcc2,2,okf + fail +okf: + set_fcc 0xf 3 + fbne fcc3,3,okg + fail +okg: + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/fbnelr.cgs b/sim/testsuite/sim/frv/fbnelr.cgs new file mode 100644 index 0000000..334d185 --- /dev/null +++ b/sim/testsuite/sim/frv/fbnelr.cgs @@ -0,0 +1,90 @@ +# frv testcase for fbnelr $FCCi,$hint +# mach: all + + .include "testutils.inc" + + start + + .global fbnelr +fbnelr: + set_spr_addr bad,lr + set_fcc 0x0 0 + fbnelr fcc0,0 + + set_spr_addr ok2,lr + set_fcc 0x1 1 + fbnelr fcc1,1 + fail +ok2: + set_spr_addr ok3,lr + set_fcc 0x2 2 + fbnelr fcc2,2 + fail +ok3: + set_spr_addr ok4,lr + set_fcc 0x3 3 + fbnelr fcc3,3 + fail +ok4: + set_spr_addr ok5,lr + set_fcc 0x4 0 + fbnelr fcc0,0 + fail +ok5: + set_spr_addr ok6,lr + set_fcc 0x5 1 + fbnelr fcc1,1 + fail +ok6: + set_spr_addr ok7,lr + set_fcc 0x6 2 + fbnelr fcc2,2 + fail +ok7: + set_spr_addr ok8,lr + set_fcc 0x7 3 + fbnelr fcc3,3 + fail +ok8: + set_spr_addr bad,lr + set_fcc 0x8 0 + fbnelr fcc0,0 + + set_spr_addr oka,lr + set_fcc 0x9 1 + fbnelr fcc1,1 + fail +oka: + set_spr_addr okb,lr + set_fcc 0xa 2 + fbnelr fcc2,2 + fail +okb: + set_spr_addr okc,lr + set_fcc 0xb 3 + fbnelr fcc3,3 + fail +okc: + set_spr_addr okd,lr + set_fcc 0xc 0 + fbnelr fcc0,0 + fail +okd: + set_spr_addr oke,lr + set_fcc 0xd 1 + fbnelr fcc1,1 + fail +oke: + set_spr_addr okf,lr + set_fcc 0xe 2 + fbnelr fcc2,2 + fail +okf: + set_spr_addr okg,lr + set_fcc 0xf 3 + fbnelr fcc3,3 + fail +okg: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/fbno.cgs b/sim/testsuite/sim/frv/fbno.cgs new file mode 100644 index 0000000..a3dc587 --- /dev/null +++ b/sim/testsuite/sim/frv/fbno.cgs @@ -0,0 +1,45 @@ +# frv testcase for fbno $FCCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global fbno +fbno: + set_fcc 0x0 0 + fbno + set_fcc 0x1 1 + fbno + set_fcc 0x2 2 + fbno + set_fcc 0x3 3 + fbno + set_fcc 0x4 0 + fbno + set_fcc 0x5 1 + fbno + set_fcc 0x6 2 + fbno + set_fcc 0x7 3 + fbno + set_fcc 0x8 0 + fbno + set_fcc 0x9 1 + fbno + set_fcc 0xa 2 + fbno + set_fcc 0xb 3 + fbno + set_fcc 0xc 0 + fbno + set_fcc 0xd 1 + fbno + set_fcc 0xe 2 + fbno + set_fcc 0xf 3 + fbno + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/fbnolr.cgs b/sim/testsuite/sim/frv/fbnolr.cgs new file mode 100644 index 0000000..be5a0ef --- /dev/null +++ b/sim/testsuite/sim/frv/fbnolr.cgs @@ -0,0 +1,47 @@ +# frv testcase for fbnolr +# mach: all + + .include "testutils.inc" + + start + + .global fbnolr +fbnolr: + set_spr_addr bad,lr + + set_fcc 0x0 0 + fbnolr + set_fcc 0x1 1 + fbnolr + set_fcc 0x2 2 + fbnolr + set_fcc 0x3 3 + fbnolr + set_fcc 0x4 0 + fbnolr + set_fcc 0x5 1 + fbnolr + set_fcc 0x6 2 + fbnolr + set_fcc 0x7 3 + fbnolr + set_fcc 0x8 0 + fbnolr + set_fcc 0x9 1 + fbnolr + set_fcc 0xa 2 + fbnolr + set_fcc 0xb 3 + fbnolr + set_fcc 0xc 0 + fbnolr + set_fcc 0xd 1 + fbnolr + set_fcc 0xe 2 + fbnolr + set_fcc 0xf 3 + fbnolr + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/fbo.cgs b/sim/testsuite/sim/frv/fbo.cgs new file mode 100644 index 0000000..42062c9 --- /dev/null +++ b/sim/testsuite/sim/frv/fbo.cgs @@ -0,0 +1,73 @@ +# frv testcase for fbo $FCCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global fbo +fbo: + set_fcc 0x0 0 + fbo fcc0,0,bad + set_fcc 0x1 1 + fbo fcc1,1,bad + set_fcc 0x2 2 + fbo fcc2,2,ok3 + fail +ok3: + set_fcc 0x3 3 + fbo fcc3,3,ok4 + fail +ok4: + set_fcc 0x4 0 + fbo fcc0,0,ok5 + fail +ok5: + set_fcc 0x5 1 + fbo fcc1,1,ok6 + fail +ok6: + set_fcc 0x6 2 + fbo fcc2,2,ok7 + fail +ok7: + set_fcc 0x7 3 + fbo fcc3,3,ok8 + fail +ok8: + set_fcc 0x8 0 + fbo fcc0,0,ok9 + fail +ok9: + set_fcc 0x9 1 + fbo fcc1,1,oka + fail +oka: + set_fcc 0xa 2 + fbo fcc2,2,okb + fail +okb: + set_fcc 0xb 3 + fbo fcc3,3,okc + fail +okc: + set_fcc 0xc 0 + fbo fcc0,0,okd + fail +okd: + set_fcc 0xd 1 + fbo fcc1,1,oke + fail +oke: + set_fcc 0xe 2 + fbo fcc2,2,okf + fail +okf: + set_fcc 0xf 3 + fbo fcc3,3,okg + fail +okg: + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/fbolr.cgs b/sim/testsuite/sim/frv/fbolr.cgs new file mode 100644 index 0000000..2f9bfb3 --- /dev/null +++ b/sim/testsuite/sim/frv/fbolr.cgs @@ -0,0 +1,90 @@ +# frv testcase for fbolr $FCCi,$hint +# mach: all + + .include "testutils.inc" + + start + + .global fbolr +fbolr: + set_spr_addr bad,lr + set_fcc 0x0 0 + fbolr fcc0,0 + + set_spr_addr bad,lr + set_fcc 0x1 1 + fbolr fcc1,1 + + set_spr_addr ok3,lr + set_fcc 0x2 2 + fbolr fcc2,2 + fail +ok3: + set_spr_addr ok4,lr + set_fcc 0x3 3 + fbolr fcc3,3 + fail +ok4: + set_spr_addr ok5,lr + set_fcc 0x4 0 + fbolr fcc0,0 + fail +ok5: + set_spr_addr ok6,lr + set_fcc 0x5 1 + fbolr fcc1,1 + fail +ok6: + set_spr_addr ok7,lr + set_fcc 0x6 2 + fbolr fcc2,2 + fail +ok7: + set_spr_addr ok8,lr + set_fcc 0x7 3 + fbolr fcc3,3 + fail +ok8: + set_spr_addr ok9,lr + set_fcc 0x8 0 + fbolr fcc0,0 + fail +ok9: + set_spr_addr oka,lr + set_fcc 0x9 1 + fbolr fcc1,1 + fail +oka: + set_spr_addr okb,lr + set_fcc 0xa 2 + fbolr fcc2,2 + fail +okb: + set_spr_addr okc,lr + set_fcc 0xb 3 + fbolr fcc3,3 + fail +okc: + set_spr_addr okd,lr + set_fcc 0xc 0 + fbolr fcc0,0 + fail +okd: + set_spr_addr oke,lr + set_fcc 0xd 1 + fbolr fcc1,1 + fail +oke: + set_spr_addr okf,lr + set_fcc 0xe 2 + fbolr fcc2,2 + fail +okf: + set_spr_addr okg,lr + set_fcc 0xf 3 + fbolr fcc3,3 + fail +okg: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/fbra.cgs b/sim/testsuite/sim/frv/fbra.cgs new file mode 100644 index 0000000..2f29308 --- /dev/null +++ b/sim/testsuite/sim/frv/fbra.cgs @@ -0,0 +1,75 @@ +# frv testcase for fbra $FCCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global fbra +fbra: + set_fcc 0x0 0 + fbra ok1 + fail +ok1: + set_fcc 0x1 1 + fbra ok2 + fail +ok2: + set_fcc 0x2 2 + fbra ok3 + fail +ok3: + set_fcc 0x3 3 + fbra ok4 + fail +ok4: + set_fcc 0x4 0 + fbra ok5 + fail +ok5: + set_fcc 0x5 1 + fbra ok6 + fail +ok6: + set_fcc 0x6 2 + fbra ok7 + fail +ok7: + set_fcc 0x7 3 + fbra ok8 + fail +ok8: + set_fcc 0x8 0 + fbra ok9 + fail +ok9: + set_fcc 0x9 1 + fbra oka + fail +oka: + set_fcc 0xa 2 + fbra okb + fail +okb: + set_fcc 0xb 3 + fbra okc + fail +okc: + set_fcc 0xc 0 + fbra okd + fail +okd: + set_fcc 0xd 1 + fbra oke + fail +oke: + set_fcc 0xe 2 + fbra okf + fail +okf: + set_fcc 0xf 3 + fbra okg + fail +okg: + + pass diff --git a/sim/testsuite/sim/frv/fbralr.cgs b/sim/testsuite/sim/frv/fbralr.cgs new file mode 100644 index 0000000..d57afc9 --- /dev/null +++ b/sim/testsuite/sim/frv/fbralr.cgs @@ -0,0 +1,91 @@ +# frv testcase for fbralr +# mach: all + + .include "testutils.inc" + + start + + .global fbralr +fbralr: + set_spr_addr ok1,lr + set_fcc 0x0 0 + fbralr + fail +ok1: + set_spr_addr ok2,lr + set_fcc 0x1 1 + fbralr + fail +ok2: + set_spr_addr ok3,lr + set_fcc 0x2 2 + fbralr + fail +ok3: + set_spr_addr ok4,lr + set_fcc 0x3 3 + fbralr + fail +ok4: + set_spr_addr ok5,lr + set_fcc 0x4 0 + fbralr + fail +ok5: + set_spr_addr ok6,lr + set_fcc 0x5 1 + fbralr + fail +ok6: + set_spr_addr ok7,lr + set_fcc 0x6 2 + fbralr + fail +ok7: + set_spr_addr ok8,lr + set_fcc 0x7 3 + fbralr + fail +ok8: + set_spr_addr ok9,lr + set_fcc 0x8 0 + fbralr + fail +ok9: + set_spr_addr oka,lr + set_fcc 0x9 1 + fbralr + fail +oka: + set_spr_addr okb,lr + set_fcc 0xa 2 + fbralr + fail +okb: + set_spr_addr okc,lr + set_fcc 0xb 3 + fbralr + fail +okc: + set_spr_addr okd,lr + set_fcc 0xc 0 + fbralr + fail +okd: + set_spr_addr oke,lr + set_fcc 0xd 1 + fbralr + fail +oke: + set_spr_addr okf,lr + set_fcc 0xe 2 + fbralr + fail +okf: + set_spr_addr okg,lr + set_fcc 0xf 3 + fbralr + fail +okg: + + pass diff --git a/sim/testsuite/sim/frv/fbu.cgs b/sim/testsuite/sim/frv/fbu.cgs new file mode 100644 index 0000000..f397001 --- /dev/null +++ b/sim/testsuite/sim/frv/fbu.cgs @@ -0,0 +1,61 @@ +# frv testcase for fbu $FCCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global fbu +fbu: + set_fcc 0x0 0 + fbu fcc0,0,bad + set_fcc 0x1 1 + fbu fcc1,1,ok2 + fail +ok2: + set_fcc 0x2 2 + fbu fcc2,2,bad + set_fcc 0x3 3 + fbu fcc3,3,ok4 + fail +ok4: + set_fcc 0x4 0 + fbu fcc0,0,bad + set_fcc 0x5 1 + fbu fcc1,1,ok6 + fail +ok6: + set_fcc 0x6 2 + fbu fcc2,2,bad + set_fcc 0x7 3 + fbu fcc3,3,ok8 + fail +ok8: + set_fcc 0x8 0 + fbu fcc0,0,bad + set_fcc 0x9 1 + fbu fcc1,1,oka + fail +oka: + set_fcc 0xa 2 + fbu fcc2,2,bad + set_fcc 0xb 3 + fbu fcc3,3,okc + fail +okc: + set_fcc 0xc 0 + fbu fcc0,0,bad + set_fcc 0xd 1 + fbu fcc1,1,oke + fail +oke: + set_fcc 0xe 2 + fbu fcc2,2,bad + set_fcc 0xf 3 + fbu fcc3,3,okg + fail +okg: + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/fbue.cgs b/sim/testsuite/sim/frv/fbue.cgs new file mode 100644 index 0000000..dd1d636 --- /dev/null +++ b/sim/testsuite/sim/frv/fbue.cgs @@ -0,0 +1,69 @@ +# frv testcase for fbue $FCCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global fbue +fbue: + set_fcc 0x0 0 + fbue fcc0,0,bad + set_fcc 0x1 1 + fbue fcc1,1,ok2 + fail +ok2: + set_fcc 0x2 2 + fbue fcc2,2,bad + set_fcc 0x3 3 + fbue fcc3,3,ok4 + fail +ok4: + set_fcc 0x4 0 + fbue fcc0,0,bad + set_fcc 0x5 1 + fbue fcc1,1,ok6 + fail +ok6: + set_fcc 0x6 2 + fbue fcc2,2,bad + set_fcc 0x7 3 + fbue fcc3,3,ok8 + fail +ok8: + set_fcc 0x8 0 + fbue fcc0,0,ok9 + fail +ok9: + set_fcc 0x9 1 + fbue fcc1,1,oka + fail +oka: + set_fcc 0xa 2 + fbue fcc2,2,okb + fail +okb: + set_fcc 0xb 3 + fbue fcc3,3,okc + fail +okc: + set_fcc 0xc 0 + fbue fcc0,0,okd + fail +okd: + set_fcc 0xd 1 + fbue fcc1,1,oke + fail +oke: + set_fcc 0xe 2 + fbue fcc2,2,okf + fail +okf: + set_fcc 0xf 3 + fbue fcc3,3,okg + fail +okg: + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/fbuelr.cgs b/sim/testsuite/sim/frv/fbuelr.cgs new file mode 100644 index 0000000..62ca6aa --- /dev/null +++ b/sim/testsuite/sim/frv/fbuelr.cgs @@ -0,0 +1,88 @@ +# frv testcase for fbuelr $FCCi,$hint +# mach: all + + .include "testutils.inc" + + start + + .global fbuelr +fbuelr: + set_spr_addr bad,lr + set_fcc 0x0 0 + fbuelr fcc0,0 + + set_spr_addr ok2,lr + set_fcc 0x1 1 + fbuelr fcc1,1 + fail +ok2: + set_spr_addr bad,lr + set_fcc 0x2 2 + fbuelr fcc2,2 + + set_spr_addr ok4,lr + set_fcc 0x3 3 + fbuelr fcc3,3 + fail +ok4: + set_spr_addr bad,lr + set_fcc 0x4 0 + fbuelr fcc0,0 + + set_spr_addr ok6,lr + set_fcc 0x5 1 + fbuelr fcc1,1 + fail +ok6: + set_spr_addr bad,lr + set_fcc 0x6 2 + fbuelr fcc2,2 + + set_spr_addr ok8,lr + set_fcc 0x7 3 + fbuelr fcc3,3 + fail +ok8: + set_spr_addr ok9,lr + set_fcc 0x8 0 + fbuelr fcc0,0 + fail +ok9: + set_spr_addr oka,lr + set_fcc 0x9 1 + fbuelr fcc1,1 + fail +oka: + set_spr_addr okb,lr + set_fcc 0xa 2 + fbuelr fcc2,2 + fail +okb: + set_spr_addr okc,lr + set_fcc 0xb 3 + fbuelr fcc3,3 + fail +okc: + set_spr_addr okd,lr + set_fcc 0xc 0 + fbuelr fcc0,0 + fail +okd: + set_spr_addr oke,lr + set_fcc 0xd 1 + fbuelr fcc1,1 + fail +oke: + set_spr_addr okf,lr + set_fcc 0xe 2 + fbuelr fcc2,2 + fail +okf: + set_spr_addr okg,lr + set_fcc 0xf 3 + fbuelr fcc3,3 + fail +okg: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/fbug.cgs b/sim/testsuite/sim/frv/fbug.cgs new file mode 100644 index 0000000..3a5ee01 --- /dev/null +++ b/sim/testsuite/sim/frv/fbug.cgs @@ -0,0 +1,69 @@ +# frv testcase for fbug $FCCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global fbug +fbug: + set_fcc 0x0 0 + fbug fcc0,0,bad + set_fcc 0x1 1 + fbug fcc1,1,ok2 + fail +ok2: + set_fcc 0x2 2 + fbug fcc2,2,ok3 + fail +ok3: + set_fcc 0x3 3 + fbug fcc3,3,ok4 + fail +ok4: + set_fcc 0x4 0 + fbug fcc0,0,bad + set_fcc 0x5 1 + fbug fcc1,1,ok6 + fail +ok6: + set_fcc 0x6 2 + fbug fcc2,2,ok7 + fail +ok7: + set_fcc 0x7 3 + fbug fcc3,3,ok8 + fail +ok8: + set_fcc 0x8 0 + fbug fcc0,0,bad + set_fcc 0x9 1 + fbug fcc1,1,oka + fail +oka: + set_fcc 0xa 2 + fbug fcc2,2,okb + fail +okb: + set_fcc 0xb 3 + fbug fcc3,3,okc + fail +okc: + set_fcc 0xc 0 + fbug fcc0,0,bad + set_fcc 0xd 1 + fbug fcc1,1,oke + fail +oke: + set_fcc 0xe 2 + fbug fcc2,2,okf + fail +okf: + set_fcc 0xf 3 + fbug fcc3,3,okg + fail +okg: + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/fbuge.cgs b/sim/testsuite/sim/frv/fbuge.cgs new file mode 100644 index 0000000..edbf7f8 --- /dev/null +++ b/sim/testsuite/sim/frv/fbuge.cgs @@ -0,0 +1,73 @@ +# frv testcase for fbuge $FCCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global fbuge +fbuge: + set_fcc 0x0 0 + fbuge fcc0,0,bad + set_fcc 0x1 1 + fbuge fcc1,1,ok2 + fail +ok2: + set_fcc 0x2 2 + fbuge fcc2,2,ok3 + fail +ok3: + set_fcc 0x3 3 + fbuge fcc3,3,ok4 + fail +ok4: + set_fcc 0x4 0 + fbuge fcc0,0,bad + set_fcc 0x5 1 + fbuge fcc1,1,ok6 + fail +ok6: + set_fcc 0x6 2 + fbuge fcc2,2,ok7 + fail +ok7: + set_fcc 0x7 3 + fbuge fcc3,3,ok8 + fail +ok8: + set_fcc 0x8 0 + fbuge fcc0,0,ok9 + fail +ok9: + set_fcc 0x9 1 + fbuge fcc1,1,oka + fail +oka: + set_fcc 0xa 2 + fbuge fcc2,2,okb + fail +okb: + set_fcc 0xb 3 + fbuge fcc3,3,okc + fail +okc: + set_fcc 0xc 0 + fbuge fcc0,0,okd + fail +okd: + set_fcc 0xd 1 + fbuge fcc1,1,oke + fail +oke: + set_fcc 0xe 2 + fbuge fcc2,2,okf + fail +okf: + set_fcc 0xf 3 + fbuge fcc3,3,okg + fail +okg: + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/fbugelr.cgs b/sim/testsuite/sim/frv/fbugelr.cgs new file mode 100644 index 0000000..b1799c5 --- /dev/null +++ b/sim/testsuite/sim/frv/fbugelr.cgs @@ -0,0 +1,90 @@ +# frv testcase for fbugelr $FCCi,$hint +# mach: all + + .include "testutils.inc" + + start + + .global fbugelr +fbugelr: + set_spr_addr bad,lr + set_fcc 0x0 0 + fbugelr fcc0,0 + + set_spr_addr ok2,lr + set_fcc 0x1 1 + fbugelr fcc1,1 + fail +ok2: + set_spr_addr ok3,lr + set_fcc 0x2 2 + fbugelr fcc2,2 + fail +ok3: + set_spr_addr ok4,lr + set_fcc 0x3 3 + fbugelr fcc3,3 + fail +ok4: + set_spr_addr bad,lr + set_fcc 0x4 0 + fbugelr fcc0,0 + + set_spr_addr ok6,lr + set_fcc 0x5 1 + fbugelr fcc1,1 + fail +ok6: + set_spr_addr ok7,lr + set_fcc 0x6 2 + fbugelr fcc2,2 + fail +ok7: + set_spr_addr ok8,lr + set_fcc 0x7 3 + fbugelr fcc3,3 + fail +ok8: + set_spr_addr ok9,lr + set_fcc 0x8 0 + fbugelr fcc0,0 + fail +ok9: + set_spr_addr oka,lr + set_fcc 0x9 1 + fbugelr fcc1,1 + fail +oka: + set_spr_addr okb,lr + set_fcc 0xa 2 + fbugelr fcc2,2 + fail +okb: + set_spr_addr okc,lr + set_fcc 0xb 3 + fbugelr fcc3,3 + fail +okc: + set_spr_addr okd,lr + set_fcc 0xc 0 + fbugelr fcc0,0 + fail +okd: + set_spr_addr oke,lr + set_fcc 0xd 1 + fbugelr fcc1,1 + fail +oke: + set_spr_addr okf,lr + set_fcc 0xe 2 + fbugelr fcc2,2 + fail +okf: + set_spr_addr okg,lr + set_fcc 0xf 3 + fbugelr fcc3,3 + fail +okg: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/fbuglr.cgs b/sim/testsuite/sim/frv/fbuglr.cgs new file mode 100644 index 0000000..d660a95 --- /dev/null +++ b/sim/testsuite/sim/frv/fbuglr.cgs @@ -0,0 +1,88 @@ +# frv testcase for fbuglr $FCCi,$hint +# mach: all + + .include "testutils.inc" + + start + + .global fbuglr +fbuglr: + set_spr_addr bad,lr + set_fcc 0x0 0 + fbuglr fcc0,0 + + set_spr_addr ok2,lr + set_fcc 0x1 1 + fbuglr fcc1,1 + fail +ok2: + set_spr_addr ok3,lr + set_fcc 0x2 2 + fbuglr fcc2,2 + fail +ok3: + set_spr_addr ok4,lr + set_fcc 0x3 3 + fbuglr fcc3,3 + fail +ok4: + set_spr_addr bad,lr + set_fcc 0x4 0 + fbuglr fcc0,0 + + set_spr_addr ok6,lr + set_fcc 0x5 1 + fbuglr fcc1,1 + fail +ok6: + set_spr_addr ok7,lr + set_fcc 0x6 2 + fbuglr fcc2,2 + fail +ok7: + set_spr_addr ok8,lr + set_fcc 0x7 3 + fbuglr fcc3,3 + fail +ok8: + set_spr_addr bad,lr + set_fcc 0x8 0 + fbuglr fcc0,0 + + set_spr_addr oka,lr + set_fcc 0x9 1 + fbuglr fcc1,1 + fail +oka: + set_spr_addr okb,lr + set_fcc 0xa 2 + fbuglr fcc2,2 + fail +okb: + set_spr_addr okc,lr + set_fcc 0xb 3 + fbuglr fcc3,3 + fail +okc: + set_spr_addr bad,lr + set_fcc 0xc 0 + fbuglr fcc0,0 + + set_spr_addr oke,lr + set_fcc 0xd 1 + fbuglr fcc1,1 + fail +oke: + set_spr_addr okf,lr + set_fcc 0xe 2 + fbuglr fcc2,2 + fail +okf: + set_spr_addr okg,lr + set_fcc 0xf 3 + fbuglr fcc3,3 + fail +okg: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/fbul.cgs b/sim/testsuite/sim/frv/fbul.cgs new file mode 100644 index 0000000..47b689d --- /dev/null +++ b/sim/testsuite/sim/frv/fbul.cgs @@ -0,0 +1,69 @@ +# frv testcase for fbul $FCCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global fbul +fbul: + set_fcc 0x0 0 + fbul fcc0,0,bad + set_fcc 0x1 1 + fbul fcc1,1,ok2 + fail +ok2: + set_fcc 0x2 2 + fbul fcc2,2,bad + set_fcc 0x3 3 + fbul fcc3,3,ok4 + fail +ok4: + set_fcc 0x4 0 + fbul fcc0,0,ok5 + fail +ok5: + set_fcc 0x5 1 + fbul fcc1,1,ok6 + fail +ok6: + set_fcc 0x6 2 + fbul fcc2,2,ok7 + fail +ok7: + set_fcc 0x7 3 + fbul fcc3,3,ok8 + fail +ok8: + set_fcc 0x8 0 + fbul fcc0,0,bad + set_fcc 0x9 1 + fbul fcc1,1,oka + fail +oka: + set_fcc 0xa 2 + fbul fcc2,2,bad + set_fcc 0xb 3 + fbul fcc3,3,okc + fail +okc: + set_fcc 0xc 0 + fbul fcc0,0,okd + fail +okd: + set_fcc 0xd 1 + fbul fcc1,1,oke + fail +oke: + set_fcc 0xe 2 + fbul fcc2,2,okf + fail +okf: + set_fcc 0xf 3 + fbul fcc3,3,okg + fail +okg: + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/fbule.cgs b/sim/testsuite/sim/frv/fbule.cgs new file mode 100644 index 0000000..ad5f4e9 --- /dev/null +++ b/sim/testsuite/sim/frv/fbule.cgs @@ -0,0 +1,73 @@ +# frv testcase for fbule $FCCi,$hint,$label16 +# mach: all + + .include "testutils.inc" + + start + + .global fbule +fbule: + set_fcc 0x0 0 + fbule fcc0,0,bad + set_fcc 0x1 1 + fbule fcc1,1,ok2 + fail +ok2: + set_fcc 0x2 2 + fbule fcc2,2,bad + set_fcc 0x3 3 + fbule fcc3,3,ok4 + fail +ok4: + set_fcc 0x4 0 + fbule fcc0,0,ok5 + fail +ok5: + set_fcc 0x5 1 + fbule fcc1,1,ok6 + fail +ok6: + set_fcc 0x6 2 + fbule fcc2,2,ok7 + fail +ok7: + set_fcc 0x7 3 + fbule fcc3,3,ok8 + fail +ok8: + set_fcc 0x8 0 + fbule fcc0,0,ok9 + fail +ok9: + set_fcc 0x9 1 + fbule fcc1,1,oka + fail +oka: + set_fcc 0xa 2 + fbule fcc2,2,okb + fail +okb: + set_fcc 0xb 3 + fbule fcc3,3,okc + fail +okc: + set_fcc 0xc 0 + fbule fcc0,0,okd + fail +okd: + set_fcc 0xd 1 + fbule fcc1,1,oke + fail +oke: + set_fcc 0xe 2 + fbule fcc2,2,okf + fail +okf: + set_fcc 0xf 3 + fbule fcc3,3,okg + fail +okg: + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/fbulelr.cgs b/sim/testsuite/sim/frv/fbulelr.cgs new file mode 100644 index 0000000..f34d58c --- /dev/null +++ b/sim/testsuite/sim/frv/fbulelr.cgs @@ -0,0 +1,90 @@ +# frv testcase for fbulelr $FCCi,$hint +# mach: all + + .include "testutils.inc" + + start + + .global fbulelr +fbulelr: + set_spr_addr bad,lr + set_fcc 0x0 0 + fbulelr fcc0,0 + + set_spr_addr ok2,lr + set_fcc 0x1 1 + fbulelr fcc1,1 + fail +ok2: + set_spr_addr bad,lr + set_fcc 0x2 2 + fbulelr fcc2,2 + + set_spr_addr ok4,lr + set_fcc 0x3 3 + fbulelr fcc3,3 + fail +ok4: + set_spr_addr ok5,lr + set_fcc 0x4 0 + fbulelr fcc0,0 + fail +ok5: + set_spr_addr ok6,lr + set_fcc 0x5 1 + fbulelr fcc1,1 + fail +ok6: + set_spr_addr ok7,lr + set_fcc 0x6 2 + fbulelr fcc2,2 + fail +ok7: + set_spr_addr ok8,lr + set_fcc 0x7 3 + fbulelr fcc3,3 + fail +ok8: + set_spr_addr ok9,lr + set_fcc 0x8 0 + fbulelr fcc0,0 + fail +ok9: + set_spr_addr oka,lr + set_fcc 0x9 1 + fbulelr fcc1,1 + fail +oka: + set_spr_addr okb,lr + set_fcc 0xa 2 + fbulelr fcc2,2 + fail +okb: + set_spr_addr okc,lr + set_fcc 0xb 3 + fbulelr fcc3,3 + fail +okc: + set_spr_addr okd,lr + set_fcc 0xc 0 + fbulelr fcc0,0 + fail +okd: + set_spr_addr oke,lr + set_fcc 0xd 1 + fbulelr fcc1,1 + fail +oke: + set_spr_addr okf,lr + set_fcc 0xe 2 + fbulelr fcc2,2 + fail +okf: + set_spr_addr okg,lr + set_fcc 0xf 3 + fbulelr fcc3,3 + fail +okg: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/fbullr.cgs b/sim/testsuite/sim/frv/fbullr.cgs new file mode 100644 index 0000000..2d5b251 --- /dev/null +++ b/sim/testsuite/sim/frv/fbullr.cgs @@ -0,0 +1,88 @@ +# frv testcase for fbullr $FCCi,$hint +# mach: all + + .include "testutils.inc" + + start + + .global fbullr +fbullr: + set_spr_addr bad,lr + set_fcc 0x0 0 + fbullr fcc0,0 + + set_spr_addr ok2,lr + set_fcc 0x1 1 + fbullr fcc1,1 + fail +ok2: + set_spr_addr bad,lr + set_fcc 0x2 2 + fbullr fcc2,2 + + set_spr_addr ok4,lr + set_fcc 0x3 3 + fbullr fcc3,3 + fail +ok4: + set_spr_addr ok5,lr + set_fcc 0x4 0 + fbullr fcc0,0 + fail +ok5: + set_spr_addr ok6,lr + set_fcc 0x5 1 + fbullr fcc1,1 + fail +ok6: + set_spr_addr ok7,lr + set_fcc 0x6 2 + fbullr fcc2,2 + fail +ok7: + set_spr_addr ok8,lr + set_fcc 0x7 3 + fbullr fcc3,3 + fail +ok8: + set_spr_addr bad,lr + set_fcc 0x8 0 + fbullr fcc0,0 + + set_spr_addr oka,lr + set_fcc 0x9 1 + fbullr fcc1,1 + fail +oka: + set_spr_addr bad,lr + set_fcc 0xa 2 + fbullr fcc2,2 + + set_spr_addr okc,lr + set_fcc 0xb 3 + fbullr fcc3,3 + fail +okc: + set_spr_addr okd,lr + set_fcc 0xc 0 + fbullr fcc0,0 + fail +okd: + set_spr_addr oke,lr + set_fcc 0xd 1 + fbullr fcc1,1 + fail +oke: + set_spr_addr okf,lr + set_fcc 0xe 2 + fbullr fcc2,2 + fail +okf: + set_spr_addr okg,lr + set_fcc 0xf 3 + fbullr fcc3,3 + fail +okg: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/fbulr.cgs b/sim/testsuite/sim/frv/fbulr.cgs new file mode 100644 index 0000000..d8594bc --- /dev/null +++ b/sim/testsuite/sim/frv/fbulr.cgs @@ -0,0 +1,84 @@ +# frv testcase for fbulr $FCCi,$hint +# mach: all + + .include "testutils.inc" + + start + + .global fbulr +fbulr: + set_spr_addr bad,lr + set_fcc 0x0 0 + fbulr fcc0,0 + + set_spr_addr ok2,lr + set_fcc 0x1 1 + fbulr fcc1,1 + fail +ok2: + set_spr_addr bad,lr + set_fcc 0x2 2 + fbulr fcc2,2 + + set_spr_addr ok4,lr + set_fcc 0x3 3 + fbulr fcc3,3 + fail +ok4: + set_spr_addr bad,lr + set_fcc 0x4 0 + fbulr fcc0,0 + + set_spr_addr ok6,lr + set_fcc 0x5 1 + fbulr fcc1,1 + fail +ok6: + set_spr_addr bad,lr + set_fcc 0x6 2 + fbulr fcc2,2 + + set_spr_addr ok8,lr + set_fcc 0x7 3 + fbulr fcc3,3 + fail +ok8: + set_spr_addr bad,lr + set_fcc 0x8 0 + fbulr fcc0,0 + + set_spr_addr oka,lr + set_fcc 0x9 1 + fbulr fcc1,1 + fail +oka: + set_spr_addr bad,lr + set_fcc 0xa 2 + fbulr fcc2,2 + + set_spr_addr okc,lr + set_fcc 0xb 3 + fbulr fcc3,3 + fail +okc: + set_spr_addr bad,lr + set_fcc 0xc 0 + fbulr fcc0,0 + + set_spr_addr oke,lr + set_fcc 0xd 1 + fbulr fcc1,1 + fail +oke: + set_spr_addr bad,lr + set_fcc 0xe 2 + fbulr fcc2,2 + + set_spr_addr okg,lr + set_fcc 0xf 3 + fbulr fcc3,3 + fail +okg: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/fcbeqlr.cgs b/sim/testsuite/sim/frv/fcbeqlr.cgs new file mode 100644 index 0000000..b87e77f --- /dev/null +++ b/sim/testsuite/sim/frv/fcbeqlr.cgs @@ -0,0 +1,262 @@ +# frv testcase for fcbeqlr $FCCi,$ccond,$hint +# mach: all + + .include "testutils.inc" + + start + + .global fcbeqlr +fcbeqlr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_fcc 0x0 0 + fcbeqlr fcc0,0,0 + + set_spr_addr bad,lr + set_fcc 0x1 1 + fcbeqlr fcc1,0,1 + + set_spr_addr bad,lr + set_fcc 0x2 2 + fcbeqlr fcc2,0,2 + + set_spr_addr bad,lr + set_fcc 0x3 3 + fcbeqlr fcc3,0,3 + + set_spr_addr bad,lr + set_fcc 0x4 0 + fcbeqlr fcc0,0,0 + + set_spr_addr bad,lr + set_fcc 0x5 1 + fcbeqlr fcc1,0,1 + + set_spr_addr bad,lr + set_fcc 0x6 2 + fcbeqlr fcc2,0,2 + + set_spr_addr bad,lr + set_fcc 0x7 3 + fcbeqlr fcc3,0,3 + + set_spr_addr ok9,lr + set_fcc 0x8 0 + fcbeqlr fcc0,0,0 + fail +ok9: + set_spr_addr oka,lr + set_fcc 0x9 1 + fcbeqlr fcc1,0,1 + fail +oka: + set_spr_addr okb,lr + set_fcc 0xa 2 + fcbeqlr fcc2,0,2 + fail +okb: + set_spr_addr okc,lr + set_fcc 0xb 3 + fcbeqlr fcc3,0,3 + fail +okc: + set_spr_addr okd,lr + set_fcc 0xc 0 + fcbeqlr fcc0,0,0 + fail +okd: + set_spr_addr oke,lr + set_fcc 0xd 1 + fcbeqlr fcc1,0,1 + fail +oke: + set_spr_addr okf,lr + set_fcc 0xe 2 + fcbeqlr fcc2,0,2 + fail +okf: + set_spr_addr okg,lr + set_fcc 0xf 3 + fcbeqlr fcc3,0,3 + fail +okg: + + ; ccond is true + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x0 0 + fcbeqlr fcc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x1 1 + fcbeqlr fcc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x2 2 + fcbeqlr fcc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x3 3 + fcbeqlr fcc3,1,3 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x4 0 + fcbeqlr fcc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x5 1 + fcbeqlr fcc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x6 2 + fcbeqlr fcc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x7 3 + fcbeqlr fcc3,1,3 + + set_spr_immed 1,lcr + set_spr_addr okp,lr + set_fcc 0x8 0 + fcbeqlr fcc0,1,0 + fail +okp: + set_spr_immed 1,lcr + set_spr_addr okq,lr + set_fcc 0x9 1 + fcbeqlr fcc1,1,1 + fail +okq: + set_spr_immed 1,lcr + set_spr_addr okr,lr + set_fcc 0xa 2 + fcbeqlr fcc2,1,2 + fail +okr: + set_spr_immed 1,lcr + set_spr_addr oks,lr + set_fcc 0xb 3 + fcbeqlr fcc3,1,3 + fail +oks: + set_spr_immed 1,lcr + set_spr_addr okt,lr + set_fcc 0xc 0 + fcbeqlr fcc0,1,0 + fail +okt: + set_spr_immed 1,lcr + set_spr_addr oku,lr + set_fcc 0xd 1 + fcbeqlr fcc1,1,1 + fail +oku: + set_spr_immed 1,lcr + set_spr_addr okv,lr + set_fcc 0xe 2 + fcbeqlr fcc2,1,2 + fail +okv: + set_spr_immed 1,lcr + set_spr_addr okw,lr + set_fcc 0xf 3 + fcbeqlr fcc3,1,3 + fail +okw: + ; ccond is false + set_spr_immed 128,lcr + + set_fcc 0x0 0 + fcbeqlr fcc0,1,0 + set_fcc 0x1 1 + fcbeqlr fcc1,1,1 + set_fcc 0x2 2 + fcbeqlr fcc2,1,2 + set_fcc 0x3 3 + fcbeqlr fcc3,1,3 + set_fcc 0x4 0 + fcbeqlr fcc0,1,0 + set_fcc 0x5 1 + fcbeqlr fcc1,1,1 + set_fcc 0x6 2 + fcbeqlr fcc2,1,2 + set_fcc 0x7 3 + fcbeqlr fcc3,1,3 + set_fcc 0x8 0 + fcbeqlr fcc0,1,0 + set_fcc 0x9 1 + fcbeqlr fcc1,1,1 + set_fcc 0xa 2 + fcbeqlr fcc2,1,2 + set_fcc 0xb 3 + fcbeqlr fcc3,1,3 + set_fcc 0xc 0 + fcbeqlr fcc0,1,0 + set_fcc 0xd 1 + fcbeqlr fcc1,1,1 + set_fcc 0xe 2 + fcbeqlr fcc2,1,2 + set_fcc 0xf 3 + fcbeqlr fcc3,1,3 + + ; ccond is false + set_spr_immed 1,lcr + set_fcc 0x0 0 + fcbeqlr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x1 1 + fcbeqlr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0x2 2 + fcbeqlr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0x3 3 + fcbeqlr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0x4 0 + fcbeqlr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x5 1 + fcbeqlr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0x6 2 + fcbeqlr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0x7 3 + fcbeqlr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0x8 0 + fcbeqlr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x9 1 + fcbeqlr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0xa 2 + fcbeqlr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0xb 3 + fcbeqlr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0xc 0 + fcbeqlr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0xd 1 + fcbeqlr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0xe 2 + fcbeqlr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0xf 3 + fcbeqlr fcc3,0,3 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/fcbgelr.cgs b/sim/testsuite/sim/frv/fcbgelr.cgs new file mode 100644 index 0000000..cc1b9d7 --- /dev/null +++ b/sim/testsuite/sim/frv/fcbgelr.cgs @@ -0,0 +1,270 @@ +# frv testcase for fcbgelr $FCCi,$ccond,$hint +# mach: all + + .include "testutils.inc" + + start + + .global fcbgelr +fcbgelr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_fcc 0x0 0 + fcbgelr fcc0,0,0 + + set_spr_addr bad,lr + set_fcc 0x1 1 + fcbgelr fcc1,0,1 + + set_spr_addr ok3,lr + set_fcc 0x2 2 + fcbgelr fcc2,0,2 + fail +ok3: + set_spr_addr ok4,lr + set_fcc 0x3 3 + fcbgelr fcc3,0,3 + fail +ok4: + set_spr_addr bad,lr + set_fcc 0x4 0 + fcbgelr fcc0,0,0 + + set_spr_addr bad,lr + set_fcc 0x5 1 + fcbgelr fcc1,0,1 + + set_spr_addr ok7,lr + set_fcc 0x6 2 + fcbgelr fcc2,0,2 + fail +ok7: + set_spr_addr ok8,lr + set_fcc 0x7 3 + fcbgelr fcc3,0,3 + fail +ok8: + set_spr_addr ok9,lr + set_fcc 0x8 0 + fcbgelr fcc0,0,0 + fail +ok9: + set_spr_addr oka,lr + set_fcc 0x9 1 + fcbgelr fcc1,0,1 + fail +oka: + set_spr_addr okb,lr + set_fcc 0xa 2 + fcbgelr fcc2,0,2 + fail +okb: + set_spr_addr okc,lr + set_fcc 0xb 3 + fcbgelr fcc3,0,3 + fail +okc: + set_spr_addr okd,lr + set_fcc 0xc 0 + fcbgelr fcc0,0,0 + fail +okd: + set_spr_addr oke,lr + set_fcc 0xd 1 + fcbgelr fcc1,0,1 + fail +oke: + set_spr_addr okf,lr + set_fcc 0xe 2 + fcbgelr fcc2,0,2 + fail +okf: + set_spr_addr okg,lr + set_fcc 0xf 3 + fcbgelr fcc3,0,3 + fail +okg: + + ; ccond is true + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x0 0 + fcbgelr fcc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x1 1 + fcbgelr fcc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr okj,lr + set_fcc 0x2 2 + fcbgelr fcc2,1,2 + fail +okj: + set_spr_immed 1,lcr + set_spr_addr okk,lr + set_fcc 0x3 3 + fcbgelr fcc3,1,3 + fail +okk: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x4 0 + fcbgelr fcc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x5 1 + fcbgelr fcc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr okn,lr + set_fcc 0x6 2 + fcbgelr fcc2,1,2 + fail +okn: + set_spr_immed 1,lcr + set_spr_addr oko,lr + set_fcc 0x7 3 + fcbgelr fcc3,1,3 + fail +oko: + set_spr_immed 1,lcr + set_spr_addr okp,lr + set_fcc 0x8 0 + fcbgelr fcc0,1,0 + fail +okp: + set_spr_immed 1,lcr + set_spr_addr okq,lr + set_fcc 0x9 1 + fcbgelr fcc1,1,1 + fail +okq: + set_spr_immed 1,lcr + set_spr_addr okr,lr + set_fcc 0xa 2 + fcbgelr fcc2,1,2 + fail +okr: + set_spr_immed 1,lcr + set_spr_addr oks,lr + set_fcc 0xb 3 + fcbgelr fcc3,1,3 + fail +oks: + set_spr_immed 1,lcr + set_spr_addr okt,lr + set_fcc 0xc 0 + fcbgelr fcc0,1,0 + fail +okt: + set_spr_immed 1,lcr + set_spr_addr oku,lr + set_fcc 0xd 1 + fcbgelr fcc1,1,1 + fail +oku: + set_spr_immed 1,lcr + set_spr_addr okv,lr + set_fcc 0xe 2 + fcbgelr fcc2,1,2 + fail +okv: + set_spr_immed 1,lcr + set_spr_addr okw,lr + set_fcc 0xf 3 + fcbgelr fcc3,1,3 + fail +okw: + ; ccond is false + set_spr_immed 128,lcr + + set_fcc 0x0 0 + fcbgelr fcc0,1,0 + set_fcc 0x1 1 + fcbgelr fcc1,1,1 + set_fcc 0x2 2 + fcbgelr fcc2,1,2 + set_fcc 0x3 3 + fcbgelr fcc3,1,3 + set_fcc 0x4 0 + fcbgelr fcc0,1,0 + set_fcc 0x5 1 + fcbgelr fcc1,1,1 + set_fcc 0x6 2 + fcbgelr fcc2,1,2 + set_fcc 0x7 3 + fcbgelr fcc3,1,3 + set_fcc 0x8 0 + fcbgelr fcc0,1,0 + set_fcc 0x9 1 + fcbgelr fcc1,1,1 + set_fcc 0xa 2 + fcbgelr fcc2,1,2 + set_fcc 0xb 3 + fcbgelr fcc3,1,3 + set_fcc 0xc 0 + fcbgelr fcc0,1,0 + set_fcc 0xd 1 + fcbgelr fcc1,1,1 + set_fcc 0xe 2 + fcbgelr fcc2,1,2 + set_fcc 0xf 3 + fcbgelr fcc3,1,3 + + ; ccond is false + set_spr_immed 1,lcr + set_fcc 0x0 0 + fcbgelr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x1 1 + fcbgelr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0x2 2 + fcbgelr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0x3 3 + fcbgelr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0x4 0 + fcbgelr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x5 1 + fcbgelr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0x6 2 + fcbgelr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0x7 3 + fcbgelr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0x8 0 + fcbgelr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x9 1 + fcbgelr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0xa 2 + fcbgelr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0xb 3 + fcbgelr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0xc 0 + fcbgelr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0xd 1 + fcbgelr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0xe 2 + fcbgelr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0xf 3 + fcbgelr fcc3,0,3 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/fcbgtlr.cgs b/sim/testsuite/sim/frv/fcbgtlr.cgs new file mode 100644 index 0000000..76204e2 --- /dev/null +++ b/sim/testsuite/sim/frv/fcbgtlr.cgs @@ -0,0 +1,262 @@ +# frv testcase for fcbgtlr $FCCi,$ccond,$hint +# mach: all + + .include "testutils.inc" + + start + + .global fcbgtlr +fcbgtlr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_fcc 0x0 0 + fcbgtlr fcc0,0,0 + + set_spr_addr bad,lr + set_fcc 0x1 1 + fcbgtlr fcc1,0,1 + + set_spr_addr ok3,lr + set_fcc 0x2 2 + fcbgtlr fcc2,0,2 + fail +ok3: + set_spr_addr ok4,lr + set_fcc 0x3 3 + fcbgtlr fcc3,0,3 + fail +ok4: + set_spr_addr bad,lr + set_fcc 0x4 0 + fcbgtlr fcc0,0,0 + + set_spr_addr bad,lr + set_fcc 0x5 1 + fcbgtlr fcc1,0,1 + + set_spr_addr ok7,lr + set_fcc 0x6 2 + fcbgtlr fcc2,0,2 + fail +ok7: + set_spr_addr ok8,lr + set_fcc 0x7 3 + fcbgtlr fcc3,0,3 + fail +ok8: + set_spr_addr bad,lr + set_fcc 0x8 0 + fcbgtlr fcc0,0,0 + + set_spr_addr bad,lr + set_fcc 0x9 1 + fcbgtlr fcc1,0,1 + + set_spr_addr okb,lr + set_fcc 0xa 2 + fcbgtlr fcc2,0,2 + fail +okb: + set_spr_addr okc,lr + set_fcc 0xb 3 + fcbgtlr fcc3,0,3 + fail +okc: + set_spr_addr bad,lr + set_fcc 0xc 0 + fcbgtlr fcc0,0,0 + + set_spr_addr bad,lr + set_fcc 0xd 1 + fcbgtlr fcc1,0,1 + + set_spr_addr okf,lr + set_fcc 0xe 2 + fcbgtlr fcc2,0,2 + fail +okf: + set_spr_addr okg,lr + set_fcc 0xf 3 + fcbgtlr fcc3,0,3 + fail +okg: + + ; ccond is true + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x0 0 + fcbgtlr fcc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x1 1 + fcbgtlr fcc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr okj,lr + set_fcc 0x2 2 + fcbgtlr fcc2,1,2 + fail +okj: + set_spr_immed 1,lcr + set_spr_addr okk,lr + set_fcc 0x3 3 + fcbgtlr fcc3,1,3 + fail +okk: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x4 0 + fcbgtlr fcc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x5 1 + fcbgtlr fcc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr okn,lr + set_fcc 0x6 2 + fcbgtlr fcc2,1,2 + fail +okn: + set_spr_immed 1,lcr + set_spr_addr oko,lr + set_fcc 0x7 3 + fcbgtlr fcc3,1,3 + fail +oko: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x8 0 + fcbgtlr fcc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x9 1 + fcbgtlr fcc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr okr,lr + set_fcc 0xa 2 + fcbgtlr fcc2,1,2 + fail +okr: + set_spr_immed 1,lcr + set_spr_addr oks,lr + set_fcc 0xb 3 + fcbgtlr fcc3,1,3 + fail +oks: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0xc 0 + fcbgtlr fcc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0xd 1 + fcbgtlr fcc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr okv,lr + set_fcc 0xe 2 + fcbgtlr fcc2,1,2 + fail +okv: + set_spr_immed 1,lcr + set_spr_addr okw,lr + set_fcc 0xf 3 + fcbgtlr fcc3,1,3 + fail +okw: + ; ccond is false + set_spr_immed 128,lcr + + set_fcc 0x0 0 + fcbgtlr fcc0,1,0 + set_fcc 0x1 1 + fcbgtlr fcc1,1,1 + set_fcc 0x2 2 + fcbgtlr fcc2,1,2 + set_fcc 0x3 3 + fcbgtlr fcc3,1,3 + set_fcc 0x4 0 + fcbgtlr fcc0,1,0 + set_fcc 0x5 1 + fcbgtlr fcc1,1,1 + set_fcc 0x6 2 + fcbgtlr fcc2,1,2 + set_fcc 0x7 3 + fcbgtlr fcc3,1,3 + set_fcc 0x8 0 + fcbgtlr fcc0,1,0 + set_fcc 0x9 1 + fcbgtlr fcc1,1,1 + set_fcc 0xa 2 + fcbgtlr fcc2,1,2 + set_fcc 0xb 3 + fcbgtlr fcc3,1,3 + set_fcc 0xc 0 + fcbgtlr fcc0,1,0 + set_fcc 0xd 1 + fcbgtlr fcc1,1,1 + set_fcc 0xe 2 + fcbgtlr fcc2,1,2 + set_fcc 0xf 3 + fcbgtlr fcc3,1,3 + + ; ccond is false + set_spr_immed 1,lcr + set_fcc 0x0 0 + fcbgtlr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x1 1 + fcbgtlr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0x2 2 + fcbgtlr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0x3 3 + fcbgtlr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0x4 0 + fcbgtlr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x5 1 + fcbgtlr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0x6 2 + fcbgtlr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0x7 3 + fcbgtlr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0x8 0 + fcbgtlr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x9 1 + fcbgtlr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0xa 2 + fcbgtlr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0xb 3 + fcbgtlr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0xc 0 + fcbgtlr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0xd 1 + fcbgtlr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0xe 2 + fcbgtlr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0xf 3 + fcbgtlr fcc3,0,3 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/fcblelr.cgs b/sim/testsuite/sim/frv/fcblelr.cgs new file mode 100644 index 0000000..b9850d6 --- /dev/null +++ b/sim/testsuite/sim/frv/fcblelr.cgs @@ -0,0 +1,270 @@ +# frv testcase for fcblelr $FCCi,$ccond,$hint +# mach: all + + .include "testutils.inc" + + start + + .global fcblelr +fcblelr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_fcc 0x0 0 + fcblelr fcc0,0,0 + + set_spr_addr bad,lr + set_fcc 0x1 1 + fcblelr fcc1,0,1 + + set_spr_addr bad,lr + set_fcc 0x2 2 + fcblelr fcc2,0,2 + + set_spr_addr bad,lr + set_fcc 0x3 3 + fcblelr fcc3,0,3 + + set_spr_addr ok5,lr + set_fcc 0x4 0 + fcblelr fcc0,0,0 + fail +ok5: + set_spr_addr ok6,lr + set_fcc 0x5 1 + fcblelr fcc1,0,1 + fail +ok6: + set_spr_addr ok7,lr + set_fcc 0x6 2 + fcblelr fcc2,0,2 + fail +ok7: + set_spr_addr ok8,lr + set_fcc 0x7 3 + fcblelr fcc3,0,3 + fail +ok8: + set_spr_addr ok9,lr + set_fcc 0x8 0 + fcblelr fcc0,0,0 + fail +ok9: + set_spr_addr oka,lr + set_fcc 0x9 1 + fcblelr fcc1,0,1 + fail +oka: + set_spr_addr okb,lr + set_fcc 0xa 2 + fcblelr fcc2,0,2 + fail +okb: + set_spr_addr okc,lr + set_fcc 0xb 3 + fcblelr fcc3,0,3 + fail +okc: + set_spr_addr okd,lr + set_fcc 0xc 0 + fcblelr fcc0,0,0 + fail +okd: + set_spr_addr oke,lr + set_fcc 0xd 1 + fcblelr fcc1,0,1 + fail +oke: + set_spr_addr okf,lr + set_fcc 0xe 2 + fcblelr fcc2,0,2 + fail +okf: + set_spr_addr okg,lr + set_fcc 0xf 3 + fcblelr fcc3,0,3 + fail +okg: + + ; ccond is true + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x0 0 + fcblelr fcc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x1 1 + fcblelr fcc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x2 2 + fcblelr fcc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x3 3 + fcblelr fcc3,1,3 + + set_spr_immed 1,lcr + set_spr_addr okl,lr + set_fcc 0x4 0 + fcblelr fcc0,1,0 + fail +okl: + set_spr_immed 1,lcr + set_spr_addr okm,lr + set_fcc 0x5 1 + fcblelr fcc1,1,1 + fail +okm: + set_spr_immed 1,lcr + set_spr_addr okn,lr + set_fcc 0x6 2 + fcblelr fcc2,1,2 + fail +okn: + set_spr_immed 1,lcr + set_spr_addr oko,lr + set_fcc 0x7 3 + fcblelr fcc3,1,3 + fail +oko: + set_spr_immed 1,lcr + set_spr_addr okp,lr + set_fcc 0x8 0 + fcblelr fcc0,1,0 + fail +okp: + set_spr_immed 1,lcr + set_spr_addr okq,lr + set_fcc 0x9 1 + fcblelr fcc1,1,1 + fail +okq: + set_spr_immed 1,lcr + set_spr_addr okr,lr + set_fcc 0xa 2 + fcblelr fcc2,1,2 + fail +okr: + set_spr_immed 1,lcr + set_spr_addr oks,lr + set_fcc 0xb 3 + fcblelr fcc3,1,3 + fail +oks: + set_spr_immed 1,lcr + set_spr_addr okt,lr + set_fcc 0xc 0 + fcblelr fcc0,1,0 + fail +okt: + set_spr_immed 1,lcr + set_spr_addr oku,lr + set_fcc 0xd 1 + fcblelr fcc1,1,1 + fail +oku: + set_spr_immed 1,lcr + set_spr_addr okv,lr + set_fcc 0xe 2 + fcblelr fcc2,1,2 + fail +okv: + set_spr_immed 1,lcr + set_spr_addr okw,lr + set_fcc 0xf 3 + fcblelr fcc3,1,3 + fail +okw: + ; ccond is false + set_spr_immed 128,lcr + + set_fcc 0x0 0 + fcblelr fcc0,1,0 + set_fcc 0x1 1 + fcblelr fcc1,1,1 + set_fcc 0x2 2 + fcblelr fcc2,1,2 + set_fcc 0x3 3 + fcblelr fcc3,1,3 + set_fcc 0x4 0 + fcblelr fcc0,1,0 + set_fcc 0x5 1 + fcblelr fcc1,1,1 + set_fcc 0x6 2 + fcblelr fcc2,1,2 + set_fcc 0x7 3 + fcblelr fcc3,1,3 + set_fcc 0x8 0 + fcblelr fcc0,1,0 + set_fcc 0x9 1 + fcblelr fcc1,1,1 + set_fcc 0xa 2 + fcblelr fcc2,1,2 + set_fcc 0xb 3 + fcblelr fcc3,1,3 + set_fcc 0xc 0 + fcblelr fcc0,1,0 + set_fcc 0xd 1 + fcblelr fcc1,1,1 + set_fcc 0xe 2 + fcblelr fcc2,1,2 + set_fcc 0xf 3 + fcblelr fcc3,1,3 + + ; ccond is false + set_spr_immed 1,lcr + set_fcc 0x0 0 + fcblelr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x1 1 + fcblelr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0x2 2 + fcblelr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0x3 3 + fcblelr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0x4 0 + fcblelr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x5 1 + fcblelr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0x6 2 + fcblelr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0x7 3 + fcblelr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0x8 0 + fcblelr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x9 1 + fcblelr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0xa 2 + fcblelr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0xb 3 + fcblelr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0xc 0 + fcblelr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0xd 1 + fcblelr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0xe 2 + fcblelr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0xf 3 + fcblelr fcc3,0,3 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/fcblglr.cgs b/sim/testsuite/sim/frv/fcblglr.cgs new file mode 100644 index 0000000..e875d40 --- /dev/null +++ b/sim/testsuite/sim/frv/fcblglr.cgs @@ -0,0 +1,270 @@ +# frv testcase for fcblglr $FCCi,$ccond,$hint +# mach: all + + .include "testutils.inc" + + start + + .global fcblglr +fcblglr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_fcc 0x0 0 + fcblglr fcc0,0,0 + + set_spr_addr bad,lr + set_fcc 0x1 1 + fcblglr fcc1,0,1 + + set_spr_addr ok3,lr + set_fcc 0x2 2 + fcblglr fcc2,0,2 + fail +ok3: + set_spr_addr ok4,lr + set_fcc 0x3 3 + fcblglr fcc3,0,3 + fail +ok4: + set_spr_addr ok5,lr + set_fcc 0x4 0 + fcblglr fcc0,0,0 + fail +ok5: + set_spr_addr ok6,lr + set_fcc 0x5 1 + fcblglr fcc1,0,1 + fail +ok6: + set_spr_addr ok7,lr + set_fcc 0x6 2 + fcblglr fcc2,0,2 + fail +ok7: + set_spr_addr ok8,lr + set_fcc 0x7 3 + fcblglr fcc3,0,3 + fail +ok8: + set_spr_addr bad,lr + set_fcc 0x8 0 + fcblglr fcc0,0,0 + + set_spr_addr bad,lr + set_fcc 0x9 1 + fcblglr fcc1,0,1 + + set_spr_addr okb,lr + set_fcc 0xa 2 + fcblglr fcc2,0,2 + fail +okb: + set_spr_addr okc,lr + set_fcc 0xb 3 + fcblglr fcc3,0,3 + fail +okc: + set_spr_addr okd,lr + set_fcc 0xc 0 + fcblglr fcc0,0,0 + fail +okd: + set_spr_addr oke,lr + set_fcc 0xd 1 + fcblglr fcc1,0,1 + fail +oke: + set_spr_addr okf,lr + set_fcc 0xe 2 + fcblglr fcc2,0,2 + fail +okf: + set_spr_addr okg,lr + set_fcc 0xf 3 + fcblglr fcc3,0,3 + fail +okg: + + ; ccond is true + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x0 0 + fcblglr fcc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x1 1 + fcblglr fcc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr okj,lr + set_fcc 0x2 2 + fcblglr fcc2,1,2 + fail +okj: + set_spr_immed 1,lcr + set_spr_addr okk,lr + set_fcc 0x3 3 + fcblglr fcc3,1,3 + fail +okk: + set_spr_immed 1,lcr + set_spr_addr okl,lr + set_fcc 0x4 0 + fcblglr fcc0,1,0 + fail +okl: + set_spr_immed 1,lcr + set_spr_addr okm,lr + set_fcc 0x5 1 + fcblglr fcc1,1,1 + fail +okm: + set_spr_immed 1,lcr + set_spr_addr okn,lr + set_fcc 0x6 2 + fcblglr fcc2,1,2 + fail +okn: + set_spr_immed 1,lcr + set_spr_addr oko,lr + set_fcc 0x7 3 + fcblglr fcc3,1,3 + fail +oko: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x8 0 + fcblglr fcc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x9 1 + fcblglr fcc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr okr,lr + set_fcc 0xa 2 + fcblglr fcc2,1,2 + fail +okr: + set_spr_immed 1,lcr + set_spr_addr oks,lr + set_fcc 0xb 3 + fcblglr fcc3,1,3 + fail +oks: + set_spr_immed 1,lcr + set_spr_addr okt,lr + set_fcc 0xc 0 + fcblglr fcc0,1,0 + fail +okt: + set_spr_immed 1,lcr + set_spr_addr oku,lr + set_fcc 0xd 1 + fcblglr fcc1,1,1 + fail +oku: + set_spr_immed 1,lcr + set_spr_addr okv,lr + set_fcc 0xe 2 + fcblglr fcc2,1,2 + fail +okv: + set_spr_immed 1,lcr + set_spr_addr okw,lr + set_fcc 0xf 3 + fcblglr fcc3,1,3 + fail +okw: + ; ccond is false + set_spr_immed 128,lcr + + set_fcc 0x0 0 + fcblglr fcc0,1,0 + set_fcc 0x1 1 + fcblglr fcc1,1,1 + set_fcc 0x2 2 + fcblglr fcc2,1,2 + set_fcc 0x3 3 + fcblglr fcc3,1,3 + set_fcc 0x4 0 + fcblglr fcc0,1,0 + set_fcc 0x5 1 + fcblglr fcc1,1,1 + set_fcc 0x6 2 + fcblglr fcc2,1,2 + set_fcc 0x7 3 + fcblglr fcc3,1,3 + set_fcc 0x8 0 + fcblglr fcc0,1,0 + set_fcc 0x9 1 + fcblglr fcc1,1,1 + set_fcc 0xa 2 + fcblglr fcc2,1,2 + set_fcc 0xb 3 + fcblglr fcc3,1,3 + set_fcc 0xc 0 + fcblglr fcc0,1,0 + set_fcc 0xd 1 + fcblglr fcc1,1,1 + set_fcc 0xe 2 + fcblglr fcc2,1,2 + set_fcc 0xf 3 + fcblglr fcc3,1,3 + + ; ccond is false + set_spr_immed 1,lcr + set_fcc 0x0 0 + fcblglr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x1 1 + fcblglr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0x2 2 + fcblglr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0x3 3 + fcblglr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0x4 0 + fcblglr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x5 1 + fcblglr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0x6 2 + fcblglr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0x7 3 + fcblglr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0x8 0 + fcblglr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x9 1 + fcblglr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0xa 2 + fcblglr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0xb 3 + fcblglr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0xc 0 + fcblglr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0xd 1 + fcblglr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0xe 2 + fcblglr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0xf 3 + fcblglr fcc3,0,3 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/fcbltlr.cgs b/sim/testsuite/sim/frv/fcbltlr.cgs new file mode 100644 index 0000000..d15dd30 --- /dev/null +++ b/sim/testsuite/sim/frv/fcbltlr.cgs @@ -0,0 +1,262 @@ +# frv testcase for fcbltlr $FCCi,$ccond,$hint +# mach: all + + .include "testutils.inc" + + start + + .global fcbltlr +fcbltlr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_fcc 0x0 0 + fcbltlr fcc0,0,0 + + set_spr_addr bad,lr + set_fcc 0x1 1 + fcbltlr fcc1,0,1 + + set_spr_addr bad,lr + set_fcc 0x2 2 + fcbltlr fcc2,0,2 + + set_spr_addr bad,lr + set_fcc 0x3 3 + fcbltlr fcc3,0,3 + + set_spr_addr ok5,lr + set_fcc 0x4 0 + fcbltlr fcc0,0,0 + fail +ok5: + set_spr_addr ok6,lr + set_fcc 0x5 1 + fcbltlr fcc1,0,1 + fail +ok6: + set_spr_addr ok7,lr + set_fcc 0x6 2 + fcbltlr fcc2,0,2 + fail +ok7: + set_spr_addr ok8,lr + set_fcc 0x7 3 + fcbltlr fcc3,0,3 + fail +ok8: + set_spr_addr bad,lr + set_fcc 0x8 0 + fcbltlr fcc0,0,0 + + set_spr_addr bad,lr + set_fcc 0x9 1 + fcbltlr fcc1,0,1 + + set_spr_addr bad,lr + set_fcc 0xa 2 + fcbltlr fcc2,0,2 + + set_spr_addr bad,lr + set_fcc 0xb 3 + fcbltlr fcc3,0,3 + + set_spr_addr okd,lr + set_fcc 0xc 0 + fcbltlr fcc0,0,0 + fail +okd: + set_spr_addr oke,lr + set_fcc 0xd 1 + fcbltlr fcc1,0,1 + fail +oke: + set_spr_addr okf,lr + set_fcc 0xe 2 + fcbltlr fcc2,0,2 + fail +okf: + set_spr_addr okg,lr + set_fcc 0xf 3 + fcbltlr fcc3,0,3 + fail +okg: + + ; ccond is true + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x0 0 + fcbltlr fcc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x1 1 + fcbltlr fcc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x2 2 + fcbltlr fcc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x3 3 + fcbltlr fcc3,1,3 + + set_spr_immed 1,lcr + set_spr_addr okl,lr + set_fcc 0x4 0 + fcbltlr fcc0,1,0 + fail +okl: + set_spr_immed 1,lcr + set_spr_addr okm,lr + set_fcc 0x5 1 + fcbltlr fcc1,1,1 + fail +okm: + set_spr_immed 1,lcr + set_spr_addr okn,lr + set_fcc 0x6 2 + fcbltlr fcc2,1,2 + fail +okn: + set_spr_immed 1,lcr + set_spr_addr oko,lr + set_fcc 0x7 3 + fcbltlr fcc3,1,3 + fail +oko: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x8 0 + fcbltlr fcc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x9 1 + fcbltlr fcc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0xa 2 + fcbltlr fcc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0xb 3 + fcbltlr fcc3,1,3 + + set_spr_immed 1,lcr + set_spr_addr okt,lr + set_fcc 0xc 0 + fcbltlr fcc0,1,0 + fail +okt: + set_spr_immed 1,lcr + set_spr_addr oku,lr + set_fcc 0xd 1 + fcbltlr fcc1,1,1 + fail +oku: + set_spr_immed 1,lcr + set_spr_addr okv,lr + set_fcc 0xe 2 + fcbltlr fcc2,1,2 + fail +okv: + set_spr_immed 1,lcr + set_spr_addr okw,lr + set_fcc 0xf 3 + fcbltlr fcc3,1,3 + fail +okw: + ; ccond is false + set_spr_immed 128,lcr + + set_fcc 0x0 0 + fcbltlr fcc0,1,0 + set_fcc 0x1 1 + fcbltlr fcc1,1,1 + set_fcc 0x2 2 + fcbltlr fcc2,1,2 + set_fcc 0x3 3 + fcbltlr fcc3,1,3 + set_fcc 0x4 0 + fcbltlr fcc0,1,0 + set_fcc 0x5 1 + fcbltlr fcc1,1,1 + set_fcc 0x6 2 + fcbltlr fcc2,1,2 + set_fcc 0x7 3 + fcbltlr fcc3,1,3 + set_fcc 0x8 0 + fcbltlr fcc0,1,0 + set_fcc 0x9 1 + fcbltlr fcc1,1,1 + set_fcc 0xa 2 + fcbltlr fcc2,1,2 + set_fcc 0xb 3 + fcbltlr fcc3,1,3 + set_fcc 0xc 0 + fcbltlr fcc0,1,0 + set_fcc 0xd 1 + fcbltlr fcc1,1,1 + set_fcc 0xe 2 + fcbltlr fcc2,1,2 + set_fcc 0xf 3 + fcbltlr fcc3,1,3 + + ; ccond is false + set_spr_immed 1,lcr + set_fcc 0x0 0 + fcbltlr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x1 1 + fcbltlr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0x2 2 + fcbltlr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0x3 3 + fcbltlr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0x4 0 + fcbltlr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x5 1 + fcbltlr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0x6 2 + fcbltlr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0x7 3 + fcbltlr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0x8 0 + fcbltlr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x9 1 + fcbltlr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0xa 2 + fcbltlr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0xb 3 + fcbltlr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0xc 0 + fcbltlr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0xd 1 + fcbltlr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0xe 2 + fcbltlr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0xf 3 + fcbltlr fcc3,0,3 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/fcbnelr.cgs b/sim/testsuite/sim/frv/fcbnelr.cgs new file mode 100644 index 0000000..cb0aa26 --- /dev/null +++ b/sim/testsuite/sim/frv/fcbnelr.cgs @@ -0,0 +1,274 @@ +# frv testcase for fcbnelr $FCCi,$ccond,$hint +# mach: all + + .include "testutils.inc" + + start + + .global fcbnelr +fcbnelr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_fcc 0x0 0 + fcbnelr fcc0,0,0 + + set_spr_addr ok2,lr + set_fcc 0x1 1 + fcbnelr fcc1,0,1 + fail +ok2: + set_spr_addr ok3,lr + set_fcc 0x2 2 + fcbnelr fcc2,0,2 + fail +ok3: + set_spr_addr ok4,lr + set_fcc 0x3 3 + fcbnelr fcc3,0,3 + fail +ok4: + set_spr_addr ok5,lr + set_fcc 0x4 0 + fcbnelr fcc0,0,0 + fail +ok5: + set_spr_addr ok6,lr + set_fcc 0x5 1 + fcbnelr fcc1,0,1 + fail +ok6: + set_spr_addr ok7,lr + set_fcc 0x6 2 + fcbnelr fcc2,0,2 + fail +ok7: + set_spr_addr ok8,lr + set_fcc 0x7 3 + fcbnelr fcc3,0,3 + fail +ok8: + set_spr_addr bad,lr + set_fcc 0x8 0 + fcbnelr fcc0,0,0 + + set_spr_addr oka,lr + set_fcc 0x9 1 + fcbnelr fcc1,0,1 + fail +oka: + set_spr_addr okb,lr + set_fcc 0xa 2 + fcbnelr fcc2,0,2 + fail +okb: + set_spr_addr okc,lr + set_fcc 0xb 3 + fcbnelr fcc3,0,3 + fail +okc: + set_spr_addr okd,lr + set_fcc 0xc 0 + fcbnelr fcc0,0,0 + fail +okd: + set_spr_addr oke,lr + set_fcc 0xd 1 + fcbnelr fcc1,0,1 + fail +oke: + set_spr_addr okf,lr + set_fcc 0xe 2 + fcbnelr fcc2,0,2 + fail +okf: + set_spr_addr okg,lr + set_fcc 0xf 3 + fcbnelr fcc3,0,3 + fail +okg: + + ; ccond is true + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x0 0 + fcbnelr fcc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr oki,lr + set_fcc 0x1 1 + fcbnelr fcc1,1,1 + fail +oki: + set_spr_immed 1,lcr + set_spr_addr okj,lr + set_fcc 0x2 2 + fcbnelr fcc2,1,2 + fail +okj: + set_spr_immed 1,lcr + set_spr_addr okk,lr + set_fcc 0x3 3 + fcbnelr fcc3,1,3 + fail +okk: + set_spr_immed 1,lcr + set_spr_addr okl,lr + set_fcc 0x4 0 + fcbnelr fcc0,1,0 + fail +okl: + set_spr_immed 1,lcr + set_spr_addr okm,lr + set_fcc 0x5 1 + fcbnelr fcc1,1,1 + fail +okm: + set_spr_immed 1,lcr + set_spr_addr okn,lr + set_fcc 0x6 2 + fcbnelr fcc2,1,2 + fail +okn: + set_spr_immed 1,lcr + set_spr_addr oko,lr + set_fcc 0x7 3 + fcbnelr fcc3,1,3 + fail +oko: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x8 0 + fcbnelr fcc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr okq,lr + set_fcc 0x9 1 + fcbnelr fcc1,1,1 + fail +okq: + set_spr_immed 1,lcr + set_spr_addr okr,lr + set_fcc 0xa 2 + fcbnelr fcc2,1,2 + fail +okr: + set_spr_immed 1,lcr + set_spr_addr oks,lr + set_fcc 0xb 3 + fcbnelr fcc3,1,3 + fail +oks: + set_spr_immed 1,lcr + set_spr_addr okt,lr + set_fcc 0xc 0 + fcbnelr fcc0,1,0 + fail +okt: + set_spr_immed 1,lcr + set_spr_addr oku,lr + set_fcc 0xd 1 + fcbnelr fcc1,1,1 + fail +oku: + set_spr_immed 1,lcr + set_spr_addr okv,lr + set_fcc 0xe 2 + fcbnelr fcc2,1,2 + fail +okv: + set_spr_immed 1,lcr + set_spr_addr okw,lr + set_fcc 0xf 3 + fcbnelr fcc3,1,3 + fail +okw: + ; ccond is false + set_spr_immed 128,lcr + + set_fcc 0x0 0 + fcbnelr fcc0,1,0 + set_fcc 0x1 1 + fcbnelr fcc1,1,1 + set_fcc 0x2 2 + fcbnelr fcc2,1,2 + set_fcc 0x3 3 + fcbnelr fcc3,1,3 + set_fcc 0x4 0 + fcbnelr fcc0,1,0 + set_fcc 0x5 1 + fcbnelr fcc1,1,1 + set_fcc 0x6 2 + fcbnelr fcc2,1,2 + set_fcc 0x7 3 + fcbnelr fcc3,1,3 + set_fcc 0x8 0 + fcbnelr fcc0,1,0 + set_fcc 0x9 1 + fcbnelr fcc1,1,1 + set_fcc 0xa 2 + fcbnelr fcc2,1,2 + set_fcc 0xb 3 + fcbnelr fcc3,1,3 + set_fcc 0xc 0 + fcbnelr fcc0,1,0 + set_fcc 0xd 1 + fcbnelr fcc1,1,1 + set_fcc 0xe 2 + fcbnelr fcc2,1,2 + set_fcc 0xf 3 + fcbnelr fcc3,1,3 + + ; ccond is false + set_spr_immed 1,lcr + set_fcc 0x0 0 + fcbnelr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x1 1 + fcbnelr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0x2 2 + fcbnelr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0x3 3 + fcbnelr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0x4 0 + fcbnelr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x5 1 + fcbnelr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0x6 2 + fcbnelr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0x7 3 + fcbnelr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0x8 0 + fcbnelr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x9 1 + fcbnelr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0xa 2 + fcbnelr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0xb 3 + fcbnelr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0xc 0 + fcbnelr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0xd 1 + fcbnelr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0xe 2 + fcbnelr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0xf 3 + fcbnelr fcc3,0,3 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/fcbnolr.cgs b/sim/testsuite/sim/frv/fcbnolr.cgs new file mode 100644 index 0000000..3c1b73a --- /dev/null +++ b/sim/testsuite/sim/frv/fcbnolr.cgs @@ -0,0 +1,185 @@ +# frv testcase for fcbnolr +# mach: all + + .include "testutils.inc" + + start + + .global fcbnolr +fcbnolr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr bad,lr + + set_fcc 0x0 0 + fcbnolr + set_fcc 0x1 1 + fcbnolr + set_fcc 0x2 2 + fcbnolr + set_fcc 0x3 3 + fcbnolr + set_fcc 0x4 0 + fcbnolr + set_fcc 0x5 1 + fcbnolr + set_fcc 0x6 2 + fcbnolr + set_fcc 0x7 3 + fcbnolr + set_fcc 0x8 0 + fcbnolr + set_fcc 0x9 1 + fcbnolr + set_fcc 0xa 2 + fcbnolr + set_fcc 0xb 3 + fcbnolr + set_fcc 0xc 0 + fcbnolr + set_fcc 0xd 1 + fcbnolr + set_fcc 0xe 2 + fcbnolr + set_fcc 0xf 3 + fcbnolr + + ; ccond is true + set_spr_immed 1,lcr + set_fcc 0x0 0 + fcbnolr + set_spr_immed 1,lcr + set_fcc 0x1 1 + fcbnolr + set_spr_immed 1,lcr + set_fcc 0x2 2 + fcbnolr + set_spr_immed 1,lcr + set_fcc 0x3 3 + fcbnolr + set_spr_immed 1,lcr + set_fcc 0x4 0 + fcbnolr + set_spr_immed 1,lcr + set_fcc 0x5 1 + fcbnolr + set_spr_immed 1,lcr + set_fcc 0x6 2 + fcbnolr + set_spr_immed 1,lcr + set_fcc 0x7 3 + fcbnolr + set_spr_immed 1,lcr + set_fcc 0x8 0 + fcbnolr + set_spr_immed 1,lcr + set_fcc 0x9 1 + fcbnolr + set_spr_immed 1,lcr + set_fcc 0xa 2 + fcbnolr + set_spr_immed 1,lcr + set_fcc 0xb 3 + fcbnolr + set_spr_immed 1,lcr + set_fcc 0xc 0 + fcbnolr + set_spr_immed 1,lcr + set_fcc 0xd 1 + fcbnolr + set_spr_immed 1,lcr + set_fcc 0xe 2 + fcbnolr + set_spr_immed 1,lcr + set_fcc 0xf 3 + fcbnolr + + ; ccond is false + set_spr_immed 128,lcr + + set_fcc 0x0 0 + fcbnolr + set_fcc 0x1 1 + fcbnolr + set_fcc 0x2 2 + fcbnolr + set_fcc 0x3 3 + fcbnolr + set_fcc 0x4 0 + fcbnolr + set_fcc 0x5 1 + fcbnolr + set_fcc 0x6 2 + fcbnolr + set_fcc 0x7 3 + fcbnolr + set_fcc 0x8 0 + fcbnolr + set_fcc 0x9 1 + fcbnolr + set_fcc 0xa 2 + fcbnolr + set_fcc 0xb 3 + fcbnolr + set_fcc 0xc 0 + fcbnolr + set_fcc 0xd 1 + fcbnolr + set_fcc 0xe 2 + fcbnolr + set_fcc 0xf 3 + fcbnolr + + ; ccond is false + set_spr_immed 1,lcr + set_fcc 0x0 0 + fcbnolr + set_spr_immed 1,lcr + set_fcc 0x1 1 + fcbnolr + set_spr_immed 1,lcr + set_fcc 0x2 2 + fcbnolr + set_spr_immed 1,lcr + set_fcc 0x3 3 + fcbnolr + set_spr_immed 1,lcr + set_fcc 0x4 0 + fcbnolr + set_spr_immed 1,lcr + set_fcc 0x5 1 + fcbnolr + set_spr_immed 1,lcr + set_fcc 0x6 2 + fcbnolr + set_spr_immed 1,lcr + set_fcc 0x7 3 + fcbnolr + set_spr_immed 1,lcr + set_fcc 0x8 0 + fcbnolr + set_spr_immed 1,lcr + set_fcc 0x9 1 + fcbnolr + set_spr_immed 1,lcr + set_fcc 0xa 2 + fcbnolr + set_spr_immed 1,lcr + set_fcc 0xb 3 + fcbnolr + set_spr_immed 1,lcr + set_fcc 0xc 0 + fcbnolr + set_spr_immed 1,lcr + set_fcc 0xd 1 + fcbnolr + set_spr_immed 1,lcr + set_fcc 0xe 2 + fcbnolr + set_spr_immed 1,lcr + set_fcc 0xf 3 + fcbnolr + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/fcbolr.cgs b/sim/testsuite/sim/frv/fcbolr.cgs new file mode 100644 index 0000000..31909f1 --- /dev/null +++ b/sim/testsuite/sim/frv/fcbolr.cgs @@ -0,0 +1,274 @@ +# frv testcase for fcbolr $FCCi,$ccond,$hint +# mach: all + + .include "testutils.inc" + + start + + .global fcbolr +fcbolr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_fcc 0x0 0 + fcbolr fcc0,0,0 + + set_spr_addr bad,lr + set_fcc 0x1 1 + fcbolr fcc1,0,1 + + set_spr_addr ok3,lr + set_fcc 0x2 2 + fcbolr fcc2,0,2 + fail +ok3: + set_spr_addr ok4,lr + set_fcc 0x3 3 + fcbolr fcc3,0,3 + fail +ok4: + set_spr_addr ok5,lr + set_fcc 0x4 0 + fcbolr fcc0,0,0 + fail +ok5: + set_spr_addr ok6,lr + set_fcc 0x5 1 + fcbolr fcc1,0,1 + fail +ok6: + set_spr_addr ok7,lr + set_fcc 0x6 2 + fcbolr fcc2,0,2 + fail +ok7: + set_spr_addr ok8,lr + set_fcc 0x7 3 + fcbolr fcc3,0,3 + fail +ok8: + set_spr_addr ok9,lr + set_fcc 0x8 0 + fcbolr fcc0,0,0 + fail +ok9: + set_spr_addr oka,lr + set_fcc 0x9 1 + fcbolr fcc1,0,1 + fail +oka: + set_spr_addr okb,lr + set_fcc 0xa 2 + fcbolr fcc2,0,2 + fail +okb: + set_spr_addr okc,lr + set_fcc 0xb 3 + fcbolr fcc3,0,3 + fail +okc: + set_spr_addr okd,lr + set_fcc 0xc 0 + fcbolr fcc0,0,0 + fail +okd: + set_spr_addr oke,lr + set_fcc 0xd 1 + fcbolr fcc1,0,1 + fail +oke: + set_spr_addr okf,lr + set_fcc 0xe 2 + fcbolr fcc2,0,2 + fail +okf: + set_spr_addr okg,lr + set_fcc 0xf 3 + fcbolr fcc3,0,3 + fail +okg: + + ; ccond is true + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x0 0 + fcbolr fcc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x1 1 + fcbolr fcc1,1,1 + + set_spr_immed 1,lcr + set_spr_addr okj,lr + set_fcc 0x2 2 + fcbolr fcc2,1,2 + fail +okj: + set_spr_immed 1,lcr + set_spr_addr okk,lr + set_fcc 0x3 3 + fcbolr fcc3,1,3 + fail +okk: + set_spr_immed 1,lcr + set_spr_addr okl,lr + set_fcc 0x4 0 + fcbolr fcc0,1,0 + fail +okl: + set_spr_immed 1,lcr + set_spr_addr okm,lr + set_fcc 0x5 1 + fcbolr fcc1,1,1 + fail +okm: + set_spr_immed 1,lcr + set_spr_addr okn,lr + set_fcc 0x6 2 + fcbolr fcc2,1,2 + fail +okn: + set_spr_immed 1,lcr + set_spr_addr oko,lr + set_fcc 0x7 3 + fcbolr fcc3,1,3 + fail +oko: + set_spr_immed 1,lcr + set_spr_addr okp,lr + set_fcc 0x8 0 + fcbolr fcc0,1,0 + fail +okp: + set_spr_immed 1,lcr + set_spr_addr okq,lr + set_fcc 0x9 1 + fcbolr fcc1,1,1 + fail +okq: + set_spr_immed 1,lcr + set_spr_addr okr,lr + set_fcc 0xa 2 + fcbolr fcc2,1,2 + fail +okr: + set_spr_immed 1,lcr + set_spr_addr oks,lr + set_fcc 0xb 3 + fcbolr fcc3,1,3 + fail +oks: + set_spr_immed 1,lcr + set_spr_addr okt,lr + set_fcc 0xc 0 + fcbolr fcc0,1,0 + fail +okt: + set_spr_immed 1,lcr + set_spr_addr oku,lr + set_fcc 0xd 1 + fcbolr fcc1,1,1 + fail +oku: + set_spr_immed 1,lcr + set_spr_addr okv,lr + set_fcc 0xe 2 + fcbolr fcc2,1,2 + fail +okv: + set_spr_immed 1,lcr + set_spr_addr okw,lr + set_fcc 0xf 3 + fcbolr fcc3,1,3 + fail +okw: + ; ccond is false + set_spr_immed 128,lcr + + set_fcc 0x0 0 + fcbolr fcc0,1,0 + set_fcc 0x1 1 + fcbolr fcc1,1,1 + set_fcc 0x2 2 + fcbolr fcc2,1,2 + set_fcc 0x3 3 + fcbolr fcc3,1,3 + set_fcc 0x4 0 + fcbolr fcc0,1,0 + set_fcc 0x5 1 + fcbolr fcc1,1,1 + set_fcc 0x6 2 + fcbolr fcc2,1,2 + set_fcc 0x7 3 + fcbolr fcc3,1,3 + set_fcc 0x8 0 + fcbolr fcc0,1,0 + set_fcc 0x9 1 + fcbolr fcc1,1,1 + set_fcc 0xa 2 + fcbolr fcc2,1,2 + set_fcc 0xb 3 + fcbolr fcc3,1,3 + set_fcc 0xc 0 + fcbolr fcc0,1,0 + set_fcc 0xd 1 + fcbolr fcc1,1,1 + set_fcc 0xe 2 + fcbolr fcc2,1,2 + set_fcc 0xf 3 + fcbolr fcc3,1,3 + + ; ccond is false + set_spr_immed 1,lcr + set_fcc 0x0 0 + fcbolr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x1 1 + fcbolr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0x2 2 + fcbolr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0x3 3 + fcbolr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0x4 0 + fcbolr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x5 1 + fcbolr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0x6 2 + fcbolr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0x7 3 + fcbolr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0x8 0 + fcbolr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x9 1 + fcbolr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0xa 2 + fcbolr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0xb 3 + fcbolr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0xc 0 + fcbolr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0xd 1 + fcbolr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0xe 2 + fcbolr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0xf 3 + fcbolr fcc3,0,3 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/fcbralr.cgs b/sim/testsuite/sim/frv/fcbralr.cgs new file mode 100644 index 0000000..60359d8 --- /dev/null +++ b/sim/testsuite/sim/frv/fcbralr.cgs @@ -0,0 +1,276 @@ +# frv testcase for fcbralr $ccond +# mach: all + + .include "testutils.inc" + + start + + .global fcbralr +fcbralr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr ok1,lr + set_fcc 0x0 0 + fcbralr 0 + fail +ok1: + set_spr_addr ok2,lr + set_fcc 0x1 1 + fcbralr 0 + fail +ok2: + set_spr_addr ok3,lr + set_fcc 0x2 2 + fcbralr 0 + fail +ok3: + set_spr_addr ok4,lr + set_fcc 0x3 3 + fcbralr 0 + fail +ok4: + set_spr_addr ok5,lr + set_fcc 0x4 0 + fcbralr 0 + fail +ok5: + set_spr_addr ok6,lr + set_fcc 0x5 1 + fcbralr 0 + fail +ok6: + set_spr_addr ok7,lr + set_fcc 0x6 2 + fcbralr 0 + fail +ok7: + set_spr_addr ok8,lr + set_fcc 0x7 3 + fcbralr 0 + fail +ok8: + set_spr_addr ok9,lr + set_fcc 0x8 0 + fcbralr 0 + fail +ok9: + set_spr_addr oka,lr + set_fcc 0x9 1 + fcbralr 0 + fail +oka: + set_spr_addr okb,lr + set_fcc 0xa 2 + fcbralr 0 + fail +okb: + set_spr_addr okc,lr + set_fcc 0xb 3 + fcbralr 0 + fail +okc: + set_spr_addr okd,lr + set_fcc 0xc 0 + fcbralr 0 + fail +okd: + set_spr_addr oke,lr + set_fcc 0xd 1 + fcbralr 0 + fail +oke: + set_spr_addr okf,lr + set_fcc 0xe 2 + fcbralr 0 + fail +okf: + set_spr_addr okg,lr + set_fcc 0xf 3 + fcbralr 0 + fail +okg: + + ; ccond is true + set_spr_immed 1,lcr + set_spr_addr okh,lr + set_fcc 0x0 0 + fcbralr 1 + fail +okh: + set_spr_immed 1,lcr + set_spr_addr oki,lr + set_fcc 0x1 1 + fcbralr 1 + fail +oki: + set_spr_immed 1,lcr + set_spr_addr okj,lr + set_fcc 0x2 2 + fcbralr 1 + fail +okj: + set_spr_immed 1,lcr + set_spr_addr okk,lr + set_fcc 0x3 3 + fcbralr 1 + fail +okk: + set_spr_immed 1,lcr + set_spr_addr okl,lr + set_fcc 0x4 0 + fcbralr 1 + fail +okl: + set_spr_immed 1,lcr + set_spr_addr okm,lr + set_fcc 0x5 1 + fcbralr 1 + fail +okm: + set_spr_immed 1,lcr + set_spr_addr okn,lr + set_fcc 0x6 2 + fcbralr 1 + fail +okn: + set_spr_immed 1,lcr + set_spr_addr oko,lr + set_fcc 0x7 3 + fcbralr 1 + fail +oko: + set_spr_immed 1,lcr + set_spr_addr okp,lr + set_fcc 0x8 0 + fcbralr 1 + fail +okp: + set_spr_immed 1,lcr + set_spr_addr okq,lr + set_fcc 0x9 1 + fcbralr 1 + fail +okq: + set_spr_immed 1,lcr + set_spr_addr okr,lr + set_fcc 0xa 2 + fcbralr 1 + fail +okr: + set_spr_immed 1,lcr + set_spr_addr oks,lr + set_fcc 0xb 3 + fcbralr 1 + fail +oks: + set_spr_immed 1,lcr + set_spr_addr okt,lr + set_fcc 0xc 0 + fcbralr 1 + fail +okt: + set_spr_immed 1,lcr + set_spr_addr oku,lr + set_fcc 0xd 1 + fcbralr 1 + fail +oku: + set_spr_immed 1,lcr + set_spr_addr okv,lr + set_fcc 0xe 2 + fcbralr 1 + fail +okv: + set_spr_immed 1,lcr + set_spr_addr okw,lr + set_fcc 0xf 3 + fcbralr 1 + fail +okw: + ; ccond is false + set_spr_immed 128,lcr + + set_fcc 0x0 0 + fcbralr 1 + set_fcc 0x1 1 + fcbralr 1 + set_fcc 0x2 2 + fcbralr 1 + set_fcc 0x3 3 + fcbralr 1 + set_fcc 0x4 0 + fcbralr 1 + set_fcc 0x5 1 + fcbralr 1 + set_fcc 0x6 2 + fcbralr 1 + set_fcc 0x7 3 + fcbralr 1 + set_fcc 0x8 0 + fcbralr 1 + set_fcc 0x9 1 + fcbralr 1 + set_fcc 0xa 2 + fcbralr 1 + set_fcc 0xb 3 + fcbralr 1 + set_fcc 0xc 0 + fcbralr 1 + set_fcc 0xd 1 + fcbralr 1 + set_fcc 0xe 2 + fcbralr 1 + set_fcc 0xf 3 + fcbralr 1 + + ; ccond is false + set_spr_immed 1,lcr + set_fcc 0x0 0 + fcbralr 0 + set_spr_immed 1,lcr + set_fcc 0x1 1 + fcbralr 0 + set_spr_immed 1,lcr + set_fcc 0x2 2 + fcbralr 0 + set_spr_immed 1,lcr + set_fcc 0x3 3 + fcbralr 0 + set_spr_immed 1,lcr + set_fcc 0x4 0 + fcbralr 0 + set_spr_immed 1,lcr + set_fcc 0x5 1 + fcbralr 0 + set_spr_immed 1,lcr + set_fcc 0x6 2 + fcbralr 0 + set_spr_immed 1,lcr + set_fcc 0x7 3 + fcbralr 0 + set_spr_immed 1,lcr + set_fcc 0x8 0 + fcbralr 0 + set_spr_immed 1,lcr + set_fcc 0x9 1 + fcbralr 0 + set_spr_immed 1,lcr + set_fcc 0xa 2 + fcbralr 0 + set_spr_immed 1,lcr + set_fcc 0xb 3 + fcbralr 0 + set_spr_immed 1,lcr + set_fcc 0xc 0 + fcbralr 0 + set_spr_immed 1,lcr + set_fcc 0xd 1 + fcbralr 0 + set_spr_immed 1,lcr + set_fcc 0xe 2 + fcbralr 0 + set_spr_immed 1,lcr + set_fcc 0xf 3 + fcbralr 0 + + pass diff --git a/sim/testsuite/sim/frv/fcbuelr.cgs b/sim/testsuite/sim/frv/fcbuelr.cgs new file mode 100644 index 0000000..e102ee3 --- /dev/null +++ b/sim/testsuite/sim/frv/fcbuelr.cgs @@ -0,0 +1,270 @@ +# frv testcase for fcbuelr $FCCi,$ccond,$hint +# mach: all + + .include "testutils.inc" + + start + + .global fcbuelr +fcbuelr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_fcc 0x0 0 + fcbuelr fcc0,0,0 + + set_spr_addr ok2,lr + set_fcc 0x1 1 + fcbuelr fcc1,0,1 + fail +ok2: + set_spr_addr bad,lr + set_fcc 0x2 2 + fcbuelr fcc2,0,2 + + set_spr_addr ok4,lr + set_fcc 0x3 3 + fcbuelr fcc3,0,3 + fail +ok4: + set_spr_addr bad,lr + set_fcc 0x4 0 + fcbuelr fcc0,0,0 + + set_spr_addr ok6,lr + set_fcc 0x5 1 + fcbuelr fcc1,0,1 + fail +ok6: + set_spr_addr bad,lr + set_fcc 0x6 2 + fcbuelr fcc2,0,2 + + set_spr_addr ok8,lr + set_fcc 0x7 3 + fcbuelr fcc3,0,3 + fail +ok8: + set_spr_addr ok9,lr + set_fcc 0x8 0 + fcbuelr fcc0,0,0 + fail +ok9: + set_spr_addr oka,lr + set_fcc 0x9 1 + fcbuelr fcc1,0,1 + fail +oka: + set_spr_addr okb,lr + set_fcc 0xa 2 + fcbuelr fcc2,0,2 + fail +okb: + set_spr_addr okc,lr + set_fcc 0xb 3 + fcbuelr fcc3,0,3 + fail +okc: + set_spr_addr okd,lr + set_fcc 0xc 0 + fcbuelr fcc0,0,0 + fail +okd: + set_spr_addr oke,lr + set_fcc 0xd 1 + fcbuelr fcc1,0,1 + fail +oke: + set_spr_addr okf,lr + set_fcc 0xe 2 + fcbuelr fcc2,0,2 + fail +okf: + set_spr_addr okg,lr + set_fcc 0xf 3 + fcbuelr fcc3,0,3 + fail +okg: + + ; ccond is true + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x0 0 + fcbuelr fcc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr oki,lr + set_fcc 0x1 1 + fcbuelr fcc1,1,1 + fail +oki: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x2 2 + fcbuelr fcc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr okk,lr + set_fcc 0x3 3 + fcbuelr fcc3,1,3 + fail +okk: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x4 0 + fcbuelr fcc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr okm,lr + set_fcc 0x5 1 + fcbuelr fcc1,1,1 + fail +okm: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x6 2 + fcbuelr fcc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr oko,lr + set_fcc 0x7 3 + fcbuelr fcc3,1,3 + fail +oko: + set_spr_immed 1,lcr + set_spr_addr okp,lr + set_fcc 0x8 0 + fcbuelr fcc0,1,0 + fail +okp: + set_spr_immed 1,lcr + set_spr_addr okq,lr + set_fcc 0x9 1 + fcbuelr fcc1,1,1 + fail +okq: + set_spr_immed 1,lcr + set_spr_addr okr,lr + set_fcc 0xa 2 + fcbuelr fcc2,1,2 + fail +okr: + set_spr_immed 1,lcr + set_spr_addr oks,lr + set_fcc 0xb 3 + fcbuelr fcc3,1,3 + fail +oks: + set_spr_immed 1,lcr + set_spr_addr okt,lr + set_fcc 0xc 0 + fcbuelr fcc0,1,0 + fail +okt: + set_spr_immed 1,lcr + set_spr_addr oku,lr + set_fcc 0xd 1 + fcbuelr fcc1,1,1 + fail +oku: + set_spr_immed 1,lcr + set_spr_addr okv,lr + set_fcc 0xe 2 + fcbuelr fcc2,1,2 + fail +okv: + set_spr_immed 1,lcr + set_spr_addr okw,lr + set_fcc 0xf 3 + fcbuelr fcc3,1,3 + fail +okw: + ; ccond is false + set_spr_immed 128,lcr + + set_fcc 0x0 0 + fcbuelr fcc0,1,0 + set_fcc 0x1 1 + fcbuelr fcc1,1,1 + set_fcc 0x2 2 + fcbuelr fcc2,1,2 + set_fcc 0x3 3 + fcbuelr fcc3,1,3 + set_fcc 0x4 0 + fcbuelr fcc0,1,0 + set_fcc 0x5 1 + fcbuelr fcc1,1,1 + set_fcc 0x6 2 + fcbuelr fcc2,1,2 + set_fcc 0x7 3 + fcbuelr fcc3,1,3 + set_fcc 0x8 0 + fcbuelr fcc0,1,0 + set_fcc 0x9 1 + fcbuelr fcc1,1,1 + set_fcc 0xa 2 + fcbuelr fcc2,1,2 + set_fcc 0xb 3 + fcbuelr fcc3,1,3 + set_fcc 0xc 0 + fcbuelr fcc0,1,0 + set_fcc 0xd 1 + fcbuelr fcc1,1,1 + set_fcc 0xe 2 + fcbuelr fcc2,1,2 + set_fcc 0xf 3 + fcbuelr fcc3,1,3 + + ; ccond is false + set_spr_immed 1,lcr + set_fcc 0x0 0 + fcbuelr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x1 1 + fcbuelr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0x2 2 + fcbuelr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0x3 3 + fcbuelr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0x4 0 + fcbuelr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x5 1 + fcbuelr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0x6 2 + fcbuelr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0x7 3 + fcbuelr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0x8 0 + fcbuelr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x9 1 + fcbuelr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0xa 2 + fcbuelr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0xb 3 + fcbuelr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0xc 0 + fcbuelr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0xd 1 + fcbuelr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0xe 2 + fcbuelr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0xf 3 + fcbuelr fcc3,0,3 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/fcbugelr.cgs b/sim/testsuite/sim/frv/fcbugelr.cgs new file mode 100644 index 0000000..8ecd141 --- /dev/null +++ b/sim/testsuite/sim/frv/fcbugelr.cgs @@ -0,0 +1,274 @@ +# frv testcase for fcbugelr $FCCi,$ccond,$hint +# mach: all + + .include "testutils.inc" + + start + + .global fcbugelr +fcbugelr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_fcc 0x0 0 + fcbugelr fcc0,0,0 + + set_spr_addr ok2,lr + set_fcc 0x1 1 + fcbugelr fcc1,0,1 + fail +ok2: + set_spr_addr ok3,lr + set_fcc 0x2 2 + fcbugelr fcc2,0,2 + fail +ok3: + set_spr_addr ok4,lr + set_fcc 0x3 3 + fcbugelr fcc3,0,3 + fail +ok4: + set_spr_addr bad,lr + set_fcc 0x4 0 + fcbugelr fcc0,0,0 + + set_spr_addr ok6,lr + set_fcc 0x5 1 + fcbugelr fcc1,0,1 + fail +ok6: + set_spr_addr ok7,lr + set_fcc 0x6 2 + fcbugelr fcc2,0,2 + fail +ok7: + set_spr_addr ok8,lr + set_fcc 0x7 3 + fcbugelr fcc3,0,3 + fail +ok8: + set_spr_addr ok9,lr + set_fcc 0x8 0 + fcbugelr fcc0,0,0 + fail +ok9: + set_spr_addr oka,lr + set_fcc 0x9 1 + fcbugelr fcc1,0,1 + fail +oka: + set_spr_addr okb,lr + set_fcc 0xa 2 + fcbugelr fcc2,0,2 + fail +okb: + set_spr_addr okc,lr + set_fcc 0xb 3 + fcbugelr fcc3,0,3 + fail +okc: + set_spr_addr okd,lr + set_fcc 0xc 0 + fcbugelr fcc0,0,0 + fail +okd: + set_spr_addr oke,lr + set_fcc 0xd 1 + fcbugelr fcc1,0,1 + fail +oke: + set_spr_addr okf,lr + set_fcc 0xe 2 + fcbugelr fcc2,0,2 + fail +okf: + set_spr_addr okg,lr + set_fcc 0xf 3 + fcbugelr fcc3,0,3 + fail +okg: + + ; ccond is true + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x0 0 + fcbugelr fcc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr oki,lr + set_fcc 0x1 1 + fcbugelr fcc1,1,1 + fail +oki: + set_spr_immed 1,lcr + set_spr_addr okj,lr + set_fcc 0x2 2 + fcbugelr fcc2,1,2 + fail +okj: + set_spr_immed 1,lcr + set_spr_addr okk,lr + set_fcc 0x3 3 + fcbugelr fcc3,1,3 + fail +okk: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x4 0 + fcbugelr fcc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr okm,lr + set_fcc 0x5 1 + fcbugelr fcc1,1,1 + fail +okm: + set_spr_immed 1,lcr + set_spr_addr okn,lr + set_fcc 0x6 2 + fcbugelr fcc2,1,2 + fail +okn: + set_spr_immed 1,lcr + set_spr_addr oko,lr + set_fcc 0x7 3 + fcbugelr fcc3,1,3 + fail +oko: + set_spr_immed 1,lcr + set_spr_addr okp,lr + set_fcc 0x8 0 + fcbugelr fcc0,1,0 + fail +okp: + set_spr_immed 1,lcr + set_spr_addr okq,lr + set_fcc 0x9 1 + fcbugelr fcc1,1,1 + fail +okq: + set_spr_immed 1,lcr + set_spr_addr okr,lr + set_fcc 0xa 2 + fcbugelr fcc2,1,2 + fail +okr: + set_spr_immed 1,lcr + set_spr_addr oks,lr + set_fcc 0xb 3 + fcbugelr fcc3,1,3 + fail +oks: + set_spr_immed 1,lcr + set_spr_addr okt,lr + set_fcc 0xc 0 + fcbugelr fcc0,1,0 + fail +okt: + set_spr_immed 1,lcr + set_spr_addr oku,lr + set_fcc 0xd 1 + fcbugelr fcc1,1,1 + fail +oku: + set_spr_immed 1,lcr + set_spr_addr okv,lr + set_fcc 0xe 2 + fcbugelr fcc2,1,2 + fail +okv: + set_spr_immed 1,lcr + set_spr_addr okw,lr + set_fcc 0xf 3 + fcbugelr fcc3,1,3 + fail +okw: + ; ccond is false + set_spr_immed 128,lcr + + set_fcc 0x0 0 + fcbugelr fcc0,1,0 + set_fcc 0x1 1 + fcbugelr fcc1,1,1 + set_fcc 0x2 2 + fcbugelr fcc2,1,2 + set_fcc 0x3 3 + fcbugelr fcc3,1,3 + set_fcc 0x4 0 + fcbugelr fcc0,1,0 + set_fcc 0x5 1 + fcbugelr fcc1,1,1 + set_fcc 0x6 2 + fcbugelr fcc2,1,2 + set_fcc 0x7 3 + fcbugelr fcc3,1,3 + set_fcc 0x8 0 + fcbugelr fcc0,1,0 + set_fcc 0x9 1 + fcbugelr fcc1,1,1 + set_fcc 0xa 2 + fcbugelr fcc2,1,2 + set_fcc 0xb 3 + fcbugelr fcc3,1,3 + set_fcc 0xc 0 + fcbugelr fcc0,1,0 + set_fcc 0xd 1 + fcbugelr fcc1,1,1 + set_fcc 0xe 2 + fcbugelr fcc2,1,2 + set_fcc 0xf 3 + fcbugelr fcc3,1,3 + + ; ccond is false + set_spr_immed 1,lcr + set_fcc 0x0 0 + fcbugelr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x1 1 + fcbugelr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0x2 2 + fcbugelr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0x3 3 + fcbugelr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0x4 0 + fcbugelr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x5 1 + fcbugelr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0x6 2 + fcbugelr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0x7 3 + fcbugelr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0x8 0 + fcbugelr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x9 1 + fcbugelr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0xa 2 + fcbugelr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0xb 3 + fcbugelr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0xc 0 + fcbugelr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0xd 1 + fcbugelr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0xe 2 + fcbugelr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0xf 3 + fcbugelr fcc3,0,3 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/fcbuglr.cgs b/sim/testsuite/sim/frv/fcbuglr.cgs new file mode 100644 index 0000000..d9470a8 --- /dev/null +++ b/sim/testsuite/sim/frv/fcbuglr.cgs @@ -0,0 +1,270 @@ +# frv testcase for fcbuglr $FCCi,$ccond,$hint +# mach: all + + .include "testutils.inc" + + start + + .global fcbuglr +fcbuglr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_fcc 0x0 0 + fcbuglr fcc0,0,0 + + set_spr_addr ok2,lr + set_fcc 0x1 1 + fcbuglr fcc1,0,1 + fail +ok2: + set_spr_addr ok3,lr + set_fcc 0x2 2 + fcbuglr fcc2,0,2 + fail +ok3: + set_spr_addr ok4,lr + set_fcc 0x3 3 + fcbuglr fcc3,0,3 + fail +ok4: + set_spr_addr bad,lr + set_fcc 0x4 0 + fcbuglr fcc0,0,0 + + set_spr_addr ok6,lr + set_fcc 0x5 1 + fcbuglr fcc1,0,1 + fail +ok6: + set_spr_addr ok7,lr + set_fcc 0x6 2 + fcbuglr fcc2,0,2 + fail +ok7: + set_spr_addr ok8,lr + set_fcc 0x7 3 + fcbuglr fcc3,0,3 + fail +ok8: + set_spr_addr bad,lr + set_fcc 0x8 0 + fcbuglr fcc0,0,0 + + set_spr_addr oka,lr + set_fcc 0x9 1 + fcbuglr fcc1,0,1 + fail +oka: + set_spr_addr okb,lr + set_fcc 0xa 2 + fcbuglr fcc2,0,2 + fail +okb: + set_spr_addr okc,lr + set_fcc 0xb 3 + fcbuglr fcc3,0,3 + fail +okc: + set_spr_addr bad,lr + set_fcc 0xc 0 + fcbuglr fcc0,0,0 + + set_spr_addr oke,lr + set_fcc 0xd 1 + fcbuglr fcc1,0,1 + fail +oke: + set_spr_addr okf,lr + set_fcc 0xe 2 + fcbuglr fcc2,0,2 + fail +okf: + set_spr_addr okg,lr + set_fcc 0xf 3 + fcbuglr fcc3,0,3 + fail +okg: + + ; ccond is true + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x0 0 + fcbuglr fcc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr oki,lr + set_fcc 0x1 1 + fcbuglr fcc1,1,1 + fail +oki: + set_spr_immed 1,lcr + set_spr_addr okj,lr + set_fcc 0x2 2 + fcbuglr fcc2,1,2 + fail +okj: + set_spr_immed 1,lcr + set_spr_addr okk,lr + set_fcc 0x3 3 + fcbuglr fcc3,1,3 + fail +okk: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x4 0 + fcbuglr fcc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr okm,lr + set_fcc 0x5 1 + fcbuglr fcc1,1,1 + fail +okm: + set_spr_immed 1,lcr + set_spr_addr okn,lr + set_fcc 0x6 2 + fcbuglr fcc2,1,2 + fail +okn: + set_spr_immed 1,lcr + set_spr_addr oko,lr + set_fcc 0x7 3 + fcbuglr fcc3,1,3 + fail +oko: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x8 0 + fcbuglr fcc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr okq,lr + set_fcc 0x9 1 + fcbuglr fcc1,1,1 + fail +okq: + set_spr_immed 1,lcr + set_spr_addr okr,lr + set_fcc 0xa 2 + fcbuglr fcc2,1,2 + fail +okr: + set_spr_immed 1,lcr + set_spr_addr oks,lr + set_fcc 0xb 3 + fcbuglr fcc3,1,3 + fail +oks: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0xc 0 + fcbuglr fcc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr oku,lr + set_fcc 0xd 1 + fcbuglr fcc1,1,1 + fail +oku: + set_spr_immed 1,lcr + set_spr_addr okv,lr + set_fcc 0xe 2 + fcbuglr fcc2,1,2 + fail +okv: + set_spr_immed 1,lcr + set_spr_addr okw,lr + set_fcc 0xf 3 + fcbuglr fcc3,1,3 + fail +okw: + ; ccond is false + set_spr_immed 128,lcr + + set_fcc 0x0 0 + fcbuglr fcc0,1,0 + set_fcc 0x1 1 + fcbuglr fcc1,1,1 + set_fcc 0x2 2 + fcbuglr fcc2,1,2 + set_fcc 0x3 3 + fcbuglr fcc3,1,3 + set_fcc 0x4 0 + fcbuglr fcc0,1,0 + set_fcc 0x5 1 + fcbuglr fcc1,1,1 + set_fcc 0x6 2 + fcbuglr fcc2,1,2 + set_fcc 0x7 3 + fcbuglr fcc3,1,3 + set_fcc 0x8 0 + fcbuglr fcc0,1,0 + set_fcc 0x9 1 + fcbuglr fcc1,1,1 + set_fcc 0xa 2 + fcbuglr fcc2,1,2 + set_fcc 0xb 3 + fcbuglr fcc3,1,3 + set_fcc 0xc 0 + fcbuglr fcc0,1,0 + set_fcc 0xd 1 + fcbuglr fcc1,1,1 + set_fcc 0xe 2 + fcbuglr fcc2,1,2 + set_fcc 0xf 3 + fcbuglr fcc3,1,3 + + ; ccond is false + set_spr_immed 1,lcr + set_fcc 0x0 0 + fcbuglr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x1 1 + fcbuglr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0x2 2 + fcbuglr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0x3 3 + fcbuglr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0x4 0 + fcbuglr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x5 1 + fcbuglr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0x6 2 + fcbuglr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0x7 3 + fcbuglr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0x8 0 + fcbuglr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x9 1 + fcbuglr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0xa 2 + fcbuglr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0xb 3 + fcbuglr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0xc 0 + fcbuglr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0xd 1 + fcbuglr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0xe 2 + fcbuglr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0xf 3 + fcbuglr fcc3,0,3 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/fcbulelr.cgs b/sim/testsuite/sim/frv/fcbulelr.cgs new file mode 100644 index 0000000..3f1da04 --- /dev/null +++ b/sim/testsuite/sim/frv/fcbulelr.cgs @@ -0,0 +1,274 @@ +# frv testcase for fcbulelr $FCCi,$ccond,$hint +# mach: all + + .include "testutils.inc" + + start + + .global fcbulelr +fcbulelr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_fcc 0x0 0 + fcbulelr fcc0,0,0 + + set_spr_addr ok2,lr + set_fcc 0x1 1 + fcbulelr fcc1,0,1 + fail +ok2: + set_spr_addr bad,lr + set_fcc 0x2 2 + fcbulelr fcc2,0,2 + + set_spr_addr ok4,lr + set_fcc 0x3 3 + fcbulelr fcc3,0,3 + fail +ok4: + set_spr_addr ok5,lr + set_fcc 0x4 0 + fcbulelr fcc0,0,0 + fail +ok5: + set_spr_addr ok6,lr + set_fcc 0x5 1 + fcbulelr fcc1,0,1 + fail +ok6: + set_spr_addr ok7,lr + set_fcc 0x6 2 + fcbulelr fcc2,0,2 + fail +ok7: + set_spr_addr ok8,lr + set_fcc 0x7 3 + fcbulelr fcc3,0,3 + fail +ok8: + set_spr_addr ok9,lr + set_fcc 0x8 0 + fcbulelr fcc0,0,0 + fail +ok9: + set_spr_addr oka,lr + set_fcc 0x9 1 + fcbulelr fcc1,0,1 + fail +oka: + set_spr_addr okb,lr + set_fcc 0xa 2 + fcbulelr fcc2,0,2 + fail +okb: + set_spr_addr okc,lr + set_fcc 0xb 3 + fcbulelr fcc3,0,3 + fail +okc: + set_spr_addr okd,lr + set_fcc 0xc 0 + fcbulelr fcc0,0,0 + fail +okd: + set_spr_addr oke,lr + set_fcc 0xd 1 + fcbulelr fcc1,0,1 + fail +oke: + set_spr_addr okf,lr + set_fcc 0xe 2 + fcbulelr fcc2,0,2 + fail +okf: + set_spr_addr okg,lr + set_fcc 0xf 3 + fcbulelr fcc3,0,3 + fail +okg: + + ; ccond is true + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x0 0 + fcbulelr fcc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr oki,lr + set_fcc 0x1 1 + fcbulelr fcc1,1,1 + fail +oki: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x2 2 + fcbulelr fcc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr okk,lr + set_fcc 0x3 3 + fcbulelr fcc3,1,3 + fail +okk: + set_spr_immed 1,lcr + set_spr_addr okl,lr + set_fcc 0x4 0 + fcbulelr fcc0,1,0 + fail +okl: + set_spr_immed 1,lcr + set_spr_addr okm,lr + set_fcc 0x5 1 + fcbulelr fcc1,1,1 + fail +okm: + set_spr_immed 1,lcr + set_spr_addr okn,lr + set_fcc 0x6 2 + fcbulelr fcc2,1,2 + fail +okn: + set_spr_immed 1,lcr + set_spr_addr oko,lr + set_fcc 0x7 3 + fcbulelr fcc3,1,3 + fail +oko: + set_spr_immed 1,lcr + set_spr_addr okp,lr + set_fcc 0x8 0 + fcbulelr fcc0,1,0 + fail +okp: + set_spr_immed 1,lcr + set_spr_addr okq,lr + set_fcc 0x9 1 + fcbulelr fcc1,1,1 + fail +okq: + set_spr_immed 1,lcr + set_spr_addr okr,lr + set_fcc 0xa 2 + fcbulelr fcc2,1,2 + fail +okr: + set_spr_immed 1,lcr + set_spr_addr oks,lr + set_fcc 0xb 3 + fcbulelr fcc3,1,3 + fail +oks: + set_spr_immed 1,lcr + set_spr_addr okt,lr + set_fcc 0xc 0 + fcbulelr fcc0,1,0 + fail +okt: + set_spr_immed 1,lcr + set_spr_addr oku,lr + set_fcc 0xd 1 + fcbulelr fcc1,1,1 + fail +oku: + set_spr_immed 1,lcr + set_spr_addr okv,lr + set_fcc 0xe 2 + fcbulelr fcc2,1,2 + fail +okv: + set_spr_immed 1,lcr + set_spr_addr okw,lr + set_fcc 0xf 3 + fcbulelr fcc3,1,3 + fail +okw: + ; ccond is false + set_spr_immed 128,lcr + + set_fcc 0x0 0 + fcbulelr fcc0,1,0 + set_fcc 0x1 1 + fcbulelr fcc1,1,1 + set_fcc 0x2 2 + fcbulelr fcc2,1,2 + set_fcc 0x3 3 + fcbulelr fcc3,1,3 + set_fcc 0x4 0 + fcbulelr fcc0,1,0 + set_fcc 0x5 1 + fcbulelr fcc1,1,1 + set_fcc 0x6 2 + fcbulelr fcc2,1,2 + set_fcc 0x7 3 + fcbulelr fcc3,1,3 + set_fcc 0x8 0 + fcbulelr fcc0,1,0 + set_fcc 0x9 1 + fcbulelr fcc1,1,1 + set_fcc 0xa 2 + fcbulelr fcc2,1,2 + set_fcc 0xb 3 + fcbulelr fcc3,1,3 + set_fcc 0xc 0 + fcbulelr fcc0,1,0 + set_fcc 0xd 1 + fcbulelr fcc1,1,1 + set_fcc 0xe 2 + fcbulelr fcc2,1,2 + set_fcc 0xf 3 + fcbulelr fcc3,1,3 + + ; ccond is false + set_spr_immed 1,lcr + set_fcc 0x0 0 + fcbulelr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x1 1 + fcbulelr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0x2 2 + fcbulelr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0x3 3 + fcbulelr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0x4 0 + fcbulelr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x5 1 + fcbulelr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0x6 2 + fcbulelr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0x7 3 + fcbulelr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0x8 0 + fcbulelr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x9 1 + fcbulelr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0xa 2 + fcbulelr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0xb 3 + fcbulelr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0xc 0 + fcbulelr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0xd 1 + fcbulelr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0xe 2 + fcbulelr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0xf 3 + fcbulelr fcc3,0,3 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/fcbullr.cgs b/sim/testsuite/sim/frv/fcbullr.cgs new file mode 100644 index 0000000..1a87dde --- /dev/null +++ b/sim/testsuite/sim/frv/fcbullr.cgs @@ -0,0 +1,270 @@ +# frv testcase for fcbullr $FCCi,$ccond,$hint +# mach: all + + .include "testutils.inc" + + start + + .global fcbullr +fcbullr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_fcc 0x0 0 + fcbullr fcc0,0,0 + + set_spr_addr ok2,lr + set_fcc 0x1 1 + fcbullr fcc1,0,1 + fail +ok2: + set_spr_addr bad,lr + set_fcc 0x2 2 + fcbullr fcc2,0,2 + + set_spr_addr ok4,lr + set_fcc 0x3 3 + fcbullr fcc3,0,3 + fail +ok4: + set_spr_addr ok5,lr + set_fcc 0x4 0 + fcbullr fcc0,0,0 + fail +ok5: + set_spr_addr ok6,lr + set_fcc 0x5 1 + fcbullr fcc1,0,1 + fail +ok6: + set_spr_addr ok7,lr + set_fcc 0x6 2 + fcbullr fcc2,0,2 + fail +ok7: + set_spr_addr ok8,lr + set_fcc 0x7 3 + fcbullr fcc3,0,3 + fail +ok8: + set_spr_addr bad,lr + set_fcc 0x8 0 + fcbullr fcc0,0,0 + + set_spr_addr oka,lr + set_fcc 0x9 1 + fcbullr fcc1,0,1 + fail +oka: + set_spr_addr bad,lr + set_fcc 0xa 2 + fcbullr fcc2,0,2 + + set_spr_addr okc,lr + set_fcc 0xb 3 + fcbullr fcc3,0,3 + fail +okc: + set_spr_addr okd,lr + set_fcc 0xc 0 + fcbullr fcc0,0,0 + fail +okd: + set_spr_addr oke,lr + set_fcc 0xd 1 + fcbullr fcc1,0,1 + fail +oke: + set_spr_addr okf,lr + set_fcc 0xe 2 + fcbullr fcc2,0,2 + fail +okf: + set_spr_addr okg,lr + set_fcc 0xf 3 + fcbullr fcc3,0,3 + fail +okg: + + ; ccond is true + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x0 0 + fcbullr fcc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr oki,lr + set_fcc 0x1 1 + fcbullr fcc1,1,1 + fail +oki: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x2 2 + fcbullr fcc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr okk,lr + set_fcc 0x3 3 + fcbullr fcc3,1,3 + fail +okk: + set_spr_immed 1,lcr + set_spr_addr okl,lr + set_fcc 0x4 0 + fcbullr fcc0,1,0 + fail +okl: + set_spr_immed 1,lcr + set_spr_addr okm,lr + set_fcc 0x5 1 + fcbullr fcc1,1,1 + fail +okm: + set_spr_immed 1,lcr + set_spr_addr okn,lr + set_fcc 0x6 2 + fcbullr fcc2,1,2 + fail +okn: + set_spr_immed 1,lcr + set_spr_addr oko,lr + set_fcc 0x7 3 + fcbullr fcc3,1,3 + fail +oko: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x8 0 + fcbullr fcc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr okq,lr + set_fcc 0x9 1 + fcbullr fcc1,1,1 + fail +okq: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0xa 2 + fcbullr fcc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr oks,lr + set_fcc 0xb 3 + fcbullr fcc3,1,3 + fail +oks: + set_spr_immed 1,lcr + set_spr_addr okt,lr + set_fcc 0xc 0 + fcbullr fcc0,1,0 + fail +okt: + set_spr_immed 1,lcr + set_spr_addr oku,lr + set_fcc 0xd 1 + fcbullr fcc1,1,1 + fail +oku: + set_spr_immed 1,lcr + set_spr_addr okv,lr + set_fcc 0xe 2 + fcbullr fcc2,1,2 + fail +okv: + set_spr_immed 1,lcr + set_spr_addr okw,lr + set_fcc 0xf 3 + fcbullr fcc3,1,3 + fail +okw: + ; ccond is false + set_spr_immed 128,lcr + + set_fcc 0x0 0 + fcbullr fcc0,1,0 + set_fcc 0x1 1 + fcbullr fcc1,1,1 + set_fcc 0x2 2 + fcbullr fcc2,1,2 + set_fcc 0x3 3 + fcbullr fcc3,1,3 + set_fcc 0x4 0 + fcbullr fcc0,1,0 + set_fcc 0x5 1 + fcbullr fcc1,1,1 + set_fcc 0x6 2 + fcbullr fcc2,1,2 + set_fcc 0x7 3 + fcbullr fcc3,1,3 + set_fcc 0x8 0 + fcbullr fcc0,1,0 + set_fcc 0x9 1 + fcbullr fcc1,1,1 + set_fcc 0xa 2 + fcbullr fcc2,1,2 + set_fcc 0xb 3 + fcbullr fcc3,1,3 + set_fcc 0xc 0 + fcbullr fcc0,1,0 + set_fcc 0xd 1 + fcbullr fcc1,1,1 + set_fcc 0xe 2 + fcbullr fcc2,1,2 + set_fcc 0xf 3 + fcbullr fcc3,1,3 + + ; ccond is false + set_spr_immed 1,lcr + set_fcc 0x0 0 + fcbullr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x1 1 + fcbullr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0x2 2 + fcbullr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0x3 3 + fcbullr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0x4 0 + fcbullr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x5 1 + fcbullr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0x6 2 + fcbullr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0x7 3 + fcbullr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0x8 0 + fcbullr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x9 1 + fcbullr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0xa 2 + fcbullr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0xb 3 + fcbullr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0xc 0 + fcbullr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0xd 1 + fcbullr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0xe 2 + fcbullr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0xf 3 + fcbullr fcc3,0,3 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/fcbulr.cgs b/sim/testsuite/sim/frv/fcbulr.cgs new file mode 100644 index 0000000..c81dff3 --- /dev/null +++ b/sim/testsuite/sim/frv/fcbulr.cgs @@ -0,0 +1,262 @@ +# frv testcase for fcbulr $FCCi,$ccond,$hint +# mach: all + + .include "testutils.inc" + + start + + .global fcbulr +fcbulr: + ; ccond is true + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_fcc 0x0 0 + fcbulr fcc0,0,0 + + set_spr_addr ok2,lr + set_fcc 0x1 1 + fcbulr fcc1,0,1 + fail +ok2: + set_spr_addr bad,lr + set_fcc 0x2 2 + fcbulr fcc2,0,2 + + set_spr_addr ok4,lr + set_fcc 0x3 3 + fcbulr fcc3,0,3 + fail +ok4: + set_spr_addr bad,lr + set_fcc 0x4 0 + fcbulr fcc0,0,0 + + set_spr_addr ok6,lr + set_fcc 0x5 1 + fcbulr fcc1,0,1 + fail +ok6: + set_spr_addr bad,lr + set_fcc 0x6 2 + fcbulr fcc2,0,2 + + set_spr_addr ok8,lr + set_fcc 0x7 3 + fcbulr fcc3,0,3 + fail +ok8: + set_spr_addr bad,lr + set_fcc 0x8 0 + fcbulr fcc0,0,0 + + set_spr_addr oka,lr + set_fcc 0x9 1 + fcbulr fcc1,0,1 + fail +oka: + set_spr_addr bad,lr + set_fcc 0xa 2 + fcbulr fcc2,0,2 + + set_spr_addr okc,lr + set_fcc 0xb 3 + fcbulr fcc3,0,3 + fail +okc: + set_spr_addr bad,lr + set_fcc 0xc 0 + fcbulr fcc0,0,0 + + set_spr_addr oke,lr + set_fcc 0xd 1 + fcbulr fcc1,0,1 + fail +oke: + set_spr_addr bad,lr + set_fcc 0xe 2 + fcbulr fcc2,0,2 + + set_spr_addr okg,lr + set_fcc 0xf 3 + fcbulr fcc3,0,3 + fail +okg: + + ; ccond is true + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x0 0 + fcbulr fcc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr oki,lr + set_fcc 0x1 1 + fcbulr fcc1,1,1 + fail +oki: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x2 2 + fcbulr fcc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr okk,lr + set_fcc 0x3 3 + fcbulr fcc3,1,3 + fail +okk: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x4 0 + fcbulr fcc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr okm,lr + set_fcc 0x5 1 + fcbulr fcc1,1,1 + fail +okm: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x6 2 + fcbulr fcc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr oko,lr + set_fcc 0x7 3 + fcbulr fcc3,1,3 + fail +oko: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0x8 0 + fcbulr fcc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr okq,lr + set_fcc 0x9 1 + fcbulr fcc1,1,1 + fail +okq: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0xa 2 + fcbulr fcc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr oks,lr + set_fcc 0xb 3 + fcbulr fcc3,1,3 + fail +oks: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0xc 0 + fcbulr fcc0,1,0 + + set_spr_immed 1,lcr + set_spr_addr oku,lr + set_fcc 0xd 1 + fcbulr fcc1,1,1 + fail +oku: + set_spr_immed 1,lcr + set_spr_addr bad,lr + set_fcc 0xe 2 + fcbulr fcc2,1,2 + + set_spr_immed 1,lcr + set_spr_addr okw,lr + set_fcc 0xf 3 + fcbulr fcc3,1,3 + fail +okw: + ; ccond is false + set_spr_immed 128,lcr + + set_fcc 0x0 0 + fcbulr fcc0,1,0 + set_fcc 0x1 1 + fcbulr fcc1,1,1 + set_fcc 0x2 2 + fcbulr fcc2,1,2 + set_fcc 0x3 3 + fcbulr fcc3,1,3 + set_fcc 0x4 0 + fcbulr fcc0,1,0 + set_fcc 0x5 1 + fcbulr fcc1,1,1 + set_fcc 0x6 2 + fcbulr fcc2,1,2 + set_fcc 0x7 3 + fcbulr fcc3,1,3 + set_fcc 0x8 0 + fcbulr fcc0,1,0 + set_fcc 0x9 1 + fcbulr fcc1,1,1 + set_fcc 0xa 2 + fcbulr fcc2,1,2 + set_fcc 0xb 3 + fcbulr fcc3,1,3 + set_fcc 0xc 0 + fcbulr fcc0,1,0 + set_fcc 0xd 1 + fcbulr fcc1,1,1 + set_fcc 0xe 2 + fcbulr fcc2,1,2 + set_fcc 0xf 3 + fcbulr fcc3,1,3 + + ; ccond is false + set_spr_immed 1,lcr + set_fcc 0x0 0 + fcbulr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x1 1 + fcbulr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0x2 2 + fcbulr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0x3 3 + fcbulr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0x4 0 + fcbulr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x5 1 + fcbulr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0x6 2 + fcbulr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0x7 3 + fcbulr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0x8 0 + fcbulr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0x9 1 + fcbulr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0xa 2 + fcbulr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0xb 3 + fcbulr fcc3,0,3 + set_spr_immed 1,lcr + set_fcc 0xc 0 + fcbulr fcc0,0,0 + set_spr_immed 1,lcr + set_fcc 0xd 1 + fcbulr fcc1,0,1 + set_spr_immed 1,lcr + set_fcc 0xe 2 + fcbulr fcc2,0,2 + set_spr_immed 1,lcr + set_fcc 0xf 3 + fcbulr fcc3,0,3 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/fckeq.cgs b/sim/testsuite/sim/frv/fckeq.cgs new file mode 100644 index 0000000..572a86d --- /dev/null +++ b/sim/testsuite/sim/frv/fckeq.cgs @@ -0,0 +1,90 @@ +# frv testcase for fckeq $FCCi,$CCj_float +# mach: all + + .include "testutils.inc" + + start + + .global fckeq +fckeq: + set_spr_immed 0x1b1b,cccr + set_fcc 0x0 0 + fckeq fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x1 0 + fckeq fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x2 0 + fckeq fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x3 0 + fckeq fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x4 0 + fckeq fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x5 0 + fckeq fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x6 0 + fckeq fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x7 0 + fckeq fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x8 0 + fckeq fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x9 0 + fckeq fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xa 0 + fckeq fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xb 0 + fckeq fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xc 0 + fckeq fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xd 0 + fckeq fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xe 0 + fckeq fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xf 0 + fckeq fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + pass diff --git a/sim/testsuite/sim/frv/fckge.cgs b/sim/testsuite/sim/frv/fckge.cgs new file mode 100644 index 0000000..91a1efd --- /dev/null +++ b/sim/testsuite/sim/frv/fckge.cgs @@ -0,0 +1,90 @@ +# frv testcase for fckge $FCCi,$CCj_float +# mach: all + + .include "testutils.inc" + + start + + .global fckge +fckge: + set_spr_immed 0x1b1b,cccr + set_fcc 0x0 0 + fckge fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x1 0 + fckge fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x2 0 + fckge fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x3 0 + fckge fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x4 0 + fckge fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x5 0 + fckge fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x6 0 + fckge fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x7 0 + fckge fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x8 0 + fckge fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x9 0 + fckge fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xa 0 + fckge fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xb 0 + fckge fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xc 0 + fckge fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xd 0 + fckge fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xe 0 + fckge fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xf 0 + fckge fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + pass diff --git a/sim/testsuite/sim/frv/fckgt.cgs b/sim/testsuite/sim/frv/fckgt.cgs new file mode 100644 index 0000000..06715f9 --- /dev/null +++ b/sim/testsuite/sim/frv/fckgt.cgs @@ -0,0 +1,90 @@ +# frv testcase for fckgt $FCCi,$CCj_float +# mach: all + + .include "testutils.inc" + + start + + .global fckgt +fckgt: + set_spr_immed 0x1b1b,cccr + set_fcc 0x0 0 + fckgt fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x1 0 + fckgt fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x2 0 + fckgt fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x3 0 + fckgt fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x4 0 + fckgt fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x5 0 + fckgt fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x6 0 + fckgt fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x7 0 + fckgt fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x8 0 + fckgt fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x9 0 + fckgt fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xa 0 + fckgt fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xb 0 + fckgt fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xc 0 + fckgt fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xd 0 + fckgt fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xe 0 + fckgt fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xf 0 + fckgt fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + pass diff --git a/sim/testsuite/sim/frv/fckle.cgs b/sim/testsuite/sim/frv/fckle.cgs new file mode 100644 index 0000000..7d5e6da --- /dev/null +++ b/sim/testsuite/sim/frv/fckle.cgs @@ -0,0 +1,90 @@ +# frv testcase for fckle $FCCi,$CCj_float +# mach: all + + .include "testutils.inc" + + start + + .global fckle +fckle: + set_spr_immed 0x1b1b,cccr + set_fcc 0x0 0 + fckle fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x1 0 + fckle fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x2 0 + fckle fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x3 0 + fckle fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x4 0 + fckle fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x5 0 + fckle fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x6 0 + fckle fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x7 0 + fckle fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x8 0 + fckle fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x9 0 + fckle fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xa 0 + fckle fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xb 0 + fckle fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xc 0 + fckle fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xd 0 + fckle fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xe 0 + fckle fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xf 0 + fckle fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + pass diff --git a/sim/testsuite/sim/frv/fcklg.cgs b/sim/testsuite/sim/frv/fcklg.cgs new file mode 100644 index 0000000..f8df5a1 --- /dev/null +++ b/sim/testsuite/sim/frv/fcklg.cgs @@ -0,0 +1,90 @@ +# frv testcase for fcklg $FCCi,$CCj_float +# mach: all + + .include "testutils.inc" + + start + + .global fcklg +fcklg: + set_spr_immed 0x1b1b,cccr + set_fcc 0x0 0 + fcklg fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x1 0 + fcklg fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x2 0 + fcklg fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x3 0 + fcklg fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x4 0 + fcklg fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x5 0 + fcklg fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x6 0 + fcklg fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x7 0 + fcklg fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x8 0 + fcklg fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x9 0 + fcklg fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xa 0 + fcklg fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xb 0 + fcklg fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xc 0 + fcklg fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xd 0 + fcklg fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xe 0 + fcklg fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xf 0 + fcklg fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + pass diff --git a/sim/testsuite/sim/frv/fcklt.cgs b/sim/testsuite/sim/frv/fcklt.cgs new file mode 100644 index 0000000..14e5371 --- /dev/null +++ b/sim/testsuite/sim/frv/fcklt.cgs @@ -0,0 +1,90 @@ +# frv testcase for fcklt $FCCi,$CCj_float +# mach: all + + .include "testutils.inc" + + start + + .global fcklt +fcklt: + set_spr_immed 0x1b1b,cccr + set_fcc 0x0 0 + fcklt fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x1 0 + fcklt fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x2 0 + fcklt fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x3 0 + fcklt fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x4 0 + fcklt fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x5 0 + fcklt fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x6 0 + fcklt fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x7 0 + fcklt fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x8 0 + fcklt fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x9 0 + fcklt fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xa 0 + fcklt fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xb 0 + fcklt fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xc 0 + fcklt fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xd 0 + fcklt fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xe 0 + fcklt fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xf 0 + fcklt fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + pass diff --git a/sim/testsuite/sim/frv/fckne.cgs b/sim/testsuite/sim/frv/fckne.cgs new file mode 100644 index 0000000..774f837 --- /dev/null +++ b/sim/testsuite/sim/frv/fckne.cgs @@ -0,0 +1,90 @@ +# frv testcase for fckne $FCCi,$CCj_float +# mach: all + + .include "testutils.inc" + + start + + .global fckne +fckne: + set_spr_immed 0x1b1b,cccr + set_fcc 0x0 0 + fckne fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x1 0 + fckne fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x2 0 + fckne fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x3 0 + fckne fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x4 0 + fckne fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x5 0 + fckne fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x6 0 + fckne fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x7 0 + fckne fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x8 0 + fckne fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x9 0 + fckne fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xa 0 + fckne fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xb 0 + fckne fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xc 0 + fckne fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xd 0 + fckne fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xe 0 + fckne fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xf 0 + fckne fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + pass diff --git a/sim/testsuite/sim/frv/fckno.cgs b/sim/testsuite/sim/frv/fckno.cgs new file mode 100644 index 0000000..08513a2 --- /dev/null +++ b/sim/testsuite/sim/frv/fckno.cgs @@ -0,0 +1,90 @@ +# frv testcase for fckno $CCj_float +# mach: all + + .include "testutils.inc" + + start + + .global fckno +fckno: + set_spr_immed 0x1b1b,cccr + set_fcc 0x0 0 + fckno cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x1 0 + fckno cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x2 0 + fckno cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x3 0 + fckno cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x4 0 + fckno cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x5 0 + fckno cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x6 0 + fckno cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x7 0 + fckno cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x8 0 + fckno cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x9 0 + fckno cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xa 0 + fckno cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xb 0 + fckno cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xc 0 + fckno cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xd 0 + fckno cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xe 0 + fckno cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xf 0 + fckno cc3 + test_spr_immed 0x1b9b,cccr + + pass diff --git a/sim/testsuite/sim/frv/fcko.cgs b/sim/testsuite/sim/frv/fcko.cgs new file mode 100644 index 0000000..06d5640 --- /dev/null +++ b/sim/testsuite/sim/frv/fcko.cgs @@ -0,0 +1,90 @@ +# frv testcase for fcko $FCCi,$CCj_float +# mach: all + + .include "testutils.inc" + + start + + .global fcko +fcko: + set_spr_immed 0x1b1b,cccr + set_fcc 0x0 0 + fcko fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x1 0 + fcko fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x2 0 + fcko fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x3 0 + fcko fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x4 0 + fcko fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x5 0 + fcko fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x6 0 + fcko fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x7 0 + fcko fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x8 0 + fcko fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x9 0 + fcko fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xa 0 + fcko fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xb 0 + fcko fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xc 0 + fcko fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xd 0 + fcko fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xe 0 + fcko fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xf 0 + fcko fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + pass diff --git a/sim/testsuite/sim/frv/fckra.cgs b/sim/testsuite/sim/frv/fckra.cgs new file mode 100644 index 0000000..a74b9fc --- /dev/null +++ b/sim/testsuite/sim/frv/fckra.cgs @@ -0,0 +1,90 @@ +# frv testcase for fckra $CCj_float +# mach: all + + .include "testutils.inc" + + start + + .global fckra +fckra: + set_spr_immed 0x1b1b,cccr + set_fcc 0x0 0 + fckra cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x1 0 + fckra cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x2 0 + fckra cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x3 0 + fckra cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x4 0 + fckra cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x5 0 + fckra cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x6 0 + fckra cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x7 0 + fckra cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x8 0 + fckra cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x9 0 + fckra cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xa 0 + fckra cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xb 0 + fckra cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xc 0 + fckra cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xd 0 + fckra cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xe 0 + fckra cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xf 0 + fckra cc3 + test_spr_immed 0x1bdb,cccr + + pass diff --git a/sim/testsuite/sim/frv/fcku.cgs b/sim/testsuite/sim/frv/fcku.cgs new file mode 100644 index 0000000..9aaa635 --- /dev/null +++ b/sim/testsuite/sim/frv/fcku.cgs @@ -0,0 +1,90 @@ +# frv testcase for fcku $FCCi,$CCj_float +# mach: all + + .include "testutils.inc" + + start + + .global fcku +fcku: + set_spr_immed 0x1b1b,cccr + set_fcc 0x0 0 + fcku fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x1 0 + fcku fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x2 0 + fcku fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x3 0 + fcku fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x4 0 + fcku fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x5 0 + fcku fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x6 0 + fcku fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x7 0 + fcku fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x8 0 + fcku fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x9 0 + fcku fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xa 0 + fcku fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xb 0 + fcku fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xc 0 + fcku fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xd 0 + fcku fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xe 0 + fcku fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xf 0 + fcku fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + pass diff --git a/sim/testsuite/sim/frv/fckue.cgs b/sim/testsuite/sim/frv/fckue.cgs new file mode 100644 index 0000000..0bd7696 --- /dev/null +++ b/sim/testsuite/sim/frv/fckue.cgs @@ -0,0 +1,90 @@ +# frv testcase for fckue $FCCi,$CCj_float +# mach: all + + .include "testutils.inc" + + start + + .global fckue +fckue: + set_spr_immed 0x1b1b,cccr + set_fcc 0x0 0 + fckue fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x1 0 + fckue fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x2 0 + fckue fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x3 0 + fckue fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x4 0 + fckue fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x5 0 + fckue fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x6 0 + fckue fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x7 0 + fckue fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x8 0 + fckue fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x9 0 + fckue fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xa 0 + fckue fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xb 0 + fckue fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xc 0 + fckue fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xd 0 + fckue fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xe 0 + fckue fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xf 0 + fckue fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + pass diff --git a/sim/testsuite/sim/frv/fckug.cgs b/sim/testsuite/sim/frv/fckug.cgs new file mode 100644 index 0000000..f810335 --- /dev/null +++ b/sim/testsuite/sim/frv/fckug.cgs @@ -0,0 +1,90 @@ +# frv testcase for fckug $FCCi,$CCj_float +# mach: all + + .include "testutils.inc" + + start + + .global fckug +fckug: + set_spr_immed 0x1b1b,cccr + set_fcc 0x0 0 + fckug fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x1 0 + fckug fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x2 0 + fckug fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x3 0 + fckug fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x4 0 + fckug fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x5 0 + fckug fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x6 0 + fckug fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x7 0 + fckug fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x8 0 + fckug fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x9 0 + fckug fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xa 0 + fckug fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xb 0 + fckug fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xc 0 + fckug fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xd 0 + fckug fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xe 0 + fckug fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xf 0 + fckug fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + pass diff --git a/sim/testsuite/sim/frv/fckuge.cgs b/sim/testsuite/sim/frv/fckuge.cgs new file mode 100644 index 0000000..d812638 --- /dev/null +++ b/sim/testsuite/sim/frv/fckuge.cgs @@ -0,0 +1,90 @@ +# frv testcase for fckuge $FCCi,$CCj_float +# mach: all + + .include "testutils.inc" + + start + + .global fckuge +fckuge: + set_spr_immed 0x1b1b,cccr + set_fcc 0x0 0 + fckuge fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x1 0 + fckuge fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x2 0 + fckuge fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x3 0 + fckuge fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x4 0 + fckuge fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x5 0 + fckuge fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x6 0 + fckuge fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x7 0 + fckuge fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x8 0 + fckuge fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x9 0 + fckuge fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xa 0 + fckuge fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xb 0 + fckuge fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xc 0 + fckuge fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xd 0 + fckuge fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xe 0 + fckuge fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xf 0 + fckuge fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + pass diff --git a/sim/testsuite/sim/frv/fckul.cgs b/sim/testsuite/sim/frv/fckul.cgs new file mode 100644 index 0000000..2d30d92 --- /dev/null +++ b/sim/testsuite/sim/frv/fckul.cgs @@ -0,0 +1,90 @@ +# frv testcase for fckul $FCCi,$CCj_float +# mach: all + + .include "testutils.inc" + + start + + .global fckul +fckul: + set_spr_immed 0x1b1b,cccr + set_fcc 0x0 0 + fckul fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x1 0 + fckul fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x2 0 + fckul fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x3 0 + fckul fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x4 0 + fckul fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x5 0 + fckul fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x6 0 + fckul fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x7 0 + fckul fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x8 0 + fckul fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x9 0 + fckul fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xa 0 + fckul fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xb 0 + fckul fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xc 0 + fckul fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xd 0 + fckul fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xe 0 + fckul fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xf 0 + fckul fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + pass diff --git a/sim/testsuite/sim/frv/fckule.cgs b/sim/testsuite/sim/frv/fckule.cgs new file mode 100644 index 0000000..9830a66 --- /dev/null +++ b/sim/testsuite/sim/frv/fckule.cgs @@ -0,0 +1,90 @@ +# frv testcase for fckule $FCCi,$CCj_float +# mach: all + + .include "testutils.inc" + + start + + .global fckule +fckule: + set_spr_immed 0x1b1b,cccr + set_fcc 0x0 0 + fckule fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x1 0 + fckule fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x2 0 + fckule fcc0,cc3 + test_spr_immed 0x1b9b,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x3 0 + fckule fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x4 0 + fckule fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x5 0 + fckule fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x6 0 + fckule fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x7 0 + fckule fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x8 0 + fckule fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0x9 0 + fckule fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xa 0 + fckule fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xb 0 + fckule fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xc 0 + fckule fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xd 0 + fckule fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xe 0 + fckule fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b1b,cccr + set_fcc 0xf 0 + fckule fcc0,cc3 + test_spr_immed 0x1bdb,cccr + + pass diff --git a/sim/testsuite/sim/frv/fcmpd.cgs b/sim/testsuite/sim/frv/fcmpd.cgs new file mode 100644 index 0000000..5c86266 --- /dev/null +++ b/sim/testsuite/sim/frv/fcmpd.cgs @@ -0,0 +1,601 @@ +# frv testcase for fcmpd $GRi,$GRj,$FCCi_2 +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + double_constants + start + load_double_constants + + .global fcmpd +fcmpd: + set_fcc 0x7,0 ; Set mask opposite of expected + fcmpd fr0,fr0,fcc0 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr0,fr4,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr0,fr8,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr0,fr12,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr0,fr16,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr0,fr20,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr0,fr24,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr0,fr28,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr0,fr32,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr0,fr36,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr0,fr40,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr0,fr44,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr0,fr48,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr0,fr52,fcc0 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr0,fr56,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr0,fr60,fcc0 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr4,fr0,fcc0 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + fcmpd fr4,fr4,fcc0 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr4,fr8,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr4,fr12,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr4,fr16,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr4,fr20,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr4,fr24,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr4,fr28,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr4,fr32,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr4,fr36,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr4,fr40,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr4,fr44,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr4,fr48,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr4,fr52,fcc0 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr4,fr56,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr4,fr60,fcc0 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr8,fr0,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr8,fr4,fcc0 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + fcmpd fr8,fr8,fcc0 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr8,fr12,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr8,fr16,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr8,fr20,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr8,fr24,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr8,fr28,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr8,fr32,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr8,fr36,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr8,fr40,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr8,fr44,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr8,fr48,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr8,fr52,fcc0 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr8,fr56,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr8,fr60,fcc0 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr12,fr0,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr12,fr4,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr12,fr8,fcc0 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + fcmpd fr12,fr12,fcc0 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr12,fr16,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr12,fr20,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr12,fr24,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr12,fr28,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr12,fr32,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr12,fr36,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr12,fr40,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr12,fr44,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr12,fr48,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr12,fr52,fcc0 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr12,fr56,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr12,fr60,fcc0 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr16,fr0,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr16,fr4,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr16,fr8,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr16,fr12,fcc0 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + fcmpd fr16,fr16,fcc0 + test_fcc 0x8,0 + set_fcc 0x7,0 ; Set mask opposite of expected + fcmpd fr16,fr20,fcc0 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr16,fr24,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr16,fr28,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr16,fr32,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr16,fr36,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr16,fr40,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr16,fr44,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr16,fr48,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr16,fr52,fcc0 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr16,fr56,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr16,fr60,fcc0 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr20,fr0,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr20,fr4,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr20,fr8,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr20,fr12,fcc0 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + fcmpd fr20,fr16,fcc0 + test_fcc 0x8,0 + set_fcc 0x7,0 ; Set mask opposite of expected + fcmpd fr20,fr20,fcc0 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr20,fr24,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr20,fr28,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr20,fr32,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr20,fr36,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr20,fr40,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr20,fr44,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr20,fr48,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr20,fr52,fcc0 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr20,fr56,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr20,fr60,fcc0 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr24,fr0,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr24,fr4,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr24,fr8,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr24,fr12,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr24,fr16,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr24,fr20,fcc0 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + fcmpd fr24,fr24,fcc0 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr24,fr28,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr24,fr32,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr24,fr36,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr24,fr40,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr24,fr44,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr24,fr48,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr24,fr52,fcc0 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr24,fr56,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr24,fr60,fcc0 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr28,fr0,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr28,fr4,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr28,fr8,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr28,fr12,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr28,fr16,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr28,fr20,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr28,fr24,fcc0 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + fcmpd fr28,fr28,fcc0 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr28,fr32,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr28,fr36,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr28,fr40,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr28,fr44,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr28,fr48,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr28,fr52,fcc0 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr28,fr56,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr28,fr60,fcc0 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr48,fr0,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr48,fr4,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr48,fr8,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr48,fr12,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr48,fr16,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr48,fr20,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr48,fr24,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr48,fr28,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr48,fr32,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr48,fr36,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr48,fr40,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr48,fr44,fcc0 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + fcmpd fr48,fr48,fcc0 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmpd fr48,fr52,fcc0 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr48,fr56,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr48,fr60,fcc0 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr52,fr0,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr52,fr4,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr52,fr8,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr52,fr12,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr52,fr16,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr52,fr20,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr52,fr24,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr52,fr28,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr52,fr32,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr52,fr36,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr52,fr40,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr52,fr44,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmpd fr52,fr48,fcc0 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + fcmpd fr52,fr52,fcc0 + test_fcc 0x8,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr52,fr56,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr52,fr60,fcc0 + test_fcc 0x1,0 + + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr56,fr0,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr56,fr4,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr56,fr8,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr56,fr12,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr56,fr16,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr56,fr20,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr56,fr24,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr56,fr28,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr56,fr32,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr56,fr36,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr56,fr40,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr56,fr44,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr56,fr48,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr56,fr52,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr56,fr56,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr56,fr60,fcc0 + test_fcc 0x1,0 + + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr60,fr0,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr60,fr4,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr60,fr8,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr60,fr12,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr60,fr16,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr60,fr20,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr60,fr24,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr60,fr28,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr60,fr32,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr60,fr36,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr60,fr40,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr60,fr44,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr60,fr48,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr60,fr52,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr60,fr56,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmpd fr60,fr60,fcc0 + test_fcc 0x1,0 + + pass diff --git a/sim/testsuite/sim/frv/fcmps.cgs b/sim/testsuite/sim/frv/fcmps.cgs new file mode 100644 index 0000000..ea1ccc0 --- /dev/null +++ b/sim/testsuite/sim/frv/fcmps.cgs @@ -0,0 +1,600 @@ +# frv testcase for fcmps $GRi,$GRj,$FCCi_2 +# mach: fr500 fr550 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global fcmps +fcmps: + set_fcc 0x7,0 ; Set mask opposite of expected + fcmps fr0,fr0,fcc0 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr0,fr4,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr0,fr8,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr0,fr12,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr0,fr16,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr0,fr20,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr0,fr24,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr0,fr28,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr0,fr32,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr0,fr36,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr0,fr40,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr0,fr44,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr0,fr48,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr0,fr52,fcc0 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr0,fr56,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr0,fr60,fcc0 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr4,fr0,fcc0 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + fcmps fr4,fr4,fcc0 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr4,fr8,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr4,fr12,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr4,fr16,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr4,fr20,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr4,fr24,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr4,fr28,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr4,fr32,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr4,fr36,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr4,fr40,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr4,fr44,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr4,fr48,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr4,fr52,fcc0 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr4,fr56,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr4,fr60,fcc0 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr8,fr0,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr8,fr4,fcc0 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + fcmps fr8,fr8,fcc0 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr8,fr12,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr8,fr16,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr8,fr20,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr8,fr24,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr8,fr28,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr8,fr32,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr8,fr36,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr8,fr40,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr8,fr44,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr8,fr48,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr8,fr52,fcc0 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr8,fr56,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr8,fr60,fcc0 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr12,fr0,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr12,fr4,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr12,fr8,fcc0 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + fcmps fr12,fr12,fcc0 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr12,fr16,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr12,fr20,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr12,fr24,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr12,fr28,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr12,fr32,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr12,fr36,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr12,fr40,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr12,fr44,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr12,fr48,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr12,fr52,fcc0 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr12,fr56,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr12,fr60,fcc0 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr16,fr0,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr16,fr4,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr16,fr8,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr16,fr12,fcc0 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + fcmps fr16,fr16,fcc0 + test_fcc 0x8,0 + set_fcc 0x7,0 ; Set mask opposite of expected + fcmps fr16,fr20,fcc0 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr16,fr24,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr16,fr28,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr16,fr32,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr16,fr36,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr16,fr40,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr16,fr44,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr16,fr48,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr16,fr52,fcc0 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr16,fr56,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr16,fr60,fcc0 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr20,fr0,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr20,fr4,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr20,fr8,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr20,fr12,fcc0 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + fcmps fr20,fr16,fcc0 + test_fcc 0x8,0 + set_fcc 0x7,0 ; Set mask opposite of expected + fcmps fr20,fr20,fcc0 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr20,fr24,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr20,fr28,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr20,fr32,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr20,fr36,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr20,fr40,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr20,fr44,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr20,fr48,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr20,fr52,fcc0 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr20,fr56,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr20,fr60,fcc0 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr24,fr0,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr24,fr4,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr24,fr8,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr24,fr12,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr24,fr16,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr24,fr20,fcc0 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + fcmps fr24,fr24,fcc0 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr24,fr28,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr24,fr32,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr24,fr36,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr24,fr40,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr24,fr44,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr24,fr48,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr24,fr52,fcc0 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr24,fr56,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr24,fr60,fcc0 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr28,fr0,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr28,fr4,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr28,fr8,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr28,fr12,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr28,fr16,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr28,fr20,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr28,fr24,fcc0 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + fcmps fr28,fr28,fcc0 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr28,fr32,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr28,fr36,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr28,fr40,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr28,fr44,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr28,fr48,fcc0 + test_fcc 0x4,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr28,fr52,fcc0 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr28,fr56,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr28,fr60,fcc0 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr48,fr0,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr48,fr4,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr48,fr8,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr48,fr12,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr48,fr16,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr48,fr20,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr48,fr24,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr48,fr28,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr48,fr32,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr48,fr36,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr48,fr40,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr48,fr44,fcc0 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + fcmps fr48,fr48,fcc0 + test_fcc 0x8,0 + set_fcc 0xb,0 ; Set mask opposite of expected + fcmps fr48,fr52,fcc0 + test_fcc 0x4,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr48,fr56,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr48,fr60,fcc0 + test_fcc 0x1,0 + + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr52,fr0,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr52,fr4,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr52,fr8,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr52,fr12,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr52,fr16,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr52,fr20,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr52,fr24,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr52,fr28,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr52,fr32,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr52,fr36,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr52,fr40,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr52,fr44,fcc0 + test_fcc 0x2,0 + set_fcc 0xd,0 ; Set mask opposite of expected + fcmps fr52,fr48,fcc0 + test_fcc 0x2,0 + set_fcc 0x7,0 ; Set mask opposite of expected + fcmps fr52,fr52,fcc0 + test_fcc 0x8,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr52,fr56,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr52,fr60,fcc0 + test_fcc 0x1,0 + + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr56,fr0,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr56,fr4,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr56,fr8,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr56,fr12,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr56,fr16,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr56,fr20,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr56,fr24,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr56,fr28,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr56,fr32,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr56,fr36,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr56,fr40,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr56,fr44,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr56,fr48,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr56,fr52,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr56,fr56,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr56,fr60,fcc0 + test_fcc 0x1,0 + + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr60,fr0,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr60,fr4,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr60,fr8,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr60,fr12,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr60,fr16,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr60,fr20,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr60,fr24,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr60,fr28,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr60,fr32,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr60,fr36,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr60,fr40,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr60,fr44,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr60,fr48,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr60,fr52,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr60,fr56,fcc0 + test_fcc 0x1,0 + set_fcc 0xe,0 ; Set mask opposite of expected + fcmps fr60,fr60,fcc0 + test_fcc 0x1,0 + + pass diff --git a/sim/testsuite/sim/frv/fdabss.cgs b/sim/testsuite/sim/frv/fdabss.cgs new file mode 100644 index 0000000..83d3e1c --- /dev/null +++ b/sim/testsuite/sim/frv/fdabss.cgs @@ -0,0 +1,25 @@ +# frv testcase for fdabss $FRj,$FRk +# mach: frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global fdabss +fdabss: + set_fr_fr fr8,fr1 + fdabss fr0,fr2 + test_fr_fr fr2,fr52 + test_fr_fr fr3,fr28 + set_fr_fr fr24,fr13 + fdabss fr12,fr2 + test_fr_fr fr2,fr24 + test_fr_fr fr3,fr24 + set_fr_fr fr52,fr29 + fdabss fr28,fr2 + test_fr_fr fr2,fr28 + test_fr_fr fr3,fr52 + + pass diff --git a/sim/testsuite/sim/frv/fdadds.cgs b/sim/testsuite/sim/frv/fdadds.cgs new file mode 100644 index 0000000..ecfa56c --- /dev/null +++ b/sim/testsuite/sim/frv/fdadds.cgs @@ -0,0 +1,134 @@ +# frv testcase for fdadds $GRi,$GRj,$GRk +# mach: fr500 fr550 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + load_float_constants1 + + .global fdadds +fdadds: + fdadds fr16,fr0,fr2 + test_fr_fr fr2,fr0 + test_fr_fr fr3,fr0 + fdadds fr16,fr4,fr2 + test_fr_fr fr2,fr4 + test_fr_fr fr3,fr4 + fdadds fr16,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr8 + fdadds fr16,fr12,fr2 + test_fr_fr fr2,fr12 + test_fr_fr fr3,fr12 + fdadds fr16,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdadds fr16,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdadds fr16,fr24,fr2 + test_fr_fr fr2,fr24 + test_fr_fr fr3,fr24 + fdadds fr16,fr28,fr2 + test_fr_fr fr2,fr28 + test_fr_fr fr3,fr28 + fdadds fr16,fr32,fr2 + test_fr_fr fr2,fr32 + test_fr_fr fr3,fr32 + fdadds fr16,fr36,fr2 + test_fr_fr fr2,fr36 + test_fr_fr fr3,fr36 + fdadds fr16,fr40,fr2 + test_fr_fr fr2,fr40 + test_fr_fr fr3,fr40 + fdadds fr16,fr44,fr2 + test_fr_fr fr2,fr44 + test_fr_fr fr3,fr44 + fdadds fr16,fr48,fr2 + test_fr_fr fr2,fr48 + test_fr_fr fr3,fr48 + fdadds fr16,fr52,fr2 + test_fr_fr fr2,fr52 + test_fr_fr fr3,fr52 + + fdadds fr20,fr0,fr2 + test_fr_fr fr2,fr0 + test_fr_fr fr3,fr0 + fdadds fr20,fr4,fr2 + test_fr_fr fr2,fr4 + test_fr_fr fr3,fr4 + fdadds fr20,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr8 + fdadds fr20,fr12,fr2 + test_fr_fr fr2,fr12 + test_fr_fr fr3,fr12 + fdadds fr20,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdadds fr20,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdadds fr20,fr24,fr2 + test_fr_fr fr2,fr24 + test_fr_fr fr3,fr24 + fdadds fr20,fr28,fr2 + test_fr_fr fr2,fr28 + test_fr_fr fr3,fr28 + fdadds fr20,fr32,fr2 + test_fr_fr fr2,fr32 + test_fr_fr fr3,fr32 + fdadds fr20,fr36,fr2 + test_fr_fr fr2,fr36 + test_fr_fr fr3,fr36 + fdadds fr20,fr40,fr2 + test_fr_fr fr2,fr40 + test_fr_fr fr3,fr40 + fdadds fr20,fr44,fr2 + test_fr_fr fr2,fr44 + test_fr_fr fr3,fr44 + fdadds fr20,fr48,fr2 + test_fr_fr fr2,fr48 + test_fr_fr fr3,fr48 + fdadds fr20,fr52,fr2 + test_fr_fr fr2,fr52 + test_fr_fr fr3,fr52 + + fdadds fr8,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdadds fr12,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdadds fr24,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdadds fr28,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + + fdadds fr36,fr40,fr2 + test_fr_fr fr2,fr44 + test_fr_fr fr3,fr44 + + pass + + diff --git a/sim/testsuite/sim/frv/fdcmps.cgs b/sim/testsuite/sim/frv/fdcmps.cgs new file mode 100644 index 0000000..397832c --- /dev/null +++ b/sim/testsuite/sim/frv/fdcmps.cgs @@ -0,0 +1,985 @@ +# frv testcase for fdcmps $FRi,$FRj,$FCCi_2 +# mach: fr500 fr550 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + load_float_constants1 + + .global fdcmps +fdcmps: + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + fdcmps fr0,fr0,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr0,fr4,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr0,fr8,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr0,fr12,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr0,fr16,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr0,fr20,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr0,fr24,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr0,fr28,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr0,fr32,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr0,fr36,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr0,fr40,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr0,fr44,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr0,fr48,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr0,fr52,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr0,fr56,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr0,fr60,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr4,fr0,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + fdcmps fr4,fr4,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr4,fr8,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr4,fr12,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr4,fr16,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr4,fr20,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr4,fr24,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr4,fr28,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr4,fr32,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr4,fr36,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr4,fr40,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr4,fr44,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr4,fr48,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr4,fr52,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr4,fr56,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr4,fr60,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr8,fr0,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr8,fr4,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + fdcmps fr8,fr8,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr8,fr12,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr8,fr16,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr8,fr20,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr8,fr24,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr8,fr28,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr8,fr32,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr8,fr36,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr8,fr40,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr8,fr44,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr8,fr48,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr8,fr52,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr8,fr56,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr8,fr60,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr12,fr0,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr12,fr4,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr12,fr8,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + fdcmps fr12,fr12,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr12,fr16,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr12,fr20,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr12,fr24,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr12,fr28,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr12,fr32,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr12,fr36,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr12,fr40,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr12,fr44,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr12,fr48,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr12,fr52,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr12,fr56,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr12,fr60,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr16,fr0,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr16,fr4,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr16,fr8,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr16,fr12,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + fdcmps fr16,fr16,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + fdcmps fr16,fr20,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr16,fr24,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr16,fr28,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr16,fr32,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr16,fr36,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr16,fr40,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr16,fr44,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr16,fr48,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr16,fr52,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr16,fr56,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr16,fr60,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr20,fr0,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr20,fr4,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr20,fr8,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr20,fr12,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + fdcmps fr20,fr16,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + fdcmps fr20,fr20,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr20,fr24,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr20,fr28,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr20,fr32,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr20,fr36,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr20,fr40,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr20,fr44,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr20,fr48,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr20,fr52,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr20,fr56,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr20,fr60,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr24,fr0,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr24,fr4,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr24,fr8,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr24,fr12,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr24,fr16,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr24,fr20,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + fdcmps fr24,fr24,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr24,fr28,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr24,fr32,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr24,fr36,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr24,fr40,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr24,fr44,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr24,fr48,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr24,fr52,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr24,fr56,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr24,fr60,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr28,fr0,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr28,fr4,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr28,fr8,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr28,fr12,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr28,fr16,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr28,fr20,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr28,fr24,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + fdcmps fr28,fr28,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr28,fr32,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr28,fr36,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr28,fr40,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr28,fr44,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr28,fr48,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr28,fr52,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr28,fr56,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr28,fr60,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr48,fr0,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr48,fr4,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr48,fr8,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr48,fr12,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr48,fr16,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr48,fr20,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr48,fr24,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr48,fr28,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr48,fr32,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr48,fr36,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr48,fr40,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr48,fr44,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + fdcmps fr48,fr48,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + fdcmps fr48,fr52,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr48,fr56,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr48,fr60,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr52,fr0,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr52,fr4,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr52,fr8,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr52,fr12,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr52,fr16,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr52,fr20,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr52,fr24,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr52,fr28,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr52,fr32,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr52,fr36,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr52,fr40,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr52,fr44,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + fdcmps fr52,fr48,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + fdcmps fr52,fr52,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr52,fr56,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr52,fr60,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr56,fr0,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr56,fr4,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr56,fr8,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr56,fr12,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr56,fr16,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr56,fr20,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr56,fr24,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr56,fr28,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr56,fr32,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr56,fr36,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr56,fr40,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr56,fr44,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr56,fr48,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr56,fr52,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr56,fr56,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr56,fr60,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr60,fr0,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr60,fr4,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr60,fr8,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr60,fr12,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr60,fr16,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr60,fr20,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr60,fr24,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr60,fr28,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr60,fr32,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr60,fr36,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr60,fr40,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr60,fr44,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr60,fr48,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr60,fr52,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr60,fr56,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + fdcmps fr60,fr60,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + + pass diff --git a/sim/testsuite/sim/frv/fddivs.cgs b/sim/testsuite/sim/frv/fddivs.cgs new file mode 100644 index 0000000..ac423b2 --- /dev/null +++ b/sim/testsuite/sim/frv/fddivs.cgs @@ -0,0 +1,195 @@ +# frv testcase for fddivs $FRi,$FRj,$FRk +# mach: frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + load_float_constants1 + + .global fddivs +fddivs: + fddivs fr0,fr28,fr2 + test_fr_fr fr2,fr0 + test_fr_fr fr3,fr0 + fddivs fr4,fr28,fr2 + test_fr_fr fr2,fr4 + test_fr_fr fr3,fr4 + fddivs fr8,fr28,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr8 + fddivs fr12,fr28,fr2 + test_fr_fr fr2,fr12 + test_fr_fr fr3,fr12 + fddivs fr16,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fddivs fr20,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fddivs fr24,fr28,fr2 + test_fr_fr fr2,fr24 + test_fr_fr fr3,fr24 + fddivs fr28,fr28,fr2 + test_fr_fr fr2,fr28 + test_fr_fr fr3,fr28 + fddivs fr32,fr28,fr2 + test_fr_fr fr2,fr32 + test_fr_fr fr3,fr32 + fddivs fr36,fr28,fr2 + test_fr_fr fr2,fr36 + test_fr_fr fr3,fr36 + fddivs fr40,fr28,fr2 + test_fr_fr fr2,fr40 + test_fr_fr fr3,fr40 + fddivs fr44,fr28,fr2 + test_fr_fr fr2,fr44 + test_fr_fr fr3,fr44 + fddivs fr48,fr28,fr2 + test_fr_fr fr2,fr48 + test_fr_fr fr3,fr48 + fddivs fr52,fr28,fr2 + test_fr_fr fr2,fr52 + test_fr_fr fr3,fr52 + + fddivs fr16,fr0,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fddivs fr16,fr4,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fddivs fr16,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fddivs fr16,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fddivs fr16,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fddivs fr16,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fddivs fr16,fr32,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fddivs fr16,fr36,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fddivs fr16,fr40,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fddivs fr16,fr44,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fddivs fr16,fr48,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fddivs fr16,fr52,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + + fddivs fr20,fr0,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fddivs fr20,fr4,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fddivs fr20,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fddivs fr20,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fddivs fr20,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fddivs fr20,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fddivs fr20,fr32,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fddivs fr20,fr36,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fddivs fr20,fr40,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fddivs fr20,fr44,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fddivs fr20,fr48,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fddivs fr20,fr52,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + + fddivs fr8,fr28,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr8 + fddivs fr28,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr8 + + fddivs fr40,fr32,fr2 + test_fr_fr fr2,fr36 + test_fr_fr fr3,fr36 + + pass + + diff --git a/sim/testsuite/sim/frv/fditos.cgs b/sim/testsuite/sim/frv/fditos.cgs new file mode 100644 index 0000000..412e8af --- /dev/null +++ b/sim/testsuite/sim/frv/fditos.cgs @@ -0,0 +1,25 @@ +# frv testcase for fditos $FRj,$FRk +# mach: frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global fditos +fditos: + set_fr_iimmed 0,0,fr2 + set_fr_iimmed 0x0000,0x0002,fr3 + fditos fr2,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr32 + + set_fr_iimmed 0xdead,0xbeef,fr2 + set_fr_iimmed 0xdead,0xbeef,fr3 + fditos fr2,fr2 + test_fr_iimmed 0xce054904,fr2 + test_fr_iimmed 0xce054904,fr3 + + pass diff --git a/sim/testsuite/sim/frv/fdivd.cgs b/sim/testsuite/sim/frv/fdivd.cgs new file mode 100644 index 0000000..65222bb --- /dev/null +++ b/sim/testsuite/sim/frv/fdivd.cgs @@ -0,0 +1,128 @@ +# frv testcase for fdivd $GRi,$GRj,$GRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + double_constants + start + load_double_constants + + .global fdivd +fdivd: + fdivd fr0,fr28,fr2 + test_dfr_dfr fr2,fr0 + fdivd fr4,fr28,fr2 + test_dfr_dfr fr2,fr4 + fdivd fr8,fr28,fr2 + test_dfr_dfr fr2,fr8 + fdivd fr12,fr28,fr2 + test_dfr_dfr fr2,fr12 + fdivd fr16,fr28,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fdivd fr20,fr28,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fdivd fr24,fr28,fr2 + test_dfr_dfr fr2,fr24 + fdivd fr28,fr28,fr2 + test_dfr_dfr fr2,fr28 + fdivd fr32,fr28,fr2 + test_dfr_dfr fr2,fr32 + fdivd fr36,fr28,fr2 + test_dfr_dfr fr2,fr36 + fdivd fr40,fr28,fr2 + test_dfr_dfr fr2,fr40 + fdivd fr44,fr28,fr2 + test_dfr_dfr fr2,fr44 + fdivd fr48,fr28,fr2 + test_dfr_dfr fr2,fr48 + fdivd fr52,fr28,fr2 + test_dfr_dfr fr2,fr52 + + fdivd fr16,fr0,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fdivd fr16,fr4,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fdivd fr16,fr8,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fdivd fr16,fr12,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fdivd fr16,fr24,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fdivd fr16,fr28,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fdivd fr16,fr32,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fdivd fr16,fr36,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fdivd fr16,fr40,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fdivd fr16,fr44,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fdivd fr16,fr48,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fdivd fr16,fr52,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + + fdivd fr20,fr0,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fdivd fr20,fr4,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fdivd fr20,fr8,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fdivd fr20,fr12,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fdivd fr20,fr24,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fdivd fr20,fr28,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fdivd fr20,fr32,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fdivd fr20,fr36,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fdivd fr20,fr40,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fdivd fr20,fr44,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fdivd fr20,fr48,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fdivd fr20,fr52,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + + fdivd fr8,fr28,fr2 + test_dfr_dfr fr2,fr8 + fdivd fr28,fr8,fr2 + test_dfr_dfr fr2,fr8 + + fdivd fr40,fr32,fr2 + test_dfr_dfr fr2,fr36 + + pass + + diff --git a/sim/testsuite/sim/frv/fdivs.cgs b/sim/testsuite/sim/frv/fdivs.cgs new file mode 100644 index 0000000..cf2bd4b --- /dev/null +++ b/sim/testsuite/sim/frv/fdivs.cgs @@ -0,0 +1,127 @@ +# frv testcase for fdivs $GRi,$GRj,$GRk +# mach: fr500 fr550 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global fdivs +fdivs: + fdivs fr0,fr28,fr1 + test_fr_fr fr1,fr0 + fdivs fr4,fr28,fr1 + test_fr_fr fr1,fr4 + fdivs fr8,fr28,fr1 + test_fr_fr fr1,fr8 + fdivs fr12,fr28,fr1 + test_fr_fr fr1,fr12 + fdivs fr16,fr28,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fdivs fr20,fr28,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fdivs fr24,fr28,fr1 + test_fr_fr fr1,fr24 + fdivs fr28,fr28,fr1 + test_fr_fr fr1,fr28 + fdivs fr32,fr28,fr1 + test_fr_fr fr1,fr32 + fdivs fr36,fr28,fr1 + test_fr_fr fr1,fr36 + fdivs fr40,fr28,fr1 + test_fr_fr fr1,fr40 + fdivs fr44,fr28,fr1 + test_fr_fr fr1,fr44 + fdivs fr48,fr28,fr1 + test_fr_fr fr1,fr48 + fdivs fr52,fr28,fr1 + test_fr_fr fr1,fr52 + + fdivs fr16,fr0,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fdivs fr16,fr4,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fdivs fr16,fr8,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fdivs fr16,fr12,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fdivs fr16,fr24,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fdivs fr16,fr28,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fdivs fr16,fr32,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fdivs fr16,fr36,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fdivs fr16,fr40,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fdivs fr16,fr44,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fdivs fr16,fr48,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fdivs fr16,fr52,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + + fdivs fr20,fr0,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fdivs fr20,fr4,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fdivs fr20,fr8,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fdivs fr20,fr12,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fdivs fr20,fr24,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fdivs fr20,fr28,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fdivs fr20,fr32,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fdivs fr20,fr36,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fdivs fr20,fr40,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fdivs fr20,fr44,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fdivs fr20,fr48,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fdivs fr20,fr52,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + + fdivs fr8,fr28,fr1 + test_fr_fr fr1,fr8 + fdivs fr28,fr8,fr1 + test_fr_fr fr1,fr8 + + fdivs fr40,fr32,fr1 + test_fr_fr fr1,fr36 + + pass + + diff --git a/sim/testsuite/sim/frv/fdmadds.cgs b/sim/testsuite/sim/frv/fdmadds.cgs new file mode 100644 index 0000000..7035366 --- /dev/null +++ b/sim/testsuite/sim/frv/fdmadds.cgs @@ -0,0 +1,226 @@ +# frv testcase for fdmadds $GRi,$GRj,$GRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + load_float_constants1 + + .global fdmadds +fdmadds: + fdmadds fr16,fr4,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmadds fr16,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmadds fr16,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmadds fr16,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmadds fr16,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmadds fr16,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmadds fr16,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmadds fr16,fr32,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmadds fr16,fr36,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmadds fr16,fr40,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmadds fr16,fr44,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmadds fr16,fr48,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + + fdmadds fr20,fr4,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmadds fr20,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmadds fr20,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmadds fr20,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmadds fr20,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmadds fr20,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmadds fr20,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmadds fr20,fr32,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmadds fr20,fr36,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmadds fr20,fr40,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmadds fr20,fr44,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmadds fr20,fr48,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + + set_fr_fr fr16,fr2 + set_fr_fr fr16,fr3 + fdmadds fr28,fr0,fr2 + test_fr_fr fr2,fr0 + test_fr_fr fr3,fr0 + set_fr_fr fr16,fr2 + set_fr_fr fr16,fr3 + fdmadds fr28,fr4,fr2 + test_fr_fr fr2,fr4 + test_fr_fr fr3,fr4 + set_fr_fr fr16,fr2 + set_fr_fr fr16,fr3 + fdmadds fr28,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr8 + set_fr_fr fr16,fr2 + set_fr_fr fr16,fr3 + fdmadds fr28,fr12,fr2 + test_fr_fr fr2,fr12 + test_fr_fr fr3,fr12 + set_fr_fr fr16,fr2 + set_fr_fr fr16,fr3 + fdmadds fr28,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + set_fr_fr fr16,fr2 + set_fr_fr fr16,fr3 + fdmadds fr28,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + set_fr_fr fr16,fr2 + set_fr_fr fr16,fr3 + fdmadds fr28,fr24,fr2 + test_fr_fr fr2,fr24 + test_fr_fr fr3,fr24 + set_fr_fr fr16,fr2 + set_fr_fr fr16,fr3 + fdmadds fr28,fr28,fr2 + test_fr_fr fr2,fr28 + test_fr_fr fr3,fr28 + set_fr_fr fr16,fr2 + set_fr_fr fr16,fr3 + fdmadds fr28,fr32,fr2 + test_fr_fr fr2,fr32 + test_fr_fr fr3,fr32 + set_fr_fr fr16,fr2 + set_fr_fr fr16,fr3 + fdmadds fr28,fr36,fr2 + test_fr_fr fr2,fr36 + test_fr_fr fr3,fr36 + set_fr_fr fr16,fr2 + set_fr_fr fr16,fr3 + fdmadds fr28,fr40,fr2 + test_fr_fr fr2,fr40 + test_fr_fr fr3,fr40 + set_fr_fr fr16,fr2 + set_fr_fr fr16,fr3 + fdmadds fr28,fr44,fr2 + test_fr_fr fr2,fr44 + test_fr_fr fr3,fr44 + set_fr_fr fr16,fr2 + set_fr_fr fr16,fr3 + fdmadds fr28,fr48,fr2 + test_fr_fr fr2,fr48 + test_fr_fr fr3,fr48 + set_fr_fr fr16,fr2 + set_fr_fr fr16,fr3 + fdmadds fr28,fr52,fr2 + test_fr_fr fr2,fr52 + test_fr_fr fr3,fr52 + + set_fr_fr fr36,fr2 + set_fr_fr fr36,fr3 + fdmadds fr28,fr8,fr2 + test_fr_fr fr2,fr32 + test_fr_fr fr3,fr32 + fdmadds fr8,fr28,fr2 + test_fr_fr fr2,fr28 + test_fr_fr fr3,fr28 + + set_fr_fr fr36,fr2 + set_fr_fr fr36,fr3 + fdmadds fr32,fr36,fr2 + test_fr_fr fr2,fr44 + test_fr_fr fr3,fr44 + + pass diff --git a/sim/testsuite/sim/frv/fdmas.cgs b/sim/testsuite/sim/frv/fdmas.cgs new file mode 100644 index 0000000..a7162db --- /dev/null +++ b/sim/testsuite/sim/frv/fdmas.cgs @@ -0,0 +1,265 @@ +# frv testcase for fdmas $FRi,$FRj,$FRk +# mach: frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + load_float_constants1 + load_float_constants2 + load_float_constants3 + + .global fdmas +fdmas: + fdmas fr16,fr4,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr4 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr4 + fdmas fr16,fr8,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr8 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr8 + fdmas fr16,fr12,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr12 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr12 + fdmas fr16,fr16,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr16 + test_fr_fr fr61,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr16 + test_fr_fr fr63,fr20 + fdmas fr16,fr20,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr16 + test_fr_fr fr61,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr16 + test_fr_fr fr63,fr20 + fdmas fr16,fr24,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr24 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr24 + fdmas fr16,fr28,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr28 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr28 + fdmas fr16,fr32,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr32 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr32 + fdmas fr16,fr36,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr36 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr36 + fdmas fr16,fr40,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr40 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr40 + fdmas fr16,fr44,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr44 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr44 + fdmas fr16,fr48,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr48 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr48 + + fdmas fr20,fr4,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr4 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr4 + fdmas fr20,fr8,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr8 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr8 + fdmas fr20,fr12,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr12 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr12 + fdmas fr20,fr16,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr16 + test_fr_fr fr61,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr16 + test_fr_fr fr63,fr20 + fdmas fr20,fr20,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr16 + test_fr_fr fr61,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr16 + test_fr_fr fr63,fr20 + fdmas fr20,fr24,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr24 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr24 + fdmas fr20,fr28,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr28 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr28 + fdmas fr20,fr32,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr32 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr32 + fdmas fr20,fr36,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr36 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr36 + fdmas fr20,fr40,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr40 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr40 + fdmas fr20,fr44,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr44 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr44 + fdmas fr20,fr48,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr48 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr48 + + fdmas fr28,fr0,fr60 + test_fr_fr fr60,fr0 + test_fr_fr fr62,fr0 + fdmas fr28,fr4,fr60 + test_fr_fr fr60,fr4 + test_fr_fr fr62,fr4 + fdmas fr28,fr8,fr60 + test_fr_fr fr60,fr8 + test_fr_fr fr61,fr16 + test_fr_fr fr61,fr20 + test_fr_fr fr62,fr8 + test_fr_fr fr63,fr16 + test_fr_fr fr63,fr20 + fdmas fr28,fr12,fr60 + test_fr_fr fr60,fr12 + test_fr_fr fr62,fr12 + fdmas fr28,fr16,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + fdmas fr28,fr20,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + fdmas fr28,fr24,fr60 + test_fr_fr fr60,fr24 + test_fr_fr fr62,fr24 + fdmas fr28,fr28,fr60 + test_fr_fr fr60,fr28 + test_fr_fr fr62,fr28 + fdmas fr28,fr32,fr60 + test_fr_fr fr60,fr32 + test_fr_fr fr61,fr36 + test_fr_fr fr62,fr32 + test_fr_fr fr63,fr36 + fdmas fr28,fr36,fr60 + test_fr_fr fr60,fr36 + test_fr_fr fr62,fr36 + fdmas fr28,fr40,fr60 + test_fr_fr fr60,fr40 + test_fr_fr fr62,fr40 + fdmas fr28,fr44,fr60 + test_fr_fr fr60,fr44 + test_fr_fr fr62,fr44 + fdmas fr28,fr48,fr60 + test_fr_fr fr60,fr48 + test_fr_fr fr62,fr48 + fdmas fr28,fr52,fr60 + test_fr_fr fr60,fr52 + test_fr_fr fr62,fr52 + + fdmas fr28,fr8,fr60 + test_fr_fr fr60,fr8 + test_fr_fr fr61,fr16 + test_fr_fr fr61,fr20 + test_fr_fr fr62,fr8 + test_fr_fr fr63,fr16 + test_fr_fr fr63,fr20 + fdmas fr8,fr28,fr60 + test_fr_fr fr60,fr8 + test_fr_fr fr61,fr16 + test_fr_fr fr61,fr20 + test_fr_fr fr62,fr8 + test_fr_fr fr63,fr16 + test_fr_fr fr63,fr20 + + fdmas fr32,fr36,fr60 + test_fr_fr fr60,fr40 + test_fr_fr fr62,fr40 + + pass diff --git a/sim/testsuite/sim/frv/fdmovs.cgs b/sim/testsuite/sim/frv/fdmovs.cgs new file mode 100644 index 0000000..58e9607 --- /dev/null +++ b/sim/testsuite/sim/frv/fdmovs.cgs @@ -0,0 +1,45 @@ +# frv testcase for fdmovs $FRj,$FRk +# mach: frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global fdmovs +fdmovs: + set_fr_fr fr4,fr1 + fdmovs fr0,fr2 + test_fr_fr fr0,fr2 + test_fr_fr fr4,fr3 + set_fr_fr fr12,fr9 + fdmovs fr8,fr2 + test_fr_fr fr8,fr2 + test_fr_fr fr12,fr3 + set_fr_fr fr20,fr17 + fdmovs fr16,fr2 + test_fr_fr fr16,fr2 + test_fr_fr fr20,fr3 + set_fr_fr fr28,fr25 + fdmovs fr24,fr2 + test_fr_fr fr24,fr2 + test_fr_fr fr28,fr3 + set_fr_fr fr36,fr33 + fdmovs fr32,fr2 + test_fr_fr fr32,fr2 + test_fr_fr fr36,fr3 + set_fr_fr fr44,fr41 + fdmovs fr40,fr2 + test_fr_fr fr40,fr2 + test_fr_fr fr44,fr3 + set_fr_fr fr52,fr49 + fdmovs fr48,fr2 + test_fr_fr fr48,fr2 + test_fr_fr fr52,fr3 + set_fr_fr fr60,fr57 + fdmovs fr56,fr2 + test_fr_iimmed 0x7fc00000,fr2 + test_fr_iimmed 0x7f800001,fr3 + + pass diff --git a/sim/testsuite/sim/frv/fdmss.cgs b/sim/testsuite/sim/frv/fdmss.cgs new file mode 100644 index 0000000..5457a1e --- /dev/null +++ b/sim/testsuite/sim/frv/fdmss.cgs @@ -0,0 +1,235 @@ +# frv testcase for fdmss $FRi,$FRj,$FRk +# mach: frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + load_float_constants1 + load_float_constants2 + load_float_constants3 + + .global fdmss +fdmss: + fdmss fr16,fr4,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + fdmss fr16,fr8,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr28 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr28 + fdmss fr16,fr12,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + fdmss fr16,fr16,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr16 + test_fr_fr fr61,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr16 + test_fr_fr fr63,fr20 + fdmss fr16,fr20,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr16 + test_fr_fr fr61,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr16 + test_fr_fr fr63,fr20 + fdmss fr16,fr24,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + fdmss fr16,fr28,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr8 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr8 + fdmss fr16,fr32,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + fdmss fr16,fr36,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + fdmss fr16,fr40,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + fdmss fr16,fr44,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + fdmss fr16,fr48,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + + fdmss fr20,fr4,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + fdmss fr20,fr8,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr28 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr28 + fdmss fr20,fr12,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + fdmss fr20,fr16,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr16 + test_fr_fr fr61,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr16 + test_fr_fr fr63,fr20 + fdmss fr20,fr20,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr16 + test_fr_fr fr61,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr16 + test_fr_fr fr63,fr20 + fdmss fr20,fr24,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + fdmss fr20,fr28,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr8 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr8 + fdmss fr20,fr32,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + fdmss fr20,fr36,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + fdmss fr20,fr40,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + fdmss fr20,fr44,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + fdmss fr20,fr48,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + + fdmss fr28,fr0,fr60 + test_fr_fr fr60,fr0 + test_fr_fr fr62,fr0 + fdmss fr28,fr4,fr60 + test_fr_fr fr60,fr4 + test_fr_fr fr62,fr4 + fdmss fr28,fr8,fr60 + test_fr_fr fr60,fr8 + test_fr_fr fr61,fr32 + test_fr_fr fr62,fr8 + test_fr_fr fr63,fr32 + fdmss fr28,fr12,fr60 + test_fr_fr fr60,fr12 + test_fr_fr fr62,fr12 + fdmss fr28,fr16,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr28 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr28 + fdmss fr28,fr20,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr28 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr28 + fdmss fr28,fr24,fr60 + test_fr_fr fr60,fr24 + test_fr_fr fr62,fr24 + fdmss fr28,fr28,fr60 + test_fr_fr fr60,fr28 + test_fr_fr fr61,fr20 + test_fr_fr fr61,fr16 + test_fr_fr fr62,fr28 + test_fr_fr fr63,fr20 + test_fr_fr fr63,fr16 + fdmss fr28,fr32,fr60 + test_fr_fr fr60,fr32 + test_fr_fr fr61,fr8 + test_fr_fr fr62,fr32 + test_fr_fr fr63,fr8 + fdmss fr28,fr36,fr60 + test_fr_fr fr60,fr36 + test_fr_fr fr62,fr36 + fdmss fr28,fr40,fr60 + test_fr_fr fr60,fr40 + test_fr_fr fr62,fr40 + fdmss fr28,fr44,fr60 + test_fr_fr fr60,fr44 + test_fr_fr fr62,fr44 + fdmss fr28,fr48,fr60 + test_fr_fr fr60,fr48 + test_fr_fr fr62,fr48 + fdmss fr28,fr52,fr60 + test_fr_fr fr60,fr52 + test_fr_fr fr62,fr52 + + fdmss fr28,fr8,fr60 + test_fr_fr fr60,fr8 + test_fr_fr fr61,fr32 + test_fr_fr fr62,fr8 + test_fr_fr fr63,fr32 + fdmss fr8,fr28,fr60 + test_fr_fr fr60,fr8 + test_fr_fr fr62,fr8 + + fdmss fr32,fr36,fr60 + test_fr_fr fr60,fr40 + test_fr_fr fr61,fr8 + test_fr_fr fr62,fr40 + test_fr_fr fr63,fr8 + + pass diff --git a/sim/testsuite/sim/frv/fdmulcs.cgs b/sim/testsuite/sim/frv/fdmulcs.cgs new file mode 100644 index 0000000..a7cb159 --- /dev/null +++ b/sim/testsuite/sim/frv/fdmulcs.cgs @@ -0,0 +1,201 @@ +# frv testcase for fdmulcs $FRi,$FRj,$FRk +# mach: fr500 fr550 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + load_float_constants1 + + .global fdmulcs +fdmulcs: + fdmulcs fr16,fr4,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmulcs fr16,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmulcs fr16,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmulcs fr16,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmulcs fr16,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmulcs fr16,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmulcs fr16,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmulcs fr16,fr32,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmulcs fr16,fr36,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmulcs fr16,fr40,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmulcs fr16,fr44,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmulcs fr16,fr48,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + + fdmulcs fr20,fr4,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmulcs fr20,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmulcs fr20,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmulcs fr20,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr3,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr2,fr20 + fdmulcs fr20,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmulcs fr20,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmulcs fr20,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmulcs fr20,fr32,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmulcs fr20,fr36,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmulcs fr20,fr40,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmulcs fr20,fr44,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmulcs fr20,fr48,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + + fdmulcs fr28,fr0,fr2 + test_fr_fr fr2,fr0 + test_fr_fr fr3,fr0 + fdmulcs fr28,fr4,fr2 + test_fr_fr fr2,fr4 + test_fr_fr fr3,fr4 + fdmulcs fr28,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr8 + fdmulcs fr28,fr12,fr2 + test_fr_fr fr2,fr12 + test_fr_fr fr3,fr12 + fdmulcs fr28,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmulcs fr28,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmulcs fr28,fr24,fr2 + test_fr_fr fr2,fr24 + test_fr_fr fr3,fr24 + fdmulcs fr28,fr28,fr2 + test_fr_fr fr2,fr28 + test_fr_fr fr3,fr28 + fdmulcs fr28,fr32,fr2 + test_fr_fr fr2,fr32 + test_fr_fr fr3,fr32 + fdmulcs fr28,fr36,fr2 + test_fr_fr fr2,fr36 + test_fr_fr fr3,fr36 + fdmulcs fr28,fr40,fr2 + test_fr_fr fr2,fr40 + test_fr_fr fr3,fr40 + fdmulcs fr28,fr44,fr2 + test_fr_fr fr2,fr44 + test_fr_fr fr3,fr44 + fdmulcs fr28,fr48,fr2 + test_fr_fr fr2,fr48 + test_fr_fr fr3,fr48 + fdmulcs fr28,fr52,fr2 + test_fr_fr fr2,fr52 + test_fr_fr fr3,fr52 + + fdmulcs fr28,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr8 + fdmulcs fr8,fr28,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr8 + + fdmulcs fr32,fr36,fr2 + test_fr_fr fr2,fr40 + test_fr_fr fr3,fr40 + + set_fr_fr fr32,fr50 ; 2 + set_fr_fr fr28,fr51 ; 1 + set_fr_fr fr44,fr52 ; 9 + set_fr_fr fr36,fr53 ; 3 + fdmulcs fr50,fr52,fr54 ; 2*3, 1*9 + test_fr_fr fr54,fr40 ; 6 + test_fr_fr fr55,fr44 ; 9 + + pass diff --git a/sim/testsuite/sim/frv/fdmuls.cgs b/sim/testsuite/sim/frv/fdmuls.cgs new file mode 100644 index 0000000..2c2c05a --- /dev/null +++ b/sim/testsuite/sim/frv/fdmuls.cgs @@ -0,0 +1,193 @@ +# frv testcase for fdmuls $FRi,$FRj,$FRk +# mach: fr500 fr550 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + load_float_constants1 + + .global fdmuls +fdmuls: + fdmuls fr16,fr4,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmuls fr16,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmuls fr16,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmuls fr16,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmuls fr16,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmuls fr16,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmuls fr16,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmuls fr16,fr32,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmuls fr16,fr36,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmuls fr16,fr40,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmuls fr16,fr44,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmuls fr16,fr48,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + + fdmuls fr20,fr4,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmuls fr20,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmuls fr20,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmuls fr20,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr3,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr2,fr20 + fdmuls fr20,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmuls fr20,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmuls fr20,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmuls fr20,fr32,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmuls fr20,fr36,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmuls fr20,fr40,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmuls fr20,fr44,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmuls fr20,fr48,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + + fdmuls fr28,fr0,fr2 + test_fr_fr fr2,fr0 + test_fr_fr fr3,fr0 + fdmuls fr28,fr4,fr2 + test_fr_fr fr2,fr4 + test_fr_fr fr3,fr4 + fdmuls fr28,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr8 + fdmuls fr28,fr12,fr2 + test_fr_fr fr2,fr12 + test_fr_fr fr3,fr12 + fdmuls fr28,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmuls fr28,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdmuls fr28,fr24,fr2 + test_fr_fr fr2,fr24 + test_fr_fr fr3,fr24 + fdmuls fr28,fr28,fr2 + test_fr_fr fr2,fr28 + test_fr_fr fr3,fr28 + fdmuls fr28,fr32,fr2 + test_fr_fr fr2,fr32 + test_fr_fr fr3,fr32 + fdmuls fr28,fr36,fr2 + test_fr_fr fr2,fr36 + test_fr_fr fr3,fr36 + fdmuls fr28,fr40,fr2 + test_fr_fr fr2,fr40 + test_fr_fr fr3,fr40 + fdmuls fr28,fr44,fr2 + test_fr_fr fr2,fr44 + test_fr_fr fr3,fr44 + fdmuls fr28,fr48,fr2 + test_fr_fr fr2,fr48 + test_fr_fr fr3,fr48 + fdmuls fr28,fr52,fr2 + test_fr_fr fr2,fr52 + test_fr_fr fr3,fr52 + + fdmuls fr28,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr8 + fdmuls fr8,fr28,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr8 + + fdmuls fr32,fr36,fr2 + test_fr_fr fr2,fr40 + test_fr_fr fr3,fr40 + + pass diff --git a/sim/testsuite/sim/frv/fdnegs.cgs b/sim/testsuite/sim/frv/fdnegs.cgs new file mode 100644 index 0000000..db409cb --- /dev/null +++ b/sim/testsuite/sim/frv/fdnegs.cgs @@ -0,0 +1,25 @@ +# frv testcase for fdnegs $FRj,$FRk +# mach: frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global fdnegs +fdnegs: + set_fr_fr fr8,fr1 + fdnegs fr0,fr2 + test_fr_fr fr2,fr52 + test_fr_fr fr3,fr28 + set_fr_fr fr24,fr13 + fdnegs fr12,fr2 + test_fr_fr fr2,fr24 + test_fr_fr fr3,fr12 + set_fr_fr fr52,fr29 + fdnegs fr28,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr0 + + pass diff --git a/sim/testsuite/sim/frv/fdsads.cgs b/sim/testsuite/sim/frv/fdsads.cgs new file mode 100644 index 0000000..123810d --- /dev/null +++ b/sim/testsuite/sim/frv/fdsads.cgs @@ -0,0 +1,119 @@ +# frv testcase for fdsads $FRi,$FRj,$FRk +# mach: fr500 fr550 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + load_float_constants1 + + .global fdsads +fdsads: + fdsads fr16,fr0,fr2 + test_fr_fr fr2,fr0 + test_fr_fr fr3,fr52 + fdsads fr16,fr4,fr2 + test_fr_fr fr2,fr4 + test_fr_fr fr3,fr48 + fdsads fr16,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr28 + fdsads fr16,fr12,fr2 + test_fr_fr fr2,fr12 + test_fr_fr fr3,fr24 + fdsads fr16,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdsads fr16,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdsads fr16,fr24,fr2 + test_fr_fr fr2,fr24 + test_fr_fr fr3,fr12 + fdsads fr16,fr28,fr2 + test_fr_fr fr2,fr28 + test_fr_fr fr3,fr8 + fdsads fr16,fr32,fr2 + test_fr_fr fr2,fr32 + fdsads fr16,fr36,fr2 + test_fr_fr fr2,fr36 + fdsads fr16,fr40,fr2 + test_fr_fr fr2,fr40 + fdsads fr16,fr44,fr2 + test_fr_fr fr2,fr44 + fdsads fr16,fr48,fr2 + test_fr_fr fr2,fr48 + test_fr_fr fr3,fr4 + fdsads fr16,fr52,fr2 + test_fr_fr fr2,fr52 + test_fr_fr fr3,fr0 + + fdsads fr20,fr0,fr2 + test_fr_fr fr2,fr0 + test_fr_fr fr3,fr52 + fdsads fr20,fr4,fr2 + test_fr_fr fr2,fr4 + test_fr_fr fr3,fr48 + fdsads fr20,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr28 + fdsads fr20,fr12,fr2 + test_fr_fr fr2,fr12 + test_fr_fr fr3,fr24 + fdsads fr20,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdsads fr20,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdsads fr20,fr24,fr2 + test_fr_fr fr2,fr24 + test_fr_fr fr3,fr12 + fdsads fr20,fr28,fr2 + test_fr_fr fr2,fr28 + test_fr_fr fr3,fr8 + fdsads fr20,fr32,fr2 + test_fr_fr fr2,fr32 + fdsads fr20,fr36,fr2 + test_fr_fr fr2,fr36 + fdsads fr20,fr40,fr2 + test_fr_fr fr2,fr40 + fdsads fr20,fr44,fr2 + test_fr_fr fr2,fr44 + fdsads fr20,fr48,fr2 + test_fr_fr fr2,fr48 + test_fr_fr fr3,fr4 + fdsads fr20,fr52,fr2 + test_fr_fr fr2,fr52 + test_fr_fr fr3,fr0 + + fdsads fr8,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fdsads fr12,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fdsads fr24,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fdsads fr28,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr32 + test_fr_fr fr3,fr32 + + fdsads fr36,fr40,fr2 + test_fr_fr fr2,fr44 + + pass + + diff --git a/sim/testsuite/sim/frv/fdsqrts.cgs b/sim/testsuite/sim/frv/fdsqrts.cgs new file mode 100644 index 0000000..6026b93 --- /dev/null +++ b/sim/testsuite/sim/frv/fdsqrts.cgs @@ -0,0 +1,17 @@ +# frv testcase for fdsqrts $FRj,$FRk +# mach: frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global fdsqrts +fdsqrts: + set_fr_iimmed 0x4049,0x0fdb,fr45 ; 3.141592654 + fdsqrts fr44,fr2 ; 9.0 + test_fr_fr fr2,fr36 ; 3.0 + test_fr_iimmed 0x3fe2dfc5,fr3 ; 1.7724539 + + pass diff --git a/sim/testsuite/sim/frv/fdstoi.cgs b/sim/testsuite/sim/frv/fdstoi.cgs new file mode 100644 index 0000000..5c79e49 --- /dev/null +++ b/sim/testsuite/sim/frv/fdstoi.cgs @@ -0,0 +1,23 @@ +# frv testcase for fdstoi $FRj,$FRk +# mach: frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global fdstoi +fdstoi: + set_fr_fr fr20,fr17 + fdstoi fr16,fr2 + test_fr_iimmed 0,fr2 + test_fr_iimmed 0,fr3 + + set_fr_iimmed 0xce05,0x4904,fr2 + set_fr_fr fr32,fr3 + fdstoi fr2,fr2 + test_fr_iimmed 0xdeadbf00,fr2 + test_fr_iimmed 0x00000002,fr3 + + pass diff --git a/sim/testsuite/sim/frv/fdsubs.cgs b/sim/testsuite/sim/frv/fdsubs.cgs new file mode 100644 index 0000000..93dae46 --- /dev/null +++ b/sim/testsuite/sim/frv/fdsubs.cgs @@ -0,0 +1,117 @@ +# frv testcase for fdsubs $FRi,$FRj,$FRk +# mach: fr500 fr550 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + load_float_constants1 + + .global fdsubs +fdsubs: + fdsubs fr0,fr16,fr2 + test_fr_fr fr2,fr0 + test_fr_fr fr3,fr0 + fdsubs fr4,fr16,fr2 + test_fr_fr fr2,fr4 + test_fr_fr fr3,fr4 + fdsubs fr8,fr16,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr8 + fdsubs fr12,fr16,fr2 + test_fr_fr fr2,fr12 + test_fr_fr fr3,fr12 + fdsubs fr16,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdsubs fr20,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdsubs fr24,fr16,fr2 + test_fr_fr fr2,fr24 + test_fr_fr fr3,fr24 + fdsubs fr28,fr16,fr2 + test_fr_fr fr2,fr28 + test_fr_fr fr3,fr28 + fdsubs fr32,fr16,fr2 + test_fr_fr fr2,fr32 + test_fr_fr fr3,fr32 + fdsubs fr36,fr16,fr2 + test_fr_fr fr2,fr36 + test_fr_fr fr3,fr36 + fdsubs fr40,fr16,fr2 + test_fr_fr fr2,fr40 + test_fr_fr fr3,fr40 + fdsubs fr44,fr16,fr2 + test_fr_fr fr2,fr44 + test_fr_fr fr3,fr44 + fdsubs fr48,fr16,fr2 + test_fr_fr fr2,fr48 + test_fr_fr fr3,fr48 + fdsubs fr52,fr16,fr2 + test_fr_fr fr2,fr52 + test_fr_fr fr3,fr52 + + fdsubs fr0,fr20,fr2 + test_fr_fr fr2,fr0 + test_fr_fr fr3,fr0 + fdsubs fr4,fr20,fr2 + test_fr_fr fr2,fr4 + test_fr_fr fr3,fr4 + fdsubs fr8,fr20,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr8 + fdsubs fr12,fr20,fr2 + test_fr_fr fr2,fr12 + test_fr_fr fr3,fr12 + fdsubs fr16,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdsubs fr20,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fdsubs fr24,fr20,fr2 + test_fr_fr fr2,fr24 + test_fr_fr fr3,fr24 + fdsubs fr28,fr20,fr2 + test_fr_fr fr2,fr28 + test_fr_fr fr3,fr28 + fdsubs fr32,fr20,fr2 + test_fr_fr fr2,fr32 + test_fr_fr fr3,fr32 + fdsubs fr36,fr20,fr2 + test_fr_fr fr2,fr36 + test_fr_fr fr3,fr36 + fdsubs fr40,fr20,fr2 + test_fr_fr fr2,fr40 + test_fr_fr fr3,fr40 + fdsubs fr44,fr20,fr2 + test_fr_fr fr2,fr44 + test_fr_fr fr3,fr44 + fdsubs fr48,fr20,fr2 + test_fr_fr fr2,fr48 + test_fr_fr fr3,fr48 + fdsubs fr52,fr20,fr2 + test_fr_fr fr2,fr52 + test_fr_fr fr3,fr52 + + fdsubs fr32,fr36,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr8 + + fdsubs fr44,fr40,fr2 + test_fr_fr fr2,fr36 + test_fr_fr fr3,fr36 + + pass + + diff --git a/sim/testsuite/sim/frv/fdtoi.cgs b/sim/testsuite/sim/frv/fdtoi.cgs new file mode 100644 index 0000000..1749852 --- /dev/null +++ b/sim/testsuite/sim/frv/fdtoi.cgs @@ -0,0 +1,32 @@ +# frv testcase for fdtoi $FRj,$FRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global fdtoi +fdtoi: + set_fr_iimmed 0,0,fr2 + set_fr_iimmed 0,0,fr3 + fdtoi fr2,fr2 + test_fr_iimmed 0,fr2 + + set_fr_iimmed 0x4000,0x0000,fr2 + set_fr_iimmed 0x0000,0x0000,fr3 + fdtoi fr2,fr2 + test_fr_iimmed 0x00000002,fr2 + + set_fr_iimmed 0xc1c0,0xa920,fr2 + set_fr_iimmed 0x8880,0x0000,fr3 + fdtoi fr2,fr2 + test_fr_iimmed 0xdeadbeef,fr2 + + set_gr_limmed 0x4031,0x0000,gr8 + set_gr_limmed 0x0000,0x0000,gr9 + movgfd gr8,fr0 + fdtoi fr0,fr0 + test_fr_iimmed 17,fr0 + + pass diff --git a/sim/testsuite/sim/frv/fitod.cgs b/sim/testsuite/sim/frv/fitod.cgs new file mode 100644 index 0000000..62ef1f2 --- /dev/null +++ b/sim/testsuite/sim/frv/fitod.cgs @@ -0,0 +1,26 @@ +# frv testcase for fitod $FRj,$FRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global fitod +fitod: + set_fr_iimmed 0,0,fr2 + fitod fr2,fr2 + test_fr_iimmed 0,fr2 + test_fr_iimmed 0,fr3 + + set_fr_iimmed 0x0000,0x0002,fr2 + fitod fr2,fr2 + test_fr_iimmed 0x40000000,fr2 + test_fr_iimmed 0x00000000,fr3 + + set_fr_iimmed 0xdead,0xbeef,fr2 + fitod fr2,fr2 + test_fr_iimmed 0xc1c0a920,fr2 + test_fr_iimmed 0x88800000,fr3 + + pass diff --git a/sim/testsuite/sim/frv/fitos.cgs b/sim/testsuite/sim/frv/fitos.cgs new file mode 100644 index 0000000..2afe290 --- /dev/null +++ b/sim/testsuite/sim/frv/fitos.cgs @@ -0,0 +1,25 @@ +# frv testcase for fitos $FRj,$FRk +# mach: fr500 fr550 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global fitos +fitos: + set_fr_iimmed 0,0,fr1 + fitos fr1,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + + set_fr_iimmed 0x0000,0x0002,fr1 + fitos fr1,fr1 + test_fr_fr fr1,fr32 + + set_fr_iimmed 0xdead,0xbeef,fr1 + fitos fr1,fr1 + test_fr_iimmed 0xce054904,fr1 + + pass diff --git a/sim/testsuite/sim/frv/fmad.cgs b/sim/testsuite/sim/frv/fmad.cgs new file mode 100644 index 0000000..64fee9c --- /dev/null +++ b/sim/testsuite/sim/frv/fmad.cgs @@ -0,0 +1,161 @@ +# frv testcase for fmad $FRi,$FRj,$FRk +# mach: frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + load_float_constants1 + + .global fmad +fmad: + fmad fr16,fr4,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr4 + fmad fr16,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr8 + fmad fr16,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr12 + fmad fr16,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fmad fr16,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fmad fr16,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr24 + fmad fr16,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr28 + fmad fr16,fr32,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr32 + fmad fr16,fr36,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr36 + fmad fr16,fr40,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr40 + fmad fr16,fr44,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr44 + fmad fr16,fr48,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr48 + + fmad fr20,fr4,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr4 + fmad fr20,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr8 + fmad fr20,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr12 + fmad fr20,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fmad fr20,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fmad fr20,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr24 + fmad fr20,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr28 + fmad fr20,fr32,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr32 + fmad fr20,fr36,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr36 + fmad fr20,fr40,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr40 + fmad fr20,fr44,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr44 + fmad fr20,fr48,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr48 + + fmad fr28,fr0,fr2 + test_fr_fr fr2,fr0 + fmad fr28,fr4,fr2 + test_fr_fr fr2,fr4 + fmad fr28,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fmad fr28,fr12,fr2 + test_fr_fr fr2,fr12 + fmad fr28,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmad fr28,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmad fr28,fr24,fr2 + test_fr_fr fr2,fr24 + fmad fr28,fr28,fr2 + test_fr_fr fr2,fr28 + fmad fr28,fr32,fr2 + test_fr_fr fr2,fr32 + test_fr_fr fr3,fr36 + fmad fr28,fr36,fr2 + test_fr_fr fr2,fr36 + fmad fr28,fr40,fr2 + test_fr_fr fr2,fr40 + fmad fr28,fr44,fr2 + test_fr_fr fr2,fr44 + fmad fr28,fr48,fr2 + test_fr_fr fr2,fr48 + fmad fr28,fr52,fr2 + test_fr_fr fr2,fr52 + + fmad fr28,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fmad fr8,fr28,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + + fmad fr32,fr36,fr2 + test_fr_fr fr2,fr40 + + pass diff --git a/sim/testsuite/sim/frv/fmaddd.cgs b/sim/testsuite/sim/frv/fmaddd.cgs new file mode 100644 index 0000000..bfa816f --- /dev/null +++ b/sim/testsuite/sim/frv/fmaddd.cgs @@ -0,0 +1,143 @@ +# frv testcase for fmaddd $GRi,$GRj,$GRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + double_constants + start + load_double_constants + + .global fmaddd +fmaddd: + set_dfr_dfr fr16,fr2 + fmaddd fr16,fr4,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmaddd fr16,fr8,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmaddd fr16,fr12,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmaddd fr16,fr16,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmaddd fr16,fr20,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmaddd fr16,fr24,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmaddd fr16,fr28,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmaddd fr16,fr32,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmaddd fr16,fr36,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmaddd fr16,fr40,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmaddd fr16,fr44,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmaddd fr16,fr48,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + + fmaddd fr20,fr4,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmaddd fr20,fr8,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmaddd fr20,fr12,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmaddd fr20,fr16,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmaddd fr20,fr20,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmaddd fr20,fr24,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmaddd fr20,fr28,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmaddd fr20,fr32,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmaddd fr20,fr36,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmaddd fr20,fr40,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmaddd fr20,fr44,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmaddd fr20,fr48,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + + set_dfr_dfr fr16,fr2 + fmaddd fr28,fr0,fr2 + test_dfr_dfr fr2,fr0 + set_dfr_dfr fr16,fr2 + fmaddd fr28,fr4,fr2 + test_dfr_dfr fr2,fr4 + set_dfr_dfr fr16,fr2 + fmaddd fr28,fr8,fr2 + test_dfr_dfr fr2,fr8 + set_dfr_dfr fr16,fr2 + fmaddd fr28,fr12,fr2 + test_dfr_dfr fr2,fr12 + set_dfr_dfr fr16,fr2 + fmaddd fr28,fr16,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + set_dfr_dfr fr16,fr2 + fmaddd fr28,fr20,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + set_dfr_dfr fr16,fr2 + fmaddd fr28,fr24,fr2 + test_dfr_dfr fr2,fr24 + set_dfr_dfr fr16,fr2 + fmaddd fr28,fr28,fr2 + test_dfr_dfr fr2,fr28 + set_dfr_dfr fr16,fr2 + fmaddd fr28,fr32,fr2 + test_dfr_dfr fr2,fr32 + set_dfr_dfr fr16,fr2 + fmaddd fr28,fr36,fr2 + test_dfr_dfr fr2,fr36 + set_dfr_dfr fr16,fr2 + fmaddd fr28,fr40,fr2 + test_dfr_dfr fr2,fr40 + set_dfr_dfr fr16,fr2 + fmaddd fr28,fr44,fr2 + test_dfr_dfr fr2,fr44 + set_dfr_dfr fr16,fr2 + fmaddd fr28,fr48,fr2 + test_dfr_dfr fr2,fr48 + set_dfr_dfr fr16,fr2 + fmaddd fr28,fr52,fr2 + test_dfr_dfr fr2,fr52 + + set_dfr_dfr fr36,fr2 + fmaddd fr28,fr8,fr2 + test_dfr_dfr fr2,fr32 + fmaddd fr8,fr28,fr2 + test_dfr_dfr fr2,fr28 + + set_dfr_dfr fr36,fr2 + fmaddd fr32,fr36,fr2 + test_dfr_dfr fr2,fr44 + + pass diff --git a/sim/testsuite/sim/frv/fmadds.cgs b/sim/testsuite/sim/frv/fmadds.cgs new file mode 100644 index 0000000..128c82a --- /dev/null +++ b/sim/testsuite/sim/frv/fmadds.cgs @@ -0,0 +1,143 @@ +# frv testcase for fmadds $GRi,$GRj,$GRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global fmadds +fmadds: + set_fr_fr fr16,fr1 + fmadds fr16,fr4,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmadds fr16,fr8,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmadds fr16,fr12,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmadds fr16,fr16,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmadds fr16,fr20,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmadds fr16,fr24,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmadds fr16,fr28,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmadds fr16,fr32,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmadds fr16,fr36,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmadds fr16,fr40,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmadds fr16,fr44,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmadds fr16,fr48,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + + fmadds fr20,fr4,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmadds fr20,fr8,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmadds fr20,fr12,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmadds fr20,fr16,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmadds fr20,fr20,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmadds fr20,fr24,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmadds fr20,fr28,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmadds fr20,fr32,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmadds fr20,fr36,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmadds fr20,fr40,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmadds fr20,fr44,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmadds fr20,fr48,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + + set_fr_fr fr16,fr1 + fmadds fr28,fr0,fr1 + test_fr_fr fr1,fr0 + set_fr_fr fr16,fr1 + fmadds fr28,fr4,fr1 + test_fr_fr fr1,fr4 + set_fr_fr fr16,fr1 + fmadds fr28,fr8,fr1 + test_fr_fr fr1,fr8 + set_fr_fr fr16,fr1 + fmadds fr28,fr12,fr1 + test_fr_fr fr1,fr12 + set_fr_fr fr16,fr1 + fmadds fr28,fr16,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + set_fr_fr fr16,fr1 + fmadds fr28,fr20,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + set_fr_fr fr16,fr1 + fmadds fr28,fr24,fr1 + test_fr_fr fr1,fr24 + set_fr_fr fr16,fr1 + fmadds fr28,fr28,fr1 + test_fr_fr fr1,fr28 + set_fr_fr fr16,fr1 + fmadds fr28,fr32,fr1 + test_fr_fr fr1,fr32 + set_fr_fr fr16,fr1 + fmadds fr28,fr36,fr1 + test_fr_fr fr1,fr36 + set_fr_fr fr16,fr1 + fmadds fr28,fr40,fr1 + test_fr_fr fr1,fr40 + set_fr_fr fr16,fr1 + fmadds fr28,fr44,fr1 + test_fr_fr fr1,fr44 + set_fr_fr fr16,fr1 + fmadds fr28,fr48,fr1 + test_fr_fr fr1,fr48 + set_fr_fr fr16,fr1 + fmadds fr28,fr52,fr1 + test_fr_fr fr1,fr52 + + set_fr_fr fr36,fr1 + fmadds fr28,fr8,fr1 + test_fr_fr fr1,fr32 + fmadds fr8,fr28,fr1 + test_fr_fr fr1,fr28 + + set_fr_fr fr36,fr1 + fmadds fr32,fr36,fr1 + test_fr_fr fr1,fr44 + + pass diff --git a/sim/testsuite/sim/frv/fmas.cgs b/sim/testsuite/sim/frv/fmas.cgs new file mode 100644 index 0000000..1e7b1df --- /dev/null +++ b/sim/testsuite/sim/frv/fmas.cgs @@ -0,0 +1,161 @@ +# frv testcase for fmas $FRi,$FRj,$FRk +# mach: fr500 fr550 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + load_float_constants1 + + .global fmas +fmas: + fmas fr16,fr4,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr4 + fmas fr16,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr8 + fmas fr16,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr12 + fmas fr16,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fmas fr16,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fmas fr16,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr24 + fmas fr16,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr28 + fmas fr16,fr32,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr32 + fmas fr16,fr36,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr36 + fmas fr16,fr40,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr40 + fmas fr16,fr44,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr44 + fmas fr16,fr48,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr48 + + fmas fr20,fr4,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr4 + fmas fr20,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr8 + fmas fr20,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr12 + fmas fr20,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fmas fr20,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fmas fr20,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr24 + fmas fr20,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr28 + fmas fr20,fr32,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr32 + fmas fr20,fr36,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr36 + fmas fr20,fr40,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr40 + fmas fr20,fr44,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr44 + fmas fr20,fr48,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr48 + + fmas fr28,fr0,fr2 + test_fr_fr fr2,fr0 + fmas fr28,fr4,fr2 + test_fr_fr fr2,fr4 + fmas fr28,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fmas fr28,fr12,fr2 + test_fr_fr fr2,fr12 + fmas fr28,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmas fr28,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmas fr28,fr24,fr2 + test_fr_fr fr2,fr24 + fmas fr28,fr28,fr2 + test_fr_fr fr2,fr28 + fmas fr28,fr32,fr2 + test_fr_fr fr2,fr32 + test_fr_fr fr3,fr36 + fmas fr28,fr36,fr2 + test_fr_fr fr2,fr36 + fmas fr28,fr40,fr2 + test_fr_fr fr2,fr40 + fmas fr28,fr44,fr2 + test_fr_fr fr2,fr44 + fmas fr28,fr48,fr2 + test_fr_fr fr2,fr48 + fmas fr28,fr52,fr2 + test_fr_fr fr2,fr52 + + fmas fr28,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fmas fr8,fr28,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + + fmas fr32,fr36,fr2 + test_fr_fr fr2,fr40 + + pass diff --git a/sim/testsuite/sim/frv/fmovd.cgs b/sim/testsuite/sim/frv/fmovd.cgs new file mode 100644 index 0000000..938faa2 --- /dev/null +++ b/sim/testsuite/sim/frv/fmovd.cgs @@ -0,0 +1,48 @@ +# frv testcase for fmovd $FRj,$FRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + double_constants + start + load_double_constants + + .global fmovd +fmovd: + fmovd fr0,fr2 + test_dfr_dfr fr0,fr2 + fmovd fr4,fr2 + test_dfr_dfr fr4,fr2 + fmovd fr8,fr2 + test_dfr_dfr fr8,fr2 + fmovd fr12,fr2 + test_dfr_dfr fr12,fr2 + fmovd fr16,fr2 + test_dfr_dfr fr16,fr2 + fmovd fr20,fr2 + test_dfr_dfr fr20,fr2 + fmovd fr24,fr2 + test_dfr_dfr fr24,fr2 + fmovd fr28,fr2 + test_dfr_dfr fr28,fr2 + fmovd fr32,fr2 + test_dfr_dfr fr32,fr2 + fmovd fr36,fr2 + test_dfr_dfr fr36,fr2 + fmovd fr40,fr2 + test_dfr_dfr fr40,fr2 + fmovd fr44,fr2 + test_dfr_dfr fr44,fr2 + fmovd fr48,fr2 + test_dfr_dfr fr48,fr2 + fmovd fr52,fr2 + test_dfr_dfr fr52,fr2 + fmovd fr56,fr2 + test_fr_iimmed 0x7ff80000,fr2 + test_fr_iimmed 0x00000000,fr3 + fmovd fr60,fr2 + test_fr_iimmed 0x7ff00000,fr2 + test_fr_iimmed 0x00000001,fr3 + + pass diff --git a/sim/testsuite/sim/frv/fmovs.cgs b/sim/testsuite/sim/frv/fmovs.cgs new file mode 100644 index 0000000..2a70277 --- /dev/null +++ b/sim/testsuite/sim/frv/fmovs.cgs @@ -0,0 +1,45 @@ +# frv testcase for fmovs $FRj,$FRk +# mach: fr500 fr550 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global fmovs +fmovs: + fmovs fr0,fr1 + test_fr_fr fr0,fr1 + fmovs fr4,fr1 + test_fr_fr fr4,fr1 + fmovs fr8,fr1 + test_fr_fr fr8,fr1 + fmovs fr12,fr1 + test_fr_fr fr12,fr1 + fmovs fr16,fr1 + test_fr_fr fr16,fr1 + fmovs fr20,fr1 + test_fr_fr fr20,fr1 + fmovs fr24,fr1 + test_fr_fr fr24,fr1 + fmovs fr28,fr1 + test_fr_fr fr28,fr1 + fmovs fr32,fr1 + test_fr_fr fr32,fr1 + fmovs fr36,fr1 + test_fr_fr fr36,fr1 + fmovs fr40,fr1 + test_fr_fr fr40,fr1 + fmovs fr44,fr1 + test_fr_fr fr44,fr1 + fmovs fr48,fr1 + test_fr_fr fr48,fr1 + fmovs fr52,fr1 + test_fr_fr fr52,fr1 + fmovs fr56,fr1 + test_fr_iimmed 0x7fc00000,fr1 + fmovs fr60,fr1 + test_fr_iimmed 0x7f800001,fr1 + + pass diff --git a/sim/testsuite/sim/frv/fmsd.cgs b/sim/testsuite/sim/frv/fmsd.cgs new file mode 100644 index 0000000..cd2efbd --- /dev/null +++ b/sim/testsuite/sim/frv/fmsd.cgs @@ -0,0 +1,146 @@ +# frv testcase for fmsd $FRi,$FRj,$FRk +# mach: frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + load_float_constants1 + + .global fmsd +fmsd: + fmsd fr16,fr4,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmsd fr16,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr28 + fmsd fr16,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmsd fr16,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fmsd fr16,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fmsd fr16,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmsd fr16,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr8 + fmsd fr16,fr32,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmsd fr16,fr36,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmsd fr16,fr40,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmsd fr16,fr44,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmsd fr16,fr48,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + + fmsd fr20,fr4,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmsd fr20,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr28 + fmsd fr20,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmsd fr20,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fmsd fr20,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fmsd fr20,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmsd fr20,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr8 + fmsd fr20,fr32,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmsd fr20,fr36,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmsd fr20,fr40,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmsd fr20,fr44,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmsd fr20,fr48,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + + fmsd fr28,fr0,fr2 + test_fr_fr fr2,fr0 + fmsd fr28,fr4,fr2 + test_fr_fr fr2,fr4 + fmsd fr28,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr32 + fmsd fr28,fr12,fr2 + test_fr_fr fr2,fr12 + fmsd fr28,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr28 + fmsd fr28,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr28 + fmsd fr28,fr24,fr2 + test_fr_fr fr2,fr24 + fmsd fr28,fr28,fr2 + test_fr_fr fr2,fr28 + test_fr_fr fr3,fr20 + test_fr_fr fr3,fr16 + fmsd fr28,fr32,fr2 + test_fr_fr fr2,fr32 + test_fr_fr fr3,fr8 + fmsd fr28,fr36,fr2 + test_fr_fr fr2,fr36 + fmsd fr28,fr40,fr2 + test_fr_fr fr2,fr40 + fmsd fr28,fr44,fr2 + test_fr_fr fr2,fr44 + fmsd fr28,fr48,fr2 + test_fr_fr fr2,fr48 + fmsd fr28,fr52,fr2 + test_fr_fr fr2,fr52 + + fmsd fr28,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr32 + fmsd fr8,fr28,fr2 + test_fr_fr fr2,fr8 + + fmsd fr32,fr36,fr2 + test_fr_fr fr2,fr40 + test_fr_fr fr3,fr8 + + pass diff --git a/sim/testsuite/sim/frv/fmss.cgs b/sim/testsuite/sim/frv/fmss.cgs new file mode 100644 index 0000000..defe069 --- /dev/null +++ b/sim/testsuite/sim/frv/fmss.cgs @@ -0,0 +1,146 @@ +# frv testcase for fmss $FRi,$FRj,$FRk +# mach: fr500 fr550 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + load_float_constants1 + + .global fmss +fmss: + fmss fr16,fr4,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmss fr16,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr28 + fmss fr16,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmss fr16,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fmss fr16,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fmss fr16,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmss fr16,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr8 + fmss fr16,fr32,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmss fr16,fr36,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmss fr16,fr40,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmss fr16,fr44,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmss fr16,fr48,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + + fmss fr20,fr4,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmss fr20,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr28 + fmss fr20,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmss fr20,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fmss fr20,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + fmss fr20,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmss fr20,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr8 + fmss fr20,fr32,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmss fr20,fr36,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmss fr20,fr40,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmss fr20,fr44,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + fmss fr20,fr48,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + + fmss fr28,fr0,fr2 + test_fr_fr fr2,fr0 + fmss fr28,fr4,fr2 + test_fr_fr fr2,fr4 + fmss fr28,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr32 + fmss fr28,fr12,fr2 + test_fr_fr fr2,fr12 + fmss fr28,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr28 + fmss fr28,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr28 + fmss fr28,fr24,fr2 + test_fr_fr fr2,fr24 + fmss fr28,fr28,fr2 + test_fr_fr fr2,fr28 + test_fr_fr fr3,fr20 + test_fr_fr fr3,fr16 + fmss fr28,fr32,fr2 + test_fr_fr fr2,fr32 + test_fr_fr fr3,fr8 + fmss fr28,fr36,fr2 + test_fr_fr fr2,fr36 + fmss fr28,fr40,fr2 + test_fr_fr fr2,fr40 + fmss fr28,fr44,fr2 + test_fr_fr fr2,fr44 + fmss fr28,fr48,fr2 + test_fr_fr fr2,fr48 + fmss fr28,fr52,fr2 + test_fr_fr fr2,fr52 + + fmss fr28,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr32 + fmss fr8,fr28,fr2 + test_fr_fr fr2,fr8 + + fmss fr32,fr36,fr2 + test_fr_fr fr2,fr40 + test_fr_fr fr3,fr8 + + pass diff --git a/sim/testsuite/sim/frv/fmsubd.cgs b/sim/testsuite/sim/frv/fmsubd.cgs new file mode 100644 index 0000000..6b4c943 --- /dev/null +++ b/sim/testsuite/sim/frv/fmsubd.cgs @@ -0,0 +1,144 @@ +# frv testcase for fmsubd $GRi,$GRj,$GRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + double_constants + start + load_double_constants + + .global fmsubd +fmsubd: + set_dfr_dfr fr16,fr2 + fmsubd fr16,fr4,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmsubd fr16,fr8,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmsubd fr16,fr12,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmsubd fr16,fr16,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmsubd fr16,fr20,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmsubd fr16,fr24,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmsubd fr16,fr28,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmsubd fr16,fr32,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmsubd fr16,fr36,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmsubd fr16,fr40,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmsubd fr16,fr44,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmsubd fr16,fr48,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + + fmsubd fr20,fr4,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmsubd fr20,fr8,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmsubd fr20,fr12,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmsubd fr20,fr16,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmsubd fr20,fr20,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmsubd fr20,fr24,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmsubd fr20,fr28,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmsubd fr20,fr32,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmsubd fr20,fr36,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmsubd fr20,fr40,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmsubd fr20,fr44,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmsubd fr20,fr48,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + + set_dfr_dfr fr16,fr2 + fmsubd fr28,fr0,fr2 + test_dfr_dfr fr2,fr0 + set_dfr_dfr fr16,fr2 + fmsubd fr28,fr4,fr2 + test_dfr_dfr fr2,fr4 + set_dfr_dfr fr16,fr2 + fmsubd fr28,fr8,fr2 + test_dfr_dfr fr2,fr8 + set_dfr_dfr fr16,fr2 + fmsubd fr28,fr12,fr2 + test_dfr_dfr fr2,fr12 + set_dfr_dfr fr16,fr2 + fmsubd fr28,fr16,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + set_dfr_dfr fr16,fr2 + fmsubd fr28,fr20,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + set_dfr_dfr fr16,fr2 + fmsubd fr28,fr24,fr2 + test_dfr_dfr fr2,fr24 + set_dfr_dfr fr16,fr2 + fmsubd fr28,fr28,fr2 + test_dfr_dfr fr2,fr28 + set_dfr_dfr fr16,fr2 + fmsubd fr28,fr32,fr2 + test_dfr_dfr fr2,fr32 + set_dfr_dfr fr16,fr2 + fmsubd fr28,fr36,fr2 + test_dfr_dfr fr2,fr36 + set_dfr_dfr fr16,fr2 + fmsubd fr28,fr40,fr2 + test_dfr_dfr fr2,fr40 + set_dfr_dfr fr16,fr2 + fmsubd fr28,fr44,fr2 + test_dfr_dfr fr2,fr44 + set_dfr_dfr fr16,fr2 + fmsubd fr28,fr48,fr2 + test_dfr_dfr fr2,fr48 + set_dfr_dfr fr16,fr2 + fmsubd fr28,fr52,fr2 + test_dfr_dfr fr2,fr52 + + set_dfr_dfr fr32,fr2 + fmsubd fr8,fr8,fr2 + test_dfr_dfr fr2,fr8 + set_dfr_dfr fr36,fr2 + fmsubd fr36,fr36,fr2 + test_dfr_dfr fr2,fr40 + + fmsubd fr32,fr36,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + + pass diff --git a/sim/testsuite/sim/frv/fmsubs.cgs b/sim/testsuite/sim/frv/fmsubs.cgs new file mode 100644 index 0000000..14a5bb3 --- /dev/null +++ b/sim/testsuite/sim/frv/fmsubs.cgs @@ -0,0 +1,144 @@ +# frv testcase for fmsubs $GRi,$GRj,$GRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global fmsubs +fmsubs: + set_fr_fr fr16,fr1 + fmsubs fr16,fr4,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmsubs fr16,fr8,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmsubs fr16,fr12,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmsubs fr16,fr16,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmsubs fr16,fr20,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmsubs fr16,fr24,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmsubs fr16,fr28,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmsubs fr16,fr32,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmsubs fr16,fr36,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmsubs fr16,fr40,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmsubs fr16,fr44,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmsubs fr16,fr48,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + + fmsubs fr20,fr4,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmsubs fr20,fr8,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmsubs fr20,fr12,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmsubs fr20,fr16,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmsubs fr20,fr20,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmsubs fr20,fr24,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmsubs fr20,fr28,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmsubs fr20,fr32,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmsubs fr20,fr36,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmsubs fr20,fr40,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmsubs fr20,fr44,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmsubs fr20,fr48,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + + set_fr_fr fr16,fr1 + fmsubs fr28,fr0,fr1 + test_fr_fr fr1,fr0 + set_fr_fr fr16,fr1 + fmsubs fr28,fr4,fr1 + test_fr_fr fr1,fr4 + set_fr_fr fr16,fr1 + fmsubs fr28,fr8,fr1 + test_fr_fr fr1,fr8 + set_fr_fr fr16,fr1 + fmsubs fr28,fr12,fr1 + test_fr_fr fr1,fr12 + set_fr_fr fr16,fr1 + fmsubs fr28,fr16,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + set_fr_fr fr16,fr1 + fmsubs fr28,fr20,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + set_fr_fr fr16,fr1 + fmsubs fr28,fr24,fr1 + test_fr_fr fr1,fr24 + set_fr_fr fr16,fr1 + fmsubs fr28,fr28,fr1 + test_fr_fr fr1,fr28 + set_fr_fr fr16,fr1 + fmsubs fr28,fr32,fr1 + test_fr_fr fr1,fr32 + set_fr_fr fr16,fr1 + fmsubs fr28,fr36,fr1 + test_fr_fr fr1,fr36 + set_fr_fr fr16,fr1 + fmsubs fr28,fr40,fr1 + test_fr_fr fr1,fr40 + set_fr_fr fr16,fr1 + fmsubs fr28,fr44,fr1 + test_fr_fr fr1,fr44 + set_fr_fr fr16,fr1 + fmsubs fr28,fr48,fr1 + test_fr_fr fr1,fr48 + set_fr_fr fr16,fr1 + fmsubs fr28,fr52,fr1 + test_fr_fr fr1,fr52 + + set_fr_fr fr32,fr1 + fmsubs fr8,fr8,fr1 + test_fr_fr fr1,fr8 + set_fr_fr fr36,fr1 + fmsubs fr36,fr36,fr1 + test_fr_fr fr1,fr40 + + fmsubs fr32,fr36,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + + pass diff --git a/sim/testsuite/sim/frv/fmuld.cgs b/sim/testsuite/sim/frv/fmuld.cgs new file mode 100644 index 0000000..e06ca07 --- /dev/null +++ b/sim/testsuite/sim/frv/fmuld.cgs @@ -0,0 +1,126 @@ +# frv testcase for fmuld $GRi,$GRj,$GRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + double_constants + start + load_double_constants + + .global fmuld +fmuld: + fmuld fr16,fr4,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmuld fr16,fr8,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmuld fr16,fr12,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmuld fr16,fr16,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmuld fr16,fr20,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmuld fr16,fr24,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmuld fr16,fr28,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmuld fr16,fr32,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmuld fr16,fr36,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmuld fr16,fr40,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmuld fr16,fr44,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmuld fr16,fr48,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + + fmuld fr20,fr4,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmuld fr20,fr8,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmuld fr20,fr12,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmuld fr20,fr16,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmuld fr20,fr20,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmuld fr20,fr24,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmuld fr20,fr28,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmuld fr20,fr32,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmuld fr20,fr36,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmuld fr20,fr40,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmuld fr20,fr44,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmuld fr20,fr48,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + + fmuld fr28,fr0,fr2 + test_dfr_dfr fr2,fr0 + fmuld fr28,fr4,fr2 + test_dfr_dfr fr2,fr4 + fmuld fr28,fr8,fr2 + test_dfr_dfr fr2,fr8 + fmuld fr28,fr12,fr2 + test_dfr_dfr fr2,fr12 + fmuld fr28,fr16,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmuld fr28,fr20,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fmuld fr28,fr24,fr2 + test_dfr_dfr fr2,fr24 + fmuld fr28,fr28,fr2 + test_dfr_dfr fr2,fr28 + fmuld fr28,fr32,fr2 + test_dfr_dfr fr2,fr32 + fmuld fr28,fr36,fr2 + test_dfr_dfr fr2,fr36 + fmuld fr28,fr40,fr2 + test_dfr_dfr fr2,fr40 + fmuld fr28,fr44,fr2 + test_dfr_dfr fr2,fr44 + fmuld fr28,fr48,fr2 + test_dfr_dfr fr2,fr48 + fmuld fr28,fr52,fr2 + test_dfr_dfr fr2,fr52 + + fmuld fr28,fr8,fr2 + test_dfr_dfr fr2,fr8 + fmuld fr8,fr28,fr2 + test_dfr_dfr fr2,fr8 + + fmuld fr32,fr36,fr2 + test_dfr_dfr fr2,fr40 + + pass diff --git a/sim/testsuite/sim/frv/fmuls.cgs b/sim/testsuite/sim/frv/fmuls.cgs new file mode 100644 index 0000000..a92fa1e --- /dev/null +++ b/sim/testsuite/sim/frv/fmuls.cgs @@ -0,0 +1,125 @@ +# frv testcase for fmuls $GRi,$GRj,$GRk +# mach: fr500 fr550 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global fmuls +fmuls: + fmuls fr16,fr4,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmuls fr16,fr8,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmuls fr16,fr12,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmuls fr16,fr16,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmuls fr16,fr20,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmuls fr16,fr24,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmuls fr16,fr28,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmuls fr16,fr32,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmuls fr16,fr36,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmuls fr16,fr40,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmuls fr16,fr44,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmuls fr16,fr48,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + + fmuls fr20,fr4,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmuls fr20,fr8,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmuls fr20,fr12,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmuls fr20,fr16,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmuls fr20,fr20,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmuls fr20,fr24,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmuls fr20,fr28,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmuls fr20,fr32,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmuls fr20,fr36,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmuls fr20,fr40,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmuls fr20,fr44,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmuls fr20,fr48,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + + fmuls fr28,fr0,fr1 + test_fr_fr fr1,fr0 + fmuls fr28,fr4,fr1 + test_fr_fr fr1,fr4 + fmuls fr28,fr8,fr1 + test_fr_fr fr1,fr8 + fmuls fr28,fr12,fr1 + test_fr_fr fr1,fr12 + fmuls fr28,fr16,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmuls fr28,fr20,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fmuls fr28,fr24,fr1 + test_fr_fr fr1,fr24 + fmuls fr28,fr28,fr1 + test_fr_fr fr1,fr28 + fmuls fr28,fr32,fr1 + test_fr_fr fr1,fr32 + fmuls fr28,fr36,fr1 + test_fr_fr fr1,fr36 + fmuls fr28,fr40,fr1 + test_fr_fr fr1,fr40 + fmuls fr28,fr44,fr1 + test_fr_fr fr1,fr44 + fmuls fr28,fr48,fr1 + test_fr_fr fr1,fr48 + fmuls fr28,fr52,fr1 + test_fr_fr fr1,fr52 + + fmuls fr28,fr8,fr1 + test_fr_fr fr1,fr8 + fmuls fr8,fr28,fr1 + test_fr_fr fr1,fr8 + + fmuls fr32,fr36,fr1 + test_fr_fr fr1,fr40 + + pass diff --git a/sim/testsuite/sim/frv/fnegd.cgs b/sim/testsuite/sim/frv/fnegd.cgs new file mode 100644 index 0000000..c18721b --- /dev/null +++ b/sim/testsuite/sim/frv/fnegd.cgs @@ -0,0 +1,26 @@ +# frv testcase for fnegd $FRj,$FRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + double_constants + start + load_double_constants + + .global fnegd +fnegd: + fnegd fr0,fr2 + test_dfr_dfr fr2,fr52 + fnegd fr8,fr2 + test_dfr_dfr fr2,fr28 + fnegd fr12,fr2 + test_dfr_dfr fr2,fr24 + fnegd fr24,fr2 + test_dfr_dfr fr2,fr12 + fnegd fr28,fr2 + test_dfr_dfr fr2,fr8 + fnegd fr52,fr2 + test_dfr_dfr fr2,fr0 + + pass diff --git a/sim/testsuite/sim/frv/fnegs.cgs b/sim/testsuite/sim/frv/fnegs.cgs new file mode 100644 index 0000000..fdb8770 --- /dev/null +++ b/sim/testsuite/sim/frv/fnegs.cgs @@ -0,0 +1,25 @@ +# frv testcase for fnegs $FRj,$FRk +# mach: fr500 fr550 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global fnegs +fnegs: + fnegs fr0,fr1 + test_fr_fr fr1,fr52 + fnegs fr8,fr1 + test_fr_fr fr1,fr28 + fnegs fr12,fr1 + test_fr_fr fr1,fr24 + fnegs fr24,fr1 + test_fr_fr fr1,fr12 + fnegs fr28,fr1 + test_fr_fr fr1,fr8 + fnegs fr52,fr1 + test_fr_fr fr1,fr0 + + pass diff --git a/sim/testsuite/sim/frv/fnop.cgs b/sim/testsuite/sim/frv/fnop.cgs new file mode 100644 index 0000000..5e48384 --- /dev/null +++ b/sim/testsuite/sim/frv/fnop.cgs @@ -0,0 +1,12 @@ +# frv testcase for fnop +# mach: fr500 fr550 frv + + .include "testutils.inc" + + start + + .global fnop +fnop: + fnop + + pass diff --git a/sim/testsuite/sim/frv/fr400/addss.cgs b/sim/testsuite/sim/frv/fr400/addss.cgs new file mode 100644 index 0000000..631d574 --- /dev/null +++ b/sim/testsuite/sim/frv/fr400/addss.cgs @@ -0,0 +1,36 @@ +# frv testcase for addss $GRi,$GRj,$GRk +# mach: fr400 + + .include "../testutils.inc" + + start + + .global add +add_nosaturate: + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + addss gr7,gr8,gr8 + test_gr_immed 3,gr8 +add_saturate_pos: + set_gr_limmed 0x7fff,0xffff,gr7 + set_gr_immed 1,gr8 + addss gr7,gr8,gr8 + test_gr_limmed 0x7fff,0xffff,gr8 + + set_gr_limmed 0x4000,0x0000,gr7 + set_gr_limmed 0x4000,0x0000,gr8 + addss gr7,gr8,gr8 + test_gr_limmed 0x7fff,0xffff,gr8 + +add_saturate_neg: + set_gr_limmed 0x8000,0x0000,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + addss gr7,gr8,gr8 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0x8000,0x0001,gr7 + set_gr_limmed 0x8000,0x0001,gr8 + addss gr7,gr8,gr8 + test_gr_limmed 0x8000,0x0000,gr8 + + pass diff --git a/sim/testsuite/sim/frv/fr400/allinsn.exp b/sim/testsuite/sim/frv/fr400/allinsn.exp new file mode 100644 index 0000000..53394ec --- /dev/null +++ b/sim/testsuite/sim/frv/fr400/allinsn.exp @@ -0,0 +1,19 @@ +# FRV simulator testsuite. + +if [istarget frv*-*] { + # load support procs (none yet) + # load_lib cgen.exp + # all machines + set all_machs "fr400 fr550" + set cpu_option -mcpu + + # The .cgs suffix is for "cgen .s". + foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.cgs]] { + # If we're only testing specific files and this isn't one of them, + # skip it. + if ![runtest_file_p $runtests $src] { + continue + } + run_sim_test $src $all_machs + } +} diff --git a/sim/testsuite/sim/frv/fr400/csdiv.cgs b/sim/testsuite/sim/frv/fr400/csdiv.cgs new file mode 100644 index 0000000..9fa6d8c --- /dev/null +++ b/sim/testsuite/sim/frv/fr400/csdiv.cgs @@ -0,0 +1,187 @@ +# frv testcase for csdiv $GRi,$GRj,$GRk,$CCi,$cond +# mach: all + + .include "../testutils.inc" + + start + + .global csdiv +csdiv: + set_spr_immed 0x1b1b,cccr + + ; simple division 12 / 3 + set_gr_immed 3,gr3 + set_gr_immed 12,gr1 + csdiv gr1,gr3,gr2,cc4,1 + test_gr_immed 4,gr2 + + ; Random example + set_gr_limmed 0x0123,0x4567,gr3 + set_gr_limmed 0xfedc,0xba98,gr1 + csdiv gr1,gr3,gr2,cc4,1 + test_gr_immed -1,gr2 + + ; Special case from the Arch Spec Vol 2 + and_spr_immed -33,isr ; turn off isr.edem + ; set up exception handler + set_psr_et 1 + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr17 + inc_gr_immed 0x170,gr17 ; address of exception handler + set_bctrlr_0_0 gr17 + set_spr_immed 128,lcr + set_gr_immed 0,gr15 + + ; divide will cause overflow + set_spr_addr ok1,lr + set_gr_immed -1,gr3 + set_gr_limmed 0x8000,0x0000,gr1 +e1: csdiv gr1,gr3,gr2,cc4,1 + test_gr_immed 1,gr15 + test_gr_limmed 0x8000,0x0000,gr2 + + ; Special case from the Arch Spec Vol 2 + or_spr_immed 0x20,isr ; turn on isr.edem + set_gr_immed -1,gr3 + set_gr_limmed 0x8000,0x0000,gr1 + csdiv gr1,gr3,gr2,cc4,1 + test_gr_limmed 0x7fff,0xffff,gr2 + + ; simple division 12 / 3 + set_gr_immed 3,gr3 + set_gr_immed 12,gr1 + csdiv gr1,gr3,gr2,cc4,0 + test_gr_limmed 0x7fff,0xffff,gr2 + + ; Random example + set_gr_limmed 0x0123,0x4567,gr3 + set_gr_limmed 0xfedc,0xba98,gr1 + csdiv gr1,gr3,gr2,cc4,0 + test_gr_limmed 0x7fff,0xffff,gr2 + + ; Special case from the Arch Spec Vol 2 + and_spr_immed -33,isr ; turn off isr.edem + set_gr_immed -1,gr3 + set_gr_limmed 0x8000,0x0000,gr1 + csdiv gr1,gr3,gr2,cc4,0 + test_gr_limmed 0x7fff,0xffff,gr2 + + or_spr_immed 0x20,isr ; turn on isr.edem + set_gr_immed -1,gr3 + set_gr_limmed 0x8000,0x0000,gr1 + csdiv gr1,gr3,gr2,cc4,0 + test_gr_limmed 0x7fff,0xffff,gr2 + + ; simple division 12 / 3 + set_gr_immed 3,gr3 + set_gr_immed 12,gr1 + csdiv gr1,gr3,gr2,cc5,0 + test_gr_immed 4,gr2 + + ; Random example + set_gr_limmed 0x0123,0x4567,gr3 + set_gr_limmed 0xfedc,0xba98,gr1 + csdiv gr1,gr3,gr2,cc5,0 + test_gr_immed -1,gr2 + + ; Special case from the Arch Spec Vol 2 + and_spr_immed -33,isr ; turn off isr.edem + ; divide will cause overflow + set_spr_addr ok1,lr + set_gr_immed -1,gr3 + set_gr_limmed 0x8000,0x0000,gr1 +e2: csdiv gr1,gr3,gr2,cc5,0 + test_gr_immed 2,gr15 + test_gr_limmed 0x8000,0x0000,gr2 + + ; Special case from the Arch Spec Vol 2 + or_spr_immed 0x20,isr ; turn on isr.edem + set_gr_immed -1,gr3 + set_gr_limmed 0x8000,0x0000,gr1 + csdiv gr1,gr3,gr2,cc5,0 + test_gr_limmed 0x7fff,0xffff,gr2 + + ; simple division 12 / 3 + set_gr_immed 3,gr3 + set_gr_immed 12,gr1 + csdiv gr1,gr3,gr2,cc5,1 + test_gr_limmed 0x7fff,0xffff,gr2 + + ; Random example + set_gr_limmed 0x0123,0x4567,gr3 + set_gr_limmed 0xfedc,0xba98,gr1 + csdiv gr1,gr3,gr2,cc5,1 + test_gr_limmed 0x7fff,0xffff,gr2 + + ; Special case from the Arch Spec Vol 2 + and_spr_immed -33,isr ; turn off isr.edem + set_gr_immed -1,gr3 + set_gr_limmed 0x8000,0x0000,gr1 + csdiv gr1,gr3,gr2,cc5,1 + test_gr_limmed 0x7fff,0xffff,gr2 + + or_spr_immed 0x20,isr ; turn on isr.edem + set_gr_immed -1,gr3 + set_gr_limmed 0x8000,0x0000,gr1 + csdiv gr1,gr3,gr2,cc5,1 + test_gr_limmed 0x7fff,0xffff,gr2 + + ; simple division 12 / 3 + set_gr_immed 3,gr3 + set_gr_immed 12,gr1 + csdiv gr1,gr3,gr2,cc6,0 + test_gr_limmed 0x7fff,0xffff,gr2 + + ; Random example + set_gr_limmed 0x0123,0x4567,gr3 + set_gr_limmed 0xfedc,0xba98,gr1 + csdiv gr1,gr3,gr2,cc6,0 + test_gr_limmed 0x7fff,0xffff,gr2 + + ; Special case from the Arch Spec Vol 2 + and_spr_immed -33,isr ; turn off isr.edem + set_gr_immed -1,gr3 + set_gr_limmed 0x8000,0x0000,gr1 + csdiv gr1,gr3,gr2,cc6,0 + test_gr_limmed 0x7fff,0xffff,gr2 + + or_spr_immed 0x20,isr ; turn on isr.edem + set_gr_immed -1,gr3 + set_gr_limmed 0x8000,0x0000,gr1 + csdiv gr1,gr3,gr2,cc6,0 + test_gr_limmed 0x7fff,0xffff,gr2 + + ; simple division 12 / 3 + set_gr_immed 3,gr3 + set_gr_immed 12,gr1 + csdiv gr1,gr3,gr2,cc7,1 + test_gr_limmed 0x7fff,0xffff,gr2 + + ; Random example + set_gr_limmed 0x0123,0x4567,gr3 + set_gr_limmed 0xfedc,0xba98,gr1 + csdiv gr1,gr3,gr2,cc7,1 + test_gr_limmed 0x7fff,0xffff,gr2 + + ; Special case from the Arch Spec Vol 2 + and_spr_immed -33,isr ; turn off isr.edem + set_gr_immed -1,gr3 + set_gr_limmed 0x8000,0x0000,gr1 + csdiv gr1,gr3,gr2,cc7,1 + test_gr_limmed 0x7fff,0xffff,gr2 + + or_spr_immed 0x20,isr ; turn on isr.edem + set_gr_immed -1,gr3 + set_gr_limmed 0x8000,0x0000,gr1 + csdiv gr1,gr3,gr2,cc7,1 + test_gr_limmed 0x7fff,0xffff,gr2 + + pass + +ok1: ; exception handler for overflow + test_spr_bits 0x18,3,0x2,isr ; isr.dtt is set + test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid + test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set + inc_gr_immed 1,gr15 + rett 0 + fail diff --git a/sim/testsuite/sim/frv/fr400/maddaccs.cgs b/sim/testsuite/sim/frv/fr400/maddaccs.cgs new file mode 100644 index 0000000..98659c4 --- /dev/null +++ b/sim/testsuite/sim/frv/fr400/maddaccs.cgs @@ -0,0 +1,131 @@ +# frv testcase for maddaccs $ACC40Si,$ACC40Sk +# mach: fr400 + + .include "../testutils.inc" + + start + + .global maddaccs +maddaccs: + set_accg_immed 0,accg0 + set_acc_immed 0x00000000,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x00000000,acc1 + maddaccs acc0,acc3 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x0000,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0xdead0000,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x0000beef,acc1 + maddaccs acc0,acc3 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg3 + test_acc_limmed 0xdead,0xbeef,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x0000dead,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0xbeef0000,acc1 + maddaccs acc0,acc3 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg3 + test_acc_limmed 0xbeef,0xdead,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x12345678,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x11111111,acc1 + maddaccs acc0,acc3 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg3 + test_acc_limmed 0x2345,0x6789,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x12345678,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0xffffffff,acc1 + maddaccs acc0,acc3 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 1,accg3 + test_acc_limmed 0x1234,0x5677,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x12345678,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xffffffff,acc1 + maddaccs acc0,acc3 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg3 + test_acc_limmed 0x1234,0x5677,acc3 + + set_spr_immed 0,msr0 + set_accg_immed 0x7f,accg0 + set_acc_immed 0xfffe7ffe,acc0 + set_accg_immed 0x0,accg1 + set_acc_immed 0x00020001,acc1 + maddaccs acc0,acc3 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + test_accg_immed 0x7f,accg3 + test_acc_limmed 0xffff,0xffff,acc3 + + set_spr_immed 0,msr0 + set_accg_immed 0x80,accg0 + set_acc_immed 0x00000001,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xfffffffe,acc1 + maddaccs acc0,acc3 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + test_accg_immed 0x80,accg3 + test_acc_limmed 0x0000,0x0000,acc3 + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_accg_immed 0,accg0 + set_acc_immed 0x00000001,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x00000001,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0x00000001,acc2 + set_accg_immed 0x7f,accg3 + set_acc_immed 0xffffffff,acc3 + maddaccs.p acc0,acc1 + maddaccs acc2,acc3 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie not set + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 0x3c,2,0x8,msr1 ; msr1.sie is set + test_spr_bits 2,1,1,msr1 ; msr1.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x0002,acc1 + test_accg_immed 0x7f,accg3 + test_acc_limmed 0xffff,0xffff,acc3 + + pass diff --git a/sim/testsuite/sim/frv/fr400/masaccs.cgs b/sim/testsuite/sim/frv/fr400/masaccs.cgs new file mode 100644 index 0000000..8fbde91 --- /dev/null +++ b/sim/testsuite/sim/frv/fr400/masaccs.cgs @@ -0,0 +1,151 @@ +# frv testcase for masaccs $ACC40Si,$ACC40Sk +# mach: fr400 + + .include "../testutils.inc" + + start + + .global masaccs +masaccs: + set_accg_immed 0,accg0 + set_acc_immed 0x00000000,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x00000000,acc1 + masaccs acc0,acc2 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x0000,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x0000,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0xdead0000,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x0000beef,acc1 + masaccs acc0,acc2 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg2 + test_acc_limmed 0xdead,0xbeef,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0xdeac,0x4111,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x0000dead,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0xbeef0000,acc1 + masaccs acc0,acc2 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg2 + test_acc_limmed 0xbeef,0xdead,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0x4111,0xdead,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x12345678,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x11111111,acc1 + masaccs acc0,acc2 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg2 + test_acc_limmed 0x2345,0x6789,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0123,0x4567,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x12345678,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0xffffffff,acc1 + masaccs acc0,acc2 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 1,accg2 + test_acc_limmed 0x1234,0x5677,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0x1234,0x5679,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x12345678,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xffffffff,acc1 + masaccs acc0,acc2 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg2 + test_acc_limmed 0x1234,0x5677,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x1234,0x5679,acc3 + + set_spr_immed 0,msr0 + set_accg_immed 0x7f,accg0 + set_acc_immed 0xfffe7ffe,acc0 + set_accg_immed 0x0,accg1 + set_acc_immed 0x00020001,acc1 + masaccs acc0,acc2 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + test_accg_immed 0x7f,accg2 + test_acc_limmed 0xffff,0xffff,acc2 + test_accg_immed 0x7f,accg3 + test_acc_limmed 0xfffc,0x7ffd,acc3 + + set_spr_immed 0,msr0 + set_accg_immed 0x80,accg0 + set_acc_immed 0x00000001,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xfffffffe,acc1 + masaccs acc0,acc2 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + test_accg_immed 0x80,accg2 + test_acc_limmed 0x0000,0x0000,acc2 + test_accg_immed 0x80,accg3 + test_acc_limmed 0x0000,0x0003,acc3 + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_accg_immed 0,accg0 + set_acc_immed 0x00000001,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x00000001,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0x00000001,acc2 + set_accg_immed 0x7f,accg3 + set_acc_immed 0xffffffff,acc3 + masaccs.p acc0,acc0 + masaccs acc2,acc2 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie not set + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 0x3c,2,0x8,msr1 ; msr1.sie is set + test_spr_bits 2,1,1,msr1 ; msr1.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x0002,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x0000,acc1 + test_accg_immed 0x7f,accg2 + test_acc_limmed 0xffff,0xffff,acc2 + test_accg_immed 0x80,accg3 + test_acc_limmed 0x0000,0x0002,acc3 + + pass diff --git a/sim/testsuite/sim/frv/fr400/maveh.cgs b/sim/testsuite/sim/frv/fr400/maveh.cgs new file mode 100644 index 0000000..445e121 --- /dev/null +++ b/sim/testsuite/sim/frv/fr400/maveh.cgs @@ -0,0 +1,319 @@ +# frv testcase for maveh $FRi,$FRj,$FRj on fr400 machines +# mach: all + + .include "../testutils.inc" + + start + + .global maveh +maveh: + ; Test Rounding toward positive infinity via RDAV + or_spr_immed 0x20000000,msr0 + and_spr_immed 0xefffffff,msr0 + + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x0000,0x0000,fr12 + + set_fr_iimmed 0x0001,0x0000,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x0002,0x0001,fr12 + + set_fr_iimmed 0x0000,0xffff,fr10 + set_fr_iimmed 0xffff,0xfffe,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x0000,0xffff,fr12 + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0xef57,0xdf78,fr12 + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0xdf78,0xef57,fr12 + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x11a3,0x33c5,fr12 + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x091a,0x2b3c,fr12 + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x4000,0x4000,fr12 + + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xffff,0xfffe,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0xc000,0xc000,fr12 + + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0xc000,0xc000,fr12 + + set_fr_iimmed 0x8000,0x8000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + maveh.p fr10,fr10,fr12 + maveh fr11,fr11,fr13 + test_fr_limmed 0x8000,0x8000,fr12 + test_fr_limmed 0x7fff,0x7fff,fr13 + + ; Test Rounding toward nearest via RD + or_spr_immed 0x10000000,msr0 + and_spr_immed 0x3fffffff,msr0 + + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x0000,0x0000,fr12 + + set_fr_iimmed 0x0001,0x0000,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x0002,0x0001,fr12 + + set_fr_iimmed 0x0000,0xffff,fr10 + set_fr_iimmed 0xffff,0xfffe,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0xffff,0xfffe,fr12 + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0xef56,0xdf77,fr12 + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0xdf77,0xef56,fr12 + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x11a3,0x33c5,fr12 + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x091a,0x2b3c,fr12 + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x4000,0x4000,fr12 + + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xffff,0xfffe,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0xc000,0xbfff,fr12 + + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0xbfff,0xbfff,fr12 + + set_fr_iimmed 0x8000,0x8000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + maveh.p fr10,fr10,fr12 + maveh fr11,fr11,fr13 + test_fr_limmed 0x8000,0x8000,fr12 + test_fr_limmed 0x7fff,0x7fff,fr13 + + ; Test Rounding toward zero via RD + or_spr_immed 0x50000000,msr0 + and_spr_immed 0x7fffffff,msr0 + + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x0000,0x0000,fr12 + + set_fr_iimmed 0x0001,0x0000,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x0001,0x0000,fr12 + + set_fr_iimmed 0x0000,0xffff,fr10 + set_fr_iimmed 0xffff,0xfffe,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x0000,0xffff,fr12 + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0xef57,0xdf78,fr12 + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0xdf78,0xef57,fr12 + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x11a2,0x33c4,fr12 + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x0919,0x2b3b,fr12 + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x4000,0x3fff,fr12 + + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xffff,0xfffe,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0xc000,0xc000,fr12 + + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0xc000,0xc000,fr12 + + set_fr_iimmed 0x8000,0x8000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + maveh.p fr10,fr10,fr12 + maveh fr11,fr11,fr13 + test_fr_limmed 0x8000,0x8000,fr12 + test_fr_limmed 0x7fff,0x7fff,fr13 + + ; Test Rounding toward positive infinity via RD + or_spr_immed 0x90000000,msr0 + and_spr_immed 0xbfffffff,msr0 + + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x0000,0x0000,fr12 + + set_fr_iimmed 0x0001,0x0000,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x0002,0x0001,fr12 + + set_fr_iimmed 0x0000,0xffff,fr10 + set_fr_iimmed 0xffff,0xfffe,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x0000,0xffff,fr12 + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0xef57,0xdf78,fr12 + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0xdf78,0xef57,fr12 + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x11a3,0x33c5,fr12 + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x091a,0x2b3c,fr12 + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x4000,0x4000,fr12 + + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xffff,0xfffe,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0xc000,0xc000,fr12 + + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0xc000,0xc000,fr12 + + set_fr_iimmed 0x8000,0x8000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + maveh.p fr10,fr10,fr12 + maveh fr11,fr11,fr13 + test_fr_limmed 0x8000,0x8000,fr12 + test_fr_limmed 0x7fff,0x7fff,fr13 + + ; Test Rounding toward negative infinity via RD + or_spr_immed 0xd0000000,msr0 + + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x0000,0x0000,fr12 + + set_fr_iimmed 0x0001,0x0000,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x0001,0x0000,fr12 + + set_fr_iimmed 0x0000,0xffff,fr10 + set_fr_iimmed 0xffff,0xfffe,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0xffff,0xfffe,fr12 + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0xef56,0xdf77,fr12 + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0xdf77,0xef56,fr12 + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x11a2,0x33c4,fr12 + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x0919,0x2b3b,fr12 + + set_spr_immed 0,msr0 + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x4000,0x3fff,fr12 + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xffff,0xfffe,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0xc000,0xbfff,fr12 + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0xbfff,0xbfff,fr12 + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x8000,0x8000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + maveh.p fr10,fr10,fr12 + maveh fr11,fr11,fr13 + test_fr_limmed 0x8000,0x8000,fr12 + test_fr_limmed 0x7fff,0x7fff,fr13 + + pass diff --git a/sim/testsuite/sim/frv/fr400/mclracc.cgs b/sim/testsuite/sim/frv/fr400/mclracc.cgs new file mode 100644 index 0000000..0297544 --- /dev/null +++ b/sim/testsuite/sim/frv/fr400/mclracc.cgs @@ -0,0 +1,79 @@ +# frv testcase for mclracc $ACC40k,$A +# mach: all + + .include "../testutils.inc" + + start + + .global mclracc +mclracc: + set_accg_immed 0xff,accg0 + set_acc_immed -1,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed -1,acc1 + set_accg_immed 0xff,accg2 + set_acc_immed -1,acc2 + set_accg_immed 0xff,accg3 + set_acc_immed -1,acc3 + + mclracc acc8,0 ; nop + test_accg_immed 0xff,accg0 + test_acc_immed -1,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed -1,acc1 + test_accg_immed 0xff,accg2 + test_acc_immed -1,acc2 + test_accg_immed 0xff,accg3 + test_acc_immed -1,acc3 + + mclracc acc8,1 ; nop + test_accg_immed 0xff,accg0 + test_acc_immed -1,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed -1,acc1 + test_accg_immed 0xff,accg2 + test_acc_immed -1,acc2 + test_accg_immed 0xff,accg3 + test_acc_immed -1,acc3 + + mclracc acc2,0 + test_accg_immed 0xff,accg0 + test_acc_immed -1,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed -1,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0,acc2 + test_accg_immed 0xff,accg3 + test_acc_immed -1,acc3 + + mclracc acc3,1 + test_accg_immed 0xff,accg0 + test_acc_immed -1,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed -1,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0,acc3 + + mclracc acc0,0 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed -1,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0,acc3 + + mclracc acc0,1 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0,acc3 + + pass diff --git a/sim/testsuite/sim/frv/fr400/mhdseth.cgs b/sim/testsuite/sim/frv/fr400/mhdseth.cgs new file mode 100644 index 0000000..b99c996 --- /dev/null +++ b/sim/testsuite/sim/frv/fr400/mhdseth.cgs @@ -0,0 +1,22 @@ +# frv testcase for mhdseth $s12,$FRk +# mach: all + + .include "../testutils.inc" + + start + + .global mhdseth +mhdseth: + set_fr_immed 0,fr1 + mhdseth 0,fr1 + test_fr_iimmed 0,fr1 + mhdseth 1,fr1 + test_fr_iimmed 0x08000800,fr1 + mhdseth 0xf,fr1 + test_fr_iimmed 0x78007800,fr1 + mhdseth -16,fr1 + test_fr_iimmed 0x80008000,fr1 + mhdseth -1,fr1 + test_fr_iimmed 0xf800f800,fr1 + + pass diff --git a/sim/testsuite/sim/frv/fr400/mhdsets.cgs b/sim/testsuite/sim/frv/fr400/mhdsets.cgs new file mode 100644 index 0000000..c495cb7 --- /dev/null +++ b/sim/testsuite/sim/frv/fr400/mhdsets.cgs @@ -0,0 +1,20 @@ +# frv testcase for mhdsets $s12,$FRk +# mach: all + + .include "../testutils.inc" + + start + + .global mhdsets +mhdsets: + set_fr_immed 0,fr1 + mhdsets 0,fr1 + test_fr_iimmed 0,fr1 + mhdsets 1,fr1 + test_fr_iimmed 0x00010001,fr1 + mhdsets 0x7ff,fr1 + test_fr_iimmed 0x07ff07ff,fr1 + mhdsets -2048,fr1 + test_fr_iimmed 0xf800f800,fr1 + + pass diff --git a/sim/testsuite/sim/frv/fr400/mhsethih.cgs b/sim/testsuite/sim/frv/fr400/mhsethih.cgs new file mode 100644 index 0000000..fed9d23 --- /dev/null +++ b/sim/testsuite/sim/frv/fr400/mhsethih.cgs @@ -0,0 +1,22 @@ +# frv testcase for mhsethih $s12,$FRk +# mach: all + + .include "../testutils.inc" + + start + + .global mhsethih +mhsethih: + set_fr_immed 0,fr1 + mhsethih 0,fr1 + test_fr_iimmed 0,fr1 + mhsethih 1,fr1 + test_fr_iimmed 0x08000000,fr1 + mhsethih 0xf,fr1 + test_fr_iimmed 0x78000000,fr1 + mhsethih -16,fr1 + test_fr_iimmed 0x80000000,fr1 + mhsethih -1,fr1 + test_fr_iimmed 0xf8000000,fr1 + + pass diff --git a/sim/testsuite/sim/frv/fr400/mhsethis.cgs b/sim/testsuite/sim/frv/fr400/mhsethis.cgs new file mode 100644 index 0000000..ade9102 --- /dev/null +++ b/sim/testsuite/sim/frv/fr400/mhsethis.cgs @@ -0,0 +1,25 @@ +# frv testcase for mhsethis $s12,$FRk +# mach: all + + .include "../testutils.inc" + + start + + .global mhsethis +mhsethis: + set_fr_immed 0,fr1 + mhsethis 0,fr1 + test_fr_iimmed 0,fr1 + mhsethis 1,fr1 + test_fr_iimmed 0x00010000,fr1 + mhsethis 0x7ff,fr1 + test_fr_iimmed 0x07ff0000,fr1 + mhsethis -2048,fr1 + test_fr_iimmed 0xf8000000,fr1 + + ; Try parallel set of hi and lo at the same time + mhsethis.p 1,fr1 + mhsetlos 2,fr1 + test_fr_iimmed 0x00010002,fr1 + + pass diff --git a/sim/testsuite/sim/frv/fr400/mhsetloh.cgs b/sim/testsuite/sim/frv/fr400/mhsetloh.cgs new file mode 100644 index 0000000..1dedb83 --- /dev/null +++ b/sim/testsuite/sim/frv/fr400/mhsetloh.cgs @@ -0,0 +1,27 @@ +# frv testcase for mhsetloh $s12,$FRk +# mach: all + + .include "../testutils.inc" + + start + + .global mhsetloh +mhsetloh: + set_fr_immed 0,fr1 + mhsetloh 0,fr1 + test_fr_iimmed 0,fr1 + mhsetloh 1,fr1 + test_fr_iimmed 0x0000800,fr1 + mhsetloh 0xf,fr1 + test_fr_iimmed 0x00007800,fr1 + mhsetloh -16,fr1 + test_fr_iimmed 0x00008000,fr1 + mhsetloh -1,fr1 + test_fr_iimmed 0x0000f800,fr1 + + ; Try parallel write to both hi and lo + mhsetloh.p 1,fr1 + mhsethih 0xf,fr1 + test_fr_iimmed 0x78000800,fr1 + + pass diff --git a/sim/testsuite/sim/frv/fr400/mhsetlos.cgs b/sim/testsuite/sim/frv/fr400/mhsetlos.cgs new file mode 100644 index 0000000..8e8839a --- /dev/null +++ b/sim/testsuite/sim/frv/fr400/mhsetlos.cgs @@ -0,0 +1,25 @@ +# frv testcase for mhsetlos $s12,$FRk +# mach: all + + .include "../testutils.inc" + + start + + .global mhsetlos +mhsetlos: + set_fr_immed 0,fr1 + mhsetlos 0,fr1 + test_fr_iimmed 0,fr1 + mhsetlos 1,fr1 + test_fr_iimmed 0x00000001,fr1 + mhsetlos 0x7ff,fr1 + test_fr_iimmed 0x000007ff,fr1 + mhsetlos -2048,fr1 + test_fr_iimmed 0x0000f800,fr1 + + ; Try parallel set of hi and lo at the same time + mhsethis.p 1,fr1 + mhsetlos 2,fr1 + test_fr_iimmed 0x00010002,fr1 + + pass diff --git a/sim/testsuite/sim/frv/fr400/movgs.cgs b/sim/testsuite/sim/frv/fr400/movgs.cgs new file mode 100644 index 0000000..4e22aab --- /dev/null +++ b/sim/testsuite/sim/frv/fr400/movgs.cgs @@ -0,0 +1,50 @@ +# frv testcase for movgs $GRj,iacc0[hl] +# mach: fr400 + + .include "../testutils.inc" + + start + + .global movgs +IACC0H: + set_gr_limmed 0xdead,0xbeef,gr8 + and_spr_immed 0,iacc0h + movgs gr8,iacc0h + test_gr_limmed 0xdead,0xbeef,gr8 + test_spr_limmed 0xdead,0xbeef,iacc0h +SPR280: + ; try alternate names for iacc0h + and_spr_immed 0,280 + movgs gr8,spr[280] ; iacc0h is spr number 280 + test_gr_limmed 0xdead,0xbeef,gr8 + test_spr_limmed 0xdead,0xbeef,spr[280] + +IACC0L: + set_gr_limmed 0xdead,0xbeef,gr8 + and_spr_immed 0,iacc0l + movgs gr8,iacc0l + test_gr_limmed 0xdead,0xbeef,gr8 + test_spr_limmed 0xdead,0xbeef,iacc0l +SPR281: + ; try alternate names for iacc0l + and_spr_immed 0,281 + movgs gr8,spr[281] ; iacc0l is spr number 281 + test_gr_limmed 0xdead,0xbeef,gr8 + test_spr_limmed 0xdead,0xbeef,spr[281] + +IACC0L_SPR281: + ; try crossing between iacc0l and spr[281] + and_spr_immed 0,281 + and_spr_immed 0,iacc0l + movgs gr8,spr[281] ; iacc0l is spr number 281 + test_gr_limmed 0xdead,0xbeef,gr8 + test_spr_limmed 0xdead,0xbeef,iacc0l + +SPR280_IACC0H: + and_spr_immed 0,280 + and_spr_immed 0,iacc0h + movgs gr8,iacc0h ; iacc0h is spr number 280 + test_gr_limmed 0xdead,0xbeef,gr8 + test_spr_limmed 0xdead,0xbeef,spr[280] + + pass diff --git a/sim/testsuite/sim/frv/fr400/movsg.cgs b/sim/testsuite/sim/frv/fr400/movsg.cgs new file mode 100644 index 0000000..3f9df25 --- /dev/null +++ b/sim/testsuite/sim/frv/fr400/movsg.cgs @@ -0,0 +1,65 @@ +# frv testcase for movsg iacc0[hl],$GRj +# mach: fr400 + + .include "../testutils.inc" + + start + + .global movsg +Iacc0h: + set_spr_limmed 0xdead,0xbeef,iacc0h + set_gr_limmed 0,0,gr8 + movsg iacc0h,gr8 + test_gr_limmed 0xdead,0xbeef,gr8 + test_spr_limmed 0xdead,0xbeef,iacc0h +Iacc0l: + set_spr_limmed 0xdead,0xbeef,iacc0l + set_gr_limmed 0,0,gr8 + movsg iacc0l,gr8 + test_gr_limmed 0xdead,0xbeef,gr8 + test_spr_limmed 0xdead,0xbeef,iacc0l + +Spr280: + set_spr_limmed 0xdead,0xbeef,spr[280] + set_gr_limmed 0,0,gr8 + movsg spr[280],gr8 + test_gr_limmed 0xdead,0xbeef,gr8 + test_spr_limmed 0xdead,0xbeef,spr[280] +Spr281: + set_spr_limmed 0xdead,0xbeef,spr[281] + set_gr_limmed 0,0,gr8 + movsg spr[281],gr8 + test_gr_limmed 0xdead,0xbeef,gr8 + test_spr_limmed 0xdead,0xbeef,spr[281] + +Iacc0h_spr280: + set_spr_limmed 0xdead,0xbeef,spr[280] + set_spr_limmed 0xdead,0xbeef,iacc0h + set_gr_limmed 0,0,gr8 + movsg iacc0h,gr8 + test_gr_limmed 0xdead,0xbeef,gr8 + test_spr_limmed 0xdead,0xbeef,spr[280] +Iacc0l_spr281: + set_spr_limmed 0xdead,0xbeef,spr[281] + set_spr_limmed 0xdead,0xbeef,iacc0l + set_gr_limmed 0,0,gr8 + movsg iacc0l,gr8 + test_gr_limmed 0xdead,0xbeef,gr8 + test_spr_limmed 0xdead,0xbeef,spr[281] + +Spr280_iacc0h: + set_spr_limmed 0xdead,0xbeef,spr[280] + set_spr_limmed 0xdead,0xbeef,iacc0h + set_gr_limmed 0,0,gr8 + movsg spr[280],gr8 + test_gr_limmed 0xdead,0xbeef,gr8 + test_spr_limmed 0xdead,0xbeef,iacc0h +Spr281_iacc0l: + set_spr_limmed 0xdead,0xbeef,spr[281] + set_spr_limmed 0xdead,0xbeef,iacc0l + set_gr_limmed 0,0,gr8 + movsg spr[281],gr8 + test_gr_limmed 0xdead,0xbeef,gr8 + test_spr_limmed 0xdead,0xbeef,iacc0l + + pass diff --git a/sim/testsuite/sim/frv/fr400/msubaccs.cgs b/sim/testsuite/sim/frv/fr400/msubaccs.cgs new file mode 100644 index 0000000..f0aba1d --- /dev/null +++ b/sim/testsuite/sim/frv/fr400/msubaccs.cgs @@ -0,0 +1,131 @@ +# frv testcase for msubaccs $ACC40Si,$ACC40Sk +# mach: fr400 + + .include "../testutils.inc" + + start + + .global msubaccs +msubaccs: + set_accg_immed 0,accg0 + set_acc_immed 0x00000000,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x00000000,acc1 + msubaccs acc0,acc3 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x0000,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0xdead0000,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x0000beef,acc1 + msubaccs acc0,acc3 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg3 + test_acc_limmed 0xdeac,0x4111,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x0000dead,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0xbeef0000,acc1 + msubaccs acc0,acc3 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg3 + test_acc_limmed 0x4111,0xdead,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x12345678,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x11111111,acc1 + msubaccs acc0,acc3 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg3 + test_acc_limmed 0x0123,0x4567,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x12345678,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0xffffffff,acc1 + msubaccs acc0,acc3 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg3 + test_acc_limmed 0x1234,0x5679,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x12345678,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xffffffff,acc1 + msubaccs acc0,acc3 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg3 + test_acc_limmed 0x1234,0x5679,acc3 + + set_spr_immed 0,msr0 + set_accg_immed 0x7f,accg0 + set_acc_immed 0xfffffffe,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xfffffffe,acc1 + msubaccs acc0,acc3 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + test_accg_immed 0x7f,accg3 + test_acc_limmed 0xffff,0xffff,acc3 + + set_spr_immed 0,msr0 + set_accg_immed 0x80,accg0 + set_acc_immed 0x00000001,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x00000002,acc1 + msubaccs acc0,acc3 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + test_accg_immed 0x80,accg3 + test_acc_limmed 0x0000,0x0000,acc3 + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_accg_immed 0,accg0 + set_acc_immed 0x00000001,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x00000001,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0x00000001,acc2 + set_accg_immed 0x80,accg3 + set_acc_immed 0x00000000,acc3 + msubaccs.p acc0,acc1 + msubaccs acc2,acc3 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 0x3c,2,0x8,msr1 ; msr0.sie is set + test_spr_bits 2,1,1,msr1 ; msr1.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x0000,acc1 + test_accg_immed 0x7f,accg3 + test_acc_limmed 0xffff,0xffff,acc3 + + pass diff --git a/sim/testsuite/sim/frv/fr400/scutss.cgs b/sim/testsuite/sim/frv/fr400/scutss.cgs new file mode 100644 index 0000000..aa115b9 --- /dev/null +++ b/sim/testsuite/sim/frv/fr400/scutss.cgs @@ -0,0 +1,642 @@ +# frv testcase for scutss $FRj,$FRk +# mach: fr400 + + .include "../testutils.inc" + + start + + .global scutss +scutss: + set_spr_immed 0xffffffe7,iacc0h + set_spr_immed 0x89abcdef,iacc0l + + set_gr_immed 0,gr10 + scutss gr10,gr11 + test_gr_limmed 0xffff,0xffe7,gr11 + + set_gr_immed 1,gr10 + scutss gr10,gr11 + test_gr_limmed 0xffff,0xffcf,gr11 + + set_gr_immed 2,gr10 + scutss gr10,gr11 + test_gr_limmed 0xffff,0xff9e,gr11 + + set_gr_immed 3,gr10 + scutss gr10,gr11 + test_gr_limmed 0xffff,0xff3c,gr11 + + set_gr_immed 4,gr10 + scutss gr10,gr11 + test_gr_limmed 0xffff,0xfe78,gr11 + + set_gr_immed 5,gr10 + scutss gr10,gr11 + test_gr_limmed 0xffff,0xfcf1,gr11 + + set_gr_immed 6,gr10 + scutss gr10,gr11 + test_gr_limmed 0xffff,0xf9e2,gr11 + + set_gr_immed 7,gr10 + scutss gr10,gr11 + test_gr_limmed 0xffff,0xf3c4,gr11 + + set_gr_immed 8,gr10 + scutss gr10,gr11 + test_gr_limmed 0xffff,0xe789,gr11 + + set_gr_immed 9,gr10 + scutss gr10,gr11 + test_gr_limmed 0xffff,0xcf13,gr11 + + set_gr_immed 10,gr10 + scutss gr10,gr11 + test_gr_limmed 0xffff,0x9e26,gr11 + + set_gr_immed 11,gr10 + scutss gr10,gr11 + test_gr_limmed 0xffff,0x3c4d,gr11 + + set_gr_immed 12,gr10 + scutss gr10,gr11 + test_gr_limmed 0xfffe,0x789a,gr11 + + set_gr_immed 13,gr10 + scutss gr10,gr11 + test_gr_limmed 0xfffc,0xf135,gr11 + + set_gr_immed 14,gr10 + scutss gr10,gr11 + test_gr_limmed 0xfff9,0xe26a,gr11 + + set_gr_immed 15,gr10 + scutss gr10,gr11 + test_gr_limmed 0xfff3,0xc4d5,gr11 + + set_gr_immed 16,gr10 + scutss gr10,gr11 + test_gr_limmed 0xffe7,0x89ab,gr11 + + set_gr_immed 17,gr10 + scutss gr10,gr11 + test_gr_limmed 0xffcf,0x1357,gr11 + + set_gr_immed 18,gr10 + scutss gr10,gr11 + test_gr_limmed 0xff9e,0x26af,gr11 + + set_gr_immed 19,gr10 + scutss gr10,gr11 + test_gr_limmed 0xff3c,0x4d5e,gr11 + + set_gr_immed 20,gr10 + scutss gr10,gr11 + test_gr_limmed 0xfe78,0x9abc,gr11 + + set_gr_immed 21,gr10 + scutss gr10,gr11 + test_gr_limmed 0xfcf1,0x3579,gr11 + + set_gr_immed 22,gr10 + scutss gr10,gr11 + test_gr_limmed 0xf9e2,0x6af3,gr11 + + set_gr_immed 23,gr10 + scutss gr10,gr11 + test_gr_limmed 0xf3c4,0xd5e6,gr11 + + set_gr_immed 24,gr10 + scutss gr10,gr11 + test_gr_limmed 0xe789,0xabcd,gr11 + + set_gr_immed 25,gr10 + scutss gr10,gr11 + test_gr_limmed 0xcf13,0x579b,gr11 + + set_gr_immed 26,gr10 + scutss gr10,gr11 + test_gr_limmed 0x9e26,0xaf37,gr11 + + set_gr_immed 27,gr10 + scutss gr10,gr11 + test_gr_limmed 0x8000,0x0000,gr11 + + set_gr_immed 28,gr10 + scutss gr10,gr11 + test_gr_limmed 0x8000,0x0000,gr11 + + set_gr_immed 29,gr10 + scutss gr10,gr11 + test_gr_limmed 0x8000,0x0000,gr11 + + set_gr_immed 30,gr10 + scutss gr10,gr11 + test_gr_limmed 0x8000,0x0000,gr11 + + set_gr_immed 31,gr10 + scutss gr10,gr11 + test_gr_limmed 0x8000,0x0000,gr11 + + set_gr_immed 32,gr10 + scutss gr10,gr11 + test_gr_limmed 0x8000,0x0000,gr11 + + set_gr_immed 33,gr10 + scutss gr10,gr11 + test_gr_limmed 0x8000,0x0000,gr11 + + set_gr_immed 34,gr10 + scutss gr10,gr11 + test_gr_limmed 0x8000,0x0000,gr11 + + set_gr_immed 35,gr10 + scutss gr10,gr11 + test_gr_limmed 0x8000,0x0000,gr11 + + set_gr_immed 36,gr10 + scutss gr10,gr11 + test_gr_limmed 0x8000,0x0000,gr11 + + set_gr_immed 37,gr10 + scutss gr10,gr11 + test_gr_limmed 0x8000,0x0000,gr11 + + set_gr_immed 38,gr10 + scutss gr10,gr11 + test_gr_limmed 0x8000,0x0000,gr11 + + set_gr_immed 39,gr10 + scutss gr10,gr11 + test_gr_limmed 0x8000,0x0000,gr11 + + set_gr_immed 40,gr10 + scutss gr10,gr11 + test_gr_limmed 0x8000,0x0000,gr11 + + set_gr_immed 41,gr10 + scutss gr10,gr11 + test_gr_limmed 0x8000,0x0000,gr11 + + set_gr_immed 42,gr10 + scutss gr10,gr11 + test_gr_limmed 0x8000,0x0000,gr11 + + set_gr_immed 43,gr10 + scutss gr10,gr11 + test_gr_limmed 0x8000,0x0000,gr11 + + set_gr_immed 44,gr10 + scutss gr10,gr11 + test_gr_limmed 0x8000,0x0000,gr11 + + set_gr_immed 45,gr10 + scutss gr10,gr11 + test_gr_limmed 0x8000,0x0000,gr11 + + set_gr_immed 46,gr10 + scutss gr10,gr11 + test_gr_limmed 0x8000,0x0000,gr11 + + set_gr_immed 47,gr10 + scutss gr10,gr11 + test_gr_limmed 0x8000,0x0000,gr11 + + set_gr_immed 48,gr10 + scutss gr10,gr11 + test_gr_limmed 0x8000,0x0000,gr11 + + set_gr_immed 49,gr10 + scutss gr10,gr11 + test_gr_limmed 0x8000,0x0000,gr11 + + set_gr_immed 50,gr10 + scutss gr10,gr11 + test_gr_limmed 0x8000,0x0000,gr11 + + set_gr_immed 51,gr10 + scutss gr10,gr11 + test_gr_limmed 0x8000,0x0000,gr11 + + set_gr_immed 52,gr10 + scutss gr10,gr11 + test_gr_limmed 0x8000,0x0000,gr11 + + set_gr_immed 53,gr10 + scutss gr10,gr11 + test_gr_limmed 0x8000,0x0000,gr11 + + set_gr_immed 54,gr10 + scutss gr10,gr11 + test_gr_limmed 0x8000,0x0000,gr11 + + set_gr_immed 55,gr10 + scutss gr10,gr11 + test_gr_limmed 0x8000,0x0000,gr11 + + set_gr_immed 56,gr10 + scutss gr10,gr11 + test_gr_limmed 0x8000,0x0000,gr11 + + set_gr_immed 57,gr10 + scutss gr10,gr11 + test_gr_limmed 0x8000,0x0000,gr11 + + set_gr_immed 58,gr10 + scutss gr10,gr11 + test_gr_limmed 0x8000,0x0000,gr11 + + set_gr_immed 59,gr10 + scutss gr10,gr11 + test_gr_limmed 0x8000,0x0000,gr11 + + set_gr_immed 60,gr10 + scutss gr10,gr11 + test_gr_limmed 0x8000,0x0000,gr11 + + set_gr_immed 61,gr10 + scutss gr10,gr11 + test_gr_limmed 0x8000,0x0000,gr11 + + set_gr_immed 62,gr10 + scutss gr10,gr11 + test_gr_limmed 0x8000,0x0000,gr11 + + set_gr_immed 63,gr10 + scutss gr10,gr11 + test_gr_limmed 0x8000,0x0000,gr11 + + set_gr_immed 64,gr10 ; same as -64 + scutss gr10,gr11 + test_gr_immed -1,gr11 + + set_gr_immed 128,gr10 ; same as 0 + scutss gr10,gr11 + test_gr_limmed 0xffff,0xffe7,gr11 + + .global scutss2 +scutss2: + set_spr_immed 0xe789abcd,iacc0h + set_spr_immed 0xefa5a5a5,iacc0l + + set_gr_limmed 0xffff,0xffff,gr10 ; -1 + scutss gr10,gr11 + test_gr_limmed 0xf3c4,0xd5e6,gr11 + + set_gr_limmed 0x0000,0x007e,gr10 ; -2 (only lower 7 bits matter) + scutss gr10,gr11 + test_gr_limmed 0xf9e2,0x6af3,gr11 + + set_gr_immed -3,gr10 + scutss gr10,gr11 + test_gr_limmed 0xfcf1,0x3579,gr11 + + set_gr_immed -4,gr10 + scutss gr10,gr11 + test_gr_limmed 0xfe78,0x9abc,gr11 + + set_gr_immed -5,gr10 + scutss gr10,gr11 + test_gr_limmed 0xff3c,0x4d5e,gr11 + + set_gr_immed -6,gr10 + scutss gr10,gr11 + test_gr_limmed 0xff9e,0x26af,gr11 + + set_gr_immed -7,gr10 + scutss gr10,gr11 + test_gr_limmed 0xffcf,0x1357,gr11 + + set_gr_immed -8,gr10 + scutss gr10,gr11 + test_gr_limmed 0xffe7,0x89ab,gr11 + + set_gr_immed -9,gr10 + scutss gr10,gr11 + test_gr_limmed 0xfff3,0xc4d5,gr11 + + set_gr_immed -10,gr10 + scutss gr10,gr11 + test_gr_limmed 0xfff9,0xe26a,gr11 + + set_gr_immed -11,gr10 + scutss gr10,gr11 + test_gr_limmed 0xfffc,0xf135,gr11 + + set_gr_immed -12,gr10 + scutss gr10,gr11 + test_gr_limmed 0xfffe,0x789a,gr11 + + set_gr_immed -13,gr10 + scutss gr10,gr11 + test_gr_limmed 0xffff,0x3c4d,gr11 + + set_gr_immed -14,gr10 + scutss gr10,gr11 + test_gr_limmed 0xffff,0x9e26,gr11 + + set_gr_immed -15,gr10 + scutss gr10,gr11 + test_gr_limmed 0xffff,0xcf13,gr11 + + set_gr_immed -16,gr10 + scutss gr10,gr11 + test_gr_limmed 0xffff,0xe789,gr11 + + set_gr_immed -17,gr10 + scutss gr10,gr11 + test_gr_limmed 0xffff,0xf3c4,gr11 + + set_gr_immed -18,gr10 + scutss gr10,gr11 + test_gr_limmed 0xffff,0xf9e2,gr11 + + set_gr_immed -19,gr10 + scutss gr10,gr11 + test_gr_limmed 0xffff,0xfcf1,gr11 + + set_gr_immed -20,gr10 + scutss gr10,gr11 + test_gr_limmed 0xffff,0xfe78,gr11 + + set_gr_immed -21,gr10 + scutss gr10,gr11 + test_gr_limmed 0xffff,0xff3c,gr11 + + set_gr_immed -22,gr10 + scutss gr10,gr11 + test_gr_limmed 0xffff,0xff9e,gr11 + + set_gr_immed -23,gr10 + scutss gr10,gr11 + test_gr_limmed 0xffff,0xffcf,gr11 + + set_gr_immed -24,gr10 + scutss gr10,gr11 + test_gr_limmed 0xffff,0xffe7,gr11 + + set_gr_immed -25,gr10 + scutss gr10,gr11 + test_gr_limmed 0xffff,0xfff3,gr11 + + set_gr_immed -26,gr10 + scutss gr10,gr11 + test_gr_limmed 0xffff,0xfff9,gr11 + + set_gr_immed -27,gr10 + scutss gr10,gr11 + test_gr_limmed 0xffff,0xfffc,gr11 + + set_gr_immed -28,gr10 + scutss gr10,gr11 + test_gr_limmed 0xffff,0xfffe,gr11 + + set_gr_immed -29,gr10 + scutss gr10,gr11 + test_gr_limmed 0xffff,0xffff,gr11 + + set_gr_immed -30,gr10 + scutss gr10,gr11 + test_gr_limmed 0xffff,0xffff,gr11 + + set_gr_immed -31,gr10 + scutss gr10,gr11 + test_gr_limmed 0xffff,0xffff,gr11 + + set_gr_immed -32,gr10 + scutss gr10,gr11 + test_gr_limmed 0xffff,0xffff,gr11 + + set_gr_limmed 0,64,gr10 ; same as -32 + scutss gr10,gr11 + test_gr_limmed 0xffff,0xffff,gr11 + + set_spr_immed 0x6789abcd,iacc0h + set_spr_immed 0xefa5a5a5,iacc0l + + set_gr_limmed 0xffff,0xffff,gr10 + scutss gr10,gr11 + test_gr_limmed 0x33c4,0xd5e6,gr11 + + set_gr_limmed 0x0000,0x007e,gr10 ; -2 (only lower 7 bits matter) + scutss gr10,gr11 + test_gr_limmed 0x19e2,0x6af3,gr11 + + set_gr_immed -3,gr10 + scutss gr10,gr11 + test_gr_limmed 0x0cf1,0x3579,gr11 + + set_gr_immed -4,gr10 + scutss gr10,gr11 + test_gr_limmed 0x0678,0x9abc,gr11 + + set_gr_immed -5,gr10 + scutss gr10,gr11 + test_gr_limmed 0x033c,0x4d5e,gr11 + + set_gr_immed -6,gr10 + scutss gr10,gr11 + test_gr_limmed 0x019e,0x26af,gr11 + + set_gr_immed -7,gr10 + scutss gr10,gr11 + test_gr_limmed 0x00cf,0x1357,gr11 + + set_gr_immed -8,gr10 + scutss gr10,gr11 + test_gr_limmed 0x0067,0x89ab,gr11 + + set_gr_immed -9,gr10 + scutss gr10,gr11 + test_gr_limmed 0x0033,0xc4d5,gr11 + + set_gr_immed -10,gr10 + scutss gr10,gr11 + test_gr_limmed 0x0019,0xe26a,gr11 + + set_gr_immed -11,gr10 + scutss gr10,gr11 + test_gr_limmed 0x000c,0xf135,gr11 + + set_gr_immed -12,gr10 + scutss gr10,gr11 + test_gr_limmed 0x0006,0x789a,gr11 + + set_gr_immed -13,gr10 + scutss gr10,gr11 + test_gr_limmed 0x0003,0x3c4d,gr11 + + set_gr_immed -14,gr10 + scutss gr10,gr11 + test_gr_limmed 0x0001,0x9e26,gr11 + + set_gr_immed -15,gr10 + scutss gr10,gr11 + test_gr_limmed 0x0000,0xcf13,gr11 + + set_gr_immed -16,gr10 + scutss gr10,gr11 + test_gr_limmed 0x0000,0x6789,gr11 + + set_gr_immed -17,gr10 + scutss gr10,gr11 + test_gr_limmed 0x0000,0x33c4,gr11 + + set_gr_immed -18,gr10 + scutss gr10,gr11 + test_gr_limmed 0x0000,0x19e2,gr11 + + set_gr_immed -19,gr10 + scutss gr10,gr11 + test_gr_limmed 0x0000,0x0cf1,gr11 + + set_gr_immed -20,gr10 + scutss gr10,gr11 + test_gr_limmed 0x0000,0x0678,gr11 + + set_gr_immed -21,gr10 + scutss gr10,gr11 + test_gr_limmed 0x0000,0x033c,gr11 + + set_gr_immed -22,gr10 + scutss gr10,gr11 + test_gr_limmed 0x0000,0x019e,gr11 + + set_gr_immed -23,gr10 + scutss gr10,gr11 + test_gr_limmed 0x0000,0x00cf,gr11 + + set_gr_immed -24,gr10 + scutss gr10,gr11 + test_gr_limmed 0x0000,0x0067,gr11 + + set_gr_immed -25,gr10 + scutss gr10,gr11 + test_gr_limmed 0x0000,0x0033,gr11 + + set_gr_immed -26,gr10 + scutss gr10,gr11 + test_gr_limmed 0x0000,0x0019,gr11 + + set_gr_immed -27,gr10 + scutss gr10,gr11 + test_gr_limmed 0x0000,0x000c,gr11 + + set_gr_immed -28,gr10 + scutss gr10,gr11 + test_gr_limmed 0x0000,0x0006,gr11 + + set_gr_immed -29,gr10 + scutss gr10,gr11 + test_gr_limmed 0x0000,0x0003,gr11 + + set_gr_immed -30,gr10 + scutss gr10,gr11 + test_gr_limmed 0x0000,0x0001,gr11 + + set_gr_immed -31,gr10 + scutss gr10,gr11 + test_gr_limmed 0x0000,0x0000,gr11 + + set_gr_immed -32,gr10 + scutss gr10,gr11 + test_gr_limmed 0x0000,0x0000,gr11 + + set_gr_immed 64,gr10 ; same as -32 + scutss gr10,gr11 + test_gr_limmed 0x0000,0x0000,gr11 + + ; Examples from the customer (modified for iacc0) + set_spr_immed 0xffffffff,iacc0h + set_spr_immed 0xffe00000,iacc0l + + set_gr_limmed 0,16,gr10 + scutss gr10,gr11 + test_gr_limmed 0xffff,0xffe0,gr11 + + set_gr_limmed 0,17,gr10 + scutss gr10,gr11 + test_gr_limmed 0xffff,0xffc0,gr11 + + set_gr_limmed 0,18,gr10 + scutss gr10,gr11 + test_gr_limmed 0xffff,0xff80,gr11 + + set_spr_immed 0,iacc0h + set_spr_immed 0x003fffff,iacc0l + + set_gr_limmed 0,40,gr10 + scutss gr10,gr11 + test_gr_limmed 0x3fff,0xff00,gr11 + + set_gr_limmed 0,41,gr10 + scutss gr10,gr11 + test_gr_limmed 0x7fff,0xfe00,gr11 + + set_spr_immed 0x7f,iacc0h + set_spr_immed 0xffe00000,iacc0l + + set_gr_limmed 0,40,gr10 + scutss gr10,gr11 + test_gr_limmed 0x7fff,0xffff,gr11 ; saturated + + set_gr_limmed 0,41,gr10 + scutss gr10,gr11 + test_gr_limmed 0x7fff,0xffff,gr11 ; saturated + + set_gr_limmed 0,42,gr10 + scutss gr10,gr11 + test_gr_limmed 0x7fff,0xffff,gr11 ; saturated + + set_spr_immed 0x08,iacc0h + set_spr_immed 0x003fffff,iacc0l + + set_gr_limmed 0,40,gr10 + scutss gr10,gr11 + test_gr_limmed 0x7fff,0xffff,gr11 ; saturated + + set_gr_limmed 0,41,gr10 + scutss gr10,gr11 + test_gr_limmed 0x7fff,0xffff,gr11 ; saturated + + set_spr_immed 0xffffffff,iacc0h + set_spr_immed 0xefe00000,iacc0l + + set_gr_limmed 0,40,gr10 + scutss gr10,gr11 + test_gr_limmed 0x8000,0x0000,gr11 ; saturated + + set_gr_limmed 0,41,gr10 + scutss gr10,gr11 + test_gr_limmed 0x8000,0x0000,gr11 ; saturated + + set_gr_limmed 0,42,gr10 + scutss gr10,gr11 + test_gr_limmed 0x8000,0x0000,gr11 ; saturated + + set_spr_immed 0x80000000,iacc0h + set_spr_immed 0x003fffff,iacc0l + + set_gr_limmed 0,16,gr10 + scutss gr10,gr11 + test_gr_limmed 0x8000,0x0000,gr11 ; saturated + + set_gr_limmed 0,17,gr10 + scutss gr10,gr11 + test_gr_limmed 0x8000,0x0000,gr11 ; saturated + + set_spr_immed 0xaf5a5a5a,iacc0h + set_spr_immed 0x5a5a5a5a,iacc0l + + set_gr_limmed 0xffff,0xfffc,gr10 + scutss gr10,gr11 + test_gr_limmed 0xfaf5,0xa5a5,gr11 + + set_spr_immed 0x2f5a5a5a,iacc0h + set_spr_immed 0x5a5a5a5a,iacc0l + + set_gr_limmed 0xffff,0xfff9,gr10 + scutss gr10,gr11 + test_gr_limmed 0x005e,0xb4b4,gr11 + + pass diff --git a/sim/testsuite/sim/frv/fr400/sdiv.cgs b/sim/testsuite/sim/frv/fr400/sdiv.cgs new file mode 100644 index 0000000..b9c03cf --- /dev/null +++ b/sim/testsuite/sim/frv/fr400/sdiv.cgs @@ -0,0 +1,71 @@ +# frv testcase for sdiv $GRi,$GRj,$GRk +# mach: all + + .include "../testutils.inc" + + start + + .global sdiv +sdiv: + ; simple division 12 / 3 + set_gr_immed 3,gr3 + set_gr_immed 12,gr1 + sdiv gr1,gr3,gr2 + test_gr_immed 4,gr2 + + ; Random example + set_gr_limmed 0x0123,0x4567,gr3 + set_gr_limmed 0xfedc,0xba98,gr1 + sdiv gr1,gr3,gr2 + test_gr_immed -1,gr2 + + ; Special case from the Arch Spec Vol 2 + or_spr_immed 0x20,isr ; turn on isr.edem + set_gr_immed -1,gr3 + set_gr_limmed 0x8000,0x0000,gr1 + sdiv gr1,gr3,gr2 + test_gr_limmed 0x7fff,0xffff,gr2 + test_spr_bits 0x4,2,1,isr ; isr.aexc is set + + and_spr_immed -33,isr ; turn off isr.edem + ; set up exception handler + set_psr_et 1 + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr17 + inc_gr_immed 0x170,gr17 ; address of exception handler + set_bctrlr_0_0 gr17 + set_spr_immed 128,lcr + set_gr_immed 0,gr15 + + ; divide will cause overflow + set_spr_addr ok1,lr + set_gr_immed -1,gr3 + set_gr_limmed 0x8000,0x0000,gr1 +e1: sdiv gr1,gr3,gr2 ; overflow + test_gr_immed 1,gr15 + test_gr_limmed 0x8000,0x0000,gr2; gr2 updated + + ; divide by zero + set_spr_addr ok2,lr + set_gr_immed 0xdeadbeef,gr2 +e2: sdiv gr1,gr0,gr2 ; divide by zero + test_gr_immed 2,gr15 ; handler called + test_gr_immed 0xdeadbeef,gr2 ; gr2 not updated. + + pass + +ok1: ; exception handler for overflow + test_spr_bits 0x18,3,0x2,isr ; isr.dtt is set + test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid + test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set + inc_gr_immed 1,gr15 + rett 0 + fail + +ok2: ; exception handler for divide by zero + test_spr_bits 0x18,3,0x3,isr ; isr.dtt is set + test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid + test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set + inc_gr_immed 1,gr15 + rett 0 + fail diff --git a/sim/testsuite/sim/frv/fr400/sdivi.cgs b/sim/testsuite/sim/frv/fr400/sdivi.cgs new file mode 100644 index 0000000..fda573e --- /dev/null +++ b/sim/testsuite/sim/frv/fr400/sdivi.cgs @@ -0,0 +1,70 @@ +# frv testcase for sdivi $GRi,$s12,$GRk +# mach: all + + .include "../testutils.inc" + + start + + .global sdivi +sdivi: + ; simple division 12 / 3 + set_gr_immed 12,gr1 + sdivi gr1,3,gr2 + test_gr_immed 4,gr2 + + ; Random example + set_gr_limmed 0xfedc,0xba98,gr1 + sdivi gr1,0x7ff,gr2 + test_gr_limmed 0xffff,0xdb93,gr2 + + ; Random negative example + set_gr_limmed 0xfedc,0xba98,gr1 + sdivi gr1,-2048,gr2 + test_gr_immed 0x2468,gr2 + + ; Special case from the Arch Spec Vol 2 + or_spr_immed 0x20,isr ; turn on isr.edem + set_gr_limmed 0x8000,0x0000,gr1 + sdivi gr1,-1,gr2 + test_gr_limmed 0x7fff,0xffff,gr2 + test_spr_bits 0x4,2,1,isr ; isr.aexc is set + + and_spr_immed -33,isr ; turn off isr.edem + ; set up exception handler + set_psr_et 1 + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr17 + inc_gr_immed 0x170,gr17 ; address of exception handler + set_bctrlr_0_0 gr17 + set_spr_immed 128,lcr + set_gr_immed 0,gr15 + + ; divide will cause overflow + set_spr_addr ok1,lr + set_gr_limmed 0x8000,0x0000,gr1 +e1: sdivi gr1,-1,gr2 + test_gr_immed 1,gr15 + test_gr_limmed 0x8000,0x0000,gr2 + + ; divide by zero + set_spr_addr ok2,lr +e2: sdivi gr1,0,gr2 ; divide by zero + test_gr_immed 2,gr15 + + pass + +ok1: ; exception handler for overflow + test_spr_bits 0x18,3,0x2,isr ; isr.dtt is set + test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid + test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set + inc_gr_immed 1,gr15 + rett 0 + fail + +ok2: ; exception handler for divide by zero + test_spr_bits 0x18,3,0x3,isr ; isr.dtt is set + test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid + test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set + inc_gr_immed 1,gr15 + rett 0 + fail diff --git a/sim/testsuite/sim/frv/fr400/slass.cgs b/sim/testsuite/sim/frv/fr400/slass.cgs new file mode 100644 index 0000000..0100052 --- /dev/null +++ b/sim/testsuite/sim/frv/fr400/slass.cgs @@ -0,0 +1,104 @@ +# frv testcase for slass $GRi,$GRj,$GRk +# mach: fr400 + + .include "../testutils.inc" + + start + + .global sll +slass0: + set_gr_immed 0,gr7 ; Shift by 0 + set_gr_immed 2,gr8 + slass gr8,gr7,gr6 + test_gr_immed 2,gr8 + test_gr_immed 0,gr7 + test_gr_immed 2,gr6 +slass1: + set_gr_immed 1,gr7 ; Shift by 1 + set_gr_immed 2,gr8 + slass gr8,gr7,gr6 + test_gr_immed 2,gr8 + test_gr_immed 1,gr7 + test_gr_immed 4,gr6 + +slass2: + set_gr_immed 31,gr7 ; Shift 1 by 31 + set_gr_immed 1,gr8 + slass gr8,gr7,gr6 + test_gr_immed 1,gr8 + test_gr_immed 31,gr7 + test_gr_limmed 0x7fff,0xffff,gr6 + +slass3: + set_gr_immed 31,gr7 ; Shift -1 by 31 + set_gr_immed -1,gr8 + slass gr8,gr7,gr6 + test_gr_immed -1,gr8 + test_gr_immed 31,gr7 + test_gr_limmed 0x8000,0x0000,gr6 + +slass4: + set_gr_immed 14,gr7 ; Shift 0xffff0000 by 14 + set_gr_limmed 0xffff,0x0000,gr8 + slass gr8,gr7,gr6 + test_gr_limmed 0xffff,0x0000,gr8 + test_gr_immed 14,gr7 + test_gr_limmed 0xc000,0x0000,gr6 + +slass5: + set_gr_immed 15,gr7 ; Shift 0xffff0000 by 15 + set_gr_limmed 0xffff,0x0000,gr8 + slass gr8,gr7,gr6 + test_gr_limmed 0xffff,0x0000,gr8 + test_gr_immed 15,gr7 + test_gr_limmed 0x8000,0x0000,gr6 + +slass6: + set_gr_immed 20,gr7 ; Shift 0xffff0000 by 20 + set_gr_limmed 0xffff,0x0000,gr8 + slass gr8,gr7,gr6 + test_gr_limmed 0xffff,0x0000,gr8 + test_gr_immed 20,gr7 + test_gr_limmed 0x8000,0x0000,gr6 + +slass7: + set_gr_immed 14,gr7 ; Shift 0x0000ffff by 14 + set_gr_limmed 0x0000,0xffff,gr8 + slass gr8,gr7,gr6 + test_gr_limmed 0x0000,0xffff,gr8 + test_gr_immed 14,gr7 + test_gr_limmed 0x3fff,0xc000,gr6 + +slass8: + set_gr_immed 15,gr7 ; Shift 0x0000ffff by 15 + set_gr_limmed 0x0000,0xffff,gr8 + slass gr8,gr7,gr6 + test_gr_limmed 0x0000,0xffff,gr8 + test_gr_immed 15,gr7 + test_gr_limmed 0x7fff,0x8000,gr6 + +slass9: + set_gr_immed 20,gr7 ; Shift 0x0000ffff by 20 + set_gr_limmed 0x0000,0xffff,gr8 + slass gr8,gr7,gr6 + test_gr_limmed 0x0000,0xffff,gr8 + test_gr_immed 20,gr7 + test_gr_limmed 0x7fff,0xffff,gr6 + +slass10: + set_gr_immed 30,gr7 ; Shift 1 by 30 + set_gr_immed 1,gr8 + slass gr8,gr7,gr6 + test_gr_immed 1,gr8 + test_gr_immed 30,gr7 + test_gr_limmed 0x4000,0x0000,gr6 + +slass11: + set_gr_immed 30,gr7 ; Shift -1 by 30 + set_gr_immed -1,gr8 + slass gr8,gr7,gr6 + test_gr_immed -1,gr8 + test_gr_immed 30,gr7 + test_gr_limmed 0xc000,0000,gr6 + + pass diff --git a/sim/testsuite/sim/frv/fr400/smass.cgs b/sim/testsuite/sim/frv/fr400/smass.cgs new file mode 100644 index 0000000..3df0fa5 --- /dev/null +++ b/sim/testsuite/sim/frv/fr400/smass.cgs @@ -0,0 +1,359 @@ +# frv testcase for smass $GRi,$GRj +# mach: fr400 + + .include "../testutils.inc" + + start + + .global smass +smass1: + ; Positive operands + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + set_spr_immed 0,iacc0h + set_spr_immed 1,iacc0l + smass gr7,gr8 + test_gr_immed 3,gr7 + test_gr_immed 2,gr8 + test_spr_immed 7,iacc0l ; result 3*2+1 + test_spr_immed 0,iacc0h +smass2: + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed 2,gr8 + set_spr_immed 0,iacc0h + set_spr_immed 1,iacc0l + smass gr7,gr8 + test_gr_immed 1,gr7 + test_gr_immed 2,gr8 + test_spr_immed 3,iacc0l ; result 1*2+1 + test_spr_immed 0,iacc0h +smass3: + set_gr_immed 2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + set_spr_immed 0,iacc0h + set_spr_immed 1,iacc0l + smass gr7,gr8 + test_gr_immed 1,gr8 + test_gr_immed 2,gr7 + test_spr_immed 3,iacc0l ; result 2*1+1 + test_spr_immed 0,iacc0h +smass4: + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed 2,gr8 + set_spr_immed 0,iacc0h + set_spr_immed 1,iacc0l + smass gr7,gr8 + test_gr_immed 2,gr8 + test_gr_immed 0,gr7 + test_spr_immed 1,iacc0l ; result 0*2+1 + test_spr_immed 0,iacc0h +smass5: + set_gr_immed 2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + set_spr_immed 0,iacc0h + set_spr_immed 1,iacc0l + smass gr7,gr8 + test_gr_immed 0,gr8 + test_gr_immed 2,gr7 + test_spr_immed 1,iacc0l ; result 2*0+1 + test_spr_immed 0,iacc0h +smass6: + set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result + set_gr_immed 2,gr8 + set_spr_immed 0,iacc0h + set_spr_immed 1,iacc0l + smass gr7,gr8 + test_gr_immed 2,gr8 + test_gr_limmed 0x3fff,0xffff,gr7 + test_spr_limmed 0x7fff,0xffff,iacc0l ; 3fffffff*2+1 + test_spr_immed 0,iacc0h +smass7: + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed 2,gr8 + set_spr_immed 0,iacc0h + set_spr_immed 1,iacc0l + smass gr7,gr8 + test_gr_immed 2,gr8 + test_gr_limmed 0x4000,0x0000,gr7 + test_spr_limmed 0x8000,0x0001,iacc0l ; 40000000*2+1 + test_spr_immed 0,iacc0h +smass8: + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed 4,gr8 + set_spr_immed 0,iacc0h + set_spr_immed 1,iacc0l + smass gr7,gr8 + test_gr_immed 4,gr8 + test_gr_limmed 0x4000,0x0000,gr7 + test_spr_immed 1,iacc0l ; 40000000*4+1 + test_spr_immed 1,iacc0h +smass9: + set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result + set_gr_limmed 0x7fff,0xffff,gr8 + set_spr_immed 0,iacc0h + set_spr_immed 1,iacc0l + smass gr7,gr8 + test_gr_limmed 0x7fff,0xffff,gr8 + test_gr_limmed 0x7fff,0xffff,gr7 + test_spr_immed 0x00000002,iacc0l ; 7fffffff*7fffffff+1 + test_spr_limmed 0x3fff,0xffff,iacc0h +smass10: + ; Mixed operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + set_spr_immed 0,iacc0h + set_spr_immed 1,iacc0l + smass gr7,gr8 + test_gr_immed 2,gr8 + test_gr_immed -3,gr7 + test_spr_immed -5,iacc0l ; -3*2+1 + test_spr_immed -1,iacc0h +smass11: + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + set_spr_immed 0,iacc0h + set_spr_immed 1,iacc0l + smass gr7,gr8 + test_gr_immed -2,gr8 + test_gr_immed 3,gr7 + test_spr_immed -5,iacc0l ; 3*-2+1 + test_spr_immed -1,iacc0h +smass12: + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + set_spr_immed 0,iacc0h + set_spr_immed 1,iacc0l + smass gr7,gr8 + test_gr_immed -2,gr8 + test_gr_immed 1,gr7 + test_spr_immed -1,iacc0l ; 1*-2+1 + test_spr_immed -1,iacc0h +smass13: + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + set_spr_immed 0,iacc0h + set_spr_immed 1,iacc0l + smass gr7,gr8 + test_gr_immed 1,gr8 + test_gr_immed -2,gr7 + test_spr_immed -1,iacc0l ; -2*1+1 + test_spr_immed -1,iacc0h +smass14: + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed -2,gr8 + set_spr_immed 0,iacc0h + set_spr_immed 1,iacc0l + smass gr7,gr8 + test_gr_immed -2,gr8 + test_gr_immed 0,gr7 + test_spr_immed 1,iacc0l ; 0*-2+1 + test_spr_immed 0,iacc0h +smass15: + set_gr_immed -2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + set_spr_immed 0,iacc0h + set_spr_immed 1,iacc0l + smass gr7,gr8 + test_gr_immed 0,gr8 + test_gr_immed -2,gr7 + test_spr_immed 1,iacc0l ; -2*0+1 + test_spr_immed 0,iacc0h +smass16: + set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result + set_gr_immed -2,gr8 + set_spr_immed 0,iacc0h + set_spr_immed 1,iacc0l + smass gr7,gr8 + test_gr_immed -2,gr8 + test_gr_limmed 0x2000,0x0001,gr7 + test_spr_limmed 0xbfff,0xffff,iacc0l ; 20000001*-2+1 + test_spr_limmed 0xffff,0xffff,iacc0h +smass17: + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + set_spr_immed 0,iacc0h + set_spr_immed 1,iacc0l + smass gr7,gr8 + test_gr_immed -2,gr8 + test_gr_limmed 0x4000,0x0000,gr7 + test_spr_limmed 0x8000,0x0001,iacc0l ; 40000000*-2+1 + test_spr_limmed 0xffff,0xffff,iacc0h +smass18: + set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result + set_gr_immed -2,gr8 + set_spr_immed 0,iacc0h + set_spr_immed 1,iacc0l + smass gr7,gr8 + test_gr_immed -2,gr8 + test_gr_limmed 0x4000,0x0001,gr7 + test_spr_limmed 0x7fff,0xffff,iacc0l ; 40000001*-2+1 + test_spr_limmed 0xffff,0xffff,iacc0h +smass19: + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed -4,gr8 + set_spr_immed 0,iacc0h + set_spr_immed 1,iacc0l + smass gr7,gr8 + test_gr_immed -4,gr8 + test_gr_limmed 0x4000,0x0000,gr7 + test_spr_limmed 0x0000,0x0001,iacc0l ; 40000000*-4+1 + test_spr_limmed 0xffff,0xffff,iacc0h +smass20: + set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result + set_gr_limmed 0x8000,0x0000,gr8 + set_spr_immed 0,iacc0h + set_spr_immed 1,iacc0l + smass gr7,gr8 + test_gr_limmed 0x8000,0x0000,gr8 + test_gr_limmed 0x7fff,0xffff,gr7 + test_spr_limmed 0x8000,0x0001,iacc0l ; 7fffffff*80000000+1 + test_spr_limmed 0xc000,0x0000,iacc0h +smass21: + ; Negative operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + set_spr_immed 0,iacc0h + set_spr_immed 1,iacc0l + smass gr7,gr8 + test_gr_immed -2,gr8 + test_gr_immed -3,gr7 + test_spr_immed 7,iacc0l ; -3*-2+1 + test_spr_immed 0,iacc0h +smass22: + set_gr_immed -1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + set_spr_immed 0,iacc0h + set_spr_immed 1,iacc0l + smass gr7,gr8 + test_gr_immed -2,gr8 + test_gr_immed -1,gr7 + test_spr_immed 3,iacc0l ; -1*-2+1 + test_spr_immed 0,iacc0h +smass23: + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed -1,gr8 + set_spr_immed 0,iacc0h + set_spr_immed 1,iacc0l + smass gr7,gr8 + test_gr_immed -1,gr8 + test_gr_immed -2,gr7 + test_spr_immed 3,iacc0l ; -2*-1+1 + test_spr_immed 0,iacc0h +smass24: + set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result + set_gr_immed -2,gr8 + set_spr_immed 0,iacc0h + set_spr_immed 1,iacc0l + smass gr7,gr8 + test_gr_immed -2,gr8 + test_gr_limmed 0xc000,0x0001,gr7 + test_spr_limmed 0x7fff,0xffff,iacc0l ; c0000001*-2+1 + test_spr_immed 0,iacc0h +smass25: + set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + set_spr_immed 0,iacc0h + set_spr_immed 1,iacc0l + smass gr7,gr8 + test_gr_immed -2,gr8 + test_gr_limmed 0xc000,0x0000,gr7 + test_spr_limmed 0x8000,0x0001,iacc0l ; c0000000*-2+1 + test_spr_immed 0,iacc0h +smass26: + set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result + set_gr_immed -4,gr8 + set_spr_immed 0,iacc0h + set_spr_immed 1,iacc0l + smass gr7,gr8 + test_gr_immed -4,gr8 + test_gr_limmed 0xc000,0x0000,gr7 + test_spr_immed 0x00000001,iacc0l ; c0000000*-4+1 + test_spr_immed 1,iacc0h +smass27: + set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result + set_gr_limmed 0x8000,0x0001,gr8 + set_spr_immed 0,iacc0h + set_spr_immed 1,iacc0l + smass gr7,gr8 + test_gr_limmed 0x8000,0x0001,gr8 + test_gr_limmed 0x8000,0x0001,gr7 + test_spr_immed 0x00000002,iacc0l ; 80000001*80000001+1 + test_spr_limmed 0x3fff,0xffff,iacc0h +smass28: + set_gr_limmed 0x8000,0x0000,gr7 ; max positive result + set_gr_limmed 0x8000,0x0000,gr8 + set_spr_immed 0,iacc0h + set_spr_immed 1,iacc0l + smass gr7,gr8 + test_gr_limmed 0x8000,0x0000,gr8 + test_gr_limmed 0x8000,0x0000,gr7 + test_spr_immed 0x00000001,iacc0l ; 80000000*80000000+1 + test_spr_limmed 0x4000,0x0000,iacc0h + +smass29: + set_gr_limmed 0x7fff,0xffff,gr7 ; not quite overflow (pos) + set_gr_limmed 0x7fff,0xffff,gr8 + set_spr_limmed 0xffff,0xfffe,iacc0l + set_spr_limmed 0x4000,0x0000,iacc0h + smass gr7,gr8 + test_gr_limmed 0x7fff,0xffff,gr8 + test_gr_limmed 0x7fff,0xffff,gr7 + test_spr_limmed 0xffff,0xffff,iacc0l ; 7fffffff*7fffffff+ + test_spr_limmed 0x7fff,0xffff,iacc0h ; 40000000fffffffe + +smass30: + set_gr_limmed 0x7fff,0xffff,gr7 ; just barely overflow (pos) + set_gr_limmed 0x7fff,0xffff,gr8 + set_spr_limmed 0xffff,0xffff,iacc0l + set_spr_limmed 0x4000,0x0000,iacc0h + smass gr7,gr8 + test_gr_limmed 0x7fff,0xffff,gr8 + test_gr_limmed 0x7fff,0xffff,gr7 + test_spr_limmed 0xffff,0xffff,iacc0l ; 7fffffff*7fffffff+ + test_spr_limmed 0x7fff,0xffff,iacc0h ; 40000000ffffffff + +smass31: + set_gr_limmed 0x7fff,0xffff,gr7 ; maximum overflow (pos) + set_gr_limmed 0x7fff,0xffff,gr8 + set_spr_limmed 0xffff,0xffff,iacc0l + set_spr_limmed 0x7fff,0xffff,iacc0h + smass gr7,gr8 + test_gr_limmed 0x7fff,0xffff,gr8 + test_gr_limmed 0x7fff,0xffff,gr7 + test_spr_limmed 0xffff,0xffff,iacc0l ; 7fffffff*7fffffff+ + test_spr_limmed 0x7fff,0xffff,iacc0h ; 7fffffffffffffff + +smass32: + set_gr_limmed 0x7fff,0xffff,gr7 ; not quite overflow (neg) + set_gr_limmed 0x8000,0x0000,gr8 + set_spr_limmed 0x8000,0x0000,iacc0l + set_spr_limmed 0xbfff,0xffff,iacc0h + smass gr7,gr8 + test_gr_limmed 0x8000,0x0000,gr8 + test_gr_limmed 0x7fff,0xffff,gr7 + test_spr_limmed 0x0000,0x0000,iacc0l ; 7fffffff*7fffffff+ + test_spr_limmed 0x8000,0x0000,iacc0h ; bfffffff80000000 + +smass33: + set_gr_limmed 0x7fff,0xffff,gr7 ; just barely overflow (neg) + set_gr_limmed 0x8000,0x0000,gr8 + set_spr_limmed 0x7fff,0xffff,iacc0l + set_spr_limmed 0xbfff,0xffff,iacc0h + smass gr7,gr8 + test_gr_limmed 0x8000,0x0000,gr8 + test_gr_limmed 0x7fff,0xffff,gr7 + test_spr_limmed 0x0000,0x0000,iacc0l ; 7fffffff*7fffffff+ + test_spr_limmed 0x8000,0x0000,iacc0h ; bfffffff7fffffff + +smass34: + set_gr_limmed 0x7fff,0xffff,gr7 ; maximum overflow (neg) + set_gr_limmed 0x8000,0x0000,gr8 + set_spr_limmed 0x0000,0x0000,iacc0l + set_spr_limmed 0x8000,0x0000,iacc0h + smass gr7,gr8 + test_gr_limmed 0x8000,0x0000,gr8 + test_gr_limmed 0x7fff,0xffff,gr7 + test_spr_limmed 0x0000,0x0000,iacc0l ; 7fffffff*7fffffff+ + test_spr_limmed 0x8000,0x0000,iacc0h ; 8000000000000000 + + pass diff --git a/sim/testsuite/sim/frv/fr400/smsss.cgs b/sim/testsuite/sim/frv/fr400/smsss.cgs new file mode 100644 index 0000000..56efa56 --- /dev/null +++ b/sim/testsuite/sim/frv/fr400/smsss.cgs @@ -0,0 +1,354 @@ +# frv testcase for smsss $GRi,$GRj +# mach: fr400 + + .include "../testutils.inc" + + start + + .global smsss +smsss1: + ; Positive operands + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + set_spr_immed 0,iacc0h + set_spr_immed 7,iacc0l + smsss gr7,gr8 + test_gr_immed 3,gr7 + test_gr_immed 2,gr8 + test_spr_immed 1,iacc0l ; result 7-3*2 + test_spr_immed 0,iacc0h +smsss2: + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed 2,gr8 + set_spr_immed 0,iacc0h + set_spr_immed 3,iacc0l + smsss gr7,gr8 + test_gr_immed 1,gr7 + test_gr_immed 2,gr8 + test_spr_immed 1,iacc0l ; result 3-1*2 + test_spr_immed 0,iacc0h +smsss3: + set_gr_immed 2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + set_spr_immed 0,iacc0h + set_spr_immed 3,iacc0l + smsss gr7,gr8 + test_gr_immed 1,gr8 + test_gr_immed 2,gr7 + test_spr_immed 1,iacc0l ; result 3-2*1 + test_spr_immed 0,iacc0h +smsss4: + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed 2,gr8 + set_spr_immed 0,iacc0h + set_spr_immed 1,iacc0l + smsss gr7,gr8 + test_gr_immed 2,gr8 + test_gr_immed 0,gr7 + test_spr_immed 1,iacc0l ; result 1-0*2 + test_spr_immed 0,iacc0h +smsss5: + set_gr_immed 2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + set_spr_immed 0,iacc0h + set_spr_immed 1,iacc0l + smsss gr7,gr8 + test_gr_immed 0,gr8 + test_gr_immed 2,gr7 + test_spr_immed 1,iacc0l ; result 1-2*0 + test_spr_immed 0,iacc0h +smsss6: + set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result + set_gr_immed 2,gr8 + set_spr_immed -1,iacc0h + set_spr_immed -1,iacc0l + smsss gr7,gr8 + test_gr_immed 2,gr8 + test_gr_limmed 0x3fff,0xffff,gr7 + test_spr_limmed 0x8000,0x0001,iacc0l ; -1-3fffffff*2 + test_spr_immed -1,iacc0h +smsss7: + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed 2,gr8 + set_spr_immed -1,iacc0h + set_spr_limmed 0x8000,0x0001,iacc0l + smsss gr7,gr8 + test_gr_immed 2,gr8 + test_gr_limmed 0x4000,0x0000,gr7 + test_spr_immed 1,iacc0l ; ffffffff80000001-40000000*2 + test_spr_immed -1,iacc0h +smsss8: + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed 4,gr8 + set_spr_immed -1,iacc0h + set_spr_immed 1,iacc0l + smsss gr7,gr8 + test_gr_immed 4,gr8 + test_gr_limmed 0x4000,0x0000,gr7 + test_spr_immed 1,iacc0l ; ffffffff00000001-40000000*4 + test_spr_immed -2,iacc0h +smsss9: + set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result + set_gr_limmed 0x7fff,0xffff,gr8 + set_spr_limmed 0x7fff,0xffff,iacc0h + set_spr_immed -1,iacc0l + smsss gr7,gr8 + test_gr_limmed 0x7fff,0xffff,gr8 + test_gr_limmed 0x7fff,0xffff,gr7 + test_spr_limmed 0xffff,0xfffe,iacc0l ; 7fffffffffffffff-7fffffff*7fffffff + test_spr_limmed 0x4000,0x0000,iacc0h +smsss10: + ; Mixed operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + set_spr_immed -1,iacc0h + set_spr_immed -5,iacc0l + smsss gr7,gr8 + test_gr_immed 2,gr8 + test_gr_immed -3,gr7 + test_spr_immed 1,iacc0l ; -5-(-3*2) + test_spr_immed 0,iacc0h +smsss11: + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + set_spr_immed -1,iacc0h + set_spr_immed -5,iacc0l + smsss gr7,gr8 + test_gr_immed -2,gr8 + test_gr_immed 3,gr7 + test_spr_immed 1,iacc0l ; -5-(3*-2) + test_spr_immed 0,iacc0h +smsss12: + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + set_spr_immed -1,iacc0h + set_spr_immed -1,iacc0l + smsss gr7,gr8 + test_gr_immed -2,gr8 + test_gr_immed 1,gr7 + test_spr_immed 1,iacc0l ; -1-(1*-2) + test_spr_immed 0,iacc0h +smsss13: + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + set_spr_immed -1,iacc0h + set_spr_immed -1,iacc0l + smsss gr7,gr8 + test_gr_immed 1,gr8 + test_gr_immed -2,gr7 + test_spr_immed 1,iacc0l ; -1-(-2*1) + test_spr_immed 0,iacc0h +smsss14: + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed -2,gr8 + set_spr_immed 0,iacc0h + set_spr_immed 1,iacc0l + smsss gr7,gr8 + test_gr_immed -2,gr8 + test_gr_immed 0,gr7 + test_spr_immed 1,iacc0l ; 1-(0*-2) + test_spr_immed 0,iacc0h +smsss15: + set_gr_immed -2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + set_spr_immed 0,iacc0h + set_spr_immed 1,iacc0l + smsss gr7,gr8 + test_gr_immed 0,gr8 + test_gr_immed -2,gr7 + test_spr_immed 1,iacc0l ; 1-(-2*0) + test_spr_immed 0,iacc0h +smsss16: + set_gr_limmed 0x2000,0x0000,gr7 ; 31 bit result + set_gr_immed -2,gr8 + set_spr_immed 0,iacc0h + set_spr_limmed 0x3fff,0xffff,iacc0l + smsss gr7,gr8 + test_gr_immed -2,gr8 + test_gr_limmed 0x2000,0x0000,gr7 + test_spr_limmed 0x7fff,0xffff,iacc0l + test_spr_immed 0,iacc0h ; 3fffffff-20000001*-2 +smsss17: + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + set_spr_immed 0,iacc0h + set_spr_immed 1,iacc0l + smsss gr7,gr8 + test_gr_immed -2,gr8 + test_gr_limmed 0x4000,0x0000,gr7 + test_spr_limmed 0x8000,0x0001,iacc0l ; 1-40000000*-2 + test_spr_immed 0,iacc0h +smsss18: + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + set_spr_immed -1,iacc0h + set_spr_immed -1,iacc0l + smsss gr7,gr8 + test_gr_immed -2,gr8 + test_gr_limmed 0x4000,0x0000,gr7 + test_spr_limmed 0x7fff,0xffff,iacc0l + test_spr_immed 0,iacc0h ; -1-40000000*-2 +smsss19: + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed -4,gr8 + set_spr_immed 0,iacc0h + set_spr_immed 1,iacc0l + smsss gr7,gr8 + test_gr_immed -4,gr8 + test_gr_limmed 0x4000,0x0000,gr7 + test_spr_immed 1,iacc0l ; 200000001-(40000000*-4) + test_spr_immed 1,iacc0h +smsss20: + set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result + set_gr_limmed 0x7fff,0xffff,gr8 + set_spr_limmed 0xbfff,0xffff,iacc0h + set_spr_limmed 0x0000,0x0001,iacc0l + smsss gr7,gr8 + test_gr_limmed 0x7fff,0xffff,gr8 + test_gr_limmed 0x7fff,0xffff,gr7 + test_spr_immed 0,iacc0l ; bfffffff00000001-(7fffffff*7fffffff) + test_spr_limmed 0x8000,0x0000,iacc0h +smsss21: + ; Negative operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + set_spr_immed 0,iacc0h + set_spr_immed 7,iacc0l + smsss gr7,gr8 + test_gr_immed -2,gr8 + test_gr_immed -3,gr7 + test_spr_immed 1,iacc0l ; 7-(-3*-2) + test_spr_immed 0,iacc0h +smsss22: + set_gr_immed -1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + set_spr_immed 0,iacc0h + set_spr_immed 3,iacc0l + smsss gr7,gr8 + test_gr_immed -2,gr8 + test_gr_immed -1,gr7 + test_spr_immed 1,iacc0l ; 3-(-1*-2) + test_spr_immed 0,iacc0h +smsss23: + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed -1,gr8 + set_spr_immed 0,iacc0h + set_spr_immed 3,iacc0l + smsss gr7,gr8 + test_gr_immed -1,gr8 + test_gr_immed -2,gr7 + test_spr_immed 1,iacc0l ; 3-(-2*-1) + test_spr_immed 0,iacc0h +smsss24: + set_gr_immed -32768,gr7 ; 31 bit result + set_gr_immed -32768,gr8 + set_spr_immed 0,iacc0h + set_spr_limmed 0xbfff,0xffff,iacc0l + smsss gr7,gr8 + test_gr_immed -32768,gr8 + test_gr_immed -32768,gr7 + test_spr_limmed 0x7fff,0xffff,iacc0l ; 7ffffffb-(-2*-2) + test_spr_immed 0,iacc0h +smsss25: + set_gr_immed 0xffff,gr7 ; 32 bit result + set_gr_immed 0xffff,gr8 + set_spr_immed 1,iacc0h + set_spr_limmed 0xfffe,0x0000,iacc0l + smsss gr7,gr8 + test_gr_immed 0xffff,gr8 + test_gr_immed 0xffff,gr7 + test_spr_limmed 0xffff,0xffff,iacc0l ; 1fffe0000-ffff*ffff + test_spr_immed 0,iacc0h +smsss26: + set_gr_limmed 0x0001,0x0000,gr7 ; 33 bit result + set_gr_limmed 0x0001,0x0000,gr8 + set_spr_immed 2,iacc0h + set_spr_immed 1,iacc0l + smsss gr7,gr8 + test_gr_limmed 0x0001,0x0000,gr8 + test_gr_limmed 0x0001,0x0000,gr7 + test_spr_immed 1,iacc0l ; 0x200000001-0x10000*0x10000 + test_spr_immed 1,iacc0h +smsss27: + set_gr_immed -2,gr7 ; almost max positive result + set_gr_immed -2,gr8 + set_spr_limmed 0x7fff,0xffff,iacc0h + set_spr_limmed 0xffff,0xffff,iacc0l + smsss gr7,gr8 + test_gr_immed -2,gr8 + test_gr_immed -2,gr7 + test_spr_limmed 0xffff,0xfffb,iacc0l ; maxpos - (-2*-2) + test_spr_limmed 0x7fff,0xffff,iacc0h +smsss28: + set_gr_immed 0,gr7 ; max positive result + set_gr_immed 0,gr8 + set_spr_limmed 0x7fff,0xffff,iacc0h + set_spr_limmed 0xffff,0xffff,iacc0l + smsss gr7,gr8 + test_gr_immed 0,gr8 + test_gr_immed 0,gr7 + test_spr_limmed 0xffff,0xffff,iacc0l ; maxpos-(0*0) + test_spr_limmed 0x7fff,0xffff,iacc0h +smsss29: + set_gr_limmed 0x7fff,0xffff,gr7 ; not quite overflow (pos) + set_gr_limmed 0x8000,0x0000,gr8 + set_spr_limmed 0x4000,0x0000,iacc0h + set_spr_limmed 0x7fff,0xffff,iacc0l + smsss gr7,gr8 + test_gr_limmed 0x8000,0x0000,gr8 + test_gr_limmed 0x7fff,0xffff,gr7 + test_spr_limmed 0xffff,0xffff,iacc0l ; 400000007fffffff - + test_spr_limmed 0x7fff,0xffff,iacc0h ; 0x80000000*0x7fffffff +smsss30: + set_gr_limmed 0x7fff,0xffff,gr7 ; just barely overflow (pos) + set_gr_limmed 0x8000,0x0000,gr8 + set_spr_limmed 0x4000,0x0000,iacc0h + set_spr_limmed 0x8000,0x0000,iacc0l + smsss gr7,gr8 + test_gr_limmed 0x8000,0x0000,gr8 + test_gr_limmed 0x7fff,0xffff,gr7 + test_spr_limmed 0xffff,0xffff,iacc0l ; 4000000080000000 - + test_spr_limmed 0x7fff,0xffff,iacc0h ; 0x80000000*0x7fffffff + +smsss31: + set_gr_limmed 0x7fff,0xffff,gr7 ; maximum overflow (pos) + set_gr_limmed 0x8000,0x0000,gr8 + set_spr_limmed 0xffff,0xffff,iacc0l + set_spr_limmed 0x7fff,0xffff,iacc0h + smsss gr7,gr8 + test_gr_limmed 0x8000,0x0000,gr8 + test_gr_limmed 0x7fff,0xffff,gr7 + test_spr_limmed 0xffff,0xffff,iacc0l ; 7fffffffffffffff - + test_spr_limmed 0x7fff,0xffff,iacc0h ; 80000000*80000000 +smsss32: + set_gr_limmed 0x7fff,0xffff,gr7 ; not quite overflow (neg) + set_gr_limmed 0x7fff,0xffff,gr8 + set_spr_immed 1,iacc0l + set_spr_limmed 0xbfff,0xffff,iacc0h + smsss gr7,gr8 + test_gr_limmed 0x7fff,0xffff,gr8 + test_gr_limmed 0x7fff,0xffff,gr7 + test_spr_limmed 0x0000,0x0000,iacc0l ; bfffffff00000001 - + test_spr_limmed 0x8000,0x0000,iacc0h ; 0x7fffffff*0x7fffffff +smsss33: + set_gr_limmed 0x7fff,0xffff,gr7 ; just barely overflow (neg) + set_gr_limmed 0x7fff,0xffff,gr8 + set_spr_immed 0,iacc0l + set_spr_limmed 0xbfff,0xffff,iacc0h + smsss gr7,gr8 + test_gr_limmed 0x7fff,0xffff,gr8 + test_gr_limmed 0x7fff,0xffff,gr7 + test_spr_limmed 0x0000,0x0000,iacc0l ; 7fffffff*7fffffff+ + test_spr_limmed 0x8000,0x0000,iacc0h ; bfffffff7fffffff +smsss34: + set_gr_limmed 0x7fff,0xffff,gr7 ; maximum overflow (neg) + set_gr_limmed 0x7fff,0xffff,gr8 + set_spr_limmed 0x0000,0x0000,iacc0l + set_spr_limmed 0x8000,0x0000,iacc0h + smsss gr7,gr8 + test_gr_limmed 0x7fff,0xffff,gr8 + test_gr_limmed 0x7fff,0xffff,gr7 + test_spr_limmed 0x0000,0x0000,iacc0l ; 8000000000000000- + test_spr_limmed 0x8000,0x0000,iacc0h ; 7fffffff*7fffffff+ + + pass diff --git a/sim/testsuite/sim/frv/fr400/smu.cgs b/sim/testsuite/sim/frv/fr400/smu.cgs new file mode 100644 index 0000000..d0087df --- /dev/null +++ b/sim/testsuite/sim/frv/fr400/smu.cgs @@ -0,0 +1,237 @@ +# frv testcase for smu $GRi,$GRj +# mach: fr400 + + .include "../testutils.inc" + + start + + .global smu +smu1: + ; Positive operands + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + smu gr7,gr8 + test_gr_immed 3,gr7 + test_gr_immed 2,gr8 + test_spr_immed 6,iacc0l + test_spr_immed 0,iacc0h +smu2: + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed 2,gr8 + smu gr7,gr8 + test_gr_immed 1,gr7 + test_gr_immed 2,gr8 + test_spr_immed 2,iacc0l + test_spr_immed 0,iacc0h +smu3: + set_gr_immed 2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + smu gr7,gr8 + test_gr_immed 1,gr8 + test_gr_immed 2,gr7 + test_spr_immed 2,iacc0l + test_spr_immed 0,iacc0h +smu4: + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed 2,gr8 + smu gr7,gr8 + test_gr_immed 2,gr8 + test_gr_immed 0,gr7 + test_spr_immed 0,iacc0l + test_spr_immed 0,iacc0h +smu5: + set_gr_immed 2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + smu gr7,gr8 + test_gr_immed 0,gr8 + test_gr_immed 2,gr7 + test_spr_immed 0,iacc0l + test_spr_immed 0,iacc0h +smu6: + set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result + set_gr_immed 2,gr8 + smu gr7,gr8 + test_gr_immed 2,gr8 + test_gr_limmed 0x3fff,0xffff,gr7 + test_spr_limmed 0x7fff,0xfffe,iacc0l + test_spr_immed 0,iacc0h +smu7: + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed 2,gr8 + smu gr7,gr8 + test_gr_immed 2,gr8 + test_gr_limmed 0x4000,0x0000,gr7 + test_spr_limmed 0x8000,0x0000,iacc0l + test_spr_immed 0,iacc0h +smu8: + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed 4,gr8 + smu gr7,gr8 + test_gr_immed 4,gr8 + test_gr_limmed 0x4000,0x0000,gr7 + test_spr_immed 0,iacc0l + test_spr_immed 1,iacc0h +smu9: + set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result + set_gr_limmed 0x7fff,0xffff,gr8 + smu gr7,gr8 + test_gr_limmed 0x7fff,0xffff,gr8 + test_gr_limmed 0x7fff,0xffff,gr7 + test_spr_immed 0x00000001,iacc0l + test_spr_limmed 0x3fff,0xffff,iacc0h +smu10: + ; Mixed operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + smu gr7,gr8 + test_gr_immed 2,gr8 + test_gr_immed -3,gr7 + test_spr_immed -6,iacc0l + test_spr_immed -1,iacc0h +smu11: + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + smu gr7,gr8 + test_gr_immed -2,gr8 + test_gr_immed 3,gr7 + test_spr_immed -6,iacc0l + test_spr_immed -1,iacc0h +smu12: + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + smu gr7,gr8 + test_gr_immed -2,gr8 + test_gr_immed 1,gr7 + test_spr_immed -2,iacc0l + test_spr_immed -1,iacc0h +smu13: + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + smu gr7,gr8 + test_gr_immed 1,gr8 + test_gr_immed -2,gr7 + test_spr_immed -2,iacc0l + test_spr_immed -1,iacc0h +smu14: + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed -2,gr8 + smu gr7,gr8 + test_gr_immed -2,gr8 + test_gr_immed 0,gr7 + test_spr_immed 0,iacc0l + test_spr_immed 0,iacc0h +smu15: + set_gr_immed -2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + smu gr7,gr8 + test_gr_immed 0,gr8 + test_gr_immed -2,gr7 + test_spr_immed 0,iacc0l + test_spr_immed 0,iacc0h +smu16: + set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result + set_gr_immed -2,gr8 + smu gr7,gr8 + test_gr_immed -2,gr8 + test_gr_limmed 0x2000,0x0001,gr7 + test_spr_limmed 0xbfff,0xfffe,iacc0l + test_spr_limmed 0xffff,0xffff,iacc0h +smu17: + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + smu gr7,gr8 + test_gr_immed -2,gr8 + test_gr_limmed 0x4000,0x0000,gr7 + test_spr_limmed 0x8000,0x0000,iacc0l + test_spr_limmed 0xffff,0xffff,iacc0h +smu18: + set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result + set_gr_immed -2,gr8 + smu gr7,gr8 + test_gr_immed -2,gr8 + test_gr_limmed 0x4000,0x0001,gr7 + test_spr_limmed 0x7fff,0xfffe,iacc0l + test_spr_limmed 0xffff,0xffff,iacc0h +smu19: + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed -4,gr8 + smu gr7,gr8 + test_gr_immed -4,gr8 + test_gr_limmed 0x4000,0x0000,gr7 + test_spr_limmed 0x0000,0x0000,iacc0l + test_spr_limmed 0xffff,0xffff,iacc0h +smu20: + set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result + set_gr_limmed 0x8000,0x0000,gr8 + smu gr7,gr8 + test_gr_limmed 0x8000,0x0000,gr8 + test_gr_limmed 0x7fff,0xffff,gr7 + test_spr_limmed 0x8000,0x0000,iacc0l + test_spr_limmed 0xc000,0x0000,iacc0h +smu21: + ; Negative operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + smu gr7,gr8 + test_gr_immed -2,gr8 + test_gr_immed -3,gr7 + test_spr_immed 6,iacc0l + test_spr_immed 0,iacc0h +smu22: + set_gr_immed -1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + smu gr7,gr8 + test_gr_immed -2,gr8 + test_gr_immed -1,gr7 + test_spr_immed 2,iacc0l + test_spr_immed 0,iacc0h +smu23: + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed -1,gr8 + smu gr7,gr8 + test_gr_immed -1,gr8 + test_gr_immed -2,gr7 + test_spr_immed 2,iacc0l + test_spr_immed 0,iacc0h +smu24: + set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result + set_gr_immed -2,gr8 + smu gr7,gr8 + test_gr_immed -2,gr8 + test_gr_limmed 0xc000,0x0001,gr7 + test_spr_limmed 0x7fff,0xfffe,iacc0l + test_spr_immed 0,iacc0h +smu25: + set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + smu gr7,gr8 + test_gr_immed -2,gr8 + test_gr_limmed 0xc000,0x0000,gr7 + test_spr_limmed 0x8000,0x0000,iacc0l + test_spr_immed 0,iacc0h +smu26: + set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result + set_gr_immed -4,gr8 + smu gr7,gr8 + test_gr_immed -4,gr8 + test_gr_limmed 0xc000,0x0000,gr7 + test_spr_immed 0x00000000,iacc0l + test_spr_immed 1,iacc0h +smu27: + set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result + set_gr_limmed 0x8000,0x0001,gr8 + smu gr7,gr8 + test_gr_limmed 0x8000,0x0001,gr8 + test_gr_limmed 0x8000,0x0001,gr7 + test_spr_immed 0x00000001,iacc0l + test_spr_limmed 0x3fff,0xffff,iacc0h +smu28: + set_gr_limmed 0x8000,0x0000,gr7 ; max positive result + set_gr_limmed 0x8000,0x0000,gr8 + smu gr7,gr8 + test_gr_limmed 0x8000,0x0000,gr8 + test_gr_limmed 0x8000,0x0000,gr7 + test_spr_immed 0x00000000,iacc0l + test_spr_limmed 0x4000,0x0000,iacc0h + + pass diff --git a/sim/testsuite/sim/frv/fr400/subss.cgs b/sim/testsuite/sim/frv/fr400/subss.cgs new file mode 100644 index 0000000..cbaafb5 --- /dev/null +++ b/sim/testsuite/sim/frv/fr400/subss.cgs @@ -0,0 +1,43 @@ +# frv testcase for subss $GRi,$GRj,$GRk +# mach: fr400 + + .include "../testutils.inc" + + start + + .global sub +sub_no_saturate: + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + subss gr8,gr7,gr8 + test_gr_immed 1,gr8 + + set_gr_immed 2,gr7 + set_gr_immed 1,gr8 + subss gr8,gr7,gr8 + test_gr_limmed 0xffff,0xffff,gr8 + +sub_saturate_neg: + set_gr_immed 1,gr7 + set_gr_limmed 0x8000,0x0000,gr8 + subss gr8,gr7,gr8 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0x7fff,0xffff,gr7 + set_gr_limmed 0xffff,0xfff0,gr8 + subss gr8,gr7,gr8 + test_gr_limmed 0x8000,0x0000,gr8 + +sub_saturate_pos: + set_gr_limmed 0xffff,0xffff,gr7 + set_gr_limmed 0x7fff,0xffff,gr8 + subss gr8,gr7,gr8 + test_gr_limmed 0x7fff,0xffff,gr8 + + set_gr_immed 0x0010,gr8 + set_gr_limmed 0x8000,0x0000,gr7 + subss gr8,gr7,gr8 + test_gr_limmed 0x7fff,0xffff,gr8 + + + pass diff --git a/sim/testsuite/sim/frv/fr400/udiv.cgs b/sim/testsuite/sim/frv/fr400/udiv.cgs new file mode 100644 index 0000000..dd92bcd --- /dev/null +++ b/sim/testsuite/sim/frv/fr400/udiv.cgs @@ -0,0 +1,46 @@ +# frv testcase for udiv $GRi,$GRj,$GRk +# mach: fr400 + + .include "../testutils.inc" + + start + + .global udiv +udiv: + ; simple division 12 / 3 + set_gr_immed 0x00000003,gr2 + set_gr_immed 0x0000000c,gr3 + udiv gr3,gr2,gr3 + test_gr_immed 0x00000003,gr2 + test_gr_immed 0x00000004,gr3 + + ; example 1 from udiv in the fr30 manual + set_gr_limmed 0x0123,0x4567,gr2 + set_gr_limmed 0xfedc,0xba98,gr3 + udiv gr3,gr2,gr3 + test_gr_limmed 0x0123,0x4567,gr2 + test_gr_immed 0x000000e0,gr3 + + ; set up exception handler + set_psr_et 1 + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr17 + inc_gr_immed 0x170,gr17 ; address of exception handler + set_bctrlr_0_0 gr17 + set_spr_immed 128,lcr + set_gr_immed 0,gr15 + + ; divide by zero + set_spr_addr ok1,lr +e1: udiv gr1,gr0,gr2 ; divide by zero + test_gr_immed 1,gr15 + + pass + +ok1: ; exception handler for divide by zero + test_spr_bits 0x18,3,0x1,isr ; isr.dtt is set + test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid + test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set + inc_gr_immed 1,gr15 + rett 0 + fail diff --git a/sim/testsuite/sim/frv/fr400/udivi.cgs b/sim/testsuite/sim/frv/fr400/udivi.cgs new file mode 100644 index 0000000..69a7937 --- /dev/null +++ b/sim/testsuite/sim/frv/fr400/udivi.cgs @@ -0,0 +1,47 @@ +# frv testcase for udivi $GRi,$s12,$GRk +# mach: fr400 + + .include "../testutils.inc" + + start + + .global udivi +udivi: + ; simple division 12 / 3 + set_gr_immed 0x0000000c,gr3 + udivi gr3,3,gr3 + test_gr_immed 0x00000004,gr3 + + ; random example + set_gr_limmed 0xfedc,0xba98,gr3 + udivi gr3,0x7ff,gr3 + test_gr_limmed 0x001f,0xdf93,gr3 + + ; random example + set_gr_limmed 0xffff,0xffff,gr3 + udivi gr3,-2048,gr3 + test_gr_immed 1,gr3 + + ; set up exception handler + set_psr_et 1 + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr17 + inc_gr_immed 0x170,gr17 ; address of exception handler + set_bctrlr_0_0 gr17 + set_spr_immed 128,lcr + set_gr_immed 0,gr15 + + ; divide by zero + set_spr_addr ok1,lr +e1: udivi gr1,0,gr2 ; divide by zero + test_gr_immed 1,gr15 + + pass + +ok1: ; exception handler for divide by zero + test_spr_bits 0x18,3,0x1,isr ; isr.dtt is set + test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid + test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set + inc_gr_immed 1,gr15 + rett 0 + fail diff --git a/sim/testsuite/sim/frv/fr500/allinsn.exp b/sim/testsuite/sim/frv/fr500/allinsn.exp new file mode 100644 index 0000000..7d19259 --- /dev/null +++ b/sim/testsuite/sim/frv/fr500/allinsn.exp @@ -0,0 +1,19 @@ +# FRV simulator testsuite. + +if [istarget frv*-*] { + # load support procs (none yet) + # load_lib cgen.exp + # all machines + set all_machs "frv fr500 fr550" + set cpu_option -mcpu + + # The .cgs suffix is for "cgen .s". + foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.cgs]] { + # If we're only testing specific files and this isn't one of them, + # skip it. + if ![runtest_file_p $runtests $src] { + continue + } + run_sim_test $src $all_machs + } +} diff --git a/sim/testsuite/sim/frv/fr500/cmqaddhss.cgs b/sim/testsuite/sim/frv/fr500/cmqaddhss.cgs new file mode 100644 index 0000000..9c88620 --- /dev/null +++ b/sim/testsuite/sim/frv/fr500/cmqaddhss.cgs @@ -0,0 +1,444 @@ +# frv testcase for cmqaddhss $FRi,$FRj,$FRj,$CCi,$cond +# mach: frv fr500 + + .include "../testutils.inc" + + start + + .global cmqaddhss +cmqaddhss: + set_spr_immed 0x1b1b,cccr + + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + cmqaddhss fr10,fr12,fr14,cc0,1 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0xdead,0xbeef,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + cmqaddhss fr10,fr12,fr14,cc0,1 + test_fr_limmed 0xbeef,0xdead,fr14 + test_fr_limmed 0x2345,0x6789,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0xffff,0xffff,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqaddhss fr10,fr12,fr14,cc0,1 + test_fr_limmed 0x1233,0x5677,fr14 + test_fr_limmed 0x7fff,0x7fff,fr15 + test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8001,0x8001,fr11 + set_fr_iimmed 0xffff,0xfffe,fr12 + set_fr_iimmed 0xfffe,0xfffe,fr13 + cmqaddhss fr10,fr12,fr14,cc4,1 + test_fr_limmed 0x8000,0x8000,fr14 + test_fr_limmed 0x8000,0x8000,fr15 + test_spr_bits 0x3c,2,0x7,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + set_fr_iimmed 0x7fff,0x0000,fr12 + set_fr_iimmed 0x0000,0x8000,fr13 + cmqaddhss.p fr10,fr10,fr14,cc4,1 + cmqaddhss fr12,fr12,fr16,cc4,1 + test_fr_limmed 0x0002,0x0002,fr14 + test_fr_limmed 0xfffe,0xfffe,fr15 + test_fr_limmed 0x7fff,0x0000,fr16 + test_fr_limmed 0x0000,0x8000,fr17 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie not set + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 0x3c,2,0x9,msr1 ; msr1.sie is set + test_spr_bits 2,1,1,msr1 ; msr1.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + cmqaddhss fr10,fr12,fr14,cc1,0 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0xdead,0xbeef,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + cmqaddhss fr10,fr12,fr14,cc1,0 + test_fr_limmed 0xbeef,0xdead,fr14 + test_fr_limmed 0x2345,0x6789,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0xffff,0xffff,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqaddhss fr10,fr12,fr14,cc1,0 + test_fr_limmed 0x1233,0x5677,fr14 + test_fr_limmed 0x7fff,0x7fff,fr15 + test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8001,0x8001,fr11 + set_fr_iimmed 0xffff,0xfffe,fr12 + set_fr_iimmed 0xfffe,0xfffe,fr13 + cmqaddhss fr10,fr12,fr14,cc5,0 + test_fr_limmed 0x8000,0x8000,fr14 + test_fr_limmed 0x8000,0x8000,fr15 + test_spr_bits 0x3c,2,0x7,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + set_fr_iimmed 0x7fff,0x0000,fr12 + set_fr_iimmed 0x0000,0x8000,fr13 + cmqaddhss.p fr10,fr10,fr14,cc5,0 + cmqaddhss fr12,fr12,fr16,cc5,0 + test_fr_limmed 0x0002,0x0002,fr14 + test_fr_limmed 0xfffe,0xfffe,fr15 + test_fr_limmed 0x7fff,0x0000,fr16 + test_fr_limmed 0x0000,0x8000,fr17 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie not set + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 0x3c,2,0x9,msr1 ; msr1.sie is set + test_spr_bits 2,1,1,msr1 ; msr1.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_fr_iimmed 0x1111,0x1111,fr14 + set_fr_iimmed 0x2222,0x2222,fr15 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + cmqaddhss fr10,fr12,fr14,cc0,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + cmqaddhss fr10,fr12,fr14,cc0,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0xffff,0xffff,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqaddhss fr10,fr12,fr14,cc0,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8001,0x8001,fr11 + set_fr_iimmed 0xffff,0xfffe,fr12 + set_fr_iimmed 0xfffe,0xfffe,fr13 + cmqaddhss fr10,fr12,fr14,cc4,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x3333,0x3333,fr16 + set_fr_iimmed 0x4444,0x4444,fr17 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + set_fr_iimmed 0x7fff,0x0000,fr12 + set_fr_iimmed 0x0000,0x8000,fr13 + cmqaddhss.p fr10,fr10,fr14,cc4,0 + cmqaddhss fr12,fr12,fr16,cc4,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_fr_limmed 0x3333,0x3333,fr16 + test_fr_limmed 0x4444,0x4444,fr17 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1111,0x1111,fr14 + set_fr_iimmed 0x2222,0x2222,fr15 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + cmqaddhss fr10,fr12,fr14,cc1,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + cmqaddhss fr10,fr12,fr14,cc1,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0xffff,0xffff,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqaddhss fr10,fr12,fr14,cc1,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8001,0x8001,fr11 + set_fr_iimmed 0xffff,0xfffe,fr12 + set_fr_iimmed 0xfffe,0xfffe,fr13 + cmqaddhss fr10,fr12,fr14,cc5,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x3333,0x3333,fr16 + set_fr_iimmed 0x4444,0x4444,fr17 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + set_fr_iimmed 0x7fff,0x0000,fr12 + set_fr_iimmed 0x0000,0x8000,fr13 + cmqaddhss.p fr10,fr10,fr14,cc5,1 + cmqaddhss fr12,fr12,fr16,cc5,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_fr_limmed 0x3333,0x3333,fr16 + test_fr_limmed 0x4444,0x4444,fr17 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1111,0x1111,fr14 + set_fr_iimmed 0x2222,0x2222,fr15 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + cmqaddhss fr10,fr12,fr14,cc2,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + cmqaddhss fr10,fr12,fr14,cc2,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0xffff,0xffff,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqaddhss fr10,fr12,fr14,cc2,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8001,0x8001,fr11 + set_fr_iimmed 0xffff,0xfffe,fr12 + set_fr_iimmed 0xfffe,0xfffe,fr13 + cmqaddhss fr10,fr12,fr14,cc6,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x3333,0x3333,fr16 + set_fr_iimmed 0x4444,0x4444,fr17 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + set_fr_iimmed 0x7fff,0x0000,fr12 + set_fr_iimmed 0x0000,0x8000,fr13 + cmqaddhss.p fr10,fr10,fr14,cc6,1 + cmqaddhss fr12,fr12,fr16,cc6,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_fr_limmed 0x3333,0x3333,fr16 + test_fr_limmed 0x4444,0x4444,fr17 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set +; + set_fr_iimmed 0x1111,0x1111,fr14 + set_fr_iimmed 0x2222,0x2222,fr15 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + cmqaddhss fr10,fr12,fr14,cc3,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + cmqaddhss fr10,fr12,fr14,cc3,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0xffff,0xffff,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqaddhss fr10,fr12,fr14,cc3,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8001,0x8001,fr11 + set_fr_iimmed 0xffff,0xfffe,fr12 + set_fr_iimmed 0xfffe,0xfffe,fr13 + cmqaddhss fr10,fr12,fr14,cc7,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x3333,0x3333,fr16 + set_fr_iimmed 0x4444,0x4444,fr17 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + set_fr_iimmed 0x7fff,0x0000,fr12 + set_fr_iimmed 0x0000,0x8000,fr13 + cmqaddhss.p fr10,fr10,fr14,cc7,1 + cmqaddhss fr12,fr12,fr16,cc7,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_fr_limmed 0x3333,0x3333,fr16 + test_fr_limmed 0x4444,0x4444,fr17 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + pass diff --git a/sim/testsuite/sim/frv/fr500/cmqaddhus.cgs b/sim/testsuite/sim/frv/fr500/cmqaddhus.cgs new file mode 100644 index 0000000..5b29c9a --- /dev/null +++ b/sim/testsuite/sim/frv/fr500/cmqaddhus.cgs @@ -0,0 +1,360 @@ +# frv testcase for cmqaddhus $FRi,$FRj,$FRj,$CCi,$cond +# mach: frv fr500 + + .include "../testutils.inc" + + start + + .global cmqaddhus +cmqaddhus: + set_spr_immed 0x1b1b,cccr + + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + cmqaddhus fr10,fr12,fr14,cc0,1 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0xdead,0xbeef,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + cmqaddhus fr10,fr12,fr14,cc0,1 + test_fr_limmed 0xbeef,0xdead,fr14 + test_fr_limmed 0x2345,0x6789,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + set_fr_iimmed 0x0002,0x0001,fr12 + set_fr_iimmed 0x0001,0x0002,fr13 + cmqaddhus fr10,fr12,fr14,cc4,1 + test_fr_limmed 0x8000,0x7fff,fr14 + test_fr_limmed 0xffff,0xffff,fr15 + test_spr_bits 0x3c,2,1,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0002,0x0001,fr10 + set_fr_iimmed 0x0001,0x0001,fr11 + set_fr_iimmed 0xfffe,0xfffe,fr12 + set_fr_iimmed 0x8000,0x8000,fr13 + cmqaddhus.p fr10,fr10,fr14,cc4,1 + cmqaddhus fr12,fr12,fr16,cc4,1 + test_fr_limmed 0x0004,0x0002,fr14 + test_fr_limmed 0x0002,0x0002,fr15 + test_fr_limmed 0xffff,0xffff,fr16 + test_fr_limmed 0xffff,0xffff,fr17 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 0x3c,2,0xf,msr1 ; msr1.sie is set + test_spr_bits 2,1,1,msr1 ; msr1.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + cmqaddhus fr10,fr12,fr14,cc1,0 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0xdead,0xbeef,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + cmqaddhus fr10,fr12,fr14,cc1,0 + test_fr_limmed 0xbeef,0xdead,fr14 + test_fr_limmed 0x2345,0x6789,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + set_fr_iimmed 0x0002,0x0001,fr12 + set_fr_iimmed 0x0001,0x0002,fr13 + cmqaddhus fr10,fr12,fr14,cc5,0 + test_fr_limmed 0x8000,0x7fff,fr14 + test_fr_limmed 0xffff,0xffff,fr15 + test_spr_bits 0x3c,2,1,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0002,0x0001,fr10 + set_fr_iimmed 0x0001,0x0001,fr11 + set_fr_iimmed 0xfffe,0xfffe,fr12 + set_fr_iimmed 0x8000,0x8000,fr13 + cmqaddhus.p fr10,fr10,fr14,cc5,0 + cmqaddhus fr12,fr12,fr16,cc5,0 + test_fr_limmed 0x0004,0x0002,fr14 + test_fr_limmed 0x0002,0x0002,fr15 + test_fr_limmed 0xffff,0xffff,fr16 + test_fr_limmed 0xffff,0xffff,fr17 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 0x3c,2,0xf,msr1 ; msr1.sie is set + test_spr_bits 2,1,1,msr1 ; msr1.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_fr_iimmed 0x1111,0x1111,fr14 + set_fr_iimmed 0x2222,0x2222,fr15 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + cmqaddhus fr10,fr12,fr14,cc0,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + cmqaddhus fr10,fr12,fr14,cc0,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + set_fr_iimmed 0x0002,0x0001,fr12 + set_fr_iimmed 0x0001,0x0002,fr13 + cmqaddhus fr10,fr12,fr14,cc4,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x3333,0x3333,fr16 + set_fr_iimmed 0x4444,0x4444,fr17 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0002,0x0001,fr10 + set_fr_iimmed 0x0001,0x0001,fr11 + set_fr_iimmed 0xfffe,0xfffe,fr12 + set_fr_iimmed 0x8000,0x8000,fr13 + cmqaddhus.p fr10,fr10,fr14,cc4,0 + cmqaddhus fr12,fr12,fr16,cc4,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_fr_limmed 0x3333,0x3333,fr16 + test_fr_limmed 0x4444,0x4444,fr17 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1111,0x1111,fr14 + set_fr_iimmed 0x2222,0x2222,fr15 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + cmqaddhus fr10,fr12,fr14,cc1,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + cmqaddhus fr10,fr12,fr14,cc1,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + set_fr_iimmed 0x0002,0x0001,fr12 + set_fr_iimmed 0x0001,0x0002,fr13 + cmqaddhus fr10,fr12,fr14,cc5,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x3333,0x3333,fr16 + set_fr_iimmed 0x4444,0x4444,fr17 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0002,0x0001,fr10 + set_fr_iimmed 0x0001,0x0001,fr11 + set_fr_iimmed 0xfffe,0xfffe,fr12 + set_fr_iimmed 0x8000,0x8000,fr13 + cmqaddhus.p fr10,fr10,fr14,cc5,1 + cmqaddhus fr12,fr12,fr16,cc5,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_fr_limmed 0x3333,0x3333,fr16 + test_fr_limmed 0x4444,0x4444,fr17 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1111,0x1111,fr14 + set_fr_iimmed 0x2222,0x2222,fr15 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + cmqaddhus fr10,fr12,fr14,cc2,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + cmqaddhus fr10,fr12,fr14,cc2,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + set_fr_iimmed 0x0002,0x0001,fr12 + set_fr_iimmed 0x0001,0x0002,fr13 + cmqaddhus fr10,fr12,fr14,cc6,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x3333,0x3333,fr16 + set_fr_iimmed 0x4444,0x4444,fr17 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0002,0x0001,fr10 + set_fr_iimmed 0x0001,0x0001,fr11 + set_fr_iimmed 0xfffe,0xfffe,fr12 + set_fr_iimmed 0x8000,0x8000,fr13 + cmqaddhus.p fr10,fr10,fr14,cc6,0 + cmqaddhus fr12,fr12,fr16,cc6,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_fr_limmed 0x3333,0x3333,fr16 + test_fr_limmed 0x4444,0x4444,fr17 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1111,0x1111,fr14 + set_fr_iimmed 0x2222,0x2222,fr15 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + cmqaddhus fr10,fr12,fr14,cc3,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + cmqaddhus fr10,fr12,fr14,cc3,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + set_fr_iimmed 0x0002,0x0001,fr12 + set_fr_iimmed 0x0001,0x0002,fr13 + cmqaddhus fr10,fr12,fr14,cc7,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x3333,0x3333,fr16 + set_fr_iimmed 0x4444,0x4444,fr17 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0002,0x0001,fr10 + set_fr_iimmed 0x0001,0x0001,fr11 + set_fr_iimmed 0xfffe,0xfffe,fr12 + set_fr_iimmed 0x8000,0x8000,fr13 + cmqaddhus.p fr10,fr10,fr14,cc7,0 + cmqaddhus fr12,fr12,fr16,cc7,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_fr_limmed 0x3333,0x3333,fr16 + test_fr_limmed 0x4444,0x4444,fr17 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + pass diff --git a/sim/testsuite/sim/frv/fr500/cmqsubhss.cgs b/sim/testsuite/sim/frv/fr500/cmqsubhss.cgs new file mode 100644 index 0000000..4dbee66 --- /dev/null +++ b/sim/testsuite/sim/frv/fr500/cmqsubhss.cgs @@ -0,0 +1,448 @@ +# frv testcase for cmqsubhss $FRi,$FRj,$FRj,$CCi,$cond +# mach: frv fr500 + + .include "../testutils.inc" + + start + + .global msubhss +msubhss: + set_spr_immed 0x1b1b,cccr + + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + cmqsubhss fr10,fr12,fr14,cc0,1 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0xdead,0x4111,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + cmqsubhss fr10,fr12,fr14,cc0,1 + test_fr_limmed 0x4111,0xdead,fr14 + test_fr_limmed 0x0123,0x4567,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0xffff,0xffff,fr12 + set_fr_iimmed 0xfffe,0xffff,fr13 + cmqsubhss fr10,fr12,fr14,cc0,1 + test_fr_limmed 0x1235,0x5679,fr14 + test_fr_limmed 0x7fff,0x7fff,fr15 + test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8001,0x8001,fr11 + set_fr_iimmed 0x0001,0x0002,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqsubhss fr10,fr12,fr14,cc4,1 + test_fr_limmed 0x8000,0x8000,fr14 + test_fr_limmed 0x8000,0x8000,fr15 + test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + set_fr_iimmed 0x8000,0x8000,fr12 + set_fr_iimmed 0x8000,0x8000,fr13 + cmqsubhss.p fr10,fr10,fr14,cc4,1 + cmqsubhss fr12,fr10,fr16,cc4,1 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0x0000,0x0000,fr15 + test_fr_limmed 0x8000,0x8000,fr16 + test_fr_limmed 0x8001,0x8001,fr17 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 0x3c,2,0xc,msr1 ; msr0.sie is set + test_spr_bits 2,1,1,msr1 ; msr1.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + cmqsubhss fr10,fr12,fr14,cc1,0 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0xdead,0x4111,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + cmqsubhss fr10,fr12,fr14,cc1,0 + test_fr_limmed 0x4111,0xdead,fr14 + test_fr_limmed 0x0123,0x4567,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0xffff,0xffff,fr12 + set_fr_iimmed 0xfffe,0xffff,fr13 + cmqsubhss fr10,fr12,fr14,cc1,0 + test_fr_limmed 0x1235,0x5679,fr14 + test_fr_limmed 0x7fff,0x7fff,fr15 + test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8001,0x8001,fr11 + set_fr_iimmed 0x0001,0x0002,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqsubhss fr10,fr12,fr14,cc5,0 + test_fr_limmed 0x8000,0x8000,fr14 + test_fr_limmed 0x8000,0x8000,fr15 + test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + set_fr_iimmed 0x8000,0x8000,fr12 + set_fr_iimmed 0x8000,0x8000,fr13 + cmqsubhss.p fr10,fr10,fr14,cc5,0 + cmqsubhss fr12,fr10,fr16,cc5,0 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0x0000,0x0000,fr15 + test_fr_limmed 0x8000,0x8000,fr16 + test_fr_limmed 0x8001,0x8001,fr17 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 0x3c,2,0xc,msr1 ; msr0.sie is set + test_spr_bits 2,1,1,msr1 ; msr1.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_fr_iimmed 0x1111,0x1111,fr14 + set_fr_iimmed 0x2222,0x2222,fr15 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + cmqsubhss fr10,fr12,fr14,cc0,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + cmqsubhss fr10,fr12,fr14,cc0,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0xffff,0xffff,fr12 + set_fr_iimmed 0xfffe,0xffff,fr13 + cmqsubhss fr10,fr12,fr14,cc0,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8001,0x8001,fr11 + set_fr_iimmed 0x0001,0x0002,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqsubhss fr10,fr12,fr14,cc4,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x3333,0x3333,fr16 + set_fr_iimmed 0x4444,0x4444,fr17 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + set_fr_iimmed 0x8000,0x8000,fr12 + set_fr_iimmed 0x8000,0x8000,fr13 + cmqsubhss.p fr10,fr10,fr14,cc4,0 + cmqsubhss fr12,fr10,fr16,cc4,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_fr_limmed 0x3333,0x3333,fr16 + test_fr_limmed 0x4444,0x4444,fr17 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1111,0x1111,fr14 + set_fr_iimmed 0x2222,0x2222,fr15 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + cmqsubhss fr10,fr12,fr14,cc1,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + cmqsubhss fr10,fr12,fr14,cc1,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0xffff,0xffff,fr12 + set_fr_iimmed 0xfffe,0xffff,fr13 + cmqsubhss fr10,fr12,fr14,cc1,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8001,0x8001,fr11 + set_fr_iimmed 0x0001,0x0002,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqsubhss fr10,fr12,fr14,cc5,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x3333,0x3333,fr16 + set_fr_iimmed 0x4444,0x4444,fr17 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + set_fr_iimmed 0x8000,0x8000,fr12 + set_fr_iimmed 0x8000,0x8000,fr13 + cmqsubhss.p fr10,fr10,fr14,cc5,1 + cmqsubhss fr12,fr10,fr16,cc5,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_fr_limmed 0x3333,0x3333,fr16 + test_fr_limmed 0x4444,0x4444,fr17 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1111,0x1111,fr14 + set_fr_iimmed 0x2222,0x2222,fr15 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + cmqsubhss fr10,fr12,fr14,cc2,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + cmqsubhss fr10,fr12,fr14,cc2,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0xffff,0xffff,fr12 + set_fr_iimmed 0xfffe,0xffff,fr13 + cmqsubhss fr10,fr12,fr14,cc2,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8001,0x8001,fr11 + set_fr_iimmed 0x0001,0x0002,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqsubhss fr10,fr12,fr14,cc6,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x3333,0x3333,fr16 + set_fr_iimmed 0x4444,0x4444,fr17 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + set_fr_iimmed 0x8000,0x8000,fr12 + set_fr_iimmed 0x8000,0x8000,fr13 + cmqsubhss.p fr10,fr10,fr14,cc6,1 + cmqsubhss fr12,fr10,fr16,cc6,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_fr_limmed 0x3333,0x3333,fr16 + test_fr_limmed 0x4444,0x4444,fr17 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1111,0x1111,fr14 + set_fr_iimmed 0x2222,0x2222,fr15 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + cmqsubhss fr10,fr12,fr14,cc3,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + cmqsubhss fr10,fr12,fr14,cc3,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0xffff,0xffff,fr12 + set_fr_iimmed 0xfffe,0xffff,fr13 + cmqsubhss fr10,fr12,fr14,cc3,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8001,0x8001,fr11 + set_fr_iimmed 0x0001,0x0002,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqsubhss fr10,fr12,fr14,cc7,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x3333,0x3333,fr16 + set_fr_iimmed 0x4444,0x4444,fr17 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + set_fr_iimmed 0x8000,0x8000,fr12 + set_fr_iimmed 0x8000,0x8000,fr13 + cmqsubhss.p fr10,fr10,fr14,cc7,1 + cmqsubhss fr12,fr10,fr16,cc7,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_fr_limmed 0x3333,0x3333,fr16 + test_fr_limmed 0x4444,0x4444,fr17 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + pass diff --git a/sim/testsuite/sim/frv/fr500/cmqsubhus.cgs b/sim/testsuite/sim/frv/fr500/cmqsubhus.cgs new file mode 100644 index 0000000..f60ae98 --- /dev/null +++ b/sim/testsuite/sim/frv/fr500/cmqsubhus.cgs @@ -0,0 +1,370 @@ +# frv testcase for cmqsubhus $FRi,$FRj,$FRj,$CCi,$cond +# mach: frv fr500 + + .include "../testutils.inc" + + start + + .global cmqsubhus +cmqsubhus: + set_spr_immed 0x1b1b,cccr + + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0xbeef,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0x0000,fr13 + cmqsubhus fr10,fr12,fr14,cc0,1 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0xdead,0xbeef,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0x1111,0x1111,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqsubhus fr10,fr12,fr14,cc0,1 + test_fr_limmed 0x0123,0x4567,fr14 + test_fr_limmed 0x7ffc,0x7ffd,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0001,0x0001,fr11 + set_fr_iimmed 0x0001,0x0002,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqsubhus fr10,fr12,fr14,cc4,1 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0x0000,0x0000,fr15 + test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0002,fr11 + set_fr_iimmed 0x0000,0x0001,fr12 + set_fr_iimmed 0x0002,0x0003,fr13 + cmqsubhus.p fr10,fr10,fr14,cc4,1 + cmqsubhus fr10,fr12,fr16,cc4,1 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0x0000,0x0000,fr15 + test_fr_limmed 0x0001,0x0000,fr16 + test_fr_limmed 0x0000,0x0000,fr17 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 0x3c,2,0x1,msr1 ; msr1.sie is set + test_spr_bits 2,1,1,msr1 ; msr1.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0xbeef,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0x0000,fr13 + cmqsubhus fr10,fr12,fr14,cc1,0 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0xdead,0xbeef,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0x1111,0x1111,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqsubhus fr10,fr12,fr14,cc1,0 + test_fr_limmed 0x0123,0x4567,fr14 + test_fr_limmed 0x7ffc,0x7ffd,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0001,0x0001,fr11 + set_fr_iimmed 0x0001,0x0002,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqsubhus fr10,fr12,fr14,cc5,0 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0x0000,0x0000,fr15 + test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0002,fr11 + set_fr_iimmed 0x0000,0x0001,fr12 + set_fr_iimmed 0x0002,0x0003,fr13 + cmqsubhus.p fr10,fr10,fr14,cc5,0 + cmqsubhus fr10,fr12,fr16,cc5,0 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0x0000,0x0000,fr15 + test_fr_limmed 0x0001,0x0000,fr16 + test_fr_limmed 0x0000,0x0000,fr17 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 0x3c,2,0x1,msr1 ; msr1.sie is set + test_spr_bits 2,1,1,msr1 ; msr1.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_fr_iimmed 0x1111,0x1111,fr14 + set_fr_iimmed 0x2222,0x2222,fr15 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0xbeef,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0x0000,fr13 + cmqsubhus fr10,fr12,fr14,cc0,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0x1111,0x1111,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqsubhus fr10,fr12,fr14,cc0,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0001,0x0001,fr11 + set_fr_iimmed 0x0001,0x0002,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqsubhus fr10,fr12,fr14,cc4,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x3333,0x3333,fr16 + set_fr_iimmed 0x4444,0x4444,fr17 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0002,fr11 + set_fr_iimmed 0x0000,0x0001,fr12 + set_fr_iimmed 0x0002,0x0003,fr13 + cmqsubhus.p fr10,fr10,fr14,cc4,0 + cmqsubhus fr10,fr12,fr16,cc4,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_fr_limmed 0x3333,0x3333,fr16 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_fr_limmed 0x4444,0x4444,fr17 + + set_fr_iimmed 0x1111,0x1111,fr14 + set_fr_iimmed 0x2222,0x2222,fr15 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0xbeef,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0x0000,fr13 + cmqsubhus fr10,fr12,fr14,cc1,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0x1111,0x1111,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqsubhus fr10,fr12,fr14,cc1,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0001,0x0001,fr11 + set_fr_iimmed 0x0001,0x0002,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqsubhus fr10,fr12,fr14,cc5,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x3333,0x3333,fr16 + set_fr_iimmed 0x4444,0x4444,fr17 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0002,fr11 + set_fr_iimmed 0x0000,0x0001,fr12 + set_fr_iimmed 0x0002,0x0003,fr13 + cmqsubhus.p fr10,fr10,fr14,cc5,1 + cmqsubhus fr10,fr12,fr16,cc5,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_fr_limmed 0x3333,0x3333,fr16 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_fr_limmed 0x4444,0x4444,fr17 + + set_fr_iimmed 0x1111,0x1111,fr14 + set_fr_iimmed 0x2222,0x2222,fr15 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0xbeef,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0x0000,fr13 + cmqsubhus fr10,fr12,fr14,cc2,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0x1111,0x1111,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqsubhus fr10,fr12,fr14,cc2,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0001,0x0001,fr11 + set_fr_iimmed 0x0001,0x0002,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqsubhus fr10,fr12,fr14,cc6,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x3333,0x3333,fr16 + set_fr_iimmed 0x4444,0x4444,fr17 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0002,fr11 + set_fr_iimmed 0x0000,0x0001,fr12 + set_fr_iimmed 0x0002,0x0003,fr13 + cmqsubhus.p fr10,fr10,fr14,cc6,0 + cmqsubhus fr10,fr12,fr16,cc6,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_fr_limmed 0x3333,0x3333,fr16 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_fr_limmed 0x4444,0x4444,fr17 +; + set_fr_iimmed 0x1111,0x1111,fr14 + set_fr_iimmed 0x2222,0x2222,fr15 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0xbeef,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0x0000,fr13 + cmqsubhus fr10,fr12,fr14,cc3,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0x1111,0x1111,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqsubhus fr10,fr12,fr14,cc3,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0001,0x0001,fr11 + set_fr_iimmed 0x0001,0x0002,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqsubhus fr10,fr12,fr14,cc7,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x3333,0x3333,fr16 + set_fr_iimmed 0x4444,0x4444,fr17 + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0002,fr11 + set_fr_iimmed 0x0000,0x0001,fr12 + set_fr_iimmed 0x0002,0x0003,fr13 + cmqsubhus.p fr10,fr10,fr14,cc7,0 + cmqsubhus fr10,fr12,fr16,cc7,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_fr_limmed 0x3333,0x3333,fr16 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 2,1,0,msr1 ; msr1.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_fr_limmed 0x4444,0x4444,fr17 + + pass diff --git a/sim/testsuite/sim/frv/fr500/dcpl.cgs b/sim/testsuite/sim/frv/fr500/dcpl.cgs new file mode 100644 index 0000000..c0c904c --- /dev/null +++ b/sim/testsuite/sim/frv/fr500/dcpl.cgs @@ -0,0 +1,65 @@ +# FRV testcase for dcpl GRi,GRj,lock +# mach: frv fr500 + + .include "../testutils.inc" + + start + + .global dcpl +dcpl: + or_spr_immed 0xc8000000,hsr0 ; caches enabled -- copy-back mode + + ; preload and lock all the lines in set 0 of the data cache + set_gr_immed 0x70000,gr10 + dcpl gr10,gr0,1 + set_mem_immed 0x11111111,gr10 + test_mem_immed 0x11111111,gr10 + + inc_gr_immed 0x1000,gr10 + set_gr_immed 1,gr11 + dcpl gr10,gr11,1 + set_mem_immed 0x22222222,gr10 + test_mem_immed 0x22222222,gr10 + + inc_gr_immed 0x1000,gr10 + set_gr_immed 63,gr11 + dcpl gr10,gr11,1 + set_mem_immed 0x33333333,gr10 + test_mem_immed 0x33333333,gr10 + + inc_gr_immed 0x1000,gr10 + set_gr_immed 64,gr11 + dcpl gr10,gr11,1 + set_mem_immed 0x44444444,gr10 + test_mem_immed 0x44444444,gr10 + + ; Now write to another address which should be in the same set + ; the write should go through to memory, since all the lines in the + ; set are locked + inc_gr_immed 0x1000,gr10 + set_mem_immed 0xdeadbeef,gr10 + test_mem_immed 0xdeadbeef,gr10 + + ; Invalidate the data cache. Only the last value stored should have made + ; it through to memory + set_gr_immed 0x70000,gr10 + invalidate_data_cache gr10 + test_mem_immed 0,gr10 + + inc_gr_immed 0x1000,gr10 + invalidate_data_cache gr10 + test_mem_immed 0,gr10 + + inc_gr_immed 0x1000,gr10 + invalidate_data_cache gr10 + test_mem_immed 0,gr10 + + inc_gr_immed 0x1000,gr10 + invalidate_data_cache gr10 + test_mem_immed 0,gr10 + + inc_gr_immed 0x1000,gr10 + invalidate_data_cache gr10 + test_mem_immed 0xdeadbeef,gr10 + + pass diff --git a/sim/testsuite/sim/frv/fr500/dcul.cgs b/sim/testsuite/sim/frv/fr500/dcul.cgs new file mode 100644 index 0000000..1c5bd93 --- /dev/null +++ b/sim/testsuite/sim/frv/fr500/dcul.cgs @@ -0,0 +1,118 @@ +# FRV testcase for dcul GRi +# mach: frv fr500 + + .include "../testutils.inc" + + start + + .global dcul +dcul: + or_spr_immed 0xc8000000,hsr0 ; caches enabled -- copy-back mode + + ; preload and lock all the lines in set 0 of the data cache + set_gr_immed 0x70000,gr10 + lock_data_cache gr10 + set_mem_immed 0x11111111,gr10 + test_mem_immed 0x11111111,gr10 + + inc_gr_immed 0x1000,gr10 + set_gr_immed 1,gr11 + lock_data_cache gr10 + set_mem_immed 0x22222222,gr10 + test_mem_immed 0x22222222,gr10 + + inc_gr_immed 0x1000,gr10 + set_gr_immed 63,gr11 + lock_data_cache gr10 + set_mem_immed 0x33333333,gr10 + test_mem_immed 0x33333333,gr10 + + inc_gr_immed 0x1000,gr10 + set_gr_immed 64,gr11 + lock_data_cache gr10 + set_mem_immed 0x44444444,gr10 + test_mem_immed 0x44444444,gr10 + + ; Now write to another address which should be in the same set + ; the write should go through to memory, since all the lines in the + ; set are locked + inc_gr_immed 0x1000,gr10 + set_mem_immed 0xdeadbeef,gr10 + test_mem_immed 0xdeadbeef,gr10 + + ; Invalidate the data cache. Only the last value stored should have made + ; it through to memory + set_gr_immed 0x70000,gr10 + invalidate_data_cache gr10 + test_mem_immed 0,gr10 + + inc_gr_immed 0x1000,gr10 + invalidate_data_cache gr10 + test_mem_immed 0,gr10 + + inc_gr_immed 0x1000,gr10 + invalidate_data_cache gr10 + test_mem_immed 0,gr10 + + inc_gr_immed 0x1000,gr10 + invalidate_data_cache gr10 + test_mem_immed 0,gr10 + + inc_gr_immed 0x1000,gr10 + invalidate_data_cache gr10 + test_mem_immed 0xdeadbeef,gr10 + + ; Now preload load and lock all the lines in set 0 of the data cache + ; again + set_gr_immed 0x70000,gr10 + lock_data_cache gr10 + set_mem_immed 0x11111111,gr10 + test_mem_immed 0x11111111,gr10 + + inc_gr_immed 0x1000,gr10 + set_gr_immed 1,gr11 + lock_data_cache gr10 + set_mem_immed 0x22222222,gr10 + test_mem_immed 0x22222222,gr10 + + inc_gr_immed 0x1000,gr10 + set_gr_immed 63,gr11 + lock_data_cache gr10 + set_mem_immed 0x33333333,gr10 + test_mem_immed 0x33333333,gr10 + + inc_gr_immed 0x1000,gr10 + set_gr_immed 64,gr11 + lock_data_cache gr10 + set_mem_immed 0x44444444,gr10 + test_mem_immed 0x44444444,gr10 + + ; unlock one line + set_gr_immed 0x72000,gr10 + dcul gr10 + + ; Now write to another address which should be in the same set. + set_gr_immed 0x75000,gr10 + set_mem_immed 0xbeefdead,gr10 + + ; All of the stored values should be retrievable + + set_gr_immed 0x70000,gr10 + test_mem_immed 0x11111111,gr10 + + inc_gr_immed 0x1000,gr10 + test_mem_immed 0x22222222,gr10 + + inc_gr_immed 0x1000,gr10 + test_mem_immed 0x33333333,gr10 + + inc_gr_immed 0x1000,gr10 + test_mem_immed 0x44444444,gr10 + + inc_gr_immed 0x1000,gr10 + test_mem_immed 0xdeadbeef,gr10 + + inc_gr_immed 0x1000,gr10 + test_mem_immed 0xbeefdead,gr10 + + pass diff --git a/sim/testsuite/sim/frv/fr500/mclracc.cgs b/sim/testsuite/sim/frv/fr500/mclracc.cgs new file mode 100644 index 0000000..43fcf75 --- /dev/null +++ b/sim/testsuite/sim/frv/fr500/mclracc.cgs @@ -0,0 +1,79 @@ +# frv testcase for mclracc $ACC40k,$A +# mach: all + + .include "../testutils.inc" + + start + + .global mclracc +mclracc: + set_accg_immed 0xff,accg0 + set_acc_immed -1,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed -1,acc1 + set_accg_immed 0xff,accg3 + set_acc_immed -1,acc3 + set_accg_immed 0xff,accg7 + set_acc_immed -1,acc7 + + mclracc acc8,0 ; nop + test_accg_immed 0xff,accg0 + test_acc_immed -1,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed -1,acc1 + test_accg_immed 0xff,accg3 + test_acc_immed -1,acc3 + test_accg_immed 0xff,accg7 + test_acc_immed -1,acc7 + + mclracc acc8,1 ; nop + test_accg_immed 0xff,accg0 + test_acc_immed -1,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed -1,acc1 + test_accg_immed 0xff,accg3 + test_acc_immed -1,acc3 + test_accg_immed 0xff,accg7 + test_acc_immed -1,acc7 + + mclracc acc3,0 + test_accg_immed 0xff,accg0 + test_acc_immed -1,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed -1,acc1 + test_accg_immed 0,accg3 + test_acc_immed 0,acc3 + test_accg_immed 0xff,accg7 + test_acc_immed -1,acc7 + + mclracc acc7,1 + test_accg_immed 0xff,accg0 + test_acc_immed -1,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed -1,acc1 + test_accg_immed 0,accg3 + test_acc_immed 0,acc3 + test_accg_immed 0,accg7 + test_acc_immed 0,acc7 + + mclracc acc0,0 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed -1,acc1 + test_accg_immed 0,accg3 + test_acc_immed 0,acc3 + test_accg_immed 0,accg7 + test_acc_immed 0,acc7 + + mclracc acc0,1 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + test_accg_immed 0,accg3 + test_acc_immed 0,acc3 + test_accg_immed 0,accg7 + test_acc_immed 0,acc7 + + pass diff --git a/sim/testsuite/sim/frv/fr500/mqaddhss.cgs b/sim/testsuite/sim/frv/fr500/mqaddhss.cgs new file mode 100644 index 0000000..7183a3f --- /dev/null +++ b/sim/testsuite/sim/frv/fr500/mqaddhss.cgs @@ -0,0 +1,79 @@ +# frv testcase for mqaddhss $FRi,$FRj,$FRj +# mach: frv fr500 + + .include "../testutils.inc" + + start + + .global mqaddhss +mqaddhss: + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + mqaddhss fr10,fr12,fr14 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0xdead,0xbeef,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + mqaddhss fr10,fr12,fr14 + test_fr_limmed 0xbeef,0xdead,fr14 + test_fr_limmed 0x2345,0x6789,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0xffff,0xffff,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + mqaddhss fr10,fr12,fr14 + test_fr_limmed 0x1233,0x5677,fr14 + test_fr_limmed 0x7fff,0x7fff,fr15 + test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8001,0x8001,fr11 + set_fr_iimmed 0xffff,0xfffe,fr12 + set_fr_iimmed 0xfffe,0xfffe,fr13 + mqaddhss fr10,fr12,fr14 + test_fr_limmed 0x8000,0x8000,fr14 + test_fr_limmed 0x8000,0x8000,fr15 + test_spr_bits 0x3c,2,0x7,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + set_fr_iimmed 0x7fff,0x0000,fr12 + set_fr_iimmed 0x0000,0x8000,fr13 + mqaddhss.p fr10,fr10,fr14 + mqaddhss fr12,fr12,fr16 + test_fr_limmed 0x0002,0x0002,fr14 + test_fr_limmed 0xfffe,0xfffe,fr15 + test_fr_limmed 0x7fff,0x0000,fr16 + test_fr_limmed 0x0000,0x8000,fr17 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie not set + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 0x3c,2,0x9,msr1 ; msr1.sie is set + test_spr_bits 2,1,1,msr1 ; msr1.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + pass diff --git a/sim/testsuite/sim/frv/fr500/mqaddhus.cgs b/sim/testsuite/sim/frv/fr500/mqaddhus.cgs new file mode 100644 index 0000000..9faa109 --- /dev/null +++ b/sim/testsuite/sim/frv/fr500/mqaddhus.cgs @@ -0,0 +1,65 @@ +# frv testcase for mqaddhus $FRi,$FRj,$FRj +# mach: frv fr500 + + .include "../testutils.inc" + + start + + .global mqaddhus +mqaddhus: + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + mqaddhus fr10,fr12,fr14 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0xdead,0xbeef,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + mqaddhus fr10,fr12,fr14 + test_fr_limmed 0xbeef,0xdead,fr14 + test_fr_limmed 0x2345,0x6789,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + set_fr_iimmed 0x0002,0x0001,fr12 + set_fr_iimmed 0x0001,0x0002,fr13 + mqaddhus fr10,fr12,fr14 + test_fr_limmed 0x8000,0x7fff,fr14 + test_fr_limmed 0xffff,0xffff,fr15 + test_spr_bits 0x3c,2,1,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0002,0x0001,fr10 + set_fr_iimmed 0x0001,0x0001,fr11 + set_fr_iimmed 0xfffe,0xfffe,fr12 + set_fr_iimmed 0x8000,0x8000,fr13 + mqaddhus.p fr10,fr10,fr14 + mqaddhus fr12,fr12,fr16 + test_fr_limmed 0x0004,0x0002,fr14 + test_fr_limmed 0x0002,0x0002,fr15 + test_fr_limmed 0xffff,0xffff,fr16 + test_fr_limmed 0xffff,0xffff,fr17 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 0x3c,2,0xf,msr1 ; msr1.sie is set + test_spr_bits 2,1,1,msr1 ; msr1.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + pass diff --git a/sim/testsuite/sim/frv/fr500/mqsubhss.cgs b/sim/testsuite/sim/frv/fr500/mqsubhss.cgs new file mode 100644 index 0000000..74d5a87 --- /dev/null +++ b/sim/testsuite/sim/frv/fr500/mqsubhss.cgs @@ -0,0 +1,79 @@ +# frv testcase for mqsubhss $FRi,$FRj,$FRj +# mach: frv fr500 + + .include "../testutils.inc" + + start + + .global msubhss +msubhss: + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + mqsubhss fr10,fr12,fr14 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0xdead,0x4111,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + mqsubhss fr10,fr12,fr14 + test_fr_limmed 0x4111,0xdead,fr14 + test_fr_limmed 0x0123,0x4567,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0xffff,0xffff,fr12 + set_fr_iimmed 0xfffe,0xffff,fr13 + mqsubhss fr10,fr12,fr14 + test_fr_limmed 0x1235,0x5679,fr14 + test_fr_limmed 0x7fff,0x7fff,fr15 + test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8001,0x8001,fr11 + set_fr_iimmed 0x0001,0x0002,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + mqsubhss fr10,fr12,fr14 + test_fr_limmed 0x8000,0x8000,fr14 + test_fr_limmed 0x8000,0x8000,fr15 + test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + set_fr_iimmed 0x8000,0x8000,fr12 + set_fr_iimmed 0x8000,0x8000,fr13 + mqsubhss.p fr10,fr10,fr14 + mqsubhss fr12,fr10,fr16 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0x0000,0x0000,fr15 + test_fr_limmed 0x8000,0x8000,fr16 + test_fr_limmed 0x8001,0x8001,fr17 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 0x3c,2,0xc,msr1 ; msr0.sie is set + test_spr_bits 2,1,1,msr1 ; msr1.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + pass diff --git a/sim/testsuite/sim/frv/fr500/mqsubhus.cgs b/sim/testsuite/sim/frv/fr500/mqsubhus.cgs new file mode 100644 index 0000000..44aa7a9 --- /dev/null +++ b/sim/testsuite/sim/frv/fr500/mqsubhus.cgs @@ -0,0 +1,66 @@ +# frv testcase for msubhus $FRi,$FRj,$FRj +# mach: frv fr500 + + .include "../testutils.inc" + + start + + .global msubhus +msubhus: + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0xbeef,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0x0000,fr13 + mqsubhus fr10,fr12,fr14 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0xdead,0xbeef,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0x1111,0x1111,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + mqsubhus fr10,fr12,fr14 + test_fr_limmed 0x0123,0x4567,fr14 + test_fr_limmed 0x7ffc,0x7ffd,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0001,0x0001,fr11 + set_fr_iimmed 0x0001,0x0002,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + mqsubhus fr10,fr12,fr14 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0x0000,0x0000,fr15 + test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0002,fr11 + set_fr_iimmed 0x0000,0x0001,fr12 + set_fr_iimmed 0x0002,0x0003,fr13 + mqsubhus.p fr10,fr10,fr14 + mqsubhus fr10,fr12,fr16 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0x0000,0x0000,fr15 + test_fr_limmed 0x0001,0x0000,fr16 + test_fr_limmed 0x0000,0x0000,fr17 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 0x3c,2,0x1,msr1 ; msr1.sie is set + test_spr_bits 2,1,1,msr1 ; msr1.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + pass diff --git a/sim/testsuite/sim/frv/fr550/allinsn.exp b/sim/testsuite/sim/frv/fr550/allinsn.exp new file mode 100644 index 0000000..1fe1795 --- /dev/null +++ b/sim/testsuite/sim/frv/fr550/allinsn.exp @@ -0,0 +1,19 @@ +# FRV simulator testsuite. + +if [istarget frv*-*] { + # load support procs (none yet) + # load_lib cgen.exp + # all machines + set all_machs "fr550" + set cpu_option -mcpu + + # The .cgs suffix is for "cgen .s". + foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.cgs]] { + # If we're only testing specific files and this isn't one of them, + # skip it. + if ![runtest_file_p $runtests $src] { + continue + } + run_sim_test $src $all_machs + } +} diff --git a/sim/testsuite/sim/frv/fr550/cmaddhss.cgs b/sim/testsuite/sim/frv/fr550/cmaddhss.cgs new file mode 100644 index 0000000..174a3dc --- /dev/null +++ b/sim/testsuite/sim/frv/fr550/cmaddhss.cgs @@ -0,0 +1,547 @@ +# frv testcase for cmaddhss $FRi,$FRj,$FRj,$CCi,$cond +# mach: all + + .include "../testutils.inc" + + start + + .global maddhss +maddhss: + set_spr_immed 0x1b1b,cccr + + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmaddhss fr10,fr11,fr12,cc0,1 + test_fr_limmed 0x0000,0x0000,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + cmaddhss fr10,fr11,fr12,cc0,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + cmaddhss fr10,fr11,fr12,cc0,1 + test_fr_limmed 0xbeef,0xdead,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmaddhss fr10,fr11,fr12,cc0,1 + test_fr_limmed 0x2345,0x6789,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + cmaddhss fr10,fr11,fr12,cc0,1 + test_fr_limmed 0x1233,0x5677,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmaddhss fr10,fr11,fr12,cc4,1 + test_fr_limmed 0x7fff,0x7fff,fr12 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xffff,0xfffe,fr11 + cmaddhss fr10,fr11,fr12,cc4,1 + test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set + test_fr_limmed 0x8000,0x8000,fr12 + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + cmaddhss fr10,fr11,fr12,cc4,1 + test_fr_limmed 0x8000,0x8000,fr12 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmaddhss.p fr10,fr10,fr12,cc4,1 + cmaddhss fr11,fr11,fr13,cc4,1 + test_fr_limmed 0x0002,0x0002,fr12 + test_fr_limmed 0x7fff,0x7fff,fr13 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmaddhss fr10,fr11,fr12,cc1,0 + test_fr_limmed 0x0000,0x0000,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + cmaddhss fr10,fr11,fr12,cc1,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + cmaddhss fr10,fr11,fr12,cc1,0 + test_fr_limmed 0xbeef,0xdead,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmaddhss fr10,fr11,fr12,cc1,0 + test_fr_limmed 0x2345,0x6789,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + cmaddhss fr10,fr11,fr12,cc1,0 + test_fr_limmed 0x1233,0x5677,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmaddhss fr10,fr11,fr12,cc5,0 + test_fr_limmed 0x7fff,0x7fff,fr12 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xffff,0xfffe,fr11 + cmaddhss fr10,fr11,fr12,cc5,0 + test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set + test_fr_limmed 0x8000,0x8000,fr12 + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + cmaddhss fr10,fr11,fr12,cc5,0 + test_fr_limmed 0x8000,0x8000,fr12 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmaddhss.p fr10,fr10,fr12,cc5,0 + cmaddhss fr11,fr11,fr13,cc5,0 + test_fr_limmed 0x0002,0x0002,fr12 + test_fr_limmed 0x7fff,0x7fff,fr13 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_fr_iimmed 0xdead,0xbeef,fr12 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmaddhss fr10,fr11,fr12,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + cmaddhss fr10,fr11,fr12,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + cmaddhss fr10,fr11,fr12,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmaddhss fr10,fr11,fr12,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + cmaddhss fr10,fr11,fr12,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmaddhss fr10,fr11,fr12,cc4,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xffff,0xfffe,fr11 + cmaddhss fr10,fr11,fr12,cc4,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + cmaddhss fr10,fr11,fr12,cc4,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xbeef,0xdead,fr13 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmaddhss.p fr10,fr10,fr12,cc4,0 + cmaddhss fr11,fr11,fr13,cc4,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_fr_limmed 0xbeef,0xdead,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xdead,0xbeef,fr12 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmaddhss fr10,fr11,fr12,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + cmaddhss fr10,fr11,fr12,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + cmaddhss fr10,fr11,fr12,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmaddhss fr10,fr11,fr12,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + cmaddhss fr10,fr11,fr12,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmaddhss fr10,fr11,fr12,cc5,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xffff,0xfffe,fr11 + cmaddhss fr10,fr11,fr12,cc5,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + cmaddhss fr10,fr11,fr12,cc5,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xbeef,0xdead,fr13 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmaddhss.p fr10,fr10,fr12,cc5,1 + cmaddhss fr11,fr11,fr13,cc5,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_fr_limmed 0xbeef,0xdead,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xdead,0xbeef,fr12 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmaddhss fr10,fr11,fr12,cc2,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + cmaddhss fr10,fr11,fr12,cc2,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + cmaddhss fr10,fr11,fr12,cc2,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmaddhss fr10,fr11,fr12,cc2,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + cmaddhss fr10,fr11,fr12,cc2,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmaddhss fr10,fr11,fr12,cc6,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xffff,0xfffe,fr11 + cmaddhss fr10,fr11,fr12,cc6,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + cmaddhss fr10,fr11,fr12,cc6,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xbeef,0xdead,fr13 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmaddhss.p fr10,fr10,fr12,cc6,1 + cmaddhss fr11,fr11,fr13,cc6,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_fr_limmed 0xbeef,0xdead,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set +; + set_fr_iimmed 0xdead,0xbeef,fr12 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmaddhss fr10,fr11,fr12,cc3,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + cmaddhss fr10,fr11,fr12,cc3,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + cmaddhss fr10,fr11,fr12,cc3,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmaddhss fr10,fr11,fr12,cc3,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + cmaddhss fr10,fr11,fr12,cc3,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmaddhss fr10,fr11,fr12,cc7,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xffff,0xfffe,fr11 + cmaddhss fr10,fr11,fr12,cc7,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + cmaddhss fr10,fr11,fr12,cc7,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xbeef,0xdead,fr13 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmaddhss.p fr10,fr10,fr12,cc7,1 + cmaddhss fr11,fr11,fr13,cc7,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_fr_limmed 0xbeef,0xdead,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + pass diff --git a/sim/testsuite/sim/frv/fr550/cmaddhus.cgs b/sim/testsuite/sim/frv/fr550/cmaddhus.cgs new file mode 100644 index 0000000..40e1152 --- /dev/null +++ b/sim/testsuite/sim/frv/fr550/cmaddhus.cgs @@ -0,0 +1,481 @@ +# frv testcase for cmaddhus $FRi,$FRj,$FRj,$CCi,$cond +# mach: all + + .include "../testutils.inc" + + start + + .global cmaddhus +cmaddhus: + set_spr_immed 0x1b1b,cccr + + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmaddhus fr10,fr11,fr12,cc0,1 + test_fr_limmed 0x0000,0x0000,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + cmaddhus fr10,fr11,fr12,cc0,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + cmaddhus fr10,fr11,fr12,cc0,1 + test_fr_limmed 0xbeef,0xdead,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmaddhus fr10,fr11,fr12,cc0,1 + test_fr_limmed 0x2345,0x6789,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmaddhus fr10,fr11,fr12,cc4,1 + test_fr_limmed 0x8000,0x7fff,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xfffe,0xfffe,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + cmaddhus fr10,fr11,fr12,cc4,1 + test_fr_limmed 0xffff,0xffff,fr12 + test_spr_bits 0x3c,2,4,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0002,0x0001,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + cmaddhus fr10,fr11,fr12,cc4,1 + test_fr_limmed 0xffff,0xffff,fr12 + test_spr_bits 0x3c,2,8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + cmaddhus.p fr10,fr10,fr12,cc4,1 + cmaddhus fr11,fr11,fr13,cc4,1 + test_fr_limmed 0x0002,0x0002,fr12 + test_fr_limmed 0xffff,0xffff,fr13 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmaddhus fr10,fr11,fr12,cc1,0 + test_fr_limmed 0x0000,0x0000,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + cmaddhus fr10,fr11,fr12,cc1,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + cmaddhus fr10,fr11,fr12,cc1,0 + test_fr_limmed 0xbeef,0xdead,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmaddhus fr10,fr11,fr12,cc1,0 + test_fr_limmed 0x2345,0x6789,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmaddhus fr10,fr11,fr12,cc5,0 + test_fr_limmed 0x8000,0x7fff,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xfffe,0xfffe,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + cmaddhus fr10,fr11,fr12,cc5,0 + test_fr_limmed 0xffff,0xffff,fr12 + test_spr_bits 0x3c,2,4,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0002,0x0001,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + cmaddhus fr10,fr11,fr12,cc5,0 + test_fr_limmed 0xffff,0xffff,fr12 + test_spr_bits 0x3c,2,8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + cmaddhus.p fr10,fr10,fr12,cc5,0 + cmaddhus fr11,fr11,fr13,cc5,0 + test_fr_limmed 0x0002,0x0002,fr12 + test_fr_limmed 0xffff,0xffff,fr13 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_fr_iimmed 0xdead,0xbeef,fr12 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmaddhus fr10,fr11,fr12,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xbeef,0x0000,fr10 + set_fr_iimmed 0x0000,0xdead,fr11 + cmaddhus fr10,fr11,fr12,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + cmaddhus fr10,fr11,fr12,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmaddhus fr10,fr11,fr12,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmaddhus fr10,fr11,fr12,cc4,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xfffe,0xfffe,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + cmaddhus fr10,fr11,fr12,cc4,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0002,0x0001,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + cmaddhus fr10,fr11,fr12,cc4,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xbeef,0xdead,fr13 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + cmaddhus.p fr10,fr10,fr12,cc4,0 + cmaddhus fr11,fr11,fr13,cc4,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_fr_limmed 0xbeef,0xdead,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xdead,0xbeef,fr12 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmaddhus fr10,fr11,fr12,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xbeef,0x0000,fr10 + set_fr_iimmed 0x0000,0xdead,fr11 + cmaddhus fr10,fr11,fr12,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + cmaddhus fr10,fr11,fr12,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmaddhus fr10,fr11,fr12,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmaddhus fr10,fr11,fr12,cc5,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xfffe,0xfffe,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + cmaddhus fr10,fr11,fr12,cc5,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0002,0x0001,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + cmaddhus fr10,fr11,fr12,cc5,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xbeef,0xdead,fr13 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + cmaddhus.p fr10,fr10,fr12,cc5,1 + cmaddhus fr11,fr11,fr13,cc5,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_fr_limmed 0xbeef,0xdead,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xdead,0xbeef,fr12 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmaddhus fr10,fr11,fr12,cc2,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xbeef,0x0000,fr10 + set_fr_iimmed 0x0000,0xdead,fr11 + cmaddhus fr10,fr11,fr12,cc2,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + cmaddhus fr10,fr11,fr12,cc2,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmaddhus fr10,fr11,fr12,cc2,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmaddhus fr10,fr11,fr12,cc6,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xfffe,0xfffe,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + cmaddhus fr10,fr11,fr12,cc6,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0002,0x0001,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + cmaddhus fr10,fr11,fr12,cc6,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xbeef,0xdead,fr13 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + cmaddhus.p fr10,fr10,fr12,cc6,0 + cmaddhus fr11,fr11,fr13,cc6,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_fr_limmed 0xbeef,0xdead,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xdead,0xbeef,fr12 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmaddhus fr10,fr11,fr12,cc3,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xbeef,0x0000,fr10 + set_fr_iimmed 0x0000,0xdead,fr11 + cmaddhus fr10,fr11,fr12,cc3,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + cmaddhus fr10,fr11,fr12,cc3,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmaddhus fr10,fr11,fr12,cc3,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmaddhus fr10,fr11,fr12,cc7,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xfffe,0xfffe,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + cmaddhus fr10,fr11,fr12,cc7,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0002,0x0001,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + cmaddhus fr10,fr11,fr12,cc7,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xbeef,0xdead,fr13 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + cmaddhus.p fr10,fr10,fr12,cc7,0 + cmaddhus fr11,fr11,fr13,cc7,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_fr_limmed 0xbeef,0xdead,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + pass diff --git a/sim/testsuite/sim/frv/fr550/cmcpxiu.cgs b/sim/testsuite/sim/frv/fr550/cmcpxiu.cgs new file mode 100644 index 0000000..341949b --- /dev/null +++ b/sim/testsuite/sim/frv/fr550/cmcpxiu.cgs @@ -0,0 +1,492 @@ +# frv testcase for cmcpxiu $GRi,$GRj,$GRk,$CCi,$cond +# mach: all + + .include "../testutils.inc" + + start + + .global cmcpxiu +cmcpxiu: + set_spr_immed 0x1b1b,cccr + + set_fr_iimmed 4,2,fr7 ; multiply small numbers + set_fr_iimmed 3,5,fr8 + cmcpxiu fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_immed 26,acc0 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 1,3,fr8 + cmcpxiu fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_immed 5,acc0 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 0,2,fr8 + cmcpxiu fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + + set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result + set_fr_iimmed 0x0001,2,fr8 + cmcpxiu fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x7fff,acc0 + + set_fr_iimmed 0x4000,1,fr7 ; 16 bit result + set_fr_iimmed 0x0001,2,fr8 + cmcpxiu fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8001,acc0 + + set_fr_iimmed 0x4000,1,fr7 ; 17 bit result + set_fr_iimmed 0x0001,4,fr8 + cmcpxiu fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_immed 0x00010001,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxiu fr7,fr8,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x0000,0x8000,fr8 + cmcpxiu fr7,fr8,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_limmed 0x4000,0x0000,acc0 + + set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_limmed 0xfffe,0x0001,acc0 + + set_fr_iimmed 0xfffe,0xffff,fr7 ; almost max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc4,1 + test_accg_immed 1,accg0 + test_acc_immed 0xfffb0003,acc0 + + set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc4,1 + test_accg_immed 1,accg0 + test_acc_immed 0xfffc0002,acc0 + + set_fr_iimmed 4,2,fr7 ; multiply small numbers + set_fr_iimmed 3,5,fr8 + cmcpxiu fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_immed 26,acc0 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 1,3,fr8 + cmcpxiu fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_immed 5,acc0 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 0,2,fr8 + cmcpxiu fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + + set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result + set_fr_iimmed 0x0001,2,fr8 + cmcpxiu fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x7fff,acc0 + + set_fr_iimmed 0x4000,1,fr7 ; 16 bit result + set_fr_iimmed 0x0001,2,fr8 + cmcpxiu fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8001,acc0 + + set_fr_iimmed 0x4000,1,fr7 ; 17 bit result + set_fr_iimmed 0x0001,4,fr8 + cmcpxiu fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_immed 0x00010001,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxiu fr7,fr8,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x0000,0x8000,fr8 + cmcpxiu fr7,fr8,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_limmed 0x4000,0x0000,acc0 + + set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_limmed 0xfffe,0x0001,acc0 + + set_fr_iimmed 0xfffe,0xffff,fr7 ; almost max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc5,0 + test_accg_immed 1,accg0 + test_acc_immed 0xfffb0003,acc0 + + set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc5,0 + test_accg_immed 1,accg0 + test_acc_immed 0xfffc0002,acc0 + + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_fr_iimmed 4,2,fr7 ; multiply small numbers + set_fr_iimmed 3,5,fr8 + cmcpxiu fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 1,3,fr8 + cmcpxiu fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 0,2,fr8 + cmcpxiu fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result + set_fr_iimmed 0x0001,2,fr8 + cmcpxiu fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,1,fr7 ; 16 bit result + set_fr_iimmed 0x0001,4,fr8 + cmcpxiu fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,1,fr7 ; 17 bit result + set_fr_iimmed 0x0001,4,fr8 + cmcpxiu fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxiu fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x0000,0x8000,fr8 + cmcpxiu fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0000,0x0001,fr7 ; saturation + set_fr_iimmed 0x0001,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x0000,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_fr_iimmed 4,2,fr7 ; multiply small numbers + set_fr_iimmed 3,5,fr8 + cmcpxiu fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 1,3,fr8 + cmcpxiu fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 0,2,fr8 + cmcpxiu fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result + set_fr_iimmed 0x0001,2,fr8 + cmcpxiu fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,1,fr7 ; 16 bit result + set_fr_iimmed 0x0001,4,fr8 + cmcpxiu fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,1,fr7 ; 17 bit result + set_fr_iimmed 0x0001,4,fr8 + cmcpxiu fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxiu fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x0000,0x8000,fr8 + cmcpxiu fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0000,0x0001,fr7 ; saturation + set_fr_iimmed 0x0001,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x0000,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_fr_iimmed 4,2,fr7 ; multiply small numbers + set_fr_iimmed 3,5,fr8 + cmcpxiu fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 1,3,fr8 + cmcpxiu fr7,fr8,acc0,cc2,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 0,2,fr8 + cmcpxiu fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result + set_fr_iimmed 0x0001,2,fr8 + cmcpxiu fr7,fr8,acc0,cc2,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,1,fr7 ; 16 bit result + set_fr_iimmed 0x0001,4,fr8 + cmcpxiu fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,1,fr7 ; 17 bit result + set_fr_iimmed 0x0001,4,fr8 + cmcpxiu fr7,fr8,acc0,cc2,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxiu fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x0000,0x8000,fr8 + cmcpxiu fr7,fr8,acc0,cc6,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0000,0x0001,fr7 ; saturation + set_fr_iimmed 0x0001,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc6,0 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x0000,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc6,1 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc6,0 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_fr_iimmed 4,2,fr7 ; multiply small numbers + set_fr_iimmed 3,5,fr8 + cmcpxiu fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 1,3,fr8 + cmcpxiu fr7,fr8,acc0,cc3,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 0,2,fr8 + cmcpxiu fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result + set_fr_iimmed 0x0001,2,fr8 + cmcpxiu fr7,fr8,acc0,cc3,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,1,fr7 ; 16 bit result + set_fr_iimmed 0x0001,4,fr8 + cmcpxiu fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,1,fr7 ; 17 bit result + set_fr_iimmed 0x0001,4,fr8 + cmcpxiu fr7,fr8,acc0,cc3,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxiu fr7,fr8,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x0000,0x8000,fr8 + cmcpxiu fr7,fr8,acc0,cc7,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0000,0x0001,fr7 ; saturation + set_fr_iimmed 0x0001,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc7,0 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x0000,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc7,1 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxiu fr7,fr8,acc0,cc7,0 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is clear + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + pass diff --git a/sim/testsuite/sim/frv/fr550/cmcpxru.cgs b/sim/testsuite/sim/frv/fr550/cmcpxru.cgs new file mode 100644 index 0000000..3eeb0a0 --- /dev/null +++ b/sim/testsuite/sim/frv/fr550/cmcpxru.cgs @@ -0,0 +1,528 @@ +# frv testcase for cmcpxru $GRi,$GRj,$GRk,$CCi,$cond +# mach: all + + .include "../testutils.inc" + + start + + .global cmcpxru +cmcpxru: + set_spr_immed 0x1b1b,cccr + + set_fr_iimmed 4,2,fr7 ; multiply small numbers + set_fr_iimmed 5,3,fr8 + cmcpxru fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_immed 14,acc0 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 3,1,fr8 + cmcpxru fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_immed 1,acc0 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmcpxru fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + + set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result + set_fr_iimmed 2,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x7ffd,acc0 + + set_fr_iimmed 0x4000,1,fr7 ; 16 bit result + set_fr_iimmed 4,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0xffff,acc0 + + set_fr_iimmed 0x8000,1,fr7 ; 17 bit result + set_fr_iimmed 4,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc0,1 + test_accg_immed 0,accg0 + test_acc_immed 0x0001ffff,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxru fr7,fr8,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x0000,fr8 + cmcpxru fr7,fr8,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_limmed 0x4000,0x0000,acc0 + + set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxru fr7,fr8,acc0,cc4,1 + test_accg_immed 0,accg0 + test_acc_limmed 0xfffe,0x0001,acc0 + + set_fr_iimmed 0x0000,0x0001,fr7 ; saturation + set_fr_iimmed 0xffff,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc4,1 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + + set_fr_iimmed 0x0000,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxru fr7,fr8,acc0,cc4,1 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + + set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxru fr7,fr8,acc0,cc4,1 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + + set_fr_iimmed 4,2,fr7 ; multiply small numbers + set_fr_iimmed 5,3,fr8 + cmcpxru fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_immed 14,acc0 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 3,1,fr8 + cmcpxru fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_immed 1,acc0 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmcpxru fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + + set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result + set_fr_iimmed 2,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x7ffd,acc0 + + set_fr_iimmed 0x4000,1,fr7 ; 16 bit result + set_fr_iimmed 4,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0xffff,acc0 + + set_fr_iimmed 0x8000,1,fr7 ; 17 bit result + set_fr_iimmed 4,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc1,0 + test_accg_immed 0,accg0 + test_acc_immed 0x0001ffff,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxru fr7,fr8,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x0000,fr8 + cmcpxru fr7,fr8,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_limmed 0x4000,0x0000,acc0 + + set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxru fr7,fr8,acc0,cc5,0 + test_accg_immed 0,accg0 + test_acc_limmed 0xfffe,0x0001,acc0 + + set_fr_iimmed 0x0000,0x0001,fr7 ; saturation + set_fr_iimmed 0xffff,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc5,0 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + + set_fr_iimmed 0x0000,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxru fr7,fr8,acc0,cc5,0 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + + set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxru fr7,fr8,acc0,cc5,0 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + + set_spr_immed 0,msr0 + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_fr_iimmed 4,2,fr7 ; multiply small numbers + set_fr_iimmed 5,3,fr8 + cmcpxru fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 3,1,fr8 + cmcpxru fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmcpxru fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result + set_fr_iimmed 2,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,1,fr7 ; 16 bit result + set_fr_iimmed 4,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,1,fr7 ; 17 bit result + set_fr_iimmed 4,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc0,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxru fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x0000,fr8 + cmcpxru fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxru fr7,fr8,acc0,cc4,0 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x0000,0x0001,fr7 ; saturation + set_fr_iimmed 0xffff,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x0000,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxru fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxru fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_spr_immed 0,msr0 + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_fr_iimmed 4,2,fr7 ; multiply small numbers + set_fr_iimmed 5,3,fr8 + cmcpxru fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 3,1,fr8 + cmcpxru fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmcpxru fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result + set_fr_iimmed 2,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,1,fr7 ; 16 bit result + set_fr_iimmed 4,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,1,fr7 ; 17 bit result + set_fr_iimmed 4,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc1,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxru fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x0000,fr8 + cmcpxru fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxru fr7,fr8,acc0,cc5,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x0000,0x0001,fr7 ; saturation + set_fr_iimmed 0xffff,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x0000,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxru fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxru fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_spr_immed 0,msr0 + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_fr_iimmed 4,2,fr7 ; multiply small numbers + set_fr_iimmed 5,3,fr8 + cmcpxru fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 3,1,fr8 + cmcpxru fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmcpxru fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result + set_fr_iimmed 2,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,1,fr7 ; 16 bit result + set_fr_iimmed 4,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,1,fr7 ; 17 bit result + set_fr_iimmed 4,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc2,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxru fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x0000,fr8 + cmcpxru fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxru fr7,fr8,acc0,cc6,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x0000,0x0001,fr7 ; saturation + set_fr_iimmed 0xffff,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc6,1 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x0000,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxru fr7,fr8,acc0,cc6,1 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxru fr7,fr8,acc0,cc6,1 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 +; + set_spr_immed 0,msr0 + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_fr_iimmed 4,2,fr7 ; multiply small numbers + set_fr_iimmed 5,3,fr8 + cmcpxru fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 3,1,fr8 + cmcpxru fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmcpxru fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result + set_fr_iimmed 2,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x4000,1,fr7 ; 16 bit result + set_fr_iimmed 4,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,1,fr7 ; 17 bit result + set_fr_iimmed 4,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc3,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmcpxru fr7,fr8,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x0000,fr8 + cmcpxru fr7,fr8,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxru fr7,fr8,acc0,cc7,1 + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x0000,0x0001,fr7 ; saturation + set_fr_iimmed 0xffff,0x0001,fr8 + cmcpxru fr7,fr8,acc0,cc7,1 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0x0000,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxru fr7,fr8,acc0,cc7,1 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + cmcpxru fr7,fr8,acc0,cc7,1 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + + pass diff --git a/sim/testsuite/sim/frv/fr550/cmmachs.cgs b/sim/testsuite/sim/frv/fr550/cmmachs.cgs new file mode 100644 index 0000000..f716867 --- /dev/null +++ b/sim/testsuite/sim/frv/fr550/cmmachs.cgs @@ -0,0 +1,1545 @@ +# frv testcase for cmmachs $GRi,$GRj,$ACCk,$CCi,$cond +# mach: all + + .include "../testutils.inc" + + start + + .global cmmachs +cmmachs: + set_spr_immed 0x1b1b,cccr + + ; Positive operands + set_spr_immed 0x0,msr0 + set_accg_immed 0x0,accg0 + set_acc_immed 0x0,acc0 + set_accg_immed 0x0,accg1 + set_acc_immed 0x0,acc1 + set_fr_iimmed 2,3,fr7 ; multiply small numbers + set_fr_iimmed 3,2,fr8 + cmmachs fr7,fr8,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + + set_fr_iimmed 0,1,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmachs fr7,fr8,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,2,fr8 + cmmachs fr7,fr8,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 8,acc0 + test_accg_immed 0,accg1 + test_acc_immed 8,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmachs fr7,fr8,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0,0x8006,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0,0x8006,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmachs fr7,fr8,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x0001,0x0006,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0001,0x0006,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x4000,0x0007,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x4000,0x0007,acc1 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr8 + cmmachs fr7,fr8,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x4000,0x0001,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x4000,0x0001,acc1 + + set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr8 + cmmachs fr7,fr8,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0xffff,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0xffff,acc1 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr8 + cmmachs fr7,fr8,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0xffff,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0xffff,acc1 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr8 + cmmachs fr7,fr8,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0xbffd,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0xbffd,acc1 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr8 + cmmachs fr7,fr8,acc0,cc4,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0x3ffd,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0x3ffd,acc1 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc4,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xbffd,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xbffd,acc1 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr8 + cmmachs fr7,fr8,acc0,cc4,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xc003,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xc003,acc1 + + set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr8 + cmmachs fr7,fr8,acc0,cc4,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xc005,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xc005,acc1 + + set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr8 + cmmachs fr7,fr8,acc0,cc4,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0x3ffec006,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3ffec006,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmachs fr7,fr8,acc0,cc4,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0x7ffec006,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x7ffec006,acc1 + + set_accg_immed 0x7f,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0x7f,accg1 + set_acc_immed 0xffffffff,acc1 + set_fr_iimmed 1,1,fr7 + set_fr_iimmed 1,1,fr8 + cmmachs fr7,fr8,acc0,cc4,1 +;;;;;;;;;;;; + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc4,1 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + + set_accg_immed -128,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed -128,accg1 + set_acc_immed 0,acc1 + set_fr_iimmed 0xffff,0,fr7 + set_fr_iimmed 1,0xffff,fr8 + cmmachs fr7,fr8,acc0,cc4,1 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x80,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x0000,0x8000,fr7 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc4,1 + test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x80,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + + ; Positive operands + set_spr_immed 0x0,msr0 + set_accg_immed 0x0,accg0 ; saturation + set_acc_immed 0x0,acc0 + set_accg_immed 0x0,accg1 + set_acc_immed 0x0,acc1 + set_fr_iimmed 2,3,fr7 ; multiply small numbers + set_fr_iimmed 3,2,fr8 + cmmachs fr7,fr8,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + + set_fr_iimmed 0,1,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmachs fr7,fr8,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,2,fr8 + cmmachs fr7,fr8,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 8,acc0 + test_accg_immed 0,accg1 + test_acc_immed 8,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmachs fr7,fr8,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0,0x8006,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0,0x8006,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmachs fr7,fr8,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x0001,0x0006,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0001,0x0006,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x4000,0x0007,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x4000,0x0007,acc1 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr8 + cmmachs fr7,fr8,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x4000,0x0001,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x4000,0x0001,acc1 + + set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr8 + cmmachs fr7,fr8,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0xffff,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0xffff,acc1 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr8 + cmmachs fr7,fr8,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0xffff,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0xffff,acc1 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr8 + cmmachs fr7,fr8,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0xbffd,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0xbffd,acc1 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr8 + cmmachs fr7,fr8,acc0,cc5,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0x3ffd,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0x3ffd,acc1 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc5,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xbffd,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xbffd,acc1 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr8 + cmmachs fr7,fr8,acc0,cc5,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xc003,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xc003,acc1 + + set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr8 + cmmachs fr7,fr8,acc0,cc5,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xc005,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xc005,acc1 + + set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr8 + cmmachs fr7,fr8,acc0,cc5,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0x3ffec006,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3ffec006,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmachs fr7,fr8,acc0,cc5,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0x7ffec006,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x7ffec006,acc1 + + set_accg_immed 0x7f,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0x7f,accg1 + set_acc_immed 0xffffffff,acc1 + set_fr_iimmed 1,1,fr7 + set_fr_iimmed 1,1,fr8 + cmmachs fr7,fr8,acc0,cc5,0 + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc5,0 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + + set_accg_immed 0x80,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed 0x80,accg1 + set_acc_immed 0,acc1 + set_fr_iimmed 0xffff,0,fr7 + set_fr_iimmed 1,0xffff,fr8 + cmmachs fr7,fr8,acc0,cc5,0 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x80,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x0000,0x8000,fr7 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc5,0 + test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x80,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + + ; Positive operands + set_spr_immed 0x0,msr0 + set_accg_immed 0x0,accg0 + set_acc_immed 0x0,acc0 + set_accg_immed 0x0,accg1 + set_acc_immed 0x0,acc1 + set_fr_iimmed 2,3,fr7 ; multiply small numbers + set_fr_iimmed 3,2,fr8 + cmmachs fr7,fr8,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0,1,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmachs fr7,fr8,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,2,fr8 + cmmachs fr7,fr8,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmachs fr7,fr8,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmachs fr7,fr8,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr8 + cmmachs fr7,fr8,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr8 + cmmachs fr7,fr8,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr8 + cmmachs fr7,fr8,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr8 + cmmachs fr7,fr8,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr8 + cmmachs fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr8 + cmmachs fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr8 + cmmachs fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr8 + cmmachs fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmachs fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_accg_immed 0x7f,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0x7f,accg1 + set_acc_immed 0xffffffff,acc1 + set_fr_iimmed 1,1,fr7 + set_fr_iimmed 1,1,fr8 + cmmachs fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x7f,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_immed 0xffffffff,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x7f,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_immed 0xffffffff,acc1 + + set_accg_immed 0x80,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed 0x80,accg1 + set_acc_immed 0,acc1 + set_fr_iimmed 0xffff,0,fr7 + set_fr_iimmed 1,0xffff,fr8 + cmmachs fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x80,accg0 ; saturation + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x0000,0x8000,fr7 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x80,accg0 ; saturation + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + + ; Positive operands + set_spr_immed 0x0,msr0 + set_accg_immed 0x0,accg0 + set_acc_immed 0x0,acc0 + set_accg_immed 0x0,accg1 + set_acc_immed 0x0,acc1 + set_fr_iimmed 2,3,fr7 ; multiply small numbers + set_fr_iimmed 3,2,fr8 + cmmachs fr7,fr8,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0,1,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmachs fr7,fr8,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,2,fr8 + cmmachs fr7,fr8,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmachs fr7,fr8,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmachs fr7,fr8,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr8 + cmmachs fr7,fr8,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr8 + cmmachs fr7,fr8,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr8 + cmmachs fr7,fr8,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr8 + cmmachs fr7,fr8,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr8 + cmmachs fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr8 + cmmachs fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr8 + cmmachs fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr8 + cmmachs fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmachs fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_accg_immed 0x7f,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0x7f,accg1 + set_acc_immed 0xffffffff,acc1 + set_fr_iimmed 1,1,fr7 + set_fr_iimmed 1,1,fr8 + cmmachs fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x7f,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_immed 0xffffffff,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x7f,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_immed 0xffffffff,acc1 + + set_accg_immed 0x80,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed 0x80,accg1 + set_acc_immed 0,acc1 + set_fr_iimmed 0xffff,0,fr7 + set_fr_iimmed 1,0xffff,fr8 + cmmachs fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x80,accg0 ; saturation + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x0000,0x8000,fr7 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x80,accg0 ; saturation + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + + ; Positive operands + set_spr_immed 0x0,msr0 + set_accg_immed 0x0,accg0 + set_acc_immed 0x0,acc0 + set_accg_immed 0x0,accg1 + set_acc_immed 0x0,acc1 + set_fr_iimmed 2,3,fr7 ; multiply small numbers + set_fr_iimmed 3,2,fr8 + cmmachs fr7,fr8,acc0,cc2,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0,1,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmachs fr7,fr8,acc0,cc2,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,2,fr8 + cmmachs fr7,fr8,acc0,cc2,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmachs fr7,fr8,acc0,cc2,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmachs fr7,fr8,acc0,cc2,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc2,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr8 + cmmachs fr7,fr8,acc0,cc2,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr8 + cmmachs fr7,fr8,acc0,cc2,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr8 + cmmachs fr7,fr8,acc0,cc2,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr8 + cmmachs fr7,fr8,acc0,cc2,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr8 + cmmachs fr7,fr8,acc0,cc6,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc6,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr8 + cmmachs fr7,fr8,acc0,cc6,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr8 + cmmachs fr7,fr8,acc0,cc6,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr8 + cmmachs fr7,fr8,acc0,cc6,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmachs fr7,fr8,acc0,cc6,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_accg_immed 0x7f,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0x7f,accg1 + set_acc_immed 0xffffffff,acc1 + set_fr_iimmed 1,1,fr7 + set_fr_iimmed 1,1,fr8 + cmmachs fr7,fr8,acc0,cc6,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x7f,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_immed 0xffffffff,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc6,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x7f,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_immed 0xffffffff,acc1 + + set_accg_immed 0x80,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed 0x80,accg1 + set_acc_immed 0,acc1 + set_fr_iimmed 0xffff,0,fr7 + set_fr_iimmed 1,0xffff,fr8 + cmmachs fr7,fr8,acc0,cc6,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x80,accg0 ; saturation + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x0000,0x8000,fr7 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc6,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x80,accg0 ; saturation + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 +; + ; Positive operands + set_spr_immed 0x0,msr0 + set_accg_immed 0x0,accg0 + set_acc_immed 0x0,acc0 + set_accg_immed 0x0,accg1 + set_acc_immed 0x0,acc1 + set_fr_iimmed 2,3,fr7 ; multiply small numbers + set_fr_iimmed 3,2,fr8 + cmmachs fr7,fr8,acc0,cc3,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0,1,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmachs fr7,fr8,acc0,cc3,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,2,fr8 + cmmachs fr7,fr8,acc0,cc3,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmachs fr7,fr8,acc0,cc3,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmachs fr7,fr8,acc0,cc3,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc3,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr8 + cmmachs fr7,fr8,acc0,cc3,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr8 + cmmachs fr7,fr8,acc0,cc3,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr8 + cmmachs fr7,fr8,acc0,cc3,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr8 + cmmachs fr7,fr8,acc0,cc3,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr8 + cmmachs fr7,fr8,acc0,cc7,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc7,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr8 + cmmachs fr7,fr8,acc0,cc7,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr8 + cmmachs fr7,fr8,acc0,cc7,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr8 + cmmachs fr7,fr8,acc0,cc7,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmachs fr7,fr8,acc0,cc7,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_accg_immed 0x7f,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0x7f,accg1 + set_acc_immed 0xffffffff,acc1 + set_fr_iimmed 1,1,fr7 + set_fr_iimmed 1,1,fr8 + cmmachs fr7,fr8,acc0,cc7,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x7f,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_immed 0xffffffff,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc7,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x7f,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_immed 0xffffffff,acc1 + + set_accg_immed 0x80,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed 0x80,accg1 + set_acc_immed 0,acc1 + set_fr_iimmed 0xffff,0,fr7 + set_fr_iimmed 1,0xffff,fr8 + cmmachs fr7,fr8,acc0,cc7,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x80,accg0 ; saturation + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x0000,0x8000,fr7 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachs fr7,fr8,acc0,cc7,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x80,accg0 ; saturation + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + + pass diff --git a/sim/testsuite/sim/frv/fr550/cmmachu.cgs b/sim/testsuite/sim/frv/fr550/cmmachu.cgs new file mode 100644 index 0000000..176d1b1 --- /dev/null +++ b/sim/testsuite/sim/frv/fr550/cmmachu.cgs @@ -0,0 +1,858 @@ +# frv testcase for cmmachu $GRi,$GRj,$GRk,$CCi,$cond +# mach: all + + .include "../testutils.inc" + + start + + .global cmmachu +cmmachu: + set_spr_immed 0x1b1b,cccr + + set_spr_immed 0,msr0 + set_accg_immed 0,accg0 + set_acc_immed 0,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0,acc1 + set_fr_iimmed 3,2,fr7 ; multiply small numbers + set_fr_iimmed 2,3,fr8 + cmmachu fr7,fr8,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 2,1,fr8 + cmmachu fr7,fr8,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 8,acc0 + test_accg_immed 0,accg1 + test_acc_immed 8,acc1 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmachu fr7,fr8,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 8,acc0 + test_accg_immed 0,accg1 + test_acc_immed 8,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmachu fr7,fr8,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8006,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8006,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmachu fr7,fr8,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x0001,0x0006,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0001,0x0006,acc1 + + set_fr_iimmed 0x8000,2,fr7 ; 17 bit result + set_fr_iimmed 2,0x8000,fr8 + cmmachu fr7,fr8,acc0,cc4,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0x00020006,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x00020006,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachu fr7,fr8,acc0,cc4,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0x40010007,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x40010007,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmachu fr7,fr8,acc0,cc4,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x8001,0x0007,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x8001,0x0007,acc1 + + set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmmachu fr7,fr8,acc0,cc4,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 1,accg0 + test_acc_limmed 0x7fff,0x0008,acc0 + test_accg_immed 1,accg1 + test_acc_limmed 0x7fff,0x0008,acc1 + + set_accg_immed 0xff,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xffffffff,acc1 + set_fr_iimmed 1,1,fr7 + set_fr_iimmed 1,1,fr8 + cmmachu fr7,fr8,acc0,cc4,1 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + + set_fr_iimmed 0xffff,0x0000,fr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cmmachu fr7,fr8,acc0,cc4,1 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + + set_spr_immed 0,msr0 + set_accg_immed 0,accg0 + set_acc_immed 0,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0,acc1 + set_fr_iimmed 3,2,fr7 ; multiply small numbers + set_fr_iimmed 2,3,fr8 + cmmachu fr7,fr8,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 2,1,fr8 + cmmachu fr7,fr8,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 8,acc0 + test_accg_immed 0,accg1 + test_acc_immed 8,acc1 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmachu fr7,fr8,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 8,acc0 + test_accg_immed 0,accg1 + test_acc_immed 8,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmachu fr7,fr8,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8006,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8006,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmachu fr7,fr8,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x0001,0x0006,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0001,0x0006,acc1 + + set_fr_iimmed 0x8000,2,fr7 ; 17 bit result + set_fr_iimmed 2,0x8000,fr8 + cmmachu fr7,fr8,acc0,cc5,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0x00020006,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x00020006,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachu fr7,fr8,acc0,cc5,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0x40010007,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x40010007,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmachu fr7,fr8,acc0,cc5,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x8001,0x0007,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x8001,0x0007,acc1 + + set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmmachu fr7,fr8,acc0,cc5,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 1,accg0 + test_acc_limmed 0x7fff,0x0008,acc0 + test_accg_immed 1,accg1 + test_acc_limmed 0x7fff,0x0008,acc1 + + set_accg_immed 0xff,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xffffffff,acc1 + set_fr_iimmed 1,1,fr7 + set_fr_iimmed 1,1,fr8 + cmmachu fr7,fr8,acc0,cc5,0 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + + set_fr_iimmed 0xffff,0x0000,fr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cmmachu fr7,fr8,acc0,cc5,0 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + + set_spr_immed 0,msr0 + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_fr_iimmed 3,2,fr7 ; multiply small numbers + set_fr_iimmed 2,3,fr8 + cmmachu fr7,fr8,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 2,1,fr8 + cmmachu fr7,fr8,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmachu fr7,fr8,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmachu fr7,fr8,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmachu fr7,fr8,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x8000,2,fr7 ; 17 bit result + set_fr_iimmed 2,0x8000,fr8 + cmmachu fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachu fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmachu fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmmachu fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_accg_immed 0xff,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xffffffff,acc1 + set_fr_iimmed 1,1,fr7 + set_fr_iimmed 1,1,fr8 + cmmachu fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0xff,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed 0xffffffff,acc1 + + set_fr_iimmed 0xffff,0x0000,fr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cmmachu fr7,fr8,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0xff,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed 0xffffffff,acc1 + + set_spr_immed 0,msr0 + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_fr_iimmed 3,2,fr7 ; multiply small numbers + set_fr_iimmed 2,3,fr8 + cmmachu fr7,fr8,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 2,1,fr8 + cmmachu fr7,fr8,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmachu fr7,fr8,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmachu fr7,fr8,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmachu fr7,fr8,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x8000,2,fr7 ; 17 bit result + set_fr_iimmed 2,0x8000,fr8 + cmmachu fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachu fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmachu fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmmachu fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_accg_immed 0xff,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xffffffff,acc1 + set_fr_iimmed 1,1,fr7 + set_fr_iimmed 1,1,fr8 + cmmachu fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0xff,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed 0xffffffff,acc1 + + set_fr_iimmed 0xffff,0x0000,fr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cmmachu fr7,fr8,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0xff,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed 0xffffffff,acc1 + + set_spr_immed 0,msr0 + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_fr_iimmed 3,2,fr7 ; multiply small numbers + set_fr_iimmed 2,3,fr8 + cmmachu fr7,fr8,acc0,cc2,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 2,1,fr8 + cmmachu fr7,fr8,acc0,cc2,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmachu fr7,fr8,acc0,cc2,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmachu fr7,fr8,acc0,cc2,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmachu fr7,fr8,acc0,cc2,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x8000,2,fr7 ; 17 bit result + set_fr_iimmed 2,0x8000,fr8 + cmmachu fr7,fr8,acc0,cc6,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachu fr7,fr8,acc0,cc6,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmachu fr7,fr8,acc0,cc6,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmmachu fr7,fr8,acc0,cc6,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_accg_immed 0xff,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xffffffff,acc1 + set_fr_iimmed 1,1,fr7 + set_fr_iimmed 1,1,fr8 + cmmachu fr7,fr8,acc0,cc6,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0xff,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed 0xffffffff,acc1 + + set_fr_iimmed 0xffff,0x0000,fr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cmmachu fr7,fr8,acc0,cc6,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0xff,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed 0xffffffff,acc1 +; + set_spr_immed 0,msr0 + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_fr_iimmed 3,2,fr7 ; multiply small numbers + set_fr_iimmed 2,3,fr8 + cmmachu fr7,fr8,acc0,cc3,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 2,1,fr8 + cmmachu fr7,fr8,acc0,cc3,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + cmmachu fr7,fr8,acc0,cc3,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + cmmachu fr7,fr8,acc0,cc3,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + cmmachu fr7,fr8,acc0,cc3,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x8000,2,fr7 ; 17 bit result + set_fr_iimmed 2,0x8000,fr8 + cmmachu fr7,fr8,acc0,cc7,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + cmmachu fr7,fr8,acc0,cc7,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + cmmachu fr7,fr8,acc0,cc7,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + cmmachu fr7,fr8,acc0,cc7,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + + set_accg_immed 0xff,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xffffffff,acc1 + set_fr_iimmed 1,1,fr7 + set_fr_iimmed 1,1,fr8 + cmmachu fr7,fr8,acc0,cc7,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0xff,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed 0xffffffff,acc1 + + set_fr_iimmed 0xffff,0x0000,fr7 + set_fr_iimmed 0xffff,0xffff,fr8 + cmmachu fr7,fr8,acc0,cc7,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0xff,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed 0xffffffff,acc1 + + pass diff --git a/sim/testsuite/sim/frv/fr550/cmqaddhss.cgs b/sim/testsuite/sim/frv/fr550/cmqaddhss.cgs new file mode 100644 index 0000000..3d32bec --- /dev/null +++ b/sim/testsuite/sim/frv/fr550/cmqaddhss.cgs @@ -0,0 +1,429 @@ +# frv testcase for cmqaddhss $FRi,$FRj,$FRj,$CCi,$cond +# mach: all + + .include "../testutils.inc" + + start + + .global cmqaddhss +cmqaddhss: + set_spr_immed 0x1b1b,cccr + + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + cmqaddhss fr10,fr12,fr14,cc0,1 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0xdead,0xbeef,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + cmqaddhss fr10,fr12,fr14,cc0,1 + test_fr_limmed 0xbeef,0xdead,fr14 + test_fr_limmed 0x2345,0x6789,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0xffff,0xffff,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqaddhss fr10,fr12,fr14,cc0,1 + test_fr_limmed 0x1233,0x5677,fr14 + test_fr_limmed 0x7fff,0x7fff,fr15 + test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8001,0x8001,fr11 + set_fr_iimmed 0xffff,0xfffe,fr12 + set_fr_iimmed 0xfffe,0xfffe,fr13 + cmqaddhss fr10,fr12,fr14,cc4,1 + test_fr_limmed 0x8000,0x8000,fr14 + test_fr_limmed 0x8000,0x8000,fr15 + test_spr_bits 0x3c,2,0x7,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + set_fr_iimmed 0x7fff,0x0000,fr12 + set_fr_iimmed 0x0000,0x8000,fr13 + cmqaddhss.p fr10,fr10,fr14,cc4,1 + cmqaddhss fr12,fr12,fr16,cc4,1 + test_fr_limmed 0x0002,0x0002,fr14 + test_fr_limmed 0xfffe,0xfffe,fr15 + test_fr_limmed 0x7fff,0x0000,fr16 + test_fr_limmed 0x0000,0x8000,fr17 + test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + cmqaddhss fr10,fr12,fr14,cc1,0 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0xdead,0xbeef,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + cmqaddhss fr10,fr12,fr14,cc1,0 + test_fr_limmed 0xbeef,0xdead,fr14 + test_fr_limmed 0x2345,0x6789,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0xffff,0xffff,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqaddhss fr10,fr12,fr14,cc1,0 + test_fr_limmed 0x1233,0x5677,fr14 + test_fr_limmed 0x7fff,0x7fff,fr15 + test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8001,0x8001,fr11 + set_fr_iimmed 0xffff,0xfffe,fr12 + set_fr_iimmed 0xfffe,0xfffe,fr13 + cmqaddhss fr10,fr12,fr14,cc5,0 + test_fr_limmed 0x8000,0x8000,fr14 + test_fr_limmed 0x8000,0x8000,fr15 + test_spr_bits 0x3c,2,0x7,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + set_fr_iimmed 0x7fff,0x0000,fr12 + set_fr_iimmed 0x0000,0x8000,fr13 + cmqaddhss.p fr10,fr10,fr14,cc5,0 + cmqaddhss fr12,fr12,fr16,cc5,0 + test_fr_limmed 0x0002,0x0002,fr14 + test_fr_limmed 0xfffe,0xfffe,fr15 + test_fr_limmed 0x7fff,0x0000,fr16 + test_fr_limmed 0x0000,0x8000,fr17 + test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_fr_iimmed 0x1111,0x1111,fr14 + set_fr_iimmed 0x2222,0x2222,fr15 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + cmqaddhss fr10,fr12,fr14,cc0,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + cmqaddhss fr10,fr12,fr14,cc0,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0xffff,0xffff,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqaddhss fr10,fr12,fr14,cc0,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8001,0x8001,fr11 + set_fr_iimmed 0xffff,0xfffe,fr12 + set_fr_iimmed 0xfffe,0xfffe,fr13 + cmqaddhss fr10,fr12,fr14,cc4,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x3333,0x3333,fr16 + set_fr_iimmed 0x4444,0x4444,fr17 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + set_fr_iimmed 0x7fff,0x0000,fr12 + set_fr_iimmed 0x0000,0x8000,fr13 + cmqaddhss.p fr10,fr10,fr14,cc4,0 + cmqaddhss fr12,fr12,fr16,cc4,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_fr_limmed 0x3333,0x3333,fr16 + test_fr_limmed 0x4444,0x4444,fr17 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1111,0x1111,fr14 + set_fr_iimmed 0x2222,0x2222,fr15 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + cmqaddhss fr10,fr12,fr14,cc1,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + cmqaddhss fr10,fr12,fr14,cc1,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0xffff,0xffff,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqaddhss fr10,fr12,fr14,cc1,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8001,0x8001,fr11 + set_fr_iimmed 0xffff,0xfffe,fr12 + set_fr_iimmed 0xfffe,0xfffe,fr13 + cmqaddhss fr10,fr12,fr14,cc5,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x3333,0x3333,fr16 + set_fr_iimmed 0x4444,0x4444,fr17 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + set_fr_iimmed 0x7fff,0x0000,fr12 + set_fr_iimmed 0x0000,0x8000,fr13 + cmqaddhss.p fr10,fr10,fr14,cc5,1 + cmqaddhss fr12,fr12,fr16,cc5,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_fr_limmed 0x3333,0x3333,fr16 + test_fr_limmed 0x4444,0x4444,fr17 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1111,0x1111,fr14 + set_fr_iimmed 0x2222,0x2222,fr15 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + cmqaddhss fr10,fr12,fr14,cc2,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + cmqaddhss fr10,fr12,fr14,cc2,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0xffff,0xffff,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqaddhss fr10,fr12,fr14,cc2,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8001,0x8001,fr11 + set_fr_iimmed 0xffff,0xfffe,fr12 + set_fr_iimmed 0xfffe,0xfffe,fr13 + cmqaddhss fr10,fr12,fr14,cc6,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x3333,0x3333,fr16 + set_fr_iimmed 0x4444,0x4444,fr17 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + set_fr_iimmed 0x7fff,0x0000,fr12 + set_fr_iimmed 0x0000,0x8000,fr13 + cmqaddhss.p fr10,fr10,fr14,cc6,1 + cmqaddhss fr12,fr12,fr16,cc6,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_fr_limmed 0x3333,0x3333,fr16 + test_fr_limmed 0x4444,0x4444,fr17 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set +; + set_fr_iimmed 0x1111,0x1111,fr14 + set_fr_iimmed 0x2222,0x2222,fr15 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + cmqaddhss fr10,fr12,fr14,cc3,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + cmqaddhss fr10,fr12,fr14,cc3,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0xffff,0xffff,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqaddhss fr10,fr12,fr14,cc3,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8001,0x8001,fr11 + set_fr_iimmed 0xffff,0xfffe,fr12 + set_fr_iimmed 0xfffe,0xfffe,fr13 + cmqaddhss fr10,fr12,fr14,cc7,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x3333,0x3333,fr16 + set_fr_iimmed 0x4444,0x4444,fr17 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + set_fr_iimmed 0x7fff,0x0000,fr12 + set_fr_iimmed 0x0000,0x8000,fr13 + cmqaddhss.p fr10,fr10,fr14,cc7,1 + cmqaddhss fr12,fr12,fr16,cc7,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_fr_limmed 0x3333,0x3333,fr16 + test_fr_limmed 0x4444,0x4444,fr17 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + pass diff --git a/sim/testsuite/sim/frv/fr550/cmqaddhus.cgs b/sim/testsuite/sim/frv/fr550/cmqaddhus.cgs new file mode 100644 index 0000000..4e25ba4 --- /dev/null +++ b/sim/testsuite/sim/frv/fr550/cmqaddhus.cgs @@ -0,0 +1,345 @@ +# frv testcase for cmqaddhus $FRi,$FRj,$FRj,$CCi,$cond +# mach: all + + .include "../testutils.inc" + + start + + .global cmqaddhus +cmqaddhus: + set_spr_immed 0x1b1b,cccr + + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + cmqaddhus fr10,fr12,fr14,cc0,1 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0xdead,0xbeef,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + cmqaddhus fr10,fr12,fr14,cc0,1 + test_fr_limmed 0xbeef,0xdead,fr14 + test_fr_limmed 0x2345,0x6789,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + set_fr_iimmed 0x0002,0x0001,fr12 + set_fr_iimmed 0x0001,0x0002,fr13 + cmqaddhus fr10,fr12,fr14,cc4,1 + test_fr_limmed 0x8000,0x7fff,fr14 + test_fr_limmed 0xffff,0xffff,fr15 + test_spr_bits 0x3c,2,1,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0002,0x0001,fr10 + set_fr_iimmed 0x0001,0x0001,fr11 + set_fr_iimmed 0xfffe,0xfffe,fr12 + set_fr_iimmed 0x8000,0x8000,fr13 + cmqaddhus.p fr10,fr10,fr14,cc4,1 + cmqaddhus fr12,fr12,fr16,cc4,1 + test_fr_limmed 0x0004,0x0002,fr14 + test_fr_limmed 0x0002,0x0002,fr15 + test_fr_limmed 0xffff,0xffff,fr16 + test_fr_limmed 0xffff,0xffff,fr17 + test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + cmqaddhus fr10,fr12,fr14,cc1,0 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0xdead,0xbeef,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + cmqaddhus fr10,fr12,fr14,cc1,0 + test_fr_limmed 0xbeef,0xdead,fr14 + test_fr_limmed 0x2345,0x6789,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + set_fr_iimmed 0x0002,0x0001,fr12 + set_fr_iimmed 0x0001,0x0002,fr13 + cmqaddhus fr10,fr12,fr14,cc5,0 + test_fr_limmed 0x8000,0x7fff,fr14 + test_fr_limmed 0xffff,0xffff,fr15 + test_spr_bits 0x3c,2,1,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0002,0x0001,fr10 + set_fr_iimmed 0x0001,0x0001,fr11 + set_fr_iimmed 0xfffe,0xfffe,fr12 + set_fr_iimmed 0x8000,0x8000,fr13 + cmqaddhus.p fr10,fr10,fr14,cc5,0 + cmqaddhus fr12,fr12,fr16,cc5,0 + test_fr_limmed 0x0004,0x0002,fr14 + test_fr_limmed 0x0002,0x0002,fr15 + test_fr_limmed 0xffff,0xffff,fr16 + test_fr_limmed 0xffff,0xffff,fr17 + test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_fr_iimmed 0x1111,0x1111,fr14 + set_fr_iimmed 0x2222,0x2222,fr15 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + cmqaddhus fr10,fr12,fr14,cc0,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + cmqaddhus fr10,fr12,fr14,cc0,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + set_fr_iimmed 0x0002,0x0001,fr12 + set_fr_iimmed 0x0001,0x0002,fr13 + cmqaddhus fr10,fr12,fr14,cc4,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x3333,0x3333,fr16 + set_fr_iimmed 0x4444,0x4444,fr17 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0002,0x0001,fr10 + set_fr_iimmed 0x0001,0x0001,fr11 + set_fr_iimmed 0xfffe,0xfffe,fr12 + set_fr_iimmed 0x8000,0x8000,fr13 + cmqaddhus.p fr10,fr10,fr14,cc4,0 + cmqaddhus fr12,fr12,fr16,cc4,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_fr_limmed 0x3333,0x3333,fr16 + test_fr_limmed 0x4444,0x4444,fr17 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1111,0x1111,fr14 + set_fr_iimmed 0x2222,0x2222,fr15 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + cmqaddhus fr10,fr12,fr14,cc1,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + cmqaddhus fr10,fr12,fr14,cc1,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + set_fr_iimmed 0x0002,0x0001,fr12 + set_fr_iimmed 0x0001,0x0002,fr13 + cmqaddhus fr10,fr12,fr14,cc5,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x3333,0x3333,fr16 + set_fr_iimmed 0x4444,0x4444,fr17 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0002,0x0001,fr10 + set_fr_iimmed 0x0001,0x0001,fr11 + set_fr_iimmed 0xfffe,0xfffe,fr12 + set_fr_iimmed 0x8000,0x8000,fr13 + cmqaddhus.p fr10,fr10,fr14,cc5,1 + cmqaddhus fr12,fr12,fr16,cc5,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_fr_limmed 0x3333,0x3333,fr16 + test_fr_limmed 0x4444,0x4444,fr17 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1111,0x1111,fr14 + set_fr_iimmed 0x2222,0x2222,fr15 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + cmqaddhus fr10,fr12,fr14,cc2,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + cmqaddhus fr10,fr12,fr14,cc2,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + set_fr_iimmed 0x0002,0x0001,fr12 + set_fr_iimmed 0x0001,0x0002,fr13 + cmqaddhus fr10,fr12,fr14,cc6,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x3333,0x3333,fr16 + set_fr_iimmed 0x4444,0x4444,fr17 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0002,0x0001,fr10 + set_fr_iimmed 0x0001,0x0001,fr11 + set_fr_iimmed 0xfffe,0xfffe,fr12 + set_fr_iimmed 0x8000,0x8000,fr13 + cmqaddhus.p fr10,fr10,fr14,cc6,0 + cmqaddhus fr12,fr12,fr16,cc6,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_fr_limmed 0x3333,0x3333,fr16 + test_fr_limmed 0x4444,0x4444,fr17 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1111,0x1111,fr14 + set_fr_iimmed 0x2222,0x2222,fr15 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + cmqaddhus fr10,fr12,fr14,cc3,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + cmqaddhus fr10,fr12,fr14,cc3,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + set_fr_iimmed 0x0002,0x0001,fr12 + set_fr_iimmed 0x0001,0x0002,fr13 + cmqaddhus fr10,fr12,fr14,cc7,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x3333,0x3333,fr16 + set_fr_iimmed 0x4444,0x4444,fr17 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0002,0x0001,fr10 + set_fr_iimmed 0x0001,0x0001,fr11 + set_fr_iimmed 0xfffe,0xfffe,fr12 + set_fr_iimmed 0x8000,0x8000,fr13 + cmqaddhus.p fr10,fr10,fr14,cc7,0 + cmqaddhus fr12,fr12,fr16,cc7,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_fr_limmed 0x3333,0x3333,fr16 + test_fr_limmed 0x4444,0x4444,fr17 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + pass diff --git a/sim/testsuite/sim/frv/fr550/cmqmachs.cgs b/sim/testsuite/sim/frv/fr550/cmqmachs.cgs new file mode 100644 index 0000000..0aee4f0 --- /dev/null +++ b/sim/testsuite/sim/frv/fr550/cmqmachs.cgs @@ -0,0 +1,1262 @@ +# frv testcase for cmqmachs $GRi,$GRj,$ACCk,$CCi,$cond +# mach: all + + .include "../testutils.inc" + + start + + .global cmqmachs +cmqmachs: + set_spr_immed 0x1b1b,cccr + + ; Positive operands + set_spr_immed 0,msr0 + set_accg_immed 0,accg0 + set_acc_immed 0,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0,acc2 + set_accg_immed 0,accg3 + set_acc_immed 0,acc3 + set_fr_iimmed 2,3,fr8 ; multiply small numbers + set_fr_iimmed 3,2,fr10 + set_fr_iimmed 0,1,fr9 ; multiply by 0 + set_fr_iimmed 2,0,fr11 + cmqmachs fr8,fr10,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0,acc3 + + set_fr_iimmed 2,1,fr8 ; multiply by 1 + set_fr_iimmed 1,2,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmachs fr8,fr10,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 8,acc0 + test_accg_immed 0,accg1 + test_acc_immed 8,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0,0x7ffe,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0,0x7ffe,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8008,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8008,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x3fff,0x7fff,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x3fff,0x7fff,acc3 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr10 + set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr11 + cmqmachs fr8,fr10,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8002,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8002,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x3fff,0x7ffd,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x3fff,0x7ffd,acc3 + + set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr10 + set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr11 + cmqmachs fr8,fr10,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8002,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8002,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x3fff,0x3ffb,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x3fff,0x3ffb,acc3 + + set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr10 + set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc4,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x0002,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x0002,acc1 + test_accg_immed 0xff,accg2 + test_acc_limmed 0xffff,0xbffb,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0xffff,0xbffb,acc3 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr10 + set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr11 + cmqmachs fr8,fr10,acc0,cc4,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x0008,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x0008,acc1 + test_accg_immed 0xff,accg2 + test_acc_limmed 0xffff,0xbffd,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0xffff,0xbffd,acc3 + + set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmachs fr8,fr10,acc0,cc4,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0009,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fff0009,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0x3fffbffd,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0x3fffbffd,acc3 + + set_accg_immed 0x7f,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0x7f,accg1 + set_acc_immed 0xffffffff,acc1 + set_accg_immed 0x7f,accg2 ; saturation + set_acc_immed 0xffffffff,acc2 + set_accg_immed 0x7f,accg3 + set_acc_immed 0xffffffff,acc3 + set_fr_iimmed 1,1,fr8 + set_fr_iimmed 1,1,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc4,1 + test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + test_accg_immed 0x7f,accg2 + test_acc_limmed 0xffff,0xffff,acc2 + test_accg_immed 0x7f,accg3 + test_acc_limmed 0xffff,0xffff,acc3 + + set_accg_immed 0x80,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed 0x80,accg1 + set_acc_immed 0,acc1 + set_accg_immed 0x80,accg2 ; saturation + set_acc_immed 0,acc2 + set_accg_immed 0x80,accg3 + set_acc_immed 0,acc3 + set_fr_iimmed 0xffff,0,fr8 + set_fr_iimmed 1,0xffff,fr10 + set_fr_iimmed 0x0000,0x8000,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc4,1 + test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x80,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + test_accg_immed 0x80,accg2 + test_acc_immed 0,acc2 + test_accg_immed 0x80,accg3 + test_acc_immed 0,acc3 + + ; Positive operands + set_spr_immed 0,msr0 + set_accg_immed 0,accg0 + set_acc_immed 0,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0,acc2 + set_accg_immed 0,accg3 + set_acc_immed 0,acc3 + set_fr_iimmed 2,3,fr8 ; multiply small numbers + set_fr_iimmed 3,2,fr10 + set_fr_iimmed 0,1,fr9 ; multiply by 0 + set_fr_iimmed 2,0,fr11 + cmqmachs fr8,fr10,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0,acc3 + + set_fr_iimmed 2,1,fr8 ; multiply by 1 + set_fr_iimmed 1,2,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmachs fr8,fr10,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 8,acc0 + test_accg_immed 0,accg1 + test_acc_immed 8,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0,0x7ffe,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0,0x7ffe,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8008,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8008,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x3fff,0x7fff,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x3fff,0x7fff,acc3 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr10 + set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr11 + cmqmachs fr8,fr10,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8002,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8002,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x3fff,0x7ffd,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x3fff,0x7ffd,acc3 + + set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr10 + set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr11 + cmqmachs fr8,fr10,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8002,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8002,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x3fff,0x3ffb,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x3fff,0x3ffb,acc3 + + set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr10 + set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc5,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x0002,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x0002,acc1 + test_accg_immed 0xff,accg2 + test_acc_limmed 0xffff,0xbffb,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0xffff,0xbffb,acc3 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr10 + set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr11 + cmqmachs fr8,fr10,acc0,cc5,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x0008,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x0008,acc1 + test_accg_immed 0xff,accg2 + test_acc_limmed 0xffff,0xbffd,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0xffff,0xbffd,acc3 + + set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmachs fr8,fr10,acc0,cc5,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0009,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fff0009,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0x3fffbffd,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0x3fffbffd,acc3 + + set_accg_immed 0x7f,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0x7f,accg1 + set_acc_immed 0xffffffff,acc1 + set_accg_immed 0x7f,accg2 ; saturation + set_acc_immed 0xffffffff,acc2 + set_accg_immed 0x7f,accg3 + set_acc_immed 0xffffffff,acc3 + set_fr_iimmed 1,1,fr8 + set_fr_iimmed 1,1,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc5,0 + test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + test_accg_immed 0x7f,accg2 + test_acc_limmed 0xffff,0xffff,acc2 + test_accg_immed 0x7f,accg3 + test_acc_limmed 0xffff,0xffff,acc3 + + set_accg_immed 0x80,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed 0x80,accg1 + set_acc_immed 0,acc1 + set_accg_immed 0x80,accg2 ; saturation + set_acc_immed 0,acc2 + set_accg_immed 0x80,accg3 + set_acc_immed 0,acc3 + set_fr_iimmed 0xffff,0,fr8 + set_fr_iimmed 1,0xffff,fr10 + set_fr_iimmed 0x0000,0x8000,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc5,0 + test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x80,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + test_accg_immed 0x80,accg2 + test_acc_immed 0,acc2 + test_accg_immed 0x80,accg3 + test_acc_immed 0,acc3 + + ; Positive operands + set_spr_immed 0,msr0 + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_accg_immed 0x00000033,accg2 + set_acc_immed 0x33333333,acc2 + set_accg_immed 0x00000044,accg3 + set_acc_immed 0x44444444,acc3 + set_fr_iimmed 2,3,fr8 ; multiply small numbers + set_fr_iimmed 3,2,fr10 + set_fr_iimmed 0,1,fr9 ; multiply by 0 + set_fr_iimmed 2,0,fr11 + cmqmachs fr8,fr10,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 2,1,fr8 ; multiply by 1 + set_fr_iimmed 1,2,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmachs fr8,fr10,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr10 + set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr11 + cmqmachs fr8,fr10,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr10 + set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr11 + cmqmachs fr8,fr10,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr10 + set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr10 + set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr11 + cmqmachs fr8,fr10,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmachs fr8,fr10,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_accg_immed 0x7f,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0x7f,accg1 + set_acc_immed 0xffffffff,acc1 + set_accg_immed 0x7f,accg2 ; saturation + set_acc_immed 0xffffffff,acc2 + set_accg_immed 0x7f,accg3 + set_acc_immed 0xffffffff,acc3 + set_fr_iimmed 1,1,fr8 + set_fr_iimmed 1,1,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x7f,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_immed 0xffffffff,acc1 + test_accg_immed 0x7f,accg2 ; saturation + test_acc_immed 0xffffffff,acc2 + test_accg_immed 0x7f,accg3 + test_acc_immed 0xffffffff,acc3 + + set_accg_immed 0x80,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed 0x80,accg1 + set_acc_immed 0,acc1 + set_accg_immed 0x80,accg2 ; saturation + set_acc_immed 0,acc2 + set_accg_immed 0x80,accg3 + set_acc_immed 0,acc3 + set_fr_iimmed 0xffff,0,fr8 + set_fr_iimmed 1,0xffff,fr10 + set_fr_iimmed 0x0000,0x8000,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x80,accg0 ; saturation + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + test_accg_immed 0x80,accg2 ; saturation + test_acc_immed 0,acc2 + test_accg_immed 0x80,accg3 + test_acc_immed 0,acc3 + + ; Positive operands + set_spr_immed 0,msr0 + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_accg_immed 0x00000033,accg2 + set_acc_immed 0x33333333,acc2 + set_accg_immed 0x00000044,accg3 + set_acc_immed 0x44444444,acc3 + set_fr_iimmed 2,3,fr8 ; multiply small numbers + set_fr_iimmed 3,2,fr10 + set_fr_iimmed 0,1,fr9 ; multiply by 0 + set_fr_iimmed 2,0,fr11 + cmqmachs fr8,fr10,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 2,1,fr8 ; multiply by 1 + set_fr_iimmed 1,2,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmachs fr8,fr10,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr10 + set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr11 + cmqmachs fr8,fr10,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr10 + set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr11 + cmqmachs fr8,fr10,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr10 + set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr10 + set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr11 + cmqmachs fr8,fr10,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmachs fr8,fr10,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_accg_immed 0x7f,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0x7f,accg1 + set_acc_immed 0xffffffff,acc1 + set_accg_immed 0x7f,accg2 ; saturation + set_acc_immed 0xffffffff,acc2 + set_accg_immed 0x7f,accg3 + set_acc_immed 0xffffffff,acc3 + set_fr_iimmed 1,1,fr8 + set_fr_iimmed 1,1,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x7f,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_immed 0xffffffff,acc1 + test_accg_immed 0x7f,accg2 ; saturation + test_acc_immed 0xffffffff,acc2 + test_accg_immed 0x7f,accg3 + test_acc_immed 0xffffffff,acc3 + + set_accg_immed 0x80,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed 0x80,accg1 + set_acc_immed 0,acc1 + set_accg_immed 0x80,accg2 ; saturation + set_acc_immed 0,acc2 + set_accg_immed 0x80,accg3 + set_acc_immed 0,acc3 + set_fr_iimmed 0xffff,0,fr8 + set_fr_iimmed 1,0xffff,fr10 + set_fr_iimmed 0x0000,0x8000,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x80,accg0 ; saturation + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + test_accg_immed 0x80,accg2 ; saturation + test_acc_immed 0,acc2 + test_accg_immed 0x80,accg3 + test_acc_immed 0,acc3 + + ; Positive operands + set_spr_immed 0,msr0 + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_accg_immed 0x00000033,accg2 + set_acc_immed 0x33333333,acc2 + set_accg_immed 0x00000044,accg3 + set_acc_immed 0x44444444,acc3 + set_fr_iimmed 2,3,fr8 ; multiply small numbers + set_fr_iimmed 3,2,fr10 + set_fr_iimmed 0,1,fr9 ; multiply by 0 + set_fr_iimmed 2,0,fr11 + cmqmachs fr8,fr10,acc0,cc2,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 2,1,fr8 ; multiply by 1 + set_fr_iimmed 1,2,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmachs fr8,fr10,acc0,cc2,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc2,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr10 + set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr11 + cmqmachs fr8,fr10,acc0,cc2,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr10 + set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr11 + cmqmachs fr8,fr10,acc0,cc2,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr10 + set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc6,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr10 + set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr11 + cmqmachs fr8,fr10,acc0,cc6,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmachs fr8,fr10,acc0,cc6,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_accg_immed 0x7f,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0x7f,accg1 + set_acc_immed 0xffffffff,acc1 + set_accg_immed 0x7f,accg2 ; saturation + set_acc_immed 0xffffffff,acc2 + set_accg_immed 0x7f,accg3 + set_acc_immed 0xffffffff,acc3 + set_fr_iimmed 1,1,fr8 + set_fr_iimmed 1,1,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc6,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x7f,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_immed 0xffffffff,acc1 + test_accg_immed 0x7f,accg2 ; saturation + test_acc_immed 0xffffffff,acc2 + test_accg_immed 0x7f,accg3 + test_acc_immed 0xffffffff,acc3 + + set_accg_immed 0x80,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed 0x80,accg1 + set_acc_immed 0,acc1 + set_accg_immed 0x80,accg2 ; saturation + set_acc_immed 0,acc2 + set_accg_immed 0x80,accg3 + set_acc_immed 0,acc3 + set_fr_iimmed 0xffff,0,fr8 + set_fr_iimmed 1,0xffff,fr10 + set_fr_iimmed 0x0000,0x8000,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc6,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x80,accg0 ; saturation + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + test_accg_immed 0x80,accg2 ; saturation + test_acc_immed 0,acc2 + test_accg_immed 0x80,accg3 + test_acc_immed 0,acc3 +; + ; Positive operands + set_spr_immed 0,msr0 + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_accg_immed 0x00000033,accg2 + set_acc_immed 0x33333333,acc2 + set_accg_immed 0x00000044,accg3 + set_acc_immed 0x44444444,acc3 + set_fr_iimmed 2,3,fr8 ; multiply small numbers + set_fr_iimmed 3,2,fr10 + set_fr_iimmed 0,1,fr9 ; multiply by 0 + set_fr_iimmed 2,0,fr11 + cmqmachs fr8,fr10,acc0,cc3,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 2,1,fr8 ; multiply by 1 + set_fr_iimmed 1,2,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmachs fr8,fr10,acc0,cc3,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc3,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr10 + set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr11 + cmqmachs fr8,fr10,acc0,cc3,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr10 + set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr11 + cmqmachs fr8,fr10,acc0,cc3,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr10 + set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc7,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr10 + set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr11 + cmqmachs fr8,fr10,acc0,cc7,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmachs fr8,fr10,acc0,cc7,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_accg_immed 0x7f,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0x7f,accg1 + set_acc_immed 0xffffffff,acc1 + set_accg_immed 0x7f,accg2 ; saturation + set_acc_immed 0xffffffff,acc2 + set_accg_immed 0x7f,accg3 + set_acc_immed 0xffffffff,acc3 + set_fr_iimmed 1,1,fr8 + set_fr_iimmed 1,1,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc7,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x7f,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_immed 0xffffffff,acc1 + test_accg_immed 0x7f,accg2 ; saturation + test_acc_immed 0xffffffff,acc2 + test_accg_immed 0x7f,accg3 + test_acc_immed 0xffffffff,acc3 + + set_accg_immed 0x80,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed 0x80,accg1 + set_acc_immed 0,acc1 + set_accg_immed 0x80,accg2 ; saturation + set_acc_immed 0,acc2 + set_accg_immed 0x80,accg3 + set_acc_immed 0,acc3 + set_fr_iimmed 0xffff,0,fr8 + set_fr_iimmed 1,0xffff,fr10 + set_fr_iimmed 0x0000,0x8000,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + cmqmachs fr8,fr10,acc0,cc7,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x80,accg0 ; saturation + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + test_accg_immed 0x80,accg2 ; saturation + test_acc_immed 0,acc2 + test_accg_immed 0x80,accg3 + test_acc_immed 0,acc3 + + pass + + diff --git a/sim/testsuite/sim/frv/fr550/cmqmachu.cgs b/sim/testsuite/sim/frv/fr550/cmqmachu.cgs new file mode 100644 index 0000000..8b880f8 --- /dev/null +++ b/sim/testsuite/sim/frv/fr550/cmqmachu.cgs @@ -0,0 +1,870 @@ +# frv testcase for cmqmachu $GRi,$GRj,$GRk,$CCi,$cond +# mach: all + + .include "../testutils.inc" + + start + + .global cmqmachu +cmqmachu: + set_spr_immed 0x1b1b,cccr + + set_spr_immed 0,msr0 + set_accg_immed 0,accg0 + set_acc_immed 0,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0,acc2 + set_accg_immed 0,accg3 + set_acc_immed 0,acc3 + set_fr_iimmed 3,2,fr8 ; multiply small numbers + set_fr_iimmed 2,3,fr10 + set_fr_iimmed 1,2,fr9 ; multiply by 1 + set_fr_iimmed 2,1,fr11 + cmqmachu fr8,fr10,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + test_accg_immed 0,accg2 + test_acc_immed 2,acc2 + test_accg_immed 0,accg3 + test_acc_immed 2,acc3 + + set_fr_iimmed 0,2,fr8 ; multiply by 0 + set_fr_iimmed 2,0,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmachu fr8,fr10,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x8000,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x8000,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x8000,2,fr9 ; 17 bit result + set_fr_iimmed 2,0x8000,fr11 + cmqmachu fr8,fr10,acc0,cc0,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8006,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8006,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0x00018000,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0x00018000,acc3 + + set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmachu fr8,fr10,acc0,cc4,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0x3fff8007,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fff8007,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x4001,0x8000,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x4001,0x8000,acc3 + + set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr11 + cmqmachu fr8,fr10,acc0,cc4,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 1,accg0 + test_acc_limmed 0x3ffd,0x8008,acc0 + test_accg_immed 1,accg1 + test_acc_limmed 0x3ffd,0x8008,acc1 + test_accg_immed 1,accg2 + test_acc_limmed 0x3fff,0x8001,acc2 + test_accg_immed 1,accg3 + test_acc_limmed 0x3fff,0x8001,acc3 + + set_accg_immed 0xff,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xffffffff,acc1 + set_accg_immed 0xff,accg2 ; saturation + set_acc_immed 0xffffffff,acc2 + set_accg_immed 0xff,accg3 + set_acc_immed 0xffffffff,acc3 + set_fr_iimmed 1,1,fr8 + set_fr_iimmed 1,1,fr10 + set_fr_iimmed 1,1,fr9 + set_fr_iimmed 1,1,fr11 + cmqmachu fr8,fr10,acc0,cc4,1 + test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + test_accg_immed 0xff,accg2 + test_acc_limmed 0xffff,0xffff,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0xffff,0xffff,acc3 + + set_fr_iimmed 0xffff,0x0000,fr8 + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0x0000,0xffff,fr9 + set_fr_iimmed 0xffff,0xffff,fr11 + cmqmachu fr8,fr10,acc0,cc4,1 + test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + test_accg_immed 0xff,accg2 + test_acc_limmed 0xffff,0xffff,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0xffff,0xffff,acc3 + + set_spr_immed 0,msr0 + set_accg_immed 0,accg0 + set_acc_immed 0,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0,acc2 + set_accg_immed 0,accg3 + set_acc_immed 0,acc3 + set_fr_iimmed 3,2,fr8 ; multiply small numbers + set_fr_iimmed 2,3,fr10 + set_fr_iimmed 1,2,fr9 ; multiply by 1 + set_fr_iimmed 2,1,fr11 + cmqmachu fr8,fr10,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + test_accg_immed 0,accg2 + test_acc_immed 2,acc2 + test_accg_immed 0,accg3 + test_acc_immed 2,acc3 + + set_fr_iimmed 0,2,fr8 ; multiply by 0 + set_fr_iimmed 2,0,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmachu fr8,fr10,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x8000,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x8000,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x8000,2,fr9 ; 17 bit result + set_fr_iimmed 2,0x8000,fr11 + cmqmachu fr8,fr10,acc0,cc1,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8006,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8006,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0x00018000,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0x00018000,acc3 + + set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmachu fr8,fr10,acc0,cc5,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0x3fff8007,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fff8007,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x4001,0x8000,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x4001,0x8000,acc3 + + set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr11 + cmqmachu fr8,fr10,acc0,cc5,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 1,accg0 + test_acc_limmed 0x3ffd,0x8008,acc0 + test_accg_immed 1,accg1 + test_acc_limmed 0x3ffd,0x8008,acc1 + test_accg_immed 1,accg2 + test_acc_limmed 0x3fff,0x8001,acc2 + test_accg_immed 1,accg3 + test_acc_limmed 0x3fff,0x8001,acc3 + + set_accg_immed 0xff,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xffffffff,acc1 + set_accg_immed 0xff,accg2 ; saturation + set_acc_immed 0xffffffff,acc2 + set_accg_immed 0xff,accg3 + set_acc_immed 0xffffffff,acc3 + set_fr_iimmed 1,1,fr8 + set_fr_iimmed 1,1,fr10 + set_fr_iimmed 1,1,fr9 + set_fr_iimmed 1,1,fr11 + cmqmachu fr8,fr10,acc0,cc5,0 + test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + test_accg_immed 0xff,accg2 + test_acc_limmed 0xffff,0xffff,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0xffff,0xffff,acc3 + + set_fr_iimmed 0xffff,0x0000,fr8 + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0x0000,0xffff,fr9 + set_fr_iimmed 0xffff,0xffff,fr11 + cmqmachu fr8,fr10,acc0,cc5,0 + test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + test_accg_immed 0xff,accg2 + test_acc_limmed 0xffff,0xffff,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0xffff,0xffff,acc3 + + set_spr_immed 0,msr0 + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_accg_immed 0x00000033,accg2 + set_acc_immed 0x33333333,acc2 + set_accg_immed 0x00000044,accg3 + set_acc_immed 0x44444444,acc3 + set_fr_iimmed 3,2,fr8 ; multiply small numbers + set_fr_iimmed 2,3,fr10 + set_fr_iimmed 1,2,fr9 ; multiply by 1 + set_fr_iimmed 2,1,fr11 + cmqmachu fr8,fr10,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0,2,fr8 ; multiply by 0 + set_fr_iimmed 2,0,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmachu fr8,fr10,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x8000,2,fr9 ; 17 bit result + set_fr_iimmed 2,0x8000,fr11 + cmqmachu fr8,fr10,acc0,cc0,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmachu fr8,fr10,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr11 + cmqmachu fr8,fr10,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_accg_immed 0xff,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xffffffff,acc1 + set_accg_immed 0xff,accg2 ; saturation + set_acc_immed 0xffffffff,acc2 + set_accg_immed 0xff,accg3 + set_acc_immed 0xffffffff,acc3 + set_fr_iimmed 1,1,fr8 + set_fr_iimmed 1,1,fr10 + set_fr_iimmed 1,1,fr9 + set_fr_iimmed 1,1,fr11 + cmqmachu fr8,fr10,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0xff,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed 0xffffffff,acc1 + test_accg_immed 0xff,accg2 ; saturation + test_acc_immed 0xffffffff,acc2 + test_accg_immed 0xff,accg3 + test_acc_immed 0xffffffff,acc3 + + set_fr_iimmed 0xffff,0x0000,fr8 + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0x0000,0xffff,fr9 + set_fr_iimmed 0xffff,0xffff,fr11 + cmqmachu fr8,fr10,acc0,cc4,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0xff,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed 0xffffffff,acc1 + test_accg_immed 0xff,accg2 ; saturation + test_acc_immed 0xffffffff,acc2 + test_accg_immed 0xff,accg3 + test_acc_immed 0xffffffff,acc3 + + set_spr_immed 0,msr0 + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_accg_immed 0x00000033,accg2 + set_acc_immed 0x33333333,acc2 + set_accg_immed 0x00000044,accg3 + set_acc_immed 0x44444444,acc3 + set_fr_iimmed 3,2,fr8 ; multiply small numbers + set_fr_iimmed 2,3,fr10 + set_fr_iimmed 1,2,fr9 ; multiply by 1 + set_fr_iimmed 2,1,fr11 + cmqmachu fr8,fr10,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0,2,fr8 ; multiply by 0 + set_fr_iimmed 2,0,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmachu fr8,fr10,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x8000,2,fr9 ; 17 bit result + set_fr_iimmed 2,0x8000,fr11 + cmqmachu fr8,fr10,acc0,cc1,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmachu fr8,fr10,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr11 + cmqmachu fr8,fr10,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_accg_immed 0xff,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xffffffff,acc1 + set_accg_immed 0xff,accg2 ; saturation + set_acc_immed 0xffffffff,acc2 + set_accg_immed 0xff,accg3 + set_acc_immed 0xffffffff,acc3 + set_fr_iimmed 1,1,fr8 + set_fr_iimmed 1,1,fr10 + set_fr_iimmed 1,1,fr9 + set_fr_iimmed 1,1,fr11 + cmqmachu fr8,fr10,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0xff,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed 0xffffffff,acc1 + test_accg_immed 0xff,accg2 ; saturation + test_acc_immed 0xffffffff,acc2 + test_accg_immed 0xff,accg3 + test_acc_immed 0xffffffff,acc3 + + set_fr_iimmed 0xffff,0x0000,fr8 + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0x0000,0xffff,fr9 + set_fr_iimmed 0xffff,0xffff,fr11 + cmqmachu fr8,fr10,acc0,cc5,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0xff,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed 0xffffffff,acc1 + test_accg_immed 0xff,accg2 ; saturation + test_acc_immed 0xffffffff,acc2 + test_accg_immed 0xff,accg3 + test_acc_immed 0xffffffff,acc3 + + set_spr_immed 0,msr0 + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_accg_immed 0x00000033,accg2 + set_acc_immed 0x33333333,acc2 + set_accg_immed 0x00000044,accg3 + set_acc_immed 0x44444444,acc3 + set_fr_iimmed 3,2,fr8 ; multiply small numbers + set_fr_iimmed 2,3,fr10 + set_fr_iimmed 1,2,fr9 ; multiply by 1 + set_fr_iimmed 2,1,fr11 + cmqmachu fr8,fr10,acc0,cc2,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0,2,fr8 ; multiply by 0 + set_fr_iimmed 2,0,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmachu fr8,fr10,acc0,cc2,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x8000,2,fr9 ; 17 bit result + set_fr_iimmed 2,0x8000,fr11 + cmqmachu fr8,fr10,acc0,cc2,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmachu fr8,fr10,acc0,cc6,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr11 + cmqmachu fr8,fr10,acc0,cc6,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_accg_immed 0xff,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xffffffff,acc1 + set_accg_immed 0xff,accg2 ; saturation + set_acc_immed 0xffffffff,acc2 + set_accg_immed 0xff,accg3 + set_acc_immed 0xffffffff,acc3 + set_fr_iimmed 1,1,fr8 + set_fr_iimmed 1,1,fr10 + set_fr_iimmed 1,1,fr9 + set_fr_iimmed 1,1,fr11 + cmqmachu fr8,fr10,acc0,cc6,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0xff,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed 0xffffffff,acc1 + test_accg_immed 0xff,accg2 ; saturation + test_acc_immed 0xffffffff,acc2 + test_accg_immed 0xff,accg3 + test_acc_immed 0xffffffff,acc3 + + set_fr_iimmed 0xffff,0x0000,fr8 + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0x0000,0xffff,fr9 + set_fr_iimmed 0xffff,0xffff,fr11 + cmqmachu fr8,fr10,acc0,cc6,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0xff,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed 0xffffffff,acc1 + test_accg_immed 0xff,accg2 ; saturation + test_acc_immed 0xffffffff,acc2 + test_accg_immed 0xff,accg3 + test_acc_immed 0xffffffff,acc3 +; + set_spr_immed 0,msr0 + set_accg_immed 0x00000011,accg0 + set_acc_immed 0x11111111,acc0 + set_accg_immed 0x00000022,accg1 + set_acc_immed 0x22222222,acc1 + set_accg_immed 0x00000033,accg2 + set_acc_immed 0x33333333,acc2 + set_accg_immed 0x00000044,accg3 + set_acc_immed 0x44444444,acc3 + set_fr_iimmed 3,2,fr8 ; multiply small numbers + set_fr_iimmed 2,3,fr10 + set_fr_iimmed 1,2,fr9 ; multiply by 1 + set_fr_iimmed 2,1,fr11 + cmqmachu fr8,fr10,acc0,cc3,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0,2,fr8 ; multiply by 0 + set_fr_iimmed 2,0,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + cmqmachu fr8,fr10,acc0,cc3,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x8000,2,fr9 ; 17 bit result + set_fr_iimmed 2,0x8000,fr11 + cmqmachu fr8,fr10,acc0,cc3,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + cmqmachu fr8,fr10,acc0,cc7,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr11 + cmqmachu fr8,fr10,acc0,cc7,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x00000011,accg0 + test_acc_immed 0x11111111,acc0 + test_accg_immed 0x00000022,accg1 + test_acc_immed 0x22222222,acc1 + test_accg_immed 0x00000033,accg2 + test_acc_immed 0x33333333,acc2 + test_accg_immed 0x00000044,accg3 + test_acc_immed 0x44444444,acc3 + + set_accg_immed 0xff,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xffffffff,acc1 + set_accg_immed 0xff,accg2 ; saturation + set_acc_immed 0xffffffff,acc2 + set_accg_immed 0xff,accg3 + set_acc_immed 0xffffffff,acc3 + set_fr_iimmed 1,1,fr8 + set_fr_iimmed 1,1,fr10 + set_fr_iimmed 1,1,fr9 + set_fr_iimmed 1,1,fr11 + cmqmachu fr8,fr10,acc0,cc7,0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0xff,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed 0xffffffff,acc1 + test_accg_immed 0xff,accg2 ; saturation + test_acc_immed 0xffffffff,acc2 + test_accg_immed 0xff,accg3 + test_acc_immed 0xffffffff,acc3 + + set_fr_iimmed 0xffff,0x0000,fr8 + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0x0000,0xffff,fr9 + set_fr_iimmed 0xffff,0xffff,fr11 + cmqmachu fr8,fr10,acc0,cc7,1 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0xff,accg0 ; saturation + test_acc_immed 0xffffffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed 0xffffffff,acc1 + test_accg_immed 0xff,accg2 ; saturation + test_acc_immed 0xffffffff,acc2 + test_accg_immed 0xff,accg3 + test_acc_immed 0xffffffff,acc3 + + pass diff --git a/sim/testsuite/sim/frv/fr550/cmqsubhss.cgs b/sim/testsuite/sim/frv/fr550/cmqsubhss.cgs new file mode 100644 index 0000000..490b449 --- /dev/null +++ b/sim/testsuite/sim/frv/fr550/cmqsubhss.cgs @@ -0,0 +1,429 @@ +# frv testcase for cmqsubhss $FRi,$FRj,$FRj,$CCi,$cond +# mach: all + + .include "../testutils.inc" + + start + + .global msubhss +msubhss: + set_spr_immed 0x1b1b,cccr + + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + cmqsubhss fr10,fr12,fr14,cc0,1 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0xdead,0x4111,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + cmqsubhss fr10,fr12,fr14,cc0,1 + test_fr_limmed 0x4111,0xdead,fr14 + test_fr_limmed 0x0123,0x4567,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0xffff,0xffff,fr12 + set_fr_iimmed 0xfffe,0xffff,fr13 + cmqsubhss fr10,fr12,fr14,cc0,1 + test_fr_limmed 0x1235,0x5679,fr14 + test_fr_limmed 0x7fff,0x7fff,fr15 + test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8001,0x8001,fr11 + set_fr_iimmed 0x0001,0x0002,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqsubhss fr10,fr12,fr14,cc4,1 + test_fr_limmed 0x8000,0x8000,fr14 + test_fr_limmed 0x8000,0x8000,fr15 + test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + set_fr_iimmed 0x8000,0x8000,fr12 + set_fr_iimmed 0x8000,0x8000,fr13 + cmqsubhss.p fr10,fr10,fr14,cc4,1 + cmqsubhss fr12,fr10,fr16,cc4,1 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0x0000,0x0000,fr15 + test_fr_limmed 0x8000,0x8000,fr16 + test_fr_limmed 0x8001,0x8001,fr17 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + cmqsubhss fr10,fr12,fr14,cc1,0 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0xdead,0x4111,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + cmqsubhss fr10,fr12,fr14,cc1,0 + test_fr_limmed 0x4111,0xdead,fr14 + test_fr_limmed 0x0123,0x4567,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0xffff,0xffff,fr12 + set_fr_iimmed 0xfffe,0xffff,fr13 + cmqsubhss fr10,fr12,fr14,cc1,0 + test_fr_limmed 0x1235,0x5679,fr14 + test_fr_limmed 0x7fff,0x7fff,fr15 + test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8001,0x8001,fr11 + set_fr_iimmed 0x0001,0x0002,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqsubhss fr10,fr12,fr14,cc5,0 + test_fr_limmed 0x8000,0x8000,fr14 + test_fr_limmed 0x8000,0x8000,fr15 + test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + set_fr_iimmed 0x8000,0x8000,fr12 + set_fr_iimmed 0x8000,0x8000,fr13 + cmqsubhss.p fr10,fr10,fr14,cc5,0 + cmqsubhss fr12,fr10,fr16,cc5,0 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0x0000,0x0000,fr15 + test_fr_limmed 0x8000,0x8000,fr16 + test_fr_limmed 0x8001,0x8001,fr17 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf not set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_fr_iimmed 0x1111,0x1111,fr14 + set_fr_iimmed 0x2222,0x2222,fr15 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + cmqsubhss fr10,fr12,fr14,cc0,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + cmqsubhss fr10,fr12,fr14,cc0,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0xffff,0xffff,fr12 + set_fr_iimmed 0xfffe,0xffff,fr13 + cmqsubhss fr10,fr12,fr14,cc0,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8001,0x8001,fr11 + set_fr_iimmed 0x0001,0x0002,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqsubhss fr10,fr12,fr14,cc4,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x3333,0x3333,fr16 + set_fr_iimmed 0x4444,0x4444,fr17 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + set_fr_iimmed 0x8000,0x8000,fr12 + set_fr_iimmed 0x8000,0x8000,fr13 + cmqsubhss.p fr10,fr10,fr14,cc4,0 + cmqsubhss fr12,fr10,fr16,cc4,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_fr_limmed 0x3333,0x3333,fr16 + test_fr_limmed 0x4444,0x4444,fr17 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1111,0x1111,fr14 + set_fr_iimmed 0x2222,0x2222,fr15 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + cmqsubhss fr10,fr12,fr14,cc1,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + cmqsubhss fr10,fr12,fr14,cc1,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0xffff,0xffff,fr12 + set_fr_iimmed 0xfffe,0xffff,fr13 + cmqsubhss fr10,fr12,fr14,cc1,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8001,0x8001,fr11 + set_fr_iimmed 0x0001,0x0002,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqsubhss fr10,fr12,fr14,cc5,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x3333,0x3333,fr16 + set_fr_iimmed 0x4444,0x4444,fr17 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + set_fr_iimmed 0x8000,0x8000,fr12 + set_fr_iimmed 0x8000,0x8000,fr13 + cmqsubhss.p fr10,fr10,fr14,cc5,1 + cmqsubhss fr12,fr10,fr16,cc5,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_fr_limmed 0x3333,0x3333,fr16 + test_fr_limmed 0x4444,0x4444,fr17 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1111,0x1111,fr14 + set_fr_iimmed 0x2222,0x2222,fr15 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + cmqsubhss fr10,fr12,fr14,cc2,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + cmqsubhss fr10,fr12,fr14,cc2,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0xffff,0xffff,fr12 + set_fr_iimmed 0xfffe,0xffff,fr13 + cmqsubhss fr10,fr12,fr14,cc2,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8001,0x8001,fr11 + set_fr_iimmed 0x0001,0x0002,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqsubhss fr10,fr12,fr14,cc6,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x3333,0x3333,fr16 + set_fr_iimmed 0x4444,0x4444,fr17 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + set_fr_iimmed 0x8000,0x8000,fr12 + set_fr_iimmed 0x8000,0x8000,fr13 + cmqsubhss.p fr10,fr10,fr14,cc6,1 + cmqsubhss fr12,fr10,fr16,cc6,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_fr_limmed 0x3333,0x3333,fr16 + test_fr_limmed 0x4444,0x4444,fr17 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is set + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1111,0x1111,fr14 + set_fr_iimmed 0x2222,0x2222,fr15 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + cmqsubhss fr10,fr12,fr14,cc3,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + cmqsubhss fr10,fr12,fr14,cc3,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0xffff,0xffff,fr12 + set_fr_iimmed 0xfffe,0xffff,fr13 + cmqsubhss fr10,fr12,fr14,cc3,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8001,0x8001,fr11 + set_fr_iimmed 0x0001,0x0002,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqsubhss fr10,fr12,fr14,cc7,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x3333,0x3333,fr16 + set_fr_iimmed 0x4444,0x4444,fr17 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + set_fr_iimmed 0x8000,0x8000,fr12 + set_fr_iimmed 0x8000,0x8000,fr13 + cmqsubhss.p fr10,fr10,fr14,cc7,1 + cmqsubhss fr12,fr10,fr16,cc7,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_fr_limmed 0x3333,0x3333,fr16 + test_fr_limmed 0x4444,0x4444,fr17 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is set + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + pass diff --git a/sim/testsuite/sim/frv/fr550/cmqsubhus.cgs b/sim/testsuite/sim/frv/fr550/cmqsubhus.cgs new file mode 100644 index 0000000..90bd89a --- /dev/null +++ b/sim/testsuite/sim/frv/fr550/cmqsubhus.cgs @@ -0,0 +1,351 @@ +# frv testcase for cmqsubhus $FRi,$FRj,$FRj,$CCi,$cond +# mach: all + + .include "../testutils.inc" + + start + + .global cmqsubhus +cmqsubhus: + set_spr_immed 0x1b1b,cccr + + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0xbeef,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0x0000,fr13 + cmqsubhus fr10,fr12,fr14,cc0,1 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0xdead,0xbeef,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0x1111,0x1111,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqsubhus fr10,fr12,fr14,cc0,1 + test_fr_limmed 0x0123,0x4567,fr14 + test_fr_limmed 0x7ffc,0x7ffd,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0001,0x0001,fr11 + set_fr_iimmed 0x0001,0x0002,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqsubhus fr10,fr12,fr14,cc4,1 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0x0000,0x0000,fr15 + test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0002,fr11 + set_fr_iimmed 0x0000,0x0001,fr12 + set_fr_iimmed 0x0002,0x0003,fr13 + cmqsubhus.p fr10,fr10,fr14,cc4,1 + cmqsubhus fr10,fr12,fr16,cc4,1 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0x0000,0x0000,fr15 + test_fr_limmed 0x0001,0x0000,fr16 + test_fr_limmed 0x0000,0x0000,fr17 + test_spr_bits 0x3c,2,0x1,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0xbeef,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0x0000,fr13 + cmqsubhus fr10,fr12,fr14,cc1,0 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0xdead,0xbeef,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0x1111,0x1111,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqsubhus fr10,fr12,fr14,cc1,0 + test_fr_limmed 0x0123,0x4567,fr14 + test_fr_limmed 0x7ffc,0x7ffd,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0001,0x0001,fr11 + set_fr_iimmed 0x0001,0x0002,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqsubhus fr10,fr12,fr14,cc5,0 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0x0000,0x0000,fr15 + test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0002,fr11 + set_fr_iimmed 0x0000,0x0001,fr12 + set_fr_iimmed 0x0002,0x0003,fr13 + cmqsubhus.p fr10,fr10,fr14,cc5,0 + cmqsubhus fr10,fr12,fr16,cc5,0 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0x0000,0x0000,fr15 + test_fr_limmed 0x0001,0x0000,fr16 + test_fr_limmed 0x0000,0x0000,fr17 + test_spr_bits 0x3c,2,0x1,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_fr_iimmed 0x1111,0x1111,fr14 + set_fr_iimmed 0x2222,0x2222,fr15 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0xbeef,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0x0000,fr13 + cmqsubhus fr10,fr12,fr14,cc0,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0x1111,0x1111,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqsubhus fr10,fr12,fr14,cc0,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0001,0x0001,fr11 + set_fr_iimmed 0x0001,0x0002,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqsubhus fr10,fr12,fr14,cc4,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x3333,0x3333,fr16 + set_fr_iimmed 0x4444,0x4444,fr17 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0002,fr11 + set_fr_iimmed 0x0000,0x0001,fr12 + set_fr_iimmed 0x0002,0x0003,fr13 + cmqsubhus.p fr10,fr10,fr14,cc4,0 + cmqsubhus fr10,fr12,fr16,cc4,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_fr_limmed 0x3333,0x3333,fr16 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_fr_limmed 0x4444,0x4444,fr17 + + set_fr_iimmed 0x1111,0x1111,fr14 + set_fr_iimmed 0x2222,0x2222,fr15 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0xbeef,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0x0000,fr13 + cmqsubhus fr10,fr12,fr14,cc1,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0x1111,0x1111,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqsubhus fr10,fr12,fr14,cc1,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0001,0x0001,fr11 + set_fr_iimmed 0x0001,0x0002,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqsubhus fr10,fr12,fr14,cc5,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x3333,0x3333,fr16 + set_fr_iimmed 0x4444,0x4444,fr17 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0002,fr11 + set_fr_iimmed 0x0000,0x0001,fr12 + set_fr_iimmed 0x0002,0x0003,fr13 + cmqsubhus.p fr10,fr10,fr14,cc5,1 + cmqsubhus fr10,fr12,fr16,cc5,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_fr_limmed 0x3333,0x3333,fr16 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_fr_limmed 0x4444,0x4444,fr17 + + set_fr_iimmed 0x1111,0x1111,fr14 + set_fr_iimmed 0x2222,0x2222,fr15 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0xbeef,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0x0000,fr13 + cmqsubhus fr10,fr12,fr14,cc2,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0x1111,0x1111,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqsubhus fr10,fr12,fr14,cc2,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0001,0x0001,fr11 + set_fr_iimmed 0x0001,0x0002,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqsubhus fr10,fr12,fr14,cc6,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x3333,0x3333,fr16 + set_fr_iimmed 0x4444,0x4444,fr17 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0002,fr11 + set_fr_iimmed 0x0000,0x0001,fr12 + set_fr_iimmed 0x0002,0x0003,fr13 + cmqsubhus.p fr10,fr10,fr14,cc6,0 + cmqsubhus fr10,fr12,fr16,cc6,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_fr_limmed 0x3333,0x3333,fr16 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_fr_limmed 0x4444,0x4444,fr17 +; + set_fr_iimmed 0x1111,0x1111,fr14 + set_fr_iimmed 0x2222,0x2222,fr15 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0xbeef,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0x0000,fr13 + cmqsubhus fr10,fr12,fr14,cc3,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0x1111,0x1111,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqsubhus fr10,fr12,fr14,cc3,0 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0001,0x0001,fr11 + set_fr_iimmed 0x0001,0x0002,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + cmqsubhus fr10,fr12,fr14,cc7,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x3333,0x3333,fr16 + set_fr_iimmed 0x4444,0x4444,fr17 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0002,fr11 + set_fr_iimmed 0x0000,0x0001,fr12 + set_fr_iimmed 0x0002,0x0003,fr13 + cmqsubhus.p fr10,fr10,fr14,cc7,0 + cmqsubhus fr10,fr12,fr16,cc7,1 + test_fr_limmed 0x1111,0x1111,fr14 + test_fr_limmed 0x2222,0x2222,fr15 + test_fr_limmed 0x3333,0x3333,fr16 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_fr_limmed 0x4444,0x4444,fr17 + + pass diff --git a/sim/testsuite/sim/frv/fr550/cmsubhss.cgs b/sim/testsuite/sim/frv/fr550/cmsubhss.cgs new file mode 100644 index 0000000..9370d54 --- /dev/null +++ b/sim/testsuite/sim/frv/fr550/cmsubhss.cgs @@ -0,0 +1,547 @@ +# frv testcase for cmsubhss $FRi,$FRj,$FRj,$CCi,$cond +# mach: all + + .include "../testutils.inc" + + start + + .global cmsubhss +cmsubhss: + set_spr_immed 0x1b1b,cccr + + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmsubhss fr10,fr11,fr12,cc0,1 + test_fr_limmed 0x0000,0x0000,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + cmsubhss fr10,fr11,fr12,cc0,1 + test_fr_limmed 0xdead,0x4111,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + cmsubhss fr10,fr11,fr12,cc0,1 + test_fr_limmed 0x4111,0xdead,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmsubhss fr10,fr11,fr12,cc0,1 + test_fr_limmed 0x0123,0x4567,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + cmsubhss fr10,fr11,fr12,cc0,1 + test_fr_limmed 0x1235,0x5679,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0xfffe,0xffff,fr11 + cmsubhss fr10,fr11,fr12,cc4,1 + test_fr_limmed 0x7fff,0x7fff,fr12 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + cmsubhss fr10,fr11,fr12,cc4,1 + test_fr_limmed 0x8000,0x8000,fr12 + test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmsubhss fr10,fr11,fr12,cc4,1 + test_fr_limmed 0x8000,0x8000,fr12 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + cmsubhss.p fr10,fr10,fr12,cc4,1 + cmsubhss fr11,fr10,fr13,cc4,1 + test_fr_limmed 0x0000,0x0000,fr12 + test_fr_limmed 0x8000,0x8000,fr13 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmsubhss fr10,fr11,fr12,cc1,0 + test_fr_limmed 0x0000,0x0000,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + cmsubhss fr10,fr11,fr12,cc1,0 + test_fr_limmed 0xdead,0x4111,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + cmsubhss fr10,fr11,fr12,cc1,0 + test_fr_limmed 0x4111,0xdead,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmsubhss fr10,fr11,fr12,cc1,0 + test_fr_limmed 0x0123,0x4567,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + cmsubhss fr10,fr11,fr12,cc1,0 + test_fr_limmed 0x1235,0x5679,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0xfffe,0xffff,fr11 + cmsubhss fr10,fr11,fr12,cc5,0 + test_fr_limmed 0x7fff,0x7fff,fr12 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + cmsubhss fr10,fr11,fr12,cc5,0 + test_fr_limmed 0x8000,0x8000,fr12 + test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmsubhss fr10,fr11,fr12,cc5,0 + test_fr_limmed 0x8000,0x8000,fr12 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + cmsubhss.p fr10,fr10,fr12,cc5,0 + cmsubhss fr11,fr10,fr13,cc5,0 + test_fr_limmed 0x0000,0x0000,fr12 + test_fr_limmed 0x8000,0x8000,fr13 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_fr_iimmed 0xdead,0xbeef,fr12 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmsubhss fr10,fr11,fr12,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + cmsubhss fr10,fr11,fr12,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + cmsubhss fr10,fr11,fr12,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmsubhss fr10,fr11,fr12,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + cmsubhss fr10,fr11,fr12,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0xfffe,0xffff,fr11 + cmsubhss fr10,fr11,fr12,cc4,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + cmsubhss fr10,fr11,fr12,cc4,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmsubhss fr10,fr11,fr12,cc4,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xbeef,0xdead,fr13 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + cmsubhss.p fr10,fr10,fr12,cc4,0 + cmsubhss fr11,fr10,fr13,cc4,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_fr_limmed 0xbeef,0xdead,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xdead,0xbeef,fr12 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmsubhss fr10,fr11,fr12,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + cmsubhss fr10,fr11,fr12,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + cmsubhss fr10,fr11,fr12,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmsubhss fr10,fr11,fr12,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + cmsubhss fr10,fr11,fr12,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0xfffe,0xffff,fr11 + cmsubhss fr10,fr11,fr12,cc5,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + cmsubhss fr10,fr11,fr12,cc5,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmsubhss fr10,fr11,fr12,cc5,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xbeef,0xdead,fr13 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + cmsubhss.p fr10,fr10,fr12,cc5,1 + cmsubhss fr11,fr10,fr13,cc5,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_fr_limmed 0xbeef,0xdead,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xdead,0xbeef,fr12 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmsubhss fr10,fr11,fr12,cc2,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + cmsubhss fr10,fr11,fr12,cc2,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + cmsubhss fr10,fr11,fr12,cc2,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmsubhss fr10,fr11,fr12,cc2,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + cmsubhss fr10,fr11,fr12,cc2,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0xfffe,0xffff,fr11 + cmsubhss fr10,fr11,fr12,cc6,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + cmsubhss fr10,fr11,fr12,cc6,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmsubhss fr10,fr11,fr12,cc6,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xbeef,0xdead,fr13 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + cmsubhss.p fr10,fr10,fr12,cc6,1 + cmsubhss fr11,fr10,fr13,cc6,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_fr_limmed 0xbeef,0xdead,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set +; + set_fr_iimmed 0xdead,0xbeef,fr12 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmsubhss fr10,fr11,fr12,cc3,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + cmsubhss fr10,fr11,fr12,cc3,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + cmsubhss fr10,fr11,fr12,cc3,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmsubhss fr10,fr11,fr12,cc3,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + cmsubhss fr10,fr11,fr12,cc3,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0xfffe,0xffff,fr11 + cmsubhss fr10,fr11,fr12,cc7,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + cmsubhss fr10,fr11,fr12,cc7,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmsubhss fr10,fr11,fr12,cc7,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xbeef,0xdead,fr13 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + cmsubhss.p fr10,fr10,fr12,cc7,1 + cmsubhss fr11,fr10,fr13,cc7,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_fr_limmed 0xbeef,0xdead,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + pass diff --git a/sim/testsuite/sim/frv/fr550/cmsubhus.cgs b/sim/testsuite/sim/frv/fr550/cmsubhus.cgs new file mode 100644 index 0000000..5cf676b --- /dev/null +++ b/sim/testsuite/sim/frv/fr550/cmsubhus.cgs @@ -0,0 +1,427 @@ +# frv testcase for cmsubhus $FRi,$FRj,$FRj,$CCi,$cond +# mach: all + + .include "../testutils.inc" + + start + + .global cmsubhus +cmsubhus: + set_spr_immed 0x1b1b,cccr + + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmsubhus fr10,fr11,fr12,cc0,1 + test_fr_limmed 0x0000,0x0000,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xdead,0xbeef,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmsubhus fr10,fr11,fr12,cc0,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmsubhus fr10,fr11,fr12,cc0,1 + test_fr_limmed 0x0123,0x4567,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmsubhus fr10,fr11,fr12,cc0,1 + test_fr_limmed 0x7ffc,0x7ffd,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + cmsubhus fr10,fr11,fr12,cc4,1 + test_fr_limmed 0x0000,0x0000,fr12 + test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmsubhus fr10,fr11,fr12,cc4,1 + test_fr_limmed 0x0000,0x0000,fr12 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0002,fr11 + cmsubhus.p fr10,fr10,fr12,cc4,1 + cmsubhus fr10,fr11,fr13,cc4,1 + test_fr_limmed 0x0000,0x0000,fr12 + test_fr_limmed 0x0000,0x0000,fr13 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmsubhus fr10,fr11,fr12,cc1,0 + test_fr_limmed 0x0000,0x0000,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xdead,0xbeef,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmsubhus fr10,fr11,fr12,cc1,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmsubhus fr10,fr11,fr12,cc1,0 + test_fr_limmed 0x0123,0x4567,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmsubhus fr10,fr11,fr12,cc1,0 + test_fr_limmed 0x7ffc,0x7ffd,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + cmsubhus fr10,fr11,fr12,cc5,0 + test_fr_limmed 0x0000,0x0000,fr12 + test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmsubhus fr10,fr11,fr12,cc5,0 + test_fr_limmed 0x0000,0x0000,fr12 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0002,fr11 + cmsubhus.p fr10,fr10,fr12,cc5,0 + cmsubhus fr10,fr11,fr13,cc5,0 + test_fr_limmed 0x0000,0x0000,fr12 + test_fr_limmed 0x0000,0x0000,fr13 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_fr_iimmed 0xdead,0xbeef,fr12 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmsubhus fr10,fr11,fr12,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xbeef,0xdead,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmsubhus fr10,fr11,fr12,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmsubhus fr10,fr11,fr12,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmsubhus fr10,fr11,fr12,cc0,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + cmsubhus fr10,fr11,fr12,cc4,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmsubhus fr10,fr11,fr12,cc4,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xbeef,0xdead,fr13 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0002,fr11 + cmsubhus.p fr10,fr10,fr12,cc4,0 + cmsubhus fr10,fr11,fr13,cc4,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_fr_limmed 0xbeef,0xdead,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xdead,0xbeef,fr12 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmsubhus fr10,fr11,fr12,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xbeef,0xdead,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmsubhus fr10,fr11,fr12,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmsubhus fr10,fr11,fr12,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmsubhus fr10,fr11,fr12,cc1,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + cmsubhus fr10,fr11,fr12,cc5,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmsubhus fr10,fr11,fr12,cc5,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xbeef,0xdead,fr13 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0002,fr11 + cmsubhus.p fr10,fr10,fr12,cc5,1 + cmsubhus fr10,fr11,fr13,cc5,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_fr_limmed 0xbeef,0xdead,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xdead,0xbeef,fr12 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmsubhus fr10,fr11,fr12,cc2,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xbeef,0xdead,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmsubhus fr10,fr11,fr12,cc2,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmsubhus fr10,fr11,fr12,cc2,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmsubhus fr10,fr11,fr12,cc2,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + cmsubhus fr10,fr11,fr12,cc6,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmsubhus fr10,fr11,fr12,cc6,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xbeef,0xdead,fr13 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0002,fr11 + cmsubhus.p fr10,fr10,fr12,cc6,0 + cmsubhus fr10,fr11,fr13,cc6,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_fr_limmed 0xbeef,0xdead,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set +; + set_fr_iimmed 0xdead,0xbeef,fr12 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmsubhus fr10,fr11,fr12,cc3,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xbeef,0xdead,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + cmsubhus fr10,fr11,fr12,cc3,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + cmsubhus fr10,fr11,fr12,cc3,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmsubhus fr10,fr11,fr12,cc3,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + cmsubhus fr10,fr11,fr12,cc7,0 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + cmsubhus fr10,fr11,fr12,cc7,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xbeef,0xdead,fr13 + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0002,fr11 + cmsubhus.p fr10,fr10,fr12,cc7,0 + cmsubhus fr10,fr11,fr13,cc7,1 + test_fr_limmed 0xdead,0xbeef,fr12 + test_fr_limmed 0xbeef,0xdead,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + pass diff --git a/sim/testsuite/sim/frv/fr550/dcpl.cgs b/sim/testsuite/sim/frv/fr550/dcpl.cgs new file mode 100644 index 0000000..93c659a --- /dev/null +++ b/sim/testsuite/sim/frv/fr550/dcpl.cgs @@ -0,0 +1,65 @@ +# FRV testcase for dcpl GRi,GRj,lock +# mach: all + + .include "../testutils.inc" + + start + + .global dcpl +dcpl: + or_spr_immed 0xc8000000,hsr0 ; caches enabled -- copy-back mode + + ; preload and lock all the lines in set 0 of the data cache + set_gr_immed 0x70000,gr10 + dcpl gr10,gr0,1 + set_mem_immed 0x11111111,gr10 + test_mem_immed 0x11111111,gr10 + + inc_gr_immed 0x2000,gr10 + set_gr_immed 1,gr11 + dcpl gr10,gr11,1 + set_mem_immed 0x22222222,gr10 + test_mem_immed 0x22222222,gr10 + + inc_gr_immed 0x2000,gr10 + set_gr_immed 63,gr11 + dcpl gr10,gr11,1 + set_mem_immed 0x33333333,gr10 + test_mem_immed 0x33333333,gr10 + + inc_gr_immed 0x2000,gr10 + set_gr_immed 64,gr11 + dcpl gr10,gr11,1 + set_mem_immed 0x44444444,gr10 + test_mem_immed 0x44444444,gr10 + + ; Now write to another address which should be in the same set + ; the write should go through to memory, since all the lines in the + ; set are locked + inc_gr_immed 0x2000,gr10 + set_mem_immed 0xdeadbeef,gr10 + test_mem_immed 0xdeadbeef,gr10 + + ; Invalidate the data cache. Only the last value stored should have made + ; it through to memory + set_gr_immed 0x70000,gr10 + invalidate_data_cache gr10 + test_mem_immed 0,gr10 + + inc_gr_immed 0x2000,gr10 + invalidate_data_cache gr10 + test_mem_immed 0,gr10 + + inc_gr_immed 0x2000,gr10 + invalidate_data_cache gr10 + test_mem_immed 0,gr10 + + inc_gr_immed 0x2000,gr10 + invalidate_data_cache gr10 + test_mem_immed 0,gr10 + + inc_gr_immed 0x2000,gr10 + invalidate_data_cache gr10 + test_mem_immed 0xdeadbeef,gr10 + + pass diff --git a/sim/testsuite/sim/frv/fr550/dcul.cgs b/sim/testsuite/sim/frv/fr550/dcul.cgs new file mode 100644 index 0000000..a3bd4be --- /dev/null +++ b/sim/testsuite/sim/frv/fr550/dcul.cgs @@ -0,0 +1,118 @@ +# FRV testcase for dcul GRi +# mach: all + + .include "../testutils.inc" + + start + + .global dcul +dcul: + or_spr_immed 0xc8000000,hsr0 ; caches enabled -- copy-back mode + + ; preload and lock all the lines in set 0 of the data cache + set_gr_immed 0x70000,gr10 + lock_data_cache gr10 + set_mem_immed 0x11111111,gr10 + test_mem_immed 0x11111111,gr10 + + inc_gr_immed 0x2000,gr10 + set_gr_immed 1,gr11 + lock_data_cache gr10 + set_mem_immed 0x22222222,gr10 + test_mem_immed 0x22222222,gr10 + + inc_gr_immed 0x2000,gr10 + set_gr_immed 63,gr11 + lock_data_cache gr10 + set_mem_immed 0x33333333,gr10 + test_mem_immed 0x33333333,gr10 + + inc_gr_immed 0x2000,gr10 + set_gr_immed 64,gr11 + lock_data_cache gr10 + set_mem_immed 0x44444444,gr10 + test_mem_immed 0x44444444,gr10 + + ; Now write to another address which should be in the same set + ; the write should go through to memory, since all the lines in the + ; set are locked + inc_gr_immed 0x2000,gr10 + set_mem_immed 0xdeadbeef,gr10 + test_mem_immed 0xdeadbeef,gr10 + + ; Invalidate the data cache. Only the last value stored should have made + ; it through to memory + set_gr_immed 0x70000,gr10 + invalidate_data_cache gr10 + test_mem_immed 0,gr10 + + inc_gr_immed 0x2000,gr10 + invalidate_data_cache gr10 + test_mem_immed 0,gr10 + + inc_gr_immed 0x2000,gr10 + invalidate_data_cache gr10 + test_mem_immed 0,gr10 + + inc_gr_immed 0x2000,gr10 + invalidate_data_cache gr10 + test_mem_immed 0,gr10 + + inc_gr_immed 0x2000,gr10 + invalidate_data_cache gr10 + test_mem_immed 0xdeadbeef,gr10 + + ; Now preload load and lock all the lines in set 0 of the data cache + ; again + set_gr_immed 0x70000,gr10 + lock_data_cache gr10 + set_mem_immed 0x11111111,gr10 + test_mem_immed 0x11111111,gr10 + + inc_gr_immed 0x2000,gr10 + set_gr_immed 1,gr11 + lock_data_cache gr10 + set_mem_immed 0x22222222,gr10 + test_mem_immed 0x22222222,gr10 + + inc_gr_immed 0x2000,gr10 + set_gr_immed 63,gr11 + lock_data_cache gr10 + set_mem_immed 0x33333333,gr10 + test_mem_immed 0x33333333,gr10 + + inc_gr_immed 0x2000,gr10 + set_gr_immed 64,gr11 + lock_data_cache gr10 + set_mem_immed 0x44444444,gr10 + test_mem_immed 0x44444444,gr10 + + ; unlock one line + set_gr_immed 0x78000,gr10 + dcul gr10 + + ; Now write to another address which should be in the same set. + set_gr_immed 0x7a000,gr10 + set_mem_immed 0xbeefdead,gr10 + + ; All of the stored values should be retrievable + + set_gr_immed 0x70000,gr10 + test_mem_immed 0x11111111,gr10 + + inc_gr_immed 0x2000,gr10 + test_mem_immed 0x22222222,gr10 + + inc_gr_immed 0x2000,gr10 + test_mem_immed 0x33333333,gr10 + + inc_gr_immed 0x2000,gr10 + test_mem_immed 0x44444444,gr10 + + inc_gr_immed 0x2000,gr10 + test_mem_immed 0xdeadbeef,gr10 + + inc_gr_immed 0x2000,gr10 + test_mem_immed 0xbeefdead,gr10 + + pass diff --git a/sim/testsuite/sim/frv/fr550/mabshs.cgs b/sim/testsuite/sim/frv/fr550/mabshs.cgs new file mode 100644 index 0000000..9168df8 --- /dev/null +++ b/sim/testsuite/sim/frv/fr550/mabshs.cgs @@ -0,0 +1,64 @@ +# frv testcase for mabshs $FRj,$FRk +# mach: all + + .include "../testutils.inc" + + start + + .global mabshs +mabshs: + set_fr_iimmed 0x0000,0x0000,fr10 + mabshs fr10,fr11 + test_fr_limmed 0x0000,0x0000,fr11 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0001,0xffff,fr10 + mabshs fr10,fr11 + test_fr_limmed 0x0001,0x0001,fr11 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x7fff,0x8001,fr10 + mabshs fr10,fr11 + test_fr_limmed 0x7fff,0x7fff,fr11 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x7fff,0x8000,fr10 + mabshs fr10,fr11 + test_fr_limmed 0x7fff,0x7fff,fr11 + test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8000,0x7fff,fr10 + mabshs fr10,fr11 + test_fr_limmed 0x7fff,0x7fff,fr11 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x7fff,0x8000,fr10 + set_fr_iimmed 0x8000,0x7fff,fr11 + mabshs.p fr10,fr12 + mabshs fr11,fr13 + test_fr_limmed 0x7fff,0x7fff,fr12 + test_fr_limmed 0x7fff,0x7fff,fr13 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + pass diff --git a/sim/testsuite/sim/frv/fr550/maddaccs.cgs b/sim/testsuite/sim/frv/fr550/maddaccs.cgs new file mode 100644 index 0000000..262a148 --- /dev/null +++ b/sim/testsuite/sim/frv/fr550/maddaccs.cgs @@ -0,0 +1,128 @@ +# frv testcase for maddaccs $ACC40Si,$ACC40Sk +# mach: all + + .include "../testutils.inc" + + start + + .global maddaccs +maddaccs: + set_accg_immed 0,accg0 + set_acc_immed 0x00000000,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x00000000,acc1 + maddaccs acc0,acc3 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x0000,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0xdead0000,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x0000beef,acc1 + maddaccs acc0,acc3 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg3 + test_acc_limmed 0xdead,0xbeef,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x0000dead,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0xbeef0000,acc1 + maddaccs acc0,acc3 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg3 + test_acc_limmed 0xbeef,0xdead,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x12345678,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x11111111,acc1 + maddaccs acc0,acc3 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg3 + test_acc_limmed 0x2345,0x6789,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x12345678,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0xffffffff,acc1 + maddaccs acc0,acc3 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 1,accg3 + test_acc_limmed 0x1234,0x5677,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x12345678,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xffffffff,acc1 + maddaccs acc0,acc3 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg3 + test_acc_limmed 0x1234,0x5677,acc3 + + set_spr_immed 0,msr0 + set_accg_immed 0x7f,accg0 + set_acc_immed 0xfffe7ffe,acc0 + set_accg_immed 0x0,accg1 + set_acc_immed 0x00020001,acc1 + maddaccs acc0,acc3 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + test_accg_immed 0x7f,accg3 + test_acc_limmed 0xffff,0xffff,acc3 + + set_spr_immed 0,msr0 + set_accg_immed 0x80,accg0 + set_acc_immed 0x00000001,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xfffffffe,acc1 + maddaccs acc0,acc3 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + test_accg_immed 0x80,accg3 + test_acc_limmed 0x0000,0x0000,acc3 + + set_spr_immed 0,msr0 + set_accg_immed 0,accg0 + set_acc_immed 0x00000001,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x00000001,acc1 + set_accg_immed 0,accg4 + set_acc_immed 0x00000001,acc4 + set_accg_immed 0x7f,accg5 + set_acc_immed 0xffffffff,acc5 + maddaccs.p acc0,acc1 + maddaccs acc4,acc5 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x0002,acc1 + test_accg_immed 0x7f,accg5 + test_acc_limmed 0xffff,0xffff,acc5 + + pass diff --git a/sim/testsuite/sim/frv/fr550/maddhss.cgs b/sim/testsuite/sim/frv/fr550/maddhss.cgs new file mode 100644 index 0000000..8c5c714 --- /dev/null +++ b/sim/testsuite/sim/frv/fr550/maddhss.cgs @@ -0,0 +1,97 @@ +# frv testcase for maddhss $FRi,$FRj,$FRj +# mach: all + + .include "../testutils.inc" + + start + + .global maddhss +maddhss: + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + maddhss fr10,fr11,fr12 + test_fr_limmed 0x0000,0x0000,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + maddhss fr10,fr11,fr12 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + maddhss fr10,fr11,fr12 + test_fr_limmed 0xbeef,0xdead,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + maddhss fr10,fr11,fr12 + test_fr_limmed 0x2345,0x6789,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + maddhss fr10,fr11,fr12 + test_fr_limmed 0x1233,0x5677,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + maddhss fr10,fr11,fr12 + test_fr_limmed 0x7fff,0x7fff,fr12 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xffff,0xfffe,fr11 + maddhss fr10,fr11,fr12 + test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set + test_fr_limmed 0x8000,0x8000,fr12 + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + maddhss fr10,fr11,fr12 + test_fr_limmed 0x8000,0x8000,fr12 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + maddhss.p fr10,fr10,fr12 + maddhss fr11,fr11,fr13 + test_fr_limmed 0x0002,0x0002,fr12 + test_fr_limmed 0x7fff,0x7fff,fr13 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + pass diff --git a/sim/testsuite/sim/frv/fr550/maddhus.cgs b/sim/testsuite/sim/frv/fr550/maddhus.cgs new file mode 100644 index 0000000..93d06bd --- /dev/null +++ b/sim/testsuite/sim/frv/fr550/maddhus.cgs @@ -0,0 +1,86 @@ +# frv testcase for maddhus $FRi,$FRj,$FRj +# mach: all + + .include "../testutils.inc" + + start + + .global maddhus +maddhus: + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + maddhus fr10,fr11,fr12 + test_fr_limmed 0x0000,0x0000,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + maddhus fr10,fr11,fr12 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + maddhus fr10,fr11,fr12 + test_fr_limmed 0xbeef,0xdead,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + maddhus fr10,fr11,fr12 + test_fr_limmed 0x2345,0x6789,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + maddhus fr10,fr11,fr12 + test_fr_limmed 0x8000,0x7fff,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xfffe,0xfffe,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + maddhus fr10,fr11,fr12 + test_fr_limmed 0xffff,0xffff,fr12 + test_spr_bits 0x3c,2,4,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0002,0x0001,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + maddhus fr10,fr11,fr12 + test_fr_limmed 0xffff,0xffff,fr12 + test_spr_bits 0x3c,2,8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + maddhus.p fr10,fr10,fr12 + maddhus fr11,fr11,fr13 + test_fr_limmed 0x0002,0x0002,fr12 + test_fr_limmed 0xffff,0xffff,fr13 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + pass diff --git a/sim/testsuite/sim/frv/fr550/masaccs.cgs b/sim/testsuite/sim/frv/fr550/masaccs.cgs new file mode 100644 index 0000000..9595d16 --- /dev/null +++ b/sim/testsuite/sim/frv/fr550/masaccs.cgs @@ -0,0 +1,148 @@ +# frv testcase for masaccs $ACC40Si,$ACC40Sk +# mach: all + + .include "../testutils.inc" + + start + + .global masaccs +masaccs: + set_accg_immed 0,accg0 + set_acc_immed 0x00000000,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x00000000,acc1 + masaccs acc0,acc2 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msro.mtt always set + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x0000,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x0000,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0xdead0000,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x0000beef,acc1 + masaccs acc0,acc2 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msro.mtt always set + test_accg_immed 0,accg2 + test_acc_limmed 0xdead,0xbeef,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0xdeac,0x4111,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x0000dead,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0xbeef0000,acc1 + masaccs acc0,acc2 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msro.mtt always set + test_accg_immed 0,accg2 + test_acc_limmed 0xbeef,0xdead,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0x4111,0xdead,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x12345678,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x11111111,acc1 + masaccs acc0,acc2 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msro.mtt always set + test_accg_immed 0,accg2 + test_acc_limmed 0x2345,0x6789,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0123,0x4567,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x12345678,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0xffffffff,acc1 + masaccs acc0,acc2 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msro.mtt always set + test_accg_immed 1,accg2 + test_acc_limmed 0x1234,0x5677,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0x1234,0x5679,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x12345678,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xffffffff,acc1 + masaccs acc0,acc2 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msro.mtt always set + test_accg_immed 0,accg2 + test_acc_limmed 0x1234,0x5677,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x1234,0x5679,acc3 + + set_spr_immed 0,msr0 + set_accg_immed 0x7f,accg0 + set_acc_immed 0xfffe7ffe,acc0 + set_accg_immed 0x0,accg1 + set_acc_immed 0x00020001,acc1 + masaccs acc0,acc2 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + test_accg_immed 0x7f,accg2 + test_acc_limmed 0xffff,0xffff,acc2 + test_accg_immed 0x7f,accg3 + test_acc_limmed 0xfffc,0x7ffd,acc3 + + set_spr_immed 0,msr0 + set_accg_immed 0x80,accg0 + set_acc_immed 0x00000001,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xfffffffe,acc1 + masaccs acc0,acc2 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + test_accg_immed 0x80,accg2 + test_acc_limmed 0x0000,0x0000,acc2 + test_accg_immed 0x80,accg3 + test_acc_limmed 0x0000,0x0003,acc3 + + set_spr_immed 0,msr0 + set_accg_immed 0,accg0 + set_acc_immed 0x00000001,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x00000001,acc1 + set_accg_immed 0,accg4 + set_acc_immed 0x00000001,acc4 + set_accg_immed 0x7f,accg5 + set_acc_immed 0xffffffff,acc5 + masaccs.p acc0,acc0 + masaccs acc4,acc4 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x0002,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x0000,acc1 + test_accg_immed 0x7f,accg4 + test_acc_limmed 0xffff,0xffff,acc4 + test_accg_immed 0x80,accg5 + test_acc_limmed 0x0000,0x0002,acc5 + + pass diff --git a/sim/testsuite/sim/frv/fr550/mdaddaccs.cgs b/sim/testsuite/sim/frv/fr550/mdaddaccs.cgs new file mode 100644 index 0000000..92d23d0 --- /dev/null +++ b/sim/testsuite/sim/frv/fr550/mdaddaccs.cgs @@ -0,0 +1,102 @@ +# frv testcase for mdaddaccs $ACC40Si,$ACC40Sk +# mach: all + + .include "../testutils.inc" + + start + + .global mdaddaccs +mdaddaccs: + set_accg_immed 0,accg0 + set_acc_immed 0x00000000,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x00000000,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0xdead0000,acc2 + set_accg_immed 0,accg3 + set_acc_immed 0x0000beef,acc3 + mdaddaccs acc0,acc2 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x0000,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0xdead,0xbeef,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x0000dead,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0xbeef0000,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0x12345678,acc2 + set_accg_immed 0,accg3 + set_acc_immed 0x11111111,acc3 + mdaddaccs acc0,acc2 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg2 + test_acc_limmed 0xbeef,0xdead,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x2345,0x6789,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x12345678,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0xffffffff,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0x12345678,acc2 + set_accg_immed 0xff,accg3 + set_acc_immed 0xffffffff,acc3 + mdaddaccs acc0,acc2 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 1,accg2 + test_acc_limmed 0x1234,0x5677,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x1234,0x5677,acc3 + + set_spr_immed 0,msr0 + set_accg_immed 0x7f,accg0 + set_acc_immed 0xfffe7ffe,acc0 + set_accg_immed 0x0,accg1 + set_acc_immed 0x00020001,acc1 + set_accg_immed 0x80,accg2 + set_acc_immed 0x00000001,acc2 + set_accg_immed 0xff,accg3 + set_acc_immed 0xfffffffe,acc3 + mdaddaccs acc0,acc2 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + test_accg_immed 0x7f,accg2 + test_acc_limmed 0xffff,0xffff,acc2 + test_accg_immed 0x80,accg3 + test_acc_limmed 0x0000,0x0000,acc3 + + set_spr_immed 0,msr0 + set_accg_immed 0,accg0 + set_acc_immed 0x00000001,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x00000001,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0x00000001,acc2 + set_accg_immed 0x7f,accg3 + set_acc_immed 0xffffffff,acc3 + mdaddaccs acc0,acc2 + test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x0002,acc2 + test_accg_immed 0x7f,accg3 + test_acc_limmed 0xffff,0xffff,acc3 + + pass diff --git a/sim/testsuite/sim/frv/fr550/mdasaccs.cgs b/sim/testsuite/sim/frv/fr550/mdasaccs.cgs new file mode 100644 index 0000000..8821621 --- /dev/null +++ b/sim/testsuite/sim/frv/fr550/mdasaccs.cgs @@ -0,0 +1,122 @@ +# frv testcase for mdasaccs $ACC40Si,$ACC40Sk +# mach: all + + .include "../testutils.inc" + + start + + .global mdasaccs +mdasaccs: + set_accg_immed 0,accg0 + set_acc_immed 0x00000000,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x00000000,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0xdead0000,acc2 + set_accg_immed 0,accg3 + set_acc_immed 0x0000beef,acc3 + mdasaccs acc0,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x0000,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x0000,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0xdead,0xbeef,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0xdeac,0x4111,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x0000dead,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0xbeef0000,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0x12345678,acc2 + set_accg_immed 0,accg3 + set_acc_immed 0x11111111,acc3 + mdasaccs acc0,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0xbeef,0xdead,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0x4111,0xdead,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x2345,0x6789,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0123,0x4567,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x12345678,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0xffffffff,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0x12345678,acc2 + set_accg_immed 0xff,accg3 + set_acc_immed 0xffffffff,acc3 + mdasaccs acc0,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 1,accg0 + test_acc_limmed 0x1234,0x5677,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0x1234,0x5679,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x1234,0x5677,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x1234,0x5679,acc3 + + set_spr_immed 0,msr0 + set_accg_immed 0x7f,accg0 + set_acc_immed 0xfffe7ffe,acc0 + set_accg_immed 0x0,accg1 + set_acc_immed 0x00020001,acc1 + set_accg_immed 0x80,accg2 + set_acc_immed 0x00000001,acc2 + set_accg_immed 0xff,accg3 + set_acc_immed 0xfffffffe,acc3 + mdasaccs acc0,acc0 + test_spr_bits 0x3c,2,0xa,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xfffc,0x7ffd,acc1 + test_accg_immed 0x80,accg2 + test_acc_limmed 0x0000,0x0000,acc2 + test_accg_immed 0x80,accg3 + test_acc_limmed 0x0000,0x0003,acc3 + + set_spr_immed 0,msr0 + set_accg_immed 0,accg0 + set_acc_immed 0x00000001,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x00000001,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0x00000001,acc2 + set_accg_immed 0x7f,accg3 + set_acc_immed 0xffffffff,acc3 + mdasaccs acc0,acc0 + test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x0002,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x0000,acc1 + test_accg_immed 0x7f,accg2 + test_acc_limmed 0xffff,0xffff,acc2 + test_accg_immed 0x80,accg3 + test_acc_limmed 0x0000,0x0002,acc3 + + pass diff --git a/sim/testsuite/sim/frv/fr550/mdsubaccs.cgs b/sim/testsuite/sim/frv/fr550/mdsubaccs.cgs new file mode 100644 index 0000000..1fe7498 --- /dev/null +++ b/sim/testsuite/sim/frv/fr550/mdsubaccs.cgs @@ -0,0 +1,102 @@ +# frv testcase for mdsubaccs $ACC40Si,$ACC40Sk +# mach: all + + .include "../testutils.inc" + + start + + .global mdsubaccs +mdsubaccs: + set_accg_immed 0,accg0 + set_acc_immed 0x00000000,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x00000000,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0xdead0000,acc2 + set_accg_immed 0,accg3 + set_acc_immed 0x0000beef,acc3 + mdsubaccs acc0,acc2 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x0000,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0xdeac,0x4111,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x0000dead,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0xbeef0000,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0x12345678,acc2 + set_accg_immed 0,accg3 + set_acc_immed 0x11111111,acc3 + mdsubaccs acc0,acc2 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0xff,accg2 + test_acc_limmed 0x4111,0xdead,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0123,0x4567,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x12345678,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0xffffffff,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0x12345678,acc2 + set_accg_immed 0xff,accg3 + set_acc_immed 0xffffffff,acc3 + mdsubaccs acc0,acc2 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0xff,accg2 + test_acc_limmed 0x1234,0x5679,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x1234,0x5679,acc3 + + set_spr_immed 0,msr0 + set_accg_immed 0x7f,accg0 + set_acc_immed 0xfffffffe,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xfffffffe,acc1 + set_accg_immed 0x80,accg2 + set_acc_immed 0x00000001,acc2 + set_accg_immed 0,accg3 + set_acc_immed 0x00000002,acc3 + mdsubaccs acc0,acc2 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + test_accg_immed 0x7f,accg2 + test_acc_limmed 0xffff,0xffff,acc2 + test_accg_immed 0x80,accg3 + test_acc_limmed 0x0000,0x0000,acc3 + + set_spr_immed 0,msr0 + set_accg_immed 0,accg0 + set_acc_immed 0x00000001,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x00000001,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0x00000001,acc2 + set_accg_immed 0x80,accg3 + set_acc_immed 0x00000000,acc3 + mdsubaccs acc0,acc2 + test_spr_bits 0x3c,2,4,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x0000,acc2 + test_accg_immed 0x7f,accg3 + test_acc_limmed 0xffff,0xffff,acc3 + + pass diff --git a/sim/testsuite/sim/frv/fr550/mmachs.cgs b/sim/testsuite/sim/frv/fr550/mmachs.cgs new file mode 100644 index 0000000..9014076 --- /dev/null +++ b/sim/testsuite/sim/frv/fr550/mmachs.cgs @@ -0,0 +1,259 @@ +# frv testcase for mmachs $GRi,$GRj,$ACCk +# mach: all + + .include "../testutils.inc" + + start + + .global mmachs +mmachs: + ; Positive operands + set_fr_iimmed 2,3,fr7 ; multiply small numbers + set_fr_iimmed 3,2,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + + set_fr_iimmed 0,1,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,2,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 8,acc0 + test_accg_immed 0,accg1 + test_acc_immed 8,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0,0x8006,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0,0x8006,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x0001,0x0006,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0001,0x0006,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x4000,0x0007,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x4000,0x0007,acc1 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x4000,0x0001,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x4000,0x0001,acc1 + + set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0xffff,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0xffff,acc1 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0xffff,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0xffff,acc1 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0xbffd,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0xbffd,acc1 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0x3ffd,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0x3ffd,acc1 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xbffd,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xbffd,acc1 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xc003,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xc003,acc1 + + set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xc005,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xc005,acc1 + + set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0x3ffec006,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3ffec006,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0x7ffec006,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x7ffec006,acc1 + + set_accg_immed 0x7f,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0x7f,accg1 + set_acc_immed 0xffffffff,acc1 + set_fr_iimmed 1,1,fr7 + set_fr_iimmed 1,1,fr8 + mmachs fr7,fr8,acc0 + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + + set_accg_immed 0x80,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed 0x80,accg1 + set_acc_immed 0,acc1 + set_fr_iimmed 0xffff,0,fr7 + set_fr_iimmed 1,0xffff,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x80,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x0000,0x8000,fr7 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x80,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + + pass + + diff --git a/sim/testsuite/sim/frv/fr550/mmachu.cgs b/sim/testsuite/sim/frv/fr550/mmachu.cgs new file mode 100644 index 0000000..cd5c03c --- /dev/null +++ b/sim/testsuite/sim/frv/fr550/mmachu.cgs @@ -0,0 +1,146 @@ +# frv testcase for mmachu $GRi,$GRj,$GRk +# mach: all + + .include "../testutils.inc" + + start + + .global mmachu +mmachu: + set_fr_iimmed 3,2,fr7 ; multiply small numbers + set_fr_iimmed 2,3,fr8 + mmachu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 2,1,fr8 + mmachu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 8,acc0 + test_accg_immed 0,accg1 + test_acc_immed 8,acc1 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + mmachu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 8,acc0 + test_accg_immed 0,accg1 + test_acc_immed 8,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + mmachu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8006,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8006,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + mmachu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x0001,0x0006,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0001,0x0006,acc1 + + set_fr_iimmed 0x8000,2,fr7 ; 17 bit result + set_fr_iimmed 2,0x8000,fr8 + mmachu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0x00020006,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x00020006,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + mmachu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0x40010007,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x40010007,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + mmachu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x8001,0x0007,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x8001,0x0007,acc1 + + set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + mmachu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 1,accg0 + test_acc_limmed 0x7fff,0x0008,acc0 + test_accg_immed 1,accg1 + test_acc_limmed 0x7fff,0x0008,acc1 + + set_accg_immed 0xff,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xffffffff,acc1 + set_fr_iimmed 1,1,fr7 + set_fr_iimmed 1,1,fr8 + mmachu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + + set_fr_iimmed 0xffff,0x0000,fr7 + set_fr_iimmed 0xffff,0xffff,fr8 + mmachu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + + pass diff --git a/sim/testsuite/sim/frv/fr550/mmrdhs.cgs b/sim/testsuite/sim/frv/fr550/mmrdhs.cgs new file mode 100644 index 0000000..1aeb1b5 --- /dev/null +++ b/sim/testsuite/sim/frv/fr550/mmrdhs.cgs @@ -0,0 +1,263 @@ +# frv testcase for mmrdhs $GRi,$GRj,$ACCk +# mach: all + + .include "../testutils.inc" + + start + + .global mmrdhs +mmrdhs: + ; Positive operands + set_fr_iimmed 2,3,fr7 ; multiply small numbers + set_fr_iimmed 3,2,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0xff,accg0 + test_acc_immed -6,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed -6,acc1 + + set_fr_iimmed 0,1,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0xff,accg0 + test_acc_immed -6,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed -6,acc1 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,2,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0xff,accg0 + test_acc_immed -8,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed -8,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0x7ffa,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0x7ffa,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xfffe,0xfffa,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xfffe,0xfffa,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xbfff,0xfff9,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xbfff,0xfff9,acc1 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xbfff,0xffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xbfff,0xffff,acc1 + + set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xc000,0x0001,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xc000,0x0001,acc1 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xc000,0x0001,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xc000,0x0001,acc1 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xc000,0x4003,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xc000,0x4003,acc1 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xc000,0xc003,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xc000,0xc003,acc1 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x4003,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x4003,acc1 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x3ffd,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x3ffd,acc1 + + set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x3ffb,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x3ffb,acc1 + + set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0xff,accg0 + test_acc_immed 0xc0013ffa,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed 0xc0013ffa,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0xff,accg0 + test_acc_immed 0x80013ffa,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed 0x80013ffa,acc1 + + set_accg_immed 0x7f,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0x7f,accg1 + set_acc_immed 0xffffffff,acc1 + set_fr_iimmed 0xffff,1,fr7 + set_fr_iimmed 1,0xffff,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + + set_fr_iimmed 0x8000,0x0000,fr7 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + + set_accg_immed 0x80,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed 0x80,accg1 + set_acc_immed 0,acc1 + set_fr_iimmed 0,1,fr7 + set_fr_iimmed 1,1,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x80,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x80,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + + pass + + diff --git a/sim/testsuite/sim/frv/fr550/mmrdhu.cgs b/sim/testsuite/sim/frv/fr550/mmrdhu.cgs new file mode 100644 index 0000000..99378bc --- /dev/null +++ b/sim/testsuite/sim/frv/fr550/mmrdhu.cgs @@ -0,0 +1,151 @@ +# frv testcase for mmrdhu $GRi,$GRj,$GRk +# mach: all + + .include "../testutils.inc" + + start + + .global mmrdhu +mmrdhu: + set_accg_immed 0x80,accg0 + set_acc_immed 0,acc0 + set_accg_immed 0x80,accg1 + set_acc_immed 0,acc1 + + set_fr_iimmed 3,2,fr7 ; multiply small numbers + set_fr_iimmed 2,3,fr8 + mmrdhu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x7f,accg0 + test_acc_immed 0xfffffffa,acc0 + test_accg_immed 0x7f,accg1 + test_acc_immed 0xfffffffa,acc1 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 2,1,fr8 + mmrdhu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x7f,accg0 + test_acc_immed 0xfffffff8,acc0 + test_accg_immed 0x7f,accg1 + test_acc_immed 0xfffffff8,acc1 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + mmrdhu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x7f,accg0 + test_acc_immed 0xfffffff8,acc0 + test_accg_immed 0x7f,accg1 + test_acc_immed 0xfffffff8,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + mmrdhu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xffff,0x7ffa,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xffff,0x7ffa,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + mmrdhu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xfffe,0xfffa,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xfffe,0xfffa,acc1 + + set_fr_iimmed 0x8000,2,fr7 ; 17 bit result + set_fr_iimmed 2,0x8000,fr8 + mmrdhu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xfffd,0xfffa,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xfffd,0xfffa,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + mmrdhu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xbffe,0xfff9,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xbffe,0xfff9,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + mmrdhu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x7f,accg0 + test_acc_limmed 0x7ffe,0xfff9,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0x7ffe,0xfff9,acc1 + + set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + mmrdhu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0x7e,accg0 + test_acc_limmed 0x8000,0xfff8,acc0 + test_accg_immed 0x7e,accg1 + test_acc_limmed 0x8000,0xfff8,acc1 + + set_accg_immed 0,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0,acc1 + set_fr_iimmed 1,1,fr7 + set_fr_iimmed 1,1,fr8 + mmrdhu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x0000,0xffff,fr7 + set_fr_iimmed 0xffff,0xffff,fr8 + mmrdhu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + pass diff --git a/sim/testsuite/sim/frv/fr550/mqaddhss.cgs b/sim/testsuite/sim/frv/fr550/mqaddhss.cgs new file mode 100644 index 0000000..b0c7853 --- /dev/null +++ b/sim/testsuite/sim/frv/fr550/mqaddhss.cgs @@ -0,0 +1,76 @@ +# frv testcase for mqaddhss $FRi,$FRj,$FRj +# mach: all + + .include "../testutils.inc" + + start + + .global mqaddhss +mqaddhss: + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + mqaddhss fr10,fr12,fr14 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0xdead,0xbeef,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + mqaddhss fr10,fr12,fr14 + test_fr_limmed 0xbeef,0xdead,fr14 + test_fr_limmed 0x2345,0x6789,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0xffff,0xffff,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + mqaddhss fr10,fr12,fr14 + test_fr_limmed 0x1233,0x5677,fr14 + test_fr_limmed 0x7fff,0x7fff,fr15 + test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8001,0x8001,fr11 + set_fr_iimmed 0xffff,0xfffe,fr12 + set_fr_iimmed 0xfffe,0xfffe,fr13 + mqaddhss fr10,fr12,fr14 + test_fr_limmed 0x8000,0x8000,fr14 + test_fr_limmed 0x8000,0x8000,fr15 + test_spr_bits 0x3c,2,0x7,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + set_fr_iimmed 0x7fff,0x0000,fr12 + set_fr_iimmed 0x0000,0x8000,fr13 + mqaddhss.p fr10,fr10,fr14 + mqaddhss fr12,fr12,fr16 + test_fr_limmed 0x0002,0x0002,fr14 + test_fr_limmed 0xfffe,0xfffe,fr15 + test_fr_limmed 0x7fff,0x0000,fr16 + test_fr_limmed 0x0000,0x8000,fr17 + test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + pass diff --git a/sim/testsuite/sim/frv/fr550/mqaddhus.cgs b/sim/testsuite/sim/frv/fr550/mqaddhus.cgs new file mode 100644 index 0000000..7f8b755 --- /dev/null +++ b/sim/testsuite/sim/frv/fr550/mqaddhus.cgs @@ -0,0 +1,62 @@ +# frv testcase for mqaddhus $FRi,$FRj,$FRj +# mach: all + + .include "../testutils.inc" + + start + + .global mqaddhus +mqaddhus: + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + mqaddhus fr10,fr12,fr14 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0xdead,0xbeef,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + mqaddhus fr10,fr12,fr14 + test_fr_limmed 0xbeef,0xdead,fr14 + test_fr_limmed 0x2345,0x6789,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + set_fr_iimmed 0x0002,0x0001,fr12 + set_fr_iimmed 0x0001,0x0002,fr13 + mqaddhus fr10,fr12,fr14 + test_fr_limmed 0x8000,0x7fff,fr14 + test_fr_limmed 0xffff,0xffff,fr15 + test_spr_bits 0x3c,2,1,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0002,0x0001,fr10 + set_fr_iimmed 0x0001,0x0001,fr11 + set_fr_iimmed 0xfffe,0xfffe,fr12 + set_fr_iimmed 0x8000,0x8000,fr13 + mqaddhus.p fr10,fr10,fr14 + mqaddhus fr12,fr12,fr16 + test_fr_limmed 0x0004,0x0002,fr14 + test_fr_limmed 0x0002,0x0002,fr15 + test_fr_limmed 0xffff,0xffff,fr16 + test_fr_limmed 0xffff,0xffff,fr17 + test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + pass diff --git a/sim/testsuite/sim/frv/fr550/mqmachs.cgs b/sim/testsuite/sim/frv/fr550/mqmachs.cgs new file mode 100644 index 0000000..2f18620 --- /dev/null +++ b/sim/testsuite/sim/frv/fr550/mqmachs.cgs @@ -0,0 +1,211 @@ +# frv testcase for mqmachs $GRi,$GRj,$ACCk +# mach: all + + .include "../testutils.inc" + + start + + .global mqmachs +mqmachs: + ; Positive operands + set_fr_iimmed 2,3,fr8 ; multiply small numbers + set_fr_iimmed 3,2,fr10 + set_fr_iimmed 0,1,fr9 ; multiply by 0 + set_fr_iimmed 2,0,fr11 + mqmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0,acc3 + + set_fr_iimmed 2,1,fr8 ; multiply by 1 + set_fr_iimmed 1,2,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + mqmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 8,acc0 + test_accg_immed 0,accg1 + test_acc_immed 8,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0,0x7ffe,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0,0x7ffe,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr11 + mqmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8008,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8008,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x3fff,0x7fff,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x3fff,0x7fff,acc3 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr10 + set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr11 + mqmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8002,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8002,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x3fff,0x7ffd,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x3fff,0x7ffd,acc3 + + set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr10 + set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr11 + mqmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8002,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8002,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x3fff,0x3ffb,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x3fff,0x3ffb,acc3 + + set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr10 + set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr11 + mqmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x0002,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x0002,acc1 + test_accg_immed 0xff,accg2 + test_acc_limmed 0xffff,0xbffb,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0xffff,0xbffb,acc3 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr10 + set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr11 + mqmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x0008,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x0008,acc1 + test_accg_immed 0xff,accg2 + test_acc_limmed 0xffff,0xbffd,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0xffff,0xbffd,acc3 + + set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + mqmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0009,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fff0009,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0x3fffbffd,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0x3fffbffd,acc3 + + set_accg_immed 0x7f,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0x7f,accg1 + set_acc_immed 0xffffffff,acc1 + set_accg_immed 0x7f,accg2 ; saturation + set_acc_immed 0xffffffff,acc2 + set_accg_immed 0x7f,accg3 + set_acc_immed 0xffffffff,acc3 + set_fr_iimmed 1,1,fr8 + set_fr_iimmed 1,1,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + mqmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + test_accg_immed 0x7f,accg2 + test_acc_limmed 0xffff,0xffff,acc2 + test_accg_immed 0x7f,accg3 + test_acc_limmed 0xffff,0xffff,acc3 + + set_accg_immed 0x80,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed 0x80,accg1 + set_acc_immed 0,acc1 + set_accg_immed 0x80,accg2 ; saturation + set_acc_immed 0,acc2 + set_accg_immed 0x80,accg3 + set_acc_immed 0,acc3 + set_fr_iimmed 0xffff,0,fr8 + set_fr_iimmed 1,0xffff,fr10 + set_fr_iimmed 0x0000,0x8000,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + mqmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x80,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + test_accg_immed 0x80,accg2 + test_acc_immed 0,acc2 + test_accg_immed 0x80,accg3 + test_acc_immed 0,acc3 + + pass + + diff --git a/sim/testsuite/sim/frv/fr550/mqmachu.cgs b/sim/testsuite/sim/frv/fr550/mqmachu.cgs new file mode 100644 index 0000000..71cba98 --- /dev/null +++ b/sim/testsuite/sim/frv/fr550/mqmachu.cgs @@ -0,0 +1,144 @@ +# frv testcase for mqmachu $GRi,$GRj,$GRk +# mach: all + + .include "../testutils.inc" + + start + + .global mqmachu +mqmachu: + set_fr_iimmed 3,2,fr8 ; multiply small numbers + set_fr_iimmed 2,3,fr10 + set_fr_iimmed 1,2,fr9 ; multiply by 1 + set_fr_iimmed 2,1,fr11 + mqmachu fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + test_accg_immed 0,accg2 + test_acc_immed 2,acc2 + test_accg_immed 0,accg3 + test_acc_immed 2,acc3 + + set_fr_iimmed 0,2,fr8 ; multiply by 0 + set_fr_iimmed 2,0,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + mqmachu fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x8000,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x8000,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x8000,2,fr9 ; 17 bit result + set_fr_iimmed 2,0x8000,fr11 + mqmachu fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8006,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8006,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0x00018000,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0x00018000,acc3 + + set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + mqmachu fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0x3fff8007,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fff8007,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x4001,0x8000,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x4001,0x8000,acc3 + + set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr11 + mqmachu fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 1,accg0 + test_acc_limmed 0x3ffd,0x8008,acc0 + test_accg_immed 1,accg1 + test_acc_limmed 0x3ffd,0x8008,acc1 + test_accg_immed 1,accg2 + test_acc_limmed 0x3fff,0x8001,acc2 + test_accg_immed 1,accg3 + test_acc_limmed 0x3fff,0x8001,acc3 + + set_accg_immed 0xff,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xffffffff,acc1 + set_accg_immed 0xff,accg2 ; saturation + set_acc_immed 0xffffffff,acc2 + set_accg_immed 0xff,accg3 + set_acc_immed 0xffffffff,acc3 + set_fr_iimmed 1,1,fr8 + set_fr_iimmed 1,1,fr10 + set_fr_iimmed 1,1,fr9 + set_fr_iimmed 1,1,fr11 + mqmachu fr8,fr10,acc0 + test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + test_accg_immed 0xff,accg2 + test_acc_limmed 0xffff,0xffff,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0xffff,0xffff,acc3 + + set_fr_iimmed 0xffff,0x0000,fr8 + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0x0000,0xffff,fr9 + set_fr_iimmed 0xffff,0xffff,fr11 + mqmachu fr8,fr10,acc0 + test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + test_accg_immed 0xff,accg2 + test_acc_limmed 0xffff,0xffff,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0xffff,0xffff,acc3 + + pass diff --git a/sim/testsuite/sim/frv/fr550/mqmacxhs.cgs b/sim/testsuite/sim/frv/fr550/mqmacxhs.cgs new file mode 100644 index 0000000..aded33e --- /dev/null +++ b/sim/testsuite/sim/frv/fr550/mqmacxhs.cgs @@ -0,0 +1,211 @@ +# frv testcase for mqmacxhs $GRi,$GRj,$ACCk +# mach: all + + .include "../testutils.inc" + + start + + .global mqmacxhs +mqmacxhs: + ; Positive operands + set_fr_iimmed 2,3,fr8 ; multiply small numbers + set_fr_iimmed 2,3,fr10 + set_fr_iimmed 0,1,fr9 ; multiply by 0 + set_fr_iimmed 0,2,fr11 + mqmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0,acc3 + + set_fr_iimmed 2,1,fr8 ; multiply by 1 + set_fr_iimmed 2,1,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 0x3fff,2,fr11 + mqmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 8,acc0 + test_accg_immed 0,accg1 + test_acc_immed 8,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0,0x7ffe,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0,0x7ffe,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 0x4000,2,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr11 + mqmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8008,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8008,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x3fff,0x7fff,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x3fff,0x7fff,acc3 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 2,0xfffd,fr10 + set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 + set_fr_iimmed 0xfffe,1,fr11 + mqmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8002,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8002,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x3fff,0x7ffd,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x3fff,0x7ffd,acc3 + + set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 + set_fr_iimmed 0xfffe,0,fr10 + set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result + set_fr_iimmed 0x2001,0xfffe,fr11 + mqmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8002,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8002,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x3fff,0x3ffb,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x3fff,0x3ffb,acc3 + + set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result + set_fr_iimmed 0x4000,0xfffe,fr10 + set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result + set_fr_iimmed 0x7fff,0x8000,fr11 + mqmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x0002,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x0002,acc1 + test_accg_immed 0xff,accg2 + test_acc_limmed 0xffff,0xbffb,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0xffff,0xbffb,acc3 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffe,0xfffd,fr10 + set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 + set_fr_iimmed 0xffff,0xfffe,fr11 + mqmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x0008,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x0008,acc1 + test_accg_immed 0xff,accg2 + test_acc_limmed 0xffff,0xbffd,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0xffff,0xbffd,acc3 + + set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + mqmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0009,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fff0009,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0x3fffbffd,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0x3fffbffd,acc3 + + set_accg_immed 0x7f,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0x7f,accg1 + set_acc_immed 0xffffffff,acc1 + set_accg_immed 0x7f,accg2 ; saturation + set_acc_immed 0xffffffff,acc2 + set_accg_immed 0x7f,accg3 + set_acc_immed 0xffffffff,acc3 + set_fr_iimmed 1,1,fr8 + set_fr_iimmed 1,1,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + mqmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + test_accg_immed 0x7f,accg2 + test_acc_limmed 0xffff,0xffff,acc2 + test_accg_immed 0x7f,accg3 + test_acc_limmed 0xffff,0xffff,acc3 + + set_accg_immed 0x80,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed 0x80,accg1 + set_acc_immed 0,acc1 + set_accg_immed 0x80,accg2 ; saturation + set_acc_immed 0,acc2 + set_accg_immed 0x80,accg3 + set_acc_immed 0,acc3 + set_fr_iimmed 0xffff,0,fr8 + set_fr_iimmed 0xffff,1,fr10 + set_fr_iimmed 0x0000,0x8000,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + mqmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x80,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + test_accg_immed 0x80,accg2 + test_acc_immed 0,acc2 + test_accg_immed 0x80,accg3 + test_acc_immed 0,acc3 + + pass + + diff --git a/sim/testsuite/sim/frv/fr550/mqsubhss.cgs b/sim/testsuite/sim/frv/fr550/mqsubhss.cgs new file mode 100644 index 0000000..a8936e9 --- /dev/null +++ b/sim/testsuite/sim/frv/fr550/mqsubhss.cgs @@ -0,0 +1,76 @@ +# frv testcase for mqsubhss $FRi,$FRj,$FRj +# mach: all + + .include "../testutils.inc" + + start + + .global msubhss +msubhss: + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0x0000,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0xbeef,fr13 + mqsubhss fr10,fr12,fr14 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0xdead,0x4111,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + set_fr_iimmed 0xbeef,0x0000,fr12 + set_fr_iimmed 0x1111,0x1111,fr13 + mqsubhss fr10,fr12,fr14 + test_fr_limmed 0x4111,0xdead,fr14 + test_fr_limmed 0x0123,0x4567,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0xffff,0xffff,fr12 + set_fr_iimmed 0xfffe,0xffff,fr13 + mqsubhss fr10,fr12,fr14 + test_fr_limmed 0x1235,0x5679,fr14 + test_fr_limmed 0x7fff,0x7fff,fr15 + test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8001,0x8001,fr11 + set_fr_iimmed 0x0001,0x0002,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + mqsubhss fr10,fr12,fr14 + test_fr_limmed 0x8000,0x8000,fr14 + test_fr_limmed 0x8000,0x8000,fr15 + test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + set_fr_iimmed 0x8000,0x8000,fr12 + set_fr_iimmed 0x8000,0x8000,fr13 + mqsubhss.p fr10,fr10,fr14 + mqsubhss fr12,fr10,fr16 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0x0000,0x0000,fr15 + test_fr_limmed 0x8000,0x8000,fr16 + test_fr_limmed 0x8001,0x8001,fr17 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + pass diff --git a/sim/testsuite/sim/frv/fr550/mqsubhus.cgs b/sim/testsuite/sim/frv/fr550/mqsubhus.cgs new file mode 100644 index 0000000..fc92eb5 --- /dev/null +++ b/sim/testsuite/sim/frv/fr550/mqsubhus.cgs @@ -0,0 +1,63 @@ +# frv testcase for msubhus $FRi,$FRj,$FRj +# mach: all + + .include "../testutils.inc" + + start + + .global msubhus +msubhus: + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0xdead,0xbeef,fr11 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0x0000,fr13 + mqsubhus fr10,fr12,fr14 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0xdead,0xbeef,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0x1111,0x1111,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + mqsubhus fr10,fr12,fr14 + test_fr_limmed 0x0123,0x4567,fr14 + test_fr_limmed 0x7ffc,0x7ffd,fr15 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0001,0x0001,fr11 + set_fr_iimmed 0x0001,0x0002,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + mqsubhus fr10,fr12,fr14 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0x0000,0x0000,fr15 + test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0002,fr11 + set_fr_iimmed 0x0000,0x0001,fr12 + set_fr_iimmed 0x0002,0x0003,fr13 + mqsubhus.p fr10,fr10,fr14 + mqsubhus fr10,fr12,fr16 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0x0000,0x0000,fr15 + test_fr_limmed 0x0001,0x0000,fr16 + test_fr_limmed 0x0000,0x0000,fr17 + test_spr_bits 0x3c,2,0x1,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + pass diff --git a/sim/testsuite/sim/frv/fr550/mqxmachs.cgs b/sim/testsuite/sim/frv/fr550/mqxmachs.cgs new file mode 100644 index 0000000..3c08e41 --- /dev/null +++ b/sim/testsuite/sim/frv/fr550/mqxmachs.cgs @@ -0,0 +1,211 @@ +# frv testcase for mqxmachs $GRi,$GRj,$ACCk +# mach: all + + .include "../testutils.inc" + + start + + .global mqxmachs +mqxmachs: + ; Positive operands + set_fr_iimmed 2,3,fr8 ; multiply small numbers + set_fr_iimmed 3,2,fr10 + set_fr_iimmed 0,1,fr9 ; multiply by 0 + set_fr_iimmed 2,0,fr11 + mqxmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + test_accg_immed 0,accg2 + test_acc_immed 6,acc2 + test_accg_immed 0,accg3 + test_acc_immed 6,acc3 + + set_fr_iimmed 2,1,fr8 ; multiply by 1 + set_fr_iimmed 1,2,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + mqxmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg2 + test_acc_immed 8,acc2 + test_accg_immed 0,accg3 + test_acc_immed 8,acc3 + test_accg_immed 0,accg0 + test_acc_limmed 0,0x7ffe,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0,0x7ffe,acc1 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr11 + mqxmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x8008,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x8008,acc3 + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0x7fff,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0x7fff,acc1 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr10 + set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr11 + mqxmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x8002,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x8002,acc3 + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0x7ffd,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0x7ffd,acc1 + + set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr10 + set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr11 + mqxmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x8002,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x8002,acc3 + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0x3ffb,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0x3ffb,acc1 + + set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr10 + set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr11 + mqxmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x0002,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x0002,acc3 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xbffb,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xbffb,acc1 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr10 + set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr11 + mqxmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x0008,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x0008,acc3 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xbffd,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xbffd,acc1 + + set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + mqxmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg2 + test_acc_immed 0x3fff0009,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0x3fff0009,acc3 + test_accg_immed 0,accg0 + test_acc_immed 0x3fffbffd,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fffbffd,acc1 + + set_accg_immed 0x7f,accg2 ; saturation + set_acc_immed 0xffffffff,acc2 + set_accg_immed 0x7f,accg3 + set_acc_immed 0xffffffff,acc3 + set_accg_immed 0x7f,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0x7f,accg1 + set_acc_immed 0xffffffff,acc1 + set_fr_iimmed 1,1,fr8 + set_fr_iimmed 1,1,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + mqxmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x7f,accg2 + test_acc_limmed 0xffff,0xffff,acc2 + test_accg_immed 0x7f,accg3 + test_acc_limmed 0xffff,0xffff,acc3 + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + + set_accg_immed 0x80,accg2 ; saturation + set_acc_immed 0,acc2 + set_accg_immed 0x80,accg3 + set_acc_immed 0,acc3 + set_accg_immed 0x80,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed 0x80,accg1 + set_acc_immed 0,acc1 + set_fr_iimmed 0xffff,0,fr8 + set_fr_iimmed 1,0xffff,fr10 + set_fr_iimmed 0x0000,0x8000,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + mqxmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x80,accg2 + test_acc_immed 0,acc2 + test_accg_immed 0x80,accg3 + test_acc_immed 0,acc3 + test_accg_immed 0x80,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + + pass + + diff --git a/sim/testsuite/sim/frv/fr550/mqxmacxhs.cgs b/sim/testsuite/sim/frv/fr550/mqxmacxhs.cgs new file mode 100644 index 0000000..32b043b --- /dev/null +++ b/sim/testsuite/sim/frv/fr550/mqxmacxhs.cgs @@ -0,0 +1,211 @@ +# frv testcase for mqxmacxhs $GRi,$GRj,$ACCk +# mach: all + + .include "../testutils.inc" + + start + + .global mqxmacxhs +mqxmacxhs: + ; Positive operands + set_fr_iimmed 2,3,fr8 ; multiply small numbers + set_fr_iimmed 2,3,fr10 + set_fr_iimmed 0,1,fr9 ; multiply by 0 + set_fr_iimmed 0,2,fr11 + mqxmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + test_accg_immed 0,accg2 + test_acc_immed 6,acc2 + test_accg_immed 0,accg3 + test_acc_immed 6,acc3 + + set_fr_iimmed 2,1,fr8 ; multiply by 1 + set_fr_iimmed 2,1,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 0x3fff,2,fr11 + mqxmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg2 + test_acc_immed 8,acc2 + test_accg_immed 0,accg3 + test_acc_immed 8,acc3 + test_accg_immed 0,accg0 + test_acc_limmed 0,0x7ffe,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0,0x7ffe,acc1 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 0x4000,2,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr11 + mqxmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x8008,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x8008,acc3 + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0x7fff,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0x7fff,acc1 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 2,0xfffd,fr10 + set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 + set_fr_iimmed 0xfffe,1,fr11 + mqxmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x8002,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x8002,acc3 + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0x7ffd,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0x7ffd,acc1 + + set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 + set_fr_iimmed 0xfffe,0,fr10 + set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result + set_fr_iimmed 0x2001,0xfffe,fr11 + mqxmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x8002,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x8002,acc3 + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0x3ffb,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0x3ffb,acc1 + + set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result + set_fr_iimmed 0x4000,0xfffe,fr10 + set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result + set_fr_iimmed 0x7fff,0x8000,fr11 + mqxmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x0002,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x0002,acc3 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xbffb,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xbffb,acc1 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffe,0xfffd,fr10 + set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 + set_fr_iimmed 0xffff,0xfffe,fr11 + mqxmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x0008,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x0008,acc3 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xbffd,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xbffd,acc1 + + set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + mqxmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg2 + test_acc_immed 0x3fff0009,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0x3fff0009,acc3 + test_accg_immed 0,accg0 + test_acc_immed 0x3fffbffd,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fffbffd,acc1 + + set_accg_immed 0x7f,accg2 ; saturation + set_acc_immed 0xffffffff,acc2 + set_accg_immed 0x7f,accg3 + set_acc_immed 0xffffffff,acc3 + set_accg_immed 0x7f,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0x7f,accg1 + set_acc_immed 0xffffffff,acc1 + set_fr_iimmed 1,1,fr8 + set_fr_iimmed 1,1,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + mqxmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x7f,accg2 + test_acc_limmed 0xffff,0xffff,acc2 + test_accg_immed 0x7f,accg3 + test_acc_limmed 0xffff,0xffff,acc3 + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + + set_accg_immed 0x80,accg2 ; saturation + set_acc_immed 0,acc2 + set_accg_immed 0x80,accg3 + set_acc_immed 0,acc3 + set_accg_immed 0x80,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed 0x80,accg1 + set_acc_immed 0,acc1 + set_fr_iimmed 0xffff,0,fr8 + set_fr_iimmed 0xffff,1,fr10 + set_fr_iimmed 0x0000,0x8000,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + mqxmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x80,accg2 + test_acc_immed 0,acc2 + test_accg_immed 0x80,accg3 + test_acc_immed 0,acc3 + test_accg_immed 0x80,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + + pass + + diff --git a/sim/testsuite/sim/frv/fr550/msubaccs.cgs b/sim/testsuite/sim/frv/fr550/msubaccs.cgs new file mode 100644 index 0000000..eeaf4a6 --- /dev/null +++ b/sim/testsuite/sim/frv/fr550/msubaccs.cgs @@ -0,0 +1,128 @@ +# frv testcase for msubaccs $ACC40Si,$ACC40Sk +# mach: all + + .include "../testutils.inc" + + start + + .global msubaccs +msubaccs: + set_accg_immed 0,accg0 + set_acc_immed 0x00000000,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x00000000,acc1 + msubaccs acc0,acc3 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x0000,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0xdead0000,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x0000beef,acc1 + msubaccs acc0,acc3 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg3 + test_acc_limmed 0xdeac,0x4111,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x0000dead,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0xbeef0000,acc1 + msubaccs acc0,acc3 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0xff,accg3 + test_acc_limmed 0x4111,0xdead,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x12345678,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x11111111,acc1 + msubaccs acc0,acc3 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg3 + test_acc_limmed 0x0123,0x4567,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x12345678,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0xffffffff,acc1 + msubaccs acc0,acc3 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0xff,accg3 + test_acc_limmed 0x1234,0x5679,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x12345678,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xffffffff,acc1 + msubaccs acc0,acc3 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + test_accg_immed 0,accg3 + test_acc_limmed 0x1234,0x5679,acc3 + + set_spr_immed 0,msr0 + set_accg_immed 0x7f,accg0 + set_acc_immed 0xfffffffe,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xfffffffe,acc1 + msubaccs acc0,acc3 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + test_accg_immed 0x7f,accg3 + test_acc_limmed 0xffff,0xffff,acc3 + + set_spr_immed 0,msr0 + set_accg_immed 0x80,accg0 + set_acc_immed 0x00000001,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x00000002,acc1 + msubaccs acc0,acc3 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + test_accg_immed 0x80,accg3 + test_acc_limmed 0x0000,0x0000,acc3 + + set_spr_immed 0,msr0 + set_accg_immed 0,accg0 + set_acc_immed 0x00000001,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x00000001,acc1 + set_accg_immed 0,accg4 + set_acc_immed 0x00000001,acc4 + set_accg_immed 0x80,accg5 + set_acc_immed 0x00000000,acc5 + msubaccs.p acc0,acc1 + msubaccs acc4,acc5 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x0000,acc1 + test_accg_immed 0x7f,accg5 + test_acc_limmed 0xffff,0xffff,acc5 + + pass diff --git a/sim/testsuite/sim/frv/fr550/msubhss.cgs b/sim/testsuite/sim/frv/fr550/msubhss.cgs new file mode 100644 index 0000000..6beb676 --- /dev/null +++ b/sim/testsuite/sim/frv/fr550/msubhss.cgs @@ -0,0 +1,97 @@ +# frv testcase for msubhss $FRi,$FRj,$FRj +# mach: all + + .include "../testutils.inc" + + start + + .global msubhss +msubhss: + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + msubhss fr10,fr11,fr12 + test_fr_limmed 0x0000,0x0000,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + msubhss fr10,fr11,fr12 + test_fr_limmed 0xdead,0x4111,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + msubhss fr10,fr11,fr12 + test_fr_limmed 0x4111,0xdead,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + msubhss fr10,fr11,fr12 + test_fr_limmed 0x0123,0x4567,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + msubhss fr10,fr11,fr12 + test_fr_limmed 0x1235,0x5679,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0xfffe,0xffff,fr11 + msubhss fr10,fr11,fr12 + test_fr_limmed 0x7fff,0x7fff,fr12 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + msubhss fr10,fr11,fr12 + test_fr_limmed 0x8000,0x8000,fr12 + test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + msubhss fr10,fr11,fr12 + test_fr_limmed 0x8000,0x8000,fr12 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + msubhss.p fr10,fr10,fr12 + msubhss fr11,fr10,fr13 + test_fr_limmed 0x0000,0x0000,fr12 + test_fr_limmed 0x8000,0x8000,fr13 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + pass diff --git a/sim/testsuite/sim/frv/fr550/msubhus.cgs b/sim/testsuite/sim/frv/fr550/msubhus.cgs new file mode 100644 index 0000000..5a3cd26 --- /dev/null +++ b/sim/testsuite/sim/frv/fr550/msubhus.cgs @@ -0,0 +1,77 @@ +# frv testcase for msubhus $FRi,$FRj,$FRj +# mach: all + + .include "../testutils.inc" + + start + + .global msubhus +msubhus: + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + msubhus fr10,fr11,fr12 + test_fr_limmed 0x0000,0x0000,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0xdead,0xbeef,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + msubhus fr10,fr11,fr12 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + msubhus fr10,fr11,fr12 + test_fr_limmed 0x0123,0x4567,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + msubhus fr10,fr11,fr12 + test_fr_limmed 0x7ffc,0x7ffd,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set + + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + msubhus fr10,fr11,fr12 + test_fr_limmed 0x0000,0x0000,fr12 + test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + msubhus fr10,fr11,fr12 + test_fr_limmed 0x0000,0x0000,fr12 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0002,fr11 + msubhus.p fr10,fr10,fr12 + msubhus fr10,fr11,fr13 + test_fr_limmed 0x0000,0x0000,fr12 + test_fr_limmed 0x0000,0x0000,fr13 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + pass diff --git a/sim/testsuite/sim/frv/fr550/mtrap.cgs b/sim/testsuite/sim/frv/fr550/mtrap.cgs new file mode 100644 index 0000000..83dca7b --- /dev/null +++ b/sim/testsuite/sim/frv/fr550/mtrap.cgs @@ -0,0 +1,50 @@ +# frv testcase for mp_exception +# mach: all + + .include "../testutils.inc" + + start + + .global mp_exception +mpx: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 0x0e0,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 + set_spr_immed 128,lcr + set_spr_addr ok1,lr + set_psr_et 1 + set_gr_immed 0,gr5 + + set_spr_immed 0,msr0 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0xffff,0xffff,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + mqaddhss fr10,fr12,fr14 + test_fr_limmed 0x1233,0x5677,fr14 + test_fr_limmed 0x7fff,0x7fff,fr15 + test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + mtrap ; generate interrupt + test_gr_immed 1,gr5 + + and_spr_immed 0xffffc000,msr0 ; Clear msr0 fields + mcmpsh fr10,fr11,fcc0 ; no exception + test_spr_bits 0x7000,12,1,msr0; msr0.mtt is always set + mtrap ; nop + test_gr_immed 1,gr5 + + pass + +; exception handler +ok1: + test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + inc_gr_immed 1,gr5 + rett 0 + fail diff --git a/sim/testsuite/sim/frv/fr550/udiv.cgs b/sim/testsuite/sim/frv/fr550/udiv.cgs new file mode 100644 index 0000000..05cbde4 --- /dev/null +++ b/sim/testsuite/sim/frv/fr550/udiv.cgs @@ -0,0 +1,48 @@ +# frv testcase for udiv $GRi,$GRj,$GRk +# mach: all + + .include "../testutils.inc" + + start + + .global udiv +udiv: + ; simple division 12 / 3 + set_gr_immed 0x00000003,gr2 + set_gr_immed 0x0000000c,gr3 + udiv gr3,gr2,gr3 + test_gr_immed 0x00000003,gr2 + test_gr_immed 0x00000004,gr3 + + ; example 1 from udiv in the fr30 manual + set_gr_limmed 0x0123,0x4567,gr2 + set_gr_limmed 0xfedc,0xba98,gr3 + udiv gr3,gr2,gr3 + test_gr_limmed 0x0123,0x4567,gr2 + test_gr_immed 0x000000e0,gr3 + + ; set up exception handler + set_psr_et 1 + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr17 + inc_gr_immed 0x170,gr17 ; address of exception handler + set_bctrlr_0_0 gr17 + set_spr_immed 128,lcr + set_gr_immed 0,gr15 + + ; divide by zero + set_spr_addr ok1,lr + set_gr_addr e1,gr17 +e1: udiv gr1,gr0,gr2 ; divide by zero + test_gr_immed 1,gr15 + + pass + +ok1: ; exception handler for divide by zero + test_spr_bits 0x18,3,0x3,isr ; isr.dtt is set + test_spr_gr epcr0,gr17 ; return address set + test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid + test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set + inc_gr_immed 1,gr15 + rett 0 + fail diff --git a/sim/testsuite/sim/frv/fr550/udivi.cgs b/sim/testsuite/sim/frv/fr550/udivi.cgs new file mode 100644 index 0000000..d5ee1c4 --- /dev/null +++ b/sim/testsuite/sim/frv/fr550/udivi.cgs @@ -0,0 +1,49 @@ +# frv testcase for udivi $GRi,$s12,$GRk +# mach: all + + .include "../testutils.inc" + + start + + .global udivi +udivi: + ; simple division 12 / 3 + set_gr_immed 0x0000000c,gr3 + udivi gr3,3,gr3 + test_gr_immed 0x00000004,gr3 + + ; random example + set_gr_limmed 0xfedc,0xba98,gr3 + udivi gr3,0x7ff,gr3 + test_gr_limmed 0x001f,0xdf93,gr3 + + ; random example + set_gr_limmed 0xffff,0xffff,gr3 + udivi gr3,-2048,gr3 + test_gr_immed 1,gr3 + + ; set up exception handler + set_psr_et 1 + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr17 + inc_gr_immed 0x170,gr17 ; address of exception handler + set_bctrlr_0_0 gr17 + set_spr_immed 128,lcr + set_gr_immed 0,gr15 + + ; divide by zero + set_spr_addr ok1,lr + set_gr_addr e1,gr17 +e1: udivi gr1,0,gr2 ; divide by zero + test_gr_immed 1,gr15 + + pass + +ok1: ; exception handler for divide by zero + test_spr_bits 0x18,3,0x3,isr ; isr.dtt is set + test_spr_gr epcr0,gr17 ; return address set + test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid + test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set + inc_gr_immed 1,gr15 + rett 0 + fail diff --git a/sim/testsuite/sim/frv/fsqrtd.cgs b/sim/testsuite/sim/frv/fsqrtd.cgs new file mode 100644 index 0000000..a428b01 --- /dev/null +++ b/sim/testsuite/sim/frv/fsqrtd.cgs @@ -0,0 +1,22 @@ +# frv testcase for fsqrtd $FRj,$FRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + double_constants + start + load_double_constants + + .global fsqrtd +fsqrtd: + fsqrtd fr44,fr2 ; 9.0 + test_dfr_dfr fr2,fr36 ; 3.0 + + set_fr_iimmed 0x4009,0x21fb,fr10 ; 3.141592654 + set_fr_iimmed 0x6000,0x0000,fr11 + fsqrtd fr10,fr10 + test_fr_iimmed 0x3ffc5bf8,fr10 ; 1.7724539 + test_fr_iimmed 0x9853a94d,fr11 + + pass diff --git a/sim/testsuite/sim/frv/fsqrts.cgs b/sim/testsuite/sim/frv/fsqrts.cgs new file mode 100644 index 0000000..e771c40 --- /dev/null +++ b/sim/testsuite/sim/frv/fsqrts.cgs @@ -0,0 +1,19 @@ +# frv testcase for fsqrts $FRj,$FRk +# mach: fr500 fr550 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global fsqrts +fsqrts: + fsqrts fr44,fr1 ; 9.0 + test_fr_fr fr1,fr36 ; 3.0 + + set_fr_iimmed 0x4049,0x0fdb,fr10 ; 3.141592654 + fsqrts fr10,fr10 + test_fr_iimmed 0x3fe2dfc5,fr10 ; 1.7724539 + + pass diff --git a/sim/testsuite/sim/frv/fstoi.cgs b/sim/testsuite/sim/frv/fstoi.cgs new file mode 100644 index 0000000..0a90a2a --- /dev/null +++ b/sim/testsuite/sim/frv/fstoi.cgs @@ -0,0 +1,24 @@ +# frv testcase for fstoi $FRj,$FRk +# mach: fr500 fr550 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global fstoi +fstoi: + fstoi fr16,fr1 + test_fr_iimmed 0,fr1 + fstoi fr20,fr1 + test_fr_iimmed 0,fr1 + + fstoi fr32,fr1 + test_fr_iimmed 0x00000002,fr1 + + set_fr_iimmed 0xce05,0x4904,fr1 + fstoi fr1,fr1 + test_fr_iimmed 0xdeadbf00,fr1 + + pass diff --git a/sim/testsuite/sim/frv/fsubd.cgs b/sim/testsuite/sim/frv/fsubd.cgs new file mode 100644 index 0000000..fed2d04 --- /dev/null +++ b/sim/testsuite/sim/frv/fsubd.cgs @@ -0,0 +1,83 @@ +# frv testcase for fsubd $GRi,$GRj,$GRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + double_constants + start + load_double_constants + + .global fsubd +fsubd: + fsubd fr0,fr16,fr2 + test_dfr_dfr fr2,fr0 + fsubd fr4,fr16,fr2 + test_dfr_dfr fr2,fr4 + fsubd fr8,fr16,fr2 + test_dfr_dfr fr2,fr8 + fsubd fr12,fr16,fr2 + test_dfr_dfr fr2,fr12 + fsubd fr16,fr16,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fsubd fr20,fr16,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fsubd fr24,fr16,fr2 + test_dfr_dfr fr2,fr24 + fsubd fr28,fr16,fr2 + test_dfr_dfr fr2,fr28 + fsubd fr32,fr16,fr2 + test_dfr_dfr fr2,fr32 + fsubd fr36,fr16,fr2 + test_dfr_dfr fr2,fr36 + fsubd fr40,fr16,fr2 + test_dfr_dfr fr2,fr40 + fsubd fr44,fr16,fr2 + test_dfr_dfr fr2,fr44 + fsubd fr48,fr16,fr2 + test_dfr_dfr fr2,fr48 + fsubd fr52,fr16,fr2 + test_dfr_dfr fr2,fr52 + + fsubd fr0,fr20,fr2 + test_dfr_dfr fr2,fr0 + fsubd fr4,fr20,fr2 + test_dfr_dfr fr2,fr4 + fsubd fr8,fr20,fr2 + test_dfr_dfr fr2,fr8 + fsubd fr12,fr20,fr2 + test_dfr_dfr fr2,fr12 + fsubd fr16,fr20,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fsubd fr20,fr20,fr2 + test_dfr_dfr fr2,fr16 + test_dfr_dfr fr2,fr20 + fsubd fr24,fr20,fr2 + test_dfr_dfr fr2,fr24 + fsubd fr28,fr20,fr2 + test_dfr_dfr fr2,fr28 + fsubd fr32,fr20,fr2 + test_dfr_dfr fr2,fr32 + fsubd fr36,fr20,fr2 + test_dfr_dfr fr2,fr36 + fsubd fr40,fr20,fr2 + test_dfr_dfr fr2,fr40 + fsubd fr44,fr20,fr2 + test_dfr_dfr fr2,fr44 + fsubd fr48,fr20,fr2 + test_dfr_dfr fr2,fr48 + fsubd fr52,fr20,fr2 + test_dfr_dfr fr2,fr52 + + fsubd fr32,fr36,fr2 + test_dfr_dfr fr2,fr8 + + fsubd fr44,fr40,fr2 + test_dfr_dfr fr2,fr36 + + pass + + diff --git a/sim/testsuite/sim/frv/fsubs.cgs b/sim/testsuite/sim/frv/fsubs.cgs new file mode 100644 index 0000000..c1143ad --- /dev/null +++ b/sim/testsuite/sim/frv/fsubs.cgs @@ -0,0 +1,82 @@ +# frv testcase for fsubs $GRi,$GRj,$GRk +# mach: fr500 fr550 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global fsubs +fsubs: + fsubs fr0,fr16,fr1 + test_fr_fr fr1,fr0 + fsubs fr4,fr16,fr1 + test_fr_fr fr1,fr4 + fsubs fr8,fr16,fr1 + test_fr_fr fr1,fr8 + fsubs fr12,fr16,fr1 + test_fr_fr fr1,fr12 + fsubs fr16,fr16,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fsubs fr20,fr16,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fsubs fr24,fr16,fr1 + test_fr_fr fr1,fr24 + fsubs fr28,fr16,fr1 + test_fr_fr fr1,fr28 + fsubs fr32,fr16,fr1 + test_fr_fr fr1,fr32 + fsubs fr36,fr16,fr1 + test_fr_fr fr1,fr36 + fsubs fr40,fr16,fr1 + test_fr_fr fr1,fr40 + fsubs fr44,fr16,fr1 + test_fr_fr fr1,fr44 + fsubs fr48,fr16,fr1 + test_fr_fr fr1,fr48 + fsubs fr52,fr16,fr1 + test_fr_fr fr1,fr52 + + fsubs fr0,fr20,fr1 + test_fr_fr fr1,fr0 + fsubs fr4,fr20,fr1 + test_fr_fr fr1,fr4 + fsubs fr8,fr20,fr1 + test_fr_fr fr1,fr8 + fsubs fr12,fr20,fr1 + test_fr_fr fr1,fr12 + fsubs fr16,fr20,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fsubs fr20,fr20,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + fsubs fr24,fr20,fr1 + test_fr_fr fr1,fr24 + fsubs fr28,fr20,fr1 + test_fr_fr fr1,fr28 + fsubs fr32,fr20,fr1 + test_fr_fr fr1,fr32 + fsubs fr36,fr20,fr1 + test_fr_fr fr1,fr36 + fsubs fr40,fr20,fr1 + test_fr_fr fr1,fr40 + fsubs fr44,fr20,fr1 + test_fr_fr fr1,fr44 + fsubs fr48,fr20,fr1 + test_fr_fr fr1,fr48 + fsubs fr52,fr20,fr1 + test_fr_fr fr1,fr52 + + fsubs fr32,fr36,fr1 + test_fr_fr fr1,fr8 + + fsubs fr44,fr40,fr1 + test_fr_fr fr1,fr36 + + pass + + diff --git a/sim/testsuite/sim/frv/fteq.cgs b/sim/testsuite/sim/frv/fteq.cgs new file mode 100644 index 0000000..020a887 --- /dev/null +++ b/sim/testsuite/sim/frv/fteq.cgs @@ -0,0 +1,101 @@ +# frv testcase for fteq $FCCi_2,$GRi,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global fteq +fteq: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_spr_addr bad,lr + set_fcc 0x0 0 + fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x1 0 + fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x2 0 + fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x3 0 + fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x4 0 + fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x5 0 + fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x6 0 + fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x7 0 + fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok8,lr + set_fcc 0x8 0 + fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok8: + set_psr_et 1 + set_spr_addr ok9,lr + set_fcc 0x9 0 + fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_psr_et 1 + set_spr_addr oka,lr + set_fcc 0xa 0 + fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_fcc 0xb 0 + fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_psr_et 1 + set_spr_addr okc,lr + set_fcc 0xc 0 + fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_fcc 0xd 0 + fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_fcc 0xe 0 + fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_fcc 0xf 0 + fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/ftge.cgs b/sim/testsuite/sim/frv/ftge.cgs new file mode 100644 index 0000000..eab7a06 --- /dev/null +++ b/sim/testsuite/sim/frv/ftge.cgs @@ -0,0 +1,109 @@ +# frv testcase for ftge $FCCi_2,$GRi,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global ftge +ftge: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_spr_addr bad,lr + set_fcc 0x0 0 + ftge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x1 0 + ftge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok2,lr + set_fcc 0x2 0 + ftge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_psr_et 1 + set_spr_addr ok3,lr + set_fcc 0x3 0 + ftge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_spr_addr bad,lr + set_fcc 0x4 0 + ftge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x5 0 + ftge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok6,lr + set_fcc 0x6 0 + ftge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_fcc 0x7 0 + ftge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_psr_et 1 + set_spr_addr ok8,lr + set_fcc 0x8 0 + ftge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok8: + set_psr_et 1 + set_spr_addr ok9,lr + set_fcc 0x9 0 + ftge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_psr_et 1 + set_spr_addr oka,lr + set_fcc 0xa 0 + ftge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_fcc 0xb 0 + ftge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_psr_et 1 + set_spr_addr okc,lr + set_fcc 0xc 0 + ftge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_fcc 0xd 0 + ftge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_fcc 0xe 0 + ftge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_fcc 0xf 0 + ftge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/ftgt.cgs b/sim/testsuite/sim/frv/ftgt.cgs new file mode 100644 index 0000000..9035fbc --- /dev/null +++ b/sim/testsuite/sim/frv/ftgt.cgs @@ -0,0 +1,101 @@ +# frv testcase for ftgt $FCCi_2,$GRi,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global ftgt +ftgt: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_spr_addr bad,lr + set_fcc 0x0 0 + ftgt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x1 0 + ftgt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok2,lr + set_fcc 0x2 0 + ftgt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_psr_et 1 + set_spr_addr ok3,lr + set_fcc 0x3 0 + ftgt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_spr_addr bad,lr + set_fcc 0x4 0 + ftgt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x5 0 + ftgt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok6,lr + set_fcc 0x6 0 + ftgt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_fcc 0x7 0 + ftgt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_spr_addr bad,lr + set_fcc 0x8 0 + ftgt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x9 0 + ftgt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr oka,lr + set_fcc 0xa 0 + ftgt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_fcc 0xb 0 + ftgt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_spr_addr bad,lr + set_fcc 0xc 0 + ftgt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0xd 0 + ftgt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr oke,lr + set_fcc 0xe 0 + ftgt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_fcc 0xf 0 + ftgt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/ftieq.cgs b/sim/testsuite/sim/frv/ftieq.cgs new file mode 100644 index 0000000..a5710ad --- /dev/null +++ b/sim/testsuite/sim/frv/ftieq.cgs @@ -0,0 +1,100 @@ +# frv testcase for ftieq $FCCi_2,$GRi,$s12 +# mach: all + + .include "testutils.inc" + + start + + .global ftieq +ftieq: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + + set_spr_addr bad,lr + set_fcc 0x0 0 + ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x1 0 + ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x2 0 + ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x3 0 + ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x4 0 + ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x5 0 + ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x6 0 + ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x7 0 + ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok8,lr + set_fcc 0x8 0 + ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok8: + set_psr_et 1 + set_spr_addr ok9,lr + set_fcc 0x9 0 + ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_psr_et 1 + set_spr_addr oka,lr + set_fcc 0xa 0 + ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_fcc 0xb 0 + ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_psr_et 1 + set_spr_addr okc,lr + set_fcc 0xc 0 + ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_fcc 0xd 0 + ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_fcc 0xe 0 + ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_fcc 0xf 0 + ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/ftige.cgs b/sim/testsuite/sim/frv/ftige.cgs new file mode 100644 index 0000000..5b58ce0 --- /dev/null +++ b/sim/testsuite/sim/frv/ftige.cgs @@ -0,0 +1,108 @@ +# frv testcase for ftige $FCCi_2,$GRi,$s12 +# mach: all + + .include "testutils.inc" + + start + + .global ftige +ftige: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + + set_spr_addr bad,lr + set_fcc 0x0 0 + ftige fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x1 0 + ftige fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok2,lr + set_fcc 0x2 0 + ftige fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_psr_et 1 + set_spr_addr ok3,lr + set_fcc 0x3 0 + ftige fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_spr_addr bad,lr + set_fcc 0x4 0 + ftige fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x5 0 + ftige fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok6,lr + set_fcc 0x6 0 + ftige fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_fcc 0x7 0 + ftige fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_psr_et 1 + set_spr_addr ok8,lr + set_fcc 0x8 0 + ftige fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok8: + set_psr_et 1 + set_spr_addr ok9,lr + set_fcc 0x9 0 + ftige fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_psr_et 1 + set_spr_addr oka,lr + set_fcc 0xa 0 + ftige fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_fcc 0xb 0 + ftige fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_psr_et 1 + set_spr_addr okc,lr + set_fcc 0xc 0 + ftige fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_fcc 0xd 0 + ftige fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_fcc 0xe 0 + ftige fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_fcc 0xf 0 + ftige fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/ftigt.cgs b/sim/testsuite/sim/frv/ftigt.cgs new file mode 100644 index 0000000..e31ead4 --- /dev/null +++ b/sim/testsuite/sim/frv/ftigt.cgs @@ -0,0 +1,100 @@ +# frv testcase for ftigt $FCCi_2,$GRi,$s12 +# mach: all + + .include "testutils.inc" + + start + + .global ftigt +ftigt: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + + set_spr_addr bad,lr + set_fcc 0x0 0 + ftigt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x1 0 + ftigt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok2,lr + set_fcc 0x2 0 + ftigt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_psr_et 1 + set_spr_addr ok3,lr + set_fcc 0x3 0 + ftigt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_spr_addr bad,lr + set_fcc 0x4 0 + ftigt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x5 0 + ftigt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok6,lr + set_fcc 0x6 0 + ftigt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_fcc 0x7 0 + ftigt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_spr_addr bad,lr + set_fcc 0x8 0 + ftigt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x9 0 + ftigt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr oka,lr + set_fcc 0xa 0 + ftigt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_fcc 0xb 0 + ftigt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_spr_addr bad,lr + set_fcc 0xc 0 + ftigt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0xd 0 + ftigt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr oke,lr + set_fcc 0xe 0 + ftigt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_fcc 0xf 0 + ftigt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/ftile.cgs b/sim/testsuite/sim/frv/ftile.cgs new file mode 100644 index 0000000..d13eeee --- /dev/null +++ b/sim/testsuite/sim/frv/ftile.cgs @@ -0,0 +1,108 @@ +# frv testcase for ftile $FCCi_2,$GRi,$s12 +# mach: all + + .include "testutils.inc" + + start + + .global ftile +ftile: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + + set_spr_addr bad,lr + set_fcc 0x0 0 + ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x1 0 + ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x2 0 + ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x3 0 + ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok4,lr + set_fcc 0x4 0 + ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok4: + set_psr_et 1 + set_spr_addr ok5,lr + set_fcc 0x5 0 + ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_psr_et 1 + set_spr_addr ok6,lr + set_fcc 0x6 0 + ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_fcc 0x7 0 + ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_psr_et 1 + set_spr_addr ok8,lr + set_fcc 0x8 0 + ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok8: + set_psr_et 1 + set_spr_addr ok9,lr + set_fcc 0x9 0 + ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_psr_et 1 + set_spr_addr oka,lr + set_fcc 0xa 0 + ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_fcc 0xb 0 + ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_psr_et 1 + set_spr_addr okc,lr + set_fcc 0xc 0 + ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_fcc 0xd 0 + ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_fcc 0xe 0 + ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_fcc 0xf 0 + ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/ftilg.cgs b/sim/testsuite/sim/frv/ftilg.cgs new file mode 100644 index 0000000..26127d2 --- /dev/null +++ b/sim/testsuite/sim/frv/ftilg.cgs @@ -0,0 +1,108 @@ +# frv testcase for ftilg $FCCi_2,$GRi,$s12 +# mach: all + + .include "testutils.inc" + + start + + .global ftilg +ftilg: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + + set_spr_addr bad,lr + set_fcc 0x0 0 + ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x1 0 + ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok2,lr + set_fcc 0x2 0 + ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_psr_et 1 + set_spr_addr ok3,lr + set_fcc 0x3 0 + ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_psr_et 1 + set_spr_addr ok4,lr + set_fcc 0x4 0 + ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok4: + set_psr_et 1 + set_spr_addr ok5,lr + set_fcc 0x5 0 + ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_psr_et 1 + set_spr_addr ok6,lr + set_fcc 0x6 0 + ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_fcc 0x7 0 + ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_spr_addr bad,lr + set_fcc 0x8 0 + ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x9 0 + ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr oka,lr + set_fcc 0xa 0 + ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_fcc 0xb 0 + ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_psr_et 1 + set_spr_addr okc,lr + set_fcc 0xc 0 + ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_fcc 0xd 0 + ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_fcc 0xe 0 + ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_fcc 0xf 0 + ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/ftilt.cgs b/sim/testsuite/sim/frv/ftilt.cgs new file mode 100644 index 0000000..7a74d5b --- /dev/null +++ b/sim/testsuite/sim/frv/ftilt.cgs @@ -0,0 +1,100 @@ +# frv testcase for ftilt $FCCi_2,$GRi,$s12 +# mach: all + + .include "testutils.inc" + + start + + .global ftilt +ftilt: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + + set_spr_addr bad,lr + set_fcc 0x0 0 + ftilt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x1 0 + ftilt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x2 0 + ftilt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x3 0 + ftilt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok4,lr + set_fcc 0x4 0 + ftilt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok4: + set_psr_et 1 + set_spr_addr ok5,lr + set_fcc 0x5 0 + ftilt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_psr_et 1 + set_spr_addr ok6,lr + set_fcc 0x6 0 + ftilt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_fcc 0x7 0 + ftilt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_spr_addr bad,lr + set_fcc 0x8 0 + ftilt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x9 0 + ftilt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0xa 0 + ftilt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0xb 0 + ftilt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr okc,lr + set_fcc 0xc 0 + ftilt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_fcc 0xd 0 + ftilt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_fcc 0xe 0 + ftilt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_fcc 0xf 0 + ftilt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/ftine.cgs b/sim/testsuite/sim/frv/ftine.cgs new file mode 100644 index 0000000..89aa5a6 --- /dev/null +++ b/sim/testsuite/sim/frv/ftine.cgs @@ -0,0 +1,112 @@ +# frv testcase for ftine $FCCi_2,$GRi,$s12 +# mach: all + + .include "testutils.inc" + + start + + .global ftine +ftine: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + + set_spr_addr bad,lr + set_fcc 0x0 0 + ftine fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok1,lr + set_fcc 0x1 0 + ftine fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok1: + set_psr_et 1 + set_spr_addr ok2,lr + set_fcc 0x2 0 + ftine fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_psr_et 1 + set_spr_addr ok3,lr + set_fcc 0x3 0 + ftine fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_psr_et 1 + set_spr_addr ok4,lr + set_fcc 0x4 0 + ftine fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok4: + set_psr_et 1 + set_spr_addr ok5,lr + set_fcc 0x5 0 + ftine fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_psr_et 1 + set_spr_addr ok6,lr + set_fcc 0x6 0 + ftine fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_fcc 0x7 0 + ftine fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_spr_addr bad,lr + set_fcc 0x8 0 + ftine fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok9,lr + set_fcc 0x9 0 + ftine fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_psr_et 1 + set_spr_addr oka,lr + set_fcc 0xa 0 + ftine fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_fcc 0xb 0 + ftine fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_psr_et 1 + set_spr_addr okc,lr + set_fcc 0xc 0 + ftine fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_fcc 0xd 0 + ftine fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_fcc 0xe 0 + ftine fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_fcc 0xf 0 + ftine fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/ftino.cgs b/sim/testsuite/sim/frv/ftino.cgs new file mode 100644 index 0000000..b08a571 --- /dev/null +++ b/sim/testsuite/sim/frv/ftino.cgs @@ -0,0 +1,53 @@ +# frv testcase for ftino +# mach: all + + .include "testutils.inc" + + start + + .global ftinev +ftinev: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_mem_limmed 0x0038,0x2000,gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_gr_immed 0,gr7 + + set_fcc 0x0 0 + ftino ; should branch to tbr + (128 + 4)*16 + set_fcc 0x1 0 + ftino ; should branch to tbr + (128 + 4)*16 + set_fcc 0x2 0 + ftino ; should branch to tbr + (128 + 4)*16 + set_fcc 0x3 0 + ftino ; should branch to tbr + (128 + 4)*16 + set_fcc 0x4 0 + ftino ; should branch to tbr + (128 + 4)*16 + set_fcc 0x5 0 + ftino ; should branch to tbr + (128 + 4)*16 + set_fcc 0x6 0 + ftino ; should branch to tbr + (128 + 4)*16 + set_fcc 0x7 0 + ftino ; should branch to tbr + (128 + 4)*16 + set_fcc 0x8 0 + ftino ; should branch to tbr + (128 + 4)*16 + set_fcc 0x9 0 + ftino ; should branch to tbr + (128 + 4)*16 + set_fcc 0xa 0 + ftino ; should branch to tbr + (128 + 4)*16 + set_fcc 0xb 0 + ftino ; should branch to tbr + (128 + 4)*16 + set_fcc 0xc 0 + ftino ; should branch to tbr + (128 + 4)*16 + set_fcc 0xd 0 + ftino ; should branch to tbr + (128 + 4)*16 + set_fcc 0xe 0 + ftino ; should branch to tbr + (128 + 4)*16 + set_fcc 0xf 0 + ftino ; should branch to tbr + (128 + 4)*16 + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/ftio.cgs b/sim/testsuite/sim/frv/ftio.cgs new file mode 100644 index 0000000..083c170 --- /dev/null +++ b/sim/testsuite/sim/frv/ftio.cgs @@ -0,0 +1,112 @@ +# frv testcase for ftio $FCCi_2,$GRi,$s12 +# mach: all + + .include "testutils.inc" + + start + + .global ftio +ftio: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + + set_spr_addr bad,lr + set_fcc 0x0 0 + ftio fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x1 0 + ftio fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok2,lr + set_fcc 0x2 0 + ftio fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_psr_et 1 + set_spr_addr ok3,lr + set_fcc 0x3 0 + ftio fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_psr_et 1 + set_spr_addr ok4,lr + set_fcc 0x4 0 + ftio fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok4: + set_psr_et 1 + set_spr_addr ok5,lr + set_fcc 0x5 0 + ftio fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_psr_et 1 + set_spr_addr ok6,lr + set_fcc 0x6 0 + ftio fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_fcc 0x7 0 + ftio fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_psr_et 1 + set_spr_addr ok8,lr + set_fcc 0x8 0 + ftio fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok8: + set_psr_et 1 + set_spr_addr ok9,lr + set_fcc 0x9 0 + ftio fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_psr_et 1 + set_spr_addr oka,lr + set_fcc 0xa 0 + ftio fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_fcc 0xb 0 + ftio fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_psr_et 1 + set_spr_addr okc,lr + set_fcc 0xc 0 + ftio fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_fcc 0xd 0 + ftio fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_fcc 0xe 0 + ftio fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_fcc 0xf 0 + ftio fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/ftira.cgs b/sim/testsuite/sim/frv/ftira.cgs new file mode 100644 index 0000000..9382b2b --- /dev/null +++ b/sim/testsuite/sim/frv/ftira.cgs @@ -0,0 +1,114 @@ +# frv testcase for ftira $GRi,$s12 +# mach: all + + .include "testutils.inc" + + start + + .global ftira +ftira: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + + set_psr_et 1 + set_spr_addr ok0,lr + set_fcc 0x0 0 + ftira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok0: + set_psr_et 1 + set_spr_addr ok1,lr + set_fcc 0x1 0 + ftira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok1: + set_psr_et 1 + set_spr_addr ok2,lr + set_fcc 0x2 0 + ftira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_psr_et 1 + set_spr_addr ok3,lr + set_fcc 0x3 0 + ftira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_psr_et 1 + set_spr_addr ok4,lr + set_fcc 0x4 0 + ftira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok4: + set_psr_et 1 + set_spr_addr ok5,lr + set_fcc 0x5 0 + ftira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_psr_et 1 + set_spr_addr ok6,lr + set_fcc 0x6 0 + ftira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_fcc 0x7 0 + ftira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_psr_et 1 + set_spr_addr ok8,lr + set_fcc 0x8 0 + ftira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok8: + set_psr_et 1 + set_spr_addr ok9,lr + set_fcc 0x9 0 + ftira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_psr_et 1 + set_spr_addr oka,lr + set_fcc 0xa 0 + ftira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_fcc 0xb 0 + ftira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_psr_et 1 + set_spr_addr okc,lr + set_fcc 0xc 0 + ftira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_fcc 0xd 0 + ftira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_fcc 0xe 0 + ftira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_fcc 0xf 0 + ftira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass diff --git a/sim/testsuite/sim/frv/ftiu.cgs b/sim/testsuite/sim/frv/ftiu.cgs new file mode 100644 index 0000000..adc40be --- /dev/null +++ b/sim/testsuite/sim/frv/ftiu.cgs @@ -0,0 +1,100 @@ +# frv testcase for ftiu $FCCi_2,$GRi,$s12 +# mach: all + + .include "testutils.inc" + + start + + .global ftiu +ftiu: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + + set_spr_addr bad,lr + set_fcc 0x0 0 + ftiu fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok1,lr + set_fcc 0x1 0 + ftiu fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok1: + set_spr_addr bad,lr + set_fcc 0x2 0 + ftiu fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok3,lr + set_fcc 0x3 0 + ftiu fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_spr_addr bad,lr + set_fcc 0x4 0 + ftiu fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok5,lr + set_fcc 0x5 0 + ftiu fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_spr_addr bad,lr + set_fcc 0x6 0 + ftiu fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok7,lr + set_fcc 0x7 0 + ftiu fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_spr_addr bad,lr + set_fcc 0x8 0 + ftiu fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok9,lr + set_fcc 0x9 0 + ftiu fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_spr_addr bad,lr + set_fcc 0xa 0 + ftiu fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr okb,lr + set_fcc 0xb 0 + ftiu fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_spr_addr bad,lr + set_fcc 0xc 0 + ftiu fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr okd,lr + set_fcc 0xd 0 + ftiu fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_spr_addr bad,lr + set_fcc 0xe 0 + ftiu fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr okf,lr + set_fcc 0xf 0 + ftiu fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/ftiue.cgs b/sim/testsuite/sim/frv/ftiue.cgs new file mode 100644 index 0000000..3111434 --- /dev/null +++ b/sim/testsuite/sim/frv/ftiue.cgs @@ -0,0 +1,108 @@ +# frv testcase for ftiue $FCCi_2,$GRi,$s12 +# mach: all + + .include "testutils.inc" + + start + + .global ftiue +ftiue: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + + set_spr_addr bad,lr + set_fcc 0x0 0 + ftiue fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok1,lr + set_fcc 0x1 0 + ftiue fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok1: + set_spr_addr bad,lr + set_fcc 0x2 0 + ftiue fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok3,lr + set_fcc 0x3 0 + ftiue fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_spr_addr bad,lr + set_fcc 0x4 0 + ftiue fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok5,lr + set_fcc 0x5 0 + ftiue fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_spr_addr bad,lr + set_fcc 0x6 0 + ftiue fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok7,lr + set_fcc 0x7 0 + ftiue fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_psr_et 1 + set_spr_addr ok8,lr + set_fcc 0x8 0 + ftiue fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok8: + set_psr_et 1 + set_spr_addr ok9,lr + set_fcc 0x9 0 + ftiue fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_psr_et 1 + set_spr_addr oka,lr + set_fcc 0xa 0 + ftiue fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_fcc 0xb 0 + ftiue fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_psr_et 1 + set_spr_addr okc,lr + set_fcc 0xc 0 + ftiue fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_fcc 0xd 0 + ftiue fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_fcc 0xe 0 + ftiue fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_fcc 0xf 0 + ftiue fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/ftiug.cgs b/sim/testsuite/sim/frv/ftiug.cgs new file mode 100644 index 0000000..9e16f89 --- /dev/null +++ b/sim/testsuite/sim/frv/ftiug.cgs @@ -0,0 +1,108 @@ +# frv testcase for ftiug $FCCi_2,$GRi,$s12 +# mach: all + + .include "testutils.inc" + + start + + .global ftiug +ftiug: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + + set_spr_addr bad,lr + set_fcc 0x0 0 + ftiug fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok1,lr + set_fcc 0x1 0 + ftiug fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok1: + set_psr_et 1 + set_spr_addr ok2,lr + set_fcc 0x2 0 + ftiug fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_psr_et 1 + set_spr_addr ok3,lr + set_fcc 0x3 0 + ftiug fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_spr_addr bad,lr + set_fcc 0x4 0 + ftiug fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok5,lr + set_fcc 0x5 0 + ftiug fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_psr_et 1 + set_spr_addr ok6,lr + set_fcc 0x6 0 + ftiug fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_fcc 0x7 0 + ftiug fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_spr_addr bad,lr + set_fcc 0x8 0 + ftiug fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok9,lr + set_fcc 0x9 0 + ftiug fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_psr_et 1 + set_spr_addr oka,lr + set_fcc 0xa 0 + ftiug fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_fcc 0xb 0 + ftiug fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_spr_addr bad,lr + set_fcc 0xc 0 + ftiug fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr okd,lr + set_fcc 0xd 0 + ftiug fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_fcc 0xe 0 + ftiug fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_fcc 0xf 0 + ftiug fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/ftiuge.cgs b/sim/testsuite/sim/frv/ftiuge.cgs new file mode 100644 index 0000000..bda587e --- /dev/null +++ b/sim/testsuite/sim/frv/ftiuge.cgs @@ -0,0 +1,112 @@ +# frv testcase for ftiuge $FCCi_2,$GRi,$s12 +# mach: all + + .include "testutils.inc" + + start + + .global ftiuge +ftiuge: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + + set_spr_addr bad,lr + set_fcc 0x0 0 + ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok1,lr + set_fcc 0x1 0 + ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok1: + set_psr_et 1 + set_spr_addr ok2,lr + set_fcc 0x2 0 + ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_psr_et 1 + set_spr_addr ok3,lr + set_fcc 0x3 0 + ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_spr_addr bad,lr + set_fcc 0x4 0 + ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok5,lr + set_fcc 0x5 0 + ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_psr_et 1 + set_spr_addr ok6,lr + set_fcc 0x6 0 + ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_fcc 0x7 0 + ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_psr_et 1 + set_spr_addr ok8,lr + set_fcc 0x8 0 + ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok8: + set_psr_et 1 + set_spr_addr ok9,lr + set_fcc 0x9 0 + ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_psr_et 1 + set_spr_addr oka,lr + set_fcc 0xa 0 + ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_fcc 0xb 0 + ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_psr_et 1 + set_spr_addr okc,lr + set_fcc 0xc 0 + ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_fcc 0xd 0 + ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_fcc 0xe 0 + ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_fcc 0xf 0 + ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/ftiul.cgs b/sim/testsuite/sim/frv/ftiul.cgs new file mode 100644 index 0000000..ee5e2ba --- /dev/null +++ b/sim/testsuite/sim/frv/ftiul.cgs @@ -0,0 +1,108 @@ +# frv testcase for ftiul $FCCi_2,$GRi,$s12 +# mach: all + + .include "testutils.inc" + + start + + .global ftiul +ftiul: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + + set_spr_addr bad,lr + set_fcc 0x0 0 + ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok1,lr + set_fcc 0x1 0 + ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok1: + set_spr_addr bad,lr + set_fcc 0x2 0 + ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok3,lr + set_fcc 0x3 0 + ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_psr_et 1 + set_spr_addr ok4,lr + set_fcc 0x4 0 + ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok4: + set_psr_et 1 + set_spr_addr ok5,lr + set_fcc 0x5 0 + ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_psr_et 1 + set_spr_addr ok6,lr + set_fcc 0x6 0 + ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_fcc 0x7 0 + ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_spr_addr bad,lr + set_fcc 0x8 0 + ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok9,lr + set_fcc 0x9 0 + ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_spr_addr bad,lr + set_fcc 0xa 0 + ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr okb,lr + set_fcc 0xb 0 + ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_psr_et 1 + set_spr_addr okc,lr + set_fcc 0xc 0 + ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_fcc 0xd 0 + ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_fcc 0xe 0 + ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_fcc 0xf 0 + ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/ftle.cgs b/sim/testsuite/sim/frv/ftle.cgs new file mode 100644 index 0000000..4ffa760 --- /dev/null +++ b/sim/testsuite/sim/frv/ftle.cgs @@ -0,0 +1,109 @@ +# frv testcase for ftle $FCCi_2,$GRi,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global ftle +ftle: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_spr_addr bad,lr + set_fcc 0x0 0 + ftle fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x1 0 + ftle fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x2 0 + ftle fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x3 0 + ftle fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok4,lr + set_fcc 0x4 0 + ftle fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok4: + set_psr_et 1 + set_spr_addr ok5,lr + set_fcc 0x5 0 + ftle fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_psr_et 1 + set_spr_addr ok6,lr + set_fcc 0x6 0 + ftle fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_fcc 0x7 0 + ftle fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_psr_et 1 + set_spr_addr ok8,lr + set_fcc 0x8 0 + ftle fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok8: + set_psr_et 1 + set_spr_addr ok9,lr + set_fcc 0x9 0 + ftle fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_psr_et 1 + set_spr_addr oka,lr + set_fcc 0xa 0 + ftle fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_fcc 0xb 0 + ftle fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_psr_et 1 + set_spr_addr okc,lr + set_fcc 0xc 0 + ftle fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_fcc 0xd 0 + ftle fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_fcc 0xe 0 + ftle fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_fcc 0xf 0 + ftle fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/ftlg.cgs b/sim/testsuite/sim/frv/ftlg.cgs new file mode 100644 index 0000000..a72f502 --- /dev/null +++ b/sim/testsuite/sim/frv/ftlg.cgs @@ -0,0 +1,109 @@ +# frv testcase for ftlg $FCCi_2,$GRi,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global ftlg +ftlg: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_spr_addr bad,lr + set_fcc 0x0 0 + ftlg fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x1 0 + ftlg fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok2,lr + set_fcc 0x2 0 + ftlg fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_psr_et 1 + set_spr_addr ok3,lr + set_fcc 0x3 0 + ftlg fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_psr_et 1 + set_spr_addr ok4,lr + set_fcc 0x4 0 + ftlg fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok4: + set_psr_et 1 + set_spr_addr ok5,lr + set_fcc 0x5 0 + ftlg fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_psr_et 1 + set_spr_addr ok6,lr + set_fcc 0x6 0 + ftlg fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_fcc 0x7 0 + ftlg fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_spr_addr bad,lr + set_fcc 0x8 0 + ftlg fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x9 0 + ftlg fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr oka,lr + set_fcc 0xa 0 + ftlg fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_fcc 0xb 0 + ftlg fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_psr_et 1 + set_spr_addr okc,lr + set_fcc 0xc 0 + ftlg fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_fcc 0xd 0 + ftlg fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_fcc 0xe 0 + ftlg fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_fcc 0xf 0 + ftlg fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/ftlt.cgs b/sim/testsuite/sim/frv/ftlt.cgs new file mode 100644 index 0000000..c934313 --- /dev/null +++ b/sim/testsuite/sim/frv/ftlt.cgs @@ -0,0 +1,101 @@ +# frv testcase for ftlt $FCCi_2,$GRi,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global ftlt +ftlt: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_spr_addr bad,lr + set_fcc 0x0 0 + ftlt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x1 0 + ftlt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x2 0 + ftlt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x3 0 + ftlt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok4,lr + set_fcc 0x4 0 + ftlt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok4: + set_psr_et 1 + set_spr_addr ok5,lr + set_fcc 0x5 0 + ftlt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_psr_et 1 + set_spr_addr ok6,lr + set_fcc 0x6 0 + ftlt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_fcc 0x7 0 + ftlt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_spr_addr bad,lr + set_fcc 0x8 0 + ftlt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x9 0 + ftlt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0xa 0 + ftlt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0xb 0 + ftlt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr okc,lr + set_fcc 0xc 0 + ftlt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_fcc 0xd 0 + ftlt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_fcc 0xe 0 + ftlt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_fcc 0xf 0 + ftlt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/ftne.cgs b/sim/testsuite/sim/frv/ftne.cgs new file mode 100644 index 0000000..03b9857 --- /dev/null +++ b/sim/testsuite/sim/frv/ftne.cgs @@ -0,0 +1,113 @@ +# frv testcase for ftne $FCCi_2,$GRi,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global ftne +ftne: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_spr_addr bad,lr + set_fcc 0x0 0 + ftne fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok1,lr + set_fcc 0x1 0 + ftne fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok1: + set_psr_et 1 + set_spr_addr ok2,lr + set_fcc 0x2 0 + ftne fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_psr_et 1 + set_spr_addr ok3,lr + set_fcc 0x3 0 + ftne fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_psr_et 1 + set_spr_addr ok4,lr + set_fcc 0x4 0 + ftne fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok4: + set_psr_et 1 + set_spr_addr ok5,lr + set_fcc 0x5 0 + ftne fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_psr_et 1 + set_spr_addr ok6,lr + set_fcc 0x6 0 + ftne fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_fcc 0x7 0 + ftne fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_spr_addr bad,lr + set_fcc 0x8 0 + ftne fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok9,lr + set_fcc 0x9 0 + ftne fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_psr_et 1 + set_spr_addr oka,lr + set_fcc 0xa 0 + ftne fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_fcc 0xb 0 + ftne fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_psr_et 1 + set_spr_addr okc,lr + set_fcc 0xc 0 + ftne fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_fcc 0xd 0 + ftne fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_fcc 0xe 0 + ftne fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_fcc 0xf 0 + ftne fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/ftno.cgs b/sim/testsuite/sim/frv/ftno.cgs new file mode 100644 index 0000000..bada522 --- /dev/null +++ b/sim/testsuite/sim/frv/ftno.cgs @@ -0,0 +1,54 @@ +# frv testcase for ftno +# mach: all + + .include "testutils.inc" + + start + + .global ftnev +ftnev: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_mem_limmed 0x0038,0x2000,gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_fcc 0x0 0 + ftno ; should branch to tbr + (128 + 4)*16 + set_fcc 0x1 0 + ftno ; should branch to tbr + (128 + 4)*16 + set_fcc 0x2 0 + ftno ; should branch to tbr + (128 + 4)*16 + set_fcc 0x3 0 + ftno ; should branch to tbr + (128 + 4)*16 + set_fcc 0x4 0 + ftno ; should branch to tbr + (128 + 4)*16 + set_fcc 0x5 0 + ftno ; should branch to tbr + (128 + 4)*16 + set_fcc 0x6 0 + ftno ; should branch to tbr + (128 + 4)*16 + set_fcc 0x7 0 + ftno ; should branch to tbr + (128 + 4)*16 + set_fcc 0x8 0 + ftno ; should branch to tbr + (128 + 4)*16 + set_fcc 0x9 0 + ftno ; should branch to tbr + (128 + 4)*16 + set_fcc 0xa 0 + ftno ; should branch to tbr + (128 + 4)*16 + set_fcc 0xb 0 + ftno ; should branch to tbr + (128 + 4)*16 + set_fcc 0xc 0 + ftno ; should branch to tbr + (128 + 4)*16 + set_fcc 0xd 0 + ftno ; should branch to tbr + (128 + 4)*16 + set_fcc 0xe 0 + ftno ; should branch to tbr + (128 + 4)*16 + set_fcc 0xf 0 + ftno ; should branch to tbr + (128 + 4)*16 + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/fto.cgs b/sim/testsuite/sim/frv/fto.cgs new file mode 100644 index 0000000..82035f4 --- /dev/null +++ b/sim/testsuite/sim/frv/fto.cgs @@ -0,0 +1,113 @@ +# frv testcase for fto $FCCi_2,$GRi,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global fto +fto: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_spr_addr bad,lr + set_fcc 0x0 0 + fto fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x1 0 + fto fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok2,lr + set_fcc 0x2 0 + fto fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_psr_et 1 + set_spr_addr ok3,lr + set_fcc 0x3 0 + fto fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_psr_et 1 + set_spr_addr ok4,lr + set_fcc 0x4 0 + fto fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok4: + set_psr_et 1 + set_spr_addr ok5,lr + set_fcc 0x5 0 + fto fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_psr_et 1 + set_spr_addr ok6,lr + set_fcc 0x6 0 + fto fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_fcc 0x7 0 + fto fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_psr_et 1 + set_spr_addr ok8,lr + set_fcc 0x8 0 + fto fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok8: + set_psr_et 1 + set_spr_addr ok9,lr + set_fcc 0x9 0 + fto fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_psr_et 1 + set_spr_addr oka,lr + set_fcc 0xa 0 + fto fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_fcc 0xb 0 + fto fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_psr_et 1 + set_spr_addr okc,lr + set_fcc 0xc 0 + fto fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_fcc 0xd 0 + fto fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_fcc 0xe 0 + fto fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_fcc 0xf 0 + fto fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/ftra.cgs b/sim/testsuite/sim/frv/ftra.cgs new file mode 100644 index 0000000..7754f69 --- /dev/null +++ b/sim/testsuite/sim/frv/ftra.cgs @@ -0,0 +1,115 @@ +# frv testcase for ftra $GRi,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global ftra +ftra: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_psr_et 1 + set_spr_addr ok0,lr + set_fcc 0x0 0 + ftra gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok0: + set_psr_et 1 + set_spr_addr ok1,lr + set_fcc 0x1 0 + ftra gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok1: + set_psr_et 1 + set_spr_addr ok2,lr + set_fcc 0x2 0 + ftra gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_psr_et 1 + set_spr_addr ok3,lr + set_fcc 0x3 0 + ftra gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_psr_et 1 + set_spr_addr ok4,lr + set_fcc 0x4 0 + ftra gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok4: + set_psr_et 1 + set_spr_addr ok5,lr + set_fcc 0x5 0 + ftra gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_psr_et 1 + set_spr_addr ok6,lr + set_fcc 0x6 0 + ftra gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_fcc 0x7 0 + ftra gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_psr_et 1 + set_spr_addr ok8,lr + set_fcc 0x8 0 + ftra gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok8: + set_psr_et 1 + set_spr_addr ok9,lr + set_fcc 0x9 0 + ftra gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_psr_et 1 + set_spr_addr oka,lr + set_fcc 0xa 0 + ftra gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_fcc 0xb 0 + ftra gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_psr_et 1 + set_spr_addr okc,lr + set_fcc 0xc 0 + ftra gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_fcc 0xd 0 + ftra gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_fcc 0xe 0 + ftra gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_fcc 0xf 0 + ftra gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass diff --git a/sim/testsuite/sim/frv/ftu.cgs b/sim/testsuite/sim/frv/ftu.cgs new file mode 100644 index 0000000..354423b --- /dev/null +++ b/sim/testsuite/sim/frv/ftu.cgs @@ -0,0 +1,101 @@ +# frv testcase for ftu $FCCi_2,$GRi,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global ftu +ftu: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_spr_addr bad,lr + set_fcc 0x0 0 + ftu fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok1,lr + set_fcc 0x1 0 + ftu fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok1: + set_spr_addr bad,lr + set_fcc 0x2 0 + ftu fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok3,lr + set_fcc 0x3 0 + ftu fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_spr_addr bad,lr + set_fcc 0x4 0 + ftu fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok5,lr + set_fcc 0x5 0 + ftu fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_spr_addr bad,lr + set_fcc 0x6 0 + ftu fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok7,lr + set_fcc 0x7 0 + ftu fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_spr_addr bad,lr + set_fcc 0x8 0 + ftu fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok9,lr + set_fcc 0x9 0 + ftu fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_spr_addr bad,lr + set_fcc 0xa 0 + ftu fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr okb,lr + set_fcc 0xb 0 + ftu fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_spr_addr bad,lr + set_fcc 0xc 0 + ftu fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr okd,lr + set_fcc 0xd 0 + ftu fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_spr_addr bad,lr + set_fcc 0xe 0 + ftu fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr okf,lr + set_fcc 0xf 0 + ftu fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/ftue.cgs b/sim/testsuite/sim/frv/ftue.cgs new file mode 100644 index 0000000..564bb30 --- /dev/null +++ b/sim/testsuite/sim/frv/ftue.cgs @@ -0,0 +1,109 @@ +# frv testcase for ftue $FCCi_2,$GRi,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global ftue +ftue: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_spr_addr bad,lr + set_fcc 0x0 0 + ftue fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok1,lr + set_fcc 0x1 0 + ftue fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok1: + set_spr_addr bad,lr + set_fcc 0x2 0 + ftue fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok3,lr + set_fcc 0x3 0 + ftue fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_spr_addr bad,lr + set_fcc 0x4 0 + ftue fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok5,lr + set_fcc 0x5 0 + ftue fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_spr_addr bad,lr + set_fcc 0x6 0 + ftue fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok7,lr + set_fcc 0x7 0 + ftue fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_psr_et 1 + set_spr_addr ok8,lr + set_fcc 0x8 0 + ftue fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok8: + set_psr_et 1 + set_spr_addr ok9,lr + set_fcc 0x9 0 + ftue fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_psr_et 1 + set_spr_addr oka,lr + set_fcc 0xa 0 + ftue fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_fcc 0xb 0 + ftue fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_psr_et 1 + set_spr_addr okc,lr + set_fcc 0xc 0 + ftue fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_fcc 0xd 0 + ftue fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_fcc 0xe 0 + ftue fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_fcc 0xf 0 + ftue fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/ftug.cgs b/sim/testsuite/sim/frv/ftug.cgs new file mode 100644 index 0000000..cc6a405 --- /dev/null +++ b/sim/testsuite/sim/frv/ftug.cgs @@ -0,0 +1,109 @@ +# frv testcase for ftug $FCCi_2,$GRi,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global ftug +ftug: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_spr_addr bad,lr + set_fcc 0x0 0 + ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok1,lr + set_fcc 0x1 0 + ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok1: + set_psr_et 1 + set_spr_addr ok2,lr + set_fcc 0x2 0 + ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_psr_et 1 + set_spr_addr ok3,lr + set_fcc 0x3 0 + ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_spr_addr bad,lr + set_fcc 0x4 0 + ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok5,lr + set_fcc 0x5 0 + ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_psr_et 1 + set_spr_addr ok6,lr + set_fcc 0x6 0 + ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_fcc 0x7 0 + ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_spr_addr bad,lr + set_fcc 0x8 0 + ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok9,lr + set_fcc 0x9 0 + ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_psr_et 1 + set_spr_addr oka,lr + set_fcc 0xa 0 + ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_fcc 0xb 0 + ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_spr_addr bad,lr + set_fcc 0xc 0 + ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr okd,lr + set_fcc 0xd 0 + ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_fcc 0xe 0 + ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_fcc 0xf 0 + ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/ftuge.cgs b/sim/testsuite/sim/frv/ftuge.cgs new file mode 100644 index 0000000..7c04eaf --- /dev/null +++ b/sim/testsuite/sim/frv/ftuge.cgs @@ -0,0 +1,113 @@ +# frv testcase for ftuge $FCCi_2,$GRi,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global ftuge +ftuge: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_spr_addr bad,lr + set_fcc 0x0 0 + ftuge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok1,lr + set_fcc 0x1 0 + ftuge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok1: + set_psr_et 1 + set_spr_addr ok2,lr + set_fcc 0x2 0 + ftuge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_psr_et 1 + set_spr_addr ok3,lr + set_fcc 0x3 0 + ftuge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_spr_addr bad,lr + set_fcc 0x4 0 + ftuge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok5,lr + set_fcc 0x5 0 + ftuge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_psr_et 1 + set_spr_addr ok6,lr + set_fcc 0x6 0 + ftuge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_fcc 0x7 0 + ftuge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_psr_et 1 + set_spr_addr ok8,lr + set_fcc 0x8 0 + ftuge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok8: + set_psr_et 1 + set_spr_addr ok9,lr + set_fcc 0x9 0 + ftuge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_psr_et 1 + set_spr_addr oka,lr + set_fcc 0xa 0 + ftuge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_fcc 0xb 0 + ftuge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_psr_et 1 + set_spr_addr okc,lr + set_fcc 0xc 0 + ftuge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_fcc 0xd 0 + ftuge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_fcc 0xe 0 + ftuge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_fcc 0xf 0 + ftuge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/ftul.cgs b/sim/testsuite/sim/frv/ftul.cgs new file mode 100644 index 0000000..b45ebb3 --- /dev/null +++ b/sim/testsuite/sim/frv/ftul.cgs @@ -0,0 +1,109 @@ +# frv testcase for ftul $FCCi_2,$GRi,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global ftul +ftul: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_spr_addr bad,lr + set_fcc 0x0 0 + ftul fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok1,lr + set_fcc 0x1 0 + ftul fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok1: + set_spr_addr bad,lr + set_fcc 0x2 0 + ftul fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok3,lr + set_fcc 0x3 0 + ftul fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_psr_et 1 + set_spr_addr ok4,lr + set_fcc 0x4 0 + ftul fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok4: + set_psr_et 1 + set_spr_addr ok5,lr + set_fcc 0x5 0 + ftul fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_psr_et 1 + set_spr_addr ok6,lr + set_fcc 0x6 0 + ftul fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_fcc 0x7 0 + ftul fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_spr_addr bad,lr + set_fcc 0x8 0 + ftul fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok9,lr + set_fcc 0x9 0 + ftul fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_spr_addr bad,lr + set_fcc 0xa 0 + ftul fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr okb,lr + set_fcc 0xb 0 + ftul fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_psr_et 1 + set_spr_addr okc,lr + set_fcc 0xc 0 + ftul fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_fcc 0xd 0 + ftul fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_fcc 0xe 0 + ftul fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_fcc 0xf 0 + ftul fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/ftule.cgs b/sim/testsuite/sim/frv/ftule.cgs new file mode 100644 index 0000000..4a93260 --- /dev/null +++ b/sim/testsuite/sim/frv/ftule.cgs @@ -0,0 +1,113 @@ +# frv testcase for ftule $FCCi_2,$GRi,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global ftule +ftule: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_spr_addr bad,lr + set_fcc 0x0 0 + ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok1,lr + set_fcc 0x1 0 + ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok1: + set_spr_addr bad,lr + set_fcc 0x2 0 + ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok3,lr + set_fcc 0x3 0 + ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_psr_et 1 + set_spr_addr ok4,lr + set_fcc 0x4 0 + ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok4: + set_psr_et 1 + set_spr_addr ok5,lr + set_fcc 0x5 0 + ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_psr_et 1 + set_spr_addr ok6,lr + set_fcc 0x6 0 + ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_fcc 0x7 0 + ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_psr_et 1 + set_spr_addr ok8,lr + set_fcc 0x8 0 + ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok8: + set_psr_et 1 + set_spr_addr ok9,lr + set_fcc 0x9 0 + ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_psr_et 1 + set_spr_addr oka,lr + set_fcc 0xa 0 + ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_fcc 0xb 0 + ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_psr_et 1 + set_spr_addr okc,lr + set_fcc 0xc 0 + ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_fcc 0xd 0 + ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_fcc 0xe 0 + ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_fcc 0xf 0 + ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/icei.cgs b/sim/testsuite/sim/frv/icei.cgs new file mode 100644 index 0000000..aac925b --- /dev/null +++ b/sim/testsuite/sim/frv/icei.cgs @@ -0,0 +1,15 @@ +# frv testcase for icei @(GRi,GRj),a +# mach: fr400 fr550 + + .include "testutils.inc" + + start + + .global icei +icei: + ; Can't really test this because of SCACHE implementation + set_gr_addr icei,gr10 + icei @(gr10,gr0),1 + icei @(gr10,gr0),1 + + pass diff --git a/sim/testsuite/sim/frv/ici.cgs b/sim/testsuite/sim/frv/ici.cgs new file mode 100644 index 0000000..8aeacae --- /dev/null +++ b/sim/testsuite/sim/frv/ici.cgs @@ -0,0 +1,39 @@ +# FRV testcase for ici @(GRi,GRj) +# mach: all + + .include "testutils.inc" + + start + + .global ici +ici: + set_gr_immed 1234,gr2 + set_spr_addr ok1,lr + bra testit + +ok1: + ; Change the first insn to set gr1 to 1235 + ; but don't invalidate the insn cache + ; should have no effect + set_gr_mem testit,gr10 + ori gr10,1,gr10 + set_mem_gr gr10,testit + set_gr_addr testit,gr10 + dcf @(gr10,gr0) ; flush data cache + set_spr_addr ok2,lr + bra testit + +ok2: ; Now invalidate the insn cache. The new insn should take effect + ici @(gr10,gr0) + set_gr_immed 1235,gr2 + set_spr_addr ok3,lr + bra testit + +ok3: + pass + +testit: + setlos 1234,gr1 + test_gr_gr gr1,gr2 + bralr + fail diff --git a/sim/testsuite/sim/frv/icpl.cgs b/sim/testsuite/sim/frv/icpl.cgs new file mode 100644 index 0000000..b86ba35 --- /dev/null +++ b/sim/testsuite/sim/frv/icpl.cgs @@ -0,0 +1,39 @@ +# FRV testcase for icpl GRi,GRj,lock +# mach: all + + .include "testutils.inc" + + start + + .global icpl + ; keep this at least 64 bytes away from doit2 + bra icpl +doit1: add gr11,gr12,gr11 + bralr + +icpl: + or_spr_immed 0x80000000,hsr0 ; insn cache: enable + and_spr_immed 0xbfffffff,hsr0 ; data cache: disable + set_gr_immed 0,gr11 + set_gr_immed 1,gr12 + set_gr_immed 2,gr13 + + set_gr_addr doit1,gr10 + icpl gr10,gr0,0 ; preload insns at doit1 + set_mem_immed 0x9600b00d,gr10 ; change to add gr11,gr13,gr11 + + set_gr_addr doit2,gr10 + set_mem_immed 0x9600b00d,gr10 ; change to add gr11,gr13,gr11 + + set_spr_addr ok1,lr + bra doit1 +ok1: test_gr_immed 1,gr11 ; used preloaded add of 1 + + set_spr_addr ok2,lr + bra doit2 +ok2: test_gr_immed 3,gr11 ; used changed add of 2 + + pass + +doit2: add gr11,gr12,gr11 + bralr diff --git a/sim/testsuite/sim/frv/icul.cgs b/sim/testsuite/sim/frv/icul.cgs new file mode 100644 index 0000000..b112f41 --- /dev/null +++ b/sim/testsuite/sim/frv/icul.cgs @@ -0,0 +1,53 @@ +# FRV testcase for icul $GRi +# mach: all + + .include "testutils.inc" + + start + + .global icul +icul: + or_spr_immed 0xc8000000,hsr0 ; caches enabled -- copy-back mode + + ; preload and lock all the lines in set 0 of the insn cache + set_gr_immed 0x70000,gr10 + set_bctrlr_0_0 gr10 + lock_insn_cache gr10 + + inc_gr_immed 0x1000,gr10 + set_bctrlr_0_0 gr10 + lock_insn_cache gr10 + + inc_gr_immed 0x1000,gr10 + set_bctrlr_0_0 gr10 + lock_insn_cache gr10 + + inc_gr_immed 0x1000,gr10 + set_bctrlr_0_0 gr10 + lock_insn_cache gr10 + + ; execute the pre-loaded insn + set_gr_immed 0x70000,gr10 + calll @(gr10,gr0) ; should come right back + inc_gr_immed 0x1000,gr10 + calll @(gr10,gr0) ; should come right back + inc_gr_immed 0x1000,gr10 + calll @(gr10,gr0) ; should come right back + inc_gr_immed 0x1000,gr10 + calll @(gr10,gr0) ; should come right back + + ; Now execute another insn which would have gone into set 0. + inc_gr_immed 0x1000,gr10 + set_bctrlr_0_0 gr10 + set_spr_immed 128,lcr + calll @(gr10,gr0) ; should come right back + + ; Now unlock one of the lines and do it again + set_gr_immed 0x71000,gr10 + icul gr10 + calll @(gr10,gr0) ; should come right back + + inc_gr_immed 0x3000,gr10 + calll @(gr10,gr0) ; should come right back + + pass diff --git a/sim/testsuite/sim/frv/interrupts.exp b/sim/testsuite/sim/frv/interrupts.exp new file mode 100644 index 0000000..e31533e --- /dev/null +++ b/sim/testsuite/sim/frv/interrupts.exp @@ -0,0 +1,19 @@ +# FRV simulator testsuite. + +if [istarget frv*-*] { + # load support procs (none yet) + # load_lib cgen.exp + # all machines + set all_machs "frv fr500 fr550 fr400" + set cpu_option -mcpu + + # The .cgs suffix is for "cgen .s". + foreach src [lsort [glob -nocomplain $srcdir/$subdir/interrupts/*.cgs]] { + # If we're only testing specific files and this isn't one of them, + # skip it. + if ![runtest_file_p $runtests $src] { + continue + } + run_sim_test $src $all_machs + } +} diff --git a/sim/testsuite/sim/frv/interrupts/Ipipe-fr400.cgs b/sim/testsuite/sim/frv/interrupts/Ipipe-fr400.cgs new file mode 100644 index 0000000..dad9f0e --- /dev/null +++ b/sim/testsuite/sim/frv/interrupts/Ipipe-fr400.cgs @@ -0,0 +1,35 @@ +# frv testcase +# mach: fr400 + + .include "testutils.inc" + + start + + .global Ipipe +Ipipe: + ; Clear the packing bit of the insn at 'pack:'. We can't + ; simply use '.p' because the assembler will catch the error. + set_gr_mem pack,gr10 + and_gr_immed 0x7fffffff,gr10 + set_mem_gr gr10,pack + set_gr_addr pack,gr10 + flush_data_cache gr10 + + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 0x070,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 + set_spr_immed 128,lcr + set_spr_addr ok0,lr + set_psr_et 1 + +bundle: add.p gr1,gr1,gr1 +pack: add gr2,gr2,gr2 +bad: add gr3,gr3,gr3 + fail +ok0: + test_spr_immed 1,esfr1 + test_spr_bits 0x3f,0,0xb,esr0 + test_spr_addr bundle,epcr0 + + pass diff --git a/sim/testsuite/sim/frv/interrupts/Ipipe-fr500.cgs b/sim/testsuite/sim/frv/interrupts/Ipipe-fr500.cgs new file mode 100644 index 0000000..b4dd770 --- /dev/null +++ b/sim/testsuite/sim/frv/interrupts/Ipipe-fr500.cgs @@ -0,0 +1,35 @@ +# frv testcase +# mach: fr500 + + .include "testutils.inc" + + start + + .global Ipipe +Ipipe: + ; Clear the packing bit of the insn at 'pack:'. We can't + ; simply use '.p' because the assembler will catch the error. + set_gr_mem pack,gr10 + and_gr_immed 0x7fffffff,gr10 + set_mem_gr gr10,pack + set_gr_addr pack,gr10 + flush_data_cache gr10 + + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 0x070,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 + set_spr_immed 128,lcr + set_spr_addr ok0,lr + set_psr_et 1 + + add.p gr1,gr1,gr1 +pack: add gr2,gr2,gr2 +bad: add gr3,gr3,gr3 + fail +ok0: + test_spr_immed 1,esfr1 + test_spr_bits 0x3f,0,0xb,esr0 + test_spr_addr bad,epcr0 + + pass diff --git a/sim/testsuite/sim/frv/interrupts/badalign-fr550.cgs b/sim/testsuite/sim/frv/interrupts/badalign-fr550.cgs new file mode 100644 index 0000000..6c0369b --- /dev/null +++ b/sim/testsuite/sim/frv/interrupts/badalign-fr550.cgs @@ -0,0 +1,42 @@ +# frv testcase to generate interrupt for st $GRk,@($GRi,$GRj) +# mach: fr550 + .include "testutils.inc" + + start + + .global align +align: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr17 + inc_gr_immed 0x100,gr17 ; address of exception handler + set_bctrlr_0_0 gr17 + set_spr_immed 128,lcr + set_psr_et 1 + set_gr_immed 0xdeadbeef,gr17 + set_gr_immed 0,gr15 + inc_gr_immed 2,sp ; out of alignment + + test_spr_bits 1,0,0,isr ; ISR.EMAM always clear (not used) + sti gr17,@(sp,0) ; no exception + sti gr17,@(sp,4) ; no exception + ldi @(sp,0),gr18 ; stored at unaligned address + test_gr_immed 0xdeadbeef,gr18 + ldi @(sp,0),gr19 ; no exception + test_gr_immed 0xdeadbeef,gr19 + + and_spr_immed 0xfffffffe,isr ; turn off ISR.EMAM + sti gr17,@(sp,0) ; misaligned -- no exception + test_gr_immed 0,gr15 + + set_gr_gr sp,gr20 + set_gr_immed 1,gr21 + set_gr_immed 0x10101010,gr10 + nop.p + ldu @(sp,gr21),gr10 ; misaligned read no exception + test_gr_immed 0,gr15 ; handler was not called + test_gr_immed 0xadbeefde,gr10 ; gr10 updated + test_gr_immed 1,gr21 ; gr21 not updated + inc_gr_immed 1,gr20 + test_gr_gr gr20,sp ; sp updated + + pass diff --git a/sim/testsuite/sim/frv/interrupts/badalign.cgs b/sim/testsuite/sim/frv/interrupts/badalign.cgs new file mode 100644 index 0000000..b866021 --- /dev/null +++ b/sim/testsuite/sim/frv/interrupts/badalign.cgs @@ -0,0 +1,73 @@ +# frv testcase to generate interrupt for st $GRk,@($GRi,$GRj) +# mach: fr500 frv + .include "testutils.inc" + + start + + .global align +align: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr17 + inc_gr_immed 0x100,gr17 ; address of exception handler + set_bctrlr_0_0 gr17 + set_spr_immed 128,lcr + set_spr_addr ok1,lr + set_psr_et 1 + set_gr_immed 0xdeadbeef,gr17 + set_gr_immed 0,gr15 + inc_gr_immed 2,sp ; out of alignment + + test_spr_bits 1,0,1,isr ; mem_address_not_aligned is masked + sti gr17,@(sp,0) ; no exception + ldi @(sp,-2),gr18 ; stored at aligned address + test_gr_immed 0xdeadbeef,gr18 + ldi @(sp,0),gr19 ; no exception + test_gr_immed 0xdeadbeef,gr19 + + and_spr_immed 0xfffffffe,isr ; turn off ISR.EMAM + set_gr_addr bad1,gr16 +bad1: sti gr17,@(sp,0) ; misaligned write in slot I1 + test_gr_immed 1,gr15 + + set_gr_addr bad3,gr16 + set_gr_gr sp,gr20 + set_gr_immed 1,gr21 + set_gr_immed 0x10101010,gr10 +bad2: nop.p +bad3: ldu @(sp,gr21),gr10 ; misaligned read in slot I2 + test_gr_immed 2,gr15 ; handler was called + test_gr_immed 0x10101010,gr10 ; gr10 not updated + test_gr_immed 1,gr21 ; gr21 not updated + inc_gr_immed 1,gr20 + test_gr_gr gr20,sp ; sp updated + + pass + +; exception handler +ok1: + cmpi gr15,0,icc0 + bne icc0,0,load + ; handle interrupt on store + test_spr_immed 0x100,esfr1 ; esr8 is active + test_spr_gr epcr8,gr16 + test_spr_bits 0x0001,0,0x1,esr8 ; esr8 is valid + test_spr_bits 0x003e,1,0xb,esr8 ; esr8.ec is set + test_spr_bits 0x0800,11,0x1,esr8 ; esr8.eav is set + test_spr_gr ear8,sp + test_spr_bits 0x01000,12,0x1,esr8 ; esr8.edv is set + test_spr_bits 0x1e000,13,0x3,esr8 ; esr8.edn is 3 + test_spr_gr edr3,gr17 ; edr3 is set + bra ret +load: + ; handle interrupt on load + test_spr_immed 0x200,esfr1 ; esr9 is active + test_spr_gr epcr9,gr16 + test_spr_bits 0x0001,0,0x1,esr9 ; esr9 is valid + test_spr_bits 0x003e,1,0xb,esr9 ; esr9.ec is set + test_spr_bits 0x0800,11,0x1,esr9 ; esr9.eav is set + test_spr_gr ear9,sp + test_spr_bits 0x1000,12,0x0,esr9 ; esr9.edv is not set +ret: + inc_gr_immed 1,gr15 + rett 0 + fail diff --git a/sim/testsuite/sim/frv/interrupts/compound-fr550.cgs b/sim/testsuite/sim/frv/interrupts/compound-fr550.cgs new file mode 100644 index 0000000..7cd2278 --- /dev/null +++ b/sim/testsuite/sim/frv/interrupts/compound-fr550.cgs @@ -0,0 +1,54 @@ +# frv testcase to generate compound exception +# mach: fr550 + .include "testutils.inc" + + start + + .global align +align: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr17 + inc_gr_immed 0x200,gr17 ; address of exception handler + set_bctrlr_0_0 gr17 + set_spr_immed 128,lcr + set_spr_addr ok1,lr + or_spr_immed 0x04000000,fsr0 ; enabled div/0 fp_exception + set_psr_et 1 + + set_gr_immed 0,gr15 + set_fr_iimmed 0x7f7f,0xffff,fr0 + set_fr_iimmed 0x0000,0x0000,fr1 + + and_spr_immed 0xfffffffe,isr ; enable mem_address_not_aligned + set_gr_addr dividef,gr16 + set_gr_addr dividei,gr17 + set_gr_immed 0xdeadbeef,gr8 + inc_gr_immed 2,sp ; misalign +store: sti.p gr8,@(sp,0) ; misaligned - no exception +dividef:fdivs.p fr0,fr1,fr2 ; fp_exception +dividei:sdiv gr1,gr0,gr1 ; division exception + test_gr_immed 1,gr15 + + pass + +; exception handler +ok1: + ; check fp_exception + test_spr_immed 0x5,esfr1 ; esr2 and esr0 are active + test_spr_gr epcr2,gr16 + test_spr_bits 0x0001,0,0x1,esr2 ; esr2 is valid + test_spr_bits 0x003e,1,0xd,esr2 ; esr2.ec is set + test_spr_bits 0x0800,11,0x0,esr2 ; esr2.eav is clear + + ; check on fp_exception + test_spr_bits 0x100000,20,0x0,fsr0 ; fsr0.qne is clear + test_spr_bits 0xe0000,17,0x1,fsr0 ; fsr0.ftt is set + test_spr_bits 0xfc00,10,0x0,fsr0 ; fsr0.aexc is clear + + ; check interrupt on dividei + test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid + test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set + + inc_gr_immed 1,gr15 + rett 0 + fail diff --git a/sim/testsuite/sim/frv/interrupts/compound.cgs b/sim/testsuite/sim/frv/interrupts/compound.cgs new file mode 100644 index 0000000..2fd928e --- /dev/null +++ b/sim/testsuite/sim/frv/interrupts/compound.cgs @@ -0,0 +1,66 @@ +# frv testcase to generate compound exception +# mach: fr500 frv + .include "testutils.inc" + + start + + .global align +align: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr17 + inc_gr_immed 0x200,gr17 ; address of exception handler + set_bctrlr_0_0 gr17 + set_spr_immed 128,lcr + set_spr_addr ok1,lr + or_spr_immed 0x04000000,fsr0 ; enabled div/0 fp_exception + set_psr_et 1 + + set_gr_immed 0,gr15 + set_fr_iimmed 0x7f7f,0xffff,fr0 + set_fr_iimmed 0x0000,0x0000,fr1 + + and_spr_immed 0xfffffffe,isr ; enable mem_address_not_aligned + set_gr_addr store,gr16 + set_gr_addr dividei,gr17 + set_gr_immed 0xdeadbeef,gr8 + inc_gr_immed 2,sp ; misalign +store: sti.p gr8,@(sp,0) ; misaligned write +dividef:fdivs.p fr0,fr1,fr2 ; fp_exception +dividei:sdiv gr1,gr0,gr1 ; division exception + test_gr_immed 1,gr15 + + pass + +; exception handler +ok1: + ; check interrupt on store + test_spr_immed 0x102,esfr1 ; esr8 and esr1 are active + test_spr_gr epcr8,gr16 + test_spr_bits 0x0001,0,0x1,esr8 ; esr8 is valid + test_spr_bits 0x003e,1,0xb,esr8 ; esr8.ec is set + test_spr_bits 0x0800,11,0x1,esr8 ; esr8.eav is set + test_spr_gr ear8,sp + test_spr_bits 0x01000,12,0x1,esr8 ; esr8.edv is set + test_spr_bits 0x1e000,13,0x3,esr8 ; esr8.edn is 3 + test_spr_gr edr3,gr8 ; edr3 is set + + ; check on fp_exception + test_spr_bits 0x100000,20,0x1,fsr0 ; fsr0.qne is set + test_spr_bits 0xe0000,17,0x1,fsr0 ; fsr0.ftt is set + test_spr_bits 0xfc00,10,0x0,fsr0 ; fsr0.aexc is clear + + test_spr_bits 0x80000000,31,0x0,fqst2 ; fq2.miv is set + test_spr_bits 0x18000,15,0x0,fqst2 ; fq2.sie is set + test_spr_bits 0x380,7,0x1,fqst2 ; fq2.ftt is set + test_spr_bits 0x7e,1,0x4,fqst2 ; fq2.cexc is set + test_spr_bits 0x1,0,0x1,fqst2 ; fq2.valid is set + test_spr_immed 0x05e40241,fqop2 ; fq2.opc + + ; check interrupt on dividei + test_spr_gr epcr1,gr17 + test_spr_bits 0x0001,0,0x1,esr1 ; esr1 is valid + test_spr_bits 0x003e,1,0x13,esr1 ; esr1.ec is set + + inc_gr_immed 1,gr15 + rett 0 + fail diff --git a/sim/testsuite/sim/frv/interrupts/data_store_error-fr550.cgs b/sim/testsuite/sim/frv/interrupts/data_store_error-fr550.cgs new file mode 100644 index 0000000..3924adc --- /dev/null +++ b/sim/testsuite/sim/frv/interrupts/data_store_error-fr550.cgs @@ -0,0 +1,53 @@ +# frv testcase to generate interrupt for st $GRk,@($GRi,$GRj) +# mach: fr550 +# sim(fr550): --memory-region 0xfeff0600,0x8000 --memory-region 0xfe800000,0x7f0010 + .include "testutils.inc" + + start + + .global dsr +dsr: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr17 + inc_gr_immed 0x140,gr17 ; address of exception handler + set_bctrlr_0_0 gr17 + set_spr_immed 128,lcr + set_psr_et 1 + + set_spr_addr ok0,lr + set_gr_immed 0,gr16 + + set_gr_immed 0xdeadbeef,gr15 + set_gr_addr 0xfeff0600,gr17 +bad1: sti gr15,@(gr17,0) ; no interrupt + test_gr_immed 0,gr16 + + set_gr_immed 0xbeefdead,gr15 + set_gr_addr 0xfeff7ffc,gr17 +bad2: sti gr15,@(gr17,0) ; no interrupt + test_gr_immed 0,gr16 + + set_gr_immed 0xbeefbeef,gr15 + set_gr_addr 0xfe800000,gr17 +bad3: sti gr15,@(gr17,0) ; cause interrupt + test_gr_immed 1,gr16 + + set_gr_immed 0xdeaddead,gr15 + set_gr_addr 0xfefefffc,gr17 +bad4: sti gr15,@(gr17,0) ; cause interrupt + test_gr_immed 2,gr16 + + sti gr0,@(sp,0) ; no interrupt + test_gr_immed 2,gr16 + + pass +ok0: + ; check interrupts + test_spr_immed 0x4000,esfr1 ; esr14 is active + test_spr_bits 0x0001,0,0x1,esr14 ; esr14 is valid + test_spr_bits 0x003e,1,0x0,esr14 ; esr14.ec is set + test_spr_bits 0x0800,11,0x0,esr14 ; esr14.eav is not set + + addi gr16,1,gr16 + rett 0 + fail diff --git a/sim/testsuite/sim/frv/interrupts/data_store_error.cgs b/sim/testsuite/sim/frv/interrupts/data_store_error.cgs new file mode 100644 index 0000000..b967d0a --- /dev/null +++ b/sim/testsuite/sim/frv/interrupts/data_store_error.cgs @@ -0,0 +1,53 @@ +# frv testcase to generate interrupt for st $GRk,@($GRi,$GRj) +# mach: fr500 +# sim(fr500): --memory-region 0xfeff0600,0x8000 --memory-region 0xfe800000,0x7f0010 + .include "testutils.inc" + + start + + .global dsr +dsr: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr17 + inc_gr_immed 0x140,gr17 ; address of exception handler + set_bctrlr_0_0 gr17 + set_spr_immed 128,lcr + set_psr_et 1 + + set_spr_addr ok0,lr + set_gr_immed 0,gr16 + + set_gr_immed 0xdeadbeef,gr15 + set_gr_addr 0xfeff0600,gr17 +bad1: sti gr15,@(gr17,0) ; cause interrupt + test_gr_immed 1,gr16 + + set_gr_immed 0xbeefdead,gr15 + set_gr_addr 0xfeff7ffc,gr17 +bad2: sti gr15,@(gr17,0) ; cause interrupt + test_gr_immed 2,gr16 + + set_gr_immed 0xbeefbeef,gr15 + set_gr_addr 0xfe800000,gr17 +bad3: sti gr15,@(gr17,0) ; cause interrupt + test_gr_immed 3,gr16 + + set_gr_immed 0xdeaddead,gr15 + set_gr_addr 0xfefefffc,gr17 +bad4: sti gr15,@(gr17,0) ; cause interrupt + test_gr_immed 4,gr16 + + sti gr0,@(sp,0) ; no interrupt + test_gr_immed 4,gr16 + + pass +ok0: + ; check interrupts + test_spr_immed 0x4000,esfr1 ; esr14 is active + test_spr_bits 0x0001,0,0x1,esr14 ; esr14 is valid + test_spr_bits 0x003e,1,0x0,esr14 ; esr14.ec is set + test_spr_bits 0x0800,11,0x0,esr14 ; esr14.eav is not set + + addi gr16,1,gr16 + rett 0 + fail diff --git a/sim/testsuite/sim/frv/interrupts/fp_exception-fr550.cgs b/sim/testsuite/sim/frv/interrupts/fp_exception-fr550.cgs new file mode 100644 index 0000000..0bb98d8 --- /dev/null +++ b/sim/testsuite/sim/frv/interrupts/fp_exception-fr550.cgs @@ -0,0 +1,185 @@ +# frv testcase to generate fp_exception +# mach: fr550 + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global align +align: + ; clear the packing bit if the insn at 'pack:'. We can't simply use + ; '.p' because the assembler will catch the error. + set_gr_mem pack,gr10 + and_gr_immed 0x7fffffff,gr10 + set_mem_gr gr10,pack + set_gr_addr pack,gr10 + flush_data_cache gr10 + + ; Make the the source register number odd at badst. We can't simply + ; code an odd register number because the assembler will catch the + ; error. + set_gr_mem badst,gr10 + or_gr_immed 0x02000000,gr10 + set_mem_gr gr10,badst + set_gr_addr badst,gr10 + flush_data_cache gr10 + + ; Make the the dest register number odd at badld. We can't simply + ; code an odd register number because the assembler will catch the + ; error. + set_gr_mem badld,gr10 + or_gr_immed 0x02000000,gr10 + set_mem_gr gr10,badld + set_gr_addr badld,gr10 + flush_data_cache gr10 + + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr17 + inc_gr_immed 0x070,gr17 ; address of exception handler + set_bctrlr_0_0 gr17 + inc_gr_immed 0x060,gr17 ; address of exception handler + set_bctrlr_0_0 gr17 + set_spr_immed 128,lcr + set_spr_addr ok1,lr + set_psr_et 1 + inc_gr_immed -4,sp ; for alignment + + set_gr_immed 0,gr20 ; PC increment + set_gr_immed 0,gr15 + + set_spr_addr ok3,lr + set_gr_immed 4,gr20 ; PC increment +badst: stdfi fr0,@(sp,0) ; misaligned reg -- slot I0 + test_gr_immed 1,gr15 + + set_spr_addr ok4,lr + set_gr_immed 8,gr20 ; PC increment + nop.p +badld: lddfi @(sp,0),fr8 ; misaligned reg -- slot I1 + test_gr_immed 2,gr15 + + set_spr_addr ok5,lr + set_gr_immed 20,gr20 ; PC increment + fnegs.p fr9,fr9 + fnegs.p fr9,fr10 + fnegs.p fr9,fr11 +pack: fnegs fr10,fr12 + fnegs fr10,fr13 ; packing violation + test_gr_immed 3,gr15 + + set_spr_addr ok1,lr + set_gr_immed 4,gr20 ; PC increment +bad: fmadds fr16,fr4,fr1 ; unimplemented + test_gr_immed 4,gr15 + + and_spr_immed 0xfbffffff,fsr0 ; disable div/0 fp_exception + set_fr_iimmed 0x7f7f,0xffff,fr0 + set_fr_iimmed 0x0000,0x0000,fr1 + fdivs fr0,fr1,fr2 ; div/0 -- no exception + test_spr_bits 0x100000,20,0x0,fsr0 ; fsr0.qne is never set + test_spr_bits 0xfc00,10,0x4,fsr0 ; fsr0.aexc is still set + test_spr_bits 0xe0000,17,0x0,fsr0 ; fsr0.ftt is clear + + set_spr_addr ok2,lr + set_gr_immed 0,gr20 ; PC increment + or_spr_immed 0x04000000,fsr0 ; enable div/0 fp_exception + set_fr_iimmed 0xdead,0xbeef,fr2 +div0: fdivs fr0,fr1,fr2 ; fp_exception - div/0 + test_fr_iimmed 0xdeadbeef,fr2 ; fr2 not updated + test_gr_immed 5,gr15 + + and_spr_immed 0xfdffffff,fsr0 ; disable inexact fp_exception + fsqrts fr32,fr2 ; inexact -- no exception + test_spr_bits 0x100000,20,0x0,fsr0 ; fsr0.qne is never set + test_spr_bits 0xfc00,10,0x6,fsr0 ; fsr0.aexc is set + test_spr_bits 0xe0000,17,0x0,fsr0 ; fsr0.ftt is clear + + set_fr_fr fr2,fr3 ; sqrt 2 + set_fr_iimmed 0xdead,0xbeef,fr2 + set_spr_addr ok6,lr + or_spr_immed 0x02000000,fsr0 ; enable inexact fp_exception +inxt1: fsqrts fr32,fr2 ; fp_exception - inexact + test_gr_immed 6,gr15 ; handler called + test_fr_fr fr2,fr3 ; fr2 updated + + set_fr_iimmed 0xdead,0xbeef,fr2 + set_spr_addr ok7,lr +inxt2: fsqrts fr32,fr2 ; fp_exception - inexact again + test_gr_immed 7,gr15 ; handler called + test_fr_fr fr2,fr3 ; fr2 updated + + pass + +; exception handler 1 -- illegal_instruction: bad insn +ok1: + test_spr_immed 1,esfr1 ; esr0 active + test_spr_bits 0x3e,1,0x5,esr0 ; esr0.ec is set + test_spr_bits 0x1,0,0x1,esr0 ; esr0.valid is set + bra ret + +; exception handler 2 - fp_exception: divide by 0 +ok2: + test_spr_bits 0x100000,20,0x0,fsr0 ; fsr0.qne is clear + test_spr_bits 0xe0000,17,0x1,fsr0 ; fsr0.ftt is set + test_spr_bits 0xfc00,10,0x4,fsr0 ; fsr0.aexc is still set + + test_spr_immed 4,esfr1 ; esr2 active + test_spr_bits 0x3e,1,0xd,esr2 ; esr2.ec is set + test_spr_bits 0x1,0,0x1,esr2 ; esr2.valid is set + test_spr_addr div0,epcr2 ; epcr2 is set + bra ret + +; exception handler 3 - illegal_instruction: register exception +ok3: + test_spr_immed 1,esfr1 ; esr0 active + test_spr_bits 0x3e,1,0x5,esr0 ; esr0.ec is set + test_spr_bits 0x1,0,0x1,esr0 ; esr0.valid is set + bra ret + +; exception handler 4 - illegal_instruction: register exception +ok4: + test_spr_immed 1,esfr1 ; esr0 active + test_spr_bits 0x3e,1,0x5,esr0 ; esr0.ec is set + test_spr_bits 0x1,0,0x1,esr0 ; esr0.valid is set + bra ret + +; exception handler 5 - illegal_instruction: sequence violation +ok5: + test_spr_immed 1,esfr1 ; esr0 active + test_spr_bits 0x3e,1,0x5,esr0 ; esr0.ec is set + test_spr_bits 0x1,0,0x1,esr0 ; esr0.valid is set + bra ret + +; exception handler 6 - fp_exception: inexact +ok6: + test_spr_bits 0x100000,20,0x0,fsr0 ; fsr0.qne is clear + test_spr_bits 0xe0000,17,0x1,fsr0 ; fsr0.ftt is set + test_spr_bits 0xfc00,10,0x6,fsr0 ; fsr0.aexc is still set + + test_spr_immed 4,esfr1 ; esr2 active + test_spr_bits 0x3e,1,0xd,esr2 ; esr2.ec is set + test_spr_bits 0x1,0,0x1,esr2 ; esr2.valid is set + test_spr_addr inxt1,epcr2 ; epcr2 is set + bra ret + +; exception handler 7 - fp_exception: inexact again +ok7: + test_spr_bits 0x100000,20,0x0,fsr0 ; fsr0.qne is clear + test_spr_bits 0xe0000,17,0x1,fsr0 ; fsr0.ftt is set + test_spr_bits 0xfc00,10,0x6,fsr0 ; fsr0.aexc is still set + + test_spr_immed 4,esfr1 ; esr2 active + test_spr_bits 0x3e,1,0xd,esr2 ; esr2.ec is set + test_spr_bits 0x1,0,0x1,esr2 ; esr2.valid is set + test_spr_addr inxt2,epcr2 ; epcr2 is set + bra ret + +ret: + inc_gr_immed 1,gr15 + movsg pcsr,gr60 + add gr60,gr20,gr60 + movgs gr60,pcsr + rett 0 + fail + diff --git a/sim/testsuite/sim/frv/interrupts/fp_exception.cgs b/sim/testsuite/sim/frv/interrupts/fp_exception.cgs new file mode 100644 index 0000000..ad5f7e4 --- /dev/null +++ b/sim/testsuite/sim/frv/interrupts/fp_exception.cgs @@ -0,0 +1,209 @@ +# frv testcase to generate fp_exception +# mach: fr500 + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global align +align: + ; clear the packing bit if the insn at 'pack:'. We can't simply use + ; '.p' because the assembler will catch the error. + set_gr_mem pack,gr10 + and_gr_immed 0x7fffffff,gr10 + set_mem_gr gr10,pack + set_gr_addr pack,gr10 + flush_data_cache gr10 + + ; Make the the source register number odd at badst. We can't simply + ; code an odd register number because the assembler will catch the + ; error. + set_gr_mem badst,gr10 + or_gr_immed 0x02000000,gr10 + set_mem_gr gr10,badst + set_gr_addr badst,gr10 + flush_data_cache gr10 + + ; Make the the dest register number odd at ld. We can't simply + ; code an odd register number because the assembler will catch the + ; error. + set_gr_mem badld,gr10 + or_gr_immed 0x02000000,gr10 + set_mem_gr gr10,badld + set_gr_addr badld,gr10 + flush_data_cache gr10 + + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr17 + inc_gr_immed 0x070,gr17 ; address of exception handler + set_bctrlr_0_0 gr17 + inc_gr_immed 0x060,gr17 ; address of exception handler + set_bctrlr_0_0 gr17 + set_spr_immed 128,lcr + set_spr_addr ok1,lr + set_psr_et 1 + inc_gr_immed -4,sp ; for alignment + + set_gr_immed 0,gr20 ; PC increment + set_gr_immed 0,gr15 + + set_spr_addr ok3,lr +badst: stdfi fr0,@(sp,0) ; misaligned reg -- slot I0 + test_gr_immed 1,gr15 + + set_spr_addr ok4,lr + nop.p +badld: lddfi @(sp,0),fr8 ; misaligned reg -- slot I1 + test_gr_immed 2,gr15 + + set_spr_addr ok5,lr + fnegs.p fr9,fr9 +pack: fnegs fr10,fr10 + fnegs fr10,fr11 ; packing violation + test_gr_immed 3,gr15 + + set_spr_addr ok1,lr + set_gr_immed 4,gr20 ; PC increment +bad: fmadds fr16,fr4,fr1 ; unimplemented + test_gr_immed 4,gr15 + + and_spr_immed 0xfbffffff,fsr0 ; disable div/0 fp_exception + set_fr_iimmed 0x7f7f,0xffff,fr0 + set_fr_iimmed 0x0000,0x0000,fr1 + fdivs fr0,fr1,fr2 ; div/0 -- no exception + test_spr_bits 0x100000,20,0x1,fsr0 ; fsr0.qne is still set + test_spr_bits 0xfc00,10,0x4,fsr0 ; fsr0.aexc is still set + test_spr_bits 0xe0000,17,0x0,fsr0 ; fsr0.ftt is clear + and_spr_immed 0xffefffff,fsr0 ; Clear fsr0.qne + + set_spr_addr ok2,lr + set_gr_immed 0,gr20 ; PC increment + or_spr_immed 0x04000000,fsr0 ; enable div/0 fp_exception + set_fr_iimmed 0xdead,0xbeef,fr2 + fdivs fr0,fr1,fr2 ; fp_exception - div/0 + test_fr_iimmed 0xdeadbeef,fr2 ; fr2 not updated + test_gr_immed 5,gr15 + + and_spr_immed 0xfdffffff,fsr0 ; disable inexact fp_exception + fsqrts fr32,fr2 ; inexact -- no exception + test_spr_bits 0x100000,20,0x1,fsr0 ; fsr0.qne is still set + test_spr_bits 0xfc00,10,0x6,fsr0 ; fsr0.aexc is set + test_spr_bits 0xe0000,17,0x0,fsr0 ; fsr0.ftt is clear + + set_fr_fr fr2,fr3 ; sqrt 2 + set_fr_iimmed 0xdead,0xbeef,fr2 + set_spr_addr ok6,lr + or_spr_immed 0x02000000,fsr0 ; enable inexact fp_exception + fsqrts fr32,fr2 ; fp_exception - inexact + test_gr_immed 6,gr15 ; handler called + test_fr_fr fr2,fr3 ; fr2 updated + + set_fr_iimmed 0xdead,0xbeef,fr2 + set_spr_addr ok7,lr + fsqrts fr32,fr2 ; fp_exception - inexact again + test_gr_immed 7,gr15 ; handler called + test_fr_fr fr2,fr3 ; fr2 updated + + pass + +; exception handler 1 -- bad insn +ok1: + test_spr_immed 1,esfr1 ; esr0 active + test_spr_bits 0x3e,1,0x5,esr0 ; esr0.ec is set + test_spr_bits 0x1,0,0x1,esr0 ; esr0.valid is set + test_spr_addr bad,epcr0 + bra ret + +; exception handler 2 - fp_exception: divide by 0 +ok2: + test_spr_bits 0x100000,20,0x1,fsr0 ; fsr0.qne is set + test_spr_bits 0xe0000,17,0x1,fsr0 ; fsr0.ftt is set + test_spr_bits 0xfc00,10,0x4,fsr0 ; fsr0.aexc is still set + + test_spr_bits 0x80000000,31,0x0,fqst2 ; fq2.miv is set + test_spr_bits 0x18000,15,0x0,fqst2 ; fq2.sie is set + test_spr_bits 0x380,7,0x1,fqst2 ; fq2.ftt is set + test_spr_bits 0x7e,1,0x4,fqst2 ; fq2.cexc is set + test_spr_bits 0x1,0,0x1,fqst2 ; fq2.valid is set + test_spr_immed 0x85e40241,fqop2 ; fq2.opc + bra ret + +; exception handler 3 - fp_exception: register exception +ok3: + test_spr_bits 0x100000,20,0x1,fsr0 ; fsr0.qne is set + test_spr_bits 0xe0000,17,0x6,fsr0 ; fsr0.ftt is set + test_spr_bits 0xfc00,10,0x0,fsr0 ; fsr0.aexc is clear + + test_spr_bits 0x80000000,31,0x0,fqst2 ; fq2.miv is set + test_spr_bits 0x18000,15,0x0,fqst2 ; fq2.sie is set + test_spr_bits 0x380,7,0x6,fqst2 ; fq2.ftt is set + test_spr_bits 0x7e,1,0x0,fqst2 ; fq2.cexc is set + test_spr_bits 0x1,0,0x1,fqst2 ; fq2.valid is set + test_spr_immed 0x83581000,fqop2 ; fq2.opc + bra ret + +; exception handler 4 - fp_exception: another register exception +ok4: + test_spr_bits 0x100000,20,0x1,fsr0 ; fsr0.qne is set + test_spr_bits 0xe0000,17,0x6,fsr0 ; fsr0.ftt is set + test_spr_bits 0xfc00,10,0x0,fsr0 ; fsr0.aexc is still clear + + test_spr_bits 0x80000000,31,0x0,fqst3 ; fq3.miv is set + test_spr_bits 0x18000,15,0x0,fqst3 ; fq3.sie is set + test_spr_bits 0x380,7,0x6,fqst3 ; fq3.ftt is set + test_spr_bits 0x7e,1,0x0,fqst3 ; fq3.cexc is set + test_spr_bits 0x1,0,0x1,fqst3 ; fq3.valid is set + test_spr_immed 0x92ec1000,fqop3 ; fq3.opc + bra ret + +; exception handler 5 - fp_exception: sequence violation +ok5: + test_spr_bits 0x100000,20,0x1,fsr0 ; fsr0.qne is set + test_spr_bits 0xe0000,17,0x4,fsr0 ; fsr0.ftt is set + test_spr_bits 0xfc00,10,0x0,fsr0 ; fsr0.aexc is still clear + + test_spr_bits 0x80000000,31,0x0,fqst3 ; fq3.miv is set + test_spr_bits 0x18000,15,0x0,fqst3 ; fq3.sie is set + test_spr_bits 0x380,7,0x4,fqst3 ; fq3.ftt is set + test_spr_bits 0x7e,1,0x0,fqst3 ; fq3.cexc is set + test_spr_bits 0x1,0,0x1,fqst3 ; fq3.valid is set + test_spr_immed 0x97e400ca,fqop3 ; fq3.opc + bra ret + +; exception handler 6 - fp_exception: inexact +ok6: + test_spr_bits 0x100000,20,0x1,fsr0 ; fsr0.qne is set + test_spr_bits 0xe0000,17,0x1,fsr0 ; fsr0.ftt is set + test_spr_bits 0xfc00,10,0x6,fsr0 ; fsr0.aexc is still set + + test_spr_bits 0x80000000,31,0x0,fqst0 ; fq0.miv is set + test_spr_bits 0x18000,15,0x0,fqst0 ; fq0.sie is set + test_spr_bits 0x380,7,0x1,fqst0 ; fq0.ftt is set + test_spr_bits 0x7e,1,0x2,fqst0 ; fq0.cexc is set + test_spr_bits 0x1,0,0x1,fqst0 ; fq0.valid is set + test_spr_immed 0x85e40160,fqop0 ; fq0.opc + bra ret + +; exception handler 7 - fp_exception: inexact again +ok7: + test_spr_bits 0x100000,20,0x1,fsr0 ; fsr0.qne is set + test_spr_bits 0xe0000,17,0x1,fsr0 ; fsr0.ftt is set + test_spr_bits 0xfc00,10,0x6,fsr0 ; fsr0.aexc is still set + + test_spr_bits 0x80000000,31,0x0,fqst1 ; fq1.miv is set + test_spr_bits 0x18000,15,0x0,fqst1 ; fq1.sie is set + test_spr_bits 0x380,7,0x1,fqst1 ; fq1.ftt is set + test_spr_bits 0x7e,1,0x2,fqst1 ; fq1.cexc is set + test_spr_bits 0x1,0,0x1,fqst1 ; fq1.valid is set + test_spr_immed 0x85e40160,fqop1 ; fq1.opc + bra ret + +ret: + inc_gr_immed 1,gr15 + movsg pcsr,gr60 + add gr60,gr20,gr60 + movgs gr60,pcsr + rett 0 + fail + diff --git a/sim/testsuite/sim/frv/interrupts/illinsn.cgs b/sim/testsuite/sim/frv/interrupts/illinsn.cgs new file mode 100644 index 0000000..fc44a8f --- /dev/null +++ b/sim/testsuite/sim/frv/interrupts/illinsn.cgs @@ -0,0 +1,38 @@ +# FRV testcase +# mach: fr500 fr550 fr400 + + .include "testutils.inc" + + start + + .global tra +tra: + and_spr_immed 0x3fffffff,hsr0 ; no caches enabled + + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 0x070,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 + inc_gr_immed 0x790,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 + set_spr_immed 128,lcr + set_psr_et 1 + set_spr_addr ok0,lr + + set_gr_addr ill1,gr7 + set_mem_immed 0x81f80000,gr7 ; unknown opcode: 7E +ill1: tira gr0,0 ; should be overridden +ill2: nop ; also illegal, but prev has priority +bad0: fail + + ; check interrupt +ok0: test_spr_addr ill1,pcsr + test_spr_immed 1,esfr1 ; esr0 active + test_spr_bits 0x3f,0,0xb,esr0 + movsg psr,gr28 + srli gr28,28,gr28 + subicc gr28,0x3,gr0,icc3 ; is fr550? + beq icc3,0,no_epcr + test_spr_addr ill1,epcr0 +no_epcr: + pass diff --git a/sim/testsuite/sim/frv/interrupts/insn_access_error-fr550.cgs b/sim/testsuite/sim/frv/interrupts/insn_access_error-fr550.cgs new file mode 100644 index 0000000..6c49299 --- /dev/null +++ b/sim/testsuite/sim/frv/interrupts/insn_access_error-fr550.cgs @@ -0,0 +1,44 @@ +# frv testcase to generate insn_access_error interrupt +# mach: fr550 +# sim: --memory-region 0xfe800000,0x7f0500 --memory-region 0xfeff0540,0xfb00 + .include "testutils.inc" + + start + + .global dsr +dsr: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr17 + inc_gr_immed 0x020,gr17 ; address of exception handler + set_bctrlr_0_0 gr17 + set_spr_immed 128,lcr + set_psr_et 1 + + set_spr_addr handler,lr + set_gr_immed 0,gr16 + + set_gr_addr ok0,gr8 + set_gr_addr 0xfe800000,gr17 + jmpl @(gr17,gr0) ; cause interrupt +ok0: + test_gr_immed 1,gr16 + + set_gr_addr ok1,gr8 + set_gr_addr 0xfefffffc,gr17 + jmpl @(gr17,gr0) ; cause interrupt +ok1: + test_gr_immed 2,gr16 + + pass +handler: + ; check interrupts + test_spr_immed 0x1,esfr1 ; esr0 is active +; test_spr_gr epcr0,gr17 ; epcr0 is not used + test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid + test_spr_bits 0x003e,1,0x2,esr0 ; esr0.ec is set + test_spr_bits 0x0800,11,0x0,esr0 ; esr0.eav is not set + + addi gr16,1,gr16 + movgs gr8,pcsr + rett 0 + fail diff --git a/sim/testsuite/sim/frv/interrupts/insn_access_error.cgs b/sim/testsuite/sim/frv/interrupts/insn_access_error.cgs new file mode 100644 index 0000000..11a9eaf --- /dev/null +++ b/sim/testsuite/sim/frv/interrupts/insn_access_error.cgs @@ -0,0 +1,56 @@ +# frv testcase to generate insn_access_error interrupt +# mach: fr500 fr400 +# sim: --memory-region 0xfeff0600,0x8000 --memory-region 0xfe800000,0x7f0040 + .include "testutils.inc" + + start + + .global dsr +dsr: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr17 + inc_gr_immed 0x020,gr17 ; address of exception handler + set_bctrlr_0_0 gr17 + set_spr_immed 128,lcr + set_psr_et 1 + + set_spr_addr handler,lr + set_gr_immed 0,gr16 + + set_gr_addr ok0,gr8 + set_gr_addr 0xfeff0600,gr17 + jmpl @(gr17,gr0) ; cause interrupt +ok0: + test_gr_immed 1,gr16 + + set_gr_addr ok1,gr8 + set_gr_addr 0xfeff7ffc,gr17 + jmpl @(gr17,gr0) ; cause interrupt +ok1: + test_gr_immed 2,gr16 + + set_gr_addr ok2,gr8 + set_gr_addr 0xfe800000,gr17 + jmpl @(gr17,gr0) ; cause interrupt +ok2: + test_gr_immed 3,gr16 + + set_gr_addr ok3,gr8 + set_gr_addr 0xfefefffc,gr17 + jmpl @(gr17,gr0) ; cause interrupt +ok3: + test_gr_immed 4,gr16 + + pass +handler: + ; check interrupts + test_spr_immed 0x1,esfr1 ; esr0 is active + test_spr_gr epcr0,gr17 + test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid + test_spr_bits 0x003e,1,0x2,esr0 ; esr0.ec is set + test_spr_bits 0x0800,11,0x0,esr0 ; esr0.eav is not set + + addi gr16,1,gr16 + movgs gr8,pcsr + rett 0 + fail diff --git a/sim/testsuite/sim/frv/interrupts/mp_exception.cgs b/sim/testsuite/sim/frv/interrupts/mp_exception.cgs new file mode 100644 index 0000000..3203acc --- /dev/null +++ b/sim/testsuite/sim/frv/interrupts/mp_exception.cgs @@ -0,0 +1,289 @@ +# frv testcase for mp_exception +# mach: fr500 fr550 frv +# xerror: + +# This program no longer assembles because the assembler +# now detects the unaligned registers. For this reason +# this test is now marked as "xerror" and prints the +# expected message "fail" + + .include "testutils.inc" + + start + + .global mp_exception +mpx: +.if 1 + fail +.else + or_spr_immed 2,msr0 ; Set msr0.ovf + or_spr_immed 2,msr1 ; Set msr1.ovf + and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt + mcmpsh fr10,fr11,fcc1 ; mp_exception: cr-not-aligned + test_spr_bits 0x7000,12,3,msr0; msr0.mtt is set + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf is set + + or_spr_immed 2,msr0 ; Set msr0.ovf + or_spr_immed 2,msr1 ; Set msr1.ovf + and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt + mcmpsh.p fr10,fr11,fcc0 ; no exception + mcmpsh fr10,fr11,fcc2 ; no exception + test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear + + mmulhs.p fr10,fr11,acc3 ; no exception + mmulhs fr10,fr11,acc1 ; mp_exception: acc-not-aligned + test_spr_bits 0x7000,12,2,msr0; msr0.mtt is set + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear + + or_spr_immed 2,msr0 ; Set msr0.ovf + or_spr_immed 2,msr1 ; Set msr1.ovf + and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt + mmulhu fr10,fr11,acc0 ; no exception + test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,1,msr0 ; msr0.ovf is still set + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + mmulxhs.p fr10,fr11,acc3 ; no exception + mmulxhs fr10,fr11,acc1 ; mp_exception: acc-not-aligned + test_spr_bits 0x7000,12,2,msr0; msr0.mtt is set + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear + + or_spr_immed 2,msr0 ; Set msr0.ovf + or_spr_immed 2,msr1 ; Set msr1.ovf + and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt + mmulxhu fr10,fr11,acc0 ; no exception + test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,1,msr0 ; msr0.ovf is still set + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + mmachs.p fr10,fr11,acc3 ; no exception + mmachs fr10,fr11,acc1 ; mp_exception: acc-not-aligned + test_spr_bits 0x7000,12,2,msr0; msr0.mtt is set + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear + + or_spr_immed 2,msr0 ; Set msr0.ovf + or_spr_immed 2,msr1 ; Set msr1.ovf + and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt + mmachu fr10,fr11,acc0 ; no exception + test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + mqaddhss.p fr10,fr12,fr17 ; mp_exception: register-not-aligned + mqaddhss fr10,fr12,fr14 ; no exception + test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + mqaddhss.p fr10,fr12,fr14 ; no exception + mqaddhss fr10,fr13,fr16 ; mp_exception: register-not-aligned + test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + mqaddhss.p fr19,fr12,fr14 ; mp_exception: register-not-aligned + mqaddhss fr10,fr13,fr16 ; mp_exception: register-not-aligned + test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear + + or_spr_immed 2,msr0 ; Set msr0.ovf + or_spr_immed 2,msr1 ; Set msr1.ovf + and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt + mqaddhss fr10,fr12,fr14 ; no exception + test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + mqmulhs.p fr10,fr11,acc3 ; no exception + mqmulhs fr10,fr11,acc2 ; mp_exception: acc-not-aligned + test_spr_bits 0x7000,12,2,msr0; msr0.mtt is set + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear + + or_spr_immed 2,msr0 ; Set msr0.ovf + or_spr_immed 2,msr1 ; Set msr1.ovf + and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt + mqmulhu fr10,fr11,acc0 ; mp_exception: register_not_aligned + test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,1,msr0 ; msr0.ovf is still set + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set + + and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt + mqmulhu fr10,fr12,acc0 ; no exception + test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,1,msr0 ; msr0.ovf is still set + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + mqmulxhs.p fr10,fr11,acc3 ; no exception + mqmulxhs fr10,fr11,acc2 ; mp_exception: acc-not-aligned + test_spr_bits 0x7000,12,2,msr0; msr0.mtt is set + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear + + or_spr_immed 2,msr0 ; Set msr0.ovf + or_spr_immed 2,msr1 ; Set msr1.ovf + and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt + mqmulxhu fr10,fr11,acc0 ; mp_exception: register-not-aligned + test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,1,msr0 ; msr0.ovf is still set + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set + + and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt + mqmulxhu fr10,fr12,acc0 ; no exception + test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,1,msr0 ; msr0.ovf is still set + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + mqmachs.p fr10,fr12,acc3 ; no exception + mqmachs fr10,fr12,acc2 ; mp_exception: acc-not-aligned + test_spr_bits 0x7000,12,2,msr0; msr0.mtt is set + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear + + and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt + mqmachu.p fr19,fr12,acc0 ; mp_exception: register-not-aligned + mqmachu fr10,fr12,acc0 ; no exception + test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear + + and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt + mqmachu.p fr10,fr12,acc0 ; no exception + mqmachu fr19,fr12,acc0 ; mp_exception: register-not-aligned + test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear + + and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt + mqmachu.p fr19,fr12,acc0 ; mp_exception: register-not-aligned + mqmachu fr19,fr12,acc0 ; mp_exception: register-not-aligned + test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear + + or_spr_immed 2,msr0 ; Set msr0.ovf + or_spr_immed 2,msr1 ; Set msr1.ovf + and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt + mqmachu fr10,fr12,acc0 ; no exception + test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + mqcpxrs.p fr10,fr12,acc0 ; no exception + mqcpxrs fr10,fr12,acc1 ; mp_exception: acc-not-aligned + test_spr_bits 0x7000,12,2,msr0; msr0.mtt is set + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear + + and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt + mqcpxru.p fr19,fr12,acc0 ; mp_exception: register-not-aligned + mqcpxru fr10,fr12,acc0 ; no exception + test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear + + and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt + mqcpxru.p fr10,fr12,acc0 ; no exception + mqcpxru fr19,fr12,acc0 ; mp_exception: register-not-aligned + test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear + + and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt + mqcpxru.p fr19,fr12,acc0 ; mp_exception: register-not-aligned + mqcpxru fr19,fr12,acc0 ; mp_exception: register-not-aligned + test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear + + or_spr_immed 2,msr0 ; Set msr0.ovf + or_spr_immed 2,msr1 ; Set msr1.ovf + and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt + mqcpxru fr10,fr12,acc0 ; no exception + test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set + + pass +.endif diff --git a/sim/testsuite/sim/frv/interrupts/privileged_instruction.cgs b/sim/testsuite/sim/frv/interrupts/privileged_instruction.cgs new file mode 100644 index 0000000..9996236 --- /dev/null +++ b/sim/testsuite/sim/frv/interrupts/privileged_instruction.cgs @@ -0,0 +1,54 @@ +# frv testcase to generate privileged_instruction interrupt +# mach: frv + + .include "testutils.inc" + + start + + .global dsr +dsr: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr17 + inc_gr_immed 0x060,gr17 ; address of exception handler + set_bctrlr_0_0 gr17 + set_spr_immed 128,lcr + set_psr_et 1 + and_spr_immed 0xfffffffb,psr ; clear psr.s + + set_spr_addr handler,lr + set_gr_immed 0,gr16 + + set_gr_addr bad1,gr17 +bad1: rett 0 ; cause interrupt + test_gr_immed 1,gr16 + set_gr_addr bad2,gr17 +bad2: rei 0 ; cause interrupt + test_gr_immed 2,gr16 + set_gr_addr bad3,gr17 +bad3: witlb gr0,@(gr0,gr0) ; cause interrupt + test_gr_immed 3,gr16 + set_gr_addr bad4,gr17 +bad4: wdtlb gr0,@(gr0,gr0) ; cause interrupt + test_gr_immed 4,gr16 + set_gr_addr bad5,gr17 +bad5: itlbi @(gr0,gr0) ; cause interrupt + test_gr_immed 5,gr16 + set_gr_addr bad6,gr17 +bad6: dtlbi @(gr0,gr0) ; cause interrupt + test_gr_immed 6,gr16 + + pass +handler: + ; check interrupts + test_spr_immed 0x1,esfr1 ; esr0 is active + test_spr_gr epcr0,gr17 + test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid + test_spr_bits 0x003e,1,0x4,esr0 ; esr0.ec is set + test_spr_bits 0x0800,11,0x0,esr0 ; esr0.eav is not set + + addi gr16,1,gr16 + movsg pcsr,gr8 + addi gr8,4,gr8 + movgs gr8,pcsr + rett 0 + fail diff --git a/sim/testsuite/sim/frv/interrupts/regalign.cgs b/sim/testsuite/sim/frv/interrupts/regalign.cgs new file mode 100644 index 0000000..afa09b5 --- /dev/null +++ b/sim/testsuite/sim/frv/interrupts/regalign.cgs @@ -0,0 +1,130 @@ +# frv testcase to generate interrupts for bad register alignment +# mach: frv + .include "testutils.inc" + + start + + .global align +align: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr17 + inc_gr_immed 0x080,gr17 ; address of exception handler + set_bctrlr_0_0 gr17 + inc_gr_immed 0x050,gr17 ; address of exception handler + set_bctrlr_0_0 gr17 + set_spr_immed 128,lcr + set_spr_addr ok1,lr + set_psr_et 1 + + ; Make the the register number odd at bad[1-4], bad9 and bada. + ; We can't simply code an odd register number because the assembler + ; will catch the error. + set_gr_mem bad1,gr10 + or_gr_immed 0x02000000,gr10 + set_mem_gr gr10,bad1 + set_gr_addr bad1,gr10 + flush_data_cache gr10 + set_gr_mem bad2,gr10 + or_gr_immed 0x02000000,gr10 + set_mem_gr gr10,bad2 + set_gr_addr bad2,gr10 + flush_data_cache gr10 + set_gr_mem bad3,gr10 + or_gr_immed 0x02000000,gr10 + set_mem_gr gr10,bad3 + set_gr_addr bad3,gr10 + flush_data_cache gr10 + set_gr_mem bad4,gr10 + or_gr_immed 0x02000000,gr10 + set_mem_gr gr10,bad4 + set_gr_addr bad4,gr10 + flush_data_cache gr10 + set_gr_mem bad9,gr10 + or_gr_immed 0x02000000,gr10 + set_mem_gr gr10,bad9 + set_gr_addr bad9,gr10 + flush_data_cache gr10 + set_gr_mem bada,gr10 + or_gr_immed 0x02000000,gr10 + set_mem_gr gr10,bada + set_gr_addr bada,gr10 + flush_data_cache gr10 + + set_gr_immed 4,gr20 ; PC increment + set_gr_immed 0,gr15 + inc_gr_immed -12,sp ; for memory alignment + + set_gr_addr bad1,gr17 +bad1: stdi gr0,@(sp,0) ; misaligned reg + test_gr_immed 1,gr15 + + set_gr_addr bad2,gr17 +bad2: lddi @(sp,0),gr8 ; misaligned reg + test_gr_immed 2,gr15 + + set_gr_addr bad3,gr17 +bad3: stdc cpr0,@(sp,gr0) ; misaligned reg + test_gr_immed 3,gr15 + + set_gr_addr bad4,gr17 +bad4: lddc @(sp,gr0),cpr8 ; misaligned reg + test_gr_immed 4,gr15 + + set_gr_addr bad5,gr17 +bad5: stqi gr2,@(sp,0) ; misaligned reg + test_gr_immed 5,gr15 + + set_gr_addr bad6,gr17 +bad6: ldqi @(sp,0),gr10 ; misaligned reg + test_gr_immed 6,gr15 + + set_gr_addr bad7,gr17 +bad7: stqc cpr2,@(sp,gr0) ; misaligned reg + test_gr_immed 7,gr15 + + set_gr_addr bad8,gr17 +bad8: ldqc @(sp,gr0),cpr10 ; misaligned reg + test_gr_immed 8,gr15 + + set_gr_immed 0,gr20 ; PC increment + set_gr_addr bad9,gr17 +bad9: stdfi fr0,@(sp,0) ; misaligned reg + test_gr_immed 9,gr15 + + set_gr_addr bada,gr17 +bada: lddfi @(sp,0),fr8 ; misaligned reg + test_gr_immed 10,gr15 + + set_gr_addr badb,gr17 +badb: stqfi fr2,@(sp,0) ; misaligned reg + test_gr_immed 11,gr15 + + set_gr_addr badc,gr17 +badc: ldqfi @(sp,0),fr10 ; misaligned reg + test_gr_immed 12,gr15 + + pass + +; exception handler +ok1: + cmpi gr20,0,icc0 + beq icc0,0,float + + ; check register_exception + test_spr_immed 0x1,esfr1 ; esr0 is active + test_spr_gr epcr0,gr17 + test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid + test_spr_bits 0x003e,1,0xc,esr0 ; esr0.ec is set + test_spr_bits 0x00c0,6,0x1,esr0 ; esr0.rec is set + test_spr_bits 0x0800,11,0x0,esr0 ; esr0.eav is not set + movsg pcsr,gr60 + add gr60,gr20,gr60 + movgs gr60,pcsr + bra ret +float: + ; check fp_exception + test_spr_immed 0,esfr1 ; no esr's active +ret: + inc_gr_immed 1,gr15 + rett 0 + fail diff --git a/sim/testsuite/sim/frv/interrupts/reset.cgs b/sim/testsuite/sim/frv/interrupts/reset.cgs new file mode 100644 index 0000000..ff2035c --- /dev/null +++ b/sim/testsuite/sim/frv/interrupts/reset.cgs @@ -0,0 +1,81 @@ +# frv testcase to generate reset interrupts +# mach: fr500 fr550 fr400 +# sim: --memory-region 0xff000000,64 + + .include "testutils.inc" + + start + + .global reset +reset: + and_spr_immed 0xfffffffb,psr ; turn off PSR.S + set_gr_immed 0xfeff0500,gr10 ; address of reset register + set_spr_immed 0x7fffffff,lcr + set_bctrlr_0_0 gr0 + +; Can't recover from hardware interrupt with enough state intact to verify it +; set_spr_addr ok1,lr +; set_mem_immed 0x3,gr10 ; cause hardware reset +; dcf @(gr10,gr0) ; Wait for store to happen +; fail +; +;ok1: ; reset should branch to reset address which should then branch here +; test_mem_immed 0x00000200,gr10 +; set_spr_addr ok2,lr +; set_mem_immed 0x2,gr10 ; cause hardware reset +; dcf @(gr10,gr0) ; Wait for store to happen +; fail +; +ok2: ; reset should branch to reset address which should then branch here +; test_mem_immed 0x00000200,gr10 + set_spr_addr ok3,lr + set_mem_immed 0x1,gr10 ; cause software reset + dcf @(gr10,gr0) ; Wait for store to happen + fail + +ok3: ; reset should branch to reset address which should then branch here + test_mem_immed 0x00000100,gr10 + test_spr_bits 0x4,2,1,psr ; psr.s is set + test_spr_bits 0x2,1,0,psr ; psr.ps not set + set_spr_addr bad,lr + set_mem_immed 0x0,gr10 ; no reset + test_mem_immed 0x0,gr10 + + ; now retest with HSR0.SA set + set_mem_immed 0,gr0 + set_gr_addr 0xff000000,gr11 + set_bctrlr_0_0 gr11 + or_spr_immed 0x00001000,hsr0 ; set HSR0.SA + +; Can't recover from hardware interrupt with enough state intact to verify it +; set_spr_addr ok4,lr +; dcf @(gr10,gr0) ; Wait for store to happen +; set_mem_immed 0x3,gr10 ; cause hardware reset +; fail +; +;ok4: ; reset should branch to reset address which should then branch here +; test_mem_immed 0x00000200,gr10 +; set_spr_addr ok5,lr +; set_mem_immed 0x2,gr10 ; cause hardware reset +; dcf @(gr10,gr0) ; Wait for store to happen +; fail +; +ok5: ; reset should branch to reset address which should then branch here +; test_mem_immed 0x00000200,gr10 + set_spr_addr ok6,lr + set_mem_immed 0x1,gr10 ; cause software reset + dcf @(gr10,gr0) ; Wait for store to happen + fail + +ok6: ; reset should branch to reset address which should then branch here + test_mem_immed 0x00000100,gr10 + test_spr_bits 0x4,2,1,psr ; psr.s is set + test_spr_bits 0x2,1,1,psr ; psr.ps is set + set_spr_addr bad,lr + set_mem_immed 0x0,gr10 ; no reset + test_mem_immed 0x0,gr10 + + pass + +bad: ; Should never get here + fail diff --git a/sim/testsuite/sim/frv/interrupts/shadow_regs.cgs b/sim/testsuite/sim/frv/interrupts/shadow_regs.cgs new file mode 100644 index 0000000..ee6bea4 --- /dev/null +++ b/sim/testsuite/sim/frv/interrupts/shadow_regs.cgs @@ -0,0 +1,205 @@ +# FRV testcase for handling of shadow registers SR0-SR4 +# mach: frv + + .include "testutils.inc" + + start + + .global tra +tra: + test_spr_bits 0x800,11,1,psr ; PSR.ESR set + test_spr_bits 0x4,2,1,psr ; PSR.S set + + ; Set up exception handler for later + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + set_spr_immed 128,lcr + set_psr_et 1 + + set_gr_immed 0x11111111,gr4 ; SGR4-7 + set_gr_immed 0x22222222,gr5 + set_gr_immed 0x33333333,gr6 + set_gr_immed 0x44444444,gr7 + set_spr_immed 0x55555555,sr0 ; UGR4-7 + set_spr_immed 0x66666666,sr1 + set_spr_immed 0x77777777,sr2 + set_spr_immed 0x88888888,sr3 + + and_spr_immed 0xfffff7ff,psr ; turn off PSR.ESR + test_gr_immed 0x11111111,gr4 ; SGR4-7 + test_gr_immed 0x22222222,gr5 + test_gr_immed 0x33333333,gr6 + test_gr_immed 0x44444444,gr7 + test_spr_immed 0x11111111,sr0 ; SGR4-7 + test_spr_immed 0x22222222,sr1 + test_spr_immed 0x33333333,sr2 + test_spr_immed 0x44444444,sr3 + + set_spr_immed 0x55555555,sr0 ; SGR4-7 + set_spr_immed 0x66666666,sr1 + set_spr_immed 0x77777777,sr2 + set_spr_immed 0x88888888,sr3 + test_gr_immed 0x55555555,gr4 ; SGR4-7 + test_gr_immed 0x66666666,gr5 + test_gr_immed 0x77777777,gr6 + test_gr_immed 0x88888888,gr7 + test_spr_immed 0x55555555,sr0 ; SGR4-7 + test_spr_immed 0x66666666,sr1 + test_spr_immed 0x77777777,sr2 + test_spr_immed 0x88888888,sr3 + + set_gr_immed 0x11111111,gr4 ; SGR4-7 + set_gr_immed 0x22222222,gr5 + set_gr_immed 0x33333333,gr6 + set_gr_immed 0x44444444,gr7 + test_gr_immed 0x11111111,gr4 ; SGR4-7 + test_gr_immed 0x22222222,gr5 + test_gr_immed 0x33333333,gr6 + test_gr_immed 0x44444444,gr7 + test_spr_immed 0x11111111,sr0 ; SGR4-7 + test_spr_immed 0x22222222,sr1 + test_spr_immed 0x33333333,sr2 + test_spr_immed 0x44444444,sr3 + + or_spr_immed 0x00000800,psr ; turn on PSR.ESR + test_gr_immed 0x11111111,gr4 ; SGR4-7 -- SR0-3 (UGR4-7) are undefined + test_gr_immed 0x22222222,gr5 + test_gr_immed 0x33333333,gr6 + test_gr_immed 0x44444444,gr7 + + set_spr_immed 0x55555555,sr0 ; UGR4-7 + set_spr_immed 0x66666666,sr1 + set_spr_immed 0x77777777,sr2 + set_spr_immed 0x88888888,sr3 + test_gr_immed 0x11111111,gr4 ; SGR4-7 + test_gr_immed 0x22222222,gr5 + test_gr_immed 0x33333333,gr6 + test_gr_immed 0x44444444,gr7 + test_spr_immed 0x55555555,sr0 ; UGR4-7 + test_spr_immed 0x66666666,sr1 + test_spr_immed 0x77777777,sr2 + test_spr_immed 0x88888888,sr3 + + and_spr_immed 0xfffffffb,psr ; turn off PSR.S + test_spr_immed 0x11111111,sr0 ; SGR4-7 + test_spr_immed 0x22222222,sr1 + test_spr_immed 0x33333333,sr2 + test_spr_immed 0x44444444,sr3 + test_gr_immed 0x55555555,gr4 ; UGR4-7 + test_gr_immed 0x66666666,gr5 + test_gr_immed 0x77777777,gr6 + test_gr_immed 0x88888888,gr7 + + ; need to generate a trap to return to supervisor mode + set_spr_addr ok0,lr + tira gr0,4 ; should branch to tbr + (128 + 4)*16 + + test_spr_bits 0x800,11,0,psr ; PSR.ESR clear + test_spr_bits 0x4,2,0,psr ; PSR.S clear + test_gr_immed 0x11111111,gr4 ; SGR4-7 + test_gr_immed 0x22222222,gr5 + test_gr_immed 0x33333333,gr6 + test_gr_immed 0x44444444,gr7 + test_spr_immed 0x11111111,sr0 ; SGR4-7 + test_spr_immed 0x22222222,sr1 + test_spr_immed 0x33333333,sr2 + test_spr_immed 0x44444444,sr3 + + set_gr_immed 0x55555555,gr4 ; SGR4-7 + set_gr_immed 0x66666666,gr5 + set_gr_immed 0x77777777,gr6 + set_gr_immed 0x88888888,gr7 + test_gr_immed 0x55555555,gr4 ; SGR4-7 + test_gr_immed 0x66666666,gr5 + test_gr_immed 0x77777777,gr6 + test_gr_immed 0x88888888,gr7 + test_spr_immed 0x55555555,sr0 ; SGR4-7 + test_spr_immed 0x66666666,sr1 + test_spr_immed 0x77777777,sr2 + test_spr_immed 0x88888888,sr3 + + set_gr_immed 0x11111111,gr4 ; SGR4-7 + set_gr_immed 0x22222222,gr5 + set_gr_immed 0x33333333,gr6 + set_gr_immed 0x44444444,gr7 + test_gr_immed 0x11111111,gr4 ; SGR4-7 + test_gr_immed 0x22222222,gr5 + test_gr_immed 0x33333333,gr6 + test_gr_immed 0x44444444,gr7 + test_spr_immed 0x11111111,sr0 ; SGR4-7 + test_spr_immed 0x22222222,sr1 + test_spr_immed 0x33333333,sr2 + test_spr_immed 0x44444444,sr3 + + ; need to generate a trap to return to supervisor mode + set_spr_addr ok1,lr + tira gr0,4 ; should branch to tbr + (128 + 4)*16 + + pass + +ok0: ; exception handler should branch here the first time + test_spr_bits 0x800,11,1,psr ; PSR.ESR set + test_spr_bits 0x4,2,1,psr ; PSR.S set + test_gr_immed 0x11111111,gr4 ; SGR4-7 + test_gr_immed 0x22222222,gr5 + test_gr_immed 0x33333333,gr6 + test_gr_immed 0x44444444,gr7 + test_spr_immed 0x55555555,sr0 ; UGR4-7 + test_spr_immed 0x66666666,sr1 + test_spr_immed 0x77777777,sr2 + test_spr_immed 0x88888888,sr3 + + and_spr_immed 0xfffff7ff,psr ; turn off PSR.ESR + test_gr_immed 0x11111111,gr4 ; SGR4-7 + test_gr_immed 0x22222222,gr5 + test_gr_immed 0x33333333,gr6 + test_gr_immed 0x44444444,gr7 + test_spr_immed 0x11111111,sr0 ; SGR4-7 + test_spr_immed 0x22222222,sr1 + test_spr_immed 0x33333333,sr2 + test_spr_immed 0x44444444,sr3 + rett 0 + fail + +ok1: ; exception handler should branch here the second time + test_spr_bits 0x800,11,0,psr ; PSR.ESR clear + test_spr_bits 0x4,2,1,psr ; PSR.S set + + test_gr_immed 0x11111111,gr4 ; SGR4-7 + test_gr_immed 0x22222222,gr5 + test_gr_immed 0x33333333,gr6 + test_gr_immed 0x44444444,gr7 + test_spr_immed 0x11111111,sr0 ; SGR4-7 + test_spr_immed 0x22222222,sr1 + test_spr_immed 0x33333333,sr2 + test_spr_immed 0x44444444,sr3 + + set_spr_immed 0x55555555,sr0 ; SGR4-7 + set_spr_immed 0x66666666,sr1 + set_spr_immed 0x77777777,sr2 + set_spr_immed 0x88888888,sr3 + test_gr_immed 0x55555555,gr4 ; SGR4-7 + test_gr_immed 0x66666666,gr5 + test_gr_immed 0x77777777,gr6 + test_gr_immed 0x88888888,gr7 + test_spr_immed 0x55555555,sr0 ; SGR4-7 + test_spr_immed 0x66666666,sr1 + test_spr_immed 0x77777777,sr2 + test_spr_immed 0x88888888,sr3 + + set_gr_immed 0x11111111,gr4 ; SGR4-7 + set_gr_immed 0x22222222,gr5 + set_gr_immed 0x33333333,gr6 + set_gr_immed 0x44444444,gr7 + test_gr_immed 0x11111111,gr4 ; SGR4-7 + test_gr_immed 0x22222222,gr5 + test_gr_immed 0x33333333,gr6 + test_gr_immed 0x44444444,gr7 + test_spr_immed 0x11111111,sr0 ; SGR4-7 + test_spr_immed 0x22222222,sr1 + test_spr_immed 0x33333333,sr2 + test_spr_immed 0x44444444,sr3 + rett 0 + fail diff --git a/sim/testsuite/sim/frv/interrupts/timer.cgs b/sim/testsuite/sim/frv/interrupts/timer.cgs new file mode 100644 index 0000000..e9cebc2 --- /dev/null +++ b/sim/testsuite/sim/frv/interrupts/timer.cgs @@ -0,0 +1,31 @@ +# frv testcase to generate timer interrupt for st $GRk,@($GRi,$GRj) +# mach: fr500 fr550 fr400 +# sim: --timer 200,14 + .include "testutils.inc" + + start + + .global align +align: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr17 + inc_gr_immed 0x2e0,gr17 ; address of exception handler + set_bctrlr_0_0 gr17 + set_spr_immed 0x7fffffff,lcr + set_spr_addr ok1,lr + and_spr_immed 0xffffff87,psr ; enable external interrupts + or_spr_immed 0x00000069,psr ; enable external interrupts + + set_gr_immed 10,gr16 + set_gr_immed 0,gr15 + +again: cmp gr15,gr16,icc0 + blt icc0,0,again + + pass + +; exception handler +ok1: + inc_gr_immed 1,gr15 + rett 0 + fail diff --git a/sim/testsuite/sim/frv/jmpil.cgs b/sim/testsuite/sim/frv/jmpil.cgs new file mode 100644 index 0000000..1d11067 --- /dev/null +++ b/sim/testsuite/sim/frv/jmpil.cgs @@ -0,0 +1,17 @@ +# frv testcase for jmpil @($GRi,$d12) +# mach: all + + .include "testutils.inc" + + start + + .global jmpil +jmpil: + set_spr_immed 0,lr + set_gr_addr ok1,gr8 + jmpil @(gr8,2) ; target gets aligned down + fail +ok1: + test_spr_immed 0,lr + + pass diff --git a/sim/testsuite/sim/frv/jmpl.cgs b/sim/testsuite/sim/frv/jmpl.cgs new file mode 100644 index 0000000..9a58e60 --- /dev/null +++ b/sim/testsuite/sim/frv/jmpl.cgs @@ -0,0 +1,18 @@ +# frv testcase for jmpl @($GRi,$GRj) +# mach: all + + .include "testutils.inc" + + start + + .global jmpl +jmpl: + set_spr_immed 0,lr + set_gr_addr ok1,gr8 + set_gr_immed 1,gr9 ; target gets aligned down + jmpl @(gr8,gr9) + fail +ok1: + test_spr_immed 0,lr + + pass diff --git a/sim/testsuite/sim/frv/jmpl.pcgs b/sim/testsuite/sim/frv/jmpl.pcgs new file mode 100644 index 0000000..2126820 --- /dev/null +++ b/sim/testsuite/sim/frv/jmpl.pcgs @@ -0,0 +1,42 @@ +# frv parallel testcase for jmpl @($GRi,$GRj),$LI +# mach: all + + .include "testutils.inc" + + start + + .global jmpl +jmpl: + set_spr_immed 0,lr + set_gr_addr ok1,gr8 + set_gr_immed 0,gr9 + jmpl.p @(gr8,gr9) + setlos 10,gr10 + fail +ok1: + test_spr_immed 0,lr + test_gr_immed 10,gr10 + + set_gr_addr ok2,gr8 + inc_gr_immed -4,gr8 + inc_gr_immed 4,gr9 + calll.p @(gr8,gr9) + setlos 11,gr11 +bad2: + fail +ok2: + test_spr_addr bad2,lr + test_gr_immed 11,gr11 + + set_gr_addr ok3,gr8 + inc_gr_immed 4,gr8 + set_gr_immed -4,gr9 + setlos 12,gr12 + calll @(gr8,gr9) +bad3: + fail +ok3: + test_spr_addr bad3,lr + test_gr_immed 12,gr12 + + pass diff --git a/sim/testsuite/sim/frv/ld.cgs b/sim/testsuite/sim/frv/ld.cgs new file mode 100644 index 0000000..35206c2 --- /dev/null +++ b/sim/testsuite/sim/frv/ld.cgs @@ -0,0 +1,29 @@ +# frv testcase for ld @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global ld +ld: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + ld @(sp,gr7),gr8 + test_gr_limmed 0xdead,0xbeef,gr8 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + ld @(sp,gr7),gr8 + test_gr_limmed 0xdead,0xbeef,gr8 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed 8,sp + set_gr_immed -4,gr7 + ld @(sp,gr7),gr8 + test_gr_limmed 0xdead,0xbeef,gr8 + + pass diff --git a/sim/testsuite/sim/frv/ldbf.cgs b/sim/testsuite/sim/frv/ldbf.cgs new file mode 100644 index 0000000..52ac077 --- /dev/null +++ b/sim/testsuite/sim/frv/ldbf.cgs @@ -0,0 +1,27 @@ +# frv testcase for ldbf @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global ldbf +ldbf: + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + ldbf @(sp,gr7),fr8 + test_fr_limmed 0x0000,0x00de,fr8 + + set_gr_immed 1,gr7 + ldbf @(sp,gr7),fr8 + test_fr_limmed 0x0000,0x00ad,fr8 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + ldbf @(sp,gr7),fr8 + test_fr_limmed 0x0000,0x0000,fr8 + + pass diff --git a/sim/testsuite/sim/frv/ldbfi.cgs b/sim/testsuite/sim/frv/ldbfi.cgs new file mode 100644 index 0000000..7e91806 --- /dev/null +++ b/sim/testsuite/sim/frv/ldbfi.cgs @@ -0,0 +1,24 @@ +# frv testcase for ldbfi @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global ldbfi +ldbfi: + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + ldbfi @(sp,0),fr8 + test_fr_limmed 0x0000,0x00de,fr8 + + ldbfi @(sp,1),fr8 + test_fr_limmed 0x0000,0x00ad,fr8 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + ldbfi @(sp,-1),fr8 + test_fr_limmed 0x0000,0x0000,fr8 + + pass diff --git a/sim/testsuite/sim/frv/ldbfu.cgs b/sim/testsuite/sim/frv/ldbfu.cgs new file mode 100644 index 0000000..3cbfb91 --- /dev/null +++ b/sim/testsuite/sim/frv/ldbfu.cgs @@ -0,0 +1,34 @@ +# frv testcase for ldbfu @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global ldbfu +ldbfu: + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + ldbfu @(sp,gr7),fr8 + test_fr_limmed 0x0000,0x00de,fr8 + test_gr_gr sp,gr20 + + inc_gr_immed 1,gr20 + set_gr_immed 1,gr7 + ldbfu @(sp,gr7),fr8 + test_fr_limmed 0x0000,0x00ad,fr8 + test_gr_gr sp,gr20 + + inc_gr_immed 2,gr20 + inc_gr_immed -1,sp + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + ldbfu @(sp,gr7),fr8 + test_fr_limmed 0x0000,0x0000,fr8 + test_gr_gr sp,gr20 + + pass diff --git a/sim/testsuite/sim/frv/ldc.cgs b/sim/testsuite/sim/frv/ldc.cgs new file mode 100644 index 0000000..4593c31 --- /dev/null +++ b/sim/testsuite/sim/frv/ldc.cgs @@ -0,0 +1,30 @@ +# frv testcase for ldc @($GRi,$GRj),$GRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global ldc +ldc: + set_mem_limmed 0xdead,0xbeef,sp + set_cpr_limmed 0xbeef,0xdead,cpr8 + + set_gr_immed 0,gr7 + ldc @(sp,gr7),cpr8 + test_cpr_limmed 0xdead,0xbeef,cpr8 + + set_cpr_limmed 0xbeef,0xdead,cpr8 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + ldc @(sp,gr7),cpr8 + test_cpr_limmed 0xdead,0xbeef,cpr8 + + set_cpr_limmed 0xbeef,0xdead,cpr8 + inc_gr_immed 8,sp + set_gr_immed -4,gr7 + ldc @(sp,gr7),cpr8 + test_cpr_limmed 0xdead,0xbeef,cpr8 + + pass diff --git a/sim/testsuite/sim/frv/ldcu.cgs b/sim/testsuite/sim/frv/ldcu.cgs new file mode 100644 index 0000000..69890a8 --- /dev/null +++ b/sim/testsuite/sim/frv/ldcu.cgs @@ -0,0 +1,34 @@ +# frv testcase for ldcu @($GRi,$GRj),$GRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global ldcu +ldcu: + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_cpr_limmed 0xbeef,0xdead,cpr8 + + set_gr_immed 0,gr7 + ldcu @(sp,gr7),cpr8 + test_cpr_limmed 0xdead,0xbeef,cpr8 + test_gr_gr sp,gr20 + + set_cpr_limmed 0xbeef,0xdead,cpr8 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + ldcu @(sp,gr7),cpr8 + test_cpr_limmed 0xdead,0xbeef,cpr8 + test_gr_gr sp,gr20 + + set_cpr_limmed 0xbeef,0xdead,cpr8 + inc_gr_immed 4,sp + set_gr_immed -4,gr7 + ldcu @(sp,gr7),cpr8 + test_cpr_limmed 0xdead,0xbeef,cpr8 + test_gr_gr sp,gr20 + + pass diff --git a/sim/testsuite/sim/frv/ldd.cgs b/sim/testsuite/sim/frv/ldd.cgs new file mode 100644 index 0000000..fa09d31 --- /dev/null +++ b/sim/testsuite/sim/frv/ldd.cgs @@ -0,0 +1,43 @@ +# frv testcase for ldd @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global ldd +ldd: + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + + set_gr_immed 0,gr7 + ldd @(sp,gr7),gr8 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + ldd @(sp,gr7),gr8 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + ldd @(sp,gr7),gr8 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + + ; loading into gr0 should have no effect + ; gr1 is sp + set_gr_gr gr1,gr8 + ldd @(sp,gr7),gr0 + test_gr_immed 0,gr0 + test_gr_gr gr1,gr8 + pass diff --git a/sim/testsuite/sim/frv/lddc.cgs b/sim/testsuite/sim/frv/lddc.cgs new file mode 100644 index 0000000..e01a214 --- /dev/null +++ b/sim/testsuite/sim/frv/lddc.cgs @@ -0,0 +1,45 @@ +# frv testcase for lddc @($GRi,$GRj),$GRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global lddc +lddc: + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_cpr_limmed 0xdead,0xbeef,cpr8 + set_cpr_limmed 0xbeef,0xdead,cpr9 + + set_gr_immed 0,gr7 + ; loading into cpr0 is business as usual + set_cpr_limmed 0xdead,0xbeef,cpr0 + set_cpr_limmed 0xbeef,0xdead,cpr1 + lddc @(sp,gr7),cpr0 + test_cpr_limmed 0xbeef,0xdead,cpr0 + test_cpr_limmed 0xdead,0xbeef,cpr1 + + lddc @(sp,gr7),cpr8 + test_cpr_limmed 0xbeef,0xdead,cpr8 + test_cpr_limmed 0xdead,0xbeef,cpr9 + + set_cpr_limmed 0xdead,0xbeef,cpr8 + set_cpr_limmed 0xbeef,0xdead,cpr9 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + lddc @(sp,gr7),cpr8 + test_cpr_limmed 0xbeef,0xdead,cpr8 + test_cpr_limmed 0xdead,0xbeef,cpr9 + + set_cpr_limmed 0xdead,0xbeef,cpr8 + set_cpr_limmed 0xbeef,0xdead,cpr9 + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + lddc @(sp,gr7),cpr8 + test_cpr_limmed 0xbeef,0xdead,cpr8 + test_cpr_limmed 0xdead,0xbeef,cpr9 + + pass diff --git a/sim/testsuite/sim/frv/lddcu.cgs b/sim/testsuite/sim/frv/lddcu.cgs new file mode 100644 index 0000000..b4ed485 --- /dev/null +++ b/sim/testsuite/sim/frv/lddcu.cgs @@ -0,0 +1,42 @@ +# frv testcase for lddcu @($GRi,$GRj),$GRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global lddcu +lddcu: + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_gr sp,gr20 + set_cpr_limmed 0xdead,0xbeef,cpr8 + set_cpr_limmed 0xbeef,0xdead,cpr9 + + set_gr_immed 0,gr7 + lddcu @(sp,gr7),cpr8 + test_cpr_limmed 0xbeef,0xdead,cpr8 + test_cpr_limmed 0xdead,0xbeef,cpr9 + test_gr_gr sp,gr20 + + set_cpr_limmed 0xdead,0xbeef,cpr8 + set_cpr_limmed 0xbeef,0xdead,cpr9 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + lddcu @(sp,gr7),cpr8 + test_cpr_limmed 0xbeef,0xdead,cpr8 + test_cpr_limmed 0xdead,0xbeef,cpr9 + test_gr_gr sp,gr20 + + set_cpr_limmed 0xdead,0xbeef,cpr8 + set_cpr_limmed 0xbeef,0xdead,cpr9 + inc_gr_immed 8,sp + set_gr_immed -8,gr7 + lddcu @(sp,gr7),cpr8 + test_cpr_limmed 0xbeef,0xdead,cpr8 + test_cpr_limmed 0xdead,0xbeef,cpr9 + test_gr_gr sp,gr20 + + pass diff --git a/sim/testsuite/sim/frv/lddf.cgs b/sim/testsuite/sim/frv/lddf.cgs new file mode 100644 index 0000000..f7bae78 --- /dev/null +++ b/sim/testsuite/sim/frv/lddf.cgs @@ -0,0 +1,46 @@ +# frv testcase for lddf @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global lddf +lddf: + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + + set_gr_immed 0,gr7 + ; loading into fr0 is business as usual + set_fr_iimmed 0xdead,0xbeef,fr0 + set_fr_iimmed 0xbeef,0xdead,fr1 + lddf @(sp,gr7),fr0 + test_fr_limmed 0xbeef,0xdead,fr0 + test_fr_limmed 0xdead,0xbeef,fr1 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + lddf @(sp,gr7),fr8 + test_fr_limmed 0xbeef,0xdead,fr8 + test_fr_limmed 0xdead,0xbeef,fr9 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + lddf @(sp,gr7),fr8 + test_fr_limmed 0xbeef,0xdead,fr8 + test_fr_limmed 0xdead,0xbeef,fr9 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + lddf @(sp,gr7),fr8 + test_fr_limmed 0xbeef,0xdead,fr8 + test_fr_limmed 0xdead,0xbeef,fr9 + + pass diff --git a/sim/testsuite/sim/frv/lddfi.cgs b/sim/testsuite/sim/frv/lddfi.cgs new file mode 100644 index 0000000..1eac916 --- /dev/null +++ b/sim/testsuite/sim/frv/lddfi.cgs @@ -0,0 +1,34 @@ +# frv testcase for lddfi @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global lddfi +lddfi: + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + + lddfi @(sp,0),fr8 + test_fr_limmed 0xbeef,0xdead,fr8 + test_fr_limmed 0xdead,0xbeef,fr9 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed -8,sp + lddfi @(sp,8),fr8 + test_fr_limmed 0xbeef,0xdead,fr8 + test_fr_limmed 0xdead,0xbeef,fr9 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed 16,sp + lddfi @(sp,-8),fr8 + test_fr_limmed 0xbeef,0xdead,fr8 + test_fr_limmed 0xdead,0xbeef,fr9 + + pass diff --git a/sim/testsuite/sim/frv/lddfu.cgs b/sim/testsuite/sim/frv/lddfu.cgs new file mode 100644 index 0000000..cb4c86e --- /dev/null +++ b/sim/testsuite/sim/frv/lddfu.cgs @@ -0,0 +1,41 @@ +# frv testcase for lddfu @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global lddfu +lddfu: + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_gr sp,gr20 + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + + set_gr_immed 0,gr7 + lddfu @(sp,gr7),fr8 + test_fr_limmed 0xbeef,0xdead,fr8 + test_fr_limmed 0xdead,0xbeef,fr9 + test_gr_gr sp,gr20 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + lddfu @(sp,gr7),fr8 + test_fr_limmed 0xbeef,0xdead,fr8 + test_fr_limmed 0xdead,0xbeef,fr9 + test_gr_gr sp,gr20 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed 8,sp + set_gr_immed -8,gr7 + lddfu @(sp,gr7),fr8 + test_fr_limmed 0xbeef,0xdead,fr8 + test_fr_limmed 0xdead,0xbeef,fr9 + test_gr_gr sp,gr20 + + pass diff --git a/sim/testsuite/sim/frv/lddi.cgs b/sim/testsuite/sim/frv/lddi.cgs new file mode 100644 index 0000000..38ef2b4 --- /dev/null +++ b/sim/testsuite/sim/frv/lddi.cgs @@ -0,0 +1,34 @@ +# frv testcase for lddi @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global lddi +lddi: + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + + lddi @(sp,0),gr8 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed -8,sp + lddi @(sp,8),gr8 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed 16,sp + lddi @(sp,-8),gr8 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + + pass diff --git a/sim/testsuite/sim/frv/lddu.cgs b/sim/testsuite/sim/frv/lddu.cgs new file mode 100644 index 0000000..5b2ead1 --- /dev/null +++ b/sim/testsuite/sim/frv/lddu.cgs @@ -0,0 +1,50 @@ +# frv testcase for lddu @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global lddu +lddu: + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_gr sp,gr20 + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + + set_gr_immed 0,gr7 + lddu @(sp,gr7),gr8 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + test_gr_gr sp,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + lddu @(sp,gr7),gr8 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + test_gr_gr sp,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed 8,sp + set_gr_immed -8,gr7 + lddu @(sp,gr7),gr8 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + test_gr_gr sp,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed 8,sp + set_gr_immed -8,gr7 + set_gr_gr sp,gr8 + lddu @(gr8,gr7),gr8 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + + pass diff --git a/sim/testsuite/sim/frv/ldf.cgs b/sim/testsuite/sim/frv/ldf.cgs new file mode 100644 index 0000000..996d72c --- /dev/null +++ b/sim/testsuite/sim/frv/ldf.cgs @@ -0,0 +1,29 @@ +# frv testcase for ldf @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global ldf +ldf: + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + ldf @(sp,gr7),fr8 + test_fr_limmed 0xdead,0xbeef,fr8 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + ldf @(sp,gr7),fr8 + test_fr_limmed 0xdead,0xbeef,fr8 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed 8,sp + set_gr_immed -4,gr7 + ldf @(sp,gr7),fr8 + test_fr_limmed 0xdead,0xbeef,fr8 + + pass diff --git a/sim/testsuite/sim/frv/ldfi.cgs b/sim/testsuite/sim/frv/ldfi.cgs new file mode 100644 index 0000000..e5ea94d --- /dev/null +++ b/sim/testsuite/sim/frv/ldfi.cgs @@ -0,0 +1,26 @@ +# frv testcase for ldfi @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global ldfi +ldfi: + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + ldfi @(sp,0),fr8 + test_fr_limmed 0xdead,0xbeef,fr8 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed -4,sp + ldfi @(sp,4),fr8 + test_fr_limmed 0xdead,0xbeef,fr8 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed 8,sp + ldfi @(sp,-4),fr8 + test_fr_limmed 0xdead,0xbeef,fr8 + + pass diff --git a/sim/testsuite/sim/frv/ldfu.cgs b/sim/testsuite/sim/frv/ldfu.cgs new file mode 100644 index 0000000..08f67db --- /dev/null +++ b/sim/testsuite/sim/frv/ldfu.cgs @@ -0,0 +1,33 @@ +# frv testcase for ldfu @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global ldfu +ldfu: + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + ldfu @(sp,gr7),fr8 + test_fr_limmed 0xdead,0xbeef,fr8 + test_gr_gr sp,gr20 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + ldfu @(sp,gr7),fr8 + test_fr_limmed 0xdead,0xbeef,fr8 + test_gr_gr sp,gr20 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed 4,sp + set_gr_immed -4,gr7 + ldfu @(sp,gr7),fr8 + test_fr_limmed 0xdead,0xbeef,fr8 + test_gr_gr sp,gr20 + + pass diff --git a/sim/testsuite/sim/frv/ldhf.cgs b/sim/testsuite/sim/frv/ldhf.cgs new file mode 100644 index 0000000..8935ac7 --- /dev/null +++ b/sim/testsuite/sim/frv/ldhf.cgs @@ -0,0 +1,27 @@ +# frv testcase for ldhf @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global ldhf +ldhf: + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + ldhf @(sp,gr7),fr8 + test_fr_limmed 0x0000,0xdead,fr8 + + set_gr_immed 2,gr7 + ldhf @(sp,gr7),fr8 + test_fr_limmed 0x0000,0xbeef,fr8 + + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + ldhf @(sp,gr7),fr8 + test_fr_limmed 0x0000,0x0000,fr8 + + pass diff --git a/sim/testsuite/sim/frv/ldhfi.cgs b/sim/testsuite/sim/frv/ldhfi.cgs new file mode 100644 index 0000000..362ec50 --- /dev/null +++ b/sim/testsuite/sim/frv/ldhfi.cgs @@ -0,0 +1,24 @@ +# frv testcase for ldhfi @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global ldhfi +ldhfi: + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + ldhfi @(sp,0),fr8 + test_fr_limmed 0x0000,0xdead,fr8 + + ldhfi @(sp,2),fr8 + test_fr_limmed 0x0000,0xbeef,fr8 + + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + ldhfi @(sp,-2),fr8 + test_fr_limmed 0x0000,0x0000,fr8 + + pass diff --git a/sim/testsuite/sim/frv/ldhfu.cgs b/sim/testsuite/sim/frv/ldhfu.cgs new file mode 100644 index 0000000..0b342e1 --- /dev/null +++ b/sim/testsuite/sim/frv/ldhfu.cgs @@ -0,0 +1,33 @@ +# frv testcase for ldhfu @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global ldhfu +ldhfu: + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + ldhfu @(sp,gr7),fr8 + test_fr_limmed 0x0000,0xdead,fr8 + test_gr_gr sp,gr20 + + inc_gr_immed 2,gr20 + set_gr_immed 2,gr7 + ldhfu @(sp,gr7),fr8 + test_fr_limmed 0x0000,0xbeef,fr8 + test_gr_gr sp,gr20 + + inc_gr_immed -2,sp + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + ldhfu @(sp,gr7),fr8 + test_fr_limmed 0x0000,0x0000,fr8 + test_gr_gr sp,gr20 + + pass diff --git a/sim/testsuite/sim/frv/ldi.cgs b/sim/testsuite/sim/frv/ldi.cgs new file mode 100644 index 0000000..f36b95d --- /dev/null +++ b/sim/testsuite/sim/frv/ldi.cgs @@ -0,0 +1,26 @@ +# frv testcase for ldi @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global ldi +ldi: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + ldi @(sp,0),gr8 + test_gr_limmed 0xdead,0xbeef,gr8 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed -4,sp + ldi @(sp,4),gr8 + test_gr_limmed 0xdead,0xbeef,gr8 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed 8,sp + ldi @(sp,-4),gr8 + test_gr_limmed 0xdead,0xbeef,gr8 + + pass diff --git a/sim/testsuite/sim/frv/ldq.cgs b/sim/testsuite/sim/frv/ldq.cgs new file mode 100644 index 0000000..e61f1de --- /dev/null +++ b/sim/testsuite/sim/frv/ldq.cgs @@ -0,0 +1,64 @@ +# frv testcase for ldq @($GRi,$GRj),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global ldq +ldq: + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0x1234,0x5678,sp + inc_gr_immed -4,sp + set_mem_limmed 0x9abc,0xdef0,sp + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + + set_gr_immed 0,gr7 + ldq @(sp,gr7),gr8 + test_gr_limmed 0x9abc,0xdef0,gr8 + test_gr_limmed 0x1234,0x5678,gr9 + test_gr_limmed 0xbeef,0xdead,gr10 + test_gr_limmed 0xdead,0xbeef,gr11 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed -16,sp + set_gr_immed 16,gr7 + ldq @(sp,gr7),gr8 + test_gr_limmed 0x9abc,0xdef0,gr8 + test_gr_limmed 0x1234,0x5678,gr9 + test_gr_limmed 0xbeef,0xdead,gr10 + test_gr_limmed 0xdead,0xbeef,gr11 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed 32,sp + set_gr_immed -16,gr7 + ldq @(sp,gr7),gr8 + test_gr_limmed 0x9abc,0xdef0,gr8 + test_gr_limmed 0x1234,0x5678,gr9 + test_gr_limmed 0xbeef,0xdead,gr10 + test_gr_limmed 0xdead,0xbeef,gr11 + + ; loading into gr0 has no effect + ; gr1 is sp + set_gr_gr gr1,gr8 + set_gr_limmed 0x1234,0x5678,gr2 + set_gr_limmed 0x9abc,0xdef0,gr3 + ldq @(sp,gr7),gr0 + test_gr_immed 0,gr0 + test_gr_gr gr1,gr8 + set_gr_immed 0x12345678,gr2 + set_gr_immed 0x9abcdef0,gr3 + + pass diff --git a/sim/testsuite/sim/frv/ldqc.cgs b/sim/testsuite/sim/frv/ldqc.cgs new file mode 100644 index 0000000..64b6a6a --- /dev/null +++ b/sim/testsuite/sim/frv/ldqc.cgs @@ -0,0 +1,60 @@ +# frv testcase for ldqc @($GRi,$GRj),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global ldqc +ldqc: + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0x1234,0x5678,sp + inc_gr_immed -4,sp + set_mem_limmed 0x9abc,0xdef0,sp + set_cpr_limmed 0xdead,0xbeef,cpr8 + set_cpr_limmed 0xbeef,0xdead,cpr9 + set_cpr_limmed 0x1234,0x5678,cpr10 + set_cpr_limmed 0x9abc,0xdef0,cpr11 + + set_gr_immed 0,gr7 + ;loading into cpr0 is business as usual + ldqc @(sp,gr7),cpr0 + test_cpr_limmed 0x9abc,0xdef0,cpr0 + test_cpr_limmed 0x1234,0x5678,cpr1 + test_cpr_limmed 0xbeef,0xdead,cpr2 + test_cpr_limmed 0xdead,0xbeef,cpr3 + + ldqc @(sp,gr7),cpr8 + test_cpr_limmed 0x9abc,0xdef0,cpr8 + test_cpr_limmed 0x1234,0x5678,cpr9 + test_cpr_limmed 0xbeef,0xdead,cpr10 + test_cpr_limmed 0xdead,0xbeef,cpr11 + + set_cpr_limmed 0xdead,0xbeef,cpr8 + set_cpr_limmed 0xbeef,0xdead,cpr9 + set_cpr_limmed 0x1234,0x5678,cpr10 + set_cpr_limmed 0x9abc,0xdef0,cpr11 + inc_gr_immed -16,sp + set_gr_immed 16,gr7 + ldqc @(sp,gr7),cpr8 + test_cpr_limmed 0x9abc,0xdef0,cpr8 + test_cpr_limmed 0x1234,0x5678,cpr9 + test_cpr_limmed 0xbeef,0xdead,cpr10 + test_cpr_limmed 0xdead,0xbeef,cpr11 + + set_cpr_limmed 0xdead,0xbeef,cpr8 + set_cpr_limmed 0xbeef,0xdead,cpr9 + set_cpr_limmed 0x1234,0x5678,cpr10 + set_cpr_limmed 0x9abc,0xdef0,cpr11 + inc_gr_immed 32,sp + set_gr_immed -16,gr7 + ldqc @(sp,gr7),cpr8 + test_cpr_limmed 0x9abc,0xdef0,cpr8 + test_cpr_limmed 0x1234,0x5678,cpr9 + test_cpr_limmed 0xbeef,0xdead,cpr10 + test_cpr_limmed 0xdead,0xbeef,cpr11 + + pass diff --git a/sim/testsuite/sim/frv/ldqcu.cgs b/sim/testsuite/sim/frv/ldqcu.cgs new file mode 100644 index 0000000..18d9246 --- /dev/null +++ b/sim/testsuite/sim/frv/ldqcu.cgs @@ -0,0 +1,57 @@ +# frv testcase for ldqcu @($GRi,$GRj),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global ldqcu +ldqcu: + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0x1234,0x5678,sp + inc_gr_immed -4,sp + set_mem_limmed 0x9abc,0xdef0,sp + set_gr_gr sp,gr20 + set_cpr_limmed 0xdead,0xbeef,cpr8 + set_cpr_limmed 0xbeef,0xdead,cpr9 + set_cpr_limmed 0x1234,0x5678,cpr10 + set_cpr_limmed 0x9abc,0xdef0,cpr11 + + set_gr_immed 0,gr7 + ldqcu @(sp,gr7),cpr8 + test_cpr_limmed 0x9abc,0xdef0,cpr8 + test_cpr_limmed 0x1234,0x5678,cpr9 + test_cpr_limmed 0xbeef,0xdead,cpr10 + test_cpr_limmed 0xdead,0xbeef,cpr11 + test_gr_gr sp,gr20 + + set_cpr_limmed 0xdead,0xbeef,cpr8 + set_cpr_limmed 0xbeef,0xdead,cpr9 + set_cpr_limmed 0x1234,0x5678,cpr10 + set_cpr_limmed 0x9abc,0xdef0,cpr11 + inc_gr_immed -16,sp + set_gr_immed 16,gr7 + ldqcu @(sp,gr7),cpr8 + test_cpr_limmed 0x9abc,0xdef0,cpr8 + test_cpr_limmed 0x1234,0x5678,cpr9 + test_cpr_limmed 0xbeef,0xdead,cpr10 + test_cpr_limmed 0xdead,0xbeef,cpr11 + test_gr_gr sp,gr20 + + set_cpr_limmed 0xdead,0xbeef,cpr8 + set_cpr_limmed 0xbeef,0xdead,cpr9 + set_cpr_limmed 0x1234,0x5678,cpr10 + set_cpr_limmed 0x9abc,0xdef0,cpr11 + inc_gr_immed 16,sp + set_gr_immed -16,gr7 + ldqcu @(sp,gr7),cpr8 + test_cpr_limmed 0x9abc,0xdef0,cpr8 + test_cpr_limmed 0x1234,0x5678,cpr9 + test_cpr_limmed 0xbeef,0xdead,cpr10 + test_cpr_limmed 0xdead,0xbeef,cpr11 + test_gr_gr sp,gr20 + + pass diff --git a/sim/testsuite/sim/frv/ldqf.cgs b/sim/testsuite/sim/frv/ldqf.cgs new file mode 100644 index 0000000..66fb65c --- /dev/null +++ b/sim/testsuite/sim/frv/ldqf.cgs @@ -0,0 +1,61 @@ +# frv testcase for ldqf @($GRi,$GRj),$GRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global ldqf +ldqf: + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0x1234,0x5678,sp + inc_gr_immed -4,sp + set_mem_limmed 0x9abc,0xdef0,sp + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x9abc,0xdef0,fr11 + + set_gr_immed 0,gr7 + ; loading into fr0 is business as usual + ldqf @(sp,gr7),fr0 + test_fr_limmed 0x9abc,0xdef0,fr0 + test_fr_limmed 0x1234,0x5678,fr1 + test_fr_limmed 0xbeef,0xdead,fr2 + test_fr_limmed 0xdead,0xbeef,fr3 + + ldqf @(sp,gr7),fr8 + test_fr_limmed 0x9abc,0xdef0,fr8 + test_fr_limmed 0x1234,0x5678,fr9 + test_fr_limmed 0xbeef,0xdead,fr10 + test_fr_limmed 0xdead,0xbeef,fr11 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x9abc,0xdef0,fr11 + inc_gr_immed -16,sp + set_gr_immed 16,gr7 + ldqf @(sp,gr7),fr8 + test_fr_limmed 0x9abc,0xdef0,fr8 + test_fr_limmed 0x1234,0x5678,fr9 + test_fr_limmed 0xbeef,0xdead,fr10 + test_fr_limmed 0xdead,0xbeef,fr11 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x9abc,0xdef0,fr11 + inc_gr_immed 32,sp + set_gr_immed -16,gr7 + ldqf @(sp,gr7),fr8 + test_fr_limmed 0x9abc,0xdef0,fr8 + test_fr_limmed 0x1234,0x5678,fr9 + test_fr_limmed 0xbeef,0xdead,fr10 + test_fr_limmed 0xdead,0xbeef,fr11 + + pass diff --git a/sim/testsuite/sim/frv/ldqfi.cgs b/sim/testsuite/sim/frv/ldqfi.cgs new file mode 100644 index 0000000..28c3b1f --- /dev/null +++ b/sim/testsuite/sim/frv/ldqfi.cgs @@ -0,0 +1,51 @@ +# frv testcase for ldqfi @($GRi,$GRj),$GRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global ldqfi +ldqfi: + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0x1234,0x5678,sp + inc_gr_immed -4,sp + set_mem_limmed 0x9abc,0xdef0,sp + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x9abc,0xdef0,fr11 + + ldqfi @(sp,0),fr8 + test_fr_limmed 0x9abc,0xdef0,fr8 + test_fr_limmed 0x1234,0x5678,fr9 + test_fr_limmed 0xbeef,0xdead,fr10 + test_fr_limmed 0xdead,0xbeef,fr11 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x9abc,0xdef0,fr11 + inc_gr_immed -16,sp + ldqfi @(sp,16),fr8 + test_fr_limmed 0x9abc,0xdef0,fr8 + test_fr_limmed 0x1234,0x5678,fr9 + test_fr_limmed 0xbeef,0xdead,fr10 + test_fr_limmed 0xdead,0xbeef,fr11 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x9abc,0xdef0,fr11 + inc_gr_immed 32,sp + ldqfi @(sp,-16),fr8 + test_fr_limmed 0x9abc,0xdef0,fr8 + test_fr_limmed 0x1234,0x5678,fr9 + test_fr_limmed 0xbeef,0xdead,fr10 + test_fr_limmed 0xdead,0xbeef,fr11 + + pass diff --git a/sim/testsuite/sim/frv/ldqfu.cgs b/sim/testsuite/sim/frv/ldqfu.cgs new file mode 100644 index 0000000..7287958 --- /dev/null +++ b/sim/testsuite/sim/frv/ldqfu.cgs @@ -0,0 +1,58 @@ +# frv testcase for ldqfu @($GRi,$GRj),$GRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global ldqfu +ldqfu: + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0x1234,0x5678,sp + inc_gr_immed -4,sp + set_mem_limmed 0x9abc,0xdef0,sp + set_gr_gr sp,gr20 + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x9abc,0xdef0,fr11 + + set_gr_immed 0,gr7 + ldqfu @(sp,gr7),fr8 + test_fr_limmed 0x9abc,0xdef0,fr8 + test_fr_limmed 0x1234,0x5678,fr9 + test_fr_limmed 0xbeef,0xdead,fr10 + test_fr_limmed 0xdead,0xbeef,fr11 + test_gr_gr sp,gr20 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x9abc,0xdef0,fr11 + inc_gr_immed -16,sp + set_gr_immed 16,gr7 + ldqfu @(sp,gr7),fr8 + test_fr_limmed 0x9abc,0xdef0,fr8 + test_fr_limmed 0x1234,0x5678,fr9 + test_fr_limmed 0xbeef,0xdead,fr10 + test_fr_limmed 0xdead,0xbeef,fr11 + test_gr_gr sp,gr20 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x9abc,0xdef0,fr11 + inc_gr_immed 16,sp + set_gr_immed -16,gr7 + ldqfu @(sp,gr7),fr8 + test_fr_limmed 0x9abc,0xdef0,fr8 + test_fr_limmed 0x1234,0x5678,fr9 + test_fr_limmed 0xbeef,0xdead,fr10 + test_fr_limmed 0xdead,0xbeef,fr11 + test_gr_gr sp,gr20 + + pass diff --git a/sim/testsuite/sim/frv/ldqi.cgs b/sim/testsuite/sim/frv/ldqi.cgs new file mode 100644 index 0000000..64d66f2 --- /dev/null +++ b/sim/testsuite/sim/frv/ldqi.cgs @@ -0,0 +1,51 @@ +# frv testcase for ldqi @($GRi,$GRj),$GRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global ldqi +ldqi: + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0x1234,0x5678,sp + inc_gr_immed -4,sp + set_mem_limmed 0x9abc,0xdef0,sp + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + + ldqi @(sp,0),gr8 + test_gr_limmed 0x9abc,0xdef0,gr8 + test_gr_limmed 0x1234,0x5678,gr9 + test_gr_limmed 0xbeef,0xdead,gr10 + test_gr_limmed 0xdead,0xbeef,gr11 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed -16,sp + ldqi @(sp,16),gr8 + test_gr_limmed 0x9abc,0xdef0,gr8 + test_gr_limmed 0x1234,0x5678,gr9 + test_gr_limmed 0xbeef,0xdead,gr10 + test_gr_limmed 0xdead,0xbeef,gr11 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed 32,sp + ldqi @(sp,-16),gr8 + test_gr_limmed 0x9abc,0xdef0,gr8 + test_gr_limmed 0x1234,0x5678,gr9 + test_gr_limmed 0xbeef,0xdead,gr10 + test_gr_limmed 0xdead,0xbeef,gr11 + + pass diff --git a/sim/testsuite/sim/frv/ldqu.cgs b/sim/testsuite/sim/frv/ldqu.cgs new file mode 100644 index 0000000..263eae1 --- /dev/null +++ b/sim/testsuite/sim/frv/ldqu.cgs @@ -0,0 +1,71 @@ +# frv testcase for ldqu @($GRi,$GRj),$GRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global ldqu +ldqu: + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0x1234,0x5678,sp + inc_gr_immed -4,sp + set_mem_limmed 0x9abc,0xdef0,sp + set_gr_gr sp,gr20 + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + + set_gr_immed 0,gr7 + ldqu @(sp,gr7),gr8 + test_gr_limmed 0x9abc,0xdef0,gr8 + test_gr_limmed 0x1234,0x5678,gr9 + test_gr_limmed 0xbeef,0xdead,gr10 + test_gr_limmed 0xdead,0xbeef,gr11 + test_gr_gr sp,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed -16,sp + set_gr_immed 16,gr7 + ldqu @(sp,gr7),gr8 + test_gr_limmed 0x9abc,0xdef0,gr8 + test_gr_limmed 0x1234,0x5678,gr9 + test_gr_limmed 0xbeef,0xdead,gr10 + test_gr_limmed 0xdead,0xbeef,gr11 + test_gr_gr sp,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed 16,sp + set_gr_immed -16,gr7 + ldqu @(sp,gr7),gr8 + test_gr_limmed 0x9abc,0xdef0,gr8 + test_gr_limmed 0x1234,0x5678,gr9 + test_gr_limmed 0xbeef,0xdead,gr10 + test_gr_limmed 0xdead,0xbeef,gr11 + test_gr_gr sp,gr20 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed 16,sp + set_gr_immed -16,gr7 + set_gr_gr sp,gr8 + ldqu @(gr8,gr7),gr8 + test_gr_limmed 0x9abc,0xdef0,gr8 + test_gr_limmed 0x1234,0x5678,gr9 + test_gr_limmed 0xbeef,0xdead,gr10 + test_gr_limmed 0xdead,0xbeef,gr11 + + pass diff --git a/sim/testsuite/sim/frv/ldsb.cgs b/sim/testsuite/sim/frv/ldsb.cgs new file mode 100644 index 0000000..4b10639 --- /dev/null +++ b/sim/testsuite/sim/frv/ldsb.cgs @@ -0,0 +1,27 @@ +# frv testcase for ldsb @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global ldsb +ldsb: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + ldsb @(sp,gr7),gr8 + test_gr_limmed 0xffff,0xffde,gr8 + + set_gr_immed 1,gr7 + ldsb @(sp,gr7),gr8 + test_gr_limmed 0xffff,0xffad,gr8 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + ldsb @(sp,gr7),gr8 + test_gr_immed 0,gr8 + + pass diff --git a/sim/testsuite/sim/frv/ldsbi.cgs b/sim/testsuite/sim/frv/ldsbi.cgs new file mode 100644 index 0000000..c90a129 --- /dev/null +++ b/sim/testsuite/sim/frv/ldsbi.cgs @@ -0,0 +1,24 @@ +# frv testcase for ldsbi @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global ldsbi +ldsbi: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + ldsbi @(sp,0),gr8 + test_gr_limmed 0xffff,0xffde,gr8 + + ldsbi @(sp,1),gr8 + test_gr_limmed 0xffff,0xffad,gr8 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + ldsbi @(sp,-1),gr8 + test_gr_immed 0,gr8 + + pass diff --git a/sim/testsuite/sim/frv/ldsbu.cgs b/sim/testsuite/sim/frv/ldsbu.cgs new file mode 100644 index 0000000..976cee8 --- /dev/null +++ b/sim/testsuite/sim/frv/ldsbu.cgs @@ -0,0 +1,40 @@ +# frv testcase for ldsbu @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global ldsbu +ldsbu: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + ldsbu @(sp,gr7),gr8 + test_gr_limmed 0xffff,0xffde,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed 1,gr9 + set_gr_immed 1,gr7 + ldsbu @(sp,gr7),gr8 + test_gr_limmed 0xffff,0xffad,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed 2,gr9 + inc_gr_immed -1,sp + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + ldsbu @(sp,gr7),gr8 + test_gr_immed 0,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed -3,sp + set_mem_limmed 0x0000,0x00da,sp + set_gr_immed 3,gr7 + ldsbu @(sp,gr7),sp + test_gr_limmed 0xffff,0xffda,sp + + pass diff --git a/sim/testsuite/sim/frv/ldsh.cgs b/sim/testsuite/sim/frv/ldsh.cgs new file mode 100644 index 0000000..c526f39 --- /dev/null +++ b/sim/testsuite/sim/frv/ldsh.cgs @@ -0,0 +1,27 @@ +# frv testcase for ldsh @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global ldsh +ldsh: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + ldsh @(sp,gr7),gr8 + test_gr_limmed 0xffff,0xdead,gr8 + + set_gr_immed 2,gr7 + ldsh @(sp,gr7),gr8 + test_gr_limmed 0xffff,0xbeef,gr8 + + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + ldsh @(sp,gr7),gr8 + test_gr_immed 0,gr8 + + pass diff --git a/sim/testsuite/sim/frv/ldshi.cgs b/sim/testsuite/sim/frv/ldshi.cgs new file mode 100644 index 0000000..69f99f1 --- /dev/null +++ b/sim/testsuite/sim/frv/ldshi.cgs @@ -0,0 +1,24 @@ +# frv testcase for ldshi @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global ldshi +ldshi: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + ldshi @(sp,0),gr8 + test_gr_limmed 0xffff,0xdead,gr8 + + ldshi @(sp,2),gr8 + test_gr_limmed 0xffff,0xbeef,gr8 + + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + ldshi @(sp,-2),gr8 + test_gr_immed 0,gr8 + + pass diff --git a/sim/testsuite/sim/frv/ldshu.cgs b/sim/testsuite/sim/frv/ldshu.cgs new file mode 100644 index 0000000..f1b8c23 --- /dev/null +++ b/sim/testsuite/sim/frv/ldshu.cgs @@ -0,0 +1,39 @@ +# frv testcase for ldshu @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global ldshu +ldshu: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + ldshu @(sp,gr7),gr8 + test_gr_limmed 0xffff,0xdead,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed 2,gr9 + set_gr_immed 2,gr7 + ldshu @(sp,gr7),gr8 + test_gr_limmed 0xffff,0xbeef,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed -2,sp + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + ldshu @(sp,gr7),gr8 + test_gr_immed 0,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed -2,sp + set_mem_limmed 0x0000,0xdead,sp + set_gr_immed 2,gr7 + ldshu @(sp,gr7),sp + test_gr_limmed 0xffff,0xdead,sp + + pass diff --git a/sim/testsuite/sim/frv/ldu.cgs b/sim/testsuite/sim/frv/ldu.cgs new file mode 100644 index 0000000..b7f2e34 --- /dev/null +++ b/sim/testsuite/sim/frv/ldu.cgs @@ -0,0 +1,39 @@ +# frv testcase for ldu @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global ldu +ldu: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + ldu @(sp,gr7),gr8 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_gr sp,gr9 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + ldu @(sp,gr7),gr8 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_gr sp,gr9 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed 4,sp + set_gr_immed -4,gr7 + ldu @(sp,gr7),gr8 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_gr sp,gr9 + + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + ldu @(sp,gr7),sp + test_gr_limmed 0xdead,0xbeef,sp + + pass diff --git a/sim/testsuite/sim/frv/ldub.cgs b/sim/testsuite/sim/frv/ldub.cgs new file mode 100644 index 0000000..1e19254 --- /dev/null +++ b/sim/testsuite/sim/frv/ldub.cgs @@ -0,0 +1,27 @@ +# frv testcase for ldub @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global ldub +ldub: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + ldub @(sp,gr7),gr8 + test_gr_limmed 0x0000,0x00de,gr8 + + set_gr_immed 1,gr7 + ldub @(sp,gr7),gr8 + test_gr_limmed 0x0000,0x00ad,gr8 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + ldub @(sp,gr7),gr8 + test_gr_limmed 0x0000,0x0000,gr8 + + pass diff --git a/sim/testsuite/sim/frv/ldubi.cgs b/sim/testsuite/sim/frv/ldubi.cgs new file mode 100644 index 0000000..4c40bee --- /dev/null +++ b/sim/testsuite/sim/frv/ldubi.cgs @@ -0,0 +1,24 @@ +# frv testcase for ldubi @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global ldubi +ldubi: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + ldubi @(sp,0),gr8 + test_gr_limmed 0x0000,0x00de,gr8 + + ldubi @(sp,1),gr8 + test_gr_limmed 0x0000,0x00ad,gr8 + + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + ldubi @(sp,-1),gr8 + test_gr_limmed 0x0000,0x0000,gr8 + + pass diff --git a/sim/testsuite/sim/frv/ldubu.cgs b/sim/testsuite/sim/frv/ldubu.cgs new file mode 100644 index 0000000..8c99ab0 --- /dev/null +++ b/sim/testsuite/sim/frv/ldubu.cgs @@ -0,0 +1,39 @@ +# frv testcase for ldubu @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global ldubu +ldubu: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + ldubu @(sp,gr7),gr8 + test_gr_limmed 0x0000,0x00de,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed 1,gr9 + set_gr_immed 1,gr7 + ldubu @(sp,gr7),gr8 + test_gr_limmed 0x0000,0x00ad,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed 2,gr9 + inc_gr_immed -1,sp + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + ldubu @(sp,gr7),gr8 + test_gr_limmed 0x0000,0x0000,gr8 + + inc_gr_immed -3,sp + set_mem_limmed 0xffff,0xffda,sp + set_gr_immed 3,gr7 + ldubu @(sp,gr7),sp + test_gr_limmed 0x0000,0x00da,sp + + pass diff --git a/sim/testsuite/sim/frv/lduh.cgs b/sim/testsuite/sim/frv/lduh.cgs new file mode 100644 index 0000000..24c3bac --- /dev/null +++ b/sim/testsuite/sim/frv/lduh.cgs @@ -0,0 +1,27 @@ +# frv testcase for lduh @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global lduh +lduh: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_immed 0,gr7 + lduh @(sp,gr7),gr8 + test_gr_limmed 0x0000,0xdead,gr8 + + set_gr_immed 2,gr7 + lduh @(sp,gr7),gr8 + test_gr_limmed 0x0000,0xbeef,gr8 + + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + lduh @(sp,gr7),gr8 + test_gr_limmed 0x0000,0x0000,gr8 + + pass diff --git a/sim/testsuite/sim/frv/lduhi.cgs b/sim/testsuite/sim/frv/lduhi.cgs new file mode 100644 index 0000000..b9896d6 --- /dev/null +++ b/sim/testsuite/sim/frv/lduhi.cgs @@ -0,0 +1,24 @@ +# frv testcase for lduhi @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global lduhi +lduhi: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + lduhi @(sp,0),gr8 + test_gr_limmed 0x0000,0xdead,gr8 + + lduhi @(sp,2),gr8 + test_gr_limmed 0x0000,0xbeef,gr8 + + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + lduhi @(sp,-2),gr8 + test_gr_limmed 0x0000,0x0000,gr8 + + pass diff --git a/sim/testsuite/sim/frv/lduhu.cgs b/sim/testsuite/sim/frv/lduhu.cgs new file mode 100644 index 0000000..52faecf --- /dev/null +++ b/sim/testsuite/sim/frv/lduhu.cgs @@ -0,0 +1,39 @@ +# frv testcase for lduhu @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global lduhu +lduhu: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + lduhu @(sp,gr7),gr8 + test_gr_limmed 0x0000,0xdead,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed 2,gr9 + set_gr_immed 2,gr7 + lduhu @(sp,gr7),gr8 + test_gr_limmed 0x0000,0xbeef,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed -2,sp + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + lduhu @(sp,gr7),gr8 + test_gr_limmed 0x0000,0x0000,gr8 + test_gr_gr sp,gr9 + + inc_gr_immed -2,sp + set_mem_limmed 0xffff,0xdead,sp + set_gr_immed 2,gr7 + lduhu @(sp,gr7),sp + test_gr_limmed 0x0000,0xdead,sp + + pass diff --git a/sim/testsuite/sim/frv/lrbranch.pcgs b/sim/testsuite/sim/frv/lrbranch.pcgs new file mode 100644 index 0000000..0ac1a75 --- /dev/null +++ b/sim/testsuite/sim/frv/lrbranch.pcgs @@ -0,0 +1,51 @@ +# frv parallel testcase for lr branching +# mach: fr500 fr550 frv + + .include "testutils.inc" + + start + + .global lrbranch +lrbranch: + ; Both conditions true + set_spr_immed 128,lcr + set_spr_addr ok1,lr + set_icc 0x4 0 + bcgelr.p icc0,0,0 + bra ok4 + fail +ok1: + test_spr_immed 127,LCR + + ; Only first condition true + set_spr_immed 128,lcr + set_spr_addr ok2,lr + set_icc 0x0 0 + bcgelr.p icc0,0,0 + bno + fail +ok2: + test_spr_immed 127,LCR + + ; Only second condition true + set_spr_immed 128,lcr + set_spr_addr ok3,lr + set_icc 0x8 0 + bcgelr.p icc0,0,0 + bra ok3 + fail +ok3: + test_spr_immed 127,LCR + + ; Both conditions false + set_spr_immed 128,lcr + set_spr_addr ok4,lr + set_icc 0x0 0 + bceqlr.p icc0,0,0 + bno + test_spr_immed 127,LCR + + pass + +ok4: + fail diff --git a/sim/testsuite/sim/frv/mabshs.cgs b/sim/testsuite/sim/frv/mabshs.cgs new file mode 100644 index 0000000..29b2532 --- /dev/null +++ b/sim/testsuite/sim/frv/mabshs.cgs @@ -0,0 +1,67 @@ +# frv testcase for mabshs $FRj,$FRk +# mach: fr400 + + .include "testutils.inc" + + start + + .global mabshs +mabshs: + set_fr_iimmed 0x0000,0x0000,fr10 + mabshs fr10,fr11 + test_fr_limmed 0x0000,0x0000,fr11 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0001,0xffff,fr10 + mabshs fr10,fr11 + test_fr_limmed 0x0001,0x0001,fr11 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x7fff,0x8001,fr10 + mabshs fr10,fr11 + test_fr_limmed 0x7fff,0x7fff,fr11 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x7fff,0x8000,fr10 + mabshs fr10,fr11 + test_fr_limmed 0x7fff,0x7fff,fr11 + test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8000,0x7fff,fr10 + mabshs fr10,fr11 + test_fr_limmed 0x7fff,0x7fff,fr11 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x7fff,0x8000,fr10 + set_fr_iimmed 0x8000,0x7fff,fr11 + mabshs.p fr10,fr12 + mabshs fr11,fr13 + test_fr_limmed 0x7fff,0x7fff,fr12 + test_fr_limmed 0x7fff,0x7fff,fr13 + test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set + test_spr_bits 0x3c,2,0x8,msr1 ; msr1.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 2,1,1,msr1 ; msr1.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + pass diff --git a/sim/testsuite/sim/frv/maddhss.cgs b/sim/testsuite/sim/frv/maddhss.cgs new file mode 100644 index 0000000..289ecc77 --- /dev/null +++ b/sim/testsuite/sim/frv/maddhss.cgs @@ -0,0 +1,100 @@ +# frv testcase for maddhss $FRi,$FRj,$FRj +# mach: frv fr500 fr400 + + .include "testutils.inc" + + start + + .global maddhss +maddhss: + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + maddhss fr10,fr11,fr12 + test_fr_limmed 0x0000,0x0000,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + maddhss fr10,fr11,fr12 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + maddhss fr10,fr11,fr12 + test_fr_limmed 0xbeef,0xdead,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + maddhss fr10,fr11,fr12 + test_fr_limmed 0x2345,0x6789,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + maddhss fr10,fr11,fr12 + test_fr_limmed 0x1233,0x5677,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + maddhss fr10,fr11,fr12 + test_fr_limmed 0x7fff,0x7fff,fr12 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xffff,0xfffe,fr11 + maddhss fr10,fr11,fr12 + test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set + test_fr_limmed 0x8000,0x8000,fr12 + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + maddhss fr10,fr11,fr12 + test_fr_limmed 0x8000,0x8000,fr12 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + maddhss.p fr10,fr10,fr12 + maddhss fr11,fr11,fr13 + test_fr_limmed 0x0002,0x0002,fr12 + test_fr_limmed 0x7fff,0x7fff,fr13 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie not set + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 0x3c,2,0xc,msr1 ; msr1.sie is set + test_spr_bits 2,1,1,msr1 ; msr1.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + pass diff --git a/sim/testsuite/sim/frv/maddhus.cgs b/sim/testsuite/sim/frv/maddhus.cgs new file mode 100644 index 0000000..fe96e69 --- /dev/null +++ b/sim/testsuite/sim/frv/maddhus.cgs @@ -0,0 +1,89 @@ +# frv testcase for maddhus $FRi,$FRj,$FRj +# mach: frv fr500 fr400 + + .include "testutils.inc" + + start + + .global maddhus +maddhus: + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + maddhus fr10,fr11,fr12 + test_fr_limmed 0x0000,0x0000,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + maddhus fr10,fr11,fr12 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + maddhus fr10,fr11,fr12 + test_fr_limmed 0xbeef,0xdead,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + maddhus fr10,fr11,fr12 + test_fr_limmed 0x2345,0x6789,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + maddhus fr10,fr11,fr12 + test_fr_limmed 0x8000,0x7fff,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xfffe,0xfffe,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + maddhus fr10,fr11,fr12 + test_fr_limmed 0xffff,0xffff,fr12 + test_spr_bits 0x3c,2,4,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0002,0x0001,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + maddhus fr10,fr11,fr12 + test_fr_limmed 0xffff,0xffff,fr12 + test_spr_bits 0x3c,2,8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + maddhus.p fr10,fr10,fr12 + maddhus fr11,fr11,fr13 + test_fr_limmed 0x0002,0x0002,fr12 + test_fr_limmed 0xffff,0xffff,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 0x3c,2,0xc,msr1 ; msr1.sie is set + test_spr_bits 2,1,1,msr1 ; msr1.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + pass diff --git a/sim/testsuite/sim/frv/mand.cgs b/sim/testsuite/sim/frv/mand.cgs new file mode 100644 index 0000000..c6aa993 --- /dev/null +++ b/sim/testsuite/sim/frv/mand.cgs @@ -0,0 +1,23 @@ +# frv testcase for mand $FRinti,$FRintj,$FRintk +# mach: all + + .include "testutils.inc" + + start + + .global mand +mand: + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + set_fr_iimmed 0x5555,0x5555,fr8 + mand fr7,fr8,fr8 + test_fr_iimmed 0,fr8 + + set_fr_iimmed 0xffff,0x0000,fr8 + mand fr7,fr8,fr8 + test_fr_iimmed 0xaaaa0000,fr8 + + set_fr_iimmed 0x0000,0xffff,fr8 + mand fr7,fr8,fr8 + test_fr_iimmed 0x0000aaaa,fr8 + + pass diff --git a/sim/testsuite/sim/frv/maveh.cgs b/sim/testsuite/sim/frv/maveh.cgs new file mode 100644 index 0000000..d48ad72 --- /dev/null +++ b/sim/testsuite/sim/frv/maveh.cgs @@ -0,0 +1,72 @@ +# frv testcase for maveh $FRi,$FRj,$FRj +# mach: all + + .include "testutils.inc" + + start + + .global maveh +maveh: + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x0000,0x0000,fr12 + + set_fr_iimmed 0x0001,0x0000,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x0001,0x0000,fr12 + + set_fr_iimmed 0x0000,0xffff,fr10 + set_fr_iimmed 0xffff,0xfffe,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0xffff,0xfffe,fr12 + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0xef56,0xdf77,fr12 + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0xdf77,0xef56,fr12 + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x11a2,0x33c4,fr12 + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x0919,0x2b3b,fr12 + + set_spr_immed 0,msr0 + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0x4000,0x3fff,fr12 + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xffff,0xfffe,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0xc000,0xbfff,fr12 + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0xfffe,0xfffe,fr11 + maveh fr10,fr11,fr12 + test_fr_limmed 0xbfff,0xbfff,fr12 + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x8000,0x8000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + maveh.p fr10,fr10,fr12 + maveh fr11,fr11,fr13 + test_fr_limmed 0x8000,0x8000,fr12 + test_fr_limmed 0x7fff,0x7fff,fr13 + + pass diff --git a/sim/testsuite/sim/frv/mbtoh.cgs b/sim/testsuite/sim/frv/mbtoh.cgs new file mode 100644 index 0000000..52895ad --- /dev/null +++ b/sim/testsuite/sim/frv/mbtoh.cgs @@ -0,0 +1,20 @@ +# frv testcase for mbtoh $FRj,$FRk +# mach: all + + .include "testutils.inc" + + start + + .global mbtoh +mbtoh: + set_fr_iimmed 0xdead,0xbeef,fr10 + mbtoh fr10,fr12 + test_fr_limmed 0x00de,0x00ad,fr12 + test_fr_limmed 0x00be,0x00ef,fr13 + + set_fr_iimmed 0x1234,0x5678,fr10 + mbtoh fr10,fr12 + test_fr_limmed 0x0012,0x0034,fr12 + test_fr_limmed 0x0056,0x0078,fr13 + + pass diff --git a/sim/testsuite/sim/frv/mbtohe.cgs b/sim/testsuite/sim/frv/mbtohe.cgs new file mode 100644 index 0000000..1e978ec --- /dev/null +++ b/sim/testsuite/sim/frv/mbtohe.cgs @@ -0,0 +1,24 @@ +# frv testcase for mbtohe $FRj,$FRk +# mach: frv + + .include "testutils.inc" + + start + + .global mbtohe +mbtohe: + set_fr_iimmed 0xdead,0xbeef,fr10 + mbtohe fr10,fr12 + test_fr_limmed 0x00de,0x00de,fr12 + test_fr_limmed 0x00ad,0x00ad,fr13 + test_fr_limmed 0x00be,0x00be,fr14 + test_fr_limmed 0x00ef,0x00ef,fr15 + + set_fr_iimmed 0x1234,0x5678,fr10 + mbtohe fr10,fr12 + test_fr_limmed 0x0012,0x0012,fr12 + test_fr_limmed 0x0034,0x0034,fr13 + test_fr_limmed 0x0056,0x0056,fr14 + test_fr_limmed 0x0078,0x0078,fr15 + + pass diff --git a/sim/testsuite/sim/frv/mclracc.cgs b/sim/testsuite/sim/frv/mclracc.cgs new file mode 100644 index 0000000..7972b9a --- /dev/null +++ b/sim/testsuite/sim/frv/mclracc.cgs @@ -0,0 +1,79 @@ +# frv testcase for mclracc $ACC40k,$A +# mach: frv + + .include "testutils.inc" + + start + + .global mclracc +mclracc: + set_accg_immed 0xff,accg0 + set_acc_immed -1,acc0 + set_accg_immed 0xff,accg8 + set_acc_immed -1,acc8 + set_accg_immed 0xff,accg31 + set_acc_immed -1,acc31 + set_accg_immed 0xff,accg62 + set_acc_immed -1,acc62 + + mclracc acc63,0 ; nop + test_accg_immed 0xff,accg0 + test_acc_immed -1,acc0 + test_accg_immed 0xff,accg8 + test_acc_immed -1,acc8 + test_accg_immed 0xff,accg31 + test_acc_immed -1,acc31 + test_accg_immed 0xff,accg62 + test_acc_immed -1,acc62 + + mclracc acc63,1 ; nop + test_accg_immed 0xff,accg0 + test_acc_immed -1,acc0 + test_accg_immed 0xff,accg8 + test_acc_immed -1,acc8 + test_accg_immed 0xff,accg31 + test_acc_immed -1,acc31 + test_accg_immed 0xff,accg62 + test_acc_immed -1,acc62 + + mclracc acc31,0 + test_accg_immed 0xff,accg0 + test_acc_immed -1,acc0 + test_accg_immed 0xff,accg8 + test_acc_immed -1,acc8 + test_accg_immed 0,accg31 + test_acc_immed 0,acc31 + test_accg_immed 0xff,accg62 + test_acc_immed -1,acc62 + + mclracc acc62,1 + test_accg_immed 0xff,accg0 + test_acc_immed -1,acc0 + test_accg_immed 0xff,accg8 + test_acc_immed -1,acc8 + test_accg_immed 0,accg31 + test_acc_immed 0,acc31 + test_accg_immed 0,accg62 + test_acc_immed 0,acc62 + + mclracc acc0,0 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0xff,accg8 + test_acc_immed -1,acc8 + test_accg_immed 0,accg31 + test_acc_immed 0,acc31 + test_accg_immed 0,accg62 + test_acc_immed 0,acc62 + + mclracc acc0,1 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg8 + test_acc_immed 0,acc8 + test_accg_immed 0,accg31 + test_acc_immed 0,acc31 + test_accg_immed 0,accg62 + test_acc_immed 0,acc62 + + pass diff --git a/sim/testsuite/sim/frv/mcmpsh.cgs b/sim/testsuite/sim/frv/mcmpsh.cgs new file mode 100644 index 0000000..50e986d --- /dev/null +++ b/sim/testsuite/sim/frv/mcmpsh.cgs @@ -0,0 +1,138 @@ +# frv testcase for mcmpsh $FRi,$FRj,$FCCk +# mach: all + + .include "testutils.inc" + + start + + .global mcmpsh +mcmpsh: + set_fr_iimmed 0x7fff,0x7fff,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + mcmpsh fr10,fr11,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + + set_fr_iimmed 0x7fff,0x7fff,fr10 + set_fr_iimmed 0x7fff,0x8000,fr11 + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + mcmpsh fr10,fr11,fcc0 + test_fcc 0x8,0 + test_fcc 0x2,1 + + set_fr_iimmed 0x7fff,0x7fff,fr10 + set_fr_iimmed 0x8000,0x7fff,fr11 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + mcmpsh fr10,fr11,fcc0 + test_fcc 0x2,0 + test_fcc 0x8,1 + + set_fr_iimmed 0x7fff,0x7fff,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + mcmpsh fr10,fr11,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + + set_fr_iimmed 0x7fff,0x8000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + mcmpsh fr10,fr11,fcc0 + test_fcc 0x8,0 + test_fcc 0x4,1 + + set_fr_iimmed 0x7fff,0x8000,fr10 + set_fr_iimmed 0x7fff,0x8000,fr11 + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + mcmpsh fr10,fr11,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + + set_fr_iimmed 0x7fff,0x8000,fr10 + set_fr_iimmed 0x8000,0x7fff,fr11 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + mcmpsh fr10,fr11,fcc0 + test_fcc 0x2,0 + test_fcc 0x4,1 + + set_fr_iimmed 0x7fff,0x8000,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + mcmpsh fr10,fr11,fcc0 + test_fcc 0x2,0 + test_fcc 0x8,1 + + set_fr_iimmed 0x8000,0x7fff,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + mcmpsh fr10,fr11,fcc0 + test_fcc 0x4,0 + test_fcc 0x8,1 + + set_fr_iimmed 0x8000,0x7fff,fr10 + set_fr_iimmed 0x7fff,0x8000,fr11 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + mcmpsh fr10,fr11,fcc0 + test_fcc 0x4,0 + test_fcc 0x2,1 + + set_fr_iimmed 0x8000,0x7fff,fr10 + set_fr_iimmed 0x8000,0x7fff,fr11 + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + mcmpsh fr10,fr11,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + + set_fr_iimmed 0x8000,0x7fff,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + mcmpsh fr10,fr11,fcc0 + test_fcc 0x8,0 + test_fcc 0x2,1 + + set_fr_iimmed 0x8000,0x8000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + mcmpsh fr10,fr11,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + + set_fr_iimmed 0x8000,0x8000,fr10 + set_fr_iimmed 0x7fff,0x8000,fr11 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + mcmpsh fr10,fr11,fcc0 + test_fcc 0x4,0 + test_fcc 0x8,1 + + set_fr_iimmed 0x8000,0x8000,fr10 + set_fr_iimmed 0x8000,0x7fff,fr11 + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + mcmpsh fr10,fr11,fcc0 + test_fcc 0x8,0 + test_fcc 0x4,1 + + set_fr_iimmed 0x8000,0x8000,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + mcmpsh fr10,fr11,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + + pass diff --git a/sim/testsuite/sim/frv/mcmpuh.cgs b/sim/testsuite/sim/frv/mcmpuh.cgs new file mode 100644 index 0000000..a6670b7 --- /dev/null +++ b/sim/testsuite/sim/frv/mcmpuh.cgs @@ -0,0 +1,138 @@ +# frv testcase for mcmpuh $FRi,$FRj,$FCCk +# mach: all + + .include "testutils.inc" + + start + + .global mcmpuh +mcmpuh: + set_fr_iimmed 0x7fff,0x7fff,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + mcmpuh fr10,fr11,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + + set_fr_iimmed 0x7fff,0x7fff,fr10 + set_fr_iimmed 0x7fff,0x8000,fr11 + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + mcmpuh fr10,fr11,fcc0 + test_fcc 0x8,0 + test_fcc 0x4,1 + + set_fr_iimmed 0x7fff,0x7fff,fr10 + set_fr_iimmed 0x8000,0x7fff,fr11 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + mcmpuh fr10,fr11,fcc0 + test_fcc 0x4,0 + test_fcc 0x8,1 + + set_fr_iimmed 0x7fff,0x7fff,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + mcmpuh fr10,fr11,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + + set_fr_iimmed 0x7fff,0x8000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + mcmpuh fr10,fr11,fcc0 + test_fcc 0x8,0 + test_fcc 0x2,1 + + set_fr_iimmed 0x7fff,0x8000,fr10 + set_fr_iimmed 0x7fff,0x8000,fr11 + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + mcmpuh fr10,fr11,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + + set_fr_iimmed 0x7fff,0x8000,fr10 + set_fr_iimmed 0x8000,0x7fff,fr11 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + mcmpuh fr10,fr11,fcc0 + test_fcc 0x4,0 + test_fcc 0x2,1 + + set_fr_iimmed 0x7fff,0x8000,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + mcmpuh fr10,fr11,fcc0 + test_fcc 0x4,0 + test_fcc 0x8,1 + + set_fr_iimmed 0x8000,0x7fff,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + mcmpuh fr10,fr11,fcc0 + test_fcc 0x2,0 + test_fcc 0x8,1 + + set_fr_iimmed 0x8000,0x7fff,fr10 + set_fr_iimmed 0x7fff,0x8000,fr11 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + mcmpuh fr10,fr11,fcc0 + test_fcc 0x2,0 + test_fcc 0x4,1 + + set_fr_iimmed 0x8000,0x7fff,fr10 + set_fr_iimmed 0x8000,0x7fff,fr11 + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + mcmpuh fr10,fr11,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + + set_fr_iimmed 0x8000,0x7fff,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + mcmpuh fr10,fr11,fcc0 + test_fcc 0x8,0 + test_fcc 0x4,1 + + set_fr_iimmed 0x8000,0x8000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + mcmpuh fr10,fr11,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + + set_fr_iimmed 0x8000,0x8000,fr10 + set_fr_iimmed 0x7fff,0x8000,fr11 + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + mcmpuh fr10,fr11,fcc0 + test_fcc 0x2,0 + test_fcc 0x8,1 + + set_fr_iimmed 0x8000,0x8000,fr10 + set_fr_iimmed 0x8000,0x7fff,fr11 + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + mcmpuh fr10,fr11,fcc0 + test_fcc 0x8,0 + test_fcc 0x2,1 + + set_fr_iimmed 0x8000,0x8000,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + mcmpuh fr10,fr11,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + + pass diff --git a/sim/testsuite/sim/frv/mcop1.cgs b/sim/testsuite/sim/frv/mcop1.cgs new file mode 100644 index 0000000..5405456 --- /dev/null +++ b/sim/testsuite/sim/frv/mcop1.cgs @@ -0,0 +1,40 @@ +# frv testcase for mcop1 $FRi,$FRj,$FRk +# mach: frv + + .include "testutils.inc" + + start + + .global mcop1 +mcop1: + mcop1.p fr19,fr12,fr13 ; mp_exception: not-implemented + mcop1 fr20,fr14,fr18 ; mp_exception: not-implemented + test_spr_bits 0x7000,12,5,msr0; msr0.mtt is set + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear + + mcop1.p fr19,fr12,fr13 ; mp_exception: not-implemented + mcop1 fr20,fr14,fr18 ; mp_exception: not-implemented + test_spr_bits 0x7000,12,5,msr0; msr0.mtt is set + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear + + mcop1 fr19,fr12,fr13 ; mp_exception: not-implemented + test_spr_bits 0x7000,12,5,msr0; msr0.mtt is set + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear + + mcop1 fr19,fr12,fr13 ; mp_exception: not-implemented + test_spr_bits 0x7000,12,5,msr0; msr0.mtt is set + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear + + pass diff --git a/sim/testsuite/sim/frv/mcop2.cgs b/sim/testsuite/sim/frv/mcop2.cgs new file mode 100644 index 0000000..f423a3e --- /dev/null +++ b/sim/testsuite/sim/frv/mcop2.cgs @@ -0,0 +1,40 @@ +# frv testcase for mcop2 $FRi,$FRj,$FRk +# mach: frv + + .include "testutils.inc" + + start + + .global mcop2 +mcop2: + mcop2.p fr19,fr12,fr13 ; mp_exception: not-implemented + mcop2 fr20,fr14,fr18 ; mp_exception: not-implemented + test_spr_bits 0x7000,12,5,msr0; msr0.mtt is set + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear + + mcop2.p fr19,fr12,fr13 ; mp_exception: not-implemented + mcop2 fr20,fr14,fr18 ; mp_exception: not-implemented + test_spr_bits 0x7000,12,5,msr0; msr0.mtt is set + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear + + mcop2 fr19,fr12,fr13 ; mp_exception: not-implemented + test_spr_bits 0x7000,12,5,msr0; msr0.mtt is set + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear + + mcop2 fr19,fr12,fr13 ; mp_exception: not-implemented + test_spr_bits 0x7000,12,5,msr0; msr0.mtt is set + test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear + test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear + test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear + + pass diff --git a/sim/testsuite/sim/frv/mcplhi.cgs b/sim/testsuite/sim/frv/mcplhi.cgs new file mode 100644 index 0000000..d1a52eb --- /dev/null +++ b/sim/testsuite/sim/frv/mcplhi.cgs @@ -0,0 +1,53 @@ +# frv testcase for mcplhi $FRi,$s6,$FRk +# mach: fr400 fr550 + + .include "testutils.inc" + + start + + .global mcplhi +mcplhi: + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_fr_iimmed 0x1234,0x5678,fr10 + mcplhi fr8,0x0,fr10 ; Shift by 0 + test_fr_iimmed 0xdead5678,fr10 + + set_fr_iimmed 0x1234,0x5678,fr10 + mcplhi fr8,0x1,fr10 ; Shift by 1 + test_fr_iimmed 0xbd5b5678,fr10 + + set_fr_iimmed 0x1234,0x5678,fr10 + mcplhi fr8,0x4,fr10 ; Shift by 4 + test_fr_iimmed 0xeadf5678,fr10 + + set_fr_iimmed 0x1234,0x5678,fr10 + mcplhi fr8,0xc,fr10 ; Shift by 12 + test_fr_iimmed 0xdeef5678,fr10 + + set_fr_iimmed 0x1234,0x5678,fr10 + mcplhi fr8,0xf,fr10 ; Shift by 15 + test_fr_iimmed 0xbeef5678,fr10 + + ; test again with truncated shift values + set_fr_iimmed 0x1234,0x5678,fr10 + mcplhi fr8,0x10,fr10 ; Shift by 0 + test_fr_iimmed 0xdead5678,fr10 + + set_fr_iimmed 0x1234,0x5678,fr10 + mcplhi fr8,0x21,fr10 ; Shift by 1 + test_fr_iimmed 0xbd5b5678,fr10 + + set_fr_iimmed 0x1234,0x5678,fr10 + mcplhi fr8,0x34,fr10 ; Shift by 4 + test_fr_iimmed 0xeadf5678,fr10 + + set_fr_iimmed 0x1234,0x5678,fr10 + mcplhi fr8,0x1c,fr10 ; Shift by 12 + test_fr_iimmed 0xdeef5678,fr10 + + set_fr_iimmed 0x1234,0x5678,fr10 + mcplhi fr8,0x2f,fr10 ; Shift by 15 + test_fr_iimmed 0xbeef5678,fr10 + + pass diff --git a/sim/testsuite/sim/frv/mcpli.cgs b/sim/testsuite/sim/frv/mcpli.cgs new file mode 100644 index 0000000..b63ec67 --- /dev/null +++ b/sim/testsuite/sim/frv/mcpli.cgs @@ -0,0 +1,61 @@ +# frv testcase for mcpli $FRi,$s6,$FRk +# mach: fr400 fr550 + + .include "testutils.inc" + + start + + .global mcpli +mcpli: + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_fr_iimmed 0x1234,0x5678,fr10 + mcpli fr8,0x0,fr10 ; Shift by 0 + test_fr_iimmed 0xdeadbeef,fr10 + + set_fr_iimmed 0x1234,0x5678,fr10 + mcpli fr8,0x1,fr10 ; Shift by 1 + test_fr_iimmed 0xbd5b7ddf,fr10 + + set_fr_iimmed 0x1234,0x5678,fr10 + mcpli fr8,0x4,fr10 ; Shift by 4 + test_fr_iimmed 0xeadbeefd,fr10 + + set_fr_iimmed 0x1234,0x5678,fr10 + mcpli fr8,0xc,fr10 ; Shift by 12 + test_fr_iimmed 0xdbeefead,fr10 + + set_fr_iimmed 0x1234,0x5678,fr10 + mcpli fr8,0x1c,fr10 ; Shift by 28 + test_fr_iimmed 0xfeefdead,fr10 + + set_fr_iimmed 0x1234,0x5678,fr10 + mcpli fr8,0x1f,fr10 ; Shift by 31 + test_fr_iimmed 0xbeefdead,fr10 + + ; test again with truncated shift values + set_fr_iimmed 0x1234,0x5678,fr10 + mcpli fr8,0x20,fr10 ; Shift by 0 + test_fr_iimmed 0xdeadbeef,fr10 + + set_fr_iimmed 0x1234,0x5678,fr10 + mcpli fr8,0x21,fr10 ; Shift by 1 + test_fr_iimmed 0xbd5b7ddf,fr10 + + set_fr_iimmed 0x1234,0x5678,fr10 + mcpli fr8,0x24,fr10 ; Shift by 4 + test_fr_iimmed 0xeadbeefd,fr10 + + set_fr_iimmed 0x1234,0x5678,fr10 + mcpli fr8,0x2c,fr10 ; Shift by 12 + test_fr_iimmed 0xdbeefead,fr10 + + set_fr_iimmed 0x1234,0x5678,fr10 + mcpli fr8,0x3c,fr10 ; Shift by 28 + test_fr_iimmed 0xfeefdead,fr10 + + set_fr_iimmed 0x1234,0x5678,fr10 + mcpli fr8,0x3f,fr10 ; Shift by 31 + test_fr_iimmed 0xbeefdead,fr10 + + pass diff --git a/sim/testsuite/sim/frv/mcpxis.cgs b/sim/testsuite/sim/frv/mcpxis.cgs new file mode 100644 index 0000000..c3dad01 --- /dev/null +++ b/sim/testsuite/sim/frv/mcpxis.cgs @@ -0,0 +1,115 @@ +# frv testcase for mcpxis $GRi,$GRj,$ACCk +# mach: all + + .include "testutils.inc" + + start + + .global mcpxis +mcpxis: + ; Positive operands + set_fr_iimmed 2,4,fr7 ; multiply small numbers + set_fr_iimmed 5,3,fr8 + mcpxis fr7,fr8,acc0 + test_accg_immed 0x00,accg0 + test_acc_immed 26,acc0 + + set_fr_iimmed 3,1,fr7 ; multiply by 0 + set_fr_iimmed 0,2,fr8 + mcpxis fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,1,fr8 + mcpxis fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 3,acc0 + + set_fr_iimmed 0x3ff8,2,fr7 ; 15 bit result + set_fr_iimmed 0x0007,2,fr8 + mcpxis fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0,0x7ffe,acc0 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 0x2000,2,fr8 + mcpxis fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0xc000,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + mcpxis fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0x0001,acc0 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 1,0xfffd,fr8 + mcpxis fr7,fr8,acc0 + test_accg_immed 0xff,accg0 + test_acc_immed -9,acc0 + + set_fr_iimmed 0xfffe,2,fr7 ; multiply by 1 + set_fr_iimmed 0xfffe,1,fr8 + mcpxis fr7,fr8,acc0 + test_accg_immed 0xff,accg0 + test_acc_immed -6,acc0 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 0xfffe,1,fr8 + mcpxis fr7,fr8,acc0 + test_accg_immed 0xff,accg0 + test_acc_immed -2,acc0 + + set_fr_iimmed 0x2001,0xffff,fr7 ; 15 bit result + set_fr_iimmed 0xffff,0xfffe,fr8 + mcpxis fr7,fr8,acc0 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xbfff,acc0 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0x0003,0xfffe,fr8 + mcpxis fr7,fr8,acc0 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0x7ffa,acc0 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max negative result + set_fr_iimmed 0x8000,0x8000,fr8 + mcpxis fr7,fr8,acc0 + test_accg_immed 0xff,accg0 + test_acc_limmed 0x8001,0x0000,acc0 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + mcpxis fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0x8000,0x0000,acc0 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffc,fr7 ; multiply small numbers + set_fr_iimmed 0xfffb,0xfffd,fr8 + mcpxis fr7,fr8,acc0 + test_accg_immed 0x00,accg0 + test_acc_immed 26,acc0 + + set_fr_iimmed 0xffff,0xffff,fr7 ; multiply by -1 + set_fr_iimmed 0xffff,0xfffe,fr8 + mcpxis fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 3,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; almost max positive result + set_fr_iimmed 0x8001,0x7fff,fr8 + mcpxis fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + + set_fr_iimmed 0x8000,0x0000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + mcpxis fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0x40000000,acc0 + + pass diff --git a/sim/testsuite/sim/frv/mcpxiu.cgs b/sim/testsuite/sim/frv/mcpxiu.cgs new file mode 100644 index 0000000..198f056 --- /dev/null +++ b/sim/testsuite/sim/frv/mcpxiu.cgs @@ -0,0 +1,76 @@ +# frv testcase for mcpxiu $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global mcpxiu +mcpxiu: + set_fr_iimmed 4,2,fr7 ; multiply small numbers + set_fr_iimmed 3,5,fr8 + mcpxiu fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 26,acc0 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 1,3,fr8 + mcpxiu fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 5,acc0 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 0,2,fr8 + mcpxiu fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + + set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result + set_fr_iimmed 0x0001,2,fr8 + mcpxiu fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x7fff,acc0 + + set_fr_iimmed 0x4000,1,fr7 ; 16 bit result + set_fr_iimmed 0x0001,2,fr8 + mcpxiu fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8001,acc0 + + set_fr_iimmed 0x4000,1,fr7 ; 17 bit result + set_fr_iimmed 0x0001,4,fr8 + mcpxiu fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0x00010001,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + mcpxiu fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x0000,0x8000,fr8 + mcpxiu fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0x4000,0x0000,acc0 + + set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + mcpxiu fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0xfffe,0x0001,acc0 + + set_fr_iimmed 0xfffe,0xffff,fr7 ; almost max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + mcpxiu fr7,fr8,acc0 + test_accg_immed 1,accg0 + test_acc_immed 0xfffb0003,acc0 + + set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + mcpxiu fr7,fr8,acc0 + test_accg_immed 1,accg0 + test_acc_immed 0xfffc0002,acc0 + + pass diff --git a/sim/testsuite/sim/frv/mcpxrs.cgs b/sim/testsuite/sim/frv/mcpxrs.cgs new file mode 100644 index 0000000..1d62a96 --- /dev/null +++ b/sim/testsuite/sim/frv/mcpxrs.cgs @@ -0,0 +1,115 @@ +# frv testcase for mcpxrs $GRi,$GRj,$ACCk +# mach: all + + .include "testutils.inc" + + start + + .global mcpxrs +mcpxrs: + ; Positive operands + set_fr_iimmed 2,4,fr7 ; multiply small numbers + set_fr_iimmed 3,5,fr8 + mcpxrs fr7,fr8,acc0 + test_accg_immed 0xff,accg0 + test_acc_immed -14,acc0 + + set_fr_iimmed 3,1,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + mcpxrs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,1,fr8 + mcpxrs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 1,acc0 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x0007,fr8 + mcpxrs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0,0x7ff0,acc0 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x2000,fr8 + mcpxrs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x4000,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + mcpxrs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0x0001,acc0 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,1,fr8 + mcpxrs fr7,fr8,acc0 + test_accg_immed 0xff,accg0 + test_acc_immed -3,acc0 + + set_fr_iimmed 0xfffe,2,fr7 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr8 + mcpxrs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 2,acc0 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 1,0xfffe,fr8 + mcpxrs fr7,fr8,acc0 + test_accg_immed 0xff,accg0 + test_acc_immed -2,acc0 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfffe,0xfff9,fr8 + mcpxrs fr7,fr8,acc0 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xbff0,acc0 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0xfffe,0x0003,fr8 + mcpxrs fr7,fr8,acc0 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0x8006,acc0 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x8000,fr8 + mcpxrs fr7,fr8,acc0 + test_accg_immed 0xff,accg0 + test_acc_limmed 0x8000,0x8000,acc0 + + set_fr_iimmed 0x8000,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + mcpxrs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0x7fff,0x8000,acc0 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffc,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffb,fr8 + mcpxrs fr7,fr8,acc0 + test_accg_immed 0xff,accg0 + test_acc_immed -14,acc0 + + set_fr_iimmed 0xffff,0xffff,fr7 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr8 + mcpxrs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 1,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; almost max positive result + set_fr_iimmed 0x7fff,0x8001,fr8 + mcpxrs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + + set_fr_iimmed 0x8000,0x0000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + mcpxrs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0x40000000,acc0 + + pass diff --git a/sim/testsuite/sim/frv/mcpxru.cgs b/sim/testsuite/sim/frv/mcpxru.cgs new file mode 100644 index 0000000..8a54392 --- /dev/null +++ b/sim/testsuite/sim/frv/mcpxru.cgs @@ -0,0 +1,94 @@ +# frv testcase for mcpxru $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global mcpxru +mcpxru: + set_fr_iimmed 4,2,fr7 ; multiply small numbers + set_fr_iimmed 5,3,fr8 + mcpxru fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 14,acc0 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 3,1,fr8 + mcpxru fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 1,acc0 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + mcpxru fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + + set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result + set_fr_iimmed 2,0x0001,fr8 + mcpxru fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x7ffd,acc0 + + set_fr_iimmed 0x4000,1,fr7 ; 16 bit result + set_fr_iimmed 4,0x0001,fr8 + mcpxru fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0xffff,acc0 + + set_fr_iimmed 0x8000,1,fr7 ; 17 bit result + set_fr_iimmed 4,0x0001,fr8 + mcpxru fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0x0001ffff,acc0 + + set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + mcpxru fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x0000,fr8 + mcpxru fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0x4000,0x0000,acc0 + + set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + mcpxru fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0xfffe,0x0001,acc0 + + set_fr_iimmed 0x0000,0x0001,fr7 ; saturation + set_fr_iimmed 0xffff,0x0001,fr8 + mcpxru fr7,fr8,acc0 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + + set_fr_iimmed 0x0000,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + mcpxru fr7,fr8,acc0 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + + set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation + set_fr_iimmed 0xffff,0xffff,fr8 + mcpxru fr7,fr8,acc0 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + + pass diff --git a/sim/testsuite/sim/frv/mcut.cgs b/sim/testsuite/sim/frv/mcut.cgs new file mode 100644 index 0000000..d6211ab --- /dev/null +++ b/sim/testsuite/sim/frv/mcut.cgs @@ -0,0 +1,509 @@ +# frv testcase for mcut $ACC40i,$FRj,$FRk +# mach: all + + .include "testutils.inc" + + start + + .global mcut +mcut: + set_accg_immed 0xffffffe7,accg0 + set_acc_immed 0x89abcdef,acc0 + + set_fr_iimmed 0,0,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xe789abcd,fr11 + + set_fr_iimmed 0,1,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xcf13579b,fr11 + + set_fr_iimmed 0,2,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x9e26af37,fr11 + + set_fr_iimmed 0,3,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x3c4d5e6f,fr11 + + set_fr_iimmed 0,4,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x789abcde,fr11 + + set_fr_iimmed 0,5,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xf13579bd,fr11 + + set_fr_iimmed 0,6,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xe26af37b,fr11 + + set_fr_iimmed 0,7,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xc4d5e6f7,fr11 + + set_fr_iimmed 0,8,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x89abcdef,fr11 + + set_fr_iimmed 0,9,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x13579bde,fr11 + + set_fr_iimmed 0,10,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x26af37bc,fr11 + + set_fr_iimmed 0,11,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x4d5e6f78,fr11 + + set_fr_iimmed 0,12,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x9abcdef0,fr11 + + set_fr_iimmed 0,13,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x3579bde0,fr11 + + set_fr_iimmed 0,14,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x6af37bc0,fr11 + + set_fr_iimmed 0,15,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xd5e6f780,fr11 + + set_fr_iimmed 0,16,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xabcdef00,fr11 + + set_fr_iimmed 0,17,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x579bde00,fr11 + + set_fr_iimmed 0,18,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xaf37bc00,fr11 + + set_fr_iimmed 0,19,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x5e6f7800,fr11 + + set_fr_iimmed 0,20,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xbcdef000,fr11 + + set_fr_iimmed 0,21,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x79bde000,fr11 + + set_fr_iimmed 0,22,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xf37bc000,fr11 + + set_fr_iimmed 0,23,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xe6f78000,fr11 + + set_fr_iimmed 0,24,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xcdef0000,fr11 + + set_fr_iimmed 0,25,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x9bde0000,fr11 + + set_fr_iimmed 0,26,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x37bc0000,fr11 + + set_fr_iimmed 0,27,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x6f780000,fr11 + + set_fr_iimmed 0,28,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xdef00000,fr11 + + set_fr_iimmed 0,29,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xbde00000,fr11 + + set_fr_iimmed 0,30,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x7bc00000,fr11 + + set_fr_iimmed 0,31,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xf7800000,fr11 + + set_fr_iimmed 0,31,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xf7800000,fr11 + + set_fr_iimmed 0,64,fr10 ; same as 0 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xe789abcd,fr11 + + set_fr_iimmed 0xffff,0xffff,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xf3c4d5e6,fr11 + + set_fr_iimmed 0x0000,0x003e,fr10 ; only lower 6 bits matter + mcut acc0,fr10,fr11 + test_fr_iimmed 0xf9e26af3,fr11 + + set_fr_iimmed 0xffff,0xfffd,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xfcf13579,fr11 + + set_fr_iimmed 0xffff,0xfffc,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xfe789abc,fr11 + + set_fr_iimmed 0xffff,0xfffb,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xff3c4d5e,fr11 + + set_fr_iimmed 0xffff,0xfffa,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xff9e26af,fr11 + + set_fr_iimmed 0xffff,0xfff9,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xffcf1357,fr11 + + set_fr_iimmed 0xffff,0xfff8,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xffe789ab,fr11 + + set_fr_iimmed 0xffff,0xfff7,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xfff3c4d5,fr11 + + set_fr_iimmed 0xffff,0xfff6,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xfff9e26a,fr11 + + set_fr_iimmed 0xffff,0xfff5,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xfffcf135,fr11 + + set_fr_iimmed 0xffff,0xfff4,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xfffe789a,fr11 + + set_fr_iimmed 0xffff,0xfff3,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xffff3c4d,fr11 + + set_fr_iimmed 0xffff,0xfff2,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xffff9e26,fr11 + + set_fr_iimmed 0xffff,0xfff1,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xffffcf13,fr11 + + set_fr_iimmed 0xffff,0xfff0,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xffffe789,fr11 + + set_fr_iimmed 0xffff,0xffef,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xfffff3c4,fr11 + + set_fr_iimmed 0xffff,0xffee,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xfffff9e2,fr11 + + set_fr_iimmed 0xffff,0xffed,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xfffffcf1,fr11 + + set_fr_iimmed 0xffff,0xffec,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xfffffe78,fr11 + + set_fr_iimmed 0xffff,0xffeb,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xffffff3c,fr11 + + set_fr_iimmed 0xffff,0xffea,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xffffff9e,fr11 + + set_fr_iimmed 0xffff,0xffe9,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xffffffcf,fr11 + + set_fr_iimmed 0xffff,0xffe8,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xffffffe7,fr11 + + set_fr_iimmed 0xffff,0xffe7,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xfffffff3,fr11 + + set_fr_iimmed 0xffff,0xffe6,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xfffffff9,fr11 + + set_fr_iimmed 0xffff,0xffe5,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xfffffffc,fr11 + + set_fr_iimmed 0xffff,0xffe4,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xfffffffe,fr11 + + set_fr_iimmed 0xffff,0xffe3,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xffffffff,fr11 + + set_fr_iimmed 0xffff,0xffe2,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xffffffff,fr11 + + set_fr_iimmed 0xffff,0xffe1,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xffffffff,fr11 + + set_fr_iimmed 0xffff,0xffe0,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xffffffff,fr11 + + set_fr_iimmed 0,32,fr10 ; same as -32 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xffffffff,fr11 + + set_accg_immed 0xffffff67,accg0 + set_acc_immed 0x89abcdef,acc0 + + set_fr_iimmed 0xffff,0xffff,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x33c4d5e6,fr11 + + set_fr_iimmed 0x0000,0x003e,fr10 ; only lower 6 bits matter + mcut acc0,fr10,fr11 + test_fr_iimmed 0x19e26af3,fr11 + + set_fr_iimmed 0xffff,0xfffd,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x0cf13579,fr11 + + set_fr_iimmed 0xffff,0xfffc,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x06789abc,fr11 + + set_fr_iimmed 0xffff,0xfffb,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x033c4d5e,fr11 + + set_fr_iimmed 0xffff,0xfffa,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x019e26af,fr11 + + set_fr_iimmed 0xffff,0xfff9,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x00cf1357,fr11 + + set_fr_iimmed 0xffff,0xfff8,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x006789ab,fr11 + + set_fr_iimmed 0xffff,0xfff7,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x0033c4d5,fr11 + + set_fr_iimmed 0xffff,0xfff6,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x0019e26a,fr11 + + set_fr_iimmed 0xffff,0xfff5,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x000cf135,fr11 + + set_fr_iimmed 0xffff,0xfff4,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x0006789a,fr11 + + set_fr_iimmed 0xffff,0xfff3,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x00033c4d,fr11 + + set_fr_iimmed 0xffff,0xfff2,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x00019e26,fr11 + + set_fr_iimmed 0xffff,0xfff1,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x0000cf13,fr11 + + set_fr_iimmed 0xffff,0xfff0,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x00006789,fr11 + + set_fr_iimmed 0xffff,0xffef,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x000033c4,fr11 + + set_fr_iimmed 0xffff,0xffee,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x000019e2,fr11 + + set_fr_iimmed 0xffff,0xffed,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x00000cf1,fr11 + + set_fr_iimmed 0xffff,0xffec,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x00000678,fr11 + + set_fr_iimmed 0xffff,0xffeb,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x0000033c,fr11 + + set_fr_iimmed 0xffff,0xffea,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x0000019e,fr11 + + set_fr_iimmed 0xffff,0xffe9,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x000000cf,fr11 + + set_fr_iimmed 0xffff,0xffe8,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x00000067,fr11 + + set_fr_iimmed 0xffff,0xffe7,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x00000033,fr11 + + set_fr_iimmed 0xffff,0xffe6,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x00000019,fr11 + + set_fr_iimmed 0xffff,0xffe5,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x0000000c,fr11 + + set_fr_iimmed 0xffff,0xffe4,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x00000006,fr11 + + set_fr_iimmed 0xffff,0xffe3,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x00000003,fr11 + + set_fr_iimmed 0xffff,0xffe2,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x00000001,fr11 + + set_fr_iimmed 0xffff,0xffe1,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x00000000,fr11 + + set_fr_iimmed 0xffff,0xffe0,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x00000000,fr11 + + set_fr_iimmed 0,32,fr10 ; same as -32 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x00000000,fr11 + + ; Examples from the customer + set_accg_immed 0xffffffff,accg0 + set_acc_immed 0xffe00000,acc0 + + set_fr_iimmed 0,16,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xe0000000,fr11 + + set_fr_iimmed 0,17,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xc0000000,fr11 + + set_fr_iimmed 0,18,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_accg_immed 0,accg0 + set_acc_immed 0x003fffff,acc0 + + set_fr_iimmed 0,16,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x3fffff00,fr11 + + set_fr_iimmed 0,17,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x7ffffe00,fr11 + + set_accg_immed 0x7f,accg0 + set_acc_immed 0xffe00000,acc0 + + set_fr_iimmed 0,16,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xe0000000,fr11 + + set_fr_iimmed 0,17,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xc0000000,fr11 + + set_fr_iimmed 0,18,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_accg_immed 0x08,accg0 + set_acc_immed 0x003fffff,acc0 + + set_fr_iimmed 0,16,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x3fffff00,fr11 + + set_fr_iimmed 0,17,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x7ffffe00,fr11 + + set_accg_immed 0xff,accg0 + set_acc_immed 0xefe00000,acc0 + + set_fr_iimmed 0,16,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xe0000000,fr11 + + set_fr_iimmed 0,17,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xc0000000,fr11 + + set_fr_iimmed 0,18,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_accg_immed 0x80,accg0 + set_acc_immed 0x003fffff,acc0 + + set_fr_iimmed 0,16,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x3fffff00,fr11 + + set_fr_iimmed 0,17,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x7ffffe00,fr11 + + set_accg_immed 0xffffffaf,accg0 + set_acc_immed 0x5a5a5a5a,acc0 + + set_fr_iimmed 0xffff,0xfffc,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0xfaf5a5a5,fr11 + + set_accg_immed 0x0000002f,accg0 + set_acc_immed 0x5a5a5a5a,acc0 + + set_fr_iimmed 0xffff,0xfff9,fr10 + mcut acc0,fr10,fr11 + test_fr_iimmed 0x005eb4b4,fr11 + + pass diff --git a/sim/testsuite/sim/frv/mcuti.cgs b/sim/testsuite/sim/frv/mcuti.cgs new file mode 100644 index 0000000..e2e702f --- /dev/null +++ b/sim/testsuite/sim/frv/mcuti.cgs @@ -0,0 +1,381 @@ +# frv testcase for mcuti $ACC40i,$s6,$FRk +# mach: all + + .include "testutils.inc" + + start + + .global mcuti +mcuti: + set_accg_immed 0xffffffe7,accg0 + set_acc_immed 0x89abcdef,acc0 + + mcuti acc0,0,fr11 + test_fr_iimmed 0xe789abcd,fr11 + + mcuti acc0,1,fr11 + test_fr_iimmed 0xcf13579b,fr11 + + mcuti acc0,2,fr11 + test_fr_iimmed 0x9e26af37,fr11 + + set_fr_iimmed 0,3,fr10 + mcuti acc0,3,fr11 + test_fr_iimmed 0x3c4d5e6f,fr11 + + mcuti acc0,4,fr11 + test_fr_iimmed 0x789abcde,fr11 + + mcuti acc0,5,fr11 + test_fr_iimmed 0xf13579bd,fr11 + + mcuti acc0,6,fr11 + test_fr_iimmed 0xe26af37b,fr11 + + mcuti acc0,7,fr11 + test_fr_iimmed 0xc4d5e6f7,fr11 + + mcuti acc0,8,fr11 + test_fr_iimmed 0x89abcdef,fr11 + + mcuti acc0,9,fr11 + test_fr_iimmed 0x13579bde,fr11 + + mcuti acc0,10,fr11 + test_fr_iimmed 0x26af37bc,fr11 + + mcuti acc0,11,fr11 + test_fr_iimmed 0x4d5e6f78,fr11 + + mcuti acc0,12,fr11 + test_fr_iimmed 0x9abcdef0,fr11 + + mcuti acc0,13,fr11 + test_fr_iimmed 0x3579bde0,fr11 + + mcuti acc0,14,fr11 + test_fr_iimmed 0x6af37bc0,fr11 + + mcuti acc0,15,fr11 + test_fr_iimmed 0xd5e6f780,fr11 + + mcuti acc0,16,fr11 + test_fr_iimmed 0xabcdef00,fr11 + + mcuti acc0,17,fr11 + test_fr_iimmed 0x579bde00,fr11 + + mcuti acc0,18,fr11 + test_fr_iimmed 0xaf37bc00,fr11 + + mcuti acc0,19,fr11 + test_fr_iimmed 0x5e6f7800,fr11 + + mcuti acc0,20,fr11 + test_fr_iimmed 0xbcdef000,fr11 + + mcuti acc0,21,fr11 + test_fr_iimmed 0x79bde000,fr11 + + mcuti acc0,22,fr11 + test_fr_iimmed 0xf37bc000,fr11 + + mcuti acc0,23,fr11 + test_fr_iimmed 0xe6f78000,fr11 + + mcuti acc0,24,fr11 + test_fr_iimmed 0xcdef0000,fr11 + + mcuti acc0,25,fr11 + test_fr_iimmed 0x9bde0000,fr11 + + mcuti acc0,26,fr11 + test_fr_iimmed 0x37bc0000,fr11 + + mcuti acc0,27,fr11 + test_fr_iimmed 0x6f780000,fr11 + + mcuti acc0,28,fr11 + test_fr_iimmed 0xdef00000,fr11 + + mcuti acc0,29,fr11 + test_fr_iimmed 0xbde00000,fr11 + + mcuti acc0,30,fr11 + test_fr_iimmed 0x7bc00000,fr11 + + mcuti acc0,31,fr11 + test_fr_iimmed 0xf7800000,fr11 + + mcuti acc0,-1,fr11 + test_fr_iimmed 0xf3c4d5e6,fr11 + + mcuti acc0,-2,fr11 + test_fr_iimmed 0xf9e26af3,fr11 + + mcuti acc0,-3,fr11 + test_fr_iimmed 0xfcf13579,fr11 + + mcuti acc0,-4,fr11 + test_fr_iimmed 0xfe789abc,fr11 + + mcuti acc0,-5,fr11 + test_fr_iimmed 0xff3c4d5e,fr11 + + mcuti acc0,-6,fr11 + test_fr_iimmed 0xff9e26af,fr11 + + mcuti acc0,-7,fr11 + test_fr_iimmed 0xffcf1357,fr11 + + mcuti acc0,-8,fr11 + test_fr_iimmed 0xffe789ab,fr11 + + mcuti acc0,-9,fr11 + test_fr_iimmed 0xfff3c4d5,fr11 + + mcuti acc0,-10,fr11 + test_fr_iimmed 0xfff9e26a,fr11 + + mcuti acc0,-11,fr11 + test_fr_iimmed 0xfffcf135,fr11 + + mcuti acc0,-12,fr11 + test_fr_iimmed 0xfffe789a,fr11 + + mcuti acc0,-13,fr11 + test_fr_iimmed 0xffff3c4d,fr11 + + mcuti acc0,-14,fr11 + test_fr_iimmed 0xffff9e26,fr11 + + mcuti acc0,-15,fr11 + test_fr_iimmed 0xffffcf13,fr11 + + mcuti acc0,-16,fr11 + test_fr_iimmed 0xffffe789,fr11 + + mcuti acc0,-17,fr11 + test_fr_iimmed 0xfffff3c4,fr11 + + mcuti acc0,-18,fr11 + test_fr_iimmed 0xfffff9e2,fr11 + + mcuti acc0,-19,fr11 + test_fr_iimmed 0xfffffcf1,fr11 + + mcuti acc0,-20,fr11 + test_fr_iimmed 0xfffffe78,fr11 + + mcuti acc0,-21,fr11 + test_fr_iimmed 0xffffff3c,fr11 + + mcuti acc0,-22,fr11 + test_fr_iimmed 0xffffff9e,fr11 + + mcuti acc0,-23,fr11 + test_fr_iimmed 0xffffffcf,fr11 + + mcuti acc0,-24,fr11 + test_fr_iimmed 0xffffffe7,fr11 + + mcuti acc0,-25,fr11 + test_fr_iimmed 0xfffffff3,fr11 + + mcuti acc0,-26,fr11 + test_fr_iimmed 0xfffffff9,fr11 + + mcuti acc0,-27,fr11 + test_fr_iimmed 0xfffffffc,fr11 + + mcuti acc0,-28,fr11 + test_fr_iimmed 0xfffffffe,fr11 + + mcuti acc0,-29,fr11 + test_fr_iimmed 0xffffffff,fr11 + + mcuti acc0,-30,fr11 + test_fr_iimmed 0xffffffff,fr11 + + mcuti acc0,-31,fr11 + test_fr_iimmed 0xffffffff,fr11 + + mcuti acc0,-32,fr11 + test_fr_iimmed 0xffffffff,fr11 + + set_accg_immed 0xffffff67,accg0 + set_acc_immed 0x89abcdef,acc0 + + mcuti acc0,-1,fr11 + test_fr_iimmed 0x33c4d5e6,fr11 + + mcuti acc0,-2,fr11 + test_fr_iimmed 0x19e26af3,fr11 + + mcuti acc0,-3,fr11 + test_fr_iimmed 0x0cf13579,fr11 + + mcuti acc0,-4,fr11 + test_fr_iimmed 0x06789abc,fr11 + + mcuti acc0,-5,fr11 + test_fr_iimmed 0x033c4d5e,fr11 + + mcuti acc0,-6,fr11 + test_fr_iimmed 0x019e26af,fr11 + + mcuti acc0,-7,fr11 + test_fr_iimmed 0x00cf1357,fr11 + + mcuti acc0,-8,fr11 + test_fr_iimmed 0x006789ab,fr11 + + mcuti acc0,-9,fr11 + test_fr_iimmed 0x0033c4d5,fr11 + + mcuti acc0,-10,fr11 + test_fr_iimmed 0x0019e26a,fr11 + + mcuti acc0,-11,fr11 + test_fr_iimmed 0x000cf135,fr11 + + mcuti acc0,-12,fr11 + test_fr_iimmed 0x0006789a,fr11 + + mcuti acc0,-13,fr11 + test_fr_iimmed 0x00033c4d,fr11 + + mcuti acc0,-14,fr11 + test_fr_iimmed 0x00019e26,fr11 + + mcuti acc0,-15,fr11 + test_fr_iimmed 0x0000cf13,fr11 + + mcuti acc0,-16,fr11 + test_fr_iimmed 0x00006789,fr11 + + mcuti acc0,-17,fr11 + test_fr_iimmed 0x000033c4,fr11 + + mcuti acc0,-18,fr11 + test_fr_iimmed 0x000019e2,fr11 + + mcuti acc0,-19,fr11 + test_fr_iimmed 0x00000cf1,fr11 + + mcuti acc0,-20,fr11 + test_fr_iimmed 0x00000678,fr11 + + mcuti acc0,-21,fr11 + test_fr_iimmed 0x0000033c,fr11 + + mcuti acc0,-22,fr11 + test_fr_iimmed 0x0000019e,fr11 + + mcuti acc0,-23,fr11 + test_fr_iimmed 0x000000cf,fr11 + + mcuti acc0,-24,fr11 + test_fr_iimmed 0x00000067,fr11 + + mcuti acc0,-25,fr11 + test_fr_iimmed 0x00000033,fr11 + + mcuti acc0,-26,fr11 + test_fr_iimmed 0x00000019,fr11 + + mcuti acc0,-27,fr11 + test_fr_iimmed 0x0000000c,fr11 + + mcuti acc0,-28,fr11 + test_fr_iimmed 0x00000006,fr11 + + mcuti acc0,-29,fr11 + test_fr_iimmed 0x00000003,fr11 + + mcuti acc0,-30,fr11 + test_fr_iimmed 0x00000001,fr11 + + mcuti acc0,-31,fr11 + test_fr_iimmed 0x00000000,fr11 + + mcuti acc0,-32,fr11 + test_fr_iimmed 0x00000000,fr11 + + ; Examples from the customer + set_accg_immed 0xffffffff,accg0 + set_acc_immed 0xffe00000,acc0 + + mcuti acc0,16,fr11 + test_fr_iimmed 0xe0000000,fr11 + + mcuti acc0,17,fr11 + test_fr_iimmed 0xc0000000,fr11 + + mcuti acc0,18,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_accg_immed 0,accg0 + set_acc_immed 0x003fffff,acc0 + + mcuti acc0,16,fr11 + test_fr_iimmed 0x3fffff00,fr11 + + mcuti acc0,17,fr11 + test_fr_iimmed 0x7ffffe00,fr11 + + set_accg_immed 0x7f,accg0 + set_acc_immed 0xffe00000,acc0 + + mcuti acc0,16,fr11 + test_fr_iimmed 0xe0000000,fr11 + + mcuti acc0,17,fr11 + test_fr_iimmed 0xc0000000,fr11 + + mcuti acc0,18,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_accg_immed 0x08,accg0 + set_acc_immed 0x003fffff,acc0 + + mcuti acc0,16,fr11 + test_fr_iimmed 0x3fffff00,fr11 + + mcuti acc0,17,fr11 + test_fr_iimmed 0x7ffffe00,fr11 + + set_accg_immed 0xff,accg0 + set_acc_immed 0xefe00000,acc0 + + mcuti acc0,16,fr11 + test_fr_iimmed 0xe0000000,fr11 + + mcuti acc0,17,fr11 + test_fr_iimmed 0xc0000000,fr11 + + mcuti acc0,18,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_accg_immed 0x80,accg0 + set_acc_immed 0x003fffff,acc0 + + mcuti acc0,16,fr11 + test_fr_iimmed 0x3fffff00,fr11 + + mcuti acc0,17,fr11 + test_fr_iimmed 0x7ffffe00,fr11 + + set_accg_immed 0xffffffaf,accg0 + set_acc_immed 0x5a5a5a5a,acc0 + + mcuti acc0,-4,fr11 + test_fr_iimmed 0xfaf5a5a5,fr11 + + set_accg_immed 0x0000002f,accg0 + set_acc_immed 0x5a5a5a5a,acc0 + + mcuti acc0,-7,fr11 + test_fr_iimmed 0x005eb4b4,fr11 + + pass diff --git a/sim/testsuite/sim/frv/mcutss.cgs b/sim/testsuite/sim/frv/mcutss.cgs new file mode 100644 index 0000000..efe3278 --- /dev/null +++ b/sim/testsuite/sim/frv/mcutss.cgs @@ -0,0 +1,505 @@ +# frv testcase for mcutss $ACC40i,$FRj,$FRk +# mach: all + + .include "testutils.inc" + + start + + .global mcutss +mcutss: + set_accg_immed 0xffffffe7,accg0 + set_acc_immed 0x89abcdef,acc0 + + set_fr_iimmed 0,0,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xe789abcd,fr11 + + set_fr_iimmed 0,1,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xcf13579b,fr11 + + set_fr_iimmed 0,2,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x9e26af37,fr11 + + set_fr_iimmed 0,3,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_fr_iimmed 0,4,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_fr_iimmed 0,5,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_fr_iimmed 0,6,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_fr_iimmed 0,7,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_fr_iimmed 0,8,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_fr_iimmed 0,9,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_fr_iimmed 0,10,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_fr_iimmed 0,11,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_fr_iimmed 0,12,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_fr_iimmed 0,13,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_fr_iimmed 0,14,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_fr_iimmed 0,15,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_fr_iimmed 0,16,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_fr_iimmed 0,17,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_fr_iimmed 0,18,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_fr_iimmed 0,19,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_fr_iimmed 0,20,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_fr_iimmed 0,21,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_fr_iimmed 0,22,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_fr_iimmed 0,23,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_fr_iimmed 0,24,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_fr_iimmed 0,25,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_fr_iimmed 0,26,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_fr_iimmed 0,27,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_fr_iimmed 0,28,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_fr_iimmed 0,29,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_fr_iimmed 0,30,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_fr_iimmed 0,31,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_fr_iimmed 0,64,fr10 ; same as 0 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xe789abcd,fr11 + + set_fr_iimmed 0xffff,0xffff,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xf3c4d5e6,fr11 + + set_fr_iimmed 0x0000,0x003e,fr10 ; only lower 6 bits matter + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xf9e26af3,fr11 + + set_fr_iimmed 0xffff,0xfffd,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xfcf13579,fr11 + + set_fr_iimmed 0xffff,0xfffc,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xfe789abc,fr11 + + set_fr_iimmed 0xffff,0xfffb,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xff3c4d5e,fr11 + + set_fr_iimmed 0xffff,0xfffa,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xff9e26af,fr11 + + set_fr_iimmed 0xffff,0xfff9,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xffcf1357,fr11 + + set_fr_iimmed 0xffff,0xfff8,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xffe789ab,fr11 + + set_fr_iimmed 0xffff,0xfff7,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xfff3c4d5,fr11 + + set_fr_iimmed 0xffff,0xfff6,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xfff9e26a,fr11 + + set_fr_iimmed 0xffff,0xfff5,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xfffcf135,fr11 + + set_fr_iimmed 0xffff,0xfff4,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xfffe789a,fr11 + + set_fr_iimmed 0xffff,0xfff3,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xffff3c4d,fr11 + + set_fr_iimmed 0xffff,0xfff2,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xffff9e26,fr11 + + set_fr_iimmed 0xffff,0xfff1,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xffffcf13,fr11 + + set_fr_iimmed 0xffff,0xfff0,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xffffe789,fr11 + + set_fr_iimmed 0xffff,0xffef,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xfffff3c4,fr11 + + set_fr_iimmed 0xffff,0xffee,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xfffff9e2,fr11 + + set_fr_iimmed 0xffff,0xffed,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xfffffcf1,fr11 + + set_fr_iimmed 0xffff,0xffec,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xfffffe78,fr11 + + set_fr_iimmed 0xffff,0xffeb,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xffffff3c,fr11 + + set_fr_iimmed 0xffff,0xffea,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xffffff9e,fr11 + + set_fr_iimmed 0xffff,0xffe9,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xffffffcf,fr11 + + set_fr_iimmed 0xffff,0xffe8,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xffffffe7,fr11 + + set_fr_iimmed 0xffff,0xffe7,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xfffffff3,fr11 + + set_fr_iimmed 0xffff,0xffe6,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xfffffff9,fr11 + + set_fr_iimmed 0xffff,0xffe5,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xfffffffc,fr11 + + set_fr_iimmed 0xffff,0xffe4,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xfffffffe,fr11 + + set_fr_iimmed 0xffff,0xffe3,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xffffffff,fr11 + + set_fr_iimmed 0xffff,0xffe2,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xffffffff,fr11 + + set_fr_iimmed 0xffff,0xffe1,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xffffffff,fr11 + + set_fr_iimmed 0xffff,0xffe0,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xffffffff,fr11 + + set_fr_iimmed 0,32,fr10 ; same as -32 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xffffffff,fr11 + + set_accg_immed 0xffffff67,accg0 + set_acc_immed 0x89abcdef,acc0 + + set_fr_iimmed 0xffff,0xffff,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x33c4d5e6,fr11 + + set_fr_iimmed 0x0000,0x003e,fr10 ; only lower 6 bits matter + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x19e26af3,fr11 + + set_fr_iimmed 0xffff,0xfffd,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x0cf13579,fr11 + + set_fr_iimmed 0xffff,0xfffc,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x06789abc,fr11 + + set_fr_iimmed 0xffff,0xfffb,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x033c4d5e,fr11 + + set_fr_iimmed 0xffff,0xfffa,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x019e26af,fr11 + + set_fr_iimmed 0xffff,0xfff9,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x00cf1357,fr11 + + set_fr_iimmed 0xffff,0xfff8,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x006789ab,fr11 + + set_fr_iimmed 0xffff,0xfff7,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x0033c4d5,fr11 + + set_fr_iimmed 0xffff,0xfff6,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x0019e26a,fr11 + + set_fr_iimmed 0xffff,0xfff5,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x000cf135,fr11 + + set_fr_iimmed 0xffff,0xfff4,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x0006789a,fr11 + + set_fr_iimmed 0xffff,0xfff3,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x00033c4d,fr11 + + set_fr_iimmed 0xffff,0xfff2,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x00019e26,fr11 + + set_fr_iimmed 0xffff,0xfff1,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x0000cf13,fr11 + + set_fr_iimmed 0xffff,0xfff0,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x00006789,fr11 + + set_fr_iimmed 0xffff,0xffef,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x000033c4,fr11 + + set_fr_iimmed 0xffff,0xffee,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x000019e2,fr11 + + set_fr_iimmed 0xffff,0xffed,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x00000cf1,fr11 + + set_fr_iimmed 0xffff,0xffec,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x00000678,fr11 + + set_fr_iimmed 0xffff,0xffeb,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x0000033c,fr11 + + set_fr_iimmed 0xffff,0xffea,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x0000019e,fr11 + + set_fr_iimmed 0xffff,0xffe9,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x000000cf,fr11 + + set_fr_iimmed 0xffff,0xffe8,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x00000067,fr11 + + set_fr_iimmed 0xffff,0xffe7,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x00000033,fr11 + + set_fr_iimmed 0xffff,0xffe6,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x00000019,fr11 + + set_fr_iimmed 0xffff,0xffe5,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x0000000c,fr11 + + set_fr_iimmed 0xffff,0xffe4,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x00000006,fr11 + + set_fr_iimmed 0xffff,0xffe3,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x00000003,fr11 + + set_fr_iimmed 0xffff,0xffe2,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x00000001,fr11 + + set_fr_iimmed 0xffff,0xffe1,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x00000000,fr11 + + set_fr_iimmed 0xffff,0xffe0,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x00000000,fr11 + + set_fr_iimmed 0,32,fr10 ; same as -32 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x00000000,fr11 + + ; Examples from the customer + set_accg_immed 0xffffffff,accg0 + set_acc_immed 0xffe00000,acc0 + + set_fr_iimmed 0,16,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xe0000000,fr11 + + set_fr_iimmed 0,17,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xc0000000,fr11 + + set_fr_iimmed 0,18,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_accg_immed 0,accg0 + set_acc_immed 0x003fffff,acc0 + + set_fr_iimmed 0,16,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x3fffff00,fr11 + + set_fr_iimmed 0,17,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x7ffffe00,fr11 + + set_accg_immed 0x7f,accg0 + set_acc_immed 0xffe00000,acc0 + + set_fr_iimmed 0,16,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x7fffffff,fr11 ; saturated + + set_fr_iimmed 0,17,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x7fffffff,fr11 ; saturated + + set_fr_iimmed 0,18,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x7fffffff,fr11 ; saturated + + set_accg_immed 0x08,accg0 + set_acc_immed 0x003fffff,acc0 + + set_fr_iimmed 0,16,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x7fffffff,fr11 ; saturated + + set_fr_iimmed 0,17,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x7fffffff,fr11 ; saturated + + set_accg_immed 0xff,accg0 + set_acc_immed 0xefe00000,acc0 + + set_fr_iimmed 0,16,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 ; saturated + + set_fr_iimmed 0,17,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 ; saturated + + set_fr_iimmed 0,18,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 ; saturated + + set_accg_immed 0x80,accg0 + set_acc_immed 0x003fffff,acc0 + + set_fr_iimmed 0,16,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 ; saturated + + set_fr_iimmed 0,17,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 ; saturated + + set_accg_immed 0xffffffaf,accg0 + set_acc_immed 0x5a5a5a5a,acc0 + + set_fr_iimmed 0xffff,0xfffc,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0xfaf5a5a5,fr11 + + set_accg_immed 0x0000002f,accg0 + set_acc_immed 0x5a5a5a5a,acc0 + + set_fr_iimmed 0xffff,0xfff9,fr10 + mcutss acc0,fr10,fr11 + test_fr_iimmed 0x005eb4b4,fr11 + + pass diff --git a/sim/testsuite/sim/frv/mcutssi.cgs b/sim/testsuite/sim/frv/mcutssi.cgs new file mode 100644 index 0000000..739912f --- /dev/null +++ b/sim/testsuite/sim/frv/mcutssi.cgs @@ -0,0 +1,380 @@ +# frv testcase for mcutssi $ACC40i,$s6,$FRk +# mach: all + + .include "testutils.inc" + + start + + .global mcutssi +mcutssi: + set_accg_immed 0xffffffe7,accg0 + set_acc_immed 0x89abcdef,acc0 + + mcutssi acc0,0,fr11 + test_fr_iimmed 0xe789abcd,fr11 + + mcutssi acc0,1,fr11 + test_fr_iimmed 0xcf13579b,fr11 + + mcutssi acc0,2,fr11 + test_fr_iimmed 0x9e26af37,fr11 + + mcutssi acc0,3,fr11 + test_fr_iimmed 0x80000000,fr11 + + mcutssi acc0,4,fr11 + test_fr_iimmed 0x80000000,fr11 + + mcutssi acc0,5,fr11 + test_fr_iimmed 0x80000000,fr11 + + mcutssi acc0,6,fr11 + test_fr_iimmed 0x80000000,fr11 + + mcutssi acc0,7,fr11 + test_fr_iimmed 0x80000000,fr11 + + mcutssi acc0,8,fr11 + test_fr_iimmed 0x80000000,fr11 + + mcutssi acc0,9,fr11 + test_fr_iimmed 0x80000000,fr11 + + mcutssi acc0,10,fr11 + test_fr_iimmed 0x80000000,fr11 + + mcutssi acc0,11,fr11 + test_fr_iimmed 0x80000000,fr11 + + mcutssi acc0,12,fr11 + test_fr_iimmed 0x80000000,fr11 + + mcutssi acc0,13,fr11 + test_fr_iimmed 0x80000000,fr11 + + mcutssi acc0,14,fr11 + test_fr_iimmed 0x80000000,fr11 + + mcutssi acc0,15,fr11 + test_fr_iimmed 0x80000000,fr11 + + mcutssi acc0,16,fr11 + test_fr_iimmed 0x80000000,fr11 + + mcutssi acc0,17,fr11 + test_fr_iimmed 0x80000000,fr11 + + mcutssi acc0,18,fr11 + test_fr_iimmed 0x80000000,fr11 + + mcutssi acc0,19,fr11 + test_fr_iimmed 0x80000000,fr11 + + mcutssi acc0,20,fr11 + test_fr_iimmed 0x80000000,fr11 + + mcutssi acc0,21,fr11 + test_fr_iimmed 0x80000000,fr11 + + mcutssi acc0,22,fr11 + test_fr_iimmed 0x80000000,fr11 + + mcutssi acc0,23,fr11 + test_fr_iimmed 0x80000000,fr11 + + mcutssi acc0,24,fr11 + test_fr_iimmed 0x80000000,fr11 + + mcutssi acc0,25,fr11 + test_fr_iimmed 0x80000000,fr11 + + mcutssi acc0,26,fr11 + test_fr_iimmed 0x80000000,fr11 + + mcutssi acc0,27,fr11 + test_fr_iimmed 0x80000000,fr11 + + mcutssi acc0,28,fr11 + test_fr_iimmed 0x80000000,fr11 + + mcutssi acc0,29,fr11 + test_fr_iimmed 0x80000000,fr11 + + mcutssi acc0,30,fr11 + test_fr_iimmed 0x80000000,fr11 + + mcutssi acc0,31,fr11 + test_fr_iimmed 0x80000000,fr11 + + mcutssi acc0,-1,fr11 + test_fr_iimmed 0xf3c4d5e6,fr11 + + mcutssi acc0,-2,fr11 + test_fr_iimmed 0xf9e26af3,fr11 + + mcutssi acc0,-3,fr11 + test_fr_iimmed 0xfcf13579,fr11 + + mcutssi acc0,-4,fr11 + test_fr_iimmed 0xfe789abc,fr11 + + mcutssi acc0,-5,fr11 + test_fr_iimmed 0xff3c4d5e,fr11 + + mcutssi acc0,-6,fr11 + test_fr_iimmed 0xff9e26af,fr11 + + mcutssi acc0,-7,fr11 + test_fr_iimmed 0xffcf1357,fr11 + + mcutssi acc0,-8,fr11 + test_fr_iimmed 0xffe789ab,fr11 + + mcutssi acc0,-9,fr11 + test_fr_iimmed 0xfff3c4d5,fr11 + + mcutssi acc0,-10,fr11 + test_fr_iimmed 0xfff9e26a,fr11 + + mcutssi acc0,-11,fr11 + test_fr_iimmed 0xfffcf135,fr11 + + mcutssi acc0,-12,fr11 + test_fr_iimmed 0xfffe789a,fr11 + + mcutssi acc0,-13,fr11 + test_fr_iimmed 0xffff3c4d,fr11 + + mcutssi acc0,-14,fr11 + test_fr_iimmed 0xffff9e26,fr11 + + mcutssi acc0,-15,fr11 + test_fr_iimmed 0xffffcf13,fr11 + + mcutssi acc0,-16,fr11 + test_fr_iimmed 0xffffe789,fr11 + + mcutssi acc0,-17,fr11 + test_fr_iimmed 0xfffff3c4,fr11 + + mcutssi acc0,-18,fr11 + test_fr_iimmed 0xfffff9e2,fr11 + + mcutssi acc0,-19,fr11 + test_fr_iimmed 0xfffffcf1,fr11 + + mcutssi acc0,-20,fr11 + test_fr_iimmed 0xfffffe78,fr11 + + mcutssi acc0,-21,fr11 + test_fr_iimmed 0xffffff3c,fr11 + + mcutssi acc0,-22,fr11 + test_fr_iimmed 0xffffff9e,fr11 + + mcutssi acc0,-23,fr11 + test_fr_iimmed 0xffffffcf,fr11 + + mcutssi acc0,-24,fr11 + test_fr_iimmed 0xffffffe7,fr11 + + mcutssi acc0,-25,fr11 + test_fr_iimmed 0xfffffff3,fr11 + + mcutssi acc0,-26,fr11 + test_fr_iimmed 0xfffffff9,fr11 + + mcutssi acc0,-27,fr11 + test_fr_iimmed 0xfffffffc,fr11 + + mcutssi acc0,-28,fr11 + test_fr_iimmed 0xfffffffe,fr11 + + mcutssi acc0,-29,fr11 + test_fr_iimmed 0xffffffff,fr11 + + mcutssi acc0,-30,fr11 + test_fr_iimmed 0xffffffff,fr11 + + mcutssi acc0,-31,fr11 + test_fr_iimmed 0xffffffff,fr11 + + mcutssi acc0,-32,fr11 + test_fr_iimmed 0xffffffff,fr11 + + set_accg_immed 0xffffff67,accg0 + set_acc_immed 0x89abcdef,acc0 + + mcutssi acc0,-1,fr11 + test_fr_iimmed 0x33c4d5e6,fr11 + + mcutssi acc0,-2,fr11 + test_fr_iimmed 0x19e26af3,fr11 + + mcutssi acc0,-3,fr11 + test_fr_iimmed 0x0cf13579,fr11 + + mcutssi acc0,-4,fr11 + test_fr_iimmed 0x06789abc,fr11 + + mcutssi acc0,-5,fr11 + test_fr_iimmed 0x033c4d5e,fr11 + + mcutssi acc0,-6,fr11 + test_fr_iimmed 0x019e26af,fr11 + + mcutssi acc0,-7,fr11 + test_fr_iimmed 0x00cf1357,fr11 + + mcutssi acc0,-8,fr11 + test_fr_iimmed 0x006789ab,fr11 + + mcutssi acc0,-9,fr11 + test_fr_iimmed 0x0033c4d5,fr11 + + mcutssi acc0,-10,fr11 + test_fr_iimmed 0x0019e26a,fr11 + + mcutssi acc0,-11,fr11 + test_fr_iimmed 0x000cf135,fr11 + + mcutssi acc0,-12,fr11 + test_fr_iimmed 0x0006789a,fr11 + + mcutssi acc0,-13,fr11 + test_fr_iimmed 0x00033c4d,fr11 + + mcutssi acc0,-14,fr11 + test_fr_iimmed 0x00019e26,fr11 + + mcutssi acc0,-15,fr11 + test_fr_iimmed 0x0000cf13,fr11 + + mcutssi acc0,-16,fr11 + test_fr_iimmed 0x00006789,fr11 + + mcutssi acc0,-17,fr11 + test_fr_iimmed 0x000033c4,fr11 + + mcutssi acc0,-18,fr11 + test_fr_iimmed 0x000019e2,fr11 + + mcutssi acc0,-19,fr11 + test_fr_iimmed 0x00000cf1,fr11 + + mcutssi acc0,-20,fr11 + test_fr_iimmed 0x00000678,fr11 + + mcutssi acc0,-21,fr11 + test_fr_iimmed 0x0000033c,fr11 + + mcutssi acc0,-22,fr11 + test_fr_iimmed 0x0000019e,fr11 + + mcutssi acc0,-23,fr11 + test_fr_iimmed 0x000000cf,fr11 + + mcutssi acc0,-24,fr11 + test_fr_iimmed 0x00000067,fr11 + + mcutssi acc0,-25,fr11 + test_fr_iimmed 0x00000033,fr11 + + mcutssi acc0,-26,fr11 + test_fr_iimmed 0x00000019,fr11 + + mcutssi acc0,-27,fr11 + test_fr_iimmed 0x0000000c,fr11 + + mcutssi acc0,-28,fr11 + test_fr_iimmed 0x00000006,fr11 + + mcutssi acc0,-29,fr11 + test_fr_iimmed 0x00000003,fr11 + + mcutssi acc0,-30,fr11 + test_fr_iimmed 0x00000001,fr11 + + mcutssi acc0,-31,fr11 + test_fr_iimmed 0x00000000,fr11 + + mcutssi acc0,-32,fr11 + test_fr_iimmed 0x00000000,fr11 + + ; Examples from the customer + set_accg_immed 0xffffffff,accg0 + set_acc_immed 0xffe00000,acc0 + + mcutssi acc0,16,fr11 + test_fr_iimmed 0xe0000000,fr11 + + mcutssi acc0,17,fr11 + test_fr_iimmed 0xc0000000,fr11 + + mcutssi acc0,18,fr11 + test_fr_iimmed 0x80000000,fr11 + + set_accg_immed 0,accg0 + set_acc_immed 0x003fffff,acc0 + + mcutssi acc0,16,fr11 + test_fr_iimmed 0x3fffff00,fr11 + + mcutssi acc0,17,fr11 + test_fr_iimmed 0x7ffffe00,fr11 + + set_accg_immed 0x7f,accg0 + set_acc_immed 0xffe00000,acc0 + + mcutssi acc0,16,fr11 + test_fr_iimmed 0x7fffffff,fr11 ; saturated + + mcutssi acc0,17,fr11 + test_fr_iimmed 0x7fffffff,fr11 ; saturated + + mcutssi acc0,18,fr11 + test_fr_iimmed 0x7fffffff,fr11 ; saturated + + set_accg_immed 0x08,accg0 + set_acc_immed 0x003fffff,acc0 + + mcutssi acc0,16,fr11 + test_fr_iimmed 0x7fffffff,fr11 ; saturated + + mcutssi acc0,17,fr11 + test_fr_iimmed 0x7fffffff,fr11 ; saturated + + set_accg_immed 0xff,accg0 + set_acc_immed 0xefe00000,acc0 + + mcutssi acc0,16,fr11 + test_fr_iimmed 0x80000000,fr11 ; saturated + + mcutssi acc0,17,fr11 + test_fr_iimmed 0x80000000,fr11 ; saturated + + mcutssi acc0,18,fr11 + test_fr_iimmed 0x80000000,fr11 ; saturated + + set_accg_immed 0x80,accg0 + set_acc_immed 0x003fffff,acc0 + + mcutssi acc0,16,fr11 + test_fr_iimmed 0x80000000,fr11 ; saturated + + mcutssi acc0,17,fr11 + test_fr_iimmed 0x80000000,fr11 ; saturated + + set_accg_immed 0xffffffaf,accg0 + set_acc_immed 0x5a5a5a5a,acc0 + + mcutssi acc0,-4,fr11 + test_fr_iimmed 0xfaf5a5a5,fr11 + + set_accg_immed 0x0000002f,accg0 + set_acc_immed 0x5a5a5a5a,acc0 + + mcutssi acc0,-7,fr11 + test_fr_iimmed 0x005eb4b4,fr11 + + pass diff --git a/sim/testsuite/sim/frv/mdaddaccs.cgs b/sim/testsuite/sim/frv/mdaddaccs.cgs new file mode 100644 index 0000000..553c4a7 --- /dev/null +++ b/sim/testsuite/sim/frv/mdaddaccs.cgs @@ -0,0 +1,102 @@ +# frv testcase for mdaddaccs $ACC40Si,$ACC40Sk +# mach: fr400 + + .include "testutils.inc" + + start + + .global mdaddaccs +mdaddaccs: + set_accg_immed 0,accg0 + set_acc_immed 0x00000000,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x00000000,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0xdead0000,acc2 + set_accg_immed 0,accg3 + set_acc_immed 0x0000beef,acc3 + mdaddaccs acc0,acc2 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x0000,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0xdead,0xbeef,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x0000dead,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0xbeef0000,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0x12345678,acc2 + set_accg_immed 0,accg3 + set_acc_immed 0x11111111,acc3 + mdaddaccs acc0,acc2 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg2 + test_acc_limmed 0xbeef,0xdead,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x2345,0x6789,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x12345678,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0xffffffff,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0x12345678,acc2 + set_accg_immed 0xff,accg3 + set_acc_immed 0xffffffff,acc3 + mdaddaccs acc0,acc2 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 1,accg2 + test_acc_limmed 0x1234,0x5677,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x1234,0x5677,acc3 + + set_spr_immed 0,msr0 + set_accg_immed 0x7f,accg0 + set_acc_immed 0xfffe7ffe,acc0 + set_accg_immed 0x0,accg1 + set_acc_immed 0x00020001,acc1 + set_accg_immed 0x80,accg2 + set_acc_immed 0x00000001,acc2 + set_accg_immed 0xff,accg3 + set_acc_immed 0xfffffffe,acc3 + mdaddaccs acc0,acc2 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + test_accg_immed 0x7f,accg2 + test_acc_limmed 0xffff,0xffff,acc2 + test_accg_immed 0x80,accg3 + test_acc_limmed 0x0000,0x0000,acc3 + + set_spr_immed 0,msr0 + set_accg_immed 0,accg0 + set_acc_immed 0x00000001,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x00000001,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0x00000001,acc2 + set_accg_immed 0x7f,accg3 + set_acc_immed 0xffffffff,acc3 + mdaddaccs acc0,acc2 + test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x0002,acc2 + test_accg_immed 0x7f,accg3 + test_acc_limmed 0xffff,0xffff,acc3 + + pass diff --git a/sim/testsuite/sim/frv/mdasaccs.cgs b/sim/testsuite/sim/frv/mdasaccs.cgs new file mode 100644 index 0000000..0535b62 --- /dev/null +++ b/sim/testsuite/sim/frv/mdasaccs.cgs @@ -0,0 +1,122 @@ +# frv testcase for mdasaccs $ACC40Si,$ACC40Sk +# mach: fr400 + + .include "testutils.inc" + + start + + .global mdasaccs +mdasaccs: + set_accg_immed 0,accg0 + set_acc_immed 0x00000000,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x00000000,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0xdead0000,acc2 + set_accg_immed 0,accg3 + set_acc_immed 0x0000beef,acc3 + mdasaccs acc0,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x0000,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x0000,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0xdead,0xbeef,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0xdeac,0x4111,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x0000dead,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0xbeef0000,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0x12345678,acc2 + set_accg_immed 0,accg3 + set_acc_immed 0x11111111,acc3 + mdasaccs acc0,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0xbeef,0xdead,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0x4111,0xdead,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x2345,0x6789,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0123,0x4567,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x12345678,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0xffffffff,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0x12345678,acc2 + set_accg_immed 0xff,accg3 + set_acc_immed 0xffffffff,acc3 + mdasaccs acc0,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 1,accg0 + test_acc_limmed 0x1234,0x5677,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0x1234,0x5679,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x1234,0x5677,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x1234,0x5679,acc3 + + set_spr_immed 0,msr0 + set_accg_immed 0x7f,accg0 + set_acc_immed 0xfffe7ffe,acc0 + set_accg_immed 0x0,accg1 + set_acc_immed 0x00020001,acc1 + set_accg_immed 0x80,accg2 + set_acc_immed 0x00000001,acc2 + set_accg_immed 0xff,accg3 + set_acc_immed 0xfffffffe,acc3 + mdasaccs acc0,acc0 + test_spr_bits 0x3c,2,0xa,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xfffc,0x7ffd,acc1 + test_accg_immed 0x80,accg2 + test_acc_limmed 0x0000,0x0000,acc2 + test_accg_immed 0x80,accg3 + test_acc_limmed 0x0000,0x0003,acc3 + + set_spr_immed 0,msr0 + set_accg_immed 0,accg0 + set_acc_immed 0x00000001,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x00000001,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0x00000001,acc2 + set_accg_immed 0x7f,accg3 + set_acc_immed 0xffffffff,acc3 + mdasaccs acc0,acc0 + test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x0002,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x0000,acc1 + test_accg_immed 0x7f,accg2 + test_acc_limmed 0xffff,0xffff,acc2 + test_accg_immed 0x80,accg3 + test_acc_limmed 0x0000,0x0002,acc3 + + pass diff --git a/sim/testsuite/sim/frv/mdcutssi.cgs b/sim/testsuite/sim/frv/mdcutssi.cgs new file mode 100644 index 0000000..8e5216c --- /dev/null +++ b/sim/testsuite/sim/frv/mdcutssi.cgs @@ -0,0 +1,513 @@ +# frv testcase for mdcutssi $ACC40i,$s6,$FRk +# mach: fr400 fr550 + + .include "testutils.inc" + + start + + .global mdcutssi +mdcutssi: + set_accg_immed 0xffffffe7,accg0 + set_acc_immed 0x89abcdef,acc0 + set_accg_immed 0xffffffe7,accg1 + set_acc_immed 0x89abcdef,acc1 + + mdcutssi acc0,0,fr10 + test_fr_iimmed 0xe789abcd,fr10 + test_fr_iimmed 0xe789abcd,fr11 + + mdcutssi acc0,1,fr10 + test_fr_iimmed 0xcf13579b,fr10 + test_fr_iimmed 0xcf13579b,fr11 + + mdcutssi acc0,2,fr10 + test_fr_iimmed 0x9e26af37,fr10 + test_fr_iimmed 0x9e26af37,fr11 + + mdcutssi acc0,3,fr10 + test_fr_iimmed 0x80000000,fr10 + test_fr_iimmed 0x80000000,fr11 + + mdcutssi acc0,4,fr10 + test_fr_iimmed 0x80000000,fr10 + test_fr_iimmed 0x80000000,fr11 + + mdcutssi acc0,5,fr10 + test_fr_iimmed 0x80000000,fr10 + test_fr_iimmed 0x80000000,fr11 + + mdcutssi acc0,6,fr10 + test_fr_iimmed 0x80000000,fr10 + test_fr_iimmed 0x80000000,fr11 + + mdcutssi acc0,7,fr10 + test_fr_iimmed 0x80000000,fr10 + test_fr_iimmed 0x80000000,fr11 + + mdcutssi acc0,8,fr10 + test_fr_iimmed 0x80000000,fr10 + test_fr_iimmed 0x80000000,fr11 + + mdcutssi acc0,9,fr10 + test_fr_iimmed 0x80000000,fr10 + test_fr_iimmed 0x80000000,fr11 + + mdcutssi acc0,10,fr10 + test_fr_iimmed 0x80000000,fr10 + test_fr_iimmed 0x80000000,fr11 + + mdcutssi acc0,11,fr10 + test_fr_iimmed 0x80000000,fr10 + test_fr_iimmed 0x80000000,fr11 + + mdcutssi acc0,12,fr10 + test_fr_iimmed 0x80000000,fr10 + test_fr_iimmed 0x80000000,fr11 + + mdcutssi acc0,13,fr10 + test_fr_iimmed 0x80000000,fr10 + test_fr_iimmed 0x80000000,fr11 + + mdcutssi acc0,14,fr10 + test_fr_iimmed 0x80000000,fr10 + test_fr_iimmed 0x80000000,fr11 + + mdcutssi acc0,15,fr10 + test_fr_iimmed 0x80000000,fr10 + test_fr_iimmed 0x80000000,fr11 + + mdcutssi acc0,16,fr10 + test_fr_iimmed 0x80000000,fr10 + test_fr_iimmed 0x80000000,fr11 + + mdcutssi acc0,17,fr10 + test_fr_iimmed 0x80000000,fr10 + test_fr_iimmed 0x80000000,fr11 + + mdcutssi acc0,18,fr10 + test_fr_iimmed 0x80000000,fr10 + test_fr_iimmed 0x80000000,fr11 + + mdcutssi acc0,19,fr10 + test_fr_iimmed 0x80000000,fr10 + test_fr_iimmed 0x80000000,fr11 + + mdcutssi acc0,20,fr10 + test_fr_iimmed 0x80000000,fr10 + test_fr_iimmed 0x80000000,fr11 + + mdcutssi acc0,21,fr10 + test_fr_iimmed 0x80000000,fr10 + test_fr_iimmed 0x80000000,fr11 + + mdcutssi acc0,22,fr10 + test_fr_iimmed 0x80000000,fr10 + test_fr_iimmed 0x80000000,fr11 + + mdcutssi acc0,23,fr10 + test_fr_iimmed 0x80000000,fr10 + test_fr_iimmed 0x80000000,fr11 + + mdcutssi acc0,24,fr10 + test_fr_iimmed 0x80000000,fr10 + test_fr_iimmed 0x80000000,fr11 + + mdcutssi acc0,25,fr10 + test_fr_iimmed 0x80000000,fr10 + test_fr_iimmed 0x80000000,fr11 + + mdcutssi acc0,26,fr10 + test_fr_iimmed 0x80000000,fr10 + test_fr_iimmed 0x80000000,fr11 + + mdcutssi acc0,27,fr10 + test_fr_iimmed 0x80000000,fr10 + test_fr_iimmed 0x80000000,fr11 + + mdcutssi acc0,28,fr10 + test_fr_iimmed 0x80000000,fr10 + test_fr_iimmed 0x80000000,fr11 + + mdcutssi acc0,29,fr10 + test_fr_iimmed 0x80000000,fr10 + test_fr_iimmed 0x80000000,fr11 + + mdcutssi acc0,30,fr10 + test_fr_iimmed 0x80000000,fr10 + test_fr_iimmed 0x80000000,fr11 + + mdcutssi acc0,31,fr10 + test_fr_iimmed 0x80000000,fr10 + test_fr_iimmed 0x80000000,fr11 + + mdcutssi acc0,-1,fr10 + test_fr_iimmed 0xf3c4d5e6,fr10 + test_fr_iimmed 0xf3c4d5e6,fr11 + + mdcutssi acc0,-2,fr10 + test_fr_iimmed 0xf9e26af3,fr10 + test_fr_iimmed 0xf9e26af3,fr11 + + mdcutssi acc0,-3,fr10 + test_fr_iimmed 0xfcf13579,fr10 + test_fr_iimmed 0xfcf13579,fr11 + + mdcutssi acc0,-4,fr10 + test_fr_iimmed 0xfe789abc,fr10 + test_fr_iimmed 0xfe789abc,fr11 + + mdcutssi acc0,-5,fr10 + test_fr_iimmed 0xff3c4d5e,fr10 + test_fr_iimmed 0xff3c4d5e,fr11 + + mdcutssi acc0,-6,fr10 + test_fr_iimmed 0xff9e26af,fr10 + test_fr_iimmed 0xff9e26af,fr11 + + mdcutssi acc0,-7,fr10 + test_fr_iimmed 0xffcf1357,fr10 + test_fr_iimmed 0xffcf1357,fr11 + + mdcutssi acc0,-8,fr10 + test_fr_iimmed 0xffe789ab,fr10 + test_fr_iimmed 0xffe789ab,fr11 + + mdcutssi acc0,-9,fr10 + test_fr_iimmed 0xfff3c4d5,fr10 + test_fr_iimmed 0xfff3c4d5,fr11 + + mdcutssi acc0,-10,fr10 + test_fr_iimmed 0xfff9e26a,fr10 + test_fr_iimmed 0xfff9e26a,fr11 + + mdcutssi acc0,-11,fr10 + test_fr_iimmed 0xfffcf135,fr10 + test_fr_iimmed 0xfffcf135,fr11 + + mdcutssi acc0,-12,fr10 + test_fr_iimmed 0xfffe789a,fr10 + test_fr_iimmed 0xfffe789a,fr11 + + mdcutssi acc0,-13,fr10 + test_fr_iimmed 0xffff3c4d,fr10 + test_fr_iimmed 0xffff3c4d,fr11 + + mdcutssi acc0,-14,fr10 + test_fr_iimmed 0xffff9e26,fr10 + test_fr_iimmed 0xffff9e26,fr11 + + mdcutssi acc0,-15,fr10 + test_fr_iimmed 0xffffcf13,fr10 + test_fr_iimmed 0xffffcf13,fr11 + + mdcutssi acc0,-16,fr10 + test_fr_iimmed 0xffffe789,fr10 + test_fr_iimmed 0xffffe789,fr11 + + mdcutssi acc0,-17,fr10 + test_fr_iimmed 0xfffff3c4,fr10 + test_fr_iimmed 0xfffff3c4,fr11 + + mdcutssi acc0,-18,fr10 + test_fr_iimmed 0xfffff9e2,fr10 + test_fr_iimmed 0xfffff9e2,fr11 + + mdcutssi acc0,-19,fr10 + test_fr_iimmed 0xfffffcf1,fr10 + test_fr_iimmed 0xfffffcf1,fr11 + + mdcutssi acc0,-20,fr10 + test_fr_iimmed 0xfffffe78,fr10 + test_fr_iimmed 0xfffffe78,fr11 + + mdcutssi acc0,-21,fr10 + test_fr_iimmed 0xffffff3c,fr10 + test_fr_iimmed 0xffffff3c,fr11 + + mdcutssi acc0,-22,fr10 + test_fr_iimmed 0xffffff9e,fr10 + test_fr_iimmed 0xffffff9e,fr11 + + mdcutssi acc0,-23,fr10 + test_fr_iimmed 0xffffffcf,fr10 + test_fr_iimmed 0xffffffcf,fr11 + + mdcutssi acc0,-24,fr10 + test_fr_iimmed 0xffffffe7,fr10 + test_fr_iimmed 0xffffffe7,fr11 + + mdcutssi acc0,-25,fr10 + test_fr_iimmed 0xfffffff3,fr10 + test_fr_iimmed 0xfffffff3,fr11 + + mdcutssi acc0,-26,fr10 + test_fr_iimmed 0xfffffff9,fr10 + test_fr_iimmed 0xfffffff9,fr11 + + mdcutssi acc0,-27,fr10 + test_fr_iimmed 0xfffffffc,fr10 + test_fr_iimmed 0xfffffffc,fr11 + + mdcutssi acc0,-28,fr10 + test_fr_iimmed 0xfffffffe,fr10 + test_fr_iimmed 0xfffffffe,fr11 + + mdcutssi acc0,-29,fr10 + test_fr_iimmed 0xffffffff,fr10 + test_fr_iimmed 0xffffffff,fr11 + + mdcutssi acc0,-30,fr10 + test_fr_iimmed 0xffffffff,fr10 + test_fr_iimmed 0xffffffff,fr11 + + mdcutssi acc0,-31,fr10 + test_fr_iimmed 0xffffffff,fr10 + test_fr_iimmed 0xffffffff,fr11 + + mdcutssi acc0,-32,fr10 + test_fr_iimmed 0xffffffff,fr10 + test_fr_iimmed 0xffffffff,fr11 + + set_accg_immed 0xffffff67,accg0 + set_acc_immed 0x89abcdef,acc0 + set_accg_immed 0xffffff67,accg1 + set_acc_immed 0x89abcdef,acc1 + + mdcutssi acc0,-1,fr10 + test_fr_iimmed 0x33c4d5e6,fr10 + test_fr_iimmed 0x33c4d5e6,fr11 + + mdcutssi acc0,-2,fr10 + test_fr_iimmed 0x19e26af3,fr10 + test_fr_iimmed 0x19e26af3,fr11 + + mdcutssi acc0,-3,fr10 + test_fr_iimmed 0x0cf13579,fr10 + test_fr_iimmed 0x0cf13579,fr11 + + mdcutssi acc0,-4,fr10 + test_fr_iimmed 0x06789abc,fr10 + test_fr_iimmed 0x06789abc,fr11 + + mdcutssi acc0,-5,fr10 + test_fr_iimmed 0x033c4d5e,fr10 + test_fr_iimmed 0x033c4d5e,fr11 + + mdcutssi acc0,-6,fr10 + test_fr_iimmed 0x019e26af,fr10 + test_fr_iimmed 0x019e26af,fr11 + + mdcutssi acc0,-7,fr10 + test_fr_iimmed 0x00cf1357,fr10 + test_fr_iimmed 0x00cf1357,fr11 + + mdcutssi acc0,-8,fr10 + test_fr_iimmed 0x006789ab,fr10 + test_fr_iimmed 0x006789ab,fr11 + + mdcutssi acc0,-9,fr10 + test_fr_iimmed 0x0033c4d5,fr10 + test_fr_iimmed 0x0033c4d5,fr11 + + mdcutssi acc0,-10,fr10 + test_fr_iimmed 0x0019e26a,fr10 + test_fr_iimmed 0x0019e26a,fr11 + + mdcutssi acc0,-11,fr10 + test_fr_iimmed 0x000cf135,fr10 + test_fr_iimmed 0x000cf135,fr11 + + mdcutssi acc0,-12,fr10 + test_fr_iimmed 0x0006789a,fr10 + test_fr_iimmed 0x0006789a,fr11 + + mdcutssi acc0,-13,fr10 + test_fr_iimmed 0x00033c4d,fr10 + test_fr_iimmed 0x00033c4d,fr11 + + mdcutssi acc0,-14,fr10 + test_fr_iimmed 0x00019e26,fr10 + test_fr_iimmed 0x00019e26,fr11 + + mdcutssi acc0,-15,fr10 + test_fr_iimmed 0x0000cf13,fr10 + test_fr_iimmed 0x0000cf13,fr11 + + mdcutssi acc0,-16,fr10 + test_fr_iimmed 0x00006789,fr10 + test_fr_iimmed 0x00006789,fr11 + + mdcutssi acc0,-17,fr10 + test_fr_iimmed 0x000033c4,fr10 + test_fr_iimmed 0x000033c4,fr11 + + mdcutssi acc0,-18,fr10 + test_fr_iimmed 0x000019e2,fr10 + test_fr_iimmed 0x000019e2,fr11 + + mdcutssi acc0,-19,fr10 + test_fr_iimmed 0x00000cf1,fr10 + test_fr_iimmed 0x00000cf1,fr11 + + mdcutssi acc0,-20,fr10 + test_fr_iimmed 0x00000678,fr10 + test_fr_iimmed 0x00000678,fr11 + + mdcutssi acc0,-21,fr10 + test_fr_iimmed 0x0000033c,fr10 + test_fr_iimmed 0x0000033c,fr11 + + mdcutssi acc0,-22,fr10 + test_fr_iimmed 0x0000019e,fr10 + test_fr_iimmed 0x0000019e,fr11 + + mdcutssi acc0,-23,fr10 + test_fr_iimmed 0x000000cf,fr10 + test_fr_iimmed 0x000000cf,fr11 + + mdcutssi acc0,-24,fr10 + test_fr_iimmed 0x00000067,fr10 + test_fr_iimmed 0x00000067,fr11 + + mdcutssi acc0,-25,fr10 + test_fr_iimmed 0x00000033,fr10 + test_fr_iimmed 0x00000033,fr11 + + mdcutssi acc0,-26,fr10 + test_fr_iimmed 0x00000019,fr10 + test_fr_iimmed 0x00000019,fr11 + + mdcutssi acc0,-27,fr10 + test_fr_iimmed 0x0000000c,fr10 + test_fr_iimmed 0x0000000c,fr11 + + mdcutssi acc0,-28,fr10 + test_fr_iimmed 0x00000006,fr10 + test_fr_iimmed 0x00000006,fr11 + + mdcutssi acc0,-29,fr10 + test_fr_iimmed 0x00000003,fr10 + test_fr_iimmed 0x00000003,fr11 + + mdcutssi acc0,-30,fr10 + test_fr_iimmed 0x00000001,fr10 + test_fr_iimmed 0x00000001,fr11 + + mdcutssi acc0,-31,fr10 + test_fr_iimmed 0x00000000,fr10 + test_fr_iimmed 0x00000000,fr11 + + mdcutssi acc0,-32,fr10 + test_fr_iimmed 0x00000000,fr10 + test_fr_iimmed 0x00000000,fr11 + + ; Examples from the customer + set_accg_immed 0xffffffff,accg0 + set_acc_immed 0xffe00000,acc0 + set_accg_immed 0xffffffff,accg1 + set_acc_immed 0xffe00000,acc1 + + mdcutssi acc0,16,fr10 + test_fr_iimmed 0xe0000000,fr10 + test_fr_iimmed 0xe0000000,fr11 + + mdcutssi acc0,17,fr10 + test_fr_iimmed 0xc0000000,fr10 + test_fr_iimmed 0xc0000000,fr11 + + mdcutssi acc0,18,fr10 + test_fr_iimmed 0x80000000,fr10 + test_fr_iimmed 0x80000000,fr11 + + set_accg_immed 0,accg0 + set_acc_immed 0x003fffff,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x003fffff,acc1 + + mdcutssi acc0,16,fr10 + test_fr_iimmed 0x3fffff00,fr10 + test_fr_iimmed 0x3fffff00,fr11 + + mdcutssi acc0,17,fr10 + test_fr_iimmed 0x7ffffe00,fr10 + test_fr_iimmed 0x7ffffe00,fr11 + + set_accg_immed 0x7f,accg0 + set_acc_immed 0xffe00000,acc0 + set_accg_immed 0x7f,accg1 + set_acc_immed 0xffe00000,acc1 + + mdcutssi acc0,16,fr10 + test_fr_iimmed 0x7fffffff,fr10 ; saturated + test_fr_iimmed 0x7fffffff,fr11 ; saturated + + mdcutssi acc0,17,fr10 + test_fr_iimmed 0x7fffffff,fr10 ; saturated + test_fr_iimmed 0x7fffffff,fr11 ; saturated + + mdcutssi acc0,18,fr10 + test_fr_iimmed 0x7fffffff,fr10 ; saturated + test_fr_iimmed 0x7fffffff,fr11 ; saturated + + set_accg_immed 0x08,accg0 + set_acc_immed 0x003fffff,acc0 + set_accg_immed 0x08,accg1 + set_acc_immed 0x003fffff,acc1 + + mdcutssi acc0,16,fr10 + test_fr_iimmed 0x7fffffff,fr10 ; saturated + test_fr_iimmed 0x7fffffff,fr11 ; saturated + + mdcutssi acc0,17,fr10 + test_fr_iimmed 0x7fffffff,fr10 ; saturated + test_fr_iimmed 0x7fffffff,fr11 ; saturated + + set_accg_immed 0xff,accg0 + set_acc_immed 0xefe00000,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xefe00000,acc1 + + mdcutssi acc0,16,fr10 + test_fr_iimmed 0x80000000,fr10 ; saturated + test_fr_iimmed 0x80000000,fr11 ; saturated + + mdcutssi acc0,17,fr10 + test_fr_iimmed 0x80000000,fr10 ; saturated + test_fr_iimmed 0x80000000,fr11 ; saturated + + mdcutssi acc0,18,fr10 + test_fr_iimmed 0x80000000,fr10 ; saturated + test_fr_iimmed 0x80000000,fr11 ; saturated + + set_accg_immed 0x80,accg0 + set_acc_immed 0x003fffff,acc0 + set_accg_immed 0x80,accg1 + set_acc_immed 0x003fffff,acc1 + + mdcutssi acc0,16,fr10 + test_fr_iimmed 0x80000000,fr10 ; saturated + test_fr_iimmed 0x80000000,fr11 ; saturated + + mdcutssi acc0,17,fr10 + test_fr_iimmed 0x80000000,fr10 ; saturated + test_fr_iimmed 0x80000000,fr11 ; saturated + + set_accg_immed 0xffffffaf,accg0 + set_acc_immed 0x5a5a5a5a,acc0 + set_accg_immed 0xffffffaf,accg1 + set_acc_immed 0x5a5a5a5a,acc1 + + mdcutssi acc0,-4,fr10 + test_fr_iimmed 0xfaf5a5a5,fr10 + test_fr_iimmed 0xfaf5a5a5,fr11 + + set_accg_immed 0x0000002f,accg0 + set_acc_immed 0x5a5a5a5a,acc0 + set_accg_immed 0x0000002f,accg1 + set_acc_immed 0x5a5a5a5a,acc1 + + mdcutssi acc0,-7,fr10 + test_fr_iimmed 0x005eb4b4,fr10 + test_fr_iimmed 0x005eb4b4,fr11 + + pass diff --git a/sim/testsuite/sim/frv/mdpackh.cgs b/sim/testsuite/sim/frv/mdpackh.cgs new file mode 100644 index 0000000..cbd0bc8 --- /dev/null +++ b/sim/testsuite/sim/frv/mdpackh.cgs @@ -0,0 +1,18 @@ +# frv testcase for mdpackh $FRi,$FRj,$FRj +# mach: all + + .include "testutils.inc" + + start + + .global mdpackh +mdpackh: + set_fr_iimmed 0xdead,0xbeef,fr10 + set_fr_iimmed 0xaaaa,0xbbbb,fr11 + set_fr_iimmed 0x1234,0x5678,fr12 + set_fr_iimmed 0xcccc,0xdddd,fr13 + mdpackh fr10,fr12,fr14 + test_fr_limmed 0xbeef,0x5678,fr14 + test_fr_limmed 0xbbbb,0xdddd,fr15 + + pass diff --git a/sim/testsuite/sim/frv/mdrotli.cgs b/sim/testsuite/sim/frv/mdrotli.cgs new file mode 100644 index 0000000..1d2e183 --- /dev/null +++ b/sim/testsuite/sim/frv/mdrotli.cgs @@ -0,0 +1,34 @@ +# frv testcase for mdrotli $FRi,$s6,$FRk +# mach: fr400 fr550 + + .include "testutils.inc" + + start + + .global mdrotli +mdrotli: + set_fr_iimmed 0,2,fr8 + set_fr_iimmed 0,2,fr9 + mdrotli fr8,-32,fr8 ; Shift by 0 + test_fr_iimmed 2,fr8 + test_fr_iimmed 2,fr9 + + set_fr_iimmed 0,2,fr8 + set_fr_iimmed 0,2,fr9 + mdrotli fr8,1,fr8 ; Shift by 1 + test_fr_iimmed 4,fr8 + test_fr_iimmed 4,fr9 + + set_fr_iimmed 0,1,fr8 + set_fr_iimmed 0,2,fr9 + mdrotli fr8,31,fr8 ; Shift by 31 + test_fr_iimmed 0x80000000,fr8 + test_fr_iimmed 1,fr9 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + mdrotli fr8,16,fr8 + test_fr_iimmed 0xbeefdead,fr8 + test_fr_iimmed 0xdeadbeef,fr9 + + pass diff --git a/sim/testsuite/sim/frv/mdsubaccs.cgs b/sim/testsuite/sim/frv/mdsubaccs.cgs new file mode 100644 index 0000000..73d2e2d --- /dev/null +++ b/sim/testsuite/sim/frv/mdsubaccs.cgs @@ -0,0 +1,102 @@ +# frv testcase for mdsubaccs $ACC40Si,$ACC40Sk +# mach: fr400 + + .include "testutils.inc" + + start + + .global mdsubaccs +mdsubaccs: + set_accg_immed 0,accg0 + set_acc_immed 0x00000000,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x00000000,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0xdead0000,acc2 + set_accg_immed 0,accg3 + set_acc_immed 0x0000beef,acc3 + mdsubaccs acc0,acc2 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x0000,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0xdeac,0x4111,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x0000dead,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0xbeef0000,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0x12345678,acc2 + set_accg_immed 0,accg3 + set_acc_immed 0x11111111,acc3 + mdsubaccs acc0,acc2 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg2 + test_acc_limmed 0x4111,0xdead,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0123,0x4567,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x12345678,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0xffffffff,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0x12345678,acc2 + set_accg_immed 0xff,accg3 + set_acc_immed 0xffffffff,acc3 + mdsubaccs acc0,acc2 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg2 + test_acc_limmed 0x1234,0x5679,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x1234,0x5679,acc3 + + set_spr_immed 0,msr0 + set_accg_immed 0x7f,accg0 + set_acc_immed 0xfffffffe,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xfffffffe,acc1 + set_accg_immed 0x80,accg2 + set_acc_immed 0x00000001,acc2 + set_accg_immed 0,accg3 + set_acc_immed 0x00000002,acc3 + mdsubaccs acc0,acc2 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + test_accg_immed 0x7f,accg2 + test_acc_limmed 0xffff,0xffff,acc2 + test_accg_immed 0x80,accg3 + test_acc_limmed 0x0000,0x0000,acc3 + + set_spr_immed 0,msr0 + set_accg_immed 0,accg0 + set_acc_immed 0x00000001,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x00000001,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0x00000001,acc2 + set_accg_immed 0x80,accg3 + set_acc_immed 0x00000000,acc3 + mdsubaccs acc0,acc2 + test_spr_bits 0x3c,2,4,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x0000,acc2 + test_accg_immed 0x7f,accg3 + test_acc_limmed 0xffff,0xffff,acc3 + + pass diff --git a/sim/testsuite/sim/frv/mdunpackh.cgs b/sim/testsuite/sim/frv/mdunpackh.cgs new file mode 100644 index 0000000..02870c8 --- /dev/null +++ b/sim/testsuite/sim/frv/mdunpackh.cgs @@ -0,0 +1,26 @@ +# frv testcase for mdunpackh $FRi,$FRj +# mach: frv + + .include "testutils.inc" + + start + + .global mdunpackh +mdunpackh: + set_fr_iimmed 0xdead,0xbeef,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + mdunpackh fr10,fr12 + test_fr_limmed 0xdead,0xdead,fr12 + test_fr_limmed 0xbeef,0xbeef,fr13 + test_fr_limmed 0x1234,0x1234,fr14 + test_fr_limmed 0x5678,0x5678,fr15 + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0xdead,0xbeef,fr11 + mdunpackh fr10,fr12 + test_fr_limmed 0x1234,0x1234,fr12 + test_fr_limmed 0x5678,0x5678,fr13 + test_fr_limmed 0xdead,0xdead,fr14 + test_fr_limmed 0xbeef,0xbeef,fr15 + + pass diff --git a/sim/testsuite/sim/frv/membar.cgs b/sim/testsuite/sim/frv/membar.cgs new file mode 100644 index 0000000..aae1d1a --- /dev/null +++ b/sim/testsuite/sim/frv/membar.cgs @@ -0,0 +1,12 @@ +# frv testcase for membar +# mach: all + + .include "testutils.inc" + + start + + .global membar +membar: + membar + + pass diff --git a/sim/testsuite/sim/frv/mexpdhd.cgs b/sim/testsuite/sim/frv/mexpdhd.cgs new file mode 100644 index 0000000..d5f95ce --- /dev/null +++ b/sim/testsuite/sim/frv/mexpdhd.cgs @@ -0,0 +1,27 @@ +# frv testcase for mexpdhd $FRi,$s6,$FRj +# mach: all + + .include "testutils.inc" + + start + + .global mexpdhd +mexpdhd: + set_fr_iimmed 0xdead,0xbeef,fr10 + mexpdhd fr10,0,fr12 + test_fr_limmed 0xdead,0xdead,fr12 + test_fr_limmed 0xdead,0xdead,fr13 + + mexpdhd fr10,1,fr12 + test_fr_limmed 0xbeef,0xbeef,fr12 + test_fr_limmed 0xbeef,0xbeef,fr13 + + mexpdhd fr10,62,fr12 + test_fr_limmed 0xdead,0xdead,fr12 + test_fr_limmed 0xdead,0xdead,fr13 + + mexpdhd fr10,63,fr12 + test_fr_limmed 0xbeef,0xbeef,fr12 + test_fr_limmed 0xbeef,0xbeef,fr13 + + pass diff --git a/sim/testsuite/sim/frv/mexpdhw.cgs b/sim/testsuite/sim/frv/mexpdhw.cgs new file mode 100644 index 0000000..a13b0f2 --- /dev/null +++ b/sim/testsuite/sim/frv/mexpdhw.cgs @@ -0,0 +1,23 @@ +# frv testcase for mexpdhw $FRi,$s6,$FRj +# mach: all + + .include "testutils.inc" + + start + + .global mexpdhw +mexpdhw: + set_fr_iimmed 0xdead,0xbeef,fr10 + mexpdhw fr10,0,fr12 + test_fr_limmed 0xdead,0xdead,fr12 + + mexpdhw fr10,1,fr12 + test_fr_limmed 0xbeef,0xbeef,fr12 + + mexpdhw fr10,62,fr12 + test_fr_limmed 0xdead,0xdead,fr12 + + mexpdhw fr10,63,fr12 + test_fr_limmed 0xbeef,0xbeef,fr12 + + pass diff --git a/sim/testsuite/sim/frv/mhdseth.cgs b/sim/testsuite/sim/frv/mhdseth.cgs new file mode 100644 index 0000000..7c09b2d --- /dev/null +++ b/sim/testsuite/sim/frv/mhdseth.cgs @@ -0,0 +1,26 @@ +# frv testcase for mhdseth $s5,$FRk +# mach: fr400 fr550 + + .include "testutils.inc" + + start + + .global setlo +setlo: + set_fr_iimmed 0xdead,0xbeef,fr1 + mhdseth 0,fr1 + test_fr_limmed 0x06ad,0x06ef,fr1 + + mhdseth 1,fr1 + test_fr_limmed 0x0ead,0x0eef,fr1 + + mhdseth 0xf,fr1 + test_fr_limmed 0x7ead,0x7eef,fr1 + + mhdseth -16,fr1 + test_fr_limmed 0x86ad,0x86ef,fr1 + + mhdseth -1,fr1 + test_fr_limmed 0xfead,0xfeef,fr1 + + pass diff --git a/sim/testsuite/sim/frv/mhdsets.cgs b/sim/testsuite/sim/frv/mhdsets.cgs new file mode 100644 index 0000000..1f26814 --- /dev/null +++ b/sim/testsuite/sim/frv/mhdsets.cgs @@ -0,0 +1,26 @@ +# frv testcase for mhdsets $u12,$FRk +# mach: fr400 fr550 + + .include "testutils.inc" + + start + + .global setlo +setlo: + set_fr_iimmed 0xdead,0xbeef,fr1 + mhdsets 0,fr1 + test_fr_limmed 0x0000,0x0000,fr1 + + mhdsets 1,fr1 + test_fr_limmed 0x0001,0x0001,fr1 + + mhdsets 0x07ff,fr1 + test_fr_limmed 0x07ff,0x07ff,fr1 + + mhdsets -2048,fr1 + test_fr_limmed 0xf800,0xf800,fr1 + + mhdsets -1,fr1 + test_fr_limmed 0xffff,0xffff,fr1 + + pass diff --git a/sim/testsuite/sim/frv/mhsethih.cgs b/sim/testsuite/sim/frv/mhsethih.cgs new file mode 100644 index 0000000..f05eb77 --- /dev/null +++ b/sim/testsuite/sim/frv/mhsethih.cgs @@ -0,0 +1,26 @@ +# frv testcase for mhsethih $s5,$FRk +# mach: fr400 fr550 + + .include "testutils.inc" + + start + + .global setlo +setlo: + set_fr_iimmed 0xdead,0xbeef,fr1 + mhsethih 0,fr1 + test_fr_limmed 0x06ad,0xbeef,fr1 + + mhsethih 1,fr1 + test_fr_limmed 0x0ead,0xbeef,fr1 + + mhsethih 0xf,fr1 + test_fr_limmed 0x7ead,0xbeef,fr1 + + mhsethih -16,fr1 + test_fr_limmed 0x86ad,0xbeef,fr1 + + mhsethih -1,fr1 + test_fr_limmed 0xfead,0xbeef,fr1 + + pass diff --git a/sim/testsuite/sim/frv/mhsethis.cgs b/sim/testsuite/sim/frv/mhsethis.cgs new file mode 100644 index 0000000..cf89336 --- /dev/null +++ b/sim/testsuite/sim/frv/mhsethis.cgs @@ -0,0 +1,26 @@ +# frv testcase for mhsethis $u12,$FRk +# mach: fr400 fr550 + + .include "testutils.inc" + + start + + .global setlo +setlo: + set_fr_iimmed 0xdead,0xbeef,fr1 + mhsethis 0,fr1 + test_fr_limmed 0x0000,0xbeef,fr1 + + mhsethis 1,fr1 + test_fr_limmed 0x0001,0xbeef,fr1 + + mhsethis 0x07ff,fr1 + test_fr_limmed 0x07ff,0xbeef,fr1 + + mhsethis -2048,fr1 + test_fr_limmed 0xf800,0xbeef,fr1 + + mhsethis -1,fr1 + test_fr_limmed 0xffff,0xbeef,fr1 + + pass diff --git a/sim/testsuite/sim/frv/mhsetloh.cgs b/sim/testsuite/sim/frv/mhsetloh.cgs new file mode 100644 index 0000000..930628d --- /dev/null +++ b/sim/testsuite/sim/frv/mhsetloh.cgs @@ -0,0 +1,26 @@ +# frv testcase for mhsetloh $s5,$FRk +# mach: fr400 fr550 + + .include "testutils.inc" + + start + + .global setlo +setlo: + set_fr_iimmed 0xdead,0xbeef,fr1 + mhsetloh 0,fr1 + test_fr_limmed 0xdead,0x06ef,fr1 + + mhsetloh 1,fr1 + test_fr_limmed 0xdead,0x0eef,fr1 + + mhsetloh 0xf,fr1 + test_fr_limmed 0xdead,0x7eef,fr1 + + mhsetloh -16,fr1 + test_fr_limmed 0xdead,0x86ef,fr1 + + mhsetloh -1,fr1 + test_fr_limmed 0xdead,0xfeef,fr1 + + pass diff --git a/sim/testsuite/sim/frv/mhsetlos.cgs b/sim/testsuite/sim/frv/mhsetlos.cgs new file mode 100644 index 0000000..fb404a2 --- /dev/null +++ b/sim/testsuite/sim/frv/mhsetlos.cgs @@ -0,0 +1,26 @@ +# frv testcase for mhsetlos $u12,$FRk +# mach: fr400 fr550 + + .include "testutils.inc" + + start + + .global setlo +setlo: + set_fr_iimmed 0xdead,0xbeef,fr1 + mhsetlos 0,fr1 + test_fr_limmed 0xdead,0x0000,fr1 + + mhsetlos 1,fr1 + test_fr_limmed 0xdead,0x0001,fr1 + + mhsetlos 0x07ff,fr1 + test_fr_limmed 0xdead,0x07ff,fr1 + + mhsetlos -2048,fr1 + test_fr_limmed 0xdead,0xf800,fr1 + + mhsetlos -1,fr1 + test_fr_limmed 0xdead,0xffff,fr1 + + pass diff --git a/sim/testsuite/sim/frv/mhtob.cgs b/sim/testsuite/sim/frv/mhtob.cgs new file mode 100644 index 0000000..efd83d7 --- /dev/null +++ b/sim/testsuite/sim/frv/mhtob.cgs @@ -0,0 +1,25 @@ +# frv testcase for mhtob $FRj,$FRk +# mach: all + + .include "testutils.inc" + + start + + .global mhtob +mhtob: + set_fr_iimmed 0x00ad,0x00ef,fr10 + set_fr_iimmed 0x0034,0x0078,fr11 + mhtob fr10,fr12 + test_fr_limmed 0xadef,0x3478,fr12 + + set_fr_iimmed 0xdead,0xbeef,fr10 ; saturation + set_fr_iimmed 0x1234,0x5678,fr11 + mhtob fr10,fr12 + test_fr_limmed 0xffff,0xffff,fr12 + + set_fr_iimmed 0x0134,0x0878,fr10 ; saturation + set_fr_iimmed 0x10ad,0x80ef,fr11 + mhtob fr10,fr12 + test_fr_limmed 0xffff,0xffff,fr12 + + pass diff --git a/sim/testsuite/sim/frv/mmachs.cgs b/sim/testsuite/sim/frv/mmachs.cgs new file mode 100644 index 0000000..0292161 --- /dev/null +++ b/sim/testsuite/sim/frv/mmachs.cgs @@ -0,0 +1,259 @@ +# frv testcase for mmachs $GRi,$GRj,$ACCk +# mach: frv fr500 fr400 + + .include "testutils.inc" + + start + + .global mmachs +mmachs: + ; Positive operands + set_fr_iimmed 2,3,fr7 ; multiply small numbers + set_fr_iimmed 3,2,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + + set_fr_iimmed 0,1,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,2,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 8,acc0 + test_accg_immed 0,accg1 + test_acc_immed 8,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0,0x8006,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0,0x8006,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0001,0x0006,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0001,0x0006,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x4000,0x0007,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x4000,0x0007,acc1 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x4000,0x0001,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x4000,0x0001,acc1 + + set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0xffff,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0xffff,acc1 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0xffff,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0xffff,acc1 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0xbffd,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0xbffd,acc1 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0x3ffd,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0x3ffd,acc1 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xbffd,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xbffd,acc1 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xc003,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xc003,acc1 + + set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xc005,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xc005,acc1 + + set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0x3ffec006,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3ffec006,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0x7ffec006,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x7ffec006,acc1 + + set_accg_immed 0x7f,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0x7f,accg1 + set_acc_immed 0xffffffff,acc1 + set_fr_iimmed 1,1,fr7 + set_fr_iimmed 1,1,fr8 + mmachs fr7,fr8,acc0 + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + + set_accg_immed 0x80,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed 0x80,accg1 + set_acc_immed 0,acc1 + set_fr_iimmed 0xffff,0,fr7 + set_fr_iimmed 1,0xffff,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x80,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x0000,0x8000,fr7 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr8 + mmachs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x80,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + + pass + + diff --git a/sim/testsuite/sim/frv/mmachu.cgs b/sim/testsuite/sim/frv/mmachu.cgs new file mode 100644 index 0000000..aad07c7 --- /dev/null +++ b/sim/testsuite/sim/frv/mmachu.cgs @@ -0,0 +1,146 @@ +# frv testcase for mmachu $GRi,$GRj,$GRk +# mach: frv fr500 fr400 + + .include "testutils.inc" + + start + + .global mmachu +mmachu: + set_fr_iimmed 3,2,fr7 ; multiply small numbers + set_fr_iimmed 2,3,fr8 + mmachu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 2,1,fr8 + mmachu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 8,acc0 + test_accg_immed 0,accg1 + test_acc_immed 8,acc1 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + mmachu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 8,acc0 + test_accg_immed 0,accg1 + test_acc_immed 8,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + mmachu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8006,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8006,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + mmachu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0001,0x0006,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0001,0x0006,acc1 + + set_fr_iimmed 0x8000,2,fr7 ; 17 bit result + set_fr_iimmed 2,0x8000,fr8 + mmachu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0x00020006,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x00020006,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + mmachu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0x40010007,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x40010007,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + mmachu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x8001,0x0007,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x8001,0x0007,acc1 + + set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + mmachu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 1,accg0 + test_acc_limmed 0x7fff,0x0008,acc0 + test_accg_immed 1,accg1 + test_acc_limmed 0x7fff,0x0008,acc1 + + set_accg_immed 0xff,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xffffffff,acc1 + set_fr_iimmed 1,1,fr7 + set_fr_iimmed 1,1,fr8 + mmachu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + + set_fr_iimmed 0xffff,0x0000,fr7 + set_fr_iimmed 0xffff,0xffff,fr8 + mmachu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + + pass diff --git a/sim/testsuite/sim/frv/mmrdhs.cgs b/sim/testsuite/sim/frv/mmrdhs.cgs new file mode 100644 index 0000000..6295bc1 --- /dev/null +++ b/sim/testsuite/sim/frv/mmrdhs.cgs @@ -0,0 +1,263 @@ +# frv testcase for mmrdhs $GRi,$GRj,$ACCk +# mach: frv fr500 fr400 + + .include "testutils.inc" + + start + + .global mmrdhs +mmrdhs: + ; Positive operands + set_fr_iimmed 2,3,fr7 ; multiply small numbers + set_fr_iimmed 3,2,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 + test_acc_immed -6,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed -6,acc1 + + set_fr_iimmed 0,1,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 + test_acc_immed -6,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed -6,acc1 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,2,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 + test_acc_immed -8,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed -8,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0x7ffa,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0x7ffa,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xfffe,0xfffa,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xfffe,0xfffa,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xbfff,0xfff9,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xbfff,0xfff9,acc1 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xbfff,0xffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xbfff,0xffff,acc1 + + set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xc000,0x0001,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xc000,0x0001,acc1 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xc000,0x0001,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xc000,0x0001,acc1 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xc000,0x4003,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xc000,0x4003,acc1 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xc000,0xc003,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xc000,0xc003,acc1 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x4003,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x4003,acc1 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x3ffd,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x3ffd,acc1 + + set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x3ffb,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x3ffb,acc1 + + set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 + test_acc_immed 0xc0013ffa,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed 0xc0013ffa,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg0 + test_acc_immed 0x80013ffa,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed 0x80013ffa,acc1 + + set_accg_immed 0x7f,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0x7f,accg1 + set_acc_immed 0xffffffff,acc1 + set_fr_iimmed 0xffff,1,fr7 + set_fr_iimmed 1,0xffff,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + + set_fr_iimmed 0x8000,0x0000,fr7 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + + set_accg_immed 0x80,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed 0x80,accg1 + set_acc_immed 0,acc1 + set_fr_iimmed 0,1,fr7 + set_fr_iimmed 1,1,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x80,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr8 + mmrdhs fr7,fr8,acc0 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x80,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + + pass + + diff --git a/sim/testsuite/sim/frv/mmrdhu.cgs b/sim/testsuite/sim/frv/mmrdhu.cgs new file mode 100644 index 0000000..b1c0243 --- /dev/null +++ b/sim/testsuite/sim/frv/mmrdhu.cgs @@ -0,0 +1,151 @@ +# frv testcase for mmrdhu $GRi,$GRj,$GRk +# mach: frv fr500 fr400 + + .include "testutils.inc" + + start + + .global mmrdhu +mmrdhu: + set_accg_immed 0x80,accg0 + set_acc_immed 0,acc0 + set_accg_immed 0x80,accg1 + set_acc_immed 0,acc1 + + set_fr_iimmed 3,2,fr7 ; multiply small numbers + set_fr_iimmed 2,3,fr8 + mmrdhu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x7f,accg0 + test_acc_immed 0xfffffffa,acc0 + test_accg_immed 0x7f,accg1 + test_acc_immed 0xfffffffa,acc1 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 2,1,fr8 + mmrdhu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x7f,accg0 + test_acc_immed 0xfffffff8,acc0 + test_accg_immed 0x7f,accg1 + test_acc_immed 0xfffffff8,acc1 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + mmrdhu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x7f,accg0 + test_acc_immed 0xfffffff8,acc0 + test_accg_immed 0x7f,accg1 + test_acc_immed 0xfffffff8,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + mmrdhu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xffff,0x7ffa,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xffff,0x7ffa,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + mmrdhu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xfffe,0xfffa,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xfffe,0xfffa,acc1 + + set_fr_iimmed 0x8000,2,fr7 ; 17 bit result + set_fr_iimmed 2,0x8000,fr8 + mmrdhu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xfffd,0xfffa,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xfffd,0xfffa,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + mmrdhu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xbffe,0xfff9,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xbffe,0xfff9,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + mmrdhu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x7f,accg0 + test_acc_limmed 0x7ffe,0xfff9,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0x7ffe,0xfff9,acc1 + + set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + mmrdhu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0x7e,accg0 + test_acc_limmed 0x8000,0xfff8,acc0 + test_accg_immed 0x7e,accg1 + test_acc_limmed 0x8000,0xfff8,acc1 + + set_accg_immed 0,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0,acc1 + set_fr_iimmed 1,1,fr7 + set_fr_iimmed 1,1,fr8 + mmrdhu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x0000,0xffff,fr7 + set_fr_iimmed 0xffff,0xffff,fr8 + mmrdhu fr7,fr8,acc0 + test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + pass diff --git a/sim/testsuite/sim/frv/mmulhs.cgs b/sim/testsuite/sim/frv/mmulhs.cgs new file mode 100644 index 0000000..2104500 --- /dev/null +++ b/sim/testsuite/sim/frv/mmulhs.cgs @@ -0,0 +1,141 @@ +# frv testcase for mmulhs $GRi,$GRj,$ACCk +# mach: all + + .include "testutils.inc" + + start + + .global mmulhs +mmulhs: + ; Positive operands + set_fr_iimmed 2,3,fr7 ; multiply small numbers + set_fr_iimmed 3,2,fr8 + mmulhs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + + set_fr_iimmed 0,1,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + mmulhs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 1,2,fr8 + mmulhs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 2,acc0 + test_accg_immed 0,accg1 + test_acc_immed 2,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + mmulhs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0,0x7ffe,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0,0x7ffe,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + mmulhs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8000,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8000,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + mmulhs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0x0001,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0x0001,acc1 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr8 + mmulhs fr7,fr8,acc0 + test_accg_immed 0xff,accg0 + test_acc_immed -6,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed -6,acc1 + + set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr8 + mmulhs fr7,fr8,acc0 + test_accg_immed 0xff,accg0 + test_acc_immed -2,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed -2,acc1 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr8 + mmulhs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr8 + mmulhs fr7,fr8,acc0 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xbffe,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xbffe,acc1 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr8 + mmulhs fr7,fr8,acc0 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0x8000,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0x8000,acc1 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr8 + mmulhs fr7,fr8,acc0 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xc000,0x8000,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xc000,0x8000,acc1 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr8 + mmulhs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + + set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr8 + mmulhs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 2,acc0 + test_accg_immed 0,accg1 + test_acc_immed 2,acc1 + + set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr8 + mmulhs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fff0001,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + mmulhs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0x40000000,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x40000000,acc1 + + pass diff --git a/sim/testsuite/sim/frv/mmulhu.cgs b/sim/testsuite/sim/frv/mmulhu.cgs new file mode 100644 index 0000000..53e9b70 --- /dev/null +++ b/sim/testsuite/sim/frv/mmulhu.cgs @@ -0,0 +1,82 @@ +# frv testcase for mmulhu $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global mmulhu +mmulhu: + set_fr_iimmed 3,2,fr7 ; multiply small numbers + set_fr_iimmed 2,3,fr8 + mmulhu fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 2,1,fr8 + mmulhu fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 2,acc0 + test_accg_immed 0,accg1 + test_acc_immed 2,acc1 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 2,0,fr8 + mmulhu fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr8 + mmulhu fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x7ffe,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x7ffe,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 2,0x4000,fr8 + mmulhu fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8000,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8000,acc1 + + set_fr_iimmed 0x8000,2,fr7 ; 17 bit result + set_fr_iimmed 2,0x8000,fr8 + mmulhu fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0x00010000,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x00010000,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + mmulhu fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fff0001,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + mmulhu fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0x4000,0x0000,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x4000,0x0000,acc1 + + set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + mmulhu fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0xfffe,0x0001,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0xfffe,0x0001,acc1 + + pass diff --git a/sim/testsuite/sim/frv/mmulxhs.cgs b/sim/testsuite/sim/frv/mmulxhs.cgs new file mode 100644 index 0000000..449becf --- /dev/null +++ b/sim/testsuite/sim/frv/mmulxhs.cgs @@ -0,0 +1,141 @@ +# frv testcase for mmulxhs $GRi,$GRj,$ACCk +# mach: all + + .include "testutils.inc" + + start + + .global mmulxhs +mmulxhs: + ; Positive operands + set_fr_iimmed 2,3,fr7 ; multiply small numbers + set_fr_iimmed 3,2,fr8 + mmulxhs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 4,acc0 + test_accg_immed 0,accg1 + test_acc_immed 9,acc1 + + set_fr_iimmed 0,1,fr7 ; multiply by 0 + set_fr_iimmed 0,2,fr8 + mmulxhs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 2,1,fr7 ; multiply by 1 + set_fr_iimmed 2,1,fr8 + mmulxhs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 2,acc0 + test_accg_immed 0,accg1 + test_acc_immed 2,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 0x3fff,2,fr8 + mmulxhs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0,0x7ffe,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0,0x7ffe,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 0x4000,2,fr8 + mmulxhs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8000,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8000,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + mmulxhs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0x0001,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0x0001,acc1 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 2,0xfffd,fr8 + mmulxhs fr7,fr8,acc0 + test_accg_immed 0xff,accg0 + test_acc_immed -6,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed -6,acc1 + + set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 + set_fr_iimmed 0xfffe,1,fr8 + mmulxhs fr7,fr8,acc0 + test_accg_immed 0xff,accg0 + test_acc_immed -2,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed -2,acc1 + + set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 + set_fr_iimmed 0xfffe,0,fr8 + mmulxhs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result + set_fr_iimmed 0x2001,0xfffe,fr8 + mmulxhs fr7,fr8,acc0 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xbffe,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xbffe,acc1 + + set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result + set_fr_iimmed 0x4000,0xfffe,fr8 + mmulxhs fr7,fr8,acc0 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0x8000,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0x8000,acc1 + + set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result + set_fr_iimmed 0x7fff,0x8000,fr8 + mmulxhs fr7,fr8,acc0 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xc000,0x8000,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xc000,0x8000,acc1 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers + set_fr_iimmed 0xfffe,0xfffd,fr8 + mmulxhs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + + set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 + set_fr_iimmed 0xffff,0xfffe,fr8 + mmulxhs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 2,acc0 + test_accg_immed 0,accg1 + test_acc_immed 2,acc1 + + set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr8 + mmulxhs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fff0001,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + mmulxhs fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0x40000000,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x40000000,acc1 + + pass diff --git a/sim/testsuite/sim/frv/mmulxhu.cgs b/sim/testsuite/sim/frv/mmulxhu.cgs new file mode 100644 index 0000000..866b64e --- /dev/null +++ b/sim/testsuite/sim/frv/mmulxhu.cgs @@ -0,0 +1,82 @@ +# frv testcase for mmulxhu $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global mmulxhu +mmulxhu: + set_fr_iimmed 3,2,fr7 ; multiply small numbers + set_fr_iimmed 3,2,fr8 + mmulxhu fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + + set_fr_iimmed 1,2,fr7 ; multiply by 1 + set_fr_iimmed 1,2,fr8 + mmulxhu fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 2,acc0 + test_accg_immed 0,accg1 + test_acc_immed 2,acc1 + + set_fr_iimmed 0,2,fr7 ; multiply by 0 + set_fr_iimmed 0,2,fr8 + mmulxhu fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result + set_fr_iimmed 0x3fff,2,fr8 + mmulxhu fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x7ffe,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x7ffe,acc1 + + set_fr_iimmed 0x4000,2,fr7 ; 16 bit result + set_fr_iimmed 0x4000,2,fr8 + mmulxhu fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8000,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8000,acc1 + + set_fr_iimmed 0x8000,2,fr7 ; 17 bit result + set_fr_iimmed 0x8000,2,fr8 + mmulxhu fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0x00010000,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x00010000,acc1 + + set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr8 + mmulxhu fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fff0001,acc1 + + set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr8 + mmulxhu fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0x4000,0x0000,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x4000,0x0000,acc1 + + set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr8 + mmulxhu fr7,fr8,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0xfffe,0x0001,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0xfffe,0x0001,acc1 + + pass diff --git a/sim/testsuite/sim/frv/mnop.cgs b/sim/testsuite/sim/frv/mnop.cgs new file mode 100644 index 0000000..54dda66 --- /dev/null +++ b/sim/testsuite/sim/frv/mnop.cgs @@ -0,0 +1,12 @@ +# frv testcase for mnop +# mach: all + + .include "testutils.inc" + + start + + .global mnop +mnop: + mnop + + pass diff --git a/sim/testsuite/sim/frv/mnot.cgs b/sim/testsuite/sim/frv/mnot.cgs new file mode 100644 index 0000000..3a90781 --- /dev/null +++ b/sim/testsuite/sim/frv/mnot.cgs @@ -0,0 +1,18 @@ +# frv testcase for mnot $FRintj,$FRintk +# mach: all + + .include "testutils.inc" + + start + + .global mnot +mnot: + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + mnot fr7,fr7 + test_fr_iimmed 0x55555555,fr7 + + set_fr_iimmed 0xdead,0xbeef,fr7 + mnot fr7,fr7 + test_fr_iimmed 0x21524110,fr7 + + pass diff --git a/sim/testsuite/sim/frv/mor.cgs b/sim/testsuite/sim/frv/mor.cgs new file mode 100644 index 0000000..72feaff --- /dev/null +++ b/sim/testsuite/sim/frv/mor.cgs @@ -0,0 +1,25 @@ +# frv testcase for mor $FRinti,$FRintj,$FRintk +# mach: all + + .include "testutils.inc" + + start + + .global mor +mor: + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + set_fr_iimmed 0x5555,0x5555,fr8 + mor fr7,fr8,fr8 + test_fr_iimmed 0xffffffff,fr8 + + set_fr_iimmed 0x0000,0x0000,fr7 + set_fr_iimmed 0x0000,0x0000,fr8 + mor fr7,fr8,fr8 + test_fr_iimmed 0x00000000,fr8 + + set_fr_iimmed 0xdead,0x0000,fr7 + set_fr_iimmed 0x0000,0xbeef,fr8 + mor fr7,fr8,fr8 + test_fr_iimmed 0xdeadbeef,fr8 + + pass diff --git a/sim/testsuite/sim/frv/mov.cgs b/sim/testsuite/sim/frv/mov.cgs new file mode 100644 index 0000000..8a077eb --- /dev/null +++ b/sim/testsuite/sim/frv/mov.cgs @@ -0,0 +1,18 @@ +# frv testcase for mov $GRi,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global ori +ori: + set_gr_immed 0xdeadbeef,gr7 + set_gr_immed 0xbeefdead,gr8 + set_icc 0x08,0 + mov gr7,gr8 + test_icc 1 0 0 0 icc0 + test_gr_immed 0xdeadbeef,gr7 + test_gr_immed 0xdeadbeef,gr8 + + pass diff --git a/sim/testsuite/sim/frv/movfg.cgs b/sim/testsuite/sim/frv/movfg.cgs new file mode 100644 index 0000000..c3da00e --- /dev/null +++ b/sim/testsuite/sim/frv/movfg.cgs @@ -0,0 +1,16 @@ +# frv testcase for movfg $FRk,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global movfg +movfg: + set_fr_iimmed 0xdead,0xbeef,fr8 + set_gr_limmed 0,0,gr8 + movfg fr8,gr8 + test_gr_limmed 0xdead,0xbeef,gr8 + test_fr_limmed 0xdead,0xbeef,fr8 + + pass diff --git a/sim/testsuite/sim/frv/movfgd.cgs b/sim/testsuite/sim/frv/movfgd.cgs new file mode 100644 index 0000000..cc2d60d --- /dev/null +++ b/sim/testsuite/sim/frv/movfgd.cgs @@ -0,0 +1,20 @@ +# frv testcase for movfgd $FRk,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global movfgd +movfgd: + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_gr_limmed 0,0,gr8 + set_gr_limmed 0,0,gr9 + movfgd fr8,gr8 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + + pass diff --git a/sim/testsuite/sim/frv/movfgq.cgs b/sim/testsuite/sim/frv/movfgq.cgs new file mode 100644 index 0000000..b3a90e8 --- /dev/null +++ b/sim/testsuite/sim/frv/movfgq.cgs @@ -0,0 +1,29 @@ +# frv testcase for movfgq $FRk,$GRj +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global movfgq +movfgq: + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x9abc,0xdef0,fr11 + set_gr_limmed 0,0,gr8 + set_gr_limmed 0,0,gr9 + set_gr_limmed 0,0,gr10 + set_gr_limmed 0,0,gr11 + movfgq fr8,gr8 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_limmed 0x1234,0x5678,gr10 + test_gr_limmed 0x9abc,0xdef0,gr11 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + test_fr_limmed 0x1234,0x5678,fr10 + test_fr_limmed 0x9abc,0xdef0,fr11 + + pass diff --git a/sim/testsuite/sim/frv/movgf.cgs b/sim/testsuite/sim/frv/movgf.cgs new file mode 100644 index 0000000..40fae33 --- /dev/null +++ b/sim/testsuite/sim/frv/movgf.cgs @@ -0,0 +1,16 @@ +# frv testcase for movgf $GRj,$FRk +# mach: all + + .include "testutils.inc" + + start + + .global movgf +movgf: + set_gr_limmed 0xdead,0xbeef,gr8 + set_fr_iimmed 0,0,fr8 + movgf gr8,fr8 + test_gr_limmed 0xdead,0xbeef,gr8 + test_fr_limmed 0xdead,0xbeef,fr8 + + pass diff --git a/sim/testsuite/sim/frv/movgfd.cgs b/sim/testsuite/sim/frv/movgfd.cgs new file mode 100644 index 0000000..df844cc --- /dev/null +++ b/sim/testsuite/sim/frv/movgfd.cgs @@ -0,0 +1,20 @@ +# frv testcase for movgfd $GRj,$FRk +# mach: all + + .include "testutils.inc" + + start + + .global movgfd +movgfd: + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_fr_iimmed 0,0,fr8 + set_fr_iimmed 0,0,fr9 + movgfd gr8,fr8 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + + pass diff --git a/sim/testsuite/sim/frv/movgfq.cgs b/sim/testsuite/sim/frv/movgfq.cgs new file mode 100644 index 0000000..0196133 --- /dev/null +++ b/sim/testsuite/sim/frv/movgfq.cgs @@ -0,0 +1,29 @@ +# frv testcase for movgfq $GRj,$FRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global movgfq +movgfq: + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + set_fr_iimmed 0,0,fr8 + set_fr_iimmed 0,0,fr9 + set_fr_iimmed 0,0,fr10 + set_fr_iimmed 0,0,fr11 + movgfq gr8,fr8 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_limmed 0xbeef,0xdead,gr9 + test_gr_limmed 0x1234,0x5678,gr10 + test_gr_limmed 0x9abc,0xdef0,gr11 + test_fr_limmed 0xdead,0xbeef,fr8 + test_fr_limmed 0xbeef,0xdead,fr9 + test_fr_limmed 0x1234,0x5678,fr10 + test_fr_limmed 0x9abc,0xdef0,fr11 + + pass diff --git a/sim/testsuite/sim/frv/movgs.cgs b/sim/testsuite/sim/frv/movgs.cgs new file mode 100644 index 0000000..f9d2f54 --- /dev/null +++ b/sim/testsuite/sim/frv/movgs.cgs @@ -0,0 +1,22 @@ +# frv testcase for movgs $GRj,$FRk +# mach: all + + .include "testutils.inc" + + start + + .global movgs +movgs: + set_gr_limmed 0xdead,0xbeef,gr8 + and_spr_immed 0,lcr + movgs gr8,lcr + test_gr_limmed 0xdead,0xbeef,gr8 + test_spr_limmed 0xdead,0xbeef,lcr + + ; try alternate names for lcr + and_spr_immed 0,273 + movgs gr8,spr[273] ; lcr is spr number 273 + test_gr_limmed 0xdead,0xbeef,gr8 + test_spr_limmed 0xdead,0xbeef,spr[273] + + pass diff --git a/sim/testsuite/sim/frv/movsg.cgs b/sim/testsuite/sim/frv/movsg.cgs new file mode 100644 index 0000000..b26dbc1 --- /dev/null +++ b/sim/testsuite/sim/frv/movsg.cgs @@ -0,0 +1,16 @@ +# frv testcase for movsg $FRk,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global movsg +movsg: + set_spr_limmed 0xdead,0xbeef,lcr + set_gr_limmed 0,0,gr8 + movsg lcr,gr8 + test_gr_limmed 0xdead,0xbeef,gr8 + test_spr_limmed 0xdead,0xbeef,lcr + + pass diff --git a/sim/testsuite/sim/frv/mpackh.cgs b/sim/testsuite/sim/frv/mpackh.cgs new file mode 100644 index 0000000..5a87cc6 --- /dev/null +++ b/sim/testsuite/sim/frv/mpackh.cgs @@ -0,0 +1,15 @@ +# frv testcase for mpackh $FRi,$FRj,$FRj +# mach: all + + .include "testutils.inc" + + start + + .global mpackh +mpackh: + set_fr_iimmed 0xdead,0xbeef,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + mpackh fr10,fr11,fr12 + test_fr_limmed 0xbeef,0x5678,fr12 + + pass diff --git a/sim/testsuite/sim/frv/mqcpxis.cgs b/sim/testsuite/sim/frv/mqcpxis.cgs new file mode 100644 index 0000000..397f533 --- /dev/null +++ b/sim/testsuite/sim/frv/mqcpxis.cgs @@ -0,0 +1,103 @@ +# frv testcase for mqcpxis $GRi,$GRj,$ACCk +# mach: all + + .include "testutils.inc" + + start + + .global mqcpxis +mqcpxis: + ; Positive operands + set_fr_iimmed 2,4,fr8 ; multiply small numbers + set_fr_iimmed 5,3,fr10 + set_fr_iimmed 3,1,fr9 ; multiply by 0 + set_fr_iimmed 0,2,fr11 + mqcpxis fr8,fr10,acc0 + test_accg_immed 0x00,accg0 + test_acc_immed 26,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + + set_fr_iimmed 2,1,fr8 ; multiply by 1 + set_fr_iimmed 1,1,fr10 + set_fr_iimmed 0x3fff,1,fr9 ; 15 bit result + set_fr_iimmed 0x0001,2,fr11 + mqcpxis fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_immed 3,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0,0x7fff,acc1 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 0x2000,2,fr10 + set_fr_iimmed 0x7fff,0x0000,fr9 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr11 + mqcpxis fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0xc000,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0x0001,acc1 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 1,0xfffd,fr10 + set_fr_iimmed 0xfffe,2,fr9 ; multiply by 1 + set_fr_iimmed 0xfffe,1,fr11 + mqcpxis fr8,fr10,acc0 + test_accg_immed 0xff,accg0 + test_acc_immed -9,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed -6,acc1 + + set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 + set_fr_iimmed 0xfffe,1,fr10 + set_fr_iimmed 0x2001,0xffff,fr9 ; 15 bit result + set_fr_iimmed 0xffff,0xfffe,fr11 + mqcpxis fr8,fr10,acc0 + test_accg_immed 0xff,accg0 + test_acc_immed -2,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xbfff,acc1 + + set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result + set_fr_iimmed 0x0003,0xfffe,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; max negative result + set_fr_iimmed 0x8000,0x8000,fr11 + mqcpxis fr8,fr10,acc0 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0x7ffa,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0x8001,0x0000,acc1 + + ; Negative operands + set_fr_iimmed 0x8000,0x8000,fr8 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr10 + set_fr_iimmed 0xfffe,0xfffc,fr9 ; multiply small numbers + set_fr_iimmed 0xfffb,0xfffd,fr11 + mqcpxis fr8,fr10,acc0 + test_accg_immed 0x00,accg0 + test_acc_limmed 0x8000,0x0000,acc0 + test_accg_immed 0x00,accg1 + test_acc_immed 26,acc1 + + set_fr_iimmed 0xffff,0xffff,fr8 ; multiply by -1 + set_fr_iimmed 0xffff,0xfffe,fr10 + set_fr_iimmed 0x7fff,0x0000,fr9 ; almost max positive result + set_fr_iimmed 0x8001,0x7fff,fr11 + mqcpxis fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_immed 3,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fff0001,acc1 + + set_fr_iimmed 0x8000,0x0000,fr8 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr10 + set_fr_iimmed 0x8000,0x0000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + mqcpxis fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0x40000000,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x40000000,acc1 + + pass diff --git a/sim/testsuite/sim/frv/mqcpxiu.cgs b/sim/testsuite/sim/frv/mqcpxiu.cgs new file mode 100644 index 0000000..22d48f6 --- /dev/null +++ b/sim/testsuite/sim/frv/mqcpxiu.cgs @@ -0,0 +1,60 @@ +# frv testcase for mqcpxiu $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global mqcpxiu +mqcpxiu: + set_fr_iimmed 4,2,fr8 ; multiply small numbers + set_fr_iimmed 3,5,fr10 + set_fr_iimmed 1,2,fr9 ; multiply by 1 + set_fr_iimmed 1,3,fr11 + mqcpxiu fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_immed 26,acc0 + test_accg_immed 0,accg1 + test_acc_immed 5,acc1 + + set_fr_iimmed 0,2,fr8 ; multiply by 0 + set_fr_iimmed 0,2,fr10 + set_fr_iimmed 0x3fff,1,fr9 ; 15 bit result + set_fr_iimmed 0x0001,2,fr11 + mqcpxiu fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x7fff,acc1 + + set_fr_iimmed 0x4000,1,fr8 ; 16 bit result + set_fr_iimmed 0x0001,2,fr10 + set_fr_iimmed 0x4000,1,fr9 ; 17 bit result + set_fr_iimmed 0x0001,4,fr11 + mqcpxiu fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8001,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x0010001,acc1 + + set_fr_iimmed 0x7fff,0x0000,fr8 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x0000,0x8000,fr11 + mqcpxiu fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x4000,0x0000,acc1 + + set_fr_iimmed 0xffff,0x0000,fr8 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr11 + mqcpxiu fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0xfffe,0x0001,acc0 + test_accg_immed 1,accg1 + test_acc_immed 0xfffc0002,acc1 + + pass diff --git a/sim/testsuite/sim/frv/mqcpxrs.cgs b/sim/testsuite/sim/frv/mqcpxrs.cgs new file mode 100644 index 0000000..d1d1f48 --- /dev/null +++ b/sim/testsuite/sim/frv/mqcpxrs.cgs @@ -0,0 +1,103 @@ +# frv testcase for mqcpxrs $GRi,$GRj,$ACCk +# mach: all + + .include "testutils.inc" + + start + + .global mqcpxrs +mqcpxrs: + ; Positive operands + set_fr_iimmed 2,4,fr8 ; multiply small numbers + set_fr_iimmed 3,5,fr10 + set_fr_iimmed 3,1,fr9 ; multiply by 0 + set_fr_iimmed 2,0,fr11 + mqcpxrs fr8,fr10,acc0 + test_accg_immed 0xff,accg0 + test_acc_immed -14,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + + set_fr_iimmed 2,1,fr8 ; multiply by 1 + set_fr_iimmed 1,1,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x0007,fr11 + mqcpxrs fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_immed 1,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0,0x7ff0,acc1 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x2000,fr10 + set_fr_iimmed 0x7fff,0x0000,fr9 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr11 + mqcpxrs fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x4000,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0x0001,acc1 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,1,fr10 + set_fr_iimmed 0xfffe,2,fr9 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr11 + mqcpxrs fr8,fr10,acc0 + test_accg_immed 0xff,accg0 + test_acc_immed -3,acc0 + test_accg_immed 0,accg1 + test_acc_immed 2,acc1 + + set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 + set_fr_iimmed 1,0xfffe,fr10 + set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result + set_fr_iimmed 0xfffe,0xfff9,fr11 + mqcpxrs fr8,fr10,acc0 + test_accg_immed 0xff,accg0 + test_acc_immed -2,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xbff0,acc1 + + set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result + set_fr_iimmed 0xfffe,0x0003,fr10 + set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result + set_fr_iimmed 0x8000,0x8000,fr11 + mqcpxrs fr8,fr10,acc0 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0x8006,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0x8000,0x8000,acc1 + + ; Negative operands + set_fr_iimmed 0x8000,0x7fff,fr8 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr10 + set_fr_iimmed 0xfffe,0xfffc,fr9 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffb,fr11 + mqcpxrs fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0x7fff,0x8000,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed -14,acc1 + + set_fr_iimmed 0xffff,0xffff,fr8 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr10 + set_fr_iimmed 0x7fff,0x0000,fr9 ; almost max positive result + set_fr_iimmed 0x7fff,0x8001,fr11 + mqcpxrs fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_immed 1,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fff0001,acc1 + + set_fr_iimmed 0x8000,0x0000,fr8 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr10 + set_fr_iimmed 0x8000,0x0000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + mqcpxrs fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0x40000000,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x40000000,acc1 + + pass diff --git a/sim/testsuite/sim/frv/mqcpxru.cgs b/sim/testsuite/sim/frv/mqcpxru.cgs new file mode 100644 index 0000000..45e1b35 --- /dev/null +++ b/sim/testsuite/sim/frv/mqcpxru.cgs @@ -0,0 +1,78 @@ +# frv testcase for mqcpxru $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global mqcpxru +mqcpxru: + set_fr_iimmed 4,2,fr8 ; multiply small numbers + set_fr_iimmed 5,3,fr10 + set_fr_iimmed 1,2,fr9 ; multiply by 1 + set_fr_iimmed 3,1,fr11 + mqcpxru fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_immed 14,acc0 + test_accg_immed 0,accg1 + test_acc_immed 1,acc1 + + set_fr_iimmed 0,2,fr8 ; multiply by 0 + set_fr_iimmed 2,0,fr10 + set_fr_iimmed 0x3fff,1,fr9 ; 15 bit result + set_fr_iimmed 2,0x0001,fr11 + mqcpxru fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x7ffd,acc1 + + set_fr_iimmed 0x4000,1,fr8 ; 16 bit result + set_fr_iimmed 4,0x0001,fr10 + set_fr_iimmed 0x8000,1,fr9 ; 17 bit result + set_fr_iimmed 4,0x0001,fr11 + mqcpxru fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0xffff,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x0001ffff,acc1 + + set_fr_iimmed 0x7fff,0x0000,fr8 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x0000,fr11 + mqcpxru fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x4000,0x0000,acc1 + + set_fr_iimmed 0xffff,0x0000,fr8 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0x0000,0x0001,fr9 ; saturation + set_fr_iimmed 0xffff,0x0001,fr11 + mqcpxru fr8,fr10,acc0 + test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0,accg0 + test_acc_limmed 0xfffe,0x0001,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + set_fr_iimmed 0x0000,0xffff,fr8 ; saturation + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0xfffe,0xffff,fr9 ; saturation + set_fr_iimmed 0xffff,0xffff,fr11 + mqcpxru fr8,fr10,acc0 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + + pass diff --git a/sim/testsuite/sim/frv/mqmachs.cgs b/sim/testsuite/sim/frv/mqmachs.cgs new file mode 100644 index 0000000..5608c64 --- /dev/null +++ b/sim/testsuite/sim/frv/mqmachs.cgs @@ -0,0 +1,211 @@ +# frv testcase for mqmachs $GRi,$GRj,$ACCk +# mach: frv fr500 fr400 + + .include "testutils.inc" + + start + + .global mqmachs +mqmachs: + ; Positive operands + set_fr_iimmed 2,3,fr8 ; multiply small numbers + set_fr_iimmed 3,2,fr10 + set_fr_iimmed 0,1,fr9 ; multiply by 0 + set_fr_iimmed 2,0,fr11 + mqmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0,acc3 + + set_fr_iimmed 2,1,fr8 ; multiply by 1 + set_fr_iimmed 1,2,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + mqmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 8,acc0 + test_accg_immed 0,accg1 + test_acc_immed 8,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0,0x7ffe,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0,0x7ffe,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr11 + mqmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8008,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8008,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x3fff,0x7fff,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x3fff,0x7fff,acc3 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr10 + set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr11 + mqmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8002,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8002,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x3fff,0x7ffd,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x3fff,0x7ffd,acc3 + + set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr10 + set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr11 + mqmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8002,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8002,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x3fff,0x3ffb,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x3fff,0x3ffb,acc3 + + set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr10 + set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr11 + mqmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x0002,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x0002,acc1 + test_accg_immed 0xff,accg2 + test_acc_limmed 0xffff,0xbffb,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0xffff,0xbffb,acc3 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr10 + set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr11 + mqmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x0008,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x0008,acc1 + test_accg_immed 0xff,accg2 + test_acc_limmed 0xffff,0xbffd,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0xffff,0xbffd,acc3 + + set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + mqmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0009,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fff0009,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0x3fffbffd,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0x3fffbffd,acc3 + + set_accg_immed 0x7f,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0x7f,accg1 + set_acc_immed 0xffffffff,acc1 + set_accg_immed 0x7f,accg2 ; saturation + set_acc_immed 0xffffffff,acc2 + set_accg_immed 0x7f,accg3 + set_acc_immed 0xffffffff,acc3 + set_fr_iimmed 1,1,fr8 + set_fr_iimmed 1,1,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + mqmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + test_accg_immed 0x7f,accg2 + test_acc_limmed 0xffff,0xffff,acc2 + test_accg_immed 0x7f,accg3 + test_acc_limmed 0xffff,0xffff,acc3 + + set_accg_immed 0x80,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed 0x80,accg1 + set_acc_immed 0,acc1 + set_accg_immed 0x80,accg2 ; saturation + set_acc_immed 0,acc2 + set_accg_immed 0x80,accg3 + set_acc_immed 0,acc3 + set_fr_iimmed 0xffff,0,fr8 + set_fr_iimmed 1,0xffff,fr10 + set_fr_iimmed 0x0000,0x8000,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + mqmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x80,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + test_accg_immed 0x80,accg2 + test_acc_immed 0,acc2 + test_accg_immed 0x80,accg3 + test_acc_immed 0,acc3 + + pass + + diff --git a/sim/testsuite/sim/frv/mqmachu.cgs b/sim/testsuite/sim/frv/mqmachu.cgs new file mode 100644 index 0000000..e16be68 --- /dev/null +++ b/sim/testsuite/sim/frv/mqmachu.cgs @@ -0,0 +1,144 @@ +# frv testcase for mqmachu $GRi,$GRj,$GRk +# mach: frv fr500 fr400 + + .include "testutils.inc" + + start + + .global mqmachu +mqmachu: + set_fr_iimmed 3,2,fr8 ; multiply small numbers + set_fr_iimmed 2,3,fr10 + set_fr_iimmed 1,2,fr9 ; multiply by 1 + set_fr_iimmed 2,1,fr11 + mqmachu fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + test_accg_immed 0,accg2 + test_acc_immed 2,acc2 + test_accg_immed 0,accg3 + test_acc_immed 2,acc3 + + set_fr_iimmed 0,2,fr8 ; multiply by 0 + set_fr_iimmed 2,0,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + mqmachu fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x8000,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x8000,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x8000,2,fr9 ; 17 bit result + set_fr_iimmed 2,0x8000,fr11 + mqmachu fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8006,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8006,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0x00018000,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0x00018000,acc3 + + set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + mqmachu fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0x3fff8007,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fff8007,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x4001,0x8000,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x4001,0x8000,acc3 + + set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr11 + mqmachu fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 1,accg0 + test_acc_limmed 0x3ffd,0x8008,acc0 + test_accg_immed 1,accg1 + test_acc_limmed 0x3ffd,0x8008,acc1 + test_accg_immed 1,accg2 + test_acc_limmed 0x3fff,0x8001,acc2 + test_accg_immed 1,accg3 + test_acc_limmed 0x3fff,0x8001,acc3 + + set_accg_immed 0xff,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xffffffff,acc1 + set_accg_immed 0xff,accg2 ; saturation + set_acc_immed 0xffffffff,acc2 + set_accg_immed 0xff,accg3 + set_acc_immed 0xffffffff,acc3 + set_fr_iimmed 1,1,fr8 + set_fr_iimmed 1,1,fr10 + set_fr_iimmed 1,1,fr9 + set_fr_iimmed 1,1,fr11 + mqmachu fr8,fr10,acc0 + test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + test_accg_immed 0xff,accg2 + test_acc_limmed 0xffff,0xffff,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0xffff,0xffff,acc3 + + set_fr_iimmed 0xffff,0x0000,fr8 + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0x0000,0xffff,fr9 + set_fr_iimmed 0xffff,0xffff,fr11 + mqmachu fr8,fr10,acc0 + test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + test_accg_immed 0xff,accg2 + test_acc_limmed 0xffff,0xffff,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0xffff,0xffff,acc3 + + pass diff --git a/sim/testsuite/sim/frv/mqmacxhs.cgs b/sim/testsuite/sim/frv/mqmacxhs.cgs new file mode 100644 index 0000000..0be1151 --- /dev/null +++ b/sim/testsuite/sim/frv/mqmacxhs.cgs @@ -0,0 +1,211 @@ +# frv testcase for mqmacxhs $GRi,$GRj,$ACCk +# mach: fr400 + + .include "testutils.inc" + + start + + .global mqmacxhs +mqmacxhs: + ; Positive operands + set_fr_iimmed 2,3,fr8 ; multiply small numbers + set_fr_iimmed 2,3,fr10 + set_fr_iimmed 0,1,fr9 ; multiply by 0 + set_fr_iimmed 0,2,fr11 + mqmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0,acc3 + + set_fr_iimmed 2,1,fr8 ; multiply by 1 + set_fr_iimmed 2,1,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 0x3fff,2,fr11 + mqmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 8,acc0 + test_accg_immed 0,accg1 + test_acc_immed 8,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0,0x7ffe,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0,0x7ffe,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 0x4000,2,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr11 + mqmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8008,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8008,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x3fff,0x7fff,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x3fff,0x7fff,acc3 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 2,0xfffd,fr10 + set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 + set_fr_iimmed 0xfffe,1,fr11 + mqmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8002,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8002,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x3fff,0x7ffd,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x3fff,0x7ffd,acc3 + + set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 + set_fr_iimmed 0xfffe,0,fr10 + set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result + set_fr_iimmed 0x2001,0xfffe,fr11 + mqmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8002,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8002,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x3fff,0x3ffb,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x3fff,0x3ffb,acc3 + + set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result + set_fr_iimmed 0x4000,0xfffe,fr10 + set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result + set_fr_iimmed 0x7fff,0x8000,fr11 + mqmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x0002,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x0002,acc1 + test_accg_immed 0xff,accg2 + test_acc_limmed 0xffff,0xbffb,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0xffff,0xbffb,acc3 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffe,0xfffd,fr10 + set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 + set_fr_iimmed 0xffff,0xfffe,fr11 + mqmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x0008,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x0008,acc1 + test_accg_immed 0xff,accg2 + test_acc_limmed 0xffff,0xbffd,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0xffff,0xbffd,acc3 + + set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + mqmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0009,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fff0009,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0x3fffbffd,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0x3fffbffd,acc3 + + set_accg_immed 0x7f,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0x7f,accg1 + set_acc_immed 0xffffffff,acc1 + set_accg_immed 0x7f,accg2 ; saturation + set_acc_immed 0xffffffff,acc2 + set_accg_immed 0x7f,accg3 + set_acc_immed 0xffffffff,acc3 + set_fr_iimmed 1,1,fr8 + set_fr_iimmed 1,1,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + mqmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + test_accg_immed 0x7f,accg2 + test_acc_limmed 0xffff,0xffff,acc2 + test_accg_immed 0x7f,accg3 + test_acc_limmed 0xffff,0xffff,acc3 + + set_accg_immed 0x80,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed 0x80,accg1 + set_acc_immed 0,acc1 + set_accg_immed 0x80,accg2 ; saturation + set_acc_immed 0,acc2 + set_accg_immed 0x80,accg3 + set_acc_immed 0,acc3 + set_fr_iimmed 0xffff,0,fr8 + set_fr_iimmed 0xffff,1,fr10 + set_fr_iimmed 0x0000,0x8000,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + mqmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x80,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + test_accg_immed 0x80,accg2 + test_acc_immed 0,acc2 + test_accg_immed 0x80,accg3 + test_acc_immed 0,acc3 + + pass + + diff --git a/sim/testsuite/sim/frv/mqmulhs.cgs b/sim/testsuite/sim/frv/mqmulhs.cgs new file mode 100644 index 0000000..0a10c29 --- /dev/null +++ b/sim/testsuite/sim/frv/mqmulhs.cgs @@ -0,0 +1,125 @@ +# frv testcase for mqmulhs $GRi,$GRj,$ACCk +# mach: all + + .include "testutils.inc" + + start + + .global mqmulhs +mqmulhs: + ; Positive operands + set_fr_iimmed 2,3,fr8 ; multiply small numbers + set_fr_iimmed 3,2,fr10 + set_fr_iimmed 0,1,fr9 ; multiply by 0 + set_fr_iimmed 2,0,fr11 + mqmulhs fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0,acc3 + + set_fr_iimmed 2,1,fr8 ; multiply by 1 + set_fr_iimmed 1,2,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + mqmulhs fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_immed 2,acc0 + test_accg_immed 0,accg1 + test_acc_immed 2,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0,0x7ffe,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0,0x7ffe,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr11 + mqmulhs fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8000,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8000,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x3fff,0x0001,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x3fff,0x0001,acc3 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr10 + set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr11 + mqmulhs fr8,fr10,acc0 + test_accg_immed 0xff,accg0 + test_acc_immed -6,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed -6,acc1 + test_accg_immed 0xff,accg2 + test_acc_immed -2,acc2 + test_accg_immed 0xff,accg3 + test_acc_immed -2,acc3 + + set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr10 + set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr11 + mqmulhs fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + test_accg_immed 0xff,accg2 + test_acc_limmed 0xffff,0xbffe,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0xffff,0xbffe,acc3 + + set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr10 + set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr11 + mqmulhs fr8,fr10,acc0 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0x8000,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0x8000,acc1 + test_accg_immed 0xff,accg2 + test_acc_limmed 0xc000,0x8000,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0xc000,0x8000,acc3 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr10 + set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr11 + mqmulhs fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + test_accg_immed 0,accg2 + test_acc_immed 2,acc2 + test_accg_immed 0,accg3 + test_acc_immed 2,acc3 + + set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + mqmulhs fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fff0001,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0x40000000,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0x40000000,acc3 + + pass diff --git a/sim/testsuite/sim/frv/mqmulhu.cgs b/sim/testsuite/sim/frv/mqmulhu.cgs new file mode 100644 index 0000000..e94c09ae9 --- /dev/null +++ b/sim/testsuite/sim/frv/mqmulhu.cgs @@ -0,0 +1,80 @@ +# frv testcase for mqmulhu $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global mqmulhu +mqmulhu: + set_fr_iimmed 3,2,fr8 ; multiply small numbers + set_fr_iimmed 2,3,fr10 + set_fr_iimmed 1,2,fr9 ; multiply by 1 + set_fr_iimmed 2,1,fr11 + mqmulhu fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + test_accg_immed 0,accg2 + test_acc_immed 2,acc2 + test_accg_immed 0,accg3 + test_acc_immed 2,acc3 + + set_fr_iimmed 0,2,fr8 ; multiply by 0 + set_fr_iimmed 2,0,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + mqmulhu fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x7ffe,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x7ffe,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x8000,2,fr9 ; 17 bit result + set_fr_iimmed 2,0x8000,fr11 + mqmulhu fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8000,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8000,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0x00010000,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0x00010000,acc3 + + set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + mqmulhu fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fff0001,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x4000,0x0000,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x4000,0x0000,acc3 + + set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr11 + mqmulhu fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0xfffe,0x0001,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0xfffe,0x0001,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0xfffe,0x0001,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0xfffe,0x0001,acc3 + + pass diff --git a/sim/testsuite/sim/frv/mqmulxhs.cgs b/sim/testsuite/sim/frv/mqmulxhs.cgs new file mode 100644 index 0000000..7686bc1 --- /dev/null +++ b/sim/testsuite/sim/frv/mqmulxhs.cgs @@ -0,0 +1,125 @@ +# frv testcase for mqmulxhs $GRi,$GRj,$ACCk +# mach: all + + .include "testutils.inc" + + start + + .global mqmulxhs +mqmulxhs: + ; Positive operands + set_fr_iimmed 2,3,fr8 ; multiply small numbers + set_fr_iimmed 3,2,fr10 + set_fr_iimmed 0,1,fr9 ; multiply by 0 + set_fr_iimmed 0,2,fr11 + mqmulxhs fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_immed 4,acc0 + test_accg_immed 0,accg1 + test_acc_immed 9,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0,acc3 + + set_fr_iimmed 2,1,fr8 ; multiply by 1 + set_fr_iimmed 2,1,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 0x3fff,2,fr11 + mqmulxhs fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_immed 2,acc0 + test_accg_immed 0,accg1 + test_acc_immed 2,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0,0x7ffe,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0,0x7ffe,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 0x4000,2,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr11 + mqmulxhs fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8000,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8000,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x3fff,0x0001,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x3fff,0x0001,acc3 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 2,0xfffd,fr10 + set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 + set_fr_iimmed 0xfffe,1,fr11 + mqmulxhs fr8,fr10,acc0 + test_accg_immed 0xff,accg0 + test_acc_immed -6,acc0 + test_accg_immed 0xff,accg1 + test_acc_immed -6,acc1 + test_accg_immed 0xff,accg2 + test_acc_immed -2,acc2 + test_accg_immed 0xff,accg3 + test_acc_immed -2,acc3 + + set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 + set_fr_iimmed 0xfffe,0,fr10 + set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result + set_fr_iimmed 0x2001,0xfffe,fr11 + mqmulxhs fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + test_accg_immed 0xff,accg2 + test_acc_limmed 0xffff,0xbffe,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0xffff,0xbffe,acc3 + + set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result + set_fr_iimmed 0x4000,0xfffe,fr10 + set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result + set_fr_iimmed 0x7fff,0x8000,fr11 + mqmulxhs fr8,fr10,acc0 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0x8000,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0x8000,acc1 + test_accg_immed 0xff,accg2 + test_acc_limmed 0xc000,0x8000,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0xc000,0x8000,acc3 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffe,0xfffd,fr10 + set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 + set_fr_iimmed 0xffff,0xfffe,fr11 + mqmulxhs fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + test_accg_immed 0,accg2 + test_acc_immed 2,acc2 + test_accg_immed 0,accg3 + test_acc_immed 2,acc3 + + set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + mqmulxhs fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fff0001,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0x40000000,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0x40000000,acc3 + + pass diff --git a/sim/testsuite/sim/frv/mqmulxhu.cgs b/sim/testsuite/sim/frv/mqmulxhu.cgs new file mode 100644 index 0000000..b60e421 --- /dev/null +++ b/sim/testsuite/sim/frv/mqmulxhu.cgs @@ -0,0 +1,80 @@ +# frv testcase for mqmulxhu $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global mqmulxhu +mqmulxhu: + set_fr_iimmed 3,2,fr8 ; multiply small numbers + set_fr_iimmed 3,2,fr10 + set_fr_iimmed 1,2,fr9 ; multiply by 1 + set_fr_iimmed 1,2,fr11 + mqmulxhu fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_immed 6,acc0 + test_accg_immed 0,accg1 + test_acc_immed 6,acc1 + test_accg_immed 0,accg2 + test_acc_immed 2,acc2 + test_accg_immed 0,accg3 + test_acc_immed 2,acc3 + + set_fr_iimmed 0,2,fr8 ; multiply by 0 + set_fr_iimmed 0,2,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 0x3fff,2,fr11 + mqmulxhu fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x7ffe,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x7ffe,acc3 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 0x4000,2,fr10 + set_fr_iimmed 0x8000,2,fr9 ; 17 bit result + set_fr_iimmed 0x8000,2,fr11 + mqmulxhu fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x8000,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x8000,acc1 + test_accg_immed 0,accg2 + test_acc_immed 0x00010000,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0x00010000,acc3 + + set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + mqmulxhu fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_immed 0x3fff0001,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fff0001,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0x4000,0x0000,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x4000,0x0000,acc3 + + set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result + set_fr_iimmed 0xffff,0xffff,fr11 + mqmulxhu fr8,fr10,acc0 + test_accg_immed 0,accg0 + test_acc_limmed 0xfffe,0x0001,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0xfffe,0x0001,acc1 + test_accg_immed 0,accg2 + test_acc_limmed 0xfffe,0x0001,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0xfffe,0x0001,acc3 + + pass diff --git a/sim/testsuite/sim/frv/mqsaths.cgs b/sim/testsuite/sim/frv/mqsaths.cgs new file mode 100644 index 0000000..61ff112 --- /dev/null +++ b/sim/testsuite/sim/frv/mqsaths.cgs @@ -0,0 +1,50 @@ +# frv testcase for mqsaths $FRi,$FRj,$FRj +# mach: fr400 fr550 + + .include "testutils.inc" + + start + + .global mqsaths +mqsaths: + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0001,0x7fff,fr11 + set_fr_iimmed 0x0000,0x0000,fr13 + mqsaths fr10,fr12,fr14 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0x0000,0x0000,fr15 + + set_fr_iimmed 0xffff,0x8000,fr10 + set_fr_iimmed 0x0000,0x0000,fr12 + set_fr_iimmed 0x0000,0x0000,fr11 + set_fr_iimmed 0x0040,0x0040,fr13 + mqsaths fr10,fr12,fr14 + test_fr_limmed 0xffff,0xffff,fr14 + test_fr_limmed 0x0000,0x0000,fr15 + + set_fr_iimmed 0x0001,0x7fff,fr10 + set_fr_iimmed 0x0040,0x0040,fr12 + set_fr_iimmed 0xffff,0x8000,fr11 + set_fr_iimmed 0x0040,0x0040,fr13 + mqsaths fr10,fr12,fr14 + test_fr_limmed 0x0001,0x0040,fr14 + test_fr_limmed 0xffff,0xffbf,fr15 + + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr12 + set_fr_iimmed 0x0001,0x7fff,fr11 + set_fr_iimmed 0x7fff,0x7fff,fr13 + mqsaths fr10,fr12,fr14 + test_fr_limmed 0x0000,0x0000,fr14 + test_fr_limmed 0x0001,0x7fff,fr15 + + set_fr_iimmed 0xffff,0x8000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr12 + set_fr_iimmed 0xffff,0x8000,fr11 + set_fr_iimmed 0x7fff,0x7fff,fr13 + mqsaths fr10,fr12,fr14 + test_fr_limmed 0xffff,0x8000,fr14 + test_fr_limmed 0xffff,0x8000,fr15 + + pass diff --git a/sim/testsuite/sim/frv/mqxmachs.cgs b/sim/testsuite/sim/frv/mqxmachs.cgs new file mode 100644 index 0000000..6791ed3 --- /dev/null +++ b/sim/testsuite/sim/frv/mqxmachs.cgs @@ -0,0 +1,211 @@ +# frv testcase for mqxmachs $GRi,$GRj,$ACCk +# mach: fr400 + + .include "testutils.inc" + + start + + .global mqxmachs +mqxmachs: + ; Positive operands + set_fr_iimmed 2,3,fr8 ; multiply small numbers + set_fr_iimmed 3,2,fr10 + set_fr_iimmed 0,1,fr9 ; multiply by 0 + set_fr_iimmed 2,0,fr11 + mqxmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + test_accg_immed 0,accg2 + test_acc_immed 6,acc2 + test_accg_immed 0,accg3 + test_acc_immed 6,acc3 + + set_fr_iimmed 2,1,fr8 ; multiply by 1 + set_fr_iimmed 1,2,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 2,0x3fff,fr11 + mqxmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg2 + test_acc_immed 8,acc2 + test_accg_immed 0,accg3 + test_acc_immed 8,acc3 + test_accg_immed 0,accg0 + test_acc_limmed 0,0x7ffe,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0,0x7ffe,acc1 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 2,0x4000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr11 + mqxmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x8008,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x8008,acc3 + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0x7fff,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0x7fff,acc1 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,2,fr10 + set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 + set_fr_iimmed 1,0xfffe,fr11 + mqxmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x8002,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x8002,acc3 + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0x7ffd,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0x7ffd,acc1 + + set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 + set_fr_iimmed 0,0xfffe,fr10 + set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result + set_fr_iimmed 0xfffe,0x2001,fr11 + mqxmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x8002,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x8002,acc3 + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0x3ffb,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0x3ffb,acc1 + + set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result + set_fr_iimmed 0xfffe,0x4000,fr10 + set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result + set_fr_iimmed 0x8000,0x7fff,fr11 + mqxmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x0002,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x0002,acc3 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xbffb,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xbffb,acc1 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffd,0xfffe,fr10 + set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 + set_fr_iimmed 0xfffe,0xffff,fr11 + mqxmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x0008,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x0008,acc3 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xbffd,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xbffd,acc1 + + set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + mqxmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg2 + test_acc_immed 0x3fff0009,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0x3fff0009,acc3 + test_accg_immed 0,accg0 + test_acc_immed 0x3fffbffd,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fffbffd,acc1 + + set_accg_immed 0x7f,accg2 ; saturation + set_acc_immed 0xffffffff,acc2 + set_accg_immed 0x7f,accg3 + set_acc_immed 0xffffffff,acc3 + set_accg_immed 0x7f,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0x7f,accg1 + set_acc_immed 0xffffffff,acc1 + set_fr_iimmed 1,1,fr8 + set_fr_iimmed 1,1,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + mqxmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x7f,accg2 + test_acc_limmed 0xffff,0xffff,acc2 + test_accg_immed 0x7f,accg3 + test_acc_limmed 0xffff,0xffff,acc3 + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + + set_accg_immed 0x80,accg2 ; saturation + set_acc_immed 0,acc2 + set_accg_immed 0x80,accg3 + set_acc_immed 0,acc3 + set_accg_immed 0x80,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed 0x80,accg1 + set_acc_immed 0,acc1 + set_fr_iimmed 0xffff,0,fr8 + set_fr_iimmed 1,0xffff,fr10 + set_fr_iimmed 0x0000,0x8000,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + mqxmachs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x80,accg2 + test_acc_immed 0,acc2 + test_accg_immed 0x80,accg3 + test_acc_immed 0,acc3 + test_accg_immed 0x80,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + + pass + + diff --git a/sim/testsuite/sim/frv/mqxmacxhs.cgs b/sim/testsuite/sim/frv/mqxmacxhs.cgs new file mode 100644 index 0000000..c644eed --- /dev/null +++ b/sim/testsuite/sim/frv/mqxmacxhs.cgs @@ -0,0 +1,211 @@ +# frv testcase for mqxmacxhs $GRi,$GRj,$ACCk +# mach: fr400 + + .include "testutils.inc" + + start + + .global mqxmacxhs +mqxmacxhs: + ; Positive operands + set_fr_iimmed 2,3,fr8 ; multiply small numbers + set_fr_iimmed 2,3,fr10 + set_fr_iimmed 0,1,fr9 ; multiply by 0 + set_fr_iimmed 0,2,fr11 + mqxmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0,acc1 + test_accg_immed 0,accg2 + test_acc_immed 6,acc2 + test_accg_immed 0,accg3 + test_acc_immed 6,acc3 + + set_fr_iimmed 2,1,fr8 ; multiply by 1 + set_fr_iimmed 2,1,fr10 + set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result + set_fr_iimmed 0x3fff,2,fr11 + mqxmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg2 + test_acc_immed 8,acc2 + test_accg_immed 0,accg3 + test_acc_immed 8,acc3 + test_accg_immed 0,accg0 + test_acc_limmed 0,0x7ffe,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0,0x7ffe,acc1 + + set_fr_iimmed 0x4000,2,fr8 ; 16 bit result + set_fr_iimmed 0x4000,2,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result + set_fr_iimmed 0x7fff,0x7fff,fr11 + mqxmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x8008,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x8008,acc3 + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0x7fff,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0x7fff,acc1 + + ; Mixed operands + set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 2,0xfffd,fr10 + set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 + set_fr_iimmed 0xfffe,1,fr11 + mqxmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x8002,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x8002,acc3 + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0x7ffd,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0x7ffd,acc1 + + set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 + set_fr_iimmed 0xfffe,0,fr10 + set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result + set_fr_iimmed 0x2001,0xfffe,fr11 + mqxmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x8002,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x8002,acc3 + test_accg_immed 0,accg0 + test_acc_limmed 0x3fff,0x3ffb,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x3fff,0x3ffb,acc1 + + set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result + set_fr_iimmed 0x4000,0xfffe,fr10 + set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result + set_fr_iimmed 0x7fff,0x8000,fr11 + mqxmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x0002,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x0002,acc3 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xbffb,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xbffb,acc1 + + ; Negative operands + set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers + set_fr_iimmed 0xfffe,0xfffd,fr10 + set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 + set_fr_iimmed 0xffff,0xfffe,fr11 + mqxmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x0008,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x0008,acc3 + test_accg_immed 0xff,accg0 + test_acc_limmed 0xffff,0xbffd,acc0 + test_accg_immed 0xff,accg1 + test_acc_limmed 0xffff,0xbffd,acc1 + + set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result + set_fr_iimmed 0x8000,0x8000,fr11 + mqxmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg2 + test_acc_immed 0x3fff0009,acc2 + test_accg_immed 0,accg3 + test_acc_immed 0x3fff0009,acc3 + test_accg_immed 0,accg0 + test_acc_immed 0x3fffbffd,acc0 + test_accg_immed 0,accg1 + test_acc_immed 0x3fffbffd,acc1 + + set_accg_immed 0x7f,accg2 ; saturation + set_acc_immed 0xffffffff,acc2 + set_accg_immed 0x7f,accg3 + set_acc_immed 0xffffffff,acc3 + set_accg_immed 0x7f,accg0 ; saturation + set_acc_immed 0xffffffff,acc0 + set_accg_immed 0x7f,accg1 + set_acc_immed 0xffffffff,acc1 + set_fr_iimmed 1,1,fr8 + set_fr_iimmed 1,1,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + mqxmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x7f,accg2 + test_acc_limmed 0xffff,0xffff,acc2 + test_accg_immed 0x7f,accg3 + test_acc_limmed 0xffff,0xffff,acc3 + test_accg_immed 0x7f,accg0 + test_acc_limmed 0xffff,0xffff,acc0 + test_accg_immed 0x7f,accg1 + test_acc_limmed 0xffff,0xffff,acc1 + + set_accg_immed 0x80,accg2 ; saturation + set_acc_immed 0,acc2 + set_accg_immed 0x80,accg3 + set_acc_immed 0,acc3 + set_accg_immed 0x80,accg0 ; saturation + set_acc_immed 0,acc0 + set_accg_immed 0x80,accg1 + set_acc_immed 0,acc1 + set_fr_iimmed 0xffff,0,fr8 + set_fr_iimmed 0xffff,1,fr10 + set_fr_iimmed 0x0000,0x8000,fr9 ; saturation + set_fr_iimmed 0x7fff,0x7fff,fr11 + mqxmacxhs fr8,fr10,acc0 + test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf is set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set + test_accg_immed 0x80,accg2 + test_acc_immed 0,acc2 + test_accg_immed 0x80,accg3 + test_acc_immed 0,acc3 + test_accg_immed 0x80,accg0 + test_acc_immed 0,acc0 + test_accg_immed 0x80,accg1 + test_acc_immed 0,acc1 + + pass + + diff --git a/sim/testsuite/sim/frv/mrdacc.cgs b/sim/testsuite/sim/frv/mrdacc.cgs new file mode 100644 index 0000000..2178036 --- /dev/null +++ b/sim/testsuite/sim/frv/mrdacc.cgs @@ -0,0 +1,26 @@ +# frv testcase for mrdacc $ACC40i,$FRintk +# mach: all + + .include "testutils.inc" + + start + + .global mrdacc +mrdacc: + set_accg_immed 0,accg0 + set_acc_immed 0,acc0 + set_accg_immed -1,accg3 + set_acc_immed -1,acc3 + set_accg_immed 0x12,accg2 + set_acc_immed 0xdeadbeef,acc2 + + mrdacc acc0,fr10 + test_fr_iimmed 0,fr10 + + mrdacc acc3,fr10 + test_fr_iimmed 0xffffffff,fr10 + + mrdacc acc2,fr10 + test_fr_iimmed 0xdeadbeef,fr10 + + pass diff --git a/sim/testsuite/sim/frv/mrdaccg.cgs b/sim/testsuite/sim/frv/mrdaccg.cgs new file mode 100644 index 0000000..96e9406 --- /dev/null +++ b/sim/testsuite/sim/frv/mrdaccg.cgs @@ -0,0 +1,26 @@ +# frv testcase for mrdaccg $ACC40i,$FRintk +# mach: all + + .include "testutils.inc" + + start + + .global mrdaccg +mrdaccg: + set_accg_immed 0,accg0 + set_acc_immed 0,acc0 + set_accg_immed -1,accg3 + set_acc_immed -1,acc3 + set_accg_immed 0x12,accg2 + set_acc_immed 0xdeadbeef,acc2 + + mrdaccg accg0,fr10 + test_fr_iimmed 0,fr10 + + mrdaccg accg3,fr10 + test_fr_iimmed 0x000000ff,fr10 + + mrdaccg accg2,fr10 + test_fr_iimmed 0x00000012,fr10 + + pass diff --git a/sim/testsuite/sim/frv/mrotli.cgs b/sim/testsuite/sim/frv/mrotli.cgs new file mode 100644 index 0000000..02220ee --- /dev/null +++ b/sim/testsuite/sim/frv/mrotli.cgs @@ -0,0 +1,34 @@ +# frv testcase for mrotli $FRi,$s6,$FRk +# mach: all + + .include "testutils.inc" + + start + + .global mrotli +mrotli: + set_fr_iimmed 0,2,fr8 + mrotli fr8,0x20,fr8 ; Shift by 0 + test_fr_iimmed 2,fr8 + + set_fr_iimmed 0,2,fr8 + mrotli fr8,0,fr8 ; Shift by 0 + test_fr_iimmed 2,fr8 + + set_fr_iimmed 0,2,fr8 + mrotli fr8,1,fr8 ; Shift by 1 + test_fr_iimmed 4,fr8 + + set_fr_iimmed 0,1,fr8 + mrotli fr8,31,fr8 ; Shift by 31 + test_fr_iimmed 0x80000000,fr8 + + set_fr_iimmed 0,2,fr8 + mrotli fr8,31,fr8 ; max rotation + test_fr_iimmed 1,fr8 + + set_fr_iimmed 0xdead,0xbeef,fr8 + mrotli fr8,16,fr8 + test_fr_iimmed 0xbeefdead,fr8 + + pass diff --git a/sim/testsuite/sim/frv/mrotri.cgs b/sim/testsuite/sim/frv/mrotri.cgs new file mode 100644 index 0000000..17a5c74 --- /dev/null +++ b/sim/testsuite/sim/frv/mrotri.cgs @@ -0,0 +1,34 @@ +# frv testcase for mrotri $FRinti,$s6,$FRintk +# mach: all + + .include "testutils.inc" + + start + + .global mrotri +mrotri: + set_fr_iimmed 0x8000,0x0000,fr8 + mrotri fr8,0x20,fr8 ; Shift by 0 + test_fr_iimmed 0x80000000,fr8 + + set_fr_iimmed 0x8000,0x0000,fr8 + mrotri fr8,0,fr8 ; Shift by 0 + test_fr_iimmed 0x80000000,fr8 + + set_fr_iimmed 0x8000,0x0000,fr8 + mrotri fr8,1,fr8 ; Shift by 1 + test_fr_iimmed 0x40000000,fr8 + + set_fr_iimmed 0x8000,0x0000,fr8 + mrotri fr8,31,fr8 ; Shift by 31 + test_fr_iimmed 1,fr8 + + set_fr_iimmed 0x4000,0x0000,fr8 + mrotri fr8,31,fr8 ; max shift + test_fr_iimmed 0x80000000,fr8 + + set_fr_iimmed 0xdead,0xbeef,fr8 + mrotri fr8,16,fr8 ; max shift + test_fr_iimmed 0xbeefdead,fr8 + + pass diff --git a/sim/testsuite/sim/frv/msaths.cgs b/sim/testsuite/sim/frv/msaths.cgs new file mode 100644 index 0000000..513d5d3 --- /dev/null +++ b/sim/testsuite/sim/frv/msaths.cgs @@ -0,0 +1,55 @@ +# frv testcase for msaths $FRi,$FRj,$FRj +# mach: all + + .include "testutils.inc" + + start + + .global msaths +msaths: + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + msaths fr10,fr11,fr12 + test_fr_limmed 0x0000,0x0000,fr12 + + set_fr_iimmed 0x0001,0x7fff,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + msaths fr10,fr11,fr12 + test_fr_limmed 0x0000,0x0000,fr12 + + set_fr_iimmed 0xffff,0x8000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + msaths fr10,fr11,fr12 + test_fr_limmed 0xffff,0xffff,fr12 + + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0040,0x0040,fr11 + msaths fr10,fr11,fr12 + test_fr_limmed 0x0000,0x0000,fr12 + + set_fr_iimmed 0x0001,0x7fff,fr10 + set_fr_iimmed 0x0040,0x0040,fr11 + msaths fr10,fr11,fr12 + test_fr_limmed 0x0001,0x0040,fr12 + + set_fr_iimmed 0xffff,0x8000,fr10 + set_fr_iimmed 0x0040,0x0040,fr11 + msaths fr10,fr11,fr12 + test_fr_limmed 0xffff,0xffbf,fr12 + + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + msaths fr10,fr11,fr12 + test_fr_limmed 0x0000,0x0000,fr12 + + set_fr_iimmed 0x0001,0x7fff,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + msaths fr10,fr11,fr12 + test_fr_limmed 0x0001,0x7fff,fr12 + + set_fr_iimmed 0xffff,0x8000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + msaths fr10,fr11,fr12 + test_fr_limmed 0xffff,0x8000,fr12 + + pass diff --git a/sim/testsuite/sim/frv/msathu.cgs b/sim/testsuite/sim/frv/msathu.cgs new file mode 100644 index 0000000..4f376b2 --- /dev/null +++ b/sim/testsuite/sim/frv/msathu.cgs @@ -0,0 +1,55 @@ +# frv testcase for msathu $FRi,$FRj,$FRj +# mach: all + + .include "testutils.inc" + + start + + .global msathu +msathu: + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + msathu fr10,fr11,fr12 + test_fr_limmed 0x0000,0x0000,fr12 + + set_fr_iimmed 0x0001,0x7fff,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + msathu fr10,fr11,fr12 + test_fr_limmed 0x0000,0x0000,fr12 + + set_fr_iimmed 0xffff,0x8000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + msathu fr10,fr11,fr12 + test_fr_limmed 0x0000,0x0000,fr12 + + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0040,0x0040,fr11 + msathu fr10,fr11,fr12 + test_fr_limmed 0x0000,0x0000,fr12 + + set_fr_iimmed 0x0001,0x7fff,fr10 + set_fr_iimmed 0x0040,0x0040,fr11 + msathu fr10,fr11,fr12 + test_fr_limmed 0x0001,0x0040,fr12 + + set_fr_iimmed 0xffff,0x8000,fr10 + set_fr_iimmed 0x0040,0x0040,fr11 + msathu fr10,fr11,fr12 + test_fr_limmed 0x0040,0x0040,fr12 + + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + msathu fr10,fr11,fr12 + test_fr_limmed 0x0000,0x0000,fr12 + + set_fr_iimmed 0x0001,0x7fff,fr10 + set_fr_iimmed 0x7fff,0x7fff,fr11 + msathu fr10,fr11,fr12 + test_fr_limmed 0x0001,0x7fff,fr12 + + set_fr_iimmed 0xffff,0xffff,fr10 + set_fr_iimmed 0x7fff,0xffff,fr11 + msathu fr10,fr11,fr12 + test_fr_limmed 0x7fff,0xffff,fr12 + + pass diff --git a/sim/testsuite/sim/frv/msllhi.cgs b/sim/testsuite/sim/frv/msllhi.cgs new file mode 100644 index 0000000..4340b9f --- /dev/null +++ b/sim/testsuite/sim/frv/msllhi.cgs @@ -0,0 +1,30 @@ +# frv testcase for msllhi $FRi,$s6,$FRk +# mach: all + + .include "testutils.inc" + + start + + .global msllhi +msllhi: + set_fr_iimmed 2,2,fr8 + msllhi fr8,0x20,fr8 ; Shift by 0 + test_fr_limmed 2,2,fr8 + + set_fr_iimmed 2,2,fr8 + msllhi fr8,0,fr8 ; Shift by 0 + test_fr_limmed 2,2,fr8 + + set_fr_iimmed 2,2,fr8 + msllhi fr8,1,fr8 ; Shift by 1 + test_fr_limmed 4,4,fr8 + + set_fr_iimmed 1,1,fr8 + msllhi fr8,31,fr8 ; Shift by 15 + test_fr_limmed 0x8000,0x8000,fr8 + + set_fr_iimmed 0xdead,0xbeef,fr8 + msllhi fr8,15,fr8 + test_fr_iimmed 0x80008000,fr8 + + pass diff --git a/sim/testsuite/sim/frv/msrahi.cgs b/sim/testsuite/sim/frv/msrahi.cgs new file mode 100644 index 0000000..182f84e --- /dev/null +++ b/sim/testsuite/sim/frv/msrahi.cgs @@ -0,0 +1,30 @@ +# frv testcase for msrahi $FRi,$s6,$FRk +# mach: all + + .include "testutils.inc" + + start + + .global msrahi +msrahi: + set_fr_iimmed 2,2,fr8 + msrahi fr8,0x20,fr8 ; Shift by 0 + test_fr_limmed 2,2,fr8 + + set_fr_iimmed 2,2,fr8 + msrahi fr8,0,fr8 ; Shift by 0 + test_fr_limmed 2,2,fr8 + + set_fr_iimmed 3,2,fr8 + msrahi fr8,1,fr8 ; Shift by 1 + test_fr_limmed 1,1,fr8 + + set_fr_iimmed 0x8000,0x7fff,fr8 + msrahi fr8,31,fr8 ; Shift by 15 + test_fr_limmed 0xffff,0x0000,fr8 + + set_fr_iimmed 0xdead,0xbeef,fr8 + msrahi fr8,15,fr8 + test_fr_iimmed 0xffffffff,fr8 + + pass diff --git a/sim/testsuite/sim/frv/msrlhi.cgs b/sim/testsuite/sim/frv/msrlhi.cgs new file mode 100644 index 0000000..c9971a9 --- /dev/null +++ b/sim/testsuite/sim/frv/msrlhi.cgs @@ -0,0 +1,30 @@ +# frv testcase for msrlhi $FRi,$s6,$FRk +# mach: all + + .include "testutils.inc" + + start + + .global msrlhi +msrlhi: + set_fr_iimmed 2,2,fr8 + msrlhi fr8,0x20,fr8 ; Shift by 0 + test_fr_limmed 2,2,fr8 + + set_fr_iimmed 2,2,fr8 + msrlhi fr8,0,fr8 ; Shift by 0 + test_fr_limmed 2,2,fr8 + + set_fr_iimmed 3,2,fr8 + msrlhi fr8,1,fr8 ; Shift by 1 + test_fr_limmed 1,1,fr8 + + set_fr_iimmed 0xffff,0x8000,fr8 + msrlhi fr8,31,fr8 ; Shift by 15 + test_fr_limmed 0x0001,0x0001,fr8 + + set_fr_iimmed 0xdead,0xbeef,fr8 + msrlhi fr8,15,fr8 + test_fr_iimmed 0x00010001,fr8 + + pass diff --git a/sim/testsuite/sim/frv/msubhss.cgs b/sim/testsuite/sim/frv/msubhss.cgs new file mode 100644 index 0000000..1ba3343 --- /dev/null +++ b/sim/testsuite/sim/frv/msubhss.cgs @@ -0,0 +1,100 @@ +# frv testcase for msubhss $FRi,$FRj,$FRj +# mach: frv fr500 fr400 + + .include "testutils.inc" + + start + + .global msubhss +msubhss: + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + msubhss fr10,fr11,fr12 + test_fr_limmed 0x0000,0x0000,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xdead,0x0000,fr10 + set_fr_iimmed 0x0000,0xbeef,fr11 + msubhss fr10,fr11,fr12 + test_fr_limmed 0xdead,0x4111,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0000,0xdead,fr10 + set_fr_iimmed 0xbeef,0x0000,fr11 + msubhss fr10,fr11,fr12 + test_fr_limmed 0x4111,0xdead,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + msubhss fr10,fr11,fr12 + test_fr_limmed 0x0123,0x4567,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0xffff,0xffff,fr11 + msubhss fr10,fr11,fr12 + test_fr_limmed 0x1235,0x5679,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0xfffe,0xffff,fr11 + msubhss fr10,fr11,fr12 + test_fr_limmed 0x7fff,0x7fff,fr12 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + msubhss fr10,fr11,fr12 + test_fr_limmed 0x8000,0x8000,fr12 + test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x8001,0x8001,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + msubhss fr10,fr11,fr12 + test_fr_limmed 0x8000,0x8000,fr12 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x8000,0x8000,fr11 + msubhss.p fr10,fr10,fr12 + msubhss fr11,fr10,fr13 + test_fr_limmed 0x0000,0x0000,fr12 + test_fr_limmed 0x8000,0x8000,fr13 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 0x3c,2,0xc,msr1 ; msr0.sie is set + test_spr_bits 2,1,1,msr1 ; msr1.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + pass diff --git a/sim/testsuite/sim/frv/msubhus.cgs b/sim/testsuite/sim/frv/msubhus.cgs new file mode 100644 index 0000000..1a002da --- /dev/null +++ b/sim/testsuite/sim/frv/msubhus.cgs @@ -0,0 +1,80 @@ +# frv testcase for msubhus $FRi,$FRj,$FRj +# mach: frv fr500 fr400 + + .include "testutils.inc" + + start + + .global msubhus +msubhus: + set_fr_iimmed 0x0000,0x0000,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + msubhus fr10,fr11,fr12 + test_fr_limmed 0x0000,0x0000,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0xdead,0xbeef,fr10 + set_fr_iimmed 0x0000,0x0000,fr11 + msubhus fr10,fr11,fr12 + test_fr_limmed 0xdead,0xbeef,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x1111,0x1111,fr11 + msubhus fr10,fr11,fr12 + test_fr_limmed 0x0123,0x4567,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x7ffe,0x7ffe,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + msubhus fr10,fr11,fr12 + test_fr_limmed 0x7ffc,0x7ffd,fr12 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0001,0x0002,fr11 + msubhus fr10,fr11,fr12 + test_fr_limmed 0x0000,0x0000,fr12 + test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0001,fr11 + msubhus fr10,fr11,fr12 + test_fr_limmed 0x0000,0x0000,fr12 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_fr_iimmed 0x0001,0x0001,fr10 + set_fr_iimmed 0x0002,0x0002,fr11 + msubhus.p fr10,fr10,fr12 + msubhus fr10,fr11,fr13 + test_fr_limmed 0x0000,0x0000,fr12 + test_fr_limmed 0x0000,0x0000,fr13 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 0x3c,2,0xc,msr1 ; msr1.sie is set + test_spr_bits 2,1,1,msr1 ; msr1.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + + pass diff --git a/sim/testsuite/sim/frv/mtrap.cgs b/sim/testsuite/sim/frv/mtrap.cgs new file mode 100644 index 0000000..65b947a --- /dev/null +++ b/sim/testsuite/sim/frv/mtrap.cgs @@ -0,0 +1,50 @@ +# frv testcase for mp_exception +# mach: frv fr500 fr400 + + .include "testutils.inc" + + start + + .global mp_exception +mpx: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 0x0e0,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 + set_spr_immed 128,lcr + set_spr_addr ok1,lr + set_psr_et 1 + set_gr_immed 0,gr5 + + set_spr_immed 0,msr0 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x7ffe,0x7ffe,fr11 + set_fr_iimmed 0xffff,0xffff,fr12 + set_fr_iimmed 0x0002,0x0001,fr13 + mqaddhss fr10,fr12,fr14 + test_fr_limmed 0x1233,0x5677,fr14 + test_fr_limmed 0x7fff,0x7fff,fr15 + test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + mtrap ; generate interrupt + test_gr_immed 1,gr5 + + and_spr_immed 0xffffc000,msr0 ; Clear msr0 fields + mcmpsh fr10,fr11,fcc0 ; no exception + test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear + mtrap ; nop + test_gr_immed 1,gr5 + + pass + +; exception handler +ok1: + test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + inc_gr_immed 1,gr5 + rett 0 + fail diff --git a/sim/testsuite/sim/frv/munpackh.cgs b/sim/testsuite/sim/frv/munpackh.cgs new file mode 100644 index 0000000..45b2bd8 --- /dev/null +++ b/sim/testsuite/sim/frv/munpackh.cgs @@ -0,0 +1,22 @@ +# frv testcase for munpackh $FRi,$FRj +# mach: all + + .include "testutils.inc" + + start + + .global munpackh +munpackh: + set_fr_iimmed 0xdead,0xbeef,fr10 + set_fr_iimmed 0x1234,0x5678,fr11 + munpackh fr10,fr12 + test_fr_limmed 0xdead,0xdead,fr12 + test_fr_limmed 0xbeef,0xbeef,fr13 + + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0xdead,0xbeef,fr11 + munpackh fr10,fr12 + test_fr_limmed 0x1234,0x1234,fr12 + test_fr_limmed 0x5678,0x5678,fr13 + + pass diff --git a/sim/testsuite/sim/frv/mwcut.cgs b/sim/testsuite/sim/frv/mwcut.cgs new file mode 100644 index 0000000..0e31b8f --- /dev/null +++ b/sim/testsuite/sim/frv/mwcut.cgs @@ -0,0 +1,269 @@ +# frv testcase for mwcut $FRi,FRj,$FRk +# mach: all + + .include "testutils.inc" + + start + + .global mwcut +mwcut: + set_fr_iimmed 0x0123,0x4567,fr8 + set_fr_iimmed 0x89ab,0xcdef,fr9 + + set_fr_iimmed 0,0,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x01234567,fr11 + + set_fr_iimmed 0,1,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x02468acf,fr11 + + set_fr_iimmed 0,2,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x048d159e,fr11 + + set_fr_iimmed 0,3,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x091a2b3c,fr11 + + set_fr_iimmed 0,4,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x12345678,fr11 + + set_fr_iimmed 0,5,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x2468acf1,fr11 + + set_fr_iimmed 0,6,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x48d159e2,fr11 + + set_fr_iimmed 0,7,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x91a2b3c4,fr11 + + set_fr_iimmed 0,8,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x23456789,fr11 + + set_fr_iimmed 0,9,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x468acf13,fr11 + + set_fr_iimmed 0,10,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x8d159e26,fr11 + + set_fr_iimmed 0,11,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x1a2b3c4d,fr11 + + set_fr_iimmed 0,12,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x3456789a,fr11 + + set_fr_iimmed 0,13,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x68acf135,fr11 + + set_fr_iimmed 0,14,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0xd159e26a,fr11 + + set_fr_iimmed 0,15,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0xa2b3c4d5,fr11 + + set_fr_iimmed 0,16,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x456789ab,fr11 + + set_fr_iimmed 0,17,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x8acf1357,fr11 + + set_fr_iimmed 0,18,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x159e26af,fr11 + + set_fr_iimmed 0,19,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x2b3c4d5e,fr11 + + set_fr_iimmed 0,20,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x56789abc,fr11 + + set_fr_iimmed 0,21,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0xacf13579,fr11 + + set_fr_iimmed 0,22,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x59e26af3,fr11 + + set_fr_iimmed 0,23,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0xb3c4d5e6,fr11 + + set_fr_iimmed 0,24,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x6789abcd,fr11 + + set_fr_iimmed 0,25,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0xcf13579b,fr11 + + set_fr_iimmed 0,26,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x9e26af37,fr11 + + set_fr_iimmed 0,27,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x3c4d5e6f,fr11 + + set_fr_iimmed 0,28,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x789abcde,fr11 + + set_fr_iimmed 0,29,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0xf13579bd,fr11 + + set_fr_iimmed 0,30,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0xe26af37b,fr11 + + set_fr_iimmed 0,31,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0xc4d5e6f7,fr11 + + set_fr_iimmed 0,32,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x89abcdef,fr11 + + set_fr_iimmed 0,33,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x13579bde,fr11 + + set_fr_iimmed 0,34,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x26af37bc,fr11 + + set_fr_iimmed 0,35,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x4d5e6f78,fr11 + + set_fr_iimmed 0,36,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x9abcdef0,fr11 + + set_fr_iimmed 0,37,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x3579bde0,fr11 + + set_fr_iimmed 0,38,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x6af37bc0,fr11 + + set_fr_iimmed 0,39,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0xd5e6f780,fr11 + + set_fr_iimmed 0,40,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0xabcdef00,fr11 + + set_fr_iimmed 0,41,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x579bde00,fr11 + + set_fr_iimmed 0,42,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0xaf37bc00,fr11 + + set_fr_iimmed 0,43,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x5e6f7800,fr11 + + set_fr_iimmed 0,44,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0xbcdef000,fr11 + + set_fr_iimmed 0,45,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x79bde000,fr11 + + set_fr_iimmed 0,46,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0xf37bc000,fr11 + + set_fr_iimmed 0,47,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0xe6f78000,fr11 + + set_fr_iimmed 0,48,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0xcdef0000,fr11 + + set_fr_iimmed 0,49,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x9bde0000,fr11 + + set_fr_iimmed 0,50,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x37bc0000,fr11 + + set_fr_iimmed 0,51,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x6f780000,fr11 + + set_fr_iimmed 0,52,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0xdef00000,fr11 + + set_fr_iimmed 0,53,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0xbde00000,fr11 + + set_fr_iimmed 0,54,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x7bc00000,fr11 + + set_fr_iimmed 0,55,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0xf7800000,fr11 + + set_fr_iimmed 0,56,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0xef000000,fr11 + + set_fr_iimmed 0,57,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0xde000000,fr11 + + set_fr_iimmed 0,58,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0xbc000000,fr11 + + set_fr_iimmed 0,59,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x78000000,fr11 + + set_fr_iimmed 0,60,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0xf0000000,fr11 + + set_fr_iimmed 0,61,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0xe0000000,fr11 + + set_fr_iimmed 0,62,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0xc0000000,fr11 + + set_fr_iimmed 0,63,fr10 + mwcut fr8,fr10,fr11 + test_fr_iimmed 0x80000000,fr11 + + pass diff --git a/sim/testsuite/sim/frv/mwcuti.cgs b/sim/testsuite/sim/frv/mwcuti.cgs new file mode 100644 index 0000000..338eab8 --- /dev/null +++ b/sim/testsuite/sim/frv/mwcuti.cgs @@ -0,0 +1,205 @@ +# frv testcase for mwcuti $FRi,s6,$FRk +# mach: all + + .include "testutils.inc" + + start + + .global mwcuti +mwcuti: + set_fr_iimmed 0x0123,0x4567,fr8 + set_fr_iimmed 0x89ab,0xcdef,fr9 + + mwcuti fr8,0,fr11 + test_fr_iimmed 0x01234567,fr11 + + mwcuti fr8,1,fr11 + test_fr_iimmed 0x02468acf,fr11 + + mwcuti fr8,2,fr11 + test_fr_iimmed 0x048d159e,fr11 + + mwcuti fr8,3,fr11 + test_fr_iimmed 0x091a2b3c,fr11 + + mwcuti fr8,4,fr11 + test_fr_iimmed 0x12345678,fr11 + + mwcuti fr8,5,fr11 + test_fr_iimmed 0x2468acf1,fr11 + + mwcuti fr8,6,fr11 + test_fr_iimmed 0x48d159e2,fr11 + + mwcuti fr8,7,fr11 + test_fr_iimmed 0x91a2b3c4,fr11 + + mwcuti fr8,8,fr11 + test_fr_iimmed 0x23456789,fr11 + + mwcuti fr8,9,fr11 + test_fr_iimmed 0x468acf13,fr11 + + mwcuti fr8,10,fr11 + test_fr_iimmed 0x8d159e26,fr11 + + mwcuti fr8,11,fr11 + test_fr_iimmed 0x1a2b3c4d,fr11 + + mwcuti fr8,12,fr11 + test_fr_iimmed 0x3456789a,fr11 + + mwcuti fr8,13,fr11 + test_fr_iimmed 0x68acf135,fr11 + + mwcuti fr8,14,fr11 + test_fr_iimmed 0xd159e26a,fr11 + + mwcuti fr8,15,fr11 + test_fr_iimmed 0xa2b3c4d5,fr11 + + mwcuti fr8,16,fr11 + test_fr_iimmed 0x456789ab,fr11 + + mwcuti fr8,17,fr11 + test_fr_iimmed 0x8acf1357,fr11 + + mwcuti fr8,18,fr11 + test_fr_iimmed 0x159e26af,fr11 + + mwcuti fr8,19,fr11 + test_fr_iimmed 0x2b3c4d5e,fr11 + + mwcuti fr8,20,fr11 + test_fr_iimmed 0x56789abc,fr11 + + mwcuti fr8,21,fr11 + test_fr_iimmed 0xacf13579,fr11 + + mwcuti fr8,22,fr11 + test_fr_iimmed 0x59e26af3,fr11 + + mwcuti fr8,23,fr11 + test_fr_iimmed 0xb3c4d5e6,fr11 + + mwcuti fr8,24,fr11 + test_fr_iimmed 0x6789abcd,fr11 + + mwcuti fr8,25,fr11 + test_fr_iimmed 0xcf13579b,fr11 + + mwcuti fr8,26,fr11 + test_fr_iimmed 0x9e26af37,fr11 + + mwcuti fr8,27,fr11 + test_fr_iimmed 0x3c4d5e6f,fr11 + + mwcuti fr8,28,fr11 + test_fr_iimmed 0x789abcde,fr11 + + mwcuti fr8,29,fr11 + test_fr_iimmed 0xf13579bd,fr11 + + mwcuti fr8,30,fr11 + test_fr_iimmed 0xe26af37b,fr11 + + mwcuti fr8,31,fr11 + test_fr_iimmed 0xc4d5e6f7,fr11 + + mwcuti fr8,32,fr11 + test_fr_iimmed 0x89abcdef,fr11 + + mwcuti fr8,33,fr11 + test_fr_iimmed 0x13579bde,fr11 + + mwcuti fr8,34,fr11 + test_fr_iimmed 0x26af37bc,fr11 + + mwcuti fr8,35,fr11 + test_fr_iimmed 0x4d5e6f78,fr11 + + mwcuti fr8,36,fr11 + test_fr_iimmed 0x9abcdef0,fr11 + + mwcuti fr8,37,fr11 + test_fr_iimmed 0x3579bde0,fr11 + + mwcuti fr8,38,fr11 + test_fr_iimmed 0x6af37bc0,fr11 + + mwcuti fr8,39,fr11 + test_fr_iimmed 0xd5e6f780,fr11 + + mwcuti fr8,40,fr11 + test_fr_iimmed 0xabcdef00,fr11 + + mwcuti fr8,41,fr11 + test_fr_iimmed 0x579bde00,fr11 + + mwcuti fr8,42,fr11 + test_fr_iimmed 0xaf37bc00,fr11 + + mwcuti fr8,43,fr11 + test_fr_iimmed 0x5e6f7800,fr11 + + mwcuti fr8,44,fr11 + test_fr_iimmed 0xbcdef000,fr11 + + mwcuti fr8,45,fr11 + test_fr_iimmed 0x79bde000,fr11 + + mwcuti fr8,46,fr11 + test_fr_iimmed 0xf37bc000,fr11 + + mwcuti fr8,47,fr11 + test_fr_iimmed 0xe6f78000,fr11 + + mwcuti fr8,48,fr11 + test_fr_iimmed 0xcdef0000,fr11 + + mwcuti fr8,49,fr11 + test_fr_iimmed 0x9bde0000,fr11 + + mwcuti fr8,50,fr11 + test_fr_iimmed 0x37bc0000,fr11 + + mwcuti fr8,51,fr11 + test_fr_iimmed 0x6f780000,fr11 + + mwcuti fr8,52,fr11 + test_fr_iimmed 0xdef00000,fr11 + + mwcuti fr8,53,fr11 + test_fr_iimmed 0xbde00000,fr11 + + mwcuti fr8,54,fr11 + test_fr_iimmed 0x7bc00000,fr11 + + mwcuti fr8,55,fr11 + test_fr_iimmed 0xf7800000,fr11 + + mwcuti fr8,56,fr11 + test_fr_iimmed 0xef000000,fr11 + + mwcuti fr8,57,fr11 + test_fr_iimmed 0xde000000,fr11 + + mwcuti fr8,58,fr11 + test_fr_iimmed 0xbc000000,fr11 + + mwcuti fr8,59,fr11 + test_fr_iimmed 0x78000000,fr11 + + mwcuti fr8,60,fr11 + test_fr_iimmed 0xf0000000,fr11 + + mwcuti fr8,61,fr11 + test_fr_iimmed 0xe0000000,fr11 + + mwcuti fr8,62,fr11 + test_fr_iimmed 0xc0000000,fr11 + + mwcuti fr8,63,fr11 + test_fr_iimmed 0x80000000,fr11 + + pass diff --git a/sim/testsuite/sim/frv/mwtacc.cgs b/sim/testsuite/sim/frv/mwtacc.cgs new file mode 100644 index 0000000..20b4d31 --- /dev/null +++ b/sim/testsuite/sim/frv/mwtacc.cgs @@ -0,0 +1,23 @@ +# frv testcase for mwtacc $FRinti,$ACC40k +# mach: all + + .include "testutils.inc" + + start + + .global mwtacc +mwtacc: + test_accg_immed 0x00,accg0 + test_acc_immed 0x00000000,acc0 + + set_fr_iimmed 0xdead,0xbeef,fr10 + mwtacc fr10,acc0 + test_accg_immed 0x00,accg0 + test_acc_immed 0xdeadbeef,acc0 + + set_fr_iimmed 0x1234,0x5678,fr10 + mwtacc fr10,acc0 + test_accg_immed 0x00,accg0 + test_acc_immed 0x12345678,acc0 + + pass diff --git a/sim/testsuite/sim/frv/mwtaccg.cgs b/sim/testsuite/sim/frv/mwtaccg.cgs new file mode 100644 index 0000000..6e26bab --- /dev/null +++ b/sim/testsuite/sim/frv/mwtaccg.cgs @@ -0,0 +1,23 @@ +# frv testcase for mwtaccg $FRinti,$ACC40k +# mach: all + + .include "testutils.inc" + + start + + .global mwtaccg +mwtaccg: + test_accg_immed 0x00,accg0 + test_acc_immed 0x00000000,acc0 + + set_fr_iimmed 0xdead,0xbeef,fr10 + mwtaccg fr10,accg0 + test_accg_immed 0xef,accg0 + test_acc_immed 0,acc0 + + set_fr_iimmed 0x1234,0x5678,fr10 + mwtaccg fr10,accg0 + test_accg_immed 0x78,accg0 + test_acc_immed 0,acc0 + + pass diff --git a/sim/testsuite/sim/frv/mxor.cgs b/sim/testsuite/sim/frv/mxor.cgs new file mode 100644 index 0000000..6d1cce1 --- /dev/null +++ b/sim/testsuite/sim/frv/mxor.cgs @@ -0,0 +1,30 @@ +# frv testcase for mxor $FRinti,$FRintj,$FRintk +# mach: all + + .include "testutils.inc" + + start + + .global mxor +mxor: + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + set_fr_iimmed 0x5555,0x5555,fr8 + mxor fr7,fr8,fr8 + test_fr_iimmed 0xffffffff,fr8 + + set_fr_iimmed 0x0000,0x0000,fr7 + set_fr_iimmed 0x0000,0x0000,fr8 + mxor fr7,fr8,fr8 + test_fr_iimmed 0x00000000,fr8 + + set_fr_iimmed 0xaaaa,0xaaaa,fr7 + set_fr_iimmed 0xaaaa,0xaaaa,fr8 + mxor fr7,fr8,fr8 + test_fr_iimmed 0x00000000,fr8 + + set_fr_iimmed 0xdead,0x0000,fr7 + set_fr_iimmed 0x0000,0xbeef,fr8 + mxor fr7,fr8,fr8 + test_fr_iimmed 0xdeadbeef,fr8 + + pass diff --git a/sim/testsuite/sim/frv/nandcr.cgs b/sim/testsuite/sim/frv/nandcr.cgs new file mode 100644 index 0000000..8d3298f --- /dev/null +++ b/sim/testsuite/sim/frv/nandcr.cgs @@ -0,0 +1,59 @@ +# frv testcase for nandcr $CCi,$CCj,$CCk +# mach: all + + .include "testutils.inc" + + start + + .global nandcr +nandcr: + set_spr_immed 0x1b1b,cccr + nandcr cc7,cc7,cc3 + test_spr_immed 0x1b1b,cccr + + nandcr cc7,cc6,cc3 + test_spr_immed 0x1b1b,cccr + + nandcr cc7,cc5,cc3 + test_spr_immed 0x1b1b,cccr + + nandcr cc7,cc4,cc3 + test_spr_immed 0x1b1b,cccr + + nandcr cc6,cc7,cc3 + test_spr_immed 0x1b1b,cccr + + nandcr cc6,cc6,cc3 + test_spr_immed 0x1b1b,cccr + + nandcr cc6,cc5,cc3 + test_spr_immed 0x1b1b,cccr + + nandcr cc6,cc4,cc3 + test_spr_immed 0x1b1b,cccr + + nandcr cc5,cc7,cc3 + test_spr_immed 0x1b1b,cccr + + nandcr cc5,cc6,cc3 + test_spr_immed 0x1b1b,cccr + + nandcr cc5,cc5,cc3 + test_spr_immed 0x1b1b,cccr + + nandcr cc5,cc4,cc3 + test_spr_immed 0x1b1b,cccr + + nandcr cc4,cc7,cc3 + test_spr_immed 0x1b1b,cccr + + nandcr cc4,cc6,cc3 + test_spr_immed 0x1b1b,cccr + + nandcr cc4,cc5,cc3 + test_spr_immed 0x1bdb,cccr + + nandcr cc4,cc4,cc3 + test_spr_immed 0x1b9b,cccr + + pass diff --git a/sim/testsuite/sim/frv/nandncr.cgs b/sim/testsuite/sim/frv/nandncr.cgs new file mode 100644 index 0000000..c761c56 --- /dev/null +++ b/sim/testsuite/sim/frv/nandncr.cgs @@ -0,0 +1,59 @@ +# frv testcase for nandncr $CCi,$CCj,$CCk +# mach: all + + .include "testutils.inc" + + start + + .global nandncr +nandncr: + set_spr_immed 0x1b1b,cccr + nandncr cc7,cc7,cc3 + test_spr_immed 0x1b1b,cccr + + nandncr cc7,cc6,cc3 + test_spr_immed 0x1b1b,cccr + + nandncr cc7,cc5,cc3 + test_spr_immed 0x1b1b,cccr + + nandncr cc7,cc4,cc3 + test_spr_immed 0x1b1b,cccr + + nandncr cc6,cc7,cc3 + test_spr_immed 0x1b1b,cccr + + nandncr cc6,cc6,cc3 + test_spr_immed 0x1b1b,cccr + + nandncr cc6,cc5,cc3 + test_spr_immed 0x1b1b,cccr + + nandncr cc6,cc4,cc3 + test_spr_immed 0x1b1b,cccr + + nandncr cc5,cc7,cc3 + test_spr_immed 0x1b1b,cccr + + nandncr cc5,cc6,cc3 + test_spr_immed 0x1b1b,cccr + + nandncr cc5,cc5,cc3 + test_spr_immed 0x1bdb,cccr + + nandncr cc5,cc4,cc3 + test_spr_immed 0x1b9b,cccr + + nandncr cc4,cc7,cc3 + test_spr_immed 0x1b1b,cccr + + nandncr cc4,cc6,cc3 + test_spr_immed 0x1b1b,cccr + + nandncr cc4,cc5,cc3 + test_spr_immed 0x1b1b,cccr + + nandncr cc4,cc4,cc3 + test_spr_immed 0x1b1b,cccr + + pass diff --git a/sim/testsuite/sim/frv/nfadds.cgs b/sim/testsuite/sim/frv/nfadds.cgs new file mode 100644 index 0000000..bdfa1dc --- /dev/null +++ b/sim/testsuite/sim/frv/nfadds.cgs @@ -0,0 +1,179 @@ +# frv testcase for nfadds $GRi,$GRj,$GRk +# mach: fr500 fr550 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global nfadds +nfadds: + nfadds fr16,fr0,fr1 + test_fr_fr fr1,fr0 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfadds fr16,fr4,fr1 + test_fr_fr fr1,fr4 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfadds fr16,fr8,fr1 + test_fr_fr fr1,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfadds fr16,fr12,fr1 + test_fr_fr fr1,fr12 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfadds fr16,fr16,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfadds fr16,fr20,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfadds fr16,fr24,fr1 + test_fr_fr fr1,fr24 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfadds fr16,fr28,fr1 + test_fr_fr fr1,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfadds fr16,fr32,fr1 + test_fr_fr fr1,fr32 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfadds fr16,fr36,fr1 + test_fr_fr fr1,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfadds fr16,fr40,fr1 + test_fr_fr fr1,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfadds fr16,fr44,fr1 + test_fr_fr fr1,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfadds fr16,fr48,fr1 + test_fr_fr fr1,fr48 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfadds fr16,fr52,fr1 + test_fr_fr fr1,fr52 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfadds fr20,fr0,fr1 + test_fr_fr fr1,fr0 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfadds fr20,fr4,fr1 + test_fr_fr fr1,fr4 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfadds fr20,fr8,fr1 + test_fr_fr fr1,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfadds fr20,fr12,fr1 + test_fr_fr fr1,fr12 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfadds fr20,fr16,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfadds fr20,fr20,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfadds fr20,fr24,fr1 + test_fr_fr fr1,fr24 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfadds fr20,fr28,fr1 + test_fr_fr fr1,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfadds fr20,fr32,fr1 + test_fr_fr fr1,fr32 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfadds fr20,fr36,fr1 + test_fr_fr fr1,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfadds fr20,fr40,fr1 + test_fr_fr fr1,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfadds fr20,fr44,fr1 + test_fr_fr fr1,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfadds fr20,fr48,fr1 + test_fr_fr fr1,fr48 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfadds fr20,fr52,fr1 + test_fr_fr fr1,fr52 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfadds fr8,fr28,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfadds fr12,fr24,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfadds fr24,fr12,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfadds fr28,fr8,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfadds fr36,fr40,fr1 + test_fr_fr fr1,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + ; try to cause exceptions + nfadds fr48,fr28,fr1 +; test_fr_fr fr1,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfadds fr52,fr28,fr1 +; test_fr_fr fr1,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfadds fr56,fr28,fr1 +; test_fr_fr fr1,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfadds fr60,fr28,fr1 +; test_fr_fr fr1,fr44 + test_spr_immed 2,fner1 + test_spr_immed 0,fner0 + + pass + + diff --git a/sim/testsuite/sim/frv/nfdadds.cgs b/sim/testsuite/sim/frv/nfdadds.cgs new file mode 100644 index 0000000..0be25e7 --- /dev/null +++ b/sim/testsuite/sim/frv/nfdadds.cgs @@ -0,0 +1,225 @@ +# frv testcase for nfdadds $FRi,$FRj,$FRk +# mach: fr500 fr550 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + load_float_constants1 + + .global nfdadds +nfdadds: + nfdadds fr16,fr0,fr2 + test_fr_fr fr2,fr0 + test_fr_fr fr3,fr0 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdadds fr16,fr4,fr2 + test_fr_fr fr2,fr4 + test_fr_fr fr3,fr4 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdadds fr16,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdadds fr16,fr12,fr2 + test_fr_fr fr2,fr12 + test_fr_fr fr3,fr12 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdadds fr16,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdadds fr16,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdadds fr16,fr24,fr2 + test_fr_fr fr2,fr24 + test_fr_fr fr3,fr24 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdadds fr16,fr28,fr2 + test_fr_fr fr2,fr28 + test_fr_fr fr3,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdadds fr16,fr32,fr2 + test_fr_fr fr2,fr32 + test_fr_fr fr3,fr32 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdadds fr16,fr36,fr2 + test_fr_fr fr2,fr36 + test_fr_fr fr3,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdadds fr16,fr40,fr2 + test_fr_fr fr2,fr40 + test_fr_fr fr3,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdadds fr16,fr44,fr2 + test_fr_fr fr2,fr44 + test_fr_fr fr3,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdadds fr16,fr48,fr2 + test_fr_fr fr2,fr48 + test_fr_fr fr3,fr48 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdadds fr16,fr52,fr2 + test_fr_fr fr2,fr52 + test_fr_fr fr3,fr52 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdadds fr20,fr0,fr2 + test_fr_fr fr2,fr0 + test_fr_fr fr3,fr0 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdadds fr20,fr4,fr2 + test_fr_fr fr2,fr4 + test_fr_fr fr3,fr4 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdadds fr20,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdadds fr20,fr12,fr2 + test_fr_fr fr2,fr12 + test_fr_fr fr3,fr12 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdadds fr20,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdadds fr20,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdadds fr20,fr24,fr2 + test_fr_fr fr2,fr24 + test_fr_fr fr3,fr24 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdadds fr20,fr28,fr2 + test_fr_fr fr2,fr28 + test_fr_fr fr3,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdadds fr20,fr32,fr2 + test_fr_fr fr2,fr32 + test_fr_fr fr3,fr32 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdadds fr20,fr36,fr2 + test_fr_fr fr2,fr36 + test_fr_fr fr3,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdadds fr20,fr40,fr2 + test_fr_fr fr2,fr40 + test_fr_fr fr3,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdadds fr20,fr44,fr2 + test_fr_fr fr2,fr44 + test_fr_fr fr3,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdadds fr20,fr48,fr2 + test_fr_fr fr2,fr48 + test_fr_fr fr3,fr48 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdadds fr20,fr52,fr2 + test_fr_fr fr2,fr52 + test_fr_fr fr3,fr52 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdadds fr8,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdadds fr12,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdadds fr24,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdadds fr28,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdadds fr36,fr40,fr2 + test_fr_fr fr2,fr44 + test_fr_fr fr3,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + ; try to cause exceptions + nfdadds fr48,fr28,fr2 +; test_fr_fr fr2,fr44 +; test_fr_fr fr3,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdadds fr52,fr28,fr2 +; test_fr_fr fr2,fr44 +; test_fr_fr fr3,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdadds fr56,fr28,fr2 +; test_fr_fr fr2,fr44 +; test_fr_fr fr3,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdadds fr60,fr28,fr2 +; test_fr_fr fr2,fr44 +; test_fr_fr fr3,fr44 + test_spr_immed 0xc,fner1 + test_spr_immed 0,fner0 + + pass + + diff --git a/sim/testsuite/sim/frv/nfdcmps.cgs b/sim/testsuite/sim/frv/nfdcmps.cgs new file mode 100644 index 0000000..977805a --- /dev/null +++ b/sim/testsuite/sim/frv/nfdcmps.cgs @@ -0,0 +1,1549 @@ +# frv testcase for nfdcmps $FRi,$FRj,$FCCi_2 +# mach: frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + load_float_constants1 + + .global nfdcmps +nfdcmps: + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + nfdcmps fr0,fr0,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr0,fr4,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr0,fr8,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr0,fr12,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr0,fr16,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr0,fr20,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr0,fr24,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr0,fr28,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr0,fr32,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr0,fr36,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr0,fr40,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr0,fr44,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr0,fr48,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr0,fr52,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr0,fr56,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr0,fr60,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr4,fr0,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + nfdcmps fr4,fr4,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr4,fr8,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr4,fr12,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr4,fr16,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr4,fr20,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr4,fr24,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr4,fr28,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr4,fr32,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr4,fr36,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr4,fr40,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr4,fr44,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr4,fr48,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr4,fr52,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr4,fr56,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr4,fr60,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr8,fr0,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr8,fr4,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + nfdcmps fr8,fr8,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr8,fr12,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr8,fr16,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr8,fr20,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr8,fr24,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr8,fr28,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr8,fr32,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr8,fr36,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr8,fr40,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr8,fr44,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr8,fr48,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr8,fr52,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr8,fr56,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr8,fr60,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr12,fr0,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr12,fr4,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr12,fr8,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + nfdcmps fr12,fr12,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr12,fr16,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr12,fr20,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr12,fr24,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr12,fr28,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr12,fr32,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr12,fr36,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr12,fr40,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr12,fr44,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr12,fr48,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr12,fr52,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr12,fr56,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr12,fr60,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr16,fr0,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr16,fr4,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr16,fr8,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr16,fr12,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + nfdcmps fr16,fr16,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + nfdcmps fr16,fr20,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr16,fr24,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr16,fr28,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr16,fr32,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr16,fr36,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr16,fr40,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr16,fr44,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr16,fr48,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr16,fr52,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr16,fr56,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr16,fr60,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr20,fr0,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr20,fr4,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr20,fr8,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr20,fr12,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + nfdcmps fr20,fr16,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + nfdcmps fr20,fr20,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr20,fr24,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr20,fr28,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr20,fr32,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr20,fr36,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr20,fr40,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr20,fr44,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr20,fr48,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr20,fr52,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr20,fr56,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr20,fr60,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr24,fr0,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr24,fr4,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr24,fr8,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr24,fr12,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr24,fr16,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr24,fr20,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + nfdcmps fr24,fr24,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr24,fr28,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr24,fr32,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr24,fr36,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr24,fr40,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr24,fr44,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr24,fr48,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr24,fr52,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr24,fr56,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr24,fr60,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr28,fr0,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr28,fr4,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr28,fr8,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr28,fr12,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr28,fr16,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr28,fr20,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr28,fr24,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + nfdcmps fr28,fr28,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr28,fr32,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr28,fr36,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr28,fr40,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr28,fr44,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr28,fr48,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr28,fr52,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr28,fr56,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr28,fr60,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr48,fr0,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr48,fr4,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr48,fr8,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr48,fr12,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr48,fr16,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr48,fr20,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr48,fr24,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr48,fr28,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr48,fr32,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr48,fr36,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr48,fr40,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr48,fr44,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + nfdcmps fr48,fr48,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xb,0 ; Set mask opposite of expected + set_fcc 0xb,1 ; Set mask opposite of expected + nfdcmps fr48,fr52,fcc0 + test_fcc 0x4,0 + test_fcc 0x4,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr48,fr56,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr48,fr60,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr52,fr0,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr52,fr4,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr52,fr8,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr52,fr12,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr52,fr16,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr52,fr20,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr52,fr24,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr52,fr28,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr52,fr32,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr52,fr36,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr52,fr40,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr52,fr44,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xd,0 ; Set mask opposite of expected + set_fcc 0xd,1 ; Set mask opposite of expected + nfdcmps fr52,fr48,fcc0 + test_fcc 0x2,0 + test_fcc 0x2,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0x7,0 ; Set mask opposite of expected + set_fcc 0x7,1 ; Set mask opposite of expected + nfdcmps fr52,fr52,fcc0 + test_fcc 0x8,0 + test_fcc 0x8,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr52,fr56,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr52,fr60,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr56,fr0,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr56,fr4,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr56,fr8,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr56,fr12,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr56,fr16,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr56,fr20,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr56,fr24,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr56,fr28,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr56,fr32,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr56,fr36,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr56,fr40,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr56,fr44,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr56,fr48,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr56,fr52,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr56,fr56,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr56,fr60,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr60,fr0,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr60,fr4,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr60,fr8,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr60,fr12,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr60,fr16,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr60,fr20,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr60,fr24,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr60,fr28,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr60,fr32,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr60,fr36,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr60,fr40,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr60,fr44,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr60,fr48,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr60,fr52,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr60,fr56,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fcc 0xe,0 ; Set mask opposite of expected + set_fcc 0xe,1 ; Set mask opposite of expected + nfdcmps fr60,fr60,fcc0 + test_fcc 0x1,0 + test_fcc 0x1,1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + pass diff --git a/sim/testsuite/sim/frv/nfddivs.cgs b/sim/testsuite/sim/frv/nfddivs.cgs new file mode 100644 index 0000000..0b16447 --- /dev/null +++ b/sim/testsuite/sim/frv/nfddivs.cgs @@ -0,0 +1,306 @@ +# frv testcase for nfddivs $FRi,$FRj,$FRk +# mach: frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + load_float_constants1 + + .global nfddivs +nfddivs: + nfddivs fr0,fr28,fr2 + test_fr_fr fr2,fr0 + test_fr_fr fr3,fr0 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr4,fr28,fr2 + test_fr_fr fr2,fr4 + test_fr_fr fr3,fr4 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr8,fr28,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr12,fr28,fr2 + test_fr_fr fr2,fr12 + test_fr_fr fr3,fr12 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr16,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr20,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr24,fr28,fr2 + test_fr_fr fr2,fr24 + test_fr_fr fr3,fr24 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr28,fr28,fr2 + test_fr_fr fr2,fr28 + test_fr_fr fr3,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr32,fr28,fr2 + test_fr_fr fr2,fr32 + test_fr_fr fr3,fr32 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr36,fr28,fr2 + test_fr_fr fr2,fr36 + test_fr_fr fr3,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr40,fr28,fr2 + test_fr_fr fr2,fr40 + test_fr_fr fr3,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr44,fr28,fr2 + test_fr_fr fr2,fr44 + test_fr_fr fr3,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr48,fr28,fr2 + test_fr_fr fr2,fr48 + test_fr_fr fr3,fr48 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr52,fr28,fr2 + test_fr_fr fr2,fr52 + test_fr_fr fr3,fr52 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfddivs fr16,fr0,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr16,fr4,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr16,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr16,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr16,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr16,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr16,fr32,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr16,fr36,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr16,fr40,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr16,fr44,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr16,fr48,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr16,fr52,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfddivs fr20,fr0,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr20,fr4,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr20,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr20,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr20,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr20,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr20,fr32,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr20,fr36,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr20,fr40,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr20,fr44,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr20,fr48,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr20,fr52,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfddivs fr8,fr28,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfddivs fr28,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfddivs fr40,fr32,fr2 + test_fr_fr fr2,fr36 + test_fr_fr fr3,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + ; try to cause exceptions + set_spr_immed 0,fner0 + set_spr_immed 0,fner1 + nfddivs fr48,fr20,fr2 +; test_fr_fr fr2,fr44 +; test_fr_fr fr3,fr44 + test_spr_immed 0xc,fner1 + test_spr_immed 0,fner0 + + set_spr_immed 0,fner0 + set_spr_immed 0,fner1 + nfddivs fr52,fr16,fr2 +; test_fr_fr fr2,fr44 +; test_fr_fr fr3,fr44 + test_spr_immed 0x0,fner1 + test_spr_immed 0,fner0 + + nfddivs fr56,fr28,fr2 +; test_fr_fr fr2,fr44 +; test_fr_fr fr3,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfddivs fr60,fr28,fr2 +; test_fr_fr fr2,fr44 +; test_fr_fr fr3,fr44 + test_spr_immed 0xc,fner1 + test_spr_immed 0,fner0 + + pass + + diff --git a/sim/testsuite/sim/frv/nfditos.cgs b/sim/testsuite/sim/frv/nfditos.cgs new file mode 100644 index 0000000..1200944 --- /dev/null +++ b/sim/testsuite/sim/frv/nfditos.cgs @@ -0,0 +1,31 @@ +# frv testcase for nfditos $FRj,$FRk +# mach: frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global nfditos +nfditos: + set_fr_iimmed 0,0,fr2 + set_fr_iimmed 0x0000,0x0002,fr3 + nfditos fr2,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr32 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fr_iimmed 0xdead,0xbeef,fr2 + set_fr_iimmed 0xdead,0xbeef,fr3 + nfditos fr2,fr2 + test_fr_iimmed 0xce054904,fr2 + test_fr_iimmed 0xce054904,fr3 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + ; TODO test cases to set ne flags + + pass diff --git a/sim/testsuite/sim/frv/nfdivs.cgs b/sim/testsuite/sim/frv/nfdivs.cgs new file mode 100644 index 0000000..73e58b8 --- /dev/null +++ b/sim/testsuite/sim/frv/nfdivs.cgs @@ -0,0 +1,234 @@ +# frv testcase for nfdivs $FRi,$FRj,$FRk +# mach: fr500 fr550 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global nfdivs +nfdivs: + nfdivs fr0,fr28,fr1 + test_fr_fr fr1,fr0 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr4,fr28,fr1 + test_fr_fr fr1,fr4 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr8,fr28,fr1 + test_fr_fr fr1,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr12,fr28,fr1 + test_fr_fr fr1,fr12 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr16,fr28,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr20,fr28,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr24,fr28,fr1 + test_fr_fr fr1,fr24 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr28,fr28,fr1 + test_fr_fr fr1,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr32,fr28,fr1 + test_fr_fr fr1,fr32 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr36,fr28,fr1 + test_fr_fr fr1,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr40,fr28,fr1 + test_fr_fr fr1,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr44,fr28,fr1 + test_fr_fr fr1,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr48,fr28,fr1 + test_fr_fr fr1,fr48 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr52,fr28,fr1 + test_fr_fr fr1,fr52 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdivs fr16,fr0,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr16,fr4,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr16,fr8,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr16,fr12,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr16,fr24,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr16,fr28,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr16,fr32,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr16,fr36,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr16,fr40,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr16,fr44,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr16,fr48,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr16,fr52,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdivs fr20,fr0,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr20,fr4,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr20,fr8,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr20,fr12,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr20,fr24,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr20,fr28,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr20,fr32,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr20,fr36,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr20,fr40,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr20,fr44,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr20,fr48,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr20,fr52,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdivs fr8,fr28,fr1 + test_fr_fr fr1,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdivs fr28,fr8,fr1 + test_fr_fr fr1,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdivs fr40,fr32,fr1 + test_fr_fr fr1,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + ; try to cause exceptions + set_spr_immed 0,fner0 + set_spr_immed 0,fner1 + nfdivs fr48,fr20,fr1 +; test_fr_fr fr1,fr44 + test_spr_immed 2,fner1 + test_spr_immed 0,fner0 + + set_spr_immed 0,fner0 + set_spr_immed 0,fner1 + nfdivs fr52,fr16,fr1 +; test_fr_fr fr1,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdivs fr56,fr28,fr1 +; test_fr_fr fr1,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdivs fr60,fr28,fr1 +; test_fr_fr fr1,fr44 + test_spr_immed 2,fner1 + test_spr_immed 0,fner0 + + pass + + diff --git a/sim/testsuite/sim/frv/nfdmadds.cgs b/sim/testsuite/sim/frv/nfdmadds.cgs new file mode 100644 index 0000000..1af110c --- /dev/null +++ b/sim/testsuite/sim/frv/nfdmadds.cgs @@ -0,0 +1,310 @@ +# frv testcase for nfdmadds $GRi,$GRj,$GRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + load_float_constants1 + + .global nfdmadds +nfdmadds: + nfdmadds fr16,fr4,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmadds fr16,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmadds fr16,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmadds fr16,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmadds fr16,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmadds fr16,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmadds fr16,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmadds fr16,fr32,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmadds fr16,fr36,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmadds fr16,fr40,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmadds fr16,fr44,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmadds fr16,fr48,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdmadds fr20,fr4,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmadds fr20,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmadds fr20,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmadds fr20,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmadds fr20,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmadds fr20,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmadds fr20,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmadds fr20,fr32,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmadds fr20,fr36,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmadds fr20,fr40,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmadds fr20,fr44,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmadds fr20,fr48,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fr_fr fr16,fr2 + set_fr_fr fr16,fr3 + nfdmadds fr28,fr0,fr2 + test_fr_fr fr2,fr0 + test_fr_fr fr3,fr0 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr2 + set_fr_fr fr16,fr3 + nfdmadds fr28,fr4,fr2 + test_fr_fr fr2,fr4 + test_fr_fr fr3,fr4 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr2 + set_fr_fr fr16,fr3 + nfdmadds fr28,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr2 + set_fr_fr fr16,fr3 + nfdmadds fr28,fr12,fr2 + test_fr_fr fr2,fr12 + test_fr_fr fr3,fr12 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr2 + set_fr_fr fr16,fr3 + nfdmadds fr28,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr2 + set_fr_fr fr16,fr3 + nfdmadds fr28,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr2 + set_fr_fr fr16,fr3 + nfdmadds fr28,fr24,fr2 + test_fr_fr fr2,fr24 + test_fr_fr fr3,fr24 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr2 + set_fr_fr fr16,fr3 + nfdmadds fr28,fr28,fr2 + test_fr_fr fr2,fr28 + test_fr_fr fr3,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr2 + set_fr_fr fr16,fr3 + nfdmadds fr28,fr32,fr2 + test_fr_fr fr2,fr32 + test_fr_fr fr3,fr32 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr2 + set_fr_fr fr16,fr3 + nfdmadds fr28,fr36,fr2 + test_fr_fr fr2,fr36 + test_fr_fr fr3,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr2 + set_fr_fr fr16,fr3 + nfdmadds fr28,fr40,fr2 + test_fr_fr fr2,fr40 + test_fr_fr fr3,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr2 + set_fr_fr fr16,fr3 + nfdmadds fr28,fr44,fr2 + test_fr_fr fr2,fr44 + test_fr_fr fr3,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr2 + set_fr_fr fr16,fr3 + nfdmadds fr28,fr48,fr2 + test_fr_fr fr2,fr48 + test_fr_fr fr3,fr48 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr2 + set_fr_fr fr16,fr3 + nfdmadds fr28,fr52,fr2 + test_fr_fr fr2,fr52 + test_fr_fr fr3,fr52 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fr_fr fr36,fr2 + set_fr_fr fr36,fr3 + nfdmadds fr28,fr8,fr2 + test_fr_fr fr2,fr32 + test_fr_fr fr3,fr32 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmadds fr8,fr28,fr2 + test_fr_fr fr2,fr28 + test_fr_fr fr3,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fr_fr fr36,fr2 + set_fr_fr fr36,fr3 + nfdmadds fr32,fr36,fr2 + test_fr_fr fr2,fr44 + test_fr_fr fr3,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + ; TODO -- test cases to set ne flags + + pass diff --git a/sim/testsuite/sim/frv/nfdmas.cgs b/sim/testsuite/sim/frv/nfdmas.cgs new file mode 100644 index 0000000..07f76aa --- /dev/null +++ b/sim/testsuite/sim/frv/nfdmas.cgs @@ -0,0 +1,349 @@ +# frv testcase for nfdmas $FRi,$FRj,$FRk +# mach: frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + load_float_constants1 + load_float_constants2 + load_float_constants3 + + .global nfdmas +nfdmas: + nfdmas fr16,fr4,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr4 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr4 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr16,fr8,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr8 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr16,fr12,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr12 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr12 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr16,fr16,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr16 + test_fr_fr fr61,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr16 + test_fr_fr fr63,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr16,fr20,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr16 + test_fr_fr fr61,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr16 + test_fr_fr fr63,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr16,fr24,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr24 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr24 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr16,fr28,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr28 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr16,fr32,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr32 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr32 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr16,fr36,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr36 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr16,fr40,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr40 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr16,fr44,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr44 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr16,fr48,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr48 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr48 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdmas fr20,fr4,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr4 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr4 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr20,fr8,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr8 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr20,fr12,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr12 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr12 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr20,fr16,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr16 + test_fr_fr fr61,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr16 + test_fr_fr fr63,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr20,fr20,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr16 + test_fr_fr fr61,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr16 + test_fr_fr fr63,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr20,fr24,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr24 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr24 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr20,fr28,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr28 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr20,fr32,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr32 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr32 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr20,fr36,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr36 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr20,fr40,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr40 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr20,fr44,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr44 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr20,fr48,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr48 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr48 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdmas fr28,fr0,fr60 + test_fr_fr fr60,fr0 + test_fr_fr fr62,fr0 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr28,fr4,fr60 + test_fr_fr fr60,fr4 + test_fr_fr fr62,fr4 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr28,fr8,fr60 + test_fr_fr fr60,fr8 + test_fr_fr fr61,fr16 + test_fr_fr fr61,fr20 + test_fr_fr fr62,fr8 + test_fr_fr fr63,fr16 + test_fr_fr fr63,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr28,fr12,fr60 + test_fr_fr fr60,fr12 + test_fr_fr fr62,fr12 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr28,fr16,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr28,fr20,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr28,fr24,fr60 + test_fr_fr fr60,fr24 + test_fr_fr fr62,fr24 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr28,fr28,fr60 + test_fr_fr fr60,fr28 + test_fr_fr fr62,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr28,fr32,fr60 + test_fr_fr fr60,fr32 + test_fr_fr fr61,fr36 + test_fr_fr fr62,fr32 + test_fr_fr fr63,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr28,fr36,fr60 + test_fr_fr fr60,fr36 + test_fr_fr fr62,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr28,fr40,fr60 + test_fr_fr fr60,fr40 + test_fr_fr fr62,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr28,fr44,fr60 + test_fr_fr fr60,fr44 + test_fr_fr fr62,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr28,fr48,fr60 + test_fr_fr fr60,fr48 + test_fr_fr fr62,fr48 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr28,fr52,fr60 + test_fr_fr fr60,fr52 + test_fr_fr fr62,fr52 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdmas fr28,fr8,fr60 + test_fr_fr fr60,fr8 + test_fr_fr fr61,fr16 + test_fr_fr fr61,fr20 + test_fr_fr fr62,fr8 + test_fr_fr fr63,fr16 + test_fr_fr fr63,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmas fr8,fr28,fr60 + test_fr_fr fr60,fr8 + test_fr_fr fr61,fr16 + test_fr_fr fr61,fr20 + test_fr_fr fr62,fr8 + test_fr_fr fr63,fr16 + test_fr_fr fr63,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdmas fr32,fr36,fr60 + test_fr_fr fr60,fr40 + test_fr_fr fr62,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + ; TODO -- test cases to set ne flags + + pass diff --git a/sim/testsuite/sim/frv/nfdmss.cgs b/sim/testsuite/sim/frv/nfdmss.cgs new file mode 100644 index 0000000..3633d70 --- /dev/null +++ b/sim/testsuite/sim/frv/nfdmss.cgs @@ -0,0 +1,319 @@ +# frv testcase for nfdmss $FRi,$FRj,$FRk +# mach: frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + load_float_constants1 + load_float_constants2 + load_float_constants3 + + .global nfdmss +nfdmss: + nfdmss fr16,fr4,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr16,fr8,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr28 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr16,fr12,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr16,fr16,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr16 + test_fr_fr fr61,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr16 + test_fr_fr fr63,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr16,fr20,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr16 + test_fr_fr fr61,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr16 + test_fr_fr fr63,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr16,fr24,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr16,fr28,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr8 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr16,fr32,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr16,fr36,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr16,fr40,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr16,fr44,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr16,fr48,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdmss fr20,fr4,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr20,fr8,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr28 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr20,fr12,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr20,fr16,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr16 + test_fr_fr fr61,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr16 + test_fr_fr fr63,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr20,fr20,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr16 + test_fr_fr fr61,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr16 + test_fr_fr fr63,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr20,fr24,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr20,fr28,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr8 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr20,fr32,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr20,fr36,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr20,fr40,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr20,fr44,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr20,fr48,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdmss fr28,fr0,fr60 + test_fr_fr fr60,fr0 + test_fr_fr fr62,fr0 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr28,fr4,fr60 + test_fr_fr fr60,fr4 + test_fr_fr fr62,fr4 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr28,fr8,fr60 + test_fr_fr fr60,fr8 + test_fr_fr fr61,fr32 + test_fr_fr fr62,fr8 + test_fr_fr fr63,fr32 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr28,fr12,fr60 + test_fr_fr fr60,fr12 + test_fr_fr fr62,fr12 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr28,fr16,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr28 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr28,fr20,fr60 + test_fr_fr fr60,fr16 + test_fr_fr fr60,fr20 + test_fr_fr fr61,fr28 + test_fr_fr fr62,fr16 + test_fr_fr fr62,fr20 + test_fr_fr fr63,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr28,fr24,fr60 + test_fr_fr fr60,fr24 + test_fr_fr fr62,fr24 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr28,fr28,fr60 + test_fr_fr fr60,fr28 + test_fr_fr fr61,fr20 + test_fr_fr fr61,fr16 + test_fr_fr fr62,fr28 + test_fr_fr fr63,fr20 + test_fr_fr fr63,fr16 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr28,fr32,fr60 + test_fr_fr fr60,fr32 + test_fr_fr fr61,fr8 + test_fr_fr fr62,fr32 + test_fr_fr fr63,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr28,fr36,fr60 + test_fr_fr fr60,fr36 + test_fr_fr fr62,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr28,fr40,fr60 + test_fr_fr fr60,fr40 + test_fr_fr fr62,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr28,fr44,fr60 + test_fr_fr fr60,fr44 + test_fr_fr fr62,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr28,fr48,fr60 + test_fr_fr fr60,fr48 + test_fr_fr fr62,fr48 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr28,fr52,fr60 + test_fr_fr fr60,fr52 + test_fr_fr fr62,fr52 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdmss fr28,fr8,fr60 + test_fr_fr fr60,fr8 + test_fr_fr fr61,fr32 + test_fr_fr fr62,fr8 + test_fr_fr fr63,fr32 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmss fr8,fr28,fr60 + test_fr_fr fr60,fr8 + test_fr_fr fr62,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdmss fr32,fr36,fr60 + test_fr_fr fr60,fr40 + test_fr_fr fr61,fr8 + test_fr_fr fr62,fr40 + test_fr_fr fr63,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + ; TODO -- test cases to set ne flags + + pass diff --git a/sim/testsuite/sim/frv/nfdmulcs.cgs b/sim/testsuite/sim/frv/nfdmulcs.cgs new file mode 100644 index 0000000..227ff29 --- /dev/null +++ b/sim/testsuite/sim/frv/nfdmulcs.cgs @@ -0,0 +1,313 @@ +# frv testcase for nfdmulcs $FRi,$FRj,$FRk +# mach: fr500 fr550 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + load_float_constants1 + + .global nfdmulcs +nfdmulcs: + nfdmulcs fr16,fr4,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr16,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr16,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr16,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr16,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr16,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr16,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr16,fr32,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr16,fr36,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr16,fr40,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr16,fr44,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr16,fr48,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdmulcs fr20,fr4,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr20,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr20,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr20,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr3,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr2,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr20,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr20,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr20,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr20,fr32,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr20,fr36,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr20,fr40,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr20,fr44,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr20,fr48,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdmulcs fr28,fr0,fr2 + test_fr_fr fr2,fr0 + test_fr_fr fr3,fr0 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr28,fr4,fr2 + test_fr_fr fr2,fr4 + test_fr_fr fr3,fr4 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr28,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr28,fr12,fr2 + test_fr_fr fr2,fr12 + test_fr_fr fr3,fr12 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr28,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr28,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr28,fr24,fr2 + test_fr_fr fr2,fr24 + test_fr_fr fr3,fr24 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr28,fr28,fr2 + test_fr_fr fr2,fr28 + test_fr_fr fr3,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr28,fr32,fr2 + test_fr_fr fr2,fr32 + test_fr_fr fr3,fr32 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr28,fr36,fr2 + test_fr_fr fr2,fr36 + test_fr_fr fr3,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr28,fr40,fr2 + test_fr_fr fr2,fr40 + test_fr_fr fr3,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr28,fr44,fr2 + test_fr_fr fr2,fr44 + test_fr_fr fr3,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr28,fr48,fr2 + test_fr_fr fr2,fr48 + test_fr_fr fr3,fr48 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr28,fr52,fr2 + test_fr_fr fr2,fr52 + test_fr_fr fr3,fr52 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdmulcs fr28,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmulcs fr8,fr28,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdmulcs fr32,fr36,fr2 + test_fr_fr fr2,fr40 + test_fr_fr fr3,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + ; try to cause exceptions + nfdmulcs fr48,fr32,fr2 +; test_fr_fr fr2,fr44 +; test_fr_fr fr3,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdmulcs fr52,fr28,fr2 +; test_fr_fr fr2,fr44 +; test_fr_fr fr3,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdmulcs fr56,fr28,fr2 +; test_fr_fr fr2,fr44 +; test_fr_fr fr3,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdmulcs fr60,fr28,fr2 +; test_fr_fr fr2,fr44 +; test_fr_fr fr3,fr44 + test_spr_immed 0xc,fner1 + test_spr_immed 0,fner0 + + ; test all regs different + set_spr_immed 0,fner0 + set_spr_immed 0,fner1 + set_fr_fr fr32,fr50 ; 2 + set_fr_fr fr28,fr51 ; 1 + set_fr_fr fr44,fr52 ; 9 + set_fr_fr fr36,fr53 ; 3 + nfdmulcs fr50,fr52,fr54 ; 2*3, 1*9 + test_fr_fr fr54,fr40 ; 6 + test_fr_fr fr55,fr44 ; 9 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + pass diff --git a/sim/testsuite/sim/frv/nfdmuls.cgs b/sim/testsuite/sim/frv/nfdmuls.cgs new file mode 100644 index 0000000..efe1580 --- /dev/null +++ b/sim/testsuite/sim/frv/nfdmuls.cgs @@ -0,0 +1,300 @@ +# frv testcase for nfdmuls $FRi,$FRj,$FRk +# mach: fr500 fr550 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + load_float_constants1 + + .global nfdmuls +nfdmuls: + nfdmuls fr16,fr4,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr16,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr16,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr16,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr16,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr16,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr16,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr16,fr32,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr16,fr36,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr16,fr40,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr16,fr44,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr16,fr48,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdmuls fr20,fr4,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr20,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr20,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr20,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr3,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr2,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr20,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr20,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr20,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr20,fr32,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr20,fr36,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr20,fr40,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr20,fr44,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr20,fr48,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdmuls fr28,fr0,fr2 + test_fr_fr fr2,fr0 + test_fr_fr fr3,fr0 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr28,fr4,fr2 + test_fr_fr fr2,fr4 + test_fr_fr fr3,fr4 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr28,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr28,fr12,fr2 + test_fr_fr fr2,fr12 + test_fr_fr fr3,fr12 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr28,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr28,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr28,fr24,fr2 + test_fr_fr fr2,fr24 + test_fr_fr fr3,fr24 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr28,fr28,fr2 + test_fr_fr fr2,fr28 + test_fr_fr fr3,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr28,fr32,fr2 + test_fr_fr fr2,fr32 + test_fr_fr fr3,fr32 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr28,fr36,fr2 + test_fr_fr fr2,fr36 + test_fr_fr fr3,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr28,fr40,fr2 + test_fr_fr fr2,fr40 + test_fr_fr fr3,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr28,fr44,fr2 + test_fr_fr fr2,fr44 + test_fr_fr fr3,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr28,fr48,fr2 + test_fr_fr fr2,fr48 + test_fr_fr fr3,fr48 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr28,fr52,fr2 + test_fr_fr fr2,fr52 + test_fr_fr fr3,fr52 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdmuls fr28,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdmuls fr8,fr28,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdmuls fr32,fr36,fr2 + test_fr_fr fr2,fr40 + test_fr_fr fr3,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + ; try to cause exceptions + nfdmuls fr48,fr32,fr2 +; test_fr_fr fr2,fr44 +; test_fr_fr fr3,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdmuls fr52,fr28,fr2 +; test_fr_fr fr2,fr44 +; test_fr_fr fr3,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdmuls fr56,fr28,fr2 +; test_fr_fr fr2,fr44 +; test_fr_fr fr3,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdmuls fr60,fr28,fr2 +; test_fr_fr fr2,fr44 +; test_fr_fr fr3,fr44 + test_spr_immed 0xc,fner1 + test_spr_immed 0,fner0 + + pass diff --git a/sim/testsuite/sim/frv/nfdsads.cgs b/sim/testsuite/sim/frv/nfdsads.cgs new file mode 100644 index 0000000..6c06f16 --- /dev/null +++ b/sim/testsuite/sim/frv/nfdsads.cgs @@ -0,0 +1,212 @@ +# frv testcase for nfdsads $FRi,$FRj,$FRk +# mach: fr500 fr550 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + load_float_constants1 + + .global nfdsads +nfdsads: + nfdsads fr16,fr0,fr2 + test_fr_fr fr2,fr0 + test_fr_fr fr3,fr52 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsads fr16,fr4,fr2 + test_fr_fr fr2,fr4 + test_fr_fr fr3,fr48 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsads fr16,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsads fr16,fr12,fr2 + test_fr_fr fr2,fr12 + test_fr_fr fr3,fr24 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsads fr16,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsads fr16,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsads fr16,fr24,fr2 + test_fr_fr fr2,fr24 + test_fr_fr fr3,fr12 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsads fr16,fr28,fr2 + test_fr_fr fr2,fr28 + test_fr_fr fr3,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsads fr16,fr32,fr2 + test_fr_fr fr2,fr32 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsads fr16,fr36,fr2 + test_fr_fr fr2,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsads fr16,fr40,fr2 + test_fr_fr fr2,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsads fr16,fr44,fr2 + test_fr_fr fr2,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsads fr16,fr48,fr2 + test_fr_fr fr2,fr48 + test_fr_fr fr3,fr4 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsads fr16,fr52,fr2 + test_fr_fr fr2,fr52 + test_fr_fr fr3,fr0 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdsads fr20,fr0,fr2 + test_fr_fr fr2,fr0 + test_fr_fr fr3,fr52 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsads fr20,fr4,fr2 + test_fr_fr fr2,fr4 + test_fr_fr fr3,fr48 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsads fr20,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsads fr20,fr12,fr2 + test_fr_fr fr2,fr12 + test_fr_fr fr3,fr24 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsads fr20,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsads fr20,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsads fr20,fr24,fr2 + test_fr_fr fr2,fr24 + test_fr_fr fr3,fr12 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsads fr20,fr28,fr2 + test_fr_fr fr2,fr28 + test_fr_fr fr3,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsads fr20,fr32,fr2 + test_fr_fr fr2,fr32 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsads fr20,fr36,fr2 + test_fr_fr fr2,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsads fr20,fr40,fr2 + test_fr_fr fr2,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsads fr20,fr44,fr2 + test_fr_fr fr2,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsads fr20,fr48,fr2 + test_fr_fr fr2,fr48 + test_fr_fr fr3,fr4 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsads fr20,fr52,fr2 + test_fr_fr fr2,fr52 + test_fr_fr fr3,fr0 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdsads fr8,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsads fr12,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsads fr24,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsads fr28,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr32 + test_fr_fr fr3,fr32 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdsads fr36,fr40,fr2 + test_fr_fr fr2,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + ; try to cause exceptions + set_fr_fr fr4,fr49 + nfdsads fr48,fr28,fr2 +; test_fr_fr fr2,fr44 +; test_fr_fr fr3,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fr_fr fr0,fr53 + nfdsads fr52,fr28,fr2 +; test_fr_fr fr2,fr44 +; test_fr_fr fr3,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdsads fr56,fr28,fr2 +; test_fr_fr fr2,fr44 +; test_fr_fr fr3,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdsads fr60,fr28,fr2 +; test_fr_fr fr2,fr44 +; test_fr_fr fr3,fr44 + test_spr_immed 0xc,fner1 + test_spr_immed 0,fner0 + + pass + + diff --git a/sim/testsuite/sim/frv/nfdsqrts.cgs b/sim/testsuite/sim/frv/nfdsqrts.cgs new file mode 100644 index 0000000..1a906bb --- /dev/null +++ b/sim/testsuite/sim/frv/nfdsqrts.cgs @@ -0,0 +1,21 @@ +# frv testcase for nfdsqrts $FRj,$FRk +# mach: frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global nfdsqrts +nfdsqrts: + set_fr_iimmed 0x4049,0x0fdb,fr45 ; 3.141592654 + nfdsqrts fr44,fr2 ; 9.0 + test_fr_fr fr2,fr36 ; 3.0 + test_fr_iimmed 0x3fe2dfc5,fr3 ; 1.7724539 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + ; TODO test cases to set ne flags + + pass diff --git a/sim/testsuite/sim/frv/nfdstoi.cgs b/sim/testsuite/sim/frv/nfdstoi.cgs new file mode 100644 index 0000000..56dc941 --- /dev/null +++ b/sim/testsuite/sim/frv/nfdstoi.cgs @@ -0,0 +1,29 @@ +# frv testcase for nfdstoi $FRj,$FRk +# mach: frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global nfdstoi +nfdstoi: + set_fr_fr fr20,fr17 + nfdstoi fr16,fr2 + test_fr_iimmed 0,fr2 + test_fr_iimmed 0,fr3 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fr_iimmed 0xce05,0x4904,fr2 + set_fr_fr fr32,fr3 + nfdstoi fr2,fr2 + test_fr_iimmed 0xdeadbf00,fr2 + test_fr_iimmed 0x00000002,fr3 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + ; TODO test cases to set ne flags + + pass diff --git a/sim/testsuite/sim/frv/nfdsubs.cgs b/sim/testsuite/sim/frv/nfdsubs.cgs new file mode 100644 index 0000000..c981aab --- /dev/null +++ b/sim/testsuite/sim/frv/nfdsubs.cgs @@ -0,0 +1,202 @@ +# frv testcase for nfdsubs $FRi,$FRj,$FRk +# mach: fr500 fr550 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + load_float_constants1 + + .global nfdsubs +nfdsubs: + nfdsubs fr0,fr16,fr2 + test_fr_fr fr2,fr0 + test_fr_fr fr3,fr0 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsubs fr4,fr16,fr2 + test_fr_fr fr2,fr4 + test_fr_fr fr3,fr4 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsubs fr8,fr16,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsubs fr12,fr16,fr2 + test_fr_fr fr2,fr12 + test_fr_fr fr3,fr12 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsubs fr16,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsubs fr20,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsubs fr24,fr16,fr2 + test_fr_fr fr2,fr24 + test_fr_fr fr3,fr24 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsubs fr28,fr16,fr2 + test_fr_fr fr2,fr28 + test_fr_fr fr3,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsubs fr32,fr16,fr2 + test_fr_fr fr2,fr32 + test_fr_fr fr3,fr32 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsubs fr36,fr16,fr2 + test_fr_fr fr2,fr36 + test_fr_fr fr3,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsubs fr40,fr16,fr2 + test_fr_fr fr2,fr40 + test_fr_fr fr3,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsubs fr44,fr16,fr2 + test_fr_fr fr2,fr44 + test_fr_fr fr3,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsubs fr48,fr16,fr2 + test_fr_fr fr2,fr48 + test_fr_fr fr3,fr48 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsubs fr52,fr16,fr2 + test_fr_fr fr2,fr52 + test_fr_fr fr3,fr52 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdsubs fr0,fr20,fr2 + test_fr_fr fr2,fr0 + test_fr_fr fr3,fr0 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsubs fr4,fr20,fr2 + test_fr_fr fr2,fr4 + test_fr_fr fr3,fr4 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsubs fr8,fr20,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsubs fr12,fr20,fr2 + test_fr_fr fr2,fr12 + test_fr_fr fr3,fr12 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsubs fr16,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsubs fr20,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsubs fr24,fr20,fr2 + test_fr_fr fr2,fr24 + test_fr_fr fr3,fr24 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsubs fr28,fr20,fr2 + test_fr_fr fr2,fr28 + test_fr_fr fr3,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsubs fr32,fr20,fr2 + test_fr_fr fr2,fr32 + test_fr_fr fr3,fr32 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsubs fr36,fr20,fr2 + test_fr_fr fr2,fr36 + test_fr_fr fr3,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsubs fr40,fr20,fr2 + test_fr_fr fr2,fr40 + test_fr_fr fr3,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsubs fr44,fr20,fr2 + test_fr_fr fr2,fr44 + test_fr_fr fr3,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsubs fr48,fr20,fr2 + test_fr_fr fr2,fr48 + test_fr_fr fr3,fr48 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfdsubs fr52,fr20,fr2 + test_fr_fr fr2,fr52 + test_fr_fr fr3,fr52 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdsubs fr32,fr36,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdsubs fr44,fr40,fr2 + test_fr_fr fr2,fr36 + test_fr_fr fr3,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + ; try to cause exceptions + nfdsubs fr4,fr28,fr2 +; test_fr_fr fr2,fr44 +; test_fr_fr fr3,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdsubs fr0,fr28,fr2 +; test_fr_fr fr2,fr44 +; test_fr_fr fr3,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdsubs fr56,fr28,fr2 +; test_fr_fr fr2,fr44 +; test_fr_fr fr3,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfdsubs fr60,fr28,fr2 +; test_fr_fr fr2,fr44 +; test_fr_fr fr3,fr44 + test_spr_immed 0xc,fner1 + test_spr_immed 0,fner0 + + pass + + diff --git a/sim/testsuite/sim/frv/nfitos.cgs b/sim/testsuite/sim/frv/nfitos.cgs new file mode 100644 index 0000000..539f7b2 --- /dev/null +++ b/sim/testsuite/sim/frv/nfitos.cgs @@ -0,0 +1,44 @@ +# frv testcase for nfitos $FRj,$FRk +# mach: fr500 fr550 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global nfitos +nfitos: + set_fr_iimmed 0,0,fr1 + nfitos fr1,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fr_iimmed 0x0000,0x0002,fr1 + nfitos fr1,fr1 + test_fr_fr fr1,fr32 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fr_iimmed 0xdead,0xbeef,fr1 + nfitos fr1,fr1 + test_fr_iimmed 0xce054904,fr1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + ; These were an attempt to cause overflow + set_fr_iimmed 0x7fff,0xffff,fr1 + nfitos fr1,fr1 + test_fr_iimmed 0x4f000000,fr1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fr_iimmed 0x8000,0x0000,fr1 + nfitos fr1,fr1 + test_fr_iimmed 0xcf000000,fr1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + pass diff --git a/sim/testsuite/sim/frv/nfmadds.cgs b/sim/testsuite/sim/frv/nfmadds.cgs new file mode 100644 index 0000000..2113cd2 --- /dev/null +++ b/sim/testsuite/sim/frv/nfmadds.cgs @@ -0,0 +1,227 @@ +# frv testcase for nfmadds $GRi,$GRj,$GRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global nfmadds +nfmadds: + set_fr_fr fr16,fr1 + nfmadds fr16,fr4,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmadds fr16,fr8,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmadds fr16,fr12,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmadds fr16,fr16,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmadds fr16,fr20,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmadds fr16,fr24,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmadds fr16,fr28,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmadds fr16,fr32,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmadds fr16,fr36,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmadds fr16,fr40,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmadds fr16,fr44,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmadds fr16,fr48,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfmadds fr20,fr4,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmadds fr20,fr8,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmadds fr20,fr12,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmadds fr20,fr16,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmadds fr20,fr20,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmadds fr20,fr24,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmadds fr20,fr28,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmadds fr20,fr32,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmadds fr20,fr36,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmadds fr20,fr40,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmadds fr20,fr44,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmadds fr20,fr48,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fr_fr fr16,fr1 + nfmadds fr28,fr0,fr1 + test_fr_fr fr1,fr0 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr1 + nfmadds fr28,fr4,fr1 + test_fr_fr fr1,fr4 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr1 + nfmadds fr28,fr8,fr1 + test_fr_fr fr1,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr1 + nfmadds fr28,fr12,fr1 + test_fr_fr fr1,fr12 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr1 + nfmadds fr28,fr16,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr1 + nfmadds fr28,fr20,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr1 + nfmadds fr28,fr24,fr1 + test_fr_fr fr1,fr24 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr1 + nfmadds fr28,fr28,fr1 + test_fr_fr fr1,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr1 + nfmadds fr28,fr32,fr1 + test_fr_fr fr1,fr32 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr1 + nfmadds fr28,fr36,fr1 + test_fr_fr fr1,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr1 + nfmadds fr28,fr40,fr1 + test_fr_fr fr1,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr1 + nfmadds fr28,fr44,fr1 + test_fr_fr fr1,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr1 + nfmadds fr28,fr48,fr1 + test_fr_fr fr1,fr48 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr1 + nfmadds fr28,fr52,fr1 + test_fr_fr fr1,fr52 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fr_fr fr36,fr1 + nfmadds fr28,fr8,fr1 + test_fr_fr fr1,fr32 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmadds fr8,fr28,fr1 + test_fr_fr fr1,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fr_fr fr36,fr1 + nfmadds fr32,fr36,fr1 + test_fr_fr fr1,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + ; TODO test cases to set ne flags + + pass diff --git a/sim/testsuite/sim/frv/nfmas.cgs b/sim/testsuite/sim/frv/nfmas.cgs new file mode 100644 index 0000000..b688dbd --- /dev/null +++ b/sim/testsuite/sim/frv/nfmas.cgs @@ -0,0 +1,297 @@ +# frv testcase for nfmas $FRi,$FRj,$FRk +# mach: fr500 fr550 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + load_float_constants1 + + .global nfmas +nfmas: + nfmas fr16,fr4,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr4 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr16,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr16,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr12 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr16,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr16,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr16,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr24 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr16,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr16,fr32,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr32 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr16,fr36,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr16,fr40,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr16,fr44,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr16,fr48,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr48 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfmas fr20,fr4,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr4 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr20,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr20,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr12 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr20,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr20,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr20,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr24 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr20,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr20,fr32,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr32 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr20,fr36,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr20,fr40,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr20,fr44,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr20,fr48,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr48 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfmas fr28,fr0,fr2 + test_fr_fr fr2,fr0 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr28,fr4,fr2 + test_fr_fr fr2,fr4 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr28,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr28,fr12,fr2 + test_fr_fr fr2,fr12 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr28,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr28,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr28,fr24,fr2 + test_fr_fr fr2,fr24 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr28,fr28,fr2 + test_fr_fr fr2,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr28,fr32,fr2 + test_fr_fr fr2,fr32 + test_fr_fr fr3,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr28,fr36,fr2 + test_fr_fr fr2,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr28,fr40,fr2 + test_fr_fr fr2,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr28,fr44,fr2 + test_fr_fr fr2,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr28,fr48,fr2 + test_fr_fr fr2,fr48 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr28,fr52,fr2 + test_fr_fr fr2,fr52 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfmas fr28,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmas fr8,fr28,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfmas fr32,fr36,fr2 + test_fr_fr fr2,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + ; try to cause exceptions + set_spr_immed 0,fner0 + set_spr_immed 0,fner1 + nfmas fr48,fr28,fr1 +; test_fr_fr fr1,fr44 +; test_fr_fr fr2,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfmas fr52,fr28,fr1 +; test_fr_fr fr1,fr44 +; test_fr_fr fr2,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfmas fr56,fr28,fr1 +; test_fr_fr fr1,fr44 +; test_fr_fr fr2,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfmas fr60,fr28,fr1 +; test_fr_fr fr1,fr44 +; test_fr_fr fr2,fr44 + test_spr_immed 6,fner1 + test_spr_immed 0,fner0 + + set_spr_immed 0,fner0 + set_spr_immed 0,fner1 + nfmas fr48,fr32,fr1 +; test_fr_fr fr1,fr44 +; test_fr_fr fr2,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfmas fr52,fr28,fr1 +; test_fr_fr fr1,fr44 +; test_fr_fr fr2,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfmas fr56,fr28,fr1 +; test_fr_fr fr1,fr44 +; test_fr_fr fr2,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfmas fr60,fr28,fr1 +; test_fr_fr fr1,fr44 +; test_fr_fr fr2,fr44 + test_spr_immed 6,fner1 + test_spr_immed 0,fner0 + + pass + diff --git a/sim/testsuite/sim/frv/nfmss.cgs b/sim/testsuite/sim/frv/nfmss.cgs new file mode 100644 index 0000000..bc7c8ef --- /dev/null +++ b/sim/testsuite/sim/frv/nfmss.cgs @@ -0,0 +1,279 @@ +# frv testcase for nfmss $FRi,$FRj,$FRk +# mach: fr500 fr550 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + load_float_constants1 + + .global nfmss +nfmss: + nfmss fr16,fr4,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr16,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr16,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr16,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr16,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr16,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr16,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr16,fr32,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr16,fr36,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr16,fr40,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr16,fr44,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr16,fr48,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfmss fr20,fr4,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr20,fr8,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr20,fr12,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr20,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr20,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr16 + test_fr_fr fr3,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr20,fr24,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr20,fr28,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr20,fr32,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr20,fr36,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr20,fr40,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr20,fr44,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr20,fr48,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfmss fr28,fr0,fr2 + test_fr_fr fr2,fr0 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr28,fr4,fr2 + test_fr_fr fr2,fr4 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr28,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr32 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr28,fr12,fr2 + test_fr_fr fr2,fr12 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr28,fr16,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr28,fr20,fr2 + test_fr_fr fr2,fr16 + test_fr_fr fr2,fr20 + test_fr_fr fr3,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr28,fr24,fr2 + test_fr_fr fr2,fr24 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr28,fr28,fr2 + test_fr_fr fr2,fr28 + test_fr_fr fr3,fr20 + test_fr_fr fr3,fr16 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr28,fr32,fr2 + test_fr_fr fr2,fr32 + test_fr_fr fr3,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr28,fr36,fr2 + test_fr_fr fr2,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr28,fr40,fr2 + test_fr_fr fr2,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr28,fr44,fr2 + test_fr_fr fr2,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr28,fr48,fr2 + test_fr_fr fr2,fr48 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr28,fr52,fr2 + test_fr_fr fr2,fr52 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfmss fr28,fr8,fr2 + test_fr_fr fr2,fr8 + test_fr_fr fr3,fr32 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmss fr8,fr28,fr2 + test_fr_fr fr2,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfmss fr32,fr36,fr2 + test_fr_fr fr2,fr40 + test_fr_fr fr3,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + ; try to cause exceptions + nfmss fr4,fr28,fr1 +; test_fr_fr fr1,fr44 +; test_fr_fr fr2,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfmss fr0,fr28,fr1 +; test_fr_fr fr1,fr44 +; test_fr_fr fr2,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfmss fr56,fr28,fr1 +; test_fr_fr fr1,fr44 +; test_fr_fr fr2,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfmss fr60,fr28,fr1 +; test_fr_fr fr1,fr44 +; test_fr_fr fr2,fr44 + test_spr_immed 0x6,fner1 + test_spr_immed 0,fner0 + + set_spr_immed 0,fner0 + set_spr_immed 0,fner1 + nfmss fr48,fr32,fr1 +; test_fr_fr fr1,fr44 +; test_fr_fr fr2,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfmss fr52,fr28,fr1 +; test_fr_fr fr1,fr44 +; test_fr_fr fr2,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfmss fr56,fr28,fr1 +; test_fr_fr fr1,fr44 +; test_fr_fr fr2,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfmss fr60,fr28,fr1 +; test_fr_fr fr1,fr44 +; test_fr_fr fr2,fr44 + test_spr_immed 0x6,fner1 + test_spr_immed 0,fner0 + + pass diff --git a/sim/testsuite/sim/frv/nfmsubs.cgs b/sim/testsuite/sim/frv/nfmsubs.cgs new file mode 100644 index 0000000..1ae87e3 --- /dev/null +++ b/sim/testsuite/sim/frv/nfmsubs.cgs @@ -0,0 +1,227 @@ +# frv testcase for nfmsubs $GRi,$GRj,$GRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global nfmsubs +nfmsubs: + set_fr_fr fr16,fr1 + nfmsubs fr16,fr4,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmsubs fr16,fr8,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmsubs fr16,fr12,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmsubs fr16,fr16,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmsubs fr16,fr20,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmsubs fr16,fr24,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmsubs fr16,fr28,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmsubs fr16,fr32,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmsubs fr16,fr36,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmsubs fr16,fr40,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmsubs fr16,fr44,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmsubs fr16,fr48,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfmsubs fr20,fr4,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmsubs fr20,fr8,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmsubs fr20,fr12,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmsubs fr20,fr16,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmsubs fr20,fr20,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmsubs fr20,fr24,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmsubs fr20,fr28,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmsubs fr20,fr32,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmsubs fr20,fr36,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmsubs fr20,fr40,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmsubs fr20,fr44,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmsubs fr20,fr48,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fr_fr fr16,fr1 + nfmsubs fr28,fr0,fr1 + test_fr_fr fr1,fr0 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr1 + nfmsubs fr28,fr4,fr1 + test_fr_fr fr1,fr4 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr1 + nfmsubs fr28,fr8,fr1 + test_fr_fr fr1,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr1 + nfmsubs fr28,fr12,fr1 + test_fr_fr fr1,fr12 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr1 + nfmsubs fr28,fr16,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr1 + nfmsubs fr28,fr20,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr1 + nfmsubs fr28,fr24,fr1 + test_fr_fr fr1,fr24 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr1 + nfmsubs fr28,fr28,fr1 + test_fr_fr fr1,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr1 + nfmsubs fr28,fr32,fr1 + test_fr_fr fr1,fr32 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr1 + nfmsubs fr28,fr36,fr1 + test_fr_fr fr1,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr1 + nfmsubs fr28,fr40,fr1 + test_fr_fr fr1,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr1 + nfmsubs fr28,fr44,fr1 + test_fr_fr fr1,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr1 + nfmsubs fr28,fr48,fr1 + test_fr_fr fr1,fr48 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr16,fr1 + nfmsubs fr28,fr52,fr1 + test_fr_fr fr1,fr52 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fr_fr fr32,fr1 + nfmsubs fr8,fr8,fr1 + test_fr_fr fr1,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + set_fr_fr fr36,fr1 + nfmsubs fr36,fr36,fr1 + test_fr_fr fr1,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfmsubs fr32,fr36,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + ; TODO test cases to set ne flags + pass diff --git a/sim/testsuite/sim/frv/nfmuls.cgs b/sim/testsuite/sim/frv/nfmuls.cgs new file mode 100644 index 0000000..e4b0d2e --- /dev/null +++ b/sim/testsuite/sim/frv/nfmuls.cgs @@ -0,0 +1,228 @@ +# frv testcase for nfmuls $FRi,$FRj,$FRk +# mach: fr500 fr550 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global nfmuls +nfmuls: + nfmuls fr16,fr4,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr16,fr8,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr16,fr12,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr16,fr16,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr16,fr20,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr16,fr24,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr16,fr28,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr16,fr32,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr16,fr36,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr16,fr40,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr16,fr44,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr16,fr48,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfmuls fr20,fr4,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr20,fr8,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr20,fr12,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr20,fr16,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr20,fr20,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr20,fr24,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr20,fr28,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr20,fr32,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr20,fr36,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr20,fr40,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr20,fr44,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr20,fr48,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfmuls fr28,fr0,fr1 + test_fr_fr fr1,fr0 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr28,fr4,fr1 + test_fr_fr fr1,fr4 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr28,fr8,fr1 + test_fr_fr fr1,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr28,fr12,fr1 + test_fr_fr fr1,fr12 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr28,fr16,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr28,fr20,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr28,fr24,fr1 + test_fr_fr fr1,fr24 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr28,fr28,fr1 + test_fr_fr fr1,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr28,fr32,fr1 + test_fr_fr fr1,fr32 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr28,fr36,fr1 + test_fr_fr fr1,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr28,fr40,fr1 + test_fr_fr fr1,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr28,fr44,fr1 + test_fr_fr fr1,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr28,fr48,fr1 + test_fr_fr fr1,fr48 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr28,fr52,fr1 + test_fr_fr fr1,fr52 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfmuls fr28,fr8,fr1 + test_fr_fr fr1,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfmuls fr8,fr28,fr1 + test_fr_fr fr1,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfmuls fr32,fr36,fr1 + test_fr_fr fr1,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + ; try to cause exceptions + nfmuls fr48,fr32,fr1 +; test_fr_fr fr1,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfmuls fr52,fr28,fr1 +; test_fr_fr fr1,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfmuls fr56,fr28,fr1 +; test_fr_fr fr1,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfmuls fr60,fr28,fr1 +; test_fr_fr fr1,fr44 + test_spr_immed 2,fner1 + test_spr_immed 0,fner0 + + pass diff --git a/sim/testsuite/sim/frv/nfsqrts.cgs b/sim/testsuite/sim/frv/nfsqrts.cgs new file mode 100644 index 0000000..8ada77a --- /dev/null +++ b/sim/testsuite/sim/frv/nfsqrts.cgs @@ -0,0 +1,35 @@ +# frv testcase for nfsqrts $FRj,$FRk +# mach: fr500 fr550 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global nfsqrts +nfsqrts: + nfsqrts fr44,fr1 ; 9.0 + test_fr_fr fr1,fr36 ; 3.0 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fr_iimmed 0x4049,0x0fdb,fr10 ; 3.141592654 + nfsqrts fr10,fr10 + test_fr_iimmed 0x3fe2dfc5,fr10 ; 1.7724539 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + ; fp_exceptions + nfsqrts fr8,fr1 ; -1 -- invalid + test_fr_iimmed 0x7fc00000,fr1 ; nan1 + test_spr_immed 2,fner1 + test_spr_immed 0,fner0 + test_spr_bits 0x80000000,31,0x0,fqst0 ; fq0.miv is clear + test_spr_bits 0x18000,15,0x0,fqst0 ; fq0.sie is clear + test_spr_bits 0x380,7,0x0,fqst0 ; fq0.ftt is clear + test_spr_bits 0x7e,1,0x0,fqst0 ; fq0.cexc is clear + test_spr_bits 0x1,0,0x0,fqst0 ; fq0.valid is clear + test_spr_immed 0,fqop0 ; fq0.opc + + pass diff --git a/sim/testsuite/sim/frv/nfstoi.cgs b/sim/testsuite/sim/frv/nfstoi.cgs new file mode 100644 index 0000000..2968128 --- /dev/null +++ b/sim/testsuite/sim/frv/nfstoi.cgs @@ -0,0 +1,49 @@ +# frv testcase for nfstoi $FRj,$FRk +# mach: fr500 fr550 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global nfstoi +nfstoi: + nfstoi fr16,fr1 + test_fr_iimmed 0,fr1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfstoi fr20,fr1 + test_fr_iimmed 0,fr1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfstoi fr32,fr1 + test_fr_iimmed 0x00000002,fr1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + set_fr_iimmed 0xce05,0x4904,fr1 + nfstoi fr1,fr1 + test_fr_iimmed 0xdeadbf00,fr1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + ; These were an attempt to cause overflow and nan exceptions + nfstoi fr48,fr1 + test_fr_iimmed 0x7fffffff,fr1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfstoi fr52,fr1 + test_fr_iimmed 0x7fffffff,fr1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfstoi fr56,fr1 + test_fr_iimmed 0x80000000,fr1 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + pass diff --git a/sim/testsuite/sim/frv/nfsubs.cgs b/sim/testsuite/sim/frv/nfsubs.cgs new file mode 100644 index 0000000..3da08b9 --- /dev/null +++ b/sim/testsuite/sim/frv/nfsubs.cgs @@ -0,0 +1,163 @@ +# frv testcase for nfsubs $FRi,$FRj,$FRk +# mach: fr500 fr550 frv + + .include "testutils.inc" + + float_constants + start + load_float_constants + + .global nfsubs +nfsubs: + nfsubs fr0,fr16,fr1 + test_fr_fr fr1,fr0 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfsubs fr4,fr16,fr1 + test_fr_fr fr1,fr4 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfsubs fr8,fr16,fr1 + test_fr_fr fr1,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfsubs fr12,fr16,fr1 + test_fr_fr fr1,fr12 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfsubs fr16,fr16,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfsubs fr20,fr16,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfsubs fr24,fr16,fr1 + test_fr_fr fr1,fr24 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfsubs fr28,fr16,fr1 + test_fr_fr fr1,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfsubs fr32,fr16,fr1 + test_fr_fr fr1,fr32 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfsubs fr36,fr16,fr1 + test_fr_fr fr1,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfsubs fr40,fr16,fr1 + test_fr_fr fr1,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfsubs fr44,fr16,fr1 + test_fr_fr fr1,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfsubs fr48,fr16,fr1 + test_fr_fr fr1,fr48 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfsubs fr52,fr16,fr1 + test_fr_fr fr1,fr52 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfsubs fr0,fr20,fr1 + test_fr_fr fr1,fr0 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfsubs fr4,fr20,fr1 + test_fr_fr fr1,fr4 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfsubs fr8,fr20,fr1 + test_fr_fr fr1,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfsubs fr12,fr20,fr1 + test_fr_fr fr1,fr12 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfsubs fr16,fr20,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfsubs fr20,fr20,fr1 + test_fr_fr fr1,fr16 + test_fr_fr fr1,fr20 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfsubs fr24,fr20,fr1 + test_fr_fr fr1,fr24 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfsubs fr28,fr20,fr1 + test_fr_fr fr1,fr28 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfsubs fr32,fr20,fr1 + test_fr_fr fr1,fr32 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfsubs fr36,fr20,fr1 + test_fr_fr fr1,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfsubs fr40,fr20,fr1 + test_fr_fr fr1,fr40 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfsubs fr44,fr20,fr1 + test_fr_fr fr1,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfsubs fr48,fr20,fr1 + test_fr_fr fr1,fr48 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + nfsubs fr52,fr20,fr1 + test_fr_fr fr1,fr52 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfsubs fr32,fr36,fr1 + test_fr_fr fr1,fr8 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfsubs fr44,fr40,fr1 + test_fr_fr fr1,fr36 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + ; try to cause exceptions + nfsubs fr4,fr28,fr1 +; test_fr_fr fr1,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfsubs fr0,fr28,fr1 +; test_fr_fr fr1,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfsubs fr56,fr28,fr1 +; test_fr_fr fr1,fr44 + test_spr_immed 0,fner1 + test_spr_immed 0,fner0 + + nfsubs fr60,fr28,fr1 +; test_fr_fr fr1,fr44 + test_spr_immed 2,fner1 + test_spr_immed 0,fner0 + + pass + + diff --git a/sim/testsuite/sim/frv/nld.cgs b/sim/testsuite/sim/frv/nld.cgs new file mode 100644 index 0000000..297468b --- /dev/null +++ b/sim/testsuite/sim/frv/nld.cgs @@ -0,0 +1,42 @@ +# frv testcase for nld @($GRi,$GRj),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global nld +nld: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr20 + set_gr_immed 0,gr7 + nld @(sp,gr7),gr8 + test_gr_limmed 0xdead,0xbeef,gr8 + test_spr_limmed 0x8880,0x0001,nesr0 + test_spr_gr neear0,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + nld @(sp,gr7),gr8 + test_gr_limmed 0xdead,0xbeef,gr8 + test_spr_limmed 0x8880,0x0401,nesr1 + test_spr_gr neear1,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed 8,sp + set_gr_immed -4,gr7 + nld @(sp,gr7),gr8 + test_gr_limmed 0xdead,0xbeef,gr8 + test_spr_limmed 0x8880,0x0801,nesr2 + test_spr_gr neear2,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + pass diff --git a/sim/testsuite/sim/frv/nldbf.cgs b/sim/testsuite/sim/frv/nldbf.cgs new file mode 100644 index 0000000..1a5c25b --- /dev/null +++ b/sim/testsuite/sim/frv/nldbf.cgs @@ -0,0 +1,42 @@ +# frv testcase for nldbf @($GRi,$GRj),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global nldbf +nldbf: + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_gr sp,gr20 + set_gr_immed 0,gr7 + nldbf @(sp,gr7),fr8 + test_fr_limmed 0x0000,0x00de,fr8 + test_spr_limmed 0xc800,0x0001,nesr0 + test_spr_gr neear0,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + inc_gr_immed 1,gr20 + set_gr_immed 1,gr7 + nldbf @(sp,gr7),fr8 + test_fr_limmed 0x0000,0x00ad,fr8 + test_spr_limmed 0xc800,0x0401,nesr1 + test_spr_gr neear1,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + inc_gr_immed 2,gr20 + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + nldbf @(sp,gr7),fr8 + test_fr_limmed 0x0000,0x0000,fr8 + test_spr_limmed 0xc800,0x0801,nesr2 + test_spr_gr neear2,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + pass diff --git a/sim/testsuite/sim/frv/nldbfi.cgs b/sim/testsuite/sim/frv/nldbfi.cgs new file mode 100644 index 0000000..aa90bc9 --- /dev/null +++ b/sim/testsuite/sim/frv/nldbfi.cgs @@ -0,0 +1,39 @@ +# frv testcase for nldbfi @($GRi,$d12),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global nldbfi +nldbfi: + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_gr sp,gr20 + nldbfi @(sp,0),fr8 + test_fr_limmed 0x0000,0x00de,fr8 + test_spr_limmed 0xc800,0x0001,nesr0 + test_spr_gr neear0,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + inc_gr_immed 1,gr20 + nldbfi @(sp,1),fr8 + test_fr_limmed 0x0000,0x00ad,fr8 + test_spr_limmed 0xc800,0x0401,nesr1 + test_spr_gr neear1,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + inc_gr_immed 2,gr20 + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + nldbfi @(sp,-1),fr8 + test_fr_limmed 0x0000,0x0000,fr8 + test_spr_limmed 0xc800,0x0801,nesr2 + test_spr_gr neear2,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + pass diff --git a/sim/testsuite/sim/frv/nldbfu.cgs b/sim/testsuite/sim/frv/nldbfu.cgs new file mode 100644 index 0000000..174042b --- /dev/null +++ b/sim/testsuite/sim/frv/nldbfu.cgs @@ -0,0 +1,46 @@ +# frv testcase for nldbfu @($GRi,$GRj),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global nldbfu +nldbfu: + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + nldbfu @(sp,gr7),fr8 + test_fr_limmed 0x0000,0x00de,fr8 + test_gr_gr sp,gr20 + test_spr_limmed 0xc800,0x0001,nesr0 + test_spr_gr neear0,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + inc_gr_immed 1,gr20 + set_gr_immed 1,gr7 + nldbfu @(sp,gr7),fr8 + test_fr_limmed 0x0000,0x00ad,fr8 + test_gr_gr sp,gr20 + test_spr_limmed 0xc800,0x0401,nesr1 + test_spr_gr neear1,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + inc_gr_immed 2,gr20 + inc_gr_immed -1,sp + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + nldbfu @(sp,gr7),fr8 + test_fr_limmed 0x0000,0x0000,fr8 + test_gr_gr sp,gr20 + test_spr_limmed 0xc800,0x0801,nesr2 + test_spr_gr neear2,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + pass diff --git a/sim/testsuite/sim/frv/nldd.cgs b/sim/testsuite/sim/frv/nldd.cgs new file mode 100644 index 0000000..1f45761 --- /dev/null +++ b/sim/testsuite/sim/frv/nldd.cgs @@ -0,0 +1,50 @@ +# frv testcase for nldd @($GRi,$GRj),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global nldd +nldd: + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + + set_gr_gr sp,gr20 + set_gr_immed 0,gr7 + nldd @(sp,gr7),gr8 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + test_spr_limmed 0x88a0,0x0001,nesr0 + test_spr_gr neear0,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + nldd @(sp,gr7),gr8 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + test_spr_limmed 0x88a0,0x0401,nesr1 + test_spr_gr neear1,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + nldd @(sp,gr7),gr8 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + test_spr_limmed 0x88a0,0x0801,nesr2 + test_spr_gr neear2,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + pass diff --git a/sim/testsuite/sim/frv/nlddf.cgs b/sim/testsuite/sim/frv/nlddf.cgs new file mode 100644 index 0000000..d30b6dd --- /dev/null +++ b/sim/testsuite/sim/frv/nlddf.cgs @@ -0,0 +1,50 @@ +# frv testcase for nlddf @($GRi,$GRj),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global nlddf +nlddf: + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + + set_gr_gr sp,gr20 + set_gr_immed 0,gr7 + nlddf @(sp,gr7),fr8 + test_fr_limmed 0xbeef,0xdead,fr8 + test_fr_limmed 0xdead,0xbeef,fr9 + test_spr_limmed 0xc8a0,0x0001,nesr0 + test_spr_gr neear0,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + nlddf @(sp,gr7),fr8 + test_fr_limmed 0xbeef,0xdead,fr8 + test_fr_limmed 0xdead,0xbeef,fr9 + test_spr_limmed 0xc8a0,0x0401,nesr1 + test_spr_gr neear1,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed 16,sp + set_gr_immed -8,gr7 + nlddf @(sp,gr7),fr8 + test_fr_limmed 0xbeef,0xdead,fr8 + test_fr_limmed 0xdead,0xbeef,fr9 + test_spr_limmed 0xc8a0,0x0801,nesr2 + test_spr_gr neear2,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + pass diff --git a/sim/testsuite/sim/frv/nlddfi.cgs b/sim/testsuite/sim/frv/nlddfi.cgs new file mode 100644 index 0000000..b58ad6f --- /dev/null +++ b/sim/testsuite/sim/frv/nlddfi.cgs @@ -0,0 +1,47 @@ +# frv testcase for nlddfi @($GRi,$d12),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global nlddfi +nlddfi: + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + + set_gr_gr sp,gr20 + nlddfi @(sp,0),fr8 + test_fr_limmed 0xbeef,0xdead,fr8 + test_fr_limmed 0xdead,0xbeef,fr9 + test_spr_limmed 0xc8a0,0x0001,nesr0 + test_spr_gr neear0,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed -8,sp + nlddfi @(sp,8),fr8 + test_fr_limmed 0xbeef,0xdead,fr8 + test_fr_limmed 0xdead,0xbeef,fr9 + test_spr_limmed 0xc8a0,0x0401,nesr1 + test_spr_gr neear1,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed 16,sp + nlddfi @(sp,-8),fr8 + test_fr_limmed 0xbeef,0xdead,fr8 + test_fr_limmed 0xdead,0xbeef,fr9 + test_spr_limmed 0xc8a0,0x0801,nesr2 + test_spr_gr neear2,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + pass diff --git a/sim/testsuite/sim/frv/nlddfu.cgs b/sim/testsuite/sim/frv/nlddfu.cgs new file mode 100644 index 0000000..d45c995 --- /dev/null +++ b/sim/testsuite/sim/frv/nlddfu.cgs @@ -0,0 +1,53 @@ +# frv testcase for nlddfu @($GRi,$GRj),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global nlddfu +nlddfu: + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_gr sp,gr20 + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + + set_gr_immed 0,gr7 + nlddfu @(sp,gr7),fr8 + test_fr_limmed 0xbeef,0xdead,fr8 + test_fr_limmed 0xdead,0xbeef,fr9 + test_gr_gr sp,gr20 + test_spr_limmed 0xc8a0,0x0001,nesr0 + test_spr_gr neear0,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + nlddfu @(sp,gr7),fr8 + test_fr_limmed 0xbeef,0xdead,fr8 + test_fr_limmed 0xdead,0xbeef,fr9 + test_gr_gr sp,gr20 + test_spr_limmed 0xc8a0,0x0401,nesr1 + test_spr_gr neear1,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + inc_gr_immed 8,sp + set_gr_immed -8,gr7 + nlddfu @(sp,gr7),fr8 + test_fr_limmed 0xbeef,0xdead,fr8 + test_fr_limmed 0xdead,0xbeef,fr9 + test_gr_gr sp,gr20 + test_spr_limmed 0xc8a0,0x0801,nesr2 + test_spr_gr neear2,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + pass diff --git a/sim/testsuite/sim/frv/nlddi.cgs b/sim/testsuite/sim/frv/nlddi.cgs new file mode 100644 index 0000000..04d2487 --- /dev/null +++ b/sim/testsuite/sim/frv/nlddi.cgs @@ -0,0 +1,47 @@ +# frv testcase for nlddi @($GRi,$d12),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global nlddi +nlddi: + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + + set_gr_gr sp,gr20 + nlddi @(sp,0),gr8 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + test_spr_limmed 0x88a0,0x0001,nesr0 + test_spr_gr neear0,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed -8,sp + nlddi @(sp,8),gr8 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + test_spr_limmed 0x88a0,0x0401,nesr1 + test_spr_gr neear1,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed 16,sp + nlddi @(sp,-8),gr8 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + test_spr_limmed 0x88a0,0x0801,nesr2 + test_spr_gr neear2,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + pass diff --git a/sim/testsuite/sim/frv/nlddu.cgs b/sim/testsuite/sim/frv/nlddu.cgs new file mode 100644 index 0000000..44565c8 --- /dev/null +++ b/sim/testsuite/sim/frv/nlddu.cgs @@ -0,0 +1,66 @@ +# frv testcase for nlddu @($GRi,$GRj),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global nlddu +nlddu: + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_gr sp,gr20 + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + + set_gr_immed 0,gr7 + nlddu @(sp,gr7),gr8 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + test_gr_gr sp,gr20 + test_spr_limmed 0x88a0,0x0001,nesr0 + test_spr_gr neear0,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + nlddu @(sp,gr7),gr8 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + test_gr_gr sp,gr20 + test_spr_limmed 0x88a0,0x0401,nesr1 + test_spr_gr neear1,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed 8,sp + set_gr_immed -8,gr7 + nlddu @(sp,gr7),gr8 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + test_gr_gr sp,gr20 + test_spr_limmed 0x88a0,0x0801,nesr2 + test_spr_gr neear2,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + inc_gr_immed 8,sp + set_gr_immed -8,gr7 + set_gr_gr sp,gr8 + nlddu @(gr8,gr7),gr8 + test_gr_limmed 0xbeef,0xdead,gr8 + test_gr_limmed 0xdead,0xbeef,gr9 + test_spr_limmed 0x88a0,0x0c01,nesr3 + test_spr_gr neear3,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + pass diff --git a/sim/testsuite/sim/frv/nldf.cgs b/sim/testsuite/sim/frv/nldf.cgs new file mode 100644 index 0000000..6aabc67 --- /dev/null +++ b/sim/testsuite/sim/frv/nldf.cgs @@ -0,0 +1,42 @@ +# frv testcase for nldf @($GRi,$GRj),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global nldf +nldf: + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_gr sp,gr20 + set_gr_immed 0,gr7 + nldf @(sp,gr7),fr8 + test_fr_limmed 0xdead,0xbeef,fr8 + test_spr_limmed 0xc880,0x0001,nesr0 + test_spr_gr neear0,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + nldf @(sp,gr7),fr8 + test_fr_limmed 0xdead,0xbeef,fr8 + test_spr_limmed 0xc880,0x0401,nesr1 + test_spr_gr neear1,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed 8,sp + set_gr_immed -4,gr7 + nldf @(sp,gr7),fr8 + test_fr_limmed 0xdead,0xbeef,fr8 + test_spr_limmed 0xc880,0x0801,nesr2 + test_spr_gr neear2,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + pass diff --git a/sim/testsuite/sim/frv/nldfi.cgs b/sim/testsuite/sim/frv/nldfi.cgs new file mode 100644 index 0000000..20f62df --- /dev/null +++ b/sim/testsuite/sim/frv/nldfi.cgs @@ -0,0 +1,39 @@ +# frv testcase for nldfi @($GRi,$d12),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global nldfi +nldfi: + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_gr sp,gr20 + nldfi @(sp,0),fr8 + test_fr_limmed 0xdead,0xbeef,fr8 + test_spr_limmed 0xc880,0x0001,nesr0 + test_spr_gr neear0,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed -4,sp + nldfi @(sp,4),fr8 + test_fr_limmed 0xdead,0xbeef,fr8 + test_spr_limmed 0xc880,0x0401,nesr1 + test_spr_gr neear1,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed 8,sp + nldfi @(sp,-4),fr8 + test_fr_limmed 0xdead,0xbeef,fr8 + test_spr_limmed 0xc880,0x0801,nesr2 + test_spr_gr neear2,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + pass diff --git a/sim/testsuite/sim/frv/nldfu.cgs b/sim/testsuite/sim/frv/nldfu.cgs new file mode 100644 index 0000000..8e95016 --- /dev/null +++ b/sim/testsuite/sim/frv/nldfu.cgs @@ -0,0 +1,45 @@ +# frv testcase for nldfu @($GRi,$GRj),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global nldfu +nldfu: + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + nldfu @(sp,gr7),fr8 + test_fr_limmed 0xdead,0xbeef,fr8 + test_gr_gr sp,gr20 + test_spr_limmed 0xc880,0x0001,nesr0 + test_spr_gr neear0,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + nldfu @(sp,gr7),fr8 + test_fr_limmed 0xdead,0xbeef,fr8 + test_gr_gr sp,gr20 + test_spr_limmed 0xc880,0x0401,nesr1 + test_spr_gr neear1,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + set_fr_iimmed 0xbeef,0xdead,fr8 + inc_gr_immed 4,sp + set_gr_immed -4,gr7 + nldfu @(sp,gr7),fr8 + test_fr_limmed 0xdead,0xbeef,fr8 + test_gr_gr sp,gr20 + test_spr_limmed 0xc880,0x0801,nesr2 + test_spr_gr neear2,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + pass diff --git a/sim/testsuite/sim/frv/nldhf.cgs b/sim/testsuite/sim/frv/nldhf.cgs new file mode 100644 index 0000000..b90d8f9 --- /dev/null +++ b/sim/testsuite/sim/frv/nldhf.cgs @@ -0,0 +1,41 @@ +# frv testcase for nldhf @($GRi,$GRj),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global nldhf +nldhf: + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_gr sp,gr20 + set_gr_immed 0,gr7 + nldhf @(sp,gr7),fr8 + test_fr_limmed 0x0000,0xdead,fr8 + test_spr_limmed 0xc840,0x0001,nesr0 + test_spr_gr neear0,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + inc_gr_immed 2,gr20 + set_gr_immed 2,gr7 + nldhf @(sp,gr7),fr8 + test_fr_limmed 0x0000,0xbeef,fr8 + test_spr_limmed 0xc840,0x0401,nesr1 + test_spr_gr neear1,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + nldhf @(sp,gr7),fr8 + test_fr_limmed 0x0000,0x0000,fr8 + test_spr_limmed 0xc840,0x0801,nesr2 + test_spr_gr neear2,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + pass diff --git a/sim/testsuite/sim/frv/nldhfi.cgs b/sim/testsuite/sim/frv/nldhfi.cgs new file mode 100644 index 0000000..bcd52ed --- /dev/null +++ b/sim/testsuite/sim/frv/nldhfi.cgs @@ -0,0 +1,38 @@ +# frv testcase for nldhfi @($GRi,$d12),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global nldhfi +nldhfi: + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_gr sp,gr20 + nldhfi @(sp,0),fr8 + test_fr_limmed 0x0000,0xdead,fr8 + test_spr_limmed 0xc840,0x0001,nesr0 + test_spr_gr neear0,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + inc_gr_immed 2,gr20 + nldhfi @(sp,2),fr8 + test_fr_limmed 0x0000,0xbeef,fr8 + test_spr_limmed 0xc840,0x0401,nesr1 + test_spr_gr neear1,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + nldhfi @(sp,-2),fr8 + test_fr_limmed 0x0000,0x0000,fr8 + test_spr_limmed 0xc840,0x0801,nesr2 + test_spr_gr neear2,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + pass diff --git a/sim/testsuite/sim/frv/nldhfu.cgs b/sim/testsuite/sim/frv/nldhfu.cgs new file mode 100644 index 0000000..97d1dd9 --- /dev/null +++ b/sim/testsuite/sim/frv/nldhfu.cgs @@ -0,0 +1,45 @@ +# frv testcase for nldhfu @($GRi,$GRj),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global nldhfu +nldhfu: + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xbeef,0xdead,fr8 + + set_gr_immed 0,gr7 + nldhfu @(sp,gr7),fr8 + test_fr_limmed 0x0000,0xdead,fr8 + test_gr_gr sp,gr20 + test_spr_limmed 0xc840,0x0001,nesr0 + test_spr_gr neear0,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + inc_gr_immed 2,gr20 + set_gr_immed 2,gr7 + nldhfu @(sp,gr7),fr8 + test_fr_limmed 0x0000,0xbeef,fr8 + test_gr_gr sp,gr20 + test_spr_limmed 0xc840,0x0401,nesr1 + test_spr_gr neear1,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + inc_gr_immed -2,sp + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + nldhfu @(sp,gr7),fr8 + test_fr_limmed 0x0000,0x0000,fr8 + test_gr_gr sp,gr20 + test_spr_limmed 0xc840,0x0801,nesr2 + test_spr_gr neear2,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + pass diff --git a/sim/testsuite/sim/frv/nldi.cgs b/sim/testsuite/sim/frv/nldi.cgs new file mode 100644 index 0000000..c70f0cb --- /dev/null +++ b/sim/testsuite/sim/frv/nldi.cgs @@ -0,0 +1,39 @@ +# frv testcase for nldi @($GRi,$d12),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global nldi +nldi: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr20 + nldi @(sp,0),gr8 + test_gr_limmed 0xdead,0xbeef,gr8 + test_spr_limmed 0x8880,0x0001,nesr0 + test_spr_gr neear0,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed -4,sp + nldi @(sp,4),gr8 + test_gr_limmed 0xdead,0xbeef,gr8 + test_spr_limmed 0x8880,0x0401,nesr1 + test_spr_gr neear1,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed 8,sp + nldi @(sp,-4),gr8 + test_gr_limmed 0xdead,0xbeef,gr8 + test_spr_limmed 0x8880,0x0801,nesr2 + test_spr_gr neear2,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + pass diff --git a/sim/testsuite/sim/frv/nldq.cgs b/sim/testsuite/sim/frv/nldq.cgs new file mode 100644 index 0000000..0338e19 --- /dev/null +++ b/sim/testsuite/sim/frv/nldq.cgs @@ -0,0 +1,67 @@ +# frv testcase for nldq @($GRi,$GRj),$GRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global nldq +nldq: + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0x1234,0x5678,sp + inc_gr_immed -4,sp + set_mem_limmed 0x9abc,0xdef0,sp + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + + set_gr_gr sp,gr20 + set_gr_immed 0,gr7 + nldq @(sp,gr7),gr8 + test_gr_limmed 0x9abc,0xdef0,gr8 + test_gr_limmed 0x1234,0x5678,gr9 + test_gr_limmed 0xbeef,0xdead,gr10 + test_gr_limmed 0xdead,0xbeef,gr11 + test_spr_limmed 0x88c0,0x0001,nesr0 + test_spr_gr neear0,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed -16,sp + set_gr_immed 16,gr7 + nldq @(sp,gr7),gr8 + test_gr_limmed 0x9abc,0xdef0,gr8 + test_gr_limmed 0x1234,0x5678,gr9 + test_gr_limmed 0xbeef,0xdead,gr10 + test_gr_limmed 0xdead,0xbeef,gr11 + test_spr_limmed 0x88c0,0x0401,nesr1 + test_spr_gr neear1,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed 32,sp + set_gr_immed -16,gr7 + nldq @(sp,gr7),gr8 + test_gr_limmed 0x9abc,0xdef0,gr8 + test_gr_limmed 0x1234,0x5678,gr9 + test_gr_limmed 0xbeef,0xdead,gr10 + test_gr_limmed 0xdead,0xbeef,gr11 + test_spr_limmed 0x88c0,0x0801,nesr2 + test_spr_gr neear2,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + pass diff --git a/sim/testsuite/sim/frv/nldqf.cgs b/sim/testsuite/sim/frv/nldqf.cgs new file mode 100644 index 0000000..8e268ac --- /dev/null +++ b/sim/testsuite/sim/frv/nldqf.cgs @@ -0,0 +1,67 @@ +# frv testcase for nldqf @($GRi,$GRj),$GRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global nldqf +nldqf: + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0x1234,0x5678,sp + inc_gr_immed -4,sp + set_mem_limmed 0x9abc,0xdef0,sp + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x9abc,0xdef0,fr11 + + set_gr_gr sp,gr20 + set_gr_immed 0,gr7 + nldqf @(sp,gr7),fr8 + test_fr_limmed 0x9abc,0xdef0,fr8 + test_fr_limmed 0x1234,0x5678,fr9 + test_fr_limmed 0xbeef,0xdead,fr10 + test_fr_limmed 0xdead,0xbeef,fr11 + test_spr_limmed 0xc8c0,0x0001,nesr0 + test_spr_gr neear0,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x9abc,0xdef0,fr11 + inc_gr_immed -16,sp + set_gr_immed 16,gr7 + nldqf @(sp,gr7),fr8 + test_fr_limmed 0x9abc,0xdef0,fr8 + test_fr_limmed 0x1234,0x5678,fr9 + test_fr_limmed 0xbeef,0xdead,fr10 + test_fr_limmed 0xdead,0xbeef,fr11 + test_spr_limmed 0xc8c0,0x0401,nesr1 + test_spr_gr neear1,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x9abc,0xdef0,fr11 + inc_gr_immed 32,sp + set_gr_immed -16,gr7 + nldqf @(sp,gr7),fr8 + test_fr_limmed 0x9abc,0xdef0,fr8 + test_fr_limmed 0x1234,0x5678,fr9 + test_fr_limmed 0xbeef,0xdead,fr10 + test_fr_limmed 0xdead,0xbeef,fr11 + test_spr_limmed 0xc8c0,0x0801,nesr2 + test_spr_gr neear2,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + pass diff --git a/sim/testsuite/sim/frv/nldqfi.cgs b/sim/testsuite/sim/frv/nldqfi.cgs new file mode 100644 index 0000000..ff05fae --- /dev/null +++ b/sim/testsuite/sim/frv/nldqfi.cgs @@ -0,0 +1,64 @@ +# frv testcase for nldqfi @($GRi,$GRj),$GRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global nldqfi +nldqfi: + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0x1234,0x5678,sp + inc_gr_immed -4,sp + set_mem_limmed 0x9abc,0xdef0,sp + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x9abc,0xdef0,fr11 + + set_gr_gr sp,gr20 + nldqfi @(sp,0),fr8 + test_fr_limmed 0x9abc,0xdef0,fr8 + test_fr_limmed 0x1234,0x5678,fr9 + test_fr_limmed 0xbeef,0xdead,fr10 + test_fr_limmed 0xdead,0xbeef,fr11 + test_spr_limmed 0xc8c0,0x0001,nesr0 + test_spr_gr neear0,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x9abc,0xdef0,fr11 + inc_gr_immed -16,sp + nldqfi @(sp,16),fr8 + test_fr_limmed 0x9abc,0xdef0,fr8 + test_fr_limmed 0x1234,0x5678,fr9 + test_fr_limmed 0xbeef,0xdead,fr10 + test_fr_limmed 0xdead,0xbeef,fr11 + test_spr_limmed 0xc8c0,0x0401,nesr1 + test_spr_gr neear1,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x9abc,0xdef0,fr11 + inc_gr_immed 32,sp + nldqfi @(sp,-16),fr8 + test_fr_limmed 0x9abc,0xdef0,fr8 + test_fr_limmed 0x1234,0x5678,fr9 + test_fr_limmed 0xbeef,0xdead,fr10 + test_fr_limmed 0xdead,0xbeef,fr11 + test_spr_limmed 0xc8c0,0x0801,nesr2 + test_spr_gr neear2,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + pass diff --git a/sim/testsuite/sim/frv/nldqfu.cgs b/sim/testsuite/sim/frv/nldqfu.cgs new file mode 100644 index 0000000..ffe2990 --- /dev/null +++ b/sim/testsuite/sim/frv/nldqfu.cgs @@ -0,0 +1,70 @@ +# frv testcase for nldqfu @($GRi,$GRj),$GRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global nldqfu +nldqfu: + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0x1234,0x5678,sp + inc_gr_immed -4,sp + set_mem_limmed 0x9abc,0xdef0,sp + set_gr_gr sp,gr20 + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x9abc,0xdef0,fr11 + + set_gr_immed 0,gr7 + nldqfu @(sp,gr7),fr8 + test_fr_limmed 0x9abc,0xdef0,fr8 + test_fr_limmed 0x1234,0x5678,fr9 + test_fr_limmed 0xbeef,0xdead,fr10 + test_fr_limmed 0xdead,0xbeef,fr11 + test_gr_gr sp,gr20 + test_spr_limmed 0xc8c0,0x0001,nesr0 + test_spr_gr neear0,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x9abc,0xdef0,fr11 + inc_gr_immed -16,sp + set_gr_immed 16,gr7 + nldqfu @(sp,gr7),fr8 + test_fr_limmed 0x9abc,0xdef0,fr8 + test_fr_limmed 0x1234,0x5678,fr9 + test_fr_limmed 0xbeef,0xdead,fr10 + test_fr_limmed 0xdead,0xbeef,fr11 + test_gr_gr sp,gr20 + test_spr_limmed 0xc8c0,0x0401,nesr1 + test_spr_gr neear1,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + set_fr_iimmed 0xdead,0xbeef,fr8 + set_fr_iimmed 0xbeef,0xdead,fr9 + set_fr_iimmed 0x1234,0x5678,fr10 + set_fr_iimmed 0x9abc,0xdef0,fr11 + inc_gr_immed 16,sp + set_gr_immed -16,gr7 + nldqfu @(sp,gr7),fr8 + test_fr_limmed 0x9abc,0xdef0,fr8 + test_fr_limmed 0x1234,0x5678,fr9 + test_fr_limmed 0xbeef,0xdead,fr10 + test_fr_limmed 0xdead,0xbeef,fr11 + test_gr_gr sp,gr20 + test_spr_limmed 0xc8c0,0x0801,nesr2 + test_spr_gr neear2,gr20 + test_spr_limmed 0x0000,0x0000,fner1 + test_spr_limmed 0x0000,0x0000,fner0 + + pass diff --git a/sim/testsuite/sim/frv/nldqu.cgs b/sim/testsuite/sim/frv/nldqu.cgs new file mode 100644 index 0000000..a7e8b30 --- /dev/null +++ b/sim/testsuite/sim/frv/nldqu.cgs @@ -0,0 +1,87 @@ +# frv testcase for nldqu @($GRi,$GRj),$GRk +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global nldqu +nldqu: + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0x1234,0x5678,sp + inc_gr_immed -4,sp + set_mem_limmed 0x9abc,0xdef0,sp + set_gr_gr sp,gr20 + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + + set_gr_immed 0,gr7 + nldqu @(sp,gr7),gr8 + test_gr_limmed 0x9abc,0xdef0,gr8 + test_gr_limmed 0x1234,0x5678,gr9 + test_gr_limmed 0xbeef,0xdead,gr10 + test_gr_limmed 0xdead,0xbeef,gr11 + test_gr_gr sp,gr20 + test_spr_limmed 0x88c0,0x0001,nesr0 + test_spr_gr neear0,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed -16,sp + set_gr_immed 16,gr7 + nldqu @(sp,gr7),gr8 + test_gr_limmed 0x9abc,0xdef0,gr8 + test_gr_limmed 0x1234,0x5678,gr9 + test_gr_limmed 0xbeef,0xdead,gr10 + test_gr_limmed 0xdead,0xbeef,gr11 + test_gr_gr sp,gr20 + test_spr_limmed 0x88c0,0x0401,nesr1 + test_spr_gr neear1,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed 16,sp + set_gr_immed -16,gr7 + nldqu @(sp,gr7),gr8 + test_gr_limmed 0x9abc,0xdef0,gr8 + test_gr_limmed 0x1234,0x5678,gr9 + test_gr_limmed 0xbeef,0xdead,gr10 + test_gr_limmed 0xdead,0xbeef,gr11 + test_gr_gr sp,gr20 + test_spr_limmed 0x88c0,0x0801,nesr2 + test_spr_gr neear2,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + set_gr_limmed 0xdead,0xbeef,gr8 + set_gr_limmed 0xbeef,0xdead,gr9 + set_gr_limmed 0x1234,0x5678,gr10 + set_gr_limmed 0x9abc,0xdef0,gr11 + inc_gr_immed 16,sp + set_gr_immed -16,gr7 + set_gr_gr sp,gr8 + nldqu @(gr8,gr7),gr8 + test_gr_limmed 0x9abc,0xdef0,gr8 + test_gr_limmed 0x1234,0x5678,gr9 + test_gr_limmed 0xbeef,0xdead,gr10 + test_gr_limmed 0xdead,0xbeef,gr11 + test_spr_limmed 0x88c0,0x0c01,nesr3 + test_spr_gr neear3,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + pass diff --git a/sim/testsuite/sim/frv/nldsb.cgs b/sim/testsuite/sim/frv/nldsb.cgs new file mode 100644 index 0000000..1db547c --- /dev/null +++ b/sim/testsuite/sim/frv/nldsb.cgs @@ -0,0 +1,42 @@ +# frv testcase for nldsb @($GRi,$GRj),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global nldsb +nldsb: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr20 + set_gr_immed 0,gr7 + nldsb @(sp,gr7),gr8 + test_gr_limmed 0xffff,0xffde,gr8 + test_spr_limmed 0x8820,0x0001,nesr0 + test_spr_gr neear0,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + inc_gr_immed 1,gr20 + set_gr_immed 1,gr7 + nldsb @(sp,gr7),gr8 + test_gr_limmed 0xffff,0xffad,gr8 + test_spr_limmed 0x8820,0x0401,nesr1 + test_spr_gr neear1,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + inc_gr_immed 2,gr20 + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + nldsb @(sp,gr7),gr8 + test_gr_immed 0,gr8 + test_spr_limmed 0x8820,0x0801,nesr2 + test_spr_gr neear2,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + pass diff --git a/sim/testsuite/sim/frv/nldsbi.cgs b/sim/testsuite/sim/frv/nldsbi.cgs new file mode 100644 index 0000000..4b9dcba --- /dev/null +++ b/sim/testsuite/sim/frv/nldsbi.cgs @@ -0,0 +1,39 @@ +# frv testcase for nldsbi @($GRi,$d12),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global nldsbi +nldsbi: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr20 + nldsbi @(sp,0),gr8 + test_gr_limmed 0xffff,0xffde,gr8 + test_spr_limmed 0x8820,0x0001,nesr0 + test_spr_gr neear0,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + inc_gr_immed 1,gr20 + nldsbi @(sp,1),gr8 + test_gr_limmed 0xffff,0xffad,gr8 + test_spr_limmed 0x8820,0x0401,nesr1 + test_spr_gr neear1,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + inc_gr_immed 2,gr20 + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + nldsbi @(sp,-1),gr8 + test_gr_immed 0,gr8 + test_spr_limmed 0x8820,0x0801,nesr2 + test_spr_gr neear2,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + pass diff --git a/sim/testsuite/sim/frv/nldsbu.cgs b/sim/testsuite/sim/frv/nldsbu.cgs new file mode 100644 index 0000000..e60ffc0 --- /dev/null +++ b/sim/testsuite/sim/frv/nldsbu.cgs @@ -0,0 +1,56 @@ +# frv testcase for nldsbu @($GRi,$GRj),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global nldsbu +nldsbu: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + nldsbu @(sp,gr7),gr8 + test_gr_limmed 0xffff,0xffde,gr8 + test_gr_gr sp,gr9 + test_spr_limmed 0x8820,0x0001,nesr0 + test_spr_gr neear0,gr9 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + inc_gr_immed 1,gr9 + set_gr_immed 1,gr7 + nldsbu @(sp,gr7),gr8 + test_gr_limmed 0xffff,0xffad,gr8 + test_gr_gr sp,gr9 + test_spr_limmed 0x8820,0x0401,nesr1 + test_spr_gr neear1,gr9 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + inc_gr_immed 2,gr9 + inc_gr_immed -1,sp + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + nldsbu @(sp,gr7),gr8 + test_gr_immed 0,gr8 + test_gr_gr sp,gr9 + test_spr_limmed 0x8820,0x0801,nesr2 + test_spr_gr neear2,gr9 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + inc_gr_immed -3,sp + set_mem_limmed 0x0000,0x00da,sp + set_gr_immed 3,gr7 + nldsbu @(sp,gr7),sp + test_gr_limmed 0xffff,0xffda,sp + test_spr_limmed 0x8120,0x0c01,nesr3 + test_spr_gr neear3,gr9 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + pass diff --git a/sim/testsuite/sim/frv/nldsh.cgs b/sim/testsuite/sim/frv/nldsh.cgs new file mode 100644 index 0000000..afc00c4 --- /dev/null +++ b/sim/testsuite/sim/frv/nldsh.cgs @@ -0,0 +1,41 @@ +# frv testcase for nldsh @($GRi,$GRj),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global nldsh +nldsh: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr20 + set_gr_immed 0,gr7 + nldsh @(sp,gr7),gr8 + test_gr_limmed 0xffff,0xdead,gr8 + test_spr_limmed 0x8860,0x0001,nesr0 + test_spr_gr neear0,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + inc_gr_immed 2,gr20 + set_gr_immed 2,gr7 + nldsh @(sp,gr7),gr8 + test_gr_limmed 0xffff,0xbeef,gr8 + test_spr_limmed 0x8860,0x0401,nesr1 + test_spr_gr neear1,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + nldsh @(sp,gr7),gr8 + test_gr_immed 0,gr8 + test_spr_limmed 0x8860,0x0801,nesr2 + test_spr_gr neear2,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + pass diff --git a/sim/testsuite/sim/frv/nldshi.cgs b/sim/testsuite/sim/frv/nldshi.cgs new file mode 100644 index 0000000..60de156 --- /dev/null +++ b/sim/testsuite/sim/frv/nldshi.cgs @@ -0,0 +1,38 @@ +# frv testcase for nldshi @($GRi,$d12),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global nldshi +nldshi: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr20 + nldshi @(sp,0),gr8 + test_gr_limmed 0xffff,0xdead,gr8 + test_spr_limmed 0x8860,0x0001,nesr0 + test_spr_gr neear0,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + inc_gr_immed 2,gr20 + nldshi @(sp,2),gr8 + test_gr_limmed 0xffff,0xbeef,gr8 + test_spr_limmed 0x8860,0x0401,nesr1 + test_spr_gr neear1,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + nldshi @(sp,-2),gr8 + test_gr_immed 0,gr8 + test_spr_limmed 0x8860,0x0801,nesr2 + test_spr_gr neear2,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + pass diff --git a/sim/testsuite/sim/frv/nldshu.cgs b/sim/testsuite/sim/frv/nldshu.cgs new file mode 100644 index 0000000..775b760 --- /dev/null +++ b/sim/testsuite/sim/frv/nldshu.cgs @@ -0,0 +1,55 @@ +# frv testcase for nldshu @($GRi,$GRj),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global nldshu +nldshu: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + nldshu @(sp,gr7),gr8 + test_gr_limmed 0xffff,0xdead,gr8 + test_gr_gr sp,gr9 + test_spr_limmed 0x8860,0x0001,nesr0 + test_spr_gr neear0,gr9 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + inc_gr_immed 2,gr9 + set_gr_immed 2,gr7 + nldshu @(sp,gr7),gr8 + test_gr_limmed 0xffff,0xbeef,gr8 + test_gr_gr sp,gr9 + test_spr_limmed 0x8860,0x0401,nesr1 + test_spr_gr neear1,gr9 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + inc_gr_immed -2,sp + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + nldshu @(sp,gr7),gr8 + test_gr_immed 0,gr8 + test_gr_gr sp,gr9 + test_spr_limmed 0x8860,0x0801,nesr2 + test_spr_gr neear2,gr9 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + inc_gr_immed -2,sp + set_mem_limmed 0x0000,0xdead,sp + set_gr_immed 2,gr7 + nldshu @(sp,gr7),sp + test_gr_limmed 0xffff,0xdead,sp + test_spr_limmed 0x8160,0x0c01,nesr3 + test_spr_gr neear3,gr9 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + pass diff --git a/sim/testsuite/sim/frv/nldu.cgs b/sim/testsuite/sim/frv/nldu.cgs new file mode 100644 index 0000000..0d1735e --- /dev/null +++ b/sim/testsuite/sim/frv/nldu.cgs @@ -0,0 +1,55 @@ +# frv testcase for nldu @($GRi,$GRj),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global nldu +nldu: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + nldu @(sp,gr7),gr8 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_gr sp,gr9 + test_spr_limmed 0x8880,0x0001,nesr0 + test_spr_gr neear0,gr9 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + nldu @(sp,gr7),gr8 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_gr sp,gr9 + test_spr_limmed 0x8880,0x0401,nesr1 + test_spr_gr neear1,gr9 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + set_gr_limmed 0xbeef,0xdead,gr8 + inc_gr_immed 4,sp + set_gr_immed -4,gr7 + nldu @(sp,gr7),gr8 + test_gr_limmed 0xdead,0xbeef,gr8 + test_gr_gr sp,gr9 + test_spr_limmed 0x8880,0x0801,nesr2 + test_spr_gr neear2,gr9 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + nldu @(sp,gr7),sp + test_gr_limmed 0xdead,0xbeef,sp + test_spr_limmed 0x8180,0x0c01,nesr3 + test_spr_gr neear3,gr9 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + pass diff --git a/sim/testsuite/sim/frv/nldub.cgs b/sim/testsuite/sim/frv/nldub.cgs new file mode 100644 index 0000000..2067bcc --- /dev/null +++ b/sim/testsuite/sim/frv/nldub.cgs @@ -0,0 +1,42 @@ +# frv testcase for nldub @($GRi,$GRj),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global nldub +nldub: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr20 + set_gr_immed 0,gr7 + nldub @(sp,gr7),gr8 + test_gr_limmed 0x0000,0x00de,gr8 + test_spr_limmed 0x8800,0x0001,nesr0 + test_spr_gr neear0,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + inc_gr_immed 1,gr20 + set_gr_immed 1,gr7 + nldub @(sp,gr7),gr8 + test_gr_limmed 0x0000,0x00ad,gr8 + test_spr_limmed 0x8800,0x0401,nesr1 + test_spr_gr neear1,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + inc_gr_immed 2,gr20 + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + nldub @(sp,gr7),gr8 + test_gr_limmed 0x0000,0x0000,gr8 + test_spr_limmed 0x8800,0x0801,nesr2 + test_spr_gr neear2,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + pass diff --git a/sim/testsuite/sim/frv/nldubi.cgs b/sim/testsuite/sim/frv/nldubi.cgs new file mode 100644 index 0000000..8eba516 --- /dev/null +++ b/sim/testsuite/sim/frv/nldubi.cgs @@ -0,0 +1,39 @@ +# frv testcase for nldubi @($GRi,$d12),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global nldubi +nldubi: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr20 + nldubi @(sp,0),gr8 + test_gr_limmed 0x0000,0x00de,gr8 + test_spr_limmed 0x8800,0x0001,nesr0 + test_spr_gr neear0,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + inc_gr_immed 1,gr20 + nldubi @(sp,1),gr8 + test_gr_limmed 0x0000,0x00ad,gr8 + test_spr_limmed 0x8800,0x0401,nesr1 + test_spr_gr neear1,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + inc_gr_immed 2,gr20 + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + nldubi @(sp,-1),gr8 + test_gr_limmed 0x0000,0x0000,gr8 + test_spr_limmed 0x8800,0x0801,nesr2 + test_spr_gr neear2,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + pass diff --git a/sim/testsuite/sim/frv/nldubu.cgs b/sim/testsuite/sim/frv/nldubu.cgs new file mode 100644 index 0000000..acf9d9c --- /dev/null +++ b/sim/testsuite/sim/frv/nldubu.cgs @@ -0,0 +1,55 @@ +# frv testcase for nldubu @($GRi,$GRj),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global nldubu +nldubu: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + nldubu @(sp,gr7),gr8 + test_gr_limmed 0x0000,0x00de,gr8 + test_gr_gr sp,gr9 + test_spr_limmed 0x8800,0x0001,nesr0 + test_spr_gr neear0,gr9 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + inc_gr_immed 1,gr9 + set_gr_immed 1,gr7 + nldubu @(sp,gr7),gr8 + test_gr_limmed 0x0000,0x00ad,gr8 + test_gr_gr sp,gr9 + test_spr_limmed 0x8800,0x0401,nesr1 + test_spr_gr neear1,gr9 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + inc_gr_immed 2,gr9 + inc_gr_immed -1,sp + set_mem_limmed 0xffff,0xff00,sp + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + nldubu @(sp,gr7),gr8 + test_gr_limmed 0x0000,0x0000,gr8 + test_spr_limmed 0x8800,0x0801,nesr2 + test_spr_gr neear2,gr9 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + inc_gr_immed -3,sp + set_mem_limmed 0xffff,0xffda,sp + set_gr_immed 3,gr7 + nldubu @(sp,gr7),sp + test_gr_limmed 0x0000,0x00da,sp + test_spr_limmed 0x8100,0x0c01,nesr3 + test_spr_gr neear3,gr9 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + pass diff --git a/sim/testsuite/sim/frv/nlduh.cgs b/sim/testsuite/sim/frv/nlduh.cgs new file mode 100644 index 0000000..1871a22 --- /dev/null +++ b/sim/testsuite/sim/frv/nlduh.cgs @@ -0,0 +1,41 @@ +# frv testcase for nlduh @($GRi,$GRj),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global nlduh +nlduh: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr20 + set_gr_immed 0,gr7 + nlduh @(sp,gr7),gr8 + test_gr_limmed 0x0000,0xdead,gr8 + test_spr_limmed 0x8840,0x0001,nesr0 + test_spr_gr neear0,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + inc_gr_immed 2,gr20 + set_gr_immed 2,gr7 + nlduh @(sp,gr7),gr8 + test_gr_limmed 0x0000,0xbeef,gr8 + test_spr_limmed 0x8840,0x0401,nesr1 + test_spr_gr neear1,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + nlduh @(sp,gr7),gr8 + test_gr_limmed 0x0000,0x0000,gr8 + test_spr_limmed 0x8840,0x0801,nesr2 + test_spr_gr neear2,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + pass diff --git a/sim/testsuite/sim/frv/nlduhi.cgs b/sim/testsuite/sim/frv/nlduhi.cgs new file mode 100644 index 0000000..ae7171e --- /dev/null +++ b/sim/testsuite/sim/frv/nlduhi.cgs @@ -0,0 +1,38 @@ +# frv testcase for nlduhi @($GRi,$d12),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global nlduhi +nlduhi: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr20 + nlduhi @(sp,0),gr8 + test_gr_limmed 0x0000,0xdead,gr8 + test_spr_limmed 0x8840,0x0001,nesr0 + test_spr_gr neear0,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + inc_gr_immed 2,gr20 + nlduhi @(sp,2),gr8 + test_gr_limmed 0x0000,0xbeef,gr8 + test_spr_limmed 0x8840,0x0401,nesr1 + test_spr_gr neear1,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + nlduhi @(sp,-2),gr8 + test_gr_limmed 0x0000,0x0000,gr8 + test_spr_limmed 0x8840,0x0801,nesr2 + test_spr_gr neear2,gr20 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + pass diff --git a/sim/testsuite/sim/frv/nlduhu.cgs b/sim/testsuite/sim/frv/nlduhu.cgs new file mode 100644 index 0000000..8142fc5 --- /dev/null +++ b/sim/testsuite/sim/frv/nlduhu.cgs @@ -0,0 +1,55 @@ +# frv testcase for nlduhu @($GRi,$GRj),$GRk +# mach: frv + + .include "testutils.inc" + + start + + .global nlduhu +nlduhu: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xbeef,0xdead,gr8 + + set_gr_gr sp,gr9 + set_gr_immed 0,gr7 + nlduhu @(sp,gr7),gr8 + test_gr_limmed 0x0000,0xdead,gr8 + test_gr_gr sp,gr9 + test_spr_limmed 0x8840,0x0001,nesr0 + test_spr_gr neear0,gr9 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + inc_gr_immed 2,gr9 + set_gr_immed 2,gr7 + nlduhu @(sp,gr7),gr8 + test_gr_limmed 0x0000,0xbeef,gr8 + test_gr_gr sp,gr9 + test_spr_limmed 0x8840,0x0401,nesr1 + test_spr_gr neear1,gr9 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + inc_gr_immed -2,sp + set_mem_limmed 0xffff,0x0000,sp + inc_gr_immed 4,sp + set_gr_immed -2,gr7 + nlduhu @(sp,gr7),gr8 + test_gr_limmed 0x0000,0x0000,gr8 + test_gr_gr sp,gr9 + test_spr_limmed 0x8840,0x0801,nesr2 + test_spr_gr neear2,gr9 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + inc_gr_immed -2,sp + set_mem_limmed 0xffff,0xdead,sp + set_gr_immed 2,gr7 + nlduhu @(sp,gr7),sp + test_gr_limmed 0x0000,0xdead,sp + test_spr_limmed 0x8140,0x0c01,nesr3 + test_spr_gr neear3,gr9 + test_spr_limmed 0x0000,0x0000,gner1 + test_spr_limmed 0x0000,0x0000,gner0 + + pass diff --git a/sim/testsuite/sim/frv/nop.cgs b/sim/testsuite/sim/frv/nop.cgs new file mode 100644 index 0000000..7180066 --- /dev/null +++ b/sim/testsuite/sim/frv/nop.cgs @@ -0,0 +1,12 @@ +# frv testcase for nop +# mach: all + + .include "testutils.inc" + + start + + .global nop +nop: + nop + + pass diff --git a/sim/testsuite/sim/frv/norcr.cgs b/sim/testsuite/sim/frv/norcr.cgs new file mode 100644 index 0000000..e097a1b --- /dev/null +++ b/sim/testsuite/sim/frv/norcr.cgs @@ -0,0 +1,59 @@ +# frv testcase for norcr $CCi,$CCj,$CCk +# mach: all + + .include "testutils.inc" + + start + + .global norcr +norcr: + set_spr_immed 0x1b1b,cccr + norcr cc7,cc7,cc3 + test_spr_immed 0x1b1b,cccr + + norcr cc7,cc6,cc3 + test_spr_immed 0x1b1b,cccr + + norcr cc7,cc5,cc3 + test_spr_immed 0x1bdb,cccr + + norcr cc7,cc4,cc3 + test_spr_immed 0x1b9b,cccr + + norcr cc6,cc7,cc3 + test_spr_immed 0x1b1b,cccr + + norcr cc6,cc6,cc3 + test_spr_immed 0x1b1b,cccr + + norcr cc6,cc5,cc3 + test_spr_immed 0x1bdb,cccr + + norcr cc6,cc4,cc3 + test_spr_immed 0x1b9b,cccr + + norcr cc5,cc7,cc3 + test_spr_immed 0x1bdb,cccr + + norcr cc5,cc6,cc3 + test_spr_immed 0x1bdb,cccr + + norcr cc5,cc5,cc3 + test_spr_immed 0x1bdb,cccr + + norcr cc5,cc4,cc3 + test_spr_immed 0x1b9b,cccr + + norcr cc4,cc7,cc3 + test_spr_immed 0x1b9b,cccr + + norcr cc4,cc6,cc3 + test_spr_immed 0x1b9b,cccr + + norcr cc4,cc5,cc3 + test_spr_immed 0x1b9b,cccr + + norcr cc4,cc4,cc3 + test_spr_immed 0x1b9b,cccr + + pass diff --git a/sim/testsuite/sim/frv/norncr.cgs b/sim/testsuite/sim/frv/norncr.cgs new file mode 100644 index 0000000..a7b95da --- /dev/null +++ b/sim/testsuite/sim/frv/norncr.cgs @@ -0,0 +1,59 @@ +# frv testcase for norncr $CCi,$CCj,$CCk +# mach: all + + .include "testutils.inc" + + start + + .global norncr +norncr: + set_spr_immed 0x1b1b,cccr + norncr cc7,cc7,cc3 + test_spr_immed 0x1b1b,cccr + + norncr cc7,cc6,cc3 + test_spr_immed 0x1b1b,cccr + + norncr cc7,cc5,cc3 + test_spr_immed 0x1bdb,cccr + + norncr cc7,cc4,cc3 + test_spr_immed 0x1b9b,cccr + + norncr cc6,cc7,cc3 + test_spr_immed 0x1b1b,cccr + + norncr cc6,cc6,cc3 + test_spr_immed 0x1b1b,cccr + + norncr cc6,cc5,cc3 + test_spr_immed 0x1bdb,cccr + + norncr cc6,cc4,cc3 + test_spr_immed 0x1b9b,cccr + + norncr cc5,cc7,cc3 + test_spr_immed 0x1b9b,cccr + + norncr cc5,cc6,cc3 + test_spr_immed 0x1b9b,cccr + + norncr cc5,cc5,cc3 + test_spr_immed 0x1b9b,cccr + + norncr cc5,cc4,cc3 + test_spr_immed 0x1b9b,cccr + + norncr cc4,cc7,cc3 + test_spr_immed 0x1bdb,cccr + + norncr cc4,cc6,cc3 + test_spr_immed 0x1bdb,cccr + + norncr cc4,cc5,cc3 + test_spr_immed 0x1bdb,cccr + + norncr cc4,cc4,cc3 + test_spr_immed 0x1b9b,cccr + + pass diff --git a/sim/testsuite/sim/frv/not.cgs b/sim/testsuite/sim/frv/not.cgs new file mode 100644 index 0000000..e44eabf --- /dev/null +++ b/sim/testsuite/sim/frv/not.cgs @@ -0,0 +1,18 @@ +# frv testcase for not $GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global not +not: + set_gr_limmed 0xaaaa,0xaaaa,gr7 + not gr7,gr7 + test_gr_limmed 0x5555,0x5555,gr7 + + set_gr_limmed 0xdead,0xbeef,gr7 + not gr7,gr7 + test_gr_limmed 0x2152,0x4110,gr7 + + pass diff --git a/sim/testsuite/sim/frv/notcr.cgs b/sim/testsuite/sim/frv/notcr.cgs new file mode 100644 index 0000000..e6c08e0 --- /dev/null +++ b/sim/testsuite/sim/frv/notcr.cgs @@ -0,0 +1,23 @@ +# frv testcase for notcr $CCi,$CCj,$CCk +# mach: all + + .include "testutils.inc" + + start + + .global notcr +notcr: + set_spr_immed 0x1b1b,cccr + notcr cc7,cc3 + test_spr_immed 0x1b5b,cccr + + notcr cc6,cc3 + test_spr_immed 0x1b1b,cccr + + notcr cc5,cc3 + test_spr_immed 0x1bdb,cccr + + notcr cc4,cc3 + test_spr_immed 0x1b9b,cccr + + pass diff --git a/sim/testsuite/sim/frv/nsdiv.cgs b/sim/testsuite/sim/frv/nsdiv.cgs new file mode 100644 index 0000000..533f2ef --- /dev/null +++ b/sim/testsuite/sim/frv/nsdiv.cgs @@ -0,0 +1,64 @@ +# frv testcase for nsdiv $GRi,$GRj,$GRk +# mach: fr500 fr550 frv + + .include "testutils.inc" + + start + + .global nsdiv +nsdiv: + set_spr_immed 0,gner0 + set_spr_immed 0,gner1 + + ; simple division 12 / 3 + set_gr_immed 3,gr3 + set_gr_immed 12,gr1 + nsdiv gr1,gr3,gr2 + test_gr_immed 4,gr2 + test_spr_immed 0,gner0 + test_spr_immed 0,gner1 + + ; Random example + set_gr_limmed 0x0123,0x4567,gr3 + set_gr_limmed 0xfedc,0xba98,gr1 + nsdiv gr1,gr3,gr2 + test_gr_immed -1,gr2 + test_spr_immed 0,gner0 + test_spr_immed 0,gner1 + + ; Special case from the Arch Spec Vol 2 + or_spr_immed 0x20,isr ; turn on isr.edem + set_gr_immed -1,gr3 + set_gr_limmed 0x8000,0x0000,gr1 + set_spr_immed 4,gner1 ; turn on NE bit for gr2 + nsdiv gr1,gr3,gr2 ; overflow is masked + test_gr_limmed 0x7fff,0xffff,gr2 + test_spr_bits 0x4,2,1,isr ; isr.aexc is set + test_spr_immed 0,gner0 + test_spr_immed 0,gner1 + + nsdiv gr1,gr0,gr32 ; divide by zero + test_spr_immed 1,gner0 + test_spr_immed 0,gner1 + + and_spr_immed -33,isr ; turn off isr.edem + set_gr_immed -1,gr3 + set_gr_limmed 0x8000,0x0000,gr1 + nsdiv gr1,gr3,gr2 + test_gr_limmed 0x8000,0x0000,gr2 + test_spr_immed 1,gner0 + test_spr_immed 4,gner1 + + nsdiv gr1,gr0,gr10 ; divide by zero + test_spr_immed 1,gner0 + test_spr_immed 0x00000404,gner1 + + ; simple division 12 / 3 -- should turn off ne flag + set_gr_immed 3,gr3 + set_gr_immed 12,gr1 + nsdiv gr1,gr3,gr2 + test_gr_immed 4,gr2 + test_spr_immed 1,gner0 + test_spr_immed 0x00000400,gner1 + + pass diff --git a/sim/testsuite/sim/frv/nsdivi.cgs b/sim/testsuite/sim/frv/nsdivi.cgs new file mode 100644 index 0000000..014fadd --- /dev/null +++ b/sim/testsuite/sim/frv/nsdivi.cgs @@ -0,0 +1,64 @@ +# frv testcase for nsdivi $GRi,$s12,$GRk +# mach: fr500 fr550 frv + + .include "testutils.inc" + + start + + .global nsdivi +nsdivi: + set_spr_immed 0,gner0 + set_spr_immed 0,gner1 + + ; simple division 12 / 3 + set_gr_immed 12,gr1 + nsdivi gr1,3,gr2 + test_gr_immed 4,gr2 + test_spr_immed 0,gner0 + test_spr_immed 0,gner1 + + ; Random example + set_gr_limmed 0xfedc,0xba98,gr1 + nsdivi gr1,0x7ff,gr2 + test_gr_limmed 0xffff,0xdb93,gr2 + test_spr_immed 0,gner0 + test_spr_immed 0,gner1 + + ; Random negative example + set_gr_limmed 0xfedc,0xba98,gr1 + nsdivi gr1,-2048,gr2 + test_gr_immed 0x2468,gr2 + test_spr_immed 0,gner0 + test_spr_immed 0,gner1 + + or_spr_immed 0x20,isr ; turn on isr.edem + set_gr_limmed 0x8000,0x0000,gr1 + nsdivi gr1,-1,gr2 + test_gr_limmed 0x7fff,0xffff,gr2 + test_spr_immed 0,gner0 + test_spr_immed 0,gner1 + + nsdivi gr1,0,gr32 ; divide by zero + test_spr_immed 1,gner0 + test_spr_immed 0,gner1 + + ; Special case from the Arch Spec Vol 2 + and_spr_immed -33,isr ; turn off isr.edem + set_gr_limmed 0x8000,0x0000,gr1 + nsdivi gr1,-1,gr2 + test_gr_limmed 0x8000,0x0000,gr2 + test_spr_immed 1,gner0 + test_spr_immed 4,gner1 + + nsdivi gr1,0,gr10 ; divide by zero + test_spr_immed 1,gner0 + test_spr_immed 0x00000404,gner1 + + ; simple division 12 / 3 -- should turn off ne flag + set_gr_immed 12,gr1 + nsdivi gr1,3,gr2 + test_gr_immed 4,gr2 + test_spr_immed 1,gner0 + test_spr_immed 0x00000400,gner1 + + pass diff --git a/sim/testsuite/sim/frv/nudiv.cgs b/sim/testsuite/sim/frv/nudiv.cgs new file mode 100644 index 0000000..58bce82 --- /dev/null +++ b/sim/testsuite/sim/frv/nudiv.cgs @@ -0,0 +1,49 @@ +# frv testcase for nudiv $GRi,$GRj,$GRk +# mach: fr500 fr550 frv + + .include "testutils.inc" + + start + + .global nudiv +nudiv: + set_spr_immed 0,gner0 + set_spr_immed 0,gner1 + + ; simple division 12 / 3 + set_gr_immed 0x00000003,gr2 + set_gr_immed 0x0000000c,gr3 + nudiv gr3,gr2,gr3 + test_gr_immed 0x00000003,gr2 + test_gr_immed 0x00000004,gr3 + test_spr_immed 0,gner0 + test_spr_immed 0,gner1 + + ; example 1 from the fr30 manual + set_gr_limmed 0x0123,0x4567,gr2 + set_gr_limmed 0xfedc,0xba98,gr3 + nudiv gr3,gr2,gr3 + test_gr_limmed 0x0123,0x4567,gr2 + test_gr_immed 0x000000e0,gr3 + test_spr_immed 0,gner0 + test_spr_immed 0,gner1 + + or_spr_immed 0x20,isr ; turn on isr.edem + nudiv gr1,gr0,gr32 ; divide by zero + test_spr_immed 1,gner0 + test_spr_immed 0,gner1 + + and_spr_immed -33,isr ; turn off isr.edem + nudiv gr1,gr0,gr10 ; divide by zero + test_spr_immed 1,gner0 + test_spr_immed 0x00000400,gner1 + + ; simple division 12 / 3 -- should turn off ne flag + set_gr_immed 12,gr1 + set_gr_immed 3,gr3 + nudiv gr1,gr3,gr10 + test_gr_immed 4,gr10 + test_spr_immed 1,gner0 + test_spr_immed 0,gner1 + + pass diff --git a/sim/testsuite/sim/frv/nudivi.cgs b/sim/testsuite/sim/frv/nudivi.cgs new file mode 100644 index 0000000..2426eb3 --- /dev/null +++ b/sim/testsuite/sim/frv/nudivi.cgs @@ -0,0 +1,51 @@ +# frv testcase for nudivi $GRi,$s12,$GRk +# mach: fr500 fr550 frv + + .include "testutils.inc" + + start + + .global nudivi +nudivi: + set_spr_immed 0,gner0 + set_spr_immed 0,gner1 + + ; simple division 12 / 3 + set_gr_immed 0x0000000c,gr3 + nudivi gr3,3,gr3 + test_gr_immed 0x00000004,gr3 + test_spr_immed 0,gner0 + test_spr_immed 0,gner1 + + ; random example + set_gr_limmed 0xfedc,0xba98,gr3 + nudivi gr3,0x7ff,gr3 + test_gr_limmed 0x001f,0xdf93,gr3 + test_spr_immed 0,gner0 + test_spr_immed 0,gner1 + + ; random example + set_gr_limmed 0xffff,0xffff,gr3 + nudivi gr3,-2048,gr3 + test_gr_immed 1,gr3 + test_spr_immed 0,gner0 + test_spr_immed 0,gner1 + + or_spr_immed 0x20,isr ; turn on isr.edem + nudivi gr1,0,gr32 ; divide by zero + test_spr_immed 1,gner0 + test_spr_immed 0,gner1 + + and_spr_immed -33,isr ; turn off isr.edem + nudivi gr1,0,gr10 ; divide by zero + test_spr_immed 1,gner0 + test_spr_immed 0x00000400,gner1 + + ; simple division 12 / 3 -- should turn off ne flag + set_gr_immed 12,gr1 + nudivi gr1,3,gr10 + test_gr_immed 4,gr10 + test_spr_immed 1,gner0 + test_spr_immed 0,gner1 + + pass diff --git a/sim/testsuite/sim/frv/or.cgs b/sim/testsuite/sim/frv/or.cgs new file mode 100644 index 0000000..b432429 --- /dev/null +++ b/sim/testsuite/sim/frv/or.cgs @@ -0,0 +1,31 @@ +# frv testcase for or $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global or +or: + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x07,0 ; Set mask opposite of expected + or gr7,gr8,gr8 + test_icc 0 1 1 1 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + + set_gr_immed 0x00000000,gr7 + set_gr_immed 0x00000000,gr8 + set_icc 0x08,0 ; Set mask opposite of expected + or gr7,gr8,gr8 + test_icc 1 0 0 0 icc0 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0x0000,gr7 + set_gr_limmed 0x0000,0xbeef,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + or gr7,gr8,gr8 + test_icc 0 1 0 1 icc0 + test_gr_limmed 0xdead,0xbeef,gr8 + + pass diff --git a/sim/testsuite/sim/frv/orcc.cgs b/sim/testsuite/sim/frv/orcc.cgs new file mode 100644 index 0000000..a0a3e5b --- /dev/null +++ b/sim/testsuite/sim/frv/orcc.cgs @@ -0,0 +1,31 @@ +# frv testcase for orcc $GRi,$GRj,$GRk,$ICCi_1 +# mach: all + + .include "testutils.inc" + + start + + .global orcc +orcc: + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x07,0 ; Set mask opposite of expected + orcc gr7,gr8,gr8,icc0 + test_icc 1 0 1 1 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + + set_gr_immed 0x00000000,gr7 + set_gr_immed 0x00000000,gr8 + set_icc 0x08,0 ; Set mask opposite of expected + orcc gr7,gr8,gr8,icc0 + test_icc 0 1 0 0 icc0 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0x0000,gr7 + set_gr_limmed 0x0000,0xbeef,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + orcc gr7,gr8,gr8,icc0 + test_icc 1 0 0 1 icc0 + test_gr_limmed 0xdead,0xbeef,gr8 + + pass diff --git a/sim/testsuite/sim/frv/orcr.cgs b/sim/testsuite/sim/frv/orcr.cgs new file mode 100644 index 0000000..a5114b2 --- /dev/null +++ b/sim/testsuite/sim/frv/orcr.cgs @@ -0,0 +1,59 @@ +# frv testcase for orcr $CCi,$CCj,$CCk +# mach: all + + .include "testutils.inc" + + start + + .global orcr +orcr: + set_spr_immed 0x1b1b,cccr + orcr cc7,cc7,cc3 + test_spr_immed 0x1b1b,cccr + + orcr cc7,cc6,cc3 + test_spr_immed 0x1b1b,cccr + + orcr cc7,cc5,cc3 + test_spr_immed 0x1b9b,cccr + + orcr cc7,cc4,cc3 + test_spr_immed 0x1bdb,cccr + + orcr cc6,cc7,cc3 + test_spr_immed 0x1b1b,cccr + + orcr cc6,cc6,cc3 + test_spr_immed 0x1b1b,cccr + + orcr cc6,cc5,cc3 + test_spr_immed 0x1b9b,cccr + + orcr cc6,cc4,cc3 + test_spr_immed 0x1bdb,cccr + + orcr cc5,cc7,cc3 + test_spr_immed 0x1b9b,cccr + + orcr cc5,cc6,cc3 + test_spr_immed 0x1b9b,cccr + + orcr cc5,cc5,cc3 + test_spr_immed 0x1b9b,cccr + + orcr cc5,cc4,cc3 + test_spr_immed 0x1bdb,cccr + + orcr cc4,cc7,cc3 + test_spr_immed 0x1bdb,cccr + + orcr cc4,cc6,cc3 + test_spr_immed 0x1bdb,cccr + + orcr cc4,cc5,cc3 + test_spr_immed 0x1bdb,cccr + + orcr cc4,cc4,cc3 + test_spr_immed 0x1bdb,cccr + + pass diff --git a/sim/testsuite/sim/frv/ori.cgs b/sim/testsuite/sim/frv/ori.cgs new file mode 100644 index 0000000..aa1d61a --- /dev/null +++ b/sim/testsuite/sim/frv/ori.cgs @@ -0,0 +1,34 @@ +# frv testcase for ori $GRi,$s12,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global ori +ori: + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_icc 0x07,0 ; Set mask opposite of expected + ori gr7,0x555,gr8 + test_icc 0 1 1 1 icc0 + test_gr_limmed 0xaaaa,0xafff,gr8 + + set_gr_immed 0x00000000,gr7 + set_icc 0x08,0 ; Set mask opposite of expected + ori gr7,0,gr8 + test_icc 1 0 0 0 icc0 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0xb800,gr7 + set_icc 0x05,0 ; Set mask opposite of expected + ori gr7,0x6ef,gr8 + test_icc 0 1 0 1 icc0 + test_gr_limmed 0xdead,0xbeef,gr8 + + set_gr_limmed 0xdead,0xb000,gr7 + set_icc 0x05,0 ; Set mask opposite of expected + ori gr7,-273,gr8 + test_icc 0 1 0 1 icc0 + test_gr_limmed 0xffff,0xfeef,gr8 + + pass diff --git a/sim/testsuite/sim/frv/oricc.cgs b/sim/testsuite/sim/frv/oricc.cgs new file mode 100644 index 0000000..71e6d53 --- /dev/null +++ b/sim/testsuite/sim/frv/oricc.cgs @@ -0,0 +1,34 @@ +# frv testcase for oricc $GRi,$s10,$GRk,$ICCi_1 +# mach: all + + .include "testutils.inc" + + start + + .global oricc +oricc: + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_icc 0x07,0 ; Set mask opposite of expected + oricc gr7,0x155,gr8,icc0 + test_icc 1 0 1 1 icc0 + test_gr_limmed 0xaaaa,0xabff,gr8 + + set_gr_immed 0x00000000,gr7 + set_icc 0x08,0 ; Set mask opposite of expected + oricc gr7,0,gr8,icc0 + test_icc 0 1 0 0 icc0 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0xbe00,gr7 + set_icc 0x05,0 ; Set mask opposite of expected + oricc gr7,0x0ef,gr8,icc0 + test_icc 1 0 0 1 icc0 + test_gr_limmed 0xdead,0xbeef,gr8 + + set_gr_limmed 0xdead,0xb000,gr7 + set_icc 0x05,0 ; Set mask opposite of expected + oricc gr7,-273,gr8,icc0 + test_icc 1 0 0 1 icc0 + test_gr_limmed 0xffff,0xfeef,gr8 + + pass diff --git a/sim/testsuite/sim/frv/orncr.cgs b/sim/testsuite/sim/frv/orncr.cgs new file mode 100644 index 0000000..b0e4e59 --- /dev/null +++ b/sim/testsuite/sim/frv/orncr.cgs @@ -0,0 +1,59 @@ +# frv testcase for orncr $CCi,$CCj,$CCk +# mach: all + + .include "testutils.inc" + + start + + .global orncr +orncr: + set_spr_immed 0x1b1b,cccr + orncr cc7,cc7,cc3 + test_spr_immed 0x1b1b,cccr + + orncr cc7,cc6,cc3 + test_spr_immed 0x1b1b,cccr + + orncr cc7,cc5,cc3 + test_spr_immed 0x1b9b,cccr + + orncr cc7,cc4,cc3 + test_spr_immed 0x1bdb,cccr + + orncr cc6,cc7,cc3 + test_spr_immed 0x1b1b,cccr + + orncr cc6,cc6,cc3 + test_spr_immed 0x1b1b,cccr + + orncr cc6,cc5,cc3 + test_spr_immed 0x1b9b,cccr + + orncr cc6,cc4,cc3 + test_spr_immed 0x1bdb,cccr + + orncr cc5,cc7,cc3 + test_spr_immed 0x1bdb,cccr + + orncr cc5,cc6,cc3 + test_spr_immed 0x1bdb,cccr + + orncr cc5,cc5,cc3 + test_spr_immed 0x1bdb,cccr + + orncr cc5,cc4,cc3 + test_spr_immed 0x1bdb,cccr + + orncr cc4,cc7,cc3 + test_spr_immed 0x1b9b,cccr + + orncr cc4,cc6,cc3 + test_spr_immed 0x1b9b,cccr + + orncr cc4,cc5,cc3 + test_spr_immed 0x1b9b,cccr + + orncr cc4,cc4,cc3 + test_spr_immed 0x1bdb,cccr + + pass diff --git a/sim/testsuite/sim/frv/parallel.exp b/sim/testsuite/sim/frv/parallel.exp new file mode 100644 index 0000000..8101a67a --- /dev/null +++ b/sim/testsuite/sim/frv/parallel.exp @@ -0,0 +1,19 @@ +# FRV simulator testsuite. + +if [istarget frv*-*] { + # load support procs (none yet) + # load_lib cgen.exp + # all machines + set all_machs "frv fr500 fr550 fr400" + set cpu_option -mcpu + + # The .pcgs suffix is for "parallel cgen .s". + foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.pcgs]] { + # If we're only testing specific files and this isn't one of them, + # skip it. + if ![runtest_file_p $runtests $src] { + continue + } + run_sim_test $src $all_machs + } +} diff --git a/sim/testsuite/sim/frv/ret.cgs b/sim/testsuite/sim/frv/ret.cgs new file mode 100644 index 0000000..1447998 --- /dev/null +++ b/sim/testsuite/sim/frv/ret.cgs @@ -0,0 +1,91 @@ +# frv testcase for ret +# mach: all + + .include "testutils.inc" + + start + + .global ret +ret: + set_spr_addr ok1,lr + set_icc 0x0 0 + ret + fail +ok1: + set_spr_addr ok2,lr + set_icc 0x1 1 + ret + fail +ok2: + set_spr_addr ok3,lr + set_icc 0x2 2 + ret + fail +ok3: + set_spr_addr ok4,lr + set_icc 0x3 3 + ret + fail +ok4: + set_spr_addr ok5,lr + set_icc 0x4 0 + ret + fail +ok5: + set_spr_addr ok6,lr + set_icc 0x5 1 + ret + fail +ok6: + set_spr_addr ok7,lr + set_icc 0x6 2 + ret + fail +ok7: + set_spr_addr ok8,lr + set_icc 0x7 3 + ret + fail +ok8: + set_spr_addr ok9,lr + set_icc 0x8 0 + ret + fail +ok9: + set_spr_addr oka,lr + set_icc 0x9 1 + ret + fail +oka: + set_spr_addr okb,lr + set_icc 0xa 2 + ret + fail +okb: + set_spr_addr okc,lr + set_icc 0xb 3 + ret + fail +okc: + set_spr_addr okd,lr + set_icc 0xc 0 + ret + fail +okd: + set_spr_addr oke,lr + set_icc 0xd 1 + ret + fail +oke: + set_spr_addr okf,lr + set_icc 0xe 2 + ret + fail +okf: + set_spr_addr okg,lr + set_icc 0xf 3 + ret + fail +okg: + + pass diff --git a/sim/testsuite/sim/frv/rett.cgs b/sim/testsuite/sim/frv/rett.cgs new file mode 100644 index 0000000..f964bae --- /dev/null +++ b/sim/testsuite/sim/frv/rett.cgs @@ -0,0 +1,30 @@ +# frv testcase for rett $debug +# mach: all + + .include "testutils.inc" + + start + + .global rett +rett: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + + set_psr_et 1 + set_spr_addr ok1,lr + set_icc 0x0 0 + tira gr7,4 ; should branch to tbr + (128 + 4)*16 +ok0: + test_gr_immed 1,gr7 + pass + fail +ok1: + inc_gr_immed 1,gr7 + rett 1 ; should be a nop + rett 0 + fail diff --git a/sim/testsuite/sim/frv/rst.cgs b/sim/testsuite/sim/frv/rst.cgs new file mode 100644 index 0000000..c8ba442 --- /dev/null +++ b/sim/testsuite/sim/frv/rst.cgs @@ -0,0 +1,107 @@ +# frv testcase for rst $GRk,@($GRi,$GRj) +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global rst +rst: + ; No nesr's active + set_gr_gr sp,gr10 + set_gr_gr sp,gr24 + set_mem_limmed 0x2222,0x2222,gr24 + set_gr_gr gr24,gr27 + inc_gr_immed -4,gr27 + set_mem_limmed 0x3333,0x3333,gr27 + set_gr_gr gr27,gr26 + inc_gr_immed -4,gr26 + set_mem_limmed 0x4444,0x4444,gr26 + set_gr_gr gr26,gr25 + inc_gr_immed -4,gr25 + set_mem_limmed 0x5555,0x5555,gr25 + set_gr_limmed 0x1111,0x1111,gr20 + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + rst gr8,@(sp,gr7) + test_mem_limmed 0xffff,0xffff,gr24 + test_mem_limmed 0x3333,0x3333,gr27 + test_mem_limmed 0x4444,0x4444,gr26 + test_mem_limmed 0x5555,0x5555,gr25 + test_gr_limmed 0x1111,0x1111,gr20 + + ; 1 nesr active with the incorrect address in neear for gr + nldi @(sp,0),gr20 + test_spr_gr neear0,gr10 + set_mem_limmed 0x2222,0x2222,gr24 + set_mem_limmed 0x3333,0x3333,gr27 + set_mem_limmed 0x4444,0x4444,gr26 + set_mem_limmed 0x5555,0x5555,gr25 + set_gr_limmed 0x1111,0x1111,gr20 + set_gr_limmed 0xffff,0xffff,gr8 + set_gr_immed -4,gr7 + rst gr8,@(sp,gr7) + test_mem_limmed 0x2222,0x2222,gr24 + test_mem_limmed 0xffff,0xffff,gr27 + test_mem_limmed 0x4444,0x4444,gr26 + test_mem_limmed 0x5555,0x5555,gr25 + test_gr_limmed 0x1111,0x1111,gr20 + + ; 1 nesr active with the incorrect address in neear for fr + inc_gr_immed -4,gr10 + nldfi @(sp,-4),fr20 + test_spr_gr neear1,gr10 + set_mem_limmed 0x2222,0x2222,gr24 + set_mem_limmed 0x3333,0x3333,gr27 + set_mem_limmed 0x4444,0x4444,gr26 + set_mem_limmed 0x5555,0x5555,gr25 + set_fr_iimmed 0x1111,0x1111,fr20 + set_gr_limmed 0xffff,0xffff,gr8 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + rst gr8,@(sp,gr7) + test_mem_limmed 0xffff,0xffff,gr24 + test_mem_limmed 0x3333,0x3333,gr27 + test_mem_limmed 0x4444,0x4444,gr26 + test_mem_limmed 0x5555,0x5555,gr25 + test_fr_limmed 0x1111,0x1111,fr20 + + ; 1 nesr active with the correct address in neear for gr + inc_gr_immed -4,gr10 + nldi @(sp,-4),gr20 + test_spr_gr neear2,gr10 + set_mem_limmed 0x2222,0x2222,gr24 + set_mem_limmed 0x3333,0x3333,gr27 + set_mem_limmed 0x4444,0x4444,gr26 + set_mem_limmed 0x5555,0x5555,gr25 + set_gr_limmed 0x1111,0x1111,gr20 + set_gr_limmed 0xffff,0xffff,gr8 + inc_gr_immed -4,sp + set_gr_immed 0,gr7 + rst gr8,@(sp,gr7) + test_mem_limmed 0x2222,0x2222,gr24 + test_mem_limmed 0x3333,0x3333,gr27 + test_mem_limmed 0xffff,0xffff,gr26 + test_mem_limmed 0x5555,0x5555,gr25 + test_gr_limmed 0xffff,0xffff,gr20 + + ; 1 nesr active with the correct address in neear for fr + inc_gr_immed -4,gr10 + nldfi @(sp,-4),fr20 + test_spr_gr neear3,gr10 + set_mem_limmed 0x2222,0x2222,gr24 + set_mem_limmed 0x3333,0x3333,gr27 + set_mem_limmed 0x4444,0x4444,gr26 + set_mem_limmed 0x5555,0x5555,gr25 + set_fr_iimmed 0x1111,0x1111,fr20 + set_gr_limmed 0xffff,0xffff,gr8 + set_gr_immed -4,gr7 + rst gr8,@(sp,gr7) + test_mem_limmed 0x2222,0x2222,gr24 + test_mem_limmed 0x3333,0x3333,gr27 + test_mem_limmed 0x4444,0x4444,gr26 + test_mem_limmed 0xffff,0xffff,gr25 + test_fr_limmed 0xffff,0xffff,fr20 + + pass diff --git a/sim/testsuite/sim/frv/rstb.cgs b/sim/testsuite/sim/frv/rstb.cgs new file mode 100644 index 0000000..e7bab42 --- /dev/null +++ b/sim/testsuite/sim/frv/rstb.cgs @@ -0,0 +1,72 @@ +# frv testcase for rstb $GRk,@($GRi,$GRj) +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global add +add: + ; No nesr's active + set_gr_gr sp,gr21 + set_gr_gr gr21,gr22 + set_gr_limmed 0x1111,0x1111,gr20 + set_mem_limmed 0x2222,0x2222,gr21 + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + rstb gr8,@(sp,gr7) + test_mem_limmed 0xff22,0x2222,sp + test_gr_limmed 0x1111,0x1111,gr20 + + ; 1 nesr active with the incorrect address in neear for gr + inc_gr_immed 3,gr22 + nldubi @(sp,3),gr20 + test_spr_gr neear0,gr22 + set_gr_limmed 0x1111,0x1111,gr20 + set_mem_limmed 0x2222,0x2222,gr21 + set_gr_limmed 0xffff,0xffff,gr8 + inc_gr_immed 1,gr7 + rstb gr8,@(sp,gr7) + test_mem_limmed 0x22ff,0x2222,gr21 + test_gr_limmed 0x1111,0x1111,gr20 + + ; 1 nesr active with the incorrect address in neear for fr + inc_gr_immed -1,gr22 + nldbfi @(sp,2),fr20 + test_spr_gr neear1,gr22 + set_fr_iimmed 0x1111,0x1111,fr20 + set_mem_limmed 0x2222,0x2222,gr21 + set_gr_limmed 0xffff,0xffff,gr8 + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + rstb gr8,@(sp,gr7) + test_mem_limmed 0x2222,0x22ff,gr21 + test_fr_limmed 0x1111,0x1111,fr20 + + ; 1 nesr active with the correct address in neear for gr + inc_gr_immed -1,gr22 + nldubi @(sp,-3),gr20 + test_spr_gr neear2,gr22 + set_gr_limmed 0x1111,0x1111,gr20 + set_mem_limmed 0x2222,0x2222,gr21 + set_gr_limmed 0xffff,0xffff,gr8 + inc_gr_immed -4,sp + set_gr_immed 1,gr7 + rstb gr8,@(sp,gr7) + test_mem_limmed 0x22ff,0x2222,gr21 + test_gr_limmed 0x0000,0x00ff,gr20 + + ; 1 nesr active with the correct address in neear for fr + inc_gr_immed -1,gr22 + nldbfi @(sp,0),fr20 + test_spr_gr neear3,gr22 + set_fr_iimmed 0x1111,0x1111,fr20 + set_mem_limmed 0x2222,0x2222,gr21 + set_gr_limmed 0xffff,0xffff,gr8 + set_gr_immed 0,gr7 + rstb gr8,@(sp,gr7) + test_mem_limmed 0xff22,0x2222,gr21 + test_fr_limmed 0x0000,0x00ff,fr20 + + pass diff --git a/sim/testsuite/sim/frv/rstbf.cgs b/sim/testsuite/sim/frv/rstbf.cgs new file mode 100644 index 0000000..e35260a --- /dev/null +++ b/sim/testsuite/sim/frv/rstbf.cgs @@ -0,0 +1,76 @@ +# frv testcase for rstbf $FRk,@($GRi,$GRj) +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global add +add: + ; No nesr's active + set_gr_gr sp,gr21 + set_gr_gr gr21,gr22 + set_fr_iimmed 0x1111,0x1111,fr20 + set_gr_limmed 0x1111,0x1111,gr20 + set_mem_limmed 0x2222,0x2222,gr21 + set_gr_immed 0,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + rstbf fr8,@(sp,gr7) + test_mem_limmed 0xff22,0x2222,sp + test_gr_limmed 0x1111,0x1111,gr20 + test_fr_limmed 0x1111,0x1111,fr20 + + ; 1 nesr active with the incorrect address in neear for gr + inc_gr_immed 1,gr22 + nldubi @(sp,1),gr20 + test_spr_gr neear0,gr22 + set_gr_limmed 0x1111,0x1111,gr20 + set_fr_iimmed 0x1111,0x1111,fr20 + set_mem_limmed 0x2222,0x2222,gr21 + set_fr_iimmed 0xffff,0xffff,fr8 + inc_gr_immed 2,gr7 + rstbf fr8,@(sp,gr7) + test_mem_limmed 0x2222,0xff22,gr21 + test_gr_limmed 0x1111,0x1111,gr20 + test_fr_limmed 0x1111,0x1111,fr20 + + ; 1 nesr active with the incorrect address in neear for fr + inc_gr_immed -1,gr22 + nldbfi @(sp,0),fr20 + test_spr_gr neear1,gr22 + set_gr_limmed 0x1111,0x1111,gr20 + set_fr_iimmed 0x1111,0x1111,fr20 + set_mem_limmed 0x2222,0x2222,gr21 + set_fr_iimmed 0xffff,0xffff,fr8 + inc_gr_immed 4,sp + set_gr_immed -1,gr7 + rstbf fr8,@(sp,gr7) + test_mem_limmed 0x2222,0x22ff,gr21 + test_gr_limmed 0x1111,0x1111,gr20 + test_fr_limmed 0x1111,0x1111,fr20 + + ; 1 nesr active with the correct address in neear for gr + set_gr_limmed 0x1111,0x1111,gr20 + set_fr_iimmed 0x1111,0x1111,fr20 + set_mem_limmed 0x2222,0x2222,gr21 + set_fr_iimmed 0xffff,0xffff,fr8 + inc_gr_immed -4,sp + set_gr_immed 1,gr7 + rstbf fr8,@(sp,gr7) + test_mem_limmed 0x22ff,0x2222,gr21 + test_gr_limmed 0x0000,0x00ff,gr20 + test_fr_limmed 0x1111,0x1111,fr20 + + ; 1 nesr active with the correct address in neear for fr + set_gr_limmed 0x1111,0x1111,gr20 + set_fr_iimmed 0x1111,0x1111,fr20 + set_mem_limmed 0x2222,0x2222,gr21 + set_fr_iimmed 0xffff,0xffff,fr8 + set_gr_immed 0,gr7 + rstbf fr8,@(sp,gr7) + test_mem_limmed 0xff22,0x2222,gr21 + test_gr_limmed 0x1111,0x1111,gr20 + test_fr_limmed 0x0000,0x00ff,fr20 + + pass diff --git a/sim/testsuite/sim/frv/rstd.cgs b/sim/testsuite/sim/frv/rstd.cgs new file mode 100644 index 0000000..bf67635 --- /dev/null +++ b/sim/testsuite/sim/frv/rstd.cgs @@ -0,0 +1,171 @@ +# frv testcase for rstd $GRk,@($GRi,$GRj) +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global add +add: + ; No nesr's active + set_gr_gr sp,gr20 + set_mem_limmed 0x2222,0x2222,gr20 + set_gr_gr gr20,gr27 + inc_gr_immed -4,gr27 + set_mem_limmed 0x3333,0x3333,gr27 + set_gr_gr gr27,gr26 + inc_gr_immed -4,gr26 + set_mem_limmed 0x4444,0x4444,gr26 + set_gr_gr gr26,gr25 + inc_gr_immed -4,gr25 + set_mem_limmed 0x5555,0x5555,gr25 + set_gr_gr gr25,gr24 + inc_gr_immed -4,gr24 + set_mem_limmed 0x6666,0x6666,gr24 + set_gr_gr gr24,gr23 + inc_gr_immed -4,gr23 + set_mem_limmed 0x7777,0x7777,gr23 + set_gr_gr gr23,gr22 + inc_gr_immed -4,gr22 + set_mem_limmed 0x8888,0x8888,gr22 + set_gr_gr gr22,gr21 + inc_gr_immed -4,gr21 + set_mem_limmed 0x9999,0x9999,gr21 + set_gr_limmed 0x1111,0x1111,gr40 + set_gr_limmed 0x1111,0x1111,gr41 + inc_gr_immed -4,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xeeee,0xeeee,gr8 + set_gr_limmed 0xffff,0xffff,gr9 + rstd gr8,@(sp,gr7) + test_mem_limmed 0xffff,0xffff,gr20 + test_mem_limmed 0xeeee,0xeeee,gr27 + test_mem_limmed 0x4444,0x4444,gr26 + test_mem_limmed 0x5555,0x5555,gr25 + test_mem_limmed 0x6666,0x6666,gr24 + test_mem_limmed 0x7777,0x7777,gr23 + test_mem_limmed 0x8888,0x8888,gr22 + test_mem_limmed 0x9999,0x9999,gr21 + test_gr_limmed 0x1111,0x1111,gr40 + test_gr_limmed 0x1111,0x1111,gr41 + + ; 1 nesr active with the incorrect address in neear for gr + set_gr_gr sp,gr10 + nlddi @(sp,0),gr40 + test_spr_gr neear0,gr10 + set_mem_limmed 0x2222,0x2222,gr20 + set_mem_limmed 0x3333,0x3333,gr27 + set_mem_limmed 0x4444,0x4444,gr26 + set_mem_limmed 0x5555,0x5555,gr25 + set_mem_limmed 0x6666,0x6666,gr24 + set_mem_limmed 0x7777,0x7777,gr23 + set_mem_limmed 0x8888,0x8888,gr22 + set_mem_limmed 0x9999,0x9999,gr21 + set_gr_limmed 0xeeee,0xeeee,gr8 + set_gr_limmed 0xffff,0xffff,gr9 + set_gr_limmed 0x1111,0x1111,gr40 + set_gr_limmed 0x1111,0x1111,gr41 + set_gr_immed -8,gr7 + rstd gr8,@(sp,gr7) + test_mem_limmed 0x2222,0x2222,gr20 + test_mem_limmed 0x3333,0x3333,gr27 + test_mem_limmed 0xffff,0xffff,gr26 + test_mem_limmed 0xeeee,0xeeee,gr25 + test_mem_limmed 0x6666,0x6666,gr24 + test_mem_limmed 0x7777,0x7777,gr23 + test_mem_limmed 0x8888,0x8888,gr22 + test_mem_limmed 0x9999,0x9999,gr21 + test_gr_limmed 0x1111,0x1111,gr40 + test_gr_limmed 0x1111,0x1111,gr41 + + ; 1 nesr active with the incorrect address in neear for fr + inc_gr_immed -8,gr10 + nlddfi @(sp,-8),fr40 + test_spr_gr neear1,gr10 + set_mem_limmed 0x2222,0x2222,gr20 + set_mem_limmed 0x3333,0x3333,gr27 + set_mem_limmed 0x4444,0x4444,gr26 + set_mem_limmed 0x5555,0x5555,gr25 + set_mem_limmed 0x6666,0x6666,gr24 + set_mem_limmed 0x7777,0x7777,gr23 + set_mem_limmed 0x8888,0x8888,gr22 + set_mem_limmed 0x9999,0x9999,gr21 + set_gr_limmed 0xeeee,0xeeee,gr8 + set_gr_limmed 0xffff,0xffff,gr9 + set_fr_iimmed 0x1111,0x1111,fr40 + set_fr_iimmed 0x1111,0x1111,fr41 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + rstd gr8,@(sp,gr7) + test_mem_limmed 0xffff,0xffff,gr20 + test_mem_limmed 0xeeee,0xeeee,gr27 + test_mem_limmed 0x4444,0x4444,gr26 + test_mem_limmed 0x5555,0x5555,gr25 + test_mem_limmed 0x6666,0x6666,gr24 + test_mem_limmed 0x7777,0x7777,gr23 + test_mem_limmed 0x8888,0x8888,gr22 + test_mem_limmed 0x9999,0x9999,gr21 + test_fr_limmed 0x1111,0x1111,fr40 + test_fr_limmed 0x1111,0x1111,fr41 + + ; 1 nesr active with the correct address in neear for gr + inc_gr_immed -8,gr10 + nlddi @(sp,-8),gr40 + test_spr_gr neear2,gr10 + set_mem_limmed 0x2222,0x2222,gr20 + set_mem_limmed 0x3333,0x3333,gr27 + set_mem_limmed 0x4444,0x4444,gr26 + set_mem_limmed 0x5555,0x5555,gr25 + set_mem_limmed 0x6666,0x6666,gr24 + set_mem_limmed 0x7777,0x7777,gr23 + set_mem_limmed 0x8888,0x8888,gr22 + set_mem_limmed 0x9999,0x9999,gr21 + set_gr_limmed 0xeeee,0xeeee,gr8 + set_gr_limmed 0xffff,0xffff,gr9 + set_gr_limmed 0x1111,0x1111,gr40 + set_gr_limmed 0x1111,0x1111,gr41 + inc_gr_immed -8,sp + set_gr_immed 0,gr7 + rstd gr8,@(sp,gr7) + test_mem_limmed 0x2222,0x2222,gr20 + test_mem_limmed 0x3333,0x3333,gr27 + test_mem_limmed 0x4444,0x4444,gr26 + test_mem_limmed 0x5555,0x5555,gr25 + test_mem_limmed 0xffff,0xffff,gr24 + test_mem_limmed 0xeeee,0xeeee,gr23 + test_mem_limmed 0x8888,0x8888,gr22 + test_mem_limmed 0x9999,0x9999,gr21 + test_gr_limmed 0xffff,0xffff,gr41 + test_gr_limmed 0xeeee,0xeeee,gr40 + + ; 1 nesr active with the correct address in neear for fr + inc_gr_immed -8,gr10 + nlddfi @(sp,-8),fr40 + test_spr_gr neear3,gr10 + set_mem_limmed 0x2222,0x2222,gr20 + set_mem_limmed 0x3333,0x3333,gr27 + set_mem_limmed 0x4444,0x4444,gr26 + set_mem_limmed 0x5555,0x5555,gr25 + set_mem_limmed 0x6666,0x6666,gr24 + set_mem_limmed 0x7777,0x7777,gr23 + set_mem_limmed 0x8888,0x8888,gr22 + set_mem_limmed 0x9999,0x9999,gr21 + set_gr_limmed 0xeeee,0xeeee,gr8 + set_gr_limmed 0xffff,0xffff,gr9 + set_fr_iimmed 0x1111,0x1111,fr40 + set_fr_iimmed 0x1111,0x1111,fr41 + set_gr_immed -8,gr7 + rstd gr8,@(sp,gr7) + test_mem_limmed 0x2222,0x2222,gr20 + test_mem_limmed 0x3333,0x3333,gr27 + test_mem_limmed 0x4444,0x4444,gr26 + test_mem_limmed 0x5555,0x5555,gr25 + test_mem_limmed 0x6666,0x6666,gr24 + test_mem_limmed 0x7777,0x7777,gr23 + test_mem_limmed 0xffff,0xffff,gr22 + test_mem_limmed 0xeeee,0xeeee,gr21 + test_fr_limmed 0xffff,0xffff,fr41 + test_fr_limmed 0xeeee,0xeeee,fr40 + + pass diff --git a/sim/testsuite/sim/frv/rstdf.cgs b/sim/testsuite/sim/frv/rstdf.cgs new file mode 100644 index 0000000..9d0d841 --- /dev/null +++ b/sim/testsuite/sim/frv/rstdf.cgs @@ -0,0 +1,186 @@ +# frv testcase for rstdf $FRk,@($GRi,$GRj) +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global add +add: + ; No nesr's active + set_gr_gr sp,gr20 + set_mem_limmed 0x2222,0x2222,gr20 + set_gr_gr gr20,gr27 + inc_gr_immed -4,gr27 + set_mem_limmed 0x3333,0x3333,gr27 + set_gr_gr gr27,gr26 + inc_gr_immed -4,gr26 + set_mem_limmed 0x4444,0x4444,gr26 + set_gr_gr gr26,gr25 + inc_gr_immed -4,gr25 + set_mem_limmed 0x5555,0x5555,gr25 + set_gr_gr gr25,gr24 + inc_gr_immed -4,gr24 + set_mem_limmed 0x6666,0x6666,gr24 + set_gr_gr gr24,gr23 + inc_gr_immed -4,gr23 + set_mem_limmed 0x7777,0x7777,gr23 + set_gr_gr gr23,gr22 + inc_gr_immed -4,gr22 + set_mem_limmed 0x8888,0x8888,gr22 + set_gr_gr gr22,gr21 + inc_gr_immed -4,gr21 + set_mem_limmed 0x9999,0x9999,gr21 + set_gr_limmed 0x1111,0x1111,gr40 + set_gr_limmed 0x1111,0x1111,gr41 + set_fr_iimmed 0x1111,0x1111,fr40 + set_fr_iimmed 0x1111,0x1111,fr41 + inc_gr_immed -4,sp + set_gr_immed 0,gr7 + set_fr_iimmed 0xeeee,0xeeee,fr8 + set_fr_iimmed 0xffff,0xffff,fr9 + rstdf fr8,@(sp,gr7) + test_mem_limmed 0xffff,0xffff,gr20 + test_mem_limmed 0xeeee,0xeeee,gr27 + test_mem_limmed 0x4444,0x4444,gr26 + test_mem_limmed 0x5555,0x5555,gr25 + test_mem_limmed 0x6666,0x6666,gr24 + test_mem_limmed 0x7777,0x7777,gr23 + test_mem_limmed 0x8888,0x8888,gr22 + test_mem_limmed 0x9999,0x9999,gr21 + test_gr_limmed 0x1111,0x1111,gr40 + test_gr_limmed 0x1111,0x1111,gr41 + test_fr_limmed 0x1111,0x1111,fr40 + test_fr_limmed 0x1111,0x1111,fr41 + + ; 1 nesr active with the incorrect address in neear for gr + set_gr_gr sp,gr10 + inc_gr_immed -16,gr10 + nlddi @(sp,-16),gr40 + test_spr_gr neear0,gr10 + set_mem_limmed 0x2222,0x2222,gr20 + set_mem_limmed 0x3333,0x3333,gr27 + set_mem_limmed 0x4444,0x4444,gr26 + set_mem_limmed 0x5555,0x5555,gr25 + set_mem_limmed 0x6666,0x6666,gr24 + set_mem_limmed 0x7777,0x7777,gr23 + set_mem_limmed 0x8888,0x8888,gr22 + set_mem_limmed 0x9999,0x9999,gr21 + set_fr_iimmed 0xeeee,0xeeee,fr8 + set_fr_iimmed 0xffff,0xffff,fr9 + set_gr_limmed 0x1111,0x1111,gr40 + set_gr_limmed 0x1111,0x1111,gr41 + set_fr_iimmed 0x1111,0x1111,fr40 + set_fr_iimmed 0x1111,0x1111,fr41 + set_gr_immed -8,gr7 + rstdf fr8,@(sp,gr7) + test_mem_limmed 0x2222,0x2222,gr20 + test_mem_limmed 0x3333,0x3333,gr27 + test_mem_limmed 0xffff,0xffff,gr26 + test_mem_limmed 0xeeee,0xeeee,gr25 + test_mem_limmed 0x6666,0x6666,gr24 + test_mem_limmed 0x7777,0x7777,gr23 + test_mem_limmed 0x8888,0x8888,gr22 + test_mem_limmed 0x9999,0x9999,gr21 + test_gr_limmed 0x1111,0x1111,gr40 + test_gr_limmed 0x1111,0x1111,gr41 + test_fr_limmed 0x1111,0x1111,fr40 + test_fr_limmed 0x1111,0x1111,fr41 + + ; 1 nesr active with the incorrect address in neear for fr + inc_gr_immed -8,gr10 + nlddfi @(sp,-24),fr40 + test_spr_gr neear1,gr10 + set_mem_limmed 0x2222,0x2222,gr20 + set_mem_limmed 0x3333,0x3333,gr27 + set_mem_limmed 0x4444,0x4444,gr26 + set_mem_limmed 0x5555,0x5555,gr25 + set_mem_limmed 0x6666,0x6666,gr24 + set_mem_limmed 0x7777,0x7777,gr23 + set_mem_limmed 0x8888,0x8888,gr22 + set_mem_limmed 0x9999,0x9999,gr21 + set_fr_iimmed 0xeeee,0xeeee,fr8 + set_fr_iimmed 0xffff,0xffff,fr9 + set_gr_limmed 0x1111,0x1111,gr40 + set_gr_limmed 0x1111,0x1111,gr41 + set_fr_iimmed 0x1111,0x1111,fr40 + set_fr_iimmed 0x1111,0x1111,fr41 + inc_gr_immed -8,sp + set_gr_immed 8,gr7 + rstdf fr8,@(sp,gr7) + test_mem_limmed 0xffff,0xffff,gr20 + test_mem_limmed 0xeeee,0xeeee,gr27 + test_mem_limmed 0x4444,0x4444,gr26 + test_mem_limmed 0x5555,0x5555,gr25 + test_mem_limmed 0x6666,0x6666,gr24 + test_mem_limmed 0x7777,0x7777,gr23 + test_mem_limmed 0x8888,0x8888,gr22 + test_mem_limmed 0x9999,0x9999,gr21 + test_gr_limmed 0x1111,0x1111,gr40 + test_gr_limmed 0x1111,0x1111,gr41 + test_fr_limmed 0x1111,0x1111,fr40 + test_fr_limmed 0x1111,0x1111,fr41 + + ; 1 nesr active with the correct address in neear for gr + set_mem_limmed 0x2222,0x2222,gr20 + set_mem_limmed 0x3333,0x3333,gr27 + set_mem_limmed 0x4444,0x4444,gr26 + set_mem_limmed 0x5555,0x5555,gr25 + set_mem_limmed 0x6666,0x6666,gr24 + set_mem_limmed 0x7777,0x7777,gr23 + set_mem_limmed 0x8888,0x8888,gr22 + set_mem_limmed 0x9999,0x9999,gr21 + set_fr_iimmed 0xeeee,0xeeee,fr8 + set_fr_iimmed 0xffff,0xffff,fr9 + set_gr_limmed 0x1111,0x1111,gr40 + set_gr_limmed 0x1111,0x1111,gr41 + set_fr_iimmed 0x1111,0x1111,fr40 + set_fr_iimmed 0x1111,0x1111,fr41 + inc_gr_immed -8,sp + set_gr_immed 0,gr7 + rstdf fr8,@(sp,gr7) + test_mem_limmed 0x2222,0x2222,gr20 + test_mem_limmed 0x3333,0x3333,gr27 + test_mem_limmed 0x4444,0x4444,gr26 + test_mem_limmed 0x5555,0x5555,gr25 + test_mem_limmed 0xffff,0xffff,gr24 + test_mem_limmed 0xeeee,0xeeee,gr23 + test_mem_limmed 0x8888,0x8888,gr22 + test_mem_limmed 0x9999,0x9999,gr21 + test_gr_limmed 0xffff,0xffff,gr41 + test_gr_limmed 0xeeee,0xeeee,gr40 + test_fr_limmed 0x1111,0x1111,fr41 + test_fr_limmed 0x1111,0x1111,fr40 + + ; 1 nesr active with the correct address in neear for fr + set_mem_limmed 0x2222,0x2222,gr20 + set_mem_limmed 0x3333,0x3333,gr27 + set_mem_limmed 0x4444,0x4444,gr26 + set_mem_limmed 0x5555,0x5555,gr25 + set_mem_limmed 0x6666,0x6666,gr24 + set_mem_limmed 0x7777,0x7777,gr23 + set_mem_limmed 0x8888,0x8888,gr22 + set_mem_limmed 0x9999,0x9999,gr21 + set_fr_iimmed 0xeeee,0xeeee,fr8 + set_fr_iimmed 0xffff,0xffff,fr9 + set_gr_limmed 0x1111,0x1111,gr40 + set_gr_limmed 0x1111,0x1111,gr41 + set_fr_iimmed 0x1111,0x1111,fr40 + set_fr_iimmed 0x1111,0x1111,fr41 + set_gr_immed -8,gr7 + rstdf fr8,@(sp,gr7) + test_mem_limmed 0x2222,0x2222,gr20 + test_mem_limmed 0x3333,0x3333,gr27 + test_mem_limmed 0x4444,0x4444,gr26 + test_mem_limmed 0x5555,0x5555,gr25 + test_mem_limmed 0x6666,0x6666,gr24 + test_mem_limmed 0x7777,0x7777,gr23 + test_mem_limmed 0xffff,0xffff,gr22 + test_mem_limmed 0xeeee,0xeeee,gr21 + test_gr_limmed 0x1111,0x1111,gr41 + test_gr_limmed 0x1111,0x1111,gr40 + test_fr_limmed 0xffff,0xffff,fr41 + test_fr_limmed 0xeeee,0xeeee,fr40 + + pass diff --git a/sim/testsuite/sim/frv/rstf.cgs b/sim/testsuite/sim/frv/rstf.cgs new file mode 100644 index 0000000..17a123a --- /dev/null +++ b/sim/testsuite/sim/frv/rstf.cgs @@ -0,0 +1,112 @@ +# frv testcase for rstf $FRk,@($GRi,$GRj) +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global add +add: + ; No nesr's active + set_gr_gr sp,gr10 + set_gr_gr sp,gr24 + set_mem_limmed 0x2222,0x2222,gr24 + set_gr_gr gr24,gr27 + inc_gr_immed -4,gr27 + set_mem_limmed 0x3333,0x3333,gr27 + set_gr_gr gr27,gr26 + inc_gr_immed -4,gr26 + set_mem_limmed 0x4444,0x4444,gr26 + set_gr_gr gr26,gr25 + inc_gr_immed -4,gr25 + set_mem_limmed 0x5555,0x5555,gr25 + set_gr_limmed 0x1111,0x1111,gr20 + set_fr_iimmed 0x1111,0x1111,fr20 + set_gr_immed 0,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + rstf fr8,@(sp,gr7) + test_mem_limmed 0xffff,0xffff,gr24 + test_mem_limmed 0x3333,0x3333,gr27 + test_mem_limmed 0x4444,0x4444,gr26 + test_mem_limmed 0x5555,0x5555,gr25 + test_gr_limmed 0x1111,0x1111,gr20 + test_fr_limmed 0x1111,0x1111,fr20 + + ; 1 nesr active with the incorrect address in neear for gr + inc_gr_immed -8,gr10 + nldi @(sp,-8),gr20 + test_spr_gr neear0,gr10 + set_mem_limmed 0x2222,0x2222,gr24 + set_mem_limmed 0x3333,0x3333,gr27 + set_mem_limmed 0x4444,0x4444,gr26 + set_mem_limmed 0x5555,0x5555,gr25 + set_gr_limmed 0x1111,0x1111,gr20 + set_fr_iimmed 0x1111,0x1111,fr20 + set_fr_iimmed 0xffff,0xffff,fr8 + set_gr_immed -4,gr7 + rstf fr8,@(sp,gr7) + test_mem_limmed 0x2222,0x2222,gr24 + test_mem_limmed 0xffff,0xffff,gr27 + test_mem_limmed 0x4444,0x4444,gr26 + test_mem_limmed 0x5555,0x5555,gr25 + test_gr_limmed 0x1111,0x1111,gr20 + test_fr_limmed 0x1111,0x1111,fr20 + + ; 1 nesr active with the incorrect address in neear for fr + inc_gr_immed -4,gr10 + nldfi @(sp,-12),fr20 + test_spr_gr neear1,gr10 + set_mem_limmed 0x2222,0x2222,gr24 + set_mem_limmed 0x3333,0x3333,gr27 + set_mem_limmed 0x4444,0x4444,gr26 + set_mem_limmed 0x5555,0x5555,gr25 + set_gr_limmed 0x1111,0x1111,gr20 + set_fr_iimmed 0x1111,0x1111,fr20 + set_fr_iimmed 0xffff,0xffff,fr8 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + rstf fr8,@(sp,gr7) + test_mem_limmed 0xffff,0xffff,gr24 + test_mem_limmed 0x3333,0x3333,gr27 + test_mem_limmed 0x4444,0x4444,gr26 + test_mem_limmed 0x5555,0x5555,gr25 + test_gr_limmed 0x1111,0x1111,gr20 + test_fr_limmed 0x1111,0x1111,fr20 + + ; 1 nesr active with the correct address in neear for gr + set_mem_limmed 0x2222,0x2222,gr24 + set_mem_limmed 0x3333,0x3333,gr27 + set_mem_limmed 0x4444,0x4444,gr26 + set_mem_limmed 0x5555,0x5555,gr25 + set_gr_limmed 0x1111,0x1111,gr20 + set_fr_iimmed 0x1111,0x1111,fr20 + set_fr_iimmed 0xffff,0xffff,fr8 + inc_gr_immed -4,sp + set_gr_immed 0,gr7 + rstf fr8,@(sp,gr7) + test_mem_limmed 0x2222,0x2222,gr24 + test_mem_limmed 0x3333,0x3333,gr27 + test_mem_limmed 0xffff,0xffff,gr26 + test_mem_limmed 0x5555,0x5555,gr25 + test_gr_limmed 0xffff,0xffff,gr20 + test_fr_limmed 0x1111,0x1111,fr20 + + ; 1 nesr active with the correct address in neear for fr + set_mem_limmed 0x2222,0x2222,gr24 + set_mem_limmed 0x3333,0x3333,gr27 + set_mem_limmed 0x4444,0x4444,gr26 + set_mem_limmed 0x5555,0x5555,gr25 + set_gr_limmed 0x1111,0x1111,gr20 + set_fr_iimmed 0x1111,0x1111,fr20 + set_fr_iimmed 0xffff,0xffff,fr8 + set_gr_immed -4,gr7 + rstf fr8,@(sp,gr7) + test_mem_limmed 0x2222,0x2222,gr24 + test_mem_limmed 0x3333,0x3333,gr27 + test_mem_limmed 0x4444,0x4444,gr26 + test_mem_limmed 0xffff,0xffff,gr25 + test_gr_limmed 0x1111,0x1111,gr20 + test_fr_limmed 0xffff,0xffff,fr20 + + pass diff --git a/sim/testsuite/sim/frv/rsth.cgs b/sim/testsuite/sim/frv/rsth.cgs new file mode 100644 index 0000000..a2b283e --- /dev/null +++ b/sim/testsuite/sim/frv/rsth.cgs @@ -0,0 +1,83 @@ +# frv testcase for rsth $GRk,@($GRi,$GRj) +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global add +add: + ; No nesr's active + set_gr_gr sp,gr22 + set_mem_limmed 0x2222,0x2222,gr22 + set_gr_gr gr22,gr21 + inc_gr_immed -4,gr21 + set_mem_limmed 0x3333,0x3333,gr21 + set_gr_gr gr22,gr23 + set_gr_limmed 0x1111,0x1111,gr20 + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + rsth gr8,@(sp,gr7) + test_mem_limmed 0xffff,0x2222,gr22 + test_mem_limmed 0x3333,0x3333,gr21 + test_gr_limmed 0x1111,0x1111,gr20 + + ; 1 nesr active with the incorrect address in neear for gr + nlduhi @(sp,0),gr20 + test_spr_gr neear0,gr23 + set_mem_limmed 0x2222,0x2222,gr22 + set_mem_limmed 0x3333,0x3333,gr21 + set_gr_limmed 0x1111,0x1111,gr20 + set_gr_limmed 0xffff,0xffff,gr8 + set_gr_immed 2,gr7 + rsth gr8,@(sp,gr7) + test_mem_limmed 0x2222,0xffff,gr22 + test_mem_limmed 0x3333,0x3333,gr21 + test_gr_limmed 0x1111,0x1111,gr20 + + ; 1 nesr active with the incorrect address in neear for fr + inc_gr_immed 2,gr23 + nldhfi @(sp,2),fr20 + test_spr_gr neear1,gr23 + set_mem_limmed 0x2222,0x2222,gr22 + set_mem_limmed 0x3333,0x3333,gr21 + set_fr_iimmed 0x1111,0x1111,fr20 + set_gr_limmed 0xffff,0xffff,gr8 + inc_gr_immed 4,sp + set_gr_immed -4,gr7 + rsth gr8,@(sp,gr7) + test_mem_limmed 0xffff,0x2222,gr22 + test_mem_limmed 0x3333,0x3333,gr21 + test_fr_limmed 0x1111,0x1111,fr20 + + ; 1 nesr active with the correct address in neear for gr + inc_gr_immed -4,gr23 + nlduhi @(sp,-6),gr20 + test_spr_gr neear2,gr23 + set_mem_limmed 0x2222,0x2222,gr22 + set_mem_limmed 0x3333,0x3333,gr21 + set_gr_limmed 0x1111,0x1111,gr20 + set_gr_limmed 0xffff,0xffff,gr8 + inc_gr_immed -4,sp + set_gr_immed -2,gr7 + rsth gr8,@(sp,gr7) + test_mem_limmed 0x2222,0x2222,gr22 + test_mem_limmed 0x3333,0xffff,gr21 + test_gr_limmed 0x0000,0xffff,gr20 + + ; 1 nesr active with the correct address in neear for fr + inc_gr_immed -2,gr23 + nldhfi @(sp,-4),fr20 + test_spr_gr neear3,gr23 + set_mem_limmed 0x2222,0x2222,gr22 + set_mem_limmed 0x3333,0x3333,gr21 + set_fr_iimmed 0x1111,0x1111,fr20 + set_gr_limmed 0xffff,0xffff,gr8 + set_gr_immed -4,gr7 + rsth gr8,@(sp,gr7) + test_mem_limmed 0x2222,0x2222,gr22 + test_mem_limmed 0xffff,0x3333,gr21 + test_fr_limmed 0x0000,0xffff,fr20 + + pass diff --git a/sim/testsuite/sim/frv/rsthf.cgs b/sim/testsuite/sim/frv/rsthf.cgs new file mode 100644 index 0000000..06adb97 --- /dev/null +++ b/sim/testsuite/sim/frv/rsthf.cgs @@ -0,0 +1,87 @@ +# frv testcase for rsthf $FRk,@($GRi,$GRj) +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global add +add: + ; No nesr's active + set_gr_gr sp,gr22 + set_mem_limmed 0x2222,0x2222,gr22 + set_gr_gr gr22,gr21 + inc_gr_immed -4,gr21 + set_mem_limmed 0x3333,0x3333,gr21 + set_gr_gr gr22,gr23 + set_gr_limmed 0x1111,0x1111,gr20 + set_fr_iimmed 0x1111,0x1111,fr20 + set_gr_immed 0,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + rsthf fr8,@(sp,gr7) + test_mem_limmed 0xffff,0x2222,gr22 + test_mem_limmed 0x3333,0x3333,gr21 + test_gr_limmed 0x1111,0x1111,gr20 + test_fr_limmed 0x1111,0x1111,fr20 + + ; 1 nesr active with the incorrect address in neear for gr + inc_gr_immed -2,gr23 + nlduhi @(sp,-2),gr20 + test_spr_gr neear0,gr23 + set_mem_limmed 0x2222,0x2222,gr22 + set_mem_limmed 0x3333,0x3333,gr21 + set_gr_limmed 0x1111,0x1111,gr20 + set_fr_iimmed 0xffff,0xffff,fr8 + set_gr_immed 2,gr7 + rsthf fr8,@(sp,gr7) + test_mem_limmed 0x2222,0xffff,gr22 + test_mem_limmed 0x3333,0x3333,gr21 + test_gr_limmed 0x1111,0x1111,gr20 + test_fr_limmed 0x1111,0x1111,fr20 + + ; 1 nesr active with the incorrect address in neear for fr + inc_gr_immed -2,gr23 + nldhfi @(sp,-4),fr20 + test_spr_gr neear1,gr23 + set_mem_limmed 0x2222,0x2222,gr22 + set_mem_limmed 0x3333,0x3333,gr21 + set_gr_limmed 0x1111,0x1111,gr20 + set_fr_iimmed 0x1111,0x1111,fr20 + set_fr_iimmed 0xffff,0xffff,fr8 + inc_gr_immed 4,sp + set_gr_immed -4,gr7 + rsthf fr8,@(sp,gr7) + test_mem_limmed 0xffff,0x2222,gr22 + test_mem_limmed 0x3333,0x3333,gr21 + test_gr_limmed 0x1111,0x1111,gr20 + test_fr_limmed 0x1111,0x1111,fr20 + + ; 1 nesr active with the correct address in neear for gr + set_mem_limmed 0x2222,0x2222,gr22 + set_mem_limmed 0x3333,0x3333,gr21 + set_gr_limmed 0x1111,0x1111,gr20 + set_fr_iimmed 0x1111,0x1111,fr20 + set_fr_iimmed 0xffff,0xffff,fr8 + inc_gr_immed -4,sp + set_gr_immed -2,gr7 + rsthf fr8,@(sp,gr7) + test_mem_limmed 0x2222,0x2222,gr22 + test_mem_limmed 0x3333,0xffff,gr21 + test_gr_limmed 0x0000,0xffff,gr20 + test_fr_limmed 0x1111,0x1111,fr20 + + ; 1 nesr active with the correct address in neear for fr + set_mem_limmed 0x2222,0x2222,gr22 + set_mem_limmed 0x3333,0x3333,gr21 + set_gr_limmed 0x1111,0x1111,gr20 + set_fr_iimmed 0x1111,0x1111,fr20 + set_fr_iimmed 0xffff,0xffff,fr8 + set_gr_immed -4,gr7 + rsthf fr8,@(sp,gr7) + test_mem_limmed 0x2222,0x2222,gr22 + test_mem_limmed 0xffff,0x3333,gr21 + test_gr_limmed 0x1111,0x1111,gr20 + test_fr_limmed 0x0000,0xffff,fr20 + + pass diff --git a/sim/testsuite/sim/frv/rstq.cgs b/sim/testsuite/sim/frv/rstq.cgs new file mode 100644 index 0000000..190c954 --- /dev/null +++ b/sim/testsuite/sim/frv/rstq.cgs @@ -0,0 +1,297 @@ +# frv testcase for rstq $GRk,@($GRi,$GRj) +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global add +add: + ; No nesr's active + set_gr_gr sp,gr6 + set_mem_limmed 0x2222,0x2222,gr6 + set_gr_gr gr6,gr27 + inc_gr_immed -4,gr27 + set_mem_limmed 0x3333,0x3333,gr27 + set_gr_gr gr27,gr26 + inc_gr_immed -4,gr26 + set_mem_limmed 0x4444,0x4444,gr26 + set_gr_gr gr26,gr25 + inc_gr_immed -4,gr25 + set_mem_limmed 0x5555,0x5555,gr25 + set_gr_gr gr25,gr24 + inc_gr_immed -4,gr24 + set_mem_limmed 0x6666,0x6666,gr24 + set_gr_gr gr24,gr23 + inc_gr_immed -4,gr23 + set_mem_limmed 0x7777,0x7777,gr23 + set_gr_gr gr23,gr22 + inc_gr_immed -4,gr22 + set_mem_limmed 0x8888,0x8888,gr22 + set_gr_gr gr22,gr21 + inc_gr_immed -4,gr21 + set_mem_limmed 0x9999,0x9999,gr21 + set_gr_gr gr21,gr20 + inc_gr_immed -4,gr20 + set_mem_limmed 0xaaaa,0xaaaa,gr20 + set_gr_gr gr20,gr19 + inc_gr_immed -4,gr19 + set_mem_limmed 0xbbbb,0xbbbb,gr19 + set_gr_gr gr19,gr18 + inc_gr_immed -4,gr18 + set_mem_limmed 0xcccc,0xcccc,gr18 + set_gr_gr gr18,gr17 + inc_gr_immed -4,gr17 + set_mem_limmed 0xdddd,0xdddd,gr17 + set_gr_gr gr17,gr16 + inc_gr_immed -4,gr16 + set_mem_limmed 0xeeee,0xeeee,gr16 + set_gr_gr gr16,gr15 + inc_gr_immed -4,gr15 + set_mem_limmed 0xf0f0,0xf0f0,gr15 + set_gr_gr gr15,gr14 + inc_gr_immed -4,gr14 + set_mem_limmed 0xf1f1,0xf1f1,gr14 + set_gr_gr gr14,gr13 + inc_gr_immed -4,gr13 + set_mem_limmed 0xf2f2,0xf2f2,gr13 + set_gr_limmed 0x1111,0x1111,gr40 + set_gr_limmed 0x1111,0x1111,gr41 + set_gr_limmed 0x1111,0x1111,gr42 + set_gr_limmed 0x1111,0x1111,gr43 + inc_gr_immed -12,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xeeee,0xeeee,gr8 + set_gr_limmed 0xffff,0xffff,gr9 + set_gr_limmed 0xcccc,0xcccc,gr10 + set_gr_limmed 0xdddd,0xdddd,gr11 + rstq gr8,@(sp,gr7) + test_mem_limmed 0xdddd,0xdddd,gr6 + test_mem_limmed 0xcccc,0xcccc,gr27 + test_mem_limmed 0xffff,0xffff,gr26 + test_mem_limmed 0xeeee,0xeeee,gr25 + test_mem_limmed 0x6666,0x6666,gr24 + test_mem_limmed 0x7777,0x7777,gr23 + test_mem_limmed 0x8888,0x8888,gr22 + test_mem_limmed 0x9999,0x9999,gr21 + test_mem_limmed 0xaaaa,0xaaaa,gr20 + test_mem_limmed 0xbbbb,0xbbbb,gr19 + test_mem_limmed 0xcccc,0xcccc,gr18 + test_mem_limmed 0xdddd,0xdddd,gr17 + test_mem_limmed 0xeeee,0xeeee,gr16 + test_mem_limmed 0xf0f0,0xf0f0,gr15 + test_mem_limmed 0xf1f1,0xf1f1,gr14 + test_mem_limmed 0xf2f2,0xf2f2,gr13 + test_gr_limmed 0x1111,0x1111,gr40 + test_gr_limmed 0x1111,0x1111,gr41 + test_gr_limmed 0x1111,0x1111,gr42 + test_gr_limmed 0x1111,0x1111,gr43 + + ; 1 nesr active with the incorrect address in neear for gr + set_gr_gr sp,gr12 + nldq @(sp,gr0),gr40 + test_spr_gr neear0,gr12 + set_mem_limmed 0x2222,0x2222,gr6 + set_mem_limmed 0x3333,0x3333,gr27 + set_mem_limmed 0x4444,0x4444,gr26 + set_mem_limmed 0x5555,0x5555,gr25 + set_mem_limmed 0x6666,0x6666,gr24 + set_mem_limmed 0x7777,0x7777,gr23 + set_mem_limmed 0x8888,0x8888,gr22 + set_mem_limmed 0x9999,0x9999,gr21 + set_mem_limmed 0xaaaa,0xaaaa,gr20 + set_mem_limmed 0xbbbb,0xbbbb,gr19 + set_mem_limmed 0xcccc,0xcccc,gr18 + set_mem_limmed 0xdddd,0xdddd,gr17 + set_mem_limmed 0xeeee,0xeeee,gr16 + set_mem_limmed 0xf0f0,0xf0f0,gr15 + set_mem_limmed 0xf1f1,0xf1f1,gr14 + set_mem_limmed 0xf2f2,0xf2f2,gr13 + set_gr_limmed 0xeeee,0xeeee,gr8 + set_gr_limmed 0xffff,0xffff,gr9 + set_gr_limmed 0xcccc,0xcccc,gr10 + set_gr_limmed 0xdddd,0xdddd,gr11 + set_gr_limmed 0x1111,0x1111,gr40 + set_gr_limmed 0x1111,0x1111,gr41 + set_gr_limmed 0x1111,0x1111,gr42 + set_gr_limmed 0x1111,0x1111,gr43 + set_gr_immed -16,gr7 + rstq gr8,@(sp,gr7) + test_mem_limmed 0x2222,0x2222,gr6 + test_mem_limmed 0x3333,0x3333,gr27 + test_mem_limmed 0x4444,0x4444,gr26 + test_mem_limmed 0x5555,0x5555,gr25 + test_mem_limmed 0xdddd,0xdddd,gr24 + test_mem_limmed 0xcccc,0xcccc,gr23 + test_mem_limmed 0xffff,0xffff,gr22 + test_mem_limmed 0xeeee,0xeeee,gr21 + test_mem_limmed 0xaaaa,0xaaaa,gr20 + test_mem_limmed 0xbbbb,0xbbbb,gr19 + test_mem_limmed 0xcccc,0xcccc,gr18 + test_mem_limmed 0xdddd,0xdddd,gr17 + test_mem_limmed 0xeeee,0xeeee,gr16 + test_mem_limmed 0xf0f0,0xf0f0,gr15 + test_mem_limmed 0xf1f1,0xf1f1,gr14 + test_mem_limmed 0xf2f2,0xf2f2,gr13 + test_gr_limmed 0x1111,0x1111,gr40 + test_gr_limmed 0x1111,0x1111,gr41 + test_gr_limmed 0x1111,0x1111,gr42 + test_gr_limmed 0x1111,0x1111,gr43 + + ; 1 nesr active with the incorrect address in neear for fr + inc_gr_immed -16,gr12 + nlddfi @(sp,-16),fr40 + test_spr_gr neear1,gr12 + set_mem_limmed 0x2222,0x2222,gr6 + set_mem_limmed 0x3333,0x3333,gr27 + set_mem_limmed 0x4444,0x4444,gr26 + set_mem_limmed 0x5555,0x5555,gr25 + set_mem_limmed 0x6666,0x6666,gr24 + set_mem_limmed 0x7777,0x7777,gr23 + set_mem_limmed 0x8888,0x8888,gr22 + set_mem_limmed 0x9999,0x9999,gr21 + set_mem_limmed 0xaaaa,0xaaaa,gr20 + set_mem_limmed 0xbbbb,0xbbbb,gr19 + set_mem_limmed 0xcccc,0xcccc,gr18 + set_mem_limmed 0xdddd,0xdddd,gr17 + set_mem_limmed 0xeeee,0xeeee,gr16 + set_mem_limmed 0xf0f0,0xf0f0,gr15 + set_mem_limmed 0xf1f1,0xf1f1,gr14 + set_mem_limmed 0xf2f2,0xf2f2,gr13 + set_gr_limmed 0xeeee,0xeeee,gr8 + set_gr_limmed 0xffff,0xffff,gr9 + set_gr_limmed 0xcccc,0xcccc,gr10 + set_gr_limmed 0xdddd,0xdddd,gr11 + set_fr_iimmed 0x1111,0x1111,fr40 + set_fr_iimmed 0x1111,0x1111,fr41 + set_fr_iimmed 0x1111,0x1111,fr42 + set_fr_iimmed 0x1111,0x1111,fr43 + inc_gr_immed -16,sp + set_gr_immed 16,gr7 + rstq gr8,@(sp,gr7) + test_mem_limmed 0xdddd,0xdddd,gr6 + test_mem_limmed 0xcccc,0xcccc,gr27 + test_mem_limmed 0xffff,0xffff,gr26 + test_mem_limmed 0xeeee,0xeeee,gr25 + test_mem_limmed 0x6666,0x6666,gr24 + test_mem_limmed 0x7777,0x7777,gr23 + test_mem_limmed 0x8888,0x8888,gr22 + test_mem_limmed 0x9999,0x9999,gr21 + test_mem_limmed 0xaaaa,0xaaaa,gr20 + test_mem_limmed 0xbbbb,0xbbbb,gr19 + test_mem_limmed 0xcccc,0xcccc,gr18 + test_mem_limmed 0xdddd,0xdddd,gr17 + test_mem_limmed 0xeeee,0xeeee,gr16 + test_mem_limmed 0xf0f0,0xf0f0,gr15 + test_mem_limmed 0xf1f1,0xf1f1,gr14 + test_mem_limmed 0xf2f2,0xf2f2,gr13 + test_fr_limmed 0x1111,0x1111,fr40 + test_fr_limmed 0x1111,0x1111,fr41 + test_fr_limmed 0x1111,0x1111,fr42 + test_fr_limmed 0x1111,0x1111,fr43 + + ; 1 nesr active with the correct address in neear for gr + inc_gr_immed -16,gr12 + nlddi @(sp,-16),gr40 + test_spr_gr neear2,gr12 + set_mem_limmed 0x2222,0x2222,gr6 + set_mem_limmed 0x3333,0x3333,gr27 + set_mem_limmed 0x4444,0x4444,gr26 + set_mem_limmed 0x5555,0x5555,gr25 + set_mem_limmed 0x6666,0x6666,gr24 + set_mem_limmed 0x7777,0x7777,gr23 + set_mem_limmed 0x8888,0x8888,gr22 + set_mem_limmed 0x9999,0x9999,gr21 + set_mem_limmed 0xaaaa,0xaaaa,gr20 + set_mem_limmed 0xbbbb,0xbbbb,gr19 + set_mem_limmed 0xcccc,0xcccc,gr18 + set_mem_limmed 0xdddd,0xdddd,gr17 + set_mem_limmed 0xeeee,0xeeee,gr16 + set_mem_limmed 0xf0f0,0xf0f0,gr15 + set_mem_limmed 0xf1f1,0xf1f1,gr14 + set_mem_limmed 0xf2f2,0xf2f2,gr13 + set_gr_limmed 0xeeee,0xeeee,gr8 + set_gr_limmed 0xffff,0xffff,gr9 + set_gr_limmed 0xcccc,0xcccc,gr10 + set_gr_limmed 0xdddd,0xdddd,gr11 + set_gr_limmed 0x1111,0x1111,gr40 + set_gr_limmed 0x1111,0x1111,gr41 + set_gr_limmed 0x1111,0x1111,gr42 + set_gr_limmed 0x1111,0x1111,gr43 + inc_gr_immed -16,sp + set_gr_immed 0,gr7 + rstq gr8,@(sp,gr7) + test_mem_limmed 0x2222,0x2222,gr6 + test_mem_limmed 0x3333,0x3333,gr27 + test_mem_limmed 0x4444,0x4444,gr26 + test_mem_limmed 0x5555,0x5555,gr25 + test_mem_limmed 0x6666,0x6666,gr24 + test_mem_limmed 0x7777,0x7777,gr23 + test_mem_limmed 0x8888,0x8888,gr22 + test_mem_limmed 0x9999,0x9999,gr21 + test_mem_limmed 0xdddd,0xdddd,gr20 + test_mem_limmed 0xcccc,0xcccc,gr19 + test_mem_limmed 0xffff,0xffff,gr18 + test_mem_limmed 0xeeee,0xeeee,gr17 + test_mem_limmed 0xeeee,0xeeee,gr16 + test_mem_limmed 0xf0f0,0xf0f0,gr15 + test_mem_limmed 0xf1f1,0xf1f1,gr14 + test_mem_limmed 0xf2f2,0xf2f2,gr13 + test_gr_limmed 0xeeee,0xeeee,gr40 + test_gr_limmed 0xffff,0xffff,gr41 + test_gr_limmed 0xcccc,0xcccc,gr42 + test_gr_limmed 0xdddd,0xdddd,gr43 + + ; 1 nesr active with the correct address in neear for fr + inc_gr_immed -16,gr12 + nlddfi @(sp,-16),fr40 + test_spr_gr neear3,gr12 + set_mem_limmed 0x2222,0x2222,gr6 + set_mem_limmed 0x3333,0x3333,gr27 + set_mem_limmed 0x4444,0x4444,gr26 + set_mem_limmed 0x5555,0x5555,gr25 + set_mem_limmed 0x6666,0x6666,gr24 + set_mem_limmed 0x7777,0x7777,gr23 + set_mem_limmed 0x8888,0x8888,gr22 + set_mem_limmed 0x9999,0x9999,gr21 + set_mem_limmed 0xaaaa,0xaaaa,gr20 + set_mem_limmed 0xbbbb,0xbbbb,gr19 + set_mem_limmed 0xcccc,0xcccc,gr18 + set_mem_limmed 0xdddd,0xdddd,gr17 + set_mem_limmed 0xeeee,0xeeee,gr16 + set_mem_limmed 0xf0f0,0xf0f0,gr15 + set_mem_limmed 0xf1f1,0xf1f1,gr14 + set_mem_limmed 0xf2f2,0xf2f2,gr13 + set_gr_limmed 0xeeee,0xeeee,gr8 + set_gr_limmed 0xffff,0xffff,gr9 + set_gr_limmed 0xcccc,0xcccc,gr10 + set_gr_limmed 0xdddd,0xdddd,gr11 + set_fr_iimmed 0x1111,0x1111,fr40 + set_fr_iimmed 0x1111,0x1111,fr41 + set_fr_iimmed 0x1111,0x1111,fr42 + set_fr_iimmed 0x1111,0x1111,fr43 + set_gr_immed -16,gr7 + rstq gr8,@(sp,gr7) + test_mem_limmed 0x2222,0x2222,gr6 + test_mem_limmed 0x3333,0x3333,gr27 + test_mem_limmed 0x4444,0x4444,gr26 + test_mem_limmed 0x5555,0x5555,gr25 + test_mem_limmed 0x6666,0x6666,gr24 + test_mem_limmed 0x7777,0x7777,gr23 + test_mem_limmed 0x8888,0x8888,gr22 + test_mem_limmed 0x9999,0x9999,gr21 + test_mem_limmed 0xaaaa,0xaaaa,gr20 + test_mem_limmed 0xbbbb,0xbbbb,gr19 + test_mem_limmed 0xcccc,0xcccc,gr18 + test_mem_limmed 0xdddd,0xdddd,gr17 + test_mem_limmed 0xdddd,0xdddd,gr16 + test_mem_limmed 0xcccc,0xcccc,gr15 + test_mem_limmed 0xffff,0xffff,gr14 + test_mem_limmed 0xeeee,0xeeee,gr13 + test_fr_limmed 0xeeee,0xeeee,fr40 + test_fr_limmed 0xffff,0xffff,fr41 + test_fr_limmed 0xcccc,0xcccc,fr42 + test_fr_limmed 0xdddd,0xdddd,fr43 + + pass diff --git a/sim/testsuite/sim/frv/rstqf.cgs b/sim/testsuite/sim/frv/rstqf.cgs new file mode 100644 index 0000000..72fd04a --- /dev/null +++ b/sim/testsuite/sim/frv/rstqf.cgs @@ -0,0 +1,333 @@ +# frv testcase for rstqf $FRk,@($GRi,$GRj) +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global add +add: + ; No nesr's active + set_gr_gr sp,gr12 + set_mem_limmed 0x2222,0x2222,gr12 + set_gr_gr gr12,gr27 + inc_gr_immed -4,gr27 + set_mem_limmed 0x3333,0x3333,gr27 + set_gr_gr gr27,gr26 + inc_gr_immed -4,gr26 + set_mem_limmed 0x4444,0x4444,gr26 + set_gr_gr gr26,gr25 + inc_gr_immed -4,gr25 + set_mem_limmed 0x5555,0x5555,gr25 + set_gr_gr gr25,gr24 + inc_gr_immed -4,gr24 + set_mem_limmed 0x6666,0x6666,gr24 + set_gr_gr gr24,gr23 + inc_gr_immed -4,gr23 + set_mem_limmed 0x7777,0x7777,gr23 + set_gr_gr gr23,gr22 + inc_gr_immed -4,gr22 + set_mem_limmed 0x8888,0x8888,gr22 + set_gr_gr gr22,gr21 + inc_gr_immed -4,gr21 + set_mem_limmed 0x9999,0x9999,gr21 + set_gr_gr gr21,gr20 + inc_gr_immed -4,gr20 + set_mem_limmed 0xaaaa,0xaaaa,gr20 + set_gr_gr gr20,gr19 + inc_gr_immed -4,gr19 + set_mem_limmed 0xbbbb,0xbbbb,gr19 + set_gr_gr gr19,gr18 + inc_gr_immed -4,gr18 + set_mem_limmed 0xcccc,0xcccc,gr18 + set_gr_gr gr18,gr17 + inc_gr_immed -4,gr17 + set_mem_limmed 0xdddd,0xdddd,gr17 + set_gr_gr gr17,gr16 + inc_gr_immed -4,gr16 + set_mem_limmed 0xeeee,0xeeee,gr16 + set_gr_gr gr16,gr15 + inc_gr_immed -4,gr15 + set_mem_limmed 0xf0f0,0xf0f0,gr15 + set_gr_gr gr15,gr14 + inc_gr_immed -4,gr14 + set_mem_limmed 0xf1f1,0xf1f1,gr14 + set_gr_gr gr14,gr13 + inc_gr_immed -4,gr13 + set_mem_limmed 0xf2f2,0xf2f2,gr13 + set_gr_limmed 0x1111,0x1111,gr40 + set_gr_limmed 0x1111,0x1111,gr41 + set_gr_limmed 0x1111,0x1111,gr42 + set_gr_limmed 0x1111,0x1111,gr43 + set_fr_iimmed 0x1111,0x1111,fr40 + set_fr_iimmed 0x1111,0x1111,fr41 + set_fr_iimmed 0x1111,0x1111,fr42 + set_fr_iimmed 0x1111,0x1111,fr43 + inc_gr_immed -12,sp + set_gr_immed 0,gr7 + set_fr_iimmed 0xeeee,0xeeee,fr8 + set_fr_iimmed 0xffff,0xffff,fr9 + set_fr_iimmed 0xcccc,0xcccc,fr10 + set_fr_iimmed 0xdddd,0xdddd,fr11 + rstqf fr8,@(sp,gr7) + test_mem_limmed 0xdddd,0xdddd,gr12 + test_mem_limmed 0xcccc,0xcccc,gr27 + test_mem_limmed 0xffff,0xffff,gr26 + test_mem_limmed 0xeeee,0xeeee,gr25 + test_mem_limmed 0x6666,0x6666,gr24 + test_mem_limmed 0x7777,0x7777,gr23 + test_mem_limmed 0x8888,0x8888,gr22 + test_mem_limmed 0x9999,0x9999,gr21 + test_mem_limmed 0xaaaa,0xaaaa,gr20 + test_mem_limmed 0xbbbb,0xbbbb,gr19 + test_mem_limmed 0xcccc,0xcccc,gr18 + test_mem_limmed 0xdddd,0xdddd,gr17 + test_mem_limmed 0xeeee,0xeeee,gr16 + test_mem_limmed 0xf0f0,0xf0f0,gr15 + test_mem_limmed 0xf1f1,0xf1f1,gr14 + test_mem_limmed 0xf2f2,0xf2f2,gr13 + test_gr_limmed 0x1111,0x1111,gr40 + test_gr_limmed 0x1111,0x1111,gr41 + test_gr_limmed 0x1111,0x1111,gr42 + test_gr_limmed 0x1111,0x1111,gr43 + test_fr_limmed 0x1111,0x1111,fr40 + test_fr_limmed 0x1111,0x1111,fr41 + test_fr_limmed 0x1111,0x1111,fr42 + test_fr_limmed 0x1111,0x1111,fr43 + + ; 1 nesr active with the incorrect address in neear for gr + set_gr_gr sp,gr10 + inc_gr_immed -32,gr10 + set_gr_immed -32,gr9 + nldq @(sp,gr9),gr40 + test_spr_gr neear0,gr10 + set_mem_limmed 0x2222,0x2222,gr12 + set_mem_limmed 0x3333,0x3333,gr27 + set_mem_limmed 0x4444,0x4444,gr26 + set_mem_limmed 0x5555,0x5555,gr25 + set_mem_limmed 0x6666,0x6666,gr24 + set_mem_limmed 0x7777,0x7777,gr23 + set_mem_limmed 0x8888,0x8888,gr22 + set_mem_limmed 0x9999,0x9999,gr21 + set_mem_limmed 0xaaaa,0xaaaa,gr20 + set_mem_limmed 0xbbbb,0xbbbb,gr19 + set_mem_limmed 0xcccc,0xcccc,gr18 + set_mem_limmed 0xdddd,0xdddd,gr17 + set_mem_limmed 0xeeee,0xeeee,gr16 + set_mem_limmed 0xf0f0,0xf0f0,gr15 + set_mem_limmed 0xf1f1,0xf1f1,gr14 + set_mem_limmed 0xf2f2,0xf2f2,gr13 + set_fr_iimmed 0xeeee,0xeeee,fr8 + set_fr_iimmed 0xffff,0xffff,fr9 + set_fr_iimmed 0xcccc,0xcccc,fr10 + set_fr_iimmed 0xdddd,0xdddd,fr11 + set_gr_limmed 0x1111,0x1111,gr40 + set_gr_limmed 0x1111,0x1111,gr41 + set_gr_limmed 0x1111,0x1111,gr42 + set_gr_limmed 0x1111,0x1111,gr43 + set_fr_iimmed 0x1111,0x1111,fr40 + set_fr_iimmed 0x1111,0x1111,fr41 + set_fr_iimmed 0x1111,0x1111,fr42 + set_fr_iimmed 0x1111,0x1111,fr43 + set_gr_immed -16,gr7 + rstqf fr8,@(sp,gr7) + test_mem_limmed 0x2222,0x2222,gr12 + test_mem_limmed 0x3333,0x3333,gr27 + test_mem_limmed 0x4444,0x4444,gr26 + test_mem_limmed 0x5555,0x5555,gr25 + test_mem_limmed 0xdddd,0xdddd,gr24 + test_mem_limmed 0xcccc,0xcccc,gr23 + test_mem_limmed 0xffff,0xffff,gr22 + test_mem_limmed 0xeeee,0xeeee,gr21 + test_mem_limmed 0xaaaa,0xaaaa,gr20 + test_mem_limmed 0xbbbb,0xbbbb,gr19 + test_mem_limmed 0xcccc,0xcccc,gr18 + test_mem_limmed 0xdddd,0xdddd,gr17 + test_mem_limmed 0xeeee,0xeeee,gr16 + test_mem_limmed 0xf0f0,0xf0f0,gr15 + test_mem_limmed 0xf1f1,0xf1f1,gr14 + test_mem_limmed 0xf2f2,0xf2f2,gr13 + test_gr_limmed 0x1111,0x1111,gr40 + test_gr_limmed 0x1111,0x1111,gr41 + test_gr_limmed 0x1111,0x1111,gr42 + test_gr_limmed 0x1111,0x1111,gr43 + test_fr_limmed 0x1111,0x1111,fr40 + test_fr_limmed 0x1111,0x1111,fr41 + test_fr_limmed 0x1111,0x1111,fr42 + test_fr_limmed 0x1111,0x1111,fr43 + + ; 1 nesr active with the incorrect address in neear for fr + inc_gr_immed -16,gr10 + nlddfi @(sp,-48),fr40 + test_spr_gr neear1,gr10 + set_mem_limmed 0x2222,0x2222,gr12 + set_mem_limmed 0x3333,0x3333,gr27 + set_mem_limmed 0x4444,0x4444,gr26 + set_mem_limmed 0x5555,0x5555,gr25 + set_mem_limmed 0x6666,0x6666,gr24 + set_mem_limmed 0x7777,0x7777,gr23 + set_mem_limmed 0x8888,0x8888,gr22 + set_mem_limmed 0x9999,0x9999,gr21 + set_mem_limmed 0xaaaa,0xaaaa,gr20 + set_mem_limmed 0xbbbb,0xbbbb,gr19 + set_mem_limmed 0xcccc,0xcccc,gr18 + set_mem_limmed 0xdddd,0xdddd,gr17 + set_mem_limmed 0xeeee,0xeeee,gr16 + set_mem_limmed 0xf0f0,0xf0f0,gr15 + set_mem_limmed 0xf1f1,0xf1f1,gr14 + set_mem_limmed 0xf2f2,0xf2f2,gr13 + set_fr_iimmed 0xeeee,0xeeee,fr8 + set_fr_iimmed 0xffff,0xffff,fr9 + set_fr_iimmed 0xcccc,0xcccc,fr10 + set_fr_iimmed 0xdddd,0xdddd,fr11 + set_gr_limmed 0x1111,0x1111,gr40 + set_gr_limmed 0x1111,0x1111,gr41 + set_gr_limmed 0x1111,0x1111,gr42 + set_gr_limmed 0x1111,0x1111,gr43 + set_fr_iimmed 0x1111,0x1111,fr40 + set_fr_iimmed 0x1111,0x1111,fr41 + set_fr_iimmed 0x1111,0x1111,fr42 + set_fr_iimmed 0x1111,0x1111,fr43 + inc_gr_immed -16,sp + set_gr_immed 16,gr7 + rstqf fr8,@(sp,gr7) + test_mem_limmed 0xdddd,0xdddd,gr12 + test_mem_limmed 0xcccc,0xcccc,gr27 + test_mem_limmed 0xffff,0xffff,gr26 + test_mem_limmed 0xeeee,0xeeee,gr25 + test_mem_limmed 0x6666,0x6666,gr24 + test_mem_limmed 0x7777,0x7777,gr23 + test_mem_limmed 0x8888,0x8888,gr22 + test_mem_limmed 0x9999,0x9999,gr21 + test_mem_limmed 0xaaaa,0xaaaa,gr20 + test_mem_limmed 0xbbbb,0xbbbb,gr19 + test_mem_limmed 0xcccc,0xcccc,gr18 + test_mem_limmed 0xdddd,0xdddd,gr17 + test_mem_limmed 0xeeee,0xeeee,gr16 + test_mem_limmed 0xf0f0,0xf0f0,gr15 + test_mem_limmed 0xf1f1,0xf1f1,gr14 + test_mem_limmed 0xf2f2,0xf2f2,gr13 + test_gr_limmed 0x1111,0x1111,gr40 + test_gr_limmed 0x1111,0x1111,gr41 + test_gr_limmed 0x1111,0x1111,gr42 + test_gr_limmed 0x1111,0x1111,gr43 + test_fr_limmed 0x1111,0x1111,fr40 + test_fr_limmed 0x1111,0x1111,fr41 + test_fr_limmed 0x1111,0x1111,fr42 + test_fr_limmed 0x1111,0x1111,fr43 + + ; 1 nesr active with the correct address in neear for gr + set_mem_limmed 0x2222,0x2222,gr12 + set_mem_limmed 0x3333,0x3333,gr27 + set_mem_limmed 0x4444,0x4444,gr26 + set_mem_limmed 0x5555,0x5555,gr25 + set_mem_limmed 0x6666,0x6666,gr24 + set_mem_limmed 0x7777,0x7777,gr23 + set_mem_limmed 0x8888,0x8888,gr22 + set_mem_limmed 0x9999,0x9999,gr21 + set_mem_limmed 0xaaaa,0xaaaa,gr20 + set_mem_limmed 0xbbbb,0xbbbb,gr19 + set_mem_limmed 0xcccc,0xcccc,gr18 + set_mem_limmed 0xdddd,0xdddd,gr17 + set_mem_limmed 0xeeee,0xeeee,gr16 + set_mem_limmed 0xf0f0,0xf0f0,gr15 + set_mem_limmed 0xf1f1,0xf1f1,gr14 + set_mem_limmed 0xf2f2,0xf2f2,gr13 + set_fr_iimmed 0xeeee,0xeeee,fr8 + set_fr_iimmed 0xffff,0xffff,fr9 + set_fr_iimmed 0xcccc,0xcccc,fr10 + set_fr_iimmed 0xdddd,0xdddd,fr11 + set_gr_limmed 0x1111,0x1111,gr40 + set_gr_limmed 0x1111,0x1111,gr41 + set_gr_limmed 0x1111,0x1111,gr42 + set_gr_limmed 0x1111,0x1111,gr43 + set_fr_iimmed 0x1111,0x1111,fr40 + set_fr_iimmed 0x1111,0x1111,fr41 + set_fr_iimmed 0x1111,0x1111,fr42 + set_fr_iimmed 0x1111,0x1111,fr43 + inc_gr_immed -16,sp + set_gr_immed 0,gr7 + rstqf fr8,@(sp,gr7) + test_mem_limmed 0x2222,0x2222,gr12 + test_mem_limmed 0x3333,0x3333,gr27 + test_mem_limmed 0x4444,0x4444,gr26 + test_mem_limmed 0x5555,0x5555,gr25 + test_mem_limmed 0x6666,0x6666,gr24 + test_mem_limmed 0x7777,0x7777,gr23 + test_mem_limmed 0x8888,0x8888,gr22 + test_mem_limmed 0x9999,0x9999,gr21 + test_mem_limmed 0xdddd,0xdddd,gr20 + test_mem_limmed 0xcccc,0xcccc,gr19 + test_mem_limmed 0xffff,0xffff,gr18 + test_mem_limmed 0xeeee,0xeeee,gr17 + test_mem_limmed 0xeeee,0xeeee,gr16 + test_mem_limmed 0xf0f0,0xf0f0,gr15 + test_mem_limmed 0xf1f1,0xf1f1,gr14 + test_mem_limmed 0xf2f2,0xf2f2,gr13 + test_gr_limmed 0xeeee,0xeeee,gr40 + test_gr_limmed 0xffff,0xffff,gr41 + test_gr_limmed 0xcccc,0xcccc,gr42 + test_gr_limmed 0xdddd,0xdddd,gr43 + test_fr_limmed 0x1111,0x1111,fr40 + test_fr_limmed 0x1111,0x1111,fr41 + test_fr_limmed 0x1111,0x1111,fr42 + test_fr_limmed 0x1111,0x1111,fr43 + + ; 1 nesr active with the correct address in neear for fr + set_mem_limmed 0x2222,0x2222,gr12 + set_mem_limmed 0x3333,0x3333,gr27 + set_mem_limmed 0x4444,0x4444,gr26 + set_mem_limmed 0x5555,0x5555,gr25 + set_mem_limmed 0x6666,0x6666,gr24 + set_mem_limmed 0x7777,0x7777,gr23 + set_mem_limmed 0x8888,0x8888,gr22 + set_mem_limmed 0x9999,0x9999,gr21 + set_mem_limmed 0xaaaa,0xaaaa,gr20 + set_mem_limmed 0xbbbb,0xbbbb,gr19 + set_mem_limmed 0xcccc,0xcccc,gr18 + set_mem_limmed 0xdddd,0xdddd,gr17 + set_mem_limmed 0xeeee,0xeeee,gr16 + set_mem_limmed 0xf0f0,0xf0f0,gr15 + set_mem_limmed 0xf1f1,0xf1f1,gr14 + set_mem_limmed 0xf2f2,0xf2f2,gr13 + set_fr_iimmed 0xeeee,0xeeee,fr8 + set_fr_iimmed 0xffff,0xffff,fr9 + set_fr_iimmed 0xcccc,0xcccc,fr10 + set_fr_iimmed 0xdddd,0xdddd,fr11 + set_gr_limmed 0x1111,0x1111,gr40 + set_gr_limmed 0x1111,0x1111,gr41 + set_gr_limmed 0x1111,0x1111,gr42 + set_gr_limmed 0x1111,0x1111,gr43 + set_fr_iimmed 0x1111,0x1111,fr40 + set_fr_iimmed 0x1111,0x1111,fr41 + set_fr_iimmed 0x1111,0x1111,fr42 + set_fr_iimmed 0x1111,0x1111,fr43 + set_gr_immed -16,gr7 + rstqf fr8,@(sp,gr7) + test_mem_limmed 0x2222,0x2222,gr12 + test_mem_limmed 0x3333,0x3333,gr27 + test_mem_limmed 0x4444,0x4444,gr26 + test_mem_limmed 0x5555,0x5555,gr25 + test_mem_limmed 0x6666,0x6666,gr24 + test_mem_limmed 0x7777,0x7777,gr23 + test_mem_limmed 0x8888,0x8888,gr22 + test_mem_limmed 0x9999,0x9999,gr21 + test_mem_limmed 0xaaaa,0xaaaa,gr20 + test_mem_limmed 0xbbbb,0xbbbb,gr19 + test_mem_limmed 0xcccc,0xcccc,gr18 + test_mem_limmed 0xdddd,0xdddd,gr17 + test_mem_limmed 0xdddd,0xdddd,gr16 + test_mem_limmed 0xcccc,0xcccc,gr15 + test_mem_limmed 0xffff,0xffff,gr14 + test_mem_limmed 0xeeee,0xeeee,gr13 + test_gr_limmed 0x1111,0x1111,gr40 + test_gr_limmed 0x1111,0x1111,gr41 + test_gr_limmed 0x1111,0x1111,gr42 + test_gr_limmed 0x1111,0x1111,gr43 + test_fr_limmed 0xeeee,0xeeee,fr40 + test_fr_limmed 0xffff,0xffff,fr41 + test_fr_limmed 0xcccc,0xcccc,fr42 + test_fr_limmed 0xdddd,0xdddd,fr43 + + pass diff --git a/sim/testsuite/sim/frv/scan.cgs b/sim/testsuite/sim/frv/scan.cgs new file mode 100644 index 0000000..d19107d --- /dev/null +++ b/sim/testsuite/sim/frv/scan.cgs @@ -0,0 +1,73 @@ +# frv testcase for scan $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global scan +scan: + set_gr_limmed 0x2aaa,0xaaaa,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + scan gr7,gr8,gr9 + test_gr_immed 0,gr9 + test_gr_limmed 0x2aaa,0xaaaa,gr7 + test_gr_limmed 0xaaaa,0xaaaa,gr8 + + set_gr_limmed 0x2aaa,0xaaaa,gr7 + set_gr_limmed 0xaaaa,0xaaab,gr8 + scan gr7,gr8,gr9 + test_gr_immed 0,gr9 + test_gr_limmed 0x2aaa,0xaaaa,gr7 + test_gr_limmed 0xaaaa,0xaaab,gr8 + + set_gr_limmed 0xd555,0x5555,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + scan gr7,gr8,gr9 + test_gr_immed 63,gr9 + test_gr_limmed 0xd555,0x5555,gr7 + test_gr_limmed 0xaaaa,0xaaaa,gr8 + + set_gr_limmed 0xd555,0x5555,gr7 + set_gr_limmed 0xaaaa,0xaaab,gr8 + scan gr7,gr8,gr9 + test_gr_immed 63,gr9 + test_gr_limmed 0xd555,0x5555,gr7 + test_gr_limmed 0xaaaa,0xaaab,gr8 + + set_gr_limmed 0xffff,0xffff,gr7 + set_gr_limmed 0x7fff,0xffff,gr8 + scan gr7,gr8,gr9 + test_gr_immed 0,gr9 + test_gr_limmed 0xffff,0xffff,gr7 + test_gr_limmed 0x7fff,0xffff,gr8 + + set_gr_limmed 0xffff,0xffff,gr7 + set_gr_limmed 0xbfff,0xffff,gr8 + scan gr7,gr8,gr9 + test_gr_immed 2,gr9 + test_gr_limmed 0xffff,0xffff,gr7 + test_gr_limmed 0xbfff,0xffff,gr8 + + set_gr_limmed 0xffff,0xffff,gr7 + set_gr_limmed 0xfffe,0xffff,gr8 + scan gr7,gr8,gr9 + test_gr_immed 16,gr9 + test_gr_limmed 0xffff,0xffff,gr7 + test_gr_limmed 0xfffe,0xffff,gr8 + + set_gr_limmed 0xffff,0xffff,gr7 + set_gr_limmed 0xffff,0xfffd,gr8 + scan gr7,gr8,gr9 + test_gr_immed 31,gr9 + test_gr_limmed 0xffff,0xffff,gr7 + test_gr_limmed 0xffff,0xfffd,gr8 + + set_gr_limmed 0xdead,0xbeef,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + scan gr7,gr8,gr9 + test_gr_immed 7,gr9 + test_gr_limmed 0xdead,0xbeef,gr7 + test_gr_limmed 0xbeef,0xdead,gr8 + + pass diff --git a/sim/testsuite/sim/frv/scani.cgs b/sim/testsuite/sim/frv/scani.cgs new file mode 100644 index 0000000..97175dc --- /dev/null +++ b/sim/testsuite/sim/frv/scani.cgs @@ -0,0 +1,55 @@ +# frv testcase for scani $GRi,$s12,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global scani +scani: + set_gr_limmed 0xffff,0xfeaa,gr7 + scani gr7,0x2aa,gr9 + test_gr_immed 0,gr9 + test_gr_limmed 0xffff,0xfeaa,gr7 + + set_gr_limmed 0xffff,0xfeaa,gr7 + scani gr7,0x2ab,gr9 + test_gr_immed 0,gr9 + test_gr_limmed 0xffff,0xfeaa,gr7 + + set_gr_limmed 0x0000,0x0155,gr7 + scani gr7,0x2aa,gr9 + test_gr_immed 63,gr9 + test_gr_limmed 0x0000,0x0155,gr7 + + set_gr_limmed 0x0000,0x0155,gr7 + scani gr7,0x2ab,gr9 + test_gr_immed 63,gr9 + test_gr_limmed 0x0000,0x0155,gr7 + + set_gr_limmed 0x7fff,0xffff,gr7 + scani gr7,-1,gr9 + test_gr_immed 0,gr9 + test_gr_limmed 0x7fff,0xffff,gr7 + + set_gr_limmed 0xbfff,0xffff,gr7 + scani gr7,-1,gr9 + test_gr_immed 1,gr9 + test_gr_limmed 0xbfff,0xffff,gr7 + + set_gr_limmed 0xfffe,0xffff,gr7 + scani gr7,-1,gr9 + test_gr_immed 15,gr9 + test_gr_limmed 0xfffe,0xffff,gr7 + + set_gr_limmed 0xffff,0xfffd,gr7 + scani gr7,-1,gr9 + test_gr_immed 30,gr9 + test_gr_limmed 0xffff,0xfffd,gr7 + + set_gr_limmed 0xdead,0xbeef,gr7 + scani gr7,-2048,gr9 + test_gr_immed 2,gr9 + test_gr_limmed 0xdead,0xbeef,gr7 + + pass diff --git a/sim/testsuite/sim/frv/sdiv.cgs b/sim/testsuite/sim/frv/sdiv.cgs new file mode 100644 index 0000000..d193b23 --- /dev/null +++ b/sim/testsuite/sim/frv/sdiv.cgs @@ -0,0 +1,75 @@ +# frv testcase for sdiv $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global sdiv +sdiv: + ; simple division 12 / 3 + set_gr_immed 3,gr3 + set_gr_immed 12,gr1 + sdiv gr1,gr3,gr2 + test_gr_immed 4,gr2 + + ; Random example + set_gr_limmed 0x0123,0x4567,gr3 + set_gr_limmed 0xfedc,0xba98,gr1 + sdiv gr1,gr3,gr2 + test_gr_immed -1,gr2 + + ; Special case from the Arch Spec Vol 2 + or_spr_immed 0x20,isr ; turn on isr.edem + set_gr_immed -1,gr3 + set_gr_limmed 0x8000,0x0000,gr1 + sdiv gr1,gr3,gr2 + test_gr_limmed 0x7fff,0xffff,gr2 + test_spr_bits 0x4,2,1,isr ; isr.aexc is set + + and_spr_immed -33,isr ; turn off isr.edem + ; set up exception handler + set_psr_et 1 + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr17 + inc_gr_immed 0x170,gr17 ; address of exception handler + set_bctrlr_0_0 gr17 + set_spr_immed 128,lcr + set_gr_immed 0,gr15 + + ; divide will cause overflow + set_spr_addr ok1,lr + set_gr_addr e1,gr17 + set_gr_immed -1,gr3 + set_gr_limmed 0x8000,0x0000,gr1 +e1: sdiv gr1,gr3,gr2 ; overflow + test_gr_immed 1,gr15 + test_gr_limmed 0x8000,0x0000,gr2; gr2 updated + + ; divide by zero + set_spr_addr ok2,lr + set_gr_addr e2,gr17 + set_gr_immed 0xdeadbeef,gr2 +e2: sdiv gr1,gr0,gr2 ; divide by zero + test_gr_immed 2,gr15 ; handler called + test_gr_immed 0xdeadbeef,gr2 ; gr2 not updated. + + pass + +ok1: ; exception handler for overflow + test_spr_bits 0x18,3,0x2,isr ; isr.dtt is set + test_spr_gr epcr0,gr17 ; return address set + test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid + test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set + inc_gr_immed 1,gr15 + rett 0 + fail + +ok2: ; exception handler for divide by zero + test_spr_bits 0x18,3,0x3,isr ; isr.dtt is set + test_spr_gr epcr0,gr17 ; return address set + test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid + test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set + inc_gr_immed 1,gr15 + rett 0 + fail diff --git a/sim/testsuite/sim/frv/sdivi.cgs b/sim/testsuite/sim/frv/sdivi.cgs new file mode 100644 index 0000000..eb781e7 --- /dev/null +++ b/sim/testsuite/sim/frv/sdivi.cgs @@ -0,0 +1,74 @@ +# frv testcase for sdivi $GRi,$s12,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global sdivi +sdivi: + ; simple division 12 / 3 + set_gr_immed 12,gr1 + sdivi gr1,3,gr2 + test_gr_immed 4,gr2 + + ; Random example + set_gr_limmed 0xfedc,0xba98,gr1 + sdivi gr1,0x7ff,gr2 + test_gr_limmed 0xffff,0xdb93,gr2 + + ; Random negative example + set_gr_limmed 0xfedc,0xba98,gr1 + sdivi gr1,-2048,gr2 + test_gr_immed 0x2468,gr2 + + ; Special case from the Arch Spec Vol 2 + or_spr_immed 0x20,isr ; turn on isr.edem + set_gr_limmed 0x8000,0x0000,gr1 + sdivi gr1,-1,gr2 + test_gr_limmed 0x7fff,0xffff,gr2 + test_spr_bits 0x4,2,1,isr ; isr.aexc is set + + and_spr_immed -33,isr ; turn off isr.edem + ; set up exception handler + set_psr_et 1 + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr17 + inc_gr_immed 0x170,gr17 ; address of exception handler + set_bctrlr_0_0 gr17 + set_spr_immed 128,lcr + set_gr_immed 0,gr15 + + ; divide will cause overflow + set_spr_addr ok1,lr + set_gr_addr e1,gr17 + set_gr_limmed 0x8000,0x0000,gr1 +e1: sdivi gr1,-1,gr2 + test_gr_immed 1,gr15 + test_gr_limmed 0x8000,0x0000,gr2 + + ; divide by zero + set_spr_addr ok2,lr + set_gr_addr e2,gr17 +e2: sdivi gr1,0,gr2 ; divide by zero + test_gr_immed 2,gr15 + + pass + +ok1: ; exception handler for overflow + test_spr_bits 0x18,3,0x2,isr ; isr.dtt is set + test_spr_gr epcr0,gr17 ; return address set + test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid + test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set + inc_gr_immed 1,gr15 + rett 0 + fail + +ok2: ; exception handler for divide by zero + test_spr_bits 0x18,3,0x3,isr ; isr.dtt is set + test_spr_gr epcr0,gr17 ; return address set + test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid + test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set + inc_gr_immed 1,gr15 + rett 0 + fail diff --git a/sim/testsuite/sim/frv/sethi.cgs b/sim/testsuite/sim/frv/sethi.cgs new file mode 100644 index 0000000..00a3bdd --- /dev/null +++ b/sim/testsuite/sim/frv/sethi.cgs @@ -0,0 +1,18 @@ +# frv testcase for sethi $s16,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global sethi +sethi: + set_gr_immed 0,gr1 + sethi 0,gr1 + test_gr_immed 0,gr1 + sethi 1,gr1 + test_gr_immed 0x00010000,gr1 + sethi 0x7fff,gr1 + test_gr_immed 0x7fff0000,gr1 + + pass diff --git a/sim/testsuite/sim/frv/sethilo.pcgs b/sim/testsuite/sim/frv/sethilo.pcgs new file mode 100644 index 0000000..c8e7b60 --- /dev/null +++ b/sim/testsuite/sim/frv/sethilo.pcgs @@ -0,0 +1,18 @@ +# frv parallel testcase for sethi $s16,$GRk and setlo $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global sethilo +sethilo: + sethi.p 0xdead,gr7 + setlo 0xbeef,gr7 + test_gr_immed 0xdeadbeef,gr7 + + setlo.p 0xdead,gr7 + sethi 0xbeef,gr7 + test_gr_immed 0xbeefdead,gr7 + + pass diff --git a/sim/testsuite/sim/frv/setlo.cgs b/sim/testsuite/sim/frv/setlo.cgs new file mode 100644 index 0000000..6bdac2e --- /dev/null +++ b/sim/testsuite/sim/frv/setlo.cgs @@ -0,0 +1,18 @@ +# frv testcase for setlo $s16,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global setlo +setlo: + set_gr_immed 0,gr1 + setlo 0,gr1 + test_gr_immed 0,gr1 + setlo 1,gr1 + test_gr_immed 1,gr1 + setlo 0x7fff,gr1 + test_gr_immed 0x7fff,gr1 + + pass diff --git a/sim/testsuite/sim/frv/setlos.cgs b/sim/testsuite/sim/frv/setlos.cgs new file mode 100644 index 0000000..8979d13 --- /dev/null +++ b/sim/testsuite/sim/frv/setlos.cgs @@ -0,0 +1,21 @@ +# frv testcase for setlos $s16,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global setlos +setlos: + setlos 0,gr1 + test_gr_immed 0,gr1 + setlos 1,gr1 + test_gr_immed 1,gr1 + setlos 0x7fff,gr1 + test_gr_immed 0x7fff,gr1 + setlos -1,gr1 + test_gr_immed -1,gr1 + setlos -32768,gr1 + test_gr_immed -32768,gr1 + + pass diff --git a/sim/testsuite/sim/frv/sll.cgs b/sim/testsuite/sim/frv/sll.cgs new file mode 100644 index 0000000..9103cf6 --- /dev/null +++ b/sim/testsuite/sim/frv/sll.cgs @@ -0,0 +1,38 @@ +# frv testcase for sll $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global sll +sll: + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_immed 2,gr8 + set_icc 0x0d,0 ; Set mask opposite of expected + sll gr8,gr7,gr8 + test_icc 1 1 0 1 icc0 + test_gr_immed 2,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_immed 2,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + sll gr8,gr7,gr8 + test_icc 1 1 1 1 icc0 + test_gr_immed 4,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_immed 1,gr8 + set_icc 0x07,0 ; Set mask opposite of expected + sll gr8,gr7,gr8 + test_icc 0 1 1 1 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_immed 2,gr8 + set_icc 0x0a,0 ; Set mask opposite of expected + sll gr8,gr7,gr8 + test_icc 1 0 1 0 icc0 + test_gr_immed 0x00000000,gr8 + + pass diff --git a/sim/testsuite/sim/frv/sllcc.cgs b/sim/testsuite/sim/frv/sllcc.cgs new file mode 100644 index 0000000..533b504 --- /dev/null +++ b/sim/testsuite/sim/frv/sllcc.cgs @@ -0,0 +1,38 @@ +# frv testcase for sllcc $GRi,$GRj,$GRk,$ICCi_1 +# mach: all + + .include "testutils.inc" + + start + + .global sllcc +sllcc: + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_immed 2,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + sllcc gr8,gr7,gr8,icc0 + test_icc 0 0 0 1 icc0 + test_gr_immed 2,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_immed 2,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + sllcc gr8,gr7,gr8,icc0 + test_icc 0 0 0 1 icc0 + test_gr_immed 4,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_immed 1,gr8 + set_icc 0x07,0 ; Set mask opposite of expected + sllcc gr8,gr7,gr8,icc0 + test_icc 1 0 0 1 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_immed 2,gr8 + set_icc 0x08,0 ; Set mask opposite of expected + sllcc gr8,gr7,gr8,icc0 + test_icc 0 1 1 0 icc0 + test_gr_immed 0x00000000,gr8 + + pass diff --git a/sim/testsuite/sim/frv/slli.cgs b/sim/testsuite/sim/frv/slli.cgs new file mode 100644 index 0000000..80c25c0 --- /dev/null +++ b/sim/testsuite/sim/frv/slli.cgs @@ -0,0 +1,34 @@ +# frv testcase for slli $GRi,$s12,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global slli +slli: + set_gr_immed 2,gr8 + set_icc 0x0d,0 ; Set mask opposite of expected + slli gr8,0x7e0,gr8 ; Shift by 0 + test_icc 1 1 0 1 icc0 + test_gr_immed 2,gr8 + + set_gr_immed 2,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + slli gr8,-31,gr8 ; Shift by 1 + test_icc 1 1 1 1 icc0 + test_gr_immed 4,gr8 + + set_gr_immed 1,gr8 + set_icc 0x07,0 ; Set mask opposite of expected + slli gr8,31,gr8 ; Shift by 31 + test_icc 0 1 1 1 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_immed 2,gr8 + set_icc 0x0a,0 ; Set mask opposite of expected + slli gr8,31,gr8 ; clear register + test_icc 1 0 1 0 icc0 + test_gr_immed 0x00000000,gr8 + + pass diff --git a/sim/testsuite/sim/frv/sllicc.cgs b/sim/testsuite/sim/frv/sllicc.cgs new file mode 100644 index 0000000..b8e4c7d --- /dev/null +++ b/sim/testsuite/sim/frv/sllicc.cgs @@ -0,0 +1,34 @@ +# frv testcase for sllicc $GRi,$s10,$GRk,$ICCi_1 +# mach: all + + .include "testutils.inc" + + start + + .global sllicc +sllicc: + set_gr_immed 2,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + sllicc gr8,0x1e0,gr8,icc0 ; Shift by 0 + test_icc 0 0 0 1 icc0 + test_gr_immed 2,gr8 + + set_gr_immed 2,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + sllicc gr8,-31,gr8,icc0 ; Shift by 1 + test_icc 0 0 0 1 icc0 + test_gr_immed 4,gr8 + + set_gr_immed 1,gr8 + set_icc 0x07,0 ; Set mask opposite of expected + sllicc gr8,31,gr8,icc0 ; Shift by 31 + test_icc 1 0 0 1 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_immed 2,gr8 + set_icc 0x08,0 ; Set mask opposite of expected + sllicc gr8,31,gr8,icc0 ; clear register + test_icc 0 1 1 0 icc0 + test_gr_immed 0x00000000,gr8 + + pass diff --git a/sim/testsuite/sim/frv/smul.cgs b/sim/testsuite/sim/frv/smul.cgs new file mode 100644 index 0000000..ed065a9 --- /dev/null +++ b/sim/testsuite/sim/frv/smul.cgs @@ -0,0 +1,182 @@ +# frv testcase for smul $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global smul +smul: + ; Positive operands + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + smul gr7,gr8,gr8 + test_gr_immed 0,gr8 + test_gr_immed 6,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed 2,gr8 + smul gr7,gr8,gr8 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed 2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + smul gr7,gr8,gr8 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed 2,gr8 + smul gr7,gr8,gr8 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + smul gr7,gr8,gr8 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result + set_gr_immed 2,gr8 + smul gr7,gr8,gr8 + test_gr_immed 0,gr8 + test_gr_limmed 0x7fff,0xfffe,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed 2,gr8 + smul gr7,gr8,gr8 + test_gr_immed 0,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed 4,gr8 + smul gr7,gr8,gr8 + test_gr_immed 1,gr8 + test_gr_limmed 0x0000,0x0000,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result + set_gr_limmed 0x7fff,0xffff,gr8 + smul gr7,gr8,gr8 + test_gr_limmed 0x3fff,0xffff,gr8 + test_gr_immed 0x00000001,gr9 + + ; Mixed operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + smul gr7,gr8,gr8 + test_gr_immed -1,gr8 + test_gr_immed -6,gr9 + + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + smul gr7,gr8,gr8 + test_gr_immed -1,gr8 + test_gr_immed -6,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + smul gr7,gr8,gr8 + test_gr_immed -1,gr8 + test_gr_immed -2,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + smul gr7,gr8,gr8 + test_gr_immed -1,gr8 + test_gr_immed -2,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed -2,gr8 + smul gr7,gr8,gr8 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + smul gr7,gr8,gr8 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result + set_gr_immed -2,gr8 + smul gr7,gr8,gr8 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0xbfff,0xfffe,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + smul gr7,gr8,gr8 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result + set_gr_immed -2,gr8 + smul gr7,gr8,gr8 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0x7fff,0xfffe,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed -4,gr8 + smul gr7,gr8,gr8 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0x0000,0x0000,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result + set_gr_limmed 0x8000,0x0000,gr8 + smul gr7,gr8,gr8 + test_gr_limmed 0xc000,0x0000,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + ; Negative operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + smul gr7,gr8,gr8 + test_gr_immed 0,gr8 + test_gr_immed 6,gr9 + + set_gr_immed -1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + smul gr7,gr8,gr8 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed -1,gr8 + smul gr7,gr8,gr8 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result + set_gr_immed -2,gr8 + smul gr7,gr8,gr8 + test_gr_immed 0,gr8 + test_gr_limmed 0x7fff,0xfffe,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + smul gr7,gr8,gr8 + test_gr_immed 0,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result + set_gr_immed -4,gr8 + smul gr7,gr8,gr8 + test_gr_immed 1,gr8 + test_gr_immed 0x00000000,gr9 + + set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result + set_gr_limmed 0x8000,0x0001,gr8 + smul gr7,gr8,gr8 + test_gr_limmed 0x3fff,0xffff,gr8 + test_gr_immed 0x00000001,gr9 + + + set_gr_limmed 0x8000,0x0000,gr7 ; max positive result + set_gr_limmed 0x8000,0x0000,gr8 + smul gr7,gr8,gr8 + test_gr_limmed 0x4000,0x0000,gr8 + test_gr_immed 0x00000000,gr9 + + pass diff --git a/sim/testsuite/sim/frv/smulcc.cgs b/sim/testsuite/sim/frv/smulcc.cgs new file mode 100644 index 0000000..76a009e --- /dev/null +++ b/sim/testsuite/sim/frv/smulcc.cgs @@ -0,0 +1,238 @@ +# frv testcase for smulcc $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global smulcc +smulcc: + ; Positive operands + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + set_icc 0x0,0 + smulcc gr7,gr8,gr8,icc0 + test_icc 0 0 0 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 6,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed 2,gr8 + set_icc 0x1,0 + smulcc gr7,gr8,gr8,icc0 + test_icc 0 0 0 1 icc0 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed 2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + set_icc 0x2,0 + smulcc gr7,gr8,gr8,icc0 + test_icc 0 0 1 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed 2,gr8 + set_icc 0xb,0 + smulcc gr7,gr8,gr8,icc0 + test_icc 0 1 1 1 icc0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + set_icc 0x8,0 + smulcc gr7,gr8,gr8,icc0 + test_icc 0 1 0 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result + set_gr_immed 2,gr8 + set_icc 0xd,0 + smulcc gr7,gr8,gr8,icc0 + test_icc 0 0 0 1 icc0 + test_gr_immed 0,gr8 + test_gr_limmed 0x7fff,0xfffe,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed 2,gr8 + set_icc 0xe,0 + smulcc gr7,gr8,gr8,icc0 + test_icc 0 0 1 0 icc0 + test_gr_immed 0,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed 4,gr8 + set_icc 0xf,0 + smulcc gr7,gr8,gr8,icc0 + test_icc 0 0 1 1 icc0 + test_gr_immed 1,gr8 + test_gr_limmed 0x0000,0x0000,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result + set_gr_limmed 0x7fff,0xffff,gr8 + set_icc 0xc,0 + smulcc gr7,gr8,gr8,icc0 + test_icc 0 0 0 0 icc0 + test_gr_limmed 0x3fff,0xffff,gr8 + test_gr_immed 0x00000001,gr9 + + ; Mixed operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + set_icc 0x5,0 + smulcc gr7,gr8,gr8,icc0 + test_icc 1 0 0 1 icc0 + test_gr_immed -1,gr8 + test_gr_immed -6,gr9 + + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + set_icc 0x6,0 + smulcc gr7,gr8,gr8,icc0 + test_icc 1 0 1 0 icc0 + test_gr_immed -1,gr8 + test_gr_immed -6,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + set_icc 0x7,0 + smulcc gr7,gr8,gr8,icc0 + test_icc 1 0 1 1 icc0 + test_gr_immed -1,gr8 + test_gr_immed -2,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + set_icc 0x4,0 + smulcc gr7,gr8,gr8,icc0 + test_icc 1 0 0 0 icc0 + test_gr_immed -1,gr8 + test_gr_immed -2,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed -2,gr8 + set_icc 0x9,0 + smulcc gr7,gr8,gr8,icc0 + test_icc 0 1 0 1 icc0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + set_icc 0xa,0 + smulcc gr7,gr8,gr8,icc0 + test_icc 0 1 1 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result + set_gr_immed -2,gr8 + set_icc 0x7,0 + smulcc gr7,gr8,gr8,icc0 + test_icc 1 0 1 1 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0xbfff,0xfffe,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + set_icc 0x4,0 + smulcc gr7,gr8,gr8,icc0 + test_icc 1 0 0 0 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result + set_gr_immed -2,gr8 + set_icc 0x5,0 + smulcc gr7,gr8,gr8,icc0 + test_icc 1 0 0 1 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0x7fff,0xfffe,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_gr_immed -4,gr8 + set_icc 0x6,0 + smulcc gr7,gr8,gr8,icc0 + test_icc 1 0 1 0 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0x0000,0x0000,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x7,0 + smulcc gr7,gr8,gr8,icc0 + test_icc 1 0 1 1 icc0 + test_gr_limmed 0xc000,0x0000,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + ; Negative operands + set_gr_immed -3,gr7 ; multiply small numbers + set_gr_immed -2,gr8 + set_icc 0xc,0 + smulcc gr7,gr8,gr8,icc0 + test_icc 0 0 0 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 6,gr9 + + set_gr_immed -1,gr7 ; multiply by 1 + set_gr_immed -2,gr8 + set_icc 0xd,0 + smulcc gr7,gr8,gr8,icc0 + test_icc 0 0 0 1 icc0 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_gr_immed -1,gr8 + set_icc 0xe,0 + smulcc gr7,gr8,gr8,icc0 + test_icc 0 0 1 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result + set_gr_immed -2,gr8 + set_icc 0xf,0 + smulcc gr7,gr8,gr8,icc0 + test_icc 0 0 1 1 icc0 + test_gr_immed 0,gr8 + test_gr_limmed 0x7fff,0xfffe,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result + set_gr_immed -2,gr8 + set_icc 0xc,0 + smulcc gr7,gr8,gr8,icc0 + test_icc 0 0 0 0 icc0 + test_gr_immed 0,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result + set_gr_immed -4,gr8 + set_icc 0xd,0 + smulcc gr7,gr8,gr8,icc0 + test_icc 0 0 0 1 icc0 + test_gr_immed 1,gr8 + test_gr_immed 0x00000000,gr9 + + set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result + set_gr_limmed 0x8000,0x0001,gr8 + set_icc 0xe,0 + smulcc gr7,gr8,gr8,icc0 + test_icc 0 0 1 0 icc0 + test_gr_limmed 0x3fff,0xffff,gr8 + test_gr_immed 0x00000001,gr9 + + + set_gr_limmed 0x8000,0x0000,gr7 ; max positive result + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0xf,0 + smulcc gr7,gr8,gr8,icc0 + test_icc 0 0 1 1 icc0 + test_gr_limmed 0x4000,0x0000,gr8 + test_gr_immed 0x00000000,gr9 + + pass diff --git a/sim/testsuite/sim/frv/smuli.cgs b/sim/testsuite/sim/frv/smuli.cgs new file mode 100644 index 0000000..19a695c --- /dev/null +++ b/sim/testsuite/sim/frv/smuli.cgs @@ -0,0 +1,210 @@ +# frv testcase for smuli $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global smuli +smuli: + ; Positive operands + set_gr_immed 3,gr7 ; multiply small numbers + set_icc 0x0,0 + smuli gr7,2,gr8 + test_icc 0 0 0 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 6,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_icc 0x1,0 + smuli gr7,2,gr8 + test_icc 0 0 0 1 icc0 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed 2,gr7 ; multiply by 1 + set_icc 0x2,0 + smuli gr7,1,gr8 + test_icc 0 0 1 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_icc 0x3,0 + smuli gr7,2,gr8 + test_icc 0 0 1 1 icc0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 2,gr7 ; multiply by 0 + set_icc 0x4,0 + smuli gr7,0,gr8 + test_icc 0 1 0 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result + set_icc 0x5,0 + smuli gr7,2,gr8 + test_icc 0 1 0 1 icc0 + test_gr_immed 0,gr8 + test_gr_limmed 0x7fff,0xfffe,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_icc 0x6,0 + smuli gr7,2,gr8 + test_icc 0 1 1 0 icc0 + test_gr_immed 0,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_icc 0x7,0 + smuli gr7,4,gr8 + test_icc 0 1 1 1 icc0 + test_gr_immed 1,gr8 + test_gr_limmed 0x0000,0x0000,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result + set_icc 0x8,0 + smuli gr7,0x7ff,gr8 + test_icc 1 0 0 0 icc0 + test_gr_immed 0x3ff,gr8 + test_gr_limmed 0x7fff,0xf801,gr9 + + ; Mixed operands + set_gr_immed -3,gr7 ; multiply small numbers + set_icc 0x9,0 + smuli gr7,2,gr8 + test_icc 1 0 0 1 icc0 + test_gr_immed -1,gr8 + test_gr_immed -6,gr9 + + set_gr_immed 3,gr7 ; multiply small numbers + set_icc 0xa,0 + smuli gr7,-2,gr8 + test_icc 1 0 1 0 icc0 + test_gr_immed -1,gr8 + test_gr_immed -6,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_icc 0xb,0 + smuli gr7,-2,gr8 + test_icc 1 0 1 1 icc0 + test_gr_immed -1,gr8 + test_gr_immed -2,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_icc 0xc,0 + smuli gr7,1,gr8 + test_icc 1 1 0 0 icc0 + test_gr_immed -1,gr8 + test_gr_immed -2,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_icc 0xd,0 + smuli gr7,-2,gr8 + test_icc 1 1 0 1 icc0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 0 + set_icc 0xe,0 + smuli gr7,0,gr8 + test_icc 1 1 1 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result + set_icc 0xf,0 + smuli gr7,-2,gr8 + test_icc 1 1 1 1 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0xbfff,0xfffe,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_icc 0x0,0 + smuli gr7,-2,gr8 + test_icc 0 0 0 0 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result + set_icc 0x1,0 + smuli gr7,-2,gr8 + test_icc 0 0 0 1 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0x7fff,0xfffe,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_icc 0x2,0 + smuli gr7,-4,gr8 + test_icc 0 0 1 0 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0x0000,0x0000,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result + set_icc 0x3,0 + smuli gr7,-2048,gr8 + test_icc 0 0 1 1 icc0 + test_gr_limmed 0xffff,0xfc00,gr8 + test_gr_limmed 0x0000,0x0800,gr9 + + ; Negative operands + set_gr_immed -3,gr7 ; multiply small numbers + set_icc 0x4,0 + smuli gr7,-2,gr8 + test_icc 0 1 0 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 6,gr9 + + set_gr_immed -1,gr7 ; multiply by 1 + set_icc 0x5,0 + smuli gr7,-2,gr8 + test_icc 0 1 0 1 icc0 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_icc 0x6,0 + smuli gr7,-1,gr8 + test_icc 0 1 1 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result + set_icc 0x7,0 + smuli gr7,-2,gr8 + test_icc 0 1 1 1 icc0 + test_gr_immed 0,gr8 + test_gr_limmed 0x7fff,0xfffe,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result + set_icc 0x8,0 + smuli gr7,-2,gr8 + test_icc 1 0 0 0 icc0 + test_gr_immed 0,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result + set_icc 0x9,0 + smuli gr7,-4,gr8 + test_icc 1 0 0 1 icc0 + test_gr_immed 1,gr8 + test_gr_immed 0x00000000,gr9 + + set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result + set_icc 0xa,0 + smuli gr7,-2048,gr8 + test_icc 1 0 1 0 icc0 + test_gr_limmed 0x0000,0x03ff,gr8 + test_gr_limmed 0xffff,0xf800,gr9 + + + set_gr_limmed 0x8000,0x0000,gr7 ; max positive result + set_icc 0xb,0 + smuli gr7,-2048,gr8 + test_icc 1 0 1 1 icc0 + test_gr_limmed 0x0000,0x0400,gr8 + test_gr_limmed 0x0000,0x0000,gr9 + + pass diff --git a/sim/testsuite/sim/frv/smulicc.cgs b/sim/testsuite/sim/frv/smulicc.cgs new file mode 100644 index 0000000..e9aa889 --- /dev/null +++ b/sim/testsuite/sim/frv/smulicc.cgs @@ -0,0 +1,210 @@ +# frv testcase for smulicc $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global smulicc +smulicc: + ; Positive operands + set_gr_immed 3,gr7 ; multiply small numbers + set_icc 0x0,0 + smulicc gr7,2,gr8,icc0 + test_icc 0 0 0 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 6,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_icc 0x1,0 + smulicc gr7,2,gr8,icc0 + test_icc 0 0 0 1 icc0 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed 2,gr7 ; multiply by 1 + set_icc 0x2,0 + smulicc gr7,1,gr8,icc0 + test_icc 0 0 1 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_icc 0x3,0 + smulicc gr7,2,gr8,icc0 + test_icc 0 1 1 1 icc0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 2,gr7 ; multiply by 0 + set_icc 0x4,0 + smulicc gr7,0,gr8,icc0 + test_icc 0 1 0 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result + set_icc 0x5,0 + smulicc gr7,2,gr8,icc0 + test_icc 0 0 0 1 icc0 + test_gr_immed 0,gr8 + test_gr_limmed 0x7fff,0xfffe,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_icc 0x6,0 + smulicc gr7,2,gr8,icc0 + test_icc 0 0 1 0 icc0 + test_gr_immed 0,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_icc 0x7,0 + smulicc gr7,4,gr8,icc0 + test_icc 0 0 1 1 icc0 + test_gr_immed 1,gr8 + test_gr_limmed 0x0000,0x0000,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result + set_icc 0x8,0 + smulicc gr7,0x1ff,gr8,icc0 + test_icc 0 0 0 0 icc0 + test_gr_immed 0xff,gr8 + test_gr_limmed 0x7fff,0xfe01,gr9 + + ; Mixed operands + set_gr_immed -3,gr7 ; multiply small numbers + set_icc 0x9,0 + smulicc gr7,2,gr8,icc0 + test_icc 1 0 0 1 icc0 + test_gr_immed -1,gr8 + test_gr_immed -6,gr9 + + set_gr_immed 3,gr7 ; multiply small numbers + set_icc 0xa,0 + smulicc gr7,-2,gr8,icc0 + test_icc 1 0 1 0 icc0 + test_gr_immed -1,gr8 + test_gr_immed -6,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_icc 0xb,0 + smulicc gr7,-2,gr8,icc0 + test_icc 1 0 1 1 icc0 + test_gr_immed -1,gr8 + test_gr_immed -2,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_icc 0xc,0 + smulicc gr7,1,gr8,icc0 + test_icc 1 0 0 0 icc0 + test_gr_immed -1,gr8 + test_gr_immed -2,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_icc 0xd,0 + smulicc gr7,-2,gr8,icc0 + test_icc 0 1 0 1 icc0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_immed -2,gr7 ; multiply by 0 + set_icc 0xe,0 + smulicc gr7,0,gr8,icc0 + test_icc 0 1 1 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result + set_icc 0xf,0 + smulicc gr7,-2,gr8,icc0 + test_icc 1 0 1 1 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0xbfff,0xfffe,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_icc 0x0,0 + smulicc gr7,-2,gr8,icc0 + test_icc 1 0 0 0 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result + set_icc 0x1,0 + smulicc gr7,-2,gr8,icc0 + test_icc 1 0 0 1 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0x7fff,0xfffe,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result + set_icc 0x2,0 + smulicc gr7,-4,gr8,icc0 + test_icc 1 0 1 0 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + test_gr_limmed 0x0000,0x0000,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result + set_icc 0x3,0 + smulicc gr7,-512,gr8,icc0 + test_icc 1 0 1 1 icc0 + test_gr_limmed 0xffff,0xff00,gr8 + test_gr_limmed 0x0000,0x0200,gr9 + + ; Negative operands + set_gr_immed -3,gr7 ; multiply small numbers + set_icc 0x4,0 + smulicc gr7,-2,gr8,icc0 + test_icc 0 0 0 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 6,gr9 + + set_gr_immed -1,gr7 ; multiply by 1 + set_icc 0x5,0 + smulicc gr7,-2,gr8,icc0 + test_icc 0 0 0 1 icc0 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed -2,gr7 ; multiply by 1 + set_icc 0x6,0 + smulicc gr7,-1,gr8,icc0 + test_icc 0 0 1 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result + set_icc 0x7,0 + smulicc gr7,-2,gr8,icc0 + test_icc 0 0 1 1 icc0 + test_gr_immed 0,gr8 + test_gr_limmed 0x7fff,0xfffe,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result + set_icc 0x8,0 + smulicc gr7,-2,gr8,icc0 + test_icc 0 0 0 0 icc0 + test_gr_immed 0,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result + set_icc 0x9,0 + smulicc gr7,-4,gr8,icc0 + test_icc 0 0 0 1 icc0 + test_gr_immed 1,gr8 + test_gr_immed 0x00000000,gr9 + + set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result + set_icc 0xa,0 + smulicc gr7,-512,gr8,icc0 + test_icc 0 0 1 0 icc0 + test_gr_limmed 0x0000,0x00ff,gr8 + test_gr_limmed 0xffff,0xfe00,gr9 + + + set_gr_limmed 0x8000,0x0000,gr7 ; max positive result + set_icc 0xb,0 + smulicc gr7,-512,gr8,icc0 + test_icc 0 0 1 1 icc0 + test_gr_limmed 0x0000,0x0100,gr8 + test_gr_limmed 0x0000,0x0000,gr9 + + pass diff --git a/sim/testsuite/sim/frv/sra.cgs b/sim/testsuite/sim/frv/sra.cgs new file mode 100644 index 0000000..0f0c864 --- /dev/null +++ b/sim/testsuite/sim/frv/sra.cgs @@ -0,0 +1,38 @@ +# frv testcase for sra $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global sra +sra: + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + sra gr8,gr7,gr8 + test_icc 0 1 0 1 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + sra gr8,gr7,gr8 + test_icc 1 1 1 1 icc0 + test_gr_limmed 0xc000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + sra gr8,gr7,gr8 + test_icc 1 1 1 1 icc0 + test_gr_immed -1,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,0 ; Set mask opposite of expected + sra gr8,gr7,gr8 + test_icc 1 0 1 0 icc0 + test_gr_immed 0x00000000,gr8 + + pass diff --git a/sim/testsuite/sim/frv/sracc.cgs b/sim/testsuite/sim/frv/sracc.cgs new file mode 100644 index 0000000..14f4a8b --- /dev/null +++ b/sim/testsuite/sim/frv/sracc.cgs @@ -0,0 +1,38 @@ +# frv testcase for sracc $GRi,$GRj,$GRk,$ICCi_1 +# mach: all + + .include "testutils.inc" + + start + + .global sracc +sracc: + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + sracc gr8,gr7,gr8,icc0 + test_icc 1 0 0 0 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x07,0 ; Set mask opposite of expected + sracc gr8,gr7,gr8,icc0 + test_icc 1 0 1 0 icc0 + test_gr_limmed 0xc000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x07,0 ; Set mask opposite of expected + sracc gr8,gr7,gr8,icc0 + test_icc 1 0 1 0 icc0 + test_gr_immed -1,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,0 ; Set mask opposite of expected + sracc gr8,gr7,gr8,icc0 + test_icc 0 1 1 1 icc0 + test_gr_immed 0x00000000,gr8 + + pass diff --git a/sim/testsuite/sim/frv/srai.cgs b/sim/testsuite/sim/frv/srai.cgs new file mode 100644 index 0000000..02b9654 --- /dev/null +++ b/sim/testsuite/sim/frv/srai.cgs @@ -0,0 +1,34 @@ +# frv testcase for srai $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global srai +srai: + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + srai gr8,0x7e0,gr8 ; Shift by 0 + test_icc 0 1 0 1 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + srai gr8,-31,gr8 ; Shift by 1 + test_icc 1 1 1 1 icc0 + test_gr_limmed 0xc000,0x0000,gr8 + + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + srai gr8,31,gr8 ; Shift by 31 + test_icc 1 1 1 1 icc0 + test_gr_immed -1,gr8 + + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,0 ; Set mask opposite of expected + srai gr8,31,gr8 ; clear register + test_icc 1 0 1 0 icc0 + test_gr_immed 0x00000000,gr8 + + pass diff --git a/sim/testsuite/sim/frv/sraicc.cgs b/sim/testsuite/sim/frv/sraicc.cgs new file mode 100644 index 0000000..5dbd1e6 --- /dev/null +++ b/sim/testsuite/sim/frv/sraicc.cgs @@ -0,0 +1,34 @@ +# frv testcase for sraicc $GRi,$GRj,$GRk,$ICCi_1 +# mach: all + + .include "testutils.inc" + + start + + .global sraicc +sraicc: + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + sraicc gr8,0x1e0,gr8,icc0 ; Shift by 0 + test_icc 1 0 0 0 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x07,0 ; Set mask opposite of expected + sraicc gr8,-31,gr8,icc0 ; Shift by 1 + test_icc 1 0 1 0 icc0 + test_gr_limmed 0xc000,0x0000,gr8 + + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x07,0 ; Set mask opposite of expected + sraicc gr8,31,gr8,icc0 ; Shift by 31 + test_icc 1 0 1 0 icc0 + test_gr_immed -1,gr8 + + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,0 ; Set mask opposite of expected + sraicc gr8,31,gr8,icc0 ; clear register + test_icc 0 1 1 1 icc0 + test_gr_immed 0x00000000,gr8 + + pass diff --git a/sim/testsuite/sim/frv/srl.cgs b/sim/testsuite/sim/frv/srl.cgs new file mode 100644 index 0000000..045e75e --- /dev/null +++ b/sim/testsuite/sim/frv/srl.cgs @@ -0,0 +1,38 @@ +# frv testcase for srl $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global srl +srl: + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + srl gr8,gr7,gr8 + test_icc 0 1 0 1 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + srl gr8,gr7,gr8 + test_icc 1 1 1 1 icc0 + test_gr_limmed 0x4000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + srl gr8,gr7,gr8 + test_icc 1 1 1 1 icc0 + test_gr_immed 1,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,0 ; Set mask opposite of expected + srl gr8,gr7,gr8 + test_icc 1 0 1 0 icc0 + test_gr_immed 0x00000000,gr8 + + pass diff --git a/sim/testsuite/sim/frv/srlcc.cgs b/sim/testsuite/sim/frv/srlcc.cgs new file mode 100644 index 0000000..1450a4b --- /dev/null +++ b/sim/testsuite/sim/frv/srlcc.cgs @@ -0,0 +1,38 @@ +# frv testcase for srlcc $GRi,$GRj,$GRk,$ICCi_1 +# mach: all + + .include "testutils.inc" + + start + + .global srlcc +srlcc: + set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + srlcc gr8,gr7,gr8,icc0 + test_icc 1 0 0 0 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + srlcc gr8,gr7,gr8,icc0 + test_icc 0 0 1 0 icc0 + test_gr_limmed 0x4000,0x0000,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + srlcc gr8,gr7,gr8,icc0 + test_icc 0 0 1 0 icc0 + test_gr_immed 1,gr8 + + set_gr_limmed 0xdead,0xbeff,gr7 ; clear register + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,0 ; Set mask opposite of expected + srlcc gr8,gr7,gr8,icc0 + test_icc 0 1 1 1 icc0 + test_gr_immed 0x00000000,gr8 + + pass diff --git a/sim/testsuite/sim/frv/srli.cgs b/sim/testsuite/sim/frv/srli.cgs new file mode 100644 index 0000000..72207d3 --- /dev/null +++ b/sim/testsuite/sim/frv/srli.cgs @@ -0,0 +1,34 @@ +# frv testcase for srli $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global srli +srli: + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + srli gr8,0x7e0,gr8 ; Shift by 0 + test_icc 0 1 0 1 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + srli gr8,-31,gr8 ; Shift by 1 + test_icc 1 1 1 1 icc0 + test_gr_limmed 0x4000,0x0000,gr8 + + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + srli gr8,31,gr8 ; Shift by 31 + test_icc 1 1 1 1 icc0 + test_gr_immed 1,gr8 + + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,0 ; Set mask opposite of expected + srli gr8,31,gr8 ; clear register + test_icc 1 0 1 0 icc0 + test_gr_immed 0x00000000,gr8 + + pass diff --git a/sim/testsuite/sim/frv/srlicc.cgs b/sim/testsuite/sim/frv/srlicc.cgs new file mode 100644 index 0000000..d232802 --- /dev/null +++ b/sim/testsuite/sim/frv/srlicc.cgs @@ -0,0 +1,34 @@ +# frv testcase for srlicc $GRi,$s10,$GRk,$ICCi_1 +# mach: all + + .include "testutils.inc" + + start + + .global srlicc +srlicc: + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + srlicc gr8,0x1e0,gr8,icc0 ; Shift by 0 + test_icc 1 0 0 0 icc0 + test_gr_limmed 0x8000,0x0000,gr8 + + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + srlicc gr8,-31,gr8,icc0 ; Shift by 1 + test_icc 0 0 1 0 icc0 + test_gr_limmed 0x4000,0x0000,gr8 + + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + srlicc gr8,31,gr8,icc0 ; Shift by 31 + test_icc 0 0 1 0 icc0 + test_gr_immed 1,gr8 + + set_gr_limmed 0x4000,0x0000,gr8 + set_icc 0x0a,0 ; Set mask opposite of expected + srlicc gr8,31,gr8,icc0 ; clear register + test_icc 0 1 1 1 icc0 + test_gr_immed 0x00000000,gr8 + + pass diff --git a/sim/testsuite/sim/frv/st.cgs b/sim/testsuite/sim/frv/st.cgs new file mode 100644 index 0000000..557713c --- /dev/null +++ b/sim/testsuite/sim/frv/st.cgs @@ -0,0 +1,16 @@ +# frv testcase for st $GRk,@($GRi,$GRj) +# mach: all + + .include "testutils.inc" + + start + + .global add +add: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + st gr8,@(sp,gr7) + test_mem_limmed 0xffff,0xffff,sp + + pass diff --git a/sim/testsuite/sim/frv/stb.cgs b/sim/testsuite/sim/frv/stb.cgs new file mode 100644 index 0000000..15fa1e6 --- /dev/null +++ b/sim/testsuite/sim/frv/stb.cgs @@ -0,0 +1,16 @@ +# frv testcase for stb $GRk,@($GRi,$GRj) +# mach: all + + .include "testutils.inc" + + start + + .global add +add: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + stb gr8,@(sp,gr7) + test_mem_limmed 0xffad,0xbeef,sp + + pass diff --git a/sim/testsuite/sim/frv/stbf.cgs b/sim/testsuite/sim/frv/stbf.cgs new file mode 100644 index 0000000..741327d --- /dev/null +++ b/sim/testsuite/sim/frv/stbf.cgs @@ -0,0 +1,16 @@ +# frv testcase for stbf $FRk,@($GRi,$GRj) +# mach: all + + .include "testutils.inc" + + start + + .global stbf +stbf: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + stbf fr8,@(sp,gr7) + test_mem_limmed 0xffad,0xbeef,sp + + pass diff --git a/sim/testsuite/sim/frv/stbfi.cgs b/sim/testsuite/sim/frv/stbfi.cgs new file mode 100644 index 0000000..cfea708 --- /dev/null +++ b/sim/testsuite/sim/frv/stbfi.cgs @@ -0,0 +1,24 @@ +# frv testcase for stbfi $FRk,@($GRi,$GRj) +# mach: all + + .include "testutils.inc" + + start + + .global stbfi +stbfi: + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_fr_iimmed 0xffff,0xffff,fr8 + stbfi fr8,@(sp,0) + test_mem_limmed 0xffad,0xbeef,sp + + inc_gr_immed 0x801,sp ; 2049 + stbfi fr8,@(sp,-2048) + test_mem_limmed 0xffff,0xbeef,gr20 + + inc_gr_immed -4094,sp + stbfi fr8,@(sp,0x7ff) + test_mem_limmed 0xffff,0xffef,gr20 + + pass diff --git a/sim/testsuite/sim/frv/stbfu.cgs b/sim/testsuite/sim/frv/stbfu.cgs new file mode 100644 index 0000000..01bbb99 --- /dev/null +++ b/sim/testsuite/sim/frv/stbfu.cgs @@ -0,0 +1,19 @@ +# frv testcase for stbfu $FRk,@($GRi,$GRj) +# mach: all + + .include "testutils.inc" + + start + + .global stbfu +stbfu: + set_gr_gr sp,gr9 + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + stbfu fr8,@(sp,gr7) + test_mem_limmed 0xffad,0xbeef,sp + test_gr_gr sp,gr9 + + pass diff --git a/sim/testsuite/sim/frv/stbi.cgs b/sim/testsuite/sim/frv/stbi.cgs new file mode 100644 index 0000000..f23efc9 --- /dev/null +++ b/sim/testsuite/sim/frv/stbi.cgs @@ -0,0 +1,24 @@ +# frv testcase for stbi $GRk,@($GRi,$GRj) +# mach: all + + .include "testutils.inc" + + start + + .global stbi +stbi: + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_gr_limmed 0xffff,0xffff,gr8 + stbi gr8,@(sp,0) + test_mem_limmed 0xffad,0xbeef,sp + + inc_gr_immed 0x801,sp ; 2049 + stbi gr8,@(sp,-2048) + test_mem_limmed 0xffff,0xbeef,gr20 + + inc_gr_immed -4094,sp + stbi gr8,@(sp,0x7ff) + test_mem_limmed 0xffff,0xffef,gr20 + + pass diff --git a/sim/testsuite/sim/frv/stbu.cgs b/sim/testsuite/sim/frv/stbu.cgs new file mode 100644 index 0000000..e56ad11 --- /dev/null +++ b/sim/testsuite/sim/frv/stbu.cgs @@ -0,0 +1,19 @@ +# frv testcase for stbu $GRk,@($GRi,$GRj) +# mach: all + + .include "testutils.inc" + + start + + .global stbu +stbu: + set_gr_gr sp,gr9 + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + stbu gr8,@(sp,gr7) + test_mem_limmed 0xffad,0xbeef,sp + test_gr_gr sp,gr9 + + pass diff --git a/sim/testsuite/sim/frv/stc.cgs b/sim/testsuite/sim/frv/stc.cgs new file mode 100644 index 0000000..581297c --- /dev/null +++ b/sim/testsuite/sim/frv/stc.cgs @@ -0,0 +1,17 @@ +# frv testcase for stc $CPRk,@($GRi,$GRj) +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global stc +stc: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_cpr_limmed 0xffff,0xffff,cpr8 + stc cpr8,@(sp,gr7) + test_mem_limmed 0xffff,0xffff,sp + + pass diff --git a/sim/testsuite/sim/frv/stcu.cgs b/sim/testsuite/sim/frv/stcu.cgs new file mode 100644 index 0000000..eb9e6c5 --- /dev/null +++ b/sim/testsuite/sim/frv/stcu.cgs @@ -0,0 +1,33 @@ +# frv testcase for stcu $CPRk,@($GRi,$GRj) +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global stcu +stcu: + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_cpr_limmed 0xffff,0xffff,cpr8 + stcu cpr8,@(sp,gr7) + test_mem_limmed 0xffff,0xffff,sp + test_gr_gr sp,gr20 + + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + set_cpr_limmed 0x1234,0x5678,cpr8 + stcu cpr8,@(sp,gr7) + test_mem_limmed 0x1234,0x5678,sp + test_gr_gr sp,gr20 + + inc_gr_immed 4,sp + set_gr_immed -4,gr7 + set_cpr_limmed 0x9abc,0xdef0,cpr8 + stcu cpr8,@(sp,gr7) + test_mem_limmed 0x9abc,0xdef0,sp + test_gr_gr sp,gr20 + + pass diff --git a/sim/testsuite/sim/frv/std.cgs b/sim/testsuite/sim/frv/std.cgs new file mode 100644 index 0000000..8a2ed12 --- /dev/null +++ b/sim/testsuite/sim/frv/std.cgs @@ -0,0 +1,32 @@ +# frv testcase for std $GRk,@($GRi,$GRj) +# mach: all + + .include "testutils.inc" + + start + + .global add +add: + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_limmed 0xdead,0xbeef,gr9 + std gr8,@(sp,gr7) + test_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xbeef,sp + + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr3 ; sp is gr1 + set_gr_limmed 0xbeef,0xdead,gr0 + set_gr_limmed 0xdead,0xbeef,gr1 + std gr0,@(gr3,gr7) + test_mem_immed 0,gr3 + inc_gr_immed 4,gr3 + test_mem_immed 0,gr3 + + pass diff --git a/sim/testsuite/sim/frv/std.pcgs b/sim/testsuite/sim/frv/std.pcgs new file mode 100644 index 0000000..d518b8b --- /dev/null +++ b/sim/testsuite/sim/frv/std.pcgs @@ -0,0 +1,37 @@ +# frv parallel testcase for std $GRk,@($GRi,$GRj) +# mach: all + + .include "testutils.inc" + + start + + .global add +add: + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_limmed 0xdead,0xbeef,gr9 + std gr8,@(sp,gr7) ; non parallel + test_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xbeef,sp + + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 4,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_limmed 0xdead,0xbeef,gr9 + std.p gr8,@(sp,gr0) ; parallel + setlos 0,gr8 + ld @(sp,gr0),gr10 + ld @(sp,gr7),gr11 + test_mem_limmed 0xbeef,0xdead,sp ; memory is set + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xbeef,sp + test_gr_immed 0xbeefdead,gr10 ; regs were pre-loaded + test_gr_immed 0xdeadbeef,gr11 ; not this one + + pass diff --git a/sim/testsuite/sim/frv/stdc.cgs b/sim/testsuite/sim/frv/stdc.cgs new file mode 100644 index 0000000..bdff0ac --- /dev/null +++ b/sim/testsuite/sim/frv/stdc.cgs @@ -0,0 +1,21 @@ +# frv testcase for stdc $CPk,@($GRi,$GRj) +# mach: frv + + .include "testutils.inc" + + start + + .global stdc +stdc: + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_cpr_limmed 0xbeef,0xdead,cpr8 + set_cpr_limmed 0xdead,0xbeef,cpr9 + stdc cpr8,@(sp,gr7) + test_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xbeef,sp + + pass diff --git a/sim/testsuite/sim/frv/stdc.pcgs b/sim/testsuite/sim/frv/stdc.pcgs new file mode 100644 index 0000000..46c4925 --- /dev/null +++ b/sim/testsuite/sim/frv/stdc.pcgs @@ -0,0 +1,38 @@ +# frv parallel testcase for stdc $CPk,@($GRi,$GRj) +# mach: frv + + .include "testutils.inc" + + start + + .global stdc +stdc: + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_cpr_limmed 0xbeef,0xdead,cpr8 + set_cpr_limmed 0xdead,0xbeef,cpr9 + stdc cpr8,@(sp,gr7) ; non parallel + test_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xbeef,sp + + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 4,gr7 + set_cpr_limmed 0xbeef,0xdead,cpr8 + set_cpr_limmed 0xdead,0xbeef,cpr9 + stdc.p cpr8,@(sp,gr0) ; parallel + addi sp,4,sp + subi sp,4,sp + ldc @(sp,gr0),cpr10 + ldc @(sp,gr7),cpr11 + test_mem_limmed 0xbeef,0xdead,sp ; memory is set + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xbeef,sp + test_cpr_limmed 0xbeef,0xdead,cpr10 + test_cpr_limmed 0xdead,0xbeef,cpr11 + + pass diff --git a/sim/testsuite/sim/frv/stdcu.cgs b/sim/testsuite/sim/frv/stdcu.cgs new file mode 100644 index 0000000..bbae5ff --- /dev/null +++ b/sim/testsuite/sim/frv/stdcu.cgs @@ -0,0 +1,44 @@ +# frv testcase for stdcu $CPk,@($GRi,$GRj) +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global stdcu +stdcu: + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr20 + set_gr_immed 0,gr7 + set_cpr_limmed 0xbeef,0xdead,cpr8 + set_cpr_limmed 0xdead,0xbeef,cpr9 + stdcu cpr8,@(sp,gr7) + test_gr_gr sp,gr20 + test_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xbeef,sp + + inc_gr_immed -12,sp + set_gr_immed 8,gr7 + set_cpr_limmed 0x1234,0x5678,cpr8 + set_cpr_limmed 0x9abc,0xdef0,cpr9 + stdcu cpr8,@(sp,gr7) + test_gr_gr sp,gr20 + test_mem_limmed 0x1234,0x5678,sp + inc_gr_immed 4,sp + test_mem_limmed 0x9abc,0xdef0,sp + + inc_gr_immed 4,sp + set_gr_immed -8,gr7 + set_cpr_limmed 0xfedc,0xba98,cpr8 + set_cpr_limmed 0x7654,0x3210,cpr9 + stdcu cpr8,@(sp,gr7) + test_gr_gr sp,gr20 + test_mem_limmed 0xfedc,0xba98,sp + inc_gr_immed 4,sp + test_mem_limmed 0x7654,0x3210,sp + + pass diff --git a/sim/testsuite/sim/frv/stdf.cgs b/sim/testsuite/sim/frv/stdf.cgs new file mode 100644 index 0000000..82c1461 --- /dev/null +++ b/sim/testsuite/sim/frv/stdf.cgs @@ -0,0 +1,21 @@ +# frv testcase for stdf $GRk,@($GRi,$GRj) +# mach: all + + .include "testutils.inc" + + start + + .global stdf +stdf: + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_fr_iimmed 0xbeef,0xdead,fr8 + set_fr_iimmed 0xdead,0xbeef,fr9 + stdf fr8,@(sp,gr7) + test_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xbeef,sp + + pass diff --git a/sim/testsuite/sim/frv/stdf.pcgs b/sim/testsuite/sim/frv/stdf.pcgs new file mode 100644 index 0000000..7ef991c --- /dev/null +++ b/sim/testsuite/sim/frv/stdf.pcgs @@ -0,0 +1,37 @@ +# frv parallel testcase for stdf $GRk,@($GRi,$GRj) +# mach: fr500 fr550 frv + + .include "testutils.inc" + + start + + .global stdf +stdf: + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_fr_iimmed 0xbeef,0xdead,fr8 + set_fr_iimmed 0xdead,0xbeef,fr9 + stdf fr8,@(sp,gr7) ; non parallel + test_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xbeef,sp + + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 4,gr7 + set_fr_iimmed 0xbeef,0xdead,fr8 + set_fr_iimmed 0xdead,0xbeef,fr9 + stdf.p fr8,@(sp,gr0) ; parallel + fnegs fr8,fr8 + ldf @(sp,gr0),fr10 + ldf @(sp,gr7),fr11 ; memory is set + test_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xbeef,sp + test_fr_iimmed 0xbeefdead,fr10 ; regs were pre-loaded + test_fr_iimmed 0xdeadbeef,fr11 ; not this one + + pass diff --git a/sim/testsuite/sim/frv/stdfi.cgs b/sim/testsuite/sim/frv/stdfi.cgs new file mode 100644 index 0000000..fea9b51 --- /dev/null +++ b/sim/testsuite/sim/frv/stdfi.cgs @@ -0,0 +1,56 @@ +# frv testcase for stdfi $FRk,@($GRi,$GRj) +# mach: all + + .include "testutils.inc" + + start + + .global stdfi +stdfi: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr20 + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_gr sp,gr21 + inc_gr_immed -4,sp + set_mem_limmed 0x1234,0x5678,sp + set_gr_gr sp,gr22 + inc_gr_immed -4,sp + set_mem_limmed 0x8765,0x4321,sp + set_gr_gr sp,gr23 + inc_gr_immed -4,sp + set_mem_limmed 0xfedc,0xba98,sp + set_gr_gr sp,gr24 + inc_gr_immed -4,sp + set_mem_limmed 0x89ab,0xcdef,sp + set_gr_gr sp,gr25 + set_fr_iimmed 0xffff,0xffff,fr8 + set_fr_iimmed 0xffff,0xffff,fr9 + + stdfi fr8,@(sp,0) + test_mem_limmed 0xffff,0xffff,gr25 + test_mem_limmed 0xffff,0xffff,gr24 + test_mem_limmed 0x8765,0x4321,gr23 + test_mem_limmed 0x1234,0x5678,gr22 + test_mem_limmed 0xbeef,0xdead,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + inc_gr_immed 0x808,sp ; 2056 + stdfi fr8,@(sp,-2048) + test_mem_limmed 0xffff,0xffff,gr25 + test_mem_limmed 0xffff,0xffff,gr24 + test_mem_limmed 0xffff,0xffff,gr23 + test_mem_limmed 0xffff,0xffff,gr22 + test_mem_limmed 0xbeef,0xdead,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + inc_gr_immed -4080,sp + stdfi fr8,@(sp,0x7f8) + test_mem_limmed 0xffff,0xffff,gr25 + test_mem_limmed 0xffff,0xffff,gr24 + test_mem_limmed 0xffff,0xffff,gr23 + test_mem_limmed 0xffff,0xffff,gr22 + test_mem_limmed 0xffff,0xffff,gr21 + test_mem_limmed 0xffff,0xffff,gr20 + + pass diff --git a/sim/testsuite/sim/frv/stdfu.cgs b/sim/testsuite/sim/frv/stdfu.cgs new file mode 100644 index 0000000..439cfa0 --- /dev/null +++ b/sim/testsuite/sim/frv/stdfu.cgs @@ -0,0 +1,24 @@ +# frv testcase for stdfu $FRk,@($GRi,$GRj) +# mach: all + + .include "testutils.inc" + + start + + .global stdfu +stdfu: + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr20 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + set_fr_iimmed 0xbeef,0xdead,fr8 + set_fr_iimmed 0xdead,0xbeef,fr9 + stdfu fr8,@(sp,gr7) + test_gr_gr sp,gr20 + test_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xbeef,sp + + pass diff --git a/sim/testsuite/sim/frv/stdi.cgs b/sim/testsuite/sim/frv/stdi.cgs new file mode 100644 index 0000000..e1a783d --- /dev/null +++ b/sim/testsuite/sim/frv/stdi.cgs @@ -0,0 +1,56 @@ +# frv testcase for stdi $GRk,@($GRi,$GRj) +# mach: all + + .include "testutils.inc" + + start + + .global stdi +stdi: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr20 + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_gr sp,gr21 + inc_gr_immed -4,sp + set_mem_limmed 0x1234,0x5678,sp + set_gr_gr sp,gr22 + inc_gr_immed -4,sp + set_mem_limmed 0x8765,0x4321,sp + set_gr_gr sp,gr23 + inc_gr_immed -4,sp + set_mem_limmed 0xfedc,0xba98,sp + set_gr_gr sp,gr24 + inc_gr_immed -4,sp + set_mem_limmed 0x89ab,0xcdef,sp + set_gr_gr sp,gr25 + set_gr_limmed 0xffff,0xffff,gr8 + set_gr_limmed 0xffff,0xffff,gr9 + + stdi gr8,@(sp,0) + test_mem_limmed 0xffff,0xffff,gr25 + test_mem_limmed 0xffff,0xffff,gr24 + test_mem_limmed 0x8765,0x4321,gr23 + test_mem_limmed 0x1234,0x5678,gr22 + test_mem_limmed 0xbeef,0xdead,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + inc_gr_immed 0x808,sp ; 2056 + stdi gr8,@(sp,-2048) + test_mem_limmed 0xffff,0xffff,gr25 + test_mem_limmed 0xffff,0xffff,gr24 + test_mem_limmed 0xffff,0xffff,gr23 + test_mem_limmed 0xffff,0xffff,gr22 + test_mem_limmed 0xbeef,0xdead,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + inc_gr_immed -4080,sp + stdi gr8,@(sp,0x7f8) + test_mem_limmed 0xffff,0xffff,gr25 + test_mem_limmed 0xffff,0xffff,gr24 + test_mem_limmed 0xffff,0xffff,gr23 + test_mem_limmed 0xffff,0xffff,gr22 + test_mem_limmed 0xffff,0xffff,gr21 + test_mem_limmed 0xffff,0xffff,gr20 + + pass diff --git a/sim/testsuite/sim/frv/stdu.cgs b/sim/testsuite/sim/frv/stdu.cgs new file mode 100644 index 0000000..b5f122f --- /dev/null +++ b/sim/testsuite/sim/frv/stdu.cgs @@ -0,0 +1,24 @@ +# frv testcase for stdu $GRk,@($GRi,$GRj) +# mach: all + + .include "testutils.inc" + + start + + .global stdu +stdu: + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr20 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_limmed 0xdead,0xbeef,gr9 + stdu gr8,@(sp,gr7) + test_gr_gr sp,gr20 + test_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xbeef,sp + + pass diff --git a/sim/testsuite/sim/frv/stf.cgs b/sim/testsuite/sim/frv/stf.cgs new file mode 100644 index 0000000..5ebc060 --- /dev/null +++ b/sim/testsuite/sim/frv/stf.cgs @@ -0,0 +1,16 @@ +# frv testcase for stf $FRk,@($GRi,$GRj) +# mach: all + + .include "testutils.inc" + + start + + .global stf +stf: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + stf fr8,@(sp,gr7) + test_mem_limmed 0xffff,0xffff,sp + + pass diff --git a/sim/testsuite/sim/frv/stfi.cgs b/sim/testsuite/sim/frv/stfi.cgs new file mode 100644 index 0000000..cfce1fd --- /dev/null +++ b/sim/testsuite/sim/frv/stfi.cgs @@ -0,0 +1,37 @@ +# frv testcase for stfi $FRk,@($GRi,$GRj) +# mach: all + + .include "testutils.inc" + + start + + .global stfi +stfi: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr20 + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_gr sp,gr21 + inc_gr_immed -4,sp + set_mem_limmed 0x1234,0x5678,sp + set_gr_gr sp,gr22 + set_fr_iimmed 0xffff,0xffff,fr8 + + stfi fr8,@(sp,0) + test_mem_limmed 0xffff,0xffff,gr22 + test_mem_limmed 0xbeef,0xdead,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + inc_gr_immed 0x804,sp ; 2052 + stfi fr8,@(sp,-2048) + test_mem_limmed 0xffff,0xffff,gr22 + test_mem_limmed 0xffff,0xffff,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + inc_gr_immed -4088,sp + stfi fr8,@(sp,0x7fc) + test_mem_limmed 0xffff,0xffff,gr22 + test_mem_limmed 0xffff,0xffff,gr21 + test_mem_limmed 0xffff,0xffff,gr20 + + pass diff --git a/sim/testsuite/sim/frv/stfu.cgs b/sim/testsuite/sim/frv/stfu.cgs new file mode 100644 index 0000000..e47e61d --- /dev/null +++ b/sim/testsuite/sim/frv/stfu.cgs @@ -0,0 +1,19 @@ +# frv testcase for stfu $FRk,@($GRi,$GRj) +# mach: all + + .include "testutils.inc" + + start + + .global stfu +stfu: + set_gr_gr sp,gr9 + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + stfu fr8,@(sp,gr7) + test_mem_limmed 0xffff,0xffff,sp + test_gr_gr sp,gr9 + + pass diff --git a/sim/testsuite/sim/frv/sth.cgs b/sim/testsuite/sim/frv/sth.cgs new file mode 100644 index 0000000..c11ae40 --- /dev/null +++ b/sim/testsuite/sim/frv/sth.cgs @@ -0,0 +1,16 @@ +# frv testcase for sth $GRk,@($GRi,$GRj) +# mach: all + + .include "testutils.inc" + + start + + .global add +add: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + sth gr8,@(sp,gr7) + test_mem_limmed 0xffff,0xbeef,sp + + pass diff --git a/sim/testsuite/sim/frv/sthf.cgs b/sim/testsuite/sim/frv/sthf.cgs new file mode 100644 index 0000000..7310e4e --- /dev/null +++ b/sim/testsuite/sim/frv/sthf.cgs @@ -0,0 +1,16 @@ +# frv testcase for sthf $FRk,@($GRi,$GRj) +# mach: all + + .include "testutils.inc" + + start + + .global sthf +sthf: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_immed 0,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + sthf fr8,@(sp,gr7) + test_mem_limmed 0xffff,0xbeef,sp + + pass diff --git a/sim/testsuite/sim/frv/sthfi.cgs b/sim/testsuite/sim/frv/sthfi.cgs new file mode 100644 index 0000000..ae9da97 --- /dev/null +++ b/sim/testsuite/sim/frv/sthfi.cgs @@ -0,0 +1,31 @@ +# frv testcase for sthfi $FRk,@($GRi,$GRj) +# mach: all + + .include "testutils.inc" + + start + + .global sthfi +sthfi: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr20 + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_gr sp,gr21 + set_fr_iimmed 0xffff,0xffff,fr8 + + sthfi fr8,@(sp,0) + test_mem_limmed 0xffff,0xdead,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + inc_gr_immed 0x802,sp ; 2050 + sthfi fr8,@(sp,-2048) + test_mem_limmed 0xffff,0xffff,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + inc_gr_immed -4092,sp + sthfi fr8,@(sp,0x7fe) + test_mem_limmed 0xffff,0xffff,gr21 + test_mem_limmed 0xffff,0xbeef,gr20 + + pass diff --git a/sim/testsuite/sim/frv/sthfu.cgs b/sim/testsuite/sim/frv/sthfu.cgs new file mode 100644 index 0000000..df472e7 --- /dev/null +++ b/sim/testsuite/sim/frv/sthfu.cgs @@ -0,0 +1,19 @@ +# frv testcase for sthfu $FRk,@($GRi,$GRj) +# mach: all + + .include "testutils.inc" + + start + + .global sthfu +sthfu: + set_gr_gr sp,gr9 + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + set_fr_iimmed 0xffff,0xffff,fr8 + sthfu fr8,@(sp,gr7) + test_mem_limmed 0xffff,0xbeef,sp + test_gr_gr sp,gr9 + + pass diff --git a/sim/testsuite/sim/frv/sthi.cgs b/sim/testsuite/sim/frv/sthi.cgs new file mode 100644 index 0000000..93636e9 --- /dev/null +++ b/sim/testsuite/sim/frv/sthi.cgs @@ -0,0 +1,31 @@ +# frv testcase for sthi $GRk,@($GRi,$GRj) +# mach: all + + .include "testutils.inc" + + start + + .global sthi +sthi: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr20 + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_gr sp,gr21 + set_gr_limmed 0xffff,0xffff,gr8 + + sthi gr8,@(sp,0) + test_mem_limmed 0xffff,0xdead,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + inc_gr_immed 0x802,sp ; 2050 + sthi gr8,@(sp,-2048) + test_mem_limmed 0xffff,0xffff,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + inc_gr_immed -4092,sp + sthi gr8,@(sp,0x7fe) + test_mem_limmed 0xffff,0xffff,gr21 + test_mem_limmed 0xffff,0xbeef,gr20 + + pass diff --git a/sim/testsuite/sim/frv/sthu.cgs b/sim/testsuite/sim/frv/sthu.cgs new file mode 100644 index 0000000..ab35b30 --- /dev/null +++ b/sim/testsuite/sim/frv/sthu.cgs @@ -0,0 +1,19 @@ +# frv testcase for sthu $GRk,@($GRi,$GRj) +# mach: all + + .include "testutils.inc" + + start + + .global sthu +sthu: + set_gr_gr sp,gr9 + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + sthu gr8,@(sp,gr7) + test_mem_limmed 0xffff,0xbeef,sp + test_gr_gr sp,gr9 + + pass diff --git a/sim/testsuite/sim/frv/sti.cgs b/sim/testsuite/sim/frv/sti.cgs new file mode 100644 index 0000000..ce05003 --- /dev/null +++ b/sim/testsuite/sim/frv/sti.cgs @@ -0,0 +1,37 @@ +# frv testcase for sti $GRk,@($GRi,$GRj) +# mach: all + + .include "testutils.inc" + + start + + .global sti +sti: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr20 + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_gr sp,gr21 + inc_gr_immed -4,sp + set_mem_limmed 0x1234,0x5678,sp + set_gr_gr sp,gr22 + set_gr_limmed 0xffff,0xffff,gr8 + + sti gr8,@(sp,0) + test_mem_limmed 0xffff,0xffff,gr22 + test_mem_limmed 0xbeef,0xdead,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + inc_gr_immed 0x804,sp ; 2052 + sti gr8,@(sp,-2048) + test_mem_limmed 0xffff,0xffff,gr22 + test_mem_limmed 0xffff,0xffff,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + inc_gr_immed -4088,sp + sti gr8,@(sp,0x7fc) + test_mem_limmed 0xffff,0xffff,gr22 + test_mem_limmed 0xffff,0xffff,gr21 + test_mem_limmed 0xffff,0xffff,gr20 + + pass diff --git a/sim/testsuite/sim/frv/stq.cgs b/sim/testsuite/sim/frv/stq.cgs new file mode 100644 index 0000000..5ec8369 --- /dev/null +++ b/sim/testsuite/sim/frv/stq.cgs @@ -0,0 +1,53 @@ +# frv testcase for stq $GRk,@($GRi,$GRj) +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global stq +stq: + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_limmed 0xdead,0xbeef,gr9 + set_gr_limmed 0xdead,0xdead,gr10 + set_gr_limmed 0xbeef,0xbeef,gr11 + stq gr8,@(sp,gr7) + test_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xdead,sp + inc_gr_immed 4,sp + test_mem_limmed 0xbeef,0xbeef,sp + + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xbeef,sp + set_gr_gr sp,gr4 ; sp is gr1 + set_gr_limmed 0xbeef,0xdead,gr0 + set_gr_limmed 0xdead,0xbeef,gr1 + set_gr_limmed 0xdead,0xdead,gr2 + set_gr_limmed 0xbeef,0xbeef,gr3 + stq gr0,@(gr4,gr7) + test_mem_immed 0,gr4 + inc_gr_immed 4,gr4 + test_mem_immed 0,gr4 + inc_gr_immed 4,gr4 + test_mem_immed 0,gr4 + inc_gr_immed 4,gr4 + test_mem_immed 0,gr4 + + pass diff --git a/sim/testsuite/sim/frv/stq.pcgs b/sim/testsuite/sim/frv/stq.pcgs new file mode 100644 index 0000000..268dd9e --- /dev/null +++ b/sim/testsuite/sim/frv/stq.pcgs @@ -0,0 +1,59 @@ +# frv parallel testcase for stq $GRk,@($GRi,$GRj) +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global stq +stq: + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_limmed 0xdead,0xbeef,gr9 + set_gr_limmed 0xdead,0xdead,gr10 + set_gr_limmed 0xbeef,0xbeef,gr11 + stq gr8,@(sp,gr7) ; non parallel + test_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xdead,sp + inc_gr_immed 4,sp + test_mem_limmed 0xbeef,0xbeef,sp + + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xbeef,sp + set_gr_immed 0,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_limmed 0xdead,0xbeef,gr9 + set_gr_limmed 0xdead,0xdead,gr10 + set_gr_limmed 0xbeef,0xbeef,gr11 + stq.p gr8,@(sp,gr7) ; parallel + setlos 0,gr8 + ldq @(sp,gr7),gr12 + test_mem_limmed 0xbeef,0xdead,sp ; memory is set + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xdead,sp + inc_gr_immed 4,sp + test_mem_limmed 0xbeef,0xbeef,sp + test_gr_immed 0xbeefdead,gr12 + test_gr_immed 0xdeadbeef,gr13 + test_gr_immed 0xdeaddead,gr14 + test_gr_immed 0xbeefbeef,gr15 + + pass diff --git a/sim/testsuite/sim/frv/stqc.cgs b/sim/testsuite/sim/frv/stqc.cgs new file mode 100644 index 0000000..19fc79d --- /dev/null +++ b/sim/testsuite/sim/frv/stqc.cgs @@ -0,0 +1,32 @@ +# frv testcase for stqc $CPRk,@($GRi,$GRj) +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global stqc +stqc: + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xbeef,sp + set_gr_immed 0,gr7 + set_cpr_limmed 0xbeef,0xdead,cpr8 + set_cpr_limmed 0xdead,0xbeef,cpr9 + set_cpr_limmed 0xdead,0xdead,cpr10 + set_cpr_limmed 0xbeef,0xbeef,cpr11 + stqc cpr8,@(sp,gr7) + test_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xdead,sp + inc_gr_immed 4,sp + test_mem_limmed 0xbeef,0xbeef,sp + + pass diff --git a/sim/testsuite/sim/frv/stqc.pcgs b/sim/testsuite/sim/frv/stqc.pcgs new file mode 100644 index 0000000..bda68ba --- /dev/null +++ b/sim/testsuite/sim/frv/stqc.pcgs @@ -0,0 +1,60 @@ +# frv parallel testcase for stqc $CPRk,@($GRi,$GRj) +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global stqc +stqc: + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xbeef,sp + set_gr_immed 0,gr7 + set_cpr_limmed 0xbeef,0xdead,cpr8 + set_cpr_limmed 0xdead,0xbeef,cpr9 + set_cpr_limmed 0xdead,0xdead,cpr10 + set_cpr_limmed 0xbeef,0xbeef,cpr11 + stqc cpr8,@(sp,gr7) ; non parallel + test_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xdead,sp + inc_gr_immed 4,sp + test_mem_limmed 0xbeef,0xbeef,sp + + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xbeef,sp + set_gr_immed 0,gr7 + set_cpr_limmed 0xbeef,0xdead,cpr8 + set_cpr_limmed 0xdead,0xbeef,cpr9 + set_cpr_limmed 0xdead,0xdead,cpr10 + set_cpr_limmed 0xbeef,0xbeef,cpr11 + stqc.p cpr8,@(sp,gr7) ; parallel + addi sp,4,sp + subi sp,4,sp + ldqc @(sp,gr7),cpr12 + test_mem_limmed 0xbeef,0xdead,sp ; memory is set + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xdead,sp + inc_gr_immed 4,sp + test_mem_limmed 0xbeef,0xbeef,sp + test_cpr_limmed 0xbeef,0xdead,cpr12 + test_cpr_limmed 0xdead,0xbeef,cpr13 + test_cpr_limmed 0xdead,0xdead,cpr14 + test_cpr_limmed 0xbeef,0xbeef,cpr15 + + pass diff --git a/sim/testsuite/sim/frv/stqcu.cgs b/sim/testsuite/sim/frv/stqcu.cgs new file mode 100644 index 0000000..a7746ca --- /dev/null +++ b/sim/testsuite/sim/frv/stqcu.cgs @@ -0,0 +1,66 @@ +# frv testcase for stqcu $CPRk,@($GRi,$GRj) +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global stqcu +stqcu: + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xbeef,sp + set_gr_gr sp,gr20 + set_gr_immed 0,gr7 + set_cpr_limmed 0xbeef,0xdead,cpr8 + set_cpr_limmed 0xdead,0xbeef,cpr9 + set_cpr_limmed 0xdead,0xdead,cpr10 + set_cpr_limmed 0xbeef,0xbeef,cpr11 + stqcu cpr8,@(sp,gr7) + test_gr_gr sp,gr20 + test_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xdead,sp + inc_gr_immed 4,sp + test_mem_limmed 0xbeef,0xbeef,sp + + inc_gr_immed -28,sp + set_gr_immed 16,gr7 + set_cpr_limmed 0x1111,0x1111,cpr8 + set_cpr_limmed 0x2222,0x2222,cpr9 + set_cpr_limmed 0x3333,0x3333,cpr10 + set_cpr_limmed 0x4444,0x4444,cpr11 + stqcu cpr8,@(sp,gr7) + test_gr_gr sp,gr20 + test_mem_limmed 0x1111,0x1111,sp + inc_gr_immed 4,sp + test_mem_limmed 0x2222,0x2222,sp + inc_gr_immed 4,sp + test_mem_limmed 0x3333,0x3333,sp + inc_gr_immed 4,sp + test_mem_limmed 0x4444,0x4444,sp + + inc_gr_immed 4,sp + set_gr_immed -16,gr7 + set_cpr_limmed 0x5555,0x5555,cpr8 + set_cpr_limmed 0x6666,0x6666,cpr9 + set_cpr_limmed 0x7777,0x7777,cpr10 + set_cpr_limmed 0x8888,0x8888,cpr11 + stqcu cpr8,@(sp,gr7) + test_gr_gr sp,gr20 + test_mem_limmed 0x5555,0x5555,sp + inc_gr_immed 4,sp + test_mem_limmed 0x6666,0x6666,sp + inc_gr_immed 4,sp + test_mem_limmed 0x7777,0x7777,sp + inc_gr_immed 4,sp + test_mem_limmed 0x8888,0x8888,sp + + pass diff --git a/sim/testsuite/sim/frv/stqf.cgs b/sim/testsuite/sim/frv/stqf.cgs new file mode 100644 index 0000000..24dbb42 --- /dev/null +++ b/sim/testsuite/sim/frv/stqf.cgs @@ -0,0 +1,32 @@ +# frv testcase for stqf $GRk,@($GRi,$GRj) +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global stqf +stqf: + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xbeef,sp + set_gr_immed 0,gr7 + set_fr_iimmed 0xbeef,0xdead,fr8 + set_fr_iimmed 0xdead,0xbeef,fr9 + set_fr_iimmed 0xdead,0xdead,fr10 + set_fr_iimmed 0xbeef,0xbeef,fr11 + stqf fr8,@(sp,gr7) + test_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xdead,sp + inc_gr_immed 4,sp + test_mem_limmed 0xbeef,0xbeef,sp + + pass diff --git a/sim/testsuite/sim/frv/stqf.pcgs b/sim/testsuite/sim/frv/stqf.pcgs new file mode 100644 index 0000000..497f5fb --- /dev/null +++ b/sim/testsuite/sim/frv/stqf.pcgs @@ -0,0 +1,59 @@ +# frv parallel testcase for stqf $GRk,@($GRi,$GRj) +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global stqf +stqf: + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xbeef,sp + set_gr_immed 0,gr7 + set_fr_iimmed 0xbeef,0xdead,fr8 + set_fr_iimmed 0xdead,0xbeef,fr9 + set_fr_iimmed 0xdead,0xdead,fr10 + set_fr_iimmed 0xbeef,0xbeef,fr11 + stqf fr8,@(sp,gr7) ; non-parallel + test_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xdead,sp + inc_gr_immed 4,sp + test_mem_limmed 0xbeef,0xbeef,sp + + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xbeef,sp + set_gr_immed 0,gr7 + set_fr_iimmed 0xbeef,0xdead,fr8 + set_fr_iimmed 0xdead,0xbeef,fr9 + set_fr_iimmed 0xdead,0xdead,fr10 + set_fr_iimmed 0xbeef,0xbeef,fr11 + stqf.p fr8,@(sp,gr7) ; parallel + fnegs fr8,fr8 + ldqf @(sp,gr7),fr12 + test_mem_limmed 0xbeef,0xdead,sp ; memory is set + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xdead,sp + inc_gr_immed 4,sp + test_mem_limmed 0xbeef,0xbeef,sp + test_fr_iimmed 0xbeefdead,fr12 + test_fr_iimmed 0xdeadbeef,fr13 + test_fr_iimmed 0xdeaddead,fr14 + test_fr_iimmed 0xbeefbeef,fr15 + + pass diff --git a/sim/testsuite/sim/frv/stqfi.cgs b/sim/testsuite/sim/frv/stqfi.cgs new file mode 100644 index 0000000..6a36a90 --- /dev/null +++ b/sim/testsuite/sim/frv/stqfi.cgs @@ -0,0 +1,95 @@ +# frv testcase for stqfi $FRk,@($GRi,$GRj) +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global stqfi +stqfi: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr10 + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_gr sp,gr11 + inc_gr_immed -4,sp + set_mem_limmed 0x1234,0x5678,sp + set_gr_gr sp,gr12 + inc_gr_immed -4,sp + set_mem_limmed 0x8765,0x4321,sp + set_gr_gr sp,gr13 + inc_gr_immed -4,sp + set_mem_limmed 0xfedc,0xba98,sp + set_gr_gr sp,gr14 + inc_gr_immed -4,sp + set_mem_limmed 0x89ab,0xcdef,sp + set_gr_gr sp,gr15 + inc_gr_immed -4,sp + set_mem_limmed 0x2345,0x6789,sp + set_gr_gr sp,gr16 + inc_gr_immed -4,sp + set_mem_limmed 0x9876,0x5432,sp + set_gr_gr sp,gr17 + inc_gr_immed -4,sp + set_mem_limmed 0x3456,0x789a,sp + set_gr_gr sp,gr18 + inc_gr_immed -4,sp + set_mem_limmed 0xa987,0x6543,sp + set_gr_gr sp,gr19 + inc_gr_immed -4,sp + set_mem_limmed 0x4567,0x89ab,sp + set_gr_gr sp,gr20 + inc_gr_immed -4,sp + set_mem_limmed 0xba98,0x7654,sp + set_gr_gr sp,gr21 + set_fr_iimmed 0xffff,0xffff,fr8 + set_fr_iimmed 0xeeee,0xeeee,fr9 + set_fr_iimmed 0xdddd,0xdddd,fr10 + set_fr_iimmed 0xcccc,0xcccc,fr11 + + stqfi fr8,@(sp,0) + test_mem_limmed 0xffff,0xffff,gr21 + test_mem_limmed 0xeeee,0xeeee,gr20 + test_mem_limmed 0xdddd,0xdddd,gr19 + test_mem_limmed 0xcccc,0xcccc,gr18 + test_mem_limmed 0x9876,0x5432,gr17 + test_mem_limmed 0x2345,0x6789,gr16 + test_mem_limmed 0x89ab,0xcdef,gr15 + test_mem_limmed 0xfedc,0xba98,gr14 + test_mem_limmed 0x8765,0x4321,gr13 + test_mem_limmed 0x1234,0x5678,gr12 + test_mem_limmed 0xbeef,0xdead,gr11 + test_mem_limmed 0xdead,0xbeef,gr10 + + inc_gr_immed 0x810,sp ; 2064 + stqfi fr8,@(sp,-2048) + test_mem_limmed 0xffff,0xffff,gr21 + test_mem_limmed 0xeeee,0xeeee,gr20 + test_mem_limmed 0xdddd,0xdddd,gr19 + test_mem_limmed 0xcccc,0xcccc,gr18 + test_mem_limmed 0xffff,0xffff,gr17 + test_mem_limmed 0xeeee,0xeeee,gr16 + test_mem_limmed 0xdddd,0xdddd,gr15 + test_mem_limmed 0xcccc,0xcccc,gr14 + test_mem_limmed 0x8765,0x4321,gr13 + test_mem_limmed 0x1234,0x5678,gr12 + test_mem_limmed 0xbeef,0xdead,gr11 + test_mem_limmed 0xdead,0xbeef,gr10 + + inc_gr_immed -4064,sp + stqfi fr8,@(sp,0x7f0) + test_mem_limmed 0xffff,0xffff,gr21 + test_mem_limmed 0xeeee,0xeeee,gr20 + test_mem_limmed 0xdddd,0xdddd,gr19 + test_mem_limmed 0xcccc,0xcccc,gr18 + test_mem_limmed 0xffff,0xffff,gr17 + test_mem_limmed 0xeeee,0xeeee,gr16 + test_mem_limmed 0xdddd,0xdddd,gr15 + test_mem_limmed 0xcccc,0xcccc,gr14 + test_mem_limmed 0xffff,0xffff,gr13 + test_mem_limmed 0xeeee,0xeeee,gr12 + test_mem_limmed 0xdddd,0xdddd,gr11 + test_mem_limmed 0xcccc,0xcccc,gr10 + + pass diff --git a/sim/testsuite/sim/frv/stqfu.cgs b/sim/testsuite/sim/frv/stqfu.cgs new file mode 100644 index 0000000..80a1494 --- /dev/null +++ b/sim/testsuite/sim/frv/stqfu.cgs @@ -0,0 +1,35 @@ +# frv testcase for stqfu $FRk,@($GRi,$GRj) +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global stqfu +stqfu: + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xbeef,sp + set_gr_gr sp,gr20 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + set_fr_iimmed 0xbeef,0xdead,fr8 + set_fr_iimmed 0xdead,0xbeef,fr9 + set_fr_iimmed 0xdead,0xdead,fr10 + set_fr_iimmed 0xbeef,0xbeef,fr11 + stqfu fr8,@(sp,gr7) + test_gr_gr sp,gr20 + test_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xdead,sp + inc_gr_immed 4,sp + test_mem_limmed 0xbeef,0xbeef,sp + + pass diff --git a/sim/testsuite/sim/frv/stqi.cgs b/sim/testsuite/sim/frv/stqi.cgs new file mode 100644 index 0000000..5a3680e --- /dev/null +++ b/sim/testsuite/sim/frv/stqi.cgs @@ -0,0 +1,95 @@ +# frv testcase for stqi $GRk,@($GRi,$GRj) +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global stqi +stqi: + set_mem_limmed 0xdead,0xbeef,sp + set_gr_gr sp,gr10 + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xdead,sp + set_gr_gr sp,gr11 + inc_gr_immed -4,sp + set_mem_limmed 0x1234,0x5678,sp + set_gr_gr sp,gr12 + inc_gr_immed -4,sp + set_mem_limmed 0x8765,0x4321,sp + set_gr_gr sp,gr13 + inc_gr_immed -4,sp + set_mem_limmed 0xfedc,0xba98,sp + set_gr_gr sp,gr14 + inc_gr_immed -4,sp + set_mem_limmed 0x89ab,0xcdef,sp + set_gr_gr sp,gr15 + inc_gr_immed -4,sp + set_mem_limmed 0x2345,0x6789,sp + set_gr_gr sp,gr16 + inc_gr_immed -4,sp + set_mem_limmed 0x9876,0x5432,sp + set_gr_gr sp,gr17 + inc_gr_immed -4,sp + set_mem_limmed 0x3456,0x789a,sp + set_gr_gr sp,gr18 + inc_gr_immed -4,sp + set_mem_limmed 0xa987,0x6543,sp + set_gr_gr sp,gr19 + inc_gr_immed -4,sp + set_mem_limmed 0x4567,0x89ab,sp + set_gr_gr sp,gr20 + inc_gr_immed -4,sp + set_mem_limmed 0xba98,0x7654,sp + set_gr_gr sp,gr21 + set_gr_limmed 0xffff,0xffff,gr4 + set_gr_limmed 0xeeee,0xeeee,gr5 + set_gr_limmed 0xdddd,0xdddd,gr6 + set_gr_limmed 0xcccc,0xcccc,gr7 + + stqi gr4,@(sp,0) + test_mem_limmed 0xffff,0xffff,gr21 + test_mem_limmed 0xeeee,0xeeee,gr20 + test_mem_limmed 0xdddd,0xdddd,gr19 + test_mem_limmed 0xcccc,0xcccc,gr18 + test_mem_limmed 0x9876,0x5432,gr17 + test_mem_limmed 0x2345,0x6789,gr16 + test_mem_limmed 0x89ab,0xcdef,gr15 + test_mem_limmed 0xfedc,0xba98,gr14 + test_mem_limmed 0x8765,0x4321,gr13 + test_mem_limmed 0x1234,0x5678,gr12 + test_mem_limmed 0xbeef,0xdead,gr11 + test_mem_limmed 0xdead,0xbeef,gr10 + + inc_gr_immed 0x810,sp ; 2064 + stqi gr4,@(sp,-2048) + test_mem_limmed 0xffff,0xffff,gr21 + test_mem_limmed 0xeeee,0xeeee,gr20 + test_mem_limmed 0xdddd,0xdddd,gr19 + test_mem_limmed 0xcccc,0xcccc,gr18 + test_mem_limmed 0xffff,0xffff,gr17 + test_mem_limmed 0xeeee,0xeeee,gr16 + test_mem_limmed 0xdddd,0xdddd,gr15 + test_mem_limmed 0xcccc,0xcccc,gr14 + test_mem_limmed 0x8765,0x4321,gr13 + test_mem_limmed 0x1234,0x5678,gr12 + test_mem_limmed 0xbeef,0xdead,gr11 + test_mem_limmed 0xdead,0xbeef,gr10 + + inc_gr_immed -4064,sp + stqi gr4,@(sp,0x7f0) + test_mem_limmed 0xffff,0xffff,gr21 + test_mem_limmed 0xeeee,0xeeee,gr20 + test_mem_limmed 0xdddd,0xdddd,gr19 + test_mem_limmed 0xcccc,0xcccc,gr18 + test_mem_limmed 0xffff,0xffff,gr17 + test_mem_limmed 0xeeee,0xeeee,gr16 + test_mem_limmed 0xdddd,0xdddd,gr15 + test_mem_limmed 0xcccc,0xcccc,gr14 + test_mem_limmed 0xffff,0xffff,gr13 + test_mem_limmed 0xeeee,0xeeee,gr12 + test_mem_limmed 0xdddd,0xdddd,gr11 + test_mem_limmed 0xcccc,0xcccc,gr10 + + pass diff --git a/sim/testsuite/sim/frv/stqu.cgs b/sim/testsuite/sim/frv/stqu.cgs new file mode 100644 index 0000000..31e8de5 --- /dev/null +++ b/sim/testsuite/sim/frv/stqu.cgs @@ -0,0 +1,35 @@ +# frv testcase for stqu $GRk,@($GRi,$GRj) +# mach: frv +# as(frv): -mcpu=frv + + .include "testutils.inc" + + start + + .global stqu +stqu: + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_mem_limmed 0xdead,0xdead,sp + inc_gr_immed -4,sp + set_mem_limmed 0xbeef,0xbeef,sp + set_gr_gr sp,gr20 + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_limmed 0xdead,0xbeef,gr9 + set_gr_limmed 0xdead,0xdead,gr10 + set_gr_limmed 0xbeef,0xbeef,gr11 + stqu gr8,@(sp,gr7) + test_gr_gr sp,gr20 + test_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed 4,sp + test_mem_limmed 0xdead,0xdead,sp + inc_gr_immed 4,sp + test_mem_limmed 0xbeef,0xbeef,sp + + pass diff --git a/sim/testsuite/sim/frv/stu.cgs b/sim/testsuite/sim/frv/stu.cgs new file mode 100644 index 0000000..cc48040 --- /dev/null +++ b/sim/testsuite/sim/frv/stu.cgs @@ -0,0 +1,19 @@ +# frv testcase for stu $GRk,@($GRi,$GRj) +# mach: all + + .include "testutils.inc" + + start + + .global stu +stu: + set_gr_gr sp,gr9 + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_gr_immed 4,gr7 + set_gr_limmed 0xffff,0xffff,gr8 + stu gr8,@(sp,gr7) + test_mem_limmed 0xffff,0xffff,sp + test_gr_gr sp,gr9 + + pass diff --git a/sim/testsuite/sim/frv/sub.cgs b/sim/testsuite/sim/frv/sub.cgs new file mode 100644 index 0000000..5a1410c --- /dev/null +++ b/sim/testsuite/sim/frv/sub.cgs @@ -0,0 +1,26 @@ +# frv testcase for sub $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global sub +sub: + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + sub gr8,gr7,gr8 + test_gr_immed 1,gr8 + + set_gr_immed 1,gr7 + set_gr_limmed 0x8000,0x0000,gr8 + sub gr8,gr7,gr8 + test_gr_limmed 0x7fff,0xffff,gr8 + + sub gr8,gr8,gr8 + test_gr_immed 0,gr8 + + sub gr8,gr7,gr8 + test_gr_immed -1,gr8 + + pass diff --git a/sim/testsuite/sim/frv/subcc.cgs b/sim/testsuite/sim/frv/subcc.cgs new file mode 100644 index 0000000..188e0ff --- /dev/null +++ b/sim/testsuite/sim/frv/subcc.cgs @@ -0,0 +1,34 @@ +# frv testcase for subcc $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global subcc +subcc: + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + subcc gr8,gr7,gr8,icc0 + test_icc 0 0 0 0 icc0 + test_gr_immed 1,gr8 + + set_gr_immed 1,gr7 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0d,0 ; Set mask opposite of expected + subcc gr8,gr7,gr8,icc0 + test_icc 0 0 1 0 icc0 + test_gr_limmed 0x7fff,0xffff,gr8 + + set_icc 0x0b,0 ; Set mask opposite of expected + subcc gr8,gr8,gr8,icc0 + test_icc 0 1 0 0 icc0 + test_gr_immed 0,gr8 + + set_icc 0x06,0 ; Set mask opposite of expected + subcc gr8,gr7,gr8,icc0 + test_icc 1 0 0 1 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + + pass diff --git a/sim/testsuite/sim/frv/subi.cgs b/sim/testsuite/sim/frv/subi.cgs new file mode 100644 index 0000000..c632838 --- /dev/null +++ b/sim/testsuite/sim/frv/subi.cgs @@ -0,0 +1,56 @@ +# frv testcase for subi $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global subi +subi: + set_gr_immed 2,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + subi gr8,1,gr8 + test_icc 1 1 1 1 icc0 + test_gr_immed 1,gr8 + + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0d,0 ; Set mask opposite of expected + subi gr8,1,gr8 + test_icc 1 1 0 1 icc0 + test_gr_limmed 0x7fff,0xffff,gr8 + + set_gr_immed 0x7ff,gr8 + set_icc 0x0b,0 ; Set mask opposite of expected + subi gr8,0x7ff,gr8 + test_icc 1 0 1 1 icc0 + test_gr_immed 0,gr8 + + set_icc 0x06,0 ; Set mask opposite of expected + subi gr8,1,gr8 + test_icc 0 1 1 0 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + + set_gr_immed 2,gr8 + set_icc 0x0e,0 ; Set mask opposite of expected + subi gr8,-1,gr8 + test_icc 1 1 1 0 icc0 + test_gr_immed 3,gr8 + + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x06,0 ; Set mask opposite of expected + subi gr8,-1,gr8 + test_icc 0 1 1 0 icc0 + test_gr_limmed 0x8000,0x0001,gr8 + + set_gr_immed -2048,gr8 + set_icc 0x0b,0 ; Set mask opposite of expected + subi gr8,-2048,gr8 + test_icc 1 0 1 1 icc0 + test_gr_immed 0,gr8 + + set_icc 0x0e,0 ; Set mask opposite of expected + subi gr8,-1,gr8 + test_icc 1 1 1 0 icc0 + test_gr_immed 1,gr8 + + pass diff --git a/sim/testsuite/sim/frv/subicc.cgs b/sim/testsuite/sim/frv/subicc.cgs new file mode 100644 index 0000000..b2296ee --- /dev/null +++ b/sim/testsuite/sim/frv/subicc.cgs @@ -0,0 +1,56 @@ +# frv testcase for subicc $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global subicc +subicc: + set_gr_immed 2,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + subicc gr8,1,gr8,icc0 + test_icc 0 0 0 0 icc0 + test_gr_immed 1,gr8 + + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0d,0 ; Set mask opposite of expected + subicc gr8,1,gr8,icc0 + test_icc 0 0 1 0 icc0 + test_gr_limmed 0x7fff,0xffff,gr8 + + set_gr_immed 0x1ff,gr8 + set_icc 0x0b,0 ; Set mask opposite of expected + subicc gr8,0x1ff,gr8,icc0 + test_icc 0 1 0 0 icc0 + test_gr_immed 0,gr8 + + set_icc 0x06,0 ; Set mask opposite of expected + subicc gr8,1,gr8,icc0 + test_icc 1 0 0 1 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + + set_gr_immed 2,gr8 + set_icc 0x0e,0 ; Set mask opposite of expected + subicc gr8,-1,gr8,icc0 + test_icc 0 0 0 1 icc0 + test_gr_immed 3,gr8 + + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x06,0 ; Set mask opposite of expected + subicc gr8,-1,gr8,icc0 + test_icc 1 0 0 1 icc0 + test_gr_limmed 0x8000,0x0001,gr8 + + set_gr_immed -512,gr8 + set_icc 0x0b,0 ; Set mask opposite of expected + subicc gr8,-512,gr8,icc0 + test_icc 0 1 0 0 icc0 + test_gr_immed 0,gr8 + + set_icc 0x0e,0 ; Set mask opposite of expected + subicc gr8,-1,gr8,icc0 + test_icc 0 0 0 1 icc0 + test_gr_immed 1,gr8 + + pass diff --git a/sim/testsuite/sim/frv/subx.cgs b/sim/testsuite/sim/frv/subx.cgs new file mode 100644 index 0000000..4559a52 --- /dev/null +++ b/sim/testsuite/sim/frv/subx.cgs @@ -0,0 +1,60 @@ +# frv testcase for subx $GRi,$GRj,$GRk,$ICCi_1 +# mach: all + + .include "testutils.inc" + + start + + .global subx +subx: + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + set_icc 0x0e,0 ; Make sure carry is off + subx gr8,gr7,gr8,icc0 + test_icc 1 1 1 0 icc0 + test_gr_immed 1,gr8 + + set_gr_immed 1,gr7 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0c,0 ; Make sure carry is off + subx gr8,gr7,gr8,icc0 + test_icc 1 1 0 0 icc0 + test_gr_limmed 0x7fff,0xffff,gr8 + + set_icc 0x0a,0 ; Make sure carry is off + subx gr8,gr8,gr8,icc0 + test_icc 1 0 1 0 icc0 + test_gr_immed 0,gr8 + + set_icc 0x06,0 ; Make sure carry is off + subx gr8,gr7,gr8,icc0 + test_icc 0 1 1 0 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + + set_gr_immed 1,gr7 + set_gr_immed 3,gr8 + set_icc 0x0f,0 ; Make sure carry is on + subx gr8,gr7,gr8,icc0 + test_icc 1 1 1 1 icc0 + test_gr_immed 1,gr8 + + set_gr_immed 0,gr7 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0d,0 ; Make sure carry is on + subx gr8,gr7,gr8,icc0 + test_icc 1 1 0 1 icc0 + test_gr_limmed 0x7fff,0xffff,gr8 + + set_gr_limmed 0x7fff,0xfffe,gr7 + set_icc 0x0b,0 ; Make sure carry is on + subx gr8,gr7,gr8,icc0 + test_icc 1 0 1 1 icc0 + test_gr_immed 0,gr8 + + set_gr_immed 0,gr7 + set_icc 0x07,0 ; Make sure carry is on + subx gr8,gr7,gr8,icc0 + test_icc 0 1 1 1 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + + pass diff --git a/sim/testsuite/sim/frv/subxcc.cgs b/sim/testsuite/sim/frv/subxcc.cgs new file mode 100644 index 0000000..713a2a7 --- /dev/null +++ b/sim/testsuite/sim/frv/subxcc.cgs @@ -0,0 +1,60 @@ +# frv testcase for subxcc $GRi,$GRj,$GRk,$ICCi_1 +# mach: all + + .include "testutils.inc" + + start + + .global subxcc +subxcc: + set_gr_immed 1,gr7 + set_gr_immed 2,gr8 + set_icc 0x0e,0 ; Make sure carry is off + subxcc gr8,gr7,gr8,icc0 + test_icc 0 0 0 0 icc0 + test_gr_immed 1,gr8 + + set_gr_immed 1,gr7 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0c,0 ; Make sure carry is off + subxcc gr8,gr7,gr8,icc0 + test_icc 0 0 1 0 icc0 + test_gr_limmed 0x7fff,0xffff,gr8 + + set_icc 0x0a,0 ; Make sure carry is off + subxcc gr8,gr8,gr8,icc0 + test_icc 0 1 0 0 icc0 + test_gr_immed 0,gr8 + + set_icc 0x06,0 ; Make sure carry is off + subxcc gr8,gr7,gr8,icc0 + test_icc 1 0 0 1 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + + set_gr_immed 1,gr7 + set_gr_immed 3,gr8 + set_icc 0x0f,0 ; Make sure carry is on + subxcc gr8,gr7,gr8,icc0 + test_icc 0 0 0 0 icc0 + test_gr_immed 1,gr8 + + set_gr_immed 0,gr7 + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0d,0 ; Make sure carry is on + subxcc gr8,gr7,gr8,icc0 + test_icc 0 0 1 0 icc0 + test_gr_limmed 0x7fff,0xffff,gr8 + + set_gr_limmed 0x7fff,0xfffe,gr7 + set_icc 0x0b,0 ; Make sure carry is on + subxcc gr8,gr7,gr8,icc0 + test_icc 0 1 0 0 icc0 + test_gr_immed 0,gr8 + + set_gr_immed 0,gr7 + set_icc 0x07,0 ; Make sure carry is on + subxcc gr8,gr7,gr8,icc0 + test_icc 1 0 0 1 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + + pass diff --git a/sim/testsuite/sim/frv/subxi.cgs b/sim/testsuite/sim/frv/subxi.cgs new file mode 100644 index 0000000..bbe8e4d --- /dev/null +++ b/sim/testsuite/sim/frv/subxi.cgs @@ -0,0 +1,61 @@ +# frv testcase for subxi $GRi,$GRj,$GRk,$ICCi_1 +# mach: all + + .include "testutils.inc" + + start + + .global subxi +subxi: + set_gr_immed 2,gr8 + set_icc 0x0e,0 ; Make sure carry is off + subxi gr8,1,gr8,icc0 + test_icc 1 1 1 0 icc0 + test_gr_immed 1,gr8 + + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0c,0 ; Make sure carry is off + subxi gr8,1,gr8,icc0 + test_icc 1 1 0 0 icc0 + test_gr_limmed 0x7fff,0xffff,gr8 + + set_gr_immed 0x1ff,gr8 + set_icc 0x0a,0 ; Make sure carry is off + subxi gr8,0x1ff,gr8,icc0 + test_icc 1 0 1 0 icc0 + test_gr_immed 0,gr8 + + set_icc 0x06,0 ; Make sure carry is off + subxi gr8,1,gr8,icc0 + test_icc 0 1 1 0 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + + set_gr_immed 3,gr8 + set_icc 0x0f,0 ; Make sure carry is on + subxi gr8,1,gr8,icc0 + test_icc 1 1 1 1 icc0 + test_gr_immed 1,gr8 + + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0d,0 ; Make sure carry is on + subxi gr8,0,gr8,icc0 + test_icc 1 1 0 1 icc0 + test_gr_limmed 0x7fff,0xffff,gr8 + + set_gr_immed 0x200,gr8 + set_icc 0x0b,0 ; Make sure carry is on + subxi gr8,0x1ff,gr8,icc0 + test_icc 1 0 1 1 icc0 + test_gr_immed 0,gr8 + + set_icc 0x07,0 ; Make sure carry is on + subxi gr8,0,gr8,icc0 + test_icc 0 1 1 1 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + + set_icc 0x07,0 ; Make sure carry is on + subxi gr8,-512,gr8,icc0 + test_icc 0 1 1 1 icc0 + test_gr_immed 510,gr8 + + pass diff --git a/sim/testsuite/sim/frv/subxicc.cgs b/sim/testsuite/sim/frv/subxicc.cgs new file mode 100644 index 0000000..369cab9 --- /dev/null +++ b/sim/testsuite/sim/frv/subxicc.cgs @@ -0,0 +1,61 @@ +# frv testcase for subxicc $GRi,$GRj,$GRk,$ICCi_1 +# mach: all + + .include "testutils.inc" + + start + + .global subxicc +subxicc: + set_gr_immed 2,gr8 + set_icc 0x0e,0 ; Make sure carry is off + subxicc gr8,1,gr8,icc0 + test_icc 0 0 0 0 icc0 + test_gr_immed 1,gr8 + + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0c,0 ; Make sure carry is off + subxicc gr8,1,gr8,icc0 + test_icc 0 0 1 0 icc0 + test_gr_limmed 0x7fff,0xffff,gr8 + + set_gr_immed 0x1ff,gr8 + set_icc 0x0a,0 ; Make sure carry is off + subxicc gr8,0x1ff,gr8,icc0 + test_icc 0 1 0 0 icc0 + test_gr_immed 0,gr8 + + set_icc 0x06,0 ; Make sure carry is off + subxicc gr8,1,gr8,icc0 + test_icc 1 0 0 1 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + + set_gr_immed 3,gr8 + set_icc 0x0f,0 ; Make sure carry is on + subxicc gr8,1,gr8,icc0 + test_icc 0 0 0 0 icc0 + test_gr_immed 1,gr8 + + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0d,0 ; Make sure carry is on + subxicc gr8,0,gr8,icc0 + test_icc 0 0 1 0 icc0 + test_gr_limmed 0x7fff,0xffff,gr8 + + set_gr_immed 0x200,gr8 + set_icc 0x0b,0 ; Make sure carry is on + subxicc gr8,0x1ff,gr8,icc0 + test_icc 0 1 0 0 icc0 + test_gr_immed 0,gr8 + + set_icc 0x07,0 ; Make sure carry is on + subxicc gr8,0,gr8,icc0 + test_icc 1 0 0 1 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + + set_icc 0x07,0 ; Make sure carry is on + subxicc gr8,-512,gr8,icc0 + test_icc 0 0 0 0 icc0 + test_gr_immed 510,gr8 + + pass diff --git a/sim/testsuite/sim/frv/swap.cgs b/sim/testsuite/sim/frv/swap.cgs new file mode 100644 index 0000000..1e22903 --- /dev/null +++ b/sim/testsuite/sim/frv/swap.cgs @@ -0,0 +1,42 @@ +# frv testcase for swap @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global swap +swap: + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_gr_gr sp,gr21 + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_gr_gr sp,gr22 + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed 4,sp + + set_gr_limmed 0xbeef,0xdead,gr8 + set_gr_immed -4,gr7 + swap @(sp,gr7),gr8 + test_gr_limmed 0xdead,0xbeef,gr8 + test_mem_limmed 0xbeef,0xdead,gr22 + test_mem_limmed 0xbeef,0xdead,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_immed 0,gr7 + swap @(sp,gr7),gr8 + test_gr_limmed 0xbeef,0xdead,gr8 + test_mem_limmed 0xbeef,0xdead,gr22 + test_mem_limmed 0xdead,0xbeef,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + set_gr_immed 4,gr7 + swap @(sp,gr7),gr8 + test_gr_limmed 0xdead,0xbeef,gr8 + test_mem_limmed 0xbeef,0xdead,gr22 + test_mem_limmed 0xdead,0xbeef,gr21 + test_mem_limmed 0xbeef,0xdead,gr20 + + pass diff --git a/sim/testsuite/sim/frv/swapi.cgs b/sim/testsuite/sim/frv/swapi.cgs new file mode 100644 index 0000000..4951bfa --- /dev/null +++ b/sim/testsuite/sim/frv/swapi.cgs @@ -0,0 +1,39 @@ +# frv testcase for swapi @($GRi,$GRj),$GRk +# mach: all + + .include "testutils.inc" + + start + + .global swapi +swapi: + set_gr_gr sp,gr20 + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed -4,sp + set_gr_gr sp,gr21 + set_mem_limmed 0xbeef,0xdead,sp + inc_gr_immed -4,sp + set_gr_gr sp,gr22 + set_mem_limmed 0xdead,0xbeef,sp + inc_gr_immed 4,sp + + set_gr_limmed 0xbeef,0xdead,gr8 + swapi @(sp,-4),gr8 + test_gr_limmed 0xdead,0xbeef,gr8 + test_mem_limmed 0xbeef,0xdead,gr22 + test_mem_limmed 0xbeef,0xdead,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + swapi @(sp,0),gr8 + test_gr_limmed 0xbeef,0xdead,gr8 + test_mem_limmed 0xbeef,0xdead,gr22 + test_mem_limmed 0xdead,0xbeef,gr21 + test_mem_limmed 0xdead,0xbeef,gr20 + + swapi @(sp,4),gr8 + test_gr_limmed 0xdead,0xbeef,gr8 + test_mem_limmed 0xbeef,0xdead,gr22 + test_mem_limmed 0xdead,0xbeef,gr21 + test_mem_limmed 0xbeef,0xdead,gr20 + + pass diff --git a/sim/testsuite/sim/frv/tc.cgs b/sim/testsuite/sim/frv/tc.cgs new file mode 100644 index 0000000..116190b --- /dev/null +++ b/sim/testsuite/sim/frv/tc.cgs @@ -0,0 +1,101 @@ +# frv testcase for tc $ICCi_2,$GRi,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global tc +tc: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_spr_addr bad,lr + set_icc 0x0 0 + tc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok1,lr + set_icc 0x1 0 + tc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok1: + set_spr_addr bad,lr + set_icc 0x2 0 + tc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok3,lr + set_icc 0x3 0 + tc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_spr_addr bad,lr + set_icc 0x4 0 + tc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok5,lr + set_icc 0x5 0 + tc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_spr_addr bad,lr + set_icc 0x6 0 + tc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok7,lr + set_icc 0x7 0 + tc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_spr_addr bad,lr + set_icc 0x8 0 + tc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok9,lr + set_icc 0x9 0 + tc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_spr_addr bad,lr + set_icc 0xa 0 + tc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr okb,lr + set_icc 0xb 0 + tc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_spr_addr bad,lr + set_icc 0xc 0 + tc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr okd,lr + set_icc 0xd 0 + tc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_spr_addr bad,lr + set_icc 0xe 0 + tc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr okf,lr + set_icc 0xf 0 + tc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/teq.cgs b/sim/testsuite/sim/frv/teq.cgs new file mode 100644 index 0000000..59c6091 --- /dev/null +++ b/sim/testsuite/sim/frv/teq.cgs @@ -0,0 +1,101 @@ +# frv testcase for teq $ICCi_2,$GRi,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global teq +teq: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_spr_addr bad,lr + set_icc 0x0 0 + teq icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x1 0 + teq icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x2 0 + teq icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x3 0 + teq icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok4,lr + set_icc 0x4 0 + teq icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok4: + set_psr_et 1 + set_spr_addr ok5,lr + set_icc 0x5 0 + teq icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_psr_et 1 + set_spr_addr ok6,lr + set_icc 0x6 0 + teq icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_icc 0x7 0 + teq icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_spr_addr bad,lr + set_icc 0x8 0 + teq icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x9 0 + teq icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xa 0 + teq icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xb 0 + teq icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr okc,lr + set_icc 0xc 0 + teq icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_icc 0xd 0 + teq icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_icc 0xe 0 + teq icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_icc 0xf 0 + teq icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/testutils.inc b/sim/testsuite/sim/frv/testutils.inc new file mode 100644 index 0000000..8261b4fa --- /dev/null +++ b/sim/testsuite/sim/frv/testutils.inc @@ -0,0 +1,656 @@ +# gr28-gr31, fr31, icc3, fcc3 are used as tmps. +# consider them call clobbered by these macros. + + .macro start + .data +failmsg: + .ascii "fail\n" +passmsg: + .ascii "pass\n" + .text + .global _start +_start: + ; enable data and insn caches in copy-back mode + ; Also enable all registers + or_spr_immed 0xc80003c0,hsr0 + and_spr_immed 0xfffff3ff,hsr0 + + ; turn on psr.nem, psr.cm, psr.ef, psr.em, psr.esr, + ; disable external interrupts + or_spr_immed 0x69f8,psr + + ; If fsr exists, enable all fp_exceptions except inexact + movsg psr,gr28 + srli gr28,28,gr28 + subicc gr28,0x2,gr0,icc3 ; is fr400? + beq icc3,0,nofsr0 + or_spr_immed 0x3d000000,fsr0 +nofsr0: + + ; Set the stack pointer + sethi.p 0x7,sp + setlo 0xfffc,sp ; TODO -- what's a good value for this? + + ; Set the TBR address + sethi.p 0xf,gr28 + setlo 0xf000,gr28 + movgs gr28,tbr ; TODO -- what's a good value for this? + + ; Go to user mode -- causes too many problems + ;and_spr_immed 0xfffffffb,psr + .endm + +; Set GR with another GR + .macro set_gr_gr src targ + addi \src,0,\targ + .endm + +; Set GR with immediate value + .macro set_gr_immed val reg + .if (\val >= -32768) && (\val <= 23767) + setlos \val,\reg + .else + setlo.p %lo(\val),\reg + sethi %hi(\val),\reg + .endif + .endm + + .macro set_gr_limmed valh vall reg + sethi.p \valh,\reg + setlo \vall,\reg + .endm + +; Set GR with address value + .macro set_gr_addr addr reg + sethi.p %hi(\addr),\reg + setlo %lo(\addr),\reg + .endm + +; Set GR with SPR + .macro set_gr_spr src targ + movsg \src,\targ + .endm + +; Set GR with a value from memory + .macro set_gr_mem addr reg + set_gr_addr \addr,gr28 + ldi @(gr28,0),\reg + .endm + +; Increment GR with immediate value + .macro inc_gr_immed val reg + .if (\val >= -2048) && (\val <= 2047) + addi \reg,\val,\reg + .else + set_gr_immed \val,gr28 + add \reg,gr28,\reg + .endif + .endm + +; AND GR with immediate value + .macro and_gr_immed val reg + .if (\val >= -2048) && (\val <= 2047) + andi \reg,\val,\reg + .else + set_gr_immed \val,gr28 + and \reg,gr28,\reg + .endif + .endm + +; OR GR with immediate value + .macro or_gr_immed val reg + .if (\val >= -2048) && (\val <= 2047) + ori \reg,\val,\reg + .else + set_gr_immed \val,gr28 + or \reg,gr28,\reg + .endif + .endm + +; Set FR with another FR + .macro set_fr_fr src targ + fmovs \src,\targ + .endm + +; Set FR with integer immediate value + .macro set_fr_iimmed valh vall reg + set_gr_limmed \valh,\vall,gr28 + movgf gr28,\reg + .endm + +; Set FR with integer immediate value + .macro set_fr_immed val reg + set_gr_immed \val,gr28 + movgf gr28,\reg + .endm + +; Set FR with a value from memory + .macro set_fr_mem addr reg + set_gr_addr \addr,gr28 + ldfi @(gr28,0),\reg + .endm + +; Set double FR with another double FR + .macro set_dfr_dfr src targ + fmovd \src,\targ + .endm + +; Set double FR with a value from memory + .macro set_dfr_mem addr reg + set_gr_addr \addr,gr28 + lddfi @(gr28,0),\reg + .endm + +; Set CPR with immediate value + .macro set_cpr_immed val reg + addi sp,-4,gr28 + set_gr_immed \val,gr29 + st gr29,@(gr28,gr0) + ldc @(gr28,gr0),\reg + .endm + + .macro set_cpr_limmed valh vall reg + addi sp,-4,gr28 + set_gr_limmed \valh,\vall,gr29 + st gr29,@(gr28,gr0) + ldc @(gr28,gr0),\reg + .endm + +; Set SPR with immediate value + .macro set_spr_immed val reg + set_gr_immed \val,gr28 + movgs gr28,\reg + .endm + + .macro set_spr_limmed valh vall reg + set_gr_limmed \valh,\vall,gr28 + movgs gr28,\reg + .endm + + .macro set_spr_addr addr reg + set_gr_addr \addr,gr28 + movgs gr28,\reg + .endm + +; increment SPR with immediate value + .macro inc_spr_immed val reg + movsg \reg,gr28 + inc_gr_immed \val,gr28 + movgs gr28,\reg + .endm + +; OR spr with immediate value + .macro or_spr_immed val reg + movsg \reg,gr28 + set_gr_immed \val,gr29 + or gr28,gr29,gr28 + movgs gr28,\reg + .endm + +; AND spr with immediate value + .macro and_spr_immed val reg + movsg \reg,gr28 + set_gr_immed \val,gr29 + and gr28,gr29,gr28 + movgs gr28,\reg + .endm + +; Set accumulator with immediate value + .macro set_acc_immed val reg + set_fr_immed \val,fr31 + mwtacc fr31,\reg + .endm + +; Set accumulator guard with immediate value + .macro set_accg_immed val reg + set_fr_immed \val,fr31 + mwtaccg fr31,\reg + .endm + +; Set memory with immediate value + .macro set_mem_immed val base + set_gr_immed \val,gr28 + sti gr28,@(\base,0) + .endm + + .macro set_mem_limmed valh vall base + set_gr_limmed \valh,\vall,gr28 + sti gr28,@(\base,0) + .endm + +; Set memory with GR value + .macro set_mem_gr reg addr + set_gr_addr \addr,gr28 + sti \reg,@(gr28,0) + .endm + +; Test the value of a general register against another general register + .macro test_gr_gr reg1 reg2 + subcc \reg1,\reg2,gr0,icc3 + beq icc3,0,test_gr\@ + fail +test_gr\@: + .endm + +; Test the value of an immediate against a general register + .macro test_gr_immed val reg + .if (\val >= -512) && (\val <= 511) + subicc \reg,\val,gr0,icc3 + .else + set_gr_immed \val,gr28 + subcc \reg,gr28,gr0,icc3 + .endif + beq icc3,0,test_gr\@ + fail +test_gr\@: + .endm + + .macro test_gr_limmed valh vall reg + set_gr_limmed \valh,\vall,gr28 + subcc \reg,gr28,gr0,icc3 + beq icc3,0,test_gr\@ + fail +test_gr\@: + .endm + +; Test the value of an floating register against an integer immediate + .macro test_fr_limmed valh vall reg + movfg \reg,gr29 + set_gr_limmed \valh,\vall,gr28 + subcc gr29,gr28,gr0,icc3 + beq icc3,0,test_gr\@ + fail +test_gr\@: + .endm + + .macro test_fr_iimmed val reg + movfg \reg,gr29 + set_gr_immed \val,gr28 + subcc gr29,gr28,gr0,icc3 + beq icc3,0,test_gr\@ + fail +test_gr\@: + .endm + +; Test the value of a floating register against another floating point register + .macro test_fr_fr reg1 reg2 + fcmps \reg1,\reg2,fcc3 + fbeq fcc3,0,test_gr\@ + fail +test_gr\@: + .endm + +; Test the value of a double floating register against another +; double floating point register + .macro test_dfr_dfr reg1 reg2 + fcmpd \reg1,\reg2,fcc3 + fbeq fcc3,0,test_gr\@ + fail +test_gr\@: + .endm + +; Test the value of a special purpose register against an integer immediate + .macro test_spr_immed val reg + movsg \reg,gr29 + set_gr_immed \val,gr28 + subcc gr29,gr28,gr0,icc3 + beq icc3,0,test_gr\@ + fail +test_gr\@: + .endm + + .macro test_spr_limmed valh vall reg + movsg \reg,gr29 + set_gr_limmed \valh,\vall,gr28 + subcc gr29,gr28,gr0,icc3 + beq icc3,0,test_gr\@ + fail +test_gr\@: + .endm + + .macro test_spr_gr spr gr + movsg \spr,gr28 + test_gr_gr \gr,gr28 + .endm + + .macro test_spr_addr addr reg + movsg \reg,gr29 + set_gr_addr \addr,gr28 + test_gr_gr gr28,gr29 + .endm + +; Test spr bits masked and shifted against the given value + .macro test_spr_bits mask,shift,val,reg + movsg \reg,gr28 + set_gr_immed \mask,gr29 + and gr28,gr29,gr28 + srli gr28,\shift,gr29 + test_gr_immed \val,gr29 + .endm + + +; Test the value of an accumulator against an integer immediate + .macro test_acc_immed val reg + mrdacc \reg,fr31 + test_fr_iimmed \val,fr31 + .endm + +; Test the value of an accumulator against an integer immediate + .macro test_acc_limmed valh vall reg + mrdacc \reg,fr31 + test_fr_limmed \valh,\vall,fr31 + .endm + +; Test the value of an accumulator guard against an integer immediate + .macro test_accg_immed val reg + mrdaccg \reg,fr31 + test_fr_iimmed \val,fr31 + .endm + +; Test CPR agains an immediate value + .macro test_cpr_limmed valh vall reg + addi sp,-4,gr31 + stc \reg,@(gr31,gr0) + test_mem_limmed \valh,\vall,gr31 + .endm + +; Test the value of an immediate against memory + .macro test_mem_immed val base + ldi @(\base,0),gr29 + .if (\val >= -512) && (\val <= 511) + subicc gr29,\val,gr0,icc3 + .else + set_gr_immed \val,gr28 + subcc gr29,gr28,gr0,icc3 + .endif + beq icc3,0,test_gr\@ + fail +test_gr\@: + .endm + + .macro test_mem_limmed valh vall base + ldi @(\base,0),gr29 + set_gr_limmed \valh,\vall,gr28 + subcc gr29,gr28,gr0,icc3 + beq icc3,0,test_gr\@ + fail +test_gr\@: + .endm + +; Set an integer condition code + .macro set_icc mask iccno + set_gr_immed 4,gr29 + smuli gr29,\iccno,gr30 + addi gr31,16,gr31 + set_gr_immed 0xf,gr28 + sll gr28,gr31,gr28 + not gr28,gr28 + movsg ccr,gr29 + and gr28,gr29,gr29 + set_gr_immed \mask,gr28 + sll gr28,gr31,gr28 + or gr28,gr29,gr29 + movgs gr29,ccr + .endm +; started here +; Test the condition codes + .macro test_icc N Z V C iccno + .if (\N == 1) + bp \iccno,0,fail\@ + .else + bn \iccno,0,fail\@ + .endif + .if (\Z == 1) + bne \iccno,0,fail\@ + .else + beq \iccno,0,fail\@ + .endif + .if (\V == 1) + bnv \iccno,0,fail\@ + .else + bv \iccno,0,fail\@ + .endif + .if (\C == 1) + bnc \iccno,0,fail\@ + .else + bc \iccno,0,fail\@ + .endif + bra test_cc\@ +fail\@: + fail +test_cc\@: + .endm + +; Set an floating point condition code + .macro set_fcc mask fccno + set_gr_immed 4,gr29 + smuli gr29,\fccno,gr30 + set_gr_immed 0xf,gr28 + sll gr28,gr31,gr28 + not gr28,gr28 + movsg ccr,gr29 + and gr28,gr29,gr29 + set_gr_immed \mask,gr28 + sll gr28,gr31,gr28 + or gr28,gr29,gr29 + movgs gr29,ccr + .endm + +; Test the condition codes + .macro test_fcc val fccno + set_gr_immed 4,gr29 + smuli gr29,\fccno,gr30 + movsg ccr,gr29 + srl gr29,gr31,gr29 + andi gr29,0xf,gr29 + test_gr_immed \val,gr29 + .endm + +; Set PSR.ET + .macro set_psr_et val + movsg psr,gr28 + .if (\val == 1) + ori gr28,1,gr28 ; Turn on SPR.ET + .else + andi gr28,0xfffffffe,gr28 ; Turn off SPR.ET + .endif + movgs gr28,psr + .endm + +; Floating point constants + .macro float_constants +f0: .float 0.0 +f1: .float 1.0 +f2: .float 2.0 +f3: .float 3.0 +f6: .float 6.0 +f9: .float 9.0 +fn0: .float -0.0 +fn1: .float -1.0 +finf: .long 0x7f800000 +fninf: .long 0xff800000 +fmax: .long 0x7f7fffff +fmin: .long 0xff7fffff +feps: .long 0x00400000 +fneps: .long 0x80400000 +fnan1: .long 0x7fc00000 +fnan2: .long 0x7f800001 + .endm + + .macro double_constants +d0: .double 0.0 +d1: .double 1.0 +d2: .double 2.0 +d3: .double 3.0 +d6: .double 6.0 +d9: .double 9.0 +dn0: .double -0.0 +dn1: .double -1.0 +dinf: .long 0x7ff00000 + .long 0x00000000 +dninf: .long 0xfff00000 + .long 0x00000000 +dmax: .long 0x7fefffff + .long 0xffffffff +dmin: .long 0xffefffff + .long 0xffffffff +deps: .long 0x00080000 + .long 0x00000000 +dneps: .long 0x80080000 + .long 0x00000000 +dnan1: .long 0x7ff80000 + .long 0x00000000 +dnan2: .long 0x7ff00000 + .long 0x00000001 + .endm + +; Load floating point constants + .macro load_float_constants + set_fr_mem fninf,fr0 + set_fr_mem fmin,fr4 + set_fr_mem fn1,fr8 + set_fr_mem fneps,fr12 + set_fr_mem fn0,fr16 + set_fr_mem f0,fr20 + set_fr_mem feps,fr24 + set_fr_mem f1,fr28 + set_fr_mem f2,fr32 + set_fr_mem f3,fr36 + set_fr_mem f6,fr40 + set_fr_mem f9,fr44 + set_fr_mem fmax,fr48 + set_fr_mem finf,fr52 + set_fr_mem fnan1,fr56 + set_fr_mem fnan2,fr60 + .endm + + .macro load_float_constants1 + set_fr_mem fninf,fr1 + set_fr_mem fmin,fr5 + set_fr_mem fn1,fr9 + set_fr_mem fneps,fr13 + set_fr_mem fn0,fr17 + set_fr_mem f0,fr21 + set_fr_mem feps,fr25 + set_fr_mem f1,fr29 + set_fr_mem f2,fr33 + set_fr_mem f3,fr37 + set_fr_mem f6,fr41 + set_fr_mem f9,fr45 + set_fr_mem fmax,fr49 + set_fr_mem finf,fr53 + set_fr_mem fnan1,fr57 + set_fr_mem fnan2,fr61 + .endm + + .macro load_float_constants2 + set_fr_mem fninf,fr2 + set_fr_mem fmin,fr6 + set_fr_mem fn1,fr10 + set_fr_mem fneps,fr14 + set_fr_mem fn0,fr18 + set_fr_mem f0,fr22 + set_fr_mem feps,fr26 + set_fr_mem f1,fr30 + set_fr_mem f2,fr34 + set_fr_mem f3,fr38 + set_fr_mem f6,fr42 + set_fr_mem f9,fr46 + set_fr_mem fmax,fr50 + set_fr_mem finf,fr54 + set_fr_mem fnan1,fr58 + set_fr_mem fnan2,fr62 + .endm + + .macro load_float_constants3 + set_fr_mem fninf,fr3 + set_fr_mem fmin,fr7 + set_fr_mem fn1,fr11 + set_fr_mem fneps,fr15 + set_fr_mem fn0,fr19 + set_fr_mem f0,fr23 + set_fr_mem feps,fr27 + set_fr_mem f1,fr31 + set_fr_mem f2,fr35 + set_fr_mem f3,fr39 + set_fr_mem f6,fr43 + set_fr_mem f9,fr47 + set_fr_mem fmax,fr51 + set_fr_mem finf,fr55 + set_fr_mem fnan1,fr59 + set_fr_mem fnan2,fr63 + .endm + + .macro load_double_constants + set_dfr_mem dninf,fr0 + set_dfr_mem dmin,fr4 + set_dfr_mem dn1,fr8 + set_dfr_mem dneps,fr12 + set_dfr_mem dn0,fr16 + set_dfr_mem d0,fr20 + set_dfr_mem deps,fr24 + set_dfr_mem d1,fr28 + set_dfr_mem d2,fr32 + set_dfr_mem d3,fr36 + set_dfr_mem d6,fr40 + set_dfr_mem d9,fr44 + set_dfr_mem dmax,fr48 + set_dfr_mem dinf,fr52 + set_dfr_mem dnan1,fr56 + set_dfr_mem dnan2,fr60 + .endm + +; Lock the insn cache at the given address + .macro lock_insn_cache address + icpl \address,gr0,1 + .endm + +; Lock the data cache at the given address + .macro lock_data_cache address + dcpl \address,gr0,1 + .endm + +; Invalidate the data cache at the given address + .macro invalidate_data_cache address + dci @(\address,gr0) + .endm + +; Flush the data cache at the given address + .macro flush_data_cache address + dcf @(\address,gr0) + .endm + +; Write a bctrlr 0,0 insn at the address contained in the given register + .macro set_bctrlr_0_0 address + set_mem_immed 0x80382000,\address ; bctrlr 0,0 + flush_data_cache \address + .endm + +; Exit with return code + .macro exit rc + setlos #1,gr7 + set_gr_immed \rc,gr8 + tira gr0,#0 + .endm + +; Pass the test case + .macro pass +pass\@: + setlos.p #5,gr10 + setlos #1,gr8 + setlos #5,gr7 + set_gr_addr passmsg,gr9 + tira gr0,#0 + exit #0 + .endm + +; Fail the testcase + .macro fail +fail\@: + setlos.p #5,gr10 + setlos #1,gr8 + setlos #5,gr7 + set_gr_addr failmsg,gr9 + tira gr0,#0 + exit #1 + .endm diff --git a/sim/testsuite/sim/frv/tge.cgs b/sim/testsuite/sim/frv/tge.cgs new file mode 100644 index 0000000..3e12d92 --- /dev/null +++ b/sim/testsuite/sim/frv/tge.cgs @@ -0,0 +1,101 @@ +# frv testcase for tge $ICCi_2,$GRi,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global tge +tge: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_psr_et 1 + set_spr_addr ok0,lr + set_icc 0x0 0 + tge icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok0: + set_psr_et 1 + set_spr_addr ok1,lr + set_icc 0x1 0 + tge icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok1: + set_spr_addr bad,lr + set_icc 0x2 0 + tge icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x3 0 + tge icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok4,lr + set_icc 0x4 0 + tge icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok4: + set_psr_et 1 + set_spr_addr ok5,lr + set_icc 0x5 0 + tge icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_spr_addr bad,lr + set_icc 0x6 0 + tge icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x7 0 + tge icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x8 0 + tge icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x9 0 + tge icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr oka,lr + set_icc 0xa 0 + tge icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_icc 0xb 0 + tge icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_spr_addr bad,lr + set_icc 0xc 0 + tge icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xd 0 + tge icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr oke,lr + set_icc 0xe 0 + tge icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_icc 0xf 0 + tge icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/tgt.cgs b/sim/testsuite/sim/frv/tgt.cgs new file mode 100644 index 0000000..7e01330 --- /dev/null +++ b/sim/testsuite/sim/frv/tgt.cgs @@ -0,0 +1,93 @@ +# frv testcase for tgt $ICCi_2,$GRi,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global tgt +tgt: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_psr_et 1 + set_spr_addr ok0,lr + set_icc 0x0 0 + tgt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok0: + set_psr_et 1 + set_spr_addr ok1,lr + set_icc 0x1 0 + tgt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok1: + set_spr_addr bad,lr + set_icc 0x2 0 + tgt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x3 0 + tgt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x4 0 + tgt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x5 0 + tgt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x6 0 + tgt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x7 0 + tgt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x8 0 + tgt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x9 0 + tgt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr oka,lr + set_icc 0xa 0 + tgt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_icc 0xb 0 + tgt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_spr_addr bad,lr + set_icc 0xc 0 + tgt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xd 0 + tgt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xe 0 + tgt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xf 0 + tgt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/thi.cgs b/sim/testsuite/sim/frv/thi.cgs new file mode 100644 index 0000000..36cc923 --- /dev/null +++ b/sim/testsuite/sim/frv/thi.cgs @@ -0,0 +1,93 @@ +# frv testcase for thi $ICCi_2,$GRi,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global thi +thi: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_psr_et 1 + set_spr_addr ok0,lr + set_icc 0x0 0 + thi icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok0: + set_spr_addr bad,lr + set_icc 0x1 0 + thi icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok2,lr + set_icc 0x2 0 + thi icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_spr_addr bad,lr + set_icc 0x3 0 + thi icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x4 0 + thi icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x5 0 + thi icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x6 0 + thi icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x7 0 + thi icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok8,lr + set_icc 0x8 0 + thi icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok8: + set_spr_addr bad,lr + set_icc 0x9 0 + thi icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr oka,lr + set_icc 0xa 0 + thi icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_spr_addr bad,lr + set_icc 0xb 0 + thi icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xc 0 + thi icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xd 0 + thi icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xe 0 + thi icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xf 0 + thi icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/tic.cgs b/sim/testsuite/sim/frv/tic.cgs new file mode 100644 index 0000000..8c746f5 --- /dev/null +++ b/sim/testsuite/sim/frv/tic.cgs @@ -0,0 +1,100 @@ +# frv testcase for tic $ICCi_2,$GRi,$s12 +# mach: all + + .include "testutils.inc" + + start + + .global tic +tic: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + + set_spr_addr bad,lr + set_icc 0x0 0 + tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok1,lr + set_icc 0x1 0 + tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok1: + set_spr_addr bad,lr + set_icc 0x2 0 + tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok3,lr + set_icc 0x3 0 + tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_spr_addr bad,lr + set_icc 0x4 0 + tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok5,lr + set_icc 0x5 0 + tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_spr_addr bad,lr + set_icc 0x6 0 + tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok7,lr + set_icc 0x7 0 + tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_spr_addr bad,lr + set_icc 0x8 0 + tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok9,lr + set_icc 0x9 0 + tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_spr_addr bad,lr + set_icc 0xa 0 + tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr okb,lr + set_icc 0xb 0 + tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_spr_addr bad,lr + set_icc 0xc 0 + tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr okd,lr + set_icc 0xd 0 + tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_spr_addr bad,lr + set_icc 0xe 0 + tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr okf,lr + set_icc 0xf 0 + tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/tieq.cgs b/sim/testsuite/sim/frv/tieq.cgs new file mode 100644 index 0000000..5dfc0e6 --- /dev/null +++ b/sim/testsuite/sim/frv/tieq.cgs @@ -0,0 +1,101 @@ +# frv testcase for tieq $ICCi_2,$GRi,$s12 +# mach: all + + .include "testutils.inc" + + start + + .global tieq +tieq: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + + set_spr_addr bad,lr + set_icc 0x0 0 + tieq icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x1 0 + tieq icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x2 0 + tieq icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x3 0 + tieq icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok4,lr + set_icc 0x4 0 + tieq icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok4: + set_psr_et 1 + set_spr_addr ok5,lr + set_icc 0x5 0 + tieq icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_psr_et 1 + set_spr_addr ok6,lr + set_icc 0x6 0 + tieq icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_icc 0x7 0 + tieq icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_psr_et 1 + set_spr_addr bad,lr + set_icc 0x8 0 + tieq icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x9 0 + tieq icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xa 0 + tieq icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xb 0 + tieq icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr okc,lr + set_icc 0xc 0 + tieq icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_icc 0xd 0 + tieq icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_icc 0xe 0 + tieq icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_icc 0xf 0 + tieq icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/tige.cgs b/sim/testsuite/sim/frv/tige.cgs new file mode 100644 index 0000000..cde3ac8 --- /dev/null +++ b/sim/testsuite/sim/frv/tige.cgs @@ -0,0 +1,101 @@ +# frv testcase for tige $ICCi_2,$GRi,$s12 +# mach: all + + .include "testutils.inc" + + start + + .global tige +tige: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + + set_psr_et 1 + set_spr_addr ok0,lr + set_icc 0x0 0 + tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok0: + set_psr_et 1 + set_spr_addr ok1,lr + set_icc 0x1 0 + tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok1: + set_spr_addr bad,lr + set_icc 0x2 0 + tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x3 0 + tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok4,lr + set_icc 0x4 0 + tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok4: + set_psr_et 1 + set_spr_addr ok5,lr + set_icc 0x5 0 + tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_psr_et 1 + set_spr_addr bad,lr + set_icc 0x6 0 + tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x7 0 + tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x8 0 + tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x9 0 + tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr oka,lr + set_icc 0xa 0 + tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_icc 0xb 0 + tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_spr_addr bad,lr + set_icc 0xc 0 + tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xd 0 + tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr oke,lr + set_icc 0xe 0 + tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_icc 0xf 0 + tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/tigt.cgs b/sim/testsuite/sim/frv/tigt.cgs new file mode 100644 index 0000000..163d92f --- /dev/null +++ b/sim/testsuite/sim/frv/tigt.cgs @@ -0,0 +1,92 @@ +# frv testcase for tigt $ICCi_2,$GRi,$s12 +# mach: all + + .include "testutils.inc" + + start + + .global tigt +tigt: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + + set_psr_et 1 + set_spr_addr ok0,lr + set_icc 0x0 0 + tigt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok0: + set_psr_et 1 + set_spr_addr ok1,lr + set_icc 0x1 0 + tigt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok1: + set_spr_addr bad,lr + set_icc 0x2 0 + tigt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x3 0 + tigt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x4 0 + tigt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x5 0 + tigt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x6 0 + tigt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x7 0 + tigt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x8 0 + tigt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x9 0 + tigt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr oka,lr + set_icc 0xa 0 + tigt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_icc 0xb 0 + tigt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_spr_addr bad,lr + set_icc 0xc 0 + tigt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xd 0 + tigt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xe 0 + tigt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xf 0 + tigt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/tihi.cgs b/sim/testsuite/sim/frv/tihi.cgs new file mode 100644 index 0000000..e564fc2 --- /dev/null +++ b/sim/testsuite/sim/frv/tihi.cgs @@ -0,0 +1,92 @@ +# frv testcase for tihi $ICCi_2,$GRi,$s12 +# mach: all + + .include "testutils.inc" + + start + + .global tihi +tihi: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + + set_psr_et 1 + set_spr_addr ok0,lr + set_icc 0x0 0 + tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok0: + set_spr_addr bad,lr + set_icc 0x1 0 + tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok2,lr + set_icc 0x2 0 + tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_spr_addr bad,lr + set_icc 0x3 0 + tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x4 0 + tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x5 0 + tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x6 0 + tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x7 0 + tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok8,lr + set_icc 0x8 0 + tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok8: + set_spr_addr bad,lr + set_icc 0x9 0 + tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr oka,lr + set_icc 0xa 0 + tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_spr_addr bad,lr + set_icc 0xb 0 + tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xc 0 + tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xd 0 + tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xe 0 + tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xf 0 + tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/tile.cgs b/sim/testsuite/sim/frv/tile.cgs new file mode 100644 index 0000000..7f5ef2a --- /dev/null +++ b/sim/testsuite/sim/frv/tile.cgs @@ -0,0 +1,108 @@ +# frv testcase for tile $ICCi_2,$GRi,$s12 +# mach: all + + .include "testutils.inc" + + start + + .global tile +tile: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + + set_spr_addr bad,lr + set_icc 0x0 0 + tile icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x1 0 + tile icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok2,lr + set_icc 0x2 0 + tile icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_psr_et 1 + set_spr_addr ok3,lr + set_icc 0x3 0 + tile icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_psr_et 1 + set_spr_addr ok4,lr + set_icc 0x4 0 + tile icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok4: + set_psr_et 1 + set_spr_addr ok5,lr + set_icc 0x5 0 + tile icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_psr_et 1 + set_spr_addr ok6,lr + set_icc 0x6 0 + tile icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_icc 0x7 0 + tile icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_psr_et 1 + set_spr_addr ok8,lr + set_icc 0x8 0 + tile icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok8: + set_psr_et 1 + set_spr_addr ok9,lr + set_icc 0x9 0 + tile icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_spr_addr bad,lr + set_icc 0xa 0 + tile icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xb 0 + tile icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr okc,lr + set_icc 0xc 0 + tile icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_icc 0xd 0 + tile icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_icc 0xe 0 + tile icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_icc 0xf 0 + tile icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/tils.cgs b/sim/testsuite/sim/frv/tils.cgs new file mode 100644 index 0000000..5713de5 --- /dev/null +++ b/sim/testsuite/sim/frv/tils.cgs @@ -0,0 +1,108 @@ +# frv testcase for tils $ICCi_2,$GRi,$s12 +# mach: all + + .include "testutils.inc" + + start + + .global tils +tils: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + + set_spr_addr bad,lr + set_icc 0x0 0 + tils icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok1,lr + set_icc 0x1 0 + tils icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok1: + set_spr_addr bad,lr + set_icc 0x2 0 + tils icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok3,lr + set_icc 0x3 0 + tils icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_psr_et 1 + set_spr_addr ok4,lr + set_icc 0x4 0 + tils icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok4: + set_psr_et 1 + set_spr_addr ok5,lr + set_icc 0x5 0 + tils icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_psr_et 1 + set_spr_addr ok6,lr + set_icc 0x6 0 + tils icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_icc 0x7 0 + tils icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_spr_addr bad,lr + set_icc 0x8 0 + tils icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok9,lr + set_icc 0x9 0 + tils icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_spr_addr bad,lr + set_icc 0xa 0 + tils icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr okb,lr + set_icc 0xb 0 + tils icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_psr_et 1 + set_spr_addr okc,lr + set_icc 0xc 0 + tils icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_icc 0xd 0 + tils icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_icc 0xe 0 + tils icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_icc 0xf 0 + tils icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/tilt.cgs b/sim/testsuite/sim/frv/tilt.cgs new file mode 100644 index 0000000..4d596b0 --- /dev/null +++ b/sim/testsuite/sim/frv/tilt.cgs @@ -0,0 +1,100 @@ +# frv testcase for tilt $ICCi_2,$GRi,$s12 +# mach: all + + .include "testutils.inc" + + start + + .global tilt +tilt: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + + set_spr_addr bad,lr + set_icc 0x0 0 + tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x1 0 + tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok2,lr + set_icc 0x2 0 + tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_psr_et 1 + set_spr_addr ok3,lr + set_icc 0x3 0 + tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_spr_addr bad,lr + set_icc 0x4 0 + tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x5 0 + tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok6,lr + set_icc 0x6 0 + tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_icc 0x7 0 + tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_psr_et 1 + set_spr_addr ok8,lr + set_icc 0x8 0 + tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok8: + set_psr_et 1 + set_spr_addr ok9,lr + set_icc 0x9 0 + tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_spr_addr bad,lr + set_icc 0xa 0 + tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xb 0 + tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr okc,lr + set_icc 0xc 0 + tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_icc 0xd 0 + tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_spr_addr bad,lr + set_icc 0xe 0 + tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xf 0 + tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/tin.cgs b/sim/testsuite/sim/frv/tin.cgs new file mode 100644 index 0000000..f55c921 --- /dev/null +++ b/sim/testsuite/sim/frv/tin.cgs @@ -0,0 +1,100 @@ +# frv testcase for tin $ICCi_2,$GRi,$s12 +# mach: all + + .include "testutils.inc" + + start + + .global tin +tin: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + + set_spr_addr bad,lr + set_icc 0x0 0 + tin icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x1 0 + tin icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x2 0 + tin icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x3 0 + tin icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x4 0 + tin icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x5 0 + tin icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x6 0 + tin icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x7 0 + tin icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok8,lr + set_icc 0x8 0 + tin icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok8: + set_psr_et 1 + set_spr_addr ok9,lr + set_icc 0x9 0 + tin icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_psr_et 1 + set_spr_addr oka,lr + set_icc 0xa 0 + tin icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_icc 0xb 0 + tin icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_psr_et 1 + set_spr_addr okc,lr + set_icc 0xc 0 + tin icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_icc 0xd 0 + tin icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_icc 0xe 0 + tin icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_icc 0xf 0 + tin icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/tinc.cgs b/sim/testsuite/sim/frv/tinc.cgs new file mode 100644 index 0000000..8e99e31 --- /dev/null +++ b/sim/testsuite/sim/frv/tinc.cgs @@ -0,0 +1,100 @@ +# frv testcase for tinc $ICCi_2,$GRi,$s12 +# mach: all + + .include "testutils.inc" + + start + + .global tinc +tinc: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + + set_psr_et 1 + set_spr_addr ok0,lr + set_icc 0x0 0 + tinc icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok0: + set_spr_addr bad,lr + set_icc 0x1 0 + tinc icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok2,lr + set_icc 0x2 0 + tinc icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_spr_addr bad,lr + set_icc 0x3 0 + tinc icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok4,lr + set_icc 0x4 0 + tinc icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok4: + set_spr_addr bad,lr + set_icc 0x5 0 + tinc icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok6,lr + set_icc 0x6 0 + tinc icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_spr_addr bad,lr + set_icc 0x7 0 + tinc icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok8,lr + set_icc 0x8 0 + tinc icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok8: + set_spr_addr bad,lr + set_icc 0x9 0 + tinc icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr oka,lr + set_icc 0xa 0 + tinc icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_spr_addr bad,lr + set_icc 0xb 0 + tinc icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr okc,lr + set_icc 0xc 0 + tinc icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_spr_addr bad,lr + set_icc 0xd 0 + tinc icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr oke,lr + set_icc 0xe 0 + tinc icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_spr_addr bad,lr + set_icc 0xf 0 + tinc icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/tine.cgs b/sim/testsuite/sim/frv/tine.cgs new file mode 100644 index 0000000..d7e8b00 --- /dev/null +++ b/sim/testsuite/sim/frv/tine.cgs @@ -0,0 +1,100 @@ +# frv testcase for tine $ICCi_2,$GRi,$s12 +# mach: all + + .include "testutils.inc" + + start + + .global tine +tine: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + + set_psr_et 1 + set_spr_addr ok0,lr + set_icc 0x0 0 + tine icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok0: + set_psr_et 1 + set_spr_addr ok1,lr + set_icc 0x1 0 + tine icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok1: + set_psr_et 1 + set_spr_addr ok2,lr + set_icc 0x2 0 + tine icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_psr_et 1 + set_spr_addr ok3,lr + set_icc 0x3 0 + tine icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_spr_addr bad,lr + set_icc 0x4 0 + tine icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x5 0 + tine icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x6 0 + tine icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x7 0 + tine icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok8,lr + set_icc 0x8 0 + tine icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok8: + set_psr_et 1 + set_spr_addr ok9,lr + set_icc 0x9 0 + tine icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_psr_et 1 + set_spr_addr oka,lr + set_icc 0xa 0 + tine icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_icc 0xb 0 + tine icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_spr_addr bad,lr + set_icc 0xc 0 + tine icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xd 0 + tine icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xe 0 + tine icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xf 0 + tine icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/tino.cgs b/sim/testsuite/sim/frv/tino.cgs new file mode 100644 index 0000000..65a2d6d --- /dev/null +++ b/sim/testsuite/sim/frv/tino.cgs @@ -0,0 +1,53 @@ +# frv testcase for tino +# mach: all + + .include "testutils.inc" + + start + + .global tinev +tinev: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_mem_limmed 0x0038,0x2000,gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_gr_immed 0,gr7 + + set_icc 0x0 0 + tino ; should branch to tbr + (128 + 4)*16 + set_icc 0x1 0 + tino ; should branch to tbr + (128 + 4)*16 + set_icc 0x2 0 + tino ; should branch to tbr + (128 + 4)*16 + set_icc 0x3 0 + tino ; should branch to tbr + (128 + 4)*16 + set_icc 0x4 0 + tino ; should branch to tbr + (128 + 4)*16 + set_icc 0x5 0 + tino ; should branch to tbr + (128 + 4)*16 + set_icc 0x6 0 + tino ; should branch to tbr + (128 + 4)*16 + set_icc 0x7 0 + tino ; should branch to tbr + (128 + 4)*16 + set_icc 0x8 0 + tino ; should branch to tbr + (128 + 4)*16 + set_icc 0x9 0 + tino ; should branch to tbr + (128 + 4)*16 + set_icc 0xa 0 + tino ; should branch to tbr + (128 + 4)*16 + set_icc 0xb 0 + tino ; should branch to tbr + (128 + 4)*16 + set_icc 0xc 0 + tino ; should branch to tbr + (128 + 4)*16 + set_icc 0xd 0 + tino ; should branch to tbr + (128 + 4)*16 + set_icc 0xe 0 + tino ; should branch to tbr + (128 + 4)*16 + set_icc 0xf 0 + tino ; should branch to tbr + (128 + 4)*16 + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/tinv.cgs b/sim/testsuite/sim/frv/tinv.cgs new file mode 100644 index 0000000..7ec34a4 --- /dev/null +++ b/sim/testsuite/sim/frv/tinv.cgs @@ -0,0 +1,100 @@ +# frv testcase for tinv $ICCi_2,$GRi,$s12 +# mach: all + + .include "testutils.inc" + + start + + .global tinv +tinv: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + + set_psr_et 1 + set_spr_addr ok0,lr + set_icc 0x0 0 + tinv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok0: + set_psr_et 1 + set_spr_addr ok1,lr + set_icc 0x1 0 + tinv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok1: + set_spr_addr bad,lr + set_icc 0x2 0 + tinv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x3 0 + tinv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok4,lr + set_icc 0x4 0 + tinv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok4: + set_psr_et 1 + set_spr_addr ok5,lr + set_icc 0x5 0 + tinv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_spr_addr bad,lr + set_icc 0x6 0 + tinv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x7 0 + tinv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok8,lr + set_icc 0x8 0 + tinv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok8: + set_psr_et 1 + set_spr_addr ok9,lr + set_icc 0x9 0 + tinv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_spr_addr bad,lr + set_icc 0xa 0 + tinv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xb 0 + tinv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr okc,lr + set_icc 0xc 0 + tinv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_icc 0xd 0 + tinv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_spr_addr bad,lr + set_icc 0xe 0 + tinv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xf 0 + tinv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/tip.cgs b/sim/testsuite/sim/frv/tip.cgs new file mode 100644 index 0000000..8353422 --- /dev/null +++ b/sim/testsuite/sim/frv/tip.cgs @@ -0,0 +1,100 @@ +# frv testcase for tip $ICCi_2,$GRi,$s12 +# mach: all + + .include "testutils.inc" + + start + + .global tip +tip: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + + set_psr_et 1 + set_spr_addr ok0,lr + set_icc 0x0 0 + tip icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok0: + set_psr_et 1 + set_spr_addr ok1,lr + set_icc 0x1 0 + tip icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok1: + set_psr_et 1 + set_spr_addr ok2,lr + set_icc 0x2 0 + tip icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_psr_et 1 + set_spr_addr ok3,lr + set_icc 0x3 0 + tip icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_psr_et 1 + set_spr_addr ok4,lr + set_icc 0x4 0 + tip icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok4: + set_psr_et 1 + set_spr_addr ok5,lr + set_icc 0x5 0 + tip icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_psr_et 1 + set_spr_addr ok6,lr + set_icc 0x6 0 + tip icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_icc 0x7 0 + tip icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_spr_addr bad,lr + set_icc 0x8 0 + tip icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x9 0 + tip icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xa 0 + tip icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xb 0 + tip icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xc 0 + tip icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xd 0 + tip icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xe 0 + tip icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xf 0 + tip icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/tira.cgs b/sim/testsuite/sim/frv/tira.cgs new file mode 100644 index 0000000..bd3139e --- /dev/null +++ b/sim/testsuite/sim/frv/tira.cgs @@ -0,0 +1,114 @@ +# frv testcase for tira $GRi,$s12 +# mach: all + + .include "testutils.inc" + + start + + .global tira +tira: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + + set_psr_et 1 + set_spr_addr ok0,lr + set_icc 0x0 0 + tira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok0: + set_psr_et 1 + set_spr_addr ok1,lr + set_icc 0x1 0 + tira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok1: + set_psr_et 1 + set_spr_addr ok2,lr + set_icc 0x2 0 + tira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_psr_et 1 + set_spr_addr ok3,lr + set_icc 0x3 0 + tira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_psr_et 1 + set_spr_addr ok4,lr + set_icc 0x4 0 + tira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok4: + set_psr_et 1 + set_spr_addr ok5,lr + set_icc 0x5 0 + tira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_psr_et 1 + set_spr_addr ok6,lr + set_icc 0x6 0 + tira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_icc 0x7 0 + tira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_psr_et 1 + set_spr_addr ok8,lr + set_icc 0x8 0 + tira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok8: + set_psr_et 1 + set_spr_addr ok9,lr + set_icc 0x9 0 + tira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_psr_et 1 + set_spr_addr oka,lr + set_icc 0xa 0 + tira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_icc 0xb 0 + tira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_psr_et 1 + set_spr_addr okc,lr + set_icc 0xc 0 + tira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_icc 0xd 0 + tira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_icc 0xe 0 + tira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_icc 0xf 0 + tira gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass diff --git a/sim/testsuite/sim/frv/tiv.cgs b/sim/testsuite/sim/frv/tiv.cgs new file mode 100644 index 0000000..84a2576 --- /dev/null +++ b/sim/testsuite/sim/frv/tiv.cgs @@ -0,0 +1,100 @@ +# frv testcase for tiv $ICCi_2,$GRi,$s12 +# mach: all + + .include "testutils.inc" + + start + + .global tiv +tiv: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + + set_spr_addr bad,lr + set_icc 0x0 0 + tiv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x1 0 + tiv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok2,lr + set_icc 0x2 0 + tiv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_psr_et 1 + set_spr_addr ok3,lr + set_icc 0x3 0 + tiv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_spr_addr bad,lr + set_icc 0x4 0 + tiv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x5 0 + tiv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok6,lr + set_icc 0x6 0 + tiv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_icc 0x7 0 + tiv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_spr_addr bad,lr + set_icc 0x8 0 + tiv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x9 0 + tiv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr oka,lr + set_icc 0xa 0 + tiv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_icc 0xb 0 + tiv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_spr_addr bad,lr + set_icc 0xc 0 + tiv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xd 0 + tiv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr oke,lr + set_icc 0xe 0 + tiv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_icc 0xf 0 + tiv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/tle.cgs b/sim/testsuite/sim/frv/tle.cgs new file mode 100644 index 0000000..1322821 --- /dev/null +++ b/sim/testsuite/sim/frv/tle.cgs @@ -0,0 +1,109 @@ +# frv testcase for tle $ICCi_2,$GRi,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global tle +tle: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_spr_addr bad,lr + set_icc 0x0 0 + tle icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x1 0 + tle icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok2,lr + set_icc 0x2 0 + tle icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_psr_et 1 + set_spr_addr ok3,lr + set_icc 0x3 0 + tle icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_psr_et 1 + set_spr_addr ok4,lr + set_icc 0x4 0 + tle icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok4: + set_psr_et 1 + set_spr_addr ok5,lr + set_icc 0x5 0 + tle icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_psr_et 1 + set_spr_addr ok6,lr + set_icc 0x6 0 + tle icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_icc 0x7 0 + tle icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_psr_et 1 + set_spr_addr ok8,lr + set_icc 0x8 0 + tle icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok8: + set_psr_et 1 + set_spr_addr ok9,lr + set_icc 0x9 0 + tle icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_spr_addr bad,lr + set_icc 0xa 0 + tle icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xb 0 + tle icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr okc,lr + set_icc 0xc 0 + tle icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_icc 0xd 0 + tle icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_icc 0xe 0 + tle icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_icc 0xf 0 + tle icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/tls.cgs b/sim/testsuite/sim/frv/tls.cgs new file mode 100644 index 0000000..708e617 --- /dev/null +++ b/sim/testsuite/sim/frv/tls.cgs @@ -0,0 +1,109 @@ +# frv testcase for tls $ICCi_2,$GRi,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global tls +tls: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_spr_addr bad,lr + set_icc 0x0 0 + tls icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok1,lr + set_icc 0x1 0 + tls icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok1: + set_spr_addr bad,lr + set_icc 0x2 0 + tls icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok3,lr + set_icc 0x3 0 + tls icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_psr_et 1 + set_spr_addr ok4,lr + set_icc 0x4 0 + tls icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok4: + set_psr_et 1 + set_spr_addr ok5,lr + set_icc 0x5 0 + tls icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_psr_et 1 + set_spr_addr ok6,lr + set_icc 0x6 0 + tls icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_icc 0x7 0 + tls icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_spr_addr bad,lr + set_icc 0x8 0 + tls icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok9,lr + set_icc 0x9 0 + tls icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_spr_addr bad,lr + set_icc 0xa 0 + tls icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr okb,lr + set_icc 0xb 0 + tls icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_psr_et 1 + set_spr_addr okc,lr + set_icc 0xc 0 + tls icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_icc 0xd 0 + tls icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_icc 0xe 0 + tls icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_icc 0xf 0 + tls icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/tlt.cgs b/sim/testsuite/sim/frv/tlt.cgs new file mode 100644 index 0000000..12ee05b --- /dev/null +++ b/sim/testsuite/sim/frv/tlt.cgs @@ -0,0 +1,101 @@ +# frv testcase for tlt $ICCi_2,$GRi,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global tlt +tlt: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_spr_addr bad,lr + set_icc 0x0 0 + tlt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x1 0 + tlt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok2,lr + set_icc 0x2 0 + tlt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_psr_et 1 + set_spr_addr ok3,lr + set_icc 0x3 0 + tlt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_spr_addr bad,lr + set_icc 0x4 0 + tlt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x5 0 + tlt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok6,lr + set_icc 0x6 0 + tlt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_icc 0x7 0 + tlt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_psr_et 1 + set_spr_addr ok8,lr + set_icc 0x8 0 + tlt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok8: + set_psr_et 1 + set_spr_addr ok9,lr + set_icc 0x9 0 + tlt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_spr_addr bad,lr + set_icc 0xa 0 + tlt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xb 0 + tlt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr okc,lr + set_icc 0xc 0 + tlt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_icc 0xd 0 + tlt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_spr_addr bad,lr + set_icc 0xe 0 + tlt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xf 0 + tlt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/tn.cgs b/sim/testsuite/sim/frv/tn.cgs new file mode 100644 index 0000000..05b0424 --- /dev/null +++ b/sim/testsuite/sim/frv/tn.cgs @@ -0,0 +1,101 @@ +# frv testcase for tn $ICCi_2,$GRi,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global tn +tn: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_spr_addr bad,lr + set_icc 0x0 0 + tn icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x1 0 + tn icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x2 0 + tn icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x3 0 + tn icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x4 0 + tn icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x5 0 + tn icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x6 0 + tn icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x7 0 + tn icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok8,lr + set_icc 0x8 0 + tn icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok8: + set_psr_et 1 + set_spr_addr ok9,lr + set_icc 0x9 0 + tn icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_psr_et 1 + set_spr_addr oka,lr + set_icc 0xa 0 + tn icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_icc 0xb 0 + tn icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_psr_et 1 + set_spr_addr okc,lr + set_icc 0xc 0 + tn icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_icc 0xd 0 + tn icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_icc 0xe 0 + tn icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_icc 0xf 0 + tn icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/tnc.cgs b/sim/testsuite/sim/frv/tnc.cgs new file mode 100644 index 0000000..808db3c --- /dev/null +++ b/sim/testsuite/sim/frv/tnc.cgs @@ -0,0 +1,101 @@ +# frv testcase for tnc $ICCi_2,$GRi,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global tnc +tnc: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_psr_et 1 + set_spr_addr ok0,lr + set_icc 0x0 0 + tnc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok0: + set_spr_addr bad,lr + set_icc 0x1 0 + tnc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok2,lr + set_icc 0x2 0 + tnc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_spr_addr bad,lr + set_icc 0x3 0 + tnc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok4,lr + set_icc 0x4 0 + tnc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok4: + set_spr_addr bad,lr + set_icc 0x5 0 + tnc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok6,lr + set_icc 0x6 0 + tnc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_spr_addr bad,lr + set_icc 0x7 0 + tnc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok8,lr + set_icc 0x8 0 + tnc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok8: + set_spr_addr bad,lr + set_icc 0x9 0 + tnc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr oka,lr + set_icc 0xa 0 + tnc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_spr_addr bad,lr + set_icc 0xb 0 + tnc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr okc,lr + set_icc 0xc 0 + tnc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_spr_addr bad,lr + set_icc 0xd 0 + tnc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr oke,lr + set_icc 0xe 0 + tnc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_spr_addr bad,lr + set_icc 0xf 0 + tnc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/tne.cgs b/sim/testsuite/sim/frv/tne.cgs new file mode 100644 index 0000000..880188d --- /dev/null +++ b/sim/testsuite/sim/frv/tne.cgs @@ -0,0 +1,101 @@ +# frv testcase for tne $ICCi_2,$GRi,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global tne +tne: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_psr_et 1 + set_spr_addr ok0,lr + set_icc 0x0 0 + tne icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok0: + set_psr_et 1 + set_spr_addr ok1,lr + set_icc 0x1 0 + tne icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok1: + set_psr_et 1 + set_spr_addr ok2,lr + set_icc 0x2 0 + tne icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_psr_et 1 + set_spr_addr ok3,lr + set_icc 0x3 0 + tne icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_spr_addr bad,lr + set_icc 0x4 0 + tne icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x5 0 + tne icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x6 0 + tne icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x7 0 + tne icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok8,lr + set_icc 0x8 0 + tne icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok8: + set_psr_et 1 + set_spr_addr ok9,lr + set_icc 0x9 0 + tne icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_psr_et 1 + set_spr_addr oka,lr + set_icc 0xa 0 + tne icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_icc 0xb 0 + tne icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_spr_addr bad,lr + set_icc 0xc 0 + tne icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xd 0 + tne icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xe 0 + tne icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xf 0 + tne icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/tno.cgs b/sim/testsuite/sim/frv/tno.cgs new file mode 100644 index 0000000..df49969 --- /dev/null +++ b/sim/testsuite/sim/frv/tno.cgs @@ -0,0 +1,54 @@ +# frv testcase for tno +# mach: all + + .include "testutils.inc" + + start + + .global tno +tno: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_mem_limmed 0x0038,0x2000,gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_spr_addr bad,lr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_icc 0x0 0 + tno ; should branch to tbr + (128 + 4)*16 + set_icc 0x1 0 + tno ; should branch to tbr + (128 + 4)*16 + set_icc 0x2 0 + tno ; should branch to tbr + (128 + 4)*16 + set_icc 0x3 0 + tno ; should branch to tbr + (128 + 4)*16 + set_icc 0x4 0 + tno ; should branch to tbr + (128 + 4)*16 + set_icc 0x5 0 + tno ; should branch to tbr + (128 + 4)*16 + set_icc 0x6 0 + tno ; should branch to tbr + (128 + 4)*16 + set_icc 0x7 0 + tno ; should branch to tbr + (128 + 4)*16 + set_icc 0x8 0 + tno ; should branch to tbr + (128 + 4)*16 + set_icc 0x9 0 + tno ; should branch to tbr + (128 + 4)*16 + set_icc 0xa 0 + tno ; should branch to tbr + (128 + 4)*16 + set_icc 0xb 0 + tno ; should branch to tbr + (128 + 4)*16 + set_icc 0xc 0 + tno ; should branch to tbr + (128 + 4)*16 + set_icc 0xd 0 + tno ; should branch to tbr + (128 + 4)*16 + set_icc 0xe 0 + tno ; should branch to tbr + (128 + 4)*16 + set_icc 0xf 0 + tno ; should branch to tbr + (128 + 4)*16 + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/tnv.cgs b/sim/testsuite/sim/frv/tnv.cgs new file mode 100644 index 0000000..d7f9241 --- /dev/null +++ b/sim/testsuite/sim/frv/tnv.cgs @@ -0,0 +1,101 @@ +# frv testcase for tnv $ICCi_2,$GRi,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global tnv +tnv: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_psr_et 1 + set_spr_addr ok0,lr + set_icc 0x0 0 + tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok0: + set_psr_et 1 + set_spr_addr ok1,lr + set_icc 0x1 0 + tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok1: + set_spr_addr bad,lr + set_icc 0x2 0 + tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x3 0 + tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok4,lr + set_icc 0x4 0 + tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok4: + set_psr_et 1 + set_spr_addr ok5,lr + set_icc 0x5 0 + tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_spr_addr bad,lr + set_icc 0x6 0 + tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x7 0 + tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok8,lr + set_icc 0x8 0 + tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok8: + set_psr_et 1 + set_spr_addr ok9,lr + set_icc 0x9 0 + tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_spr_addr bad,lr + set_icc 0xa 0 + tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xb 0 + tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr okc,lr + set_icc 0xc 0 + tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_icc 0xd 0 + tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_spr_addr bad,lr + set_icc 0xe 0 + tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xf 0 + tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/tp.cgs b/sim/testsuite/sim/frv/tp.cgs new file mode 100644 index 0000000..2709e31 --- /dev/null +++ b/sim/testsuite/sim/frv/tp.cgs @@ -0,0 +1,101 @@ +# frv testcase for tp $ICCi_2,$GRi,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global tp +tp: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_psr_et 1 + set_spr_addr ok0,lr + set_icc 0x0 0 + tp icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok0: + set_psr_et 1 + set_spr_addr ok1,lr + set_icc 0x1 0 + tp icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok1: + set_psr_et 1 + set_spr_addr ok2,lr + set_icc 0x2 0 + tp icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_psr_et 1 + set_spr_addr ok3,lr + set_icc 0x3 0 + tp icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_psr_et 1 + set_spr_addr ok4,lr + set_icc 0x4 0 + tp icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok4: + set_psr_et 1 + set_spr_addr ok5,lr + set_icc 0x5 0 + tp icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_psr_et 1 + set_spr_addr ok6,lr + set_icc 0x6 0 + tp icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_icc 0x7 0 + tp icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_spr_addr bad,lr + set_icc 0x8 0 + tp icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x9 0 + tp icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xa 0 + tp icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xb 0 + tp icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xc 0 + tp icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xd 0 + tp icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xe 0 + tp icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xf 0 + tp icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/tra.cgs b/sim/testsuite/sim/frv/tra.cgs new file mode 100644 index 0000000..368c83a --- /dev/null +++ b/sim/testsuite/sim/frv/tra.cgs @@ -0,0 +1,117 @@ +# frv testcase for tra $GRi,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global tra +tra: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_psr_et 1 + set_spr_addr ok0,lr + set_icc 0x0 0 + tra gr7,gr8 ; should branch to tbr + (128 + 4)*16 +bad0: + fail +ok0: + test_spr_addr bad0,pcsr + set_psr_et 1 + set_spr_addr ok1,lr + set_icc 0x1 0 + tra gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok1: + set_psr_et 1 + set_spr_addr ok2,lr + set_icc 0x2 0 + tra gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_psr_et 1 + set_spr_addr ok3,lr + set_icc 0x3 0 + tra gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_psr_et 1 + set_spr_addr ok4,lr + set_icc 0x4 0 + tra gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok4: + set_psr_et 1 + set_spr_addr ok5,lr + set_icc 0x5 0 + tra gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok5: + set_psr_et 1 + set_spr_addr ok6,lr + set_icc 0x6 0 + tra gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_icc 0x7 0 + tra gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_psr_et 1 + set_spr_addr ok8,lr + set_icc 0x8 0 + tra gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok8: + set_psr_et 1 + set_spr_addr ok9,lr + set_icc 0x9 0 + tra gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_psr_et 1 + set_spr_addr oka,lr + set_icc 0xa 0 + tra gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_icc 0xb 0 + tra gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_psr_et 1 + set_spr_addr okc,lr + set_icc 0xc 0 + tra gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_icc 0xd 0 + tra gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_icc 0xe 0 + tra gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_icc 0xf 0 + tra gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass diff --git a/sim/testsuite/sim/frv/tv.cgs b/sim/testsuite/sim/frv/tv.cgs new file mode 100644 index 0000000..d173f29 --- /dev/null +++ b/sim/testsuite/sim/frv/tv.cgs @@ -0,0 +1,101 @@ +# frv testcase for tv $ICCi_2,$GRi,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global tv +tv: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_spr_addr bad,lr + set_icc 0x0 0 + tv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x1 0 + tv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok2,lr + set_icc 0x2 0 + tv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok2: + set_psr_et 1 + set_spr_addr ok3,lr + set_icc 0x3 0 + tv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok3: + set_spr_addr bad,lr + set_icc 0x4 0 + tv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x5 0 + tv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok6,lr + set_icc 0x6 0 + tv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok6: + set_psr_et 1 + set_spr_addr ok7,lr + set_icc 0x7 0 + tv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok7: + set_spr_addr bad,lr + set_icc 0x8 0 + tv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0x9 0 + tv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr oka,lr + set_icc 0xa 0 + tv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_icc 0xb 0 + tv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_spr_addr bad,lr + set_icc 0xc 0 + tv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_icc 0xd 0 + tv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr oke,lr + set_icc 0xe 0 + tv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_icc 0xf 0 + tv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail diff --git a/sim/testsuite/sim/frv/udiv.cgs b/sim/testsuite/sim/frv/udiv.cgs new file mode 100644 index 0000000..35cfa8c --- /dev/null +++ b/sim/testsuite/sim/frv/udiv.cgs @@ -0,0 +1,48 @@ +# frv testcase for udiv $GRi,$GRj,$GRk +# mach: frv fr500 fr400 + + .include "testutils.inc" + + start + + .global udiv +udiv: + ; simple division 12 / 3 + set_gr_immed 0x00000003,gr2 + set_gr_immed 0x0000000c,gr3 + udiv gr3,gr2,gr3 + test_gr_immed 0x00000003,gr2 + test_gr_immed 0x00000004,gr3 + + ; example 1 from udiv in the fr30 manual + set_gr_limmed 0x0123,0x4567,gr2 + set_gr_limmed 0xfedc,0xba98,gr3 + udiv gr3,gr2,gr3 + test_gr_limmed 0x0123,0x4567,gr2 + test_gr_immed 0x000000e0,gr3 + + ; set up exception handler + set_psr_et 1 + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr17 + inc_gr_immed 0x170,gr17 ; address of exception handler + set_bctrlr_0_0 gr17 + set_spr_immed 128,lcr + set_gr_immed 0,gr15 + + ; divide by zero + set_spr_addr ok1,lr + set_gr_addr e1,gr17 +e1: udiv gr1,gr0,gr2 ; divide by zero + test_gr_immed 1,gr15 + + pass + +ok1: ; exception handler for divide by zero + test_spr_bits 0x18,3,0x1,isr ; isr.dtt is set + test_spr_gr epcr0,gr17 ; return address set + test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid + test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set + inc_gr_immed 1,gr15 + rett 0 + fail diff --git a/sim/testsuite/sim/frv/udivi.cgs b/sim/testsuite/sim/frv/udivi.cgs new file mode 100644 index 0000000..6a50590 --- /dev/null +++ b/sim/testsuite/sim/frv/udivi.cgs @@ -0,0 +1,49 @@ +# frv testcase for udivi $GRi,$s12,$GRk +# mach: frv fr500 fr400 + + .include "testutils.inc" + + start + + .global udivi +udivi: + ; simple division 12 / 3 + set_gr_immed 0x0000000c,gr3 + udivi gr3,3,gr3 + test_gr_immed 0x00000004,gr3 + + ; random example + set_gr_limmed 0xfedc,0xba98,gr3 + udivi gr3,0x7ff,gr3 + test_gr_limmed 0x001f,0xdf93,gr3 + + ; random example + set_gr_limmed 0xffff,0xffff,gr3 + udivi gr3,-2048,gr3 + test_gr_immed 1,gr3 + + ; set up exception handler + set_psr_et 1 + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr17 + inc_gr_immed 0x170,gr17 ; address of exception handler + set_bctrlr_0_0 gr17 + set_spr_immed 128,lcr + set_gr_immed 0,gr15 + + ; divide by zero + set_spr_addr ok1,lr + set_gr_addr e1,gr17 +e1: udivi gr1,0,gr2 ; divide by zero + test_gr_immed 1,gr15 + + pass + +ok1: ; exception handler for divide by zero + test_spr_bits 0x18,3,0x1,isr ; isr.dtt is set + test_spr_gr epcr0,gr17 ; return address set + test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid + test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set + inc_gr_immed 1,gr15 + rett 0 + fail diff --git a/sim/testsuite/sim/frv/umul.cgs b/sim/testsuite/sim/frv/umul.cgs new file mode 100644 index 0000000..6c61221 --- /dev/null +++ b/sim/testsuite/sim/frv/umul.cgs @@ -0,0 +1,76 @@ +# frv testcase for umul $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global umul +umul: + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + umul gr7,gr8,gr8 + test_gr_immed 0,gr8 + test_gr_immed 6,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed 2,gr8 + umul gr7,gr8,gr8 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed 2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + umul gr7,gr8,gr8 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed 2,gr8 + umul gr7,gr8,gr8 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + umul gr7,gr8,gr8 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result + set_gr_immed 2,gr8 + umul gr7,gr8,gr8 + test_gr_immed 0,gr8 + test_gr_limmed 0x7fff,0xfffe,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed 2,gr8 + umul gr7,gr8,gr8 + test_gr_immed 0,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + set_gr_limmed 0x8000,0x0000,gr7 ; 33 bit result + set_gr_immed 2,gr8 + umul gr7,gr8,gr8 + test_gr_immed 1,gr8 + test_gr_immed 0x00000000,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result + set_gr_limmed 0x7fff,0xffff,gr8 + umul gr7,gr8,gr8 + test_gr_limmed 0x3fff,0xffff,gr8 + test_gr_immed 0x00000001,gr9 + + set_gr_limmed 0x8000,0x0000,gr7 ; max positive result + set_gr_limmed 0x8000,0x0000,gr8 + umul gr7,gr8,gr8 + test_gr_limmed 0x4000,0x0000,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0xffff,0xffff,gr7 ; max positive result + set_gr_limmed 0xffff,0xffff,gr8 + umul gr7,gr8,gr8 + test_gr_limmed 0xffff,0xfffe,gr8 + test_gr_immed 1,gr9 + + pass diff --git a/sim/testsuite/sim/frv/umulcc.cgs b/sim/testsuite/sim/frv/umulcc.cgs new file mode 100644 index 0000000..c2b5cff --- /dev/null +++ b/sim/testsuite/sim/frv/umulcc.cgs @@ -0,0 +1,98 @@ +# frv testcase for umulcc $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global umulcc +umulcc: + set_gr_immed 3,gr7 ; multiply small numbers + set_gr_immed 2,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + umulcc gr7,gr8,gr8,icc0 + test_icc 0 0 1 1 icc0 + test_gr_immed 0,gr8 + test_gr_immed 6,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_gr_immed 2,gr8 + set_icc 0x0e,0 ; Set mask opposite of expected + umulcc gr7,gr8,gr8,icc0 + test_icc 0 0 1 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed 2,gr7 ; multiply by 1 + set_gr_immed 1,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + umulcc gr7,gr8,gr8,icc0 + test_icc 0 0 1 1 icc0 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_gr_immed 2,gr8 + set_icc 0x0b,0 ; Set mask opposite of expected + umulcc gr7,gr8,gr8,icc0 + test_icc 0 1 1 1 icc0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 2,gr7 ; multiply by 0 + set_gr_immed 0,gr8 + set_icc 0x0a,0 ; Set mask opposite of expected + umulcc gr7,gr8,gr8,icc0 + test_icc 0 1 1 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result + set_gr_immed 2,gr8 + set_icc 0x0f,0 ; Set mask opposite of expected + umulcc gr7,gr8,gr8,icc0 + test_icc 0 0 1 1 icc0 + test_gr_immed 0,gr8 + test_gr_limmed 0x7fff,0xfffe,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_gr_immed 2,gr8 + set_icc 0x0e,0 ; Set mask opposite of expected + umulcc gr7,gr8,gr8,icc0 + test_icc 0 0 1 0 icc0 + test_gr_immed 0,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + set_gr_limmed 0x8000,0x0000,gr7 ; 33 bit result + set_gr_immed 2,gr8 + set_icc 0x0d,0 ; Set mask opposite of expected + umulcc gr7,gr8,gr8,icc0 + test_icc 0 0 0 1 icc0 + test_gr_immed 1,gr8 + test_gr_immed 0x00000000,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result + set_gr_limmed 0x7fff,0xffff,gr8 + set_icc 0x0d,0 ; Set mask opposite of expected + umulcc gr7,gr8,gr8,icc0 + test_icc 0 0 0 1 icc0 + test_gr_limmed 0x3fff,0xffff,gr8 + test_gr_immed 1,gr9 + + set_gr_limmed 0x8000,0x0000,gr7 ; max positive result + set_gr_limmed 0x8000,0x0000,gr8 + set_icc 0x0d,0 ; Set mask opposite of expected + umulcc gr7,gr8,gr8,icc0 + test_icc 0 0 0 1 icc0 + test_gr_limmed 0x4000,0x0000,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0xffff,0xffff,gr7 ; max positive result + set_gr_limmed 0xffff,0xffff,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + umulcc gr7,gr8,gr8,icc0 + test_icc 1 0 0 1 icc0 + test_gr_limmed 0xffff,0xfffe,gr8 + test_gr_immed 1,gr9 + + pass diff --git a/sim/testsuite/sim/frv/umuli.cgs b/sim/testsuite/sim/frv/umuli.cgs new file mode 100644 index 0000000..6f1b9c1 --- /dev/null +++ b/sim/testsuite/sim/frv/umuli.cgs @@ -0,0 +1,87 @@ +# frv testcase for umuli $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global umuli +umuli: + set_gr_immed 3,gr7 ; multiply small numbers + set_icc 0x0f,0 ; Set mask opposite of expected + umuli gr7,2,gr8 + test_icc 1 1 1 1 icc0 + test_gr_immed 0,gr8 + test_gr_immed 6,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_icc 0x0e,0 ; Set mask opposite of expected + umuli gr7,2,gr8 + test_icc 1 1 1 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed 2,gr7 ; multiply by 1 + set_icc 0x0f,0 ; Set mask opposite of expected + umuli gr7,1,gr8 + test_icc 1 1 1 1 icc0 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_icc 0x0b,0 ; Set mask opposite of expected + umuli gr7,2,gr8 + test_icc 1 0 1 1 icc0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 2,gr7 ; multiply by 0 + set_icc 0x0a,0 ; Set mask opposite of expected + umuli gr7,0,gr8 + test_icc 1 0 1 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result + set_icc 0x0f,0 ; Set mask opposite of expected + umuli gr7,2,gr8 + test_icc 1 1 1 1 icc0 + test_gr_immed 0,gr8 + test_gr_limmed 0x7fff,0xfffe,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_icc 0x0e,0 ; Set mask opposite of expected + umuli gr7,2,gr8 + test_icc 1 1 1 0 icc0 + test_gr_immed 0,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + set_gr_limmed 0x8000,0x0000,gr7 ; 33 bit result + set_icc 0x09,0 ; Set mask opposite of expected + umuli gr7,2,gr8 + test_icc 1 0 0 1 icc0 + test_gr_immed 1,gr8 + test_gr_immed 0x00000000,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result + set_icc 0x0d,0 ; Set mask opposite of expected + umuli gr7,0x7ff,gr8 + test_icc 1 1 0 1 icc0 + test_gr_immed 0x3ff,gr8 + test_gr_limmed 0x7fff,0xf801,gr9 + + set_gr_limmed 0x8000,0x0000,gr7 ; max positive result + set_icc 0x09,0 ; Set mask opposite of expected + umuli gr7,-2048,gr8 + test_icc 1 0 0 1 icc0 + test_gr_limmed 0x7fff,0xfc00,gr8 + test_gr_limmed 0x0000,0x0000,gr9 + + set_gr_limmed 0xffff,0xffff,gr7 ; max positive result + set_icc 0x05,0 ; Set mask opposite of expected + umuli gr7,-1,gr8 + test_icc 0 1 0 1 icc0 + test_gr_limmed 0xffff,0xfffe,gr8 + test_gr_immed 1,gr9 + + pass diff --git a/sim/testsuite/sim/frv/umulicc.cgs b/sim/testsuite/sim/frv/umulicc.cgs new file mode 100644 index 0000000..0d0d0c1 --- /dev/null +++ b/sim/testsuite/sim/frv/umulicc.cgs @@ -0,0 +1,87 @@ +# frv testcase for umulicc $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global umulicc +umulicc: + set_gr_immed 3,gr7 ; multiply small numbers + set_icc 0x0f,0 ; Set mask opposite of expected + umulicc gr7,2,gr8,icc0 + test_icc 0 0 1 1 icc0 + test_gr_immed 0,gr8 + test_gr_immed 6,gr9 + + set_gr_immed 1,gr7 ; multiply by 1 + set_icc 0x0e,0 ; Set mask opposite of expected + umulicc gr7,2,gr8,icc0 + test_icc 0 0 1 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed 2,gr7 ; multiply by 1 + set_icc 0x0f,0 ; Set mask opposite of expected + umulicc gr7,1,gr8,icc0 + test_icc 0 0 1 1 icc0 + test_gr_immed 0,gr8 + test_gr_immed 2,gr9 + + set_gr_immed 0,gr7 ; multiply by 0 + set_icc 0x0b,0 ; Set mask opposite of expected + umulicc gr7,2,gr8,icc0 + test_icc 0 1 1 1 icc0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_immed 2,gr7 ; multiply by 0 + set_icc 0x0a,0 ; Set mask opposite of expected + umulicc gr7,0,gr8,icc0 + test_icc 0 1 1 0 icc0 + test_gr_immed 0,gr8 + test_gr_immed 0,gr9 + + set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result + set_icc 0x0f,0 ; Set mask opposite of expected + umulicc gr7,2,gr8,icc0 + test_icc 0 0 1 1 icc0 + test_gr_immed 0,gr8 + test_gr_limmed 0x7fff,0xfffe,gr9 + + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result + set_icc 0x0e,0 ; Set mask opposite of expected + umulicc gr7,2,gr8,icc0 + test_icc 0 0 1 0 icc0 + test_gr_immed 0,gr8 + test_gr_limmed 0x8000,0x0000,gr9 + + set_gr_limmed 0x8000,0x0000,gr7 ; 33 bit result + set_icc 0x09,0 ; Set mask opposite of expected + umulicc gr7,2,gr8,icc0 + test_icc 0 0 0 1 icc0 + test_gr_immed 1,gr8 + test_gr_immed 0x00000000,gr9 + + set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result + set_icc 0x0d,0 ; Set mask opposite of expected + umulicc gr7,0x1ff,gr8,icc0 + test_icc 0 0 0 1 icc0 + test_gr_immed 0xff,gr8 + test_gr_limmed 0x7fff,0xfe01,gr9 + + set_gr_limmed 0x8000,0x0000,gr7 ; max positive result + set_icc 0x09,0 ; Set mask opposite of expected + umulicc gr7,-512,gr8,icc0 + test_icc 0 0 0 1 icc0 + test_gr_limmed 0x7fff,0xff00,gr8 + test_gr_limmed 0x0000,0x0000,gr9 + + set_gr_limmed 0xffff,0xffff,gr7 ; max positive result + set_icc 0x05,0 ; Set mask opposite of expected + umulicc gr7,-1,gr8,icc0 + test_icc 1 0 0 1 icc0 + test_gr_limmed 0xffff,0xfffe,gr8 + test_gr_immed 1,gr9 + + pass diff --git a/sim/testsuite/sim/frv/xor.cgs b/sim/testsuite/sim/frv/xor.cgs new file mode 100644 index 0000000..97310e4 --- /dev/null +++ b/sim/testsuite/sim/frv/xor.cgs @@ -0,0 +1,38 @@ +# frv testcase for xor $GRi,$GRj,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global xor +xor: + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x07,0 ; Set mask opposite of expected + xor gr7,gr8,gr8 + test_icc 0 1 1 1 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + + set_gr_immed 0x00000000,gr7 + set_gr_immed 0x00000000,gr8 + set_icc 0x08,0 ; Set mask opposite of expected + xor gr7,gr8,gr8 + test_icc 1 0 0 0 icc0 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_icc 0x0b,0 ; Set mask opposite of expected + xor gr7,gr8,gr8 + test_icc 1 0 1 1 icc0 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0x0000,gr7 + set_gr_limmed 0x0000,0xbeef,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + xor gr7,gr8,gr8 + test_icc 0 1 0 1 icc0 + test_gr_limmed 0xdead,0xbeef,gr8 + + pass diff --git a/sim/testsuite/sim/frv/xorcc.cgs b/sim/testsuite/sim/frv/xorcc.cgs new file mode 100644 index 0000000..9516b78 --- /dev/null +++ b/sim/testsuite/sim/frv/xorcc.cgs @@ -0,0 +1,38 @@ +# frv testcase for xorcc $GRi,$GRj,$GRk,$ICCi_1 +# mach: all + + .include "testutils.inc" + + start + + .global xorcc +xorcc: + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0x5555,0x5555,gr8 + set_icc 0x07,0 ; Set mask opposite of expected + xorcc gr7,gr8,gr8,icc0 + test_icc 1 0 1 1 icc0 + test_gr_limmed 0xffff,0xffff,gr8 + + set_gr_immed 0x00000000,gr7 + set_gr_immed 0x00000000,gr8 + set_icc 0x08,0 ; Set mask opposite of expected + xorcc gr7,gr8,gr8,icc0 + test_icc 0 1 0 0 icc0 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_icc 0x0b,0 ; Set mask opposite of expected + xorcc gr7,gr8,gr8,icc0 + test_icc 0 1 1 1 icc0 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xdead,0x0000,gr7 + set_gr_limmed 0x0000,0xbeef,gr8 + set_icc 0x05,0 ; Set mask opposite of expected + xorcc gr7,gr8,gr8,icc0 + test_icc 1 0 0 1 icc0 + test_gr_limmed 0xdead,0xbeef,gr8 + + pass diff --git a/sim/testsuite/sim/frv/xorcr.cgs b/sim/testsuite/sim/frv/xorcr.cgs new file mode 100644 index 0000000..bcb153b --- /dev/null +++ b/sim/testsuite/sim/frv/xorcr.cgs @@ -0,0 +1,59 @@ +# frv testcase for xorcr $CCi,$CCj,$CCk +# mach: all + + .include "testutils.inc" + + start + + .global xorcr +xorcr: + set_spr_immed 0x1b1b,cccr + xorcr cc7,cc7,cc3 + test_spr_immed 0x1b1b,cccr + + xorcr cc7,cc6,cc3 + test_spr_immed 0x1b1b,cccr + + xorcr cc7,cc5,cc3 + test_spr_immed 0x1b1b,cccr + + xorcr cc7,cc4,cc3 + test_spr_immed 0x1b1b,cccr + + xorcr cc6,cc7,cc3 + test_spr_immed 0x1b1b,cccr + + xorcr cc6,cc6,cc3 + test_spr_immed 0x1b1b,cccr + + xorcr cc6,cc5,cc3 + test_spr_immed 0x1b1b,cccr + + xorcr cc6,cc4,cc3 + test_spr_immed 0x1b1b,cccr + + xorcr cc5,cc7,cc3 + test_spr_immed 0x1b1b,cccr + + xorcr cc5,cc6,cc3 + test_spr_immed 0x1b1b,cccr + + xorcr cc5,cc5,cc3 + test_spr_immed 0x1b9b,cccr + + xorcr cc5,cc4,cc3 + test_spr_immed 0x1bdb,cccr + + xorcr cc4,cc7,cc3 + test_spr_immed 0x1bdb,cccr + + xorcr cc4,cc6,cc3 + test_spr_immed 0x1bdb,cccr + + xorcr cc4,cc5,cc3 + test_spr_immed 0x1bdb,cccr + + xorcr cc4,cc4,cc3 + test_spr_immed 0x1b9b,cccr + + pass diff --git a/sim/testsuite/sim/frv/xori.cgs b/sim/testsuite/sim/frv/xori.cgs new file mode 100644 index 0000000..ed26660 --- /dev/null +++ b/sim/testsuite/sim/frv/xori.cgs @@ -0,0 +1,35 @@ +# frv testcase for xori $GRi,$s12,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global xori +xori: + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_icc 0x07,0 ; Set mask opposite of expected + xori gr7,0x555,gr8 + test_icc 0 1 1 1 icc0 + test_gr_limmed 0xaaaa,0xafff,gr8 + + set_gr_immed 0x00000000,gr7 + set_gr_immed 0x00000000,gr8 + set_icc 0x08,0 ; Set mask opposite of expected + xori gr7,0,gr8 + test_icc 1 0 0 0 icc0 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_icc 0x0b,0 ; Set mask opposite of expected + xori gr7,0x2aa,gr8 + test_icc 1 0 1 1 icc0 + test_gr_limmed 0xaaaa,0xa800,gr8 + + set_gr_limmed 0xdead,0x0000,gr7 + set_icc 0x05,0 ; Set mask opposite of expected + xori gr7,-273,gr8 + test_icc 0 1 0 1 icc0 + test_gr_limmed 0x2152,0xfeef,gr8 + + pass diff --git a/sim/testsuite/sim/frv/xoricc.cgs b/sim/testsuite/sim/frv/xoricc.cgs new file mode 100644 index 0000000..b473620 --- /dev/null +++ b/sim/testsuite/sim/frv/xoricc.cgs @@ -0,0 +1,36 @@ +# frv testcase for xoricc $GRi,$s10,$GRk,$ICCi_1 +# mach: all + + .include "testutils.inc" + + start + + .global xoricc +xoricc: + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_icc 0x07,0 ; Set mask opposite of expected + xoricc gr7,0x155,gr8,icc0 + test_icc 1 0 1 1 icc0 + test_gr_limmed 0xaaaa,0xabff,gr8 + + set_gr_immed 0x00000000,gr7 + set_gr_immed 0x00000000,gr8 + set_icc 0x08,0 ; Set mask opposite of expected + xoricc gr7,0,gr8,icc0 + test_icc 0 1 0 0 icc0 + test_gr_immed 0x00000000,gr8 + + set_gr_limmed 0xaaaa,0xaaaa,gr7 + set_gr_limmed 0xaaaa,0xaaaa,gr8 + set_icc 0x07,0 ; Set mask opposite of expected + xoricc gr7,0xaa,gr8,icc0 + test_icc 1 0 1 1 icc0 + test_gr_limmed 0xaaaa,0xaa00,gr8 + + set_gr_limmed 0xdead,0xb000,gr7 + set_icc 0x0d,0 ; Set mask opposite of expected + xoricc gr7,-273,gr8,icc0 + test_icc 0 0 0 1 icc0 + test_gr_limmed 0x2152,0x4eef,gr8 + + pass diff --git a/sim/testsuite/sim/h8300/ChangeLog b/sim/testsuite/sim/h8300/ChangeLog new file mode 100644 index 0000000..4dc6559 --- /dev/null +++ b/sim/testsuite/sim/h8300/ChangeLog @@ -0,0 +1,84 @@ +2003-07-22 Michael Snyder + + * cmpw.s: Add test for less-than-zero immediate. + * shll.s: Test for shll reg, reg. + * shlr.s: Test for shlr reg, reg. + * mova.s: Add dozens of new mova tests. + +2003-05-30 Alexandre Oliva + + * allinsn.exp: Fix typos introduced on 2003-05-27. + +2003-05-29 Michael Snyder + + * tas.s: Use er4 for h8h and h8s, er3 for h8sx. + +2003-05-28 Michael Snyder + + * subs.s: New file. + * subx.s: New file. + * allinsn.exp: Add new subs and subx tests. + * testutils.inc: Simplify (and fix) set_carry_flag. + (clear_carry_flag, set_zero_flag, clear_zero_flag...): New macros. + * addx.s: Use simplified set_carry_flag. + +2003-05-27 Michael Snyder + + * tas.s: New file. + * band.s: New file. + * biand.s: New file. + * allinsn.exp: Add tas, band, biand tests. + * brabc.s: Add abs8 test. + * bset.s: Add bset/ne, bclr/ne tests. + +2003-05-23 Michael Snyder + + * and.b.s: Add andc exr. + * or.b.s: Add orc.exr. + * xor.b.s: Add xor exr. + + * jmp.s: Fix 8-bit indirect test. Add 7-bit vector test. + +2003-05-22 Michael Snyder + + * stack.s: Add rte/l and rts/l tests. + * allinsn.exp: Add stack tests. + +2003-05-21 Michael Snyder + + * stack.s: New file: test stack operations. + * stack.s: Add bsr, jsr tests. + * stack.s: Add trapa, rte tests. + + * div.s: Corrections for size of dividend. + +2003-05-20 Michael Snyder + + * mul.s: Corrections for unsigned multiply. + + * div.s: New file, test div instructions. + * allinsn.exp: Add div test. + +2003-05-19 Michael Snyder + + * mul.s: New file, test mul instructions. + * allinsn.exp: Add mul test. + +2003-05-14 Michael Snyder + + * addb.s, addw.s, addl.s, addw.s, addx.s, andb.s, andw.s, andl.s, + bfld.s, brabc.s, bra.s, bset.s, cmpb.s, cmpw.s, cmpl.s, daa.s, + das.s, dec.s, extw.s, extl.s, inc.s, jmp.s, ldc.s, ldm.s, mac.s, + mova.s, movb.s, movw.s, movl.s, movmd.s, movsd.s, neg.s, nop.s, + not.s, orb.s, orw.s, orl.s, rotl.s, rotr.s, rotxl.s, rotxr.s, + shal.s, shar.s, shll.s, shlr.s, stc.s, subb.s, subw.s, subl.s, + xorb.s, xorw.s, xorl.s: New files. + * allinsn.exp: New file. + +Local Variables: +mode: change-log +left-margin: 8 +fill-column: 74 +version-control: never +change-log-default-name: "ChangeLog" +End: diff --git a/sim/testsuite/sim/h8300/addb.s b/sim/testsuite/sim/h8300/addb.s new file mode 100644 index 0000000..f1e4ebf --- /dev/null +++ b/sim/testsuite/sim/h8300/addb.s @@ -0,0 +1,778 @@ +# Hitachi H8 testcase 'add.b' +# mach(): all +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + # Instructions tested: + # add.b #xx:8, rd ; 8 rd xxxxxxxx + # add.b #xx:8, @erd ; 7 d rd ???? 8 ???? xxxxxxxx + # add.b #xx:8, @erd+ ; 0 1 7 4 6 c rd 1??? 8 ???? xxxxxxxx + # add.b #xx:8, @erd- ; 0 1 7 6 6 c rd 1??? 8 ???? xxxxxxxx + # add.b #xx:8, @+erd ; 0 1 7 5 6 c rd 1??? 8 ???? xxxxxxxx + # add.b #xx:8, @-erd ; 0 1 7 7 6 c rd 1??? 8 ???? xxxxxxxx + # add.b #xx:8, @(d:16, erd) ; 0 1 7 4 6 e b30 | rd, b31, dd:16 8 ???? xxxxxxxx + # add.b #xx:8, @(d:32, erd) ; 7 8 b30 | rd, 4 6 a 2 8 dd:32 8 ???? xxxxxxxx + # add.b #xx:8, @aa:8 ; 7 f aaaaaaaa 8 ???? xxxxxxxx + # add.b #xx:8, @aa:16 ; 6 a 1 1??? aa:16 8 ???? xxxxxxxx + # add.b #xx:8, @aa:32 ; 6 a 3 1??? aa:32 8 ???? xxxxxxxx + # add.b rs, rd ; 0 8 rs rd + # add.b reg8, @erd ; 7 d rd ???? 0 8 rs ???? + # add.b reg8, @erd+ ; 0 1 7 9 8 rd 1 rs + # add.b reg8, @erd- ; 0 1 7 9 a rd 1 rs + # add.b reg8, @+erd ; 0 1 7 9 9 rd 1 rs + # add.b reg8, @-erd ; 0 1 7 9 b rd 1 rs + # add.b reg8, @(d:16, erd) ; 0 1 7 9 c b30 | rd32, 1 rs8 imm16 + # add.b reg8, @(d:32, erd) ; 0 1 7 9 d b31 | rd32, 1 rs8 imm32 + # add.b reg8, @aa:8 ; 7 f aaaaaaaa 0 8 rs ???? + # add.b reg8, @aa:16 ; 6 a 1 1??? aa:16 0 8 rs ???? + # add.b reg8, @aa:32 ; 6 a 3 1??? aa:32 0 8 rs ???? + # + + # Coming soon: + # add.b #xx:8, @(d:2, erd) ; 0 1 7 b30 | b21 | dd:2, 8 ???? xxxxxxxx + # add.b reg8, @(d:2, erd) ; 0 1 7 9 dd:2 rd32 1 rs8 + # ... + +.data +pre_byte: .byte 0 +byte_dest: .byte 0 +post_byte: .byte 0 + + start + +add_b_imm8_reg: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; add.b #xx:8,Rd + add.b #5:8, r0l ; Immediate 8-bit src, reg8 dst + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0xa5aa r0 ; add result: a5 + 5 +.if (sim_cpu) ; non-zero means h8300h, s, or sx + test_h_gr32 0xa5a5a5aa er0 ; add result: a5 + 5 +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +add_b_imm8_rdind: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.b #xx:8,@eRd + mov #byte_dest, er0 + add.b #5:8, @er0 ; Immediate 8-bit src, reg indirect dst +;;; .word 0x7d00 +;;; .word 0x8005 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 byte_dest, er0 ; er0 still contains address + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the add to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #5, r0l + beq .L1 + fail +.L1: + +add_b_imm8_rdpostinc: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.b #xx:8,@eRd+ + mov #byte_dest, er0 + add.b #5:8, @er0+ ; Immediate 8-bit src, reg post-inc dst +;;; .word 0x0174 +;;; .word 0x6c08 +;;; .word 0x8005 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 post_byte, er0 ; er0 contains address plus one + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the add to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #10, r0l + beq .L2 + fail +.L2: + +add_b_imm8_rdpostdec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.b #xx:8,@eRd- + mov #byte_dest, er0 + add.b #5:8, @er0- ; Immediate 8-bit src, reg post-dec dst +;;; .word 0x0176 +;;; .word 0x6c08 +;;; .word 0x8005 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 pre_byte, er0 ; er0 contains address minus one + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the add to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #15, r0l + beq .L3 + fail +.L3: + +add_b_imm8_rdpreinc: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.b #xx:8,@+eRd + mov #pre_byte, er0 + add.b #5:8, @+er0 ; Immediate 8-bit src, reg pre-inc dst +;;; .word 0x0175 +;;; .word 0x6c08 +;;; .word 0x8005 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 byte_dest, er0 ; er0 contains destination address + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the add to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #20, r0l + beq .L4 + fail +.L4: + +add_b_imm8_rdpredec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.b #xx:8,@-eRd + mov #post_byte, er0 + add.b #5:8, @-er0 ; Immediate 8-bit src, reg pre-dec dst +;;; .word 0x0177 +;;; .word 0x6c08 +;;; .word 0x8005 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 byte_dest, er0 ; er0 contains destination address + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the add to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #25, r0l + beq .L5 + fail +.L5: + +add_b_imm8_disp16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.b #xx:8,@(dd:16, eRd) + mov #post_byte, er0 + add.b #5:8, @(-1:16, er0) ; Immediate 8-bit src, 16-bit reg disp dest. +;;; .word 0x0174 +;;; .word 0x6e08 +;;; .word 0xffff +;;; .word 0x8005 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 post_byte, er0 ; er0 contains address plus one + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the add to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #30, r0l + beq .L6 + fail +.L6: + +add_b_imm8_disp32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.b #xx:8,@(dd:32, eRd) + mov #pre_byte, er0 + add.b #5:8, @(1:32, er0) ; Immediate 8-bit src, 32-bit reg disp. dest. +;;; .word 0x7804 +;;; .word 0x6a28 +;;; .word 0x0000 +;;; .word 0x0001 +;;; .word 0x8005 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 pre_byte, er0 ; er0 contains address minus one + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the add to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #35, r0l + beq .L7 + fail +.L7: + +add_b_imm8_abs8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.b reg8,@aa:8 + ;; NOTE: for abs8, we will use the SBR register as a base, + ;; since otherwise we would have to make sure that the destination + ;; was in the zero page. + ;; + mov #byte_dest-100, er0 + ldc er0, sbr + add.b #5, @100:8 ; 8-bit reg src, 8-bit absolute dest +;;; .word 0x7f64 +;;; .word 0x8005 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 byte_dest-100, er0 ; reg 0 has base address + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the add to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #40, r0l + beq .L8 + fail +.L8: + +add_b_imm8_abs16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.b #xx:8,@aa:16 + add.b #5:8, @byte_dest:16 ; Immediate 8-bit src, 16-bit absolute dest +;;; .word 0x6a18 +;;; .word byte_dest +;;; .word 0x8005 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the add to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #45, r0l + beq .L9 + fail +.L9: + +add_b_imm8_abs32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.b #xx:8,@aa:32 + add.b #5:8, @byte_dest:32 ; Immediate 8-bit src, 32-bit absolute dest +;;; .word 0x6a38 +;;; .long byte_dest +;;; .word 0x8005 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the add to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #50, r0l + beq .L10 + fail +.L10: + +.endif + +add_b_reg8_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; add.b Rs,Rd + mov.b #5, r0h + add.b r0h, r0l ; Register operand + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0x05aa r0 ; add result: a5 + 5 +.if (sim_cpu) ; non-zero means h8300h, s, or sx + test_h_gr32 0xa5a505aa er0 ; add result: a5 + 5 +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +add_b_reg8_rdind: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.b rs8,@eRd ; Add to register indirect + mov #byte_dest, er0 + mov #5, r1l + add.b r1l, @er0 ; reg8 src, reg indirect dest +;;; .word 0x7d00 +;;; .word 0x0890 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 byte_dest er0 ; er0 still contains address + test_h_gr32 0xa5a5a505 er1 ; er1 has the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the add to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #55, r0l + beq .L11 + fail +.L11: + +add_b_reg8_rdpostinc: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.b rs8,@eRd+ ; Add to register post-increment + mov #byte_dest, er0 + mov #5, r1l + add.b r1l, @er0+ ; reg8 src, reg post-incr dest +;;; .word 0x0179 +;;; .word 0x8019 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 post_byte er0 ; er0 contains address plus one + test_h_gr32 0xa5a5a505 er1 ; er1 has the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the add to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #60, r0l + beq .L12 + fail +.L12: + +add_b_reg8_rdpostdec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.b rs8,@eRd- ; Add to register post-decrement + mov #byte_dest, er0 + mov #5, r1l + add.b r1l, @er0- ; reg8 src, reg post-decr dest +;;; .word 0x0179 +;;; .word 0xa019 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 pre_byte er0 ; er0 contains address minus one + test_h_gr32 0xa5a5a505 er1 ; er1 has the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the add to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #65, r0l + beq .L13 + fail +.L13: + +add_b_reg8_rdpreinc: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.b rs8,@+eRd ; Add to register pre-increment + mov #pre_byte, er0 + mov #5, r1l + add.b r1l, @+er0 ; reg8 src, reg pre-incr dest +;;; .word 0x0179 +;;; .word 0x9019 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 byte_dest er0 ; er0 contains destination address + test_h_gr32 0xa5a5a505 er1 ; er1 has the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the add to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #70, r0l + beq .L14 + fail +.L14: + +add_b_reg8_rdpredec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.b rs8,@-eRd ; Add to register pre-decrement + mov #post_byte, er0 + mov #5, r1l + add.b r1l, @-er0 ; reg8 src, reg pre-decr dest +;;; .word 0x0179 +;;; .word 0xb019 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 byte_dest er0 ; er0 contains destination address + test_h_gr32 0xa5a5a505 er1 ; er1 has the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the add to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #75, r0l + beq .L15 + fail +.L15: + +add_b_reg8_disp16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.b rs8,@(dd:16, eRd) ; Add to register + 16-bit displacement + mov #pre_byte, er0 + mov #5, r1l + add.b r1l, @(1:16, er0) ; reg8 src, 16-bit reg disp dest +;;; .word 0x0179 +;;; .word 0xc019 +;;; .word 0x0001 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 pre_byte er0 ; er0 contains address minus one + test_h_gr32 0xa5a5a505 er1 ; er1 has the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the add to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #80, r0l + beq .L16 + fail +.L16: + +add_b_reg8_disp32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.b rs8,@-eRd ; Add to register plus 32-bit displacement + mov #post_byte, er0 + mov #5, r1l + add.b r1l, @(-1:32, er0) ; reg8 src, 32-bit reg disp dest +;;; .word 0x0179 +;;; .word 0xd819 +;;; .word 0xffff +;;; .word 0xffff + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 post_byte er0 ; er0 contains address plus one + test_h_gr32 0xa5a5a505 er1 ; er1 has the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the add to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #85, r0l + beq .L17 + fail +.L17: + +add_b_reg8_abs8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.b reg8,@aa:8 + ;; NOTE: for abs8, we will use the SBR register as a base, + ;; since otherwise we would have to make sure that the destination + ;; was in the zero page. + ;; + mov #byte_dest-100, er0 + ldc er0, sbr + mov #5, r1l + add.b r1l, @100:8 ; 8-bit reg src, 8-bit absolute dest +;;; .word 0x7f64 +;;; .word 0x0890 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 byte_dest-100, er0 ; reg 0 has base address + test_h_gr32 0xa5a5a505 er1 ; reg 1 has test load + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the add to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #90, r0l + beq .L18 + fail +.L18: + +add_b_reg8_abs16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.b reg8,@aa:16 + mov #5, r0l + add.b r0l, @byte_dest:16 ; 8-bit reg src, 16-bit absolute dest +;;; .word 0x6a18 +;;; .word byte_dest +;;; .word 0x0880 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 0xa5a5a505 er0 ; reg 0 has test load + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the add to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #95, r0l + beq .L19 + fail +.L19: + +add_b_reg8_abs32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.b reg8,@aa:32 + mov #5, r0l + add.b r0l, @byte_dest:32 ; 8-bit reg src, 32-bit absolute dest +;;; .word 0x6a38 +;;; .long byte_dest +;;; .word 0x0880 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 0xa5a5a505 er0 ; reg 0 has test load + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the add to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #100, r0l + beq .L20 + fail +.L20: + +.endif + + pass + + exit 0 diff --git a/sim/testsuite/sim/h8300/addl.s b/sim/testsuite/sim/h8300/addl.s new file mode 100644 index 0000000..586fcf6 --- /dev/null +++ b/sim/testsuite/sim/h8300/addl.s @@ -0,0 +1,1865 @@ +# Hitachi H8 testcase 'add.l' +# mach(): h8300h h8300s h8sx +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + # Instructions tested: + # add.l xx:3, erd + # add.l xx:16, erd + # add.l xx:32, erd + # add.l xx:16, @erd + # add.l xx:16, @erd+ + # add.l xx:16, @erd- + # add.l xx:16, @+erd + # add.l xx:16, @-erd + # add.l xx:16, @(dd:2, erd) + # add.l xx:16, @(dd:16, erd) + # add.l xx:16, @(dd:32, erd) + # add.l xx:16, @aa:16 + # add.l xx:16, @aa:32 + # add.l xx:32, @erd+ + # add.l xx:32, @erd- + # add.l xx:32, @+erd + # add.l xx:32, @-erd + # add.l xx:32, @(dd:2, erd) + # add.l xx:32, @(dd:16, erd) + # add.l xx:32, @(dd:32, erd) + # add.l xx:32, @aa:16 + # add.l xx:32, @aa:32 + # add.l ers, erd + # add.l ers, @erd + # add.l ers, @erd+ + # add.l ers, @erd- + # add.l ers, @+erd + # add.l ers, @-erd + # add.l ers, @(dd:2, erd) + # add.l ers, @(dd:16, erd) + # add.l ers, @(dd:32, erd) + # add.l ers, @aa:16 + # add.l ers, @aa:32 + # add.l ers, erd + # add.l @ers, erd + # add.l @ers+, erd + # add.l @ers-, erd + # add.l @+ers, erd + # add.l @-ers, erd + # add.l @(dd:2, ers), erd + # add.l @(dd:16, ers), erd + # add.l @(dd:32, ers), erd + # add.l @aa:16, erd + # add.l @aa:32, erd + # add.l @ers, @erd + # add.l @ers+, @erd+ + # add.l @ers-, @erd- + # add.l @+ers, +@erd + # add.l @-ers, @-erd + # add.l @(dd:2, ers), @(dd:2, erd) + # add.l @(dd:16, ers), @(dd:16, erd) + # add.l @(dd:32, ers), @(dd:32, erd) + # add.l @aa:16, @aa:16 + # add.l @aa:32, @aa:32 + + start + + .data + .align 4 +long_src: + .long 0x12345678 +long_dst: + .long 0x87654321 + + .text + + ;; + ;; Add long from immediate source + ;; + +.if (sim_cpu == h8sx) +add_l_imm3_to_reg32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l #xx:3, erd + add.l #0x3:3, er0 ; Immediate 16-bit operand +;;; .word 0x0ab8 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a5a5a8 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +add_l_imm16_to_reg32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l #xx:16, erd + add.l #0x1234, er0 ; Immediate 16-bit operand +;;; .word 0x7a18 +;;; .word 0x1234 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a5b7d9 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif + +add_l_imm32_to_reg32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l #xx:32, erd + add.l #0x12345678, er0 ; Immediate 32-bit operand +;;; .word 0x7a10 +;;; .long 0x12345678 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xb7d9fc1d er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +add_l_imm16_to_indirect: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l #xx:16, @erd + mov.l #long_dst, er1 + add.l #0xdead:16, @er1 ; Register indirect operand +;;; .word 0x010e +;;; .word 0x0110 +;;; .word 0xdead + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x876621ce, @long_dst + beq .Lnext11 + fail +.Lnext11: + mov.l #0x87654321, @long_dst ; Initialize it again for the next use. + +add_l_imm16_to_postinc: ; post-increment from imm16 to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l #xx:16, @erd+ + mov.l #long_dst, er1 + add.l #0xdead:16, @er1+ ; Imm16, register post-incr operands. +;;; .word 0x010e +;;; .word 0x8110 +;;; .word 0xdead + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst+4, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x876621ce, @long_dst + beq .Lnext12 + fail +.Lnext12: + mov.l #0x87654321, @long_dst ; initialize it again for the next use. + +add_l_imm16_to_postdec: ; post-decrement from imm16 to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l #xx:16, @erd- + mov.l #long_dst, er1 + add.l #0xdead:16, @er1- ; Imm16, register post-decr operands. +;;; .word 0x010e +;;; .word 0xa110 +;;; .word 0xdead + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst-4, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x876621ce, @long_dst + beq .Lnext13 + fail +.Lnext13: + mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. + +add_l_imm16_to_preinc: ; pre-increment from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l #xx:16, @+erd + mov.l #long_dst-4, er1 + add.l #0xdead:16, @+er1 ; Imm16, register pre-incr operands +;;; .word 0x010e +;;; .word 0x9110 +;;; .word 0xdead + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x876621ce, @long_dst + beq .Lnext14 + fail +.Lnext14: + mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. + +add_l_imm16_to_predec: ; pre-decrement from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l #xx:16, @-erd + mov.l #long_dst+4, er1 + add.l #0xdead:16, @-er1 ; Imm16, register pre-decr operands +;;; .word 0x010e +;;; .word 0xb110 +;;; .word 0xdead + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x876621ce, @long_dst + beq .Lnext15 + fail +.Lnext15: + mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. + +add_l_imm16_to_disp2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l #xx:16, @(dd:2, erd) + mov.l #long_dst-12, er1 + add.l #0xdead:16, @(12:2, er1) ; Imm16, reg plus 2-bit disp. operand +;;; .word 0x010e +;;; .word 0x3110 +;;; .word 0xdead + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst-12, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x876621ce, @long_dst + beq .Lnext16 + fail +.Lnext16: + mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. + +add_l_imm16_to_disp16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l #xx:16, @(dd:16, erd) + mov.l #long_dst-4, er1 + add.l #0xdead:16, @(4:16, er1) ; Register plus 16-bit disp. operand +;;; .word 0x010e +;;; .word 0xc110 +;;; .word 0xdead +;;; .word 0x0004 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst-4, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x876621ce, @long_dst + beq .Lnext17 + fail +.Lnext17: + mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. + +add_l_imm16_to_disp32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l #xx:16, @(dd:32, erd) + mov.l #long_dst-8, er1 + add.l #0xdead:16, @(8:32, er1) ; Register plus 32-bit disp. operand +;;; .word 0x010e +;;; .word 0xc910 +;;; .word 0xdead +;;; .long 8 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst-8, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x876621ce, @long_dst + beq .Lnext18 + fail +.Lnext18: + mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. + +add_l_imm16_to_abs16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l #xx:16, @aa:16 + add.l #0xdead:16, @long_dst:16 ; 16-bit address-direct operand +;;; .word 0x010e +;;; .word 0x4010 +;;; .word 0xdead +;;; .word @long_dst + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed + test_gr_a5a5 1 ; (first, because on h8/300 we must use one + test_gr_a5a5 2 ; to examine the destination memory). + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x876621ce, @long_dst + beq .Lnext19 + fail +.Lnext19: + mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. + +add_l_imm16_to_abs32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l #xx:16, @aa:32 + add.l #0xdead:16, @long_dst:32 ; 32-bit address-direct operand +;;; .word 0x010e +;;; .word 0x4810 +;;; .word 0xdead +;;; .long @long_dst + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed + test_gr_a5a5 1 ; (first, because on h8/300 we must use one + test_gr_a5a5 2 ; to examine the destination memory). + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x876621ce, @long_dst + beq .Lnext20 + fail +.Lnext20: + mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. + +add_l_imm32_to_indirect: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l #xx:32, @erd + mov.l #long_dst, er1 + add.l #0xcafedead:32, @er1 ; Register indirect operand +;;; .word 0x010e +;;; .word 0x0118 +;;; .long 0xcafedead + + ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 + test_neg_clear + test_zero_clear + test_ovf_set + test_carry_set + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x526421ce, @long_dst + beq .Lnext21 + fail +.Lnext21: + mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. + +add_l_imm32_to_postinc: ; post-increment from imm32 to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l #xx:32, @erd+ + mov.l #long_dst, er1 + add.l #0xcafedead:32, @er1+ ; Imm32, register post-incr operands. +;;; .word 0x010e +;;; .word 0x8118 +;;; .long 0xcafedead + + ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 + test_neg_clear + test_zero_clear + test_ovf_set + test_carry_set + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst+4, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x526421ce, @long_dst + beq .Lnext22 + fail +.Lnext22: + mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. + +add_l_imm32_to_postdec: ; post-decrement from imm32 to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l #xx:32, @erd- + mov.l #long_dst, er1 + add.l #0xcafedead:32, @er1- ; Imm32, register post-decr operands. +;;; .word 0x010e +;;; .word 0xa118 +;;; .long 0xcafedead + + ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 + test_neg_clear + test_zero_clear + test_ovf_set + test_carry_set + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst-4, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x526421ce, @long_dst + beq .Lnext23 + fail +.Lnext23: + mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. + +add_l_imm32_to_preinc: ; pre-increment from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l #xx:32, @+erd + mov.l #long_dst-4, er1 + add.l #0xcafedead:32, @+er1 ; Imm32, register pre-incr operands +;;; .word 0x010e +;;; .word 0x9118 +;;; .long 0xcafedead + + ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 + test_neg_clear + test_zero_clear + test_ovf_set + test_carry_set + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x526421ce, @long_dst + beq .Lnext24 + fail +.Lnext24: + mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. + +add_l_imm32_to_predec: ; pre-decrement from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l #xx:32, @-erd + mov.l #long_dst+4, er1 + add.l #0xcafedead:32, @-er1 ; Imm32, register pre-decr operands +;;; .word 0x010e +;;; .word 0xb118 +;;; .long 0xcafedead + + ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 + test_neg_clear + test_zero_clear + test_ovf_set + test_carry_set + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x526421ce, @long_dst + beq .Lnext25 + fail +.Lnext25: + mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. + +add_l_imm32_to_disp2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l #xx:32, @(dd:2, erd) + mov.l #long_dst-12, er1 + add.l #0xcafedead:32, @(12:2, er1) ; Imm32, reg plus 2-bit disp. operand +;;; .word 0x010e +;;; .word 0x3118 +;;; .long 0xcafedead + + ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 + test_neg_clear + test_zero_clear + test_ovf_set + test_carry_set + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst-12, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x526421ce, @long_dst + beq .Lnext26 + fail +.Lnext26: + mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. + +add_l_imm32_to_disp16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l #xx:32, @(dd:16, erd) + mov.l #long_dst-4, er1 + add.l #0xcafedead:32, @(4:16, er1) ; Register plus 16-bit disp. operand +;;; .word 0x010e +;;; .word 0xc118 +;;; .long 0xcafedead +;;; .word 0x0004 + + ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 + test_neg_clear + test_zero_clear + test_ovf_set + test_carry_set + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst-4, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x526421ce, @long_dst + beq .Lnext27 + fail +.Lnext27: + mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. + +add_l_imm32_to_disp32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l #xx:32, @(dd:32, erd) + mov.l #long_dst-8, er1 + add.l #0xcafedead:32, @(8:32, er1) ; Register plus 32-bit disp. operand +;;; .word 0x010e +;;; .word 0xc918 +;;; .long 0xcafedead +;;; .long 8 + + ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 + test_neg_clear + test_zero_clear + test_ovf_set + test_carry_set + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst-8, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x526421ce, @long_dst + beq .Lnext28 + fail +.Lnext28: + mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. + +add_l_imm32_to_abs16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l #xx:32, @aa:16 + add.l #0xcafedead:32, @long_dst:16 ; 16-bit address-direct operand +;;; .word 0x010e +;;; .word 0x4018 +;;; .long 0xcafedead +;;; .word @long_dst + + ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 + test_neg_clear + test_zero_clear + test_ovf_set + test_carry_set + + test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed + test_gr_a5a5 1 ; (first, because on h8/300 we must use one + test_gr_a5a5 2 ; to examine the destination memory). + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x526421ce, @long_dst + beq .Lnext29 + fail +.Lnext29: + mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. + +add_l_imm32_to_abs32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l #xx:32, @aa:32 + add.l #0xcafedead:32, @long_dst:32 ; 32-bit address-direct operand +;;; .word 0x010e +;;; .word 0x4818 +;;; .long 0xcafedead +;;; .long @long_dst + + ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 + test_neg_clear + test_zero_clear + test_ovf_set + test_carry_set + + test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed + test_gr_a5a5 1 ; (first, because on h8/300 we must use one + test_gr_a5a5 2 ; to examine the destination memory). + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x526421ce, @long_dst + beq .Lnext30 + fail +.Lnext30: + mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. +.endif + + ;; + ;; Add long from register source + ;; + +add_l_reg32_to_reg32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l ers, erd + mov.l #0x12345678, er1 + add.l er1, er0 ; Register 32-bit operand +;;; .word 0x0a90 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xb7d9fc1d er0 ; add result + test_h_gr32 0x12345678 er1 ; add src unchanged + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +add_l_reg32_to_indirect: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l ers, @erd + mov.l #long_dst, er1 + add.l er0, @er1 ; Register indirect operand +;;; .word 0x0109 +;;; .word 0x0110 + + ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 + test_neg_clear + test_zero_clear + test_ovf_set + test_carry_set + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x2d0ae8c6, @long_dst + beq .Lnext44 + fail +.Lnext44: + mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. + +add_l_reg32_to_postinc: ; post-increment from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l ers, @erd+ + mov.l #long_dst, er1 + add.l er0, @er1+ ; Register post-incr operand +;;; .word 0x0109 +;;; .word 0x8110 + + ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 + test_neg_clear + test_zero_clear + test_ovf_set + test_carry_set + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst+4, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x2d0ae8c6, @long_dst + beq .Lnext49 + fail +.Lnext49: + mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. + +add_l_reg32_to_postdec: ; post-decrement from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l ers, @erd- + mov.l #long_dst, er1 + add.l er0, @er1- ; Register post-decr operand +;;; .word 0x0109 +;;; .word 0xa110 + + ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 + test_neg_clear + test_zero_clear + test_ovf_set + test_carry_set + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst-4, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x2d0ae8c6, @long_dst + beq .Lnext50 + fail +.Lnext50: + mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. + +add_l_reg32_to_preinc: ; pre-increment from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l ers, @+erd + mov.l #long_dst-4, er1 + add.l er0, @+er1 ; Register pre-incr operand +;;; .word 0x0109 +;;; .word 0x9110 + + ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 + test_neg_clear + test_zero_clear + test_ovf_set + test_carry_set + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x2d0ae8c6, @long_dst + beq .Lnext51 + fail +.Lnext51: + mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. + +add_l_reg32_to_predec: ; pre-decrement from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l ers, @-erd + mov.l #long_dst+4, er1 + add.l er0, @-er1 ; Register pre-decr operand +;;; .word 0x0109 +;;; .word 0xb110 + + ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 + test_neg_clear + test_zero_clear + test_ovf_set + test_carry_set + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x2d0ae8c6, @long_dst + beq .Lnext48 + fail +.Lnext48: + mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. + +add_l_reg32_to_disp2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l ers, @(dd:2, erd) + mov.l #long_dst-12, er1 + add.l er0, @(12:2, er1) ; Register plus 2-bit disp. operand +;;; .word 0x0109 +;;; .word 0x3110 + + ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 + test_neg_clear + test_zero_clear + test_ovf_set + test_carry_set + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst-12, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x2d0ae8c6, @long_dst + beq .Lnext52 + fail +.Lnext52: + mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. + +add_l_reg32_to_disp16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l ers, @(dd:16, erd) + mov.l #long_dst-4, er1 + add.l er0, @(4:16, er1) ; Register plus 16-bit disp. operand +;;; .word 0x0109 +;;; .word 0xc110 +;;; .word 0x0004 + + ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 + test_neg_clear + test_zero_clear + test_ovf_set + test_carry_set + + test_h_gr32 long_dst-4, er1 + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x2d0ae8c6, @long_dst + beq .Lnext45 + fail +.Lnext45: + mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. + +add_l_reg32_to_disp32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l ers, @(dd:32, erd) + mov.l #long_dst-8, er1 + add.l er0, @(8:32, er1) ; Register plus 32-bit disp. operand +;;; .word 0x0109 +;;; .word 0xc910 +;;; .long 8 + + ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 + test_neg_clear + test_zero_clear + test_ovf_set + test_carry_set + + test_h_gr32 long_dst-8, er1 + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x2d0ae8c6, @long_dst + beq .Lnext46 + fail +.Lnext46: + mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. + +add_l_reg32_to_abs16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l ers, @aa:16 + add.l er0, @long_dst:16 ; 16-bit address-direct operand +;;; .word 0x0109 +;;; .word 0x4110 +;;; .word @long_dst + + ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 + test_neg_clear + test_zero_clear + test_ovf_set + test_carry_set + + test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed + test_gr_a5a5 1 ; (first, because on h8/300 we must use one + test_gr_a5a5 2 ; to examine the destination memory). + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x2d0ae8c6, @long_dst + beq .Lnext41 + fail +.Lnext41: + mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. + +add_l_reg32_to_abs32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l ers, @aa:32 + add.l er0, @long_dst:32 ; 32-bit address-direct operand +;;; .word 0x0109 +;;; .word 0x4910 +;;; .long @long_dst + + ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 + test_neg_clear + test_zero_clear + test_ovf_set + test_carry_set + + test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed + test_gr_a5a5 1 ; (first, because on h8/300 we must use one + test_gr_a5a5 2 ; to examine the destination memory). + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x2d0ae8c6, @long_dst + beq .Lnext42 + fail +.Lnext42: + mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. + + ;; + ;; Add long to register destination. + ;; + +add_l_indirect_to_reg32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l @ers, Rd + mov.l #long_src, er1 + add.l @er1, er0 ; Register indirect operand +;;; .word 0x010a +;;; .word 0x0110 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xb7d9fc1d er0 + + test_h_gr32 long_src, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +add_l_postinc_to_reg32: ; post-increment from mem to register + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l @ers+, erd + mov.l #long_src, er1 + add.l @er1+, er0 ; Register post-incr operand +;;; .word 0x010a +;;; .word 0x8110 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xb7d9fc1d er0 + + test_h_gr32 long_src+4, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +add_l_postdec_to_reg32: ; post-decrement from mem to register + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l @ers-, erd + mov.l #long_src, er1 + add.l @er1-, er0 ; Register post-decr operand +;;; .word 0x010a +;;; .word 0xa110 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xb7d9fc1d er0 + + test_h_gr32 long_src-4, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +add_l_preinc_to_reg32: ; pre-increment from mem to register + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l @+ers, erd + mov.l #long_src-4, er1 + add.l @+er1, er0 ; Register pre-incr operand +;;; .word 0x010a +;;; .word 0x9110 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xb7d9fc1d er0 + + test_h_gr32 long_src, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +add_l_predec_to_reg32: ; pre-decrement from mem to register + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l @-ers, erd + mov.l #long_src+4, er1 + add.l @-er1, er0 ; Register pre-decr operand +;;; .word 0x010a +;;; .word 0xb110 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xb7d9fc1d er0 + + test_h_gr32 long_src, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + +add_l_disp2_to_reg32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l @(dd:2, ers), erd + mov.l #long_src-4, er1 + add.l @(4:2, er1), er0 ; Register plus 2-bit disp. operand +;;; .word 0x010a +;;; .word 0x1110 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xb7d9fc1d er0 ; mov result: a5a5 | 7777 + + test_h_gr32 long_src-4, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +add_l_disp16_to_reg32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l @(dd:16, ers), erd + mov.l #long_src+0x1234, er1 + add.l @(-0x1234:16, er1), er0 ; Register plus 16-bit disp. operand +;;; .word 0x010a +;;; .word 0xc110 +;;; .word -0x1234 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xb7d9fc1d er0 ; mov result: a5a5 | 7777 + + test_h_gr32 long_src+0x1234, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +add_l_disp32_to_reg32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l @(dd:32, ers), erd + mov.l #long_src+65536, er1 + add.l @(-65536:32, er1), er0 ; Register plus 32-bit disp. operand +;;; .word 0x010a +;;; .word 0xc910 +;;; .long -65536 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xb7d9fc1d er0 ; mov result: a5a5 | 7777 + + test_h_gr32 long_src+65536, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +add_l_abs16_to_reg32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l @aa:16, erd + add.l @long_src:16, er0 ; 16-bit address-direct operand +;;; .word 0x010a +;;; .word 0x4010 +;;; .word @long_src + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xb7d9fc1d er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +add_l_abs32_to_reg32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l @aa:32, erd + add.l @long_src:32, er0 ; 32-bit address-direct operand +;;; .word 0x010a +;;; .word 0x4810 +;;; .long @long_src + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xb7d9fc1d er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + + ;; + ;; Add long from memory to memory + ;; + +add_l_indirect_to_indirect: ; reg indirect, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l @ers, @erd + mov.l #long_src, er1 + mov.l #long_dst, er0 + add.l @er1, @er0 +;;; .word 0x0104 +;;; .word 0x691c +;;; .word 0x0010 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 long_dst er0 + test_h_gr32 long_src er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x99999999, @long_dst ; FIXME + beq .Lnext55 + fail +.Lnext55: + ;; Now clear the destination location, and verify that. + mov.l #0x87654321, @long_dst + cmp.l #0x99999999, @long_dst + bne .Lnext56 + fail +.Lnext56: ; OK, pass on. + +add_l_postinc_to_postinc: ; reg post-increment, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l @ers+, @erd+ + mov.l #long_src, er1 + mov.l #long_dst, er0 + add.l @er1+, @er0+ +;;; .word 0x0104 +;;; .word 0x6d1c +;;; .word 0x8010 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 long_dst+4 er0 + test_h_gr32 long_src+4 er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x99999999, @long_dst + beq .Lnext65 + fail +.Lnext65: + ;; Now clear the destination location, and verify that. + mov.l #0x87654321, @long_dst + cmp.l #0x99999999, @long_dst + bne .Lnext66 + fail +.Lnext66: ; OK, pass on. + +add_l_postdec_to_postdec: ; reg post-decrement, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l @ers-, @erd- + mov.l #long_src, er1 + mov.l #long_dst, er0 + add.l @er1-, @er0- +;;; .word 0x0106 +;;; .word 0x6d1c +;;; .word 0xa010 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 long_dst-4 er0 + test_h_gr32 long_src-4 er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x99999999, @long_dst + beq .Lnext75 + fail +.Lnext75: + ;; Now clear the destination location, and verify that. + mov.l #0x87654321, @long_dst + cmp.l #0x99999999, @long_dst + bne .Lnext76 + fail +.Lnext76: ; OK, pass on. + +add_l_preinc_to_preinc: ; reg pre-increment, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l @+ers, @+erd + mov.l #long_src-4, er1 + mov.l #long_dst-4, er0 + add.l @+er1, @+er0 +;;; .word 0x0105 +;;; .word 0x6d1c +;;; .word 0x9010 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 long_dst er0 + test_h_gr32 long_src er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x99999999, @long_dst + beq .Lnext85 + fail +.Lnext85: + ;; Now clear the destination location, and verify that. + mov.l #0x87654321, @long_dst + cmp.l #0x99999999, @long_dst + bne .Lnext86 + fail +.Lnext86: ; OK, pass on. + +add_l_predec_to_predec: ; reg pre-decrement, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l @-ers, @-erd + mov.l #long_src+4, er1 + mov.l #long_dst+4, er0 + add.l @-er1, @-er0 +;;; .word 0x0107 +;;; .word 0x6d1c +;;; .word 0xb010 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 long_dst er0 + test_h_gr32 long_src er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x99999999, @long_dst + beq .Lnext95 + fail +.Lnext95: + ;; Now clear the destination location, and verify that. + mov.l #0x87654321, @long_dst + cmp.l #0x99999999, @long_dst + bne .Lnext96 + fail +.Lnext96: ; OK, pass on. + +add_l_disp2_to_disp2: ; reg 2-bit disp, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l @(dd:2, ers), @(dd:2, erd) + mov.l #long_src-4, er1 + mov.l #long_dst-8, er0 + add.l @(4:2, er1), @(8:2, er0) +;;; .word 0x0105 +;;; .word 0x691c +;;; .word 0x2010 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 long_dst-8 er0 + test_h_gr32 long_src-4 er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x99999999, @long_dst + beq .Lnext105 + fail +.Lnext105: + ;; Now clear the destination location, and verify that. + mov.l #0x87654321, @long_dst + cmp.l #0x99999999, @long_dst + bne .Lnext106 + fail +.Lnext106: ; OK, pass on. + +add_l_disp16_to_disp16: ; reg 16-bit disp, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l @(dd:16, ers), @(dd:16, erd) + mov.l #long_src-1, er1 + mov.l #long_dst-2, er0 + add.l @(1:16, er1), @(2:16, er0) +;;; .word 0x0104 +;;; .word 0x6f1c +;;; .word 0x0001 +;;; .word 0xc010 +;;; .word 0x0002 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 long_dst-2 er0 + test_h_gr32 long_src-1 er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x99999999, @long_dst + beq .Lnext115 + fail +.Lnext115: + ;; Now clear the destination location, and verify that. + mov.l #0x87654321, @long_dst + cmp.l #0x99999999, @long_dst + bne .Lnext116 + fail +.Lnext116: ; OK, pass on. + +add_l_disp32_to_disp32: ; reg 32-bit disp, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l @(dd:32, ers), @(dd:32, erd) + mov.l #long_src-1, er1 + mov.l #long_dst-2, er0 + add.l @(1:32, er1), @(2:32, er0) +;;; .word 0x7894 +;;; .word 0x6b2c +;;; .word 0xc9c8 +;;; .long 1 +;;; .word 0xc810 +;;; .long 2 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 long_dst-2 er0 + test_h_gr32 long_src-1 er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x99999999, @long_dst + beq .Lnext125 + fail +.Lnext125: + ;; Now clear the destination location, and verify that. + mov.l #0x87654321, @long_dst + cmp.l #0x99999999, @long_dst + bne .Lnext126 + fail +.Lnext126: ; OK, pass on. + +add_l_abs16_to_abs16: ; 16-bit absolute addr, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l @aa:16, @aa:16 + add.l @long_src:16, @long_dst:16 +;;; .word 0x0104 +;;; .word 0x6b0c +;;; .word @long_src +;;; .word 0x4010 +;;; .word @long_dst + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + + test_gr_a5a5 0 ; Make sure *NO* general registers are changed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x99999999, @long_dst + beq .Lnext135 + fail +.Lnext135: + ;; Now clear the destination location, and verify that. + mov.l #0x87654321, @long_dst + cmp.l #0x99999999, @long_dst + bne .Lnext136 + fail +.Lnext136: ; OK, pass on. + +add_l_abs32_to_abs32: ; 32-bit absolute addr, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l @aa:32, @aa:32 + add.l @long_src:32, @long_dst:32 +;;; .word 0x0104 +;;; .word 0x6b2c +;;; .long @long_src +;;; .word 0x4810 +;;; .long @long_dst + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure *NO* general registers are changed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x99999999, @long_dst + beq .Lnext145 + fail +.Lnext145: + ;; Now clear the destination location, and verify that. + mov.l #0x87654321, @long_dst + cmp.l #0x99999999, @long_dst + bne .Lnext146 + fail +.Lnext146: ; OK, pass on. + +.endif + + pass + + exit 0 diff --git a/sim/testsuite/sim/h8300/adds.s b/sim/testsuite/sim/h8300/adds.s new file mode 100644 index 0000000..9789e87 --- /dev/null +++ b/sim/testsuite/sim/h8300/adds.s @@ -0,0 +1,74 @@ +# Hitachi H8 testcase 'adds' +# mach(): h8300h h8300s h8sx +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + # Instructions tested: + # adds #1, erd ; 0 b 0 xerd + # adds #2, erd ; 0 b 8 xerd + # adds #4, erd ; 0 b 9 xerd + # + + start +.if (sim_cpu) ; 32 bit only +adds_1: + set_grs_a5a5 + set_ccr_zero + + adds #1, er0 + + test_cc_clear ; adds should not affect any condition codes + test_h_gr32 0xa5a5a5a6 er0 ; result of adds #1 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +adds_2: + set_grs_a5a5 + set_ccr_zero + + adds #2, er0 + + test_cc_clear ; adds should not affect any condition codes + test_h_gr32 0xa5a5a5a7 er0 ; result of adds #2 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +adds_4: + set_grs_a5a5 + set_ccr_zero + + adds #4, er0 + + test_cc_clear ; adds should not affect any condition codes + test_h_gr32 0xa5a5a5a9 er0 ; result of adds #4 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + pass +.endif + exit 0 diff --git a/sim/testsuite/sim/h8300/addw.s b/sim/testsuite/sim/h8300/addw.s new file mode 100644 index 0000000..c38bf69 --- /dev/null +++ b/sim/testsuite/sim/h8300/addw.s @@ -0,0 +1,87 @@ +# Hitachi H8 testcase 'add.w' +# mach(): all +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + # Instructions tested: + # add.w xx:3, rd ; 0 a 0xxx rd (sx only) + # add.w xx:16, rd ; 7 9 1 rd imm16 + # add.w rs, rd ; 0 9 rs rd + # + + start + +.if (sim_cpu == h8sx) ; 3-bit immediate mode only for h8sx +add_w_imm3: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; add.w #xx:3,Rd ; Immediate 3-bit operand + add.w #7, r0 ; FIXME will not assemble yet +; .word 0x0a70 ; Fake it until assembler will take it. + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0xa5ac r0 ; add result: a5a5 + 7 + test_h_gr32 0xa5a5a5ac er0 ; add result: a5a5 + 7 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif + +.if (sim_cpu) ; non-zero means h8300h, s, or sx +add_w_imm16: + ;; add.w immediate not available in h8300 mode. + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; add.w #xx:16,Rd + add.w #0x111, r0 ; Immediate 16-bit operand + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0xa6b6 r0 ; add result: a5a5 + 111 + test_h_gr32 0xa5a5a6b6 er0 ; add result: a5a5 + 111 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif + +add_w_reg: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; add.w Rs,Rd + mov.w #0x111, r1 + add.w r1, r0 ; Register operand + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0xa6b6 r0 ; add result: a5a5 + 111 + test_h_gr16 0x0111 r1 +.if (sim_cpu) ; non-zero means h8300h, s, or sx + test_h_gr32 0xa5a5a6b6 er0 ; add result: a5a5 + 111 + test_h_gr32 0xa5a50111 er1 +.endif + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + pass + + exit 0 diff --git a/sim/testsuite/sim/h8300/addx.s b/sim/testsuite/sim/h8300/addx.s new file mode 100644 index 0000000..ef4e9d3 --- /dev/null +++ b/sim/testsuite/sim/h8300/addx.s @@ -0,0 +1,992 @@ +# Hitachi H8 testcase 'addx' +# mach(): all +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + # Instructions tested: + # addx.b #xx:8, rd8 ; 9 rd8 xxxxxxxx + # addx.b #xx:8, @erd ; 7 d erd ???? 9 ???? xxxxxxxx + # addx.b #xx:8, @erd- ; 0 1 7 6 6 c erd 1??? 9 ???? xxxxxxxx + # addx.b rs8, rd8 ; 0 e rs8 rd8 + # addx.b rs8, @erd ; 7 d erd ???? 0 e rs8 ???? + # addx.b rs8, @erd- ; 0 1 7 6 6 c erd 1??? 0 e rs8 ???? + # addx.b @ers, rd8 ; 7 c ers ???? 0 e ???? rd8 + # addx.b @ers-, rd8 ; 0 1 7 6 6 c ers 00?? 0 e ???? rd8 + # addx.b @ers, @erd ; 0 1 7 4 6 8 ers d 0 erd 1 ???? + # addx.b @ers-, @erd- ; 0 1 7 6 6 c ers d a erd 1 ???? + # + # word ops + # long ops + +.data +byte_src: .byte 0x5 +byte_dest: .byte 0 + + .align 2 +word_src: .word 0x505 +word_dest: .word 0 + + .align 4 +long_src: .long 0x50505 +long_dest: .long 0 + + + start + +addx_b_imm8_0: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; addx.b #xx:8,Rd ; Addx with carry initially zero. + addx.b #5, r0l ; Immediate 8-bit operand + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr16 0xa5aa r0 ; add result: a5 + 5 +.if (sim_cpu) ; non-zero means h8300h, s, or sx + test_h_gr32 0xa5a5a5aa er0 ; add result: a5 + 5 +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +addx_b_imm8_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; addx.b #xx:8,Rd ; Addx with carry initially one. + set_carry_flag + addx.b #5, r0l ; Immediate 8-bit operand + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr16 0xa5ab r0 ; add result: a5 + 5 + 1 +.if (sim_cpu) ; non-zero means h8300h, s, or sx + test_h_gr32 0xa5a5a5ab er0 ; add result: a5 + 5 + 1 +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +addx_b_imm8_rdind: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; addx.b #xx:8,@eRd ; Addx to register indirect + mov #byte_dest, er0 + addx.b #5, @er0 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 byte_dest er0 ; er0 still contains address + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the add to memory. + cmp.b #5, @byte_dest + beq .Lb1 + fail +.Lb1: + +addx_b_imm8_rdpostdec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; addx.b #xx:8,@eRd- ; Addx to register post-decrement + mov #byte_dest, er0 + addx.b #5, @er0- + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 byte_dest-1 er0 ; er0 contains address minus one + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the add to memory. + cmp.b #10, @byte_dest + beq .Lb2 + fail +.Lb2: +.endif + +addx_b_reg8_0: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; addx.b Rs,Rd ; addx with carry initially zero + mov.b #5, r0h + addx.b r0h, r0l ; Register operand + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr16 0x05aa r0 ; add result: a5 + 5 +.if (sim_cpu) ; non-zero means h8300h, s, or sx + test_h_gr32 0xa5a505aa er0 ; add result: a5 + 5 +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +addx_b_reg8_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; addx.b Rs,Rd ; addx with carry initially one + mov.b #5, r0h + set_carry_flag + addx.b r0h, r0l ; Register operand + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr16 0x05ab r0 ; add result: a5 + 5 + 1 +.if (sim_cpu) ; non-zero means h8300h, s, or sx + test_h_gr32 0xa5a505ab er0 ; add result: a5 + 5 + 1 +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +addx_b_reg8_rdind: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; addx.b rs8,@eRd ; Addx to register indirect + mov #byte_dest, er0 + mov.b #5, r1l + addx.b r1l, @er0 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 byte_dest er0 ; er0 still contains address + test_h_gr32 0xa5a5a505 er1 ; er1 has the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the add to memory. + cmp.b #15, @byte_dest + beq .Lb3 + fail +.Lb3: + +addx_b_reg8_rdpostdec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; addx.b rs8,@eRd- ; Addx to register post-decrement + mov #byte_dest, er0 + mov.b #5, r1l + addx.b r1l, @er0- + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 byte_dest-1 er0 ; er0 contains address minus one + test_h_gr32 0xa5a5a505 er1 ; er1 contains the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the add to memory. + cmp.b #20, @byte_dest + beq .Lb4 + fail +.Lb4: + +addx_b_rsind_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; addx.b @eRs,rd8 ; Addx from reg indirect to reg + mov #byte_src, er0 + addx.b @er0, r1l + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 byte_src er0 ; er0 still contains address + test_h_gr32 0xa5a5a5aa er1 ; er1 contains the sum + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +addx_b_rspostdec_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; addx.b @eRs-,rd8 ; Addx to register post-decrement + mov #byte_src, er0 + addx.b @er0-, r1l + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 byte_src-1 er0 ; er0 contains address minus one + test_h_gr32 0xa5a5a5aa er1 ; er1 contains the sum + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +addx_b_rsind_rsind: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; addx.b @eRs,rd8 ; Addx from reg indirect to reg + mov #byte_src, er0 + mov #byte_dest, er1 + addx.b @er0, @er1 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 byte_src er0 ; er0 still contains src address + test_h_gr32 byte_dest er1 ; er1 still contains dst address + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ;; Now check the result of the add to memory. + cmp.b #25, @byte_dest + beq .Lb5 + fail +.Lb5: + +addx_b_rspostdec_rspostdec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; addx.b @eRs-,rd8 ; Addx to register post-decrement + mov #byte_src, er0 + mov #byte_dest, er1 + addx.b @er0-, @er1- + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 byte_src-1 er0 ; er0 contains src address minus one + test_h_gr32 byte_dest-1 er1 ; er1 contains dst address minus one + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ;; Now check the result of the add to memory. + cmp.b #30, @byte_dest + beq .Lb6 + fail +.Lb6: + +addx_w_imm16_0: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; addx.w #xx:16,Rd ; Addx with carry initially zero. + addx.w #0x505, r0 ; Immediate 16-bit operand + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr16 0xaaaa r0 ; add result: 0xa5a5 + 0x505 + test_h_gr32 0xa5a5aaaa er0 ; add result: 0xa5a5 + 0x505 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +addx_w_imm16_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; addx.w #xx:16,Rd ; Addx with carry initially one. + set_carry_flag + addx.w #0x505, r0 ; Immediate 16-bit operand + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr16 0xaaab r0 ; add result: 0xa5a5 + 0x505 + 1 + test_h_gr32 0xa5a5aaab er0 ; add result: 0xa5a5 + 0x505 + 1 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +addx_w_imm16_rdind: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; addx.w #xx:16,@eRd ; Addx to register indirect + mov #word_dest, er0 + addx.w #0x505, @er0 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 word_dest er0 ; er0 still contains address + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the add to memory. + cmp.w #0x505, @word_dest + beq .Lw1 + fail +.Lw1: + +addx_w_imm16_rdpostdec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; addx.w #xx:16,@eRd- ; Addx to register post-decrement + mov #word_dest, er0 + addx.w #0x505, @er0- + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 word_dest-2 er0 ; er0 contains address minus one + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the add to memory. + cmp.w #0xa0a, @word_dest + beq .Lw2 + fail +.Lw2: + +addx_w_reg16_0: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; addx.w Rs,Rd ; addx with carry initially zero + mov.w #0x505, e0 + addx.w e0, r0 ; Register operand + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 0x0505aaaa er0 ; add result: + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +addx_w_reg16_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; addx.w Rs,Rd ; addx with carry initially one + mov.w #0x505, e0 + set_carry_flag + addx.w e0, r0 ; Register operand + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 0x0505aaab er0 ; add result: + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +addx_w_reg16_rdind: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; addx.w rs8,@eRd ; Addx to register indirect + mov #word_dest, er0 + mov.w #0x505, r1 + addx.w r1, @er0 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 word_dest er0 ; er0 still contains address + test_h_gr32 0xa5a50505 er1 ; er1 has the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the add to memory. + cmp.w #0xf0f, @word_dest + beq .Lw3 + fail +.Lw3: + +addx_w_reg16_rdpostdec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; addx.w rs8,@eRd- ; Addx to register post-decrement + mov #word_dest, er0 + mov.w #0x505, r1 + addx.w r1, @er0- + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 word_dest-2 er0 ; er0 contains address minus one + test_h_gr32 0xa5a50505 er1 ; er1 contains the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the add to memory. + cmp.w #0x1414, @word_dest + beq .Lw4 + fail +.Lw4: + +addx_w_rsind_reg16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; addx.w @eRs,rd8 ; Addx from reg indirect to reg + mov #word_src, er0 + addx.w @er0, r1 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 word_src er0 ; er0 still contains address + test_h_gr32 0xa5a5aaaa er1 ; er1 contains the sum + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +addx_w_rspostdec_reg16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; addx.w @eRs-,rd8 ; Addx to register post-decrement + mov #word_src, er0 + addx.w @er0-, r1 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 word_src-2 er0 ; er0 contains address minus one + test_h_gr32 0xa5a5aaaa er1 ; er1 contains the sum + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +addx_w_rsind_rdind: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; addx.w @eRs,rd8 ; Addx from reg indirect to reg + mov #word_src, er0 + mov #word_dest, er1 + addx.w @er0, @er1 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 word_src er0 ; er0 still contains src address + test_h_gr32 word_dest er1 ; er1 still contains dst address + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ;; Now check the result of the add to memory. + cmp.w #0x1919, @word_dest + beq .Lw5 + fail +.Lw5: + +addx_w_rspostdec_rdpostdec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; addx.w @eRs-,rd8 ; Addx to register post-decrement + mov #word_src, er0 + mov #word_dest, er1 + addx.w @er0-, @er1- + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 word_src-2 er0 ; er0 contains src address minus one + test_h_gr32 word_dest-2 er1 ; er1 contains dst address minus one + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ;; Now check the result of the add to memory. + cmp.w #0x1e1e, @word_dest + beq .Lw6 + fail +.Lw6: + +addx_l_imm32_0: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; addx.l #xx:32,Rd ; Addx with carry initially zero. + addx.l #0x50505, er0 ; Immediate 32-bit operand + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 0xa5aaaaaa er0 ; add result: + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +addx_l_imm32_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; addx.l #xx:32,Rd ; Addx with carry initially one. + set_carry_flag + addx.l #0x50505, er0 ; Immediate 32-bit operand + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 0xa5aaaaab er0 ; add result: + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +addx_l_imm32_rdind: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; addx.l #xx:32,@eRd ; Addx to register indirect + mov #long_dest, er0 + addx.l #0x50505, @er0 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 long_dest er0 ; er0 still contains address + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the add to memory. + cmp.l #0x50505, @long_dest + beq .Ll1 + fail +.Ll1: + +addx_l_imm32_rdpostdec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; addx.l #xx:32,@eRd- ; Addx to register post-decrement + mov #long_dest, er0 + addx.l #0x50505, @er0- + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 long_dest-4 er0 ; er0 contains address minus one + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the add to memory. + cmp.l #0xa0a0a, @long_dest + beq .Ll2 + fail +.Ll2: + +addx_l_reg32_0: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; addx.l Rs,Rd ; addx with carry initially zero + mov.l #0x50505, er0 + addx.l er0, er1 ; Register operand + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 0x50505 er0 ; add load + test_h_gr32 0xa5aaaaaa er1 ; add result: + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +addx_l_reg32_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; addx.l Rs,Rd ; addx with carry initially one + mov.l #0x50505, er0 + set_carry_flag + addx.l er0, er1 ; Register operand + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 0x50505 er0 ; add result: + test_h_gr32 0xa5aaaaab er1 ; add result: + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +addx_l_reg32_rdind: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; addx.l rs8,@eRd ; Addx to register indirect + mov #long_dest, er0 + mov.l #0x50505, er1 + addx.l er1, @er0 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 long_dest er0 ; er0 still contains address + test_h_gr32 0x50505 er1 ; er1 has the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the add to memory. + cmp.l #0xf0f0f, @long_dest + beq .Ll3 + fail +.Ll3: + +addx_l_reg32_rdpostdec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; addx.l rs8,@eRd- ; Addx to register post-decrement + mov #long_dest, er0 + mov.l #0x50505, er1 + addx.l er1, @er0- + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 long_dest-4 er0 ; er0 contains address minus one + test_h_gr32 0x50505 er1 ; er1 contains the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the add to memory. + cmp.l #0x141414, @long_dest + beq .Ll4 + fail +.Ll4: + +addx_l_rsind_reg32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; addx.l @eRs,rd8 ; Addx from reg indirect to reg + mov #long_src, er0 + addx.l @er0, er1 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 long_src er0 ; er0 still contains address + test_h_gr32 0xa5aaaaaa er1 ; er1 contains the sum + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +addx_l_rspostdec_reg32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; addx.l @eRs-,rd8 ; Addx to register post-decrement + mov #long_src, er0 + addx.l @er0-, er1 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 long_src-4 er0 ; er0 contains address minus one + test_h_gr32 0xa5aaaaaa er1 ; er1 contains the sum + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +addx_l_rsind_rdind: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; addx.l @eRs,rd8 ; Addx from reg indirect to reg + mov #long_src, er0 + mov #long_dest, er1 + addx.l @er0, @er1 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 long_src er0 ; er0 still contains src address + test_h_gr32 long_dest er1 ; er1 still contains dst address + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ;; Now check the result of the add to memory. + cmp.l #0x191919, @long_dest + beq .Ll5 + fail +.Ll5: + +addx_l_rspostdec_rdpostdec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; addx.l @eRs-,rd8 ; Addx to register post-decrement + mov #long_src, er0 + mov #long_dest, er1 + addx.l @er0-, @er1- + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 long_src-4 er0 ; er0 contains src address minus one + test_h_gr32 long_dest-4 er1 ; er1 contains dst address minus one + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ;; Now check the result of the add to memory. + cmp.l #0x1e1e1e, @long_dest + beq .Ll6 + fail +.Ll6: +.endif + pass + + exit 0 diff --git a/sim/testsuite/sim/h8300/allinsn.exp b/sim/testsuite/sim/h8300/allinsn.exp new file mode 100644 index 0000000..82fedeb --- /dev/null +++ b/sim/testsuite/sim/h8300/allinsn.exp @@ -0,0 +1,65 @@ +# Hitachi H8/300 (h, s, sx) simulator testsuite + +set all "h8300 h8300h h8300s h8sx" + +if {[istarget h8300*-*-*] || [istarget h8sx*-*-*]} then { + run_sim_test addb.s $all + run_sim_test addw.s $all + run_sim_test addl.s $all + run_sim_test adds.s $all + run_sim_test addx.s $all + run_sim_test andb.s $all + run_sim_test andw.s $all + run_sim_test andl.s $all + run_sim_test band.s $all + run_sim_test bfld.s h8sx + run_sim_test biand.s $all + run_sim_test bra.s $all + run_sim_test bset.s $all + run_sim_test cmpb.s $all + run_sim_test cmpw.s $all + run_sim_test cmpl.s $all + run_sim_test daa.s $all + run_sim_test das.s $all + run_sim_test dec.s $all + run_sim_test div.s $all + run_sim_test extw.s $all + run_sim_test extl.s $all + run_sim_test inc.s $all + run_sim_test jmp.s $all + run_sim_test ldc.s $all + run_sim_test ldm.s $all + run_sim_test mac.s $all + run_sim_test movb.s $all + run_sim_test movw.s $all + run_sim_test movl.s $all + run_sim_test mova.s h8sx + run_sim_test movmd.s h8sx + run_sim_test movsd.s h8sx + run_sim_test mul.s $all + run_sim_test neg.s $all + run_sim_test nop.s $all + run_sim_test not.s $all + run_sim_test orb.s $all + run_sim_test orw.s $all + run_sim_test orl.s $all + run_sim_test rotl.s $all + run_sim_test rotr.s $all + run_sim_test rotxl.s $all + run_sim_test rotxr.s $all + run_sim_test shal.s $all + run_sim_test shar.s $all + run_sim_test shll.s $all + run_sim_test shlr.s $all + run_sim_test stack.s $all + run_sim_test stc.s $all + run_sim_test subb.s $all + run_sim_test subw.s $all + run_sim_test subl.s $all + run_sim_test subs.s $all + run_sim_test subx.s $all + run_sim_test tas.s $all + run_sim_test xorb.s $all + run_sim_test xorw.s $all + run_sim_test xorl.s $all +} diff --git a/sim/testsuite/sim/h8300/andb.s b/sim/testsuite/sim/h8300/andb.s new file mode 100644 index 0000000..8f11805 --- /dev/null +++ b/sim/testsuite/sim/h8300/andb.s @@ -0,0 +1,527 @@ +# Hitachi H8 testcase 'and.b' +# mach(): all +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + # Instructions tested: + # and.b #xx:8, rd ; e rd xxxxxxxx + # and.b #xx:8, @erd ; 7 d rd ???? e ???? xxxxxxxx + # and.b #xx:8, @erd+ ; 0 1 7 4 6 c rd 1??? e ???? xxxxxxxx + # and.b #xx:8, @erd- ; 0 1 7 6 6 c rd 1??? e ???? xxxxxxxx + # and.b #xx:8, @+erd ; 0 1 7 5 6 c rd 1??? e ???? xxxxxxxx + # and.b #xx:8, @-erd ; 0 1 7 7 6 c rd 1??? e ???? xxxxxxxx + # and.b rs, rd ; 1 6 rs rd + # and.b reg8, @erd ; 7 d rd ???? 1 6 rs ???? + # and.b reg8, @erd+ ; 0 1 7 9 8 rd 6 rs + # and.b reg8, @erd- ; 0 1 7 9 a rd 6 rs + # and.b reg8, @+erd ; 0 1 7 9 9 rd 6 rs + # and.b reg8, @-erd ; 0 1 7 9 b rd 6 rs + # + # andc #xx:8, ccr ; 0 6 xxxxxxxx + # andc #xx:8, exr ; 0 1 4 1 0 6 xxxxxxxx + + # Coming soon: + # ... + +.data +pre_byte: .byte 0 +byte_dest: .byte 0xa5 +post_byte: .byte 0 + + start + +and_b_imm8_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; and.b #xx:8,Rd + and.b #0xaa, r0l ; Immediate 8-bit operand + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0xa5a0 r0 ; and result: a5 & aa +.if (sim_cpu) ; non-zero means h8300h, s, or sx + test_h_gr32 0xa5a5a5a0 er0 ; and result: a5 & aa +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +and_b_imm8_rdind: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; and.b #xx:8,@eRd + mov #byte_dest, er0 + and.b #0xaa:8, @er0 ; Immediate 8-bit src, reg indirect dst +;;; .word 0x7d00 +;;; .word 0xe0aa + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 byte_dest, er0 ; er0 still contains address + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the and to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0xa0, r0l + beq .L1 + fail +.L1: + +and_b_imm8_rdpostinc: + mov #byte_dest, er0 + mov.b #0xa5, r1l + mov.b r1l, @er0 + + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; and.b #xx:8,@eRd+ + mov #byte_dest, er0 + and.b #0x55:8, @er0+ ; Immediate 8-bit src, reg post-incr dest +;;; .word 0x0174 +;;; .word 0x6c08 +;;; .word 0xe055 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 post_byte, er0 ; er0 contains address plus one + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the and to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0x05, r0l + beq .L2 + fail +.L2: + +and_b_imm8_rdpostdec: + mov #byte_dest, er0 + mov.b #0xa5, r1l + mov.b r1l, @er0 + + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; and.b #xx:8,@eRd- + mov #byte_dest, er0 + and.b #0xaa:8, @er0- ; Immediate 8-bit src, reg post-decr dest +;;; .word 0x0176 +;;; .word 0x6c08 +;;; .word 0xe0aa + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 pre_byte, er0 ; er0 contains address minus one + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the and to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0xa0, r0l + beq .L3 + fail +.L3: + +and_b_imm8_rdpreinc: + mov #byte_dest, er0 + mov.b #0xa5, r1l + mov.b r1l, @er0 + + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; and.b #xx:8,@+eRd + mov #pre_byte, er0 + and.b #0x55:8, @+er0 ; Immediate 8-bit src, reg pre-incr dest +;;; .word 0x0175 +;;; .word 0x6c08 +;;; .word 0xe055 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 byte_dest, er0 ; er0 contains destination address + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the and to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0x05, r0l + beq .L4 + fail +.L4: + +and_b_imm8_rdpredec: + mov #byte_dest, er0 + mov.b #0xa5, r1l + mov.b r1l, @er0 + + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; and.b #xx:8,@-eRd + mov #post_byte, er0 + and.b #0xaa:8, @-er0 ; Immediate 8-bit src, reg pre-decr dest +;;; .word 0x0177 +;;; .word 0x6c08 +;;; .word 0xe0aa + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 byte_dest, er0 ; er0 contains destination address + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the and to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0xa0, r0l + beq .L5 + fail +.L5: + +.endif ; h8sx + +and_b_reg8_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; and.b Rs,Rd + mov.b #0xaa, r0h + and.b r0h, r0l ; Register operand + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0xaaa0 r0 ; and result: a5 & aa +.if (sim_cpu) ; non-zero means h8300h, s, or sx + test_h_gr32 0xa5a5aaa0 er0 ; and result: a5 & aa +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +and_b_reg8_rdind: + mov #byte_dest, er0 + mov.b #0xa5, r1l + mov.b r1l, @er0 + + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; and.b rs8,@eRd ; And to register indirect + mov #byte_dest, er0 + mov #0x55, r1l + and.b r1l, @er0 ; reg8 src, reg indirect dest +;;; .word 0x7d00 +;;; .word 0x1690 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 byte_dest er0 ; er0 still contains address + test_h_gr32 0xa5a5a555 er1 ; er1 has the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the and to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0x05, r0l + beq .L6 + fail +.L6: + +and_b_reg8_rdpostinc: + mov #byte_dest, er0 + mov.b #0xa5, r1l + mov.b r1l, @er0 + + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; and.b rs8,@eRd+ ; And to register post-incr + mov #byte_dest, er0 + mov #0xaa, r1l + and.b r1l, @er0+ ; reg8 src, reg post-incr dest +;;; .word 0x0179 +;;; .word 0x8069 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 post_byte er0 ; er0 contains address plus one + test_h_gr32 0xa5a5a5aa er1 ; er1 has the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the and to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0xa0, r0l + beq .L7 + fail +.L7: + +and_b_reg8_rdpostdec: + mov #byte_dest, er0 + mov.b #0xa5, r1l + mov.b r1l, @er0 + + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; and.b rs8,@eRd- ; And to register post-decr + mov #byte_dest, er0 + mov #0x55, r1l + and.b r1l, @er0- ; reg8 src, reg post-decr dest +;;; .word 0x0179 +;;; .word 0xa069 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 pre_byte er0 ; er0 contains address minus one + test_h_gr32 0xa5a5a555 er1 ; er1 has the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the and to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0x05, r0l + beq .L8 + fail +.L8: + +and_b_reg8_rdpreinc: + mov #byte_dest, er0 + mov.b #0xa5, r1l + mov.b r1l, @er0 + + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; and.b rs8,@+eRd ; And to register post-incr + mov #pre_byte, er0 + mov #0xaa, r1l + and.b r1l, @+er0 ; reg8 src, reg post-incr dest +;;; .word 0x0179 +;;; .word 0x9069 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 byte_dest er0 ; er0 contains destination address + test_h_gr32 0xa5a5a5aa er1 ; er1 has the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the and to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0xa0, r0l + beq .L9 + fail +.L9: + +and_b_reg8_rdpredec: + mov #byte_dest, er0 + mov.b #0xa5, r1l + mov.b r1l, @er0 + + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; and.b rs8,@-eRd ; And to register post-decr + mov #post_byte, er0 + mov #0x55, r1l + and.b r1l, @-er0 ; reg8 src, reg post-decr dest +;;; .word 0x0179 +;;; .word 0xb069 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 byte_dest er0 ; er0 contains destination address + test_h_gr32 0xa5a5a555 er1 ; er1 has the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the and to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0x05, r0l + beq .L10 + fail +.L10: +.endif ; h8sx + +andc_imm8_ccr: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; andc #xx:8,ccr + set_ccr 0xff + + test_neg_set + andc #0xf7, ccr ; Immediate 8-bit operand (neg flag) + test_neg_clear + + test_zero_set + andc #0xfb, ccr ; Immediate 8-bit operand (zero flag) + test_zero_clear + + test_ovf_set + andc #0xfd, ccr ; Immediate 8-bit operand (overflow flag) + test_ovf_clear + + test_carry_set + andc #0xfe, ccr ; Immediate 8-bit operand (carry flag) + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8300s || sim_cpu == h8sx) ; Earlier versions, no exr +andc_imm8_exr: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ldc #0xff, exr + stc exr, r0l + test_h_gr8 0x87, r0l + + ;; andc #xx:8,exr + set_ccr_zero + andc #0x7f, exr + test_cc_clear + stc exr, r0l + test_h_gr8 0x7, r0l + + andc #0x3, exr + stc exr, r0l + test_h_gr8 0x3, r0l + + andc #0x1, exr + stc exr, r0l + test_h_gr8 0x1, r0l + + andc #0x0, exr + stc exr, r0l + test_h_gr8 0x0, r0l + + test_h_gr32 0xa5a5a500 er0 + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif ; not h8300 or h8300h + + pass + + exit 0 diff --git a/sim/testsuite/sim/h8300/andl.s b/sim/testsuite/sim/h8300/andl.s new file mode 100644 index 0000000..ac09edc --- /dev/null +++ b/sim/testsuite/sim/h8300/andl.s @@ -0,0 +1,77 @@ +# Hitachi H8 testcase 'and.l' +# mach(): h8300h h8300s h8sx +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + start + +.if (sim_cpu == h8sx) ; 16-bit immediate is only available on sx. +and_l_imm16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; and.l #xx:16,Rd + and.l #0xaaaa:16, er0 ; Immediate 16-bit operand + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + + test_h_gr32 0x0000a0a0 er0 ; and result: a5a5a5a5 & aaaa + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif + +and_l_imm32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; and.l #xx:32,Rd + and.l #0xaaaaaaaa, er0 ; Immediate 32-bit operand + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + + test_h_gr32 0xa0a0a0a0 er0 ; and result: a5a5a5a5 & aaaaaaaa + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +and_l_reg: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; and.l Rs,Rd + mov.l #0xaaaaaaaa, er1 + and.l er1, er0 ; Register operand + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + + test_h_gr32 0xa0a0a0a0 er0 ; and result: a5a5a5a5 & aaaaaaaa + test_h_gr32 0xaaaaaaaa er1 ; Make sure er1 is unchanged + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + pass + + exit 0 diff --git a/sim/testsuite/sim/h8300/andw.s b/sim/testsuite/sim/h8300/andw.s new file mode 100644 index 0000000..4267179 --- /dev/null +++ b/sim/testsuite/sim/h8300/andw.s @@ -0,0 +1,61 @@ +# Hitachi H8 testcase 'and.w' +# mach(): h8300h h8300s h8sx +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + start + +.if (sim_cpu) ; non-zero means h8300h, s, or sx +and_w_imm16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; and.w #xx:16,Rd + and.w #0xaaaa, r0 ; Immediate 16-bit operand + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0xa0a0 r0 ; and result: a5a5 & aaaa +.if (sim_cpu) ; non-zero means h8300h, s, or sx + test_h_gr32 0xa5a5a0a0 er0 ; and result: a5a5 & aaaa +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif + +and_w_reg: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; and.w Rs,Rd + mov.w #0xaaaa, r1 + and.w r1, r0 ; Register operand + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0xa0a0 r0 ; and result: a5a5 & aaaa + test_h_gr16 0xaaaa r1 ; Make sure r1 is unchanged +.if (sim_cpu) ; non-zero means h8300h, s, or sx + test_h_gr32 0xa5a5a0a0 er0 ; and result: a5a5 & aaaa + test_h_gr32 0xa5a5aaaa er1 ; Make sure er1 is unchanged +.endif + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + pass + + exit 0 diff --git a/sim/testsuite/sim/h8300/band.s b/sim/testsuite/sim/h8300/band.s new file mode 100644 index 0000000..f3455ad --- /dev/null +++ b/sim/testsuite/sim/h8300/band.s @@ -0,0 +1,525 @@ +# Hitachi H8 testcase 'band', 'bor', 'bxor', 'bld', 'bst', 'bstz' +# mach(): all +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + .data +byte_src: .byte 0xa5 +byte_dst: .byte 0 + + start + +band_imm3_reg8: + set_grs_a5a5 + set_ccr_zero + ;; band xx:3, reg8 + band #7, r0l ; this should NOT set the carry flag. + test_cc_clear + band #6, r0l ; this should NOT set the carry flag. + test_cc_clear + + orc #1, ccr ; set the carry flag + band #7, r0l ; this should NOT clear the carry flag + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + band #6, r0l ; this should clear the carry flag + test_cc_clear + + test_grs_a5a5 ; general registers should not be changed. + +band_imm3_ind: + set_grs_a5a5 +.if (sim_cpu == h8300) + mov #byte_src, r1 + set_ccr_zero + ;; band xx:3, ind + band #7, @r1 ; this should NOT set the carry flag. + test_cc_clear + band #6, @r1 ; this should NOT set the carry flag. + test_cc_clear + + orc #1, ccr ; set the carry flag + band #7, @r1 ; this should NOT clear the carry flag + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + band #6, @r1 ; this should clear the carry flag + test_cc_clear +;;; test_h_gr16 byte_src r1 ;FIXME +.else + mov #byte_src, er1 + set_ccr_zero + ;; band xx:3, ind + band #7, @er1 ; this should NOT set the carry flag. + test_cc_clear + band #6, @er1 ; this should NOT set the carry flag. + test_cc_clear + + orc #1, ccr ; set the carry flag + band #7, @er1 ; this should NOT clear the carry flag + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + band #6, @er1 ; this should clear the carry flag + test_cc_clear + test_h_gr32 byte_src er1 +.endif ; h8300 + test_gr_a5a5 0 ; general registers should not be changed. + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +band_imm3_abs8: + set_grs_a5a5 + mov.b r1l, @0x20 + set_ccr_zero + ;; band xx:3, aa:8 + band #7, @0x20:8 ; this should NOT set the carry flag. + test_cc_clear + band #6, @0x20:8 ; this should NOT set the carry flag. + test_cc_clear + + orc #1, ccr ; set the carry flag + band #7, @0x20:8 ; this should NOT clear the carry flag + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + band #6, @0x20:8 ; this should clear the carry flag + test_cc_clear + + test_grs_a5a5 ; general registers should not be changed. + +.if (sim_cpu) ; non-zero means not h8300 +band_imm3_abs16: + set_grs_a5a5 + set_ccr_zero + ;; band xx:3, aa:16 + band #7, @byte_src:16 ; this should NOT set the carry flag. + test_cc_clear + band #6, @byte_src:16 ; this should NOT set the carry flag. + test_cc_clear + + orc #1, ccr ; set the carry flag + band #7, @byte_src:16 ; this should NOT clear the carry flag + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + band #6, @byte_src:16 ; this should clear the carry flag + test_cc_clear + + test_grs_a5a5 ; general registers should not be changed. + +band_imm3_abs32: + set_grs_a5a5 + set_ccr_zero + ;; band xx:3, aa:32 + band #7, @byte_src:32 ; this should NOT set the carry flag. + test_cc_clear + band #6, @byte_src:32 ; this should NOT set the carry flag. + test_cc_clear + + orc #1, ccr ; set the carry flag + band #7, @byte_src:32 ; this should NOT clear the carry flag + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + band #6, @byte_src:32 ; this should clear the carry flag + test_cc_clear + + test_grs_a5a5 ; general registers should not be changed. +.endif + +bor_imm3_reg8: + set_grs_a5a5 + set_ccr_zero + ;; bor xx:3, reg8 + bor #6, r0l ; this should NOT set the carry flag. + test_cc_clear + + bor #7, r0l ; this should set the carry flag. + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + + orc #1, ccr ; set the carry flag + bor #7, r0l ; this should NOT clear the carry flag + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + bor #6, r0l ; this should NOT clear the carry flag + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + + test_grs_a5a5 ; general registers should not be changed. + +bor_imm3_abs8: + set_grs_a5a5 + mov.b r1l, @0x20 + set_ccr_zero + ;; bor xx:3, aa:8 + bor #6, @0x20:8 ; this should NOT set the carry flag. + test_cc_clear + bor #7, @0x20:8 ; this should set the carry flag. + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + + orc #1, ccr ; set the carry flag + bor #7, @0x20:8 ; this should NOT clear the carry flag + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + bor #6, @0x20:8 ; this should NOT clear the carry flag + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + + test_grs_a5a5 ; general registers should not be changed. + +bxor_imm3_reg8: + set_grs_a5a5 + set_ccr_zero + ;; bxor xx:3, reg8 + bxor #6, r0l ; this should NOT set the carry flag. + test_cc_clear + + bxor #7, r0l ; this should set the carry flag. + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + + orc #1, ccr ; set the carry flag + bxor #6, r0l ; this should NOT clear the carry flag + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + + bxor #7, r0l ; this should clear the carry flag + test_cc_clear + + test_grs_a5a5 ; general registers should not be changed. + +bxor_imm3_abs8: + set_grs_a5a5 + mov.b r1l, @0x20 + set_ccr_zero + ;; bxor xx:3, aa:8 + bxor #6, @0x20:8 ; this should NOT set the carry flag. + test_cc_clear + bxor #7, @0x20:8 ; this should set the carry flag. + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + + orc #1, ccr ; set the carry flag + bxor #6, @0x20:8 ; this should NOT clear the carry flag + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + + bxor #7, @0x20:8 ; this should clear the carry flag + test_cc_clear + + test_grs_a5a5 ; general registers should not be changed. + +bld_imm3_reg8: + set_grs_a5a5 + set_ccr_zero + ;; bld xx:3, reg8 + bld #6, r0l ; this should NOT set the carry flag. + test_cc_clear + bld #7, r0l ; this should set the carry flag. + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + + test_grs_a5a5 ; general registers should not be changed. + +bld_imm3_ind: + set_grs_a5a5 +.if (sim_cpu == h8300) + mov #byte_src, r1 + set_ccr_zero + ;; bld xx:3, ind + bld #6, @r1 ; this should NOT set the carry flag. + test_cc_clear + bld #7, @r1 ; this should set the carry flag. + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear +;;; test_h_gr16 byte_src r1 ;FIXME +.else + mov #byte_src, er1 + set_ccr_zero + ;; bld xx:3, ind + bld #6, @er1 ; this should NOT set the carry flag. + test_cc_clear + bld #7, @er1 ; this should NOT set the carry flag. + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + test_h_gr32 byte_src er1 +.endif ; h8300 + test_gr_a5a5 0 ; general registers should not be changed. + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +bld_imm3_abs8: + set_grs_a5a5 + mov.b r1l, @0x20 + set_ccr_zero + ;; bld xx:3, aa:8 + bld #6, @0x20:8 ; this should NOT set the carry flag. + test_cc_clear + bld #7, @0x20:8 ; this should set the carry flag. + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + + test_grs_a5a5 ; general registers should not be changed. + +.if (sim_cpu) ; non-zero means not h8300 +bld_imm3_abs16: + set_grs_a5a5 + set_ccr_zero + ;; bld xx:3, aa:16 + bld #6, @byte_src:16 ; this should NOT set the carry flag. + test_cc_clear + bld #7, @byte_src:16 ; this should set the carry flag. + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + + test_grs_a5a5 ; general registers should not be changed. + +bld_imm3_abs32: + set_grs_a5a5 + set_ccr_zero + ;; bld xx:3, aa:32 + bld #6, @byte_src:32 ; this should NOT set the carry flag. + test_cc_clear + bld #7, @byte_src:32 ; this should set the carry flag. + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + + test_grs_a5a5 ; general registers should not be changed. +.endif + +bst_imm3_reg8: + set_grs_a5a5 + set_ccr_zero + ;; bst xx:3, reg8 + bst #7, r0l ; this should clear bit 7 + test_cc_clear + test_h_gr16 0xa525 r0 + + set_ccr_zero + orc #1, ccr ; set the carry flag + bst #6, r0l ; this should set bit 6 + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + test_h_gr16 0xa565 r0 + + test_gr_a5a5 1 ; Rest of general regs should not be changed. + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +bst_imm3_abs8: + set_grs_a5a5 + mov.b r1l, @0x20 + set_ccr_zero + ;; bst xx:3, aa:8 + bst #7, @0x20:8 ; this should clear bit 7 + test_cc_clear + mov.b @0x20, r0l + test_h_gr16 0xa525 r0 + + set_ccr_zero + orc #1, ccr ; set the carry flag + bst #6, @0x20:8 ; this should set bit 6 + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + mov.b @0x20, r0l + test_h_gr16 0xa565 r0 + + test_gr_a5a5 1 ; general registers should not be changed. + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +bstz_imm3_abs8: + set_grs_a5a5 + mov.b r1l, @0x20 + set_ccr_zero + ;; bstz xx:3, aa:8 + bstz #7, @0x20:8 ; this should clear bit 7 + test_cc_clear + mov.b @0x20, r0l + test_h_gr16 0xa525 r0 + + set_ccr_zero + orc #4, ccr ; set the zero flag + bstz #6, @0x20:8 ; this should set bit 6 + test_carry_clear + test_ovf_clear + test_neg_clear + test_zero_set + mov.b @0x20, r0l + test_h_gr16 0xa565 r0 + + test_gr_a5a5 1 ; general registers should not be changed. + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif ; h8sx + +btst_imm3_reg8: + set_grs_a5a5 + set_ccr_zero + ;; btst xx:3, reg8 + btst #7, r0l ; this should NOT set the zero flag. + test_cc_clear + btst #6, r0l ; this should set the zero flag. + test_carry_clear + test_ovf_clear + test_neg_clear + test_zero_set + + test_grs_a5a5 ; general registers should not be changed. + +btst_imm3_ind: + set_grs_a5a5 +.if (sim_cpu == h8300) + mov #byte_src, r1 + set_ccr_zero + ;; btst xx:3, ind + btst #7, @r1 ; this should NOT set the zero flag. + test_cc_clear + btst #6, @r1 ; this should set the zero flag. + test_carry_clear + test_ovf_clear + test_neg_clear + test_zero_set +;;; test_h_gr16 byte_src r1 ;FIXME +.else + mov #byte_src, er1 + set_ccr_zero + ;; btst xx:3, ind + btst #7, @er1 ; this should NOT set the zero flag. + test_cc_clear + btst #6, @er1 ; this should NOT set the zero flag. + test_carry_clear + test_ovf_clear + test_neg_clear + test_zero_set + test_h_gr32 byte_src er1 +.endif ; h8300 + test_gr_a5a5 0 ; general registers should not be changed. + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +btst_imm3_abs8: + set_grs_a5a5 + mov.b r1l, @0x20 + set_ccr_zero + ;; btst xx:3, aa:8 + btst #7, @0x20:8 ; this should NOT set the zero flag. + test_cc_clear + btst #6, @0x20:8 ; this should set the zero flag. + test_carry_clear + test_ovf_clear + test_neg_clear + test_zero_set + + test_grs_a5a5 ; general registers should not be changed. + +.if (sim_cpu) ; non-zero means not h8300 +btst_imm3_abs16: + set_grs_a5a5 + set_ccr_zero + ;; btst xx:3, aa:16 + btst #7, @byte_src:16 ; this should NOT set the zero flag. + test_cc_clear + btst #6, @byte_src:16 ; this should set the zero flag. + test_carry_clear + test_ovf_clear + test_neg_clear + test_zero_set + + test_grs_a5a5 ; general registers should not be changed. + +btst_imm3_abs32: + set_grs_a5a5 + set_ccr_zero + ;; btst xx:3, aa:32 + btst #7, @byte_src:32 ; this should NOT set the zero flag. + test_cc_clear + btst #6, @byte_src:32 ; this should set the zero flag. + test_carry_clear + test_ovf_clear + test_neg_clear + test_zero_set + + test_grs_a5a5 ; general registers should not be changed. +.endif + + pass + exit 0 diff --git a/sim/testsuite/sim/h8300/bfld.s b/sim/testsuite/sim/h8300/bfld.s new file mode 100644 index 0000000..7c55007 --- /dev/null +++ b/sim/testsuite/sim/h8300/bfld.s @@ -0,0 +1,286 @@ +# Hitachi H8 testcase 'bfld', 'bfst' +# mach(): h8sx +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + .data +byte_src: .byte 0xa5 +byte_dst: .byte 0 + + start + +.if (sim_cpu == h8sx) +bfld_imm8_ind: + set_grs_a5a5 + mov #byte_src, er2 + + ;; bfld #xx:8, @ers, rd8 + set_ccr_zero + bfld #1, @er2, r1l + test_cc_clear + test_h_gr8 1 r1l + + set_ccr_zero + bfld #2, @er2, r1l + test_cc_clear + test_h_gr8 0 r1l + + set_ccr_zero + bfld #7, @er2, r1l + test_cc_clear + test_h_gr8 5 r1l + + set_ccr_zero + bfld #0x10, @er2, r1l + test_cc_clear + test_h_gr8 0 r1l + + set_ccr_zero + bfld #0x20, @er2, r1l + test_cc_clear + test_h_gr8 1 r1l + + set_ccr_zero + bfld #0xf0, @er2, r1l + test_cc_clear + test_h_gr8 0xa r1l + + test_h_gr32 0xa5a5a5a5 er0 + test_h_gr32 0xa5a5a50a er1 + test_h_gr32 byte_src er2 + test_h_gr32 0xa5a5a5a5 er3 + test_h_gr32 0xa5a5a5a5 er4 + test_h_gr32 0xa5a5a5a5 er5 + test_h_gr32 0xa5a5a5a5 er6 + test_h_gr32 0xa5a5a5a5 er7 + +bfld_imm8_abs16: + set_grs_a5a5 + + ;; bfld #xx:8, @aa:16, rd8 + set_ccr_zero + bfld #0x80, @byte_src:16, r1l + test_cc_clear + test_h_gr8 1 r1l + + set_ccr_zero + bfld #0x40, @byte_src:16, r1l + test_cc_clear + test_h_gr8 0 r1l + + set_ccr_zero + bfld #0xe0, @byte_src:16, r1l + test_cc_clear + test_h_gr8 0x5 r1l + + set_ccr_zero + bfld #0x3c, @byte_src:16, r1l + test_cc_clear + test_h_gr8 9 r1l + + set_ccr_zero + bfld #0xfe, @byte_src:16, r1l + test_cc_clear + test_h_gr8 0x52 r1l + + set_ccr_zero + bfld #0, @byte_src:16, r1l + test_cc_clear + test_h_gr8 0 r1l + + test_h_gr32 0xa5a5a5a5 er0 + test_h_gr32 0xa5a5a500 er1 + test_h_gr32 0xa5a5a5a5 er2 + test_h_gr32 0xa5a5a5a5 er3 + test_h_gr32 0xa5a5a5a5 er4 + test_h_gr32 0xa5a5a5a5 er5 + test_h_gr32 0xa5a5a5a5 er6 + test_h_gr32 0xa5a5a5a5 er7 + +bfst_imm8_ind: + set_grs_a5a5 + mov #byte_dst, er2 + + ;; bfst rd8, #xx:8, @ers + mov.b #0, @byte_dst + set_ccr_zero + bfst r1l, #1, @er2 +;;; .word 0x7d20 +;;; .word 0xf901 + + test_cc_clear + cmp.b #1, @byte_dst + bne fail1:16 + + mov.b #0, @byte_dst + set_ccr_zero + bfst r1l, #2, @er2 +;;; .word 0x7d20 +;;; .word 0xf902 + + test_cc_clear + cmp.b #2, @byte_dst + bne fail1:16 + + mov.b #0, @byte_dst + set_ccr_zero + bfst r1l, #7, @er2 +;;; .word 0x7d20 +;;; .word 0xf907 + + test_cc_clear + cmp.b #5, @byte_dst + bne fail1:16 + + mov.b #0, @byte_dst + set_ccr_zero + bfst r1l, #0x10, @er2 +;;; .word 0x7d20 +;;; .word 0xf910 + + test_cc_clear + cmp.b #0x10, @byte_dst + bne fail1:16 + + mov.b #0, @byte_dst + set_ccr_zero + bfst r1l, #0x20, @er2 +;;; .word 0x7d20 +;;; .word 0xf920 + + test_cc_clear + cmp.b #0x20, @byte_dst + bne fail1:16 + + mov.b #0, @byte_dst + set_ccr_zero + bfst r1l, #0xf0, @er2 +;;; .word 0x7d20 +;;; .word 0xf9f0 + + test_cc_clear + cmp.b #0x50, @byte_dst + bne fail1:16 + + test_h_gr32 0xa5a5a5a5 er0 + test_h_gr32 0xa5a5a5a5 er1 + test_h_gr32 byte_dst er2 + test_h_gr32 0xa5a5a5a5 er3 + test_h_gr32 0xa5a5a5a5 er4 + test_h_gr32 0xa5a5a5a5 er5 + test_h_gr32 0xa5a5a5a5 er6 + test_h_gr32 0xa5a5a5a5 er7 + +bfst_imm8_abs32: + set_grs_a5a5 + + ;; bfst #xx:8, @aa:32, rd8 + mov.b #0, @byte_dst + set_ccr_zero + bfst r1l, #0x80, @byte_dst:32 +;;; .word 0x6a38 +;;; .long byte_dst +;;; .word 0xf980 + + test_cc_clear + cmp.b #0x80, @byte_dst + bne fail1:16 + + mov.b #0, @byte_dst + set_ccr_zero + bfst r1l, #0x40, @byte_dst:32 +;;; .word 0x6a38 +;;; .long byte_dst +;;; .word 0xf940 + + test_cc_clear + cmp.b #0x40, @byte_dst + bne fail1:16 + + mov.b #0, @byte_dst + set_ccr_zero + bfst r1l, #0xe0, @byte_dst:32 +;;; .word 0x6a38 +;;; .long byte_dst +;;; .word 0xf9e0 + + test_cc_clear + cmp.b #0xa0, @byte_dst + bne fail1:16 + + mov.b #0, @byte_dst + set_ccr_zero + bfst r1l, #0x3c, @byte_dst:32 +;;; .word 0x6a38 +;;; .long byte_dst +;;; .word 0xf93c + + test_cc_clear + cmp.b #0x14, @byte_dst + bne fail1:16 + + mov.b #0, @byte_dst + set_ccr_zero + bfst r1l, #0xfe, @byte_dst:32 +;;; .word 0x6a38 +;;; .long byte_dst +;;; .word 0xf9fe + + test_cc_clear + cmp.b #0x4a, @byte_dst + bne fail1:16 + + mov.b #0, @byte_dst + set_ccr_zero + bfst r1l, #0, @byte_dst:32 +;;; .word 0x6a38 +;;; .long byte_dst +;;; .word 0xf900 + + test_cc_clear + cmp.b #0x0, @byte_dst + bne fail1:16 + + mov.b #0, @byte_dst + set_ccr_zero + bfst r1l, #0x38, @byte_dst:32 +;;; .word 0x6a38 +;;; .long byte_dst +;;; .word 0xf938 + + test_cc_clear + cmp.b #0x28, @byte_dst + bne fail1:16 + + ;; + ;; Now let's do one in which the bits in the destination + ;; are appropriately combined with the bits in the source. + ;; + + mov.b #0xc3, @byte_dst + set_ccr_zero + bfst r1l, #0x3c, @byte_dst:32 +;;; .word 0x6a38 +;;; .long byte_dst +;;; .word 0xf93c + + test_cc_clear + cmp.b #0xd7, @byte_dst + bne fail1:16 + + test_grs_a5a5 + +.endif + pass + + exit 0 + +fail1: fail + diff --git a/sim/testsuite/sim/h8300/biand.s b/sim/testsuite/sim/h8300/biand.s new file mode 100644 index 0000000..07d3ecf --- /dev/null +++ b/sim/testsuite/sim/h8300/biand.s @@ -0,0 +1,473 @@ +# Hitachi H8 testcase 'biand', 'bior', 'bixor', 'bild', 'bist', 'bistz' +# mach(): all +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + .data +byte_src: .byte 0xa5 +byte_dst: .byte 0 + + start + +biand_imm3_reg8: + set_grs_a5a5 + set_ccr_zero + ;; biand xx:3, reg8 + biand #6, r0l ; this should NOT set the carry flag. + test_cc_clear + biand #7, r0l ; this should NOT set the carry flag. + test_cc_clear + + orc #1, ccr ; set the carry flag + biand #6, r0l ; this should NOT clear the carry flag + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + biand #7, r0l ; this should clear the carry flag + test_cc_clear + + test_grs_a5a5 ; general registers should not be changed. + +biand_imm3_ind: + set_grs_a5a5 +.if (sim_cpu == h8300) + mov #byte_src, r1 + set_ccr_zero + ;; biand xx:3, ind + biand #6, @r1 ; this should NOT set the carry flag. + test_cc_clear + biand #7, @r1 ; this should NOT set the carry flag. + test_cc_clear + + orc #1, ccr ; set the carry flag + biand #6, @r1 ; this should NOT clear the carry flag + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + biand #7, @r1 ; this should clear the carry flag + test_cc_clear +;;; test_h_gr16 byte_src r1 ;FIXME +.else + mov #byte_src, er1 + set_ccr_zero + ;; biand xx:3, ind + biand #6, @er1 ; this should NOT set the carry flag. + test_cc_clear + biand #7, @er1 ; this should NOT set the carry flag. + test_cc_clear + + orc #1, ccr ; set the carry flag + biand #6, @er1 ; this should NOT clear the carry flag + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + biand #7, @er1 ; this should clear the carry flag + test_cc_clear + test_h_gr32 byte_src er1 +.endif ; h8300 + test_gr_a5a5 0 ; general registers should not be changed. + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +biand_imm3_abs8: + set_grs_a5a5 + mov.b r1l, @0x20 + set_ccr_zero + ;; biand xx:3, aa:8 + biand #6, @0x20:8 ; this should NOT set the carry flag. + test_cc_clear + biand #7, @0x20:8 ; this should NOT set the carry flag. + test_cc_clear + + orc #1, ccr ; set the carry flag + biand #6, @0x20:8 ; this should NOT clear the carry flag + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + biand #7, @0x20:8 ; this should clear the carry flag + test_cc_clear + + test_grs_a5a5 ; general registers should not be changed. + +.if (sim_cpu) ; non-zero means not h8300 +biand_imm3_abs16: + set_grs_a5a5 + set_ccr_zero + ;; biand xx:3, aa:16 + biand #6, @byte_src:16 ; this should NOT set the carry flag. + test_cc_clear + biand #7, @byte_src:16 ; this should NOT set the carry flag. + test_cc_clear + + orc #1, ccr ; set the carry flag + biand #6, @byte_src:16 ; this should NOT clear the carry flag + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + biand #7, @byte_src:16 ; this should clear the carry flag + test_cc_clear + + test_grs_a5a5 ; general registers should not be changed. + +biand_imm3_abs32: + set_grs_a5a5 + set_ccr_zero + ;; biand xx:3, aa:32 + biand #6, @byte_src:32 ; this should NOT set the carry flag. + test_cc_clear + biand #7, @byte_src:32 ; this should NOT set the carry flag. + test_cc_clear + + orc #1, ccr ; set the carry flag + biand #6, @byte_src:32 ; this should NOT clear the carry flag + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + biand #7, @byte_src:32 ; this should clear the carry flag + test_cc_clear + + test_grs_a5a5 ; general registers should not be changed. +.endif + +bior_imm3_reg8: + set_grs_a5a5 + set_ccr_zero + ;; bior xx:3, reg8 + bior #7, r0l ; this should NOT set the carry flag. + test_cc_clear + + bior #6, r0l ; this should set the carry flag. + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + + orc #1, ccr ; set the carry flag + bior #6, r0l ; this should NOT clear the carry flag + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + bior #7, r0l ; this should NOT clear the carry flag + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + + test_grs_a5a5 ; general registers should not be changed. + +bior_imm3_abs8: + set_grs_a5a5 + mov.b r1l, @0x20 + set_ccr_zero + ;; bior xx:3, aa:8 + bior #7, @0x20:8 ; this should NOT set the carry flag. + test_cc_clear + bior #6, @0x20:8 ; this should set the carry flag. + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + + orc #1, ccr ; set the carry flag + bior #6, @0x20:8 ; this should NOT clear the carry flag + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + bior #7, @0x20:8 ; this should NOT clear the carry flag + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + + test_grs_a5a5 ; general registers should not be changed. + +bixor_imm3_reg8: + set_grs_a5a5 + set_ccr_zero + ;; bixor xx:3, reg8 + bixor #7, r0l ; this should NOT set the carry flag. + test_cc_clear + + bixor #6, r0l ; this should set the carry flag. + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + + orc #1, ccr ; set the carry flag + bixor #7, r0l ; this should NOT clear the carry flag + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + + bixor #6, r0l ; this should clear the carry flag + test_cc_clear + + test_grs_a5a5 ; general registers should not be changed. + +bixor_imm3_abs8: + set_grs_a5a5 + mov.b r1l, @0x20 + set_ccr_zero + ;; bixor xx:3, aa:8 + bixor #7, @0x20:8 ; this should NOT set the carry flag. + test_cc_clear + bixor #6, @0x20:8 ; this should set the carry flag. + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + + orc #1, ccr ; set the carry flag + bixor #7, @0x20:8 ; this should NOT clear the carry flag + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + + bixor #6, @0x20:8 ; this should clear the carry flag + test_cc_clear + + test_grs_a5a5 ; general registers should not be changed. + +bild_imm3_reg8: + set_grs_a5a5 + set_ccr_zero + ;; bild xx:3, reg8 + bild #7, r0l ; this should NOT set the carry flag. + test_cc_clear + bild #6, r0l ; this should set the carry flag. + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + + test_grs_a5a5 ; general registers should not be changed. + +bild_imm3_ind: + set_grs_a5a5 +.if (sim_cpu == h8300) + mov #byte_src, r1 + set_ccr_zero + ;; bild xx:3, ind + bild #7, @r1 ; this should NOT set the carry flag. + test_cc_clear + bild #6, @r1 ; this should set the carry flag. + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear +;;; test_h_gr16 byte_src r1 ;FIXME +.else + mov #byte_src, er1 + set_ccr_zero + ;; bild xx:3, ind + bild #7, @er1 ; this should NOT set the carry flag. + test_cc_clear + bild #6, @er1 ; this should NOT set the carry flag. + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + test_h_gr32 byte_src er1 +.endif ; h8300 + test_gr_a5a5 0 ; general registers should not be changed. + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +bild_imm3_abs8: + set_grs_a5a5 + mov.b r1l, @0x20 + set_ccr_zero + ;; bild xx:3, aa:8 + bild #7, @0x20:8 ; this should NOT set the carry flag. + test_cc_clear + bild #6, @0x20:8 ; this should set the carry flag. + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + + test_grs_a5a5 ; general registers should not be changed. + +.if (sim_cpu) ; non-zero means not h8300 +bild_imm3_abs16: + set_grs_a5a5 + set_ccr_zero + ;; bild xx:3, aa:16 + bild #7, @byte_src:16 ; this should NOT set the carry flag. + test_cc_clear + bild #6, @byte_src:16 ; this should set the carry flag. + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + + test_grs_a5a5 ; general registers should not be changed. + +bild_imm3_abs32: + set_grs_a5a5 + set_ccr_zero + ;; bild xx:3, aa:32 + bild #7, @byte_src:32 ; this should NOT set the carry flag. + test_cc_clear + bild #6, @byte_src:32 ; this should set the carry flag. + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + + test_grs_a5a5 ; general registers should not be changed. +.endif + +bist_imm3_reg8: + set_grs_a5a5 + set_ccr_zero + ;; bist xx:3, reg8 + bist #6, r0l ; this should set bit 6 + test_cc_clear + test_h_gr16 0xa5e5 r0 + + set_ccr_zero + orc #1, ccr ; set the carry flag + bist #7, r0l ; this should clear bit 7 + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + test_h_gr16 0xa565 r0 + + test_gr_a5a5 1 ; Rest of general regs should not be changed. + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +bist_imm3_abs8: + set_grs_a5a5 + mov.b r1l, @0x20 + set_ccr_zero + ;; bist xx:3, aa:8 + bist #6, @0x20:8 ; this should set bit 6 + test_cc_clear + mov.b @0x20, r0l + test_h_gr16 0xa5e5 r0 + + set_ccr_zero + orc #1, ccr ; set the carry flag + bist #7, @0x20:8 ; this should clear bit 7 + test_carry_set + test_ovf_clear + test_neg_clear + test_zero_clear + mov.b @0x20, r0l + test_h_gr16 0xa565 r0 + + test_gr_a5a5 1 ; general registers should not be changed. + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +bistz_imm3_abs8: + set_grs_a5a5 + mov.b r1l, @0x20 + set_ccr_zero + ;; bistz xx:3, aa:8 + bistz #6, @0x20:8 ; this should set bit 6 + test_cc_clear + mov.b @0x20, r0l + test_h_gr16 0xa5e5 r0 + + set_ccr_zero + orc #4, ccr ; set the zero flag + bistz #7, @0x20:8 ; this should clear bit 7 + test_carry_clear + test_ovf_clear + test_neg_clear + test_zero_set + mov.b @0x20, r0l + test_h_gr16 0xa565 r0 + + test_gr_a5a5 1 ; general registers should not be changed. + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif ; h8sx + +bnot_imm3_reg8: + set_grs_a5a5 + set_ccr_zero + ;; bnot xx:3, reg8 + bnot #7, r0l + test_cc_clear + test_h_gr16 0xa525 r0 + set_ccr_zero + bnot #6, r0l + test_cc_clear + test_h_gr16 0xa565 r0 + set_ccr_zero + bnot #5, r0l + test_cc_clear + test_h_gr16 0xa545 r0 + set_ccr_zero + bnot #4, r0l + test_cc_clear + test_h_gr16 0xa555 r0 + set_ccr_zero + + bnot #4, r0l + bnot #5, r0l + bnot #6, r0l + bnot #7, r0l + test_cc_clear + test_grs_a5a5 ; general registers should not be changed. + +bnot_imm3_abs8: + set_grs_a5a5 + mov.b r1l, @0x20 + set_ccr_zero + ;; bnot xx:3, aa:8 + bnot #7, @0x20:8 + bnot #6, @0x20:8 + bnot #5, @0x20:8 + bnot #4, @0x20:8 + test_cc_clear + test_grs_a5a5 + mov @0x20, r0l + test_h_gr16 0xa555 r0 + + pass + exit 0 diff --git a/sim/testsuite/sim/h8300/bra.s b/sim/testsuite/sim/h8300/bra.s new file mode 100644 index 0000000..2ec10dc --- /dev/null +++ b/sim/testsuite/sim/h8300/bra.s @@ -0,0 +1,165 @@ +# Hitachi H8 testcase 'bra' +# mach(): all +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + start +.if (sim_cpu == h8sx) + .data + .align 4 +disp8: .long tgt_reg8 +disp16: .long tgt_reg16 +disp32: .long tgt_reg32 +dslot: .byte 0 + .text +.endif + +bra_8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; bra dd:8 ; 8-bit displacement + bra tgt_8:8 +;;; .word 0x40xx ; where "xx" is tgt_8 - '.'. + fail + +tgt_8: + test_cc_clear + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu) ; not available in h8/300 mode +bra_16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; bra dd:16 ; 16-bit displacement + bra tgt_24:16 ; NOTE: hard-coded to avoid relaxing. +;;; .word 0x5800 +;;; .word tgt_24 - . + fail + +tgt_24: + test_cc_clear + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif + +.if (sim_cpu == h8sx) +bra_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; bra rn.b ; 8-bit register indirect + sub.l #src8, @disp8 + mov.l @disp8, er5 + bra r5l.b +;;; .word 0x5955 +src8: fail + +tgt_reg8: + test_cc_clear + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 +;;; test_h_gr32 tgt_reg8 er5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +bra_reg16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; bra rn.w ; 16-bit register indirect + sub.l #src16, @disp16 + mov.l @disp16, er5 + bra r5.w +;;; .word 0x5956 +src16: fail + +tgt_reg16: + test_cc_clear + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 +;;; test_h_gr32 tgt_reg16 er5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +bra_reg32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; bra ern ; 32-bit register indirect + sub.l #src32, @disp32 + mov.l @disp32, er5 + bra er5.l +;;; .word 0x5957 +src32: fail + +tgt_reg32: + test_cc_clear + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 +;;; test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +bra_s: set_grs_a5a5 + set_ccr_zero + + bra/s tgt_post_delay +;;; .word 0x4017 + ;; The following instruction is in the delay slot, and should execute. + mov.b #1, @dslot + ;; After this, the next instructions should not execute. + fail + +tgt_post_delay: + test_cc_clear + cmp.b #0, @dslot ; Should be non-zero if delay slot executed. + bne dslot_ok + fail + +dslot_ok: + test_gr_a5a5 0 ; Make sure all general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.endif + + pass + exit 0 + + \ No newline at end of file diff --git a/sim/testsuite/sim/h8300/brabc.s b/sim/testsuite/sim/h8300/brabc.s new file mode 100644 index 0000000..b9a08ea --- /dev/null +++ b/sim/testsuite/sim/h8300/brabc.s @@ -0,0 +1,116 @@ +# Hitachi H8 testcase 'bra/bc' +# mach(): h8sx +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + .data +byte_src: .byte 0xa5 + + start + +.if (sim_cpu == h8sx) +brabc_ind_disp8: + set_grs_a5a5 + mov #byte_src, er1 + set_ccr_zero + ;; bra/bc xx:3, @erd, disp8 + bra/bc #1, @er1, .Lpass1:8 +;;; .word 0x7c10 +;;; .word 0x4110 + fail +.Lpass1: + bra/bc #2, @er1, .Lfail1:8 +;;; .word 0x7c10 +;;; .word 0x4202 + bra .Lpass2 +.Lfail1: + fail +.Lpass2: + test_cc_clear + test_h_gr32 0xa5a5a5a5 er0 + test_h_gr32 byte_src er1 + test_h_gr32 0xa5a5a5a5 er2 + test_h_gr32 0xa5a5a5a5 er3 + test_h_gr32 0xa5a5a5a5 er4 + test_h_gr32 0xa5a5a5a5 er5 + test_h_gr32 0xa5a5a5a5 er6 + test_h_gr32 0xa5a5a5a5 er7 + +brabc_abs8_disp16: + set_grs_a5a5 + mov.b #0xa5, @0x20:32 + set_ccr_zero + ;; bra/bc xx:3, @aa:8, disp16 + bra/bc #1, @0x20:8, .Lpass3:16 + fail +.Lpass3: + bra/bc #2, @0x20:8, Lfail:16 + + test_cc_clear + test_grs_a5a5 + +brabc_abs16_disp16: + set_grs_a5a5 + set_ccr_zero + ;; bra/bc xx:3, @aa:16, disp16 + bra/bc #1, @byte_src:16, .Lpass5:16 + fail +.Lpass5: + bra/bc #2, @byte_src:16, Lfail:16 + + test_cc_clear + test_grs_a5a5 + +brabs_ind_disp8: + set_grs_a5a5 + mov #byte_src, er1 + set_ccr_zero + ;; bra/bs xx:3, @erd, disp8 + bra/bs #2, @er1, .Lpass7:8 +;;; .word 0x7c10 +;;; .word 0x4a10 + fail +.Lpass7: + bra/bs #1, @er1, .Lfail3:8 +;;; .word 0x7c10 +;;; .word 0x4902 + bra .Lpass8 +.Lfail3: + fail +.Lpass8: + test_cc_clear + test_h_gr32 0xa5a5a5a5 er0 + test_h_gr32 byte_src er1 + test_h_gr32 0xa5a5a5a5 er2 + test_h_gr32 0xa5a5a5a5 er3 + test_h_gr32 0xa5a5a5a5 er4 + test_h_gr32 0xa5a5a5a5 er5 + test_h_gr32 0xa5a5a5a5 er6 + test_h_gr32 0xa5a5a5a5 er7 + +brabs_abs32_disp16: + set_grs_a5a5 + set_ccr_zero + ;; bra/bs xx:3, @aa:32, disp16 + bra/bs #2, @byte_src:32, .Lpass9:16 + fail +.Lpass9: + bra/bs #1, @byte_src:32, Lfail:16 + + test_cc_clear + test_grs_a5a5 + +.endif + + pass + + exit 0 + +Lfail: fail diff --git a/sim/testsuite/sim/h8300/bset.s b/sim/testsuite/sim/h8300/bset.s new file mode 100644 index 0000000..a94e916 --- /dev/null +++ b/sim/testsuite/sim/h8300/bset.s @@ -0,0 +1,886 @@ +# Hitachi H8 testcase 'bset', 'bclr' +# mach(): all +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + # Instructions tested: + # + # bset xx:3, rd8 ; 7 0 ?xxx rd8 + # bclr xx:3, rd8 ; 7 2 ?xxx rd8 + # bset xx:3, @erd ; 7 d 0rd ???? 7 0 ?xxx ???? + # bclr xx:3, @erd ; 7 d 0rd ???? 7 2 ?xxx ???? + # bset xx:3, @abs16 ; 6 a 1 1??? aa:16 7 0 ?xxx ???? + # bclr xx:3, @abs16 ; 6 a 1 1??? aa:16 7 2 ?xxx ???? + # bset reg8, rd8 ; 6 0 rs8 rd8 + # bclr reg8, rd8 ; 6 2 rs8 rd8 + # bset reg8, @erd ; 7 d 0rd ???? 6 0 rs8 ???? + # bclr reg8, @erd ; 7 d 0rd ???? 6 2 rs8 ???? + # bset reg8, @abs32 ; 6 a 3 1??? aa:32 6 0 rs8 ???? + # bclr reg8, @abs32 ; 6 a 3 1??? aa:32 6 2 rs8 ???? + # + # bset/eq xx:3, rd8 + # bclr/eq xx:3, rd8 + # bset/ne xx:3, rd8 + # bclr/ne xx:3, rd8 + + .data +byte_dst: .byte 0 + + start + +bset_imm3_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; bset xx:3, rd8 + mov #0, r1l + set_ccr_zero + bset #0, r1l + test_cc_clear + test_h_gr8 1 r1l + + set_ccr_zero + bset #1, r1l + test_cc_clear + test_h_gr8 3 r1l + + set_ccr_zero + bset #2, r1l + test_cc_clear + test_h_gr8 7 r1l + + set_ccr_zero + bset #3, r1l + test_cc_clear + test_h_gr8 15 r1l + + set_ccr_zero + bset #4, r1l + test_cc_clear + test_h_gr8 31 r1l + + set_ccr_zero + bset #5, r1l + test_cc_clear + test_h_gr8 63 r1l + + set_ccr_zero + bset #6, r1l + test_cc_clear + test_h_gr8 127 r1l + + set_ccr_zero + bset #7, r1l + test_cc_clear + test_h_gr8 255 r1l + +.if (sim_cpu == h8300) + test_h_gr16 0xa5ff, r1 +.else + test_h_gr32 0xa5a5a5ff er1 +.endif + +bclr_imm3_reg8: + set_ccr_zero + bclr #7, r1l + test_cc_clear + test_h_gr8 127 r1l + + set_ccr_zero + bclr #6, r1l + test_cc_clear + test_h_gr8 63 r1l + + set_ccr_zero + bclr #5, r1l + test_cc_clear + test_h_gr8 31 r1l + + set_ccr_zero + bclr #4, r1l + test_cc_clear + test_h_gr8 15 r1l + + set_ccr_zero + bclr #3, r1l + test_cc_clear + test_h_gr8 7 r1l + + set_ccr_zero + bclr #2, r1l + test_cc_clear + test_h_gr8 3 r1l + + set_ccr_zero + bclr #1, r1l + test_cc_clear + test_h_gr8 1 r1l + + set_ccr_zero + bclr #0, r1l + test_cc_clear + test_h_gr8 0 r1l + + test_gr_a5a5 0 ; Make sure other general regs not disturbed +.if (sim_cpu == h8300) + test_h_gr16 0xa500 r1 +.else + test_h_gr32 0xa5a5a500 er1 +.endif + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu) +bset_imm3_ind: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; bset xx:3, @erd + mov #byte_dst, er1 + set_ccr_zero + bset #0, @er1 + test_cc_clear + mov @er1, r2l + test_h_gr8 1 r2l + + set_ccr_zero + bset #1, @er1 + test_cc_clear + mov @er1, r2l + test_h_gr8 3 r2l + + set_ccr_zero + bset #2, @er1 + test_cc_clear + mov @er1, r2l + test_h_gr8 7 r2l + + set_ccr_zero + bset #3, @er1 + test_cc_clear + mov @er1, r2l + test_h_gr8 15 r2l + + set_ccr_zero + bset #4, @er1 + test_cc_clear + mov @er1, r2l + test_h_gr8 31 r2l + + set_ccr_zero + bset #5, @er1 + test_cc_clear + mov @er1, r2l + test_h_gr8 63 r2l + + set_ccr_zero + bset #6, @er1 + test_cc_clear + mov @er1, r2l + test_h_gr8 127 r2l + + set_ccr_zero + bset #7, @er1 + test_cc_clear + mov @er1, r2l + test_h_gr8 255 r2l + +.if (sim_cpu == h8300) + test_h_gr16 0xa5ff r2 +.else + test_h_gr32 0xa5a5a5ff er2 +.endif + +bclr_imm3_ind: + set_ccr_zero + bclr #7, @er1 + test_cc_clear + mov @er1, r2l + test_h_gr8 127 r2l + + set_ccr_zero + bclr #6, @er1 + test_cc_clear + mov @er1, r2l + test_h_gr8 63 r2l + + set_ccr_zero + bclr #5, @er1 + test_cc_clear + mov @er1, r2l + test_h_gr8 31 r2l + + set_ccr_zero + bclr #4, @er1 + test_cc_clear + mov @er1, r2l + test_h_gr8 15 r2l + + set_ccr_zero + bclr #3, @er1 + test_cc_clear + mov @er1, r2l + test_h_gr8 7 r2l + + set_ccr_zero + bclr #2, @er1 + test_cc_clear + mov @er1, r2l + test_h_gr8 3 r2l + + set_ccr_zero + bclr #1, @er1 + test_cc_clear + mov @er1, r2l + test_h_gr8 1 r2l + + set_ccr_zero + bclr #0, @er1 + test_cc_clear + mov @er1, r2l + test_h_gr8 0 r2l + + test_gr_a5a5 0 ; Make sure other general regs not disturbed +.if (sim_cpu == h8300) + test_h_gr16 byte_dst r1 + test_h_gr16 0xa500 r2 +.else + test_h_gr32 byte_dst er1 + test_h_gr32 0xa5a5a500 er2 +.endif + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +bset_imm3_abs16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; bset xx:3, @aa:16 + set_ccr_zero + bset #0, @byte_dst:16 + test_cc_clear + mov @byte_dst, r2l + test_h_gr8 1 r2l + + set_ccr_zero + bset #1, @byte_dst:16 + test_cc_clear + mov @byte_dst, r2l + test_h_gr8 3 r2l + + set_ccr_zero + bset #2, @byte_dst:16 + test_cc_clear + mov @byte_dst, r2l + test_h_gr8 7 r2l + + set_ccr_zero + bset #3, @byte_dst:16 + test_cc_clear + mov @byte_dst, r2l + test_h_gr8 15 r2l + + set_ccr_zero + bset #4, @byte_dst:16 + test_cc_clear + mov @byte_dst, r2l + test_h_gr8 31 r2l + + set_ccr_zero + bset #5, @byte_dst:16 + test_cc_clear + mov @byte_dst, r2l + test_h_gr8 63 r2l + + set_ccr_zero + bset #6, @byte_dst:16 + test_cc_clear + mov @byte_dst, r2l + test_h_gr8 127 r2l + + set_ccr_zero + bset #7, @byte_dst:16 + test_cc_clear + mov @byte_dst, r2l + test_h_gr8 255 r2l + +.if (sim_cpu == h8300) + test_h_gr16 0xa5ff r2 +.else + test_h_gr32 0xa5a5a5ff er2 +.endif + +bclr_imm3_abs16: + set_ccr_zero + bclr #7, @byte_dst:16 + test_cc_clear + mov @byte_dst, r2l + test_h_gr8 127 r2l + + set_ccr_zero + bclr #6, @byte_dst:16 + test_cc_clear + mov @byte_dst, r2l + test_h_gr8 63 r2l + + set_ccr_zero + bclr #5, @byte_dst:16 + test_cc_clear + mov @byte_dst, r2l + test_h_gr8 31 r2l + + set_ccr_zero + bclr #4, @byte_dst:16 + test_cc_clear + mov @byte_dst, r2l + test_h_gr8 15 r2l + + set_ccr_zero + bclr #3, @byte_dst:16 + test_cc_clear + mov @byte_dst, r2l + test_h_gr8 7 r2l + + set_ccr_zero + bclr #2, @byte_dst:16 + test_cc_clear + mov @byte_dst, r2l + test_h_gr8 3 r2l + + set_ccr_zero + bclr #1, @byte_dst:16 + test_cc_clear + mov @byte_dst, r2l + test_h_gr8 1 r2l + + set_ccr_zero + bclr #0, @byte_dst:16 + test_cc_clear + mov @byte_dst, r2l + test_h_gr8 0 r2l + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 1 +.if (sim_cpu == h8300) + test_h_gr16 0xa500 r2 +.else + test_h_gr32 0xa5a5a500 er2 +.endif + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif + +bset_rs8_rd8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; bset rs8, rd8 + mov #0, r1h + mov #0, r1l + set_ccr_zero + bset r1h, r1l + test_cc_clear + test_h_gr8 1 r1l + + mov #1, r1h + set_ccr_zero + bset r1h, r1l + test_cc_clear + test_h_gr8 3 r1l + + mov #2, r1h + set_ccr_zero + bset r1h, r1l + test_cc_clear + test_h_gr8 7 r1l + + mov #3, r1h + set_ccr_zero + bset r1h, r1l + test_cc_clear + test_h_gr8 15 r1l + + mov #4, r1h + set_ccr_zero + bset r1h, r1l + test_cc_clear + test_h_gr8 31 r1l + + mov #5, r1h + set_ccr_zero + bset r1h, r1l + test_cc_clear + test_h_gr8 63 r1l + + mov #6, r1h + set_ccr_zero + bset r1h, r1l + test_cc_clear + test_h_gr8 127 r1l + + mov #7, r1h + set_ccr_zero + bset r1h, r1l + test_cc_clear + test_h_gr8 255 r1l + +.if (sim_cpu == h8300) + test_h_gr16 0x07ff, r1 +.else + test_h_gr32 0xa5a507ff er1 +.endif + +bclr_rs8_rd8: + mov #7, r1h + set_ccr_zero + bclr r1h, r1l + test_cc_clear + test_h_gr8 127 r1l + + mov #6, r1h + set_ccr_zero + bclr r1h, r1l + test_cc_clear + test_h_gr8 63 r1l + + mov #5, r1h + set_ccr_zero + bclr r1h, r1l + test_cc_clear + test_h_gr8 31 r1l + + mov #4, r1h + set_ccr_zero + bclr r1h, r1l + test_cc_clear + test_h_gr8 15 r1l + + mov #3, r1h + set_ccr_zero + bclr r1h, r1l + test_cc_clear + test_h_gr8 7 r1l + + mov #2, r1h + set_ccr_zero + bclr r1h, r1l + test_cc_clear + test_h_gr8 3 r1l + + mov #1, r1h + set_ccr_zero + bclr r1h, r1l + test_cc_clear + test_h_gr8 1 r1l + + mov #0, r1h + set_ccr_zero + bclr r1h, r1l + test_cc_clear + test_h_gr8 0 r1l + + test_gr_a5a5 0 ; Make sure other general regs not disturbed +.if (sim_cpu == h8300) + test_h_gr16 0x0000 r1 +.else + test_h_gr32 0xa5a50000 er1 +.endif + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu) +bset_rs8_ind: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; bset rs8, @erd + mov #byte_dst, er1 + mov #0, r2h + set_ccr_zero + bset r2h, @er1 + test_cc_clear + mov @er1, r2l + test_h_gr8 1 r2l + + mov #1, r2h + set_ccr_zero + bset r2h, @er1 + test_cc_clear + mov @er1, r2l + test_h_gr8 3 r2l + + mov #2, r2h + set_ccr_zero + bset r2h, @er1 + test_cc_clear + mov @er1, r2l + test_h_gr8 7 r2l + + mov #3, r2h + set_ccr_zero + bset r2h, @er1 + test_cc_clear + mov @er1, r2l + test_h_gr8 15 r2l + + mov #4, r2h + set_ccr_zero + bset r2h, @er1 + test_cc_clear + mov @er1, r2l + test_h_gr8 31 r2l + + mov #5, r2h + set_ccr_zero + bset r2h, @er1 + test_cc_clear + mov @er1, r2l + test_h_gr8 63 r2l + + mov #6, r2h + set_ccr_zero + bset r2h, @er1 + test_cc_clear + mov @er1, r2l + test_h_gr8 127 r2l + + mov #7, r2h + set_ccr_zero + bset r2h, @er1 + test_cc_clear + mov @er1, r2l + test_h_gr8 255 r2l + +.if (sim_cpu == h8300) + test_h_gr16 0x07ff r2 +.else + test_h_gr32 0xa5a507ff er2 +.endif + +bclr_rs8_ind: + mov #7, r2h + set_ccr_zero + bclr r2h, @er1 + test_cc_clear + mov @er1, r2l + test_h_gr8 127 r2l + + mov #6, r2h + set_ccr_zero + bclr r2h, @er1 + test_cc_clear + mov @er1, r2l + test_h_gr8 63 r2l + + mov #5, r2h + set_ccr_zero + bclr r2h, @er1 + test_cc_clear + mov @er1, r2l + test_h_gr8 31 r2l + + mov #4, r2h + set_ccr_zero + bclr r2h, @er1 + test_cc_clear + mov @er1, r2l + test_h_gr8 15 r2l + + mov #3, r2h + set_ccr_zero + bclr r2h, @er1 + test_cc_clear + mov @er1, r2l + test_h_gr8 7 r2l + + mov #2, r2h + set_ccr_zero + bclr r2h, @er1 + test_cc_clear + mov @er1, r2l + test_h_gr8 3 r2l + + mov #1, r2h + set_ccr_zero + bclr r2h, @er1 + test_cc_clear + mov @er1, r2l + test_h_gr8 1 r2l + + mov #0, r2h + set_ccr_zero + bclr r2h, @er1 + test_cc_clear + mov @er1, r2l + test_h_gr8 0 r2l + + test_gr_a5a5 0 ; Make sure other general regs not disturbed +.if (sim_cpu == h8300) + test_h_gr16 byte_dst r1 + test_h_gr16 0x0000 r2 +.else + test_h_gr32 byte_dst er1 + test_h_gr32 0xa5a50000 er2 +.endif + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +bset_rs8_abs32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; bset rs8, @aa:32 + mov #0, r2h + set_ccr_zero + bset r2h, @byte_dst:32 + test_cc_clear + mov @byte_dst, r2l + test_h_gr8 1 r2l + + mov #1, r2h + set_ccr_zero + bset r2h, @byte_dst:32 + test_cc_clear + mov @byte_dst, r2l + test_h_gr8 3 r2l + + mov #2, r2h + set_ccr_zero + bset r2h, @byte_dst:32 + test_cc_clear + mov @byte_dst, r2l + test_h_gr8 7 r2l + + mov #3, r2h + set_ccr_zero + bset r2h, @byte_dst:32 + test_cc_clear + mov @byte_dst, r2l + test_h_gr8 15 r2l + + mov #4, r2h + set_ccr_zero + bset r2h, @byte_dst:32 + test_cc_clear + mov @byte_dst, r2l + test_h_gr8 31 r2l + + mov #5, r2h + set_ccr_zero + bset r2h, @byte_dst:32 + test_cc_clear + mov @byte_dst, r2l + test_h_gr8 63 r2l + + mov #6, r2h + set_ccr_zero + bset r2h, @byte_dst:32 + test_cc_clear + mov @byte_dst, r2l + test_h_gr8 127 r2l + + mov #7, r2h + set_ccr_zero + bset r2h, @byte_dst:32 + test_cc_clear + mov @byte_dst, r2l + test_h_gr8 255 r2l + +.if (sim_cpu == h8300) + test_h_gr16 0x07ff r2 +.else + test_h_gr32 0xa5a507ff er2 +.endif + +bclr_rs8_abs32: + mov #7, r2h + set_ccr_zero + bclr r2h, @byte_dst:32 + test_cc_clear + mov @byte_dst, r2l + test_h_gr8 127 r2l + + mov #6, r2h + set_ccr_zero + bclr r2h, @byte_dst:32 + test_cc_clear + mov @byte_dst, r2l + test_h_gr8 63 r2l + + mov #5, r2h + set_ccr_zero + bclr r2h, @byte_dst:32 + test_cc_clear + mov @byte_dst, r2l + test_h_gr8 31 r2l + + mov #4, r2h + set_ccr_zero + bclr r2h, @byte_dst:32 + test_cc_clear + mov @byte_dst, r2l + test_h_gr8 15 r2l + + mov #3, r2h + set_ccr_zero + bclr r2h, @byte_dst:32 + test_cc_clear + mov @byte_dst, r2l + test_h_gr8 7 r2l + + mov #2, r2h + set_ccr_zero + bclr r2h, @byte_dst:32 + test_cc_clear + mov @byte_dst, r2l + test_h_gr8 3 r2l + + mov #1, r2h + set_ccr_zero + bclr r2h, @byte_dst:32 + test_cc_clear + mov @byte_dst, r2l + test_h_gr8 1 r2l + + mov #0, r2h + set_ccr_zero + bclr r2h, @byte_dst:32 + test_cc_clear + mov @byte_dst, r2l + test_h_gr8 0 r2l + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 1 +.if (sim_cpu == h8300) + test_h_gr16 0x0000 r2 +.else + test_h_gr32 0xa5a50000 er2 +.endif + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif + +.if (sim_cpu == h8sx) +bset_eq_imm3_abs16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; bset/eq xx:3, rd8 + mov #0, @byte_dst + set_ccr_zero + bset/eq #0, @byte_dst:16 ; Zero is clear, should have no effect. + test_cc_clear + mov @byte_dst, r1l + test_h_gr8 0 r1l + + set_ccr_zero + orc #4, ccr ; Set zero flag + bset/eq #0, @byte_dst:16 ; Zero is set: operation should succeed. + + test_neg_clear + test_zero_set + test_ovf_clear + test_carry_clear + + mov @byte_dst, r1l + test_h_gr8 1 r1l + +bclr_eq_imm3_abs32: + mov #1, @byte_dst + set_ccr_zero + bclr/eq #0, @byte_dst:32 ; Zero is clear, should have no effect. + test_cc_clear + mov @byte_dst, r1l + test_h_gr8 1 r1l + + set_ccr_zero + orc #4, ccr ; Set zero flag + bclr/eq #0, @byte_dst:32 ; Zero is set: operation should succeed. + test_neg_clear + test_zero_set + test_ovf_clear + test_carry_clear + mov @byte_dst, r1l + test_h_gr8 0 r1l + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 0xa5a5a500 er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +bset_ne_imm3_abs16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; bset/ne xx:3, aa:16 + mov #0, @byte_dst + set_ccr_zero + orc #4, ccr ; Set zero flag + bset/ne #0, @byte_dst:16 ; Zero is set; should have no effect. + test_zero_set + test_neg_clear + test_ovf_clear + test_carry_clear + mov @byte_dst, r1l + test_h_gr8 0 r1l + + set_ccr_zero + bset/ne #0, @byte_dst:16 ; Zero is clear: operation should succeed. + test_cc_clear + mov @byte_dst, r1l + test_h_gr8 1 r1l + +bclr_ne_imm3_abs32: + mov #1, @byte_dst + set_ccr_zero + orc #4, ccr ; Set zero flag + ;; bclr/ne xx:3, aa:16 + bclr/ne #0, @byte_dst:32 ; Zero is set, should have no effect. + test_neg_clear + test_zero_set + test_ovf_clear + test_carry_clear + mov @byte_dst, r1l + test_h_gr8 1 r1l + + set_ccr_zero + bclr/ne #0, @byte_dst:32 ; Zero is clear: operation should succeed. + test_cc_clear + mov @byte_dst, r1l + test_h_gr8 0 r1l + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 0xa5a5a500 er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif + + pass + exit 0 diff --git a/sim/testsuite/sim/h8300/cmpb.s b/sim/testsuite/sim/h8300/cmpb.s new file mode 100644 index 0000000..1a4f23c --- /dev/null +++ b/sim/testsuite/sim/h8300/cmpb.s @@ -0,0 +1,1086 @@ +# Hitachi H8 testcase 'cmp.b' +# mach(): all +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + # Instructions tested: + # cmp.b #xx:8, rd ; a rd xxxxxxxx + # cmp.b #xx:8, @erd ; 7 d rd ???? a ???? xxxxxxxx + # cmp.b #xx:8, @erd+ ; 0 1 7 4 6 c rd 1??? a ???? xxxxxxxx + # cmp.b #xx:8, @erd- ; 0 1 7 6 6 c rd 1??? a ???? xxxxxxxx + # cmp.b #xx:8, @+erd ; 0 1 7 5 6 c rd 1??? a ???? xxxxxxxx + # cmp.b #xx:8, @-erd ; 0 1 7 7 6 c rd 1??? a ???? xxxxxxxx + # cmp.b rs, rd ; 1 c rs rd + # cmp.b reg8, @erd ; 7 d rd ???? 1 c rs ???? + # cmp.b reg8, @erd+ ; 0 1 7 9 8 rd 2 rs + # cmp.b reg8, @erd- ; 0 1 7 9 a rd 2 rs + # cmp.b reg8, @+erd ; 0 1 7 9 9 rd 2 rs + # cmp.b reg8, @-erd ; 0 1 7 9 b rd 2 rs + # cmp.b rsind, rdind ; 7 c 0rs 5 0 ?rd 2 ???? + # cmp.b rspostinc, rdpostinc ; 0 1 7 4 6 c 0rs c 8 ?rd 2 ???? + # cmp.b rspostdec, rdpostdec ; 0 1 7 6 6 c 0rs c a ?rd 2 ???? + # cmp.b rspreinc, rdpreinc ; 0 1 7 5 6 c 0rs c 9 ?rd 2 ???? + # cmp.b rspredec, rdpredec ; 0 1 7 7 6 c 0rs c b ?rd 2 ???? + # cmp.b disp2, disp2 ; 0 1 7 01dd:2 6 8 0rs c 00dd:2 ?rd 2 ???? + # cmp.b disp16, disp16 ; 0 1 7 4 6 e 0rs c dd:16 c 0rd 2 ???? dd:16 + # cmp.b disp32, disp32 ; 7 8 0rs 4 6 a 2 c dd:32 c 1rd 2 ???? dd:32 + # cmp.b indexb16, indexb16 ; 0 1 7 5 6 e 0rs c dd:16 d 0rd 2 ???? dd:16 + # cmp.b indexw16, indexw16 ; 0 1 7 6 6 e 0rs c dd:16 e 0rd 2 ???? dd:16 + # cmp.b indexl16, indexl16 ; 0 1 7 7 6 e 0rs c dd:16 f 0rd 2 ???? dd:16 + # cmp.b indexb32, indexb32 ; 7 8 0rs 5 6 a 2 c dd:32 d 1rd 2 ???? dd:32 + # cmp.b indexw32, indexw32 ; 7 8 0rs 6 6 a 2 c dd:32 e 1rd 2 ???? dd:32 + # cmp.b indexl32, indexl32 ; 7 8 0rs 7 6 a 2 c dd:32 f 1rd 2 ???? dd:32 + # cmp.b abs16, abs16 ; 6 a 1 5 aa:16 4 0??? 2 ???? aa:16 + # cmp.b abs32, abs32 ; 6 a 3 5 aa:32 4 1??? 2 ???? aa:32 + # + + # Coming soon: + + # ... + +.data +byte_src: .byte 0x5a +pre_byte: .byte 0 +byte_dst: .byte 0xa5 +post_byte: .byte 0 + + start + +cmp_b_imm8_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; cmp.b #xx:8,Rd + cmp.b #0xa5, r0l ; Immediate 8-bit src, reg8 dest + beq .Leq1 + fail +.Leq1: cmp.b #0xa6, r0l + blt .Llt1 + fail +.Llt1: cmp.b #0xa4, r0l + bgt .Lgt1 + fail +.Lgt1: + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0xa5a5 r0 ; r0 unchanged +.if (sim_cpu) ; non-zero means h8300h, s, or sx + test_h_gr32 0xa5a5a5a5 er0 ; er0 unchanged +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +cmp_b_imm8_rdind: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; cmp.b #xx:8,@eRd + mov #byte_dst, er0 + cmp.b #0xa5:8, @er0 ; Immediate 8-bit src, reg indirect dst +;;; .word 0x7d00 +;;; .word 0xa0a5 + beq .Leq2 + fail +.Leq2: set_ccr_zero + cmp.b #0xa6, @er0 +;;; .word 0x7d00 +;;; .word 0xa0a6 + blt .Llt2 + fail +.Llt2: set_ccr_zero + cmp.b #0xa4, @er0 +;;; .word 0x7d00 +;;; .word 0xa0a4 + bgt .Lgt2 + fail +.Lgt2: + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 byte_dst er0 ; er0 still contains address + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the cmp to memory (memory unchanged). + sub.b r0l, r0l + mov.b @byte_dst, r0l + cmp.b #0xa5, r0l + beq .L2 + fail +.L2: + +cmp_b_imm8_rdpostinc: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; cmp.b #xx:8,@eRd+ + mov #byte_dst, er0 + cmp.b #0xa5:8, @er0+ ; Immediate 8-bit src, reg postinc dst +;;; .word 0x0174 +;;; .word 0x6c08 +;;; .word 0xa0a5 + beq .Leq3 + fail +.Leq3: test_h_gr32 post_byte er0 ; er0 contains address plus one + mov #byte_dst, er0 + set_ccr_zero + cmp.b #0xa6, @er0+ +;;; .word 0x0174 +;;; .word 0x6c08 +;;; .word 0xa0a6 + blt .Llt3 + fail +.Llt3: test_h_gr32 post_byte er0 ; er0 contains address plus one + mov #byte_dst, er0 + set_ccr_zero + cmp.b #0xa4, @er0+ +;;; .word 0x0174 +;;; .word 0x6c08 +;;; .word 0xa0a4 + bgt .Lgt3 + fail +.Lgt3: + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 post_byte er0 ; er0 contains address plus one + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the cmp to memory (memory unchanged). + sub.b r0l, r0l + mov.b @byte_dst, r0l + cmp.b #0xa5, r0l + beq .L3 + fail +.L3: + +cmp_b_imm8_rdpostdec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; cmp.b #xx:8,@eRd- + mov #byte_dst, er0 + cmp.b #0xa5:8, @er0- ; Immediate 8-bit src, reg postdec dst +;;; .word 0x0176 +;;; .word 0x6c08 +;;; .word 0xa0a5 + beq .Leq4 + fail +.Leq4: test_h_gr32 pre_byte er0 ; er0 contains address minus one + mov #byte_dst, er0 + set_ccr_zero + cmp.b #0xa6, @er0- +;;; .word 0x0176 +;;; .word 0x6c08 +;;; .word 0xa0a6 + blt .Llt4 + fail +.Llt4: test_h_gr32 pre_byte er0 ; er0 contains address minus one + mov #byte_dst, er0 + set_ccr_zero + cmp.b #0xa4, @er0- +;;; .word 0x0176 +;;; .word 0x6c08 +;;; .word 0xa0a4 + bgt .Lgt4 + fail +.Lgt4: + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 pre_byte er0 ; er0 contains address minus one + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the cmp to memory (memory unchanged). + sub.b r0l, r0l + mov.b @byte_dst, r0l + cmp.b #0xa5, r0l + beq .L4 + fail +.L4: + +cmp_b_imm8_rdpreinc: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; cmp.b #xx:8,@+eRd + mov #pre_byte, er0 + cmp.b #0xa5:8, @+er0 ; Immediate 8-bit src, reg pre-inc dst +;;; .word 0x0175 +;;; .word 0x6c08 +;;; .word 0xa0a5 + beq .Leq5 + fail +.Leq5: test_h_gr32 byte_dst er0 ; er0 contains destination address + mov #pre_byte, er0 + set_ccr_zero + cmp.b #0xa6, @+er0 +;;; .word 0x0175 +;;; .word 0x6c08 +;;; .word 0xa0a6 + blt .Llt5 + fail +.Llt5: test_h_gr32 byte_dst er0 ; er0 contains destination address + mov #pre_byte, er0 + set_ccr_zero + cmp.b #0xa4, @+er0 +;;; .word 0x0175 +;;; .word 0x6c08 +;;; .word 0xa0a4 + bgt .Lgt5 + fail +.Lgt5: + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 byte_dst er0 ; er0 contains destination address + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the cmp to memory (memory unchanged). + sub.b r0l, r0l + mov.b @byte_dst, r0l + cmp.b #0xa5, r0l + beq .L5 + fail +.L5: + +cmp_b_imm8_rdpredec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; cmp.b #xx:8,@-eRd + mov #post_byte, er0 + cmp.b #0xa5:8, @-er0 ; Immediate 8-bit src, reg pre-dec dst +;;; .word 0x0177 +;;; .word 0x6c08 +;;; .word 0xa0a5 + beq .Leq6 + fail +.Leq6: test_h_gr32 byte_dst er0 ; er0 contains destination address + mov #post_byte, er0 + set_ccr_zero + cmp.b #0xa6, @-er0 +;;; .word 0x0177 +;;; .word 0x6c08 +;;; .word 0xa0a6 + blt .Llt6 + fail +.Llt6: test_h_gr32 byte_dst er0 ; er0 contains destination address + mov #post_byte, er0 + set_ccr_zero + cmp.b #0xa4, @-er0 +;;; .word 0x0177 +;;; .word 0x6c08 +;;; .word 0xa0a4 + bgt .Lgt6 + fail +.Lgt6: + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 byte_dst er0 ; er0 contains destination address + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the cmp to memory (memory unchanged). + sub.b r0l, r0l + mov.b @byte_dst, r0l + cmp.b #0xa5, r0l + beq .L6 + fail +.L6: + + +.endif + +cmp_b_reg8_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; cmp.b Rs,Rd + mov.b #0xa5, r0h + cmp.b r0h, r0l ; Reg8 src, reg8 dst + beq .Leq7 + fail +.Leq7: mov.b #0xa6, r0h + cmp.b r0h, r0l + blt .Llt7 + fail +.Llt7: mov.b #0xa4, r0h + cmp.b r0h, r0l + bgt .Lgt7 + fail +.Lgt7: + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0xa4a5 r0 ; r0l unchanged. +.if (sim_cpu) ; non-zero means h8300h, s, or sx + test_h_gr32 0xa5a5a4a5 er0 ; r0l unchanged +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +cmp_b_reg8_rdind: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; cmp.b rs8,@eRd ; cmp reg8 to register indirect + mov #byte_dst, er0 + mov #0xa5, r1l + cmp.b r1l, @er0 ; reg8 src, reg indirect dest +;;; .word 0x7d00 +;;; .word 0x1c90 + beq .Leq8 + fail +.Leq8: set_ccr_zero + mov #0xa6, r1l + cmp.b r1l, @er0 +;;; .word 0x7d00 +;;; .word 0x1c90 + blt .Llt8 + fail +.Llt8: set_ccr_zero + mov #0xa4, r1l + cmp.b r1l, @er0 +;;; .word 0x7d00 +;;; .word 0x1c90 + bgt .Lgt8 + fail +.Lgt8: + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 byte_dst er0 ; er0 still contains address + test_h_gr32 0xa5a5a5a4 er1 ; er1 has the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the cmp to memory (no change). + sub.b r0l, r0l + mov.b @byte_dst, r0l + cmp.b #0xa5, r0l + beq .L8 + fail +.L8: + +cmp_b_reg8_rdpostinc: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; cmp.b reg8,@eRd+ + mov #byte_dst, er0 + mov #0xa5, r1l + cmp.b r1l, @er0+ ; Immediate 8-bit src, reg post-incr dst +;;; .word 0x0179 +;;; .word 0x8029 + beq .Leq9 + fail +.Leq9: test_h_gr32 post_byte er0 ; er0 contains address plus one + mov #byte_dst er0 + mov #0xa6, r1l + set_ccr_zero + cmp.b r1l, @er0+ +;;; .word 0x0179 +;;; .word 0x8029 + blt .Llt9 + fail +.Llt9: test_h_gr32 post_byte er0 ; er0 contains address plus one + mov #byte_dst er0 + mov #0xa4, r1l + set_ccr_zero + cmp.b r1l, @er0+ +;;; .word 0x0179 +;;; .word 0x8029 + bgt .Lgt9 + fail +.Lgt9: + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 post_byte er0 ; er0 contains address plus one + test_h_gr32 0xa5a5a5a4 er1 ; er1 contains test load + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the cmp to memory (memory unchanged). + sub.b r0l, r0l + mov.b @byte_dst, r0l + cmp.b #0xa5, r0l + beq .L9 + fail +.L9: + +cmp_b_reg8_rdpostdec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; cmp.b reg8,@eRd- + mov #byte_dst, er0 + mov #0xa5, r1l + cmp.b r1l, @er0- ; Immediate 8-bit src, reg postdec dst +;;; .word 0x0179 +;;; .word 0xa029 + beq .Leq10 + fail +.Leq10: test_h_gr32 pre_byte er0 ; er0 contains address minus one + mov #byte_dst er0 + mov #0xa6, r1l + set_ccr_zero + cmp.b r1l, @er0- +;;; .word 0x0179 +;;; .word 0xa029 + blt .Llt10 + fail +.Llt10: test_h_gr32 pre_byte er0 ; er0 contains address minus one + mov #byte_dst er0 + mov #0xa4, r1l + set_ccr_zero + cmp.b r1l, @er0- +;;; .word 0x0179 +;;; .word 0xa029 + bgt .Lgt10 + fail +.Lgt10: + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 pre_byte er0 ; er0 contains address minus one + test_h_gr32 0xa5a5a5a4 er1 ; er1 contains test load + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the cmp to memory (memory unchanged). + sub.b r0l, r0l + mov.b @byte_dst, r0l + cmp.b #0xa5, r0l + beq .L10 + fail +.L10: + +cmp_b_reg8_rdpreinc: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; cmp.b reg8,@+eRd + mov #pre_byte, er0 + mov #0xa5, r1l + cmp.b r1l, @+er0 ; Immediate 8-bit src, reg post-incr dst +;;; .word 0x0179 +;;; .word 0x9029 + beq .Leq11 + fail +.Leq11: test_h_gr32 byte_dst er0 ; er0 contains destination address + mov #pre_byte er0 + mov #0xa6, r1l + set_ccr_zero + cmp.b r1l, @+er0 +;;; .word 0x0179 +;;; .word 0x9029 + blt .Llt11 + fail +.Llt11: test_h_gr32 byte_dst er0 ; er0 contains destination address + mov #pre_byte er0 + mov #0xa4, r1l + set_ccr_zero + cmp.b r1l, @+er0 +;;; .word 0x0179 +;;; .word 0x9029 + bgt .Lgt11 + fail +.Lgt11: + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 byte_dst er0 ; er0 contains destination address + test_h_gr32 0xa5a5a5a4 er1 ; er1 contains test load + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the cmp to memory (memory unchanged). + sub.b r0l, r0l + mov.b @byte_dst, r0l + cmp.b #0xa5, r0l + beq .L11 + fail +.L11: + +cmp_b_reg8_rdpredec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; cmp.b reg8,@-eRd + mov #post_byte, er0 + mov #0xa5, r1l + cmp.b r1l, @-er0 ; Immediate 8-bit src, reg postdec dst +;;; .word 0x0179 +;;; .word 0xb029 + beq .Leq12 + fail +.Leq12: test_h_gr32 byte_dst er0 ; er0 contains destination address + mov #post_byte er0 + mov #0xa6, r1l + set_ccr_zero + cmp.b r1l, @-er0 +;;; .word 0x0179 +;;; .word 0xb029 + blt .Llt12 + fail +.Llt12: test_h_gr32 byte_dst er0 ; er0 contains destination address + mov #post_byte er0 + mov #0xa4, r1l + set_ccr_zero + cmp.b r1l, @-er0 +;;; .word 0x0179 +;;; .word 0xb029 + bgt .Lgt12 + fail +.Lgt12: + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 byte_dst er0 ; er0 contains destination address + test_h_gr32 0xa5a5a5a4 er1 ; er1 contains test load + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the cmp to memory (memory unchanged). + sub.b r0l, r0l + mov.b @byte_dst, r0l + cmp.b #0xa5, r0l + beq .L12 + fail +.L12: + +cmp_b_rsind_rdind: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov #byte_src, er1 + mov #byte_dst, er2 + set_ccr_zero + cmp.b @er1, @er2 + test_neg_clear ; N=0, Z=0, V=1, C=0 + test_zero_clear + test_ovf_set + test_carry_clear + + test_gr_a5a5 0 + test_h_gr32 byte_src er1 + test_h_gr32 byte_dst er2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.b #0x5a, @byte_src:16 + bne fail1 + cmp.b #0xa5, @byte_dst:16 + bne fail1 +.if 1 ; ambiguous +cmp_b_rspostinc_rdpostinc: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov #byte_src, er1 + mov #byte_dst, er2 + set_ccr_zero + cmp.b @er1+, @er2+ +;;; .word 0x0174 +;;; .word 0x6c1c +;;; .word 0x8220 + + test_neg_clear ; N=0, Z=0, V=1, C=0 + test_zero_clear + test_ovf_set + test_carry_clear + + test_gr_a5a5 0 + test_h_gr32 byte_src+1 er1 + test_h_gr32 byte_dst+1 er2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.b #0x5a, @byte_src:16 + bne fail1 + cmp.b #0xa5, @byte_dst:16 + bne fail1 +.endif +.if 1 ; ambiguous +cmp_b_rspostdec_rdpostdec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov #byte_src, er1 + mov #byte_dst, er2 + set_ccr_zero + cmp.b @er1-, @er2- +;;; .word 0x0176 +;;; .word 0x6c1c +;;; .word 0xa220 + + test_neg_clear ; N=0, Z=0, V=1, C=0 + test_zero_clear + test_ovf_set + test_carry_clear + + test_gr_a5a5 0 + test_h_gr32 byte_src-1 er1 + test_h_gr32 byte_dst-1 er2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.b #0x5a, @byte_src:16 + bne fail1 + cmp.b #0xa5, @byte_dst:16 + bne fail1 +.endif + +cmp_b_rspreinc_rdpreinc: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov #byte_src-1, er1 + mov #byte_dst-1, er2 + set_ccr_zero + cmp.b @+er1, @+er2 +;;; .word 0x0175 +;;; .word 0x6c1c +;;; .word 0x9220 + + test_neg_clear ; N=0, Z=0, V=1, C=0 + test_zero_clear + test_ovf_set + test_carry_clear + + test_gr_a5a5 0 + test_h_gr32 byte_src er1 + test_h_gr32 byte_dst er2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.b #0x5a, @byte_src:16 + bne fail1 + cmp.b #0xa5, @byte_dst:16 + bne fail1 + +cmp_b_rspredec_predec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov #byte_src+1, er1 + mov #byte_dst+1, er2 + set_ccr_zero + cmp.b @-er1, @-er2 +;;; .word 0x0177 +;;; .word 0x6c1c +;;; .word 0xb220 + + test_neg_clear ; N=0, Z=0, V=1, C=0 + test_zero_clear + test_ovf_set + test_carry_clear + + test_gr_a5a5 0 + test_h_gr32 byte_src er1 + test_h_gr32 byte_dst er2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.b #0x5a, @byte_src:16 + bne fail1 + cmp.b #0xa5, @byte_dst:16 + bne fail1 + +cmp_b_disp2_disp2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov #byte_src-1, er1 + mov #byte_dst-2, er2 + set_ccr_zero + cmp.b @(1:2, er1), @(2:2, er2) +;;; .word 0x0175 +;;; .word 0x681c +;;; .word 0x2220 + + test_neg_clear ; N=0, Z=0, V=1, C=0 + test_zero_clear + test_ovf_set + test_carry_clear + + test_gr_a5a5 0 + test_h_gr32 byte_src-1 er1 + test_h_gr32 byte_dst-2 er2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.b #0x5a, @byte_src:16 + bne fail1 + cmp.b #0xa5, @byte_dst:16 + bne fail1 + +cmp_b_disp16_disp16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov #byte_src-3, er1 + mov #byte_dst-4, er2 + set_ccr_zero + cmp.b @(3:16, er1), @(4:16, er2) +;;; .word 0x0174 +;;; .word 0x6e1c +;;; .word 3 +;;; .word 0xc220 +;;; .word 4 + + test_neg_clear ; N=0, Z=0, V=1, C=0 + test_zero_clear + test_ovf_set + test_carry_clear + + test_gr_a5a5 0 + test_h_gr32 byte_src-3 er1 + test_h_gr32 byte_dst-4 er2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.b #0x5a, @byte_src:16 + bne fail1 + cmp.b #0xa5, @byte_dst:16 + bne fail1 + +cmp_b_disp32_disp32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov #byte_src+5, er1 + mov #byte_dst+6, er2 + set_ccr_zero + cmp.b @(-5:32, er1), @(-6:32, er2) +;;; .word 0x7814 +;;; .word 0x6a2c +;;; .long -5 +;;; .word 0xca20 +;;; .long -6 + + test_neg_clear ; N=0, Z=0, V=1, C=0 + test_zero_clear + test_ovf_set + test_carry_clear + + test_gr_a5a5 0 + test_h_gr32 byte_src+5 er1 + test_h_gr32 byte_dst+6 er2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.b #0x5a, @byte_src:16 + bne fail1 + cmp.b #0xa5, @byte_dst:16 + bne fail1 + +cmp_b_indexb16_indexb16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov #0xffffff01, er1 + mov #0xffffff02, er2 + set_ccr_zero + cmp.b @(byte_src-1:16, r1.b), @(byte_dst-2:16, r2.b) +;;; .word 0x0175 +;;; .word 0x6e1c +;;; .word byte_src-1 +;;; .word 0xd220 +;;; .word byte_dst-2 + + test_neg_clear ; N=0, Z=0, V=1, C=0 + test_zero_clear + test_ovf_set + test_carry_clear + + test_gr_a5a5 0 + test_h_gr32 0xffffff01 er1 + test_h_gr32 0xffffff02 er2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.b #0x5a, @byte_src:16 + bne fail1 + cmp.b #0xa5, @byte_dst:16 + bne fail1 +.if 1 ; ambiguous +cmp_b_indexw16_indexw16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov #0xffff0003, er1 + mov #0xffff0004, er2 + set_ccr_zero + cmp.b @(byte_src-3:16, r1.w), @(byte_dst-4:16, r2.w) +;;; .word 0x0176 +;;; .word 0x6e1c +;;; .word byte_src-3 +;;; .word 0xe220 +;;; .word byte_dst-4 + + test_neg_clear ; N=0, Z=0, V=1, C=0 + test_zero_clear + test_ovf_set + test_carry_clear + + test_gr_a5a5 0 + test_h_gr32 0xffff0003 er1 + test_h_gr32 0xffff0004 er2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.b #0x5a, @byte_src:16 + bne fail1 + cmp.b #0xa5, @byte_dst:16 + bne fail1 +.endif + +cmp_b_indexl16_indexl16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov #0x00000005, er1 + mov #0x00000006, er2 + set_ccr_zero + cmp.b @(byte_src-5:16, er1.l), @(byte_dst-6:16, er2.l) +;;; .word 0x0177 +;;; .word 0x6e1c +;;; .word byte_src-5 +;;; .word 0xf220 +;;; .word byte_dst-6 + + test_neg_clear ; N=0, Z=0, V=1, C=0 + test_zero_clear + test_ovf_set + test_carry_clear + + test_gr_a5a5 0 + test_h_gr32 0x00000005 er1 + test_h_gr32 0x00000006 er2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.b #0x5a, @byte_src:16 + bne fail1 + cmp.b #0xa5, @byte_dst:16 + bne fail1 + +cmp_b_indexb32_indexb32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov #0xffffff01, er1 + mov #0xffffff02, er2 + set_ccr_zero + cmp.b @(byte_src-1:32, r1.b), @(byte_dst-2:32, r2.b) +;;; .word 0x7815 +;;; .word 0x6a2c +;;; .long byte_src-1 +;;; .word 0xda20 +;;; .long byte_dst-2 + + test_neg_clear ; N=0, Z=0, V=1, C=0 + test_zero_clear + test_ovf_set + test_carry_clear + + test_gr_a5a5 0 + test_h_gr32 0xffffff01 er1 + test_h_gr32 0xffffff02 er2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.b #0x5a, @byte_src:16 + bne fail1 + cmp.b #0xa5, @byte_dst:16 + bne fail1 + +.if 1 ; ambiguous +cmp_b_indexw32_indexw32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov #0xffff0003, er1 + mov #0xffff0004, er2 + set_ccr_zero + cmp.b @(byte_src-3:32, r1.w), @(byte_dst-4:32, r2.w) +;;; .word 0x7816 +;;; .word 0x6a2c +;;; .long byte_src-3 +;;; .word 0xea20 +;;; .long byte_dst-4 + + test_neg_clear ; N=0, Z=0, V=1, C=0 + test_zero_clear + test_ovf_set + test_carry_clear + + test_gr_a5a5 0 + test_h_gr32 0xffff0003 er1 + test_h_gr32 0xffff0004 er2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.b #0x5a, @byte_src:16 + bne fail1 + cmp.b #0xa5, @byte_dst:16 + bne fail1 +.endif + +cmp_b_indexl32_indexl32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov #0x00000005, er1 + mov #0x00000006, er2 + set_ccr_zero + cmp.b @(byte_src-5:32, er1.l), @(byte_dst-6:32, er2.l) +;;; .word 0x7817 +;;; .word 0x6a2c +;;; .long byte_src-5 +;;; .word 0xfa20 +;;; .long byte_dst-6 + + test_neg_clear ; N=0, Z=0, V=1, C=0 + test_zero_clear + test_ovf_set + test_carry_clear + + test_gr_a5a5 0 + test_h_gr32 0x00000005 er1 + test_h_gr32 0x00000006 er2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.b #0x5a, @byte_src:16 + bne fail1 + cmp.b #0xa5, @byte_dst:16 + bne fail1 + +cmp_b_abs16_abs16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + cmp.b @byte_src:16, @byte_dst:16 + + test_neg_clear ; N=0, Z=0, V=1, C=0 + test_zero_clear + test_ovf_set + test_carry_clear + + test_grs_a5a5 + cmp.b #0x5a, @byte_src:16 + bne fail1 + cmp.b #0xa5, @byte_dst:16 + bne fail1 + +cmp_b_abs32_abs32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + cmp.b @byte_src:32, @byte_dst:32 + + test_neg_clear ; N=0, Z=0, V=1, C=0 + test_zero_clear + test_ovf_set + test_carry_clear + + test_grs_a5a5 + cmp.b #0x5a, @byte_src:16 + bne fail1 + cmp.b #0xa5, @byte_dst:16 + bne fail1 + +.endif + pass + + exit 0 + +fail1: fail diff --git a/sim/testsuite/sim/h8300/cmpl.s b/sim/testsuite/sim/h8300/cmpl.s new file mode 100644 index 0000000..55f235a --- /dev/null +++ b/sim/testsuite/sim/h8300/cmpl.s @@ -0,0 +1,106 @@ +# Hitachi H8 testcase 'cmp.w' +# mach(): h8300h h8300s h8sx +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + start + +.if (sim_cpu == h8sx) ; 3-bit immediate mode only for h8sx +cmp_l_imm3: ; + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; cmp.l #xx:3,eRd ; Immediate 3-bit operand + mov.l #5, er0 + cmp.l #5, er0 + beq eq3 + fail +eq3: + cmp.l #6, er0 + blt lt3 + fail +lt3: + cmp.l #4, er0 + bgt gt3 + fail +gt3: + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + + test_h_gr32 0x00000005 er0 ; er0 unchanged + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif + +cmp_l_imm16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; cmp.l #xx:8,Rd + cmp.l #0xa5a5a5a5, er0 ; Immediate 16-bit operand + beq eqi + fail +eqi: cmp.l #0xa5a5a5a6, er0 + blt lti + fail +lti: cmp.l #0xa5a5a5a4, er0 + bgt gti + fail +gti: + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + + test_h_gr32 0xa5a5a5a5 er0 ; er0 unchanged + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +cmp_w_reg: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; cmp.l Rs,Rd + mov.l #0xa5a5a5a5, er1 + cmp.l er1, er0 ; Register operand + beq eqr + fail +eqr: mov.l #0xa5a5a5a6, er1 + cmp.l er1, er0 + blt ltr + fail +ltr: mov.l #0xa5a5a5a4, er1 + cmp.l er1, er0 + bgt gtr + fail +gtr: + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + + test_h_gr32 0xa5a5a5a5 er0 ; r0 unchanged + test_h_gr32 0xa5a5a5a4 er1 ; r1 unchanged + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + pass + + exit 0 diff --git a/sim/testsuite/sim/h8300/cmpw.s b/sim/testsuite/sim/h8300/cmpw.s new file mode 100644 index 0000000..872c56c --- /dev/null +++ b/sim/testsuite/sim/h8300/cmpw.s @@ -0,0 +1,126 @@ +# Hitachi H8 testcase 'cmp.w' +# mach(): all +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + start + +.if (sim_cpu == h8sx) ; 3-bit immediate mode only for h8sx +cmp_w_imm3: ; + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; cmp.w #xx:3,Rd ; Immediate 3-bit operand + mov.w #5, r0 + cmp.w #5, r0 + beq eq3 + fail +eq3: + cmp.w #6, r0 + blt lt3 + fail +lt3: + cmp.w #4, r0 + bgt gt3 + fail +gt3: + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr32 0xa5a50005 er0 ; er0 unchanged + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif + +.if (sim_cpu) ; non-zero means h8300h, s, or sx +cmp_w_imm16: ; cmp.w immediate not available in h8300 mode. + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; cmp.w #xx:16,Rd + cmp.w #0xa5a5, r0 ; Immediate 16-bit operand + beq eqi + fail +eqi: cmp.w #0xa5a6, r0 + blt lti + fail +lti: cmp.w #0xa5a4, r0 + bgt gti + fail +gti: + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0xa5a5 r0 ; r0 unchanged +.if (sim_cpu) ; non-zero means h8300h, s, or sx + test_h_gr32 0xa5a5a5a5 er0 ; er0 unchanged +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +cmp_w_imm16_less_than_zero: ; Test for less-than-zero immediate + set_grs_a5a5 + ;; cmp.w #xx:16, Rd, where #xx < 0 (ie. #xx > 0x7fff). + sub.w r0, r0 + cmp.w #0x8001, r0 + bls ltz + fail +ltz: test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.endif + +cmp_w_reg: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; cmp.w Rs,Rd + mov.w #0xa5a5, r1 + cmp.w r1, r0 ; Register operand + beq eqr + fail +eqr: mov.w #0xa5a6, r1 + cmp.w r1, r0 + blt ltr + fail +ltr: mov.w #0xa5a4, r1 + cmp.w r1, r0 + bgt gtr + fail +gtr: + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0xa5a5 r0 ; r0 unchanged. + test_h_gr16 0xa5a4 r1 ; r1 unchanged. +.if (sim_cpu) ; non-zero means h8300h, s, or sx + test_h_gr32 0xa5a5a5a5 er0 ; r0 unchanged + test_h_gr32 0xa5a5a5a4 er1 ; r1 unchanged +.endif + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + pass + + exit 0 diff --git a/sim/testsuite/sim/h8300/daa.s b/sim/testsuite/sim/h8300/daa.s new file mode 100644 index 0000000..5f81eba --- /dev/null +++ b/sim/testsuite/sim/h8300/daa.s @@ -0,0 +1,36 @@ +# Hitachi H8 testcase 'daa' +# mach(): all +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + start + +daa_8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; daa Rd + daa r0l ; register operand + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + + test_h_gr8 5 r0l + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + pass + + exit 0 + diff --git a/sim/testsuite/sim/h8300/das.s b/sim/testsuite/sim/h8300/das.s new file mode 100644 index 0000000..9317f19 --- /dev/null +++ b/sim/testsuite/sim/h8300/das.s @@ -0,0 +1,36 @@ +# Hitachi H8 testcase 'das' +# mach(): all +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + start + +das_8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; das Rd + das r0l ; register operand + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + pass + + exit 0 + diff --git a/sim/testsuite/sim/h8300/dec.s b/sim/testsuite/sim/h8300/dec.s new file mode 100644 index 0000000..122f311 --- /dev/null +++ b/sim/testsuite/sim/h8300/dec.s @@ -0,0 +1,117 @@ +# Hitachi H8 testcase 'dec.b, dec.w, dec.l' +# mach(): all +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + start + +dec_b: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; dec.b Rd + dec.b r0h ; Decrement 8-bit reg by one + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0xa4a5 r0 ; dec result: a4|a5 +.if (sim_cpu) ; non-zero means h8300h, s, or sx + test_h_gr32 0xa5a5a4a5 er0 ; dec result: a5|a5|a4|a5 +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu) ; non-zero means h8300h, s, or sx +dec_w_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; dec.w #1, Rd + dec.w #1, r0 ; Decrement 16-bit reg by one + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0xa5a4 r0 ; dec result: a5|a4 + + test_h_gr32 0xa5a5a5a4 er0 ; dec result: a5|a5|a5|a4 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +dec_w_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; dec.w #2, Rd + dec.w #2, r0 ; Decrement 16-bit reg by two + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0xa5a3 r0 ; dec result: a5|a3 + + test_h_gr32 0xa5a5a5a3 er0 ; dec result: a5|a5|a5|a3 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +dec_l_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; dec.l #1, eRd + dec.l #1, er0 ; Decrement 32-bit reg by one + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + + test_h_gr32 0xa5a5a5a4 er0 ; dec result: a5|a5|a5|a4 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +dec_l_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; dec.l #2, eRd + dec.l #2, er0 ; Decrement 32-bit reg by two + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + + test_h_gr32 0xa5a5a5a3 er0 ; dec result: a5|a5|a5|a3 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif + + pass + + exit 0 diff --git a/sim/testsuite/sim/h8300/div.s b/sim/testsuite/sim/h8300/div.s new file mode 100644 index 0000000..518b62f --- /dev/null +++ b/sim/testsuite/sim/h8300/div.s @@ -0,0 +1,387 @@ +# Hitachi H8 testcase 'divs', 'divu', 'divxs', 'divxu' +# mach(): all +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + start + +.if (sim_cpu == h8sx) +divs_w_reg_reg: + set_grs_a5a5 + + ;; divs.w rs, rd + mov.w #32, r1 + mov.w #-2, r2 + set_ccr_zero + divs.w r2, r1 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_carry_clear + test_zero_clear + test_ovf_clear + + test_gr_a5a5 0 + test_h_gr16 0xfff0 r1 + test_h_gr32 0xa5a5fffe er2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +divs_w_imm4_reg: + set_grs_a5a5 + + ;; divs.w xx:4, rd + mov.w #32, r1 + set_ccr_zero + divs.w #-2:4, r1 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_carry_clear + test_zero_clear + test_ovf_clear + + test_gr_a5a5 0 + test_h_gr16 -16 r1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +divs_l_reg_reg: + set_grs_a5a5 + + ;; divs.l ers, erd + mov.l #320000, er1 + mov.l #-2, er2 + set_ccr_zero + divs.l er2, er1 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_carry_clear + test_zero_clear + test_ovf_clear + + test_gr_a5a5 0 + test_h_gr32 -160000 er1 + test_h_gr32 -2 er2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +divs_l_imm4_reg: + set_grs_a5a5 + + ;; divs.l xx:4, rd + mov.l #320000, er1 + set_ccr_zero + divs.l #-2:4, er1 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_carry_clear + test_zero_clear + test_ovf_clear + + test_gr_a5a5 0 + test_h_gr32 -160000 er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +divu_w_reg_reg: + set_grs_a5a5 + + ;; divu.w rs, rd + mov.w #32, r1 + mov.w #2, r2 + set_ccr_zero + divu.w r2, r1 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_gr_a5a5 0 + test_h_gr16 16 r1 + test_h_gr32 0xa5a50002 er2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +divu_w_imm4_reg: + set_grs_a5a5 + + ;; divu.w xx:4, rd + mov.w #32, r1 + set_ccr_zero + divu.w #2:4, r1 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_gr_a5a5 0 + test_h_gr16 16 r1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +divu_l_reg_reg: + set_grs_a5a5 + + ;; divu.l ers, erd + mov.l #320000, er1 + mov.l #2, er2 + set_ccr_zero + divu.l er2, er1 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_gr_a5a5 0 + test_h_gr32 160000 er1 + test_h_gr32 2 er2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +divu_l_imm4_reg: + set_grs_a5a5 + + ;; divu.l xx:4, rd + mov.l #320000, er1 + set_ccr_zero + divu.l #2:4, er1 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_gr_a5a5 0 + test_h_gr32 160000 er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.endif + +.if (sim_cpu) ; not equal to zero ie. not h8 +divxs_b_reg_reg: + set_grs_a5a5 + + ;; divxs.b rs, rd + mov.w #32, r1 + mov.b #-2, r2l + set_ccr_zero + divxs.b r2l, r1 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_carry_clear + test_zero_clear + test_ovf_clear + + test_gr_a5a5 0 + test_h_gr16 0x00f0 r1 + test_h_gr32 0xa5a5a5fe er2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +divxs_b_imm4_reg: + set_grs_a5a5 + + ;; divxs.b xx:4, rd + mov.w #32, r1 + set_ccr_zero + divxs.b #-2:4, r1 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_carry_clear + test_zero_clear + test_ovf_clear + + test_gr_a5a5 0 + test_h_gr16 0x00f0 r1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif ; h8sx + +divxs_w_reg_reg: + set_grs_a5a5 + + ;; divxs.w ers, erd + mov.l #0x1000, er1 + mov.w #-0x1000, r2 + set_ccr_zero + divxs.w r2, er1 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_carry_clear + test_zero_clear + test_ovf_clear + + test_gr_a5a5 0 + test_h_gr32 0x0000ffff er1 + test_h_gr32 0xa5a5f000 er2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +divxs_w_imm4_reg: + set_grs_a5a5 + + ;; divxs.w xx:4, rd + mov.l #-4, er1 + set_ccr_zero + divxs.w #2:4, er1 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_carry_clear + test_zero_clear + test_ovf_clear + + test_gr_a5a5 0 + test_h_gr32 0x0000fffe er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif ; h8sx +.endif ; not h8 + +divxu_b_reg_reg: + set_grs_a5a5 + + ;; divxu.b rs, rd + mov.w #32, r1 + mov.b #2, r2l + set_ccr_zero + divxu.b r2l, r1 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_gr_a5a5 0 + test_h_gr16 0x0010 r1 + test_h_gr16 0xa502 r2 +.if (sim_cpu) + test_h_gr32 0xa5a5a502 er2 +.endif + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu) ; not h8 +.if (sim_cpu == h8sx) +divxu_b_imm4_reg: + set_grs_a5a5 + + ;; divxu.b xx:4, rd + mov.w #32, r1 + set_ccr_zero + divxu.b #2:4, r1 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_gr_a5a5 0 + test_h_gr16 0x0010 r1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif ; h8sx + +divxu_w_reg_reg: + set_grs_a5a5 + + ;; divxu.w ers, erd + mov.l #0x1000, er1 + mov.w #0x1000, r2 + set_ccr_zero + divxu.w r2, er1 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_gr_a5a5 0 + test_h_gr32 0x00000001 er1 + test_h_gr32 0xa5a51000 er2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +divxu_w_imm4_reg: + set_grs_a5a5 + + ;; divxu.w xx:4, rd + mov.l #0xffff, er1 + set_ccr_zero + divxu.w #2:4, er1 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_gr_a5a5 0 + test_h_gr32 0x00017fff er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif ; h8sx +.endif ; not h8 + + pass + + exit 0 diff --git a/sim/testsuite/sim/h8300/extl.s b/sim/testsuite/sim/h8300/extl.s new file mode 100644 index 0000000..001f6d3 --- /dev/null +++ b/sim/testsuite/sim/h8300/extl.s @@ -0,0 +1,1146 @@ +# Hitachi H8 testcase 'exts.l, extu.l' +# mach(): h8300h h8300s h8sx +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + start + + .data + .align 4 +pos: .long 0xffff0001 +neg: .long 0x00008000 + +pos2: .long 0xffffff01 +neg2: .long 0x00000080 + + .text + +exts_l_reg32_p: + set_grs_a5a5 + set_ccr_zero + ;; exts.l ern32 + mov.w #1, r0 + exts.l er0 + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 0x00000001 er0 ; result of sign extend + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +exts_l_reg32_n: + set_grs_a5a5 + set_ccr_zero + ;; exts.l ern32 + mov.w #0xffff, r0 + exts.l er0 + + ;; Test ccr H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xffffffff er0 ; result of sign extend + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +extu_l_reg32_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.l ern32 + mov.w #0xffff, r0 + extu.l er0 + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 0x0000ffff er0 ; result of zero extend + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +exts_l_ind_p: + set_grs_a5a5 + set_ccr_zero + ;; exts.l @ern32 + mov.l #pos, er1 + exts.l @er1 + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 pos er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0x00000001, @pos + beq .Lslindp + fail +.Lslindp: + mov.l #0xffff0001, @pos ; Restore initial value + +exts_l_ind_n: + set_grs_a5a5 + set_ccr_zero + ;; exts.l @ern32 + mov.l #neg, er1 + exts.l @er1 + + ;; Test ccr H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 neg er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0xffff8000, @neg + beq .Lslindn + fail +.Lslindn: +;;; Note: leave the value as 0xffff8000, so that extu has work to do. + +extu_l_ind_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.l @ern32 + mov.l #neg, er1 + extu.l @er1 + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 neg er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0x00008000, @neg + beq .Lulindn + fail +.Lulindn: +;;; Note: leave the value as 0x00008000, so that extu has work to do. + +exts_l_postinc_p: + set_grs_a5a5 + set_ccr_zero + ;; exts.l @ern32+ + mov.l #pos, er1 + exts.l @er1+ + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 pos+4 er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0x00000001, @pos + beq .Lslpostincp + fail +.Lslpostincp: + mov.l #0xffff0001, @pos ; Restore initial value + +exts_l_postinc_n: + set_grs_a5a5 + set_ccr_zero + ;; exts.l @ern32+ + mov.l #neg, er1 + exts.l @er1+ + + ;; Test ccr H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 neg+4 er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0xffff8000, @neg + beq .Lslpostincn + fail +.Lslpostincn: +;;; Note: leave the value as 0xffff8000, so that extu has work to do. + +extu_l_postinc_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.l @ern32+ + mov.l #neg, er1 + extu.l @er1+ + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 neg+4 er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0x00008000, @neg + beq .Lulpostincn + fail +.Lulpostincn: +;;; Note: leave the value as 0x00008000, so that extu has work to do. + +exts_l_postdec_p: + set_grs_a5a5 + set_ccr_zero + ;; exts.l @ern32- + mov.l #pos, er1 + exts.l @er1- + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 pos-4 er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0x00000001, @pos + beq .Lslpostdecp + fail +.Lslpostdecp: + mov.l #0xffff0001, @pos ; Restore initial value + +exts_l_postdec_n: + set_grs_a5a5 + set_ccr_zero + ;; exts.l @ern32- + mov.l #neg, er1 + exts.l @er1- + + ;; Test ccr H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 neg-4 er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0xffff8000, @neg + beq .Lslpostdecn + fail +.Lslpostdecn: +;;; Note: leave the value as 0xffff8000, so that extu has work to do. + +extu_l_postdec_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.l @ern32- + mov.l #neg, er1 + extu.l @er1- + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 neg-4 er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0x00008000, @neg + beq .Lulpostdecn + fail +.Lulpostdecn: +;;; Note: leave the value as 0x00008000, so that extu has work to do. + +exts_l_preinc_p: + set_grs_a5a5 + set_ccr_zero + ;; exts.l @+ern32 + mov.l #pos-4, er1 + exts.l @+er1 + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 pos er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0x00000001, @pos + beq .Lslpreincp + fail +.Lslpreincp: + mov.l #0xffff0001, @pos ; Restore initial value + +exts_l_preinc_n: + set_grs_a5a5 + set_ccr_zero + ;; exts.l @+ern32 + mov.l #neg-4, er1 + exts.l @+er1 + + ;; Test ccr H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 neg er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0xffff8000, @neg + beq .Lslpreincn + fail +.Lslpreincn: +;;; Note: leave the value as 0xffff8000, so that extu has work to do. + +extu_l_preinc_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.l @+ern32 + mov.l #neg-4, er1 + extu.l @+er1 + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 neg er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0x00008000, @neg + beq .Lulpreincn + fail +.Lulpreincn: +;;; Note: leave the value as 0x00008000, so that extu has work to do. + +exts_l_predec_p: + set_grs_a5a5 + set_ccr_zero + ;; exts.l @-ern32 + mov.l #pos+4, er1 + exts.l @-er1 + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 pos er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0x00000001, @pos + beq .Lslpredecp + fail +.Lslpredecp: + mov.l #0xffff0001, @pos ; Restore initial value + +exts_l_predec_n: + set_grs_a5a5 + set_ccr_zero + ;; exts.l @-ern32 + mov.l #neg+4, er1 + exts.l @-er1 + + ;; Test ccr H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 neg er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0xffff8000, @neg + beq .Lslpredecn + fail +.Lslpredecn: +;;; Note: leave the value as 0xffff8000, so that extu has work to do. + +extu_l_predec_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.l @-ern32 + mov.l #neg+4, er1 + extu.l @-er1 + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 neg er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0x00008000, @neg + beq .Lulpredecn + fail +.Lulpredecn: +;;; Note: leave the value as 0x00008000, so that extu has work to do. + +extu_l_disp2_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.l @(dd:2, ern32) + mov.l #neg-8, er1 + extu.l @(8:2, er1) + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 neg-8 er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0x00008000, @neg + beq .Luldisp2n + fail +.Luldisp2n: +;;; Note: leave the value as 0x00008000, so that extu has work to do. + +extu_l_disp16_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.l @(dd:16, ern32) + mov.l #neg-44, er1 + extu.l @(44:16, er1) + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 neg-44 er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0x00008000, @neg + beq .Luldisp16n + fail +.Luldisp16n: +;;; Note: leave the value as 0x00008000, so that extu has work to do. + +extu_l_disp32_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.l @(dd:32, ern32) + mov.l #neg+444, er1 + extu.l @(-444:32, er1) + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 neg+444 er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0x00008000, @neg + beq .Luldisp32n + fail +.Luldisp32n: +;;; Note: leave the value as 0x00008000, so that extu has work to do. + +extu_l_abs16_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.l @aa:16 + extu.l @neg:16 + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0x00008000, @neg + beq .Lulabs16n + fail +.Lulabs16n: +;;; Note: leave the value as 0x00008000, so that extu has work to do. + +extu_l_abs32_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.l @aa:32 + extu.l @neg:32 + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0x00008000, @neg + beq .Lulabs32n + fail +.Lulabs32n: +;;; Note: leave the value as 0x00008000, so that extu has work to do. + + + + # + # exts #2, nn + # + +exts_l_reg32_2_p: + set_grs_a5a5 + set_ccr_zero + ;; exts.l #2, ern32 + mov.b #1, r0l + exts.l #2, er0 + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 0x00000001 er0 ; result of sign extend + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +exts_l_reg32_2_n: + set_grs_a5a5 + set_ccr_zero + ;; exts.l #2, ern32 + mov.b #0xff, r0l + exts.l #2, er0 + + ;; Test ccr H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_ovf_clear + test_zero_clear + test_carry_clear + + test_h_gr32 0xffffffff er0 ; result of sign extend + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +extu_l_reg32_2_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.l #2, ern32 + mov.b #0xff, r0l + extu.l #2, er0 + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 0x000000ff er0 ; result of zero extend + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +exts_l_ind_2_p: + set_grs_a5a5 + set_ccr_zero + ;; exts.l #2, @ern32 + mov.l #pos2, er1 + exts.l #2, @er1 + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 pos2 er1 ; result of sign extend + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0x00000001, @pos2 + beq .Lslindp2 + fail +.Lslindp2: + mov.l #0xffffff01, @pos2 ; Restore initial value + +exts_l_ind_2_n: + set_grs_a5a5 + set_ccr_zero + ;; exts.l #2, @ern32 + mov.l #neg2, er1 + exts.l #2, @er1 + + ;; Test ccr H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_ovf_clear + test_zero_clear + test_carry_clear + + test_h_gr32 neg2 er1 ; result of sign extend + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0xffffff80, @neg2 + beq .Lslindn2 + fail +.Lslindn2: +;;; Note: leave the value as 0xffffff80, so that extu has work to do. + +extu_l_ind_2_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.l #2, @ern32 + mov.l #neg2, er1 + extu.l #2, @er1 + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 neg2 er1 ; result of zero extend + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0x00000080, @neg2 + beq .Lulindn2 + fail +.Lulindn2: +;;; Note: leave the value as 0x00000080, like it started out. + +exts_l_postinc_2_p: + set_grs_a5a5 + set_ccr_zero + ;; exts.l #2, @ern32+ + mov.l #pos2, er1 + exts.l #2, @er1+ + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 pos2+4 er1 ; result of sign extend + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0x00000001, @pos2 + beq .Lslpostincp2 + fail +.Lslpostincp2: + mov.l #0xffffff01, @pos2 ; Restore initial value + +exts_l_postinc_2_n: + set_grs_a5a5 + set_ccr_zero + ;; exts.l #2, @ern32+ + mov.l #neg2, er1 + exts.l #2, @er1+ + + ;; Test ccr H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_ovf_clear + test_zero_clear + test_carry_clear + + test_h_gr32 neg2+4 er1 ; result of sign extend + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0xffffff80, @neg2 + beq .Lslpostincn2 + fail +.Lslpostincn2: +;;; Note: leave the value as 0xffffff80, so that extu has work to do. + +extu_l_postinc_2_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.l #2, @ern32+ + mov.l #neg2, er1 + extu.l #2, @er1+ + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 neg2+4 er1 ; result of zero extend + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0x00000080, @neg2 + beq .Lulpostincn2 + fail +.Lulpostincn2: +;;; Note: leave the value as 0x00000080, like it started out. + +exts_l_postdec_2_p: + set_grs_a5a5 + set_ccr_zero + ;; exts.l #2, @ern32- + mov.l #pos2, er1 + exts.l #2, @er1- + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 pos2-4 er1 ; result of sign extend + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0x00000001, @pos2 + beq .Lslpostdecp2 + fail +.Lslpostdecp2: + mov.l #0xffffff01, @pos2 ; Restore initial value + +exts_l_postdec_2_n: + set_grs_a5a5 + set_ccr_zero + ;; exts.l #2, @ern32- + mov.l #neg2, er1 + exts.l #2, @er1- + + ;; Test ccr H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_ovf_clear + test_zero_clear + test_carry_clear + + test_h_gr32 neg2-4 er1 ; result of sign extend + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0xffffff80, @neg2 + beq .Lslpostdecn2 + fail +.Lslpostdecn2: +;;; Note: leave the value as 0xffffff80, so that extu has work to do. + +extu_l_postdec_2_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.l #2, @ern32- + mov.l #neg2, er1 + extu.l #2, @er1- + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 neg2-4 er1 ; result of zero extend + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0x00000080, @neg2 + beq .Lulpostdecn2 + fail +.Lulpostdecn2: +;;; Note: leave the value as 0x00000080, like it started out. + +exts_l_preinc_2_p: + set_grs_a5a5 + set_ccr_zero + ;; exts.l #2, @+ern32 + mov.l #pos2-4, er1 + exts.l #2, @+er1 + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 pos2 er1 ; result of sign extend + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0x00000001, @pos2 + beq .Lslpreincp2 + fail +.Lslpreincp2: + mov.l #0xffffff01, @pos2 ; Restore initial value + +exts_l_preinc_2_n: + set_grs_a5a5 + set_ccr_zero + ;; exts.l #2, @+ern32 + mov.l #neg2-4, er1 + exts.l #2, @+er1 + + ;; Test ccr H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_ovf_clear + test_zero_clear + test_carry_clear + + test_h_gr32 neg2 er1 ; result of sign extend + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0xffffff80, @neg2 + beq .Lslpreincn2 + fail +.Lslpreincn2: +;;; Note: leave the value as 0xffffff80, so that extu has work to do. + +extu_l_preinc_2_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.l #2, @+ern32 + mov.l #neg2-4, er1 + extu.l #2, @+er1 + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 neg2 er1 ; result of zero extend + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0x00000080, @neg2 + beq .Lulpreincn2 + fail +.Lulpreincn2: +;;; Note: leave the value as 0x00000080, like it started out. + +exts_l_predec_2_p: + set_grs_a5a5 + set_ccr_zero + ;; exts.l #2, @-ern32 + mov.l #pos2+4, er1 + exts.l #2, @-er1 + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 pos2 er1 ; result of sign extend + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0x00000001, @pos2 + beq .Lslpredecp2 + fail +.Lslpredecp2: + mov.l #0xffffff01, @pos2 ; Restore initial value + +exts_l_predec_2_n: + set_grs_a5a5 + set_ccr_zero + ;; exts.l #2, @-ern32 + mov.l #neg2+4, er1 + exts.l #2, @-er1 + + ;; Test ccr H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_ovf_clear + test_zero_clear + test_carry_clear + + test_h_gr32 neg2 er1 ; result of sign extend + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0xffffff80, @neg2 + beq .Lslpredecn2 + fail +.Lslpredecn2: +;;; Note: leave the value as 0xffffff80, so that extu has work to do. + +extu_l_predec_2_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.l #2, @-ern32 + mov.l #neg2+4, er1 + extu.l #2, @-er1 + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 neg2 er1 ; result of zero extend + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0x00000080, @neg2 + beq .Lulpredecn2 + fail +.Lulpredecn2: +;;; Note: leave the value as 0x00000080, like it started out. + +extu_l_disp2_2_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.l #2, @(dd:2, ern32) + mov.l #neg2-8, er1 + extu.l #2, @(8:2, er1) + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 neg2-8 er1 ; result of zero extend + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0x00000080, @neg2 + beq .Luldisp2n2 + fail +.Luldisp2n2: +;;; Note: leave the value as 0x00000080, like it started out. + +extu_l_disp16_2_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.l #2, @(dd:16, ern32) + mov.l #neg2-44, er1 + extu.l #2, @(44:16, er1) + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 neg2-44 er1 ; result of zero extend + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0x00000080, @neg2 + beq .Luldisp16n2 + fail +.Luldisp16n2: +;;; Note: leave the value as 0x00000080, like it started out. + +extu_l_disp32_2_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.l #2, @(dd:32, ern32) + mov.l #neg2+444, er1 + extu.l #2, @(-444:32, er1) + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 neg2+444 er1 ; result of zero extend + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0x00000080, @neg2 + beq .Luldisp32n2 + fail +.Luldisp32n2: +;;; Note: leave the value as 0x00000080, like it started out. + +extu_l_abs16_2_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.l #2, @aa:16 + extu.l #2, @neg2:16 + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0x00000080, @neg2 + beq .Lulabs16n2 + fail +.Lulabs16n2: +;;; Note: leave the value as 0x00000080, like it started out. + +extu_l_abs32_2_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.l #2, @aa:32 + extu.l #2, @neg2:32 + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0x00000080, @neg2 + beq .Lulabs32n2 + fail +.Lulabs32n2: +;;; Note: leave the value as 0x00000080, like it started out. + +.endif + + pass + + exit 0 + + + + diff --git a/sim/testsuite/sim/h8300/extw.s b/sim/testsuite/sim/h8300/extw.s new file mode 100644 index 0000000..b1eb491 --- /dev/null +++ b/sim/testsuite/sim/h8300/extw.s @@ -0,0 +1,580 @@ +# Hitachi H8 testcase 'exts.w, extu.w' +# mach(): h8300h h8300s h8sx +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + start + + .data + .align 2 +pos: .word 0xff01 +neg: .word 0x0080 + + .text + +exts_w_reg16_p: + set_grs_a5a5 + set_ccr_zero + ;; exts.w rn16 + mov.b #1, r0l + exts.w r0 + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 0xa5a50001 er0 ; result of sign extend + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +exts_w_reg16_n: + set_grs_a5a5 + set_ccr_zero + ;; exts.w rn16 + mov.b #0xff, r0l + exts.w r0 + + ;; Test ccr H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a5ffff er0 ; result of sign extend + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +extu_w_reg16_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.w rn16 + mov.b #0xff, r0l + extu.w r0 + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 0xa5a500ff er0 ; result of zero extend + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +exts_w_ind_p: + set_grs_a5a5 + set_ccr_zero + ;; exts.w @ern + mov.l #pos, er1 + exts.w @er1 + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 pos er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.w #0x0001, @pos + beq .Lswindp + fail +.Lswindp: + mov.w #0xff01, @pos ; Restore initial value + +exts_w_ind_n: + set_grs_a5a5 + set_ccr_zero + ;; exts.w @ern + mov.l #neg, er1 + exts.w @er1 + + ;; Test ccr H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 neg er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.w #0xff80, @neg + beq .Lswindn + fail +.Lswindn: + ;; Note: leave the value as 0xff80, so that extu has work to do. + +extu_w_ind_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.w @ern + mov.l #neg, er1 + extu.w @er1 + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 neg er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.w #0x0080, @neg + beq .Luwindn + fail +.Luwindn: + ;; Note: leave the value as 0x0080, like it started out. + +exts_w_postinc_p: + set_grs_a5a5 + set_ccr_zero + ;; exts.w @ern+ + mov.l #pos, er1 + exts.w @er1+ + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 pos+2 er1 ; er1 still contains target address plus 2 + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.w #0x0001, @pos + beq .Lswpostincp + fail +.Lswpostincp: + mov.w #0xff01, @pos ; Restore initial value + +exts_w_postinc_n: + set_grs_a5a5 + set_ccr_zero + ;; exts.w @ern+ + mov.l #neg, er1 + exts.w @er1+ + + ;; Test ccr H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 neg+2 er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.w #0xff80, @neg + beq .Lswpostincn + fail +.Lswpostincn: + ;; Note: leave the value as 0xff80, so that extu has work to do. + +extu_w_postinc_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.w @ern+ + mov.l #neg, er1 + extu.w @er1+ + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 neg+2 er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.w #0x0080, @neg + beq .Luwpostincn + fail +.Luwpostincn: + ;; Note: leave the value as 0x0080, like it started out. + +exts_w_postdec_p: + set_grs_a5a5 + set_ccr_zero + ;; exts.w @ern- + mov.l #pos, er1 + exts.w @er1- + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 pos-2 er1 ; er1 still contains target address plus 2 + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.w #0x0001, @pos + beq .Lswpostdecp + fail +.Lswpostdecp: + mov.w #0xff01, @pos ; Restore initial value + +exts_w_postdec_n: + set_grs_a5a5 + set_ccr_zero + ;; exts.w @ern- + mov.l #neg, er1 + exts.w @er1- + + ;; Test ccr H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 neg-2 er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.w #0xff80, @neg + beq .Lswpostdecn + fail +.Lswpostdecn: + ;; Note: leave the value as 0xff80, so that extu has work to do. + +extu_w_postdec_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.w @ern- + mov.l #neg, er1 + extu.w @er1- + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 neg-2 er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.w #0x0080, @neg + beq .Luwpostdecn + fail +.Luwpostdecn: + ;; Note: leave the value as 0x0080, like it started out. + +exts_w_preinc_p: + set_grs_a5a5 + set_ccr_zero + ;; exts.w @+ern + mov.l #pos-2, er1 + exts.w @+er1 + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 pos er1 ; er1 still contains target address plus 2 + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.w #0x0001, @pos + beq .Lswpreincp + fail +.Lswpreincp: + mov.w #0xff01, @pos ; Restore initial value + +exts_w_preinc_n: + set_grs_a5a5 + set_ccr_zero + ;; exts.w @+ern + mov.l #neg-2, er1 + exts.w @+er1 + + ;; Test ccr H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 neg er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.w #0xff80, @neg + beq .Lswpreincn + fail +.Lswpreincn: + ;; Note: leave the value as 0xff80, so that extu has work to do. + +extu_w_preinc_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.w @+ern + mov.l #neg-2, er1 + extu.w @+er1 + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 neg er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.w #0x0080, @neg + beq .Luwpreincn + fail +.Luwpreincn: + ;; Note: leave the value as 0x0080, like it started out. + +exts_w_predec_p: + set_grs_a5a5 + set_ccr_zero + ;; exts.w @-ern + mov.l #pos+2, er1 + exts.w @-er1 + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 pos er1 ; er1 still contains target address plus 2 + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.w #0x0001, @pos + beq .Lswpredecp + fail +.Lswpredecp: + mov.w #0xff01, @pos ; Restore initial value + +exts_w_predec_n: + set_grs_a5a5 + set_ccr_zero + ;; exts.w @-ern + mov.l #neg+2, er1 + exts.w @-er1 + + ;; Test ccr H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 neg er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.w #0xff80, @neg + beq .Lswpredecn + fail +.Lswpredecn: + ;; Note: leave the value as 0xff80, so that extu has work to do. + +extu_w_predec_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.w @-ern + mov.l #neg+2, er1 + extu.w @-er1 + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 neg er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.w #0x0080, @neg + beq .Luwpredecn + fail +.Luwpredecn: + ;; Note: leave the value as 0x0080, like it started out. + +extu_w_disp2_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.w @(dd:2, ern) + mov.l #neg-2, er1 + extu.w @(2:2, er1) + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 neg-2 er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.w #0x0080, @neg + beq .Luwdisp2n + fail +.Luwdisp2n: + ;; Note: leave the value as 0x0080, like it started out. + +extu_w_disp16_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.w @(dd:16, ern) + mov.l #neg-44, er1 + extu.w @(44:16, er1) + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 neg-44 er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.w #0x0080, @neg + beq .Luwdisp16n + fail +.Luwdisp16n: + ;; Note: leave the value as 0x0080, like it started out. + +extu_w_disp32_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.w @(dd:32, ern) + mov.l #neg+444, er1 + extu.w @(-444:32, er1) + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 neg+444 er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.w #0x0080, @neg + beq .Luwdisp32n + fail +.Luwdisp32n: + ;; Note: leave the value as 0x0080, like it started out. + +extu_w_abs16_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.w @aa:16 + extu.w @neg:16 + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.w #0x0080, @neg + beq .Luwabs16n + fail +.Luwabs16n: + ;; Note: leave the value as 0x0080, like it started out. + +extu_w_abs32_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.w @aa:32 + extu.w @neg:32 + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.w #0x0080, @neg + beq .Luwabs32n + fail +.Luwabs32n: + ;; Note: leave the value as 0x0080, like it started out. + +.endif + + pass + + exit 0 diff --git a/sim/testsuite/sim/h8300/inc.s b/sim/testsuite/sim/h8300/inc.s new file mode 100644 index 0000000..69d2c3b --- /dev/null +++ b/sim/testsuite/sim/h8300/inc.s @@ -0,0 +1,117 @@ +# Hitachi H8 testcase 'inc, inc.w, inc.l' +# mach(): all +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + start + +inc_b: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; inc.b Rd + inc.b r0h ; Increment 8-bit reg by one + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0xa6a5 r0 ; inc result: a6|a5 +.if (sim_cpu) ; non-zero means h8300h, s, or sx + test_h_gr32 0xa5a5a6a5 er0 ; inc result: a5|a5|a6|a5 +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu) ; non-zero means h8300h, s, or sx +inc_w_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; inc.w #1, Rd + inc.w #1, r0 ; Increment 16-bit reg by one + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0xa5a6 r0 ; inc result: a5|a6 + + test_h_gr32 0xa5a5a5a6 er0 ; inc result: a5|a5|a5|a6 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +inc_w_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; inc.w #2, Rd + inc.w #2, r0 ; Increment 16-bit reg by two + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0xa5a7 r0 ; inc result: a5|a7 + + test_h_gr32 0xa5a5a5a7 er0 ; inc result: a5|a5|a5|a7 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +inc_l_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; inc.l #1, eRd + inc.l #1, er0 ; Increment 32-bit reg by one + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + + test_h_gr32 0xa5a5a5a6 er0 ; inc result: a5|a5|a5|a6 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +inc_l_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; inc.l #2, eRd + inc.l #2, er0 ; Increment 32-bit reg by two + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + + test_h_gr32 0xa5a5a5a7 er0 ; inc result: a5|a5|a5|a7 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif + + pass + + exit 0 diff --git a/sim/testsuite/sim/h8300/jmp.s b/sim/testsuite/sim/h8300/jmp.s new file mode 100644 index 0000000..30a4b28 --- /dev/null +++ b/sim/testsuite/sim/h8300/jmp.s @@ -0,0 +1,123 @@ +# Hitachi H8 testcase 'jmp' +# mach(): all +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + .data +vector_area: + .fill 0x400, 1, 0 + + start + +.if (sim_cpu == h8sx) +jmp_8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov.l #.Ltgt_8:32, @0x20 + set_ccr_zero + ;; jmp @@aa:8 ; 8-bit displacement + jmp @@0x20 + fail + +.Ltgt_8: + test_cc_clear + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +jmp_7: ; vector jump + mov.l #vector_area, er0 + ldc.l er0, vbr + set_grs_a5a5 + mov.l #.Ltgt_7:32, @vector_area+0x300 + set_ccr_zero + + jmp @@0x300 + fail +.Ltgt_7: + test_cc_clear + test_grs_a5a5 + stc.l vbr, er0 + test_h_gr32 vector_area, er0 + +.endif ; h8sx + +jmp_24: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; jmp @aa:24 ; 24-bit address + jmp @.Ltgt_24:24 + fail + +.Ltgt_24: + test_cc_clear + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu) ; Non-zero means h8300h, h8300s, or h8sx +jmp_reg: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; jmp @ern ; register indirect + mov.l #.Ltgt_reg, er5 + jmp @er5 + fail + +.Ltgt_reg: + test_cc_clear + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_h_gr32 .Ltgt_reg er5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif ; not h8300 + +.if (sim_cpu == h8sx) +jmp_32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; jmp @aa:32 ; 32-bit address +; jmp @.Ltgt_32:32 ; NOTE: hard-coded to avoid relaxing + .word 0x5908 + .long .Ltgt_32 + fail + +.Ltgt_32: + test_cc_clear + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif ; h8sx + + pass + exit 0 + + \ No newline at end of file diff --git a/sim/testsuite/sim/h8300/ldc.s b/sim/testsuite/sim/h8300/ldc.s new file mode 100644 index 0000000..3712a6c --- /dev/null +++ b/sim/testsuite/sim/h8300/ldc.s @@ -0,0 +1,375 @@ +# Hitachi H8 testcase 'ldc' +# mach(): all +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + .data +byte_pre: + .byte 0 +byte_src: + .byte 0xff +byte_post: + .byte 0 + + start + +ldc_imm8_ccr: + set_grs_a5a5 + set_ccr_zero + + ldc #0xff, ccr ; set all ccr flags high, immediate operand + bcs .L1 ; carry flag set? + fail +.L1: bvs .L2 ; overflow flag set? + fail +.L2: beq .L3 ; zero flag set? + fail +.L3: bmi .L4 ; neg flag set? + fail +.L4: + ldc #0, ccr ; set all ccr flags low, immediate operand + bcc .L5 ; carry flag clear? + fail +.L5: bvc .L6 ; overflow flag clear? + fail +.L6: bne .L7 ; zero flag clear? + fail +.L7: bpl .L8 ; neg flag clear? + fail +.L8: + test_cc_clear + test_grs_a5a5 + +ldc_reg8_ccr: + set_grs_a5a5 + set_ccr_zero + + mov #0xff, r0h + ldc r0h, ccr ; set all ccr flags high, reg operand + bcs .L11 ; carry flag set? + fail +.L11: bvs .L12 ; overflow flag set? + fail +.L12: beq .L13 ; zero flag set? + fail +.L13: bmi .L14 ; neg flag set? + fail +.L14: + mov #0, r0h + ldc r0h, ccr ; set all ccr flags low, reg operand + bcc .L15 ; carry flag clear? + fail +.L15: bvc .L16 ; overflow flag clear? + fail +.L16: bne .L17 ; zero flag clear? + fail +.L17: bpl .L18 ; neg flag clear? + fail +.L18: + test_cc_clear + test_h_gr16 0x00a5 r0 ; Register 0 modified by test procedure. + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8300s || sim_cpu == h8sx) ; Earlier versions, no exr +ldc_imm8_exr: + set_grs_a5a5 + set_ccr_zero + + ldc #0, exr + ldc #0x87, exr ; set exr to 0x87 + + stc exr, r0l ; retrieve and check exr value + cmp.b #0x87, r0l + beq .L19 + fail +.L19: + test_h_gr16 0xa587 r0 ; Register 0 modified by test procedure. + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +ldc_reg8_exr: + set_grs_a5a5 + set_ccr_zero + + ldc #0, exr + mov #0x87, r0h + ldc r0h, exr ; set exr to 0x87 + + stc exr, r0l ; retrieve and check exr value + cmp.b #0x87, r0l + beq .L21 + fail +.L21: + test_h_gr16 0x8787 r0 ; Register 0 modified by test procedure. + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +ldc_abs16_ccr: + set_grs_a5a5 + set_ccr_zero + + ldc @byte_src:16, ccr ; abs16 src + stc ccr, r0l ; copy into general reg + + test_h_gr32 0xa5a5a5ff er0 ; ff in r0l, a5 elsewhere. + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +ldc_abs16_exr: + set_grs_a5a5 + set_ccr_zero + + ldc #0, exr + ldc @byte_src:16, exr ; abs16 src + stc exr, r0l ; copy into general reg + + test_h_gr32 0xa5a5a587 er0 ; 87 in r0l, a5 elsewhere. + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +ldc_abs32_ccr: + set_grs_a5a5 + set_ccr_zero + + ldc @byte_src:32, ccr ; abs32 src + stc ccr, r0l ; copy into general reg + + test_h_gr32 0xa5a5a5ff er0 ; ff in r0l, a5 elsewhere. + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +ldc_abs32_exr: + set_grs_a5a5 + set_ccr_zero + + ldc #0, exr + ldc @byte_src:32, exr ; abs32 src + stc exr, r0l ; copy into general reg + + test_h_gr32 0xa5a5a587 er0 ; 87 in r0l, a5 elsewhere. + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +ldc_disp16_ccr: + set_grs_a5a5 + set_ccr_zero + + mov #byte_pre, er1 + ldc @(1:16, er1), ccr ; disp16 src + stc ccr, r0l ; copy into general reg + + test_h_gr32 0xa5a5a5ff er0 ; ff in r0l, a5 elsewhere. + test_h_gr32 byte_pre, er1 ; er1 still contains address + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +ldc_disp16_exr: + set_grs_a5a5 + set_ccr_zero + + ldc #0, exr + mov #byte_post, er1 + ldc @(-1:16, er1), exr ; disp16 src + stc exr, r0l ; copy into general reg + + test_h_gr32 0xa5a5a587 er0 ; 87 in r0l, a5 elsewhere. + test_h_gr32 byte_post, er1 ; er1 still contains address + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +ldc_disp32_ccr: + set_grs_a5a5 + set_ccr_zero + + mov #byte_pre, er1 + ldc @(1:32, er1), ccr ; disp32 src + stc ccr, r0l ; copy into general reg + + test_h_gr32 0xa5a5a5ff er0 ; ff in r0l, a5 elsewhere. + test_h_gr32 byte_pre, er1 ; er1 still contains address + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +ldc_disp32_exr: + set_grs_a5a5 + set_ccr_zero + + ldc #0, exr + mov #byte_post, er1 + ldc @(-1:32, er1), exr ; disp16 src + stc exr, r0l ; copy into general reg + + test_h_gr32 0xa5a5a587 er0 ; 87 in r0l, a5 elsewhere. + test_h_gr32 byte_post, er1 ; er1 still contains address + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +ldc_postinc_ccr: + set_grs_a5a5 + set_ccr_zero + + mov #byte_src, er1 + ldc @er1+, ccr ; postinc src + stc ccr, r0l ; copy into general reg + + test_h_gr32 0xa5a5a5ff er0 ; ff in r0l, a5 elsewhere. + test_h_gr32 byte_src+2, er1 ; er1 still contains address + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +ldc_postinc_exr: + set_grs_a5a5 + set_ccr_zero + + ldc #0, exr + mov #byte_src, er1 + ldc @er1+, exr ; postinc src + stc exr, r0l ; copy into general reg + + test_h_gr32 0xa5a5a587 er0 ; 87 in r0l, a5 elsewhere. + test_h_gr32 byte_src+2, er1 ; er1 still contains address + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +ldc_ind_ccr: + set_grs_a5a5 + set_ccr_zero + + mov #byte_src, er1 + ldc @er1, ccr ; postinc src + stc ccr, r0l ; copy into general reg + + test_h_gr32 0xa5a5a5ff er0 ; ff in r0l, a5 elsewhere. + test_h_gr32 byte_src, er1 ; er1 still contains address + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +ldc_ind_exr: + set_grs_a5a5 + set_ccr_zero + + ldc #0, exr + mov #byte_src, er1 + ldc @er1, exr ; postinc src + stc exr, r0l ; copy into general reg + + test_h_gr32 0xa5a5a587 er0 ; 87 in r0l, a5 elsewhere. + test_h_gr32 byte_src, er1 ; er1 still contains address + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.endif + +.if (sim_cpu == h8sx) ; New vbr and sbr registers for h8sx +ldc_reg_sbr: + set_grs_a5a5 + set_ccr_zero + + mov #0xaaaaaaaa, er0 + ldc er0, sbr ; set sbr to 0xaaaaaaaa + stc sbr, er1 ; retreive and check sbr value + + test_h_gr32 0xaaaaaaaa er1 + test_h_gr32 0xaaaaaaaa er0 ; Register 0 modified by test procedure. + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +ldc_reg_vbr: + set_grs_a5a5 + set_ccr_zero + + mov #0xaaaaaaaa, er0 + ldc er0, vbr ; set sbr to 0xaaaaaaaa + stc vbr, er1 ; retreive and check sbr value + + test_h_gr32 0xaaaaaaaa er1 + test_h_gr32 0xaaaaaaaa er0 ; Register 0 modified by test procedure. + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.endif + pass + + exit 0 diff --git a/sim/testsuite/sim/h8300/ldm.s b/sim/testsuite/sim/h8300/ldm.s new file mode 100644 index 0000000..c816221 --- /dev/null +++ b/sim/testsuite/sim/h8300/ldm.s @@ -0,0 +1,233 @@ +# Hitachi H8 testcase 'ldm', 'stm' +# mach(): all +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + .data + .align 4 +_stack: .long 0,1,2,3,4,5,6,7,8,9,0,0,0,0,0,0 + .long 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 + .long 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 + .long 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 +_stack_top: + + start + +.if (sim_cpu == h8300s || sim_cpu == h8sx) ; Earlier versions, no exr +stm_2reg: + set_grs_a5a5 + mov #_stack_top, er7 + mov #2, er2 + mov #3, er3 + + set_ccr_zero + stm er2-er3, @-sp + test_cc_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 1 + test_h_gr32 2 er2 + test_h_gr32 3 er3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_h_gr32 _stack_top-8, er7 + + mov @_stack_top-4, er0 + cmp #2, er0 + bne fail1 + + mov @_stack_top-8, er0 + cmp #3, er0 + bne fail1 + + mov @_stack_top-12, er0 + cmp #0, er0 + bne fail1 + +stm_3reg: + set_grs_a5a5 + mov #_stack_top, er7 + mov #4, er4 + mov #5, er5 + mov #6, er6 + + set_ccr_zero + stm er4-er6, @-sp + test_cc_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_h_gr32 4 er4 + test_h_gr32 5 er5 + test_h_gr32 6 er6 + test_h_gr32 _stack_top-12, er7 + + mov @_stack_top-4, er0 + cmp #4, er0 + bne fail1 + + mov @_stack_top-8, er0 + cmp #5, er0 + bne fail1 + + mov @_stack_top-12, er0 + cmp #6, er0 + bne fail1 + + mov @_stack_top-16, er0 + cmp #0, er0 + bne fail1 + +stm_4reg: + set_grs_a5a5 + mov #_stack_top, er7 + mov #1, er0 + mov #2, er1 + mov #3, er2 + mov #4, er3 + + set_ccr_zero + stm er0-er3, @-sp + test_cc_clear + + test_h_gr32 1 er0 + test_h_gr32 2 er1 + test_h_gr32 3 er2 + test_h_gr32 4 er3 + test_gr_a5a5 4 ; Make sure other general regs not disturbed + test_gr_a5a5 5 + test_gr_a5a5 6 + test_h_gr32 _stack_top-16, er7 + + mov @_stack_top-4, er0 + cmp #1, er0 + bne fail1 + + mov @_stack_top-8, er0 + cmp #2, er0 + bne fail1 + + mov @_stack_top-12, er0 + cmp #3, er0 + bne fail1 + + mov @_stack_top-16, er0 + cmp #4, er0 + bne fail1 + + mov @_stack_top-20, er0 + cmp #0, er0 + bne fail1 + +ldm_2reg: + set_grs_a5a5 + mov #_stack, er7 + + set_ccr_zero + ldm @sp+, er2-er3 + test_cc_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 1 + test_h_gr32 1 er2 + test_h_gr32 0 er3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_h_gr32 _stack+8, er7 + +ldm_3reg: + set_grs_a5a5 + mov #_stack+4, er7 + + set_ccr_zero + ldm @sp+, er4-er6 + test_cc_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_h_gr32 3 er4 + test_h_gr32 2 er5 + test_h_gr32 1 er6 + test_h_gr32 _stack+16, er7 + +ldm_4reg: + set_grs_a5a5 + mov #_stack+4, er7 + + set_ccr_zero + ldm @sp+, er0-er3 + test_cc_clear + + test_h_gr32 4 er0 + test_h_gr32 3 er1 + test_h_gr32 2 er2 + test_h_gr32 1 er3 + test_gr_a5a5 4 ; Make sure other general regs not disturbed + test_gr_a5a5 5 + test_gr_a5a5 6 + test_h_gr32 _stack+20, er7 +.endif + +pushpop: + set_grs_a5a5 +.if (sim_cpu == h8300) + mov #_stack_top, r7 + mov #12, r1 + mov #34, r2 + mov #56, r3 + push r1 + push r2 + push r3 + pop r4 + pop r5 + pop r6 + + test_gr_a5a5 0 ; Make sure other general _reg_ not disturbed + test_h_gr16 12 r1 + test_h_gr16 34 r2 + test_h_gr16 56 r3 + test_h_gr16 56 r4 + test_h_gr16 34 r5 + test_h_gr16 12 r6 + mov #_stack_top, r0 + cmp.w r0, r7 + bne fail1 +.else + mov #_stack_top, er7 + mov #12, er1 + mov #34, er2 + mov #56, er3 + push er1 + push er2 + push er3 + pop er4 + pop er5 + pop er6 + + test_gr_a5a5 0 ; Make sure other general _reg_ not disturbed + test_h_gr32 12 er1 + test_h_gr32 34 er2 + test_h_gr32 56 er3 + test_h_gr32 56 er4 + test_h_gr32 34 er5 + test_h_gr32 12 er6 + test_h_gr32 _stack_top, er7 +.endif + + pass + + exit 0 + +fail1: fail diff --git a/sim/testsuite/sim/h8300/mac.s b/sim/testsuite/sim/h8300/mac.s new file mode 100644 index 0000000..d60fe30 --- /dev/null +++ b/sim/testsuite/sim/h8300/mac.s @@ -0,0 +1,263 @@ +# Hitachi H8 testcase 'mac' +# mach(): h8300s h8sx +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + .data +src1: .word 0 +src2: .word 0 + +array: .word 0x7fff + .word 0x7fff + .word 0x7fff + .word 0x7fff + .word 0x7fff + .word 0x7fff + .word 0x7fff + .word 0x7fff + .word 0x7fff + .word 0x7fff + .word 0x7fff + .word 0x7fff + .word 0x7fff + .word 0x7fff + .word 0x7fff + .word 0x7fff + + start + +.if (sim_cpu) +_clrmac: + set_grs_a5a5 + set_ccr_zero + clrmac + test_cc_clear + test_grs_a5a5 + ;; Now see if the mac is actually clear... + stmac mach, er0 + test_zero_set + test_neg_clear + test_ovf_clear + test_h_gr32 0 er0 + stmac macl, er1 + test_zero_set + test_neg_clear + test_ovf_clear + test_h_gr32 0 er1 + +ld_stmac: + set_grs_a5a5 + sub.l er2, er2 + set_ccr_zero + ldmac er1, macl + stmac macl, er2 + test_ovf_clear + test_carry_clear + ;; neg and zero are undefined + test_h_gr32 0xa5a5a5a5 er2 + + sub.l er2, er2 + set_ccr_zero + ldmac er1, mach + stmac mach, er2 + test_ovf_clear + test_carry_clear + ;; neg and zero are undefined + test_h_gr32 0x0001a5 er2 + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +mac_2x2: + set_grs_a5a5 + mov.w #2, r1 + mov.w r1, @src1 + mov.w #2, r2 + mov.w r2, @src2 + mov #src1, er1 + mov #src2, er2 + set_ccr_zero + clrmac + mac @er1+, @er2+ + test_cc_clear + + test_h_gr32 0xa5a5a5a5 er0 + test_h_gr32 src1+2 er1 + test_h_gr32 src2+2 er2 + test_h_gr32 0xa5a5a5a5 er3 + test_h_gr32 0xa5a5a5a5 er4 + test_h_gr32 0xa5a5a5a5 er5 + test_h_gr32 0xa5a5a5a5 er6 + test_h_gr32 0xa5a5a5a5 er7 + + stmac macl, er0 + test_zero_clear + test_neg_clear + test_ovf_clear + test_h_gr32 4 er0 + + stmac mach, er0 + test_zero_clear + test_neg_clear + test_ovf_clear + test_h_gr32 0 er0 + +mac_same_reg_2x4: + ;; Use same reg for src and dst. Should be incremented twice, + ;; and fetch values from consecutive locations. + set_grs_a5a5 + mov.w #2, r1 + mov.w r1, @src1 + mov.w #4, r2 + mov.w r2, @src2 + mov #src1, er1 + + set_ccr_zero + clrmac + mac @er1+, @er1+ ; same register for src and dst + test_cc_clear + + test_h_gr32 0xa5a5a5a5 er0 + test_h_gr32 src1+4 er1 + test_h_gr32 0xa5a50004 er2 + test_h_gr32 0xa5a5a5a5 er3 + test_h_gr32 0xa5a5a5a5 er4 + test_h_gr32 0xa5a5a5a5 er5 + test_h_gr32 0xa5a5a5a5 er6 + test_h_gr32 0xa5a5a5a5 er7 + + stmac macl, er0 + test_zero_clear + test_neg_clear + test_ovf_clear + test_h_gr32 8 er0 + + stmac mach, er0 + test_zero_clear + test_neg_clear + test_ovf_clear + test_h_gr32 0 er0 + +mac_0x0: + set_grs_a5a5 + mov.w #0, r1 + mov.w r1, @src1 + mov.w #0, r2 + mov.w r2, @src2 + mov #src1, er1 + mov #src2, er2 + set_ccr_zero + clrmac + mac @er1+, @er2+ + test_cc_clear + + test_h_gr32 0xa5a5a5a5 er0 + test_h_gr32 src1+2 er1 + test_h_gr32 src2+2 er2 + test_h_gr32 0xa5a5a5a5 er3 + test_h_gr32 0xa5a5a5a5 er4 + test_h_gr32 0xa5a5a5a5 er5 + test_h_gr32 0xa5a5a5a5 er6 + test_h_gr32 0xa5a5a5a5 er7 + + stmac macl, er0 + test_zero_set ; zero flag is set + test_neg_clear + test_ovf_clear + test_h_gr32 0 er0 ; result is zero + + stmac mach, er0 + test_zero_set + test_neg_clear + test_ovf_clear + test_h_gr32 0 er0 + +mac_neg2x2: + set_grs_a5a5 + mov.w #-2, r1 + mov.w r1, @src1 + mov.w #2, r2 + mov.w r2, @src2 + mov #src1, er1 + mov #src2, er2 + set_ccr_zero + clrmac + mac @er1+, @er2+ + test_cc_clear + + test_h_gr32 0xa5a5a5a5 er0 + test_h_gr32 src1+2 er1 + test_h_gr32 src2+2 er2 + test_h_gr32 0xa5a5a5a5 er3 + test_h_gr32 0xa5a5a5a5 er4 + test_h_gr32 0xa5a5a5a5 er5 + test_h_gr32 0xa5a5a5a5 er6 + test_h_gr32 0xa5a5a5a5 er7 + + stmac macl, er0 + test_zero_clear + test_neg_set ; neg flag is set + test_ovf_clear + test_h_gr32 -4 er0 ; result is negative + + stmac mach, er0 + test_zero_clear + test_neg_set + test_ovf_clear + test_h_gr32 -1 er0 ; negative sign extend + +mac_array: + ;; Use same reg for src and dst, pointing to an array of shorts + set_grs_a5a5 + mov #array, er1 + + set_ccr_zero + clrmac + mac @er1+, @er1+ ; same register for src and dst + mac @er1+, @er1+ ; repeat 8 times + mac @er1+, @er1+ + mac @er1+, @er1+ + mac @er1+, @er1+ + mac @er1+, @er1+ + mac @er1+, @er1+ + mac @er1+, @er1+ + test_cc_clear + + test_h_gr32 0xa5a5a5a5 er0 + test_h_gr32 array+32 er1 + test_h_gr32 0xa5a5a5a5 er2 + test_h_gr32 0xa5a5a5a5 er3 + test_h_gr32 0xa5a5a5a5 er4 + test_h_gr32 0xa5a5a5a5 er5 + test_h_gr32 0xa5a5a5a5 er6 + test_h_gr32 0xa5a5a5a5 er7 + + stmac macl, er0 + test_zero_clear + test_neg_clear + test_ovf_clear + test_h_gr32 0xfff80008 er0 + + stmac mach, er0 + test_zero_clear + test_neg_clear + test_ovf_clear + test_h_gr32 1 er0 ; result is greater than 32 bits + +.endif + + pass + + exit 0 diff --git a/sim/testsuite/sim/h8300/mova.s b/sim/testsuite/sim/h8300/mova.s new file mode 100644 index 0000000..a4bcfd6 --- /dev/null +++ b/sim/testsuite/sim/h8300/mova.s @@ -0,0 +1,838 @@ +# Hitachi H8 testcase 'mova' +# mach(): h8sx +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + .data +foo: .long 0x01010101 + .long 0x10101010 + .long 0x11111111 + + start + +movabl16_reg8: + set_grs_a5a5 + set_ccr_zero + + mova/b.l @(1:16, r2l.b), er3 + + test_cc_clear + test_gr_a5a5 0 ; Make sure other regs not affected + test_gr_a5a5 1 + test_gr_a5a5 2 + test_h_gr32 0xa6 er3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +movabl16_reg16: + set_grs_a5a5 + set_ccr_zero + + mova/b.l @(1:16, r2.w), er3 + + test_cc_clear + test_gr_a5a5 0 ; Make sure other regs not affected + test_gr_a5a5 1 + test_gr_a5a5 2 + test_h_gr32 0xa5a6 er3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +movabl32_reg8: + set_grs_a5a5 + set_ccr_zero + + mova/b.l @(1:32, r2l.b), er3 + + test_cc_clear + test_gr_a5a5 0 ; Make sure other regs not affected + test_gr_a5a5 1 + test_gr_a5a5 2 + test_h_gr32 0xa6 er3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +movabl32_reg16: + set_grs_a5a5 + set_ccr_zero + + mova/b.l @(1:32, r2.w), er3 + + test_cc_clear + test_gr_a5a5 0 ; Make sure other regs not affected + test_gr_a5a5 1 + test_gr_a5a5 2 + test_h_gr32 0xa5a6 er3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +movawl16_reg8: + set_grs_a5a5 + set_ccr_zero + + mova/w.l @(1:16, r2l.b), er3 + + test_cc_clear + test_gr_a5a5 0 ; Make sure other regs not affected + test_gr_a5a5 1 + test_gr_a5a5 2 + test_h_gr32 0x14b er3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +movawl16_reg16: + set_grs_a5a5 + set_ccr_zero + + mova/w.l @(1:16, r2.w), er3 + + test_cc_clear + test_gr_a5a5 0 ; Make sure other regs not affected + test_gr_a5a5 1 + test_gr_a5a5 2 + test_h_gr32 0x14b4b er3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +movawl32_reg8: + set_grs_a5a5 + set_ccr_zero + + mova/w.l @(1:32, r2l.b), er3 + + test_cc_clear + test_gr_a5a5 0 ; Make sure other regs not affected + test_gr_a5a5 1 + test_gr_a5a5 2 + test_h_gr32 0x14b er3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +movawl32_reg16: + set_grs_a5a5 + set_ccr_zero + + mova/w.l @(1:32, r2.w), er3 + + test_cc_clear + test_gr_a5a5 0 ; Make sure other regs not affected + test_gr_a5a5 1 + test_gr_a5a5 2 + test_h_gr32 0x14b4b er3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +movall16_reg8: + set_grs_a5a5 + set_ccr_zero + + mova/l.l @(1:16, r2l.b), er3 + + test_cc_clear + test_gr_a5a5 0 ; Make sure other regs not affected + test_gr_a5a5 1 + test_gr_a5a5 2 + test_h_gr32 0x295 er3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +movall16_reg16: + set_grs_a5a5 + set_ccr_zero + + mova/l.l @(1:16, r2.w), er3 + + test_cc_clear + test_gr_a5a5 0 ; Make sure other regs not affected + test_gr_a5a5 1 + test_gr_a5a5 2 + test_h_gr32 0x29695 er3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +movall32_reg8: + set_grs_a5a5 + set_ccr_zero + + mova/l.l @(1:32, r2l.b), er3 + + test_cc_clear + test_gr_a5a5 0 ; Make sure other regs not affected + test_gr_a5a5 1 + test_gr_a5a5 2 + test_h_gr32 0x295 er3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +movall32_reg16: + set_grs_a5a5 + set_ccr_zero + + mova/l.l @(1:32, r2.w), er3 + + test_cc_clear + test_gr_a5a5 0 ; Make sure other regs not affected + test_gr_a5a5 1 + test_gr_a5a5 2 + test_h_gr32 0x29695 er3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +t02_mova: + set_grs_a5a5 + set_ccr_zero + + mov.l #0x01010101, er1 + mova/b.c @(0x1234:16,r1l.b),er1 ; 7A891234 + test_h_gr32 0x1235, er1 ; 1s + mov.l #0x01010101, er1 + mova/b.c @(0x1234:16,r1.w),er1 ; 7A991234 + test_h_gr32 0x1335, er1 ; 2s + mov.l #0x01010101, er1 + mova/w.c @(0x1234:16,r1l.b),er1 ; 7AA91234 + test_h_gr32 0x1236, er1 ; 3s + mov.l #0x01010101, er1 + mova/w.c @(0x1234:16,r1.w),er1 ; 7AB91234 + test_h_gr32 0x1436, er1 ; 4s + mov.l #0x01010101, er1 + mova/l.c @(0x1234:16,r1l.b),er1 ; 7AC91234 + test_h_gr32 0x1238, er1 ; 5s + mov.l #0x01010101, er1 + mova/l.c @(0x1234:16,r1.w),er1 ; 7AD91234 + test_h_gr32 0x1638, er1 ; 6s + mov.l #0x01010101, er1 + mova/b.c @(0x12345678:32,r1l.b),er1 ; 7A8112345678 + test_h_gr32 0x12345679, er1 ; 7s + mov.l #0x01010101, er1 + mova/b.c @(0x12345678:32,r1.w),er1 ; 7A9112345678 + test_h_gr32 0x12345779, er1 ; 8s + mov.l #0x01010101, er1 + mova/w.c @(0x12345678:32,r1l.b),er1 ; 7AA112345678 + test_h_gr32 0x1234567a, er1 ; 9s + mov.l #0x01010101, er1 + mova/w.c @(0x12345678:32,r1.w),er1 ; 7AB112345678 + test_h_gr32 0x1234587a, er1 ; 10s + mov.l #0x01010101, er1 + mova/l.c @(0x12345678:32,r1l.b),er1 ; 7AC112345678 + test_h_gr32 0x1234567c, er1 ; 11s + mov.l #0x01010101, er1 + mova/l.c @(0x12345678:32,r1.w),er1 ; 7AD112345678 + test_h_gr32 0x12345a7c, er1 ; 12s + +t02b: + mov.l #0x01010101, er3 + mova/b.l @(0x1234:16,r3l.b),er1 ; 78B87A891234 + test_h_gr32 0x1235, er1 ; 1 + mova/b.l @(0x1234:16,r3.w),er1 ; 78397A991234 + test_h_gr32 0x1335, er1 ; 2 + mova/w.l @(0x1234:16,r3l.b),er1 ; 78B87AA91234 + test_h_gr32 0x1236, er1 ; 3 + mova/w.l @(0x1234:16,r3.w),er1 ; 78397AB91234 + test_h_gr32 0x1436, er1 ; 4 + mova/l.l @(0x1234:16,r3l.b),er1 ; 78B87AC91234 + test_h_gr32 0x1238, er1 ; 5 + mova/l.l @(0x1234:16,r3.w),er1 ; 78397AD91234 + test_h_gr32 0x1638, er1 ; 6 + mova/b.l @(0x12345678:32,r3l.b),er1 ; 78B87A8112345678 + test_h_gr32 0x12345679, er1 ; 7 + mova/b.l @(0x12345678:32,r3.w),er1 ; 78397A9112345678 + test_h_gr32 0x12345779, er1 ; 8 + mova/w.l @(0x12345678:32,r3l.b),er1 ; 78B87AA112345678 + test_h_gr32 0x1234567a, er1 ; 9 + mova/w.l @(0x12345678:32,r3.w),er1 ; 78397AB112345678 + test_h_gr32 0x1234587a, er1 ; 10 + mova/l.l @(0x12345678:32,r3l.b),er1 ; 78B87AC112345678 + test_h_gr32 0x1234567c, er1 ; 11 + mova/l.l @(0x12345678:32,r3.w),er1 ; 78397AD112345678 + test_h_gr32 0x12345a7c, er1 ; 12 + test_h_gr32 0x01010101, er3 +t02c: + mov.l #foo, er2 + mova/b.l @(0x1234:16,@er2.b),er1 ;017F02811234 + test_h_gr32 0x1235, er1 ; 13 + test_h_gr32 foo, er2 + mova/b.l @(0x1234:16,@(0x1:2,er2).b),er1 ;017F12811234 + test_h_gr32 0x1235, er1 ; 18 + test_h_gr32 foo, er2 + mova/b.l @(0x1234:16,@er2+.b),er1 ;017F82811234 + test_h_gr32 0x1235, er1 ; 14 + test_h_gr32 foo+1, er2 + mova/b.l @(0x1234:16,@-er2.b),er1 ;017FB2811234 + test_h_gr32 0x1235, er1 ; 17 + test_h_gr32 foo, er2 + mova/b.l @(0x1234:16,@+er2.b),er1 ;017F92811234 + test_h_gr32 0x1235, er1 ; 16 + test_h_gr32 foo+1, er2 + mova/b.l @(0x1234:16,@er2-.b),er1 ;017FA2811234 + test_h_gr32 0x1235, er1 ; 15 + test_h_gr32 foo, er2 +t02d: + mov.l #4, er2 + mova/b.l @(0x1234:16, @(foo:16, er2).b), er1 + test_h_gr32 0x1244, er1 ; 19 + mova/b.l @(0x1234:16, @(foo:16, r2L.b).b), er1 + test_h_gr32 0x1244, er1 ; 21 + mova/b.l @(0x1234:16, @(foo:16, r2.w).b), er1 + test_h_gr32 0x1244, er1 ; 22 + mova/b.l @(0x1234:16, @(foo:16, er2.l).b), er1 + test_h_gr32 0x1244, er1 ; 23 + + mov.l #4, er2 + mova/b.l @(0x1234:16, @(foo:32, er2).b), er1 + test_h_gr32 0x1244, er1 ; 20 + mova/b.l @(0x1234:16, @(foo:32, r2L.b).b), er1 + test_h_gr32 0x1244, er1 ; 24 + mova/b.l @(0x1234:16, @(foo:32, r2.w).b), er1 + test_h_gr32 0x1244, er1 ; 25 + mova/b.l @(0x1234:16, @(foo:32, er2.l).b), er1 + test_h_gr32 0x1244, er1 ; 26 + + mova/b.l @(0x1234:16,@foo:16.b),er1 + test_h_gr32 0x1235, er1 ; 27 + mova/b.l @(0x1234:16,@foo:32.b),er1 + test_h_gr32 0x1235, er1 ; 28 + +t02e: + mov.l #foo, er2 + mova/b.l @(0x1234:16,@er2.w),er1 ;015F02911234 + test_h_gr32 0x1335, er1 ; 29 + test_h_gr32 foo, er2 + mova/b.l @(0x1234:16,@(0x2:2,er2).w),er1 ;015F12911234 + test_h_gr32 0x1335, er1 ; 34 + test_h_gr32 foo, er2 + mova/b.l @(0x1234:16,@er2+.w),er1 ;015F82911234 + test_h_gr32 0x1335, er1 ; 30 + test_h_gr32 foo+2, er2 + mova/b.l @(0x1234:16,@-er2.w),er1 ;015FB2911234 + test_h_gr32 0x1335, er1 ; 33 + test_h_gr32 foo, er2 + mova/b.l @(0x1234:16,@+er2.w),er1 ;015F92911234 + test_h_gr32 0x1335, er1 ; 32 + test_h_gr32 foo+2, er2 + mova/b.l @(0x1234:16,@er2-.w),er1 ;015FA2911234 + test_h_gr32 0x1335, er1 ; 31 + test_h_gr32 foo, er2 + + mov.l #4, er2 + mova/b.l @(0x1234:16, @(foo:16, er2).w), er1 + test_h_gr32 0x2244, er1 ; 35 + shar.l er2 + mova/b.l @(0x1234:16, @(foo:16, r2L.b).w), er1 + test_h_gr32 0x2244, er1 ; 37 + mova/b.l @(0x1234:16, @(foo:16, r2.w).w), er1 + test_h_gr32 0x2244, er1 ; 38 + mova/b.l @(0x1234:16, @(foo:16, er2.l).w), er1 + test_h_gr32 0x2244, er1 ; 39 + + mov.l #4, er2 + mova/b.l @(0x1234:16, @(foo:32, er2).w), er1 + test_h_gr32 0x2244, er1 ; 36 + shar.l er2 + mova/b.l @(0x1234:16, @(foo:32, r2L.b).w), er1 + test_h_gr32 0x2244, er1 ; 40 + mova/b.l @(0x1234:16, @(foo:32, r2.w).w), er1 + test_h_gr32 0x2244, er1 ; 41 + mova/b.l @(0x1234:16, @(foo:32, er2.l).w), er1 + test_h_gr32 0x2244, er1 ; 42 + + mova/b.l @(0x1234:16,@foo:16.w),er1 ;015F40919ABC1234 + test_h_gr32 0x1335, er1 ; 43 + mova/b.l @(0x1234:16,@foo:32.w),er1 ;015F48919ABCDEF01234 + test_h_gr32 0x1335, er1 ; 44 + +t02f: + mov.l #foo, er2 + mova/w.l @(0x1234:16,@er2.b),er1 ;017F02A11234 + test_h_gr32 0x1236, er1 ; 45 + mova/w.l @(0x1234:16,@(0x1:2,er2).b),er1 ;017F12A11234 + test_h_gr32 0x1236, er1 ; 50 + mova/w.l @(0x1234:16,@er2+.b),er1 ;017F82A11234 + test_h_gr32 0x1236, er1 ; 46 + test_h_gr32 foo+1, er2 + mova/w.l @(0x1234:16,@-er2.b),er1 ;017FB2A11234 + test_h_gr32 0x1236, er1 ; 49 + test_h_gr32 foo, er2 + mova/w.l @(0x1234:16,@+er2.b),er1 ;017F92A11234 + test_h_gr32 0x1236, er1 ; 48 + test_h_gr32 foo+1, er2 + mova/w.l @(0x1234:16,@er2-.b),er1 ;017FA2A11234 + test_h_gr32 0x1236, er1 ; 47 + test_h_gr32 foo, er2 + +t02g: + mov.l #4, er2 + mova/w.l @(0x1234:16, @(foo:16, er2).b), er1 + test_h_gr32 0x1254, er1 ; 51 + mova/w.l @(0x1234:16, @(foo:16, r2L.b).b), er1 + test_h_gr32 0x1254, er1 ; 53 + mova/w.l @(0x1234:16, @(foo:16, r2.w).b), er1 + test_h_gr32 0x1254, er1 ; 54 + mova/w.l @(0x1234:16, @(foo:16, er2.l).b), er1 + test_h_gr32 0x1254, er1 ; 55 + + mov.l #4, er2 + mova/w.l @(0x1234:16, @(foo:32, er2).b), er1 + test_h_gr32 0x1254, er1 ; 52 + mova/w.l @(0x1234:16, @(foo:32, r2L.b).b), er1 + test_h_gr32 0x1254, er1 ; 56 + mova/w.l @(0x1234:16, @(foo:32, r2.w).b), er1 + test_h_gr32 0x1254, er1 ; 57 + mova/w.l @(0x1234:16, @(foo:32, er2.l).b), er1 + test_h_gr32 0x1254, er1 ; 58 + + mova/w.l @(0x1234:16,@foo:16.b),er1 ;017F40A19ABC1234 + test_h_gr32 0x1236, er1 ; 59 (can't test -- points into the woods) + mova/w.l @(0x1234:16,@foo:32.b),er1 ;017F48A19ABCDEF01234 + test_h_gr32 0x1236, er1 ; 60 (can't test -- points into the woods) + +t02h: + mov.l #foo, er2 + mova/w.l @(0x1234:16,@er2.w),er1 ;015F02B11234 + test_h_gr32 0x1436, er1 ; 61 + mova/w.l @(0x1234:16,@(0x2:2,er2).w),er1 ;015F12B11234 + test_h_gr32 0x1436, er1 ; 66, 0x1234 + (@(4+foo).w << 1 + mova/w.l @(0x1234:16,@er2+.w),er1 ;015F82B11234 + test_h_gr32 0x1436, er1 ; 62 + test_h_gr32 foo+2, er2 + mova/w.l @(0x1234:16,@-er2.w),er1 ;015FB2B11234 + test_h_gr32 0x1436, er1 ; 63 + test_h_gr32 foo, er2 + mova/w.l @(0x1234:16,@+er2.w),er1 ;015F92B11234 + test_h_gr32 0x1436, er1 ; 64 + test_h_gr32 foo+2, er2 + mova/w.l @(0x1234:16,@er2-.w),er1 ;015FA2B11234 + test_h_gr32 0x1436, er1 ; 65 + test_h_gr32 foo, er2 +t02i: + mov.l #4, er2 + mova/w.l @(0x1234:16, @(foo:16, er2).w), er1 + test_h_gr32 0x3254, er1 ; 67 + shar.l er2 + mova/w.l @(0x1234:16, @(foo:16, r2L.b).w), er1 + test_h_gr32 0x3254, er1 ; 69 + mova/w.l @(0x1234:16, @(foo:16, r2.w).w), er1 + test_h_gr32 0x3254, er1 ; 70 + mova/w.l @(0x1234:16, @(foo:16, er2.l).w), er1 + test_h_gr32 0x3254, er1 ; 71 + + mov.l #4, er2 + mova/w.l @(0x1234:16, @(foo:32, er2).w), er1 + test_h_gr32 0x3254, er1 ; 68 + shar.l er2 + mova/w.l @(0x1234:16, @(foo:32, r2L.b).w), er1 + test_h_gr32 0x3254, er1 ; 72 + mova/w.l @(0x1234:16, @(foo:32, r2.w).w), er1 + test_h_gr32 0x3254, er1 ; 73 + mova/w.l @(0x1234:16, @(foo:32, er2.l).w), er1 + test_h_gr32 0x3254, er1 ; 74 + + mova/w.l @(0x1234:16,@foo:16.w),er1 ;015F40B19ABC1234 + test_h_gr32 0x1436, er1 ; 75 (can't test -- points into the woods) + mova/w.l @(0x1234:16,@foo:32.w),er1 ;015F48B19ABCDEF01234 + test_h_gr32 0x1436, er1 ; 76 (can't test -- points into the woods) + +t02j: + mov.l #foo, er2 + mova/l.l @(0x1234:16,@er2.b),er1 ;017F02C11234 + test_h_gr32 0x1238, er1 ; 77 + mova/l.l @(0x1234:16,@(0x1:2,er2).b),er1 ;017F12C11234 + test_h_gr32 0x1238, er1 ; 82 + mova/l.l @(0x1234:16,@er2+.b),er1 ;017F82C11234 + test_h_gr32 0x1238, er1 ; 78 + test_h_gr32 foo+1, er2 + mova/l.l @(0x1234:16,@-er2.b),er1 ;017FB2C11234 + test_h_gr32 0x1238, er1 ; 79 + test_h_gr32 foo, er2 + mova/l.l @(0x1234:16,@+er2.b),er1 ;017F92C11234 + test_h_gr32 0x1238, er1 ; 80 + test_h_gr32 foo+1, er2 + mova/l.l @(0x1234:16,@er2-.b),er1 ;017FA2C11234 + test_h_gr32 0x1238, er1 ; 81 + test_h_gr32 foo, er2 + +t02k: + mov.l #4, er2 + mova/l.l @(0x1234:16, @(foo:16, er2).b), er1 + test_h_gr32 0x1274, er1 ; 83 + mova/l.l @(0x1234:16, @(foo:16, r2L.b).b), er1 + test_h_gr32 0x1274, er1 ; 85 + mova/l.l @(0x1234:16, @(foo:16, r2.w).b), er1 + test_h_gr32 0x1274, er1 ; 86 + mova/l.l @(0x1234:16, @(foo:16, er2.l).b), er1 + test_h_gr32 0x1274, er1 ; 87 + + mov.l #4, er2 + mova/l.l @(0x1234:16, @(foo:32, er2).b), er1 + test_h_gr32 0x1274, er1 ; 84 + mova/l.l @(0x1234:16, @(foo:32, r2L.b).b), er1 + test_h_gr32 0x1274, er1 ; 88 + mova/l.l @(0x1234:16, @(foo:32, r2.w).b), er1 + test_h_gr32 0x1274, er1 ; 89 + mova/l.l @(0x1234:16, @(foo:32, er2.l).b), er1 + test_h_gr32 0x1274, er1 ; 90 + + mova/l.l @(0x1234:16,@foo:16.b),er1 ;017F40C19ABC1234 + test_h_gr32 0x1238, er1 ; 91 (can't test -- points into the woods) + mova/l.l @(0x1234:16,@foo:32.b),er1 ;017F48C19ABCDEF01234 + test_h_gr32 0x1238, er1 ; 92 (can't test -- points into the woods) + +t02l: + mov.l #foo, er2 + mova/l.l @(0x1234:16,@er2.w),er1 ;015F02D11234 + test_h_gr32 0x1638, er1 ; 93 + mova/l.l @(0x1234:16,@(0x2:2,er2).w),er1 ;015F12D11234 + test_h_gr32 0x1638, er1 ; 98 + mova/l.l @(0x1234:16,@er2+.w),er1 ;015F82D11234 + test_h_gr32 0x1638, er1 ; 94 + test_h_gr32 foo+2, er2 + mova/l.l @(0x1234:16,@-er2.w),er1 ;015FB2D11234 + test_h_gr32 0x1638, er1 ; 97 + test_h_gr32 foo, er2 + mova/l.l @(0x1234:16,@+er2.w),er1 ;015F92D11234 + test_h_gr32 0x1638, er1 ; 96 + test_h_gr32 foo+2, er2 + mova/l.l @(0x1234:16,@er2-.w),er1 ;015FA2D11234 + test_h_gr32 0x1638, er1 ; 95 + test_h_gr32 foo, er2 + +t02o: + mov.l #4, er2 + mova/l.l @(0x1234:16, @(foo:16, er2).w), er1 + test_h_gr32 0x5274, er1 ; 99 + shar.l er2 + mova/l.l @(0x1234:16, @(foo:16, r2L.b).w), er1 + test_h_gr32 0x5274, er1 ; 101 + mova/l.l @(0x1234:16, @(foo:16, r2.w).w), er1 + test_h_gr32 0x5274, er1 ; 102 + mova/l.l @(0x1234:16, @(foo:16, er2.l).w), er1 + test_h_gr32 0x5274, er1 ; 103 + + mov.l #4, er2 + mova/l.l @(0x1234:16, @(foo:32, er2).w), er1 + test_h_gr32 0x5274, er1 ; 100 + shar.l er2 + mova/l.l @(0x1234:16, @(foo:32, r2L.b).w), er1 + test_h_gr32 0x5274, er1 ; 104 + mova/l.l @(0x1234:16, @(foo:32, r2.w).w), er1 + test_h_gr32 0x5274, er1 ; 105 + mova/l.l @(0x1234:16, @(foo:32, er2.l).w), er1 + test_h_gr32 0x5274, er1 ; 106 + + mova/l.l @(0x1234:16,@foo:16.w),er1 ;015F40D19ABC1234 + test_h_gr32 0x1638, er1 ; 107 (can't test -- points into the woods) + mova/l.l @(0x1234:16,@foo:32.w),er1 ;015F48D19ABCDEF01234 + test_h_gr32 0x1638, er1 ; 108 (can't test -- points into the woods) + +t02p: + mov.l #foo, er2 + mova/b.l @(0x12345678:32,@er2.b),er1 ;017F028912345678 + test_h_gr32 0x12345679, er1 ; 109 + mova/b.l @(0x12345678:32,@(0x1:2,er2).b),er1 ;017F128912345678 + test_h_gr32 0x12345679, er1 ; 114 + mova/b.l @(0x12345678:32,@er2+.b),er1 ;017F828912345678 + test_h_gr32 0x12345679, er1 ; 110 + test_h_gr32 foo+1, er2 + mova/b.l @(0x12345678:32,@-er2.b),er1 ;017FB28912345678 + test_h_gr32 0x12345679, er1 ; 113 + test_h_gr32 foo, er2 + mova/b.l @(0x12345678:32,@+er2.b),er1 ;017F928912345678 + test_h_gr32 0x12345679, er1 ; 112 + test_h_gr32 foo+1, er2 + mova/b.l @(0x12345678:32,@er2-.b),er1 ;017FA28912345678 + test_h_gr32 0x12345679, er1 ; 111 + test_h_gr32 foo, er2 + +t02q: + mov.l #4, er2 + mova/b.l @(0x12345678:32, @(foo:16, er2).b), er1 + test_h_gr32 0x12345688, er1 ; 115 + mova/b.l @(0x12345678:32, @(foo:16, r2L.b).b), er1 + test_h_gr32 0x12345688, er1 ; 117 + mova/b.l @(0x12345678:32, @(foo:16, r2.w).b), er1 + test_h_gr32 0x12345688, er1 ; 118 + mova/b.l @(0x12345678:32, @(foo:16, er2.l).b), er1 + test_h_gr32 0x12345688, er1 ; 119 + + mov.l #4, er2 + mova/b.l @(0x12345678:32, @(foo:32, er2).b), er1 + test_h_gr32 0x12345688, er1 ; 116 + mova/b.l @(0x12345678:32, @(foo:32, r2L.b).b), er1 + test_h_gr32 0x12345688, er1 ; 120 + mova/b.l @(0x12345678:32, @(foo:32, r2.w).b), er1 + test_h_gr32 0x12345688, er1 ; 121 + mova/b.l @(0x12345678:32, @(foo:32, er2.l).b), er1 + test_h_gr32 0x12345688, er1 ; 122 + + mova/b.l @(0x12345678:32,@foo:16.b),er1 + test_h_gr32 0x12345679, er1 ; 123 + mova/b.l @(0x12345678:32,@foo:32.b),er1 + test_h_gr32 0x12345679, er1 ; 124 + +t02r: + mov.l #foo, er2 + mova/b.l @(0x12345678:32,@er2.w),er1 ;015F029912345678 + test_h_gr32 0x12345779, er1 ; 125 + mova/b.l @(0x12345678:32,@(0x2:2,er2).w),er1 ;015F129912345678 + test_h_gr32 0x12345779, er1 ; 130 + mova/b.l @(0x12345678:32,@er2+.w),er1 ;015F829912345678 + test_h_gr32 0x12345779, er1 ; 126 + test_h_gr32 foo+2, er2 + mova/b.l @(0x12345678:32,@-er2.w),er1 ;015FB29912345678 + test_h_gr32 0x12345779, er1 ; 129 + test_h_gr32 foo, er2 + mova/b.l @(0x12345678:32,@+er2.w),er1 ;015F929912345678 + test_h_gr32 0x12345779, er1 ; 128 + test_h_gr32 foo+2, er2 + mova/b.l @(0x12345678:32,@er2-.w),er1 ;015FA29912345678 + test_h_gr32 0x12345779, er1 ; 127 + test_h_gr32 foo, er2 + + mov.l #4, er2 + mova/b.l @(0x12345678:32, @(foo:16, er2).w), er1 + test_h_gr32 0x12346688, er1 ; 131 + shar.l er2 + mova/b.l @(0x12345678:32, @(foo:16, r2L.b).w), er1 + test_h_gr32 0x12346688, er1 ; 133 + mova/b.l @(0x12345678:32, @(foo:16, r2.w).w), er1 + test_h_gr32 0x12346688, er1 ; 134 + mova/b.l @(0x12345678:32, @(foo:16, er2.l).w), er1 + test_h_gr32 0x12346688, er1 ; 135 + + mov.l #4, er2 + mova/b.l @(0x12345678:32, @(foo:32, er2).w), er1 + test_h_gr32 0x12346688, er1 ; 132 + shar.l er2 + mova/b.l @(0x12345678:32, @(foo:32, r2L.b).w), er1 + test_h_gr32 0x12346688, er1 ; 136 + mova/b.l @(0x12345678:32, @(foo:32, r2.w).w), er1 + test_h_gr32 0x12346688, er1 ; 137 + mova/b.l @(0x12345678:32, @(foo:32, er2.l).w), er1 + test_h_gr32 0x12346688, er1 ; 138 + + mova/b.l @(0x12345678:32,@foo:16.w),er1 + test_h_gr32 0x12345779, er1 ; 139 + mova/b.l @(0x12345678:32,@foo:32.w),er1 + test_h_gr32 0x12345779, er1 ; 140 + +t02s: + mov.l #foo, er2 + mova/w.l @(0x12345678:32,@er2.b),er1 ;017F02A912345678 + test_h_gr32 0x1234567a, er1 ; 141 + mova/w.l @(0x12345678:32,@(0x1:2,er2).b),er1 ;017F12A912345678 + test_h_gr32 0x1234567a, er1 ; 146 + mova/w.l @(0x12345678:32,@er2+.b),er1 ;017F82A912345678 + test_h_gr32 0x1234567a, er1 ; 142 + test_h_gr32 foo+1, er2 + mova/w.l @(0x12345678:32,@-er2.b),er1 ;017FB2A912345678 + test_h_gr32 0x1234567a, er1 ; 145 + test_h_gr32 foo, er2 + mova/w.l @(0x12345678:32,@+er2.b),er1 ;017F92A912345678 + test_h_gr32 0x1234567a, er1 ; 144 + test_h_gr32 foo+1, er2 + mova/w.l @(0x12345678:32,@er2-.b),er1 ;017FA2A912345678 + test_h_gr32 0x1234567a, er1 ; 143 + test_h_gr32 foo, er2 + + mov.l #4, er2 + mova/w.l @(0x12345678:32, @(foo:16, er2).b), er1 + test_h_gr32 0x12345698, er1 ; 147 + mova/w.l @(0x12345678:32, @(foo:16, r2L.b).b), er1 + test_h_gr32 0x12345698, er1 ; 149 + mova/w.l @(0x12345678:32, @(foo:16, r2.w).b), er1 + test_h_gr32 0x12345698, er1 ; 150 + mova/w.l @(0x12345678:32, @(foo:16, er2.l).b), er1 + test_h_gr32 0x12345698, er1 ; 151 + + mov.l #4, er2 + mova/w.l @(0x12345678:32, @(foo:32, er2).b), er1 + test_h_gr32 0x12345698, er1 ; 148 + mova/w.l @(0x12345678:32, @(foo:32, r2L.b).b), er1 + test_h_gr32 0x12345698, er1 ; 152 + mova/w.l @(0x12345678:32, @(foo:32, r2.w).b), er1 + test_h_gr32 0x12345698, er1 ; 153 + mova/w.l @(0x12345678:32, @(foo:32, er2.l).b), er1 + test_h_gr32 0x12345698, er1 ; 154 + + mova/w.l @(0x12345678:32,@foo:16.b),er1 + test_h_gr32 0x1234567a, er1 ; 155 + mova/w.l @(0x12345678:32,@foo:32.b),er1 + test_h_gr32 0x1234567a, er1 ; 156 + +t02t: + mov.l #foo, er2 + mova/w.l @(0x12345678:32,@er2.w),er1 ;015F02B912345678 + test_h_gr32 0x1234587a, er1 ; 157 + mova/w.l @(0x12345678:32,@(0x2:2,er2).w),er1 ;015F12B912345678 + test_h_gr32 0x1234587a, er1 ; 162 + mova/w.l @(0x12345678:32,@er2+.w),er1 ;015F82B912345678 + test_h_gr32 0x1234587a, er1 ; 158 + test_h_gr32 foo+2, er2 + mova/w.l @(0x12345678:32,@-er2.w),er1 ;015FB2B912345678 + test_h_gr32 0x1234587a, er1 ; 161 + test_h_gr32 foo, er2 + mova/w.l @(0x12345678:32,@+er2.w),er1 ;015F92B912345678 + test_h_gr32 0x1234587a, er1 ; 160 + test_h_gr32 foo+2, er2 + mova/w.l @(0x12345678:32,@er2-.w),er1 ;015FA2B912345678 + test_h_gr32 0x1234587a, er1 ; 159 + test_h_gr32 foo, er2 + + mov.l #4, er2 + mova/w.l @(0x12345678:32, @(foo:16, er2).w), er1 + test_h_gr32 0x12347698, er1 ; 163 + shar.l er2 + mova/w.l @(0x12345678:32, @(foo:16, r2L.b).w), er1 + test_h_gr32 0x12347698, er1 ; 165 + mova/w.l @(0x12345678:32, @(foo:16, r2.w).w), er1 + test_h_gr32 0x12347698, er1 ; 166 + mova/w.l @(0x12345678:32, @(foo:16, er2.l).w), er1 + test_h_gr32 0x12347698, er1 ; 167 + + mov.l #4, er2 + mova/w.l @(0x12345678:32, @(foo:32, er2).w), er1 + test_h_gr32 0x12347698, er1 ; 164 + shar.l er2 + mova/w.l @(0x12345678:32, @(foo:32, r2L.b).w), er1 + test_h_gr32 0x12347698, er1 ; 168 + mova/w.l @(0x12345678:32, @(foo:32, r2.w).w), er1 + test_h_gr32 0x12347698, er1 ; 169 + mova/w.l @(0x12345678:32, @(foo:32, er2.l).w), er1 + test_h_gr32 0x12347698, er1 ; 170 + + mova/w.l @(0x12345678:32,@foo:16.w),er1 + test_h_gr32 0x1234587a, er1 ; 171 + mova/w.l @(0x12345678:32,@foo:32.w),er1 + test_h_gr32 0x1234587a, er1 ; 172 + +t02u: + mov.l #foo, er2 + mova/l.l @(0x12345678:32,@er2.b),er1 ;017F02C912345678 + test_h_gr32 0x1234567c, er1 ; 173 + mova/l.l @(0x12345678:32,@(0x1:2,er2).b),er1 ;017F12C912345678 + test_h_gr32 0x1234567c, er1 ; 178 + mova/l.l @(0x12345678:32,@er2+.b),er1 ;017F82C912345678 + test_h_gr32 0x1234567c, er1 ; 174 + test_h_gr32 foo+1, er2 + mova/l.l @(0x12345678:32,@-er2.b),er1 ;017FB2C912345678 + test_h_gr32 0x1234567c, er1 ; 177 + test_h_gr32 foo, er2 + mova/l.l @(0x12345678:32,@+er2.b),er1 ;017F92C912345678 + test_h_gr32 0x1234567c, er1 ; 176 + test_h_gr32 foo+1, er2 + mova/l.l @(0x12345678:32,@er2-.b),er1 ;017FA2C912345678 + test_h_gr32 0x1234567c, er1 ; 175 + test_h_gr32 foo, er2 + + mov.l #4, er2 + mova/l.l @(0x12345678:32, @(foo:16, er2).b), er1 + test_h_gr32 0x123456b8, er1 ; 179 + mova/l.l @(0x12345678:32, @(foo:16, r2L.b).b), er1 + test_h_gr32 0x123456b8, er1 ; 181 + mova/l.l @(0x12345678:32, @(foo:16, r2.w).b), er1 + test_h_gr32 0x123456b8, er1 ; 182 + mova/l.l @(0x12345678:32, @(foo:16, er2.l).b), er1 + test_h_gr32 0x123456b8, er1 ; 183 + + mov.l #4, er2 + mova/l.l @(0x12345678:32, @(foo:32, er2).b), er1 + test_h_gr32 0x123456b8, er1 ; 180 + mova/l.l @(0x12345678:32, @(foo:32, r2L.b).b), er1 + test_h_gr32 0x123456b8, er1 ; 184 + mova/l.l @(0x12345678:32, @(foo:32, r2.w).b), er1 + test_h_gr32 0x123456b8, er1 ; 185 + mova/l.l @(0x12345678:32, @(foo:32, er2.l).b), er1 + test_h_gr32 0x123456b8, er1 ; 186 + + mova/l.l @(0x12345678:32,@foo:16.b),er1 + test_h_gr32 0x1234567c, er1 ; 187 + mova/l.l @(0x12345678:32,@foo:32.b),er1 + test_h_gr32 0x1234567c, er1 ; 188 + +t02v: + mov.l #foo, er2 + mova/l.l @(0x12345678:32,@er2.w),er1 ;015F02D912345678 + test_h_gr32 0x12345a7c, er1 ; 189 + mova/l.l @(0x12345678:32,@(0x2:2,er2).w),er1 ;015F12D912345678 + test_h_gr32 0x12345a7c, er1 ; 194 + mova/l.l @(0x12345678:32,@er2+.w),er1 ;015F82D912345678 + test_h_gr32 0x12345a7c, er1 ; 190 + test_h_gr32 foo+2, er2 + mova/l.l @(0x12345678:32,@-er2.w),er1 ;015FB2D912345678 + test_h_gr32 0x12345a7c, er1 ; 193 + test_h_gr32 foo, er2 + mova/l.l @(0x12345678:32,@+er2.w),er1 ;015F92D912345678 + test_h_gr32 0x12345a7c, er1 ; 192 + test_h_gr32 foo+2, er2 + mova/l.l @(0x12345678:32,@er2-.w),er1 ;015FA2D912345678 + test_h_gr32 0x12345a7c, er1 ; 191 + test_h_gr32 foo, er2 + + mov.l #4, er2 + mova/l.l @(0x12345678:32, @(foo:16, er2).w), er1 + test_h_gr32 0x123496b8, er1 ; 195 + shar.l er2 + mova/l.l @(0x12345678:32, @(foo:16, r2L.b).w), er1 + test_h_gr32 0x123496b8, er1 ; 197 + mova/l.l @(0x12345678:32, @(foo:16, r2.w).w), er1 + test_h_gr32 0x123496b8, er1 ; 198 + mova/l.l @(0x12345678:32, @(foo:16, er2.l).w), er1 + test_h_gr32 0x123496b8, er1 ; 199 + + mov.l #4, er2 + mova/l.l @(0x12345678:32, @(foo:32, er2).w), er1 + test_h_gr32 0x123496b8, er1 ; 195 + shar.l er2 + mova/l.l @(0x12345678:32, @(foo:32, r2L.b).w), er1 + test_h_gr32 0x123496b8, er1 ; 197 + mova/l.l @(0x12345678:32, @(foo:32, r2.w).w), er1 + test_h_gr32 0x123496b8, er1 ; 198 + mova/l.l @(0x12345678:32, @(foo:32, er2.l).w), er1 + test_h_gr32 0x123496b8, er1 ; 199 + + mova/l.l @(0x12345678:32,@foo:16.w),er1 + test_h_gr32 0x12345a7c, er1 ; 203 + mova/l.l @(0x12345678:32,@foo:32.w),er1 + test_h_gr32 0x12345a7c, er1 ; 204 + + test_gr_a5a5 0 + test_h_gr32 2, er2 + test_h_gr32 0x01010101, er3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + pass + + exit 0 diff --git a/sim/testsuite/sim/h8300/movb.s b/sim/testsuite/sim/h8300/movb.s new file mode 100644 index 0000000..87dcdf3 --- /dev/null +++ b/sim/testsuite/sim/h8300/movb.s @@ -0,0 +1,2221 @@ +# Hitachi H8 testcase 'mov.w' +# mach(): h8300h h8300s h8sx +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + start + + .data + .align 4 +byte_src: + .byte 0x77 +byte_dst: + .byte 0 + + .text + + ;; + ;; Move byte from immediate source + ;; + +.if (sim_cpu == h8sx) +mov_b_imm8_to_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b #xx:8, rd + mov.b #0x77:8, r0l ; Immediate 3-bit operand +;;; .word 0xf877 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a5a577 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif + +.if (sim_cpu == h8sx) +mov_b_imm4_to_abs16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b #xx:4, @aa:16 + mov.b #0xf:4, @byte_dst:16 ; 16-bit address-direct operand +;;; .word 0x6adf +;;; .word @byte_dst + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed + test_gr_a5a5 1 ; (first, because on h8/300 we must use one + test_gr_a5a5 2 ; to examine the destination memory). + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b #0xf, @byte_dst + beq .Lnext21 + fail +.Lnext21: + mov.b #0, @byte_dst ; zero it again for the next use. + +mov_b_imm4_to_abs32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b #xx:4, @aa:32 + mov.b #0xf:4, @byte_dst:32 ; 32-bit address-direct operand +;;; .word 0x6aff +;;; .long @byte_dst + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed + test_gr_a5a5 1 ; (first, because on h8/300 we must use one + test_gr_a5a5 2 ; to examine the destination memory). + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b #0xf, @byte_dst + beq .Lnext22 + fail +.Lnext22: + mov.b #0, @byte_dst ; zero it again for the next use. + +mov_b_imm8_to_indirect: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b #xx:8, @erd + mov.l #byte_dst, er1 + mov.b #0xa5:8, @er1 ; Register indirect operand +;;; .word 0x017d +;;; .word 0x01a5 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 byte_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b #0xa5, @byte_dst + beq .Lnext1 + fail +.Lnext1: + mov.b #0, @byte_dst ; zero it again for the next use. + +mov_b_imm8_to_postinc: ; post-increment from imm8 to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b #xx:8, @erd+ + mov.l #byte_dst, er1 + mov.b #0xa5:8, @er1+ ; Imm8, register post-incr operands. +;;; .word 0x017d +;;; .word 0x81a5 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 byte_dst+1, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b #0xa5, @byte_dst + beq .Lnext2 + fail +.Lnext2: + mov.b #0, @byte_dst ; zero it again for the next use. + +mov_b_imm8_to_postdec: ; post-decrement from imm8 to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b #xx:8, @erd- + mov.l #byte_dst, er1 + mov.b #0xa5:8, @er1- ; Imm8, register post-decr operands. +;;; .word 0x017d +;;; .word 0xa1a5 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 byte_dst-1, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b #0xa5, @byte_dst + beq .Lnext3 + fail +.Lnext3: + mov.b #0, @byte_dst ; zero it again for the next use. + +mov_b_imm8_to_preinc: ; pre-increment from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b #xx:8, @+erd + mov.l #byte_dst-1, er1 + mov.b #0xa5:8, @+er1 ; Imm8, register pre-incr operands +;;; .word 0x017d +;;; .word 0x91a5 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 byte_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b #0xa5, @byte_dst + beq .Lnext4 + fail +.Lnext4: + mov.b #0, @byte_dst ; zero it again for the next use. + +mov_b_imm8_to_predec: ; pre-decrement from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b #xx:8, @-erd + mov.l #byte_dst+1, er1 + mov.b #0xa5:8, @-er1 ; Imm8, register pre-decr operands +;;; .word 0x017d +;;; .word 0xb1a5 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 byte_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b #0xa5, @byte_dst + beq .Lnext5 + fail +.Lnext5: + mov.b #0, @byte_dst ; zero it again for the next use. + +mov_b_imm8_to_disp2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b #xx:8, @(dd:2, erd) + mov.l #byte_dst-3, er1 + mov.b #0xa5:8, @(3:2, er1) ; Imm8, reg plus 2-bit disp. operand +;;; .word 0x017d +;;; .word 0x31a5 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 byte_dst-3, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b #0xa5, @byte_dst + beq .Lnext6 + fail +.Lnext6: + mov.b #0, @byte_dst ; zero it again for the next use. + +mov_b_imm8_to_disp16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b #xx:8, @(dd:16, erd) + mov.l #byte_dst-4, er1 + mov.b #0xa5:8, @(4:16, er1) ; Register plus 16-bit disp. operand +;;; .word 0x017d +;;; .word 0x6f90 +;;; .word 0x0004 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 byte_dst-4, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b #0xa5, @byte_dst + beq .Lnext7 + fail +.Lnext7: + mov.b #0, @byte_dst ; zero it again for the next use. + +mov_b_imm8_to_disp32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b #xx:8, @(dd:32, erd) + mov.l #byte_dst-8, er1 + mov.b #0xa5:8, @(8:32, er1) ; Register plus 32-bit disp. operand +;;; .word 0x017d +;;; .word 0xc9a5 +;;; .long 8 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 byte_dst-8, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b #0xa5, @byte_dst + beq .Lnext8 + fail +.Lnext8: + mov.b #0, @byte_dst ; zero it again for the next use. + +mov_b_imm8_to_indexb16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov.l #0xffffff01, er1 + set_ccr_zero + ;; mov.b #xx:8, @(dd:16, rd.b) + mov.b #0xa5:8, @(byte_dst-1:16, r1.b) ; byte indexed operand + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 0xffffff01, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b #0xa5, @byte_dst + bne fail1 + mov.b #0, @byte_dst ; zero it again for the next use. + +mov_b_imm8_to_indexw16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov.l #0xffff0002, er1 + set_ccr_zero + ;; mov.b #xx:8, @(dd:16, rd.w) + mov.b #0xa5:8, @(byte_dst-2:16, r1.w) ; byte indexed operand + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 0xffff0002, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b #0xa5, @byte_dst + bne fail1 + mov.b #0, @byte_dst ; zero it again for the next use. + +mov_b_imm8_to_indexl16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov.l #0x00000003, er1 + set_ccr_zero + ;; mov.b #xx:8, @(dd:16, erd.l) + mov.b #0xa5:8, @(byte_dst-3:16, er1.l) ; byte indexed operand + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 0x00000003, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b #0xa5, @byte_dst + bne fail1 + mov.b #0, @byte_dst ; zero it again for the next use. + +mov_b_imm8_to_indexb32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov.l #0xffffff04, er1 + set_ccr_zero + ;; mov.b #xx:8, @(dd:32, rd.b) + mov.b #0xa5:8, @(byte_dst-4:32, r1.b) ; byte indexed operand + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 0xffffff04 er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b #0xa5, @byte_dst + bne fail1 + mov.b #0, @byte_dst ; zero it again for the next use. + +mov_b_imm8_to_indexw32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov.l #0xffff0005, er1 + set_ccr_zero + ;; mov.b #xx:8, @(dd:32, rd.w) + mov.b #0xa5:8, @(byte_dst-5:32, r1.w) ; byte indexed operand + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 0xffff0005 er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b #0xa5, @byte_dst + bne fail1 + mov.b #0, @byte_dst ; zero it again for the next use. + +mov_b_imm8_to_indexl32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov.l #0x00000006, er1 + set_ccr_zero + ;; mov.b #xx:8, @(dd:32, erd.l) + mov.b #0xa5:8, @(byte_dst-6:32, er1.l) ; byte indexed operand + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 0x00000006 er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b #0xa5, @byte_dst + bne fail1 + mov.b #0, @byte_dst ; zero it again for the next use. + +mov_b_imm8_to_abs16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b #xx:8, @aa:16 + mov.b #0xa5:8, @byte_dst:16 ; 16-bit address-direct operand +;;; .word 0x017d +;;; .word 0x40a5 +;;; .word @byte_dst + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed + test_gr_a5a5 1 ; (first, because on h8/300 we must use one + test_gr_a5a5 2 ; to examine the destination memory). + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b #0xa5, @byte_dst + beq .Lnext9 + fail +.Lnext9: + mov.b #0, @byte_dst ; zero it again for the next use. + +mov_b_imm8_to_abs32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b #xx:8, @aa:32 + mov.b #0xa5:8, @byte_dst:32 ; 32-bit address-direct operand +;;; .word 0x017d +;;; .word 0x48a5 +;;; .long @byte_dst + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed + test_gr_a5a5 1 ; (first, because on h8/300 we must use one + test_gr_a5a5 2 ; to examine the destination memory). + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b #0xa5, @byte_dst + beq .Lnext10 + fail +.Lnext10: + mov.b #0, @byte_dst ; zero it again for the next use. + +.endif + + ;; + ;; Move byte from register source + ;; + +mov_b_reg8_to_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b ers, erd + mov.b #0x12, r1l + mov.b r1l, r0l ; Register 8-bit operand +;;; .word 0x0c98 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + test_h_gr16 0xa512 r0 + test_h_gr16 0xa512 r1 ; mov src unchanged +.if (sim_cpu) + test_h_gr32 0xa5a5a512 er0 + test_h_gr32 0xa5a5a512 er1 ; mov src unchanged +.endif + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + +mov_b_reg8_to_indirect: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b ers, @erd + mov.l #byte_dst, er1 + mov.b r0l, @er1 ; Register indirect operand +;;; .word 0x6898 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 byte_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + mov.b @byte_dst, r0l + cmp.b r2l, r0l + beq .Lnext44 + fail +.Lnext44: + mov.b #0, r0l + mov.b r0l, @byte_dst ; zero it again for the next use. + +.if (sim_cpu == h8sx) +mov_b_reg8_to_postinc: ; post-increment from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b ers, @erd+ + mov.l #byte_dst, er1 + mov.b r0l, @er1+ ; Register post-incr operand +;;; .word 0x0173 +;;; .word 0x6c98 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 byte_dst+1, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b r2l, @byte_dst + beq .Lnext49 + fail +.Lnext49: + mov.b #0, @byte_dst ; zero it again for the next use. + +mov_b_reg8_to_postdec: ; post-decrement from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b ers, @erd- + mov.l #byte_dst, er1 + mov.b r0l, @er1- ; Register post-decr operand +;;; .word 0x0171 +;;; .word 0x6c98 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 byte_dst-1, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b r2l, @byte_dst + beq .Lnext50 + fail +.Lnext50: + mov.b #0, @byte_dst ; zero it again for the next use. + +mov_b_reg8_to_preinc: ; pre-increment from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b ers, @+erd + mov.l #byte_dst-1, er1 + mov.b r0l, @+er1 ; Register pre-incr operand +;;; .word 0x0172 +;;; .word 0x6c98 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 byte_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b r2l, @byte_dst + beq .Lnext51 + fail +.Lnext51: + mov.b #0, @byte_dst ; zero it again for the next use. +.endif + +mov_b_reg8_to_predec: ; pre-decrement from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b ers, @-erd + mov.l #byte_dst+1, er1 + mov.b r0l, @-er1 ; Register pre-decr operand +;;; .word 0x6c98 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 byte_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + mov.b @byte_dst, r0l + cmp.b r2l, r0l + beq .Lnext48 + fail +.Lnext48: + mov.b #0, r0l + mov.b r0l, @byte_dst ; zero it again for the next use. + +.if (sim_cpu == h8sx) +mov_b_reg8_to_disp2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b ers, @(dd:2, erd) + mov.l #byte_dst-3, er1 + mov.b r0l, @(3:2, er1) ; Register plus 2-bit disp. operand +;;; .word 0x0173 +;;; .word 0x6898 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 byte_dst-3, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b r2l, @byte_dst + beq .Lnext52 + fail +.Lnext52: + mov.b #0, @byte_dst ; zero it again for the next use. +.endif + +mov_b_reg8_to_disp16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b ers, @(dd:16, erd) + mov.l #byte_dst-4, er1 + mov.b r0l, @(4:16, er1) ; Register plus 16-bit disp. operand +;;; .word 0x6e98 +;;; .word 0x0004 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 byte_dst-4, er1 + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + mov.b @byte_dst, r0l + cmp.b r2l, r0l + beq .Lnext45 + fail +.Lnext45: + mov.b #0, r0l + mov.b r0l, @byte_dst ; zero it again for the next use. + +mov_b_reg8_to_disp32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b ers, @(dd:32, erd) + mov.l #byte_dst-8, er1 + mov.b r0l, @(8:32, er1) ; Register plus 32-bit disp. operand +;;; .word 0x7810 +;;; .word 0x6aa8 +;;; .long 8 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 byte_dst-8, er1 + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + mov.b @byte_dst, r0l + cmp.b r2l, r0l + beq .Lnext46 + fail +.Lnext46: + mov.b #0, r0l + mov.b r0l, @byte_dst ; zero it again for the next use. + +.if (sim_cpu == h8sx) +mov_b_reg8_to_indexb16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov.l #0xffffff01, er1 + set_ccr_zero + ;; mov.b ers, @(dd:16, rd.b) + mov.b r0l, @(byte_dst-1:16, r1.b) ; byte indexed operand + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xffffff01 er1 + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b @byte_dst, r0l + bne fail1 + mov.b #0, @byte_dst ; zero it again for the next use. + +mov_b_reg8_to_indexw16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov.l #0xffff0002, er1 + set_ccr_zero + ;; mov.b ers, @(dd:16, rd.w) + mov.b r0l, @(byte_dst-2:16, r1.w) ; byte indexed operand + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xffff0002 er1 + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b @byte_dst, r0l + bne fail1 + mov.b #0, @byte_dst ; zero it again for the next use. + +mov_b_reg8_to_indexl16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov.l #0x00000003, er1 + set_ccr_zero + ;; mov.b ers, @(dd:16, erd.l) + mov.b r0l, @(byte_dst-3:16, er1.l) ; byte indexed operand + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0x00000003 er1 + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b @byte_dst, r0l + bne fail1 + mov.b #0, @byte_dst ; zero it again for the next use. + +mov_b_reg8_to_indexb32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov.l #0xffffff04 er1 + set_ccr_zero + ;; mov.b ers, @(dd:32, rd.b) + mov.b r0l, @(byte_dst-4:32, r1.b) ; byte indexed operand + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xffffff04, er1 + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b @byte_dst, r0l + bne fail1 + mov.b #0, @byte_dst ; zero it again for the next use. + +mov_b_reg8_to_indexw32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov.l #0xffff0005 er1 + set_ccr_zero + ;; mov.b ers, @(dd:32, rd.w) + mov.b r0l, @(byte_dst-5:32, r1.w) ; byte indexed operand + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xffff0005, er1 + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b @byte_dst, r0l + bne fail1 + mov.b #0, @byte_dst ; zero it again for the next use. + +mov_b_reg8_to_indexl32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov.l #0x00000006 er1 + set_ccr_zero + ;; mov.b ers, @(dd:32, erd.l) + mov.b r0l, @(byte_dst-6:32, er1.l) ; byte indexed operand + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0x00000006, er1 + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b @byte_dst, r0l + bne fail1 + mov.b #0, @byte_dst ; zero it again for the next use. +.endif + +.if (sim_cpu == h8sx) +mov_b_reg8_to_abs8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + mov.l #byte_dst-20, er0 + ldc er0, sbr + set_ccr_zero + ;; mov.b ers, @aa:8 + mov.b r1l, @20:8 ; 8-bit address-direct (sbr-relative) operand + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 byte_dst-20, er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b @byte_dst, r1l + bne fail1 + mov.b #0, @byte_dst ; zero it again for the next use. +.endif + +mov_b_reg8_to_abs16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b ers, @aa:16 + mov.b r0l, @byte_dst:16 ; 16-bit address-direct operand +;;; .word 0x6a88 +;;; .word @byte_dst + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed + test_gr_a5a5 1 ; (first, because on h8/300 we must use one + test_gr_a5a5 2 ; to examine the destination memory). + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + mov.b @byte_dst, r0l + cmp.b r0l, r1l + beq .Lnext41 + fail +.Lnext41: + mov.b #0, r0l + mov.b r0l, @byte_dst ; zero it again for the next use. + +mov_b_reg8_to_abs32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b ers, @aa:32 + mov.b r0l, @byte_dst:32 ; 32-bit address-direct operand +;;; .word 0x6aa8 +;;; .long @byte_dst + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed + test_gr_a5a5 1 ; (first, because on h8/300 we must use one + test_gr_a5a5 2 ; to examine the destination memory). + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + mov.b @byte_dst, r0l + cmp.b r0l, r1l + beq .Lnext42 + fail +.Lnext42: + mov.b #0, r0l + mov.b r0l, @byte_dst ; zero it again for the next use. + + ;; + ;; Move byte to register destination. + ;; + +mov_b_indirect_to_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b @ers, rd + mov.l #byte_src, er1 + mov.b @er1, r0l ; Register indirect operand +;;; .word 0x6818 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a5a577 er0 + + test_h_gr32 byte_src, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +mov_b_postinc_to_reg8: ; post-increment from mem to register + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b @ers+, rd + + mov.l #byte_src, er1 + mov.b @er1+, r0l ; Register post-incr operand +;;; .word 0x6c18 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a5a577 er0 + + test_h_gr32 byte_src+1, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +mov_b_postdec_to_reg8: ; post-decrement from mem to register + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b @ers-, rd + + mov.l #byte_src, er1 + mov.b @er1-, r0l ; Register post-decr operand +;;; .word 0x0172 +;;; .word 0x6c18 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a5a577 er0 + + test_h_gr32 byte_src-1, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +mov_b_preinc_to_reg8: ; pre-increment from mem to register + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b @+ers, rd + + mov.l #byte_src-1, er1 + mov.b @+er1, r0l ; Register pre-incr operand +;;; .word 0x0171 +;;; .word 0x6c18 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a5a577 er0 + + test_h_gr32 byte_src, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +mov_b_predec_to_reg8: ; pre-decrement from mem to register + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b @-ers, rd + + mov.l #byte_src+1, er1 + mov.b @-er1, r0l ; Register pre-decr operand +;;; .word 0x0173 +;;; .word 0x6c18 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a5a577 er0 + + test_h_gr32 byte_src, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + +mov_b_disp2_to_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b @(dd:2, ers), rd + mov.l #byte_src-1, er1 + mov.b @(1:2, er1), r0l ; Register plus 2-bit disp. operand +;;; .word 0x0171 +;;; .word 0x6818 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a5a577 er0 ; mov result: a5a5 | 7777 + + test_h_gr32 byte_src-1, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif + +mov_b_disp16_to_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b @(dd:16, ers), rd + mov.l #byte_src+0x1234, er1 + mov.b @(-0x1234:16, er1), r0l ; Register plus 16-bit disp. operand +;;; .word 0x6e18 +;;; .word -0x1234 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a5a577 er0 ; mov result: a5a5 | 7777 + + test_h_gr32 byte_src+0x1234, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +mov_b_disp32_to_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b @(dd:32, ers), rd + mov.l #byte_src+65536, er1 + mov.b @(-65536:32, er1), r0l ; Register plus 32-bit disp. operand +;;; .word 0x7810 +;;; .word 0x6a28 +;;; .long -65536 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a5a577 er0 ; mov result: a5a5 | 7777 + + test_h_gr32 byte_src+65536, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +mov_b_indexb16_to_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov.l #0xffffff01, er1 + set_ccr_zero + ;; mov.b @(dd:16, rs.b), rd + mov.b @(byte_src-1:16, r1.b), r0l ; indexed byte operand + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a5a577 er0 ; mov result: a5a5a5 | 77 + + test_h_gr32 0xffffff01, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +mov_b_indexw16_to_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov.l #0xffff0002, er1 + set_ccr_zero + ;; mov.b @(dd:16, rs.w), rd + mov.b @(byte_src-2:16, r1.w), r0l ; indexed byte operand + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a5a577 er0 ; mov result: a5a5a5 | 77 + + test_h_gr32 0xffff0002, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +mov_b_indexl16_to_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov.l #0x00000003, er1 + set_ccr_zero + ;; mov.b @(dd:16, ers.l), rd + mov.b @(byte_src-3:16, er1.l), r0l ; indexed byte operand + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a5a577 er0 ; mov result: a5a5a5 | 77 + + test_h_gr32 0x00000003, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +mov_b_indexb32_to_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov.l #0xffffff04, er1 + set_ccr_zero + ;; mov.b @(dd:32, rs.b), rd + mov.b @(byte_src-4:32, r1.b), r0l ; indexed byte operand + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a5a577 er0 ; mov result: a5a5 | 7777 + + test_h_gr32 0xffffff04 er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +mov_b_indexw32_to_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov.l #0xffff0005, er1 + set_ccr_zero + ;; mov.b @(dd:32, rs.w), rd + mov.b @(byte_src-5:32, r1.w), r0l ; indexed byte operand + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a5a577 er0 ; mov result: a5a5 | 7777 + + test_h_gr32 0xffff0005 er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +mov_b_indexl32_to_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov.l #0x00000006, er1 + set_ccr_zero + ;; mov.b @(dd:32, ers.l), rd + mov.b @(byte_src-6:32, er1.l), r0l ; indexed byte operand + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a5a577 er0 ; mov result: a5a5 | 7777 + + test_h_gr32 0x00000006 er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.endif + +.if (sim_cpu == h8sx) +mov_b_abs8_to_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov.l #byte_src-255, er1 + ldc er1, sbr + set_ccr_zero + ;; mov.b @aa:8, rd + mov.b @0xff:8, r0l ; 8-bit (sbr relative) address-direct operand + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a5a577 er0 + + test_h_gr32 byte_src-255, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif + +mov_b_abs16_to_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b @aa:16, rd + mov.b @byte_src:16, r0l ; 16-bit address-direct operand +;;; .word 0x6a08 +;;; .word @byte_src + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a5a577 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +mov_b_abs32_to_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b @aa:32, rd + mov.b @byte_src:32, r0l ; 32-bit address-direct operand +;;; .word 0x6a28 +;;; .long @byte_src + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a5a577 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) + + ;; + ;; Move byte from memory to memory + ;; + +mov_b_indirect_to_indirect: ; reg indirect, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b @ers, @erd + + mov.l #byte_src, er1 + mov.l #byte_dst, er0 + mov.b @er1, @er0 +;;; .word 0x0178 +;;; .word 0x0100 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 byte_dst er0 + test_h_gr32 byte_src er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b @byte_src, @byte_dst + beq .Lnext55 + fail +.Lnext55: + ;; Now clear the destination location, and verify that. + mov.b #0, @byte_dst + cmp.b @byte_src, @byte_dst + bne .Lnext56 + fail +.Lnext56: ; OK, pass on. + +mov_b_postinc_to_postinc: ; reg post-increment, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b @ers+, @erd+ + + mov.l #byte_src, er1 + mov.l #byte_dst, er0 + mov.b @er1+, @er0+ +;;; .word 0x0178 +;;; .word 0x8180 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 byte_dst+1 er0 + test_h_gr32 byte_src+1 er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b @byte_src, @byte_dst + beq .Lnext65 + fail +.Lnext65: + ;; Now clear the destination location, and verify that. + mov.b #0, @byte_dst + cmp.b @byte_src, @byte_dst + bne .Lnext66 + fail +.Lnext66: ; OK, pass on. + +mov_b_postdec_to_postdec: ; reg post-decrement, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b @ers-, @erd- + + mov.l #byte_src, er1 + mov.l #byte_dst, er0 + mov.b @er1-, @er0- +;;; .word 0x0178 +;;; .word 0xa1a0 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 byte_dst-1 er0 + test_h_gr32 byte_src-1 er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b @byte_src, @byte_dst + beq .Lnext75 + fail +.Lnext75: + ;; Now clear the destination location, and verify that. + mov.b #0, @byte_dst + cmp.b @byte_src, @byte_dst + bne .Lnext76 + fail +.Lnext76: ; OK, pass on. + +mov_b_preinc_to_preinc: ; reg pre-increment, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b @+ers, @+erd + + mov.l #byte_src-1, er1 + mov.l #byte_dst-1, er0 + mov.b @+er1, @+er0 +;;; .word 0x0178 +;;; .word 0x9190 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 byte_dst er0 + test_h_gr32 byte_src er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b @byte_src, @byte_dst + beq .Lnext85 + fail +.Lnext85: + ;; Now clear the destination location, and verify that. + mov.b #0, @byte_dst + cmp.b @byte_src, @byte_dst + bne .Lnext86 + fail +.Lnext86: ; OK, pass on. + +mov_b_predec_to_predec: ; reg pre-decrement, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b @-ers, @-erd + + mov.l #byte_src+1, er1 + mov.l #byte_dst+1, er0 + mov.b @-er1, @-er0 +;;; .word 0x0178 +;;; .word 0xb1b0 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 byte_dst er0 + test_h_gr32 byte_src er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b @byte_src, @byte_dst + beq .Lnext95 + fail +.Lnext95: + ;; Now clear the destination location, and verify that. + mov.b #0, @byte_dst + cmp.b @byte_src, @byte_dst + bne .Lnext96 + fail +.Lnext96: ; OK, pass on. + +mov_b_disp2_to_disp2: ; reg 2-bit disp, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b @(dd:2, ers), @(dd:2, erd) + + mov.l #byte_src-1, er1 + mov.l #byte_dst-2, er0 + mov.b @(1:2, er1), @(2:2, er0) +;;; .word 0x0178 +;;; .word 0x1120 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 byte_dst-2 er0 + test_h_gr32 byte_src-1 er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b @byte_src, @byte_dst + beq .Lnext105 + fail +.Lnext105: + ;; Now clear the destination location, and verify that. + mov.b #0, @byte_dst + cmp.b @byte_src, @byte_dst + bne .Lnext106 + fail +.Lnext106: ; OK, pass on. + +mov_b_disp16_to_disp16: ; reg 16-bit disp, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b @(dd:16, ers), @(dd:16, erd) + + mov.l #byte_src-1, er1 + mov.l #byte_dst-2, er0 + mov.b @(1:16, er1), @(2:16, er0) +;;; .word 0x0178 +;;; .word 0xc1c0 +;;; .word 0x0001 +;;; .word 0x0002 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 byte_dst-2 er0 + test_h_gr32 byte_src-1 er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b @byte_src, @byte_dst + beq .Lnext115 + fail +.Lnext115: + ;; Now clear the destination location, and verify that. + mov.b #0, @byte_dst + cmp.b @byte_src, @byte_dst + bne .Lnext116 + fail +.Lnext116: ; OK, pass on. + +mov_b_disp32_to_disp32: ; reg 32-bit disp, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b @(dd:32, ers), @(dd:32, erd) + + mov.l #byte_src-1, er1 + mov.l #byte_dst-2, er0 + mov.b @(1:32, er1), @(2:32, er0) +;;; .word 0x0178 +;;; .word 0xc9c8 +;;; .long 1 +;;; .long 2 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 byte_dst-2 er0 + test_h_gr32 byte_src-1 er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b @byte_src, @byte_dst + beq .Lnext125 + fail +.Lnext125: + ;; Now clear the destination location, and verify that. + mov.b #0, @byte_dst + cmp.b @byte_src, @byte_dst + bne .Lnext126 + fail +.Lnext126: ; OK, pass on. + +mov_b_indexb16_to_indexb16: ; reg 16-bit indexed, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov.l #0xffffff01, er1 + mov.l #0xffffff02, er0 + ;; mov.b @(dd:16, rs.b), @(dd:16, rd.b) + set_ccr_zero + mov.b @(byte_src-1:16, r1.b), @(byte_dst-2:16, r0.b) + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 0xffffff02 er0 + test_h_gr32 0xffffff01 er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b @byte_src, @byte_dst + bne fail1 + ;; Now clear the destination location, and verify that. + mov.b #0, @byte_dst + cmp.b @byte_src, @byte_dst + beq fail1 + +mov_b_indexw16_to_indewb16: ; reg 16-bit indexed, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov.l #0xffff0003, er1 + mov.l #0xffff0004, er0 + ;; mov.b @(dd:16, rs.w), @(dd:16, rd.w) + set_ccr_zero + mov.b @(byte_src-3:16, r1.w), @(byte_dst-4:16, r0.w) + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 0xffff0004 er0 + test_h_gr32 0xffff0003 er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b @byte_src, @byte_dst + bne fail1 + ;; Now clear the destination location, and verify that. + mov.b #0, @byte_dst + cmp.b @byte_src, @byte_dst + beq fail1 + +mov_b_indexl16_to_indexl16: ; reg 16-bit indexed, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov.l #0x00000005, er1 + mov.l #0x00000006, er0 + ;; mov.b @(dd:16, ers.l), @(dd:16, erd.l) + set_ccr_zero + mov.b @(byte_src-5:16, er1.l), @(byte_dst-6:16, er0.l) + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 0x00000006 er0 + test_h_gr32 0x00000005 er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b @byte_src, @byte_dst + bne fail1 + ;; Now clear the destination location, and verify that. + mov.b #0, @byte_dst + cmp.b @byte_src, @byte_dst + beq fail1 + +mov_b_indexb32_to_indexb32: ; reg 32-bit indexed, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov.l #0xffffff01, er1 + mov.l #0xffffff02, er0 + set_ccr_zero + ;; mov.b @(dd:32, rs.b), @(dd:32, rd.b) + mov.b @(byte_src-1:32, r1.b), @(byte_dst-2:32, r0.b) + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 0xffffff02 er0 + test_h_gr32 0xffffff01 er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b @byte_src, @byte_dst + bne fail1 + ;; Now clear the destination location, and verify that. + mov.b #0, @byte_dst + cmp.b @byte_src, @byte_dst + beq fail1 + +mov_b_indexw32_to_indexw32: ; reg 32-bit indexed, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov.l #0xffff0003, er1 + mov.l #0xffff0004, er0 + set_ccr_zero + ;; mov.b @(dd:32, rs.w), @(dd:32, rd.w) + mov.b @(byte_src-3:32, r1.w), @(byte_dst-4:32, r0.w) + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 0xffff0004 er0 + test_h_gr32 0xffff0003 er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b @byte_src, @byte_dst + bne fail1 + ;; Now clear the destination location, and verify that. + mov.b #0, @byte_dst + cmp.b @byte_src, @byte_dst + beq fail1 + +mov_b_indexl32_to_indexl32: ; reg 32-bit indexed, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov.l #0x00000005, er1 + mov.l #0x00000006, er0 + set_ccr_zero + ;; mov.b @(dd:32, rs.w), @(dd:32, rd.w) + mov.b @(byte_src-5:32, er1.l), @(byte_dst-6:32, er0.l) + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 0x00000006 er0 + test_h_gr32 0x00000005 er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b @byte_src, @byte_dst + bne fail1 + ;; Now clear the destination location, and verify that. + mov.b #0, @byte_dst + cmp.b @byte_src, @byte_dst + beq fail1 + +mov_b_abs16_to_abs16: ; 16-bit absolute addr, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b @aa:16, @aa:16 + + mov.b @byte_src:16, @byte_dst:16 +;;; .word 0x0178 +;;; .word 0x4040 +;;; .word @byte_src +;;; .word @byte_dst + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + + test_gr_a5a5 0 ; Make sure *NO* general registers are changed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b @byte_src, @byte_dst + beq .Lnext135 + fail +.Lnext135: + ;; Now clear the destination location, and verify that. + mov.b #0, @byte_dst + cmp.b @byte_src, @byte_dst + bne .Lnext136 + fail +.Lnext136: ; OK, pass on. + +mov_b_abs32_to_abs32: ; 32-bit absolute addr, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b @aa:32, @aa:32 + + mov.b @byte_src:32, @byte_dst:32 +;;; .word 0x0178 +;;; .word 0x4848 +;;; .long @byte_src +;;; .long @byte_dst + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure *NO* general registers are changed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b @byte_src, @byte_dst + beq .Lnext145 + fail +.Lnext145: + ;; Now clear the destination location, and verify that. + mov.b #0, @byte_dst + cmp.b @byte_src, @byte_dst + bne .Lnext146 + fail +.Lnext146: ; OK, pass on. + + +.endif + + pass + + exit 0 + +fail1: + fail + \ No newline at end of file diff --git a/sim/testsuite/sim/h8300/movl.s b/sim/testsuite/sim/h8300/movl.s new file mode 100644 index 0000000..dcc3922 --- /dev/null +++ b/sim/testsuite/sim/h8300/movl.s @@ -0,0 +1,2160 @@ +# Hitachi H8 testcase 'mov.l' +# mach(): h8300h h8300s h8sx +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + start + + .data + .align 4 +long_src: + .long 0x77777777 +long_dst: + .long 0 + + .text + + ;; + ;; Move long from immediate source + ;; + +.if (sim_cpu == h8sx) +mov_l_imm3_to_reg32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:3, erd + mov.l #0x3:3, er0 ; Immediate 3-bit operand +;;; .word 0x0fb8 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0x3 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +mov_l_imm16_to_reg32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:16, erd + mov.l #0x1234, er0 ; Immediate 16-bit operand +;;; .word 0x7a08 +;;; .word 0x1234 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0x1234 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif + +mov_l_imm32_to_reg32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:32, erd + mov.l #0x12345678, er0 ; Immediate 32-bit operand +;;; .word 0x7a00 +;;; .long 0x12345678 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0x12345678 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +mov_l_imm8_to_indirect: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:8, @erd + mov.l #long_dst, er1 + mov.l #0xa5:8, @er1 ; Register indirect operand +;;; .word 0x010d +;;; .word 0x01a5 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0xa5, @long_dst + beq .Lnext1 + fail +.Lnext1: + mov.l #0, @long_dst ; zero it again for the next use. + +mov_l_imm8_to_postinc: ; post-increment from imm8 to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:8, @erd+ + mov.l #long_dst, er1 + mov.l #0xa5:8, @er1+ ; Imm8, register post-incr operands. +;;; .word 0x010d +;;; .word 0x81a5 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst+4, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0xa5, @long_dst + beq .Lnext2 + fail +.Lnext2: + mov.l #0, @long_dst ; zero it again for the next use. + +mov_l_imm8_to_postdec: ; post-decrement from imm8 to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:8, @erd- + mov.l #long_dst, er1 + mov.l #0xa5:8, @er1- ; Imm8, register post-decr operands. +;;; .word 0x010d +;;; .word 0xa1a5 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst-4, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0xa5, @long_dst + beq .Lnext3 + fail +.Lnext3: + mov.l #0, @long_dst ; zero it again for the next use. + +mov_l_imm8_to_preinc: ; pre-increment from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:8, @+erd + mov.l #long_dst-4, er1 + mov.l #0xa5:8, @+er1 ; Imm8, register pre-incr operands +;;; .word 0x010d +;;; .word 0x91a5 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0xa5, @long_dst + beq .Lnext4 + fail +.Lnext4: + mov.l #0, @long_dst ; zero it again for the next use. + +mov_l_imm8_to_predec: ; pre-decrement from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:8, @-erd + mov.l #long_dst+4, er1 + mov.l #0xa5:8, @-er1 ; Imm8, register pre-decr operands +;;; .word 0x010d +;;; .word 0xb1a5 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0xa5, @long_dst + beq .Lnext5 + fail +.Lnext5: + mov.l #0, @long_dst ; zero it again for the next use. + +mov_l_imm8_to_disp2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:8, @(dd:2, erd) + mov.l #long_dst-12, er1 + mov.l #0xa5:8, @(12:2, er1) ; Imm8, reg plus 2-bit disp. operand +;;; .word 0x010d +;;; .word 0x31a5 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst-12, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0xa5, @long_dst + beq .Lnext6 + fail +.Lnext6: + mov.l #0, @long_dst ; zero it again for the next use. + +mov_l_imm8_to_disp16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:8, @(dd:16, erd) + mov.l #long_dst-4, er1 + mov.l #0xa5:8, @(4:16, er1) ; Register plus 16-bit disp. operand +;;; .word 0x010d +;;; .word 0x6f90 +;;; .word 0x0004 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst-4, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0xa5, @long_dst + beq .Lnext7 + fail +.Lnext7: + mov.l #0, @long_dst ; zero it again for the next use. + +mov_l_imm8_to_disp32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:8, @(dd:32, erd) + mov.l #long_dst-8, er1 + mov.l #0xa5:8, @(8:32, er1) ; Register plus 32-bit disp. operand +;;; .word 0x010d +;;; .word 0xc9a5 +;;; .long 8 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst-8, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0xa5, @long_dst + beq .Lnext8 + fail +.Lnext8: + mov.l #0, @long_dst ; zero it again for the next use. + +mov_l_imm8_to_abs16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:8, @aa:16 + mov.l #0xa5:8, @long_dst:16 ; 16-bit address-direct operand +;;; .word 0x010d +;;; .word 0x40a5 +;;; .word @long_dst + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed + test_gr_a5a5 1 ; (first, because on h8/300 we must use one + test_gr_a5a5 2 ; to examine the destination memory). + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0xa5, @long_dst + beq .Lnext9 + fail +.Lnext9: + mov.l #0, @long_dst ; zero it again for the next use. + +mov_l_imm8_to_abs32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:8, @aa:32 + mov.l #0xa5:8, @long_dst:32 ; 32-bit address-direct operand +;;; .word 0x010d +;;; .word 0x48a5 +;;; .long @long_dst + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed + test_gr_a5a5 1 ; (first, because on h8/300 we must use one + test_gr_a5a5 2 ; to examine the destination memory). + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0xa5, @long_dst + beq .Lnext10 + fail +.Lnext10: + mov.l #0, @long_dst ; zero it again for the next use. + +mov_l_imm16_to_indirect: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:16, @erd + mov.l #long_dst, er1 + mov.l #0xdead:16, @er1 ; Register indirect operand +;;; .word 0x7a7c +;;; .word 0xdead +;;; .word 0x0100 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0xdead, @long_dst + beq .Lnext11 + fail +.Lnext11: + mov.l #0, @long_dst ; zero it again for the next use. + +mov_l_imm16_to_postinc: ; post-increment from imm16 to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:16, @erd+ + mov.l #long_dst, er1 + mov.l #0xdead:16, @er1+ ; Imm16, register post-incr operands. +;;; .word 0x7a7c +;;; .word 0xdead +;;; .word 0x8100 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst+4, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0xdead, @long_dst + beq .Lnext12 + fail +.Lnext12: + mov.l #0, @long_dst ; zero it again for the next use. + +mov_l_imm16_to_postdec: ; post-decrement from imm16 to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:16, @erd- + mov.l #long_dst, er1 + mov.l #0xdead:16, @er1- ; Imm16, register post-decr operands. +;;; .word 0x7a7c +;;; .word 0xdead +;;; .word 0xa100 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst-4, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0xdead, @long_dst + beq .Lnext13 + fail +.Lnext13: + mov.l #0, @long_dst ; zero it again for the next use. + +mov_l_imm16_to_preinc: ; pre-increment from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:16, @+erd + mov.l #long_dst-4, er1 + mov.l #0xdead:16, @+er1 ; Imm16, register pre-incr operands +;;; .word 0x7a7c +;;; .word 0xdead +;;; .word 0x9100 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0xdead, @long_dst + beq .Lnext14 + fail +.Lnext14: + mov.l #0, @long_dst ; zero it again for the next use. + +mov_l_imm16_to_predec: ; pre-decrement from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:16, @-erd + mov.l #long_dst+4, er1 + mov.l #0xdead:16, @-er1 ; Imm16, register pre-decr operands +;;; .word 0x7a7c +;;; .word 0xdead +;;; .word 0xb100 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0xdead, @long_dst + beq .Lnext15 + fail +.Lnext15: + mov.l #0, @long_dst ; zero it again for the next use. + +mov_l_imm16_to_disp2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:16, @(dd:2, erd) + mov.l #long_dst-12, er1 + mov.l #0xdead:16, @(12:2, er1) ; Imm16, reg plus 2-bit disp. operand +;;; .word 0x7a7c +;;; .word 0xdead +;;; .word 0x3100 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst-12, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0xdead, @long_dst + beq .Lnext16 + fail +.Lnext16: + mov.l #0, @long_dst ; zero it again for the next use. + +mov_l_imm16_to_disp16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:16, @(dd:16, erd) + mov.l #long_dst-4, er1 + mov.l #0xdead:16, @(4:16, er1) ; Register plus 16-bit disp. operand +;;; .word 0x7a7c +;;; .word 0xdead +;;; .word 0xc100 +;;; .word 0x0004 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst-4, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0xdead, @long_dst + beq .Lnext17 + fail +.Lnext17: + mov.l #0, @long_dst ; zero it again for the next use. + +mov_l_imm16_to_disp32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:16, @(dd:32, erd) + mov.l #long_dst-8, er1 + mov.l #0xdead:16, @(8:32, er1) ; Register plus 32-bit disp. operand +;;; .word 0x7a7c +;;; .word 0xdead +;;; .word 0xc900 +;;; .long 8 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst-8, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0xdead, @long_dst + beq .Lnext18 + fail +.Lnext18: + mov.l #0, @long_dst ; zero it again for the next use. + +mov_l_imm16_to_abs16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:16, @aa:16 + mov.l #0xdead:16, @long_dst:16 ; 16-bit address-direct operand +;;; .word 0x7a7c +;;; .word 0xdead +;;; .word 0x4000 +;;; .word @long_dst + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed + test_gr_a5a5 1 ; (first, because on h8/300 we must use one + test_gr_a5a5 2 ; to examine the destination memory). + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0xdead, @long_dst + beq .Lnext19 + fail +.Lnext19: + mov.l #0, @long_dst ; zero it again for the next use. + +mov_l_imm16_to_abs32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:16, @aa:32 + mov.l #0xdead:16, @long_dst:32 ; 32-bit address-direct operand +;;; .word 0x7a7c +;;; .word 0xdead +;;; .word 0x4800 +;;; .long @long_dst + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed + test_gr_a5a5 1 ; (first, because on h8/300 we must use one + test_gr_a5a5 2 ; to examine the destination memory). + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0xdead, @long_dst + beq .Lnext20 + fail +.Lnext20: + mov.l #0, @long_dst ; zero it again for the next use. + +mov_l_imm32_to_indirect: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:32, @erd + mov.l #long_dst, er1 + mov.l #0xcafedead:32, @er1 ; Register indirect operand +;;; .word 0x7a74 +;;; .long 0xcafedead +;;; .word 0x0100 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0xcafedead, @long_dst + beq .Lnext21 + fail +.Lnext21: + mov.l #0, @long_dst ; zero it again for the next use. + +mov_l_imm32_to_postinc: ; post-increment from imm32 to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:32, @erd+ + mov.l #long_dst, er1 + mov.l #0xcafedead:32, @er1+ ; Imm32, register post-incr operands. +;;; .word 0x7a74 +;;; .long 0xcafedead +;;; .word 0x8100 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst+4, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0xcafedead, @long_dst + beq .Lnext22 + fail +.Lnext22: + mov.l #0, @long_dst ; zero it again for the next use. + +mov_l_imm32_to_postdec: ; post-decrement from imm32 to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:32, @erd- + mov.l #long_dst, er1 + mov.l #0xcafedead:32, @er1- ; Imm32, register post-decr operands. +;;; .word 0x7a74 +;;; .long 0xcafedead +;;; .word 0xa100 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst-4, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0xcafedead, @long_dst + beq .Lnext23 + fail +.Lnext23: + mov.l #0, @long_dst ; zero it again for the next use. + +mov_l_imm32_to_preinc: ; pre-increment from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:32, @+erd + mov.l #long_dst-4, er1 + mov.l #0xcafedead:32, @+er1 ; Imm32, register pre-incr operands +;;; .word 0x7a74 +;;; .long 0xcafedead +;;; .word 0x9100 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0xcafedead, @long_dst + beq .Lnext24 + fail +.Lnext24: + mov.l #0, @long_dst ; zero it again for the next use. + +mov_l_imm32_to_predec: ; pre-decrement from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:32, @-erd + mov.l #long_dst+4, er1 + mov.l #0xcafedead:32, @-er1 ; Imm32, register pre-decr operands +;;; .word 0x7a74 +;;; .long 0xcafedead +;;; .word 0xb100 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0xcafedead, @long_dst + beq .Lnext25 + fail +.Lnext25: + mov.l #0, @long_dst ; zero it again for the next use. + +mov_l_imm32_to_disp2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:32, @(dd:2, erd) + mov.l #long_dst-12, er1 + mov.l #0xcafedead:32, @(12:2, er1) ; Imm32, reg plus 2-bit disp. operand +;;; .word 0x7a74 +;;; .long 0xcafedead +;;; .word 0x3100 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst-12, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0xcafedead, @long_dst + beq .Lnext26 + fail +.Lnext26: + mov.l #0, @long_dst ; zero it again for the next use. + +mov_l_imm32_to_disp16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:32, @(dd:16, erd) + mov.l #long_dst-4, er1 + mov.l #0xcafedead:32, @(4:16, er1) ; Register plus 16-bit disp. operand +;;; .word 0x7a74 +;;; .long 0xcafedead +;;; .word 0xc100 +;;; .word 0x0004 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst-4, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0xcafedead, @long_dst + beq .Lnext27 + fail +.Lnext27: + mov.l #0, @long_dst ; zero it again for the next use. + +mov_l_imm32_to_disp32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:32, @(dd:32, erd) + mov.l #long_dst-8, er1 + mov.l #0xcafedead:32, @(8:32, er1) ; Register plus 32-bit disp. operand +;;; .word 0x7a74 +;;; .long 0xcafedead +;;; .word 0xc900 +;;; .long 8 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst-8, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0xcafedead, @long_dst + beq .Lnext28 + fail +.Lnext28: + mov.l #0, @long_dst ; zero it again for the next use. + +mov_l_imm32_to_abs16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:32, @aa:16 + mov.l #0xcafedead:32, @long_dst:16 ; 16-bit address-direct operand +;;; .word 0x7a74 +;;; .long 0xcafedead +;;; .word 0x4000 +;;; .word @long_dst + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed + test_gr_a5a5 1 ; (first, because on h8/300 we must use one + test_gr_a5a5 2 ; to examine the destination memory). + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0xcafedead, @long_dst + beq .Lnext29 + fail +.Lnext29: + mov.l #0, @long_dst ; zero it again for the next use. + +mov_l_imm32_to_abs32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:32, @aa:32 + mov.l #0xcafedead:32, @long_dst:32 ; 32-bit address-direct operand +;;; .word 0x7a74 +;;; .long 0xcafedead +;;; .word 0x4800 +;;; .long @long_dst + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed + test_gr_a5a5 1 ; (first, because on h8/300 we must use one + test_gr_a5a5 2 ; to examine the destination memory). + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0xcafedead, @long_dst + beq .Lnext30 + fail +.Lnext30: + mov.l #0, @long_dst ; zero it again for the next use. + +.endif + + ;; + ;; Move long from register source + ;; + +mov_l_reg32_to_reg32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l ers, erd + mov.l #0x12345678, er1 + mov.l er1, er0 ; Register 32-bit operand +;;; .word 0x0f90 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + test_h_gr32 0x12345678 er0 + test_h_gr32 0x12345678 er1 ; mov src unchanged + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +mov_l_reg32_to_indirect: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l ers, @erd + mov.l #long_dst, er1 + mov.l er0, @er1 ; Register indirect operand +;;; .word 0x0100 +;;; .word 0x6990 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + mov.l #0, er0 + mov.l @long_dst, er0 + cmp.l er2, er0 + beq .Lnext44 + fail +.Lnext44: + mov.l #0, er0 + mov.l er0, @long_dst ; zero it again for the next use. + +.if (sim_cpu == h8sx) +mov_l_reg32_to_postinc: ; post-increment from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l ers, @erd+ + mov.l #long_dst, er1 + mov.l er0, @er1+ ; Register post-incr operand +;;; .word 0x0103 +;;; .word 0x6d90 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst+4, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l er2, @long_dst + beq .Lnext49 + fail +.Lnext49: + mov.l #0, @long_dst ; zero it again for the next use. + +mov_l_reg32_to_postdec: ; post-decrement from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l ers, @erd- + mov.l #long_dst, er1 + mov.l er0, @er1- ; Register post-decr operand +;;; .word 0x0101 +;;; .word 0x6d90 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst-4, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l er2, @long_dst + beq .Lnext50 + fail +.Lnext50: + mov.l #0, @long_dst ; zero it again for the next use. + +mov_l_reg32_to_preinc: ; pre-increment from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l ers, @+erd + mov.l #long_dst-4, er1 + mov.l er0, @+er1 ; Register pre-incr operand +;;; .word 0x0102 +;;; .word 0x6d90 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l er2, @long_dst + beq .Lnext51 + fail +.Lnext51: + mov.l #0, @long_dst ; zero it again for the next use. +.endif ; h8sx + +mov_l_reg32_to_predec: ; pre-decrement from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l ers, @-erd + mov.l #long_dst+4, er1 + mov.l er0, @-er1 ; Register pre-decr operand +;;; .word 0x0100 +;;; .word 0x6d90 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + mov.l #0, er0 + mov.l @long_dst, er0 + cmp.l er2, er0 + beq .Lnext48 + fail +.Lnext48: + mov.l #0, er0 + mov.l er0, @long_dst ; zero it again for the next use. + +.if (sim_cpu == h8sx) +mov_l_reg32_to_disp2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l ers, @(dd:2, erd) + mov.l #long_dst-12, er1 + mov.l er0, @(12:2, er1) ; Register plus 2-bit disp. operand +;;; .word 0x0103 +;;; .word 0x6990 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst-12, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l er2, @long_dst + beq .Lnext52 + fail +.Lnext52: + mov.l #0, @long_dst ; zero it again for the next use. +.endif ; h8sx + +mov_l_reg32_to_disp16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l ers, @(dd:16, erd) + mov.l #long_dst-4, er1 + mov.l er0, @(4:16, er1) ; Register plus 16-bit disp. operand +;;; .word 0x0100 +;;; .word 0x6f90 +;;; .word 0x0004 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 long_dst-4, er1 + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + mov.l #0, er0 + mov.l @long_dst, er0 + cmp.l er2, er0 + beq .Lnext45 + fail +.Lnext45: + mov.l #0, er0 + mov.l er0, @long_dst ; zero it again for the next use. + +mov_l_reg32_to_disp32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l ers, @(dd:32, erd) + mov.l #long_dst-8, er1 + mov.l er0, @(8:32, er1) ; Register plus 32-bit disp. operand +;;; .word 0x7890 +;;; .word 0x6ba0 +;;; .long 8 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 long_dst-8, er1 + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + mov.l #0, er0 + mov.l @long_dst, er0 + cmp.l er2, er0 + beq .Lnext46 + fail +.Lnext46: + mov.l #0, er0 + mov.l er0, @long_dst ; zero it again for the next use. + +mov_l_reg32_to_abs16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l ers, @aa:16 + mov.l er0, @long_dst:16 ; 16-bit address-direct operand +;;; .word 0x0100 +;;; .word 0x6b80 +;;; .word @long_dst + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed + test_gr_a5a5 1 ; (first, because on h8/300 we must use one + test_gr_a5a5 2 ; to examine the destination memory). + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + mov.l #0, er0 + mov.l @long_dst, er0 + cmp.l er0, er1 + beq .Lnext41 + fail +.Lnext41: + mov.l #0, er0 + mov.l er0, @long_dst ; zero it again for the next use. + +mov_l_reg32_to_abs32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l ers, @aa:32 + mov.l er0, @long_dst:32 ; 32-bit address-direct operand +;;; .word 0x0100 +;;; .word 0x6ba0 +;;; .long @long_dst + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed + test_gr_a5a5 1 ; (first, because on h8/300 we must use one + test_gr_a5a5 2 ; to examine the destination memory). + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + mov.l #0, er0 + mov.l @long_dst, er0 + cmp.l er0, er1 + beq .Lnext42 + fail +.Lnext42: + mov.l #0, er0 + mov.l er0, @long_dst ; zero it again for the next use. + + ;; + ;; Move long to register destination. + ;; + +mov_l_indirect_to_reg32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l @ers, erd + mov.l #long_src, er1 + mov.l @er1, er0 ; Register indirect operand +;;; .word 0x0100 +;;; .word 0x6910 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0x77777777 er0 + + test_h_gr32 long_src, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +mov_l_postinc_to_reg32: ; post-increment from mem to register + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l @ers+, erd + + mov.l #long_src, er1 + mov.l @er1+, er0 ; Register post-incr operand +;;; .word 0x0100 +;;; .word 0x6d10 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0x77777777 er0 + + test_h_gr32 long_src+4, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +mov_l_postdec_to_reg32: ; post-decrement from mem to register + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l @ers-, erd + + mov.l #long_src, er1 + mov.l @er1-, er0 ; Register post-decr operand +;;; .word 0x0102 +;;; .word 0x6d10 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0x77777777 er0 + + test_h_gr32 long_src-4, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +mov_l_preinc_to_reg32: ; pre-increment from mem to register + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l @+ers, erd + + mov.l #long_src-4, er1 + mov.l @+er1, er0 ; Register pre-incr operand +;;; .word 0x0101 +;;; .word 0x6d10 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0x77777777 er0 + + test_h_gr32 long_src, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +mov_l_predec_to_reg32: ; pre-decrement from mem to register + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l @-ers, erd + + mov.l #long_src+4, er1 + mov.l @-er1, er0 ; Register pre-decr operand +;;; .word 0x0103 +;;; .word 0x6d10 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0x77777777 er0 + + test_h_gr32 long_src, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + +mov_l_disp2_to_reg32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l @(dd:2, ers), erd + mov.l #long_src-4, er1 + mov.l @(4:2, er1), er0 ; Register plus 2-bit disp. operand +;;; .word 0x0101 +;;; .word 0x6910 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0x77777777 er0 ; mov result: a5a5 | 7777 + + test_h_gr32 long_src-4, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif ; h8sx + +mov_l_disp16_to_reg32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l @(dd:16, ers), erd + mov.l #long_src+0x1234, er1 + mov.l @(-0x1234:16, er1), er0 ; Register plus 16-bit disp. operand +;;; .word 0x0100 +;;; .word 0x6f10 +;;; .word -0x1234 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0x77777777 er0 ; mov result: a5a5 | 7777 + + test_h_gr32 long_src+0x1234, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +mov_l_disp32_to_reg32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l @(dd:32, ers), erd + mov.l #long_src+65536, er1 + mov.l @(-65536:32, er1), er0 ; Register plus 32-bit disp. operand +;;; .word 0x7890 +;;; .word 0x6b20 +;;; .long -65536 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0x77777777 er0 ; mov result: a5a5 | 7777 + + test_h_gr32 long_src+65536, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +mov_l_abs16_to_reg32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l @aa:16, erd + mov.l @long_src:16, er0 ; 16-bit address-direct operand +;;; .word 0x0100 +;;; .word 0x6b00 +;;; .word @long_src + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0x77777777 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +mov_l_abs32_to_reg32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l @aa:32, erd + mov.l @long_src:32, er0 ; 32-bit address-direct operand +;;; .word 0x0100 +;;; .word 0x6b20 +;;; .long @long_src + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0x77777777 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + +.if (sim_cpu == h8sx) + + ;; + ;; Move long from memory to memory + ;; + +mov_l_indirect_to_indirect: ; reg indirect, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l @ers, @erd + + mov.l #long_src, er1 + mov.l #long_dst, er0 + mov.l @er1, @er0 +;;; .word 0x0108 +;;; .word 0x0100 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 long_dst er0 + test_h_gr32 long_src er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l @long_src, @long_dst + beq .Lnext55 + fail +.Lnext55: + ;; Now clear the destination location, and verify that. + mov.l #0, @long_dst + cmp.l @long_src, @long_dst + bne .Lnext56 + fail +.Lnext56: ; OK, pass on. + +mov_l_postinc_to_postinc: ; reg post-increment, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l @ers+, @erd+ + + mov.l #long_src, er1 + mov.l #long_dst, er0 + mov.l @er1+, @er0+ +;;; .word 0x0108 +;;; .word 0x8180 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 long_dst+4 er0 + test_h_gr32 long_src+4 er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l @long_src, @long_dst + beq .Lnext65 + fail +.Lnext65: + ;; Now clear the destination location, and verify that. + mov.l #0, @long_dst + cmp.l @long_src, @long_dst + bne .Lnext66 + fail +.Lnext66: ; OK, pass on. + +mov_l_postdec_to_postdec: ; reg post-decrement, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l @ers-, @erd- + + mov.l #long_src, er1 + mov.l #long_dst, er0 + mov.l @er1-, @er0- +;;; .word 0x0108 +;;; .word 0xa1a0 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 long_dst-4 er0 + test_h_gr32 long_src-4 er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l @long_src, @long_dst + beq .Lnext75 + fail +.Lnext75: + ;; Now clear the destination location, and verify that. + mov.l #0, @long_dst + cmp.l @long_src, @long_dst + bne .Lnext76 + fail +.Lnext76: ; OK, pass on. + +mov_l_preinc_to_preinc: ; reg pre-increment, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l @+ers, @+erd + + mov.l #long_src-4, er1 + mov.l #long_dst-4, er0 + mov.l @+er1, @+er0 +;;; .word 0x0108 +;;; .word 0x9190 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 long_dst er0 + test_h_gr32 long_src er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l @long_src, @long_dst + beq .Lnext85 + fail +.Lnext85: + ;; Now clear the destination location, and verify that. + mov.l #0, @long_dst + cmp.l @long_src, @long_dst + bne .Lnext86 + fail +.Lnext86: ; OK, pass on. + +mov_l_predec_to_predec: ; reg pre-decrement, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l @-ers, @-erd + + mov.l #long_src+4, er1 + mov.l #long_dst+4, er0 + mov.l @-er1, @-er0 +;;; .word 0x0108 +;;; .word 0xb1b0 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 long_dst er0 + test_h_gr32 long_src er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l @long_src, @long_dst + beq .Lnext95 + fail +.Lnext95: + ;; Now clear the destination location, and verify that. + mov.l #0, @long_dst + cmp.l @long_src, @long_dst + bne .Lnext96 + fail +.Lnext96: ; OK, pass on. + +mov_l_disp2_to_disp2: ; reg 2-bit disp, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l @(dd:2, ers), @(dd:2, erd) + + mov.l #long_src-4, er1 + mov.l #long_dst-8, er0 + mov.l @(4:2, er1), @(8:2, er0) +;;; .word 0x0108 +;;; .word 0x1120 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 long_dst-8 er0 + test_h_gr32 long_src-4 er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l @long_src, @long_dst + beq .Lnext105 + fail +.Lnext105: + ;; Now clear the destination location, and verify that. + mov.l #0, @long_dst + cmp.l @long_src, @long_dst + bne .Lnext106 + fail +.Lnext106: ; OK, pass on. + +mov_l_disp16_to_disp16: ; reg 16-bit disp, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l @(dd:16, ers), @(dd:16, erd) + + mov.l #long_src-1, er1 + mov.l #long_dst-2, er0 + mov.l @(1:16, er1), @(2:16, er0) +;;; .word 0x0108 +;;; .word 0xc1c0 +;;; .word 0x0001 +;;; .word 0x0002 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 long_dst-2 er0 + test_h_gr32 long_src-1 er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l @long_src, @long_dst + beq .Lnext115 + fail +.Lnext115: + ;; Now clear the destination location, and verify that. + mov.l #0, @long_dst + cmp.l @long_src, @long_dst + bne .Lnext116 + fail +.Lnext116: ; OK, pass on. + +mov_l_disp32_to_disp32: ; reg 32-bit disp, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l @(dd:32, ers), @(dd:32, erd) + + mov.l #long_src-1, er1 + mov.l #long_dst-2, er0 + mov.l @(1:32, er1), @(2:32, er0) +;;; .word 0x0108 +;;; .word 0xc9c8 +;;; .long 1 +;;; .long 2 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 long_dst-2 er0 + test_h_gr32 long_src-1 er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l @long_src, @long_dst + beq .Lnext125 + fail +.Lnext125: + ;; Now clear the destination location, and verify that. + mov.l #0, @long_dst + cmp.l @long_src, @long_dst + bne .Lnext126 + fail +.Lnext126: ; OK, pass on. + +mov_l_abs16_to_abs16: ; 16-bit absolute addr, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l @aa:16, @aa:16 + + mov.l @long_src:16, @long_dst:16 +;;; .word 0x0108 +;;; .word 0x4040 +;;; .word @long_src +;;; .word @long_dst + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + + test_gr_a5a5 0 ; Make sure *NO* general registers are changed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l @long_src, @long_dst + beq .Lnext135 + fail +.Lnext135: + ;; Now clear the destination location, and verify that. + mov.l #0, @long_dst + cmp.l @long_src, @long_dst + bne .Lnext136 + fail +.Lnext136: ; OK, pass on. + +mov_l_abs32_to_abs32: ; 32-bit absolute addr, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l @aa:32, @aa:32 + + mov.l @long_src:32, @long_dst:32 +;;; .word 0x0108 +;;; .word 0x4848 +;;; .long @long_src +;;; .long @long_dst + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure *NO* general registers are changed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l @long_src, @long_dst + beq .Lnext145 + fail +.Lnext145: + ;; Now clear the destination location, and verify that. + mov.l #0, @long_dst + cmp.l @long_src, @long_dst + bne .Lnext146 + fail +.Lnext146: ; OK, pass on. + + +.endif + + pass + + exit 0 diff --git a/sim/testsuite/sim/h8300/movmd.s b/sim/testsuite/sim/h8300/movmd.s new file mode 100644 index 0000000..fefdc33 --- /dev/null +++ b/sim/testsuite/sim/h8300/movmd.s @@ -0,0 +1,129 @@ +# Hitachi H8 testcase 'movmd' +# mach(): h8sx +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + .data +byte_src: + .byte 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 +byte_dst: + .byte 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 + + .align 2 +word_src: + .word 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 +word_dst: + .word 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 + + .align 4 +long_src: + .long 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 +long_dst: + .long 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 + + start +.if (sim_cpu == h8sx) +movmd_b:# + # Byte block transfer + # + set_grs_a5a5 + + mov #byte_src, er5 + mov #byte_dst, er6 + mov #10, r4 + set_ccr_zero + ;; movmd.b + movmd.b +;;; .word 0x7b94 + + test_cc_clear + test_gr_a5a5 0 + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_h_gr32 0xa5a50000 er4 + test_h_gr32 byte_src+10 er5 + test_h_gr32 byte_dst+10 er6 + test_gr_a5a5 7 + + # + # Now make sure exactly 10 bytes were transferred. + memcmp byte_src byte_dst 10 + cmp.b #0, @byte_dst+10 + beq .L0 + fail +.L0: + +movmd_w:# + # Word block transfer + # + set_grs_a5a5 + + mov #word_src, er5 + mov #word_dst, er6 + mov #10, r4 + set_ccr_zero + ;; movmd.w + movmd.w +;;; .word 0x7ba4 + + test_cc_clear + test_gr_a5a5 0 + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_h_gr32 0xa5a50000 er4 + test_h_gr32 word_src+20 er5 + test_h_gr32 word_dst+20 er6 + test_gr_a5a5 7 + + # + # Now make sure exactly 20 bytes were transferred. + memcmp word_src word_dst 20 + cmp.w #0, @word_dst+20 + beq .L1 + fail +.L1: + +movmd_l:# + # Long block transfer + # + set_grs_a5a5 + + mov #long_src, er5 + mov #long_dst, er6 + mov #10, r4 + set_ccr_zero + ;; movmd.b + movmd.l +;;; .word 0x7bb4 + + test_cc_clear + test_gr_a5a5 0 + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_h_gr32 0xa5a50000 er4 + test_h_gr32 long_src+40 er5 + test_h_gr32 long_dst+40 er6 + test_gr_a5a5 7 + + # + # Now make sure exactly 40 bytes were transferred. + memcmp long_src long_dst 40 + cmp.l #0, @long_dst+40 + beq .L2 + fail +.L2: + +.endif + pass + + exit 0 diff --git a/sim/testsuite/sim/h8300/movsd.s b/sim/testsuite/sim/h8300/movsd.s new file mode 100644 index 0000000..2689c53 --- /dev/null +++ b/sim/testsuite/sim/h8300/movsd.s @@ -0,0 +1,100 @@ +# Hitachi H8 testcase 'movsd' +# mach(): all +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + .data +src: .byte 'h', 'e', 'l', 'l', 'o', 0 +dst1: .byte 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +dst2: .byte 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 + + start +.if (sim_cpu == h8sx) +movsd_n:# + # In this test, the transfer will stop after n bytes. + # + set_grs_a5a5 + + mov #src, er5 + mov #dst1, er6 + mov #4, r4 + set_ccr_zero + ;; movsd.b disp:16 + movsd.b fail1:16 +;;; .word 0x7b84 +;;; .word 0x02 + + bra pass1 +fail1: fail +pass1: test_cc_clear + test_gr_a5a5 0 + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_h_gr32 0xa5a50000 er4 + test_h_gr32 src+4 er5 + test_h_gr32 dst1+4 er6 + test_gr_a5a5 7 + + # + # Now make sure exactly 4 bytes were transferred. + cmp.b @src, @dst1 + bne fail1:16 + cmp.b @src+1, @dst1+1 + bne fail1:16 + cmp.b @src+2, @dst1+2 + bne fail1:16 + cmp.b @src+3, @dst1+3 + bne fail1:16 + cmp.b @src+4, @dst1+4 + beq fail1:16 + +movsd_s:# + # In this test, the entire null-terminated string is transferred. + # + set_grs_a5a5 + + mov #src, er5 + mov #dst2, er6 + mov #8, r4 + set_ccr_zero + ;; movsd.b disp:16 + movsd.b pass2:16 +;;; .word 0x7b84 +;;; .word 0x10 + +fail2: fail +pass2: test_cc_clear + test_gr_a5a5 0 + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_h_gr32 0xa5a50002 er4 + test_h_gr32 src+6 er5 + test_h_gr32 dst2+6 er6 + test_gr_a5a5 7 + # + # Now make sure 5 bytes were transferred, and the 6th is zero. + cmp.b @src, @dst2 + bne fail2:16 + cmp.b @src+1, @dst2+1 + bne fail2:16 + cmp.b @src+2, @dst2+2 + bne fail2:16 + cmp.b @src+3, @dst2+3 + bne fail2:16 + cmp.b @src+4, @dst2+4 + bne fail2:16 + cmp.b #0, @dst2+5 + bne fail2:16 +.endif + pass + + exit 0 diff --git a/sim/testsuite/sim/h8300/movw.s b/sim/testsuite/sim/h8300/movw.s new file mode 100644 index 0000000..b8b09ea --- /dev/null +++ b/sim/testsuite/sim/h8300/movw.s @@ -0,0 +1,1857 @@ +# Hitachi H8 testcase 'mov.w' +# mach(): h8300h h8300s h8sx +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + start + + .data + .align 2 +word_src: + .word 0x7777 +word_dst: + .word 0 + + .text + + ;; + ;; Move word from immediate source + ;; + +.if (sim_cpu == h8sx) +mov_w_imm3_to_reg16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w #xx:3, rd + mov.w #0x3:3, r0 ; Immediate 3-bit operand +;;; .word 0x0f30 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a50003 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif + +mov_w_imm16_to_reg16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w #xx:16, rd + mov.w #0x1234, r0 ; Immediate 16-bit operand +;;; .word 0x7900 +;;; .word 0x1234 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a51234 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +mov_w_imm4_to_abs16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w #xx:4, @aa:16 + mov.w #0xf:4, @word_dst:16 ; 4-bit imm to 16-bit address-direct +;;; .word 0x6bdf +;;; .word @word_dst + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed + test_gr_a5a5 1 ; (first, because on h8/300 we must use one + test_gr_a5a5 2 ; to examine the destination memory). + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w #0xf, @word_dst + beq .Lnext21 + fail +.Lnext21: + mov.w #0, @word_dst ; zero it again for the next use. + +mov_w_imm4_to_abs32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w #xx:4, @aa:32 + mov.w #0xf:4, @word_dst:32 ; 4-bit imm to 32-bit address-direct +;;; .word 0x6bff +;;; .long @word_dst + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed + test_gr_a5a5 1 ; (first, because on h8/300 we must use one + test_gr_a5a5 2 ; to examine the destination memory). + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w #0xf, @word_dst + beq .Lnext22 + fail +.Lnext22: + mov.w #0, @word_dst ; zero it again for the next use. + +mov_w_imm8_to_indirect: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w #xx:8, @erd + mov.l #word_dst, er1 + mov.w #0xa5:8, @er1 ; Register indirect operand +;;; .word 0x015d +;;; .word 0x01a5 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 word_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w #0xa5, @word_dst + beq .Lnext1 + fail +.Lnext1: + mov.w #0, @word_dst ; zero it again for the next use. + +mov_w_imm8_to_postinc: ; post-increment from imm8 to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w #xx:8, @erd+ + mov.l #word_dst, er1 + mov.w #0xa5:8, @er1+ ; Imm8, register post-incr operands. +;;; .word 0x015d +;;; .word 0x81a5 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 word_dst+2, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w #0xa5, @word_dst + beq .Lnext2 + fail +.Lnext2: + mov.w #0, @word_dst ; zero it again for the next use. + +mov_w_imm8_to_postdec: ; post-decrement from imm8 to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w #xx:8, @erd- + mov.l #word_dst, er1 + mov.w #0xa5:8, @er1- ; Imm8, register post-decr operands. +;;; .word 0x015d +;;; .word 0xa1a5 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 word_dst-2, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w #0xa5, @word_dst + beq .Lnext3 + fail +.Lnext3: + mov.w #0, @word_dst ; zero it again for the next use. + +mov_w_imm8_to_preinc: ; pre-increment from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w #xx:8, @+erd + mov.l #word_dst-2, er1 + mov.w #0xa5:8, @+er1 ; Imm8, register pre-incr operands +;;; .word 0x015d +;;; .word 0x91a5 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 word_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w #0xa5, @word_dst + beq .Lnext4 + fail +.Lnext4: + mov.w #0, @word_dst ; zero it again for the next use. + +mov_w_imm8_to_predec: ; pre-decrement from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w #xx:8, @-erd + mov.l #word_dst+2, er1 + mov.w #0xa5:8, @-er1 ; Imm8, register pre-decr operands +;;; .word 0x015d +;;; .word 0xb1a5 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 word_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w #0xa5, @word_dst + beq .Lnext5 + fail +.Lnext5: + mov.w #0, @word_dst ; zero it again for the next use. + +mov_w_imm8_to_disp2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w #xx:8, @(dd:2, erd) + mov.l #word_dst-6, er1 + mov.w #0xa5:8, @(6:2, er1) ; Imm8, reg plus 2-bit disp. operand +;;; .word 0x015d +;;; .word 0x31a5 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 word_dst-6, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w #0xa5, @word_dst + beq .Lnext6 + fail +.Lnext6: + mov.w #0, @word_dst ; zero it again for the next use. + +mov_w_imm8_to_disp16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w #xx:8, @(dd:16, erd) + mov.l #word_dst-4, er1 + mov.w #0xa5:8, @(4:16, er1) ; Register plus 16-bit disp. operand +;;; .word 0x015d +;;; .word 0x6f90 +;;; .word 0x0004 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 word_dst-4, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w #0xa5, @word_dst + beq .Lnext7 + fail +.Lnext7: + mov.w #0, @word_dst ; zero it again for the next use. + +mov_w_imm8_to_disp32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w #xx:8, @(dd:32, erd) + mov.l #word_dst-8, er1 + mov.w #0xa5:8, @(8:32, er1) ; Register plus 32-bit disp. operand +;;; .word 0x015d +;;; .word 0xc9a5 +;;; .long 8 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 word_dst-8, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w #0xa5, @word_dst + beq .Lnext8 + fail +.Lnext8: + mov.w #0, @word_dst ; zero it again for the next use. + +mov_w_imm8_to_abs16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w #xx:8, @aa:16 + mov.w #0xa5:8, @word_dst:16 ; 16-bit address-direct operand +;;; .word 0x015d +;;; .word 0x40a5 +;;; .word @word_dst + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed + test_gr_a5a5 1 ; (first, because on h8/300 we must use one + test_gr_a5a5 2 ; to examine the destination memory). + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w #0xa5, @word_dst + beq .Lnext9 + fail +.Lnext9: + mov.w #0, @word_dst ; zero it again for the next use. + +mov_w_imm8_to_abs32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w #xx:8, @aa:32 + mov.w #0xa5:8, @word_dst:32 ; 32-bit address-direct operand +;;; .word 0x015d +;;; .word 0x48a5 +;;; .long @word_dst + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed + test_gr_a5a5 1 ; (first, because on h8/300 we must use one + test_gr_a5a5 2 ; to examine the destination memory). + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w #0xa5, @word_dst + beq .Lnext10 + fail +.Lnext10: + mov.w #0, @word_dst ; zero it again for the next use. + +mov_w_imm16_to_indirect: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w #xx:16, @erd + mov.l #word_dst, er1 + mov.w #0xdead:16, @er1 ; Register indirect operand +;;; .word 0x7974 +;;; .word 0xdead +;;; .word 0x0100 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 word_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w #0xdead, @word_dst + beq .Lnext11 + fail +.Lnext11: + mov.w #0, @word_dst ; zero it again for the next use. + +mov_w_imm16_to_postinc: ; post-increment from imm16 to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w #xx:16, @erd+ + mov.l #word_dst, er1 + mov.w #0xdead:16, @er1+ ; Imm16, register post-incr operands. +;;; .word 0x7974 +;;; .word 0xdead +;;; .word 0x8100 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 word_dst+2, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w #0xdead, @word_dst + beq .Lnext12 + fail +.Lnext12: + mov.w #0, @word_dst ; zero it again for the next use. + +mov_w_imm16_to_postdec: ; post-decrement from imm16 to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w #xx:16, @erd- + mov.l #word_dst, er1 + mov.w #0xdead:16, @er1- ; Imm16, register post-decr operands. +;;; .word 0x7974 +;;; .word 0xdead +;;; .word 0xa100 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 word_dst-2, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w #0xdead, @word_dst + beq .Lnext13 + fail +.Lnext13: + mov.w #0, @word_dst ; zero it again for the next use. + +mov_w_imm16_to_preinc: ; pre-increment from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w #xx:16, @+erd + mov.l #word_dst-2, er1 + mov.w #0xdead:16, @+er1 ; Imm16, register pre-incr operands +;;; .word 0x7974 +;;; .word 0xdead +;;; .word 0x9100 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 word_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w #0xdead, @word_dst + beq .Lnext14 + fail +.Lnext14: + mov.w #0, @word_dst ; zero it again for the next use. + +mov_w_imm16_to_predec: ; pre-decrement from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w #xx:16, @-erd + mov.l #word_dst+2, er1 + mov.w #0xdead:16, @-er1 ; Imm16, register pre-decr operands +;;; .word 0x7974 +;;; .word 0xdead +;;; .word 0xb100 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 word_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w #0xdead, @word_dst + beq .Lnext15 + fail +.Lnext15: + mov.w #0, @word_dst ; zero it again for the next use. + +mov_w_imm16_to_disp2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w #xx:16, @(dd:2, erd) + mov.l #word_dst-6, er1 + mov.w #0xdead:16, @(6:2, er1) ; Imm16, reg plus 2-bit disp. operand +;;; .word 0x7974 +;;; .word 0xdead +;;; .word 0x3100 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 word_dst-6, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w #0xdead, @word_dst + beq .Lnext16 + fail +.Lnext16: + mov.w #0, @word_dst ; zero it again for the next use. + +mov_w_imm16_to_disp16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w #xx:16, @(dd:16, erd) + mov.l #word_dst-4, er1 + mov.w #0xdead:16, @(4:16, er1) ; Register plus 16-bit disp. operand +;;; .word 0x7974 +;;; .word 0xdead +;;; .word 0xc100 +;;; .word 0x0004 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 word_dst-4, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w #0xdead, @word_dst + beq .Lnext17 + fail +.Lnext17: + mov.w #0, @word_dst ; zero it again for the next use. + +mov_w_imm16_to_disp32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w #xx:16, @(dd:32, erd) + mov.l #word_dst-8, er1 + mov.w #0xdead:16, @(8:32, er1) ; Register plus 32-bit disp. operand +;;; .word 0x7974 +;;; .word 0xdead +;;; .word 0xc900 +;;; .long 8 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 word_dst-8, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w #0xdead, @word_dst + beq .Lnext18 + fail +.Lnext18: + mov.w #0, @word_dst ; zero it again for the next use. + +mov_w_imm16_to_abs16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w #xx:16, @aa:16 + mov.w #0xdead:16, @word_dst:16 ; 16-bit address-direct operand +;;; .word 0x7974 +;;; .word 0xdead +;;; .word 0x4000 +;;; .word @word_dst + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed + test_gr_a5a5 1 ; (first, because on h8/300 we must use one + test_gr_a5a5 2 ; to examine the destination memory). + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w #0xdead, @word_dst + beq .Lnext19 + fail +.Lnext19: + mov.w #0, @word_dst ; zero it again for the next use. + +mov_w_imm16_to_abs32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w #xx:16, @aa:32 + mov.w #0xdead:16, @word_dst:32 ; 32-bit address-direct operand +;;; .word 0x7974 +;;; .word 0xdead +;;; .word 0x4800 +;;; .long @word_dst + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed + test_gr_a5a5 1 ; (first, because on h8/300 we must use one + test_gr_a5a5 2 ; to examine the destination memory). + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w #0xdead, @word_dst + beq .Lnext20 + fail +.Lnext20: + mov.w #0, @word_dst ; zero it again for the next use. +.endif + + ;; + ;; Move word from register source + ;; + +mov_w_reg16_to_reg16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w ers, erd + mov.w #0x1234, r1 + mov.w r1, r0 ; Register 16-bit operand +;;; .word 0x0d10 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + test_h_gr16 0x1234 r0 + test_h_gr16 0x1234 r1 ; mov src unchanged +.if (sim_cpu) + test_h_gr32 0xa5a51234 er0 + test_h_gr32 0xa5a51234 er1 ; mov src unchanged +.endif + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + +mov_w_reg16_to_indirect: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w ers, @erd + mov.l #word_dst, er1 + mov.w r0, @er1 ; Register indirect operand +;;; .word 0x6990 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 word_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + mov.w #0, r0 + mov.w @word_dst, r0 + cmp.w r2, r0 + beq .Lnext44 + fail +.Lnext44: + mov.w #0, r0 + mov.w r0, @word_dst ; zero it again for the next use. + +.if (sim_cpu == h8sx) +mov_w_reg16_to_postinc: ; post-increment from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w ers, @erd+ + mov.l #word_dst, er1 + mov.w r0, @er1+ ; Register post-incr operand +;;; .word 0x0153 +;;; .word 0x6d90 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 word_dst+2, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w r2, @word_dst + beq .Lnext49 + fail +.Lnext49: + mov.w #0, @word_dst ; zero it again for the next use. + +mov_w_reg16_to_postdec: ; post-decrement from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w ers, @erd- + mov.l #word_dst, er1 + mov.w r0, @er1- ; Register post-decr operand +;;; .word 0x0151 +;;; .word 0x6d90 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 word_dst-2, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w r2, @word_dst + beq .Lnext50 + fail +.Lnext50: + mov.w #0, @word_dst ; zero it again for the next use. + +mov_w_reg16_to_preinc: ; pre-increment from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w ers, @+erd + mov.l #word_dst-2, er1 + mov.w r0, @+er1 ; Register pre-incr operand +;;; .word 0x0152 +;;; .word 0x6d90 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 word_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w r2, @word_dst + beq .Lnext51 + fail +.Lnext51: + mov.w #0, @word_dst ; zero it again for the next use. +.endif + +mov_w_reg16_to_predec: ; pre-decrement from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w ers, @-erd + mov.l #word_dst+2, er1 + mov.w r0, @-er1 ; Register pre-decr operand +;;; .word 0x6d90 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 word_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + mov.w #0, r0 + mov.w @word_dst, r0 + cmp.w r2, r0 + beq .Lnext48 + fail +.Lnext48: + mov.w #0, r0 + mov.w r0, @word_dst ; zero it again for the next use. + +.if (sim_cpu == h8sx) +mov_w_reg16_to_disp2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w ers, @(dd:2, erd) + mov.l #word_dst-6, er1 + mov.w r0, @(6:2, er1) ; Register plus 2-bit disp. operand +;;; .word 0x0153 +;;; .word 0x6990 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 word_dst-6, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w r2, @word_dst + beq .Lnext52 + fail +.Lnext52: + mov.w #0, @word_dst ; zero it again for the next use. +.endif + +mov_w_reg16_to_disp16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w ers, @(dd:16, erd) + mov.l #word_dst-4, er1 + mov.w r0, @(4:16, er1) ; Register plus 16-bit disp. operand +;;; .word 0x6f90 +;;; .word 0x0004 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 word_dst-4, er1 + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + mov.w #0, r0 + mov.w @word_dst, r0 + cmp.w r2, r0 + beq .Lnext45 + fail +.Lnext45: + mov.w #0, r0 + mov.w r0, @word_dst ; zero it again for the next use. + +mov_w_reg16_to_disp32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w ers, @(dd:32, erd) + mov.l #word_dst-8, er1 + mov.w r0, @(8:32, er1) ; Register plus 32-bit disp. operand +;;; .word 0x7810 +;;; .word 0x6ba0 +;;; .long 8 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 word_dst-8, er1 + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + mov.w #0, r0 + mov.w @word_dst, r0 + cmp.w r2, r0 + beq .Lnext46 + fail +.Lnext46: + mov.w #0, r0 + mov.w r0, @word_dst ; zero it again for the next use. + +mov_w_reg16_to_abs16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w ers, @aa:16 + mov.w r0, @word_dst:16 ; 16-bit address-direct operand +;;; .word 0x6b80 +;;; .word @word_dst + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed + test_gr_a5a5 1 ; (first, because on h8/300 we must use one + test_gr_a5a5 2 ; to examine the destination memory). + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + mov.w #0, r0 + mov.w @word_dst, r0 + cmp.w r0, r1 + beq .Lnext41 + fail +.Lnext41: + mov.w #0, r0 + mov.w r0, @word_dst ; zero it again for the next use. + +mov_w_reg16_to_abs32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w ers, @aa:32 + mov.w r0, @word_dst:32 ; 32-bit address-direct operand +;;; .word 0x6ba0 +;;; .long @word_dst + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed + test_gr_a5a5 1 ; (first, because on h8/300 we must use one + test_gr_a5a5 2 ; to examine the destination memory). + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + mov.w #0, r0 + mov.w @word_dst, r0 + cmp.w r0, r1 + beq .Lnext42 + fail +.Lnext42: + mov.w #0, r0 + mov.w r0, @word_dst ; zero it again for the next use. + + ;; + ;; Move word to register destination. + ;; + +mov_w_indirect_to_reg16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w @ers, rd + mov.l #word_src, er1 + mov.w @er1, r0 ; Register indirect operand +;;; .word 0x6910 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a57777 er0 + + test_h_gr32 word_src, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +mov_w_postinc_to_reg16: ; post-increment from mem to register + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w @ers+, rd + + mov.l #word_src, er1 + mov.w @er1+, r0 ; Register post-incr operand +;;; .word 0x6d10 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a57777 er0 + + test_h_gr32 word_src+2, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +mov_w_postdec_to_reg16: ; post-decrement from mem to register + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w @ers-, rd + + mov.l #word_src, er1 + mov.w @er1-, r0 ; Register post-decr operand +;;; .word 0x0152 +;;; .word 0x6d10 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a57777 er0 + + test_h_gr32 word_src-2, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +mov_w_preinc_to_reg16: ; pre-increment from mem to register + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w @+ers, rd + + mov.l #word_src-2, er1 + mov.w @+er1, r0 ; Register pre-incr operand +;;; .word 0x0151 +;;; .word 0x6d10 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a57777 er0 + + test_h_gr32 word_src, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +mov_w_predec_to_reg16: ; pre-decrement from mem to register + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w @-ers, rd + + mov.l #word_src+2, er1 + mov.w @-er1, r0 ; Register pre-decr operand +;;; .word 0x0153 +;;; .word 0x6d10 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a57777 er0 + + test_h_gr32 word_src, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + +mov_w_disp2_to_reg16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w @(dd:2, ers), rd + mov.l #word_src-2, er1 + mov.w @(2:2, er1), r0 ; Register plus 2-bit disp. operand +;;; .word 0x0151 +;;; .word 0x6910 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a57777 er0 ; mov result: a5a5 | 7777 + + test_h_gr32 word_src-2, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif + +mov_w_disp16_to_reg16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w @(dd:16, ers), rd + mov.l #word_src+0x1234, er1 + mov.w @(-0x1234:16, er1), r0 ; Register plus 16-bit disp. operand +;;; .word 0x6f10 +;;; .word -0x1234 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a57777 er0 ; mov result: a5a5 | 7777 + + test_h_gr32 word_src+0x1234, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +mov_w_disp32_to_reg16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w @(dd:32, ers), rd + mov.l #word_src+65536, er1 + mov.w @(-65536:32, er1), r0 ; Register plus 32-bit disp. operand +;;; .word 0x7810 +;;; .word 0x6b20 +;;; .long -65536 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a57777 er0 ; mov result: a5a5 | 7777 + + test_h_gr32 word_src+65536, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +mov_w_abs16_to_reg16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w @aa:16, rd + mov.w @word_src:16, r0 ; 16-bit address-direct operand +;;; .word 0x6b00 +;;; .word @word_src + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a57777 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +mov_w_abs32_to_reg16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w @aa:32, rd + mov.w @word_src:32, r0 ; 32-bit address-direct operand +;;; .word 0x6b20 +;;; .long @word_src + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a57777 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) + + ;; + ;; Move word from memory to memory + ;; + +mov_w_indirect_to_indirect: ; reg indirect, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w @ers, @erd + + mov.l #word_src, er1 + mov.l #word_dst, er0 + mov.w @er1, @er0 +;;; .word 0x0158 +;;; .word 0x0100 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 word_dst er0 + test_h_gr32 word_src er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w @word_src, @word_dst + beq .Lnext55 + fail +.Lnext55: + ;; Now clear the destination location, and verify that. + mov.w #0, @word_dst + cmp.w @word_src, @word_dst + bne .Lnext56 + fail +.Lnext56: ; OK, pass on. + +mov_w_postinc_to_postinc: ; reg post-increment, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w @ers+, @erd+ + + mov.l #word_src, er1 + mov.l #word_dst, er0 + mov.w @er1+, @er0+ +;;; .word 0x0158 +;;; .word 0x8180 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 word_dst+2 er0 + test_h_gr32 word_src+2 er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w @word_src, @word_dst + beq .Lnext65 + fail +.Lnext65: + ;; Now clear the destination location, and verify that. + mov.w #0, @word_dst + cmp.w @word_src, @word_dst + bne .Lnext66 + fail +.Lnext66: ; OK, pass on. + +mov_w_postdec_to_postdec: ; reg post-decrement, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w @ers-, @erd- + + mov.l #word_src, er1 + mov.l #word_dst, er0 + mov.w @er1-, @er0- +;;; .word 0x0158 +;;; .word 0xa1a0 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 word_dst-2 er0 + test_h_gr32 word_src-2 er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w @word_src, @word_dst + beq .Lnext75 + fail +.Lnext75: + ;; Now clear the destination location, and verify that. + mov.w #0, @word_dst + cmp.w @word_src, @word_dst + bne .Lnext76 + fail +.Lnext76: ; OK, pass on. + +mov_w_preinc_to_preinc: ; reg pre-increment, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w @+ers, @+erd + + mov.l #word_src-2, er1 + mov.l #word_dst-2, er0 + mov.w @+er1, @+er0 +;;; .word 0x0158 +;;; .word 0x9190 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 word_dst er0 + test_h_gr32 word_src er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w @word_src, @word_dst + beq .Lnext85 + fail +.Lnext85: + ;; Now clear the destination location, and verify that. + mov.w #0, @word_dst + cmp.w @word_src, @word_dst + bne .Lnext86 + fail +.Lnext86: ; OK, pass on. + +mov_w_predec_to_predec: ; reg pre-decrement, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w @-ers, @-erd + + mov.l #word_src+2, er1 + mov.l #word_dst+2, er0 + mov.w @-er1, @-er0 +;;; .word 0x0158 +;;; .word 0xb1b0 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 word_dst er0 + test_h_gr32 word_src er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w @word_src, @word_dst + beq .Lnext95 + fail +.Lnext95: + ;; Now clear the destination location, and verify that. + mov.w #0, @word_dst + cmp.w @word_src, @word_dst + bne .Lnext96 + fail +.Lnext96: ; OK, pass on. + +mov_w_disp2_to_disp2: ; reg 2-bit disp, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w @(dd:2, ers), @(dd:2, erd) + + mov.l #word_src-2, er1 + mov.l #word_dst-4, er0 + mov.w @(2:2, er1), @(4:2, er0) +;;; .word 0x0158 +;;; .word 0x1120 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 word_dst-4 er0 + test_h_gr32 word_src-2 er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w @word_src, @word_dst + beq .Lnext105 + fail +.Lnext105: + ;; Now clear the destination location, and verify that. + mov.w #0, @word_dst + cmp.w @word_src, @word_dst + bne .Lnext106 + fail +.Lnext106: ; OK, pass on. + +mov_w_disp16_to_disp16: ; reg 16-bit disp, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w @(dd:16, ers), @(dd:16, erd) + + mov.l #word_src-1, er1 + mov.l #word_dst-2, er0 + mov.w @(1:16, er1), @(2:16, er0) +;;; .word 0x0158 +;;; .word 0xc1c0 +;;; .word 0x0001 +;;; .word 0x0002 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 word_dst-2 er0 + test_h_gr32 word_src-1 er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w @word_src, @word_dst + beq .Lnext115 + fail +.Lnext115: + ;; Now clear the destination location, and verify that. + mov.w #0, @word_dst + cmp.w @word_src, @word_dst + bne .Lnext116 + fail +.Lnext116: ; OK, pass on. + +mov_w_disp32_to_disp32: ; reg 32-bit disp, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w @(dd:32, ers), @(dd:32, erd) + + mov.l #word_src-1, er1 + mov.l #word_dst-2, er0 + mov.w @(1:32, er1), @(2:32, er0) +;;; .word 0x0158 +;;; .word 0xc9c8 +;;; .long 1 +;;; .long 2 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 word_dst-2 er0 + test_h_gr32 word_src-1 er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w @word_src, @word_dst + beq .Lnext125 + fail +.Lnext125: + ;; Now clear the destination location, and verify that. + mov.w #0, @word_dst + cmp.w @word_src, @word_dst + bne .Lnext126 + fail +.Lnext126: ; OK, pass on. + +mov_w_abs16_to_abs16: ; 16-bit absolute addr, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w @aa:16, @aa:16 + + mov.w @word_src:16, @word_dst:16 +;;; .word 0x0158 +;;; .word 0x4040 +;;; .word @word_src +;;; .word @word_dst + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + + test_gr_a5a5 0 ; Make sure *NO* general registers are changed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w @word_src, @word_dst + beq .Lnext135 + fail +.Lnext135: + ;; Now clear the destination location, and verify that. + mov.w #0, @word_dst + cmp.w @word_src, @word_dst + bne .Lnext136 + fail +.Lnext136: ; OK, pass on. + +mov_w_abs32_to_abs32: ; 32-bit absolute addr, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w @aa:32, @aa:32 + + mov.w @word_src:32, @word_dst:32 +;;; .word 0x0158 +;;; .word 0x4848 +;;; .long @word_src +;;; .long @word_dst + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure *NO* general registers are changed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w @word_src, @word_dst + beq .Lnext145 + fail +.Lnext145: + ;; Now clear the destination location, and verify that. + mov.w #0, @word_dst + cmp.w @word_src, @word_dst + bne .Lnext146 + fail +.Lnext146: ; OK, pass on. + + +.endif + + pass + + exit 0 diff --git a/sim/testsuite/sim/h8300/mul.s b/sim/testsuite/sim/h8300/mul.s new file mode 100644 index 0000000..70ab7ec --- /dev/null +++ b/sim/testsuite/sim/h8300/mul.s @@ -0,0 +1,474 @@ +# Hitachi H8 testcase 'muls', 'muls/u', mulu', 'mulu/u', 'mulxs', 'mulxu' +# mach(): all +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + start + +.if (sim_cpu == h8sx) +muls_w_reg_reg: + set_grs_a5a5 + + ;; muls.w rs, rd + mov.w #32, r1 + mov.w #-2, r2 + set_ccr_zero + muls.w r2, r1 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_carry_clear + test_zero_clear + test_ovf_clear + + test_gr_a5a5 0 + test_h_gr16 -64 r1 + test_h_gr32 0xa5a5fffe er2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +muls_w_imm4_reg: + set_grs_a5a5 + + ;; muls.w xx:4, rd + mov.w #32, r1 + set_ccr_zero + muls.w #-2:4, r1 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_carry_clear + test_zero_clear + test_ovf_clear + + test_gr_a5a5 0 + test_h_gr16 -64 r1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +muls_l_reg_reg: + set_grs_a5a5 + + ;; muls.l ers, erd + mov.l #320000, er1 + mov.l #-2, er2 + set_ccr_zero + muls.l er2, er1 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_carry_clear + test_zero_clear + test_ovf_clear + + test_gr_a5a5 0 + test_h_gr32 -640000 er1 + test_h_gr32 -2 er2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +muls_l_imm4_reg: + set_grs_a5a5 + + ;; muls.l xx:4, rd + mov.l #320000, er1 + set_ccr_zero + muls.l #-2:4, er1 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_carry_clear + test_zero_clear + test_ovf_clear + + test_gr_a5a5 0 + test_h_gr32 -640000 er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +muls_u_l_reg_reg: + set_grs_a5a5 + + ;; muls/u.l ers, erd + mov.l #0x10000000, er1 + mov.l #-16, er2 + set_ccr_zero + muls/u.l er2, er1 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_carry_clear + test_zero_clear + test_ovf_clear + + test_gr_a5a5 0 + test_h_gr32 -1 er1 + test_h_gr32 -16 er2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +muls_u_l_imm4_reg: + set_grs_a5a5 + + ;; muls/u.l xx:4, rd + mov.l #0xffffffff, er1 + set_ccr_zero + muls/u.l #2:4, er1 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_carry_clear + test_zero_clear + test_ovf_clear + + test_gr_a5a5 0 + test_h_gr32 -1 er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +mulu_w_reg_reg: + set_grs_a5a5 + + ;; mulu.w rs, rd + mov.w #32, r1 + mov.w #-2, r2 + set_ccr_zero + mulu.w r2, r1 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_gr_a5a5 0 + test_h_gr16 -64 r1 + test_h_gr32 0xa5a5fffe er2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +mulu_w_imm4_reg: + set_grs_a5a5 + + ;; mulu.w xx:4, rd + mov.w #32, r1 + set_ccr_zero + mulu.w #-2:4, r1 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_gr_a5a5 0 + test_h_gr16 0x1c0 r1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +mulu_l_reg_reg: + set_grs_a5a5 + + ;; mulu.l ers, erd + mov.l #320000, er1 + mov.l #-2, er2 + set_ccr_zero + mulu.l er2, er1 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_gr_a5a5 0 + test_h_gr32 -640000 er1 + test_h_gr32 -2 er2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +mulu_l_imm4_reg: + set_grs_a5a5 + + ;; mulu.l xx:4, rd + mov.l #320000, er1 + set_ccr_zero + mulu.l #-2:4, er1 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_gr_a5a5 0 + test_h_gr32 0x445c00 er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +mulu_u_l_reg_reg: + set_grs_a5a5 + + ;; mulu/u.l ers, erd + mov.l #0x10000000, er1 + mov.l #16, er2 + set_ccr_zero + mulu/u.l er2, er1 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_gr_a5a5 0 + test_h_gr32 1 er1 + test_h_gr32 16 er2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +mulu_u_l_imm4_reg: + set_grs_a5a5 + + ;; mulu/u.l xx:4, rd + mov.l #0xffffffff, er1 + set_ccr_zero + mulu/u.l #2:4, er1 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_gr_a5a5 0 + test_h_gr32 0x1 er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif + +.if (sim_cpu) ; not equal to zero ie. not h8 +mulxs_b_reg_reg: + set_grs_a5a5 + + ;; mulxs.b rs, rd + mov.b #32, r1l + mov.b #-2, r2l + set_ccr_zero + mulxs.b r2l, r1 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_carry_clear + test_zero_clear + test_ovf_clear + + test_gr_a5a5 0 + test_h_gr16 -64 r1 + test_h_gr32 0xa5a5a5fe er2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +mulxs_b_imm4_reg: + set_grs_a5a5 + + ;; mulxs.b xx:4, rd + mov.w #32, r1 + set_ccr_zero + mulxs.b #-2:4, r1 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_carry_clear + test_zero_clear + test_ovf_clear + + test_gr_a5a5 0 + test_h_gr16 -64 r1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif ; h8sx + +mulxs_w_reg_reg: + set_grs_a5a5 + + ;; mulxs.w ers, erd + mov.w #0x1000, r1 + mov.w #-0x1000, r2 + set_ccr_zero + mulxs.w r2, er1 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_carry_clear + test_zero_clear + test_ovf_clear + + test_gr_a5a5 0 + test_h_gr32 0xff000000 er1 + test_h_gr32 0xa5a5f000 er2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +mulxs_w_imm4_reg: + set_grs_a5a5 + + ;; mulxs.w xx:4, rd + mov.w #-1, r1 + set_ccr_zero + mulxs.w #2:4, er1 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_carry_clear + test_zero_clear + test_ovf_clear + + test_gr_a5a5 0 + test_h_gr32 -2 er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif ; h8sx +.endif ; not h8 + +mulxu_b_reg_reg: + set_grs_a5a5 + + ;; mulxu.b rs, rd + mov.b #32, r1l + mov.b #-2, r2l + set_ccr_zero + mulxu.b r2l, r1 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_gr_a5a5 0 + test_h_gr16 0x1fc0 r1 + test_h_gr16 0xa5fe r2 +.if (sim_cpu) + test_h_gr32 0xa5a5a5fe er2 +.endif + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu) ; not h8 +.if (sim_cpu == h8sx) +mulxu_b_imm4_reg: + set_grs_a5a5 + + ;; mulxu.b xx:4, rd + mov.b #32, r1l + set_ccr_zero + mulxu.b #-2:4, r1 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_gr_a5a5 0 + test_h_gr16 0x1c0 r1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif ; h8sx + +mulxu_w_reg_reg: + set_grs_a5a5 + + ;; mulxu.w ers, erd + mov.w #0x1000, r1 + mov.w #-0x1000, r2 + set_ccr_zero + mulxu.w r2, er1 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_gr_a5a5 0 + test_h_gr32 0x0f000000 er1 + test_h_gr32 0xa5a5f000 er2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +mulxu_w_imm4_reg: + set_grs_a5a5 + + ;; mulxu.w xx:4, rd + mov.w #-1, r1 + set_ccr_zero + mulxu.w #2:4, er1 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_gr_a5a5 0 + test_h_gr32 0x1fffe er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif ; h8sx +.endif ; not h8 + + pass + + exit 0 diff --git a/sim/testsuite/sim/h8300/neg.s b/sim/testsuite/sim/h8300/neg.s new file mode 100644 index 0000000..de82476 --- /dev/null +++ b/sim/testsuite/sim/h8300/neg.s @@ -0,0 +1,1022 @@ +# Hitachi H8 testcase 'neg.b, neg.w, neg.l' +# mach(): all +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + # Instructions tested: + # neg.b rd ; 1 7 8 rd + # neg.b @erd ; 7 d rd ???? 1 7 8 ignore + # neg.b @erd+ ; 0 1 7 4 6 c rd 1??? 1 7 8 ignore + # neg.b @erd- ; 0 1 7 6 6 c rd 1??? 1 7 8 ignore + # neg.b @+erd ; 0 1 7 5 6 c rd 1??? 1 7 8 ignore + # neg.b @-erd ; 0 1 7 7 6 c rd 1??? 1 7 8 ignore + # neg.b @(d:2, erd) ; 0 1 7 01dd 6 8 rd 8 1 7 8 ignore + # neg.b @(d:16, erd) ; 0 1 7 4 6 e rd 1??? dd:16 1 7 8 ignore + # neg.b @(d:32, erd) ; 7 8 rd 4 6 a 2 1??? dd:32 1 7 8 ignore + # neg.b @aa:16 ; 6 a 1 1??? aa:16 1 7 8 ignore + # neg.b @aa:32 ; 6 a 3 1??? aa:32 1 7 8 ignore + # word operations + # long operations + # + # Coming soon: + # neg.b @aa:8 ; 7 f aaaaaaaa 1 7 8 ignore + # + + .data +byte_dest: .byte 0xa5 + .align 2 +word_dest: .word 0xa5a5 + .align 4 +long_dest: .long 0xa5a5a5a5 + start + + # + # Note: apparently carry is set for neg of anything except zero. + # + + # + # 8-bit byte operations + # + +neg_b_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; neg.b Rd + neg r0l ; 8-bit register +;;; .word 0x1788 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_ovf_clear + test_zero_clear + test_neg_clear + + cmp.b #0x5b, r0l ; result of "neg 0xa5" + beq .Lbrd + fail +.Lbrd: + test_h_gr16 0xa55b r0 ; r0 changed by 'neg' +.if (sim_cpu) ; non-zero means h8300h, s, or sx + test_h_gr32 0xa5a5a55b er0 ; er0 changed by 'neg' +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +neg_b_rdind: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; neg.b @eRd + mov #byte_dest, er0 + neg.b @er0 ; register indirect operand +;;; .word 0x7d00 +;;; .word 0x1780 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 byte_dest er0 ; er0 still contains address + cmp.b #0x5b, @er0 ; memory contents changed + beq .Lbind + fail +.Lbind: + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +neg_b_rdpostinc: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; neg.b @eRd+ + mov #byte_dest, er0 ; register post-increment operand + neg.b @er0+ +;;; .word 0x0174 +;;; .word 0x6c08 +;;; .word 0x1780 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 byte_dest+1 er0 ; er0 contains address plus one + cmp.b #0xa5, @-er0 + beq .Lbpostinc + fail +.Lbpostinc: + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +neg_b_rdpostdec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; neg.b @eRd- + mov #byte_dest, er0 ; register post-decrement operand + neg.b @er0- +;;; .word 0x0176 +;;; .word 0x6c08 +;;; .word 0x1780 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 byte_dest-1 er0 ; er0 contains address minus one + cmp.b #0x5b, @+er0 + beq .Lbpostdec + fail +.Lbpostdec: + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +neg_b_rdpreinc: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; neg.b @+eRd + mov #byte_dest-1, er0 + neg.b @+er0 ; reg pre-increment operand +;;; .word 0x0175 +;;; .word 0x6c08 +;;; .word 0x1780 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_ovf_clear + test_zero_clear + test_neg_set + + cmp.b #0xa5, @er0 + beq .Lbpreinc + fail +.Lbpreinc: + test_h_gr32 byte_dest er0 ; er0 contains destination address + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +neg_b_rdpredec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; neg.b @-eRd + mov #byte_dest+1, er0 + neg.b @-er0 ; reg pre-decr operand +;;; .word 0x0177 +;;; .word 0x6c08 +;;; .word 0x1780 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_ovf_clear + test_zero_clear + test_neg_clear + + cmp.b #0x5b, @er0 + beq .Lbpredec + fail +.Lbpredec: + test_h_gr32 byte_dest er0 ; er0 contains destination address + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +neg_b_disp2dst: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; neg.b @(dd:2, erd) + mov #byte_dest-1, er0 + neg.b @(1:2, er0) ; reg plus 2-bit displacement +;;; .word 0x0175 +;;; .word 0x6808 +;;; .word 0x1780 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_ovf_clear + test_zero_clear + test_neg_set + + cmp.b #0xa5, @+er0 + beq .Lbdisp2 + fail +.Lbdisp2: + test_h_gr32 byte_dest er0 ; er0 contains destination address + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +neg_b_disp16dst: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; neg.b @(dd:16, erd) + mov #byte_dest+100, er0 + neg.b @(-100:16, er0) ; reg plus 16-bit displacement +;;; .word 0x0174 +;;; .word 0x6e08 +;;; .word -100 +;;; .word 0x1780 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_ovf_clear + test_zero_clear + test_neg_clear + + cmp.b #0x5b, @byte_dest + beq .Lbdisp16 + fail +.Lbdisp16: + test_h_gr32 byte_dest+100 er0 ; er0 contains destination address + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +neg_b_disp32dst: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; neg.b @(dd:32, erd) + mov #byte_dest-0xfffff, er0 + neg.b @(0xfffff:32, er0) ; reg plus 32-bit displacement +;;; .word 0x7804 +;;; .word 0x6a28 +;;; .long 0xfffff +;;; .word 0x1780 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_ovf_clear + test_zero_clear + test_neg_set + + cmp.b #0xa5, @byte_dest + beq .Lbdisp32 + fail +.Lbdisp32: + test_h_gr32 byte_dest-0xfffff er0 ; er0 contains destination address + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +neg_b_abs16dst: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; neg.b @aa:16 + neg.b @byte_dest:16 ; 16-bit absolute address +;;; .word 0x6a18 +;;; .word byte_dest +;;; .word 0x1780 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_ovf_clear + test_zero_clear + test_neg_clear + + cmp.b #0x5b, @byte_dest + beq .Lbabs16 + fail +.Lbabs16: + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +neg_b_abs32dst: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; neg.b @aa:32 + neg.b @byte_dest:32 ; 32-bit absolute address +;;; .word 0x6a38 +;;; .long byte_dest +;;; .word 0x1780 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_ovf_clear + test_zero_clear + test_neg_set + + cmp.b #0xa5, @byte_dest + beq .Lbabs32 + fail +.Lbabs32: + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif + + # + # 16-bit word operations + # + +.if (sim_cpu) ; any except plain-vanilla h8/300 +neg_w_reg16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; neg.w Rd + neg r1 ; 16-bit register operand +;;; .word 0x1791 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_ovf_clear + test_zero_clear + test_neg_clear + + cmp.w #0x5a5b, r1 ; result of "neg 0xa5a5" + beq .Lwrd + fail +.Lwrd: + test_h_gr32 0xa5a55a5b er1 ; er1 changed by 'neg' + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +neg_w_rdind: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; neg.w @eRd + mov #word_dest, er1 + neg.w @er1 ; register indirect operand +;;; .word 0x0154 +;;; .word 0x6d18 +;;; .word 0x1790 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_ovf_clear + test_zero_clear + test_neg_clear + + cmp.w #0x5a5b, @word_dest ; memory contents changed + beq .Lwind + fail +.Lwind: + test_h_gr32 word_dest er1 ; er1 still contains address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +neg_w_rdpostinc: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; neg.w @eRd+ + mov #word_dest, er1 ; register post-increment operand + neg.w @er1+ +;;; .word 0x0154 +;;; .word 0x6d18 +;;; .word 0x1790 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_ovf_clear + test_zero_clear + test_neg_set + + cmp.w #0xa5a5, @word_dest + beq .Lwpostinc + fail +.Lwpostinc: + test_h_gr32 word_dest+2 er1 ; er1 contains address plus two + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +neg_w_rdpostdec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; neg.w @eRd- + mov #word_dest, er1 + neg.w @er1- +;;; .word 0x0156 +;;; .word 0x6d18 +;;; .word 0x1790 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_ovf_clear + test_zero_clear + test_neg_clear + + cmp.w #0x5a5b, @word_dest + beq .Lwpostdec + fail +.Lwpostdec: + test_h_gr32 word_dest-2 er1 ; er1 contains address minus two + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +neg_w_rdpreinc: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; neg.w @+eRd + mov #word_dest-2, er1 + neg.w @+er1 ; reg pre-increment operand +;;; .word 0x0155 +;;; .word 0x6d18 +;;; .word 0x1790 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_ovf_clear + test_zero_clear + test_neg_set + + cmp.w #0xa5a5, @word_dest + beq .Lwpreinc + fail +.Lwpreinc: + test_h_gr32 word_dest er1 ; er1 contains destination address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +neg_w_rdpredec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; neg.w @-eRd + mov #word_dest+2, er1 + neg.w @-er1 ; reg pre-decr operand +;;; .word 0x0157 +;;; .word 0x6d18 +;;; .word 0x1790 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_ovf_clear + test_zero_clear + test_neg_clear + + cmp.w #0x5a5b, @word_dest + beq .Lwpredec + fail +.Lwpredec: + test_h_gr32 word_dest er1 ; er1 contains destination address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +neg_w_disp2dst: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; neg.w @(dd:2, erd) + mov #word_dest-2, er1 + neg.w @(2:2, er1) ; reg plus 2-bit displacement +;;; .word 0x0155 +;;; .word 0x6918 +;;; .word 0x1790 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_ovf_clear + test_zero_clear + test_neg_set + + cmp.w #0xa5a5, @word_dest + beq .Lwdisp2 + fail +.Lwdisp2: + test_h_gr32 word_dest-2 er1 ; er1 contains address minus one + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +neg_w_disp16dst: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; neg.w @(dd:16, erd) + mov #word_dest+100, er1 + neg.w @(-100:16, er1) ; reg plus 16-bit displacement +;;; .word 0x0154 +;;; .word 0x6f18 +;;; .word -100 +;;; .word 0x1790 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_ovf_clear + test_zero_clear + test_neg_clear + + cmp.w #0x5a5b, @word_dest + beq .Lwdisp16 + fail +.Lwdisp16: + test_h_gr32 word_dest+100 er1 ; er1 contains destination address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +neg_w_disp32dst: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; neg.w @(dd:32, erd) + mov #word_dest-0xfffff, er1 + neg.w @(0xfffff:32, er1) ; reg plus 32-bit displacement +;;; .word 0x7814 +;;; .word 0x6b28 +;;; .long 0xfffff +;;; .word 0x1790 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_ovf_clear + test_zero_clear + test_neg_set + + cmp.w #0xa5a5, @word_dest + beq .Lwdisp32 + fail +.Lwdisp32: + test_h_gr32 word_dest-0xfffff er1 ; er1 contains destination address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +neg_w_abs16dst: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; neg.w @aa:16 + neg.w @word_dest:16 ; 16-bit absolute address +;;; .word 0x6b18 +;;; .word word_dest +;;; .word 0x1790 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_ovf_clear + test_zero_clear + test_neg_clear + + cmp.w #0x5a5b, @word_dest + beq .Lwabs16 + fail +.Lwabs16: + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +neg_w_abs32dst: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; neg.w @aa:32 + neg.w @word_dest:32 ; 32-bit absolute address +;;; .word 0x6b38 +;;; .long word_dest +;;; .word 0x1790 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_ovf_clear + test_zero_clear + test_neg_set + + cmp.w #0xa5a5, @word_dest + beq .Lwabs32 + fail +.Lwabs32: + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.endif ; h8sx +.endif ; h8/300 + + # + # 32-bit word operations + # + +.if (sim_cpu) ; any except plain-vanilla h8/300 +neg_l_reg16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; neg.l eRd + neg er1 ; 32-bit register operand +;;; .word 0x17b1 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_ovf_clear + test_zero_clear + test_neg_clear + + cmp.l #0x5a5a5a5b, er1 ; result of "neg 0xa5a5a5a5" + beq .Llrd + fail +.Llrd: + test_h_gr32 0x5a5a5a5b er1 ; er1 changed by 'neg' + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +neg_l_rdind: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; neg.l @eRd + mov #long_dest, er1 + neg.l @er1 ; register indirect operand +;;; .word 0x0104 +;;; .word 0x6d18 +;;; .word 0x17b0 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_ovf_clear + test_zero_clear + test_neg_clear + + cmp.l #0x5a5a5a5b, @long_dest ; memory contents changed + beq .Llind + fail +.Llind: + test_h_gr32 long_dest er1 ; er1 still contains address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +neg_l_rdpostinc: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; neg.l @eRd+ + mov #long_dest, er1 ; register post-increment operand + neg.l @er1+ +;;; .word 0x0104 +;;; .word 0x6d18 +;;; .word 0x17b0 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_ovf_clear + test_zero_clear + test_neg_set + + cmp.l #0xa5a5a5a5, @long_dest + beq .Llpostinc + fail +.Llpostinc: + test_h_gr32 long_dest+4 er1 ; er1 contains address plus two + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +neg_l_rdpostdec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; neg.l @eRd- + mov #long_dest, er1 + neg.l @er1- +;;; .word 0x0106 +;;; .word 0x6d18 +;;; .word 0x17b0 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_ovf_clear + test_zero_clear + test_neg_clear + + cmp.l #0x5a5a5a5b, @long_dest + beq .Llpostdec + fail +.Llpostdec: + test_h_gr32 long_dest-4 er1 ; er1 contains address minus two + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +neg_l_rdpreinc: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; neg.l @+eRd + mov #long_dest-4, er1 + neg.l @+er1 ; reg pre-increment operand +;;; .word 0x0105 +;;; .word 0x6d18 +;;; .word 0x17b0 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_ovf_clear + test_zero_clear + test_neg_set + + cmp.l #0xa5a5a5a5, @long_dest + beq .Llpreinc + fail +.Llpreinc: + test_h_gr32 long_dest er1 ; er1 contains destination address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +neg_l_rdpredec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; neg.l @-eRd + mov #long_dest+4, er1 + neg.l @-er1 ; reg pre-decr operand +;;; .word 0x0107 +;;; .word 0x6d18 +;;; .word 0x17b0 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_ovf_clear + test_zero_clear + test_neg_clear + + cmp.l #0x5a5a5a5b, @long_dest + beq .Llpredec + fail +.Llpredec: + test_h_gr32 long_dest er1 ; er1 contains destination address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +neg_l_disp2dst: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; neg.l @(dd:2, erd) + mov #long_dest-4, er1 + neg.l @(4:2, er1) ; reg plus 2-bit displacement +;;; .word 0x0105 +;;; .word 0x6918 +;;; .word 0x17b0 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_ovf_clear + test_zero_clear + test_neg_set + + cmp.l #0xa5a5a5a5, @long_dest + beq .Lldisp2 + fail +.Lldisp2: + test_h_gr32 long_dest-4 er1 ; er1 contains address minus one + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +neg_l_disp16dst: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; neg.l @(dd:16, erd) + mov #long_dest+100, er1 + neg.l @(-100:16, er1) ; reg plus 16-bit displacement +;;; .word 0x0104 +;;; .word 0x6f18 +;;; .word -100 +;;; .word 0x17b0 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_ovf_clear + test_zero_clear + test_neg_clear + + cmp.l #0x5a5a5a5b, @long_dest + beq .Lldisp16 + fail +.Lldisp16: + test_h_gr32 long_dest+100 er1 ; er1 contains destination address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +neg_l_disp32dst: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; neg.l @(dd:32, erd) + mov #long_dest-0xfffff, er1 + neg.l @(0xfffff:32, er1) ; reg plus 32-bit displacement +;;; .word 0x7894 +;;; .word 0x6b28 +;;; .long 0xfffff +;;; .word 0x17b0 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_ovf_clear + test_zero_clear + test_neg_set + + cmp.l #0xa5a5a5a5, @long_dest + beq .Lldisp32 + fail +.Lldisp32: + test_h_gr32 long_dest-0xfffff er1 ; er1 contains destination address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +neg_l_abs16dst: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; neg.l @aa:16 + neg.l @long_dest:16 ; 16-bit absolute address +;;; .word 0x0104 +;;; .word 0x6b08 +;;; .word long_dest +;;; .word 0x17b0 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_ovf_clear + test_zero_clear + test_neg_clear + + cmp.l #0x5a5a5a5b, @long_dest + beq .Llabs16 + fail +.Llabs16: + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +neg_l_abs32dst: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; neg.l @aa:32 + neg.l @long_dest:32 ; 32-bit absolute address +;;; .word 0x0104 +;;; .word 0x6b28 +;;; .long long_dest +;;; .word 0x17b0 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_ovf_clear + test_zero_clear + test_neg_set + + cmp.l #0xa5a5a5a5, @long_dest + beq .Llabs32 + fail +.Llabs32: + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.endif ; h8sx +.endif ; h8/300 + + pass + + exit 0 diff --git a/sim/testsuite/sim/h8300/nop.s b/sim/testsuite/sim/h8300/nop.s new file mode 100644 index 0000000..1d63b67 --- /dev/null +++ b/sim/testsuite/sim/h8300/nop.s @@ -0,0 +1,26 @@ +# Hitachi H8 testcase 'nop' +# mach(): all +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + start + +nop: set_grs_a5a5 + set_ccr_zero + + nop + + test_cc_clear + test_grs_a5a5 + + + pass + + exit 0 diff --git a/sim/testsuite/sim/h8300/not.s b/sim/testsuite/sim/h8300/not.s new file mode 100644 index 0000000..862c2b2 --- /dev/null +++ b/sim/testsuite/sim/h8300/not.s @@ -0,0 +1,1009 @@ +# Hitachi H8 testcase 'not.b, not.w, not.l' +# mach(): all +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + # Instructions tested: + # not.b rd ; 1 7 0 rd + # not.b @erd ; 7 d rd ???? 1 7 0 ignore + # not.b @erd+ ; 0 1 7 4 6 c rd 1??? 1 7 0 ignore + # not.b @erd- ; 0 1 7 6 6 c rd 1??? 1 7 0 ignore + # not.b @+erd ; 0 1 7 5 6 c rd 1??? 1 7 0 ignore + # not.b @-erd ; 0 1 7 7 6 c rd 1??? 1 7 0 ignore + # not.b @(d:2, erd) ; 0 1 7 01dd 6 8 rd 8 1 7 0 ignore + # not.b @(d:16, erd) ; 0 1 7 4 6 e rd 1??? dd:16 1 7 0 ignore + # not.b @(d:32, erd) ; 7 8 rd 4 6 a 2 1??? dd:32 1 7 0 ignore + # not.b @aa:16 ; 6 a 1 1??? aa:16 1 7 0 ignore + # not.b @aa:32 ; 6 a 3 1??? aa:32 1 7 0 ignore + # word operations + # long operations + # + # Coming soon: + # not.b @aa:8 ; 7 f aaaaaaaa 1 7 0 ignore + # + +.data +byte_dest: .byte 0xa5 + .align 2 +word_dest: .word 0xa5a5 + .align 4 +long_dest: .long 0xa5a5a5a5 + start + + # + # 8-bit byte operations + # + +not_b_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; not.b Rd + not r0l ; 8-bit register +;;; .word 0x1708 + + cmp.b #0x5a, r0l ; result of "not 0xa5" + beq .Lbrd + fail +.Lbrd: + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0xa55a r0 ; r0 changed by 'not' +.if (sim_cpu) ; non-zero means h8300h, s, or sx + test_h_gr32 0xa5a5a55a er0 ; er0 changed by 'not' +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +not_b_rdind: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; not.b @eRd + mov #byte_dest, er0 + not.b @er0 ; register indirect operand +;;; .word 0x7d00 +;;; .word 0x1700 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 byte_dest er0 ; er0 still contains address + cmp.b #0x5a:8, @er0 ; memory contents changed + beq .Lbind + fail +.Lbind: + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +not_b_rdpostinc: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; not.b @eRd+ + mov #byte_dest, er0 ; register post-increment operand + not.b @er0+ +;;; .word 0x0174 +;;; .word 0x6c08 +;;; .word 0x1700 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 byte_dest+1 er0 ; er0 contains address plus one + cmp.b #0xa5:8, @-er0 + beq .Lbpostinc + fail +.Lbpostinc: + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +not_b_rdpostdec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; not.b @eRd- + mov #byte_dest, er0 ; register post-decrement operand + not.b @er0- +;;; .word 0x0176 +;;; .word 0x6c08 +;;; .word 0x1700 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 byte_dest-1 er0 ; er0 contains address minus one + cmp.b #0x5a:8, @+er0 +;;; .word 0x0175 +;;; .word 0x6c08 +;;; .word 0xa05a + beq .Lbpostdec + fail +.Lbpostdec: + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +not_b_rdpreinc: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; not.b @+eRd + mov #byte_dest-1, er0 + not.b @+er0 ; reg pre-increment operand +;;; .word 0x0175 +;;; .word 0x6c08 +;;; .word 0x1700 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + cmp.b #0xa5:8, @er0 + beq .Lbpreinc + fail +.Lbpreinc: + test_h_gr32 byte_dest er0 ; er0 contains destination address + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +not_b_rdpredec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; not.b @-eRd + mov #byte_dest+1, er0 + not.b @-er0 ; reg pre-decr operand +;;; .word 0x0177 +;;; .word 0x6c08 +;;; .word 0x1700 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + cmp.b #0x5a:8, @er0 + beq .Lbpredec + fail +.Lbpredec: + test_h_gr32 byte_dest er0 ; er0 contains destination address + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +not_b_disp2dst: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; not.b @(dd:2, erd) + mov #byte_dest-1, er0 + not.b @(1:2, er0) ; reg plus 2-bit displacement +;;; .word 0x0175 +;;; .word 0x6808 +;;; .word 0x1700 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + cmp.b #0xa5:8, @+er0 + beq .Lbdisp2 + fail +.Lbdisp2: + test_h_gr32 byte_dest er0 ; er0 contains destination address + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +not_b_disp16dst: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; not.b @(dd:16, erd) + mov #byte_dest+100, er0 + not.b @(-100:16, er0) ; reg plus 16-bit displacement +;;; .word 0x0174 +;;; .word 0x6e08 +;;; .word -100 +;;; .word 0x1700 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + cmp.b #0x5a:8, @byte_dest + beq .Lbdisp16 + fail +.Lbdisp16: + test_h_gr32 byte_dest+100 er0 ; er0 contains destination address + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +not_b_disp32dst: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; not.b @(dd:32, erd) + mov #byte_dest-0xfffff, er0 + not.b @(0xfffff:32, er0) ; reg plus 32-bit displacement +;;; .word 0x7804 +;;; .word 0x6a28 +;;; .long 0xfffff +;;; .word 0x1700 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + cmp.b #0xa5:8, @byte_dest + beq .Lbdisp32 + fail +.Lbdisp32: + test_h_gr32 byte_dest-0xfffff er0 ; er0 contains destination address + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +not_b_abs16dst: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; not.b @aa:16 + not.b @byte_dest:16 ; 16-bit absolute address +;;; .word 0x6a18 +;;; .word byte_dest +;;; .word 0x1700 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + cmp.b #0x5a:8, @byte_dest + beq .Lbabs16 + fail +.Lbabs16: + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +not_b_abs32dst: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; not.b @aa:32 + not.b @byte_dest:32 ; 32-bit absolute address +;;; .word 0x6a38 +;;; .long byte_dest +;;; .word 0x1700 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + cmp.b #0xa5:8, @byte_dest + beq .Lbabs32 + fail +.Lbabs32: + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif + + # + # 16-bit word operations + # + +.if (sim_cpu) ; any except plain-vanilla h8/300 +not_w_reg16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; not.w Rd + not r1 ; 16-bit register operand +;;; .word 0x1711 + + cmp.w #0x5a5a, r1 ; result of "not 0xa5a5" + beq .Lwrd + fail +.Lwrd: + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr32 0xa5a55a5a er1 ; er1 changed by 'not' + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +not_w_rdind: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; not.w @eRd + mov #word_dest, er1 + not.w @er1 ; register indirect operand +;;; .word 0x0154 +;;; .word 0x6d18 +;;; .word 0x1710 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + cmp.w #0x5a5a, @word_dest ; memory contents changed + beq .Lwind + fail +.Lwind: + test_h_gr32 word_dest er1 ; er1 still contains address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +not_w_rdpostinc: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; not.w @eRd+ + mov #word_dest, er1 ; register post-increment operand + not.w @er1+ +;;; .word 0x0154 +;;; .word 0x6d18 +;;; .word 0x1710 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + cmp.w #0xa5a5, @word_dest + beq .Lwpostinc + fail +.Lwpostinc: + test_h_gr32 word_dest+2 er1 ; er1 contains address plus two + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +not_w_rdpostdec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; not.w @eRd- + mov #word_dest, er1 + not.w @er1- +;;; .word 0x0156 +;;; .word 0x6d18 +;;; .word 0x1710 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + cmp.w #0x5a5a, @word_dest + beq .Lwpostdec + fail +.Lwpostdec: + test_h_gr32 word_dest-2 er1 ; er1 contains address minus two + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +not_w_rdpreinc: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; not.w @+eRd + mov #word_dest-2, er1 + not.w @+er1 ; reg pre-increment operand +;;; .word 0x0155 +;;; .word 0x6d18 +;;; .word 0x1710 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + cmp.w #0xa5a5, @word_dest + beq .Lwpreinc + fail +.Lwpreinc: + test_h_gr32 word_dest er1 ; er1 contains destination address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +not_w_rdpredec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; not.w @-eRd + mov #word_dest+2, er1 + not.w @-er1 ; reg pre-decr operand +;;; .word 0x0157 +;;; .word 0x6d18 +;;; .word 0x1710 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + cmp.w #0x5a5a, @word_dest + beq .Lwpredec + fail +.Lwpredec: + test_h_gr32 word_dest er1 ; er1 contains destination address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +not_w_disp2dst: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; not.w @(dd:2, erd) + mov #word_dest-2, er1 + not.w @(2:2, er1) ; reg plus 2-bit displacement +;;; .word 0x0155 +;;; .word 0x6918 +;;; .word 0x1710 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + cmp.w #0xa5a5, @word_dest + beq .Lwdisp2 + fail +.Lwdisp2: + test_h_gr32 word_dest-2 er1 ; er1 contains address minus one + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +not_w_disp16dst: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; not.w @(dd:16, erd) + mov #word_dest+100, er1 + not.w @(-100:16, er1) ; reg plus 16-bit displacement +;;; .word 0x0154 +;;; .word 0x6f18 +;;; .word -100 +;;; .word 0x1710 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + cmp.w #0x5a5a, @word_dest + beq .Lwdisp16 + fail +.Lwdisp16: + test_h_gr32 word_dest+100 er1 ; er1 contains destination address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +not_w_disp32dst: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; not.w @(dd:32, erd) + mov #word_dest-0xfffff, er1 + not.w @(0xfffff:32, er1) ; reg plus 32-bit displacement +;;; .word 0x7814 +;;; .word 0x6b28 +;;; .long 0xfffff +;;; .word 0x1710 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + cmp.w #0xa5a5, @word_dest + beq .Lwdisp32 + fail +.Lwdisp32: + test_h_gr32 word_dest-0xfffff er1 ; er1 contains destination address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +not_w_abs16dst: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; not.w @aa:16 + not.w @word_dest:16 ; 16-bit absolute address +;;; .word 0x6b18 +;;; .word word_dest +;;; .word 0x1710 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + cmp.w #0x5a5a, @word_dest + beq .Lwabs16 + fail +.Lwabs16: + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +not_w_abs32dst: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; not.w @aa:32 + not.w @word_dest:32 ; 32-bit absolute address +;;; .word 0x6b38 +;;; .long word_dest +;;; .word 0x1710 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + cmp.w #0xa5a5, @word_dest + beq .Lwabs32 + fail +.Lwabs32: + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.endif ; h8sx +.endif ; h8/300 + + # + # 32-bit word operations + # + +.if (sim_cpu) ; any except plain-vanilla h8/300 +not_l_reg16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; not.l eRd + not er1 ; 32-bit register operand +;;; .word 0x1731 + + cmp.l #0x5a5a5a5a, er1 ; result of "not 0xa5a5a5a5" + beq .Llrd + fail +.Llrd: + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr32 0x5a5a5a5a er1 ; er1 changed by 'not' + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +not_l_rdind: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; not.l @eRd + mov #long_dest, er1 + not.l @er1 ; register indirect operand +;;; .word 0x0104 +;;; .word 0x6d18 +;;; .word 0x1730 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + cmp.l #0x5a5a5a5a, @long_dest ; memory contents changed + beq .Llind + fail +.Llind: + test_h_gr32 long_dest er1 ; er1 still contains address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +not_l_rdpostinc: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; not.l @eRd+ + mov #long_dest, er1 ; register post-increment operand + not.l @er1+ +;;; .word 0x0104 +;;; .word 0x6d18 +;;; .word 0x1730 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + cmp.l #0xa5a5a5a5, @long_dest + beq .Llpostinc + fail +.Llpostinc: + test_h_gr32 long_dest+4 er1 ; er1 contains address plus two + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +not_l_rdpostdec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; not.l @eRd- + mov #long_dest, er1 + not.l @er1- +;;; .word 0x0106 +;;; .word 0x6d18 +;;; .word 0x1730 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + cmp.l #0x5a5a5a5a, @long_dest + beq .Llpostdec + fail +.Llpostdec: + test_h_gr32 long_dest-4 er1 ; er1 contains address minus two + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +not_l_rdpreinc: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; not.l @+eRd + mov #long_dest-4, er1 + not.l @+er1 ; reg pre-increment operand +;;; .word 0x0105 +;;; .word 0x6d18 +;;; .word 0x1730 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + cmp.l #0xa5a5a5a5, @long_dest + beq .Llpreinc + fail +.Llpreinc: + test_h_gr32 long_dest er1 ; er1 contains destination address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +not_l_rdpredec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; not.l @-eRd + mov #long_dest+4, er1 + not.l @-er1 ; reg pre-decr operand +;;; .word 0x0107 +;;; .word 0x6d18 +;;; .word 0x1730 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + cmp.l #0x5a5a5a5a, @long_dest + beq .Llpredec + fail +.Llpredec: + test_h_gr32 long_dest er1 ; er1 contains destination address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +not_l_disp2dst: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; not.l @(dd:2, erd) + mov #long_dest-4, er1 + not.l @(4:2, er1) ; reg plus 2-bit displacement +;;; .word 0x0105 +;;; .word 0x6918 +;;; .word 0x1730 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + cmp.l #0xa5a5a5a5, @long_dest + beq .Lldisp2 + fail +.Lldisp2: + test_h_gr32 long_dest-4 er1 ; er1 contains address minus one + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +not_l_disp16dst: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; not.l @(dd:16, erd) + mov #long_dest+100, er1 + not.l @(-100:16, er1) ; reg plus 16-bit displacement +;;; .word 0x0104 +;;; .word 0x6f18 +;;; .word -100 +;;; .word 0x1730 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + cmp.l #0x5a5a5a5a, @long_dest + beq .Lldisp16 + fail +.Lldisp16: + test_h_gr32 long_dest+100 er1 ; er1 contains destination address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +not_l_disp32dst: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; not.l @(dd:32, erd) + mov #long_dest-0xfffff, er1 + not.l @(0xfffff:32, er1) ; reg plus 32-bit displacement +;;; .word 0x7894 +;;; .word 0x6b28 +;;; .long 0xfffff +;;; .word 0x1730 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + cmp.l #0xa5a5a5a5, @long_dest + beq .Lldisp32 + fail +.Lldisp32: + test_h_gr32 long_dest-0xfffff er1 ; er1 contains destination address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +not_l_abs16dst: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; not.l @aa:16 + not.l @long_dest:16 ; 16-bit absolute address +;;; .word 0x0104 +;;; .word 0x6b08 +;;; .word long_dest +;;; .word 0x1730 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + cmp.l #0x5a5a5a5a, @long_dest + beq .Llabs16 + fail +.Llabs16: + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +not_l_abs32dst: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; not.l @aa:32 + not.l @long_dest:32 ; 32-bit absolute address +;;; .word 0x0104 +;;; .word 0x6b28 +;;; .long long_dest +;;; .word 0x1730 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + cmp.l #0xa5a5a5a5, @long_dest + beq .Llabs32 + fail +.Llabs32: + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.endif ; h8sx +.endif ; h8/300 + + pass + + exit 0 diff --git a/sim/testsuite/sim/h8300/orb.s b/sim/testsuite/sim/h8300/orb.s new file mode 100644 index 0000000..72da8e6 --- /dev/null +++ b/sim/testsuite/sim/h8300/orb.s @@ -0,0 +1,532 @@ +# Hitachi H8 testcase 'or.b' +# mach(): all +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + # Instructions tested: + # or.b #xx:8, rd ; c rd xxxxxxxx + # or.b #xx:8, @erd ; 7 d rd ???? c ???? xxxxxxxx + # or.b #xx:8, @erd+ ; 0 1 7 4 6 c rd 1??? c ???? xxxxxxxx + # or.b #xx:8, @erd- ; 0 1 7 6 6 c rd 1??? c ???? xxxxxxxx + # or.b #xx:8, @+erd ; 0 1 7 5 6 c rd 1??? c ???? xxxxxxxx + # or.b #xx:8, @-erd ; 0 1 7 7 6 c rd 1??? c ???? xxxxxxxx + # or.b rs, rd ; 1 4 rs rd + # or.b reg8, @erd ; 7 d rd ???? 1 4 rs ???? + # or.b reg8, @erd+ ; 0 1 7 9 8 rd 4 rs + # or.b reg8, @erd- ; 0 1 7 9 a rd 4 rs + # or.b reg8, @+erd ; 0 1 7 9 9 rd 4 rs + # or.b reg8, @-erd ; 0 1 7 9 b rd 4 rs + # + # orc #xx:8, ccr + # orc #xx:8, exr + + + # Coming soon: + # ... + +.data +pre_byte: .byte 0 +byte_dest: .byte 0xa5 +post_byte: .byte 0 + + start + +or_b_imm8_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; or.b #xx:8,Rd + or.b #0xaa, r0l ; Immediate 8-bit src, reg8 dest + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0xa5af r0 ; or result: a5 | aa +.if (sim_cpu) ; non-zero means h8300h, s, or sx + test_h_gr32 0xa5a5a5af er0 ; or result: a5 | aa +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +or_b_imm8_rdind: + mov #byte_dest, er0 + mov.b #0xa5, r1l + mov.b r1l, @er0 + + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; or.b #xx:8,@eRd + mov #byte_dest, er0 + or.b #0xaa:8, @er0 ; Immediate 8-bit src, reg indirect dst +;;; .word 0x7d00 +;;; .word 0xc0aa + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 byte_dest, er0 ; er0 still contains address + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the or to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0xaf, r0l + beq .L1 + fail +.L1: + +or_b_imm8_rdpostinc: + mov #byte_dest, er0 + mov.b #0xa5, r1l + mov.b r1l, @er0 + + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; or.b #xx:8,@eRd+ + mov #byte_dest, er0 + or.b #0x55:8, @er0+ ; Immediate 8-bit src, reg post-incr dest +;;; .word 0x0174 +;;; .word 0x6c08 +;;; .word 0xc055 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 post_byte, er0 ; er0 contains address plus one + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the or to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0xf5, r0l + beq .L2 + fail +.L2: + +or_b_imm8_rdpostdec: + mov #byte_dest, er0 + mov.b #0xa5, r1l + mov.b r1l, @er0 + + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; or.b #xx:8,@eRd- + mov #byte_dest, er0 + or.b #0xaa:8, @er0- ; Immediate 8-bit src, reg post-decr dest +;;; .word 0x0176 +;;; .word 0x6c08 +;;; .word 0xc0aa + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 pre_byte, er0 ; er0 contains address minus one + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the or to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0xaf, r0l + beq .L3 + fail +.L3: + +or_b_imm8_rdpreinc: + mov #byte_dest, er0 + mov.b #0xa5, r1l + mov.b r1l, @er0 + + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; or.b #xx:8,@+eRd + mov #pre_byte, er0 + or.b #0x55:8, @+er0 ; Immediate 8-bit src, reg pre-incr dest +;;; .word 0x0175 +;;; .word 0x6c08 +;;; .word 0xc055 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 byte_dest, er0 ; er0 contains destination address + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the or to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0xf5, r0l + beq .L4 + fail +.L4: + +or_b_imm8_rdpredec: + mov #byte_dest, er0 + mov.b #0xa5, r1l + mov.b r1l, @er0 + + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; or.b #xx:8,@-eRd + mov #post_byte, er0 + or.b #0xaa:8, @-er0 ; Immediate 8-bit src, reg pre-decr dest +;;; .word 0x0177 +;;; .word 0x6c08 +;;; .word 0xc0aa + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 byte_dest, er0 ; er0 contains destination address + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the or to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0xaf, r0l + beq .L5 + fail +.L5: + + +.endif + +or_b_reg8_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; or.b Rs,Rd + mov.b #0xaa, r0h + or.b r0h, r0l ; Reg8 src, reg8 dest + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0xaaaf r0 ; or result: a5 | aa +.if (sim_cpu) ; non-zero means h8300h, s, or sx + test_h_gr32 0xa5a5aaaf er0 ; or result: a5 | aa +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +or_b_reg8_rdind: + mov #byte_dest, er0 + mov.b #0xa5, r1l + mov.b r1l, @er0 + + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; or.b rs8,@eRd ; or reg8 to register indirect + mov #byte_dest, er0 + mov #0xaa, r1l + or.b r1l, @er0 ; reg8 src, reg indirect dest +;;; .word 0x7d00 +;;; .word 0x1490 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 byte_dest er0 ; er0 still contains address + test_h_gr32 0xa5a5a5aa er1 ; er1 has the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the or to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0xaf, r0l + beq .L6 + fail +.L6: + +or_b_reg8_rdpostinc: + mov #byte_dest, er0 + mov.b #0xa5, r1l + mov.b r1l, @er0 + + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; or.b rs8,@eRd+ ; or reg8 to register indirect post-increment + mov #byte_dest, er0 + mov #0x55, r1l + or.b r1l, @er0+ ; reg8 src, reg post-incr dest +;;; .word 0x0179 +;;; .word 0x8049 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 post_byte er0 ; er0 contains address plus one + test_h_gr32 0xa5a5a555 er1 ; er1 has the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the or to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0xf5, r0l + beq .L7 + fail +.L7: + +or_b_reg8_rdpostdec: + mov #byte_dest, er0 + mov.b #0xa5, r1l + mov.b r1l, @er0 + + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; or.b rs8,@eRd- ; or reg8 to register indirect post-decrement + mov #byte_dest, er0 + mov #0xaa, r1l + or.b r1l, @er0- ; reg8 src, reg post-decr dest +;;; .word 0x0179 +;;; .word 0xa049 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 pre_byte er0 ; er0 contains address minus one + test_h_gr32 0xa5a5a5aa er1 ; er1 has the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the or to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0xaf, r0l + beq .L8 + fail +.L8: + +or_b_reg8_rdpreinc: + mov #byte_dest, er0 + mov.b #0xa5, r1l + mov.b r1l, @er0 + + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; or.b rs8,@+eRd ; or reg8 to register indirect pre-increment + mov #pre_byte, er0 + mov #0x55, r1l + or.b r1l, @+er0 ; reg8 src, reg pre-incr dest +;;; .word 0x0179 +;;; .word 0x9049 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 byte_dest er0 ; er0 contains destination address + test_h_gr32 0xa5a5a555 er1 ; er1 has the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the or to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0xf5, r0l + beq .L9 + fail +.L9: + +or_b_reg8_rdpredec: + mov #byte_dest, er0 + mov.b #0xa5, r1l + mov.b r1l, @er0 + + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; or.b rs8,@-eRd ; or reg8 to register indirect pre-decrement + mov #post_byte, er0 + mov #0xaa, r1l + or.b r1l, @-er0 ; reg8 src, reg pre-decr dest +;;; .word 0x0179 +;;; .word 0xb049 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 byte_dest er0 ; er0 contains destination address + test_h_gr32 0xa5a5a5aa er1 ; er1 has the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the or to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0xaf, r0l + beq .L10 + fail +.L10: + +.endif + +orc_imm8_ccr: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; orc #xx:8,ccr + + test_neg_clear + orc #0x8, ccr ; Immediate 8-bit operand (neg flag) + test_neg_set + + test_zero_clear + orc #0x4, ccr ; Immediate 8-bit operand (zero flag) + test_zero_set + + test_ovf_clear + orc #0x2, ccr ; Immediate 8-bit operand (overflow flag) + test_ovf_set + + test_carry_clear + orc #0x1, ccr ; Immediate 8-bit operand (carry flag) + test_carry_set + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8300s || sim_cpu == h8sx) ; Earlier versions, no exr +orc_imm8_exr: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ldc #0, exr + stc exr, r0l + test_h_gr8 0, r0l + + ;; orc #xx:8,exr + + orc #0x1, exr + stc exr,r0l + test_h_gr8 1, r0l + + orc #0x2, exr + stc exr,r0l + test_h_gr8 3, r0l + + orc #0x4, exr + stc exr,r0l + test_h_gr8 7, r0l + + orc #0x80, exr + stc exr,r0l + test_h_gr8 0x87, r0l + + test_h_gr32 0xa5a5a587 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif ; not h8300 or h8300h + + pass + + exit 0 diff --git a/sim/testsuite/sim/h8300/orl.s b/sim/testsuite/sim/h8300/orl.s new file mode 100644 index 0000000..03c3f22 --- /dev/null +++ b/sim/testsuite/sim/h8300/orl.s @@ -0,0 +1,77 @@ +# Hitachi H8 testcase 'or.l' +# mach(): h8300h h8300s h8sx +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + start + +.if (sim_cpu == h8sx) ; 16-bit immediate is only available on sx. +or_l_imm16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; or.l #xx:16,Rd + or.l #0xaaaa, er0 ; Immediate 16-bit operand + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + + test_h_gr32 0xa5a5afaf er0 ; or result: a5a5a5a5 | aaaa + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif + +or_l_imm32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; or.l #xx:32,Rd + or.l #0xaaaaaaaa, er0 ; Immediate 32-bit operand + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + + test_h_gr32 0xafafafaf er0 ; or result: a5a5a5a5 | aaaaaaaa + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +or_l_reg: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; or.l Rs,Rd + mov.l #0xaaaaaaaa, er1 + or.l er1, er0 ; Register operand + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + + test_h_gr32 0xafafafaf er0 ; or result: a5a5a5a5 | aaaaaaaa + test_h_gr32 0xaaaaaaaa er1 ; Make sure er1 is unchanged + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + pass + + exit 0 diff --git a/sim/testsuite/sim/h8300/orw.s b/sim/testsuite/sim/h8300/orw.s new file mode 100644 index 0000000..32eef45 --- /dev/null +++ b/sim/testsuite/sim/h8300/orw.s @@ -0,0 +1,61 @@ +# Hitachi H8 testcase 'or.w' +# mach(): h8300h h8300s h8sx +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + start + +.if (sim_cpu) ; non-zero means h8300h, s, or sx +or_w_imm16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; or.w #xx:16,Rd + or.w #0xaaaa, r0 ; Immediate 16-bit operand + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0xafaf r0 ; or result: a5a5 | aaaa +.if (sim_cpu) ; non-zero means h8300h, s, or sx + test_h_gr32 0xa5a5afaf er0 ; or result: a5a5 | aaaa +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif + +or_w_reg: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; or.w Rs,Rd + mov.w #0xaaaa, r1 + or.w r1, r0 ; Register operand + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0xafaf r0 ; or result: a5a5 | aaaa + test_h_gr16 0xaaaa r1 ; Make sure r1 is unchanged +.if (sim_cpu) ; non-zero means h8300h, s, or sx + test_h_gr32 0xa5a5afaf er0 ; or result: a5a5 | aaaa + test_h_gr32 0xa5a5aaaa er1 ; Make sure er1 is unchanged +.endif + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + pass + + exit 0 diff --git a/sim/testsuite/sim/h8300/rotl.s b/sim/testsuite/sim/h8300/rotl.s new file mode 100644 index 0000000..088345d --- /dev/null +++ b/sim/testsuite/sim/h8300/rotl.s @@ -0,0 +1,1212 @@ +# Hitachi H8 testcase 'rotl' +# mach(): all +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + start + + .data +byte_dest: .byte 0xa5 + .align 2 +word_dest: .word 0xa5a5 + .align 4 +long_dest: .long 0xa5a5a5a5 + + .text + +rotl_b_reg8_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotl.b r0l ; shift left arithmetic by one + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + test_h_gr16 0xa54b r0 ; 1010 0101 -> 0100 1011 +.if (sim_cpu) + test_h_gr32 0xa5a5a54b er0 +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +rotl_b_ind_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest, er0 + rotl.b @er0 ; shift right arithmetic by one, indirect + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 byte_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0100 1011 + cmp.b #0x4b, @byte_dest + beq .Lbind1 + fail +.Lbind1: + mov.b #0xa5, @byte_dest + +rotl_b_indexb16_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov.b #5, r0l + rotl.b @(byte_dest-5:16, r0.b) ; indexed byte/byte + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 0xa5a5a505 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0100 1011 + cmp.b #0x4b, @byte_dest + beq .Lbindexb161 + fail +.Lbindexb161: + mov.b #0xa5, @byte_dest + +rotl_b_indexw16_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov.w #256, r0 + rotl.b @(byte_dest-256:16, r0.w) ; indexed byte/word + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 0xa5a50100 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0100 1011 + cmp.b #0x4b, @byte_dest + beq .Lbindexw161 + fail +.Lbindexw161: + mov.b #0xa5, @byte_dest + +rotl_b_indexl16_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov.l #0xffffffff, er0 + rotl.b @(byte_dest+1:16, er0.l) ; indexed byte/long + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 0xffffffff er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0100 1011 + cmp.b #0x4b, @byte_dest + beq .Lbindexl161 + fail +.Lbindexl161: + mov.b #0xa5, @byte_dest + +rotl_b_indexb32_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov.b #5, r1l + rotl.b @(byte_dest-5:32, r1.b) ; indexed byte/byte + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 0xa5a5a505 er1 + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0100 1011 + cmp.b #0x4b, @byte_dest + beq .Lbindexb321 + fail +.Lbindexb321: + mov.b #0xa5, @byte_dest + +rotl_b_indexw32_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov.w #256, r1 + rotl.b @(byte_dest-256:32, r1.w) ; indexed byte/word + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 0xa5a50100 er1 + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0100 1011 + cmp.b #0x4b, @byte_dest + beq .Lbindexw321 + fail +.Lbindexw321: + mov.b #0xa5, @byte_dest + +rotl_b_indexl32_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov.l #0xffffffff, er1 + rotl.b @(byte_dest+1:32, er1.l) ; indexed byte/long + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 0xffffffff er1 + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0100 1011 + cmp.b #0x4b, @byte_dest + beq .Lbindexl321 + fail +.Lbindexl321: + mov.b #0xa5, @byte_dest + +.endif + +rotl_b_reg8_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotl.b #2, r0l ; shift left arithmetic by two + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr16 0xa596 r0 ; 1010 0101 -> 1001 0110 +.if (sim_cpu) + test_h_gr32 0xa5a5a596 er0 +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +rotl_b_ind_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest, er0 + rotl.b #2, @er0 ; shift right arithmetic by one, indirect + + test_carry_clear ; H=0 N=1 Z=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 byte_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 1001 0110 + cmp.b #0x96, @byte_dest + beq .Lbind2 + fail +.Lbind2: + mov.b #0xa5, @byte_dest + +rotl_b_indexb16_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov.b #5, r0l + rotl.b #2, @(byte_dest-5:16, r0.b) ; indexed byte/byte + + test_carry_clear ; H=0 N=1 Z=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 0xa5a5a505 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 1001 0110 + cmp.b #0x96, @byte_dest + beq .Lbindexb162 + fail +.Lbindexb162: + mov.b #0xa5, @byte_dest + +rotl_b_indexw16_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov.w #256, r0 + rotl.b #2, @(byte_dest-256:16, r0.w) ; indexed byte/word + + test_carry_clear ; H=0 N=1 Z=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 0xa5a50100 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 1001 0110 + cmp.b #0x96, @byte_dest + beq .Lbindexw162 + fail +.Lbindexw162: + mov.b #0xa5, @byte_dest + +rotl_b_indexl16_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov.l #0xffffffff, er0 + rotl.b #2, @(byte_dest+1:16, er0.l) ; indexed byte/long + + test_carry_clear ; H=0 N=1 Z=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 0xffffffff er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 1001 0110 + cmp.b #0x96, @byte_dest + beq .Lbindexl162 + fail +.Lbindexl162: + mov.b #0xa5, @byte_dest + +rotl_b_indexb32_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov.b #5, r1l + rotl.b #2, @(byte_dest-5:32, r1.b) ; indexed byte/byte + + test_carry_clear ; H=0 N=1 Z=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 0xa5a5a505 er1 + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 1001 0110 + cmp.b #0x96, @byte_dest + beq .Lbindexb322 + fail +.Lbindexb322: + mov.b #0xa5, @byte_dest + +rotl_b_indexw32_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov.w #256, r1 + rotl.b #2, @(byte_dest-256:32, r1.w) ; indexed byte/word + + test_carry_clear ; H=0 N=1 Z=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 0xa5a50100 er1 + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 1001 0110 + cmp.b #0x96, @byte_dest + beq .Lbindexw322 + fail +.Lbindexw322: + mov.b #0xa5, @byte_dest + +rotl_b_indexl32_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov.l #0xffffffff, er1 + rotl.b #2, @(byte_dest+1:32, er1.l) ; indexed byte/long + + test_carry_clear ; H=0 N=1 Z=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 0xffffffff er1 + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 1001 0110 + cmp.b #0x96, @byte_dest + beq .Lbindexl322 + fail +.Lbindexl322: + mov.b #0xa5, @byte_dest + +.endif + +.if (sim_cpu) ; Not available in h8300 mode +rotl_w_reg16_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotl.w r0 ; shift left arithmetic by one + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + test_h_gr16 0x4b4b r0 ; 1010 0101 1010 0101 -> 0100 1011 0100 1011 + test_h_gr32 0xa5a54b4b er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +rotl_w_indexb16_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov.b #5, r0l + rotl.w @(word_dest-10:16, r0.b) ; indexed word/byte + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 0xa5a5a505 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0100 1011 0100 1011 + cmp.w #0x4b4b, @word_dest + beq .Lwindexb161 + fail +.Lwindexb161: + mov.w #0xa5a5, @word_dest + +rotl_w_indexw16_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov.w #256, r0 + rotl.w @(word_dest-512:16, r0.w) ; indexed word/word + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 0xa5a50100 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0100 1011 0100 1011 + cmp.w #0x4b4b, @word_dest + beq .Lwindexw161 + fail +.Lwindexw161: + mov.w #0xa5a5, @word_dest + +rotl_w_indexl16_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov.l #0xffffffff, er0 + rotl.w @(word_dest+2:16, er0.l) ; indexed word/long + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 0xffffffff er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0100 1011 0100 1011 + cmp.w #0x4b4b, @word_dest + beq .Lwindexl161 + fail +.Lwindexl161: + mov.w #0xa5a5, @word_dest + +rotl_w_indexb32_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov.b #5, r1l + rotl.w @(word_dest-10:32, r1.b) ; indexed word/byte + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 0xa5a5a505 er1 + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0100 1011 0100 1011 + cmp.w #0x4b4b, @word_dest + beq .Lwindexb321 + fail +.Lwindexb321: + mov.w #0xa5a5, @word_dest + +rotl_w_indexw32_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov.w #256, r1 + rotl.w @(word_dest-512:32, r1.w) ; indexed word/byte + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 0xa5a50100 er1 + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0100 1011 0100 1011 + cmp.w #0x4b4b, @word_dest + beq .Lwindexw321 + fail +.Lwindexw321: + mov.w #0xa5a5, @word_dest + +rotl_w_indexl32_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov.l #0xffffffff, er1 + rotl.w @(word_dest+2:32, er1.l) ; indexed word/byte + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 0xffffffff er1 + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0100 1011 0100 1011 + cmp.w #0x4b4b, @word_dest + beq .Lwindexl321 + fail +.Lwindexl321: + mov.w #0xa5a5, @word_dest +.endif + +rotl_w_reg16_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotl.w #2, r0 ; shift left arithmetic by two + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + test_h_gr16 0x9696 r0 ; 1010 0101 1010 0101 -> 1001 0110 1001 0110 + test_h_gr32 0xa5a59696 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +rotl_w_indexb16_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov.b #5, r0l + rotl.w #2, @(word_dest-10:16, r0.b) ; indexed word/byte + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 0xa5a5a505 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 1001 0110 1001 0110 + cmp.w #0x9696, @word_dest + beq .Lwindexb162 + fail +.Lwindexb162: + mov.w #0xa5a5, @word_dest + +rotl_w_indexw16_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov.w #256, r0 + rotl.w #2, @(word_dest-512:16, r0.w) ; indexed word/word + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 0xa5a50100 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 1001 0110 1001 0110 + cmp.w #0x9696, @word_dest + beq .Lwindexw162 + fail +.Lwindexw162: + mov.w #0xa5a5, @word_dest + +rotl_w_indexl16_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov.l #0xffffffff, er0 + rotl.w #2, @(word_dest+2:16, er0.l) ; indexed word/long + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 0xffffffff er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 1001 0110 1001 0110 + cmp.w #0x9696, @word_dest + beq .Lwindexl162 + fail +.Lwindexl162: + mov.w #0xa5a5, @word_dest + +rotl_w_indexb32_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov.b #5, r1l + rotl.w #2, @(word_dest-10:32, r1.b) ; indexed word/byte + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 0xa5a5a505 er1 + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 1001 0110 1001 0110 + cmp.w #0x9696, @word_dest + beq .Lwindexb322 + fail +.Lwindexb322: + mov.w #0xa5a5, @word_dest + +rotl_w_indexw32_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov.w #256, r1 + rotl.w #2, @(word_dest-512:32, r1.w) ; indexed word/byte + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 0xa5a50100 er1 + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 1001 0110 1001 0110 + cmp.w #0x9696, @word_dest + beq .Lwindexw322 + fail +.Lwindexw322: + mov.w #0xa5a5, @word_dest + +rotl_w_indexl32_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov.l #0xffffffff, er1 + rotl.w #2, @(word_dest+2:32, er1.l) ; indexed word/byte + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 0xffffffff er1 + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 1001 0110 1001 0110 + cmp.w #0x9696, @word_dest + beq .Lwindexl322 + fail +.Lwindexl322: + mov.w #0xa5a5, @word_dest +.endif + +rotl_l_reg32_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotl.l er0 ; shift left arithmetic by one + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ; -> 0100 1011 0100 1011 0100 1011 0100 1011 + test_h_gr32 0x4b4b4b4b er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +rotl_l_indexb16_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov.b #5, r0l + rotl.l @(long_dest-20:16, er0.b) ; indexed long/byte + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 0xa5a5a505 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ; -> 0100 1011 0100 1011 0100 1011 0100 1011 + cmp.l #0x4b4b4b4b, @long_dest + beq .Llindexb161 + fail +.Llindexb161: + mov.l #0xa5a5a5a5, @long_dest + +rotl_l_indexw16_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov.w #256, r0 + rotl.l @(long_dest-1024:16, er0.w) ; indexed long/word + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 0xa5a50100 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ; -> 0100 1011 0100 1011 0100 1011 0100 1011 + cmp.l #0x4b4b4b4b, @long_dest + beq .Llindexw161 + fail +.Llindexw161: + mov.l #0xa5a5a5a5, @long_dest + +rotl_l_indexl16_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov.l #0xffffffff, er0 + rotl.l @(long_dest+4:16, er0.l) ; indexed long/long + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 0xffffffff er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ; -> 0100 1011 0100 1011 0100 1011 0100 1011 + cmp.l #0x4b4b4b4b, @long_dest + beq .Llindexl161 + fail +.Llindexl161: + mov.l #0xa5a5a5a5, @long_dest + +rotl_l_indexb32_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov.b #5, r1l + rotl.l @(long_dest-20:32, er1.b) ; indexed long/byte + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 0xa5a5a505 er1 + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ; -> 0100 1011 0100 1011 0100 1011 0100 1011 + cmp.l #0x4b4b4b4b, @long_dest + beq .Llindexb321 + fail +.Llindexb321: + mov.l #0xa5a5a5a5, @long_dest + +rotl_l_indexw32_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov.w #256, r1 + rotl.l @(long_dest-1024:32, er1.w) ; indexed long/byte + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 0xa5a50100 er1 + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ; -> 0100 1011 0100 1011 0100 1011 0100 1011 + cmp.l #0x4b4b4b4b, @long_dest + beq .Llindexw321 + fail +.Llindexw321: + mov.l #0xa5a5a5a5, @long_dest + +rotl_l_indexl32_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov.l #0xffffffff, er1 + rotl.l @(long_dest+4:32, er1.l) ; indexed long/byte + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 0xffffffff er1 + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ; -> 0100 1011 0100 1011 0100 1011 0100 1011 + cmp.l #0x4b4b4b4b, @long_dest + beq .Llindexl321 + fail +.Llindexl321: + mov.l #0xa5a5a5a5, @long_dest +.endif + +rotl_l_reg32_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotl.l #2, er0 ; shift left arithmetic by two + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ; -> 1001 0110 1001 0110 1001 0110 1001 0110 + test_h_gr32 0x96969696 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +rotl_l_indexb16_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov.b #5, r0l + rotl.l #2, @(long_dest-20:16, er0.b) ; indexed long/byte + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 0xa5a5a505 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ; -> 1001 0110 1001 0110 1001 0110 1001 0110 + cmp.l #0x96969696, @long_dest + beq .Llindexb162 + fail +.Llindexb162: + mov.l #0xa5a5a5a5, @long_dest + +rotl_l_indexw16_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov.w #256, r0 + rotl.l #2, @(long_dest-1024:16, er0.w) ; indexed long/word + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 0xa5a50100 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ; -> 1001 0110 1001 0110 1001 0110 1001 0110 + cmp.l #0x96969696, @long_dest + beq .Llindexw162 + fail +.Llindexw162: + mov.l #0xa5a5a5a5, @long_dest + +rotl_l_indexl16_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov.l #0xffffffff, er0 + rotl.l #2, @(long_dest+4:16, er0.l) ; indexed long/long + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 0xffffffff er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ; -> 1001 0110 1001 0110 1001 0110 1001 0110 + cmp.l #0x96969696, @long_dest + beq .Llindexl162 + fail +.Llindexl162: + mov.l #0xa5a5a5a5, @long_dest + +rotl_l_indexb32_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov.b #5, r1l + rotl.l #2, @(long_dest-20:32, er1.b) ; indexed long/byte + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 0xa5a5a505 er1 + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ; -> 1001 0110 1001 0110 1001 0110 1001 0110 + cmp.l #0x96969696, @long_dest + beq .Llindexb322 + fail +.Llindexb322: + mov.l #0xa5a5a5a5, @long_dest + +rotl_l_indexw32_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov.w #256, r1 + rotl.l #2, @(long_dest-1024:32, er1.w) ; indexed long/byte + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 0xa5a50100 er1 + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ; -> 1001 0110 1001 0110 1001 0110 1001 0110 + cmp.l #0x96969696, @long_dest + beq .Llindexw322 + fail +.Llindexw322: + mov.l #0xa5a5a5a5, @long_dest + +rotl_l_indexl32_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov.l #0xffffffff, er1 + rotl.l #2, @(long_dest+4:32, er1.l) ; indexed long/byte + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 0xffffffff er1 + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ; -> 1001 0110 1001 0110 1001 0110 1001 0110 + cmp.l #0x96969696, @long_dest + beq .Llindexl322 + fail +.Llindexl322: + mov.l #0xa5a5a5a5, @long_dest +.endif +.endif + + pass + + exit 0 + diff --git a/sim/testsuite/sim/h8300/rotr.s b/sim/testsuite/sim/h8300/rotr.s new file mode 100644 index 0000000..2a964c1 --- /dev/null +++ b/sim/testsuite/sim/h8300/rotr.s @@ -0,0 +1,1802 @@ +# Hitachi H8 testcase 'rotr' +# mach(): all +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + start + + .data +byte_dest: .byte 0xa5 + .align 2 +word_dest: .word 0xa5a5 + .align 4 +long_dest: .long 0xa5a5a5a5 + + .text + +rotr_b_reg8_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotr.b r0l ; shift right arithmetic by one + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr16 0xa5d2 r0 ; 1010 0101 -> 1101 0010 +.if (sim_cpu) + test_h_gr32 0xa5a5a5d2 er0 +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +rotr_b_ind_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest, er0 + rotr.b @er0 ; shift right arithmetic by one, indirect + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 byte_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 1101 0010 + cmp.b #0xd2, @byte_dest + beq .Lbind1 + fail +.Lbind1: + mov.b #0xa5, @byte_dest + +rotr_b_postinc_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest, er0 + rotr.b @er0+ ; shift right arithmetic by one, postinc + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 byte_dest+1 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 1101 0010 + cmp.b #0xd2, @byte_dest + beq .Lbpostinc1 + fail +.Lbpostinc1: + mov.b #0xa5, @byte_dest + +rotr_b_postdec_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest, er0 + rotr.b @er0- ; shift right arithmetic by one, postdec + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 byte_dest-1 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 1101 0010 + cmp.b #0xd2, @byte_dest + beq .Lbpostdec1 + fail +.Lbpostdec1: + mov.b #0xa5, @byte_dest + +rotr_b_preinc_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest-1, er0 + rotr.b @+er0 ; shift right arithmetic by one, preinc + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 byte_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 1101 0010 + cmp.b #0xd2, @byte_dest + beq .Lbpreinc1 + fail +.Lbpreinc1: + mov.b #0xa5, @byte_dest + +rotr_b_predec_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest+1, er0 + rotr.b @-er0 ; shift right arithmetic by one, predec + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 byte_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 1101 0010 + cmp.b #0xd2, @byte_dest + beq .Lbpredec1 + fail +.Lbpredec1: + mov.b #0xa5, @byte_dest + +rotr_b_disp2_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest-2, er0 + rotr.b @(2:2, er0) ; shift right arithmetic by one, disp2 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 byte_dest-2 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 1101 0010 + cmp.b #0xd2, @byte_dest + beq .Lbdisp21 + fail +.Lbdisp21: + mov.b #0xa5, @byte_dest + +rotr_b_disp16_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest-44, er0 + rotr.b @(44:16, er0) ; shift right arithmetic by one, disp16 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 byte_dest-44 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 1101 0010 + cmp.b #0xd2, @byte_dest + beq .Lbdisp161 + fail +.Lbdisp161: + mov.b #0xa5, @byte_dest + +rotr_b_disp32_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest-666, er0 + rotr.b @(666:32, er0) ; shift right arithmetic by one, disp32 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 byte_dest-666 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 1101 0010 + cmp.b #0xd2, @byte_dest + beq .Lbdisp321 + fail +.Lbdisp321: + mov.b #0xa5, @byte_dest + +rotr_b_abs16_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotr.b @byte_dest:16 ; shift right arithmetic by one, abs16 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 1101 0010 + cmp.b #0xd2, @byte_dest + beq .Lbabs161 + fail +.Lbabs161: + mov.b #0xa5, @byte_dest + +rotr_b_abs32_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotr.b @byte_dest:32 ; shift right arithmetic by one, abs32 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 1101 0010 + cmp.b #0xd2, @byte_dest + beq .Lbabs321 + fail +.Lbabs321: + mov.b #0xa5, @byte_dest +.endif + +rotr_b_reg8_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotr.b #2, r0l ; shift right arithmetic by two + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + test_h_gr16 0xa569 r0 ; 1010 0101 -> 0110 1001 +.if (sim_cpu) + test_h_gr32 0xa5a5a569 er0 +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +rotr_b_ind_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest, er0 + rotr.b #2, @er0 ; shift right arithmetic by two, indirect + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 byte_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0110 1001 + cmp.b #0x69, @byte_dest + beq .Lbind2 + fail +.Lbind2: + mov.b #0xa5, @byte_dest + +rotr_b_postinc_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest, er0 + rotr.b #2, @er0+ ; shift right arithmetic by two, postinc + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 byte_dest+1 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0110 1001 + cmp.b #0x69, @byte_dest + beq .Lbpostinc2 + fail +.Lbpostinc2: + mov.b #0xa5, @byte_dest + +rotr_b_postdec_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest, er0 + rotr.b #2, @er0- ; shift right arithmetic by two, postdec + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 byte_dest-1 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0110 1001 + cmp.b #0x69, @byte_dest + beq .Lbpostdec2 + fail +.Lbpostdec2: + mov.b #0xa5, @byte_dest + +rotr_b_preinc_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest-1, er0 + rotr.b #2, @+er0 ; shift right arithmetic by two, preinc + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 byte_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0110 1001 + cmp.b #0x69, @byte_dest + beq .Lbpreinc2 + fail +.Lbpreinc2: + mov.b #0xa5, @byte_dest + +rotr_b_predec_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest+1, er0 + rotr.b #2, @-er0 ; shift right arithmetic by two, predec + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 byte_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0110 1001 + cmp.b #0x69, @byte_dest + beq .Lbpredec2 + fail +.Lbpredec2: + mov.b #0xa5, @byte_dest + +rotr_b_disp2_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest-2, er0 + rotr.b #2, @(2:2, er0) ; shift right arithmetic by two, disp2 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 byte_dest-2 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0110 1001 + cmp.b #0x69, @byte_dest + beq .Lbdisp22 + fail +.Lbdisp22: + mov.b #0xa5, @byte_dest + +rotr_b_disp16_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest-44, er0 + rotr.b #2, @(44:16, er0) ; shift right arithmetic by two, disp16 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 byte_dest-44 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0110 1001 + cmp.b #0x69, @byte_dest + beq .Lbdisp162 + fail +.Lbdisp162: + mov.b #0xa5, @byte_dest + +rotr_b_disp32_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest-666, er0 + rotr.b #2, @(666:32, er0) ; shift right arithmetic by two, disp32 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 byte_dest-666 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0110 1001 + cmp.b #0x69, @byte_dest + beq .Lbdisp322 + fail +.Lbdisp322: + mov.b #0xa5, @byte_dest + +rotr_b_abs16_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotr.b #2, @byte_dest:16 ; shift right arithmetic by two, abs16 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0110 1001 + cmp.b #0x69, @byte_dest + beq .Lbabs162 + fail +.Lbabs162: + mov.b #0xa5, @byte_dest + +rotr_b_abs32_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotr.b #2, @byte_dest:32 ; shift right arithmetic by two, abs32 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0110 1001 + cmp.b #0x69, @byte_dest + beq .Lbabs322 + fail +.Lbabs322: + mov.b #0xa5, @byte_dest +.endif + +.if (sim_cpu) ; Not available in h8300 mode +rotr_w_reg16_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotr.w r0 ; shift right arithmetic by one + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + test_h_gr16 0xd2d2 r0 ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 + test_h_gr32 0xa5a5d2d2 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +rotr_w_ind_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest, er0 + rotr.w @er0 ; shift right arithmetic by one, indirect + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 word_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 + cmp.w #0xd2d2, @word_dest + beq .Lwind1 + fail +.Lwind1: + mov.w #0xa5a5, @word_dest + +rotr_w_postinc_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest, er0 + rotr.w @er0+ ; shift right arithmetic by one, postinc + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 word_dest+2 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 + cmp.w #0xd2d2, @word_dest + beq .Lwpostinc1 + fail +.Lwpostinc1: + mov.w #0xa5a5, @word_dest + +rotr_w_postdec_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest, er0 + rotr.w @er0- ; shift right arithmetic by one, postdec + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 word_dest-2 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 + cmp.w #0xd2d2, @word_dest + beq .Lwpostdec1 + fail +.Lwpostdec1: + mov.w #0xa5a5, @word_dest + +rotr_w_preinc_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest-2, er0 + rotr.w @+er0 ; shift right arithmetic by one, preinc + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 word_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 + cmp.w #0xd2d2, @word_dest + beq .Lwpreinc1 + fail +.Lwpreinc1: + mov.w #0xa5a5, @word_dest + +rotr_w_predec_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest+2, er0 + rotr.w @-er0 ; shift right arithmetic by one, predec + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 word_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 + cmp.w #0xd2d2, @word_dest + beq .Lwpredec1 + fail +.Lwpredec1: + mov.w #0xa5a5, @word_dest + +rotr_w_disp2_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest-4, er0 + rotr.w @(4:2, er0) ; shift right arithmetic by one, disp2 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 word_dest-4 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 + cmp.w #0xd2d2, @word_dest + beq .Lwdisp21 + fail +.Lwdisp21: + mov.w #0xa5a5, @word_dest + +rotr_w_disp16_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest-44, er0 + rotr.w @(44:16, er0) ; shift right arithmetic by one, disp16 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 word_dest-44 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 + cmp.w #0xd2d2, @word_dest + beq .Lwdisp161 + fail +.Lwdisp161: + mov.w #0xa5a5, @word_dest + +rotr_w_disp32_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest-666, er0 + rotr.w @(666:32, er0) ; shift right arithmetic by one, disp32 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 word_dest-666 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 + cmp.w #0xd2d2, @word_dest + beq .Lwdisp321 + fail +.Lwdisp321: + mov.w #0xa5a5, @word_dest + +rotr_w_abs16_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotr.w @word_dest:16 ; shift right arithmetic by one, abs16 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 + cmp.w #0xd2d2, @word_dest + beq .Lwabs161 + fail +.Lwabs161: + mov.w #0xa5a5, @word_dest + +rotr_w_abs32_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotr.w @word_dest:32 ; shift right arithmetic by one, abs32 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 + cmp.w #0xd2d2, @word_dest + beq .Lwabs321 + fail +.Lwabs321: + mov.w #0xa5a5, @word_dest +.endif + +rotr_w_reg16_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotr.w #2, r0 ; shift right arithmetic by two + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr16 0x6969 r0 ; 1010 0101 1010 0101 -> 0110 1001 0110 1001 + test_h_gr32 0xa5a56969 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +rotr_w_ind_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest, er0 + rotr.w #2, @er0 ; shift right arithmetic by two, indirect + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0110 1001 0110 1001 + cmp.w #0x6969, @word_dest + beq .Lwind2 + fail +.Lwind2: + mov.w #0xa5a5, @word_dest + +rotr_w_postinc_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest, er0 + rotr.w #2, @er0+ ; shift right arithmetic by two, postinc + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest+2 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0110 1001 0110 1001 + cmp.w #0x6969, @word_dest + beq .Lwpostinc2 + fail +.Lwpostinc2: + mov.w #0xa5a5, @word_dest + +rotr_w_postdec_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest, er0 + rotr.w #2, @er0- ; shift right arithmetic by two, postdec + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest-2 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0110 1001 0110 1001 + cmp.w #0x6969, @word_dest + beq .Lwpostdec2 + fail +.Lwpostdec2: + mov.w #0xa5a5, @word_dest + +rotr_w_preinc_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest-2, er0 + rotr.w #2, @+er0 ; shift right arithmetic by two, preinc + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0110 1001 0110 1001 + cmp.w #0x6969, @word_dest + beq .Lwpreinc2 + fail +.Lwpreinc2: + mov.w #0xa5a5, @word_dest + +rotr_w_predec_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest+2, er0 + rotr.w #2, @-er0 ; shift right arithmetic by two, predec + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0110 1001 0110 1001 + cmp.w #0x6969, @word_dest + beq .Lwpredec2 + fail +.Lwpredec2: + mov.w #0xa5a5, @word_dest + +rotr_w_disp2_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest-4, er0 + rotr.w #2, @(4:2, er0) ; shift right arithmetic by two, disp2 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest-4 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0110 1001 0110 1001 + cmp.w #0x6969, @word_dest + beq .Lwdisp22 + fail +.Lwdisp22: + mov.w #0xa5a5, @word_dest + +rotr_w_disp16_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest-44, er0 + rotr.w #2, @(44:16, er0) ; shift right arithmetic by two, disp16 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest-44 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0110 1001 0110 1001 + cmp.w #0x6969, @word_dest + beq .Lwdisp162 + fail +.Lwdisp162: + mov.w #0xa5a5, @word_dest + +rotr_w_disp32_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest-666, er0 + rotr.w #2, @(666:32, er0) ; shift right arithmetic by two, disp32 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest-666 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0110 1001 0110 1001 + cmp.w #0x6969, @word_dest + beq .Lwdisp322 + fail +.Lwdisp322: + mov.w #0xa5a5, @word_dest + +rotr_w_abs16_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotr.w #2, @word_dest:16 ; shift right arithmetic by two, abs16 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0110 1001 0110 1001 + cmp.w #0x6969, @word_dest + beq .Lwabs162 + fail +.Lwabs162: + mov.w #0xa5a5, @word_dest + +rotr_w_abs32_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotr.w #2, @word_dest:32 ; shift right arithmetic by two, abs32 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0110 1001 0110 1001 + cmp.w #0x6969, @word_dest + beq .Lwabs322 + fail +.Lwabs322: + mov.w #0xa5a5, @word_dest +.endif + +rotr_l_reg32_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotr.l er0 ; shift right arithmetic by one, register + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ; -> 1101 0010 1101 0010 1101 0010 1101 0010 + test_h_gr32 0xd2d2d2d2 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +rotr_l_ind_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest, er0 + rotr.l @er0 ; shift right arithmetic by one, indirect + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 long_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 1101 0010 1101 0010 1101 0010 1101 0010 + cmp.l #0xd2d2d2d2, @long_dest + beq .Llind1 + fail +.Llind1: + mov #0xa5a5a5a5, @long_dest + +rotr_l_postinc_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest, er0 + rotr.l @er0+ ; shift right arithmetic by one, postinc + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 long_dest+4 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 1101 0010 1101 0010 1101 0010 1101 0010 + cmp.l #0xd2d2d2d2, @long_dest + beq .Llpostinc1 + fail +.Llpostinc1: + mov #0xa5a5a5a5, @long_dest + +rotr_l_postdec_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest, er0 + rotr.l @er0- ; shift right arithmetic by one, postdec + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 long_dest-4 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 1101 0010 1101 0010 1101 0010 1101 0010 + cmp.l #0xd2d2d2d2, @long_dest + beq .Llpostdec1 + fail +.Llpostdec1: + mov #0xa5a5a5a5, @long_dest + +rotr_l_preinc_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest-4, er0 + rotr.l @+er0 ; shift right arithmetic by one, preinc + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 long_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 1101 0010 1101 0010 1101 0010 1101 0010 + cmp.l #0xd2d2d2d2, @long_dest + beq .Llpreinc1 + fail +.Llpreinc1: + mov #0xa5a5a5a5, @long_dest + +rotr_l_predec_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest+4, er0 + rotr.l @-er0 ; shift right arithmetic by one, predec + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 long_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 1101 0010 1101 0010 1101 0010 1101 0010 + cmp.l #0xd2d2d2d2, @long_dest + beq .Llpredec1 + fail +.Llpredec1: + mov #0xa5a5a5a5, @long_dest + +rotr_l_disp2_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest-8, er0 + rotr.l @(8:2, er0) ; shift right arithmetic by one, disp2 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 long_dest-8 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 1101 0010 1101 0010 1101 0010 1101 0010 + cmp.l #0xd2d2d2d2, @long_dest + beq .Lldisp21 + fail +.Lldisp21: + mov #0xa5a5a5a5, @long_dest + +rotr_l_disp16_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest-44, er0 + rotr.l @(44:16, er0) ; shift right arithmetic by one, disp16 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 long_dest-44 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 1101 0010 1101 0010 1101 0010 1101 0010 + cmp.l #0xd2d2d2d2, @long_dest + beq .Lldisp161 + fail +.Lldisp161: + mov #0xa5a5a5a5, @long_dest + +rotr_l_disp32_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest-666, er0 + rotr.l @(666:32, er0) ; shift right arithmetic by one, disp32 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 long_dest-666 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 1101 0010 1101 0010 1101 0010 1101 0010 + cmp.l #0xd2d2d2d2, @long_dest + beq .Lldisp321 + fail +.Lldisp321: + mov #0xa5a5a5a5, @long_dest + +rotr_l_abs16_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotr.l @long_dest:16 ; shift right arithmetic by one, abs16 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 1101 0010 1101 0010 1101 0010 1101 0010 + cmp.l #0xd2d2d2d2, @long_dest + beq .Llabs161 + fail +.Llabs161: + mov #0xa5a5a5a5, @long_dest + +rotr_l_abs32_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotr.l @long_dest:32 ; shift right arithmetic by one, abs32 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 1101 0010 1101 0010 1101 0010 1101 0010 + cmp.l #0xd2d2d2d2, @long_dest + beq .Llabs321 + fail +.Llabs321: + mov #0xa5a5a5a5, @long_dest +.endif + +rotr_l_reg32_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotr.l #2, er0 ; shift right arithmetic by two, register + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ; -> 0110 1001 0110 1001 0110 1001 0110 1001 + test_h_gr32 0x69696969 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) + +rotr_l_ind_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest, er0 + rotr.l #2, @er0 ; shift right arithmetic by two, indirect + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0110 1001 0110 1001 0110 1001 0110 1001 + cmp.l #0x69696969, @long_dest + beq .Llind2 + fail +.Llind2: + mov #0xa5a5a5a5, @long_dest + +rotr_l_postinc_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest, er0 + rotr.l #2, @er0+ ; shift right arithmetic by two, postinc + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest+4 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0110 1001 0110 1001 0110 1001 0110 1001 + cmp.l #0x69696969, @long_dest + beq .Llpostinc2 + fail +.Llpostinc2: + mov #0xa5a5a5a5, @long_dest + +rotr_l_postdec_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest, er0 + rotr.l #2, @er0- ; shift right arithmetic by two, postdec + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest-4 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0110 1001 0110 1001 0110 1001 0110 1001 + cmp.l #0x69696969, @long_dest + beq .Llpostdec2 + fail +.Llpostdec2: + mov #0xa5a5a5a5, @long_dest + +rotr_l_preinc_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest-4, er0 + rotr.l #2, @+er0 ; shift right arithmetic by two, preinc + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0110 1001 0110 1001 0110 1001 0110 1001 + cmp.l #0x69696969, @long_dest + beq .Llpreinc2 + fail +.Llpreinc2: + mov #0xa5a5a5a5, @long_dest + +rotr_l_predec_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest+4, er0 + rotr.l #2, @-er0 ; shift right arithmetic by two, predec + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0110 1001 0110 1001 0110 1001 0110 1001 + cmp.l #0x69696969, @long_dest + beq .Llpredec2 + fail +.Llpredec2: + mov #0xa5a5a5a5, @long_dest + +rotr_l_disp2_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest-8, er0 + rotr.l #2, @(8:2, er0) ; shift right arithmetic by two, disp2 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest-8 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0110 1001 0110 1001 0110 1001 0110 1001 + cmp.l #0x69696969, @long_dest + beq .Lldisp22 + fail +.Lldisp22: + mov #0xa5a5a5a5, @long_dest + +rotr_l_disp16_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest-44, er0 + rotr.l #2, @(44:16, er0) ; shift right arithmetic by two, disp16 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest-44 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0110 1001 0110 1001 0110 1001 0110 1001 + cmp.l #0x69696969, @long_dest + beq .Lldisp162 + fail +.Lldisp162: + mov #0xa5a5a5a5, @long_dest + +rotr_l_disp32_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest-666, er0 + rotr.l #2, @(666:32, er0) ; shift right arithmetic by two, disp32 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest-666 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0110 1001 0110 1001 0110 1001 0110 1001 + cmp.l #0x69696969, @long_dest + beq .Lldisp322 + fail +.Lldisp322: + mov #0xa5a5a5a5, @long_dest + +rotr_l_abs16_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotr.l #2, @long_dest:16 ; shift right arithmetic by two, abs16 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0110 1001 0110 1001 0110 1001 0110 1001 + cmp.l #0x69696969, @long_dest + beq .Llabs162 + fail +.Llabs162: + mov #0xa5a5a5a5, @long_dest + +rotr_l_abs32_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotr.l #2, @long_dest:32 ; shift right arithmetic by two, abs32 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0110 1001 0110 1001 0110 1001 0110 1001 + cmp.l #0x69696969, @long_dest + beq .Llabs322 + fail +.Llabs322: + mov #0xa5a5a5a5, @long_dest + +.endif +.endif + pass + + exit 0 + diff --git a/sim/testsuite/sim/h8300/rotxl.s b/sim/testsuite/sim/h8300/rotxl.s new file mode 100644 index 0000000..3ae703e --- /dev/null +++ b/sim/testsuite/sim/h8300/rotxl.s @@ -0,0 +1,167 @@ +# Hitachi H8 testcase 'rotxl' +# mach(): all +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + start + + .data +byte_dest: .byte 0xa5 + .align 2 +word_dest: .word 0xa5a5 + .align 4 +long_dest: .long 0xa5a5a5a5 + + .text + +rotxl_b_reg8_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotxl.b r0l ; shift left arithmetic by one +;;; .word 0x1208 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + test_h_gr16 0xa54a r0 ; 1010 0101 -> 0100 1010 +.if (sim_cpu) + test_h_gr32 0xa5a5a54a er0 +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +rotxl_b_reg8_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotxl.b #2, r0l ; shift left arithmetic by two +;;; .word 0x1248 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr16 0xa595 r0 ; 1010 0101 -> 1001 0101 +.if (sim_cpu) + test_h_gr32 0xa5a5a595 er0 +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu) ; Not available in h8300 mode +rotxl_w_reg16_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotxl.w r0 ; shift left arithmetic by one +;;; .word 0x1210 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + test_h_gr16 0x4b4a r0 ; 1010 0101 1010 0101 -> 0100 1011 0100 1010 + test_h_gr32 0xa5a54b4a er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +rotxl_w_reg16_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotxl.w #2, r0 ; shift left arithmetic by two +;;; .word 0x1250 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + test_h_gr16 0x9695 r0 ; 1010 0101 1010 0101 -> 1001 0110 1001 0101 + test_h_gr32 0xa5a59695 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +rotxl_l_reg32_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotxl.l er0 ; shift left arithmetic by one +;;; .word 1030 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ; -> 0100 1011 0100 1011 0100 1011 0100 1010 + test_h_gr32 0x4b4b4b4a er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +rotxl_l_reg32_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotxl.l #2, er0 ; shift left arithmetic by two +;;; .word 0x1270 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ; -> 1001 0110 1001 0110 1001 0110 1001 0101 + test_h_gr32 0x96969695 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.endif + + pass + + exit 0 + diff --git a/sim/testsuite/sim/h8300/rotxr.s b/sim/testsuite/sim/h8300/rotxr.s new file mode 100644 index 0000000..96ec8a1 --- /dev/null +++ b/sim/testsuite/sim/h8300/rotxr.s @@ -0,0 +1,2002 @@ +# Hitachi H8 testcase 'rotxr' +# mach(): all +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + start + + .data +byte_dest: .byte 0xa5 + .align 2 +word_dest: .word 0xa5a5 + .align 4 +long_dest: .long 0xa5a5a5a5 + + .text + +rotxr_b_reg8_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotxr.b r0l ; shift right arithmetic by one +;;; .word 0x1308 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr16 0xa552 r0 ; 1010 0101 -> 0101 0010 +.if (sim_cpu) + test_h_gr32 0xa5a5a552 er0 +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +rotxr_b_ind_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest, er0 + rotxr.b @er0 ; shift right arithmetic by one, indirect +;;; .word 0x7d00 +;;; .word 0x1300 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 byte_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0101 0010 + cmp.b #0x52, @byte_dest + beq .Lbind1 + fail +.Lbind1: + mov #0xa5a5a5a5, @byte_dest + +rotxr_b_postinc_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest, er0 + rotxr.b @er0+ ; shift right arithmetic by one, postinc +;;; .word 0x0174 +;;; .word 0x6c08 +;;; .word 0x1300 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 byte_dest+1 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0101 0010 + cmp.b #0x52, @byte_dest + beq .Lbpostinc1 + fail +.Lbpostinc1: + mov #0xa5a5a5a5, @byte_dest + +rotxr_b_postdec_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest, er0 + rotxr.b @er0- ; shift right arithmetic by one, postdec +;;; .word 0x0176 +;;; .word 0x6c08 +;;; .word 0x1300 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 byte_dest-1 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0101 0010 + cmp.b #0x52, @byte_dest + beq .Lbpostdec1 + fail +.Lbpostdec1: + mov #0xa5a5a5a5, @byte_dest + +rotxr_b_preinc_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest-1, er0 + rotxr.b @+er0 ; shift right arithmetic by one, preinc +;;; .word 0x0175 +;;; .word 0x6c08 +;;; .word 0x1300 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 byte_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0101 0010 + cmp.b #0x52, @byte_dest + beq .Lbpreinc1 + fail +.Lbpreinc1: + mov #0xa5a5a5a5, @byte_dest + +rotxr_b_predec_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest+1, er0 + rotxr.b @-er0 ; shift right arithmetic by one, predec +;;; .word 0x0177 +;;; .word 0x6c08 +;;; .word 0x1300 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 byte_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0101 0010 + cmp.b #0x52, @byte_dest + beq .Lbpredec1 + fail +.Lbpredec1: + mov #0xa5a5a5a5, @byte_dest + +rotxr_b_disp2_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest-2, er0 + rotxr.b @(2:2, er0) ; shift right arithmetic by one, disp2 +;;; .word 0x0176 +;;; .word 0x6808 +;;; .word 0x1300 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 byte_dest-2 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0101 0010 + cmp.b #0x52, @byte_dest + beq .Lbdisp21 + fail +.Lbdisp21: + mov #0xa5a5a5a5, @byte_dest + +rotxr_b_disp16_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest-44, er0 + rotxr.b @(44:16, er0) ; shift right arithmetic by one, disp16 +;;; .word 0x0174 +;;; .word 0x6e08 +;;; .word 44 +;;; .word 0x1300 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 byte_dest-44 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0101 0010 + cmp.b #0x52, @byte_dest + beq .Lbdisp161 + fail +.Lbdisp161: + mov #0xa5a5a5a5, @byte_dest + +rotxr_b_disp32_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest-666, er0 + rotxr.b @(666:32, er0) ; shift right arithmetic by one, disp32 +;;; .word 0x7884 +;;; .word 0x6a28 +;;; .long 666 +;;; .word 0x1300 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 byte_dest-666 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0101 0010 + cmp.b #0x52, @byte_dest + beq .Lbdisp321 + fail +.Lbdisp321: + mov #0xa5a5a5a5, @byte_dest + +rotxr_b_abs16_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotxr.b @byte_dest:16 ; shift right arithmetic by one, abs16 +;;; .word 0x6a18 +;;; .word byte_dest +;;; .word 0x1300 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0101 0010 + cmp.b #0x52, @byte_dest + beq .Lbabs161 + fail +.Lbabs161: + mov #0xa5a5a5a5, @byte_dest + +rotxr_b_abs32_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotxr.b @byte_dest:32 ; shift right arithmetic by one, abs32 +;;; .word 0x6a38 +;;; .long byte_dest +;;; .word 0x1300 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0101 0010 + cmp.b #0x52, @byte_dest + beq .Lbabs321 + fail +.Lbabs321: + mov #0xa5a5a5a5, @byte_dest +.endif + +rotxr_b_reg8_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotxr.b #2, r0l ; shift right arithmetic by two +;;; .word 0x1348 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr16 0xa5a9 r0 ; 1010 0101 -> 1010 1001 +.if (sim_cpu) + test_h_gr32 0xa5a5a5a9 er0 +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +rotxr_b_ind_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest, er0 + rotxr.b #2, @er0 ; shift right arithmetic by two, indirect +;;; .word 0x7d00 +;;; .word 0x1340 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 byte_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 1010 1001 + cmp.b #0xa9, @byte_dest + beq .Lbind2 + fail +.Lbind2: + mov #0xa5a5a5a5, @byte_dest + +rotxr_b_postinc_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest, er0 + rotxr.b #2, @er0+ ; shift right arithmetic by two, postinc +;;; .word 0x0174 +;;; .word 0x6c08 +;;; .word 0x1340 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 byte_dest+1 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 1010 1001 + cmp.b #0xa9, @byte_dest + beq .Lbpostinc2 + fail +.Lbpostinc2: + mov #0xa5a5a5a5, @byte_dest + +rotxr_b_postdec_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest, er0 + rotxr.b #2, @er0- ; shift right arithmetic by two, postdec +;;; .word 0x0176 +;;; .word 0x6c08 +;;; .word 0x1340 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 byte_dest-1 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 1010 1001 + cmp.b #0xa9, @byte_dest + beq .Lbpostdec2 + fail +.Lbpostdec2: + mov #0xa5a5a5a5, @byte_dest + +rotxr_b_preinc_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest-1, er0 + rotxr.b #2, @+er0 ; shift right arithmetic by two, preinc +;;; .word 0x0175 +;;; .word 0x6c08 +;;; .word 0x1340 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 byte_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 1010 1001 + cmp.b #0xa9, @byte_dest + beq .Lbpreinc2 + fail +.Lbpreinc2: + mov #0xa5a5a5a5, @byte_dest + +rotxr_b_predec_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest+1, er0 + rotxr.b #2, @-er0 ; shift right arithmetic by two, predec +;;; .word 0x0177 +;;; .word 0x6c08 +;;; .word 0x1340 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 byte_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 1010 1001 + cmp.b #0xa9, @byte_dest + beq .Lbpredec2 + fail +.Lbpredec2: + mov #0xa5a5a5a5, @byte_dest + +rotxr_b_disp2_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest-2, er0 + rotxr.b #2, @(2:2, er0) ; shift right arithmetic by two, disp2 +;;; .word 0x0176 +;;; .word 0x6808 +;;; .word 0x1340 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 byte_dest-2 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 1010 1001 + cmp.b #0xa9, @byte_dest + beq .Lbdisp22 + fail +.Lbdisp22: + mov #0xa5a5a5a5, @byte_dest + +rotxr_b_disp16_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest-44, er0 + rotxr.b #2, @(44:16, er0) ; shift right arithmetic by two, disp16 +;;; .word 0x0174 +;;; .word 0x6e08 +;;; .word 44 +;;; .word 0x1340 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 byte_dest-44 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 1010 1001 + cmp.b #0xa9, @byte_dest + beq .Lbdisp162 + fail +.Lbdisp162: + mov #0xa5a5a5a5, @byte_dest + +rotxr_b_disp32_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest-666, er0 + rotxr.b #2, @(666:32, er0) ; shift right arithmetic by two, disp32 +;;; .word 0x7884 +;;; .word 0x6a28 +;;; .long 666 +;;; .word 0x1340 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 byte_dest-666 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 1010 1001 + cmp.b #0xa9, @byte_dest + beq .Lbdisp322 + fail +.Lbdisp322: + mov #0xa5a5a5a5, @byte_dest + +rotxr_b_abs16_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotxr.b #2, @byte_dest:16 ; shift right arithmetic by two, abs16 +;;; .word 0x6a18 +;;; .word byte_dest +;;; .word 0x1340 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 1010 1001 + cmp.b #0xa9, @byte_dest + beq .Lbabs162 + fail +.Lbabs162: + mov #0xa5a5a5a5, @byte_dest + +rotxr_b_abs32_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotxr.b #2, @byte_dest:32 ; shift right arithmetic by two, abs32 +;;; .word 0x6a38 +;;; .long byte_dest +;;; .word 0x1340 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 1010 1001 + cmp.b #0xa9, @byte_dest + beq .Lbabs322 + fail +.Lbabs322: + mov #0xa5a5a5a5, @byte_dest +.endif + +.if (sim_cpu) ; Not available in h8300 mode +rotxr_w_reg16_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotxr.w r0 ; shift right arithmetic by one +;;; .word 0x1310 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr16 0x52d2 r0 ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 + test_h_gr32 0xa5a552d2 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +rotxr_w_ind_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest, er0 + rotxr.w @er0 ; shift right arithmetic by one, indirect +;;; .word 0x7d80 +;;; .word 0x1310 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 + cmp.w #0x52d2, @word_dest + beq .Lwind1 + fail +.Lwind1: + mov #0xa5a5a5a5, @word_dest + +rotxr_w_postinc_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest, er0 + rotxr.w @er0+ ; shift right arithmetic by one, postinc +;;; .word 0x0154 +;;; .word 0x6d08 +;;; .word 0x1310 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest+2 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 + cmp.w #0x52d2, @word_dest + beq .Lwpostinc1 + fail +.Lwpostinc1: + mov #0xa5a5a5a5, @word_dest + +rotxr_w_postdec_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest, er0 + rotxr.w @er0- ; shift right arithmetic by one, postdec +;;; .word 0x0156 +;;; .word 0x6d08 +;;; .word 0x1310 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest-2 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 + cmp.w #0x52d2, @word_dest + beq .Lwpostdec1 + fail +.Lwpostdec1: + mov #0xa5a5a5a5, @word_dest + +rotxr_w_preinc_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest-2, er0 + rotxr.w @+er0 ; shift right arithmetic by one, preinc +;;; .word 0x0155 +;;; .word 0x6d08 +;;; .word 0x1310 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 + cmp.w #0x52d2, @word_dest + beq .Lwpreinc1 + fail +.Lwpreinc1: + mov #0xa5a5a5a5, @word_dest + +rotxr_w_predec_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest+2, er0 + rotxr.w @-er0 ; shift right arithmetic by one, predec +;;; .word 0x0157 +;;; .word 0x6d08 +;;; .word 0x1310 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 + cmp.w #0x52d2, @word_dest + beq .Lwpredec1 + fail +.Lwpredec1: + mov #0xa5a5a5a5, @word_dest + +rotxr_w_disp2_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest-4, er0 + rotxr.w @(4:2, er0) ; shift right arithmetic by one, disp2 +;;; .word 0x0156 +;;; .word 0xa908 +;;; .word 0x1310 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest-4 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 + cmp.w #0x52d2, @word_dest + beq .Lwdisp21 + fail +.Lwdisp21: + mov #0xa5a5a5a5, @word_dest + +rotxr_w_disp16_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest-44, er0 + rotxr.w @(44:16, er0) ; shift right arithmetic by one, disp16 +;;; .word 0x0154 +;;; .word 0x6f08 +;;; .word 44 +;;; .word 0x1310 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest-44 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 + cmp.w #0x52d2, @word_dest + beq .Lwdisp161 + fail +.Lwdisp161: + mov #0xa5a5a5a5, @word_dest + +rotxr_w_disp32_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest-666, er0 + rotxr.w @(666:32, er0) ; shift right arithmetic by one, disp32 +;;; .word 0x7884 +;;; .word 0x6b28 +;;; .long 666 +;;; .word 0x1310 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest-666 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 + cmp.w #0x52d2, @word_dest + beq .Lwdisp321 + fail +.Lwdisp321: + mov #0xa5a5a5a5, @word_dest + +rotxr_w_abs16_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotxr.w @word_dest:16 ; shift right arithmetic by one, abs16 +;;; .word 0x6b18 +;;; .word word_dest +;;; .word 0x1310 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 + cmp.w #0x52d2, @word_dest + beq .Lwabs161 + fail +.Lwabs161: + mov #0xa5a5a5a5, @word_dest + +rotxr_w_abs32_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotxr.w @word_dest:32 ; shift right arithmetic by one, abs32 +;;; .word 0x6b38 +;;; .long word_dest +;;; .word 0x1310 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 + cmp.w #0x52d2, @word_dest + beq .Lwabs321 + fail +.Lwabs321: + mov #0xa5a5a5a5, @word_dest +.endif + +rotxr_w_reg16_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotxr.w #2, r0 ; shift right arithmetic by two +;;; .word 0x1350 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr16 0xa969 r0 ; 1010 0101 1010 0101 -> 1010 1001 0110 1001 + test_h_gr32 0xa5a5a969 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +rotxr_w_ind_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest, er0 + rotxr.w #2, @er0 ; shift right arithmetic by two, indirect +;;; .word 0x7d80 +;;; .word 0x1350 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 word_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 1010 1001 0110 1001 + cmp.w #0xa969, @word_dest + beq .Lwind2 + fail +.Lwind2: + mov #0xa5a5a5a5, @word_dest + +rotxr_w_postinc_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest, er0 + rotxr.w #2, @er0+ ; shift right arithmetic by two, postinc +;;; .word 0x0154 +;;; .word 0x6d08 +;;; .word 0x1350 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 word_dest+2 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 1010 1001 0110 1001 + cmp.w #0xa969, @word_dest + beq .Lwpostinc2 + fail +.Lwpostinc2: + mov #0xa5a5a5a5, @word_dest + +rotxr_w_postdec_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest, er0 + rotxr.w #2, @er0- ; shift right arithmetic by two, postdec +;;; .word 0x0156 +;;; .word 0x6d08 +;;; .word 0x1350 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 word_dest-2 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 1010 1001 0110 1001 + cmp.w #0xa969, @word_dest + beq .Lwpostdec2 + fail +.Lwpostdec2: + mov #0xa5a5a5a5, @word_dest + +rotxr_w_preinc_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest-2, er0 + rotxr.w #2, @+er0 ; shift right arithmetic by two, preinc +;;; .word 0x0155 +;;; .word 0x6d08 +;;; .word 0x1350 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 word_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 1010 1001 0110 1001 + cmp.w #0xa969, @word_dest + beq .Lwpreinc2 + fail +.Lwpreinc2: + mov #0xa5a5a5a5, @word_dest + +rotxr_w_predec_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest+2, er0 + rotxr.w #2, @-er0 ; shift right arithmetic by two, predec +;;; .word 0x0157 +;;; .word 0x6d08 +;;; .word 0x1350 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 word_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 1010 1001 0110 1001 + cmp.w #0xa969, @word_dest + beq .Lwpredec2 + fail +.Lwpredec2: + mov #0xa5a5a5a5, @word_dest + +rotxr_w_disp2_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest-4, er0 + rotxr.w #2, @(4:2, er0) ; shift right arithmetic by two, disp2 +;;; .word 0x0156 +;;; .word 0xa908 +;;; .word 0x1350 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 word_dest-4 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 1010 1001 0110 1001 + cmp.w #0xa969, @word_dest + beq .Lwdisp22 + fail +.Lwdisp22: + mov #0xa5a5a5a5, @word_dest + +rotxr_w_disp16_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest-44, er0 + rotxr.w #2, @(44:16, er0) ; shift right arithmetic by two, disp16 +;;; .word 0x0154 +;;; .word 0x6f08 +;;; .word 44 +;;; .word 0x1350 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 word_dest-44 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 1010 1001 0110 1001 + cmp.w #0xa969, @word_dest + beq .Lwdisp162 + fail +.Lwdisp162: + mov #0xa5a5a5a5, @word_dest + +rotxr_w_disp32_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest-666, er0 + rotxr.w #2, @(666:32, er0) ; shift right arithmetic by two, disp32 +;;; .word 0x7884 +;;; .word 0x6b28 +;;; .long 666 +;;; .word 0x1350 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 word_dest-666 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 1010 1001 0110 1001 + cmp.w #0xa969, @word_dest + beq .Lwdisp322 + fail +.Lwdisp322: + mov #0xa5a5a5a5, @word_dest + +rotxr_w_abs16_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotxr.w #2, @word_dest:16 ; shift right arithmetic by two, abs16 +;;; .word 0x6b18 +;;; .word word_dest +;;; .word 0x1350 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 1010 1001 0110 1001 + cmp.w #0xa969, @word_dest + beq .Lwabs162 + fail +.Lwabs162: + mov #0xa5a5a5a5, @word_dest + +rotxr_w_abs32_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotxr.w #2, @word_dest:32 ; shift right arithmetic by two, abs32 +;;; .word 0x6b38 +;;; .long word_dest +;;; .word 0x1350 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 1010 1001 0110 1001 + cmp.w #0xa969, @word_dest + beq .Lwabs322 + fail +.Lwabs322: + mov #0xa5a5a5a5, @word_dest +.endif + +rotxr_l_reg32_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotxr.l er0 ; shift right arithmetic by one, register +;;; .word 0x1330 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ; -> 0101 0010 1101 0010 1101 0010 1101 0010 + test_h_gr32 0x52d2d2d2 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +rotxr_l_ind_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest, er0 + rotxr.l @er0 ; shift right arithmetic by one, indirect +;;; .word 0x0104 +;;; .word 0xa908 +;;; .word 0x1330 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 + cmp.l #0x52d2d2d2, @long_dest + beq .Llind1 + fail +.Llind1: + mov #0xa5a5a5a5, @long_dest + +rotxr_l_postinc_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest, er0 + rotxr.l @er0+ ; shift right arithmetic by one, postinc +;;; .word 0x0104 +;;; .word 0x6d08 +;;; .word 0x1330 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest+4 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 + cmp.l #0x52d2d2d2, @long_dest + beq .Llpostinc1 + fail +.Llpostinc1: + mov #0xa5a5a5a5, @long_dest + +rotxr_l_postdec_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest, er0 + rotxr.l @er0- ; shift right arithmetic by one, postdec +;;; .word 0x0106 +;;; .word 0x6d08 +;;; .word 0x1330 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest-4 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 + cmp.l #0x52d2d2d2, @long_dest + beq .Llpostdec1 + fail +.Llpostdec1: + mov #0xa5a5a5a5, @long_dest + +rotxr_l_preinc_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest-4, er0 + rotxr.l @+er0 ; shift right arithmetic by one, preinc +;;; .word 0x0105 +;;; .word 0x6d08 +;;; .word 0x1330 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 + cmp.l #0x52d2d2d2, @long_dest + beq .Llpreinc1 + fail +.Llpreinc1: + mov #0xa5a5a5a5, @long_dest + +rotxr_l_predec_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest+4, er0 + rotxr.l @-er0 ; shift right arithmetic by one, predec +;;; .word 0x0107 +;;; .word 0x6d08 +;;; .word 0x1330 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 + cmp.l #0x52d2d2d2, @long_dest + beq .Llpredec1 + fail +.Llpredec1: + mov #0xa5a5a5a5, @long_dest + +rotxr_l_disp2_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest-8, er0 + rotxr.l @(8:2, er0) ; shift right arithmetic by one, disp2 +;;; .word 0x0106 +;;; .word 0xa908 +;;; .word 0x1330 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest-8 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 + cmp.l #0x52d2d2d2, @long_dest + beq .Lldisp21 + fail +.Lldisp21: + mov #0xa5a5a5a5, @long_dest + +rotxr_l_disp16_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest-44, er0 + rotxr.l @(44:16, er0) ; shift right arithmetic by one, disp16 +;;; .word 0x0104 +;;; .word 0x6f08 +;;; .word 44 +;;; .word 0x1330 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest-44 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 + cmp.l #0x52d2d2d2, @long_dest + beq .Lldisp161 + fail +.Lldisp161: + mov #0xa5a5a5a5, @long_dest + +rotxr_l_disp32_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest-666, er0 + rotxr.l @(666:32, er0) ; shift right arithmetic by one, disp32 +;;; .word 0x7884 +;;; .word 0x6b28 +;;; .long 666 +;;; .word 0x1330 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest-666 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 + cmp.l #0x52d2d2d2, @long_dest + beq .Lldisp321 + fail +.Lldisp321: + mov #0xa5a5a5a5, @long_dest + +rotxr_l_abs16_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotxr.l @long_dest:16 ; shift right arithmetic by one, abs16 +;;; .word 0x0104 +;;; .word 0x6b08 +;;; .word long_dest +;;; .word 0x1330 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 + cmp.l #0x52d2d2d2, @long_dest + beq .Llabs161 + fail +.Llabs161: + mov #0xa5a5a5a5, @long_dest + +rotxr_l_abs32_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotxr.l @long_dest:32 ; shift right arithmetic by one, abs32 +;;; .word 0x0104 +;;; .word 0x6b28 +;;; .long long_dest +;;; .word 0x1330 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 + cmp.l #0x52d2d2d2, @long_dest + beq .Llabs321 + fail +.Llabs321: + mov #0xa5a5a5a5, @long_dest +.endif + +rotxr_l_reg32_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotxr.l #2, er0 ; shift right arithmetic by two, register +;;; .word 0x1370 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ; -> 1010 1001 0110 1001 0110 1001 0110 1001 + test_h_gr32 0xa9696969 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) + +rotxr_l_ind_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest, er0 + rotxr.l #2, @er0 ; shift right arithmetic by two, indirect +;;; .word 0x0104 +;;; .word 0xa908 +;;; .word 0x1370 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 long_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 1010 1001 0110 1001 0110 1001 0110 1001 + cmp.l #0xa9696969, @long_dest + beq .Llind2 + fail +.Llind2: + mov #0xa5a5a5a5, @long_dest + +rotxr_l_postinc_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest, er0 + rotxr.l #2, @er0+ ; shift right arithmetic by two, postinc +;;; .word 0x0104 +;;; .word 0x6d08 +;;; .word 0x1370 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 long_dest+4 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 1010 1001 0110 1001 0110 1001 0110 1001 + cmp.l #0xa9696969, @long_dest + beq .Llpostinc2 + fail +.Llpostinc2: + mov #0xa5a5a5a5, @long_dest + +rotxr_l_postdec_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest, er0 + rotxr.l #2, @er0- ; shift right arithmetic by two, postdec +;;; .word 0x0106 +;;; .word 0x6d08 +;;; .word 0x1370 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 long_dest-4 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 1010 1001 0110 1001 0110 1001 0110 1001 + cmp.l #0xa9696969, @long_dest + beq .Llpostdec2 + fail +.Llpostdec2: + mov #0xa5a5a5a5, @long_dest + +rotxr_l_preinc_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest-4, er0 + rotxr.l #2, @+er0 ; shift right arithmetic by two, preinc +;;; .word 0x0105 +;;; .word 0x6d08 +;;; .word 0x1370 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 long_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 1010 1001 0110 1001 0110 1001 0110 1001 + cmp.l #0xa9696969, @long_dest + beq .Llpreinc2 + fail +.Llpreinc2: + mov #0xa5a5a5a5, @long_dest + +rotxr_l_predec_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest+4, er0 + rotxr.l #2, @-er0 ; shift right arithmetic by two, predec +;;; .word 0x0107 +;;; .word 0x6d08 +;;; .word 0x1370 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 long_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 1010 1001 0110 1001 0110 1001 0110 1001 + cmp.l #0xa9696969, @long_dest + beq .Llpredec2 + fail +.Llpredec2: + mov #0xa5a5a5a5, @long_dest + +rotxr_l_disp2_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest-8, er0 + rotxr.l #2, @(8:2, er0) ; shift right arithmetic by two, disp2 +;;; .word 0x0106 +;;; .word 0xa908 +;;; .word 0x1370 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 long_dest-8 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 1010 1001 0110 1001 0110 1001 0110 1001 + cmp.l #0xa9696969, @long_dest + beq .Lldisp22 + fail +.Lldisp22: + mov #0xa5a5a5a5, @long_dest + +rotxr_l_disp16_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest-44, er0 + rotxr.l #2, @(44:16, er0) ; shift right arithmetic by two, disp16 +;;; .word 0x0104 +;;; .word 0x6f08 +;;; .word 44 +;;; .word 0x1370 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 long_dest-44 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 1010 1001 0110 1001 0110 1001 0110 1001 + cmp.l #0xa9696969, @long_dest + beq .Lldisp162 + fail +.Lldisp162: + mov #0xa5a5a5a5, @long_dest + +rotxr_l_disp32_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest-666, er0 + rotxr.l #2, @(666:32, er0) ; shift right arithmetic by two, disp32 +;;; .word 0x7884 +;;; .word 0x6b28 +;;; .long 666 +;;; .word 0x1370 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 long_dest-666 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 1010 1001 0110 1001 0110 1001 0110 1001 + cmp.l #0xa9696969, @long_dest + beq .Lldisp322 + fail +.Lldisp322: + mov #0xa5a5a5a5, @long_dest + +rotxr_l_abs16_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotxr.l #2, @long_dest:16 ; shift right arithmetic by two, abs16 +;;; .word 0x0104 +;;; .word 0x6b08 +;;; .word long_dest +;;; .word 0x1370 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 1010 1001 0110 1001 0110 1001 0110 1001 + cmp.l #0xa9696969, @long_dest + beq .Llabs162 + fail +.Llabs162: + mov #0xa5a5a5a5, @long_dest + +rotxr_l_abs32_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + rotxr.l #2, @long_dest:32 ; shift right arithmetic by two, abs32 +;;; .word 0x0104 +;;; .word 0x6b28 +;;; .long long_dest +;;; .word 0x1370 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 1010 1001 0110 1001 0110 1001 0110 1001 + cmp.l #0xa9696969, @long_dest + beq .Llabs322 + fail +.Llabs322: + mov #0xa5a5a5a5, @long_dest + +.endif +.endif + pass + + exit 0 + diff --git a/sim/testsuite/sim/h8300/shal.s b/sim/testsuite/sim/h8300/shal.s new file mode 100644 index 0000000..ccea907 --- /dev/null +++ b/sim/testsuite/sim/h8300/shal.s @@ -0,0 +1,167 @@ +# Hitachi H8 testcase 'shal' +# mach(): all +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + start + + .data +byte_dest: .byte 0xa5 + .align 2 +word_dest: .word 0xa5a5 + .align 4 +long_dest: .long 0xa5a5a5a5 + + .text + +shal_b_reg8_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shal.b r0l ; shift left arithmetic by one +;;; .word 0x1088 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear +; test_ovf_clear ; FIXME + test_neg_clear + test_h_gr16 0xa54a r0 ; 1010 0101 -> 0100 1010 +.if (sim_cpu) + test_h_gr32 0xa5a5a54a er0 +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +shal_b_reg8_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shal.b #2, r0l ; shift left arithmetic by two +;;; .word 0x10c8 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear +; test_ovf_clear ; FIXME + test_neg_set + + test_h_gr16 0xa594 r0 ; 1010 0101 -> 1001 0100 +.if (sim_cpu) + test_h_gr32 0xa5a5a594 er0 +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu) ; Not available in h8300 mode +shal_w_reg16_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shal.w r0 ; shift left arithmetic by one +;;; .word 0x1090 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear +; test_ovf_clear ; FIXME + test_neg_clear + test_h_gr16 0x4b4a r0 ; 1010 0101 1010 0101 -> 0100 1011 0100 1010 + test_h_gr32 0xa5a54b4a er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +shal_w_reg16_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shal.w #2, r0 ; shift left arithmetic by two +;;; .word 0x10d0 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear +; test_ovf_clear ; FIXME + test_neg_set + test_h_gr16 0x9694 r0 ; 1010 0101 1010 0101 -> 1001 0110 1001 0100 + test_h_gr32 0xa5a59694 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +shal_l_reg32_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shal.l er0 ; shift left arithmetic by one +;;; .word 10b0 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear +; test_ovf_clear ; FIXME + test_neg_clear + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ; -> 0100 1011 0100 1011 0100 1011 0100 1010 + test_h_gr32 0x4b4b4b4a er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +shal_l_reg32_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shal.l #2, er0 ; shift left arithmetic by two +;;; .word 0x10f0 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear +; test_ovf_clear ; FIXME + test_neg_set + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ; -> 1001 0110 1001 0110 1001 0110 1001 0100 + test_h_gr32 0x96969694 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.endif + + pass + + exit 0 + diff --git a/sim/testsuite/sim/h8300/shar.s b/sim/testsuite/sim/h8300/shar.s new file mode 100644 index 0000000..9c9166b --- /dev/null +++ b/sim/testsuite/sim/h8300/shar.s @@ -0,0 +1,2000 @@ +# Hitachi H8 testcase 'shar' +# mach(): all +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + start + + .data +byte_dest: .byte 0xa5 + .align 2 +word_dest: .word 0xa5a5 + .align 4 +long_dest: .long 0xa5a5a5a5 + + .text + +shar_b_reg8_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shar.b r0l ; shift right arithmetic by one +;;; .word 0x1188 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr16 0xa5d2 r0 ; 1010 0101 -> 1101 0010 +.if (sim_cpu) + test_h_gr32 0xa5a5a5d2 er0 +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +shar_b_ind_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest, er0 + shar.b @er0 ; shift right arithmetic by one, indirect +;;; .word 0x7d00 +;;; .word 0x1180 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 byte_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 1101 0010 + cmp.b #0xd2, @byte_dest + beq .Lbind1 + fail +.Lbind1: + mov.b #0xa5, @byte_dest + +shar_b_postinc_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest, er0 + shar.b @er0+ ; shift right arithmetic by one, postinc +;;; .word 0x0174 +;;; .word 0x6c08 +;;; .word 0x1180 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 byte_dest+1 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 1101 0010 + cmp.b #0xd2, @byte_dest + beq .Lbpostinc1 + fail +.Lbpostinc1: + mov.b #0xa5, @byte_dest + +shar_b_postdec_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest, er0 + shar.b @er0- ; shift right arithmetic by one, postdec +;;; .word 0x0176 +;;; .word 0x6c08 +;;; .word 0x1180 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 byte_dest-1 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 1101 0010 + cmp.b #0xd2, @byte_dest + beq .Lbpostdec1 + fail +.Lbpostdec1: + mov.b #0xa5, @byte_dest + +shar_b_preinc_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest-1, er0 + shar.b @+er0 ; shift right arithmetic by one, preinc +;;; .word 0x0175 +;;; .word 0x6c08 +;;; .word 0x1180 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 byte_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 1101 0010 + cmp.b #0xd2, @byte_dest + beq .Lbpreinc1 + fail +.Lbpreinc1: + mov.b #0xa5, @byte_dest + +shar_b_predec_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest+1, er0 + shar.b @-er0 ; shift right arithmetic by one, predec +;;; .word 0x0177 +;;; .word 0x6c08 +;;; .word 0x1180 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 byte_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 1101 0010 + cmp.b #0xd2, @byte_dest + beq .Lbpredec1 + fail +.Lbpredec1: + mov.b #0xa5, @byte_dest + +shar_b_disp2_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest-2, er0 + shar.b @(2:2, er0) ; shift right arithmetic by one, disp2 +;;; .word 0x0176 +;;; .word 0x6808 +;;; .word 0x1180 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 byte_dest-2 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 1101 0010 + cmp.b #0xd2, @byte_dest + beq .Lbdisp21 + fail +.Lbdisp21: + mov.b #0xa5, @byte_dest + +shar_b_disp16_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest-44, er0 + shar.b @(44:16, er0) ; shift right arithmetic by one, disp16 +;;; .word 0x0174 +;;; .word 0x6e08 +;;; .word 44 +;;; .word 0x1180 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 byte_dest-44 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 1101 0010 + cmp.b #0xd2, @byte_dest + beq .Lbdisp161 + fail +.Lbdisp161: + mov.b #0xa5, @byte_dest + +shar_b_disp32_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest-666, er0 + shar.b @(666:32, er0) ; shift right arithmetic by one, disp32 +;;; .word 0x7884 +;;; .word 0x6a28 +;;; .long 666 +;;; .word 0x1180 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 byte_dest-666 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 1101 0010 + cmp.b #0xd2, @byte_dest + beq .Lbdisp321 + fail +.Lbdisp321: + mov.b #0xa5, @byte_dest + +shar_b_abs16_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shar.b @byte_dest:16 ; shift right arithmetic by one, abs16 +;;; .word 0x6a18 +;;; .word byte_dest +;;; .word 0x1180 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 1101 0010 + cmp.b #0xd2, @byte_dest + beq .Lbabs161 + fail +.Lbabs161: + mov.b #0xa5, @byte_dest + +shar_b_abs32_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shar.b @byte_dest:32 ; shift right arithmetic by one, abs32 +;;; .word 0x6a38 +;;; .long byte_dest +;;; .word 0x1180 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 1101 0010 + cmp.b #0xd2, @byte_dest + beq .Lbabs321 + fail +.Lbabs321: + mov.b #0xa5, @byte_dest +.endif + +shar_b_reg8_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shar.b #2, r0l ; shift right arithmetic by two +;;; .word 0x11c8 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + test_h_gr16 0xa5e9 r0 ; 1010 0101 -> 1110 1001 +.if (sim_cpu) + test_h_gr32 0xa5a5a5e9 er0 +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +shar_b_ind_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest, er0 + shar.b #2, @er0 ; shift right arithmetic by two, indirect +;;; .word 0x7d00 +;;; .word 0x11c0 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 byte_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 1110 1001 + cmp.b #0xe9, @byte_dest + beq .Lbind2 + fail +.Lbind2: + mov.b #0xa5, @byte_dest + +shar_b_postinc_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest, er0 + shar.b #2, @er0+ ; shift right arithmetic by two, postinc +;;; .word 0x0174 +;;; .word 0x6c08 +;;; .word 0x11c0 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 byte_dest+1 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 1110 1001 + cmp.b #0xe9, @byte_dest + beq .Lbpostinc2 + fail +.Lbpostinc2: + mov.b #0xa5, @byte_dest + +shar_b_postdec_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest, er0 + shar.b #2, @er0- ; shift right arithmetic by two, postdec +;;; .word 0x0176 +;;; .word 0x6c08 +;;; .word 0x11c0 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 byte_dest-1 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 1110 1001 + cmp.b #0xe9, @byte_dest + beq .Lbpostdec2 + fail +.Lbpostdec2: + mov.b #0xa5, @byte_dest + +shar_b_preinc_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest-1, er0 + shar.b #2, @+er0 ; shift right arithmetic by two, preinc +;;; .word 0x0175 +;;; .word 0x6c08 +;;; .word 0x11c0 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 byte_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 1110 1001 + cmp.b #0xe9, @byte_dest + beq .Lbpreinc2 + fail +.Lbpreinc2: + mov.b #0xa5, @byte_dest + +shar_b_predec_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest+1, er0 + shar.b #2, @-er0 ; shift right arithmetic by two, predec +;;; .word 0x0177 +;;; .word 0x6c08 +;;; .word 0x11c0 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 byte_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 1110 1001 + cmp.b #0xe9, @byte_dest + beq .Lbpredec2 + fail +.Lbpredec2: + mov.b #0xa5, @byte_dest + +shar_b_disp2_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest-2, er0 + shar.b #2, @(2:2, er0) ; shift right arithmetic by two, disp2 +;;; .word 0x0176 +;;; .word 0x6808 +;;; .word 0x11c0 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 byte_dest-2 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 1110 1001 + cmp.b #0xe9, @byte_dest + beq .Lbdisp22 + fail +.Lbdisp22: + mov.b #0xa5, @byte_dest + +shar_b_disp16_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest-44, er0 + shar.b #2, @(44:16, er0) ; shift right arithmetic by two, disp16 +;;; .word 0x0174 +;;; .word 0x6e08 +;;; .word 44 +;;; .word 0x11c0 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 byte_dest-44 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 1110 1001 + cmp.b #0xe9, @byte_dest + beq .Lbdisp162 + fail +.Lbdisp162: + mov.b #0xa5, @byte_dest + +shar_b_disp32_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest-666, er0 + shar.b #2, @(666:32, er0) ; shift right arithmetic by two, disp32 +;;; .word 0x7884 +;;; .word 0x6a28 +;;; .long 666 +;;; .word 0x11c0 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 byte_dest-666 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 1110 1001 + cmp.b #0xe9, @byte_dest + beq .Lbdisp322 + fail +.Lbdisp322: + mov.b #0xa5, @byte_dest + +shar_b_abs16_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shar.b #2, @byte_dest:16 ; shift right arithmetic by two, abs16 +;;; .word 0x6a18 +;;; .word byte_dest +;;; .word 0x11c0 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 1110 1001 + cmp.b #0xe9, @byte_dest + beq .Lbabs162 + fail +.Lbabs162: + mov.b #0xa5, @byte_dest + +shar_b_abs32_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shar.b #2, @byte_dest:32 ; shift right arithmetic by two, abs32 +;;; .word 0x6a38 +;;; .long byte_dest +;;; .word 0x11c0 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 1110 1001 + cmp.b #0xe9, @byte_dest + beq .Lbabs322 + fail +.Lbabs322: + mov.b #0xa5, @byte_dest +.endif + +.if (sim_cpu) ; Not available in h8300 mode +shar_w_reg16_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shar.w r0 ; shift right arithmetic by one +;;; .word 0x1190 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + test_h_gr16 0xd2d2 r0 ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 + test_h_gr32 0xa5a5d2d2 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +shar_w_ind_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest, er0 + shar.w @er0 ; shift right arithmetic by one, indirect +;;; .word 0x7d80 +;;; .word 0x1190 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 word_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 + cmp.w #0xd2d2, @word_dest + beq .Lwind1 + fail +.Lwind1: + mov.w #0xa5a5, @word_dest + +shar_w_postinc_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest, er0 + shar.w @er0+ ; shift right arithmetic by one, postinc +;;; .word 0x0154 +;;; .word 0x6d08 +;;; .word 0x1190 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 word_dest+2 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 + cmp.w #0xd2d2, @word_dest + beq .Lwpostinc1 + fail +.Lwpostinc1: + mov.w #0xa5a5, @word_dest + +shar_w_postdec_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest, er0 + shar.w @er0- ; shift right arithmetic by one, postdec +;;; .word 0x0156 +;;; .word 0x6d08 +;;; .word 0x1190 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 word_dest-2 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 + cmp.w #0xd2d2, @word_dest + beq .Lwpostdec1 + fail +.Lwpostdec1: + mov.w #0xa5a5, @word_dest + +shar_w_preinc_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest-2, er0 + shar.w @+er0 ; shift right arithmetic by one, preinc +;;; .word 0x0155 +;;; .word 0x6d08 +;;; .word 0x1190 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 word_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 + cmp.w #0xd2d2, @word_dest + beq .Lwpreinc1 + fail +.Lwpreinc1: + mov.w #0xa5a5, @word_dest + +shar_w_predec_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest+2, er0 + shar.w @-er0 ; shift right arithmetic by one, predec +;;; .word 0x0157 +;;; .word 0x6d08 +;;; .word 0x1190 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 word_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 + cmp.w #0xd2d2, @word_dest + beq .Lwpredec1 + fail +.Lwpredec1: + mov.w #0xa5a5, @word_dest + +shar_w_disp2_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest-4, er0 + shar.w @(4:2, er0) ; shift right arithmetic by one, disp2 +;;; .word 0x0156 +;;; .word 0x6908 +;;; .word 0x1190 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 word_dest-4 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 + cmp.w #0xd2d2, @word_dest + beq .Lwdisp21 + fail +.Lwdisp21: + mov.w #0xa5a5, @word_dest + +shar_w_disp16_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest-44, er0 + shar.w @(44:16, er0) ; shift right arithmetic by one, disp16 +;;; .word 0x0154 +;;; .word 0x6f08 +;;; .word 44 +;;; .word 0x1190 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 word_dest-44 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 + cmp.w #0xd2d2, @word_dest + beq .Lwdisp161 + fail +.Lwdisp161: + mov.w #0xa5a5, @word_dest + +shar_w_disp32_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest-666, er0 + shar.w @(666:32, er0) ; shift right arithmetic by one, disp32 +;;; .word 0x7884 +;;; .word 0x6b28 +;;; .long 666 +;;; .word 0x1190 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 word_dest-666 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 + cmp.w #0xd2d2, @word_dest + beq .Lwdisp321 + fail +.Lwdisp321: + mov.w #0xa5a5, @word_dest + +shar_w_abs16_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shar.w @word_dest:16 ; shift right arithmetic by one, abs16 +;;; .word 0x6b18 +;;; .word word_dest +;;; .word 0x1190 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 + cmp.w #0xd2d2, @word_dest + beq .Lwabs161 + fail +.Lwabs161: + mov.w #0xa5a5, @word_dest + +shar_w_abs32_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shar.w @word_dest:32 ; shift right arithmetic by one, abs32 +;;; .word 0x6b38 +;;; .long word_dest +;;; .word 0x1190 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 1101 0010 1101 0010 + cmp.w #0xd2d2, @word_dest + beq .Lwabs321 + fail +.Lwabs321: + mov.w #0xa5a5, @word_dest +.endif + +shar_w_reg16_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shar.w #2, r0 ; shift right arithmetic by two +;;; .word 0x11d0 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr16 0xe969 r0 ; 1010 0101 1010 0101 -> 1110 1001 0110 1001 + test_h_gr32 0xa5a5e969 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +shar_w_ind_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest, er0 + shar.w #2, @er0 ; shift right arithmetic by two, indirect +;;; .word 0x7d80 +;;; .word 0x11d0 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 word_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 1110 1001 0110 1001 + cmp.w #0xe969, @word_dest + beq .Lwind2 + fail +.Lwind2: + mov.w #0xa5a5, @word_dest + +shar_w_postinc_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest, er0 + shar.w #2, @er0+ ; shift right arithmetic by two, postinc +;;; .word 0x0154 +;;; .word 0x6d08 +;;; .word 0x11d0 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 word_dest+2 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 1110 1001 0110 1001 + cmp.w #0xe969, @word_dest + beq .Lwpostinc2 + fail +.Lwpostinc2: + mov.w #0xa5a5, @word_dest + +shar_w_postdec_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest, er0 + shar.w #2, @er0- ; shift right arithmetic by two, postdec +;;; .word 0x0156 +;;; .word 0x6d08 +;;; .word 0x11d0 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 word_dest-2 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 1110 1001 0110 1001 + cmp.w #0xe969, @word_dest + beq .Lwpostdec2 + fail +.Lwpostdec2: + mov.w #0xa5a5, @word_dest + +shar_w_preinc_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest-2, er0 + shar.w #2, @+er0 ; shift right arithmetic by two, preinc +;;; .word 0x0155 +;;; .word 0x6d08 +;;; .word 0x11d0 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 word_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 1110 1001 0110 1001 + cmp.w #0xe969, @word_dest + beq .Lwpreinc2 + fail +.Lwpreinc2: + mov.w #0xa5a5, @word_dest + +shar_w_predec_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest+2, er0 + shar.w #2, @-er0 ; shift right arithmetic by two, predec +;;; .word 0x0157 +;;; .word 0x6d08 +;;; .word 0x11d0 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 word_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 1110 1001 0110 1001 + cmp.w #0xe969, @word_dest + beq .Lwpredec2 + fail +.Lwpredec2: + mov.w #0xa5a5, @word_dest + +shar_w_disp2_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest-4, er0 + shar.w #2, @(4:2, er0) ; shift right arithmetic by two, disp2 +;;; .word 0x0156 +;;; .word 0x6908 +;;; .word 0x11d0 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 word_dest-4 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 1110 1001 0110 1001 + cmp.w #0xe969, @word_dest + beq .Lwdisp22 + fail +.Lwdisp22: + mov.w #0xa5a5, @word_dest + +shar_w_disp16_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest-44, er0 + shar.w #2, @(44:16, er0) ; shift right arithmetic by two, disp16 +;;; .word 0x0154 +;;; .word 0x6f08 +;;; .word 44 +;;; .word 0x11d0 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 word_dest-44 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 1110 1001 0110 1001 + cmp.w #0xe969, @word_dest + beq .Lwdisp162 + fail +.Lwdisp162: + mov.w #0xa5a5, @word_dest + +shar_w_disp32_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest-666, er0 + shar.w #2, @(666:32, er0) ; shift right arithmetic by two, disp32 +;;; .word 0x7884 +;;; .word 0x6b28 +;;; .long 666 +;;; .word 0x11d0 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 word_dest-666 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 1110 1001 0110 1001 + cmp.w #0xe969, @word_dest + beq .Lwdisp322 + fail +.Lwdisp322: + mov.w #0xa5a5, @word_dest + +shar_w_abs16_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shar.w #2, @word_dest:16 ; shift right arithmetic by two, abs16 +;;; .word 0x6b18 +;;; .word word_dest +;;; .word 0x11d0 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 1110 1001 0110 1001 + cmp.w #0xe969, @word_dest + beq .Lwabs162 + fail +.Lwabs162: + mov.w #0xa5a5, @word_dest + +shar_w_abs32_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shar.w #2, @word_dest:32 ; shift right arithmetic by two, abs32 +;;; .word 0x6b38 +;;; .long word_dest +;;; .word 0x11d0 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 1110 1001 0110 1001 + cmp.w #0xe969, @word_dest + beq .Lwabs322 + fail +.Lwabs322: + mov.w #0xa5a5, @word_dest +.endif + +shar_l_reg32_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shar.l er0 ; shift right arithmetic by one, register +;;; .word 0x11b0 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ; -> 1101 0010 1101 0010 1101 0010 1101 0010 + test_h_gr32 0xd2d2d2d2 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +shar_l_ind_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest, er0 + shar.l @er0 ; shift right arithmetic by one, indirect +;;; .word 0x0104 +;;; .word 0x6908 +;;; .word 0x11b0 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 long_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 1101 0010 1101 0010 1101 0010 1101 0010 + cmp.l #0xd2d2d2d2, @long_dest + beq .Llind1 + fail +.Llind1: + mov #0xa5a5a5a5, @long_dest + +shar_l_postinc_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest, er0 + shar.l @er0+ ; shift right arithmetic by one, postinc +;;; .word 0x0104 +;;; .word 0x6d08 +;;; .word 0x11b0 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 long_dest+4 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 1101 0010 1101 0010 1101 0010 1101 0010 + cmp.l #0xd2d2d2d2, @long_dest + beq .Llpostinc1 + fail +.Llpostinc1: + mov #0xa5a5a5a5, @long_dest + +shar_l_postdec_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest, er0 + shar.l @er0- ; shift right arithmetic by one, postdec +;;; .word 0x0106 +;;; .word 0x6d08 +;;; .word 0x11b0 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 long_dest-4 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 1101 0010 1101 0010 1101 0010 1101 0010 + cmp.l #0xd2d2d2d2, @long_dest + beq .Llpostdec1 + fail +.Llpostdec1: + mov #0xa5a5a5a5, @long_dest + +shar_l_preinc_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest-4, er0 + shar.l @+er0 ; shift right arithmetic by one, preinc +;;; .word 0x0105 +;;; .word 0x6d08 +;;; .word 0x11b0 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 long_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 1101 0010 1101 0010 1101 0010 1101 0010 + cmp.l #0xd2d2d2d2, @long_dest + beq .Llpreinc1 + fail +.Llpreinc1: + mov #0xa5a5a5a5, @long_dest + +shar_l_predec_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest+4, er0 + shar.l @-er0 ; shift right arithmetic by one, predec +;;; .word 0x0107 +;;; .word 0x6d08 +;;; .word 0x11b0 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 long_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 1101 0010 1101 0010 1101 0010 1101 0010 + cmp.l #0xd2d2d2d2, @long_dest + beq .Llpredec1 + fail +.Llpredec1: + mov #0xa5a5a5a5, @long_dest + +shar_l_disp2_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest-8, er0 + shar.l @(8:2, er0) ; shift right arithmetic by one, disp2 +;;; .word 0x0106 +;;; .word 0x6908 +;;; .word 0x11b0 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 long_dest-8 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 1101 0010 1101 0010 1101 0010 1101 0010 + cmp.l #0xd2d2d2d2, @long_dest + beq .Lldisp21 + fail +.Lldisp21: + mov #0xa5a5a5a5, @long_dest + +shar_l_disp16_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest-44, er0 + shar.l @(44:16, er0) ; shift right arithmetic by one, disp16 +;;; .word 0x0104 +;;; .word 0x6f08 +;;; .word 44 +;;; .word 0x11b0 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 long_dest-44 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 1101 0010 1101 0010 1101 0010 1101 0010 + cmp.l #0xd2d2d2d2, @long_dest + beq .Lldisp161 + fail +.Lldisp161: + mov #0xa5a5a5a5, @long_dest + +shar_l_disp32_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest-666, er0 + shar.l @(666:32, er0) ; shift right arithmetic by one, disp32 +;;; .word 0x7884 +;;; .word 0x6b28 +;;; .long 666 +;;; .word 0x11b0 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 long_dest-666 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 1101 0010 1101 0010 1101 0010 1101 0010 + cmp.l #0xd2d2d2d2, @long_dest + beq .Lldisp321 + fail +.Lldisp321: + mov #0xa5a5a5a5, @long_dest + +shar_l_abs16_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shar.l @long_dest:16 ; shift right arithmetic by one, abs16 +;;; .word 0x0104 +;;; .word 0x6b08 +;;; .word long_dest +;;; .word 0x11b0 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 1101 0010 1101 0010 1101 0010 1101 0010 + cmp.l #0xd2d2d2d2, @long_dest + beq .Llabs161 + fail +.Llabs161: + mov #0xa5a5a5a5, @long_dest + +shar_l_abs32_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shar.l @long_dest:32 ; shift right arithmetic by one, abs32 +;;; .word 0x0104 +;;; .word 0x6b28 +;;; .long long_dest +;;; .word 0x11b0 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 1101 0010 1101 0010 1101 0010 1101 0010 + cmp.l #0xd2d2d2d2, @long_dest + beq .Llabs321 + fail +.Llabs321: + mov #0xa5a5a5a5, @long_dest +.endif + +shar_l_reg32_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shar.l #2, er0 ; shift right arithmetic by two, register +;;; .word 0x11f0 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ; -> 1110 1001 0110 1001 0110 1001 0110 1001 + test_h_gr32 0xe9696969 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) + +shar_l_ind_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest, er0 + shar.l #2, @er0 ; shift right arithmetic by two, indirect +;;; .word 0x0104 +;;; .word 0x6908 +;;; .word 0x11f0 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 long_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 1110 1001 0110 1001 0110 1001 0110 1001 + cmp.l #0xe9696969, @long_dest + beq .Llind2 + fail +.Llind2: + mov #0xa5a5a5a5, @long_dest + +shar_l_postinc_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest, er0 + shar.l #2, @er0+ ; shift right arithmetic by two, postinc +;;; .word 0x0104 +;;; .word 0x6d08 +;;; .word 0x11f0 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 long_dest+4 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 1110 1001 0110 1001 0110 1001 0110 1001 + cmp.l #0xe9696969, @long_dest + beq .Llpostinc2 + fail +.Llpostinc2: + mov #0xa5a5a5a5, @long_dest + +shar_l_postdec_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest, er0 + shar.l #2, @er0- ; shift right arithmetic by two, postdec +;;; .word 0x0106 +;;; .word 0x6d08 +;;; .word 0x11f0 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 long_dest-4 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 1110 1001 0110 1001 0110 1001 0110 1001 + cmp.l #0xe9696969, @long_dest + beq .Llpostdec2 + fail +.Llpostdec2: + mov #0xa5a5a5a5, @long_dest + +shar_l_preinc_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest-4, er0 + shar.l #2, @+er0 ; shift right arithmetic by two, preinc +;;; .word 0x0105 +;;; .word 0x6d08 +;;; .word 0x11f0 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 long_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 1110 1001 0110 1001 0110 1001 0110 1001 + cmp.l #0xe9696969, @long_dest + beq .Llpreinc2 + fail +.Llpreinc2: + mov #0xa5a5a5a5, @long_dest + +shar_l_predec_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest+4, er0 + shar.l #2, @-er0 ; shift right arithmetic by two, predec +;;; .word 0x0107 +;;; .word 0x6d08 +;;; .word 0x11f0 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 long_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 1110 1001 0110 1001 0110 1001 0110 1001 + cmp.l #0xe9696969, @long_dest + beq .Llpredec2 + fail +.Llpredec2: + mov #0xa5a5a5a5, @long_dest + +shar_l_disp2_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest-8, er0 + shar.l #2, @(8:2, er0) ; shift right arithmetic by two, disp2 +;;; .word 0x0106 +;;; .word 0x6908 +;;; .word 0x11f0 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 long_dest-8 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 1110 1001 0110 1001 0110 1001 0110 1001 + cmp.l #0xe9696969, @long_dest + beq .Lldisp22 + fail +.Lldisp22: + mov #0xa5a5a5a5, @long_dest + +shar_l_disp16_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest-44, er0 + shar.l #2, @(44:16, er0) ; shift right arithmetic by two, disp16 +;;; .word 0x0104 +;;; .word 0x6f08 +;;; .word 44 +;;; .word 0x11f0 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 long_dest-44 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 1110 1001 0110 1001 0110 1001 0110 1001 + cmp.l #0xe9696969, @long_dest + beq .Lldisp162 + fail +.Lldisp162: + mov #0xa5a5a5a5, @long_dest + +shar_l_disp32_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest-666, er0 + shar.l #2, @(666:32, er0) ; shift right arithmetic by two, disp32 +;;; .word 0x7884 +;;; .word 0x6b28 +;;; .long 666 +;;; .word 0x11f0 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr32 long_dest-666 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 1110 1001 0110 1001 0110 1001 0110 1001 + cmp.l #0xe9696969, @long_dest + beq .Lldisp322 + fail +.Lldisp322: + mov #0xa5a5a5a5, @long_dest + +shar_l_abs16_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shar.l #2, @long_dest:16 ; shift right arithmetic by two, abs16 +;;; .word 0x0104 +;;; .word 0x6b08 +;;; .word long_dest +;;; .word 0x11f0 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 1110 1001 0110 1001 0110 1001 0110 1001 + cmp.l #0xe9696969, @long_dest + beq .Llabs162 + fail +.Llabs162: + mov #0xa5a5a5a5, @long_dest + +shar_l_abs32_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shar.l #2, @long_dest:32 ; shift right arithmetic by two, abs32 +;;; .word 0x0104 +;;; .word 0x6b28 +;;; .long long_dest +;;; .word 0x11f0 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 1110 1001 0110 1001 0110 1001 0110 1001 + cmp.l #0xe9696969, @long_dest + beq .Llabs322 + fail +.Llabs322: + mov #0xa5a5a5a5, @long_dest + +.endif +.endif + pass + + exit 0 + diff --git a/sim/testsuite/sim/h8300/shll.s b/sim/testsuite/sim/h8300/shll.s new file mode 100644 index 0000000..7fbf14d --- /dev/null +++ b/sim/testsuite/sim/h8300/shll.s @@ -0,0 +1,375 @@ +# Hitachi H8 testcase 'shll' +# mach(): all +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + start + + .data +byte_dest: .byte 0xa5 + .align 2 +word_dest: .word 0xa5a5 + .align 4 +long_dest: .long 0xa5a5a5a5 + + .text + +shll_b_reg8_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shll.b r0l ; shift left logical by one +;;; .word 0x1008 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + test_h_gr16 0xa54a r0 ; 1010 0101 -> 0100 1010 +.if (sim_cpu) + test_h_gr32 0xa5a5a54a er0 +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +shll_b_reg8_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shll.b #2, r0l ; shift left logical by two +;;; .word 0x1048 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + + test_h_gr16 0xa594 r0 ; 1010 0101 -> 1001 0100 +.if (sim_cpu) + test_h_gr32 0xa5a5a594 er0 +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +shll_b_reg8_4: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shll.b #4, r0l ; shift left logical by four +;;; .word 0x10a8 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + test_h_gr16 0xa550 r0 ; 1010 0101 -> 0101 0000 + test_h_gr32 0xa5a5a550 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +shll_b_reg8_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #5, r0h + shll.b r0h, r0l ; shift left logical by register value + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + test_h_gr16 0x05a0 r0 ; 1010 0101 -> 1010 0000 + test_h_gr32 0xa5a505a0 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif + +.if (sim_cpu) ; Not available in h8300 mode +shll_w_reg16_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shll.w r0 ; shift left logical by one +;;; .word 0x1010 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + test_h_gr16 0x4b4a r0 ; 1010 0101 1010 0101 -> 0100 1011 0100 1010 + test_h_gr32 0xa5a54b4a er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +shll_w_reg16_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shll.w #2, r0 ; shift left logical by two +;;; .word 0x1050 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + test_h_gr16 0x9694 r0 ; 1010 0101 1010 0101 -> 1001 0110 1001 0100 + test_h_gr32 0xa5a59694 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +shll_w_reg16_4: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shll.w #4, r0 ; shift left logical by four +;;; .word 0x1020 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + test_h_gr16 0x5a50 r0 ; 1010 0101 1010 0101 -> 0101 1010 0101 0000 + test_h_gr32 0xa5a55a50 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +shll_w_reg16_8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shll.w #8, r0 ; shift left logical by eight +;;; .word 0x1060 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + test_h_gr16 0xa500 r0 ; 1010 0101 1010 0101 -> 1010 0101 0000 0000 + test_h_gr32 0xa5a5a500 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +shll_w_reg16_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #5, r0h + shll.w r0h, r0 ; shift left logical by register value + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + test_h_gr16 0xb4a0 r0 ; 1010 0101 1010 0101 -> 1011 0100 1010 0000 + test_h_gr32 0xa5a5b4a0 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif + +shll_l_reg32_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shll.l er0 ; shift left logical by one +;;; .word 1030 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ; -> 0100 1011 0100 1011 0100 1011 0100 1010 + test_h_gr32 0x4b4b4b4a er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +shll_l_reg32_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shll.l #2, er0 ; shift left logical by two +;;; .word 0x1070 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ; -> 1001 0110 1001 0110 1001 0110 1001 0100 + test_h_gr32 0x96969694 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +shll_l_reg32_4: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shll.l #4, er0 ; shift left logical by four +;;; .word 0x1038 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ; -> 0101 1010 0101 1010 0101 1010 0101 0000 + test_h_gr32 0x5a5a5a50 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +shll_l_reg32_8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shll.l #8, er0 ; shift left logical by eight +;;; .word 0x1078 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + test_h_gr16 0xa500 r0 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ; -> 1010 0101 1010 0101 1010 0101 0000 0000 + test_h_gr32 0xa5a5a500 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +shll_l_reg32_16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shll.l #16, er0 ; shift left logical by sixteen +;;; .word 0x10f8 + + test_carry_set ; H=0 N=1 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_set + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 1010 0101 1010 0101 0000 0000 0000 0000 + test_h_gr32 0xa5a50000 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +shll_l_reg32_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #5, r1l + shll.l r1l, er0 ; shift left logical by register value + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_set + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ; -> 1011 0100 1011 0100 1011 0100 1010 0000 + test_h_gr32 0xb4b4b4a0 er0 + + test_h_gr32 0xa5a5a505 er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif +.endif + + pass + + exit 0 + diff --git a/sim/testsuite/sim/h8300/shlr.s b/sim/testsuite/sim/h8300/shlr.s new file mode 100644 index 0000000..4223313 --- /dev/null +++ b/sim/testsuite/sim/h8300/shlr.s @@ -0,0 +1,4085 @@ +# Hitachi H8 testcase 'shlr' +# mach(): all +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + start + + .data +byte_dest: .byte 0xa5 + .align 2 +word_dest: .word 0xa5a5 + .align 4 +long_dest: .long 0xa5a5a5a5 + + .text + +shlr_b_reg8_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shlr.b r0l ; shift right logical by one +;;; .word 0x1108 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr16 0xa552 r0 ; 1010 0101 -> 0101 0010 +.if (sim_cpu) + test_h_gr32 0xa5a5a552 er0 +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +shlr_b_ind_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest, er0 + shlr.b @er0 ; shift right logical by one, indirect +;;; .word 0x7d00 +;;; .word 0x1100 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 byte_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0101 0010 + cmp.b #0x52, @byte_dest + beq .Lbind1 + fail +.Lbind1: + mov.b #0xa5, @byte_dest + +shlr_b_postinc_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest, er0 + shlr.b @er0+ ; shift right logical by one, postinc +;;; .word 0x0174 +;;; .word 0x6c08 +;;; .word 0x1100 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 byte_dest+1 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0101 0010 + cmp.b #0x52, @byte_dest + beq .Lbpostinc1 + fail +.Lbpostinc1: + mov.b #0xa5, @byte_dest + +shlr_b_postdec_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest, er0 + shlr.b @er0- ; shift right logical by one, postdec +;;; .word 0x0176 +;;; .word 0x6c08 +;;; .word 0x1100 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 byte_dest-1 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0101 0010 + cmp.b #0x52, @byte_dest + beq .Lbpostdec1 + fail +.Lbpostdec1: + mov.b #0xa5, @byte_dest + +shlr_b_preinc_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest-1, er0 + shlr.b @+er0 ; shift right logical by one, preinc +;;; .word 0x0175 +;;; .word 0x6c08 +;;; .word 0x1100 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 byte_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0101 0010 + cmp.b #0x52, @byte_dest + beq .Lbpreinc1 + fail +.Lbpreinc1: + mov.b #0xa5, @byte_dest + +shlr_b_predec_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest+1, er0 + shlr.b @-er0 ; shift right logical by one, predec +;;; .word 0x0177 +;;; .word 0x6c08 +;;; .word 0x1100 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 byte_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0101 0010 + cmp.b #0x52, @byte_dest + beq .Lbpredec1 + fail +.Lbpredec1: + mov.b #0xa5, @byte_dest + +shlr_b_disp2_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest-2, er0 + shlr.b @(2:2, er0) ; shift right logical by one, disp2 +;;; .word 0x0176 +;;; .word 0x6808 +;;; .word 0x1100 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 byte_dest-2 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0101 0010 + cmp.b #0x52, @byte_dest + beq .Lbdisp21 + fail +.Lbdisp21: + mov.b #0xa5, @byte_dest + +shlr_b_disp16_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest-44, er0 + shlr.b @(44:16, er0) ; shift right logical by one, disp16 +;;; .word 0x0174 +;;; .word 0x6e08 +;;; .word 44 +;;; .word 0x1100 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 byte_dest-44 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0101 0010 + cmp.b #0x52, @byte_dest + beq .Lbdisp161 + fail +.Lbdisp161: + mov.b #0xa5, @byte_dest + +shlr_b_disp32_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest-666, er0 + shlr.b @(666:32, er0) ; shift right logical by one, disp32 +;;; .word 0x7884 +;;; .word 0x6a28 +;;; .long 666 +;;; .word 0x1100 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 byte_dest-666 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0101 0010 + cmp.b #0x52, @byte_dest + beq .Lbdisp321 + fail +.Lbdisp321: + mov.b #0xa5, @byte_dest + +shlr_b_abs16_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shlr.b @byte_dest:16 ; shift right logical by one, abs16 +;;; .word 0x6a18 +;;; .word byte_dest +;;; .word 0x1100 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0101 0010 + cmp.b #0x52, @byte_dest + beq .Lbabs161 + fail +.Lbabs161: + mov.b #0xa5, @byte_dest + +shlr_b_abs32_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shlr.b @byte_dest:32 ; shift right logical by one, abs32 +;;; .word 0x6a38 +;;; .long byte_dest +;;; .word 0x1100 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0101 0010 + cmp.b #0x52, @byte_dest + beq .Lbabs321 + fail +.Lbabs321: + mov.b #0xa5, @byte_dest +.endif + +shlr_b_reg8_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shlr.b #2, r0l ; shift right logical by two +;;; .word 0x1148 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + test_h_gr16 0xa529 r0 ; 1010 0101 -> 0010 1001 +.if (sim_cpu) + test_h_gr32 0xa5a5a529 er0 +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +shlr_b_ind_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest, er0 + shlr.b #2, @er0 ; shift right logical by two, indirect +;;; .word 0x7d00 +;;; .word 0x1140 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 byte_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0010 1001 + cmp.b #0x29, @byte_dest + beq .Lbind2 + fail +.Lbind2: + mov.b #0xa5, @byte_dest + +shlr_b_postinc_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest, er0 + shlr.b #2, @er0+ ; shift right logical by two, postinc +;;; .word 0x0174 +;;; .word 0x6c08 +;;; .word 0x1140 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 byte_dest+1 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0010 1001 + cmp.b #0x29, @byte_dest + beq .Lbpostinc2 + fail +.Lbpostinc2: + mov.b #0xa5, @byte_dest + +shlr_b_postdec_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest, er0 + shlr.b #2, @er0- ; shift right logical by two, postdec +;;; .word 0x0176 +;;; .word 0x6c08 +;;; .word 0x1140 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 byte_dest-1 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0010 1001 + cmp.b #0x29, @byte_dest + beq .Lbpostdec2 + fail +.Lbpostdec2: + mov.b #0xa5, @byte_dest + +shlr_b_preinc_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest-1, er0 + shlr.b #2, @+er0 ; shift right logical by two, preinc +;;; .word 0x0175 +;;; .word 0x6c08 +;;; .word 0x1140 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 byte_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0010 1001 + cmp.b #0x29, @byte_dest + beq .Lbpreinc2 + fail +.Lbpreinc2: + mov.b #0xa5, @byte_dest + +shlr_b_predec_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest+1, er0 + shlr.b #2, @-er0 ; shift right logical by two, predec +;;; .word 0x0177 +;;; .word 0x6c08 +;;; .word 0x1140 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 byte_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0010 1001 + cmp.b #0x29, @byte_dest + beq .Lbpredec2 + fail +.Lbpredec2: + mov.b #0xa5, @byte_dest + +shlr_b_disp2_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest-2, er0 + shlr.b #2, @(2:2, er0) ; shift right logical by two, disp2 +;;; .word 0x0176 +;;; .word 0x6808 +;;; .word 0x1140 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 byte_dest-2 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0010 1001 + cmp.b #0x29, @byte_dest + beq .Lbdisp22 + fail +.Lbdisp22: + mov.b #0xa5, @byte_dest + +shlr_b_disp16_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest-44, er0 + shlr.b #2, @(44:16, er0) ; shift right logical by two, disp16 +;;; .word 0x0174 +;;; .word 0x6e08 +;;; .word 44 +;;; .word 0x1140 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 byte_dest-44 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0010 1001 + cmp.b #0x29, @byte_dest + beq .Lbdisp162 + fail +.Lbdisp162: + mov.b #0xa5, @byte_dest + +shlr_b_disp32_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest-666, er0 + shlr.b #2, @(666:32, er0) ; shift right logical by two, disp32 +;;; .word 0x7884 +;;; .word 0x6a28 +;;; .long 666 +;;; .word 0x1140 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 byte_dest-666 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0010 1001 + cmp.b #0x29, @byte_dest + beq .Lbdisp322 + fail +.Lbdisp322: + mov.b #0xa5, @byte_dest + +shlr_b_abs16_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shlr.b #2, @byte_dest:16 ; shift right logical by two, abs16 +;;; .word 0x6a18 +;;; .word byte_dest +;;; .word 0x1140 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0010 1001 + cmp.b #0x29, @byte_dest + beq .Lbabs162 + fail +.Lbabs162: + mov.b #0xa5, @byte_dest + +shlr_b_abs32_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shlr.b #2, @byte_dest:32 ; shift right logical by two, abs32 +;;; .word 0x6a38 +;;; .long byte_dest +;;; .word 0x1140 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0010 1001 + cmp.b #0x29, @byte_dest + beq .Lbabs322 + fail +.Lbabs322: + mov.b #0xa5, @byte_dest + +shlr_b_reg8_4: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shlr.b #4, r0l ; shift right logical by four +;;; .word 0x11a8 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr16 0xa50a r0 ; 1010 0101 -> 0000 1010 + test_h_gr32 0xa5a5a50a er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +shlr_b_reg8_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #5, r0h + shlr.b r0h, r0l ; shift right logical by register value + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr16 0x0505 r0 ; 1010 0101 -> 0000 0101 + test_h_gr32 0xa5a50505 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +shlr_b_ind_4: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest, er0 + shlr.b #4, @er0 ; shift right logical by four, indirect +;;; .word 0x7d00 +;;; .word 0x11a0 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 byte_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0000 1010 + cmp.b #0x0a, @byte_dest + beq .Lbind4 + fail +.Lbind4: + mov.b #0xa5, @byte_dest + +shlr_b_postinc_4: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest, er0 + shlr.b #4, @er0+ ; shift right logical by four, postinc +;;; .word 0x0174 +;;; .word 0x6c08 +;;; .word 0x11a0 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 byte_dest+1 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0000 1010 + cmp.b #0x0a, @byte_dest + beq .Lbpostinc4 + fail +.Lbpostinc4: + mov.b #0xa5, @byte_dest + +shlr_b_postdec_4: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest, er0 + shlr.b #4, @er0- ; shift right logical by four, postdec +;;; .word 0x0176 +;;; .word 0x6c08 +;;; .word 0x11a0 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 byte_dest-1 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0000 1010 + cmp.b #0x0a, @byte_dest + beq .Lbpostdec4 + fail +.Lbpostdec4: + mov.b #0xa5, @byte_dest + +shlr_b_preinc_4: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest-1, er0 + shlr.b #4, @+er0 ; shift right logical by four, preinc +;;; .word 0x0175 +;;; .word 0x6c08 +;;; .word 0x11a0 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 byte_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0000 1010 + cmp.b #0x0a, @byte_dest + beq .Lbpreinc4 + fail +.Lbpreinc4: + mov.b #0xa5, @byte_dest + +shlr_b_predec_4: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest+1, er0 + shlr.b #4, @-er0 ; shift right logical by four, predec +;;; .word 0x0177 +;;; .word 0x6c08 +;;; .word 0x11a0 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 byte_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0000 1010 + cmp.b #0x0a, @byte_dest + beq .Lbpredec4 + fail +.Lbpredec4: + mov.b #0xa5, @byte_dest + +shlr_b_disp2_4: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest-2, er0 + shlr.b #4, @(2:2, er0) ; shift right logical by four, disp2 +;;; .word 0x0176 +;;; .word 0x6808 +;;; .word 0x11a0 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 byte_dest-2 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0000 1010 + cmp.b #0x0a, @byte_dest + beq .Lbdisp24 + fail +.Lbdisp24: + mov.b #0xa5, @byte_dest + +shlr_b_disp16_4: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest-44, er0 + shlr.b #4, @(44:16, er0) ; shift right logical by four, disp16 +;;; .word 0x0174 +;;; .word 0x6e08 +;;; .word 44 +;;; .word 0x11a0 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 byte_dest-44 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0000 1010 + cmp.b #0x0a, @byte_dest + beq .Lbdisp164 + fail +.Lbdisp164: + mov.b #0xa5, @byte_dest + +shlr_b_disp32_4: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #byte_dest-666, er0 + shlr.b #4, @(666:32, er0) ; shift right logical by four, disp32 +;;; .word 0x7884 +;;; .word 0x6a28 +;;; .long 666 +;;; .word 0x11a0 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 byte_dest-666 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0000 1010 + cmp.b #0x0a, @byte_dest + beq .Lbdisp324 + fail +.Lbdisp324: + mov.b #0xa5, @byte_dest + +shlr_b_abs16_4: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shlr.b #4, @byte_dest:16 ; shift right logical by four, abs16 +;;; .word 0x6a18 +;;; .word byte_dest +;;; .word 0x11a0 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0000 1010 + cmp.b #0x0a, @byte_dest + beq .Lbabs164 + fail +.Lbabs164: + mov.b #0xa5, @byte_dest + +shlr_b_abs32_4: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shlr.b #4, @byte_dest:32 ; shift right logical by four, abs32 +;;; .word 0x6a38 +;;; .long byte_dest +;;; .word 0x11a0 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 -> 0000 1010 + cmp.b #0x0a, @byte_dest + beq .Lbabs324 + fail +.Lbabs324: + mov.b #0xa5, @byte_dest +.endif + +.if (sim_cpu == h8sx) +shlr_w_imm5_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shlr.w #15:5, r0 ; shift right logical by 5-bit immediate +;;; .word 0x038f +;;; .word 0x1110 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + ; 1010 0101 1010 0101 -> 0000 0000 0000 0001 + test_h_gr32 0xa5a50001 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif + +.if (sim_cpu) ; Not available in h8300 mode +shlr_w_reg16_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shlr.w r0 ; shift right logical by one +;;; .word 0x1110 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + test_h_gr16 0x52d2 r0 ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 + test_h_gr32 0xa5a552d2 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +shlr_w_ind_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest, er0 + shlr.w @er0 ; shift right logical by one, indirect +;;; .word 0x7d80 +;;; .word 0x1110 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 + cmp.w #0x52d2, @word_dest + beq .Lwind1 + fail +.Lwind1: + mov.w #0xa5a5, @word_dest + +shlr_w_postinc_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest, er0 + shlr.w @er0+ ; shift right logical by one, postinc +;;; .word 0x0154 +;;; .word 0x6d08 +;;; .word 0x1110 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest+2 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 + cmp.w #0x52d2, @word_dest + beq .Lwpostinc1 + fail +.Lwpostinc1: + mov.w #0xa5a5, @word_dest + +shlr_w_postdec_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest, er0 + shlr.w @er0- ; shift right logical by one, postdec +;;; .word 0x0156 +;;; .word 0x6d08 +;;; .word 0x1110 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest-2 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 + cmp.w #0x52d2, @word_dest + beq .Lwpostdec1 + fail +.Lwpostdec1: + mov.w #0xa5a5, @word_dest + +shlr_w_preinc_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest-2, er0 + shlr.w @+er0 ; shift right logical by one, preinc +;;; .word 0x0155 +;;; .word 0x6d08 +;;; .word 0x1110 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 + cmp.w #0x52d2, @word_dest + beq .Lwpreinc1 + fail +.Lwpreinc1: + mov.w #0xa5a5, @word_dest + +shlr_w_predec_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest+2, er0 + shlr.w @-er0 ; shift right logical by one, predec +;;; .word 0x0157 +;;; .word 0x6d08 +;;; .word 0x1110 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 + cmp.w #0x52d2, @word_dest + beq .Lwpredec1 + fail +.Lwpredec1: + mov.w #0xa5a5, @word_dest + +shlr_w_disp2_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest-4, er0 + shlr.w @(4:2, er0) ; shift right logical by one, disp2 +;;; .word 0x0156 +;;; .word 0x6908 +;;; .word 0x1110 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest-4 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 + cmp.w #0x52d2, @word_dest + beq .Lwdisp21 + fail +.Lwdisp21: + mov.w #0xa5a5, @word_dest + +shlr_w_disp16_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest-44, er0 + shlr.w @(44:16, er0) ; shift right logical by one, disp16 +;;; .word 0x0154 +;;; .word 0x6f08 +;;; .word 44 +;;; .word 0x1110 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest-44 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 + cmp.w #0x52d2, @word_dest + beq .Lwdisp161 + fail +.Lwdisp161: + mov.w #0xa5a5, @word_dest + +shlr_w_disp32_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest-666, er0 + shlr.w @(666:32, er0) ; shift right logical by one, disp32 +;;; .word 0x7884 +;;; .word 0x6b28 +;;; .long 666 +;;; .word 0x1110 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest-666 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 + cmp.w #0x52d2, @word_dest + beq .Lwdisp321 + fail +.Lwdisp321: + mov.w #0xa5a5, @word_dest + +shlr_w_abs16_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shlr.w @word_dest:16 ; shift right logical by one, abs16 +;;; .word 0x6b18 +;;; .word word_dest +;;; .word 0x1110 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 + cmp.w #0x52d2, @word_dest + beq .Lwabs161 + fail +.Lwabs161: + mov.w #0xa5a5, @word_dest + +shlr_w_abs32_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shlr.w @word_dest:32 ; shift right logical by one, abs32 +;;; .word 0x6b38 +;;; .long word_dest +;;; .word 0x1110 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 + cmp.w #0x52d2, @word_dest + beq .Lwabs321 + fail +.Lwabs321: + mov.w #0xa5a5, @word_dest +.endif + +shlr_w_reg16_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shlr.w #2, r0 ; shift right logical by two +;;; .word 0x1150 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr16 0x2969 r0 ; 1010 0101 1010 0101 -> 0010 1001 0110 1001 + test_h_gr32 0xa5a52969 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +shlr_w_ind_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest, er0 + shlr.w #2, @er0 ; shift right logical by two, indirect +;;; .word 0x7d80 +;;; .word 0x1150 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0010 1001 0110 1001 + cmp.w #0x2969, @word_dest + beq .Lwind2 + fail +.Lwind2: + mov.w #0xa5a5, @word_dest + +shlr_w_postinc_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest, er0 + shlr.w #2, @er0+ ; shift right logical by two, postinc +;;; .word 0x0154 +;;; .word 0x6d08 +;;; .word 0x1150 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest+2 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0010 1001 0110 1001 + cmp.w #0x2969, @word_dest + beq .Lwpostinc2 + fail +.Lwpostinc2: + mov.w #0xa5a5, @word_dest + +shlr_w_postdec_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest, er0 + shlr.w #2, @er0- ; shift right logical by two, postdec +;;; .word 0x0156 +;;; .word 0x6d08 +;;; .word 0x1150 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest-2 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0010 1001 0110 1001 + cmp.w #0x2969, @word_dest + beq .Lwpostdec2 + fail +.Lwpostdec2: + mov.w #0xa5a5, @word_dest + +shlr_w_preinc_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest-2, er0 + shlr.w #2, @+er0 ; shift right logical by two, preinc +;;; .word 0x0155 +;;; .word 0x6d08 +;;; .word 0x1150 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0010 1001 0110 1001 + cmp.w #0x2969, @word_dest + beq .Lwpreinc2 + fail +.Lwpreinc2: + mov.w #0xa5a5, @word_dest + +shlr_w_predec_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest+2, er0 + shlr.w #2, @-er0 ; shift right logical by two, predec +;;; .word 0x0157 +;;; .word 0x6d08 +;;; .word 0x1150 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0010 1001 0110 1001 + cmp.w #0x2969, @word_dest + beq .Lwpredec2 + fail +.Lwpredec2: + mov.w #0xa5a5, @word_dest + +shlr_w_disp2_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest-4, er0 + shlr.w #2, @(4:2, er0) ; shift right logical by two, disp2 +;;; .word 0x0156 +;;; .word 0x6908 +;;; .word 0x1150 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest-4 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0010 1001 0110 1001 + cmp.w #0x2969, @word_dest + beq .Lwdisp22 + fail +.Lwdisp22: + mov.w #0xa5a5, @word_dest + +shlr_w_disp16_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest-44, er0 + shlr.w #2, @(44:16, er0) ; shift right logical by two, disp16 +;;; .word 0x0154 +;;; .word 0x6f08 +;;; .word 44 +;;; .word 0x1150 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest-44 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0010 1001 0110 1001 + cmp.w #0x2969, @word_dest + beq .Lwdisp162 + fail +.Lwdisp162: + mov.w #0xa5a5, @word_dest + +shlr_w_disp32_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest-666, er0 + shlr.w #2, @(666:32, er0) ; shift right logical by two, disp32 +;;; .word 0x7884 +;;; .word 0x6b28 +;;; .long 666 +;;; .word 0x1150 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest-666 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0010 1001 0110 1001 + cmp.w #0x2969, @word_dest + beq .Lwdisp322 + fail +.Lwdisp322: + mov.w #0xa5a5, @word_dest + +shlr_w_abs16_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shlr.w #2, @word_dest:16 ; shift right logical by two, abs16 +;;; .word 0x6b18 +;;; .word word_dest +;;; .word 0x1150 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0010 1001 0110 1001 + cmp.w #0x2969, @word_dest + beq .Lwabs162 + fail +.Lwabs162: + mov.w #0xa5a5, @word_dest + +shlr_w_abs32_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shlr.w #2, @word_dest:32 ; shift right logical by two, abs32 +;;; .word 0x6b38 +;;; .long word_dest +;;; .word 0x1150 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0010 1001 0110 1001 + cmp.w #0x2969, @word_dest + beq .Lwabs322 + fail +.Lwabs322: + mov.w #0xa5a5, @word_dest + +shlr_w_reg16_4: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shlr.w #4, r0 ; shift right logical by four +;;; .word 0x1120 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr16 0x0a5a r0 ; 1010 0101 1010 0101 -> 0000 1010 0101 1010 + test_h_gr32 0xa5a50a5a er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +shlr_w_reg16_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #5, r1l + shlr.w r1l, r0 ; shift right logical by register value + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr16 0x052d r0 ; 1010 0101 1010 0101 -> 0000 0101 0010 1101 + test_h_gr32 0xa5a5052d er0 + test_h_gr32 0xa5a5a505 er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +shlr_w_ind_4: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest, er0 + shlr.w #4, @er0 ; shift right logical by four, indirect +;;; .word 0x7d80 +;;; .word 0x1120 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0000 1010 0101 1010 + cmp.w #0x0a5a, @word_dest + beq .Lwind4 + fail +.Lwind4: + mov.w #0xa5a5, @word_dest + +shlr_w_postinc_4: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest, er0 + shlr.w #4, @er0+ ; shift right logical by four, postinc +;;; .word 0x0154 +;;; .word 0x6d08 +;;; .word 0x1120 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest+2 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0000 1010 0101 1010 + cmp.w #0x0a5a, @word_dest + beq .Lwpostinc4 + fail +.Lwpostinc4: + mov.w #0xa5a5, @word_dest + +shlr_w_postdec_4: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest, er0 + shlr.w #4, @er0- ; shift right logical by four, postdec +;;; .word 0x0156 +;;; .word 0x6d08 +;;; .word 0x1120 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest-2 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0000 1010 0101 1010 + cmp.w #0x0a5a, @word_dest + beq .Lwpostdec4 + fail +.Lwpostdec4: + mov.w #0xa5a5, @word_dest + +shlr_w_preinc_4: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest-2, er0 + shlr.w #4, @+er0 ; shift right logical by four, preinc +;;; .word 0x0155 +;;; .word 0x6d08 +;;; .word 0x1120 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0000 1010 0101 1010 + cmp.w #0x0a5a, @word_dest + beq .Lwpreinc4 + fail +.Lwpreinc4: + mov.w #0xa5a5, @word_dest + +shlr_w_predec_4: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest+2, er0 + shlr.w #4, @-er0 ; shift right logical by four, predec +;;; .word 0x0157 +;;; .word 0x6d08 +;;; .word 0x1120 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0000 1010 0101 1010 + cmp.w #0x0a5a, @word_dest + beq .Lwpredec4 + fail +.Lwpredec4: + mov.w #0xa5a5, @word_dest + +shlr_w_disp2_4: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest-4, er0 + shlr.w #4, @(4:2, er0) ; shift right logical by four, disp2 +;;; .word 0x0156 +;;; .word 0x6908 +;;; .word 0x1120 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest-4 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0000 1010 0101 1010 + cmp.w #0x0a5a, @word_dest + beq .Lwdisp24 + fail +.Lwdisp24: + mov.w #0xa5a5, @word_dest + +shlr_w_disp16_4: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest-44, er0 + shlr.w #4, @(44:16, er0) ; shift right logical by four, disp16 +;;; .word 0x0154 +;;; .word 0x6f08 +;;; .word 44 +;;; .word 0x1120 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest-44 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0000 1010 0101 1010 + cmp.w #0x0a5a, @word_dest + beq .Lwdisp164 + fail +.Lwdisp164: + mov.w #0xa5a5, @word_dest + +shlr_w_disp32_4: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest-666, er0 + shlr.w #4, @(666:32, er0) ; shift right logical by four, disp32 +;;; .word 0x7884 +;;; .word 0x6b28 +;;; .long 666 +;;; .word 0x1120 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest-666 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0000 1010 0101 1010 + cmp.w #0x0a5a, @word_dest + beq .Lwdisp324 + fail +.Lwdisp324: + mov.w #0xa5a5, @word_dest + +shlr_w_abs16_4: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shlr.w #4, @word_dest:16 ; shift right logical by four, abs16 +;;; .word 0x6b18 +;;; .word word_dest +;;; .word 0x1120 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0000 1010 0101 1010 + cmp.w #0x0a5a, @word_dest + beq .Lwabs164 + fail +.Lwabs164: + mov.w #0xa5a5, @word_dest + +shlr_w_abs32_4: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shlr.w #4, @word_dest:32 ; shift right logical by four, abs32 +;;; .word 0x6b38 +;;; .long word_dest +;;; .word 0x1120 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0000 1010 0101 1010 + cmp.w #0x0a5a, @word_dest + beq .Lwabs324 + fail +.Lwabs324: + mov.w #0xa5a5, @word_dest + +shlr_w_reg16_8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shlr.w #8, r0 ; shift right logical by eight +;;; .word 0x1160 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr16 0x00a5 r0 ; 1010 0101 1010 0101 -> 0000 0000 1010 0101 + test_h_gr32 0xa5a500a5 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +shlr_w_ind_8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest, er0 + shlr.w #8, @er0 ; shift right logical by eight, indirect +;;; .word 0x7d80 +;;; .word 0x1160 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0000 0000 1010 0101 + cmp.w #0x00a5, @word_dest + beq .Lwind8 + fail +.Lwind8: + mov.w #0xa5a5, @word_dest + +shlr_w_postinc_8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest, er0 + shlr.w #8, @er0+ ; shift right logical by eight, postinc +;;; .word 0x0154 +;;; .word 0x6d08 +;;; .word 0x1160 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest+2 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0000 0000 1010 0101 + cmp.w #0x00a5, @word_dest + beq .Lwpostinc8 + fail +.Lwpostinc8: + mov.w #0xa5a5, @word_dest + +shlr_w_postdec_8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest, er0 + shlr.w #8, @er0- ; shift right logical by eight, postdec +;;; .word 0x0156 +;;; .word 0x6d08 +;;; .word 0x1160 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest-2 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0000 0000 1010 0101 + cmp.w #0x00a5, @word_dest + beq .Lwpostdec8 + fail +.Lwpostdec8: + mov.w #0xa5a5, @word_dest + +shlr_w_preinc_8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest-2, er0 + shlr.w #8, @+er0 ; shift right logical by eight, preinc +;;; .word 0x0155 +;;; .word 0x6d08 +;;; .word 0x1160 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0000 0000 1010 0101 + cmp.w #0x00a5, @word_dest + beq .Lwpreinc8 + fail +.Lwpreinc8: + mov.w #0xa5a5, @word_dest + +shlr_w_predec_8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest+2, er0 + shlr.w #8, @-er0 ; shift right logical by eight, predec +;;; .word 0x0157 +;;; .word 0x6d08 +;;; .word 0x1160 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0000 0000 1010 0101 + cmp.w #0x00a5, @word_dest + beq .Lwpredec8 + fail +.Lwpredec8: + mov.w #0xa5a5, @word_dest + +shlr_w_disp2_8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest-4, er0 + shlr.w #8, @(4:2, er0) ; shift right logical by eight, disp2 +;;; .word 0x0156 +;;; .word 0x6908 +;;; .word 0x1160 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest-4 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0000 0000 1010 0101 + cmp.w #0x00a5, @word_dest + beq .Lwdisp28 + fail +.Lwdisp28: + mov.w #0xa5a5, @word_dest + +shlr_w_disp16_8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest-44, er0 + shlr.w #8, @(44:16, er0) ; shift right logical by eight, disp16 +;;; .word 0x0154 +;;; .word 0x6f08 +;;; .word 44 +;;; .word 0x1160 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest-44 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0000 0000 1010 0101 + cmp.w #0x00a5, @word_dest + beq .Lwdisp168 + fail +.Lwdisp168: + mov.w #0xa5a5, @word_dest + +shlr_w_disp32_8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #word_dest-666, er0 + shlr.w #8, @(666:32, er0) ; shift right logical by eight, disp32 +;;; .word 0x7884 +;;; .word 0x6b28 +;;; .long 666 +;;; .word 0x1160 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 word_dest-666 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0000 0000 1010 0101 + cmp.w #0x00a5, @word_dest + beq .Lwdisp328 + fail +.Lwdisp328: + mov.w #0xa5a5, @word_dest + +shlr_w_abs16_8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shlr.w #8, @word_dest:16 ; shift right logical by eight, abs16 +;;; .word 0x6b18 +;;; .word word_dest +;;; .word 0x1160 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0000 0000 1010 0101 + cmp.w #0x00a5, @word_dest + beq .Lwabs168 + fail +.Lwabs168: + mov.w #0xa5a5, @word_dest + +shlr_w_abs32_8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shlr.w #8, @word_dest:32 ; shift right logical by eight, abs32 +;;; .word 0x6b38 +;;; .long word_dest +;;; .word 0x1160 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 -> 0000 0000 1010 0101 + cmp.w #0x00a5, @word_dest + beq .Lwabs328 + fail +.Lwabs328: + mov.w #0xa5a5, @word_dest + +shlr_l_imm5_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shlr.l #31:5, er0 ; shift right logical by 5-bit immediate +;;; .word 0x0399 +;;; .word 0x1130 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ; -> 0000 0000 0000 0000 0000 0000 0000 0001 + test_h_gr32 0x1 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif + +shlr_l_reg32_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shlr.l er0 ; shift right logical by one, register +;;; .word 0x1130 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ; -> 0101 0010 1101 0010 1101 0010 1101 0010 + test_h_gr32 0x52d2d2d2 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +shlr_l_ind_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest, er0 + shlr.l @er0 ; shift right logical by one, indirect +;;; .word 0x0104 +;;; .word 0x6908 +;;; .word 0x1130 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 + cmp.l #0x52d2d2d2, @long_dest + beq .Llind1 + fail +.Llind1: + mov #0xa5a5a5a5, @long_dest + +shlr_l_postinc_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest, er0 + shlr.l @er0+ ; shift right logical by one, postinc +;;; .word 0x0104 +;;; .word 0x6d08 +;;; .word 0x1130 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest+4 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 + cmp.l #0x52d2d2d2, @long_dest + beq .Llpostinc1 + fail +.Llpostinc1: + mov #0xa5a5a5a5, @long_dest + +shlr_l_postdec_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest, er0 + shlr.l @er0- ; shift right logical by one, postdec +;;; .word 0x0106 +;;; .word 0x6d08 +;;; .word 0x1130 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest-4 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 + cmp.l #0x52d2d2d2, @long_dest + beq .Llpostdec1 + fail +.Llpostdec1: + mov #0xa5a5a5a5, @long_dest + +shlr_l_preinc_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest-4, er0 + shlr.l @+er0 ; shift right logical by one, preinc +;;; .word 0x0105 +;;; .word 0x6d08 +;;; .word 0x1130 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 + cmp.l #0x52d2d2d2, @long_dest + beq .Llpreinc1 + fail +.Llpreinc1: + mov #0xa5a5a5a5, @long_dest + +shlr_l_predec_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest+4, er0 + shlr.l @-er0 ; shift right logical by one, predec +;;; .word 0x0107 +;;; .word 0x6d08 +;;; .word 0x1130 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 + cmp.l #0x52d2d2d2, @long_dest + beq .Llpredec1 + fail +.Llpredec1: + mov #0xa5a5a5a5, @long_dest + +shlr_l_disp2_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest-8, er0 + shlr.l @(8:2, er0) ; shift right logical by one, disp2 +;;; .word 0x0106 +;;; .word 0x6908 +;;; .word 0x1130 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest-8 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 + cmp.l #0x52d2d2d2, @long_dest + beq .Lldisp21 + fail +.Lldisp21: + mov #0xa5a5a5a5, @long_dest + +shlr_l_disp16_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest-44, er0 + shlr.l @(44:16, er0) ; shift right logical by one, disp16 +;;; .word 0x0104 +;;; .word 0x6f08 +;;; .word 44 +;;; .word 0x1130 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest-44 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 + cmp.l #0x52d2d2d2, @long_dest + beq .Lldisp161 + fail +.Lldisp161: + mov #0xa5a5a5a5, @long_dest + +shlr_l_disp32_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest-666, er0 + shlr.l @(666:32, er0) ; shift right logical by one, disp32 +;;; .word 0x7884 +;;; .word 0x6b28 +;;; .long 666 +;;; .word 0x1130 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest-666 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 + cmp.l #0x52d2d2d2, @long_dest + beq .Lldisp321 + fail +.Lldisp321: + mov #0xa5a5a5a5, @long_dest + +shlr_l_abs16_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shlr.l @long_dest:16 ; shift right logical by one, abs16 +;;; .word 0x0104 +;;; .word 0x6b08 +;;; .word long_dest +;;; .word 0x1130 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 + cmp.l #0x52d2d2d2, @long_dest + beq .Llabs161 + fail +.Llabs161: + mov #0xa5a5a5a5, @long_dest + +shlr_l_abs32_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shlr.l @long_dest:32 ; shift right logical by one, abs32 +;;; .word 0x0104 +;;; .word 0x6b28 +;;; .long long_dest +;;; .word 0x1130 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 + cmp.l #0x52d2d2d2, @long_dest + beq .Llabs321 + fail +.Llabs321: + mov #0xa5a5a5a5, @long_dest +.endif + +shlr_l_reg32_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shlr.l #2, er0 ; shift right logical by two, register +;;; .word 0x1170 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ; -> 0010 1001 0110 1001 0110 1001 0110 1001 + test_h_gr32 0x29696969 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) + +shlr_l_ind_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest, er0 + shlr.l #2, @er0 ; shift right logical by two, indirect +;;; .word 0x0104 +;;; .word 0x6908 +;;; .word 0x1170 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0010 1001 0110 1001 0110 1001 0110 1001 + cmp.l #0x29696969, @long_dest + beq .Llind2 + fail +.Llind2: + mov #0xa5a5a5a5, @long_dest + +shlr_l_postinc_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest, er0 + shlr.l #2, @er0+ ; shift right logical by two, postinc +;;; .word 0x0104 +;;; .word 0x6d08 +;;; .word 0x1170 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest+4 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0010 1001 0110 1001 0110 1001 0110 1001 + cmp.l #0x29696969, @long_dest + beq .Llpostinc2 + fail +.Llpostinc2: + mov #0xa5a5a5a5, @long_dest + +shlr_l_postdec_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest, er0 + shlr.l #2, @er0- ; shift right logical by two, postdec +;;; .word 0x0106 +;;; .word 0x6d08 +;;; .word 0x1170 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest-4 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0010 1001 0110 1001 0110 1001 0110 1001 + cmp.l #0x29696969, @long_dest + beq .Llpostdec2 + fail +.Llpostdec2: + mov #0xa5a5a5a5, @long_dest + +shlr_l_preinc_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest-4, er0 + shlr.l #2, @+er0 ; shift right logical by two, preinc +;;; .word 0x0105 +;;; .word 0x6d08 +;;; .word 0x1170 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0010 1001 0110 1001 0110 1001 0110 1001 + cmp.l #0x29696969, @long_dest + beq .Llpreinc2 + fail +.Llpreinc2: + mov #0xa5a5a5a5, @long_dest + +shlr_l_predec_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest+4, er0 + shlr.l #2, @-er0 ; shift right logical by two, predec +;;; .word 0x0107 +;;; .word 0x6d08 +;;; .word 0x1170 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0010 1001 0110 1001 0110 1001 0110 1001 + cmp.l #0x29696969, @long_dest + beq .Llpredec2 + fail +.Llpredec2: + mov #0xa5a5a5a5, @long_dest + +shlr_l_disp2_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest-8, er0 + shlr.l #2, @(8:2, er0) ; shift right logical by two, disp2 +;;; .word 0x0106 +;;; .word 0x6908 +;;; .word 0x1170 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest-8 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0010 1001 0110 1001 0110 1001 0110 1001 + cmp.l #0x29696969, @long_dest + beq .Lldisp22 + fail +.Lldisp22: + mov #0xa5a5a5a5, @long_dest + +shlr_l_disp16_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest-44, er0 + shlr.l #2, @(44:16, er0) ; shift right logical by two, disp16 +;;; .word 0x0104 +;;; .word 0x6f08 +;;; .word 44 +;;; .word 0x1170 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest-44 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0010 1001 0110 1001 0110 1001 0110 1001 + cmp.l #0x29696969, @long_dest + beq .Lldisp162 + fail +.Lldisp162: + mov #0xa5a5a5a5, @long_dest + +shlr_l_disp32_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest-666, er0 + shlr.l #2, @(666:32, er0) ; shift right logical by two, disp32 +;;; .word 0x7884 +;;; .word 0x6b28 +;;; .long 666 +;;; .word 0x1170 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest-666 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0010 1001 0110 1001 0110 1001 0110 1001 + cmp.l #0x29696969, @long_dest + beq .Lldisp322 + fail +.Lldisp322: + mov #0xa5a5a5a5, @long_dest + +shlr_l_abs16_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shlr.l #2, @long_dest:16 ; shift right logical by two, abs16 +;;; .word 0x0104 +;;; .word 0x6b08 +;;; .word long_dest +;;; .word 0x1170 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0010 1001 0110 1001 0110 1001 0110 1001 + cmp.l #0x29696969, @long_dest + beq .Llabs162 + fail +.Llabs162: + mov #0xa5a5a5a5, @long_dest + +shlr_l_abs32_2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shlr.l #2, @long_dest:32 ; shift right logical by two, abs32 +;;; .word 0x0104 +;;; .word 0x6b28 +;;; .long long_dest +;;; .word 0x1170 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0010 1001 0110 1001 0110 1001 0110 1001 + cmp.l #0x29696969, @long_dest + beq .Llabs322 + fail +.Llabs322: + mov #0xa5a5a5a5, @long_dest + +shlr_l_reg32_4: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shlr.l #4, er0 ; shift right logical by four, register +;;; .word 0x1138 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ; -> 0000 1010 0101 1010 0101 1010 0101 1010 + test_h_gr32 0x0a5a5a5a er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +shlr_l_reg32_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #5, r1l + shlr.l r1l, er0 ; shift right logical by value of register + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ; -> 0000 0101 0010 1101 0010 1101 0010 1101 + test_h_gr32 0x052d2d2d er0 + test_h_gr32 0xa5a5a505 er1 + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +shlr_l_ind_4: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest, er0 + shlr.l #4, @er0 ; shift right logical by four, indirect +;;; .word 0x0104 +;;; .word 0x6908 +;;; .word 0x1138 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0000 1010 0101 1010 0101 1010 0101 1010 + cmp.l #0x0a5a5a5a, @long_dest + beq .Llind4 + fail +.Llind4: + mov #0xa5a5a5a5, @long_dest + +shlr_l_postinc_4: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest, er0 + shlr.l #4, @er0+ ; shift right logical by four, postinc +;;; .word 0x0104 +;;; .word 0x6d08 +;;; .word 0x1138 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest+4 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0000 1010 0101 1010 0101 1010 0101 1010 + cmp.l #0x0a5a5a5a, @long_dest + beq .Llpostinc4 + fail +.Llpostinc4: + mov #0xa5a5a5a5, @long_dest + +shlr_l_postdec_4: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest, er0 + shlr.l #4, @er0- ; shift right logical by four, postdec +;;; .word 0x0106 +;;; .word 0x6d08 +;;; .word 0x1138 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest-4 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0000 1010 0101 1010 0101 1010 0101 1010 + cmp.l #0x0a5a5a5a, @long_dest + beq .Llpostdec4 + fail +.Llpostdec4: + mov #0xa5a5a5a5, @long_dest + +shlr_l_preinc_4: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest-4, er0 + shlr.l #4, @+er0 ; shift right logical by four, preinc +;;; .word 0x0105 +;;; .word 0x6d08 +;;; .word 0x1138 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0000 1010 0101 1010 0101 1010 0101 1010 + cmp.l #0x0a5a5a5a, @long_dest + beq .Llpreinc4 + fail +.Llpreinc4: + mov #0xa5a5a5a5, @long_dest + +shlr_l_predec_4: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest+4, er0 + shlr.l #4, @-er0 ; shift right logical by four, predec +;;; .word 0x0107 +;;; .word 0x6d08 +;;; .word 0x1138 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0000 1010 0101 1010 0101 1010 0101 1010 + cmp.l #0x0a5a5a5a, @long_dest + beq .Llpredec4 + fail +.Llpredec4: + mov #0xa5a5a5a5, @long_dest + +shlr_l_disp2_4: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest-8, er0 + shlr.l #4, @(8:2, er0) ; shift right logical by four, disp2 +;;; .word 0x0106 +;;; .word 0x6908 +;;; .word 0x1138 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest-8 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0000 1010 0101 1010 0101 1010 0101 1010 + cmp.l #0x0a5a5a5a, @long_dest + beq .Lldisp24 + fail +.Lldisp24: + mov #0xa5a5a5a5, @long_dest + +shlr_l_disp16_4: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest-44, er0 + shlr.l #4, @(44:16, er0) ; shift right logical by four, disp16 +;;; .word 0x0104 +;;; .word 0x6f08 +;;; .word 44 +;;; .word 0x1138 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest-44 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0000 1010 0101 1010 0101 1010 0101 1010 + cmp.l #0x0a5a5a5a, @long_dest + beq .Lldisp164 + fail +.Lldisp164: + mov #0xa5a5a5a5, @long_dest + +shlr_l_disp32_4: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest-666, er0 + shlr.l #4, @(666:32, er0) ; shift right logical by four, disp32 +;;; .word 0x7884 +;;; .word 0x6b28 +;;; .long 666 +;;; .word 0x1138 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest-666 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0000 1010 0101 1010 0101 1010 0101 1010 + cmp.l #0x0a5a5a5a, @long_dest + beq .Lldisp324 + fail +.Lldisp324: + mov #0xa5a5a5a5, @long_dest + +shlr_l_abs16_4: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shlr.l #4, @long_dest:16 ; shift right logical by four, abs16 +;;; .word 0x0104 +;;; .word 0x6b08 +;;; .word long_dest +;;; .word 0x1138 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0000 1010 0101 1010 0101 1010 0101 1010 + cmp.l #0x0a5a5a5a, @long_dest + beq .Llabs164 + fail +.Llabs164: + mov #0xa5a5a5a5, @long_dest + +shlr_l_abs32_4: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shlr.l #4, @long_dest:32 ; shift right logical by four, abs32 +;;; .word 0x0104 +;;; .word 0x6b28 +;;; .long long_dest +;;; .word 0x1138 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0000 1010 0101 1010 0101 1010 0101 1010 + cmp.l #0x0a5a5a5a, @long_dest + beq .Llabs324 + fail +.Llabs324: + mov #0xa5a5a5a5, @long_dest + +shlr_l_reg32_8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shlr.l #8, er0 ; shift right logical by eight, register +;;; .word 0x1178 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ; -> 0000 0000 1010 0101 1010 0101 1010 0101 + test_h_gr32 0x00a5a5a5 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +shlr_l_ind_8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest, er0 + shlr.l #8, @er0 ; shift right logical by eight, indirect +;;; .word 0x0104 +;;; .word 0x6908 +;;; .word 0x1178 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0000 0000 1010 0101 1010 0101 1010 0101 + cmp.l #0x00a5a5a5, @long_dest + beq .Llind8 + fail +.Llind8: + mov #0xa5a5a5a5, @long_dest + +shlr_l_postinc_8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest, er0 + shlr.l #8, @er0+ ; shift right logical by eight, postinc +;;; .word 0x0104 +;;; .word 0x6d08 +;;; .word 0x1178 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest+4 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0000 0000 1010 0101 1010 0101 1010 0101 + cmp.l #0x00a5a5a5, @long_dest + beq .Llpostinc8 + fail +.Llpostinc8: + mov #0xa5a5a5a5, @long_dest + +shlr_l_postdec_8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest, er0 + shlr.l #8, @er0- ; shift right logical by eight, postdec +;;; .word 0x0106 +;;; .word 0x6d08 +;;; .word 0x1178 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest-4 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0000 0000 1010 0101 1010 0101 1010 0101 + cmp.l #0x00a5a5a5, @long_dest + beq .Llpostdec8 + fail +.Llpostdec8: + mov #0xa5a5a5a5, @long_dest + +shlr_l_preinc_8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest-4, er0 + shlr.l #8, @+er0 ; shift right logical by eight, preinc +;;; .word 0x0105 +;;; .word 0x6d08 +;;; .word 0x1178 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0000 0000 1010 0101 1010 0101 1010 0101 + cmp.l #0x00a5a5a5, @long_dest + beq .Llpreinc8 + fail +.Llpreinc8: + mov #0xa5a5a5a5, @long_dest + +shlr_l_predec_8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest+4, er0 + shlr.l #8, @-er0 ; shift right logical by eight, predec +;;; .word 0x0107 +;;; .word 0x6d08 +;;; .word 0x1178 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0000 0000 1010 0101 1010 0101 1010 0101 + cmp.l #0x00a5a5a5, @long_dest + beq .Llpredec8 + fail +.Llpredec8: + mov #0xa5a5a5a5, @long_dest + +shlr_l_disp2_8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest-8, er0 + shlr.l #8, @(8:2, er0) ; shift right logical by eight, disp2 +;;; .word 0x0106 +;;; .word 0x6908 +;;; .word 0x1178 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest-8 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0000 0000 1010 0101 1010 0101 1010 0101 + cmp.l #0x00a5a5a5, @long_dest + beq .Lldisp28 + fail +.Lldisp28: + mov #0xa5a5a5a5, @long_dest + +shlr_l_disp16_8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest-44, er0 + shlr.l #8, @(44:16, er0) ; shift right logical by eight, disp16 +;;; .word 0x0104 +;;; .word 0x6f08 +;;; .word 44 +;;; .word 0x1178 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest-44 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0000 0000 1010 0101 1010 0101 1010 0101 + cmp.l #0x00a5a5a5, @long_dest + beq .Lldisp168 + fail +.Lldisp168: + mov #0xa5a5a5a5, @long_dest + +shlr_l_disp32_8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest-666, er0 + shlr.l #8, @(666:32, er0) ; shift right logical by eight, disp32 +;;; .word 0x7884 +;;; .word 0x6b28 +;;; .long 666 +;;; .word 0x1178 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest-666 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0000 0000 1010 0101 1010 0101 1010 0101 + cmp.l #0x00a5a5a5, @long_dest + beq .Lldisp328 + fail +.Lldisp328: + mov #0xa5a5a5a5, @long_dest + +shlr_l_abs16_8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shlr.l #8, @long_dest:16 ; shift right logical by eight, abs16 +;;; .word 0x0104 +;;; .word 0x6b08 +;;; .word long_dest +;;; .word 0x1178 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0000 0000 1010 0101 1010 0101 1010 0101 + cmp.l #0x00a5a5a5, @long_dest + beq .Llabs168 + fail +.Llabs168: + mov #0xa5a5a5a5, @long_dest + +shlr_l_abs32_8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shlr.l #8, @long_dest:32 ; shift right logical by eight, abs32 +;;; .word 0x0104 +;;; .word 0x6b28 +;;; .long long_dest +;;; .word 0x1178 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0000 0000 1010 0101 1010 0101 1010 0101 + cmp.l #0x00a5a5a5, @long_dest + beq .Llabs328 + fail +.Llabs328: + mov #0xa5a5a5a5, @long_dest + +shlr_l_reg32_16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shlr.l #16, er0 ; shift right logical by sixteen, register +;;; .word 0x11f8 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0000 0000 0000 0000 1010 0101 1010 0101 + test_h_gr32 0x0000a5a5 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +shlr_l_ind_16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest, er0 + shlr.l #16, @er0 ; shift right logical by sixteen, indirect +;;; .word 0x0104 +;;; .word 0x6908 +;;; .word 0x11f8 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0000 0000 0000 0000 1010 0101 1010 0101 + cmp.l #0x0000a5a5, @long_dest + beq .Llind16 + fail +.Llind16: + mov #0xa5a5a5a5, @long_dest + +shlr_l_postinc_16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest, er0 + shlr.l #16, @er0+ ; shift right logical by sixteen, postinc +;;; .word 0x0104 +;;; .word 0x6d08 +;;; .word 0x11f8 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest+4 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0000 0000 0000 0000 1010 0101 1010 0101 + cmp.l #0x0000a5a5, @long_dest + beq .Llpostinc16 + fail +.Llpostinc16: + mov #0xa5a5a5a5, @long_dest + +shlr_l_postdec_16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest, er0 + shlr.l #16, @er0- ; shift right logical by sixteen, postdec +;;; .word 0x0106 +;;; .word 0x6d08 +;;; .word 0x11f8 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest-4 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0000 0000 0000 0000 1010 0101 1010 0101 + cmp.l #0x0000a5a5, @long_dest + beq .Llpostdec16 + fail +.Llpostdec16: + mov #0xa5a5a5a5, @long_dest + +shlr_l_preinc_16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest-4, er0 + shlr.l #16, @+er0 ; shift right logical by sixteen, preinc +;;; .word 0x0105 +;;; .word 0x6d08 +;;; .word 0x11f8 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0000 0000 0000 0000 1010 0101 1010 0101 + cmp.l #0x0000a5a5, @long_dest + beq .Llpreinc16 + fail +.Llpreinc16: + mov #0xa5a5a5a5, @long_dest + +shlr_l_predec_16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest+4, er0 + shlr.l #16, @-er0 ; shift right logical by sixteen, predec +;;; .word 0x0107 +;;; .word 0x6d08 +;;; .word 0x11f8 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0000 0000 0000 0000 1010 0101 1010 0101 + cmp.l #0x0000a5a5, @long_dest + beq .Llpredec16 + fail +.Llpredec16: + mov #0xa5a5a5a5, @long_dest + +shlr_l_disp2_16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest-8, er0 + shlr.l #16, @(8:2, er0) ; shift right logical by 16, dest2 +;;; .word 0x0106 +;;; .word 0x6908 +;;; .word 0x11f8 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest-8 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0000 0000 0000 0000 1010 0101 1010 0101 + cmp.l #0x0000a5a5, @long_dest + beq .Lldisp216 + fail +.Lldisp216: + mov #0xa5a5a5a5, @long_dest + +shlr_l_disp16_16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest-44, er0 + shlr.l #16, @(44:16, er0) ; shift right logical by 16, disp16 +;;; .word 0x0104 +;;; .word 0x6f08 +;;; .word 44 +;;; .word 0x11f8 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest-44 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0000 0000 0000 0000 1010 0101 1010 0101 + cmp.l #0x0000a5a5, @long_dest + beq .Lldisp1616 + fail +.Lldisp1616: + mov #0xa5a5a5a5, @long_dest + +shlr_l_disp32_16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + mov #long_dest-666, er0 + shlr.l #16, @(666:32, er0) ; shift right logical by 16, disp32 +;;; .word 0x7884 +;;; .word 0x6b28 +;;; .long 666 +;;; .word 0x11f8 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_h_gr32 long_dest-666 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0000 0000 0000 0000 1010 0101 1010 0101 + cmp.l #0x0000a5a5, @long_dest + beq .Lldisp3216 + fail +.Lldisp3216: + mov #0xa5a5a5a5, @long_dest + +shlr_l_abs16_16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shlr.l #16, @long_dest:16 ; shift right logical by 16, abs16 +;;; .word 0x0104 +;;; .word 0x6b08 +;;; .word long_dest +;;; .word 0x11f8 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0000 0000 0000 0000 1010 0101 1010 0101 + cmp.l #0x0000a5a5, @long_dest + beq .Llabs1616 + fail +.Llabs1616: + mov #0xa5a5a5a5, @long_dest + +shlr_l_abs32_16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + shlr.l #16, @long_dest:32 ; shift right logical by 16, abs32 +;;; .word 0x0104 +;;; .word 0x6b28 +;;; .long long_dest +;;; .word 0x11f8 + + test_carry_set ; H=0 N=0 Z=0 V=0 C=1 + test_zero_clear + test_ovf_clear + test_neg_clear + + test_gr_a5a5 0 ; Make sure ALL general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ; 1010 0101 1010 0101 1010 0101 1010 0101 + ;; -> 0000 0000 0000 0000 1010 0101 1010 0101 + cmp.l #0x0000a5a5, @long_dest + beq .Llabs3216 + fail +.Llabs3216: + mov #0xa5a5a5a5, @long_dest +.endif +.endif + pass + + exit 0 + diff --git a/sim/testsuite/sim/h8300/stack.s b/sim/testsuite/sim/h8300/stack.s new file mode 100644 index 0000000..dd53445 --- /dev/null +++ b/sim/testsuite/sim/h8300/stack.s @@ -0,0 +1,445 @@ +# Hitachi H8 testcase 'ldc' +# mach(): all +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + start + +.data + .align 4 +stack: +.if (sim_cpu == h8300) + .fill 128, 2, 0 +.else + .fill 128, 4, 0 +.endif +stacktop: + + .text + +push_w: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero +.if (sim_cpu == h8300) + mov.w #stacktop, r7 +.else + mov.l #stacktop, er7 +.endif + push.w r0 ; a5a5 is negative + test_neg_set + test_carry_clear + test_zero_clear + test_ovf_clear + + push.w r1 + push.w r2 + push.w r3 + + test_gr_a5a5 0 + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + + mov @stacktop-2, r0 + test_gr_a5a5 0 + mov @stacktop-4, r0 + test_gr_a5a5 0 + mov @stacktop-6, r0 + test_gr_a5a5 0 + mov @stacktop-8, r0 + test_gr_a5a5 0 + + mov.w #1, r1 + mov.w #2, r2 + mov.w #3, r3 + mov.w #4, r4 + + push.w r1 ; #1 is non-negative, non-zero + test_cc_clear + + push.w r2 + push.w r3 + push.w r4 + + test_h_gr16 1 r1 + test_h_gr16 2 r2 + test_h_gr16 3 r3 + test_h_gr16 4 r4 + + mov @stacktop-10, r0 + test_h_gr16 1 r0 + mov @stacktop-12, r0 + test_h_gr16 2 r0 + mov @stacktop-14, r0 + test_h_gr16 3 r0 + mov @stacktop-16, r0 + test_h_gr16 4 r0 + +.if (sim_cpu == h8300) + test_h_gr16 4 r0 + test_h_gr16 1 r1 + test_h_gr16 2 r2 + test_h_gr16 3 r3 + test_h_gr16 4 r4 +;;; test_h_gr16 stacktop-16 r7 ; FIXME +.else + test_h_gr32 0xa5a50004 er0 + test_h_gr32 0xa5a50001 er1 + test_h_gr32 0xa5a50002 er2 + test_h_gr32 0xa5a50003 er3 + test_h_gr32 0xa5a50004 er4 + test_h_gr32 stacktop-16 er7 +.endif + test_gr_a5a5 5 + test_gr_a5a5 6 + +pop_w: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero +.if (sim_cpu == h8300) + mov.w #stacktop-16, r7 +.else + mov.l #stacktop-16, er7 +.endif + pop.w r4 + pop.w r3 + pop.w r2 + pop.w r1 ; Should set all flags zero + test_cc_clear + + test_h_gr16 1 r1 + test_h_gr16 2 r2 + test_h_gr16 3 r3 + test_h_gr16 4 r4 + + pop.w r4 + pop.w r3 + pop.w r2 + pop.w r1 ; a5a5 is negative + test_neg_set + test_carry_clear + test_zero_clear + test_ovf_clear + + test_gr_a5a5 0 + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 +.if (sim_cpu == h8300) +;;; test_h_gr16 stacktop r7 ; FIXME +.else + test_h_gr32 stacktop er7 +.endif + +.if (sim_cpu) ; non-zero means not h8300 +push_l: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + mov.l #stacktop, er7 + push.l er0 ; a5a5 is negative + test_neg_set + test_carry_clear + test_zero_clear + test_ovf_clear + + push.l er1 + push.l er2 + push.l er3 + + test_gr_a5a5 0 + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + + mov @stacktop-4, er0 + test_gr_a5a5 0 + mov @stacktop-8, er0 + test_gr_a5a5 0 + mov @stacktop-12, er0 + test_gr_a5a5 0 + mov @stacktop-16, er0 + test_gr_a5a5 0 + + mov #1, er1 + mov #2, er2 + mov #3, er3 + mov #4, er4 + + push.l er1 ; #1 is non-negative, non-zero + test_cc_clear + + push.l er2 + push.l er3 + push.l er4 + + test_h_gr32 1 er1 + test_h_gr32 2 er2 + test_h_gr32 3 er3 + test_h_gr32 4 er4 + + mov @stacktop-20, er0 + test_h_gr32 1 er0 + mov @stacktop-24, er0 + test_h_gr32 2 er0 + mov @stacktop-28, er0 + test_h_gr32 3 er0 + mov @stacktop-32, er0 + test_h_gr32 4 er0 + + test_h_gr32 4 er0 + test_h_gr32 1 er1 + test_h_gr32 2 er2 + test_h_gr32 3 er3 + test_h_gr32 4 er4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_h_gr32 stacktop-32 er7 + +pop_l: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + mov.l #stacktop-32, er7 + pop.l er4 + pop.l er3 + pop.l er2 + pop.l er1 ; Should set all flags zero + test_cc_clear + + test_h_gr32 1 er1 + test_h_gr32 2 er2 + test_h_gr32 3 er3 + test_h_gr32 4 er4 + + pop.l er4 + pop.l er3 + pop.l er2 + pop.l er1 ; a5a5 is negative + test_neg_set + test_carry_clear + test_zero_clear + test_ovf_clear + + test_gr_a5a5 0 + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_h_gr32 stacktop er7 +.endif + + ;; Jump over subroutine + jmp _bsr + +bsr_jsr_func: + test_ccr 0 ; call should not affect ccr + mov.w #0, r0 + mov.w #1, r1 + mov.w #2, r2 + mov.w #3, r3 + mov.w #4, r4 + mov.w #5, r5 + mov.w #6, r6 + rts + +_bsr: set_grs_a5a5 +.if (sim_cpu == h8300) + mov.w #stacktop, r7 +.else + mov.l #stacktop, er7 +.endif + set_ccr_zero + bsr bsr_jsr_func + + test_h_gr16 0 r0 + test_h_gr16 1 r1 + test_h_gr16 2 r2 + test_h_gr16 3 r3 + test_h_gr16 4 r4 + test_h_gr16 5 r5 + test_h_gr16 6 r6 +.if (sim_cpu == h8300) +;;; test_h_gr16 stacktop, r7 ; FIXME +.else + test_h_gr32 stacktop, er7 +.endif + +_jsr: set_grs_a5a5 +.if (sim_cpu == h8300) + mov.w #stacktop, r7 +.else + mov.l #stacktop, er7 +.endif + set_ccr_zero + jsr bsr_jsr_func + + test_h_gr16 0 r0 + test_h_gr16 1 r1 + test_h_gr16 2 r2 + test_h_gr16 3 r3 + test_h_gr16 4 r4 + test_h_gr16 5 r5 + test_h_gr16 6 r6 +.if (sim_cpu == h8300) +;;; test_h_gr16 stacktop, r7 ; FIXME +.else + test_h_gr32 stacktop, er7 +.endif + +.if (sim_cpu) ; not zero ie. not h8300 +_trapa: + set_grs_a5a5 + mov.l #trap_handler, er7 ; trap vector + mov.l er7, @0x2c + mov.l #stacktop, er7 + set_ccr_zero + trapa #3 + + test_cc_clear ; ccr should be restored by rte + test_h_gr16 0x10 r0 + test_h_gr16 0x11 r1 + test_h_gr16 0x12 r2 + test_h_gr16 0x13 r3 + test_h_gr16 0x14 r4 + test_h_gr16 0x15 r5 + test_h_gr16 0x16 r6 + test_h_gr32 stacktop er7 +.endif + +.if (sim_cpu == h8sx) +_rtsl: ; Test rts/l insn. + set_grs_a5a5 + mov #0,r0l + mov #1,r1l + mov #2,r2l + mov #3,r3l + mov #4,r4l + mov #5,r5l + mov #6,r6l + mov #stacktop, er7 + + jsr rtsl1_func + test_h_gr32 0xa5a5a500 er0 + test_h_gr32 0xa5a5a501 er1 + test_h_gr32 0xa5a5a502 er2 + test_h_gr32 0xa5a5a503 er3 + test_h_gr32 0xa5a5a504 er4 + test_h_gr32 0xa5a5a505 er5 + test_h_gr32 0xa5a5a506 er6 + test_h_gr32 stacktop er7 + + jsr rtsl2_func + test_h_gr32 0xa5a5a500 er0 + test_h_gr32 0xa5a5a501 er1 + test_h_gr32 0xa5a5a502 er2 + test_h_gr32 0xa5a5a503 er3 + test_h_gr32 0xa5a5a504 er4 + test_h_gr32 0xa5a5a505 er5 + test_h_gr32 0xa5a5a506 er6 + test_h_gr32 stacktop er7 + + jsr rtsl3_func + test_h_gr32 0xa5a5a500 er0 + test_h_gr32 0xa5a5a501 er1 + test_h_gr32 0xa5a5a502 er2 + test_h_gr32 0xa5a5a503 er3 + test_h_gr32 0xa5a5a504 er4 + test_h_gr32 0xa5a5a505 er5 + test_h_gr32 0xa5a5a506 er6 + test_h_gr32 stacktop er7 + + jsr rtsl4_func + test_h_gr32 0xa5a5a500 er0 + test_h_gr32 0xa5a5a501 er1 + test_h_gr32 0xa5a5a502 er2 + test_h_gr32 0xa5a5a503 er3 + test_h_gr32 0xa5a5a504 er4 + test_h_gr32 0xa5a5a505 er5 + test_h_gr32 0xa5a5a506 er6 + test_h_gr32 stacktop er7 +.endif ; h8sx + + pass + + exit 0 + + ;; Handler for a software exception (trap). +trap_handler: + ;; Test the 'i' interrupt mask flag. + stc ccr, r0l + test_h_gr8 0x80, r0l + ;; Change the registers (so we know we've been here) + mov.w #0x10, r0 + mov.w #0x11, r1 + mov.w #0x12, r2 + mov.w #0x13, r3 + mov.w #0x14, r4 + mov.w #0x15, r5 + mov.w #0x16, r6 + ;; Change the ccr (which will be restored by RTE) + orc #0xff, ccr + rte + +.if (sim_cpu == h8sx) + ;; Functions for testing rts/l +rtsl1_func: ; Save and restore R0 + push.l er0 + ;; Now modify it, and verify the modification. + mov #0xfeedface, er0 + test_h_gr32 0xfeedface, er0 + ;; Then use rts/l to restore them and return. + rts/l er0 + +rtsl2_func: ; Save and restore R5 and R6 + push.l er5 + push.l er6 + ;; Now modify them, and verify the modification. + mov #0xdeadbeef, er5 + mov #0xfeedface, er6 + test_h_gr32 0xdeadbeef, er5 + test_h_gr32 0xfeedface, er6 + ;; Then use rts/l to restore them and return. + rts/l (er5-er6) + +rtsl3_func: ; Save and restore R4, R5, and R6 + push.l er4 + push.l er5 + push.l er6 + ;; Now modify them, and verify the modification. + mov #0xdeafcafe, er4 + mov #0xdeadbeef, er5 + mov #0xfeedface, er6 + test_h_gr32 0xdeafcafe, er4 + test_h_gr32 0xdeadbeef, er5 + test_h_gr32 0xfeedface, er6 + ;; Then use rts/l to restore them and return. + rts/l (er4-er6) + +rtsl4_func: ; Save and restore R0 - R3 + push.l er0 + push.l er1 + push.l er2 + push.l er3 + ;; Now modify them, and verify the modification. + mov #0xdadacafe, er0 + mov #0xfeedbeef, er1 + mov #0xdeadface, er2 + mov #0xf00dd00d, er3 + test_h_gr32 0xdadacafe, er0 + test_h_gr32 0xfeedbeef, er1 + test_h_gr32 0xdeadface, er2 + test_h_gr32 0xf00dd00d, er3 + ;; Then use rts/l to restore them and return. + rts/l (er0-er3) +.endif ; h8sx diff --git a/sim/testsuite/sim/h8300/stc.s b/sim/testsuite/sim/h8300/stc.s new file mode 100644 index 0000000..232bd5a --- /dev/null +++ b/sim/testsuite/sim/h8300/stc.s @@ -0,0 +1,401 @@ +# Hitachi H8 testcase 'stc' +# mach(): all +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + .data +byte_dest1: + .byte 0 + .byte 0 +byte_dest2: + .byte 0 + .byte 0 +byte_dest3: + .byte 0 + .byte 0 +byte_dest4: + .byte 0 + .byte 0 +byte_dest5: + .byte 0 + .byte 0 +byte_dest6: + .byte 0 + .byte 0 +byte_dest7: + .byte 0 + .byte 0 +byte_dest8: + .byte 0 + .byte 0 +byte_dest9: + .byte 0 + .byte 0 +byte_dest10: + .byte 0 + .byte 0 +byte_dest11: + .byte 0 + .byte 0 +byte_dest12: + .byte 0 + .byte 0 + + start + +stc_ccr_reg8: + set_grs_a5a5 + set_ccr_zero + + ldc #0xff, ccr ; test value + stc ccr, r0h ; copy test value to r0h + + test_h_gr16 0xffa5 r0 ; ff in r0h, a5 in r0l +.if (sim_cpu) ; h/s/sx + test_h_gr32 0xa5a5ffa5 er0 ; ff in r0h, a5 everywhere else +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8300s || sim_cpu == h8sx) ; Earlier versions, no exr +stc_exr_reg8: + set_grs_a5a5 + set_ccr_zero + + ldc #0x87, exr ; set exr to 0x87 + stc exr, r0l ; retrieve and check exr value + cmp.b #0x87, r0l + beq .L21 + fail +.L21: + test_h_gr32 0xa5a5a587 er0 ; Register 0 modified by test procedure. + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +stc_ccr_abs16: + set_grs_a5a5 + set_ccr_zero + + ldc #0xff, ccr + stc ccr, @byte_dest1:16 ; abs16 dest + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +stc_exr_abs16: + set_grs_a5a5 + set_ccr_zero + + ldc #0x87, exr + stc exr, @byte_dest2:16 ; abs16 dest + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +stc_ccr_abs32: + set_grs_a5a5 + set_ccr_zero + + ldc #0xff, ccr + stc ccr, @byte_dest3:32 ; abs32 dest + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +stc_exr_abs32: + set_grs_a5a5 + set_ccr_zero + + ldc #0x87, exr + stc exr, @byte_dest4:32 ; abs32 dest + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +stc_ccr_disp16: + set_grs_a5a5 + set_ccr_zero + + mov #byte_dest5-1, er1 + ldc #0xff, ccr + stc ccr, @(1:16,er1) ; disp16 dest (5) + + test_h_gr32 byte_dest5-1, er1 ; er1 still contains address + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +stc_exr_disp16: + set_grs_a5a5 + set_ccr_zero + + mov #byte_dest6+1, er1 + ldc #0x87, exr + stc exr, @(-1:16,er1) ; disp16 dest (6) + + test_h_gr32 byte_dest6+1, er1 ; er1 still contains address + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +stc_ccr_disp32: + set_grs_a5a5 + set_ccr_zero + + mov #byte_dest7-1, er1 + ldc #0xff, ccr + stc ccr, @(1:32,er1) ; disp32 dest (7) + + test_h_gr32 byte_dest7-1, er1 ; er1 still contains address + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +stc_exr_disp32: + set_grs_a5a5 + set_ccr_zero + + mov #byte_dest8+1, er1 + ldc #0x87, exr + stc exr, @(-1:32,er1) ; disp16 dest (8) + + test_h_gr32 byte_dest8+1, er1 ; er1 still contains address + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +stc_ccr_predecr: + set_grs_a5a5 + set_ccr_zero + + mov #byte_dest9+2, er1 + ldc #0xff, ccr + stc ccr, @-er1 ; predecr dest (9) + + test_h_gr32 byte_dest9 er1 ; er1 still contains address + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +stc_exr_predecr: + set_grs_a5a5 + set_ccr_zero + + mov #byte_dest10+2, er1 + ldc #0x87, exr + stc exr, @-er1 ; predecr dest (10) + + test_h_gr32 byte_dest10, er1 ; er1 still contains address + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +stc_ccr_ind: + set_grs_a5a5 + set_ccr_zero + + mov #byte_dest11, er1 + ldc #0xff, ccr + stc ccr, @er1 ; postinc dest (11) + + test_h_gr32 byte_dest11, er1 ; er1 still contains address + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +stc_exr_ind: + set_grs_a5a5 + set_ccr_zero + + mov #byte_dest12, er1 + ldc #0x87, exr + stc exr, @er1, exr ; postinc dest (12) + + test_h_gr32 byte_dest12, er1 ; er1 still contains address + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.endif + +.if (sim_cpu == h8sx) ; New vbr and sbr registers for h8sx +stc_sbr_reg: + set_grs_a5a5 + set_ccr_zero + + mov #0xaaaaaaaa, er0 + ldc er0, sbr ; set sbr to 0xaaaaaaaa + stc sbr, er1 ; retreive and check sbr value + + test_h_gr32 0xaaaaaaaa er1 + test_h_gr32 0xaaaaaaaa er0 ; Register 0 modified by test procedure. + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +stc_vbr_reg: + set_grs_a5a5 + set_ccr_zero + + mov #0xaaaaaaaa, er0 + ldc er0, vbr ; set sbr to 0xaaaaaaaa + stc vbr, er1 ; retreive and check sbr value + + test_h_gr32 0xaaaaaaaa er1 + test_h_gr32 0xaaaaaaaa er0 ; Register 0 modified by test procedure. + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +check_results: + ;; Now check results + mov @byte_dest1, r0h + cmp.b #0xff, r0h + beq .L1 + fail + +.L1: mov @byte_dest2, r0h + cmp.b #0x87, r0h + beq .L2 + fail + +.L2: mov @byte_dest3, r0h + cmp.b #0xff, r0h + beq .L3 + fail + +.L3: mov @byte_dest4, r0h + cmp.b #0x87, r0h + beq .L4 + fail + +.L4: mov @byte_dest5, r0h + cmp.b #0xff, r0h + beq .L5 + fail + +.L5: mov @byte_dest6, r0h + cmp.b #0x87, r0h + beq .L6 + fail + +.L6: mov @byte_dest7, r0h + cmp.b #0xff, r0h + beq .L7 + fail + +.L7: mov @byte_dest8, r0h + cmp.b #0x87, r0h + beq .L8 + fail + +.L8: mov @byte_dest9, r0h + cmp.b #0xff, r0h + beq .L9 + fail + +.L9: mov @byte_dest10, r0h + cmp.b #0x87, r0h + beq .L10 + fail + +.L10: mov @byte_dest11, r0h + cmp.b #0xff, r0h + beq .L11 + fail + +.L11: mov @byte_dest12, r0h + cmp.b #0x87, r0h + beq .L12 + fail + +.L12: +.endif + pass + + exit 0 diff --git a/sim/testsuite/sim/h8300/subb.s b/sim/testsuite/sim/h8300/subb.s new file mode 100644 index 0000000..0183294 --- /dev/null +++ b/sim/testsuite/sim/h8300/subb.s @@ -0,0 +1,289 @@ +# Hitachi H8 testcase 'sub.b' +# mach(): all +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + # Instructions tested: + # sub.b #xx:8, rd ; + # sub.b #xx:8, @erd ; 7 d rd ???? a ???? xxxxxxxx + # sub.b #xx:8, @erd+ ; 0 1 7 4 6 c rd 1??? a ???? xxxxxxxx + # sub.b #xx:8, @erd- ; 0 1 7 6 6 c rd 1??? a ???? xxxxxxxx + # sub.b rs, rd ; 1 8 rs rd + # sub.b reg8, @erd ; 7 d rd ???? 1 8 rs ???? + # sub.b reg8, @erd+ ; 0 1 7 9 8 rd 3 rs + # sub.b reg8, @erd- ; 0 1 7 9 a rd 3 rs + # + + # Coming soon: + # sub.b #xx:8, @+erd ; 0 1 7 5 6 c rd 1??? a ???? xxxxxxxx + # sub.b #xx:8, @-erd ; 0 1 7 7 6 c rd 1??? a ???? xxxxxxxx + # sub.b reg8, @+erd ; 0 1 7 9 9 rd 3 rs + # sub.b reg8, @-erd ; 0 1 7 9 b rd 3 rs + # ... + +.data +pre_byte: .byte 0 +byte_dest: .byte 0xa5 +post_byte: .byte 0 + + start + +.if (0) ; Guess what? Sub.b immediate reg8 is illegal! +sub_b_imm8_reg: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; sub.b #xx:8,Rd + sub.b #5, r0l ; Immediate 8-bit operand + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0xa5a0 r0 ; sub result: a5 - 5 +.if (sim_cpu) ; non-zero means h8300h, s, or sx + test_h_gr32 0xa5a5a5a0 er0 ; sub result: a5 - 5 +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif + +.if (sim_cpu == h8sx) +sub_b_imm8_rdind: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; sub.b #xx:8,@eRd + mov #byte_dest, er0 + sub.b #5:8, @er0 ; Immediate 8-bit src, reg indirect dst +;;; .word 0x7d00 +;;; .word 0xa105 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 byte_dest, er0 ; er0 still contains address + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the sub to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0xa0, r0l + beq .L1 + fail +.L1: + +sub_b_imm8_rdpostinc: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; sub.b #xx:8,@eRd+ + mov #byte_dest, er0 + sub.b #5:8, @er0+ ; Immediate 8-bit src, reg post-incr dest +;;; .word 0x0174 +;;; .word 0x6c08 +;;; .word 0xa105 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 post_byte, er0 ; er0 still contains address plus one + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the sub to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0x9b, r0l + beq .L2 + fail +.L2: + +sub_b_imm8_rdpostdec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; sub.b #xx:8,@eRd- + mov #byte_dest, er0 + sub.b #5:8, @er0- ; Immediate 8-bit src, reg post-decr dest +;;; .word 0x0176 +;;; .word 0x6c08 +;;; .word 0xa105 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 pre_byte, er0 ; er0 still contains address minus one + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the sub to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0x96, r0l + beq .L3 + fail +.L3: + +.endif + +sub_b_reg8_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; sub.b Rs,Rd + mov.b #5, r0h + sub.b r0h, r0l ; Register operand + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0x05a0 r0 ; sub result: a5 - 5 +.if (sim_cpu) ; non-zero means h8300h, s, or sx + test_h_gr32 0xa5a505a0 er0 ; sub result: a5 - 5 +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +sub_b_reg8_rdind: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; sub.b rs8,@eRd ; Subx to register indirect + mov #byte_dest, er0 + mov #5, r1l + sub.b r1l, @er0 ; reg8 src, reg indirect dest +;;; .word 0x7d00 +;;; .word 0x1890 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 byte_dest er0 ; er0 still contains address + test_h_gr32 0xa5a5a505 er1 ; er1 has the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the sub to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0x91, r0l + beq .L4 + fail +.L4: + +sub_b_reg8_rdpostinc: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; sub.b rs8,@eRd+ ; Subx to register indirect + mov #byte_dest, er0 + mov #5, r1l + sub.b r1l, @er0+ ; reg8 src, reg indirect dest +;;; .word 0x0179 +;;; .word 0x8039 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 post_byte er0 ; er0 still contains address plus one + test_h_gr32 0xa5a5a505 er1 ; er1 has the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the sub to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0x8c, r0l + beq .L5 + fail +.L5: + +sub_b_reg8_rdpostdec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; sub.b rs8,@eRd- ; Subx to register indirect + mov #byte_dest, er0 + mov #5, r1l + sub.b r1l, @er0- ; reg8 src, reg indirect dest +;;; .word 0x0179 +;;; .word 0xa039 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 pre_byte er0 ; er0 still contains address minus one + test_h_gr32 0xa5a5a505 er1 ; er1 has the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the sub to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0x87, r0l + beq .L6 + fail +.L6: + +.endif + + pass + + exit 0 diff --git a/sim/testsuite/sim/h8300/subl.s b/sim/testsuite/sim/h8300/subl.s new file mode 100644 index 0000000..7f62f11 --- /dev/null +++ b/sim/testsuite/sim/h8300/subl.s @@ -0,0 +1,91 @@ +# Hitachi H8 testcase 'sub.l' +# mach(): h8300h h8300s h8sx +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + start + +.if (sim_cpu == h8sx) ; +sub_l_imm3: ; 3-bit immediate mode only for h8sx + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; sub.l #xx:3,eRd ; Immediate 3-bit operand + sub.l #7:3, er0 + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr32 0xa5a5a59e er0 ; sub result: a5a5 - 7 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +sub_l_imm16: ; sub immediate 16-bit value + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; sub.l #xx:16,eRd ; Immediate 16-bit operand + sub.l #0x1111:16, er0 + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0x9494 r0 ; sub result: a5a5 - 1111 + test_h_gr32 0xa5a59494 er0 ; sub result: a5a5 - 1111 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.endif + +sub_l_imm32: + ;; sub.l immediate not available in h8300 mode. + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; sub.l #xx:32,Rd + sub.l #0x11111111, er0 ; Immediate 32-bit operand + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr32 0x94949494 er0 ; sub result: a5a5a5a5 - 11111111 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +sub.l.reg: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; add.l Rs,Rd + mov.l #0x11111111, er1 + sub.l er1, er0 ; Register operand + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr32 0x94949494 er0 ; sub result: a5a5a5a5 - 11111111 + test_h_gr32 0x11111111 er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + pass + + exit 0 diff --git a/sim/testsuite/sim/h8300/subs.s b/sim/testsuite/sim/h8300/subs.s new file mode 100644 index 0000000..1bb5eea --- /dev/null +++ b/sim/testsuite/sim/h8300/subs.s @@ -0,0 +1,74 @@ +# Hitachi H8 testcase 'subs' +# mach(): h8300h h8300s h8sx +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + # Instructions tested: + # subs #1, erd ; 1 b 0 0erd + # subs #2, erd ; 1 b 8 0erd + # subs #4, erd ; 1 b 9 0erd + # + + start +.if (sim_cpu) ; 32 bit only +subs_1: + set_grs_a5a5 + set_ccr_zero + + subs #1, er0 + + test_cc_clear ; subs should not affect any condition codes + test_h_gr32 0xa5a5a5a4 er0 ; result of subs #1 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +subs_2: + set_grs_a5a5 + set_ccr_zero + + subs #2, er0 + + test_cc_clear ; subs should not affect any condition codes + test_h_gr32 0xa5a5a5a3 er0 ; result of subs #2 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +subs_4: + set_grs_a5a5 + set_ccr_zero + + subs #4, er0 + + test_cc_clear ; subs should not affect any condition codes + test_h_gr32 0xa5a5a5a1 er0 ; result of subs #4 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + pass +.endif + exit 0 diff --git a/sim/testsuite/sim/h8300/subw.s b/sim/testsuite/sim/h8300/subw.s new file mode 100644 index 0000000..2370250 --- /dev/null +++ b/sim/testsuite/sim/h8300/subw.s @@ -0,0 +1,78 @@ +# Hitachi H8 testcase 'sub.w' +# mach(): all +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + start +.if (sim_cpu == h8sx) ; 3-bit immediate mode only for h8sx +sub_w_imm3: ; sub.w immediate not available in h8300 mode. + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; sub.w #xx:3,Rd ; Immediate 3-bit operand + sub.w #7:3, r0 + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0xa59e r0 ; sub result: a5a5 - 7 + test_h_gr32 0xa5a5a59e er0 ; sub result: a5a5 - 7 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif + +.if (sim_cpu) ; non-zero means h8300h, s, or sx +sub_w_imm16: ; sub.w immediate not available in h8300 mode. + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; sub.w #xx:16,Rd + sub.w #0x111, r0 ; Immediate 16-bit operand + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0xa494 r0 ; sub result: a5a5 - 111 + test_h_gr32 0xa5a5a494 er0 ; sub result: a5a5 - 111 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif + +sub.w.reg: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; sub.w Rs,Rd + mov.w #0x111, r1 + sub.w r1, r0 ; Register operand + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0xa494 r0 ; sub result: a5a5 - 111 + test_h_gr16 0x0111 r1 +.if (sim_cpu) ; non-zero means h8300h, s, or sx + test_h_gr32 0xa5a5a494 er0 ; sub result: a5a5 - 111 + test_h_gr32 0xa5a50111 er1 +.endif + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + pass + + exit 0 diff --git a/sim/testsuite/sim/h8300/subx.s b/sim/testsuite/sim/h8300/subx.s new file mode 100644 index 0000000..78656bc --- /dev/null +++ b/sim/testsuite/sim/h8300/subx.s @@ -0,0 +1,1010 @@ +# Hitachi H8 testcase 'subx' +# mach(): all +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + # Instructions tested: + # subx.b #xx:8, rd8 ; b rd8 xxxxxxxx + # subx.b #xx:8, @erd ; 7 d erd ???? b ???? xxxxxxxx + # subx.b #xx:8, @erd- ; 0 1 7 6 6 c erd 1??? b ???? xxxxxxxx + # subx.b rs8, rd8 ; 1 e rs8 rd8 + # subx.b rs8, @erd ; 7 d erd ???? 1 e rs8 ???? + # subx.b rs8, @erd- ; 0 1 7 6 6 c erd 1??? 1 e rs8 ???? + # subx.b @ers, rd8 ; 7 c ers ???? 1 e ???? rd8 + # subx.b @ers-, rd8 ; 0 1 7 6 6 c ers 00?? 1 e ???? rd8 + # subx.b @ers, @erd ; 0 1 7 4 6 8 ers d 0 erd 3 ???? + # subx.b @ers-, @erd- ; 0 1 7 6 6 c ers d a erd 3 ???? + # + # word ops + # long ops + +.data +byte_src: .byte 0x5 +byte_dest: .byte 0 + + .align 2 +word_src: .word 0x505 +word_dest: .word 0 + + .align 4 +long_src: .long 0x50505 +long_dest: .long 0 + + + start + +subx_b_imm8_0: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; subx.b #xx:8,Rd ; Subx with carry initially zero. + subx.b #5, r0l ; Immediate 8-bit operand + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr16 0xa5a0 r0 ; sub result: a5 - 5 +.if (sim_cpu) ; non-zero means h8300h, s, or sx + test_h_gr32 0xa5a5a5a0 er0 ; sub result: a5 - 5 +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +subx_b_imm8_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; subx.b #xx:8,Rd ; Subx with carry initially one. + set_carry_flag + subx.b #4, r0l ; Immediate 8-bit operand + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr16 0xa5a0 r0 ; sub result: a5 - (4 + 1) +.if (sim_cpu) ; non-zero means h8300h, s, or sx + test_h_gr32 0xa5a5a5a0 er0 ; sub result: a5 - (4 + 1) +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +subx_b_imm8_rdind: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; subx.b #xx:8,@eRd ; Subx to register indirect + mov #byte_dest, er0 + mov.b #0xa5, @er0 + set_ccr_zero + subx.b #5, @er0 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 byte_dest er0 ; er0 still contains subress + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the sub to memory. + cmp.b #0xa0, @byte_dest + beq .Lb1 + fail +.Lb1: + +subx_b_imm8_rdpostdec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; subx.b #xx:8,@eRd- ; Subx to register post-decrement + mov #byte_dest, er0 + mov.b #0xa5, @er0 + set_ccr_zero + subx.b #5, @er0- + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 byte_dest-1 er0 ; er0 contains subress minus one + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the sub to memory. + cmp.b #0xa0, @byte_dest + beq .Lb2 + fail +.Lb2: +.endif + +subx_b_reg8_0: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; subx.b Rs,Rd ; subx with carry initially zero + mov.b #5, r0h + set_ccr_zero + subx.b r0h, r0l ; Register operand + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr16 0x05a0 r0 ; sub result: a5 - 5 +.if (sim_cpu) ; non-zero means h8300h, s, or sx + test_h_gr32 0xa5a505a0 er0 ; sub result: a5 - 5 +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +subx_b_reg8_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; subx.b Rs,Rd ; subx with carry initially one + mov.b #4, r0h + set_ccr_zero + set_carry_flag + subx.b r0h, r0l ; Register operand + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr16 0x04a0 r0 ; sub result: a5 - (4 + 1) +.if (sim_cpu) ; non-zero means h8300h, s, or sx + test_h_gr32 0xa5a504a0 er0 ; sub result: a5 - (4 + 1) +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +subx_b_reg8_rdind: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; subx.b rs8,@eRd ; Subx to register indirect + mov #byte_dest, er0 + mov.b #0xa5, @er0 + mov.b #5, r1l + set_ccr_zero + subx.b r1l, @er0 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 byte_dest er0 ; er0 still contains subress + test_h_gr32 0xa5a5a505 er1 ; er1 has the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the sub to memory. + cmp.b #0xa0, @byte_dest + beq .Lb3 + fail +.Lb3: + +subx_b_reg8_rdpostdec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; subx.b rs8,@eRd- ; Subx to register post-decrement + mov #byte_dest, er0 + mov.b #0xa5, @er0 + mov.b #5, r1l + set_ccr_zero + subx.b r1l, @er0- + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 byte_dest-1 er0 ; er0 contains subress minus one + test_h_gr32 0xa5a5a505 er1 ; er1 contains the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the sub to memory. + cmp.b #0xa0, @byte_dest + beq .Lb4 + fail +.Lb4: + +subx_b_rsind_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; subx.b @eRs,rd8 ; Subx from reg indirect to reg + mov #byte_src, er0 + set_ccr_zero + subx.b @er0, r1l + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 byte_src er0 ; er0 still contains subress + test_h_gr32 0xa5a5a5a0 er1 ; er1 contains the sum + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +subx_b_rspostdec_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; subx.b @eRs-,rd8 ; Subx to register post-decrement + mov #byte_src, er0 + set_ccr_zero + subx.b @er0-, r1l + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 byte_src-1 er0 ; er0 contains subress minus one + test_h_gr32 0xa5a5a5a0 er1 ; er1 contains the sum + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +subx_b_rsind_rdind: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; subx.b @eRs,rd8 ; Subx from reg indirect to reg + mov #byte_src, er0 + mov #byte_dest, er1 + mov.b #0xa5, @er1 + set_ccr_zero + subx.b @er0, @er1 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 byte_src er0 ; er0 still contains src subress + test_h_gr32 byte_dest er1 ; er1 still contains dst subress + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ;; Now check the result of the sub to memory. + cmp.b #0xa0, @byte_dest + beq .Lb5 + fail +.Lb5: + +subx_b_rspostdec_rdpostdec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + mov #byte_src, er0 + mov #byte_dest, er1 + mov.b #0xa5, @er1 + set_ccr_zero + ;; subx.b @eRs-,@erd- ; Subx post-decrement to post-decrement + subx.b @er0-, @er1- + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 byte_src-1 er0 ; er0 contains src subress minus one + test_h_gr32 byte_dest-1 er1 ; er1 contains dst subress minus one + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ;; Now check the result of the sub to memory. + cmp.b #0xa0, @byte_dest + beq .Lb6 + fail +.Lb6: + +subx_w_imm16_0: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; subx.w #xx:16,Rd ; Subx with carry initially zero. + subx.w #0x505, r0 ; Immediate 16-bit operand + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr16 0xa0a0 r0 ; sub result: 0xa5a5 + 0x505 + test_h_gr32 0xa5a5a0a0 er0 ; sub result: 0xa5a5 + 0x505 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +subx_w_imm16_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; subx.w #xx:16,Rd ; Subx with carry initially one. + set_carry_flag + subx.w #0x504, r0 ; Immediate 16-bit operand + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr16 0xa0a0 r0 ; sub result: 0xa5a5 + 0x505 + 1 + test_h_gr32 0xa5a5a0a0 er0 ; sub result: 0xa5a5 + 0x505 + 1 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +subx_w_imm16_rdind: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; subx.w #xx:16,@eRd ; Subx to register indirect + mov #word_dest, er0 + mov.w #0xa5a5, @er0 + set_ccr_zero + subx.w #0x505, @er0 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 word_dest er0 ; er0 still contains subress + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the sub to memory. + cmp.w #0xa0a0, @word_dest + beq .Lw1 + fail +.Lw1: + +subx_w_imm16_rdpostdec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; subx.w #xx:16,@eRd- ; Subx to register post-decrement + mov #word_dest, er0 + mov.w #0xa5a5, @er0 + set_ccr_zero + subx.w #0x505, @er0- + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 word_dest-2 er0 ; er0 contains subress minus one + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the sub to memory. + cmp.w #0xa0a0, @word_dest + beq .Lw2 + fail +.Lw2: + +subx_w_reg16_0: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; subx.w Rs,Rd ; subx with carry initially zero + mov.w #0x505, e0 + set_ccr_zero + subx.w e0, r0 ; Register operand + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 0x0505a0a0 er0 ; sub result: + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +subx_w_reg16_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; subx.w Rs,Rd ; subx with carry initially one + mov.w #0x504, e0 + set_ccr_zero + set_carry_flag + subx.w e0, r0 ; Register operand + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 0x0504a0a0 er0 ; sub result: + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +subx_w_reg16_rdind: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; subx.w rs8,@eRd ; Subx to register indirect + mov #word_dest, er0 + mov.w #0xa5a5, @er0 + mov.w #0x505, r1 + set_ccr_zero + subx.w r1, @er0 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 word_dest er0 ; er0 still contains subress + test_h_gr32 0xa5a50505 er1 ; er1 has the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the sub to memory. + cmp.w #0xa0a0, @word_dest + beq .Lw3 + fail +.Lw3: + +subx_w_reg16_rdpostdec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; subx.w rs8,@eRd- ; Subx to register post-decrement + mov #word_dest, er0 + mov.w #0xa5a5, @er0 + mov.w #0x505, r1 + set_ccr_zero + subx.w r1, @er0- + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 word_dest-2 er0 ; er0 contains subress minus one + test_h_gr32 0xa5a50505 er1 ; er1 contains the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the sub to memory. + cmp.w #0xa0a0, @word_dest + beq .Lw4 + fail +.Lw4: + +subx_w_rsind_reg16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; subx.w @eRs,rd8 ; Subx from reg indirect to reg + mov #word_src, er0 + set_ccr_zero + subx.w @er0, r1 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 word_src er0 ; er0 still contains subress + test_h_gr32 0xa5a5a0a0 er1 ; er1 contains the sum + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +subx_w_rspostdec_reg16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; subx.w @eRs-,rd8 ; Subx to register post-decrement + mov #word_src, er0 + set_ccr_zero + subx.w @er0-, r1 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 word_src-2 er0 ; er0 contains subress minus one + test_h_gr32 0xa5a5a0a0 er1 ; er1 contains the sum + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +subx_w_rsind_rdind: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; subx.w @eRs,rd8 ; Subx from reg indirect to reg + mov #word_src, er0 + mov #word_dest, er1 + mov.w #0xa5a5, @er1 + set_ccr_zero + subx.w @er0, @er1 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 word_src er0 ; er0 still contains src subress + test_h_gr32 word_dest er1 ; er1 still contains dst subress + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ;; Now check the result of the sub to memory. + cmp.w #0xa0a0, @word_dest + beq .Lw5 + fail +.Lw5: + +subx_w_rspostdec_rdpostdec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; subx.w @eRs-,rd8 ; Subx to register post-decrement + mov #word_src, er0 + mov #word_dest, er1 + mov.w #0xa5a5, @er1 + set_ccr_zero + subx.w @er0-, @er1- + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 word_src-2 er0 ; er0 contains src subress minus one + test_h_gr32 word_dest-2 er1 ; er1 contains dst subress minus one + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ;; Now check the result of the sub to memory. + cmp.w #0xa0a0, @word_dest + beq .Lw6 + fail +.Lw6: + +subx_l_imm32_0: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; subx.l #xx:32,Rd ; Subx with carry initially zero. + subx.l #0x50505, er0 ; Immediate 32-bit operand + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 0xa5a0a0a0 er0 ; sub result: + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +subx_l_imm32_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; subx.l #xx:32,Rd ; Subx with carry initially one. + set_carry_flag + subx.l #0x50504, er0 ; Immediate 32-bit operand + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 0xa5a0a0a0 er0 ; sub result: + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +subx_l_imm32_rdind: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; subx.l #xx:32,@eRd ; Subx to register indirect + mov #long_dest, er0 + mov.l #0xa5a5a5a5, @er0 + set_ccr_zero + subx.l #0x50505, @er0 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 long_dest er0 ; er0 still contains subress + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the sub to memory. + cmp.l #0xa5a0a0a0, @long_dest + beq .Ll1 + fail +.Ll1: + +subx_l_imm32_rdpostdec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; subx.l #xx:32,@eRd- ; Subx to register post-decrement + mov #long_dest, er0 + mov.l #0xa5a5a5a5, @er0 + set_ccr_zero + subx.l #0x50505, @er0- + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 long_dest-4 er0 ; er0 contains subress minus one + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the sub to memory. + cmp.l #0xa5a0a0a0, @long_dest + beq .Ll2 + fail +.Ll2: + +subx_l_reg32_0: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; subx.l Rs,Rd ; subx with carry initially zero + mov.l #0x50505, er0 + set_ccr_zero + subx.l er0, er1 ; Register operand + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 0x50505 er0 ; sub load + test_h_gr32 0xa5a0a0a0 er1 ; sub result: + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +subx_l_reg32_1: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; subx.l Rs,Rd ; subx with carry initially one + mov.l #0x50504, er0 + set_ccr_zero + set_carry_flag + subx.l er0, er1 ; Register operand + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 0x50504 er0 ; sub result: + test_h_gr32 0xa5a0a0a0 er1 ; sub result: + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +subx_l_reg32_rdind: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; subx.l rs8,@eRd ; Subx to register indirect + mov #long_dest, er0 + mov.l er1, @er0 + mov.l #0x50505, er1 + set_ccr_zero + subx.l er1, @er0 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 long_dest er0 ; er0 still contains subress + test_h_gr32 0x50505 er1 ; er1 has the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the sub to memory. + cmp.l #0xa5a0a0a0, @long_dest + beq .Ll3 + fail +.Ll3: + +subx_l_reg32_rdpostdec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; subx.l rs8,@eRd- ; Subx to register post-decrement + mov #long_dest, er0 + mov.l er1, @er0 + mov.l #0x50505, er1 + set_ccr_zero + subx.l er1, @er0- + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 long_dest-4 er0 ; er0 contains subress minus one + test_h_gr32 0x50505 er1 ; er1 contains the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the sub to memory. + cmp.l #0xa5a0a0a0, @long_dest + beq .Ll4 + fail +.Ll4: + +subx_l_rsind_reg32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; subx.l @eRs,rd8 ; Subx from reg indirect to reg + mov #long_src, er0 + set_ccr_zero + subx.l @er0, er1 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 long_src er0 ; er0 still contains subress + test_h_gr32 0xa5a0a0a0 er1 ; er1 contains the sum + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +subx_l_rspostdec_reg32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; subx.l @eRs-,rd8 ; Subx to register post-decrement + mov #long_src, er0 + set_ccr_zero + subx.l @er0-, er1 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 long_src-4 er0 ; er0 contains subress minus one + test_h_gr32 0xa5a0a0a0 er1 ; er1 contains the sum + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +subx_l_rsind_rdind: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; subx.l @eRs,rd8 ; Subx from reg indirect to reg + mov #long_src, er0 + mov #long_dest, er1 + mov.l er2, @er1 + set_ccr_zero + subx.l @er0, @er1 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 long_src er0 ; er0 still contains src subress + test_h_gr32 long_dest er1 ; er1 still contains dst subress + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ;; Now check the result of the sub to memory. + cmp.l #0xa5a0a0a0, @long_dest + beq .Ll5 + fail +.Ll5: + +subx_l_rspostdec_rdpostdec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + ;; subx.l @eRs-,rd8 ; Subx to register post-decrement + mov #long_src, er0 + mov #long_dest, er1 + mov.l er2, @er1 + set_ccr_zero + subx.l @er0-, @er1- + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 long_src-4 er0 ; er0 contains src subress minus one + test_h_gr32 long_dest-4 er1 ; er1 contains dst subress minus one + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + ;; Now check the result of the sub to memory. + cmp.l #0xa5a0a0a0, @long_dest + beq .Ll6 + fail +.Ll6: +.endif + pass + + exit 0 diff --git a/sim/testsuite/sim/h8300/tas.s b/sim/testsuite/sim/h8300/tas.s new file mode 100644 index 0000000..b8aebd8 --- /dev/null +++ b/sim/testsuite/sim/h8300/tas.s @@ -0,0 +1,80 @@ +# Hitachi H8 testcase 'tas' +# mach(): h8300h h8300s h8sx +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + .data +byte_dst: .byte 0 + + start + +tas_ind: ; test and set instruction + set_grs_a5a5 + mov #byte_dst, er4 + set_ccr_zero + ;; tas @erd + tas @er4 ; should set zero flag + test_carry_clear + test_neg_clear + test_ovf_clear + test_zero_set + + tas @er4 ; should clear zero, set neg + test_carry_clear + test_neg_set + test_ovf_clear + test_zero_clear + + test_gr_a5a5 0 ; general regs have not been modified + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_h_gr32 byte_dst, er4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + mov.b @byte_dst, r0l ; test variable has MSB set? + test_h_gr8 0x80 r0l + +.if (sim_cpu == h8sx) ; h8sx can use any register for tas +tas_h8sx: ; test and set instruction + mov.b #0, @byte_dst + set_grs_a5a5 + mov #byte_dst, er3 + set_ccr_zero + ;; tas @erd + tas @er3 ; should set zero flag + test_carry_clear + test_neg_clear + test_ovf_clear + test_zero_set + + tas @er3 ; should clear zero, set neg + test_carry_clear + test_neg_set + test_ovf_clear + test_zero_clear + + test_gr_a5a5 0 ; general regs have not been modified + test_gr_a5a5 1 + test_gr_a5a5 2 + test_h_gr32 byte_dst, er3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + mov.b @byte_dst, r0l ; test variable has MSB set? + test_h_gr8 0x80 r0l +.endif ; h8sx + + pass + exit 0 diff --git a/sim/testsuite/sim/h8300/testutils.inc b/sim/testsuite/sim/h8300/testutils.inc new file mode 100644 index 0000000..9c2c27a --- /dev/null +++ b/sim/testsuite/sim/h8300/testutils.inc @@ -0,0 +1,351 @@ +# Support macros for the Hitachi H8 assembly test cases. + +; Set up a minimal machine state + .macro start + .equ h8300, 0 + .equ h8300h, 1 + .equ h8300s, 2 + .equ h8sx, 3 + .if (sim_cpu == h8300s) + .h8300s + .else + .if (sim_cpu == h8300h) + .h8300h + .else + .if (sim_cpu == h8sx) + .h8300sx + .endif + .endif + .endif + + .text + .align 2 + .global _start +_start: + jmp _main + + .data + .align 2 + .global pass_str + .global fail_str + .global ok_str + .global pass_loc + .global fail_loc + .global ok_loc +pass_str: + .ascii "pass\n" +fail_str: + .ascii "fail\n" +ok_str: + .ascii "ok\n" +pass_loc16: + .word pass_str +pass_loc32: + .long pass_str +fail_loc16: + .word fail_str +fail_loc32: + .long fail_str +ok_loc16: + .word ok_str +ok_loc32: + .long ok_str + .text + + .global _write_and_exit +_write_and_exit: +;ssize_t write(int fd, const void *buf, size_t count); +;Integer arguments have to be zero extended. +.if (sim_cpu) +#if __INT_MAX__ == 32767 + extu.l er0 +#endif +.endif + jsr @@0xc7 + mov #0, r0 + jmp _exit + + .global _exit +_exit: + mov.b r0l, r0h + mov.w #0xdead, r1 + mov.w #0xbeef, r2 + sleep + + .global _main +_main: + .endm + + +; Exit with an exit code + .macro exit code + mov.w #\code, r0 + jmp _exit + .endm + +; Output "pass\n" + .macro pass + mov.w #0, r0 ; fd == stdout +.if (sim_cpu == h8300) + mov.w #pass_str, r1 ; buf == "pass\n" + mov.w #5, r2 ; len == 5 +.else + mov.l #pass_str, er1 ; buf == "pass\n" + mov.l #5, er2 ; len == 5 +.endif + jmp _write_and_exit + .endm + +; Output "fail\n" + .macro fail + mov.w #0, r0 ; fd == stdout +.if (sim_cpu == h8300) + mov.w #fail_str, r1 ; buf == "fail\n" + mov.w #5, r2 ; len == 5 +.else + mov.l #fail_str, er1 ; buf == "fail\n" + mov.l #5, er2 ; len == 5 +.endif + jmp _write_and_exit + .endm + + +; Load an 8-bit immediate value into a general register +; (reg must be r0l - r7l or r0h - r7h) + .macro mvi_h_gr8 val reg + mov.b #\val, \reg + .endm + +; Load a 16-bit immediate value into a general register +; (reg must be r0 - r7) + .macro mvi_h_gr16 val reg + mov.w #\val, \reg + .endm + +; Load a 32-bit immediate value into a general register +; (reg must be er0 - er7) + .macro mvi_h_gr32 val reg + mov.l #\val, \reg + .endm + +; Test the value of an 8-bit immediate against a general register +; (reg must be r0l - r7l or r0h - r7h) + .macro test_h_gr8 val reg + cmp.b #\val, \reg + beq .Ltest_gr8\@ + fail +.Ltest_gr8\@: + .endm + +; Test the value of a 16-bit immediate against a general register +; (reg must be r0 - r7) + .macro test_h_gr16 val reg h=h l=l + .if (sim_cpu == h8300) + test_h_gr8 (\val >> 8) \reg\h + test_h_gr8 (\val & 0xff) \reg\l + .else + cmp.w #\val, \reg + beq .Ltest_gr16\@ + fail +.Ltest_gr16\@: + .endif + .endm + +; Test the value of a 32-bit immediate against a general register +; (reg must be er0 - er7) + .macro test_h_gr32 val reg + cmp.l #\val, \reg + beq .Ltest_gr32\@ + fail +.Ltest_gr32\@: + .endm + +; Set a general register to the fixed pattern 'a5a5a5a5' + .macro set_gr_a5a5 reg + .if (sim_cpu == 0) + ; h8300 + mov.w #0xa5a5, r\reg + .else + mov.l #0xa5a5a5a5, er\reg + .endif + .endm + +; Set all general registers to the fixed pattern 'a5a5a5a5' + .macro set_grs_a5a5 + .if (sim_cpu == 0) + ; h8300 + mov.w #0xa5a5, r0 + mov.w #0xa5a5, r1 + mov.w #0xa5a5, r2 + mov.w #0xa5a5, r3 + mov.w #0xa5a5, r4 + mov.w #0xa5a5, r5 + mov.w #0xa5a5, r6 + mov.w #0xa5a5, r7 + .else + mov.l #0xa5a5a5a5, er0 + mov.l #0xa5a5a5a5, er1 + mov.l #0xa5a5a5a5, er2 + mov.l #0xa5a5a5a5, er3 + mov.l #0xa5a5a5a5, er4 + mov.l #0xa5a5a5a5, er5 + mov.l #0xa5a5a5a5, er6 + mov.l #0xa5a5a5a5, er7 + .endif + .endm + +; Test that a general register contains the fixed pattern 'a5a5a5a5' + .macro test_gr_a5a5 reg + .if (sim_cpu == 0) + ; h8300 + test_h_gr16 0xa5a5 r\reg + .else + test_h_gr32 0xa5a5a5a5 er\reg + .endif + .endm + +; Test that all general regs contain the fixed pattern 'a5a5a5a5' + .macro test_grs_a5a5 + test_gr_a5a5 0 + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + .endm + +; Set condition code register to an explicit value + .macro set_ccr val + ldc #\val, ccr + .endm + +; Set all condition code flags to zero + .macro set_ccr_zero + ldc #0, ccr + .endm + +; Set carry flag true + .macro set_carry_flag + orc #1, ccr + .endm + +; Clear carry flag + .macro clear_carry_flag + andc 0xfe, ccr + .endm + +; Set zero flag true + .macro set_zero_flag + orc #4, ccr + .endm + +; Clear zero flag + .macro clear_zero_flag + andc 0xfb, ccr + .endm + +; Set neg flag true + .macro set_neg_flag + orc #8, ccr + .endm + +; Clear neg flag + .macro clear_neg_flag + andc 0xf7, ccr + .endm + +; Test that carry flag is clear + .macro test_carry_clear + bcc .Lcc\@ + fail ; carry flag not clear +.Lcc\@: + .endm + +; Test that carry flag is set + .macro test_carry_set + bcs .Lcs\@ + fail ; carry flag not clear +.Lcs\@: + .endm + +; Test that overflow flag is clear + .macro test_ovf_clear + bvc .Lvc\@ + fail ; overflow flag not clear +.Lvc\@: + .endm + +; Test that overflow flag is set + .macro test_ovf_set + bvs .Lvs\@ + fail ; overflow flag not clear +.Lvs\@: + .endm + +; Test that zero flag is clear + .macro test_zero_clear + bne .Lne\@ + fail ; zero flag not clear +.Lne\@: + .endm + +; Test that zero flag is set + .macro test_zero_set + beq .Leq\@ + fail ; zero flag not clear +.Leq\@: + .endm + +; Test that neg flag is clear + .macro test_neg_clear + bpl .Lneg\@ + fail ; negative flag not clear +.Lneg\@: + .endm + +; Test that neg flag is set + .macro test_neg_set + bmi .Lneg\@ + fail ; negative flag not clear +.Lneg\@: + .endm + +; Test ccr against an explicit value + .macro test_ccr val + .data +tccr\@: .byte 0 + .text + mov.b r0l, @tccr\@ + stc ccr, r0l + cmp.b #\val, r0l + bne .Ltcc\@ + fail +.Ltcc\@: + mov.b @tccr\@, r0l + .endm + +; Test that all (accessable) condition codes are clear + .macro test_cc_clear + test_carry_clear + test_ovf_clear + test_zero_clear + test_neg_clear + ; leaves H, I, U, and UI untested + .endm + +; Compare memory, fail if not equal (h8sx only, len > 0). + .macro memcmp src dst len + mov.l #\src, er5 + mov.l #\dst, er6 + mov.l #\len, er4 +.Lmemcmp_\@: + cmp.b @er5+, @er6+ + beq .Lmemcmp2_\@ + fail +.Lmemcmp2_\@: + dec.l #1, er4 + bne .Lmemcmp_\@ + .endm + diff --git a/sim/testsuite/sim/h8300/xorb.s b/sim/testsuite/sim/h8300/xorb.s new file mode 100644 index 0000000..337c396 --- /dev/null +++ b/sim/testsuite/sim/h8300/xorb.s @@ -0,0 +1,378 @@ +# Hitachi H8 testcase 'xor.b' +# mach(): all +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + # Instructions tested: + # xor.b #xx:8, rd ; d rd xxxxxxxx + # xor.b #xx:8, @erd ; 7 d rd ???? d ???? xxxxxxxx + # xor.b #xx:8, @erd+ ; 0 1 7 4 6 c rd 1??? d ???? xxxxxxxx + # xor.b #xx:8, @erd- ; 0 1 7 6 6 c rd 1??? d ???? xxxxxxxx + # xor.b #xx:8, @+erd ; 0 1 7 5 6 c rd 1??? d ???? xxxxxxxx + # xor.b #xx:8, @-erd ; 0 1 7 7 6 c rd 1??? d ???? xxxxxxxx + # xor.b rs, rd ; 1 5 rs rd + # xor.b reg8, @erd ; 7 d rd ???? 1 5 rs ???? + # xor.b reg8, @erd+ ; 0 1 7 9 8 rd 5 rs + # xor.b reg8, @erd- ; 0 1 7 9 a rd 5 rs + # xor.b reg8, @+erd ; 0 1 7 9 9 rd 5 rs + # xor.b reg8, @-erd ; 0 1 7 9 b rd 5 rs + # + # xorc #xx:8, ccr ; + # xorc #xx:8, exr ; + + # Coming soon: + # ... + +.data +pre_byte: .byte 0 +byte_dest: .byte 0xa5 +post_byte: .byte 0 + + start + +xor_b_imm8_reg: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; xor.b #xx:8,Rd + xor.b #0xff, r0l ; Immediate 8-bit operand + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0xa55a r0 ; xor result: a5 ^ ff +.if (sim_cpu) ; non-zero means h8300h, s, or sx + test_h_gr32 0xa5a5a55a er0 ; xor result: a5 ^ ff +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +xor_b_imm8_rdind: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; xor.b #xx:8,@eRd + mov #byte_dest, er0 + xor.b #0xff:8, @er0 ; Immediate 8-bit src, reg indirect dst +;;; .word 0x7d00 +;;; .word 0xd0ff + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 byte_dest, er0 ; er0 still contains address + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the xor to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0x5a, r0l + beq .L1 + fail +.L1: + +xor_b_imm8_postinc: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; xor.b #xx:8,@eRd+ + mov #byte_dest, er0 + xor.b #0xff:8, @er0+ ; Immediate 8-bit src, reg indirect dst +;;; .word 0x0174 +;;; .word 0x6c08 +;;; .word 0xd0ff + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 post_byte, er0 ; er0 contains address plus one + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the xor to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0xa5, r0l + beq .L2 + fail +.L2: + +xor_b_imm8_rdpostdec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; xor.b #xx:8,@eRd- + mov #byte_dest, er0 + xor.b #0xff:8, @er0- ; Immediate 8-bit src, reg indirect dst +;;; .word 0x0176 +;;; .word 0x6c08 +;;; .word 0xd0ff + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 pre_byte, er0 ; er0 contains address minus one + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the xor to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0x5a, r0l + beq .L3 + fail +.L3: + + +.endif + +xor_b_reg8_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; xor.b Rs,Rd + mov.b #0xff, r0h + xor.b r0h, r0l ; Register operand + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0xff5a r0 ; xor result: a5 ^ ff +.if (sim_cpu) ; non-zero means h8300h, s, or sx + test_h_gr32 0xa5a5ff5a er0 ; xor result: a5 ^ ff +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +xor_b_reg8_rdind: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; xor.b rs8,@eRd ; xor reg8 to register indirect + mov #byte_dest, er0 + mov #0xff, r1l + xor.b r1l, @er0 ; reg8 src, reg indirect dest +;;; .word 0x7d00 +;;; .word 0x1590 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 byte_dest er0 ; er0 still contains address + test_h_gr32 0xa5a5a5ff er1 ; er1 has the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the or to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0xa5, r0l + beq .L4 + fail +.L4: + +xor_b_reg8_rdpostinc: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; xor.b rs8,@eRd+ ; xor reg8 to register post-increment + mov #byte_dest, er0 + mov #0xff, r1l + xor.b r1l, @er0+ ; reg8 src, reg post-increment dest +;;; .word 0x0179 +;;; .word 0x8059 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 post_byte er0 ; er0 contains address plus one + test_h_gr32 0xa5a5a5ff er1 ; er1 has the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the or to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0x5a, r0l + beq .L5 + fail +.L5: + +xor_b_reg8_rdpostdec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; xor.b rs8,@eRd- ; xor reg8 to register post-decrement + mov #byte_dest, er0 + mov #0xff, r1l + xor.b r1l, @er0- ; reg8 src, reg indirect dest +;;; .word 0x0179 +;;; .word 0xa059 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 pre_byte er0 ; er0 contains address minus one + test_h_gr32 0xa5a5a5ff er1 ; er1 has the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the or to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0xa5, r0l + beq .L6 + fail +.L6: + +.endif ; h8sx + +xorc_imm8_ccr: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; xorc #xx:8,ccr + + test_neg_clear + xorc #0x8, ccr ; Immediate 8-bit operand (neg flag) + test_neg_set + xorc #0x8, ccr + test_neg_clear + + test_zero_clear + xorc #0x4, ccr ; Immediate 8-bit operand (zero flag) + test_zero_set + xorc #0x4, ccr + test_zero_clear + + test_ovf_clear + xorc #0x2, ccr ; Immediate 8-bit operand (overflow flag) + test_ovf_set + xorc #0x2, ccr + test_ovf_clear + + test_carry_clear + xorc #0x1, ccr ; Immediate 8-bit operand (carry flag) + test_carry_set + xorc #0x1, ccr + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8300s || sim_cpu == h8sx) ; Earlier versions, no exr +xorc_imm8_exr: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ldc #0, exr + stc exr, r0l + test_h_gr8 0, r0l + + set_ccr_zero + ;; xorc #xx:8,exr + + xorc #0x80, exr + test_cc_clear + stc exr, r0l + test_h_gr8 0x80, r0l + xorc #0x80, exr + stc exr, r0l + test_h_gr8 0, r0l + + xorc #0x4, exr + stc exr, r0l + test_h_gr8 4, r0l + xorc #0x4, exr + stc exr, r0l + test_h_gr8 0, r0l + + xorc #0x2, exr ; Immediate 8-bit operand (overflow flag) + stc exr, r0l + test_h_gr8 2, r0l + xorc #0x2, exr + stc exr, r0l + test_h_gr8 0, r0l + + xorc #0x1, exr ; Immediate 8-bit operand (carry flag) + stc exr, r0l + test_h_gr8 1, r0l + xorc #0x1, exr + stc exr, r0l + test_h_gr8 0, r0l + + test_h_gr32 0xa5a5a500 er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif ; not h8300 or h8300h + + pass + + exit 0 diff --git a/sim/testsuite/sim/h8300/xorl.s b/sim/testsuite/sim/h8300/xorl.s new file mode 100644 index 0000000..67b2e49 --- /dev/null +++ b/sim/testsuite/sim/h8300/xorl.s @@ -0,0 +1,77 @@ +# Hitachi H8 testcase 'xor.l' +# mach(): h8300h h8300s h8sx +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + start + +.if (sim_cpu == h8sx) ; 16-bit immediate is only available on sx. +xor_l_imm16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; xor.l #xx:16,Rd + xor.l #0xffff:16, er0 ; Immediate 16-bit operand + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + + test_h_gr32 0xa5a55a5a er0 ; xor result: a5a5a5a5 | ffff + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif + +xor_l_imm32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; xor.l #xx:32,Rd + xor.l #0xffffffff, er0 ; Immediate 32-bit operand + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + + test_h_gr32 0x5a5a5a5a er0 ; xor result: a5a5a5a5 ^ ffffffff + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +xor_l_reg: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; xor.l Rs,Rd + mov.l #0xffffffff, er1 + xor.l er1, er0 ; Register operand + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + + test_h_gr32 0x5a5a5a5a er0 ; xor result: a5a5a5a5 ^ ffffffff + test_h_gr32 0xffffffff er1 ; Make sure er1 is unchanged + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + pass + + exit 0 diff --git a/sim/testsuite/sim/h8300/xorw.s b/sim/testsuite/sim/h8300/xorw.s new file mode 100644 index 0000000..3c5e5b8 --- /dev/null +++ b/sim/testsuite/sim/h8300/xorw.s @@ -0,0 +1,61 @@ +# Hitachi H8 testcase 'xor.w' +# mach(): h8300h h8300s h8sx +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + start + +.if (sim_cpu) ; non-zero means h8300h, s, or sx +xor_w_imm16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; xor.w #xx:16,Rd + xor.w #0xffff, r0 ; Immediate 16-bit operand + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0x5a5a r0 ; xor result: a5a5 ^ ffff +.if (sim_cpu) ; non-zero means h8300h, s, or sx + test_h_gr32 0xa5a55a5a er0 ; xor result: a5a5 ^ ffff +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif + +xor_w_reg: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; xor.w Rs,Rd + mov.w #0xffff, r1 + xor.w r1, r0 ; Register operand + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0x5a5a r0 ; xor result: a5a5 ^ ffff + test_h_gr16 0xffff r1 ; Make sure r1 is unchanged +.if (sim_cpu) ; non-zero means h8300h, s, or sx + test_h_gr32 0xa5a55a5a er0 ; xor result: a5a5 ^ ffff + test_h_gr32 0xa5a5ffff er1 ; Make sure er1 is unchanged +.endif + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + pass + + exit 0 diff --git a/sim/testsuite/sim/sh/ChangeLog b/sim/testsuite/sim/sh/ChangeLog new file mode 100644 index 0000000..7df64f7 --- /dev/null +++ b/sim/testsuite/sim/sh/ChangeLog @@ -0,0 +1,33 @@ +2003-08-11 Michael Snyder + + * macl.s: New file. + * macw.s: New file. + * allinsn.exp: Add new tests for mac.w and mac.l. + +2003-07-25 Michael Snyder + + * pshai.s, pshar.s, pshli.s, pshlr.s: New files. + * allinsn.exp: Add psha, pshl tests. + * pdec.s, pinc.s, padd.s, paddc.s: New files. + * allinsn.exp: Add pdec, pinc, padd, paddc tests. + * pand.s, pdmsb.s: New files. + * allinsn.exp: Add pand, pdmsb tests. + +2003-07-23 Michael Snyder + + * pmuls.s: New file. + +2003-07-08 Michael Snyder + + * allinsn.exp, testutils.inc, add.s, fabs.s, fadd.s, fcmpeq.s, + fcmpgt.s, fcnvds.s, fcnvsd.s, fdiv.s, fldi0.s, fldi1.s, flds.s, + float.s, fmac.s, fmov.s, fmul.s, fneg.s, frchg.s, fschg.s, + fsqrt.s, fsub.s, ftrc.s, shll16.s, shll2.s, shll8.s, shll.s, + shlr16.s, shlr2.s, shlr8.s, shlr.s, swap.s: New files. + +Local Variables: +mode: change-log +left-margin: 8 +fill-column: 74 +version-control: never +End: diff --git a/sim/testsuite/sim/sh/add.s b/sim/testsuite/sim/sh/add.s new file mode 100644 index 0000000..9519251 --- /dev/null +++ b/sim/testsuite/sim/sh/add.s @@ -0,0 +1,86 @@ +# sh testcase for add +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + .align 2 +_x: .long 1 +_y: .long 1 + + start + +add_reg_reg_direct: + set_grs_a5a5 + mov.l i, r1 + mov.l j, r2 + add r1, r2 + test_gr0_a5a5 + assertreg 2 r1 + assertreg 4 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + +add_reg_reg_indirect: + set_grs_a5a5 + mov.l x, r1 + mov.l y, r2 + mov.l @r1, r1 + mov.l @r2, r2 + add r1, r2 + test_gr0_a5a5 + assertreg 1 r1 + assertreg 2 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + +add_imm_reg: + set_grs_a5a5 + add #0x16, r1 + test_gr0_a5a5 + assertreg 0xa5a5a5bb r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + + pass + + exit 0 + + .align 2 +x: .long _x +y: .long _y +i: .long 2 +j: .long 2 + diff --git a/sim/testsuite/sim/sh/allinsn.exp b/sim/testsuite/sim/sh/allinsn.exp new file mode 100644 index 0000000..7192e81 --- /dev/null +++ b/sim/testsuite/sim/sh/allinsn.exp @@ -0,0 +1,49 @@ +# sh tests + +set all "sh shdsp" + +if [istarget sh-*elf] { + run_sim_test add.s $all + run_sim_test fabs.s sh + run_sim_test fadd.s sh + run_sim_test fcmpeq.s sh + run_sim_test fcmpgt.s sh + run_sim_test fcnvds.s sh + run_sim_test fcnvsd.s sh + run_sim_test fdiv.s sh + run_sim_test fldi0.s sh + run_sim_test fldi1.s sh + run_sim_test flds.s sh + run_sim_test float.s sh + run_sim_test fmac.s sh + run_sim_test fmov.s sh + run_sim_test fmul.s sh + run_sim_test fneg.s sh + run_sim_test frchg.s sh + run_sim_test fschg.s sh + run_sim_test fsqrt.s sh + run_sim_test fsub.s sh + run_sim_test ftrc.s sh + run_sim_test macl.s sh + run_sim_test macw.s sh + run_sim_test paddc.s shdsp + run_sim_test padd.s shdsp + run_sim_test pand.s shdsp + run_sim_test pdec.s shdsp + run_sim_test pdmsb.s shdsp + run_sim_test pinc.s shdsp + run_sim_test pmuls.s shdsp + run_sim_test pshai.s shdsp + run_sim_test pshar.s shdsp + run_sim_test pshli.s shdsp + run_sim_test pshlr.s shdsp + run_sim_test shll.s $all + run_sim_test shll2.s $all + run_sim_test shll8.s $all + run_sim_test shll16.s $all + run_sim_test shlr.s $all + run_sim_test shlr2.s $all + run_sim_test shlr8.s $all + run_sim_test shlr16.s $all + run_sim_test swap.s $all +} diff --git a/sim/testsuite/sim/sh/fabs.s b/sim/testsuite/sim/sh/fabs.s new file mode 100644 index 0000000..1fb354e --- /dev/null +++ b/sim/testsuite/sim/sh/fabs.s @@ -0,0 +1,115 @@ +# sh testcase for fabs +# mach: sh +# as(sh): -defsym sim_cpu=0 + + .include "testutils.inc" + + start +fabs_freg_b0: + single_prec + bank0 + set_grs_a5a5 + set_fprs_a5a5 + # fabs(0.0) = 0.0. + fldi0 fr0 + fabs fr0 + fldi0 fr1 + fcmp/eq fr0, fr1 + bt .L1 + fail +.L1: + # fabs(1.0) = 1.0. + fldi1 fr0 + fabs fr0 + fldi1 fr1 + fcmp/eq fr0, fr1 + bt .L2 + fail +.L2: + # fabs(-1.0) = 1.0. + fldi1 fr0 + fneg fr0 + fabs fr0 + fldi1 fr1 + fcmp/eq fr0, fr1 + bt .L3 + fail +.L3: + test_grs_a5a5 + test_fpr_a5a5 fr2 + test_fpr_a5a5 fr3 + test_fpr_a5a5 fr4 + test_fpr_a5a5 fr5 + test_fpr_a5a5 fr6 + test_fpr_a5a5 fr7 + test_fpr_a5a5 fr8 + test_fpr_a5a5 fr9 + test_fpr_a5a5 fr10 + test_fpr_a5a5 fr11 + test_fpr_a5a5 fr12 + test_fpr_a5a5 fr13 + test_fpr_a5a5 fr14 + test_fpr_a5a5 fr15 + +fabs_dreg_b0: + # double precision tests. + set_grs_a5a5 + set_fprs_a5a5 + double_prec + # fabs(0.0) = 0.0. + fldi0 fr0 + flds fr0, fpul + fcnvsd fpul, dr0 + fabs dr0 + assert_dpreg_i 0 dr0 + + # fabs(1.0) = 1.0. + fldi1 fr0 + flds fr0, fpul + fcnvsd fpul, dr0 + fabs dr0 + assert_dpreg_i 1 dr0 + + # check. + fldi1 fr2 + flds fr2, fpul + fcnvsd fpul, dr2 + fcmp/eq dr0, dr2 + bt .L4 + fail + +.L4: + # fabs(-1.0) = 1.0. + fldi1 fr0 + fneg fr0 + flds fr0, fpul + fcnvsd fpul, dr0 + fabs dr0 + assert_dpreg_i 1 dr0 + + # check. + fldi1 fr2 + flds fr2, fpul + fcnvsd fpul, dr2 + fcmp/eq dr0, dr2 + bt .L5 + fail +.L5: + test_grs_a5a5 + assert_dpreg_i 1 dr0 + assert_dpreg_i 1 dr2 + test_fpr_a5a5 fr4 + test_fpr_a5a5 fr5 + test_fpr_a5a5 fr6 + test_fpr_a5a5 fr7 + test_fpr_a5a5 fr8 + test_fpr_a5a5 fr9 + test_fpr_a5a5 fr10 + test_fpr_a5a5 fr11 + test_fpr_a5a5 fr12 + test_fpr_a5a5 fr13 + test_fpr_a5a5 fr14 + test_fpr_a5a5 fr15 + + pass + exit 0 diff --git a/sim/testsuite/sim/sh/fadd.s b/sim/testsuite/sim/sh/fadd.s new file mode 100644 index 0000000..72431f0 --- /dev/null +++ b/sim/testsuite/sim/sh/fadd.s @@ -0,0 +1,75 @@ +# sh testcase for fadd +# mach: sh +# as(sh): -defsym sim_cpu=0 + + .include "testutils.inc" + + start +fadd_freg_freg_b0: + set_grs_a5a5 + set_fprs_a5a5 + bank0 + + fldi1 fr0 + fldi1 fr1 + fadd fr0, fr1 + assert_fpreg_i 2 fr1 + + fldi0 fr0 + fldi1 fr1 + fadd fr0, fr1 + assert_fpreg_i 1 fr1 + + fldi1 fr0 + fldi0 fr1 + fadd fr0, fr1 + assert_fpreg_i 1 fr1 + test_grs_a5a5 + assert_fpreg_i 1 fr0 + test_fpr_a5a5 fr2 + test_fpr_a5a5 fr3 + test_fpr_a5a5 fr4 + test_fpr_a5a5 fr5 + test_fpr_a5a5 fr6 + test_fpr_a5a5 fr7 + test_fpr_a5a5 fr8 + test_fpr_a5a5 fr9 + test_fpr_a5a5 fr10 + test_fpr_a5a5 fr11 + test_fpr_a5a5 fr12 + test_fpr_a5a5 fr13 + test_fpr_a5a5 fr14 + test_fpr_a5a5 fr15 + +fadd_dreg_dreg_b0: + set_grs_a5a5 + set_fprs_a5a5 + double_prec + fldi1 fr0 + fldi1 fr2 + flds fr0, fpul + fcnvsd fpul, dr0 + flds fr2, fpul + fcnvsd fpul, dr2 + fadd dr0, dr2 + fcnvds dr2, fpul + fsts fpul, fr0 + + test_grs_a5a5 + assert_fpreg_i 2, fr0 + assert_dpreg_i 2, dr2 + test_fpr_a5a5 fr4 + test_fpr_a5a5 fr5 + test_fpr_a5a5 fr6 + test_fpr_a5a5 fr7 + test_fpr_a5a5 fr8 + test_fpr_a5a5 fr9 + test_fpr_a5a5 fr10 + test_fpr_a5a5 fr11 + test_fpr_a5a5 fr12 + test_fpr_a5a5 fr13 + test_fpr_a5a5 fr14 + test_fpr_a5a5 fr15 + + pass + exit 0 diff --git a/sim/testsuite/sim/sh/fcmpeq.s b/sim/testsuite/sim/sh/fcmpeq.s new file mode 100644 index 0000000..9c0ef57 --- /dev/null +++ b/sim/testsuite/sim/sh/fcmpeq.s @@ -0,0 +1,119 @@ +# sh testcase for fcmpeq +# mach: sh +# as(sh): -defsym sim_cpu=0 + + .include "testutils.inc" + + start +fcmpeq_single: + set_grs_a5a5 + set_fprs_a5a5 + # 1.0 == 1.0. + fldi1 fr0 + fldi1 fr1 + fcmp/eq fr0, fr1 + bt .L0 + fail +.L0: + # 0.0 != 1.0. + fldi0 fr0 + fldi1 fr1 + fcmp/eq fr0, fr1 + bf .L1 + fail +.L1: + # 1.0 != 0.0. + fldi1 fr0 + fldi0 fr1 + fcmp/eq fr0, fr1 + bf .L2 + fail +.L2: + # 2.0 != 1.0 + fldi1 fr0 + fadd fr0, fr0 + fldi1 fr1 + fcmp/eq fr0, fr1 + bf .L3 + fail +.L3: + test_grs_a5a5 + assert_fpreg_i 2, fr0 + assert_fpreg_i 1, fr1 + test_fpr_a5a5 fr2 + test_fpr_a5a5 fr3 + test_fpr_a5a5 fr4 + test_fpr_a5a5 fr5 + test_fpr_a5a5 fr6 + test_fpr_a5a5 fr7 + test_fpr_a5a5 fr8 + test_fpr_a5a5 fr9 + test_fpr_a5a5 fr10 + test_fpr_a5a5 fr11 + test_fpr_a5a5 fr12 + test_fpr_a5a5 fr13 + test_fpr_a5a5 fr14 + test_fpr_a5a5 fr15 + +fcmpeq_double: + # 1.0 == 1.0 + set_grs_a5a5 + set_fprs_a5a5 + double_prec + fldi1 fr0 + fldi1 fr2 + _s2d fr0, dr0 + _s2d fr2, dr2 + fcmp/eq dr0, dr2 + bt .L10 + fail +.L10: + # 0.0 != 1.0 + fldi0 fr0 + fldi1 fr2 + _s2d fr0, dr0 + _s2d fr2, dr2 + fcmp/eq dr0, dr2 + bf .L11 + fail +.L11: + # 1.0 != 0.0 + fldi1 fr0 + fldi0 fr2 + _s2d fr0, dr0 + _s2d fr2, dr2 + fcmp/eq dr0, dr2 + bf .L12 + fail +.L12: + # 2.0 != 1.0 + fldi1 fr0 + single_prec + fadd fr0, fr0 + double_prec + fldi1 fr2 + _s2d fr0, dr0 + _s2d fr2, dr2 + fcmp/eq dr0, dr2 + bf .L13 + fail +.L13: + test_grs_a5a5 + assert_dpreg_i 2, dr0 + assert_dpreg_i 1, dr2 + test_fpr_a5a5 fr4 + test_fpr_a5a5 fr5 + test_fpr_a5a5 fr6 + test_fpr_a5a5 fr7 + test_fpr_a5a5 fr8 + test_fpr_a5a5 fr9 + test_fpr_a5a5 fr10 + test_fpr_a5a5 fr11 + test_fpr_a5a5 fr12 + test_fpr_a5a5 fr13 + test_fpr_a5a5 fr14 + test_fpr_a5a5 fr15 + + pass + exit 0 + diff --git a/sim/testsuite/sim/sh/fcmpgt.s b/sim/testsuite/sim/sh/fcmpgt.s new file mode 100644 index 0000000..c6945ba --- /dev/null +++ b/sim/testsuite/sim/sh/fcmpgt.s @@ -0,0 +1,119 @@ +# sh testcase for fcmpgt +# mach: sh +# as(sh): -defsym sim_cpu=0 + + .include "testutils.inc" + + start +fcmpgt_single: + set_grs_a5a5 + set_fprs_a5a5 + # 1.0 !> 1.0. + fldi1 fr0 + fldi1 fr1 + fcmp/gt fr0, fr1 + bf .L0 + fail +.L0: + # 0.0 !> 1.0. + fldi0 fr0 + fldi1 fr1 + fcmp/gt fr0, fr1 + bt .L1 + fail +.L1: + # 1.0 > 0.0. + fldi1 fr0 + fldi0 fr1 + fcmp/gt fr0, fr1 + bf .L2 + fail +.L2: + # 2.0 > 1.0 + fldi1 fr0 + fadd fr0, fr0 + fldi1 fr1 + fcmp/gt fr0, fr1 + bf .L3 + fail +.L3: + test_grs_a5a5 + assert_fpreg_i 2, fr0 + assert_fpreg_i 1, fr1 + test_fpr_a5a5 fr2 + test_fpr_a5a5 fr3 + test_fpr_a5a5 fr4 + test_fpr_a5a5 fr5 + test_fpr_a5a5 fr6 + test_fpr_a5a5 fr7 + test_fpr_a5a5 fr8 + test_fpr_a5a5 fr9 + test_fpr_a5a5 fr10 + test_fpr_a5a5 fr11 + test_fpr_a5a5 fr12 + test_fpr_a5a5 fr13 + test_fpr_a5a5 fr14 + test_fpr_a5a5 fr15 + +fcmpgt_double: + # double precision tests. + set_grs_a5a5 + set_fprs_a5a5 + double_prec + # 1.0 !> 1.0. + fldi1 fr0 + fldi1 fr2 + _s2d fr0, dr0 + _s2d fr2, dr2 + fcmp/gt dr0, dr2 + bf .L10 + fail +.L10: + # 0.0 !> 1.0. + fldi0 fr0 + fldi1 fr2 + _s2d fr0, dr0 + _s2d fr2, dr2 + fcmp/gt dr0, dr2 + bt .L11 + fail +.L11: + # 1.0 > 0.0. + fldi1 fr0 + fldi0 fr2 + _s2d fr0, dr0 + _s2d fr2, dr2 + fcmp/gt dr0, dr2 + bf .L12 + fail +.L12: + # 2.0 > 1.0. + fldi1 fr0 + single_prec + fadd fr0, fr0 + double_prec + fldi1 fr2 + _s2d fr0, dr0 + _s2d fr2, dr2 + fcmp/gt dr0, dr2 + bf .L13 + fail +.L13: + test_grs_a5a5 + assert_dpreg_i 2, dr0 + assert_dpreg_i 1, dr2 + test_fpr_a5a5 fr4 + test_fpr_a5a5 fr5 + test_fpr_a5a5 fr6 + test_fpr_a5a5 fr7 + test_fpr_a5a5 fr8 + test_fpr_a5a5 fr9 + test_fpr_a5a5 fr10 + test_fpr_a5a5 fr11 + test_fpr_a5a5 fr12 + test_fpr_a5a5 fr13 + test_fpr_a5a5 fr14 + test_fpr_a5a5 fr15 + + pass + exit 0 diff --git a/sim/testsuite/sim/sh/fcnvds.s b/sim/testsuite/sim/sh/fcnvds.s new file mode 100644 index 0000000..cffcb49 --- /dev/null +++ b/sim/testsuite/sim/sh/fcnvds.s @@ -0,0 +1,56 @@ +# sh testcase for fcnvds +# mach: sh +# as(sh): -defsym sim_cpu=0 + + .include "testutils.inc" + + start + double_prec + sz_64 + set_grs_a5a5 + set_fprs_a5a5 + mov.l ax, r0 + fmov @r0, dr0 + fcnvds dr0, fpul + fsts fpul, fr2 + + assert_dpreg_i 5, dr0 + single_prec + assert_fpreg_i 5, fr2 + test_fpr_a5a5 fr3 + test_fpr_a5a5 fr4 + test_fpr_a5a5 fr5 + test_fpr_a5a5 fr6 + test_fpr_a5a5 fr7 + test_fpr_a5a5 fr8 + test_fpr_a5a5 fr9 + test_fpr_a5a5 fr10 + test_fpr_a5a5 fr11 + test_fpr_a5a5 fr12 + test_fpr_a5a5 fr13 + test_fpr_a5a5 fr14 + test_fpr_a5a5 fr15 + + assertreg0 x + test_gr_a5a5 r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + + pass + exit 0 + + .align 2 +x: .double 5.0 +ax: .long x + diff --git a/sim/testsuite/sim/sh/fcnvsd.s b/sim/testsuite/sim/sh/fcnvsd.s new file mode 100644 index 0000000..6592540 --- /dev/null +++ b/sim/testsuite/sim/sh/fcnvsd.s @@ -0,0 +1,40 @@ +# sh testcase for fcnvsd +# mach: sh +# as(sh): -defsym sim_cpu=0 + + .include "testutils.inc" + + start + set_grs_a5a5 + set_fprs_a5a5 + double_prec + fldi1 fr0 + flds fr0, fpul + fcnvsd fpul, dr2 + assert_dpreg_i 1, dr2 + + # Convert back. + fcnvds dr2, fpul + fsts fpul, fr1 + single_prec + assert_fpreg_i 1, fr1 + fcmp/eq fr0, fr1 + bt .L0 + fail +.L0: + test_grs_a5a5 + test_fpr_a5a5 fr4 + test_fpr_a5a5 fr5 + test_fpr_a5a5 fr6 + test_fpr_a5a5 fr7 + test_fpr_a5a5 fr8 + test_fpr_a5a5 fr9 + test_fpr_a5a5 fr10 + test_fpr_a5a5 fr11 + test_fpr_a5a5 fr12 + test_fpr_a5a5 fr13 + test_fpr_a5a5 fr14 + test_fpr_a5a5 fr15 + pass + exit 0 + diff --git a/sim/testsuite/sim/sh/fdiv.s b/sim/testsuite/sim/sh/fdiv.s new file mode 100644 index 0000000..629e774 --- /dev/null +++ b/sim/testsuite/sim/sh/fdiv.s @@ -0,0 +1,91 @@ +# sh testcase for fdiv +# mach: sh +# as(sh): -defsym sim_cpu=0 + + .include "testutils.inc" + + start +fdiv_single: + # Single test + set_grs_a5a5 + set_fprs_a5a5 + single_prec + # 1.0 / 0.0 should be INF + # (and not crash the sim). + fldi0 fr0 + fldi1 fr1 + fdiv fr0, fr1 + assert_fpreg_x 0x7f800000, fr1 + + # 0.0 / 1.0 == 0.0. + fldi0 fr0 + fldi1 fr1 + fdiv fr1, fr0 + assert_fpreg_x 0, fr0 + + # 2.0 / 1.0 == 2.0. + fldi1 fr1 + fldi1 fr2 + fadd fr2, fr2 + fdiv fr1, fr2 + assert_fpreg_i 2, fr2 + + # (1.0 / 2.0) + (1.0 / 2.0) == 1.0. + fldi1 fr1 + fldi1 fr2 + fadd fr2, fr2 + fdiv fr2, fr1 + # fr1 should contain 0.5. + fadd fr1, fr1 + assert_fpreg_i 1, fr1 + test_grs_a5a5 + assert_fpreg_i 2, fr2 + test_fpr_a5a5 fr3 + test_fpr_a5a5 fr4 + test_fpr_a5a5 fr5 + test_fpr_a5a5 fr6 + test_fpr_a5a5 fr7 + test_fpr_a5a5 fr8 + test_fpr_a5a5 fr9 + test_fpr_a5a5 fr10 + test_fpr_a5a5 fr11 + test_fpr_a5a5 fr12 + test_fpr_a5a5 fr13 + test_fpr_a5a5 fr14 + test_fpr_a5a5 fr15 + +fdiv_double: + # Double test + set_grs_a5a5 + set_fprs_a5a5 + # (1.0 / 2.0) + (1.0 / 2.0) == 1.0. + fldi1 fr1 + fldi1 fr2 + # This add must be in single precision. The rest must be in double. + fadd fr2, fr2 + double_prec + _s2d fr1, dr0 + _s2d fr2, dr2 + fdiv dr2, dr0 + # dr0 should contain 0.5. + # double it, expect 1.0. + fadd dr0, dr0 + assert_dpreg_i 1, dr0 + assert_dpreg_i 2, dr2 + test_grs_a5a5 + test_fpr_a5a5 fr4 + test_fpr_a5a5 fr5 + test_fpr_a5a5 fr6 + test_fpr_a5a5 fr7 + test_fpr_a5a5 fr8 + test_fpr_a5a5 fr9 + test_fpr_a5a5 fr10 + test_fpr_a5a5 fr11 + test_fpr_a5a5 fr12 + test_fpr_a5a5 fr13 + test_fpr_a5a5 fr14 + test_fpr_a5a5 fr15 + + pass + exit 0 + diff --git a/sim/testsuite/sim/sh/fldi0.s b/sim/testsuite/sim/sh/fldi0.s new file mode 100644 index 0000000..1e20058 --- /dev/null +++ b/sim/testsuite/sim/sh/fldi0.s @@ -0,0 +1,37 @@ +# sh testcase for fldi0 $frn +# mach: sh +# as(sh): -defsym sim_cpu=0 + + .include "testutils.inc" + + start +fldi0_single: + set_grs_a5a5 + set_fprs_a5a5 + fldi0 fr0 + fldi0 fr2 + fldi0 fr4 + fldi0 fr6 + fldi0 fr8 + fldi0 fr10 + fldi0 fr12 + fldi0 fr14 + test_grs_a5a5 + assert_fpreg_i 0 fr0 + assert_fpreg_i 0 fr2 + assert_fpreg_i 0 fr4 + assert_fpreg_i 0 fr6 + assert_fpreg_i 0 fr8 + assert_fpreg_i 0 fr10 + assert_fpreg_i 0 fr12 + assert_fpreg_i 0 fr14 + assert_fpreg_x 0xa5a5a5a5 fr1 + assert_fpreg_x 0xa5a5a5a5 fr3 + assert_fpreg_x 0xa5a5a5a5 fr5 + assert_fpreg_x 0xa5a5a5a5 fr7 + assert_fpreg_x 0xa5a5a5a5 fr9 + assert_fpreg_x 0xa5a5a5a5 fr11 + assert_fpreg_x 0xa5a5a5a5 fr13 + assert_fpreg_x 0xa5a5a5a5 fr15 + pass + exit 0 diff --git a/sim/testsuite/sim/sh/fldi1.s b/sim/testsuite/sim/sh/fldi1.s new file mode 100644 index 0000000..1b7c170 --- /dev/null +++ b/sim/testsuite/sim/sh/fldi1.s @@ -0,0 +1,38 @@ +# sh testcase for fldi1 $frn +# mach: sh +# as(sh): -defsym sim_cpu=0 + + .include "testutils.inc" + + start +fldi1_single: + set_grs_a5a5 + set_fprs_a5a5 + fldi1 fr1 + fldi1 fr3 + fldi1 fr5 + fldi1 fr7 + fldi1 fr9 + fldi1 fr11 + fldi1 fr13 + fldi1 fr15 + test_grs_a5a5 + assert_fpreg_x 0xa5a5a5a5 fr0 + assert_fpreg_x 0xa5a5a5a5 fr2 + assert_fpreg_x 0xa5a5a5a5 fr4 + assert_fpreg_x 0xa5a5a5a5 fr6 + assert_fpreg_x 0xa5a5a5a5 fr8 + assert_fpreg_x 0xa5a5a5a5 fr10 + assert_fpreg_x 0xa5a5a5a5 fr12 + assert_fpreg_x 0xa5a5a5a5 fr14 + assert_fpreg_i 1 fr1 + assert_fpreg_i 1 fr3 + assert_fpreg_i 1 fr5 + assert_fpreg_i 1 fr7 + assert_fpreg_i 1 fr9 + assert_fpreg_i 1 fr11 + assert_fpreg_i 1 fr13 + assert_fpreg_i 1 fr15 + + pass + exit 0 diff --git a/sim/testsuite/sim/sh/flds.s b/sim/testsuite/sim/sh/flds.s new file mode 100644 index 0000000..086b4ed --- /dev/null +++ b/sim/testsuite/sim/sh/flds.s @@ -0,0 +1,43 @@ +# sh testcase for flds +# mach: sh +# as(sh): -defsym sim_cpu=0 + + .include "testutils.inc" + + start +flds_zero: + set_grs_a5a5 + set_fprs_a5a5 + fldi0 fr0 + flds fr0, fpul + fsts fpul, fr1 + fcmp/eq fr0, fr1 + bt flds_one + fail +flds_one: + fldi1 fr0 + flds fr0, fpul + fsts fpul, fr1 + fcmp/eq fr0, fr1 + bt .L0 + fail +.L0: + test_grs_a5a5 + assert_fpreg_i 1, fr0 + assert_fpreg_i 1, fr1 + test_fpr_a5a5 fr2 + test_fpr_a5a5 fr3 + test_fpr_a5a5 fr4 + test_fpr_a5a5 fr5 + test_fpr_a5a5 fr6 + test_fpr_a5a5 fr7 + test_fpr_a5a5 fr8 + test_fpr_a5a5 fr9 + test_fpr_a5a5 fr10 + test_fpr_a5a5 fr11 + test_fpr_a5a5 fr12 + test_fpr_a5a5 fr13 + test_fpr_a5a5 fr14 + test_fpr_a5a5 fr15 + pass + exit 0 diff --git a/sim/testsuite/sim/sh/float.s b/sim/testsuite/sim/sh/float.s new file mode 100644 index 0000000..e5a3bc6 --- /dev/null +++ b/sim/testsuite/sim/sh/float.s @@ -0,0 +1,149 @@ +# sh testcase for float +# mach: sh +# as(sh): -defsym sim_cpu=0 + + .include "testutils.inc" + + start + +float_pos: + set_grs_a5a5 + set_fprs_a5a5 + single_prec + mov #3, r0 + lds r0, fpul + float fpul, fr2 + + # Check the result. + fldi1 fr0 + fldi1 fr1 + fadd fr0, fr1 + fadd fr0, fr1 + fcmp/eq fr1, fr2 + bt float_neg + fail + +float_neg: + mov #3, r0 + neg r0, r0 + lds r0, fpul + float fpul, fr2 + + # Check the result. + fldi1 fr0 + fldi1 fr1 + fadd fr0, fr1 + fadd fr0, fr1 + fneg fr1 + fcmp/eq fr1, fr2 + bt .L0 + fail +.L0: + assertreg0 -3 + test_gr_a5a5 r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + + assert_fpreg_i 1, fr0 + assert_fpreg_i -3, fr1 + assert_fpreg_i -3, fr2 + test_fpr_a5a5 fr3 + test_fpr_a5a5 fr4 + test_fpr_a5a5 fr5 + test_fpr_a5a5 fr6 + test_fpr_a5a5 fr7 + test_fpr_a5a5 fr8 + test_fpr_a5a5 fr9 + test_fpr_a5a5 fr10 + test_fpr_a5a5 fr11 + test_fpr_a5a5 fr12 + test_fpr_a5a5 fr13 + test_fpr_a5a5 fr14 + test_fpr_a5a5 fr15 + +double_pos: + set_grs_a5a5 + set_fprs_a5a5 + double_prec + mov #3, r0 + lds r0, fpul + float fpul, dr4 + + # check the result. + fldi1 fr0 + fldi1 fr1 + single_prec + fadd fr0, fr1 + fadd fr0, fr1 + double_prec + _s2d fr1, dr2 + fcmp/eq dr2, dr4 + bt double_neg + fail + +double_neg: + double_prec + mov #3, r0 + neg r0, r0 + lds r0, fpul + float fpul, dr4 + + # check the result. + fldi1 fr0 + fldi1 fr1 + single_prec + fadd fr0, fr1 + fadd fr0, fr1 + fneg fr1 + double_prec + _s2d fr1, dr2 + fcmp/eq dr2, dr4 + bt .L2 + fail +.L2: + assertreg0 -3 + test_gr_a5a5 r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + + single_prec + assert_fpreg_i 1, fr0 + assert_fpreg_i -3, fr1 + double_prec + assert_dpreg_i -3, dr2 + assert_dpreg_i -3, dr4 + test_fpr_a5a5 fr6 + test_fpr_a5a5 fr7 + test_fpr_a5a5 fr8 + test_fpr_a5a5 fr9 + test_fpr_a5a5 fr10 + test_fpr_a5a5 fr11 + test_fpr_a5a5 fr12 + test_fpr_a5a5 fr13 + test_fpr_a5a5 fr14 + test_fpr_a5a5 fr15 + + pass + exit 0 diff --git a/sim/testsuite/sim/sh/fmac.s b/sim/testsuite/sim/sh/fmac.s new file mode 100644 index 0000000..eba1da5 --- /dev/null +++ b/sim/testsuite/sim/sh/fmac.s @@ -0,0 +1,98 @@ +# sh testcase for fmac +# mach: sh +# as(sh): -defsym sim_cpu=0 + + .include "testutils.inc" + + start +fmac_: + set_grs_a5a5 + set_fprs_a5a5 + # 0.0 * x + y = y. + + fldi0 fr0 + fldi1 fr1 + fldi1 fr2 + fmac fr0, fr1, fr2 + # check result. + fldi1 fr0 + fcmp/eq fr0, fr2 + bt .L0 + fail +.L0: + # x * y + 0.0 = x * y. + + fldi1 fr0 + fldi1 fr1 + fldi0 fr2 + # double it. + fadd fr1, fr2 + fmac fr0, fr1, fr2 + # check result. + fldi1 fr0 + fadd fr0, fr0 + fcmp/eq fr0, fr2 + bt .L1 + fail +.L1: + # x * 0.0 + y = y. + + fldi1 fr0 + fldi0 fr1 + fldi1 fr2 + fadd fr2, fr2 + fmac fr0, fr1, fr2 + # check result. + fldi1 fr0 + # double fr0. + fadd fr0, fr0 + fcmp/eq fr0, fr2 + bt .L2 + fail +.L2: + # x * 0.0 + 0.0 = 0.0 + + fldi1 fr0 + fadd fr0, fr0 + fldi0 fr1 + fldi0 fr2 + fmac fr0, fr1, fr2 + # check result. + fldi0 fr0 + fcmp/eq fr0, fr2 + bt .L3 + fail +.L3: + # 0.0 * x + 0.0 = 0.0. + + fldi0 fr0 + fldi1 fr1 + # double it. + fadd fr1, fr1 + fldi0 fr2 + fmac fr0, fr1, fr2 + # check result. + fldi0 fr0 + fcmp/eq fr0, fr2 + bt .L4 + fail +.L4: + test_grs_a5a5 + assert_fpreg_i 0, fr0 + assert_fpreg_i 2, fr1 + assert_fpreg_i 0, fr2 + test_fpr_a5a5 fr3 + test_fpr_a5a5 fr4 + test_fpr_a5a5 fr5 + test_fpr_a5a5 fr6 + test_fpr_a5a5 fr7 + test_fpr_a5a5 fr8 + test_fpr_a5a5 fr9 + test_fpr_a5a5 fr10 + test_fpr_a5a5 fr11 + test_fpr_a5a5 fr12 + test_fpr_a5a5 fr13 + test_fpr_a5a5 fr14 + test_fpr_a5a5 fr15 + pass + exit 0 diff --git a/sim/testsuite/sim/sh/fmov.s b/sim/testsuite/sim/sh/fmov.s new file mode 100644 index 0000000..29c51b5 --- /dev/null +++ b/sim/testsuite/sim/sh/fmov.s @@ -0,0 +1,322 @@ +# sh testcase for all fmov instructions +# mach: sh +# as(sh): -defsym sim_cpu=0 + + .include "testutils.inc" + + .macro init + fldi0 fr0 + fldi1 fr1 + fldi1 fr2 + fldi1 fr3 + .endm + + start + +fmov1: # Test fr -> fr. + set_grs_a5a5 + set_fprs_a5a5 + init + single_prec + sz_32 + fmov fr0, fr1 + # Ensure fr0 and fr1 are now equal. + fcmp/eq fr0, fr1 + bt fmov2 + fail + +fmov2: # Test dr -> dr. + init + double_prec + sz_64 + fmov dr0, dr2 + # Ensure dr0 and dr2 are now equal. + fcmp/eq dr0, dr2 + bt fmov3 + fail + +fmov3: # Test dr -> xd and xd -> dr. + init + sz_64 + fmov dr0, xd0 + # Ensure dr0 and xd0 are now equal. + fmov xd0, dr2 + fcmp/eq dr0, dr2 + bt fmov4 + fail + +fmov4: # Test xd -> xd. + init + sz_64 + double_prec + fmov dr0, xd0 + fmov xd0, xd2 + fmov xd2, dr2 + # Ensure dr0 and dr2 are now equal. + fcmp/eq dr0, dr2 + bt .L0 + fail + + # FIXME: test fmov.s fr -> @gr, fmov dr -> @gr + # FIXME: test fmov.s @gr -> fr, fmov @gr -> dr + # FIXME: test fmov.s @gr+ -> fr, fmov @gr+ -> dr + # FIXME: test fmov.s fr -> @-gr, fmov dr -> @-gr + # FIXME: test fmov.s @(r0,gr) -> fr, fmov @(r0,gr) -> dr + # FIXME: test fmov.s fr -> @(r0,gr), fmov dr -> @(r0,gr) + +.L0: + test_grs_a5a5 + sz_32 + single_prec + assert_fpreg_i 0, fr0 + assert_fpreg_i 1, fr1 + assert_fpreg_i 0, fr2 + assert_fpreg_i 1, fr3 + test_fpr_a5a5 fr4 + test_fpr_a5a5 fr5 + test_fpr_a5a5 fr6 + test_fpr_a5a5 fr7 + test_fpr_a5a5 fr8 + test_fpr_a5a5 fr9 + test_fpr_a5a5 fr10 + test_fpr_a5a5 fr11 + test_fpr_a5a5 fr12 + test_fpr_a5a5 fr13 + test_fpr_a5a5 fr14 + test_fpr_a5a5 fr15 + +fmov5: # Test fr -> @rn and @rn -> fr. + init + sz_32 + single_prec + # FIXME! Use a reserved memory location! + mov #40, r0 + shll8 r0 + fmov fr0, @r0 + fmov @r0, fr1 + fcmp/eq fr0, fr1 + bt fmov6 + fail + +fmov6: # Test dr -> @rn and @rn -> dr. + init + sz_64 + double_prec + mov #40, r0 + shll8 r0 + fmov dr0, @r0 + fmov @r0, dr2 + fcmp/eq dr0, dr2 + bt fmov7 + fail + +fmov7: # Test xd -> @rn and @rn -> xd. + init + sz_64 + double_prec + mov #40, r0 + shll8 r0 + fmov dr0, xd0 + fmov xd0, @r0 + fmov @r0, xd2 + fmov xd2, dr2 + fcmp/eq dr0, dr2 + bt fmov8 + fail + +fmov8: # Test fr -> @-rn. + init + sz_32 + single_prec + mov #40, r0 + shll8 r0 + # Preserve. + mov r0, r1 + fmov fr0, @-r0 + fmov @r0, fr2 + fcmp/eq fr0, fr2 + bt f8b + fail +f8b: # check pre-dec. + add #4, r0 + cmp/eq r0, r1 + bt fmov9 + fail + +fmov9: # Test dr -> @-rn. + init + sz_64 + double_prec + mov #40, r0 + shll8 r0 + # Preserve r0. + mov r0, r1 + fmov dr0, @-r0 + fmov @r0, dr2 + fcmp/eq dr0, dr2 + bt f9b + fail +f9b: # check pre-dec. + add #8, r0 + cmp/eq r0, r1 + bt fmov10 + fail + +fmov10: # Test xd -> @-rn. + init + sz_64 + double_prec + mov #40, r0 + shll8 r0 + # Preserve r0. + mov r0, r1 + fmov dr0, xd0 + fmov xd0, @-r0 + fmov @r0, xd2 + fmov xd2, dr2 + fcmp/eq dr0, dr2 + bt f10b + fail +f10b: # check pre-dec. + add #8, r0 + cmp/eq r0, r1 + bt fmov11 + fail + +fmov11: # Test @rn+ -> fr. + init + sz_32 + single_prec + mov #40, r0 + shll8 r0 + # Preserve r0. + mov r0, r1 + fmov fr0, @r0 + fmov @r0+, fr2 + fcmp/eq fr0, fr2 + bt f11b + fail +f11b: # check post-inc. + add #4, r1 + cmp/eq r0, r1 + bt fmov12 + fail + +fmov12: # Test @rn+ -> dr. + init + sz_64 + double_prec + mov #40, r0 + shll8 r0 + # preserve r0. + mov r0, r1 + fmov dr0, @r0 + fmov @r0+, dr2 + fcmp/eq dr0, dr2 + bt f12b + fail +f12b: # check post-inc. + add #8, r1 + cmp/eq r0, r1 + bt fmov13 + fail + +fmov13: # Test @rn -> xd. + init + sz_64 + double_prec + mov #40, r0 + shll8 r0 + # Preserve r0. + mov r0, r1 + fmov dr0, xd0 + fmov xd0, @r0 + fmov @r0+, xd2 + fmov xd2, dr2 + fcmp/eq dr0, dr2 + bt f13b + fail +f13b: + add #8, r1 + cmp/eq r0, r1 + bt fmov14 + fail + +fmov14: # Test fr -> @(r0,rn), @(r0, rn) -> fr. + init + sz_32 + single_prec + mov #40, r0 + shll8 r0 + mov #0, r1 + fmov fr0, @(r0, r1) + fmov @(r0, r1), fr1 + fcmp/eq fr0, fr1 + bt fmov15 + fail + +fmov15: # Test dr -> @(r0, rn), @(r0, rn) -> dr. + init + sz_64 + double_prec + mov #40, r0 + shll8 r0 + mov #0, r1 + fmov dr0, @(r0, r1) + fmov @(r0, r1), dr2 + fcmp/eq dr0, dr2 + bt fmov16 + fail + +fmov16: # Test xd -> @(r0, rn), @(r0, rn) -> xd. + init + sz_64 + double_prec + mov #40, r0 + shll8 r0 + mov #0, r1 + fmov dr0, xd0 + fmov xd0, @(r0, r1) + fmov @(r0, r1), xd2 + fmov xd2, dr2 + fcmp/eq dr0, dr2 + bt .L1 + fail +.L1: + assertreg0 0x2800 + assertreg 0, r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + + sz_32 + single_prec + assert_fpreg_i 0, fr0 + assert_fpreg_i 1, fr1 + assert_fpreg_i 0, fr2 + assert_fpreg_i 1, fr3 + test_fpr_a5a5 fr4 + test_fpr_a5a5 fr5 + test_fpr_a5a5 fr6 + test_fpr_a5a5 fr7 + test_fpr_a5a5 fr8 + test_fpr_a5a5 fr9 + test_fpr_a5a5 fr10 + test_fpr_a5a5 fr11 + test_fpr_a5a5 fr12 + test_fpr_a5a5 fr13 + test_fpr_a5a5 fr14 + test_fpr_a5a5 fr15 + + pass + exit 0 diff --git a/sim/testsuite/sim/sh/fmul.s b/sim/testsuite/sim/sh/fmul.s new file mode 100644 index 0000000..81a2545 --- /dev/null +++ b/sim/testsuite/sim/sh/fmul.s @@ -0,0 +1,116 @@ +# sh testcase for fmul +# mach: sh +# as(sh): -defsym sim_cpu=0 + + .include "testutils.inc" + + .macro init + fldi0 fr0 + fldi1 fr1 + fldi1 fr2 + fadd fr2, fr2 + .endm + + start +fmul_single: + set_grs_a5a5 + set_fprs_a5a5 + # 0.0 * 0.0 = 0.0. + init + fmul fr0, fr0 + assert_fpreg_i 0, fr0 + + # 0.0 * 1.0 = 0.0. + init + fmul fr1, fr0 + assert_fpreg_i 0, fr0 + + # 1.0 * 0.0 = 0.0. + init + fmul fr0, fr1 + assert_fpreg_i 0, fr1 + + # 1.0 * 1.0 = 1.0. + init + fmul fr1, fr1 + assert_fpreg_i 1, fr1 + + # 2.0 * 1.0 = 2.0. + init + fmul fr2, fr1 + assert_fpreg_i 2, fr1 + + test_grs_a5a5 + assert_fpreg_i 0, fr0 + assert_fpreg_i 2, fr1 + assert_fpreg_i 2, fr2 + test_fpr_a5a5 fr3 + test_fpr_a5a5 fr4 + test_fpr_a5a5 fr5 + test_fpr_a5a5 fr6 + test_fpr_a5a5 fr7 + test_fpr_a5a5 fr8 + test_fpr_a5a5 fr9 + test_fpr_a5a5 fr10 + test_fpr_a5a5 fr11 + test_fpr_a5a5 fr12 + test_fpr_a5a5 fr13 + test_fpr_a5a5 fr14 + test_fpr_a5a5 fr15 + + .macro dinit + fldi0 fr0 + fldi1 fr2 + fldi1 fr4 + single_prec + fadd fr4, fr4 + double_prec + _s2d fr0, dr0 + _s2d fr2, dr2 + _s2d fr4, dr4 + .endm + +fmul_double: + double_prec + # 0.0 * 0.0 = 0.0. + dinit + fmul dr0, dr0 + assert_dpreg_i 0, dr0 + + # 0.0 * 1.0 = 0.0. + dinit + fmul dr2, dr0 + assert_dpreg_i 0, dr0 + + # 1.0 * 0.0 = 0.0. + dinit + fmul dr0, dr2 + assert_dpreg_i 0, dr2 + + # 1.0 * 1.0 = 1.0. + dinit + fmul dr2, dr2 + assert_dpreg_i 1, dr2 + + # 2.0 * 1.0 = 2.0. + dinit + fmul dr4, dr2 + assert_dpreg_i 2, dr2 + + test_grs_a5a5 + assert_dpreg_i 0, dr0 + assert_dpreg_i 2, dr2 + assert_dpreg_i 2, dr4 + test_fpr_a5a5 fr6 + test_fpr_a5a5 fr7 + test_fpr_a5a5 fr8 + test_fpr_a5a5 fr9 + test_fpr_a5a5 fr10 + test_fpr_a5a5 fr11 + test_fpr_a5a5 fr12 + test_fpr_a5a5 fr13 + test_fpr_a5a5 fr14 + test_fpr_a5a5 fr15 + + pass + exit 0 diff --git a/sim/testsuite/sim/sh/fneg.s b/sim/testsuite/sim/sh/fneg.s new file mode 100644 index 0000000..dd5fe5d --- /dev/null +++ b/sim/testsuite/sim/sh/fneg.s @@ -0,0 +1,112 @@ +# sh testcase for fneg +# mach: sh +# as(sh): -defsym sim_cpu=0 + + .include "testutils.inc" + + start +fneg_single: + set_grs_a5a5 + set_fprs_a5a5 + # neg(0.0) = 0.0. + fldi0 fr0 + fldi0 fr1 + fneg fr0 + fcmp/eq fr0, fr1 + bt .L0 + fail +.L0: + # neg(1.0) = fsub(0,1) + fldi1 fr0 + fneg fr0 + fldi0 fr1 + fldi1 fr2 + fsub fr2, fr1 + fcmp/eq fr0, fr1 + bt .L1 + fail +.L1: + # neg(neg(1.0)) = 1.0. + fldi1 fr0 + fldi1 fr1 + fneg fr0 + fneg fr0 + fcmp/eq fr0, fr1 + bt .L2 + fail +.L2: + test_grs_a5a5 + assert_fpreg_i 1, fr0 + assert_fpreg_i 1, fr1 + assert_fpreg_i 1, fr2 + test_fpr_a5a5 fr3 + test_fpr_a5a5 fr4 + test_fpr_a5a5 fr5 + test_fpr_a5a5 fr6 + test_fpr_a5a5 fr7 + test_fpr_a5a5 fr8 + test_fpr_a5a5 fr9 + test_fpr_a5a5 fr10 + test_fpr_a5a5 fr11 + test_fpr_a5a5 fr12 + test_fpr_a5a5 fr13 + test_fpr_a5a5 fr14 + test_fpr_a5a5 fr15 + +fneg_double: + set_grs_a5a5 + set_fprs_a5a5 + double_prec + # neg(0.0) = 0.0. + fldi0 fr0 + fldi0 fr2 + _s2d fr0, dr0 + _s2d fr2, dr2 + fneg dr0 + fcmp/eq dr0, dr2 + bt .L10 + fail +.L10: + # neg(1.0) = fsub(0,1) + fldi1 fr0 + _s2d fr0, dr0 + fneg dr0 + fldi0 fr2 + fldi1 fr3 + single_prec + fsub fr3, fr2 + double_prec + _s2d fr2, dr2 + fcmp/eq dr0, dr2 + bt .L11 + fail +.L11: + # neg(neg(1.0)) = 1.0. + fldi1 fr0 + _s2d fr0, dr0 + fldi1 fr2 + _s2d fr2, dr2 + fneg dr2 + fneg dr2 + fcmp/eq dr0, dr2 + bt .L12 + fail +.L12: + test_grs_a5a5 + assert_dpreg_i 1, dr0 + assert_dpreg_i 1, dr2 + test_fpr_a5a5 fr4 + test_fpr_a5a5 fr5 + test_fpr_a5a5 fr6 + test_fpr_a5a5 fr7 + test_fpr_a5a5 fr8 + test_fpr_a5a5 fr9 + test_fpr_a5a5 fr10 + test_fpr_a5a5 fr11 + test_fpr_a5a5 fr12 + test_fpr_a5a5 fr13 + test_fpr_a5a5 fr14 + test_fpr_a5a5 fr15 + + pass + exit 0 diff --git a/sim/testsuite/sim/sh/frchg.s b/sim/testsuite/sim/sh/frchg.s new file mode 100644 index 0000000..c5dc099 --- /dev/null +++ b/sim/testsuite/sim/sh/frchg.s @@ -0,0 +1,30 @@ +# sh testcase for frchg +# mach: sh +# as(sh): -defsym sim_cpu=0 + + .include "testutils.inc" + + start + set_grs_a5a5 + set_fprs_a5a5 + sts fpscr, r0 + assertreg0 0 + frchg + sts fpscr, r0 + assertreg0 0x200000 + frchg + sts fpscr, r0 + assertreg0 0 + frchg + sts fpscr, r0 + assertreg0 0x200000 + frchg + sts fpscr, r0 + assertreg0 0 + + set_greg 0xa5a5a5a5, r0 + test_grs_a5a5 + test_fprs_a5a5 + + pass + exit 0 diff --git a/sim/testsuite/sim/sh/fschg.s b/sim/testsuite/sim/sh/fschg.s new file mode 100644 index 0000000..7454787 --- /dev/null +++ b/sim/testsuite/sim/sh/fschg.s @@ -0,0 +1,29 @@ +# sh testcase for fschg +# mach: sh +# as(sh): -defsym sim_cpu=0 + + .include "testutils.inc" + + start + set_grs_a5a5 + set_fprs_a5a5 + sts fpscr, r0 + assertreg0 0 + fschg + sts fpscr, r0 + assertreg0 0x100000 + fschg + sts fpscr, r0 + assertreg0 0 + fschg + sts fpscr, r0 + assertreg0 0x100000 + fschg + sts fpscr, r0 + assertreg0 0 + + set_greg 0xa5a5a5a5 r0 + test_grs_a5a5 + test_fprs_a5a5 + pass + exit 0 diff --git a/sim/testsuite/sim/sh/fsqrt.s b/sim/testsuite/sim/sh/fsqrt.s new file mode 100644 index 0000000..cb61bcf --- /dev/null +++ b/sim/testsuite/sim/sh/fsqrt.s @@ -0,0 +1,120 @@ +# sh testcase for fsqrt +# mach: sh +# as(sh): -defsym sim_cpu=0 + + .include "testutils.inc" + + start +fsqrt_single: + set_grs_a5a5 + set_fprs_a5a5 + # sqrt(0.0) = 0.0. + fldi0 fr0 + fsqrt fr0 + fldi0 fr1 + fcmp/eq fr0, fr1 + bt .L0 + fail +.L0: + # sqrt(1.0) = 1.0. + fldi1 fr0 + fsqrt fr0 + fldi1 fr1 + fcmp/eq fr0, fr1 + bt .L1 + fail +.L1: + # sqrt(4.0) = 2.0 + fldi1 fr0 + # Double it. + fadd fr0, fr0 + # Double it again. + fadd fr0, fr0 + fsqrt fr0 + fldi1 fr1 + # Double it. + fadd fr1, fr1 + fcmp/eq fr0, fr1 + bt .L2 + fail +.L2: + test_grs_a5a5 + assert_fpreg_i 2, fr0 + assert_fpreg_i 2, fr1 + test_fpr_a5a5 fr2 + test_fpr_a5a5 fr3 + test_fpr_a5a5 fr4 + test_fpr_a5a5 fr5 + test_fpr_a5a5 fr6 + test_fpr_a5a5 fr7 + test_fpr_a5a5 fr8 + test_fpr_a5a5 fr9 + test_fpr_a5a5 fr10 + test_fpr_a5a5 fr11 + test_fpr_a5a5 fr12 + test_fpr_a5a5 fr13 + test_fpr_a5a5 fr14 + test_fpr_a5a5 fr15 + +fsqrt_double: + double_prec + set_grs_a5a5 + set_fprs_a5a5 + # sqrt(0.0) = 0.0. + fldi0 fr0 + _s2d fr0, dr0 + fsqrt dr0 + fldi0 fr2 + _s2d fr2, dr2 + fcmp/eq dr0, dr2 + bt .L10 + fail +.L10: + # sqrt(1.0) = 1.0. + fldi1 fr0 + _s2d fr0, dr0 + fsqrt dr0 + fldi1 fr2 + _s2d fr2, dr2 + fcmp/eq dr0, dr2 + bt .L11 + fail +.L11: + # sqrt(4.0) = 2.0. + fldi1 fr0 + # Double it. + single_prec + fadd fr0, fr0 + # Double it again. + fadd fr0, fr0 + double_prec + _s2d fr0, dr0 + fsqrt dr0 + fldi1 fr2 + # Double it. + single_prec + fadd fr2, fr2 + double_prec + _s2d fr2, dr2 + fcmp/eq dr0, dr2 + bt .L12 + fail +.L12: + test_grs_a5a5 + assert_dpreg_i 2, dr0 + assert_dpreg_i 2, dr2 + test_fpr_a5a5 fr4 + test_fpr_a5a5 fr5 + test_fpr_a5a5 fr6 + test_fpr_a5a5 fr7 + test_fpr_a5a5 fr8 + test_fpr_a5a5 fr9 + test_fpr_a5a5 fr10 + test_fpr_a5a5 fr11 + test_fpr_a5a5 fr12 + test_fpr_a5a5 fr13 + test_fpr_a5a5 fr14 + test_fpr_a5a5 fr15 + + pass + exit 0 diff --git a/sim/testsuite/sim/sh/fsub.s b/sim/testsuite/sim/sh/fsub.s new file mode 100644 index 0000000..dfe9172 --- /dev/null +++ b/sim/testsuite/sim/sh/fsub.s @@ -0,0 +1,136 @@ +# sh testcase for fsub +# mach: sh +# as(sh): -defsym sim_cpu=0 + + .include "testutils.inc" + + start +fsub_single: + set_grs_a5a5 + set_fprs_a5a5 + # 0.0 - 0.0 = 0.0. + fldi0 fr0 + fldi0 fr1 + fsub fr0, fr1 + fldi0 fr2 + fcmp/eq fr1, fr2 + bt .L0 + fail +.L0: + # 1.0 - 0.0 = 1.0. + fldi0 fr0 + fldi1 fr1 + fsub fr0, fr1 + fldi1 fr2 + fcmp/eq fr1, fr2 + bt .L1 + fail +.L1: + # 1.0 - 1.0 = 0.0. + fldi1 fr0 + fldi1 fr1 + fsub fr0, fr1 + fldi0 fr2 + fcmp/eq fr1, fr2 + bt .L2 + fail +.L2: + # 0.0 - 1.0 = -1.0. + fldi1 fr0 + fldi0 fr1 + fsub fr0, fr1 + fldi1 fr2 + fneg fr2 + fcmp/eq fr1, fr2 + bt .L3 + fail +.L3: + test_grs_a5a5 + assert_fpreg_i 1, fr0 + assert_fpreg_i -1, fr1 + assert_fpreg_i -1, fr2 + test_fpr_a5a5 fr3 + test_fpr_a5a5 fr4 + test_fpr_a5a5 fr5 + test_fpr_a5a5 fr6 + test_fpr_a5a5 fr7 + test_fpr_a5a5 fr8 + test_fpr_a5a5 fr9 + test_fpr_a5a5 fr10 + test_fpr_a5a5 fr11 + test_fpr_a5a5 fr12 + test_fpr_a5a5 fr13 + test_fpr_a5a5 fr14 + test_fpr_a5a5 fr15 + +fsub_double: + set_grs_a5a5 + set_fprs_a5a5 + double_prec + # 0.0 - 0.0 = 0.0. + fldi0 fr0 + fldi0 fr2 + _s2d fr0, dr0 + _s2d fr2, dr2 + fsub dr0, dr2 + fldi0 fr4 + _s2d fr4, dr4 + fcmp/eq dr2, dr4 + bt .L10 + fail +.L10: + # 1.0 - 0.0 = 1.0. + fldi0 fr0 + fldi1 fr2 + _s2d fr0, dr0 + _s2d fr2, dr2 + fsub dr0, dr2 + fldi1 fr4 + _s2d fr4, dr4 + fcmp/eq dr2, dr4 + bt .L11 + fail +.L11: + # 1.0 - 1.0 = 0.0. + fldi1 fr0 + fldi1 fr2 + _s2d fr0, dr0 + _s2d fr2, dr2 + fsub dr0, dr2 + fldi0 fr4 + _s2d fr4, dr4 + fcmp/eq dr2, dr4 + bt .L12 + fail +.L12: + # 0.0 - 1.0 = -1.0. + fldi1 fr0 + fldi0 fr2 + _s2d fr0, dr0 + _s2d fr2, dr2 + fsub dr0, dr2 + fldi1 fr4 + single_prec + fneg fr4 + double_prec + _s2d fr4, dr4 + fcmp/eq dr2, dr4 + bt .L13 + fail +.L13: + test_grs_a5a5 + assert_dpreg_i 1, dr0 + assert_dpreg_i -1, dr2 + assert_dpreg_i -1, dr4 + test_fpr_a5a5 fr6 + test_fpr_a5a5 fr7 + test_fpr_a5a5 fr8 + test_fpr_a5a5 fr9 + test_fpr_a5a5 fr10 + test_fpr_a5a5 fr11 + test_fpr_a5a5 fr12 + test_fpr_a5a5 fr13 + test_fpr_a5a5 fr14 + test_fpr_a5a5 fr15 + pass + exit 0 diff --git a/sim/testsuite/sim/sh/ftrc.s b/sim/testsuite/sim/sh/ftrc.s new file mode 100644 index 0000000..25e33be --- /dev/null +++ b/sim/testsuite/sim/sh/ftrc.s @@ -0,0 +1,156 @@ +# sh testcase for ftrc +# mach: sh +# as(sh): -defsym sim_cpu=0 + + .include "testutils.inc" + + start +ftrc_single: + set_grs_a5a5 + set_fprs_a5a5 + # ftrc(0.0) = 0. + fldi0 fr0 + ftrc fr0, fpul + # check results. + mov #0, r0 + sts fpul, r1 + cmp/eq r0, r1 + bt .L0 + fail +.L0: + # ftrc(1.5) = 1. + fldi1 fr0 + fldi1 fr1 + fldi1 fr2 + # double it. + fadd fr2, fr2 + # form the fraction. + fdiv fr2, fr1 + fadd fr1, fr0 + # now we've got 1.5 in fr0. + ftrc fr0, fpul + # check results. + mov #1, r0 + sts fpul, r1 + cmp/eq r0, r1 + bt .L1 + fail +.L1: + # ftrc(-1.5) = -1. + fldi1 fr0 + fneg fr0 + fldi1 fr1 + fldi1 fr2 + # double it. + fadd fr2, fr2 + # form the fraction. + fdiv fr2, fr1 + fneg fr1 + # -1 + -0.5 = -1.5. + fadd fr1, fr0 + # now we've got 1.5 in fr0. + ftrc fr0, fpul + # check results. + mov #1, r0 + neg r0, r0 + sts fpul, r1 + cmp/eq r0, r1 + bt ftrc_double + fail + +ftrc_double: + double_prec + # ftrc(0.0) = 0. + fldi0 fr0 + _s2d fr0, dr0 + ftrc dr0, fpul + # check results. + mov #0, r0 + sts fpul, r1 + cmp/eq r0, r1 + bt .L10 + fail +.L10: + # ftrc(1.5) = 1. + fldi1 fr0 + fldi1 fr2 + fldi1 fr4 + # double it. + single_prec + fadd fr4, fr4 + # form 0.5. + fdiv fr4, fr2 + fadd fr2, fr0 + double_prec + # now we've got 1.5 in fr0, so do some single->double + # conversions and perform the ftrc. + _s2d fr0, dr0 + _s2d fr2, dr2 + _s2d fr4, dr4 + ftrc dr0, fpul + + # check results. + mov #1, r0 + sts fpul, r1 + cmp/eq r0, r1 + bt .L11 + fail +.L11: + # ftrc(-1.5) = -1. + fldi1 fr0 + fneg fr0 + fldi1 fr2 + fldi1 fr4 + single_prec + # double it. + fadd fr4, fr4 + # form the fraction. + fdiv fr4, fr2 + fneg fr2 + # -1 + -0.5 = -1.5. + fadd fr2, fr0 + double_prec + # now we've got 1.5 in fr0, so do some single->double + # conversions and perform the ftrc. + _s2d fr0, dr0 + _s2d fr2, dr2 + _s2d fr4, dr4 + ftrc dr0, fpul + + # check results. + mov #1, r0 + neg r0, r0 + sts fpul, r1 + cmp/eq r0, r1 + bt .L12 + fail +.L12: + assertreg0 -1 + assertreg -1, r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + + assert_dpreg_i 2, dr4 + test_fpr_a5a5 fr6 + test_fpr_a5a5 fr7 + test_fpr_a5a5 fr8 + test_fpr_a5a5 fr9 + test_fpr_a5a5 fr10 + test_fpr_a5a5 fr11 + test_fpr_a5a5 fr12 + test_fpr_a5a5 fr13 + test_fpr_a5a5 fr14 + test_fpr_a5a5 fr15 + pass + exit 0 diff --git a/sim/testsuite/sim/sh/macl.s b/sim/testsuite/sim/sh/macl.s new file mode 100644 index 0000000..39b3b7d --- /dev/null +++ b/sim/testsuite/sim/sh/macl.s @@ -0,0 +1,54 @@ +# sh testcase for mac.l +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + # force S-bit clear + clrs + +init: + # Prime {MACL, MACH} to #1. + mov #1, r0 + dmulu.l r0, r0 + + # Set up addresses. + mov.l pfour00, r0 ! 85 + mov.l pfour12, r1 ! 17 + +test: + mac.l @r0+, @r1+ + +check: + # Check result. + assert_sreg 0, mach + assert_sreg 85*17+1, macl + + # Ensure post-increment occurred. + assertreg0 four00+4 + assertreg four12+4, r1 + +doubleinc: + mov.l pfour00, r0 + mac.l @r0+, @r0+ + assertreg0 four00+8 + + + pass + exit 0 + + .align 1 +four00: + .long 85 + .long 2 +four12: + .long 17 + .long 3 + + .align 2 +pfour00: + .long four00 +pfour12: + .long four12 diff --git a/sim/testsuite/sim/sh/macw.s b/sim/testsuite/sim/sh/macw.s new file mode 100644 index 0000000..7e3ebc0 --- /dev/null +++ b/sim/testsuite/sim/sh/macw.s @@ -0,0 +1,56 @@ +# sh testcase for mac.w +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + set_grs_a5a5 + + # Prime {MACL, MACH} to #1. + mov #1, r0 + dmulu.l r0, r0 + + # Set up addresses. + mov.l pfour00, r0 ! 85 + mov.l pfour12, r1 ! 17 + +test: + mac.w @r0+, @r1+ ! MAC = 85 * 17 + 1 + +check: + # Check result. + assert_sreg 0, mach + assert_sreg 85*17+1, macl + + # Ensure post-increment occurred. + assertreg0 four00+2 + assertreg four12+2, r1 + +doubleinc: + mov.l pfour00, r0 + mac.w @r0+, @r0+ + assertreg0 four00+4 + + set_greg 0xa5a5a5a5, r0 + set_greg 0xa5a5a5a5, r1 + + test_grs_a5a5 + + pass + exit 0 + + .align 2 +four00: + .word 85 + .word 2 +four12: + .word 17 + .word 3 + + +pfour00: + .long four00 +pfour12: + .long four12 diff --git a/sim/testsuite/sim/sh/padd.s b/sim/testsuite/sim/sh/padd.s new file mode 100644 index 0000000..072935d --- /dev/null +++ b/sim/testsuite/sim/sh/padd.s @@ -0,0 +1,54 @@ +# sh testcase for padd +# mach: shdsp +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + set_grs_a5a5 + lds r0, a0 + pcopy a0, a1 + lds r0, x0 + lds r0, x1 + lds r0, y0 + lds r0, y1 + pcopy x0, m0 + pcopy y1, m1 + + padd x0, y0, a0 + assert_sreg 0x4b4b4b4a, a0 + + # 2 + 2 = 4 + mov #2, r0 + lds r0, x0 + lds r0, y0 + padd x0, y0, a0 + assert_sreg 4, a0 + + set_dcfalse + dct padd x0, y0, a1 + assert_sreg2 0xa5a5a5a5, a1 + set_dctrue + dct padd x0, y0, a1 + assert_sreg2 4, a1 + + set_dctrue + dcf padd x0, y0, m1 + assert_sreg2 0xa5a5a5a5, m1 + set_dcfalse + dcf padd x0, y0, m1 + assert_sreg2 4, m1 + + # padd / pmuls + + padd x0, y0, y0 pmuls x1, y1, m1 + assert_sreg 4, y0 + assert_sreg2 0x3fc838b2, m1 ! (int) 0xa5a5 x (int) 0xa5a5 x 2 + + set_greg 0xa5a5a5a5, r0 + test_grs_a5a5 + assert_sreg 0xa5a5a5a5, x1 + assert_sreg 0xa5a5a5a5, y1 + + pass + exit 0 diff --git a/sim/testsuite/sim/sh/paddc.s b/sim/testsuite/sim/sh/paddc.s new file mode 100644 index 0000000..0dd3b67 --- /dev/null +++ b/sim/testsuite/sim/sh/paddc.s @@ -0,0 +1,39 @@ +# sh testcase for paddc +# mach: shdsp +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + set_grs_a5a5 + lds r0, a0 + pcopy a0, a1 + lds r0, x0 + lds r0, x1 + lds r0, y0 + lds r0, y1 + pcopy x0, m0 + pcopy y1, m1 + + # 2 + 2 = 4 + set_dcfalse + mov #2, r0 + lds r0, x0 + lds r0, y0 + paddc x0, y0, a0 + assert_sreg 4, a0 + + # 2 + 2 + carry = 5 + set_dctrue + paddc x0, y0, a1 + assert_sreg2 5, a1 + + set_greg 0xa5a5a5a5, r0 + test_grs_a5a5 + assert_sreg 0xa5a5a5a5, x1 + assert_sreg 0xa5a5a5a5, y1 + assert_sreg2 0xa5a5a5a5, m0 + assert_sreg2 0xa5a5a5a5, m1 + + pass + exit 0 diff --git a/sim/testsuite/sim/sh/pand.s b/sim/testsuite/sim/sh/pand.s new file mode 100644 index 0000000..cddf058 --- /dev/null +++ b/sim/testsuite/sim/sh/pand.s @@ -0,0 +1,48 @@ +# sh testcase for pand +# mach: shdsp +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + set_grs_a5a5 + lds r0, a0 + pcopy a0, a1 + lds r0, x0 + lds r0, x1 + lds r0, y0 + lds r0, y1 + pcopy x0, m0 + pcopy y1, m1 + + pand x0, y0, a0 + assert_sreg 0xa5a50000, a0 + + # 0xa5a5a5a5 & 0x5a5a5a5a == 0 + set_greg 0x5a5a5a5a r0 + lds r0, x0 + pand x0, y0, a0 + assert_sreg 0, a0 + + set_dcfalse + dct pand x0, y0, m0 + assert_sreg2 0xa5a5a5a5, m0 + set_dctrue + dct pand x0, y0, m0 + assert_sreg2 0, m0 + + set_dctrue + dcf pand x0, y0, m1 + assert_sreg2 0xa5a5a5a5, m1 + set_dcfalse + dcf pand x0, y0, m1 + assert_sreg2 0, m1 + + set_greg 0xa5a5a5a5, r0 + test_grs_a5a5 + assert_sreg 0xa5a5a5a5, x1 + assert_sreg 0xa5a5a5a5, y1 + assert_sreg2 0xa5a5a5a5, a1 + + pass + exit 0 diff --git a/sim/testsuite/sim/sh/pdec.s b/sim/testsuite/sim/sh/pdec.s new file mode 100644 index 0000000..fa4b6a5 --- /dev/null +++ b/sim/testsuite/sim/sh/pdec.s @@ -0,0 +1,110 @@ +# sh testcase for pdec +# mach: shdsp +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + +pdecx: + set_grs_a5a5 + lds r0, a0 + pcopy a0, a1 + lds r0, x0 + lds r0, x1 + lds r0, y0 + lds r0, y1 + pcopy x0, m0 + pcopy y1, m1 + + pdec x0, y0 + assert_sreg 0xa5a40000, y0 + + test_grs_a5a5 + assert_sreg 0xa5a5a5a5, x0 + assert_sreg 0xa5a5a5a5, x1 + assert_sreg 0xa5a5a5a5, y1 + assert_sreg 0xa5a5a5a5, a0 + assert_sreg2 0xa5a5a5a5, a1 + assert_sreg2 0xa5a5a5a5, m0 + assert_sreg2 0xa5a5a5a5, m1 + +pdecy: + set_grs_a5a5 + lds r0, a0 + pcopy a0, a1 + lds r0, x0 + lds r0, x1 + lds r0, y0 + lds r0, y1 + pcopy x0, m0 + pcopy y1, m1 + + pdec y0, x0 + assert_sreg 0xa5a40000, x0 + + test_grs_a5a5 + assert_sreg 0xa5a5a5a5, y0 + assert_sreg 0xa5a5a5a5, x1 + assert_sreg 0xa5a5a5a5, y1 + assert_sreg 0xa5a5a5a5, a0 + assert_sreg2 0xa5a5a5a5, a1 + assert_sreg2 0xa5a5a5a5, m0 + assert_sreg2 0xa5a5a5a5, m1 + +dct_pdecx: + set_grs_a5a5 + lds r0, a0 + pcopy a0, a1 + lds r0, x0 + lds r0, x1 + lds r0, y0 + lds r0, y1 + pcopy x0, m0 + pcopy y1, m1 + + set_dcfalse + dct pdec x0, y0 + assert_sreg 0xa5a5a5a5, y0 + set_dctrue + dct pdec x0, y0 + assert_sreg 0xa5a40000, y0 + + test_grs_a5a5 + assert_sreg 0xa5a5a5a5, x0 + assert_sreg 0xa5a5a5a5, x1 + assert_sreg 0xa5a5a5a5, y1 + assert_sreg 0xa5a5a5a5, a0 + assert_sreg2 0xa5a5a5a5, a1 + assert_sreg2 0xa5a5a5a5, m0 + assert_sreg2 0xa5a5a5a5, m1 + +dcf_pdecy: + set_grs_a5a5 + lds r0, a0 + pcopy a0, a1 + lds r0, x0 + lds r0, x1 + lds r0, y0 + lds r0, y1 + pcopy x0, m0 + pcopy y1, m1 + + set_dctrue + dcf pdec y0, x0 + assert_sreg 0xa5a5a5a5, x0 + set_dcfalse + dcf pdec y0, x0 + assert_sreg 0xa5a40000, x0 + + test_grs_a5a5 + assert_sreg 0xa5a5a5a5, x1 + assert_sreg 0xa5a5a5a5, y0 + assert_sreg 0xa5a5a5a5, y1 + assert_sreg 0xa5a5a5a5, a0 + assert_sreg2 0xa5a5a5a5, a1 + assert_sreg2 0xa5a5a5a5, m0 + assert_sreg2 0xa5a5a5a5, m1 + + pass + exit 0 diff --git a/sim/testsuite/sim/sh/pdmsb.s b/sim/testsuite/sim/sh/pdmsb.s new file mode 100644 index 0000000..0cb7829 --- /dev/null +++ b/sim/testsuite/sim/sh/pdmsb.s @@ -0,0 +1,230 @@ +# sh testcase for pdmsb +# mach: shdsp +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + set_grs_a5a5 + lds r0, a0 + pcopy a0, a1 + lds r0, x0 + lds r0, x1 + lds r0, y0 + lds r0, y1 + pcopy x0, m0 + pcopy y1, m1 + + set_sreg 0x0, x0 +L0: pdmsb x0, x1 +# assert_sreg 31<<16, x1 + set_sreg 0x1, x0 +L1: pdmsb x0, x1 + assert_sreg 30<<16, x1 + set_sreg 0x3, x0 +L2: pdmsb x0, x1 + assert_sreg 29<<16, x1 + set_sreg 0x7, x0 +L3: pdmsb x0, x1 + assert_sreg 28<<16, x1 + set_sreg 0xf, x0 +L4: pdmsb x0, x1 + assert_sreg 27<<16, x1 + set_sreg 0x1f, x0 +L5: pdmsb x0, x1 + assert_sreg 26<<16, x1 + set_sreg 0x3f, x0 +L6: pdmsb x0, x1 + assert_sreg 25<<16, x1 + set_sreg 0x7f, x0 +L7: pdmsb x0, x1 + assert_sreg 24<<16, x1 + set_sreg 0xff, x0 +L8: pdmsb x0, x1 + assert_sreg 23<<16, x1 + + set_sreg 0x1ff, x0 +L9: pdmsb x0, x1 + assert_sreg 22<<16, x1 + set_sreg 0x3ff, x0 +L10: pdmsb x0, x1 + assert_sreg 21<<16, x1 + set_sreg 0x7ff, x0 +L11: pdmsb x0, x1 + assert_sreg 20<<16, x1 + set_sreg 0xfff, x0 +L12: pdmsb x0, x1 + assert_sreg 19<<16, x1 + set_sreg 0x1fff, x0 +L13: pdmsb x0, x1 + assert_sreg 18<<16, x1 + set_sreg 0x3fff, x0 +L14: pdmsb x0, x1 + assert_sreg 17<<16, x1 + set_sreg 0x7fff, x0 +L15: pdmsb x0, x1 + assert_sreg 16<<16, x1 + set_sreg 0xffff, x0 +L16: pdmsb x0, x1 + assert_sreg 15<<16, x1 + + set_sreg 0x1ffff, x0 +L17: pdmsb x0, x1 + assert_sreg 14<<16, x1 + set_sreg 0x3ffff, x0 +L18: pdmsb x0, x1 + assert_sreg 13<<16, x1 + set_sreg 0x7ffff, x0 +L19: pdmsb x0, x1 + assert_sreg 12<<16, x1 + set_sreg 0xfffff, x0 +L20: pdmsb x0, x1 + assert_sreg 11<<16, x1 + set_sreg 0x1fffff, x0 +L21: pdmsb x0, x1 + assert_sreg 10<<16, x1 + set_sreg 0x3fffff, x0 +L22: pdmsb x0, x1 + assert_sreg 9<<16, x1 + set_sreg 0x7fffff, x0 +L23: pdmsb x0, x1 + assert_sreg 8<<16, x1 + set_sreg 0xffffff, x0 +L24: pdmsb x0, x1 + assert_sreg 7<<16, x1 + + set_sreg 0x1ffffff, x0 +L25: pdmsb x0, x1 + assert_sreg 6<<16, x1 + set_sreg 0x3ffffff, x0 +L26: pdmsb x0, x1 + assert_sreg 5<<16, x1 + set_sreg 0x7ffffff, x0 +L27: pdmsb x0, x1 + assert_sreg 4<<16, x1 + set_sreg 0xfffffff, x0 +L28: pdmsb x0, x1 + assert_sreg 3<<16, x1 + set_sreg 0x1fffffff, x0 +L29: pdmsb x0, x1 + assert_sreg 2<<16, x1 + set_sreg 0x3fffffff, x0 +L30: pdmsb x0, x1 + assert_sreg 1<<16, x1 + set_sreg 0x7fffffff, x0 +L31: pdmsb x0, x1 + assert_sreg 0<<16, x1 + set_sreg 0xffffffff, x0 +L32: pdmsb x0, x1 +# assert_sreg 31<<16, x1 + + set_sreg 0xfffffffe, x0 +L33: pdmsb x0, x1 + assert_sreg 30<<16, x1 + set_sreg 0xfffffffc, x0 +L34: pdmsb x0, x1 + assert_sreg 29<<16, x1 + set_sreg 0xfffffff8, x0 +L35: pdmsb x0, x1 + assert_sreg 28<<16, x1 + set_sreg 0xfffffff0, x0 +L36: pdmsb x0, x1 + assert_sreg 27<<16, x1 + set_sreg 0xffffffe0, x0 +L37: pdmsb x0, x1 + assert_sreg 26<<16, x1 + set_sreg 0xffffffc0, x0 +L38: pdmsb x0, x1 + assert_sreg 25<<16, x1 + set_sreg 0xffffff80, x0 +L39: pdmsb x0, x1 + assert_sreg 24<<16, x1 + set_sreg 0xffffff00, x0 +L40: pdmsb x0, x1 + assert_sreg 23<<16, x1 + + set_sreg 0xfffffe00, x0 +L41: pdmsb x0, x1 + assert_sreg 22<<16, x1 + set_sreg 0xfffffc00, x0 +L42: pdmsb x0, x1 + assert_sreg 21<<16, x1 + set_sreg 0xfffff800, x0 +L43: pdmsb x0, x1 + assert_sreg 20<<16, x1 + set_sreg 0xfffff000, x0 +L44: pdmsb x0, x1 + assert_sreg 19<<16, x1 + set_sreg 0xffffe000, x0 +L45: pdmsb x0, x1 + assert_sreg 18<<16, x1 + set_sreg 0xffffc000, x0 +L46: pdmsb x0, x1 + assert_sreg 17<<16, x1 + set_sreg 0xffff8000, x0 +L47: pdmsb x0, x1 + assert_sreg 16<<16, x1 + set_sreg 0xffff0000, x0 +L48: pdmsb x0, x1 + assert_sreg 15<<16, x1 + + set_sreg 0xfffe0000, x0 +L49: pdmsb x0, x1 + assert_sreg 14<<16, x1 + set_sreg 0xfffc0000, x0 +L50: pdmsb x0, x1 + assert_sreg 13<<16, x1 + set_sreg 0xfff80000, x0 +L51: pdmsb x0, x1 + assert_sreg 12<<16, x1 + set_sreg 0xfff00000, x0 +L52: pdmsb x0, x1 + assert_sreg 11<<16, x1 + set_sreg 0xffe00000, x0 +L53: pdmsb x0, x1 + assert_sreg 10<<16, x1 + set_sreg 0xffc00000, x0 +L54: pdmsb x0, x1 + assert_sreg 9<<16, x1 + set_sreg 0xff800000, x0 +L55: pdmsb x0, x1 + assert_sreg 8<<16, x1 + set_sreg 0xff000000, x0 +L56: pdmsb x0, x1 + assert_sreg 7<<16, x1 + + set_sreg 0xfe000000, x0 +L57: pdmsb x0, x1 + assert_sreg 6<<16, x1 + set_sreg 0xfc000000, x0 +L58: pdmsb x0, x1 + assert_sreg 5<<16, x1 + set_sreg 0xf8000000, x0 +L59: pdmsb x0, x1 + assert_sreg 4<<16, x1 + set_sreg 0xf0000000, x0 +L60: pdmsb x0, x1 + assert_sreg 3<<16, x1 + set_sreg 0xe0000000, x0 +L61: pdmsb x0, x1 + assert_sreg 2<<16, x1 + set_sreg 0xc0000000, x0 +L62: pdmsb x0, x1 + assert_sreg 1<<16, x1 + set_sreg 0x80000000, x0 +L63: pdmsb x0, x1 + assert_sreg 0<<16, x1 + set_sreg 0x00000000, x0 +L64: pdmsb x0, x1 +# assert_sreg 31<<16, x1 + + test_grs_a5a5 + assert_sreg 0xa5a5a5a5, y0 + assert_sreg 0xa5a5a5a5, y1 + assert_sreg 0xa5a5a5a5, a0 + assert_sreg2 0xa5a5a5a5, a1 + assert_sreg2 0xa5a5a5a5, m0 + assert_sreg2 0xa5a5a5a5, m1 + + pass + exit 0 diff --git a/sim/testsuite/sim/sh/pinc.s b/sim/testsuite/sim/sh/pinc.s new file mode 100644 index 0000000..0067bc0 --- /dev/null +++ b/sim/testsuite/sim/sh/pinc.s @@ -0,0 +1,110 @@ +# sh testcase for pinc +# mach: shdsp +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + +pincx: + set_grs_a5a5 + lds r0, a0 + pcopy a0, a1 + lds r0, x0 + lds r0, x1 + lds r0, y0 + lds r0, y1 + pcopy x0, m0 + pcopy y1, m1 + + pinc x0, y0 + assert_sreg 0xa5a60000, y0 + + test_grs_a5a5 + assert_sreg 0xa5a5a5a5, x0 + assert_sreg 0xa5a5a5a5, x1 + assert_sreg 0xa5a5a5a5, y1 + assert_sreg 0xa5a5a5a5, a0 + assert_sreg2 0xa5a5a5a5, a1 + assert_sreg2 0xa5a5a5a5, m0 + assert_sreg2 0xa5a5a5a5, m1 + +pincy: + set_grs_a5a5 + lds r0, a0 + pcopy a0, a1 + lds r0, x0 + lds r0, x1 + lds r0, y0 + lds r0, y1 + pcopy x0, m0 + pcopy y1, m1 + + pinc y0, x0 + assert_sreg 0xa5a60000, x0 + + test_grs_a5a5 + assert_sreg 0xa5a5a5a5, y0 + assert_sreg 0xa5a5a5a5, x1 + assert_sreg 0xa5a5a5a5, y1 + assert_sreg 0xa5a5a5a5, a0 + assert_sreg2 0xa5a5a5a5, a1 + assert_sreg2 0xa5a5a5a5, m0 + assert_sreg2 0xa5a5a5a5, m1 + +dct_pincx: + set_grs_a5a5 + lds r0, a0 + pcopy a0, a1 + lds r0, x0 + lds r0, x1 + lds r0, y0 + lds r0, y1 + pcopy x0, m0 + pcopy y1, m1 + + set_dcfalse + dct pinc x0, y0 + assert_sreg 0xa5a5a5a5, y0 + set_dctrue + dct pinc x0, y0 + assert_sreg 0xa5a60000, y0 + + test_grs_a5a5 + assert_sreg 0xa5a5a5a5, x0 + assert_sreg 0xa5a5a5a5, x1 + assert_sreg 0xa5a5a5a5, y1 + assert_sreg 0xa5a5a5a5, a0 + assert_sreg2 0xa5a5a5a5, a1 + assert_sreg2 0xa5a5a5a5, m0 + assert_sreg2 0xa5a5a5a5, m1 + +dcf_pincy: + set_grs_a5a5 + lds r0, a0 + pcopy a0, a1 + lds r0, x0 + lds r0, x1 + lds r0, y0 + lds r0, y1 + pcopy x0, m0 + pcopy y1, m1 + + set_dctrue + dcf pinc y0, x0 + assert_sreg 0xa5a5a5a5, x0 + set_dcfalse + dcf pinc y0, x0 + assert_sreg 0xa5a60000, x0 + + test_grs_a5a5 + assert_sreg 0xa5a5a5a5, x1 + assert_sreg 0xa5a5a5a5, y0 + assert_sreg 0xa5a5a5a5, y1 + assert_sreg 0xa5a5a5a5, a0 + assert_sreg2 0xa5a5a5a5, a1 + assert_sreg2 0xa5a5a5a5, m0 + assert_sreg2 0xa5a5a5a5, m1 + + pass + exit 0 diff --git a/sim/testsuite/sim/sh/pmuls.s b/sim/testsuite/sim/sh/pmuls.s new file mode 100644 index 0000000..4cff878 --- /dev/null +++ b/sim/testsuite/sim/sh/pmuls.s @@ -0,0 +1,33 @@ +# sh testcase for pmuls +# mach: shdsp +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + set_grs_a5a5 + lds r0, a0 + pcopy a0, a1 + lds r0, x0 + lds r0, x1 + lds r0, y0 + lds r0, y1 + pcopy x0, m0 + pcopy y1, m1 + + # 2 x 2 = 8 (?) + # (I don't understand why the result is x2, + # but that's what it says in the manual...) + mov #2, r0 + shll16 r0 + lds r0, y0 + lds r0, y1 + pmuls y0, y1, a0 + + assert_sreg 8, a0 + + set_greg 0xa5a5a5a5, r0 + test_grs_a5a5 + pass + exit 0 + diff --git a/sim/testsuite/sim/sh/pshai.s b/sim/testsuite/sim/sh/pshai.s new file mode 100644 index 0000000..b2cdbbc --- /dev/null +++ b/sim/testsuite/sim/sh/pshai.s @@ -0,0 +1,200 @@ +# sh testcase for psha +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + +psha_imm: ! shift arithmetic, immediate operand + set_grs_a5a5 + lds r0, a0 + pcopy a0, a1 + lds r0, x0 + lds r0, x1 + lds r0, y0 + lds r0, y1 + pcopy x0, m0 + pcopy y1, m1 + + set_sreg 0x1, a0 + psha #0, a0 + assert_sreg 0x1, a0 + psha #-0, a0 + assert_sreg 0x1, a0 + + psha #1, a0 + assert_sreg 0x2, a0 + psha #-1, a0 + assert_sreg 0x1, a0 + + psha #2, a0 + assert_sreg 0x4, a0 + psha #-2, a0 + assert_sreg 0x1, a0 + + psha #3, a0 + assert_sreg 0x8, a0 + psha #-3, a0 + assert_sreg 0x1, a0 + + psha #4, a0 + assert_sreg 0x10, a0 + psha #-4, a0 + assert_sreg 0x1, a0 + + psha #5, a0 + assert_sreg 0x20, a0 + psha #-5, a0 + assert_sreg 0x1, a0 + + psha #6, a0 + assert_sreg 0x40, a0 + psha #-6, a0 + assert_sreg 0x1, a0 + + psha #7, a0 + assert_sreg 0x80, a0 + psha #-7, a0 + assert_sreg 0x1, a0 + + psha #8, a0 + assert_sreg 0x100, a0 + psha #-8, a0 + assert_sreg 0x1, a0 + + psha #9, a0 + assert_sreg 0x200, a0 + psha #-9, a0 + assert_sreg 0x1, a0 + + psha #10, a0 + assert_sreg 0x400, a0 + psha #-10, a0 + assert_sreg 0x1, a0 + + psha #11, a0 + assert_sreg 0x800, a0 + psha #-11, a0 + assert_sreg 0x1, a0 + + psha #12, a0 + assert_sreg 0x1000, a0 + psha #-12, a0 + assert_sreg 0x1, a0 + + psha #13, a0 + assert_sreg 0x2000, a0 + psha #-13, a0 + assert_sreg 0x1, a0 + + psha #14, a0 + assert_sreg 0x4000, a0 + psha #-14, a0 + assert_sreg 0x1, a0 + + psha #15, a0 + assert_sreg 0x8000, a0 + psha #-15, a0 + assert_sreg 0x1, a0 + + psha #16, a0 + assert_sreg 0x10000, a0 + psha #-16, a0 + assert_sreg 0x1, a0 + + psha #17, a0 + assert_sreg 0x20000, a0 + psha #-17, a0 + assert_sreg 0x1, a0 + + psha #18, a0 + assert_sreg 0x40000, a0 + psha #-18, a0 + assert_sreg 0x1, a0 + + psha #19, a0 + assert_sreg 0x80000, a0 + psha #-19, a0 + assert_sreg 0x1, a0 + + psha #20, a0 + assert_sreg 0x100000, a0 + psha #-20, a0 + assert_sreg 0x1, a0 + + psha #21, a0 + assert_sreg 0x200000, a0 + psha #-21, a0 + assert_sreg 0x1, a0 + + psha #22, a0 + assert_sreg 0x400000, a0 + psha #-22, a0 + assert_sreg 0x1, a0 + + psha #23, a0 + assert_sreg 0x800000, a0 + psha #-23, a0 + assert_sreg 0x1, a0 + + psha #24, a0 + assert_sreg 0x1000000, a0 + psha #-24, a0 + assert_sreg 0x1, a0 + + psha #25, a0 + assert_sreg 0x2000000, a0 + psha #-25, a0 + assert_sreg 0x1, a0 + + psha #26, a0 + assert_sreg 0x4000000, a0 + psha #-26, a0 + assert_sreg 0x1, a0 + + psha #27, a0 + assert_sreg 0x8000000, a0 + psha #-27, a0 + assert_sreg 0x1, a0 + + psha #28, a0 + assert_sreg 0x10000000, a0 + psha #-28, a0 + assert_sreg 0x1, a0 + + psha #29, a0 + assert_sreg 0x20000000, a0 + psha #-29, a0 + assert_sreg 0x1, a0 + + psha #30, a0 + assert_sreg 0x40000000, a0 + psha #-30, a0 + assert_sreg 0x1, a0 + + psha #31, a0 + assert_sreg 0x80000000, a0 + psha #-31, a0 + assert_sreg 0xffffffff, a0 + + psha #32, a0 + assert_sreg 0x00000000, a0 +# I don't grok what should happen here... +# psha #-32, a0 +# assert_sreg 0x0, a0 + + test_grs_a5a5 + assert_sreg2 0xa5a5a5a5, a1 + assert_sreg 0xa5a5a5a5, x0 + assert_sreg 0xa5a5a5a5, x1 + assert_sreg 0xa5a5a5a5, y0 + assert_sreg 0xa5a5a5a5, y1 + assert_sreg2 0xa5a5a5a5, m0 + assert_sreg2 0xa5a5a5a5, m1 + + + pass + exit 0 + diff --git a/sim/testsuite/sim/sh/pshar.s b/sim/testsuite/sim/sh/pshar.s new file mode 100644 index 0000000..01c4b5f --- /dev/null +++ b/sim/testsuite/sim/sh/pshar.s @@ -0,0 +1,265 @@ +# sh testcase for psha +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + +psha_reg: ! shift arithmetic, register operand + set_grs_a5a5 + lds r0, a0 + pcopy a0, a1 + lds r0, x0 + lds r0, x1 + lds r0, y0 + lds r0, y1 + pcopy x0, m0 + pcopy y1, m1 + + set_sreg 0x1, x0 + set_sreg 0x0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x10000, y0 + psha x0, y0, x0 + assert_sreg 0x2, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x20000, y0 + psha x0, y0, x0 + assert_sreg 0x4, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x30000, y0 + psha x0, y0, x0 + assert_sreg 0x8, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x40000, y0 + psha x0, y0, x0 + assert_sreg 0x10, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x50000, y0 + psha x0, y0, x0 + assert_sreg 0x20, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x60000, y0 + psha x0, y0, x0 + assert_sreg 0x40, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x70000, y0 + psha x0, y0, x0 + assert_sreg 0x80, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x80000, y0 + psha x0, y0, x0 + assert_sreg 0x100, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x90000, y0 + psha x0, y0, x0 + assert_sreg 0x200, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0xa0000, y0 + psha x0, y0, x0 + assert_sreg 0x400, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0xb0000, y0 + psha x0, y0, x0 + assert_sreg 0x800, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0xc0000, y0 + psha x0, y0, x0 + assert_sreg 0x1000, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0xd0000, y0 + psha x0, y0, x0 + assert_sreg 0x2000, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0xe0000, y0 + psha x0, y0, x0 + assert_sreg 0x4000, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0xf0000, y0 + psha x0, y0, x0 + assert_sreg 0x8000, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x100000, y0 + psha x0, y0, x0 + assert_sreg 0x10000, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x110000, y0 + psha x0, y0, x0 + assert_sreg 0x20000, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x120000, y0 + psha x0, y0, x0 + assert_sreg 0x40000, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x130000, y0 + psha x0, y0, x0 + assert_sreg 0x80000, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x140000, y0 + psha x0, y0, x0 + assert_sreg 0x100000, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x150000, y0 + psha x0, y0, x0 + assert_sreg 0x200000, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x160000, y0 + psha x0, y0, x0 + assert_sreg 0x400000, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x170000, y0 + psha x0, y0, x0 + assert_sreg 0x800000, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x180000, y0 + psha x0, y0, x0 + assert_sreg 0x1000000, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x190000, y0 + psha x0, y0, x0 + assert_sreg 0x2000000, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x1a0000, y0 + psha x0, y0, x0 + assert_sreg 0x4000000, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x1b0000, y0 + psha x0, y0, x0 + assert_sreg 0x8000000, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x1c0000, y0 + psha x0, y0, x0 + assert_sreg 0x10000000, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x1d0000, y0 + psha x0, y0, x0 + assert_sreg 0x20000000, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x1e0000, y0 + psha x0, y0, x0 + assert_sreg 0x40000000, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x1f0000, y0 + psha x0, y0, x0 + assert_sreg 0x80000000, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0xffffffff, x0 + + set_sreg 0x200000, y0 + psha x0, y0, x0 + assert_sreg 0x00000000, x0 +# I don't grok what should happen here... +# pneg y0, y0 +# psha x0, y0, x0 +# assert_sreg 0x0, x0 + + test_grs_a5a5 + assert_sreg 0xa5a5a5a5, a0 + assert_sreg2 0xa5a5a5a5, a1 + assert_sreg 0xa5a5a5a5, x1 + assert_sreg 0xa5a5a5a5, y1 + assert_sreg2 0xa5a5a5a5, m0 + assert_sreg2 0xa5a5a5a5, m1 + + + pass + exit 0 + diff --git a/sim/testsuite/sim/sh/pshli.s b/sim/testsuite/sim/sh/pshli.s new file mode 100644 index 0000000..a6616e8 --- /dev/null +++ b/sim/testsuite/sim/sh/pshli.s @@ -0,0 +1,119 @@ +# sh testcase for pshl +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + +pshl_imm: ! shift logical, immediate operand + set_grs_a5a5 + lds r0, a0 + pcopy a0, a1 + lds r0, x0 + lds r0, x1 + lds r0, y0 + lds r0, y1 + pcopy x0, m0 + pcopy y1, m1 + + set_sreg 0x10000, a0 + pshl #0, a0 + assert_sreg 0x10000, a0 + pshl #-0, a0 + assert_sreg 0x10000, a0 + + pshl #1, a0 + assert_sreg 0x20000, a0 + pshl #-1, a0 + assert_sreg 0x10000, a0 + + pshl #2, a0 + assert_sreg 0x40000, a0 + pshl #-2, a0 + assert_sreg 0x10000, a0 + + pshl #3, a0 + assert_sreg 0x80000, a0 + pshl #-3, a0 + assert_sreg 0x10000, a0 + + pshl #4, a0 + assert_sreg 0x100000, a0 + pshl #-4, a0 + assert_sreg 0x10000, a0 + + pshl #5, a0 + assert_sreg 0x200000, a0 + pshl #-5, a0 + assert_sreg 0x10000, a0 + + pshl #6, a0 + assert_sreg 0x400000, a0 + pshl #-6, a0 + assert_sreg 0x10000, a0 + + pshl #7, a0 + assert_sreg 0x800000, a0 + pshl #-7, a0 + assert_sreg 0x10000, a0 + + pshl #8, a0 + assert_sreg 0x1000000, a0 + pshl #-8, a0 + assert_sreg 0x10000, a0 + + pshl #9, a0 + assert_sreg 0x2000000, a0 + pshl #-9, a0 + assert_sreg 0x10000, a0 + + pshl #10, a0 + assert_sreg 0x4000000, a0 + pshl #-10, a0 + assert_sreg 0x10000, a0 + + pshl #11, a0 + assert_sreg 0x8000000, a0 + pshl #-11, a0 + assert_sreg 0x10000, a0 + + pshl #12, a0 + assert_sreg 0x10000000, a0 + pshl #-12, a0 + assert_sreg 0x10000, a0 + + pshl #13, a0 + assert_sreg 0x20000000, a0 + pshl #-13, a0 + assert_sreg 0x10000, a0 + + pshl #14, a0 + assert_sreg 0x40000000, a0 + pshl #-14, a0 + assert_sreg 0x10000, a0 + + pshl #15, a0 + assert_sreg 0x80000000, a0 + pshl #-15, a0 + assert_sreg 0x10000, a0 + + pshl #16, a0 + assert_sreg 0x00000000, a0 + pshl #-16, a0 + assert_sreg 0x0, a0 + + test_grs_a5a5 + assert_sreg2 0xa5a5a5a5, a1 + assert_sreg 0xa5a5a5a5, x0 + assert_sreg 0xa5a5a5a5, x1 + assert_sreg 0xa5a5a5a5, y0 + assert_sreg 0xa5a5a5a5, y1 + assert_sreg2 0xa5a5a5a5, m0 + assert_sreg2 0xa5a5a5a5, m1 + + + pass + exit 0 + diff --git a/sim/testsuite/sim/sh/pshlr.s b/sim/testsuite/sim/sh/pshlr.s new file mode 100644 index 0000000..36cb47f --- /dev/null +++ b/sim/testsuite/sim/sh/pshlr.s @@ -0,0 +1,152 @@ +# sh testcase for pshl +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + +pshl_reg: ! shift arithmetic, register operand + set_grs_a5a5 + lds r0, a0 + pcopy a0, a1 + lds r0, x0 + lds r0, x1 + lds r0, y0 + lds r0, y1 + pcopy x0, m0 + pcopy y1, m1 + + set_sreg 0x10000, x0 + set_sreg 0x0, y0 + pshl x0, y0, x0 + assert_sreg 0x10000, x0 + pneg y0, y0 + pshl x0, y0, x0 + assert_sreg 0x10000, x0 + + set_sreg 0x10000, y0 + pshl x0, y0, x0 + assert_sreg 0x20000, x0 + pneg y0, y0 + pshl x0, y0, x0 + assert_sreg 0x10000, x0 + + set_sreg 0x20000, y0 + pshl x0, y0, x0 + assert_sreg 0x40000, x0 + pneg y0, y0 + pshl x0, y0, x0 + assert_sreg 0x10000, x0 + + set_sreg 0x30000, y0 + pshl x0, y0, x0 + assert_sreg 0x80000, x0 + pneg y0, y0 + pshl x0, y0, x0 + assert_sreg 0x10000, x0 + + set_sreg 0x40000, y0 + pshl x0, y0, x0 + assert_sreg 0x100000, x0 + pneg y0, y0 + pshl x0, y0, x0 + assert_sreg 0x10000, x0 + + set_sreg 0x50000, y0 + pshl x0, y0, x0 + assert_sreg 0x200000, x0 + pneg y0, y0 + pshl x0, y0, x0 + assert_sreg 0x10000, x0 + + set_sreg 0x60000, y0 + pshl x0, y0, x0 + assert_sreg 0x400000, x0 + pneg y0, y0 + pshl x0, y0, x0 + assert_sreg 0x10000, x0 + + set_sreg 0x70000, y0 + pshl x0, y0, x0 + assert_sreg 0x800000, x0 + pneg y0, y0 + pshl x0, y0, x0 + assert_sreg 0x10000, x0 + + set_sreg 0x80000, y0 + pshl x0, y0, x0 + assert_sreg 0x1000000, x0 + pneg y0, y0 + pshl x0, y0, x0 + assert_sreg 0x10000, x0 + + set_sreg 0x90000, y0 + pshl x0, y0, x0 + assert_sreg 0x2000000, x0 + pneg y0, y0 + pshl x0, y0, x0 + assert_sreg 0x10000, x0 + + set_sreg 0xa0000, y0 + pshl x0, y0, x0 + assert_sreg 0x4000000, x0 + pneg y0, y0 + pshl x0, y0, x0 + assert_sreg 0x10000, x0 + + set_sreg 0xb0000, y0 + pshl x0, y0, x0 + assert_sreg 0x8000000, x0 + pneg y0, y0 + pshl x0, y0, x0 + assert_sreg 0x10000, x0 + + set_sreg 0xc0000, y0 + pshl x0, y0, x0 + assert_sreg 0x10000000, x0 + pneg y0, y0 + pshl x0, y0, x0 + assert_sreg 0x10000, x0 + + set_sreg 0xd0000, y0 + pshl x0, y0, x0 + assert_sreg 0x20000000, x0 + pneg y0, y0 + pshl x0, y0, x0 + assert_sreg 0x10000, x0 + + set_sreg 0xe0000, y0 + pshl x0, y0, x0 + assert_sreg 0x40000000, x0 + pneg y0, y0 + pshl x0, y0, x0 + assert_sreg 0x10000, x0 + + set_sreg 0xf0000, y0 + pshl x0, y0, x0 + assert_sreg 0x80000000, x0 + pneg y0, y0 + pshl x0, y0, x0 + assert_sreg 0x10000, x0 + + set_sreg 0x100000, y0 + pshl x0, y0, x0 + assert_sreg 0x00000000, x0 + pneg y0, y0 + pshl x0, y0, x0 + assert_sreg 0x0, x0 + + test_grs_a5a5 + assert_sreg2 0xa5a5a5a5, a0 + assert_sreg2 0xa5a5a5a5, a1 + assert_sreg 0xa5a5a5a5, x1 + assert_sreg 0xa5a5a5a5, y1 + assert_sreg2 0xa5a5a5a5, m0 + assert_sreg2 0xa5a5a5a5, m1 + + + pass + exit 0 + diff --git a/sim/testsuite/sim/sh/shll.s b/sim/testsuite/sim/sh/shll.s new file mode 100644 index 0000000..ec2ea12 --- /dev/null +++ b/sim/testsuite/sim/sh/shll.s @@ -0,0 +1,91 @@ +# sh testcase for shll +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + +shll: + set_grs_a5a5 + mov #1, r1 + shll r1 + assertreg 2, r1 + shll r1 + assertreg 4, r1 + shll r1 + assertreg 8, r1 + shll r1 + assertreg 16, r1 + shll r1 + assertreg 32, r1 + shll r1 + assertreg 64, r1 + shll r1 + assertreg 0x80, r1 + shll r1 + assertreg 0x100, r1 + shll r1 + assertreg 0x200, r1 + shll r1 + assertreg 0x400, r1 + shll r1 + assertreg 0x800, r1 + shll r1 + assertreg 0x1000, r1 + shll r1 + assertreg 0x2000, r1 + shll r1 + assertreg 0x4000, r1 + shll r1 + assertreg 0x8000, r1 + shll r1 + assertreg 0x10000, r1 + shll r1 + assertreg 0x20000, r1 + shll r1 + assertreg 0x40000, r1 + shll r1 + assertreg 0x80000, r1 + shll r1 + assertreg 0x100000, r1 + shll r1 + assertreg 0x200000, r1 + shll r1 + assertreg 0x400000, r1 + shll r1 + assertreg 0x800000, r1 + shll r1 + assertreg 0x1000000, r1 + shll r1 + assertreg 0x2000000, r1 + shll r1 + assertreg 0x4000000, r1 + shll r1 + assertreg 0x8000000, r1 + shll r1 + assertreg 0x10000000, r1 + shll r1 + assertreg 0x20000000, r1 + shll r1 + assertreg 0x40000000, r1 + shll r1 + assertreg 0x80000000, r1 + shll r1 + assertreg 0, r1 + shll r1 + assertreg 0, r1 + + # another: + mov #1, r1 + shll r1 + shll r1 + shll r1 + assertreg 8, r1 + + set_greg 0xa5a5a5a5, r1 + test_grs_a5a5 + + pass + exit 0 diff --git a/sim/testsuite/sim/sh/shll16.s b/sim/testsuite/sim/sh/shll16.s new file mode 100644 index 0000000..4574835 --- /dev/null +++ b/sim/testsuite/sim/sh/shll16.s @@ -0,0 +1,46 @@ +# sh testcase for shll16 +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + +shll16: + set_grs_a5a5 + mov #0x18, r1 + shll16 r1 + assertreg 0x180000, r1 + shll16 r1 + assertreg 0, r1 + + # another: + mov #1, r1 + shll16 r1 + mov #1, r7 + shll r7 + shll r7 + shll r7 + shll r7 + shll r7 + shll r7 + shll r7 + shll r7 + shll r7 + shll r7 + shll r7 + shll r7 + shll r7 + shll r7 + shll r7 + shll r7 + cmp/eq r1, r7 + bt okay + fail +okay: + set_greg 0xa5a5a5a5, r1 + set_greg 0xa5a5a5a5, r7 + test_grs_a5a5 + pass + exit 0 diff --git a/sim/testsuite/sim/sh/shll2.s b/sim/testsuite/sim/sh/shll2.s new file mode 100644 index 0000000..01a784c --- /dev/null +++ b/sim/testsuite/sim/sh/shll2.s @@ -0,0 +1,51 @@ +# sh testcase for shll2 +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + +shll2: + set_grs_a5a5 + mov #1, r1 + shll2 r1 + assertreg 4, r1 + shll2 r1 + assertreg 16, r1 + shll2 r1 + assertreg 64, r1 + shll2 r1 + assertreg 0x100, r1 + shll2 r1 + assertreg 0x400, r1 + shll2 r1 + assertreg 0x1000, r1 + shll2 r1 + assertreg 0x4000, r1 + shll2 r1 + assertreg 0x10000, r1 + shll2 r1 + assertreg 0x40000, r1 + shll2 r1 + assertreg 0x100000, r1 + shll2 r1 + assertreg 0x400000, r1 + shll2 r1 + assertreg 0x1000000, r1 + shll2 r1 + assertreg 0x4000000, r1 + shll2 r1 + assertreg 0x10000000, r1 + shll2 r1 + assertreg 0x40000000, r1 + shll2 r1 + assertreg 0, r1 + + set_greg 0xa5a5a5a5, r1 + test_grs_a5a5 + + pass + exit 0 + diff --git a/sim/testsuite/sim/sh/shll8.s b/sim/testsuite/sim/sh/shll8.s new file mode 100644 index 0000000..71e241d --- /dev/null +++ b/sim/testsuite/sim/sh/shll8.s @@ -0,0 +1,42 @@ +# sh testcase for shll8 +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + +shll8: + set_grs_a5a5 + mov #1, r1 + shll8 r1 + assertreg 0x100, r1 + shll8 r1 + assertreg 0x10000, r1 + shll8 r1 + assertreg 0x1000000, r1 + shll8 r1 + assertreg 0, r1 + + # another: + mov #1, r1 + shll8 r1 + mov #1, r2 + shll r2 + shll r2 + shll r2 + shll r2 + shll r2 + shll r2 + shll r2 + shll r2 + cmp/eq r1, r2 + bt okay + fail +okay: + set_greg 0xa5a5a5a5, r1 + set_greg 0xa5a5a5a5, r2 + test_grs_a5a5 + pass + exit 0 diff --git a/sim/testsuite/sim/sh/shlr.s b/sim/testsuite/sim/sh/shlr.s new file mode 100644 index 0000000..8755afb --- /dev/null +++ b/sim/testsuite/sim/sh/shlr.s @@ -0,0 +1,42 @@ +# sh testcase for shlr +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + +shlr: + set_grs_a5a5 + mov #0, r0 + or #192, r0 + shlr r0 + assertreg0 96 + shlr r0 + assertreg0 48 + shlr r0 + assertreg0 24 + shlr r0 + assertreg0 12 + shlr r0 + assertreg0 6 + shlr r0 + assertreg0 3 + + # Make sure a bit is shifted into T. + shlr r0 + bf wrong + assertreg0 1 + # Ditto. + shlr r0 + bf wrong + assertreg0 0 + + set_greg 0xa5a5a5a5, r0 + test_grs_a5a5 + pass + exit 0 + +wrong: + fail diff --git a/sim/testsuite/sim/sh/shlr16.s b/sim/testsuite/sim/sh/shlr16.s new file mode 100644 index 0000000..1161c66 --- /dev/null +++ b/sim/testsuite/sim/sh/shlr16.s @@ -0,0 +1,20 @@ +# sh testcase for shlr16 +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + +shrl16: + set_grs_a5a5 + shlr16 r0 + assertreg0 0xa5a5 + shlr16 r0 + assertreg0 0 + + set_greg 0xa5a5a5a5, r0 + test_grs_a5a5 + pass + exit 0 diff --git a/sim/testsuite/sim/sh/shlr2.s b/sim/testsuite/sim/sh/shlr2.s new file mode 100644 index 0000000..ce554dd --- /dev/null +++ b/sim/testsuite/sim/sh/shlr2.s @@ -0,0 +1,48 @@ +# sh testcase for shlr2 +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + +shrl2: + set_grs_a5a5 + shlr2 r0 + assertreg0 0x29696969 + shlr2 r0 + assertreg0 0x0a5a5a5a + shlr2 r0 + assertreg0 0x02969696 + shlr2 r0 + assertreg0 0x00a5a5a5 + shlr2 r0 + assertreg0 0x00296969 + shlr2 r0 + assertreg0 0x000a5a5a + shlr2 r0 + assertreg0 0x00029696 + shlr2 r0 + assertreg0 0x0000a5a5 + shlr2 r0 + assertreg0 0x00002969 + shlr2 r0 + assertreg0 0x00000a5a + shlr2 r0 + assertreg0 0x00000296 + shlr2 r0 + assertreg0 0x000000a5 + shlr2 r0 + assertreg0 0x00000029 + shlr2 r0 + assertreg0 0x0000000a + shlr2 r0 + assertreg0 0x00000002 + shlr2 r0 + assertreg0 0 + + set_greg 0xa5a5a5a5 r0 + test_grs_a5a5 + pass + exit 0 diff --git a/sim/testsuite/sim/sh/shlr8.s b/sim/testsuite/sim/sh/shlr8.s new file mode 100644 index 0000000..d609af1 --- /dev/null +++ b/sim/testsuite/sim/sh/shlr8.s @@ -0,0 +1,24 @@ +# sh testcase for shlr8 +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + +shrl8: + set_grs_a5a5 + shlr8 r0 + assertreg0 0xa5a5a5 + shlr8 r0 + assertreg0 0xa5a5 + shlr8 r0 + assertreg0 0xa5 + shlr8 r0 + assertreg0 0x0 + + set_greg 0xa5a5a5a5, r0 + test_grs_a5a5 + pass + exit 0 diff --git a/sim/testsuite/sim/sh/swap.s b/sim/testsuite/sim/sh/swap.s new file mode 100644 index 0000000..4dd6572 --- /dev/null +++ b/sim/testsuite/sim/sh/swap.s @@ -0,0 +1,59 @@ +# sh testcase for swap +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + +swapb: + set_grs_a5a5 + mov #0x5a, r0 + shll8 r0 + or #0xa5, r0 + assertreg0 0x5aa5 + + swap.b r0, r1 + assertreg 0xa55a, r1 + + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + +swapw: + set_grs_a5a5 + mov #0x5a, r0 + shll16 r0 + or #0xa5, r0 + assertreg0 0x5a00a5 + + swap.w r0, r1 + assertreg 0xa5005a, r1 + + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + + pass + exit 0 diff --git a/sim/testsuite/sim/sh/testutils.inc b/sim/testsuite/sim/sh/testutils.inc new file mode 100644 index 0000000..5c547f2 --- /dev/null +++ b/sim/testsuite/sim/sh/testutils.inc @@ -0,0 +1,588 @@ +# Support macros for the sh assembly test cases. + + .equ no_dsp, 0 + .equ yes_dsp, 1 + + .section .rodata + .align 2 +_pass: .string "pass\n" +_fail: .string "fail\n" +_stack: .fill 128, 4, 0 +stackt: + + .macro push reg + mov.l \reg, @-r15 + .endm + + .macro pop reg + mov.l @r15+, \reg + .endm + + .macro start + .text + .align 1 + .global start +start: mov.l stackp, r15 + bra main + nop + .align 2 +stackp: .long stackt +mpass: + mov #4, r4 + mov #1, r5 + mov.l ppass, r6 + mov #5, r7 + trapa #34 + rts + nop +mfail: + mov #4, r4 + mov #1, r5 + mov.l pfail, r6 + mov #5, r7 + trapa #34 + mov #1, r5 +mexit: + mov #1, r4 + mov #0, r6 + mov #0, r7 + trapa #34 + .align 2 +ppass: .long _pass +pfail: .long _fail + +mtesta5: + push r0 + mov.l a5a5, r0 + cmp/eq r1, r0 + bf mfail + cmp/eq r2, r0 + bf mfail + cmp/eq r3, r0 + bf mfail + cmp/eq r4, r0 + bf mfail + cmp/eq r5, r0 + bf mfail + cmp/eq r6, r0 + bf mfail + cmp/eq r7, r0 + bf mfail + cmp/eq r8, r0 + bf mfail + cmp/eq r9, r0 + bf mfail + cmp/eq r10, r0 + bf mfail + cmp/eq r11, r0 + bf mfail + cmp/eq r12, r0 + bf mfail + cmp/eq r13, r0 + bf mfail + cmp/eq r14, r0 + bf mfail + # restore and check r0 + pop r0 + cmp/eq r0, r1 + bf mfail + # pass + rts + nop +.if (sim_cpu == no_dsp) +mtesta5_fp: + push r0 + flds fr0, fpul + sts fpul, r0 + push r0 + mov.l a5a5, r0 + lds r0, fpul + fsts fpul, fr0 + fcmp/eq fr1, fr0 + bf mfail + fcmp/eq fr2, fr0 + bf mfail + fcmp/eq fr3, fr0 + bf mfail + fcmp/eq fr4, fr0 + bf mfail + fcmp/eq fr5, fr0 + bf mfail + fcmp/eq fr6, fr0 + bf mfail + fcmp/eq fr7, fr0 + bf mfail + fcmp/eq fr8, fr0 + bf mfail + fcmp/eq fr9, fr0 + bf mfail + fcmp/eq fr10, fr0 + bf mfail + fcmp/eq fr11, fr0 + bf mfail + fcmp/eq fr12, fr0 + bf mfail + fcmp/eq fr13, fr0 + bf mfail + fcmp/eq fr14, fr0 + bf mfail + fcmp/eq fr15, fr0 + bf mfail + # restore and check fr0 + pop r0 + lds r0, fpul + fsts fpul, fr0 + fcmp/eq fr0, fr1 + bf mfail + # restore r0 and pass + pop r0 + rts + nop +.endif + +mseta5: + mov.l a5a5, r0 + mov.l a5a5, r1 + mov.l a5a5, r2 + mov.l a5a5, r3 + mov.l a5a5, r4 + mov.l a5a5, r5 + mov.l a5a5, r6 + mov.l a5a5, r7 + mov.l a5a5, r8 + mov.l a5a5, r9 + mov.l a5a5, r10 + mov.l a5a5, r11 + mov.l a5a5, r12 + mov.l a5a5, r13 + mov.l a5a5, r14 + rts + nop + +.if (sim_cpu == no_dsp) +mseta5_fp: + push r0 + mov.l a5a5, r0 + lds r0, fpul + fsts fpul, fr0 + fsts fpul, fr1 + fsts fpul, fr2 + fsts fpul, fr3 + fsts fpul, fr4 + fsts fpul, fr5 + fsts fpul, fr6 + fsts fpul, fr7 + fsts fpul, fr8 + fsts fpul, fr9 + fsts fpul, fr10 + fsts fpul, fr11 + fsts fpul, fr12 + fsts fpul, fr13 + fsts fpul, fr14 + fsts fpul, fr15 + pop r0 + rts + nop +.endif + + .align 2 +a5a5: .long 0xa5a5a5a5 +main: + .endm + + .macro exit val + mov #\val, r5 + bra mexit + nop + .endm + + .macro pass + bsr mpass + nop + .endm + + .macro fail + bra mfail + nop + .endm + + # Assert value of register (any general register but r0) + # Preserves r0 on stack, restores it on success. + .macro assertreg val reg + push r0 + mov.l .Larval\@, r0 + cmp/eq r0, \reg + bt .Lar\@ + fail + .align 2 +.Larval\@: + .long \val +.Lar\@: pop r0 + .endm + + # Assert value of register zero + # Preserves r1 on stack, restores it on success. + .macro assertreg0 val + push r1 + mov.l .Lazval\@, r1 + cmp/eq r1, r0 + bt .Laz\@ + fail + .align 2 +.Lazval\@: + .long \val +.Laz\@: pop r1 + .endm + + # Assert value of system register + # [mach, macl, pr, dsr, a0, x0, x1, y0, y1, ...] + .macro assert_sreg val reg + push r0 + sts \reg, r0 + assertreg0 \val + pop r0 + .endm + + # Assert value of system register that isn't directly stc-able + # [a1, m0, m1, ...] + .macro assert_sreg2 val reg + push r0 + sts a0, r0 + push r0 + pcopy \reg, a0 + sts a0, r0 + assertreg0 \val + pop r0 + lds r0, a0 + pop r0 + .endm + + # Assert value of control register + # [gbr, vbr, ssr, spc, sgr, dbr, r[0-7]_bank, sr, mod, re, rs, ...] + .macro assert_creg val reg + push r0 + stc \reg, r0 + assertreg0 \val + pop r0 + .endm + + # Assert integer value of fp register + # Preserves r0 on stack, restores it on success + # Assumes single-precision fp mode + .macro assert_fpreg_i val freg + push r0 + ftrc \freg, fpul + sts fpul, r0 + assertreg0 \val + pop r0 + .endm + + # Assert integer value of dp register + # Preserves r0 on stack, restores it on success + # Assumes double-precision fp mode + .macro assert_dpreg_i val dreg + push r0 + ftrc \dreg, fpul + sts fpul, r0 + assertreg0 \val + pop r0 + .endm + + # Assert hex value of fp register + # Preserves r0 on stack, restores it on success + # Assumes single-precision fp mode + .macro assert_fpreg_x val freg + push r0 + flds \freg, fpul + sts fpul, r0 + assertreg0 \val + pop r0 + .endm + + # Set FP bank 0 + # Saves and restores r0 and r1 + .macro bank0 + push r0 + push r1 + mov #32, r1 + shll16 r1 + not r1, r1 + sts fpscr, r0 + and r1, r0 + lds r0, fpscr + pop r1 + pop r0 + .endm + + # Set FP bank 1 + .macro bank1 + push r0 + push r1 + mov #32, r1 + shll16 r1 + sts fpscr, r0 + or r1, r0 + lds r0, fpscr + pop r1 + pop r0 + .endm + + # Set FP 32-bit xfer + .macro sz_32 + push r0 + push r1 + mov #16, r1 + shll16 r1 + not r1, r1 + sts fpscr, r0 + and r1, r0 + lds r0, fpscr + pop r1 + pop r0 + .endm + + # Set FP 64-bit xfer + .macro sz_64 + push r0 + push r1 + mov #16, r1 + shll16 r1 + sts fpscr, r0 + or r1, r0 + lds r0, fpscr + pop r1 + pop r0 + .endm + + # Set FP single precision + .macro single_prec + push r0 + push r1 + mov #8, r1 + shll16 r1 + not r1, r1 + sts fpscr, r0 + and r1, r0 + lds r0, fpscr + pop r1 + pop r0 + .endm + + # Set FP double precision + .macro double_prec + push r0 + push r1 + mov #8, r1 + shll16 r1 + sts fpscr, r0 + or r1, r0 + lds r0, fpscr + pop r1 + pop r0 + .endm + + .macro set_carry + sett + .endm + + .macro set_ovf + sett + .endm + + .macro clear_carry + clrt + .endm + + .macro clear_ovf + clrt + .endm + + # sets, clrs + + + .macro set_grs_a5a5 + bsr mseta5 + nop + .endm + + .macro set_greg val greg + mov.l gregval\@, \greg + bra set_greg\@ + nop + .align 2 +gregval\@: .long \val +set_greg\@: + .endm + + .macro set_fprs_a5a5 + bsr mseta5_fp + nop + .endm + + .macro test_grs_a5a5 + bsr mtesta5 + nop + .endm + + .macro test_fprs_a5a5 + bsr mtesta5_fp + nop + .endm + + .macro test_gr_a5a5 reg + assertreg 0xa5a5a5a5 \reg + .endm + + .macro test_fpr_a5a5 reg + assert_fpreg_x 0xa5a5a5a5 \reg + .endm + + .macro test_gr0_a5a5 + assertreg0 0xa5a5a5a5 + .endm + + # Perform a single to double precision floating point conversion. + # Assumes correct settings of fpscr. + .macro _s2d fpr dpr + flds \fpr, fpul + fcnvsd fpul, \dpr + .endm + + # Manipulate the status register + .macro set_sr val + push r0 + mov.l .Lsrval\@, r0 + ldc r0, sr + pop r0 + bra .Lsetsr\@ + nop + .align 2 +.Lsrval\@: + .long \val +.Lsetsr\@: + .endm + + .macro get_sr reg + stc sr, \reg + .endm + + .macro test_sr val + push r0 + get_sr r0 + assertreg0 \val + pop r0 + .endm + + .macro set_sr_bit + push r0 + push r1 + get_sr r0 + mov.l .Lsrbitval\@, r1 + or r1, r0 + ldc r0, sr + pop r1 + pop r0 + bra .Lsrbit\@ + nop + .align 2 +.Lsrbitval: + .long \val +.Lsrbit: + .endm + + .macro test_sr_bit_set val + push r0 + push r1 + get_sr r0 + mov.l .Ltsbsval\@, r1 + tst r1, r0 + bf .Ltsbs\@ + fail + .align 2 +.Ltsbsval\@: + .long \val +.Ltsbs\@: + pop r1 + pop r0 + .endm + + .macro test_sr_bit_clear val + push r0 + push r1 + get_sr r0 + mov.l .Ltsbcval\@, r1 + not r0, r0 + tst r1, r0 + bf .Ltsbc\@ + fail + .align 2 +.Ltsbcval\@: + .long \val +.Ltsbc\@: + pop r1 + pop r0 + .endm + + # Set system registers + .macro set_sreg val reg + # [mach, macl, pr, dsr, a0, x0, x1, y0, y1, ...] + push r0 + mov.l .Lssrval\@, r0 + lds r0, \reg + pop r0 + bra .Lssr\@ + nop +.Lssrval\@: + .long \val +.Lssr\@: + .endm + + .macro set_sreg2 val reg + # [a1, m0, m1, ...] + push r0 + sts a0, r0 + push r0 + mov.l .Lssr2val\@, r0 + lds r0, a0 + pcopy a0, \reg + pop r0 + lds r0, a0 + pop r0 + bra .Lssr2_\@ + nop +.Lssr2val\@: + .long \val +.Lssr2_\@: + .endm + + + .macro set_creg val reg + # + push r0 + mov.l .Lscrval\@, r0 + ldc r0, \reg + pop r0 + bra .Lscr\@ + nop +.Lscrval\@: + .long \val +.Lscr\@: + .endm + + .macro set_dctrue + push r0 + sts dsr, r0 + or #1, r0 + lds r0, dsr + pop r0 + .endm + + .macro set_dcfalse + push r0 + sts dsr, r0 + not r0, r0 + or #1, r0 + not r0, r0 + lds r0, dsr + pop r0 + .endm -- cgit v1.1